Bug Summary

File:llvm/lib/CodeGen/MachineInstr.cpp
Warning:line 1819, column 7
Value stored to 'HaveSemi' is never read

Annotated Source Code

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clang -cc1 -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name MachineInstr.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mframe-pointer=none -fmath-errno -fno-rounding-math -mconstructor-aliases -munwind-tables -target-cpu x86-64 -tune-cpu generic -fno-split-dwarf-inlining -debugger-tuning=gdb -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-12/lib/clang/12.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/build-llvm/lib/CodeGen -I /build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen -I /build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/build-llvm/include -I /build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0/backward -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-12/lib/clang/12.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++14 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/build-llvm/lib/CodeGen -fdebug-prefix-map=/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b=. -ferror-limit 19 -fvisibility-inlines-hidden -stack-protector 2 -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -o /tmp/scan-build-2020-09-17-195756-12974-1 -x c++ /build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/MachineInstr.cpp
1//===- lib/CodeGen/MachineInstr.cpp ---------------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// Methods common to all machine instructions.
10//
11//===----------------------------------------------------------------------===//
12
13#include "llvm/CodeGen/MachineInstr.h"
14#include "llvm/ADT/APFloat.h"
15#include "llvm/ADT/ArrayRef.h"
16#include "llvm/ADT/FoldingSet.h"
17#include "llvm/ADT/Hashing.h"
18#include "llvm/ADT/None.h"
19#include "llvm/ADT/STLExtras.h"
20#include "llvm/ADT/SmallBitVector.h"
21#include "llvm/ADT/SmallString.h"
22#include "llvm/ADT/SmallVector.h"
23#include "llvm/Analysis/AliasAnalysis.h"
24#include "llvm/Analysis/Loads.h"
25#include "llvm/Analysis/MemoryLocation.h"
26#include "llvm/CodeGen/GlobalISel/RegisterBank.h"
27#include "llvm/CodeGen/MachineBasicBlock.h"
28#include "llvm/CodeGen/MachineFrameInfo.h"
29#include "llvm/CodeGen/MachineFunction.h"
30#include "llvm/CodeGen/MachineInstrBuilder.h"
31#include "llvm/CodeGen/MachineInstrBundle.h"
32#include "llvm/CodeGen/MachineMemOperand.h"
33#include "llvm/CodeGen/MachineModuleInfo.h"
34#include "llvm/CodeGen/MachineOperand.h"
35#include "llvm/CodeGen/MachineRegisterInfo.h"
36#include "llvm/CodeGen/PseudoSourceValue.h"
37#include "llvm/CodeGen/TargetInstrInfo.h"
38#include "llvm/CodeGen/TargetRegisterInfo.h"
39#include "llvm/CodeGen/TargetSubtargetInfo.h"
40#include "llvm/Config/llvm-config.h"
41#include "llvm/IR/Constants.h"
42#include "llvm/IR/DebugInfoMetadata.h"
43#include "llvm/IR/DebugLoc.h"
44#include "llvm/IR/DerivedTypes.h"
45#include "llvm/IR/Function.h"
46#include "llvm/IR/InlineAsm.h"
47#include "llvm/IR/InstrTypes.h"
48#include "llvm/IR/Intrinsics.h"
49#include "llvm/IR/LLVMContext.h"
50#include "llvm/IR/Metadata.h"
51#include "llvm/IR/Module.h"
52#include "llvm/IR/ModuleSlotTracker.h"
53#include "llvm/IR/Operator.h"
54#include "llvm/IR/Type.h"
55#include "llvm/IR/Value.h"
56#include "llvm/MC/MCInstrDesc.h"
57#include "llvm/MC/MCRegisterInfo.h"
58#include "llvm/MC/MCSymbol.h"
59#include "llvm/Support/Casting.h"
60#include "llvm/Support/CommandLine.h"
61#include "llvm/Support/Compiler.h"
62#include "llvm/Support/Debug.h"
63#include "llvm/Support/ErrorHandling.h"
64#include "llvm/Support/FormattedStream.h"
65#include "llvm/Support/LowLevelTypeImpl.h"
66#include "llvm/Support/MathExtras.h"
67#include "llvm/Support/raw_ostream.h"
68#include "llvm/Target/TargetIntrinsicInfo.h"
69#include "llvm/Target/TargetMachine.h"
70#include <algorithm>
71#include <cassert>
72#include <cstddef>
73#include <cstdint>
74#include <cstring>
75#include <iterator>
76#include <utility>
77
78using namespace llvm;
79
80static const MachineFunction *getMFIfAvailable(const MachineInstr &MI) {
81 if (const MachineBasicBlock *MBB = MI.getParent())
82 if (const MachineFunction *MF = MBB->getParent())
83 return MF;
84 return nullptr;
85}
86
87// Try to crawl up to the machine function and get TRI and IntrinsicInfo from
88// it.
89static void tryToGetTargetInfo(const MachineInstr &MI,
90 const TargetRegisterInfo *&TRI,
91 const MachineRegisterInfo *&MRI,
92 const TargetIntrinsicInfo *&IntrinsicInfo,
93 const TargetInstrInfo *&TII) {
94
95 if (const MachineFunction *MF = getMFIfAvailable(MI)) {
96 TRI = MF->getSubtarget().getRegisterInfo();
97 MRI = &MF->getRegInfo();
98 IntrinsicInfo = MF->getTarget().getIntrinsicInfo();
99 TII = MF->getSubtarget().getInstrInfo();
100 }
101}
102
103void MachineInstr::addImplicitDefUseOperands(MachineFunction &MF) {
104 if (MCID->ImplicitDefs)
105 for (const MCPhysReg *ImpDefs = MCID->getImplicitDefs(); *ImpDefs;
106 ++ImpDefs)
107 addOperand(MF, MachineOperand::CreateReg(*ImpDefs, true, true));
108 if (MCID->ImplicitUses)
109 for (const MCPhysReg *ImpUses = MCID->getImplicitUses(); *ImpUses;
110 ++ImpUses)
111 addOperand(MF, MachineOperand::CreateReg(*ImpUses, false, true));
112}
113
114/// MachineInstr ctor - This constructor creates a MachineInstr and adds the
115/// implicit operands. It reserves space for the number of operands specified by
116/// the MCInstrDesc.
117MachineInstr::MachineInstr(MachineFunction &MF, const MCInstrDesc &tid,
118 DebugLoc dl, bool NoImp)
119 : MCID(&tid), debugLoc(std::move(dl)), DebugInstrNum(0) {
120 assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor")((debugLoc.hasTrivialDestructor() && "Expected trivial destructor"
) ? static_cast<void> (0) : __assert_fail ("debugLoc.hasTrivialDestructor() && \"Expected trivial destructor\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/MachineInstr.cpp"
, 120, __PRETTY_FUNCTION__))
;
121
122 // Reserve space for the expected number of operands.
123 if (unsigned NumOps = MCID->getNumOperands() +
124 MCID->getNumImplicitDefs() + MCID->getNumImplicitUses()) {
125 CapOperands = OperandCapacity::get(NumOps);
126 Operands = MF.allocateOperandArray(CapOperands);
127 }
128
129 if (!NoImp)
130 addImplicitDefUseOperands(MF);
131}
132
133/// MachineInstr ctor - Copies MachineInstr arg exactly.
134/// Does not copy the number from debug instruction numbering, to preserve
135/// uniqueness.
136MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
137 : MCID(&MI.getDesc()), Info(MI.Info), debugLoc(MI.getDebugLoc()),
138 DebugInstrNum(0) {
139 assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor")((debugLoc.hasTrivialDestructor() && "Expected trivial destructor"
) ? static_cast<void> (0) : __assert_fail ("debugLoc.hasTrivialDestructor() && \"Expected trivial destructor\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/MachineInstr.cpp"
, 139, __PRETTY_FUNCTION__))
;
140
141 CapOperands = OperandCapacity::get(MI.getNumOperands());
142 Operands = MF.allocateOperandArray(CapOperands);
143
144 // Copy operands.
145 for (const MachineOperand &MO : MI.operands())
146 addOperand(MF, MO);
147
148 // Copy all the sensible flags.
149 setFlags(MI.Flags);
150}
151
152void MachineInstr::moveBefore(MachineInstr *MovePos) {
153 MovePos->getParent()->splice(MovePos, getParent(), getIterator());
154}
155
156/// getRegInfo - If this instruction is embedded into a MachineFunction,
157/// return the MachineRegisterInfo object for the current function, otherwise
158/// return null.
159MachineRegisterInfo *MachineInstr::getRegInfo() {
160 if (MachineBasicBlock *MBB = getParent())
161 return &MBB->getParent()->getRegInfo();
162 return nullptr;
163}
164
165/// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
166/// this instruction from their respective use lists. This requires that the
167/// operands already be on their use lists.
168void MachineInstr::RemoveRegOperandsFromUseLists(MachineRegisterInfo &MRI) {
169 for (MachineOperand &MO : operands())
170 if (MO.isReg())
171 MRI.removeRegOperandFromUseList(&MO);
172}
173
174/// AddRegOperandsToUseLists - Add all of the register operands in
175/// this instruction from their respective use lists. This requires that the
176/// operands not be on their use lists yet.
177void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &MRI) {
178 for (MachineOperand &MO : operands())
179 if (MO.isReg())
180 MRI.addRegOperandToUseList(&MO);
181}
182
183void MachineInstr::addOperand(const MachineOperand &Op) {
184 MachineBasicBlock *MBB = getParent();
185 assert(MBB && "Use MachineInstrBuilder to add operands to dangling instrs")((MBB && "Use MachineInstrBuilder to add operands to dangling instrs"
) ? static_cast<void> (0) : __assert_fail ("MBB && \"Use MachineInstrBuilder to add operands to dangling instrs\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/MachineInstr.cpp"
, 185, __PRETTY_FUNCTION__))
;
186 MachineFunction *MF = MBB->getParent();
187 assert(MF && "Use MachineInstrBuilder to add operands to dangling instrs")((MF && "Use MachineInstrBuilder to add operands to dangling instrs"
) ? static_cast<void> (0) : __assert_fail ("MF && \"Use MachineInstrBuilder to add operands to dangling instrs\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/MachineInstr.cpp"
, 187, __PRETTY_FUNCTION__))
;
188 addOperand(*MF, Op);
189}
190
191/// Move NumOps MachineOperands from Src to Dst, with support for overlapping
192/// ranges. If MRI is non-null also update use-def chains.
193static void moveOperands(MachineOperand *Dst, MachineOperand *Src,
194 unsigned NumOps, MachineRegisterInfo *MRI) {
195 if (MRI)
196 return MRI->moveOperands(Dst, Src, NumOps);
197 // MachineOperand is a trivially copyable type so we can just use memmove.
198 assert(Dst && Src && "Unknown operands")((Dst && Src && "Unknown operands") ? static_cast
<void> (0) : __assert_fail ("Dst && Src && \"Unknown operands\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/MachineInstr.cpp"
, 198, __PRETTY_FUNCTION__))
;
199 std::memmove(Dst, Src, NumOps * sizeof(MachineOperand));
200}
201
202/// addOperand - Add the specified operand to the instruction. If it is an
203/// implicit operand, it is added to the end of the operand list. If it is
204/// an explicit operand it is added at the end of the explicit operand list
205/// (before the first implicit operand).
206void MachineInstr::addOperand(MachineFunction &MF, const MachineOperand &Op) {
207 assert(MCID && "Cannot add operands before providing an instr descriptor")((MCID && "Cannot add operands before providing an instr descriptor"
) ? static_cast<void> (0) : __assert_fail ("MCID && \"Cannot add operands before providing an instr descriptor\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/MachineInstr.cpp"
, 207, __PRETTY_FUNCTION__))
;
208
209 // Check if we're adding one of our existing operands.
210 if (&Op >= Operands && &Op < Operands + NumOperands) {
211 // This is unusual: MI->addOperand(MI->getOperand(i)).
212 // If adding Op requires reallocating or moving existing operands around,
213 // the Op reference could go stale. Support it by copying Op.
214 MachineOperand CopyOp(Op);
215 return addOperand(MF, CopyOp);
216 }
217
218 // Find the insert location for the new operand. Implicit registers go at
219 // the end, everything else goes before the implicit regs.
220 //
221 // FIXME: Allow mixed explicit and implicit operands on inline asm.
222 // InstrEmitter::EmitSpecialNode() is marking inline asm clobbers as
223 // implicit-defs, but they must not be moved around. See the FIXME in
224 // InstrEmitter.cpp.
225 unsigned OpNo = getNumOperands();
226 bool isImpReg = Op.isReg() && Op.isImplicit();
227 if (!isImpReg && !isInlineAsm()) {
228 while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) {
229 --OpNo;
230 assert(!Operands[OpNo].isTied() && "Cannot move tied operands")((!Operands[OpNo].isTied() && "Cannot move tied operands"
) ? static_cast<void> (0) : __assert_fail ("!Operands[OpNo].isTied() && \"Cannot move tied operands\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/MachineInstr.cpp"
, 230, __PRETTY_FUNCTION__))
;
231 }
232 }
233
234#ifndef NDEBUG
235 bool isDebugOp = Op.getType() == MachineOperand::MO_Metadata ||
236 Op.getType() == MachineOperand::MO_MCSymbol;
237 // OpNo now points as the desired insertion point. Unless this is a variadic
238 // instruction, only implicit regs are allowed beyond MCID->getNumOperands().
239 // RegMask operands go between the explicit and implicit operands.
240 assert((isImpReg || Op.isRegMask() || MCID->isVariadic() ||(((isImpReg || Op.isRegMask() || MCID->isVariadic() || OpNo
< MCID->getNumOperands() || isDebugOp) && "Trying to add an operand to a machine instr that is already done!"
) ? static_cast<void> (0) : __assert_fail ("(isImpReg || Op.isRegMask() || MCID->isVariadic() || OpNo < MCID->getNumOperands() || isDebugOp) && \"Trying to add an operand to a machine instr that is already done!\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/MachineInstr.cpp"
, 242, __PRETTY_FUNCTION__))
241 OpNo < MCID->getNumOperands() || isDebugOp) &&(((isImpReg || Op.isRegMask() || MCID->isVariadic() || OpNo
< MCID->getNumOperands() || isDebugOp) && "Trying to add an operand to a machine instr that is already done!"
) ? static_cast<void> (0) : __assert_fail ("(isImpReg || Op.isRegMask() || MCID->isVariadic() || OpNo < MCID->getNumOperands() || isDebugOp) && \"Trying to add an operand to a machine instr that is already done!\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/MachineInstr.cpp"
, 242, __PRETTY_FUNCTION__))
242 "Trying to add an operand to a machine instr that is already done!")(((isImpReg || Op.isRegMask() || MCID->isVariadic() || OpNo
< MCID->getNumOperands() || isDebugOp) && "Trying to add an operand to a machine instr that is already done!"
) ? static_cast<void> (0) : __assert_fail ("(isImpReg || Op.isRegMask() || MCID->isVariadic() || OpNo < MCID->getNumOperands() || isDebugOp) && \"Trying to add an operand to a machine instr that is already done!\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/MachineInstr.cpp"
, 242, __PRETTY_FUNCTION__))
;
243#endif
244
245 MachineRegisterInfo *MRI = getRegInfo();
246
247 // Determine if the Operands array needs to be reallocated.
248 // Save the old capacity and operand array.
249 OperandCapacity OldCap = CapOperands;
250 MachineOperand *OldOperands = Operands;
251 if (!OldOperands || OldCap.getSize() == getNumOperands()) {
252 CapOperands = OldOperands ? OldCap.getNext() : OldCap.get(1);
253 Operands = MF.allocateOperandArray(CapOperands);
254 // Move the operands before the insertion point.
255 if (OpNo)
256 moveOperands(Operands, OldOperands, OpNo, MRI);
257 }
258
259 // Move the operands following the insertion point.
260 if (OpNo != NumOperands)
261 moveOperands(Operands + OpNo + 1, OldOperands + OpNo, NumOperands - OpNo,
262 MRI);
263 ++NumOperands;
264
265 // Deallocate the old operand array.
266 if (OldOperands != Operands && OldOperands)
267 MF.deallocateOperandArray(OldCap, OldOperands);
268
269 // Copy Op into place. It still needs to be inserted into the MRI use lists.
270 MachineOperand *NewMO = new (Operands + OpNo) MachineOperand(Op);
271 NewMO->ParentMI = this;
272
273 // When adding a register operand, tell MRI about it.
274 if (NewMO->isReg()) {
275 // Ensure isOnRegUseList() returns false, regardless of Op's status.
276 NewMO->Contents.Reg.Prev = nullptr;
277 // Ignore existing ties. This is not a property that can be copied.
278 NewMO->TiedTo = 0;
279 // Add the new operand to MRI, but only for instructions in an MBB.
280 if (MRI)
281 MRI->addRegOperandToUseList(NewMO);
282 // The MCID operand information isn't accurate until we start adding
283 // explicit operands. The implicit operands are added first, then the
284 // explicits are inserted before them.
285 if (!isImpReg) {
286 // Tie uses to defs as indicated in MCInstrDesc.
287 if (NewMO->isUse()) {
288 int DefIdx = MCID->getOperandConstraint(OpNo, MCOI::TIED_TO);
289 if (DefIdx != -1)
290 tieOperands(DefIdx, OpNo);
291 }
292 // If the register operand is flagged as early, mark the operand as such.
293 if (MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1)
294 NewMO->setIsEarlyClobber(true);
295 }
296 }
297}
298
299/// RemoveOperand - Erase an operand from an instruction, leaving it with one
300/// fewer operand than it started with.
301///
302void MachineInstr::RemoveOperand(unsigned OpNo) {
303 assert(OpNo < getNumOperands() && "Invalid operand number")((OpNo < getNumOperands() && "Invalid operand number"
) ? static_cast<void> (0) : __assert_fail ("OpNo < getNumOperands() && \"Invalid operand number\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/MachineInstr.cpp"
, 303, __PRETTY_FUNCTION__))
;
304 untieRegOperand(OpNo);
305
306#ifndef NDEBUG
307 // Moving tied operands would break the ties.
308 for (unsigned i = OpNo + 1, e = getNumOperands(); i != e; ++i)
309 if (Operands[i].isReg())
310 assert(!Operands[i].isTied() && "Cannot move tied operands")((!Operands[i].isTied() && "Cannot move tied operands"
) ? static_cast<void> (0) : __assert_fail ("!Operands[i].isTied() && \"Cannot move tied operands\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/MachineInstr.cpp"
, 310, __PRETTY_FUNCTION__))
;
311#endif
312
313 MachineRegisterInfo *MRI = getRegInfo();
314 if (MRI && Operands[OpNo].isReg())
315 MRI->removeRegOperandFromUseList(Operands + OpNo);
316
317 // Don't call the MachineOperand destructor. A lot of this code depends on
318 // MachineOperand having a trivial destructor anyway, and adding a call here
319 // wouldn't make it 'destructor-correct'.
320
321 if (unsigned N = NumOperands - 1 - OpNo)
322 moveOperands(Operands + OpNo, Operands + OpNo + 1, N, MRI);
323 --NumOperands;
324}
325
326void MachineInstr::setExtraInfo(MachineFunction &MF,
327 ArrayRef<MachineMemOperand *> MMOs,
328 MCSymbol *PreInstrSymbol,
329 MCSymbol *PostInstrSymbol,
330 MDNode *HeapAllocMarker) {
331 bool HasPreInstrSymbol = PreInstrSymbol != nullptr;
332 bool HasPostInstrSymbol = PostInstrSymbol != nullptr;
333 bool HasHeapAllocMarker = HeapAllocMarker != nullptr;
334 int NumPointers =
335 MMOs.size() + HasPreInstrSymbol + HasPostInstrSymbol + HasHeapAllocMarker;
336
337 // Drop all extra info if there is none.
338 if (NumPointers <= 0) {
339 Info.clear();
340 return;
341 }
342
343 // If more than one pointer, then store out of line. Store heap alloc markers
344 // out of line because PointerSumType cannot hold more than 4 tag types with
345 // 32-bit pointers.
346 // FIXME: Maybe we should make the symbols in the extra info mutable?
347 else if (NumPointers > 1 || HasHeapAllocMarker) {
348 Info.set<EIIK_OutOfLine>(MF.createMIExtraInfo(
349 MMOs, PreInstrSymbol, PostInstrSymbol, HeapAllocMarker));
350 return;
351 }
352
353 // Otherwise store the single pointer inline.
354 if (HasPreInstrSymbol)
355 Info.set<EIIK_PreInstrSymbol>(PreInstrSymbol);
356 else if (HasPostInstrSymbol)
357 Info.set<EIIK_PostInstrSymbol>(PostInstrSymbol);
358 else
359 Info.set<EIIK_MMO>(MMOs[0]);
360}
361
362void MachineInstr::dropMemRefs(MachineFunction &MF) {
363 if (memoperands_empty())
364 return;
365
366 setExtraInfo(MF, {}, getPreInstrSymbol(), getPostInstrSymbol(),
367 getHeapAllocMarker());
368}
369
370void MachineInstr::setMemRefs(MachineFunction &MF,
371 ArrayRef<MachineMemOperand *> MMOs) {
372 if (MMOs.empty()) {
373 dropMemRefs(MF);
374 return;
375 }
376
377 setExtraInfo(MF, MMOs, getPreInstrSymbol(), getPostInstrSymbol(),
378 getHeapAllocMarker());
379}
380
381void MachineInstr::addMemOperand(MachineFunction &MF,
382 MachineMemOperand *MO) {
383 SmallVector<MachineMemOperand *, 2> MMOs;
384 MMOs.append(memoperands_begin(), memoperands_end());
385 MMOs.push_back(MO);
386 setMemRefs(MF, MMOs);
387}
388
389void MachineInstr::cloneMemRefs(MachineFunction &MF, const MachineInstr &MI) {
390 if (this == &MI)
391 // Nothing to do for a self-clone!
392 return;
393
394 assert(&MF == MI.getMF() &&((&MF == MI.getMF() && "Invalid machine functions when cloning memory refrences!"
) ? static_cast<void> (0) : __assert_fail ("&MF == MI.getMF() && \"Invalid machine functions when cloning memory refrences!\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/MachineInstr.cpp"
, 395, __PRETTY_FUNCTION__))
395 "Invalid machine functions when cloning memory refrences!")((&MF == MI.getMF() && "Invalid machine functions when cloning memory refrences!"
) ? static_cast<void> (0) : __assert_fail ("&MF == MI.getMF() && \"Invalid machine functions when cloning memory refrences!\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/MachineInstr.cpp"
, 395, __PRETTY_FUNCTION__))
;
396 // See if we can just steal the extra info already allocated for the
397 // instruction. We can do this whenever the pre- and post-instruction symbols
398 // are the same (including null).
399 if (getPreInstrSymbol() == MI.getPreInstrSymbol() &&
400 getPostInstrSymbol() == MI.getPostInstrSymbol() &&
401 getHeapAllocMarker() == MI.getHeapAllocMarker()) {
402 Info = MI.Info;
403 return;
404 }
405
406 // Otherwise, fall back on a copy-based clone.
407 setMemRefs(MF, MI.memoperands());
408}
409
410/// Check to see if the MMOs pointed to by the two MemRefs arrays are
411/// identical.
412static bool hasIdenticalMMOs(ArrayRef<MachineMemOperand *> LHS,
413 ArrayRef<MachineMemOperand *> RHS) {
414 if (LHS.size() != RHS.size())
415 return false;
416
417 auto LHSPointees = make_pointee_range(LHS);
418 auto RHSPointees = make_pointee_range(RHS);
419 return std::equal(LHSPointees.begin(), LHSPointees.end(),
420 RHSPointees.begin());
421}
422
423void MachineInstr::cloneMergedMemRefs(MachineFunction &MF,
424 ArrayRef<const MachineInstr *> MIs) {
425 // Try handling easy numbers of MIs with simpler mechanisms.
426 if (MIs.empty()) {
427 dropMemRefs(MF);
428 return;
429 }
430 if (MIs.size() == 1) {
431 cloneMemRefs(MF, *MIs[0]);
432 return;
433 }
434 // Because an empty memoperands list provides *no* information and must be
435 // handled conservatively (assuming the instruction can do anything), the only
436 // way to merge with it is to drop all other memoperands.
437 if (MIs[0]->memoperands_empty()) {
438 dropMemRefs(MF);
439 return;
440 }
441
442 // Handle the general case.
443 SmallVector<MachineMemOperand *, 2> MergedMMOs;
444 // Start with the first instruction.
445 assert(&MF == MIs[0]->getMF() &&((&MF == MIs[0]->getMF() && "Invalid machine functions when cloning memory references!"
) ? static_cast<void> (0) : __assert_fail ("&MF == MIs[0]->getMF() && \"Invalid machine functions when cloning memory references!\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/MachineInstr.cpp"
, 446, __PRETTY_FUNCTION__))
446 "Invalid machine functions when cloning memory references!")((&MF == MIs[0]->getMF() && "Invalid machine functions when cloning memory references!"
) ? static_cast<void> (0) : __assert_fail ("&MF == MIs[0]->getMF() && \"Invalid machine functions when cloning memory references!\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/MachineInstr.cpp"
, 446, __PRETTY_FUNCTION__))
;
447 MergedMMOs.append(MIs[0]->memoperands_begin(), MIs[0]->memoperands_end());
448 // Now walk all the other instructions and accumulate any different MMOs.
449 for (const MachineInstr &MI : make_pointee_range(MIs.slice(1))) {
450 assert(&MF == MI.getMF() &&((&MF == MI.getMF() && "Invalid machine functions when cloning memory references!"
) ? static_cast<void> (0) : __assert_fail ("&MF == MI.getMF() && \"Invalid machine functions when cloning memory references!\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/MachineInstr.cpp"
, 451, __PRETTY_FUNCTION__))
451 "Invalid machine functions when cloning memory references!")((&MF == MI.getMF() && "Invalid machine functions when cloning memory references!"
) ? static_cast<void> (0) : __assert_fail ("&MF == MI.getMF() && \"Invalid machine functions when cloning memory references!\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/MachineInstr.cpp"
, 451, __PRETTY_FUNCTION__))
;
452
453 // Skip MIs with identical operands to the first. This is a somewhat
454 // arbitrary hack but will catch common cases without being quadratic.
455 // TODO: We could fully implement merge semantics here if needed.
456 if (hasIdenticalMMOs(MIs[0]->memoperands(), MI.memoperands()))
457 continue;
458
459 // Because an empty memoperands list provides *no* information and must be
460 // handled conservatively (assuming the instruction can do anything), the
461 // only way to merge with it is to drop all other memoperands.
462 if (MI.memoperands_empty()) {
463 dropMemRefs(MF);
464 return;
465 }
466
467 // Otherwise accumulate these into our temporary buffer of the merged state.
468 MergedMMOs.append(MI.memoperands_begin(), MI.memoperands_end());
469 }
470
471 setMemRefs(MF, MergedMMOs);
472}
473
474void MachineInstr::setPreInstrSymbol(MachineFunction &MF, MCSymbol *Symbol) {
475 // Do nothing if old and new symbols are the same.
476 if (Symbol == getPreInstrSymbol())
477 return;
478
479 // If there was only one symbol and we're removing it, just clear info.
480 if (!Symbol && Info.is<EIIK_PreInstrSymbol>()) {
481 Info.clear();
482 return;
483 }
484
485 setExtraInfo(MF, memoperands(), Symbol, getPostInstrSymbol(),
486 getHeapAllocMarker());
487}
488
489void MachineInstr::setPostInstrSymbol(MachineFunction &MF, MCSymbol *Symbol) {
490 // Do nothing if old and new symbols are the same.
491 if (Symbol == getPostInstrSymbol())
492 return;
493
494 // If there was only one symbol and we're removing it, just clear info.
495 if (!Symbol && Info.is<EIIK_PostInstrSymbol>()) {
496 Info.clear();
497 return;
498 }
499
500 setExtraInfo(MF, memoperands(), getPreInstrSymbol(), Symbol,
501 getHeapAllocMarker());
502}
503
504void MachineInstr::setHeapAllocMarker(MachineFunction &MF, MDNode *Marker) {
505 // Do nothing if old and new symbols are the same.
506 if (Marker == getHeapAllocMarker())
507 return;
508
509 setExtraInfo(MF, memoperands(), getPreInstrSymbol(), getPostInstrSymbol(),
510 Marker);
511}
512
513void MachineInstr::cloneInstrSymbols(MachineFunction &MF,
514 const MachineInstr &MI) {
515 if (this == &MI)
516 // Nothing to do for a self-clone!
517 return;
518
519 assert(&MF == MI.getMF() &&((&MF == MI.getMF() && "Invalid machine functions when cloning instruction symbols!"
) ? static_cast<void> (0) : __assert_fail ("&MF == MI.getMF() && \"Invalid machine functions when cloning instruction symbols!\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/MachineInstr.cpp"
, 520, __PRETTY_FUNCTION__))
520 "Invalid machine functions when cloning instruction symbols!")((&MF == MI.getMF() && "Invalid machine functions when cloning instruction symbols!"
) ? static_cast<void> (0) : __assert_fail ("&MF == MI.getMF() && \"Invalid machine functions when cloning instruction symbols!\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/MachineInstr.cpp"
, 520, __PRETTY_FUNCTION__))
;
521
522 setPreInstrSymbol(MF, MI.getPreInstrSymbol());
523 setPostInstrSymbol(MF, MI.getPostInstrSymbol());
524 setHeapAllocMarker(MF, MI.getHeapAllocMarker());
525}
526
527uint16_t MachineInstr::mergeFlagsWith(const MachineInstr &Other) const {
528 // For now, the just return the union of the flags. If the flags get more
529 // complicated over time, we might need more logic here.
530 return getFlags() | Other.getFlags();
531}
532
533uint16_t MachineInstr::copyFlagsFromInstruction(const Instruction &I) {
534 uint16_t MIFlags = 0;
535 // Copy the wrapping flags.
536 if (const OverflowingBinaryOperator *OB =
537 dyn_cast<OverflowingBinaryOperator>(&I)) {
538 if (OB->hasNoSignedWrap())
539 MIFlags |= MachineInstr::MIFlag::NoSWrap;
540 if (OB->hasNoUnsignedWrap())
541 MIFlags |= MachineInstr::MIFlag::NoUWrap;
542 }
543
544 // Copy the exact flag.
545 if (const PossiblyExactOperator *PE = dyn_cast<PossiblyExactOperator>(&I))
546 if (PE->isExact())
547 MIFlags |= MachineInstr::MIFlag::IsExact;
548
549 // Copy the fast-math flags.
550 if (const FPMathOperator *FP = dyn_cast<FPMathOperator>(&I)) {
551 const FastMathFlags Flags = FP->getFastMathFlags();
552 if (Flags.noNaNs())
553 MIFlags |= MachineInstr::MIFlag::FmNoNans;
554 if (Flags.noInfs())
555 MIFlags |= MachineInstr::MIFlag::FmNoInfs;
556 if (Flags.noSignedZeros())
557 MIFlags |= MachineInstr::MIFlag::FmNsz;
558 if (Flags.allowReciprocal())
559 MIFlags |= MachineInstr::MIFlag::FmArcp;
560 if (Flags.allowContract())
561 MIFlags |= MachineInstr::MIFlag::FmContract;
562 if (Flags.approxFunc())
563 MIFlags |= MachineInstr::MIFlag::FmAfn;
564 if (Flags.allowReassoc())
565 MIFlags |= MachineInstr::MIFlag::FmReassoc;
566 }
567
568 return MIFlags;
569}
570
571void MachineInstr::copyIRFlags(const Instruction &I) {
572 Flags = copyFlagsFromInstruction(I);
573}
574
575bool MachineInstr::hasPropertyInBundle(uint64_t Mask, QueryType Type) const {
576 assert(!isBundledWithPred() && "Must be called on bundle header")((!isBundledWithPred() && "Must be called on bundle header"
) ? static_cast<void> (0) : __assert_fail ("!isBundledWithPred() && \"Must be called on bundle header\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/MachineInstr.cpp"
, 576, __PRETTY_FUNCTION__))
;
577 for (MachineBasicBlock::const_instr_iterator MII = getIterator();; ++MII) {
578 if (MII->getDesc().getFlags() & Mask) {
579 if (Type == AnyInBundle)
580 return true;
581 } else {
582 if (Type == AllInBundle && !MII->isBundle())
583 return false;
584 }
585 // This was the last instruction in the bundle.
586 if (!MII->isBundledWithSucc())
587 return Type == AllInBundle;
588 }
589}
590
591bool MachineInstr::isIdenticalTo(const MachineInstr &Other,
592 MICheckType Check) const {
593 // If opcodes or number of operands are not the same then the two
594 // instructions are obviously not identical.
595 if (Other.getOpcode() != getOpcode() ||
596 Other.getNumOperands() != getNumOperands())
597 return false;
598
599 if (isBundle()) {
600 // We have passed the test above that both instructions have the same
601 // opcode, so we know that both instructions are bundles here. Let's compare
602 // MIs inside the bundle.
603 assert(Other.isBundle() && "Expected that both instructions are bundles.")((Other.isBundle() && "Expected that both instructions are bundles."
) ? static_cast<void> (0) : __assert_fail ("Other.isBundle() && \"Expected that both instructions are bundles.\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/MachineInstr.cpp"
, 603, __PRETTY_FUNCTION__))
;
604 MachineBasicBlock::const_instr_iterator I1 = getIterator();
605 MachineBasicBlock::const_instr_iterator I2 = Other.getIterator();
606 // Loop until we analysed the last intruction inside at least one of the
607 // bundles.
608 while (I1->isBundledWithSucc() && I2->isBundledWithSucc()) {
609 ++I1;
610 ++I2;
611 if (!I1->isIdenticalTo(*I2, Check))
612 return false;
613 }
614 // If we've reached the end of just one of the two bundles, but not both,
615 // the instructions are not identical.
616 if (I1->isBundledWithSucc() || I2->isBundledWithSucc())
617 return false;
618 }
619
620 // Check operands to make sure they match.
621 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
622 const MachineOperand &MO = getOperand(i);
623 const MachineOperand &OMO = Other.getOperand(i);
624 if (!MO.isReg()) {
625 if (!MO.isIdenticalTo(OMO))
626 return false;
627 continue;
628 }
629
630 // Clients may or may not want to ignore defs when testing for equality.
631 // For example, machine CSE pass only cares about finding common
632 // subexpressions, so it's safe to ignore virtual register defs.
633 if (MO.isDef()) {
634 if (Check == IgnoreDefs)
635 continue;
636 else if (Check == IgnoreVRegDefs) {
637 if (!Register::isVirtualRegister(MO.getReg()) ||
638 !Register::isVirtualRegister(OMO.getReg()))
639 if (!MO.isIdenticalTo(OMO))
640 return false;
641 } else {
642 if (!MO.isIdenticalTo(OMO))
643 return false;
644 if (Check == CheckKillDead && MO.isDead() != OMO.isDead())
645 return false;
646 }
647 } else {
648 if (!MO.isIdenticalTo(OMO))
649 return false;
650 if (Check == CheckKillDead && MO.isKill() != OMO.isKill())
651 return false;
652 }
653 }
654 // If DebugLoc does not match then two debug instructions are not identical.
655 if (isDebugInstr())
656 if (getDebugLoc() && Other.getDebugLoc() &&
657 getDebugLoc() != Other.getDebugLoc())
658 return false;
659 return true;
660}
661
662const MachineFunction *MachineInstr::getMF() const {
663 return getParent()->getParent();
664}
665
666MachineInstr *MachineInstr::removeFromParent() {
667 assert(getParent() && "Not embedded in a basic block!")((getParent() && "Not embedded in a basic block!") ? static_cast
<void> (0) : __assert_fail ("getParent() && \"Not embedded in a basic block!\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/MachineInstr.cpp"
, 667, __PRETTY_FUNCTION__))
;
668 return getParent()->remove(this);
669}
670
671MachineInstr *MachineInstr::removeFromBundle() {
672 assert(getParent() && "Not embedded in a basic block!")((getParent() && "Not embedded in a basic block!") ? static_cast
<void> (0) : __assert_fail ("getParent() && \"Not embedded in a basic block!\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/MachineInstr.cpp"
, 672, __PRETTY_FUNCTION__))
;
673 return getParent()->remove_instr(this);
674}
675
676void MachineInstr::eraseFromParent() {
677 assert(getParent() && "Not embedded in a basic block!")((getParent() && "Not embedded in a basic block!") ? static_cast
<void> (0) : __assert_fail ("getParent() && \"Not embedded in a basic block!\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/MachineInstr.cpp"
, 677, __PRETTY_FUNCTION__))
;
678 getParent()->erase(this);
679}
680
681void MachineInstr::eraseFromParentAndMarkDBGValuesForRemoval() {
682 assert(getParent() && "Not embedded in a basic block!")((getParent() && "Not embedded in a basic block!") ? static_cast
<void> (0) : __assert_fail ("getParent() && \"Not embedded in a basic block!\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/MachineInstr.cpp"
, 682, __PRETTY_FUNCTION__))
;
683 MachineBasicBlock *MBB = getParent();
684 MachineFunction *MF = MBB->getParent();
685 assert(MF && "Not embedded in a function!")((MF && "Not embedded in a function!") ? static_cast<
void> (0) : __assert_fail ("MF && \"Not embedded in a function!\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/MachineInstr.cpp"
, 685, __PRETTY_FUNCTION__))
;
686
687 MachineInstr *MI = (MachineInstr *)this;
688 MachineRegisterInfo &MRI = MF->getRegInfo();
689
690 for (const MachineOperand &MO : MI->operands()) {
691 if (!MO.isReg() || !MO.isDef())
692 continue;
693 Register Reg = MO.getReg();
694 if (!Reg.isVirtual())
695 continue;
696 MRI.markUsesInDebugValueAsUndef(Reg);
697 }
698 MI->eraseFromParent();
699}
700
701void MachineInstr::eraseFromBundle() {
702 assert(getParent() && "Not embedded in a basic block!")((getParent() && "Not embedded in a basic block!") ? static_cast
<void> (0) : __assert_fail ("getParent() && \"Not embedded in a basic block!\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/MachineInstr.cpp"
, 702, __PRETTY_FUNCTION__))
;
703 getParent()->erase_instr(this);
704}
705
706bool MachineInstr::isCandidateForCallSiteEntry(QueryType Type) const {
707 if (!isCall(Type))
708 return false;
709 switch (getOpcode()) {
710 case TargetOpcode::PATCHABLE_EVENT_CALL:
711 case TargetOpcode::PATCHABLE_TYPED_EVENT_CALL:
712 case TargetOpcode::PATCHPOINT:
713 case TargetOpcode::STACKMAP:
714 case TargetOpcode::STATEPOINT:
715 return false;
716 }
717 return true;
718}
719
720bool MachineInstr::shouldUpdateCallSiteInfo() const {
721 if (isBundle())
722 return isCandidateForCallSiteEntry(MachineInstr::AnyInBundle);
723 return isCandidateForCallSiteEntry();
724}
725
726unsigned MachineInstr::getNumExplicitOperands() const {
727 unsigned NumOperands = MCID->getNumOperands();
728 if (!MCID->isVariadic())
729 return NumOperands;
730
731 for (unsigned I = NumOperands, E = getNumOperands(); I != E; ++I) {
732 const MachineOperand &MO = getOperand(I);
733 // The operands must always be in the following order:
734 // - explicit reg defs,
735 // - other explicit operands (reg uses, immediates, etc.),
736 // - implicit reg defs
737 // - implicit reg uses
738 if (MO.isReg() && MO.isImplicit())
739 break;
740 ++NumOperands;
741 }
742 return NumOperands;
743}
744
745unsigned MachineInstr::getNumExplicitDefs() const {
746 unsigned NumDefs = MCID->getNumDefs();
747 if (!MCID->isVariadic())
748 return NumDefs;
749
750 for (unsigned I = NumDefs, E = getNumOperands(); I != E; ++I) {
751 const MachineOperand &MO = getOperand(I);
752 if (!MO.isReg() || !MO.isDef() || MO.isImplicit())
753 break;
754 ++NumDefs;
755 }
756 return NumDefs;
757}
758
759void MachineInstr::bundleWithPred() {
760 assert(!isBundledWithPred() && "MI is already bundled with its predecessor")((!isBundledWithPred() && "MI is already bundled with its predecessor"
) ? static_cast<void> (0) : __assert_fail ("!isBundledWithPred() && \"MI is already bundled with its predecessor\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/MachineInstr.cpp"
, 760, __PRETTY_FUNCTION__))
;
761 setFlag(BundledPred);
762 MachineBasicBlock::instr_iterator Pred = getIterator();
763 --Pred;
764 assert(!Pred->isBundledWithSucc() && "Inconsistent bundle flags")((!Pred->isBundledWithSucc() && "Inconsistent bundle flags"
) ? static_cast<void> (0) : __assert_fail ("!Pred->isBundledWithSucc() && \"Inconsistent bundle flags\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/MachineInstr.cpp"
, 764, __PRETTY_FUNCTION__))
;
765 Pred->setFlag(BundledSucc);
766}
767
768void MachineInstr::bundleWithSucc() {
769 assert(!isBundledWithSucc() && "MI is already bundled with its successor")((!isBundledWithSucc() && "MI is already bundled with its successor"
) ? static_cast<void> (0) : __assert_fail ("!isBundledWithSucc() && \"MI is already bundled with its successor\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/MachineInstr.cpp"
, 769, __PRETTY_FUNCTION__))
;
770 setFlag(BundledSucc);
771 MachineBasicBlock::instr_iterator Succ = getIterator();
772 ++Succ;
773 assert(!Succ->isBundledWithPred() && "Inconsistent bundle flags")((!Succ->isBundledWithPred() && "Inconsistent bundle flags"
) ? static_cast<void> (0) : __assert_fail ("!Succ->isBundledWithPred() && \"Inconsistent bundle flags\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/MachineInstr.cpp"
, 773, __PRETTY_FUNCTION__))
;
774 Succ->setFlag(BundledPred);
775}
776
777void MachineInstr::unbundleFromPred() {
778 assert(isBundledWithPred() && "MI isn't bundled with its predecessor")((isBundledWithPred() && "MI isn't bundled with its predecessor"
) ? static_cast<void> (0) : __assert_fail ("isBundledWithPred() && \"MI isn't bundled with its predecessor\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/MachineInstr.cpp"
, 778, __PRETTY_FUNCTION__))
;
779 clearFlag(BundledPred);
780 MachineBasicBlock::instr_iterator Pred = getIterator();
781 --Pred;
782 assert(Pred->isBundledWithSucc() && "Inconsistent bundle flags")((Pred->isBundledWithSucc() && "Inconsistent bundle flags"
) ? static_cast<void> (0) : __assert_fail ("Pred->isBundledWithSucc() && \"Inconsistent bundle flags\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/MachineInstr.cpp"
, 782, __PRETTY_FUNCTION__))
;
783 Pred->clearFlag(BundledSucc);
784}
785
786void MachineInstr::unbundleFromSucc() {
787 assert(isBundledWithSucc() && "MI isn't bundled with its successor")((isBundledWithSucc() && "MI isn't bundled with its successor"
) ? static_cast<void> (0) : __assert_fail ("isBundledWithSucc() && \"MI isn't bundled with its successor\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/MachineInstr.cpp"
, 787, __PRETTY_FUNCTION__))
;
788 clearFlag(BundledSucc);
789 MachineBasicBlock::instr_iterator Succ = getIterator();
790 ++Succ;
791 assert(Succ->isBundledWithPred() && "Inconsistent bundle flags")((Succ->isBundledWithPred() && "Inconsistent bundle flags"
) ? static_cast<void> (0) : __assert_fail ("Succ->isBundledWithPred() && \"Inconsistent bundle flags\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/MachineInstr.cpp"
, 791, __PRETTY_FUNCTION__))
;
792 Succ->clearFlag(BundledPred);
793}
794
795bool MachineInstr::isStackAligningInlineAsm() const {
796 if (isInlineAsm()) {
797 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
798 if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
799 return true;
800 }
801 return false;
802}
803
804InlineAsm::AsmDialect MachineInstr::getInlineAsmDialect() const {
805 assert(isInlineAsm() && "getInlineAsmDialect() only works for inline asms!")((isInlineAsm() && "getInlineAsmDialect() only works for inline asms!"
) ? static_cast<void> (0) : __assert_fail ("isInlineAsm() && \"getInlineAsmDialect() only works for inline asms!\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/MachineInstr.cpp"
, 805, __PRETTY_FUNCTION__))
;
806 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
807 return InlineAsm::AsmDialect((ExtraInfo & InlineAsm::Extra_AsmDialect) != 0);
808}
809
810int MachineInstr::findInlineAsmFlagIdx(unsigned OpIdx,
811 unsigned *GroupNo) const {
812 assert(isInlineAsm() && "Expected an inline asm instruction")((isInlineAsm() && "Expected an inline asm instruction"
) ? static_cast<void> (0) : __assert_fail ("isInlineAsm() && \"Expected an inline asm instruction\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/MachineInstr.cpp"
, 812, __PRETTY_FUNCTION__))
;
813 assert(OpIdx < getNumOperands() && "OpIdx out of range")((OpIdx < getNumOperands() && "OpIdx out of range"
) ? static_cast<void> (0) : __assert_fail ("OpIdx < getNumOperands() && \"OpIdx out of range\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/MachineInstr.cpp"
, 813, __PRETTY_FUNCTION__))
;
814
815 // Ignore queries about the initial operands.
816 if (OpIdx < InlineAsm::MIOp_FirstOperand)
817 return -1;
818
819 unsigned Group = 0;
820 unsigned NumOps;
821 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
822 i += NumOps) {
823 const MachineOperand &FlagMO = getOperand(i);
824 // If we reach the implicit register operands, stop looking.
825 if (!FlagMO.isImm())
826 return -1;
827 NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
828 if (i + NumOps > OpIdx) {
829 if (GroupNo)
830 *GroupNo = Group;
831 return i;
832 }
833 ++Group;
834 }
835 return -1;
836}
837
838const DILabel *MachineInstr::getDebugLabel() const {
839 assert(isDebugLabel() && "not a DBG_LABEL")((isDebugLabel() && "not a DBG_LABEL") ? static_cast<
void> (0) : __assert_fail ("isDebugLabel() && \"not a DBG_LABEL\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/MachineInstr.cpp"
, 839, __PRETTY_FUNCTION__))
;
840 return cast<DILabel>(getOperand(0).getMetadata());
841}
842
843const MachineOperand &MachineInstr::getDebugVariableOp() const {
844 assert((isDebugValue() || isDebugRef()) && "not a DBG_VALUE")(((isDebugValue() || isDebugRef()) && "not a DBG_VALUE"
) ? static_cast<void> (0) : __assert_fail ("(isDebugValue() || isDebugRef()) && \"not a DBG_VALUE\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/MachineInstr.cpp"
, 844, __PRETTY_FUNCTION__))
;
845 return getOperand(2);
846}
847
848MachineOperand &MachineInstr::getDebugVariableOp() {
849 assert((isDebugValue() || isDebugRef()) && "not a DBG_VALUE")(((isDebugValue() || isDebugRef()) && "not a DBG_VALUE"
) ? static_cast<void> (0) : __assert_fail ("(isDebugValue() || isDebugRef()) && \"not a DBG_VALUE\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/MachineInstr.cpp"
, 849, __PRETTY_FUNCTION__))
;
850 return getOperand(2);
851}
852
853const DILocalVariable *MachineInstr::getDebugVariable() const {
854 assert((isDebugValue() || isDebugRef()) && "not a DBG_VALUE")(((isDebugValue() || isDebugRef()) && "not a DBG_VALUE"
) ? static_cast<void> (0) : __assert_fail ("(isDebugValue() || isDebugRef()) && \"not a DBG_VALUE\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/MachineInstr.cpp"
, 854, __PRETTY_FUNCTION__))
;
855 return cast<DILocalVariable>(getOperand(2).getMetadata());
856}
857
858MachineOperand &MachineInstr::getDebugExpressionOp() {
859 assert((isDebugValue() || isDebugRef()) && "not a DBG_VALUE")(((isDebugValue() || isDebugRef()) && "not a DBG_VALUE"
) ? static_cast<void> (0) : __assert_fail ("(isDebugValue() || isDebugRef()) && \"not a DBG_VALUE\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/MachineInstr.cpp"
, 859, __PRETTY_FUNCTION__))
;
860 return getOperand(3);
861}
862
863const DIExpression *MachineInstr::getDebugExpression() const {
864 assert((isDebugValue() || isDebugRef()) && "not a DBG_VALUE")(((isDebugValue() || isDebugRef()) && "not a DBG_VALUE"
) ? static_cast<void> (0) : __assert_fail ("(isDebugValue() || isDebugRef()) && \"not a DBG_VALUE\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/MachineInstr.cpp"
, 864, __PRETTY_FUNCTION__))
;
865 return cast<DIExpression>(getOperand(3).getMetadata());
866}
867
868bool MachineInstr::isDebugEntryValue() const {
869 return isDebugValue() && getDebugExpression()->isEntryValue();
870}
871
872const TargetRegisterClass*
873MachineInstr::getRegClassConstraint(unsigned OpIdx,
874 const TargetInstrInfo *TII,
875 const TargetRegisterInfo *TRI) const {
876 assert(getParent() && "Can't have an MBB reference here!")((getParent() && "Can't have an MBB reference here!")
? static_cast<void> (0) : __assert_fail ("getParent() && \"Can't have an MBB reference here!\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/MachineInstr.cpp"
, 876, __PRETTY_FUNCTION__))
;
877 assert(getMF() && "Can't have an MF reference here!")((getMF() && "Can't have an MF reference here!") ? static_cast
<void> (0) : __assert_fail ("getMF() && \"Can't have an MF reference here!\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/MachineInstr.cpp"
, 877, __PRETTY_FUNCTION__))
;
878 const MachineFunction &MF = *getMF();
879
880 // Most opcodes have fixed constraints in their MCInstrDesc.
881 if (!isInlineAsm())
882 return TII->getRegClass(getDesc(), OpIdx, TRI, MF);
883
884 if (!getOperand(OpIdx).isReg())
885 return nullptr;
886
887 // For tied uses on inline asm, get the constraint from the def.
888 unsigned DefIdx;
889 if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx))
890 OpIdx = DefIdx;
891
892 // Inline asm stores register class constraints in the flag word.
893 int FlagIdx = findInlineAsmFlagIdx(OpIdx);
894 if (FlagIdx < 0)
895 return nullptr;
896
897 unsigned Flag = getOperand(FlagIdx).getImm();
898 unsigned RCID;
899 if ((InlineAsm::getKind(Flag) == InlineAsm::Kind_RegUse ||
900 InlineAsm::getKind(Flag) == InlineAsm::Kind_RegDef ||
901 InlineAsm::getKind(Flag) == InlineAsm::Kind_RegDefEarlyClobber) &&
902 InlineAsm::hasRegClassConstraint(Flag, RCID))
903 return TRI->getRegClass(RCID);
904
905 // Assume that all registers in a memory operand are pointers.
906 if (InlineAsm::getKind(Flag) == InlineAsm::Kind_Mem)
907 return TRI->getPointerRegClass(MF);
908
909 return nullptr;
910}
911
912const TargetRegisterClass *MachineInstr::getRegClassConstraintEffectForVReg(
913 Register Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII,
914 const TargetRegisterInfo *TRI, bool ExploreBundle) const {
915 // Check every operands inside the bundle if we have
916 // been asked to.
917 if (ExploreBundle)
918 for (ConstMIBundleOperands OpndIt(*this); OpndIt.isValid() && CurRC;
919 ++OpndIt)
920 CurRC = OpndIt->getParent()->getRegClassConstraintEffectForVRegImpl(
921 OpndIt.getOperandNo(), Reg, CurRC, TII, TRI);
922 else
923 // Otherwise, just check the current operands.
924 for (unsigned i = 0, e = NumOperands; i < e && CurRC; ++i)
925 CurRC = getRegClassConstraintEffectForVRegImpl(i, Reg, CurRC, TII, TRI);
926 return CurRC;
927}
928
929const TargetRegisterClass *MachineInstr::getRegClassConstraintEffectForVRegImpl(
930 unsigned OpIdx, Register Reg, const TargetRegisterClass *CurRC,
931 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const {
932 assert(CurRC && "Invalid initial register class")((CurRC && "Invalid initial register class") ? static_cast
<void> (0) : __assert_fail ("CurRC && \"Invalid initial register class\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/MachineInstr.cpp"
, 932, __PRETTY_FUNCTION__))
;
933 // Check if Reg is constrained by some of its use/def from MI.
934 const MachineOperand &MO = getOperand(OpIdx);
935 if (!MO.isReg() || MO.getReg() != Reg)
936 return CurRC;
937 // If yes, accumulate the constraints through the operand.
938 return getRegClassConstraintEffect(OpIdx, CurRC, TII, TRI);
939}
940
941const TargetRegisterClass *MachineInstr::getRegClassConstraintEffect(
942 unsigned OpIdx, const TargetRegisterClass *CurRC,
943 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const {
944 const TargetRegisterClass *OpRC = getRegClassConstraint(OpIdx, TII, TRI);
945 const MachineOperand &MO = getOperand(OpIdx);
946 assert(MO.isReg() &&((MO.isReg() && "Cannot get register constraints for non-register operand"
) ? static_cast<void> (0) : __assert_fail ("MO.isReg() && \"Cannot get register constraints for non-register operand\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/MachineInstr.cpp"
, 947, __PRETTY_FUNCTION__))
947 "Cannot get register constraints for non-register operand")((MO.isReg() && "Cannot get register constraints for non-register operand"
) ? static_cast<void> (0) : __assert_fail ("MO.isReg() && \"Cannot get register constraints for non-register operand\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/MachineInstr.cpp"
, 947, __PRETTY_FUNCTION__))
;
948 assert(CurRC && "Invalid initial register class")((CurRC && "Invalid initial register class") ? static_cast
<void> (0) : __assert_fail ("CurRC && \"Invalid initial register class\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/MachineInstr.cpp"
, 948, __PRETTY_FUNCTION__))
;
949 if (unsigned SubIdx = MO.getSubReg()) {
950 if (OpRC)
951 CurRC = TRI->getMatchingSuperRegClass(CurRC, OpRC, SubIdx);
952 else
953 CurRC = TRI->getSubClassWithSubReg(CurRC, SubIdx);
954 } else if (OpRC)
955 CurRC = TRI->getCommonSubClass(CurRC, OpRC);
956 return CurRC;
957}
958
959/// Return the number of instructions inside the MI bundle, not counting the
960/// header instruction.
961unsigned MachineInstr::getBundleSize() const {
962 MachineBasicBlock::const_instr_iterator I = getIterator();
963 unsigned Size = 0;
964 while (I->isBundledWithSucc()) {
965 ++Size;
966 ++I;
967 }
968 return Size;
969}
970
971/// Returns true if the MachineInstr has an implicit-use operand of exactly
972/// the given register (not considering sub/super-registers).
973bool MachineInstr::hasRegisterImplicitUseOperand(Register Reg) const {
974 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
975 const MachineOperand &MO = getOperand(i);
976 if (MO.isReg() && MO.isUse() && MO.isImplicit() && MO.getReg() == Reg)
977 return true;
978 }
979 return false;
980}
981
982/// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
983/// the specific register or -1 if it is not found. It further tightens
984/// the search criteria to a use that kills the register if isKill is true.
985int MachineInstr::findRegisterUseOperandIdx(
986 Register Reg, bool isKill, const TargetRegisterInfo *TRI) const {
987 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
988 const MachineOperand &MO = getOperand(i);
989 if (!MO.isReg() || !MO.isUse())
990 continue;
991 Register MOReg = MO.getReg();
992 if (!MOReg)
993 continue;
994 if (MOReg == Reg || (TRI && Reg && MOReg && TRI->regsOverlap(MOReg, Reg)))
995 if (!isKill || MO.isKill())
996 return i;
997 }
998 return -1;
999}
1000
1001/// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
1002/// indicating if this instruction reads or writes Reg. This also considers
1003/// partial defines.
1004std::pair<bool,bool>
1005MachineInstr::readsWritesVirtualRegister(Register Reg,
1006 SmallVectorImpl<unsigned> *Ops) const {
1007 bool PartDef = false; // Partial redefine.
1008 bool FullDef = false; // Full define.
1009 bool Use = false;
1010
1011 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1012 const MachineOperand &MO = getOperand(i);
1013 if (!MO.isReg() || MO.getReg() != Reg)
1014 continue;
1015 if (Ops)
1016 Ops->push_back(i);
1017 if (MO.isUse())
1018 Use |= !MO.isUndef();
1019 else if (MO.getSubReg() && !MO.isUndef())
1020 // A partial def undef doesn't count as reading the register.
1021 PartDef = true;
1022 else
1023 FullDef = true;
1024 }
1025 // A partial redefine uses Reg unless there is also a full define.
1026 return std::make_pair(Use || (PartDef && !FullDef), PartDef || FullDef);
1027}
1028
1029/// findRegisterDefOperandIdx() - Returns the operand index that is a def of
1030/// the specified register or -1 if it is not found. If isDead is true, defs
1031/// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
1032/// also checks if there is a def of a super-register.
1033int
1034MachineInstr::findRegisterDefOperandIdx(Register Reg, bool isDead, bool Overlap,
1035 const TargetRegisterInfo *TRI) const {
1036 bool isPhys = Register::isPhysicalRegister(Reg);
1037 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1038 const MachineOperand &MO = getOperand(i);
1039 // Accept regmask operands when Overlap is set.
1040 // Ignore them when looking for a specific def operand (Overlap == false).
1041 if (isPhys && Overlap && MO.isRegMask() && MO.clobbersPhysReg(Reg))
1042 return i;
1043 if (!MO.isReg() || !MO.isDef())
1044 continue;
1045 Register MOReg = MO.getReg();
1046 bool Found = (MOReg == Reg);
1047 if (!Found && TRI && isPhys && Register::isPhysicalRegister(MOReg)) {
1048 if (Overlap)
1049 Found = TRI->regsOverlap(MOReg, Reg);
1050 else
1051 Found = TRI->isSubRegister(MOReg, Reg);
1052 }
1053 if (Found && (!isDead || MO.isDead()))
1054 return i;
1055 }
1056 return -1;
1057}
1058
1059/// findFirstPredOperandIdx() - Find the index of the first operand in the
1060/// operand list that is used to represent the predicate. It returns -1 if
1061/// none is found.
1062int MachineInstr::findFirstPredOperandIdx() const {
1063 // Don't call MCID.findFirstPredOperandIdx() because this variant
1064 // is sometimes called on an instruction that's not yet complete, and
1065 // so the number of operands is less than the MCID indicates. In
1066 // particular, the PTX target does this.
1067 const MCInstrDesc &MCID = getDesc();
1068 if (MCID.isPredicable()) {
1069 for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
1070 if (MCID.OpInfo[i].isPredicate())
1071 return i;
1072 }
1073
1074 return -1;
1075}
1076
1077// MachineOperand::TiedTo is 4 bits wide.
1078const unsigned TiedMax = 15;
1079
1080/// tieOperands - Mark operands at DefIdx and UseIdx as tied to each other.
1081///
1082/// Use and def operands can be tied together, indicated by a non-zero TiedTo
1083/// field. TiedTo can have these values:
1084///
1085/// 0: Operand is not tied to anything.
1086/// 1 to TiedMax-1: Tied to getOperand(TiedTo-1).
1087/// TiedMax: Tied to an operand >= TiedMax-1.
1088///
1089/// The tied def must be one of the first TiedMax operands on a normal
1090/// instruction. INLINEASM instructions allow more tied defs.
1091///
1092void MachineInstr::tieOperands(unsigned DefIdx, unsigned UseIdx) {
1093 MachineOperand &DefMO = getOperand(DefIdx);
1094 MachineOperand &UseMO = getOperand(UseIdx);
1095 assert(DefMO.isDef() && "DefIdx must be a def operand")((DefMO.isDef() && "DefIdx must be a def operand") ? static_cast
<void> (0) : __assert_fail ("DefMO.isDef() && \"DefIdx must be a def operand\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/MachineInstr.cpp"
, 1095, __PRETTY_FUNCTION__))
;
1096 assert(UseMO.isUse() && "UseIdx must be a use operand")((UseMO.isUse() && "UseIdx must be a use operand") ? static_cast
<void> (0) : __assert_fail ("UseMO.isUse() && \"UseIdx must be a use operand\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/MachineInstr.cpp"
, 1096, __PRETTY_FUNCTION__))
;
1097 assert(!DefMO.isTied() && "Def is already tied to another use")((!DefMO.isTied() && "Def is already tied to another use"
) ? static_cast<void> (0) : __assert_fail ("!DefMO.isTied() && \"Def is already tied to another use\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/MachineInstr.cpp"
, 1097, __PRETTY_FUNCTION__))
;
1098 assert(!UseMO.isTied() && "Use is already tied to another def")((!UseMO.isTied() && "Use is already tied to another def"
) ? static_cast<void> (0) : __assert_fail ("!UseMO.isTied() && \"Use is already tied to another def\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/MachineInstr.cpp"
, 1098, __PRETTY_FUNCTION__))
;
1099
1100 if (DefIdx < TiedMax)
1101 UseMO.TiedTo = DefIdx + 1;
1102 else {
1103 // Inline asm can use the group descriptors to find tied operands, but on
1104 // normal instruction, the tied def must be within the first TiedMax
1105 // operands.
1106 assert(isInlineAsm() && "DefIdx out of range")((isInlineAsm() && "DefIdx out of range") ? static_cast
<void> (0) : __assert_fail ("isInlineAsm() && \"DefIdx out of range\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/MachineInstr.cpp"
, 1106, __PRETTY_FUNCTION__))
;
1107 UseMO.TiedTo = TiedMax;
1108 }
1109
1110 // UseIdx can be out of range, we'll search for it in findTiedOperandIdx().
1111 DefMO.TiedTo = std::min(UseIdx + 1, TiedMax);
1112}
1113
1114/// Given the index of a tied register operand, find the operand it is tied to.
1115/// Defs are tied to uses and vice versa. Returns the index of the tied operand
1116/// which must exist.
1117unsigned MachineInstr::findTiedOperandIdx(unsigned OpIdx) const {
1118 const MachineOperand &MO = getOperand(OpIdx);
1119 assert(MO.isTied() && "Operand isn't tied")((MO.isTied() && "Operand isn't tied") ? static_cast<
void> (0) : __assert_fail ("MO.isTied() && \"Operand isn't tied\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/MachineInstr.cpp"
, 1119, __PRETTY_FUNCTION__))
;
1120
1121 // Normally TiedTo is in range.
1122 if (MO.TiedTo < TiedMax)
1123 return MO.TiedTo - 1;
1124
1125 // Uses on normal instructions can be out of range.
1126 if (!isInlineAsm()) {
1127 // Normal tied defs must be in the 0..TiedMax-1 range.
1128 if (MO.isUse())
1129 return TiedMax - 1;
1130 // MO is a def. Search for the tied use.
1131 for (unsigned i = TiedMax - 1, e = getNumOperands(); i != e; ++i) {
1132 const MachineOperand &UseMO = getOperand(i);
1133 if (UseMO.isReg() && UseMO.isUse() && UseMO.TiedTo == OpIdx + 1)
1134 return i;
1135 }
1136 llvm_unreachable("Can't find tied use")::llvm::llvm_unreachable_internal("Can't find tied use", "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/MachineInstr.cpp"
, 1136)
;
1137 }
1138
1139 // Now deal with inline asm by parsing the operand group descriptor flags.
1140 // Find the beginning of each operand group.
1141 SmallVector<unsigned, 8> GroupIdx;
1142 unsigned OpIdxGroup = ~0u;
1143 unsigned NumOps;
1144 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
1145 i += NumOps) {
1146 const MachineOperand &FlagMO = getOperand(i);
1147 assert(FlagMO.isImm() && "Invalid tied operand on inline asm")((FlagMO.isImm() && "Invalid tied operand on inline asm"
) ? static_cast<void> (0) : __assert_fail ("FlagMO.isImm() && \"Invalid tied operand on inline asm\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/MachineInstr.cpp"
, 1147, __PRETTY_FUNCTION__))
;
1148 unsigned CurGroup = GroupIdx.size();
1149 GroupIdx.push_back(i);
1150 NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
1151 // OpIdx belongs to this operand group.
1152 if (OpIdx > i && OpIdx < i + NumOps)
1153 OpIdxGroup = CurGroup;
1154 unsigned TiedGroup;
1155 if (!InlineAsm::isUseOperandTiedToDef(FlagMO.getImm(), TiedGroup))
1156 continue;
1157 // Operands in this group are tied to operands in TiedGroup which must be
1158 // earlier. Find the number of operands between the two groups.
1159 unsigned Delta = i - GroupIdx[TiedGroup];
1160
1161 // OpIdx is a use tied to TiedGroup.
1162 if (OpIdxGroup == CurGroup)
1163 return OpIdx - Delta;
1164
1165 // OpIdx is a def tied to this use group.
1166 if (OpIdxGroup == TiedGroup)
1167 return OpIdx + Delta;
1168 }
1169 llvm_unreachable("Invalid tied operand on inline asm")::llvm::llvm_unreachable_internal("Invalid tied operand on inline asm"
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/MachineInstr.cpp"
, 1169)
;
1170}
1171
1172/// clearKillInfo - Clears kill flags on all operands.
1173///
1174void MachineInstr::clearKillInfo() {
1175 for (MachineOperand &MO : operands()) {
1176 if (MO.isReg() && MO.isUse())
1177 MO.setIsKill(false);
1178 }
1179}
1180
1181void MachineInstr::substituteRegister(Register FromReg, Register ToReg,
1182 unsigned SubIdx,
1183 const TargetRegisterInfo &RegInfo) {
1184 if (Register::isPhysicalRegister(ToReg)) {
1185 if (SubIdx)
1186 ToReg = RegInfo.getSubReg(ToReg, SubIdx);
1187 for (MachineOperand &MO : operands()) {
1188 if (!MO.isReg() || MO.getReg() != FromReg)
1189 continue;
1190 MO.substPhysReg(ToReg, RegInfo);
1191 }
1192 } else {
1193 for (MachineOperand &MO : operands()) {
1194 if (!MO.isReg() || MO.getReg() != FromReg)
1195 continue;
1196 MO.substVirtReg(ToReg, SubIdx, RegInfo);
1197 }
1198 }
1199}
1200
1201/// isSafeToMove - Return true if it is safe to move this instruction. If
1202/// SawStore is set to true, it means that there is a store (or call) between
1203/// the instruction's location and its intended destination.
1204bool MachineInstr::isSafeToMove(AAResults *AA, bool &SawStore) const {
1205 // Ignore stuff that we obviously can't move.
1206 //
1207 // Treat volatile loads as stores. This is not strictly necessary for
1208 // volatiles, but it is required for atomic loads. It is not allowed to move
1209 // a load across an atomic load with Ordering > Monotonic.
1210 if (mayStore() || isCall() || isPHI() ||
1211 (mayLoad() && hasOrderedMemoryRef())) {
1212 SawStore = true;
1213 return false;
1214 }
1215
1216 if (isPosition() || isDebugInstr() || isTerminator() ||
1217 mayRaiseFPException() || hasUnmodeledSideEffects())
1218 return false;
1219
1220 // See if this instruction does a load. If so, we have to guarantee that the
1221 // loaded value doesn't change between the load and the its intended
1222 // destination. The check for isInvariantLoad gives the target the chance to
1223 // classify the load as always returning a constant, e.g. a constant pool
1224 // load.
1225 if (mayLoad() && !isDereferenceableInvariantLoad(AA))
1226 // Otherwise, this is a real load. If there is a store between the load and
1227 // end of block, we can't move it.
1228 return !SawStore;
1229
1230 return true;
1231}
1232
1233bool MachineInstr::mayAlias(AAResults *AA, const MachineInstr &Other,
1234 bool UseTBAA) const {
1235 const MachineFunction *MF = getMF();
1236 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
1237 const MachineFrameInfo &MFI = MF->getFrameInfo();
1238
1239 // If neither instruction stores to memory, they can't alias in any
1240 // meaningful way, even if they read from the same address.
1241 if (!mayStore() && !Other.mayStore())
1242 return false;
1243
1244 // Both instructions must be memory operations to be able to alias.
1245 if (!mayLoadOrStore() || !Other.mayLoadOrStore())
1246 return false;
1247
1248 // Let the target decide if memory accesses cannot possibly overlap.
1249 if (TII->areMemAccessesTriviallyDisjoint(*this, Other))
1250 return false;
1251
1252 // FIXME: Need to handle multiple memory operands to support all targets.
1253 if (!hasOneMemOperand() || !Other.hasOneMemOperand())
1254 return true;
1255
1256 MachineMemOperand *MMOa = *memoperands_begin();
1257 MachineMemOperand *MMOb = *Other.memoperands_begin();
1258
1259 // The following interface to AA is fashioned after DAGCombiner::isAlias
1260 // and operates with MachineMemOperand offset with some important
1261 // assumptions:
1262 // - LLVM fundamentally assumes flat address spaces.
1263 // - MachineOperand offset can *only* result from legalization and
1264 // cannot affect queries other than the trivial case of overlap
1265 // checking.
1266 // - These offsets never wrap and never step outside
1267 // of allocated objects.
1268 // - There should never be any negative offsets here.
1269 //
1270 // FIXME: Modify API to hide this math from "user"
1271 // Even before we go to AA we can reason locally about some
1272 // memory objects. It can save compile time, and possibly catch some
1273 // corner cases not currently covered.
1274
1275 int64_t OffsetA = MMOa->getOffset();
1276 int64_t OffsetB = MMOb->getOffset();
1277 int64_t MinOffset = std::min(OffsetA, OffsetB);
1278
1279 uint64_t WidthA = MMOa->getSize();
1280 uint64_t WidthB = MMOb->getSize();
1281 bool KnownWidthA = WidthA != MemoryLocation::UnknownSize;
1282 bool KnownWidthB = WidthB != MemoryLocation::UnknownSize;
1283
1284 const Value *ValA = MMOa->getValue();
1285 const Value *ValB = MMOb->getValue();
1286 bool SameVal = (ValA && ValB && (ValA == ValB));
1287 if (!SameVal) {
1288 const PseudoSourceValue *PSVa = MMOa->getPseudoValue();
1289 const PseudoSourceValue *PSVb = MMOb->getPseudoValue();
1290 if (PSVa && ValB && !PSVa->mayAlias(&MFI))
1291 return false;
1292 if (PSVb && ValA && !PSVb->mayAlias(&MFI))
1293 return false;
1294 if (PSVa && PSVb && (PSVa == PSVb))
1295 SameVal = true;
1296 }
1297
1298 if (SameVal) {
1299 if (!KnownWidthA || !KnownWidthB)
1300 return true;
1301 int64_t MaxOffset = std::max(OffsetA, OffsetB);
1302 int64_t LowWidth = (MinOffset == OffsetA) ? WidthA : WidthB;
1303 return (MinOffset + LowWidth > MaxOffset);
1304 }
1305
1306 if (!AA)
1307 return true;
1308
1309 if (!ValA || !ValB)
1310 return true;
1311
1312 assert((OffsetA >= 0) && "Negative MachineMemOperand offset")(((OffsetA >= 0) && "Negative MachineMemOperand offset"
) ? static_cast<void> (0) : __assert_fail ("(OffsetA >= 0) && \"Negative MachineMemOperand offset\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/MachineInstr.cpp"
, 1312, __PRETTY_FUNCTION__))
;
1313 assert((OffsetB >= 0) && "Negative MachineMemOperand offset")(((OffsetB >= 0) && "Negative MachineMemOperand offset"
) ? static_cast<void> (0) : __assert_fail ("(OffsetB >= 0) && \"Negative MachineMemOperand offset\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/MachineInstr.cpp"
, 1313, __PRETTY_FUNCTION__))
;
1314
1315 int64_t OverlapA = KnownWidthA ? WidthA + OffsetA - MinOffset
1316 : MemoryLocation::UnknownSize;
1317 int64_t OverlapB = KnownWidthB ? WidthB + OffsetB - MinOffset
1318 : MemoryLocation::UnknownSize;
1319
1320 AliasResult AAResult = AA->alias(
1321 MemoryLocation(ValA, OverlapA,
1322 UseTBAA ? MMOa->getAAInfo() : AAMDNodes()),
1323 MemoryLocation(ValB, OverlapB,
1324 UseTBAA ? MMOb->getAAInfo() : AAMDNodes()));
1325
1326 return (AAResult != NoAlias);
1327}
1328
1329/// hasOrderedMemoryRef - Return true if this instruction may have an ordered
1330/// or volatile memory reference, or if the information describing the memory
1331/// reference is not available. Return false if it is known to have no ordered
1332/// memory references.
1333bool MachineInstr::hasOrderedMemoryRef() const {
1334 // An instruction known never to access memory won't have a volatile access.
1335 if (!mayStore() &&
1336 !mayLoad() &&
1337 !isCall() &&
1338 !hasUnmodeledSideEffects())
1339 return false;
1340
1341 // Otherwise, if the instruction has no memory reference information,
1342 // conservatively assume it wasn't preserved.
1343 if (memoperands_empty())
1344 return true;
1345
1346 // Check if any of our memory operands are ordered.
1347 return llvm::any_of(memoperands(), [](const MachineMemOperand *MMO) {
1348 return !MMO->isUnordered();
1349 });
1350}
1351
1352/// isDereferenceableInvariantLoad - Return true if this instruction will never
1353/// trap and is loading from a location whose value is invariant across a run of
1354/// this function.
1355bool MachineInstr::isDereferenceableInvariantLoad(AAResults *AA) const {
1356 // If the instruction doesn't load at all, it isn't an invariant load.
1357 if (!mayLoad())
1358 return false;
1359
1360 // If the instruction has lost its memoperands, conservatively assume that
1361 // it may not be an invariant load.
1362 if (memoperands_empty())
1363 return false;
1364
1365 const MachineFrameInfo &MFI = getParent()->getParent()->getFrameInfo();
1366
1367 for (MachineMemOperand *MMO : memoperands()) {
1368 if (!MMO->isUnordered())
1369 // If the memory operand has ordering side effects, we can't move the
1370 // instruction. Such an instruction is technically an invariant load,
1371 // but the caller code would need updated to expect that.
1372 return false;
1373 if (MMO->isStore()) return false;
1374 if (MMO->isInvariant() && MMO->isDereferenceable())
1375 continue;
1376
1377 // A load from a constant PseudoSourceValue is invariant.
1378 if (const PseudoSourceValue *PSV = MMO->getPseudoValue())
1379 if (PSV->isConstant(&MFI))
1380 continue;
1381
1382 if (const Value *V = MMO->getValue()) {
1383 // If we have an AliasAnalysis, ask it whether the memory is constant.
1384 if (AA &&
1385 AA->pointsToConstantMemory(
1386 MemoryLocation(V, MMO->getSize(), MMO->getAAInfo())))
1387 continue;
1388 }
1389
1390 // Otherwise assume conservatively.
1391 return false;
1392 }
1393
1394 // Everything checks out.
1395 return true;
1396}
1397
1398/// isConstantValuePHI - If the specified instruction is a PHI that always
1399/// merges together the same virtual register, return the register, otherwise
1400/// return 0.
1401unsigned MachineInstr::isConstantValuePHI() const {
1402 if (!isPHI())
1403 return 0;
1404 assert(getNumOperands() >= 3 &&((getNumOperands() >= 3 && "It's illegal to have a PHI without source operands"
) ? static_cast<void> (0) : __assert_fail ("getNumOperands() >= 3 && \"It's illegal to have a PHI without source operands\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/MachineInstr.cpp"
, 1405, __PRETTY_FUNCTION__))
1405 "It's illegal to have a PHI without source operands")((getNumOperands() >= 3 && "It's illegal to have a PHI without source operands"
) ? static_cast<void> (0) : __assert_fail ("getNumOperands() >= 3 && \"It's illegal to have a PHI without source operands\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/MachineInstr.cpp"
, 1405, __PRETTY_FUNCTION__))
;
1406
1407 Register Reg = getOperand(1).getReg();
1408 for (unsigned i = 3, e = getNumOperands(); i < e; i += 2)
1409 if (getOperand(i).getReg() != Reg)
1410 return 0;
1411 return Reg;
1412}
1413
1414bool MachineInstr::hasUnmodeledSideEffects() const {
1415 if (hasProperty(MCID::UnmodeledSideEffects))
1416 return true;
1417 if (isInlineAsm()) {
1418 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1419 if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1420 return true;
1421 }
1422
1423 return false;
1424}
1425
1426bool MachineInstr::isLoadFoldBarrier() const {
1427 return mayStore() || isCall() || hasUnmodeledSideEffects();
1428}
1429
1430/// allDefsAreDead - Return true if all the defs of this instruction are dead.
1431///
1432bool MachineInstr::allDefsAreDead() const {
1433 for (const MachineOperand &MO : operands()) {
1434 if (!MO.isReg() || MO.isUse())
1435 continue;
1436 if (!MO.isDead())
1437 return false;
1438 }
1439 return true;
1440}
1441
1442/// copyImplicitOps - Copy implicit register operands from specified
1443/// instruction to this instruction.
1444void MachineInstr::copyImplicitOps(MachineFunction &MF,
1445 const MachineInstr &MI) {
1446 for (unsigned i = MI.getDesc().getNumOperands(), e = MI.getNumOperands();
1447 i != e; ++i) {
1448 const MachineOperand &MO = MI.getOperand(i);
1449 if ((MO.isReg() && MO.isImplicit()) || MO.isRegMask())
1450 addOperand(MF, MO);
1451 }
1452}
1453
1454bool MachineInstr::hasComplexRegisterTies() const {
1455 const MCInstrDesc &MCID = getDesc();
1456 for (unsigned I = 0, E = getNumOperands(); I < E; ++I) {
1457 const auto &Operand = getOperand(I);
1458 if (!Operand.isReg() || Operand.isDef())
1459 // Ignore the defined registers as MCID marks only the uses as tied.
1460 continue;
1461 int ExpectedTiedIdx = MCID.getOperandConstraint(I, MCOI::TIED_TO);
1462 int TiedIdx = Operand.isTied() ? int(findTiedOperandIdx(I)) : -1;
1463 if (ExpectedTiedIdx != TiedIdx)
1464 return true;
1465 }
1466 return false;
1467}
1468
1469LLT MachineInstr::getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes,
1470 const MachineRegisterInfo &MRI) const {
1471 const MachineOperand &Op = getOperand(OpIdx);
1472 if (!Op.isReg())
1473 return LLT{};
1474
1475 if (isVariadic() || OpIdx >= getNumExplicitOperands())
1476 return MRI.getType(Op.getReg());
1477
1478 auto &OpInfo = getDesc().OpInfo[OpIdx];
1479 if (!OpInfo.isGenericType())
1480 return MRI.getType(Op.getReg());
1481
1482 if (PrintedTypes[OpInfo.getGenericTypeIndex()])
1483 return LLT{};
1484
1485 LLT TypeToPrint = MRI.getType(Op.getReg());
1486 // Don't mark the type index printed if it wasn't actually printed: maybe
1487 // another operand with the same type index has an actual type attached:
1488 if (TypeToPrint.isValid())
1489 PrintedTypes.set(OpInfo.getGenericTypeIndex());
1490 return TypeToPrint;
1491}
1492
1493#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
1494LLVM_DUMP_METHOD__attribute__((noinline)) __attribute__((__used__)) void MachineInstr::dump() const {
1495 dbgs() << " ";
1496 print(dbgs());
1497}
1498
1499LLVM_DUMP_METHOD__attribute__((noinline)) __attribute__((__used__)) void MachineInstr::dumprImpl(
1500 const MachineRegisterInfo &MRI, unsigned Depth, unsigned MaxDepth,
1501 SmallPtrSetImpl<const MachineInstr *> &AlreadySeenInstrs) const {
1502 if (Depth >= MaxDepth)
1503 return;
1504 if (!AlreadySeenInstrs.insert(this).second)
1505 return;
1506 // PadToColumn always inserts at least one space.
1507 // Don't mess up the alignment if we don't want any space.
1508 if (Depth)
1509 fdbgs().PadToColumn(Depth * 2);
1510 print(fdbgs());
1511 for (const MachineOperand &MO : operands()) {
1512 if (!MO.isReg() || MO.isDef())
1513 continue;
1514 Register Reg = MO.getReg();
1515 if (Reg.isPhysical())
1516 continue;
1517 const MachineInstr *NewMI = MRI.getUniqueVRegDef(Reg);
1518 if (NewMI == nullptr)
1519 continue;
1520 NewMI->dumprImpl(MRI, Depth + 1, MaxDepth, AlreadySeenInstrs);
1521 }
1522}
1523
1524LLVM_DUMP_METHOD__attribute__((noinline)) __attribute__((__used__)) void MachineInstr::dumpr(const MachineRegisterInfo &MRI,
1525 unsigned MaxDepth) const {
1526 SmallPtrSet<const MachineInstr *, 16> AlreadySeenInstrs;
1527 dumprImpl(MRI, 0, MaxDepth, AlreadySeenInstrs);
1528}
1529#endif
1530
1531void MachineInstr::print(raw_ostream &OS, bool IsStandalone, bool SkipOpers,
1532 bool SkipDebugLoc, bool AddNewLine,
1533 const TargetInstrInfo *TII) const {
1534 const Module *M = nullptr;
1535 const Function *F = nullptr;
1536 if (const MachineFunction *MF = getMFIfAvailable(*this)) {
1537 F = &MF->getFunction();
1538 M = F->getParent();
1539 if (!TII)
1540 TII = MF->getSubtarget().getInstrInfo();
1541 }
1542
1543 ModuleSlotTracker MST(M);
1544 if (F)
1545 MST.incorporateFunction(*F);
1546 print(OS, MST, IsStandalone, SkipOpers, SkipDebugLoc, AddNewLine, TII);
1547}
1548
1549void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST,
1550 bool IsStandalone, bool SkipOpers, bool SkipDebugLoc,
1551 bool AddNewLine, const TargetInstrInfo *TII) const {
1552 // We can be a bit tidier if we know the MachineFunction.
1553 const TargetRegisterInfo *TRI = nullptr;
1554 const MachineRegisterInfo *MRI = nullptr;
1555 const TargetIntrinsicInfo *IntrinsicInfo = nullptr;
1556 tryToGetTargetInfo(*this, TRI, MRI, IntrinsicInfo, TII);
1557
1558 if (isCFIInstruction())
1559 assert(getNumOperands() == 1 && "Expected 1 operand in CFI instruction")((getNumOperands() == 1 && "Expected 1 operand in CFI instruction"
) ? static_cast<void> (0) : __assert_fail ("getNumOperands() == 1 && \"Expected 1 operand in CFI instruction\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/MachineInstr.cpp"
, 1559, __PRETTY_FUNCTION__))
;
1560
1561 SmallBitVector PrintedTypes(8);
1562 bool ShouldPrintRegisterTies = IsStandalone || hasComplexRegisterTies();
1563 auto getTiedOperandIdx = [&](unsigned OpIdx) {
1564 if (!ShouldPrintRegisterTies)
1565 return 0U;
1566 const MachineOperand &MO = getOperand(OpIdx);
1567 if (MO.isReg() && MO.isTied() && !MO.isDef())
1568 return findTiedOperandIdx(OpIdx);
1569 return 0U;
1570 };
1571 unsigned StartOp = 0;
1572 unsigned e = getNumOperands();
1573
1574 // Print explicitly defined operands on the left of an assignment syntax.
1575 while (StartOp < e) {
1576 const MachineOperand &MO = getOperand(StartOp);
1577 if (!MO.isReg() || !MO.isDef() || MO.isImplicit())
1578 break;
1579
1580 if (StartOp != 0)
1581 OS << ", ";
1582
1583 LLT TypeToPrint = MRI ? getTypeToPrint(StartOp, PrintedTypes, *MRI) : LLT{};
1584 unsigned TiedOperandIdx = getTiedOperandIdx(StartOp);
1585 MO.print(OS, MST, TypeToPrint, StartOp, /*PrintDef=*/false, IsStandalone,
1586 ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1587 ++StartOp;
1588 }
1589
1590 if (StartOp != 0)
1591 OS << " = ";
1592
1593 if (getFlag(MachineInstr::FrameSetup))
1594 OS << "frame-setup ";
1595 if (getFlag(MachineInstr::FrameDestroy))
1596 OS << "frame-destroy ";
1597 if (getFlag(MachineInstr::FmNoNans))
1598 OS << "nnan ";
1599 if (getFlag(MachineInstr::FmNoInfs))
1600 OS << "ninf ";
1601 if (getFlag(MachineInstr::FmNsz))
1602 OS << "nsz ";
1603 if (getFlag(MachineInstr::FmArcp))
1604 OS << "arcp ";
1605 if (getFlag(MachineInstr::FmContract))
1606 OS << "contract ";
1607 if (getFlag(MachineInstr::FmAfn))
1608 OS << "afn ";
1609 if (getFlag(MachineInstr::FmReassoc))
1610 OS << "reassoc ";
1611 if (getFlag(MachineInstr::NoUWrap))
1612 OS << "nuw ";
1613 if (getFlag(MachineInstr::NoSWrap))
1614 OS << "nsw ";
1615 if (getFlag(MachineInstr::IsExact))
1616 OS << "exact ";
1617 if (getFlag(MachineInstr::NoFPExcept))
1618 OS << "nofpexcept ";
1619 if (getFlag(MachineInstr::NoMerge))
1620 OS << "nomerge ";
1621
1622 // Print the opcode name.
1623 if (TII)
1624 OS << TII->getName(getOpcode());
1625 else
1626 OS << "UNKNOWN";
1627
1628 if (SkipOpers)
1629 return;
1630
1631 // Print the rest of the operands.
1632 bool FirstOp = true;
1633 unsigned AsmDescOp = ~0u;
1634 unsigned AsmOpCount = 0;
1635
1636 if (isInlineAsm() && e >= InlineAsm::MIOp_FirstOperand) {
1637 // Print asm string.
1638 OS << " ";
1639 const unsigned OpIdx = InlineAsm::MIOp_AsmString;
1640 LLT TypeToPrint = MRI ? getTypeToPrint(OpIdx, PrintedTypes, *MRI) : LLT{};
1641 unsigned TiedOperandIdx = getTiedOperandIdx(OpIdx);
1642 getOperand(OpIdx).print(OS, MST, TypeToPrint, OpIdx, /*PrintDef=*/true, IsStandalone,
1643 ShouldPrintRegisterTies, TiedOperandIdx, TRI,
1644 IntrinsicInfo);
1645
1646 // Print HasSideEffects, MayLoad, MayStore, IsAlignStack
1647 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1648 if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1649 OS << " [sideeffect]";
1650 if (ExtraInfo & InlineAsm::Extra_MayLoad)
1651 OS << " [mayload]";
1652 if (ExtraInfo & InlineAsm::Extra_MayStore)
1653 OS << " [maystore]";
1654 if (ExtraInfo & InlineAsm::Extra_IsConvergent)
1655 OS << " [isconvergent]";
1656 if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
1657 OS << " [alignstack]";
1658 if (getInlineAsmDialect() == InlineAsm::AD_ATT)
1659 OS << " [attdialect]";
1660 if (getInlineAsmDialect() == InlineAsm::AD_Intel)
1661 OS << " [inteldialect]";
1662
1663 StartOp = AsmDescOp = InlineAsm::MIOp_FirstOperand;
1664 FirstOp = false;
1665 }
1666
1667 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
1668 const MachineOperand &MO = getOperand(i);
1669
1670 if (FirstOp) FirstOp = false; else OS << ",";
1671 OS << " ";
1672
1673 if (isDebugValue() && MO.isMetadata()) {
1674 // Pretty print DBG_VALUE instructions.
1675 auto *DIV = dyn_cast<DILocalVariable>(MO.getMetadata());
1676 if (DIV && !DIV->getName().empty())
1677 OS << "!\"" << DIV->getName() << '\"';
1678 else {
1679 LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};
1680 unsigned TiedOperandIdx = getTiedOperandIdx(i);
1681 MO.print(OS, MST, TypeToPrint, i, /*PrintDef=*/true, IsStandalone,
1682 ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1683 }
1684 } else if (isDebugLabel() && MO.isMetadata()) {
1685 // Pretty print DBG_LABEL instructions.
1686 auto *DIL = dyn_cast<DILabel>(MO.getMetadata());
1687 if (DIL && !DIL->getName().empty())
1688 OS << "\"" << DIL->getName() << '\"';
1689 else {
1690 LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};
1691 unsigned TiedOperandIdx = getTiedOperandIdx(i);
1692 MO.print(OS, MST, TypeToPrint, i, /*PrintDef=*/true, IsStandalone,
1693 ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1694 }
1695 } else if (i == AsmDescOp && MO.isImm()) {
1696 // Pretty print the inline asm operand descriptor.
1697 OS << '$' << AsmOpCount++;
1698 unsigned Flag = MO.getImm();
1699 OS << ":[";
1700 OS << InlineAsm::getKindName(InlineAsm::getKind(Flag));
1701
1702 unsigned RCID = 0;
1703 if (!InlineAsm::isImmKind(Flag) && !InlineAsm::isMemKind(Flag) &&
1704 InlineAsm::hasRegClassConstraint(Flag, RCID)) {
1705 if (TRI) {
1706 OS << ':' << TRI->getRegClassName(TRI->getRegClass(RCID));
1707 } else
1708 OS << ":RC" << RCID;
1709 }
1710
1711 if (InlineAsm::isMemKind(Flag)) {
1712 unsigned MCID = InlineAsm::getMemoryConstraintID(Flag);
1713 OS << ":" << InlineAsm::getMemConstraintName(MCID);
1714 }
1715
1716 unsigned TiedTo = 0;
1717 if (InlineAsm::isUseOperandTiedToDef(Flag, TiedTo))
1718 OS << " tiedto:$" << TiedTo;
1719
1720 OS << ']';
1721
1722 // Compute the index of the next operand descriptor.
1723 AsmDescOp += 1 + InlineAsm::getNumOperandRegisters(Flag);
1724 } else {
1725 LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};
1726 unsigned TiedOperandIdx = getTiedOperandIdx(i);
1727 if (MO.isImm() && isOperandSubregIdx(i))
1728 MachineOperand::printSubRegIdx(OS, MO.getImm(), TRI);
1729 else
1730 MO.print(OS, MST, TypeToPrint, i, /*PrintDef=*/true, IsStandalone,
1731 ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1732 }
1733 }
1734
1735 // Print any optional symbols attached to this instruction as-if they were
1736 // operands.
1737 if (MCSymbol *PreInstrSymbol = getPreInstrSymbol()) {
1738 if (!FirstOp) {
1739 FirstOp = false;
1740 OS << ',';
1741 }
1742 OS << " pre-instr-symbol ";
1743 MachineOperand::printSymbol(OS, *PreInstrSymbol);
1744 }
1745 if (MCSymbol *PostInstrSymbol = getPostInstrSymbol()) {
1746 if (!FirstOp) {
1747 FirstOp = false;
1748 OS << ',';
1749 }
1750 OS << " post-instr-symbol ";
1751 MachineOperand::printSymbol(OS, *PostInstrSymbol);
1752 }
1753 if (MDNode *HeapAllocMarker = getHeapAllocMarker()) {
1754 if (!FirstOp) {
1755 FirstOp = false;
1756 OS << ',';
1757 }
1758 OS << " heap-alloc-marker ";
1759 HeapAllocMarker->printAsOperand(OS, MST);
1760 }
1761
1762 if (DebugInstrNum) {
1763 if (!FirstOp)
1764 OS << ",";
1765 OS << " debug-instr-number " << DebugInstrNum;
1766 }
1767
1768 if (!SkipDebugLoc) {
1769 if (const DebugLoc &DL = getDebugLoc()) {
1770 if (!FirstOp)
1771 OS << ',';
1772 OS << " debug-location ";
1773 DL->printAsOperand(OS, MST);
1774 }
1775 }
1776
1777 if (!memoperands_empty()) {
1778 SmallVector<StringRef, 0> SSNs;
1779 const LLVMContext *Context = nullptr;
1780 std::unique_ptr<LLVMContext> CtxPtr;
1781 const MachineFrameInfo *MFI = nullptr;
1782 if (const MachineFunction *MF = getMFIfAvailable(*this)) {
1783 MFI = &MF->getFrameInfo();
1784 Context = &MF->getFunction().getContext();
1785 } else {
1786 CtxPtr = std::make_unique<LLVMContext>();
1787 Context = CtxPtr.get();
1788 }
1789
1790 OS << " :: ";
1791 bool NeedComma = false;
1792 for (const MachineMemOperand *Op : memoperands()) {
1793 if (NeedComma)
1794 OS << ", ";
1795 Op->print(OS, MST, SSNs, *Context, MFI, TII);
1796 NeedComma = true;
1797 }
1798 }
1799
1800 if (SkipDebugLoc)
1801 return;
1802
1803 bool HaveSemi = false;
1804
1805 // Print debug location information.
1806 if (const DebugLoc &DL = getDebugLoc()) {
1807 if (!HaveSemi) {
1808 OS << ';';
1809 HaveSemi = true;
1810 }
1811 OS << ' ';
1812 DL.print(OS);
1813 }
1814
1815 // Print extra comments for DEBUG_VALUE.
1816 if (isDebugValue() && getDebugVariableOp().isMetadata()) {
1817 if (!HaveSemi) {
1818 OS << ";";
1819 HaveSemi = true;
Value stored to 'HaveSemi' is never read
1820 }
1821 auto *DV = getDebugVariable();
1822 OS << " line no:" << DV->getLine();
1823 if (isIndirectDebugValue())
1824 OS << " indirect";
1825 }
1826 // TODO: DBG_LABEL
1827
1828 if (AddNewLine)
1829 OS << '\n';
1830}
1831
1832bool MachineInstr::addRegisterKilled(Register IncomingReg,
1833 const TargetRegisterInfo *RegInfo,
1834 bool AddIfNotFound) {
1835 bool isPhysReg = Register::isPhysicalRegister(IncomingReg);
1836 bool hasAliases = isPhysReg &&
1837 MCRegAliasIterator(IncomingReg, RegInfo, false).isValid();
1838 bool Found = false;
1839 SmallVector<unsigned,4> DeadOps;
1840 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1841 MachineOperand &MO = getOperand(i);
1842 if (!MO.isReg() || !MO.isUse() || MO.isUndef())
1843 continue;
1844
1845 // DEBUG_VALUE nodes do not contribute to code generation and should
1846 // always be ignored. Failure to do so may result in trying to modify
1847 // KILL flags on DEBUG_VALUE nodes.
1848 if (MO.isDebug())
1849 continue;
1850
1851 Register Reg = MO.getReg();
1852 if (!Reg)
1853 continue;
1854
1855 if (Reg == IncomingReg) {
1856 if (!Found) {
1857 if (MO.isKill())
1858 // The register is already marked kill.
1859 return true;
1860 if (isPhysReg && isRegTiedToDefOperand(i))
1861 // Two-address uses of physregs must not be marked kill.
1862 return true;
1863 MO.setIsKill();
1864 Found = true;
1865 }
1866 } else if (hasAliases && MO.isKill() && Register::isPhysicalRegister(Reg)) {
1867 // A super-register kill already exists.
1868 if (RegInfo->isSuperRegister(IncomingReg, Reg))
1869 return true;
1870 if (RegInfo->isSubRegister(IncomingReg, Reg))
1871 DeadOps.push_back(i);
1872 }
1873 }
1874
1875 // Trim unneeded kill operands.
1876 while (!DeadOps.empty()) {
1877 unsigned OpIdx = DeadOps.back();
1878 if (getOperand(OpIdx).isImplicit() &&
1879 (!isInlineAsm() || findInlineAsmFlagIdx(OpIdx) < 0))
1880 RemoveOperand(OpIdx);
1881 else
1882 getOperand(OpIdx).setIsKill(false);
1883 DeadOps.pop_back();
1884 }
1885
1886 // If not found, this means an alias of one of the operands is killed. Add a
1887 // new implicit operand if required.
1888 if (!Found && AddIfNotFound) {
1889 addOperand(MachineOperand::CreateReg(IncomingReg,
1890 false /*IsDef*/,
1891 true /*IsImp*/,
1892 true /*IsKill*/));
1893 return true;
1894 }
1895 return Found;
1896}
1897
1898void MachineInstr::clearRegisterKills(Register Reg,
1899 const TargetRegisterInfo *RegInfo) {
1900 if (!Register::isPhysicalRegister(Reg))
1901 RegInfo = nullptr;
1902 for (MachineOperand &MO : operands()) {
1903 if (!MO.isReg() || !MO.isUse() || !MO.isKill())
1904 continue;
1905 Register OpReg = MO.getReg();
1906 if ((RegInfo && RegInfo->regsOverlap(Reg, OpReg)) || Reg == OpReg)
1907 MO.setIsKill(false);
1908 }
1909}
1910
1911bool MachineInstr::addRegisterDead(Register Reg,
1912 const TargetRegisterInfo *RegInfo,
1913 bool AddIfNotFound) {
1914 bool isPhysReg = Register::isPhysicalRegister(Reg);
1915 bool hasAliases = isPhysReg &&
1916 MCRegAliasIterator(Reg, RegInfo, false).isValid();
1917 bool Found = false;
1918 SmallVector<unsigned,4> DeadOps;
1919 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1920 MachineOperand &MO = getOperand(i);
1921 if (!MO.isReg() || !MO.isDef())
1922 continue;
1923 Register MOReg = MO.getReg();
1924 if (!MOReg)
1925 continue;
1926
1927 if (MOReg == Reg) {
1928 MO.setIsDead();
1929 Found = true;
1930 } else if (hasAliases && MO.isDead() &&
1931 Register::isPhysicalRegister(MOReg)) {
1932 // There exists a super-register that's marked dead.
1933 if (RegInfo->isSuperRegister(Reg, MOReg))
1934 return true;
1935 if (RegInfo->isSubRegister(Reg, MOReg))
1936 DeadOps.push_back(i);
1937 }
1938 }
1939
1940 // Trim unneeded dead operands.
1941 while (!DeadOps.empty()) {
1942 unsigned OpIdx = DeadOps.back();
1943 if (getOperand(OpIdx).isImplicit() &&
1944 (!isInlineAsm() || findInlineAsmFlagIdx(OpIdx) < 0))
1945 RemoveOperand(OpIdx);
1946 else
1947 getOperand(OpIdx).setIsDead(false);
1948 DeadOps.pop_back();
1949 }
1950
1951 // If not found, this means an alias of one of the operands is dead. Add a
1952 // new implicit operand if required.
1953 if (Found || !AddIfNotFound)
1954 return Found;
1955
1956 addOperand(MachineOperand::CreateReg(Reg,
1957 true /*IsDef*/,
1958 true /*IsImp*/,
1959 false /*IsKill*/,
1960 true /*IsDead*/));
1961 return true;
1962}
1963
1964void MachineInstr::clearRegisterDeads(Register Reg) {
1965 for (MachineOperand &MO : operands()) {
1966 if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg)
1967 continue;
1968 MO.setIsDead(false);
1969 }
1970}
1971
1972void MachineInstr::setRegisterDefReadUndef(Register Reg, bool IsUndef) {
1973 for (MachineOperand &MO : operands()) {
1974 if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg || MO.getSubReg() == 0)
1975 continue;
1976 MO.setIsUndef(IsUndef);
1977 }
1978}
1979
1980void MachineInstr::addRegisterDefined(Register Reg,
1981 const TargetRegisterInfo *RegInfo) {
1982 if (Register::isPhysicalRegister(Reg)) {
1983 MachineOperand *MO = findRegisterDefOperand(Reg, false, false, RegInfo);
1984 if (MO)
1985 return;
1986 } else {
1987 for (const MachineOperand &MO : operands()) {
1988 if (MO.isReg() && MO.getReg() == Reg && MO.isDef() &&
1989 MO.getSubReg() == 0)
1990 return;
1991 }
1992 }
1993 addOperand(MachineOperand::CreateReg(Reg,
1994 true /*IsDef*/,
1995 true /*IsImp*/));
1996}
1997
1998void MachineInstr::setPhysRegsDeadExcept(ArrayRef<Register> UsedRegs,
1999 const TargetRegisterInfo &TRI) {
2000 bool HasRegMask = false;
2001 for (MachineOperand &MO : operands()) {
2002 if (MO.isRegMask()) {
2003 HasRegMask = true;
2004 continue;
2005 }
2006 if (!MO.isReg() || !MO.isDef()) continue;
2007 Register Reg = MO.getReg();
2008 if (!Reg.isPhysical())
2009 continue;
2010 // If there are no uses, including partial uses, the def is dead.
2011 if (llvm::none_of(UsedRegs,
2012 [&](MCRegister Use) { return TRI.regsOverlap(Use, Reg); }))
2013 MO.setIsDead();
2014 }
2015
2016 // This is a call with a register mask operand.
2017 // Mask clobbers are always dead, so add defs for the non-dead defines.
2018 if (HasRegMask)
2019 for (ArrayRef<Register>::iterator I = UsedRegs.begin(), E = UsedRegs.end();
2020 I != E; ++I)
2021 addRegisterDefined(*I, &TRI);
2022}
2023
2024unsigned
2025MachineInstrExpressionTrait::getHashValue(const MachineInstr* const &MI) {
2026 // Build up a buffer of hash code components.
2027 SmallVector<size_t, 16> HashComponents;
2028 HashComponents.reserve(MI->getNumOperands() + 1);
2029 HashComponents.push_back(MI->getOpcode());
2030 for (const MachineOperand &MO : MI->operands()) {
2031 if (MO.isReg() && MO.isDef() && Register::isVirtualRegister(MO.getReg()))
2032 continue; // Skip virtual register defs.
2033
2034 HashComponents.push_back(hash_value(MO));
2035 }
2036 return hash_combine_range(HashComponents.begin(), HashComponents.end());
2037}
2038
2039void MachineInstr::emitError(StringRef Msg) const {
2040 // Find the source location cookie.
2041 unsigned LocCookie = 0;
2042 const MDNode *LocMD = nullptr;
2043 for (unsigned i = getNumOperands(); i != 0; --i) {
2044 if (getOperand(i-1).isMetadata() &&
2045 (LocMD = getOperand(i-1).getMetadata()) &&
2046 LocMD->getNumOperands() != 0) {
2047 if (const ConstantInt *CI =
2048 mdconst::dyn_extract<ConstantInt>(LocMD->getOperand(0))) {
2049 LocCookie = CI->getZExtValue();
2050 break;
2051 }
2052 }
2053 }
2054
2055 if (const MachineBasicBlock *MBB = getParent())
2056 if (const MachineFunction *MF = MBB->getParent())
2057 return MF->getMMI().getModule()->getContext().emitError(LocCookie, Msg);
2058 report_fatal_error(Msg);
2059}
2060
2061MachineInstrBuilder llvm::BuildMI(MachineFunction &MF, const DebugLoc &DL,
2062 const MCInstrDesc &MCID, bool IsIndirect,
2063 Register Reg, const MDNode *Variable,
2064 const MDNode *Expr) {
2065 assert(isa<DILocalVariable>(Variable) && "not a variable")((isa<DILocalVariable>(Variable) && "not a variable"
) ? static_cast<void> (0) : __assert_fail ("isa<DILocalVariable>(Variable) && \"not a variable\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/MachineInstr.cpp"
, 2065, __PRETTY_FUNCTION__))
;
2066 assert(cast<DIExpression>(Expr)->isValid() && "not an expression")((cast<DIExpression>(Expr)->isValid() && "not an expression"
) ? static_cast<void> (0) : __assert_fail ("cast<DIExpression>(Expr)->isValid() && \"not an expression\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/MachineInstr.cpp"
, 2066, __PRETTY_FUNCTION__))
;
2067 assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&((cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic
(DL) && "Expected inlined-at fields to agree") ? static_cast
<void> (0) : __assert_fail ("cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) && \"Expected inlined-at fields to agree\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/MachineInstr.cpp"
, 2068, __PRETTY_FUNCTION__))
2068 "Expected inlined-at fields to agree")((cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic
(DL) && "Expected inlined-at fields to agree") ? static_cast
<void> (0) : __assert_fail ("cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) && \"Expected inlined-at fields to agree\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/MachineInstr.cpp"
, 2068, __PRETTY_FUNCTION__))
;
2069 auto MIB = BuildMI(MF, DL, MCID).addReg(Reg, RegState::Debug);
2070 if (IsIndirect)
2071 MIB.addImm(0U);
2072 else
2073 MIB.addReg(0U, RegState::Debug);
2074 return MIB.addMetadata(Variable).addMetadata(Expr);
2075}
2076
2077MachineInstrBuilder llvm::BuildMI(MachineFunction &MF, const DebugLoc &DL,
2078 const MCInstrDesc &MCID, bool IsIndirect,
2079 MachineOperand &MO, const MDNode *Variable,
2080 const MDNode *Expr) {
2081 assert(isa<DILocalVariable>(Variable) && "not a variable")((isa<DILocalVariable>(Variable) && "not a variable"
) ? static_cast<void> (0) : __assert_fail ("isa<DILocalVariable>(Variable) && \"not a variable\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/MachineInstr.cpp"
, 2081, __PRETTY_FUNCTION__))
;
2082 assert(cast<DIExpression>(Expr)->isValid() && "not an expression")((cast<DIExpression>(Expr)->isValid() && "not an expression"
) ? static_cast<void> (0) : __assert_fail ("cast<DIExpression>(Expr)->isValid() && \"not an expression\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/MachineInstr.cpp"
, 2082, __PRETTY_FUNCTION__))
;
2083 assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&((cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic
(DL) && "Expected inlined-at fields to agree") ? static_cast
<void> (0) : __assert_fail ("cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) && \"Expected inlined-at fields to agree\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/MachineInstr.cpp"
, 2084, __PRETTY_FUNCTION__))
2084 "Expected inlined-at fields to agree")((cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic
(DL) && "Expected inlined-at fields to agree") ? static_cast
<void> (0) : __assert_fail ("cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) && \"Expected inlined-at fields to agree\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/MachineInstr.cpp"
, 2084, __PRETTY_FUNCTION__))
;
2085 if (MO.isReg())
2086 return BuildMI(MF, DL, MCID, IsIndirect, MO.getReg(), Variable, Expr);
2087
2088 auto MIB = BuildMI(MF, DL, MCID).add(MO);
2089 if (IsIndirect)
2090 MIB.addImm(0U);
2091 else
2092 MIB.addReg(0U, RegState::Debug);
2093 return MIB.addMetadata(Variable).addMetadata(Expr);
2094 }
2095
2096MachineInstrBuilder llvm::BuildMI(MachineBasicBlock &BB,
2097 MachineBasicBlock::iterator I,
2098 const DebugLoc &DL, const MCInstrDesc &MCID,
2099 bool IsIndirect, Register Reg,
2100 const MDNode *Variable, const MDNode *Expr) {
2101 MachineFunction &MF = *BB.getParent();
2102 MachineInstr *MI = BuildMI(MF, DL, MCID, IsIndirect, Reg, Variable, Expr);
2103 BB.insert(I, MI);
2104 return MachineInstrBuilder(MF, MI);
2105}
2106
2107MachineInstrBuilder llvm::BuildMI(MachineBasicBlock &BB,
2108 MachineBasicBlock::iterator I,
2109 const DebugLoc &DL, const MCInstrDesc &MCID,
2110 bool IsIndirect, MachineOperand &MO,
2111 const MDNode *Variable, const MDNode *Expr) {
2112 MachineFunction &MF = *BB.getParent();
2113 MachineInstr *MI = BuildMI(MF, DL, MCID, IsIndirect, MO, Variable, Expr);
2114 BB.insert(I, MI);
2115 return MachineInstrBuilder(MF, *MI);
2116}
2117
2118/// Compute the new DIExpression to use with a DBG_VALUE for a spill slot.
2119/// This prepends DW_OP_deref when spilling an indirect DBG_VALUE.
2120static const DIExpression *computeExprForSpill(const MachineInstr &MI) {
2121 assert(MI.getOperand(0).isReg() && "can't spill non-register")((MI.getOperand(0).isReg() && "can't spill non-register"
) ? static_cast<void> (0) : __assert_fail ("MI.getOperand(0).isReg() && \"can't spill non-register\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/MachineInstr.cpp"
, 2121, __PRETTY_FUNCTION__))
;
2122 assert(MI.getDebugVariable()->isValidLocationForIntrinsic(MI.getDebugLoc()) &&((MI.getDebugVariable()->isValidLocationForIntrinsic(MI.getDebugLoc
()) && "Expected inlined-at fields to agree") ? static_cast
<void> (0) : __assert_fail ("MI.getDebugVariable()->isValidLocationForIntrinsic(MI.getDebugLoc()) && \"Expected inlined-at fields to agree\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/MachineInstr.cpp"
, 2123, __PRETTY_FUNCTION__))
2123 "Expected inlined-at fields to agree")((MI.getDebugVariable()->isValidLocationForIntrinsic(MI.getDebugLoc
()) && "Expected inlined-at fields to agree") ? static_cast
<void> (0) : __assert_fail ("MI.getDebugVariable()->isValidLocationForIntrinsic(MI.getDebugLoc()) && \"Expected inlined-at fields to agree\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/MachineInstr.cpp"
, 2123, __PRETTY_FUNCTION__))
;
2124
2125 const DIExpression *Expr = MI.getDebugExpression();
2126 if (MI.isIndirectDebugValue()) {
2127 assert(MI.getDebugOffset().getImm() == 0 &&((MI.getDebugOffset().getImm() == 0 && "DBG_VALUE with nonzero offset"
) ? static_cast<void> (0) : __assert_fail ("MI.getDebugOffset().getImm() == 0 && \"DBG_VALUE with nonzero offset\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/MachineInstr.cpp"
, 2128, __PRETTY_FUNCTION__))
2128 "DBG_VALUE with nonzero offset")((MI.getDebugOffset().getImm() == 0 && "DBG_VALUE with nonzero offset"
) ? static_cast<void> (0) : __assert_fail ("MI.getDebugOffset().getImm() == 0 && \"DBG_VALUE with nonzero offset\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/MachineInstr.cpp"
, 2128, __PRETTY_FUNCTION__))
;
2129 Expr = DIExpression::prepend(Expr, DIExpression::DerefBefore);
2130 }
2131 return Expr;
2132}
2133
2134MachineInstr *llvm::buildDbgValueForSpill(MachineBasicBlock &BB,
2135 MachineBasicBlock::iterator I,
2136 const MachineInstr &Orig,
2137 int FrameIndex) {
2138 const DIExpression *Expr = computeExprForSpill(Orig);
2139 return BuildMI(BB, I, Orig.getDebugLoc(), Orig.getDesc())
2140 .addFrameIndex(FrameIndex)
2141 .addImm(0U)
2142 .addMetadata(Orig.getDebugVariable())
2143 .addMetadata(Expr);
2144}
2145
2146void llvm::updateDbgValueForSpill(MachineInstr &Orig, int FrameIndex) {
2147 const DIExpression *Expr = computeExprForSpill(Orig);
2148 Orig.getDebugOperand(0).ChangeToFrameIndex(FrameIndex);
2149 Orig.getDebugOffset().ChangeToImmediate(0U);
2150 Orig.getDebugExpressionOp().setMetadata(Expr);
2151}
2152
2153void MachineInstr::collectDebugValues(
2154 SmallVectorImpl<MachineInstr *> &DbgValues) {
2155 MachineInstr &MI = *this;
2156 if (!MI.getOperand(0).isReg())
2157 return;
2158
2159 MachineBasicBlock::iterator DI = MI; ++DI;
2160 for (MachineBasicBlock::iterator DE = MI.getParent()->end();
2161 DI != DE; ++DI) {
2162 if (!DI->isDebugValue())
2163 return;
2164 if (DI->getDebugOperandForReg(MI.getOperand(0).getReg()))
2165 DbgValues.push_back(&*DI);
2166 }
2167}
2168
2169void MachineInstr::changeDebugValuesDefReg(Register Reg) {
2170 // Collect matching debug values.
2171 SmallVector<MachineInstr *, 2> DbgValues;
2172
2173 if (!getOperand(0).isReg())
2174 return;
2175
2176 Register DefReg = getOperand(0).getReg();
2177 auto *MRI = getRegInfo();
2178 for (auto &MO : MRI->use_operands(DefReg)) {
2179 auto *DI = MO.getParent();
2180 if (!DI->isDebugValue())
2181 continue;
2182 if (DI->getDebugOperandForReg(DefReg)) {
2183 DbgValues.push_back(DI);
2184 }
2185 }
2186
2187 // Propagate Reg to debug value instructions.
2188 for (auto *DBI : DbgValues)
2189 DBI->getDebugOperandForReg(DefReg)->setReg(Reg);
2190}
2191
2192using MMOList = SmallVector<const MachineMemOperand *, 2>;
2193
2194static unsigned getSpillSlotSize(const MMOList &Accesses,
2195 const MachineFrameInfo &MFI) {
2196 unsigned Size = 0;
2197 for (auto A : Accesses)
2198 if (MFI.isSpillSlotObjectIndex(
2199 cast<FixedStackPseudoSourceValue>(A->getPseudoValue())
2200 ->getFrameIndex()))
2201 Size += A->getSize();
2202 return Size;
2203}
2204
2205Optional<unsigned>
2206MachineInstr::getSpillSize(const TargetInstrInfo *TII) const {
2207 int FI;
2208 if (TII->isStoreToStackSlotPostFE(*this, FI)) {
2209 const MachineFrameInfo &MFI = getMF()->getFrameInfo();
2210 if (MFI.isSpillSlotObjectIndex(FI))
2211 return (*memoperands_begin())->getSize();
2212 }
2213 return None;
2214}
2215
2216Optional<unsigned>
2217MachineInstr::getFoldedSpillSize(const TargetInstrInfo *TII) const {
2218 MMOList Accesses;
2219 if (TII->hasStoreToStackSlot(*this, Accesses))
2220 return getSpillSlotSize(Accesses, getMF()->getFrameInfo());
2221 return None;
2222}
2223
2224Optional<unsigned>
2225MachineInstr::getRestoreSize(const TargetInstrInfo *TII) const {
2226 int FI;
2227 if (TII->isLoadFromStackSlotPostFE(*this, FI)) {
2228 const MachineFrameInfo &MFI = getMF()->getFrameInfo();
2229 if (MFI.isSpillSlotObjectIndex(FI))
2230 return (*memoperands_begin())->getSize();
2231 }
2232 return None;
2233}
2234
2235Optional<unsigned>
2236MachineInstr::getFoldedRestoreSize(const TargetInstrInfo *TII) const {
2237 MMOList Accesses;
2238 if (TII->hasLoadFromStackSlot(*this, Accesses))
2239 return getSpillSlotSize(Accesses, getMF()->getFrameInfo());
2240 return None;
2241}
2242
2243unsigned MachineInstr::getDebugInstrNum() {
2244 if (DebugInstrNum == 0)
2245 DebugInstrNum = getParent()->getParent()->getNewDebugInstrNum();
2246 return DebugInstrNum;
2247}