Bug Summary

File:llvm/lib/CodeGen/MachineInstr.cpp
Warning:line 1863, column 7
Value stored to 'HaveSemi' is never read

Annotated Source Code

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clang -cc1 -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name MachineInstr.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mframe-pointer=none -fmath-errno -fno-rounding-math -mconstructor-aliases -munwind-tables -target-cpu x86-64 -tune-cpu generic -fno-split-dwarf-inlining -debugger-tuning=gdb -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-12/lib/clang/12.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/build-llvm/lib/CodeGen -I /build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen -I /build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/build-llvm/include -I /build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0/backward -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-12/lib/clang/12.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++14 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/build-llvm/lib/CodeGen -fdebug-prefix-map=/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d=. -ferror-limit 19 -fvisibility-inlines-hidden -stack-protector 2 -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -o /tmp/scan-build-2020-11-29-190409-37574-1 -x c++ /build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/MachineInstr.cpp
1//===- lib/CodeGen/MachineInstr.cpp ---------------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// Methods common to all machine instructions.
10//
11//===----------------------------------------------------------------------===//
12
13#include "llvm/CodeGen/MachineInstr.h"
14#include "llvm/ADT/APFloat.h"
15#include "llvm/ADT/ArrayRef.h"
16#include "llvm/ADT/FoldingSet.h"
17#include "llvm/ADT/Hashing.h"
18#include "llvm/ADT/None.h"
19#include "llvm/ADT/STLExtras.h"
20#include "llvm/ADT/SmallBitVector.h"
21#include "llvm/ADT/SmallString.h"
22#include "llvm/ADT/SmallVector.h"
23#include "llvm/Analysis/AliasAnalysis.h"
24#include "llvm/Analysis/Loads.h"
25#include "llvm/Analysis/MemoryLocation.h"
26#include "llvm/CodeGen/GlobalISel/RegisterBank.h"
27#include "llvm/CodeGen/MachineBasicBlock.h"
28#include "llvm/CodeGen/MachineFrameInfo.h"
29#include "llvm/CodeGen/MachineFunction.h"
30#include "llvm/CodeGen/MachineInstrBuilder.h"
31#include "llvm/CodeGen/MachineInstrBundle.h"
32#include "llvm/CodeGen/MachineMemOperand.h"
33#include "llvm/CodeGen/MachineModuleInfo.h"
34#include "llvm/CodeGen/MachineOperand.h"
35#include "llvm/CodeGen/MachineRegisterInfo.h"
36#include "llvm/CodeGen/PseudoSourceValue.h"
37#include "llvm/CodeGen/StackMaps.h"
38#include "llvm/CodeGen/TargetInstrInfo.h"
39#include "llvm/CodeGen/TargetRegisterInfo.h"
40#include "llvm/CodeGen/TargetSubtargetInfo.h"
41#include "llvm/Config/llvm-config.h"
42#include "llvm/IR/Constants.h"
43#include "llvm/IR/DebugInfoMetadata.h"
44#include "llvm/IR/DebugLoc.h"
45#include "llvm/IR/DerivedTypes.h"
46#include "llvm/IR/Function.h"
47#include "llvm/IR/InlineAsm.h"
48#include "llvm/IR/InstrTypes.h"
49#include "llvm/IR/Intrinsics.h"
50#include "llvm/IR/LLVMContext.h"
51#include "llvm/IR/Metadata.h"
52#include "llvm/IR/Module.h"
53#include "llvm/IR/ModuleSlotTracker.h"
54#include "llvm/IR/Operator.h"
55#include "llvm/IR/Type.h"
56#include "llvm/IR/Value.h"
57#include "llvm/MC/MCInstrDesc.h"
58#include "llvm/MC/MCRegisterInfo.h"
59#include "llvm/MC/MCSymbol.h"
60#include "llvm/Support/Casting.h"
61#include "llvm/Support/CommandLine.h"
62#include "llvm/Support/Compiler.h"
63#include "llvm/Support/Debug.h"
64#include "llvm/Support/ErrorHandling.h"
65#include "llvm/Support/FormattedStream.h"
66#include "llvm/Support/LowLevelTypeImpl.h"
67#include "llvm/Support/MathExtras.h"
68#include "llvm/Support/raw_ostream.h"
69#include "llvm/Target/TargetIntrinsicInfo.h"
70#include "llvm/Target/TargetMachine.h"
71#include <algorithm>
72#include <cassert>
73#include <cstddef>
74#include <cstdint>
75#include <cstring>
76#include <iterator>
77#include <utility>
78
79using namespace llvm;
80
81static const MachineFunction *getMFIfAvailable(const MachineInstr &MI) {
82 if (const MachineBasicBlock *MBB = MI.getParent())
83 if (const MachineFunction *MF = MBB->getParent())
84 return MF;
85 return nullptr;
86}
87
88// Try to crawl up to the machine function and get TRI and IntrinsicInfo from
89// it.
90static void tryToGetTargetInfo(const MachineInstr &MI,
91 const TargetRegisterInfo *&TRI,
92 const MachineRegisterInfo *&MRI,
93 const TargetIntrinsicInfo *&IntrinsicInfo,
94 const TargetInstrInfo *&TII) {
95
96 if (const MachineFunction *MF = getMFIfAvailable(MI)) {
97 TRI = MF->getSubtarget().getRegisterInfo();
98 MRI = &MF->getRegInfo();
99 IntrinsicInfo = MF->getTarget().getIntrinsicInfo();
100 TII = MF->getSubtarget().getInstrInfo();
101 }
102}
103
104void MachineInstr::addImplicitDefUseOperands(MachineFunction &MF) {
105 if (MCID->ImplicitDefs)
106 for (const MCPhysReg *ImpDefs = MCID->getImplicitDefs(); *ImpDefs;
107 ++ImpDefs)
108 addOperand(MF, MachineOperand::CreateReg(*ImpDefs, true, true));
109 if (MCID->ImplicitUses)
110 for (const MCPhysReg *ImpUses = MCID->getImplicitUses(); *ImpUses;
111 ++ImpUses)
112 addOperand(MF, MachineOperand::CreateReg(*ImpUses, false, true));
113}
114
115/// MachineInstr ctor - This constructor creates a MachineInstr and adds the
116/// implicit operands. It reserves space for the number of operands specified by
117/// the MCInstrDesc.
118MachineInstr::MachineInstr(MachineFunction &MF, const MCInstrDesc &tid,
119 DebugLoc dl, bool NoImp)
120 : MCID(&tid), debugLoc(std::move(dl)), DebugInstrNum(0) {
121 assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor")((debugLoc.hasTrivialDestructor() && "Expected trivial destructor"
) ? static_cast<void> (0) : __assert_fail ("debugLoc.hasTrivialDestructor() && \"Expected trivial destructor\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/MachineInstr.cpp"
, 121, __PRETTY_FUNCTION__))
;
122
123 // Reserve space for the expected number of operands.
124 if (unsigned NumOps = MCID->getNumOperands() +
125 MCID->getNumImplicitDefs() + MCID->getNumImplicitUses()) {
126 CapOperands = OperandCapacity::get(NumOps);
127 Operands = MF.allocateOperandArray(CapOperands);
128 }
129
130 if (!NoImp)
131 addImplicitDefUseOperands(MF);
132}
133
134/// MachineInstr ctor - Copies MachineInstr arg exactly.
135/// Does not copy the number from debug instruction numbering, to preserve
136/// uniqueness.
137MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
138 : MCID(&MI.getDesc()), Info(MI.Info), debugLoc(MI.getDebugLoc()),
139 DebugInstrNum(0) {
140 assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor")((debugLoc.hasTrivialDestructor() && "Expected trivial destructor"
) ? static_cast<void> (0) : __assert_fail ("debugLoc.hasTrivialDestructor() && \"Expected trivial destructor\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/MachineInstr.cpp"
, 140, __PRETTY_FUNCTION__))
;
141
142 CapOperands = OperandCapacity::get(MI.getNumOperands());
143 Operands = MF.allocateOperandArray(CapOperands);
144
145 // Copy operands.
146 for (const MachineOperand &MO : MI.operands())
147 addOperand(MF, MO);
148
149 // Copy all the sensible flags.
150 setFlags(MI.Flags);
151}
152
153void MachineInstr::moveBefore(MachineInstr *MovePos) {
154 MovePos->getParent()->splice(MovePos, getParent(), getIterator());
155}
156
157/// getRegInfo - If this instruction is embedded into a MachineFunction,
158/// return the MachineRegisterInfo object for the current function, otherwise
159/// return null.
160MachineRegisterInfo *MachineInstr::getRegInfo() {
161 if (MachineBasicBlock *MBB = getParent())
162 return &MBB->getParent()->getRegInfo();
163 return nullptr;
164}
165
166/// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
167/// this instruction from their respective use lists. This requires that the
168/// operands already be on their use lists.
169void MachineInstr::RemoveRegOperandsFromUseLists(MachineRegisterInfo &MRI) {
170 for (MachineOperand &MO : operands())
171 if (MO.isReg())
172 MRI.removeRegOperandFromUseList(&MO);
173}
174
175/// AddRegOperandsToUseLists - Add all of the register operands in
176/// this instruction from their respective use lists. This requires that the
177/// operands not be on their use lists yet.
178void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &MRI) {
179 for (MachineOperand &MO : operands())
180 if (MO.isReg())
181 MRI.addRegOperandToUseList(&MO);
182}
183
184void MachineInstr::addOperand(const MachineOperand &Op) {
185 MachineBasicBlock *MBB = getParent();
186 assert(MBB && "Use MachineInstrBuilder to add operands to dangling instrs")((MBB && "Use MachineInstrBuilder to add operands to dangling instrs"
) ? static_cast<void> (0) : __assert_fail ("MBB && \"Use MachineInstrBuilder to add operands to dangling instrs\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/MachineInstr.cpp"
, 186, __PRETTY_FUNCTION__))
;
187 MachineFunction *MF = MBB->getParent();
188 assert(MF && "Use MachineInstrBuilder to add operands to dangling instrs")((MF && "Use MachineInstrBuilder to add operands to dangling instrs"
) ? static_cast<void> (0) : __assert_fail ("MF && \"Use MachineInstrBuilder to add operands to dangling instrs\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/MachineInstr.cpp"
, 188, __PRETTY_FUNCTION__))
;
189 addOperand(*MF, Op);
190}
191
192/// Move NumOps MachineOperands from Src to Dst, with support for overlapping
193/// ranges. If MRI is non-null also update use-def chains.
194static void moveOperands(MachineOperand *Dst, MachineOperand *Src,
195 unsigned NumOps, MachineRegisterInfo *MRI) {
196 if (MRI)
197 return MRI->moveOperands(Dst, Src, NumOps);
198 // MachineOperand is a trivially copyable type so we can just use memmove.
199 assert(Dst && Src && "Unknown operands")((Dst && Src && "Unknown operands") ? static_cast
<void> (0) : __assert_fail ("Dst && Src && \"Unknown operands\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/MachineInstr.cpp"
, 199, __PRETTY_FUNCTION__))
;
200 std::memmove(Dst, Src, NumOps * sizeof(MachineOperand));
201}
202
203/// addOperand - Add the specified operand to the instruction. If it is an
204/// implicit operand, it is added to the end of the operand list. If it is
205/// an explicit operand it is added at the end of the explicit operand list
206/// (before the first implicit operand).
207void MachineInstr::addOperand(MachineFunction &MF, const MachineOperand &Op) {
208 assert(MCID && "Cannot add operands before providing an instr descriptor")((MCID && "Cannot add operands before providing an instr descriptor"
) ? static_cast<void> (0) : __assert_fail ("MCID && \"Cannot add operands before providing an instr descriptor\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/MachineInstr.cpp"
, 208, __PRETTY_FUNCTION__))
;
209
210 // Check if we're adding one of our existing operands.
211 if (&Op >= Operands && &Op < Operands + NumOperands) {
212 // This is unusual: MI->addOperand(MI->getOperand(i)).
213 // If adding Op requires reallocating or moving existing operands around,
214 // the Op reference could go stale. Support it by copying Op.
215 MachineOperand CopyOp(Op);
216 return addOperand(MF, CopyOp);
217 }
218
219 // Find the insert location for the new operand. Implicit registers go at
220 // the end, everything else goes before the implicit regs.
221 //
222 // FIXME: Allow mixed explicit and implicit operands on inline asm.
223 // InstrEmitter::EmitSpecialNode() is marking inline asm clobbers as
224 // implicit-defs, but they must not be moved around. See the FIXME in
225 // InstrEmitter.cpp.
226 unsigned OpNo = getNumOperands();
227 bool isImpReg = Op.isReg() && Op.isImplicit();
228 if (!isImpReg && !isInlineAsm()) {
229 while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) {
230 --OpNo;
231 assert(!Operands[OpNo].isTied() && "Cannot move tied operands")((!Operands[OpNo].isTied() && "Cannot move tied operands"
) ? static_cast<void> (0) : __assert_fail ("!Operands[OpNo].isTied() && \"Cannot move tied operands\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/MachineInstr.cpp"
, 231, __PRETTY_FUNCTION__))
;
232 }
233 }
234
235#ifndef NDEBUG
236 bool isDebugOp = Op.getType() == MachineOperand::MO_Metadata ||
237 Op.getType() == MachineOperand::MO_MCSymbol;
238 // OpNo now points as the desired insertion point. Unless this is a variadic
239 // instruction, only implicit regs are allowed beyond MCID->getNumOperands().
240 // RegMask operands go between the explicit and implicit operands.
241 assert((isImpReg || Op.isRegMask() || MCID->isVariadic() ||(((isImpReg || Op.isRegMask() || MCID->isVariadic() || OpNo
< MCID->getNumOperands() || isDebugOp) && "Trying to add an operand to a machine instr that is already done!"
) ? static_cast<void> (0) : __assert_fail ("(isImpReg || Op.isRegMask() || MCID->isVariadic() || OpNo < MCID->getNumOperands() || isDebugOp) && \"Trying to add an operand to a machine instr that is already done!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/MachineInstr.cpp"
, 243, __PRETTY_FUNCTION__))
242 OpNo < MCID->getNumOperands() || isDebugOp) &&(((isImpReg || Op.isRegMask() || MCID->isVariadic() || OpNo
< MCID->getNumOperands() || isDebugOp) && "Trying to add an operand to a machine instr that is already done!"
) ? static_cast<void> (0) : __assert_fail ("(isImpReg || Op.isRegMask() || MCID->isVariadic() || OpNo < MCID->getNumOperands() || isDebugOp) && \"Trying to add an operand to a machine instr that is already done!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/MachineInstr.cpp"
, 243, __PRETTY_FUNCTION__))
243 "Trying to add an operand to a machine instr that is already done!")(((isImpReg || Op.isRegMask() || MCID->isVariadic() || OpNo
< MCID->getNumOperands() || isDebugOp) && "Trying to add an operand to a machine instr that is already done!"
) ? static_cast<void> (0) : __assert_fail ("(isImpReg || Op.isRegMask() || MCID->isVariadic() || OpNo < MCID->getNumOperands() || isDebugOp) && \"Trying to add an operand to a machine instr that is already done!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/MachineInstr.cpp"
, 243, __PRETTY_FUNCTION__))
;
244#endif
245
246 MachineRegisterInfo *MRI = getRegInfo();
247
248 // Determine if the Operands array needs to be reallocated.
249 // Save the old capacity and operand array.
250 OperandCapacity OldCap = CapOperands;
251 MachineOperand *OldOperands = Operands;
252 if (!OldOperands || OldCap.getSize() == getNumOperands()) {
253 CapOperands = OldOperands ? OldCap.getNext() : OldCap.get(1);
254 Operands = MF.allocateOperandArray(CapOperands);
255 // Move the operands before the insertion point.
256 if (OpNo)
257 moveOperands(Operands, OldOperands, OpNo, MRI);
258 }
259
260 // Move the operands following the insertion point.
261 if (OpNo != NumOperands)
262 moveOperands(Operands + OpNo + 1, OldOperands + OpNo, NumOperands - OpNo,
263 MRI);
264 ++NumOperands;
265
266 // Deallocate the old operand array.
267 if (OldOperands != Operands && OldOperands)
268 MF.deallocateOperandArray(OldCap, OldOperands);
269
270 // Copy Op into place. It still needs to be inserted into the MRI use lists.
271 MachineOperand *NewMO = new (Operands + OpNo) MachineOperand(Op);
272 NewMO->ParentMI = this;
273
274 // When adding a register operand, tell MRI about it.
275 if (NewMO->isReg()) {
276 // Ensure isOnRegUseList() returns false, regardless of Op's status.
277 NewMO->Contents.Reg.Prev = nullptr;
278 // Ignore existing ties. This is not a property that can be copied.
279 NewMO->TiedTo = 0;
280 // Add the new operand to MRI, but only for instructions in an MBB.
281 if (MRI)
282 MRI->addRegOperandToUseList(NewMO);
283 // The MCID operand information isn't accurate until we start adding
284 // explicit operands. The implicit operands are added first, then the
285 // explicits are inserted before them.
286 if (!isImpReg) {
287 // Tie uses to defs as indicated in MCInstrDesc.
288 if (NewMO->isUse()) {
289 int DefIdx = MCID->getOperandConstraint(OpNo, MCOI::TIED_TO);
290 if (DefIdx != -1)
291 tieOperands(DefIdx, OpNo);
292 }
293 // If the register operand is flagged as early, mark the operand as such.
294 if (MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1)
295 NewMO->setIsEarlyClobber(true);
296 }
297 }
298}
299
300/// RemoveOperand - Erase an operand from an instruction, leaving it with one
301/// fewer operand than it started with.
302///
303void MachineInstr::RemoveOperand(unsigned OpNo) {
304 assert(OpNo < getNumOperands() && "Invalid operand number")((OpNo < getNumOperands() && "Invalid operand number"
) ? static_cast<void> (0) : __assert_fail ("OpNo < getNumOperands() && \"Invalid operand number\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/MachineInstr.cpp"
, 304, __PRETTY_FUNCTION__))
;
305 untieRegOperand(OpNo);
306
307#ifndef NDEBUG
308 // Moving tied operands would break the ties.
309 for (unsigned i = OpNo + 1, e = getNumOperands(); i != e; ++i)
310 if (Operands[i].isReg())
311 assert(!Operands[i].isTied() && "Cannot move tied operands")((!Operands[i].isTied() && "Cannot move tied operands"
) ? static_cast<void> (0) : __assert_fail ("!Operands[i].isTied() && \"Cannot move tied operands\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/MachineInstr.cpp"
, 311, __PRETTY_FUNCTION__))
;
312#endif
313
314 MachineRegisterInfo *MRI = getRegInfo();
315 if (MRI && Operands[OpNo].isReg())
316 MRI->removeRegOperandFromUseList(Operands + OpNo);
317
318 // Don't call the MachineOperand destructor. A lot of this code depends on
319 // MachineOperand having a trivial destructor anyway, and adding a call here
320 // wouldn't make it 'destructor-correct'.
321
322 if (unsigned N = NumOperands - 1 - OpNo)
323 moveOperands(Operands + OpNo, Operands + OpNo + 1, N, MRI);
324 --NumOperands;
325}
326
327void MachineInstr::setExtraInfo(MachineFunction &MF,
328 ArrayRef<MachineMemOperand *> MMOs,
329 MCSymbol *PreInstrSymbol,
330 MCSymbol *PostInstrSymbol,
331 MDNode *HeapAllocMarker) {
332 bool HasPreInstrSymbol = PreInstrSymbol != nullptr;
333 bool HasPostInstrSymbol = PostInstrSymbol != nullptr;
334 bool HasHeapAllocMarker = HeapAllocMarker != nullptr;
335 int NumPointers =
336 MMOs.size() + HasPreInstrSymbol + HasPostInstrSymbol + HasHeapAllocMarker;
337
338 // Drop all extra info if there is none.
339 if (NumPointers <= 0) {
340 Info.clear();
341 return;
342 }
343
344 // If more than one pointer, then store out of line. Store heap alloc markers
345 // out of line because PointerSumType cannot hold more than 4 tag types with
346 // 32-bit pointers.
347 // FIXME: Maybe we should make the symbols in the extra info mutable?
348 else if (NumPointers > 1 || HasHeapAllocMarker) {
349 Info.set<EIIK_OutOfLine>(MF.createMIExtraInfo(
350 MMOs, PreInstrSymbol, PostInstrSymbol, HeapAllocMarker));
351 return;
352 }
353
354 // Otherwise store the single pointer inline.
355 if (HasPreInstrSymbol)
356 Info.set<EIIK_PreInstrSymbol>(PreInstrSymbol);
357 else if (HasPostInstrSymbol)
358 Info.set<EIIK_PostInstrSymbol>(PostInstrSymbol);
359 else
360 Info.set<EIIK_MMO>(MMOs[0]);
361}
362
363void MachineInstr::dropMemRefs(MachineFunction &MF) {
364 if (memoperands_empty())
365 return;
366
367 setExtraInfo(MF, {}, getPreInstrSymbol(), getPostInstrSymbol(),
368 getHeapAllocMarker());
369}
370
371void MachineInstr::setMemRefs(MachineFunction &MF,
372 ArrayRef<MachineMemOperand *> MMOs) {
373 if (MMOs.empty()) {
374 dropMemRefs(MF);
375 return;
376 }
377
378 setExtraInfo(MF, MMOs, getPreInstrSymbol(), getPostInstrSymbol(),
379 getHeapAllocMarker());
380}
381
382void MachineInstr::addMemOperand(MachineFunction &MF,
383 MachineMemOperand *MO) {
384 SmallVector<MachineMemOperand *, 2> MMOs;
385 MMOs.append(memoperands_begin(), memoperands_end());
386 MMOs.push_back(MO);
387 setMemRefs(MF, MMOs);
388}
389
390void MachineInstr::cloneMemRefs(MachineFunction &MF, const MachineInstr &MI) {
391 if (this == &MI)
392 // Nothing to do for a self-clone!
393 return;
394
395 assert(&MF == MI.getMF() &&((&MF == MI.getMF() && "Invalid machine functions when cloning memory refrences!"
) ? static_cast<void> (0) : __assert_fail ("&MF == MI.getMF() && \"Invalid machine functions when cloning memory refrences!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/MachineInstr.cpp"
, 396, __PRETTY_FUNCTION__))
396 "Invalid machine functions when cloning memory refrences!")((&MF == MI.getMF() && "Invalid machine functions when cloning memory refrences!"
) ? static_cast<void> (0) : __assert_fail ("&MF == MI.getMF() && \"Invalid machine functions when cloning memory refrences!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/MachineInstr.cpp"
, 396, __PRETTY_FUNCTION__))
;
397 // See if we can just steal the extra info already allocated for the
398 // instruction. We can do this whenever the pre- and post-instruction symbols
399 // are the same (including null).
400 if (getPreInstrSymbol() == MI.getPreInstrSymbol() &&
401 getPostInstrSymbol() == MI.getPostInstrSymbol() &&
402 getHeapAllocMarker() == MI.getHeapAllocMarker()) {
403 Info = MI.Info;
404 return;
405 }
406
407 // Otherwise, fall back on a copy-based clone.
408 setMemRefs(MF, MI.memoperands());
409}
410
411/// Check to see if the MMOs pointed to by the two MemRefs arrays are
412/// identical.
413static bool hasIdenticalMMOs(ArrayRef<MachineMemOperand *> LHS,
414 ArrayRef<MachineMemOperand *> RHS) {
415 if (LHS.size() != RHS.size())
416 return false;
417
418 auto LHSPointees = make_pointee_range(LHS);
419 auto RHSPointees = make_pointee_range(RHS);
420 return std::equal(LHSPointees.begin(), LHSPointees.end(),
421 RHSPointees.begin());
422}
423
424void MachineInstr::cloneMergedMemRefs(MachineFunction &MF,
425 ArrayRef<const MachineInstr *> MIs) {
426 // Try handling easy numbers of MIs with simpler mechanisms.
427 if (MIs.empty()) {
428 dropMemRefs(MF);
429 return;
430 }
431 if (MIs.size() == 1) {
432 cloneMemRefs(MF, *MIs[0]);
433 return;
434 }
435 // Because an empty memoperands list provides *no* information and must be
436 // handled conservatively (assuming the instruction can do anything), the only
437 // way to merge with it is to drop all other memoperands.
438 if (MIs[0]->memoperands_empty()) {
439 dropMemRefs(MF);
440 return;
441 }
442
443 // Handle the general case.
444 SmallVector<MachineMemOperand *, 2> MergedMMOs;
445 // Start with the first instruction.
446 assert(&MF == MIs[0]->getMF() &&((&MF == MIs[0]->getMF() && "Invalid machine functions when cloning memory references!"
) ? static_cast<void> (0) : __assert_fail ("&MF == MIs[0]->getMF() && \"Invalid machine functions when cloning memory references!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/MachineInstr.cpp"
, 447, __PRETTY_FUNCTION__))
447 "Invalid machine functions when cloning memory references!")((&MF == MIs[0]->getMF() && "Invalid machine functions when cloning memory references!"
) ? static_cast<void> (0) : __assert_fail ("&MF == MIs[0]->getMF() && \"Invalid machine functions when cloning memory references!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/MachineInstr.cpp"
, 447, __PRETTY_FUNCTION__))
;
448 MergedMMOs.append(MIs[0]->memoperands_begin(), MIs[0]->memoperands_end());
449 // Now walk all the other instructions and accumulate any different MMOs.
450 for (const MachineInstr &MI : make_pointee_range(MIs.slice(1))) {
451 assert(&MF == MI.getMF() &&((&MF == MI.getMF() && "Invalid machine functions when cloning memory references!"
) ? static_cast<void> (0) : __assert_fail ("&MF == MI.getMF() && \"Invalid machine functions when cloning memory references!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/MachineInstr.cpp"
, 452, __PRETTY_FUNCTION__))
452 "Invalid machine functions when cloning memory references!")((&MF == MI.getMF() && "Invalid machine functions when cloning memory references!"
) ? static_cast<void> (0) : __assert_fail ("&MF == MI.getMF() && \"Invalid machine functions when cloning memory references!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/MachineInstr.cpp"
, 452, __PRETTY_FUNCTION__))
;
453
454 // Skip MIs with identical operands to the first. This is a somewhat
455 // arbitrary hack but will catch common cases without being quadratic.
456 // TODO: We could fully implement merge semantics here if needed.
457 if (hasIdenticalMMOs(MIs[0]->memoperands(), MI.memoperands()))
458 continue;
459
460 // Because an empty memoperands list provides *no* information and must be
461 // handled conservatively (assuming the instruction can do anything), the
462 // only way to merge with it is to drop all other memoperands.
463 if (MI.memoperands_empty()) {
464 dropMemRefs(MF);
465 return;
466 }
467
468 // Otherwise accumulate these into our temporary buffer of the merged state.
469 MergedMMOs.append(MI.memoperands_begin(), MI.memoperands_end());
470 }
471
472 setMemRefs(MF, MergedMMOs);
473}
474
475void MachineInstr::setPreInstrSymbol(MachineFunction &MF, MCSymbol *Symbol) {
476 // Do nothing if old and new symbols are the same.
477 if (Symbol == getPreInstrSymbol())
478 return;
479
480 // If there was only one symbol and we're removing it, just clear info.
481 if (!Symbol && Info.is<EIIK_PreInstrSymbol>()) {
482 Info.clear();
483 return;
484 }
485
486 setExtraInfo(MF, memoperands(), Symbol, getPostInstrSymbol(),
487 getHeapAllocMarker());
488}
489
490void MachineInstr::setPostInstrSymbol(MachineFunction &MF, MCSymbol *Symbol) {
491 // Do nothing if old and new symbols are the same.
492 if (Symbol == getPostInstrSymbol())
493 return;
494
495 // If there was only one symbol and we're removing it, just clear info.
496 if (!Symbol && Info.is<EIIK_PostInstrSymbol>()) {
497 Info.clear();
498 return;
499 }
500
501 setExtraInfo(MF, memoperands(), getPreInstrSymbol(), Symbol,
502 getHeapAllocMarker());
503}
504
505void MachineInstr::setHeapAllocMarker(MachineFunction &MF, MDNode *Marker) {
506 // Do nothing if old and new symbols are the same.
507 if (Marker == getHeapAllocMarker())
508 return;
509
510 setExtraInfo(MF, memoperands(), getPreInstrSymbol(), getPostInstrSymbol(),
511 Marker);
512}
513
514void MachineInstr::cloneInstrSymbols(MachineFunction &MF,
515 const MachineInstr &MI) {
516 if (this == &MI)
517 // Nothing to do for a self-clone!
518 return;
519
520 assert(&MF == MI.getMF() &&((&MF == MI.getMF() && "Invalid machine functions when cloning instruction symbols!"
) ? static_cast<void> (0) : __assert_fail ("&MF == MI.getMF() && \"Invalid machine functions when cloning instruction symbols!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/MachineInstr.cpp"
, 521, __PRETTY_FUNCTION__))
521 "Invalid machine functions when cloning instruction symbols!")((&MF == MI.getMF() && "Invalid machine functions when cloning instruction symbols!"
) ? static_cast<void> (0) : __assert_fail ("&MF == MI.getMF() && \"Invalid machine functions when cloning instruction symbols!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/MachineInstr.cpp"
, 521, __PRETTY_FUNCTION__))
;
522
523 setPreInstrSymbol(MF, MI.getPreInstrSymbol());
524 setPostInstrSymbol(MF, MI.getPostInstrSymbol());
525 setHeapAllocMarker(MF, MI.getHeapAllocMarker());
526}
527
528uint16_t MachineInstr::mergeFlagsWith(const MachineInstr &Other) const {
529 // For now, the just return the union of the flags. If the flags get more
530 // complicated over time, we might need more logic here.
531 return getFlags() | Other.getFlags();
532}
533
534uint16_t MachineInstr::copyFlagsFromInstruction(const Instruction &I) {
535 uint16_t MIFlags = 0;
536 // Copy the wrapping flags.
537 if (const OverflowingBinaryOperator *OB =
538 dyn_cast<OverflowingBinaryOperator>(&I)) {
539 if (OB->hasNoSignedWrap())
540 MIFlags |= MachineInstr::MIFlag::NoSWrap;
541 if (OB->hasNoUnsignedWrap())
542 MIFlags |= MachineInstr::MIFlag::NoUWrap;
543 }
544
545 // Copy the exact flag.
546 if (const PossiblyExactOperator *PE = dyn_cast<PossiblyExactOperator>(&I))
547 if (PE->isExact())
548 MIFlags |= MachineInstr::MIFlag::IsExact;
549
550 // Copy the fast-math flags.
551 if (const FPMathOperator *FP = dyn_cast<FPMathOperator>(&I)) {
552 const FastMathFlags Flags = FP->getFastMathFlags();
553 if (Flags.noNaNs())
554 MIFlags |= MachineInstr::MIFlag::FmNoNans;
555 if (Flags.noInfs())
556 MIFlags |= MachineInstr::MIFlag::FmNoInfs;
557 if (Flags.noSignedZeros())
558 MIFlags |= MachineInstr::MIFlag::FmNsz;
559 if (Flags.allowReciprocal())
560 MIFlags |= MachineInstr::MIFlag::FmArcp;
561 if (Flags.allowContract())
562 MIFlags |= MachineInstr::MIFlag::FmContract;
563 if (Flags.approxFunc())
564 MIFlags |= MachineInstr::MIFlag::FmAfn;
565 if (Flags.allowReassoc())
566 MIFlags |= MachineInstr::MIFlag::FmReassoc;
567 }
568
569 return MIFlags;
570}
571
572void MachineInstr::copyIRFlags(const Instruction &I) {
573 Flags = copyFlagsFromInstruction(I);
574}
575
576bool MachineInstr::hasPropertyInBundle(uint64_t Mask, QueryType Type) const {
577 assert(!isBundledWithPred() && "Must be called on bundle header")((!isBundledWithPred() && "Must be called on bundle header"
) ? static_cast<void> (0) : __assert_fail ("!isBundledWithPred() && \"Must be called on bundle header\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/MachineInstr.cpp"
, 577, __PRETTY_FUNCTION__))
;
578 for (MachineBasicBlock::const_instr_iterator MII = getIterator();; ++MII) {
579 if (MII->getDesc().getFlags() & Mask) {
580 if (Type == AnyInBundle)
581 return true;
582 } else {
583 if (Type == AllInBundle && !MII->isBundle())
584 return false;
585 }
586 // This was the last instruction in the bundle.
587 if (!MII->isBundledWithSucc())
588 return Type == AllInBundle;
589 }
590}
591
592bool MachineInstr::isIdenticalTo(const MachineInstr &Other,
593 MICheckType Check) const {
594 // If opcodes or number of operands are not the same then the two
595 // instructions are obviously not identical.
596 if (Other.getOpcode() != getOpcode() ||
597 Other.getNumOperands() != getNumOperands())
598 return false;
599
600 if (isBundle()) {
601 // We have passed the test above that both instructions have the same
602 // opcode, so we know that both instructions are bundles here. Let's compare
603 // MIs inside the bundle.
604 assert(Other.isBundle() && "Expected that both instructions are bundles.")((Other.isBundle() && "Expected that both instructions are bundles."
) ? static_cast<void> (0) : __assert_fail ("Other.isBundle() && \"Expected that both instructions are bundles.\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/MachineInstr.cpp"
, 604, __PRETTY_FUNCTION__))
;
605 MachineBasicBlock::const_instr_iterator I1 = getIterator();
606 MachineBasicBlock::const_instr_iterator I2 = Other.getIterator();
607 // Loop until we analysed the last intruction inside at least one of the
608 // bundles.
609 while (I1->isBundledWithSucc() && I2->isBundledWithSucc()) {
610 ++I1;
611 ++I2;
612 if (!I1->isIdenticalTo(*I2, Check))
613 return false;
614 }
615 // If we've reached the end of just one of the two bundles, but not both,
616 // the instructions are not identical.
617 if (I1->isBundledWithSucc() || I2->isBundledWithSucc())
618 return false;
619 }
620
621 // Check operands to make sure they match.
622 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
623 const MachineOperand &MO = getOperand(i);
624 const MachineOperand &OMO = Other.getOperand(i);
625 if (!MO.isReg()) {
626 if (!MO.isIdenticalTo(OMO))
627 return false;
628 continue;
629 }
630
631 // Clients may or may not want to ignore defs when testing for equality.
632 // For example, machine CSE pass only cares about finding common
633 // subexpressions, so it's safe to ignore virtual register defs.
634 if (MO.isDef()) {
635 if (Check == IgnoreDefs)
636 continue;
637 else if (Check == IgnoreVRegDefs) {
638 if (!Register::isVirtualRegister(MO.getReg()) ||
639 !Register::isVirtualRegister(OMO.getReg()))
640 if (!MO.isIdenticalTo(OMO))
641 return false;
642 } else {
643 if (!MO.isIdenticalTo(OMO))
644 return false;
645 if (Check == CheckKillDead && MO.isDead() != OMO.isDead())
646 return false;
647 }
648 } else {
649 if (!MO.isIdenticalTo(OMO))
650 return false;
651 if (Check == CheckKillDead && MO.isKill() != OMO.isKill())
652 return false;
653 }
654 }
655 // If DebugLoc does not match then two debug instructions are not identical.
656 if (isDebugInstr())
657 if (getDebugLoc() && Other.getDebugLoc() &&
658 getDebugLoc() != Other.getDebugLoc())
659 return false;
660 return true;
661}
662
663const MachineFunction *MachineInstr::getMF() const {
664 return getParent()->getParent();
665}
666
667MachineInstr *MachineInstr::removeFromParent() {
668 assert(getParent() && "Not embedded in a basic block!")((getParent() && "Not embedded in a basic block!") ? static_cast
<void> (0) : __assert_fail ("getParent() && \"Not embedded in a basic block!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/MachineInstr.cpp"
, 668, __PRETTY_FUNCTION__))
;
669 return getParent()->remove(this);
670}
671
672MachineInstr *MachineInstr::removeFromBundle() {
673 assert(getParent() && "Not embedded in a basic block!")((getParent() && "Not embedded in a basic block!") ? static_cast
<void> (0) : __assert_fail ("getParent() && \"Not embedded in a basic block!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/MachineInstr.cpp"
, 673, __PRETTY_FUNCTION__))
;
674 return getParent()->remove_instr(this);
675}
676
677void MachineInstr::eraseFromParent() {
678 assert(getParent() && "Not embedded in a basic block!")((getParent() && "Not embedded in a basic block!") ? static_cast
<void> (0) : __assert_fail ("getParent() && \"Not embedded in a basic block!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/MachineInstr.cpp"
, 678, __PRETTY_FUNCTION__))
;
679 getParent()->erase(this);
680}
681
682void MachineInstr::eraseFromParentAndMarkDBGValuesForRemoval() {
683 assert(getParent() && "Not embedded in a basic block!")((getParent() && "Not embedded in a basic block!") ? static_cast
<void> (0) : __assert_fail ("getParent() && \"Not embedded in a basic block!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/MachineInstr.cpp"
, 683, __PRETTY_FUNCTION__))
;
684 MachineBasicBlock *MBB = getParent();
685 MachineFunction *MF = MBB->getParent();
686 assert(MF && "Not embedded in a function!")((MF && "Not embedded in a function!") ? static_cast<
void> (0) : __assert_fail ("MF && \"Not embedded in a function!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/MachineInstr.cpp"
, 686, __PRETTY_FUNCTION__))
;
687
688 MachineInstr *MI = (MachineInstr *)this;
689 MachineRegisterInfo &MRI = MF->getRegInfo();
690
691 for (const MachineOperand &MO : MI->operands()) {
692 if (!MO.isReg() || !MO.isDef())
693 continue;
694 Register Reg = MO.getReg();
695 if (!Reg.isVirtual())
696 continue;
697 MRI.markUsesInDebugValueAsUndef(Reg);
698 }
699 MI->eraseFromParent();
700}
701
702void MachineInstr::eraseFromBundle() {
703 assert(getParent() && "Not embedded in a basic block!")((getParent() && "Not embedded in a basic block!") ? static_cast
<void> (0) : __assert_fail ("getParent() && \"Not embedded in a basic block!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/MachineInstr.cpp"
, 703, __PRETTY_FUNCTION__))
;
704 getParent()->erase_instr(this);
705}
706
707bool MachineInstr::isCandidateForCallSiteEntry(QueryType Type) const {
708 if (!isCall(Type))
709 return false;
710 switch (getOpcode()) {
711 case TargetOpcode::PATCHABLE_EVENT_CALL:
712 case TargetOpcode::PATCHABLE_TYPED_EVENT_CALL:
713 case TargetOpcode::PATCHPOINT:
714 case TargetOpcode::STACKMAP:
715 case TargetOpcode::STATEPOINT:
716 return false;
717 }
718 return true;
719}
720
721bool MachineInstr::shouldUpdateCallSiteInfo() const {
722 if (isBundle())
723 return isCandidateForCallSiteEntry(MachineInstr::AnyInBundle);
724 return isCandidateForCallSiteEntry();
725}
726
727unsigned MachineInstr::getNumExplicitOperands() const {
728 unsigned NumOperands = MCID->getNumOperands();
729 if (!MCID->isVariadic())
730 return NumOperands;
731
732 for (unsigned I = NumOperands, E = getNumOperands(); I != E; ++I) {
733 const MachineOperand &MO = getOperand(I);
734 // The operands must always be in the following order:
735 // - explicit reg defs,
736 // - other explicit operands (reg uses, immediates, etc.),
737 // - implicit reg defs
738 // - implicit reg uses
739 if (MO.isReg() && MO.isImplicit())
740 break;
741 ++NumOperands;
742 }
743 return NumOperands;
744}
745
746unsigned MachineInstr::getNumExplicitDefs() const {
747 unsigned NumDefs = MCID->getNumDefs();
748 if (!MCID->isVariadic())
749 return NumDefs;
750
751 for (unsigned I = NumDefs, E = getNumOperands(); I != E; ++I) {
752 const MachineOperand &MO = getOperand(I);
753 if (!MO.isReg() || !MO.isDef() || MO.isImplicit())
754 break;
755 ++NumDefs;
756 }
757 return NumDefs;
758}
759
760void MachineInstr::bundleWithPred() {
761 assert(!isBundledWithPred() && "MI is already bundled with its predecessor")((!isBundledWithPred() && "MI is already bundled with its predecessor"
) ? static_cast<void> (0) : __assert_fail ("!isBundledWithPred() && \"MI is already bundled with its predecessor\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/MachineInstr.cpp"
, 761, __PRETTY_FUNCTION__))
;
762 setFlag(BundledPred);
763 MachineBasicBlock::instr_iterator Pred = getIterator();
764 --Pred;
765 assert(!Pred->isBundledWithSucc() && "Inconsistent bundle flags")((!Pred->isBundledWithSucc() && "Inconsistent bundle flags"
) ? static_cast<void> (0) : __assert_fail ("!Pred->isBundledWithSucc() && \"Inconsistent bundle flags\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/MachineInstr.cpp"
, 765, __PRETTY_FUNCTION__))
;
766 Pred->setFlag(BundledSucc);
767}
768
769void MachineInstr::bundleWithSucc() {
770 assert(!isBundledWithSucc() && "MI is already bundled with its successor")((!isBundledWithSucc() && "MI is already bundled with its successor"
) ? static_cast<void> (0) : __assert_fail ("!isBundledWithSucc() && \"MI is already bundled with its successor\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/MachineInstr.cpp"
, 770, __PRETTY_FUNCTION__))
;
771 setFlag(BundledSucc);
772 MachineBasicBlock::instr_iterator Succ = getIterator();
773 ++Succ;
774 assert(!Succ->isBundledWithPred() && "Inconsistent bundle flags")((!Succ->isBundledWithPred() && "Inconsistent bundle flags"
) ? static_cast<void> (0) : __assert_fail ("!Succ->isBundledWithPred() && \"Inconsistent bundle flags\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/MachineInstr.cpp"
, 774, __PRETTY_FUNCTION__))
;
775 Succ->setFlag(BundledPred);
776}
777
778void MachineInstr::unbundleFromPred() {
779 assert(isBundledWithPred() && "MI isn't bundled with its predecessor")((isBundledWithPred() && "MI isn't bundled with its predecessor"
) ? static_cast<void> (0) : __assert_fail ("isBundledWithPred() && \"MI isn't bundled with its predecessor\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/MachineInstr.cpp"
, 779, __PRETTY_FUNCTION__))
;
780 clearFlag(BundledPred);
781 MachineBasicBlock::instr_iterator Pred = getIterator();
782 --Pred;
783 assert(Pred->isBundledWithSucc() && "Inconsistent bundle flags")((Pred->isBundledWithSucc() && "Inconsistent bundle flags"
) ? static_cast<void> (0) : __assert_fail ("Pred->isBundledWithSucc() && \"Inconsistent bundle flags\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/MachineInstr.cpp"
, 783, __PRETTY_FUNCTION__))
;
784 Pred->clearFlag(BundledSucc);
785}
786
787void MachineInstr::unbundleFromSucc() {
788 assert(isBundledWithSucc() && "MI isn't bundled with its successor")((isBundledWithSucc() && "MI isn't bundled with its successor"
) ? static_cast<void> (0) : __assert_fail ("isBundledWithSucc() && \"MI isn't bundled with its successor\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/MachineInstr.cpp"
, 788, __PRETTY_FUNCTION__))
;
789 clearFlag(BundledSucc);
790 MachineBasicBlock::instr_iterator Succ = getIterator();
791 ++Succ;
792 assert(Succ->isBundledWithPred() && "Inconsistent bundle flags")((Succ->isBundledWithPred() && "Inconsistent bundle flags"
) ? static_cast<void> (0) : __assert_fail ("Succ->isBundledWithPred() && \"Inconsistent bundle flags\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/MachineInstr.cpp"
, 792, __PRETTY_FUNCTION__))
;
793 Succ->clearFlag(BundledPred);
794}
795
796bool MachineInstr::isStackAligningInlineAsm() const {
797 if (isInlineAsm()) {
798 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
799 if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
800 return true;
801 }
802 return false;
803}
804
805InlineAsm::AsmDialect MachineInstr::getInlineAsmDialect() const {
806 assert(isInlineAsm() && "getInlineAsmDialect() only works for inline asms!")((isInlineAsm() && "getInlineAsmDialect() only works for inline asms!"
) ? static_cast<void> (0) : __assert_fail ("isInlineAsm() && \"getInlineAsmDialect() only works for inline asms!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/MachineInstr.cpp"
, 806, __PRETTY_FUNCTION__))
;
807 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
808 return InlineAsm::AsmDialect((ExtraInfo & InlineAsm::Extra_AsmDialect) != 0);
809}
810
811int MachineInstr::findInlineAsmFlagIdx(unsigned OpIdx,
812 unsigned *GroupNo) const {
813 assert(isInlineAsm() && "Expected an inline asm instruction")((isInlineAsm() && "Expected an inline asm instruction"
) ? static_cast<void> (0) : __assert_fail ("isInlineAsm() && \"Expected an inline asm instruction\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/MachineInstr.cpp"
, 813, __PRETTY_FUNCTION__))
;
814 assert(OpIdx < getNumOperands() && "OpIdx out of range")((OpIdx < getNumOperands() && "OpIdx out of range"
) ? static_cast<void> (0) : __assert_fail ("OpIdx < getNumOperands() && \"OpIdx out of range\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/MachineInstr.cpp"
, 814, __PRETTY_FUNCTION__))
;
815
816 // Ignore queries about the initial operands.
817 if (OpIdx < InlineAsm::MIOp_FirstOperand)
818 return -1;
819
820 unsigned Group = 0;
821 unsigned NumOps;
822 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
823 i += NumOps) {
824 const MachineOperand &FlagMO = getOperand(i);
825 // If we reach the implicit register operands, stop looking.
826 if (!FlagMO.isImm())
827 return -1;
828 NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
829 if (i + NumOps > OpIdx) {
830 if (GroupNo)
831 *GroupNo = Group;
832 return i;
833 }
834 ++Group;
835 }
836 return -1;
837}
838
839const DILabel *MachineInstr::getDebugLabel() const {
840 assert(isDebugLabel() && "not a DBG_LABEL")((isDebugLabel() && "not a DBG_LABEL") ? static_cast<
void> (0) : __assert_fail ("isDebugLabel() && \"not a DBG_LABEL\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/MachineInstr.cpp"
, 840, __PRETTY_FUNCTION__))
;
841 return cast<DILabel>(getOperand(0).getMetadata());
842}
843
844const MachineOperand &MachineInstr::getDebugVariableOp() const {
845 assert((isDebugValue() || isDebugRef()) && "not a DBG_VALUE")(((isDebugValue() || isDebugRef()) && "not a DBG_VALUE"
) ? static_cast<void> (0) : __assert_fail ("(isDebugValue() || isDebugRef()) && \"not a DBG_VALUE\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/MachineInstr.cpp"
, 845, __PRETTY_FUNCTION__))
;
846 return getOperand(2);
847}
848
849MachineOperand &MachineInstr::getDebugVariableOp() {
850 assert((isDebugValue() || isDebugRef()) && "not a DBG_VALUE")(((isDebugValue() || isDebugRef()) && "not a DBG_VALUE"
) ? static_cast<void> (0) : __assert_fail ("(isDebugValue() || isDebugRef()) && \"not a DBG_VALUE\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/MachineInstr.cpp"
, 850, __PRETTY_FUNCTION__))
;
851 return getOperand(2);
852}
853
854const DILocalVariable *MachineInstr::getDebugVariable() const {
855 assert((isDebugValue() || isDebugRef()) && "not a DBG_VALUE")(((isDebugValue() || isDebugRef()) && "not a DBG_VALUE"
) ? static_cast<void> (0) : __assert_fail ("(isDebugValue() || isDebugRef()) && \"not a DBG_VALUE\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/MachineInstr.cpp"
, 855, __PRETTY_FUNCTION__))
;
856 return cast<DILocalVariable>(getOperand(2).getMetadata());
857}
858
859MachineOperand &MachineInstr::getDebugExpressionOp() {
860 assert((isDebugValue() || isDebugRef()) && "not a DBG_VALUE")(((isDebugValue() || isDebugRef()) && "not a DBG_VALUE"
) ? static_cast<void> (0) : __assert_fail ("(isDebugValue() || isDebugRef()) && \"not a DBG_VALUE\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/MachineInstr.cpp"
, 860, __PRETTY_FUNCTION__))
;
861 return getOperand(3);
862}
863
864const DIExpression *MachineInstr::getDebugExpression() const {
865 assert((isDebugValue() || isDebugRef()) && "not a DBG_VALUE")(((isDebugValue() || isDebugRef()) && "not a DBG_VALUE"
) ? static_cast<void> (0) : __assert_fail ("(isDebugValue() || isDebugRef()) && \"not a DBG_VALUE\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/MachineInstr.cpp"
, 865, __PRETTY_FUNCTION__))
;
866 return cast<DIExpression>(getOperand(3).getMetadata());
867}
868
869bool MachineInstr::isDebugEntryValue() const {
870 return isDebugValue() && getDebugExpression()->isEntryValue();
871}
872
873const TargetRegisterClass*
874MachineInstr::getRegClassConstraint(unsigned OpIdx,
875 const TargetInstrInfo *TII,
876 const TargetRegisterInfo *TRI) const {
877 assert(getParent() && "Can't have an MBB reference here!")((getParent() && "Can't have an MBB reference here!")
? static_cast<void> (0) : __assert_fail ("getParent() && \"Can't have an MBB reference here!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/MachineInstr.cpp"
, 877, __PRETTY_FUNCTION__))
;
878 assert(getMF() && "Can't have an MF reference here!")((getMF() && "Can't have an MF reference here!") ? static_cast
<void> (0) : __assert_fail ("getMF() && \"Can't have an MF reference here!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/MachineInstr.cpp"
, 878, __PRETTY_FUNCTION__))
;
879 const MachineFunction &MF = *getMF();
880
881 // Most opcodes have fixed constraints in their MCInstrDesc.
882 if (!isInlineAsm())
883 return TII->getRegClass(getDesc(), OpIdx, TRI, MF);
884
885 if (!getOperand(OpIdx).isReg())
886 return nullptr;
887
888 // For tied uses on inline asm, get the constraint from the def.
889 unsigned DefIdx;
890 if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx))
891 OpIdx = DefIdx;
892
893 // Inline asm stores register class constraints in the flag word.
894 int FlagIdx = findInlineAsmFlagIdx(OpIdx);
895 if (FlagIdx < 0)
896 return nullptr;
897
898 unsigned Flag = getOperand(FlagIdx).getImm();
899 unsigned RCID;
900 if ((InlineAsm::getKind(Flag) == InlineAsm::Kind_RegUse ||
901 InlineAsm::getKind(Flag) == InlineAsm::Kind_RegDef ||
902 InlineAsm::getKind(Flag) == InlineAsm::Kind_RegDefEarlyClobber) &&
903 InlineAsm::hasRegClassConstraint(Flag, RCID))
904 return TRI->getRegClass(RCID);
905
906 // Assume that all registers in a memory operand are pointers.
907 if (InlineAsm::getKind(Flag) == InlineAsm::Kind_Mem)
908 return TRI->getPointerRegClass(MF);
909
910 return nullptr;
911}
912
913const TargetRegisterClass *MachineInstr::getRegClassConstraintEffectForVReg(
914 Register Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII,
915 const TargetRegisterInfo *TRI, bool ExploreBundle) const {
916 // Check every operands inside the bundle if we have
917 // been asked to.
918 if (ExploreBundle)
919 for (ConstMIBundleOperands OpndIt(*this); OpndIt.isValid() && CurRC;
920 ++OpndIt)
921 CurRC = OpndIt->getParent()->getRegClassConstraintEffectForVRegImpl(
922 OpndIt.getOperandNo(), Reg, CurRC, TII, TRI);
923 else
924 // Otherwise, just check the current operands.
925 for (unsigned i = 0, e = NumOperands; i < e && CurRC; ++i)
926 CurRC = getRegClassConstraintEffectForVRegImpl(i, Reg, CurRC, TII, TRI);
927 return CurRC;
928}
929
930const TargetRegisterClass *MachineInstr::getRegClassConstraintEffectForVRegImpl(
931 unsigned OpIdx, Register Reg, const TargetRegisterClass *CurRC,
932 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const {
933 assert(CurRC && "Invalid initial register class")((CurRC && "Invalid initial register class") ? static_cast
<void> (0) : __assert_fail ("CurRC && \"Invalid initial register class\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/MachineInstr.cpp"
, 933, __PRETTY_FUNCTION__))
;
934 // Check if Reg is constrained by some of its use/def from MI.
935 const MachineOperand &MO = getOperand(OpIdx);
936 if (!MO.isReg() || MO.getReg() != Reg)
937 return CurRC;
938 // If yes, accumulate the constraints through the operand.
939 return getRegClassConstraintEffect(OpIdx, CurRC, TII, TRI);
940}
941
942const TargetRegisterClass *MachineInstr::getRegClassConstraintEffect(
943 unsigned OpIdx, const TargetRegisterClass *CurRC,
944 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const {
945 const TargetRegisterClass *OpRC = getRegClassConstraint(OpIdx, TII, TRI);
946 const MachineOperand &MO = getOperand(OpIdx);
947 assert(MO.isReg() &&((MO.isReg() && "Cannot get register constraints for non-register operand"
) ? static_cast<void> (0) : __assert_fail ("MO.isReg() && \"Cannot get register constraints for non-register operand\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/MachineInstr.cpp"
, 948, __PRETTY_FUNCTION__))
948 "Cannot get register constraints for non-register operand")((MO.isReg() && "Cannot get register constraints for non-register operand"
) ? static_cast<void> (0) : __assert_fail ("MO.isReg() && \"Cannot get register constraints for non-register operand\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/MachineInstr.cpp"
, 948, __PRETTY_FUNCTION__))
;
949 assert(CurRC && "Invalid initial register class")((CurRC && "Invalid initial register class") ? static_cast
<void> (0) : __assert_fail ("CurRC && \"Invalid initial register class\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/MachineInstr.cpp"
, 949, __PRETTY_FUNCTION__))
;
950 if (unsigned SubIdx = MO.getSubReg()) {
951 if (OpRC)
952 CurRC = TRI->getMatchingSuperRegClass(CurRC, OpRC, SubIdx);
953 else
954 CurRC = TRI->getSubClassWithSubReg(CurRC, SubIdx);
955 } else if (OpRC)
956 CurRC = TRI->getCommonSubClass(CurRC, OpRC);
957 return CurRC;
958}
959
960/// Return the number of instructions inside the MI bundle, not counting the
961/// header instruction.
962unsigned MachineInstr::getBundleSize() const {
963 MachineBasicBlock::const_instr_iterator I = getIterator();
964 unsigned Size = 0;
965 while (I->isBundledWithSucc()) {
966 ++Size;
967 ++I;
968 }
969 return Size;
970}
971
972/// Returns true if the MachineInstr has an implicit-use operand of exactly
973/// the given register (not considering sub/super-registers).
974bool MachineInstr::hasRegisterImplicitUseOperand(Register Reg) const {
975 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
976 const MachineOperand &MO = getOperand(i);
977 if (MO.isReg() && MO.isUse() && MO.isImplicit() && MO.getReg() == Reg)
978 return true;
979 }
980 return false;
981}
982
983/// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
984/// the specific register or -1 if it is not found. It further tightens
985/// the search criteria to a use that kills the register if isKill is true.
986int MachineInstr::findRegisterUseOperandIdx(
987 Register Reg, bool isKill, const TargetRegisterInfo *TRI) const {
988 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
989 const MachineOperand &MO = getOperand(i);
990 if (!MO.isReg() || !MO.isUse())
991 continue;
992 Register MOReg = MO.getReg();
993 if (!MOReg)
994 continue;
995 if (MOReg == Reg || (TRI && Reg && MOReg && TRI->regsOverlap(MOReg, Reg)))
996 if (!isKill || MO.isKill())
997 return i;
998 }
999 return -1;
1000}
1001
1002/// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
1003/// indicating if this instruction reads or writes Reg. This also considers
1004/// partial defines.
1005std::pair<bool,bool>
1006MachineInstr::readsWritesVirtualRegister(Register Reg,
1007 SmallVectorImpl<unsigned> *Ops) const {
1008 bool PartDef = false; // Partial redefine.
1009 bool FullDef = false; // Full define.
1010 bool Use = false;
1011
1012 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1013 const MachineOperand &MO = getOperand(i);
1014 if (!MO.isReg() || MO.getReg() != Reg)
1015 continue;
1016 if (Ops)
1017 Ops->push_back(i);
1018 if (MO.isUse())
1019 Use |= !MO.isUndef();
1020 else if (MO.getSubReg() && !MO.isUndef())
1021 // A partial def undef doesn't count as reading the register.
1022 PartDef = true;
1023 else
1024 FullDef = true;
1025 }
1026 // A partial redefine uses Reg unless there is also a full define.
1027 return std::make_pair(Use || (PartDef && !FullDef), PartDef || FullDef);
1028}
1029
1030/// findRegisterDefOperandIdx() - Returns the operand index that is a def of
1031/// the specified register or -1 if it is not found. If isDead is true, defs
1032/// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
1033/// also checks if there is a def of a super-register.
1034int
1035MachineInstr::findRegisterDefOperandIdx(Register Reg, bool isDead, bool Overlap,
1036 const TargetRegisterInfo *TRI) const {
1037 bool isPhys = Register::isPhysicalRegister(Reg);
1038 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1039 const MachineOperand &MO = getOperand(i);
1040 // Accept regmask operands when Overlap is set.
1041 // Ignore them when looking for a specific def operand (Overlap == false).
1042 if (isPhys && Overlap && MO.isRegMask() && MO.clobbersPhysReg(Reg))
1043 return i;
1044 if (!MO.isReg() || !MO.isDef())
1045 continue;
1046 Register MOReg = MO.getReg();
1047 bool Found = (MOReg == Reg);
1048 if (!Found && TRI && isPhys && Register::isPhysicalRegister(MOReg)) {
1049 if (Overlap)
1050 Found = TRI->regsOverlap(MOReg, Reg);
1051 else
1052 Found = TRI->isSubRegister(MOReg, Reg);
1053 }
1054 if (Found && (!isDead || MO.isDead()))
1055 return i;
1056 }
1057 return -1;
1058}
1059
1060/// findFirstPredOperandIdx() - Find the index of the first operand in the
1061/// operand list that is used to represent the predicate. It returns -1 if
1062/// none is found.
1063int MachineInstr::findFirstPredOperandIdx() const {
1064 // Don't call MCID.findFirstPredOperandIdx() because this variant
1065 // is sometimes called on an instruction that's not yet complete, and
1066 // so the number of operands is less than the MCID indicates. In
1067 // particular, the PTX target does this.
1068 const MCInstrDesc &MCID = getDesc();
1069 if (MCID.isPredicable()) {
1070 for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
1071 if (MCID.OpInfo[i].isPredicate())
1072 return i;
1073 }
1074
1075 return -1;
1076}
1077
1078// MachineOperand::TiedTo is 4 bits wide.
1079const unsigned TiedMax = 15;
1080
1081/// tieOperands - Mark operands at DefIdx and UseIdx as tied to each other.
1082///
1083/// Use and def operands can be tied together, indicated by a non-zero TiedTo
1084/// field. TiedTo can have these values:
1085///
1086/// 0: Operand is not tied to anything.
1087/// 1 to TiedMax-1: Tied to getOperand(TiedTo-1).
1088/// TiedMax: Tied to an operand >= TiedMax-1.
1089///
1090/// The tied def must be one of the first TiedMax operands on a normal
1091/// instruction. INLINEASM instructions allow more tied defs.
1092///
1093void MachineInstr::tieOperands(unsigned DefIdx, unsigned UseIdx) {
1094 MachineOperand &DefMO = getOperand(DefIdx);
1095 MachineOperand &UseMO = getOperand(UseIdx);
1096 assert(DefMO.isDef() && "DefIdx must be a def operand")((DefMO.isDef() && "DefIdx must be a def operand") ? static_cast
<void> (0) : __assert_fail ("DefMO.isDef() && \"DefIdx must be a def operand\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/MachineInstr.cpp"
, 1096, __PRETTY_FUNCTION__))
;
1097 assert(UseMO.isUse() && "UseIdx must be a use operand")((UseMO.isUse() && "UseIdx must be a use operand") ? static_cast
<void> (0) : __assert_fail ("UseMO.isUse() && \"UseIdx must be a use operand\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/MachineInstr.cpp"
, 1097, __PRETTY_FUNCTION__))
;
1098 assert(!DefMO.isTied() && "Def is already tied to another use")((!DefMO.isTied() && "Def is already tied to another use"
) ? static_cast<void> (0) : __assert_fail ("!DefMO.isTied() && \"Def is already tied to another use\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/MachineInstr.cpp"
, 1098, __PRETTY_FUNCTION__))
;
1099 assert(!UseMO.isTied() && "Use is already tied to another def")((!UseMO.isTied() && "Use is already tied to another def"
) ? static_cast<void> (0) : __assert_fail ("!UseMO.isTied() && \"Use is already tied to another def\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/MachineInstr.cpp"
, 1099, __PRETTY_FUNCTION__))
;
1100
1101 if (DefIdx < TiedMax)
1102 UseMO.TiedTo = DefIdx + 1;
1103 else {
1104 // Inline asm can use the group descriptors to find tied operands,
1105 // statepoint tied operands are trivial to match (1-1 reg def with reg use),
1106 // but on normal instruction, the tied def must be within the first TiedMax
1107 // operands.
1108 assert((isInlineAsm() || getOpcode() == TargetOpcode::STATEPOINT) &&(((isInlineAsm() || getOpcode() == TargetOpcode::STATEPOINT) &&
"DefIdx out of range") ? static_cast<void> (0) : __assert_fail
("(isInlineAsm() || getOpcode() == TargetOpcode::STATEPOINT) && \"DefIdx out of range\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/MachineInstr.cpp"
, 1109, __PRETTY_FUNCTION__))
1109 "DefIdx out of range")(((isInlineAsm() || getOpcode() == TargetOpcode::STATEPOINT) &&
"DefIdx out of range") ? static_cast<void> (0) : __assert_fail
("(isInlineAsm() || getOpcode() == TargetOpcode::STATEPOINT) && \"DefIdx out of range\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/MachineInstr.cpp"
, 1109, __PRETTY_FUNCTION__))
;
1110 UseMO.TiedTo = TiedMax;
1111 }
1112
1113 // UseIdx can be out of range, we'll search for it in findTiedOperandIdx().
1114 DefMO.TiedTo = std::min(UseIdx + 1, TiedMax);
1115}
1116
1117/// Given the index of a tied register operand, find the operand it is tied to.
1118/// Defs are tied to uses and vice versa. Returns the index of the tied operand
1119/// which must exist.
1120unsigned MachineInstr::findTiedOperandIdx(unsigned OpIdx) const {
1121 const MachineOperand &MO = getOperand(OpIdx);
1122 assert(MO.isTied() && "Operand isn't tied")((MO.isTied() && "Operand isn't tied") ? static_cast<
void> (0) : __assert_fail ("MO.isTied() && \"Operand isn't tied\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/MachineInstr.cpp"
, 1122, __PRETTY_FUNCTION__))
;
1123
1124 // Normally TiedTo is in range.
1125 if (MO.TiedTo < TiedMax)
1126 return MO.TiedTo - 1;
1127
1128 // Uses on normal instructions can be out of range.
1129 if (!isInlineAsm() && getOpcode() != TargetOpcode::STATEPOINT) {
1130 // Normal tied defs must be in the 0..TiedMax-1 range.
1131 if (MO.isUse())
1132 return TiedMax - 1;
1133 // MO is a def. Search for the tied use.
1134 for (unsigned i = TiedMax - 1, e = getNumOperands(); i != e; ++i) {
1135 const MachineOperand &UseMO = getOperand(i);
1136 if (UseMO.isReg() && UseMO.isUse() && UseMO.TiedTo == OpIdx + 1)
1137 return i;
1138 }
1139 llvm_unreachable("Can't find tied use")::llvm::llvm_unreachable_internal("Can't find tied use", "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/MachineInstr.cpp"
, 1139)
;
1140 }
1141
1142 if (getOpcode() == TargetOpcode::STATEPOINT) {
1143 // In STATEPOINT defs correspond 1-1 to GC pointer operands passed
1144 // on registers.
1145 StatepointOpers SO(this);
1146 unsigned CurUseIdx = SO.getFirstGCPtrIdx();
1147 assert(CurUseIdx != -1U && "only gc pointer statepoint operands can be tied")((CurUseIdx != -1U && "only gc pointer statepoint operands can be tied"
) ? static_cast<void> (0) : __assert_fail ("CurUseIdx != -1U && \"only gc pointer statepoint operands can be tied\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/MachineInstr.cpp"
, 1147, __PRETTY_FUNCTION__))
;
1148 unsigned NumDefs = getNumDefs();
1149 for (unsigned CurDefIdx = 0; CurDefIdx < NumDefs; ++CurDefIdx) {
1150 while (!getOperand(CurUseIdx).isReg())
1151 CurUseIdx = StackMaps::getNextMetaArgIdx(this, CurUseIdx);
1152 if (OpIdx == CurDefIdx)
1153 return CurUseIdx;
1154 if (OpIdx == CurUseIdx)
1155 return CurDefIdx;
1156 CurUseIdx = StackMaps::getNextMetaArgIdx(this, CurUseIdx);
1157 }
1158 llvm_unreachable("Can't find tied use")::llvm::llvm_unreachable_internal("Can't find tied use", "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/MachineInstr.cpp"
, 1158)
;
1159 }
1160
1161 // Now deal with inline asm by parsing the operand group descriptor flags.
1162 // Find the beginning of each operand group.
1163 SmallVector<unsigned, 8> GroupIdx;
1164 unsigned OpIdxGroup = ~0u;
1165 unsigned NumOps;
1166 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
1167 i += NumOps) {
1168 const MachineOperand &FlagMO = getOperand(i);
1169 assert(FlagMO.isImm() && "Invalid tied operand on inline asm")((FlagMO.isImm() && "Invalid tied operand on inline asm"
) ? static_cast<void> (0) : __assert_fail ("FlagMO.isImm() && \"Invalid tied operand on inline asm\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/MachineInstr.cpp"
, 1169, __PRETTY_FUNCTION__))
;
1170 unsigned CurGroup = GroupIdx.size();
1171 GroupIdx.push_back(i);
1172 NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
1173 // OpIdx belongs to this operand group.
1174 if (OpIdx > i && OpIdx < i + NumOps)
1175 OpIdxGroup = CurGroup;
1176 unsigned TiedGroup;
1177 if (!InlineAsm::isUseOperandTiedToDef(FlagMO.getImm(), TiedGroup))
1178 continue;
1179 // Operands in this group are tied to operands in TiedGroup which must be
1180 // earlier. Find the number of operands between the two groups.
1181 unsigned Delta = i - GroupIdx[TiedGroup];
1182
1183 // OpIdx is a use tied to TiedGroup.
1184 if (OpIdxGroup == CurGroup)
1185 return OpIdx - Delta;
1186
1187 // OpIdx is a def tied to this use group.
1188 if (OpIdxGroup == TiedGroup)
1189 return OpIdx + Delta;
1190 }
1191 llvm_unreachable("Invalid tied operand on inline asm")::llvm::llvm_unreachable_internal("Invalid tied operand on inline asm"
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/MachineInstr.cpp"
, 1191)
;
1192}
1193
1194/// clearKillInfo - Clears kill flags on all operands.
1195///
1196void MachineInstr::clearKillInfo() {
1197 for (MachineOperand &MO : operands()) {
1198 if (MO.isReg() && MO.isUse())
1199 MO.setIsKill(false);
1200 }
1201}
1202
1203void MachineInstr::substituteRegister(Register FromReg, Register ToReg,
1204 unsigned SubIdx,
1205 const TargetRegisterInfo &RegInfo) {
1206 if (Register::isPhysicalRegister(ToReg)) {
1207 if (SubIdx)
1208 ToReg = RegInfo.getSubReg(ToReg, SubIdx);
1209 for (MachineOperand &MO : operands()) {
1210 if (!MO.isReg() || MO.getReg() != FromReg)
1211 continue;
1212 MO.substPhysReg(ToReg, RegInfo);
1213 }
1214 } else {
1215 for (MachineOperand &MO : operands()) {
1216 if (!MO.isReg() || MO.getReg() != FromReg)
1217 continue;
1218 MO.substVirtReg(ToReg, SubIdx, RegInfo);
1219 }
1220 }
1221}
1222
1223/// isSafeToMove - Return true if it is safe to move this instruction. If
1224/// SawStore is set to true, it means that there is a store (or call) between
1225/// the instruction's location and its intended destination.
1226bool MachineInstr::isSafeToMove(AAResults *AA, bool &SawStore) const {
1227 // Ignore stuff that we obviously can't move.
1228 //
1229 // Treat volatile loads as stores. This is not strictly necessary for
1230 // volatiles, but it is required for atomic loads. It is not allowed to move
1231 // a load across an atomic load with Ordering > Monotonic.
1232 if (mayStore() || isCall() || isPHI() ||
1233 (mayLoad() && hasOrderedMemoryRef())) {
1234 SawStore = true;
1235 return false;
1236 }
1237
1238 if (isPosition() || isDebugInstr() || isTerminator() ||
1239 mayRaiseFPException() || hasUnmodeledSideEffects())
1240 return false;
1241
1242 // See if this instruction does a load. If so, we have to guarantee that the
1243 // loaded value doesn't change between the load and the its intended
1244 // destination. The check for isInvariantLoad gives the target the chance to
1245 // classify the load as always returning a constant, e.g. a constant pool
1246 // load.
1247 if (mayLoad() && !isDereferenceableInvariantLoad(AA))
1248 // Otherwise, this is a real load. If there is a store between the load and
1249 // end of block, we can't move it.
1250 return !SawStore;
1251
1252 return true;
1253}
1254
1255bool MachineInstr::mayAlias(AAResults *AA, const MachineInstr &Other,
1256 bool UseTBAA) const {
1257 const MachineFunction *MF = getMF();
1258 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
1259 const MachineFrameInfo &MFI = MF->getFrameInfo();
1260
1261 // Execulde call instruction which may alter the memory but can not be handled
1262 // by this function.
1263 if (isCall() || Other.isCall())
1264 return true;
1265
1266 // If neither instruction stores to memory, they can't alias in any
1267 // meaningful way, even if they read from the same address.
1268 if (!mayStore() && !Other.mayStore())
1269 return false;
1270
1271 // Both instructions must be memory operations to be able to alias.
1272 if (!mayLoadOrStore() || !Other.mayLoadOrStore())
1273 return false;
1274
1275 // Let the target decide if memory accesses cannot possibly overlap.
1276 if (TII->areMemAccessesTriviallyDisjoint(*this, Other))
1277 return false;
1278
1279 // Memory operations without memory operands may access anything. Be
1280 // conservative and assume `MayAlias`.
1281 if (memoperands_empty() || Other.memoperands_empty())
1282 return true;
1283
1284 // Skip if there are too many memory operands.
1285 auto NumChecks = getNumMemOperands() * Other.getNumMemOperands();
1286 if (NumChecks > TII->getMemOperandAACheckLimit())
1287 return true;
1288
1289 auto HasAlias = [MFI, AA, UseTBAA](const MachineMemOperand *MMOa,
1290 const MachineMemOperand *MMOb) {
1291 // The following interface to AA is fashioned after DAGCombiner::isAlias
1292 // and operates with MachineMemOperand offset with some important
1293 // assumptions:
1294 // - LLVM fundamentally assumes flat address spaces.
1295 // - MachineOperand offset can *only* result from legalization and
1296 // cannot affect queries other than the trivial case of overlap
1297 // checking.
1298 // - These offsets never wrap and never step outside
1299 // of allocated objects.
1300 // - There should never be any negative offsets here.
1301 //
1302 // FIXME: Modify API to hide this math from "user"
1303 // Even before we go to AA we can reason locally about some
1304 // memory objects. It can save compile time, and possibly catch some
1305 // corner cases not currently covered.
1306
1307 int64_t OffsetA = MMOa->getOffset();
1308 int64_t OffsetB = MMOb->getOffset();
1309 int64_t MinOffset = std::min(OffsetA, OffsetB);
1310
1311 uint64_t WidthA = MMOa->getSize();
1312 uint64_t WidthB = MMOb->getSize();
1313 bool KnownWidthA = WidthA != MemoryLocation::UnknownSize;
1314 bool KnownWidthB = WidthB != MemoryLocation::UnknownSize;
1315
1316 const Value *ValA = MMOa->getValue();
1317 const Value *ValB = MMOb->getValue();
1318 bool SameVal = (ValA && ValB && (ValA == ValB));
1319 if (!SameVal) {
1320 const PseudoSourceValue *PSVa = MMOa->getPseudoValue();
1321 const PseudoSourceValue *PSVb = MMOb->getPseudoValue();
1322 if (PSVa && ValB && !PSVa->mayAlias(&MFI))
1323 return false;
1324 if (PSVb && ValA && !PSVb->mayAlias(&MFI))
1325 return false;
1326 if (PSVa && PSVb && (PSVa == PSVb))
1327 SameVal = true;
1328 }
1329
1330 if (SameVal) {
1331 if (!KnownWidthA || !KnownWidthB)
1332 return true;
1333 int64_t MaxOffset = std::max(OffsetA, OffsetB);
1334 int64_t LowWidth = (MinOffset == OffsetA) ? WidthA : WidthB;
1335 return (MinOffset + LowWidth > MaxOffset);
1336 }
1337
1338 if (!AA)
1339 return true;
1340
1341 if (!ValA || !ValB)
1342 return true;
1343
1344 assert((OffsetA >= 0) && "Negative MachineMemOperand offset")(((OffsetA >= 0) && "Negative MachineMemOperand offset"
) ? static_cast<void> (0) : __assert_fail ("(OffsetA >= 0) && \"Negative MachineMemOperand offset\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/MachineInstr.cpp"
, 1344, __PRETTY_FUNCTION__))
;
1345 assert((OffsetB >= 0) && "Negative MachineMemOperand offset")(((OffsetB >= 0) && "Negative MachineMemOperand offset"
) ? static_cast<void> (0) : __assert_fail ("(OffsetB >= 0) && \"Negative MachineMemOperand offset\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/MachineInstr.cpp"
, 1345, __PRETTY_FUNCTION__))
;
1346
1347 int64_t OverlapA = KnownWidthA ? WidthA + OffsetA - MinOffset
1348 : MemoryLocation::UnknownSize;
1349 int64_t OverlapB = KnownWidthB ? WidthB + OffsetB - MinOffset
1350 : MemoryLocation::UnknownSize;
1351
1352 AliasResult AAResult =
1353 AA->alias(MemoryLocation(ValA, OverlapA,
1354 UseTBAA ? MMOa->getAAInfo() : AAMDNodes()),
1355 MemoryLocation(ValB, OverlapB,
1356 UseTBAA ? MMOb->getAAInfo() : AAMDNodes()));
1357
1358 return (AAResult != NoAlias);
1359 };
1360
1361 // Check each pair of memory operands from both instructions, which can't
1362 // alias only if all pairs won't alias.
1363 for (auto *MMOa : memoperands())
1364 for (auto *MMOb : Other.memoperands())
1365 if (HasAlias(MMOa, MMOb))
1366 return true;
1367
1368 return false;
1369}
1370
1371/// hasOrderedMemoryRef - Return true if this instruction may have an ordered
1372/// or volatile memory reference, or if the information describing the memory
1373/// reference is not available. Return false if it is known to have no ordered
1374/// memory references.
1375bool MachineInstr::hasOrderedMemoryRef() const {
1376 // An instruction known never to access memory won't have a volatile access.
1377 if (!mayStore() &&
1378 !mayLoad() &&
1379 !isCall() &&
1380 !hasUnmodeledSideEffects())
1381 return false;
1382
1383 // Otherwise, if the instruction has no memory reference information,
1384 // conservatively assume it wasn't preserved.
1385 if (memoperands_empty())
1386 return true;
1387
1388 // Check if any of our memory operands are ordered.
1389 return llvm::any_of(memoperands(), [](const MachineMemOperand *MMO) {
1390 return !MMO->isUnordered();
1391 });
1392}
1393
1394/// isDereferenceableInvariantLoad - Return true if this instruction will never
1395/// trap and is loading from a location whose value is invariant across a run of
1396/// this function.
1397bool MachineInstr::isDereferenceableInvariantLoad(AAResults *AA) const {
1398 // If the instruction doesn't load at all, it isn't an invariant load.
1399 if (!mayLoad())
1400 return false;
1401
1402 // If the instruction has lost its memoperands, conservatively assume that
1403 // it may not be an invariant load.
1404 if (memoperands_empty())
1405 return false;
1406
1407 const MachineFrameInfo &MFI = getParent()->getParent()->getFrameInfo();
1408
1409 for (MachineMemOperand *MMO : memoperands()) {
1410 if (!MMO->isUnordered())
1411 // If the memory operand has ordering side effects, we can't move the
1412 // instruction. Such an instruction is technically an invariant load,
1413 // but the caller code would need updated to expect that.
1414 return false;
1415 if (MMO->isStore()) return false;
1416 if (MMO->isInvariant() && MMO->isDereferenceable())
1417 continue;
1418
1419 // A load from a constant PseudoSourceValue is invariant.
1420 if (const PseudoSourceValue *PSV = MMO->getPseudoValue())
1421 if (PSV->isConstant(&MFI))
1422 continue;
1423
1424 if (const Value *V = MMO->getValue()) {
1425 // If we have an AliasAnalysis, ask it whether the memory is constant.
1426 if (AA &&
1427 AA->pointsToConstantMemory(
1428 MemoryLocation(V, MMO->getSize(), MMO->getAAInfo())))
1429 continue;
1430 }
1431
1432 // Otherwise assume conservatively.
1433 return false;
1434 }
1435
1436 // Everything checks out.
1437 return true;
1438}
1439
1440/// isConstantValuePHI - If the specified instruction is a PHI that always
1441/// merges together the same virtual register, return the register, otherwise
1442/// return 0.
1443unsigned MachineInstr::isConstantValuePHI() const {
1444 if (!isPHI())
1445 return 0;
1446 assert(getNumOperands() >= 3 &&((getNumOperands() >= 3 && "It's illegal to have a PHI without source operands"
) ? static_cast<void> (0) : __assert_fail ("getNumOperands() >= 3 && \"It's illegal to have a PHI without source operands\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/MachineInstr.cpp"
, 1447, __PRETTY_FUNCTION__))
1447 "It's illegal to have a PHI without source operands")((getNumOperands() >= 3 && "It's illegal to have a PHI without source operands"
) ? static_cast<void> (0) : __assert_fail ("getNumOperands() >= 3 && \"It's illegal to have a PHI without source operands\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/MachineInstr.cpp"
, 1447, __PRETTY_FUNCTION__))
;
1448
1449 Register Reg = getOperand(1).getReg();
1450 for (unsigned i = 3, e = getNumOperands(); i < e; i += 2)
1451 if (getOperand(i).getReg() != Reg)
1452 return 0;
1453 return Reg;
1454}
1455
1456bool MachineInstr::hasUnmodeledSideEffects() const {
1457 if (hasProperty(MCID::UnmodeledSideEffects))
1458 return true;
1459 if (isInlineAsm()) {
1460 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1461 if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1462 return true;
1463 }
1464
1465 return false;
1466}
1467
1468bool MachineInstr::isLoadFoldBarrier() const {
1469 return mayStore() || isCall() || hasUnmodeledSideEffects();
1470}
1471
1472/// allDefsAreDead - Return true if all the defs of this instruction are dead.
1473///
1474bool MachineInstr::allDefsAreDead() const {
1475 for (const MachineOperand &MO : operands()) {
1476 if (!MO.isReg() || MO.isUse())
1477 continue;
1478 if (!MO.isDead())
1479 return false;
1480 }
1481 return true;
1482}
1483
1484/// copyImplicitOps - Copy implicit register operands from specified
1485/// instruction to this instruction.
1486void MachineInstr::copyImplicitOps(MachineFunction &MF,
1487 const MachineInstr &MI) {
1488 for (unsigned i = MI.getDesc().getNumOperands(), e = MI.getNumOperands();
1489 i != e; ++i) {
1490 const MachineOperand &MO = MI.getOperand(i);
1491 if ((MO.isReg() && MO.isImplicit()) || MO.isRegMask())
1492 addOperand(MF, MO);
1493 }
1494}
1495
1496bool MachineInstr::hasComplexRegisterTies() const {
1497 const MCInstrDesc &MCID = getDesc();
1498 if (MCID.Opcode == TargetOpcode::STATEPOINT)
1499 return true;
1500 for (unsigned I = 0, E = getNumOperands(); I < E; ++I) {
1501 const auto &Operand = getOperand(I);
1502 if (!Operand.isReg() || Operand.isDef())
1503 // Ignore the defined registers as MCID marks only the uses as tied.
1504 continue;
1505 int ExpectedTiedIdx = MCID.getOperandConstraint(I, MCOI::TIED_TO);
1506 int TiedIdx = Operand.isTied() ? int(findTiedOperandIdx(I)) : -1;
1507 if (ExpectedTiedIdx != TiedIdx)
1508 return true;
1509 }
1510 return false;
1511}
1512
1513LLT MachineInstr::getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes,
1514 const MachineRegisterInfo &MRI) const {
1515 const MachineOperand &Op = getOperand(OpIdx);
1516 if (!Op.isReg())
1517 return LLT{};
1518
1519 if (isVariadic() || OpIdx >= getNumExplicitOperands())
1520 return MRI.getType(Op.getReg());
1521
1522 auto &OpInfo = getDesc().OpInfo[OpIdx];
1523 if (!OpInfo.isGenericType())
1524 return MRI.getType(Op.getReg());
1525
1526 if (PrintedTypes[OpInfo.getGenericTypeIndex()])
1527 return LLT{};
1528
1529 LLT TypeToPrint = MRI.getType(Op.getReg());
1530 // Don't mark the type index printed if it wasn't actually printed: maybe
1531 // another operand with the same type index has an actual type attached:
1532 if (TypeToPrint.isValid())
1533 PrintedTypes.set(OpInfo.getGenericTypeIndex());
1534 return TypeToPrint;
1535}
1536
1537#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
1538LLVM_DUMP_METHOD__attribute__((noinline)) __attribute__((__used__)) void MachineInstr::dump() const {
1539 dbgs() << " ";
1540 print(dbgs());
1541}
1542
1543LLVM_DUMP_METHOD__attribute__((noinline)) __attribute__((__used__)) void MachineInstr::dumprImpl(
1544 const MachineRegisterInfo &MRI, unsigned Depth, unsigned MaxDepth,
1545 SmallPtrSetImpl<const MachineInstr *> &AlreadySeenInstrs) const {
1546 if (Depth >= MaxDepth)
1547 return;
1548 if (!AlreadySeenInstrs.insert(this).second)
1549 return;
1550 // PadToColumn always inserts at least one space.
1551 // Don't mess up the alignment if we don't want any space.
1552 if (Depth)
1553 fdbgs().PadToColumn(Depth * 2);
1554 print(fdbgs());
1555 for (const MachineOperand &MO : operands()) {
1556 if (!MO.isReg() || MO.isDef())
1557 continue;
1558 Register Reg = MO.getReg();
1559 if (Reg.isPhysical())
1560 continue;
1561 const MachineInstr *NewMI = MRI.getUniqueVRegDef(Reg);
1562 if (NewMI == nullptr)
1563 continue;
1564 NewMI->dumprImpl(MRI, Depth + 1, MaxDepth, AlreadySeenInstrs);
1565 }
1566}
1567
1568LLVM_DUMP_METHOD__attribute__((noinline)) __attribute__((__used__)) void MachineInstr::dumpr(const MachineRegisterInfo &MRI,
1569 unsigned MaxDepth) const {
1570 SmallPtrSet<const MachineInstr *, 16> AlreadySeenInstrs;
1571 dumprImpl(MRI, 0, MaxDepth, AlreadySeenInstrs);
1572}
1573#endif
1574
1575void MachineInstr::print(raw_ostream &OS, bool IsStandalone, bool SkipOpers,
1576 bool SkipDebugLoc, bool AddNewLine,
1577 const TargetInstrInfo *TII) const {
1578 const Module *M = nullptr;
1579 const Function *F = nullptr;
1580 if (const MachineFunction *MF = getMFIfAvailable(*this)) {
1581 F = &MF->getFunction();
1582 M = F->getParent();
1583 if (!TII)
1584 TII = MF->getSubtarget().getInstrInfo();
1585 }
1586
1587 ModuleSlotTracker MST(M);
1588 if (F)
1589 MST.incorporateFunction(*F);
1590 print(OS, MST, IsStandalone, SkipOpers, SkipDebugLoc, AddNewLine, TII);
1591}
1592
1593void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST,
1594 bool IsStandalone, bool SkipOpers, bool SkipDebugLoc,
1595 bool AddNewLine, const TargetInstrInfo *TII) const {
1596 // We can be a bit tidier if we know the MachineFunction.
1597 const TargetRegisterInfo *TRI = nullptr;
1598 const MachineRegisterInfo *MRI = nullptr;
1599 const TargetIntrinsicInfo *IntrinsicInfo = nullptr;
1600 tryToGetTargetInfo(*this, TRI, MRI, IntrinsicInfo, TII);
1601
1602 if (isCFIInstruction())
1603 assert(getNumOperands() == 1 && "Expected 1 operand in CFI instruction")((getNumOperands() == 1 && "Expected 1 operand in CFI instruction"
) ? static_cast<void> (0) : __assert_fail ("getNumOperands() == 1 && \"Expected 1 operand in CFI instruction\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/MachineInstr.cpp"
, 1603, __PRETTY_FUNCTION__))
;
1604
1605 SmallBitVector PrintedTypes(8);
1606 bool ShouldPrintRegisterTies = IsStandalone || hasComplexRegisterTies();
1607 auto getTiedOperandIdx = [&](unsigned OpIdx) {
1608 if (!ShouldPrintRegisterTies)
1609 return 0U;
1610 const MachineOperand &MO = getOperand(OpIdx);
1611 if (MO.isReg() && MO.isTied() && !MO.isDef())
1612 return findTiedOperandIdx(OpIdx);
1613 return 0U;
1614 };
1615 unsigned StartOp = 0;
1616 unsigned e = getNumOperands();
1617
1618 // Print explicitly defined operands on the left of an assignment syntax.
1619 while (StartOp < e) {
1620 const MachineOperand &MO = getOperand(StartOp);
1621 if (!MO.isReg() || !MO.isDef() || MO.isImplicit())
1622 break;
1623
1624 if (StartOp != 0)
1625 OS << ", ";
1626
1627 LLT TypeToPrint = MRI ? getTypeToPrint(StartOp, PrintedTypes, *MRI) : LLT{};
1628 unsigned TiedOperandIdx = getTiedOperandIdx(StartOp);
1629 MO.print(OS, MST, TypeToPrint, StartOp, /*PrintDef=*/false, IsStandalone,
1630 ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1631 ++StartOp;
1632 }
1633
1634 if (StartOp != 0)
1635 OS << " = ";
1636
1637 if (getFlag(MachineInstr::FrameSetup))
1638 OS << "frame-setup ";
1639 if (getFlag(MachineInstr::FrameDestroy))
1640 OS << "frame-destroy ";
1641 if (getFlag(MachineInstr::FmNoNans))
1642 OS << "nnan ";
1643 if (getFlag(MachineInstr::FmNoInfs))
1644 OS << "ninf ";
1645 if (getFlag(MachineInstr::FmNsz))
1646 OS << "nsz ";
1647 if (getFlag(MachineInstr::FmArcp))
1648 OS << "arcp ";
1649 if (getFlag(MachineInstr::FmContract))
1650 OS << "contract ";
1651 if (getFlag(MachineInstr::FmAfn))
1652 OS << "afn ";
1653 if (getFlag(MachineInstr::FmReassoc))
1654 OS << "reassoc ";
1655 if (getFlag(MachineInstr::NoUWrap))
1656 OS << "nuw ";
1657 if (getFlag(MachineInstr::NoSWrap))
1658 OS << "nsw ";
1659 if (getFlag(MachineInstr::IsExact))
1660 OS << "exact ";
1661 if (getFlag(MachineInstr::NoFPExcept))
1662 OS << "nofpexcept ";
1663 if (getFlag(MachineInstr::NoMerge))
1664 OS << "nomerge ";
1665
1666 // Print the opcode name.
1667 if (TII)
1668 OS << TII->getName(getOpcode());
1669 else
1670 OS << "UNKNOWN";
1671
1672 if (SkipOpers)
1673 return;
1674
1675 // Print the rest of the operands.
1676 bool FirstOp = true;
1677 unsigned AsmDescOp = ~0u;
1678 unsigned AsmOpCount = 0;
1679
1680 if (isInlineAsm() && e >= InlineAsm::MIOp_FirstOperand) {
1681 // Print asm string.
1682 OS << " ";
1683 const unsigned OpIdx = InlineAsm::MIOp_AsmString;
1684 LLT TypeToPrint = MRI ? getTypeToPrint(OpIdx, PrintedTypes, *MRI) : LLT{};
1685 unsigned TiedOperandIdx = getTiedOperandIdx(OpIdx);
1686 getOperand(OpIdx).print(OS, MST, TypeToPrint, OpIdx, /*PrintDef=*/true, IsStandalone,
1687 ShouldPrintRegisterTies, TiedOperandIdx, TRI,
1688 IntrinsicInfo);
1689
1690 // Print HasSideEffects, MayLoad, MayStore, IsAlignStack
1691 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1692 if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1693 OS << " [sideeffect]";
1694 if (ExtraInfo & InlineAsm::Extra_MayLoad)
1695 OS << " [mayload]";
1696 if (ExtraInfo & InlineAsm::Extra_MayStore)
1697 OS << " [maystore]";
1698 if (ExtraInfo & InlineAsm::Extra_IsConvergent)
1699 OS << " [isconvergent]";
1700 if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
1701 OS << " [alignstack]";
1702 if (getInlineAsmDialect() == InlineAsm::AD_ATT)
1703 OS << " [attdialect]";
1704 if (getInlineAsmDialect() == InlineAsm::AD_Intel)
1705 OS << " [inteldialect]";
1706
1707 StartOp = AsmDescOp = InlineAsm::MIOp_FirstOperand;
1708 FirstOp = false;
1709 }
1710
1711 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
1712 const MachineOperand &MO = getOperand(i);
1713
1714 if (FirstOp) FirstOp = false; else OS << ",";
1715 OS << " ";
1716
1717 if (isDebugValue() && MO.isMetadata()) {
1718 // Pretty print DBG_VALUE instructions.
1719 auto *DIV = dyn_cast<DILocalVariable>(MO.getMetadata());
1720 if (DIV && !DIV->getName().empty())
1721 OS << "!\"" << DIV->getName() << '\"';
1722 else {
1723 LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};
1724 unsigned TiedOperandIdx = getTiedOperandIdx(i);
1725 MO.print(OS, MST, TypeToPrint, i, /*PrintDef=*/true, IsStandalone,
1726 ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1727 }
1728 } else if (isDebugLabel() && MO.isMetadata()) {
1729 // Pretty print DBG_LABEL instructions.
1730 auto *DIL = dyn_cast<DILabel>(MO.getMetadata());
1731 if (DIL && !DIL->getName().empty())
1732 OS << "\"" << DIL->getName() << '\"';
1733 else {
1734 LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};
1735 unsigned TiedOperandIdx = getTiedOperandIdx(i);
1736 MO.print(OS, MST, TypeToPrint, i, /*PrintDef=*/true, IsStandalone,
1737 ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1738 }
1739 } else if (i == AsmDescOp && MO.isImm()) {
1740 // Pretty print the inline asm operand descriptor.
1741 OS << '$' << AsmOpCount++;
1742 unsigned Flag = MO.getImm();
1743 OS << ":[";
1744 OS << InlineAsm::getKindName(InlineAsm::getKind(Flag));
1745
1746 unsigned RCID = 0;
1747 if (!InlineAsm::isImmKind(Flag) && !InlineAsm::isMemKind(Flag) &&
1748 InlineAsm::hasRegClassConstraint(Flag, RCID)) {
1749 if (TRI) {
1750 OS << ':' << TRI->getRegClassName(TRI->getRegClass(RCID));
1751 } else
1752 OS << ":RC" << RCID;
1753 }
1754
1755 if (InlineAsm::isMemKind(Flag)) {
1756 unsigned MCID = InlineAsm::getMemoryConstraintID(Flag);
1757 OS << ":" << InlineAsm::getMemConstraintName(MCID);
1758 }
1759
1760 unsigned TiedTo = 0;
1761 if (InlineAsm::isUseOperandTiedToDef(Flag, TiedTo))
1762 OS << " tiedto:$" << TiedTo;
1763
1764 OS << ']';
1765
1766 // Compute the index of the next operand descriptor.
1767 AsmDescOp += 1 + InlineAsm::getNumOperandRegisters(Flag);
1768 } else {
1769 LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};
1770 unsigned TiedOperandIdx = getTiedOperandIdx(i);
1771 if (MO.isImm() && isOperandSubregIdx(i))
1772 MachineOperand::printSubRegIdx(OS, MO.getImm(), TRI);
1773 else
1774 MO.print(OS, MST, TypeToPrint, i, /*PrintDef=*/true, IsStandalone,
1775 ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1776 }
1777 }
1778
1779 // Print any optional symbols attached to this instruction as-if they were
1780 // operands.
1781 if (MCSymbol *PreInstrSymbol = getPreInstrSymbol()) {
1782 if (!FirstOp) {
1783 FirstOp = false;
1784 OS << ',';
1785 }
1786 OS << " pre-instr-symbol ";
1787 MachineOperand::printSymbol(OS, *PreInstrSymbol);
1788 }
1789 if (MCSymbol *PostInstrSymbol = getPostInstrSymbol()) {
1790 if (!FirstOp) {
1791 FirstOp = false;
1792 OS << ',';
1793 }
1794 OS << " post-instr-symbol ";
1795 MachineOperand::printSymbol(OS, *PostInstrSymbol);
1796 }
1797 if (MDNode *HeapAllocMarker = getHeapAllocMarker()) {
1798 if (!FirstOp) {
1799 FirstOp = false;
1800 OS << ',';
1801 }
1802 OS << " heap-alloc-marker ";
1803 HeapAllocMarker->printAsOperand(OS, MST);
1804 }
1805
1806 if (DebugInstrNum) {
1807 if (!FirstOp)
1808 OS << ",";
1809 OS << " debug-instr-number " << DebugInstrNum;
1810 }
1811
1812 if (!SkipDebugLoc) {
1813 if (const DebugLoc &DL = getDebugLoc()) {
1814 if (!FirstOp)
1815 OS << ',';
1816 OS << " debug-location ";
1817 DL->printAsOperand(OS, MST);
1818 }
1819 }
1820
1821 if (!memoperands_empty()) {
1822 SmallVector<StringRef, 0> SSNs;
1823 const LLVMContext *Context = nullptr;
1824 std::unique_ptr<LLVMContext> CtxPtr;
1825 const MachineFrameInfo *MFI = nullptr;
1826 if (const MachineFunction *MF = getMFIfAvailable(*this)) {
1827 MFI = &MF->getFrameInfo();
1828 Context = &MF->getFunction().getContext();
1829 } else {
1830 CtxPtr = std::make_unique<LLVMContext>();
1831 Context = CtxPtr.get();
1832 }
1833
1834 OS << " :: ";
1835 bool NeedComma = false;
1836 for (const MachineMemOperand *Op : memoperands()) {
1837 if (NeedComma)
1838 OS << ", ";
1839 Op->print(OS, MST, SSNs, *Context, MFI, TII);
1840 NeedComma = true;
1841 }
1842 }
1843
1844 if (SkipDebugLoc)
1845 return;
1846
1847 bool HaveSemi = false;
1848
1849 // Print debug location information.
1850 if (const DebugLoc &DL = getDebugLoc()) {
1851 if (!HaveSemi) {
1852 OS << ';';
1853 HaveSemi = true;
1854 }
1855 OS << ' ';
1856 DL.print(OS);
1857 }
1858
1859 // Print extra comments for DEBUG_VALUE.
1860 if (isDebugValue() && getDebugVariableOp().isMetadata()) {
1861 if (!HaveSemi) {
1862 OS << ";";
1863 HaveSemi = true;
Value stored to 'HaveSemi' is never read
1864 }
1865 auto *DV = getDebugVariable();
1866 OS << " line no:" << DV->getLine();
1867 if (isIndirectDebugValue())
1868 OS << " indirect";
1869 }
1870 // TODO: DBG_LABEL
1871
1872 if (AddNewLine)
1873 OS << '\n';
1874}
1875
1876bool MachineInstr::addRegisterKilled(Register IncomingReg,
1877 const TargetRegisterInfo *RegInfo,
1878 bool AddIfNotFound) {
1879 bool isPhysReg = Register::isPhysicalRegister(IncomingReg);
1880 bool hasAliases = isPhysReg &&
1881 MCRegAliasIterator(IncomingReg, RegInfo, false).isValid();
1882 bool Found = false;
1883 SmallVector<unsigned,4> DeadOps;
1884 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1885 MachineOperand &MO = getOperand(i);
1886 if (!MO.isReg() || !MO.isUse() || MO.isUndef())
1887 continue;
1888
1889 // DEBUG_VALUE nodes do not contribute to code generation and should
1890 // always be ignored. Failure to do so may result in trying to modify
1891 // KILL flags on DEBUG_VALUE nodes.
1892 if (MO.isDebug())
1893 continue;
1894
1895 Register Reg = MO.getReg();
1896 if (!Reg)
1897 continue;
1898
1899 if (Reg == IncomingReg) {
1900 if (!Found) {
1901 if (MO.isKill())
1902 // The register is already marked kill.
1903 return true;
1904 if (isPhysReg && isRegTiedToDefOperand(i))
1905 // Two-address uses of physregs must not be marked kill.
1906 return true;
1907 MO.setIsKill();
1908 Found = true;
1909 }
1910 } else if (hasAliases && MO.isKill() && Register::isPhysicalRegister(Reg)) {
1911 // A super-register kill already exists.
1912 if (RegInfo->isSuperRegister(IncomingReg, Reg))
1913 return true;
1914 if (RegInfo->isSubRegister(IncomingReg, Reg))
1915 DeadOps.push_back(i);
1916 }
1917 }
1918
1919 // Trim unneeded kill operands.
1920 while (!DeadOps.empty()) {
1921 unsigned OpIdx = DeadOps.back();
1922 if (getOperand(OpIdx).isImplicit() &&
1923 (!isInlineAsm() || findInlineAsmFlagIdx(OpIdx) < 0))
1924 RemoveOperand(OpIdx);
1925 else
1926 getOperand(OpIdx).setIsKill(false);
1927 DeadOps.pop_back();
1928 }
1929
1930 // If not found, this means an alias of one of the operands is killed. Add a
1931 // new implicit operand if required.
1932 if (!Found && AddIfNotFound) {
1933 addOperand(MachineOperand::CreateReg(IncomingReg,
1934 false /*IsDef*/,
1935 true /*IsImp*/,
1936 true /*IsKill*/));
1937 return true;
1938 }
1939 return Found;
1940}
1941
1942void MachineInstr::clearRegisterKills(Register Reg,
1943 const TargetRegisterInfo *RegInfo) {
1944 if (!Register::isPhysicalRegister(Reg))
1945 RegInfo = nullptr;
1946 for (MachineOperand &MO : operands()) {
1947 if (!MO.isReg() || !MO.isUse() || !MO.isKill())
1948 continue;
1949 Register OpReg = MO.getReg();
1950 if ((RegInfo && RegInfo->regsOverlap(Reg, OpReg)) || Reg == OpReg)
1951 MO.setIsKill(false);
1952 }
1953}
1954
1955bool MachineInstr::addRegisterDead(Register Reg,
1956 const TargetRegisterInfo *RegInfo,
1957 bool AddIfNotFound) {
1958 bool isPhysReg = Register::isPhysicalRegister(Reg);
1959 bool hasAliases = isPhysReg &&
1960 MCRegAliasIterator(Reg, RegInfo, false).isValid();
1961 bool Found = false;
1962 SmallVector<unsigned,4> DeadOps;
1963 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1964 MachineOperand &MO = getOperand(i);
1965 if (!MO.isReg() || !MO.isDef())
1966 continue;
1967 Register MOReg = MO.getReg();
1968 if (!MOReg)
1969 continue;
1970
1971 if (MOReg == Reg) {
1972 MO.setIsDead();
1973 Found = true;
1974 } else if (hasAliases && MO.isDead() &&
1975 Register::isPhysicalRegister(MOReg)) {
1976 // There exists a super-register that's marked dead.
1977 if (RegInfo->isSuperRegister(Reg, MOReg))
1978 return true;
1979 if (RegInfo->isSubRegister(Reg, MOReg))
1980 DeadOps.push_back(i);
1981 }
1982 }
1983
1984 // Trim unneeded dead operands.
1985 while (!DeadOps.empty()) {
1986 unsigned OpIdx = DeadOps.back();
1987 if (getOperand(OpIdx).isImplicit() &&
1988 (!isInlineAsm() || findInlineAsmFlagIdx(OpIdx) < 0))
1989 RemoveOperand(OpIdx);
1990 else
1991 getOperand(OpIdx).setIsDead(false);
1992 DeadOps.pop_back();
1993 }
1994
1995 // If not found, this means an alias of one of the operands is dead. Add a
1996 // new implicit operand if required.
1997 if (Found || !AddIfNotFound)
1998 return Found;
1999
2000 addOperand(MachineOperand::CreateReg(Reg,
2001 true /*IsDef*/,
2002 true /*IsImp*/,
2003 false /*IsKill*/,
2004 true /*IsDead*/));
2005 return true;
2006}
2007
2008void MachineInstr::clearRegisterDeads(Register Reg) {
2009 for (MachineOperand &MO : operands()) {
2010 if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg)
2011 continue;
2012 MO.setIsDead(false);
2013 }
2014}
2015
2016void MachineInstr::setRegisterDefReadUndef(Register Reg, bool IsUndef) {
2017 for (MachineOperand &MO : operands()) {
2018 if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg || MO.getSubReg() == 0)
2019 continue;
2020 MO.setIsUndef(IsUndef);
2021 }
2022}
2023
2024void MachineInstr::addRegisterDefined(Register Reg,
2025 const TargetRegisterInfo *RegInfo) {
2026 if (Register::isPhysicalRegister(Reg)) {
2027 MachineOperand *MO = findRegisterDefOperand(Reg, false, false, RegInfo);
2028 if (MO)
2029 return;
2030 } else {
2031 for (const MachineOperand &MO : operands()) {
2032 if (MO.isReg() && MO.getReg() == Reg && MO.isDef() &&
2033 MO.getSubReg() == 0)
2034 return;
2035 }
2036 }
2037 addOperand(MachineOperand::CreateReg(Reg,
2038 true /*IsDef*/,
2039 true /*IsImp*/));
2040}
2041
2042void MachineInstr::setPhysRegsDeadExcept(ArrayRef<Register> UsedRegs,
2043 const TargetRegisterInfo &TRI) {
2044 bool HasRegMask = false;
2045 for (MachineOperand &MO : operands()) {
2046 if (MO.isRegMask()) {
2047 HasRegMask = true;
2048 continue;
2049 }
2050 if (!MO.isReg() || !MO.isDef()) continue;
2051 Register Reg = MO.getReg();
2052 if (!Reg.isPhysical())
2053 continue;
2054 // If there are no uses, including partial uses, the def is dead.
2055 if (llvm::none_of(UsedRegs,
2056 [&](MCRegister Use) { return TRI.regsOverlap(Use, Reg); }))
2057 MO.setIsDead();
2058 }
2059
2060 // This is a call with a register mask operand.
2061 // Mask clobbers are always dead, so add defs for the non-dead defines.
2062 if (HasRegMask)
2063 for (ArrayRef<Register>::iterator I = UsedRegs.begin(), E = UsedRegs.end();
2064 I != E; ++I)
2065 addRegisterDefined(*I, &TRI);
2066}
2067
2068unsigned
2069MachineInstrExpressionTrait::getHashValue(const MachineInstr* const &MI) {
2070 // Build up a buffer of hash code components.
2071 SmallVector<size_t, 16> HashComponents;
2072 HashComponents.reserve(MI->getNumOperands() + 1);
2073 HashComponents.push_back(MI->getOpcode());
2074 for (const MachineOperand &MO : MI->operands()) {
2075 if (MO.isReg() && MO.isDef() && Register::isVirtualRegister(MO.getReg()))
2076 continue; // Skip virtual register defs.
2077
2078 HashComponents.push_back(hash_value(MO));
2079 }
2080 return hash_combine_range(HashComponents.begin(), HashComponents.end());
2081}
2082
2083void MachineInstr::emitError(StringRef Msg) const {
2084 // Find the source location cookie.
2085 unsigned LocCookie = 0;
2086 const MDNode *LocMD = nullptr;
2087 for (unsigned i = getNumOperands(); i != 0; --i) {
2088 if (getOperand(i-1).isMetadata() &&
2089 (LocMD = getOperand(i-1).getMetadata()) &&
2090 LocMD->getNumOperands() != 0) {
2091 if (const ConstantInt *CI =
2092 mdconst::dyn_extract<ConstantInt>(LocMD->getOperand(0))) {
2093 LocCookie = CI->getZExtValue();
2094 break;
2095 }
2096 }
2097 }
2098
2099 if (const MachineBasicBlock *MBB = getParent())
2100 if (const MachineFunction *MF = MBB->getParent())
2101 return MF->getMMI().getModule()->getContext().emitError(LocCookie, Msg);
2102 report_fatal_error(Msg);
2103}
2104
2105MachineInstrBuilder llvm::BuildMI(MachineFunction &MF, const DebugLoc &DL,
2106 const MCInstrDesc &MCID, bool IsIndirect,
2107 Register Reg, const MDNode *Variable,
2108 const MDNode *Expr) {
2109 assert(isa<DILocalVariable>(Variable) && "not a variable")((isa<DILocalVariable>(Variable) && "not a variable"
) ? static_cast<void> (0) : __assert_fail ("isa<DILocalVariable>(Variable) && \"not a variable\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/MachineInstr.cpp"
, 2109, __PRETTY_FUNCTION__))
;
2110 assert(cast<DIExpression>(Expr)->isValid() && "not an expression")((cast<DIExpression>(Expr)->isValid() && "not an expression"
) ? static_cast<void> (0) : __assert_fail ("cast<DIExpression>(Expr)->isValid() && \"not an expression\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/MachineInstr.cpp"
, 2110, __PRETTY_FUNCTION__))
;
2111 assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&((cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic
(DL) && "Expected inlined-at fields to agree") ? static_cast
<void> (0) : __assert_fail ("cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) && \"Expected inlined-at fields to agree\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/MachineInstr.cpp"
, 2112, __PRETTY_FUNCTION__))
2112 "Expected inlined-at fields to agree")((cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic
(DL) && "Expected inlined-at fields to agree") ? static_cast
<void> (0) : __assert_fail ("cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) && \"Expected inlined-at fields to agree\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/MachineInstr.cpp"
, 2112, __PRETTY_FUNCTION__))
;
2113 auto MIB = BuildMI(MF, DL, MCID).addReg(Reg, RegState::Debug);
2114 if (IsIndirect)
2115 MIB.addImm(0U);
2116 else
2117 MIB.addReg(0U, RegState::Debug);
2118 return MIB.addMetadata(Variable).addMetadata(Expr);
2119}
2120
2121MachineInstrBuilder llvm::BuildMI(MachineFunction &MF, const DebugLoc &DL,
2122 const MCInstrDesc &MCID, bool IsIndirect,
2123 MachineOperand &MO, const MDNode *Variable,
2124 const MDNode *Expr) {
2125 assert(isa<DILocalVariable>(Variable) && "not a variable")((isa<DILocalVariable>(Variable) && "not a variable"
) ? static_cast<void> (0) : __assert_fail ("isa<DILocalVariable>(Variable) && \"not a variable\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/MachineInstr.cpp"
, 2125, __PRETTY_FUNCTION__))
;
2126 assert(cast<DIExpression>(Expr)->isValid() && "not an expression")((cast<DIExpression>(Expr)->isValid() && "not an expression"
) ? static_cast<void> (0) : __assert_fail ("cast<DIExpression>(Expr)->isValid() && \"not an expression\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/MachineInstr.cpp"
, 2126, __PRETTY_FUNCTION__))
;
2127 assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&((cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic
(DL) && "Expected inlined-at fields to agree") ? static_cast
<void> (0) : __assert_fail ("cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) && \"Expected inlined-at fields to agree\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/MachineInstr.cpp"
, 2128, __PRETTY_FUNCTION__))
2128 "Expected inlined-at fields to agree")((cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic
(DL) && "Expected inlined-at fields to agree") ? static_cast
<void> (0) : __assert_fail ("cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) && \"Expected inlined-at fields to agree\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/MachineInstr.cpp"
, 2128, __PRETTY_FUNCTION__))
;
2129 if (MO.isReg())
2130 return BuildMI(MF, DL, MCID, IsIndirect, MO.getReg(), Variable, Expr);
2131
2132 auto MIB = BuildMI(MF, DL, MCID).add(MO);
2133 if (IsIndirect)
2134 MIB.addImm(0U);
2135 else
2136 MIB.addReg(0U, RegState::Debug);
2137 return MIB.addMetadata(Variable).addMetadata(Expr);
2138 }
2139
2140MachineInstrBuilder llvm::BuildMI(MachineBasicBlock &BB,
2141 MachineBasicBlock::iterator I,
2142 const DebugLoc &DL, const MCInstrDesc &MCID,
2143 bool IsIndirect, Register Reg,
2144 const MDNode *Variable, const MDNode *Expr) {
2145 MachineFunction &MF = *BB.getParent();
2146 MachineInstr *MI = BuildMI(MF, DL, MCID, IsIndirect, Reg, Variable, Expr);
2147 BB.insert(I, MI);
2148 return MachineInstrBuilder(MF, MI);
2149}
2150
2151MachineInstrBuilder llvm::BuildMI(MachineBasicBlock &BB,
2152 MachineBasicBlock::iterator I,
2153 const DebugLoc &DL, const MCInstrDesc &MCID,
2154 bool IsIndirect, MachineOperand &MO,
2155 const MDNode *Variable, const MDNode *Expr) {
2156 MachineFunction &MF = *BB.getParent();
2157 MachineInstr *MI = BuildMI(MF, DL, MCID, IsIndirect, MO, Variable, Expr);
2158 BB.insert(I, MI);
2159 return MachineInstrBuilder(MF, *MI);
2160}
2161
2162/// Compute the new DIExpression to use with a DBG_VALUE for a spill slot.
2163/// This prepends DW_OP_deref when spilling an indirect DBG_VALUE.
2164static const DIExpression *computeExprForSpill(const MachineInstr &MI) {
2165 assert(MI.getOperand(0).isReg() && "can't spill non-register")((MI.getOperand(0).isReg() && "can't spill non-register"
) ? static_cast<void> (0) : __assert_fail ("MI.getOperand(0).isReg() && \"can't spill non-register\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/MachineInstr.cpp"
, 2165, __PRETTY_FUNCTION__))
;
2166 assert(MI.getDebugVariable()->isValidLocationForIntrinsic(MI.getDebugLoc()) &&((MI.getDebugVariable()->isValidLocationForIntrinsic(MI.getDebugLoc
()) && "Expected inlined-at fields to agree") ? static_cast
<void> (0) : __assert_fail ("MI.getDebugVariable()->isValidLocationForIntrinsic(MI.getDebugLoc()) && \"Expected inlined-at fields to agree\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/MachineInstr.cpp"
, 2167, __PRETTY_FUNCTION__))
2167 "Expected inlined-at fields to agree")((MI.getDebugVariable()->isValidLocationForIntrinsic(MI.getDebugLoc
()) && "Expected inlined-at fields to agree") ? static_cast
<void> (0) : __assert_fail ("MI.getDebugVariable()->isValidLocationForIntrinsic(MI.getDebugLoc()) && \"Expected inlined-at fields to agree\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/MachineInstr.cpp"
, 2167, __PRETTY_FUNCTION__))
;
2168
2169 const DIExpression *Expr = MI.getDebugExpression();
2170 if (MI.isIndirectDebugValue()) {
2171 assert(MI.getDebugOffset().getImm() == 0 &&((MI.getDebugOffset().getImm() == 0 && "DBG_VALUE with nonzero offset"
) ? static_cast<void> (0) : __assert_fail ("MI.getDebugOffset().getImm() == 0 && \"DBG_VALUE with nonzero offset\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/MachineInstr.cpp"
, 2172, __PRETTY_FUNCTION__))
2172 "DBG_VALUE with nonzero offset")((MI.getDebugOffset().getImm() == 0 && "DBG_VALUE with nonzero offset"
) ? static_cast<void> (0) : __assert_fail ("MI.getDebugOffset().getImm() == 0 && \"DBG_VALUE with nonzero offset\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/MachineInstr.cpp"
, 2172, __PRETTY_FUNCTION__))
;
2173 Expr = DIExpression::prepend(Expr, DIExpression::DerefBefore);
2174 }
2175 return Expr;
2176}
2177
2178MachineInstr *llvm::buildDbgValueForSpill(MachineBasicBlock &BB,
2179 MachineBasicBlock::iterator I,
2180 const MachineInstr &Orig,
2181 int FrameIndex) {
2182 const DIExpression *Expr = computeExprForSpill(Orig);
2183 return BuildMI(BB, I, Orig.getDebugLoc(), Orig.getDesc())
2184 .addFrameIndex(FrameIndex)
2185 .addImm(0U)
2186 .addMetadata(Orig.getDebugVariable())
2187 .addMetadata(Expr);
2188}
2189
2190void llvm::updateDbgValueForSpill(MachineInstr &Orig, int FrameIndex) {
2191 const DIExpression *Expr = computeExprForSpill(Orig);
2192 Orig.getDebugOperand(0).ChangeToFrameIndex(FrameIndex);
2193 Orig.getDebugOffset().ChangeToImmediate(0U);
2194 Orig.getDebugExpressionOp().setMetadata(Expr);
2195}
2196
2197void MachineInstr::collectDebugValues(
2198 SmallVectorImpl<MachineInstr *> &DbgValues) {
2199 MachineInstr &MI = *this;
2200 if (!MI.getOperand(0).isReg())
2201 return;
2202
2203 MachineBasicBlock::iterator DI = MI; ++DI;
2204 for (MachineBasicBlock::iterator DE = MI.getParent()->end();
2205 DI != DE; ++DI) {
2206 if (!DI->isDebugValue())
2207 return;
2208 if (DI->getDebugOperandForReg(MI.getOperand(0).getReg()))
2209 DbgValues.push_back(&*DI);
2210 }
2211}
2212
2213void MachineInstr::changeDebugValuesDefReg(Register Reg) {
2214 // Collect matching debug values.
2215 SmallVector<MachineInstr *, 2> DbgValues;
2216
2217 if (!getOperand(0).isReg())
2218 return;
2219
2220 Register DefReg = getOperand(0).getReg();
2221 auto *MRI = getRegInfo();
2222 for (auto &MO : MRI->use_operands(DefReg)) {
2223 auto *DI = MO.getParent();
2224 if (!DI->isDebugValue())
2225 continue;
2226 if (DI->getDebugOperandForReg(DefReg)) {
2227 DbgValues.push_back(DI);
2228 }
2229 }
2230
2231 // Propagate Reg to debug value instructions.
2232 for (auto *DBI : DbgValues)
2233 DBI->getDebugOperandForReg(DefReg)->setReg(Reg);
2234}
2235
2236using MMOList = SmallVector<const MachineMemOperand *, 2>;
2237
2238static unsigned getSpillSlotSize(const MMOList &Accesses,
2239 const MachineFrameInfo &MFI) {
2240 unsigned Size = 0;
2241 for (auto A : Accesses)
2242 if (MFI.isSpillSlotObjectIndex(
2243 cast<FixedStackPseudoSourceValue>(A->getPseudoValue())
2244 ->getFrameIndex()))
2245 Size += A->getSize();
2246 return Size;
2247}
2248
2249Optional<unsigned>
2250MachineInstr::getSpillSize(const TargetInstrInfo *TII) const {
2251 int FI;
2252 if (TII->isStoreToStackSlotPostFE(*this, FI)) {
2253 const MachineFrameInfo &MFI = getMF()->getFrameInfo();
2254 if (MFI.isSpillSlotObjectIndex(FI))
2255 return (*memoperands_begin())->getSize();
2256 }
2257 return None;
2258}
2259
2260Optional<unsigned>
2261MachineInstr::getFoldedSpillSize(const TargetInstrInfo *TII) const {
2262 MMOList Accesses;
2263 if (TII->hasStoreToStackSlot(*this, Accesses))
2264 return getSpillSlotSize(Accesses, getMF()->getFrameInfo());
2265 return None;
2266}
2267
2268Optional<unsigned>
2269MachineInstr::getRestoreSize(const TargetInstrInfo *TII) const {
2270 int FI;
2271 if (TII->isLoadFromStackSlotPostFE(*this, FI)) {
2272 const MachineFrameInfo &MFI = getMF()->getFrameInfo();
2273 if (MFI.isSpillSlotObjectIndex(FI))
2274 return (*memoperands_begin())->getSize();
2275 }
2276 return None;
2277}
2278
2279Optional<unsigned>
2280MachineInstr::getFoldedRestoreSize(const TargetInstrInfo *TII) const {
2281 MMOList Accesses;
2282 if (TII->hasLoadFromStackSlot(*this, Accesses))
2283 return getSpillSlotSize(Accesses, getMF()->getFrameInfo());
2284 return None;
2285}
2286
2287unsigned MachineInstr::getDebugInstrNum() {
2288 if (DebugInstrNum == 0)
2289 DebugInstrNum = getParent()->getParent()->getNewDebugInstrNum();
2290 return DebugInstrNum;
2291}