Bug Summary

File:llvm/lib/CodeGen/MachineInstr.cpp
Warning:line 1764, column 7
Value stored to 'HaveSemi' is never read

Annotated Source Code

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clang -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name MachineInstr.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mthread-model posix -mframe-pointer=none -fmath-errno -fno-rounding-math -masm-verbose -mconstructor-aliases -munwind-tables -fuse-init-array -target-cpu x86-64 -dwarf-column-info -debugger-tuning=gdb -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-10/lib/clang/10.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/build-llvm/lib/CodeGen -I /build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen -I /build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/build-llvm/include -I /build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0/backward -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-10/lib/clang/10.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++14 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/build-llvm/lib/CodeGen -fdebug-prefix-map=/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809=. -ferror-limit 19 -fmessage-length 0 -fvisibility-inlines-hidden -stack-protector 2 -fgnuc-version=4.2.1 -fobjc-runtime=gcc -fdiagnostics-show-option -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -o /tmp/scan-build-2019-12-11-181444-25759-1 -x c++ /build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/MachineInstr.cpp
1//===- lib/CodeGen/MachineInstr.cpp ---------------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// Methods common to all machine instructions.
10//
11//===----------------------------------------------------------------------===//
12
13#include "llvm/CodeGen/MachineInstr.h"
14#include "llvm/ADT/APFloat.h"
15#include "llvm/ADT/ArrayRef.h"
16#include "llvm/ADT/FoldingSet.h"
17#include "llvm/ADT/Hashing.h"
18#include "llvm/ADT/None.h"
19#include "llvm/ADT/STLExtras.h"
20#include "llvm/ADT/SmallBitVector.h"
21#include "llvm/ADT/SmallString.h"
22#include "llvm/ADT/SmallVector.h"
23#include "llvm/Analysis/AliasAnalysis.h"
24#include "llvm/Analysis/Loads.h"
25#include "llvm/Analysis/MemoryLocation.h"
26#include "llvm/CodeGen/GlobalISel/RegisterBank.h"
27#include "llvm/CodeGen/MachineBasicBlock.h"
28#include "llvm/CodeGen/MachineFrameInfo.h"
29#include "llvm/CodeGen/MachineFunction.h"
30#include "llvm/CodeGen/MachineInstrBuilder.h"
31#include "llvm/CodeGen/MachineInstrBundle.h"
32#include "llvm/CodeGen/MachineMemOperand.h"
33#include "llvm/CodeGen/MachineModuleInfo.h"
34#include "llvm/CodeGen/MachineOperand.h"
35#include "llvm/CodeGen/MachineRegisterInfo.h"
36#include "llvm/CodeGen/PseudoSourceValue.h"
37#include "llvm/CodeGen/TargetInstrInfo.h"
38#include "llvm/CodeGen/TargetRegisterInfo.h"
39#include "llvm/CodeGen/TargetSubtargetInfo.h"
40#include "llvm/Config/llvm-config.h"
41#include "llvm/IR/Constants.h"
42#include "llvm/IR/DebugInfoMetadata.h"
43#include "llvm/IR/DebugLoc.h"
44#include "llvm/IR/DerivedTypes.h"
45#include "llvm/IR/Function.h"
46#include "llvm/IR/InlineAsm.h"
47#include "llvm/IR/InstrTypes.h"
48#include "llvm/IR/Intrinsics.h"
49#include "llvm/IR/LLVMContext.h"
50#include "llvm/IR/Metadata.h"
51#include "llvm/IR/Module.h"
52#include "llvm/IR/ModuleSlotTracker.h"
53#include "llvm/IR/Operator.h"
54#include "llvm/IR/Type.h"
55#include "llvm/IR/Value.h"
56#include "llvm/MC/MCInstrDesc.h"
57#include "llvm/MC/MCRegisterInfo.h"
58#include "llvm/MC/MCSymbol.h"
59#include "llvm/Support/Casting.h"
60#include "llvm/Support/CommandLine.h"
61#include "llvm/Support/Compiler.h"
62#include "llvm/Support/Debug.h"
63#include "llvm/Support/ErrorHandling.h"
64#include "llvm/Support/LowLevelTypeImpl.h"
65#include "llvm/Support/MathExtras.h"
66#include "llvm/Support/raw_ostream.h"
67#include "llvm/Target/TargetIntrinsicInfo.h"
68#include "llvm/Target/TargetMachine.h"
69#include <algorithm>
70#include <cassert>
71#include <cstddef>
72#include <cstdint>
73#include <cstring>
74#include <iterator>
75#include <utility>
76
77using namespace llvm;
78
79static const MachineFunction *getMFIfAvailable(const MachineInstr &MI) {
80 if (const MachineBasicBlock *MBB = MI.getParent())
81 if (const MachineFunction *MF = MBB->getParent())
82 return MF;
83 return nullptr;
84}
85
86// Try to crawl up to the machine function and get TRI and IntrinsicInfo from
87// it.
88static void tryToGetTargetInfo(const MachineInstr &MI,
89 const TargetRegisterInfo *&TRI,
90 const MachineRegisterInfo *&MRI,
91 const TargetIntrinsicInfo *&IntrinsicInfo,
92 const TargetInstrInfo *&TII) {
93
94 if (const MachineFunction *MF = getMFIfAvailable(MI)) {
95 TRI = MF->getSubtarget().getRegisterInfo();
96 MRI = &MF->getRegInfo();
97 IntrinsicInfo = MF->getTarget().getIntrinsicInfo();
98 TII = MF->getSubtarget().getInstrInfo();
99 }
100}
101
102void MachineInstr::addImplicitDefUseOperands(MachineFunction &MF) {
103 if (MCID->ImplicitDefs)
104 for (const MCPhysReg *ImpDefs = MCID->getImplicitDefs(); *ImpDefs;
105 ++ImpDefs)
106 addOperand(MF, MachineOperand::CreateReg(*ImpDefs, true, true));
107 if (MCID->ImplicitUses)
108 for (const MCPhysReg *ImpUses = MCID->getImplicitUses(); *ImpUses;
109 ++ImpUses)
110 addOperand(MF, MachineOperand::CreateReg(*ImpUses, false, true));
111}
112
113/// MachineInstr ctor - This constructor creates a MachineInstr and adds the
114/// implicit operands. It reserves space for the number of operands specified by
115/// the MCInstrDesc.
116MachineInstr::MachineInstr(MachineFunction &MF, const MCInstrDesc &tid,
117 DebugLoc dl, bool NoImp)
118 : MCID(&tid), debugLoc(std::move(dl)) {
119 assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor")((debugLoc.hasTrivialDestructor() && "Expected trivial destructor"
) ? static_cast<void> (0) : __assert_fail ("debugLoc.hasTrivialDestructor() && \"Expected trivial destructor\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/MachineInstr.cpp"
, 119, __PRETTY_FUNCTION__))
;
120
121 // Reserve space for the expected number of operands.
122 if (unsigned NumOps = MCID->getNumOperands() +
123 MCID->getNumImplicitDefs() + MCID->getNumImplicitUses()) {
124 CapOperands = OperandCapacity::get(NumOps);
125 Operands = MF.allocateOperandArray(CapOperands);
126 }
127
128 if (!NoImp)
129 addImplicitDefUseOperands(MF);
130}
131
132/// MachineInstr ctor - Copies MachineInstr arg exactly
133///
134MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
135 : MCID(&MI.getDesc()), Info(MI.Info), debugLoc(MI.getDebugLoc()) {
136 assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor")((debugLoc.hasTrivialDestructor() && "Expected trivial destructor"
) ? static_cast<void> (0) : __assert_fail ("debugLoc.hasTrivialDestructor() && \"Expected trivial destructor\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/MachineInstr.cpp"
, 136, __PRETTY_FUNCTION__))
;
137
138 CapOperands = OperandCapacity::get(MI.getNumOperands());
139 Operands = MF.allocateOperandArray(CapOperands);
140
141 // Copy operands.
142 for (const MachineOperand &MO : MI.operands())
143 addOperand(MF, MO);
144
145 // Copy all the sensible flags.
146 setFlags(MI.Flags);
147}
148
149/// getRegInfo - If this instruction is embedded into a MachineFunction,
150/// return the MachineRegisterInfo object for the current function, otherwise
151/// return null.
152MachineRegisterInfo *MachineInstr::getRegInfo() {
153 if (MachineBasicBlock *MBB = getParent())
154 return &MBB->getParent()->getRegInfo();
155 return nullptr;
156}
157
158/// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
159/// this instruction from their respective use lists. This requires that the
160/// operands already be on their use lists.
161void MachineInstr::RemoveRegOperandsFromUseLists(MachineRegisterInfo &MRI) {
162 for (MachineOperand &MO : operands())
163 if (MO.isReg())
164 MRI.removeRegOperandFromUseList(&MO);
165}
166
167/// AddRegOperandsToUseLists - Add all of the register operands in
168/// this instruction from their respective use lists. This requires that the
169/// operands not be on their use lists yet.
170void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &MRI) {
171 for (MachineOperand &MO : operands())
172 if (MO.isReg())
173 MRI.addRegOperandToUseList(&MO);
174}
175
176void MachineInstr::addOperand(const MachineOperand &Op) {
177 MachineBasicBlock *MBB = getParent();
178 assert(MBB && "Use MachineInstrBuilder to add operands to dangling instrs")((MBB && "Use MachineInstrBuilder to add operands to dangling instrs"
) ? static_cast<void> (0) : __assert_fail ("MBB && \"Use MachineInstrBuilder to add operands to dangling instrs\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/MachineInstr.cpp"
, 178, __PRETTY_FUNCTION__))
;
179 MachineFunction *MF = MBB->getParent();
180 assert(MF && "Use MachineInstrBuilder to add operands to dangling instrs")((MF && "Use MachineInstrBuilder to add operands to dangling instrs"
) ? static_cast<void> (0) : __assert_fail ("MF && \"Use MachineInstrBuilder to add operands to dangling instrs\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/MachineInstr.cpp"
, 180, __PRETTY_FUNCTION__))
;
181 addOperand(*MF, Op);
182}
183
184/// Move NumOps MachineOperands from Src to Dst, with support for overlapping
185/// ranges. If MRI is non-null also update use-def chains.
186static void moveOperands(MachineOperand *Dst, MachineOperand *Src,
187 unsigned NumOps, MachineRegisterInfo *MRI) {
188 if (MRI)
189 return MRI->moveOperands(Dst, Src, NumOps);
190
191 // MachineOperand is a trivially copyable type so we can just use memmove.
192 std::memmove(Dst, Src, NumOps * sizeof(MachineOperand));
193}
194
195/// addOperand - Add the specified operand to the instruction. If it is an
196/// implicit operand, it is added to the end of the operand list. If it is
197/// an explicit operand it is added at the end of the explicit operand list
198/// (before the first implicit operand).
199void MachineInstr::addOperand(MachineFunction &MF, const MachineOperand &Op) {
200 assert(MCID && "Cannot add operands before providing an instr descriptor")((MCID && "Cannot add operands before providing an instr descriptor"
) ? static_cast<void> (0) : __assert_fail ("MCID && \"Cannot add operands before providing an instr descriptor\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/MachineInstr.cpp"
, 200, __PRETTY_FUNCTION__))
;
201
202 // Check if we're adding one of our existing operands.
203 if (&Op >= Operands && &Op < Operands + NumOperands) {
204 // This is unusual: MI->addOperand(MI->getOperand(i)).
205 // If adding Op requires reallocating or moving existing operands around,
206 // the Op reference could go stale. Support it by copying Op.
207 MachineOperand CopyOp(Op);
208 return addOperand(MF, CopyOp);
209 }
210
211 // Find the insert location for the new operand. Implicit registers go at
212 // the end, everything else goes before the implicit regs.
213 //
214 // FIXME: Allow mixed explicit and implicit operands on inline asm.
215 // InstrEmitter::EmitSpecialNode() is marking inline asm clobbers as
216 // implicit-defs, but they must not be moved around. See the FIXME in
217 // InstrEmitter.cpp.
218 unsigned OpNo = getNumOperands();
219 bool isImpReg = Op.isReg() && Op.isImplicit();
220 if (!isImpReg && !isInlineAsm()) {
221 while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) {
222 --OpNo;
223 assert(!Operands[OpNo].isTied() && "Cannot move tied operands")((!Operands[OpNo].isTied() && "Cannot move tied operands"
) ? static_cast<void> (0) : __assert_fail ("!Operands[OpNo].isTied() && \"Cannot move tied operands\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/MachineInstr.cpp"
, 223, __PRETTY_FUNCTION__))
;
224 }
225 }
226
227#ifndef NDEBUG
228 bool isDebugOp = Op.getType() == MachineOperand::MO_Metadata ||
229 Op.getType() == MachineOperand::MO_MCSymbol;
230 // OpNo now points as the desired insertion point. Unless this is a variadic
231 // instruction, only implicit regs are allowed beyond MCID->getNumOperands().
232 // RegMask operands go between the explicit and implicit operands.
233 assert((isImpReg || Op.isRegMask() || MCID->isVariadic() ||(((isImpReg || Op.isRegMask() || MCID->isVariadic() || OpNo
< MCID->getNumOperands() || isDebugOp) && "Trying to add an operand to a machine instr that is already done!"
) ? static_cast<void> (0) : __assert_fail ("(isImpReg || Op.isRegMask() || MCID->isVariadic() || OpNo < MCID->getNumOperands() || isDebugOp) && \"Trying to add an operand to a machine instr that is already done!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/MachineInstr.cpp"
, 235, __PRETTY_FUNCTION__))
234 OpNo < MCID->getNumOperands() || isDebugOp) &&(((isImpReg || Op.isRegMask() || MCID->isVariadic() || OpNo
< MCID->getNumOperands() || isDebugOp) && "Trying to add an operand to a machine instr that is already done!"
) ? static_cast<void> (0) : __assert_fail ("(isImpReg || Op.isRegMask() || MCID->isVariadic() || OpNo < MCID->getNumOperands() || isDebugOp) && \"Trying to add an operand to a machine instr that is already done!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/MachineInstr.cpp"
, 235, __PRETTY_FUNCTION__))
235 "Trying to add an operand to a machine instr that is already done!")(((isImpReg || Op.isRegMask() || MCID->isVariadic() || OpNo
< MCID->getNumOperands() || isDebugOp) && "Trying to add an operand to a machine instr that is already done!"
) ? static_cast<void> (0) : __assert_fail ("(isImpReg || Op.isRegMask() || MCID->isVariadic() || OpNo < MCID->getNumOperands() || isDebugOp) && \"Trying to add an operand to a machine instr that is already done!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/MachineInstr.cpp"
, 235, __PRETTY_FUNCTION__))
;
236#endif
237
238 MachineRegisterInfo *MRI = getRegInfo();
239
240 // Determine if the Operands array needs to be reallocated.
241 // Save the old capacity and operand array.
242 OperandCapacity OldCap = CapOperands;
243 MachineOperand *OldOperands = Operands;
244 if (!OldOperands || OldCap.getSize() == getNumOperands()) {
245 CapOperands = OldOperands ? OldCap.getNext() : OldCap.get(1);
246 Operands = MF.allocateOperandArray(CapOperands);
247 // Move the operands before the insertion point.
248 if (OpNo)
249 moveOperands(Operands, OldOperands, OpNo, MRI);
250 }
251
252 // Move the operands following the insertion point.
253 if (OpNo != NumOperands)
254 moveOperands(Operands + OpNo + 1, OldOperands + OpNo, NumOperands - OpNo,
255 MRI);
256 ++NumOperands;
257
258 // Deallocate the old operand array.
259 if (OldOperands != Operands && OldOperands)
260 MF.deallocateOperandArray(OldCap, OldOperands);
261
262 // Copy Op into place. It still needs to be inserted into the MRI use lists.
263 MachineOperand *NewMO = new (Operands + OpNo) MachineOperand(Op);
264 NewMO->ParentMI = this;
265
266 // When adding a register operand, tell MRI about it.
267 if (NewMO->isReg()) {
268 // Ensure isOnRegUseList() returns false, regardless of Op's status.
269 NewMO->Contents.Reg.Prev = nullptr;
270 // Ignore existing ties. This is not a property that can be copied.
271 NewMO->TiedTo = 0;
272 // Add the new operand to MRI, but only for instructions in an MBB.
273 if (MRI)
274 MRI->addRegOperandToUseList(NewMO);
275 // The MCID operand information isn't accurate until we start adding
276 // explicit operands. The implicit operands are added first, then the
277 // explicits are inserted before them.
278 if (!isImpReg) {
279 // Tie uses to defs as indicated in MCInstrDesc.
280 if (NewMO->isUse()) {
281 int DefIdx = MCID->getOperandConstraint(OpNo, MCOI::TIED_TO);
282 if (DefIdx != -1)
283 tieOperands(DefIdx, OpNo);
284 }
285 // If the register operand is flagged as early, mark the operand as such.
286 if (MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1)
287 NewMO->setIsEarlyClobber(true);
288 }
289 }
290}
291
292/// RemoveOperand - Erase an operand from an instruction, leaving it with one
293/// fewer operand than it started with.
294///
295void MachineInstr::RemoveOperand(unsigned OpNo) {
296 assert(OpNo < getNumOperands() && "Invalid operand number")((OpNo < getNumOperands() && "Invalid operand number"
) ? static_cast<void> (0) : __assert_fail ("OpNo < getNumOperands() && \"Invalid operand number\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/MachineInstr.cpp"
, 296, __PRETTY_FUNCTION__))
;
297 untieRegOperand(OpNo);
298
299#ifndef NDEBUG
300 // Moving tied operands would break the ties.
301 for (unsigned i = OpNo + 1, e = getNumOperands(); i != e; ++i)
302 if (Operands[i].isReg())
303 assert(!Operands[i].isTied() && "Cannot move tied operands")((!Operands[i].isTied() && "Cannot move tied operands"
) ? static_cast<void> (0) : __assert_fail ("!Operands[i].isTied() && \"Cannot move tied operands\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/MachineInstr.cpp"
, 303, __PRETTY_FUNCTION__))
;
304#endif
305
306 MachineRegisterInfo *MRI = getRegInfo();
307 if (MRI && Operands[OpNo].isReg())
308 MRI->removeRegOperandFromUseList(Operands + OpNo);
309
310 // Don't call the MachineOperand destructor. A lot of this code depends on
311 // MachineOperand having a trivial destructor anyway, and adding a call here
312 // wouldn't make it 'destructor-correct'.
313
314 if (unsigned N = NumOperands - 1 - OpNo)
315 moveOperands(Operands + OpNo, Operands + OpNo + 1, N, MRI);
316 --NumOperands;
317}
318
319void MachineInstr::setExtraInfo(MachineFunction &MF,
320 ArrayRef<MachineMemOperand *> MMOs,
321 MCSymbol *PreInstrSymbol,
322 MCSymbol *PostInstrSymbol,
323 MDNode *HeapAllocMarker) {
324 bool HasPreInstrSymbol = PreInstrSymbol != nullptr;
325 bool HasPostInstrSymbol = PostInstrSymbol != nullptr;
326 bool HasHeapAllocMarker = HeapAllocMarker != nullptr;
327 int NumPointers =
328 MMOs.size() + HasPreInstrSymbol + HasPostInstrSymbol + HasHeapAllocMarker;
329
330 // Drop all extra info if there is none.
331 if (NumPointers <= 0) {
332 Info.clear();
333 return;
334 }
335
336 // If more than one pointer, then store out of line. Store heap alloc markers
337 // out of line because PointerSumType cannot hold more than 4 tag types with
338 // 32-bit pointers.
339 // FIXME: Maybe we should make the symbols in the extra info mutable?
340 else if (NumPointers > 1 || HasHeapAllocMarker) {
341 Info.set<EIIK_OutOfLine>(MF.createMIExtraInfo(
342 MMOs, PreInstrSymbol, PostInstrSymbol, HeapAllocMarker));
343 return;
344 }
345
346 // Otherwise store the single pointer inline.
347 if (HasPreInstrSymbol)
348 Info.set<EIIK_PreInstrSymbol>(PreInstrSymbol);
349 else if (HasPostInstrSymbol)
350 Info.set<EIIK_PostInstrSymbol>(PostInstrSymbol);
351 else
352 Info.set<EIIK_MMO>(MMOs[0]);
353}
354
355void MachineInstr::dropMemRefs(MachineFunction &MF) {
356 if (memoperands_empty())
357 return;
358
359 setExtraInfo(MF, {}, getPreInstrSymbol(), getPostInstrSymbol(),
360 getHeapAllocMarker());
361}
362
363void MachineInstr::setMemRefs(MachineFunction &MF,
364 ArrayRef<MachineMemOperand *> MMOs) {
365 if (MMOs.empty()) {
366 dropMemRefs(MF);
367 return;
368 }
369
370 setExtraInfo(MF, MMOs, getPreInstrSymbol(), getPostInstrSymbol(),
371 getHeapAllocMarker());
372}
373
374void MachineInstr::addMemOperand(MachineFunction &MF,
375 MachineMemOperand *MO) {
376 SmallVector<MachineMemOperand *, 2> MMOs;
377 MMOs.append(memoperands_begin(), memoperands_end());
378 MMOs.push_back(MO);
379 setMemRefs(MF, MMOs);
380}
381
382void MachineInstr::cloneMemRefs(MachineFunction &MF, const MachineInstr &MI) {
383 if (this == &MI)
384 // Nothing to do for a self-clone!
385 return;
386
387 assert(&MF == MI.getMF() &&((&MF == MI.getMF() && "Invalid machine functions when cloning memory refrences!"
) ? static_cast<void> (0) : __assert_fail ("&MF == MI.getMF() && \"Invalid machine functions when cloning memory refrences!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/MachineInstr.cpp"
, 388, __PRETTY_FUNCTION__))
388 "Invalid machine functions when cloning memory refrences!")((&MF == MI.getMF() && "Invalid machine functions when cloning memory refrences!"
) ? static_cast<void> (0) : __assert_fail ("&MF == MI.getMF() && \"Invalid machine functions when cloning memory refrences!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/MachineInstr.cpp"
, 388, __PRETTY_FUNCTION__))
;
389 // See if we can just steal the extra info already allocated for the
390 // instruction. We can do this whenever the pre- and post-instruction symbols
391 // are the same (including null).
392 if (getPreInstrSymbol() == MI.getPreInstrSymbol() &&
393 getPostInstrSymbol() == MI.getPostInstrSymbol() &&
394 getHeapAllocMarker() == MI.getHeapAllocMarker()) {
395 Info = MI.Info;
396 return;
397 }
398
399 // Otherwise, fall back on a copy-based clone.
400 setMemRefs(MF, MI.memoperands());
401}
402
403/// Check to see if the MMOs pointed to by the two MemRefs arrays are
404/// identical.
405static bool hasIdenticalMMOs(ArrayRef<MachineMemOperand *> LHS,
406 ArrayRef<MachineMemOperand *> RHS) {
407 if (LHS.size() != RHS.size())
408 return false;
409
410 auto LHSPointees = make_pointee_range(LHS);
411 auto RHSPointees = make_pointee_range(RHS);
412 return std::equal(LHSPointees.begin(), LHSPointees.end(),
413 RHSPointees.begin());
414}
415
416void MachineInstr::cloneMergedMemRefs(MachineFunction &MF,
417 ArrayRef<const MachineInstr *> MIs) {
418 // Try handling easy numbers of MIs with simpler mechanisms.
419 if (MIs.empty()) {
420 dropMemRefs(MF);
421 return;
422 }
423 if (MIs.size() == 1) {
424 cloneMemRefs(MF, *MIs[0]);
425 return;
426 }
427 // Because an empty memoperands list provides *no* information and must be
428 // handled conservatively (assuming the instruction can do anything), the only
429 // way to merge with it is to drop all other memoperands.
430 if (MIs[0]->memoperands_empty()) {
431 dropMemRefs(MF);
432 return;
433 }
434
435 // Handle the general case.
436 SmallVector<MachineMemOperand *, 2> MergedMMOs;
437 // Start with the first instruction.
438 assert(&MF == MIs[0]->getMF() &&((&MF == MIs[0]->getMF() && "Invalid machine functions when cloning memory references!"
) ? static_cast<void> (0) : __assert_fail ("&MF == MIs[0]->getMF() && \"Invalid machine functions when cloning memory references!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/MachineInstr.cpp"
, 439, __PRETTY_FUNCTION__))
439 "Invalid machine functions when cloning memory references!")((&MF == MIs[0]->getMF() && "Invalid machine functions when cloning memory references!"
) ? static_cast<void> (0) : __assert_fail ("&MF == MIs[0]->getMF() && \"Invalid machine functions when cloning memory references!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/MachineInstr.cpp"
, 439, __PRETTY_FUNCTION__))
;
440 MergedMMOs.append(MIs[0]->memoperands_begin(), MIs[0]->memoperands_end());
441 // Now walk all the other instructions and accumulate any different MMOs.
442 for (const MachineInstr &MI : make_pointee_range(MIs.slice(1))) {
443 assert(&MF == MI.getMF() &&((&MF == MI.getMF() && "Invalid machine functions when cloning memory references!"
) ? static_cast<void> (0) : __assert_fail ("&MF == MI.getMF() && \"Invalid machine functions when cloning memory references!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/MachineInstr.cpp"
, 444, __PRETTY_FUNCTION__))
444 "Invalid machine functions when cloning memory references!")((&MF == MI.getMF() && "Invalid machine functions when cloning memory references!"
) ? static_cast<void> (0) : __assert_fail ("&MF == MI.getMF() && \"Invalid machine functions when cloning memory references!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/MachineInstr.cpp"
, 444, __PRETTY_FUNCTION__))
;
445
446 // Skip MIs with identical operands to the first. This is a somewhat
447 // arbitrary hack but will catch common cases without being quadratic.
448 // TODO: We could fully implement merge semantics here if needed.
449 if (hasIdenticalMMOs(MIs[0]->memoperands(), MI.memoperands()))
450 continue;
451
452 // Because an empty memoperands list provides *no* information and must be
453 // handled conservatively (assuming the instruction can do anything), the
454 // only way to merge with it is to drop all other memoperands.
455 if (MI.memoperands_empty()) {
456 dropMemRefs(MF);
457 return;
458 }
459
460 // Otherwise accumulate these into our temporary buffer of the merged state.
461 MergedMMOs.append(MI.memoperands_begin(), MI.memoperands_end());
462 }
463
464 setMemRefs(MF, MergedMMOs);
465}
466
467void MachineInstr::setPreInstrSymbol(MachineFunction &MF, MCSymbol *Symbol) {
468 // Do nothing if old and new symbols are the same.
469 if (Symbol == getPreInstrSymbol())
470 return;
471
472 // If there was only one symbol and we're removing it, just clear info.
473 if (!Symbol && Info.is<EIIK_PreInstrSymbol>()) {
474 Info.clear();
475 return;
476 }
477
478 setExtraInfo(MF, memoperands(), Symbol, getPostInstrSymbol(),
479 getHeapAllocMarker());
480}
481
482void MachineInstr::setPostInstrSymbol(MachineFunction &MF, MCSymbol *Symbol) {
483 // Do nothing if old and new symbols are the same.
484 if (Symbol == getPostInstrSymbol())
485 return;
486
487 // If there was only one symbol and we're removing it, just clear info.
488 if (!Symbol && Info.is<EIIK_PostInstrSymbol>()) {
489 Info.clear();
490 return;
491 }
492
493 setExtraInfo(MF, memoperands(), getPreInstrSymbol(), Symbol,
494 getHeapAllocMarker());
495}
496
497void MachineInstr::setHeapAllocMarker(MachineFunction &MF, MDNode *Marker) {
498 // Do nothing if old and new symbols are the same.
499 if (Marker == getHeapAllocMarker())
500 return;
501
502 setExtraInfo(MF, memoperands(), getPreInstrSymbol(), getPostInstrSymbol(),
503 Marker);
504}
505
506void MachineInstr::cloneInstrSymbols(MachineFunction &MF,
507 const MachineInstr &MI) {
508 if (this == &MI)
509 // Nothing to do for a self-clone!
510 return;
511
512 assert(&MF == MI.getMF() &&((&MF == MI.getMF() && "Invalid machine functions when cloning instruction symbols!"
) ? static_cast<void> (0) : __assert_fail ("&MF == MI.getMF() && \"Invalid machine functions when cloning instruction symbols!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/MachineInstr.cpp"
, 513, __PRETTY_FUNCTION__))
513 "Invalid machine functions when cloning instruction symbols!")((&MF == MI.getMF() && "Invalid machine functions when cloning instruction symbols!"
) ? static_cast<void> (0) : __assert_fail ("&MF == MI.getMF() && \"Invalid machine functions when cloning instruction symbols!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/MachineInstr.cpp"
, 513, __PRETTY_FUNCTION__))
;
514
515 setPreInstrSymbol(MF, MI.getPreInstrSymbol());
516 setPostInstrSymbol(MF, MI.getPostInstrSymbol());
517 setHeapAllocMarker(MF, MI.getHeapAllocMarker());
518}
519
520uint16_t MachineInstr::mergeFlagsWith(const MachineInstr &Other) const {
521 // For now, the just return the union of the flags. If the flags get more
522 // complicated over time, we might need more logic here.
523 return getFlags() | Other.getFlags();
524}
525
526uint16_t MachineInstr::copyFlagsFromInstruction(const Instruction &I) {
527 uint16_t MIFlags = 0;
528 // Copy the wrapping flags.
529 if (const OverflowingBinaryOperator *OB =
530 dyn_cast<OverflowingBinaryOperator>(&I)) {
531 if (OB->hasNoSignedWrap())
532 MIFlags |= MachineInstr::MIFlag::NoSWrap;
533 if (OB->hasNoUnsignedWrap())
534 MIFlags |= MachineInstr::MIFlag::NoUWrap;
535 }
536
537 // Copy the exact flag.
538 if (const PossiblyExactOperator *PE = dyn_cast<PossiblyExactOperator>(&I))
539 if (PE->isExact())
540 MIFlags |= MachineInstr::MIFlag::IsExact;
541
542 // Copy the fast-math flags.
543 if (const FPMathOperator *FP = dyn_cast<FPMathOperator>(&I)) {
544 const FastMathFlags Flags = FP->getFastMathFlags();
545 if (Flags.noNaNs())
546 MIFlags |= MachineInstr::MIFlag::FmNoNans;
547 if (Flags.noInfs())
548 MIFlags |= MachineInstr::MIFlag::FmNoInfs;
549 if (Flags.noSignedZeros())
550 MIFlags |= MachineInstr::MIFlag::FmNsz;
551 if (Flags.allowReciprocal())
552 MIFlags |= MachineInstr::MIFlag::FmArcp;
553 if (Flags.allowContract())
554 MIFlags |= MachineInstr::MIFlag::FmContract;
555 if (Flags.approxFunc())
556 MIFlags |= MachineInstr::MIFlag::FmAfn;
557 if (Flags.allowReassoc())
558 MIFlags |= MachineInstr::MIFlag::FmReassoc;
559 }
560
561 return MIFlags;
562}
563
564void MachineInstr::copyIRFlags(const Instruction &I) {
565 Flags = copyFlagsFromInstruction(I);
566}
567
568bool MachineInstr::hasPropertyInBundle(uint64_t Mask, QueryType Type) const {
569 assert(!isBundledWithPred() && "Must be called on bundle header")((!isBundledWithPred() && "Must be called on bundle header"
) ? static_cast<void> (0) : __assert_fail ("!isBundledWithPred() && \"Must be called on bundle header\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/MachineInstr.cpp"
, 569, __PRETTY_FUNCTION__))
;
570 for (MachineBasicBlock::const_instr_iterator MII = getIterator();; ++MII) {
571 if (MII->getDesc().getFlags() & Mask) {
572 if (Type == AnyInBundle)
573 return true;
574 } else {
575 if (Type == AllInBundle && !MII->isBundle())
576 return false;
577 }
578 // This was the last instruction in the bundle.
579 if (!MII->isBundledWithSucc())
580 return Type == AllInBundle;
581 }
582}
583
584bool MachineInstr::isIdenticalTo(const MachineInstr &Other,
585 MICheckType Check) const {
586 // If opcodes or number of operands are not the same then the two
587 // instructions are obviously not identical.
588 if (Other.getOpcode() != getOpcode() ||
589 Other.getNumOperands() != getNumOperands())
590 return false;
591
592 if (isBundle()) {
593 // We have passed the test above that both instructions have the same
594 // opcode, so we know that both instructions are bundles here. Let's compare
595 // MIs inside the bundle.
596 assert(Other.isBundle() && "Expected that both instructions are bundles.")((Other.isBundle() && "Expected that both instructions are bundles."
) ? static_cast<void> (0) : __assert_fail ("Other.isBundle() && \"Expected that both instructions are bundles.\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/MachineInstr.cpp"
, 596, __PRETTY_FUNCTION__))
;
597 MachineBasicBlock::const_instr_iterator I1 = getIterator();
598 MachineBasicBlock::const_instr_iterator I2 = Other.getIterator();
599 // Loop until we analysed the last intruction inside at least one of the
600 // bundles.
601 while (I1->isBundledWithSucc() && I2->isBundledWithSucc()) {
602 ++I1;
603 ++I2;
604 if (!I1->isIdenticalTo(*I2, Check))
605 return false;
606 }
607 // If we've reached the end of just one of the two bundles, but not both,
608 // the instructions are not identical.
609 if (I1->isBundledWithSucc() || I2->isBundledWithSucc())
610 return false;
611 }
612
613 // Check operands to make sure they match.
614 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
615 const MachineOperand &MO = getOperand(i);
616 const MachineOperand &OMO = Other.getOperand(i);
617 if (!MO.isReg()) {
618 if (!MO.isIdenticalTo(OMO))
619 return false;
620 continue;
621 }
622
623 // Clients may or may not want to ignore defs when testing for equality.
624 // For example, machine CSE pass only cares about finding common
625 // subexpressions, so it's safe to ignore virtual register defs.
626 if (MO.isDef()) {
627 if (Check == IgnoreDefs)
628 continue;
629 else if (Check == IgnoreVRegDefs) {
630 if (!Register::isVirtualRegister(MO.getReg()) ||
631 !Register::isVirtualRegister(OMO.getReg()))
632 if (!MO.isIdenticalTo(OMO))
633 return false;
634 } else {
635 if (!MO.isIdenticalTo(OMO))
636 return false;
637 if (Check == CheckKillDead && MO.isDead() != OMO.isDead())
638 return false;
639 }
640 } else {
641 if (!MO.isIdenticalTo(OMO))
642 return false;
643 if (Check == CheckKillDead && MO.isKill() != OMO.isKill())
644 return false;
645 }
646 }
647 // If DebugLoc does not match then two debug instructions are not identical.
648 if (isDebugInstr())
649 if (getDebugLoc() && Other.getDebugLoc() &&
650 getDebugLoc() != Other.getDebugLoc())
651 return false;
652 return true;
653}
654
655const MachineFunction *MachineInstr::getMF() const {
656 return getParent()->getParent();
657}
658
659MachineInstr *MachineInstr::removeFromParent() {
660 assert(getParent() && "Not embedded in a basic block!")((getParent() && "Not embedded in a basic block!") ? static_cast
<void> (0) : __assert_fail ("getParent() && \"Not embedded in a basic block!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/MachineInstr.cpp"
, 660, __PRETTY_FUNCTION__))
;
661 return getParent()->remove(this);
662}
663
664MachineInstr *MachineInstr::removeFromBundle() {
665 assert(getParent() && "Not embedded in a basic block!")((getParent() && "Not embedded in a basic block!") ? static_cast
<void> (0) : __assert_fail ("getParent() && \"Not embedded in a basic block!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/MachineInstr.cpp"
, 665, __PRETTY_FUNCTION__))
;
666 return getParent()->remove_instr(this);
667}
668
669void MachineInstr::eraseFromParent() {
670 assert(getParent() && "Not embedded in a basic block!")((getParent() && "Not embedded in a basic block!") ? static_cast
<void> (0) : __assert_fail ("getParent() && \"Not embedded in a basic block!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/MachineInstr.cpp"
, 670, __PRETTY_FUNCTION__))
;
671 getParent()->erase(this);
672}
673
674void MachineInstr::eraseFromParentAndMarkDBGValuesForRemoval() {
675 assert(getParent() && "Not embedded in a basic block!")((getParent() && "Not embedded in a basic block!") ? static_cast
<void> (0) : __assert_fail ("getParent() && \"Not embedded in a basic block!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/MachineInstr.cpp"
, 675, __PRETTY_FUNCTION__))
;
676 MachineBasicBlock *MBB = getParent();
677 MachineFunction *MF = MBB->getParent();
678 assert(MF && "Not embedded in a function!")((MF && "Not embedded in a function!") ? static_cast<
void> (0) : __assert_fail ("MF && \"Not embedded in a function!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/MachineInstr.cpp"
, 678, __PRETTY_FUNCTION__))
;
679
680 MachineInstr *MI = (MachineInstr *)this;
681 MachineRegisterInfo &MRI = MF->getRegInfo();
682
683 for (const MachineOperand &MO : MI->operands()) {
684 if (!MO.isReg() || !MO.isDef())
685 continue;
686 Register Reg = MO.getReg();
687 if (!Reg.isVirtual())
688 continue;
689 MRI.markUsesInDebugValueAsUndef(Reg);
690 }
691 MI->eraseFromParent();
692}
693
694void MachineInstr::eraseFromBundle() {
695 assert(getParent() && "Not embedded in a basic block!")((getParent() && "Not embedded in a basic block!") ? static_cast
<void> (0) : __assert_fail ("getParent() && \"Not embedded in a basic block!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/MachineInstr.cpp"
, 695, __PRETTY_FUNCTION__))
;
696 getParent()->erase_instr(this);
697}
698
699unsigned MachineInstr::getNumExplicitOperands() const {
700 unsigned NumOperands = MCID->getNumOperands();
701 if (!MCID->isVariadic())
702 return NumOperands;
703
704 for (unsigned I = NumOperands, E = getNumOperands(); I != E; ++I) {
705 const MachineOperand &MO = getOperand(I);
706 // The operands must always be in the following order:
707 // - explicit reg defs,
708 // - other explicit operands (reg uses, immediates, etc.),
709 // - implicit reg defs
710 // - implicit reg uses
711 if (MO.isReg() && MO.isImplicit())
712 break;
713 ++NumOperands;
714 }
715 return NumOperands;
716}
717
718unsigned MachineInstr::getNumExplicitDefs() const {
719 unsigned NumDefs = MCID->getNumDefs();
720 if (!MCID->isVariadic())
721 return NumDefs;
722
723 for (unsigned I = NumDefs, E = getNumOperands(); I != E; ++I) {
724 const MachineOperand &MO = getOperand(I);
725 if (!MO.isReg() || !MO.isDef() || MO.isImplicit())
726 break;
727 ++NumDefs;
728 }
729 return NumDefs;
730}
731
732void MachineInstr::bundleWithPred() {
733 assert(!isBundledWithPred() && "MI is already bundled with its predecessor")((!isBundledWithPred() && "MI is already bundled with its predecessor"
) ? static_cast<void> (0) : __assert_fail ("!isBundledWithPred() && \"MI is already bundled with its predecessor\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/MachineInstr.cpp"
, 733, __PRETTY_FUNCTION__))
;
734 setFlag(BundledPred);
735 MachineBasicBlock::instr_iterator Pred = getIterator();
736 --Pred;
737 assert(!Pred->isBundledWithSucc() && "Inconsistent bundle flags")((!Pred->isBundledWithSucc() && "Inconsistent bundle flags"
) ? static_cast<void> (0) : __assert_fail ("!Pred->isBundledWithSucc() && \"Inconsistent bundle flags\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/MachineInstr.cpp"
, 737, __PRETTY_FUNCTION__))
;
738 Pred->setFlag(BundledSucc);
739}
740
741void MachineInstr::bundleWithSucc() {
742 assert(!isBundledWithSucc() && "MI is already bundled with its successor")((!isBundledWithSucc() && "MI is already bundled with its successor"
) ? static_cast<void> (0) : __assert_fail ("!isBundledWithSucc() && \"MI is already bundled with its successor\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/MachineInstr.cpp"
, 742, __PRETTY_FUNCTION__))
;
743 setFlag(BundledSucc);
744 MachineBasicBlock::instr_iterator Succ = getIterator();
745 ++Succ;
746 assert(!Succ->isBundledWithPred() && "Inconsistent bundle flags")((!Succ->isBundledWithPred() && "Inconsistent bundle flags"
) ? static_cast<void> (0) : __assert_fail ("!Succ->isBundledWithPred() && \"Inconsistent bundle flags\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/MachineInstr.cpp"
, 746, __PRETTY_FUNCTION__))
;
747 Succ->setFlag(BundledPred);
748}
749
750void MachineInstr::unbundleFromPred() {
751 assert(isBundledWithPred() && "MI isn't bundled with its predecessor")((isBundledWithPred() && "MI isn't bundled with its predecessor"
) ? static_cast<void> (0) : __assert_fail ("isBundledWithPred() && \"MI isn't bundled with its predecessor\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/MachineInstr.cpp"
, 751, __PRETTY_FUNCTION__))
;
752 clearFlag(BundledPred);
753 MachineBasicBlock::instr_iterator Pred = getIterator();
754 --Pred;
755 assert(Pred->isBundledWithSucc() && "Inconsistent bundle flags")((Pred->isBundledWithSucc() && "Inconsistent bundle flags"
) ? static_cast<void> (0) : __assert_fail ("Pred->isBundledWithSucc() && \"Inconsistent bundle flags\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/MachineInstr.cpp"
, 755, __PRETTY_FUNCTION__))
;
756 Pred->clearFlag(BundledSucc);
757}
758
759void MachineInstr::unbundleFromSucc() {
760 assert(isBundledWithSucc() && "MI isn't bundled with its successor")((isBundledWithSucc() && "MI isn't bundled with its successor"
) ? static_cast<void> (0) : __assert_fail ("isBundledWithSucc() && \"MI isn't bundled with its successor\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/MachineInstr.cpp"
, 760, __PRETTY_FUNCTION__))
;
761 clearFlag(BundledSucc);
762 MachineBasicBlock::instr_iterator Succ = getIterator();
763 ++Succ;
764 assert(Succ->isBundledWithPred() && "Inconsistent bundle flags")((Succ->isBundledWithPred() && "Inconsistent bundle flags"
) ? static_cast<void> (0) : __assert_fail ("Succ->isBundledWithPred() && \"Inconsistent bundle flags\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/MachineInstr.cpp"
, 764, __PRETTY_FUNCTION__))
;
765 Succ->clearFlag(BundledPred);
766}
767
768bool MachineInstr::isStackAligningInlineAsm() const {
769 if (isInlineAsm()) {
770 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
771 if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
772 return true;
773 }
774 return false;
775}
776
777InlineAsm::AsmDialect MachineInstr::getInlineAsmDialect() const {
778 assert(isInlineAsm() && "getInlineAsmDialect() only works for inline asms!")((isInlineAsm() && "getInlineAsmDialect() only works for inline asms!"
) ? static_cast<void> (0) : __assert_fail ("isInlineAsm() && \"getInlineAsmDialect() only works for inline asms!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/MachineInstr.cpp"
, 778, __PRETTY_FUNCTION__))
;
779 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
780 return InlineAsm::AsmDialect((ExtraInfo & InlineAsm::Extra_AsmDialect) != 0);
781}
782
783int MachineInstr::findInlineAsmFlagIdx(unsigned OpIdx,
784 unsigned *GroupNo) const {
785 assert(isInlineAsm() && "Expected an inline asm instruction")((isInlineAsm() && "Expected an inline asm instruction"
) ? static_cast<void> (0) : __assert_fail ("isInlineAsm() && \"Expected an inline asm instruction\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/MachineInstr.cpp"
, 785, __PRETTY_FUNCTION__))
;
786 assert(OpIdx < getNumOperands() && "OpIdx out of range")((OpIdx < getNumOperands() && "OpIdx out of range"
) ? static_cast<void> (0) : __assert_fail ("OpIdx < getNumOperands() && \"OpIdx out of range\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/MachineInstr.cpp"
, 786, __PRETTY_FUNCTION__))
;
787
788 // Ignore queries about the initial operands.
789 if (OpIdx < InlineAsm::MIOp_FirstOperand)
790 return -1;
791
792 unsigned Group = 0;
793 unsigned NumOps;
794 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
795 i += NumOps) {
796 const MachineOperand &FlagMO = getOperand(i);
797 // If we reach the implicit register operands, stop looking.
798 if (!FlagMO.isImm())
799 return -1;
800 NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
801 if (i + NumOps > OpIdx) {
802 if (GroupNo)
803 *GroupNo = Group;
804 return i;
805 }
806 ++Group;
807 }
808 return -1;
809}
810
811const DILabel *MachineInstr::getDebugLabel() const {
812 assert(isDebugLabel() && "not a DBG_LABEL")((isDebugLabel() && "not a DBG_LABEL") ? static_cast<
void> (0) : __assert_fail ("isDebugLabel() && \"not a DBG_LABEL\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/MachineInstr.cpp"
, 812, __PRETTY_FUNCTION__))
;
813 return cast<DILabel>(getOperand(0).getMetadata());
814}
815
816const DILocalVariable *MachineInstr::getDebugVariable() const {
817 assert(isDebugValue() && "not a DBG_VALUE")((isDebugValue() && "not a DBG_VALUE") ? static_cast<
void> (0) : __assert_fail ("isDebugValue() && \"not a DBG_VALUE\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/MachineInstr.cpp"
, 817, __PRETTY_FUNCTION__))
;
818 return cast<DILocalVariable>(getOperand(2).getMetadata());
819}
820
821const DIExpression *MachineInstr::getDebugExpression() const {
822 assert(isDebugValue() && "not a DBG_VALUE")((isDebugValue() && "not a DBG_VALUE") ? static_cast<
void> (0) : __assert_fail ("isDebugValue() && \"not a DBG_VALUE\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/MachineInstr.cpp"
, 822, __PRETTY_FUNCTION__))
;
823 return cast<DIExpression>(getOperand(3).getMetadata());
824}
825
826bool MachineInstr::isDebugEntryValue() const {
827 return isDebugValue() && getDebugExpression()->isEntryValue();
828}
829
830const TargetRegisterClass*
831MachineInstr::getRegClassConstraint(unsigned OpIdx,
832 const TargetInstrInfo *TII,
833 const TargetRegisterInfo *TRI) const {
834 assert(getParent() && "Can't have an MBB reference here!")((getParent() && "Can't have an MBB reference here!")
? static_cast<void> (0) : __assert_fail ("getParent() && \"Can't have an MBB reference here!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/MachineInstr.cpp"
, 834, __PRETTY_FUNCTION__))
;
835 assert(getMF() && "Can't have an MF reference here!")((getMF() && "Can't have an MF reference here!") ? static_cast
<void> (0) : __assert_fail ("getMF() && \"Can't have an MF reference here!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/MachineInstr.cpp"
, 835, __PRETTY_FUNCTION__))
;
836 const MachineFunction &MF = *getMF();
837
838 // Most opcodes have fixed constraints in their MCInstrDesc.
839 if (!isInlineAsm())
840 return TII->getRegClass(getDesc(), OpIdx, TRI, MF);
841
842 if (!getOperand(OpIdx).isReg())
843 return nullptr;
844
845 // For tied uses on inline asm, get the constraint from the def.
846 unsigned DefIdx;
847 if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx))
848 OpIdx = DefIdx;
849
850 // Inline asm stores register class constraints in the flag word.
851 int FlagIdx = findInlineAsmFlagIdx(OpIdx);
852 if (FlagIdx < 0)
853 return nullptr;
854
855 unsigned Flag = getOperand(FlagIdx).getImm();
856 unsigned RCID;
857 if ((InlineAsm::getKind(Flag) == InlineAsm::Kind_RegUse ||
858 InlineAsm::getKind(Flag) == InlineAsm::Kind_RegDef ||
859 InlineAsm::getKind(Flag) == InlineAsm::Kind_RegDefEarlyClobber) &&
860 InlineAsm::hasRegClassConstraint(Flag, RCID))
861 return TRI->getRegClass(RCID);
862
863 // Assume that all registers in a memory operand are pointers.
864 if (InlineAsm::getKind(Flag) == InlineAsm::Kind_Mem)
865 return TRI->getPointerRegClass(MF);
866
867 return nullptr;
868}
869
870const TargetRegisterClass *MachineInstr::getRegClassConstraintEffectForVReg(
871 Register Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII,
872 const TargetRegisterInfo *TRI, bool ExploreBundle) const {
873 // Check every operands inside the bundle if we have
874 // been asked to.
875 if (ExploreBundle)
876 for (ConstMIBundleOperands OpndIt(*this); OpndIt.isValid() && CurRC;
877 ++OpndIt)
878 CurRC = OpndIt->getParent()->getRegClassConstraintEffectForVRegImpl(
879 OpndIt.getOperandNo(), Reg, CurRC, TII, TRI);
880 else
881 // Otherwise, just check the current operands.
882 for (unsigned i = 0, e = NumOperands; i < e && CurRC; ++i)
883 CurRC = getRegClassConstraintEffectForVRegImpl(i, Reg, CurRC, TII, TRI);
884 return CurRC;
885}
886
887const TargetRegisterClass *MachineInstr::getRegClassConstraintEffectForVRegImpl(
888 unsigned OpIdx, Register Reg, const TargetRegisterClass *CurRC,
889 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const {
890 assert(CurRC && "Invalid initial register class")((CurRC && "Invalid initial register class") ? static_cast
<void> (0) : __assert_fail ("CurRC && \"Invalid initial register class\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/MachineInstr.cpp"
, 890, __PRETTY_FUNCTION__))
;
891 // Check if Reg is constrained by some of its use/def from MI.
892 const MachineOperand &MO = getOperand(OpIdx);
893 if (!MO.isReg() || MO.getReg() != Reg)
894 return CurRC;
895 // If yes, accumulate the constraints through the operand.
896 return getRegClassConstraintEffect(OpIdx, CurRC, TII, TRI);
897}
898
899const TargetRegisterClass *MachineInstr::getRegClassConstraintEffect(
900 unsigned OpIdx, const TargetRegisterClass *CurRC,
901 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const {
902 const TargetRegisterClass *OpRC = getRegClassConstraint(OpIdx, TII, TRI);
903 const MachineOperand &MO = getOperand(OpIdx);
904 assert(MO.isReg() &&((MO.isReg() && "Cannot get register constraints for non-register operand"
) ? static_cast<void> (0) : __assert_fail ("MO.isReg() && \"Cannot get register constraints for non-register operand\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/MachineInstr.cpp"
, 905, __PRETTY_FUNCTION__))
905 "Cannot get register constraints for non-register operand")((MO.isReg() && "Cannot get register constraints for non-register operand"
) ? static_cast<void> (0) : __assert_fail ("MO.isReg() && \"Cannot get register constraints for non-register operand\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/MachineInstr.cpp"
, 905, __PRETTY_FUNCTION__))
;
906 assert(CurRC && "Invalid initial register class")((CurRC && "Invalid initial register class") ? static_cast
<void> (0) : __assert_fail ("CurRC && \"Invalid initial register class\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/MachineInstr.cpp"
, 906, __PRETTY_FUNCTION__))
;
907 if (unsigned SubIdx = MO.getSubReg()) {
908 if (OpRC)
909 CurRC = TRI->getMatchingSuperRegClass(CurRC, OpRC, SubIdx);
910 else
911 CurRC = TRI->getSubClassWithSubReg(CurRC, SubIdx);
912 } else if (OpRC)
913 CurRC = TRI->getCommonSubClass(CurRC, OpRC);
914 return CurRC;
915}
916
917/// Return the number of instructions inside the MI bundle, not counting the
918/// header instruction.
919unsigned MachineInstr::getBundleSize() const {
920 MachineBasicBlock::const_instr_iterator I = getIterator();
921 unsigned Size = 0;
922 while (I->isBundledWithSucc()) {
923 ++Size;
924 ++I;
925 }
926 return Size;
927}
928
929/// Returns true if the MachineInstr has an implicit-use operand of exactly
930/// the given register (not considering sub/super-registers).
931bool MachineInstr::hasRegisterImplicitUseOperand(Register Reg) const {
932 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
933 const MachineOperand &MO = getOperand(i);
934 if (MO.isReg() && MO.isUse() && MO.isImplicit() && MO.getReg() == Reg)
935 return true;
936 }
937 return false;
938}
939
940/// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
941/// the specific register or -1 if it is not found. It further tightens
942/// the search criteria to a use that kills the register if isKill is true.
943int MachineInstr::findRegisterUseOperandIdx(
944 Register Reg, bool isKill, const TargetRegisterInfo *TRI) const {
945 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
946 const MachineOperand &MO = getOperand(i);
947 if (!MO.isReg() || !MO.isUse())
948 continue;
949 Register MOReg = MO.getReg();
950 if (!MOReg)
951 continue;
952 if (MOReg == Reg || (TRI && Reg && MOReg && TRI->regsOverlap(MOReg, Reg)))
953 if (!isKill || MO.isKill())
954 return i;
955 }
956 return -1;
957}
958
959/// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
960/// indicating if this instruction reads or writes Reg. This also considers
961/// partial defines.
962std::pair<bool,bool>
963MachineInstr::readsWritesVirtualRegister(Register Reg,
964 SmallVectorImpl<unsigned> *Ops) const {
965 bool PartDef = false; // Partial redefine.
966 bool FullDef = false; // Full define.
967 bool Use = false;
968
969 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
970 const MachineOperand &MO = getOperand(i);
971 if (!MO.isReg() || MO.getReg() != Reg)
972 continue;
973 if (Ops)
974 Ops->push_back(i);
975 if (MO.isUse())
976 Use |= !MO.isUndef();
977 else if (MO.getSubReg() && !MO.isUndef())
978 // A partial def undef doesn't count as reading the register.
979 PartDef = true;
980 else
981 FullDef = true;
982 }
983 // A partial redefine uses Reg unless there is also a full define.
984 return std::make_pair(Use || (PartDef && !FullDef), PartDef || FullDef);
985}
986
987/// findRegisterDefOperandIdx() - Returns the operand index that is a def of
988/// the specified register or -1 if it is not found. If isDead is true, defs
989/// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
990/// also checks if there is a def of a super-register.
991int
992MachineInstr::findRegisterDefOperandIdx(Register Reg, bool isDead, bool Overlap,
993 const TargetRegisterInfo *TRI) const {
994 bool isPhys = Register::isPhysicalRegister(Reg);
995 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
996 const MachineOperand &MO = getOperand(i);
997 // Accept regmask operands when Overlap is set.
998 // Ignore them when looking for a specific def operand (Overlap == false).
999 if (isPhys && Overlap && MO.isRegMask() && MO.clobbersPhysReg(Reg))
1000 return i;
1001 if (!MO.isReg() || !MO.isDef())
1002 continue;
1003 Register MOReg = MO.getReg();
1004 bool Found = (MOReg == Reg);
1005 if (!Found && TRI && isPhys && Register::isPhysicalRegister(MOReg)) {
1006 if (Overlap)
1007 Found = TRI->regsOverlap(MOReg, Reg);
1008 else
1009 Found = TRI->isSubRegister(MOReg, Reg);
1010 }
1011 if (Found && (!isDead || MO.isDead()))
1012 return i;
1013 }
1014 return -1;
1015}
1016
1017/// findFirstPredOperandIdx() - Find the index of the first operand in the
1018/// operand list that is used to represent the predicate. It returns -1 if
1019/// none is found.
1020int MachineInstr::findFirstPredOperandIdx() const {
1021 // Don't call MCID.findFirstPredOperandIdx() because this variant
1022 // is sometimes called on an instruction that's not yet complete, and
1023 // so the number of operands is less than the MCID indicates. In
1024 // particular, the PTX target does this.
1025 const MCInstrDesc &MCID = getDesc();
1026 if (MCID.isPredicable()) {
1027 for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
1028 if (MCID.OpInfo[i].isPredicate())
1029 return i;
1030 }
1031
1032 return -1;
1033}
1034
1035// MachineOperand::TiedTo is 4 bits wide.
1036const unsigned TiedMax = 15;
1037
1038/// tieOperands - Mark operands at DefIdx and UseIdx as tied to each other.
1039///
1040/// Use and def operands can be tied together, indicated by a non-zero TiedTo
1041/// field. TiedTo can have these values:
1042///
1043/// 0: Operand is not tied to anything.
1044/// 1 to TiedMax-1: Tied to getOperand(TiedTo-1).
1045/// TiedMax: Tied to an operand >= TiedMax-1.
1046///
1047/// The tied def must be one of the first TiedMax operands on a normal
1048/// instruction. INLINEASM instructions allow more tied defs.
1049///
1050void MachineInstr::tieOperands(unsigned DefIdx, unsigned UseIdx) {
1051 MachineOperand &DefMO = getOperand(DefIdx);
1052 MachineOperand &UseMO = getOperand(UseIdx);
1053 assert(DefMO.isDef() && "DefIdx must be a def operand")((DefMO.isDef() && "DefIdx must be a def operand") ? static_cast
<void> (0) : __assert_fail ("DefMO.isDef() && \"DefIdx must be a def operand\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/MachineInstr.cpp"
, 1053, __PRETTY_FUNCTION__))
;
1054 assert(UseMO.isUse() && "UseIdx must be a use operand")((UseMO.isUse() && "UseIdx must be a use operand") ? static_cast
<void> (0) : __assert_fail ("UseMO.isUse() && \"UseIdx must be a use operand\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/MachineInstr.cpp"
, 1054, __PRETTY_FUNCTION__))
;
1055 assert(!DefMO.isTied() && "Def is already tied to another use")((!DefMO.isTied() && "Def is already tied to another use"
) ? static_cast<void> (0) : __assert_fail ("!DefMO.isTied() && \"Def is already tied to another use\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/MachineInstr.cpp"
, 1055, __PRETTY_FUNCTION__))
;
1056 assert(!UseMO.isTied() && "Use is already tied to another def")((!UseMO.isTied() && "Use is already tied to another def"
) ? static_cast<void> (0) : __assert_fail ("!UseMO.isTied() && \"Use is already tied to another def\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/MachineInstr.cpp"
, 1056, __PRETTY_FUNCTION__))
;
1057
1058 if (DefIdx < TiedMax)
1059 UseMO.TiedTo = DefIdx + 1;
1060 else {
1061 // Inline asm can use the group descriptors to find tied operands, but on
1062 // normal instruction, the tied def must be within the first TiedMax
1063 // operands.
1064 assert(isInlineAsm() && "DefIdx out of range")((isInlineAsm() && "DefIdx out of range") ? static_cast
<void> (0) : __assert_fail ("isInlineAsm() && \"DefIdx out of range\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/MachineInstr.cpp"
, 1064, __PRETTY_FUNCTION__))
;
1065 UseMO.TiedTo = TiedMax;
1066 }
1067
1068 // UseIdx can be out of range, we'll search for it in findTiedOperandIdx().
1069 DefMO.TiedTo = std::min(UseIdx + 1, TiedMax);
1070}
1071
1072/// Given the index of a tied register operand, find the operand it is tied to.
1073/// Defs are tied to uses and vice versa. Returns the index of the tied operand
1074/// which must exist.
1075unsigned MachineInstr::findTiedOperandIdx(unsigned OpIdx) const {
1076 const MachineOperand &MO = getOperand(OpIdx);
1077 assert(MO.isTied() && "Operand isn't tied")((MO.isTied() && "Operand isn't tied") ? static_cast<
void> (0) : __assert_fail ("MO.isTied() && \"Operand isn't tied\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/MachineInstr.cpp"
, 1077, __PRETTY_FUNCTION__))
;
1078
1079 // Normally TiedTo is in range.
1080 if (MO.TiedTo < TiedMax)
1081 return MO.TiedTo - 1;
1082
1083 // Uses on normal instructions can be out of range.
1084 if (!isInlineAsm()) {
1085 // Normal tied defs must be in the 0..TiedMax-1 range.
1086 if (MO.isUse())
1087 return TiedMax - 1;
1088 // MO is a def. Search for the tied use.
1089 for (unsigned i = TiedMax - 1, e = getNumOperands(); i != e; ++i) {
1090 const MachineOperand &UseMO = getOperand(i);
1091 if (UseMO.isReg() && UseMO.isUse() && UseMO.TiedTo == OpIdx + 1)
1092 return i;
1093 }
1094 llvm_unreachable("Can't find tied use")::llvm::llvm_unreachable_internal("Can't find tied use", "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/MachineInstr.cpp"
, 1094)
;
1095 }
1096
1097 // Now deal with inline asm by parsing the operand group descriptor flags.
1098 // Find the beginning of each operand group.
1099 SmallVector<unsigned, 8> GroupIdx;
1100 unsigned OpIdxGroup = ~0u;
1101 unsigned NumOps;
1102 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
1103 i += NumOps) {
1104 const MachineOperand &FlagMO = getOperand(i);
1105 assert(FlagMO.isImm() && "Invalid tied operand on inline asm")((FlagMO.isImm() && "Invalid tied operand on inline asm"
) ? static_cast<void> (0) : __assert_fail ("FlagMO.isImm() && \"Invalid tied operand on inline asm\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/MachineInstr.cpp"
, 1105, __PRETTY_FUNCTION__))
;
1106 unsigned CurGroup = GroupIdx.size();
1107 GroupIdx.push_back(i);
1108 NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
1109 // OpIdx belongs to this operand group.
1110 if (OpIdx > i && OpIdx < i + NumOps)
1111 OpIdxGroup = CurGroup;
1112 unsigned TiedGroup;
1113 if (!InlineAsm::isUseOperandTiedToDef(FlagMO.getImm(), TiedGroup))
1114 continue;
1115 // Operands in this group are tied to operands in TiedGroup which must be
1116 // earlier. Find the number of operands between the two groups.
1117 unsigned Delta = i - GroupIdx[TiedGroup];
1118
1119 // OpIdx is a use tied to TiedGroup.
1120 if (OpIdxGroup == CurGroup)
1121 return OpIdx - Delta;
1122
1123 // OpIdx is a def tied to this use group.
1124 if (OpIdxGroup == TiedGroup)
1125 return OpIdx + Delta;
1126 }
1127 llvm_unreachable("Invalid tied operand on inline asm")::llvm::llvm_unreachable_internal("Invalid tied operand on inline asm"
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/MachineInstr.cpp"
, 1127)
;
1128}
1129
1130/// clearKillInfo - Clears kill flags on all operands.
1131///
1132void MachineInstr::clearKillInfo() {
1133 for (MachineOperand &MO : operands()) {
1134 if (MO.isReg() && MO.isUse())
1135 MO.setIsKill(false);
1136 }
1137}
1138
1139void MachineInstr::substituteRegister(Register FromReg, Register ToReg,
1140 unsigned SubIdx,
1141 const TargetRegisterInfo &RegInfo) {
1142 if (Register::isPhysicalRegister(ToReg)) {
1143 if (SubIdx)
1144 ToReg = RegInfo.getSubReg(ToReg, SubIdx);
1145 for (MachineOperand &MO : operands()) {
1146 if (!MO.isReg() || MO.getReg() != FromReg)
1147 continue;
1148 MO.substPhysReg(ToReg, RegInfo);
1149 }
1150 } else {
1151 for (MachineOperand &MO : operands()) {
1152 if (!MO.isReg() || MO.getReg() != FromReg)
1153 continue;
1154 MO.substVirtReg(ToReg, SubIdx, RegInfo);
1155 }
1156 }
1157}
1158
1159/// isSafeToMove - Return true if it is safe to move this instruction. If
1160/// SawStore is set to true, it means that there is a store (or call) between
1161/// the instruction's location and its intended destination.
1162bool MachineInstr::isSafeToMove(AAResults *AA, bool &SawStore) const {
1163 // Ignore stuff that we obviously can't move.
1164 //
1165 // Treat volatile loads as stores. This is not strictly necessary for
1166 // volatiles, but it is required for atomic loads. It is not allowed to move
1167 // a load across an atomic load with Ordering > Monotonic.
1168 if (mayStore() || isCall() || isPHI() ||
1169 (mayLoad() && hasOrderedMemoryRef())) {
1170 SawStore = true;
1171 return false;
1172 }
1173
1174 if (isPosition() || isDebugInstr() || isTerminator() ||
1175 mayRaiseFPException() || hasUnmodeledSideEffects())
1176 return false;
1177
1178 // See if this instruction does a load. If so, we have to guarantee that the
1179 // loaded value doesn't change between the load and the its intended
1180 // destination. The check for isInvariantLoad gives the targe the chance to
1181 // classify the load as always returning a constant, e.g. a constant pool
1182 // load.
1183 if (mayLoad() && !isDereferenceableInvariantLoad(AA))
1184 // Otherwise, this is a real load. If there is a store between the load and
1185 // end of block, we can't move it.
1186 return !SawStore;
1187
1188 return true;
1189}
1190
1191bool MachineInstr::mayAlias(AAResults *AA, const MachineInstr &Other,
1192 bool UseTBAA) const {
1193 const MachineFunction *MF = getMF();
1194 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
1195 const MachineFrameInfo &MFI = MF->getFrameInfo();
1196
1197 // If neither instruction stores to memory, they can't alias in any
1198 // meaningful way, even if they read from the same address.
1199 if (!mayStore() && !Other.mayStore())
1200 return false;
1201
1202 // Let the target decide if memory accesses cannot possibly overlap.
1203 if (TII->areMemAccessesTriviallyDisjoint(*this, Other))
1204 return false;
1205
1206 // FIXME: Need to handle multiple memory operands to support all targets.
1207 if (!hasOneMemOperand() || !Other.hasOneMemOperand())
1208 return true;
1209
1210 MachineMemOperand *MMOa = *memoperands_begin();
1211 MachineMemOperand *MMOb = *Other.memoperands_begin();
1212
1213 // The following interface to AA is fashioned after DAGCombiner::isAlias
1214 // and operates with MachineMemOperand offset with some important
1215 // assumptions:
1216 // - LLVM fundamentally assumes flat address spaces.
1217 // - MachineOperand offset can *only* result from legalization and
1218 // cannot affect queries other than the trivial case of overlap
1219 // checking.
1220 // - These offsets never wrap and never step outside
1221 // of allocated objects.
1222 // - There should never be any negative offsets here.
1223 //
1224 // FIXME: Modify API to hide this math from "user"
1225 // Even before we go to AA we can reason locally about some
1226 // memory objects. It can save compile time, and possibly catch some
1227 // corner cases not currently covered.
1228
1229 int64_t OffsetA = MMOa->getOffset();
1230 int64_t OffsetB = MMOb->getOffset();
1231 int64_t MinOffset = std::min(OffsetA, OffsetB);
1232
1233 uint64_t WidthA = MMOa->getSize();
1234 uint64_t WidthB = MMOb->getSize();
1235 bool KnownWidthA = WidthA != MemoryLocation::UnknownSize;
1236 bool KnownWidthB = WidthB != MemoryLocation::UnknownSize;
1237
1238 const Value *ValA = MMOa->getValue();
1239 const Value *ValB = MMOb->getValue();
1240 bool SameVal = (ValA && ValB && (ValA == ValB));
1241 if (!SameVal) {
1242 const PseudoSourceValue *PSVa = MMOa->getPseudoValue();
1243 const PseudoSourceValue *PSVb = MMOb->getPseudoValue();
1244 if (PSVa && ValB && !PSVa->mayAlias(&MFI))
1245 return false;
1246 if (PSVb && ValA && !PSVb->mayAlias(&MFI))
1247 return false;
1248 if (PSVa && PSVb && (PSVa == PSVb))
1249 SameVal = true;
1250 }
1251
1252 if (SameVal) {
1253 if (!KnownWidthA || !KnownWidthB)
1254 return true;
1255 int64_t MaxOffset = std::max(OffsetA, OffsetB);
1256 int64_t LowWidth = (MinOffset == OffsetA) ? WidthA : WidthB;
1257 return (MinOffset + LowWidth > MaxOffset);
1258 }
1259
1260 if (!AA)
1261 return true;
1262
1263 if (!ValA || !ValB)
1264 return true;
1265
1266 assert((OffsetA >= 0) && "Negative MachineMemOperand offset")(((OffsetA >= 0) && "Negative MachineMemOperand offset"
) ? static_cast<void> (0) : __assert_fail ("(OffsetA >= 0) && \"Negative MachineMemOperand offset\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/MachineInstr.cpp"
, 1266, __PRETTY_FUNCTION__))
;
1267 assert((OffsetB >= 0) && "Negative MachineMemOperand offset")(((OffsetB >= 0) && "Negative MachineMemOperand offset"
) ? static_cast<void> (0) : __assert_fail ("(OffsetB >= 0) && \"Negative MachineMemOperand offset\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/MachineInstr.cpp"
, 1267, __PRETTY_FUNCTION__))
;
1268
1269 int64_t OverlapA = KnownWidthA ? WidthA + OffsetA - MinOffset
1270 : MemoryLocation::UnknownSize;
1271 int64_t OverlapB = KnownWidthB ? WidthB + OffsetB - MinOffset
1272 : MemoryLocation::UnknownSize;
1273
1274 AliasResult AAResult = AA->alias(
1275 MemoryLocation(ValA, OverlapA,
1276 UseTBAA ? MMOa->getAAInfo() : AAMDNodes()),
1277 MemoryLocation(ValB, OverlapB,
1278 UseTBAA ? MMOb->getAAInfo() : AAMDNodes()));
1279
1280 return (AAResult != NoAlias);
1281}
1282
1283/// hasOrderedMemoryRef - Return true if this instruction may have an ordered
1284/// or volatile memory reference, or if the information describing the memory
1285/// reference is not available. Return false if it is known to have no ordered
1286/// memory references.
1287bool MachineInstr::hasOrderedMemoryRef() const {
1288 // An instruction known never to access memory won't have a volatile access.
1289 if (!mayStore() &&
1290 !mayLoad() &&
1291 !isCall() &&
1292 !hasUnmodeledSideEffects())
1293 return false;
1294
1295 // Otherwise, if the instruction has no memory reference information,
1296 // conservatively assume it wasn't preserved.
1297 if (memoperands_empty())
1298 return true;
1299
1300 // Check if any of our memory operands are ordered.
1301 return llvm::any_of(memoperands(), [](const MachineMemOperand *MMO) {
1302 return !MMO->isUnordered();
1303 });
1304}
1305
1306/// isDereferenceableInvariantLoad - Return true if this instruction will never
1307/// trap and is loading from a location whose value is invariant across a run of
1308/// this function.
1309bool MachineInstr::isDereferenceableInvariantLoad(AAResults *AA) const {
1310 // If the instruction doesn't load at all, it isn't an invariant load.
1311 if (!mayLoad())
1312 return false;
1313
1314 // If the instruction has lost its memoperands, conservatively assume that
1315 // it may not be an invariant load.
1316 if (memoperands_empty())
1317 return false;
1318
1319 const MachineFrameInfo &MFI = getParent()->getParent()->getFrameInfo();
1320
1321 for (MachineMemOperand *MMO : memoperands()) {
1322 if (!MMO->isUnordered())
1323 // If the memory operand has ordering side effects, we can't move the
1324 // instruction. Such an instruction is technically an invariant load,
1325 // but the caller code would need updated to expect that.
1326 return false;
1327 if (MMO->isStore()) return false;
1328 if (MMO->isInvariant() && MMO->isDereferenceable())
1329 continue;
1330
1331 // A load from a constant PseudoSourceValue is invariant.
1332 if (const PseudoSourceValue *PSV = MMO->getPseudoValue())
1333 if (PSV->isConstant(&MFI))
1334 continue;
1335
1336 if (const Value *V = MMO->getValue()) {
1337 // If we have an AliasAnalysis, ask it whether the memory is constant.
1338 if (AA &&
1339 AA->pointsToConstantMemory(
1340 MemoryLocation(V, MMO->getSize(), MMO->getAAInfo())))
1341 continue;
1342 }
1343
1344 // Otherwise assume conservatively.
1345 return false;
1346 }
1347
1348 // Everything checks out.
1349 return true;
1350}
1351
1352/// isConstantValuePHI - If the specified instruction is a PHI that always
1353/// merges together the same virtual register, return the register, otherwise
1354/// return 0.
1355unsigned MachineInstr::isConstantValuePHI() const {
1356 if (!isPHI())
1357 return 0;
1358 assert(getNumOperands() >= 3 &&((getNumOperands() >= 3 && "It's illegal to have a PHI without source operands"
) ? static_cast<void> (0) : __assert_fail ("getNumOperands() >= 3 && \"It's illegal to have a PHI without source operands\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/MachineInstr.cpp"
, 1359, __PRETTY_FUNCTION__))
1359 "It's illegal to have a PHI without source operands")((getNumOperands() >= 3 && "It's illegal to have a PHI without source operands"
) ? static_cast<void> (0) : __assert_fail ("getNumOperands() >= 3 && \"It's illegal to have a PHI without source operands\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/MachineInstr.cpp"
, 1359, __PRETTY_FUNCTION__))
;
1360
1361 Register Reg = getOperand(1).getReg();
1362 for (unsigned i = 3, e = getNumOperands(); i < e; i += 2)
1363 if (getOperand(i).getReg() != Reg)
1364 return 0;
1365 return Reg;
1366}
1367
1368bool MachineInstr::hasUnmodeledSideEffects() const {
1369 if (hasProperty(MCID::UnmodeledSideEffects))
1370 return true;
1371 if (isInlineAsm()) {
1372 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1373 if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1374 return true;
1375 }
1376
1377 return false;
1378}
1379
1380bool MachineInstr::isLoadFoldBarrier() const {
1381 return mayStore() || isCall() || hasUnmodeledSideEffects();
1382}
1383
1384/// allDefsAreDead - Return true if all the defs of this instruction are dead.
1385///
1386bool MachineInstr::allDefsAreDead() const {
1387 for (const MachineOperand &MO : operands()) {
1388 if (!MO.isReg() || MO.isUse())
1389 continue;
1390 if (!MO.isDead())
1391 return false;
1392 }
1393 return true;
1394}
1395
1396/// copyImplicitOps - Copy implicit register operands from specified
1397/// instruction to this instruction.
1398void MachineInstr::copyImplicitOps(MachineFunction &MF,
1399 const MachineInstr &MI) {
1400 for (unsigned i = MI.getDesc().getNumOperands(), e = MI.getNumOperands();
1401 i != e; ++i) {
1402 const MachineOperand &MO = MI.getOperand(i);
1403 if ((MO.isReg() && MO.isImplicit()) || MO.isRegMask())
1404 addOperand(MF, MO);
1405 }
1406}
1407
1408bool MachineInstr::hasComplexRegisterTies() const {
1409 const MCInstrDesc &MCID = getDesc();
1410 for (unsigned I = 0, E = getNumOperands(); I < E; ++I) {
1411 const auto &Operand = getOperand(I);
1412 if (!Operand.isReg() || Operand.isDef())
1413 // Ignore the defined registers as MCID marks only the uses as tied.
1414 continue;
1415 int ExpectedTiedIdx = MCID.getOperandConstraint(I, MCOI::TIED_TO);
1416 int TiedIdx = Operand.isTied() ? int(findTiedOperandIdx(I)) : -1;
1417 if (ExpectedTiedIdx != TiedIdx)
1418 return true;
1419 }
1420 return false;
1421}
1422
1423LLT MachineInstr::getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes,
1424 const MachineRegisterInfo &MRI) const {
1425 const MachineOperand &Op = getOperand(OpIdx);
1426 if (!Op.isReg())
1427 return LLT{};
1428
1429 if (isVariadic() || OpIdx >= getNumExplicitOperands())
1430 return MRI.getType(Op.getReg());
1431
1432 auto &OpInfo = getDesc().OpInfo[OpIdx];
1433 if (!OpInfo.isGenericType())
1434 return MRI.getType(Op.getReg());
1435
1436 if (PrintedTypes[OpInfo.getGenericTypeIndex()])
1437 return LLT{};
1438
1439 LLT TypeToPrint = MRI.getType(Op.getReg());
1440 // Don't mark the type index printed if it wasn't actually printed: maybe
1441 // another operand with the same type index has an actual type attached:
1442 if (TypeToPrint.isValid())
1443 PrintedTypes.set(OpInfo.getGenericTypeIndex());
1444 return TypeToPrint;
1445}
1446
1447#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
1448LLVM_DUMP_METHOD__attribute__((noinline)) __attribute__((__used__)) void MachineInstr::dump() const {
1449 dbgs() << " ";
1450 print(dbgs());
1451}
1452#endif
1453
1454void MachineInstr::print(raw_ostream &OS, bool IsStandalone, bool SkipOpers,
1455 bool SkipDebugLoc, bool AddNewLine,
1456 const TargetInstrInfo *TII) const {
1457 const Module *M = nullptr;
1458 const Function *F = nullptr;
1459 if (const MachineFunction *MF = getMFIfAvailable(*this)) {
1460 F = &MF->getFunction();
1461 M = F->getParent();
1462 if (!TII)
1463 TII = MF->getSubtarget().getInstrInfo();
1464 }
1465
1466 ModuleSlotTracker MST(M);
1467 if (F)
1468 MST.incorporateFunction(*F);
1469 print(OS, MST, IsStandalone, SkipOpers, SkipDebugLoc, AddNewLine, TII);
1470}
1471
1472void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST,
1473 bool IsStandalone, bool SkipOpers, bool SkipDebugLoc,
1474 bool AddNewLine, const TargetInstrInfo *TII) const {
1475 // We can be a bit tidier if we know the MachineFunction.
1476 const MachineFunction *MF = nullptr;
1477 const TargetRegisterInfo *TRI = nullptr;
1478 const MachineRegisterInfo *MRI = nullptr;
1479 const TargetIntrinsicInfo *IntrinsicInfo = nullptr;
1480 tryToGetTargetInfo(*this, TRI, MRI, IntrinsicInfo, TII);
1481
1482 if (isCFIInstruction())
1483 assert(getNumOperands() == 1 && "Expected 1 operand in CFI instruction")((getNumOperands() == 1 && "Expected 1 operand in CFI instruction"
) ? static_cast<void> (0) : __assert_fail ("getNumOperands() == 1 && \"Expected 1 operand in CFI instruction\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/MachineInstr.cpp"
, 1483, __PRETTY_FUNCTION__))
;
1484
1485 SmallBitVector PrintedTypes(8);
1486 bool ShouldPrintRegisterTies = IsStandalone || hasComplexRegisterTies();
1487 auto getTiedOperandIdx = [&](unsigned OpIdx) {
1488 if (!ShouldPrintRegisterTies)
1489 return 0U;
1490 const MachineOperand &MO = getOperand(OpIdx);
1491 if (MO.isReg() && MO.isTied() && !MO.isDef())
1492 return findTiedOperandIdx(OpIdx);
1493 return 0U;
1494 };
1495 unsigned StartOp = 0;
1496 unsigned e = getNumOperands();
1497
1498 // Print explicitly defined operands on the left of an assignment syntax.
1499 while (StartOp < e) {
1500 const MachineOperand &MO = getOperand(StartOp);
1501 if (!MO.isReg() || !MO.isDef() || MO.isImplicit())
1502 break;
1503
1504 if (StartOp != 0)
1505 OS << ", ";
1506
1507 LLT TypeToPrint = MRI ? getTypeToPrint(StartOp, PrintedTypes, *MRI) : LLT{};
1508 unsigned TiedOperandIdx = getTiedOperandIdx(StartOp);
1509 MO.print(OS, MST, TypeToPrint, /*PrintDef=*/false, IsStandalone,
1510 ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1511 ++StartOp;
1512 }
1513
1514 if (StartOp != 0)
1515 OS << " = ";
1516
1517 if (getFlag(MachineInstr::FrameSetup))
1518 OS << "frame-setup ";
1519 if (getFlag(MachineInstr::FrameDestroy))
1520 OS << "frame-destroy ";
1521 if (getFlag(MachineInstr::FmNoNans))
1522 OS << "nnan ";
1523 if (getFlag(MachineInstr::FmNoInfs))
1524 OS << "ninf ";
1525 if (getFlag(MachineInstr::FmNsz))
1526 OS << "nsz ";
1527 if (getFlag(MachineInstr::FmArcp))
1528 OS << "arcp ";
1529 if (getFlag(MachineInstr::FmContract))
1530 OS << "contract ";
1531 if (getFlag(MachineInstr::FmAfn))
1532 OS << "afn ";
1533 if (getFlag(MachineInstr::FmReassoc))
1534 OS << "reassoc ";
1535 if (getFlag(MachineInstr::NoUWrap))
1536 OS << "nuw ";
1537 if (getFlag(MachineInstr::NoSWrap))
1538 OS << "nsw ";
1539 if (getFlag(MachineInstr::IsExact))
1540 OS << "exact ";
1541 if (getFlag(MachineInstr::FPExcept))
1542 OS << "fpexcept ";
1543
1544 // Print the opcode name.
1545 if (TII)
1546 OS << TII->getName(getOpcode());
1547 else
1548 OS << "UNKNOWN";
1549
1550 if (SkipOpers)
1551 return;
1552
1553 // Print the rest of the operands.
1554 bool FirstOp = true;
1555 unsigned AsmDescOp = ~0u;
1556 unsigned AsmOpCount = 0;
1557
1558 if (isInlineAsm() && e >= InlineAsm::MIOp_FirstOperand) {
1559 // Print asm string.
1560 OS << " ";
1561 const unsigned OpIdx = InlineAsm::MIOp_AsmString;
1562 LLT TypeToPrint = MRI ? getTypeToPrint(OpIdx, PrintedTypes, *MRI) : LLT{};
1563 unsigned TiedOperandIdx = getTiedOperandIdx(OpIdx);
1564 getOperand(OpIdx).print(OS, MST, TypeToPrint, /*PrintDef=*/true, IsStandalone,
1565 ShouldPrintRegisterTies, TiedOperandIdx, TRI,
1566 IntrinsicInfo);
1567
1568 // Print HasSideEffects, MayLoad, MayStore, IsAlignStack
1569 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1570 if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1571 OS << " [sideeffect]";
1572 if (ExtraInfo & InlineAsm::Extra_MayLoad)
1573 OS << " [mayload]";
1574 if (ExtraInfo & InlineAsm::Extra_MayStore)
1575 OS << " [maystore]";
1576 if (ExtraInfo & InlineAsm::Extra_IsConvergent)
1577 OS << " [isconvergent]";
1578 if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
1579 OS << " [alignstack]";
1580 if (getInlineAsmDialect() == InlineAsm::AD_ATT)
1581 OS << " [attdialect]";
1582 if (getInlineAsmDialect() == InlineAsm::AD_Intel)
1583 OS << " [inteldialect]";
1584
1585 StartOp = AsmDescOp = InlineAsm::MIOp_FirstOperand;
1586 FirstOp = false;
1587 }
1588
1589 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
1590 const MachineOperand &MO = getOperand(i);
1591
1592 if (FirstOp) FirstOp = false; else OS << ",";
1593 OS << " ";
1594
1595 if (isDebugValue() && MO.isMetadata()) {
1596 // Pretty print DBG_VALUE instructions.
1597 auto *DIV = dyn_cast<DILocalVariable>(MO.getMetadata());
1598 if (DIV && !DIV->getName().empty())
1599 OS << "!\"" << DIV->getName() << '\"';
1600 else {
1601 LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};
1602 unsigned TiedOperandIdx = getTiedOperandIdx(i);
1603 MO.print(OS, MST, TypeToPrint, /*PrintDef=*/true, IsStandalone,
1604 ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1605 }
1606 } else if (isDebugLabel() && MO.isMetadata()) {
1607 // Pretty print DBG_LABEL instructions.
1608 auto *DIL = dyn_cast<DILabel>(MO.getMetadata());
1609 if (DIL && !DIL->getName().empty())
1610 OS << "\"" << DIL->getName() << '\"';
1611 else {
1612 LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};
1613 unsigned TiedOperandIdx = getTiedOperandIdx(i);
1614 MO.print(OS, MST, TypeToPrint, /*PrintDef=*/true, IsStandalone,
1615 ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1616 }
1617 } else if (i == AsmDescOp && MO.isImm()) {
1618 // Pretty print the inline asm operand descriptor.
1619 OS << '$' << AsmOpCount++;
1620 unsigned Flag = MO.getImm();
1621 switch (InlineAsm::getKind(Flag)) {
1622 case InlineAsm::Kind_RegUse: OS << ":[reguse"; break;
1623 case InlineAsm::Kind_RegDef: OS << ":[regdef"; break;
1624 case InlineAsm::Kind_RegDefEarlyClobber: OS << ":[regdef-ec"; break;
1625 case InlineAsm::Kind_Clobber: OS << ":[clobber"; break;
1626 case InlineAsm::Kind_Imm: OS << ":[imm"; break;
1627 case InlineAsm::Kind_Mem: OS << ":[mem"; break;
1628 default: OS << ":[??" << InlineAsm::getKind(Flag); break;
1629 }
1630
1631 unsigned RCID = 0;
1632 if (!InlineAsm::isImmKind(Flag) && !InlineAsm::isMemKind(Flag) &&
1633 InlineAsm::hasRegClassConstraint(Flag, RCID)) {
1634 if (TRI) {
1635 OS << ':' << TRI->getRegClassName(TRI->getRegClass(RCID));
1636 } else
1637 OS << ":RC" << RCID;
1638 }
1639
1640 if (InlineAsm::isMemKind(Flag)) {
1641 unsigned MCID = InlineAsm::getMemoryConstraintID(Flag);
1642 switch (MCID) {
1643 case InlineAsm::Constraint_es: OS << ":es"; break;
1644 case InlineAsm::Constraint_i: OS << ":i"; break;
1645 case InlineAsm::Constraint_m: OS << ":m"; break;
1646 case InlineAsm::Constraint_o: OS << ":o"; break;
1647 case InlineAsm::Constraint_v: OS << ":v"; break;
1648 case InlineAsm::Constraint_Q: OS << ":Q"; break;
1649 case InlineAsm::Constraint_R: OS << ":R"; break;
1650 case InlineAsm::Constraint_S: OS << ":S"; break;
1651 case InlineAsm::Constraint_T: OS << ":T"; break;
1652 case InlineAsm::Constraint_Um: OS << ":Um"; break;
1653 case InlineAsm::Constraint_Un: OS << ":Un"; break;
1654 case InlineAsm::Constraint_Uq: OS << ":Uq"; break;
1655 case InlineAsm::Constraint_Us: OS << ":Us"; break;
1656 case InlineAsm::Constraint_Ut: OS << ":Ut"; break;
1657 case InlineAsm::Constraint_Uv: OS << ":Uv"; break;
1658 case InlineAsm::Constraint_Uy: OS << ":Uy"; break;
1659 case InlineAsm::Constraint_X: OS << ":X"; break;
1660 case InlineAsm::Constraint_Z: OS << ":Z"; break;
1661 case InlineAsm::Constraint_ZC: OS << ":ZC"; break;
1662 case InlineAsm::Constraint_Zy: OS << ":Zy"; break;
1663 default: OS << ":?"; break;
1664 }
1665 }
1666
1667 unsigned TiedTo = 0;
1668 if (InlineAsm::isUseOperandTiedToDef(Flag, TiedTo))
1669 OS << " tiedto:$" << TiedTo;
1670
1671 OS << ']';
1672
1673 // Compute the index of the next operand descriptor.
1674 AsmDescOp += 1 + InlineAsm::getNumOperandRegisters(Flag);
1675 } else {
1676 LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};
1677 unsigned TiedOperandIdx = getTiedOperandIdx(i);
1678 if (MO.isImm() && isOperandSubregIdx(i))
1679 MachineOperand::printSubRegIdx(OS, MO.getImm(), TRI);
1680 else
1681 MO.print(OS, MST, TypeToPrint, /*PrintDef=*/true, IsStandalone,
1682 ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1683 }
1684 }
1685
1686 // Print any optional symbols attached to this instruction as-if they were
1687 // operands.
1688 if (MCSymbol *PreInstrSymbol = getPreInstrSymbol()) {
1689 if (!FirstOp) {
1690 FirstOp = false;
1691 OS << ',';
1692 }
1693 OS << " pre-instr-symbol ";
1694 MachineOperand::printSymbol(OS, *PreInstrSymbol);
1695 }
1696 if (MCSymbol *PostInstrSymbol = getPostInstrSymbol()) {
1697 if (!FirstOp) {
1698 FirstOp = false;
1699 OS << ',';
1700 }
1701 OS << " post-instr-symbol ";
1702 MachineOperand::printSymbol(OS, *PostInstrSymbol);
1703 }
1704 if (MDNode *HeapAllocMarker = getHeapAllocMarker()) {
1705 if (!FirstOp) {
1706 FirstOp = false;
1707 OS << ',';
1708 }
1709 OS << " heap-alloc-marker ";
1710 HeapAllocMarker->printAsOperand(OS, MST);
1711 }
1712
1713 if (!SkipDebugLoc) {
1714 if (const DebugLoc &DL = getDebugLoc()) {
1715 if (!FirstOp)
1716 OS << ',';
1717 OS << " debug-location ";
1718 DL->printAsOperand(OS, MST);
1719 }
1720 }
1721
1722 if (!memoperands_empty()) {
1723 SmallVector<StringRef, 0> SSNs;
1724 const LLVMContext *Context = nullptr;
1725 std::unique_ptr<LLVMContext> CtxPtr;
1726 const MachineFrameInfo *MFI = nullptr;
1727 if (const MachineFunction *MF = getMFIfAvailable(*this)) {
1728 MFI = &MF->getFrameInfo();
1729 Context = &MF->getFunction().getContext();
1730 } else {
1731 CtxPtr = std::make_unique<LLVMContext>();
1732 Context = CtxPtr.get();
1733 }
1734
1735 OS << " :: ";
1736 bool NeedComma = false;
1737 for (const MachineMemOperand *Op : memoperands()) {
1738 if (NeedComma)
1739 OS << ", ";
1740 Op->print(OS, MST, SSNs, *Context, MFI, TII);
1741 NeedComma = true;
1742 }
1743 }
1744
1745 if (SkipDebugLoc)
1746 return;
1747
1748 bool HaveSemi = false;
1749
1750 // Print debug location information.
1751 if (const DebugLoc &DL = getDebugLoc()) {
1752 if (!HaveSemi) {
1753 OS << ';';
1754 HaveSemi = true;
1755 }
1756 OS << ' ';
1757 DL.print(OS);
1758 }
1759
1760 // Print extra comments for DEBUG_VALUE.
1761 if (isDebugValue() && getOperand(e - 2).isMetadata()) {
1762 if (!HaveSemi) {
1763 OS << ";";
1764 HaveSemi = true;
Value stored to 'HaveSemi' is never read
1765 }
1766 auto *DV = cast<DILocalVariable>(getOperand(e - 2).getMetadata());
1767 OS << " line no:" << DV->getLine();
1768 if (auto *InlinedAt = debugLoc->getInlinedAt()) {
1769 DebugLoc InlinedAtDL(InlinedAt);
1770 if (InlinedAtDL && MF) {
1771 OS << " inlined @[ ";
1772 InlinedAtDL.print(OS);
1773 OS << " ]";
1774 }
1775 }
1776 if (isIndirectDebugValue())
1777 OS << " indirect";
1778 }
1779 // TODO: DBG_LABEL
1780
1781 if (AddNewLine)
1782 OS << '\n';
1783}
1784
1785bool MachineInstr::addRegisterKilled(Register IncomingReg,
1786 const TargetRegisterInfo *RegInfo,
1787 bool AddIfNotFound) {
1788 bool isPhysReg = Register::isPhysicalRegister(IncomingReg);
1789 bool hasAliases = isPhysReg &&
1790 MCRegAliasIterator(IncomingReg, RegInfo, false).isValid();
1791 bool Found = false;
1792 SmallVector<unsigned,4> DeadOps;
1793 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1794 MachineOperand &MO = getOperand(i);
1795 if (!MO.isReg() || !MO.isUse() || MO.isUndef())
1796 continue;
1797
1798 // DEBUG_VALUE nodes do not contribute to code generation and should
1799 // always be ignored. Failure to do so may result in trying to modify
1800 // KILL flags on DEBUG_VALUE nodes.
1801 if (MO.isDebug())
1802 continue;
1803
1804 Register Reg = MO.getReg();
1805 if (!Reg)
1806 continue;
1807
1808 if (Reg == IncomingReg) {
1809 if (!Found) {
1810 if (MO.isKill())
1811 // The register is already marked kill.
1812 return true;
1813 if (isPhysReg && isRegTiedToDefOperand(i))
1814 // Two-address uses of physregs must not be marked kill.
1815 return true;
1816 MO.setIsKill();
1817 Found = true;
1818 }
1819 } else if (hasAliases && MO.isKill() && Register::isPhysicalRegister(Reg)) {
1820 // A super-register kill already exists.
1821 if (RegInfo->isSuperRegister(IncomingReg, Reg))
1822 return true;
1823 if (RegInfo->isSubRegister(IncomingReg, Reg))
1824 DeadOps.push_back(i);
1825 }
1826 }
1827
1828 // Trim unneeded kill operands.
1829 while (!DeadOps.empty()) {
1830 unsigned OpIdx = DeadOps.back();
1831 if (getOperand(OpIdx).isImplicit() &&
1832 (!isInlineAsm() || findInlineAsmFlagIdx(OpIdx) < 0))
1833 RemoveOperand(OpIdx);
1834 else
1835 getOperand(OpIdx).setIsKill(false);
1836 DeadOps.pop_back();
1837 }
1838
1839 // If not found, this means an alias of one of the operands is killed. Add a
1840 // new implicit operand if required.
1841 if (!Found && AddIfNotFound) {
1842 addOperand(MachineOperand::CreateReg(IncomingReg,
1843 false /*IsDef*/,
1844 true /*IsImp*/,
1845 true /*IsKill*/));
1846 return true;
1847 }
1848 return Found;
1849}
1850
1851void MachineInstr::clearRegisterKills(Register Reg,
1852 const TargetRegisterInfo *RegInfo) {
1853 if (!Register::isPhysicalRegister(Reg))
1854 RegInfo = nullptr;
1855 for (MachineOperand &MO : operands()) {
1856 if (!MO.isReg() || !MO.isUse() || !MO.isKill())
1857 continue;
1858 Register OpReg = MO.getReg();
1859 if ((RegInfo && RegInfo->regsOverlap(Reg, OpReg)) || Reg == OpReg)
1860 MO.setIsKill(false);
1861 }
1862}
1863
1864bool MachineInstr::addRegisterDead(Register Reg,
1865 const TargetRegisterInfo *RegInfo,
1866 bool AddIfNotFound) {
1867 bool isPhysReg = Register::isPhysicalRegister(Reg);
1868 bool hasAliases = isPhysReg &&
1869 MCRegAliasIterator(Reg, RegInfo, false).isValid();
1870 bool Found = false;
1871 SmallVector<unsigned,4> DeadOps;
1872 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1873 MachineOperand &MO = getOperand(i);
1874 if (!MO.isReg() || !MO.isDef())
1875 continue;
1876 Register MOReg = MO.getReg();
1877 if (!MOReg)
1878 continue;
1879
1880 if (MOReg == Reg) {
1881 MO.setIsDead();
1882 Found = true;
1883 } else if (hasAliases && MO.isDead() &&
1884 Register::isPhysicalRegister(MOReg)) {
1885 // There exists a super-register that's marked dead.
1886 if (RegInfo->isSuperRegister(Reg, MOReg))
1887 return true;
1888 if (RegInfo->isSubRegister(Reg, MOReg))
1889 DeadOps.push_back(i);
1890 }
1891 }
1892
1893 // Trim unneeded dead operands.
1894 while (!DeadOps.empty()) {
1895 unsigned OpIdx = DeadOps.back();
1896 if (getOperand(OpIdx).isImplicit() &&
1897 (!isInlineAsm() || findInlineAsmFlagIdx(OpIdx) < 0))
1898 RemoveOperand(OpIdx);
1899 else
1900 getOperand(OpIdx).setIsDead(false);
1901 DeadOps.pop_back();
1902 }
1903
1904 // If not found, this means an alias of one of the operands is dead. Add a
1905 // new implicit operand if required.
1906 if (Found || !AddIfNotFound)
1907 return Found;
1908
1909 addOperand(MachineOperand::CreateReg(Reg,
1910 true /*IsDef*/,
1911 true /*IsImp*/,
1912 false /*IsKill*/,
1913 true /*IsDead*/));
1914 return true;
1915}
1916
1917void MachineInstr::clearRegisterDeads(Register Reg) {
1918 for (MachineOperand &MO : operands()) {
1919 if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg)
1920 continue;
1921 MO.setIsDead(false);
1922 }
1923}
1924
1925void MachineInstr::setRegisterDefReadUndef(Register Reg, bool IsUndef) {
1926 for (MachineOperand &MO : operands()) {
1927 if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg || MO.getSubReg() == 0)
1928 continue;
1929 MO.setIsUndef(IsUndef);
1930 }
1931}
1932
1933void MachineInstr::addRegisterDefined(Register Reg,
1934 const TargetRegisterInfo *RegInfo) {
1935 if (Register::isPhysicalRegister(Reg)) {
1936 MachineOperand *MO = findRegisterDefOperand(Reg, false, false, RegInfo);
1937 if (MO)
1938 return;
1939 } else {
1940 for (const MachineOperand &MO : operands()) {
1941 if (MO.isReg() && MO.getReg() == Reg && MO.isDef() &&
1942 MO.getSubReg() == 0)
1943 return;
1944 }
1945 }
1946 addOperand(MachineOperand::CreateReg(Reg,
1947 true /*IsDef*/,
1948 true /*IsImp*/));
1949}
1950
1951void MachineInstr::setPhysRegsDeadExcept(ArrayRef<Register> UsedRegs,
1952 const TargetRegisterInfo &TRI) {
1953 bool HasRegMask = false;
1954 for (MachineOperand &MO : operands()) {
1955 if (MO.isRegMask()) {
1956 HasRegMask = true;
1957 continue;
1958 }
1959 if (!MO.isReg() || !MO.isDef()) continue;
1960 Register Reg = MO.getReg();
1961 if (!Reg.isPhysical())
1962 continue;
1963 // If there are no uses, including partial uses, the def is dead.
1964 if (llvm::none_of(UsedRegs,
1965 [&](MCRegister Use) { return TRI.regsOverlap(Use, Reg); }))
1966 MO.setIsDead();
1967 }
1968
1969 // This is a call with a register mask operand.
1970 // Mask clobbers are always dead, so add defs for the non-dead defines.
1971 if (HasRegMask)
1972 for (ArrayRef<Register>::iterator I = UsedRegs.begin(), E = UsedRegs.end();
1973 I != E; ++I)
1974 addRegisterDefined(*I, &TRI);
1975}
1976
1977unsigned
1978MachineInstrExpressionTrait::getHashValue(const MachineInstr* const &MI) {
1979 // Build up a buffer of hash code components.
1980 SmallVector<size_t, 8> HashComponents;
1981 HashComponents.reserve(MI->getNumOperands() + 1);
1982 HashComponents.push_back(MI->getOpcode());
1983 for (const MachineOperand &MO : MI->operands()) {
1984 if (MO.isReg() && MO.isDef() && Register::isVirtualRegister(MO.getReg()))
1985 continue; // Skip virtual register defs.
1986
1987 HashComponents.push_back(hash_value(MO));
1988 }
1989 return hash_combine_range(HashComponents.begin(), HashComponents.end());
1990}
1991
1992void MachineInstr::emitError(StringRef Msg) const {
1993 // Find the source location cookie.
1994 unsigned LocCookie = 0;
1995 const MDNode *LocMD = nullptr;
1996 for (unsigned i = getNumOperands(); i != 0; --i) {
1997 if (getOperand(i-1).isMetadata() &&
1998 (LocMD = getOperand(i-1).getMetadata()) &&
1999 LocMD->getNumOperands() != 0) {
2000 if (const ConstantInt *CI =
2001 mdconst::dyn_extract<ConstantInt>(LocMD->getOperand(0))) {
2002 LocCookie = CI->getZExtValue();
2003 break;
2004 }
2005 }
2006 }
2007
2008 if (const MachineBasicBlock *MBB = getParent())
2009 if (const MachineFunction *MF = MBB->getParent())
2010 return MF->getMMI().getModule()->getContext().emitError(LocCookie, Msg);
2011 report_fatal_error(Msg);
2012}
2013
2014MachineInstrBuilder llvm::BuildMI(MachineFunction &MF, const DebugLoc &DL,
2015 const MCInstrDesc &MCID, bool IsIndirect,
2016 Register Reg, const MDNode *Variable,
2017 const MDNode *Expr) {
2018 assert(isa<DILocalVariable>(Variable) && "not a variable")((isa<DILocalVariable>(Variable) && "not a variable"
) ? static_cast<void> (0) : __assert_fail ("isa<DILocalVariable>(Variable) && \"not a variable\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/MachineInstr.cpp"
, 2018, __PRETTY_FUNCTION__))
;
2019 assert(cast<DIExpression>(Expr)->isValid() && "not an expression")((cast<DIExpression>(Expr)->isValid() && "not an expression"
) ? static_cast<void> (0) : __assert_fail ("cast<DIExpression>(Expr)->isValid() && \"not an expression\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/MachineInstr.cpp"
, 2019, __PRETTY_FUNCTION__))
;
2020 assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&((cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic
(DL) && "Expected inlined-at fields to agree") ? static_cast
<void> (0) : __assert_fail ("cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) && \"Expected inlined-at fields to agree\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/MachineInstr.cpp"
, 2021, __PRETTY_FUNCTION__))
2021 "Expected inlined-at fields to agree")((cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic
(DL) && "Expected inlined-at fields to agree") ? static_cast
<void> (0) : __assert_fail ("cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) && \"Expected inlined-at fields to agree\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/MachineInstr.cpp"
, 2021, __PRETTY_FUNCTION__))
;
2022 auto MIB = BuildMI(MF, DL, MCID).addReg(Reg, RegState::Debug);
2023 if (IsIndirect)
2024 MIB.addImm(0U);
2025 else
2026 MIB.addReg(0U, RegState::Debug);
2027 return MIB.addMetadata(Variable).addMetadata(Expr);
2028}
2029
2030MachineInstrBuilder llvm::BuildMI(MachineFunction &MF, const DebugLoc &DL,
2031 const MCInstrDesc &MCID, bool IsIndirect,
2032 MachineOperand &MO, const MDNode *Variable,
2033 const MDNode *Expr) {
2034 assert(isa<DILocalVariable>(Variable) && "not a variable")((isa<DILocalVariable>(Variable) && "not a variable"
) ? static_cast<void> (0) : __assert_fail ("isa<DILocalVariable>(Variable) && \"not a variable\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/MachineInstr.cpp"
, 2034, __PRETTY_FUNCTION__))
;
2035 assert(cast<DIExpression>(Expr)->isValid() && "not an expression")((cast<DIExpression>(Expr)->isValid() && "not an expression"
) ? static_cast<void> (0) : __assert_fail ("cast<DIExpression>(Expr)->isValid() && \"not an expression\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/MachineInstr.cpp"
, 2035, __PRETTY_FUNCTION__))
;
2036 assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&((cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic
(DL) && "Expected inlined-at fields to agree") ? static_cast
<void> (0) : __assert_fail ("cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) && \"Expected inlined-at fields to agree\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/MachineInstr.cpp"
, 2037, __PRETTY_FUNCTION__))
2037 "Expected inlined-at fields to agree")((cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic
(DL) && "Expected inlined-at fields to agree") ? static_cast
<void> (0) : __assert_fail ("cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) && \"Expected inlined-at fields to agree\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/MachineInstr.cpp"
, 2037, __PRETTY_FUNCTION__))
;
2038 if (MO.isReg())
2039 return BuildMI(MF, DL, MCID, IsIndirect, MO.getReg(), Variable, Expr);
2040
2041 auto MIB = BuildMI(MF, DL, MCID).add(MO);
2042 if (IsIndirect)
2043 MIB.addImm(0U);
2044 else
2045 MIB.addReg(0U, RegState::Debug);
2046 return MIB.addMetadata(Variable).addMetadata(Expr);
2047 }
2048
2049MachineInstrBuilder llvm::BuildMI(MachineBasicBlock &BB,
2050 MachineBasicBlock::iterator I,
2051 const DebugLoc &DL, const MCInstrDesc &MCID,
2052 bool IsIndirect, Register Reg,
2053 const MDNode *Variable, const MDNode *Expr) {
2054 MachineFunction &MF = *BB.getParent();
2055 MachineInstr *MI = BuildMI(MF, DL, MCID, IsIndirect, Reg, Variable, Expr);
2056 BB.insert(I, MI);
2057 return MachineInstrBuilder(MF, MI);
2058}
2059
2060MachineInstrBuilder llvm::BuildMI(MachineBasicBlock &BB,
2061 MachineBasicBlock::iterator I,
2062 const DebugLoc &DL, const MCInstrDesc &MCID,
2063 bool IsIndirect, MachineOperand &MO,
2064 const MDNode *Variable, const MDNode *Expr) {
2065 MachineFunction &MF = *BB.getParent();
2066 MachineInstr *MI = BuildMI(MF, DL, MCID, IsIndirect, MO, Variable, Expr);
2067 BB.insert(I, MI);
2068 return MachineInstrBuilder(MF, *MI);
2069}
2070
2071/// Compute the new DIExpression to use with a DBG_VALUE for a spill slot.
2072/// This prepends DW_OP_deref when spilling an indirect DBG_VALUE.
2073static const DIExpression *computeExprForSpill(const MachineInstr &MI) {
2074 assert(MI.getOperand(0).isReg() && "can't spill non-register")((MI.getOperand(0).isReg() && "can't spill non-register"
) ? static_cast<void> (0) : __assert_fail ("MI.getOperand(0).isReg() && \"can't spill non-register\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/MachineInstr.cpp"
, 2074, __PRETTY_FUNCTION__))
;
2075 assert(MI.getDebugVariable()->isValidLocationForIntrinsic(MI.getDebugLoc()) &&((MI.getDebugVariable()->isValidLocationForIntrinsic(MI.getDebugLoc
()) && "Expected inlined-at fields to agree") ? static_cast
<void> (0) : __assert_fail ("MI.getDebugVariable()->isValidLocationForIntrinsic(MI.getDebugLoc()) && \"Expected inlined-at fields to agree\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/MachineInstr.cpp"
, 2076, __PRETTY_FUNCTION__))
2076 "Expected inlined-at fields to agree")((MI.getDebugVariable()->isValidLocationForIntrinsic(MI.getDebugLoc
()) && "Expected inlined-at fields to agree") ? static_cast
<void> (0) : __assert_fail ("MI.getDebugVariable()->isValidLocationForIntrinsic(MI.getDebugLoc()) && \"Expected inlined-at fields to agree\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/MachineInstr.cpp"
, 2076, __PRETTY_FUNCTION__))
;
2077
2078 const DIExpression *Expr = MI.getDebugExpression();
2079 if (MI.isIndirectDebugValue()) {
2080 assert(MI.getOperand(1).getImm() == 0 && "DBG_VALUE with nonzero offset")((MI.getOperand(1).getImm() == 0 && "DBG_VALUE with nonzero offset"
) ? static_cast<void> (0) : __assert_fail ("MI.getOperand(1).getImm() == 0 && \"DBG_VALUE with nonzero offset\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/MachineInstr.cpp"
, 2080, __PRETTY_FUNCTION__))
;
2081 Expr = DIExpression::prepend(Expr, DIExpression::DerefBefore);
2082 }
2083 return Expr;
2084}
2085
2086MachineInstr *llvm::buildDbgValueForSpill(MachineBasicBlock &BB,
2087 MachineBasicBlock::iterator I,
2088 const MachineInstr &Orig,
2089 int FrameIndex) {
2090 const DIExpression *Expr = computeExprForSpill(Orig);
2091 return BuildMI(BB, I, Orig.getDebugLoc(), Orig.getDesc())
2092 .addFrameIndex(FrameIndex)
2093 .addImm(0U)
2094 .addMetadata(Orig.getDebugVariable())
2095 .addMetadata(Expr);
2096}
2097
2098void llvm::updateDbgValueForSpill(MachineInstr &Orig, int FrameIndex) {
2099 const DIExpression *Expr = computeExprForSpill(Orig);
2100 Orig.getOperand(0).ChangeToFrameIndex(FrameIndex);
2101 Orig.getOperand(1).ChangeToImmediate(0U);
2102 Orig.getOperand(3).setMetadata(Expr);
2103}
2104
2105void MachineInstr::collectDebugValues(
2106 SmallVectorImpl<MachineInstr *> &DbgValues) {
2107 MachineInstr &MI = *this;
2108 if (!MI.getOperand(0).isReg())
2109 return;
2110
2111 MachineBasicBlock::iterator DI = MI; ++DI;
2112 for (MachineBasicBlock::iterator DE = MI.getParent()->end();
2113 DI != DE; ++DI) {
2114 if (!DI->isDebugValue())
2115 return;
2116 if (DI->getOperand(0).isReg() &&
2117 DI->getOperand(0).getReg() == MI.getOperand(0).getReg())
2118 DbgValues.push_back(&*DI);
2119 }
2120}
2121
2122void MachineInstr::changeDebugValuesDefReg(Register Reg) {
2123 // Collect matching debug values.
2124 SmallVector<MachineInstr *, 2> DbgValues;
2125
2126 if (!getOperand(0).isReg())
2127 return;
2128
2129 unsigned DefReg = getOperand(0).getReg();
2130 auto *MRI = getRegInfo();
2131 for (auto &MO : MRI->use_operands(DefReg)) {
2132 auto *DI = MO.getParent();
2133 if (!DI->isDebugValue())
2134 continue;
2135 if (DI->getOperand(0).isReg() &&
2136 DI->getOperand(0).getReg() == DefReg){
2137 DbgValues.push_back(DI);
2138 }
2139 }
2140
2141 // Propagate Reg to debug value instructions.
2142 for (auto *DBI : DbgValues)
2143 DBI->getOperand(0).setReg(Reg);
2144}
2145
2146using MMOList = SmallVector<const MachineMemOperand *, 2>;
2147
2148static unsigned getSpillSlotSize(MMOList &Accesses,
2149 const MachineFrameInfo &MFI) {
2150 unsigned Size = 0;
2151 for (auto A : Accesses)
2152 if (MFI.isSpillSlotObjectIndex(
2153 cast<FixedStackPseudoSourceValue>(A->getPseudoValue())
2154 ->getFrameIndex()))
2155 Size += A->getSize();
2156 return Size;
2157}
2158
2159Optional<unsigned>
2160MachineInstr::getSpillSize(const TargetInstrInfo *TII) const {
2161 int FI;
2162 if (TII->isStoreToStackSlotPostFE(*this, FI)) {
2163 const MachineFrameInfo &MFI = getMF()->getFrameInfo();
2164 if (MFI.isSpillSlotObjectIndex(FI))
2165 return (*memoperands_begin())->getSize();
2166 }
2167 return None;
2168}
2169
2170Optional<unsigned>
2171MachineInstr::getFoldedSpillSize(const TargetInstrInfo *TII) const {
2172 MMOList Accesses;
2173 if (TII->hasStoreToStackSlot(*this, Accesses))
2174 return getSpillSlotSize(Accesses, getMF()->getFrameInfo());
2175 return None;
2176}
2177
2178Optional<unsigned>
2179MachineInstr::getRestoreSize(const TargetInstrInfo *TII) const {
2180 int FI;
2181 if (TII->isLoadFromStackSlotPostFE(*this, FI)) {
2182 const MachineFrameInfo &MFI = getMF()->getFrameInfo();
2183 if (MFI.isSpillSlotObjectIndex(FI))
2184 return (*memoperands_begin())->getSize();
2185 }
2186 return None;
2187}
2188
2189Optional<unsigned>
2190MachineInstr::getFoldedRestoreSize(const TargetInstrInfo *TII) const {
2191 MMOList Accesses;
2192 if (TII->hasLoadFromStackSlot(*this, Accesses))
2193 return getSpillSlotSize(Accesses, getMF()->getFrameInfo());
2194 return None;
2195}