Bug Summary

File:lib/CodeGen/MachineRegisterInfo.cpp
Location:line 133, column 28
Description:Called C++ object pointer is null

Annotated Source Code

1//===-- lib/Codegen/MachineRegisterInfo.cpp -------------------------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Implementation of the MachineRegisterInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/CodeGen/MachineRegisterInfo.h"
15#include "llvm/CodeGen/MachineInstrBuilder.h"
16#include "llvm/Support/raw_os_ostream.h"
17#include "llvm/Target/TargetInstrInfo.h"
18#include "llvm/Target/TargetMachine.h"
19#include "llvm/Target/TargetSubtargetInfo.h"
20
21using namespace llvm;
22
23// Pin the vtable to this file.
24void MachineRegisterInfo::Delegate::anchor() {}
25
26MachineRegisterInfo::MachineRegisterInfo(const MachineFunction *MF)
27 : MF(MF), TheDelegate(nullptr), IsSSA(true), TracksLiveness(true),
28 TracksSubRegLiveness(false) {
29 VRegInfo.reserve(256);
30 RegAllocHints.reserve(256);
31 UsedRegUnits.resize(getTargetRegisterInfo()->getNumRegUnits());
32 UsedPhysRegMask.resize(getTargetRegisterInfo()->getNumRegs());
33
34 // Create the physreg use/def lists.
35 PhysRegUseDefLists.resize(getTargetRegisterInfo()->getNumRegs(), nullptr);
36}
37
38/// setRegClass - Set the register class of the specified virtual register.
39///
40void
41MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) {
42 assert(RC && RC->isAllocatable() && "Invalid RC for virtual register")((RC && RC->isAllocatable() && "Invalid RC for virtual register"
) ? static_cast<void> (0) : __assert_fail ("RC && RC->isAllocatable() && \"Invalid RC for virtual register\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.6~svn224240/lib/CodeGen/MachineRegisterInfo.cpp"
, 42, __PRETTY_FUNCTION__));
43 VRegInfo[Reg].first = RC;
44}
45
46const TargetRegisterClass *
47MachineRegisterInfo::constrainRegClass(unsigned Reg,
48 const TargetRegisterClass *RC,
49 unsigned MinNumRegs) {
50 const TargetRegisterClass *OldRC = getRegClass(Reg);
51 if (OldRC == RC)
52 return RC;
53 const TargetRegisterClass *NewRC =
54 getTargetRegisterInfo()->getCommonSubClass(OldRC, RC);
55 if (!NewRC || NewRC == OldRC)
56 return NewRC;
57 if (NewRC->getNumRegs() < MinNumRegs)
58 return nullptr;
59 setRegClass(Reg, NewRC);
60 return NewRC;
61}
62
63bool
64MachineRegisterInfo::recomputeRegClass(unsigned Reg, const TargetMachine &TM) {
65 const TargetInstrInfo *TII = TM.getSubtargetImpl()->getInstrInfo();
66 const TargetRegisterClass *OldRC = getRegClass(Reg);
67 const TargetRegisterClass *NewRC =
68 getTargetRegisterInfo()->getLargestLegalSuperClass(OldRC);
69
70 // Stop early if there is no room to grow.
71 if (NewRC == OldRC)
72 return false;
73
74 // Accumulate constraints from all uses.
75 for (MachineOperand &MO : reg_nodbg_operands(Reg)) {
76 // Apply the effect of the given operand to NewRC.
77 MachineInstr *MI = MO.getParent();
78 unsigned OpNo = &MO - &MI->getOperand(0);
79 NewRC = MI->getRegClassConstraintEffect(OpNo, NewRC, TII,
80 getTargetRegisterInfo());
81 if (!NewRC || NewRC == OldRC)
82 return false;
83 }
84 setRegClass(Reg, NewRC);
85 return true;
86}
87
88/// createVirtualRegister - Create and return a new virtual register in the
89/// function with the specified register class.
90///
91unsigned
92MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass){
93 assert(RegClass && "Cannot create register without RegClass!")((RegClass && "Cannot create register without RegClass!"
) ? static_cast<void> (0) : __assert_fail ("RegClass && \"Cannot create register without RegClass!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.6~svn224240/lib/CodeGen/MachineRegisterInfo.cpp"
, 93, __PRETTY_FUNCTION__));
94 assert(RegClass->isAllocatable() &&((RegClass->isAllocatable() && "Virtual register RegClass must be allocatable."
) ? static_cast<void> (0) : __assert_fail ("RegClass->isAllocatable() && \"Virtual register RegClass must be allocatable.\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.6~svn224240/lib/CodeGen/MachineRegisterInfo.cpp"
, 95, __PRETTY_FUNCTION__))
95 "Virtual register RegClass must be allocatable.")((RegClass->isAllocatable() && "Virtual register RegClass must be allocatable."
) ? static_cast<void> (0) : __assert_fail ("RegClass->isAllocatable() && \"Virtual register RegClass must be allocatable.\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.6~svn224240/lib/CodeGen/MachineRegisterInfo.cpp"
, 95, __PRETTY_FUNCTION__));
96
97 // New virtual register number.
98 unsigned Reg = TargetRegisterInfo::index2VirtReg(getNumVirtRegs());
99 VRegInfo.grow(Reg);
100 VRegInfo[Reg].first = RegClass;
101 RegAllocHints.grow(Reg);
102 if (TheDelegate)
103 TheDelegate->MRI_NoteNewVirtualRegister(Reg);
104 return Reg;
105}
106
107/// clearVirtRegs - Remove all virtual registers (after physreg assignment).
108void MachineRegisterInfo::clearVirtRegs() {
109#ifndef NDEBUG
110 for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i) {
111 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
112 if (!VRegInfo[Reg].second)
113 continue;
114 verifyUseList(Reg);
115 llvm_unreachable("Remaining virtual register operands")::llvm::llvm_unreachable_internal("Remaining virtual register operands"
, "/tmp/buildd/llvm-toolchain-snapshot-3.6~svn224240/lib/CodeGen/MachineRegisterInfo.cpp"
, 115);
116 }
117#endif
118 VRegInfo.clear();
119}
120
121void MachineRegisterInfo::verifyUseList(unsigned Reg) const {
122#ifndef NDEBUG
123 bool Valid = true;
124 for (MachineOperand &M : reg_operands(Reg)) {
125 MachineOperand *MO = &M;
126 MachineInstr *MI = MO->getParent();
12
←
Calling 'MachineOperand::getParent'
→
13
←
Returning from 'MachineOperand::getParent'
→
14
←
'MI' initialized here
→
127 if (!MI) {
15
←
Assuming 'MI' is null
→
16
←
Taking true branch
→
128 errs() << PrintReg(Reg, getTargetRegisterInfo())
129 << " use list MachineOperand " << MO
130 << " has no parent instruction.\n";
131 Valid = false;
132 }
133 MachineOperand *MO0 = &MI->getOperand(0);
17
←
Called C++ object pointer is null
134 unsigned NumOps = MI->getNumOperands();
135 if (!(MO >= MO0 && MO < MO0+NumOps)) {
136 errs() << PrintReg(Reg, getTargetRegisterInfo())
137 << " use list MachineOperand " << MO
138 << " doesn't belong to parent MI: " << *MI;
139 Valid = false;
140 }
141 if (!MO->isReg()) {
142 errs() << PrintReg(Reg, getTargetRegisterInfo())
143 << " MachineOperand " << MO << ": " << *MO
144 << " is not a register\n";
145 Valid = false;
146 }
147 if (MO->getReg() != Reg) {
148 errs() << PrintReg(Reg, getTargetRegisterInfo())
149 << " use-list MachineOperand " << MO << ": "
150 << *MO << " is the wrong register\n";
151 Valid = false;
152 }
153 }
154 assert(Valid && "Invalid use list")((Valid && "Invalid use list") ? static_cast<void>
(0) : __assert_fail ("Valid && \"Invalid use list\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.6~svn224240/lib/CodeGen/MachineRegisterInfo.cpp"
, 154, __PRETTY_FUNCTION__));
155#endif
156}
157
158void MachineRegisterInfo::verifyUseLists() const {
159#ifndef NDEBUG
160 for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i)
1
Assuming 'i' is equal to 'e'
→
2
←
Loop condition is false. Execution continues on line 162
→
161 verifyUseList(TargetRegisterInfo::index2VirtReg(i));
162 for (unsigned i = 1, e = getTargetRegisterInfo()->getNumRegs(); i != e; ++i)
3
←
Assuming 'i' is not equal to 'e'
→
4
←
Loop condition is true. Entering loop body
→
5
←
Assuming 'i' is not equal to 'e'
→
6
←
Loop condition is true. Entering loop body
→
7
←
Assuming 'i' is not equal to 'e'
→
8
←
Loop condition is true. Entering loop body
→
9
←
Assuming 'i' is not equal to 'e'
→
10
←
Loop condition is true. Entering loop body
→
163 verifyUseList(i);
11
←
Calling 'MachineRegisterInfo::verifyUseList'
→
164#endif
165}
166
167/// Add MO to the linked list of operands for its register.
168void MachineRegisterInfo::addRegOperandToUseList(MachineOperand *MO) {
169 assert(!MO->isOnRegUseList() && "Already on list")((!MO->isOnRegUseList() && "Already on list") ? static_cast
<void> (0) : __assert_fail ("!MO->isOnRegUseList() && \"Already on list\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.6~svn224240/lib/CodeGen/MachineRegisterInfo.cpp"
, 169, __PRETTY_FUNCTION__));
170 MachineOperand *&HeadRef = getRegUseDefListHead(MO->getReg());
171 MachineOperand *const Head = HeadRef;
172
173 // Head points to the first list element.
174 // Next is NULL on the last list element.
175 // Prev pointers are circular, so Head->Prev == Last.
176
177 // Head is NULL for an empty list.
178 if (!Head) {
179 MO->Contents.Reg.Prev = MO;
180 MO->Contents.Reg.Next = nullptr;
181 HeadRef = MO;
182 return;
183 }
184 assert(MO->getReg() == Head->getReg() && "Different regs on the same list!")((MO->getReg() == Head->getReg() && "Different regs on the same list!"
) ? static_cast<void> (0) : __assert_fail ("MO->getReg() == Head->getReg() && \"Different regs on the same list!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.6~svn224240/lib/CodeGen/MachineRegisterInfo.cpp"
, 184, __PRETTY_FUNCTION__));
185
186 // Insert MO between Last and Head in the circular Prev chain.
187 MachineOperand *Last = Head->Contents.Reg.Prev;
188 assert(Last && "Inconsistent use list")((Last && "Inconsistent use list") ? static_cast<void
> (0) : __assert_fail ("Last && \"Inconsistent use list\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.6~svn224240/lib/CodeGen/MachineRegisterInfo.cpp"
, 188, __PRETTY_FUNCTION__));
189 assert(MO->getReg() == Last->getReg() && "Different regs on the same list!")((MO->getReg() == Last->getReg() && "Different regs on the same list!"
) ? static_cast<void> (0) : __assert_fail ("MO->getReg() == Last->getReg() && \"Different regs on the same list!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.6~svn224240/lib/CodeGen/MachineRegisterInfo.cpp"
, 189, __PRETTY_FUNCTION__));
190 Head->Contents.Reg.Prev = MO;
191 MO->Contents.Reg.Prev = Last;
192
193 // Def operands always precede uses. This allows def_iterator to stop early.
194 // Insert def operands at the front, and use operands at the back.
195 if (MO->isDef()) {
196 // Insert def at the front.
197 MO->Contents.Reg.Next = Head;
198 HeadRef = MO;
199 } else {
200 // Insert use at the end.
201 MO->Contents.Reg.Next = nullptr;
202 Last->Contents.Reg.Next = MO;
203 }
204}
205
206/// Remove MO from its use-def list.
207void MachineRegisterInfo::removeRegOperandFromUseList(MachineOperand *MO) {
208 assert(MO->isOnRegUseList() && "Operand not on use list")((MO->isOnRegUseList() && "Operand not on use list"
) ? static_cast<void> (0) : __assert_fail ("MO->isOnRegUseList() && \"Operand not on use list\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.6~svn224240/lib/CodeGen/MachineRegisterInfo.cpp"
, 208, __PRETTY_FUNCTION__));
209 MachineOperand *&HeadRef = getRegUseDefListHead(MO->getReg());
210 MachineOperand *const Head = HeadRef;
211 assert(Head && "List already empty")((Head && "List already empty") ? static_cast<void
> (0) : __assert_fail ("Head && \"List already empty\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.6~svn224240/lib/CodeGen/MachineRegisterInfo.cpp"
, 211, __PRETTY_FUNCTION__));
212
213 // Unlink this from the doubly linked list of operands.
214 MachineOperand *Next = MO->Contents.Reg.Next;
215 MachineOperand *Prev = MO->Contents.Reg.Prev;
216
217 // Prev links are circular, next link is NULL instead of looping back to Head.
218 if (MO == Head)
219 HeadRef = Next;
220 else
221 Prev->Contents.Reg.Next = Next;
222
223 (Next ? Next : Head)->Contents.Reg.Prev = Prev;
224
225 MO->Contents.Reg.Prev = nullptr;
226 MO->Contents.Reg.Next = nullptr;
227}
228
229/// Move NumOps operands from Src to Dst, updating use-def lists as needed.
230///
231/// The Dst range is assumed to be uninitialized memory. (Or it may contain
232/// operands that won't be destroyed, which is OK because the MO destructor is
233/// trivial anyway).
234///
235/// The Src and Dst ranges may overlap.
236void MachineRegisterInfo::moveOperands(MachineOperand *Dst,
237 MachineOperand *Src,
238 unsigned NumOps) {
239 assert(Src != Dst && NumOps && "Noop moveOperands")((Src != Dst && NumOps && "Noop moveOperands"
) ? static_cast<void> (0) : __assert_fail ("Src != Dst && NumOps && \"Noop moveOperands\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.6~svn224240/lib/CodeGen/MachineRegisterInfo.cpp"
, 239, __PRETTY_FUNCTION__));
240
241 // Copy backwards if Dst is within the Src range.
242 int Stride = 1;
243 if (Dst >= Src && Dst < Src + NumOps) {
244 Stride = -1;
245 Dst += NumOps - 1;
246 Src += NumOps - 1;
247 }
248
249 // Copy one operand at a time.
250 do {
251 new (Dst) MachineOperand(*Src);
252
253 // Dst takes Src's place in the use-def chain.
254 if (Src->isReg()) {
255 MachineOperand *&Head = getRegUseDefListHead(Src->getReg());
256 MachineOperand *Prev = Src->Contents.Reg.Prev;
257 MachineOperand *Next = Src->Contents.Reg.Next;
258 assert(Head && "List empty, but operand is chained")((Head && "List empty, but operand is chained") ? static_cast
<void> (0) : __assert_fail ("Head && \"List empty, but operand is chained\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.6~svn224240/lib/CodeGen/MachineRegisterInfo.cpp"
, 258, __PRETTY_FUNCTION__));
259 assert(Prev && "Operand was not on use-def list")((Prev && "Operand was not on use-def list") ? static_cast
<void> (0) : __assert_fail ("Prev && \"Operand was not on use-def list\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.6~svn224240/lib/CodeGen/MachineRegisterInfo.cpp"
, 259, __PRETTY_FUNCTION__));
260
261 // Prev links are circular, next link is NULL instead of looping back to
262 // Head.
263 if (Src == Head)
264 Head = Dst;
265 else
266 Prev->Contents.Reg.Next = Dst;
267
268 // Update Prev pointer. This also works when Src was pointing to itself
269 // in a 1-element list. In that case Head == Dst.
270 (Next ? Next : Head)->Contents.Reg.Prev = Dst;
271 }
272
273 Dst += Stride;
274 Src += Stride;
275 } while (--NumOps);
276}
277
278/// replaceRegWith - Replace all instances of FromReg with ToReg in the
279/// machine function. This is like llvm-level X->replaceAllUsesWith(Y),
280/// except that it also changes any definitions of the register as well.
281/// If ToReg is a physical register we apply the sub register to obtain the
282/// final/proper physical register.
283void MachineRegisterInfo::replaceRegWith(unsigned FromReg, unsigned ToReg) {
284 assert(FromReg != ToReg && "Cannot replace a reg with itself")((FromReg != ToReg && "Cannot replace a reg with itself"
) ? static_cast<void> (0) : __assert_fail ("FromReg != ToReg && \"Cannot replace a reg with itself\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.6~svn224240/lib/CodeGen/MachineRegisterInfo.cpp"
, 284, __PRETTY_FUNCTION__));
285
286 const TargetRegisterInfo *TRI = getTargetRegisterInfo();
287
288 // TODO: This could be more efficient by bulk changing the operands.
289 for (reg_iterator I = reg_begin(FromReg), E = reg_end(); I != E; ) {
290 MachineOperand &O = *I;
291 ++I;
292 if (TargetRegisterInfo::isPhysicalRegister(ToReg)) {
293 O.substPhysReg(ToReg, *TRI);
294 } else {
295 O.setReg(ToReg);
296 }
297 }
298}
299
300/// getVRegDef - Return the machine instr that defines the specified virtual
301/// register or null if none is found. This assumes that the code is in SSA
302/// form, so there should only be one definition.
303MachineInstr *MachineRegisterInfo::getVRegDef(unsigned Reg) const {
304 // Since we are in SSA form, we can use the first definition.
305 def_instr_iterator I = def_instr_begin(Reg);
306 assert((I.atEnd() || std::next(I) == def_instr_end()) &&(((I.atEnd() || std::next(I) == def_instr_end()) && "getVRegDef assumes a single definition or no definition"
) ? static_cast<void> (0) : __assert_fail ("(I.atEnd() || std::next(I) == def_instr_end()) && \"getVRegDef assumes a single definition or no definition\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.6~svn224240/lib/CodeGen/MachineRegisterInfo.cpp"
, 307, __PRETTY_FUNCTION__))
307 "getVRegDef assumes a single definition or no definition")(((I.atEnd() || std::next(I) == def_instr_end()) && "getVRegDef assumes a single definition or no definition"
) ? static_cast<void> (0) : __assert_fail ("(I.atEnd() || std::next(I) == def_instr_end()) && \"getVRegDef assumes a single definition or no definition\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.6~svn224240/lib/CodeGen/MachineRegisterInfo.cpp"
, 307, __PRETTY_FUNCTION__));
308 return !I.atEnd() ? &*I : nullptr;
309}
310
311/// getUniqueVRegDef - Return the unique machine instr that defines the
312/// specified virtual register or null if none is found. If there are
313/// multiple definitions or no definition, return null.
314MachineInstr *MachineRegisterInfo::getUniqueVRegDef(unsigned Reg) const {
315 if (def_empty(Reg)) return nullptr;
316 def_instr_iterator I = def_instr_begin(Reg);
317 if (std::next(I) != def_instr_end())
318 return nullptr;
319 return &*I;
320}
321
322bool MachineRegisterInfo::hasOneNonDBGUse(unsigned RegNo) const {
323 use_nodbg_iterator UI = use_nodbg_begin(RegNo);
324 if (UI == use_nodbg_end())
325 return false;
326 return ++UI == use_nodbg_end();
327}
328
329/// clearKillFlags - Iterate over all the uses of the given register and
330/// clear the kill flag from the MachineOperand. This function is used by
331/// optimization passes which extend register lifetimes and need only
332/// preserve conservative kill flag information.
333void MachineRegisterInfo::clearKillFlags(unsigned Reg) const {
334 for (MachineOperand &MO : use_operands(Reg))
335 MO.setIsKill(false);
336}
337
338bool MachineRegisterInfo::isLiveIn(unsigned Reg) const {
339 for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
340 if (I->first == Reg || I->second == Reg)
341 return true;
342 return false;
343}
344
345/// getLiveInPhysReg - If VReg is a live-in virtual register, return the
346/// corresponding live-in physical register.
347unsigned MachineRegisterInfo::getLiveInPhysReg(unsigned VReg) const {
348 for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
349 if (I->second == VReg)
350 return I->first;
351 return 0;
352}
353
354/// getLiveInVirtReg - If PReg is a live-in physical register, return the
355/// corresponding live-in physical register.
356unsigned MachineRegisterInfo::getLiveInVirtReg(unsigned PReg) const {
357 for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
358 if (I->first == PReg)
359 return I->second;
360 return 0;
361}
362
363/// EmitLiveInCopies - Emit copies to initialize livein virtual registers
364/// into the given entry block.
365void
366MachineRegisterInfo::EmitLiveInCopies(MachineBasicBlock *EntryMBB,
367 const TargetRegisterInfo &TRI,
368 const TargetInstrInfo &TII) {
369 // Emit the copies into the top of the block.
370 for (unsigned i = 0, e = LiveIns.size(); i != e; ++i)
371 if (LiveIns[i].second) {
372 if (use_empty(LiveIns[i].second)) {
373 // The livein has no uses. Drop it.
374 //
375 // It would be preferable to have isel avoid creating live-in
376 // records for unused arguments in the first place, but it's
377 // complicated by the debug info code for arguments.
378 LiveIns.erase(LiveIns.begin() + i);
379 --i; --e;
380 } else {
381 // Emit a copy.
382 BuildMI(*EntryMBB, EntryMBB->begin(), DebugLoc(),
383 TII.get(TargetOpcode::COPY), LiveIns[i].second)
384 .addReg(LiveIns[i].first);
385
386 // Add the register to the entry block live-in set.
387 EntryMBB->addLiveIn(LiveIns[i].first);
388 }
389 } else {
390 // Add the register to the entry block live-in set.
391 EntryMBB->addLiveIn(LiveIns[i].first);
392 }
393}
394
395unsigned MachineRegisterInfo::getMaxLaneMaskForVReg(unsigned Reg) const
396{
397 // Lane masks are only defined for vregs.
398 assert(TargetRegisterInfo::isVirtualRegister(Reg))((TargetRegisterInfo::isVirtualRegister(Reg)) ? static_cast<
void> (0) : __assert_fail ("TargetRegisterInfo::isVirtualRegister(Reg)"
, "/tmp/buildd/llvm-toolchain-snapshot-3.6~svn224240/lib/CodeGen/MachineRegisterInfo.cpp"
, 398, __PRETTY_FUNCTION__));
399 const TargetRegisterClass &TRC = *getRegClass(Reg);
400 return TRC.getLaneMask();
401}
402
403#ifndef NDEBUG
404void MachineRegisterInfo::dumpUses(unsigned Reg) const {
405 for (MachineInstr &I : use_instructions(Reg))
406 I.dump();
407}
408#endif
409
410void MachineRegisterInfo::freezeReservedRegs(const MachineFunction &MF) {
411 ReservedRegs = getTargetRegisterInfo()->getReservedRegs(MF);
412 assert(ReservedRegs.size() == getTargetRegisterInfo()->getNumRegs() &&((ReservedRegs.size() == getTargetRegisterInfo()->getNumRegs
() && "Invalid ReservedRegs vector from target") ? static_cast
<void> (0) : __assert_fail ("ReservedRegs.size() == getTargetRegisterInfo()->getNumRegs() && \"Invalid ReservedRegs vector from target\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.6~svn224240/lib/CodeGen/MachineRegisterInfo.cpp"
, 413, __PRETTY_FUNCTION__))
413 "Invalid ReservedRegs vector from target")((ReservedRegs.size() == getTargetRegisterInfo()->getNumRegs
() && "Invalid ReservedRegs vector from target") ? static_cast
<void> (0) : __assert_fail ("ReservedRegs.size() == getTargetRegisterInfo()->getNumRegs() && \"Invalid ReservedRegs vector from target\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.6~svn224240/lib/CodeGen/MachineRegisterInfo.cpp"
, 413, __PRETTY_FUNCTION__));
414}
415
416bool MachineRegisterInfo::isConstantPhysReg(unsigned PhysReg,
417 const MachineFunction &MF) const {
418 assert(TargetRegisterInfo::isPhysicalRegister(PhysReg))((TargetRegisterInfo::isPhysicalRegister(PhysReg)) ? static_cast
<void> (0) : __assert_fail ("TargetRegisterInfo::isPhysicalRegister(PhysReg)"
, "/tmp/buildd/llvm-toolchain-snapshot-3.6~svn224240/lib/CodeGen/MachineRegisterInfo.cpp"
, 418, __PRETTY_FUNCTION__));
419
420 // Check if any overlapping register is modified, or allocatable so it may be
421 // used later.
422 for (MCRegAliasIterator AI(PhysReg, getTargetRegisterInfo(), true);
423 AI.isValid(); ++AI)
424 if (!def_empty(*AI) || isAllocatable(*AI))
425 return false;
426 return true;
427}
428
429/// markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the
430/// specified register as undefined which causes the DBG_VALUE to be
431/// deleted during LiveDebugVariables analysis.
432void MachineRegisterInfo::markUsesInDebugValueAsUndef(unsigned Reg) const {
433 // Mark any DBG_VALUE that uses Reg as undef (but don't delete it.)
434 MachineRegisterInfo::use_instr_iterator nextI;
435 for (use_instr_iterator I = use_instr_begin(Reg), E = use_instr_end();
436 I != E; I = nextI) {
437 nextI = std::next(I); // I is invalidated by the setReg
438 MachineInstr *UseMI = &*I;
439 if (UseMI->isDebugValue())
440 UseMI->getOperand(0).setReg(0U);
441 }
442}