Bug Summary

File:lib/Target/Mips/Disassembler/MipsDisassembler.cpp
Location:line 869, column 5
Description:Value stored to 'Result' is never read

Annotated Source Code

1//===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file is part of the Mips Disassembler.
11//
12//===----------------------------------------------------------------------===//
13
14#include "Mips.h"
15#include "MipsRegisterInfo.h"
16#include "MipsSubtarget.h"
17#include "llvm/MC/MCContext.h"
18#include "llvm/MC/MCDisassembler.h"
19#include "llvm/MC/MCFixedLenDisassembler.h"
20#include "llvm/MC/MCInst.h"
21#include "llvm/MC/MCSubtargetInfo.h"
22#include "llvm/Support/MathExtras.h"
23#include "llvm/Support/TargetRegistry.h"
24
25using namespace llvm;
26
27#define DEBUG_TYPE"mips-disassembler" "mips-disassembler"
28
29typedef MCDisassembler::DecodeStatus DecodeStatus;
30
31namespace {
32
33class MipsDisassembler : public MCDisassembler {
34 bool IsMicroMips;
35 bool IsBigEndian;
36public:
37 MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool IsBigEndian)
38 : MCDisassembler(STI, Ctx),
39 IsMicroMips(STI.getFeatureBits()[Mips::FeatureMicroMips]),
40 IsBigEndian(IsBigEndian) {}
41
42 bool hasMips3() const { return STI.getFeatureBits()[Mips::FeatureMips3]; }
43 bool hasMips32() const { return STI.getFeatureBits()[Mips::FeatureMips32]; }
44 bool hasMips32r6() const {
45 return STI.getFeatureBits()[Mips::FeatureMips32r6];
46 }
47
48 bool isGP64() const { return STI.getFeatureBits()[Mips::FeatureGP64Bit]; }
49
50 bool hasCnMips() const { return STI.getFeatureBits()[Mips::FeatureCnMips]; }
51
52 bool hasCOP3() const {
53 // Only present in MIPS-I and MIPS-II
54 return !hasMips32() && !hasMips3();
55 }
56
57 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
58 ArrayRef<uint8_t> Bytes, uint64_t Address,
59 raw_ostream &VStream,
60 raw_ostream &CStream) const override;
61};
62
63} // end anonymous namespace
64
65// Forward declare these because the autogenerated code will reference them.
66// Definitions are further down.
67static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
68 unsigned RegNo,
69 uint64_t Address,
70 const void *Decoder);
71
72static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
73 unsigned RegNo,
74 uint64_t Address,
75 const void *Decoder);
76
77static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst,
78 unsigned RegNo,
79 uint64_t Address,
80 const void *Decoder);
81
82static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst,
83 unsigned RegNo,
84 uint64_t Address,
85 const void *Decoder);
86
87static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst,
88 unsigned RegNo,
89 uint64_t Address,
90 const void *Decoder);
91
92static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
93 unsigned RegNo,
94 uint64_t Address,
95 const void *Decoder);
96
97static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
98 unsigned Insn,
99 uint64_t Address,
100 const void *Decoder);
101
102static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
103 unsigned RegNo,
104 uint64_t Address,
105 const void *Decoder);
106
107static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
108 unsigned RegNo,
109 uint64_t Address,
110 const void *Decoder);
111
112static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
113 unsigned RegNo,
114 uint64_t Address,
115 const void *Decoder);
116
117static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
118 unsigned RegNo,
119 uint64_t Address,
120 const void *Decoder);
121
122static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
123 unsigned RegNo,
124 uint64_t Address,
125 const void *Decoder);
126
127static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
128 uint64_t Address,
129 const void *Decoder);
130
131static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
132 unsigned Insn,
133 uint64_t Address,
134 const void *Decoder);
135
136static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
137 unsigned RegNo,
138 uint64_t Address,
139 const void *Decoder);
140
141static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
142 unsigned RegNo,
143 uint64_t Address,
144 const void *Decoder);
145
146static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
147 unsigned RegNo,
148 uint64_t Address,
149 const void *Decoder);
150
151static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
152 unsigned RegNo,
153 uint64_t Address,
154 const void *Decoder);
155
156static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
157 unsigned RegNo,
158 uint64_t Address,
159 const void *Decoder);
160
161static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
162 unsigned RegNo,
163 uint64_t Address,
164 const void *Decoder);
165
166static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
167 unsigned RegNo,
168 uint64_t Address,
169 const void *Decoder);
170
171static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
172 unsigned RegNo,
173 uint64_t Address,
174 const void *Decoder);
175
176static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
177 unsigned RegNo,
178 uint64_t Address,
179 const void *Decoder);
180
181static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst,
182 unsigned RegNo,
183 uint64_t Address,
184 const void *Decoder);
185
186static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
187 unsigned RegNo,
188 uint64_t Address,
189 const void *Decoder);
190
191static DecodeStatus DecodeBranchTarget(MCInst &Inst,
192 unsigned Offset,
193 uint64_t Address,
194 const void *Decoder);
195
196static DecodeStatus DecodeJumpTarget(MCInst &Inst,
197 unsigned Insn,
198 uint64_t Address,
199 const void *Decoder);
200
201static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
202 unsigned Offset,
203 uint64_t Address,
204 const void *Decoder);
205
206static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
207 unsigned Offset,
208 uint64_t Address,
209 const void *Decoder);
210
211// DecodeBranchTarget7MM - Decode microMIPS branch offset, which is
212// shifted left by 1 bit.
213static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst,
214 unsigned Offset,
215 uint64_t Address,
216 const void *Decoder);
217
218// DecodeBranchTarget10MM - Decode microMIPS branch offset, which is
219// shifted left by 1 bit.
220static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst,
221 unsigned Offset,
222 uint64_t Address,
223 const void *Decoder);
224
225// DecodeBranchTargetMM - Decode microMIPS branch offset, which is
226// shifted left by 1 bit.
227static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
228 unsigned Offset,
229 uint64_t Address,
230 const void *Decoder);
231
232// DecodeJumpTargetMM - Decode microMIPS jump target, which is
233// shifted left by 1 bit.
234static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
235 unsigned Insn,
236 uint64_t Address,
237 const void *Decoder);
238
239static DecodeStatus DecodeMem(MCInst &Inst,
240 unsigned Insn,
241 uint64_t Address,
242 const void *Decoder);
243
244static DecodeStatus DecodeMemEVA(MCInst &Inst,
245 unsigned Insn,
246 uint64_t Address,
247 const void *Decoder);
248
249static DecodeStatus DecodeLoadByte9(MCInst &Inst,
250 unsigned Insn,
251 uint64_t Address,
252 const void *Decoder);
253
254static DecodeStatus DecodeLoadByte15(MCInst &Inst,
255 unsigned Insn,
256 uint64_t Address,
257 const void *Decoder);
258
259static DecodeStatus DecodeCacheOp(MCInst &Inst,
260 unsigned Insn,
261 uint64_t Address,
262 const void *Decoder);
263
264static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst,
265 unsigned Insn,
266 uint64_t Address,
267 const void *Decoder);
268
269static DecodeStatus DecodeCacheOpMM(MCInst &Inst,
270 unsigned Insn,
271 uint64_t Address,
272 const void *Decoder);
273
274static DecodeStatus DecodeStoreEvaOpMM(MCInst &Inst,
275 unsigned Insn,
276 uint64_t Address,
277 const void *Decoder);
278
279static DecodeStatus DecodePrefeOpMM(MCInst &Inst,
280 unsigned Insn,
281 uint64_t Address,
282 const void *Decoder);
283
284static DecodeStatus DecodeSyncI(MCInst &Inst,
285 unsigned Insn,
286 uint64_t Address,
287 const void *Decoder);
288
289static DecodeStatus DecodeSynciR6(MCInst &Inst,
290 unsigned Insn,
291 uint64_t Address,
292 const void *Decoder);
293
294static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
295 uint64_t Address, const void *Decoder);
296
297static DecodeStatus DecodeMemMMImm4(MCInst &Inst,
298 unsigned Insn,
299 uint64_t Address,
300 const void *Decoder);
301
302static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst,
303 unsigned Insn,
304 uint64_t Address,
305 const void *Decoder);
306
307static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst,
308 unsigned Insn,
309 uint64_t Address,
310 const void *Decoder);
311
312static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst,
313 unsigned Insn,
314 uint64_t Address,
315 const void *Decoder);
316
317static DecodeStatus DecodeMemMMImm9(MCInst &Inst,
318 unsigned Insn,
319 uint64_t Address,
320 const void *Decoder);
321
322static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
323 unsigned Insn,
324 uint64_t Address,
325 const void *Decoder);
326
327static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
328 unsigned Insn,
329 uint64_t Address,
330 const void *Decoder);
331
332static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn,
333 uint64_t Address,
334 const void *Decoder);
335
336static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn,
337 uint64_t Address,
338 const void *Decoder);
339
340static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn,
341 uint64_t Address,
342 const void *Decoder);
343
344static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, unsigned Insn,
345 uint64_t Address,
346 const void *Decoder);
347
348static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
349 unsigned Insn,
350 uint64_t Address,
351 const void *Decoder);
352
353static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst,
354 unsigned Value,
355 uint64_t Address,
356 const void *Decoder);
357
358static DecodeStatus DecodeUImm6Lsl2(MCInst &Inst,
359 unsigned Value,
360 uint64_t Address,
361 const void *Decoder);
362
363static DecodeStatus DecodeLiSimm7(MCInst &Inst,
364 unsigned Value,
365 uint64_t Address,
366 const void *Decoder);
367
368static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst,
369 unsigned Value,
370 uint64_t Address,
371 const void *Decoder);
372
373static DecodeStatus DecodeSimm4(MCInst &Inst,
374 unsigned Value,
375 uint64_t Address,
376 const void *Decoder);
377
378static DecodeStatus DecodeSimm16(MCInst &Inst,
379 unsigned Insn,
380 uint64_t Address,
381 const void *Decoder);
382
383template <unsigned Bits, int Offset>
384static DecodeStatus DecodeUImmWithOffset(MCInst &Inst, unsigned Value,
385 uint64_t Address, const void *Decoder);
386
387static DecodeStatus DecodeInsSize(MCInst &Inst,
388 unsigned Insn,
389 uint64_t Address,
390 const void *Decoder);
391
392static DecodeStatus DecodeExtSize(MCInst &Inst,
393 unsigned Insn,
394 uint64_t Address,
395 const void *Decoder);
396
397static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
398 uint64_t Address, const void *Decoder);
399
400static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
401 uint64_t Address, const void *Decoder);
402
403static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn,
404 uint64_t Address, const void *Decoder);
405
406static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn,
407 uint64_t Address, const void *Decoder);
408
409static DecodeStatus DecodeUImm5lsl2(MCInst &Inst, unsigned Insn,
410 uint64_t Address, const void *Decoder);
411
412static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn,
413 uint64_t Address, const void *Decoder);
414
415/// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't
416/// handle.
417template <typename InsnType>
418static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
419 const void *Decoder);
420
421template <typename InsnType>
422static DecodeStatus
423DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
424 const void *Decoder);
425
426template <typename InsnType>
427static DecodeStatus
428DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
429 const void *Decoder);
430
431template <typename InsnType>
432static DecodeStatus
433DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
434 const void *Decoder);
435
436template <typename InsnType>
437static DecodeStatus
438DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
439 const void *Decoder);
440
441template <typename InsnType>
442static DecodeStatus
443DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
444 const void *Decoder);
445
446template <typename InsnType>
447static DecodeStatus
448DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
449 const void *Decoder);
450
451static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn,
452 uint64_t Address,
453 const void *Decoder);
454
455static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn,
456 uint64_t Address,
457 const void *Decoder);
458
459static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned Insn,
460 uint64_t Address,
461 const void *Decoder);
462
463namespace llvm {
464extern Target TheMipselTarget, TheMipsTarget, TheMips64Target,
465 TheMips64elTarget;
466}
467
468static MCDisassembler *createMipsDisassembler(
469 const Target &T,
470 const MCSubtargetInfo &STI,
471 MCContext &Ctx) {
472 return new MipsDisassembler(STI, Ctx, true);
473}
474
475static MCDisassembler *createMipselDisassembler(
476 const Target &T,
477 const MCSubtargetInfo &STI,
478 MCContext &Ctx) {
479 return new MipsDisassembler(STI, Ctx, false);
480}
481
482extern "C" void LLVMInitializeMipsDisassembler() {
483 // Register the disassembler.
484 TargetRegistry::RegisterMCDisassembler(TheMipsTarget,
485 createMipsDisassembler);
486 TargetRegistry::RegisterMCDisassembler(TheMipselTarget,
487 createMipselDisassembler);
488 TargetRegistry::RegisterMCDisassembler(TheMips64Target,
489 createMipsDisassembler);
490 TargetRegistry::RegisterMCDisassembler(TheMips64elTarget,
491 createMipselDisassembler);
492}
493
494#include "MipsGenDisassemblerTables.inc"
495
496static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
497 const MipsDisassembler *Dis = static_cast<const MipsDisassembler*>(D);
498 const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo();
499 return *(RegInfo->getRegClass(RC).begin() + RegNo);
500}
501
502template <typename InsnType>
503static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
504 const void *Decoder) {
505 typedef DecodeStatus (*DecodeFN)(MCInst &, unsigned, uint64_t, const void *);
506 // The size of the n field depends on the element size
507 // The register class also depends on this.
508 InsnType tmp = fieldFromInstruction(insn, 17, 5);
509 unsigned NSize = 0;
510 DecodeFN RegDecoder = nullptr;
511 if ((tmp & 0x18) == 0x00) { // INSVE_B
512 NSize = 4;
513 RegDecoder = DecodeMSA128BRegisterClass;
514 } else if ((tmp & 0x1c) == 0x10) { // INSVE_H
515 NSize = 3;
516 RegDecoder = DecodeMSA128HRegisterClass;
517 } else if ((tmp & 0x1e) == 0x18) { // INSVE_W
518 NSize = 2;
519 RegDecoder = DecodeMSA128WRegisterClass;
520 } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D
521 NSize = 1;
522 RegDecoder = DecodeMSA128DRegisterClass;
523 } else
524 llvm_unreachable("Invalid encoding")::llvm::llvm_unreachable_internal("Invalid encoding", "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn253036/lib/Target/Mips/Disassembler/MipsDisassembler.cpp"
, 524);
525
526 assert(NSize != 0 && RegDecoder != nullptr)((NSize != 0 && RegDecoder != nullptr) ? static_cast<
void> (0) : __assert_fail ("NSize != 0 && RegDecoder != nullptr"
, "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn253036/lib/Target/Mips/Disassembler/MipsDisassembler.cpp"
, 526, __PRETTY_FUNCTION__));
527
528 // $wd
529 tmp = fieldFromInstruction(insn, 6, 5);
530 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
531 return MCDisassembler::Fail;
532 // $wd_in
533 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
534 return MCDisassembler::Fail;
535 // $n
536 tmp = fieldFromInstruction(insn, 16, NSize);
537 MI.addOperand(MCOperand::createImm(tmp));
538 // $ws
539 tmp = fieldFromInstruction(insn, 11, 5);
540 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
541 return MCDisassembler::Fail;
542 // $n2
543 MI.addOperand(MCOperand::createImm(0));
544
545 return MCDisassembler::Success;
546}
547
548template <typename InsnType>
549static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn,
550 uint64_t Address,
551 const void *Decoder) {
552 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
553 // (otherwise we would have matched the ADDI instruction from the earlier
554 // ISA's instead).
555 //
556 // We have:
557 // 0b001000 sssss ttttt iiiiiiiiiiiiiiii
558 // BOVC if rs >= rt
559 // BEQZALC if rs == 0 && rt != 0
560 // BEQC if rs < rt && rs != 0
561
562 InsnType Rs = fieldFromInstruction(insn, 21, 5);
563 InsnType Rt = fieldFromInstruction(insn, 16, 5);
564 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
565 bool HasRs = false;
566
567 if (Rs >= Rt) {
568 MI.setOpcode(Mips::BOVC);
569 HasRs = true;
570 } else if (Rs != 0 && Rs < Rt) {
571 MI.setOpcode(Mips::BEQC);
572 HasRs = true;
573 } else
574 MI.setOpcode(Mips::BEQZALC);
575
576 if (HasRs)
577 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
578 Rs)));
579
580 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
581 Rt)));
582 MI.addOperand(MCOperand::createImm(Imm));
583
584 return MCDisassembler::Success;
585}
586
587template <typename InsnType>
588static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn,
589 uint64_t Address,
590 const void *Decoder) {
591 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
592 // (otherwise we would have matched the ADDI instruction from the earlier
593 // ISA's instead).
594 //
595 // We have:
596 // 0b011000 sssss ttttt iiiiiiiiiiiiiiii
597 // BNVC if rs >= rt
598 // BNEZALC if rs == 0 && rt != 0
599 // BNEC if rs < rt && rs != 0
600
601 InsnType Rs = fieldFromInstruction(insn, 21, 5);
602 InsnType Rt = fieldFromInstruction(insn, 16, 5);
603 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
604 bool HasRs = false;
605
606 if (Rs >= Rt) {
607 MI.setOpcode(Mips::BNVC);
608 HasRs = true;
609 } else if (Rs != 0 && Rs < Rt) {
610 MI.setOpcode(Mips::BNEC);
611 HasRs = true;
612 } else
613 MI.setOpcode(Mips::BNEZALC);
614
615 if (HasRs)
616 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
617 Rs)));
618
619 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
620 Rt)));
621 MI.addOperand(MCOperand::createImm(Imm));
622
623 return MCDisassembler::Success;
624}
625
626template <typename InsnType>
627static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn,
628 uint64_t Address,
629 const void *Decoder) {
630 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
631 // (otherwise we would have matched the BLEZL instruction from the earlier
632 // ISA's instead).
633 //
634 // We have:
635 // 0b010110 sssss ttttt iiiiiiiiiiiiiiii
636 // Invalid if rs == 0
637 // BLEZC if rs == 0 && rt != 0
638 // BGEZC if rs == rt && rt != 0
639 // BGEC if rs != rt && rs != 0 && rt != 0
640
641 InsnType Rs = fieldFromInstruction(insn, 21, 5);
642 InsnType Rt = fieldFromInstruction(insn, 16, 5);
643 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
644 bool HasRs = false;
645
646 if (Rt == 0)
647 return MCDisassembler::Fail;
648 else if (Rs == 0)
649 MI.setOpcode(Mips::BLEZC);
650 else if (Rs == Rt)
651 MI.setOpcode(Mips::BGEZC);
652 else {
653 HasRs = true;
654 MI.setOpcode(Mips::BGEC);
655 }
656
657 if (HasRs)
658 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
659 Rs)));
660
661 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
662 Rt)));
663
664 MI.addOperand(MCOperand::createImm(Imm));
665
666 return MCDisassembler::Success;
667}
668
669template <typename InsnType>
670static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn,
671 uint64_t Address,
672 const void *Decoder) {
673 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
674 // (otherwise we would have matched the BGTZL instruction from the earlier
675 // ISA's instead).
676 //
677 // We have:
678 // 0b010111 sssss ttttt iiiiiiiiiiiiiiii
679 // Invalid if rs == 0
680 // BGTZC if rs == 0 && rt != 0
681 // BLTZC if rs == rt && rt != 0
682 // BLTC if rs != rt && rs != 0 && rt != 0
683
684 bool HasRs = false;
685
686 InsnType Rs = fieldFromInstruction(insn, 21, 5);
687 InsnType Rt = fieldFromInstruction(insn, 16, 5);
688 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
689
690 if (Rt == 0)
691 return MCDisassembler::Fail;
692 else if (Rs == 0)
693 MI.setOpcode(Mips::BGTZC);
694 else if (Rs == Rt)
695 MI.setOpcode(Mips::BLTZC);
696 else {
697 MI.setOpcode(Mips::BLTC);
698 HasRs = true;
699 }
700
701 if (HasRs)
702 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
703 Rs)));
704
705 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
706 Rt)));
707
708 MI.addOperand(MCOperand::createImm(Imm));
709
710 return MCDisassembler::Success;
711}
712
713template <typename InsnType>
714static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn,
715 uint64_t Address,
716 const void *Decoder) {
717 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
718 // (otherwise we would have matched the BGTZ instruction from the earlier
719 // ISA's instead).
720 //
721 // We have:
722 // 0b000111 sssss ttttt iiiiiiiiiiiiiiii
723 // BGTZ if rt == 0
724 // BGTZALC if rs == 0 && rt != 0
725 // BLTZALC if rs != 0 && rs == rt
726 // BLTUC if rs != 0 && rs != rt
727
728 InsnType Rs = fieldFromInstruction(insn, 21, 5);
729 InsnType Rt = fieldFromInstruction(insn, 16, 5);
730 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
731 bool HasRs = false;
732 bool HasRt = false;
733
734 if (Rt == 0) {
735 MI.setOpcode(Mips::BGTZ);
736 HasRs = true;
737 } else if (Rs == 0) {
738 MI.setOpcode(Mips::BGTZALC);
739 HasRt = true;
740 } else if (Rs == Rt) {
741 MI.setOpcode(Mips::BLTZALC);
742 HasRs = true;
743 } else {
744 MI.setOpcode(Mips::BLTUC);
745 HasRs = true;
746 HasRt = true;
747 }
748
749 if (HasRs)
750 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
751 Rs)));
752
753 if (HasRt)
754 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
755 Rt)));
756
757 MI.addOperand(MCOperand::createImm(Imm));
758
759 return MCDisassembler::Success;
760}
761
762template <typename InsnType>
763static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn,
764 uint64_t Address,
765 const void *Decoder) {
766 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
767 // (otherwise we would have matched the BLEZL instruction from the earlier
768 // ISA's instead).
769 //
770 // We have:
771 // 0b000110 sssss ttttt iiiiiiiiiiiiiiii
772 // Invalid if rs == 0
773 // BLEZALC if rs == 0 && rt != 0
774 // BGEZALC if rs == rt && rt != 0
775 // BGEUC if rs != rt && rs != 0 && rt != 0
776
777 InsnType Rs = fieldFromInstruction(insn, 21, 5);
778 InsnType Rt = fieldFromInstruction(insn, 16, 5);
779 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
780 bool HasRs = false;
781
782 if (Rt == 0)
783 return MCDisassembler::Fail;
784 else if (Rs == 0)
785 MI.setOpcode(Mips::BLEZALC);
786 else if (Rs == Rt)
787 MI.setOpcode(Mips::BGEZALC);
788 else {
789 HasRs = true;
790 MI.setOpcode(Mips::BGEUC);
791 }
792
793 if (HasRs)
794 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
795 Rs)));
796 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
797 Rt)));
798
799 MI.addOperand(MCOperand::createImm(Imm));
800
801 return MCDisassembler::Success;
802}
803
804/// Read two bytes from the ArrayRef and return 16 bit halfword sorted
805/// according to the given endianess.
806static DecodeStatus readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address,
807 uint64_t &Size, uint32_t &Insn,
808 bool IsBigEndian) {
809 // We want to read exactly 2 Bytes of data.
810 if (Bytes.size() < 2) {
811 Size = 0;
812 return MCDisassembler::Fail;
813 }
814
815 if (IsBigEndian) {
816 Insn = (Bytes[0] << 8) | Bytes[1];
817 } else {
818 Insn = (Bytes[1] << 8) | Bytes[0];
819 }
820
821 return MCDisassembler::Success;
822}
823
824/// Read four bytes from the ArrayRef and return 32 bit word sorted
825/// according to the given endianess
826static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address,
827 uint64_t &Size, uint32_t &Insn,
828 bool IsBigEndian, bool IsMicroMips) {
829 // We want to read exactly 4 Bytes of data.
830 if (Bytes.size() < 4) {
831 Size = 0;
832 return MCDisassembler::Fail;
833 }
834
835 // High 16 bits of a 32-bit microMIPS instruction (where the opcode is)
836 // always precede the low 16 bits in the instruction stream (that is, they
837 // are placed at lower addresses in the instruction stream).
838 //
839 // microMIPS byte ordering:
840 // Big-endian: 0 | 1 | 2 | 3
841 // Little-endian: 1 | 0 | 3 | 2
842
843 if (IsBigEndian) {
844 // Encoded as a big-endian 32-bit word in the stream.
845 Insn =
846 (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | (Bytes[0] << 24);
847 } else {
848 if (IsMicroMips) {
849 Insn = (Bytes[2] << 0) | (Bytes[3] << 8) | (Bytes[0] << 16) |
850 (Bytes[1] << 24);
851 } else {
852 Insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) |
853 (Bytes[3] << 24);
854 }
855 }
856
857 return MCDisassembler::Success;
858}
859
860DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
861 ArrayRef<uint8_t> Bytes,
862 uint64_t Address,
863 raw_ostream &VStream,
864 raw_ostream &CStream) const {
865 uint32_t Insn;
866 DecodeStatus Result;
867
868 if (IsMicroMips) {
869 Result = readInstruction16(Bytes, Address, Size, Insn, IsBigEndian);
Value stored to 'Result' is never read
870
871 if (hasMips32r6()) {
872 DEBUG(dbgs() << "Trying MicroMipsR616 table (16-bit instructions):\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("mips-disassembler")) { dbgs() << "Trying MicroMipsR616 table (16-bit instructions):\n"
; } } while (0);
873 // Calling the auto-generated decoder function for microMIPS32R6
874 // (and microMIPS64R6) 16-bit instructions.
875 Result = decodeInstruction(DecoderTableMicroMipsR616, Instr, Insn,
876 Address, this, STI);
877 if (Result != MCDisassembler::Fail) {
878 Size = 2;
879 return Result;
880 }
881 }
882
883 DEBUG(dbgs() << "Trying MicroMips16 table (16-bit instructions):\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("mips-disassembler")) { dbgs() << "Trying MicroMips16 table (16-bit instructions):\n"
; } } while (0);
884 // Calling the auto-generated decoder function for microMIPS 16-bit
885 // instructions.
886 Result = decodeInstruction(DecoderTableMicroMips16, Instr, Insn, Address,
887 this, STI);
888 if (Result != MCDisassembler::Fail) {
889 Size = 2;
890 return Result;
891 }
892
893 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, true);
894 if (Result == MCDisassembler::Fail)
895 return MCDisassembler::Fail;
896
897 if (hasMips32r6()) {
898 DEBUG(dbgs() << "Trying MicroMips32r632 table (32-bit instructions):\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("mips-disassembler")) { dbgs() << "Trying MicroMips32r632 table (32-bit instructions):\n"
; } } while (0);
899 // Calling the auto-generated decoder function.
900 Result = decodeInstruction(DecoderTableMicroMipsR632, Instr, Insn, Address,
901 this, STI);
902 if (Result != MCDisassembler::Fail) {
903 Size = 4;
904 return Result;
905 }
906 }
907
908 DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("mips-disassembler")) { dbgs() << "Trying MicroMips32 table (32-bit instructions):\n"
; } } while (0);
909 // Calling the auto-generated decoder function.
910 Result = decodeInstruction(DecoderTableMicroMips32, Instr, Insn, Address,
911 this, STI);
912 if (Result != MCDisassembler::Fail) {
913 Size = 4;
914 return Result;
915 }
916 return MCDisassembler::Fail;
917 }
918
919 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false);
920 if (Result == MCDisassembler::Fail)
921 return MCDisassembler::Fail;
922
923 if (hasCOP3()) {
924 DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("mips-disassembler")) { dbgs() << "Trying COP3_ table (32-bit opcodes):\n"
; } } while (0);
925 Result =
926 decodeInstruction(DecoderTableCOP3_32, Instr, Insn, Address, this, STI);
927 if (Result != MCDisassembler::Fail) {
928 Size = 4;
929 return Result;
930 }
931 }
932
933 if (hasMips32r6() && isGP64()) {
934 DEBUG(dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("mips-disassembler")) { dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n"
; } } while (0);
935 Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, Instr, Insn,
936 Address, this, STI);
937 if (Result != MCDisassembler::Fail) {
938 Size = 4;
939 return Result;
940 }
941 }
942
943 if (hasMips32r6()) {
944 DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("mips-disassembler")) { dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n"
; } } while (0);
945 Result = decodeInstruction(DecoderTableMips32r6_64r632, Instr, Insn,
946 Address, this, STI);
947 if (Result != MCDisassembler::Fail) {
948 Size = 4;
949 return Result;
950 }
951 }
952
953 if (hasCnMips()) {
954 DEBUG(dbgs() << "Trying CnMips table (32-bit opcodes):\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("mips-disassembler")) { dbgs() << "Trying CnMips table (32-bit opcodes):\n"
; } } while (0);
955 Result = decodeInstruction(DecoderTableCnMips32, Instr, Insn,
956 Address, this, STI);
957 if (Result != MCDisassembler::Fail) {
958 Size = 4;
959 return Result;
960 }
961 }
962
963 if (isGP64()) {
964 DEBUG(dbgs() << "Trying Mips64 (GPR64) table (32-bit opcodes):\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("mips-disassembler")) { dbgs() << "Trying Mips64 (GPR64) table (32-bit opcodes):\n"
; } } while (0);
965 Result = decodeInstruction(DecoderTableMips6432, Instr, Insn,
966 Address, this, STI);
967 if (Result != MCDisassembler::Fail) {
968 Size = 4;
969 return Result;
970 }
971 }
972
973 DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("mips-disassembler")) { dbgs() << "Trying Mips table (32-bit opcodes):\n"
; } } while (0);
974 // Calling the auto-generated decoder function.
975 Result =
976 decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI);
977 if (Result != MCDisassembler::Fail) {
978 Size = 4;
979 return Result;
980 }
981
982 return MCDisassembler::Fail;
983}
984
985static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
986 unsigned RegNo,
987 uint64_t Address,
988 const void *Decoder) {
989
990 return MCDisassembler::Fail;
991
992}
993
994static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
995 unsigned RegNo,
996 uint64_t Address,
997 const void *Decoder) {
998
999 if (RegNo > 31)
1000 return MCDisassembler::Fail;
1001
1002 unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo);
1003 Inst.addOperand(MCOperand::createReg(Reg));
1004 return MCDisassembler::Success;
1005}
1006
1007static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst,
1008 unsigned RegNo,
1009 uint64_t Address,
1010 const void *Decoder) {
1011 if (RegNo > 7)
1012 return MCDisassembler::Fail;
1013 unsigned Reg = getReg(Decoder, Mips::GPRMM16RegClassID, RegNo);
1014 Inst.addOperand(MCOperand::createReg(Reg));
1015 return MCDisassembler::Success;
1016}
1017
1018static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst,
1019 unsigned RegNo,
1020 uint64_t Address,
1021 const void *Decoder) {
1022 if (RegNo > 7)
1023 return MCDisassembler::Fail;
1024 unsigned Reg = getReg(Decoder, Mips::GPRMM16ZeroRegClassID, RegNo);
1025 Inst.addOperand(MCOperand::createReg(Reg));
1026 return MCDisassembler::Success;
1027}
1028
1029static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst,
1030 unsigned RegNo,
1031 uint64_t Address,
1032 const void *Decoder) {
1033 if (RegNo > 7)
1034 return MCDisassembler::Fail;
1035 unsigned Reg = getReg(Decoder, Mips::GPRMM16MovePRegClassID, RegNo);
1036 Inst.addOperand(MCOperand::createReg(Reg));
1037 return MCDisassembler::Success;
1038}
1039
1040static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
1041 unsigned RegNo,
1042 uint64_t Address,
1043 const void *Decoder) {
1044 if (RegNo > 31)
1045 return MCDisassembler::Fail;
1046 unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo);
1047 Inst.addOperand(MCOperand::createReg(Reg));
1048 return MCDisassembler::Success;
1049}
1050
1051static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
1052 unsigned RegNo,
1053 uint64_t Address,
1054 const void *Decoder) {
1055 if (static_cast<const MipsDisassembler *>(Decoder)->isGP64())
1056 return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder);
1057
1058 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
1059}
1060
1061static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
1062 unsigned RegNo,
1063 uint64_t Address,
1064 const void *Decoder) {
1065 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
1066}
1067
1068static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
1069 unsigned RegNo,
1070 uint64_t Address,
1071 const void *Decoder) {
1072 if (RegNo > 31)
1073 return MCDisassembler::Fail;
1074
1075 unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo);
1076 Inst.addOperand(MCOperand::createReg(Reg));
1077 return MCDisassembler::Success;
1078}
1079
1080static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
1081 unsigned RegNo,
1082 uint64_t Address,
1083 const void *Decoder) {
1084 if (RegNo > 31)
1085 return MCDisassembler::Fail;
1086
1087 unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo);
1088 Inst.addOperand(MCOperand::createReg(Reg));
1089 return MCDisassembler::Success;
1090}
1091
1092static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
1093 unsigned RegNo,
1094 uint64_t Address,
1095 const void *Decoder) {
1096 if (RegNo > 31)
1097 return MCDisassembler::Fail;
1098 unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo);
1099 Inst.addOperand(MCOperand::createReg(Reg));
1100 return MCDisassembler::Success;
1101}
1102
1103static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
1104 unsigned RegNo,
1105 uint64_t Address,
1106 const void *Decoder) {
1107 if (RegNo > 7)
1108 return MCDisassembler::Fail;
1109 unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo);
1110 Inst.addOperand(MCOperand::createReg(Reg));
1111 return MCDisassembler::Success;
1112}
1113
1114static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
1115 uint64_t Address,
1116 const void *Decoder) {
1117 if (RegNo > 31)
1118 return MCDisassembler::Fail;
1119
1120 unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo);
1121 Inst.addOperand(MCOperand::createReg(Reg));
1122 return MCDisassembler::Success;
1123}
1124
1125static DecodeStatus DecodeMem(MCInst &Inst,
1126 unsigned Insn,
1127 uint64_t Address,
1128 const void *Decoder) {
1129 int Offset = SignExtend32<16>(Insn & 0xffff);
1130 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1131 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1132
1133 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1134 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1135
1136 if (Inst.getOpcode() == Mips::SC ||
1137 Inst.getOpcode() == Mips::SCD)
1138 Inst.addOperand(MCOperand::createReg(Reg));
1139
1140 Inst.addOperand(MCOperand::createReg(Reg));
1141 Inst.addOperand(MCOperand::createReg(Base));
1142 Inst.addOperand(MCOperand::createImm(Offset));
1143
1144 return MCDisassembler::Success;
1145}
1146
1147static DecodeStatus DecodeMemEVA(MCInst &Inst,
1148 unsigned Insn,
1149 uint64_t Address,
1150 const void *Decoder) {
1151 int Offset = SignExtend32<9>(Insn >> 7);
1152 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1153 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1154
1155 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1156 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1157
1158 if (Inst.getOpcode() == Mips::SCE)
1159 Inst.addOperand(MCOperand::createReg(Reg));
1160
1161 Inst.addOperand(MCOperand::createReg(Reg));
1162 Inst.addOperand(MCOperand::createReg(Base));
1163 Inst.addOperand(MCOperand::createImm(Offset));
1164
1165 return MCDisassembler::Success;
1166}
1167
1168static DecodeStatus DecodeLoadByte9(MCInst &Inst,
1169 unsigned Insn,
1170 uint64_t Address,
1171 const void *Decoder) {
1172 int Offset = SignExtend32<9>(Insn & 0x1ff);
1173 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1174 unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1175
1176 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1177 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1178
1179 Inst.addOperand(MCOperand::createReg(Reg));
1180 Inst.addOperand(MCOperand::createReg(Base));
1181 Inst.addOperand(MCOperand::createImm(Offset));
1182
1183 return MCDisassembler::Success;
1184}
1185
1186static DecodeStatus DecodeLoadByte15(MCInst &Inst,
1187 unsigned Insn,
1188 uint64_t Address,
1189 const void *Decoder) {
1190 int Offset = SignExtend32<16>(Insn & 0xffff);
1191 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1192 unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1193
1194 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1195 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1196
1197 Inst.addOperand(MCOperand::createReg(Reg));
1198 Inst.addOperand(MCOperand::createReg(Base));
1199 Inst.addOperand(MCOperand::createImm(Offset));
1200
1201 return MCDisassembler::Success;
1202}
1203
1204static DecodeStatus DecodeCacheOp(MCInst &Inst,
1205 unsigned Insn,
1206 uint64_t Address,
1207 const void *Decoder) {
1208 int Offset = SignExtend32<16>(Insn & 0xffff);
1209 unsigned Hint = fieldFromInstruction(Insn, 16, 5);
1210 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1211
1212 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1213
1214 Inst.addOperand(MCOperand::createReg(Base));
1215 Inst.addOperand(MCOperand::createImm(Offset));
1216 Inst.addOperand(MCOperand::createImm(Hint));
1217
1218 return MCDisassembler::Success;
1219}
1220
1221static DecodeStatus DecodeCacheOpMM(MCInst &Inst,
1222 unsigned Insn,
1223 uint64_t Address,
1224 const void *Decoder) {
1225 int Offset = SignExtend32<12>(Insn & 0xfff);
1226 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1227 unsigned Hint = fieldFromInstruction(Insn, 21, 5);
1228
1229 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1230
1231 Inst.addOperand(MCOperand::createReg(Base));
1232 Inst.addOperand(MCOperand::createImm(Offset));
1233 Inst.addOperand(MCOperand::createImm(Hint));
1234
1235 return MCDisassembler::Success;
1236}
1237
1238static DecodeStatus DecodePrefeOpMM(MCInst &Inst,
1239 unsigned Insn,
1240 uint64_t Address,
1241 const void *Decoder) {
1242 int Offset = SignExtend32<9>(Insn & 0x1ff);
1243 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1244 unsigned Hint = fieldFromInstruction(Insn, 21, 5);
1245
1246 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1247
1248 Inst.addOperand(MCOperand::createReg(Base));
1249 Inst.addOperand(MCOperand::createImm(Offset));
1250 Inst.addOperand(MCOperand::createImm(Hint));
1251
1252 return MCDisassembler::Success;
1253}
1254
1255static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst,
1256 unsigned Insn,
1257 uint64_t Address,
1258 const void *Decoder) {
1259 int Offset = SignExtend32<9>(Insn >> 7);
1260 unsigned Hint = fieldFromInstruction(Insn, 16, 5);
1261 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1262
1263 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1264
1265 Inst.addOperand(MCOperand::createReg(Base));
1266 Inst.addOperand(MCOperand::createImm(Offset));
1267 Inst.addOperand(MCOperand::createImm(Hint));
1268
1269 return MCDisassembler::Success;
1270}
1271
1272static DecodeStatus DecodeStoreEvaOpMM(MCInst &Inst,
1273 unsigned Insn,
1274 uint64_t Address,
1275 const void *Decoder) {
1276 int Offset = SignExtend32<9>(Insn & 0x1ff);
1277 unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1278 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1279
1280 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1281 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1282
1283 Inst.addOperand(MCOperand::createReg(Reg));
1284 Inst.addOperand(MCOperand::createReg(Base));
1285 Inst.addOperand(MCOperand::createImm(Offset));
1286
1287 return MCDisassembler::Success;
1288}
1289
1290static DecodeStatus DecodeSyncI(MCInst &Inst,
1291 unsigned Insn,
1292 uint64_t Address,
1293 const void *Decoder) {
1294 int Offset = SignExtend32<16>(Insn & 0xffff);
1295 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1296
1297 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1298
1299 Inst.addOperand(MCOperand::createReg(Base));
1300 Inst.addOperand(MCOperand::createImm(Offset));
1301
1302 return MCDisassembler::Success;
1303}
1304
1305static DecodeStatus DecodeSynciR6(MCInst &Inst,
1306 unsigned Insn,
1307 uint64_t Address,
1308 const void *Decoder) {
1309 int Immediate = SignExtend32<16>(Insn & 0xffff);
1310 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1311
1312 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1313
1314 Inst.addOperand(MCOperand::createReg(Base));
1315 Inst.addOperand(MCOperand::createImm(Immediate));
1316
1317 return MCDisassembler::Success;
1318}
1319
1320static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
1321 uint64_t Address, const void *Decoder) {
1322 int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10));
1323 unsigned Reg = fieldFromInstruction(Insn, 6, 5);
1324 unsigned Base = fieldFromInstruction(Insn, 11, 5);
1325
1326 Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg);
1327 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1328
1329 Inst.addOperand(MCOperand::createReg(Reg));
1330 Inst.addOperand(MCOperand::createReg(Base));
1331
1332 // The immediate field of an LD/ST instruction is scaled which means it must
1333 // be multiplied (when decoding) by the size (in bytes) of the instructions'
1334 // data format.
1335 // .b - 1 byte
1336 // .h - 2 bytes
1337 // .w - 4 bytes
1338 // .d - 8 bytes
1339 switch(Inst.getOpcode())
1340 {
1341 default:
1342 assert (0 && "Unexpected instruction")((0 && "Unexpected instruction") ? static_cast<void
> (0) : __assert_fail ("0 && \"Unexpected instruction\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn253036/lib/Target/Mips/Disassembler/MipsDisassembler.cpp"
, 1342, __PRETTY_FUNCTION__));
1343 return MCDisassembler::Fail;
1344 break;
1345 case Mips::LD_B:
1346 case Mips::ST_B:
1347 Inst.addOperand(MCOperand::createImm(Offset));
1348 break;
1349 case Mips::LD_H:
1350 case Mips::ST_H:
1351 Inst.addOperand(MCOperand::createImm(Offset * 2));
1352 break;
1353 case Mips::LD_W:
1354 case Mips::ST_W:
1355 Inst.addOperand(MCOperand::createImm(Offset * 4));
1356 break;
1357 case Mips::LD_D:
1358 case Mips::ST_D:
1359 Inst.addOperand(MCOperand::createImm(Offset * 8));
1360 break;
1361 }
1362
1363 return MCDisassembler::Success;
1364}
1365
1366static DecodeStatus DecodeMemMMImm4(MCInst &Inst,
1367 unsigned Insn,
1368 uint64_t Address,
1369 const void *Decoder) {
1370 unsigned Offset = Insn & 0xf;
1371 unsigned Reg = fieldFromInstruction(Insn, 7, 3);
1372 unsigned Base = fieldFromInstruction(Insn, 4, 3);
1373
1374 switch (Inst.getOpcode()) {
1375 case Mips::LBU16_MM:
1376 case Mips::LHU16_MM:
1377 case Mips::LW16_MM:
1378 if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder)
1379 == MCDisassembler::Fail)
1380 return MCDisassembler::Fail;
1381 break;
1382 case Mips::SB16_MM:
1383 case Mips::SB16_MMR6:
1384 case Mips::SH16_MM:
1385 case Mips::SH16_MMR6:
1386 case Mips::SW16_MM:
1387 case Mips::SW16_MMR6:
1388 if (DecodeGPRMM16ZeroRegisterClass(Inst, Reg, Address, Decoder)
1389 == MCDisassembler::Fail)
1390 return MCDisassembler::Fail;
1391 break;
1392 }
1393
1394 if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder)
1395 == MCDisassembler::Fail)
1396 return MCDisassembler::Fail;
1397
1398 switch (Inst.getOpcode()) {
1399 case Mips::LBU16_MM:
1400 if (Offset == 0xf)
1401 Inst.addOperand(MCOperand::createImm(-1));
1402 else
1403 Inst.addOperand(MCOperand::createImm(Offset));
1404 break;
1405 case Mips::SB16_MM:
1406 case Mips::SB16_MMR6:
1407 Inst.addOperand(MCOperand::createImm(Offset));
1408 break;
1409 case Mips::LHU16_MM:
1410 case Mips::SH16_MM:
1411 case Mips::SH16_MMR6:
1412 Inst.addOperand(MCOperand::createImm(Offset << 1));
1413 break;
1414 case Mips::LW16_MM:
1415 case Mips::SW16_MM:
1416 case Mips::SW16_MMR6:
1417 Inst.addOperand(MCOperand::createImm(Offset << 2));
1418 break;
1419 }
1420
1421 return MCDisassembler::Success;
1422}
1423
1424static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst,
1425 unsigned Insn,
1426 uint64_t Address,
1427 const void *Decoder) {
1428 unsigned Offset = Insn & 0x1F;
1429 unsigned Reg = fieldFromInstruction(Insn, 5, 5);
1430
1431 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1432
1433 Inst.addOperand(MCOperand::createReg(Reg));
1434 Inst.addOperand(MCOperand::createReg(Mips::SP));
1435 Inst.addOperand(MCOperand::createImm(Offset << 2));
1436
1437 return MCDisassembler::Success;
1438}
1439
1440static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst,
1441 unsigned Insn,
1442 uint64_t Address,
1443 const void *Decoder) {
1444 unsigned Offset = Insn & 0x7F;
1445 unsigned Reg = fieldFromInstruction(Insn, 7, 3);
1446
1447 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1448
1449 Inst.addOperand(MCOperand::createReg(Reg));
1450 Inst.addOperand(MCOperand::createReg(Mips::GP));
1451 Inst.addOperand(MCOperand::createImm(Offset << 2));
1452
1453 return MCDisassembler::Success;
1454}
1455
1456static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst,
1457 unsigned Insn,
1458 uint64_t Address,
1459 const void *Decoder) {
1460 int Offset;
1461 switch (Inst.getOpcode()) {
1462 case Mips::LWM16_MMR6:
1463 case Mips::SWM16_MMR6:
1464 Offset = fieldFromInstruction(Insn, 4, 4);
1465 break;
1466 default:
1467 Offset = SignExtend32<4>(Insn & 0xf);
1468 break;
1469 }
1470
1471 if (DecodeRegListOperand16(Inst, Insn, Address, Decoder)
1472 == MCDisassembler::Fail)
1473 return MCDisassembler::Fail;
1474
1475 Inst.addOperand(MCOperand::createReg(Mips::SP));
1476 Inst.addOperand(MCOperand::createImm(Offset << 2));
1477
1478 return MCDisassembler::Success;
1479}
1480
1481static DecodeStatus DecodeMemMMImm9(MCInst &Inst,
1482 unsigned Insn,
1483 uint64_t Address,
1484 const void *Decoder) {
1485 int Offset = SignExtend32<9>(Insn & 0x1ff);
1486 unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1487 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1488
1489 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1490 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1491
1492 if (Inst.getOpcode() == Mips::SCE_MM)
1493 Inst.addOperand(MCOperand::createReg(Reg));
1494
1495 Inst.addOperand(MCOperand::createReg(Reg));
1496 Inst.addOperand(MCOperand::createReg(Base));
1497 Inst.addOperand(MCOperand::createImm(Offset));
1498
1499 return MCDisassembler::Success;
1500}
1501
1502static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
1503 unsigned Insn,
1504 uint64_t Address,
1505 const void *Decoder) {
1506 int Offset = SignExtend32<12>(Insn & 0x0fff);
1507 unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1508 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1509
1510 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1511 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1512
1513 switch (Inst.getOpcode()) {
1514 case Mips::SWM32_MM:
1515 case Mips::LWM32_MM:
1516 if (DecodeRegListOperand(Inst, Insn, Address, Decoder)
1517 == MCDisassembler::Fail)
1518 return MCDisassembler::Fail;
1519 Inst.addOperand(MCOperand::createReg(Base));
1520 Inst.addOperand(MCOperand::createImm(Offset));
1521 break;
1522 case Mips::SC_MM:
1523 Inst.addOperand(MCOperand::createReg(Reg));
1524 // fallthrough
1525 default:
1526 Inst.addOperand(MCOperand::createReg(Reg));
1527 if (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM)
1528 Inst.addOperand(MCOperand::createReg(Reg+1));
1529
1530 Inst.addOperand(MCOperand::createReg(Base));
1531 Inst.addOperand(MCOperand::createImm(Offset));
1532 }
1533
1534 return MCDisassembler::Success;
1535}
1536
1537static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
1538 unsigned Insn,
1539 uint64_t Address,
1540 const void *Decoder) {
1541 int Offset = SignExtend32<16>(Insn & 0xffff);
1542 unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1543 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1544
1545 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1546 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1547
1548 Inst.addOperand(MCOperand::createReg(Reg));
1549 Inst.addOperand(MCOperand::createReg(Base));
1550 Inst.addOperand(MCOperand::createImm(Offset));
1551
1552 return MCDisassembler::Success;
1553}
1554
1555static DecodeStatus DecodeFMem(MCInst &Inst,
1556 unsigned Insn,
1557 uint64_t Address,
1558 const void *Decoder) {
1559 int Offset = SignExtend32<16>(Insn & 0xffff);
1560 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1561 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1562
1563 Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg);
1564 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1565
1566 Inst.addOperand(MCOperand::createReg(Reg));
1567 Inst.addOperand(MCOperand::createReg(Base));
1568 Inst.addOperand(MCOperand::createImm(Offset));
1569
1570 return MCDisassembler::Success;
1571}
1572
1573static DecodeStatus DecodeFMem2(MCInst &Inst,
1574 unsigned Insn,
1575 uint64_t Address,
1576 const void *Decoder) {
1577 int Offset = SignExtend32<16>(Insn & 0xffff);
1578 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1579 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1580
1581 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
1582 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1583
1584 Inst.addOperand(MCOperand::createReg(Reg));
1585 Inst.addOperand(MCOperand::createReg(Base));
1586 Inst.addOperand(MCOperand::createImm(Offset));
1587
1588 return MCDisassembler::Success;
1589}
1590
1591static DecodeStatus DecodeFMem3(MCInst &Inst,
1592 unsigned Insn,
1593 uint64_t Address,
1594 const void *Decoder) {
1595 int Offset = SignExtend32<16>(Insn & 0xffff);
1596 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1597 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1598
1599 Reg = getReg(Decoder, Mips::COP3RegClassID, Reg);
1600 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1601
1602 Inst.addOperand(MCOperand::createReg(Reg));
1603 Inst.addOperand(MCOperand::createReg(Base));
1604 Inst.addOperand(MCOperand::createImm(Offset));
1605
1606 return MCDisassembler::Success;
1607}
1608
1609static DecodeStatus DecodeFMemCop2R6(MCInst &Inst,
1610 unsigned Insn,
1611 uint64_t Address,
1612 const void *Decoder) {
1613 int Offset = SignExtend32<11>(Insn & 0x07ff);
1614 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1615 unsigned Base = fieldFromInstruction(Insn, 11, 5);
1616
1617 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
1618 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1619
1620 Inst.addOperand(MCOperand::createReg(Reg));
1621 Inst.addOperand(MCOperand::createReg(Base));
1622 Inst.addOperand(MCOperand::createImm(Offset));
1623
1624 return MCDisassembler::Success;
1625}
1626static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
1627 unsigned Insn,
1628 uint64_t Address,
1629 const void *Decoder) {
1630 int64_t Offset = SignExtend64<9>((Insn >> 7) & 0x1ff);
1631 unsigned Rt = fieldFromInstruction(Insn, 16, 5);
1632 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1633
1634 Rt = getReg(Decoder, Mips::GPR32RegClassID, Rt);
1635 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1636
1637 if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){
1638 Inst.addOperand(MCOperand::createReg(Rt));
1639 }
1640
1641 Inst.addOperand(MCOperand::createReg(Rt));
1642 Inst.addOperand(MCOperand::createReg(Base));
1643 Inst.addOperand(MCOperand::createImm(Offset));
1644
1645 return MCDisassembler::Success;
1646}
1647
1648static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
1649 unsigned RegNo,
1650 uint64_t Address,
1651 const void *Decoder) {
1652 // Currently only hardware register 29 is supported.
1653 if (RegNo != 29)
1654 return MCDisassembler::Fail;
1655 Inst.addOperand(MCOperand::createReg(Mips::HWR29));
1656 return MCDisassembler::Success;
1657}
1658
1659static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
1660 unsigned RegNo,
1661 uint64_t Address,
1662 const void *Decoder) {
1663 if (RegNo > 30 || RegNo %2)
1664 return MCDisassembler::Fail;
1665
1666 ;
1667 unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2);
1668 Inst.addOperand(MCOperand::createReg(Reg));
1669 return MCDisassembler::Success;
1670}
1671
1672static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
1673 unsigned RegNo,
1674 uint64_t Address,
1675 const void *Decoder) {
1676 if (RegNo >= 4)
1677 return MCDisassembler::Fail;
1678
1679 unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo);
1680 Inst.addOperand(MCOperand::createReg(Reg));
1681 return MCDisassembler::Success;
1682}
1683
1684static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
1685 unsigned RegNo,
1686 uint64_t Address,
1687 const void *Decoder) {
1688 if (RegNo >= 4)
1689 return MCDisassembler::Fail;
1690
1691 unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo);
1692 Inst.addOperand(MCOperand::createReg(Reg));
1693 return MCDisassembler::Success;
1694}
1695
1696static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
1697 unsigned RegNo,
1698 uint64_t Address,
1699 const void *Decoder) {
1700 if (RegNo >= 4)
1701 return MCDisassembler::Fail;
1702
1703 unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo);
1704 Inst.addOperand(MCOperand::createReg(Reg));
1705 return MCDisassembler::Success;
1706}
1707
1708static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
1709 unsigned RegNo,
1710 uint64_t Address,
1711 const void *Decoder) {
1712 if (RegNo > 31)
1713 return MCDisassembler::Fail;
1714
1715 unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo);
1716 Inst.addOperand(MCOperand::createReg(Reg));
1717 return MCDisassembler::Success;
1718}
1719
1720static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
1721 unsigned RegNo,
1722 uint64_t Address,
1723 const void *Decoder) {
1724 if (RegNo > 31)
1725 return MCDisassembler::Fail;
1726
1727 unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo);
1728 Inst.addOperand(MCOperand::createReg(Reg));
1729 return MCDisassembler::Success;
1730}
1731
1732static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
1733 unsigned RegNo,
1734 uint64_t Address,
1735 const void *Decoder) {
1736 if (RegNo > 31)
1737 return MCDisassembler::Fail;
1738
1739 unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo);
1740 Inst.addOperand(MCOperand::createReg(Reg));
1741 return MCDisassembler::Success;
1742}
1743
1744static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
1745 unsigned RegNo,
1746 uint64_t Address,
1747 const void *Decoder) {
1748 if (RegNo > 31)
1749 return MCDisassembler::Fail;
1750
1751 unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo);
1752 Inst.addOperand(MCOperand::createReg(Reg));
1753 return MCDisassembler::Success;
1754}
1755
1756static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
1757 unsigned RegNo,
1758 uint64_t Address,
1759 const void *Decoder) {
1760 if (RegNo > 7)
1761 return MCDisassembler::Fail;
1762
1763 unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo);
1764 Inst.addOperand(MCOperand::createReg(Reg));
1765 return MCDisassembler::Success;
1766}
1767
1768static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst,
1769 unsigned RegNo,
1770 uint64_t Address,
1771 const void *Decoder) {
1772 if (RegNo > 31)
1773 return MCDisassembler::Fail;
1774
1775 unsigned Reg = getReg(Decoder, Mips::COP0RegClassID, RegNo);
1776 Inst.addOperand(MCOperand::createReg(Reg));
1777 return MCDisassembler::Success;
1778}
1779
1780static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
1781 unsigned RegNo,
1782 uint64_t Address,
1783 const void *Decoder) {
1784 if (RegNo > 31)
1785 return MCDisassembler::Fail;
1786
1787 unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo);
1788 Inst.addOperand(MCOperand::createReg(Reg));
1789 return MCDisassembler::Success;
1790}
1791
1792static DecodeStatus DecodeBranchTarget(MCInst &Inst,
1793 unsigned Offset,
1794 uint64_t Address,
1795 const void *Decoder) {
1796 int32_t BranchOffset = (SignExtend32<16>(Offset) * 4) + 4;
1797 Inst.addOperand(MCOperand::createImm(BranchOffset));
1798 return MCDisassembler::Success;
1799}
1800
1801static DecodeStatus DecodeJumpTarget(MCInst &Inst,
1802 unsigned Insn,
1803 uint64_t Address,
1804 const void *Decoder) {
1805
1806 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2;
1807 Inst.addOperand(MCOperand::createImm(JumpOffset));
1808 return MCDisassembler::Success;
1809}
1810
1811static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
1812 unsigned Offset,
1813 uint64_t Address,
1814 const void *Decoder) {
1815 int32_t BranchOffset = SignExtend32<21>(Offset) * 4;
1816
1817 Inst.addOperand(MCOperand::createImm(BranchOffset));
1818 return MCDisassembler::Success;
1819}
1820
1821static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
1822 unsigned Offset,
1823 uint64_t Address,
1824 const void *Decoder) {
1825 int32_t BranchOffset = SignExtend32<26>(Offset) * 4;
1826
1827 Inst.addOperand(MCOperand::createImm(BranchOffset));
1828 return MCDisassembler::Success;
1829}
1830
1831static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst,
1832 unsigned Offset,
1833 uint64_t Address,
1834 const void *Decoder) {
1835 int32_t BranchOffset = SignExtend32<7>(Offset) << 1;
1836 Inst.addOperand(MCOperand::createImm(BranchOffset));
1837 return MCDisassembler::Success;
1838}
1839
1840static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst,
1841 unsigned Offset,
1842 uint64_t Address,
1843 const void *Decoder) {
1844 int32_t BranchOffset = SignExtend32<10>(Offset) << 1;
1845 Inst.addOperand(MCOperand::createImm(BranchOffset));
1846 return MCDisassembler::Success;
1847}
1848
1849static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
1850 unsigned Offset,
1851 uint64_t Address,
1852 const void *Decoder) {
1853 int32_t BranchOffset = SignExtend32<16>(Offset) * 2;
1854 Inst.addOperand(MCOperand::createImm(BranchOffset));
1855 return MCDisassembler::Success;
1856}
1857
1858static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
1859 unsigned Insn,
1860 uint64_t Address,
1861 const void *Decoder) {
1862 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1;
1863 Inst.addOperand(MCOperand::createImm(JumpOffset));
1864 return MCDisassembler::Success;
1865}
1866
1867static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst,
1868 unsigned Value,
1869 uint64_t Address,
1870 const void *Decoder) {
1871 if (Value == 0)
1872 Inst.addOperand(MCOperand::createImm(1));
1873 else if (Value == 0x7)
1874 Inst.addOperand(MCOperand::createImm(-1));
1875 else
1876 Inst.addOperand(MCOperand::createImm(Value << 2));
1877 return MCDisassembler::Success;
1878}
1879
1880static DecodeStatus DecodeUImm6Lsl2(MCInst &Inst,
1881 unsigned Value,
1882 uint64_t Address,
1883 const void *Decoder) {
1884 Inst.addOperand(MCOperand::createImm(Value << 2));
1885 return MCDisassembler::Success;
1886}
1887
1888static DecodeStatus DecodeLiSimm7(MCInst &Inst,
1889 unsigned Value,
1890 uint64_t Address,
1891 const void *Decoder) {
1892 if (Value == 0x7F)
1893 Inst.addOperand(MCOperand::createImm(-1));
1894 else
1895 Inst.addOperand(MCOperand::createImm(Value));
1896 return MCDisassembler::Success;
1897}
1898
1899static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst,
1900 unsigned Value,
1901 uint64_t Address,
1902 const void *Decoder) {
1903 Inst.addOperand(MCOperand::createImm(Value == 0x0 ? 8 : Value));
1904 return MCDisassembler::Success;
1905}
1906
1907static DecodeStatus DecodeSimm4(MCInst &Inst,
1908 unsigned Value,
1909 uint64_t Address,
1910 const void *Decoder) {
1911 Inst.addOperand(MCOperand::createImm(SignExtend32<4>(Value)));
1912 return MCDisassembler::Success;
1913}
1914
1915static DecodeStatus DecodeSimm16(MCInst &Inst,
1916 unsigned Insn,
1917 uint64_t Address,
1918 const void *Decoder) {
1919 Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Insn)));
1920 return MCDisassembler::Success;
1921}
1922
1923template <unsigned Bits, int Offset>
1924static DecodeStatus DecodeUImmWithOffset(MCInst &Inst, unsigned Value,
1925 uint64_t Address,
1926 const void *Decoder) {
1927 Value &= ((1 << Bits) - 1);
1928 Inst.addOperand(MCOperand::createImm(Value + Offset));
1929 return MCDisassembler::Success;
1930}
1931
1932static DecodeStatus DecodeInsSize(MCInst &Inst,
1933 unsigned Insn,
1934 uint64_t Address,
1935 const void *Decoder) {
1936 // First we need to grab the pos(lsb) from MCInst.
1937 int Pos = Inst.getOperand(2).getImm();
1938 int Size = (int) Insn - Pos + 1;
1939 Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Size)));
1940 return MCDisassembler::Success;
1941}
1942
1943static DecodeStatus DecodeExtSize(MCInst &Inst,
1944 unsigned Insn,
1945 uint64_t Address,
1946 const void *Decoder) {
1947 int Size = (int) Insn + 1;
1948 Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Size)));
1949 return MCDisassembler::Success;
1950}
1951
1952static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
1953 uint64_t Address, const void *Decoder) {
1954 Inst.addOperand(MCOperand::createImm(SignExtend32<19>(Insn) * 4));
1955 return MCDisassembler::Success;
1956}
1957
1958static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
1959 uint64_t Address, const void *Decoder) {
1960 Inst.addOperand(MCOperand::createImm(SignExtend32<18>(Insn) * 8));
1961 return MCDisassembler::Success;
1962}
1963
1964static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn,
1965 uint64_t Address, const void *Decoder) {
1966 int32_t DecodedValue;
1967 switch (Insn) {
1968 case 0: DecodedValue = 256; break;
1969 case 1: DecodedValue = 257; break;
1970 case 510: DecodedValue = -258; break;
1971 case 511: DecodedValue = -257; break;
1972 default: DecodedValue = SignExtend32<9>(Insn); break;
1973 }
1974 Inst.addOperand(MCOperand::createImm(DecodedValue * 4));
1975 return MCDisassembler::Success;
1976}
1977
1978static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn,
1979 uint64_t Address, const void *Decoder) {
1980 // Insn must be >= 0, since it is unsigned that condition is always true.
1981 assert(Insn < 16)((Insn < 16) ? static_cast<void> (0) : __assert_fail
("Insn < 16", "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn253036/lib/Target/Mips/Disassembler/MipsDisassembler.cpp"
, 1981, __PRETTY_FUNCTION__));
1982 int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64,
1983 255, 32768, 65535};
1984 Inst.addOperand(MCOperand::createImm(DecodedValues[Insn]));
1985 return MCDisassembler::Success;
1986}
1987
1988static DecodeStatus DecodeUImm5lsl2(MCInst &Inst, unsigned Insn,
1989 uint64_t Address, const void *Decoder) {
1990 Inst.addOperand(MCOperand::createImm(Insn << 2));
1991 return MCDisassembler::Success;
1992}
1993
1994static DecodeStatus DecodeRegListOperand(MCInst &Inst,
1995 unsigned Insn,
1996 uint64_t Address,
1997 const void *Decoder) {
1998 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5,
1999 Mips::S6, Mips::S7, Mips::FP};
2000 unsigned RegNum;
2001
2002 unsigned RegLst = fieldFromInstruction(Insn, 21, 5);
2003
2004 // Empty register lists are not allowed.
2005 if (RegLst == 0)
2006 return MCDisassembler::Fail;
2007
2008 RegNum = RegLst & 0xf;
2009
2010 // RegLst values 10-15, and 26-31 are reserved.
2011 if (RegNum > 9)
2012 return MCDisassembler::Fail;
2013
2014 for (unsigned i = 0; i < RegNum; i++)
2015 Inst.addOperand(MCOperand::createReg(Regs[i]));
2016
2017 if (RegLst & 0x10)
2018 Inst.addOperand(MCOperand::createReg(Mips::RA));
2019
2020 return MCDisassembler::Success;
2021}
2022
2023static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn,
2024 uint64_t Address,
2025 const void *Decoder) {
2026 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3};
2027 unsigned RegLst;
2028 switch(Inst.getOpcode()) {
2029 default:
2030 RegLst = fieldFromInstruction(Insn, 4, 2);
2031 break;
2032 case Mips::LWM16_MMR6:
2033 case Mips::SWM16_MMR6:
2034 RegLst = fieldFromInstruction(Insn, 8, 2);
2035 break;
2036 }
2037 unsigned RegNum = RegLst & 0x3;
2038
2039 for (unsigned i = 0; i <= RegNum; i++)
2040 Inst.addOperand(MCOperand::createReg(Regs[i]));
2041
2042 Inst.addOperand(MCOperand::createReg(Mips::RA));
2043
2044 return MCDisassembler::Success;
2045}
2046
2047static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned Insn,
2048 uint64_t Address, const void *Decoder) {
2049
2050 unsigned RegPair = fieldFromInstruction(Insn, 7, 3);
2051
2052 switch (RegPair) {
2053 default:
2054 return MCDisassembler::Fail;
2055 case 0:
2056 Inst.addOperand(MCOperand::createReg(Mips::A1));
2057 Inst.addOperand(MCOperand::createReg(Mips::A2));
2058 break;
2059 case 1:
2060 Inst.addOperand(MCOperand::createReg(Mips::A1));
2061 Inst.addOperand(MCOperand::createReg(Mips::A3));
2062 break;
2063 case 2:
2064 Inst.addOperand(MCOperand::createReg(Mips::A2));
2065 Inst.addOperand(MCOperand::createReg(Mips::A3));
2066 break;
2067 case 3:
2068 Inst.addOperand(MCOperand::createReg(Mips::A0));
2069 Inst.addOperand(MCOperand::createReg(Mips::S5));
2070 break;
2071 case 4:
2072 Inst.addOperand(MCOperand::createReg(Mips::A0));
2073 Inst.addOperand(MCOperand::createReg(Mips::S6));
2074 break;
2075 case 5:
2076 Inst.addOperand(MCOperand::createReg(Mips::A0));
2077 Inst.addOperand(MCOperand::createReg(Mips::A1));
2078 break;
2079 case 6:
2080 Inst.addOperand(MCOperand::createReg(Mips::A0));
2081 Inst.addOperand(MCOperand::createReg(Mips::A2));
2082 break;
2083 case 7:
2084 Inst.addOperand(MCOperand::createReg(Mips::A0));
2085 Inst.addOperand(MCOperand::createReg(Mips::A3));
2086 break;
2087 }
2088
2089 return MCDisassembler::Success;
2090}
2091
2092static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn,
2093 uint64_t Address, const void *Decoder) {
2094 Inst.addOperand(MCOperand::createImm(SignExtend32<25>(Insn << 2)));
2095 return MCDisassembler::Success;
2096}