File: | lib/Target/Mips/Disassembler/MipsDisassembler.cpp |
Location: | line 841, column 14 |
Description: | Function call argument is an uninitialized value |
1 | //===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===// | |||
2 | // | |||
3 | // The LLVM Compiler Infrastructure | |||
4 | // | |||
5 | // This file is distributed under the University of Illinois Open Source | |||
6 | // License. See LICENSE.TXT for details. | |||
7 | // | |||
8 | //===----------------------------------------------------------------------===// | |||
9 | // | |||
10 | // This file is part of the Mips Disassembler. | |||
11 | // | |||
12 | //===----------------------------------------------------------------------===// | |||
13 | ||||
14 | #include "Mips.h" | |||
15 | #include "MipsRegisterInfo.h" | |||
16 | #include "MipsSubtarget.h" | |||
17 | #include "llvm/MC/MCContext.h" | |||
18 | #include "llvm/MC/MCDisassembler.h" | |||
19 | #include "llvm/MC/MCFixedLenDisassembler.h" | |||
20 | #include "llvm/MC/MCInst.h" | |||
21 | #include "llvm/MC/MCSubtargetInfo.h" | |||
22 | #include "llvm/Support/MathExtras.h" | |||
23 | #include "llvm/Support/TargetRegistry.h" | |||
24 | ||||
25 | using namespace llvm; | |||
26 | ||||
27 | #define DEBUG_TYPE"mips-disassembler" "mips-disassembler" | |||
28 | ||||
29 | typedef MCDisassembler::DecodeStatus DecodeStatus; | |||
30 | ||||
31 | namespace { | |||
32 | ||||
33 | class MipsDisassembler : public MCDisassembler { | |||
34 | bool IsMicroMips; | |||
35 | bool IsBigEndian; | |||
36 | public: | |||
37 | MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool IsBigEndian) | |||
38 | : MCDisassembler(STI, Ctx), | |||
39 | IsMicroMips(STI.getFeatureBits()[Mips::FeatureMicroMips]), | |||
40 | IsBigEndian(IsBigEndian) {} | |||
41 | ||||
42 | bool hasMips3() const { return STI.getFeatureBits()[Mips::FeatureMips3]; } | |||
43 | bool hasMips32() const { return STI.getFeatureBits()[Mips::FeatureMips32]; } | |||
44 | bool hasMips32r6() const { | |||
45 | return STI.getFeatureBits()[Mips::FeatureMips32r6]; | |||
46 | } | |||
47 | ||||
48 | bool isGP64() const { return STI.getFeatureBits()[Mips::FeatureGP64Bit]; } | |||
49 | ||||
50 | bool hasCnMips() const { return STI.getFeatureBits()[Mips::FeatureCnMips]; } | |||
51 | ||||
52 | bool hasCOP3() const { | |||
53 | // Only present in MIPS-I and MIPS-II | |||
54 | return !hasMips32() && !hasMips3(); | |||
55 | } | |||
56 | ||||
57 | DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, | |||
58 | ArrayRef<uint8_t> Bytes, uint64_t Address, | |||
59 | raw_ostream &VStream, | |||
60 | raw_ostream &CStream) const override; | |||
61 | }; | |||
62 | ||||
63 | } // end anonymous namespace | |||
64 | ||||
65 | // Forward declare these because the autogenerated code will reference them. | |||
66 | // Definitions are further down. | |||
67 | static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, | |||
68 | unsigned RegNo, | |||
69 | uint64_t Address, | |||
70 | const void *Decoder); | |||
71 | ||||
72 | static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, | |||
73 | unsigned RegNo, | |||
74 | uint64_t Address, | |||
75 | const void *Decoder); | |||
76 | ||||
77 | static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, | |||
78 | unsigned RegNo, | |||
79 | uint64_t Address, | |||
80 | const void *Decoder); | |||
81 | ||||
82 | static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, | |||
83 | unsigned RegNo, | |||
84 | uint64_t Address, | |||
85 | const void *Decoder); | |||
86 | ||||
87 | static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst, | |||
88 | unsigned RegNo, | |||
89 | uint64_t Address, | |||
90 | const void *Decoder); | |||
91 | ||||
92 | static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, | |||
93 | unsigned RegNo, | |||
94 | uint64_t Address, | |||
95 | const void *Decoder); | |||
96 | ||||
97 | static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, | |||
98 | unsigned Insn, | |||
99 | uint64_t Address, | |||
100 | const void *Decoder); | |||
101 | ||||
102 | static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, | |||
103 | unsigned RegNo, | |||
104 | uint64_t Address, | |||
105 | const void *Decoder); | |||
106 | ||||
107 | static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, | |||
108 | unsigned RegNo, | |||
109 | uint64_t Address, | |||
110 | const void *Decoder); | |||
111 | ||||
112 | static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, | |||
113 | unsigned RegNo, | |||
114 | uint64_t Address, | |||
115 | const void *Decoder); | |||
116 | ||||
117 | static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, | |||
118 | unsigned RegNo, | |||
119 | uint64_t Address, | |||
120 | const void *Decoder); | |||
121 | ||||
122 | static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, | |||
123 | unsigned RegNo, | |||
124 | uint64_t Address, | |||
125 | const void *Decoder); | |||
126 | ||||
127 | static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, | |||
128 | uint64_t Address, | |||
129 | const void *Decoder); | |||
130 | ||||
131 | static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, | |||
132 | unsigned Insn, | |||
133 | uint64_t Address, | |||
134 | const void *Decoder); | |||
135 | ||||
136 | static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, | |||
137 | unsigned RegNo, | |||
138 | uint64_t Address, | |||
139 | const void *Decoder); | |||
140 | ||||
141 | static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, | |||
142 | unsigned RegNo, | |||
143 | uint64_t Address, | |||
144 | const void *Decoder); | |||
145 | ||||
146 | static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, | |||
147 | unsigned RegNo, | |||
148 | uint64_t Address, | |||
149 | const void *Decoder); | |||
150 | ||||
151 | static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, | |||
152 | unsigned RegNo, | |||
153 | uint64_t Address, | |||
154 | const void *Decoder); | |||
155 | ||||
156 | static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, | |||
157 | unsigned RegNo, | |||
158 | uint64_t Address, | |||
159 | const void *Decoder); | |||
160 | ||||
161 | static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, | |||
162 | unsigned RegNo, | |||
163 | uint64_t Address, | |||
164 | const void *Decoder); | |||
165 | ||||
166 | static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, | |||
167 | unsigned RegNo, | |||
168 | uint64_t Address, | |||
169 | const void *Decoder); | |||
170 | ||||
171 | static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, | |||
172 | unsigned RegNo, | |||
173 | uint64_t Address, | |||
174 | const void *Decoder); | |||
175 | ||||
176 | static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, | |||
177 | unsigned RegNo, | |||
178 | uint64_t Address, | |||
179 | const void *Decoder); | |||
180 | ||||
181 | static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst, | |||
182 | unsigned RegNo, | |||
183 | uint64_t Address, | |||
184 | const void *Decoder); | |||
185 | ||||
186 | static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, | |||
187 | unsigned RegNo, | |||
188 | uint64_t Address, | |||
189 | const void *Decoder); | |||
190 | ||||
191 | static DecodeStatus DecodeBranchTarget(MCInst &Inst, | |||
192 | unsigned Offset, | |||
193 | uint64_t Address, | |||
194 | const void *Decoder); | |||
195 | ||||
196 | static DecodeStatus DecodeJumpTarget(MCInst &Inst, | |||
197 | unsigned Insn, | |||
198 | uint64_t Address, | |||
199 | const void *Decoder); | |||
200 | ||||
201 | static DecodeStatus DecodeBranchTarget21(MCInst &Inst, | |||
202 | unsigned Offset, | |||
203 | uint64_t Address, | |||
204 | const void *Decoder); | |||
205 | ||||
206 | static DecodeStatus DecodeBranchTarget26(MCInst &Inst, | |||
207 | unsigned Offset, | |||
208 | uint64_t Address, | |||
209 | const void *Decoder); | |||
210 | ||||
211 | // DecodeBranchTarget7MM - Decode microMIPS branch offset, which is | |||
212 | // shifted left by 1 bit. | |||
213 | static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, | |||
214 | unsigned Offset, | |||
215 | uint64_t Address, | |||
216 | const void *Decoder); | |||
217 | ||||
218 | // DecodeBranchTarget10MM - Decode microMIPS branch offset, which is | |||
219 | // shifted left by 1 bit. | |||
220 | static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, | |||
221 | unsigned Offset, | |||
222 | uint64_t Address, | |||
223 | const void *Decoder); | |||
224 | ||||
225 | // DecodeBranchTargetMM - Decode microMIPS branch offset, which is | |||
226 | // shifted left by 1 bit. | |||
227 | static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, | |||
228 | unsigned Offset, | |||
229 | uint64_t Address, | |||
230 | const void *Decoder); | |||
231 | ||||
232 | // DecodeJumpTargetMM - Decode microMIPS jump target, which is | |||
233 | // shifted left by 1 bit. | |||
234 | static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, | |||
235 | unsigned Insn, | |||
236 | uint64_t Address, | |||
237 | const void *Decoder); | |||
238 | ||||
239 | static DecodeStatus DecodeMem(MCInst &Inst, | |||
240 | unsigned Insn, | |||
241 | uint64_t Address, | |||
242 | const void *Decoder); | |||
243 | ||||
244 | static DecodeStatus DecodeCacheOp(MCInst &Inst, | |||
245 | unsigned Insn, | |||
246 | uint64_t Address, | |||
247 | const void *Decoder); | |||
248 | ||||
249 | static DecodeStatus DecodeCacheOpR6(MCInst &Inst, | |||
250 | unsigned Insn, | |||
251 | uint64_t Address, | |||
252 | const void *Decoder); | |||
253 | ||||
254 | static DecodeStatus DecodeCacheOpMM(MCInst &Inst, | |||
255 | unsigned Insn, | |||
256 | uint64_t Address, | |||
257 | const void *Decoder); | |||
258 | ||||
259 | static DecodeStatus DecodeSyncI(MCInst &Inst, | |||
260 | unsigned Insn, | |||
261 | uint64_t Address, | |||
262 | const void *Decoder); | |||
263 | ||||
264 | static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, | |||
265 | uint64_t Address, const void *Decoder); | |||
266 | ||||
267 | static DecodeStatus DecodeMemMMImm4(MCInst &Inst, | |||
268 | unsigned Insn, | |||
269 | uint64_t Address, | |||
270 | const void *Decoder); | |||
271 | ||||
272 | static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, | |||
273 | unsigned Insn, | |||
274 | uint64_t Address, | |||
275 | const void *Decoder); | |||
276 | ||||
277 | static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst, | |||
278 | unsigned Insn, | |||
279 | uint64_t Address, | |||
280 | const void *Decoder); | |||
281 | ||||
282 | static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst, | |||
283 | unsigned Insn, | |||
284 | uint64_t Address, | |||
285 | const void *Decoder); | |||
286 | ||||
287 | static DecodeStatus DecodeMemMMImm9(MCInst &Inst, | |||
288 | unsigned Insn, | |||
289 | uint64_t Address, | |||
290 | const void *Decoder); | |||
291 | ||||
292 | static DecodeStatus DecodeMemMMImm12(MCInst &Inst, | |||
293 | unsigned Insn, | |||
294 | uint64_t Address, | |||
295 | const void *Decoder); | |||
296 | ||||
297 | static DecodeStatus DecodeMemMMImm16(MCInst &Inst, | |||
298 | unsigned Insn, | |||
299 | uint64_t Address, | |||
300 | const void *Decoder); | |||
301 | ||||
302 | static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn, | |||
303 | uint64_t Address, | |||
304 | const void *Decoder); | |||
305 | ||||
306 | static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn, | |||
307 | uint64_t Address, | |||
308 | const void *Decoder); | |||
309 | ||||
310 | static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn, | |||
311 | uint64_t Address, | |||
312 | const void *Decoder); | |||
313 | ||||
314 | static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, unsigned Insn, | |||
315 | uint64_t Address, | |||
316 | const void *Decoder); | |||
317 | ||||
318 | static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, | |||
319 | unsigned Insn, | |||
320 | uint64_t Address, | |||
321 | const void *Decoder); | |||
322 | ||||
323 | static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, | |||
324 | unsigned Value, | |||
325 | uint64_t Address, | |||
326 | const void *Decoder); | |||
327 | ||||
328 | static DecodeStatus DecodeUImm6Lsl2(MCInst &Inst, | |||
329 | unsigned Value, | |||
330 | uint64_t Address, | |||
331 | const void *Decoder); | |||
332 | ||||
333 | static DecodeStatus DecodeLiSimm7(MCInst &Inst, | |||
334 | unsigned Value, | |||
335 | uint64_t Address, | |||
336 | const void *Decoder); | |||
337 | ||||
338 | static DecodeStatus DecodeSimm4(MCInst &Inst, | |||
339 | unsigned Value, | |||
340 | uint64_t Address, | |||
341 | const void *Decoder); | |||
342 | ||||
343 | static DecodeStatus DecodeSimm16(MCInst &Inst, | |||
344 | unsigned Insn, | |||
345 | uint64_t Address, | |||
346 | const void *Decoder); | |||
347 | ||||
348 | // Decode the immediate field of an LSA instruction which | |||
349 | // is off by one. | |||
350 | static DecodeStatus DecodeLSAImm(MCInst &Inst, | |||
351 | unsigned Insn, | |||
352 | uint64_t Address, | |||
353 | const void *Decoder); | |||
354 | ||||
355 | static DecodeStatus DecodeInsSize(MCInst &Inst, | |||
356 | unsigned Insn, | |||
357 | uint64_t Address, | |||
358 | const void *Decoder); | |||
359 | ||||
360 | static DecodeStatus DecodeExtSize(MCInst &Inst, | |||
361 | unsigned Insn, | |||
362 | uint64_t Address, | |||
363 | const void *Decoder); | |||
364 | ||||
365 | static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, | |||
366 | uint64_t Address, const void *Decoder); | |||
367 | ||||
368 | static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, | |||
369 | uint64_t Address, const void *Decoder); | |||
370 | ||||
371 | static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, | |||
372 | uint64_t Address, const void *Decoder); | |||
373 | ||||
374 | static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn, | |||
375 | uint64_t Address, const void *Decoder); | |||
376 | ||||
377 | static DecodeStatus DecodeUImm5lsl2(MCInst &Inst, unsigned Insn, | |||
378 | uint64_t Address, const void *Decoder); | |||
379 | ||||
380 | static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn, | |||
381 | uint64_t Address, const void *Decoder); | |||
382 | ||||
383 | /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't | |||
384 | /// handle. | |||
385 | template <typename InsnType> | |||
386 | static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address, | |||
387 | const void *Decoder); | |||
388 | ||||
389 | template <typename InsnType> | |||
390 | static DecodeStatus | |||
391 | DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, | |||
392 | const void *Decoder); | |||
393 | ||||
394 | template <typename InsnType> | |||
395 | static DecodeStatus | |||
396 | DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, | |||
397 | const void *Decoder); | |||
398 | ||||
399 | template <typename InsnType> | |||
400 | static DecodeStatus | |||
401 | DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, | |||
402 | const void *Decoder); | |||
403 | ||||
404 | template <typename InsnType> | |||
405 | static DecodeStatus | |||
406 | DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, | |||
407 | const void *Decoder); | |||
408 | ||||
409 | template <typename InsnType> | |||
410 | static DecodeStatus | |||
411 | DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, | |||
412 | const void *Decoder); | |||
413 | ||||
414 | template <typename InsnType> | |||
415 | static DecodeStatus | |||
416 | DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, | |||
417 | const void *Decoder); | |||
418 | ||||
419 | static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn, | |||
420 | uint64_t Address, | |||
421 | const void *Decoder); | |||
422 | ||||
423 | static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn, | |||
424 | uint64_t Address, | |||
425 | const void *Decoder); | |||
426 | ||||
427 | static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned Insn, | |||
428 | uint64_t Address, | |||
429 | const void *Decoder); | |||
430 | ||||
431 | namespace llvm { | |||
432 | extern Target TheMipselTarget, TheMipsTarget, TheMips64Target, | |||
433 | TheMips64elTarget; | |||
434 | } | |||
435 | ||||
436 | static MCDisassembler *createMipsDisassembler( | |||
437 | const Target &T, | |||
438 | const MCSubtargetInfo &STI, | |||
439 | MCContext &Ctx) { | |||
440 | return new MipsDisassembler(STI, Ctx, true); | |||
441 | } | |||
442 | ||||
443 | static MCDisassembler *createMipselDisassembler( | |||
444 | const Target &T, | |||
445 | const MCSubtargetInfo &STI, | |||
446 | MCContext &Ctx) { | |||
447 | return new MipsDisassembler(STI, Ctx, false); | |||
448 | } | |||
449 | ||||
450 | extern "C" void LLVMInitializeMipsDisassembler() { | |||
451 | // Register the disassembler. | |||
452 | TargetRegistry::RegisterMCDisassembler(TheMipsTarget, | |||
453 | createMipsDisassembler); | |||
454 | TargetRegistry::RegisterMCDisassembler(TheMipselTarget, | |||
455 | createMipselDisassembler); | |||
456 | TargetRegistry::RegisterMCDisassembler(TheMips64Target, | |||
457 | createMipsDisassembler); | |||
458 | TargetRegistry::RegisterMCDisassembler(TheMips64elTarget, | |||
459 | createMipselDisassembler); | |||
460 | } | |||
461 | ||||
462 | #include "MipsGenDisassemblerTables.inc" | |||
463 | ||||
464 | static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) { | |||
465 | const MipsDisassembler *Dis = static_cast<const MipsDisassembler*>(D); | |||
466 | const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo(); | |||
467 | return *(RegInfo->getRegClass(RC).begin() + RegNo); | |||
468 | } | |||
469 | ||||
470 | template <typename InsnType> | |||
471 | static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address, | |||
472 | const void *Decoder) { | |||
473 | typedef DecodeStatus (*DecodeFN)(MCInst &, unsigned, uint64_t, const void *); | |||
474 | // The size of the n field depends on the element size | |||
475 | // The register class also depends on this. | |||
476 | InsnType tmp = fieldFromInstruction(insn, 17, 5); | |||
477 | unsigned NSize = 0; | |||
478 | DecodeFN RegDecoder = nullptr; | |||
479 | if ((tmp & 0x18) == 0x00) { // INSVE_B | |||
480 | NSize = 4; | |||
481 | RegDecoder = DecodeMSA128BRegisterClass; | |||
482 | } else if ((tmp & 0x1c) == 0x10) { // INSVE_H | |||
483 | NSize = 3; | |||
484 | RegDecoder = DecodeMSA128HRegisterClass; | |||
485 | } else if ((tmp & 0x1e) == 0x18) { // INSVE_W | |||
486 | NSize = 2; | |||
487 | RegDecoder = DecodeMSA128WRegisterClass; | |||
488 | } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D | |||
489 | NSize = 1; | |||
490 | RegDecoder = DecodeMSA128DRegisterClass; | |||
491 | } else | |||
492 | llvm_unreachable("Invalid encoding")::llvm::llvm_unreachable_internal("Invalid encoding", "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn246424/lib/Target/Mips/Disassembler/MipsDisassembler.cpp" , 492); | |||
493 | ||||
494 | assert(NSize != 0 && RegDecoder != nullptr)((NSize != 0 && RegDecoder != nullptr) ? static_cast< void> (0) : __assert_fail ("NSize != 0 && RegDecoder != nullptr" , "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn246424/lib/Target/Mips/Disassembler/MipsDisassembler.cpp" , 494, __PRETTY_FUNCTION__)); | |||
495 | ||||
496 | // $wd | |||
497 | tmp = fieldFromInstruction(insn, 6, 5); | |||
498 | if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) | |||
499 | return MCDisassembler::Fail; | |||
500 | // $wd_in | |||
501 | if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) | |||
502 | return MCDisassembler::Fail; | |||
503 | // $n | |||
504 | tmp = fieldFromInstruction(insn, 16, NSize); | |||
505 | MI.addOperand(MCOperand::createImm(tmp)); | |||
506 | // $ws | |||
507 | tmp = fieldFromInstruction(insn, 11, 5); | |||
508 | if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) | |||
509 | return MCDisassembler::Fail; | |||
510 | // $n2 | |||
511 | MI.addOperand(MCOperand::createImm(0)); | |||
512 | ||||
513 | return MCDisassembler::Success; | |||
514 | } | |||
515 | ||||
516 | template <typename InsnType> | |||
517 | static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn, | |||
518 | uint64_t Address, | |||
519 | const void *Decoder) { | |||
520 | // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled | |||
521 | // (otherwise we would have matched the ADDI instruction from the earlier | |||
522 | // ISA's instead). | |||
523 | // | |||
524 | // We have: | |||
525 | // 0b001000 sssss ttttt iiiiiiiiiiiiiiii | |||
526 | // BOVC if rs >= rt | |||
527 | // BEQZALC if rs == 0 && rt != 0 | |||
528 | // BEQC if rs < rt && rs != 0 | |||
529 | ||||
530 | InsnType Rs = fieldFromInstruction(insn, 21, 5); | |||
531 | InsnType Rt = fieldFromInstruction(insn, 16, 5); | |||
532 | InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; | |||
533 | bool HasRs = false; | |||
534 | ||||
535 | if (Rs >= Rt) { | |||
536 | MI.setOpcode(Mips::BOVC); | |||
537 | HasRs = true; | |||
538 | } else if (Rs != 0 && Rs < Rt) { | |||
539 | MI.setOpcode(Mips::BEQC); | |||
540 | HasRs = true; | |||
541 | } else | |||
542 | MI.setOpcode(Mips::BEQZALC); | |||
543 | ||||
544 | if (HasRs) | |||
545 | MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, | |||
546 | Rs))); | |||
547 | ||||
548 | MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, | |||
549 | Rt))); | |||
550 | MI.addOperand(MCOperand::createImm(Imm)); | |||
551 | ||||
552 | return MCDisassembler::Success; | |||
553 | } | |||
554 | ||||
555 | template <typename InsnType> | |||
556 | static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, | |||
557 | uint64_t Address, | |||
558 | const void *Decoder) { | |||
559 | // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled | |||
560 | // (otherwise we would have matched the ADDI instruction from the earlier | |||
561 | // ISA's instead). | |||
562 | // | |||
563 | // We have: | |||
564 | // 0b011000 sssss ttttt iiiiiiiiiiiiiiii | |||
565 | // BNVC if rs >= rt | |||
566 | // BNEZALC if rs == 0 && rt != 0 | |||
567 | // BNEC if rs < rt && rs != 0 | |||
568 | ||||
569 | InsnType Rs = fieldFromInstruction(insn, 21, 5); | |||
570 | InsnType Rt = fieldFromInstruction(insn, 16, 5); | |||
571 | InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; | |||
572 | bool HasRs = false; | |||
573 | ||||
574 | if (Rs >= Rt) { | |||
575 | MI.setOpcode(Mips::BNVC); | |||
576 | HasRs = true; | |||
577 | } else if (Rs != 0 && Rs < Rt) { | |||
578 | MI.setOpcode(Mips::BNEC); | |||
579 | HasRs = true; | |||
580 | } else | |||
581 | MI.setOpcode(Mips::BNEZALC); | |||
582 | ||||
583 | if (HasRs) | |||
584 | MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, | |||
585 | Rs))); | |||
586 | ||||
587 | MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, | |||
588 | Rt))); | |||
589 | MI.addOperand(MCOperand::createImm(Imm)); | |||
590 | ||||
591 | return MCDisassembler::Success; | |||
592 | } | |||
593 | ||||
594 | template <typename InsnType> | |||
595 | static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, | |||
596 | uint64_t Address, | |||
597 | const void *Decoder) { | |||
598 | // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled | |||
599 | // (otherwise we would have matched the BLEZL instruction from the earlier | |||
600 | // ISA's instead). | |||
601 | // | |||
602 | // We have: | |||
603 | // 0b010110 sssss ttttt iiiiiiiiiiiiiiii | |||
604 | // Invalid if rs == 0 | |||
605 | // BLEZC if rs == 0 && rt != 0 | |||
606 | // BGEZC if rs == rt && rt != 0 | |||
607 | // BGEC if rs != rt && rs != 0 && rt != 0 | |||
608 | ||||
609 | InsnType Rs = fieldFromInstruction(insn, 21, 5); | |||
610 | InsnType Rt = fieldFromInstruction(insn, 16, 5); | |||
611 | InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; | |||
612 | bool HasRs = false; | |||
613 | ||||
614 | if (Rt == 0) | |||
615 | return MCDisassembler::Fail; | |||
616 | else if (Rs == 0) | |||
617 | MI.setOpcode(Mips::BLEZC); | |||
618 | else if (Rs == Rt) | |||
619 | MI.setOpcode(Mips::BGEZC); | |||
620 | else { | |||
621 | HasRs = true; | |||
622 | MI.setOpcode(Mips::BGEC); | |||
623 | } | |||
624 | ||||
625 | if (HasRs) | |||
626 | MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, | |||
627 | Rs))); | |||
628 | ||||
629 | MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, | |||
630 | Rt))); | |||
631 | ||||
632 | MI.addOperand(MCOperand::createImm(Imm)); | |||
633 | ||||
634 | return MCDisassembler::Success; | |||
635 | } | |||
636 | ||||
637 | template <typename InsnType> | |||
638 | static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, | |||
639 | uint64_t Address, | |||
640 | const void *Decoder) { | |||
641 | // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled | |||
642 | // (otherwise we would have matched the BGTZL instruction from the earlier | |||
643 | // ISA's instead). | |||
644 | // | |||
645 | // We have: | |||
646 | // 0b010111 sssss ttttt iiiiiiiiiiiiiiii | |||
647 | // Invalid if rs == 0 | |||
648 | // BGTZC if rs == 0 && rt != 0 | |||
649 | // BLTZC if rs == rt && rt != 0 | |||
650 | // BLTC if rs != rt && rs != 0 && rt != 0 | |||
651 | ||||
652 | bool HasRs = false; | |||
653 | ||||
654 | InsnType Rs = fieldFromInstruction(insn, 21, 5); | |||
655 | InsnType Rt = fieldFromInstruction(insn, 16, 5); | |||
656 | InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; | |||
657 | ||||
658 | if (Rt == 0) | |||
659 | return MCDisassembler::Fail; | |||
660 | else if (Rs == 0) | |||
661 | MI.setOpcode(Mips::BGTZC); | |||
662 | else if (Rs == Rt) | |||
663 | MI.setOpcode(Mips::BLTZC); | |||
664 | else { | |||
665 | MI.setOpcode(Mips::BLTC); | |||
666 | HasRs = true; | |||
667 | } | |||
668 | ||||
669 | if (HasRs) | |||
670 | MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, | |||
671 | Rs))); | |||
672 | ||||
673 | MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, | |||
674 | Rt))); | |||
675 | ||||
676 | MI.addOperand(MCOperand::createImm(Imm)); | |||
677 | ||||
678 | return MCDisassembler::Success; | |||
679 | } | |||
680 | ||||
681 | template <typename InsnType> | |||
682 | static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, | |||
683 | uint64_t Address, | |||
684 | const void *Decoder) { | |||
685 | // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled | |||
686 | // (otherwise we would have matched the BGTZ instruction from the earlier | |||
687 | // ISA's instead). | |||
688 | // | |||
689 | // We have: | |||
690 | // 0b000111 sssss ttttt iiiiiiiiiiiiiiii | |||
691 | // BGTZ if rt == 0 | |||
692 | // BGTZALC if rs == 0 && rt != 0 | |||
693 | // BLTZALC if rs != 0 && rs == rt | |||
694 | // BLTUC if rs != 0 && rs != rt | |||
695 | ||||
696 | InsnType Rs = fieldFromInstruction(insn, 21, 5); | |||
697 | InsnType Rt = fieldFromInstruction(insn, 16, 5); | |||
698 | InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; | |||
699 | bool HasRs = false; | |||
700 | bool HasRt = false; | |||
701 | ||||
702 | if (Rt == 0) { | |||
703 | MI.setOpcode(Mips::BGTZ); | |||
704 | HasRs = true; | |||
705 | } else if (Rs == 0) { | |||
706 | MI.setOpcode(Mips::BGTZALC); | |||
707 | HasRt = true; | |||
708 | } else if (Rs == Rt) { | |||
709 | MI.setOpcode(Mips::BLTZALC); | |||
710 | HasRs = true; | |||
711 | } else { | |||
712 | MI.setOpcode(Mips::BLTUC); | |||
713 | HasRs = true; | |||
714 | HasRt = true; | |||
715 | } | |||
716 | ||||
717 | if (HasRs) | |||
718 | MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, | |||
719 | Rs))); | |||
720 | ||||
721 | if (HasRt) | |||
722 | MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, | |||
723 | Rt))); | |||
724 | ||||
725 | MI.addOperand(MCOperand::createImm(Imm)); | |||
726 | ||||
727 | return MCDisassembler::Success; | |||
728 | } | |||
729 | ||||
730 | template <typename InsnType> | |||
731 | static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn, | |||
732 | uint64_t Address, | |||
733 | const void *Decoder) { | |||
734 | // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled | |||
735 | // (otherwise we would have matched the BLEZL instruction from the earlier | |||
736 | // ISA's instead). | |||
737 | // | |||
738 | // We have: | |||
739 | // 0b000110 sssss ttttt iiiiiiiiiiiiiiii | |||
740 | // Invalid if rs == 0 | |||
741 | // BLEZALC if rs == 0 && rt != 0 | |||
742 | // BGEZALC if rs == rt && rt != 0 | |||
743 | // BGEUC if rs != rt && rs != 0 && rt != 0 | |||
744 | ||||
745 | InsnType Rs = fieldFromInstruction(insn, 21, 5); | |||
746 | InsnType Rt = fieldFromInstruction(insn, 16, 5); | |||
747 | InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; | |||
748 | bool HasRs = false; | |||
749 | ||||
750 | if (Rt == 0) | |||
751 | return MCDisassembler::Fail; | |||
752 | else if (Rs == 0) | |||
753 | MI.setOpcode(Mips::BLEZALC); | |||
754 | else if (Rs == Rt) | |||
755 | MI.setOpcode(Mips::BGEZALC); | |||
756 | else { | |||
757 | HasRs = true; | |||
758 | MI.setOpcode(Mips::BGEUC); | |||
759 | } | |||
760 | ||||
761 | if (HasRs) | |||
762 | MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, | |||
763 | Rs))); | |||
764 | MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, | |||
765 | Rt))); | |||
766 | ||||
767 | MI.addOperand(MCOperand::createImm(Imm)); | |||
768 | ||||
769 | return MCDisassembler::Success; | |||
770 | } | |||
771 | ||||
772 | /// Read two bytes from the ArrayRef and return 16 bit halfword sorted | |||
773 | /// according to the given endianess. | |||
774 | static DecodeStatus readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address, | |||
775 | uint64_t &Size, uint32_t &Insn, | |||
776 | bool IsBigEndian) { | |||
777 | // We want to read exactly 2 Bytes of data. | |||
778 | if (Bytes.size() < 2) { | |||
779 | Size = 0; | |||
780 | return MCDisassembler::Fail; | |||
781 | } | |||
782 | ||||
783 | if (IsBigEndian) { | |||
784 | Insn = (Bytes[0] << 8) | Bytes[1]; | |||
785 | } else { | |||
786 | Insn = (Bytes[1] << 8) | Bytes[0]; | |||
787 | } | |||
788 | ||||
789 | return MCDisassembler::Success; | |||
790 | } | |||
791 | ||||
792 | /// Read four bytes from the ArrayRef and return 32 bit word sorted | |||
793 | /// according to the given endianess | |||
794 | static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address, | |||
795 | uint64_t &Size, uint32_t &Insn, | |||
796 | bool IsBigEndian, bool IsMicroMips) { | |||
797 | // We want to read exactly 4 Bytes of data. | |||
798 | if (Bytes.size() < 4) { | |||
799 | Size = 0; | |||
800 | return MCDisassembler::Fail; | |||
801 | } | |||
802 | ||||
803 | // High 16 bits of a 32-bit microMIPS instruction (where the opcode is) | |||
804 | // always precede the low 16 bits in the instruction stream (that is, they | |||
805 | // are placed at lower addresses in the instruction stream). | |||
806 | // | |||
807 | // microMIPS byte ordering: | |||
808 | // Big-endian: 0 | 1 | 2 | 3 | |||
809 | // Little-endian: 1 | 0 | 3 | 2 | |||
810 | ||||
811 | if (IsBigEndian) { | |||
812 | // Encoded as a big-endian 32-bit word in the stream. | |||
813 | Insn = | |||
814 | (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | (Bytes[0] << 24); | |||
815 | } else { | |||
816 | if (IsMicroMips) { | |||
817 | Insn = (Bytes[2] << 0) | (Bytes[3] << 8) | (Bytes[0] << 16) | | |||
818 | (Bytes[1] << 24); | |||
819 | } else { | |||
820 | Insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) | | |||
821 | (Bytes[3] << 24); | |||
822 | } | |||
823 | } | |||
824 | ||||
825 | return MCDisassembler::Success; | |||
826 | } | |||
827 | ||||
828 | DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, | |||
829 | ArrayRef<uint8_t> Bytes, | |||
830 | uint64_t Address, | |||
831 | raw_ostream &VStream, | |||
832 | raw_ostream &CStream) const { | |||
833 | uint32_t Insn; | |||
| ||||
834 | DecodeStatus Result; | |||
835 | ||||
836 | if (IsMicroMips) { | |||
837 | Result = readInstruction16(Bytes, Address, Size, Insn, IsBigEndian); | |||
838 | ||||
839 | DEBUG(dbgs() << "Trying MicroMips16 table (16-bit instructions):\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("mips-disassembler")) { dbgs() << "Trying MicroMips16 table (16-bit instructions):\n" ; } } while (0); | |||
840 | // Calling the auto-generated decoder function. | |||
841 | Result = decodeInstruction(DecoderTableMicroMips16, Instr, Insn, Address, | |||
| ||||
842 | this, STI); | |||
843 | if (Result != MCDisassembler::Fail) { | |||
844 | Size = 2; | |||
845 | return Result; | |||
846 | } | |||
847 | ||||
848 | Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, true); | |||
849 | if (Result == MCDisassembler::Fail) | |||
850 | return MCDisassembler::Fail; | |||
851 | ||||
852 | if (hasMips32r6()) { | |||
853 | DEBUG(dbgs() << "Trying MicroMips32r632 table (32-bit instructions):\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("mips-disassembler")) { dbgs() << "Trying MicroMips32r632 table (32-bit instructions):\n" ; } } while (0); | |||
854 | // Calling the auto-generated decoder function. | |||
855 | Result = decodeInstruction(DecoderTableMicroMipsR632, Instr, Insn, Address, | |||
856 | this, STI); | |||
857 | } else { | |||
858 | DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("mips-disassembler")) { dbgs() << "Trying MicroMips32 table (32-bit instructions):\n" ; } } while (0); | |||
859 | // Calling the auto-generated decoder function. | |||
860 | Result = decodeInstruction(DecoderTableMicroMips32, Instr, Insn, Address, | |||
861 | this, STI); | |||
862 | } | |||
863 | ||||
864 | if (Result != MCDisassembler::Fail) { | |||
865 | Size = 4; | |||
866 | return Result; | |||
867 | } | |||
868 | return MCDisassembler::Fail; | |||
869 | } | |||
870 | ||||
871 | Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false); | |||
872 | if (Result == MCDisassembler::Fail) | |||
873 | return MCDisassembler::Fail; | |||
874 | ||||
875 | if (hasCOP3()) { | |||
876 | DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("mips-disassembler")) { dbgs() << "Trying COP3_ table (32-bit opcodes):\n" ; } } while (0); | |||
877 | Result = | |||
878 | decodeInstruction(DecoderTableCOP3_32, Instr, Insn, Address, this, STI); | |||
879 | if (Result != MCDisassembler::Fail) { | |||
880 | Size = 4; | |||
881 | return Result; | |||
882 | } | |||
883 | } | |||
884 | ||||
885 | if (hasMips32r6() && isGP64()) { | |||
886 | DEBUG(dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("mips-disassembler")) { dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n" ; } } while (0); | |||
887 | Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, Instr, Insn, | |||
888 | Address, this, STI); | |||
889 | if (Result != MCDisassembler::Fail) { | |||
890 | Size = 4; | |||
891 | return Result; | |||
892 | } | |||
893 | } | |||
894 | ||||
895 | if (hasMips32r6()) { | |||
896 | DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("mips-disassembler")) { dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n" ; } } while (0); | |||
897 | Result = decodeInstruction(DecoderTableMips32r6_64r632, Instr, Insn, | |||
898 | Address, this, STI); | |||
899 | if (Result != MCDisassembler::Fail) { | |||
900 | Size = 4; | |||
901 | return Result; | |||
902 | } | |||
903 | } | |||
904 | ||||
905 | if (hasCnMips()) { | |||
906 | DEBUG(dbgs() << "Trying CnMips table (32-bit opcodes):\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("mips-disassembler")) { dbgs() << "Trying CnMips table (32-bit opcodes):\n" ; } } while (0); | |||
907 | Result = decodeInstruction(DecoderTableCnMips32, Instr, Insn, | |||
908 | Address, this, STI); | |||
909 | if (Result != MCDisassembler::Fail) { | |||
910 | Size = 4; | |||
911 | return Result; | |||
912 | } | |||
913 | } | |||
914 | ||||
915 | if (isGP64()) { | |||
916 | DEBUG(dbgs() << "Trying Mips64 (GPR64) table (32-bit opcodes):\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("mips-disassembler")) { dbgs() << "Trying Mips64 (GPR64) table (32-bit opcodes):\n" ; } } while (0); | |||
917 | Result = decodeInstruction(DecoderTableMips6432, Instr, Insn, | |||
918 | Address, this, STI); | |||
919 | if (Result != MCDisassembler::Fail) { | |||
920 | Size = 4; | |||
921 | return Result; | |||
922 | } | |||
923 | } | |||
924 | ||||
925 | DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("mips-disassembler")) { dbgs() << "Trying Mips table (32-bit opcodes):\n" ; } } while (0); | |||
926 | // Calling the auto-generated decoder function. | |||
927 | Result = | |||
928 | decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI); | |||
929 | if (Result != MCDisassembler::Fail) { | |||
930 | Size = 4; | |||
931 | return Result; | |||
932 | } | |||
933 | ||||
934 | return MCDisassembler::Fail; | |||
935 | } | |||
936 | ||||
937 | static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, | |||
938 | unsigned RegNo, | |||
939 | uint64_t Address, | |||
940 | const void *Decoder) { | |||
941 | ||||
942 | return MCDisassembler::Fail; | |||
943 | ||||
944 | } | |||
945 | ||||
946 | static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, | |||
947 | unsigned RegNo, | |||
948 | uint64_t Address, | |||
949 | const void *Decoder) { | |||
950 | ||||
951 | if (RegNo > 31) | |||
952 | return MCDisassembler::Fail; | |||
953 | ||||
954 | unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo); | |||
955 | Inst.addOperand(MCOperand::createReg(Reg)); | |||
956 | return MCDisassembler::Success; | |||
957 | } | |||
958 | ||||
959 | static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, | |||
960 | unsigned RegNo, | |||
961 | uint64_t Address, | |||
962 | const void *Decoder) { | |||
963 | if (RegNo > 7) | |||
964 | return MCDisassembler::Fail; | |||
965 | unsigned Reg = getReg(Decoder, Mips::GPRMM16RegClassID, RegNo); | |||
966 | Inst.addOperand(MCOperand::createReg(Reg)); | |||
967 | return MCDisassembler::Success; | |||
968 | } | |||
969 | ||||
970 | static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, | |||
971 | unsigned RegNo, | |||
972 | uint64_t Address, | |||
973 | const void *Decoder) { | |||
974 | if (RegNo > 7) | |||
975 | return MCDisassembler::Fail; | |||
976 | unsigned Reg = getReg(Decoder, Mips::GPRMM16ZeroRegClassID, RegNo); | |||
977 | Inst.addOperand(MCOperand::createReg(Reg)); | |||
978 | return MCDisassembler::Success; | |||
979 | } | |||
980 | ||||
981 | static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst, | |||
982 | unsigned RegNo, | |||
983 | uint64_t Address, | |||
984 | const void *Decoder) { | |||
985 | if (RegNo > 7) | |||
986 | return MCDisassembler::Fail; | |||
987 | unsigned Reg = getReg(Decoder, Mips::GPRMM16MovePRegClassID, RegNo); | |||
988 | Inst.addOperand(MCOperand::createReg(Reg)); | |||
989 | return MCDisassembler::Success; | |||
990 | } | |||
991 | ||||
992 | static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, | |||
993 | unsigned RegNo, | |||
994 | uint64_t Address, | |||
995 | const void *Decoder) { | |||
996 | if (RegNo > 31) | |||
997 | return MCDisassembler::Fail; | |||
998 | unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo); | |||
999 | Inst.addOperand(MCOperand::createReg(Reg)); | |||
1000 | return MCDisassembler::Success; | |||
1001 | } | |||
1002 | ||||
1003 | static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, | |||
1004 | unsigned RegNo, | |||
1005 | uint64_t Address, | |||
1006 | const void *Decoder) { | |||
1007 | if (static_cast<const MipsDisassembler *>(Decoder)->isGP64()) | |||
1008 | return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder); | |||
1009 | ||||
1010 | return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); | |||
1011 | } | |||
1012 | ||||
1013 | static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, | |||
1014 | unsigned RegNo, | |||
1015 | uint64_t Address, | |||
1016 | const void *Decoder) { | |||
1017 | return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); | |||
1018 | } | |||
1019 | ||||
1020 | static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, | |||
1021 | unsigned RegNo, | |||
1022 | uint64_t Address, | |||
1023 | const void *Decoder) { | |||
1024 | if (RegNo > 31) | |||
1025 | return MCDisassembler::Fail; | |||
1026 | ||||
1027 | unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo); | |||
1028 | Inst.addOperand(MCOperand::createReg(Reg)); | |||
1029 | return MCDisassembler::Success; | |||
1030 | } | |||
1031 | ||||
1032 | static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, | |||
1033 | unsigned RegNo, | |||
1034 | uint64_t Address, | |||
1035 | const void *Decoder) { | |||
1036 | if (RegNo > 31) | |||
1037 | return MCDisassembler::Fail; | |||
1038 | ||||
1039 | unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo); | |||
1040 | Inst.addOperand(MCOperand::createReg(Reg)); | |||
1041 | return MCDisassembler::Success; | |||
1042 | } | |||
1043 | ||||
1044 | static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, | |||
1045 | unsigned RegNo, | |||
1046 | uint64_t Address, | |||
1047 | const void *Decoder) { | |||
1048 | if (RegNo > 31) | |||
1049 | return MCDisassembler::Fail; | |||
1050 | unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo); | |||
1051 | Inst.addOperand(MCOperand::createReg(Reg)); | |||
1052 | return MCDisassembler::Success; | |||
1053 | } | |||
1054 | ||||
1055 | static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, | |||
1056 | unsigned RegNo, | |||
1057 | uint64_t Address, | |||
1058 | const void *Decoder) { | |||
1059 | if (RegNo > 7) | |||
1060 | return MCDisassembler::Fail; | |||
1061 | unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo); | |||
1062 | Inst.addOperand(MCOperand::createReg(Reg)); | |||
1063 | return MCDisassembler::Success; | |||
1064 | } | |||
1065 | ||||
1066 | static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, | |||
1067 | uint64_t Address, | |||
1068 | const void *Decoder) { | |||
1069 | if (RegNo > 31) | |||
1070 | return MCDisassembler::Fail; | |||
1071 | ||||
1072 | unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo); | |||
1073 | Inst.addOperand(MCOperand::createReg(Reg)); | |||
1074 | return MCDisassembler::Success; | |||
1075 | } | |||
1076 | ||||
1077 | static DecodeStatus DecodeMem(MCInst &Inst, | |||
1078 | unsigned Insn, | |||
1079 | uint64_t Address, | |||
1080 | const void *Decoder) { | |||
1081 | int Offset = SignExtend32<16>(Insn & 0xffff); | |||
1082 | unsigned Reg = fieldFromInstruction(Insn, 16, 5); | |||
1083 | unsigned Base = fieldFromInstruction(Insn, 21, 5); | |||
1084 | ||||
1085 | Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); | |||
1086 | Base = getReg(Decoder, Mips::GPR32RegClassID, Base); | |||
1087 | ||||
1088 | if(Inst.getOpcode() == Mips::SC || | |||
1089 | Inst.getOpcode() == Mips::SCD){ | |||
1090 | Inst.addOperand(MCOperand::createReg(Reg)); | |||
1091 | } | |||
1092 | ||||
1093 | Inst.addOperand(MCOperand::createReg(Reg)); | |||
1094 | Inst.addOperand(MCOperand::createReg(Base)); | |||
1095 | Inst.addOperand(MCOperand::createImm(Offset)); | |||
1096 | ||||
1097 | return MCDisassembler::Success; | |||
1098 | } | |||
1099 | ||||
1100 | static DecodeStatus DecodeCacheOp(MCInst &Inst, | |||
1101 | unsigned Insn, | |||
1102 | uint64_t Address, | |||
1103 | const void *Decoder) { | |||
1104 | int Offset = SignExtend32<16>(Insn & 0xffff); | |||
1105 | unsigned Hint = fieldFromInstruction(Insn, 16, 5); | |||
1106 | unsigned Base = fieldFromInstruction(Insn, 21, 5); | |||
1107 | ||||
1108 | Base = getReg(Decoder, Mips::GPR32RegClassID, Base); | |||
1109 | ||||
1110 | Inst.addOperand(MCOperand::createReg(Base)); | |||
1111 | Inst.addOperand(MCOperand::createImm(Offset)); | |||
1112 | Inst.addOperand(MCOperand::createImm(Hint)); | |||
1113 | ||||
1114 | return MCDisassembler::Success; | |||
1115 | } | |||
1116 | ||||
1117 | static DecodeStatus DecodeCacheOpMM(MCInst &Inst, | |||
1118 | unsigned Insn, | |||
1119 | uint64_t Address, | |||
1120 | const void *Decoder) { | |||
1121 | int Offset = SignExtend32<12>(Insn & 0xfff); | |||
1122 | unsigned Base = fieldFromInstruction(Insn, 16, 5); | |||
1123 | unsigned Hint = fieldFromInstruction(Insn, 21, 5); | |||
1124 | ||||
1125 | Base = getReg(Decoder, Mips::GPR32RegClassID, Base); | |||
1126 | ||||
1127 | Inst.addOperand(MCOperand::createReg(Base)); | |||
1128 | Inst.addOperand(MCOperand::createImm(Offset)); | |||
1129 | Inst.addOperand(MCOperand::createImm(Hint)); | |||
1130 | ||||
1131 | return MCDisassembler::Success; | |||
1132 | } | |||
1133 | ||||
1134 | static DecodeStatus DecodeCacheOpR6(MCInst &Inst, | |||
1135 | unsigned Insn, | |||
1136 | uint64_t Address, | |||
1137 | const void *Decoder) { | |||
1138 | int Offset = fieldFromInstruction(Insn, 7, 9); | |||
1139 | unsigned Hint = fieldFromInstruction(Insn, 16, 5); | |||
1140 | unsigned Base = fieldFromInstruction(Insn, 21, 5); | |||
1141 | ||||
1142 | Base = getReg(Decoder, Mips::GPR32RegClassID, Base); | |||
1143 | ||||
1144 | Inst.addOperand(MCOperand::createReg(Base)); | |||
1145 | Inst.addOperand(MCOperand::createImm(Offset)); | |||
1146 | Inst.addOperand(MCOperand::createImm(Hint)); | |||
1147 | ||||
1148 | return MCDisassembler::Success; | |||
1149 | } | |||
1150 | ||||
1151 | static DecodeStatus DecodeSyncI(MCInst &Inst, | |||
1152 | unsigned Insn, | |||
1153 | uint64_t Address, | |||
1154 | const void *Decoder) { | |||
1155 | int Offset = SignExtend32<16>(Insn & 0xffff); | |||
1156 | unsigned Base = fieldFromInstruction(Insn, 21, 5); | |||
1157 | ||||
1158 | Base = getReg(Decoder, Mips::GPR32RegClassID, Base); | |||
1159 | ||||
1160 | Inst.addOperand(MCOperand::createReg(Base)); | |||
1161 | Inst.addOperand(MCOperand::createImm(Offset)); | |||
1162 | ||||
1163 | return MCDisassembler::Success; | |||
1164 | } | |||
1165 | ||||
1166 | static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, | |||
1167 | uint64_t Address, const void *Decoder) { | |||
1168 | int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10)); | |||
1169 | unsigned Reg = fieldFromInstruction(Insn, 6, 5); | |||
1170 | unsigned Base = fieldFromInstruction(Insn, 11, 5); | |||
1171 | ||||
1172 | Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg); | |||
1173 | Base = getReg(Decoder, Mips::GPR32RegClassID, Base); | |||
1174 | ||||
1175 | Inst.addOperand(MCOperand::createReg(Reg)); | |||
1176 | Inst.addOperand(MCOperand::createReg(Base)); | |||
1177 | ||||
1178 | // The immediate field of an LD/ST instruction is scaled which means it must | |||
1179 | // be multiplied (when decoding) by the size (in bytes) of the instructions' | |||
1180 | // data format. | |||
1181 | // .b - 1 byte | |||
1182 | // .h - 2 bytes | |||
1183 | // .w - 4 bytes | |||
1184 | // .d - 8 bytes | |||
1185 | switch(Inst.getOpcode()) | |||
1186 | { | |||
1187 | default: | |||
1188 | assert (0 && "Unexpected instruction")((0 && "Unexpected instruction") ? static_cast<void > (0) : __assert_fail ("0 && \"Unexpected instruction\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn246424/lib/Target/Mips/Disassembler/MipsDisassembler.cpp" , 1188, __PRETTY_FUNCTION__)); | |||
1189 | return MCDisassembler::Fail; | |||
1190 | break; | |||
1191 | case Mips::LD_B: | |||
1192 | case Mips::ST_B: | |||
1193 | Inst.addOperand(MCOperand::createImm(Offset)); | |||
1194 | break; | |||
1195 | case Mips::LD_H: | |||
1196 | case Mips::ST_H: | |||
1197 | Inst.addOperand(MCOperand::createImm(Offset * 2)); | |||
1198 | break; | |||
1199 | case Mips::LD_W: | |||
1200 | case Mips::ST_W: | |||
1201 | Inst.addOperand(MCOperand::createImm(Offset * 4)); | |||
1202 | break; | |||
1203 | case Mips::LD_D: | |||
1204 | case Mips::ST_D: | |||
1205 | Inst.addOperand(MCOperand::createImm(Offset * 8)); | |||
1206 | break; | |||
1207 | } | |||
1208 | ||||
1209 | return MCDisassembler::Success; | |||
1210 | } | |||
1211 | ||||
1212 | static DecodeStatus DecodeMemMMImm4(MCInst &Inst, | |||
1213 | unsigned Insn, | |||
1214 | uint64_t Address, | |||
1215 | const void *Decoder) { | |||
1216 | unsigned Offset = Insn & 0xf; | |||
1217 | unsigned Reg = fieldFromInstruction(Insn, 7, 3); | |||
1218 | unsigned Base = fieldFromInstruction(Insn, 4, 3); | |||
1219 | ||||
1220 | switch (Inst.getOpcode()) { | |||
1221 | case Mips::LBU16_MM: | |||
1222 | case Mips::LHU16_MM: | |||
1223 | case Mips::LW16_MM: | |||
1224 | if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder) | |||
1225 | == MCDisassembler::Fail) | |||
1226 | return MCDisassembler::Fail; | |||
1227 | break; | |||
1228 | case Mips::SB16_MM: | |||
1229 | case Mips::SH16_MM: | |||
1230 | case Mips::SW16_MM: | |||
1231 | if (DecodeGPRMM16ZeroRegisterClass(Inst, Reg, Address, Decoder) | |||
1232 | == MCDisassembler::Fail) | |||
1233 | return MCDisassembler::Fail; | |||
1234 | break; | |||
1235 | } | |||
1236 | ||||
1237 | if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder) | |||
1238 | == MCDisassembler::Fail) | |||
1239 | return MCDisassembler::Fail; | |||
1240 | ||||
1241 | switch (Inst.getOpcode()) { | |||
1242 | case Mips::LBU16_MM: | |||
1243 | if (Offset == 0xf) | |||
1244 | Inst.addOperand(MCOperand::createImm(-1)); | |||
1245 | else | |||
1246 | Inst.addOperand(MCOperand::createImm(Offset)); | |||
1247 | break; | |||
1248 | case Mips::SB16_MM: | |||
1249 | Inst.addOperand(MCOperand::createImm(Offset)); | |||
1250 | break; | |||
1251 | case Mips::LHU16_MM: | |||
1252 | case Mips::SH16_MM: | |||
1253 | Inst.addOperand(MCOperand::createImm(Offset << 1)); | |||
1254 | break; | |||
1255 | case Mips::LW16_MM: | |||
1256 | case Mips::SW16_MM: | |||
1257 | Inst.addOperand(MCOperand::createImm(Offset << 2)); | |||
1258 | break; | |||
1259 | } | |||
1260 | ||||
1261 | return MCDisassembler::Success; | |||
1262 | } | |||
1263 | ||||
1264 | static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, | |||
1265 | unsigned Insn, | |||
1266 | uint64_t Address, | |||
1267 | const void *Decoder) { | |||
1268 | unsigned Offset = Insn & 0x1F; | |||
1269 | unsigned Reg = fieldFromInstruction(Insn, 5, 5); | |||
1270 | ||||
1271 | Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); | |||
1272 | ||||
1273 | Inst.addOperand(MCOperand::createReg(Reg)); | |||
1274 | Inst.addOperand(MCOperand::createReg(Mips::SP)); | |||
1275 | Inst.addOperand(MCOperand::createImm(Offset << 2)); | |||
1276 | ||||
1277 | return MCDisassembler::Success; | |||
1278 | } | |||
1279 | ||||
1280 | static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst, | |||
1281 | unsigned Insn, | |||
1282 | uint64_t Address, | |||
1283 | const void *Decoder) { | |||
1284 | unsigned Offset = Insn & 0x7F; | |||
1285 | unsigned Reg = fieldFromInstruction(Insn, 7, 3); | |||
1286 | ||||
1287 | Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); | |||
1288 | ||||
1289 | Inst.addOperand(MCOperand::createReg(Reg)); | |||
1290 | Inst.addOperand(MCOperand::createReg(Mips::GP)); | |||
1291 | Inst.addOperand(MCOperand::createImm(Offset << 2)); | |||
1292 | ||||
1293 | return MCDisassembler::Success; | |||
1294 | } | |||
1295 | ||||
1296 | static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst, | |||
1297 | unsigned Insn, | |||
1298 | uint64_t Address, | |||
1299 | const void *Decoder) { | |||
1300 | int Offset = SignExtend32<4>(Insn & 0xf); | |||
1301 | ||||
1302 | if (DecodeRegListOperand16(Inst, Insn, Address, Decoder) | |||
1303 | == MCDisassembler::Fail) | |||
1304 | return MCDisassembler::Fail; | |||
1305 | ||||
1306 | Inst.addOperand(MCOperand::createReg(Mips::SP)); | |||
1307 | Inst.addOperand(MCOperand::createImm(Offset << 2)); | |||
1308 | ||||
1309 | return MCDisassembler::Success; | |||
1310 | } | |||
1311 | ||||
1312 | static DecodeStatus DecodeMemMMImm9(MCInst &Inst, | |||
1313 | unsigned Insn, | |||
1314 | uint64_t Address, | |||
1315 | const void *Decoder) { | |||
1316 | int Offset = SignExtend32<9>(Insn & 0x1ff); | |||
1317 | unsigned Reg = fieldFromInstruction(Insn, 21, 5); | |||
1318 | unsigned Base = fieldFromInstruction(Insn, 16, 5); | |||
1319 | ||||
1320 | Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); | |||
1321 | Base = getReg(Decoder, Mips::GPR32RegClassID, Base); | |||
1322 | ||||
1323 | Inst.addOperand(MCOperand::createReg(Reg)); | |||
1324 | Inst.addOperand(MCOperand::createReg(Base)); | |||
1325 | Inst.addOperand(MCOperand::createImm(Offset)); | |||
1326 | ||||
1327 | return MCDisassembler::Success; | |||
1328 | } | |||
1329 | ||||
1330 | static DecodeStatus DecodeMemMMImm12(MCInst &Inst, | |||
1331 | unsigned Insn, | |||
1332 | uint64_t Address, | |||
1333 | const void *Decoder) { | |||
1334 | int Offset = SignExtend32<12>(Insn & 0x0fff); | |||
1335 | unsigned Reg = fieldFromInstruction(Insn, 21, 5); | |||
1336 | unsigned Base = fieldFromInstruction(Insn, 16, 5); | |||
1337 | ||||
1338 | Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); | |||
1339 | Base = getReg(Decoder, Mips::GPR32RegClassID, Base); | |||
1340 | ||||
1341 | switch (Inst.getOpcode()) { | |||
1342 | case Mips::SWM32_MM: | |||
1343 | case Mips::LWM32_MM: | |||
1344 | if (DecodeRegListOperand(Inst, Insn, Address, Decoder) | |||
1345 | == MCDisassembler::Fail) | |||
1346 | return MCDisassembler::Fail; | |||
1347 | Inst.addOperand(MCOperand::createReg(Base)); | |||
1348 | Inst.addOperand(MCOperand::createImm(Offset)); | |||
1349 | break; | |||
1350 | case Mips::SC_MM: | |||
1351 | Inst.addOperand(MCOperand::createReg(Reg)); | |||
1352 | // fallthrough | |||
1353 | default: | |||
1354 | Inst.addOperand(MCOperand::createReg(Reg)); | |||
1355 | if (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM) | |||
1356 | Inst.addOperand(MCOperand::createReg(Reg+1)); | |||
1357 | ||||
1358 | Inst.addOperand(MCOperand::createReg(Base)); | |||
1359 | Inst.addOperand(MCOperand::createImm(Offset)); | |||
1360 | } | |||
1361 | ||||
1362 | return MCDisassembler::Success; | |||
1363 | } | |||
1364 | ||||
1365 | static DecodeStatus DecodeMemMMImm16(MCInst &Inst, | |||
1366 | unsigned Insn, | |||
1367 | uint64_t Address, | |||
1368 | const void *Decoder) { | |||
1369 | int Offset = SignExtend32<16>(Insn & 0xffff); | |||
1370 | unsigned Reg = fieldFromInstruction(Insn, 21, 5); | |||
1371 | unsigned Base = fieldFromInstruction(Insn, 16, 5); | |||
1372 | ||||
1373 | Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); | |||
1374 | Base = getReg(Decoder, Mips::GPR32RegClassID, Base); | |||
1375 | ||||
1376 | Inst.addOperand(MCOperand::createReg(Reg)); | |||
1377 | Inst.addOperand(MCOperand::createReg(Base)); | |||
1378 | Inst.addOperand(MCOperand::createImm(Offset)); | |||
1379 | ||||
1380 | return MCDisassembler::Success; | |||
1381 | } | |||
1382 | ||||
1383 | static DecodeStatus DecodeFMem(MCInst &Inst, | |||
1384 | unsigned Insn, | |||
1385 | uint64_t Address, | |||
1386 | const void *Decoder) { | |||
1387 | int Offset = SignExtend32<16>(Insn & 0xffff); | |||
1388 | unsigned Reg = fieldFromInstruction(Insn, 16, 5); | |||
1389 | unsigned Base = fieldFromInstruction(Insn, 21, 5); | |||
1390 | ||||
1391 | Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg); | |||
1392 | Base = getReg(Decoder, Mips::GPR32RegClassID, Base); | |||
1393 | ||||
1394 | Inst.addOperand(MCOperand::createReg(Reg)); | |||
1395 | Inst.addOperand(MCOperand::createReg(Base)); | |||
1396 | Inst.addOperand(MCOperand::createImm(Offset)); | |||
1397 | ||||
1398 | return MCDisassembler::Success; | |||
1399 | } | |||
1400 | ||||
1401 | static DecodeStatus DecodeFMem2(MCInst &Inst, | |||
1402 | unsigned Insn, | |||
1403 | uint64_t Address, | |||
1404 | const void *Decoder) { | |||
1405 | int Offset = SignExtend32<16>(Insn & 0xffff); | |||
1406 | unsigned Reg = fieldFromInstruction(Insn, 16, 5); | |||
1407 | unsigned Base = fieldFromInstruction(Insn, 21, 5); | |||
1408 | ||||
1409 | Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); | |||
1410 | Base = getReg(Decoder, Mips::GPR32RegClassID, Base); | |||
1411 | ||||
1412 | Inst.addOperand(MCOperand::createReg(Reg)); | |||
1413 | Inst.addOperand(MCOperand::createReg(Base)); | |||
1414 | Inst.addOperand(MCOperand::createImm(Offset)); | |||
1415 | ||||
1416 | return MCDisassembler::Success; | |||
1417 | } | |||
1418 | ||||
1419 | static DecodeStatus DecodeFMem3(MCInst &Inst, | |||
1420 | unsigned Insn, | |||
1421 | uint64_t Address, | |||
1422 | const void *Decoder) { | |||
1423 | int Offset = SignExtend32<16>(Insn & 0xffff); | |||
1424 | unsigned Reg = fieldFromInstruction(Insn, 16, 5); | |||
1425 | unsigned Base = fieldFromInstruction(Insn, 21, 5); | |||
1426 | ||||
1427 | Reg = getReg(Decoder, Mips::COP3RegClassID, Reg); | |||
1428 | Base = getReg(Decoder, Mips::GPR32RegClassID, Base); | |||
1429 | ||||
1430 | Inst.addOperand(MCOperand::createReg(Reg)); | |||
1431 | Inst.addOperand(MCOperand::createReg(Base)); | |||
1432 | Inst.addOperand(MCOperand::createImm(Offset)); | |||
1433 | ||||
1434 | return MCDisassembler::Success; | |||
1435 | } | |||
1436 | ||||
1437 | static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, | |||
1438 | unsigned Insn, | |||
1439 | uint64_t Address, | |||
1440 | const void *Decoder) { | |||
1441 | int Offset = SignExtend32<11>(Insn & 0x07ff); | |||
1442 | unsigned Reg = fieldFromInstruction(Insn, 16, 5); | |||
1443 | unsigned Base = fieldFromInstruction(Insn, 11, 5); | |||
1444 | ||||
1445 | Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); | |||
1446 | Base = getReg(Decoder, Mips::GPR32RegClassID, Base); | |||
1447 | ||||
1448 | Inst.addOperand(MCOperand::createReg(Reg)); | |||
1449 | Inst.addOperand(MCOperand::createReg(Base)); | |||
1450 | Inst.addOperand(MCOperand::createImm(Offset)); | |||
1451 | ||||
1452 | return MCDisassembler::Success; | |||
1453 | } | |||
1454 | static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, | |||
1455 | unsigned Insn, | |||
1456 | uint64_t Address, | |||
1457 | const void *Decoder) { | |||
1458 | int64_t Offset = SignExtend64<9>((Insn >> 7) & 0x1ff); | |||
1459 | unsigned Rt = fieldFromInstruction(Insn, 16, 5); | |||
1460 | unsigned Base = fieldFromInstruction(Insn, 21, 5); | |||
1461 | ||||
1462 | Rt = getReg(Decoder, Mips::GPR32RegClassID, Rt); | |||
1463 | Base = getReg(Decoder, Mips::GPR32RegClassID, Base); | |||
1464 | ||||
1465 | if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){ | |||
1466 | Inst.addOperand(MCOperand::createReg(Rt)); | |||
1467 | } | |||
1468 | ||||
1469 | Inst.addOperand(MCOperand::createReg(Rt)); | |||
1470 | Inst.addOperand(MCOperand::createReg(Base)); | |||
1471 | Inst.addOperand(MCOperand::createImm(Offset)); | |||
1472 | ||||
1473 | return MCDisassembler::Success; | |||
1474 | } | |||
1475 | ||||
1476 | static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, | |||
1477 | unsigned RegNo, | |||
1478 | uint64_t Address, | |||
1479 | const void *Decoder) { | |||
1480 | // Currently only hardware register 29 is supported. | |||
1481 | if (RegNo != 29) | |||
1482 | return MCDisassembler::Fail; | |||
1483 | Inst.addOperand(MCOperand::createReg(Mips::HWR29)); | |||
1484 | return MCDisassembler::Success; | |||
1485 | } | |||
1486 | ||||
1487 | static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, | |||
1488 | unsigned RegNo, | |||
1489 | uint64_t Address, | |||
1490 | const void *Decoder) { | |||
1491 | if (RegNo > 30 || RegNo %2) | |||
1492 | return MCDisassembler::Fail; | |||
1493 | ||||
1494 | ; | |||
1495 | unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2); | |||
1496 | Inst.addOperand(MCOperand::createReg(Reg)); | |||
1497 | return MCDisassembler::Success; | |||
1498 | } | |||
1499 | ||||
1500 | static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, | |||
1501 | unsigned RegNo, | |||
1502 | uint64_t Address, | |||
1503 | const void *Decoder) { | |||
1504 | if (RegNo >= 4) | |||
1505 | return MCDisassembler::Fail; | |||
1506 | ||||
1507 | unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo); | |||
1508 | Inst.addOperand(MCOperand::createReg(Reg)); | |||
1509 | return MCDisassembler::Success; | |||
1510 | } | |||
1511 | ||||
1512 | static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, | |||
1513 | unsigned RegNo, | |||
1514 | uint64_t Address, | |||
1515 | const void *Decoder) { | |||
1516 | if (RegNo >= 4) | |||
1517 | return MCDisassembler::Fail; | |||
1518 | ||||
1519 | unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo); | |||
1520 | Inst.addOperand(MCOperand::createReg(Reg)); | |||
1521 | return MCDisassembler::Success; | |||
1522 | } | |||
1523 | ||||
1524 | static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, | |||
1525 | unsigned RegNo, | |||
1526 | uint64_t Address, | |||
1527 | const void *Decoder) { | |||
1528 | if (RegNo >= 4) | |||
1529 | return MCDisassembler::Fail; | |||
1530 | ||||
1531 | unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo); | |||
1532 | Inst.addOperand(MCOperand::createReg(Reg)); | |||
1533 | return MCDisassembler::Success; | |||
1534 | } | |||
1535 | ||||
1536 | static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, | |||
1537 | unsigned RegNo, | |||
1538 | uint64_t Address, | |||
1539 | const void *Decoder) { | |||
1540 | if (RegNo > 31) | |||
1541 | return MCDisassembler::Fail; | |||
1542 | ||||
1543 | unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo); | |||
1544 | Inst.addOperand(MCOperand::createReg(Reg)); | |||
1545 | return MCDisassembler::Success; | |||
1546 | } | |||
1547 | ||||
1548 | static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, | |||
1549 | unsigned RegNo, | |||
1550 | uint64_t Address, | |||
1551 | const void *Decoder) { | |||
1552 | if (RegNo > 31) | |||
1553 | return MCDisassembler::Fail; | |||
1554 | ||||
1555 | unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo); | |||
1556 | Inst.addOperand(MCOperand::createReg(Reg)); | |||
1557 | return MCDisassembler::Success; | |||
1558 | } | |||
1559 | ||||
1560 | static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, | |||
1561 | unsigned RegNo, | |||
1562 | uint64_t Address, | |||
1563 | const void *Decoder) { | |||
1564 | if (RegNo > 31) | |||
1565 | return MCDisassembler::Fail; | |||
1566 | ||||
1567 | unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo); | |||
1568 | Inst.addOperand(MCOperand::createReg(Reg)); | |||
1569 | return MCDisassembler::Success; | |||
1570 | } | |||
1571 | ||||
1572 | static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, | |||
1573 | unsigned RegNo, | |||
1574 | uint64_t Address, | |||
1575 | const void *Decoder) { | |||
1576 | if (RegNo > 31) | |||
1577 | return MCDisassembler::Fail; | |||
1578 | ||||
1579 | unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo); | |||
1580 | Inst.addOperand(MCOperand::createReg(Reg)); | |||
1581 | return MCDisassembler::Success; | |||
1582 | } | |||
1583 | ||||
1584 | static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, | |||
1585 | unsigned RegNo, | |||
1586 | uint64_t Address, | |||
1587 | const void *Decoder) { | |||
1588 | if (RegNo > 7) | |||
1589 | return MCDisassembler::Fail; | |||
1590 | ||||
1591 | unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo); | |||
1592 | Inst.addOperand(MCOperand::createReg(Reg)); | |||
1593 | return MCDisassembler::Success; | |||
1594 | } | |||
1595 | ||||
1596 | static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst, | |||
1597 | unsigned RegNo, | |||
1598 | uint64_t Address, | |||
1599 | const void *Decoder) { | |||
1600 | if (RegNo > 31) | |||
1601 | return MCDisassembler::Fail; | |||
1602 | ||||
1603 | unsigned Reg = getReg(Decoder, Mips::COP0RegClassID, RegNo); | |||
1604 | Inst.addOperand(MCOperand::createReg(Reg)); | |||
1605 | return MCDisassembler::Success; | |||
1606 | } | |||
1607 | ||||
1608 | static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, | |||
1609 | unsigned RegNo, | |||
1610 | uint64_t Address, | |||
1611 | const void *Decoder) { | |||
1612 | if (RegNo > 31) | |||
1613 | return MCDisassembler::Fail; | |||
1614 | ||||
1615 | unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo); | |||
1616 | Inst.addOperand(MCOperand::createReg(Reg)); | |||
1617 | return MCDisassembler::Success; | |||
1618 | } | |||
1619 | ||||
1620 | static DecodeStatus DecodeBranchTarget(MCInst &Inst, | |||
1621 | unsigned Offset, | |||
1622 | uint64_t Address, | |||
1623 | const void *Decoder) { | |||
1624 | int32_t BranchOffset = (SignExtend32<16>(Offset) * 4) + 4; | |||
1625 | Inst.addOperand(MCOperand::createImm(BranchOffset)); | |||
1626 | return MCDisassembler::Success; | |||
1627 | } | |||
1628 | ||||
1629 | static DecodeStatus DecodeJumpTarget(MCInst &Inst, | |||
1630 | unsigned Insn, | |||
1631 | uint64_t Address, | |||
1632 | const void *Decoder) { | |||
1633 | ||||
1634 | unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2; | |||
1635 | Inst.addOperand(MCOperand::createImm(JumpOffset)); | |||
1636 | return MCDisassembler::Success; | |||
1637 | } | |||
1638 | ||||
1639 | static DecodeStatus DecodeBranchTarget21(MCInst &Inst, | |||
1640 | unsigned Offset, | |||
1641 | uint64_t Address, | |||
1642 | const void *Decoder) { | |||
1643 | int32_t BranchOffset = SignExtend32<21>(Offset) * 4; | |||
1644 | ||||
1645 | Inst.addOperand(MCOperand::createImm(BranchOffset)); | |||
1646 | return MCDisassembler::Success; | |||
1647 | } | |||
1648 | ||||
1649 | static DecodeStatus DecodeBranchTarget26(MCInst &Inst, | |||
1650 | unsigned Offset, | |||
1651 | uint64_t Address, | |||
1652 | const void *Decoder) { | |||
1653 | int32_t BranchOffset = SignExtend32<26>(Offset) * 4; | |||
1654 | ||||
1655 | Inst.addOperand(MCOperand::createImm(BranchOffset)); | |||
1656 | return MCDisassembler::Success; | |||
1657 | } | |||
1658 | ||||
1659 | static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, | |||
1660 | unsigned Offset, | |||
1661 | uint64_t Address, | |||
1662 | const void *Decoder) { | |||
1663 | int32_t BranchOffset = SignExtend32<7>(Offset) << 1; | |||
1664 | Inst.addOperand(MCOperand::createImm(BranchOffset)); | |||
1665 | return MCDisassembler::Success; | |||
1666 | } | |||
1667 | ||||
1668 | static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, | |||
1669 | unsigned Offset, | |||
1670 | uint64_t Address, | |||
1671 | const void *Decoder) { | |||
1672 | int32_t BranchOffset = SignExtend32<10>(Offset) << 1; | |||
1673 | Inst.addOperand(MCOperand::createImm(BranchOffset)); | |||
1674 | return MCDisassembler::Success; | |||
1675 | } | |||
1676 | ||||
1677 | static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, | |||
1678 | unsigned Offset, | |||
1679 | uint64_t Address, | |||
1680 | const void *Decoder) { | |||
1681 | int32_t BranchOffset = SignExtend32<16>(Offset) * 2; | |||
1682 | Inst.addOperand(MCOperand::createImm(BranchOffset)); | |||
1683 | return MCDisassembler::Success; | |||
1684 | } | |||
1685 | ||||
1686 | static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, | |||
1687 | unsigned Insn, | |||
1688 | uint64_t Address, | |||
1689 | const void *Decoder) { | |||
1690 | unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1; | |||
1691 | Inst.addOperand(MCOperand::createImm(JumpOffset)); | |||
1692 | return MCDisassembler::Success; | |||
1693 | } | |||
1694 | ||||
1695 | static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, | |||
1696 | unsigned Value, | |||
1697 | uint64_t Address, | |||
1698 | const void *Decoder) { | |||
1699 | if (Value == 0) | |||
1700 | Inst.addOperand(MCOperand::createImm(1)); | |||
1701 | else if (Value == 0x7) | |||
1702 | Inst.addOperand(MCOperand::createImm(-1)); | |||
1703 | else | |||
1704 | Inst.addOperand(MCOperand::createImm(Value << 2)); | |||
1705 | return MCDisassembler::Success; | |||
1706 | } | |||
1707 | ||||
1708 | static DecodeStatus DecodeUImm6Lsl2(MCInst &Inst, | |||
1709 | unsigned Value, | |||
1710 | uint64_t Address, | |||
1711 | const void *Decoder) { | |||
1712 | Inst.addOperand(MCOperand::createImm(Value << 2)); | |||
1713 | return MCDisassembler::Success; | |||
1714 | } | |||
1715 | ||||
1716 | static DecodeStatus DecodeLiSimm7(MCInst &Inst, | |||
1717 | unsigned Value, | |||
1718 | uint64_t Address, | |||
1719 | const void *Decoder) { | |||
1720 | if (Value == 0x7F) | |||
1721 | Inst.addOperand(MCOperand::createImm(-1)); | |||
1722 | else | |||
1723 | Inst.addOperand(MCOperand::createImm(Value)); | |||
1724 | return MCDisassembler::Success; | |||
1725 | } | |||
1726 | ||||
1727 | static DecodeStatus DecodeSimm4(MCInst &Inst, | |||
1728 | unsigned Value, | |||
1729 | uint64_t Address, | |||
1730 | const void *Decoder) { | |||
1731 | Inst.addOperand(MCOperand::createImm(SignExtend32<4>(Value))); | |||
1732 | return MCDisassembler::Success; | |||
1733 | } | |||
1734 | ||||
1735 | static DecodeStatus DecodeSimm16(MCInst &Inst, | |||
1736 | unsigned Insn, | |||
1737 | uint64_t Address, | |||
1738 | const void *Decoder) { | |||
1739 | Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Insn))); | |||
1740 | return MCDisassembler::Success; | |||
1741 | } | |||
1742 | ||||
1743 | static DecodeStatus DecodeLSAImm(MCInst &Inst, | |||
1744 | unsigned Insn, | |||
1745 | uint64_t Address, | |||
1746 | const void *Decoder) { | |||
1747 | // We add one to the immediate field as it was encoded as 'imm - 1'. | |||
1748 | Inst.addOperand(MCOperand::createImm(Insn + 1)); | |||
1749 | return MCDisassembler::Success; | |||
1750 | } | |||
1751 | ||||
1752 | static DecodeStatus DecodeInsSize(MCInst &Inst, | |||
1753 | unsigned Insn, | |||
1754 | uint64_t Address, | |||
1755 | const void *Decoder) { | |||
1756 | // First we need to grab the pos(lsb) from MCInst. | |||
1757 | int Pos = Inst.getOperand(2).getImm(); | |||
1758 | int Size = (int) Insn - Pos + 1; | |||
1759 | Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Size))); | |||
1760 | return MCDisassembler::Success; | |||
1761 | } | |||
1762 | ||||
1763 | static DecodeStatus DecodeExtSize(MCInst &Inst, | |||
1764 | unsigned Insn, | |||
1765 | uint64_t Address, | |||
1766 | const void *Decoder) { | |||
1767 | int Size = (int) Insn + 1; | |||
1768 | Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Size))); | |||
1769 | return MCDisassembler::Success; | |||
1770 | } | |||
1771 | ||||
1772 | static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, | |||
1773 | uint64_t Address, const void *Decoder) { | |||
1774 | Inst.addOperand(MCOperand::createImm(SignExtend32<19>(Insn) * 4)); | |||
1775 | return MCDisassembler::Success; | |||
1776 | } | |||
1777 | ||||
1778 | static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, | |||
1779 | uint64_t Address, const void *Decoder) { | |||
1780 | Inst.addOperand(MCOperand::createImm(SignExtend32<18>(Insn) * 8)); | |||
1781 | return MCDisassembler::Success; | |||
1782 | } | |||
1783 | ||||
1784 | static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, | |||
1785 | uint64_t Address, const void *Decoder) { | |||
1786 | int32_t DecodedValue; | |||
1787 | switch (Insn) { | |||
1788 | case 0: DecodedValue = 256; break; | |||
1789 | case 1: DecodedValue = 257; break; | |||
1790 | case 510: DecodedValue = -258; break; | |||
1791 | case 511: DecodedValue = -257; break; | |||
1792 | default: DecodedValue = SignExtend32<9>(Insn); break; | |||
1793 | } | |||
1794 | Inst.addOperand(MCOperand::createImm(DecodedValue * 4)); | |||
1795 | return MCDisassembler::Success; | |||
1796 | } | |||
1797 | ||||
1798 | static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn, | |||
1799 | uint64_t Address, const void *Decoder) { | |||
1800 | // Insn must be >= 0, since it is unsigned that condition is always true. | |||
1801 | assert(Insn < 16)((Insn < 16) ? static_cast<void> (0) : __assert_fail ("Insn < 16", "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn246424/lib/Target/Mips/Disassembler/MipsDisassembler.cpp" , 1801, __PRETTY_FUNCTION__)); | |||
1802 | int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, | |||
1803 | 255, 32768, 65535}; | |||
1804 | Inst.addOperand(MCOperand::createImm(DecodedValues[Insn])); | |||
1805 | return MCDisassembler::Success; | |||
1806 | } | |||
1807 | ||||
1808 | static DecodeStatus DecodeUImm5lsl2(MCInst &Inst, unsigned Insn, | |||
1809 | uint64_t Address, const void *Decoder) { | |||
1810 | Inst.addOperand(MCOperand::createImm(Insn << 2)); | |||
1811 | return MCDisassembler::Success; | |||
1812 | } | |||
1813 | ||||
1814 | static DecodeStatus DecodeRegListOperand(MCInst &Inst, | |||
1815 | unsigned Insn, | |||
1816 | uint64_t Address, | |||
1817 | const void *Decoder) { | |||
1818 | unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, | |||
1819 | Mips::S6, Mips::FP}; | |||
1820 | unsigned RegNum; | |||
1821 | ||||
1822 | unsigned RegLst = fieldFromInstruction(Insn, 21, 5); | |||
1823 | // Empty register lists are not allowed. | |||
1824 | if (RegLst == 0) | |||
1825 | return MCDisassembler::Fail; | |||
1826 | ||||
1827 | RegNum = RegLst & 0xf; | |||
1828 | for (unsigned i = 0; i < RegNum; i++) | |||
1829 | Inst.addOperand(MCOperand::createReg(Regs[i])); | |||
1830 | ||||
1831 | if (RegLst & 0x10) | |||
1832 | Inst.addOperand(MCOperand::createReg(Mips::RA)); | |||
1833 | ||||
1834 | return MCDisassembler::Success; | |||
1835 | } | |||
1836 | ||||
1837 | static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn, | |||
1838 | uint64_t Address, | |||
1839 | const void *Decoder) { | |||
1840 | unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3}; | |||
1841 | unsigned RegLst = fieldFromInstruction(Insn, 4, 2); | |||
1842 | unsigned RegNum = RegLst & 0x3; | |||
1843 | ||||
1844 | for (unsigned i = 0; i <= RegNum; i++) | |||
1845 | Inst.addOperand(MCOperand::createReg(Regs[i])); | |||
1846 | ||||
1847 | Inst.addOperand(MCOperand::createReg(Mips::RA)); | |||
1848 | ||||
1849 | return MCDisassembler::Success; | |||
1850 | } | |||
1851 | ||||
1852 | static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned Insn, | |||
1853 | uint64_t Address, const void *Decoder) { | |||
1854 | ||||
1855 | unsigned RegPair = fieldFromInstruction(Insn, 7, 3); | |||
1856 | ||||
1857 | switch (RegPair) { | |||
1858 | default: | |||
1859 | return MCDisassembler::Fail; | |||
1860 | case 0: | |||
1861 | Inst.addOperand(MCOperand::createReg(Mips::A1)); | |||
1862 | Inst.addOperand(MCOperand::createReg(Mips::A2)); | |||
1863 | break; | |||
1864 | case 1: | |||
1865 | Inst.addOperand(MCOperand::createReg(Mips::A1)); | |||
1866 | Inst.addOperand(MCOperand::createReg(Mips::A3)); | |||
1867 | break; | |||
1868 | case 2: | |||
1869 | Inst.addOperand(MCOperand::createReg(Mips::A2)); | |||
1870 | Inst.addOperand(MCOperand::createReg(Mips::A3)); | |||
1871 | break; | |||
1872 | case 3: | |||
1873 | Inst.addOperand(MCOperand::createReg(Mips::A0)); | |||
1874 | Inst.addOperand(MCOperand::createReg(Mips::S5)); | |||
1875 | break; | |||
1876 | case 4: | |||
1877 | Inst.addOperand(MCOperand::createReg(Mips::A0)); | |||
1878 | Inst.addOperand(MCOperand::createReg(Mips::S6)); | |||
1879 | break; | |||
1880 | case 5: | |||
1881 | Inst.addOperand(MCOperand::createReg(Mips::A0)); | |||
1882 | Inst.addOperand(MCOperand::createReg(Mips::A1)); | |||
1883 | break; | |||
1884 | case 6: | |||
1885 | Inst.addOperand(MCOperand::createReg(Mips::A0)); | |||
1886 | Inst.addOperand(MCOperand::createReg(Mips::A2)); | |||
1887 | break; | |||
1888 | case 7: | |||
1889 | Inst.addOperand(MCOperand::createReg(Mips::A0)); | |||
1890 | Inst.addOperand(MCOperand::createReg(Mips::A3)); | |||
1891 | break; | |||
1892 | } | |||
1893 | ||||
1894 | return MCDisassembler::Success; | |||
1895 | } | |||
1896 | ||||
1897 | static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn, | |||
1898 | uint64_t Address, const void *Decoder) { | |||
1899 | Inst.addOperand(MCOperand::createImm(SignExtend32<25>(Insn << 2))); | |||
1900 | return MCDisassembler::Success; | |||
1901 | } |