/tmp/buildd/llvm-toolchain-snapshot-3.8~svn250694/lib/Target/Mips/MipsISelLowering.cpp

Bug Summary

File:	lib/Target/Mips/MipsISelLowering.cpp
Location:	line 1314, column 3
Description:	Value stored to 'BB' is never read

Annotated Source Code

1	//===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
2	//
3	// The LLVM Compiler Infrastructure
4	//
5	// This file is distributed under the University of Illinois Open Source
6	// License. See LICENSE.TXT for details.
7	//
8	//===----------------------------------------------------------------------===//
9	//
10	// This file defines the interfaces that Mips uses to lower LLVM code into a
11	// selection DAG.
12	//
13	//===----------------------------------------------------------------------===//
14	#include "MipsISelLowering.h"
15	#include "InstPrinter/MipsInstPrinter.h"
16	#include "MCTargetDesc/MipsBaseInfo.h"
17	#include "MipsCCState.h"
18	#include "MipsMachineFunction.h"
19	#include "MipsSubtarget.h"
20	#include "MipsTargetMachine.h"
21	#include "MipsTargetObjectFile.h"
22	#include "llvm/ADT/Statistic.h"
23	#include "llvm/ADT/StringSwitch.h"
24	#include "llvm/CodeGen/CallingConvLower.h"
25	#include "llvm/CodeGen/MachineFrameInfo.h"
26	#include "llvm/CodeGen/MachineFunction.h"
27	#include "llvm/CodeGen/MachineInstrBuilder.h"
28	#include "llvm/CodeGen/MachineJumpTableInfo.h"
29	#include "llvm/CodeGen/MachineRegisterInfo.h"
30	#include "llvm/CodeGen/FunctionLoweringInfo.h"
31	#include "llvm/CodeGen/SelectionDAGISel.h"
32	#include "llvm/CodeGen/ValueTypes.h"
33	#include "llvm/IR/CallingConv.h"
34	#include "llvm/IR/DerivedTypes.h"
35	#include "llvm/IR/GlobalVariable.h"
36	#include "llvm/Support/CommandLine.h"
37	#include "llvm/Support/Debug.h"
38	#include "llvm/Support/ErrorHandling.h"
39	#include "llvm/Support/raw_ostream.h"
40	#include <cctype>
41
42	using namespace llvm;
43
44	#define DEBUG_TYPE"mips-lower" "mips-lower"
45
46	STATISTIC(NumTailCalls, "Number of tail calls")static llvm::Statistic NumTailCalls = { "mips-lower", "Number of tail calls" , 0, 0 };
47
48	static cl::opt<bool>
49	LargeGOT("mxgot", cl::Hidden,
50	cl::desc("MIPS: Enable GOT larger than 64k."), cl::init(false));
51
52	static cl::opt<bool>
53	NoZeroDivCheck("mno-check-zero-division", cl::Hidden,
54	cl::desc("MIPS: Don't trap on integer division by zero."),
55	cl::init(false));
56
57	static const MCPhysReg Mips64DPRegs[8] = {
58	Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64,
59	Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64
60	};
61
62	// If I is a shifted mask, set the size (Size) and the first bit of the
63	// mask (Pos), and return true.
64	// For example, if I is 0x003ff800, (Pos, Size) = (11, 11).
65	static bool isShiftedMask(uint64_t I, uint64_t &Pos, uint64_t &Size) {
66	if (!isShiftedMask_64(I))
67	return false;
68
69	Size = countPopulation(I);
70	Pos = countTrailingZeros(I);
71	return true;
72	}
73
74	SDValue MipsTargetLowering::getGlobalReg(SelectionDAG &DAG, EVT Ty) const {
75	MipsFunctionInfo *FI = DAG.getMachineFunction().getInfo<MipsFunctionInfo>();
76	return DAG.getRegister(FI->getGlobalBaseReg(), Ty);
77	}
78
79	SDValue MipsTargetLowering::getTargetNode(GlobalAddressSDNode *N, EVT Ty,
80	SelectionDAG &DAG,
81	unsigned Flag) const {
82	return DAG.getTargetGlobalAddress(N->getGlobal(), SDLoc(N), Ty, 0, Flag);
83	}
84
85	SDValue MipsTargetLowering::getTargetNode(ExternalSymbolSDNode *N, EVT Ty,
86	SelectionDAG &DAG,
87	unsigned Flag) const {
88	return DAG.getTargetExternalSymbol(N->getSymbol(), Ty, Flag);
89	}
90
91	SDValue MipsTargetLowering::getTargetNode(BlockAddressSDNode *N, EVT Ty,
92	SelectionDAG &DAG,
93	unsigned Flag) const {
94	return DAG.getTargetBlockAddress(N->getBlockAddress(), Ty, 0, Flag);
95	}
96
97	SDValue MipsTargetLowering::getTargetNode(JumpTableSDNode *N, EVT Ty,
98	SelectionDAG &DAG,
99	unsigned Flag) const {
100	return DAG.getTargetJumpTable(N->getIndex(), Ty, Flag);
101	}
102
103	SDValue MipsTargetLowering::getTargetNode(ConstantPoolSDNode *N, EVT Ty,
104	SelectionDAG &DAG,
105	unsigned Flag) const {
106	return DAG.getTargetConstantPool(N->getConstVal(), Ty, N->getAlignment(),
107	N->getOffset(), Flag);
108	}
109
110	const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
111	switch ((MipsISD::NodeType)Opcode) {
112	case MipsISD::FIRST_NUMBER: break;
113	case MipsISD::JmpLink: return "MipsISD::JmpLink";
114	case MipsISD::TailCall: return "MipsISD::TailCall";
115	case MipsISD::Hi: return "MipsISD::Hi";
116	case MipsISD::Lo: return "MipsISD::Lo";
117	case MipsISD::GPRel: return "MipsISD::GPRel";
118	case MipsISD::ThreadPointer: return "MipsISD::ThreadPointer";
119	case MipsISD::Ret: return "MipsISD::Ret";
120	case MipsISD::EH_RETURN: return "MipsISD::EH_RETURN";
121	case MipsISD::FPBrcond: return "MipsISD::FPBrcond";
122	case MipsISD::FPCmp: return "MipsISD::FPCmp";
123	case MipsISD::CMovFP_T: return "MipsISD::CMovFP_T";
124	case MipsISD::CMovFP_F: return "MipsISD::CMovFP_F";
125	case MipsISD::TruncIntFP: return "MipsISD::TruncIntFP";
126	case MipsISD::MFHI: return "MipsISD::MFHI";
127	case MipsISD::MFLO: return "MipsISD::MFLO";
128	case MipsISD::MTLOHI: return "MipsISD::MTLOHI";
129	case MipsISD::Mult: return "MipsISD::Mult";
130	case MipsISD::Multu: return "MipsISD::Multu";
131	case MipsISD::MAdd: return "MipsISD::MAdd";
132	case MipsISD::MAddu: return "MipsISD::MAddu";
133	case MipsISD::MSub: return "MipsISD::MSub";
134	case MipsISD::MSubu: return "MipsISD::MSubu";
135	case MipsISD::DivRem: return "MipsISD::DivRem";
136	case MipsISD::DivRemU: return "MipsISD::DivRemU";
137	case MipsISD::DivRem16: return "MipsISD::DivRem16";
138	case MipsISD::DivRemU16: return "MipsISD::DivRemU16";
139	case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64";
140	case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64";
141	case MipsISD::Wrapper: return "MipsISD::Wrapper";
142	case MipsISD::DynAlloc: return "MipsISD::DynAlloc";
143	case MipsISD::Sync: return "MipsISD::Sync";
144	case MipsISD::Ext: return "MipsISD::Ext";
145	case MipsISD::Ins: return "MipsISD::Ins";
146	case MipsISD::LWL: return "MipsISD::LWL";
147	case MipsISD::LWR: return "MipsISD::LWR";
148	case MipsISD::SWL: return "MipsISD::SWL";
149	case MipsISD::SWR: return "MipsISD::SWR";
150	case MipsISD::LDL: return "MipsISD::LDL";
151	case MipsISD::LDR: return "MipsISD::LDR";
152	case MipsISD::SDL: return "MipsISD::SDL";
153	case MipsISD::SDR: return "MipsISD::SDR";
154	case MipsISD::EXTP: return "MipsISD::EXTP";
155	case MipsISD::EXTPDP: return "MipsISD::EXTPDP";
156	case MipsISD::EXTR_S_H: return "MipsISD::EXTR_S_H";
157	case MipsISD::EXTR_W: return "MipsISD::EXTR_W";
158	case MipsISD::EXTR_R_W: return "MipsISD::EXTR_R_W";
159	case MipsISD::EXTR_RS_W: return "MipsISD::EXTR_RS_W";
160	case MipsISD::SHILO: return "MipsISD::SHILO";
161	case MipsISD::MTHLIP: return "MipsISD::MTHLIP";
162	case MipsISD::MULSAQ_S_W_PH: return "MipsISD::MULSAQ_S_W_PH";
163	case MipsISD::MAQ_S_W_PHL: return "MipsISD::MAQ_S_W_PHL";
164	case MipsISD::MAQ_S_W_PHR: return "MipsISD::MAQ_S_W_PHR";
165	case MipsISD::MAQ_SA_W_PHL: return "MipsISD::MAQ_SA_W_PHL";
166	case MipsISD::MAQ_SA_W_PHR: return "MipsISD::MAQ_SA_W_PHR";
167	case MipsISD::DPAU_H_QBL: return "MipsISD::DPAU_H_QBL";
168	case MipsISD::DPAU_H_QBR: return "MipsISD::DPAU_H_QBR";
169	case MipsISD::DPSU_H_QBL: return "MipsISD::DPSU_H_QBL";
170	case MipsISD::DPSU_H_QBR: return "MipsISD::DPSU_H_QBR";
171	case MipsISD::DPAQ_S_W_PH: return "MipsISD::DPAQ_S_W_PH";
172	case MipsISD::DPSQ_S_W_PH: return "MipsISD::DPSQ_S_W_PH";
173	case MipsISD::DPAQ_SA_L_W: return "MipsISD::DPAQ_SA_L_W";
174	case MipsISD::DPSQ_SA_L_W: return "MipsISD::DPSQ_SA_L_W";
175	case MipsISD::DPA_W_PH: return "MipsISD::DPA_W_PH";
176	case MipsISD::DPS_W_PH: return "MipsISD::DPS_W_PH";
177	case MipsISD::DPAQX_S_W_PH: return "MipsISD::DPAQX_S_W_PH";
178	case MipsISD::DPAQX_SA_W_PH: return "MipsISD::DPAQX_SA_W_PH";
179	case MipsISD::DPAX_W_PH: return "MipsISD::DPAX_W_PH";
180	case MipsISD::DPSX_W_PH: return "MipsISD::DPSX_W_PH";
181	case MipsISD::DPSQX_S_W_PH: return "MipsISD::DPSQX_S_W_PH";
182	case MipsISD::DPSQX_SA_W_PH: return "MipsISD::DPSQX_SA_W_PH";
183	case MipsISD::MULSA_W_PH: return "MipsISD::MULSA_W_PH";
184	case MipsISD::MULT: return "MipsISD::MULT";
185	case MipsISD::MULTU: return "MipsISD::MULTU";
186	case MipsISD::MADD_DSP: return "MipsISD::MADD_DSP";
187	case MipsISD::MADDU_DSP: return "MipsISD::MADDU_DSP";
188	case MipsISD::MSUB_DSP: return "MipsISD::MSUB_DSP";
189	case MipsISD::MSUBU_DSP: return "MipsISD::MSUBU_DSP";
190	case MipsISD::SHLL_DSP: return "MipsISD::SHLL_DSP";
191	case MipsISD::SHRA_DSP: return "MipsISD::SHRA_DSP";
192	case MipsISD::SHRL_DSP: return "MipsISD::SHRL_DSP";
193	case MipsISD::SETCC_DSP: return "MipsISD::SETCC_DSP";
194	case MipsISD::SELECT_CC_DSP: return "MipsISD::SELECT_CC_DSP";
195	case MipsISD::VALL_ZERO: return "MipsISD::VALL_ZERO";
196	case MipsISD::VANY_ZERO: return "MipsISD::VANY_ZERO";
197	case MipsISD::VALL_NONZERO: return "MipsISD::VALL_NONZERO";
198	case MipsISD::VANY_NONZERO: return "MipsISD::VANY_NONZERO";
199	case MipsISD::VCEQ: return "MipsISD::VCEQ";
200	case MipsISD::VCLE_S: return "MipsISD::VCLE_S";
201	case MipsISD::VCLE_U: return "MipsISD::VCLE_U";
202	case MipsISD::VCLT_S: return "MipsISD::VCLT_S";
203	case MipsISD::VCLT_U: return "MipsISD::VCLT_U";
204	case MipsISD::VSMAX: return "MipsISD::VSMAX";
205	case MipsISD::VSMIN: return "MipsISD::VSMIN";
206	case MipsISD::VUMAX: return "MipsISD::VUMAX";
207	case MipsISD::VUMIN: return "MipsISD::VUMIN";
208	case MipsISD::VEXTRACT_SEXT_ELT: return "MipsISD::VEXTRACT_SEXT_ELT";
209	case MipsISD::VEXTRACT_ZEXT_ELT: return "MipsISD::VEXTRACT_ZEXT_ELT";
210	case MipsISD::VNOR: return "MipsISD::VNOR";
211	case MipsISD::VSHF: return "MipsISD::VSHF";
212	case MipsISD::SHF: return "MipsISD::SHF";
213	case MipsISD::ILVEV: return "MipsISD::ILVEV";
214	case MipsISD::ILVOD: return "MipsISD::ILVOD";
215	case MipsISD::ILVL: return "MipsISD::ILVL";
216	case MipsISD::ILVR: return "MipsISD::ILVR";
217	case MipsISD::PCKEV: return "MipsISD::PCKEV";
218	case MipsISD::PCKOD: return "MipsISD::PCKOD";
219	case MipsISD::INSVE: return "MipsISD::INSVE";
220	}
221	return nullptr;
222	}
223
224	MipsTargetLowering::MipsTargetLowering(const MipsTargetMachine &TM,
225	const MipsSubtarget &STI)
226	: TargetLowering(TM), Subtarget(STI), ABI(TM.getABI()) {
227	// Mips does not have i1 type, so use i32 for
228	// setcc operations results (slt, sgt, ...).
229	setBooleanContents(ZeroOrOneBooleanContent);
230	setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
231	// The cmp.cond.fmt instruction in MIPS32r6/MIPS64r6 uses 0 and -1 like MSA
232	// does. Integer booleans still use 0 and 1.
233	if (Subtarget.hasMips32r6())
234	setBooleanContents(ZeroOrOneBooleanContent,
235	ZeroOrNegativeOneBooleanContent);
236
237	// Load extented operations for i1 types must be promoted
238	for (MVT VT : MVT::integer_valuetypes()) {
239	setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
240	setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
241	setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
242	}
243
244	// MIPS doesn't have extending float->double load/store. Set LoadExtAction
245	// for f32, f16
246	for (MVT VT : MVT::fp_valuetypes()) {
247	setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
248	setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand);
249	}
250
251	// Set LoadExtAction for f16 vectors to Expand
252	for (MVT VT : MVT::fp_vector_valuetypes()) {
253	MVT F16VT = MVT::getVectorVT(MVT::f16, VT.getVectorNumElements());
254	if (F16VT.isValid())
255	setLoadExtAction(ISD::EXTLOAD, VT, F16VT, Expand);
256	}
257
258	setTruncStoreAction(MVT::f32, MVT::f16, Expand);
259	setTruncStoreAction(MVT::f64, MVT::f16, Expand);
260
261	setTruncStoreAction(MVT::f64, MVT::f32, Expand);
262
263	// Used by legalize types to correctly generate the setcc result.
264	// Without this, every float setcc comes with a AND/OR with the result,
265	// we don't want this, since the fpcmp result goes to a flag register,
266	// which is used implicitly by brcond and select operations.
267	AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
268
269	// Mips Custom Operations
270	setOperationAction(ISD::BR_JT, MVT::Other, Custom);
271	setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
272	setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
273	setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
274	setOperationAction(ISD::JumpTable, MVT::i32, Custom);
275	setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
276	setOperationAction(ISD::SELECT, MVT::f32, Custom);
277	setOperationAction(ISD::SELECT, MVT::f64, Custom);
278	setOperationAction(ISD::SELECT, MVT::i32, Custom);
279	setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
280	setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
281	setOperationAction(ISD::SETCC, MVT::f32, Custom);
282	setOperationAction(ISD::SETCC, MVT::f64, Custom);
283	setOperationAction(ISD::BRCOND, MVT::Other, Custom);
284	setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
285	setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
286	setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
287
288	if (Subtarget.isGP64bit()) {
289	setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
290	setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
291	setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
292	setOperationAction(ISD::JumpTable, MVT::i64, Custom);
293	setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
294	setOperationAction(ISD::SELECT, MVT::i64, Custom);
295	setOperationAction(ISD::LOAD, MVT::i64, Custom);
296	setOperationAction(ISD::STORE, MVT::i64, Custom);
297	setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
298	setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
299	setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
300	setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
301	}
302
303	if (!Subtarget.isGP64bit()) {
304	setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
305	setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
306	setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
307	}
308
309	setOperationAction(ISD::ADD, MVT::i32, Custom);
310	if (Subtarget.isGP64bit())
311	setOperationAction(ISD::ADD, MVT::i64, Custom);
312
313	setOperationAction(ISD::SDIV, MVT::i32, Expand);
314	setOperationAction(ISD::SREM, MVT::i32, Expand);
315	setOperationAction(ISD::UDIV, MVT::i32, Expand);
316	setOperationAction(ISD::UREM, MVT::i32, Expand);
317	setOperationAction(ISD::SDIV, MVT::i64, Expand);
318	setOperationAction(ISD::SREM, MVT::i64, Expand);
319	setOperationAction(ISD::UDIV, MVT::i64, Expand);
320	setOperationAction(ISD::UREM, MVT::i64, Expand);
321
322	// Operations not directly supported by Mips.
323	setOperationAction(ISD::BR_CC, MVT::f32, Expand);
324	setOperationAction(ISD::BR_CC, MVT::f64, Expand);
325	setOperationAction(ISD::BR_CC, MVT::i32, Expand);
326	setOperationAction(ISD::BR_CC, MVT::i64, Expand);
327	setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
328	setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
329	setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
330	setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
331	setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
332	setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
333	setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
334	if (Subtarget.hasCnMips()) {
335	setOperationAction(ISD::CTPOP, MVT::i32, Legal);
336	setOperationAction(ISD::CTPOP, MVT::i64, Legal);
337	} else {
338	setOperationAction(ISD::CTPOP, MVT::i32, Expand);
339	setOperationAction(ISD::CTPOP, MVT::i64, Expand);
340	}
341	setOperationAction(ISD::CTTZ, MVT::i32, Expand);
342	setOperationAction(ISD::CTTZ, MVT::i64, Expand);
343	setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
344	setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
345	setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
346	setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
347	setOperationAction(ISD::ROTL, MVT::i32, Expand);
348	setOperationAction(ISD::ROTL, MVT::i64, Expand);
349	setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
350	setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
351
352	if (!Subtarget.hasMips32r2())
353	setOperationAction(ISD::ROTR, MVT::i32, Expand);
354
355	if (!Subtarget.hasMips64r2())
356	setOperationAction(ISD::ROTR, MVT::i64, Expand);
357
358	setOperationAction(ISD::FSIN, MVT::f32, Expand);
359	setOperationAction(ISD::FSIN, MVT::f64, Expand);
360	setOperationAction(ISD::FCOS, MVT::f32, Expand);
361	setOperationAction(ISD::FCOS, MVT::f64, Expand);
362	setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
363	setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
364	setOperationAction(ISD::FPOWI, MVT::f32, Expand);
365	setOperationAction(ISD::FPOW, MVT::f32, Expand);
366	setOperationAction(ISD::FPOW, MVT::f64, Expand);
367	setOperationAction(ISD::FLOG, MVT::f32, Expand);
368	setOperationAction(ISD::FLOG2, MVT::f32, Expand);
369	setOperationAction(ISD::FLOG10, MVT::f32, Expand);
370	setOperationAction(ISD::FEXP, MVT::f32, Expand);
371	setOperationAction(ISD::FMA, MVT::f32, Expand);
372	setOperationAction(ISD::FMA, MVT::f64, Expand);
373	setOperationAction(ISD::FREM, MVT::f32, Expand);
374	setOperationAction(ISD::FREM, MVT::f64, Expand);
375
376	// Lower f16 conversion operations into library calls
377	setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
378	setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
379	setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
380	setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
381
382	setOperationAction(ISD::EH_RETURN, MVT::Other, Custom);
383
384	setOperationAction(ISD::VASTART, MVT::Other, Custom);
385	setOperationAction(ISD::VAARG, MVT::Other, Custom);
386	setOperationAction(ISD::VACOPY, MVT::Other, Expand);
387	setOperationAction(ISD::VAEND, MVT::Other, Expand);
388
389	// Use the default for now
390	setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
391	setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
392
393	setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand);
394	setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
395	setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand);
396	setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
397
398	setInsertFencesForAtomic(true);
399
400	if (!Subtarget.hasMips32r2()) {
401	setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
402	setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
403	}
404
405	// MIPS16 lacks MIPS32's clz and clo instructions.
406	if (!Subtarget.hasMips32() \|\| Subtarget.inMips16Mode())
407	setOperationAction(ISD::CTLZ, MVT::i32, Expand);
408	if (!Subtarget.hasMips64())
409	setOperationAction(ISD::CTLZ, MVT::i64, Expand);
410
411	if (!Subtarget.hasMips32r2())
412	setOperationAction(ISD::BSWAP, MVT::i32, Expand);
413	if (!Subtarget.hasMips64r2())
414	setOperationAction(ISD::BSWAP, MVT::i64, Expand);
415
416	if (Subtarget.isGP64bit()) {
417	setLoadExtAction(ISD::SEXTLOAD, MVT::i64, MVT::i32, Custom);
418	setLoadExtAction(ISD::ZEXTLOAD, MVT::i64, MVT::i32, Custom);
419	setLoadExtAction(ISD::EXTLOAD, MVT::i64, MVT::i32, Custom);
420	setTruncStoreAction(MVT::i64, MVT::i32, Custom);
421	}
422
423	setOperationAction(ISD::TRAP, MVT::Other, Legal);
424
425	setTargetDAGCombine(ISD::SDIVREM);
426	setTargetDAGCombine(ISD::UDIVREM);
427	setTargetDAGCombine(ISD::SELECT);
428	setTargetDAGCombine(ISD::AND);
429	setTargetDAGCombine(ISD::OR);
430	setTargetDAGCombine(ISD::ADD);
431
432	setMinFunctionAlignment(Subtarget.isGP64bit() ? 3 : 2);
433
434	// The arguments on the stack are defined in terms of 4-byte slots on O32
435	// and 8-byte slots on N32/N64.
436	setMinStackArgumentAlignment((ABI.IsN32() \|\| ABI.IsN64()) ? 8 : 4);
437
438	setStackPointerRegisterToSaveRestore(ABI.IsN64() ? Mips::SP_64 : Mips::SP);
439
440	setExceptionPointerRegister(ABI.IsN64() ? Mips::A0_64 : Mips::A0);
441	setExceptionSelectorRegister(ABI.IsN64() ? Mips::A1_64 : Mips::A1);
442
443	MaxStoresPerMemcpy = 16;
444
445	isMicroMips = Subtarget.inMicroMipsMode();
446	}
447
448	const MipsTargetLowering *MipsTargetLowering::create(const MipsTargetMachine &TM,
449	const MipsSubtarget &STI) {
450	if (STI.inMips16Mode())
451	return llvm::createMips16TargetLowering(TM, STI);
452
453	return llvm::createMipsSETargetLowering(TM, STI);
454	}
455
456	// Create a fast isel object.
457	FastISel *
458	MipsTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
459	const TargetLibraryInfo *libInfo) const {
460	if (!funcInfo.MF->getTarget().Options.EnableFastISel)
461	return TargetLowering::createFastISel(funcInfo, libInfo);
462	return Mips::createFastISel(funcInfo, libInfo);
463	}
464
465	EVT MipsTargetLowering::getSetCCResultType(const DataLayout &, LLVMContext &,
466	EVT VT) const {
467	if (!VT.isVector())
468	return MVT::i32;
469	return VT.changeVectorElementTypeToInteger();
470	}
471
472	static SDValue performDivRemCombine(SDNode *N, SelectionDAG &DAG,
473	TargetLowering::DAGCombinerInfo &DCI,
474	const MipsSubtarget &Subtarget) {
475	if (DCI.isBeforeLegalizeOps())
476	return SDValue();
477
478	EVT Ty = N->getValueType(0);
479	unsigned LO = (Ty == MVT::i32) ? Mips::LO0 : Mips::LO0_64;
480	unsigned HI = (Ty == MVT::i32) ? Mips::HI0 : Mips::HI0_64;
481	unsigned Opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem16 :
482	MipsISD::DivRemU16;
483	SDLoc DL(N);
484
485	SDValue DivRem = DAG.getNode(Opc, DL, MVT::Glue,
486	N->getOperand(0), N->getOperand(1));
487	SDValue InChain = DAG.getEntryNode();
488	SDValue InGlue = DivRem;
489
490	// insert MFLO
491	if (N->hasAnyUseOfValue(0)) {
492	SDValue CopyFromLo = DAG.getCopyFromReg(InChain, DL, LO, Ty,
493	InGlue);
494	DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo);
495	InChain = CopyFromLo.getValue(1);
496	InGlue = CopyFromLo.getValue(2);
497	}
498
499	// insert MFHI
500	if (N->hasAnyUseOfValue(1)) {
501	SDValue CopyFromHi = DAG.getCopyFromReg(InChain, DL,
502	HI, Ty, InGlue);
503	DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi);
504	}
505
506	return SDValue();
507	}
508
509	static Mips::CondCode condCodeToFCC(ISD::CondCode CC) {
510	switch (CC) {
511	default: llvm_unreachable("Unknown fp condition code!")::llvm::llvm_unreachable_internal("Unknown fp condition code!" , "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn250694/lib/Target/Mips/MipsISelLowering.cpp" , 511);
512	case ISD::SETEQ:
513	case ISD::SETOEQ: return Mips::FCOND_OEQ;
514	case ISD::SETUNE: return Mips::FCOND_UNE;
515	case ISD::SETLT:
516	case ISD::SETOLT: return Mips::FCOND_OLT;
517	case ISD::SETGT:
518	case ISD::SETOGT: return Mips::FCOND_OGT;
519	case ISD::SETLE:
520	case ISD::SETOLE: return Mips::FCOND_OLE;
521	case ISD::SETGE:
522	case ISD::SETOGE: return Mips::FCOND_OGE;
523	case ISD::SETULT: return Mips::FCOND_ULT;
524	case ISD::SETULE: return Mips::FCOND_ULE;
525	case ISD::SETUGT: return Mips::FCOND_UGT;
526	case ISD::SETUGE: return Mips::FCOND_UGE;
527	case ISD::SETUO: return Mips::FCOND_UN;
528	case ISD::SETO: return Mips::FCOND_OR;
529	case ISD::SETNE:
530	case ISD::SETONE: return Mips::FCOND_ONE;
531	case ISD::SETUEQ: return Mips::FCOND_UEQ;
532	}
533	}
534
535
536	/// This function returns true if the floating point conditional branches and
537	/// conditional moves which use condition code CC should be inverted.
538	static bool invertFPCondCodeUser(Mips::CondCode CC) {
539	if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
540	return false;
541
542	assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) &&(((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) && "Illegal Condition Code") ? static_cast<void> (0) : __assert_fail ("(CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) && \"Illegal Condition Code\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn250694/lib/Target/Mips/MipsISelLowering.cpp" , 543, __PRETTY_FUNCTION__))
543	"Illegal Condition Code")(((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) && "Illegal Condition Code") ? static_cast<void> (0) : __assert_fail ("(CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) && \"Illegal Condition Code\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn250694/lib/Target/Mips/MipsISelLowering.cpp" , 543, __PRETTY_FUNCTION__));
544
545	return true;
546	}
547
548	// Creates and returns an FPCmp node from a setcc node.
549	// Returns Op if setcc is not a floating point comparison.
550	static SDValue createFPCmp(SelectionDAG &DAG, const SDValue &Op) {
551	// must be a SETCC node
552	if (Op.getOpcode() != ISD::SETCC)
553	return Op;
554
555	SDValue LHS = Op.getOperand(0);
556
557	if (!LHS.getValueType().isFloatingPoint())
558	return Op;
559
560	SDValue RHS = Op.getOperand(1);
561	SDLoc DL(Op);
562
563	// Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of
564	// node if necessary.
565	ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
566
567	return DAG.getNode(MipsISD::FPCmp, DL, MVT::Glue, LHS, RHS,
568	DAG.getConstant(condCodeToFCC(CC), DL, MVT::i32));
569	}
570
571	// Creates and returns a CMovFPT/F node.
572	static SDValue createCMovFP(SelectionDAG &DAG, SDValue Cond, SDValue True,
573	SDValue False, SDLoc DL) {
574	ConstantSDNode *CC = cast<ConstantSDNode>(Cond.getOperand(2));
575	bool invert = invertFPCondCodeUser((Mips::CondCode)CC->getSExtValue());
576	SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32);
577
578	return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL,
579	True.getValueType(), True, FCC0, False, Cond);
580	}
581
582	static SDValue performSELECTCombine(SDNode *N, SelectionDAG &DAG,
583	TargetLowering::DAGCombinerInfo &DCI,
584	const MipsSubtarget &Subtarget) {
585	if (DCI.isBeforeLegalizeOps())
586	return SDValue();
587
588	SDValue SetCC = N->getOperand(0);
589
590	if ((SetCC.getOpcode() != ISD::SETCC) \|\|
591	!SetCC.getOperand(0).getValueType().isInteger())
592	return SDValue();
593
594	SDValue False = N->getOperand(2);
595	EVT FalseTy = False.getValueType();
596
597	if (!FalseTy.isInteger())
598	return SDValue();
599
600	ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(False);
601
602	// If the RHS (False) is 0, we swap the order of the operands
603	// of ISD::SELECT (obviously also inverting the condition) so that we can
604	// take advantage of conditional moves using the $0 register.
605	// Example:
606	// return (a != 0) ? x : 0;
607	// load $reg, x
608	// movz $reg, $0, a
609	if (!FalseC)
610	return SDValue();
611
612	const SDLoc DL(N);
613
614	if (!FalseC->getZExtValue()) {
615	ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get();
616	SDValue True = N->getOperand(1);
617
618	SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0),
619	SetCC.getOperand(1), ISD::getSetCCInverse(CC, true));
620
621	return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True);
622	}
623
624	// If both operands are integer constants there's a possibility that we
625	// can do some interesting optimizations.
626	SDValue True = N->getOperand(1);
627	ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(True);
628
629	if (!TrueC \|\| !True.getValueType().isInteger())
630	return SDValue();
631
632	// We'll also ignore MVT::i64 operands as this optimizations proves
633	// to be ineffective because of the required sign extensions as the result
634	// of a SETCC operator is always MVT::i32 for non-vector types.
635	if (True.getValueType() == MVT::i64)
636	return SDValue();
637
638	int64_t Diff = TrueC->getSExtValue() - FalseC->getSExtValue();
639
640	// 1) (a < x) ? y : y-1
641	// slti $reg1, a, x
642	// addiu $reg2, $reg1, y-1
643	if (Diff == 1)
644	return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, False);
645
646	// 2) (a < x) ? y-1 : y
647	// slti $reg1, a, x
648	// xor $reg1, $reg1, 1
649	// addiu $reg2, $reg1, y-1
650	if (Diff == -1) {
651	ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get();
652	SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0),
653	SetCC.getOperand(1), ISD::getSetCCInverse(CC, true));
654	return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, True);
655	}
656
657	// Couldn't optimize.
658	return SDValue();
659	}
660
661	static SDValue performCMovFPCombine(SDNode *N, SelectionDAG &DAG,
662	TargetLowering::DAGCombinerInfo &DCI,
663	const MipsSubtarget &Subtarget) {
664	if (DCI.isBeforeLegalizeOps())
665	return SDValue();
666
667	SDValue ValueIfTrue = N->getOperand(0), ValueIfFalse = N->getOperand(2);
668
669	ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(ValueIfFalse);
670	if (!FalseC \|\| FalseC->getZExtValue())
671	return SDValue();
672
673	// Since RHS (False) is 0, we swap the order of the True/False operands
674	// (obviously also inverting the condition) so that we can
675	// take advantage of conditional moves using the $0 register.
676	// Example:
677	// return (a != 0) ? x : 0;
678	// load $reg, x
679	// movz $reg, $0, a
680	unsigned Opc = (N->getOpcode() == MipsISD::CMovFP_T) ? MipsISD::CMovFP_F :
681	MipsISD::CMovFP_T;
682
683	SDValue FCC = N->getOperand(1), Glue = N->getOperand(3);
684	return DAG.getNode(Opc, SDLoc(N), ValueIfFalse.getValueType(),
685	ValueIfFalse, FCC, ValueIfTrue, Glue);
686	}
687
688	static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG,
689	TargetLowering::DAGCombinerInfo &DCI,
690	const MipsSubtarget &Subtarget) {
691	// Pattern match EXT.
692	// $dst = and ((sra or srl) $src , pos), (2**size - 1)
693	// => ext $dst, $src, size, pos
694	if (DCI.isBeforeLegalizeOps() \|\| !Subtarget.hasExtractInsert())
695	return SDValue();
696
697	SDValue ShiftRight = N->getOperand(0), Mask = N->getOperand(1);
698	unsigned ShiftRightOpc = ShiftRight.getOpcode();
699
700	// Op's first operand must be a shift right.
701	if (ShiftRightOpc != ISD::SRA && ShiftRightOpc != ISD::SRL)
702	return SDValue();
703
704	// The second operand of the shift must be an immediate.
705	ConstantSDNode *CN;
706	if (!(CN = dyn_cast<ConstantSDNode>(ShiftRight.getOperand(1))))
707	return SDValue();
708
709	uint64_t Pos = CN->getZExtValue();
710	uint64_t SMPos, SMSize;
711
712	// Op's second operand must be a shifted mask.
713	if (!(CN = dyn_cast<ConstantSDNode>(Mask)) \|\|
714	!isShiftedMask(CN->getZExtValue(), SMPos, SMSize))
715	return SDValue();
716
717	// Return if the shifted mask does not start at bit 0 or the sum of its size
718	// and Pos exceeds the word's size.
719	EVT ValTy = N->getValueType(0);
720	if (SMPos != 0 \|\| Pos + SMSize > ValTy.getSizeInBits())
721	return SDValue();
722
723	SDLoc DL(N);
724	return DAG.getNode(MipsISD::Ext, DL, ValTy,
725	ShiftRight.getOperand(0),
726	DAG.getConstant(Pos, DL, MVT::i32),
727	DAG.getConstant(SMSize, DL, MVT::i32));
728	}
729
730	static SDValue performORCombine(SDNode *N, SelectionDAG &DAG,
731	TargetLowering::DAGCombinerInfo &DCI,
732	const MipsSubtarget &Subtarget) {
733	// Pattern match INS.
734	// $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1),
735	// where mask1 = (2**size - 1) << pos, mask0 = ~mask1
736	// => ins $dst, $src, size, pos, $src1
737	if (DCI.isBeforeLegalizeOps() \|\| !Subtarget.hasExtractInsert())
738	return SDValue();
739
740	SDValue And0 = N->getOperand(0), And1 = N->getOperand(1);
741	uint64_t SMPos0, SMSize0, SMPos1, SMSize1;
742	ConstantSDNode *CN;
743
744	// See if Op's first operand matches (and $src1 , mask0).
745	if (And0.getOpcode() != ISD::AND)
746	return SDValue();
747
748	if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) \|\|
749	!isShiftedMask(~CN->getSExtValue(), SMPos0, SMSize0))
750	return SDValue();
751
752	// See if Op's second operand matches (and (shl $src, pos), mask1).
753	if (And1.getOpcode() != ISD::AND)
754	return SDValue();
755
756	if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) \|\|
757	!isShiftedMask(CN->getZExtValue(), SMPos1, SMSize1))
758	return SDValue();
759
760	// The shift masks must have the same position and size.
761	if (SMPos0 != SMPos1 \|\| SMSize0 != SMSize1)
762	return SDValue();
763
764	SDValue Shl = And1.getOperand(0);
765	if (Shl.getOpcode() != ISD::SHL)
766	return SDValue();
767
768	if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1))))
769	return SDValue();
770
771	unsigned Shamt = CN->getZExtValue();
772
773	// Return if the shift amount and the first bit position of mask are not the
774	// same.
775	EVT ValTy = N->getValueType(0);
776	if ((Shamt != SMPos0) \|\| (SMPos0 + SMSize0 > ValTy.getSizeInBits()))
777	return SDValue();
778
779	SDLoc DL(N);
780	return DAG.getNode(MipsISD::Ins, DL, ValTy, Shl.getOperand(0),
781	DAG.getConstant(SMPos0, DL, MVT::i32),
782	DAG.getConstant(SMSize0, DL, MVT::i32),
783	And0.getOperand(0));
784	}
785
786	static SDValue performADDCombine(SDNode *N, SelectionDAG &DAG,
787	TargetLowering::DAGCombinerInfo &DCI,
788	const MipsSubtarget &Subtarget) {
789	// (add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt))
790
791	if (DCI.isBeforeLegalizeOps())
792	return SDValue();
793
794	SDValue Add = N->getOperand(1);
795
796	if (Add.getOpcode() != ISD::ADD)
797	return SDValue();
798
799	SDValue Lo = Add.getOperand(1);
800
801	if ((Lo.getOpcode() != MipsISD::Lo) \|\|
802	(Lo.getOperand(0).getOpcode() != ISD::TargetJumpTable))
803	return SDValue();
804
805	EVT ValTy = N->getValueType(0);
806	SDLoc DL(N);
807
808	SDValue Add1 = DAG.getNode(ISD::ADD, DL, ValTy, N->getOperand(0),
809	Add.getOperand(0));
810	return DAG.getNode(ISD::ADD, DL, ValTy, Add1, Lo);
811	}
812
813	SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI)
814	const {
815	SelectionDAG &DAG = DCI.DAG;
816	unsigned Opc = N->getOpcode();
817
818	switch (Opc) {
819	default: break;
820	case ISD::SDIVREM:
821	case ISD::UDIVREM:
822	return performDivRemCombine(N, DAG, DCI, Subtarget);
823	case ISD::SELECT:
824	return performSELECTCombine(N, DAG, DCI, Subtarget);
825	case MipsISD::CMovFP_F:
826	case MipsISD::CMovFP_T:
827	return performCMovFPCombine(N, DAG, DCI, Subtarget);
828	case ISD::AND:
829	return performANDCombine(N, DAG, DCI, Subtarget);
830	case ISD::OR:
831	return performORCombine(N, DAG, DCI, Subtarget);
832	case ISD::ADD:
833	return performADDCombine(N, DAG, DCI, Subtarget);
834	}
835
836	return SDValue();
837	}
838
839	void
840	MipsTargetLowering::LowerOperationWrapper(SDNode *N,
841	SmallVectorImpl<SDValue> &Results,
842	SelectionDAG &DAG) const {
843	SDValue Res = LowerOperation(SDValue(N, 0), DAG);
844
845	for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I)
846	Results.push_back(Res.getValue(I));
847	}
848
849	void
850	MipsTargetLowering::ReplaceNodeResults(SDNode *N,
851	SmallVectorImpl<SDValue> &Results,
852	SelectionDAG &DAG) const {
853	return LowerOperationWrapper(N, Results, DAG);
854	}
855
856	SDValue MipsTargetLowering::
857	LowerOperation(SDValue Op, SelectionDAG &DAG) const
858	{
859	switch (Op.getOpcode())
860	{
861	case ISD::BR_JT: return lowerBR_JT(Op, DAG);
862	case ISD::BRCOND: return lowerBRCOND(Op, DAG);
863	case ISD::ConstantPool: return lowerConstantPool(Op, DAG);
864	case ISD::GlobalAddress: return lowerGlobalAddress(Op, DAG);
865	case ISD::BlockAddress: return lowerBlockAddress(Op, DAG);
866	case ISD::GlobalTLSAddress: return lowerGlobalTLSAddress(Op, DAG);
867	case ISD::JumpTable: return lowerJumpTable(Op, DAG);
868	case ISD::SELECT: return lowerSELECT(Op, DAG);
869	case ISD::SELECT_CC: return lowerSELECT_CC(Op, DAG);
870	case ISD::SETCC: return lowerSETCC(Op, DAG);
871	case ISD::VASTART: return lowerVASTART(Op, DAG);
872	case ISD::VAARG: return lowerVAARG(Op, DAG);
873	case ISD::FCOPYSIGN: return lowerFCOPYSIGN(Op, DAG);
874	case ISD::FRAMEADDR: return lowerFRAMEADDR(Op, DAG);
875	case ISD::RETURNADDR: return lowerRETURNADDR(Op, DAG);
876	case ISD::EH_RETURN: return lowerEH_RETURN(Op, DAG);
877	case ISD::ATOMIC_FENCE: return lowerATOMIC_FENCE(Op, DAG);
878	case ISD::SHL_PARTS: return lowerShiftLeftParts(Op, DAG);
879	case ISD::SRA_PARTS: return lowerShiftRightParts(Op, DAG, true);
880	case ISD::SRL_PARTS: return lowerShiftRightParts(Op, DAG, false);
881	case ISD::LOAD: return lowerLOAD(Op, DAG);
882	case ISD::STORE: return lowerSTORE(Op, DAG);
883	case ISD::ADD: return lowerADD(Op, DAG);
884	case ISD::FP_TO_SINT: return lowerFP_TO_SINT(Op, DAG);
885	}
886	return SDValue();
887	}
888
889	//===----------------------------------------------------------------------===//
890	// Lower helper functions
891	//===----------------------------------------------------------------------===//
892
893	// addLiveIn - This helper function adds the specified physical register to the
894	// MachineFunction as a live in value. It also creates a corresponding
895	// virtual register for it.
896	static unsigned
897	addLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC)
898	{
899	unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
900	MF.getRegInfo().addLiveIn(PReg, VReg);
901	return VReg;
902	}
903
904	static MachineBasicBlock insertDivByZeroTrap(MachineInstr MI,
905	MachineBasicBlock &MBB,
906	const TargetInstrInfo &TII,
907	bool Is64Bit) {
908	if (NoZeroDivCheck)
909	return &MBB;
910
911	// Insert instruction "teq $divisor_reg, $zero, 7".
912	MachineBasicBlock::iterator I(MI);
913	MachineInstrBuilder MIB;
914	MachineOperand &Divisor = MI->getOperand(2);
915	MIB = BuildMI(MBB, std::next(I), MI->getDebugLoc(), TII.get(Mips::TEQ))
916	.addReg(Divisor.getReg(), getKillRegState(Divisor.isKill()))
917	.addReg(Mips::ZERO).addImm(7);
918
919	// Use the 32-bit sub-register if this is a 64-bit division.
920	if (Is64Bit)
921	MIB->getOperand(0).setSubReg(Mips::sub_32);
922
923	// Clear Divisor's kill flag.
924	Divisor.setIsKill(false);
925
926	// We would normally delete the original instruction here but in this case
927	// we only needed to inject an additional instruction rather than replace it.
928
929	return &MBB;
930	}
931
932	MachineBasicBlock *
933	MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
934	MachineBasicBlock *BB) const {
935	switch (MI->getOpcode()) {
936	default:
937	llvm_unreachable("Unexpected instr type to insert")::llvm::llvm_unreachable_internal("Unexpected instr type to insert" , "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn250694/lib/Target/Mips/MipsISelLowering.cpp" , 937);
938	case Mips::ATOMIC_LOAD_ADD_I8:
939	return emitAtomicBinaryPartword(MI, BB, 1, Mips::ADDu);
940	case Mips::ATOMIC_LOAD_ADD_I16:
941	return emitAtomicBinaryPartword(MI, BB, 2, Mips::ADDu);
942	case Mips::ATOMIC_LOAD_ADD_I32:
943	return emitAtomicBinary(MI, BB, 4, Mips::ADDu);
944	case Mips::ATOMIC_LOAD_ADD_I64:
945	return emitAtomicBinary(MI, BB, 8, Mips::DADDu);
946
947	case Mips::ATOMIC_LOAD_AND_I8:
948	return emitAtomicBinaryPartword(MI, BB, 1, Mips::AND);
949	case Mips::ATOMIC_LOAD_AND_I16:
950	return emitAtomicBinaryPartword(MI, BB, 2, Mips::AND);
951	case Mips::ATOMIC_LOAD_AND_I32:
952	return emitAtomicBinary(MI, BB, 4, Mips::AND);
953	case Mips::ATOMIC_LOAD_AND_I64:
954	return emitAtomicBinary(MI, BB, 8, Mips::AND64);
955
956	case Mips::ATOMIC_LOAD_OR_I8:
957	return emitAtomicBinaryPartword(MI, BB, 1, Mips::OR);
958	case Mips::ATOMIC_LOAD_OR_I16:
959	return emitAtomicBinaryPartword(MI, BB, 2, Mips::OR);
960	case Mips::ATOMIC_LOAD_OR_I32:
961	return emitAtomicBinary(MI, BB, 4, Mips::OR);
962	case Mips::ATOMIC_LOAD_OR_I64:
963	return emitAtomicBinary(MI, BB, 8, Mips::OR64);
964
965	case Mips::ATOMIC_LOAD_XOR_I8:
966	return emitAtomicBinaryPartword(MI, BB, 1, Mips::XOR);
967	case Mips::ATOMIC_LOAD_XOR_I16:
968	return emitAtomicBinaryPartword(MI, BB, 2, Mips::XOR);
969	case Mips::ATOMIC_LOAD_XOR_I32:
970	return emitAtomicBinary(MI, BB, 4, Mips::XOR);
971	case Mips::ATOMIC_LOAD_XOR_I64:
972	return emitAtomicBinary(MI, BB, 8, Mips::XOR64);
973
974	case Mips::ATOMIC_LOAD_NAND_I8:
975	return emitAtomicBinaryPartword(MI, BB, 1, 0, true);
976	case Mips::ATOMIC_LOAD_NAND_I16:
977	return emitAtomicBinaryPartword(MI, BB, 2, 0, true);
978	case Mips::ATOMIC_LOAD_NAND_I32:
979	return emitAtomicBinary(MI, BB, 4, 0, true);
980	case Mips::ATOMIC_LOAD_NAND_I64:
981	return emitAtomicBinary(MI, BB, 8, 0, true);
982
983	case Mips::ATOMIC_LOAD_SUB_I8:
984	return emitAtomicBinaryPartword(MI, BB, 1, Mips::SUBu);
985	case Mips::ATOMIC_LOAD_SUB_I16:
986	return emitAtomicBinaryPartword(MI, BB, 2, Mips::SUBu);
987	case Mips::ATOMIC_LOAD_SUB_I32:
988	return emitAtomicBinary(MI, BB, 4, Mips::SUBu);
989	case Mips::ATOMIC_LOAD_SUB_I64:
990	return emitAtomicBinary(MI, BB, 8, Mips::DSUBu);
991
992	case Mips::ATOMIC_SWAP_I8:
993	return emitAtomicBinaryPartword(MI, BB, 1, 0);
994	case Mips::ATOMIC_SWAP_I16:
995	return emitAtomicBinaryPartword(MI, BB, 2, 0);
996	case Mips::ATOMIC_SWAP_I32:
997	return emitAtomicBinary(MI, BB, 4, 0);
998	case Mips::ATOMIC_SWAP_I64:
999	return emitAtomicBinary(MI, BB, 8, 0);
1000
1001	case Mips::ATOMIC_CMP_SWAP_I8:
1002	return emitAtomicCmpSwapPartword(MI, BB, 1);
1003	case Mips::ATOMIC_CMP_SWAP_I16:
1004	return emitAtomicCmpSwapPartword(MI, BB, 2);
1005	case Mips::ATOMIC_CMP_SWAP_I32:
1006	return emitAtomicCmpSwap(MI, BB, 4);
1007	case Mips::ATOMIC_CMP_SWAP_I64:
1008	return emitAtomicCmpSwap(MI, BB, 8);
1009	case Mips::PseudoSDIV:
1010	case Mips::PseudoUDIV:
1011	case Mips::DIV:
1012	case Mips::DIVU:
1013	case Mips::MOD:
1014	case Mips::MODU:
1015	return insertDivByZeroTrap(MI, BB, Subtarget.getInstrInfo(), false);
1016	case Mips::PseudoDSDIV:
1017	case Mips::PseudoDUDIV:
1018	case Mips::DDIV:
1019	case Mips::DDIVU:
1020	case Mips::DMOD:
1021	case Mips::DMODU:
1022	return insertDivByZeroTrap(MI, BB, Subtarget.getInstrInfo(), true);
1023	case Mips::SEL_D:
1024	return emitSEL_D(MI, BB);
1025
1026	case Mips::PseudoSELECT_I:
1027	case Mips::PseudoSELECT_I64:
1028	case Mips::PseudoSELECT_S:
1029	case Mips::PseudoSELECT_D32:
1030	case Mips::PseudoSELECT_D64:
1031	return emitPseudoSELECT(MI, BB, false, Mips::BNE);
1032	case Mips::PseudoSELECTFP_F_I:
1033	case Mips::PseudoSELECTFP_F_I64:
1034	case Mips::PseudoSELECTFP_F_S:
1035	case Mips::PseudoSELECTFP_F_D32:
1036	case Mips::PseudoSELECTFP_F_D64:
1037	return emitPseudoSELECT(MI, BB, true, Mips::BC1F);
1038	case Mips::PseudoSELECTFP_T_I:
1039	case Mips::PseudoSELECTFP_T_I64:
1040	case Mips::PseudoSELECTFP_T_S:
1041	case Mips::PseudoSELECTFP_T_D32:
1042	case Mips::PseudoSELECTFP_T_D64:
1043	return emitPseudoSELECT(MI, BB, true, Mips::BC1T);
1044	}
1045	}
1046
1047	// This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and
1048	// Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true)
1049	MachineBasicBlock *
1050	MipsTargetLowering::emitAtomicBinary(MachineInstr MI, MachineBasicBlock BB,
1051	unsigned Size, unsigned BinOpcode,
1052	bool Nand) const {
1053	assert((Size == 4 \|\| Size == 8) && "Unsupported size for EmitAtomicBinary.")(((Size == 4 \|\| Size == 8) && "Unsupported size for EmitAtomicBinary." ) ? static_cast<void> (0) : __assert_fail ("(Size == 4 \|\| Size == 8) && \"Unsupported size for EmitAtomicBinary.\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn250694/lib/Target/Mips/MipsISelLowering.cpp" , 1053, __PRETTY_FUNCTION__));
1054
1055	MachineFunction *MF = BB->getParent();
1056	MachineRegisterInfo &RegInfo = MF->getRegInfo();
1057	const TargetRegisterClass RC = getRegClassFor(MVT::getIntegerVT(Size 8));
1058	const TargetInstrInfo *TII = Subtarget.getInstrInfo();
1059	DebugLoc DL = MI->getDebugLoc();
1060	unsigned LL, SC, AND, NOR, ZERO, BEQ;
1061
1062	if (Size == 4) {
1063	if (isMicroMips) {
1064	LL = Mips::LL_MM;
1065	SC = Mips::SC_MM;
1066	} else {
1067	LL = Subtarget.hasMips32r6() ? Mips::LL_R6 : Mips::LL;
1068	SC = Subtarget.hasMips32r6() ? Mips::SC_R6 : Mips::SC;
1069	}
1070	AND = Mips::AND;
1071	NOR = Mips::NOR;
1072	ZERO = Mips::ZERO;
1073	BEQ = Mips::BEQ;
1074	} else {
1075	LL = Subtarget.hasMips64r6() ? Mips::LLD_R6 : Mips::LLD;
1076	SC = Subtarget.hasMips64r6() ? Mips::SCD_R6 : Mips::SCD;
1077	AND = Mips::AND64;
1078	NOR = Mips::NOR64;
1079	ZERO = Mips::ZERO_64;
1080	BEQ = Mips::BEQ64;
1081	}
1082
1083	unsigned OldVal = MI->getOperand(0).getReg();
1084	unsigned Ptr = MI->getOperand(1).getReg();
1085	unsigned Incr = MI->getOperand(2).getReg();
1086
1087	unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1088	unsigned AndRes = RegInfo.createVirtualRegister(RC);
1089	unsigned Success = RegInfo.createVirtualRegister(RC);
1090
1091	// insert new blocks after the current block
1092	const BasicBlock *LLVM_BB = BB->getBasicBlock();
1093	MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1094	MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1095	MachineFunction::iterator It = BB;
1096	++It;
1097	MF->insert(It, loopMBB);
1098	MF->insert(It, exitMBB);
1099
1100	// Transfer the remainder of BB and its successor edges to exitMBB.
1101	exitMBB->splice(exitMBB->begin(), BB,
1102	std::next(MachineBasicBlock::iterator(MI)), BB->end());
1103	exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1104
1105	// thisMBB:
1106	// ...
1107	// fallthrough --> loopMBB
1108	BB->addSuccessor(loopMBB);
1109	loopMBB->addSuccessor(loopMBB);
1110	loopMBB->addSuccessor(exitMBB);
1111
1112	// loopMBB:
1113	// ll oldval, 0(ptr)
1114	// <binop> storeval, oldval, incr
1115	// sc success, storeval, 0(ptr)
1116	// beq success, $0, loopMBB
1117	BB = loopMBB;
1118	BuildMI(BB, DL, TII->get(LL), OldVal).addReg(Ptr).addImm(0);
1119	if (Nand) {
1120	// and andres, oldval, incr
1121	// nor storeval, $0, andres
1122	BuildMI(BB, DL, TII->get(AND), AndRes).addReg(OldVal).addReg(Incr);
1123	BuildMI(BB, DL, TII->get(NOR), StoreVal).addReg(ZERO).addReg(AndRes);
1124	} else if (BinOpcode) {
1125	// <binop> storeval, oldval, incr
1126	BuildMI(BB, DL, TII->get(BinOpcode), StoreVal).addReg(OldVal).addReg(Incr);
1127	} else {
1128	StoreVal = Incr;
1129	}
1130	BuildMI(BB, DL, TII->get(SC), Success).addReg(StoreVal).addReg(Ptr).addImm(0);
1131	BuildMI(BB, DL, TII->get(BEQ)).addReg(Success).addReg(ZERO).addMBB(loopMBB);
1132
1133	MI->eraseFromParent(); // The instruction is gone now.
1134
1135	return exitMBB;
1136	}
1137
1138	MachineBasicBlock *MipsTargetLowering::emitSignExtendToI32InReg(
1139	MachineInstr MI, MachineBasicBlock BB, unsigned Size, unsigned DstReg,
1140	unsigned SrcReg) const {
1141	const TargetInstrInfo *TII = Subtarget.getInstrInfo();
1142	DebugLoc DL = MI->getDebugLoc();
1143
1144	if (Subtarget.hasMips32r2() && Size == 1) {
1145	BuildMI(BB, DL, TII->get(Mips::SEB), DstReg).addReg(SrcReg);
1146	return BB;
1147	}
1148
1149	if (Subtarget.hasMips32r2() && Size == 2) {
1150	BuildMI(BB, DL, TII->get(Mips::SEH), DstReg).addReg(SrcReg);
1151	return BB;
1152	}
1153
1154	MachineFunction *MF = BB->getParent();
1155	MachineRegisterInfo &RegInfo = MF->getRegInfo();
1156	const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1157	unsigned ScrReg = RegInfo.createVirtualRegister(RC);
1158
1159	assert(Size < 32)((Size < 32) ? static_cast<void> (0) : __assert_fail ("Size < 32", "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn250694/lib/Target/Mips/MipsISelLowering.cpp" , 1159, __PRETTY_FUNCTION__));
1160	int64_t ShiftImm = 32 - (Size * 8);
1161
1162	BuildMI(BB, DL, TII->get(Mips::SLL), ScrReg).addReg(SrcReg).addImm(ShiftImm);
1163	BuildMI(BB, DL, TII->get(Mips::SRA), DstReg).addReg(ScrReg).addImm(ShiftImm);
1164
1165	return BB;
1166	}
1167
1168	MachineBasicBlock *MipsTargetLowering::emitAtomicBinaryPartword(
1169	MachineInstr MI, MachineBasicBlock BB, unsigned Size, unsigned BinOpcode,
1170	bool Nand) const {
1171	assert((Size == 1 \|\| Size == 2) &&(((Size == 1 \|\| Size == 2) && "Unsupported size for EmitAtomicBinaryPartial." ) ? static_cast<void> (0) : __assert_fail ("(Size == 1 \|\| Size == 2) && \"Unsupported size for EmitAtomicBinaryPartial.\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn250694/lib/Target/Mips/MipsISelLowering.cpp" , 1172, __PRETTY_FUNCTION__))
1172	"Unsupported size for EmitAtomicBinaryPartial.")(((Size == 1 \|\| Size == 2) && "Unsupported size for EmitAtomicBinaryPartial." ) ? static_cast<void> (0) : __assert_fail ("(Size == 1 \|\| Size == 2) && \"Unsupported size for EmitAtomicBinaryPartial.\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn250694/lib/Target/Mips/MipsISelLowering.cpp" , 1172, __PRETTY_FUNCTION__));
1173
1174	MachineFunction *MF = BB->getParent();
1175	MachineRegisterInfo &RegInfo = MF->getRegInfo();
1176	const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1177	const TargetInstrInfo *TII = Subtarget.getInstrInfo();
1178	DebugLoc DL = MI->getDebugLoc();
1179
1180	unsigned Dest = MI->getOperand(0).getReg();
1181	unsigned Ptr = MI->getOperand(1).getReg();
1182	unsigned Incr = MI->getOperand(2).getReg();
1183
1184	unsigned AlignedAddr = RegInfo.createVirtualRegister(RC);
1185	unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
1186	unsigned Mask = RegInfo.createVirtualRegister(RC);
1187	unsigned Mask2 = RegInfo.createVirtualRegister(RC);
1188	unsigned NewVal = RegInfo.createVirtualRegister(RC);
1189	unsigned OldVal = RegInfo.createVirtualRegister(RC);
1190	unsigned Incr2 = RegInfo.createVirtualRegister(RC);
1191	unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC);
1192	unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC);
1193	unsigned MaskUpper = RegInfo.createVirtualRegister(RC);
1194	unsigned AndRes = RegInfo.createVirtualRegister(RC);
1195	unsigned BinOpRes = RegInfo.createVirtualRegister(RC);
1196	unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC);
1197	unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1198	unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC);
1199	unsigned SrlRes = RegInfo.createVirtualRegister(RC);
1200	unsigned Success = RegInfo.createVirtualRegister(RC);
1201
1202	// insert new blocks after the current block
1203	const BasicBlock *LLVM_BB = BB->getBasicBlock();
1204	MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1205	MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1206	MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1207	MachineFunction::iterator It = BB;
1208	++It;
1209	MF->insert(It, loopMBB);
1210	MF->insert(It, sinkMBB);
1211	MF->insert(It, exitMBB);
1212
1213	// Transfer the remainder of BB and its successor edges to exitMBB.
1214	exitMBB->splice(exitMBB->begin(), BB,
1215	std::next(MachineBasicBlock::iterator(MI)), BB->end());
1216	exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1217
1218	BB->addSuccessor(loopMBB);
1219	loopMBB->addSuccessor(loopMBB);
1220	loopMBB->addSuccessor(sinkMBB);
1221	sinkMBB->addSuccessor(exitMBB);
1222
1223	// thisMBB:
1224	// addiu masklsb2,$0,-4 # 0xfffffffc
1225	// and alignedaddr,ptr,masklsb2
1226	// andi ptrlsb2,ptr,3
1227	// sll shiftamt,ptrlsb2,3
1228	// ori maskupper,$0,255 # 0xff
1229	// sll mask,maskupper,shiftamt
1230	// nor mask2,$0,mask
1231	// sll incr2,incr,shiftamt
1232
1233	int64_t MaskImm = (Size == 1) ? 255 : 65535;
1234	BuildMI(BB, DL, TII->get(Mips::ADDiu), MaskLSB2)
1235	.addReg(Mips::ZERO).addImm(-4);
1236	BuildMI(BB, DL, TII->get(Mips::AND), AlignedAddr)
1237	.addReg(Ptr).addReg(MaskLSB2);
1238	BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3);
1239	if (Subtarget.isLittle()) {
1240	BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1241	} else {
1242	unsigned Off = RegInfo.createVirtualRegister(RC);
1243	BuildMI(BB, DL, TII->get(Mips::XORi), Off)
1244	.addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2);
1245	BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
1246	}
1247	BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper)
1248	.addReg(Mips::ZERO).addImm(MaskImm);
1249	BuildMI(BB, DL, TII->get(Mips::SLLV), Mask)
1250	.addReg(MaskUpper).addReg(ShiftAmt);
1251	BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
1252	BuildMI(BB, DL, TII->get(Mips::SLLV), Incr2).addReg(Incr).addReg(ShiftAmt);
1253
1254	// atomic.load.binop
1255	// loopMBB:
1256	// ll oldval,0(alignedaddr)
1257	// binop binopres,oldval,incr2
1258	// and newval,binopres,mask
1259	// and maskedoldval0,oldval,mask2
1260	// or storeval,maskedoldval0,newval
1261	// sc success,storeval,0(alignedaddr)
1262	// beq success,$0,loopMBB
1263
1264	// atomic.swap
1265	// loopMBB:
1266	// ll oldval,0(alignedaddr)
1267	// and newval,incr2,mask
1268	// and maskedoldval0,oldval,mask2
1269	// or storeval,maskedoldval0,newval
1270	// sc success,storeval,0(alignedaddr)
1271	// beq success,$0,loopMBB
1272
1273	BB = loopMBB;
1274	unsigned LL = isMicroMips ? Mips::LL_MM : Mips::LL;
1275	BuildMI(BB, DL, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0);
1276	if (Nand) {
1277	// and andres, oldval, incr2
1278	// nor binopres, $0, andres
1279	// and newval, binopres, mask
1280	BuildMI(BB, DL, TII->get(Mips::AND), AndRes).addReg(OldVal).addReg(Incr2);
1281	BuildMI(BB, DL, TII->get(Mips::NOR), BinOpRes)
1282	.addReg(Mips::ZERO).addReg(AndRes);
1283	BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask);
1284	} else if (BinOpcode) {
1285	// <binop> binopres, oldval, incr2
1286	// and newval, binopres, mask
1287	BuildMI(BB, DL, TII->get(BinOpcode), BinOpRes).addReg(OldVal).addReg(Incr2);
1288	BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask);
1289	} else { // atomic.swap
1290	// and newval, incr2, mask
1291	BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(Incr2).addReg(Mask);
1292	}
1293
1294	BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal0)
1295	.addReg(OldVal).addReg(Mask2);
1296	BuildMI(BB, DL, TII->get(Mips::OR), StoreVal)
1297	.addReg(MaskedOldVal0).addReg(NewVal);
1298	unsigned SC = isMicroMips ? Mips::SC_MM : Mips::SC;
1299	BuildMI(BB, DL, TII->get(SC), Success)
1300	.addReg(StoreVal).addReg(AlignedAddr).addImm(0);
1301	BuildMI(BB, DL, TII->get(Mips::BEQ))
1302	.addReg(Success).addReg(Mips::ZERO).addMBB(loopMBB);
1303
1304	// sinkMBB:
1305	// and maskedoldval1,oldval,mask
1306	// srl srlres,maskedoldval1,shiftamt
1307	// sign_extend dest,srlres
1308	BB = sinkMBB;
1309
1310	BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal1)
1311	.addReg(OldVal).addReg(Mask);
1312	BuildMI(BB, DL, TII->get(Mips::SRLV), SrlRes)
1313	.addReg(MaskedOldVal1).addReg(ShiftAmt);
1314	BB = emitSignExtendToI32InReg(MI, BB, Size, Dest, SrlRes);
	Value stored to 'BB' is never read
1315
1316	MI->eraseFromParent(); // The instruction is gone now.
1317
1318	return exitMBB;
1319	}
1320
1321	MachineBasicBlock * MipsTargetLowering::emitAtomicCmpSwap(MachineInstr *MI,
1322	MachineBasicBlock *BB,
1323	unsigned Size) const {
1324	assert((Size == 4 \|\| Size == 8) && "Unsupported size for EmitAtomicCmpSwap.")(((Size == 4 \|\| Size == 8) && "Unsupported size for EmitAtomicCmpSwap." ) ? static_cast<void> (0) : __assert_fail ("(Size == 4 \|\| Size == 8) && \"Unsupported size for EmitAtomicCmpSwap.\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn250694/lib/Target/Mips/MipsISelLowering.cpp" , 1324, __PRETTY_FUNCTION__));
1325
1326	MachineFunction *MF = BB->getParent();
1327	MachineRegisterInfo &RegInfo = MF->getRegInfo();
1328	const TargetRegisterClass RC = getRegClassFor(MVT::getIntegerVT(Size 8));
1329	const TargetInstrInfo *TII = Subtarget.getInstrInfo();
1330	DebugLoc DL = MI->getDebugLoc();
1331	unsigned LL, SC, ZERO, BNE, BEQ;
1332
1333	if (Size == 4) {
1334	LL = isMicroMips ? Mips::LL_MM : Mips::LL;
1335	SC = isMicroMips ? Mips::SC_MM : Mips::SC;
1336	ZERO = Mips::ZERO;
1337	BNE = Mips::BNE;
1338	BEQ = Mips::BEQ;
1339	} else {
1340	LL = Mips::LLD;
1341	SC = Mips::SCD;
1342	ZERO = Mips::ZERO_64;
1343	BNE = Mips::BNE64;
1344	BEQ = Mips::BEQ64;
1345	}
1346
1347	unsigned Dest = MI->getOperand(0).getReg();
1348	unsigned Ptr = MI->getOperand(1).getReg();
1349	unsigned OldVal = MI->getOperand(2).getReg();
1350	unsigned NewVal = MI->getOperand(3).getReg();
1351
1352	unsigned Success = RegInfo.createVirtualRegister(RC);
1353
1354	// insert new blocks after the current block
1355	const BasicBlock *LLVM_BB = BB->getBasicBlock();
1356	MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1357	MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1358	MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1359	MachineFunction::iterator It = BB;
1360	++It;
1361	MF->insert(It, loop1MBB);
1362	MF->insert(It, loop2MBB);
1363	MF->insert(It, exitMBB);
1364
1365	// Transfer the remainder of BB and its successor edges to exitMBB.
1366	exitMBB->splice(exitMBB->begin(), BB,
1367	std::next(MachineBasicBlock::iterator(MI)), BB->end());
1368	exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1369
1370	// thisMBB:
1371	// ...
1372	// fallthrough --> loop1MBB
1373	BB->addSuccessor(loop1MBB);
1374	loop1MBB->addSuccessor(exitMBB);
1375	loop1MBB->addSuccessor(loop2MBB);
1376	loop2MBB->addSuccessor(loop1MBB);
1377	loop2MBB->addSuccessor(exitMBB);
1378
1379	// loop1MBB:
1380	// ll dest, 0(ptr)
1381	// bne dest, oldval, exitMBB
1382	BB = loop1MBB;
1383	BuildMI(BB, DL, TII->get(LL), Dest).addReg(Ptr).addImm(0);
1384	BuildMI(BB, DL, TII->get(BNE))
1385	.addReg(Dest).addReg(OldVal).addMBB(exitMBB);
1386
1387	// loop2MBB:
1388	// sc success, newval, 0(ptr)
1389	// beq success, $0, loop1MBB
1390	BB = loop2MBB;
1391	BuildMI(BB, DL, TII->get(SC), Success)
1392	.addReg(NewVal).addReg(Ptr).addImm(0);
1393	BuildMI(BB, DL, TII->get(BEQ))
1394	.addReg(Success).addReg(ZERO).addMBB(loop1MBB);
1395
1396	MI->eraseFromParent(); // The instruction is gone now.
1397
1398	return exitMBB;
1399	}
1400
1401	MachineBasicBlock *
1402	MipsTargetLowering::emitAtomicCmpSwapPartword(MachineInstr *MI,
1403	MachineBasicBlock *BB,
1404	unsigned Size) const {
1405	assert((Size == 1 \|\| Size == 2) &&(((Size == 1 \|\| Size == 2) && "Unsupported size for EmitAtomicCmpSwapPartial." ) ? static_cast<void> (0) : __assert_fail ("(Size == 1 \|\| Size == 2) && \"Unsupported size for EmitAtomicCmpSwapPartial.\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn250694/lib/Target/Mips/MipsISelLowering.cpp" , 1406, __PRETTY_FUNCTION__))
1406	"Unsupported size for EmitAtomicCmpSwapPartial.")(((Size == 1 \|\| Size == 2) && "Unsupported size for EmitAtomicCmpSwapPartial." ) ? static_cast<void> (0) : __assert_fail ("(Size == 1 \|\| Size == 2) && \"Unsupported size for EmitAtomicCmpSwapPartial.\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn250694/lib/Target/Mips/MipsISelLowering.cpp" , 1406, __PRETTY_FUNCTION__));
1407
1408	MachineFunction *MF = BB->getParent();
1409	MachineRegisterInfo &RegInfo = MF->getRegInfo();
1410	const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1411	const TargetInstrInfo *TII = Subtarget.getInstrInfo();
1412	DebugLoc DL = MI->getDebugLoc();
1413
1414	unsigned Dest = MI->getOperand(0).getReg();
1415	unsigned Ptr = MI->getOperand(1).getReg();
1416	unsigned CmpVal = MI->getOperand(2).getReg();
1417	unsigned NewVal = MI->getOperand(3).getReg();
1418
1419	unsigned AlignedAddr = RegInfo.createVirtualRegister(RC);
1420	unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
1421	unsigned Mask = RegInfo.createVirtualRegister(RC);
1422	unsigned Mask2 = RegInfo.createVirtualRegister(RC);
1423	unsigned ShiftedCmpVal = RegInfo.createVirtualRegister(RC);
1424	unsigned OldVal = RegInfo.createVirtualRegister(RC);
1425	unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC);
1426	unsigned ShiftedNewVal = RegInfo.createVirtualRegister(RC);
1427	unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC);
1428	unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC);
1429	unsigned MaskUpper = RegInfo.createVirtualRegister(RC);
1430	unsigned MaskedCmpVal = RegInfo.createVirtualRegister(RC);
1431	unsigned MaskedNewVal = RegInfo.createVirtualRegister(RC);
1432	unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC);
1433	unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1434	unsigned SrlRes = RegInfo.createVirtualRegister(RC);
1435	unsigned Success = RegInfo.createVirtualRegister(RC);
1436
1437	// insert new blocks after the current block
1438	const BasicBlock *LLVM_BB = BB->getBasicBlock();
1439	MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1440	MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1441	MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1442	MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1443	MachineFunction::iterator It = BB;
1444	++It;
1445	MF->insert(It, loop1MBB);
1446	MF->insert(It, loop2MBB);
1447	MF->insert(It, sinkMBB);
1448	MF->insert(It, exitMBB);
1449
1450	// Transfer the remainder of BB and its successor edges to exitMBB.
1451	exitMBB->splice(exitMBB->begin(), BB,
1452	std::next(MachineBasicBlock::iterator(MI)), BB->end());
1453	exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1454
1455	BB->addSuccessor(loop1MBB);
1456	loop1MBB->addSuccessor(sinkMBB);
1457	loop1MBB->addSuccessor(loop2MBB);
1458	loop2MBB->addSuccessor(loop1MBB);
1459	loop2MBB->addSuccessor(sinkMBB);
1460	sinkMBB->addSuccessor(exitMBB);
1461
1462	// FIXME: computation of newval2 can be moved to loop2MBB.
1463	// thisMBB:
1464	// addiu masklsb2,$0,-4 # 0xfffffffc
1465	// and alignedaddr,ptr,masklsb2
1466	// andi ptrlsb2,ptr,3
1467	// sll shiftamt,ptrlsb2,3
1468	// ori maskupper,$0,255 # 0xff
1469	// sll mask,maskupper,shiftamt
1470	// nor mask2,$0,mask
1471	// andi maskedcmpval,cmpval,255
1472	// sll shiftedcmpval,maskedcmpval,shiftamt
1473	// andi maskednewval,newval,255
1474	// sll shiftednewval,maskednewval,shiftamt
1475	int64_t MaskImm = (Size == 1) ? 255 : 65535;
1476	BuildMI(BB, DL, TII->get(Mips::ADDiu), MaskLSB2)
1477	.addReg(Mips::ZERO).addImm(-4);
1478	BuildMI(BB, DL, TII->get(Mips::AND), AlignedAddr)
1479	.addReg(Ptr).addReg(MaskLSB2);
1480	BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3);
1481	if (Subtarget.isLittle()) {
1482	BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1483	} else {
1484	unsigned Off = RegInfo.createVirtualRegister(RC);
1485	BuildMI(BB, DL, TII->get(Mips::XORi), Off)
1486	.addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2);
1487	BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
1488	}
1489	BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper)
1490	.addReg(Mips::ZERO).addImm(MaskImm);
1491	BuildMI(BB, DL, TII->get(Mips::SLLV), Mask)
1492	.addReg(MaskUpper).addReg(ShiftAmt);
1493	BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
1494	BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedCmpVal)
1495	.addReg(CmpVal).addImm(MaskImm);
1496	BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedCmpVal)
1497	.addReg(MaskedCmpVal).addReg(ShiftAmt);
1498	BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedNewVal)
1499	.addReg(NewVal).addImm(MaskImm);
1500	BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedNewVal)
1501	.addReg(MaskedNewVal).addReg(ShiftAmt);
1502
1503	// loop1MBB:
1504	// ll oldval,0(alginedaddr)
1505	// and maskedoldval0,oldval,mask
1506	// bne maskedoldval0,shiftedcmpval,sinkMBB
1507	BB = loop1MBB;
1508	unsigned LL = isMicroMips ? Mips::LL_MM : Mips::LL;
1509	BuildMI(BB, DL, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0);
1510	BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal0)
1511	.addReg(OldVal).addReg(Mask);
1512	BuildMI(BB, DL, TII->get(Mips::BNE))
1513	.addReg(MaskedOldVal0).addReg(ShiftedCmpVal).addMBB(sinkMBB);
1514
1515	// loop2MBB:
1516	// and maskedoldval1,oldval,mask2
1517	// or storeval,maskedoldval1,shiftednewval
1518	// sc success,storeval,0(alignedaddr)
1519	// beq success,$0,loop1MBB
1520	BB = loop2MBB;
1521	BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal1)
1522	.addReg(OldVal).addReg(Mask2);
1523	BuildMI(BB, DL, TII->get(Mips::OR), StoreVal)
1524	.addReg(MaskedOldVal1).addReg(ShiftedNewVal);
1525	unsigned SC = isMicroMips ? Mips::SC_MM : Mips::SC;
1526	BuildMI(BB, DL, TII->get(SC), Success)
1527	.addReg(StoreVal).addReg(AlignedAddr).addImm(0);
1528	BuildMI(BB, DL, TII->get(Mips::BEQ))
1529	.addReg(Success).addReg(Mips::ZERO).addMBB(loop1MBB);
1530
1531	// sinkMBB:
1532	// srl srlres,maskedoldval0,shiftamt
1533	// sign_extend dest,srlres
1534	BB = sinkMBB;
1535
1536	BuildMI(BB, DL, TII->get(Mips::SRLV), SrlRes)
1537	.addReg(MaskedOldVal0).addReg(ShiftAmt);
1538	BB = emitSignExtendToI32InReg(MI, BB, Size, Dest, SrlRes);
1539
1540	MI->eraseFromParent(); // The instruction is gone now.
1541
1542	return exitMBB;
1543	}
1544
1545	MachineBasicBlock MipsTargetLowering::emitSEL_D(MachineInstr MI,
1546	MachineBasicBlock *BB) const {
1547	MachineFunction *MF = BB->getParent();
1548	const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
1549	const TargetInstrInfo *TII = Subtarget.getInstrInfo();
1550	MachineRegisterInfo &RegInfo = MF->getRegInfo();
1551	DebugLoc DL = MI->getDebugLoc();
1552	MachineBasicBlock::iterator II(MI);
1553
1554	unsigned Fc = MI->getOperand(1).getReg();
1555	const auto &FGR64RegClass = TRI->getRegClass(Mips::FGR64RegClassID);
1556
1557	unsigned Fc2 = RegInfo.createVirtualRegister(FGR64RegClass);
1558
1559	BuildMI(*BB, II, DL, TII->get(Mips::SUBREG_TO_REG), Fc2)
1560	.addImm(0)
1561	.addReg(Fc)
1562	.addImm(Mips::sub_lo);
1563
1564	// We don't erase the original instruction, we just replace the condition
1565	// register with the 64-bit super-register.
1566	MI->getOperand(1).setReg(Fc2);
1567
1568	return BB;
1569	}
1570
1571	//===----------------------------------------------------------------------===//
1572	// Misc Lower Operation implementation
1573	//===----------------------------------------------------------------------===//
1574	SDValue MipsTargetLowering::lowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
1575	SDValue Chain = Op.getOperand(0);
1576	SDValue Table = Op.getOperand(1);
1577	SDValue Index = Op.getOperand(2);
1578	SDLoc DL(Op);
1579	auto &TD = DAG.getDataLayout();
1580	EVT PTy = getPointerTy(TD);
1581	unsigned EntrySize =
1582	DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(TD);
1583
1584	Index = DAG.getNode(ISD::MUL, DL, PTy, Index,
1585	DAG.getConstant(EntrySize, DL, PTy));
1586	SDValue Addr = DAG.getNode(ISD::ADD, DL, PTy, Index, Table);
1587
1588	EVT MemVT = EVT::getIntegerVT(DAG.getContext(), EntrySize 8);
1589	Addr =
1590	DAG.getExtLoad(ISD::SEXTLOAD, DL, PTy, Chain, Addr,
1591	MachinePointerInfo::getJumpTable(DAG.getMachineFunction()),
1592	MemVT, false, false, false, 0);
1593	Chain = Addr.getValue(1);
1594
1595	if ((getTargetMachine().getRelocationModel() == Reloc::PIC_) \|\| ABI.IsN64()) {
1596	// For PIC, the sequence is:
1597	// BRIND(load(Jumptable + index) + RelocBase)
1598	// RelocBase can be JumpTable, GOT or some sort of global base.
1599	Addr = DAG.getNode(ISD::ADD, DL, PTy, Addr,
1600	getPICJumpTableRelocBase(Table, DAG));
1601	}
1602
1603	return DAG.getNode(ISD::BRIND, DL, MVT::Other, Chain, Addr);
1604	}
1605
1606	SDValue MipsTargetLowering::lowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
1607	// The first operand is the chain, the second is the condition, the third is
1608	// the block to branch to if the condition is true.
1609	SDValue Chain = Op.getOperand(0);
1610	SDValue Dest = Op.getOperand(2);
1611	SDLoc DL(Op);
1612
1613	assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6())((!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6( )) ? static_cast<void> (0) : __assert_fail ("!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6()" , "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn250694/lib/Target/Mips/MipsISelLowering.cpp" , 1613, __PRETTY_FUNCTION__));
1614	SDValue CondRes = createFPCmp(DAG, Op.getOperand(1));
1615
1616	// Return if flag is not set by a floating point comparison.
1617	if (CondRes.getOpcode() != MipsISD::FPCmp)
1618	return Op;
1619
1620	SDValue CCNode = CondRes.getOperand(2);
1621	Mips::CondCode CC =
1622	(Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue();
1623	unsigned Opc = invertFPCondCodeUser(CC) ? Mips::BRANCH_F : Mips::BRANCH_T;
1624	SDValue BrCode = DAG.getConstant(Opc, DL, MVT::i32);
1625	SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32);
1626	return DAG.getNode(MipsISD::FPBrcond, DL, Op.getValueType(), Chain, BrCode,
1627	FCC0, Dest, CondRes);
1628	}
1629
1630	SDValue MipsTargetLowering::
1631	lowerSELECT(SDValue Op, SelectionDAG &DAG) const
1632	{
1633	assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6())((!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6( )) ? static_cast<void> (0) : __assert_fail ("!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6()" , "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn250694/lib/Target/Mips/MipsISelLowering.cpp" , 1633, __PRETTY_FUNCTION__));
1634	SDValue Cond = createFPCmp(DAG, Op.getOperand(0));
1635
1636	// Return if flag is not set by a floating point comparison.
1637	if (Cond.getOpcode() != MipsISD::FPCmp)
1638	return Op;
1639
1640	return createCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2),
1641	SDLoc(Op));
1642	}
1643
1644	SDValue MipsTargetLowering::
1645	lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const
1646	{
1647	SDLoc DL(Op);
1648	EVT Ty = Op.getOperand(0).getValueType();
1649	SDValue Cond =
1650	DAG.getNode(ISD::SETCC, DL, getSetCCResultType(DAG.getDataLayout(),
1651	*DAG.getContext(), Ty),
1652	Op.getOperand(0), Op.getOperand(1), Op.getOperand(4));
1653
1654	return DAG.getNode(ISD::SELECT, DL, Op.getValueType(), Cond, Op.getOperand(2),
1655	Op.getOperand(3));
1656	}
1657
1658	SDValue MipsTargetLowering::lowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1659	assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6())((!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6( )) ? static_cast<void> (0) : __assert_fail ("!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6()" , "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn250694/lib/Target/Mips/MipsISelLowering.cpp" , 1659, __PRETTY_FUNCTION__));
1660	SDValue Cond = createFPCmp(DAG, Op);
1661
1662	assert(Cond.getOpcode() == MipsISD::FPCmp &&((Cond.getOpcode() == MipsISD::FPCmp && "Floating point operand expected." ) ? static_cast<void> (0) : __assert_fail ("Cond.getOpcode() == MipsISD::FPCmp && \"Floating point operand expected.\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn250694/lib/Target/Mips/MipsISelLowering.cpp" , 1663, __PRETTY_FUNCTION__))
1663	"Floating point operand expected.")((Cond.getOpcode() == MipsISD::FPCmp && "Floating point operand expected." ) ? static_cast<void> (0) : __assert_fail ("Cond.getOpcode() == MipsISD::FPCmp && \"Floating point operand expected.\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn250694/lib/Target/Mips/MipsISelLowering.cpp" , 1663, __PRETTY_FUNCTION__));
1664
1665	SDLoc DL(Op);
1666	SDValue True = DAG.getConstant(1, DL, MVT::i32);
1667	SDValue False = DAG.getConstant(0, DL, MVT::i32);
1668
1669	return createCMovFP(DAG, Cond, True, False, DL);
1670	}
1671
1672	SDValue MipsTargetLowering::lowerGlobalAddress(SDValue Op,
1673	SelectionDAG &DAG) const {
1674	EVT Ty = Op.getValueType();
1675	GlobalAddressSDNode *N = cast<GlobalAddressSDNode>(Op);
1676	const GlobalValue *GV = N->getGlobal();
1677
1678	if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !ABI.IsN64()) {
1679	const MipsTargetObjectFile *TLOF =
1680	static_cast<const MipsTargetObjectFile *>(
1681	getTargetMachine().getObjFileLowering());
1682	if (TLOF->IsGlobalInSmallSection(GV, getTargetMachine()))
1683	// %gp_rel relocation
1684	return getAddrGPRel(N, SDLoc(N), Ty, DAG);
1685
1686	// %hi/%lo relocation
1687	return getAddrNonPIC(N, SDLoc(N), Ty, DAG);
1688	}
1689
1690	if (GV->hasInternalLinkage() \|\| (GV->hasLocalLinkage() && !isa<Function>(GV)))
1691	return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() \|\| ABI.IsN64());
1692
1693	if (LargeGOT)
1694	return getAddrGlobalLargeGOT(
1695	N, SDLoc(N), Ty, DAG, MipsII::MO_GOT_HI16, MipsII::MO_GOT_LO16,
1696	DAG.getEntryNode(),
1697	MachinePointerInfo::getGOT(DAG.getMachineFunction()));
1698
1699	return getAddrGlobal(
1700	N, SDLoc(N), Ty, DAG,
1701	(ABI.IsN32() \|\| ABI.IsN64()) ? MipsII::MO_GOT_DISP : MipsII::MO_GOT16,
1702	DAG.getEntryNode(), MachinePointerInfo::getGOT(DAG.getMachineFunction()));
1703	}
1704
1705	SDValue MipsTargetLowering::lowerBlockAddress(SDValue Op,
1706	SelectionDAG &DAG) const {
1707	BlockAddressSDNode *N = cast<BlockAddressSDNode>(Op);
1708	EVT Ty = Op.getValueType();
1709
1710	if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !ABI.IsN64())
1711	return getAddrNonPIC(N, SDLoc(N), Ty, DAG);
1712
1713	return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() \|\| ABI.IsN64());
1714	}
1715
1716	SDValue MipsTargetLowering::
1717	lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
1718	{
1719	// If the relocation model is PIC, use the General Dynamic TLS Model or
1720	// Local Dynamic TLS model, otherwise use the Initial Exec or
1721	// Local Exec TLS Model.
1722
1723	GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1724	if (DAG.getTarget().Options.EmulatedTLS)
1725	return LowerToTLSEmulatedModel(GA, DAG);
1726
1727	SDLoc DL(GA);
1728	const GlobalValue *GV = GA->getGlobal();
1729	EVT PtrVT = getPointerTy(DAG.getDataLayout());
1730
1731	TLSModel::Model model = getTargetMachine().getTLSModel(GV);
1732
1733	if (model == TLSModel::GeneralDynamic \|\| model == TLSModel::LocalDynamic) {
1734	// General Dynamic and Local Dynamic TLS Model.
1735	unsigned Flag = (model == TLSModel::LocalDynamic) ? MipsII::MO_TLSLDM
1736	: MipsII::MO_TLSGD;
1737
1738	SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, Flag);
1739	SDValue Argument = DAG.getNode(MipsISD::Wrapper, DL, PtrVT,
1740	getGlobalReg(DAG, PtrVT), TGA);
1741	unsigned PtrSize = PtrVT.getSizeInBits();
1742	IntegerType PtrTy = Type::getIntNTy(DAG.getContext(), PtrSize);
1743
1744	SDValue TlsGetAddr = DAG.getExternalSymbol("__tls_get_addr", PtrVT);
1745
1746	ArgListTy Args;
1747	ArgListEntry Entry;
1748	Entry.Node = Argument;
1749	Entry.Ty = PtrTy;
1750	Args.push_back(Entry);
1751
1752	TargetLowering::CallLoweringInfo CLI(DAG);
1753	CLI.setDebugLoc(DL).setChain(DAG.getEntryNode())
1754	.setCallee(CallingConv::C, PtrTy, TlsGetAddr, std::move(Args), 0);
1755	std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
1756
1757	SDValue Ret = CallResult.first;
1758
1759	if (model != TLSModel::LocalDynamic)
1760	return Ret;
1761
1762	SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
1763	MipsII::MO_DTPREL_HI);
1764	SDValue Hi = DAG.getNode(MipsISD::Hi, DL, PtrVT, TGAHi);
1765	SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
1766	MipsII::MO_DTPREL_LO);
1767	SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo);
1768	SDValue Add = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Ret);
1769	return DAG.getNode(ISD::ADD, DL, PtrVT, Add, Lo);
1770	}
1771
1772	SDValue Offset;
1773	if (model == TLSModel::InitialExec) {
1774	// Initial Exec TLS Model
1775	SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
1776	MipsII::MO_GOTTPREL);
1777	TGA = DAG.getNode(MipsISD::Wrapper, DL, PtrVT, getGlobalReg(DAG, PtrVT),
1778	TGA);
1779	Offset = DAG.getLoad(PtrVT, DL,
1780	DAG.getEntryNode(), TGA, MachinePointerInfo(),
1781	false, false, false, 0);
1782	} else {
1783	// Local Exec TLS Model
1784	assert(model == TLSModel::LocalExec)((model == TLSModel::LocalExec) ? static_cast<void> (0) : __assert_fail ("model == TLSModel::LocalExec", "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn250694/lib/Target/Mips/MipsISelLowering.cpp" , 1784, __PRETTY_FUNCTION__));
1785	SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
1786	MipsII::MO_TPREL_HI);
1787	SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
1788	MipsII::MO_TPREL_LO);
1789	SDValue Hi = DAG.getNode(MipsISD::Hi, DL, PtrVT, TGAHi);
1790	SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo);
1791	Offset = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1792	}
1793
1794	SDValue ThreadPointer = DAG.getNode(MipsISD::ThreadPointer, DL, PtrVT);
1795	return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadPointer, Offset);
1796	}
1797
1798	SDValue MipsTargetLowering::
1799	lowerJumpTable(SDValue Op, SelectionDAG &DAG) const
1800	{
1801	JumpTableSDNode *N = cast<JumpTableSDNode>(Op);
1802	EVT Ty = Op.getValueType();
1803
1804	if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !ABI.IsN64())
1805	return getAddrNonPIC(N, SDLoc(N), Ty, DAG);
1806
1807	return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() \|\| ABI.IsN64());
1808	}
1809
1810	SDValue MipsTargetLowering::
1811	lowerConstantPool(SDValue Op, SelectionDAG &DAG) const
1812	{
1813	ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
1814	EVT Ty = Op.getValueType();
1815
1816	if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !ABI.IsN64()) {
1817	const MipsTargetObjectFile *TLOF =
1818	static_cast<const MipsTargetObjectFile *>(
1819	getTargetMachine().getObjFileLowering());
1820
1821	if (TLOF->IsConstantInSmallSection(DAG.getDataLayout(), N->getConstVal(),
1822	getTargetMachine()))
1823	// %gp_rel relocation
1824	return getAddrGPRel(N, SDLoc(N), Ty, DAG);
1825
1826	return getAddrNonPIC(N, SDLoc(N), Ty, DAG);
1827	}
1828
1829	return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() \|\| ABI.IsN64());
1830	}
1831
1832	SDValue MipsTargetLowering::lowerVASTART(SDValue Op, SelectionDAG &DAG) const {
1833	MachineFunction &MF = DAG.getMachineFunction();
1834	MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
1835
1836	SDLoc DL(Op);
1837	SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
1838	getPointerTy(MF.getDataLayout()));
1839
1840	// vastart just stores the address of the VarArgsFrameIndex slot into the
1841	// memory location argument.
1842	const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1843	return DAG.getStore(Op.getOperand(0), DL, FI, Op.getOperand(1),
1844	MachinePointerInfo(SV), false, false, 0);
1845	}
1846
1847	SDValue MipsTargetLowering::lowerVAARG(SDValue Op, SelectionDAG &DAG) const {
1848	SDNode *Node = Op.getNode();
1849	EVT VT = Node->getValueType(0);
1850	SDValue Chain = Node->getOperand(0);
1851	SDValue VAListPtr = Node->getOperand(1);
1852	unsigned Align = Node->getConstantOperandVal(3);
1853	const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
1854	SDLoc DL(Node);
1855	unsigned ArgSlotSizeInBytes = (ABI.IsN32() \|\| ABI.IsN64()) ? 8 : 4;
1856
1857	SDValue VAListLoad =
1858	DAG.getLoad(getPointerTy(DAG.getDataLayout()), DL, Chain, VAListPtr,
1859	MachinePointerInfo(SV), false, false, false, 0);
1860	SDValue VAList = VAListLoad;
1861
1862	// Re-align the pointer if necessary.
1863	// It should only ever be necessary for 64-bit types on O32 since the minimum
1864	// argument alignment is the same as the maximum type alignment for N32/N64.
1865	//
1866	// FIXME: We currently align too often. The code generator doesn't notice
1867	// when the pointer is still aligned from the last va_arg (or pair of
1868	// va_args for the i64 on O32 case).
1869	if (Align > getMinStackArgumentAlignment()) {
1870	assert(((Align & (Align-1)) == 0) && "Expected Align to be a power of 2")((((Align & (Align-1)) == 0) && "Expected Align to be a power of 2" ) ? static_cast<void> (0) : __assert_fail ("((Align & (Align-1)) == 0) && \"Expected Align to be a power of 2\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn250694/lib/Target/Mips/MipsISelLowering.cpp" , 1870, __PRETTY_FUNCTION__));
1871
1872	VAList = DAG.getNode(ISD::ADD, DL, VAList.getValueType(), VAList,
1873	DAG.getConstant(Align - 1, DL, VAList.getValueType()));
1874
1875	VAList = DAG.getNode(ISD::AND, DL, VAList.getValueType(), VAList,
1876	DAG.getConstant(-(int64_t)Align, DL,
1877	VAList.getValueType()));
1878	}
1879
1880	// Increment the pointer, VAList, to the next vaarg.
1881	auto &TD = DAG.getDataLayout();
1882	unsigned ArgSizeInBytes =
1883	TD.getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext()));
1884	SDValue Tmp3 = DAG.getNode(ISD::ADD, DL, VAList.getValueType(), VAList,
1885	DAG.getConstant(RoundUpToAlignment(ArgSizeInBytes,
1886	ArgSlotSizeInBytes),
1887	DL, VAList.getValueType()));
1888	// Store the incremented VAList to the legalized pointer
1889	Chain = DAG.getStore(VAListLoad.getValue(1), DL, Tmp3, VAListPtr,
1890	MachinePointerInfo(SV), false, false, 0);
1891
1892	// In big-endian mode we must adjust the pointer when the load size is smaller
1893	// than the argument slot size. We must also reduce the known alignment to
1894	// match. For example in the N64 ABI, we must add 4 bytes to the offset to get
1895	// the correct half of the slot, and reduce the alignment from 8 (slot
1896	// alignment) down to 4 (type alignment).
1897	if (!Subtarget.isLittle() && ArgSizeInBytes < ArgSlotSizeInBytes) {
1898	unsigned Adjustment = ArgSlotSizeInBytes - ArgSizeInBytes;
1899	VAList = DAG.getNode(ISD::ADD, DL, VAListPtr.getValueType(), VAList,
1900	DAG.getIntPtrConstant(Adjustment, DL));
1901	}
1902	// Load the actual argument out of the pointer VAList
1903	return DAG.getLoad(VT, DL, Chain, VAList, MachinePointerInfo(), false, false,
1904	false, 0);
1905	}
1906
1907	static SDValue lowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG,
1908	bool HasExtractInsert) {
1909	EVT TyX = Op.getOperand(0).getValueType();
1910	EVT TyY = Op.getOperand(1).getValueType();
1911	SDLoc DL(Op);
1912	SDValue Const1 = DAG.getConstant(1, DL, MVT::i32);
1913	SDValue Const31 = DAG.getConstant(31, DL, MVT::i32);
1914	SDValue Res;
1915
1916	// If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it
1917	// to i32.
1918	SDValue X = (TyX == MVT::f32) ?
1919	DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) :
1920	DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0),
1921	Const1);
1922	SDValue Y = (TyY == MVT::f32) ?
1923	DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(1)) :
1924	DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(1),
1925	Const1);
1926
1927	if (HasExtractInsert) {
1928	// ext E, Y, 31, 1 ; extract bit31 of Y
1929	// ins X, E, 31, 1 ; insert extracted bit at bit31 of X
1930	SDValue E = DAG.getNode(MipsISD::Ext, DL, MVT::i32, Y, Const31, Const1);
1931	Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, E, Const31, Const1, X);
1932	} else {
1933	// sll SllX, X, 1
1934	// srl SrlX, SllX, 1
1935	// srl SrlY, Y, 31
1936	// sll SllY, SrlX, 31
1937	// or Or, SrlX, SllY
1938	SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1);
1939	SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1);
1940	SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31);
1941	SDValue SllY = DAG.getNode(ISD::SHL, DL, MVT::i32, SrlY, Const31);
1942	Res = DAG.getNode(ISD::OR, DL, MVT::i32, SrlX, SllY);
1943	}
1944
1945	if (TyX == MVT::f32)
1946	return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Res);
1947
1948	SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
1949	Op.getOperand(0),
1950	DAG.getConstant(0, DL, MVT::i32));
1951	return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res);
1952	}
1953
1954	static SDValue lowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG,
1955	bool HasExtractInsert) {
1956	unsigned WidthX = Op.getOperand(0).getValueSizeInBits();
1957	unsigned WidthY = Op.getOperand(1).getValueSizeInBits();
1958	EVT TyX = MVT::getIntegerVT(WidthX), TyY = MVT::getIntegerVT(WidthY);
1959	SDLoc DL(Op);
1960	SDValue Const1 = DAG.getConstant(1, DL, MVT::i32);
1961
1962	// Bitcast to integer nodes.
1963	SDValue X = DAG.getNode(ISD::BITCAST, DL, TyX, Op.getOperand(0));
1964	SDValue Y = DAG.getNode(ISD::BITCAST, DL, TyY, Op.getOperand(1));
1965
1966	if (HasExtractInsert) {
1967	// ext E, Y, width(Y) - 1, 1 ; extract bit width(Y)-1 of Y
1968	// ins X, E, width(X) - 1, 1 ; insert extracted bit at bit width(X)-1 of X
1969	SDValue E = DAG.getNode(MipsISD::Ext, DL, TyY, Y,
1970	DAG.getConstant(WidthY - 1, DL, MVT::i32), Const1);
1971
1972	if (WidthX > WidthY)
1973	E = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, E);
1974	else if (WidthY > WidthX)
1975	E = DAG.getNode(ISD::TRUNCATE, DL, TyX, E);
1976
1977	SDValue I = DAG.getNode(MipsISD::Ins, DL, TyX, E,
1978	DAG.getConstant(WidthX - 1, DL, MVT::i32), Const1,
1979	X);
1980	return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), I);
1981	}
1982
1983	// (d)sll SllX, X, 1
1984	// (d)srl SrlX, SllX, 1
1985	// (d)srl SrlY, Y, width(Y)-1
1986	// (d)sll SllY, SrlX, width(Y)-1
1987	// or Or, SrlX, SllY
1988	SDValue SllX = DAG.getNode(ISD::SHL, DL, TyX, X, Const1);
1989	SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1);
1990	SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y,
1991	DAG.getConstant(WidthY - 1, DL, MVT::i32));
1992
1993	if (WidthX > WidthY)
1994	SrlY = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, SrlY);
1995	else if (WidthY > WidthX)
1996	SrlY = DAG.getNode(ISD::TRUNCATE, DL, TyX, SrlY);
1997
1998	SDValue SllY = DAG.getNode(ISD::SHL, DL, TyX, SrlY,
1999	DAG.getConstant(WidthX - 1, DL, MVT::i32));
2000	SDValue Or = DAG.getNode(ISD::OR, DL, TyX, SrlX, SllY);
2001	return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Or);
2002	}
2003
2004	SDValue
2005	MipsTargetLowering::lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
2006	if (Subtarget.isGP64bit())
2007	return lowerFCOPYSIGN64(Op, DAG, Subtarget.hasExtractInsert());
2008
2009	return lowerFCOPYSIGN32(Op, DAG, Subtarget.hasExtractInsert());
2010	}
2011
2012	SDValue MipsTargetLowering::
2013	lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
2014	// check the depth
2015	assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) &&(((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue () == 0) && "Frame address can only be determined for current frame." ) ? static_cast<void> (0) : __assert_fail ("(cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) && \"Frame address can only be determined for current frame.\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn250694/lib/Target/Mips/MipsISelLowering.cpp" , 2016, __PRETTY_FUNCTION__))
2016	"Frame address can only be determined for current frame.")(((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue () == 0) && "Frame address can only be determined for current frame." ) ? static_cast<void> (0) : __assert_fail ("(cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) && \"Frame address can only be determined for current frame.\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn250694/lib/Target/Mips/MipsISelLowering.cpp" , 2016, __PRETTY_FUNCTION__));
2017
2018	MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2019	MFI->setFrameAddressIsTaken(true);
2020	EVT VT = Op.getValueType();
2021	SDLoc DL(Op);
2022	SDValue FrameAddr = DAG.getCopyFromReg(
2023	DAG.getEntryNode(), DL, ABI.IsN64() ? Mips::FP_64 : Mips::FP, VT);
2024	return FrameAddr;
2025	}
2026
2027	SDValue MipsTargetLowering::lowerRETURNADDR(SDValue Op,
2028	SelectionDAG &DAG) const {
2029	if (verifyReturnAddressArgumentIsConstant(Op, DAG))
2030	return SDValue();
2031
2032	// check the depth
2033	assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) &&(((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue () == 0) && "Return address can be determined only for current frame." ) ? static_cast<void> (0) : __assert_fail ("(cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) && \"Return address can be determined only for current frame.\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn250694/lib/Target/Mips/MipsISelLowering.cpp" , 2034, __PRETTY_FUNCTION__))
2034	"Return address can be determined only for current frame.")(((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue () == 0) && "Return address can be determined only for current frame." ) ? static_cast<void> (0) : __assert_fail ("(cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) && \"Return address can be determined only for current frame.\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn250694/lib/Target/Mips/MipsISelLowering.cpp" , 2034, __PRETTY_FUNCTION__));
2035
2036	MachineFunction &MF = DAG.getMachineFunction();
2037	MachineFrameInfo *MFI = MF.getFrameInfo();
2038	MVT VT = Op.getSimpleValueType();
2039	unsigned RA = ABI.IsN64() ? Mips::RA_64 : Mips::RA;
2040	MFI->setReturnAddressIsTaken(true);
2041
2042	// Return RA, which contains the return address. Mark it an implicit live-in.
2043	unsigned Reg = MF.addLiveIn(RA, getRegClassFor(VT));
2044	return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(Op), Reg, VT);
2045	}
2046
2047	// An EH_RETURN is the result of lowering llvm.eh.return which in turn is
2048	// generated from __builtin_eh_return (offset, handler)
2049	// The effect of this is to adjust the stack pointer by "offset"
2050	// and then branch to "handler".
2051	SDValue MipsTargetLowering::lowerEH_RETURN(SDValue Op, SelectionDAG &DAG)
2052	const {
2053	MachineFunction &MF = DAG.getMachineFunction();
2054	MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
2055
2056	MipsFI->setCallsEhReturn();
2057	SDValue Chain = Op.getOperand(0);
2058	SDValue Offset = Op.getOperand(1);
2059	SDValue Handler = Op.getOperand(2);
2060	SDLoc DL(Op);
2061	EVT Ty = ABI.IsN64() ? MVT::i64 : MVT::i32;
2062
2063	// Store stack offset in V1, store jump target in V0. Glue CopyToReg and
2064	// EH_RETURN nodes, so that instructions are emitted back-to-back.
2065	unsigned OffsetReg = ABI.IsN64() ? Mips::V1_64 : Mips::V1;
2066	unsigned AddrReg = ABI.IsN64() ? Mips::V0_64 : Mips::V0;
2067	Chain = DAG.getCopyToReg(Chain, DL, OffsetReg, Offset, SDValue());
2068	Chain = DAG.getCopyToReg(Chain, DL, AddrReg, Handler, Chain.getValue(1));
2069	return DAG.getNode(MipsISD::EH_RETURN, DL, MVT::Other, Chain,
2070	DAG.getRegister(OffsetReg, Ty),
2071	DAG.getRegister(AddrReg, getPointerTy(MF.getDataLayout())),
2072	Chain.getValue(1));
2073	}
2074
2075	SDValue MipsTargetLowering::lowerATOMIC_FENCE(SDValue Op,
2076	SelectionDAG &DAG) const {
2077	// FIXME: Need pseudo-fence for 'singlethread' fences
2078	// FIXME: Set SType for weaker fences where supported/appropriate.
2079	unsigned SType = 0;
2080	SDLoc DL(Op);
2081	return DAG.getNode(MipsISD::Sync, DL, MVT::Other, Op.getOperand(0),
2082	DAG.getConstant(SType, DL, MVT::i32));
2083	}
2084
2085	SDValue MipsTargetLowering::lowerShiftLeftParts(SDValue Op,
2086	SelectionDAG &DAG) const {
2087	SDLoc DL(Op);
2088	MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32;
2089
2090	SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);
2091	SDValue Shamt = Op.getOperand(2);
2092	// if shamt < (VT.bits):
2093	// lo = (shl lo, shamt)
2094	// hi = (or (shl hi, shamt) (srl (srl lo, 1), ~shamt))
2095	// else:
2096	// lo = 0
2097	// hi = (shl lo, shamt[4:0])
2098	SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
2099	DAG.getConstant(-1, DL, MVT::i32));
2100	SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, VT, Lo,
2101	DAG.getConstant(1, DL, VT));
2102	SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, ShiftRight1Lo, Not);
2103	SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, Hi, Shamt);
2104	SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo);
2105	SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt);
2106	SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
2107	DAG.getConstant(VT.getSizeInBits(), DL, MVT::i32));
2108	Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond,
2109	DAG.getConstant(0, DL, VT), ShiftLeftLo);
2110	Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftLeftLo, Or);
2111
2112	SDValue Ops[2] = {Lo, Hi};
2113	return DAG.getMergeValues(Ops, DL);
2114	}
2115
2116	SDValue MipsTargetLowering::lowerShiftRightParts(SDValue Op, SelectionDAG &DAG,
2117	bool IsSRA) const {
2118	SDLoc DL(Op);
2119	SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);
2120	SDValue Shamt = Op.getOperand(2);
2121	MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32;
2122
2123	// if shamt < (VT.bits):
2124	// lo = (or (shl (shl hi, 1), ~shamt) (srl lo, shamt))
2125	// if isSRA:
2126	// hi = (sra hi, shamt)
2127	// else:
2128	// hi = (srl hi, shamt)
2129	// else:
2130	// if isSRA:
2131	// lo = (sra hi, shamt[4:0])
2132	// hi = (sra hi, 31)
2133	// else:
2134	// lo = (srl hi, shamt[4:0])
2135	// hi = 0
2136	SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
2137	DAG.getConstant(-1, DL, MVT::i32));
2138	SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, VT, Hi,
2139	DAG.getConstant(1, DL, VT));
2140	SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, ShiftLeft1Hi, Not);
2141	SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, Lo, Shamt);
2142	SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo);
2143	SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL,
2144	DL, VT, Hi, Shamt);
2145	SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
2146	DAG.getConstant(VT.getSizeInBits(), DL, MVT::i32));
2147	SDValue Ext = DAG.getNode(ISD::SRA, DL, VT, Hi,
2148	DAG.getConstant(VT.getSizeInBits() - 1, DL, VT));
2149	Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftRightHi, Or);
2150	Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond,
2151	IsSRA ? Ext : DAG.getConstant(0, DL, VT), ShiftRightHi);
2152
2153	SDValue Ops[2] = {Lo, Hi};
2154	return DAG.getMergeValues(Ops, DL);
2155	}
2156
2157	static SDValue createLoadLR(unsigned Opc, SelectionDAG &DAG, LoadSDNode *LD,
2158	SDValue Chain, SDValue Src, unsigned Offset) {
2159	SDValue Ptr = LD->getBasePtr();
2160	EVT VT = LD->getValueType(0), MemVT = LD->getMemoryVT();
2161	EVT BasePtrVT = Ptr.getValueType();
2162	SDLoc DL(LD);
2163	SDVTList VTList = DAG.getVTList(VT, MVT::Other);
2164
2165	if (Offset)
2166	Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr,
2167	DAG.getConstant(Offset, DL, BasePtrVT));
2168
2169	SDValue Ops[] = { Chain, Ptr, Src };
2170	return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT,
2171	LD->getMemOperand());
2172	}
2173
2174	// Expand an unaligned 32 or 64-bit integer load node.
2175	SDValue MipsTargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const {
2176	LoadSDNode *LD = cast<LoadSDNode>(Op);
2177	EVT MemVT = LD->getMemoryVT();
2178
2179	if (Subtarget.systemSupportsUnalignedAccess())
2180	return Op;
2181
2182	// Return if load is aligned or if MemVT is neither i32 nor i64.
2183	if ((LD->getAlignment() >= MemVT.getSizeInBits() / 8) \|\|
2184	((MemVT != MVT::i32) && (MemVT != MVT::i64)))
2185	return SDValue();
2186
2187	bool IsLittle = Subtarget.isLittle();
2188	EVT VT = Op.getValueType();
2189	ISD::LoadExtType ExtType = LD->getExtensionType();
2190	SDValue Chain = LD->getChain(), Undef = DAG.getUNDEF(VT);
2191
2192	assert((VT == MVT::i32) \|\| (VT == MVT::i64))(((VT == MVT::i32) \|\| (VT == MVT::i64)) ? static_cast<void > (0) : __assert_fail ("(VT == MVT::i32) \|\| (VT == MVT::i64)" , "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn250694/lib/Target/Mips/MipsISelLowering.cpp" , 2192, __PRETTY_FUNCTION__));
2193
2194	// Expand
2195	// (set dst, (i64 (load baseptr)))
2196	// to
2197	// (set tmp, (ldl (add baseptr, 7), undef))
2198	// (set dst, (ldr baseptr, tmp))
2199	if ((VT == MVT::i64) && (ExtType == ISD::NON_EXTLOAD)) {
2200	SDValue LDL = createLoadLR(MipsISD::LDL, DAG, LD, Chain, Undef,
2201	IsLittle ? 7 : 0);
2202	return createLoadLR(MipsISD::LDR, DAG, LD, LDL.getValue(1), LDL,
2203	IsLittle ? 0 : 7);
2204	}
2205
2206	SDValue LWL = createLoadLR(MipsISD::LWL, DAG, LD, Chain, Undef,
2207	IsLittle ? 3 : 0);
2208	SDValue LWR = createLoadLR(MipsISD::LWR, DAG, LD, LWL.getValue(1), LWL,
2209	IsLittle ? 0 : 3);
2210
2211	// Expand
2212	// (set dst, (i32 (load baseptr))) or
2213	// (set dst, (i64 (sextload baseptr))) or
2214	// (set dst, (i64 (extload baseptr)))
2215	// to
2216	// (set tmp, (lwl (add baseptr, 3), undef))
2217	// (set dst, (lwr baseptr, tmp))
2218	if ((VT == MVT::i32) \|\| (ExtType == ISD::SEXTLOAD) \|\|
2219	(ExtType == ISD::EXTLOAD))
2220	return LWR;
2221
2222	assert((VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD))(((VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD)) ? static_cast <void> (0) : __assert_fail ("(VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD)" , "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn250694/lib/Target/Mips/MipsISelLowering.cpp" , 2222, __PRETTY_FUNCTION__));
2223
2224	// Expand
2225	// (set dst, (i64 (zextload baseptr)))
2226	// to
2227	// (set tmp0, (lwl (add baseptr, 3), undef))
2228	// (set tmp1, (lwr baseptr, tmp0))
2229	// (set tmp2, (shl tmp1, 32))
2230	// (set dst, (srl tmp2, 32))
2231	SDLoc DL(LD);
2232	SDValue Const32 = DAG.getConstant(32, DL, MVT::i32);
2233	SDValue SLL = DAG.getNode(ISD::SHL, DL, MVT::i64, LWR, Const32);
2234	SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32);
2235	SDValue Ops[] = { SRL, LWR.getValue(1) };
2236	return DAG.getMergeValues(Ops, DL);
2237	}
2238
2239	static SDValue createStoreLR(unsigned Opc, SelectionDAG &DAG, StoreSDNode *SD,
2240	SDValue Chain, unsigned Offset) {
2241	SDValue Ptr = SD->getBasePtr(), Value = SD->getValue();
2242	EVT MemVT = SD->getMemoryVT(), BasePtrVT = Ptr.getValueType();
2243	SDLoc DL(SD);
2244	SDVTList VTList = DAG.getVTList(MVT::Other);
2245
2246	if (Offset)
2247	Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr,
2248	DAG.getConstant(Offset, DL, BasePtrVT));
2249
2250	SDValue Ops[] = { Chain, Value, Ptr };
2251	return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT,
2252	SD->getMemOperand());
2253	}
2254
2255	// Expand an unaligned 32 or 64-bit integer store node.
2256	static SDValue lowerUnalignedIntStore(StoreSDNode *SD, SelectionDAG &DAG,
2257	bool IsLittle) {
2258	SDValue Value = SD->getValue(), Chain = SD->getChain();
2259	EVT VT = Value.getValueType();
2260
2261	// Expand
2262	// (store val, baseptr) or
2263	// (truncstore val, baseptr)
2264	// to
2265	// (swl val, (add baseptr, 3))
2266	// (swr val, baseptr)
2267	if ((VT == MVT::i32) \|\| SD->isTruncatingStore()) {
2268	SDValue SWL = createStoreLR(MipsISD::SWL, DAG, SD, Chain,
2269	IsLittle ? 3 : 0);
2270	return createStoreLR(MipsISD::SWR, DAG, SD, SWL, IsLittle ? 0 : 3);
2271	}
2272
2273	assert(VT == MVT::i64)((VT == MVT::i64) ? static_cast<void> (0) : __assert_fail ("VT == MVT::i64", "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn250694/lib/Target/Mips/MipsISelLowering.cpp" , 2273, __PRETTY_FUNCTION__));
2274
2275	// Expand
2276	// (store val, baseptr)
2277	// to
2278	// (sdl val, (add baseptr, 7))
2279	// (sdr val, baseptr)
2280	SDValue SDL = createStoreLR(MipsISD::SDL, DAG, SD, Chain, IsLittle ? 7 : 0);
2281	return createStoreLR(MipsISD::SDR, DAG, SD, SDL, IsLittle ? 0 : 7);
2282	}
2283
2284	// Lower (store (fp_to_sint $fp) $ptr) to (store (TruncIntFP $fp), $ptr).
2285	static SDValue lowerFP_TO_SINT_STORE(StoreSDNode *SD, SelectionDAG &DAG) {
2286	SDValue Val = SD->getValue();
2287
2288	if (Val.getOpcode() != ISD::FP_TO_SINT)
2289	return SDValue();
2290
2291	EVT FPTy = EVT::getFloatingPointVT(Val.getValueSizeInBits());
2292	SDValue Tr = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Val), FPTy,
2293	Val.getOperand(0));
2294
2295	return DAG.getStore(SD->getChain(), SDLoc(SD), Tr, SD->getBasePtr(),
2296	SD->getPointerInfo(), SD->isVolatile(),
2297	SD->isNonTemporal(), SD->getAlignment());
2298	}
2299
2300	SDValue MipsTargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const {
2301	StoreSDNode *SD = cast<StoreSDNode>(Op);
2302	EVT MemVT = SD->getMemoryVT();
2303
2304	// Lower unaligned integer stores.
2305	if (!Subtarget.systemSupportsUnalignedAccess() &&
2306	(SD->getAlignment() < MemVT.getSizeInBits() / 8) &&
2307	((MemVT == MVT::i32) \|\| (MemVT == MVT::i64)))
2308	return lowerUnalignedIntStore(SD, DAG, Subtarget.isLittle());
2309
2310	return lowerFP_TO_SINT_STORE(SD, DAG);
2311	}
2312
2313	SDValue MipsTargetLowering::lowerADD(SDValue Op, SelectionDAG &DAG) const {
2314	if (Op->getOperand(0).getOpcode() != ISD::FRAMEADDR
2315	\|\| cast<ConstantSDNode>
2316	(Op->getOperand(0).getOperand(0))->getZExtValue() != 0
2317	\|\| Op->getOperand(1).getOpcode() != ISD::FRAME_TO_ARGS_OFFSET)
2318	return SDValue();
2319
2320	// The pattern
2321	// (add (frameaddr 0), (frame_to_args_offset))
2322	// results from lowering llvm.eh.dwarf.cfa intrinsic. Transform it to
2323	// (add FrameObject, 0)
2324	// where FrameObject is a fixed StackObject with offset 0 which points to
2325	// the old stack pointer.
2326	MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2327	EVT ValTy = Op->getValueType(0);
2328	int FI = MFI->CreateFixedObject(Op.getValueSizeInBits() / 8, 0, false);
2329	SDValue InArgsAddr = DAG.getFrameIndex(FI, ValTy);
2330	SDLoc DL(Op);
2331	return DAG.getNode(ISD::ADD, DL, ValTy, InArgsAddr,
2332	DAG.getConstant(0, DL, ValTy));
2333	}
2334
2335	SDValue MipsTargetLowering::lowerFP_TO_SINT(SDValue Op,
2336	SelectionDAG &DAG) const {
2337	EVT FPTy = EVT::getFloatingPointVT(Op.getValueSizeInBits());
2338	SDValue Trunc = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Op), FPTy,
2339	Op.getOperand(0));
2340	return DAG.getNode(ISD::BITCAST, SDLoc(Op), Op.getValueType(), Trunc);
2341	}
2342
2343	//===----------------------------------------------------------------------===//
2344	// Calling Convention Implementation
2345	//===----------------------------------------------------------------------===//
2346
2347	//===----------------------------------------------------------------------===//
2348	// TODO: Implement a generic logic using tblgen that can support this.
2349	// Mips O32 ABI rules:
2350	// ---
2351	// i32 - Passed in A0, A1, A2, A3 and stack
2352	// f32 - Only passed in f32 registers if no int reg has been used yet to hold
2353	// an argument. Otherwise, passed in A1, A2, A3 and stack.
2354	// f64 - Only passed in two aliased f32 registers if no int reg has been used
2355	// yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is
2356	// not used, it must be shadowed. If only A3 is available, shadow it and
2357	// go to stack.
2358	//
2359	// For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack.
2360	//===----------------------------------------------------------------------===//
2361
2362	static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT,
2363	CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
2364	CCState &State, ArrayRef<MCPhysReg> F64Regs) {
2365	const MipsSubtarget &Subtarget = static_cast<const MipsSubtarget &>(
2366	State.getMachineFunction().getSubtarget());
2367
2368	static const MCPhysReg IntRegs[] = { Mips::A0, Mips::A1, Mips::A2, Mips::A3 };
2369	static const MCPhysReg F32Regs[] = { Mips::F12, Mips::F14 };
2370
2371	// Do not process byval args here.
2372	if (ArgFlags.isByVal())
2373	return true;
2374
2375	// Promote i8 and i16
2376	if (ArgFlags.isInReg() && !Subtarget.isLittle()) {
2377	if (LocVT == MVT::i8 \|\| LocVT == MVT::i16 \|\| LocVT == MVT::i32) {
2378	LocVT = MVT::i32;
2379	if (ArgFlags.isSExt())
2380	LocInfo = CCValAssign::SExtUpper;
2381	else if (ArgFlags.isZExt())
2382	LocInfo = CCValAssign::ZExtUpper;
2383	else
2384	LocInfo = CCValAssign::AExtUpper;
2385	}
2386	}
2387
2388	// Promote i8 and i16
2389	if (LocVT == MVT::i8 \|\| LocVT == MVT::i16) {
2390	LocVT = MVT::i32;
2391	if (ArgFlags.isSExt())
2392	LocInfo = CCValAssign::SExt;
2393	else if (ArgFlags.isZExt())
2394	LocInfo = CCValAssign::ZExt;
2395	else
2396	LocInfo = CCValAssign::AExt;
2397	}
2398
2399	unsigned Reg;
2400
2401	// f32 and f64 are allocated in A0, A1, A2, A3 when either of the following
2402	// is true: function is vararg, argument is 3rd or higher, there is previous
2403	// argument which is not f32 or f64.
2404	bool AllocateFloatsInIntReg = State.isVarArg() \|\| ValNo > 1 \|\|
2405	State.getFirstUnallocated(F32Regs) != ValNo;
2406	unsigned OrigAlign = ArgFlags.getOrigAlign();
2407	bool isI64 = (ValVT == MVT::i32 && OrigAlign == 8);
2408
2409	if (ValVT == MVT::i32 \|\| (ValVT == MVT::f32 && AllocateFloatsInIntReg)) {
2410	Reg = State.AllocateReg(IntRegs);
2411	// If this is the first part of an i64 arg,
2412	// the allocated register must be either A0 or A2.
2413	if (isI64 && (Reg == Mips::A1 \|\| Reg == Mips::A3))
2414	Reg = State.AllocateReg(IntRegs);
2415	LocVT = MVT::i32;
2416	} else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) {
2417	// Allocate int register and shadow next int register. If first
2418	// available register is Mips::A1 or Mips::A3, shadow it too.
2419	Reg = State.AllocateReg(IntRegs);
2420	if (Reg == Mips::A1 \|\| Reg == Mips::A3)
2421	Reg = State.AllocateReg(IntRegs);
2422	State.AllocateReg(IntRegs);
2423	LocVT = MVT::i32;
2424	} else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) {
2425	// we are guaranteed to find an available float register
2426	if (ValVT == MVT::f32) {
2427	Reg = State.AllocateReg(F32Regs);
2428	// Shadow int register
2429	State.AllocateReg(IntRegs);
2430	} else {
2431	Reg = State.AllocateReg(F64Regs);
2432	// Shadow int registers
2433	unsigned Reg2 = State.AllocateReg(IntRegs);
2434	if (Reg2 == Mips::A1 \|\| Reg2 == Mips::A3)
2435	State.AllocateReg(IntRegs);
2436	State.AllocateReg(IntRegs);
2437	}
2438	} else
2439	llvm_unreachable("Cannot handle this ValVT.")::llvm::llvm_unreachable_internal("Cannot handle this ValVT." , "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn250694/lib/Target/Mips/MipsISelLowering.cpp" , 2439);
2440
2441	if (!Reg) {
2442	unsigned Offset = State.AllocateStack(ValVT.getSizeInBits() >> 3,
2443	OrigAlign);
2444	State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
2445	} else
2446	State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2447
2448	return false;
2449	}
2450
2451	static bool CC_MipsO32_FP32(unsigned ValNo, MVT ValVT,
2452	MVT LocVT, CCValAssign::LocInfo LocInfo,
2453	ISD::ArgFlagsTy ArgFlags, CCState &State) {
2454	static const MCPhysReg F64Regs[] = { Mips::D6, Mips::D7 };
2455
2456	return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs);
2457	}
2458
2459	static bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT,
2460	MVT LocVT, CCValAssign::LocInfo LocInfo,
2461	ISD::ArgFlagsTy ArgFlags, CCState &State) {
2462	static const MCPhysReg F64Regs[] = { Mips::D12_64, Mips::D14_64 };
2463
2464	return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs);
2465	}
2466
2467	static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT,
2468	CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
2469	CCState &State) LLVM_ATTRIBUTE_UNUSED__attribute__((__unused__));
2470
2471	#include "MipsGenCallingConv.inc"
2472
2473	//===----------------------------------------------------------------------===//
2474	// Call Calling Convention Implementation
2475	//===----------------------------------------------------------------------===//
2476
2477	// Return next O32 integer argument register.
2478	static unsigned getNextIntArgReg(unsigned Reg) {
2479	assert((Reg == Mips::A0) \|\| (Reg == Mips::A2))(((Reg == Mips::A0) \|\| (Reg == Mips::A2)) ? static_cast<void > (0) : __assert_fail ("(Reg == Mips::A0) \|\| (Reg == Mips::A2)" , "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn250694/lib/Target/Mips/MipsISelLowering.cpp" , 2479, __PRETTY_FUNCTION__));
2480	return (Reg == Mips::A0) ? Mips::A1 : Mips::A3;
2481	}
2482
2483	SDValue
2484	MipsTargetLowering::passArgOnStack(SDValue StackPtr, unsigned Offset,
2485	SDValue Chain, SDValue Arg, SDLoc DL,
2486	bool IsTailCall, SelectionDAG &DAG) const {
2487	if (!IsTailCall) {
2488	SDValue PtrOff =
2489	DAG.getNode(ISD::ADD, DL, getPointerTy(DAG.getDataLayout()), StackPtr,
2490	DAG.getIntPtrConstant(Offset, DL));
2491	return DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo(), false,
2492	false, 0);
2493	}
2494
2495	MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2496	int FI = MFI->CreateFixedObject(Arg.getValueSizeInBits() / 8, Offset, false);
2497	SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
2498	return DAG.getStore(Chain, DL, Arg, FIN, MachinePointerInfo(),
2499	/isVolatile=/ true, false, 0);
2500	}
2501
2502	void MipsTargetLowering::
2503	getOpndList(SmallVectorImpl<SDValue> &Ops,
2504	std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
2505	bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
2506	bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee,
2507	SDValue Chain) const {
2508	// Insert node "GP copy globalreg" before call to function.
2509	//
2510	// R_MIPS_CALL* operators (emitted when non-internal functions are called
2511	// in PIC mode) allow symbols to be resolved via lazy binding.
2512	// The lazy binding stub requires GP to point to the GOT.
2513	// Note that we don't need GP to point to the GOT for indirect calls
2514	// (when R_MIPS_CALL* is not used for the call) because Mips linker generates
2515	// lazy binding stub for a function only when R_MIPS_CALL* are the only relocs
2516	// used for the function (that is, Mips linker doesn't generate lazy binding
2517	// stub for a function whose address is taken in the program).
2518	if (IsPICCall && !InternalLinkage && IsCallReloc) {
2519	unsigned GPReg = ABI.IsN64() ? Mips::GP_64 : Mips::GP;
2520	EVT Ty = ABI.IsN64() ? MVT::i64 : MVT::i32;
2521	RegsToPass.push_back(std::make_pair(GPReg, getGlobalReg(CLI.DAG, Ty)));
2522	}
2523
2524	// Build a sequence of copy-to-reg nodes chained together with token
2525	// chain and flag operands which copy the outgoing args into registers.
2526	// The InFlag in necessary since all emitted instructions must be
2527	// stuck together.
2528	SDValue InFlag;
2529
2530	for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2531	Chain = CLI.DAG.getCopyToReg(Chain, CLI.DL, RegsToPass[i].first,
2532	RegsToPass[i].second, InFlag);
2533	InFlag = Chain.getValue(1);
2534	}
2535
2536	// Add argument registers to the end of the list so that they are
2537	// known live into the call.
2538	for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2539	Ops.push_back(CLI.DAG.getRegister(RegsToPass[i].first,
2540	RegsToPass[i].second.getValueType()));
2541
2542	// Add a register mask operand representing the call-preserved registers.
2543	const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
2544	const uint32_t *Mask =
2545	TRI->getCallPreservedMask(CLI.DAG.getMachineFunction(), CLI.CallConv);
2546	assert(Mask && "Missing call preserved mask for calling convention")((Mask && "Missing call preserved mask for calling convention" ) ? static_cast<void> (0) : __assert_fail ("Mask && \"Missing call preserved mask for calling convention\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn250694/lib/Target/Mips/MipsISelLowering.cpp" , 2546, __PRETTY_FUNCTION__));
2547	if (Subtarget.inMips16HardFloat()) {
2548	if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(CLI.Callee)) {
2549	llvm::StringRef Sym = G->getGlobal()->getName();
2550	Function *F = G->getGlobal()->getParent()->getFunction(Sym);
2551	if (F && F->hasFnAttribute("__Mips16RetHelper")) {
2552	Mask = MipsRegisterInfo::getMips16RetHelperMask();
2553	}
2554	}
2555	}
2556	Ops.push_back(CLI.DAG.getRegisterMask(Mask));
2557
2558	if (InFlag.getNode())
2559	Ops.push_back(InFlag);
2560	}
2561
2562	/// LowerCall - functions arguments are copied from virtual regs to
2563	/// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
2564	SDValue
2565	MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2566	SmallVectorImpl<SDValue> &InVals) const {
2567	SelectionDAG &DAG = CLI.DAG;
2568	SDLoc DL = CLI.DL;
2569	SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2570	SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2571	SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2572	SDValue Chain = CLI.Chain;
2573	SDValue Callee = CLI.Callee;
2574	bool &IsTailCall = CLI.IsTailCall;
2575	CallingConv::ID CallConv = CLI.CallConv;
2576	bool IsVarArg = CLI.IsVarArg;
2577
2578	MachineFunction &MF = DAG.getMachineFunction();
2579	MachineFrameInfo *MFI = MF.getFrameInfo();
2580	const TargetFrameLowering *TFL = Subtarget.getFrameLowering();
2581	MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
2582	bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
2583
2584	// Analyze operands of the call, assigning locations to each operand.
2585	SmallVector<CCValAssign, 16> ArgLocs;
2586	MipsCCState CCInfo(
2587	CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, *DAG.getContext(),
2588	MipsCCState::getSpecialCallingConvForCallee(Callee.getNode(), Subtarget));
2589
2590	// Allocate the reserved argument area. It seems strange to do this from the
2591	// caller side but removing it breaks the frame size calculation.
2592	CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(CallConv), 1);
2593
2594	CCInfo.AnalyzeCallOperands(Outs, CC_Mips, CLI.getArgs(), Callee.getNode());
2595
2596	// Get a count of how many bytes are to be pushed on the stack.
2597	unsigned NextStackOffset = CCInfo.getNextStackOffset();
2598
2599	// Check if it's really possible to do a tail call.
2600	if (IsTailCall)
2601	IsTailCall = isEligibleForTailCallOptimization(
2602	CCInfo, NextStackOffset, *MF.getInfo<MipsFunctionInfo>());
2603
2604	if (!IsTailCall && CLI.CS && CLI.CS->isMustTailCall())
2605	report_fatal_error("failed to perform tail call elimination on a call "
2606	"site marked musttail");
2607
2608	if (IsTailCall)
2609	++NumTailCalls;
2610
2611	// Chain is the output chain of the last Load/Store or CopyToReg node.
2612	// ByValChain is the output chain of the last Memcpy node created for copying
2613	// byval arguments to the stack.
2614	unsigned StackAlignment = TFL->getStackAlignment();
2615	NextStackOffset = RoundUpToAlignment(NextStackOffset, StackAlignment);
2616	SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, DL, true);
2617
2618	if (!IsTailCall)
2619	Chain = DAG.getCALLSEQ_START(Chain, NextStackOffsetVal, DL);
2620
2621	SDValue StackPtr =
2622	DAG.getCopyFromReg(Chain, DL, ABI.IsN64() ? Mips::SP_64 : Mips::SP,
2623	getPointerTy(DAG.getDataLayout()));
2624
2625	// With EABI is it possible to have 16 args on registers.
2626	std::deque< std::pair<unsigned, SDValue> > RegsToPass;
2627	SmallVector<SDValue, 8> MemOpChains;
2628
2629	CCInfo.rewindByValRegsInfo();
2630
2631	// Walk the register/memloc assignments, inserting copies/loads.
2632	for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2633	SDValue Arg = OutVals[i];
2634	CCValAssign &VA = ArgLocs[i];
2635	MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT();
2636	ISD::ArgFlagsTy Flags = Outs[i].Flags;
2637	bool UseUpperBits = false;
2638
2639	// ByVal Arg.
2640	if (Flags.isByVal()) {
2641	unsigned FirstByValReg, LastByValReg;
2642	unsigned ByValIdx = CCInfo.getInRegsParamsProcessed();
2643	CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg);
2644
2645	assert(Flags.getByValSize() &&((Flags.getByValSize() && "ByVal args of size 0 should have been ignored by front-end." ) ? static_cast<void> (0) : __assert_fail ("Flags.getByValSize() && \"ByVal args of size 0 should have been ignored by front-end.\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn250694/lib/Target/Mips/MipsISelLowering.cpp" , 2646, __PRETTY_FUNCTION__))
2646	"ByVal args of size 0 should have been ignored by front-end.")((Flags.getByValSize() && "ByVal args of size 0 should have been ignored by front-end." ) ? static_cast<void> (0) : __assert_fail ("Flags.getByValSize() && \"ByVal args of size 0 should have been ignored by front-end.\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn250694/lib/Target/Mips/MipsISelLowering.cpp" , 2646, __PRETTY_FUNCTION__));
2647	assert(ByValIdx < CCInfo.getInRegsParamsCount())((ByValIdx < CCInfo.getInRegsParamsCount()) ? static_cast< void> (0) : __assert_fail ("ByValIdx < CCInfo.getInRegsParamsCount()" , "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn250694/lib/Target/Mips/MipsISelLowering.cpp" , 2647, __PRETTY_FUNCTION__));
2648	assert(!IsTailCall &&((!IsTailCall && "Do not tail-call optimize if there is a byval argument." ) ? static_cast<void> (0) : __assert_fail ("!IsTailCall && \"Do not tail-call optimize if there is a byval argument.\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn250694/lib/Target/Mips/MipsISelLowering.cpp" , 2649, __PRETTY_FUNCTION__))
2649	"Do not tail-call optimize if there is a byval argument.")((!IsTailCall && "Do not tail-call optimize if there is a byval argument." ) ? static_cast<void> (0) : __assert_fail ("!IsTailCall && \"Do not tail-call optimize if there is a byval argument.\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn250694/lib/Target/Mips/MipsISelLowering.cpp" , 2649, __PRETTY_FUNCTION__));
2650	passByValArg(Chain, DL, RegsToPass, MemOpChains, StackPtr, MFI, DAG, Arg,
2651	FirstByValReg, LastByValReg, Flags, Subtarget.isLittle(),
2652	VA);
2653	CCInfo.nextInRegsParam();
2654	continue;
2655	}
2656
2657	// Promote the value if needed.
2658	switch (VA.getLocInfo()) {
2659	default:
2660	llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn250694/lib/Target/Mips/MipsISelLowering.cpp" , 2660);
2661	case CCValAssign::Full:
2662	if (VA.isRegLoc()) {
2663	if ((ValVT == MVT::f32 && LocVT == MVT::i32) \|\|
2664	(ValVT == MVT::f64 && LocVT == MVT::i64) \|\|
2665	(ValVT == MVT::i64 && LocVT == MVT::f64))
2666	Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg);
2667	else if (ValVT == MVT::f64 && LocVT == MVT::i32) {
2668	SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
2669	Arg, DAG.getConstant(0, DL, MVT::i32));
2670	SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
2671	Arg, DAG.getConstant(1, DL, MVT::i32));
2672	if (!Subtarget.isLittle())
2673	std::swap(Lo, Hi);
2674	unsigned LocRegLo = VA.getLocReg();
2675	unsigned LocRegHigh = getNextIntArgReg(LocRegLo);
2676	RegsToPass.push_back(std::make_pair(LocRegLo, Lo));
2677	RegsToPass.push_back(std::make_pair(LocRegHigh, Hi));
2678	continue;
2679	}
2680	}
2681	break;
2682	case CCValAssign::BCvt:
2683	Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg);
2684	break;
2685	case CCValAssign::SExtUpper:
2686	UseUpperBits = true;
2687	// Fallthrough
2688	case CCValAssign::SExt:
2689	Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, LocVT, Arg);
2690	break;
2691	case CCValAssign::ZExtUpper:
2692	UseUpperBits = true;
2693	// Fallthrough
2694	case CCValAssign::ZExt:
2695	Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, LocVT, Arg);
2696	break;
2697	case CCValAssign::AExtUpper:
2698	UseUpperBits = true;
2699	// Fallthrough
2700	case CCValAssign::AExt:
2701	Arg = DAG.getNode(ISD::ANY_EXTEND, DL, LocVT, Arg);
2702	break;
2703	}
2704
2705	if (UseUpperBits) {
2706	unsigned ValSizeInBits = Outs[i].ArgVT.getSizeInBits();
2707	unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
2708	Arg = DAG.getNode(
2709	ISD::SHL, DL, VA.getLocVT(), Arg,
2710	DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT()));
2711	}
2712
2713	// Arguments that can be passed on register must be kept at
2714	// RegsToPass vector
2715	if (VA.isRegLoc()) {
2716	RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2717	continue;
2718	}
2719
2720	// Register can't get to this point...
2721	assert(VA.isMemLoc())((VA.isMemLoc()) ? static_cast<void> (0) : __assert_fail ("VA.isMemLoc()", "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn250694/lib/Target/Mips/MipsISelLowering.cpp" , 2721, __PRETTY_FUNCTION__));
2722
2723	// emit ISD::STORE whichs stores the
2724	// parameter value to a stack Location
2725	MemOpChains.push_back(passArgOnStack(StackPtr, VA.getLocMemOffset(),
2726	Chain, Arg, DL, IsTailCall, DAG));
2727	}
2728
2729	// Transform all store nodes into one single node because all store
2730	// nodes are independent of each other.
2731	if (!MemOpChains.empty())
2732	Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
2733
2734	// If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
2735	// direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
2736	// node so that legalize doesn't hack it.
2737	bool IsPICCall = (ABI.IsN64() \|\| IsPIC); // true if calls are translated to
2738	// jalr $25
2739	bool GlobalOrExternal = false, InternalLinkage = false, IsCallReloc = false;
2740	SDValue CalleeLo;
2741	EVT Ty = Callee.getValueType();
2742
2743	if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2744	if (IsPICCall) {
2745	const GlobalValue *Val = G->getGlobal();
2746	InternalLinkage = Val->hasInternalLinkage();
2747
2748	if (InternalLinkage)
2749	Callee = getAddrLocal(G, DL, Ty, DAG, ABI.IsN32() \|\| ABI.IsN64());
2750	else if (LargeGOT) {
2751	Callee = getAddrGlobalLargeGOT(G, DL, Ty, DAG, MipsII::MO_CALL_HI16,
2752	MipsII::MO_CALL_LO16, Chain,
2753	FuncInfo->callPtrInfo(Val));
2754	IsCallReloc = true;
2755	} else {
2756	Callee = getAddrGlobal(G, DL, Ty, DAG, MipsII::MO_GOT_CALL, Chain,
2757	FuncInfo->callPtrInfo(Val));
2758	IsCallReloc = true;
2759	}
2760	} else
2761	Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL,
2762	getPointerTy(DAG.getDataLayout()), 0,
2763	MipsII::MO_NO_FLAG);
2764	GlobalOrExternal = true;
2765	}
2766	else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2767	const char *Sym = S->getSymbol();
2768
2769	if (!ABI.IsN64() && !IsPIC) // !N64 && static
2770	Callee = DAG.getTargetExternalSymbol(
2771	Sym, getPointerTy(DAG.getDataLayout()), MipsII::MO_NO_FLAG);
2772	else if (LargeGOT) {
2773	Callee = getAddrGlobalLargeGOT(S, DL, Ty, DAG, MipsII::MO_CALL_HI16,
2774	MipsII::MO_CALL_LO16, Chain,
2775	FuncInfo->callPtrInfo(Sym));
2776	IsCallReloc = true;
2777	} else { // N64 \|\| PIC
2778	Callee = getAddrGlobal(S, DL, Ty, DAG, MipsII::MO_GOT_CALL, Chain,
2779	FuncInfo->callPtrInfo(Sym));
2780	IsCallReloc = true;
2781	}
2782
2783	GlobalOrExternal = true;
2784	}
2785
2786	SmallVector<SDValue, 8> Ops(1, Chain);
2787	SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2788
2789	getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal, InternalLinkage,
2790	IsCallReloc, CLI, Callee, Chain);
2791
2792	if (IsTailCall)
2793	return DAG.getNode(MipsISD::TailCall, DL, MVT::Other, Ops);
2794
2795	Chain = DAG.getNode(MipsISD::JmpLink, DL, NodeTys, Ops);
2796	SDValue InFlag = Chain.getValue(1);
2797
2798	// Create the CALLSEQ_END node.
2799	Chain = DAG.getCALLSEQ_END(Chain, NextStackOffsetVal,
2800	DAG.getIntPtrConstant(0, DL, true), InFlag, DL);
2801	InFlag = Chain.getValue(1);
2802
2803	// Handle result values, copying them out of physregs into vregs that we
2804	// return.
2805	return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG,
2806	InVals, CLI);
2807	}
2808
2809	/// LowerCallResult - Lower the result values of a call into the
2810	/// appropriate copies out of appropriate physical registers.
2811	SDValue MipsTargetLowering::LowerCallResult(
2812	SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool IsVarArg,
2813	const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG,
2814	SmallVectorImpl<SDValue> &InVals,
2815	TargetLowering::CallLoweringInfo &CLI) const {
2816	// Assign locations to each value returned by this call.
2817	SmallVector<CCValAssign, 16> RVLocs;
2818	MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
2819	*DAG.getContext());
2820	CCInfo.AnalyzeCallResult(Ins, RetCC_Mips, CLI);
2821
2822	// Copy all of the result registers out of their specified physreg.
2823	for (unsigned i = 0; i != RVLocs.size(); ++i) {
2824	CCValAssign &VA = RVLocs[i];
2825	assert(VA.isRegLoc() && "Can only return in registers!")((VA.isRegLoc() && "Can only return in registers!") ? static_cast<void> (0) : __assert_fail ("VA.isRegLoc() && \"Can only return in registers!\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn250694/lib/Target/Mips/MipsISelLowering.cpp" , 2825, __PRETTY_FUNCTION__));
2826
2827	SDValue Val = DAG.getCopyFromReg(Chain, DL, RVLocs[i].getLocReg(),
2828	RVLocs[i].getLocVT(), InFlag);
2829	Chain = Val.getValue(1);
2830	InFlag = Val.getValue(2);
2831
2832	if (VA.isUpperBitsInLoc()) {
2833	unsigned ValSizeInBits = Ins[i].ArgVT.getSizeInBits();
2834	unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
2835	unsigned Shift =
2836	VA.getLocInfo() == CCValAssign::ZExtUpper ? ISD::SRL : ISD::SRA;
2837	Val = DAG.getNode(
2838	Shift, DL, VA.getLocVT(), Val,
2839	DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT()));
2840	}
2841
2842	switch (VA.getLocInfo()) {
2843	default:
2844	llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn250694/lib/Target/Mips/MipsISelLowering.cpp" , 2844);
2845	case CCValAssign::Full:
2846	break;
2847	case CCValAssign::BCvt:
2848	Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val);
2849	break;
2850	case CCValAssign::AExt:
2851	case CCValAssign::AExtUpper:
2852	Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
2853	break;
2854	case CCValAssign::ZExt:
2855	case CCValAssign::ZExtUpper:
2856	Val = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Val,
2857	DAG.getValueType(VA.getValVT()));
2858	Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
2859	break;
2860	case CCValAssign::SExt:
2861	case CCValAssign::SExtUpper:
2862	Val = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Val,
2863	DAG.getValueType(VA.getValVT()));
2864	Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
2865	break;
2866	}
2867
2868	InVals.push_back(Val);
2869	}
2870
2871	return Chain;
2872	}
2873
2874	static SDValue UnpackFromArgumentSlot(SDValue Val, const CCValAssign &VA,
2875	EVT ArgVT, SDLoc DL, SelectionDAG &DAG) {
2876	MVT LocVT = VA.getLocVT();
2877	EVT ValVT = VA.getValVT();
2878
2879	// Shift into the upper bits if necessary.
2880	switch (VA.getLocInfo()) {
2881	default:
2882	break;
2883	case CCValAssign::AExtUpper:
2884	case CCValAssign::SExtUpper:
2885	case CCValAssign::ZExtUpper: {
2886	unsigned ValSizeInBits = ArgVT.getSizeInBits();
2887	unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
2888	unsigned Opcode =
2889	VA.getLocInfo() == CCValAssign::ZExtUpper ? ISD::SRL : ISD::SRA;
2890	Val = DAG.getNode(
2891	Opcode, DL, VA.getLocVT(), Val,
2892	DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT()));
2893	break;
2894	}
2895	}
2896
2897	// If this is an value smaller than the argument slot size (32-bit for O32,
2898	// 64-bit for N32/N64), it has been promoted in some way to the argument slot
2899	// size. Extract the value and insert any appropriate assertions regarding
2900	// sign/zero extension.
2901	switch (VA.getLocInfo()) {
2902	default:
2903	llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn250694/lib/Target/Mips/MipsISelLowering.cpp" , 2903);
2904	case CCValAssign::Full:
2905	break;
2906	case CCValAssign::AExtUpper:
2907	case CCValAssign::AExt:
2908	Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val);
2909	break;
2910	case CCValAssign::SExtUpper:
2911	case CCValAssign::SExt:
2912	Val = DAG.getNode(ISD::AssertSext, DL, LocVT, Val, DAG.getValueType(ValVT));
2913	Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val);
2914	break;
2915	case CCValAssign::ZExtUpper:
2916	case CCValAssign::ZExt:
2917	Val = DAG.getNode(ISD::AssertZext, DL, LocVT, Val, DAG.getValueType(ValVT));
2918	Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val);
2919	break;
2920	case CCValAssign::BCvt:
2921	Val = DAG.getNode(ISD::BITCAST, DL, ValVT, Val);
2922	break;
2923	}
2924
2925	return Val;
2926	}
2927
2928	//===----------------------------------------------------------------------===//
2929	// Formal Arguments Calling Convention Implementation
2930	//===----------------------------------------------------------------------===//
2931	/// LowerFormalArguments - transform physical registers into virtual registers
2932	/// and generate load operations for arguments places on the stack.
2933	SDValue
2934	MipsTargetLowering::LowerFormalArguments(SDValue Chain,
2935	CallingConv::ID CallConv,
2936	bool IsVarArg,
2937	const SmallVectorImpl<ISD::InputArg> &Ins,
2938	SDLoc DL, SelectionDAG &DAG,
2939	SmallVectorImpl<SDValue> &InVals)
2940	const {
2941	MachineFunction &MF = DAG.getMachineFunction();
2942	MachineFrameInfo *MFI = MF.getFrameInfo();
2943	MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
2944
2945	MipsFI->setVarArgsFrameIndex(0);
2946
2947	// Used with vargs to acumulate store chains.
2948	std::vector<SDValue> OutChains;
2949
2950	// Assign locations to all of the incoming arguments.
2951	SmallVector<CCValAssign, 16> ArgLocs;
2952	MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
2953	*DAG.getContext());
2954	CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(CallConv), 1);
2955	Function::const_arg_iterator FuncArg =
2956	DAG.getMachineFunction().getFunction()->arg_begin();
2957
2958	CCInfo.AnalyzeFormalArguments(Ins, CC_Mips_FixedArg);
2959	MipsFI->setFormalArgInfo(CCInfo.getNextStackOffset(),
2960	CCInfo.getInRegsParamsCount() > 0);
2961
2962	unsigned CurArgIdx = 0;
2963	CCInfo.rewindByValRegsInfo();
2964
2965	for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2966	CCValAssign &VA = ArgLocs[i];
2967	if (Ins[i].isOrigArg()) {
2968	std::advance(FuncArg, Ins[i].getOrigArgIndex() - CurArgIdx);
2969	CurArgIdx = Ins[i].getOrigArgIndex();
2970	}
2971	EVT ValVT = VA.getValVT();
2972	ISD::ArgFlagsTy Flags = Ins[i].Flags;
2973	bool IsRegLoc = VA.isRegLoc();
2974
2975	if (Flags.isByVal()) {
2976	assert(Ins[i].isOrigArg() && "Byval arguments cannot be implicit")((Ins[i].isOrigArg() && "Byval arguments cannot be implicit" ) ? static_cast<void> (0) : __assert_fail ("Ins[i].isOrigArg() && \"Byval arguments cannot be implicit\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn250694/lib/Target/Mips/MipsISelLowering.cpp" , 2976, __PRETTY_FUNCTION__));
2977	unsigned FirstByValReg, LastByValReg;
2978	unsigned ByValIdx = CCInfo.getInRegsParamsProcessed();
2979	CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg);
2980
2981	assert(Flags.getByValSize() &&((Flags.getByValSize() && "ByVal args of size 0 should have been ignored by front-end." ) ? static_cast<void> (0) : __assert_fail ("Flags.getByValSize() && \"ByVal args of size 0 should have been ignored by front-end.\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn250694/lib/Target/Mips/MipsISelLowering.cpp" , 2982, __PRETTY_FUNCTION__))
2982	"ByVal args of size 0 should have been ignored by front-end.")((Flags.getByValSize() && "ByVal args of size 0 should have been ignored by front-end." ) ? static_cast<void> (0) : __assert_fail ("Flags.getByValSize() && \"ByVal args of size 0 should have been ignored by front-end.\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn250694/lib/Target/Mips/MipsISelLowering.cpp" , 2982, __PRETTY_FUNCTION__));
2983	assert(ByValIdx < CCInfo.getInRegsParamsCount())((ByValIdx < CCInfo.getInRegsParamsCount()) ? static_cast< void> (0) : __assert_fail ("ByValIdx < CCInfo.getInRegsParamsCount()" , "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn250694/lib/Target/Mips/MipsISelLowering.cpp" , 2983, __PRETTY_FUNCTION__));
2984	copyByValRegs(Chain, DL, OutChains, DAG, Flags, InVals, &*FuncArg,
2985	FirstByValReg, LastByValReg, VA, CCInfo);
2986	CCInfo.nextInRegsParam();
2987	continue;
2988	}
2989
2990	// Arguments stored on registers
2991	if (IsRegLoc) {
2992	MVT RegVT = VA.getLocVT();
2993	unsigned ArgReg = VA.getLocReg();
2994	const TargetRegisterClass *RC = getRegClassFor(RegVT);
2995
2996	// Transform the arguments stored on
2997	// physical registers into virtual ones
2998	unsigned Reg = addLiveIn(DAG.getMachineFunction(), ArgReg, RC);
2999	SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT);
3000
3001	ArgValue = UnpackFromArgumentSlot(ArgValue, VA, Ins[i].ArgVT, DL, DAG);
3002
3003	// Handle floating point arguments passed in integer registers and
3004	// long double arguments passed in floating point registers.
3005	if ((RegVT == MVT::i32 && ValVT == MVT::f32) \|\|
3006	(RegVT == MVT::i64 && ValVT == MVT::f64) \|\|
3007	(RegVT == MVT::f64 && ValVT == MVT::i64))
3008	ArgValue = DAG.getNode(ISD::BITCAST, DL, ValVT, ArgValue);
3009	else if (ABI.IsO32() && RegVT == MVT::i32 &&
3010	ValVT == MVT::f64) {
3011	unsigned Reg2 = addLiveIn(DAG.getMachineFunction(),
3012	getNextIntArgReg(ArgReg), RC);
3013	SDValue ArgValue2 = DAG.getCopyFromReg(Chain, DL, Reg2, RegVT);
3014	if (!Subtarget.isLittle())
3015	std::swap(ArgValue, ArgValue2);
3016	ArgValue = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64,
3017	ArgValue, ArgValue2);
3018	}
3019
3020	InVals.push_back(ArgValue);
3021	} else { // VA.isRegLoc()
3022	MVT LocVT = VA.getLocVT();
3023
3024	if (ABI.IsO32()) {
3025	// We ought to be able to use LocVT directly but O32 sets it to i32
3026	// when allocating floating point values to integer registers.
3027	// This shouldn't influence how we load the value into registers unless
3028	// we are targeting softfloat.
3029	if (VA.getValVT().isFloatingPoint() && !Subtarget.useSoftFloat())
3030	LocVT = VA.getValVT();
3031	}
3032
3033	// sanity check
3034	assert(VA.isMemLoc())((VA.isMemLoc()) ? static_cast<void> (0) : __assert_fail ("VA.isMemLoc()", "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn250694/lib/Target/Mips/MipsISelLowering.cpp" , 3034, __PRETTY_FUNCTION__));
3035
3036	// The stack pointer offset is relative to the caller stack frame.
3037	int FI = MFI->CreateFixedObject(LocVT.getSizeInBits() / 8,
3038	VA.getLocMemOffset(), true);
3039
3040	// Create load nodes to retrieve arguments from the stack
3041	SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
3042	SDValue ArgValue = DAG.getLoad(
3043	LocVT, DL, Chain, FIN,
3044	MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI),
3045	false, false, false, 0);
3046	OutChains.push_back(ArgValue.getValue(1));
3047
3048	ArgValue = UnpackFromArgumentSlot(ArgValue, VA, Ins[i].ArgVT, DL, DAG);
3049
3050	InVals.push_back(ArgValue);
3051	}
3052	}
3053
3054	for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3055	// The mips ABIs for returning structs by value requires that we copy
3056	// the sret argument into $v0 for the return. Save the argument into
3057	// a virtual register so that we can access it from the return points.
3058	if (Ins[i].Flags.isSRet()) {
3059	unsigned Reg = MipsFI->getSRetReturnReg();
3060	if (!Reg) {
3061	Reg = MF.getRegInfo().createVirtualRegister(
3062	getRegClassFor(ABI.IsN64() ? MVT::i64 : MVT::i32));
3063	MipsFI->setSRetReturnReg(Reg);
3064	}
3065	SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), DL, Reg, InVals[i]);
3066	Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Copy, Chain);
3067	break;
3068	}
3069	}
3070
3071	if (IsVarArg)
3072	writeVarArgRegs(OutChains, Chain, DL, DAG, CCInfo);
3073
3074	// All stores are grouped in one node to allow the matching between
3075	// the size of Ins and InVals. This only happens when on varg functions
3076	if (!OutChains.empty()) {
3077	OutChains.push_back(Chain);
3078	Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains);
3079	}
3080
3081	return Chain;
3082	}
3083
3084	//===----------------------------------------------------------------------===//
3085	// Return Value Calling Convention Implementation
3086	//===----------------------------------------------------------------------===//
3087
3088	bool
3089	MipsTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
3090	MachineFunction &MF, bool IsVarArg,
3091	const SmallVectorImpl<ISD::OutputArg> &Outs,
3092	LLVMContext &Context) const {
3093	SmallVector<CCValAssign, 16> RVLocs;
3094	MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
3095	return CCInfo.CheckReturn(Outs, RetCC_Mips);
3096	}
3097
3098	bool
3099	MipsTargetLowering::shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const {
3100	if (Subtarget.hasMips3() && Subtarget.useSoftFloat()) {
3101	if (Type == MVT::i32)
3102	return true;
3103	}
3104	return IsSigned;
3105	}
3106
3107	SDValue
3108	MipsTargetLowering::LowerReturn(SDValue Chain,
3109	CallingConv::ID CallConv, bool IsVarArg,
3110	const SmallVectorImpl<ISD::OutputArg> &Outs,
3111	const SmallVectorImpl<SDValue> &OutVals,
3112	SDLoc DL, SelectionDAG &DAG) const {
3113	// CCValAssign - represent the assignment of
3114	// the return value to a location
3115	SmallVector<CCValAssign, 16> RVLocs;
3116	MachineFunction &MF = DAG.getMachineFunction();
3117
3118	// CCState - Info about the registers and stack slot.
3119	MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext());
3120
3121	// Analyze return values.
3122	CCInfo.AnalyzeReturn(Outs, RetCC_Mips);
3123
3124	SDValue Flag;
3125	SmallVector<SDValue, 4> RetOps(1, Chain);
3126
3127	// Copy the result values into the output registers.
3128	for (unsigned i = 0; i != RVLocs.size(); ++i) {
3129	SDValue Val = OutVals[i];
3130	CCValAssign &VA = RVLocs[i];
3131	assert(VA.isRegLoc() && "Can only return in registers!")((VA.isRegLoc() && "Can only return in registers!") ? static_cast<void> (0) : __assert_fail ("VA.isRegLoc() && \"Can only return in registers!\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn250694/lib/Target/Mips/MipsISelLowering.cpp" , 3131, __PRETTY_FUNCTION__));
3132	bool UseUpperBits = false;
3133
3134	switch (VA.getLocInfo()) {
3135	default:
3136	llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn250694/lib/Target/Mips/MipsISelLowering.cpp" , 3136);
3137	case CCValAssign::Full:
3138	break;
3139	case CCValAssign::BCvt:
3140	Val = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Val);
3141	break;
3142	case CCValAssign::AExtUpper:
3143	UseUpperBits = true;
3144	// Fallthrough
3145	case CCValAssign::AExt:
3146	Val = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Val);
3147	break;
3148	case CCValAssign::ZExtUpper:
3149	UseUpperBits = true;
3150	// Fallthrough
3151	case CCValAssign::ZExt:
3152	Val = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Val);
3153	break;
3154	case CCValAssign::SExtUpper:
3155	UseUpperBits = true;
3156	// Fallthrough
3157	case CCValAssign::SExt:
3158	Val = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Val);
3159	break;
3160	}
3161
3162	if (UseUpperBits) {
3163	unsigned ValSizeInBits = Outs[i].ArgVT.getSizeInBits();
3164	unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
3165	Val = DAG.getNode(
3166	ISD::SHL, DL, VA.getLocVT(), Val,
3167	DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT()));
3168	}
3169
3170	Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Flag);
3171
3172	// Guarantee that all emitted copies are stuck together with flags.
3173	Flag = Chain.getValue(1);
3174	RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
3175	}
3176
3177	// The mips ABIs for returning structs by value requires that we copy
3178	// the sret argument into $v0 for the return. We saved the argument into
3179	// a virtual register in the entry block, so now we copy the value out
3180	// and into $v0.
3181	if (MF.getFunction()->hasStructRetAttr()) {
3182	MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
3183	unsigned Reg = MipsFI->getSRetReturnReg();
3184
3185	if (!Reg)
3186	llvm_unreachable("sret virtual register not created in the entry block")::llvm::llvm_unreachable_internal("sret virtual register not created in the entry block" , "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn250694/lib/Target/Mips/MipsISelLowering.cpp" , 3186);
3187	SDValue Val =
3188	DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(DAG.getDataLayout()));
3189	unsigned V0 = ABI.IsN64() ? Mips::V0_64 : Mips::V0;
3190
3191	Chain = DAG.getCopyToReg(Chain, DL, V0, Val, Flag);
3192	Flag = Chain.getValue(1);
3193	RetOps.push_back(DAG.getRegister(V0, getPointerTy(DAG.getDataLayout())));
3194	}
3195
3196	RetOps[0] = Chain; // Update chain.
3197
3198	// Add the flag if we have it.
3199	if (Flag.getNode())
3200	RetOps.push_back(Flag);
3201
3202	// Return on Mips is always a "jr $ra"
3203	return DAG.getNode(MipsISD::Ret, DL, MVT::Other, RetOps);
3204	}
3205
3206	//===----------------------------------------------------------------------===//
3207	// Mips Inline Assembly Support
3208	//===----------------------------------------------------------------------===//
3209
3210	/// getConstraintType - Given a constraint letter, return the type of
3211	/// constraint it is for this target.
3212	MipsTargetLowering::ConstraintType
3213	MipsTargetLowering::getConstraintType(StringRef Constraint) const {
3214	// Mips specific constraints
3215	// GCC config/mips/constraints.md
3216	//
3217	// 'd' : An address register. Equivalent to r
3218	// unless generating MIPS16 code.
3219	// 'y' : Equivalent to r; retained for
3220	// backwards compatibility.
3221	// 'c' : A register suitable for use in an indirect
3222	// jump. This will always be $25 for -mabicalls.
3223	// 'l' : The lo register. 1 word storage.
3224	// 'x' : The hilo register pair. Double word storage.
3225	if (Constraint.size() == 1) {
3226	switch (Constraint[0]) {
3227	default : break;
3228	case 'd':
3229	case 'y':
3230	case 'f':
3231	case 'c':
3232	case 'l':
3233	case 'x':
3234	return C_RegisterClass;
3235	case 'R':
3236	return C_Memory;
3237	}
3238	}
3239
3240	if (Constraint == "ZC")
3241	return C_Memory;
3242
3243	return TargetLowering::getConstraintType(Constraint);
3244	}
3245
3246	/// Examine constraint type and operand type and determine a weight value.
3247	/// This object must already have been set up with the operand type
3248	/// and the current alternative constraint selected.
3249	TargetLowering::ConstraintWeight
3250	MipsTargetLowering::getSingleConstraintMatchWeight(
3251	AsmOperandInfo &info, const char *constraint) const {
3252	ConstraintWeight weight = CW_Invalid;
3253	Value *CallOperandVal = info.CallOperandVal;
3254	// If we don't have a value, we can't do a match,
3255	// but allow it at the lowest weight.
3256	if (!CallOperandVal)
3257	return CW_Default;
3258	Type *type = CallOperandVal->getType();
3259	// Look at the constraint type.
3260	switch (*constraint) {
3261	default:
3262	weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
3263	break;
3264	case 'd':
3265	case 'y':
3266	if (type->isIntegerTy())
3267	weight = CW_Register;
3268	break;
3269	case 'f': // FPU or MSA register
3270	if (Subtarget.hasMSA() && type->isVectorTy() &&
3271	cast<VectorType>(type)->getBitWidth() == 128)
3272	weight = CW_Register;
3273	else if (type->isFloatTy())
3274	weight = CW_Register;
3275	break;
3276	case 'c': // $25 for indirect jumps
3277	case 'l': // lo register
3278	case 'x': // hilo register pair
3279	if (type->isIntegerTy())
3280	weight = CW_SpecificReg;
3281	break;
3282	case 'I': // signed 16 bit immediate
3283	case 'J': // integer zero
3284	case 'K': // unsigned 16 bit immediate
3285	case 'L': // signed 32 bit immediate where lower 16 bits are 0
3286	case 'N': // immediate in the range of -65535 to -1 (inclusive)
3287	case 'O': // signed 15 bit immediate (+- 16383)
3288	case 'P': // immediate in the range of 65535 to 1 (inclusive)
3289	if (isa<ConstantInt>(CallOperandVal))
3290	weight = CW_Constant;
3291	break;
3292	case 'R':
3293	weight = CW_Memory;
3294	break;
3295	}
3296	return weight;
3297	}
3298
3299	/// This is a helper function to parse a physical register string and split it
3300	/// into non-numeric and numeric parts (Prefix and Reg). The first boolean flag
3301	/// that is returned indicates whether parsing was successful. The second flag
3302	/// is true if the numeric part exists.
3303	static std::pair<bool, bool> parsePhysicalReg(StringRef C, StringRef &Prefix,
3304	unsigned long long &Reg) {
3305	if (C.front() != '{' \|\| C.back() != '}')
3306	return std::make_pair(false, false);
3307
3308	// Search for the first numeric character.
3309	StringRef::const_iterator I, B = C.begin() + 1, E = C.end() - 1;
3310	I = std::find_if(B, E, std::ptr_fun(isdigit));
3311
3312	Prefix = StringRef(B, I - B);
3313
3314	// The second flag is set to false if no numeric characters were found.
3315	if (I == E)
3316	return std::make_pair(true, false);
3317
3318	// Parse the numeric characters.
3319	return std::make_pair(!getAsUnsignedInteger(StringRef(I, E - I), 10, Reg),
3320	true);
3321	}
3322
3323	std::pair<unsigned, const TargetRegisterClass *> MipsTargetLowering::
3324	parseRegForInlineAsmConstraint(StringRef C, MVT VT) const {
3325	const TargetRegisterInfo *TRI =
3326	Subtarget.getRegisterInfo();
3327	const TargetRegisterClass *RC;
3328	StringRef Prefix;
3329	unsigned long long Reg;
3330
3331	std::pair<bool, bool> R = parsePhysicalReg(C, Prefix, Reg);
3332
3333	if (!R.first)
3334	return std::make_pair(0U, nullptr);
3335
3336	if ((Prefix == "hi" \|\| Prefix == "lo")) { // Parse hi/lo.
3337	// No numeric characters follow "hi" or "lo".
3338	if (R.second)
3339	return std::make_pair(0U, nullptr);
3340
3341	RC = TRI->getRegClass(Prefix == "hi" ?
3342	Mips::HI32RegClassID : Mips::LO32RegClassID);
3343	return std::make_pair(*(RC->begin()), RC);
3344	} else if (Prefix.startswith("$msa")) {
3345	// Parse $msa(ir\|csr\|access\|save\|modify\|request\|map\|unmap)
3346
3347	// No numeric characters follow the name.
3348	if (R.second)
3349	return std::make_pair(0U, nullptr);
3350
3351	Reg = StringSwitch<unsigned long long>(Prefix)
3352	.Case("$msair", Mips::MSAIR)
3353	.Case("$msacsr", Mips::MSACSR)
3354	.Case("$msaaccess", Mips::MSAAccess)
3355	.Case("$msasave", Mips::MSASave)
3356	.Case("$msamodify", Mips::MSAModify)
3357	.Case("$msarequest", Mips::MSARequest)
3358	.Case("$msamap", Mips::MSAMap)
3359	.Case("$msaunmap", Mips::MSAUnmap)
3360	.Default(0);
3361
3362	if (!Reg)
3363	return std::make_pair(0U, nullptr);
3364
3365	RC = TRI->getRegClass(Mips::MSACtrlRegClassID);
3366	return std::make_pair(Reg, RC);
3367	}
3368
3369	if (!R.second)
3370	return std::make_pair(0U, nullptr);
3371
3372	if (Prefix == "$f") { // Parse $f0-$f31.
3373	// If the size of FP registers is 64-bit or Reg is an even number, select
3374	// the 64-bit register class. Otherwise, select the 32-bit register class.
3375	if (VT == MVT::Other)
3376	VT = (Subtarget.isFP64bit() \|\| !(Reg % 2)) ? MVT::f64 : MVT::f32;
3377
3378	RC = getRegClassFor(VT);
3379
3380	if (RC == &Mips::AFGR64RegClass) {
3381	assert(Reg % 2 == 0)((Reg % 2 == 0) ? static_cast<void> (0) : __assert_fail ("Reg % 2 == 0", "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn250694/lib/Target/Mips/MipsISelLowering.cpp" , 3381, __PRETTY_FUNCTION__));
3382	Reg >>= 1;
3383	}
3384	} else if (Prefix == "$fcc") // Parse $fcc0-$fcc7.
3385	RC = TRI->getRegClass(Mips::FCCRegClassID);
3386	else if (Prefix == "$w") { // Parse $w0-$w31.
3387	RC = getRegClassFor((VT == MVT::Other) ? MVT::v16i8 : VT);
3388	} else { // Parse $0-$31.
3389	assert(Prefix == "$")((Prefix == "$") ? static_cast<void> (0) : __assert_fail ("Prefix == \"$\"", "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn250694/lib/Target/Mips/MipsISelLowering.cpp" , 3389, __PRETTY_FUNCTION__));
3390	RC = getRegClassFor((VT == MVT::Other) ? MVT::i32 : VT);
3391	}
3392
3393	assert(Reg < RC->getNumRegs())((Reg < RC->getNumRegs()) ? static_cast<void> (0) : __assert_fail ("Reg < RC->getNumRegs()", "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn250694/lib/Target/Mips/MipsISelLowering.cpp" , 3393, __PRETTY_FUNCTION__));
3394	return std::make_pair(*(RC->begin() + Reg), RC);
3395	}
3396
3397	/// Given a register class constraint, like 'r', if this corresponds directly
3398	/// to an LLVM register class, return a register of 0 and the register class
3399	/// pointer.
3400	std::pair<unsigned, const TargetRegisterClass *>
3401	MipsTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
3402	StringRef Constraint,
3403	MVT VT) const {
3404	if (Constraint.size() == 1) {
3405	switch (Constraint[0]) {
3406	case 'd': // Address register. Same as 'r' unless generating MIPS16 code.
3407	case 'y': // Same as 'r'. Exists for compatibility.
3408	case 'r':
3409	if (VT == MVT::i32 \|\| VT == MVT::i16 \|\| VT == MVT::i8) {
3410	if (Subtarget.inMips16Mode())
3411	return std::make_pair(0U, &Mips::CPU16RegsRegClass);
3412	return std::make_pair(0U, &Mips::GPR32RegClass);
3413	}
3414	if (VT == MVT::i64 && !Subtarget.isGP64bit())
3415	return std::make_pair(0U, &Mips::GPR32RegClass);
3416	if (VT == MVT::i64 && Subtarget.isGP64bit())
3417	return std::make_pair(0U, &Mips::GPR64RegClass);
3418	// This will generate an error message
3419	return std::make_pair(0U, nullptr);
3420	case 'f': // FPU or MSA register
3421	if (VT == MVT::v16i8)
3422	return std::make_pair(0U, &Mips::MSA128BRegClass);
3423	else if (VT == MVT::v8i16 \|\| VT == MVT::v8f16)
3424	return std::make_pair(0U, &Mips::MSA128HRegClass);
3425	else if (VT == MVT::v4i32 \|\| VT == MVT::v4f32)
3426	return std::make_pair(0U, &Mips::MSA128WRegClass);
3427	else if (VT == MVT::v2i64 \|\| VT == MVT::v2f64)
3428	return std::make_pair(0U, &Mips::MSA128DRegClass);
3429	else if (VT == MVT::f32)
3430	return std::make_pair(0U, &Mips::FGR32RegClass);
3431	else if ((VT == MVT::f64) && (!Subtarget.isSingleFloat())) {
3432	if (Subtarget.isFP64bit())
3433	return std::make_pair(0U, &Mips::FGR64RegClass);
3434	return std::make_pair(0U, &Mips::AFGR64RegClass);
3435	}
3436	break;
3437	case 'c': // register suitable for indirect jump
3438	if (VT == MVT::i32)
3439	return std::make_pair((unsigned)Mips::T9, &Mips::GPR32RegClass);
3440	assert(VT == MVT::i64 && "Unexpected type.")((VT == MVT::i64 && "Unexpected type.") ? static_cast <void> (0) : __assert_fail ("VT == MVT::i64 && \"Unexpected type.\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn250694/lib/Target/Mips/MipsISelLowering.cpp" , 3440, __PRETTY_FUNCTION__));
3441	return std::make_pair((unsigned)Mips::T9_64, &Mips::GPR64RegClass);
3442	case 'l': // register suitable for indirect jump
3443	if (VT == MVT::i32)
3444	return std::make_pair((unsigned)Mips::LO0, &Mips::LO32RegClass);
3445	return std::make_pair((unsigned)Mips::LO0_64, &Mips::LO64RegClass);
3446	case 'x': // register suitable for indirect jump
3447	// Fixme: Not triggering the use of both hi and low
3448	// This will generate an error message
3449	return std::make_pair(0U, nullptr);
3450	}
3451	}
3452
3453	std::pair<unsigned, const TargetRegisterClass *> R;
3454	R = parseRegForInlineAsmConstraint(Constraint, VT);
3455
3456	if (R.second)
3457	return R;
3458
3459	return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
3460	}
3461
3462	/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
3463	/// vector. If it is invalid, don't add anything to Ops.
3464	void MipsTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
3465	std::string &Constraint,
3466	std::vector<SDValue>&Ops,
3467	SelectionDAG &DAG) const {
3468	SDLoc DL(Op);
3469	SDValue Result;
3470
3471	// Only support length 1 constraints for now.
3472	if (Constraint.length() > 1) return;
3473
3474	char ConstraintLetter = Constraint[0];
3475	switch (ConstraintLetter) {
3476	default: break; // This will fall through to the generic implementation
3477	case 'I': // Signed 16 bit constant
3478	// If this fails, the parent routine will give an error
3479	if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3480	EVT Type = Op.getValueType();
3481	int64_t Val = C->getSExtValue();
3482	if (isInt<16>(Val)) {
3483	Result = DAG.getTargetConstant(Val, DL, Type);
3484	break;
3485	}
3486	}
3487	return;
3488	case 'J': // integer zero
3489	if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3490	EVT Type = Op.getValueType();
3491	int64_t Val = C->getZExtValue();
3492	if (Val == 0) {
3493	Result = DAG.getTargetConstant(0, DL, Type);
3494	break;
3495	}
3496	}
3497	return;
3498	case 'K': // unsigned 16 bit immediate
3499	if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3500	EVT Type = Op.getValueType();
3501	uint64_t Val = (uint64_t)C->getZExtValue();
3502	if (isUInt<16>(Val)) {
3503	Result = DAG.getTargetConstant(Val, DL, Type);
3504	break;
3505	}
3506	}
3507	return;
3508	case 'L': // signed 32 bit immediate where lower 16 bits are 0
3509	if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3510	EVT Type = Op.getValueType();
3511	int64_t Val = C->getSExtValue();
3512	if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)){
3513	Result = DAG.getTargetConstant(Val, DL, Type);
3514	break;
3515	}
3516	}
3517	return;
3518	case 'N': // immediate in the range of -65535 to -1 (inclusive)
3519	if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3520	EVT Type = Op.getValueType();
3521	int64_t Val = C->getSExtValue();
3522	if ((Val >= -65535) && (Val <= -1)) {
3523	Result = DAG.getTargetConstant(Val, DL, Type);
3524	break;
3525	}
3526	}
3527	return;
3528	case 'O': // signed 15 bit immediate
3529	if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3530	EVT Type = Op.getValueType();
3531	int64_t Val = C->getSExtValue();
3532	if ((isInt<15>(Val))) {
3533	Result = DAG.getTargetConstant(Val, DL, Type);
3534	break;
3535	}
3536	}
3537	return;
3538	case 'P': // immediate in the range of 1 to 65535 (inclusive)
3539	if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3540	EVT Type = Op.getValueType();
3541	int64_t Val = C->getSExtValue();
3542	if ((Val <= 65535) && (Val >= 1)) {
3543	Result = DAG.getTargetConstant(Val, DL, Type);
3544	break;
3545	}
3546	}
3547	return;
3548	}
3549
3550	if (Result.getNode()) {
3551	Ops.push_back(Result);
3552	return;
3553	}
3554
3555	TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
3556	}
3557
3558	bool MipsTargetLowering::isLegalAddressingMode(const DataLayout &DL,
3559	const AddrMode &AM, Type *Ty,
3560	unsigned AS) const {
3561	// No global is ever allowed as a base.
3562	if (AM.BaseGV)
3563	return false;
3564
3565	switch (AM.Scale) {
3566	case 0: // "r+i" or just "i", depending on HasBaseReg.
3567	break;
3568	case 1:
3569	if (!AM.HasBaseReg) // allow "r+i".
3570	break;
3571	return false; // disallow "r+r" or "r+r+i".
3572	default:
3573	return false;
3574	}
3575
3576	return true;
3577	}
3578
3579	bool
3580	MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
3581	// The Mips target isn't yet aware of offsets.
3582	return false;
3583	}
3584
3585	EVT MipsTargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
3586	unsigned SrcAlign,
3587	bool IsMemset, bool ZeroMemset,
3588	bool MemcpyStrSrc,
3589	MachineFunction &MF) const {
3590	if (Subtarget.hasMips64())
3591	return MVT::i64;
3592
3593	return MVT::i32;
3594	}
3595
3596	bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3597	if (VT != MVT::f32 && VT != MVT::f64)
3598	return false;
3599	if (Imm.isNegZero())
3600	return false;
3601	return Imm.isZero();
3602	}
3603
3604	unsigned MipsTargetLowering::getJumpTableEncoding() const {
3605	if (ABI.IsN64())
3606	return MachineJumpTableInfo::EK_GPRel64BlockAddress;
3607
3608	return TargetLowering::getJumpTableEncoding();
3609	}
3610
3611	bool MipsTargetLowering::useSoftFloat() const {
3612	return Subtarget.useSoftFloat();
3613	}
3614
3615	void MipsTargetLowering::copyByValRegs(
3616	SDValue Chain, SDLoc DL, std::vector<SDValue> &OutChains, SelectionDAG &DAG,
3617	const ISD::ArgFlagsTy &Flags, SmallVectorImpl<SDValue> &InVals,
3618	const Argument *FuncArg, unsigned FirstReg, unsigned LastReg,
3619	const CCValAssign &VA, MipsCCState &State) const {
3620	MachineFunction &MF = DAG.getMachineFunction();
3621	MachineFrameInfo *MFI = MF.getFrameInfo();
3622	unsigned GPRSizeInBytes = Subtarget.getGPRSizeInBytes();
3623	unsigned NumRegs = LastReg - FirstReg;
3624	unsigned RegAreaSize = NumRegs * GPRSizeInBytes;
3625	unsigned FrameObjSize = std::max(Flags.getByValSize(), RegAreaSize);
3626	int FrameObjOffset;
3627	ArrayRef<MCPhysReg> ByValArgRegs = ABI.GetByValArgRegs();
3628
3629	if (RegAreaSize)
3630	FrameObjOffset =
3631	(int)ABI.GetCalleeAllocdArgSizeInBytes(State.getCallingConv()) -
3632	(int)((ByValArgRegs.size() - FirstReg) * GPRSizeInBytes);
3633	else
3634	FrameObjOffset = VA.getLocMemOffset();
3635
3636	// Create frame object.
3637	EVT PtrTy = getPointerTy(DAG.getDataLayout());
3638	int FI = MFI->CreateFixedObject(FrameObjSize, FrameObjOffset, true);
3639	SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
3640	InVals.push_back(FIN);
3641
3642	if (!NumRegs)
3643	return;
3644
3645	// Copy arg registers.
3646	MVT RegTy = MVT::getIntegerVT(GPRSizeInBytes * 8);
3647	const TargetRegisterClass *RC = getRegClassFor(RegTy);
3648
3649	for (unsigned I = 0; I < NumRegs; ++I) {
3650	unsigned ArgReg = ByValArgRegs[FirstReg + I];
3651	unsigned VReg = addLiveIn(MF, ArgReg, RC);
3652	unsigned Offset = I * GPRSizeInBytes;
3653	SDValue StorePtr = DAG.getNode(ISD::ADD, DL, PtrTy, FIN,
3654	DAG.getConstant(Offset, DL, PtrTy));
3655	SDValue Store = DAG.getStore(Chain, DL, DAG.getRegister(VReg, RegTy),
3656	StorePtr, MachinePointerInfo(FuncArg, Offset),
3657	false, false, 0);
3658	OutChains.push_back(Store);
3659	}
3660	}
3661
3662	// Copy byVal arg to registers and stack.
3663	void MipsTargetLowering::passByValArg(
3664	SDValue Chain, SDLoc DL,
3665	std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
3666	SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr,
3667	MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg, unsigned FirstReg,
3668	unsigned LastReg, const ISD::ArgFlagsTy &Flags, bool isLittle,
3669	const CCValAssign &VA) const {
3670	unsigned ByValSizeInBytes = Flags.getByValSize();
3671	unsigned OffsetInBytes = 0; // From beginning of struct
3672	unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes();
3673	unsigned Alignment = std::min(Flags.getByValAlign(), RegSizeInBytes);
3674	EVT PtrTy = getPointerTy(DAG.getDataLayout()),
3675	RegTy = MVT::getIntegerVT(RegSizeInBytes * 8);
3676	unsigned NumRegs = LastReg - FirstReg;
3677
3678	if (NumRegs) {
3679	ArrayRef<MCPhysReg> ArgRegs = ABI.GetByValArgRegs();
3680	bool LeftoverBytes = (NumRegs * RegSizeInBytes > ByValSizeInBytes);
3681	unsigned I = 0;
3682
3683	// Copy words to registers.
3684	for (; I < NumRegs - LeftoverBytes; ++I, OffsetInBytes += RegSizeInBytes) {
3685	SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
3686	DAG.getConstant(OffsetInBytes, DL, PtrTy));
3687	SDValue LoadVal = DAG.getLoad(RegTy, DL, Chain, LoadPtr,
3688	MachinePointerInfo(), false, false, false,
3689	Alignment);
3690	MemOpChains.push_back(LoadVal.getValue(1));
3691	unsigned ArgReg = ArgRegs[FirstReg + I];
3692	RegsToPass.push_back(std::make_pair(ArgReg, LoadVal));
3693	}
3694
3695	// Return if the struct has been fully copied.
3696	if (ByValSizeInBytes == OffsetInBytes)
3697	return;
3698
3699	// Copy the remainder of the byval argument with sub-word loads and shifts.
3700	if (LeftoverBytes) {
3701	SDValue Val;
3702
3703	for (unsigned LoadSizeInBytes = RegSizeInBytes / 2, TotalBytesLoaded = 0;
3704	OffsetInBytes < ByValSizeInBytes; LoadSizeInBytes /= 2) {
3705	unsigned RemainingSizeInBytes = ByValSizeInBytes - OffsetInBytes;
3706
3707	if (RemainingSizeInBytes < LoadSizeInBytes)
3708	continue;
3709
3710	// Load subword.
3711	SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
3712	DAG.getConstant(OffsetInBytes, DL,
3713	PtrTy));
3714	SDValue LoadVal = DAG.getExtLoad(
3715	ISD::ZEXTLOAD, DL, RegTy, Chain, LoadPtr, MachinePointerInfo(),
3716	MVT::getIntegerVT(LoadSizeInBytes * 8), false, false, false,
3717	Alignment);
3718	MemOpChains.push_back(LoadVal.getValue(1));
3719
3720	// Shift the loaded value.
3721	unsigned Shamt;
3722
3723	if (isLittle)
3724	Shamt = TotalBytesLoaded * 8;
3725	else
3726	Shamt = (RegSizeInBytes - (TotalBytesLoaded + LoadSizeInBytes)) * 8;
3727
3728	SDValue Shift = DAG.getNode(ISD::SHL, DL, RegTy, LoadVal,
3729	DAG.getConstant(Shamt, DL, MVT::i32));
3730
3731	if (Val.getNode())
3732	Val = DAG.getNode(ISD::OR, DL, RegTy, Val, Shift);
3733	else
3734	Val = Shift;
3735
3736	OffsetInBytes += LoadSizeInBytes;
3737	TotalBytesLoaded += LoadSizeInBytes;
3738	Alignment = std::min(Alignment, LoadSizeInBytes);
3739	}
3740
3741	unsigned ArgReg = ArgRegs[FirstReg + I];
3742	RegsToPass.push_back(std::make_pair(ArgReg, Val));
3743	return;
3744	}
3745	}
3746
3747	// Copy remainder of byval arg to it with memcpy.
3748	unsigned MemCpySize = ByValSizeInBytes - OffsetInBytes;
3749	SDValue Src = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
3750	DAG.getConstant(OffsetInBytes, DL, PtrTy));
3751	SDValue Dst = DAG.getNode(ISD::ADD, DL, PtrTy, StackPtr,
3752	DAG.getIntPtrConstant(VA.getLocMemOffset(), DL));
3753	Chain = DAG.getMemcpy(Chain, DL, Dst, Src,
3754	DAG.getConstant(MemCpySize, DL, PtrTy),
3755	Alignment, /isVolatile=/false, /AlwaysInline=/false,
3756	/isTailCall=/false,
3757	MachinePointerInfo(), MachinePointerInfo());
3758	MemOpChains.push_back(Chain);
3759	}
3760
3761	void MipsTargetLowering::writeVarArgRegs(std::vector<SDValue> &OutChains,
3762	SDValue Chain, SDLoc DL,
3763	SelectionDAG &DAG,
3764	CCState &State) const {
3765	ArrayRef<MCPhysReg> ArgRegs = ABI.GetVarArgRegs();
3766	unsigned Idx = State.getFirstUnallocated(ArgRegs);
3767	unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes();
3768	MVT RegTy = MVT::getIntegerVT(RegSizeInBytes * 8);
3769	const TargetRegisterClass *RC = getRegClassFor(RegTy);
3770	MachineFunction &MF = DAG.getMachineFunction();
3771	MachineFrameInfo *MFI = MF.getFrameInfo();
3772	MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
3773
3774	// Offset of the first variable argument from stack pointer.
3775	int VaArgOffset;
3776
3777	if (ArgRegs.size() == Idx)
3778	VaArgOffset =
3779	RoundUpToAlignment(State.getNextStackOffset(), RegSizeInBytes);
3780	else {
3781	VaArgOffset =
3782	(int)ABI.GetCalleeAllocdArgSizeInBytes(State.getCallingConv()) -
3783	(int)(RegSizeInBytes * (ArgRegs.size() - Idx));
3784	}
3785
3786	// Record the frame index of the first variable argument
3787	// which is a value necessary to VASTART.
3788	int FI = MFI->CreateFixedObject(RegSizeInBytes, VaArgOffset, true);
3789	MipsFI->setVarArgsFrameIndex(FI);
3790
3791	// Copy the integer registers that have not been used for argument passing
3792	// to the argument register save area. For O32, the save area is allocated
3793	// in the caller's stack frame, while for N32/64, it is allocated in the
3794	// callee's stack frame.
3795	for (unsigned I = Idx; I < ArgRegs.size();
3796	++I, VaArgOffset += RegSizeInBytes) {
3797	unsigned Reg = addLiveIn(MF, ArgRegs[I], RC);
3798	SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegTy);
3799	FI = MFI->CreateFixedObject(RegSizeInBytes, VaArgOffset, true);
3800	SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
3801	SDValue Store = DAG.getStore(Chain, DL, ArgValue, PtrOff,
3802	MachinePointerInfo(), false, false, 0);
3803	cast<StoreSDNode>(Store.getNode())->getMemOperand()->setValue(
3804	(Value *)nullptr);
3805	OutChains.push_back(Store);
3806	}
3807	}
3808
3809	void MipsTargetLowering::HandleByVal(CCState *State, unsigned &Size,
3810	unsigned Align) const {
3811	const TargetFrameLowering *TFL = Subtarget.getFrameLowering();
3812
3813	assert(Size && "Byval argument's size shouldn't be 0.")((Size && "Byval argument's size shouldn't be 0.") ? static_cast <void> (0) : __assert_fail ("Size && \"Byval argument's size shouldn't be 0.\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn250694/lib/Target/Mips/MipsISelLowering.cpp" , 3813, __PRETTY_FUNCTION__));
3814
3815	Align = std::min(Align, TFL->getStackAlignment());
3816
3817	unsigned FirstReg = 0;
3818	unsigned NumRegs = 0;
3819
3820	if (State->getCallingConv() != CallingConv::Fast) {
3821	unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes();
3822	ArrayRef<MCPhysReg> IntArgRegs = ABI.GetByValArgRegs();
3823	// FIXME: The O32 case actually describes no shadow registers.
3824	const MCPhysReg *ShadowRegs =
3825	ABI.IsO32() ? IntArgRegs.data() : Mips64DPRegs;
3826
3827	// We used to check the size as well but we can't do that anymore since
3828	// CCState::HandleByVal() rounds up the size after calling this function.
3829	assert(!(Align % RegSizeInBytes) &&((!(Align % RegSizeInBytes) && "Byval argument's alignment should be a multiple of" "RegSizeInBytes.") ? static_cast<void> (0) : __assert_fail ("!(Align % RegSizeInBytes) && \"Byval argument's alignment should be a multiple of\" \"RegSizeInBytes.\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn250694/lib/Target/Mips/MipsISelLowering.cpp" , 3831, __PRETTY_FUNCTION__))
3830	"Byval argument's alignment should be a multiple of"((!(Align % RegSizeInBytes) && "Byval argument's alignment should be a multiple of" "RegSizeInBytes.") ? static_cast<void> (0) : __assert_fail ("!(Align % RegSizeInBytes) && \"Byval argument's alignment should be a multiple of\" \"RegSizeInBytes.\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn250694/lib/Target/Mips/MipsISelLowering.cpp" , 3831, __PRETTY_FUNCTION__))
3831	"RegSizeInBytes.")((!(Align % RegSizeInBytes) && "Byval argument's alignment should be a multiple of" "RegSizeInBytes.") ? static_cast<void> (0) : __assert_fail ("!(Align % RegSizeInBytes) && \"Byval argument's alignment should be a multiple of\" \"RegSizeInBytes.\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn250694/lib/Target/Mips/MipsISelLowering.cpp" , 3831, __PRETTY_FUNCTION__));
3832
3833	FirstReg = State->getFirstUnallocated(IntArgRegs);
3834
3835	// If Align > RegSizeInBytes, the first arg register must be even.
3836	// FIXME: This condition happens to do the right thing but it's not the
3837	// right way to test it. We want to check that the stack frame offset
3838	// of the register is aligned.
3839	if ((Align > RegSizeInBytes) && (FirstReg % 2)) {
3840	State->AllocateReg(IntArgRegs[FirstReg], ShadowRegs[FirstReg]);
3841	++FirstReg;
3842	}
3843
3844	// Mark the registers allocated.
3845	Size = RoundUpToAlignment(Size, RegSizeInBytes);
3846	for (unsigned I = FirstReg; Size > 0 && (I < IntArgRegs.size());
3847	Size -= RegSizeInBytes, ++I, ++NumRegs)
3848	State->AllocateReg(IntArgRegs[I], ShadowRegs[I]);
3849	}
3850
3851	State->addInRegsParamInfo(FirstReg, FirstReg + NumRegs);
3852	}
3853
3854	MachineBasicBlock *
3855	MipsTargetLowering::emitPseudoSELECT(MachineInstr MI, MachineBasicBlock BB,
3856	bool isFPCmp, unsigned Opc) const {
3857	assert(!(Subtarget.hasMips4() \|\| Subtarget.hasMips32()) &&((!(Subtarget.hasMips4() \|\| Subtarget.hasMips32()) && "Subtarget already supports SELECT nodes with the use of" "conditional-move instructions." ) ? static_cast<void> (0) : __assert_fail ("!(Subtarget.hasMips4() \|\| Subtarget.hasMips32()) && \"Subtarget already supports SELECT nodes with the use of\" \"conditional-move instructions.\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn250694/lib/Target/Mips/MipsISelLowering.cpp" , 3859, __PRETTY_FUNCTION__))
3858	"Subtarget already supports SELECT nodes with the use of"((!(Subtarget.hasMips4() \|\| Subtarget.hasMips32()) && "Subtarget already supports SELECT nodes with the use of" "conditional-move instructions." ) ? static_cast<void> (0) : __assert_fail ("!(Subtarget.hasMips4() \|\| Subtarget.hasMips32()) && \"Subtarget already supports SELECT nodes with the use of\" \"conditional-move instructions.\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn250694/lib/Target/Mips/MipsISelLowering.cpp" , 3859, __PRETTY_FUNCTION__))
3859	"conditional-move instructions.")((!(Subtarget.hasMips4() \|\| Subtarget.hasMips32()) && "Subtarget already supports SELECT nodes with the use of" "conditional-move instructions." ) ? static_cast<void> (0) : __assert_fail ("!(Subtarget.hasMips4() \|\| Subtarget.hasMips32()) && \"Subtarget already supports SELECT nodes with the use of\" \"conditional-move instructions.\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn250694/lib/Target/Mips/MipsISelLowering.cpp" , 3859, __PRETTY_FUNCTION__));
3860
3861	const TargetInstrInfo *TII =
3862	Subtarget.getInstrInfo();
3863	DebugLoc DL = MI->getDebugLoc();
3864
3865	// To "insert" a SELECT instruction, we actually have to insert the
3866	// diamond control-flow pattern. The incoming instruction knows the
3867	// destination vreg to set, the condition code register to branch on, the
3868	// true/false values to select between, and a branch opcode to use.
3869	const BasicBlock *LLVM_BB = BB->getBasicBlock();
3870	MachineFunction::iterator It = BB;
3871	++It;
3872
3873	// thisMBB:
3874	// ...
3875	// TrueVal = ...
3876	// setcc r1, r2, r3
3877	// bNE r1, r0, copy1MBB
3878	// fallthrough --> copy0MBB
3879	MachineBasicBlock *thisMBB = BB;
3880	MachineFunction *F = BB->getParent();
3881	MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
3882	MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
3883	F->insert(It, copy0MBB);
3884	F->insert(It, sinkMBB);
3885
3886	// Transfer the remainder of BB and its successor edges to sinkMBB.
3887	sinkMBB->splice(sinkMBB->begin(), BB,
3888	std::next(MachineBasicBlock::iterator(MI)), BB->end());
3889	sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
3890
3891	// Next, add the true and fallthrough blocks as its successors.
3892	BB->addSuccessor(copy0MBB);
3893	BB->addSuccessor(sinkMBB);
3894
3895	if (isFPCmp) {
3896	// bc1[tf] cc, sinkMBB
3897	BuildMI(BB, DL, TII->get(Opc))
3898	.addReg(MI->getOperand(1).getReg())
3899	.addMBB(sinkMBB);
3900	} else {
3901	// bne rs, $0, sinkMBB
3902	BuildMI(BB, DL, TII->get(Opc))
3903	.addReg(MI->getOperand(1).getReg())
3904	.addReg(Mips::ZERO)
3905	.addMBB(sinkMBB);
3906	}
3907
3908	// copy0MBB:
3909	// %FalseValue = ...
3910	// # fallthrough to sinkMBB
3911	BB = copy0MBB;
3912
3913	// Update machine-CFG edges
3914	BB->addSuccessor(sinkMBB);
3915
3916	// sinkMBB:
3917	// %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
3918	// ...
3919	BB = sinkMBB;
3920
3921	BuildMI(*BB, BB->begin(), DL,
3922	TII->get(Mips::PHI), MI->getOperand(0).getReg())
3923	.addReg(MI->getOperand(2).getReg()).addMBB(thisMBB)
3924	.addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB);
3925
3926	MI->eraseFromParent(); // The pseudo instruction is gone now.
3927
3928	return BB;
3929	}
3930
3931	// FIXME? Maybe this could be a TableGen attribute on some registers and
3932	// this table could be generated automatically from RegInfo.
3933	unsigned MipsTargetLowering::getRegisterByName(const char* RegName, EVT VT,
3934	SelectionDAG &DAG) const {
3935	// Named registers is expected to be fairly rare. For now, just support $28
3936	// since the linux kernel uses it.
3937	if (Subtarget.isGP64bit()) {
3938	unsigned Reg = StringSwitch<unsigned>(RegName)
3939	.Case("$28", Mips::GP_64)
3940	.Default(0);
3941	if (Reg)
3942	return Reg;
3943	} else {
3944	unsigned Reg = StringSwitch<unsigned>(RegName)
3945	.Case("$28", Mips::GP)
3946	.Default(0);
3947	if (Reg)
3948	return Reg;
3949	}
3950	report_fatal_error("Invalid register name global variable");
3951	}