/tmp/buildd/llvm-toolchain-snapshot-3.7~svn227492/lib/Target/Mips/MipsISelLowering.cpp

Bug Summary

File:	lib/Target/Mips/MipsISelLowering.cpp
Location:	line 1472, column 3
Description:	Value stored to 'BB' is never read

Annotated Source Code

1	//===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
2	//
3	// The LLVM Compiler Infrastructure
4	//
5	// This file is distributed under the University of Illinois Open Source
6	// License. See LICENSE.TXT for details.
7	//
8	//===----------------------------------------------------------------------===//
9	//
10	// This file defines the interfaces that Mips uses to lower LLVM code into a
11	// selection DAG.
12	//
13	//===----------------------------------------------------------------------===//
14	#include "MipsISelLowering.h"
15	#include "InstPrinter/MipsInstPrinter.h"
16	#include "MCTargetDesc/MipsBaseInfo.h"
17	#include "MipsCCState.h"
18	#include "MipsMachineFunction.h"
19	#include "MipsSubtarget.h"
20	#include "MipsTargetMachine.h"
21	#include "MipsTargetObjectFile.h"
22	#include "llvm/ADT/Statistic.h"
23	#include "llvm/ADT/StringSwitch.h"
24	#include "llvm/CodeGen/CallingConvLower.h"
25	#include "llvm/CodeGen/MachineFrameInfo.h"
26	#include "llvm/CodeGen/MachineFunction.h"
27	#include "llvm/CodeGen/MachineInstrBuilder.h"
28	#include "llvm/CodeGen/MachineJumpTableInfo.h"
29	#include "llvm/CodeGen/MachineRegisterInfo.h"
30	#include "llvm/CodeGen/SelectionDAGISel.h"
31	#include "llvm/CodeGen/ValueTypes.h"
32	#include "llvm/IR/CallingConv.h"
33	#include "llvm/IR/DerivedTypes.h"
34	#include "llvm/IR/GlobalVariable.h"
35	#include "llvm/Support/CommandLine.h"
36	#include "llvm/Support/Debug.h"
37	#include "llvm/Support/ErrorHandling.h"
38	#include "llvm/Support/raw_ostream.h"
39	#include <cctype>
40
41	using namespace llvm;
42
43	#define DEBUG_TYPE"mips-lower" "mips-lower"
44
45	STATISTIC(NumTailCalls, "Number of tail calls")static llvm::Statistic NumTailCalls = { "mips-lower", "Number of tail calls" , 0, 0 };
46
47	static cl::opt<bool>
48	LargeGOT("mxgot", cl::Hidden,
49	cl::desc("MIPS: Enable GOT larger than 64k."), cl::init(false));
50
51	static cl::opt<bool>
52	NoZeroDivCheck("mno-check-zero-division", cl::Hidden,
53	cl::desc("MIPS: Don't trap on integer division by zero."),
54	cl::init(false));
55
56	cl::opt<bool>
57	EnableMipsFastISel("mips-fast-isel", cl::Hidden,
58	cl::desc("Allow mips-fast-isel to be used"),
59	cl::init(false));
60
61	static const MCPhysReg Mips64DPRegs[8] = {
62	Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64,
63	Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64
64	};
65
66	// If I is a shifted mask, set the size (Size) and the first bit of the
67	// mask (Pos), and return true.
68	// For example, if I is 0x003ff800, (Pos, Size) = (11, 11).
69	static bool isShiftedMask(uint64_t I, uint64_t &Pos, uint64_t &Size) {
70	if (!isShiftedMask_64(I))
71	return false;
72
73	Size = CountPopulation_64(I);
74	Pos = countTrailingZeros(I);
75	return true;
76	}
77
78	SDValue MipsTargetLowering::getGlobalReg(SelectionDAG &DAG, EVT Ty) const {
79	MipsFunctionInfo *FI = DAG.getMachineFunction().getInfo<MipsFunctionInfo>();
80	return DAG.getRegister(FI->getGlobalBaseReg(), Ty);
81	}
82
83	SDValue MipsTargetLowering::getTargetNode(GlobalAddressSDNode *N, EVT Ty,
84	SelectionDAG &DAG,
85	unsigned Flag) const {
86	return DAG.getTargetGlobalAddress(N->getGlobal(), SDLoc(N), Ty, 0, Flag);
87	}
88
89	SDValue MipsTargetLowering::getTargetNode(ExternalSymbolSDNode *N, EVT Ty,
90	SelectionDAG &DAG,
91	unsigned Flag) const {
92	return DAG.getTargetExternalSymbol(N->getSymbol(), Ty, Flag);
93	}
94
95	SDValue MipsTargetLowering::getTargetNode(BlockAddressSDNode *N, EVT Ty,
96	SelectionDAG &DAG,
97	unsigned Flag) const {
98	return DAG.getTargetBlockAddress(N->getBlockAddress(), Ty, 0, Flag);
99	}
100
101	SDValue MipsTargetLowering::getTargetNode(JumpTableSDNode *N, EVT Ty,
102	SelectionDAG &DAG,
103	unsigned Flag) const {
104	return DAG.getTargetJumpTable(N->getIndex(), Ty, Flag);
105	}
106
107	SDValue MipsTargetLowering::getTargetNode(ConstantPoolSDNode *N, EVT Ty,
108	SelectionDAG &DAG,
109	unsigned Flag) const {
110	return DAG.getTargetConstantPool(N->getConstVal(), Ty, N->getAlignment(),
111	N->getOffset(), Flag);
112	}
113
114	const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
115	switch (Opcode) {
116	case MipsISD::JmpLink: return "MipsISD::JmpLink";
117	case MipsISD::TailCall: return "MipsISD::TailCall";
118	case MipsISD::Hi: return "MipsISD::Hi";
119	case MipsISD::Lo: return "MipsISD::Lo";
120	case MipsISD::GPRel: return "MipsISD::GPRel";
121	case MipsISD::ThreadPointer: return "MipsISD::ThreadPointer";
122	case MipsISD::Ret: return "MipsISD::Ret";
123	case MipsISD::EH_RETURN: return "MipsISD::EH_RETURN";
124	case MipsISD::FPBrcond: return "MipsISD::FPBrcond";
125	case MipsISD::FPCmp: return "MipsISD::FPCmp";
126	case MipsISD::CMovFP_T: return "MipsISD::CMovFP_T";
127	case MipsISD::CMovFP_F: return "MipsISD::CMovFP_F";
128	case MipsISD::TruncIntFP: return "MipsISD::TruncIntFP";
129	case MipsISD::MFHI: return "MipsISD::MFHI";
130	case MipsISD::MFLO: return "MipsISD::MFLO";
131	case MipsISD::MTLOHI: return "MipsISD::MTLOHI";
132	case MipsISD::Mult: return "MipsISD::Mult";
133	case MipsISD::Multu: return "MipsISD::Multu";
134	case MipsISD::MAdd: return "MipsISD::MAdd";
135	case MipsISD::MAddu: return "MipsISD::MAddu";
136	case MipsISD::MSub: return "MipsISD::MSub";
137	case MipsISD::MSubu: return "MipsISD::MSubu";
138	case MipsISD::DivRem: return "MipsISD::DivRem";
139	case MipsISD::DivRemU: return "MipsISD::DivRemU";
140	case MipsISD::DivRem16: return "MipsISD::DivRem16";
141	case MipsISD::DivRemU16: return "MipsISD::DivRemU16";
142	case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64";
143	case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64";
144	case MipsISD::Wrapper: return "MipsISD::Wrapper";
145	case MipsISD::Sync: return "MipsISD::Sync";
146	case MipsISD::Ext: return "MipsISD::Ext";
147	case MipsISD::Ins: return "MipsISD::Ins";
148	case MipsISD::LWL: return "MipsISD::LWL";
149	case MipsISD::LWR: return "MipsISD::LWR";
150	case MipsISD::SWL: return "MipsISD::SWL";
151	case MipsISD::SWR: return "MipsISD::SWR";
152	case MipsISD::LDL: return "MipsISD::LDL";
153	case MipsISD::LDR: return "MipsISD::LDR";
154	case MipsISD::SDL: return "MipsISD::SDL";
155	case MipsISD::SDR: return "MipsISD::SDR";
156	case MipsISD::EXTP: return "MipsISD::EXTP";
157	case MipsISD::EXTPDP: return "MipsISD::EXTPDP";
158	case MipsISD::EXTR_S_H: return "MipsISD::EXTR_S_H";
159	case MipsISD::EXTR_W: return "MipsISD::EXTR_W";
160	case MipsISD::EXTR_R_W: return "MipsISD::EXTR_R_W";
161	case MipsISD::EXTR_RS_W: return "MipsISD::EXTR_RS_W";
162	case MipsISD::SHILO: return "MipsISD::SHILO";
163	case MipsISD::MTHLIP: return "MipsISD::MTHLIP";
164	case MipsISD::MULT: return "MipsISD::MULT";
165	case MipsISD::MULTU: return "MipsISD::MULTU";
166	case MipsISD::MADD_DSP: return "MipsISD::MADD_DSP";
167	case MipsISD::MADDU_DSP: return "MipsISD::MADDU_DSP";
168	case MipsISD::MSUB_DSP: return "MipsISD::MSUB_DSP";
169	case MipsISD::MSUBU_DSP: return "MipsISD::MSUBU_DSP";
170	case MipsISD::SHLL_DSP: return "MipsISD::SHLL_DSP";
171	case MipsISD::SHRA_DSP: return "MipsISD::SHRA_DSP";
172	case MipsISD::SHRL_DSP: return "MipsISD::SHRL_DSP";
173	case MipsISD::SETCC_DSP: return "MipsISD::SETCC_DSP";
174	case MipsISD::SELECT_CC_DSP: return "MipsISD::SELECT_CC_DSP";
175	case MipsISD::VALL_ZERO: return "MipsISD::VALL_ZERO";
176	case MipsISD::VANY_ZERO: return "MipsISD::VANY_ZERO";
177	case MipsISD::VALL_NONZERO: return "MipsISD::VALL_NONZERO";
178	case MipsISD::VANY_NONZERO: return "MipsISD::VANY_NONZERO";
179	case MipsISD::VCEQ: return "MipsISD::VCEQ";
180	case MipsISD::VCLE_S: return "MipsISD::VCLE_S";
181	case MipsISD::VCLE_U: return "MipsISD::VCLE_U";
182	case MipsISD::VCLT_S: return "MipsISD::VCLT_S";
183	case MipsISD::VCLT_U: return "MipsISD::VCLT_U";
184	case MipsISD::VSMAX: return "MipsISD::VSMAX";
185	case MipsISD::VSMIN: return "MipsISD::VSMIN";
186	case MipsISD::VUMAX: return "MipsISD::VUMAX";
187	case MipsISD::VUMIN: return "MipsISD::VUMIN";
188	case MipsISD::VEXTRACT_SEXT_ELT: return "MipsISD::VEXTRACT_SEXT_ELT";
189	case MipsISD::VEXTRACT_ZEXT_ELT: return "MipsISD::VEXTRACT_ZEXT_ELT";
190	case MipsISD::VNOR: return "MipsISD::VNOR";
191	case MipsISD::VSHF: return "MipsISD::VSHF";
192	case MipsISD::SHF: return "MipsISD::SHF";
193	case MipsISD::ILVEV: return "MipsISD::ILVEV";
194	case MipsISD::ILVOD: return "MipsISD::ILVOD";
195	case MipsISD::ILVL: return "MipsISD::ILVL";
196	case MipsISD::ILVR: return "MipsISD::ILVR";
197	case MipsISD::PCKEV: return "MipsISD::PCKEV";
198	case MipsISD::PCKOD: return "MipsISD::PCKOD";
199	case MipsISD::INSVE: return "MipsISD::INSVE";
200	default: return nullptr;
201	}
202	}
203
204	MipsTargetLowering::MipsTargetLowering(const MipsTargetMachine &TM,
205	const MipsSubtarget &STI)
206	: TargetLowering(TM), Subtarget(STI) {
207	// Mips does not have i1 type, so use i32 for
208	// setcc operations results (slt, sgt, ...).
209	setBooleanContents(ZeroOrOneBooleanContent);
210	setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
211	// The cmp.cond.fmt instruction in MIPS32r6/MIPS64r6 uses 0 and -1 like MSA
212	// does. Integer booleans still use 0 and 1.
213	if (Subtarget.hasMips32r6())
214	setBooleanContents(ZeroOrOneBooleanContent,
215	ZeroOrNegativeOneBooleanContent);
216
217	// Load extented operations for i1 types must be promoted
218	for (MVT VT : MVT::integer_valuetypes()) {
219	setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
220	setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
221	setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
222	}
223
224	// MIPS doesn't have extending float->double load/store
225	for (MVT VT : MVT::fp_valuetypes())
226	setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
227	setTruncStoreAction(MVT::f64, MVT::f32, Expand);
228
229	// Used by legalize types to correctly generate the setcc result.
230	// Without this, every float setcc comes with a AND/OR with the result,
231	// we don't want this, since the fpcmp result goes to a flag register,
232	// which is used implicitly by brcond and select operations.
233	AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
234
235	// Mips Custom Operations
236	setOperationAction(ISD::BR_JT, MVT::Other, Custom);
237	setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
238	setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
239	setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
240	setOperationAction(ISD::JumpTable, MVT::i32, Custom);
241	setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
242	setOperationAction(ISD::SELECT, MVT::f32, Custom);
243	setOperationAction(ISD::SELECT, MVT::f64, Custom);
244	setOperationAction(ISD::SELECT, MVT::i32, Custom);
245	setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
246	setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
247	setOperationAction(ISD::SETCC, MVT::f32, Custom);
248	setOperationAction(ISD::SETCC, MVT::f64, Custom);
249	setOperationAction(ISD::BRCOND, MVT::Other, Custom);
250	setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
251	setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
252	setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
253
254	if (Subtarget.isGP64bit()) {
255	setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
256	setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
257	setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
258	setOperationAction(ISD::JumpTable, MVT::i64, Custom);
259	setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
260	setOperationAction(ISD::SELECT, MVT::i64, Custom);
261	setOperationAction(ISD::LOAD, MVT::i64, Custom);
262	setOperationAction(ISD::STORE, MVT::i64, Custom);
263	setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
264	setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
265	setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
266	setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
267	}
268
269	if (!Subtarget.isGP64bit()) {
270	setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
271	setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
272	setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
273	}
274
275	setOperationAction(ISD::ADD, MVT::i32, Custom);
276	if (Subtarget.isGP64bit())
277	setOperationAction(ISD::ADD, MVT::i64, Custom);
278
279	setOperationAction(ISD::SDIV, MVT::i32, Expand);
280	setOperationAction(ISD::SREM, MVT::i32, Expand);
281	setOperationAction(ISD::UDIV, MVT::i32, Expand);
282	setOperationAction(ISD::UREM, MVT::i32, Expand);
283	setOperationAction(ISD::SDIV, MVT::i64, Expand);
284	setOperationAction(ISD::SREM, MVT::i64, Expand);
285	setOperationAction(ISD::UDIV, MVT::i64, Expand);
286	setOperationAction(ISD::UREM, MVT::i64, Expand);
287
288	// Operations not directly supported by Mips.
289	setOperationAction(ISD::BR_CC, MVT::f32, Expand);
290	setOperationAction(ISD::BR_CC, MVT::f64, Expand);
291	setOperationAction(ISD::BR_CC, MVT::i32, Expand);
292	setOperationAction(ISD::BR_CC, MVT::i64, Expand);
293	setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
294	setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
295	setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
296	setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
297	setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
298	setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
299	setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
300	if (Subtarget.hasCnMips()) {
301	setOperationAction(ISD::CTPOP, MVT::i32, Legal);
302	setOperationAction(ISD::CTPOP, MVT::i64, Legal);
303	} else {
304	setOperationAction(ISD::CTPOP, MVT::i32, Expand);
305	setOperationAction(ISD::CTPOP, MVT::i64, Expand);
306	}
307	setOperationAction(ISD::CTTZ, MVT::i32, Expand);
308	setOperationAction(ISD::CTTZ, MVT::i64, Expand);
309	setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
310	setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
311	setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
312	setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
313	setOperationAction(ISD::ROTL, MVT::i32, Expand);
314	setOperationAction(ISD::ROTL, MVT::i64, Expand);
315	setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
316	setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
317
318	if (!Subtarget.hasMips32r2())
319	setOperationAction(ISD::ROTR, MVT::i32, Expand);
320
321	if (!Subtarget.hasMips64r2())
322	setOperationAction(ISD::ROTR, MVT::i64, Expand);
323
324	setOperationAction(ISD::FSIN, MVT::f32, Expand);
325	setOperationAction(ISD::FSIN, MVT::f64, Expand);
326	setOperationAction(ISD::FCOS, MVT::f32, Expand);
327	setOperationAction(ISD::FCOS, MVT::f64, Expand);
328	setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
329	setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
330	setOperationAction(ISD::FPOWI, MVT::f32, Expand);
331	setOperationAction(ISD::FPOW, MVT::f32, Expand);
332	setOperationAction(ISD::FPOW, MVT::f64, Expand);
333	setOperationAction(ISD::FLOG, MVT::f32, Expand);
334	setOperationAction(ISD::FLOG2, MVT::f32, Expand);
335	setOperationAction(ISD::FLOG10, MVT::f32, Expand);
336	setOperationAction(ISD::FEXP, MVT::f32, Expand);
337	setOperationAction(ISD::FMA, MVT::f32, Expand);
338	setOperationAction(ISD::FMA, MVT::f64, Expand);
339	setOperationAction(ISD::FREM, MVT::f32, Expand);
340	setOperationAction(ISD::FREM, MVT::f64, Expand);
341
342	setOperationAction(ISD::EH_RETURN, MVT::Other, Custom);
343
344	setOperationAction(ISD::VASTART, MVT::Other, Custom);
345	setOperationAction(ISD::VAARG, MVT::Other, Custom);
346	setOperationAction(ISD::VACOPY, MVT::Other, Expand);
347	setOperationAction(ISD::VAEND, MVT::Other, Expand);
348
349	// Use the default for now
350	setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
351	setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
352
353	setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand);
354	setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
355	setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand);
356	setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
357
358	setInsertFencesForAtomic(true);
359
360	if (!Subtarget.hasMips32r2()) {
361	setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
362	setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
363	}
364
365	// MIPS16 lacks MIPS32's clz and clo instructions.
366	if (!Subtarget.hasMips32() \|\| Subtarget.inMips16Mode())
367	setOperationAction(ISD::CTLZ, MVT::i32, Expand);
368	if (!Subtarget.hasMips64())
369	setOperationAction(ISD::CTLZ, MVT::i64, Expand);
370
371	if (!Subtarget.hasMips32r2())
372	setOperationAction(ISD::BSWAP, MVT::i32, Expand);
373	if (!Subtarget.hasMips64r2())
374	setOperationAction(ISD::BSWAP, MVT::i64, Expand);
375
376	if (Subtarget.isGP64bit()) {
377	setLoadExtAction(ISD::SEXTLOAD, MVT::i64, MVT::i32, Custom);
378	setLoadExtAction(ISD::ZEXTLOAD, MVT::i64, MVT::i32, Custom);
379	setLoadExtAction(ISD::EXTLOAD, MVT::i64, MVT::i32, Custom);
380	setTruncStoreAction(MVT::i64, MVT::i32, Custom);
381	}
382
383	setOperationAction(ISD::TRAP, MVT::Other, Legal);
384
385	setTargetDAGCombine(ISD::SDIVREM);
386	setTargetDAGCombine(ISD::UDIVREM);
387	setTargetDAGCombine(ISD::SELECT);
388	setTargetDAGCombine(ISD::AND);
389	setTargetDAGCombine(ISD::OR);
390	setTargetDAGCombine(ISD::ADD);
391
392	setMinFunctionAlignment(Subtarget.isGP64bit() ? 3 : 2);
393
394	// The arguments on the stack are defined in terms of 4-byte slots on O32
395	// and 8-byte slots on N32/N64.
396	setMinStackArgumentAlignment(
397	(Subtarget.isABI_N32() \|\| Subtarget.isABI_N64()) ? 8 : 4);
398
399	setStackPointerRegisterToSaveRestore(Subtarget.isABI_N64() ? Mips::SP_64
400	: Mips::SP);
401
402	setExceptionPointerRegister(Subtarget.isABI_N64() ? Mips::A0_64 : Mips::A0);
403	setExceptionSelectorRegister(Subtarget.isABI_N64() ? Mips::A1_64 : Mips::A1);
404
405	MaxStoresPerMemcpy = 16;
406
407	isMicroMips = Subtarget.inMicroMipsMode();
408	}
409
410	const MipsTargetLowering *MipsTargetLowering::create(const MipsTargetMachine &TM,
411	const MipsSubtarget &STI) {
412	if (STI.inMips16Mode())
413	return llvm::createMips16TargetLowering(TM, STI);
414
415	return llvm::createMipsSETargetLowering(TM, STI);
416	}
417
418	// Create a fast isel object.
419	FastISel *
420	MipsTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
421	const TargetLibraryInfo *libInfo) const {
422	if (!EnableMipsFastISel)
423	return TargetLowering::createFastISel(funcInfo, libInfo);
424	return Mips::createFastISel(funcInfo, libInfo);
425	}
426
427	EVT MipsTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
428	if (!VT.isVector())
429	return MVT::i32;
430	return VT.changeVectorElementTypeToInteger();
431	}
432
433	static SDValue performDivRemCombine(SDNode *N, SelectionDAG &DAG,
434	TargetLowering::DAGCombinerInfo &DCI,
435	const MipsSubtarget &Subtarget) {
436	if (DCI.isBeforeLegalizeOps())
437	return SDValue();
438
439	EVT Ty = N->getValueType(0);
440	unsigned LO = (Ty == MVT::i32) ? Mips::LO0 : Mips::LO0_64;
441	unsigned HI = (Ty == MVT::i32) ? Mips::HI0 : Mips::HI0_64;
442	unsigned Opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem16 :
443	MipsISD::DivRemU16;
444	SDLoc DL(N);
445
446	SDValue DivRem = DAG.getNode(Opc, DL, MVT::Glue,
447	N->getOperand(0), N->getOperand(1));
448	SDValue InChain = DAG.getEntryNode();
449	SDValue InGlue = DivRem;
450
451	// insert MFLO
452	if (N->hasAnyUseOfValue(0)) {
453	SDValue CopyFromLo = DAG.getCopyFromReg(InChain, DL, LO, Ty,
454	InGlue);
455	DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo);
456	InChain = CopyFromLo.getValue(1);
457	InGlue = CopyFromLo.getValue(2);
458	}
459
460	// insert MFHI
461	if (N->hasAnyUseOfValue(1)) {
462	SDValue CopyFromHi = DAG.getCopyFromReg(InChain, DL,
463	HI, Ty, InGlue);
464	DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi);
465	}
466
467	return SDValue();
468	}
469
470	static Mips::CondCode condCodeToFCC(ISD::CondCode CC) {
471	switch (CC) {
472	default: llvm_unreachable("Unknown fp condition code!")::llvm::llvm_unreachable_internal("Unknown fp condition code!" , "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn227492/lib/Target/Mips/MipsISelLowering.cpp" , 472);
473	case ISD::SETEQ:
474	case ISD::SETOEQ: return Mips::FCOND_OEQ;
475	case ISD::SETUNE: return Mips::FCOND_UNE;
476	case ISD::SETLT:
477	case ISD::SETOLT: return Mips::FCOND_OLT;
478	case ISD::SETGT:
479	case ISD::SETOGT: return Mips::FCOND_OGT;
480	case ISD::SETLE:
481	case ISD::SETOLE: return Mips::FCOND_OLE;
482	case ISD::SETGE:
483	case ISD::SETOGE: return Mips::FCOND_OGE;
484	case ISD::SETULT: return Mips::FCOND_ULT;
485	case ISD::SETULE: return Mips::FCOND_ULE;
486	case ISD::SETUGT: return Mips::FCOND_UGT;
487	case ISD::SETUGE: return Mips::FCOND_UGE;
488	case ISD::SETUO: return Mips::FCOND_UN;
489	case ISD::SETO: return Mips::FCOND_OR;
490	case ISD::SETNE:
491	case ISD::SETONE: return Mips::FCOND_ONE;
492	case ISD::SETUEQ: return Mips::FCOND_UEQ;
493	}
494	}
495
496
497	/// This function returns true if the floating point conditional branches and
498	/// conditional moves which use condition code CC should be inverted.
499	static bool invertFPCondCodeUser(Mips::CondCode CC) {
500	if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
501	return false;
502
503	assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) &&(((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) && "Illegal Condition Code") ? static_cast<void> (0) : __assert_fail ("(CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) && \"Illegal Condition Code\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn227492/lib/Target/Mips/MipsISelLowering.cpp" , 504, __PRETTY_FUNCTION__))
504	"Illegal Condition Code")(((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) && "Illegal Condition Code") ? static_cast<void> (0) : __assert_fail ("(CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) && \"Illegal Condition Code\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn227492/lib/Target/Mips/MipsISelLowering.cpp" , 504, __PRETTY_FUNCTION__));
505
506	return true;
507	}
508
509	// Creates and returns an FPCmp node from a setcc node.
510	// Returns Op if setcc is not a floating point comparison.
511	static SDValue createFPCmp(SelectionDAG &DAG, const SDValue &Op) {
512	// must be a SETCC node
513	if (Op.getOpcode() != ISD::SETCC)
514	return Op;
515
516	SDValue LHS = Op.getOperand(0);
517
518	if (!LHS.getValueType().isFloatingPoint())
519	return Op;
520
521	SDValue RHS = Op.getOperand(1);
522	SDLoc DL(Op);
523
524	// Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of
525	// node if necessary.
526	ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
527
528	return DAG.getNode(MipsISD::FPCmp, DL, MVT::Glue, LHS, RHS,
529	DAG.getConstant(condCodeToFCC(CC), MVT::i32));
530	}
531
532	// Creates and returns a CMovFPT/F node.
533	static SDValue createCMovFP(SelectionDAG &DAG, SDValue Cond, SDValue True,
534	SDValue False, SDLoc DL) {
535	ConstantSDNode *CC = cast<ConstantSDNode>(Cond.getOperand(2));
536	bool invert = invertFPCondCodeUser((Mips::CondCode)CC->getSExtValue());
537	SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32);
538
539	return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL,
540	True.getValueType(), True, FCC0, False, Cond);
541	}
542
543	static SDValue performSELECTCombine(SDNode *N, SelectionDAG &DAG,
544	TargetLowering::DAGCombinerInfo &DCI,
545	const MipsSubtarget &Subtarget) {
546	if (DCI.isBeforeLegalizeOps())
547	return SDValue();
548
549	SDValue SetCC = N->getOperand(0);
550
551	if ((SetCC.getOpcode() != ISD::SETCC) \|\|
552	!SetCC.getOperand(0).getValueType().isInteger())
553	return SDValue();
554
555	SDValue False = N->getOperand(2);
556	EVT FalseTy = False.getValueType();
557
558	if (!FalseTy.isInteger())
559	return SDValue();
560
561	ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(False);
562
563	// If the RHS (False) is 0, we swap the order of the operands
564	// of ISD::SELECT (obviously also inverting the condition) so that we can
565	// take advantage of conditional moves using the $0 register.
566	// Example:
567	// return (a != 0) ? x : 0;
568	// load $reg, x
569	// movz $reg, $0, a
570	if (!FalseC)
571	return SDValue();
572
573	const SDLoc DL(N);
574
575	if (!FalseC->getZExtValue()) {
576	ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get();
577	SDValue True = N->getOperand(1);
578
579	SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0),
580	SetCC.getOperand(1), ISD::getSetCCInverse(CC, true));
581
582	return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True);
583	}
584
585	// If both operands are integer constants there's a possibility that we
586	// can do some interesting optimizations.
587	SDValue True = N->getOperand(1);
588	ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(True);
589
590	if (!TrueC \|\| !True.getValueType().isInteger())
591	return SDValue();
592
593	// We'll also ignore MVT::i64 operands as this optimizations proves
594	// to be ineffective because of the required sign extensions as the result
595	// of a SETCC operator is always MVT::i32 for non-vector types.
596	if (True.getValueType() == MVT::i64)
597	return SDValue();
598
599	int64_t Diff = TrueC->getSExtValue() - FalseC->getSExtValue();
600
601	// 1) (a < x) ? y : y-1
602	// slti $reg1, a, x
603	// addiu $reg2, $reg1, y-1
604	if (Diff == 1)
605	return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, False);
606
607	// 2) (a < x) ? y-1 : y
608	// slti $reg1, a, x
609	// xor $reg1, $reg1, 1
610	// addiu $reg2, $reg1, y-1
611	if (Diff == -1) {
612	ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get();
613	SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0),
614	SetCC.getOperand(1), ISD::getSetCCInverse(CC, true));
615	return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, True);
616	}
617
618	// Couldn't optimize.
619	return SDValue();
620	}
621
622	static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG,
623	TargetLowering::DAGCombinerInfo &DCI,
624	const MipsSubtarget &Subtarget) {
625	// Pattern match EXT.
626	// $dst = and ((sra or srl) $src , pos), (2**size - 1)
627	// => ext $dst, $src, size, pos
628	if (DCI.isBeforeLegalizeOps() \|\| !Subtarget.hasExtractInsert())
629	return SDValue();
630
631	SDValue ShiftRight = N->getOperand(0), Mask = N->getOperand(1);
632	unsigned ShiftRightOpc = ShiftRight.getOpcode();
633
634	// Op's first operand must be a shift right.
635	if (ShiftRightOpc != ISD::SRA && ShiftRightOpc != ISD::SRL)
636	return SDValue();
637
638	// The second operand of the shift must be an immediate.
639	ConstantSDNode *CN;
640	if (!(CN = dyn_cast<ConstantSDNode>(ShiftRight.getOperand(1))))
641	return SDValue();
642
643	uint64_t Pos = CN->getZExtValue();
644	uint64_t SMPos, SMSize;
645
646	// Op's second operand must be a shifted mask.
647	if (!(CN = dyn_cast<ConstantSDNode>(Mask)) \|\|
648	!isShiftedMask(CN->getZExtValue(), SMPos, SMSize))
649	return SDValue();
650
651	// Return if the shifted mask does not start at bit 0 or the sum of its size
652	// and Pos exceeds the word's size.
653	EVT ValTy = N->getValueType(0);
654	if (SMPos != 0 \|\| Pos + SMSize > ValTy.getSizeInBits())
655	return SDValue();
656
657	return DAG.getNode(MipsISD::Ext, SDLoc(N), ValTy,
658	ShiftRight.getOperand(0), DAG.getConstant(Pos, MVT::i32),
659	DAG.getConstant(SMSize, MVT::i32));
660	}
661
662	static SDValue performORCombine(SDNode *N, SelectionDAG &DAG,
663	TargetLowering::DAGCombinerInfo &DCI,
664	const MipsSubtarget &Subtarget) {
665	// Pattern match INS.
666	// $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1),
667	// where mask1 = (2**size - 1) << pos, mask0 = ~mask1
668	// => ins $dst, $src, size, pos, $src1
669	if (DCI.isBeforeLegalizeOps() \|\| !Subtarget.hasExtractInsert())
670	return SDValue();
671
672	SDValue And0 = N->getOperand(0), And1 = N->getOperand(1);
673	uint64_t SMPos0, SMSize0, SMPos1, SMSize1;
674	ConstantSDNode *CN;
675
676	// See if Op's first operand matches (and $src1 , mask0).
677	if (And0.getOpcode() != ISD::AND)
678	return SDValue();
679
680	if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) \|\|
681	!isShiftedMask(~CN->getSExtValue(), SMPos0, SMSize0))
682	return SDValue();
683
684	// See if Op's second operand matches (and (shl $src, pos), mask1).
685	if (And1.getOpcode() != ISD::AND)
686	return SDValue();
687
688	if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) \|\|
689	!isShiftedMask(CN->getZExtValue(), SMPos1, SMSize1))
690	return SDValue();
691
692	// The shift masks must have the same position and size.
693	if (SMPos0 != SMPos1 \|\| SMSize0 != SMSize1)
694	return SDValue();
695
696	SDValue Shl = And1.getOperand(0);
697	if (Shl.getOpcode() != ISD::SHL)
698	return SDValue();
699
700	if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1))))
701	return SDValue();
702
703	unsigned Shamt = CN->getZExtValue();
704
705	// Return if the shift amount and the first bit position of mask are not the
706	// same.
707	EVT ValTy = N->getValueType(0);
708	if ((Shamt != SMPos0) \|\| (SMPos0 + SMSize0 > ValTy.getSizeInBits()))
709	return SDValue();
710
711	return DAG.getNode(MipsISD::Ins, SDLoc(N), ValTy, Shl.getOperand(0),
712	DAG.getConstant(SMPos0, MVT::i32),
713	DAG.getConstant(SMSize0, MVT::i32), And0.getOperand(0));
714	}
715
716	static SDValue performADDCombine(SDNode *N, SelectionDAG &DAG,
717	TargetLowering::DAGCombinerInfo &DCI,
718	const MipsSubtarget &Subtarget) {
719	// (add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt))
720
721	if (DCI.isBeforeLegalizeOps())
722	return SDValue();
723
724	SDValue Add = N->getOperand(1);
725
726	if (Add.getOpcode() != ISD::ADD)
727	return SDValue();
728
729	SDValue Lo = Add.getOperand(1);
730
731	if ((Lo.getOpcode() != MipsISD::Lo) \|\|
732	(Lo.getOperand(0).getOpcode() != ISD::TargetJumpTable))
733	return SDValue();
734
735	EVT ValTy = N->getValueType(0);
736	SDLoc DL(N);
737
738	SDValue Add1 = DAG.getNode(ISD::ADD, DL, ValTy, N->getOperand(0),
739	Add.getOperand(0));
740	return DAG.getNode(ISD::ADD, DL, ValTy, Add1, Lo);
741	}
742
743	SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI)
744	const {
745	SelectionDAG &DAG = DCI.DAG;
746	unsigned Opc = N->getOpcode();
747
748	switch (Opc) {
749	default: break;
750	case ISD::SDIVREM:
751	case ISD::UDIVREM:
752	return performDivRemCombine(N, DAG, DCI, Subtarget);
753	case ISD::SELECT:
754	return performSELECTCombine(N, DAG, DCI, Subtarget);
755	case ISD::AND:
756	return performANDCombine(N, DAG, DCI, Subtarget);
757	case ISD::OR:
758	return performORCombine(N, DAG, DCI, Subtarget);
759	case ISD::ADD:
760	return performADDCombine(N, DAG, DCI, Subtarget);
761	}
762
763	return SDValue();
764	}
765
766	void
767	MipsTargetLowering::LowerOperationWrapper(SDNode *N,
768	SmallVectorImpl<SDValue> &Results,
769	SelectionDAG &DAG) const {
770	SDValue Res = LowerOperation(SDValue(N, 0), DAG);
771
772	for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I)
773	Results.push_back(Res.getValue(I));
774	}
775
776	void
777	MipsTargetLowering::ReplaceNodeResults(SDNode *N,
778	SmallVectorImpl<SDValue> &Results,
779	SelectionDAG &DAG) const {
780	return LowerOperationWrapper(N, Results, DAG);
781	}
782
783	SDValue MipsTargetLowering::
784	LowerOperation(SDValue Op, SelectionDAG &DAG) const
785	{
786	switch (Op.getOpcode())
787	{
788	case ISD::BR_JT: return lowerBR_JT(Op, DAG);
789	case ISD::BRCOND: return lowerBRCOND(Op, DAG);
790	case ISD::ConstantPool: return lowerConstantPool(Op, DAG);
791	case ISD::GlobalAddress: return lowerGlobalAddress(Op, DAG);
792	case ISD::BlockAddress: return lowerBlockAddress(Op, DAG);
793	case ISD::GlobalTLSAddress: return lowerGlobalTLSAddress(Op, DAG);
794	case ISD::JumpTable: return lowerJumpTable(Op, DAG);
795	case ISD::SELECT: return lowerSELECT(Op, DAG);
796	case ISD::SELECT_CC: return lowerSELECT_CC(Op, DAG);
797	case ISD::SETCC: return lowerSETCC(Op, DAG);
798	case ISD::VASTART: return lowerVASTART(Op, DAG);
799	case ISD::VAARG: return lowerVAARG(Op, DAG);
800	case ISD::FCOPYSIGN: return lowerFCOPYSIGN(Op, DAG);
801	case ISD::FRAMEADDR: return lowerFRAMEADDR(Op, DAG);
802	case ISD::RETURNADDR: return lowerRETURNADDR(Op, DAG);
803	case ISD::EH_RETURN: return lowerEH_RETURN(Op, DAG);
804	case ISD::ATOMIC_FENCE: return lowerATOMIC_FENCE(Op, DAG);
805	case ISD::SHL_PARTS: return lowerShiftLeftParts(Op, DAG);
806	case ISD::SRA_PARTS: return lowerShiftRightParts(Op, DAG, true);
807	case ISD::SRL_PARTS: return lowerShiftRightParts(Op, DAG, false);
808	case ISD::LOAD: return lowerLOAD(Op, DAG);
809	case ISD::STORE: return lowerSTORE(Op, DAG);
810	case ISD::ADD: return lowerADD(Op, DAG);
811	case ISD::FP_TO_SINT: return lowerFP_TO_SINT(Op, DAG);
812	}
813	return SDValue();
814	}
815
816	//===----------------------------------------------------------------------===//
817	// Lower helper functions
818	//===----------------------------------------------------------------------===//
819
820	// addLiveIn - This helper function adds the specified physical register to the
821	// MachineFunction as a live in value. It also creates a corresponding
822	// virtual register for it.
823	static unsigned
824	addLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC)
825	{
826	unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
827	MF.getRegInfo().addLiveIn(PReg, VReg);
828	return VReg;
829	}
830
831	static MachineBasicBlock insertDivByZeroTrap(MachineInstr MI,
832	MachineBasicBlock &MBB,
833	const TargetInstrInfo &TII,
834	bool Is64Bit) {
835	if (NoZeroDivCheck)
836	return &MBB;
837
838	// Insert instruction "teq $divisor_reg, $zero, 7".
839	MachineBasicBlock::iterator I(MI);
840	MachineInstrBuilder MIB;
841	MachineOperand &Divisor = MI->getOperand(2);
842	MIB = BuildMI(MBB, std::next(I), MI->getDebugLoc(), TII.get(Mips::TEQ))
843	.addReg(Divisor.getReg(), getKillRegState(Divisor.isKill()))
844	.addReg(Mips::ZERO).addImm(7);
845
846	// Use the 32-bit sub-register if this is a 64-bit division.
847	if (Is64Bit)
848	MIB->getOperand(0).setSubReg(Mips::sub_32);
849
850	// Clear Divisor's kill flag.
851	Divisor.setIsKill(false);
852
853	// We would normally delete the original instruction here but in this case
854	// we only needed to inject an additional instruction rather than replace it.
855
856	return &MBB;
857	}
858
859	MachineBasicBlock *
860	MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
861	MachineBasicBlock *BB) const {
862	switch (MI->getOpcode()) {
863	default:
864	llvm_unreachable("Unexpected instr type to insert")::llvm::llvm_unreachable_internal("Unexpected instr type to insert" , "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn227492/lib/Target/Mips/MipsISelLowering.cpp" , 864);
865	case Mips::ATOMIC_LOAD_ADD_I8:
866	return emitAtomicBinaryPartword(MI, BB, 1, Mips::ADDu);
867	case Mips::ATOMIC_LOAD_ADD_I16:
868	return emitAtomicBinaryPartword(MI, BB, 2, Mips::ADDu);
869	case Mips::ATOMIC_LOAD_ADD_I32:
870	return emitAtomicBinary(MI, BB, 4, Mips::ADDu);
871	case Mips::ATOMIC_LOAD_ADD_I64:
872	return emitAtomicBinary(MI, BB, 8, Mips::DADDu);
873
874	case Mips::ATOMIC_LOAD_AND_I8:
875	return emitAtomicBinaryPartword(MI, BB, 1, Mips::AND);
876	case Mips::ATOMIC_LOAD_AND_I16:
877	return emitAtomicBinaryPartword(MI, BB, 2, Mips::AND);
878	case Mips::ATOMIC_LOAD_AND_I32:
879	return emitAtomicBinary(MI, BB, 4, Mips::AND);
880	case Mips::ATOMIC_LOAD_AND_I64:
881	return emitAtomicBinary(MI, BB, 8, Mips::AND64);
882
883	case Mips::ATOMIC_LOAD_OR_I8:
884	return emitAtomicBinaryPartword(MI, BB, 1, Mips::OR);
885	case Mips::ATOMIC_LOAD_OR_I16:
886	return emitAtomicBinaryPartword(MI, BB, 2, Mips::OR);
887	case Mips::ATOMIC_LOAD_OR_I32:
888	return emitAtomicBinary(MI, BB, 4, Mips::OR);
889	case Mips::ATOMIC_LOAD_OR_I64:
890	return emitAtomicBinary(MI, BB, 8, Mips::OR64);
891
892	case Mips::ATOMIC_LOAD_XOR_I8:
893	return emitAtomicBinaryPartword(MI, BB, 1, Mips::XOR);
894	case Mips::ATOMIC_LOAD_XOR_I16:
895	return emitAtomicBinaryPartword(MI, BB, 2, Mips::XOR);
896	case Mips::ATOMIC_LOAD_XOR_I32:
897	return emitAtomicBinary(MI, BB, 4, Mips::XOR);
898	case Mips::ATOMIC_LOAD_XOR_I64:
899	return emitAtomicBinary(MI, BB, 8, Mips::XOR64);
900
901	case Mips::ATOMIC_LOAD_NAND_I8:
902	return emitAtomicBinaryPartword(MI, BB, 1, 0, true);
903	case Mips::ATOMIC_LOAD_NAND_I16:
904	return emitAtomicBinaryPartword(MI, BB, 2, 0, true);
905	case Mips::ATOMIC_LOAD_NAND_I32:
906	return emitAtomicBinary(MI, BB, 4, 0, true);
907	case Mips::ATOMIC_LOAD_NAND_I64:
908	return emitAtomicBinary(MI, BB, 8, 0, true);
909
910	case Mips::ATOMIC_LOAD_SUB_I8:
911	return emitAtomicBinaryPartword(MI, BB, 1, Mips::SUBu);
912	case Mips::ATOMIC_LOAD_SUB_I16:
913	return emitAtomicBinaryPartword(MI, BB, 2, Mips::SUBu);
914	case Mips::ATOMIC_LOAD_SUB_I32:
915	return emitAtomicBinary(MI, BB, 4, Mips::SUBu);
916	case Mips::ATOMIC_LOAD_SUB_I64:
917	return emitAtomicBinary(MI, BB, 8, Mips::DSUBu);
918
919	case Mips::ATOMIC_SWAP_I8:
920	return emitAtomicBinaryPartword(MI, BB, 1, 0);
921	case Mips::ATOMIC_SWAP_I16:
922	return emitAtomicBinaryPartword(MI, BB, 2, 0);
923	case Mips::ATOMIC_SWAP_I32:
924	return emitAtomicBinary(MI, BB, 4, 0);
925	case Mips::ATOMIC_SWAP_I64:
926	return emitAtomicBinary(MI, BB, 8, 0);
927
928	case Mips::ATOMIC_CMP_SWAP_I8:
929	return emitAtomicCmpSwapPartword(MI, BB, 1);
930	case Mips::ATOMIC_CMP_SWAP_I16:
931	return emitAtomicCmpSwapPartword(MI, BB, 2);
932	case Mips::ATOMIC_CMP_SWAP_I32:
933	return emitAtomicCmpSwap(MI, BB, 4);
934	case Mips::ATOMIC_CMP_SWAP_I64:
935	return emitAtomicCmpSwap(MI, BB, 8);
936	case Mips::PseudoSDIV:
937	case Mips::PseudoUDIV:
938	case Mips::DIV:
939	case Mips::DIVU:
940	case Mips::MOD:
941	case Mips::MODU:
942	return insertDivByZeroTrap(
943	MI, BB, getTargetMachine().getSubtargetImpl()->getInstrInfo(), false);
944	case Mips::PseudoDSDIV:
945	case Mips::PseudoDUDIV:
946	case Mips::DDIV:
947	case Mips::DDIVU:
948	case Mips::DMOD:
949	case Mips::DMODU:
950	return insertDivByZeroTrap(
951	MI, BB, getTargetMachine().getSubtargetImpl()->getInstrInfo(), true);
952	case Mips::SEL_D:
953	return emitSEL_D(MI, BB);
954
955	case Mips::PseudoSELECT_I:
956	case Mips::PseudoSELECT_I64:
957	case Mips::PseudoSELECT_S:
958	case Mips::PseudoSELECT_D32:
959	case Mips::PseudoSELECT_D64:
960	return emitPseudoSELECT(MI, BB, false, Mips::BNE);
961	case Mips::PseudoSELECTFP_F_I:
962	case Mips::PseudoSELECTFP_F_I64:
963	case Mips::PseudoSELECTFP_F_S:
964	case Mips::PseudoSELECTFP_F_D32:
965	case Mips::PseudoSELECTFP_F_D64:
966	return emitPseudoSELECT(MI, BB, true, Mips::BC1F);
967	case Mips::PseudoSELECTFP_T_I:
968	case Mips::PseudoSELECTFP_T_I64:
969	case Mips::PseudoSELECTFP_T_S:
970	case Mips::PseudoSELECTFP_T_D32:
971	case Mips::PseudoSELECTFP_T_D64:
972	return emitPseudoSELECT(MI, BB, true, Mips::BC1T);
973	}
974	}
975
976	// This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and
977	// Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true)
978	MachineBasicBlock *
979	MipsTargetLowering::emitAtomicBinary(MachineInstr MI, MachineBasicBlock BB,
980	unsigned Size, unsigned BinOpcode,
981	bool Nand) const {
982	assert((Size == 4 \|\| Size == 8) && "Unsupported size for EmitAtomicBinary.")(((Size == 4 \|\| Size == 8) && "Unsupported size for EmitAtomicBinary." ) ? static_cast<void> (0) : __assert_fail ("(Size == 4 \|\| Size == 8) && \"Unsupported size for EmitAtomicBinary.\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn227492/lib/Target/Mips/MipsISelLowering.cpp" , 982, __PRETTY_FUNCTION__));
983
984	MachineFunction *MF = BB->getParent();
985	MachineRegisterInfo &RegInfo = MF->getRegInfo();
986	const TargetRegisterClass RC = getRegClassFor(MVT::getIntegerVT(Size 8));
987	const TargetInstrInfo *TII =
988	getTargetMachine().getSubtargetImpl()->getInstrInfo();
989	DebugLoc DL = MI->getDebugLoc();
990	unsigned LL, SC, AND, NOR, ZERO, BEQ;
991
992	if (Size == 4) {
993	if (isMicroMips) {
994	LL = Mips::LL_MM;
995	SC = Mips::SC_MM;
996	} else {
997	LL = Subtarget.hasMips32r6() ? Mips::LL_R6 : Mips::LL;
998	SC = Subtarget.hasMips32r6() ? Mips::SC_R6 : Mips::SC;
999	}
1000	AND = Mips::AND;
1001	NOR = Mips::NOR;
1002	ZERO = Mips::ZERO;
1003	BEQ = Mips::BEQ;
1004	} else {
1005	LL = Subtarget.hasMips64r6() ? Mips::LLD_R6 : Mips::LLD;
1006	SC = Subtarget.hasMips64r6() ? Mips::SCD_R6 : Mips::SCD;
1007	AND = Mips::AND64;
1008	NOR = Mips::NOR64;
1009	ZERO = Mips::ZERO_64;
1010	BEQ = Mips::BEQ64;
1011	}
1012
1013	unsigned OldVal = MI->getOperand(0).getReg();
1014	unsigned Ptr = MI->getOperand(1).getReg();
1015	unsigned Incr = MI->getOperand(2).getReg();
1016
1017	unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1018	unsigned AndRes = RegInfo.createVirtualRegister(RC);
1019	unsigned Success = RegInfo.createVirtualRegister(RC);
1020
1021	// insert new blocks after the current block
1022	const BasicBlock *LLVM_BB = BB->getBasicBlock();
1023	MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1024	MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1025	MachineFunction::iterator It = BB;
1026	++It;
1027	MF->insert(It, loopMBB);
1028	MF->insert(It, exitMBB);
1029
1030	// Transfer the remainder of BB and its successor edges to exitMBB.
1031	exitMBB->splice(exitMBB->begin(), BB,
1032	std::next(MachineBasicBlock::iterator(MI)), BB->end());
1033	exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1034
1035	// thisMBB:
1036	// ...
1037	// fallthrough --> loopMBB
1038	BB->addSuccessor(loopMBB);
1039	loopMBB->addSuccessor(loopMBB);
1040	loopMBB->addSuccessor(exitMBB);
1041
1042	// loopMBB:
1043	// ll oldval, 0(ptr)
1044	// <binop> storeval, oldval, incr
1045	// sc success, storeval, 0(ptr)
1046	// beq success, $0, loopMBB
1047	BB = loopMBB;
1048	BuildMI(BB, DL, TII->get(LL), OldVal).addReg(Ptr).addImm(0);
1049	if (Nand) {
1050	// and andres, oldval, incr
1051	// nor storeval, $0, andres
1052	BuildMI(BB, DL, TII->get(AND), AndRes).addReg(OldVal).addReg(Incr);
1053	BuildMI(BB, DL, TII->get(NOR), StoreVal).addReg(ZERO).addReg(AndRes);
1054	} else if (BinOpcode) {
1055	// <binop> storeval, oldval, incr
1056	BuildMI(BB, DL, TII->get(BinOpcode), StoreVal).addReg(OldVal).addReg(Incr);
1057	} else {
1058	StoreVal = Incr;
1059	}
1060	BuildMI(BB, DL, TII->get(SC), Success).addReg(StoreVal).addReg(Ptr).addImm(0);
1061	BuildMI(BB, DL, TII->get(BEQ)).addReg(Success).addReg(ZERO).addMBB(loopMBB);
1062
1063	MI->eraseFromParent(); // The instruction is gone now.
1064
1065	return exitMBB;
1066	}
1067
1068	MachineBasicBlock *MipsTargetLowering::emitSignExtendToI32InReg(
1069	MachineInstr MI, MachineBasicBlock BB, unsigned Size, unsigned DstReg,
1070	unsigned SrcReg) const {
1071	const TargetInstrInfo *TII =
1072	getTargetMachine().getSubtargetImpl()->getInstrInfo();
1073	DebugLoc DL = MI->getDebugLoc();
1074
1075	if (Subtarget.hasMips32r2() && Size == 1) {
1076	BuildMI(BB, DL, TII->get(Mips::SEB), DstReg).addReg(SrcReg);
1077	return BB;
1078	}
1079
1080	if (Subtarget.hasMips32r2() && Size == 2) {
1081	BuildMI(BB, DL, TII->get(Mips::SEH), DstReg).addReg(SrcReg);
1082	return BB;
1083	}
1084
1085	MachineFunction *MF = BB->getParent();
1086	MachineRegisterInfo &RegInfo = MF->getRegInfo();
1087	const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1088	unsigned ScrReg = RegInfo.createVirtualRegister(RC);
1089
1090	assert(Size < 32)((Size < 32) ? static_cast<void> (0) : __assert_fail ("Size < 32", "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn227492/lib/Target/Mips/MipsISelLowering.cpp" , 1090, __PRETTY_FUNCTION__));
1091	int64_t ShiftImm = 32 - (Size * 8);
1092
1093	BuildMI(BB, DL, TII->get(Mips::SLL), ScrReg).addReg(SrcReg).addImm(ShiftImm);
1094	BuildMI(BB, DL, TII->get(Mips::SRA), DstReg).addReg(ScrReg).addImm(ShiftImm);
1095
1096	return BB;
1097	}
1098
1099	MachineBasicBlock *MipsTargetLowering::emitAtomicBinaryPartword(
1100	MachineInstr MI, MachineBasicBlock BB, unsigned Size, unsigned BinOpcode,
1101	bool Nand) const {
1102	assert((Size == 1 \|\| Size == 2) &&(((Size == 1 \|\| Size == 2) && "Unsupported size for EmitAtomicBinaryPartial." ) ? static_cast<void> (0) : __assert_fail ("(Size == 1 \|\| Size == 2) && \"Unsupported size for EmitAtomicBinaryPartial.\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn227492/lib/Target/Mips/MipsISelLowering.cpp" , 1103, __PRETTY_FUNCTION__))
1103	"Unsupported size for EmitAtomicBinaryPartial.")(((Size == 1 \|\| Size == 2) && "Unsupported size for EmitAtomicBinaryPartial." ) ? static_cast<void> (0) : __assert_fail ("(Size == 1 \|\| Size == 2) && \"Unsupported size for EmitAtomicBinaryPartial.\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn227492/lib/Target/Mips/MipsISelLowering.cpp" , 1103, __PRETTY_FUNCTION__));
1104
1105	MachineFunction *MF = BB->getParent();
1106	MachineRegisterInfo &RegInfo = MF->getRegInfo();
1107	const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1108	const TargetInstrInfo *TII =
1109	getTargetMachine().getSubtargetImpl()->getInstrInfo();
1110	DebugLoc DL = MI->getDebugLoc();
1111
1112	unsigned Dest = MI->getOperand(0).getReg();
1113	unsigned Ptr = MI->getOperand(1).getReg();
1114	unsigned Incr = MI->getOperand(2).getReg();
1115
1116	unsigned AlignedAddr = RegInfo.createVirtualRegister(RC);
1117	unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
1118	unsigned Mask = RegInfo.createVirtualRegister(RC);
1119	unsigned Mask2 = RegInfo.createVirtualRegister(RC);
1120	unsigned NewVal = RegInfo.createVirtualRegister(RC);
1121	unsigned OldVal = RegInfo.createVirtualRegister(RC);
1122	unsigned Incr2 = RegInfo.createVirtualRegister(RC);
1123	unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC);
1124	unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC);
1125	unsigned MaskUpper = RegInfo.createVirtualRegister(RC);
1126	unsigned AndRes = RegInfo.createVirtualRegister(RC);
1127	unsigned BinOpRes = RegInfo.createVirtualRegister(RC);
1128	unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC);
1129	unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1130	unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC);
1131	unsigned SrlRes = RegInfo.createVirtualRegister(RC);
1132	unsigned Success = RegInfo.createVirtualRegister(RC);
1133
1134	// insert new blocks after the current block
1135	const BasicBlock *LLVM_BB = BB->getBasicBlock();
1136	MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1137	MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1138	MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1139	MachineFunction::iterator It = BB;
1140	++It;
1141	MF->insert(It, loopMBB);
1142	MF->insert(It, sinkMBB);
1143	MF->insert(It, exitMBB);
1144
1145	// Transfer the remainder of BB and its successor edges to exitMBB.
1146	exitMBB->splice(exitMBB->begin(), BB,
1147	std::next(MachineBasicBlock::iterator(MI)), BB->end());
1148	exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1149
1150	BB->addSuccessor(loopMBB);
1151	loopMBB->addSuccessor(loopMBB);
1152	loopMBB->addSuccessor(sinkMBB);
1153	sinkMBB->addSuccessor(exitMBB);
1154
1155	// thisMBB:
1156	// addiu masklsb2,$0,-4 # 0xfffffffc
1157	// and alignedaddr,ptr,masklsb2
1158	// andi ptrlsb2,ptr,3
1159	// sll shiftamt,ptrlsb2,3
1160	// ori maskupper,$0,255 # 0xff
1161	// sll mask,maskupper,shiftamt
1162	// nor mask2,$0,mask
1163	// sll incr2,incr,shiftamt
1164
1165	int64_t MaskImm = (Size == 1) ? 255 : 65535;
1166	BuildMI(BB, DL, TII->get(Mips::ADDiu), MaskLSB2)
1167	.addReg(Mips::ZERO).addImm(-4);
1168	BuildMI(BB, DL, TII->get(Mips::AND), AlignedAddr)
1169	.addReg(Ptr).addReg(MaskLSB2);
1170	BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3);
1171	if (Subtarget.isLittle()) {
1172	BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1173	} else {
1174	unsigned Off = RegInfo.createVirtualRegister(RC);
1175	BuildMI(BB, DL, TII->get(Mips::XORi), Off)
1176	.addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2);
1177	BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
1178	}
1179	BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper)
1180	.addReg(Mips::ZERO).addImm(MaskImm);
1181	BuildMI(BB, DL, TII->get(Mips::SLLV), Mask)
1182	.addReg(MaskUpper).addReg(ShiftAmt);
1183	BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
1184	BuildMI(BB, DL, TII->get(Mips::SLLV), Incr2).addReg(Incr).addReg(ShiftAmt);
1185
1186	// atomic.load.binop
1187	// loopMBB:
1188	// ll oldval,0(alignedaddr)
1189	// binop binopres,oldval,incr2
1190	// and newval,binopres,mask
1191	// and maskedoldval0,oldval,mask2
1192	// or storeval,maskedoldval0,newval
1193	// sc success,storeval,0(alignedaddr)
1194	// beq success,$0,loopMBB
1195
1196	// atomic.swap
1197	// loopMBB:
1198	// ll oldval,0(alignedaddr)
1199	// and newval,incr2,mask
1200	// and maskedoldval0,oldval,mask2
1201	// or storeval,maskedoldval0,newval
1202	// sc success,storeval,0(alignedaddr)
1203	// beq success,$0,loopMBB
1204
1205	BB = loopMBB;
1206	unsigned LL = isMicroMips ? Mips::LL_MM : Mips::LL;
1207	BuildMI(BB, DL, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0);
1208	if (Nand) {
1209	// and andres, oldval, incr2
1210	// nor binopres, $0, andres
1211	// and newval, binopres, mask
1212	BuildMI(BB, DL, TII->get(Mips::AND), AndRes).addReg(OldVal).addReg(Incr2);
1213	BuildMI(BB, DL, TII->get(Mips::NOR), BinOpRes)
1214	.addReg(Mips::ZERO).addReg(AndRes);
1215	BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask);
1216	} else if (BinOpcode) {
1217	// <binop> binopres, oldval, incr2
1218	// and newval, binopres, mask
1219	BuildMI(BB, DL, TII->get(BinOpcode), BinOpRes).addReg(OldVal).addReg(Incr2);
1220	BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask);
1221	} else { // atomic.swap
1222	// and newval, incr2, mask
1223	BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(Incr2).addReg(Mask);
1224	}
1225
1226	BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal0)
1227	.addReg(OldVal).addReg(Mask2);
1228	BuildMI(BB, DL, TII->get(Mips::OR), StoreVal)
1229	.addReg(MaskedOldVal0).addReg(NewVal);
1230	unsigned SC = isMicroMips ? Mips::SC_MM : Mips::SC;
1231	BuildMI(BB, DL, TII->get(SC), Success)
1232	.addReg(StoreVal).addReg(AlignedAddr).addImm(0);
1233	BuildMI(BB, DL, TII->get(Mips::BEQ))
1234	.addReg(Success).addReg(Mips::ZERO).addMBB(loopMBB);
1235
1236	// sinkMBB:
1237	// and maskedoldval1,oldval,mask
1238	// srl srlres,maskedoldval1,shiftamt
1239	// sign_extend dest,srlres
1240	BB = sinkMBB;
1241
1242	BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal1)
1243	.addReg(OldVal).addReg(Mask);
1244	BuildMI(BB, DL, TII->get(Mips::SRLV), SrlRes)
1245	.addReg(MaskedOldVal1).addReg(ShiftAmt);
1246	BB = emitSignExtendToI32InReg(MI, BB, Size, Dest, SrlRes);
1247
1248	MI->eraseFromParent(); // The instruction is gone now.
1249
1250	return exitMBB;
1251	}
1252
1253	MachineBasicBlock * MipsTargetLowering::emitAtomicCmpSwap(MachineInstr *MI,
1254	MachineBasicBlock *BB,
1255	unsigned Size) const {
1256	assert((Size == 4 \|\| Size == 8) && "Unsupported size for EmitAtomicCmpSwap.")(((Size == 4 \|\| Size == 8) && "Unsupported size for EmitAtomicCmpSwap." ) ? static_cast<void> (0) : __assert_fail ("(Size == 4 \|\| Size == 8) && \"Unsupported size for EmitAtomicCmpSwap.\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn227492/lib/Target/Mips/MipsISelLowering.cpp" , 1256, __PRETTY_FUNCTION__));
1257
1258	MachineFunction *MF = BB->getParent();
1259	MachineRegisterInfo &RegInfo = MF->getRegInfo();
1260	const TargetRegisterClass RC = getRegClassFor(MVT::getIntegerVT(Size 8));
1261	const TargetInstrInfo *TII =
1262	getTargetMachine().getSubtargetImpl()->getInstrInfo();
1263	DebugLoc DL = MI->getDebugLoc();
1264	unsigned LL, SC, ZERO, BNE, BEQ;
1265
1266	if (Size == 4) {
1267	LL = isMicroMips ? Mips::LL_MM : Mips::LL;
1268	SC = isMicroMips ? Mips::SC_MM : Mips::SC;
1269	ZERO = Mips::ZERO;
1270	BNE = Mips::BNE;
1271	BEQ = Mips::BEQ;
1272	} else {
1273	LL = Mips::LLD;
1274	SC = Mips::SCD;
1275	ZERO = Mips::ZERO_64;
1276	BNE = Mips::BNE64;
1277	BEQ = Mips::BEQ64;
1278	}
1279
1280	unsigned Dest = MI->getOperand(0).getReg();
1281	unsigned Ptr = MI->getOperand(1).getReg();
1282	unsigned OldVal = MI->getOperand(2).getReg();
1283	unsigned NewVal = MI->getOperand(3).getReg();
1284
1285	unsigned Success = RegInfo.createVirtualRegister(RC);
1286
1287	// insert new blocks after the current block
1288	const BasicBlock *LLVM_BB = BB->getBasicBlock();
1289	MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1290	MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1291	MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1292	MachineFunction::iterator It = BB;
1293	++It;
1294	MF->insert(It, loop1MBB);
1295	MF->insert(It, loop2MBB);
1296	MF->insert(It, exitMBB);
1297
1298	// Transfer the remainder of BB and its successor edges to exitMBB.
1299	exitMBB->splice(exitMBB->begin(), BB,
1300	std::next(MachineBasicBlock::iterator(MI)), BB->end());
1301	exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1302
1303	// thisMBB:
1304	// ...
1305	// fallthrough --> loop1MBB
1306	BB->addSuccessor(loop1MBB);
1307	loop1MBB->addSuccessor(exitMBB);
1308	loop1MBB->addSuccessor(loop2MBB);
1309	loop2MBB->addSuccessor(loop1MBB);
1310	loop2MBB->addSuccessor(exitMBB);
1311
1312	// loop1MBB:
1313	// ll dest, 0(ptr)
1314	// bne dest, oldval, exitMBB
1315	BB = loop1MBB;
1316	BuildMI(BB, DL, TII->get(LL), Dest).addReg(Ptr).addImm(0);
1317	BuildMI(BB, DL, TII->get(BNE))
1318	.addReg(Dest).addReg(OldVal).addMBB(exitMBB);
1319
1320	// loop2MBB:
1321	// sc success, newval, 0(ptr)
1322	// beq success, $0, loop1MBB
1323	BB = loop2MBB;
1324	BuildMI(BB, DL, TII->get(SC), Success)
1325	.addReg(NewVal).addReg(Ptr).addImm(0);
1326	BuildMI(BB, DL, TII->get(BEQ))
1327	.addReg(Success).addReg(ZERO).addMBB(loop1MBB);
1328
1329	MI->eraseFromParent(); // The instruction is gone now.
1330
1331	return exitMBB;
1332	}
1333
1334	MachineBasicBlock *
1335	MipsTargetLowering::emitAtomicCmpSwapPartword(MachineInstr *MI,
1336	MachineBasicBlock *BB,
1337	unsigned Size) const {
1338	assert((Size == 1 \|\| Size == 2) &&(((Size == 1 \|\| Size == 2) && "Unsupported size for EmitAtomicCmpSwapPartial." ) ? static_cast<void> (0) : __assert_fail ("(Size == 1 \|\| Size == 2) && \"Unsupported size for EmitAtomicCmpSwapPartial.\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn227492/lib/Target/Mips/MipsISelLowering.cpp" , 1339, __PRETTY_FUNCTION__))
1339	"Unsupported size for EmitAtomicCmpSwapPartial.")(((Size == 1 \|\| Size == 2) && "Unsupported size for EmitAtomicCmpSwapPartial." ) ? static_cast<void> (0) : __assert_fail ("(Size == 1 \|\| Size == 2) && \"Unsupported size for EmitAtomicCmpSwapPartial.\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn227492/lib/Target/Mips/MipsISelLowering.cpp" , 1339, __PRETTY_FUNCTION__));
1340
1341	MachineFunction *MF = BB->getParent();
1342	MachineRegisterInfo &RegInfo = MF->getRegInfo();
1343	const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1344	const TargetInstrInfo *TII =
1345	getTargetMachine().getSubtargetImpl()->getInstrInfo();
1346	DebugLoc DL = MI->getDebugLoc();
1347
1348	unsigned Dest = MI->getOperand(0).getReg();
1349	unsigned Ptr = MI->getOperand(1).getReg();
1350	unsigned CmpVal = MI->getOperand(2).getReg();
1351	unsigned NewVal = MI->getOperand(3).getReg();
1352
1353	unsigned AlignedAddr = RegInfo.createVirtualRegister(RC);
1354	unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
1355	unsigned Mask = RegInfo.createVirtualRegister(RC);
1356	unsigned Mask2 = RegInfo.createVirtualRegister(RC);
1357	unsigned ShiftedCmpVal = RegInfo.createVirtualRegister(RC);
1358	unsigned OldVal = RegInfo.createVirtualRegister(RC);
1359	unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC);
1360	unsigned ShiftedNewVal = RegInfo.createVirtualRegister(RC);
1361	unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC);
1362	unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC);
1363	unsigned MaskUpper = RegInfo.createVirtualRegister(RC);
1364	unsigned MaskedCmpVal = RegInfo.createVirtualRegister(RC);
1365	unsigned MaskedNewVal = RegInfo.createVirtualRegister(RC);
1366	unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC);
1367	unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1368	unsigned SrlRes = RegInfo.createVirtualRegister(RC);
1369	unsigned Success = RegInfo.createVirtualRegister(RC);
1370
1371	// insert new blocks after the current block
1372	const BasicBlock *LLVM_BB = BB->getBasicBlock();
1373	MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1374	MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1375	MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1376	MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1377	MachineFunction::iterator It = BB;
1378	++It;
1379	MF->insert(It, loop1MBB);
1380	MF->insert(It, loop2MBB);
1381	MF->insert(It, sinkMBB);
1382	MF->insert(It, exitMBB);
1383
1384	// Transfer the remainder of BB and its successor edges to exitMBB.
1385	exitMBB->splice(exitMBB->begin(), BB,
1386	std::next(MachineBasicBlock::iterator(MI)), BB->end());
1387	exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1388
1389	BB->addSuccessor(loop1MBB);
1390	loop1MBB->addSuccessor(sinkMBB);
1391	loop1MBB->addSuccessor(loop2MBB);
1392	loop2MBB->addSuccessor(loop1MBB);
1393	loop2MBB->addSuccessor(sinkMBB);
1394	sinkMBB->addSuccessor(exitMBB);
1395
1396	// FIXME: computation of newval2 can be moved to loop2MBB.
1397	// thisMBB:
1398	// addiu masklsb2,$0,-4 # 0xfffffffc
1399	// and alignedaddr,ptr,masklsb2
1400	// andi ptrlsb2,ptr,3
1401	// sll shiftamt,ptrlsb2,3
1402	// ori maskupper,$0,255 # 0xff
1403	// sll mask,maskupper,shiftamt
1404	// nor mask2,$0,mask
1405	// andi maskedcmpval,cmpval,255
1406	// sll shiftedcmpval,maskedcmpval,shiftamt
1407	// andi maskednewval,newval,255
1408	// sll shiftednewval,maskednewval,shiftamt
1409	int64_t MaskImm = (Size == 1) ? 255 : 65535;
1410	BuildMI(BB, DL, TII->get(Mips::ADDiu), MaskLSB2)
1411	.addReg(Mips::ZERO).addImm(-4);
1412	BuildMI(BB, DL, TII->get(Mips::AND), AlignedAddr)
1413	.addReg(Ptr).addReg(MaskLSB2);
1414	BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3);
1415	if (Subtarget.isLittle()) {
1416	BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1417	} else {
1418	unsigned Off = RegInfo.createVirtualRegister(RC);
1419	BuildMI(BB, DL, TII->get(Mips::XORi), Off)
1420	.addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2);
1421	BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
1422	}
1423	BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper)
1424	.addReg(Mips::ZERO).addImm(MaskImm);
1425	BuildMI(BB, DL, TII->get(Mips::SLLV), Mask)
1426	.addReg(MaskUpper).addReg(ShiftAmt);
1427	BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
1428	BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedCmpVal)
1429	.addReg(CmpVal).addImm(MaskImm);
1430	BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedCmpVal)
1431	.addReg(MaskedCmpVal).addReg(ShiftAmt);
1432	BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedNewVal)
1433	.addReg(NewVal).addImm(MaskImm);
1434	BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedNewVal)
1435	.addReg(MaskedNewVal).addReg(ShiftAmt);
1436
1437	// loop1MBB:
1438	// ll oldval,0(alginedaddr)
1439	// and maskedoldval0,oldval,mask
1440	// bne maskedoldval0,shiftedcmpval,sinkMBB
1441	BB = loop1MBB;
1442	unsigned LL = isMicroMips ? Mips::LL_MM : Mips::LL;
1443	BuildMI(BB, DL, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0);
1444	BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal0)
1445	.addReg(OldVal).addReg(Mask);
1446	BuildMI(BB, DL, TII->get(Mips::BNE))
1447	.addReg(MaskedOldVal0).addReg(ShiftedCmpVal).addMBB(sinkMBB);
1448
1449	// loop2MBB:
1450	// and maskedoldval1,oldval,mask2
1451	// or storeval,maskedoldval1,shiftednewval
1452	// sc success,storeval,0(alignedaddr)
1453	// beq success,$0,loop1MBB
1454	BB = loop2MBB;
1455	BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal1)
1456	.addReg(OldVal).addReg(Mask2);
1457	BuildMI(BB, DL, TII->get(Mips::OR), StoreVal)
1458	.addReg(MaskedOldVal1).addReg(ShiftedNewVal);
1459	unsigned SC = isMicroMips ? Mips::SC_MM : Mips::SC;
1460	BuildMI(BB, DL, TII->get(SC), Success)
1461	.addReg(StoreVal).addReg(AlignedAddr).addImm(0);
1462	BuildMI(BB, DL, TII->get(Mips::BEQ))
1463	.addReg(Success).addReg(Mips::ZERO).addMBB(loop1MBB);
1464
1465	// sinkMBB:
1466	// srl srlres,maskedoldval0,shiftamt
1467	// sign_extend dest,srlres
1468	BB = sinkMBB;
1469
1470	BuildMI(BB, DL, TII->get(Mips::SRLV), SrlRes)
1471	.addReg(MaskedOldVal0).addReg(ShiftAmt);
1472	BB = emitSignExtendToI32InReg(MI, BB, Size, Dest, SrlRes);
	Value stored to 'BB' is never read
1473
1474	MI->eraseFromParent(); // The instruction is gone now.
1475
1476	return exitMBB;
1477	}
1478
1479	MachineBasicBlock MipsTargetLowering::emitSEL_D(MachineInstr MI,
1480	MachineBasicBlock *BB) const {
1481	MachineFunction *MF = BB->getParent();
1482	const TargetRegisterInfo *TRI =
1483	getTargetMachine().getSubtargetImpl()->getRegisterInfo();
1484	const TargetInstrInfo *TII =
1485	getTargetMachine().getSubtargetImpl()->getInstrInfo();
1486	MachineRegisterInfo &RegInfo = MF->getRegInfo();
1487	DebugLoc DL = MI->getDebugLoc();
1488	MachineBasicBlock::iterator II(MI);
1489
1490	unsigned Fc = MI->getOperand(1).getReg();
1491	const auto &FGR64RegClass = TRI->getRegClass(Mips::FGR64RegClassID);
1492
1493	unsigned Fc2 = RegInfo.createVirtualRegister(FGR64RegClass);
1494
1495	BuildMI(*BB, II, DL, TII->get(Mips::SUBREG_TO_REG), Fc2)
1496	.addImm(0)
1497	.addReg(Fc)
1498	.addImm(Mips::sub_lo);
1499
1500	// We don't erase the original instruction, we just replace the condition
1501	// register with the 64-bit super-register.
1502	MI->getOperand(1).setReg(Fc2);
1503
1504	return BB;
1505	}
1506
1507	//===----------------------------------------------------------------------===//
1508	// Misc Lower Operation implementation
1509	//===----------------------------------------------------------------------===//
1510	SDValue MipsTargetLowering::lowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
1511	SDValue Chain = Op.getOperand(0);
1512	SDValue Table = Op.getOperand(1);
1513	SDValue Index = Op.getOperand(2);
1514	SDLoc DL(Op);
1515	EVT PTy = getPointerTy();
1516	unsigned EntrySize =
1517	DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(*getDataLayout());
1518
1519	Index = DAG.getNode(ISD::MUL, DL, PTy, Index,
1520	DAG.getConstant(EntrySize, PTy));
1521	SDValue Addr = DAG.getNode(ISD::ADD, DL, PTy, Index, Table);
1522
1523	EVT MemVT = EVT::getIntegerVT(DAG.getContext(), EntrySize 8);
1524	Addr = DAG.getExtLoad(ISD::SEXTLOAD, DL, PTy, Chain, Addr,
1525	MachinePointerInfo::getJumpTable(), MemVT, false, false,
1526	false, 0);
1527	Chain = Addr.getValue(1);
1528
1529	if ((getTargetMachine().getRelocationModel() == Reloc::PIC_) \|\|
1530	Subtarget.isABI_N64()) {
1531	// For PIC, the sequence is:
1532	// BRIND(load(Jumptable + index) + RelocBase)
1533	// RelocBase can be JumpTable, GOT or some sort of global base.
1534	Addr = DAG.getNode(ISD::ADD, DL, PTy, Addr,
1535	getPICJumpTableRelocBase(Table, DAG));
1536	}
1537
1538	return DAG.getNode(ISD::BRIND, DL, MVT::Other, Chain, Addr);
1539	}
1540
1541	SDValue MipsTargetLowering::lowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
1542	// The first operand is the chain, the second is the condition, the third is
1543	// the block to branch to if the condition is true.
1544	SDValue Chain = Op.getOperand(0);
1545	SDValue Dest = Op.getOperand(2);
1546	SDLoc DL(Op);
1547
1548	assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6())((!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6( )) ? static_cast<void> (0) : __assert_fail ("!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6()" , "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn227492/lib/Target/Mips/MipsISelLowering.cpp" , 1548, __PRETTY_FUNCTION__));
1549	SDValue CondRes = createFPCmp(DAG, Op.getOperand(1));
1550
1551	// Return if flag is not set by a floating point comparison.
1552	if (CondRes.getOpcode() != MipsISD::FPCmp)
1553	return Op;
1554
1555	SDValue CCNode = CondRes.getOperand(2);
1556	Mips::CondCode CC =
1557	(Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue();
1558	unsigned Opc = invertFPCondCodeUser(CC) ? Mips::BRANCH_F : Mips::BRANCH_T;
1559	SDValue BrCode = DAG.getConstant(Opc, MVT::i32);
1560	SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32);
1561	return DAG.getNode(MipsISD::FPBrcond, DL, Op.getValueType(), Chain, BrCode,
1562	FCC0, Dest, CondRes);
1563	}
1564
1565	SDValue MipsTargetLowering::
1566	lowerSELECT(SDValue Op, SelectionDAG &DAG) const
1567	{
1568	assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6())((!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6( )) ? static_cast<void> (0) : __assert_fail ("!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6()" , "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn227492/lib/Target/Mips/MipsISelLowering.cpp" , 1568, __PRETTY_FUNCTION__));
1569	SDValue Cond = createFPCmp(DAG, Op.getOperand(0));
1570
1571	// Return if flag is not set by a floating point comparison.
1572	if (Cond.getOpcode() != MipsISD::FPCmp)
1573	return Op;
1574
1575	return createCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2),
1576	SDLoc(Op));
1577	}
1578
1579	SDValue MipsTargetLowering::
1580	lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const
1581	{
1582	SDLoc DL(Op);
1583	EVT Ty = Op.getOperand(0).getValueType();
1584	SDValue Cond = DAG.getNode(ISD::SETCC, DL,
1585	getSetCCResultType(*DAG.getContext(), Ty),
1586	Op.getOperand(0), Op.getOperand(1),
1587	Op.getOperand(4));
1588
1589	return DAG.getNode(ISD::SELECT, DL, Op.getValueType(), Cond, Op.getOperand(2),
1590	Op.getOperand(3));
1591	}
1592
1593	SDValue MipsTargetLowering::lowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1594	assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6())((!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6( )) ? static_cast<void> (0) : __assert_fail ("!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6()" , "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn227492/lib/Target/Mips/MipsISelLowering.cpp" , 1594, __PRETTY_FUNCTION__));
1595	SDValue Cond = createFPCmp(DAG, Op);
1596
1597	assert(Cond.getOpcode() == MipsISD::FPCmp &&((Cond.getOpcode() == MipsISD::FPCmp && "Floating point operand expected." ) ? static_cast<void> (0) : __assert_fail ("Cond.getOpcode() == MipsISD::FPCmp && \"Floating point operand expected.\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn227492/lib/Target/Mips/MipsISelLowering.cpp" , 1598, __PRETTY_FUNCTION__))
1598	"Floating point operand expected.")((Cond.getOpcode() == MipsISD::FPCmp && "Floating point operand expected." ) ? static_cast<void> (0) : __assert_fail ("Cond.getOpcode() == MipsISD::FPCmp && \"Floating point operand expected.\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn227492/lib/Target/Mips/MipsISelLowering.cpp" , 1598, __PRETTY_FUNCTION__));
1599
1600	SDValue True = DAG.getConstant(1, MVT::i32);
1601	SDValue False = DAG.getConstant(0, MVT::i32);
1602
1603	return createCMovFP(DAG, Cond, True, False, SDLoc(Op));
1604	}
1605
1606	SDValue MipsTargetLowering::lowerGlobalAddress(SDValue Op,
1607	SelectionDAG &DAG) const {
1608	EVT Ty = Op.getValueType();
1609	GlobalAddressSDNode *N = cast<GlobalAddressSDNode>(Op);
1610	const GlobalValue *GV = N->getGlobal();
1611
1612	if (getTargetMachine().getRelocationModel() != Reloc::PIC_ &&
1613	!Subtarget.isABI_N64()) {
1614	const MipsTargetObjectFile &TLOF =
1615	(const MipsTargetObjectFile&)getObjFileLowering();
1616
1617	if (TLOF.IsGlobalInSmallSection(GV, getTargetMachine()))
1618	// %gp_rel relocation
1619	return getAddrGPRel(N, SDLoc(N), Ty, DAG);
1620
1621	// %hi/%lo relocation
1622	return getAddrNonPIC(N, SDLoc(N), Ty, DAG);
1623	}
1624
1625	if (GV->hasInternalLinkage() \|\| (GV->hasLocalLinkage() && !isa<Function>(GV)))
1626	return getAddrLocal(N, SDLoc(N), Ty, DAG,
1627	Subtarget.isABI_N32() \|\| Subtarget.isABI_N64());
1628
1629	if (LargeGOT)
1630	return getAddrGlobalLargeGOT(N, SDLoc(N), Ty, DAG, MipsII::MO_GOT_HI16,
1631	MipsII::MO_GOT_LO16, DAG.getEntryNode(),
1632	MachinePointerInfo::getGOT());
1633
1634	return getAddrGlobal(N, SDLoc(N), Ty, DAG,
1635	(Subtarget.isABI_N32() \|\| Subtarget.isABI_N64())
1636	? MipsII::MO_GOT_DISP
1637	: MipsII::MO_GOT16,
1638	DAG.getEntryNode(), MachinePointerInfo::getGOT());
1639	}
1640
1641	SDValue MipsTargetLowering::lowerBlockAddress(SDValue Op,
1642	SelectionDAG &DAG) const {
1643	BlockAddressSDNode *N = cast<BlockAddressSDNode>(Op);
1644	EVT Ty = Op.getValueType();
1645
1646	if (getTargetMachine().getRelocationModel() != Reloc::PIC_ &&
1647	!Subtarget.isABI_N64())
1648	return getAddrNonPIC(N, SDLoc(N), Ty, DAG);
1649
1650	return getAddrLocal(N, SDLoc(N), Ty, DAG,
1651	Subtarget.isABI_N32() \|\| Subtarget.isABI_N64());
1652	}
1653
1654	SDValue MipsTargetLowering::
1655	lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
1656	{
1657	// If the relocation model is PIC, use the General Dynamic TLS Model or
1658	// Local Dynamic TLS model, otherwise use the Initial Exec or
1659	// Local Exec TLS Model.
1660
1661	GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1662	SDLoc DL(GA);
1663	const GlobalValue *GV = GA->getGlobal();
1664	EVT PtrVT = getPointerTy();
1665
1666	TLSModel::Model model = getTargetMachine().getTLSModel(GV);
1667
1668	if (model == TLSModel::GeneralDynamic \|\| model == TLSModel::LocalDynamic) {
1669	// General Dynamic and Local Dynamic TLS Model.
1670	unsigned Flag = (model == TLSModel::LocalDynamic) ? MipsII::MO_TLSLDM
1671	: MipsII::MO_TLSGD;
1672
1673	SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, Flag);
1674	SDValue Argument = DAG.getNode(MipsISD::Wrapper, DL, PtrVT,
1675	getGlobalReg(DAG, PtrVT), TGA);
1676	unsigned PtrSize = PtrVT.getSizeInBits();
1677	IntegerType PtrTy = Type::getIntNTy(DAG.getContext(), PtrSize);
1678
1679	SDValue TlsGetAddr = DAG.getExternalSymbol("__tls_get_addr", PtrVT);
1680
1681	ArgListTy Args;
1682	ArgListEntry Entry;
1683	Entry.Node = Argument;
1684	Entry.Ty = PtrTy;
1685	Args.push_back(Entry);
1686
1687	TargetLowering::CallLoweringInfo CLI(DAG);
1688	CLI.setDebugLoc(DL).setChain(DAG.getEntryNode())
1689	.setCallee(CallingConv::C, PtrTy, TlsGetAddr, std::move(Args), 0);
1690	std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
1691
1692	SDValue Ret = CallResult.first;
1693
1694	if (model != TLSModel::LocalDynamic)
1695	return Ret;
1696
1697	SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
1698	MipsII::MO_DTPREL_HI);
1699	SDValue Hi = DAG.getNode(MipsISD::Hi, DL, PtrVT, TGAHi);
1700	SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
1701	MipsII::MO_DTPREL_LO);
1702	SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo);
1703	SDValue Add = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Ret);
1704	return DAG.getNode(ISD::ADD, DL, PtrVT, Add, Lo);
1705	}
1706
1707	SDValue Offset;
1708	if (model == TLSModel::InitialExec) {
1709	// Initial Exec TLS Model
1710	SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
1711	MipsII::MO_GOTTPREL);
1712	TGA = DAG.getNode(MipsISD::Wrapper, DL, PtrVT, getGlobalReg(DAG, PtrVT),
1713	TGA);
1714	Offset = DAG.getLoad(PtrVT, DL,
1715	DAG.getEntryNode(), TGA, MachinePointerInfo(),
1716	false, false, false, 0);
1717	} else {
1718	// Local Exec TLS Model
1719	assert(model == TLSModel::LocalExec)((model == TLSModel::LocalExec) ? static_cast<void> (0) : __assert_fail ("model == TLSModel::LocalExec", "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn227492/lib/Target/Mips/MipsISelLowering.cpp" , 1719, __PRETTY_FUNCTION__));
1720	SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
1721	MipsII::MO_TPREL_HI);
1722	SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
1723	MipsII::MO_TPREL_LO);
1724	SDValue Hi = DAG.getNode(MipsISD::Hi, DL, PtrVT, TGAHi);
1725	SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo);
1726	Offset = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1727	}
1728
1729	SDValue ThreadPointer = DAG.getNode(MipsISD::ThreadPointer, DL, PtrVT);
1730	return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadPointer, Offset);
1731	}
1732
1733	SDValue MipsTargetLowering::
1734	lowerJumpTable(SDValue Op, SelectionDAG &DAG) const
1735	{
1736	JumpTableSDNode *N = cast<JumpTableSDNode>(Op);
1737	EVT Ty = Op.getValueType();
1738
1739	if (getTargetMachine().getRelocationModel() != Reloc::PIC_ &&
1740	!Subtarget.isABI_N64())
1741	return getAddrNonPIC(N, SDLoc(N), Ty, DAG);
1742
1743	return getAddrLocal(N, SDLoc(N), Ty, DAG,
1744	Subtarget.isABI_N32() \|\| Subtarget.isABI_N64());
1745	}
1746
1747	SDValue MipsTargetLowering::
1748	lowerConstantPool(SDValue Op, SelectionDAG &DAG) const
1749	{
1750	ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
1751	EVT Ty = Op.getValueType();
1752
1753	if (getTargetMachine().getRelocationModel() != Reloc::PIC_ &&
1754	!Subtarget.isABI_N64()) {
1755	const MipsTargetObjectFile &TLOF =
1756	(const MipsTargetObjectFile&)getObjFileLowering();
1757
1758	if (TLOF.IsConstantInSmallSection(N->getConstVal(), getTargetMachine()))
1759	// %gp_rel relocation
1760	return getAddrGPRel(N, SDLoc(N), Ty, DAG);
1761
1762	return getAddrNonPIC(N, SDLoc(N), Ty, DAG);
1763	}
1764
1765	return getAddrLocal(N, SDLoc(N), Ty, DAG,
1766	Subtarget.isABI_N32() \|\| Subtarget.isABI_N64());
1767	}
1768
1769	SDValue MipsTargetLowering::lowerVASTART(SDValue Op, SelectionDAG &DAG) const {
1770	MachineFunction &MF = DAG.getMachineFunction();
1771	MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
1772
1773	SDLoc DL(Op);
1774	SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
1775	getPointerTy());
1776
1777	// vastart just stores the address of the VarArgsFrameIndex slot into the
1778	// memory location argument.
1779	const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1780	return DAG.getStore(Op.getOperand(0), DL, FI, Op.getOperand(1),
1781	MachinePointerInfo(SV), false, false, 0);
1782	}
1783
1784	SDValue MipsTargetLowering::lowerVAARG(SDValue Op, SelectionDAG &DAG) const {
1785	SDNode *Node = Op.getNode();
1786	EVT VT = Node->getValueType(0);
1787	SDValue Chain = Node->getOperand(0);
1788	SDValue VAListPtr = Node->getOperand(1);
1789	unsigned Align = Node->getConstantOperandVal(3);
1790	const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
1791	SDLoc DL(Node);
1792	unsigned ArgSlotSizeInBytes =
1793	(Subtarget.isABI_N32() \|\| Subtarget.isABI_N64()) ? 8 : 4;
1794
1795	SDValue VAListLoad = DAG.getLoad(getPointerTy(), DL, Chain, VAListPtr,
1796	MachinePointerInfo(SV), false, false, false,
1797	0);
1798	SDValue VAList = VAListLoad;
1799
1800	// Re-align the pointer if necessary.
1801	// It should only ever be necessary for 64-bit types on O32 since the minimum
1802	// argument alignment is the same as the maximum type alignment for N32/N64.
1803	//
1804	// FIXME: We currently align too often. The code generator doesn't notice
1805	// when the pointer is still aligned from the last va_arg (or pair of
1806	// va_args for the i64 on O32 case).
1807	if (Align > getMinStackArgumentAlignment()) {
1808	assert(((Align & (Align-1)) == 0) && "Expected Align to be a power of 2")((((Align & (Align-1)) == 0) && "Expected Align to be a power of 2" ) ? static_cast<void> (0) : __assert_fail ("((Align & (Align-1)) == 0) && \"Expected Align to be a power of 2\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn227492/lib/Target/Mips/MipsISelLowering.cpp" , 1808, __PRETTY_FUNCTION__));
1809
1810	VAList = DAG.getNode(ISD::ADD, DL, VAList.getValueType(), VAList,
1811	DAG.getConstant(Align - 1,
1812	VAList.getValueType()));
1813
1814	VAList = DAG.getNode(ISD::AND, DL, VAList.getValueType(), VAList,
1815	DAG.getConstant(-(int64_t)Align,
1816	VAList.getValueType()));
1817	}
1818
1819	// Increment the pointer, VAList, to the next vaarg.
1820	unsigned ArgSizeInBytes = getDataLayout()->getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext()));
1821	SDValue Tmp3 = DAG.getNode(ISD::ADD, DL, VAList.getValueType(), VAList,
1822	DAG.getConstant(RoundUpToAlignment(ArgSizeInBytes, ArgSlotSizeInBytes),
1823	VAList.getValueType()));
1824	// Store the incremented VAList to the legalized pointer
1825	Chain = DAG.getStore(VAListLoad.getValue(1), DL, Tmp3, VAListPtr,
1826	MachinePointerInfo(SV), false, false, 0);
1827
1828	// In big-endian mode we must adjust the pointer when the load size is smaller
1829	// than the argument slot size. We must also reduce the known alignment to
1830	// match. For example in the N64 ABI, we must add 4 bytes to the offset to get
1831	// the correct half of the slot, and reduce the alignment from 8 (slot
1832	// alignment) down to 4 (type alignment).
1833	if (!Subtarget.isLittle() && ArgSizeInBytes < ArgSlotSizeInBytes) {
1834	unsigned Adjustment = ArgSlotSizeInBytes - ArgSizeInBytes;
1835	VAList = DAG.getNode(ISD::ADD, DL, VAListPtr.getValueType(), VAList,
1836	DAG.getIntPtrConstant(Adjustment));
1837	}
1838	// Load the actual argument out of the pointer VAList
1839	return DAG.getLoad(VT, DL, Chain, VAList, MachinePointerInfo(), false, false,
1840	false, 0);
1841	}
1842
1843	static SDValue lowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG,
1844	bool HasExtractInsert) {
1845	EVT TyX = Op.getOperand(0).getValueType();
1846	EVT TyY = Op.getOperand(1).getValueType();
1847	SDValue Const1 = DAG.getConstant(1, MVT::i32);
1848	SDValue Const31 = DAG.getConstant(31, MVT::i32);
1849	SDLoc DL(Op);
1850	SDValue Res;
1851
1852	// If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it
1853	// to i32.
1854	SDValue X = (TyX == MVT::f32) ?
1855	DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) :
1856	DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0),
1857	Const1);
1858	SDValue Y = (TyY == MVT::f32) ?
1859	DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(1)) :
1860	DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(1),
1861	Const1);
1862
1863	if (HasExtractInsert) {
1864	// ext E, Y, 31, 1 ; extract bit31 of Y
1865	// ins X, E, 31, 1 ; insert extracted bit at bit31 of X
1866	SDValue E = DAG.getNode(MipsISD::Ext, DL, MVT::i32, Y, Const31, Const1);
1867	Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, E, Const31, Const1, X);
1868	} else {
1869	// sll SllX, X, 1
1870	// srl SrlX, SllX, 1
1871	// srl SrlY, Y, 31
1872	// sll SllY, SrlX, 31
1873	// or Or, SrlX, SllY
1874	SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1);
1875	SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1);
1876	SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31);
1877	SDValue SllY = DAG.getNode(ISD::SHL, DL, MVT::i32, SrlY, Const31);
1878	Res = DAG.getNode(ISD::OR, DL, MVT::i32, SrlX, SllY);
1879	}
1880
1881	if (TyX == MVT::f32)
1882	return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Res);
1883
1884	SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
1885	Op.getOperand(0), DAG.getConstant(0, MVT::i32));
1886	return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res);
1887	}
1888
1889	static SDValue lowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG,
1890	bool HasExtractInsert) {
1891	unsigned WidthX = Op.getOperand(0).getValueSizeInBits();
1892	unsigned WidthY = Op.getOperand(1).getValueSizeInBits();
1893	EVT TyX = MVT::getIntegerVT(WidthX), TyY = MVT::getIntegerVT(WidthY);
1894	SDValue Const1 = DAG.getConstant(1, MVT::i32);
1895	SDLoc DL(Op);
1896
1897	// Bitcast to integer nodes.
1898	SDValue X = DAG.getNode(ISD::BITCAST, DL, TyX, Op.getOperand(0));
1899	SDValue Y = DAG.getNode(ISD::BITCAST, DL, TyY, Op.getOperand(1));
1900
1901	if (HasExtractInsert) {
1902	// ext E, Y, width(Y) - 1, 1 ; extract bit width(Y)-1 of Y
1903	// ins X, E, width(X) - 1, 1 ; insert extracted bit at bit width(X)-1 of X
1904	SDValue E = DAG.getNode(MipsISD::Ext, DL, TyY, Y,
1905	DAG.getConstant(WidthY - 1, MVT::i32), Const1);
1906
1907	if (WidthX > WidthY)
1908	E = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, E);
1909	else if (WidthY > WidthX)
1910	E = DAG.getNode(ISD::TRUNCATE, DL, TyX, E);
1911
1912	SDValue I = DAG.getNode(MipsISD::Ins, DL, TyX, E,
1913	DAG.getConstant(WidthX - 1, MVT::i32), Const1, X);
1914	return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), I);
1915	}
1916
1917	// (d)sll SllX, X, 1
1918	// (d)srl SrlX, SllX, 1
1919	// (d)srl SrlY, Y, width(Y)-1
1920	// (d)sll SllY, SrlX, width(Y)-1
1921	// or Or, SrlX, SllY
1922	SDValue SllX = DAG.getNode(ISD::SHL, DL, TyX, X, Const1);
1923	SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1);
1924	SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y,
1925	DAG.getConstant(WidthY - 1, MVT::i32));
1926
1927	if (WidthX > WidthY)
1928	SrlY = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, SrlY);
1929	else if (WidthY > WidthX)
1930	SrlY = DAG.getNode(ISD::TRUNCATE, DL, TyX, SrlY);
1931
1932	SDValue SllY = DAG.getNode(ISD::SHL, DL, TyX, SrlY,
1933	DAG.getConstant(WidthX - 1, MVT::i32));
1934	SDValue Or = DAG.getNode(ISD::OR, DL, TyX, SrlX, SllY);
1935	return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Or);
1936	}
1937
1938	SDValue
1939	MipsTargetLowering::lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
1940	if (Subtarget.isGP64bit())
1941	return lowerFCOPYSIGN64(Op, DAG, Subtarget.hasExtractInsert());
1942
1943	return lowerFCOPYSIGN32(Op, DAG, Subtarget.hasExtractInsert());
1944	}
1945
1946	SDValue MipsTargetLowering::
1947	lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
1948	// check the depth
1949	assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) &&(((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue () == 0) && "Frame address can only be determined for current frame." ) ? static_cast<void> (0) : __assert_fail ("(cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) && \"Frame address can only be determined for current frame.\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn227492/lib/Target/Mips/MipsISelLowering.cpp" , 1950, __PRETTY_FUNCTION__))
1950	"Frame address can only be determined for current frame.")(((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue () == 0) && "Frame address can only be determined for current frame." ) ? static_cast<void> (0) : __assert_fail ("(cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) && \"Frame address can only be determined for current frame.\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn227492/lib/Target/Mips/MipsISelLowering.cpp" , 1950, __PRETTY_FUNCTION__));
1951
1952	MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
1953	MFI->setFrameAddressIsTaken(true);
1954	EVT VT = Op.getValueType();
1955	SDLoc DL(Op);
1956	SDValue FrameAddr =
1957	DAG.getCopyFromReg(DAG.getEntryNode(), DL,
1958	Subtarget.isABI_N64() ? Mips::FP_64 : Mips::FP, VT);
1959	return FrameAddr;
1960	}
1961
1962	SDValue MipsTargetLowering::lowerRETURNADDR(SDValue Op,
1963	SelectionDAG &DAG) const {
1964	if (verifyReturnAddressArgumentIsConstant(Op, DAG))
1965	return SDValue();
1966
1967	// check the depth
1968	assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) &&(((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue () == 0) && "Return address can be determined only for current frame." ) ? static_cast<void> (0) : __assert_fail ("(cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) && \"Return address can be determined only for current frame.\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn227492/lib/Target/Mips/MipsISelLowering.cpp" , 1969, __PRETTY_FUNCTION__))
1969	"Return address can be determined only for current frame.")(((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue () == 0) && "Return address can be determined only for current frame." ) ? static_cast<void> (0) : __assert_fail ("(cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) && \"Return address can be determined only for current frame.\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn227492/lib/Target/Mips/MipsISelLowering.cpp" , 1969, __PRETTY_FUNCTION__));
1970
1971	MachineFunction &MF = DAG.getMachineFunction();
1972	MachineFrameInfo *MFI = MF.getFrameInfo();
1973	MVT VT = Op.getSimpleValueType();
1974	unsigned RA = Subtarget.isABI_N64() ? Mips::RA_64 : Mips::RA;
1975	MFI->setReturnAddressIsTaken(true);
1976
1977	// Return RA, which contains the return address. Mark it an implicit live-in.
1978	unsigned Reg = MF.addLiveIn(RA, getRegClassFor(VT));
1979	return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(Op), Reg, VT);
1980	}
1981
1982	// An EH_RETURN is the result of lowering llvm.eh.return which in turn is
1983	// generated from __builtin_eh_return (offset, handler)
1984	// The effect of this is to adjust the stack pointer by "offset"
1985	// and then branch to "handler".
1986	SDValue MipsTargetLowering::lowerEH_RETURN(SDValue Op, SelectionDAG &DAG)
1987	const {
1988	MachineFunction &MF = DAG.getMachineFunction();
1989	MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
1990
1991	MipsFI->setCallsEhReturn();
1992	SDValue Chain = Op.getOperand(0);
1993	SDValue Offset = Op.getOperand(1);
1994	SDValue Handler = Op.getOperand(2);
1995	SDLoc DL(Op);
1996	EVT Ty = Subtarget.isABI_N64() ? MVT::i64 : MVT::i32;
1997
1998	// Store stack offset in V1, store jump target in V0. Glue CopyToReg and
1999	// EH_RETURN nodes, so that instructions are emitted back-to-back.
2000	unsigned OffsetReg = Subtarget.isABI_N64() ? Mips::V1_64 : Mips::V1;
2001	unsigned AddrReg = Subtarget.isABI_N64() ? Mips::V0_64 : Mips::V0;
2002	Chain = DAG.getCopyToReg(Chain, DL, OffsetReg, Offset, SDValue());
2003	Chain = DAG.getCopyToReg(Chain, DL, AddrReg, Handler, Chain.getValue(1));
2004	return DAG.getNode(MipsISD::EH_RETURN, DL, MVT::Other, Chain,
2005	DAG.getRegister(OffsetReg, Ty),
2006	DAG.getRegister(AddrReg, getPointerTy()),
2007	Chain.getValue(1));
2008	}
2009
2010	SDValue MipsTargetLowering::lowerATOMIC_FENCE(SDValue Op,
2011	SelectionDAG &DAG) const {
2012	// FIXME: Need pseudo-fence for 'singlethread' fences
2013	// FIXME: Set SType for weaker fences where supported/appropriate.
2014	unsigned SType = 0;
2015	SDLoc DL(Op);
2016	return DAG.getNode(MipsISD::Sync, DL, MVT::Other, Op.getOperand(0),
2017	DAG.getConstant(SType, MVT::i32));
2018	}
2019
2020	SDValue MipsTargetLowering::lowerShiftLeftParts(SDValue Op,
2021	SelectionDAG &DAG) const {
2022	SDLoc DL(Op);
2023	MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32;
2024
2025	SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);
2026	SDValue Shamt = Op.getOperand(2);
2027	// if shamt < (VT.bits):
2028	// lo = (shl lo, shamt)
2029	// hi = (or (shl hi, shamt) (srl (srl lo, 1), ~shamt))
2030	// else:
2031	// lo = 0
2032	// hi = (shl lo, shamt[4:0])
2033	SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
2034	DAG.getConstant(-1, MVT::i32));
2035	SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, VT, Lo,
2036	DAG.getConstant(1, VT));
2037	SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, ShiftRight1Lo, Not);
2038	SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, Hi, Shamt);
2039	SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo);
2040	SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt);
2041	SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
2042	DAG.getConstant(0x20, MVT::i32));
2043	Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond,
2044	DAG.getConstant(0, VT), ShiftLeftLo);
2045	Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftLeftLo, Or);
2046
2047	SDValue Ops[2] = {Lo, Hi};
2048	return DAG.getMergeValues(Ops, DL);
2049	}
2050
2051	SDValue MipsTargetLowering::lowerShiftRightParts(SDValue Op, SelectionDAG &DAG,
2052	bool IsSRA) const {
2053	SDLoc DL(Op);
2054	SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);
2055	SDValue Shamt = Op.getOperand(2);
2056	MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32;
2057
2058	// if shamt < (VT.bits):
2059	// lo = (or (shl (shl hi, 1), ~shamt) (srl lo, shamt))
2060	// if isSRA:
2061	// hi = (sra hi, shamt)
2062	// else:
2063	// hi = (srl hi, shamt)
2064	// else:
2065	// if isSRA:
2066	// lo = (sra hi, shamt[4:0])
2067	// hi = (sra hi, 31)
2068	// else:
2069	// lo = (srl hi, shamt[4:0])
2070	// hi = 0
2071	SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
2072	DAG.getConstant(-1, MVT::i32));
2073	SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, VT, Hi,
2074	DAG.getConstant(1, VT));
2075	SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, ShiftLeft1Hi, Not);
2076	SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, Lo, Shamt);
2077	SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo);
2078	SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL,
2079	DL, VT, Hi, Shamt);
2080	SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
2081	DAG.getConstant(0x20, MVT::i32));
2082	SDValue Shift31 = DAG.getNode(ISD::SRA, DL, VT, Hi, DAG.getConstant(31, VT));
2083	Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftRightHi, Or);
2084	Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond,
2085	IsSRA ? Shift31 : DAG.getConstant(0, VT), ShiftRightHi);
2086
2087	SDValue Ops[2] = {Lo, Hi};
2088	return DAG.getMergeValues(Ops, DL);
2089	}
2090
2091	static SDValue createLoadLR(unsigned Opc, SelectionDAG &DAG, LoadSDNode *LD,
2092	SDValue Chain, SDValue Src, unsigned Offset) {
2093	SDValue Ptr = LD->getBasePtr();
2094	EVT VT = LD->getValueType(0), MemVT = LD->getMemoryVT();
2095	EVT BasePtrVT = Ptr.getValueType();
2096	SDLoc DL(LD);
2097	SDVTList VTList = DAG.getVTList(VT, MVT::Other);
2098
2099	if (Offset)
2100	Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr,
2101	DAG.getConstant(Offset, BasePtrVT));
2102
2103	SDValue Ops[] = { Chain, Ptr, Src };
2104	return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT,
2105	LD->getMemOperand());
2106	}
2107
2108	// Expand an unaligned 32 or 64-bit integer load node.
2109	SDValue MipsTargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const {
2110	LoadSDNode *LD = cast<LoadSDNode>(Op);
2111	EVT MemVT = LD->getMemoryVT();
2112
2113	if (Subtarget.systemSupportsUnalignedAccess())
2114	return Op;
2115
2116	// Return if load is aligned or if MemVT is neither i32 nor i64.
2117	if ((LD->getAlignment() >= MemVT.getSizeInBits() / 8) \|\|
2118	((MemVT != MVT::i32) && (MemVT != MVT::i64)))
2119	return SDValue();
2120
2121	bool IsLittle = Subtarget.isLittle();
2122	EVT VT = Op.getValueType();
2123	ISD::LoadExtType ExtType = LD->getExtensionType();
2124	SDValue Chain = LD->getChain(), Undef = DAG.getUNDEF(VT);
2125
2126	assert((VT == MVT::i32) \|\| (VT == MVT::i64))(((VT == MVT::i32) \|\| (VT == MVT::i64)) ? static_cast<void > (0) : __assert_fail ("(VT == MVT::i32) \|\| (VT == MVT::i64)" , "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn227492/lib/Target/Mips/MipsISelLowering.cpp" , 2126, __PRETTY_FUNCTION__));
2127
2128	// Expand
2129	// (set dst, (i64 (load baseptr)))
2130	// to
2131	// (set tmp, (ldl (add baseptr, 7), undef))
2132	// (set dst, (ldr baseptr, tmp))
2133	if ((VT == MVT::i64) && (ExtType == ISD::NON_EXTLOAD)) {
2134	SDValue LDL = createLoadLR(MipsISD::LDL, DAG, LD, Chain, Undef,
2135	IsLittle ? 7 : 0);
2136	return createLoadLR(MipsISD::LDR, DAG, LD, LDL.getValue(1), LDL,
2137	IsLittle ? 0 : 7);
2138	}
2139
2140	SDValue LWL = createLoadLR(MipsISD::LWL, DAG, LD, Chain, Undef,
2141	IsLittle ? 3 : 0);
2142	SDValue LWR = createLoadLR(MipsISD::LWR, DAG, LD, LWL.getValue(1), LWL,
2143	IsLittle ? 0 : 3);
2144
2145	// Expand
2146	// (set dst, (i32 (load baseptr))) or
2147	// (set dst, (i64 (sextload baseptr))) or
2148	// (set dst, (i64 (extload baseptr)))
2149	// to
2150	// (set tmp, (lwl (add baseptr, 3), undef))
2151	// (set dst, (lwr baseptr, tmp))
2152	if ((VT == MVT::i32) \|\| (ExtType == ISD::SEXTLOAD) \|\|
2153	(ExtType == ISD::EXTLOAD))
2154	return LWR;
2155
2156	assert((VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD))(((VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD)) ? static_cast <void> (0) : __assert_fail ("(VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD)" , "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn227492/lib/Target/Mips/MipsISelLowering.cpp" , 2156, __PRETTY_FUNCTION__));
2157
2158	// Expand
2159	// (set dst, (i64 (zextload baseptr)))
2160	// to
2161	// (set tmp0, (lwl (add baseptr, 3), undef))
2162	// (set tmp1, (lwr baseptr, tmp0))
2163	// (set tmp2, (shl tmp1, 32))
2164	// (set dst, (srl tmp2, 32))
2165	SDLoc DL(LD);
2166	SDValue Const32 = DAG.getConstant(32, MVT::i32);
2167	SDValue SLL = DAG.getNode(ISD::SHL, DL, MVT::i64, LWR, Const32);
2168	SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32);
2169	SDValue Ops[] = { SRL, LWR.getValue(1) };
2170	return DAG.getMergeValues(Ops, DL);
2171	}
2172
2173	static SDValue createStoreLR(unsigned Opc, SelectionDAG &DAG, StoreSDNode *SD,
2174	SDValue Chain, unsigned Offset) {
2175	SDValue Ptr = SD->getBasePtr(), Value = SD->getValue();
2176	EVT MemVT = SD->getMemoryVT(), BasePtrVT = Ptr.getValueType();
2177	SDLoc DL(SD);
2178	SDVTList VTList = DAG.getVTList(MVT::Other);
2179
2180	if (Offset)
2181	Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr,
2182	DAG.getConstant(Offset, BasePtrVT));
2183
2184	SDValue Ops[] = { Chain, Value, Ptr };
2185	return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT,
2186	SD->getMemOperand());
2187	}
2188
2189	// Expand an unaligned 32 or 64-bit integer store node.
2190	static SDValue lowerUnalignedIntStore(StoreSDNode *SD, SelectionDAG &DAG,
2191	bool IsLittle) {
2192	SDValue Value = SD->getValue(), Chain = SD->getChain();
2193	EVT VT = Value.getValueType();
2194
2195	// Expand
2196	// (store val, baseptr) or
2197	// (truncstore val, baseptr)
2198	// to
2199	// (swl val, (add baseptr, 3))
2200	// (swr val, baseptr)
2201	if ((VT == MVT::i32) \|\| SD->isTruncatingStore()) {
2202	SDValue SWL = createStoreLR(MipsISD::SWL, DAG, SD, Chain,
2203	IsLittle ? 3 : 0);
2204	return createStoreLR(MipsISD::SWR, DAG, SD, SWL, IsLittle ? 0 : 3);
2205	}
2206
2207	assert(VT == MVT::i64)((VT == MVT::i64) ? static_cast<void> (0) : __assert_fail ("VT == MVT::i64", "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn227492/lib/Target/Mips/MipsISelLowering.cpp" , 2207, __PRETTY_FUNCTION__));
2208
2209	// Expand
2210	// (store val, baseptr)
2211	// to
2212	// (sdl val, (add baseptr, 7))
2213	// (sdr val, baseptr)
2214	SDValue SDL = createStoreLR(MipsISD::SDL, DAG, SD, Chain, IsLittle ? 7 : 0);
2215	return createStoreLR(MipsISD::SDR, DAG, SD, SDL, IsLittle ? 0 : 7);
2216	}
2217
2218	// Lower (store (fp_to_sint $fp) $ptr) to (store (TruncIntFP $fp), $ptr).
2219	static SDValue lowerFP_TO_SINT_STORE(StoreSDNode *SD, SelectionDAG &DAG) {
2220	SDValue Val = SD->getValue();
2221
2222	if (Val.getOpcode() != ISD::FP_TO_SINT)
2223	return SDValue();
2224
2225	EVT FPTy = EVT::getFloatingPointVT(Val.getValueSizeInBits());
2226	SDValue Tr = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Val), FPTy,
2227	Val.getOperand(0));
2228
2229	return DAG.getStore(SD->getChain(), SDLoc(SD), Tr, SD->getBasePtr(),
2230	SD->getPointerInfo(), SD->isVolatile(),
2231	SD->isNonTemporal(), SD->getAlignment());
2232	}
2233
2234	SDValue MipsTargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const {
2235	StoreSDNode *SD = cast<StoreSDNode>(Op);
2236	EVT MemVT = SD->getMemoryVT();
2237
2238	// Lower unaligned integer stores.
2239	if (!Subtarget.systemSupportsUnalignedAccess() &&
2240	(SD->getAlignment() < MemVT.getSizeInBits() / 8) &&
2241	((MemVT == MVT::i32) \|\| (MemVT == MVT::i64)))
2242	return lowerUnalignedIntStore(SD, DAG, Subtarget.isLittle());
2243
2244	return lowerFP_TO_SINT_STORE(SD, DAG);
2245	}
2246
2247	SDValue MipsTargetLowering::lowerADD(SDValue Op, SelectionDAG &DAG) const {
2248	if (Op->getOperand(0).getOpcode() != ISD::FRAMEADDR
2249	\|\| cast<ConstantSDNode>
2250	(Op->getOperand(0).getOperand(0))->getZExtValue() != 0
2251	\|\| Op->getOperand(1).getOpcode() != ISD::FRAME_TO_ARGS_OFFSET)
2252	return SDValue();
2253
2254	// The pattern
2255	// (add (frameaddr 0), (frame_to_args_offset))
2256	// results from lowering llvm.eh.dwarf.cfa intrinsic. Transform it to
2257	// (add FrameObject, 0)
2258	// where FrameObject is a fixed StackObject with offset 0 which points to
2259	// the old stack pointer.
2260	MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2261	EVT ValTy = Op->getValueType(0);
2262	int FI = MFI->CreateFixedObject(Op.getValueSizeInBits() / 8, 0, false);
2263	SDValue InArgsAddr = DAG.getFrameIndex(FI, ValTy);
2264	return DAG.getNode(ISD::ADD, SDLoc(Op), ValTy, InArgsAddr,
2265	DAG.getConstant(0, ValTy));
2266	}
2267
2268	SDValue MipsTargetLowering::lowerFP_TO_SINT(SDValue Op,
2269	SelectionDAG &DAG) const {
2270	EVT FPTy = EVT::getFloatingPointVT(Op.getValueSizeInBits());
2271	SDValue Trunc = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Op), FPTy,
2272	Op.getOperand(0));
2273	return DAG.getNode(ISD::BITCAST, SDLoc(Op), Op.getValueType(), Trunc);
2274	}
2275
2276	//===----------------------------------------------------------------------===//
2277	// Calling Convention Implementation
2278	//===----------------------------------------------------------------------===//
2279
2280	//===----------------------------------------------------------------------===//
2281	// TODO: Implement a generic logic using tblgen that can support this.
2282	// Mips O32 ABI rules:
2283	// ---
2284	// i32 - Passed in A0, A1, A2, A3 and stack
2285	// f32 - Only passed in f32 registers if no int reg has been used yet to hold
2286	// an argument. Otherwise, passed in A1, A2, A3 and stack.
2287	// f64 - Only passed in two aliased f32 registers if no int reg has been used
2288	// yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is
2289	// not used, it must be shadowed. If only A3 is available, shadow it and
2290	// go to stack.
2291	//
2292	// For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack.
2293	//===----------------------------------------------------------------------===//
2294
2295	static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT,
2296	CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
2297	CCState &State, const MCPhysReg *F64Regs) {
2298	const MipsSubtarget &Subtarget =
2299	State.getMachineFunction().getTarget()
2300	.getSubtarget<const MipsSubtarget>();
2301
2302	static const unsigned IntRegsSize = 4, FloatRegsSize = 2;
2303
2304	static const MCPhysReg IntRegs[] = { Mips::A0, Mips::A1, Mips::A2, Mips::A3 };
2305	static const MCPhysReg F32Regs[] = { Mips::F12, Mips::F14 };
2306
2307	// Do not process byval args here.
2308	if (ArgFlags.isByVal())
2309	return true;
2310
2311	// Promote i8 and i16
2312	if (ArgFlags.isInReg() && !Subtarget.isLittle()) {
2313	if (LocVT == MVT::i8 \|\| LocVT == MVT::i16 \|\| LocVT == MVT::i32) {
2314	LocVT = MVT::i32;
2315	if (ArgFlags.isSExt())
2316	LocInfo = CCValAssign::SExtUpper;
2317	else if (ArgFlags.isZExt())
2318	LocInfo = CCValAssign::ZExtUpper;
2319	else
2320	LocInfo = CCValAssign::AExtUpper;
2321	}
2322	}
2323
2324	// Promote i8 and i16
2325	if (LocVT == MVT::i8 \|\| LocVT == MVT::i16) {
2326	LocVT = MVT::i32;
2327	if (ArgFlags.isSExt())
2328	LocInfo = CCValAssign::SExt;
2329	else if (ArgFlags.isZExt())
2330	LocInfo = CCValAssign::ZExt;
2331	else
2332	LocInfo = CCValAssign::AExt;
2333	}
2334
2335	unsigned Reg;
2336
2337	// f32 and f64 are allocated in A0, A1, A2, A3 when either of the following
2338	// is true: function is vararg, argument is 3rd or higher, there is previous
2339	// argument which is not f32 or f64.
2340	bool AllocateFloatsInIntReg = State.isVarArg() \|\| ValNo > 1
2341	\|\| State.getFirstUnallocated(F32Regs, FloatRegsSize) != ValNo;
2342	unsigned OrigAlign = ArgFlags.getOrigAlign();
2343	bool isI64 = (ValVT == MVT::i32 && OrigAlign == 8);
2344
2345	if (ValVT == MVT::i32 \|\| (ValVT == MVT::f32 && AllocateFloatsInIntReg)) {
2346	Reg = State.AllocateReg(IntRegs, IntRegsSize);
2347	// If this is the first part of an i64 arg,
2348	// the allocated register must be either A0 or A2.
2349	if (isI64 && (Reg == Mips::A1 \|\| Reg == Mips::A3))
2350	Reg = State.AllocateReg(IntRegs, IntRegsSize);
2351	LocVT = MVT::i32;
2352	} else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) {
2353	// Allocate int register and shadow next int register. If first
2354	// available register is Mips::A1 or Mips::A3, shadow it too.
2355	Reg = State.AllocateReg(IntRegs, IntRegsSize);
2356	if (Reg == Mips::A1 \|\| Reg == Mips::A3)
2357	Reg = State.AllocateReg(IntRegs, IntRegsSize);
2358	State.AllocateReg(IntRegs, IntRegsSize);
2359	LocVT = MVT::i32;
2360	} else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) {
2361	// we are guaranteed to find an available float register
2362	if (ValVT == MVT::f32) {
2363	Reg = State.AllocateReg(F32Regs, FloatRegsSize);
2364	// Shadow int register
2365	State.AllocateReg(IntRegs, IntRegsSize);
2366	} else {
2367	Reg = State.AllocateReg(F64Regs, FloatRegsSize);
2368	// Shadow int registers
2369	unsigned Reg2 = State.AllocateReg(IntRegs, IntRegsSize);
2370	if (Reg2 == Mips::A1 \|\| Reg2 == Mips::A3)
2371	State.AllocateReg(IntRegs, IntRegsSize);
2372	State.AllocateReg(IntRegs, IntRegsSize);
2373	}
2374	} else
2375	llvm_unreachable("Cannot handle this ValVT.")::llvm::llvm_unreachable_internal("Cannot handle this ValVT." , "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn227492/lib/Target/Mips/MipsISelLowering.cpp" , 2375);
2376
2377	if (!Reg) {
2378	unsigned Offset = State.AllocateStack(ValVT.getSizeInBits() >> 3,
2379	OrigAlign);
2380	State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
2381	} else
2382	State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2383
2384	return false;
2385	}
2386
2387	static bool CC_MipsO32_FP32(unsigned ValNo, MVT ValVT,
2388	MVT LocVT, CCValAssign::LocInfo LocInfo,
2389	ISD::ArgFlagsTy ArgFlags, CCState &State) {
2390	static const MCPhysReg F64Regs[] = { Mips::D6, Mips::D7 };
2391
2392	return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs);
2393	}
2394
2395	static bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT,
2396	MVT LocVT, CCValAssign::LocInfo LocInfo,
2397	ISD::ArgFlagsTy ArgFlags, CCState &State) {
2398	static const MCPhysReg F64Regs[] = { Mips::D12_64, Mips::D14_64 };
2399
2400	return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs);
2401	}
2402
2403	static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT,
2404	CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
2405	CCState &State) LLVM_ATTRIBUTE_UNUSED__attribute__((__unused__));
2406
2407	#include "MipsGenCallingConv.inc"
2408
2409	//===----------------------------------------------------------------------===//
2410	// Call Calling Convention Implementation
2411	//===----------------------------------------------------------------------===//
2412
2413	// Return next O32 integer argument register.
2414	static unsigned getNextIntArgReg(unsigned Reg) {
2415	assert((Reg == Mips::A0) \|\| (Reg == Mips::A2))(((Reg == Mips::A0) \|\| (Reg == Mips::A2)) ? static_cast<void > (0) : __assert_fail ("(Reg == Mips::A0) \|\| (Reg == Mips::A2)" , "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn227492/lib/Target/Mips/MipsISelLowering.cpp" , 2415, __PRETTY_FUNCTION__));
2416	return (Reg == Mips::A0) ? Mips::A1 : Mips::A3;
2417	}
2418
2419	SDValue
2420	MipsTargetLowering::passArgOnStack(SDValue StackPtr, unsigned Offset,
2421	SDValue Chain, SDValue Arg, SDLoc DL,
2422	bool IsTailCall, SelectionDAG &DAG) const {
2423	if (!IsTailCall) {
2424	SDValue PtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr,
2425	DAG.getIntPtrConstant(Offset));
2426	return DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo(), false,
2427	false, 0);
2428	}
2429
2430	MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2431	int FI = MFI->CreateFixedObject(Arg.getValueSizeInBits() / 8, Offset, false);
2432	SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2433	return DAG.getStore(Chain, DL, Arg, FIN, MachinePointerInfo(),
2434	/isVolatile=/ true, false, 0);
2435	}
2436
2437	void MipsTargetLowering::
2438	getOpndList(SmallVectorImpl<SDValue> &Ops,
2439	std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
2440	bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
2441	bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee,
2442	SDValue Chain) const {
2443	// Insert node "GP copy globalreg" before call to function.
2444	//
2445	// R_MIPS_CALL* operators (emitted when non-internal functions are called
2446	// in PIC mode) allow symbols to be resolved via lazy binding.
2447	// The lazy binding stub requires GP to point to the GOT.
2448	// Note that we don't need GP to point to the GOT for indirect calls
2449	// (when R_MIPS_CALL* is not used for the call) because Mips linker generates
2450	// lazy binding stub for a function only when R_MIPS_CALL* are the only relocs
2451	// used for the function (that is, Mips linker doesn't generate lazy binding
2452	// stub for a function whose address is taken in the program).
2453	if (IsPICCall && !InternalLinkage && IsCallReloc) {
2454	unsigned GPReg = Subtarget.isABI_N64() ? Mips::GP_64 : Mips::GP;
2455	EVT Ty = Subtarget.isABI_N64() ? MVT::i64 : MVT::i32;
2456	RegsToPass.push_back(std::make_pair(GPReg, getGlobalReg(CLI.DAG, Ty)));
2457	}
2458
2459	// Build a sequence of copy-to-reg nodes chained together with token
2460	// chain and flag operands which copy the outgoing args into registers.
2461	// The InFlag in necessary since all emitted instructions must be
2462	// stuck together.
2463	SDValue InFlag;
2464
2465	for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2466	Chain = CLI.DAG.getCopyToReg(Chain, CLI.DL, RegsToPass[i].first,
2467	RegsToPass[i].second, InFlag);
2468	InFlag = Chain.getValue(1);
2469	}
2470
2471	// Add argument registers to the end of the list so that they are
2472	// known live into the call.
2473	for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2474	Ops.push_back(CLI.DAG.getRegister(RegsToPass[i].first,
2475	RegsToPass[i].second.getValueType()));
2476
2477	// Add a register mask operand representing the call-preserved registers.
2478	const TargetRegisterInfo *TRI =
2479	getTargetMachine().getSubtargetImpl()->getRegisterInfo();
2480	const uint32_t *Mask = TRI->getCallPreservedMask(CLI.CallConv);
2481	assert(Mask && "Missing call preserved mask for calling convention")((Mask && "Missing call preserved mask for calling convention" ) ? static_cast<void> (0) : __assert_fail ("Mask && \"Missing call preserved mask for calling convention\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn227492/lib/Target/Mips/MipsISelLowering.cpp" , 2481, __PRETTY_FUNCTION__));
2482	if (Subtarget.inMips16HardFloat()) {
2483	if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(CLI.Callee)) {
2484	llvm::StringRef Sym = G->getGlobal()->getName();
2485	Function *F = G->getGlobal()->getParent()->getFunction(Sym);
2486	if (F && F->hasFnAttribute("__Mips16RetHelper")) {
2487	Mask = MipsRegisterInfo::getMips16RetHelperMask();
2488	}
2489	}
2490	}
2491	Ops.push_back(CLI.DAG.getRegisterMask(Mask));
2492
2493	if (InFlag.getNode())
2494	Ops.push_back(InFlag);
2495	}
2496
2497	/// LowerCall - functions arguments are copied from virtual regs to
2498	/// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
2499	SDValue
2500	MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2501	SmallVectorImpl<SDValue> &InVals) const {
2502	SelectionDAG &DAG = CLI.DAG;
2503	SDLoc DL = CLI.DL;
2504	SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2505	SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2506	SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2507	SDValue Chain = CLI.Chain;
2508	SDValue Callee = CLI.Callee;
2509	bool &IsTailCall = CLI.IsTailCall;
2510	CallingConv::ID CallConv = CLI.CallConv;
2511	bool IsVarArg = CLI.IsVarArg;
2512
2513	MachineFunction &MF = DAG.getMachineFunction();
2514	MachineFrameInfo *MFI = MF.getFrameInfo();
2515	const TargetFrameLowering *TFL = MF.getSubtarget().getFrameLowering();
2516	MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
2517	bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
2518
2519	// Analyze operands of the call, assigning locations to each operand.
2520	SmallVector<CCValAssign, 16> ArgLocs;
2521	MipsCCState CCInfo(
2522	CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, *DAG.getContext(),
2523	MipsCCState::getSpecialCallingConvForCallee(Callee.getNode(), Subtarget));
2524
2525	// Allocate the reserved argument area. It seems strange to do this from the
2526	// caller side but removing it breaks the frame size calculation.
2527	const MipsABIInfo &ABI =
2528	static_cast<const MipsTargetMachine &>(MF.getTarget()).getABI();
2529	CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(CallConv), 1);
2530
2531	CCInfo.AnalyzeCallOperands(Outs, CC_Mips, CLI.getArgs(), Callee.getNode());
2532
2533	// Get a count of how many bytes are to be pushed on the stack.
2534	unsigned NextStackOffset = CCInfo.getNextStackOffset();
2535
2536	// Check if it's really possible to do a tail call.
2537	if (IsTailCall)
2538	IsTailCall = isEligibleForTailCallOptimization(
2539	CCInfo, NextStackOffset, *MF.getInfo<MipsFunctionInfo>());
2540
2541	if (!IsTailCall && CLI.CS && CLI.CS->isMustTailCall())
2542	report_fatal_error("failed to perform tail call elimination on a call "
2543	"site marked musttail");
2544
2545	if (IsTailCall)
2546	++NumTailCalls;
2547
2548	// Chain is the output chain of the last Load/Store or CopyToReg node.
2549	// ByValChain is the output chain of the last Memcpy node created for copying
2550	// byval arguments to the stack.
2551	unsigned StackAlignment = TFL->getStackAlignment();
2552	NextStackOffset = RoundUpToAlignment(NextStackOffset, StackAlignment);
2553	SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, true);
2554
2555	if (!IsTailCall)
2556	Chain = DAG.getCALLSEQ_START(Chain, NextStackOffsetVal, DL);
2557
2558	SDValue StackPtr = DAG.getCopyFromReg(
2559	Chain, DL, Subtarget.isABI_N64() ? Mips::SP_64 : Mips::SP,
2560	getPointerTy());
2561
2562	// With EABI is it possible to have 16 args on registers.
2563	std::deque< std::pair<unsigned, SDValue> > RegsToPass;
2564	SmallVector<SDValue, 8> MemOpChains;
2565
2566	CCInfo.rewindByValRegsInfo();
2567
2568	// Walk the register/memloc assignments, inserting copies/loads.
2569	for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2570	SDValue Arg = OutVals[i];
2571	CCValAssign &VA = ArgLocs[i];
2572	MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT();
2573	ISD::ArgFlagsTy Flags = Outs[i].Flags;
2574	bool UseUpperBits = false;
2575
2576	// ByVal Arg.
2577	if (Flags.isByVal()) {
2578	unsigned FirstByValReg, LastByValReg;
2579	unsigned ByValIdx = CCInfo.getInRegsParamsProcessed();
2580	CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg);
2581
2582	assert(Flags.getByValSize() &&((Flags.getByValSize() && "ByVal args of size 0 should have been ignored by front-end." ) ? static_cast<void> (0) : __assert_fail ("Flags.getByValSize() && \"ByVal args of size 0 should have been ignored by front-end.\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn227492/lib/Target/Mips/MipsISelLowering.cpp" , 2583, __PRETTY_FUNCTION__))
2583	"ByVal args of size 0 should have been ignored by front-end.")((Flags.getByValSize() && "ByVal args of size 0 should have been ignored by front-end." ) ? static_cast<void> (0) : __assert_fail ("Flags.getByValSize() && \"ByVal args of size 0 should have been ignored by front-end.\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn227492/lib/Target/Mips/MipsISelLowering.cpp" , 2583, __PRETTY_FUNCTION__));
2584	assert(ByValIdx < CCInfo.getInRegsParamsCount())((ByValIdx < CCInfo.getInRegsParamsCount()) ? static_cast< void> (0) : __assert_fail ("ByValIdx < CCInfo.getInRegsParamsCount()" , "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn227492/lib/Target/Mips/MipsISelLowering.cpp" , 2584, __PRETTY_FUNCTION__));
2585	assert(!IsTailCall &&((!IsTailCall && "Do not tail-call optimize if there is a byval argument." ) ? static_cast<void> (0) : __assert_fail ("!IsTailCall && \"Do not tail-call optimize if there is a byval argument.\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn227492/lib/Target/Mips/MipsISelLowering.cpp" , 2586, __PRETTY_FUNCTION__))
2586	"Do not tail-call optimize if there is a byval argument.")((!IsTailCall && "Do not tail-call optimize if there is a byval argument." ) ? static_cast<void> (0) : __assert_fail ("!IsTailCall && \"Do not tail-call optimize if there is a byval argument.\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn227492/lib/Target/Mips/MipsISelLowering.cpp" , 2586, __PRETTY_FUNCTION__));
2587	passByValArg(Chain, DL, RegsToPass, MemOpChains, StackPtr, MFI, DAG, Arg,
2588	FirstByValReg, LastByValReg, Flags, Subtarget.isLittle(),
2589	VA);
2590	CCInfo.nextInRegsParam();
2591	continue;
2592	}
2593
2594	// Promote the value if needed.
2595	switch (VA.getLocInfo()) {
2596	default:
2597	llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn227492/lib/Target/Mips/MipsISelLowering.cpp" , 2597);
2598	case CCValAssign::Full:
2599	if (VA.isRegLoc()) {
2600	if ((ValVT == MVT::f32 && LocVT == MVT::i32) \|\|
2601	(ValVT == MVT::f64 && LocVT == MVT::i64) \|\|
2602	(ValVT == MVT::i64 && LocVT == MVT::f64))
2603	Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg);
2604	else if (ValVT == MVT::f64 && LocVT == MVT::i32) {
2605	SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
2606	Arg, DAG.getConstant(0, MVT::i32));
2607	SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
2608	Arg, DAG.getConstant(1, MVT::i32));
2609	if (!Subtarget.isLittle())
2610	std::swap(Lo, Hi);
2611	unsigned LocRegLo = VA.getLocReg();
2612	unsigned LocRegHigh = getNextIntArgReg(LocRegLo);
2613	RegsToPass.push_back(std::make_pair(LocRegLo, Lo));
2614	RegsToPass.push_back(std::make_pair(LocRegHigh, Hi));
2615	continue;
2616	}
2617	}
2618	break;
2619	case CCValAssign::BCvt:
2620	Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg);
2621	break;
2622	case CCValAssign::SExtUpper:
2623	UseUpperBits = true;
2624	// Fallthrough
2625	case CCValAssign::SExt:
2626	Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, LocVT, Arg);
2627	break;
2628	case CCValAssign::ZExtUpper:
2629	UseUpperBits = true;
2630	// Fallthrough
2631	case CCValAssign::ZExt:
2632	Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, LocVT, Arg);
2633	break;
2634	case CCValAssign::AExtUpper:
2635	UseUpperBits = true;
2636	// Fallthrough
2637	case CCValAssign::AExt:
2638	Arg = DAG.getNode(ISD::ANY_EXTEND, DL, LocVT, Arg);
2639	break;
2640	}
2641
2642	if (UseUpperBits) {
2643	unsigned ValSizeInBits = Outs[i].ArgVT.getSizeInBits();
2644	unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
2645	Arg = DAG.getNode(
2646	ISD::SHL, DL, VA.getLocVT(), Arg,
2647	DAG.getConstant(LocSizeInBits - ValSizeInBits, VA.getLocVT()));
2648	}
2649
2650	// Arguments that can be passed on register must be kept at
2651	// RegsToPass vector
2652	if (VA.isRegLoc()) {
2653	RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2654	continue;
2655	}
2656
2657	// Register can't get to this point...
2658	assert(VA.isMemLoc())((VA.isMemLoc()) ? static_cast<void> (0) : __assert_fail ("VA.isMemLoc()", "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn227492/lib/Target/Mips/MipsISelLowering.cpp" , 2658, __PRETTY_FUNCTION__));
2659
2660	// emit ISD::STORE whichs stores the
2661	// parameter value to a stack Location
2662	MemOpChains.push_back(passArgOnStack(StackPtr, VA.getLocMemOffset(),
2663	Chain, Arg, DL, IsTailCall, DAG));
2664	}
2665
2666	// Transform all store nodes into one single node because all store
2667	// nodes are independent of each other.
2668	if (!MemOpChains.empty())
2669	Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
2670
2671	// If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
2672	// direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
2673	// node so that legalize doesn't hack it.
2674	bool IsPICCall =
2675	(Subtarget.isABI_N64() \|\| IsPIC); // true if calls are translated to
2676	// jalr $25
2677	bool GlobalOrExternal = false, InternalLinkage = false, IsCallReloc = false;
2678	SDValue CalleeLo;
2679	EVT Ty = Callee.getValueType();
2680
2681	if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2682	if (IsPICCall) {
2683	const GlobalValue *Val = G->getGlobal();
2684	InternalLinkage = Val->hasInternalLinkage();
2685
2686	if (InternalLinkage)
2687	Callee = getAddrLocal(G, DL, Ty, DAG,
2688	Subtarget.isABI_N32() \|\| Subtarget.isABI_N64());
2689	else if (LargeGOT) {
2690	Callee = getAddrGlobalLargeGOT(G, DL, Ty, DAG, MipsII::MO_CALL_HI16,
2691	MipsII::MO_CALL_LO16, Chain,
2692	FuncInfo->callPtrInfo(Val));
2693	IsCallReloc = true;
2694	} else {
2695	Callee = getAddrGlobal(G, DL, Ty, DAG, MipsII::MO_GOT_CALL, Chain,
2696	FuncInfo->callPtrInfo(Val));
2697	IsCallReloc = true;
2698	}
2699	} else
2700	Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, getPointerTy(), 0,
2701	MipsII::MO_NO_FLAG);
2702	GlobalOrExternal = true;
2703	}
2704	else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2705	const char *Sym = S->getSymbol();
2706
2707	if (!Subtarget.isABI_N64() && !IsPIC) // !N64 && static
2708	Callee =
2709	DAG.getTargetExternalSymbol(Sym, getPointerTy(), MipsII::MO_NO_FLAG);
2710	else if (LargeGOT) {
2711	Callee = getAddrGlobalLargeGOT(S, DL, Ty, DAG, MipsII::MO_CALL_HI16,
2712	MipsII::MO_CALL_LO16, Chain,
2713	FuncInfo->callPtrInfo(Sym));
2714	IsCallReloc = true;
2715	} else { // N64 \|\| PIC
2716	Callee = getAddrGlobal(S, DL, Ty, DAG, MipsII::MO_GOT_CALL, Chain,
2717	FuncInfo->callPtrInfo(Sym));
2718	IsCallReloc = true;
2719	}
2720
2721	GlobalOrExternal = true;
2722	}
2723
2724	SmallVector<SDValue, 8> Ops(1, Chain);
2725	SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2726
2727	getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal, InternalLinkage,
2728	IsCallReloc, CLI, Callee, Chain);
2729
2730	if (IsTailCall)
2731	return DAG.getNode(MipsISD::TailCall, DL, MVT::Other, Ops);
2732
2733	Chain = DAG.getNode(MipsISD::JmpLink, DL, NodeTys, Ops);
2734	SDValue InFlag = Chain.getValue(1);
2735
2736	// Create the CALLSEQ_END node.
2737	Chain = DAG.getCALLSEQ_END(Chain, NextStackOffsetVal,
2738	DAG.getIntPtrConstant(0, true), InFlag, DL);
2739	InFlag = Chain.getValue(1);
2740
2741	// Handle result values, copying them out of physregs into vregs that we
2742	// return.
2743	return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG,
2744	InVals, CLI);
2745	}
2746
2747	/// LowerCallResult - Lower the result values of a call into the
2748	/// appropriate copies out of appropriate physical registers.
2749	SDValue MipsTargetLowering::LowerCallResult(
2750	SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool IsVarArg,
2751	const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG,
2752	SmallVectorImpl<SDValue> &InVals,
2753	TargetLowering::CallLoweringInfo &CLI) const {
2754	// Assign locations to each value returned by this call.
2755	SmallVector<CCValAssign, 16> RVLocs;
2756	MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
2757	*DAG.getContext());
2758	CCInfo.AnalyzeCallResult(Ins, RetCC_Mips, CLI);
2759
2760	// Copy all of the result registers out of their specified physreg.
2761	for (unsigned i = 0; i != RVLocs.size(); ++i) {
2762	CCValAssign &VA = RVLocs[i];
2763	assert(VA.isRegLoc() && "Can only return in registers!")((VA.isRegLoc() && "Can only return in registers!") ? static_cast<void> (0) : __assert_fail ("VA.isRegLoc() && \"Can only return in registers!\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn227492/lib/Target/Mips/MipsISelLowering.cpp" , 2763, __PRETTY_FUNCTION__));
2764
2765	SDValue Val = DAG.getCopyFromReg(Chain, DL, RVLocs[i].getLocReg(),
2766	RVLocs[i].getLocVT(), InFlag);
2767	Chain = Val.getValue(1);
2768	InFlag = Val.getValue(2);
2769
2770	if (VA.isUpperBitsInLoc()) {
2771	unsigned ValSizeInBits = Ins[i].ArgVT.getSizeInBits();
2772	unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
2773	unsigned Shift =
2774	VA.getLocInfo() == CCValAssign::ZExtUpper ? ISD::SRL : ISD::SRA;
2775	Val = DAG.getNode(
2776	Shift, DL, VA.getLocVT(), Val,
2777	DAG.getConstant(LocSizeInBits - ValSizeInBits, VA.getLocVT()));
2778	}
2779
2780	switch (VA.getLocInfo()) {
2781	default:
2782	llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn227492/lib/Target/Mips/MipsISelLowering.cpp" , 2782);
2783	case CCValAssign::Full:
2784	break;
2785	case CCValAssign::BCvt:
2786	Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val);
2787	break;
2788	case CCValAssign::AExt:
2789	case CCValAssign::AExtUpper:
2790	Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
2791	break;
2792	case CCValAssign::ZExt:
2793	case CCValAssign::ZExtUpper:
2794	Val = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Val,
2795	DAG.getValueType(VA.getValVT()));
2796	Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
2797	break;
2798	case CCValAssign::SExt:
2799	case CCValAssign::SExtUpper:
2800	Val = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Val,
2801	DAG.getValueType(VA.getValVT()));
2802	Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
2803	break;
2804	}
2805
2806	InVals.push_back(Val);
2807	}
2808
2809	return Chain;
2810	}
2811
2812	static SDValue UnpackFromArgumentSlot(SDValue Val, const CCValAssign &VA,
2813	EVT ArgVT, SDLoc DL, SelectionDAG &DAG) {
2814	MVT LocVT = VA.getLocVT();
2815	EVT ValVT = VA.getValVT();
2816
2817	// Shift into the upper bits if necessary.
2818	switch (VA.getLocInfo()) {
2819	default:
2820	break;
2821	case CCValAssign::AExtUpper:
2822	case CCValAssign::SExtUpper:
2823	case CCValAssign::ZExtUpper: {
2824	unsigned ValSizeInBits = ArgVT.getSizeInBits();
2825	unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
2826	unsigned Opcode =
2827	VA.getLocInfo() == CCValAssign::ZExtUpper ? ISD::SRL : ISD::SRA;
2828	Val = DAG.getNode(
2829	Opcode, DL, VA.getLocVT(), Val,
2830	DAG.getConstant(LocSizeInBits - ValSizeInBits, VA.getLocVT()));
2831	break;
2832	}
2833	}
2834
2835	// If this is an value smaller than the argument slot size (32-bit for O32,
2836	// 64-bit for N32/N64), it has been promoted in some way to the argument slot
2837	// size. Extract the value and insert any appropriate assertions regarding
2838	// sign/zero extension.
2839	switch (VA.getLocInfo()) {
2840	default:
2841	llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn227492/lib/Target/Mips/MipsISelLowering.cpp" , 2841);
2842	case CCValAssign::Full:
2843	break;
2844	case CCValAssign::AExtUpper:
2845	case CCValAssign::AExt:
2846	Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val);
2847	break;
2848	case CCValAssign::SExtUpper:
2849	case CCValAssign::SExt:
2850	Val = DAG.getNode(ISD::AssertSext, DL, LocVT, Val, DAG.getValueType(ValVT));
2851	Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val);
2852	break;
2853	case CCValAssign::ZExtUpper:
2854	case CCValAssign::ZExt:
2855	Val = DAG.getNode(ISD::AssertZext, DL, LocVT, Val, DAG.getValueType(ValVT));
2856	Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val);
2857	break;
2858	case CCValAssign::BCvt:
2859	Val = DAG.getNode(ISD::BITCAST, DL, ValVT, Val);
2860	break;
2861	}
2862
2863	return Val;
2864	}
2865
2866	//===----------------------------------------------------------------------===//
2867	// Formal Arguments Calling Convention Implementation
2868	//===----------------------------------------------------------------------===//
2869	/// LowerFormalArguments - transform physical registers into virtual registers
2870	/// and generate load operations for arguments places on the stack.
2871	SDValue
2872	MipsTargetLowering::LowerFormalArguments(SDValue Chain,
2873	CallingConv::ID CallConv,
2874	bool IsVarArg,
2875	const SmallVectorImpl<ISD::InputArg> &Ins,
2876	SDLoc DL, SelectionDAG &DAG,
2877	SmallVectorImpl<SDValue> &InVals)
2878	const {
2879	MachineFunction &MF = DAG.getMachineFunction();
2880	MachineFrameInfo *MFI = MF.getFrameInfo();
2881	MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
2882
2883	MipsFI->setVarArgsFrameIndex(0);
2884
2885	// Used with vargs to acumulate store chains.
2886	std::vector<SDValue> OutChains;
2887
2888	// Assign locations to all of the incoming arguments.
2889	SmallVector<CCValAssign, 16> ArgLocs;
2890	MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
2891	*DAG.getContext());
2892	const MipsABIInfo &ABI =
2893	static_cast<const MipsTargetMachine &>(MF.getTarget()).getABI();
2894	CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(CallConv), 1);
2895	Function::const_arg_iterator FuncArg =
2896	DAG.getMachineFunction().getFunction()->arg_begin();
2897
2898	CCInfo.AnalyzeFormalArguments(Ins, CC_Mips_FixedArg);
2899	MipsFI->setFormalArgInfo(CCInfo.getNextStackOffset(),
2900	CCInfo.getInRegsParamsCount() > 0);
2901
2902	unsigned CurArgIdx = 0;
2903	CCInfo.rewindByValRegsInfo();
2904
2905	for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2906	CCValAssign &VA = ArgLocs[i];
2907	std::advance(FuncArg, Ins[i].OrigArgIndex - CurArgIdx);
2908	CurArgIdx = Ins[i].OrigArgIndex;
2909	EVT ValVT = VA.getValVT();
2910	ISD::ArgFlagsTy Flags = Ins[i].Flags;
2911	bool IsRegLoc = VA.isRegLoc();
2912
2913	if (Flags.isByVal()) {
2914	unsigned FirstByValReg, LastByValReg;
2915	unsigned ByValIdx = CCInfo.getInRegsParamsProcessed();
2916	CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg);
2917
2918	assert(Flags.getByValSize() &&((Flags.getByValSize() && "ByVal args of size 0 should have been ignored by front-end." ) ? static_cast<void> (0) : __assert_fail ("Flags.getByValSize() && \"ByVal args of size 0 should have been ignored by front-end.\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn227492/lib/Target/Mips/MipsISelLowering.cpp" , 2919, __PRETTY_FUNCTION__))
2919	"ByVal args of size 0 should have been ignored by front-end.")((Flags.getByValSize() && "ByVal args of size 0 should have been ignored by front-end." ) ? static_cast<void> (0) : __assert_fail ("Flags.getByValSize() && \"ByVal args of size 0 should have been ignored by front-end.\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn227492/lib/Target/Mips/MipsISelLowering.cpp" , 2919, __PRETTY_FUNCTION__));
2920	assert(ByValIdx < CCInfo.getInRegsParamsCount())((ByValIdx < CCInfo.getInRegsParamsCount()) ? static_cast< void> (0) : __assert_fail ("ByValIdx < CCInfo.getInRegsParamsCount()" , "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn227492/lib/Target/Mips/MipsISelLowering.cpp" , 2920, __PRETTY_FUNCTION__));
2921	copyByValRegs(Chain, DL, OutChains, DAG, Flags, InVals, &*FuncArg,
2922	FirstByValReg, LastByValReg, VA, CCInfo);
2923	CCInfo.nextInRegsParam();
2924	continue;
2925	}
2926
2927	// Arguments stored on registers
2928	if (IsRegLoc) {
2929	MVT RegVT = VA.getLocVT();
2930	unsigned ArgReg = VA.getLocReg();
2931	const TargetRegisterClass *RC = getRegClassFor(RegVT);
2932
2933	// Transform the arguments stored on
2934	// physical registers into virtual ones
2935	unsigned Reg = addLiveIn(DAG.getMachineFunction(), ArgReg, RC);
2936	SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT);
2937
2938	ArgValue = UnpackFromArgumentSlot(ArgValue, VA, Ins[i].ArgVT, DL, DAG);
2939
2940	// Handle floating point arguments passed in integer registers and
2941	// long double arguments passed in floating point registers.
2942	if ((RegVT == MVT::i32 && ValVT == MVT::f32) \|\|
2943	(RegVT == MVT::i64 && ValVT == MVT::f64) \|\|
2944	(RegVT == MVT::f64 && ValVT == MVT::i64))
2945	ArgValue = DAG.getNode(ISD::BITCAST, DL, ValVT, ArgValue);
2946	else if (Subtarget.isABI_O32() && RegVT == MVT::i32 &&
2947	ValVT == MVT::f64) {
2948	unsigned Reg2 = addLiveIn(DAG.getMachineFunction(),
2949	getNextIntArgReg(ArgReg), RC);
2950	SDValue ArgValue2 = DAG.getCopyFromReg(Chain, DL, Reg2, RegVT);
2951	if (!Subtarget.isLittle())
2952	std::swap(ArgValue, ArgValue2);
2953	ArgValue = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64,
2954	ArgValue, ArgValue2);
2955	}
2956
2957	InVals.push_back(ArgValue);
2958	} else { // VA.isRegLoc()
2959	MVT LocVT = VA.getLocVT();
2960
2961	if (Subtarget.isABI_O32()) {
2962	// We ought to be able to use LocVT directly but O32 sets it to i32
2963	// when allocating floating point values to integer registers.
2964	// This shouldn't influence how we load the value into registers unless
2965	// we are targetting softfloat.
2966	if (VA.getValVT().isFloatingPoint() && !Subtarget.abiUsesSoftFloat())
2967	LocVT = VA.getValVT();
2968	}
2969
2970	// sanity check
2971	assert(VA.isMemLoc())((VA.isMemLoc()) ? static_cast<void> (0) : __assert_fail ("VA.isMemLoc()", "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn227492/lib/Target/Mips/MipsISelLowering.cpp" , 2971, __PRETTY_FUNCTION__));
2972
2973	// The stack pointer offset is relative to the caller stack frame.
2974	int FI = MFI->CreateFixedObject(LocVT.getSizeInBits() / 8,
2975	VA.getLocMemOffset(), true);
2976
2977	// Create load nodes to retrieve arguments from the stack
2978	SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2979	SDValue ArgValue = DAG.getLoad(LocVT, DL, Chain, FIN,
2980	MachinePointerInfo::getFixedStack(FI),
2981	false, false, false, 0);
2982	OutChains.push_back(ArgValue.getValue(1));
2983
2984	ArgValue = UnpackFromArgumentSlot(ArgValue, VA, Ins[i].ArgVT, DL, DAG);
2985
2986	InVals.push_back(ArgValue);
2987	}
2988	}
2989
2990	for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2991	// The mips ABIs for returning structs by value requires that we copy
2992	// the sret argument into $v0 for the return. Save the argument into
2993	// a virtual register so that we can access it from the return points.
2994	if (Ins[i].Flags.isSRet()) {
2995	unsigned Reg = MipsFI->getSRetReturnReg();
2996	if (!Reg) {
2997	Reg = MF.getRegInfo().createVirtualRegister(
2998	getRegClassFor(Subtarget.isABI_N64() ? MVT::i64 : MVT::i32));
2999	MipsFI->setSRetReturnReg(Reg);
3000	}
3001	SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), DL, Reg, InVals[i]);
3002	Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Copy, Chain);
3003	break;
3004	}
3005	}
3006
3007	if (IsVarArg)
3008	writeVarArgRegs(OutChains, Chain, DL, DAG, CCInfo);
3009
3010	// All stores are grouped in one node to allow the matching between
3011	// the size of Ins and InVals. This only happens when on varg functions
3012	if (!OutChains.empty()) {
3013	OutChains.push_back(Chain);
3014	Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains);
3015	}
3016
3017	return Chain;
3018	}
3019
3020	//===----------------------------------------------------------------------===//
3021	// Return Value Calling Convention Implementation
3022	//===----------------------------------------------------------------------===//
3023
3024	bool
3025	MipsTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
3026	MachineFunction &MF, bool IsVarArg,
3027	const SmallVectorImpl<ISD::OutputArg> &Outs,
3028	LLVMContext &Context) const {
3029	SmallVector<CCValAssign, 16> RVLocs;
3030	MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
3031	return CCInfo.CheckReturn(Outs, RetCC_Mips);
3032	}
3033
3034	SDValue
3035	MipsTargetLowering::LowerReturn(SDValue Chain,
3036	CallingConv::ID CallConv, bool IsVarArg,
3037	const SmallVectorImpl<ISD::OutputArg> &Outs,
3038	const SmallVectorImpl<SDValue> &OutVals,
3039	SDLoc DL, SelectionDAG &DAG) const {
3040	// CCValAssign - represent the assignment of
3041	// the return value to a location
3042	SmallVector<CCValAssign, 16> RVLocs;
3043	MachineFunction &MF = DAG.getMachineFunction();
3044
3045	// CCState - Info about the registers and stack slot.
3046	MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext());
3047
3048	// Analyze return values.
3049	CCInfo.AnalyzeReturn(Outs, RetCC_Mips);
3050
3051	SDValue Flag;
3052	SmallVector<SDValue, 4> RetOps(1, Chain);
3053
3054	// Copy the result values into the output registers.
3055	for (unsigned i = 0; i != RVLocs.size(); ++i) {
3056	SDValue Val = OutVals[i];
3057	CCValAssign &VA = RVLocs[i];
3058	assert(VA.isRegLoc() && "Can only return in registers!")((VA.isRegLoc() && "Can only return in registers!") ? static_cast<void> (0) : __assert_fail ("VA.isRegLoc() && \"Can only return in registers!\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn227492/lib/Target/Mips/MipsISelLowering.cpp" , 3058, __PRETTY_FUNCTION__));
3059	bool UseUpperBits = false;
3060
3061	switch (VA.getLocInfo()) {
3062	default:
3063	llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn227492/lib/Target/Mips/MipsISelLowering.cpp" , 3063);
3064	case CCValAssign::Full:
3065	break;
3066	case CCValAssign::BCvt:
3067	Val = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Val);
3068	break;
3069	case CCValAssign::AExtUpper:
3070	UseUpperBits = true;
3071	// Fallthrough
3072	case CCValAssign::AExt:
3073	Val = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Val);
3074	break;
3075	case CCValAssign::ZExtUpper:
3076	UseUpperBits = true;
3077	// Fallthrough
3078	case CCValAssign::ZExt:
3079	Val = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Val);
3080	break;
3081	case CCValAssign::SExtUpper:
3082	UseUpperBits = true;
3083	// Fallthrough
3084	case CCValAssign::SExt:
3085	Val = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Val);
3086	break;
3087	}
3088
3089	if (UseUpperBits) {
3090	unsigned ValSizeInBits = Outs[i].ArgVT.getSizeInBits();
3091	unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
3092	Val = DAG.getNode(
3093	ISD::SHL, DL, VA.getLocVT(), Val,
3094	DAG.getConstant(LocSizeInBits - ValSizeInBits, VA.getLocVT()));
3095	}
3096
3097	Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Flag);
3098
3099	// Guarantee that all emitted copies are stuck together with flags.
3100	Flag = Chain.getValue(1);
3101	RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
3102	}
3103
3104	// The mips ABIs for returning structs by value requires that we copy
3105	// the sret argument into $v0 for the return. We saved the argument into
3106	// a virtual register in the entry block, so now we copy the value out
3107	// and into $v0.
3108	if (MF.getFunction()->hasStructRetAttr()) {
3109	MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
3110	unsigned Reg = MipsFI->getSRetReturnReg();
3111
3112	if (!Reg)
3113	llvm_unreachable("sret virtual register not created in the entry block")::llvm::llvm_unreachable_internal("sret virtual register not created in the entry block" , "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn227492/lib/Target/Mips/MipsISelLowering.cpp" , 3113);
3114	SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy());
3115	unsigned V0 = Subtarget.isABI_N64() ? Mips::V0_64 : Mips::V0;
3116
3117	Chain = DAG.getCopyToReg(Chain, DL, V0, Val, Flag);
3118	Flag = Chain.getValue(1);
3119	RetOps.push_back(DAG.getRegister(V0, getPointerTy()));
3120	}
3121
3122	RetOps[0] = Chain; // Update chain.
3123
3124	// Add the flag if we have it.
3125	if (Flag.getNode())
3126	RetOps.push_back(Flag);
3127
3128	// Return on Mips is always a "jr $ra"
3129	return DAG.getNode(MipsISD::Ret, DL, MVT::Other, RetOps);
3130	}
3131
3132	//===----------------------------------------------------------------------===//
3133	// Mips Inline Assembly Support
3134	//===----------------------------------------------------------------------===//
3135
3136	/// getConstraintType - Given a constraint letter, return the type of
3137	/// constraint it is for this target.
3138	MipsTargetLowering::ConstraintType MipsTargetLowering::
3139	getConstraintType(const std::string &Constraint) const
3140	{
3141	// Mips specific constraints
3142	// GCC config/mips/constraints.md
3143	//
3144	// 'd' : An address register. Equivalent to r
3145	// unless generating MIPS16 code.
3146	// 'y' : Equivalent to r; retained for
3147	// backwards compatibility.
3148	// 'c' : A register suitable for use in an indirect
3149	// jump. This will always be $25 for -mabicalls.
3150	// 'l' : The lo register. 1 word storage.
3151	// 'x' : The hilo register pair. Double word storage.
3152	if (Constraint.size() == 1) {
3153	switch (Constraint[0]) {
3154	default : break;
3155	case 'd':
3156	case 'y':
3157	case 'f':
3158	case 'c':
3159	case 'l':
3160	case 'x':
3161	return C_RegisterClass;
3162	case 'R':
3163	return C_Memory;
3164	}
3165	}
3166	return TargetLowering::getConstraintType(Constraint);
3167	}
3168
3169	/// Examine constraint type and operand type and determine a weight value.
3170	/// This object must already have been set up with the operand type
3171	/// and the current alternative constraint selected.
3172	TargetLowering::ConstraintWeight
3173	MipsTargetLowering::getSingleConstraintMatchWeight(
3174	AsmOperandInfo &info, const char *constraint) const {
3175	ConstraintWeight weight = CW_Invalid;
3176	Value *CallOperandVal = info.CallOperandVal;
3177	// If we don't have a value, we can't do a match,
3178	// but allow it at the lowest weight.
3179	if (!CallOperandVal)
3180	return CW_Default;
3181	Type *type = CallOperandVal->getType();
3182	// Look at the constraint type.
3183	switch (*constraint) {
3184	default:
3185	weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
3186	break;
3187	case 'd':
3188	case 'y':
3189	if (type->isIntegerTy())
3190	weight = CW_Register;
3191	break;
3192	case 'f': // FPU or MSA register
3193	if (Subtarget.hasMSA() && type->isVectorTy() &&
3194	cast<VectorType>(type)->getBitWidth() == 128)
3195	weight = CW_Register;
3196	else if (type->isFloatTy())
3197	weight = CW_Register;
3198	break;
3199	case 'c': // $25 for indirect jumps
3200	case 'l': // lo register
3201	case 'x': // hilo register pair
3202	if (type->isIntegerTy())
3203	weight = CW_SpecificReg;
3204	break;
3205	case 'I': // signed 16 bit immediate
3206	case 'J': // integer zero
3207	case 'K': // unsigned 16 bit immediate
3208	case 'L': // signed 32 bit immediate where lower 16 bits are 0
3209	case 'N': // immediate in the range of -65535 to -1 (inclusive)
3210	case 'O': // signed 15 bit immediate (+- 16383)
3211	case 'P': // immediate in the range of 65535 to 1 (inclusive)
3212	if (isa<ConstantInt>(CallOperandVal))
3213	weight = CW_Constant;
3214	break;
3215	case 'R':
3216	weight = CW_Memory;
3217	break;
3218	}
3219	return weight;
3220	}
3221
3222	/// This is a helper function to parse a physical register string and split it
3223	/// into non-numeric and numeric parts (Prefix and Reg). The first boolean flag
3224	/// that is returned indicates whether parsing was successful. The second flag
3225	/// is true if the numeric part exists.
3226	static std::pair<bool, bool>
3227	parsePhysicalReg(StringRef C, std::string &Prefix,
3228	unsigned long long &Reg) {
3229	if (C.front() != '{' \|\| C.back() != '}')
3230	return std::make_pair(false, false);
3231
3232	// Search for the first numeric character.
3233	StringRef::const_iterator I, B = C.begin() + 1, E = C.end() - 1;
3234	I = std::find_if(B, E, std::ptr_fun(isdigit));
3235
3236	Prefix.assign(B, I - B);
3237
3238	// The second flag is set to false if no numeric characters were found.
3239	if (I == E)
3240	return std::make_pair(true, false);
3241
3242	// Parse the numeric characters.
3243	return std::make_pair(!getAsUnsignedInteger(StringRef(I, E - I), 10, Reg),
3244	true);
3245	}
3246
3247	std::pair<unsigned, const TargetRegisterClass *> MipsTargetLowering::
3248	parseRegForInlineAsmConstraint(StringRef C, MVT VT) const {
3249	const TargetRegisterInfo *TRI =
3250	getTargetMachine().getSubtargetImpl()->getRegisterInfo();
3251	const TargetRegisterClass *RC;
3252	std::string Prefix;
3253	unsigned long long Reg;
3254
3255	std::pair<bool, bool> R = parsePhysicalReg(C, Prefix, Reg);
3256
3257	if (!R.first)
3258	return std::make_pair(0U, nullptr);
3259
3260	if ((Prefix == "hi" \|\| Prefix == "lo")) { // Parse hi/lo.
3261	// No numeric characters follow "hi" or "lo".
3262	if (R.second)
3263	return std::make_pair(0U, nullptr);
3264
3265	RC = TRI->getRegClass(Prefix == "hi" ?
3266	Mips::HI32RegClassID : Mips::LO32RegClassID);
3267	return std::make_pair(*(RC->begin()), RC);
3268	} else if (Prefix.compare(0, 4, "$msa") == 0) {
3269	// Parse $msa(ir\|csr\|access\|save\|modify\|request\|map\|unmap)
3270
3271	// No numeric characters follow the name.
3272	if (R.second)
3273	return std::make_pair(0U, nullptr);
3274
3275	Reg = StringSwitch<unsigned long long>(Prefix)
3276	.Case("$msair", Mips::MSAIR)
3277	.Case("$msacsr", Mips::MSACSR)
3278	.Case("$msaaccess", Mips::MSAAccess)
3279	.Case("$msasave", Mips::MSASave)
3280	.Case("$msamodify", Mips::MSAModify)
3281	.Case("$msarequest", Mips::MSARequest)
3282	.Case("$msamap", Mips::MSAMap)
3283	.Case("$msaunmap", Mips::MSAUnmap)
3284	.Default(0);
3285
3286	if (!Reg)
3287	return std::make_pair(0U, nullptr);
3288
3289	RC = TRI->getRegClass(Mips::MSACtrlRegClassID);
3290	return std::make_pair(Reg, RC);
3291	}
3292
3293	if (!R.second)
3294	return std::make_pair(0U, nullptr);
3295
3296	if (Prefix == "$f") { // Parse $f0-$f31.
3297	// If the size of FP registers is 64-bit or Reg is an even number, select
3298	// the 64-bit register class. Otherwise, select the 32-bit register class.
3299	if (VT == MVT::Other)
3300	VT = (Subtarget.isFP64bit() \|\| !(Reg % 2)) ? MVT::f64 : MVT::f32;
3301
3302	RC = getRegClassFor(VT);
3303
3304	if (RC == &Mips::AFGR64RegClass) {
3305	assert(Reg % 2 == 0)((Reg % 2 == 0) ? static_cast<void> (0) : __assert_fail ("Reg % 2 == 0", "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn227492/lib/Target/Mips/MipsISelLowering.cpp" , 3305, __PRETTY_FUNCTION__));
3306	Reg >>= 1;
3307	}
3308	} else if (Prefix == "$fcc") // Parse $fcc0-$fcc7.
3309	RC = TRI->getRegClass(Mips::FCCRegClassID);
3310	else if (Prefix == "$w") { // Parse $w0-$w31.
3311	RC = getRegClassFor((VT == MVT::Other) ? MVT::v16i8 : VT);
3312	} else { // Parse $0-$31.
3313	assert(Prefix == "$")((Prefix == "$") ? static_cast<void> (0) : __assert_fail ("Prefix == \"$\"", "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn227492/lib/Target/Mips/MipsISelLowering.cpp" , 3313, __PRETTY_FUNCTION__));
3314	RC = getRegClassFor((VT == MVT::Other) ? MVT::i32 : VT);
3315	}
3316
3317	assert(Reg < RC->getNumRegs())((Reg < RC->getNumRegs()) ? static_cast<void> (0) : __assert_fail ("Reg < RC->getNumRegs()", "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn227492/lib/Target/Mips/MipsISelLowering.cpp" , 3317, __PRETTY_FUNCTION__));
3318	return std::make_pair(*(RC->begin() + Reg), RC);
3319	}
3320
3321	/// Given a register class constraint, like 'r', if this corresponds directly
3322	/// to an LLVM register class, return a register of 0 and the register class
3323	/// pointer.
3324	std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering::
3325	getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const
3326	{
3327	if (Constraint.size() == 1) {
3328	switch (Constraint[0]) {
3329	case 'd': // Address register. Same as 'r' unless generating MIPS16 code.
3330	case 'y': // Same as 'r'. Exists for compatibility.
3331	case 'r':
3332	if (VT == MVT::i32 \|\| VT == MVT::i16 \|\| VT == MVT::i8) {
3333	if (Subtarget.inMips16Mode())
3334	return std::make_pair(0U, &Mips::CPU16RegsRegClass);
3335	return std::make_pair(0U, &Mips::GPR32RegClass);
3336	}
3337	if (VT == MVT::i64 && !Subtarget.isGP64bit())
3338	return std::make_pair(0U, &Mips::GPR32RegClass);
3339	if (VT == MVT::i64 && Subtarget.isGP64bit())
3340	return std::make_pair(0U, &Mips::GPR64RegClass);
3341	// This will generate an error message
3342	return std::make_pair(0U, nullptr);
3343	case 'f': // FPU or MSA register
3344	if (VT == MVT::v16i8)
3345	return std::make_pair(0U, &Mips::MSA128BRegClass);
3346	else if (VT == MVT::v8i16 \|\| VT == MVT::v8f16)
3347	return std::make_pair(0U, &Mips::MSA128HRegClass);
3348	else if (VT == MVT::v4i32 \|\| VT == MVT::v4f32)
3349	return std::make_pair(0U, &Mips::MSA128WRegClass);
3350	else if (VT == MVT::v2i64 \|\| VT == MVT::v2f64)
3351	return std::make_pair(0U, &Mips::MSA128DRegClass);
3352	else if (VT == MVT::f32)
3353	return std::make_pair(0U, &Mips::FGR32RegClass);
3354	else if ((VT == MVT::f64) && (!Subtarget.isSingleFloat())) {
3355	if (Subtarget.isFP64bit())
3356	return std::make_pair(0U, &Mips::FGR64RegClass);
3357	return std::make_pair(0U, &Mips::AFGR64RegClass);
3358	}
3359	break;
3360	case 'c': // register suitable for indirect jump
3361	if (VT == MVT::i32)
3362	return std::make_pair((unsigned)Mips::T9, &Mips::GPR32RegClass);
3363	assert(VT == MVT::i64 && "Unexpected type.")((VT == MVT::i64 && "Unexpected type.") ? static_cast <void> (0) : __assert_fail ("VT == MVT::i64 && \"Unexpected type.\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn227492/lib/Target/Mips/MipsISelLowering.cpp" , 3363, __PRETTY_FUNCTION__));
3364	return std::make_pair((unsigned)Mips::T9_64, &Mips::GPR64RegClass);
3365	case 'l': // register suitable for indirect jump
3366	if (VT == MVT::i32)
3367	return std::make_pair((unsigned)Mips::LO0, &Mips::LO32RegClass);
3368	return std::make_pair((unsigned)Mips::LO0_64, &Mips::LO64RegClass);
3369	case 'x': // register suitable for indirect jump
3370	// Fixme: Not triggering the use of both hi and low
3371	// This will generate an error message
3372	return std::make_pair(0U, nullptr);
3373	}
3374	}
3375
3376	std::pair<unsigned, const TargetRegisterClass *> R;
3377	R = parseRegForInlineAsmConstraint(Constraint, VT);
3378
3379	if (R.second)
3380	return R;
3381
3382	return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
3383	}
3384
3385	/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
3386	/// vector. If it is invalid, don't add anything to Ops.
3387	void MipsTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
3388	std::string &Constraint,
3389	std::vector<SDValue>&Ops,
3390	SelectionDAG &DAG) const {
3391	SDValue Result;
3392
3393	// Only support length 1 constraints for now.
3394	if (Constraint.length() > 1) return;
3395
3396	char ConstraintLetter = Constraint[0];
3397	switch (ConstraintLetter) {
3398	default: break; // This will fall through to the generic implementation
3399	case 'I': // Signed 16 bit constant
3400	// If this fails, the parent routine will give an error
3401	if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3402	EVT Type = Op.getValueType();
3403	int64_t Val = C->getSExtValue();
3404	if (isInt<16>(Val)) {
3405	Result = DAG.getTargetConstant(Val, Type);
3406	break;
3407	}
3408	}
3409	return;
3410	case 'J': // integer zero
3411	if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3412	EVT Type = Op.getValueType();
3413	int64_t Val = C->getZExtValue();
3414	if (Val == 0) {
3415	Result = DAG.getTargetConstant(0, Type);
3416	break;
3417	}
3418	}
3419	return;
3420	case 'K': // unsigned 16 bit immediate
3421	if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3422	EVT Type = Op.getValueType();
3423	uint64_t Val = (uint64_t)C->getZExtValue();
3424	if (isUInt<16>(Val)) {
3425	Result = DAG.getTargetConstant(Val, Type);
3426	break;
3427	}
3428	}
3429	return;
3430	case 'L': // signed 32 bit immediate where lower 16 bits are 0
3431	if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3432	EVT Type = Op.getValueType();
3433	int64_t Val = C->getSExtValue();
3434	if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)){
3435	Result = DAG.getTargetConstant(Val, Type);
3436	break;
3437	}
3438	}
3439	return;
3440	case 'N': // immediate in the range of -65535 to -1 (inclusive)
3441	if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3442	EVT Type = Op.getValueType();
3443	int64_t Val = C->getSExtValue();
3444	if ((Val >= -65535) && (Val <= -1)) {
3445	Result = DAG.getTargetConstant(Val, Type);
3446	break;
3447	}
3448	}
3449	return;
3450	case 'O': // signed 15 bit immediate
3451	if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3452	EVT Type = Op.getValueType();
3453	int64_t Val = C->getSExtValue();
3454	if ((isInt<15>(Val))) {
3455	Result = DAG.getTargetConstant(Val, Type);
3456	break;
3457	}
3458	}
3459	return;
3460	case 'P': // immediate in the range of 1 to 65535 (inclusive)
3461	if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3462	EVT Type = Op.getValueType();
3463	int64_t Val = C->getSExtValue();
3464	if ((Val <= 65535) && (Val >= 1)) {
3465	Result = DAG.getTargetConstant(Val, Type);
3466	break;
3467	}
3468	}
3469	return;
3470	}
3471
3472	if (Result.getNode()) {
3473	Ops.push_back(Result);
3474	return;
3475	}
3476
3477	TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
3478	}
3479
3480	bool MipsTargetLowering::isLegalAddressingMode(const AddrMode &AM,
3481	Type *Ty) const {
3482	// No global is ever allowed as a base.
3483	if (AM.BaseGV)
3484	return false;
3485
3486	switch (AM.Scale) {
3487	case 0: // "r+i" or just "i", depending on HasBaseReg.
3488	break;
3489	case 1:
3490	if (!AM.HasBaseReg) // allow "r+i".
3491	break;
3492	return false; // disallow "r+r" or "r+r+i".
3493	default:
3494	return false;
3495	}
3496
3497	return true;
3498	}
3499
3500	bool
3501	MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
3502	// The Mips target isn't yet aware of offsets.
3503	return false;
3504	}
3505
3506	EVT MipsTargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
3507	unsigned SrcAlign,
3508	bool IsMemset, bool ZeroMemset,
3509	bool MemcpyStrSrc,
3510	MachineFunction &MF) const {
3511	if (Subtarget.hasMips64())
3512	return MVT::i64;
3513
3514	return MVT::i32;
3515	}
3516
3517	bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3518	if (VT != MVT::f32 && VT != MVT::f64)
3519	return false;
3520	if (Imm.isNegZero())
3521	return false;
3522	return Imm.isZero();
3523	}
3524
3525	unsigned MipsTargetLowering::getJumpTableEncoding() const {
3526	if (Subtarget.isABI_N64())
3527	return MachineJumpTableInfo::EK_GPRel64BlockAddress;
3528
3529	return TargetLowering::getJumpTableEncoding();
3530	}
3531
3532	void MipsTargetLowering::copyByValRegs(
3533	SDValue Chain, SDLoc DL, std::vector<SDValue> &OutChains, SelectionDAG &DAG,
3534	const ISD::ArgFlagsTy &Flags, SmallVectorImpl<SDValue> &InVals,
3535	const Argument *FuncArg, unsigned FirstReg, unsigned LastReg,
3536	const CCValAssign &VA, MipsCCState &State) const {
3537	MachineFunction &MF = DAG.getMachineFunction();
3538	MachineFrameInfo *MFI = MF.getFrameInfo();
3539	unsigned GPRSizeInBytes = Subtarget.getGPRSizeInBytes();
3540	unsigned NumRegs = LastReg - FirstReg;
3541	unsigned RegAreaSize = NumRegs * GPRSizeInBytes;
3542	unsigned FrameObjSize = std::max(Flags.getByValSize(), RegAreaSize);
3543	int FrameObjOffset;
3544	const MipsABIInfo &ABI =
3545	static_cast<const MipsTargetMachine &>(MF.getTarget()).getABI();
3546	ArrayRef<MCPhysReg> ByValArgRegs = ABI.GetByValArgRegs();
3547
3548	if (RegAreaSize)
3549	FrameObjOffset =
3550	(int)ABI.GetCalleeAllocdArgSizeInBytes(State.getCallingConv()) -
3551	(int)((ByValArgRegs.size() - FirstReg) * GPRSizeInBytes);
3552	else
3553	FrameObjOffset = VA.getLocMemOffset();
3554
3555	// Create frame object.
3556	EVT PtrTy = getPointerTy();
3557	int FI = MFI->CreateFixedObject(FrameObjSize, FrameObjOffset, true);
3558	SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
3559	InVals.push_back(FIN);
3560
3561	if (!NumRegs)
3562	return;
3563
3564	// Copy arg registers.
3565	MVT RegTy = MVT::getIntegerVT(GPRSizeInBytes * 8);
3566	const TargetRegisterClass *RC = getRegClassFor(RegTy);
3567
3568	for (unsigned I = 0; I < NumRegs; ++I) {
3569	unsigned ArgReg = ByValArgRegs[FirstReg + I];
3570	unsigned VReg = addLiveIn(MF, ArgReg, RC);
3571	unsigned Offset = I * GPRSizeInBytes;
3572	SDValue StorePtr = DAG.getNode(ISD::ADD, DL, PtrTy, FIN,
3573	DAG.getConstant(Offset, PtrTy));
3574	SDValue Store = DAG.getStore(Chain, DL, DAG.getRegister(VReg, RegTy),
3575	StorePtr, MachinePointerInfo(FuncArg, Offset),
3576	false, false, 0);
3577	OutChains.push_back(Store);
3578	}
3579	}
3580
3581	// Copy byVal arg to registers and stack.
3582	void MipsTargetLowering::passByValArg(
3583	SDValue Chain, SDLoc DL,
3584	std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
3585	SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr,
3586	MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg, unsigned FirstReg,
3587	unsigned LastReg, const ISD::ArgFlagsTy &Flags, bool isLittle,
3588	const CCValAssign &VA) const {
3589	unsigned ByValSizeInBytes = Flags.getByValSize();
3590	unsigned OffsetInBytes = 0; // From beginning of struct
3591	unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes();
3592	unsigned Alignment = std::min(Flags.getByValAlign(), RegSizeInBytes);
3593	EVT PtrTy = getPointerTy(), RegTy = MVT::getIntegerVT(RegSizeInBytes * 8);
3594	unsigned NumRegs = LastReg - FirstReg;
3595
3596	if (NumRegs) {
3597	const ArrayRef<MCPhysReg> ArgRegs =
3598	static_cast<const MipsTargetMachine &>(DAG.getTarget())
3599	.getABI()
3600	.GetByValArgRegs();
3601	bool LeftoverBytes = (NumRegs * RegSizeInBytes > ByValSizeInBytes);
3602	unsigned I = 0;
3603
3604	// Copy words to registers.
3605	for (; I < NumRegs - LeftoverBytes; ++I, OffsetInBytes += RegSizeInBytes) {
3606	SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
3607	DAG.getConstant(OffsetInBytes, PtrTy));
3608	SDValue LoadVal = DAG.getLoad(RegTy, DL, Chain, LoadPtr,
3609	MachinePointerInfo(), false, false, false,
3610	Alignment);
3611	MemOpChains.push_back(LoadVal.getValue(1));
3612	unsigned ArgReg = ArgRegs[FirstReg + I];
3613	RegsToPass.push_back(std::make_pair(ArgReg, LoadVal));
3614	}
3615
3616	// Return if the struct has been fully copied.
3617	if (ByValSizeInBytes == OffsetInBytes)
3618	return;
3619
3620	// Copy the remainder of the byval argument with sub-word loads and shifts.
3621	if (LeftoverBytes) {
3622	SDValue Val;
3623
3624	for (unsigned LoadSizeInBytes = RegSizeInBytes / 2, TotalBytesLoaded = 0;
3625	OffsetInBytes < ByValSizeInBytes; LoadSizeInBytes /= 2) {
3626	unsigned RemainingSizeInBytes = ByValSizeInBytes - OffsetInBytes;
3627
3628	if (RemainingSizeInBytes < LoadSizeInBytes)
3629	continue;
3630
3631	// Load subword.
3632	SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
3633	DAG.getConstant(OffsetInBytes, PtrTy));
3634	SDValue LoadVal = DAG.getExtLoad(
3635	ISD::ZEXTLOAD, DL, RegTy, Chain, LoadPtr, MachinePointerInfo(),
3636	MVT::getIntegerVT(LoadSizeInBytes * 8), false, false, false,
3637	Alignment);
3638	MemOpChains.push_back(LoadVal.getValue(1));
3639
3640	// Shift the loaded value.
3641	unsigned Shamt;
3642
3643	if (isLittle)
3644	Shamt = TotalBytesLoaded * 8;
3645	else
3646	Shamt = (RegSizeInBytes - (TotalBytesLoaded + LoadSizeInBytes)) * 8;
3647
3648	SDValue Shift = DAG.getNode(ISD::SHL, DL, RegTy, LoadVal,
3649	DAG.getConstant(Shamt, MVT::i32));
3650
3651	if (Val.getNode())
3652	Val = DAG.getNode(ISD::OR, DL, RegTy, Val, Shift);
3653	else
3654	Val = Shift;
3655
3656	OffsetInBytes += LoadSizeInBytes;
3657	TotalBytesLoaded += LoadSizeInBytes;
3658	Alignment = std::min(Alignment, LoadSizeInBytes);
3659	}
3660
3661	unsigned ArgReg = ArgRegs[FirstReg + I];
3662	RegsToPass.push_back(std::make_pair(ArgReg, Val));
3663	return;
3664	}
3665	}
3666
3667	// Copy remainder of byval arg to it with memcpy.
3668	unsigned MemCpySize = ByValSizeInBytes - OffsetInBytes;
3669	SDValue Src = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
3670	DAG.getConstant(OffsetInBytes, PtrTy));
3671	SDValue Dst = DAG.getNode(ISD::ADD, DL, PtrTy, StackPtr,
3672	DAG.getIntPtrConstant(VA.getLocMemOffset()));
3673	Chain = DAG.getMemcpy(Chain, DL, Dst, Src, DAG.getConstant(MemCpySize, PtrTy),
3674	Alignment, /isVolatile=/false, /AlwaysInline=/false,
3675	MachinePointerInfo(), MachinePointerInfo());
3676	MemOpChains.push_back(Chain);
3677	}
3678
3679	void MipsTargetLowering::writeVarArgRegs(std::vector<SDValue> &OutChains,
3680	SDValue Chain, SDLoc DL,
3681	SelectionDAG &DAG,
3682	CCState &State) const {
3683	const ArrayRef<MCPhysReg> ArgRegs =
3684	static_cast<const MipsTargetMachine &>(DAG.getTarget())
3685	.getABI()
3686	.GetVarArgRegs();
3687	unsigned Idx = State.getFirstUnallocated(ArgRegs.data(), ArgRegs.size());
3688	unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes();
3689	MVT RegTy = MVT::getIntegerVT(RegSizeInBytes * 8);
3690	const TargetRegisterClass *RC = getRegClassFor(RegTy);
3691	MachineFunction &MF = DAG.getMachineFunction();
3692	MachineFrameInfo *MFI = MF.getFrameInfo();
3693	MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
3694
3695	// Offset of the first variable argument from stack pointer.
3696	int VaArgOffset;
3697
3698	if (ArgRegs.size() == Idx)
3699	VaArgOffset =
3700	RoundUpToAlignment(State.getNextStackOffset(), RegSizeInBytes);
3701	else {
3702	const MipsABIInfo &ABI =
3703	static_cast<const MipsTargetMachine &>(MF.getTarget()).getABI();
3704	VaArgOffset =
3705	(int)ABI.GetCalleeAllocdArgSizeInBytes(State.getCallingConv()) -
3706	(int)(RegSizeInBytes * (ArgRegs.size() - Idx));
3707	}
3708
3709	// Record the frame index of the first variable argument
3710	// which is a value necessary to VASTART.
3711	int FI = MFI->CreateFixedObject(RegSizeInBytes, VaArgOffset, true);
3712	MipsFI->setVarArgsFrameIndex(FI);
3713
3714	// Copy the integer registers that have not been used for argument passing
3715	// to the argument register save area. For O32, the save area is allocated
3716	// in the caller's stack frame, while for N32/64, it is allocated in the
3717	// callee's stack frame.
3718	for (unsigned I = Idx; I < ArgRegs.size();
3719	++I, VaArgOffset += RegSizeInBytes) {
3720	unsigned Reg = addLiveIn(MF, ArgRegs[I], RC);
3721	SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegTy);
3722	FI = MFI->CreateFixedObject(RegSizeInBytes, VaArgOffset, true);
3723	SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy());
3724	SDValue Store = DAG.getStore(Chain, DL, ArgValue, PtrOff,
3725	MachinePointerInfo(), false, false, 0);
3726	cast<StoreSDNode>(Store.getNode())->getMemOperand()->setValue(
3727	(Value *)nullptr);
3728	OutChains.push_back(Store);
3729	}
3730	}
3731
3732	void MipsTargetLowering::HandleByVal(CCState *State, unsigned &Size,
3733	unsigned Align) const {
3734	MachineFunction &MF = State->getMachineFunction();
3735	const TargetFrameLowering *TFL = MF.getSubtarget().getFrameLowering();
3736
3737	assert(Size && "Byval argument's size shouldn't be 0.")((Size && "Byval argument's size shouldn't be 0.") ? static_cast <void> (0) : __assert_fail ("Size && \"Byval argument's size shouldn't be 0.\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn227492/lib/Target/Mips/MipsISelLowering.cpp" , 3737, __PRETTY_FUNCTION__));
3738
3739	Align = std::min(Align, TFL->getStackAlignment());
3740
3741	unsigned FirstReg = 0;
3742	unsigned NumRegs = 0;
3743
3744	if (State->getCallingConv() != CallingConv::Fast) {
3745	unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes();
3746	const ArrayRef<MCPhysReg> IntArgRegs =
3747	static_cast<const MipsTargetMachine &>(MF.getTarget())
3748	.getABI()
3749	.GetByValArgRegs();
3750	// FIXME: The O32 case actually describes no shadow registers.
3751	const MCPhysReg *ShadowRegs =
3752	Subtarget.isABI_O32() ? IntArgRegs.data() : Mips64DPRegs;
3753
3754	// We used to check the size as well but we can't do that anymore since
3755	// CCState::HandleByVal() rounds up the size after calling this function.
3756	assert(!(Align % RegSizeInBytes) &&((!(Align % RegSizeInBytes) && "Byval argument's alignment should be a multiple of" "RegSizeInBytes.") ? static_cast<void> (0) : __assert_fail ("!(Align % RegSizeInBytes) && \"Byval argument's alignment should be a multiple of\" \"RegSizeInBytes.\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn227492/lib/Target/Mips/MipsISelLowering.cpp" , 3758, __PRETTY_FUNCTION__))
3757	"Byval argument's alignment should be a multiple of"((!(Align % RegSizeInBytes) && "Byval argument's alignment should be a multiple of" "RegSizeInBytes.") ? static_cast<void> (0) : __assert_fail ("!(Align % RegSizeInBytes) && \"Byval argument's alignment should be a multiple of\" \"RegSizeInBytes.\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn227492/lib/Target/Mips/MipsISelLowering.cpp" , 3758, __PRETTY_FUNCTION__))
3758	"RegSizeInBytes.")((!(Align % RegSizeInBytes) && "Byval argument's alignment should be a multiple of" "RegSizeInBytes.") ? static_cast<void> (0) : __assert_fail ("!(Align % RegSizeInBytes) && \"Byval argument's alignment should be a multiple of\" \"RegSizeInBytes.\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn227492/lib/Target/Mips/MipsISelLowering.cpp" , 3758, __PRETTY_FUNCTION__));
3759
3760	FirstReg = State->getFirstUnallocated(IntArgRegs.data(), IntArgRegs.size());
3761
3762	// If Align > RegSizeInBytes, the first arg register must be even.
3763	// FIXME: This condition happens to do the right thing but it's not the
3764	// right way to test it. We want to check that the stack frame offset
3765	// of the register is aligned.
3766	if ((Align > RegSizeInBytes) && (FirstReg % 2)) {
3767	State->AllocateReg(IntArgRegs[FirstReg], ShadowRegs[FirstReg]);
3768	++FirstReg;
3769	}
3770
3771	// Mark the registers allocated.
3772	Size = RoundUpToAlignment(Size, RegSizeInBytes);
3773	for (unsigned I = FirstReg; Size > 0 && (I < IntArgRegs.size());
3774	Size -= RegSizeInBytes, ++I, ++NumRegs)
3775	State->AllocateReg(IntArgRegs[I], ShadowRegs[I]);
3776	}
3777
3778	State->addInRegsParamInfo(FirstReg, FirstReg + NumRegs);
3779	}
3780
3781	MachineBasicBlock *
3782	MipsTargetLowering::emitPseudoSELECT(MachineInstr MI, MachineBasicBlock BB,
3783	bool isFPCmp, unsigned Opc) const {
3784	assert(!(Subtarget.hasMips4() \|\| Subtarget.hasMips32()) &&((!(Subtarget.hasMips4() \|\| Subtarget.hasMips32()) && "Subtarget already supports SELECT nodes with the use of" "conditional-move instructions." ) ? static_cast<void> (0) : __assert_fail ("!(Subtarget.hasMips4() \|\| Subtarget.hasMips32()) && \"Subtarget already supports SELECT nodes with the use of\" \"conditional-move instructions.\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn227492/lib/Target/Mips/MipsISelLowering.cpp" , 3786, __PRETTY_FUNCTION__))
3785	"Subtarget already supports SELECT nodes with the use of"((!(Subtarget.hasMips4() \|\| Subtarget.hasMips32()) && "Subtarget already supports SELECT nodes with the use of" "conditional-move instructions." ) ? static_cast<void> (0) : __assert_fail ("!(Subtarget.hasMips4() \|\| Subtarget.hasMips32()) && \"Subtarget already supports SELECT nodes with the use of\" \"conditional-move instructions.\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn227492/lib/Target/Mips/MipsISelLowering.cpp" , 3786, __PRETTY_FUNCTION__))
3786	"conditional-move instructions.")((!(Subtarget.hasMips4() \|\| Subtarget.hasMips32()) && "Subtarget already supports SELECT nodes with the use of" "conditional-move instructions." ) ? static_cast<void> (0) : __assert_fail ("!(Subtarget.hasMips4() \|\| Subtarget.hasMips32()) && \"Subtarget already supports SELECT nodes with the use of\" \"conditional-move instructions.\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn227492/lib/Target/Mips/MipsISelLowering.cpp" , 3786, __PRETTY_FUNCTION__));
3787
3788	const TargetInstrInfo *TII =
3789	getTargetMachine().getSubtargetImpl()->getInstrInfo();
3790	DebugLoc DL = MI->getDebugLoc();
3791
3792	// To "insert" a SELECT instruction, we actually have to insert the
3793	// diamond control-flow pattern. The incoming instruction knows the
3794	// destination vreg to set, the condition code register to branch on, the
3795	// true/false values to select between, and a branch opcode to use.
3796	const BasicBlock *LLVM_BB = BB->getBasicBlock();
3797	MachineFunction::iterator It = BB;
3798	++It;
3799
3800	// thisMBB:
3801	// ...
3802	// TrueVal = ...
3803	// setcc r1, r2, r3
3804	// bNE r1, r0, copy1MBB
3805	// fallthrough --> copy0MBB
3806	MachineBasicBlock *thisMBB = BB;
3807	MachineFunction *F = BB->getParent();
3808	MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
3809	MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
3810	F->insert(It, copy0MBB);
3811	F->insert(It, sinkMBB);
3812
3813	// Transfer the remainder of BB and its successor edges to sinkMBB.
3814	sinkMBB->splice(sinkMBB->begin(), BB,
3815	std::next(MachineBasicBlock::iterator(MI)), BB->end());
3816	sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
3817
3818	// Next, add the true and fallthrough blocks as its successors.
3819	BB->addSuccessor(copy0MBB);
3820	BB->addSuccessor(sinkMBB);
3821
3822	if (isFPCmp) {
3823	// bc1[tf] cc, sinkMBB
3824	BuildMI(BB, DL, TII->get(Opc))
3825	.addReg(MI->getOperand(1).getReg())
3826	.addMBB(sinkMBB);
3827	} else {
3828	// bne rs, $0, sinkMBB
3829	BuildMI(BB, DL, TII->get(Opc))
3830	.addReg(MI->getOperand(1).getReg())
3831	.addReg(Mips::ZERO)
3832	.addMBB(sinkMBB);
3833	}
3834
3835	// copy0MBB:
3836	// %FalseValue = ...
3837	// # fallthrough to sinkMBB
3838	BB = copy0MBB;
3839
3840	// Update machine-CFG edges
3841	BB->addSuccessor(sinkMBB);
3842
3843	// sinkMBB:
3844	// %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
3845	// ...
3846	BB = sinkMBB;
3847
3848	BuildMI(*BB, BB->begin(), DL,
3849	TII->get(Mips::PHI), MI->getOperand(0).getReg())
3850	.addReg(MI->getOperand(2).getReg()).addMBB(thisMBB)
3851	.addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB);
3852
3853	MI->eraseFromParent(); // The pseudo instruction is gone now.
3854
3855	return BB;
3856	}
3857
3858	// FIXME? Maybe this could be a TableGen attribute on some registers and
3859	// this table could be generated automatically from RegInfo.
3860	unsigned MipsTargetLowering::getRegisterByName(const char* RegName,
3861	EVT VT) const {
3862	// Named registers is expected to be fairly rare. For now, just support $28
3863	// since the linux kernel uses it.
3864	if (Subtarget.isGP64bit()) {
3865	unsigned Reg = StringSwitch<unsigned>(RegName)
3866	.Case("$28", Mips::GP_64)
3867	.Default(0);
3868	if (Reg)
3869	return Reg;
3870	} else {
3871	unsigned Reg = StringSwitch<unsigned>(RegName)
3872	.Case("$28", Mips::GP)
3873	.Default(0);
3874	if (Reg)
3875	return Reg;
3876	}
3877	report_fatal_error("Invalid register name global variable");
3878	}