/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MipsISelLowering.cpp

Bug Summary

File:	lib/Target/Mips/MipsISelLowering.cpp
Location:	line 1600, column 3
Description:	Value stored to 'BB' is never read

Annotated Source Code

1	//===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
2	//
3	// The LLVM Compiler Infrastructure
4	//
5	// This file is distributed under the University of Illinois Open Source
6	// License. See LICENSE.TXT for details.
7	//
8	//===----------------------------------------------------------------------===//
9	//
10	// This file defines the interfaces that Mips uses to lower LLVM code into a
11	// selection DAG.
12	//
13	//===----------------------------------------------------------------------===//
14	#include "MipsISelLowering.h"
15	#include "InstPrinter/MipsInstPrinter.h"
16	#include "MCTargetDesc/MipsBaseInfo.h"
17	#include "MipsCCState.h"
18	#include "MipsMachineFunction.h"
19	#include "MipsSubtarget.h"
20	#include "MipsTargetMachine.h"
21	#include "MipsTargetObjectFile.h"
22	#include "llvm/ADT/Statistic.h"
23	#include "llvm/ADT/StringSwitch.h"
24	#include "llvm/CodeGen/CallingConvLower.h"
25	#include "llvm/CodeGen/MachineFrameInfo.h"
26	#include "llvm/CodeGen/MachineFunction.h"
27	#include "llvm/CodeGen/MachineInstrBuilder.h"
28	#include "llvm/CodeGen/MachineJumpTableInfo.h"
29	#include "llvm/CodeGen/MachineRegisterInfo.h"
30	#include "llvm/CodeGen/FunctionLoweringInfo.h"
31	#include "llvm/CodeGen/SelectionDAGISel.h"
32	#include "llvm/CodeGen/ValueTypes.h"
33	#include "llvm/IR/CallingConv.h"
34	#include "llvm/IR/DerivedTypes.h"
35	#include "llvm/IR/GlobalVariable.h"
36	#include "llvm/Support/CommandLine.h"
37	#include "llvm/Support/Debug.h"
38	#include "llvm/Support/ErrorHandling.h"
39	#include "llvm/Support/raw_ostream.h"
40	#include <cctype>
41
42	using namespace llvm;
43
44	#define DEBUG_TYPE"mips-lower" "mips-lower"
45
46	STATISTIC(NumTailCalls, "Number of tail calls")static llvm::Statistic NumTailCalls = { "mips-lower", "Number of tail calls" , 0, 0 };
47
48	static cl::opt<bool>
49	LargeGOT("mxgot", cl::Hidden,
50	cl::desc("MIPS: Enable GOT larger than 64k."), cl::init(false));
51
52	static cl::opt<bool>
53	NoZeroDivCheck("mno-check-zero-division", cl::Hidden,
54	cl::desc("MIPS: Don't trap on integer division by zero."),
55	cl::init(false));
56
57	static const MCPhysReg Mips64DPRegs[8] = {
58	Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64,
59	Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64
60	};
61
62	// If I is a shifted mask, set the size (Size) and the first bit of the
63	// mask (Pos), and return true.
64	// For example, if I is 0x003ff800, (Pos, Size) = (11, 11).
65	static bool isShiftedMask(uint64_t I, uint64_t &Pos, uint64_t &Size) {
66	if (!isShiftedMask_64(I))
67	return false;
68
69	Size = countPopulation(I);
70	Pos = countTrailingZeros(I);
71	return true;
72	}
73
74	SDValue MipsTargetLowering::getGlobalReg(SelectionDAG &DAG, EVT Ty) const {
75	MipsFunctionInfo *FI = DAG.getMachineFunction().getInfo<MipsFunctionInfo>();
76	return DAG.getRegister(FI->getGlobalBaseReg(), Ty);
77	}
78
79	SDValue MipsTargetLowering::getTargetNode(GlobalAddressSDNode *N, EVT Ty,
80	SelectionDAG &DAG,
81	unsigned Flag) const {
82	return DAG.getTargetGlobalAddress(N->getGlobal(), SDLoc(N), Ty, 0, Flag);
83	}
84
85	SDValue MipsTargetLowering::getTargetNode(ExternalSymbolSDNode *N, EVT Ty,
86	SelectionDAG &DAG,
87	unsigned Flag) const {
88	return DAG.getTargetExternalSymbol(N->getSymbol(), Ty, Flag);
89	}
90
91	SDValue MipsTargetLowering::getTargetNode(BlockAddressSDNode *N, EVT Ty,
92	SelectionDAG &DAG,
93	unsigned Flag) const {
94	return DAG.getTargetBlockAddress(N->getBlockAddress(), Ty, 0, Flag);
95	}
96
97	SDValue MipsTargetLowering::getTargetNode(JumpTableSDNode *N, EVT Ty,
98	SelectionDAG &DAG,
99	unsigned Flag) const {
100	return DAG.getTargetJumpTable(N->getIndex(), Ty, Flag);
101	}
102
103	SDValue MipsTargetLowering::getTargetNode(ConstantPoolSDNode *N, EVT Ty,
104	SelectionDAG &DAG,
105	unsigned Flag) const {
106	return DAG.getTargetConstantPool(N->getConstVal(), Ty, N->getAlignment(),
107	N->getOffset(), Flag);
108	}
109
110	const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
111	switch ((MipsISD::NodeType)Opcode) {
112	case MipsISD::FIRST_NUMBER: break;
113	case MipsISD::JmpLink: return "MipsISD::JmpLink";
114	case MipsISD::TailCall: return "MipsISD::TailCall";
115	case MipsISD::Hi: return "MipsISD::Hi";
116	case MipsISD::Lo: return "MipsISD::Lo";
117	case MipsISD::GPRel: return "MipsISD::GPRel";
118	case MipsISD::ThreadPointer: return "MipsISD::ThreadPointer";
119	case MipsISD::Ret: return "MipsISD::Ret";
120	case MipsISD::ERet: return "MipsISD::ERet";
121	case MipsISD::EH_RETURN: return "MipsISD::EH_RETURN";
122	case MipsISD::FPBrcond: return "MipsISD::FPBrcond";
123	case MipsISD::FPCmp: return "MipsISD::FPCmp";
124	case MipsISD::CMovFP_T: return "MipsISD::CMovFP_T";
125	case MipsISD::CMovFP_F: return "MipsISD::CMovFP_F";
126	case MipsISD::TruncIntFP: return "MipsISD::TruncIntFP";
127	case MipsISD::MFHI: return "MipsISD::MFHI";
128	case MipsISD::MFLO: return "MipsISD::MFLO";
129	case MipsISD::MTLOHI: return "MipsISD::MTLOHI";
130	case MipsISD::Mult: return "MipsISD::Mult";
131	case MipsISD::Multu: return "MipsISD::Multu";
132	case MipsISD::MAdd: return "MipsISD::MAdd";
133	case MipsISD::MAddu: return "MipsISD::MAddu";
134	case MipsISD::MSub: return "MipsISD::MSub";
135	case MipsISD::MSubu: return "MipsISD::MSubu";
136	case MipsISD::DivRem: return "MipsISD::DivRem";
137	case MipsISD::DivRemU: return "MipsISD::DivRemU";
138	case MipsISD::DivRem16: return "MipsISD::DivRem16";
139	case MipsISD::DivRemU16: return "MipsISD::DivRemU16";
140	case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64";
141	case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64";
142	case MipsISD::Wrapper: return "MipsISD::Wrapper";
143	case MipsISD::DynAlloc: return "MipsISD::DynAlloc";
144	case MipsISD::Sync: return "MipsISD::Sync";
145	case MipsISD::Ext: return "MipsISD::Ext";
146	case MipsISD::Ins: return "MipsISD::Ins";
147	case MipsISD::LWL: return "MipsISD::LWL";
148	case MipsISD::LWR: return "MipsISD::LWR";
149	case MipsISD::SWL: return "MipsISD::SWL";
150	case MipsISD::SWR: return "MipsISD::SWR";
151	case MipsISD::LDL: return "MipsISD::LDL";
152	case MipsISD::LDR: return "MipsISD::LDR";
153	case MipsISD::SDL: return "MipsISD::SDL";
154	case MipsISD::SDR: return "MipsISD::SDR";
155	case MipsISD::EXTP: return "MipsISD::EXTP";
156	case MipsISD::EXTPDP: return "MipsISD::EXTPDP";
157	case MipsISD::EXTR_S_H: return "MipsISD::EXTR_S_H";
158	case MipsISD::EXTR_W: return "MipsISD::EXTR_W";
159	case MipsISD::EXTR_R_W: return "MipsISD::EXTR_R_W";
160	case MipsISD::EXTR_RS_W: return "MipsISD::EXTR_RS_W";
161	case MipsISD::SHILO: return "MipsISD::SHILO";
162	case MipsISD::MTHLIP: return "MipsISD::MTHLIP";
163	case MipsISD::MULSAQ_S_W_PH: return "MipsISD::MULSAQ_S_W_PH";
164	case MipsISD::MAQ_S_W_PHL: return "MipsISD::MAQ_S_W_PHL";
165	case MipsISD::MAQ_S_W_PHR: return "MipsISD::MAQ_S_W_PHR";
166	case MipsISD::MAQ_SA_W_PHL: return "MipsISD::MAQ_SA_W_PHL";
167	case MipsISD::MAQ_SA_W_PHR: return "MipsISD::MAQ_SA_W_PHR";
168	case MipsISD::DPAU_H_QBL: return "MipsISD::DPAU_H_QBL";
169	case MipsISD::DPAU_H_QBR: return "MipsISD::DPAU_H_QBR";
170	case MipsISD::DPSU_H_QBL: return "MipsISD::DPSU_H_QBL";
171	case MipsISD::DPSU_H_QBR: return "MipsISD::DPSU_H_QBR";
172	case MipsISD::DPAQ_S_W_PH: return "MipsISD::DPAQ_S_W_PH";
173	case MipsISD::DPSQ_S_W_PH: return "MipsISD::DPSQ_S_W_PH";
174	case MipsISD::DPAQ_SA_L_W: return "MipsISD::DPAQ_SA_L_W";
175	case MipsISD::DPSQ_SA_L_W: return "MipsISD::DPSQ_SA_L_W";
176	case MipsISD::DPA_W_PH: return "MipsISD::DPA_W_PH";
177	case MipsISD::DPS_W_PH: return "MipsISD::DPS_W_PH";
178	case MipsISD::DPAQX_S_W_PH: return "MipsISD::DPAQX_S_W_PH";
179	case MipsISD::DPAQX_SA_W_PH: return "MipsISD::DPAQX_SA_W_PH";
180	case MipsISD::DPAX_W_PH: return "MipsISD::DPAX_W_PH";
181	case MipsISD::DPSX_W_PH: return "MipsISD::DPSX_W_PH";
182	case MipsISD::DPSQX_S_W_PH: return "MipsISD::DPSQX_S_W_PH";
183	case MipsISD::DPSQX_SA_W_PH: return "MipsISD::DPSQX_SA_W_PH";
184	case MipsISD::MULSA_W_PH: return "MipsISD::MULSA_W_PH";
185	case MipsISD::MULT: return "MipsISD::MULT";
186	case MipsISD::MULTU: return "MipsISD::MULTU";
187	case MipsISD::MADD_DSP: return "MipsISD::MADD_DSP";
188	case MipsISD::MADDU_DSP: return "MipsISD::MADDU_DSP";
189	case MipsISD::MSUB_DSP: return "MipsISD::MSUB_DSP";
190	case MipsISD::MSUBU_DSP: return "MipsISD::MSUBU_DSP";
191	case MipsISD::SHLL_DSP: return "MipsISD::SHLL_DSP";
192	case MipsISD::SHRA_DSP: return "MipsISD::SHRA_DSP";
193	case MipsISD::SHRL_DSP: return "MipsISD::SHRL_DSP";
194	case MipsISD::SETCC_DSP: return "MipsISD::SETCC_DSP";
195	case MipsISD::SELECT_CC_DSP: return "MipsISD::SELECT_CC_DSP";
196	case MipsISD::VALL_ZERO: return "MipsISD::VALL_ZERO";
197	case MipsISD::VANY_ZERO: return "MipsISD::VANY_ZERO";
198	case MipsISD::VALL_NONZERO: return "MipsISD::VALL_NONZERO";
199	case MipsISD::VANY_NONZERO: return "MipsISD::VANY_NONZERO";
200	case MipsISD::VCEQ: return "MipsISD::VCEQ";
201	case MipsISD::VCLE_S: return "MipsISD::VCLE_S";
202	case MipsISD::VCLE_U: return "MipsISD::VCLE_U";
203	case MipsISD::VCLT_S: return "MipsISD::VCLT_S";
204	case MipsISD::VCLT_U: return "MipsISD::VCLT_U";
205	case MipsISD::VSMAX: return "MipsISD::VSMAX";
206	case MipsISD::VSMIN: return "MipsISD::VSMIN";
207	case MipsISD::VUMAX: return "MipsISD::VUMAX";
208	case MipsISD::VUMIN: return "MipsISD::VUMIN";
209	case MipsISD::VEXTRACT_SEXT_ELT: return "MipsISD::VEXTRACT_SEXT_ELT";
210	case MipsISD::VEXTRACT_ZEXT_ELT: return "MipsISD::VEXTRACT_ZEXT_ELT";
211	case MipsISD::VNOR: return "MipsISD::VNOR";
212	case MipsISD::VSHF: return "MipsISD::VSHF";
213	case MipsISD::SHF: return "MipsISD::SHF";
214	case MipsISD::ILVEV: return "MipsISD::ILVEV";
215	case MipsISD::ILVOD: return "MipsISD::ILVOD";
216	case MipsISD::ILVL: return "MipsISD::ILVL";
217	case MipsISD::ILVR: return "MipsISD::ILVR";
218	case MipsISD::PCKEV: return "MipsISD::PCKEV";
219	case MipsISD::PCKOD: return "MipsISD::PCKOD";
220	case MipsISD::INSVE: return "MipsISD::INSVE";
221	}
222	return nullptr;
223	}
224
225	MipsTargetLowering::MipsTargetLowering(const MipsTargetMachine &TM,
226	const MipsSubtarget &STI)
227	: TargetLowering(TM), Subtarget(STI), ABI(TM.getABI()) {
228	// Mips does not have i1 type, so use i32 for
229	// setcc operations results (slt, sgt, ...).
230	setBooleanContents(ZeroOrOneBooleanContent);
231	setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
232	// The cmp.cond.fmt instruction in MIPS32r6/MIPS64r6 uses 0 and -1 like MSA
233	// does. Integer booleans still use 0 and 1.
234	if (Subtarget.hasMips32r6())
235	setBooleanContents(ZeroOrOneBooleanContent,
236	ZeroOrNegativeOneBooleanContent);
237
238	// Load extented operations for i1 types must be promoted
239	for (MVT VT : MVT::integer_valuetypes()) {
240	setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
241	setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
242	setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
243	}
244
245	// MIPS doesn't have extending float->double load/store. Set LoadExtAction
246	// for f32, f16
247	for (MVT VT : MVT::fp_valuetypes()) {
248	setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
249	setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand);
250	}
251
252	// Set LoadExtAction for f16 vectors to Expand
253	for (MVT VT : MVT::fp_vector_valuetypes()) {
254	MVT F16VT = MVT::getVectorVT(MVT::f16, VT.getVectorNumElements());
255	if (F16VT.isValid())
256	setLoadExtAction(ISD::EXTLOAD, VT, F16VT, Expand);
257	}
258
259	setTruncStoreAction(MVT::f32, MVT::f16, Expand);
260	setTruncStoreAction(MVT::f64, MVT::f16, Expand);
261
262	setTruncStoreAction(MVT::f64, MVT::f32, Expand);
263
264	// Used by legalize types to correctly generate the setcc result.
265	// Without this, every float setcc comes with a AND/OR with the result,
266	// we don't want this, since the fpcmp result goes to a flag register,
267	// which is used implicitly by brcond and select operations.
268	AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
269
270	// Mips Custom Operations
271	setOperationAction(ISD::BR_JT, MVT::Other, Custom);
272	setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
273	setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
274	setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
275	setOperationAction(ISD::JumpTable, MVT::i32, Custom);
276	setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
277	setOperationAction(ISD::SELECT, MVT::f32, Custom);
278	setOperationAction(ISD::SELECT, MVT::f64, Custom);
279	setOperationAction(ISD::SELECT, MVT::i32, Custom);
280	setOperationAction(ISD::SETCC, MVT::f32, Custom);
281	setOperationAction(ISD::SETCC, MVT::f64, Custom);
282	setOperationAction(ISD::BRCOND, MVT::Other, Custom);
283	setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
284	setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
285	setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
286
287	if (Subtarget.isGP64bit()) {
288	setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
289	setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
290	setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
291	setOperationAction(ISD::JumpTable, MVT::i64, Custom);
292	setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
293	setOperationAction(ISD::SELECT, MVT::i64, Custom);
294	setOperationAction(ISD::LOAD, MVT::i64, Custom);
295	setOperationAction(ISD::STORE, MVT::i64, Custom);
296	setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
297	setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
298	setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
299	setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
300	}
301
302	if (!Subtarget.isGP64bit()) {
303	setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
304	setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
305	setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
306	}
307
308	setOperationAction(ISD::ADD, MVT::i32, Custom);
309	if (Subtarget.isGP64bit())
310	setOperationAction(ISD::ADD, MVT::i64, Custom);
311
312	setOperationAction(ISD::SDIV, MVT::i32, Expand);
313	setOperationAction(ISD::SREM, MVT::i32, Expand);
314	setOperationAction(ISD::UDIV, MVT::i32, Expand);
315	setOperationAction(ISD::UREM, MVT::i32, Expand);
316	setOperationAction(ISD::SDIV, MVT::i64, Expand);
317	setOperationAction(ISD::SREM, MVT::i64, Expand);
318	setOperationAction(ISD::UDIV, MVT::i64, Expand);
319	setOperationAction(ISD::UREM, MVT::i64, Expand);
320
321	// Operations not directly supported by Mips.
322	setOperationAction(ISD::BR_CC, MVT::f32, Expand);
323	setOperationAction(ISD::BR_CC, MVT::f64, Expand);
324	setOperationAction(ISD::BR_CC, MVT::i32, Expand);
325	setOperationAction(ISD::BR_CC, MVT::i64, Expand);
326	setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
327	setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
328	setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
329	setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
330	setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
331	setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
332	setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
333	setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
334	setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
335	if (Subtarget.hasCnMips()) {
336	setOperationAction(ISD::CTPOP, MVT::i32, Legal);
337	setOperationAction(ISD::CTPOP, MVT::i64, Legal);
338	} else {
339	setOperationAction(ISD::CTPOP, MVT::i32, Expand);
340	setOperationAction(ISD::CTPOP, MVT::i64, Expand);
341	}
342	setOperationAction(ISD::CTTZ, MVT::i32, Expand);
343	setOperationAction(ISD::CTTZ, MVT::i64, Expand);
344	setOperationAction(ISD::ROTL, MVT::i32, Expand);
345	setOperationAction(ISD::ROTL, MVT::i64, Expand);
346	setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
347	setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
348
349	if (!Subtarget.hasMips32r2())
350	setOperationAction(ISD::ROTR, MVT::i32, Expand);
351
352	if (!Subtarget.hasMips64r2())
353	setOperationAction(ISD::ROTR, MVT::i64, Expand);
354
355	setOperationAction(ISD::FSIN, MVT::f32, Expand);
356	setOperationAction(ISD::FSIN, MVT::f64, Expand);
357	setOperationAction(ISD::FCOS, MVT::f32, Expand);
358	setOperationAction(ISD::FCOS, MVT::f64, Expand);
359	setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
360	setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
361	setOperationAction(ISD::FPOWI, MVT::f32, Expand);
362	setOperationAction(ISD::FPOW, MVT::f32, Expand);
363	setOperationAction(ISD::FPOW, MVT::f64, Expand);
364	setOperationAction(ISD::FLOG, MVT::f32, Expand);
365	setOperationAction(ISD::FLOG2, MVT::f32, Expand);
366	setOperationAction(ISD::FLOG10, MVT::f32, Expand);
367	setOperationAction(ISD::FEXP, MVT::f32, Expand);
368	setOperationAction(ISD::FMA, MVT::f32, Expand);
369	setOperationAction(ISD::FMA, MVT::f64, Expand);
370	setOperationAction(ISD::FREM, MVT::f32, Expand);
371	setOperationAction(ISD::FREM, MVT::f64, Expand);
372
373	// Lower f16 conversion operations into library calls
374	setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
375	setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
376	setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
377	setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
378
379	setOperationAction(ISD::EH_RETURN, MVT::Other, Custom);
380
381	setOperationAction(ISD::VASTART, MVT::Other, Custom);
382	setOperationAction(ISD::VAARG, MVT::Other, Custom);
383	setOperationAction(ISD::VACOPY, MVT::Other, Expand);
384	setOperationAction(ISD::VAEND, MVT::Other, Expand);
385
386	// Use the default for now
387	setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
388	setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
389
390	if (!Subtarget.isGP64bit()) {
391	setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
392	setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
393	}
394
395
396	if (!Subtarget.hasMips32r2()) {
397	setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
398	setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
399	}
400
401	// MIPS16 lacks MIPS32's clz and clo instructions.
402	if (!Subtarget.hasMips32() \|\| Subtarget.inMips16Mode())
403	setOperationAction(ISD::CTLZ, MVT::i32, Expand);
404	if (!Subtarget.hasMips64())
405	setOperationAction(ISD::CTLZ, MVT::i64, Expand);
406
407	if (!Subtarget.hasMips32r2())
408	setOperationAction(ISD::BSWAP, MVT::i32, Expand);
409	if (!Subtarget.hasMips64r2())
410	setOperationAction(ISD::BSWAP, MVT::i64, Expand);
411
412	if (Subtarget.isGP64bit()) {
413	setLoadExtAction(ISD::SEXTLOAD, MVT::i64, MVT::i32, Custom);
414	setLoadExtAction(ISD::ZEXTLOAD, MVT::i64, MVT::i32, Custom);
415	setLoadExtAction(ISD::EXTLOAD, MVT::i64, MVT::i32, Custom);
416	setTruncStoreAction(MVT::i64, MVT::i32, Custom);
417	}
418
419	setOperationAction(ISD::TRAP, MVT::Other, Legal);
420
421	setTargetDAGCombine(ISD::SDIVREM);
422	setTargetDAGCombine(ISD::UDIVREM);
423	setTargetDAGCombine(ISD::SELECT);
424	setTargetDAGCombine(ISD::AND);
425	setTargetDAGCombine(ISD::OR);
426	setTargetDAGCombine(ISD::ADD);
427	setTargetDAGCombine(ISD::AssertZext);
428
429	setMinFunctionAlignment(Subtarget.isGP64bit() ? 3 : 2);
430
431	// The arguments on the stack are defined in terms of 4-byte slots on O32
432	// and 8-byte slots on N32/N64.
433	setMinStackArgumentAlignment((ABI.IsN32() \|\| ABI.IsN64()) ? 8 : 4);
434
435	setStackPointerRegisterToSaveRestore(ABI.IsN64() ? Mips::SP_64 : Mips::SP);
436
437	MaxStoresPerMemcpy = 16;
438
439	isMicroMips = Subtarget.inMicroMipsMode();
440	}
441
442	const MipsTargetLowering *MipsTargetLowering::create(const MipsTargetMachine &TM,
443	const MipsSubtarget &STI) {
444	if (STI.inMips16Mode())
445	return llvm::createMips16TargetLowering(TM, STI);
446
447	return llvm::createMipsSETargetLowering(TM, STI);
448	}
449
450	// Create a fast isel object.
451	FastISel *
452	MipsTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
453	const TargetLibraryInfo *libInfo) const {
454	if (!funcInfo.MF->getTarget().Options.EnableFastISel)
455	return TargetLowering::createFastISel(funcInfo, libInfo);
456	return Mips::createFastISel(funcInfo, libInfo);
457	}
458
459	EVT MipsTargetLowering::getSetCCResultType(const DataLayout &, LLVMContext &,
460	EVT VT) const {
461	if (!VT.isVector())
462	return MVT::i32;
463	return VT.changeVectorElementTypeToInteger();
464	}
465
466	static SDValue performDivRemCombine(SDNode *N, SelectionDAG &DAG,
467	TargetLowering::DAGCombinerInfo &DCI,
468	const MipsSubtarget &Subtarget) {
469	if (DCI.isBeforeLegalizeOps())
470	return SDValue();
471
472	EVT Ty = N->getValueType(0);
473	unsigned LO = (Ty == MVT::i32) ? Mips::LO0 : Mips::LO0_64;
474	unsigned HI = (Ty == MVT::i32) ? Mips::HI0 : Mips::HI0_64;
475	unsigned Opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem16 :
476	MipsISD::DivRemU16;
477	SDLoc DL(N);
478
479	SDValue DivRem = DAG.getNode(Opc, DL, MVT::Glue,
480	N->getOperand(0), N->getOperand(1));
481	SDValue InChain = DAG.getEntryNode();
482	SDValue InGlue = DivRem;
483
484	// insert MFLO
485	if (N->hasAnyUseOfValue(0)) {
486	SDValue CopyFromLo = DAG.getCopyFromReg(InChain, DL, LO, Ty,
487	InGlue);
488	DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo);
489	InChain = CopyFromLo.getValue(1);
490	InGlue = CopyFromLo.getValue(2);
491	}
492
493	// insert MFHI
494	if (N->hasAnyUseOfValue(1)) {
495	SDValue CopyFromHi = DAG.getCopyFromReg(InChain, DL,
496	HI, Ty, InGlue);
497	DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi);
498	}
499
500	return SDValue();
501	}
502
503	static Mips::CondCode condCodeToFCC(ISD::CondCode CC) {
504	switch (CC) {
505	default: llvm_unreachable("Unknown fp condition code!")::llvm::llvm_unreachable_internal("Unknown fp condition code!" , "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MipsISelLowering.cpp" , 505);
506	case ISD::SETEQ:
507	case ISD::SETOEQ: return Mips::FCOND_OEQ;
508	case ISD::SETUNE: return Mips::FCOND_UNE;
509	case ISD::SETLT:
510	case ISD::SETOLT: return Mips::FCOND_OLT;
511	case ISD::SETGT:
512	case ISD::SETOGT: return Mips::FCOND_OGT;
513	case ISD::SETLE:
514	case ISD::SETOLE: return Mips::FCOND_OLE;
515	case ISD::SETGE:
516	case ISD::SETOGE: return Mips::FCOND_OGE;
517	case ISD::SETULT: return Mips::FCOND_ULT;
518	case ISD::SETULE: return Mips::FCOND_ULE;
519	case ISD::SETUGT: return Mips::FCOND_UGT;
520	case ISD::SETUGE: return Mips::FCOND_UGE;
521	case ISD::SETUO: return Mips::FCOND_UN;
522	case ISD::SETO: return Mips::FCOND_OR;
523	case ISD::SETNE:
524	case ISD::SETONE: return Mips::FCOND_ONE;
525	case ISD::SETUEQ: return Mips::FCOND_UEQ;
526	}
527	}
528
529
530	/// This function returns true if the floating point conditional branches and
531	/// conditional moves which use condition code CC should be inverted.
532	static bool invertFPCondCodeUser(Mips::CondCode CC) {
533	if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
534	return false;
535
536	assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) &&(((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) && "Illegal Condition Code") ? static_cast<void> (0) : __assert_fail ("(CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) && \"Illegal Condition Code\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MipsISelLowering.cpp" , 537, __PRETTY_FUNCTION__))
537	"Illegal Condition Code")(((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) && "Illegal Condition Code") ? static_cast<void> (0) : __assert_fail ("(CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) && \"Illegal Condition Code\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MipsISelLowering.cpp" , 537, __PRETTY_FUNCTION__));
538
539	return true;
540	}
541
542	// Creates and returns an FPCmp node from a setcc node.
543	// Returns Op if setcc is not a floating point comparison.
544	static SDValue createFPCmp(SelectionDAG &DAG, const SDValue &Op) {
545	// must be a SETCC node
546	if (Op.getOpcode() != ISD::SETCC)
547	return Op;
548
549	SDValue LHS = Op.getOperand(0);
550
551	if (!LHS.getValueType().isFloatingPoint())
552	return Op;
553
554	SDValue RHS = Op.getOperand(1);
555	SDLoc DL(Op);
556
557	// Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of
558	// node if necessary.
559	ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
560
561	return DAG.getNode(MipsISD::FPCmp, DL, MVT::Glue, LHS, RHS,
562	DAG.getConstant(condCodeToFCC(CC), DL, MVT::i32));
563	}
564
565	// Creates and returns a CMovFPT/F node.
566	static SDValue createCMovFP(SelectionDAG &DAG, SDValue Cond, SDValue True,
567	SDValue False, SDLoc DL) {
568	ConstantSDNode *CC = cast<ConstantSDNode>(Cond.getOperand(2));
569	bool invert = invertFPCondCodeUser((Mips::CondCode)CC->getSExtValue());
570	SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32);
571
572	return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL,
573	True.getValueType(), True, FCC0, False, Cond);
574	}
575
576	static SDValue performSELECTCombine(SDNode *N, SelectionDAG &DAG,
577	TargetLowering::DAGCombinerInfo &DCI,
578	const MipsSubtarget &Subtarget) {
579	if (DCI.isBeforeLegalizeOps())
580	return SDValue();
581
582	SDValue SetCC = N->getOperand(0);
583
584	if ((SetCC.getOpcode() != ISD::SETCC) \|\|
585	!SetCC.getOperand(0).getValueType().isInteger())
586	return SDValue();
587
588	SDValue False = N->getOperand(2);
589	EVT FalseTy = False.getValueType();
590
591	if (!FalseTy.isInteger())
592	return SDValue();
593
594	ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(False);
595
596	// If the RHS (False) is 0, we swap the order of the operands
597	// of ISD::SELECT (obviously also inverting the condition) so that we can
598	// take advantage of conditional moves using the $0 register.
599	// Example:
600	// return (a != 0) ? x : 0;
601	// load $reg, x
602	// movz $reg, $0, a
603	if (!FalseC)
604	return SDValue();
605
606	const SDLoc DL(N);
607
608	if (!FalseC->getZExtValue()) {
609	ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get();
610	SDValue True = N->getOperand(1);
611
612	SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0),
613	SetCC.getOperand(1), ISD::getSetCCInverse(CC, true));
614
615	return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True);
616	}
617
618	// If both operands are integer constants there's a possibility that we
619	// can do some interesting optimizations.
620	SDValue True = N->getOperand(1);
621	ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(True);
622
623	if (!TrueC \|\| !True.getValueType().isInteger())
624	return SDValue();
625
626	// We'll also ignore MVT::i64 operands as this optimizations proves
627	// to be ineffective because of the required sign extensions as the result
628	// of a SETCC operator is always MVT::i32 for non-vector types.
629	if (True.getValueType() == MVT::i64)
630	return SDValue();
631
632	int64_t Diff = TrueC->getSExtValue() - FalseC->getSExtValue();
633
634	// 1) (a < x) ? y : y-1
635	// slti $reg1, a, x
636	// addiu $reg2, $reg1, y-1
637	if (Diff == 1)
638	return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, False);
639
640	// 2) (a < x) ? y-1 : y
641	// slti $reg1, a, x
642	// xor $reg1, $reg1, 1
643	// addiu $reg2, $reg1, y-1
644	if (Diff == -1) {
645	ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get();
646	SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0),
647	SetCC.getOperand(1), ISD::getSetCCInverse(CC, true));
648	return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, True);
649	}
650
651	// Couldn't optimize.
652	return SDValue();
653	}
654
655	static SDValue performCMovFPCombine(SDNode *N, SelectionDAG &DAG,
656	TargetLowering::DAGCombinerInfo &DCI,
657	const MipsSubtarget &Subtarget) {
658	if (DCI.isBeforeLegalizeOps())
659	return SDValue();
660
661	SDValue ValueIfTrue = N->getOperand(0), ValueIfFalse = N->getOperand(2);
662
663	ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(ValueIfFalse);
664	if (!FalseC \|\| FalseC->getZExtValue())
665	return SDValue();
666
667	// Since RHS (False) is 0, we swap the order of the True/False operands
668	// (obviously also inverting the condition) so that we can
669	// take advantage of conditional moves using the $0 register.
670	// Example:
671	// return (a != 0) ? x : 0;
672	// load $reg, x
673	// movz $reg, $0, a
674	unsigned Opc = (N->getOpcode() == MipsISD::CMovFP_T) ? MipsISD::CMovFP_F :
675	MipsISD::CMovFP_T;
676
677	SDValue FCC = N->getOperand(1), Glue = N->getOperand(3);
678	return DAG.getNode(Opc, SDLoc(N), ValueIfFalse.getValueType(),
679	ValueIfFalse, FCC, ValueIfTrue, Glue);
680	}
681
682	static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG,
683	TargetLowering::DAGCombinerInfo &DCI,
684	const MipsSubtarget &Subtarget) {
685	// Pattern match EXT.
686	// $dst = and ((sra or srl) $src , pos), (2**size - 1)
687	// => ext $dst, $src, size, pos
688	if (DCI.isBeforeLegalizeOps() \|\| !Subtarget.hasExtractInsert())
689	return SDValue();
690
691	SDValue ShiftRight = N->getOperand(0), Mask = N->getOperand(1);
692	unsigned ShiftRightOpc = ShiftRight.getOpcode();
693
694	// Op's first operand must be a shift right.
695	if (ShiftRightOpc != ISD::SRA && ShiftRightOpc != ISD::SRL)
696	return SDValue();
697
698	// The second operand of the shift must be an immediate.
699	ConstantSDNode *CN;
700	if (!(CN = dyn_cast<ConstantSDNode>(ShiftRight.getOperand(1))))
701	return SDValue();
702
703	uint64_t Pos = CN->getZExtValue();
704	uint64_t SMPos, SMSize;
705
706	// Op's second operand must be a shifted mask.
707	if (!(CN = dyn_cast<ConstantSDNode>(Mask)) \|\|
708	!isShiftedMask(CN->getZExtValue(), SMPos, SMSize))
709	return SDValue();
710
711	// Return if the shifted mask does not start at bit 0 or the sum of its size
712	// and Pos exceeds the word's size.
713	EVT ValTy = N->getValueType(0);
714	if (SMPos != 0 \|\| Pos + SMSize > ValTy.getSizeInBits())
715	return SDValue();
716
717	SDLoc DL(N);
718	return DAG.getNode(MipsISD::Ext, DL, ValTy,
719	ShiftRight.getOperand(0),
720	DAG.getConstant(Pos, DL, MVT::i32),
721	DAG.getConstant(SMSize, DL, MVT::i32));
722	}
723
724	static SDValue performORCombine(SDNode *N, SelectionDAG &DAG,
725	TargetLowering::DAGCombinerInfo &DCI,
726	const MipsSubtarget &Subtarget) {
727	// Pattern match INS.
728	// $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1),
729	// where mask1 = (2**size - 1) << pos, mask0 = ~mask1
730	// => ins $dst, $src, size, pos, $src1
731	if (DCI.isBeforeLegalizeOps() \|\| !Subtarget.hasExtractInsert())
732	return SDValue();
733
734	SDValue And0 = N->getOperand(0), And1 = N->getOperand(1);
735	uint64_t SMPos0, SMSize0, SMPos1, SMSize1;
736	ConstantSDNode *CN;
737
738	// See if Op's first operand matches (and $src1 , mask0).
739	if (And0.getOpcode() != ISD::AND)
740	return SDValue();
741
742	if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) \|\|
743	!isShiftedMask(~CN->getSExtValue(), SMPos0, SMSize0))
744	return SDValue();
745
746	// See if Op's second operand matches (and (shl $src, pos), mask1).
747	if (And1.getOpcode() != ISD::AND)
748	return SDValue();
749
750	if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) \|\|
751	!isShiftedMask(CN->getZExtValue(), SMPos1, SMSize1))
752	return SDValue();
753
754	// The shift masks must have the same position and size.
755	if (SMPos0 != SMPos1 \|\| SMSize0 != SMSize1)
756	return SDValue();
757
758	SDValue Shl = And1.getOperand(0);
759	if (Shl.getOpcode() != ISD::SHL)
760	return SDValue();
761
762	if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1))))
763	return SDValue();
764
765	unsigned Shamt = CN->getZExtValue();
766
767	// Return if the shift amount and the first bit position of mask are not the
768	// same.
769	EVT ValTy = N->getValueType(0);
770	if ((Shamt != SMPos0) \|\| (SMPos0 + SMSize0 > ValTy.getSizeInBits()))
771	return SDValue();
772
773	SDLoc DL(N);
774	return DAG.getNode(MipsISD::Ins, DL, ValTy, Shl.getOperand(0),
775	DAG.getConstant(SMPos0, DL, MVT::i32),
776	DAG.getConstant(SMSize0, DL, MVT::i32),
777	And0.getOperand(0));
778	}
779
780	static SDValue performADDCombine(SDNode *N, SelectionDAG &DAG,
781	TargetLowering::DAGCombinerInfo &DCI,
782	const MipsSubtarget &Subtarget) {
783	// (add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt))
784
785	if (DCI.isBeforeLegalizeOps())
786	return SDValue();
787
788	SDValue Add = N->getOperand(1);
789
790	if (Add.getOpcode() != ISD::ADD)
791	return SDValue();
792
793	SDValue Lo = Add.getOperand(1);
794
795	if ((Lo.getOpcode() != MipsISD::Lo) \|\|
796	(Lo.getOperand(0).getOpcode() != ISD::TargetJumpTable))
797	return SDValue();
798
799	EVT ValTy = N->getValueType(0);
800	SDLoc DL(N);
801
802	SDValue Add1 = DAG.getNode(ISD::ADD, DL, ValTy, N->getOperand(0),
803	Add.getOperand(0));
804	return DAG.getNode(ISD::ADD, DL, ValTy, Add1, Lo);
805	}
806
807	static SDValue performAssertZextCombine(SDNode *N, SelectionDAG &DAG,
808	TargetLowering::DAGCombinerInfo &DCI,
809	const MipsSubtarget &Subtarget) {
810	SDValue N0 = N->getOperand(0);
811	EVT NarrowerVT = cast<VTSDNode>(N->getOperand(1))->getVT();
812
813	if (N0.getOpcode() != ISD::TRUNCATE)
814	return SDValue();
815
816	if (N0.getOperand(0).getOpcode() != ISD::AssertZext)
817	return SDValue();
818
819	// fold (AssertZext (trunc (AssertZext x))) -> (trunc (AssertZext x))
820	// if the type of the extension of the innermost AssertZext node is
821	// smaller from that of the outermost node, eg:
822	// (AssertZext:i32 (trunc:i32 (AssertZext:i64 X, i32)), i8)
823	// -> (trunc:i32 (AssertZext X, i8))
824	SDValue WiderAssertZext = N0.getOperand(0);
825	EVT WiderVT = cast<VTSDNode>(WiderAssertZext->getOperand(1))->getVT();
826
827	if (NarrowerVT.bitsLT(WiderVT)) {
828	SDValue NewAssertZext = DAG.getNode(
829	ISD::AssertZext, SDLoc(N), WiderAssertZext.getValueType(),
830	WiderAssertZext.getOperand(0), DAG.getValueType(NarrowerVT));
831	return DAG.getNode(ISD::TRUNCATE, SDLoc(N), N->getValueType(0),
832	NewAssertZext);
833	}
834
835	return SDValue();
836	}
837
838	SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI)
839	const {
840	SelectionDAG &DAG = DCI.DAG;
841	unsigned Opc = N->getOpcode();
842
843	switch (Opc) {
844	default: break;
845	case ISD::SDIVREM:
846	case ISD::UDIVREM:
847	return performDivRemCombine(N, DAG, DCI, Subtarget);
848	case ISD::SELECT:
849	return performSELECTCombine(N, DAG, DCI, Subtarget);
850	case MipsISD::CMovFP_F:
851	case MipsISD::CMovFP_T:
852	return performCMovFPCombine(N, DAG, DCI, Subtarget);
853	case ISD::AND:
854	return performANDCombine(N, DAG, DCI, Subtarget);
855	case ISD::OR:
856	return performORCombine(N, DAG, DCI, Subtarget);
857	case ISD::ADD:
858	return performADDCombine(N, DAG, DCI, Subtarget);
859	case ISD::AssertZext:
860	return performAssertZextCombine(N, DAG, DCI, Subtarget);
861	}
862
863	return SDValue();
864	}
865
866	bool MipsTargetLowering::isCheapToSpeculateCttz() const {
867	return Subtarget.hasMips32();
868	}
869
870	bool MipsTargetLowering::isCheapToSpeculateCtlz() const {
871	return Subtarget.hasMips32();
872	}
873
874	void
875	MipsTargetLowering::LowerOperationWrapper(SDNode *N,
876	SmallVectorImpl<SDValue> &Results,
877	SelectionDAG &DAG) const {
878	SDValue Res = LowerOperation(SDValue(N, 0), DAG);
879
880	for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I)
881	Results.push_back(Res.getValue(I));
882	}
883
884	void
885	MipsTargetLowering::ReplaceNodeResults(SDNode *N,
886	SmallVectorImpl<SDValue> &Results,
887	SelectionDAG &DAG) const {
888	return LowerOperationWrapper(N, Results, DAG);
889	}
890
891	SDValue MipsTargetLowering::
892	LowerOperation(SDValue Op, SelectionDAG &DAG) const
893	{
894	switch (Op.getOpcode())
895	{
896	case ISD::BR_JT: return lowerBR_JT(Op, DAG);
897	case ISD::BRCOND: return lowerBRCOND(Op, DAG);
898	case ISD::ConstantPool: return lowerConstantPool(Op, DAG);
899	case ISD::GlobalAddress: return lowerGlobalAddress(Op, DAG);
900	case ISD::BlockAddress: return lowerBlockAddress(Op, DAG);
901	case ISD::GlobalTLSAddress: return lowerGlobalTLSAddress(Op, DAG);
902	case ISD::JumpTable: return lowerJumpTable(Op, DAG);
903	case ISD::SELECT: return lowerSELECT(Op, DAG);
904	case ISD::SETCC: return lowerSETCC(Op, DAG);
905	case ISD::VASTART: return lowerVASTART(Op, DAG);
906	case ISD::VAARG: return lowerVAARG(Op, DAG);
907	case ISD::FCOPYSIGN: return lowerFCOPYSIGN(Op, DAG);
908	case ISD::FRAMEADDR: return lowerFRAMEADDR(Op, DAG);
909	case ISD::RETURNADDR: return lowerRETURNADDR(Op, DAG);
910	case ISD::EH_RETURN: return lowerEH_RETURN(Op, DAG);
911	case ISD::ATOMIC_FENCE: return lowerATOMIC_FENCE(Op, DAG);
912	case ISD::SHL_PARTS: return lowerShiftLeftParts(Op, DAG);
913	case ISD::SRA_PARTS: return lowerShiftRightParts(Op, DAG, true);
914	case ISD::SRL_PARTS: return lowerShiftRightParts(Op, DAG, false);
915	case ISD::LOAD: return lowerLOAD(Op, DAG);
916	case ISD::STORE: return lowerSTORE(Op, DAG);
917	case ISD::ADD: return lowerADD(Op, DAG);
918	case ISD::FP_TO_SINT: return lowerFP_TO_SINT(Op, DAG);
919	}
920	return SDValue();
921	}
922
923	//===----------------------------------------------------------------------===//
924	// Lower helper functions
925	//===----------------------------------------------------------------------===//
926
927	// addLiveIn - This helper function adds the specified physical register to the
928	// MachineFunction as a live in value. It also creates a corresponding
929	// virtual register for it.
930	static unsigned
931	addLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC)
932	{
933	unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
934	MF.getRegInfo().addLiveIn(PReg, VReg);
935	return VReg;
936	}
937
938	static MachineBasicBlock insertDivByZeroTrap(MachineInstr MI,
939	MachineBasicBlock &MBB,
940	const TargetInstrInfo &TII,
941	bool Is64Bit, bool IsMicroMips) {
942	if (NoZeroDivCheck)
943	return &MBB;
944
945	// Insert instruction "teq $divisor_reg, $zero, 7".
946	MachineBasicBlock::iterator I(MI);
947	MachineInstrBuilder MIB;
948	MachineOperand &Divisor = MI->getOperand(2);
949	MIB = BuildMI(MBB, std::next(I), MI->getDebugLoc(),
950	TII.get(IsMicroMips ? Mips::TEQ_MM : Mips::TEQ))
951	.addReg(Divisor.getReg(), getKillRegState(Divisor.isKill()))
952	.addReg(Mips::ZERO).addImm(7);
953
954	// Use the 32-bit sub-register if this is a 64-bit division.
955	if (Is64Bit)
956	MIB->getOperand(0).setSubReg(Mips::sub_32);
957
958	// Clear Divisor's kill flag.
959	Divisor.setIsKill(false);
960
961	// We would normally delete the original instruction here but in this case
962	// we only needed to inject an additional instruction rather than replace it.
963
964	return &MBB;
965	}
966
967	MachineBasicBlock *
968	MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
969	MachineBasicBlock *BB) const {
970	switch (MI->getOpcode()) {
971	default:
972	llvm_unreachable("Unexpected instr type to insert")::llvm::llvm_unreachable_internal("Unexpected instr type to insert" , "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MipsISelLowering.cpp" , 972);
973	case Mips::ATOMIC_LOAD_ADD_I8:
974	return emitAtomicBinaryPartword(MI, BB, 1, Mips::ADDu);
975	case Mips::ATOMIC_LOAD_ADD_I16:
976	return emitAtomicBinaryPartword(MI, BB, 2, Mips::ADDu);
977	case Mips::ATOMIC_LOAD_ADD_I32:
978	return emitAtomicBinary(MI, BB, 4, Mips::ADDu);
979	case Mips::ATOMIC_LOAD_ADD_I64:
980	return emitAtomicBinary(MI, BB, 8, Mips::DADDu);
981
982	case Mips::ATOMIC_LOAD_AND_I8:
983	return emitAtomicBinaryPartword(MI, BB, 1, Mips::AND);
984	case Mips::ATOMIC_LOAD_AND_I16:
985	return emitAtomicBinaryPartword(MI, BB, 2, Mips::AND);
986	case Mips::ATOMIC_LOAD_AND_I32:
987	return emitAtomicBinary(MI, BB, 4, Mips::AND);
988	case Mips::ATOMIC_LOAD_AND_I64:
989	return emitAtomicBinary(MI, BB, 8, Mips::AND64);
990
991	case Mips::ATOMIC_LOAD_OR_I8:
992	return emitAtomicBinaryPartword(MI, BB, 1, Mips::OR);
993	case Mips::ATOMIC_LOAD_OR_I16:
994	return emitAtomicBinaryPartword(MI, BB, 2, Mips::OR);
995	case Mips::ATOMIC_LOAD_OR_I32:
996	return emitAtomicBinary(MI, BB, 4, Mips::OR);
997	case Mips::ATOMIC_LOAD_OR_I64:
998	return emitAtomicBinary(MI, BB, 8, Mips::OR64);
999
1000	case Mips::ATOMIC_LOAD_XOR_I8:
1001	return emitAtomicBinaryPartword(MI, BB, 1, Mips::XOR);
1002	case Mips::ATOMIC_LOAD_XOR_I16:
1003	return emitAtomicBinaryPartword(MI, BB, 2, Mips::XOR);
1004	case Mips::ATOMIC_LOAD_XOR_I32:
1005	return emitAtomicBinary(MI, BB, 4, Mips::XOR);
1006	case Mips::ATOMIC_LOAD_XOR_I64:
1007	return emitAtomicBinary(MI, BB, 8, Mips::XOR64);
1008
1009	case Mips::ATOMIC_LOAD_NAND_I8:
1010	return emitAtomicBinaryPartword(MI, BB, 1, 0, true);
1011	case Mips::ATOMIC_LOAD_NAND_I16:
1012	return emitAtomicBinaryPartword(MI, BB, 2, 0, true);
1013	case Mips::ATOMIC_LOAD_NAND_I32:
1014	return emitAtomicBinary(MI, BB, 4, 0, true);
1015	case Mips::ATOMIC_LOAD_NAND_I64:
1016	return emitAtomicBinary(MI, BB, 8, 0, true);
1017
1018	case Mips::ATOMIC_LOAD_SUB_I8:
1019	return emitAtomicBinaryPartword(MI, BB, 1, Mips::SUBu);
1020	case Mips::ATOMIC_LOAD_SUB_I16:
1021	return emitAtomicBinaryPartword(MI, BB, 2, Mips::SUBu);
1022	case Mips::ATOMIC_LOAD_SUB_I32:
1023	return emitAtomicBinary(MI, BB, 4, Mips::SUBu);
1024	case Mips::ATOMIC_LOAD_SUB_I64:
1025	return emitAtomicBinary(MI, BB, 8, Mips::DSUBu);
1026
1027	case Mips::ATOMIC_SWAP_I8:
1028	return emitAtomicBinaryPartword(MI, BB, 1, 0);
1029	case Mips::ATOMIC_SWAP_I16:
1030	return emitAtomicBinaryPartword(MI, BB, 2, 0);
1031	case Mips::ATOMIC_SWAP_I32:
1032	return emitAtomicBinary(MI, BB, 4, 0);
1033	case Mips::ATOMIC_SWAP_I64:
1034	return emitAtomicBinary(MI, BB, 8, 0);
1035
1036	case Mips::ATOMIC_CMP_SWAP_I8:
1037	return emitAtomicCmpSwapPartword(MI, BB, 1);
1038	case Mips::ATOMIC_CMP_SWAP_I16:
1039	return emitAtomicCmpSwapPartword(MI, BB, 2);
1040	case Mips::ATOMIC_CMP_SWAP_I32:
1041	return emitAtomicCmpSwap(MI, BB, 4);
1042	case Mips::ATOMIC_CMP_SWAP_I64:
1043	return emitAtomicCmpSwap(MI, BB, 8);
1044	case Mips::PseudoSDIV:
1045	case Mips::PseudoUDIV:
1046	case Mips::DIV:
1047	case Mips::DIVU:
1048	case Mips::MOD:
1049	case Mips::MODU:
1050	return insertDivByZeroTrap(MI, BB, Subtarget.getInstrInfo(), false,
1051	false);
1052	case Mips::SDIV_MM_Pseudo:
1053	case Mips::UDIV_MM_Pseudo:
1054	case Mips::SDIV_MM:
1055	case Mips::UDIV_MM:
1056	case Mips::DIV_MMR6:
1057	case Mips::DIVU_MMR6:
1058	case Mips::MOD_MMR6:
1059	case Mips::MODU_MMR6:
1060	return insertDivByZeroTrap(MI, BB, Subtarget.getInstrInfo(), false, true);
1061	case Mips::PseudoDSDIV:
1062	case Mips::PseudoDUDIV:
1063	case Mips::DDIV:
1064	case Mips::DDIVU:
1065	case Mips::DMOD:
1066	case Mips::DMODU:
1067	return insertDivByZeroTrap(MI, BB, Subtarget.getInstrInfo(), true, false);
1068	case Mips::DDIV_MM64R6:
1069	case Mips::DDIVU_MM64R6:
1070	case Mips::DMOD_MM64R6:
1071	case Mips::DMODU_MM64R6:
1072	return insertDivByZeroTrap(MI, BB, Subtarget.getInstrInfo(), true, true);
1073	case Mips::SEL_D:
1074	return emitSEL_D(MI, BB);
1075
1076	case Mips::PseudoSELECT_I:
1077	case Mips::PseudoSELECT_I64:
1078	case Mips::PseudoSELECT_S:
1079	case Mips::PseudoSELECT_D32:
1080	case Mips::PseudoSELECT_D64:
1081	return emitPseudoSELECT(MI, BB, false, Mips::BNE);
1082	case Mips::PseudoSELECTFP_F_I:
1083	case Mips::PseudoSELECTFP_F_I64:
1084	case Mips::PseudoSELECTFP_F_S:
1085	case Mips::PseudoSELECTFP_F_D32:
1086	case Mips::PseudoSELECTFP_F_D64:
1087	return emitPseudoSELECT(MI, BB, true, Mips::BC1F);
1088	case Mips::PseudoSELECTFP_T_I:
1089	case Mips::PseudoSELECTFP_T_I64:
1090	case Mips::PseudoSELECTFP_T_S:
1091	case Mips::PseudoSELECTFP_T_D32:
1092	case Mips::PseudoSELECTFP_T_D64:
1093	return emitPseudoSELECT(MI, BB, true, Mips::BC1T);
1094	}
1095	}
1096
1097	// This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and
1098	// Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true)
1099	MachineBasicBlock *
1100	MipsTargetLowering::emitAtomicBinary(MachineInstr MI, MachineBasicBlock BB,
1101	unsigned Size, unsigned BinOpcode,
1102	bool Nand) const {
1103	assert((Size == 4 \|\| Size == 8) && "Unsupported size for EmitAtomicBinary.")(((Size == 4 \|\| Size == 8) && "Unsupported size for EmitAtomicBinary." ) ? static_cast<void> (0) : __assert_fail ("(Size == 4 \|\| Size == 8) && \"Unsupported size for EmitAtomicBinary.\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MipsISelLowering.cpp" , 1103, __PRETTY_FUNCTION__));
1104
1105	MachineFunction *MF = BB->getParent();
1106	MachineRegisterInfo &RegInfo = MF->getRegInfo();
1107	const TargetRegisterClass RC = getRegClassFor(MVT::getIntegerVT(Size 8));
1108	const TargetInstrInfo *TII = Subtarget.getInstrInfo();
1109	DebugLoc DL = MI->getDebugLoc();
1110	unsigned LL, SC, AND, NOR, ZERO, BEQ;
1111
1112	// FIXME: The below code should check for the ISA to emit the correct 64bit
1113	// operations when the size is 4.
1114	if (Size == 4) {
1115	if (isMicroMips) {
1116	LL = Mips::LL_MM;
1117	SC = Mips::SC_MM;
1118	} else {
1119	LL = Subtarget.hasMips32r6() ? Mips::LL_R6 : Mips::LL;
1120	SC = Subtarget.hasMips32r6() ? Mips::SC_R6 : Mips::SC;
1121	}
1122	AND = Mips::AND;
1123	NOR = Mips::NOR;
1124	ZERO = Mips::ZERO;
1125	BEQ = Mips::BEQ;
1126	} else {
1127	LL = Subtarget.hasMips64r6() ? Mips::LLD_R6 : Mips::LLD;
1128	SC = Subtarget.hasMips64r6() ? Mips::SCD_R6 : Mips::SCD;
1129	AND = Mips::AND64;
1130	NOR = Mips::NOR64;
1131	ZERO = Mips::ZERO_64;
1132	BEQ = Mips::BEQ64;
1133	}
1134
1135	unsigned OldVal = MI->getOperand(0).getReg();
1136	unsigned Ptr = MI->getOperand(1).getReg();
1137	unsigned Incr = MI->getOperand(2).getReg();
1138
1139	unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1140	unsigned AndRes = RegInfo.createVirtualRegister(RC);
1141	unsigned Success = RegInfo.createVirtualRegister(RC);
1142
1143	// insert new blocks after the current block
1144	const BasicBlock *LLVM_BB = BB->getBasicBlock();
1145	MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1146	MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1147	MachineFunction::iterator It = ++BB->getIterator();
1148	MF->insert(It, loopMBB);
1149	MF->insert(It, exitMBB);
1150
1151	// Transfer the remainder of BB and its successor edges to exitMBB.
1152	exitMBB->splice(exitMBB->begin(), BB,
1153	std::next(MachineBasicBlock::iterator(MI)), BB->end());
1154	exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1155
1156	// thisMBB:
1157	// ...
1158	// fallthrough --> loopMBB
1159	BB->addSuccessor(loopMBB);
1160	loopMBB->addSuccessor(loopMBB);
1161	loopMBB->addSuccessor(exitMBB);
1162
1163	// loopMBB:
1164	// ll oldval, 0(ptr)
1165	// <binop> storeval, oldval, incr
1166	// sc success, storeval, 0(ptr)
1167	// beq success, $0, loopMBB
1168	BB = loopMBB;
1169	BuildMI(BB, DL, TII->get(LL), OldVal).addReg(Ptr).addImm(0);
1170	if (Nand) {
1171	// and andres, oldval, incr
1172	// nor storeval, $0, andres
1173	BuildMI(BB, DL, TII->get(AND), AndRes).addReg(OldVal).addReg(Incr);
1174	BuildMI(BB, DL, TII->get(NOR), StoreVal).addReg(ZERO).addReg(AndRes);
1175	} else if (BinOpcode) {
1176	// <binop> storeval, oldval, incr
1177	BuildMI(BB, DL, TII->get(BinOpcode), StoreVal).addReg(OldVal).addReg(Incr);
1178	} else {
1179	StoreVal = Incr;
1180	}
1181	BuildMI(BB, DL, TII->get(SC), Success).addReg(StoreVal).addReg(Ptr).addImm(0);
1182	BuildMI(BB, DL, TII->get(BEQ)).addReg(Success).addReg(ZERO).addMBB(loopMBB);
1183
1184	MI->eraseFromParent(); // The instruction is gone now.
1185
1186	return exitMBB;
1187	}
1188
1189	MachineBasicBlock *MipsTargetLowering::emitSignExtendToI32InReg(
1190	MachineInstr MI, MachineBasicBlock BB, unsigned Size, unsigned DstReg,
1191	unsigned SrcReg) const {
1192	const TargetInstrInfo *TII = Subtarget.getInstrInfo();
1193	DebugLoc DL = MI->getDebugLoc();
1194
1195	if (Subtarget.hasMips32r2() && Size == 1) {
1196	BuildMI(BB, DL, TII->get(Mips::SEB), DstReg).addReg(SrcReg);
1197	return BB;
1198	}
1199
1200	if (Subtarget.hasMips32r2() && Size == 2) {
1201	BuildMI(BB, DL, TII->get(Mips::SEH), DstReg).addReg(SrcReg);
1202	return BB;
1203	}
1204
1205	MachineFunction *MF = BB->getParent();
1206	MachineRegisterInfo &RegInfo = MF->getRegInfo();
1207	const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1208	unsigned ScrReg = RegInfo.createVirtualRegister(RC);
1209
1210	assert(Size < 32)((Size < 32) ? static_cast<void> (0) : __assert_fail ("Size < 32", "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MipsISelLowering.cpp" , 1210, __PRETTY_FUNCTION__));
1211	int64_t ShiftImm = 32 - (Size * 8);
1212
1213	BuildMI(BB, DL, TII->get(Mips::SLL), ScrReg).addReg(SrcReg).addImm(ShiftImm);
1214	BuildMI(BB, DL, TII->get(Mips::SRA), DstReg).addReg(ScrReg).addImm(ShiftImm);
1215
1216	return BB;
1217	}
1218
1219	MachineBasicBlock *MipsTargetLowering::emitAtomicBinaryPartword(
1220	MachineInstr MI, MachineBasicBlock BB, unsigned Size, unsigned BinOpcode,
1221	bool Nand) const {
1222	assert((Size == 1 \|\| Size == 2) &&(((Size == 1 \|\| Size == 2) && "Unsupported size for EmitAtomicBinaryPartial." ) ? static_cast<void> (0) : __assert_fail ("(Size == 1 \|\| Size == 2) && \"Unsupported size for EmitAtomicBinaryPartial.\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MipsISelLowering.cpp" , 1223, __PRETTY_FUNCTION__))
1223	"Unsupported size for EmitAtomicBinaryPartial.")(((Size == 1 \|\| Size == 2) && "Unsupported size for EmitAtomicBinaryPartial." ) ? static_cast<void> (0) : __assert_fail ("(Size == 1 \|\| Size == 2) && \"Unsupported size for EmitAtomicBinaryPartial.\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MipsISelLowering.cpp" , 1223, __PRETTY_FUNCTION__));
1224
1225	MachineFunction *MF = BB->getParent();
1226	MachineRegisterInfo &RegInfo = MF->getRegInfo();
1227	const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1228	bool ArePtrs64bit = ABI.ArePtrs64bit();
1229	const TargetRegisterClass *RCp =
1230	getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32);
1231	const TargetInstrInfo *TII = Subtarget.getInstrInfo();
1232	DebugLoc DL = MI->getDebugLoc();
1233
1234	unsigned Dest = MI->getOperand(0).getReg();
1235	unsigned Ptr = MI->getOperand(1).getReg();
1236	unsigned Incr = MI->getOperand(2).getReg();
1237
1238	unsigned AlignedAddr = RegInfo.createVirtualRegister(RCp);
1239	unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
1240	unsigned Mask = RegInfo.createVirtualRegister(RC);
1241	unsigned Mask2 = RegInfo.createVirtualRegister(RC);
1242	unsigned NewVal = RegInfo.createVirtualRegister(RC);
1243	unsigned OldVal = RegInfo.createVirtualRegister(RC);
1244	unsigned Incr2 = RegInfo.createVirtualRegister(RC);
1245	unsigned MaskLSB2 = RegInfo.createVirtualRegister(RCp);
1246	unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC);
1247	unsigned MaskUpper = RegInfo.createVirtualRegister(RC);
1248	unsigned AndRes = RegInfo.createVirtualRegister(RC);
1249	unsigned BinOpRes = RegInfo.createVirtualRegister(RC);
1250	unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC);
1251	unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1252	unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC);
1253	unsigned SrlRes = RegInfo.createVirtualRegister(RC);
1254	unsigned Success = RegInfo.createVirtualRegister(RC);
1255
1256	// insert new blocks after the current block
1257	const BasicBlock *LLVM_BB = BB->getBasicBlock();
1258	MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1259	MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1260	MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1261	MachineFunction::iterator It = ++BB->getIterator();
1262	MF->insert(It, loopMBB);
1263	MF->insert(It, sinkMBB);
1264	MF->insert(It, exitMBB);
1265
1266	// Transfer the remainder of BB and its successor edges to exitMBB.
1267	exitMBB->splice(exitMBB->begin(), BB,
1268	std::next(MachineBasicBlock::iterator(MI)), BB->end());
1269	exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1270
1271	BB->addSuccessor(loopMBB);
1272	loopMBB->addSuccessor(loopMBB);
1273	loopMBB->addSuccessor(sinkMBB);
1274	sinkMBB->addSuccessor(exitMBB);
1275
1276	// thisMBB:
1277	// addiu masklsb2,$0,-4 # 0xfffffffc
1278	// and alignedaddr,ptr,masklsb2
1279	// andi ptrlsb2,ptr,3
1280	// sll shiftamt,ptrlsb2,3
1281	// ori maskupper,$0,255 # 0xff
1282	// sll mask,maskupper,shiftamt
1283	// nor mask2,$0,mask
1284	// sll incr2,incr,shiftamt
1285
1286	int64_t MaskImm = (Size == 1) ? 255 : 65535;
1287	BuildMI(BB, DL, TII->get(ABI.GetPtrAddiuOp()), MaskLSB2)
1288	.addReg(ABI.GetNullPtr()).addImm(-4);
1289	BuildMI(BB, DL, TII->get(ABI.GetPtrAndOp()), AlignedAddr)
1290	.addReg(Ptr).addReg(MaskLSB2);
1291	BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2)
1292	.addReg(Ptr, 0, ArePtrs64bit ? Mips::sub_32 : 0).addImm(3);
1293	if (Subtarget.isLittle()) {
1294	BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1295	} else {
1296	unsigned Off = RegInfo.createVirtualRegister(RC);
1297	BuildMI(BB, DL, TII->get(Mips::XORi), Off)
1298	.addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2);
1299	BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
1300	}
1301	BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper)
1302	.addReg(Mips::ZERO).addImm(MaskImm);
1303	BuildMI(BB, DL, TII->get(Mips::SLLV), Mask)
1304	.addReg(MaskUpper).addReg(ShiftAmt);
1305	BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
1306	BuildMI(BB, DL, TII->get(Mips::SLLV), Incr2).addReg(Incr).addReg(ShiftAmt);
1307
1308	// atomic.load.binop
1309	// loopMBB:
1310	// ll oldval,0(alignedaddr)
1311	// binop binopres,oldval,incr2
1312	// and newval,binopres,mask
1313	// and maskedoldval0,oldval,mask2
1314	// or storeval,maskedoldval0,newval
1315	// sc success,storeval,0(alignedaddr)
1316	// beq success,$0,loopMBB
1317
1318	// atomic.swap
1319	// loopMBB:
1320	// ll oldval,0(alignedaddr)
1321	// and newval,incr2,mask
1322	// and maskedoldval0,oldval,mask2
1323	// or storeval,maskedoldval0,newval
1324	// sc success,storeval,0(alignedaddr)
1325	// beq success,$0,loopMBB
1326
1327	BB = loopMBB;
1328	unsigned LL = isMicroMips ? Mips::LL_MM : Mips::LL;
1329	BuildMI(BB, DL, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0);
1330	if (Nand) {
1331	// and andres, oldval, incr2
1332	// nor binopres, $0, andres
1333	// and newval, binopres, mask
1334	BuildMI(BB, DL, TII->get(Mips::AND), AndRes).addReg(OldVal).addReg(Incr2);
1335	BuildMI(BB, DL, TII->get(Mips::NOR), BinOpRes)
1336	.addReg(Mips::ZERO).addReg(AndRes);
1337	BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask);
1338	} else if (BinOpcode) {
1339	// <binop> binopres, oldval, incr2
1340	// and newval, binopres, mask
1341	BuildMI(BB, DL, TII->get(BinOpcode), BinOpRes).addReg(OldVal).addReg(Incr2);
1342	BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask);
1343	} else { // atomic.swap
1344	// and newval, incr2, mask
1345	BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(Incr2).addReg(Mask);
1346	}
1347
1348	BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal0)
1349	.addReg(OldVal).addReg(Mask2);
1350	BuildMI(BB, DL, TII->get(Mips::OR), StoreVal)
1351	.addReg(MaskedOldVal0).addReg(NewVal);
1352	unsigned SC = isMicroMips ? Mips::SC_MM : Mips::SC;
1353	BuildMI(BB, DL, TII->get(SC), Success)
1354	.addReg(StoreVal).addReg(AlignedAddr).addImm(0);
1355	BuildMI(BB, DL, TII->get(Mips::BEQ))
1356	.addReg(Success).addReg(Mips::ZERO).addMBB(loopMBB);
1357
1358	// sinkMBB:
1359	// and maskedoldval1,oldval,mask
1360	// srl srlres,maskedoldval1,shiftamt
1361	// sign_extend dest,srlres
1362	BB = sinkMBB;
1363
1364	BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal1)
1365	.addReg(OldVal).addReg(Mask);
1366	BuildMI(BB, DL, TII->get(Mips::SRLV), SrlRes)
1367	.addReg(MaskedOldVal1).addReg(ShiftAmt);
1368	BB = emitSignExtendToI32InReg(MI, BB, Size, Dest, SrlRes);
1369
1370	MI->eraseFromParent(); // The instruction is gone now.
1371
1372	return exitMBB;
1373	}
1374
1375	MachineBasicBlock * MipsTargetLowering::emitAtomicCmpSwap(MachineInstr *MI,
1376	MachineBasicBlock *BB,
1377	unsigned Size) const {
1378	assert((Size == 4 \|\| Size == 8) && "Unsupported size for EmitAtomicCmpSwap.")(((Size == 4 \|\| Size == 8) && "Unsupported size for EmitAtomicCmpSwap." ) ? static_cast<void> (0) : __assert_fail ("(Size == 4 \|\| Size == 8) && \"Unsupported size for EmitAtomicCmpSwap.\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MipsISelLowering.cpp" , 1378, __PRETTY_FUNCTION__));
1379
1380	MachineFunction *MF = BB->getParent();
1381	MachineRegisterInfo &RegInfo = MF->getRegInfo();
1382	const TargetRegisterClass RC = getRegClassFor(MVT::getIntegerVT(Size 8));
1383	const TargetInstrInfo *TII = Subtarget.getInstrInfo();
1384	DebugLoc DL = MI->getDebugLoc();
1385	unsigned LL, SC, ZERO, BNE, BEQ;
1386
1387	if (Size == 4) {
1388	if (isMicroMips) {
1389	LL = Mips::LL_MM;
1390	SC = Mips::SC_MM;
1391	} else {
1392	LL = Subtarget.hasMips32r6() ? Mips::LL_R6 : Mips::LL;
1393	SC = Subtarget.hasMips32r6() ? Mips::SC_R6 : Mips::SC;
1394	}
1395	ZERO = Mips::ZERO;
1396	BNE = Mips::BNE;
1397	BEQ = Mips::BEQ;
1398	} else {
1399	LL = Subtarget.hasMips64r6() ? Mips::LLD_R6 : Mips::LLD;
1400	SC = Subtarget.hasMips64r6() ? Mips::SCD_R6 : Mips::SCD;
1401	ZERO = Mips::ZERO_64;
1402	BNE = Mips::BNE64;
1403	BEQ = Mips::BEQ64;
1404	}
1405
1406	unsigned Dest = MI->getOperand(0).getReg();
1407	unsigned Ptr = MI->getOperand(1).getReg();
1408	unsigned OldVal = MI->getOperand(2).getReg();
1409	unsigned NewVal = MI->getOperand(3).getReg();
1410
1411	unsigned Success = RegInfo.createVirtualRegister(RC);
1412
1413	// insert new blocks after the current block
1414	const BasicBlock *LLVM_BB = BB->getBasicBlock();
1415	MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1416	MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1417	MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1418	MachineFunction::iterator It = ++BB->getIterator();
1419	MF->insert(It, loop1MBB);
1420	MF->insert(It, loop2MBB);
1421	MF->insert(It, exitMBB);
1422
1423	// Transfer the remainder of BB and its successor edges to exitMBB.
1424	exitMBB->splice(exitMBB->begin(), BB,
1425	std::next(MachineBasicBlock::iterator(MI)), BB->end());
1426	exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1427
1428	// thisMBB:
1429	// ...
1430	// fallthrough --> loop1MBB
1431	BB->addSuccessor(loop1MBB);
1432	loop1MBB->addSuccessor(exitMBB);
1433	loop1MBB->addSuccessor(loop2MBB);
1434	loop2MBB->addSuccessor(loop1MBB);
1435	loop2MBB->addSuccessor(exitMBB);
1436
1437	// loop1MBB:
1438	// ll dest, 0(ptr)
1439	// bne dest, oldval, exitMBB
1440	BB = loop1MBB;
1441	BuildMI(BB, DL, TII->get(LL), Dest).addReg(Ptr).addImm(0);
1442	BuildMI(BB, DL, TII->get(BNE))
1443	.addReg(Dest).addReg(OldVal).addMBB(exitMBB);
1444
1445	// loop2MBB:
1446	// sc success, newval, 0(ptr)
1447	// beq success, $0, loop1MBB
1448	BB = loop2MBB;
1449	BuildMI(BB, DL, TII->get(SC), Success)
1450	.addReg(NewVal).addReg(Ptr).addImm(0);
1451	BuildMI(BB, DL, TII->get(BEQ))
1452	.addReg(Success).addReg(ZERO).addMBB(loop1MBB);
1453
1454	MI->eraseFromParent(); // The instruction is gone now.
1455
1456	return exitMBB;
1457	}
1458
1459	MachineBasicBlock *
1460	MipsTargetLowering::emitAtomicCmpSwapPartword(MachineInstr *MI,
1461	MachineBasicBlock *BB,
1462	unsigned Size) const {
1463	assert((Size == 1 \|\| Size == 2) &&(((Size == 1 \|\| Size == 2) && "Unsupported size for EmitAtomicCmpSwapPartial." ) ? static_cast<void> (0) : __assert_fail ("(Size == 1 \|\| Size == 2) && \"Unsupported size for EmitAtomicCmpSwapPartial.\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MipsISelLowering.cpp" , 1464, __PRETTY_FUNCTION__))
1464	"Unsupported size for EmitAtomicCmpSwapPartial.")(((Size == 1 \|\| Size == 2) && "Unsupported size for EmitAtomicCmpSwapPartial." ) ? static_cast<void> (0) : __assert_fail ("(Size == 1 \|\| Size == 2) && \"Unsupported size for EmitAtomicCmpSwapPartial.\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MipsISelLowering.cpp" , 1464, __PRETTY_FUNCTION__));
1465
1466	MachineFunction *MF = BB->getParent();
1467	MachineRegisterInfo &RegInfo = MF->getRegInfo();
1468	const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1469	bool ArePtrs64bit = ABI.ArePtrs64bit();
1470	const TargetRegisterClass *RCp =
1471	getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32);
1472	const TargetInstrInfo *TII = Subtarget.getInstrInfo();
1473	DebugLoc DL = MI->getDebugLoc();
1474
1475	unsigned Dest = MI->getOperand(0).getReg();
1476	unsigned Ptr = MI->getOperand(1).getReg();
1477	unsigned CmpVal = MI->getOperand(2).getReg();
1478	unsigned NewVal = MI->getOperand(3).getReg();
1479
1480	unsigned AlignedAddr = RegInfo.createVirtualRegister(RCp);
1481	unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
1482	unsigned Mask = RegInfo.createVirtualRegister(RC);
1483	unsigned Mask2 = RegInfo.createVirtualRegister(RC);
1484	unsigned ShiftedCmpVal = RegInfo.createVirtualRegister(RC);
1485	unsigned OldVal = RegInfo.createVirtualRegister(RC);
1486	unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC);
1487	unsigned ShiftedNewVal = RegInfo.createVirtualRegister(RC);
1488	unsigned MaskLSB2 = RegInfo.createVirtualRegister(RCp);
1489	unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC);
1490	unsigned MaskUpper = RegInfo.createVirtualRegister(RC);
1491	unsigned MaskedCmpVal = RegInfo.createVirtualRegister(RC);
1492	unsigned MaskedNewVal = RegInfo.createVirtualRegister(RC);
1493	unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC);
1494	unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1495	unsigned SrlRes = RegInfo.createVirtualRegister(RC);
1496	unsigned Success = RegInfo.createVirtualRegister(RC);
1497
1498	// insert new blocks after the current block
1499	const BasicBlock *LLVM_BB = BB->getBasicBlock();
1500	MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1501	MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1502	MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1503	MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1504	MachineFunction::iterator It = ++BB->getIterator();
1505	MF->insert(It, loop1MBB);
1506	MF->insert(It, loop2MBB);
1507	MF->insert(It, sinkMBB);
1508	MF->insert(It, exitMBB);
1509
1510	// Transfer the remainder of BB and its successor edges to exitMBB.
1511	exitMBB->splice(exitMBB->begin(), BB,
1512	std::next(MachineBasicBlock::iterator(MI)), BB->end());
1513	exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1514
1515	BB->addSuccessor(loop1MBB);
1516	loop1MBB->addSuccessor(sinkMBB);
1517	loop1MBB->addSuccessor(loop2MBB);
1518	loop2MBB->addSuccessor(loop1MBB);
1519	loop2MBB->addSuccessor(sinkMBB);
1520	sinkMBB->addSuccessor(exitMBB);
1521
1522	// FIXME: computation of newval2 can be moved to loop2MBB.
1523	// thisMBB:
1524	// addiu masklsb2,$0,-4 # 0xfffffffc
1525	// and alignedaddr,ptr,masklsb2
1526	// andi ptrlsb2,ptr,3
1527	// xori ptrlsb2,ptrlsb2,3 # Only for BE
1528	// sll shiftamt,ptrlsb2,3
1529	// ori maskupper,$0,255 # 0xff
1530	// sll mask,maskupper,shiftamt
1531	// nor mask2,$0,mask
1532	// andi maskedcmpval,cmpval,255
1533	// sll shiftedcmpval,maskedcmpval,shiftamt
1534	// andi maskednewval,newval,255
1535	// sll shiftednewval,maskednewval,shiftamt
1536	int64_t MaskImm = (Size == 1) ? 255 : 65535;
1537	BuildMI(BB, DL, TII->get(ArePtrs64bit ? Mips::DADDiu : Mips::ADDiu), MaskLSB2)
1538	.addReg(ABI.GetNullPtr()).addImm(-4);
1539	BuildMI(BB, DL, TII->get(ArePtrs64bit ? Mips::AND64 : Mips::AND), AlignedAddr)
1540	.addReg(Ptr).addReg(MaskLSB2);
1541	BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2)
1542	.addReg(Ptr, 0, ArePtrs64bit ? Mips::sub_32 : 0).addImm(3);
1543	if (Subtarget.isLittle()) {
1544	BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1545	} else {
1546	unsigned Off = RegInfo.createVirtualRegister(RC);
1547	BuildMI(BB, DL, TII->get(Mips::XORi), Off)
1548	.addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2);
1549	BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
1550	}
1551	BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper)
1552	.addReg(Mips::ZERO).addImm(MaskImm);
1553	BuildMI(BB, DL, TII->get(Mips::SLLV), Mask)
1554	.addReg(MaskUpper).addReg(ShiftAmt);
1555	BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
1556	BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedCmpVal)
1557	.addReg(CmpVal).addImm(MaskImm);
1558	BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedCmpVal)
1559	.addReg(MaskedCmpVal).addReg(ShiftAmt);
1560	BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedNewVal)
1561	.addReg(NewVal).addImm(MaskImm);
1562	BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedNewVal)
1563	.addReg(MaskedNewVal).addReg(ShiftAmt);
1564
1565	// loop1MBB:
1566	// ll oldval,0(alginedaddr)
1567	// and maskedoldval0,oldval,mask
1568	// bne maskedoldval0,shiftedcmpval,sinkMBB
1569	BB = loop1MBB;
1570	unsigned LL = isMicroMips ? Mips::LL_MM : Mips::LL;
1571	BuildMI(BB, DL, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0);
1572	BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal0)
1573	.addReg(OldVal).addReg(Mask);
1574	BuildMI(BB, DL, TII->get(Mips::BNE))
1575	.addReg(MaskedOldVal0).addReg(ShiftedCmpVal).addMBB(sinkMBB);
1576
1577	// loop2MBB:
1578	// and maskedoldval1,oldval,mask2
1579	// or storeval,maskedoldval1,shiftednewval
1580	// sc success,storeval,0(alignedaddr)
1581	// beq success,$0,loop1MBB
1582	BB = loop2MBB;
1583	BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal1)
1584	.addReg(OldVal).addReg(Mask2);
1585	BuildMI(BB, DL, TII->get(Mips::OR), StoreVal)
1586	.addReg(MaskedOldVal1).addReg(ShiftedNewVal);
1587	unsigned SC = isMicroMips ? Mips::SC_MM : Mips::SC;
1588	BuildMI(BB, DL, TII->get(SC), Success)
1589	.addReg(StoreVal).addReg(AlignedAddr).addImm(0);
1590	BuildMI(BB, DL, TII->get(Mips::BEQ))
1591	.addReg(Success).addReg(Mips::ZERO).addMBB(loop1MBB);
1592
1593	// sinkMBB:
1594	// srl srlres,maskedoldval0,shiftamt
1595	// sign_extend dest,srlres
1596	BB = sinkMBB;
1597
1598	BuildMI(BB, DL, TII->get(Mips::SRLV), SrlRes)
1599	.addReg(MaskedOldVal0).addReg(ShiftAmt);
1600	BB = emitSignExtendToI32InReg(MI, BB, Size, Dest, SrlRes);
	Value stored to 'BB' is never read
1601
1602	MI->eraseFromParent(); // The instruction is gone now.
1603
1604	return exitMBB;
1605	}
1606
1607	MachineBasicBlock MipsTargetLowering::emitSEL_D(MachineInstr MI,
1608	MachineBasicBlock *BB) const {
1609	MachineFunction *MF = BB->getParent();
1610	const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
1611	const TargetInstrInfo *TII = Subtarget.getInstrInfo();
1612	MachineRegisterInfo &RegInfo = MF->getRegInfo();
1613	DebugLoc DL = MI->getDebugLoc();
1614	MachineBasicBlock::iterator II(MI);
1615
1616	unsigned Fc = MI->getOperand(1).getReg();
1617	const auto &FGR64RegClass = TRI->getRegClass(Mips::FGR64RegClassID);
1618
1619	unsigned Fc2 = RegInfo.createVirtualRegister(FGR64RegClass);
1620
1621	BuildMI(*BB, II, DL, TII->get(Mips::SUBREG_TO_REG), Fc2)
1622	.addImm(0)
1623	.addReg(Fc)
1624	.addImm(Mips::sub_lo);
1625
1626	// We don't erase the original instruction, we just replace the condition
1627	// register with the 64-bit super-register.
1628	MI->getOperand(1).setReg(Fc2);
1629
1630	return BB;
1631	}
1632
1633	//===----------------------------------------------------------------------===//
1634	// Misc Lower Operation implementation
1635	//===----------------------------------------------------------------------===//
1636	SDValue MipsTargetLowering::lowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
1637	SDValue Chain = Op.getOperand(0);
1638	SDValue Table = Op.getOperand(1);
1639	SDValue Index = Op.getOperand(2);
1640	SDLoc DL(Op);
1641	auto &TD = DAG.getDataLayout();
1642	EVT PTy = getPointerTy(TD);
1643	unsigned EntrySize =
1644	DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(TD);
1645
1646	Index = DAG.getNode(ISD::MUL, DL, PTy, Index,
1647	DAG.getConstant(EntrySize, DL, PTy));
1648	SDValue Addr = DAG.getNode(ISD::ADD, DL, PTy, Index, Table);
1649
1650	EVT MemVT = EVT::getIntegerVT(DAG.getContext(), EntrySize 8);
1651	Addr =
1652	DAG.getExtLoad(ISD::SEXTLOAD, DL, PTy, Chain, Addr,
1653	MachinePointerInfo::getJumpTable(DAG.getMachineFunction()),
1654	MemVT, false, false, false, 0);
1655	Chain = Addr.getValue(1);
1656
1657	if ((getTargetMachine().getRelocationModel() == Reloc::PIC_) \|\| ABI.IsN64()) {
1658	// For PIC, the sequence is:
1659	// BRIND(load(Jumptable + index) + RelocBase)
1660	// RelocBase can be JumpTable, GOT or some sort of global base.
1661	Addr = DAG.getNode(ISD::ADD, DL, PTy, Addr,
1662	getPICJumpTableRelocBase(Table, DAG));
1663	}
1664
1665	return DAG.getNode(ISD::BRIND, DL, MVT::Other, Chain, Addr);
1666	}
1667
1668	SDValue MipsTargetLowering::lowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
1669	// The first operand is the chain, the second is the condition, the third is
1670	// the block to branch to if the condition is true.
1671	SDValue Chain = Op.getOperand(0);
1672	SDValue Dest = Op.getOperand(2);
1673	SDLoc DL(Op);
1674
1675	assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6())((!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6( )) ? static_cast<void> (0) : __assert_fail ("!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6()" , "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MipsISelLowering.cpp" , 1675, __PRETTY_FUNCTION__));
1676	SDValue CondRes = createFPCmp(DAG, Op.getOperand(1));
1677
1678	// Return if flag is not set by a floating point comparison.
1679	if (CondRes.getOpcode() != MipsISD::FPCmp)
1680	return Op;
1681
1682	SDValue CCNode = CondRes.getOperand(2);
1683	Mips::CondCode CC =
1684	(Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue();
1685	unsigned Opc = invertFPCondCodeUser(CC) ? Mips::BRANCH_F : Mips::BRANCH_T;
1686	SDValue BrCode = DAG.getConstant(Opc, DL, MVT::i32);
1687	SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32);
1688	return DAG.getNode(MipsISD::FPBrcond, DL, Op.getValueType(), Chain, BrCode,
1689	FCC0, Dest, CondRes);
1690	}
1691
1692	SDValue MipsTargetLowering::
1693	lowerSELECT(SDValue Op, SelectionDAG &DAG) const
1694	{
1695	assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6())((!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6( )) ? static_cast<void> (0) : __assert_fail ("!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6()" , "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MipsISelLowering.cpp" , 1695, __PRETTY_FUNCTION__));
1696	SDValue Cond = createFPCmp(DAG, Op.getOperand(0));
1697
1698	// Return if flag is not set by a floating point comparison.
1699	if (Cond.getOpcode() != MipsISD::FPCmp)
1700	return Op;
1701
1702	return createCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2),
1703	SDLoc(Op));
1704	}
1705
1706	SDValue MipsTargetLowering::lowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1707	assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6())((!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6( )) ? static_cast<void> (0) : __assert_fail ("!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6()" , "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MipsISelLowering.cpp" , 1707, __PRETTY_FUNCTION__));
1708	SDValue Cond = createFPCmp(DAG, Op);
1709
1710	assert(Cond.getOpcode() == MipsISD::FPCmp &&((Cond.getOpcode() == MipsISD::FPCmp && "Floating point operand expected." ) ? static_cast<void> (0) : __assert_fail ("Cond.getOpcode() == MipsISD::FPCmp && \"Floating point operand expected.\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MipsISelLowering.cpp" , 1711, __PRETTY_FUNCTION__))
1711	"Floating point operand expected.")((Cond.getOpcode() == MipsISD::FPCmp && "Floating point operand expected." ) ? static_cast<void> (0) : __assert_fail ("Cond.getOpcode() == MipsISD::FPCmp && \"Floating point operand expected.\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MipsISelLowering.cpp" , 1711, __PRETTY_FUNCTION__));
1712
1713	SDLoc DL(Op);
1714	SDValue True = DAG.getConstant(1, DL, MVT::i32);
1715	SDValue False = DAG.getConstant(0, DL, MVT::i32);
1716
1717	return createCMovFP(DAG, Cond, True, False, DL);
1718	}
1719
1720	SDValue MipsTargetLowering::lowerGlobalAddress(SDValue Op,
1721	SelectionDAG &DAG) const {
1722	EVT Ty = Op.getValueType();
1723	GlobalAddressSDNode *N = cast<GlobalAddressSDNode>(Op);
1724	const GlobalValue *GV = N->getGlobal();
1725
1726	if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !ABI.IsN64()) {
1727	const MipsTargetObjectFile *TLOF =
1728	static_cast<const MipsTargetObjectFile *>(
1729	getTargetMachine().getObjFileLowering());
1730	if (TLOF->IsGlobalInSmallSection(GV, getTargetMachine()))
1731	// %gp_rel relocation
1732	return getAddrGPRel(N, SDLoc(N), Ty, DAG);
1733
1734	// %hi/%lo relocation
1735	return getAddrNonPIC(N, SDLoc(N), Ty, DAG);
1736	}
1737
1738	if (GV->hasInternalLinkage() \|\| (GV->hasLocalLinkage() && !isa<Function>(GV)))
1739	return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() \|\| ABI.IsN64());
1740
1741	if (LargeGOT)
1742	return getAddrGlobalLargeGOT(
1743	N, SDLoc(N), Ty, DAG, MipsII::MO_GOT_HI16, MipsII::MO_GOT_LO16,
1744	DAG.getEntryNode(),
1745	MachinePointerInfo::getGOT(DAG.getMachineFunction()));
1746
1747	return getAddrGlobal(
1748	N, SDLoc(N), Ty, DAG,
1749	(ABI.IsN32() \|\| ABI.IsN64()) ? MipsII::MO_GOT_DISP : MipsII::MO_GOT,
1750	DAG.getEntryNode(), MachinePointerInfo::getGOT(DAG.getMachineFunction()));
1751	}
1752
1753	SDValue MipsTargetLowering::lowerBlockAddress(SDValue Op,
1754	SelectionDAG &DAG) const {
1755	BlockAddressSDNode *N = cast<BlockAddressSDNode>(Op);
1756	EVT Ty = Op.getValueType();
1757
1758	if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !ABI.IsN64())
1759	return getAddrNonPIC(N, SDLoc(N), Ty, DAG);
1760
1761	return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() \|\| ABI.IsN64());
1762	}
1763
1764	SDValue MipsTargetLowering::
1765	lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
1766	{
1767	// If the relocation model is PIC, use the General Dynamic TLS Model or
1768	// Local Dynamic TLS model, otherwise use the Initial Exec or
1769	// Local Exec TLS Model.
1770
1771	GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1772	if (DAG.getTarget().Options.EmulatedTLS)
1773	return LowerToTLSEmulatedModel(GA, DAG);
1774
1775	SDLoc DL(GA);
1776	const GlobalValue *GV = GA->getGlobal();
1777	EVT PtrVT = getPointerTy(DAG.getDataLayout());
1778
1779	TLSModel::Model model = getTargetMachine().getTLSModel(GV);
1780
1781	if (model == TLSModel::GeneralDynamic \|\| model == TLSModel::LocalDynamic) {
1782	// General Dynamic and Local Dynamic TLS Model.
1783	unsigned Flag = (model == TLSModel::LocalDynamic) ? MipsII::MO_TLSLDM
1784	: MipsII::MO_TLSGD;
1785
1786	SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, Flag);
1787	SDValue Argument = DAG.getNode(MipsISD::Wrapper, DL, PtrVT,
1788	getGlobalReg(DAG, PtrVT), TGA);
1789	unsigned PtrSize = PtrVT.getSizeInBits();
1790	IntegerType PtrTy = Type::getIntNTy(DAG.getContext(), PtrSize);
1791
1792	SDValue TlsGetAddr = DAG.getExternalSymbol("__tls_get_addr", PtrVT);
1793
1794	ArgListTy Args;
1795	ArgListEntry Entry;
1796	Entry.Node = Argument;
1797	Entry.Ty = PtrTy;
1798	Args.push_back(Entry);
1799
1800	TargetLowering::CallLoweringInfo CLI(DAG);
1801	CLI.setDebugLoc(DL).setChain(DAG.getEntryNode())
1802	.setCallee(CallingConv::C, PtrTy, TlsGetAddr, std::move(Args), 0);
1803	std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
1804
1805	SDValue Ret = CallResult.first;
1806
1807	if (model != TLSModel::LocalDynamic)
1808	return Ret;
1809
1810	SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
1811	MipsII::MO_DTPREL_HI);
1812	SDValue Hi = DAG.getNode(MipsISD::Hi, DL, PtrVT, TGAHi);
1813	SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
1814	MipsII::MO_DTPREL_LO);
1815	SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo);
1816	SDValue Add = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Ret);
1817	return DAG.getNode(ISD::ADD, DL, PtrVT, Add, Lo);
1818	}
1819
1820	SDValue Offset;
1821	if (model == TLSModel::InitialExec) {
1822	// Initial Exec TLS Model
1823	SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
1824	MipsII::MO_GOTTPREL);
1825	TGA = DAG.getNode(MipsISD::Wrapper, DL, PtrVT, getGlobalReg(DAG, PtrVT),
1826	TGA);
1827	Offset = DAG.getLoad(PtrVT, DL,
1828	DAG.getEntryNode(), TGA, MachinePointerInfo(),
1829	false, false, false, 0);
1830	} else {
1831	// Local Exec TLS Model
1832	assert(model == TLSModel::LocalExec)((model == TLSModel::LocalExec) ? static_cast<void> (0) : __assert_fail ("model == TLSModel::LocalExec", "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MipsISelLowering.cpp" , 1832, __PRETTY_FUNCTION__));
1833	SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
1834	MipsII::MO_TPREL_HI);
1835	SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
1836	MipsII::MO_TPREL_LO);
1837	SDValue Hi = DAG.getNode(MipsISD::Hi, DL, PtrVT, TGAHi);
1838	SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo);
1839	Offset = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1840	}
1841
1842	SDValue ThreadPointer = DAG.getNode(MipsISD::ThreadPointer, DL, PtrVT);
1843	return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadPointer, Offset);
1844	}
1845
1846	SDValue MipsTargetLowering::
1847	lowerJumpTable(SDValue Op, SelectionDAG &DAG) const
1848	{
1849	JumpTableSDNode *N = cast<JumpTableSDNode>(Op);
1850	EVT Ty = Op.getValueType();
1851
1852	if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !ABI.IsN64())
1853	return getAddrNonPIC(N, SDLoc(N), Ty, DAG);
1854
1855	return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() \|\| ABI.IsN64());
1856	}
1857
1858	SDValue MipsTargetLowering::
1859	lowerConstantPool(SDValue Op, SelectionDAG &DAG) const
1860	{
1861	ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
1862	EVT Ty = Op.getValueType();
1863
1864	if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !ABI.IsN64()) {
1865	const MipsTargetObjectFile *TLOF =
1866	static_cast<const MipsTargetObjectFile *>(
1867	getTargetMachine().getObjFileLowering());
1868
1869	if (TLOF->IsConstantInSmallSection(DAG.getDataLayout(), N->getConstVal(),
1870	getTargetMachine()))
1871	// %gp_rel relocation
1872	return getAddrGPRel(N, SDLoc(N), Ty, DAG);
1873
1874	return getAddrNonPIC(N, SDLoc(N), Ty, DAG);
1875	}
1876
1877	return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() \|\| ABI.IsN64());
1878	}
1879
1880	SDValue MipsTargetLowering::lowerVASTART(SDValue Op, SelectionDAG &DAG) const {
1881	MachineFunction &MF = DAG.getMachineFunction();
1882	MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
1883
1884	SDLoc DL(Op);
1885	SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
1886	getPointerTy(MF.getDataLayout()));
1887
1888	// vastart just stores the address of the VarArgsFrameIndex slot into the
1889	// memory location argument.
1890	const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1891	return DAG.getStore(Op.getOperand(0), DL, FI, Op.getOperand(1),
1892	MachinePointerInfo(SV), false, false, 0);
1893	}
1894
1895	SDValue MipsTargetLowering::lowerVAARG(SDValue Op, SelectionDAG &DAG) const {
1896	SDNode *Node = Op.getNode();
1897	EVT VT = Node->getValueType(0);
1898	SDValue Chain = Node->getOperand(0);
1899	SDValue VAListPtr = Node->getOperand(1);
1900	unsigned Align = Node->getConstantOperandVal(3);
1901	const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
1902	SDLoc DL(Node);
1903	unsigned ArgSlotSizeInBytes = (ABI.IsN32() \|\| ABI.IsN64()) ? 8 : 4;
1904
1905	SDValue VAListLoad =
1906	DAG.getLoad(getPointerTy(DAG.getDataLayout()), DL, Chain, VAListPtr,
1907	MachinePointerInfo(SV), false, false, false, 0);
1908	SDValue VAList = VAListLoad;
1909
1910	// Re-align the pointer if necessary.
1911	// It should only ever be necessary for 64-bit types on O32 since the minimum
1912	// argument alignment is the same as the maximum type alignment for N32/N64.
1913	//
1914	// FIXME: We currently align too often. The code generator doesn't notice
1915	// when the pointer is still aligned from the last va_arg (or pair of
1916	// va_args for the i64 on O32 case).
1917	if (Align > getMinStackArgumentAlignment()) {
1918	assert(((Align & (Align-1)) == 0) && "Expected Align to be a power of 2")((((Align & (Align-1)) == 0) && "Expected Align to be a power of 2" ) ? static_cast<void> (0) : __assert_fail ("((Align & (Align-1)) == 0) && \"Expected Align to be a power of 2\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MipsISelLowering.cpp" , 1918, __PRETTY_FUNCTION__));
1919
1920	VAList = DAG.getNode(ISD::ADD, DL, VAList.getValueType(), VAList,
1921	DAG.getConstant(Align - 1, DL, VAList.getValueType()));
1922
1923	VAList = DAG.getNode(ISD::AND, DL, VAList.getValueType(), VAList,
1924	DAG.getConstant(-(int64_t)Align, DL,
1925	VAList.getValueType()));
1926	}
1927
1928	// Increment the pointer, VAList, to the next vaarg.
1929	auto &TD = DAG.getDataLayout();
1930	unsigned ArgSizeInBytes =
1931	TD.getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext()));
1932	SDValue Tmp3 =
1933	DAG.getNode(ISD::ADD, DL, VAList.getValueType(), VAList,
1934	DAG.getConstant(alignTo(ArgSizeInBytes, ArgSlotSizeInBytes),
1935	DL, VAList.getValueType()));
1936	// Store the incremented VAList to the legalized pointer
1937	Chain = DAG.getStore(VAListLoad.getValue(1), DL, Tmp3, VAListPtr,
1938	MachinePointerInfo(SV), false, false, 0);
1939
1940	// In big-endian mode we must adjust the pointer when the load size is smaller
1941	// than the argument slot size. We must also reduce the known alignment to
1942	// match. For example in the N64 ABI, we must add 4 bytes to the offset to get
1943	// the correct half of the slot, and reduce the alignment from 8 (slot
1944	// alignment) down to 4 (type alignment).
1945	if (!Subtarget.isLittle() && ArgSizeInBytes < ArgSlotSizeInBytes) {
1946	unsigned Adjustment = ArgSlotSizeInBytes - ArgSizeInBytes;
1947	VAList = DAG.getNode(ISD::ADD, DL, VAListPtr.getValueType(), VAList,
1948	DAG.getIntPtrConstant(Adjustment, DL));
1949	}
1950	// Load the actual argument out of the pointer VAList
1951	return DAG.getLoad(VT, DL, Chain, VAList, MachinePointerInfo(), false, false,
1952	false, 0);
1953	}
1954
1955	static SDValue lowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG,
1956	bool HasExtractInsert) {
1957	EVT TyX = Op.getOperand(0).getValueType();
1958	EVT TyY = Op.getOperand(1).getValueType();
1959	SDLoc DL(Op);
1960	SDValue Const1 = DAG.getConstant(1, DL, MVT::i32);
1961	SDValue Const31 = DAG.getConstant(31, DL, MVT::i32);
1962	SDValue Res;
1963
1964	// If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it
1965	// to i32.
1966	SDValue X = (TyX == MVT::f32) ?
1967	DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) :
1968	DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0),
1969	Const1);
1970	SDValue Y = (TyY == MVT::f32) ?
1971	DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(1)) :
1972	DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(1),
1973	Const1);
1974
1975	if (HasExtractInsert) {
1976	// ext E, Y, 31, 1 ; extract bit31 of Y
1977	// ins X, E, 31, 1 ; insert extracted bit at bit31 of X
1978	SDValue E = DAG.getNode(MipsISD::Ext, DL, MVT::i32, Y, Const31, Const1);
1979	Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, E, Const31, Const1, X);
1980	} else {
1981	// sll SllX, X, 1
1982	// srl SrlX, SllX, 1
1983	// srl SrlY, Y, 31
1984	// sll SllY, SrlX, 31
1985	// or Or, SrlX, SllY
1986	SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1);
1987	SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1);
1988	SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31);
1989	SDValue SllY = DAG.getNode(ISD::SHL, DL, MVT::i32, SrlY, Const31);
1990	Res = DAG.getNode(ISD::OR, DL, MVT::i32, SrlX, SllY);
1991	}
1992
1993	if (TyX == MVT::f32)
1994	return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Res);
1995
1996	SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
1997	Op.getOperand(0),
1998	DAG.getConstant(0, DL, MVT::i32));
1999	return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res);
2000	}
2001
2002	static SDValue lowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG,
2003	bool HasExtractInsert) {
2004	unsigned WidthX = Op.getOperand(0).getValueSizeInBits();
2005	unsigned WidthY = Op.getOperand(1).getValueSizeInBits();
2006	EVT TyX = MVT::getIntegerVT(WidthX), TyY = MVT::getIntegerVT(WidthY);
2007	SDLoc DL(Op);
2008	SDValue Const1 = DAG.getConstant(1, DL, MVT::i32);
2009
2010	// Bitcast to integer nodes.
2011	SDValue X = DAG.getNode(ISD::BITCAST, DL, TyX, Op.getOperand(0));
2012	SDValue Y = DAG.getNode(ISD::BITCAST, DL, TyY, Op.getOperand(1));
2013
2014	if (HasExtractInsert) {
2015	// ext E, Y, width(Y) - 1, 1 ; extract bit width(Y)-1 of Y
2016	// ins X, E, width(X) - 1, 1 ; insert extracted bit at bit width(X)-1 of X
2017	SDValue E = DAG.getNode(MipsISD::Ext, DL, TyY, Y,
2018	DAG.getConstant(WidthY - 1, DL, MVT::i32), Const1);
2019
2020	if (WidthX > WidthY)
2021	E = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, E);
2022	else if (WidthY > WidthX)
2023	E = DAG.getNode(ISD::TRUNCATE, DL, TyX, E);
2024
2025	SDValue I = DAG.getNode(MipsISD::Ins, DL, TyX, E,
2026	DAG.getConstant(WidthX - 1, DL, MVT::i32), Const1,
2027	X);
2028	return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), I);
2029	}
2030
2031	// (d)sll SllX, X, 1
2032	// (d)srl SrlX, SllX, 1
2033	// (d)srl SrlY, Y, width(Y)-1
2034	// (d)sll SllY, SrlX, width(Y)-1
2035	// or Or, SrlX, SllY
2036	SDValue SllX = DAG.getNode(ISD::SHL, DL, TyX, X, Const1);
2037	SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1);
2038	SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y,
2039	DAG.getConstant(WidthY - 1, DL, MVT::i32));
2040
2041	if (WidthX > WidthY)
2042	SrlY = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, SrlY);
2043	else if (WidthY > WidthX)
2044	SrlY = DAG.getNode(ISD::TRUNCATE, DL, TyX, SrlY);
2045
2046	SDValue SllY = DAG.getNode(ISD::SHL, DL, TyX, SrlY,
2047	DAG.getConstant(WidthX - 1, DL, MVT::i32));
2048	SDValue Or = DAG.getNode(ISD::OR, DL, TyX, SrlX, SllY);
2049	return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Or);
2050	}
2051
2052	SDValue
2053	MipsTargetLowering::lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
2054	if (Subtarget.isGP64bit())
2055	return lowerFCOPYSIGN64(Op, DAG, Subtarget.hasExtractInsert());
2056
2057	return lowerFCOPYSIGN32(Op, DAG, Subtarget.hasExtractInsert());
2058	}
2059
2060	SDValue MipsTargetLowering::
2061	lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
2062	// check the depth
2063	assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) &&(((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue () == 0) && "Frame address can only be determined for current frame." ) ? static_cast<void> (0) : __assert_fail ("(cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) && \"Frame address can only be determined for current frame.\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MipsISelLowering.cpp" , 2064, __PRETTY_FUNCTION__))
2064	"Frame address can only be determined for current frame.")(((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue () == 0) && "Frame address can only be determined for current frame." ) ? static_cast<void> (0) : __assert_fail ("(cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) && \"Frame address can only be determined for current frame.\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MipsISelLowering.cpp" , 2064, __PRETTY_FUNCTION__));
2065
2066	MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2067	MFI->setFrameAddressIsTaken(true);
2068	EVT VT = Op.getValueType();
2069	SDLoc DL(Op);
2070	SDValue FrameAddr = DAG.getCopyFromReg(
2071	DAG.getEntryNode(), DL, ABI.IsN64() ? Mips::FP_64 : Mips::FP, VT);
2072	return FrameAddr;
2073	}
2074
2075	SDValue MipsTargetLowering::lowerRETURNADDR(SDValue Op,
2076	SelectionDAG &DAG) const {
2077	if (verifyReturnAddressArgumentIsConstant(Op, DAG))
2078	return SDValue();
2079
2080	// check the depth
2081	assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) &&(((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue () == 0) && "Return address can be determined only for current frame." ) ? static_cast<void> (0) : __assert_fail ("(cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) && \"Return address can be determined only for current frame.\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MipsISelLowering.cpp" , 2082, __PRETTY_FUNCTION__))
2082	"Return address can be determined only for current frame.")(((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue () == 0) && "Return address can be determined only for current frame." ) ? static_cast<void> (0) : __assert_fail ("(cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) && \"Return address can be determined only for current frame.\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MipsISelLowering.cpp" , 2082, __PRETTY_FUNCTION__));
2083
2084	MachineFunction &MF = DAG.getMachineFunction();
2085	MachineFrameInfo *MFI = MF.getFrameInfo();
2086	MVT VT = Op.getSimpleValueType();
2087	unsigned RA = ABI.IsN64() ? Mips::RA_64 : Mips::RA;
2088	MFI->setReturnAddressIsTaken(true);
2089
2090	// Return RA, which contains the return address. Mark it an implicit live-in.
2091	unsigned Reg = MF.addLiveIn(RA, getRegClassFor(VT));
2092	return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(Op), Reg, VT);
2093	}
2094
2095	// An EH_RETURN is the result of lowering llvm.eh.return which in turn is
2096	// generated from __builtin_eh_return (offset, handler)
2097	// The effect of this is to adjust the stack pointer by "offset"
2098	// and then branch to "handler".
2099	SDValue MipsTargetLowering::lowerEH_RETURN(SDValue Op, SelectionDAG &DAG)
2100	const {
2101	MachineFunction &MF = DAG.getMachineFunction();
2102	MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
2103
2104	MipsFI->setCallsEhReturn();
2105	SDValue Chain = Op.getOperand(0);
2106	SDValue Offset = Op.getOperand(1);
2107	SDValue Handler = Op.getOperand(2);
2108	SDLoc DL(Op);
2109	EVT Ty = ABI.IsN64() ? MVT::i64 : MVT::i32;
2110
2111	// Store stack offset in V1, store jump target in V0. Glue CopyToReg and
2112	// EH_RETURN nodes, so that instructions are emitted back-to-back.
2113	unsigned OffsetReg = ABI.IsN64() ? Mips::V1_64 : Mips::V1;
2114	unsigned AddrReg = ABI.IsN64() ? Mips::V0_64 : Mips::V0;
2115	Chain = DAG.getCopyToReg(Chain, DL, OffsetReg, Offset, SDValue());
2116	Chain = DAG.getCopyToReg(Chain, DL, AddrReg, Handler, Chain.getValue(1));
2117	return DAG.getNode(MipsISD::EH_RETURN, DL, MVT::Other, Chain,
2118	DAG.getRegister(OffsetReg, Ty),
2119	DAG.getRegister(AddrReg, getPointerTy(MF.getDataLayout())),
2120	Chain.getValue(1));
2121	}
2122
2123	SDValue MipsTargetLowering::lowerATOMIC_FENCE(SDValue Op,
2124	SelectionDAG &DAG) const {
2125	// FIXME: Need pseudo-fence for 'singlethread' fences
2126	// FIXME: Set SType for weaker fences where supported/appropriate.
2127	unsigned SType = 0;
2128	SDLoc DL(Op);
2129	return DAG.getNode(MipsISD::Sync, DL, MVT::Other, Op.getOperand(0),
2130	DAG.getConstant(SType, DL, MVT::i32));
2131	}
2132
2133	SDValue MipsTargetLowering::lowerShiftLeftParts(SDValue Op,
2134	SelectionDAG &DAG) const {
2135	SDLoc DL(Op);
2136	MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32;
2137
2138	SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);
2139	SDValue Shamt = Op.getOperand(2);
2140	// if shamt < (VT.bits):
2141	// lo = (shl lo, shamt)
2142	// hi = (or (shl hi, shamt) (srl (srl lo, 1), ~shamt))
2143	// else:
2144	// lo = 0
2145	// hi = (shl lo, shamt[4:0])
2146	SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
2147	DAG.getConstant(-1, DL, MVT::i32));
2148	SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, VT, Lo,
2149	DAG.getConstant(1, DL, VT));
2150	SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, ShiftRight1Lo, Not);
2151	SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, Hi, Shamt);
2152	SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo);
2153	SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt);
2154	SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
2155	DAG.getConstant(VT.getSizeInBits(), DL, MVT::i32));
2156	Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond,
2157	DAG.getConstant(0, DL, VT), ShiftLeftLo);
2158	Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftLeftLo, Or);
2159
2160	SDValue Ops[2] = {Lo, Hi};
2161	return DAG.getMergeValues(Ops, DL);
2162	}
2163
2164	SDValue MipsTargetLowering::lowerShiftRightParts(SDValue Op, SelectionDAG &DAG,
2165	bool IsSRA) const {
2166	SDLoc DL(Op);
2167	SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);
2168	SDValue Shamt = Op.getOperand(2);
2169	MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32;
2170
2171	// if shamt < (VT.bits):
2172	// lo = (or (shl (shl hi, 1), ~shamt) (srl lo, shamt))
2173	// if isSRA:
2174	// hi = (sra hi, shamt)
2175	// else:
2176	// hi = (srl hi, shamt)
2177	// else:
2178	// if isSRA:
2179	// lo = (sra hi, shamt[4:0])
2180	// hi = (sra hi, 31)
2181	// else:
2182	// lo = (srl hi, shamt[4:0])
2183	// hi = 0
2184	SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
2185	DAG.getConstant(-1, DL, MVT::i32));
2186	SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, VT, Hi,
2187	DAG.getConstant(1, DL, VT));
2188	SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, ShiftLeft1Hi, Not);
2189	SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, Lo, Shamt);
2190	SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo);
2191	SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL,
2192	DL, VT, Hi, Shamt);
2193	SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
2194	DAG.getConstant(VT.getSizeInBits(), DL, MVT::i32));
2195	SDValue Ext = DAG.getNode(ISD::SRA, DL, VT, Hi,
2196	DAG.getConstant(VT.getSizeInBits() - 1, DL, VT));
2197	Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftRightHi, Or);
2198	Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond,
2199	IsSRA ? Ext : DAG.getConstant(0, DL, VT), ShiftRightHi);
2200
2201	SDValue Ops[2] = {Lo, Hi};
2202	return DAG.getMergeValues(Ops, DL);
2203	}
2204
2205	static SDValue createLoadLR(unsigned Opc, SelectionDAG &DAG, LoadSDNode *LD,
2206	SDValue Chain, SDValue Src, unsigned Offset) {
2207	SDValue Ptr = LD->getBasePtr();
2208	EVT VT = LD->getValueType(0), MemVT = LD->getMemoryVT();
2209	EVT BasePtrVT = Ptr.getValueType();
2210	SDLoc DL(LD);
2211	SDVTList VTList = DAG.getVTList(VT, MVT::Other);
2212
2213	if (Offset)
2214	Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr,
2215	DAG.getConstant(Offset, DL, BasePtrVT));
2216
2217	SDValue Ops[] = { Chain, Ptr, Src };
2218	return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT,
2219	LD->getMemOperand());
2220	}
2221
2222	// Expand an unaligned 32 or 64-bit integer load node.
2223	SDValue MipsTargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const {
2224	LoadSDNode *LD = cast<LoadSDNode>(Op);
2225	EVT MemVT = LD->getMemoryVT();
2226
2227	if (Subtarget.systemSupportsUnalignedAccess())
2228	return Op;
2229
2230	// Return if load is aligned or if MemVT is neither i32 nor i64.
2231	if ((LD->getAlignment() >= MemVT.getSizeInBits() / 8) \|\|
2232	((MemVT != MVT::i32) && (MemVT != MVT::i64)))
2233	return SDValue();
2234
2235	bool IsLittle = Subtarget.isLittle();
2236	EVT VT = Op.getValueType();
2237	ISD::LoadExtType ExtType = LD->getExtensionType();
2238	SDValue Chain = LD->getChain(), Undef = DAG.getUNDEF(VT);
2239
2240	assert((VT == MVT::i32) \|\| (VT == MVT::i64))(((VT == MVT::i32) \|\| (VT == MVT::i64)) ? static_cast<void > (0) : __assert_fail ("(VT == MVT::i32) \|\| (VT == MVT::i64)" , "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MipsISelLowering.cpp" , 2240, __PRETTY_FUNCTION__));
2241
2242	// Expand
2243	// (set dst, (i64 (load baseptr)))
2244	// to
2245	// (set tmp, (ldl (add baseptr, 7), undef))
2246	// (set dst, (ldr baseptr, tmp))
2247	if ((VT == MVT::i64) && (ExtType == ISD::NON_EXTLOAD)) {
2248	SDValue LDL = createLoadLR(MipsISD::LDL, DAG, LD, Chain, Undef,
2249	IsLittle ? 7 : 0);
2250	return createLoadLR(MipsISD::LDR, DAG, LD, LDL.getValue(1), LDL,
2251	IsLittle ? 0 : 7);
2252	}
2253
2254	SDValue LWL = createLoadLR(MipsISD::LWL, DAG, LD, Chain, Undef,
2255	IsLittle ? 3 : 0);
2256	SDValue LWR = createLoadLR(MipsISD::LWR, DAG, LD, LWL.getValue(1), LWL,
2257	IsLittle ? 0 : 3);
2258
2259	// Expand
2260	// (set dst, (i32 (load baseptr))) or
2261	// (set dst, (i64 (sextload baseptr))) or
2262	// (set dst, (i64 (extload baseptr)))
2263	// to
2264	// (set tmp, (lwl (add baseptr, 3), undef))
2265	// (set dst, (lwr baseptr, tmp))
2266	if ((VT == MVT::i32) \|\| (ExtType == ISD::SEXTLOAD) \|\|
2267	(ExtType == ISD::EXTLOAD))
2268	return LWR;
2269
2270	assert((VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD))(((VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD)) ? static_cast <void> (0) : __assert_fail ("(VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD)" , "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MipsISelLowering.cpp" , 2270, __PRETTY_FUNCTION__));
2271
2272	// Expand
2273	// (set dst, (i64 (zextload baseptr)))
2274	// to
2275	// (set tmp0, (lwl (add baseptr, 3), undef))
2276	// (set tmp1, (lwr baseptr, tmp0))
2277	// (set tmp2, (shl tmp1, 32))
2278	// (set dst, (srl tmp2, 32))
2279	SDLoc DL(LD);
2280	SDValue Const32 = DAG.getConstant(32, DL, MVT::i32);
2281	SDValue SLL = DAG.getNode(ISD::SHL, DL, MVT::i64, LWR, Const32);
2282	SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32);
2283	SDValue Ops[] = { SRL, LWR.getValue(1) };
2284	return DAG.getMergeValues(Ops, DL);
2285	}
2286
2287	static SDValue createStoreLR(unsigned Opc, SelectionDAG &DAG, StoreSDNode *SD,
2288	SDValue Chain, unsigned Offset) {
2289	SDValue Ptr = SD->getBasePtr(), Value = SD->getValue();
2290	EVT MemVT = SD->getMemoryVT(), BasePtrVT = Ptr.getValueType();
2291	SDLoc DL(SD);
2292	SDVTList VTList = DAG.getVTList(MVT::Other);
2293
2294	if (Offset)
2295	Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr,
2296	DAG.getConstant(Offset, DL, BasePtrVT));
2297
2298	SDValue Ops[] = { Chain, Value, Ptr };
2299	return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT,
2300	SD->getMemOperand());
2301	}
2302
2303	// Expand an unaligned 32 or 64-bit integer store node.
2304	static SDValue lowerUnalignedIntStore(StoreSDNode *SD, SelectionDAG &DAG,
2305	bool IsLittle) {
2306	SDValue Value = SD->getValue(), Chain = SD->getChain();
2307	EVT VT = Value.getValueType();
2308
2309	// Expand
2310	// (store val, baseptr) or
2311	// (truncstore val, baseptr)
2312	// to
2313	// (swl val, (add baseptr, 3))
2314	// (swr val, baseptr)
2315	if ((VT == MVT::i32) \|\| SD->isTruncatingStore()) {
2316	SDValue SWL = createStoreLR(MipsISD::SWL, DAG, SD, Chain,
2317	IsLittle ? 3 : 0);
2318	return createStoreLR(MipsISD::SWR, DAG, SD, SWL, IsLittle ? 0 : 3);
2319	}
2320
2321	assert(VT == MVT::i64)((VT == MVT::i64) ? static_cast<void> (0) : __assert_fail ("VT == MVT::i64", "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MipsISelLowering.cpp" , 2321, __PRETTY_FUNCTION__));
2322
2323	// Expand
2324	// (store val, baseptr)
2325	// to
2326	// (sdl val, (add baseptr, 7))
2327	// (sdr val, baseptr)
2328	SDValue SDL = createStoreLR(MipsISD::SDL, DAG, SD, Chain, IsLittle ? 7 : 0);
2329	return createStoreLR(MipsISD::SDR, DAG, SD, SDL, IsLittle ? 0 : 7);
2330	}
2331
2332	// Lower (store (fp_to_sint $fp) $ptr) to (store (TruncIntFP $fp), $ptr).
2333	static SDValue lowerFP_TO_SINT_STORE(StoreSDNode *SD, SelectionDAG &DAG) {
2334	SDValue Val = SD->getValue();
2335
2336	if (Val.getOpcode() != ISD::FP_TO_SINT)
2337	return SDValue();
2338
2339	EVT FPTy = EVT::getFloatingPointVT(Val.getValueSizeInBits());
2340	SDValue Tr = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Val), FPTy,
2341	Val.getOperand(0));
2342
2343	return DAG.getStore(SD->getChain(), SDLoc(SD), Tr, SD->getBasePtr(),
2344	SD->getPointerInfo(), SD->isVolatile(),
2345	SD->isNonTemporal(), SD->getAlignment());
2346	}
2347
2348	SDValue MipsTargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const {
2349	StoreSDNode *SD = cast<StoreSDNode>(Op);
2350	EVT MemVT = SD->getMemoryVT();
2351
2352	// Lower unaligned integer stores.
2353	if (!Subtarget.systemSupportsUnalignedAccess() &&
2354	(SD->getAlignment() < MemVT.getSizeInBits() / 8) &&
2355	((MemVT == MVT::i32) \|\| (MemVT == MVT::i64)))
2356	return lowerUnalignedIntStore(SD, DAG, Subtarget.isLittle());
2357
2358	return lowerFP_TO_SINT_STORE(SD, DAG);
2359	}
2360
2361	SDValue MipsTargetLowering::lowerADD(SDValue Op, SelectionDAG &DAG) const {
2362	if (Op->getOperand(0).getOpcode() != ISD::FRAMEADDR
2363	\|\| cast<ConstantSDNode>
2364	(Op->getOperand(0).getOperand(0))->getZExtValue() != 0
2365	\|\| Op->getOperand(1).getOpcode() != ISD::FRAME_TO_ARGS_OFFSET)
2366	return SDValue();
2367
2368	// The pattern
2369	// (add (frameaddr 0), (frame_to_args_offset))
2370	// results from lowering llvm.eh.dwarf.cfa intrinsic. Transform it to
2371	// (add FrameObject, 0)
2372	// where FrameObject is a fixed StackObject with offset 0 which points to
2373	// the old stack pointer.
2374	MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2375	EVT ValTy = Op->getValueType(0);
2376	int FI = MFI->CreateFixedObject(Op.getValueSizeInBits() / 8, 0, false);
2377	SDValue InArgsAddr = DAG.getFrameIndex(FI, ValTy);
2378	SDLoc DL(Op);
2379	return DAG.getNode(ISD::ADD, DL, ValTy, InArgsAddr,
2380	DAG.getConstant(0, DL, ValTy));
2381	}
2382
2383	SDValue MipsTargetLowering::lowerFP_TO_SINT(SDValue Op,
2384	SelectionDAG &DAG) const {
2385	EVT FPTy = EVT::getFloatingPointVT(Op.getValueSizeInBits());
2386	SDValue Trunc = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Op), FPTy,
2387	Op.getOperand(0));
2388	return DAG.getNode(ISD::BITCAST, SDLoc(Op), Op.getValueType(), Trunc);
2389	}
2390
2391	//===----------------------------------------------------------------------===//
2392	// Calling Convention Implementation
2393	//===----------------------------------------------------------------------===//
2394
2395	//===----------------------------------------------------------------------===//
2396	// TODO: Implement a generic logic using tblgen that can support this.
2397	// Mips O32 ABI rules:
2398	// ---
2399	// i32 - Passed in A0, A1, A2, A3 and stack
2400	// f32 - Only passed in f32 registers if no int reg has been used yet to hold
2401	// an argument. Otherwise, passed in A1, A2, A3 and stack.
2402	// f64 - Only passed in two aliased f32 registers if no int reg has been used
2403	// yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is
2404	// not used, it must be shadowed. If only A3 is available, shadow it and
2405	// go to stack.
2406	//
2407	// For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack.
2408	//===----------------------------------------------------------------------===//
2409
2410	static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT,
2411	CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
2412	CCState &State, ArrayRef<MCPhysReg> F64Regs) {
2413	const MipsSubtarget &Subtarget = static_cast<const MipsSubtarget &>(
2414	State.getMachineFunction().getSubtarget());
2415
2416	static const MCPhysReg IntRegs[] = { Mips::A0, Mips::A1, Mips::A2, Mips::A3 };
2417	static const MCPhysReg F32Regs[] = { Mips::F12, Mips::F14 };
2418
2419	// Do not process byval args here.
2420	if (ArgFlags.isByVal())
2421	return true;
2422
2423	// Promote i8 and i16
2424	if (ArgFlags.isInReg() && !Subtarget.isLittle()) {
2425	if (LocVT == MVT::i8 \|\| LocVT == MVT::i16 \|\| LocVT == MVT::i32) {
2426	LocVT = MVT::i32;
2427	if (ArgFlags.isSExt())
2428	LocInfo = CCValAssign::SExtUpper;
2429	else if (ArgFlags.isZExt())
2430	LocInfo = CCValAssign::ZExtUpper;
2431	else
2432	LocInfo = CCValAssign::AExtUpper;
2433	}
2434	}
2435
2436	// Promote i8 and i16
2437	if (LocVT == MVT::i8 \|\| LocVT == MVT::i16) {
2438	LocVT = MVT::i32;
2439	if (ArgFlags.isSExt())
2440	LocInfo = CCValAssign::SExt;
2441	else if (ArgFlags.isZExt())
2442	LocInfo = CCValAssign::ZExt;
2443	else
2444	LocInfo = CCValAssign::AExt;
2445	}
2446
2447	unsigned Reg;
2448
2449	// f32 and f64 are allocated in A0, A1, A2, A3 when either of the following
2450	// is true: function is vararg, argument is 3rd or higher, there is previous
2451	// argument which is not f32 or f64.
2452	bool AllocateFloatsInIntReg = State.isVarArg() \|\| ValNo > 1 \|\|
2453	State.getFirstUnallocated(F32Regs) != ValNo;
2454	unsigned OrigAlign = ArgFlags.getOrigAlign();
2455	bool isI64 = (ValVT == MVT::i32 && OrigAlign == 8);
2456
2457	if (ValVT == MVT::i32 \|\| (ValVT == MVT::f32 && AllocateFloatsInIntReg)) {
2458	Reg = State.AllocateReg(IntRegs);
2459	// If this is the first part of an i64 arg,
2460	// the allocated register must be either A0 or A2.
2461	if (isI64 && (Reg == Mips::A1 \|\| Reg == Mips::A3))
2462	Reg = State.AllocateReg(IntRegs);
2463	LocVT = MVT::i32;
2464	} else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) {
2465	// Allocate int register and shadow next int register. If first
2466	// available register is Mips::A1 or Mips::A3, shadow it too.
2467	Reg = State.AllocateReg(IntRegs);
2468	if (Reg == Mips::A1 \|\| Reg == Mips::A3)
2469	Reg = State.AllocateReg(IntRegs);
2470	State.AllocateReg(IntRegs);
2471	LocVT = MVT::i32;
2472	} else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) {
2473	// we are guaranteed to find an available float register
2474	if (ValVT == MVT::f32) {
2475	Reg = State.AllocateReg(F32Regs);
2476	// Shadow int register
2477	State.AllocateReg(IntRegs);
2478	} else {
2479	Reg = State.AllocateReg(F64Regs);
2480	// Shadow int registers
2481	unsigned Reg2 = State.AllocateReg(IntRegs);
2482	if (Reg2 == Mips::A1 \|\| Reg2 == Mips::A3)
2483	State.AllocateReg(IntRegs);
2484	State.AllocateReg(IntRegs);
2485	}
2486	} else
2487	llvm_unreachable("Cannot handle this ValVT.")::llvm::llvm_unreachable_internal("Cannot handle this ValVT." , "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MipsISelLowering.cpp" , 2487);
2488
2489	if (!Reg) {
2490	unsigned Offset = State.AllocateStack(ValVT.getSizeInBits() >> 3,
2491	OrigAlign);
2492	State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
2493	} else
2494	State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2495
2496	return false;
2497	}
2498
2499	static bool CC_MipsO32_FP32(unsigned ValNo, MVT ValVT,
2500	MVT LocVT, CCValAssign::LocInfo LocInfo,
2501	ISD::ArgFlagsTy ArgFlags, CCState &State) {
2502	static const MCPhysReg F64Regs[] = { Mips::D6, Mips::D7 };
2503
2504	return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs);
2505	}
2506
2507	static bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT,
2508	MVT LocVT, CCValAssign::LocInfo LocInfo,
2509	ISD::ArgFlagsTy ArgFlags, CCState &State) {
2510	static const MCPhysReg F64Regs[] = { Mips::D12_64, Mips::D14_64 };
2511
2512	return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs);
2513	}
2514
2515	static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT,
2516	CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
2517	CCState &State) LLVM_ATTRIBUTE_UNUSED__attribute__((__unused__));
2518
2519	#include "MipsGenCallingConv.inc"
2520
2521	//===----------------------------------------------------------------------===//
2522	// Call Calling Convention Implementation
2523	//===----------------------------------------------------------------------===//
2524
2525	// Return next O32 integer argument register.
2526	static unsigned getNextIntArgReg(unsigned Reg) {
2527	assert((Reg == Mips::A0) \|\| (Reg == Mips::A2))(((Reg == Mips::A0) \|\| (Reg == Mips::A2)) ? static_cast<void > (0) : __assert_fail ("(Reg == Mips::A0) \|\| (Reg == Mips::A2)" , "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MipsISelLowering.cpp" , 2527, __PRETTY_FUNCTION__));
2528	return (Reg == Mips::A0) ? Mips::A1 : Mips::A3;
2529	}
2530
2531	SDValue
2532	MipsTargetLowering::passArgOnStack(SDValue StackPtr, unsigned Offset,
2533	SDValue Chain, SDValue Arg, SDLoc DL,
2534	bool IsTailCall, SelectionDAG &DAG) const {
2535	if (!IsTailCall) {
2536	SDValue PtrOff =
2537	DAG.getNode(ISD::ADD, DL, getPointerTy(DAG.getDataLayout()), StackPtr,
2538	DAG.getIntPtrConstant(Offset, DL));
2539	return DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo(), false,
2540	false, 0);
2541	}
2542
2543	MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2544	int FI = MFI->CreateFixedObject(Arg.getValueSizeInBits() / 8, Offset, false);
2545	SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
2546	return DAG.getStore(Chain, DL, Arg, FIN, MachinePointerInfo(),
2547	/isVolatile=/ true, false, 0);
2548	}
2549
2550	void MipsTargetLowering::
2551	getOpndList(SmallVectorImpl<SDValue> &Ops,
2552	std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
2553	bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
2554	bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee,
2555	SDValue Chain) const {
2556	// Insert node "GP copy globalreg" before call to function.
2557	//
2558	// R_MIPS_CALL* operators (emitted when non-internal functions are called
2559	// in PIC mode) allow symbols to be resolved via lazy binding.
2560	// The lazy binding stub requires GP to point to the GOT.
2561	// Note that we don't need GP to point to the GOT for indirect calls
2562	// (when R_MIPS_CALL* is not used for the call) because Mips linker generates
2563	// lazy binding stub for a function only when R_MIPS_CALL* are the only relocs
2564	// used for the function (that is, Mips linker doesn't generate lazy binding
2565	// stub for a function whose address is taken in the program).
2566	if (IsPICCall && !InternalLinkage && IsCallReloc) {
2567	unsigned GPReg = ABI.IsN64() ? Mips::GP_64 : Mips::GP;
2568	EVT Ty = ABI.IsN64() ? MVT::i64 : MVT::i32;
2569	RegsToPass.push_back(std::make_pair(GPReg, getGlobalReg(CLI.DAG, Ty)));
2570	}
2571
2572	// Build a sequence of copy-to-reg nodes chained together with token
2573	// chain and flag operands which copy the outgoing args into registers.
2574	// The InFlag in necessary since all emitted instructions must be
2575	// stuck together.
2576	SDValue InFlag;
2577
2578	for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2579	Chain = CLI.DAG.getCopyToReg(Chain, CLI.DL, RegsToPass[i].first,
2580	RegsToPass[i].second, InFlag);
2581	InFlag = Chain.getValue(1);
2582	}
2583
2584	// Add argument registers to the end of the list so that they are
2585	// known live into the call.
2586	for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2587	Ops.push_back(CLI.DAG.getRegister(RegsToPass[i].first,
2588	RegsToPass[i].second.getValueType()));
2589
2590	// Add a register mask operand representing the call-preserved registers.
2591	const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
2592	const uint32_t *Mask =
2593	TRI->getCallPreservedMask(CLI.DAG.getMachineFunction(), CLI.CallConv);
2594	assert(Mask && "Missing call preserved mask for calling convention")((Mask && "Missing call preserved mask for calling convention" ) ? static_cast<void> (0) : __assert_fail ("Mask && \"Missing call preserved mask for calling convention\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MipsISelLowering.cpp" , 2594, __PRETTY_FUNCTION__));
2595	if (Subtarget.inMips16HardFloat()) {
2596	if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(CLI.Callee)) {
2597	llvm::StringRef Sym = G->getGlobal()->getName();
2598	Function *F = G->getGlobal()->getParent()->getFunction(Sym);
2599	if (F && F->hasFnAttribute("__Mips16RetHelper")) {
2600	Mask = MipsRegisterInfo::getMips16RetHelperMask();
2601	}
2602	}
2603	}
2604	Ops.push_back(CLI.DAG.getRegisterMask(Mask));
2605
2606	if (InFlag.getNode())
2607	Ops.push_back(InFlag);
2608	}
2609
2610	/// LowerCall - functions arguments are copied from virtual regs to
2611	/// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
2612	SDValue
2613	MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2614	SmallVectorImpl<SDValue> &InVals) const {
2615	SelectionDAG &DAG = CLI.DAG;
2616	SDLoc DL = CLI.DL;
2617	SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2618	SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2619	SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2620	SDValue Chain = CLI.Chain;
2621	SDValue Callee = CLI.Callee;
2622	bool &IsTailCall = CLI.IsTailCall;
2623	CallingConv::ID CallConv = CLI.CallConv;
2624	bool IsVarArg = CLI.IsVarArg;
2625
2626	MachineFunction &MF = DAG.getMachineFunction();
2627	MachineFrameInfo *MFI = MF.getFrameInfo();
2628	const TargetFrameLowering *TFL = Subtarget.getFrameLowering();
2629	MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
2630	bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
2631
2632	// Analyze operands of the call, assigning locations to each operand.
2633	SmallVector<CCValAssign, 16> ArgLocs;
2634	MipsCCState CCInfo(
2635	CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, *DAG.getContext(),
2636	MipsCCState::getSpecialCallingConvForCallee(Callee.getNode(), Subtarget));
2637
2638	// Allocate the reserved argument area. It seems strange to do this from the
2639	// caller side but removing it breaks the frame size calculation.
2640	CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(CallConv), 1);
2641
2642	CCInfo.AnalyzeCallOperands(Outs, CC_Mips, CLI.getArgs(), Callee.getNode());
2643
2644	// Get a count of how many bytes are to be pushed on the stack.
2645	unsigned NextStackOffset = CCInfo.getNextStackOffset();
2646
2647	// Check if it's really possible to do a tail call.
2648	if (IsTailCall)
2649	IsTailCall = isEligibleForTailCallOptimization(
2650	CCInfo, NextStackOffset, *MF.getInfo<MipsFunctionInfo>());
2651
2652	if (!IsTailCall && CLI.CS && CLI.CS->isMustTailCall())
2653	report_fatal_error("failed to perform tail call elimination on a call "
2654	"site marked musttail");
2655
2656	if (IsTailCall)
2657	++NumTailCalls;
2658
2659	// Chain is the output chain of the last Load/Store or CopyToReg node.
2660	// ByValChain is the output chain of the last Memcpy node created for copying
2661	// byval arguments to the stack.
2662	unsigned StackAlignment = TFL->getStackAlignment();
2663	NextStackOffset = alignTo(NextStackOffset, StackAlignment);
2664	SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, DL, true);
2665
2666	if (!IsTailCall)
2667	Chain = DAG.getCALLSEQ_START(Chain, NextStackOffsetVal, DL);
2668
2669	SDValue StackPtr =
2670	DAG.getCopyFromReg(Chain, DL, ABI.IsN64() ? Mips::SP_64 : Mips::SP,
2671	getPointerTy(DAG.getDataLayout()));
2672
2673	// With EABI is it possible to have 16 args on registers.
2674	std::deque< std::pair<unsigned, SDValue> > RegsToPass;
2675	SmallVector<SDValue, 8> MemOpChains;
2676
2677	CCInfo.rewindByValRegsInfo();
2678
2679	// Walk the register/memloc assignments, inserting copies/loads.
2680	for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2681	SDValue Arg = OutVals[i];
2682	CCValAssign &VA = ArgLocs[i];
2683	MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT();
2684	ISD::ArgFlagsTy Flags = Outs[i].Flags;
2685	bool UseUpperBits = false;
2686
2687	// ByVal Arg.
2688	if (Flags.isByVal()) {
2689	unsigned FirstByValReg, LastByValReg;
2690	unsigned ByValIdx = CCInfo.getInRegsParamsProcessed();
2691	CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg);
2692
2693	assert(Flags.getByValSize() &&((Flags.getByValSize() && "ByVal args of size 0 should have been ignored by front-end." ) ? static_cast<void> (0) : __assert_fail ("Flags.getByValSize() && \"ByVal args of size 0 should have been ignored by front-end.\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MipsISelLowering.cpp" , 2694, __PRETTY_FUNCTION__))
2694	"ByVal args of size 0 should have been ignored by front-end.")((Flags.getByValSize() && "ByVal args of size 0 should have been ignored by front-end." ) ? static_cast<void> (0) : __assert_fail ("Flags.getByValSize() && \"ByVal args of size 0 should have been ignored by front-end.\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MipsISelLowering.cpp" , 2694, __PRETTY_FUNCTION__));
2695	assert(ByValIdx < CCInfo.getInRegsParamsCount())((ByValIdx < CCInfo.getInRegsParamsCount()) ? static_cast< void> (0) : __assert_fail ("ByValIdx < CCInfo.getInRegsParamsCount()" , "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MipsISelLowering.cpp" , 2695, __PRETTY_FUNCTION__));
2696	assert(!IsTailCall &&((!IsTailCall && "Do not tail-call optimize if there is a byval argument." ) ? static_cast<void> (0) : __assert_fail ("!IsTailCall && \"Do not tail-call optimize if there is a byval argument.\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MipsISelLowering.cpp" , 2697, __PRETTY_FUNCTION__))
2697	"Do not tail-call optimize if there is a byval argument.")((!IsTailCall && "Do not tail-call optimize if there is a byval argument." ) ? static_cast<void> (0) : __assert_fail ("!IsTailCall && \"Do not tail-call optimize if there is a byval argument.\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MipsISelLowering.cpp" , 2697, __PRETTY_FUNCTION__));
2698	passByValArg(Chain, DL, RegsToPass, MemOpChains, StackPtr, MFI, DAG, Arg,
2699	FirstByValReg, LastByValReg, Flags, Subtarget.isLittle(),
2700	VA);
2701	CCInfo.nextInRegsParam();
2702	continue;
2703	}
2704
2705	// Promote the value if needed.
2706	switch (VA.getLocInfo()) {
2707	default:
2708	llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MipsISelLowering.cpp" , 2708);
2709	case CCValAssign::Full:
2710	if (VA.isRegLoc()) {
2711	if ((ValVT == MVT::f32 && LocVT == MVT::i32) \|\|
2712	(ValVT == MVT::f64 && LocVT == MVT::i64) \|\|
2713	(ValVT == MVT::i64 && LocVT == MVT::f64))
2714	Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg);
2715	else if (ValVT == MVT::f64 && LocVT == MVT::i32) {
2716	SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
2717	Arg, DAG.getConstant(0, DL, MVT::i32));
2718	SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
2719	Arg, DAG.getConstant(1, DL, MVT::i32));
2720	if (!Subtarget.isLittle())
2721	std::swap(Lo, Hi);
2722	unsigned LocRegLo = VA.getLocReg();
2723	unsigned LocRegHigh = getNextIntArgReg(LocRegLo);
2724	RegsToPass.push_back(std::make_pair(LocRegLo, Lo));
2725	RegsToPass.push_back(std::make_pair(LocRegHigh, Hi));
2726	continue;
2727	}
2728	}
2729	break;
2730	case CCValAssign::BCvt:
2731	Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg);
2732	break;
2733	case CCValAssign::SExtUpper:
2734	UseUpperBits = true;
2735	// Fallthrough
2736	case CCValAssign::SExt:
2737	Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, LocVT, Arg);
2738	break;
2739	case CCValAssign::ZExtUpper:
2740	UseUpperBits = true;
2741	// Fallthrough
2742	case CCValAssign::ZExt:
2743	Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, LocVT, Arg);
2744	break;
2745	case CCValAssign::AExtUpper:
2746	UseUpperBits = true;
2747	// Fallthrough
2748	case CCValAssign::AExt:
2749	Arg = DAG.getNode(ISD::ANY_EXTEND, DL, LocVT, Arg);
2750	break;
2751	}
2752
2753	if (UseUpperBits) {
2754	unsigned ValSizeInBits = Outs[i].ArgVT.getSizeInBits();
2755	unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
2756	Arg = DAG.getNode(
2757	ISD::SHL, DL, VA.getLocVT(), Arg,
2758	DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT()));
2759	}
2760
2761	// Arguments that can be passed on register must be kept at
2762	// RegsToPass vector
2763	if (VA.isRegLoc()) {
2764	RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2765	continue;
2766	}
2767
2768	// Register can't get to this point...
2769	assert(VA.isMemLoc())((VA.isMemLoc()) ? static_cast<void> (0) : __assert_fail ("VA.isMemLoc()", "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MipsISelLowering.cpp" , 2769, __PRETTY_FUNCTION__));
2770
2771	// emit ISD::STORE whichs stores the
2772	// parameter value to a stack Location
2773	MemOpChains.push_back(passArgOnStack(StackPtr, VA.getLocMemOffset(),
2774	Chain, Arg, DL, IsTailCall, DAG));
2775	}
2776
2777	// Transform all store nodes into one single node because all store
2778	// nodes are independent of each other.
2779	if (!MemOpChains.empty())
2780	Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
2781
2782	// If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
2783	// direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
2784	// node so that legalize doesn't hack it.
2785	bool IsPICCall = (ABI.IsN64() \|\| IsPIC); // true if calls are translated to
2786	// jalr $25
2787	bool GlobalOrExternal = false, InternalLinkage = false, IsCallReloc = false;
2788	SDValue CalleeLo;
2789	EVT Ty = Callee.getValueType();
2790
2791	if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2792	if (IsPICCall) {
2793	const GlobalValue *Val = G->getGlobal();
2794	InternalLinkage = Val->hasInternalLinkage();
2795
2796	if (InternalLinkage)
2797	Callee = getAddrLocal(G, DL, Ty, DAG, ABI.IsN32() \|\| ABI.IsN64());
2798	else if (LargeGOT) {
2799	Callee = getAddrGlobalLargeGOT(G, DL, Ty, DAG, MipsII::MO_CALL_HI16,
2800	MipsII::MO_CALL_LO16, Chain,
2801	FuncInfo->callPtrInfo(Val));
2802	IsCallReloc = true;
2803	} else {
2804	Callee = getAddrGlobal(G, DL, Ty, DAG, MipsII::MO_GOT_CALL, Chain,
2805	FuncInfo->callPtrInfo(Val));
2806	IsCallReloc = true;
2807	}
2808	} else
2809	Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL,
2810	getPointerTy(DAG.getDataLayout()), 0,
2811	MipsII::MO_NO_FLAG);
2812	GlobalOrExternal = true;
2813	}
2814	else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2815	const char *Sym = S->getSymbol();
2816
2817	if (!ABI.IsN64() && !IsPIC) // !N64 && static
2818	Callee = DAG.getTargetExternalSymbol(
2819	Sym, getPointerTy(DAG.getDataLayout()), MipsII::MO_NO_FLAG);
2820	else if (LargeGOT) {
2821	Callee = getAddrGlobalLargeGOT(S, DL, Ty, DAG, MipsII::MO_CALL_HI16,
2822	MipsII::MO_CALL_LO16, Chain,
2823	FuncInfo->callPtrInfo(Sym));
2824	IsCallReloc = true;
2825	} else { // N64 \|\| PIC
2826	Callee = getAddrGlobal(S, DL, Ty, DAG, MipsII::MO_GOT_CALL, Chain,
2827	FuncInfo->callPtrInfo(Sym));
2828	IsCallReloc = true;
2829	}
2830
2831	GlobalOrExternal = true;
2832	}
2833
2834	SmallVector<SDValue, 8> Ops(1, Chain);
2835	SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2836
2837	getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal, InternalLinkage,
2838	IsCallReloc, CLI, Callee, Chain);
2839
2840	if (IsTailCall)
2841	return DAG.getNode(MipsISD::TailCall, DL, MVT::Other, Ops);
2842
2843	Chain = DAG.getNode(MipsISD::JmpLink, DL, NodeTys, Ops);
2844	SDValue InFlag = Chain.getValue(1);
2845
2846	// Create the CALLSEQ_END node.
2847	Chain = DAG.getCALLSEQ_END(Chain, NextStackOffsetVal,
2848	DAG.getIntPtrConstant(0, DL, true), InFlag, DL);
2849	InFlag = Chain.getValue(1);
2850
2851	// Handle result values, copying them out of physregs into vregs that we
2852	// return.
2853	return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG,
2854	InVals, CLI);
2855	}
2856
2857	/// LowerCallResult - Lower the result values of a call into the
2858	/// appropriate copies out of appropriate physical registers.
2859	SDValue MipsTargetLowering::LowerCallResult(
2860	SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool IsVarArg,
2861	const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG,
2862	SmallVectorImpl<SDValue> &InVals,
2863	TargetLowering::CallLoweringInfo &CLI) const {
2864	// Assign locations to each value returned by this call.
2865	SmallVector<CCValAssign, 16> RVLocs;
2866	MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
2867	*DAG.getContext());
2868	CCInfo.AnalyzeCallResult(Ins, RetCC_Mips, CLI);
2869
2870	// Copy all of the result registers out of their specified physreg.
2871	for (unsigned i = 0; i != RVLocs.size(); ++i) {
2872	CCValAssign &VA = RVLocs[i];
2873	assert(VA.isRegLoc() && "Can only return in registers!")((VA.isRegLoc() && "Can only return in registers!") ? static_cast<void> (0) : __assert_fail ("VA.isRegLoc() && \"Can only return in registers!\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MipsISelLowering.cpp" , 2873, __PRETTY_FUNCTION__));
2874
2875	SDValue Val = DAG.getCopyFromReg(Chain, DL, RVLocs[i].getLocReg(),
2876	RVLocs[i].getLocVT(), InFlag);
2877	Chain = Val.getValue(1);
2878	InFlag = Val.getValue(2);
2879
2880	if (VA.isUpperBitsInLoc()) {
2881	unsigned ValSizeInBits = Ins[i].ArgVT.getSizeInBits();
2882	unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
2883	unsigned Shift =
2884	VA.getLocInfo() == CCValAssign::ZExtUpper ? ISD::SRL : ISD::SRA;
2885	Val = DAG.getNode(
2886	Shift, DL, VA.getLocVT(), Val,
2887	DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT()));
2888	}
2889
2890	switch (VA.getLocInfo()) {
2891	default:
2892	llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MipsISelLowering.cpp" , 2892);
2893	case CCValAssign::Full:
2894	break;
2895	case CCValAssign::BCvt:
2896	Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val);
2897	break;
2898	case CCValAssign::AExt:
2899	case CCValAssign::AExtUpper:
2900	Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
2901	break;
2902	case CCValAssign::ZExt:
2903	case CCValAssign::ZExtUpper:
2904	Val = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Val,
2905	DAG.getValueType(VA.getValVT()));
2906	Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
2907	break;
2908	case CCValAssign::SExt:
2909	case CCValAssign::SExtUpper:
2910	Val = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Val,
2911	DAG.getValueType(VA.getValVT()));
2912	Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
2913	break;
2914	}
2915
2916	InVals.push_back(Val);
2917	}
2918
2919	return Chain;
2920	}
2921
2922	static SDValue UnpackFromArgumentSlot(SDValue Val, const CCValAssign &VA,
2923	EVT ArgVT, SDLoc DL, SelectionDAG &DAG) {
2924	MVT LocVT = VA.getLocVT();
2925	EVT ValVT = VA.getValVT();
2926
2927	// Shift into the upper bits if necessary.
2928	switch (VA.getLocInfo()) {
2929	default:
2930	break;
2931	case CCValAssign::AExtUpper:
2932	case CCValAssign::SExtUpper:
2933	case CCValAssign::ZExtUpper: {
2934	unsigned ValSizeInBits = ArgVT.getSizeInBits();
2935	unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
2936	unsigned Opcode =
2937	VA.getLocInfo() == CCValAssign::ZExtUpper ? ISD::SRL : ISD::SRA;
2938	Val = DAG.getNode(
2939	Opcode, DL, VA.getLocVT(), Val,
2940	DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT()));
2941	break;
2942	}
2943	}
2944
2945	// If this is an value smaller than the argument slot size (32-bit for O32,
2946	// 64-bit for N32/N64), it has been promoted in some way to the argument slot
2947	// size. Extract the value and insert any appropriate assertions regarding
2948	// sign/zero extension.
2949	switch (VA.getLocInfo()) {
2950	default:
2951	llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MipsISelLowering.cpp" , 2951);
2952	case CCValAssign::Full:
2953	break;
2954	case CCValAssign::AExtUpper:
2955	case CCValAssign::AExt:
2956	Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val);
2957	break;
2958	case CCValAssign::SExtUpper:
2959	case CCValAssign::SExt:
2960	Val = DAG.getNode(ISD::AssertSext, DL, LocVT, Val, DAG.getValueType(ValVT));
2961	Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val);
2962	break;
2963	case CCValAssign::ZExtUpper:
2964	case CCValAssign::ZExt:
2965	Val = DAG.getNode(ISD::AssertZext, DL, LocVT, Val, DAG.getValueType(ValVT));
2966	Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val);
2967	break;
2968	case CCValAssign::BCvt:
2969	Val = DAG.getNode(ISD::BITCAST, DL, ValVT, Val);
2970	break;
2971	}
2972
2973	return Val;
2974	}
2975
2976	//===----------------------------------------------------------------------===//
2977	// Formal Arguments Calling Convention Implementation
2978	//===----------------------------------------------------------------------===//
2979	/// LowerFormalArguments - transform physical registers into virtual registers
2980	/// and generate load operations for arguments places on the stack.
2981	SDValue
2982	MipsTargetLowering::LowerFormalArguments(SDValue Chain,
2983	CallingConv::ID CallConv,
2984	bool IsVarArg,
2985	const SmallVectorImpl<ISD::InputArg> &Ins,
2986	SDLoc DL, SelectionDAG &DAG,
2987	SmallVectorImpl<SDValue> &InVals)
2988	const {
2989	MachineFunction &MF = DAG.getMachineFunction();
2990	MachineFrameInfo *MFI = MF.getFrameInfo();
2991	MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
2992
2993	MipsFI->setVarArgsFrameIndex(0);
2994
2995	// Used with vargs to acumulate store chains.
2996	std::vector<SDValue> OutChains;
2997
2998	// Assign locations to all of the incoming arguments.
2999	SmallVector<CCValAssign, 16> ArgLocs;
3000	MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
3001	*DAG.getContext());
3002	CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(CallConv), 1);
3003	const Function *Func = DAG.getMachineFunction().getFunction();
3004	Function::const_arg_iterator FuncArg = Func->arg_begin();
3005
3006	if (Func->hasFnAttribute("interrupt") && !Func->arg_empty())
3007	report_fatal_error(
3008	"Functions with the interrupt attribute cannot have arguments!");
3009
3010	CCInfo.AnalyzeFormalArguments(Ins, CC_Mips_FixedArg);
3011	MipsFI->setFormalArgInfo(CCInfo.getNextStackOffset(),
3012	CCInfo.getInRegsParamsCount() > 0);
3013
3014	unsigned CurArgIdx = 0;
3015	CCInfo.rewindByValRegsInfo();
3016
3017	for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3018	CCValAssign &VA = ArgLocs[i];
3019	if (Ins[i].isOrigArg()) {
3020	std::advance(FuncArg, Ins[i].getOrigArgIndex() - CurArgIdx);
3021	CurArgIdx = Ins[i].getOrigArgIndex();
3022	}
3023	EVT ValVT = VA.getValVT();
3024	ISD::ArgFlagsTy Flags = Ins[i].Flags;
3025	bool IsRegLoc = VA.isRegLoc();
3026
3027	if (Flags.isByVal()) {
3028	assert(Ins[i].isOrigArg() && "Byval arguments cannot be implicit")((Ins[i].isOrigArg() && "Byval arguments cannot be implicit" ) ? static_cast<void> (0) : __assert_fail ("Ins[i].isOrigArg() && \"Byval arguments cannot be implicit\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MipsISelLowering.cpp" , 3028, __PRETTY_FUNCTION__));
3029	unsigned FirstByValReg, LastByValReg;
3030	unsigned ByValIdx = CCInfo.getInRegsParamsProcessed();
3031	CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg);
3032
3033	assert(Flags.getByValSize() &&((Flags.getByValSize() && "ByVal args of size 0 should have been ignored by front-end." ) ? static_cast<void> (0) : __assert_fail ("Flags.getByValSize() && \"ByVal args of size 0 should have been ignored by front-end.\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MipsISelLowering.cpp" , 3034, __PRETTY_FUNCTION__))
3034	"ByVal args of size 0 should have been ignored by front-end.")((Flags.getByValSize() && "ByVal args of size 0 should have been ignored by front-end." ) ? static_cast<void> (0) : __assert_fail ("Flags.getByValSize() && \"ByVal args of size 0 should have been ignored by front-end.\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MipsISelLowering.cpp" , 3034, __PRETTY_FUNCTION__));
3035	assert(ByValIdx < CCInfo.getInRegsParamsCount())((ByValIdx < CCInfo.getInRegsParamsCount()) ? static_cast< void> (0) : __assert_fail ("ByValIdx < CCInfo.getInRegsParamsCount()" , "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MipsISelLowering.cpp" , 3035, __PRETTY_FUNCTION__));
3036	copyByValRegs(Chain, DL, OutChains, DAG, Flags, InVals, &*FuncArg,
3037	FirstByValReg, LastByValReg, VA, CCInfo);
3038	CCInfo.nextInRegsParam();
3039	continue;
3040	}
3041
3042	// Arguments stored on registers
3043	if (IsRegLoc) {
3044	MVT RegVT = VA.getLocVT();
3045	unsigned ArgReg = VA.getLocReg();
3046	const TargetRegisterClass *RC = getRegClassFor(RegVT);
3047
3048	// Transform the arguments stored on
3049	// physical registers into virtual ones
3050	unsigned Reg = addLiveIn(DAG.getMachineFunction(), ArgReg, RC);
3051	SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT);
3052
3053	ArgValue = UnpackFromArgumentSlot(ArgValue, VA, Ins[i].ArgVT, DL, DAG);
3054
3055	// Handle floating point arguments passed in integer registers and
3056	// long double arguments passed in floating point registers.
3057	if ((RegVT == MVT::i32 && ValVT == MVT::f32) \|\|
3058	(RegVT == MVT::i64 && ValVT == MVT::f64) \|\|
3059	(RegVT == MVT::f64 && ValVT == MVT::i64))
3060	ArgValue = DAG.getNode(ISD::BITCAST, DL, ValVT, ArgValue);
3061	else if (ABI.IsO32() && RegVT == MVT::i32 &&
3062	ValVT == MVT::f64) {
3063	unsigned Reg2 = addLiveIn(DAG.getMachineFunction(),
3064	getNextIntArgReg(ArgReg), RC);
3065	SDValue ArgValue2 = DAG.getCopyFromReg(Chain, DL, Reg2, RegVT);
3066	if (!Subtarget.isLittle())
3067	std::swap(ArgValue, ArgValue2);
3068	ArgValue = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64,
3069	ArgValue, ArgValue2);
3070	}
3071
3072	InVals.push_back(ArgValue);
3073	} else { // VA.isRegLoc()
3074	MVT LocVT = VA.getLocVT();
3075
3076	if (ABI.IsO32()) {
3077	// We ought to be able to use LocVT directly but O32 sets it to i32
3078	// when allocating floating point values to integer registers.
3079	// This shouldn't influence how we load the value into registers unless
3080	// we are targeting softfloat.
3081	if (VA.getValVT().isFloatingPoint() && !Subtarget.useSoftFloat())
3082	LocVT = VA.getValVT();
3083	}
3084
3085	// sanity check
3086	assert(VA.isMemLoc())((VA.isMemLoc()) ? static_cast<void> (0) : __assert_fail ("VA.isMemLoc()", "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MipsISelLowering.cpp" , 3086, __PRETTY_FUNCTION__));
3087
3088	// The stack pointer offset is relative to the caller stack frame.
3089	int FI = MFI->CreateFixedObject(LocVT.getSizeInBits() / 8,
3090	VA.getLocMemOffset(), true);
3091
3092	// Create load nodes to retrieve arguments from the stack
3093	SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
3094	SDValue ArgValue = DAG.getLoad(
3095	LocVT, DL, Chain, FIN,
3096	MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI),
3097	false, false, false, 0);
3098	OutChains.push_back(ArgValue.getValue(1));
3099
3100	ArgValue = UnpackFromArgumentSlot(ArgValue, VA, Ins[i].ArgVT, DL, DAG);
3101
3102	InVals.push_back(ArgValue);
3103	}
3104	}
3105
3106	for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3107	// The mips ABIs for returning structs by value requires that we copy
3108	// the sret argument into $v0 for the return. Save the argument into
3109	// a virtual register so that we can access it from the return points.
3110	if (Ins[i].Flags.isSRet()) {
3111	unsigned Reg = MipsFI->getSRetReturnReg();
3112	if (!Reg) {
3113	Reg = MF.getRegInfo().createVirtualRegister(
3114	getRegClassFor(ABI.IsN64() ? MVT::i64 : MVT::i32));
3115	MipsFI->setSRetReturnReg(Reg);
3116	}
3117	SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), DL, Reg, InVals[i]);
3118	Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Copy, Chain);
3119	break;
3120	}
3121	}
3122
3123	if (IsVarArg)
3124	writeVarArgRegs(OutChains, Chain, DL, DAG, CCInfo);
3125
3126	// All stores are grouped in one node to allow the matching between
3127	// the size of Ins and InVals. This only happens when on varg functions
3128	if (!OutChains.empty()) {
3129	OutChains.push_back(Chain);
3130	Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains);
3131	}
3132
3133	return Chain;
3134	}
3135
3136	//===----------------------------------------------------------------------===//
3137	// Return Value Calling Convention Implementation
3138	//===----------------------------------------------------------------------===//
3139
3140	bool
3141	MipsTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
3142	MachineFunction &MF, bool IsVarArg,
3143	const SmallVectorImpl<ISD::OutputArg> &Outs,
3144	LLVMContext &Context) const {
3145	SmallVector<CCValAssign, 16> RVLocs;
3146	MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
3147	return CCInfo.CheckReturn(Outs, RetCC_Mips);
3148	}
3149
3150	bool
3151	MipsTargetLowering::shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const {
3152	if (Subtarget.hasMips3() && Subtarget.useSoftFloat()) {
3153	if (Type == MVT::i32)
3154	return true;
3155	}
3156	return IsSigned;
3157	}
3158
3159	SDValue
3160	MipsTargetLowering::LowerInterruptReturn(SmallVectorImpl<SDValue> &RetOps,
3161	SDLoc DL, SelectionDAG &DAG) const {
3162
3163	MachineFunction &MF = DAG.getMachineFunction();
3164	MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
3165
3166	MipsFI->setISR();
3167
3168	return DAG.getNode(MipsISD::ERet, DL, MVT::Other, RetOps);
3169	}
3170
3171	SDValue
3172	MipsTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
3173	bool IsVarArg,
3174	const SmallVectorImpl<ISD::OutputArg> &Outs,
3175	const SmallVectorImpl<SDValue> &OutVals,
3176	SDLoc DL, SelectionDAG &DAG) const {
3177	// CCValAssign - represent the assignment of
3178	// the return value to a location
3179	SmallVector<CCValAssign, 16> RVLocs;
3180	MachineFunction &MF = DAG.getMachineFunction();
3181
3182	// CCState - Info about the registers and stack slot.
3183	MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext());
3184
3185	// Analyze return values.
3186	CCInfo.AnalyzeReturn(Outs, RetCC_Mips);
3187
3188	SDValue Flag;
3189	SmallVector<SDValue, 4> RetOps(1, Chain);
3190
3191	// Copy the result values into the output registers.
3192	for (unsigned i = 0; i != RVLocs.size(); ++i) {
3193	SDValue Val = OutVals[i];
3194	CCValAssign &VA = RVLocs[i];
3195	assert(VA.isRegLoc() && "Can only return in registers!")((VA.isRegLoc() && "Can only return in registers!") ? static_cast<void> (0) : __assert_fail ("VA.isRegLoc() && \"Can only return in registers!\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MipsISelLowering.cpp" , 3195, __PRETTY_FUNCTION__));
3196	bool UseUpperBits = false;
3197
3198	switch (VA.getLocInfo()) {
3199	default:
3200	llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MipsISelLowering.cpp" , 3200);
3201	case CCValAssign::Full:
3202	break;
3203	case CCValAssign::BCvt:
3204	Val = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Val);
3205	break;
3206	case CCValAssign::AExtUpper:
3207	UseUpperBits = true;
3208	// Fallthrough
3209	case CCValAssign::AExt:
3210	Val = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Val);
3211	break;
3212	case CCValAssign::ZExtUpper:
3213	UseUpperBits = true;
3214	// Fallthrough
3215	case CCValAssign::ZExt:
3216	Val = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Val);
3217	break;
3218	case CCValAssign::SExtUpper:
3219	UseUpperBits = true;
3220	// Fallthrough
3221	case CCValAssign::SExt:
3222	Val = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Val);
3223	break;
3224	}
3225
3226	if (UseUpperBits) {
3227	unsigned ValSizeInBits = Outs[i].ArgVT.getSizeInBits();
3228	unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
3229	Val = DAG.getNode(
3230	ISD::SHL, DL, VA.getLocVT(), Val,
3231	DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT()));
3232	}
3233
3234	Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Flag);
3235
3236	// Guarantee that all emitted copies are stuck together with flags.
3237	Flag = Chain.getValue(1);
3238	RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
3239	}
3240
3241	// The mips ABIs for returning structs by value requires that we copy
3242	// the sret argument into $v0 for the return. We saved the argument into
3243	// a virtual register in the entry block, so now we copy the value out
3244	// and into $v0.
3245	if (MF.getFunction()->hasStructRetAttr()) {
3246	MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
3247	unsigned Reg = MipsFI->getSRetReturnReg();
3248
3249	if (!Reg)
3250	llvm_unreachable("sret virtual register not created in the entry block")::llvm::llvm_unreachable_internal("sret virtual register not created in the entry block" , "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MipsISelLowering.cpp" , 3250);
3251	SDValue Val =
3252	DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(DAG.getDataLayout()));
3253	unsigned V0 = ABI.IsN64() ? Mips::V0_64 : Mips::V0;
3254
3255	Chain = DAG.getCopyToReg(Chain, DL, V0, Val, Flag);
3256	Flag = Chain.getValue(1);
3257	RetOps.push_back(DAG.getRegister(V0, getPointerTy(DAG.getDataLayout())));
3258	}
3259
3260	RetOps[0] = Chain; // Update chain.
3261
3262	// Add the flag if we have it.
3263	if (Flag.getNode())
3264	RetOps.push_back(Flag);
3265
3266	// ISRs must use "eret".
3267	if (DAG.getMachineFunction().getFunction()->hasFnAttribute("interrupt"))
3268	return LowerInterruptReturn(RetOps, DL, DAG);
3269
3270	// Standard return on Mips is a "jr $ra"
3271	return DAG.getNode(MipsISD::Ret, DL, MVT::Other, RetOps);
3272	}
3273
3274	//===----------------------------------------------------------------------===//
3275	// Mips Inline Assembly Support
3276	//===----------------------------------------------------------------------===//
3277
3278	/// getConstraintType - Given a constraint letter, return the type of
3279	/// constraint it is for this target.
3280	MipsTargetLowering::ConstraintType
3281	MipsTargetLowering::getConstraintType(StringRef Constraint) const {
3282	// Mips specific constraints
3283	// GCC config/mips/constraints.md
3284	//
3285	// 'd' : An address register. Equivalent to r
3286	// unless generating MIPS16 code.
3287	// 'y' : Equivalent to r; retained for
3288	// backwards compatibility.
3289	// 'c' : A register suitable for use in an indirect
3290	// jump. This will always be $25 for -mabicalls.
3291	// 'l' : The lo register. 1 word storage.
3292	// 'x' : The hilo register pair. Double word storage.
3293	if (Constraint.size() == 1) {
3294	switch (Constraint[0]) {
3295	default : break;
3296	case 'd':
3297	case 'y':
3298	case 'f':
3299	case 'c':
3300	case 'l':
3301	case 'x':
3302	return C_RegisterClass;
3303	case 'R':
3304	return C_Memory;
3305	}
3306	}
3307
3308	if (Constraint == "ZC")
3309	return C_Memory;
3310
3311	return TargetLowering::getConstraintType(Constraint);
3312	}
3313
3314	/// Examine constraint type and operand type and determine a weight value.
3315	/// This object must already have been set up with the operand type
3316	/// and the current alternative constraint selected.
3317	TargetLowering::ConstraintWeight
3318	MipsTargetLowering::getSingleConstraintMatchWeight(
3319	AsmOperandInfo &info, const char *constraint) const {
3320	ConstraintWeight weight = CW_Invalid;
3321	Value *CallOperandVal = info.CallOperandVal;
3322	// If we don't have a value, we can't do a match,
3323	// but allow it at the lowest weight.
3324	if (!CallOperandVal)
3325	return CW_Default;
3326	Type *type = CallOperandVal->getType();
3327	// Look at the constraint type.
3328	switch (*constraint) {
3329	default:
3330	weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
3331	break;
3332	case 'd':
3333	case 'y':
3334	if (type->isIntegerTy())
3335	weight = CW_Register;
3336	break;
3337	case 'f': // FPU or MSA register
3338	if (Subtarget.hasMSA() && type->isVectorTy() &&
3339	cast<VectorType>(type)->getBitWidth() == 128)
3340	weight = CW_Register;
3341	else if (type->isFloatTy())
3342	weight = CW_Register;
3343	break;
3344	case 'c': // $25 for indirect jumps
3345	case 'l': // lo register
3346	case 'x': // hilo register pair
3347	if (type->isIntegerTy())
3348	weight = CW_SpecificReg;
3349	break;
3350	case 'I': // signed 16 bit immediate
3351	case 'J': // integer zero
3352	case 'K': // unsigned 16 bit immediate
3353	case 'L': // signed 32 bit immediate where lower 16 bits are 0
3354	case 'N': // immediate in the range of -65535 to -1 (inclusive)
3355	case 'O': // signed 15 bit immediate (+- 16383)
3356	case 'P': // immediate in the range of 65535 to 1 (inclusive)
3357	if (isa<ConstantInt>(CallOperandVal))
3358	weight = CW_Constant;
3359	break;
3360	case 'R':
3361	weight = CW_Memory;
3362	break;
3363	}
3364	return weight;
3365	}
3366
3367	/// This is a helper function to parse a physical register string and split it
3368	/// into non-numeric and numeric parts (Prefix and Reg). The first boolean flag
3369	/// that is returned indicates whether parsing was successful. The second flag
3370	/// is true if the numeric part exists.
3371	static std::pair<bool, bool> parsePhysicalReg(StringRef C, StringRef &Prefix,
3372	unsigned long long &Reg) {
3373	if (C.front() != '{' \|\| C.back() != '}')
3374	return std::make_pair(false, false);
3375
3376	// Search for the first numeric character.
3377	StringRef::const_iterator I, B = C.begin() + 1, E = C.end() - 1;
3378	I = std::find_if(B, E, isdigit);
3379
3380	Prefix = StringRef(B, I - B);
3381
3382	// The second flag is set to false if no numeric characters were found.
3383	if (I == E)
3384	return std::make_pair(true, false);
3385
3386	// Parse the numeric characters.
3387	return std::make_pair(!getAsUnsignedInteger(StringRef(I, E - I), 10, Reg),
3388	true);
3389	}
3390
3391	std::pair<unsigned, const TargetRegisterClass *> MipsTargetLowering::
3392	parseRegForInlineAsmConstraint(StringRef C, MVT VT) const {
3393	const TargetRegisterInfo *TRI =
3394	Subtarget.getRegisterInfo();
3395	const TargetRegisterClass *RC;
3396	StringRef Prefix;
3397	unsigned long long Reg;
3398
3399	std::pair<bool, bool> R = parsePhysicalReg(C, Prefix, Reg);
3400
3401	if (!R.first)
3402	return std::make_pair(0U, nullptr);
3403
3404	if ((Prefix == "hi" \|\| Prefix == "lo")) { // Parse hi/lo.
3405	// No numeric characters follow "hi" or "lo".
3406	if (R.second)
3407	return std::make_pair(0U, nullptr);
3408
3409	RC = TRI->getRegClass(Prefix == "hi" ?
3410	Mips::HI32RegClassID : Mips::LO32RegClassID);
3411	return std::make_pair(*(RC->begin()), RC);
3412	} else if (Prefix.startswith("$msa")) {
3413	// Parse $msa(ir\|csr\|access\|save\|modify\|request\|map\|unmap)
3414
3415	// No numeric characters follow the name.
3416	if (R.second)
3417	return std::make_pair(0U, nullptr);
3418
3419	Reg = StringSwitch<unsigned long long>(Prefix)
3420	.Case("$msair", Mips::MSAIR)
3421	.Case("$msacsr", Mips::MSACSR)
3422	.Case("$msaaccess", Mips::MSAAccess)
3423	.Case("$msasave", Mips::MSASave)
3424	.Case("$msamodify", Mips::MSAModify)
3425	.Case("$msarequest", Mips::MSARequest)
3426	.Case("$msamap", Mips::MSAMap)
3427	.Case("$msaunmap", Mips::MSAUnmap)
3428	.Default(0);
3429
3430	if (!Reg)
3431	return std::make_pair(0U, nullptr);
3432
3433	RC = TRI->getRegClass(Mips::MSACtrlRegClassID);
3434	return std::make_pair(Reg, RC);
3435	}
3436
3437	if (!R.second)
3438	return std::make_pair(0U, nullptr);
3439
3440	if (Prefix == "$f") { // Parse $f0-$f31.
3441	// If the size of FP registers is 64-bit or Reg is an even number, select
3442	// the 64-bit register class. Otherwise, select the 32-bit register class.
3443	if (VT == MVT::Other)
3444	VT = (Subtarget.isFP64bit() \|\| !(Reg % 2)) ? MVT::f64 : MVT::f32;
3445
3446	RC = getRegClassFor(VT);
3447
3448	if (RC == &Mips::AFGR64RegClass) {
3449	assert(Reg % 2 == 0)((Reg % 2 == 0) ? static_cast<void> (0) : __assert_fail ("Reg % 2 == 0", "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MipsISelLowering.cpp" , 3449, __PRETTY_FUNCTION__));
3450	Reg >>= 1;
3451	}
3452	} else if (Prefix == "$fcc") // Parse $fcc0-$fcc7.
3453	RC = TRI->getRegClass(Mips::FCCRegClassID);
3454	else if (Prefix == "$w") { // Parse $w0-$w31.
3455	RC = getRegClassFor((VT == MVT::Other) ? MVT::v16i8 : VT);
3456	} else { // Parse $0-$31.
3457	assert(Prefix == "$")((Prefix == "$") ? static_cast<void> (0) : __assert_fail ("Prefix == \"$\"", "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MipsISelLowering.cpp" , 3457, __PRETTY_FUNCTION__));
3458	RC = getRegClassFor((VT == MVT::Other) ? MVT::i32 : VT);
3459	}
3460
3461	assert(Reg < RC->getNumRegs())((Reg < RC->getNumRegs()) ? static_cast<void> (0) : __assert_fail ("Reg < RC->getNumRegs()", "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MipsISelLowering.cpp" , 3461, __PRETTY_FUNCTION__));
3462	return std::make_pair(*(RC->begin() + Reg), RC);
3463	}
3464
3465	/// Given a register class constraint, like 'r', if this corresponds directly
3466	/// to an LLVM register class, return a register of 0 and the register class
3467	/// pointer.
3468	std::pair<unsigned, const TargetRegisterClass *>
3469	MipsTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
3470	StringRef Constraint,
3471	MVT VT) const {
3472	if (Constraint.size() == 1) {
3473	switch (Constraint[0]) {
3474	case 'd': // Address register. Same as 'r' unless generating MIPS16 code.
3475	case 'y': // Same as 'r'. Exists for compatibility.
3476	case 'r':
3477	if (VT == MVT::i32 \|\| VT == MVT::i16 \|\| VT == MVT::i8) {
3478	if (Subtarget.inMips16Mode())
3479	return std::make_pair(0U, &Mips::CPU16RegsRegClass);
3480	return std::make_pair(0U, &Mips::GPR32RegClass);
3481	}
3482	if (VT == MVT::i64 && !Subtarget.isGP64bit())
3483	return std::make_pair(0U, &Mips::GPR32RegClass);
3484	if (VT == MVT::i64 && Subtarget.isGP64bit())
3485	return std::make_pair(0U, &Mips::GPR64RegClass);
3486	// This will generate an error message
3487	return std::make_pair(0U, nullptr);
3488	case 'f': // FPU or MSA register
3489	if (VT == MVT::v16i8)
3490	return std::make_pair(0U, &Mips::MSA128BRegClass);
3491	else if (VT == MVT::v8i16 \|\| VT == MVT::v8f16)
3492	return std::make_pair(0U, &Mips::MSA128HRegClass);
3493	else if (VT == MVT::v4i32 \|\| VT == MVT::v4f32)
3494	return std::make_pair(0U, &Mips::MSA128WRegClass);
3495	else if (VT == MVT::v2i64 \|\| VT == MVT::v2f64)
3496	return std::make_pair(0U, &Mips::MSA128DRegClass);
3497	else if (VT == MVT::f32)
3498	return std::make_pair(0U, &Mips::FGR32RegClass);
3499	else if ((VT == MVT::f64) && (!Subtarget.isSingleFloat())) {
3500	if (Subtarget.isFP64bit())
3501	return std::make_pair(0U, &Mips::FGR64RegClass);
3502	return std::make_pair(0U, &Mips::AFGR64RegClass);
3503	}
3504	break;
3505	case 'c': // register suitable for indirect jump
3506	if (VT == MVT::i32)
3507	return std::make_pair((unsigned)Mips::T9, &Mips::GPR32RegClass);
3508	assert(VT == MVT::i64 && "Unexpected type.")((VT == MVT::i64 && "Unexpected type.") ? static_cast <void> (0) : __assert_fail ("VT == MVT::i64 && \"Unexpected type.\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MipsISelLowering.cpp" , 3508, __PRETTY_FUNCTION__));
3509	return std::make_pair((unsigned)Mips::T9_64, &Mips::GPR64RegClass);
3510	case 'l': // register suitable for indirect jump
3511	if (VT == MVT::i32)
3512	return std::make_pair((unsigned)Mips::LO0, &Mips::LO32RegClass);
3513	return std::make_pair((unsigned)Mips::LO0_64, &Mips::LO64RegClass);
3514	case 'x': // register suitable for indirect jump
3515	// Fixme: Not triggering the use of both hi and low
3516	// This will generate an error message
3517	return std::make_pair(0U, nullptr);
3518	}
3519	}
3520
3521	std::pair<unsigned, const TargetRegisterClass *> R;
3522	R = parseRegForInlineAsmConstraint(Constraint, VT);
3523
3524	if (R.second)
3525	return R;
3526
3527	return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
3528	}
3529
3530	/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
3531	/// vector. If it is invalid, don't add anything to Ops.
3532	void MipsTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
3533	std::string &Constraint,
3534	std::vector<SDValue>&Ops,
3535	SelectionDAG &DAG) const {
3536	SDLoc DL(Op);
3537	SDValue Result;
3538
3539	// Only support length 1 constraints for now.
3540	if (Constraint.length() > 1) return;
3541
3542	char ConstraintLetter = Constraint[0];
3543	switch (ConstraintLetter) {
3544	default: break; // This will fall through to the generic implementation
3545	case 'I': // Signed 16 bit constant
3546	// If this fails, the parent routine will give an error
3547	if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3548	EVT Type = Op.getValueType();
3549	int64_t Val = C->getSExtValue();
3550	if (isInt<16>(Val)) {
3551	Result = DAG.getTargetConstant(Val, DL, Type);
3552	break;
3553	}
3554	}
3555	return;
3556	case 'J': // integer zero
3557	if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3558	EVT Type = Op.getValueType();
3559	int64_t Val = C->getZExtValue();
3560	if (Val == 0) {
3561	Result = DAG.getTargetConstant(0, DL, Type);
3562	break;
3563	}
3564	}
3565	return;
3566	case 'K': // unsigned 16 bit immediate
3567	if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3568	EVT Type = Op.getValueType();
3569	uint64_t Val = (uint64_t)C->getZExtValue();
3570	if (isUInt<16>(Val)) {
3571	Result = DAG.getTargetConstant(Val, DL, Type);
3572	break;
3573	}
3574	}
3575	return;
3576	case 'L': // signed 32 bit immediate where lower 16 bits are 0
3577	if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3578	EVT Type = Op.getValueType();
3579	int64_t Val = C->getSExtValue();
3580	if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)){
3581	Result = DAG.getTargetConstant(Val, DL, Type);
3582	break;
3583	}
3584	}
3585	return;
3586	case 'N': // immediate in the range of -65535 to -1 (inclusive)
3587	if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3588	EVT Type = Op.getValueType();
3589	int64_t Val = C->getSExtValue();
3590	if ((Val >= -65535) && (Val <= -1)) {
3591	Result = DAG.getTargetConstant(Val, DL, Type);
3592	break;
3593	}
3594	}
3595	return;
3596	case 'O': // signed 15 bit immediate
3597	if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3598	EVT Type = Op.getValueType();
3599	int64_t Val = C->getSExtValue();
3600	if ((isInt<15>(Val))) {
3601	Result = DAG.getTargetConstant(Val, DL, Type);
3602	break;
3603	}
3604	}
3605	return;
3606	case 'P': // immediate in the range of 1 to 65535 (inclusive)
3607	if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3608	EVT Type = Op.getValueType();
3609	int64_t Val = C->getSExtValue();
3610	if ((Val <= 65535) && (Val >= 1)) {
3611	Result = DAG.getTargetConstant(Val, DL, Type);
3612	break;
3613	}
3614	}
3615	return;
3616	}
3617
3618	if (Result.getNode()) {
3619	Ops.push_back(Result);
3620	return;
3621	}
3622
3623	TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
3624	}
3625
3626	bool MipsTargetLowering::isLegalAddressingMode(const DataLayout &DL,
3627	const AddrMode &AM, Type *Ty,
3628	unsigned AS) const {
3629	// No global is ever allowed as a base.
3630	if (AM.BaseGV)
3631	return false;
3632
3633	switch (AM.Scale) {
3634	case 0: // "r+i" or just "i", depending on HasBaseReg.
3635	break;
3636	case 1:
3637	if (!AM.HasBaseReg) // allow "r+i".
3638	break;
3639	return false; // disallow "r+r" or "r+r+i".
3640	default:
3641	return false;
3642	}
3643
3644	return true;
3645	}
3646
3647	bool
3648	MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
3649	// The Mips target isn't yet aware of offsets.
3650	return false;
3651	}
3652
3653	EVT MipsTargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
3654	unsigned SrcAlign,
3655	bool IsMemset, bool ZeroMemset,
3656	bool MemcpyStrSrc,
3657	MachineFunction &MF) const {
3658	if (Subtarget.hasMips64())
3659	return MVT::i64;
3660
3661	return MVT::i32;
3662	}
3663
3664	bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3665	if (VT != MVT::f32 && VT != MVT::f64)
3666	return false;
3667	if (Imm.isNegZero())
3668	return false;
3669	return Imm.isZero();
3670	}
3671
3672	unsigned MipsTargetLowering::getJumpTableEncoding() const {
3673	if (ABI.IsN64())
3674	return MachineJumpTableInfo::EK_GPRel64BlockAddress;
3675
3676	return TargetLowering::getJumpTableEncoding();
3677	}
3678
3679	bool MipsTargetLowering::useSoftFloat() const {
3680	return Subtarget.useSoftFloat();
3681	}
3682
3683	void MipsTargetLowering::copyByValRegs(
3684	SDValue Chain, SDLoc DL, std::vector<SDValue> &OutChains, SelectionDAG &DAG,
3685	const ISD::ArgFlagsTy &Flags, SmallVectorImpl<SDValue> &InVals,
3686	const Argument *FuncArg, unsigned FirstReg, unsigned LastReg,
3687	const CCValAssign &VA, MipsCCState &State) const {
3688	MachineFunction &MF = DAG.getMachineFunction();
3689	MachineFrameInfo *MFI = MF.getFrameInfo();
3690	unsigned GPRSizeInBytes = Subtarget.getGPRSizeInBytes();
3691	unsigned NumRegs = LastReg - FirstReg;
3692	unsigned RegAreaSize = NumRegs * GPRSizeInBytes;
3693	unsigned FrameObjSize = std::max(Flags.getByValSize(), RegAreaSize);
3694	int FrameObjOffset;
3695	ArrayRef<MCPhysReg> ByValArgRegs = ABI.GetByValArgRegs();
3696
3697	if (RegAreaSize)
3698	FrameObjOffset =
3699	(int)ABI.GetCalleeAllocdArgSizeInBytes(State.getCallingConv()) -
3700	(int)((ByValArgRegs.size() - FirstReg) * GPRSizeInBytes);
3701	else
3702	FrameObjOffset = VA.getLocMemOffset();
3703
3704	// Create frame object.
3705	EVT PtrTy = getPointerTy(DAG.getDataLayout());
3706	int FI = MFI->CreateFixedObject(FrameObjSize, FrameObjOffset, true);
3707	SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
3708	InVals.push_back(FIN);
3709
3710	if (!NumRegs)
3711	return;
3712
3713	// Copy arg registers.
3714	MVT RegTy = MVT::getIntegerVT(GPRSizeInBytes * 8);
3715	const TargetRegisterClass *RC = getRegClassFor(RegTy);
3716
3717	for (unsigned I = 0; I < NumRegs; ++I) {
3718	unsigned ArgReg = ByValArgRegs[FirstReg + I];
3719	unsigned VReg = addLiveIn(MF, ArgReg, RC);
3720	unsigned Offset = I * GPRSizeInBytes;
3721	SDValue StorePtr = DAG.getNode(ISD::ADD, DL, PtrTy, FIN,
3722	DAG.getConstant(Offset, DL, PtrTy));
3723	SDValue Store = DAG.getStore(Chain, DL, DAG.getRegister(VReg, RegTy),
3724	StorePtr, MachinePointerInfo(FuncArg, Offset),
3725	false, false, 0);
3726	OutChains.push_back(Store);
3727	}
3728	}
3729
3730	// Copy byVal arg to registers and stack.
3731	void MipsTargetLowering::passByValArg(
3732	SDValue Chain, SDLoc DL,
3733	std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
3734	SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr,
3735	MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg, unsigned FirstReg,
3736	unsigned LastReg, const ISD::ArgFlagsTy &Flags, bool isLittle,
3737	const CCValAssign &VA) const {
3738	unsigned ByValSizeInBytes = Flags.getByValSize();
3739	unsigned OffsetInBytes = 0; // From beginning of struct
3740	unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes();
3741	unsigned Alignment = std::min(Flags.getByValAlign(), RegSizeInBytes);
3742	EVT PtrTy = getPointerTy(DAG.getDataLayout()),
3743	RegTy = MVT::getIntegerVT(RegSizeInBytes * 8);
3744	unsigned NumRegs = LastReg - FirstReg;
3745
3746	if (NumRegs) {
3747	ArrayRef<MCPhysReg> ArgRegs = ABI.GetByValArgRegs();
3748	bool LeftoverBytes = (NumRegs * RegSizeInBytes > ByValSizeInBytes);
3749	unsigned I = 0;
3750
3751	// Copy words to registers.
3752	for (; I < NumRegs - LeftoverBytes; ++I, OffsetInBytes += RegSizeInBytes) {
3753	SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
3754	DAG.getConstant(OffsetInBytes, DL, PtrTy));
3755	SDValue LoadVal = DAG.getLoad(RegTy, DL, Chain, LoadPtr,
3756	MachinePointerInfo(), false, false, false,
3757	Alignment);
3758	MemOpChains.push_back(LoadVal.getValue(1));
3759	unsigned ArgReg = ArgRegs[FirstReg + I];
3760	RegsToPass.push_back(std::make_pair(ArgReg, LoadVal));
3761	}
3762
3763	// Return if the struct has been fully copied.
3764	if (ByValSizeInBytes == OffsetInBytes)
3765	return;
3766
3767	// Copy the remainder of the byval argument with sub-word loads and shifts.
3768	if (LeftoverBytes) {
3769	SDValue Val;
3770
3771	for (unsigned LoadSizeInBytes = RegSizeInBytes / 2, TotalBytesLoaded = 0;
3772	OffsetInBytes < ByValSizeInBytes; LoadSizeInBytes /= 2) {
3773	unsigned RemainingSizeInBytes = ByValSizeInBytes - OffsetInBytes;
3774
3775	if (RemainingSizeInBytes < LoadSizeInBytes)
3776	continue;
3777
3778	// Load subword.
3779	SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
3780	DAG.getConstant(OffsetInBytes, DL,
3781	PtrTy));
3782	SDValue LoadVal = DAG.getExtLoad(
3783	ISD::ZEXTLOAD, DL, RegTy, Chain, LoadPtr, MachinePointerInfo(),
3784	MVT::getIntegerVT(LoadSizeInBytes * 8), false, false, false,
3785	Alignment);
3786	MemOpChains.push_back(LoadVal.getValue(1));
3787
3788	// Shift the loaded value.
3789	unsigned Shamt;
3790
3791	if (isLittle)
3792	Shamt = TotalBytesLoaded * 8;
3793	else
3794	Shamt = (RegSizeInBytes - (TotalBytesLoaded + LoadSizeInBytes)) * 8;
3795
3796	SDValue Shift = DAG.getNode(ISD::SHL, DL, RegTy, LoadVal,
3797	DAG.getConstant(Shamt, DL, MVT::i32));
3798
3799	if (Val.getNode())
3800	Val = DAG.getNode(ISD::OR, DL, RegTy, Val, Shift);
3801	else
3802	Val = Shift;
3803
3804	OffsetInBytes += LoadSizeInBytes;
3805	TotalBytesLoaded += LoadSizeInBytes;
3806	Alignment = std::min(Alignment, LoadSizeInBytes);
3807	}
3808
3809	unsigned ArgReg = ArgRegs[FirstReg + I];
3810	RegsToPass.push_back(std::make_pair(ArgReg, Val));
3811	return;
3812	}
3813	}
3814
3815	// Copy remainder of byval arg to it with memcpy.
3816	unsigned MemCpySize = ByValSizeInBytes - OffsetInBytes;
3817	SDValue Src = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
3818	DAG.getConstant(OffsetInBytes, DL, PtrTy));
3819	SDValue Dst = DAG.getNode(ISD::ADD, DL, PtrTy, StackPtr,
3820	DAG.getIntPtrConstant(VA.getLocMemOffset(), DL));
3821	Chain = DAG.getMemcpy(Chain, DL, Dst, Src,
3822	DAG.getConstant(MemCpySize, DL, PtrTy),
3823	Alignment, /isVolatile=/false, /AlwaysInline=/false,
3824	/isTailCall=/false,
3825	MachinePointerInfo(), MachinePointerInfo());
3826	MemOpChains.push_back(Chain);
3827	}
3828
3829	void MipsTargetLowering::writeVarArgRegs(std::vector<SDValue> &OutChains,
3830	SDValue Chain, SDLoc DL,
3831	SelectionDAG &DAG,
3832	CCState &State) const {
3833	ArrayRef<MCPhysReg> ArgRegs = ABI.GetVarArgRegs();
3834	unsigned Idx = State.getFirstUnallocated(ArgRegs);
3835	unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes();
3836	MVT RegTy = MVT::getIntegerVT(RegSizeInBytes * 8);
3837	const TargetRegisterClass *RC = getRegClassFor(RegTy);
3838	MachineFunction &MF = DAG.getMachineFunction();
3839	MachineFrameInfo *MFI = MF.getFrameInfo();
3840	MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
3841
3842	// Offset of the first variable argument from stack pointer.
3843	int VaArgOffset;
3844
3845	if (ArgRegs.size() == Idx)
3846	VaArgOffset = alignTo(State.getNextStackOffset(), RegSizeInBytes);
3847	else {
3848	VaArgOffset =
3849	(int)ABI.GetCalleeAllocdArgSizeInBytes(State.getCallingConv()) -
3850	(int)(RegSizeInBytes * (ArgRegs.size() - Idx));
3851	}
3852
3853	// Record the frame index of the first variable argument
3854	// which is a value necessary to VASTART.
3855	int FI = MFI->CreateFixedObject(RegSizeInBytes, VaArgOffset, true);
3856	MipsFI->setVarArgsFrameIndex(FI);
3857
3858	// Copy the integer registers that have not been used for argument passing
3859	// to the argument register save area. For O32, the save area is allocated
3860	// in the caller's stack frame, while for N32/64, it is allocated in the
3861	// callee's stack frame.
3862	for (unsigned I = Idx; I < ArgRegs.size();
3863	++I, VaArgOffset += RegSizeInBytes) {
3864	unsigned Reg = addLiveIn(MF, ArgRegs[I], RC);
3865	SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegTy);
3866	FI = MFI->CreateFixedObject(RegSizeInBytes, VaArgOffset, true);
3867	SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
3868	SDValue Store = DAG.getStore(Chain, DL, ArgValue, PtrOff,
3869	MachinePointerInfo(), false, false, 0);
3870	cast<StoreSDNode>(Store.getNode())->getMemOperand()->setValue(
3871	(Value *)nullptr);
3872	OutChains.push_back(Store);
3873	}
3874	}
3875
3876	void MipsTargetLowering::HandleByVal(CCState *State, unsigned &Size,
3877	unsigned Align) const {
3878	const TargetFrameLowering *TFL = Subtarget.getFrameLowering();
3879
3880	assert(Size && "Byval argument's size shouldn't be 0.")((Size && "Byval argument's size shouldn't be 0.") ? static_cast <void> (0) : __assert_fail ("Size && \"Byval argument's size shouldn't be 0.\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MipsISelLowering.cpp" , 3880, __PRETTY_FUNCTION__));
3881
3882	Align = std::min(Align, TFL->getStackAlignment());
3883
3884	unsigned FirstReg = 0;
3885	unsigned NumRegs = 0;
3886
3887	if (State->getCallingConv() != CallingConv::Fast) {
3888	unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes();
3889	ArrayRef<MCPhysReg> IntArgRegs = ABI.GetByValArgRegs();
3890	// FIXME: The O32 case actually describes no shadow registers.
3891	const MCPhysReg *ShadowRegs =
3892	ABI.IsO32() ? IntArgRegs.data() : Mips64DPRegs;
3893
3894	// We used to check the size as well but we can't do that anymore since
3895	// CCState::HandleByVal() rounds up the size after calling this function.
3896	assert(!(Align % RegSizeInBytes) &&((!(Align % RegSizeInBytes) && "Byval argument's alignment should be a multiple of" "RegSizeInBytes.") ? static_cast<void> (0) : __assert_fail ("!(Align % RegSizeInBytes) && \"Byval argument's alignment should be a multiple of\" \"RegSizeInBytes.\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MipsISelLowering.cpp" , 3898, __PRETTY_FUNCTION__))
3897	"Byval argument's alignment should be a multiple of"((!(Align % RegSizeInBytes) && "Byval argument's alignment should be a multiple of" "RegSizeInBytes.") ? static_cast<void> (0) : __assert_fail ("!(Align % RegSizeInBytes) && \"Byval argument's alignment should be a multiple of\" \"RegSizeInBytes.\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MipsISelLowering.cpp" , 3898, __PRETTY_FUNCTION__))
3898	"RegSizeInBytes.")((!(Align % RegSizeInBytes) && "Byval argument's alignment should be a multiple of" "RegSizeInBytes.") ? static_cast<void> (0) : __assert_fail ("!(Align % RegSizeInBytes) && \"Byval argument's alignment should be a multiple of\" \"RegSizeInBytes.\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MipsISelLowering.cpp" , 3898, __PRETTY_FUNCTION__));
3899
3900	FirstReg = State->getFirstUnallocated(IntArgRegs);
3901
3902	// If Align > RegSizeInBytes, the first arg register must be even.
3903	// FIXME: This condition happens to do the right thing but it's not the
3904	// right way to test it. We want to check that the stack frame offset
3905	// of the register is aligned.
3906	if ((Align > RegSizeInBytes) && (FirstReg % 2)) {
3907	State->AllocateReg(IntArgRegs[FirstReg], ShadowRegs[FirstReg]);
3908	++FirstReg;
3909	}
3910
3911	// Mark the registers allocated.
3912	Size = alignTo(Size, RegSizeInBytes);
3913	for (unsigned I = FirstReg; Size > 0 && (I < IntArgRegs.size());
3914	Size -= RegSizeInBytes, ++I, ++NumRegs)
3915	State->AllocateReg(IntArgRegs[I], ShadowRegs[I]);
3916	}
3917
3918	State->addInRegsParamInfo(FirstReg, FirstReg + NumRegs);
3919	}
3920
3921	MachineBasicBlock *
3922	MipsTargetLowering::emitPseudoSELECT(MachineInstr MI, MachineBasicBlock BB,
3923	bool isFPCmp, unsigned Opc) const {
3924	assert(!(Subtarget.hasMips4() \|\| Subtarget.hasMips32()) &&((!(Subtarget.hasMips4() \|\| Subtarget.hasMips32()) && "Subtarget already supports SELECT nodes with the use of" "conditional-move instructions." ) ? static_cast<void> (0) : __assert_fail ("!(Subtarget.hasMips4() \|\| Subtarget.hasMips32()) && \"Subtarget already supports SELECT nodes with the use of\" \"conditional-move instructions.\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MipsISelLowering.cpp" , 3926, __PRETTY_FUNCTION__))
3925	"Subtarget already supports SELECT nodes with the use of"((!(Subtarget.hasMips4() \|\| Subtarget.hasMips32()) && "Subtarget already supports SELECT nodes with the use of" "conditional-move instructions." ) ? static_cast<void> (0) : __assert_fail ("!(Subtarget.hasMips4() \|\| Subtarget.hasMips32()) && \"Subtarget already supports SELECT nodes with the use of\" \"conditional-move instructions.\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MipsISelLowering.cpp" , 3926, __PRETTY_FUNCTION__))
3926	"conditional-move instructions.")((!(Subtarget.hasMips4() \|\| Subtarget.hasMips32()) && "Subtarget already supports SELECT nodes with the use of" "conditional-move instructions." ) ? static_cast<void> (0) : __assert_fail ("!(Subtarget.hasMips4() \|\| Subtarget.hasMips32()) && \"Subtarget already supports SELECT nodes with the use of\" \"conditional-move instructions.\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MipsISelLowering.cpp" , 3926, __PRETTY_FUNCTION__));
3927
3928	const TargetInstrInfo *TII =
3929	Subtarget.getInstrInfo();
3930	DebugLoc DL = MI->getDebugLoc();
3931
3932	// To "insert" a SELECT instruction, we actually have to insert the
3933	// diamond control-flow pattern. The incoming instruction knows the
3934	// destination vreg to set, the condition code register to branch on, the
3935	// true/false values to select between, and a branch opcode to use.
3936	const BasicBlock *LLVM_BB = BB->getBasicBlock();
3937	MachineFunction::iterator It = ++BB->getIterator();
3938
3939	// thisMBB:
3940	// ...
3941	// TrueVal = ...
3942	// setcc r1, r2, r3
3943	// bNE r1, r0, copy1MBB
3944	// fallthrough --> copy0MBB
3945	MachineBasicBlock *thisMBB = BB;
3946	MachineFunction *F = BB->getParent();
3947	MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
3948	MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
3949	F->insert(It, copy0MBB);
3950	F->insert(It, sinkMBB);
3951
3952	// Transfer the remainder of BB and its successor edges to sinkMBB.
3953	sinkMBB->splice(sinkMBB->begin(), BB,
3954	std::next(MachineBasicBlock::iterator(MI)), BB->end());
3955	sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
3956
3957	// Next, add the true and fallthrough blocks as its successors.
3958	BB->addSuccessor(copy0MBB);
3959	BB->addSuccessor(sinkMBB);
3960
3961	if (isFPCmp) {
3962	// bc1[tf] cc, sinkMBB
3963	BuildMI(BB, DL, TII->get(Opc))
3964	.addReg(MI->getOperand(1).getReg())
3965	.addMBB(sinkMBB);
3966	} else {
3967	// bne rs, $0, sinkMBB
3968	BuildMI(BB, DL, TII->get(Opc))
3969	.addReg(MI->getOperand(1).getReg())
3970	.addReg(Mips::ZERO)
3971	.addMBB(sinkMBB);
3972	}
3973
3974	// copy0MBB:
3975	// %FalseValue = ...
3976	// # fallthrough to sinkMBB
3977	BB = copy0MBB;
3978
3979	// Update machine-CFG edges
3980	BB->addSuccessor(sinkMBB);
3981
3982	// sinkMBB:
3983	// %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
3984	// ...
3985	BB = sinkMBB;
3986
3987	BuildMI(*BB, BB->begin(), DL,
3988	TII->get(Mips::PHI), MI->getOperand(0).getReg())
3989	.addReg(MI->getOperand(2).getReg()).addMBB(thisMBB)
3990	.addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB);
3991
3992	MI->eraseFromParent(); // The pseudo instruction is gone now.
3993
3994	return BB;
3995	}
3996
3997	// FIXME? Maybe this could be a TableGen attribute on some registers and
3998	// this table could be generated automatically from RegInfo.
3999	unsigned MipsTargetLowering::getRegisterByName(const char* RegName, EVT VT,
4000	SelectionDAG &DAG) const {
4001	// Named registers is expected to be fairly rare. For now, just support $28
4002	// since the linux kernel uses it.
4003	if (Subtarget.isGP64bit()) {
4004	unsigned Reg = StringSwitch<unsigned>(RegName)
4005	.Case("$28", Mips::GP_64)
4006	.Default(0);
4007	if (Reg)
4008	return Reg;
4009	} else {
4010	unsigned Reg = StringSwitch<unsigned>(RegName)
4011	.Case("$28", Mips::GP)
4012	.Default(0);
4013	if (Reg)
4014	return Reg;
4015	}
4016	report_fatal_error("Invalid register name global variable");
4017	}