Bug Summary

File:lib/Target/Mips/MipsISelLowering.cpp
Warning:line 1955, column 3
Value stored to 'BB' is never read

Annotated Source Code

1//===- MipsISelLowering.cpp - Mips DAG Lowering Implementation ------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that Mips uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#include "MipsISelLowering.h"
16#include "InstPrinter/MipsInstPrinter.h"
17#include "MCTargetDesc/MipsBaseInfo.h"
18#include "MCTargetDesc/MipsMCTargetDesc.h"
19#include "MipsCCState.h"
20#include "MipsInstrInfo.h"
21#include "MipsMachineFunction.h"
22#include "MipsRegisterInfo.h"
23#include "MipsSubtarget.h"
24#include "MipsTargetMachine.h"
25#include "MipsTargetObjectFile.h"
26#include "llvm/ADT/APFloat.h"
27#include "llvm/ADT/ArrayRef.h"
28#include "llvm/ADT/SmallVector.h"
29#include "llvm/ADT/Statistic.h"
30#include "llvm/ADT/StringSwitch.h"
31#include "llvm/ADT/StringRef.h"
32#include "llvm/CodeGen/CallingConvLower.h"
33#include "llvm/CodeGen/FunctionLoweringInfo.h"
34#include "llvm/CodeGen/ISDOpcodes.h"
35#include "llvm/CodeGen/MachineBasicBlock.h"
36#include "llvm/CodeGen/MachineFrameInfo.h"
37#include "llvm/CodeGen/MachineFunction.h"
38#include "llvm/CodeGen/MachineInstr.h"
39#include "llvm/CodeGen/MachineInstrBuilder.h"
40#include "llvm/CodeGen/MachineJumpTableInfo.h"
41#include "llvm/CodeGen/MachineMemOperand.h"
42#include "llvm/CodeGen/MachineOperand.h"
43#include "llvm/CodeGen/MachineRegisterInfo.h"
44#include "llvm/CodeGen/MachineValueType.h"
45#include "llvm/CodeGen/RuntimeLibcalls.h"
46#include "llvm/CodeGen/SelectionDAG.h"
47#include "llvm/CodeGen/SelectionDAGNodes.h"
48#include "llvm/CodeGen/ValueTypes.h"
49#include "llvm/IR/CallingConv.h"
50#include "llvm/IR/Constants.h"
51#include "llvm/IR/DataLayout.h"
52#include "llvm/IR/DebugLoc.h"
53#include "llvm/IR/DerivedTypes.h"
54#include "llvm/IR/Function.h"
55#include "llvm/IR/GlobalValue.h"
56#include "llvm/IR/Type.h"
57#include "llvm/IR/Value.h"
58#include "llvm/MC/MCRegisterInfo.h"
59#include "llvm/Support/Casting.h"
60#include "llvm/Support/CodeGen.h"
61#include "llvm/Support/CommandLine.h"
62#include "llvm/Support/Compiler.h"
63#include "llvm/Support/ErrorHandling.h"
64#include "llvm/Support/MathExtras.h"
65#include "llvm/Target/TargetFrameLowering.h"
66#include "llvm/Target/TargetInstrInfo.h"
67#include "llvm/Target/TargetMachine.h"
68#include "llvm/Target/TargetOptions.h"
69#include "llvm/Target/TargetRegisterInfo.h"
70#include <algorithm>
71#include <cassert>
72#include <cctype>
73#include <cstdint>
74#include <deque>
75#include <iterator>
76#include <utility>
77#include <vector>
78
79using namespace llvm;
80
81#define DEBUG_TYPE"mips-lower" "mips-lower"
82
83STATISTIC(NumTailCalls, "Number of tail calls")static llvm::Statistic NumTailCalls = {"mips-lower", "NumTailCalls"
, "Number of tail calls", {0}, false}
;
84
85static cl::opt<bool>
86LargeGOT("mxgot", cl::Hidden,
87 cl::desc("MIPS: Enable GOT larger than 64k."), cl::init(false));
88
89static cl::opt<bool>
90NoZeroDivCheck("mno-check-zero-division", cl::Hidden,
91 cl::desc("MIPS: Don't trap on integer division by zero."),
92 cl::init(false));
93
94static const MCPhysReg Mips64DPRegs[8] = {
95 Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64,
96 Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64
97};
98
99// If I is a shifted mask, set the size (Size) and the first bit of the
100// mask (Pos), and return true.
101// For example, if I is 0x003ff800, (Pos, Size) = (11, 11).
102static bool isShiftedMask(uint64_t I, uint64_t &Pos, uint64_t &Size) {
103 if (!isShiftedMask_64(I))
104 return false;
105
106 Size = countPopulation(I);
107 Pos = countTrailingZeros(I);
108 return true;
109}
110
111// The MIPS MSA ABI passes vector arguments in the integer register set.
112// The number of integer registers used is dependant on the ABI used.
113MVT MipsTargetLowering::getRegisterTypeForCallingConv(MVT VT) const {
114 if (VT.isVector() && Subtarget.hasMSA())
115 return Subtarget.isABI_O32() ? MVT::i32 : MVT::i64;
116 return MipsTargetLowering::getRegisterType(VT);
117}
118
119MVT MipsTargetLowering::getRegisterTypeForCallingConv(LLVMContext &Context,
120 EVT VT) const {
121 if (VT.isVector()) {
122 if (Subtarget.isABI_O32()) {
123 return MVT::i32;
124 } else {
125 return (VT.getSizeInBits() == 32) ? MVT::i32 : MVT::i64;
126 }
127 }
128 return MipsTargetLowering::getRegisterType(Context, VT);
129}
130
131unsigned MipsTargetLowering::getNumRegistersForCallingConv(LLVMContext &Context,
132 EVT VT) const {
133 if (VT.isVector())
134 return std::max((VT.getSizeInBits() / (Subtarget.isABI_O32() ? 32 : 64)),
135 1U);
136 return MipsTargetLowering::getNumRegisters(Context, VT);
137}
138
139unsigned MipsTargetLowering::getVectorTypeBreakdownForCallingConv(
140 LLVMContext &Context, EVT VT, EVT &IntermediateVT,
141 unsigned &NumIntermediates, MVT &RegisterVT) const {
142 // Break down vector types to either 2 i64s or 4 i32s.
143 RegisterVT = getRegisterTypeForCallingConv(Context, VT) ;
144 IntermediateVT = RegisterVT;
145 NumIntermediates = VT.getSizeInBits() < RegisterVT.getSizeInBits()
146 ? VT.getVectorNumElements()
147 : VT.getSizeInBits() / RegisterVT.getSizeInBits();
148
149 return NumIntermediates;
150}
151
152SDValue MipsTargetLowering::getGlobalReg(SelectionDAG &DAG, EVT Ty) const {
153 MipsFunctionInfo *FI = DAG.getMachineFunction().getInfo<MipsFunctionInfo>();
154 return DAG.getRegister(FI->getGlobalBaseReg(), Ty);
155}
156
157SDValue MipsTargetLowering::getTargetNode(GlobalAddressSDNode *N, EVT Ty,
158 SelectionDAG &DAG,
159 unsigned Flag) const {
160 return DAG.getTargetGlobalAddress(N->getGlobal(), SDLoc(N), Ty, 0, Flag);
161}
162
163SDValue MipsTargetLowering::getTargetNode(ExternalSymbolSDNode *N, EVT Ty,
164 SelectionDAG &DAG,
165 unsigned Flag) const {
166 return DAG.getTargetExternalSymbol(N->getSymbol(), Ty, Flag);
167}
168
169SDValue MipsTargetLowering::getTargetNode(BlockAddressSDNode *N, EVT Ty,
170 SelectionDAG &DAG,
171 unsigned Flag) const {
172 return DAG.getTargetBlockAddress(N->getBlockAddress(), Ty, 0, Flag);
173}
174
175SDValue MipsTargetLowering::getTargetNode(JumpTableSDNode *N, EVT Ty,
176 SelectionDAG &DAG,
177 unsigned Flag) const {
178 return DAG.getTargetJumpTable(N->getIndex(), Ty, Flag);
179}
180
181SDValue MipsTargetLowering::getTargetNode(ConstantPoolSDNode *N, EVT Ty,
182 SelectionDAG &DAG,
183 unsigned Flag) const {
184 return DAG.getTargetConstantPool(N->getConstVal(), Ty, N->getAlignment(),
185 N->getOffset(), Flag);
186}
187
188const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
189 switch ((MipsISD::NodeType)Opcode) {
190 case MipsISD::FIRST_NUMBER: break;
191 case MipsISD::JmpLink: return "MipsISD::JmpLink";
192 case MipsISD::TailCall: return "MipsISD::TailCall";
193 case MipsISD::Highest: return "MipsISD::Highest";
194 case MipsISD::Higher: return "MipsISD::Higher";
195 case MipsISD::Hi: return "MipsISD::Hi";
196 case MipsISD::Lo: return "MipsISD::Lo";
197 case MipsISD::GotHi: return "MipsISD::GotHi";
198 case MipsISD::GPRel: return "MipsISD::GPRel";
199 case MipsISD::ThreadPointer: return "MipsISD::ThreadPointer";
200 case MipsISD::Ret: return "MipsISD::Ret";
201 case MipsISD::ERet: return "MipsISD::ERet";
202 case MipsISD::EH_RETURN: return "MipsISD::EH_RETURN";
203 case MipsISD::FPBrcond: return "MipsISD::FPBrcond";
204 case MipsISD::FPCmp: return "MipsISD::FPCmp";
205 case MipsISD::FSELECT: return "MipsISD::FSELECT";
206 case MipsISD::MTC1_D64: return "MipsISD::MTC1_D64";
207 case MipsISD::CMovFP_T: return "MipsISD::CMovFP_T";
208 case MipsISD::CMovFP_F: return "MipsISD::CMovFP_F";
209 case MipsISD::TruncIntFP: return "MipsISD::TruncIntFP";
210 case MipsISD::MFHI: return "MipsISD::MFHI";
211 case MipsISD::MFLO: return "MipsISD::MFLO";
212 case MipsISD::MTLOHI: return "MipsISD::MTLOHI";
213 case MipsISD::Mult: return "MipsISD::Mult";
214 case MipsISD::Multu: return "MipsISD::Multu";
215 case MipsISD::MAdd: return "MipsISD::MAdd";
216 case MipsISD::MAddu: return "MipsISD::MAddu";
217 case MipsISD::MSub: return "MipsISD::MSub";
218 case MipsISD::MSubu: return "MipsISD::MSubu";
219 case MipsISD::DivRem: return "MipsISD::DivRem";
220 case MipsISD::DivRemU: return "MipsISD::DivRemU";
221 case MipsISD::DivRem16: return "MipsISD::DivRem16";
222 case MipsISD::DivRemU16: return "MipsISD::DivRemU16";
223 case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64";
224 case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64";
225 case MipsISD::Wrapper: return "MipsISD::Wrapper";
226 case MipsISD::DynAlloc: return "MipsISD::DynAlloc";
227 case MipsISD::Sync: return "MipsISD::Sync";
228 case MipsISD::Ext: return "MipsISD::Ext";
229 case MipsISD::Ins: return "MipsISD::Ins";
230 case MipsISD::CIns: return "MipsISD::CIns";
231 case MipsISD::LWL: return "MipsISD::LWL";
232 case MipsISD::LWR: return "MipsISD::LWR";
233 case MipsISD::SWL: return "MipsISD::SWL";
234 case MipsISD::SWR: return "MipsISD::SWR";
235 case MipsISD::LDL: return "MipsISD::LDL";
236 case MipsISD::LDR: return "MipsISD::LDR";
237 case MipsISD::SDL: return "MipsISD::SDL";
238 case MipsISD::SDR: return "MipsISD::SDR";
239 case MipsISD::EXTP: return "MipsISD::EXTP";
240 case MipsISD::EXTPDP: return "MipsISD::EXTPDP";
241 case MipsISD::EXTR_S_H: return "MipsISD::EXTR_S_H";
242 case MipsISD::EXTR_W: return "MipsISD::EXTR_W";
243 case MipsISD::EXTR_R_W: return "MipsISD::EXTR_R_W";
244 case MipsISD::EXTR_RS_W: return "MipsISD::EXTR_RS_W";
245 case MipsISD::SHILO: return "MipsISD::SHILO";
246 case MipsISD::MTHLIP: return "MipsISD::MTHLIP";
247 case MipsISD::MULSAQ_S_W_PH: return "MipsISD::MULSAQ_S_W_PH";
248 case MipsISD::MAQ_S_W_PHL: return "MipsISD::MAQ_S_W_PHL";
249 case MipsISD::MAQ_S_W_PHR: return "MipsISD::MAQ_S_W_PHR";
250 case MipsISD::MAQ_SA_W_PHL: return "MipsISD::MAQ_SA_W_PHL";
251 case MipsISD::MAQ_SA_W_PHR: return "MipsISD::MAQ_SA_W_PHR";
252 case MipsISD::DPAU_H_QBL: return "MipsISD::DPAU_H_QBL";
253 case MipsISD::DPAU_H_QBR: return "MipsISD::DPAU_H_QBR";
254 case MipsISD::DPSU_H_QBL: return "MipsISD::DPSU_H_QBL";
255 case MipsISD::DPSU_H_QBR: return "MipsISD::DPSU_H_QBR";
256 case MipsISD::DPAQ_S_W_PH: return "MipsISD::DPAQ_S_W_PH";
257 case MipsISD::DPSQ_S_W_PH: return "MipsISD::DPSQ_S_W_PH";
258 case MipsISD::DPAQ_SA_L_W: return "MipsISD::DPAQ_SA_L_W";
259 case MipsISD::DPSQ_SA_L_W: return "MipsISD::DPSQ_SA_L_W";
260 case MipsISD::DPA_W_PH: return "MipsISD::DPA_W_PH";
261 case MipsISD::DPS_W_PH: return "MipsISD::DPS_W_PH";
262 case MipsISD::DPAQX_S_W_PH: return "MipsISD::DPAQX_S_W_PH";
263 case MipsISD::DPAQX_SA_W_PH: return "MipsISD::DPAQX_SA_W_PH";
264 case MipsISD::DPAX_W_PH: return "MipsISD::DPAX_W_PH";
265 case MipsISD::DPSX_W_PH: return "MipsISD::DPSX_W_PH";
266 case MipsISD::DPSQX_S_W_PH: return "MipsISD::DPSQX_S_W_PH";
267 case MipsISD::DPSQX_SA_W_PH: return "MipsISD::DPSQX_SA_W_PH";
268 case MipsISD::MULSA_W_PH: return "MipsISD::MULSA_W_PH";
269 case MipsISD::MULT: return "MipsISD::MULT";
270 case MipsISD::MULTU: return "MipsISD::MULTU";
271 case MipsISD::MADD_DSP: return "MipsISD::MADD_DSP";
272 case MipsISD::MADDU_DSP: return "MipsISD::MADDU_DSP";
273 case MipsISD::MSUB_DSP: return "MipsISD::MSUB_DSP";
274 case MipsISD::MSUBU_DSP: return "MipsISD::MSUBU_DSP";
275 case MipsISD::SHLL_DSP: return "MipsISD::SHLL_DSP";
276 case MipsISD::SHRA_DSP: return "MipsISD::SHRA_DSP";
277 case MipsISD::SHRL_DSP: return "MipsISD::SHRL_DSP";
278 case MipsISD::SETCC_DSP: return "MipsISD::SETCC_DSP";
279 case MipsISD::SELECT_CC_DSP: return "MipsISD::SELECT_CC_DSP";
280 case MipsISD::VALL_ZERO: return "MipsISD::VALL_ZERO";
281 case MipsISD::VANY_ZERO: return "MipsISD::VANY_ZERO";
282 case MipsISD::VALL_NONZERO: return "MipsISD::VALL_NONZERO";
283 case MipsISD::VANY_NONZERO: return "MipsISD::VANY_NONZERO";
284 case MipsISD::VCEQ: return "MipsISD::VCEQ";
285 case MipsISD::VCLE_S: return "MipsISD::VCLE_S";
286 case MipsISD::VCLE_U: return "MipsISD::VCLE_U";
287 case MipsISD::VCLT_S: return "MipsISD::VCLT_S";
288 case MipsISD::VCLT_U: return "MipsISD::VCLT_U";
289 case MipsISD::VSMAX: return "MipsISD::VSMAX";
290 case MipsISD::VSMIN: return "MipsISD::VSMIN";
291 case MipsISD::VUMAX: return "MipsISD::VUMAX";
292 case MipsISD::VUMIN: return "MipsISD::VUMIN";
293 case MipsISD::VEXTRACT_SEXT_ELT: return "MipsISD::VEXTRACT_SEXT_ELT";
294 case MipsISD::VEXTRACT_ZEXT_ELT: return "MipsISD::VEXTRACT_ZEXT_ELT";
295 case MipsISD::VNOR: return "MipsISD::VNOR";
296 case MipsISD::VSHF: return "MipsISD::VSHF";
297 case MipsISD::SHF: return "MipsISD::SHF";
298 case MipsISD::ILVEV: return "MipsISD::ILVEV";
299 case MipsISD::ILVOD: return "MipsISD::ILVOD";
300 case MipsISD::ILVL: return "MipsISD::ILVL";
301 case MipsISD::ILVR: return "MipsISD::ILVR";
302 case MipsISD::PCKEV: return "MipsISD::PCKEV";
303 case MipsISD::PCKOD: return "MipsISD::PCKOD";
304 case MipsISD::INSVE: return "MipsISD::INSVE";
305 }
306 return nullptr;
307}
308
309MipsTargetLowering::MipsTargetLowering(const MipsTargetMachine &TM,
310 const MipsSubtarget &STI)
311 : TargetLowering(TM), Subtarget(STI), ABI(TM.getABI()) {
312 // Mips does not have i1 type, so use i32 for
313 // setcc operations results (slt, sgt, ...).
314 setBooleanContents(ZeroOrOneBooleanContent);
315 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
316 // The cmp.cond.fmt instruction in MIPS32r6/MIPS64r6 uses 0 and -1 like MSA
317 // does. Integer booleans still use 0 and 1.
318 if (Subtarget.hasMips32r6())
319 setBooleanContents(ZeroOrOneBooleanContent,
320 ZeroOrNegativeOneBooleanContent);
321
322 // Load extented operations for i1 types must be promoted
323 for (MVT VT : MVT::integer_valuetypes()) {
324 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
325 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
326 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
327 }
328
329 // MIPS doesn't have extending float->double load/store. Set LoadExtAction
330 // for f32, f16
331 for (MVT VT : MVT::fp_valuetypes()) {
332 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
333 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand);
334 }
335
336 // Set LoadExtAction for f16 vectors to Expand
337 for (MVT VT : MVT::fp_vector_valuetypes()) {
338 MVT F16VT = MVT::getVectorVT(MVT::f16, VT.getVectorNumElements());
339 if (F16VT.isValid())
340 setLoadExtAction(ISD::EXTLOAD, VT, F16VT, Expand);
341 }
342
343 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
344 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
345
346 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
347
348 // Used by legalize types to correctly generate the setcc result.
349 // Without this, every float setcc comes with a AND/OR with the result,
350 // we don't want this, since the fpcmp result goes to a flag register,
351 // which is used implicitly by brcond and select operations.
352 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
353
354 // Mips Custom Operations
355 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
356 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
357 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
358 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
359 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
360 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
361 setOperationAction(ISD::SELECT, MVT::f32, Custom);
362 setOperationAction(ISD::SELECT, MVT::f64, Custom);
363 setOperationAction(ISD::SELECT, MVT::i32, Custom);
364 setOperationAction(ISD::SETCC, MVT::f32, Custom);
365 setOperationAction(ISD::SETCC, MVT::f64, Custom);
366 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
367 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
368 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
369 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
370
371 if (Subtarget.isGP64bit()) {
372 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
373 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
374 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
375 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
376 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
377 setOperationAction(ISD::SELECT, MVT::i64, Custom);
378 setOperationAction(ISD::LOAD, MVT::i64, Custom);
379 setOperationAction(ISD::STORE, MVT::i64, Custom);
380 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
381 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
382 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
383 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
384 }
385
386 if (!Subtarget.isGP64bit()) {
387 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
388 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
389 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
390 }
391
392 setOperationAction(ISD::EH_DWARF_CFA, MVT::i32, Custom);
393 if (Subtarget.isGP64bit())
394 setOperationAction(ISD::EH_DWARF_CFA, MVT::i64, Custom);
395
396 setOperationAction(ISD::SDIV, MVT::i32, Expand);
397 setOperationAction(ISD::SREM, MVT::i32, Expand);
398 setOperationAction(ISD::UDIV, MVT::i32, Expand);
399 setOperationAction(ISD::UREM, MVT::i32, Expand);
400 setOperationAction(ISD::SDIV, MVT::i64, Expand);
401 setOperationAction(ISD::SREM, MVT::i64, Expand);
402 setOperationAction(ISD::UDIV, MVT::i64, Expand);
403 setOperationAction(ISD::UREM, MVT::i64, Expand);
404
405 if (!(Subtarget.hasDSP() && Subtarget.hasMips32r2())) {
406 setOperationAction(ISD::ADDC, MVT::i32, Expand);
407 setOperationAction(ISD::ADDE, MVT::i32, Expand);
408 }
409
410 setOperationAction(ISD::ADDC, MVT::i64, Expand);
411 setOperationAction(ISD::ADDE, MVT::i64, Expand);
412 setOperationAction(ISD::SUBC, MVT::i32, Expand);
413 setOperationAction(ISD::SUBE, MVT::i32, Expand);
414 setOperationAction(ISD::SUBC, MVT::i64, Expand);
415 setOperationAction(ISD::SUBE, MVT::i64, Expand);
416
417 // Operations not directly supported by Mips.
418 setOperationAction(ISD::BR_CC, MVT::f32, Expand);
419 setOperationAction(ISD::BR_CC, MVT::f64, Expand);
420 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
421 setOperationAction(ISD::BR_CC, MVT::i64, Expand);
422 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
423 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
424 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
425 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
426 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
427 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
428 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
429 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
430 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
431 if (Subtarget.hasCnMips()) {
432 setOperationAction(ISD::CTPOP, MVT::i32, Legal);
433 setOperationAction(ISD::CTPOP, MVT::i64, Legal);
434 } else {
435 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
436 setOperationAction(ISD::CTPOP, MVT::i64, Expand);
437 }
438 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
439 setOperationAction(ISD::CTTZ, MVT::i64, Expand);
440 setOperationAction(ISD::ROTL, MVT::i32, Expand);
441 setOperationAction(ISD::ROTL, MVT::i64, Expand);
442 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
443 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
444
445 if (!Subtarget.hasMips32r2())
446 setOperationAction(ISD::ROTR, MVT::i32, Expand);
447
448 if (!Subtarget.hasMips64r2())
449 setOperationAction(ISD::ROTR, MVT::i64, Expand);
450
451 setOperationAction(ISD::FSIN, MVT::f32, Expand);
452 setOperationAction(ISD::FSIN, MVT::f64, Expand);
453 setOperationAction(ISD::FCOS, MVT::f32, Expand);
454 setOperationAction(ISD::FCOS, MVT::f64, Expand);
455 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
456 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
457 setOperationAction(ISD::FPOW, MVT::f32, Expand);
458 setOperationAction(ISD::FPOW, MVT::f64, Expand);
459 setOperationAction(ISD::FLOG, MVT::f32, Expand);
460 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
461 setOperationAction(ISD::FLOG10, MVT::f32, Expand);
462 setOperationAction(ISD::FEXP, MVT::f32, Expand);
463 setOperationAction(ISD::FMA, MVT::f32, Expand);
464 setOperationAction(ISD::FMA, MVT::f64, Expand);
465 setOperationAction(ISD::FREM, MVT::f32, Expand);
466 setOperationAction(ISD::FREM, MVT::f64, Expand);
467
468 // Lower f16 conversion operations into library calls
469 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
470 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
471 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
472 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
473
474 setOperationAction(ISD::EH_RETURN, MVT::Other, Custom);
475
476 setOperationAction(ISD::VASTART, MVT::Other, Custom);
477 setOperationAction(ISD::VAARG, MVT::Other, Custom);
478 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
479 setOperationAction(ISD::VAEND, MVT::Other, Expand);
480
481 // Use the default for now
482 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
483 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
484
485 if (!Subtarget.isGP64bit()) {
486 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
487 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
488 }
489
490 if (!Subtarget.hasMips32r2()) {
491 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
492 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
493 }
494
495 // MIPS16 lacks MIPS32's clz and clo instructions.
496 if (!Subtarget.hasMips32() || Subtarget.inMips16Mode())
497 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
498 if (!Subtarget.hasMips64())
499 setOperationAction(ISD::CTLZ, MVT::i64, Expand);
500
501 if (!Subtarget.hasMips32r2())
502 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
503 if (!Subtarget.hasMips64r2())
504 setOperationAction(ISD::BSWAP, MVT::i64, Expand);
505
506 if (Subtarget.isGP64bit()) {
507 setLoadExtAction(ISD::SEXTLOAD, MVT::i64, MVT::i32, Custom);
508 setLoadExtAction(ISD::ZEXTLOAD, MVT::i64, MVT::i32, Custom);
509 setLoadExtAction(ISD::EXTLOAD, MVT::i64, MVT::i32, Custom);
510 setTruncStoreAction(MVT::i64, MVT::i32, Custom);
511 }
512
513 setOperationAction(ISD::TRAP, MVT::Other, Legal);
514
515 setTargetDAGCombine(ISD::SDIVREM);
516 setTargetDAGCombine(ISD::UDIVREM);
517 setTargetDAGCombine(ISD::SELECT);
518 setTargetDAGCombine(ISD::AND);
519 setTargetDAGCombine(ISD::OR);
520 setTargetDAGCombine(ISD::ADD);
521 setTargetDAGCombine(ISD::SUB);
522 setTargetDAGCombine(ISD::AssertZext);
523 setTargetDAGCombine(ISD::SHL);
524
525 if (ABI.IsO32()) {
526 // These libcalls are not available in 32-bit.
527 setLibcallName(RTLIB::SHL_I128, nullptr);
528 setLibcallName(RTLIB::SRL_I128, nullptr);
529 setLibcallName(RTLIB::SRA_I128, nullptr);
530 }
531
532 setMinFunctionAlignment(Subtarget.isGP64bit() ? 3 : 2);
533
534 // The arguments on the stack are defined in terms of 4-byte slots on O32
535 // and 8-byte slots on N32/N64.
536 setMinStackArgumentAlignment((ABI.IsN32() || ABI.IsN64()) ? 8 : 4);
537
538 setStackPointerRegisterToSaveRestore(ABI.IsN64() ? Mips::SP_64 : Mips::SP);
539
540 MaxStoresPerMemcpy = 16;
541
542 isMicroMips = Subtarget.inMicroMipsMode();
543}
544
545const MipsTargetLowering *MipsTargetLowering::create(const MipsTargetMachine &TM,
546 const MipsSubtarget &STI) {
547 if (STI.inMips16Mode())
548 return createMips16TargetLowering(TM, STI);
549
550 return createMipsSETargetLowering(TM, STI);
551}
552
553// Create a fast isel object.
554FastISel *
555MipsTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
556 const TargetLibraryInfo *libInfo) const {
557 const MipsTargetMachine &TM =
558 static_cast<const MipsTargetMachine &>(funcInfo.MF->getTarget());
559
560 // We support only the standard encoding [MIPS32,MIPS32R5] ISAs.
561 bool UseFastISel = TM.Options.EnableFastISel && Subtarget.hasMips32() &&
562 !Subtarget.hasMips32r6() && !Subtarget.inMips16Mode() &&
563 !Subtarget.inMicroMipsMode();
564
565 // Disable if either of the following is true:
566 // We do not generate PIC, the ABI is not O32, LargeGOT is being used.
567 if (!TM.isPositionIndependent() || !TM.getABI().IsO32() || LargeGOT)
568 UseFastISel = false;
569
570 return UseFastISel ? Mips::createFastISel(funcInfo, libInfo) : nullptr;
571}
572
573EVT MipsTargetLowering::getSetCCResultType(const DataLayout &, LLVMContext &,
574 EVT VT) const {
575 if (!VT.isVector())
576 return MVT::i32;
577 return VT.changeVectorElementTypeToInteger();
578}
579
580static SDValue performDivRemCombine(SDNode *N, SelectionDAG &DAG,
581 TargetLowering::DAGCombinerInfo &DCI,
582 const MipsSubtarget &Subtarget) {
583 if (DCI.isBeforeLegalizeOps())
584 return SDValue();
585
586 EVT Ty = N->getValueType(0);
587 unsigned LO = (Ty == MVT::i32) ? Mips::LO0 : Mips::LO0_64;
588 unsigned HI = (Ty == MVT::i32) ? Mips::HI0 : Mips::HI0_64;
589 unsigned Opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem16 :
590 MipsISD::DivRemU16;
591 SDLoc DL(N);
592
593 SDValue DivRem = DAG.getNode(Opc, DL, MVT::Glue,
594 N->getOperand(0), N->getOperand(1));
595 SDValue InChain = DAG.getEntryNode();
596 SDValue InGlue = DivRem;
597
598 // insert MFLO
599 if (N->hasAnyUseOfValue(0)) {
600 SDValue CopyFromLo = DAG.getCopyFromReg(InChain, DL, LO, Ty,
601 InGlue);
602 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo);
603 InChain = CopyFromLo.getValue(1);
604 InGlue = CopyFromLo.getValue(2);
605 }
606
607 // insert MFHI
608 if (N->hasAnyUseOfValue(1)) {
609 SDValue CopyFromHi = DAG.getCopyFromReg(InChain, DL,
610 HI, Ty, InGlue);
611 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi);
612 }
613
614 return SDValue();
615}
616
617static Mips::CondCode condCodeToFCC(ISD::CondCode CC) {
618 switch (CC) {
619 default: llvm_unreachable("Unknown fp condition code!")::llvm::llvm_unreachable_internal("Unknown fp condition code!"
, "/build/llvm-toolchain-snapshot-6.0~svn316068/lib/Target/Mips/MipsISelLowering.cpp"
, 619)
;
620 case ISD::SETEQ:
621 case ISD::SETOEQ: return Mips::FCOND_OEQ;
622 case ISD::SETUNE: return Mips::FCOND_UNE;
623 case ISD::SETLT:
624 case ISD::SETOLT: return Mips::FCOND_OLT;
625 case ISD::SETGT:
626 case ISD::SETOGT: return Mips::FCOND_OGT;
627 case ISD::SETLE:
628 case ISD::SETOLE: return Mips::FCOND_OLE;
629 case ISD::SETGE:
630 case ISD::SETOGE: return Mips::FCOND_OGE;
631 case ISD::SETULT: return Mips::FCOND_ULT;
632 case ISD::SETULE: return Mips::FCOND_ULE;
633 case ISD::SETUGT: return Mips::FCOND_UGT;
634 case ISD::SETUGE: return Mips::FCOND_UGE;
635 case ISD::SETUO: return Mips::FCOND_UN;
636 case ISD::SETO: return Mips::FCOND_OR;
637 case ISD::SETNE:
638 case ISD::SETONE: return Mips::FCOND_ONE;
639 case ISD::SETUEQ: return Mips::FCOND_UEQ;
640 }
641}
642
643/// This function returns true if the floating point conditional branches and
644/// conditional moves which use condition code CC should be inverted.
645static bool invertFPCondCodeUser(Mips::CondCode CC) {
646 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
647 return false;
648
649 assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) &&(((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT)
&& "Illegal Condition Code") ? static_cast<void>
(0) : __assert_fail ("(CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) && \"Illegal Condition Code\""
, "/build/llvm-toolchain-snapshot-6.0~svn316068/lib/Target/Mips/MipsISelLowering.cpp"
, 650, __PRETTY_FUNCTION__))
650 "Illegal Condition Code")(((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT)
&& "Illegal Condition Code") ? static_cast<void>
(0) : __assert_fail ("(CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) && \"Illegal Condition Code\""
, "/build/llvm-toolchain-snapshot-6.0~svn316068/lib/Target/Mips/MipsISelLowering.cpp"
, 650, __PRETTY_FUNCTION__))
;
651
652 return true;
653}
654
655// Creates and returns an FPCmp node from a setcc node.
656// Returns Op if setcc is not a floating point comparison.
657static SDValue createFPCmp(SelectionDAG &DAG, const SDValue &Op) {
658 // must be a SETCC node
659 if (Op.getOpcode() != ISD::SETCC)
660 return Op;
661
662 SDValue LHS = Op.getOperand(0);
663
664 if (!LHS.getValueType().isFloatingPoint())
665 return Op;
666
667 SDValue RHS = Op.getOperand(1);
668 SDLoc DL(Op);
669
670 // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of
671 // node if necessary.
672 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
673
674 return DAG.getNode(MipsISD::FPCmp, DL, MVT::Glue, LHS, RHS,
675 DAG.getConstant(condCodeToFCC(CC), DL, MVT::i32));
676}
677
678// Creates and returns a CMovFPT/F node.
679static SDValue createCMovFP(SelectionDAG &DAG, SDValue Cond, SDValue True,
680 SDValue False, const SDLoc &DL) {
681 ConstantSDNode *CC = cast<ConstantSDNode>(Cond.getOperand(2));
682 bool invert = invertFPCondCodeUser((Mips::CondCode)CC->getSExtValue());
683 SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32);
684
685 return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL,
686 True.getValueType(), True, FCC0, False, Cond);
687}
688
689static SDValue performSELECTCombine(SDNode *N, SelectionDAG &DAG,
690 TargetLowering::DAGCombinerInfo &DCI,
691 const MipsSubtarget &Subtarget) {
692 if (DCI.isBeforeLegalizeOps())
693 return SDValue();
694
695 SDValue SetCC = N->getOperand(0);
696
697 if ((SetCC.getOpcode() != ISD::SETCC) ||
698 !SetCC.getOperand(0).getValueType().isInteger())
699 return SDValue();
700
701 SDValue False = N->getOperand(2);
702 EVT FalseTy = False.getValueType();
703
704 if (!FalseTy.isInteger())
705 return SDValue();
706
707 ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(False);
708
709 // If the RHS (False) is 0, we swap the order of the operands
710 // of ISD::SELECT (obviously also inverting the condition) so that we can
711 // take advantage of conditional moves using the $0 register.
712 // Example:
713 // return (a != 0) ? x : 0;
714 // load $reg, x
715 // movz $reg, $0, a
716 if (!FalseC)
717 return SDValue();
718
719 const SDLoc DL(N);
720
721 if (!FalseC->getZExtValue()) {
722 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get();
723 SDValue True = N->getOperand(1);
724
725 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0),
726 SetCC.getOperand(1), ISD::getSetCCInverse(CC, true));
727
728 return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True);
729 }
730
731 // If both operands are integer constants there's a possibility that we
732 // can do some interesting optimizations.
733 SDValue True = N->getOperand(1);
734 ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(True);
735
736 if (!TrueC || !True.getValueType().isInteger())
737 return SDValue();
738
739 // We'll also ignore MVT::i64 operands as this optimizations proves
740 // to be ineffective because of the required sign extensions as the result
741 // of a SETCC operator is always MVT::i32 for non-vector types.
742 if (True.getValueType() == MVT::i64)
743 return SDValue();
744
745 int64_t Diff = TrueC->getSExtValue() - FalseC->getSExtValue();
746
747 // 1) (a < x) ? y : y-1
748 // slti $reg1, a, x
749 // addiu $reg2, $reg1, y-1
750 if (Diff == 1)
751 return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, False);
752
753 // 2) (a < x) ? y-1 : y
754 // slti $reg1, a, x
755 // xor $reg1, $reg1, 1
756 // addiu $reg2, $reg1, y-1
757 if (Diff == -1) {
758 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get();
759 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0),
760 SetCC.getOperand(1), ISD::getSetCCInverse(CC, true));
761 return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, True);
762 }
763
764 // Couldn't optimize.
765 return SDValue();
766}
767
768static SDValue performCMovFPCombine(SDNode *N, SelectionDAG &DAG,
769 TargetLowering::DAGCombinerInfo &DCI,
770 const MipsSubtarget &Subtarget) {
771 if (DCI.isBeforeLegalizeOps())
772 return SDValue();
773
774 SDValue ValueIfTrue = N->getOperand(0), ValueIfFalse = N->getOperand(2);
775
776 ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(ValueIfFalse);
777 if (!FalseC || FalseC->getZExtValue())
778 return SDValue();
779
780 // Since RHS (False) is 0, we swap the order of the True/False operands
781 // (obviously also inverting the condition) so that we can
782 // take advantage of conditional moves using the $0 register.
783 // Example:
784 // return (a != 0) ? x : 0;
785 // load $reg, x
786 // movz $reg, $0, a
787 unsigned Opc = (N->getOpcode() == MipsISD::CMovFP_T) ? MipsISD::CMovFP_F :
788 MipsISD::CMovFP_T;
789
790 SDValue FCC = N->getOperand(1), Glue = N->getOperand(3);
791 return DAG.getNode(Opc, SDLoc(N), ValueIfFalse.getValueType(),
792 ValueIfFalse, FCC, ValueIfTrue, Glue);
793}
794
795static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG,
796 TargetLowering::DAGCombinerInfo &DCI,
797 const MipsSubtarget &Subtarget) {
798 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert())
799 return SDValue();
800
801 SDValue FirstOperand = N->getOperand(0);
802 unsigned FirstOperandOpc = FirstOperand.getOpcode();
803 SDValue Mask = N->getOperand(1);
804 EVT ValTy = N->getValueType(0);
805 SDLoc DL(N);
806
807 uint64_t Pos = 0, SMPos, SMSize;
808 ConstantSDNode *CN;
809 SDValue NewOperand;
810 unsigned Opc;
811
812 // Op's second operand must be a shifted mask.
813 if (!(CN = dyn_cast<ConstantSDNode>(Mask)) ||
814 !isShiftedMask(CN->getZExtValue(), SMPos, SMSize))
815 return SDValue();
816
817 if (FirstOperandOpc == ISD::SRA || FirstOperandOpc == ISD::SRL) {
818 // Pattern match EXT.
819 // $dst = and ((sra or srl) $src , pos), (2**size - 1)
820 // => ext $dst, $src, pos, size
821
822 // The second operand of the shift must be an immediate.
823 if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.getOperand(1))))
824 return SDValue();
825
826 Pos = CN->getZExtValue();
827
828 // Return if the shifted mask does not start at bit 0 or the sum of its size
829 // and Pos exceeds the word's size.
830 if (SMPos != 0 || Pos + SMSize > ValTy.getSizeInBits())
831 return SDValue();
832
833 Opc = MipsISD::Ext;
834 NewOperand = FirstOperand.getOperand(0);
835 } else if (FirstOperandOpc == ISD::SHL && Subtarget.hasCnMips()) {
836 // Pattern match CINS.
837 // $dst = and (shl $src , pos), mask
838 // => cins $dst, $src, pos, size
839 // mask is a shifted mask with consecutive 1's, pos = shift amount,
840 // size = population count.
841
842 // The second operand of the shift must be an immediate.
843 if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.getOperand(1))))
844 return SDValue();
845
846 Pos = CN->getZExtValue();
847
848 if (SMPos != Pos || Pos >= ValTy.getSizeInBits() || SMSize >= 32 ||
849 Pos + SMSize > ValTy.getSizeInBits())
850 return SDValue();
851
852 NewOperand = FirstOperand.getOperand(0);
853 // SMSize is 'location' (position) in this case, not size.
854 SMSize--;
855 Opc = MipsISD::CIns;
856 } else {
857 // Pattern match EXT.
858 // $dst = and $src, (2**size - 1) , if size > 16
859 // => ext $dst, $src, pos, size , pos = 0
860
861 // If the mask is <= 0xffff, andi can be used instead.
862 if (CN->getZExtValue() <= 0xffff)
863 return SDValue();
864
865 // Return if the mask doesn't start at position 0.
866 if (SMPos)
867 return SDValue();
868
869 Opc = MipsISD::Ext;
870 NewOperand = FirstOperand;
871 }
872 return DAG.getNode(Opc, DL, ValTy, NewOperand,
873 DAG.getConstant(Pos, DL, MVT::i32),
874 DAG.getConstant(SMSize, DL, MVT::i32));
875}
876
877static SDValue performORCombine(SDNode *N, SelectionDAG &DAG,
878 TargetLowering::DAGCombinerInfo &DCI,
879 const MipsSubtarget &Subtarget) {
880 // Pattern match INS.
881 // $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1),
882 // where mask1 = (2**size - 1) << pos, mask0 = ~mask1
883 // => ins $dst, $src, size, pos, $src1
884 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert())
885 return SDValue();
886
887 SDValue And0 = N->getOperand(0), And1 = N->getOperand(1);
888 uint64_t SMPos0, SMSize0, SMPos1, SMSize1;
889 ConstantSDNode *CN, *CN1;
890
891 // See if Op's first operand matches (and $src1 , mask0).
892 if (And0.getOpcode() != ISD::AND)
893 return SDValue();
894
895 if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) ||
896 !isShiftedMask(~CN->getSExtValue(), SMPos0, SMSize0))
897 return SDValue();
898
899 // See if Op's second operand matches (and (shl $src, pos), mask1).
900 if (And1.getOpcode() == ISD::AND &&
901 And1.getOperand(0).getOpcode() == ISD::SHL) {
902
903 if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) ||
904 !isShiftedMask(CN->getZExtValue(), SMPos1, SMSize1))
905 return SDValue();
906
907 // The shift masks must have the same position and size.
908 if (SMPos0 != SMPos1 || SMSize0 != SMSize1)
909 return SDValue();
910
911 SDValue Shl = And1.getOperand(0);
912
913 if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1))))
914 return SDValue();
915
916 unsigned Shamt = CN->getZExtValue();
917
918 // Return if the shift amount and the first bit position of mask are not the
919 // same.
920 EVT ValTy = N->getValueType(0);
921 if ((Shamt != SMPos0) || (SMPos0 + SMSize0 > ValTy.getSizeInBits()))
922 return SDValue();
923
924 SDLoc DL(N);
925 return DAG.getNode(MipsISD::Ins, DL, ValTy, Shl.getOperand(0),
926 DAG.getConstant(SMPos0, DL, MVT::i32),
927 DAG.getConstant(SMSize0, DL, MVT::i32),
928 And0.getOperand(0));
929 } else {
930 // Pattern match DINS.
931 // $dst = or (and $src, mask0), mask1
932 // where mask0 = ((1 << SMSize0) -1) << SMPos0
933 // => dins $dst, $src, pos, size
934 if (~CN->getSExtValue() == ((((int64_t)1 << SMSize0) - 1) << SMPos0) &&
935 ((SMSize0 + SMPos0 <= 64 && Subtarget.hasMips64r2()) ||
936 (SMSize0 + SMPos0 <= 32))) {
937 // Check if AND instruction has constant as argument
938 bool isConstCase = And1.getOpcode() != ISD::AND;
939 if (And1.getOpcode() == ISD::AND) {
940 if (!(CN1 = dyn_cast<ConstantSDNode>(And1->getOperand(1))))
941 return SDValue();
942 } else {
943 if (!(CN1 = dyn_cast<ConstantSDNode>(N->getOperand(1))))
944 return SDValue();
945 }
946 // Don't generate INS if constant OR operand doesn't fit into bits
947 // cleared by constant AND operand.
948 if (CN->getSExtValue() & CN1->getSExtValue())
949 return SDValue();
950
951 SDLoc DL(N);
952 EVT ValTy = N->getOperand(0)->getValueType(0);
953 SDValue Const1;
954 SDValue SrlX;
955 if (!isConstCase) {
956 Const1 = DAG.getConstant(SMPos0, DL, MVT::i32);
957 SrlX = DAG.getNode(ISD::SRL, DL, And1->getValueType(0), And1, Const1);
958 }
959 return DAG.getNode(
960 MipsISD::Ins, DL, N->getValueType(0),
961 isConstCase
962 ? DAG.getConstant(CN1->getSExtValue() >> SMPos0, DL, ValTy)
963 : SrlX,
964 DAG.getConstant(SMPos0, DL, MVT::i32),
965 DAG.getConstant(ValTy.getSizeInBits() / 8 < 8 ? SMSize0 & 31
966 : SMSize0,
967 DL, MVT::i32),
968 And0->getOperand(0));
969
970 }
971 return SDValue();
972 }
973}
974
975static SDValue performMADD_MSUBCombine(SDNode *ROOTNode, SelectionDAG &CurDAG,
976 const MipsSubtarget &Subtarget) {
977 // ROOTNode must have a multiplication as an operand for the match to be
978 // successful.
979 if (ROOTNode->getOperand(0).getOpcode() != ISD::MUL &&
980 ROOTNode->getOperand(1).getOpcode() != ISD::MUL)
981 return SDValue();
982
983 // We don't handle vector types here.
984 if (ROOTNode->getValueType(0).isVector())
985 return SDValue();
986
987 // For MIPS64, madd / msub instructions are inefficent to use with 64 bit
988 // arithmetic. E.g.
989 // (add (mul a b) c) =>
990 // let res = (madd (mthi (drotr c 32))x(mtlo c) a b) in
991 // MIPS64: (or (dsll (mfhi res) 32) (dsrl (dsll (mflo res) 32) 32)
992 // or
993 // MIPS64R2: (dins (mflo res) (mfhi res) 32 32)
994 //
995 // The overhead of setting up the Hi/Lo registers and reassembling the
996 // result makes this a dubious optimzation for MIPS64. The core of the
997 // problem is that Hi/Lo contain the upper and lower 32 bits of the
998 // operand and result.
999 //
1000 // It requires a chain of 4 add/mul for MIPS64R2 to get better code
1001 // density than doing it naively, 5 for MIPS64. Additionally, using
1002 // madd/msub on MIPS64 requires the operands actually be 32 bit sign
1003 // extended operands, not true 64 bit values.
1004 //
1005 // FIXME: For the moment, disable this completely for MIPS64.
1006 if (Subtarget.hasMips64())
1007 return SDValue();
1008
1009 SDValue Mult = ROOTNode->getOperand(0).getOpcode() == ISD::MUL
1010 ? ROOTNode->getOperand(0)
1011 : ROOTNode->getOperand(1);
1012
1013 SDValue AddOperand = ROOTNode->getOperand(0).getOpcode() == ISD::MUL
1014 ? ROOTNode->getOperand(1)
1015 : ROOTNode->getOperand(0);
1016
1017 // Transform this to a MADD only if the user of this node is the add.
1018 // If there are other users of the mul, this function returns here.
1019 if (!Mult.hasOneUse())
1020 return SDValue();
1021
1022 // maddu and madd are unusual instructions in that on MIPS64 bits 63..31
1023 // must be in canonical form, i.e. sign extended. For MIPS32, the operands
1024 // of the multiply must have 32 or more sign bits, otherwise we cannot
1025 // perform this optimization. We have to check this here as we're performing
1026 // this optimization pre-legalization.
1027 SDValue MultLHS = Mult->getOperand(0);
1028 SDValue MultRHS = Mult->getOperand(1);
1029
1030 bool IsSigned = MultLHS->getOpcode() == ISD::SIGN_EXTEND &&
1031 MultRHS->getOpcode() == ISD::SIGN_EXTEND;
1032 bool IsUnsigned = MultLHS->getOpcode() == ISD::ZERO_EXTEND &&
1033 MultRHS->getOpcode() == ISD::ZERO_EXTEND;
1034
1035 if (!IsSigned && !IsUnsigned)
1036 return SDValue();
1037
1038 // Initialize accumulator.
1039 SDLoc DL(ROOTNode);
1040 SDValue TopHalf;
1041 SDValue BottomHalf;
1042 BottomHalf = CurDAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, AddOperand,
1043 CurDAG.getIntPtrConstant(0, DL));
1044
1045 TopHalf = CurDAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, AddOperand,
1046 CurDAG.getIntPtrConstant(1, DL));
1047 SDValue ACCIn = CurDAG.getNode(MipsISD::MTLOHI, DL, MVT::Untyped,
1048 BottomHalf,
1049 TopHalf);
1050
1051 // Create MipsMAdd(u) / MipsMSub(u) node.
1052 bool IsAdd = ROOTNode->getOpcode() == ISD::ADD;
1053 unsigned Opcode = IsAdd ? (IsUnsigned ? MipsISD::MAddu : MipsISD::MAdd)
1054 : (IsUnsigned ? MipsISD::MSubu : MipsISD::MSub);
1055 SDValue MAddOps[3] = {
1056 CurDAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Mult->getOperand(0)),
1057 CurDAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Mult->getOperand(1)), ACCIn};
1058 EVT VTs[2] = {MVT::i32, MVT::i32};
1059 SDValue MAdd = CurDAG.getNode(Opcode, DL, VTs, MAddOps);
1060
1061 SDValue ResLo = CurDAG.getNode(MipsISD::MFLO, DL, MVT::i32, MAdd);
1062 SDValue ResHi = CurDAG.getNode(MipsISD::MFHI, DL, MVT::i32, MAdd);
1063 SDValue Combined =
1064 CurDAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, ResLo, ResHi);
1065 return Combined;
1066}
1067
1068static SDValue performSUBCombine(SDNode *N, SelectionDAG &DAG,
1069 TargetLowering::DAGCombinerInfo &DCI,
1070 const MipsSubtarget &Subtarget) {
1071 // (sub v0 (mul v1, v2)) => (msub v1, v2, v0)
1072 if (DCI.isBeforeLegalizeOps()) {
1073 if (Subtarget.hasMips32() && !Subtarget.hasMips32r6() &&
1074 !Subtarget.inMips16Mode() && N->getValueType(0) == MVT::i64)
1075 return performMADD_MSUBCombine(N, DAG, Subtarget);
1076
1077 return SDValue();
1078 }
1079
1080 return SDValue();
1081}
1082
1083static SDValue performADDCombine(SDNode *N, SelectionDAG &DAG,
1084 TargetLowering::DAGCombinerInfo &DCI,
1085 const MipsSubtarget &Subtarget) {
1086 // (add v0 (mul v1, v2)) => (madd v1, v2, v0)
1087 if (DCI.isBeforeLegalizeOps()) {
1088 if (Subtarget.hasMips32() && !Subtarget.hasMips32r6() &&
1089 !Subtarget.inMips16Mode() && N->getValueType(0) == MVT::i64)
1090 return performMADD_MSUBCombine(N, DAG, Subtarget);
1091
1092 return SDValue();
1093 }
1094
1095 // (add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt))
1096 SDValue Add = N->getOperand(1);
1097
1098 if (Add.getOpcode() != ISD::ADD)
1099 return SDValue();
1100
1101 SDValue Lo = Add.getOperand(1);
1102
1103 if ((Lo.getOpcode() != MipsISD::Lo) ||
1104 (Lo.getOperand(0).getOpcode() != ISD::TargetJumpTable))
1105 return SDValue();
1106
1107 EVT ValTy = N->getValueType(0);
1108 SDLoc DL(N);
1109
1110 SDValue Add1 = DAG.getNode(ISD::ADD, DL, ValTy, N->getOperand(0),
1111 Add.getOperand(0));
1112 return DAG.getNode(ISD::ADD, DL, ValTy, Add1, Lo);
1113}
1114
1115static SDValue performSHLCombine(SDNode *N, SelectionDAG &DAG,
1116 TargetLowering::DAGCombinerInfo &DCI,
1117 const MipsSubtarget &Subtarget) {
1118 // Pattern match CINS.
1119 // $dst = shl (and $src , imm), pos
1120 // => cins $dst, $src, pos, size
1121
1122 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasCnMips())
1123 return SDValue();
1124
1125 SDValue FirstOperand = N->getOperand(0);
1126 unsigned FirstOperandOpc = FirstOperand.getOpcode();
1127 SDValue SecondOperand = N->getOperand(1);
1128 EVT ValTy = N->getValueType(0);
1129 SDLoc DL(N);
1130
1131 uint64_t Pos = 0, SMPos, SMSize;
1132 ConstantSDNode *CN;
1133 SDValue NewOperand;
1134
1135 // The second operand of the shift must be an immediate.
1136 if (!(CN = dyn_cast<ConstantSDNode>(SecondOperand)))
1137 return SDValue();
1138
1139 Pos = CN->getZExtValue();
1140
1141 if (Pos >= ValTy.getSizeInBits())
1142 return SDValue();
1143
1144 if (FirstOperandOpc != ISD::AND)
1145 return SDValue();
1146
1147 // AND's second operand must be a shifted mask.
1148 if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.getOperand(1))) ||
1149 !isShiftedMask(CN->getZExtValue(), SMPos, SMSize))
1150 return SDValue();
1151
1152 // Return if the shifted mask does not start at bit 0 or the sum of its size
1153 // and Pos exceeds the word's size.
1154 if (SMPos != 0 || SMSize > 32 || Pos + SMSize > ValTy.getSizeInBits())
1155 return SDValue();
1156
1157 NewOperand = FirstOperand.getOperand(0);
1158 // SMSize is 'location' (position) in this case, not size.
1159 SMSize--;
1160
1161 return DAG.getNode(MipsISD::CIns, DL, ValTy, NewOperand,
1162 DAG.getConstant(Pos, DL, MVT::i32),
1163 DAG.getConstant(SMSize, DL, MVT::i32));
1164}
1165
1166SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI)
1167 const {
1168 SelectionDAG &DAG = DCI.DAG;
1169 unsigned Opc = N->getOpcode();
1170
1171 switch (Opc) {
1172 default: break;
1173 case ISD::SDIVREM:
1174 case ISD::UDIVREM:
1175 return performDivRemCombine(N, DAG, DCI, Subtarget);
1176 case ISD::SELECT:
1177 return performSELECTCombine(N, DAG, DCI, Subtarget);
1178 case MipsISD::CMovFP_F:
1179 case MipsISD::CMovFP_T:
1180 return performCMovFPCombine(N, DAG, DCI, Subtarget);
1181 case ISD::AND:
1182 return performANDCombine(N, DAG, DCI, Subtarget);
1183 case ISD::OR:
1184 return performORCombine(N, DAG, DCI, Subtarget);
1185 case ISD::ADD:
1186 return performADDCombine(N, DAG, DCI, Subtarget);
1187 case ISD::SHL:
1188 return performSHLCombine(N, DAG, DCI, Subtarget);
1189 case ISD::SUB:
1190 return performSUBCombine(N, DAG, DCI, Subtarget);
1191 }
1192
1193 return SDValue();
1194}
1195
1196bool MipsTargetLowering::isCheapToSpeculateCttz() const {
1197 return Subtarget.hasMips32();
1198}
1199
1200bool MipsTargetLowering::isCheapToSpeculateCtlz() const {
1201 return Subtarget.hasMips32();
1202}
1203
1204void
1205MipsTargetLowering::LowerOperationWrapper(SDNode *N,
1206 SmallVectorImpl<SDValue> &Results,
1207 SelectionDAG &DAG) const {
1208 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
1209
1210 for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I)
1211 Results.push_back(Res.getValue(I));
1212}
1213
1214void
1215MipsTargetLowering::ReplaceNodeResults(SDNode *N,
1216 SmallVectorImpl<SDValue> &Results,
1217 SelectionDAG &DAG) const {
1218 return LowerOperationWrapper(N, Results, DAG);
1219}
1220
1221SDValue MipsTargetLowering::
1222LowerOperation(SDValue Op, SelectionDAG &DAG) const
1223{
1224 switch (Op.getOpcode())
1225 {
1226 case ISD::BRCOND: return lowerBRCOND(Op, DAG);
1227 case ISD::ConstantPool: return lowerConstantPool(Op, DAG);
1228 case ISD::GlobalAddress: return lowerGlobalAddress(Op, DAG);
1229 case ISD::BlockAddress: return lowerBlockAddress(Op, DAG);
1230 case ISD::GlobalTLSAddress: return lowerGlobalTLSAddress(Op, DAG);
1231 case ISD::JumpTable: return lowerJumpTable(Op, DAG);
1232 case ISD::SELECT: return lowerSELECT(Op, DAG);
1233 case ISD::SETCC: return lowerSETCC(Op, DAG);
1234 case ISD::VASTART: return lowerVASTART(Op, DAG);
1235 case ISD::VAARG: return lowerVAARG(Op, DAG);
1236 case ISD::FCOPYSIGN: return lowerFCOPYSIGN(Op, DAG);
1237 case ISD::FRAMEADDR: return lowerFRAMEADDR(Op, DAG);
1238 case ISD::RETURNADDR: return lowerRETURNADDR(Op, DAG);
1239 case ISD::EH_RETURN: return lowerEH_RETURN(Op, DAG);
1240 case ISD::ATOMIC_FENCE: return lowerATOMIC_FENCE(Op, DAG);
1241 case ISD::SHL_PARTS: return lowerShiftLeftParts(Op, DAG);
1242 case ISD::SRA_PARTS: return lowerShiftRightParts(Op, DAG, true);
1243 case ISD::SRL_PARTS: return lowerShiftRightParts(Op, DAG, false);
1244 case ISD::LOAD: return lowerLOAD(Op, DAG);
1245 case ISD::STORE: return lowerSTORE(Op, DAG);
1246 case ISD::EH_DWARF_CFA: return lowerEH_DWARF_CFA(Op, DAG);
1247 case ISD::FP_TO_SINT: return lowerFP_TO_SINT(Op, DAG);
1248 }
1249 return SDValue();
1250}
1251
1252//===----------------------------------------------------------------------===//
1253// Lower helper functions
1254//===----------------------------------------------------------------------===//
1255
1256// addLiveIn - This helper function adds the specified physical register to the
1257// MachineFunction as a live in value. It also creates a corresponding
1258// virtual register for it.
1259static unsigned
1260addLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC)
1261{
1262 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
1263 MF.getRegInfo().addLiveIn(PReg, VReg);
1264 return VReg;
1265}
1266
1267static MachineBasicBlock *insertDivByZeroTrap(MachineInstr &MI,
1268 MachineBasicBlock &MBB,
1269 const TargetInstrInfo &TII,
1270 bool Is64Bit, bool IsMicroMips) {
1271 if (NoZeroDivCheck)
1272 return &MBB;
1273
1274 // Insert instruction "teq $divisor_reg, $zero, 7".
1275 MachineBasicBlock::iterator I(MI);
1276 MachineInstrBuilder MIB;
1277 MachineOperand &Divisor = MI.getOperand(2);
1278 MIB = BuildMI(MBB, std::next(I), MI.getDebugLoc(),
1279 TII.get(IsMicroMips ? Mips::TEQ_MM : Mips::TEQ))
1280 .addReg(Divisor.getReg(), getKillRegState(Divisor.isKill()))
1281 .addReg(Mips::ZERO)
1282 .addImm(7);
1283
1284 // Use the 32-bit sub-register if this is a 64-bit division.
1285 if (Is64Bit)
1286 MIB->getOperand(0).setSubReg(Mips::sub_32);
1287
1288 // Clear Divisor's kill flag.
1289 Divisor.setIsKill(false);
1290
1291 // We would normally delete the original instruction here but in this case
1292 // we only needed to inject an additional instruction rather than replace it.
1293
1294 return &MBB;
1295}
1296
1297MachineBasicBlock *
1298MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
1299 MachineBasicBlock *BB) const {
1300 switch (MI.getOpcode()) {
1301 default:
1302 llvm_unreachable("Unexpected instr type to insert")::llvm::llvm_unreachable_internal("Unexpected instr type to insert"
, "/build/llvm-toolchain-snapshot-6.0~svn316068/lib/Target/Mips/MipsISelLowering.cpp"
, 1302)
;
1303 case Mips::ATOMIC_LOAD_ADD_I8:
1304 return emitAtomicBinaryPartword(MI, BB, 1, Mips::ADDu);
1305 case Mips::ATOMIC_LOAD_ADD_I16:
1306 return emitAtomicBinaryPartword(MI, BB, 2, Mips::ADDu);
1307 case Mips::ATOMIC_LOAD_ADD_I32:
1308 return emitAtomicBinary(MI, BB, 4, Mips::ADDu);
1309 case Mips::ATOMIC_LOAD_ADD_I64:
1310 return emitAtomicBinary(MI, BB, 8, Mips::DADDu);
1311
1312 case Mips::ATOMIC_LOAD_AND_I8:
1313 return emitAtomicBinaryPartword(MI, BB, 1, Mips::AND);
1314 case Mips::ATOMIC_LOAD_AND_I16:
1315 return emitAtomicBinaryPartword(MI, BB, 2, Mips::AND);
1316 case Mips::ATOMIC_LOAD_AND_I32:
1317 return emitAtomicBinary(MI, BB, 4, Mips::AND);
1318 case Mips::ATOMIC_LOAD_AND_I64:
1319 return emitAtomicBinary(MI, BB, 8, Mips::AND64);
1320
1321 case Mips::ATOMIC_LOAD_OR_I8:
1322 return emitAtomicBinaryPartword(MI, BB, 1, Mips::OR);
1323 case Mips::ATOMIC_LOAD_OR_I16:
1324 return emitAtomicBinaryPartword(MI, BB, 2, Mips::OR);
1325 case Mips::ATOMIC_LOAD_OR_I32:
1326 return emitAtomicBinary(MI, BB, 4, Mips::OR);
1327 case Mips::ATOMIC_LOAD_OR_I64:
1328 return emitAtomicBinary(MI, BB, 8, Mips::OR64);
1329
1330 case Mips::ATOMIC_LOAD_XOR_I8:
1331 return emitAtomicBinaryPartword(MI, BB, 1, Mips::XOR);
1332 case Mips::ATOMIC_LOAD_XOR_I16:
1333 return emitAtomicBinaryPartword(MI, BB, 2, Mips::XOR);
1334 case Mips::ATOMIC_LOAD_XOR_I32:
1335 return emitAtomicBinary(MI, BB, 4, Mips::XOR);
1336 case Mips::ATOMIC_LOAD_XOR_I64:
1337 return emitAtomicBinary(MI, BB, 8, Mips::XOR64);
1338
1339 case Mips::ATOMIC_LOAD_NAND_I8:
1340 return emitAtomicBinaryPartword(MI, BB, 1, 0, true);
1341 case Mips::ATOMIC_LOAD_NAND_I16:
1342 return emitAtomicBinaryPartword(MI, BB, 2, 0, true);
1343 case Mips::ATOMIC_LOAD_NAND_I32:
1344 return emitAtomicBinary(MI, BB, 4, 0, true);
1345 case Mips::ATOMIC_LOAD_NAND_I64:
1346 return emitAtomicBinary(MI, BB, 8, 0, true);
1347
1348 case Mips::ATOMIC_LOAD_SUB_I8:
1349 return emitAtomicBinaryPartword(MI, BB, 1, Mips::SUBu);
1350 case Mips::ATOMIC_LOAD_SUB_I16:
1351 return emitAtomicBinaryPartword(MI, BB, 2, Mips::SUBu);
1352 case Mips::ATOMIC_LOAD_SUB_I32:
1353 return emitAtomicBinary(MI, BB, 4, Mips::SUBu);
1354 case Mips::ATOMIC_LOAD_SUB_I64:
1355 return emitAtomicBinary(MI, BB, 8, Mips::DSUBu);
1356
1357 case Mips::ATOMIC_SWAP_I8:
1358 return emitAtomicBinaryPartword(MI, BB, 1, 0);
1359 case Mips::ATOMIC_SWAP_I16:
1360 return emitAtomicBinaryPartword(MI, BB, 2, 0);
1361 case Mips::ATOMIC_SWAP_I32:
1362 return emitAtomicBinary(MI, BB, 4, 0);
1363 case Mips::ATOMIC_SWAP_I64:
1364 return emitAtomicBinary(MI, BB, 8, 0);
1365
1366 case Mips::ATOMIC_CMP_SWAP_I8:
1367 return emitAtomicCmpSwapPartword(MI, BB, 1);
1368 case Mips::ATOMIC_CMP_SWAP_I16:
1369 return emitAtomicCmpSwapPartword(MI, BB, 2);
1370 case Mips::ATOMIC_CMP_SWAP_I32:
1371 return emitAtomicCmpSwap(MI, BB, 4);
1372 case Mips::ATOMIC_CMP_SWAP_I64:
1373 return emitAtomicCmpSwap(MI, BB, 8);
1374 case Mips::PseudoSDIV:
1375 case Mips::PseudoUDIV:
1376 case Mips::DIV:
1377 case Mips::DIVU:
1378 case Mips::MOD:
1379 case Mips::MODU:
1380 return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), false,
1381 false);
1382 case Mips::SDIV_MM_Pseudo:
1383 case Mips::UDIV_MM_Pseudo:
1384 case Mips::SDIV_MM:
1385 case Mips::UDIV_MM:
1386 case Mips::DIV_MMR6:
1387 case Mips::DIVU_MMR6:
1388 case Mips::MOD_MMR6:
1389 case Mips::MODU_MMR6:
1390 return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), false, true);
1391 case Mips::PseudoDSDIV:
1392 case Mips::PseudoDUDIV:
1393 case Mips::DDIV:
1394 case Mips::DDIVU:
1395 case Mips::DMOD:
1396 case Mips::DMODU:
1397 return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), true, false);
1398 case Mips::DDIV_MM64R6:
1399 case Mips::DDIVU_MM64R6:
1400 case Mips::DMOD_MM64R6:
1401 case Mips::DMODU_MM64R6:
1402 return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), true, true);
1403
1404 case Mips::PseudoSELECT_I:
1405 case Mips::PseudoSELECT_I64:
1406 case Mips::PseudoSELECT_S:
1407 case Mips::PseudoSELECT_D32:
1408 case Mips::PseudoSELECT_D64:
1409 return emitPseudoSELECT(MI, BB, false, Mips::BNE);
1410 case Mips::PseudoSELECTFP_F_I:
1411 case Mips::PseudoSELECTFP_F_I64:
1412 case Mips::PseudoSELECTFP_F_S:
1413 case Mips::PseudoSELECTFP_F_D32:
1414 case Mips::PseudoSELECTFP_F_D64:
1415 return emitPseudoSELECT(MI, BB, true, Mips::BC1F);
1416 case Mips::PseudoSELECTFP_T_I:
1417 case Mips::PseudoSELECTFP_T_I64:
1418 case Mips::PseudoSELECTFP_T_S:
1419 case Mips::PseudoSELECTFP_T_D32:
1420 case Mips::PseudoSELECTFP_T_D64:
1421 return emitPseudoSELECT(MI, BB, true, Mips::BC1T);
1422 }
1423}
1424
1425// This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and
1426// Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true)
1427MachineBasicBlock *MipsTargetLowering::emitAtomicBinary(MachineInstr &MI,
1428 MachineBasicBlock *BB,
1429 unsigned Size,
1430 unsigned BinOpcode,
1431 bool Nand) const {
1432 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicBinary.")(((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicBinary."
) ? static_cast<void> (0) : __assert_fail ("(Size == 4 || Size == 8) && \"Unsupported size for EmitAtomicBinary.\""
, "/build/llvm-toolchain-snapshot-6.0~svn316068/lib/Target/Mips/MipsISelLowering.cpp"
, 1432, __PRETTY_FUNCTION__))
;
1433
1434 MachineFunction *MF = BB->getParent();
1435 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1436 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8));
1437 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
1438 const bool ArePtrs64bit = ABI.ArePtrs64bit();
1439 DebugLoc DL = MI.getDebugLoc();
1440 unsigned LL, SC, AND, NOR, ZERO, BEQ;
1441
1442 if (Size == 4) {
1443 if (isMicroMips) {
1444 LL = Mips::LL_MM;
1445 SC = Mips::SC_MM;
1446 } else {
1447 LL = Subtarget.hasMips32r6()
1448 ? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6)
1449 : (ArePtrs64bit ? Mips::LL64 : Mips::LL);
1450 SC = Subtarget.hasMips32r6()
1451 ? (ArePtrs64bit ? Mips::SC64_R6 : Mips::SC_R6)
1452 : (ArePtrs64bit ? Mips::SC64 : Mips::SC);
1453 }
1454
1455 AND = Mips::AND;
1456 NOR = Mips::NOR;
1457 ZERO = Mips::ZERO;
1458 BEQ = Mips::BEQ;
1459 } else {
1460 LL = Subtarget.hasMips64r6() ? Mips::LLD_R6 : Mips::LLD;
1461 SC = Subtarget.hasMips64r6() ? Mips::SCD_R6 : Mips::SCD;
1462 AND = Mips::AND64;
1463 NOR = Mips::NOR64;
1464 ZERO = Mips::ZERO_64;
1465 BEQ = Mips::BEQ64;
1466 }
1467
1468 unsigned OldVal = MI.getOperand(0).getReg();
1469 unsigned Ptr = MI.getOperand(1).getReg();
1470 unsigned Incr = MI.getOperand(2).getReg();
1471
1472 unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1473 unsigned AndRes = RegInfo.createVirtualRegister(RC);
1474 unsigned Success = RegInfo.createVirtualRegister(RC);
1475
1476 // insert new blocks after the current block
1477 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1478 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1479 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1480 MachineFunction::iterator It = ++BB->getIterator();
1481 MF->insert(It, loopMBB);
1482 MF->insert(It, exitMBB);
1483
1484 // Transfer the remainder of BB and its successor edges to exitMBB.
1485 exitMBB->splice(exitMBB->begin(), BB,
1486 std::next(MachineBasicBlock::iterator(MI)), BB->end());
1487 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1488
1489 // thisMBB:
1490 // ...
1491 // fallthrough --> loopMBB
1492 BB->addSuccessor(loopMBB);
1493 loopMBB->addSuccessor(loopMBB);
1494 loopMBB->addSuccessor(exitMBB);
1495
1496 // loopMBB:
1497 // ll oldval, 0(ptr)
1498 // <binop> storeval, oldval, incr
1499 // sc success, storeval, 0(ptr)
1500 // beq success, $0, loopMBB
1501 BB = loopMBB;
1502 BuildMI(BB, DL, TII->get(LL), OldVal).addReg(Ptr).addImm(0);
1503 if (Nand) {
1504 // and andres, oldval, incr
1505 // nor storeval, $0, andres
1506 BuildMI(BB, DL, TII->get(AND), AndRes).addReg(OldVal).addReg(Incr);
1507 BuildMI(BB, DL, TII->get(NOR), StoreVal).addReg(ZERO).addReg(AndRes);
1508 } else if (BinOpcode) {
1509 // <binop> storeval, oldval, incr
1510 BuildMI(BB, DL, TII->get(BinOpcode), StoreVal).addReg(OldVal).addReg(Incr);
1511 } else {
1512 StoreVal = Incr;
1513 }
1514 BuildMI(BB, DL, TII->get(SC), Success).addReg(StoreVal).addReg(Ptr).addImm(0);
1515 BuildMI(BB, DL, TII->get(BEQ)).addReg(Success).addReg(ZERO).addMBB(loopMBB);
1516
1517 MI.eraseFromParent(); // The instruction is gone now.
1518
1519 return exitMBB;
1520}
1521
1522MachineBasicBlock *MipsTargetLowering::emitSignExtendToI32InReg(
1523 MachineInstr &MI, MachineBasicBlock *BB, unsigned Size, unsigned DstReg,
1524 unsigned SrcReg) const {
1525 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
1526 const DebugLoc &DL = MI.getDebugLoc();
1527
1528 if (Subtarget.hasMips32r2() && Size == 1) {
1529 BuildMI(BB, DL, TII->get(Mips::SEB), DstReg).addReg(SrcReg);
1530 return BB;
1531 }
1532
1533 if (Subtarget.hasMips32r2() && Size == 2) {
1534 BuildMI(BB, DL, TII->get(Mips::SEH), DstReg).addReg(SrcReg);
1535 return BB;
1536 }
1537
1538 MachineFunction *MF = BB->getParent();
1539 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1540 const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1541 unsigned ScrReg = RegInfo.createVirtualRegister(RC);
1542
1543 assert(Size < 32)((Size < 32) ? static_cast<void> (0) : __assert_fail
("Size < 32", "/build/llvm-toolchain-snapshot-6.0~svn316068/lib/Target/Mips/MipsISelLowering.cpp"
, 1543, __PRETTY_FUNCTION__))
;
1544 int64_t ShiftImm = 32 - (Size * 8);
1545
1546 BuildMI(BB, DL, TII->get(Mips::SLL), ScrReg).addReg(SrcReg).addImm(ShiftImm);
1547 BuildMI(BB, DL, TII->get(Mips::SRA), DstReg).addReg(ScrReg).addImm(ShiftImm);
1548
1549 return BB;
1550}
1551
1552MachineBasicBlock *MipsTargetLowering::emitAtomicBinaryPartword(
1553 MachineInstr &MI, MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode,
1554 bool Nand) const {
1555 assert((Size == 1 || Size == 2) &&(((Size == 1 || Size == 2) && "Unsupported size for EmitAtomicBinaryPartial."
) ? static_cast<void> (0) : __assert_fail ("(Size == 1 || Size == 2) && \"Unsupported size for EmitAtomicBinaryPartial.\""
, "/build/llvm-toolchain-snapshot-6.0~svn316068/lib/Target/Mips/MipsISelLowering.cpp"
, 1556, __PRETTY_FUNCTION__))
1556 "Unsupported size for EmitAtomicBinaryPartial.")(((Size == 1 || Size == 2) && "Unsupported size for EmitAtomicBinaryPartial."
) ? static_cast<void> (0) : __assert_fail ("(Size == 1 || Size == 2) && \"Unsupported size for EmitAtomicBinaryPartial.\""
, "/build/llvm-toolchain-snapshot-6.0~svn316068/lib/Target/Mips/MipsISelLowering.cpp"
, 1556, __PRETTY_FUNCTION__))
;
1557
1558 MachineFunction *MF = BB->getParent();
1559 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1560 const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1561 const bool ArePtrs64bit = ABI.ArePtrs64bit();
1562 const TargetRegisterClass *RCp =
1563 getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32);
1564 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
1565 DebugLoc DL = MI.getDebugLoc();
1566
1567 unsigned Dest = MI.getOperand(0).getReg();
1568 unsigned Ptr = MI.getOperand(1).getReg();
1569 unsigned Incr = MI.getOperand(2).getReg();
1570
1571 unsigned AlignedAddr = RegInfo.createVirtualRegister(RCp);
1572 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
1573 unsigned Mask = RegInfo.createVirtualRegister(RC);
1574 unsigned Mask2 = RegInfo.createVirtualRegister(RC);
1575 unsigned NewVal = RegInfo.createVirtualRegister(RC);
1576 unsigned OldVal = RegInfo.createVirtualRegister(RC);
1577 unsigned Incr2 = RegInfo.createVirtualRegister(RC);
1578 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RCp);
1579 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC);
1580 unsigned MaskUpper = RegInfo.createVirtualRegister(RC);
1581 unsigned AndRes = RegInfo.createVirtualRegister(RC);
1582 unsigned BinOpRes = RegInfo.createVirtualRegister(RC);
1583 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC);
1584 unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1585 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC);
1586 unsigned SrlRes = RegInfo.createVirtualRegister(RC);
1587 unsigned Success = RegInfo.createVirtualRegister(RC);
1588
1589 unsigned LL, SC;
1590 if (isMicroMips) {
1591 LL = Mips::LL_MM;
1592 SC = Mips::SC_MM;
1593 } else {
1594 LL = Subtarget.hasMips32r6() ? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6)
1595 : (ArePtrs64bit ? Mips::LL64 : Mips::LL);
1596 SC = Subtarget.hasMips32r6() ? (ArePtrs64bit ? Mips::SC64_R6 : Mips::SC_R6)
1597 : (ArePtrs64bit ? Mips::SC64 : Mips::SC);
1598 }
1599
1600 // insert new blocks after the current block
1601 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1602 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1603 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1604 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1605 MachineFunction::iterator It = ++BB->getIterator();
1606 MF->insert(It, loopMBB);
1607 MF->insert(It, sinkMBB);
1608 MF->insert(It, exitMBB);
1609
1610 // Transfer the remainder of BB and its successor edges to exitMBB.
1611 exitMBB->splice(exitMBB->begin(), BB,
1612 std::next(MachineBasicBlock::iterator(MI)), BB->end());
1613 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1614
1615 BB->addSuccessor(loopMBB);
1616 loopMBB->addSuccessor(loopMBB);
1617 loopMBB->addSuccessor(sinkMBB);
1618 sinkMBB->addSuccessor(exitMBB);
1619
1620 // thisMBB:
1621 // addiu masklsb2,$0,-4 # 0xfffffffc
1622 // and alignedaddr,ptr,masklsb2
1623 // andi ptrlsb2,ptr,3
1624 // sll shiftamt,ptrlsb2,3
1625 // ori maskupper,$0,255 # 0xff
1626 // sll mask,maskupper,shiftamt
1627 // nor mask2,$0,mask
1628 // sll incr2,incr,shiftamt
1629
1630 int64_t MaskImm = (Size == 1) ? 255 : 65535;
1631 BuildMI(BB, DL, TII->get(ABI.GetPtrAddiuOp()), MaskLSB2)
1632 .addReg(ABI.GetNullPtr()).addImm(-4);
1633 BuildMI(BB, DL, TII->get(ABI.GetPtrAndOp()), AlignedAddr)
1634 .addReg(Ptr).addReg(MaskLSB2);
1635 BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2)
1636 .addReg(Ptr, 0, ArePtrs64bit ? Mips::sub_32 : 0).addImm(3);
1637 if (Subtarget.isLittle()) {
1638 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1639 } else {
1640 unsigned Off = RegInfo.createVirtualRegister(RC);
1641 BuildMI(BB, DL, TII->get(Mips::XORi), Off)
1642 .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2);
1643 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
1644 }
1645 BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper)
1646 .addReg(Mips::ZERO).addImm(MaskImm);
1647 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask)
1648 .addReg(MaskUpper).addReg(ShiftAmt);
1649 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
1650 BuildMI(BB, DL, TII->get(Mips::SLLV), Incr2).addReg(Incr).addReg(ShiftAmt);
1651
1652 // atomic.load.binop
1653 // loopMBB:
1654 // ll oldval,0(alignedaddr)
1655 // binop binopres,oldval,incr2
1656 // and newval,binopres,mask
1657 // and maskedoldval0,oldval,mask2
1658 // or storeval,maskedoldval0,newval
1659 // sc success,storeval,0(alignedaddr)
1660 // beq success,$0,loopMBB
1661
1662 // atomic.swap
1663 // loopMBB:
1664 // ll oldval,0(alignedaddr)
1665 // and newval,incr2,mask
1666 // and maskedoldval0,oldval,mask2
1667 // or storeval,maskedoldval0,newval
1668 // sc success,storeval,0(alignedaddr)
1669 // beq success,$0,loopMBB
1670
1671 BB = loopMBB;
1672 BuildMI(BB, DL, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0);
1673 if (Nand) {
1674 // and andres, oldval, incr2
1675 // nor binopres, $0, andres
1676 // and newval, binopres, mask
1677 BuildMI(BB, DL, TII->get(Mips::AND), AndRes).addReg(OldVal).addReg(Incr2);
1678 BuildMI(BB, DL, TII->get(Mips::NOR), BinOpRes)
1679 .addReg(Mips::ZERO).addReg(AndRes);
1680 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask);
1681 } else if (BinOpcode) {
1682 // <binop> binopres, oldval, incr2
1683 // and newval, binopres, mask
1684 BuildMI(BB, DL, TII->get(BinOpcode), BinOpRes).addReg(OldVal).addReg(Incr2);
1685 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask);
1686 } else { // atomic.swap
1687 // and newval, incr2, mask
1688 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(Incr2).addReg(Mask);
1689 }
1690
1691 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal0)
1692 .addReg(OldVal).addReg(Mask2);
1693 BuildMI(BB, DL, TII->get(Mips::OR), StoreVal)
1694 .addReg(MaskedOldVal0).addReg(NewVal);
1695 BuildMI(BB, DL, TII->get(SC), Success)
1696 .addReg(StoreVal).addReg(AlignedAddr).addImm(0);
1697 BuildMI(BB, DL, TII->get(Mips::BEQ))
1698 .addReg(Success).addReg(Mips::ZERO).addMBB(loopMBB);
1699
1700 // sinkMBB:
1701 // and maskedoldval1,oldval,mask
1702 // srl srlres,maskedoldval1,shiftamt
1703 // sign_extend dest,srlres
1704 BB = sinkMBB;
1705
1706 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal1)
1707 .addReg(OldVal).addReg(Mask);
1708 BuildMI(BB, DL, TII->get(Mips::SRLV), SrlRes)
1709 .addReg(MaskedOldVal1).addReg(ShiftAmt);
1710 BB = emitSignExtendToI32InReg(MI, BB, Size, Dest, SrlRes);
1711
1712 MI.eraseFromParent(); // The instruction is gone now.
1713
1714 return exitMBB;
1715}
1716
1717MachineBasicBlock *MipsTargetLowering::emitAtomicCmpSwap(MachineInstr &MI,
1718 MachineBasicBlock *BB,
1719 unsigned Size) const {
1720 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicCmpSwap.")(((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicCmpSwap."
) ? static_cast<void> (0) : __assert_fail ("(Size == 4 || Size == 8) && \"Unsupported size for EmitAtomicCmpSwap.\""
, "/build/llvm-toolchain-snapshot-6.0~svn316068/lib/Target/Mips/MipsISelLowering.cpp"
, 1720, __PRETTY_FUNCTION__))
;
1721
1722 MachineFunction *MF = BB->getParent();
1723 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1724 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8));
1725 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
1726 const bool ArePtrs64bit = ABI.ArePtrs64bit();
1727 DebugLoc DL = MI.getDebugLoc();
1728 unsigned LL, SC, ZERO, BNE, BEQ;
1729
1730 if (Size == 4) {
1731 if (isMicroMips) {
1732 LL = Mips::LL_MM;
1733 SC = Mips::SC_MM;
1734 } else {
1735 LL = Subtarget.hasMips32r6()
1736 ? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6)
1737 : (ArePtrs64bit ? Mips::LL64 : Mips::LL);
1738 SC = Subtarget.hasMips32r6()
1739 ? (ArePtrs64bit ? Mips::SC64_R6 : Mips::SC_R6)
1740 : (ArePtrs64bit ? Mips::SC64 : Mips::SC);
1741 }
1742
1743 ZERO = Mips::ZERO;
1744 BNE = Mips::BNE;
1745 BEQ = Mips::BEQ;
1746 } else {
1747 LL = Subtarget.hasMips64r6() ? Mips::LLD_R6 : Mips::LLD;
1748 SC = Subtarget.hasMips64r6() ? Mips::SCD_R6 : Mips::SCD;
1749 ZERO = Mips::ZERO_64;
1750 BNE = Mips::BNE64;
1751 BEQ = Mips::BEQ64;
1752 }
1753
1754 unsigned Dest = MI.getOperand(0).getReg();
1755 unsigned Ptr = MI.getOperand(1).getReg();
1756 unsigned OldVal = MI.getOperand(2).getReg();
1757 unsigned NewVal = MI.getOperand(3).getReg();
1758
1759 unsigned Success = RegInfo.createVirtualRegister(RC);
1760
1761 // insert new blocks after the current block
1762 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1763 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1764 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1765 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1766 MachineFunction::iterator It = ++BB->getIterator();
1767 MF->insert(It, loop1MBB);
1768 MF->insert(It, loop2MBB);
1769 MF->insert(It, exitMBB);
1770
1771 // Transfer the remainder of BB and its successor edges to exitMBB.
1772 exitMBB->splice(exitMBB->begin(), BB,
1773 std::next(MachineBasicBlock::iterator(MI)), BB->end());
1774 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1775
1776 // thisMBB:
1777 // ...
1778 // fallthrough --> loop1MBB
1779 BB->addSuccessor(loop1MBB);
1780 loop1MBB->addSuccessor(exitMBB);
1781 loop1MBB->addSuccessor(loop2MBB);
1782 loop2MBB->addSuccessor(loop1MBB);
1783 loop2MBB->addSuccessor(exitMBB);
1784
1785 // loop1MBB:
1786 // ll dest, 0(ptr)
1787 // bne dest, oldval, exitMBB
1788 BB = loop1MBB;
1789 BuildMI(BB, DL, TII->get(LL), Dest).addReg(Ptr).addImm(0);
1790 BuildMI(BB, DL, TII->get(BNE))
1791 .addReg(Dest).addReg(OldVal).addMBB(exitMBB);
1792
1793 // loop2MBB:
1794 // sc success, newval, 0(ptr)
1795 // beq success, $0, loop1MBB
1796 BB = loop2MBB;
1797 BuildMI(BB, DL, TII->get(SC), Success)
1798 .addReg(NewVal).addReg(Ptr).addImm(0);
1799 BuildMI(BB, DL, TII->get(BEQ))
1800 .addReg(Success).addReg(ZERO).addMBB(loop1MBB);
1801
1802 MI.eraseFromParent(); // The instruction is gone now.
1803
1804 return exitMBB;
1805}
1806
1807MachineBasicBlock *MipsTargetLowering::emitAtomicCmpSwapPartword(
1808 MachineInstr &MI, MachineBasicBlock *BB, unsigned Size) const {
1809 assert((Size == 1 || Size == 2) &&(((Size == 1 || Size == 2) && "Unsupported size for EmitAtomicCmpSwapPartial."
) ? static_cast<void> (0) : __assert_fail ("(Size == 1 || Size == 2) && \"Unsupported size for EmitAtomicCmpSwapPartial.\""
, "/build/llvm-toolchain-snapshot-6.0~svn316068/lib/Target/Mips/MipsISelLowering.cpp"
, 1810, __PRETTY_FUNCTION__))
1810 "Unsupported size for EmitAtomicCmpSwapPartial.")(((Size == 1 || Size == 2) && "Unsupported size for EmitAtomicCmpSwapPartial."
) ? static_cast<void> (0) : __assert_fail ("(Size == 1 || Size == 2) && \"Unsupported size for EmitAtomicCmpSwapPartial.\""
, "/build/llvm-toolchain-snapshot-6.0~svn316068/lib/Target/Mips/MipsISelLowering.cpp"
, 1810, __PRETTY_FUNCTION__))
;
1811
1812 MachineFunction *MF = BB->getParent();
1813 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1814 const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1815 const bool ArePtrs64bit = ABI.ArePtrs64bit();
1816 const TargetRegisterClass *RCp =
1817 getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32);
1818 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
1819 DebugLoc DL = MI.getDebugLoc();
1820
1821 unsigned Dest = MI.getOperand(0).getReg();
1822 unsigned Ptr = MI.getOperand(1).getReg();
1823 unsigned CmpVal = MI.getOperand(2).getReg();
1824 unsigned NewVal = MI.getOperand(3).getReg();
1825
1826 unsigned AlignedAddr = RegInfo.createVirtualRegister(RCp);
1827 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
1828 unsigned Mask = RegInfo.createVirtualRegister(RC);
1829 unsigned Mask2 = RegInfo.createVirtualRegister(RC);
1830 unsigned ShiftedCmpVal = RegInfo.createVirtualRegister(RC);
1831 unsigned OldVal = RegInfo.createVirtualRegister(RC);
1832 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC);
1833 unsigned ShiftedNewVal = RegInfo.createVirtualRegister(RC);
1834 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RCp);
1835 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC);
1836 unsigned MaskUpper = RegInfo.createVirtualRegister(RC);
1837 unsigned MaskedCmpVal = RegInfo.createVirtualRegister(RC);
1838 unsigned MaskedNewVal = RegInfo.createVirtualRegister(RC);
1839 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC);
1840 unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1841 unsigned SrlRes = RegInfo.createVirtualRegister(RC);
1842 unsigned Success = RegInfo.createVirtualRegister(RC);
1843 unsigned LL, SC;
1844
1845 if (isMicroMips) {
1846 LL = Mips::LL_MM;
1847 SC = Mips::SC_MM;
1848 } else {
1849 LL = Subtarget.hasMips32r6() ? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6)
1850 : (ArePtrs64bit ? Mips::LL64 : Mips::LL);
1851 SC = Subtarget.hasMips32r6() ? (ArePtrs64bit ? Mips::SC64_R6 : Mips::SC_R6)
1852 : (ArePtrs64bit ? Mips::SC64 : Mips::SC);
1853 }
1854
1855 // insert new blocks after the current block
1856 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1857 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1858 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1859 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1860 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1861 MachineFunction::iterator It = ++BB->getIterator();
1862 MF->insert(It, loop1MBB);
1863 MF->insert(It, loop2MBB);
1864 MF->insert(It, sinkMBB);
1865 MF->insert(It, exitMBB);
1866
1867 // Transfer the remainder of BB and its successor edges to exitMBB.
1868 exitMBB->splice(exitMBB->begin(), BB,
1869 std::next(MachineBasicBlock::iterator(MI)), BB->end());
1870 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1871
1872 BB->addSuccessor(loop1MBB);
1873 loop1MBB->addSuccessor(sinkMBB);
1874 loop1MBB->addSuccessor(loop2MBB);
1875 loop2MBB->addSuccessor(loop1MBB);
1876 loop2MBB->addSuccessor(sinkMBB);
1877 sinkMBB->addSuccessor(exitMBB);
1878
1879 // FIXME: computation of newval2 can be moved to loop2MBB.
1880 // thisMBB:
1881 // addiu masklsb2,$0,-4 # 0xfffffffc
1882 // and alignedaddr,ptr,masklsb2
1883 // andi ptrlsb2,ptr,3
1884 // xori ptrlsb2,ptrlsb2,3 # Only for BE
1885 // sll shiftamt,ptrlsb2,3
1886 // ori maskupper,$0,255 # 0xff
1887 // sll mask,maskupper,shiftamt
1888 // nor mask2,$0,mask
1889 // andi maskedcmpval,cmpval,255
1890 // sll shiftedcmpval,maskedcmpval,shiftamt
1891 // andi maskednewval,newval,255
1892 // sll shiftednewval,maskednewval,shiftamt
1893 int64_t MaskImm = (Size == 1) ? 255 : 65535;
1894 BuildMI(BB, DL, TII->get(ArePtrs64bit ? Mips::DADDiu : Mips::ADDiu), MaskLSB2)
1895 .addReg(ABI.GetNullPtr()).addImm(-4);
1896 BuildMI(BB, DL, TII->get(ArePtrs64bit ? Mips::AND64 : Mips::AND), AlignedAddr)
1897 .addReg(Ptr).addReg(MaskLSB2);
1898 BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2)
1899 .addReg(Ptr, 0, ArePtrs64bit ? Mips::sub_32 : 0).addImm(3);
1900 if (Subtarget.isLittle()) {
1901 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1902 } else {
1903 unsigned Off = RegInfo.createVirtualRegister(RC);
1904 BuildMI(BB, DL, TII->get(Mips::XORi), Off)
1905 .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2);
1906 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
1907 }
1908 BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper)
1909 .addReg(Mips::ZERO).addImm(MaskImm);
1910 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask)
1911 .addReg(MaskUpper).addReg(ShiftAmt);
1912 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
1913 BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedCmpVal)
1914 .addReg(CmpVal).addImm(MaskImm);
1915 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedCmpVal)
1916 .addReg(MaskedCmpVal).addReg(ShiftAmt);
1917 BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedNewVal)
1918 .addReg(NewVal).addImm(MaskImm);
1919 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedNewVal)
1920 .addReg(MaskedNewVal).addReg(ShiftAmt);
1921
1922 // loop1MBB:
1923 // ll oldval,0(alginedaddr)
1924 // and maskedoldval0,oldval,mask
1925 // bne maskedoldval0,shiftedcmpval,sinkMBB
1926 BB = loop1MBB;
1927 BuildMI(BB, DL, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0);
1928 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal0)
1929 .addReg(OldVal).addReg(Mask);
1930 BuildMI(BB, DL, TII->get(Mips::BNE))
1931 .addReg(MaskedOldVal0).addReg(ShiftedCmpVal).addMBB(sinkMBB);
1932
1933 // loop2MBB:
1934 // and maskedoldval1,oldval,mask2
1935 // or storeval,maskedoldval1,shiftednewval
1936 // sc success,storeval,0(alignedaddr)
1937 // beq success,$0,loop1MBB
1938 BB = loop2MBB;
1939 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal1)
1940 .addReg(OldVal).addReg(Mask2);
1941 BuildMI(BB, DL, TII->get(Mips::OR), StoreVal)
1942 .addReg(MaskedOldVal1).addReg(ShiftedNewVal);
1943 BuildMI(BB, DL, TII->get(SC), Success)
1944 .addReg(StoreVal).addReg(AlignedAddr).addImm(0);
1945 BuildMI(BB, DL, TII->get(Mips::BEQ))
1946 .addReg(Success).addReg(Mips::ZERO).addMBB(loop1MBB);
1947
1948 // sinkMBB:
1949 // srl srlres,maskedoldval0,shiftamt
1950 // sign_extend dest,srlres
1951 BB = sinkMBB;
1952
1953 BuildMI(BB, DL, TII->get(Mips::SRLV), SrlRes)
1954 .addReg(MaskedOldVal0).addReg(ShiftAmt);
1955 BB = emitSignExtendToI32InReg(MI, BB, Size, Dest, SrlRes);
Value stored to 'BB' is never read
1956
1957 MI.eraseFromParent(); // The instruction is gone now.
1958
1959 return exitMBB;
1960}
1961
1962SDValue MipsTargetLowering::lowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
1963 // The first operand is the chain, the second is the condition, the third is
1964 // the block to branch to if the condition is true.
1965 SDValue Chain = Op.getOperand(0);
1966 SDValue Dest = Op.getOperand(2);
1967 SDLoc DL(Op);
1968
1969 assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6())((!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6(
)) ? static_cast<void> (0) : __assert_fail ("!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6()"
, "/build/llvm-toolchain-snapshot-6.0~svn316068/lib/Target/Mips/MipsISelLowering.cpp"
, 1969, __PRETTY_FUNCTION__))
;
1970 SDValue CondRes = createFPCmp(DAG, Op.getOperand(1));
1971
1972 // Return if flag is not set by a floating point comparison.
1973 if (CondRes.getOpcode() != MipsISD::FPCmp)
1974 return Op;
1975
1976 SDValue CCNode = CondRes.getOperand(2);
1977 Mips::CondCode CC =
1978 (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue();
1979 unsigned Opc = invertFPCondCodeUser(CC) ? Mips::BRANCH_F : Mips::BRANCH_T;
1980 SDValue BrCode = DAG.getConstant(Opc, DL, MVT::i32);
1981 SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32);
1982 return DAG.getNode(MipsISD::FPBrcond, DL, Op.getValueType(), Chain, BrCode,
1983 FCC0, Dest, CondRes);
1984}
1985
1986SDValue MipsTargetLowering::
1987lowerSELECT(SDValue Op, SelectionDAG &DAG) const
1988{
1989 assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6())((!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6(
)) ? static_cast<void> (0) : __assert_fail ("!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6()"
, "/build/llvm-toolchain-snapshot-6.0~svn316068/lib/Target/Mips/MipsISelLowering.cpp"
, 1989, __PRETTY_FUNCTION__))
;
1990 SDValue Cond = createFPCmp(DAG, Op.getOperand(0));
1991
1992 // Return if flag is not set by a floating point comparison.
1993 if (Cond.getOpcode() != MipsISD::FPCmp)
1994 return Op;
1995
1996 return createCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2),
1997 SDLoc(Op));
1998}
1999
2000SDValue MipsTargetLowering::lowerSETCC(SDValue Op, SelectionDAG &DAG) const {
2001 assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6())((!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6(
)) ? static_cast<void> (0) : __assert_fail ("!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6()"
, "/build/llvm-toolchain-snapshot-6.0~svn316068/lib/Target/Mips/MipsISelLowering.cpp"
, 2001, __PRETTY_FUNCTION__))
;
2002 SDValue Cond = createFPCmp(DAG, Op);
2003
2004 assert(Cond.getOpcode() == MipsISD::FPCmp &&((Cond.getOpcode() == MipsISD::FPCmp && "Floating point operand expected."
) ? static_cast<void> (0) : __assert_fail ("Cond.getOpcode() == MipsISD::FPCmp && \"Floating point operand expected.\""
, "/build/llvm-toolchain-snapshot-6.0~svn316068/lib/Target/Mips/MipsISelLowering.cpp"
, 2005, __PRETTY_FUNCTION__))
2005 "Floating point operand expected.")((Cond.getOpcode() == MipsISD::FPCmp && "Floating point operand expected."
) ? static_cast<void> (0) : __assert_fail ("Cond.getOpcode() == MipsISD::FPCmp && \"Floating point operand expected.\""
, "/build/llvm-toolchain-snapshot-6.0~svn316068/lib/Target/Mips/MipsISelLowering.cpp"
, 2005, __PRETTY_FUNCTION__))
;
2006
2007 SDLoc DL(Op);
2008 SDValue True = DAG.getConstant(1, DL, MVT::i32);
2009 SDValue False = DAG.getConstant(0, DL, MVT::i32);
2010
2011 return createCMovFP(DAG, Cond, True, False, DL);
2012}
2013
2014SDValue MipsTargetLowering::lowerGlobalAddress(SDValue Op,
2015 SelectionDAG &DAG) const {
2016 EVT Ty = Op.getValueType();
2017 GlobalAddressSDNode *N = cast<GlobalAddressSDNode>(Op);
2018 const GlobalValue *GV = N->getGlobal();
2019
2020 if (!isPositionIndependent()) {
2021 const MipsTargetObjectFile *TLOF =
2022 static_cast<const MipsTargetObjectFile *>(
2023 getTargetMachine().getObjFileLowering());
2024 const GlobalObject *GO = GV->getBaseObject();
2025 if (GO && TLOF->IsGlobalInSmallSection(GO, getTargetMachine()))
2026 // %gp_rel relocation
2027 return getAddrGPRel(N, SDLoc(N), Ty, DAG, ABI.IsN64());
2028
2029 // %hi/%lo relocation
2030 return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG)
2031 // %highest/%higher/%hi/%lo relocation
2032 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG);
2033 }
2034
2035 // Every other architecture would use shouldAssumeDSOLocal in here, but
2036 // mips is special.
2037 // * In PIC code mips requires got loads even for local statics!
2038 // * To save on got entries, for local statics the got entry contains the
2039 // page and an additional add instruction takes care of the low bits.
2040 // * It is legal to access a hidden symbol with a non hidden undefined,
2041 // so one cannot guarantee that all access to a hidden symbol will know
2042 // it is hidden.
2043 // * Mips linkers don't support creating a page and a full got entry for
2044 // the same symbol.
2045 // * Given all that, we have to use a full got entry for hidden symbols :-(
2046 if (GV->hasLocalLinkage())
2047 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64());
2048
2049 if (LargeGOT)
2050 return getAddrGlobalLargeGOT(
2051 N, SDLoc(N), Ty, DAG, MipsII::MO_GOT_HI16, MipsII::MO_GOT_LO16,
2052 DAG.getEntryNode(),
2053 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
2054
2055 return getAddrGlobal(
2056 N, SDLoc(N), Ty, DAG,
2057 (ABI.IsN32() || ABI.IsN64()) ? MipsII::MO_GOT_DISP : MipsII::MO_GOT,
2058 DAG.getEntryNode(), MachinePointerInfo::getGOT(DAG.getMachineFunction()));
2059}
2060
2061SDValue MipsTargetLowering::lowerBlockAddress(SDValue Op,
2062 SelectionDAG &DAG) const {
2063 BlockAddressSDNode *N = cast<BlockAddressSDNode>(Op);
2064 EVT Ty = Op.getValueType();
2065
2066 if (!isPositionIndependent())
2067 return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG)
2068 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG);
2069
2070 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64());
2071}
2072
2073SDValue MipsTargetLowering::
2074lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
2075{
2076 // If the relocation model is PIC, use the General Dynamic TLS Model or
2077 // Local Dynamic TLS model, otherwise use the Initial Exec or
2078 // Local Exec TLS Model.
2079
2080 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
2081 if (DAG.getTarget().Options.EmulatedTLS)
2082 return LowerToTLSEmulatedModel(GA, DAG);
2083
2084 SDLoc DL(GA);
2085 const GlobalValue *GV = GA->getGlobal();
2086 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2087
2088 TLSModel::Model model = getTargetMachine().getTLSModel(GV);
2089
2090 if (model == TLSModel::GeneralDynamic || model == TLSModel::LocalDynamic) {
2091 // General Dynamic and Local Dynamic TLS Model.
2092 unsigned Flag = (model == TLSModel::LocalDynamic) ? MipsII::MO_TLSLDM
2093 : MipsII::MO_TLSGD;
2094
2095 SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, Flag);
2096 SDValue Argument = DAG.getNode(MipsISD::Wrapper, DL, PtrVT,
2097 getGlobalReg(DAG, PtrVT), TGA);
2098 unsigned PtrSize = PtrVT.getSizeInBits();
2099 IntegerType *PtrTy = Type::getIntNTy(*DAG.getContext(), PtrSize);
2100
2101 SDValue TlsGetAddr = DAG.getExternalSymbol("__tls_get_addr", PtrVT);
2102
2103 ArgListTy Args;
2104 ArgListEntry Entry;
2105 Entry.Node = Argument;
2106 Entry.Ty = PtrTy;
2107 Args.push_back(Entry);
2108
2109 TargetLowering::CallLoweringInfo CLI(DAG);
2110 CLI.setDebugLoc(DL)
2111 .setChain(DAG.getEntryNode())
2112 .setLibCallee(CallingConv::C, PtrTy, TlsGetAddr, std::move(Args));
2113 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
2114
2115 SDValue Ret = CallResult.first;
2116
2117 if (model != TLSModel::LocalDynamic)
2118 return Ret;
2119
2120 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2121 MipsII::MO_DTPREL_HI);
2122 SDValue Hi = DAG.getNode(MipsISD::Hi, DL, PtrVT, TGAHi);
2123 SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2124 MipsII::MO_DTPREL_LO);
2125 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo);
2126 SDValue Add = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Ret);
2127 return DAG.getNode(ISD::ADD, DL, PtrVT, Add, Lo);
2128 }
2129
2130 SDValue Offset;
2131 if (model == TLSModel::InitialExec) {
2132 // Initial Exec TLS Model
2133 SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2134 MipsII::MO_GOTTPREL);
2135 TGA = DAG.getNode(MipsISD::Wrapper, DL, PtrVT, getGlobalReg(DAG, PtrVT),
2136 TGA);
2137 Offset =
2138 DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), TGA, MachinePointerInfo());
2139 } else {
2140 // Local Exec TLS Model
2141 assert(model == TLSModel::LocalExec)((model == TLSModel::LocalExec) ? static_cast<void> (0)
: __assert_fail ("model == TLSModel::LocalExec", "/build/llvm-toolchain-snapshot-6.0~svn316068/lib/Target/Mips/MipsISelLowering.cpp"
, 2141, __PRETTY_FUNCTION__))
;
2142 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2143 MipsII::MO_TPREL_HI);
2144 SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2145 MipsII::MO_TPREL_LO);
2146 SDValue Hi = DAG.getNode(MipsISD::Hi, DL, PtrVT, TGAHi);
2147 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo);
2148 Offset = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
2149 }
2150
2151 SDValue ThreadPointer = DAG.getNode(MipsISD::ThreadPointer, DL, PtrVT);
2152 return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadPointer, Offset);
2153}
2154
2155SDValue MipsTargetLowering::
2156lowerJumpTable(SDValue Op, SelectionDAG &DAG) const
2157{
2158 JumpTableSDNode *N = cast<JumpTableSDNode>(Op);
2159 EVT Ty = Op.getValueType();
2160
2161 if (!isPositionIndependent())
2162 return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG)
2163 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG);
2164
2165 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64());
2166}
2167
2168SDValue MipsTargetLowering::
2169lowerConstantPool(SDValue Op, SelectionDAG &DAG) const
2170{
2171 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
2172 EVT Ty = Op.getValueType();
2173
2174 if (!isPositionIndependent()) {
2175 const MipsTargetObjectFile *TLOF =
2176 static_cast<const MipsTargetObjectFile *>(
2177 getTargetMachine().getObjFileLowering());
2178
2179 if (TLOF->IsConstantInSmallSection(DAG.getDataLayout(), N->getConstVal(),
2180 getTargetMachine()))
2181 // %gp_rel relocation
2182 return getAddrGPRel(N, SDLoc(N), Ty, DAG, ABI.IsN64());
2183
2184 return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG)
2185 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG);
2186 }
2187
2188 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64());
2189}
2190
2191SDValue MipsTargetLowering::lowerVASTART(SDValue Op, SelectionDAG &DAG) const {
2192 MachineFunction &MF = DAG.getMachineFunction();
2193 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
2194
2195 SDLoc DL(Op);
2196 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
2197 getPointerTy(MF.getDataLayout()));
2198
2199 // vastart just stores the address of the VarArgsFrameIndex slot into the
2200 // memory location argument.
2201 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2202 return DAG.getStore(Op.getOperand(0), DL, FI, Op.getOperand(1),
2203 MachinePointerInfo(SV));
2204}
2205
2206SDValue MipsTargetLowering::lowerVAARG(SDValue Op, SelectionDAG &DAG) const {
2207 SDNode *Node = Op.getNode();
2208 EVT VT = Node->getValueType(0);
2209 SDValue Chain = Node->getOperand(0);
2210 SDValue VAListPtr = Node->getOperand(1);
2211 unsigned Align = Node->getConstantOperandVal(3);
2212 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
2213 SDLoc DL(Node);
2214 unsigned ArgSlotSizeInBytes = (ABI.IsN32() || ABI.IsN64()) ? 8 : 4;
2215
2216 SDValue VAListLoad = DAG.getLoad(getPointerTy(DAG.getDataLayout()), DL, Chain,
2217 VAListPtr, MachinePointerInfo(SV));
2218 SDValue VAList = VAListLoad;
2219
2220 // Re-align the pointer if necessary.
2221 // It should only ever be necessary for 64-bit types on O32 since the minimum
2222 // argument alignment is the same as the maximum type alignment for N32/N64.
2223 //
2224 // FIXME: We currently align too often. The code generator doesn't notice
2225 // when the pointer is still aligned from the last va_arg (or pair of
2226 // va_args for the i64 on O32 case).
2227 if (Align > getMinStackArgumentAlignment()) {
2228 assert(((Align & (Align-1)) == 0) && "Expected Align to be a power of 2")((((Align & (Align-1)) == 0) && "Expected Align to be a power of 2"
) ? static_cast<void> (0) : __assert_fail ("((Align & (Align-1)) == 0) && \"Expected Align to be a power of 2\""
, "/build/llvm-toolchain-snapshot-6.0~svn316068/lib/Target/Mips/MipsISelLowering.cpp"
, 2228, __PRETTY_FUNCTION__))
;
2229
2230 VAList = DAG.getNode(ISD::ADD, DL, VAList.getValueType(), VAList,
2231 DAG.getConstant(Align - 1, DL, VAList.getValueType()));
2232
2233 VAList = DAG.getNode(ISD::AND, DL, VAList.getValueType(), VAList,
2234 DAG.getConstant(-(int64_t)Align, DL,
2235 VAList.getValueType()));
2236 }
2237
2238 // Increment the pointer, VAList, to the next vaarg.
2239 auto &TD = DAG.getDataLayout();
2240 unsigned ArgSizeInBytes =
2241 TD.getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext()));
2242 SDValue Tmp3 =
2243 DAG.getNode(ISD::ADD, DL, VAList.getValueType(), VAList,
2244 DAG.getConstant(alignTo(ArgSizeInBytes, ArgSlotSizeInBytes),
2245 DL, VAList.getValueType()));
2246 // Store the incremented VAList to the legalized pointer
2247 Chain = DAG.getStore(VAListLoad.getValue(1), DL, Tmp3, VAListPtr,
2248 MachinePointerInfo(SV));
2249
2250 // In big-endian mode we must adjust the pointer when the load size is smaller
2251 // than the argument slot size. We must also reduce the known alignment to
2252 // match. For example in the N64 ABI, we must add 4 bytes to the offset to get
2253 // the correct half of the slot, and reduce the alignment from 8 (slot
2254 // alignment) down to 4 (type alignment).
2255 if (!Subtarget.isLittle() && ArgSizeInBytes < ArgSlotSizeInBytes) {
2256 unsigned Adjustment = ArgSlotSizeInBytes - ArgSizeInBytes;
2257 VAList = DAG.getNode(ISD::ADD, DL, VAListPtr.getValueType(), VAList,
2258 DAG.getIntPtrConstant(Adjustment, DL));
2259 }
2260 // Load the actual argument out of the pointer VAList
2261 return DAG.getLoad(VT, DL, Chain, VAList, MachinePointerInfo());
2262}
2263
2264static SDValue lowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG,
2265 bool HasExtractInsert) {
2266 EVT TyX = Op.getOperand(0).getValueType();
2267 EVT TyY = Op.getOperand(1).getValueType();
2268 SDLoc DL(Op);
2269 SDValue Const1 = DAG.getConstant(1, DL, MVT::i32);
2270 SDValue Const31 = DAG.getConstant(31, DL, MVT::i32);
2271 SDValue Res;
2272
2273 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it
2274 // to i32.
2275 SDValue X = (TyX == MVT::f32) ?
2276 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) :
2277 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0),
2278 Const1);
2279 SDValue Y = (TyY == MVT::f32) ?
2280 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(1)) :
2281 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(1),
2282 Const1);
2283
2284 if (HasExtractInsert) {
2285 // ext E, Y, 31, 1 ; extract bit31 of Y
2286 // ins X, E, 31, 1 ; insert extracted bit at bit31 of X
2287 SDValue E = DAG.getNode(MipsISD::Ext, DL, MVT::i32, Y, Const31, Const1);
2288 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, E, Const31, Const1, X);
2289 } else {
2290 // sll SllX, X, 1
2291 // srl SrlX, SllX, 1
2292 // srl SrlY, Y, 31
2293 // sll SllY, SrlX, 31
2294 // or Or, SrlX, SllY
2295 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1);
2296 SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1);
2297 SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31);
2298 SDValue SllY = DAG.getNode(ISD::SHL, DL, MVT::i32, SrlY, Const31);
2299 Res = DAG.getNode(ISD::OR, DL, MVT::i32, SrlX, SllY);
2300 }
2301
2302 if (TyX == MVT::f32)
2303 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Res);
2304
2305 SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
2306 Op.getOperand(0),
2307 DAG.getConstant(0, DL, MVT::i32));
2308 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res);
2309}
2310
2311static SDValue lowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG,
2312 bool HasExtractInsert) {
2313 unsigned WidthX = Op.getOperand(0).getValueSizeInBits();
2314 unsigned WidthY = Op.getOperand(1).getValueSizeInBits();
2315 EVT TyX = MVT::getIntegerVT(WidthX), TyY = MVT::getIntegerVT(WidthY);
2316 SDLoc DL(Op);
2317 SDValue Const1 = DAG.getConstant(1, DL, MVT::i32);
2318
2319 // Bitcast to integer nodes.
2320 SDValue X = DAG.getNode(ISD::BITCAST, DL, TyX, Op.getOperand(0));
2321 SDValue Y = DAG.getNode(ISD::BITCAST, DL, TyY, Op.getOperand(1));
2322
2323 if (HasExtractInsert) {
2324 // ext E, Y, width(Y) - 1, 1 ; extract bit width(Y)-1 of Y
2325 // ins X, E, width(X) - 1, 1 ; insert extracted bit at bit width(X)-1 of X
2326 SDValue E = DAG.getNode(MipsISD::Ext, DL, TyY, Y,
2327 DAG.getConstant(WidthY - 1, DL, MVT::i32), Const1);
2328
2329 if (WidthX > WidthY)
2330 E = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, E);
2331 else if (WidthY > WidthX)
2332 E = DAG.getNode(ISD::TRUNCATE, DL, TyX, E);
2333
2334 SDValue I = DAG.getNode(MipsISD::Ins, DL, TyX, E,
2335 DAG.getConstant(WidthX - 1, DL, MVT::i32), Const1,
2336 X);
2337 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), I);
2338 }
2339
2340 // (d)sll SllX, X, 1
2341 // (d)srl SrlX, SllX, 1
2342 // (d)srl SrlY, Y, width(Y)-1
2343 // (d)sll SllY, SrlX, width(Y)-1
2344 // or Or, SrlX, SllY
2345 SDValue SllX = DAG.getNode(ISD::SHL, DL, TyX, X, Const1);
2346 SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1);
2347 SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y,
2348 DAG.getConstant(WidthY - 1, DL, MVT::i32));
2349
2350 if (WidthX > WidthY)
2351 SrlY = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, SrlY);
2352 else if (WidthY > WidthX)
2353 SrlY = DAG.getNode(ISD::TRUNCATE, DL, TyX, SrlY);
2354
2355 SDValue SllY = DAG.getNode(ISD::SHL, DL, TyX, SrlY,
2356 DAG.getConstant(WidthX - 1, DL, MVT::i32));
2357 SDValue Or = DAG.getNode(ISD::OR, DL, TyX, SrlX, SllY);
2358 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Or);
2359}
2360
2361SDValue
2362MipsTargetLowering::lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
2363 if (Subtarget.isGP64bit())
2364 return lowerFCOPYSIGN64(Op, DAG, Subtarget.hasExtractInsert());
2365
2366 return lowerFCOPYSIGN32(Op, DAG, Subtarget.hasExtractInsert());
2367}
2368
2369SDValue MipsTargetLowering::
2370lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
2371 // check the depth
2372 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) &&(((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue
() == 0) && "Frame address can only be determined for current frame."
) ? static_cast<void> (0) : __assert_fail ("(cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) && \"Frame address can only be determined for current frame.\""
, "/build/llvm-toolchain-snapshot-6.0~svn316068/lib/Target/Mips/MipsISelLowering.cpp"
, 2373, __PRETTY_FUNCTION__))
2373 "Frame address can only be determined for current frame.")(((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue
() == 0) && "Frame address can only be determined for current frame."
) ? static_cast<void> (0) : __assert_fail ("(cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) && \"Frame address can only be determined for current frame.\""
, "/build/llvm-toolchain-snapshot-6.0~svn316068/lib/Target/Mips/MipsISelLowering.cpp"
, 2373, __PRETTY_FUNCTION__))
;
2374
2375 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
2376 MFI.setFrameAddressIsTaken(true);
2377 EVT VT = Op.getValueType();
2378 SDLoc DL(Op);
2379 SDValue FrameAddr = DAG.getCopyFromReg(
2380 DAG.getEntryNode(), DL, ABI.IsN64() ? Mips::FP_64 : Mips::FP, VT);
2381 return FrameAddr;
2382}
2383
2384SDValue MipsTargetLowering::lowerRETURNADDR(SDValue Op,
2385 SelectionDAG &DAG) const {
2386 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
2387 return SDValue();
2388
2389 // check the depth
2390 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) &&(((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue
() == 0) && "Return address can be determined only for current frame."
) ? static_cast<void> (0) : __assert_fail ("(cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) && \"Return address can be determined only for current frame.\""
, "/build/llvm-toolchain-snapshot-6.0~svn316068/lib/Target/Mips/MipsISelLowering.cpp"
, 2391, __PRETTY_FUNCTION__))
2391 "Return address can be determined only for current frame.")(((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue
() == 0) && "Return address can be determined only for current frame."
) ? static_cast<void> (0) : __assert_fail ("(cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) && \"Return address can be determined only for current frame.\""
, "/build/llvm-toolchain-snapshot-6.0~svn316068/lib/Target/Mips/MipsISelLowering.cpp"
, 2391, __PRETTY_FUNCTION__))
;
2392
2393 MachineFunction &MF = DAG.getMachineFunction();
2394 MachineFrameInfo &MFI = MF.getFrameInfo();
2395 MVT VT = Op.getSimpleValueType();
2396 unsigned RA = ABI.IsN64() ? Mips::RA_64 : Mips::RA;
2397 MFI.setReturnAddressIsTaken(true);
2398
2399 // Return RA, which contains the return address. Mark it an implicit live-in.
2400 unsigned Reg = MF.addLiveIn(RA, getRegClassFor(VT));
2401 return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(Op), Reg, VT);
2402}
2403
2404// An EH_RETURN is the result of lowering llvm.eh.return which in turn is
2405// generated from __builtin_eh_return (offset, handler)
2406// The effect of this is to adjust the stack pointer by "offset"
2407// and then branch to "handler".
2408SDValue MipsTargetLowering::lowerEH_RETURN(SDValue Op, SelectionDAG &DAG)
2409 const {
2410 MachineFunction &MF = DAG.getMachineFunction();
2411 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
2412
2413 MipsFI->setCallsEhReturn();
2414 SDValue Chain = Op.getOperand(0);
2415 SDValue Offset = Op.getOperand(1);
2416 SDValue Handler = Op.getOperand(2);
2417 SDLoc DL(Op);
2418 EVT Ty = ABI.IsN64() ? MVT::i64 : MVT::i32;
2419
2420 // Store stack offset in V1, store jump target in V0. Glue CopyToReg and
2421 // EH_RETURN nodes, so that instructions are emitted back-to-back.
2422 unsigned OffsetReg = ABI.IsN64() ? Mips::V1_64 : Mips::V1;
2423 unsigned AddrReg = ABI.IsN64() ? Mips::V0_64 : Mips::V0;
2424 Chain = DAG.getCopyToReg(Chain, DL, OffsetReg, Offset, SDValue());
2425 Chain = DAG.getCopyToReg(Chain, DL, AddrReg, Handler, Chain.getValue(1));
2426 return DAG.getNode(MipsISD::EH_RETURN, DL, MVT::Other, Chain,
2427 DAG.getRegister(OffsetReg, Ty),
2428 DAG.getRegister(AddrReg, getPointerTy(MF.getDataLayout())),
2429 Chain.getValue(1));
2430}
2431
2432SDValue MipsTargetLowering::lowerATOMIC_FENCE(SDValue Op,
2433 SelectionDAG &DAG) const {
2434 // FIXME: Need pseudo-fence for 'singlethread' fences
2435 // FIXME: Set SType for weaker fences where supported/appropriate.
2436 unsigned SType = 0;
2437 SDLoc DL(Op);
2438 return DAG.getNode(MipsISD::Sync, DL, MVT::Other, Op.getOperand(0),
2439 DAG.getConstant(SType, DL, MVT::i32));
2440}
2441
2442SDValue MipsTargetLowering::lowerShiftLeftParts(SDValue Op,
2443 SelectionDAG &DAG) const {
2444 SDLoc DL(Op);
2445 MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32;
2446
2447 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);
2448 SDValue Shamt = Op.getOperand(2);
2449 // if shamt < (VT.bits):
2450 // lo = (shl lo, shamt)
2451 // hi = (or (shl hi, shamt) (srl (srl lo, 1), ~shamt))
2452 // else:
2453 // lo = 0
2454 // hi = (shl lo, shamt[4:0])
2455 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
2456 DAG.getConstant(-1, DL, MVT::i32));
2457 SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, VT, Lo,
2458 DAG.getConstant(1, DL, VT));
2459 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, ShiftRight1Lo, Not);
2460 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, Hi, Shamt);
2461 SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo);
2462 SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt);
2463 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
2464 DAG.getConstant(VT.getSizeInBits(), DL, MVT::i32));
2465 Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond,
2466 DAG.getConstant(0, DL, VT), ShiftLeftLo);
2467 Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftLeftLo, Or);
2468
2469 SDValue Ops[2] = {Lo, Hi};
2470 return DAG.getMergeValues(Ops, DL);
2471}
2472
2473SDValue MipsTargetLowering::lowerShiftRightParts(SDValue Op, SelectionDAG &DAG,
2474 bool IsSRA) const {
2475 SDLoc DL(Op);
2476 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);
2477 SDValue Shamt = Op.getOperand(2);
2478 MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32;
2479
2480 // if shamt < (VT.bits):
2481 // lo = (or (shl (shl hi, 1), ~shamt) (srl lo, shamt))
2482 // if isSRA:
2483 // hi = (sra hi, shamt)
2484 // else:
2485 // hi = (srl hi, shamt)
2486 // else:
2487 // if isSRA:
2488 // lo = (sra hi, shamt[4:0])
2489 // hi = (sra hi, 31)
2490 // else:
2491 // lo = (srl hi, shamt[4:0])
2492 // hi = 0
2493 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
2494 DAG.getConstant(-1, DL, MVT::i32));
2495 SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, VT, Hi,
2496 DAG.getConstant(1, DL, VT));
2497 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, ShiftLeft1Hi, Not);
2498 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, Lo, Shamt);
2499 SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo);
2500 SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL,
2501 DL, VT, Hi, Shamt);
2502 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
2503 DAG.getConstant(VT.getSizeInBits(), DL, MVT::i32));
2504 SDValue Ext = DAG.getNode(ISD::SRA, DL, VT, Hi,
2505 DAG.getConstant(VT.getSizeInBits() - 1, DL, VT));
2506 Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftRightHi, Or);
2507 Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond,
2508 IsSRA ? Ext : DAG.getConstant(0, DL, VT), ShiftRightHi);
2509
2510 SDValue Ops[2] = {Lo, Hi};
2511 return DAG.getMergeValues(Ops, DL);
2512}
2513
2514static SDValue createLoadLR(unsigned Opc, SelectionDAG &DAG, LoadSDNode *LD,
2515 SDValue Chain, SDValue Src, unsigned Offset) {
2516 SDValue Ptr = LD->getBasePtr();
2517 EVT VT = LD->getValueType(0), MemVT = LD->getMemoryVT();
2518 EVT BasePtrVT = Ptr.getValueType();
2519 SDLoc DL(LD);
2520 SDVTList VTList = DAG.getVTList(VT, MVT::Other);
2521
2522 if (Offset)
2523 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr,
2524 DAG.getConstant(Offset, DL, BasePtrVT));
2525
2526 SDValue Ops[] = { Chain, Ptr, Src };
2527 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT,
2528 LD->getMemOperand());
2529}
2530
2531// Expand an unaligned 32 or 64-bit integer load node.
2532SDValue MipsTargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const {
2533 LoadSDNode *LD = cast<LoadSDNode>(Op);
2534 EVT MemVT = LD->getMemoryVT();
2535
2536 if (Subtarget.systemSupportsUnalignedAccess())
2537 return Op;
2538
2539 // Return if load is aligned or if MemVT is neither i32 nor i64.
2540 if ((LD->getAlignment() >= MemVT.getSizeInBits() / 8) ||
2541 ((MemVT != MVT::i32) && (MemVT != MVT::i64)))
2542 return SDValue();
2543
2544 bool IsLittle = Subtarget.isLittle();
2545 EVT VT = Op.getValueType();
2546 ISD::LoadExtType ExtType = LD->getExtensionType();
2547 SDValue Chain = LD->getChain(), Undef = DAG.getUNDEF(VT);
2548
2549 assert((VT == MVT::i32) || (VT == MVT::i64))(((VT == MVT::i32) || (VT == MVT::i64)) ? static_cast<void
> (0) : __assert_fail ("(VT == MVT::i32) || (VT == MVT::i64)"
, "/build/llvm-toolchain-snapshot-6.0~svn316068/lib/Target/Mips/MipsISelLowering.cpp"
, 2549, __PRETTY_FUNCTION__))
;
2550
2551 // Expand
2552 // (set dst, (i64 (load baseptr)))
2553 // to
2554 // (set tmp, (ldl (add baseptr, 7), undef))
2555 // (set dst, (ldr baseptr, tmp))
2556 if ((VT == MVT::i64) && (ExtType == ISD::NON_EXTLOAD)) {
2557 SDValue LDL = createLoadLR(MipsISD::LDL, DAG, LD, Chain, Undef,
2558 IsLittle ? 7 : 0);
2559 return createLoadLR(MipsISD::LDR, DAG, LD, LDL.getValue(1), LDL,
2560 IsLittle ? 0 : 7);
2561 }
2562
2563 SDValue LWL = createLoadLR(MipsISD::LWL, DAG, LD, Chain, Undef,
2564 IsLittle ? 3 : 0);
2565 SDValue LWR = createLoadLR(MipsISD::LWR, DAG, LD, LWL.getValue(1), LWL,
2566 IsLittle ? 0 : 3);
2567
2568 // Expand
2569 // (set dst, (i32 (load baseptr))) or
2570 // (set dst, (i64 (sextload baseptr))) or
2571 // (set dst, (i64 (extload baseptr)))
2572 // to
2573 // (set tmp, (lwl (add baseptr, 3), undef))
2574 // (set dst, (lwr baseptr, tmp))
2575 if ((VT == MVT::i32) || (ExtType == ISD::SEXTLOAD) ||
2576 (ExtType == ISD::EXTLOAD))
2577 return LWR;
2578
2579 assert((VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD))(((VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD)) ? static_cast
<void> (0) : __assert_fail ("(VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD)"
, "/build/llvm-toolchain-snapshot-6.0~svn316068/lib/Target/Mips/MipsISelLowering.cpp"
, 2579, __PRETTY_FUNCTION__))
;
2580
2581 // Expand
2582 // (set dst, (i64 (zextload baseptr)))
2583 // to
2584 // (set tmp0, (lwl (add baseptr, 3), undef))
2585 // (set tmp1, (lwr baseptr, tmp0))
2586 // (set tmp2, (shl tmp1, 32))
2587 // (set dst, (srl tmp2, 32))
2588 SDLoc DL(LD);
2589 SDValue Const32 = DAG.getConstant(32, DL, MVT::i32);
2590 SDValue SLL = DAG.getNode(ISD::SHL, DL, MVT::i64, LWR, Const32);
2591 SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32);
2592 SDValue Ops[] = { SRL, LWR.getValue(1) };
2593 return DAG.getMergeValues(Ops, DL);
2594}
2595
2596static SDValue createStoreLR(unsigned Opc, SelectionDAG &DAG, StoreSDNode *SD,
2597 SDValue Chain, unsigned Offset) {
2598 SDValue Ptr = SD->getBasePtr(), Value = SD->getValue();
2599 EVT MemVT = SD->getMemoryVT(), BasePtrVT = Ptr.getValueType();
2600 SDLoc DL(SD);
2601 SDVTList VTList = DAG.getVTList(MVT::Other);
2602
2603 if (Offset)
2604 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr,
2605 DAG.getConstant(Offset, DL, BasePtrVT));
2606
2607 SDValue Ops[] = { Chain, Value, Ptr };
2608 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT,
2609 SD->getMemOperand());
2610}
2611
2612// Expand an unaligned 32 or 64-bit integer store node.
2613static SDValue lowerUnalignedIntStore(StoreSDNode *SD, SelectionDAG &DAG,
2614 bool IsLittle) {
2615 SDValue Value = SD->getValue(), Chain = SD->getChain();
2616 EVT VT = Value.getValueType();
2617
2618 // Expand
2619 // (store val, baseptr) or
2620 // (truncstore val, baseptr)
2621 // to
2622 // (swl val, (add baseptr, 3))
2623 // (swr val, baseptr)
2624 if ((VT == MVT::i32) || SD->isTruncatingStore()) {
2625 SDValue SWL = createStoreLR(MipsISD::SWL, DAG, SD, Chain,
2626 IsLittle ? 3 : 0);
2627 return createStoreLR(MipsISD::SWR, DAG, SD, SWL, IsLittle ? 0 : 3);
2628 }
2629
2630 assert(VT == MVT::i64)((VT == MVT::i64) ? static_cast<void> (0) : __assert_fail
("VT == MVT::i64", "/build/llvm-toolchain-snapshot-6.0~svn316068/lib/Target/Mips/MipsISelLowering.cpp"
, 2630, __PRETTY_FUNCTION__))
;
2631
2632 // Expand
2633 // (store val, baseptr)
2634 // to
2635 // (sdl val, (add baseptr, 7))
2636 // (sdr val, baseptr)
2637 SDValue SDL = createStoreLR(MipsISD::SDL, DAG, SD, Chain, IsLittle ? 7 : 0);
2638 return createStoreLR(MipsISD::SDR, DAG, SD, SDL, IsLittle ? 0 : 7);
2639}
2640
2641// Lower (store (fp_to_sint $fp) $ptr) to (store (TruncIntFP $fp), $ptr).
2642static SDValue lowerFP_TO_SINT_STORE(StoreSDNode *SD, SelectionDAG &DAG) {
2643 SDValue Val = SD->getValue();
2644
2645 if (Val.getOpcode() != ISD::FP_TO_SINT)
2646 return SDValue();
2647
2648 EVT FPTy = EVT::getFloatingPointVT(Val.getValueSizeInBits());
2649 SDValue Tr = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Val), FPTy,
2650 Val.getOperand(0));
2651 return DAG.getStore(SD->getChain(), SDLoc(SD), Tr, SD->getBasePtr(),
2652 SD->getPointerInfo(), SD->getAlignment(),
2653 SD->getMemOperand()->getFlags());
2654}
2655
2656SDValue MipsTargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const {
2657 StoreSDNode *SD = cast<StoreSDNode>(Op);
2658 EVT MemVT = SD->getMemoryVT();
2659
2660 // Lower unaligned integer stores.
2661 if (!Subtarget.systemSupportsUnalignedAccess() &&
2662 (SD->getAlignment() < MemVT.getSizeInBits() / 8) &&
2663 ((MemVT == MVT::i32) || (MemVT == MVT::i64)))
2664 return lowerUnalignedIntStore(SD, DAG, Subtarget.isLittle());
2665
2666 return lowerFP_TO_SINT_STORE(SD, DAG);
2667}
2668
2669SDValue MipsTargetLowering::lowerEH_DWARF_CFA(SDValue Op,
2670 SelectionDAG &DAG) const {
2671
2672 // Return a fixed StackObject with offset 0 which points to the old stack
2673 // pointer.
2674 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
2675 EVT ValTy = Op->getValueType(0);
2676 int FI = MFI.CreateFixedObject(Op.getValueSizeInBits() / 8, 0, false);
2677 return DAG.getFrameIndex(FI, ValTy);
2678}
2679
2680SDValue MipsTargetLowering::lowerFP_TO_SINT(SDValue Op,
2681 SelectionDAG &DAG) const {
2682 EVT FPTy = EVT::getFloatingPointVT(Op.getValueSizeInBits());
2683 SDValue Trunc = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Op), FPTy,
2684 Op.getOperand(0));
2685 return DAG.getNode(ISD::BITCAST, SDLoc(Op), Op.getValueType(), Trunc);
2686}
2687
2688//===----------------------------------------------------------------------===//
2689// Calling Convention Implementation
2690//===----------------------------------------------------------------------===//
2691
2692//===----------------------------------------------------------------------===//
2693// TODO: Implement a generic logic using tblgen that can support this.
2694// Mips O32 ABI rules:
2695// ---
2696// i32 - Passed in A0, A1, A2, A3 and stack
2697// f32 - Only passed in f32 registers if no int reg has been used yet to hold
2698// an argument. Otherwise, passed in A1, A2, A3 and stack.
2699// f64 - Only passed in two aliased f32 registers if no int reg has been used
2700// yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is
2701// not used, it must be shadowed. If only A3 is available, shadow it and
2702// go to stack.
2703// vXiX - Received as scalarized i32s, passed in A0 - A3 and the stack.
2704// vXf32 - Passed in either a pair of registers {A0, A1}, {A2, A3} or {A0 - A3}
2705// with the remainder spilled to the stack.
2706// vXf64 - Passed in either {A0, A1, A2, A3} or {A2, A3} and in both cases
2707// spilling the remainder to the stack.
2708//
2709// For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack.
2710//===----------------------------------------------------------------------===//
2711
2712static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT,
2713 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
2714 CCState &State, ArrayRef<MCPhysReg> F64Regs) {
2715 const MipsSubtarget &Subtarget = static_cast<const MipsSubtarget &>(
2716 State.getMachineFunction().getSubtarget());
2717
2718 static const MCPhysReg IntRegs[] = { Mips::A0, Mips::A1, Mips::A2, Mips::A3 };
2719
2720 const MipsCCState * MipsState = static_cast<MipsCCState *>(&State);
2721
2722 static const MCPhysReg F32Regs[] = { Mips::F12, Mips::F14 };
2723
2724 static const MCPhysReg FloatVectorIntRegs[] = { Mips::A0, Mips::A2 };
2725
2726 // Do not process byval args here.
2727 if (ArgFlags.isByVal())
2728 return true;
2729
2730 // Promote i8 and i16
2731 if (ArgFlags.isInReg() && !Subtarget.isLittle()) {
2732 if (LocVT == MVT::i8 || LocVT == MVT::i16 || LocVT == MVT::i32) {
2733 LocVT = MVT::i32;
2734 if (ArgFlags.isSExt())
2735 LocInfo = CCValAssign::SExtUpper;
2736 else if (ArgFlags.isZExt())
2737 LocInfo = CCValAssign::ZExtUpper;
2738 else
2739 LocInfo = CCValAssign::AExtUpper;
2740 }
2741 }
2742
2743 // Promote i8 and i16
2744 if (LocVT == MVT::i8 || LocVT == MVT::i16) {
2745 LocVT = MVT::i32;
2746 if (ArgFlags.isSExt())
2747 LocInfo = CCValAssign::SExt;
2748 else if (ArgFlags.isZExt())
2749 LocInfo = CCValAssign::ZExt;
2750 else
2751 LocInfo = CCValAssign::AExt;
2752 }
2753
2754 unsigned Reg;
2755
2756 // f32 and f64 are allocated in A0, A1, A2, A3 when either of the following
2757 // is true: function is vararg, argument is 3rd or higher, there is previous
2758 // argument which is not f32 or f64.
2759 bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1 ||
2760 State.getFirstUnallocated(F32Regs) != ValNo;
2761 unsigned OrigAlign = ArgFlags.getOrigAlign();
2762 bool isI64 = (ValVT == MVT::i32 && OrigAlign == 8);
2763 bool isVectorFloat = MipsState->WasOriginalArgVectorFloat(ValNo);
2764
2765 // The MIPS vector ABI for floats passes them in a pair of registers
2766 if (ValVT == MVT::i32 && isVectorFloat) {
2767 // This is the start of an vector that was scalarized into an unknown number
2768 // of components. It doesn't matter how many there are. Allocate one of the
2769 // notional 8 byte aligned registers which map onto the argument stack, and
2770 // shadow the register lost to alignment requirements.
2771 if (ArgFlags.isSplit()) {
2772 Reg = State.AllocateReg(FloatVectorIntRegs);
2773 if (Reg == Mips::A2)
2774 State.AllocateReg(Mips::A1);
2775 else if (Reg == 0)
2776 State.AllocateReg(Mips::A3);
2777 } else {
2778 // If we're an intermediate component of the split, we can just attempt to
2779 // allocate a register directly.
2780 Reg = State.AllocateReg(IntRegs);
2781 }
2782 } else if (ValVT == MVT::i32 || (ValVT == MVT::f32 && AllocateFloatsInIntReg)) {
2783 Reg = State.AllocateReg(IntRegs);
2784 // If this is the first part of an i64 arg,
2785 // the allocated register must be either A0 or A2.
2786 if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3))
2787 Reg = State.AllocateReg(IntRegs);
2788 LocVT = MVT::i32;
2789 } else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) {
2790 // Allocate int register and shadow next int register. If first
2791 // available register is Mips::A1 or Mips::A3, shadow it too.
2792 Reg = State.AllocateReg(IntRegs);
2793 if (Reg == Mips::A1 || Reg == Mips::A3)
2794 Reg = State.AllocateReg(IntRegs);
2795 State.AllocateReg(IntRegs);
2796 LocVT = MVT::i32;
2797 } else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) {
2798 // we are guaranteed to find an available float register
2799 if (ValVT == MVT::f32) {
2800 Reg = State.AllocateReg(F32Regs);
2801 // Shadow int register
2802 State.AllocateReg(IntRegs);
2803 } else {
2804 Reg = State.AllocateReg(F64Regs);
2805 // Shadow int registers
2806 unsigned Reg2 = State.AllocateReg(IntRegs);
2807 if (Reg2 == Mips::A1 || Reg2 == Mips::A3)
2808 State.AllocateReg(IntRegs);
2809 State.AllocateReg(IntRegs);
2810 }
2811 } else
2812 llvm_unreachable("Cannot handle this ValVT.")::llvm::llvm_unreachable_internal("Cannot handle this ValVT."
, "/build/llvm-toolchain-snapshot-6.0~svn316068/lib/Target/Mips/MipsISelLowering.cpp"
, 2812)
;
2813
2814 if (!Reg) {
2815 unsigned Offset = State.AllocateStack(ValVT.getSizeInBits() >> 3,
2816 OrigAlign);
2817 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
2818 } else
2819 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2820
2821 return false;
2822}
2823
2824static bool CC_MipsO32_FP32(unsigned ValNo, MVT ValVT,
2825 MVT LocVT, CCValAssign::LocInfo LocInfo,
2826 ISD::ArgFlagsTy ArgFlags, CCState &State) {
2827 static const MCPhysReg F64Regs[] = { Mips::D6, Mips::D7 };
2828
2829 return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs);
2830}
2831
2832static bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT,
2833 MVT LocVT, CCValAssign::LocInfo LocInfo,
2834 ISD::ArgFlagsTy ArgFlags, CCState &State) {
2835 static const MCPhysReg F64Regs[] = { Mips::D12_64, Mips::D14_64 };
2836
2837 return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs);
2838}
2839
2840static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT,
2841 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
2842 CCState &State) LLVM_ATTRIBUTE_UNUSED__attribute__((__unused__));
2843
2844#include "MipsGenCallingConv.inc"
2845
2846//===----------------------------------------------------------------------===//
2847// Call Calling Convention Implementation
2848//===----------------------------------------------------------------------===//
2849
2850// Return next O32 integer argument register.
2851static unsigned getNextIntArgReg(unsigned Reg) {
2852 assert((Reg == Mips::A0) || (Reg == Mips::A2))(((Reg == Mips::A0) || (Reg == Mips::A2)) ? static_cast<void
> (0) : __assert_fail ("(Reg == Mips::A0) || (Reg == Mips::A2)"
, "/build/llvm-toolchain-snapshot-6.0~svn316068/lib/Target/Mips/MipsISelLowering.cpp"
, 2852, __PRETTY_FUNCTION__))
;
2853 return (Reg == Mips::A0) ? Mips::A1 : Mips::A3;
2854}
2855
2856SDValue MipsTargetLowering::passArgOnStack(SDValue StackPtr, unsigned Offset,
2857 SDValue Chain, SDValue Arg,
2858 const SDLoc &DL, bool IsTailCall,
2859 SelectionDAG &DAG) const {
2860 if (!IsTailCall) {
2861 SDValue PtrOff =
2862 DAG.getNode(ISD::ADD, DL, getPointerTy(DAG.getDataLayout()), StackPtr,
2863 DAG.getIntPtrConstant(Offset, DL));
2864 return DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo());
2865 }
2866
2867 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
2868 int FI = MFI.CreateFixedObject(Arg.getValueSizeInBits() / 8, Offset, false);
2869 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
2870 return DAG.getStore(Chain, DL, Arg, FIN, MachinePointerInfo(),
2871 /* Alignment = */ 0, MachineMemOperand::MOVolatile);
2872}
2873
2874void MipsTargetLowering::
2875getOpndList(SmallVectorImpl<SDValue> &Ops,
2876 std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
2877 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
2878 bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee,
2879 SDValue Chain) const {
2880 // Insert node "GP copy globalreg" before call to function.
2881 //
2882 // R_MIPS_CALL* operators (emitted when non-internal functions are called
2883 // in PIC mode) allow symbols to be resolved via lazy binding.
2884 // The lazy binding stub requires GP to point to the GOT.
2885 // Note that we don't need GP to point to the GOT for indirect calls
2886 // (when R_MIPS_CALL* is not used for the call) because Mips linker generates
2887 // lazy binding stub for a function only when R_MIPS_CALL* are the only relocs
2888 // used for the function (that is, Mips linker doesn't generate lazy binding
2889 // stub for a function whose address is taken in the program).
2890 if (IsPICCall && !InternalLinkage && IsCallReloc) {
2891 unsigned GPReg = ABI.IsN64() ? Mips::GP_64 : Mips::GP;
2892 EVT Ty = ABI.IsN64() ? MVT::i64 : MVT::i32;
2893 RegsToPass.push_back(std::make_pair(GPReg, getGlobalReg(CLI.DAG, Ty)));
2894 }
2895
2896 // Build a sequence of copy-to-reg nodes chained together with token
2897 // chain and flag operands which copy the outgoing args into registers.
2898 // The InFlag in necessary since all emitted instructions must be
2899 // stuck together.
2900 SDValue InFlag;
2901
2902 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2903 Chain = CLI.DAG.getCopyToReg(Chain, CLI.DL, RegsToPass[i].first,
2904 RegsToPass[i].second, InFlag);
2905 InFlag = Chain.getValue(1);
2906 }
2907
2908 // Add argument registers to the end of the list so that they are
2909 // known live into the call.
2910 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2911 Ops.push_back(CLI.DAG.getRegister(RegsToPass[i].first,
2912 RegsToPass[i].second.getValueType()));
2913
2914 // Add a register mask operand representing the call-preserved registers.
2915 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
2916 const uint32_t *Mask =
2917 TRI->getCallPreservedMask(CLI.DAG.getMachineFunction(), CLI.CallConv);
2918 assert(Mask && "Missing call preserved mask for calling convention")((Mask && "Missing call preserved mask for calling convention"
) ? static_cast<void> (0) : __assert_fail ("Mask && \"Missing call preserved mask for calling convention\""
, "/build/llvm-toolchain-snapshot-6.0~svn316068/lib/Target/Mips/MipsISelLowering.cpp"
, 2918, __PRETTY_FUNCTION__))
;
2919 if (Subtarget.inMips16HardFloat()) {
2920 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(CLI.Callee)) {
2921 StringRef Sym = G->getGlobal()->getName();
2922 Function *F = G->getGlobal()->getParent()->getFunction(Sym);
2923 if (F && F->hasFnAttribute("__Mips16RetHelper")) {
2924 Mask = MipsRegisterInfo::getMips16RetHelperMask();
2925 }
2926 }
2927 }
2928 Ops.push_back(CLI.DAG.getRegisterMask(Mask));
2929
2930 if (InFlag.getNode())
2931 Ops.push_back(InFlag);
2932}
2933
2934/// LowerCall - functions arguments are copied from virtual regs to
2935/// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
2936SDValue
2937MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2938 SmallVectorImpl<SDValue> &InVals) const {
2939 SelectionDAG &DAG = CLI.DAG;
2940 SDLoc DL = CLI.DL;
2941 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2942 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2943 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2944 SDValue Chain = CLI.Chain;
2945 SDValue Callee = CLI.Callee;
2946 bool &IsTailCall = CLI.IsTailCall;
2947 CallingConv::ID CallConv = CLI.CallConv;
2948 bool IsVarArg = CLI.IsVarArg;
2949
2950 MachineFunction &MF = DAG.getMachineFunction();
2951 MachineFrameInfo &MFI = MF.getFrameInfo();
2952 const TargetFrameLowering *TFL = Subtarget.getFrameLowering();
2953 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
2954 bool IsPIC = isPositionIndependent();
2955
2956 // Analyze operands of the call, assigning locations to each operand.
2957 SmallVector<CCValAssign, 16> ArgLocs;
2958 MipsCCState CCInfo(
2959 CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, *DAG.getContext(),
2960 MipsCCState::getSpecialCallingConvForCallee(Callee.getNode(), Subtarget));
2961
2962 // Allocate the reserved argument area. It seems strange to do this from the
2963 // caller side but removing it breaks the frame size calculation.
2964 CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(CallConv), 1);
2965
2966 const ExternalSymbolSDNode *ES =
2967 dyn_cast_or_null<const ExternalSymbolSDNode>(Callee.getNode());
2968 CCInfo.AnalyzeCallOperands(Outs, CC_Mips, CLI.getArgs(),
2969 ES ? ES->getSymbol() : nullptr);
2970
2971 // Get a count of how many bytes are to be pushed on the stack.
2972 unsigned NextStackOffset = CCInfo.getNextStackOffset();
2973
2974 // Check if it's really possible to do a tail call. Restrict it to functions
2975 // that are part of this compilation unit.
2976 bool InternalLinkage = false;
2977 if (IsTailCall) {
2978 IsTailCall = isEligibleForTailCallOptimization(
2979 CCInfo, NextStackOffset, *MF.getInfo<MipsFunctionInfo>());
2980 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2981 InternalLinkage = G->getGlobal()->hasInternalLinkage();
2982 IsTailCall &= (InternalLinkage || G->getGlobal()->hasLocalLinkage() ||
2983 G->getGlobal()->hasPrivateLinkage() ||
2984 G->getGlobal()->hasHiddenVisibility() ||
2985 G->getGlobal()->hasProtectedVisibility());
2986 }
2987 }
2988 if (!IsTailCall && CLI.CS && CLI.CS.isMustTailCall())
2989 report_fatal_error("failed to perform tail call elimination on a call "
2990 "site marked musttail");
2991
2992 if (IsTailCall)
2993 ++NumTailCalls;
2994
2995 SDValue StackPtr =
2996 DAG.getCopyFromReg(Chain, DL, ABI.IsN64() ? Mips::SP_64 : Mips::SP,
2997 getPointerTy(DAG.getDataLayout()));
2998
2999 std::deque<std::pair<unsigned, SDValue>> RegsToPass;
3000 SmallVector<SDValue, 8> MemOpChains;
3001
3002 CCInfo.rewindByValRegsInfo();
3003
3004 // Walk the register/memloc assignments, inserting copies/loads.
3005 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3006 SDValue Arg = OutVals[i];
3007 CCValAssign &VA = ArgLocs[i];
3008 MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT();
3009 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3010 bool UseUpperBits = false;
3011
3012 // ByVal Arg.
3013 if (Flags.isByVal()) {
3014 unsigned FirstByValReg, LastByValReg;
3015 unsigned ByValIdx = CCInfo.getInRegsParamsProcessed();
3016 CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg);
3017
3018 assert(Flags.getByValSize() &&((Flags.getByValSize() && "ByVal args of size 0 should have been ignored by front-end."
) ? static_cast<void> (0) : __assert_fail ("Flags.getByValSize() && \"ByVal args of size 0 should have been ignored by front-end.\""
, "/build/llvm-toolchain-snapshot-6.0~svn316068/lib/Target/Mips/MipsISelLowering.cpp"
, 3019, __PRETTY_FUNCTION__))
3019 "ByVal args of size 0 should have been ignored by front-end.")((Flags.getByValSize() && "ByVal args of size 0 should have been ignored by front-end."
) ? static_cast<void> (0) : __assert_fail ("Flags.getByValSize() && \"ByVal args of size 0 should have been ignored by front-end.\""
, "/build/llvm-toolchain-snapshot-6.0~svn316068/lib/Target/Mips/MipsISelLowering.cpp"
, 3019, __PRETTY_FUNCTION__))
;
3020 assert(ByValIdx < CCInfo.getInRegsParamsCount())((ByValIdx < CCInfo.getInRegsParamsCount()) ? static_cast<
void> (0) : __assert_fail ("ByValIdx < CCInfo.getInRegsParamsCount()"
, "/build/llvm-toolchain-snapshot-6.0~svn316068/lib/Target/Mips/MipsISelLowering.cpp"
, 3020, __PRETTY_FUNCTION__))
;
3021 assert(!IsTailCall &&((!IsTailCall && "Do not tail-call optimize if there is a byval argument."
) ? static_cast<void> (0) : __assert_fail ("!IsTailCall && \"Do not tail-call optimize if there is a byval argument.\""
, "/build/llvm-toolchain-snapshot-6.0~svn316068/lib/Target/Mips/MipsISelLowering.cpp"
, 3022, __PRETTY_FUNCTION__))
3022 "Do not tail-call optimize if there is a byval argument.")((!IsTailCall && "Do not tail-call optimize if there is a byval argument."
) ? static_cast<void> (0) : __assert_fail ("!IsTailCall && \"Do not tail-call optimize if there is a byval argument.\""
, "/build/llvm-toolchain-snapshot-6.0~svn316068/lib/Target/Mips/MipsISelLowering.cpp"
, 3022, __PRETTY_FUNCTION__))
;
3023 Chain = passByValArg(Chain, DL, RegsToPass, MemOpChains, StackPtr, MFI, DAG, Arg,
3024 FirstByValReg, LastByValReg, Flags, Subtarget.isLittle(),
3025 VA);
3026 CCInfo.nextInRegsParam();
3027 continue;
3028 }
3029
3030 // Promote the value if needed.
3031 switch (VA.getLocInfo()) {
3032 default:
3033 llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-6.0~svn316068/lib/Target/Mips/MipsISelLowering.cpp"
, 3033)
;
3034 case CCValAssign::Full:
3035 if (VA.isRegLoc()) {
3036 if ((ValVT == MVT::f32 && LocVT == MVT::i32) ||
3037 (ValVT == MVT::f64 && LocVT == MVT::i64) ||
3038 (ValVT == MVT::i64 && LocVT == MVT::f64))
3039 Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg);
3040 else if (ValVT == MVT::f64 && LocVT == MVT::i32) {
3041 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
3042 Arg, DAG.getConstant(0, DL, MVT::i32));
3043 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
3044 Arg, DAG.getConstant(1, DL, MVT::i32));
3045 if (!Subtarget.isLittle())
3046 std::swap(Lo, Hi);
3047 unsigned LocRegLo = VA.getLocReg();
3048 unsigned LocRegHigh = getNextIntArgReg(LocRegLo);
3049 RegsToPass.push_back(std::make_pair(LocRegLo, Lo));
3050 RegsToPass.push_back(std::make_pair(LocRegHigh, Hi));
3051 continue;
3052 }
3053 }
3054 break;
3055 case CCValAssign::BCvt:
3056 Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg);
3057 break;
3058 case CCValAssign::SExtUpper:
3059 UseUpperBits = true;
3060 LLVM_FALLTHROUGH[[clang::fallthrough]];
3061 case CCValAssign::SExt:
3062 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, LocVT, Arg);
3063 break;
3064 case CCValAssign::ZExtUpper:
3065 UseUpperBits = true;
3066 LLVM_FALLTHROUGH[[clang::fallthrough]];
3067 case CCValAssign::ZExt:
3068 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, LocVT, Arg);
3069 break;
3070 case CCValAssign::AExtUpper:
3071 UseUpperBits = true;
3072 LLVM_FALLTHROUGH[[clang::fallthrough]];
3073 case CCValAssign::AExt:
3074 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, LocVT, Arg);
3075 break;
3076 }
3077
3078 if (UseUpperBits) {
3079 unsigned ValSizeInBits = Outs[i].ArgVT.getSizeInBits();
3080 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
3081 Arg = DAG.getNode(
3082 ISD::SHL, DL, VA.getLocVT(), Arg,
3083 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT()));
3084 }
3085
3086 // Arguments that can be passed on register must be kept at
3087 // RegsToPass vector
3088 if (VA.isRegLoc()) {
3089 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
3090 continue;
3091 }
3092
3093 // Register can't get to this point...
3094 assert(VA.isMemLoc())((VA.isMemLoc()) ? static_cast<void> (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-6.0~svn316068/lib/Target/Mips/MipsISelLowering.cpp"
, 3094, __PRETTY_FUNCTION__))
;
3095
3096 // emit ISD::STORE whichs stores the
3097 // parameter value to a stack Location
3098 MemOpChains.push_back(passArgOnStack(StackPtr, VA.getLocMemOffset(),
3099 Chain, Arg, DL, IsTailCall, DAG));
3100 }
3101
3102 // Transform all store nodes into one single node because all store
3103 // nodes are independent of each other.
3104 if (!MemOpChains.empty())
3105 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
3106
3107 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
3108 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
3109 // node so that legalize doesn't hack it.
3110
3111 EVT Ty = Callee.getValueType();
3112 bool GlobalOrExternal = false, IsCallReloc = false;
3113
3114 // Chain is the output chain of the last Load/Store or CopyToReg node.
3115 // ByValChain is the output chain of the last Memcpy node created for copying
3116 // byval arguments to the stack.
3117 unsigned StackAlignment = TFL->getStackAlignment();
3118 NextStackOffset = alignTo(NextStackOffset, StackAlignment);
3119 SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, DL, true);
3120
3121 if (!IsTailCall)
3122 Chain = DAG.getCALLSEQ_START(Chain, NextStackOffset, 0, DL);
3123
3124 // The long-calls feature is ignored in case of PIC.
3125 // While we do not support -mshared / -mno-shared properly,
3126 // ignore long-calls in case of -mabicalls too.
3127 if (!Subtarget.isABICalls() && !IsPIC) {
3128 // If the function should be called using "long call",
3129 // get its address into a register to prevent using
3130 // of the `jal` instruction for the direct call.
3131 if (auto *N = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3132 if (Subtarget.useLongCalls())
3133 Callee = Subtarget.hasSym32()
3134 ? getAddrNonPIC(N, SDLoc(N), Ty, DAG)
3135 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG);
3136 } else if (auto *N = dyn_cast<GlobalAddressSDNode>(Callee)) {
3137 bool UseLongCalls = Subtarget.useLongCalls();
3138 // If the function has long-call/far/near attribute
3139 // it overrides command line switch pased to the backend.
3140 if (auto *F = dyn_cast<Function>(N->getGlobal())) {
3141 if (F->hasFnAttribute("long-call"))
3142 UseLongCalls = true;
3143 else if (F->hasFnAttribute("short-call"))
3144 UseLongCalls = false;
3145 }
3146 if (UseLongCalls)
3147 Callee = Subtarget.hasSym32()
3148 ? getAddrNonPIC(N, SDLoc(N), Ty, DAG)
3149 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG);
3150 }
3151 }
3152
3153 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3154 if (IsPIC) {
3155 const GlobalValue *Val = G->getGlobal();
3156 InternalLinkage = Val->hasInternalLinkage();
3157
3158 if (InternalLinkage)
3159 Callee = getAddrLocal(G, DL, Ty, DAG, ABI.IsN32() || ABI.IsN64());
3160 else if (LargeGOT) {
3161 Callee = getAddrGlobalLargeGOT(G, DL, Ty, DAG, MipsII::MO_CALL_HI16,
3162 MipsII::MO_CALL_LO16, Chain,
3163 FuncInfo->callPtrInfo(Val));
3164 IsCallReloc = true;
3165 } else {
3166 Callee = getAddrGlobal(G, DL, Ty, DAG, MipsII::MO_GOT_CALL, Chain,
3167 FuncInfo->callPtrInfo(Val));
3168 IsCallReloc = true;
3169 }
3170 } else
3171 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL,
3172 getPointerTy(DAG.getDataLayout()), 0,
3173 MipsII::MO_NO_FLAG);
3174 GlobalOrExternal = true;
3175 }
3176 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3177 const char *Sym = S->getSymbol();
3178
3179 if (!IsPIC) // static
3180 Callee = DAG.getTargetExternalSymbol(
3181 Sym, getPointerTy(DAG.getDataLayout()), MipsII::MO_NO_FLAG);
3182 else if (LargeGOT) {
3183 Callee = getAddrGlobalLargeGOT(S, DL, Ty, DAG, MipsII::MO_CALL_HI16,
3184 MipsII::MO_CALL_LO16, Chain,
3185 FuncInfo->callPtrInfo(Sym));
3186 IsCallReloc = true;
3187 } else { // PIC
3188 Callee = getAddrGlobal(S, DL, Ty, DAG, MipsII::MO_GOT_CALL, Chain,
3189 FuncInfo->callPtrInfo(Sym));
3190 IsCallReloc = true;
3191 }
3192
3193 GlobalOrExternal = true;
3194 }
3195
3196 SmallVector<SDValue, 8> Ops(1, Chain);
3197 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3198
3199 getOpndList(Ops, RegsToPass, IsPIC, GlobalOrExternal, InternalLinkage,
3200 IsCallReloc, CLI, Callee, Chain);
3201
3202 if (IsTailCall) {
3203 MF.getFrameInfo().setHasTailCall();
3204 return DAG.getNode(MipsISD::TailCall, DL, MVT::Other, Ops);
3205 }
3206
3207 Chain = DAG.getNode(MipsISD::JmpLink, DL, NodeTys, Ops);
3208 SDValue InFlag = Chain.getValue(1);
3209
3210 // Create the CALLSEQ_END node.
3211 Chain = DAG.getCALLSEQ_END(Chain, NextStackOffsetVal,
3212 DAG.getIntPtrConstant(0, DL, true), InFlag, DL);
3213 InFlag = Chain.getValue(1);
3214
3215 // Handle result values, copying them out of physregs into vregs that we
3216 // return.
3217 return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG,
3218 InVals, CLI);
3219}
3220
3221/// LowerCallResult - Lower the result values of a call into the
3222/// appropriate copies out of appropriate physical registers.
3223SDValue MipsTargetLowering::LowerCallResult(
3224 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool IsVarArg,
3225 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
3226 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals,
3227 TargetLowering::CallLoweringInfo &CLI) const {
3228 // Assign locations to each value returned by this call.
3229 SmallVector<CCValAssign, 16> RVLocs;
3230 MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
3231 *DAG.getContext());
3232
3233 const ExternalSymbolSDNode *ES =
3234 dyn_cast_or_null<const ExternalSymbolSDNode>(CLI.Callee.getNode());
3235 CCInfo.AnalyzeCallResult(Ins, RetCC_Mips, CLI.RetTy,
3236 ES ? ES->getSymbol() : nullptr);
3237
3238 // Copy all of the result registers out of their specified physreg.
3239 for (unsigned i = 0; i != RVLocs.size(); ++i) {
3240 CCValAssign &VA = RVLocs[i];
3241 assert(VA.isRegLoc() && "Can only return in registers!")((VA.isRegLoc() && "Can only return in registers!") ?
static_cast<void> (0) : __assert_fail ("VA.isRegLoc() && \"Can only return in registers!\""
, "/build/llvm-toolchain-snapshot-6.0~svn316068/lib/Target/Mips/MipsISelLowering.cpp"
, 3241, __PRETTY_FUNCTION__))
;
3242
3243 SDValue Val = DAG.getCopyFromReg(Chain, DL, RVLocs[i].getLocReg(),
3244 RVLocs[i].getLocVT(), InFlag);
3245 Chain = Val.getValue(1);
3246 InFlag = Val.getValue(2);
3247
3248 if (VA.isUpperBitsInLoc()) {
3249 unsigned ValSizeInBits = Ins[i].ArgVT.getSizeInBits();
3250 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
3251 unsigned Shift =
3252 VA.getLocInfo() == CCValAssign::ZExtUpper ? ISD::SRL : ISD::SRA;
3253 Val = DAG.getNode(
3254 Shift, DL, VA.getLocVT(), Val,
3255 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT()));
3256 }
3257
3258 switch (VA.getLocInfo()) {
3259 default:
3260 llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-6.0~svn316068/lib/Target/Mips/MipsISelLowering.cpp"
, 3260)
;
3261 case CCValAssign::Full:
3262 break;
3263 case CCValAssign::BCvt:
3264 Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val);
3265 break;
3266 case CCValAssign::AExt:
3267 case CCValAssign::AExtUpper:
3268 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
3269 break;
3270 case CCValAssign::ZExt:
3271 case CCValAssign::ZExtUpper:
3272 Val = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Val,
3273 DAG.getValueType(VA.getValVT()));
3274 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
3275 break;
3276 case CCValAssign::SExt:
3277 case CCValAssign::SExtUpper:
3278 Val = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Val,
3279 DAG.getValueType(VA.getValVT()));
3280 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
3281 break;
3282 }
3283
3284 InVals.push_back(Val);
3285 }
3286
3287 return Chain;
3288}
3289
3290static SDValue UnpackFromArgumentSlot(SDValue Val, const CCValAssign &VA,
3291 EVT ArgVT, const SDLoc &DL,
3292 SelectionDAG &DAG) {
3293 MVT LocVT = VA.getLocVT();
3294 EVT ValVT = VA.getValVT();
3295
3296 // Shift into the upper bits if necessary.
3297 switch (VA.getLocInfo()) {
3298 default:
3299 break;
3300 case CCValAssign::AExtUpper:
3301 case CCValAssign::SExtUpper:
3302 case CCValAssign::ZExtUpper: {
3303 unsigned ValSizeInBits = ArgVT.getSizeInBits();
3304 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
3305 unsigned Opcode =
3306 VA.getLocInfo() == CCValAssign::ZExtUpper ? ISD::SRL : ISD::SRA;
3307 Val = DAG.getNode(
3308 Opcode, DL, VA.getLocVT(), Val,
3309 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT()));
3310 break;
3311 }
3312 }
3313
3314 // If this is an value smaller than the argument slot size (32-bit for O32,
3315 // 64-bit for N32/N64), it has been promoted in some way to the argument slot
3316 // size. Extract the value and insert any appropriate assertions regarding
3317 // sign/zero extension.
3318 switch (VA.getLocInfo()) {
3319 default:
3320 llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-6.0~svn316068/lib/Target/Mips/MipsISelLowering.cpp"
, 3320)
;
3321 case CCValAssign::Full:
3322 break;
3323 case CCValAssign::AExtUpper:
3324 case CCValAssign::AExt:
3325 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val);
3326 break;
3327 case CCValAssign::SExtUpper:
3328 case CCValAssign::SExt:
3329 Val = DAG.getNode(ISD::AssertSext, DL, LocVT, Val, DAG.getValueType(ValVT));
3330 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val);
3331 break;
3332 case CCValAssign::ZExtUpper:
3333 case CCValAssign::ZExt:
3334 Val = DAG.getNode(ISD::AssertZext, DL, LocVT, Val, DAG.getValueType(ValVT));
3335 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val);
3336 break;
3337 case CCValAssign::BCvt:
3338 Val = DAG.getNode(ISD::BITCAST, DL, ValVT, Val);
3339 break;
3340 }
3341
3342 return Val;
3343}
3344
3345//===----------------------------------------------------------------------===//
3346// Formal Arguments Calling Convention Implementation
3347//===----------------------------------------------------------------------===//
3348/// LowerFormalArguments - transform physical registers into virtual registers
3349/// and generate load operations for arguments places on the stack.
3350SDValue MipsTargetLowering::LowerFormalArguments(
3351 SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
3352 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
3353 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
3354 MachineFunction &MF = DAG.getMachineFunction();
3355 MachineFrameInfo &MFI = MF.getFrameInfo();
3356 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
3357
3358 MipsFI->setVarArgsFrameIndex(0);
3359
3360 // Used with vargs to acumulate store chains.
3361 std::vector<SDValue> OutChains;
3362
3363 // Assign locations to all of the incoming arguments.
3364 SmallVector<CCValAssign, 16> ArgLocs;
3365 MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
3366 *DAG.getContext());
3367 CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(CallConv), 1);
3368 const Function *Func = DAG.getMachineFunction().getFunction();
3369 Function::const_arg_iterator FuncArg = Func->arg_begin();
3370
3371 if (Func->hasFnAttribute("interrupt") && !Func->arg_empty())
3372 report_fatal_error(
3373 "Functions with the interrupt attribute cannot have arguments!");
3374
3375 CCInfo.AnalyzeFormalArguments(Ins, CC_Mips_FixedArg);
3376 MipsFI->setFormalArgInfo(CCInfo.getNextStackOffset(),
3377 CCInfo.getInRegsParamsCount() > 0);
3378
3379 unsigned CurArgIdx = 0;
3380 CCInfo.rewindByValRegsInfo();
3381
3382 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3383 CCValAssign &VA = ArgLocs[i];
3384 if (Ins[i].isOrigArg()) {
3385 std::advance(FuncArg, Ins[i].getOrigArgIndex() - CurArgIdx);
3386 CurArgIdx = Ins[i].getOrigArgIndex();
3387 }
3388 EVT ValVT = VA.getValVT();
3389 ISD::ArgFlagsTy Flags = Ins[i].Flags;
3390 bool IsRegLoc = VA.isRegLoc();
3391
3392 if (Flags.isByVal()) {
3393 assert(Ins[i].isOrigArg() && "Byval arguments cannot be implicit")((Ins[i].isOrigArg() && "Byval arguments cannot be implicit"
) ? static_cast<void> (0) : __assert_fail ("Ins[i].isOrigArg() && \"Byval arguments cannot be implicit\""
, "/build/llvm-toolchain-snapshot-6.0~svn316068/lib/Target/Mips/MipsISelLowering.cpp"
, 3393, __PRETTY_FUNCTION__))
;
3394 unsigned FirstByValReg, LastByValReg;
3395 unsigned ByValIdx = CCInfo.getInRegsParamsProcessed();
3396 CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg);
3397
3398 assert(Flags.getByValSize() &&((Flags.getByValSize() && "ByVal args of size 0 should have been ignored by front-end."
) ? static_cast<void> (0) : __assert_fail ("Flags.getByValSize() && \"ByVal args of size 0 should have been ignored by front-end.\""
, "/build/llvm-toolchain-snapshot-6.0~svn316068/lib/Target/Mips/MipsISelLowering.cpp"
, 3399, __PRETTY_FUNCTION__))
3399 "ByVal args of size 0 should have been ignored by front-end.")((Flags.getByValSize() && "ByVal args of size 0 should have been ignored by front-end."
) ? static_cast<void> (0) : __assert_fail ("Flags.getByValSize() && \"ByVal args of size 0 should have been ignored by front-end.\""
, "/build/llvm-toolchain-snapshot-6.0~svn316068/lib/Target/Mips/MipsISelLowering.cpp"
, 3399, __PRETTY_FUNCTION__))
;
3400 assert(ByValIdx < CCInfo.getInRegsParamsCount())((ByValIdx < CCInfo.getInRegsParamsCount()) ? static_cast<
void> (0) : __assert_fail ("ByValIdx < CCInfo.getInRegsParamsCount()"
, "/build/llvm-toolchain-snapshot-6.0~svn316068/lib/Target/Mips/MipsISelLowering.cpp"
, 3400, __PRETTY_FUNCTION__))
;
3401 copyByValRegs(Chain, DL, OutChains, DAG, Flags, InVals, &*FuncArg,
3402 FirstByValReg, LastByValReg, VA, CCInfo);
3403 CCInfo.nextInRegsParam();
3404 continue;
3405 }
3406
3407 // Arguments stored on registers
3408 if (IsRegLoc) {
3409 MVT RegVT = VA.getLocVT();
3410 unsigned ArgReg = VA.getLocReg();
3411 const TargetRegisterClass *RC = getRegClassFor(RegVT);
3412
3413 // Transform the arguments stored on
3414 // physical registers into virtual ones
3415 unsigned Reg = addLiveIn(DAG.getMachineFunction(), ArgReg, RC);
3416 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT);
3417
3418 ArgValue = UnpackFromArgumentSlot(ArgValue, VA, Ins[i].ArgVT, DL, DAG);
3419
3420 // Handle floating point arguments passed in integer registers and
3421 // long double arguments passed in floating point registers.
3422 if ((RegVT == MVT::i32 && ValVT == MVT::f32) ||
3423 (RegVT == MVT::i64 && ValVT == MVT::f64) ||
3424 (RegVT == MVT::f64 && ValVT == MVT::i64))
3425 ArgValue = DAG.getNode(ISD::BITCAST, DL, ValVT, ArgValue);
3426 else if (ABI.IsO32() && RegVT == MVT::i32 &&
3427 ValVT == MVT::f64) {
3428 unsigned Reg2 = addLiveIn(DAG.getMachineFunction(),
3429 getNextIntArgReg(ArgReg), RC);
3430 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, DL, Reg2, RegVT);
3431 if (!Subtarget.isLittle())
3432 std::swap(ArgValue, ArgValue2);
3433 ArgValue = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64,
3434 ArgValue, ArgValue2);
3435 }
3436
3437 InVals.push_back(ArgValue);
3438 } else { // VA.isRegLoc()
3439 MVT LocVT = VA.getLocVT();
3440
3441 if (ABI.IsO32()) {
3442 // We ought to be able to use LocVT directly but O32 sets it to i32
3443 // when allocating floating point values to integer registers.
3444 // This shouldn't influence how we load the value into registers unless
3445 // we are targeting softfloat.
3446 if (VA.getValVT().isFloatingPoint() && !Subtarget.useSoftFloat())
3447 LocVT = VA.getValVT();
3448 }
3449
3450 // sanity check
3451 assert(VA.isMemLoc())((VA.isMemLoc()) ? static_cast<void> (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-6.0~svn316068/lib/Target/Mips/MipsISelLowering.cpp"
, 3451, __PRETTY_FUNCTION__))
;
3452
3453 // The stack pointer offset is relative to the caller stack frame.
3454 int FI = MFI.CreateFixedObject(LocVT.getSizeInBits() / 8,
3455 VA.getLocMemOffset(), true);
3456
3457 // Create load nodes to retrieve arguments from the stack
3458 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
3459 SDValue ArgValue = DAG.getLoad(
3460 LocVT, DL, Chain, FIN,
3461 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI));
3462 OutChains.push_back(ArgValue.getValue(1));
3463
3464 ArgValue = UnpackFromArgumentSlot(ArgValue, VA, Ins[i].ArgVT, DL, DAG);
3465
3466 InVals.push_back(ArgValue);
3467 }
3468 }
3469
3470 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3471 // The mips ABIs for returning structs by value requires that we copy
3472 // the sret argument into $v0 for the return. Save the argument into
3473 // a virtual register so that we can access it from the return points.
3474 if (Ins[i].Flags.isSRet()) {
3475 unsigned Reg = MipsFI->getSRetReturnReg();
3476 if (!Reg) {
3477 Reg = MF.getRegInfo().createVirtualRegister(
3478 getRegClassFor(ABI.IsN64() ? MVT::i64 : MVT::i32));
3479 MipsFI->setSRetReturnReg(Reg);
3480 }
3481 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), DL, Reg, InVals[i]);
3482 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Copy, Chain);
3483 break;
3484 }
3485 }
3486
3487 if (IsVarArg)
3488 writeVarArgRegs(OutChains, Chain, DL, DAG, CCInfo);
3489
3490 // All stores are grouped in one node to allow the matching between
3491 // the size of Ins and InVals. This only happens when on varg functions
3492 if (!OutChains.empty()) {
3493 OutChains.push_back(Chain);
3494 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains);
3495 }
3496
3497 return Chain;
3498}
3499
3500//===----------------------------------------------------------------------===//
3501// Return Value Calling Convention Implementation
3502//===----------------------------------------------------------------------===//
3503
3504bool
3505MipsTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
3506 MachineFunction &MF, bool IsVarArg,
3507 const SmallVectorImpl<ISD::OutputArg> &Outs,
3508 LLVMContext &Context) const {
3509 SmallVector<CCValAssign, 16> RVLocs;
3510 MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
3511 return CCInfo.CheckReturn(Outs, RetCC_Mips);
3512}
3513
3514bool
3515MipsTargetLowering::shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const {
3516 if (Subtarget.hasMips3() && Subtarget.useSoftFloat()) {
3517 if (Type == MVT::i32)
3518 return true;
3519 }
3520 return IsSigned;
3521}
3522
3523SDValue
3524MipsTargetLowering::LowerInterruptReturn(SmallVectorImpl<SDValue> &RetOps,
3525 const SDLoc &DL,
3526 SelectionDAG &DAG) const {
3527 MachineFunction &MF = DAG.getMachineFunction();
3528 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
3529
3530 MipsFI->setISR();
3531
3532 return DAG.getNode(MipsISD::ERet, DL, MVT::Other, RetOps);
3533}
3534
3535SDValue
3536MipsTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
3537 bool IsVarArg,
3538 const SmallVectorImpl<ISD::OutputArg> &Outs,
3539 const SmallVectorImpl<SDValue> &OutVals,
3540 const SDLoc &DL, SelectionDAG &DAG) const {
3541 // CCValAssign - represent the assignment of
3542 // the return value to a location
3543 SmallVector<CCValAssign, 16> RVLocs;
3544 MachineFunction &MF = DAG.getMachineFunction();
3545
3546 // CCState - Info about the registers and stack slot.
3547 MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext());
3548
3549 // Analyze return values.
3550 CCInfo.AnalyzeReturn(Outs, RetCC_Mips);
3551
3552 SDValue Flag;
3553 SmallVector<SDValue, 4> RetOps(1, Chain);
3554
3555 // Copy the result values into the output registers.
3556 for (unsigned i = 0; i != RVLocs.size(); ++i) {
3557 SDValue Val = OutVals[i];
3558 CCValAssign &VA = RVLocs[i];
3559 assert(VA.isRegLoc() && "Can only return in registers!")((VA.isRegLoc() && "Can only return in registers!") ?
static_cast<void> (0) : __assert_fail ("VA.isRegLoc() && \"Can only return in registers!\""
, "/build/llvm-toolchain-snapshot-6.0~svn316068/lib/Target/Mips/MipsISelLowering.cpp"
, 3559, __PRETTY_FUNCTION__))
;
3560 bool UseUpperBits = false;
3561
3562 switch (VA.getLocInfo()) {
3563 default:
3564 llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-6.0~svn316068/lib/Target/Mips/MipsISelLowering.cpp"
, 3564)
;
3565 case CCValAssign::Full:
3566 break;
3567 case CCValAssign::BCvt:
3568 Val = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Val);
3569 break;
3570 case CCValAssign::AExtUpper:
3571 UseUpperBits = true;
3572 LLVM_FALLTHROUGH[[clang::fallthrough]];
3573 case CCValAssign::AExt:
3574 Val = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Val);
3575 break;
3576 case CCValAssign::ZExtUpper:
3577 UseUpperBits = true;
3578 LLVM_FALLTHROUGH[[clang::fallthrough]];
3579 case CCValAssign::ZExt:
3580 Val = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Val);
3581 break;
3582 case CCValAssign::SExtUpper:
3583 UseUpperBits = true;
3584 LLVM_FALLTHROUGH[[clang::fallthrough]];
3585 case CCValAssign::SExt:
3586 Val = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Val);
3587 break;
3588 }
3589
3590 if (UseUpperBits) {
3591 unsigned ValSizeInBits = Outs[i].ArgVT.getSizeInBits();
3592 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
3593 Val = DAG.getNode(
3594 ISD::SHL, DL, VA.getLocVT(), Val,
3595 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT()));
3596 }
3597
3598 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Flag);
3599
3600 // Guarantee that all emitted copies are stuck together with flags.
3601 Flag = Chain.getValue(1);
3602 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
3603 }
3604
3605 // The mips ABIs for returning structs by value requires that we copy
3606 // the sret argument into $v0 for the return. We saved the argument into
3607 // a virtual register in the entry block, so now we copy the value out
3608 // and into $v0.
3609 if (MF.getFunction()->hasStructRetAttr()) {
3610 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
3611 unsigned Reg = MipsFI->getSRetReturnReg();
3612
3613 if (!Reg)
3614 llvm_unreachable("sret virtual register not created in the entry block")::llvm::llvm_unreachable_internal("sret virtual register not created in the entry block"
, "/build/llvm-toolchain-snapshot-6.0~svn316068/lib/Target/Mips/MipsISelLowering.cpp"
, 3614)
;
3615 SDValue Val =
3616 DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(DAG.getDataLayout()));
3617 unsigned V0 = ABI.IsN64() ? Mips::V0_64 : Mips::V0;
3618
3619 Chain = DAG.getCopyToReg(Chain, DL, V0, Val, Flag);
3620 Flag = Chain.getValue(1);
3621 RetOps.push_back(DAG.getRegister(V0, getPointerTy(DAG.getDataLayout())));
3622 }
3623
3624 RetOps[0] = Chain; // Update chain.
3625
3626 // Add the flag if we have it.
3627 if (Flag.getNode())
3628 RetOps.push_back(Flag);
3629
3630 // ISRs must use "eret".
3631 if (DAG.getMachineFunction().getFunction()->hasFnAttribute("interrupt"))
3632 return LowerInterruptReturn(RetOps, DL, DAG);
3633
3634 // Standard return on Mips is a "jr $ra"
3635 return DAG.getNode(MipsISD::Ret, DL, MVT::Other, RetOps);
3636}
3637
3638//===----------------------------------------------------------------------===//
3639// Mips Inline Assembly Support
3640//===----------------------------------------------------------------------===//
3641
3642/// getConstraintType - Given a constraint letter, return the type of
3643/// constraint it is for this target.
3644MipsTargetLowering::ConstraintType
3645MipsTargetLowering::getConstraintType(StringRef Constraint) const {
3646 // Mips specific constraints
3647 // GCC config/mips/constraints.md
3648 //
3649 // 'd' : An address register. Equivalent to r
3650 // unless generating MIPS16 code.
3651 // 'y' : Equivalent to r; retained for
3652 // backwards compatibility.
3653 // 'c' : A register suitable for use in an indirect
3654 // jump. This will always be $25 for -mabicalls.
3655 // 'l' : The lo register. 1 word storage.
3656 // 'x' : The hilo register pair. Double word storage.
3657 if (Constraint.size() == 1) {
3658 switch (Constraint[0]) {
3659 default : break;
3660 case 'd':
3661 case 'y':
3662 case 'f':
3663 case 'c':
3664 case 'l':
3665 case 'x':
3666 return C_RegisterClass;
3667 case 'R':
3668 return C_Memory;
3669 }
3670 }
3671
3672 if (Constraint == "ZC")
3673 return C_Memory;
3674
3675 return TargetLowering::getConstraintType(Constraint);
3676}
3677
3678/// Examine constraint type and operand type and determine a weight value.
3679/// This object must already have been set up with the operand type
3680/// and the current alternative constraint selected.
3681TargetLowering::ConstraintWeight
3682MipsTargetLowering::getSingleConstraintMatchWeight(
3683 AsmOperandInfo &info, const char *constraint) const {
3684 ConstraintWeight weight = CW_Invalid;
3685 Value *CallOperandVal = info.CallOperandVal;
3686 // If we don't have a value, we can't do a match,
3687 // but allow it at the lowest weight.
3688 if (!CallOperandVal)
3689 return CW_Default;
3690 Type *type = CallOperandVal->getType();
3691 // Look at the constraint type.
3692 switch (*constraint) {
3693 default:
3694 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
3695 break;
3696 case 'd':
3697 case 'y':
3698 if (type->isIntegerTy())
3699 weight = CW_Register;
3700 break;
3701 case 'f': // FPU or MSA register
3702 if (Subtarget.hasMSA() && type->isVectorTy() &&
3703 cast<VectorType>(type)->getBitWidth() == 128)
3704 weight = CW_Register;
3705 else if (type->isFloatTy())
3706 weight = CW_Register;
3707 break;
3708 case 'c': // $25 for indirect jumps
3709 case 'l': // lo register
3710 case 'x': // hilo register pair
3711 if (type->isIntegerTy())
3712 weight = CW_SpecificReg;
3713 break;
3714 case 'I': // signed 16 bit immediate
3715 case 'J': // integer zero
3716 case 'K': // unsigned 16 bit immediate
3717 case 'L': // signed 32 bit immediate where lower 16 bits are 0
3718 case 'N': // immediate in the range of -65535 to -1 (inclusive)
3719 case 'O': // signed 15 bit immediate (+- 16383)
3720 case 'P': // immediate in the range of 65535 to 1 (inclusive)
3721 if (isa<ConstantInt>(CallOperandVal))
3722 weight = CW_Constant;
3723 break;
3724 case 'R':
3725 weight = CW_Memory;
3726 break;
3727 }
3728 return weight;
3729}
3730
3731/// This is a helper function to parse a physical register string and split it
3732/// into non-numeric and numeric parts (Prefix and Reg). The first boolean flag
3733/// that is returned indicates whether parsing was successful. The second flag
3734/// is true if the numeric part exists.
3735static std::pair<bool, bool> parsePhysicalReg(StringRef C, StringRef &Prefix,
3736 unsigned long long &Reg) {
3737 if (C.front() != '{' || C.back() != '}')
3738 return std::make_pair(false, false);
3739
3740 // Search for the first numeric character.
3741 StringRef::const_iterator I, B = C.begin() + 1, E = C.end() - 1;
3742 I = std::find_if(B, E, isdigit);
3743
3744 Prefix = StringRef(B, I - B);
3745
3746 // The second flag is set to false if no numeric characters were found.
3747 if (I == E)
3748 return std::make_pair(true, false);
3749
3750 // Parse the numeric characters.
3751 return std::make_pair(!getAsUnsignedInteger(StringRef(I, E - I), 10, Reg),
3752 true);
3753}
3754
3755std::pair<unsigned, const TargetRegisterClass *> MipsTargetLowering::
3756parseRegForInlineAsmConstraint(StringRef C, MVT VT) const {
3757 const TargetRegisterInfo *TRI =
3758 Subtarget.getRegisterInfo();
3759 const TargetRegisterClass *RC;
3760 StringRef Prefix;
3761 unsigned long long Reg;
3762
3763 std::pair<bool, bool> R = parsePhysicalReg(C, Prefix, Reg);
3764
3765 if (!R.first)
3766 return std::make_pair(0U, nullptr);
3767
3768 if ((Prefix == "hi" || Prefix == "lo")) { // Parse hi/lo.
3769 // No numeric characters follow "hi" or "lo".
3770 if (R.second)
3771 return std::make_pair(0U, nullptr);
3772
3773 RC = TRI->getRegClass(Prefix == "hi" ?
3774 Mips::HI32RegClassID : Mips::LO32RegClassID);
3775 return std::make_pair(*(RC->begin()), RC);
3776 } else if (Prefix.startswith("$msa")) {
3777 // Parse $msa(ir|csr|access|save|modify|request|map|unmap)
3778
3779 // No numeric characters follow the name.
3780 if (R.second)
3781 return std::make_pair(0U, nullptr);
3782
3783 Reg = StringSwitch<unsigned long long>(Prefix)
3784 .Case("$msair", Mips::MSAIR)
3785 .Case("$msacsr", Mips::MSACSR)
3786 .Case("$msaaccess", Mips::MSAAccess)
3787 .Case("$msasave", Mips::MSASave)
3788 .Case("$msamodify", Mips::MSAModify)
3789 .Case("$msarequest", Mips::MSARequest)
3790 .Case("$msamap", Mips::MSAMap)
3791 .Case("$msaunmap", Mips::MSAUnmap)
3792 .Default(0);
3793
3794 if (!Reg)
3795 return std::make_pair(0U, nullptr);
3796
3797 RC = TRI->getRegClass(Mips::MSACtrlRegClassID);
3798 return std::make_pair(Reg, RC);
3799 }
3800
3801 if (!R.second)
3802 return std::make_pair(0U, nullptr);
3803
3804 if (Prefix == "$f") { // Parse $f0-$f31.
3805 // If the size of FP registers is 64-bit or Reg is an even number, select
3806 // the 64-bit register class. Otherwise, select the 32-bit register class.
3807 if (VT == MVT::Other)
3808 VT = (Subtarget.isFP64bit() || !(Reg % 2)) ? MVT::f64 : MVT::f32;
3809
3810 RC = getRegClassFor(VT);
3811
3812 if (RC == &Mips::AFGR64RegClass) {
3813 assert(Reg % 2 == 0)((Reg % 2 == 0) ? static_cast<void> (0) : __assert_fail
("Reg % 2 == 0", "/build/llvm-toolchain-snapshot-6.0~svn316068/lib/Target/Mips/MipsISelLowering.cpp"
, 3813, __PRETTY_FUNCTION__))
;
3814 Reg >>= 1;
3815 }
3816 } else if (Prefix == "$fcc") // Parse $fcc0-$fcc7.
3817 RC = TRI->getRegClass(Mips::FCCRegClassID);
3818 else if (Prefix == "$w") { // Parse $w0-$w31.
3819 RC = getRegClassFor((VT == MVT::Other) ? MVT::v16i8 : VT);
3820 } else { // Parse $0-$31.
3821 assert(Prefix == "$")((Prefix == "$") ? static_cast<void> (0) : __assert_fail
("Prefix == \"$\"", "/build/llvm-toolchain-snapshot-6.0~svn316068/lib/Target/Mips/MipsISelLowering.cpp"
, 3821, __PRETTY_FUNCTION__))
;
3822 RC = getRegClassFor((VT == MVT::Other) ? MVT::i32 : VT);
3823 }
3824
3825 assert(Reg < RC->getNumRegs())((Reg < RC->getNumRegs()) ? static_cast<void> (0)
: __assert_fail ("Reg < RC->getNumRegs()", "/build/llvm-toolchain-snapshot-6.0~svn316068/lib/Target/Mips/MipsISelLowering.cpp"
, 3825, __PRETTY_FUNCTION__))
;
3826 return std::make_pair(*(RC->begin() + Reg), RC);
3827}
3828
3829/// Given a register class constraint, like 'r', if this corresponds directly
3830/// to an LLVM register class, return a register of 0 and the register class
3831/// pointer.
3832std::pair<unsigned, const TargetRegisterClass *>
3833MipsTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
3834 StringRef Constraint,
3835 MVT VT) const {
3836 if (Constraint.size() == 1) {
3837 switch (Constraint[0]) {
3838 case 'd': // Address register. Same as 'r' unless generating MIPS16 code.
3839 case 'y': // Same as 'r'. Exists for compatibility.
3840 case 'r':
3841 if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) {
3842 if (Subtarget.inMips16Mode())
3843 return std::make_pair(0U, &Mips::CPU16RegsRegClass);
3844 return std::make_pair(0U, &Mips::GPR32RegClass);
3845 }
3846 if (VT == MVT::i64 && !Subtarget.isGP64bit())
3847 return std::make_pair(0U, &Mips::GPR32RegClass);
3848 if (VT == MVT::i64 && Subtarget.isGP64bit())
3849 return std::make_pair(0U, &Mips::GPR64RegClass);
3850 // This will generate an error message
3851 return std::make_pair(0U, nullptr);
3852 case 'f': // FPU or MSA register
3853 if (VT == MVT::v16i8)
3854 return std::make_pair(0U, &Mips::MSA128BRegClass);
3855 else if (VT == MVT::v8i16 || VT == MVT::v8f16)
3856 return std::make_pair(0U, &Mips::MSA128HRegClass);
3857 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
3858 return std::make_pair(0U, &Mips::MSA128WRegClass);
3859 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
3860 return std::make_pair(0U, &Mips::MSA128DRegClass);
3861 else if (VT == MVT::f32)
3862 return std::make_pair(0U, &Mips::FGR32RegClass);
3863 else if ((VT == MVT::f64) && (!Subtarget.isSingleFloat())) {
3864 if (Subtarget.isFP64bit())
3865 return std::make_pair(0U, &Mips::FGR64RegClass);
3866 return std::make_pair(0U, &Mips::AFGR64RegClass);
3867 }
3868 break;
3869 case 'c': // register suitable for indirect jump
3870 if (VT == MVT::i32)
3871 return std::make_pair((unsigned)Mips::T9, &Mips::GPR32RegClass);
3872 assert(VT == MVT::i64 && "Unexpected type.")((VT == MVT::i64 && "Unexpected type.") ? static_cast
<void> (0) : __assert_fail ("VT == MVT::i64 && \"Unexpected type.\""
, "/build/llvm-toolchain-snapshot-6.0~svn316068/lib/Target/Mips/MipsISelLowering.cpp"
, 3872, __PRETTY_FUNCTION__))
;
3873 return std::make_pair((unsigned)Mips::T9_64, &Mips::GPR64RegClass);
3874 case 'l': // register suitable for indirect jump
3875 if (VT == MVT::i32)
3876 return std::make_pair((unsigned)Mips::LO0, &Mips::LO32RegClass);
3877 return std::make_pair((unsigned)Mips::LO0_64, &Mips::LO64RegClass);
3878 case 'x': // register suitable for indirect jump
3879 // Fixme: Not triggering the use of both hi and low
3880 // This will generate an error message
3881 return std::make_pair(0U, nullptr);
3882 }
3883 }
3884
3885 std::pair<unsigned, const TargetRegisterClass *> R;
3886 R = parseRegForInlineAsmConstraint(Constraint, VT);
3887
3888 if (R.second)
3889 return R;
3890
3891 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
3892}
3893
3894/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
3895/// vector. If it is invalid, don't add anything to Ops.
3896void MipsTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
3897 std::string &Constraint,
3898 std::vector<SDValue>&Ops,
3899 SelectionDAG &DAG) const {
3900 SDLoc DL(Op);
3901 SDValue Result;
3902
3903 // Only support length 1 constraints for now.
3904 if (Constraint.length() > 1) return;
3905
3906 char ConstraintLetter = Constraint[0];
3907 switch (ConstraintLetter) {
3908 default: break; // This will fall through to the generic implementation
3909 case 'I': // Signed 16 bit constant
3910 // If this fails, the parent routine will give an error
3911 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3912 EVT Type = Op.getValueType();
3913 int64_t Val = C->getSExtValue();
3914 if (isInt<16>(Val)) {
3915 Result = DAG.getTargetConstant(Val, DL, Type);
3916 break;
3917 }
3918 }
3919 return;
3920 case 'J': // integer zero
3921 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3922 EVT Type = Op.getValueType();
3923 int64_t Val = C->getZExtValue();
3924 if (Val == 0) {
3925 Result = DAG.getTargetConstant(0, DL, Type);
3926 break;
3927 }
3928 }
3929 return;
3930 case 'K': // unsigned 16 bit immediate
3931 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3932 EVT Type = Op.getValueType();
3933 uint64_t Val = (uint64_t)C->getZExtValue();
3934 if (isUInt<16>(Val)) {
3935 Result = DAG.getTargetConstant(Val, DL, Type);
3936 break;
3937 }
3938 }
3939 return;
3940 case 'L': // signed 32 bit immediate where lower 16 bits are 0
3941 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3942 EVT Type = Op.getValueType();
3943 int64_t Val = C->getSExtValue();
3944 if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)){
3945 Result = DAG.getTargetConstant(Val, DL, Type);
3946 break;
3947 }
3948 }
3949 return;
3950 case 'N': // immediate in the range of -65535 to -1 (inclusive)
3951 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3952 EVT Type = Op.getValueType();
3953 int64_t Val = C->getSExtValue();
3954 if ((Val >= -65535) && (Val <= -1)) {
3955 Result = DAG.getTargetConstant(Val, DL, Type);
3956 break;
3957 }
3958 }
3959 return;
3960 case 'O': // signed 15 bit immediate
3961 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3962 EVT Type = Op.getValueType();
3963 int64_t Val = C->getSExtValue();
3964 if ((isInt<15>(Val))) {
3965 Result = DAG.getTargetConstant(Val, DL, Type);
3966 break;
3967 }
3968 }
3969 return;
3970 case 'P': // immediate in the range of 1 to 65535 (inclusive)
3971 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3972 EVT Type = Op.getValueType();
3973 int64_t Val = C->getSExtValue();
3974 if ((Val <= 65535) && (Val >= 1)) {
3975 Result = DAG.getTargetConstant(Val, DL, Type);
3976 break;
3977 }
3978 }
3979 return;
3980 }
3981
3982 if (Result.getNode()) {
3983 Ops.push_back(Result);
3984 return;
3985 }
3986
3987 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
3988}
3989
3990bool MipsTargetLowering::isLegalAddressingMode(const DataLayout &DL,
3991 const AddrMode &AM, Type *Ty,
3992 unsigned AS, Instruction *I) const {
3993 // No global is ever allowed as a base.
3994 if (AM.BaseGV)
3995 return false;
3996
3997 switch (AM.Scale) {
3998 case 0: // "r+i" or just "i", depending on HasBaseReg.
3999 break;
4000 case 1:
4001 if (!AM.HasBaseReg) // allow "r+i".
4002 break;
4003 return false; // disallow "r+r" or "r+r+i".
4004 default:
4005 return false;
4006 }
4007
4008 return true;
4009}
4010
4011bool
4012MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
4013 // The Mips target isn't yet aware of offsets.
4014 return false;
4015}
4016
4017EVT MipsTargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
4018 unsigned SrcAlign,
4019 bool IsMemset, bool ZeroMemset,
4020 bool MemcpyStrSrc,
4021 MachineFunction &MF) const {
4022 if (Subtarget.hasMips64())
4023 return MVT::i64;
4024
4025 return MVT::i32;
4026}
4027
4028bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
4029 if (VT != MVT::f32 && VT != MVT::f64)
4030 return false;
4031 if (Imm.isNegZero())
4032 return false;
4033 return Imm.isZero();
4034}
4035
4036unsigned MipsTargetLowering::getJumpTableEncoding() const {
4037
4038 // FIXME: For space reasons this should be: EK_GPRel32BlockAddress.
4039 if (ABI.IsN64() && isPositionIndependent())
4040 return MachineJumpTableInfo::EK_GPRel64BlockAddress;
4041
4042 return TargetLowering::getJumpTableEncoding();
4043}
4044
4045bool MipsTargetLowering::useSoftFloat() const {
4046 return Subtarget.useSoftFloat();
4047}
4048
4049void MipsTargetLowering::copyByValRegs(
4050 SDValue Chain, const SDLoc &DL, std::vector<SDValue> &OutChains,
4051 SelectionDAG &DAG, const ISD::ArgFlagsTy &Flags,
4052 SmallVectorImpl<SDValue> &InVals, const Argument *FuncArg,
4053 unsigned FirstReg, unsigned LastReg, const CCValAssign &VA,
4054 MipsCCState &State) const {
4055 MachineFunction &MF = DAG.getMachineFunction();
4056 MachineFrameInfo &MFI = MF.getFrameInfo();
4057 unsigned GPRSizeInBytes = Subtarget.getGPRSizeInBytes();
4058 unsigned NumRegs = LastReg - FirstReg;
4059 unsigned RegAreaSize = NumRegs * GPRSizeInBytes;
4060 unsigned FrameObjSize = std::max(Flags.getByValSize(), RegAreaSize);
4061 int FrameObjOffset;
4062 ArrayRef<MCPhysReg> ByValArgRegs = ABI.GetByValArgRegs();
4063
4064 if (RegAreaSize)
4065 FrameObjOffset =
4066 (int)ABI.GetCalleeAllocdArgSizeInBytes(State.getCallingConv()) -
4067 (int)((ByValArgRegs.size() - FirstReg) * GPRSizeInBytes);
4068 else
4069 FrameObjOffset = VA.getLocMemOffset();
4070
4071 // Create frame object.
4072 EVT PtrTy = getPointerTy(DAG.getDataLayout());
4073 int FI = MFI.CreateFixedObject(FrameObjSize, FrameObjOffset, true);
4074 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
4075 InVals.push_back(FIN);
4076
4077 if (!NumRegs)
4078 return;
4079
4080 // Copy arg registers.
4081 MVT RegTy = MVT::getIntegerVT(GPRSizeInBytes * 8);
4082 const TargetRegisterClass *RC = getRegClassFor(RegTy);
4083
4084 for (unsigned I = 0; I < NumRegs; ++I) {
4085 unsigned ArgReg = ByValArgRegs[FirstReg + I];
4086 unsigned VReg = addLiveIn(MF, ArgReg, RC);
4087 unsigned Offset = I * GPRSizeInBytes;
4088 SDValue StorePtr = DAG.getNode(ISD::ADD, DL, PtrTy, FIN,
4089 DAG.getConstant(Offset, DL, PtrTy));
4090 SDValue Store = DAG.getStore(Chain, DL, DAG.getRegister(VReg, RegTy),
4091 StorePtr, MachinePointerInfo(FuncArg, Offset));
4092 OutChains.push_back(Store);
4093 }
4094}
4095
4096// Copy byVal arg to registers and stack.
4097SDValue MipsTargetLowering::passByValArg(
4098 SDValue Chain, const SDLoc &DL,
4099 std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
4100 SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr,
4101 MachineFrameInfo &MFI, SelectionDAG &DAG, SDValue Arg, unsigned FirstReg,
4102 unsigned LastReg, const ISD::ArgFlagsTy &Flags, bool isLittle,
4103 const CCValAssign &VA) const {
4104 unsigned ByValSizeInBytes = Flags.getByValSize();
4105 unsigned OffsetInBytes = 0; // From beginning of struct
4106 unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes();
4107 unsigned Alignment = std::min(Flags.getByValAlign(), RegSizeInBytes);
4108 EVT PtrTy = getPointerTy(DAG.getDataLayout()),
4109 RegTy = MVT::getIntegerVT(RegSizeInBytes * 8);
4110 unsigned NumRegs = LastReg - FirstReg;
4111
4112 if (NumRegs) {
4113 ArrayRef<MCPhysReg> ArgRegs = ABI.GetByValArgRegs();
4114 bool LeftoverBytes = (NumRegs * RegSizeInBytes > ByValSizeInBytes);
4115 unsigned I = 0;
4116
4117 // Copy words to registers.
4118 for (; I < NumRegs - LeftoverBytes; ++I, OffsetInBytes += RegSizeInBytes) {
4119 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
4120 DAG.getConstant(OffsetInBytes, DL, PtrTy));
4121 SDValue LoadVal = DAG.getLoad(RegTy, DL, Chain, LoadPtr,
4122 MachinePointerInfo(), Alignment);
4123 MemOpChains.push_back(LoadVal.getValue(1));
4124 unsigned ArgReg = ArgRegs[FirstReg + I];
4125 RegsToPass.push_back(std::make_pair(ArgReg, LoadVal));
4126 }
4127
4128 // Return if the struct has been fully copied.
4129 if (ByValSizeInBytes == OffsetInBytes)
4130 return Chain;
4131
4132 // Copy the remainder of the byval argument with sub-word loads and shifts.
4133 if (LeftoverBytes) {
4134 SDValue Val;
4135
4136 for (unsigned LoadSizeInBytes = RegSizeInBytes / 2, TotalBytesLoaded = 0;
4137 OffsetInBytes < ByValSizeInBytes; LoadSizeInBytes /= 2) {
4138 unsigned RemainingSizeInBytes = ByValSizeInBytes - OffsetInBytes;
4139
4140 if (RemainingSizeInBytes < LoadSizeInBytes)
4141 continue;
4142
4143 // Load subword.
4144 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
4145 DAG.getConstant(OffsetInBytes, DL,
4146 PtrTy));
4147 SDValue LoadVal = DAG.getExtLoad(
4148 ISD::ZEXTLOAD, DL, RegTy, Chain, LoadPtr, MachinePointerInfo(),
4149 MVT::getIntegerVT(LoadSizeInBytes * 8), Alignment);
4150 MemOpChains.push_back(LoadVal.getValue(1));
4151
4152 // Shift the loaded value.
4153 unsigned Shamt;
4154
4155 if (isLittle)
4156 Shamt = TotalBytesLoaded * 8;
4157 else
4158 Shamt = (RegSizeInBytes - (TotalBytesLoaded + LoadSizeInBytes)) * 8;
4159
4160 SDValue Shift = DAG.getNode(ISD::SHL, DL, RegTy, LoadVal,
4161 DAG.getConstant(Shamt, DL, MVT::i32));
4162
4163 if (Val.getNode())
4164 Val = DAG.getNode(ISD::OR, DL, RegTy, Val, Shift);
4165 else
4166 Val = Shift;
4167
4168 OffsetInBytes += LoadSizeInBytes;
4169 TotalBytesLoaded += LoadSizeInBytes;
4170 Alignment = std::min(Alignment, LoadSizeInBytes);
4171 }
4172
4173 unsigned ArgReg = ArgRegs[FirstReg + I];
4174 RegsToPass.push_back(std::make_pair(ArgReg, Val));
4175 return Chain;
4176 }
4177 }
4178
4179 // Copy remainder of byval arg to it with memcpy.
4180 unsigned MemCpySize = ByValSizeInBytes - OffsetInBytes;
4181 SDValue Src = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
4182 DAG.getConstant(OffsetInBytes, DL, PtrTy));
4183 SDValue Dst = DAG.getNode(ISD::ADD, DL, PtrTy, StackPtr,
4184 DAG.getIntPtrConstant(VA.getLocMemOffset(), DL));
4185 Chain = DAG.getMemcpy(
4186 Chain, DL, Dst, Src, DAG.getConstant(MemCpySize, DL, PtrTy), Alignment,
4187 /*isVolatile=*/false, /*AlwaysInline=*/false,
4188 /*isTailCall=*/false, MachinePointerInfo(), MachinePointerInfo());
4189 MemOpChains.push_back(Chain);
4190
4191 return Chain;
4192}
4193
4194void MipsTargetLowering::writeVarArgRegs(std::vector<SDValue> &OutChains,
4195 SDValue Chain, const SDLoc &DL,
4196 SelectionDAG &DAG,
4197 CCState &State) const {
4198 ArrayRef<MCPhysReg> ArgRegs = ABI.GetVarArgRegs();
4199 unsigned Idx = State.getFirstUnallocated(ArgRegs);
4200 unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes();
4201 MVT RegTy = MVT::getIntegerVT(RegSizeInBytes * 8);
4202 const TargetRegisterClass *RC = getRegClassFor(RegTy);
4203 MachineFunction &MF = DAG.getMachineFunction();
4204 MachineFrameInfo &MFI = MF.getFrameInfo();
4205 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
4206
4207 // Offset of the first variable argument from stack pointer.
4208 int VaArgOffset;
4209
4210 if (ArgRegs.size() == Idx)
4211 VaArgOffset = alignTo(State.getNextStackOffset(), RegSizeInBytes);
4212 else {
4213 VaArgOffset =
4214 (int)ABI.GetCalleeAllocdArgSizeInBytes(State.getCallingConv()) -
4215 (int)(RegSizeInBytes * (ArgRegs.size() - Idx));
4216 }
4217
4218 // Record the frame index of the first variable argument
4219 // which is a value necessary to VASTART.
4220 int FI = MFI.CreateFixedObject(RegSizeInBytes, VaArgOffset, true);
4221 MipsFI->setVarArgsFrameIndex(FI);
4222
4223 // Copy the integer registers that have not been used for argument passing
4224 // to the argument register save area. For O32, the save area is allocated
4225 // in the caller's stack frame, while for N32/64, it is allocated in the
4226 // callee's stack frame.
4227 for (unsigned I = Idx; I < ArgRegs.size();
4228 ++I, VaArgOffset += RegSizeInBytes) {
4229 unsigned Reg = addLiveIn(MF, ArgRegs[I], RC);
4230 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegTy);
4231 FI = MFI.CreateFixedObject(RegSizeInBytes, VaArgOffset, true);
4232 SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
4233 SDValue Store =
4234 DAG.getStore(Chain, DL, ArgValue, PtrOff, MachinePointerInfo());
4235 cast<StoreSDNode>(Store.getNode())->getMemOperand()->setValue(
4236 (Value *)nullptr);
4237 OutChains.push_back(Store);
4238 }
4239}
4240
4241void MipsTargetLowering::HandleByVal(CCState *State, unsigned &Size,
4242 unsigned Align) const {
4243 const TargetFrameLowering *TFL = Subtarget.getFrameLowering();
4244
4245 assert(Size && "Byval argument's size shouldn't be 0.")((Size && "Byval argument's size shouldn't be 0.") ? static_cast
<void> (0) : __assert_fail ("Size && \"Byval argument's size shouldn't be 0.\""
, "/build/llvm-toolchain-snapshot-6.0~svn316068/lib/Target/Mips/MipsISelLowering.cpp"
, 4245, __PRETTY_FUNCTION__))
;
4246
4247 Align = std::min(Align, TFL->getStackAlignment());
4248
4249 unsigned FirstReg = 0;
4250 unsigned NumRegs = 0;
4251
4252 if (State->getCallingConv() != CallingConv::Fast) {
4253 unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes();
4254 ArrayRef<MCPhysReg> IntArgRegs = ABI.GetByValArgRegs();
4255 // FIXME: The O32 case actually describes no shadow registers.
4256 const MCPhysReg *ShadowRegs =
4257 ABI.IsO32() ? IntArgRegs.data() : Mips64DPRegs;
4258
4259 // We used to check the size as well but we can't do that anymore since
4260 // CCState::HandleByVal() rounds up the size after calling this function.
4261 assert(!(Align % RegSizeInBytes) &&((!(Align % RegSizeInBytes) && "Byval argument's alignment should be a multiple of"
"RegSizeInBytes.") ? static_cast<void> (0) : __assert_fail
("!(Align % RegSizeInBytes) && \"Byval argument's alignment should be a multiple of\" \"RegSizeInBytes.\""
, "/build/llvm-toolchain-snapshot-6.0~svn316068/lib/Target/Mips/MipsISelLowering.cpp"
, 4263, __PRETTY_FUNCTION__))
4262 "Byval argument's alignment should be a multiple of"((!(Align % RegSizeInBytes) && "Byval argument's alignment should be a multiple of"
"RegSizeInBytes.") ? static_cast<void> (0) : __assert_fail
("!(Align % RegSizeInBytes) && \"Byval argument's alignment should be a multiple of\" \"RegSizeInBytes.\""
, "/build/llvm-toolchain-snapshot-6.0~svn316068/lib/Target/Mips/MipsISelLowering.cpp"
, 4263, __PRETTY_FUNCTION__))
4263 "RegSizeInBytes.")((!(Align % RegSizeInBytes) && "Byval argument's alignment should be a multiple of"
"RegSizeInBytes.") ? static_cast<void> (0) : __assert_fail
("!(Align % RegSizeInBytes) && \"Byval argument's alignment should be a multiple of\" \"RegSizeInBytes.\""
, "/build/llvm-toolchain-snapshot-6.0~svn316068/lib/Target/Mips/MipsISelLowering.cpp"
, 4263, __PRETTY_FUNCTION__))
;
4264
4265 FirstReg = State->getFirstUnallocated(IntArgRegs);
4266
4267 // If Align > RegSizeInBytes, the first arg register must be even.
4268 // FIXME: This condition happens to do the right thing but it's not the
4269 // right way to test it. We want to check that the stack frame offset
4270 // of the register is aligned.
4271 if ((Align > RegSizeInBytes) && (FirstReg % 2)) {
4272 State->AllocateReg(IntArgRegs[FirstReg], ShadowRegs[FirstReg]);
4273 ++FirstReg;
4274 }
4275
4276 // Mark the registers allocated.
4277 Size = alignTo(Size, RegSizeInBytes);
4278 for (unsigned I = FirstReg; Size > 0 && (I < IntArgRegs.size());
4279 Size -= RegSizeInBytes, ++I, ++NumRegs)
4280 State->AllocateReg(IntArgRegs[I], ShadowRegs[I]);
4281 }
4282
4283 State->addInRegsParamInfo(FirstReg, FirstReg + NumRegs);
4284}
4285
4286MachineBasicBlock *MipsTargetLowering::emitPseudoSELECT(MachineInstr &MI,
4287 MachineBasicBlock *BB,
4288 bool isFPCmp,
4289 unsigned Opc) const {
4290 assert(!(Subtarget.hasMips4() || Subtarget.hasMips32()) &&((!(Subtarget.hasMips4() || Subtarget.hasMips32()) &&
"Subtarget already supports SELECT nodes with the use of" "conditional-move instructions."
) ? static_cast<void> (0) : __assert_fail ("!(Subtarget.hasMips4() || Subtarget.hasMips32()) && \"Subtarget already supports SELECT nodes with the use of\" \"conditional-move instructions.\""
, "/build/llvm-toolchain-snapshot-6.0~svn316068/lib/Target/Mips/MipsISelLowering.cpp"
, 4292, __PRETTY_FUNCTION__))
4291 "Subtarget already supports SELECT nodes with the use of"((!(Subtarget.hasMips4() || Subtarget.hasMips32()) &&
"Subtarget already supports SELECT nodes with the use of" "conditional-move instructions."
) ? static_cast<void> (0) : __assert_fail ("!(Subtarget.hasMips4() || Subtarget.hasMips32()) && \"Subtarget already supports SELECT nodes with the use of\" \"conditional-move instructions.\""
, "/build/llvm-toolchain-snapshot-6.0~svn316068/lib/Target/Mips/MipsISelLowering.cpp"
, 4292, __PRETTY_FUNCTION__))
4292 "conditional-move instructions.")((!(Subtarget.hasMips4() || Subtarget.hasMips32()) &&
"Subtarget already supports SELECT nodes with the use of" "conditional-move instructions."
) ? static_cast<void> (0) : __assert_fail ("!(Subtarget.hasMips4() || Subtarget.hasMips32()) && \"Subtarget already supports SELECT nodes with the use of\" \"conditional-move instructions.\""
, "/build/llvm-toolchain-snapshot-6.0~svn316068/lib/Target/Mips/MipsISelLowering.cpp"
, 4292, __PRETTY_FUNCTION__))
;
4293
4294 const TargetInstrInfo *TII =
4295 Subtarget.getInstrInfo();
4296 DebugLoc DL = MI.getDebugLoc();
4297
4298 // To "insert" a SELECT instruction, we actually have to insert the
4299 // diamond control-flow pattern. The incoming instruction knows the
4300 // destination vreg to set, the condition code register to branch on, the
4301 // true/false values to select between, and a branch opcode to use.
4302 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4303 MachineFunction::iterator It = ++BB->getIterator();
4304
4305 // thisMBB:
4306 // ...
4307 // TrueVal = ...
4308 // setcc r1, r2, r3
4309 // bNE r1, r0, copy1MBB
4310 // fallthrough --> copy0MBB
4311 MachineBasicBlock *thisMBB = BB;
4312 MachineFunction *F = BB->getParent();
4313 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
4314 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
4315 F->insert(It, copy0MBB);
4316 F->insert(It, sinkMBB);
4317
4318 // Transfer the remainder of BB and its successor edges to sinkMBB.
4319 sinkMBB->splice(sinkMBB->begin(), BB,
4320 std::next(MachineBasicBlock::iterator(MI)), BB->end());
4321 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
4322
4323 // Next, add the true and fallthrough blocks as its successors.
4324 BB->addSuccessor(copy0MBB);
4325 BB->addSuccessor(sinkMBB);
4326
4327 if (isFPCmp) {
4328 // bc1[tf] cc, sinkMBB
4329 BuildMI(BB, DL, TII->get(Opc))
4330 .addReg(MI.getOperand(1).getReg())
4331 .addMBB(sinkMBB);
4332 } else {
4333 // bne rs, $0, sinkMBB
4334 BuildMI(BB, DL, TII->get(Opc))
4335 .addReg(MI.getOperand(1).getReg())
4336 .addReg(Mips::ZERO)
4337 .addMBB(sinkMBB);
4338 }
4339
4340 // copy0MBB:
4341 // %FalseValue = ...
4342 // # fallthrough to sinkMBB
4343 BB = copy0MBB;
4344
4345 // Update machine-CFG edges
4346 BB->addSuccessor(sinkMBB);
4347
4348 // sinkMBB:
4349 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
4350 // ...
4351 BB = sinkMBB;
4352
4353 BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(0).getReg())
4354 .addReg(MI.getOperand(2).getReg())
4355 .addMBB(thisMBB)
4356 .addReg(MI.getOperand(3).getReg())
4357 .addMBB(copy0MBB);
4358
4359 MI.eraseFromParent(); // The pseudo instruction is gone now.
4360
4361 return BB;
4362}
4363
4364// FIXME? Maybe this could be a TableGen attribute on some registers and
4365// this table could be generated automatically from RegInfo.
4366unsigned MipsTargetLowering::getRegisterByName(const char* RegName, EVT VT,
4367 SelectionDAG &DAG) const {
4368 // Named registers is expected to be fairly rare. For now, just support $28
4369 // since the linux kernel uses it.
4370 if (Subtarget.isGP64bit()) {
4371 unsigned Reg = StringSwitch<unsigned>(RegName)
4372 .Case("$28", Mips::GP_64)
4373 .Default(0);
4374 if (Reg)
4375 return Reg;
4376 } else {
4377 unsigned Reg = StringSwitch<unsigned>(RegName)
4378 .Case("$28", Mips::GP)
4379 .Default(0);
4380 if (Reg)
4381 return Reg;
4382 }
4383 report_fatal_error("Invalid register name global variable");
4384}