Bug Summary

File:lib/Target/Mips/MipsISelLowering.cpp
Warning:line 1744, column 3
Value stored to 'BB' is never read

Annotated Source Code

1//===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that Mips uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14#include "MipsISelLowering.h"
15#include "InstPrinter/MipsInstPrinter.h"
16#include "MCTargetDesc/MipsBaseInfo.h"
17#include "MipsCCState.h"
18#include "MipsMachineFunction.h"
19#include "MipsSubtarget.h"
20#include "MipsTargetMachine.h"
21#include "MipsTargetObjectFile.h"
22#include "llvm/ADT/Statistic.h"
23#include "llvm/ADT/StringSwitch.h"
24#include "llvm/CodeGen/CallingConvLower.h"
25#include "llvm/CodeGen/MachineFrameInfo.h"
26#include "llvm/CodeGen/MachineFunction.h"
27#include "llvm/CodeGen/MachineInstrBuilder.h"
28#include "llvm/CodeGen/MachineJumpTableInfo.h"
29#include "llvm/CodeGen/MachineRegisterInfo.h"
30#include "llvm/CodeGen/FunctionLoweringInfo.h"
31#include "llvm/CodeGen/SelectionDAGISel.h"
32#include "llvm/CodeGen/ValueTypes.h"
33#include "llvm/IR/CallingConv.h"
34#include "llvm/IR/DerivedTypes.h"
35#include "llvm/IR/GlobalVariable.h"
36#include "llvm/Support/CommandLine.h"
37#include "llvm/Support/Debug.h"
38#include "llvm/Support/ErrorHandling.h"
39#include "llvm/Support/raw_ostream.h"
40#include <cctype>
41
42using namespace llvm;
43
44#define DEBUG_TYPE"mips-lower" "mips-lower"
45
46STATISTIC(NumTailCalls, "Number of tail calls")static llvm::Statistic NumTailCalls = {"mips-lower", "NumTailCalls"
, "Number of tail calls", {0}, false}
;
47
48static cl::opt<bool>
49LargeGOT("mxgot", cl::Hidden,
50 cl::desc("MIPS: Enable GOT larger than 64k."), cl::init(false));
51
52static cl::opt<bool>
53NoZeroDivCheck("mno-check-zero-division", cl::Hidden,
54 cl::desc("MIPS: Don't trap on integer division by zero."),
55 cl::init(false));
56
57static const MCPhysReg Mips64DPRegs[8] = {
58 Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64,
59 Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64
60};
61
62// If I is a shifted mask, set the size (Size) and the first bit of the
63// mask (Pos), and return true.
64// For example, if I is 0x003ff800, (Pos, Size) = (11, 11).
65static bool isShiftedMask(uint64_t I, uint64_t &Pos, uint64_t &Size) {
66 if (!isShiftedMask_64(I))
67 return false;
68
69 Size = countPopulation(I);
70 Pos = countTrailingZeros(I);
71 return true;
72}
73
74SDValue MipsTargetLowering::getGlobalReg(SelectionDAG &DAG, EVT Ty) const {
75 MipsFunctionInfo *FI = DAG.getMachineFunction().getInfo<MipsFunctionInfo>();
76 return DAG.getRegister(FI->getGlobalBaseReg(), Ty);
77}
78
79SDValue MipsTargetLowering::getTargetNode(GlobalAddressSDNode *N, EVT Ty,
80 SelectionDAG &DAG,
81 unsigned Flag) const {
82 return DAG.getTargetGlobalAddress(N->getGlobal(), SDLoc(N), Ty, 0, Flag);
83}
84
85SDValue MipsTargetLowering::getTargetNode(ExternalSymbolSDNode *N, EVT Ty,
86 SelectionDAG &DAG,
87 unsigned Flag) const {
88 return DAG.getTargetExternalSymbol(N->getSymbol(), Ty, Flag);
89}
90
91SDValue MipsTargetLowering::getTargetNode(BlockAddressSDNode *N, EVT Ty,
92 SelectionDAG &DAG,
93 unsigned Flag) const {
94 return DAG.getTargetBlockAddress(N->getBlockAddress(), Ty, 0, Flag);
95}
96
97SDValue MipsTargetLowering::getTargetNode(JumpTableSDNode *N, EVT Ty,
98 SelectionDAG &DAG,
99 unsigned Flag) const {
100 return DAG.getTargetJumpTable(N->getIndex(), Ty, Flag);
101}
102
103SDValue MipsTargetLowering::getTargetNode(ConstantPoolSDNode *N, EVT Ty,
104 SelectionDAG &DAG,
105 unsigned Flag) const {
106 return DAG.getTargetConstantPool(N->getConstVal(), Ty, N->getAlignment(),
107 N->getOffset(), Flag);
108}
109
110const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
111 switch ((MipsISD::NodeType)Opcode) {
112 case MipsISD::FIRST_NUMBER: break;
113 case MipsISD::JmpLink: return "MipsISD::JmpLink";
114 case MipsISD::TailCall: return "MipsISD::TailCall";
115 case MipsISD::Highest: return "MipsISD::Highest";
116 case MipsISD::Higher: return "MipsISD::Higher";
117 case MipsISD::Hi: return "MipsISD::Hi";
118 case MipsISD::Lo: return "MipsISD::Lo";
119 case MipsISD::GotHi: return "MipsISD::GotHi";
120 case MipsISD::GPRel: return "MipsISD::GPRel";
121 case MipsISD::ThreadPointer: return "MipsISD::ThreadPointer";
122 case MipsISD::Ret: return "MipsISD::Ret";
123 case MipsISD::ERet: return "MipsISD::ERet";
124 case MipsISD::EH_RETURN: return "MipsISD::EH_RETURN";
125 case MipsISD::FPBrcond: return "MipsISD::FPBrcond";
126 case MipsISD::FPCmp: return "MipsISD::FPCmp";
127 case MipsISD::CMovFP_T: return "MipsISD::CMovFP_T";
128 case MipsISD::CMovFP_F: return "MipsISD::CMovFP_F";
129 case MipsISD::TruncIntFP: return "MipsISD::TruncIntFP";
130 case MipsISD::MFHI: return "MipsISD::MFHI";
131 case MipsISD::MFLO: return "MipsISD::MFLO";
132 case MipsISD::MTLOHI: return "MipsISD::MTLOHI";
133 case MipsISD::Mult: return "MipsISD::Mult";
134 case MipsISD::Multu: return "MipsISD::Multu";
135 case MipsISD::MAdd: return "MipsISD::MAdd";
136 case MipsISD::MAddu: return "MipsISD::MAddu";
137 case MipsISD::MSub: return "MipsISD::MSub";
138 case MipsISD::MSubu: return "MipsISD::MSubu";
139 case MipsISD::DivRem: return "MipsISD::DivRem";
140 case MipsISD::DivRemU: return "MipsISD::DivRemU";
141 case MipsISD::DivRem16: return "MipsISD::DivRem16";
142 case MipsISD::DivRemU16: return "MipsISD::DivRemU16";
143 case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64";
144 case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64";
145 case MipsISD::Wrapper: return "MipsISD::Wrapper";
146 case MipsISD::DynAlloc: return "MipsISD::DynAlloc";
147 case MipsISD::Sync: return "MipsISD::Sync";
148 case MipsISD::Ext: return "MipsISD::Ext";
149 case MipsISD::Ins: return "MipsISD::Ins";
150 case MipsISD::CIns: return "MipsISD::CIns";
151 case MipsISD::LWL: return "MipsISD::LWL";
152 case MipsISD::LWR: return "MipsISD::LWR";
153 case MipsISD::SWL: return "MipsISD::SWL";
154 case MipsISD::SWR: return "MipsISD::SWR";
155 case MipsISD::LDL: return "MipsISD::LDL";
156 case MipsISD::LDR: return "MipsISD::LDR";
157 case MipsISD::SDL: return "MipsISD::SDL";
158 case MipsISD::SDR: return "MipsISD::SDR";
159 case MipsISD::EXTP: return "MipsISD::EXTP";
160 case MipsISD::EXTPDP: return "MipsISD::EXTPDP";
161 case MipsISD::EXTR_S_H: return "MipsISD::EXTR_S_H";
162 case MipsISD::EXTR_W: return "MipsISD::EXTR_W";
163 case MipsISD::EXTR_R_W: return "MipsISD::EXTR_R_W";
164 case MipsISD::EXTR_RS_W: return "MipsISD::EXTR_RS_W";
165 case MipsISD::SHILO: return "MipsISD::SHILO";
166 case MipsISD::MTHLIP: return "MipsISD::MTHLIP";
167 case MipsISD::MULSAQ_S_W_PH: return "MipsISD::MULSAQ_S_W_PH";
168 case MipsISD::MAQ_S_W_PHL: return "MipsISD::MAQ_S_W_PHL";
169 case MipsISD::MAQ_S_W_PHR: return "MipsISD::MAQ_S_W_PHR";
170 case MipsISD::MAQ_SA_W_PHL: return "MipsISD::MAQ_SA_W_PHL";
171 case MipsISD::MAQ_SA_W_PHR: return "MipsISD::MAQ_SA_W_PHR";
172 case MipsISD::DPAU_H_QBL: return "MipsISD::DPAU_H_QBL";
173 case MipsISD::DPAU_H_QBR: return "MipsISD::DPAU_H_QBR";
174 case MipsISD::DPSU_H_QBL: return "MipsISD::DPSU_H_QBL";
175 case MipsISD::DPSU_H_QBR: return "MipsISD::DPSU_H_QBR";
176 case MipsISD::DPAQ_S_W_PH: return "MipsISD::DPAQ_S_W_PH";
177 case MipsISD::DPSQ_S_W_PH: return "MipsISD::DPSQ_S_W_PH";
178 case MipsISD::DPAQ_SA_L_W: return "MipsISD::DPAQ_SA_L_W";
179 case MipsISD::DPSQ_SA_L_W: return "MipsISD::DPSQ_SA_L_W";
180 case MipsISD::DPA_W_PH: return "MipsISD::DPA_W_PH";
181 case MipsISD::DPS_W_PH: return "MipsISD::DPS_W_PH";
182 case MipsISD::DPAQX_S_W_PH: return "MipsISD::DPAQX_S_W_PH";
183 case MipsISD::DPAQX_SA_W_PH: return "MipsISD::DPAQX_SA_W_PH";
184 case MipsISD::DPAX_W_PH: return "MipsISD::DPAX_W_PH";
185 case MipsISD::DPSX_W_PH: return "MipsISD::DPSX_W_PH";
186 case MipsISD::DPSQX_S_W_PH: return "MipsISD::DPSQX_S_W_PH";
187 case MipsISD::DPSQX_SA_W_PH: return "MipsISD::DPSQX_SA_W_PH";
188 case MipsISD::MULSA_W_PH: return "MipsISD::MULSA_W_PH";
189 case MipsISD::MULT: return "MipsISD::MULT";
190 case MipsISD::MULTU: return "MipsISD::MULTU";
191 case MipsISD::MADD_DSP: return "MipsISD::MADD_DSP";
192 case MipsISD::MADDU_DSP: return "MipsISD::MADDU_DSP";
193 case MipsISD::MSUB_DSP: return "MipsISD::MSUB_DSP";
194 case MipsISD::MSUBU_DSP: return "MipsISD::MSUBU_DSP";
195 case MipsISD::SHLL_DSP: return "MipsISD::SHLL_DSP";
196 case MipsISD::SHRA_DSP: return "MipsISD::SHRA_DSP";
197 case MipsISD::SHRL_DSP: return "MipsISD::SHRL_DSP";
198 case MipsISD::SETCC_DSP: return "MipsISD::SETCC_DSP";
199 case MipsISD::SELECT_CC_DSP: return "MipsISD::SELECT_CC_DSP";
200 case MipsISD::VALL_ZERO: return "MipsISD::VALL_ZERO";
201 case MipsISD::VANY_ZERO: return "MipsISD::VANY_ZERO";
202 case MipsISD::VALL_NONZERO: return "MipsISD::VALL_NONZERO";
203 case MipsISD::VANY_NONZERO: return "MipsISD::VANY_NONZERO";
204 case MipsISD::VCEQ: return "MipsISD::VCEQ";
205 case MipsISD::VCLE_S: return "MipsISD::VCLE_S";
206 case MipsISD::VCLE_U: return "MipsISD::VCLE_U";
207 case MipsISD::VCLT_S: return "MipsISD::VCLT_S";
208 case MipsISD::VCLT_U: return "MipsISD::VCLT_U";
209 case MipsISD::VSMAX: return "MipsISD::VSMAX";
210 case MipsISD::VSMIN: return "MipsISD::VSMIN";
211 case MipsISD::VUMAX: return "MipsISD::VUMAX";
212 case MipsISD::VUMIN: return "MipsISD::VUMIN";
213 case MipsISD::VEXTRACT_SEXT_ELT: return "MipsISD::VEXTRACT_SEXT_ELT";
214 case MipsISD::VEXTRACT_ZEXT_ELT: return "MipsISD::VEXTRACT_ZEXT_ELT";
215 case MipsISD::VNOR: return "MipsISD::VNOR";
216 case MipsISD::VSHF: return "MipsISD::VSHF";
217 case MipsISD::SHF: return "MipsISD::SHF";
218 case MipsISD::ILVEV: return "MipsISD::ILVEV";
219 case MipsISD::ILVOD: return "MipsISD::ILVOD";
220 case MipsISD::ILVL: return "MipsISD::ILVL";
221 case MipsISD::ILVR: return "MipsISD::ILVR";
222 case MipsISD::PCKEV: return "MipsISD::PCKEV";
223 case MipsISD::PCKOD: return "MipsISD::PCKOD";
224 case MipsISD::INSVE: return "MipsISD::INSVE";
225 }
226 return nullptr;
227}
228
229MipsTargetLowering::MipsTargetLowering(const MipsTargetMachine &TM,
230 const MipsSubtarget &STI)
231 : TargetLowering(TM), Subtarget(STI), ABI(TM.getABI()) {
232 // Mips does not have i1 type, so use i32 for
233 // setcc operations results (slt, sgt, ...).
234 setBooleanContents(ZeroOrOneBooleanContent);
235 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
236 // The cmp.cond.fmt instruction in MIPS32r6/MIPS64r6 uses 0 and -1 like MSA
237 // does. Integer booleans still use 0 and 1.
238 if (Subtarget.hasMips32r6())
239 setBooleanContents(ZeroOrOneBooleanContent,
240 ZeroOrNegativeOneBooleanContent);
241
242 // Load extented operations for i1 types must be promoted
243 for (MVT VT : MVT::integer_valuetypes()) {
244 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
245 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
246 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
247 }
248
249 // MIPS doesn't have extending float->double load/store. Set LoadExtAction
250 // for f32, f16
251 for (MVT VT : MVT::fp_valuetypes()) {
252 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
253 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand);
254 }
255
256 // Set LoadExtAction for f16 vectors to Expand
257 for (MVT VT : MVT::fp_vector_valuetypes()) {
258 MVT F16VT = MVT::getVectorVT(MVT::f16, VT.getVectorNumElements());
259 if (F16VT.isValid())
260 setLoadExtAction(ISD::EXTLOAD, VT, F16VT, Expand);
261 }
262
263 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
264 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
265
266 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
267
268 // Used by legalize types to correctly generate the setcc result.
269 // Without this, every float setcc comes with a AND/OR with the result,
270 // we don't want this, since the fpcmp result goes to a flag register,
271 // which is used implicitly by brcond and select operations.
272 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
273
274 // Mips Custom Operations
275 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
276 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
277 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
278 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
279 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
280 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
281 setOperationAction(ISD::SELECT, MVT::f32, Custom);
282 setOperationAction(ISD::SELECT, MVT::f64, Custom);
283 setOperationAction(ISD::SELECT, MVT::i32, Custom);
284 setOperationAction(ISD::SETCC, MVT::f32, Custom);
285 setOperationAction(ISD::SETCC, MVT::f64, Custom);
286 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
287 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
288 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
289 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
290
291 if (Subtarget.isGP64bit()) {
292 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
293 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
294 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
295 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
296 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
297 setOperationAction(ISD::SELECT, MVT::i64, Custom);
298 setOperationAction(ISD::LOAD, MVT::i64, Custom);
299 setOperationAction(ISD::STORE, MVT::i64, Custom);
300 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
301 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
302 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
303 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
304 }
305
306 if (!Subtarget.isGP64bit()) {
307 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
308 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
309 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
310 }
311
312 setOperationAction(ISD::EH_DWARF_CFA, MVT::i32, Custom);
313 if (Subtarget.isGP64bit())
314 setOperationAction(ISD::EH_DWARF_CFA, MVT::i64, Custom);
315
316 setOperationAction(ISD::SDIV, MVT::i32, Expand);
317 setOperationAction(ISD::SREM, MVT::i32, Expand);
318 setOperationAction(ISD::UDIV, MVT::i32, Expand);
319 setOperationAction(ISD::UREM, MVT::i32, Expand);
320 setOperationAction(ISD::SDIV, MVT::i64, Expand);
321 setOperationAction(ISD::SREM, MVT::i64, Expand);
322 setOperationAction(ISD::UDIV, MVT::i64, Expand);
323 setOperationAction(ISD::UREM, MVT::i64, Expand);
324
325 // Operations not directly supported by Mips.
326 setOperationAction(ISD::BR_CC, MVT::f32, Expand);
327 setOperationAction(ISD::BR_CC, MVT::f64, Expand);
328 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
329 setOperationAction(ISD::BR_CC, MVT::i64, Expand);
330 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
331 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
332 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
333 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
334 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
335 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
336 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
337 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
338 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
339 if (Subtarget.hasCnMips()) {
340 setOperationAction(ISD::CTPOP, MVT::i32, Legal);
341 setOperationAction(ISD::CTPOP, MVT::i64, Legal);
342 } else {
343 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
344 setOperationAction(ISD::CTPOP, MVT::i64, Expand);
345 }
346 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
347 setOperationAction(ISD::CTTZ, MVT::i64, Expand);
348 setOperationAction(ISD::ROTL, MVT::i32, Expand);
349 setOperationAction(ISD::ROTL, MVT::i64, Expand);
350 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
351 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
352
353 if (!Subtarget.hasMips32r2())
354 setOperationAction(ISD::ROTR, MVT::i32, Expand);
355
356 if (!Subtarget.hasMips64r2())
357 setOperationAction(ISD::ROTR, MVT::i64, Expand);
358
359 setOperationAction(ISD::FSIN, MVT::f32, Expand);
360 setOperationAction(ISD::FSIN, MVT::f64, Expand);
361 setOperationAction(ISD::FCOS, MVT::f32, Expand);
362 setOperationAction(ISD::FCOS, MVT::f64, Expand);
363 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
364 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
365 setOperationAction(ISD::FPOWI, MVT::f32, Expand);
366 setOperationAction(ISD::FPOW, MVT::f32, Expand);
367 setOperationAction(ISD::FPOW, MVT::f64, Expand);
368 setOperationAction(ISD::FLOG, MVT::f32, Expand);
369 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
370 setOperationAction(ISD::FLOG10, MVT::f32, Expand);
371 setOperationAction(ISD::FEXP, MVT::f32, Expand);
372 setOperationAction(ISD::FMA, MVT::f32, Expand);
373 setOperationAction(ISD::FMA, MVT::f64, Expand);
374 setOperationAction(ISD::FREM, MVT::f32, Expand);
375 setOperationAction(ISD::FREM, MVT::f64, Expand);
376
377 // Lower f16 conversion operations into library calls
378 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
379 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
380 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
381 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
382
383 setOperationAction(ISD::EH_RETURN, MVT::Other, Custom);
384
385 setOperationAction(ISD::VASTART, MVT::Other, Custom);
386 setOperationAction(ISD::VAARG, MVT::Other, Custom);
387 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
388 setOperationAction(ISD::VAEND, MVT::Other, Expand);
389
390 // Use the default for now
391 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
392 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
393
394 if (!Subtarget.isGP64bit()) {
395 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
396 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
397 }
398
399
400 if (!Subtarget.hasMips32r2()) {
401 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
402 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
403 }
404
405 // MIPS16 lacks MIPS32's clz and clo instructions.
406 if (!Subtarget.hasMips32() || Subtarget.inMips16Mode())
407 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
408 if (!Subtarget.hasMips64())
409 setOperationAction(ISD::CTLZ, MVT::i64, Expand);
410
411 if (!Subtarget.hasMips32r2())
412 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
413 if (!Subtarget.hasMips64r2())
414 setOperationAction(ISD::BSWAP, MVT::i64, Expand);
415
416 if (Subtarget.isGP64bit()) {
417 setLoadExtAction(ISD::SEXTLOAD, MVT::i64, MVT::i32, Custom);
418 setLoadExtAction(ISD::ZEXTLOAD, MVT::i64, MVT::i32, Custom);
419 setLoadExtAction(ISD::EXTLOAD, MVT::i64, MVT::i32, Custom);
420 setTruncStoreAction(MVT::i64, MVT::i32, Custom);
421 }
422
423 setOperationAction(ISD::TRAP, MVT::Other, Legal);
424
425 setTargetDAGCombine(ISD::SDIVREM);
426 setTargetDAGCombine(ISD::UDIVREM);
427 setTargetDAGCombine(ISD::SELECT);
428 setTargetDAGCombine(ISD::AND);
429 setTargetDAGCombine(ISD::OR);
430 setTargetDAGCombine(ISD::ADD);
431 setTargetDAGCombine(ISD::AssertZext);
432 setTargetDAGCombine(ISD::SHL);
433
434 if (ABI.IsO32()) {
435 // These libcalls are not available in 32-bit.
436 setLibcallName(RTLIB::SHL_I128, nullptr);
437 setLibcallName(RTLIB::SRL_I128, nullptr);
438 setLibcallName(RTLIB::SRA_I128, nullptr);
439 }
440
441 setMinFunctionAlignment(Subtarget.isGP64bit() ? 3 : 2);
442
443 // The arguments on the stack are defined in terms of 4-byte slots on O32
444 // and 8-byte slots on N32/N64.
445 setMinStackArgumentAlignment((ABI.IsN32() || ABI.IsN64()) ? 8 : 4);
446
447 setStackPointerRegisterToSaveRestore(ABI.IsN64() ? Mips::SP_64 : Mips::SP);
448
449 MaxStoresPerMemcpy = 16;
450
451 isMicroMips = Subtarget.inMicroMipsMode();
452}
453
454const MipsTargetLowering *MipsTargetLowering::create(const MipsTargetMachine &TM,
455 const MipsSubtarget &STI) {
456 if (STI.inMips16Mode())
457 return llvm::createMips16TargetLowering(TM, STI);
458
459 return llvm::createMipsSETargetLowering(TM, STI);
460}
461
462// Create a fast isel object.
463FastISel *
464MipsTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
465 const TargetLibraryInfo *libInfo) const {
466 const MipsTargetMachine &TM =
467 static_cast<const MipsTargetMachine &>(funcInfo.MF->getTarget());
468
469 // We support only the standard encoding [MIPS32,MIPS32R5] ISAs.
470 bool UseFastISel = TM.Options.EnableFastISel && Subtarget.hasMips32() &&
471 !Subtarget.hasMips32r6() && !Subtarget.inMips16Mode() &&
472 !Subtarget.inMicroMipsMode();
473
474 // Disable if we don't generate PIC or the ABI isn't O32.
475 if (!TM.isPositionIndependent() || !TM.getABI().IsO32())
476 UseFastISel = false;
477
478 return UseFastISel ? Mips::createFastISel(funcInfo, libInfo) : nullptr;
479}
480
481EVT MipsTargetLowering::getSetCCResultType(const DataLayout &, LLVMContext &,
482 EVT VT) const {
483 if (!VT.isVector())
484 return MVT::i32;
485 return VT.changeVectorElementTypeToInteger();
486}
487
488static SDValue performDivRemCombine(SDNode *N, SelectionDAG &DAG,
489 TargetLowering::DAGCombinerInfo &DCI,
490 const MipsSubtarget &Subtarget) {
491 if (DCI.isBeforeLegalizeOps())
492 return SDValue();
493
494 EVT Ty = N->getValueType(0);
495 unsigned LO = (Ty == MVT::i32) ? Mips::LO0 : Mips::LO0_64;
496 unsigned HI = (Ty == MVT::i32) ? Mips::HI0 : Mips::HI0_64;
497 unsigned Opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem16 :
498 MipsISD::DivRemU16;
499 SDLoc DL(N);
500
501 SDValue DivRem = DAG.getNode(Opc, DL, MVT::Glue,
502 N->getOperand(0), N->getOperand(1));
503 SDValue InChain = DAG.getEntryNode();
504 SDValue InGlue = DivRem;
505
506 // insert MFLO
507 if (N->hasAnyUseOfValue(0)) {
508 SDValue CopyFromLo = DAG.getCopyFromReg(InChain, DL, LO, Ty,
509 InGlue);
510 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo);
511 InChain = CopyFromLo.getValue(1);
512 InGlue = CopyFromLo.getValue(2);
513 }
514
515 // insert MFHI
516 if (N->hasAnyUseOfValue(1)) {
517 SDValue CopyFromHi = DAG.getCopyFromReg(InChain, DL,
518 HI, Ty, InGlue);
519 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi);
520 }
521
522 return SDValue();
523}
524
525static Mips::CondCode condCodeToFCC(ISD::CondCode CC) {
526 switch (CC) {
527 default: llvm_unreachable("Unknown fp condition code!")::llvm::llvm_unreachable_internal("Unknown fp condition code!"
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/Target/Mips/MipsISelLowering.cpp"
, 527)
;
528 case ISD::SETEQ:
529 case ISD::SETOEQ: return Mips::FCOND_OEQ;
530 case ISD::SETUNE: return Mips::FCOND_UNE;
531 case ISD::SETLT:
532 case ISD::SETOLT: return Mips::FCOND_OLT;
533 case ISD::SETGT:
534 case ISD::SETOGT: return Mips::FCOND_OGT;
535 case ISD::SETLE:
536 case ISD::SETOLE: return Mips::FCOND_OLE;
537 case ISD::SETGE:
538 case ISD::SETOGE: return Mips::FCOND_OGE;
539 case ISD::SETULT: return Mips::FCOND_ULT;
540 case ISD::SETULE: return Mips::FCOND_ULE;
541 case ISD::SETUGT: return Mips::FCOND_UGT;
542 case ISD::SETUGE: return Mips::FCOND_UGE;
543 case ISD::SETUO: return Mips::FCOND_UN;
544 case ISD::SETO: return Mips::FCOND_OR;
545 case ISD::SETNE:
546 case ISD::SETONE: return Mips::FCOND_ONE;
547 case ISD::SETUEQ: return Mips::FCOND_UEQ;
548 }
549}
550
551
552/// This function returns true if the floating point conditional branches and
553/// conditional moves which use condition code CC should be inverted.
554static bool invertFPCondCodeUser(Mips::CondCode CC) {
555 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
556 return false;
557
558 assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) &&(((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT)
&& "Illegal Condition Code") ? static_cast<void>
(0) : __assert_fail ("(CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) && \"Illegal Condition Code\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/Target/Mips/MipsISelLowering.cpp"
, 559, __PRETTY_FUNCTION__))
559 "Illegal Condition Code")(((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT)
&& "Illegal Condition Code") ? static_cast<void>
(0) : __assert_fail ("(CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) && \"Illegal Condition Code\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/Target/Mips/MipsISelLowering.cpp"
, 559, __PRETTY_FUNCTION__))
;
560
561 return true;
562}
563
564// Creates and returns an FPCmp node from a setcc node.
565// Returns Op if setcc is not a floating point comparison.
566static SDValue createFPCmp(SelectionDAG &DAG, const SDValue &Op) {
567 // must be a SETCC node
568 if (Op.getOpcode() != ISD::SETCC)
569 return Op;
570
571 SDValue LHS = Op.getOperand(0);
572
573 if (!LHS.getValueType().isFloatingPoint())
574 return Op;
575
576 SDValue RHS = Op.getOperand(1);
577 SDLoc DL(Op);
578
579 // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of
580 // node if necessary.
581 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
582
583 return DAG.getNode(MipsISD::FPCmp, DL, MVT::Glue, LHS, RHS,
584 DAG.getConstant(condCodeToFCC(CC), DL, MVT::i32));
585}
586
587// Creates and returns a CMovFPT/F node.
588static SDValue createCMovFP(SelectionDAG &DAG, SDValue Cond, SDValue True,
589 SDValue False, const SDLoc &DL) {
590 ConstantSDNode *CC = cast<ConstantSDNode>(Cond.getOperand(2));
591 bool invert = invertFPCondCodeUser((Mips::CondCode)CC->getSExtValue());
592 SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32);
593
594 return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL,
595 True.getValueType(), True, FCC0, False, Cond);
596}
597
598static SDValue performSELECTCombine(SDNode *N, SelectionDAG &DAG,
599 TargetLowering::DAGCombinerInfo &DCI,
600 const MipsSubtarget &Subtarget) {
601 if (DCI.isBeforeLegalizeOps())
602 return SDValue();
603
604 SDValue SetCC = N->getOperand(0);
605
606 if ((SetCC.getOpcode() != ISD::SETCC) ||
607 !SetCC.getOperand(0).getValueType().isInteger())
608 return SDValue();
609
610 SDValue False = N->getOperand(2);
611 EVT FalseTy = False.getValueType();
612
613 if (!FalseTy.isInteger())
614 return SDValue();
615
616 ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(False);
617
618 // If the RHS (False) is 0, we swap the order of the operands
619 // of ISD::SELECT (obviously also inverting the condition) so that we can
620 // take advantage of conditional moves using the $0 register.
621 // Example:
622 // return (a != 0) ? x : 0;
623 // load $reg, x
624 // movz $reg, $0, a
625 if (!FalseC)
626 return SDValue();
627
628 const SDLoc DL(N);
629
630 if (!FalseC->getZExtValue()) {
631 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get();
632 SDValue True = N->getOperand(1);
633
634 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0),
635 SetCC.getOperand(1), ISD::getSetCCInverse(CC, true));
636
637 return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True);
638 }
639
640 // If both operands are integer constants there's a possibility that we
641 // can do some interesting optimizations.
642 SDValue True = N->getOperand(1);
643 ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(True);
644
645 if (!TrueC || !True.getValueType().isInteger())
646 return SDValue();
647
648 // We'll also ignore MVT::i64 operands as this optimizations proves
649 // to be ineffective because of the required sign extensions as the result
650 // of a SETCC operator is always MVT::i32 for non-vector types.
651 if (True.getValueType() == MVT::i64)
652 return SDValue();
653
654 int64_t Diff = TrueC->getSExtValue() - FalseC->getSExtValue();
655
656 // 1) (a < x) ? y : y-1
657 // slti $reg1, a, x
658 // addiu $reg2, $reg1, y-1
659 if (Diff == 1)
660 return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, False);
661
662 // 2) (a < x) ? y-1 : y
663 // slti $reg1, a, x
664 // xor $reg1, $reg1, 1
665 // addiu $reg2, $reg1, y-1
666 if (Diff == -1) {
667 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get();
668 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0),
669 SetCC.getOperand(1), ISD::getSetCCInverse(CC, true));
670 return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, True);
671 }
672
673 // Couldn't optimize.
674 return SDValue();
675}
676
677static SDValue performCMovFPCombine(SDNode *N, SelectionDAG &DAG,
678 TargetLowering::DAGCombinerInfo &DCI,
679 const MipsSubtarget &Subtarget) {
680 if (DCI.isBeforeLegalizeOps())
681 return SDValue();
682
683 SDValue ValueIfTrue = N->getOperand(0), ValueIfFalse = N->getOperand(2);
684
685 ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(ValueIfFalse);
686 if (!FalseC || FalseC->getZExtValue())
687 return SDValue();
688
689 // Since RHS (False) is 0, we swap the order of the True/False operands
690 // (obviously also inverting the condition) so that we can
691 // take advantage of conditional moves using the $0 register.
692 // Example:
693 // return (a != 0) ? x : 0;
694 // load $reg, x
695 // movz $reg, $0, a
696 unsigned Opc = (N->getOpcode() == MipsISD::CMovFP_T) ? MipsISD::CMovFP_F :
697 MipsISD::CMovFP_T;
698
699 SDValue FCC = N->getOperand(1), Glue = N->getOperand(3);
700 return DAG.getNode(Opc, SDLoc(N), ValueIfFalse.getValueType(),
701 ValueIfFalse, FCC, ValueIfTrue, Glue);
702}
703
704static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG,
705 TargetLowering::DAGCombinerInfo &DCI,
706 const MipsSubtarget &Subtarget) {
707 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert())
708 return SDValue();
709
710 SDValue FirstOperand = N->getOperand(0);
711 unsigned FirstOperandOpc = FirstOperand.getOpcode();
712 SDValue Mask = N->getOperand(1);
713 EVT ValTy = N->getValueType(0);
714 SDLoc DL(N);
715
716 uint64_t Pos = 0, SMPos, SMSize;
717 ConstantSDNode *CN;
718 SDValue NewOperand;
719 unsigned Opc;
720
721 // Op's second operand must be a shifted mask.
722 if (!(CN = dyn_cast<ConstantSDNode>(Mask)) ||
723 !isShiftedMask(CN->getZExtValue(), SMPos, SMSize))
724 return SDValue();
725
726 if (FirstOperandOpc == ISD::SRA || FirstOperandOpc == ISD::SRL) {
727 // Pattern match EXT.
728 // $dst = and ((sra or srl) $src , pos), (2**size - 1)
729 // => ext $dst, $src, pos, size
730
731 // The second operand of the shift must be an immediate.
732 if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.getOperand(1))))
733 return SDValue();
734
735 Pos = CN->getZExtValue();
736
737 // Return if the shifted mask does not start at bit 0 or the sum of its size
738 // and Pos exceeds the word's size.
739 if (SMPos != 0 || Pos + SMSize > ValTy.getSizeInBits())
740 return SDValue();
741
742 Opc = MipsISD::Ext;
743 NewOperand = FirstOperand.getOperand(0);
744 } else if (FirstOperandOpc == ISD::SHL && Subtarget.hasCnMips()) {
745 // Pattern match CINS.
746 // $dst = and (shl $src , pos), mask
747 // => cins $dst, $src, pos, size
748 // mask is a shifted mask with consecutive 1's, pos = shift amount,
749 // size = population count.
750
751 // The second operand of the shift must be an immediate.
752 if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.getOperand(1))))
753 return SDValue();
754
755 Pos = CN->getZExtValue();
756
757 if (SMPos != Pos || Pos >= ValTy.getSizeInBits() || SMSize >= 32 ||
758 Pos + SMSize > ValTy.getSizeInBits())
759 return SDValue();
760
761 NewOperand = FirstOperand.getOperand(0);
762 // SMSize is 'location' (position) in this case, not size.
763 SMSize--;
764 Opc = MipsISD::CIns;
765 } else {
766 // Pattern match EXT.
767 // $dst = and $src, (2**size - 1) , if size > 16
768 // => ext $dst, $src, pos, size , pos = 0
769
770 // If the mask is <= 0xffff, andi can be used instead.
771 if (CN->getZExtValue() <= 0xffff)
772 return SDValue();
773
774 // Return if the mask doesn't start at position 0.
775 if (SMPos)
776 return SDValue();
777
778 Opc = MipsISD::Ext;
779 NewOperand = FirstOperand;
780 }
781 return DAG.getNode(Opc, DL, ValTy, NewOperand,
782 DAG.getConstant(Pos, DL, MVT::i32),
783 DAG.getConstant(SMSize, DL, MVT::i32));
784}
785
786static SDValue performORCombine(SDNode *N, SelectionDAG &DAG,
787 TargetLowering::DAGCombinerInfo &DCI,
788 const MipsSubtarget &Subtarget) {
789 // Pattern match INS.
790 // $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1),
791 // where mask1 = (2**size - 1) << pos, mask0 = ~mask1
792 // => ins $dst, $src, size, pos, $src1
793 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert())
794 return SDValue();
795
796 SDValue And0 = N->getOperand(0), And1 = N->getOperand(1);
797 uint64_t SMPos0, SMSize0, SMPos1, SMSize1;
798 ConstantSDNode *CN;
799
800 // See if Op's first operand matches (and $src1 , mask0).
801 if (And0.getOpcode() != ISD::AND)
802 return SDValue();
803
804 if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) ||
805 !isShiftedMask(~CN->getSExtValue(), SMPos0, SMSize0))
806 return SDValue();
807
808 // See if Op's second operand matches (and (shl $src, pos), mask1).
809 if (And1.getOpcode() != ISD::AND)
810 return SDValue();
811
812 if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) ||
813 !isShiftedMask(CN->getZExtValue(), SMPos1, SMSize1))
814 return SDValue();
815
816 // The shift masks must have the same position and size.
817 if (SMPos0 != SMPos1 || SMSize0 != SMSize1)
818 return SDValue();
819
820 SDValue Shl = And1.getOperand(0);
821 if (Shl.getOpcode() != ISD::SHL)
822 return SDValue();
823
824 if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1))))
825 return SDValue();
826
827 unsigned Shamt = CN->getZExtValue();
828
829 // Return if the shift amount and the first bit position of mask are not the
830 // same.
831 EVT ValTy = N->getValueType(0);
832 if ((Shamt != SMPos0) || (SMPos0 + SMSize0 > ValTy.getSizeInBits()))
833 return SDValue();
834
835 SDLoc DL(N);
836 return DAG.getNode(MipsISD::Ins, DL, ValTy, Shl.getOperand(0),
837 DAG.getConstant(SMPos0, DL, MVT::i32),
838 DAG.getConstant(SMSize0, DL, MVT::i32),
839 And0.getOperand(0));
840}
841
842static SDValue performADDCombine(SDNode *N, SelectionDAG &DAG,
843 TargetLowering::DAGCombinerInfo &DCI,
844 const MipsSubtarget &Subtarget) {
845 // (add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt))
846
847 if (DCI.isBeforeLegalizeOps())
848 return SDValue();
849
850 SDValue Add = N->getOperand(1);
851
852 if (Add.getOpcode() != ISD::ADD)
853 return SDValue();
854
855 SDValue Lo = Add.getOperand(1);
856
857 if ((Lo.getOpcode() != MipsISD::Lo) ||
858 (Lo.getOperand(0).getOpcode() != ISD::TargetJumpTable))
859 return SDValue();
860
861 EVT ValTy = N->getValueType(0);
862 SDLoc DL(N);
863
864 SDValue Add1 = DAG.getNode(ISD::ADD, DL, ValTy, N->getOperand(0),
865 Add.getOperand(0));
866 return DAG.getNode(ISD::ADD, DL, ValTy, Add1, Lo);
867}
868
869static SDValue performAssertZextCombine(SDNode *N, SelectionDAG &DAG,
870 TargetLowering::DAGCombinerInfo &DCI,
871 const MipsSubtarget &Subtarget) {
872 SDValue N0 = N->getOperand(0);
873 EVT NarrowerVT = cast<VTSDNode>(N->getOperand(1))->getVT();
874
875 if (N0.getOpcode() != ISD::TRUNCATE)
876 return SDValue();
877
878 if (N0.getOperand(0).getOpcode() != ISD::AssertZext)
879 return SDValue();
880
881 // fold (AssertZext (trunc (AssertZext x))) -> (trunc (AssertZext x))
882 // if the type of the extension of the innermost AssertZext node is
883 // smaller from that of the outermost node, eg:
884 // (AssertZext:i32 (trunc:i32 (AssertZext:i64 X, i32)), i8)
885 // -> (trunc:i32 (AssertZext X, i8))
886 SDValue WiderAssertZext = N0.getOperand(0);
887 EVT WiderVT = cast<VTSDNode>(WiderAssertZext->getOperand(1))->getVT();
888
889 if (NarrowerVT.bitsLT(WiderVT)) {
890 SDValue NewAssertZext = DAG.getNode(
891 ISD::AssertZext, SDLoc(N), WiderAssertZext.getValueType(),
892 WiderAssertZext.getOperand(0), DAG.getValueType(NarrowerVT));
893 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), N->getValueType(0),
894 NewAssertZext);
895 }
896
897 return SDValue();
898}
899
900
901static SDValue performSHLCombine(SDNode *N, SelectionDAG &DAG,
902 TargetLowering::DAGCombinerInfo &DCI,
903 const MipsSubtarget &Subtarget) {
904 // Pattern match CINS.
905 // $dst = shl (and $src , imm), pos
906 // => cins $dst, $src, pos, size
907
908 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasCnMips())
909 return SDValue();
910
911 SDValue FirstOperand = N->getOperand(0);
912 unsigned FirstOperandOpc = FirstOperand.getOpcode();
913 SDValue SecondOperand = N->getOperand(1);
914 EVT ValTy = N->getValueType(0);
915 SDLoc DL(N);
916
917 uint64_t Pos = 0, SMPos, SMSize;
918 ConstantSDNode *CN;
919 SDValue NewOperand;
920
921 // The second operand of the shift must be an immediate.
922 if (!(CN = dyn_cast<ConstantSDNode>(SecondOperand)))
923 return SDValue();
924
925 Pos = CN->getZExtValue();
926
927 if (Pos >= ValTy.getSizeInBits())
928 return SDValue();
929
930 if (FirstOperandOpc != ISD::AND)
931 return SDValue();
932
933 // AND's second operand must be a shifted mask.
934 if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.getOperand(1))) ||
935 !isShiftedMask(CN->getZExtValue(), SMPos, SMSize))
936 return SDValue();
937
938 // Return if the shifted mask does not start at bit 0 or the sum of its size
939 // and Pos exceeds the word's size.
940 if (SMPos != 0 || SMSize > 32 || Pos + SMSize > ValTy.getSizeInBits())
941 return SDValue();
942
943 NewOperand = FirstOperand.getOperand(0);
944 // SMSize is 'location' (position) in this case, not size.
945 SMSize--;
946
947 return DAG.getNode(MipsISD::CIns, DL, ValTy, NewOperand,
948 DAG.getConstant(Pos, DL, MVT::i32),
949 DAG.getConstant(SMSize, DL, MVT::i32));
950}
951
952SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI)
953 const {
954 SelectionDAG &DAG = DCI.DAG;
955 unsigned Opc = N->getOpcode();
956
957 switch (Opc) {
958 default: break;
959 case ISD::SDIVREM:
960 case ISD::UDIVREM:
961 return performDivRemCombine(N, DAG, DCI, Subtarget);
962 case ISD::SELECT:
963 return performSELECTCombine(N, DAG, DCI, Subtarget);
964 case MipsISD::CMovFP_F:
965 case MipsISD::CMovFP_T:
966 return performCMovFPCombine(N, DAG, DCI, Subtarget);
967 case ISD::AND:
968 return performANDCombine(N, DAG, DCI, Subtarget);
969 case ISD::OR:
970 return performORCombine(N, DAG, DCI, Subtarget);
971 case ISD::ADD:
972 return performADDCombine(N, DAG, DCI, Subtarget);
973 case ISD::AssertZext:
974 return performAssertZextCombine(N, DAG, DCI, Subtarget);
975 case ISD::SHL:
976 return performSHLCombine(N, DAG, DCI, Subtarget);
977 }
978
979 return SDValue();
980}
981
982bool MipsTargetLowering::isCheapToSpeculateCttz() const {
983 return Subtarget.hasMips32();
984}
985
986bool MipsTargetLowering::isCheapToSpeculateCtlz() const {
987 return Subtarget.hasMips32();
988}
989
990void
991MipsTargetLowering::LowerOperationWrapper(SDNode *N,
992 SmallVectorImpl<SDValue> &Results,
993 SelectionDAG &DAG) const {
994 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
995
996 for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I)
997 Results.push_back(Res.getValue(I));
998}
999
1000void
1001MipsTargetLowering::ReplaceNodeResults(SDNode *N,
1002 SmallVectorImpl<SDValue> &Results,
1003 SelectionDAG &DAG) const {
1004 return LowerOperationWrapper(N, Results, DAG);
1005}
1006
1007SDValue MipsTargetLowering::
1008LowerOperation(SDValue Op, SelectionDAG &DAG) const
1009{
1010 switch (Op.getOpcode())
1011 {
1012 case ISD::BRCOND: return lowerBRCOND(Op, DAG);
1013 case ISD::ConstantPool: return lowerConstantPool(Op, DAG);
1014 case ISD::GlobalAddress: return lowerGlobalAddress(Op, DAG);
1015 case ISD::BlockAddress: return lowerBlockAddress(Op, DAG);
1016 case ISD::GlobalTLSAddress: return lowerGlobalTLSAddress(Op, DAG);
1017 case ISD::JumpTable: return lowerJumpTable(Op, DAG);
1018 case ISD::SELECT: return lowerSELECT(Op, DAG);
1019 case ISD::SETCC: return lowerSETCC(Op, DAG);
1020 case ISD::VASTART: return lowerVASTART(Op, DAG);
1021 case ISD::VAARG: return lowerVAARG(Op, DAG);
1022 case ISD::FCOPYSIGN: return lowerFCOPYSIGN(Op, DAG);
1023 case ISD::FRAMEADDR: return lowerFRAMEADDR(Op, DAG);
1024 case ISD::RETURNADDR: return lowerRETURNADDR(Op, DAG);
1025 case ISD::EH_RETURN: return lowerEH_RETURN(Op, DAG);
1026 case ISD::ATOMIC_FENCE: return lowerATOMIC_FENCE(Op, DAG);
1027 case ISD::SHL_PARTS: return lowerShiftLeftParts(Op, DAG);
1028 case ISD::SRA_PARTS: return lowerShiftRightParts(Op, DAG, true);
1029 case ISD::SRL_PARTS: return lowerShiftRightParts(Op, DAG, false);
1030 case ISD::LOAD: return lowerLOAD(Op, DAG);
1031 case ISD::STORE: return lowerSTORE(Op, DAG);
1032 case ISD::EH_DWARF_CFA: return lowerEH_DWARF_CFA(Op, DAG);
1033 case ISD::FP_TO_SINT: return lowerFP_TO_SINT(Op, DAG);
1034 }
1035 return SDValue();
1036}
1037
1038//===----------------------------------------------------------------------===//
1039// Lower helper functions
1040//===----------------------------------------------------------------------===//
1041
1042// addLiveIn - This helper function adds the specified physical register to the
1043// MachineFunction as a live in value. It also creates a corresponding
1044// virtual register for it.
1045static unsigned
1046addLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC)
1047{
1048 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
1049 MF.getRegInfo().addLiveIn(PReg, VReg);
1050 return VReg;
1051}
1052
1053static MachineBasicBlock *insertDivByZeroTrap(MachineInstr &MI,
1054 MachineBasicBlock &MBB,
1055 const TargetInstrInfo &TII,
1056 bool Is64Bit, bool IsMicroMips) {
1057 if (NoZeroDivCheck)
1058 return &MBB;
1059
1060 // Insert instruction "teq $divisor_reg, $zero, 7".
1061 MachineBasicBlock::iterator I(MI);
1062 MachineInstrBuilder MIB;
1063 MachineOperand &Divisor = MI.getOperand(2);
1064 MIB = BuildMI(MBB, std::next(I), MI.getDebugLoc(),
1065 TII.get(IsMicroMips ? Mips::TEQ_MM : Mips::TEQ))
1066 .addReg(Divisor.getReg(), getKillRegState(Divisor.isKill()))
1067 .addReg(Mips::ZERO)
1068 .addImm(7);
1069
1070 // Use the 32-bit sub-register if this is a 64-bit division.
1071 if (Is64Bit)
1072 MIB->getOperand(0).setSubReg(Mips::sub_32);
1073
1074 // Clear Divisor's kill flag.
1075 Divisor.setIsKill(false);
1076
1077 // We would normally delete the original instruction here but in this case
1078 // we only needed to inject an additional instruction rather than replace it.
1079
1080 return &MBB;
1081}
1082
1083MachineBasicBlock *
1084MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
1085 MachineBasicBlock *BB) const {
1086 switch (MI.getOpcode()) {
1087 default:
1088 llvm_unreachable("Unexpected instr type to insert")::llvm::llvm_unreachable_internal("Unexpected instr type to insert"
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/Target/Mips/MipsISelLowering.cpp"
, 1088)
;
1089 case Mips::ATOMIC_LOAD_ADD_I8:
1090 return emitAtomicBinaryPartword(MI, BB, 1, Mips::ADDu);
1091 case Mips::ATOMIC_LOAD_ADD_I16:
1092 return emitAtomicBinaryPartword(MI, BB, 2, Mips::ADDu);
1093 case Mips::ATOMIC_LOAD_ADD_I32:
1094 return emitAtomicBinary(MI, BB, 4, Mips::ADDu);
1095 case Mips::ATOMIC_LOAD_ADD_I64:
1096 return emitAtomicBinary(MI, BB, 8, Mips::DADDu);
1097
1098 case Mips::ATOMIC_LOAD_AND_I8:
1099 return emitAtomicBinaryPartword(MI, BB, 1, Mips::AND);
1100 case Mips::ATOMIC_LOAD_AND_I16:
1101 return emitAtomicBinaryPartword(MI, BB, 2, Mips::AND);
1102 case Mips::ATOMIC_LOAD_AND_I32:
1103 return emitAtomicBinary(MI, BB, 4, Mips::AND);
1104 case Mips::ATOMIC_LOAD_AND_I64:
1105 return emitAtomicBinary(MI, BB, 8, Mips::AND64);
1106
1107 case Mips::ATOMIC_LOAD_OR_I8:
1108 return emitAtomicBinaryPartword(MI, BB, 1, Mips::OR);
1109 case Mips::ATOMIC_LOAD_OR_I16:
1110 return emitAtomicBinaryPartword(MI, BB, 2, Mips::OR);
1111 case Mips::ATOMIC_LOAD_OR_I32:
1112 return emitAtomicBinary(MI, BB, 4, Mips::OR);
1113 case Mips::ATOMIC_LOAD_OR_I64:
1114 return emitAtomicBinary(MI, BB, 8, Mips::OR64);
1115
1116 case Mips::ATOMIC_LOAD_XOR_I8:
1117 return emitAtomicBinaryPartword(MI, BB, 1, Mips::XOR);
1118 case Mips::ATOMIC_LOAD_XOR_I16:
1119 return emitAtomicBinaryPartword(MI, BB, 2, Mips::XOR);
1120 case Mips::ATOMIC_LOAD_XOR_I32:
1121 return emitAtomicBinary(MI, BB, 4, Mips::XOR);
1122 case Mips::ATOMIC_LOAD_XOR_I64:
1123 return emitAtomicBinary(MI, BB, 8, Mips::XOR64);
1124
1125 case Mips::ATOMIC_LOAD_NAND_I8:
1126 return emitAtomicBinaryPartword(MI, BB, 1, 0, true);
1127 case Mips::ATOMIC_LOAD_NAND_I16:
1128 return emitAtomicBinaryPartword(MI, BB, 2, 0, true);
1129 case Mips::ATOMIC_LOAD_NAND_I32:
1130 return emitAtomicBinary(MI, BB, 4, 0, true);
1131 case Mips::ATOMIC_LOAD_NAND_I64:
1132 return emitAtomicBinary(MI, BB, 8, 0, true);
1133
1134 case Mips::ATOMIC_LOAD_SUB_I8:
1135 return emitAtomicBinaryPartword(MI, BB, 1, Mips::SUBu);
1136 case Mips::ATOMIC_LOAD_SUB_I16:
1137 return emitAtomicBinaryPartword(MI, BB, 2, Mips::SUBu);
1138 case Mips::ATOMIC_LOAD_SUB_I32:
1139 return emitAtomicBinary(MI, BB, 4, Mips::SUBu);
1140 case Mips::ATOMIC_LOAD_SUB_I64:
1141 return emitAtomicBinary(MI, BB, 8, Mips::DSUBu);
1142
1143 case Mips::ATOMIC_SWAP_I8:
1144 return emitAtomicBinaryPartword(MI, BB, 1, 0);
1145 case Mips::ATOMIC_SWAP_I16:
1146 return emitAtomicBinaryPartword(MI, BB, 2, 0);
1147 case Mips::ATOMIC_SWAP_I32:
1148 return emitAtomicBinary(MI, BB, 4, 0);
1149 case Mips::ATOMIC_SWAP_I64:
1150 return emitAtomicBinary(MI, BB, 8, 0);
1151
1152 case Mips::ATOMIC_CMP_SWAP_I8:
1153 return emitAtomicCmpSwapPartword(MI, BB, 1);
1154 case Mips::ATOMIC_CMP_SWAP_I16:
1155 return emitAtomicCmpSwapPartword(MI, BB, 2);
1156 case Mips::ATOMIC_CMP_SWAP_I32:
1157 return emitAtomicCmpSwap(MI, BB, 4);
1158 case Mips::ATOMIC_CMP_SWAP_I64:
1159 return emitAtomicCmpSwap(MI, BB, 8);
1160 case Mips::PseudoSDIV:
1161 case Mips::PseudoUDIV:
1162 case Mips::DIV:
1163 case Mips::DIVU:
1164 case Mips::MOD:
1165 case Mips::MODU:
1166 return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), false,
1167 false);
1168 case Mips::SDIV_MM_Pseudo:
1169 case Mips::UDIV_MM_Pseudo:
1170 case Mips::SDIV_MM:
1171 case Mips::UDIV_MM:
1172 case Mips::DIV_MMR6:
1173 case Mips::DIVU_MMR6:
1174 case Mips::MOD_MMR6:
1175 case Mips::MODU_MMR6:
1176 return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), false, true);
1177 case Mips::PseudoDSDIV:
1178 case Mips::PseudoDUDIV:
1179 case Mips::DDIV:
1180 case Mips::DDIVU:
1181 case Mips::DMOD:
1182 case Mips::DMODU:
1183 return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), true, false);
1184 case Mips::DDIV_MM64R6:
1185 case Mips::DDIVU_MM64R6:
1186 case Mips::DMOD_MM64R6:
1187 case Mips::DMODU_MM64R6:
1188 return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), true, true);
1189 case Mips::SEL_D:
1190 case Mips::SEL_D_MMR6:
1191 return emitSEL_D(MI, BB);
1192
1193 case Mips::PseudoSELECT_I:
1194 case Mips::PseudoSELECT_I64:
1195 case Mips::PseudoSELECT_S:
1196 case Mips::PseudoSELECT_D32:
1197 case Mips::PseudoSELECT_D64:
1198 return emitPseudoSELECT(MI, BB, false, Mips::BNE);
1199 case Mips::PseudoSELECTFP_F_I:
1200 case Mips::PseudoSELECTFP_F_I64:
1201 case Mips::PseudoSELECTFP_F_S:
1202 case Mips::PseudoSELECTFP_F_D32:
1203 case Mips::PseudoSELECTFP_F_D64:
1204 return emitPseudoSELECT(MI, BB, true, Mips::BC1F);
1205 case Mips::PseudoSELECTFP_T_I:
1206 case Mips::PseudoSELECTFP_T_I64:
1207 case Mips::PseudoSELECTFP_T_S:
1208 case Mips::PseudoSELECTFP_T_D32:
1209 case Mips::PseudoSELECTFP_T_D64:
1210 return emitPseudoSELECT(MI, BB, true, Mips::BC1T);
1211 }
1212}
1213
1214// This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and
1215// Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true)
1216MachineBasicBlock *MipsTargetLowering::emitAtomicBinary(MachineInstr &MI,
1217 MachineBasicBlock *BB,
1218 unsigned Size,
1219 unsigned BinOpcode,
1220 bool Nand) const {
1221 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicBinary.")(((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicBinary."
) ? static_cast<void> (0) : __assert_fail ("(Size == 4 || Size == 8) && \"Unsupported size for EmitAtomicBinary.\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/Target/Mips/MipsISelLowering.cpp"
, 1221, __PRETTY_FUNCTION__))
;
1222
1223 MachineFunction *MF = BB->getParent();
1224 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1225 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8));
1226 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
1227 const bool ArePtrs64bit = ABI.ArePtrs64bit();
1228 DebugLoc DL = MI.getDebugLoc();
1229 unsigned LL, SC, AND, NOR, ZERO, BEQ;
1230
1231 if (Size == 4) {
1232 if (isMicroMips) {
1233 LL = Mips::LL_MM;
1234 SC = Mips::SC_MM;
1235 } else {
1236 LL = Subtarget.hasMips32r6()
1237 ? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6)
1238 : (ArePtrs64bit ? Mips::LL64 : Mips::LL);
1239 SC = Subtarget.hasMips32r6()
1240 ? (ArePtrs64bit ? Mips::SC64_R6 : Mips::SC_R6)
1241 : (ArePtrs64bit ? Mips::SC64 : Mips::SC);
1242 }
1243
1244 AND = Mips::AND;
1245 NOR = Mips::NOR;
1246 ZERO = Mips::ZERO;
1247 BEQ = Mips::BEQ;
1248 } else {
1249 LL = Subtarget.hasMips64r6() ? Mips::LLD_R6 : Mips::LLD;
1250 SC = Subtarget.hasMips64r6() ? Mips::SCD_R6 : Mips::SCD;
1251 AND = Mips::AND64;
1252 NOR = Mips::NOR64;
1253 ZERO = Mips::ZERO_64;
1254 BEQ = Mips::BEQ64;
1255 }
1256
1257 unsigned OldVal = MI.getOperand(0).getReg();
1258 unsigned Ptr = MI.getOperand(1).getReg();
1259 unsigned Incr = MI.getOperand(2).getReg();
1260
1261 unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1262 unsigned AndRes = RegInfo.createVirtualRegister(RC);
1263 unsigned Success = RegInfo.createVirtualRegister(RC);
1264
1265 // insert new blocks after the current block
1266 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1267 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1268 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1269 MachineFunction::iterator It = ++BB->getIterator();
1270 MF->insert(It, loopMBB);
1271 MF->insert(It, exitMBB);
1272
1273 // Transfer the remainder of BB and its successor edges to exitMBB.
1274 exitMBB->splice(exitMBB->begin(), BB,
1275 std::next(MachineBasicBlock::iterator(MI)), BB->end());
1276 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1277
1278 // thisMBB:
1279 // ...
1280 // fallthrough --> loopMBB
1281 BB->addSuccessor(loopMBB);
1282 loopMBB->addSuccessor(loopMBB);
1283 loopMBB->addSuccessor(exitMBB);
1284
1285 // loopMBB:
1286 // ll oldval, 0(ptr)
1287 // <binop> storeval, oldval, incr
1288 // sc success, storeval, 0(ptr)
1289 // beq success, $0, loopMBB
1290 BB = loopMBB;
1291 BuildMI(BB, DL, TII->get(LL), OldVal).addReg(Ptr).addImm(0);
1292 if (Nand) {
1293 // and andres, oldval, incr
1294 // nor storeval, $0, andres
1295 BuildMI(BB, DL, TII->get(AND), AndRes).addReg(OldVal).addReg(Incr);
1296 BuildMI(BB, DL, TII->get(NOR), StoreVal).addReg(ZERO).addReg(AndRes);
1297 } else if (BinOpcode) {
1298 // <binop> storeval, oldval, incr
1299 BuildMI(BB, DL, TII->get(BinOpcode), StoreVal).addReg(OldVal).addReg(Incr);
1300 } else {
1301 StoreVal = Incr;
1302 }
1303 BuildMI(BB, DL, TII->get(SC), Success).addReg(StoreVal).addReg(Ptr).addImm(0);
1304 BuildMI(BB, DL, TII->get(BEQ)).addReg(Success).addReg(ZERO).addMBB(loopMBB);
1305
1306 MI.eraseFromParent(); // The instruction is gone now.
1307
1308 return exitMBB;
1309}
1310
1311MachineBasicBlock *MipsTargetLowering::emitSignExtendToI32InReg(
1312 MachineInstr &MI, MachineBasicBlock *BB, unsigned Size, unsigned DstReg,
1313 unsigned SrcReg) const {
1314 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
1315 const DebugLoc &DL = MI.getDebugLoc();
1316
1317 if (Subtarget.hasMips32r2() && Size == 1) {
1318 BuildMI(BB, DL, TII->get(Mips::SEB), DstReg).addReg(SrcReg);
1319 return BB;
1320 }
1321
1322 if (Subtarget.hasMips32r2() && Size == 2) {
1323 BuildMI(BB, DL, TII->get(Mips::SEH), DstReg).addReg(SrcReg);
1324 return BB;
1325 }
1326
1327 MachineFunction *MF = BB->getParent();
1328 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1329 const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1330 unsigned ScrReg = RegInfo.createVirtualRegister(RC);
1331
1332 assert(Size < 32)((Size < 32) ? static_cast<void> (0) : __assert_fail
("Size < 32", "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/Target/Mips/MipsISelLowering.cpp"
, 1332, __PRETTY_FUNCTION__))
;
1333 int64_t ShiftImm = 32 - (Size * 8);
1334
1335 BuildMI(BB, DL, TII->get(Mips::SLL), ScrReg).addReg(SrcReg).addImm(ShiftImm);
1336 BuildMI(BB, DL, TII->get(Mips::SRA), DstReg).addReg(ScrReg).addImm(ShiftImm);
1337
1338 return BB;
1339}
1340
1341MachineBasicBlock *MipsTargetLowering::emitAtomicBinaryPartword(
1342 MachineInstr &MI, MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode,
1343 bool Nand) const {
1344 assert((Size == 1 || Size == 2) &&(((Size == 1 || Size == 2) && "Unsupported size for EmitAtomicBinaryPartial."
) ? static_cast<void> (0) : __assert_fail ("(Size == 1 || Size == 2) && \"Unsupported size for EmitAtomicBinaryPartial.\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/Target/Mips/MipsISelLowering.cpp"
, 1345, __PRETTY_FUNCTION__))
1345 "Unsupported size for EmitAtomicBinaryPartial.")(((Size == 1 || Size == 2) && "Unsupported size for EmitAtomicBinaryPartial."
) ? static_cast<void> (0) : __assert_fail ("(Size == 1 || Size == 2) && \"Unsupported size for EmitAtomicBinaryPartial.\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/Target/Mips/MipsISelLowering.cpp"
, 1345, __PRETTY_FUNCTION__))
;
1346
1347 MachineFunction *MF = BB->getParent();
1348 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1349 const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1350 const bool ArePtrs64bit = ABI.ArePtrs64bit();
1351 const TargetRegisterClass *RCp =
1352 getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32);
1353 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
1354 DebugLoc DL = MI.getDebugLoc();
1355
1356 unsigned Dest = MI.getOperand(0).getReg();
1357 unsigned Ptr = MI.getOperand(1).getReg();
1358 unsigned Incr = MI.getOperand(2).getReg();
1359
1360 unsigned AlignedAddr = RegInfo.createVirtualRegister(RCp);
1361 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
1362 unsigned Mask = RegInfo.createVirtualRegister(RC);
1363 unsigned Mask2 = RegInfo.createVirtualRegister(RC);
1364 unsigned NewVal = RegInfo.createVirtualRegister(RC);
1365 unsigned OldVal = RegInfo.createVirtualRegister(RC);
1366 unsigned Incr2 = RegInfo.createVirtualRegister(RC);
1367 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RCp);
1368 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC);
1369 unsigned MaskUpper = RegInfo.createVirtualRegister(RC);
1370 unsigned AndRes = RegInfo.createVirtualRegister(RC);
1371 unsigned BinOpRes = RegInfo.createVirtualRegister(RC);
1372 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC);
1373 unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1374 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC);
1375 unsigned SrlRes = RegInfo.createVirtualRegister(RC);
1376 unsigned Success = RegInfo.createVirtualRegister(RC);
1377
1378 unsigned LL, SC;
1379 if (isMicroMips) {
1380 LL = Mips::LL_MM;
1381 SC = Mips::SC_MM;
1382 } else {
1383 LL = Subtarget.hasMips32r6() ? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6)
1384 : (ArePtrs64bit ? Mips::LL64 : Mips::LL);
1385 SC = Subtarget.hasMips32r6() ? (ArePtrs64bit ? Mips::SC64_R6 : Mips::SC_R6)
1386 : (ArePtrs64bit ? Mips::SC64 : Mips::SC);
1387 }
1388
1389 // insert new blocks after the current block
1390 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1391 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1392 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1393 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1394 MachineFunction::iterator It = ++BB->getIterator();
1395 MF->insert(It, loopMBB);
1396 MF->insert(It, sinkMBB);
1397 MF->insert(It, exitMBB);
1398
1399 // Transfer the remainder of BB and its successor edges to exitMBB.
1400 exitMBB->splice(exitMBB->begin(), BB,
1401 std::next(MachineBasicBlock::iterator(MI)), BB->end());
1402 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1403
1404 BB->addSuccessor(loopMBB);
1405 loopMBB->addSuccessor(loopMBB);
1406 loopMBB->addSuccessor(sinkMBB);
1407 sinkMBB->addSuccessor(exitMBB);
1408
1409 // thisMBB:
1410 // addiu masklsb2,$0,-4 # 0xfffffffc
1411 // and alignedaddr,ptr,masklsb2
1412 // andi ptrlsb2,ptr,3
1413 // sll shiftamt,ptrlsb2,3
1414 // ori maskupper,$0,255 # 0xff
1415 // sll mask,maskupper,shiftamt
1416 // nor mask2,$0,mask
1417 // sll incr2,incr,shiftamt
1418
1419 int64_t MaskImm = (Size == 1) ? 255 : 65535;
1420 BuildMI(BB, DL, TII->get(ABI.GetPtrAddiuOp()), MaskLSB2)
1421 .addReg(ABI.GetNullPtr()).addImm(-4);
1422 BuildMI(BB, DL, TII->get(ABI.GetPtrAndOp()), AlignedAddr)
1423 .addReg(Ptr).addReg(MaskLSB2);
1424 BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2)
1425 .addReg(Ptr, 0, ArePtrs64bit ? Mips::sub_32 : 0).addImm(3);
1426 if (Subtarget.isLittle()) {
1427 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1428 } else {
1429 unsigned Off = RegInfo.createVirtualRegister(RC);
1430 BuildMI(BB, DL, TII->get(Mips::XORi), Off)
1431 .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2);
1432 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
1433 }
1434 BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper)
1435 .addReg(Mips::ZERO).addImm(MaskImm);
1436 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask)
1437 .addReg(MaskUpper).addReg(ShiftAmt);
1438 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
1439 BuildMI(BB, DL, TII->get(Mips::SLLV), Incr2).addReg(Incr).addReg(ShiftAmt);
1440
1441 // atomic.load.binop
1442 // loopMBB:
1443 // ll oldval,0(alignedaddr)
1444 // binop binopres,oldval,incr2
1445 // and newval,binopres,mask
1446 // and maskedoldval0,oldval,mask2
1447 // or storeval,maskedoldval0,newval
1448 // sc success,storeval,0(alignedaddr)
1449 // beq success,$0,loopMBB
1450
1451 // atomic.swap
1452 // loopMBB:
1453 // ll oldval,0(alignedaddr)
1454 // and newval,incr2,mask
1455 // and maskedoldval0,oldval,mask2
1456 // or storeval,maskedoldval0,newval
1457 // sc success,storeval,0(alignedaddr)
1458 // beq success,$0,loopMBB
1459
1460 BB = loopMBB;
1461 BuildMI(BB, DL, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0);
1462 if (Nand) {
1463 // and andres, oldval, incr2
1464 // nor binopres, $0, andres
1465 // and newval, binopres, mask
1466 BuildMI(BB, DL, TII->get(Mips::AND), AndRes).addReg(OldVal).addReg(Incr2);
1467 BuildMI(BB, DL, TII->get(Mips::NOR), BinOpRes)
1468 .addReg(Mips::ZERO).addReg(AndRes);
1469 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask);
1470 } else if (BinOpcode) {
1471 // <binop> binopres, oldval, incr2
1472 // and newval, binopres, mask
1473 BuildMI(BB, DL, TII->get(BinOpcode), BinOpRes).addReg(OldVal).addReg(Incr2);
1474 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask);
1475 } else { // atomic.swap
1476 // and newval, incr2, mask
1477 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(Incr2).addReg(Mask);
1478 }
1479
1480 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal0)
1481 .addReg(OldVal).addReg(Mask2);
1482 BuildMI(BB, DL, TII->get(Mips::OR), StoreVal)
1483 .addReg(MaskedOldVal0).addReg(NewVal);
1484 BuildMI(BB, DL, TII->get(SC), Success)
1485 .addReg(StoreVal).addReg(AlignedAddr).addImm(0);
1486 BuildMI(BB, DL, TII->get(Mips::BEQ))
1487 .addReg(Success).addReg(Mips::ZERO).addMBB(loopMBB);
1488
1489 // sinkMBB:
1490 // and maskedoldval1,oldval,mask
1491 // srl srlres,maskedoldval1,shiftamt
1492 // sign_extend dest,srlres
1493 BB = sinkMBB;
1494
1495 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal1)
1496 .addReg(OldVal).addReg(Mask);
1497 BuildMI(BB, DL, TII->get(Mips::SRLV), SrlRes)
1498 .addReg(MaskedOldVal1).addReg(ShiftAmt);
1499 BB = emitSignExtendToI32InReg(MI, BB, Size, Dest, SrlRes);
1500
1501 MI.eraseFromParent(); // The instruction is gone now.
1502
1503 return exitMBB;
1504}
1505
1506MachineBasicBlock *MipsTargetLowering::emitAtomicCmpSwap(MachineInstr &MI,
1507 MachineBasicBlock *BB,
1508 unsigned Size) const {
1509 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicCmpSwap.")(((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicCmpSwap."
) ? static_cast<void> (0) : __assert_fail ("(Size == 4 || Size == 8) && \"Unsupported size for EmitAtomicCmpSwap.\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/Target/Mips/MipsISelLowering.cpp"
, 1509, __PRETTY_FUNCTION__))
;
1510
1511 MachineFunction *MF = BB->getParent();
1512 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1513 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8));
1514 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
1515 const bool ArePtrs64bit = ABI.ArePtrs64bit();
1516 DebugLoc DL = MI.getDebugLoc();
1517 unsigned LL, SC, ZERO, BNE, BEQ;
1518
1519 if (Size == 4) {
1520 if (isMicroMips) {
1521 LL = Mips::LL_MM;
1522 SC = Mips::SC_MM;
1523 } else {
1524 LL = Subtarget.hasMips32r6()
1525 ? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6)
1526 : (ArePtrs64bit ? Mips::LL64 : Mips::LL);
1527 SC = Subtarget.hasMips32r6()
1528 ? (ArePtrs64bit ? Mips::SC64_R6 : Mips::SC_R6)
1529 : (ArePtrs64bit ? Mips::SC64 : Mips::SC);
1530 }
1531
1532 ZERO = Mips::ZERO;
1533 BNE = Mips::BNE;
1534 BEQ = Mips::BEQ;
1535 } else {
1536 LL = Subtarget.hasMips64r6() ? Mips::LLD_R6 : Mips::LLD;
1537 SC = Subtarget.hasMips64r6() ? Mips::SCD_R6 : Mips::SCD;
1538 ZERO = Mips::ZERO_64;
1539 BNE = Mips::BNE64;
1540 BEQ = Mips::BEQ64;
1541 }
1542
1543 unsigned Dest = MI.getOperand(0).getReg();
1544 unsigned Ptr = MI.getOperand(1).getReg();
1545 unsigned OldVal = MI.getOperand(2).getReg();
1546 unsigned NewVal = MI.getOperand(3).getReg();
1547
1548 unsigned Success = RegInfo.createVirtualRegister(RC);
1549
1550 // insert new blocks after the current block
1551 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1552 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1553 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1554 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1555 MachineFunction::iterator It = ++BB->getIterator();
1556 MF->insert(It, loop1MBB);
1557 MF->insert(It, loop2MBB);
1558 MF->insert(It, exitMBB);
1559
1560 // Transfer the remainder of BB and its successor edges to exitMBB.
1561 exitMBB->splice(exitMBB->begin(), BB,
1562 std::next(MachineBasicBlock::iterator(MI)), BB->end());
1563 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1564
1565 // thisMBB:
1566 // ...
1567 // fallthrough --> loop1MBB
1568 BB->addSuccessor(loop1MBB);
1569 loop1MBB->addSuccessor(exitMBB);
1570 loop1MBB->addSuccessor(loop2MBB);
1571 loop2MBB->addSuccessor(loop1MBB);
1572 loop2MBB->addSuccessor(exitMBB);
1573
1574 // loop1MBB:
1575 // ll dest, 0(ptr)
1576 // bne dest, oldval, exitMBB
1577 BB = loop1MBB;
1578 BuildMI(BB, DL, TII->get(LL), Dest).addReg(Ptr).addImm(0);
1579 BuildMI(BB, DL, TII->get(BNE))
1580 .addReg(Dest).addReg(OldVal).addMBB(exitMBB);
1581
1582 // loop2MBB:
1583 // sc success, newval, 0(ptr)
1584 // beq success, $0, loop1MBB
1585 BB = loop2MBB;
1586 BuildMI(BB, DL, TII->get(SC), Success)
1587 .addReg(NewVal).addReg(Ptr).addImm(0);
1588 BuildMI(BB, DL, TII->get(BEQ))
1589 .addReg(Success).addReg(ZERO).addMBB(loop1MBB);
1590
1591 MI.eraseFromParent(); // The instruction is gone now.
1592
1593 return exitMBB;
1594}
1595
1596MachineBasicBlock *MipsTargetLowering::emitAtomicCmpSwapPartword(
1597 MachineInstr &MI, MachineBasicBlock *BB, unsigned Size) const {
1598 assert((Size == 1 || Size == 2) &&(((Size == 1 || Size == 2) && "Unsupported size for EmitAtomicCmpSwapPartial."
) ? static_cast<void> (0) : __assert_fail ("(Size == 1 || Size == 2) && \"Unsupported size for EmitAtomicCmpSwapPartial.\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/Target/Mips/MipsISelLowering.cpp"
, 1599, __PRETTY_FUNCTION__))
1599 "Unsupported size for EmitAtomicCmpSwapPartial.")(((Size == 1 || Size == 2) && "Unsupported size for EmitAtomicCmpSwapPartial."
) ? static_cast<void> (0) : __assert_fail ("(Size == 1 || Size == 2) && \"Unsupported size for EmitAtomicCmpSwapPartial.\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/Target/Mips/MipsISelLowering.cpp"
, 1599, __PRETTY_FUNCTION__))
;
1600
1601 MachineFunction *MF = BB->getParent();
1602 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1603 const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1604 const bool ArePtrs64bit = ABI.ArePtrs64bit();
1605 const TargetRegisterClass *RCp =
1606 getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32);
1607 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
1608 DebugLoc DL = MI.getDebugLoc();
1609
1610 unsigned Dest = MI.getOperand(0).getReg();
1611 unsigned Ptr = MI.getOperand(1).getReg();
1612 unsigned CmpVal = MI.getOperand(2).getReg();
1613 unsigned NewVal = MI.getOperand(3).getReg();
1614
1615 unsigned AlignedAddr = RegInfo.createVirtualRegister(RCp);
1616 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
1617 unsigned Mask = RegInfo.createVirtualRegister(RC);
1618 unsigned Mask2 = RegInfo.createVirtualRegister(RC);
1619 unsigned ShiftedCmpVal = RegInfo.createVirtualRegister(RC);
1620 unsigned OldVal = RegInfo.createVirtualRegister(RC);
1621 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC);
1622 unsigned ShiftedNewVal = RegInfo.createVirtualRegister(RC);
1623 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RCp);
1624 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC);
1625 unsigned MaskUpper = RegInfo.createVirtualRegister(RC);
1626 unsigned MaskedCmpVal = RegInfo.createVirtualRegister(RC);
1627 unsigned MaskedNewVal = RegInfo.createVirtualRegister(RC);
1628 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC);
1629 unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1630 unsigned SrlRes = RegInfo.createVirtualRegister(RC);
1631 unsigned Success = RegInfo.createVirtualRegister(RC);
1632 unsigned LL, SC;
1633
1634 if (isMicroMips) {
1635 LL = Mips::LL_MM;
1636 SC = Mips::SC_MM;
1637 } else {
1638 LL = Subtarget.hasMips32r6() ? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6)
1639 : (ArePtrs64bit ? Mips::LL64 : Mips::LL);
1640 SC = Subtarget.hasMips32r6() ? (ArePtrs64bit ? Mips::SC64_R6 : Mips::SC_R6)
1641 : (ArePtrs64bit ? Mips::SC64 : Mips::SC);
1642 }
1643
1644 // insert new blocks after the current block
1645 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1646 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1647 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1648 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1649 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1650 MachineFunction::iterator It = ++BB->getIterator();
1651 MF->insert(It, loop1MBB);
1652 MF->insert(It, loop2MBB);
1653 MF->insert(It, sinkMBB);
1654 MF->insert(It, exitMBB);
1655
1656 // Transfer the remainder of BB and its successor edges to exitMBB.
1657 exitMBB->splice(exitMBB->begin(), BB,
1658 std::next(MachineBasicBlock::iterator(MI)), BB->end());
1659 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1660
1661 BB->addSuccessor(loop1MBB);
1662 loop1MBB->addSuccessor(sinkMBB);
1663 loop1MBB->addSuccessor(loop2MBB);
1664 loop2MBB->addSuccessor(loop1MBB);
1665 loop2MBB->addSuccessor(sinkMBB);
1666 sinkMBB->addSuccessor(exitMBB);
1667
1668 // FIXME: computation of newval2 can be moved to loop2MBB.
1669 // thisMBB:
1670 // addiu masklsb2,$0,-4 # 0xfffffffc
1671 // and alignedaddr,ptr,masklsb2
1672 // andi ptrlsb2,ptr,3
1673 // xori ptrlsb2,ptrlsb2,3 # Only for BE
1674 // sll shiftamt,ptrlsb2,3
1675 // ori maskupper,$0,255 # 0xff
1676 // sll mask,maskupper,shiftamt
1677 // nor mask2,$0,mask
1678 // andi maskedcmpval,cmpval,255
1679 // sll shiftedcmpval,maskedcmpval,shiftamt
1680 // andi maskednewval,newval,255
1681 // sll shiftednewval,maskednewval,shiftamt
1682 int64_t MaskImm = (Size == 1) ? 255 : 65535;
1683 BuildMI(BB, DL, TII->get(ArePtrs64bit ? Mips::DADDiu : Mips::ADDiu), MaskLSB2)
1684 .addReg(ABI.GetNullPtr()).addImm(-4);
1685 BuildMI(BB, DL, TII->get(ArePtrs64bit ? Mips::AND64 : Mips::AND), AlignedAddr)
1686 .addReg(Ptr).addReg(MaskLSB2);
1687 BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2)
1688 .addReg(Ptr, 0, ArePtrs64bit ? Mips::sub_32 : 0).addImm(3);
1689 if (Subtarget.isLittle()) {
1690 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1691 } else {
1692 unsigned Off = RegInfo.createVirtualRegister(RC);
1693 BuildMI(BB, DL, TII->get(Mips::XORi), Off)
1694 .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2);
1695 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
1696 }
1697 BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper)
1698 .addReg(Mips::ZERO).addImm(MaskImm);
1699 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask)
1700 .addReg(MaskUpper).addReg(ShiftAmt);
1701 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
1702 BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedCmpVal)
1703 .addReg(CmpVal).addImm(MaskImm);
1704 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedCmpVal)
1705 .addReg(MaskedCmpVal).addReg(ShiftAmt);
1706 BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedNewVal)
1707 .addReg(NewVal).addImm(MaskImm);
1708 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedNewVal)
1709 .addReg(MaskedNewVal).addReg(ShiftAmt);
1710
1711 // loop1MBB:
1712 // ll oldval,0(alginedaddr)
1713 // and maskedoldval0,oldval,mask
1714 // bne maskedoldval0,shiftedcmpval,sinkMBB
1715 BB = loop1MBB;
1716 BuildMI(BB, DL, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0);
1717 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal0)
1718 .addReg(OldVal).addReg(Mask);
1719 BuildMI(BB, DL, TII->get(Mips::BNE))
1720 .addReg(MaskedOldVal0).addReg(ShiftedCmpVal).addMBB(sinkMBB);
1721
1722 // loop2MBB:
1723 // and maskedoldval1,oldval,mask2
1724 // or storeval,maskedoldval1,shiftednewval
1725 // sc success,storeval,0(alignedaddr)
1726 // beq success,$0,loop1MBB
1727 BB = loop2MBB;
1728 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal1)
1729 .addReg(OldVal).addReg(Mask2);
1730 BuildMI(BB, DL, TII->get(Mips::OR), StoreVal)
1731 .addReg(MaskedOldVal1).addReg(ShiftedNewVal);
1732 BuildMI(BB, DL, TII->get(SC), Success)
1733 .addReg(StoreVal).addReg(AlignedAddr).addImm(0);
1734 BuildMI(BB, DL, TII->get(Mips::BEQ))
1735 .addReg(Success).addReg(Mips::ZERO).addMBB(loop1MBB);
1736
1737 // sinkMBB:
1738 // srl srlres,maskedoldval0,shiftamt
1739 // sign_extend dest,srlres
1740 BB = sinkMBB;
1741
1742 BuildMI(BB, DL, TII->get(Mips::SRLV), SrlRes)
1743 .addReg(MaskedOldVal0).addReg(ShiftAmt);
1744 BB = emitSignExtendToI32InReg(MI, BB, Size, Dest, SrlRes);
Value stored to 'BB' is never read
1745
1746 MI.eraseFromParent(); // The instruction is gone now.
1747
1748 return exitMBB;
1749}
1750
1751MachineBasicBlock *MipsTargetLowering::emitSEL_D(MachineInstr &MI,
1752 MachineBasicBlock *BB) const {
1753 MachineFunction *MF = BB->getParent();
1754 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
1755 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
1756 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1757 DebugLoc DL = MI.getDebugLoc();
1758 MachineBasicBlock::iterator II(MI);
1759
1760 unsigned Fc = MI.getOperand(1).getReg();
1761 const auto &FGR64RegClass = TRI->getRegClass(Mips::FGR64RegClassID);
1762
1763 unsigned Fc2 = RegInfo.createVirtualRegister(FGR64RegClass);
1764
1765 BuildMI(*BB, II, DL, TII->get(Mips::SUBREG_TO_REG), Fc2)
1766 .addImm(0)
1767 .addReg(Fc)
1768 .addImm(Mips::sub_lo);
1769
1770 // We don't erase the original instruction, we just replace the condition
1771 // register with the 64-bit super-register.
1772 MI.getOperand(1).setReg(Fc2);
1773
1774 return BB;
1775}
1776
1777SDValue MipsTargetLowering::lowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
1778 // The first operand is the chain, the second is the condition, the third is
1779 // the block to branch to if the condition is true.
1780 SDValue Chain = Op.getOperand(0);
1781 SDValue Dest = Op.getOperand(2);
1782 SDLoc DL(Op);
1783
1784 assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6())((!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6(
)) ? static_cast<void> (0) : __assert_fail ("!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6()"
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/Target/Mips/MipsISelLowering.cpp"
, 1784, __PRETTY_FUNCTION__))
;
1785 SDValue CondRes = createFPCmp(DAG, Op.getOperand(1));
1786
1787 // Return if flag is not set by a floating point comparison.
1788 if (CondRes.getOpcode() != MipsISD::FPCmp)
1789 return Op;
1790
1791 SDValue CCNode = CondRes.getOperand(2);
1792 Mips::CondCode CC =
1793 (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue();
1794 unsigned Opc = invertFPCondCodeUser(CC) ? Mips::BRANCH_F : Mips::BRANCH_T;
1795 SDValue BrCode = DAG.getConstant(Opc, DL, MVT::i32);
1796 SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32);
1797 return DAG.getNode(MipsISD::FPBrcond, DL, Op.getValueType(), Chain, BrCode,
1798 FCC0, Dest, CondRes);
1799}
1800
1801SDValue MipsTargetLowering::
1802lowerSELECT(SDValue Op, SelectionDAG &DAG) const
1803{
1804 assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6())((!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6(
)) ? static_cast<void> (0) : __assert_fail ("!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6()"
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/Target/Mips/MipsISelLowering.cpp"
, 1804, __PRETTY_FUNCTION__))
;
1805 SDValue Cond = createFPCmp(DAG, Op.getOperand(0));
1806
1807 // Return if flag is not set by a floating point comparison.
1808 if (Cond.getOpcode() != MipsISD::FPCmp)
1809 return Op;
1810
1811 return createCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2),
1812 SDLoc(Op));
1813}
1814
1815SDValue MipsTargetLowering::lowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1816 assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6())((!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6(
)) ? static_cast<void> (0) : __assert_fail ("!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6()"
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/Target/Mips/MipsISelLowering.cpp"
, 1816, __PRETTY_FUNCTION__))
;
1817 SDValue Cond = createFPCmp(DAG, Op);
1818
1819 assert(Cond.getOpcode() == MipsISD::FPCmp &&((Cond.getOpcode() == MipsISD::FPCmp && "Floating point operand expected."
) ? static_cast<void> (0) : __assert_fail ("Cond.getOpcode() == MipsISD::FPCmp && \"Floating point operand expected.\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/Target/Mips/MipsISelLowering.cpp"
, 1820, __PRETTY_FUNCTION__))
1820 "Floating point operand expected.")((Cond.getOpcode() == MipsISD::FPCmp && "Floating point operand expected."
) ? static_cast<void> (0) : __assert_fail ("Cond.getOpcode() == MipsISD::FPCmp && \"Floating point operand expected.\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/Target/Mips/MipsISelLowering.cpp"
, 1820, __PRETTY_FUNCTION__))
;
1821
1822 SDLoc DL(Op);
1823 SDValue True = DAG.getConstant(1, DL, MVT::i32);
1824 SDValue False = DAG.getConstant(0, DL, MVT::i32);
1825
1826 return createCMovFP(DAG, Cond, True, False, DL);
1827}
1828
1829SDValue MipsTargetLowering::lowerGlobalAddress(SDValue Op,
1830 SelectionDAG &DAG) const {
1831 EVT Ty = Op.getValueType();
1832 GlobalAddressSDNode *N = cast<GlobalAddressSDNode>(Op);
1833 const GlobalValue *GV = N->getGlobal();
1834
1835 if (!isPositionIndependent()) {
1836 const MipsTargetObjectFile *TLOF =
1837 static_cast<const MipsTargetObjectFile *>(
1838 getTargetMachine().getObjFileLowering());
1839 const GlobalObject *GO = GV->getBaseObject();
1840 if (GO && TLOF->IsGlobalInSmallSection(GO, getTargetMachine()))
1841 // %gp_rel relocation
1842 return getAddrGPRel(N, SDLoc(N), Ty, DAG);
1843
1844 // %hi/%lo relocation
1845 return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG)
1846 // %highest/%higher/%hi/%lo relocation
1847 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG);
1848 }
1849
1850 // Every other architecture would use shouldAssumeDSOLocal in here, but
1851 // mips is special.
1852 // * In PIC code mips requires got loads even for local statics!
1853 // * To save on got entries, for local statics the got entry contains the
1854 // page and an additional add instruction takes care of the low bits.
1855 // * It is legal to access a hidden symbol with a non hidden undefined,
1856 // so one cannot guarantee that all access to a hidden symbol will know
1857 // it is hidden.
1858 // * Mips linkers don't support creating a page and a full got entry for
1859 // the same symbol.
1860 // * Given all that, we have to use a full got entry for hidden symbols :-(
1861 if (GV->hasLocalLinkage())
1862 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64());
1863
1864 if (LargeGOT)
1865 return getAddrGlobalLargeGOT(
1866 N, SDLoc(N), Ty, DAG, MipsII::MO_GOT_HI16, MipsII::MO_GOT_LO16,
1867 DAG.getEntryNode(),
1868 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
1869
1870 return getAddrGlobal(
1871 N, SDLoc(N), Ty, DAG,
1872 (ABI.IsN32() || ABI.IsN64()) ? MipsII::MO_GOT_DISP : MipsII::MO_GOT,
1873 DAG.getEntryNode(), MachinePointerInfo::getGOT(DAG.getMachineFunction()));
1874}
1875
1876SDValue MipsTargetLowering::lowerBlockAddress(SDValue Op,
1877 SelectionDAG &DAG) const {
1878 BlockAddressSDNode *N = cast<BlockAddressSDNode>(Op);
1879 EVT Ty = Op.getValueType();
1880
1881 if (!isPositionIndependent())
1882 return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG)
1883 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG);
1884
1885 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64());
1886}
1887
1888SDValue MipsTargetLowering::
1889lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
1890{
1891 // If the relocation model is PIC, use the General Dynamic TLS Model or
1892 // Local Dynamic TLS model, otherwise use the Initial Exec or
1893 // Local Exec TLS Model.
1894
1895 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1896 if (DAG.getTarget().Options.EmulatedTLS)
1897 return LowerToTLSEmulatedModel(GA, DAG);
1898
1899 SDLoc DL(GA);
1900 const GlobalValue *GV = GA->getGlobal();
1901 EVT PtrVT = getPointerTy(DAG.getDataLayout());
1902
1903 TLSModel::Model model = getTargetMachine().getTLSModel(GV);
1904
1905 if (model == TLSModel::GeneralDynamic || model == TLSModel::LocalDynamic) {
1906 // General Dynamic and Local Dynamic TLS Model.
1907 unsigned Flag = (model == TLSModel::LocalDynamic) ? MipsII::MO_TLSLDM
1908 : MipsII::MO_TLSGD;
1909
1910 SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, Flag);
1911 SDValue Argument = DAG.getNode(MipsISD::Wrapper, DL, PtrVT,
1912 getGlobalReg(DAG, PtrVT), TGA);
1913 unsigned PtrSize = PtrVT.getSizeInBits();
1914 IntegerType *PtrTy = Type::getIntNTy(*DAG.getContext(), PtrSize);
1915
1916 SDValue TlsGetAddr = DAG.getExternalSymbol("__tls_get_addr", PtrVT);
1917
1918 ArgListTy Args;
1919 ArgListEntry Entry;
1920 Entry.Node = Argument;
1921 Entry.Ty = PtrTy;
1922 Args.push_back(Entry);
1923
1924 TargetLowering::CallLoweringInfo CLI(DAG);
1925 CLI.setDebugLoc(DL)
1926 .setChain(DAG.getEntryNode())
1927 .setLibCallee(CallingConv::C, PtrTy, TlsGetAddr, std::move(Args));
1928 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
1929
1930 SDValue Ret = CallResult.first;
1931
1932 if (model != TLSModel::LocalDynamic)
1933 return Ret;
1934
1935 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
1936 MipsII::MO_DTPREL_HI);
1937 SDValue Hi = DAG.getNode(MipsISD::Hi, DL, PtrVT, TGAHi);
1938 SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
1939 MipsII::MO_DTPREL_LO);
1940 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo);
1941 SDValue Add = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Ret);
1942 return DAG.getNode(ISD::ADD, DL, PtrVT, Add, Lo);
1943 }
1944
1945 SDValue Offset;
1946 if (model == TLSModel::InitialExec) {
1947 // Initial Exec TLS Model
1948 SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
1949 MipsII::MO_GOTTPREL);
1950 TGA = DAG.getNode(MipsISD::Wrapper, DL, PtrVT, getGlobalReg(DAG, PtrVT),
1951 TGA);
1952 Offset =
1953 DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), TGA, MachinePointerInfo());
1954 } else {
1955 // Local Exec TLS Model
1956 assert(model == TLSModel::LocalExec)((model == TLSModel::LocalExec) ? static_cast<void> (0)
: __assert_fail ("model == TLSModel::LocalExec", "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/Target/Mips/MipsISelLowering.cpp"
, 1956, __PRETTY_FUNCTION__))
;
1957 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
1958 MipsII::MO_TPREL_HI);
1959 SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
1960 MipsII::MO_TPREL_LO);
1961 SDValue Hi = DAG.getNode(MipsISD::Hi, DL, PtrVT, TGAHi);
1962 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo);
1963 Offset = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1964 }
1965
1966 SDValue ThreadPointer = DAG.getNode(MipsISD::ThreadPointer, DL, PtrVT);
1967 return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadPointer, Offset);
1968}
1969
1970SDValue MipsTargetLowering::
1971lowerJumpTable(SDValue Op, SelectionDAG &DAG) const
1972{
1973 JumpTableSDNode *N = cast<JumpTableSDNode>(Op);
1974 EVT Ty = Op.getValueType();
1975
1976 if (!isPositionIndependent())
1977 return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG)
1978 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG);
1979
1980 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64());
1981}
1982
1983SDValue MipsTargetLowering::
1984lowerConstantPool(SDValue Op, SelectionDAG &DAG) const
1985{
1986 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
1987 EVT Ty = Op.getValueType();
1988
1989 if (!isPositionIndependent()) {
1990 const MipsTargetObjectFile *TLOF =
1991 static_cast<const MipsTargetObjectFile *>(
1992 getTargetMachine().getObjFileLowering());
1993
1994 if (TLOF->IsConstantInSmallSection(DAG.getDataLayout(), N->getConstVal(),
1995 getTargetMachine()))
1996 // %gp_rel relocation
1997 return getAddrGPRel(N, SDLoc(N), Ty, DAG);
1998
1999 return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG)
2000 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG);
2001 }
2002
2003 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64());
2004}
2005
2006SDValue MipsTargetLowering::lowerVASTART(SDValue Op, SelectionDAG &DAG) const {
2007 MachineFunction &MF = DAG.getMachineFunction();
2008 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
2009
2010 SDLoc DL(Op);
2011 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
2012 getPointerTy(MF.getDataLayout()));
2013
2014 // vastart just stores the address of the VarArgsFrameIndex slot into the
2015 // memory location argument.
2016 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2017 return DAG.getStore(Op.getOperand(0), DL, FI, Op.getOperand(1),
2018 MachinePointerInfo(SV));
2019}
2020
2021SDValue MipsTargetLowering::lowerVAARG(SDValue Op, SelectionDAG &DAG) const {
2022 SDNode *Node = Op.getNode();
2023 EVT VT = Node->getValueType(0);
2024 SDValue Chain = Node->getOperand(0);
2025 SDValue VAListPtr = Node->getOperand(1);
2026 unsigned Align = Node->getConstantOperandVal(3);
2027 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
2028 SDLoc DL(Node);
2029 unsigned ArgSlotSizeInBytes = (ABI.IsN32() || ABI.IsN64()) ? 8 : 4;
2030
2031 SDValue VAListLoad = DAG.getLoad(getPointerTy(DAG.getDataLayout()), DL, Chain,
2032 VAListPtr, MachinePointerInfo(SV));
2033 SDValue VAList = VAListLoad;
2034
2035 // Re-align the pointer if necessary.
2036 // It should only ever be necessary for 64-bit types on O32 since the minimum
2037 // argument alignment is the same as the maximum type alignment for N32/N64.
2038 //
2039 // FIXME: We currently align too often. The code generator doesn't notice
2040 // when the pointer is still aligned from the last va_arg (or pair of
2041 // va_args for the i64 on O32 case).
2042 if (Align > getMinStackArgumentAlignment()) {
2043 assert(((Align & (Align-1)) == 0) && "Expected Align to be a power of 2")((((Align & (Align-1)) == 0) && "Expected Align to be a power of 2"
) ? static_cast<void> (0) : __assert_fail ("((Align & (Align-1)) == 0) && \"Expected Align to be a power of 2\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/Target/Mips/MipsISelLowering.cpp"
, 2043, __PRETTY_FUNCTION__))
;
2044
2045 VAList = DAG.getNode(ISD::ADD, DL, VAList.getValueType(), VAList,
2046 DAG.getConstant(Align - 1, DL, VAList.getValueType()));
2047
2048 VAList = DAG.getNode(ISD::AND, DL, VAList.getValueType(), VAList,
2049 DAG.getConstant(-(int64_t)Align, DL,
2050 VAList.getValueType()));
2051 }
2052
2053 // Increment the pointer, VAList, to the next vaarg.
2054 auto &TD = DAG.getDataLayout();
2055 unsigned ArgSizeInBytes =
2056 TD.getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext()));
2057 SDValue Tmp3 =
2058 DAG.getNode(ISD::ADD, DL, VAList.getValueType(), VAList,
2059 DAG.getConstant(alignTo(ArgSizeInBytes, ArgSlotSizeInBytes),
2060 DL, VAList.getValueType()));
2061 // Store the incremented VAList to the legalized pointer
2062 Chain = DAG.getStore(VAListLoad.getValue(1), DL, Tmp3, VAListPtr,
2063 MachinePointerInfo(SV));
2064
2065 // In big-endian mode we must adjust the pointer when the load size is smaller
2066 // than the argument slot size. We must also reduce the known alignment to
2067 // match. For example in the N64 ABI, we must add 4 bytes to the offset to get
2068 // the correct half of the slot, and reduce the alignment from 8 (slot
2069 // alignment) down to 4 (type alignment).
2070 if (!Subtarget.isLittle() && ArgSizeInBytes < ArgSlotSizeInBytes) {
2071 unsigned Adjustment = ArgSlotSizeInBytes - ArgSizeInBytes;
2072 VAList = DAG.getNode(ISD::ADD, DL, VAListPtr.getValueType(), VAList,
2073 DAG.getIntPtrConstant(Adjustment, DL));
2074 }
2075 // Load the actual argument out of the pointer VAList
2076 return DAG.getLoad(VT, DL, Chain, VAList, MachinePointerInfo());
2077}
2078
2079static SDValue lowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG,
2080 bool HasExtractInsert) {
2081 EVT TyX = Op.getOperand(0).getValueType();
2082 EVT TyY = Op.getOperand(1).getValueType();
2083 SDLoc DL(Op);
2084 SDValue Const1 = DAG.getConstant(1, DL, MVT::i32);
2085 SDValue Const31 = DAG.getConstant(31, DL, MVT::i32);
2086 SDValue Res;
2087
2088 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it
2089 // to i32.
2090 SDValue X = (TyX == MVT::f32) ?
2091 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) :
2092 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0),
2093 Const1);
2094 SDValue Y = (TyY == MVT::f32) ?
2095 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(1)) :
2096 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(1),
2097 Const1);
2098
2099 if (HasExtractInsert) {
2100 // ext E, Y, 31, 1 ; extract bit31 of Y
2101 // ins X, E, 31, 1 ; insert extracted bit at bit31 of X
2102 SDValue E = DAG.getNode(MipsISD::Ext, DL, MVT::i32, Y, Const31, Const1);
2103 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, E, Const31, Const1, X);
2104 } else {
2105 // sll SllX, X, 1
2106 // srl SrlX, SllX, 1
2107 // srl SrlY, Y, 31
2108 // sll SllY, SrlX, 31
2109 // or Or, SrlX, SllY
2110 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1);
2111 SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1);
2112 SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31);
2113 SDValue SllY = DAG.getNode(ISD::SHL, DL, MVT::i32, SrlY, Const31);
2114 Res = DAG.getNode(ISD::OR, DL, MVT::i32, SrlX, SllY);
2115 }
2116
2117 if (TyX == MVT::f32)
2118 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Res);
2119
2120 SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
2121 Op.getOperand(0),
2122 DAG.getConstant(0, DL, MVT::i32));
2123 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res);
2124}
2125
2126static SDValue lowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG,
2127 bool HasExtractInsert) {
2128 unsigned WidthX = Op.getOperand(0).getValueSizeInBits();
2129 unsigned WidthY = Op.getOperand(1).getValueSizeInBits();
2130 EVT TyX = MVT::getIntegerVT(WidthX), TyY = MVT::getIntegerVT(WidthY);
2131 SDLoc DL(Op);
2132 SDValue Const1 = DAG.getConstant(1, DL, MVT::i32);
2133
2134 // Bitcast to integer nodes.
2135 SDValue X = DAG.getNode(ISD::BITCAST, DL, TyX, Op.getOperand(0));
2136 SDValue Y = DAG.getNode(ISD::BITCAST, DL, TyY, Op.getOperand(1));
2137
2138 if (HasExtractInsert) {
2139 // ext E, Y, width(Y) - 1, 1 ; extract bit width(Y)-1 of Y
2140 // ins X, E, width(X) - 1, 1 ; insert extracted bit at bit width(X)-1 of X
2141 SDValue E = DAG.getNode(MipsISD::Ext, DL, TyY, Y,
2142 DAG.getConstant(WidthY - 1, DL, MVT::i32), Const1);
2143
2144 if (WidthX > WidthY)
2145 E = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, E);
2146 else if (WidthY > WidthX)
2147 E = DAG.getNode(ISD::TRUNCATE, DL, TyX, E);
2148
2149 SDValue I = DAG.getNode(MipsISD::Ins, DL, TyX, E,
2150 DAG.getConstant(WidthX - 1, DL, MVT::i32), Const1,
2151 X);
2152 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), I);
2153 }
2154
2155 // (d)sll SllX, X, 1
2156 // (d)srl SrlX, SllX, 1
2157 // (d)srl SrlY, Y, width(Y)-1
2158 // (d)sll SllY, SrlX, width(Y)-1
2159 // or Or, SrlX, SllY
2160 SDValue SllX = DAG.getNode(ISD::SHL, DL, TyX, X, Const1);
2161 SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1);
2162 SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y,
2163 DAG.getConstant(WidthY - 1, DL, MVT::i32));
2164
2165 if (WidthX > WidthY)
2166 SrlY = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, SrlY);
2167 else if (WidthY > WidthX)
2168 SrlY = DAG.getNode(ISD::TRUNCATE, DL, TyX, SrlY);
2169
2170 SDValue SllY = DAG.getNode(ISD::SHL, DL, TyX, SrlY,
2171 DAG.getConstant(WidthX - 1, DL, MVT::i32));
2172 SDValue Or = DAG.getNode(ISD::OR, DL, TyX, SrlX, SllY);
2173 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Or);
2174}
2175
2176SDValue
2177MipsTargetLowering::lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
2178 if (Subtarget.isGP64bit())
2179 return lowerFCOPYSIGN64(Op, DAG, Subtarget.hasExtractInsert());
2180
2181 return lowerFCOPYSIGN32(Op, DAG, Subtarget.hasExtractInsert());
2182}
2183
2184SDValue MipsTargetLowering::
2185lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
2186 // check the depth
2187 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) &&(((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue
() == 0) && "Frame address can only be determined for current frame."
) ? static_cast<void> (0) : __assert_fail ("(cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) && \"Frame address can only be determined for current frame.\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/Target/Mips/MipsISelLowering.cpp"
, 2188, __PRETTY_FUNCTION__))
2188 "Frame address can only be determined for current frame.")(((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue
() == 0) && "Frame address can only be determined for current frame."
) ? static_cast<void> (0) : __assert_fail ("(cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) && \"Frame address can only be determined for current frame.\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/Target/Mips/MipsISelLowering.cpp"
, 2188, __PRETTY_FUNCTION__))
;
2189
2190 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
2191 MFI.setFrameAddressIsTaken(true);
2192 EVT VT = Op.getValueType();
2193 SDLoc DL(Op);
2194 SDValue FrameAddr = DAG.getCopyFromReg(
2195 DAG.getEntryNode(), DL, ABI.IsN64() ? Mips::FP_64 : Mips::FP, VT);
2196 return FrameAddr;
2197}
2198
2199SDValue MipsTargetLowering::lowerRETURNADDR(SDValue Op,
2200 SelectionDAG &DAG) const {
2201 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
2202 return SDValue();
2203
2204 // check the depth
2205 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) &&(((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue
() == 0) && "Return address can be determined only for current frame."
) ? static_cast<void> (0) : __assert_fail ("(cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) && \"Return address can be determined only for current frame.\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/Target/Mips/MipsISelLowering.cpp"
, 2206, __PRETTY_FUNCTION__))
2206 "Return address can be determined only for current frame.")(((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue
() == 0) && "Return address can be determined only for current frame."
) ? static_cast<void> (0) : __assert_fail ("(cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) && \"Return address can be determined only for current frame.\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/Target/Mips/MipsISelLowering.cpp"
, 2206, __PRETTY_FUNCTION__))
;
2207
2208 MachineFunction &MF = DAG.getMachineFunction();
2209 MachineFrameInfo &MFI = MF.getFrameInfo();
2210 MVT VT = Op.getSimpleValueType();
2211 unsigned RA = ABI.IsN64() ? Mips::RA_64 : Mips::RA;
2212 MFI.setReturnAddressIsTaken(true);
2213
2214 // Return RA, which contains the return address. Mark it an implicit live-in.
2215 unsigned Reg = MF.addLiveIn(RA, getRegClassFor(VT));
2216 return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(Op), Reg, VT);
2217}
2218
2219// An EH_RETURN is the result of lowering llvm.eh.return which in turn is
2220// generated from __builtin_eh_return (offset, handler)
2221// The effect of this is to adjust the stack pointer by "offset"
2222// and then branch to "handler".
2223SDValue MipsTargetLowering::lowerEH_RETURN(SDValue Op, SelectionDAG &DAG)
2224 const {
2225 MachineFunction &MF = DAG.getMachineFunction();
2226 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
2227
2228 MipsFI->setCallsEhReturn();
2229 SDValue Chain = Op.getOperand(0);
2230 SDValue Offset = Op.getOperand(1);
2231 SDValue Handler = Op.getOperand(2);
2232 SDLoc DL(Op);
2233 EVT Ty = ABI.IsN64() ? MVT::i64 : MVT::i32;
2234
2235 // Store stack offset in V1, store jump target in V0. Glue CopyToReg and
2236 // EH_RETURN nodes, so that instructions are emitted back-to-back.
2237 unsigned OffsetReg = ABI.IsN64() ? Mips::V1_64 : Mips::V1;
2238 unsigned AddrReg = ABI.IsN64() ? Mips::V0_64 : Mips::V0;
2239 Chain = DAG.getCopyToReg(Chain, DL, OffsetReg, Offset, SDValue());
2240 Chain = DAG.getCopyToReg(Chain, DL, AddrReg, Handler, Chain.getValue(1));
2241 return DAG.getNode(MipsISD::EH_RETURN, DL, MVT::Other, Chain,
2242 DAG.getRegister(OffsetReg, Ty),
2243 DAG.getRegister(AddrReg, getPointerTy(MF.getDataLayout())),
2244 Chain.getValue(1));
2245}
2246
2247SDValue MipsTargetLowering::lowerATOMIC_FENCE(SDValue Op,
2248 SelectionDAG &DAG) const {
2249 // FIXME: Need pseudo-fence for 'singlethread' fences
2250 // FIXME: Set SType for weaker fences where supported/appropriate.
2251 unsigned SType = 0;
2252 SDLoc DL(Op);
2253 return DAG.getNode(MipsISD::Sync, DL, MVT::Other, Op.getOperand(0),
2254 DAG.getConstant(SType, DL, MVT::i32));
2255}
2256
2257SDValue MipsTargetLowering::lowerShiftLeftParts(SDValue Op,
2258 SelectionDAG &DAG) const {
2259 SDLoc DL(Op);
2260 MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32;
2261
2262 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);
2263 SDValue Shamt = Op.getOperand(2);
2264 // if shamt < (VT.bits):
2265 // lo = (shl lo, shamt)
2266 // hi = (or (shl hi, shamt) (srl (srl lo, 1), ~shamt))
2267 // else:
2268 // lo = 0
2269 // hi = (shl lo, shamt[4:0])
2270 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
2271 DAG.getConstant(-1, DL, MVT::i32));
2272 SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, VT, Lo,
2273 DAG.getConstant(1, DL, VT));
2274 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, ShiftRight1Lo, Not);
2275 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, Hi, Shamt);
2276 SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo);
2277 SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt);
2278 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
2279 DAG.getConstant(VT.getSizeInBits(), DL, MVT::i32));
2280 Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond,
2281 DAG.getConstant(0, DL, VT), ShiftLeftLo);
2282 Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftLeftLo, Or);
2283
2284 SDValue Ops[2] = {Lo, Hi};
2285 return DAG.getMergeValues(Ops, DL);
2286}
2287
2288SDValue MipsTargetLowering::lowerShiftRightParts(SDValue Op, SelectionDAG &DAG,
2289 bool IsSRA) const {
2290 SDLoc DL(Op);
2291 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);
2292 SDValue Shamt = Op.getOperand(2);
2293 MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32;
2294
2295 // if shamt < (VT.bits):
2296 // lo = (or (shl (shl hi, 1), ~shamt) (srl lo, shamt))
2297 // if isSRA:
2298 // hi = (sra hi, shamt)
2299 // else:
2300 // hi = (srl hi, shamt)
2301 // else:
2302 // if isSRA:
2303 // lo = (sra hi, shamt[4:0])
2304 // hi = (sra hi, 31)
2305 // else:
2306 // lo = (srl hi, shamt[4:0])
2307 // hi = 0
2308 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
2309 DAG.getConstant(-1, DL, MVT::i32));
2310 SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, VT, Hi,
2311 DAG.getConstant(1, DL, VT));
2312 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, ShiftLeft1Hi, Not);
2313 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, Lo, Shamt);
2314 SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo);
2315 SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL,
2316 DL, VT, Hi, Shamt);
2317 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
2318 DAG.getConstant(VT.getSizeInBits(), DL, MVT::i32));
2319 SDValue Ext = DAG.getNode(ISD::SRA, DL, VT, Hi,
2320 DAG.getConstant(VT.getSizeInBits() - 1, DL, VT));
2321 Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftRightHi, Or);
2322 Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond,
2323 IsSRA ? Ext : DAG.getConstant(0, DL, VT), ShiftRightHi);
2324
2325 SDValue Ops[2] = {Lo, Hi};
2326 return DAG.getMergeValues(Ops, DL);
2327}
2328
2329static SDValue createLoadLR(unsigned Opc, SelectionDAG &DAG, LoadSDNode *LD,
2330 SDValue Chain, SDValue Src, unsigned Offset) {
2331 SDValue Ptr = LD->getBasePtr();
2332 EVT VT = LD->getValueType(0), MemVT = LD->getMemoryVT();
2333 EVT BasePtrVT = Ptr.getValueType();
2334 SDLoc DL(LD);
2335 SDVTList VTList = DAG.getVTList(VT, MVT::Other);
2336
2337 if (Offset)
2338 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr,
2339 DAG.getConstant(Offset, DL, BasePtrVT));
2340
2341 SDValue Ops[] = { Chain, Ptr, Src };
2342 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT,
2343 LD->getMemOperand());
2344}
2345
2346// Expand an unaligned 32 or 64-bit integer load node.
2347SDValue MipsTargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const {
2348 LoadSDNode *LD = cast<LoadSDNode>(Op);
2349 EVT MemVT = LD->getMemoryVT();
2350
2351 if (Subtarget.systemSupportsUnalignedAccess())
2352 return Op;
2353
2354 // Return if load is aligned or if MemVT is neither i32 nor i64.
2355 if ((LD->getAlignment() >= MemVT.getSizeInBits() / 8) ||
2356 ((MemVT != MVT::i32) && (MemVT != MVT::i64)))
2357 return SDValue();
2358
2359 bool IsLittle = Subtarget.isLittle();
2360 EVT VT = Op.getValueType();
2361 ISD::LoadExtType ExtType = LD->getExtensionType();
2362 SDValue Chain = LD->getChain(), Undef = DAG.getUNDEF(VT);
2363
2364 assert((VT == MVT::i32) || (VT == MVT::i64))(((VT == MVT::i32) || (VT == MVT::i64)) ? static_cast<void
> (0) : __assert_fail ("(VT == MVT::i32) || (VT == MVT::i64)"
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/Target/Mips/MipsISelLowering.cpp"
, 2364, __PRETTY_FUNCTION__))
;
2365
2366 // Expand
2367 // (set dst, (i64 (load baseptr)))
2368 // to
2369 // (set tmp, (ldl (add baseptr, 7), undef))
2370 // (set dst, (ldr baseptr, tmp))
2371 if ((VT == MVT::i64) && (ExtType == ISD::NON_EXTLOAD)) {
2372 SDValue LDL = createLoadLR(MipsISD::LDL, DAG, LD, Chain, Undef,
2373 IsLittle ? 7 : 0);
2374 return createLoadLR(MipsISD::LDR, DAG, LD, LDL.getValue(1), LDL,
2375 IsLittle ? 0 : 7);
2376 }
2377
2378 SDValue LWL = createLoadLR(MipsISD::LWL, DAG, LD, Chain, Undef,
2379 IsLittle ? 3 : 0);
2380 SDValue LWR = createLoadLR(MipsISD::LWR, DAG, LD, LWL.getValue(1), LWL,
2381 IsLittle ? 0 : 3);
2382
2383 // Expand
2384 // (set dst, (i32 (load baseptr))) or
2385 // (set dst, (i64 (sextload baseptr))) or
2386 // (set dst, (i64 (extload baseptr)))
2387 // to
2388 // (set tmp, (lwl (add baseptr, 3), undef))
2389 // (set dst, (lwr baseptr, tmp))
2390 if ((VT == MVT::i32) || (ExtType == ISD::SEXTLOAD) ||
2391 (ExtType == ISD::EXTLOAD))
2392 return LWR;
2393
2394 assert((VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD))(((VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD)) ? static_cast
<void> (0) : __assert_fail ("(VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD)"
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/Target/Mips/MipsISelLowering.cpp"
, 2394, __PRETTY_FUNCTION__))
;
2395
2396 // Expand
2397 // (set dst, (i64 (zextload baseptr)))
2398 // to
2399 // (set tmp0, (lwl (add baseptr, 3), undef))
2400 // (set tmp1, (lwr baseptr, tmp0))
2401 // (set tmp2, (shl tmp1, 32))
2402 // (set dst, (srl tmp2, 32))
2403 SDLoc DL(LD);
2404 SDValue Const32 = DAG.getConstant(32, DL, MVT::i32);
2405 SDValue SLL = DAG.getNode(ISD::SHL, DL, MVT::i64, LWR, Const32);
2406 SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32);
2407 SDValue Ops[] = { SRL, LWR.getValue(1) };
2408 return DAG.getMergeValues(Ops, DL);
2409}
2410
2411static SDValue createStoreLR(unsigned Opc, SelectionDAG &DAG, StoreSDNode *SD,
2412 SDValue Chain, unsigned Offset) {
2413 SDValue Ptr = SD->getBasePtr(), Value = SD->getValue();
2414 EVT MemVT = SD->getMemoryVT(), BasePtrVT = Ptr.getValueType();
2415 SDLoc DL(SD);
2416 SDVTList VTList = DAG.getVTList(MVT::Other);
2417
2418 if (Offset)
2419 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr,
2420 DAG.getConstant(Offset, DL, BasePtrVT));
2421
2422 SDValue Ops[] = { Chain, Value, Ptr };
2423 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT,
2424 SD->getMemOperand());
2425}
2426
2427// Expand an unaligned 32 or 64-bit integer store node.
2428static SDValue lowerUnalignedIntStore(StoreSDNode *SD, SelectionDAG &DAG,
2429 bool IsLittle) {
2430 SDValue Value = SD->getValue(), Chain = SD->getChain();
2431 EVT VT = Value.getValueType();
2432
2433 // Expand
2434 // (store val, baseptr) or
2435 // (truncstore val, baseptr)
2436 // to
2437 // (swl val, (add baseptr, 3))
2438 // (swr val, baseptr)
2439 if ((VT == MVT::i32) || SD->isTruncatingStore()) {
2440 SDValue SWL = createStoreLR(MipsISD::SWL, DAG, SD, Chain,
2441 IsLittle ? 3 : 0);
2442 return createStoreLR(MipsISD::SWR, DAG, SD, SWL, IsLittle ? 0 : 3);
2443 }
2444
2445 assert(VT == MVT::i64)((VT == MVT::i64) ? static_cast<void> (0) : __assert_fail
("VT == MVT::i64", "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/Target/Mips/MipsISelLowering.cpp"
, 2445, __PRETTY_FUNCTION__))
;
2446
2447 // Expand
2448 // (store val, baseptr)
2449 // to
2450 // (sdl val, (add baseptr, 7))
2451 // (sdr val, baseptr)
2452 SDValue SDL = createStoreLR(MipsISD::SDL, DAG, SD, Chain, IsLittle ? 7 : 0);
2453 return createStoreLR(MipsISD::SDR, DAG, SD, SDL, IsLittle ? 0 : 7);
2454}
2455
2456// Lower (store (fp_to_sint $fp) $ptr) to (store (TruncIntFP $fp), $ptr).
2457static SDValue lowerFP_TO_SINT_STORE(StoreSDNode *SD, SelectionDAG &DAG) {
2458 SDValue Val = SD->getValue();
2459
2460 if (Val.getOpcode() != ISD::FP_TO_SINT)
2461 return SDValue();
2462
2463 EVT FPTy = EVT::getFloatingPointVT(Val.getValueSizeInBits());
2464 SDValue Tr = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Val), FPTy,
2465 Val.getOperand(0));
2466 return DAG.getStore(SD->getChain(), SDLoc(SD), Tr, SD->getBasePtr(),
2467 SD->getPointerInfo(), SD->getAlignment(),
2468 SD->getMemOperand()->getFlags());
2469}
2470
2471SDValue MipsTargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const {
2472 StoreSDNode *SD = cast<StoreSDNode>(Op);
2473 EVT MemVT = SD->getMemoryVT();
2474
2475 // Lower unaligned integer stores.
2476 if (!Subtarget.systemSupportsUnalignedAccess() &&
2477 (SD->getAlignment() < MemVT.getSizeInBits() / 8) &&
2478 ((MemVT == MVT::i32) || (MemVT == MVT::i64)))
2479 return lowerUnalignedIntStore(SD, DAG, Subtarget.isLittle());
2480
2481 return lowerFP_TO_SINT_STORE(SD, DAG);
2482}
2483
2484SDValue MipsTargetLowering::lowerEH_DWARF_CFA(SDValue Op,
2485 SelectionDAG &DAG) const {
2486
2487 // Return a fixed StackObject with offset 0 which points to the old stack
2488 // pointer.
2489 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
2490 EVT ValTy = Op->getValueType(0);
2491 int FI = MFI.CreateFixedObject(Op.getValueSizeInBits() / 8, 0, false);
2492 return DAG.getFrameIndex(FI, ValTy);
2493}
2494
2495SDValue MipsTargetLowering::lowerFP_TO_SINT(SDValue Op,
2496 SelectionDAG &DAG) const {
2497 EVT FPTy = EVT::getFloatingPointVT(Op.getValueSizeInBits());
2498 SDValue Trunc = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Op), FPTy,
2499 Op.getOperand(0));
2500 return DAG.getNode(ISD::BITCAST, SDLoc(Op), Op.getValueType(), Trunc);
2501}
2502
2503//===----------------------------------------------------------------------===//
2504// Calling Convention Implementation
2505//===----------------------------------------------------------------------===//
2506
2507//===----------------------------------------------------------------------===//
2508// TODO: Implement a generic logic using tblgen that can support this.
2509// Mips O32 ABI rules:
2510// ---
2511// i32 - Passed in A0, A1, A2, A3 and stack
2512// f32 - Only passed in f32 registers if no int reg has been used yet to hold
2513// an argument. Otherwise, passed in A1, A2, A3 and stack.
2514// f64 - Only passed in two aliased f32 registers if no int reg has been used
2515// yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is
2516// not used, it must be shadowed. If only A3 is available, shadow it and
2517// go to stack.
2518//
2519// For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack.
2520//===----------------------------------------------------------------------===//
2521
2522static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT,
2523 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
2524 CCState &State, ArrayRef<MCPhysReg> F64Regs) {
2525 const MipsSubtarget &Subtarget = static_cast<const MipsSubtarget &>(
2526 State.getMachineFunction().getSubtarget());
2527
2528 static const MCPhysReg IntRegs[] = { Mips::A0, Mips::A1, Mips::A2, Mips::A3 };
2529 static const MCPhysReg F32Regs[] = { Mips::F12, Mips::F14 };
2530
2531 // Do not process byval args here.
2532 if (ArgFlags.isByVal())
2533 return true;
2534
2535 // Promote i8 and i16
2536 if (ArgFlags.isInReg() && !Subtarget.isLittle()) {
2537 if (LocVT == MVT::i8 || LocVT == MVT::i16 || LocVT == MVT::i32) {
2538 LocVT = MVT::i32;
2539 if (ArgFlags.isSExt())
2540 LocInfo = CCValAssign::SExtUpper;
2541 else if (ArgFlags.isZExt())
2542 LocInfo = CCValAssign::ZExtUpper;
2543 else
2544 LocInfo = CCValAssign::AExtUpper;
2545 }
2546 }
2547
2548 // Promote i8 and i16
2549 if (LocVT == MVT::i8 || LocVT == MVT::i16) {
2550 LocVT = MVT::i32;
2551 if (ArgFlags.isSExt())
2552 LocInfo = CCValAssign::SExt;
2553 else if (ArgFlags.isZExt())
2554 LocInfo = CCValAssign::ZExt;
2555 else
2556 LocInfo = CCValAssign::AExt;
2557 }
2558
2559 unsigned Reg;
2560
2561 // f32 and f64 are allocated in A0, A1, A2, A3 when either of the following
2562 // is true: function is vararg, argument is 3rd or higher, there is previous
2563 // argument which is not f32 or f64.
2564 bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1 ||
2565 State.getFirstUnallocated(F32Regs) != ValNo;
2566 unsigned OrigAlign = ArgFlags.getOrigAlign();
2567 bool isI64 = (ValVT == MVT::i32 && OrigAlign == 8);
2568
2569 if (ValVT == MVT::i32 || (ValVT == MVT::f32 && AllocateFloatsInIntReg)) {
2570 Reg = State.AllocateReg(IntRegs);
2571 // If this is the first part of an i64 arg,
2572 // the allocated register must be either A0 or A2.
2573 if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3))
2574 Reg = State.AllocateReg(IntRegs);
2575 LocVT = MVT::i32;
2576 } else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) {
2577 // Allocate int register and shadow next int register. If first
2578 // available register is Mips::A1 or Mips::A3, shadow it too.
2579 Reg = State.AllocateReg(IntRegs);
2580 if (Reg == Mips::A1 || Reg == Mips::A3)
2581 Reg = State.AllocateReg(IntRegs);
2582 State.AllocateReg(IntRegs);
2583 LocVT = MVT::i32;
2584 } else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) {
2585 // we are guaranteed to find an available float register
2586 if (ValVT == MVT::f32) {
2587 Reg = State.AllocateReg(F32Regs);
2588 // Shadow int register
2589 State.AllocateReg(IntRegs);
2590 } else {
2591 Reg = State.AllocateReg(F64Regs);
2592 // Shadow int registers
2593 unsigned Reg2 = State.AllocateReg(IntRegs);
2594 if (Reg2 == Mips::A1 || Reg2 == Mips::A3)
2595 State.AllocateReg(IntRegs);
2596 State.AllocateReg(IntRegs);
2597 }
2598 } else
2599 llvm_unreachable("Cannot handle this ValVT.")::llvm::llvm_unreachable_internal("Cannot handle this ValVT."
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/Target/Mips/MipsISelLowering.cpp"
, 2599)
;
2600
2601 if (!Reg) {
2602 unsigned Offset = State.AllocateStack(ValVT.getSizeInBits() >> 3,
2603 OrigAlign);
2604 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
2605 } else
2606 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2607
2608 return false;
2609}
2610
2611static bool CC_MipsO32_FP32(unsigned ValNo, MVT ValVT,
2612 MVT LocVT, CCValAssign::LocInfo LocInfo,
2613 ISD::ArgFlagsTy ArgFlags, CCState &State) {
2614 static const MCPhysReg F64Regs[] = { Mips::D6, Mips::D7 };
2615
2616 return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs);
2617}
2618
2619static bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT,
2620 MVT LocVT, CCValAssign::LocInfo LocInfo,
2621 ISD::ArgFlagsTy ArgFlags, CCState &State) {
2622 static const MCPhysReg F64Regs[] = { Mips::D12_64, Mips::D14_64 };
2623
2624 return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs);
2625}
2626
2627static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT,
2628 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
2629 CCState &State) LLVM_ATTRIBUTE_UNUSED__attribute__((__unused__));
2630
2631#include "MipsGenCallingConv.inc"
2632
2633//===----------------------------------------------------------------------===//
2634// Call Calling Convention Implementation
2635//===----------------------------------------------------------------------===//
2636
2637// Return next O32 integer argument register.
2638static unsigned getNextIntArgReg(unsigned Reg) {
2639 assert((Reg == Mips::A0) || (Reg == Mips::A2))(((Reg == Mips::A0) || (Reg == Mips::A2)) ? static_cast<void
> (0) : __assert_fail ("(Reg == Mips::A0) || (Reg == Mips::A2)"
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/Target/Mips/MipsISelLowering.cpp"
, 2639, __PRETTY_FUNCTION__))
;
2640 return (Reg == Mips::A0) ? Mips::A1 : Mips::A3;
2641}
2642
2643SDValue MipsTargetLowering::passArgOnStack(SDValue StackPtr, unsigned Offset,
2644 SDValue Chain, SDValue Arg,
2645 const SDLoc &DL, bool IsTailCall,
2646 SelectionDAG &DAG) const {
2647 if (!IsTailCall) {
2648 SDValue PtrOff =
2649 DAG.getNode(ISD::ADD, DL, getPointerTy(DAG.getDataLayout()), StackPtr,
2650 DAG.getIntPtrConstant(Offset, DL));
2651 return DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo());
2652 }
2653
2654 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
2655 int FI = MFI.CreateFixedObject(Arg.getValueSizeInBits() / 8, Offset, false);
2656 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
2657 return DAG.getStore(Chain, DL, Arg, FIN, MachinePointerInfo(),
2658 /* Alignment = */ 0, MachineMemOperand::MOVolatile);
2659}
2660
2661void MipsTargetLowering::
2662getOpndList(SmallVectorImpl<SDValue> &Ops,
2663 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
2664 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
2665 bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee,
2666 SDValue Chain) const {
2667 // Insert node "GP copy globalreg" before call to function.
2668 //
2669 // R_MIPS_CALL* operators (emitted when non-internal functions are called
2670 // in PIC mode) allow symbols to be resolved via lazy binding.
2671 // The lazy binding stub requires GP to point to the GOT.
2672 // Note that we don't need GP to point to the GOT for indirect calls
2673 // (when R_MIPS_CALL* is not used for the call) because Mips linker generates
2674 // lazy binding stub for a function only when R_MIPS_CALL* are the only relocs
2675 // used for the function (that is, Mips linker doesn't generate lazy binding
2676 // stub for a function whose address is taken in the program).
2677 if (IsPICCall && !InternalLinkage && IsCallReloc) {
2678 unsigned GPReg = ABI.IsN64() ? Mips::GP_64 : Mips::GP;
2679 EVT Ty = ABI.IsN64() ? MVT::i64 : MVT::i32;
2680 RegsToPass.push_back(std::make_pair(GPReg, getGlobalReg(CLI.DAG, Ty)));
2681 }
2682
2683 // Build a sequence of copy-to-reg nodes chained together with token
2684 // chain and flag operands which copy the outgoing args into registers.
2685 // The InFlag in necessary since all emitted instructions must be
2686 // stuck together.
2687 SDValue InFlag;
2688
2689 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2690 Chain = CLI.DAG.getCopyToReg(Chain, CLI.DL, RegsToPass[i].first,
2691 RegsToPass[i].second, InFlag);
2692 InFlag = Chain.getValue(1);
2693 }
2694
2695 // Add argument registers to the end of the list so that they are
2696 // known live into the call.
2697 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2698 Ops.push_back(CLI.DAG.getRegister(RegsToPass[i].first,
2699 RegsToPass[i].second.getValueType()));
2700
2701 // Add a register mask operand representing the call-preserved registers.
2702 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
2703 const uint32_t *Mask =
2704 TRI->getCallPreservedMask(CLI.DAG.getMachineFunction(), CLI.CallConv);
2705 assert(Mask && "Missing call preserved mask for calling convention")((Mask && "Missing call preserved mask for calling convention"
) ? static_cast<void> (0) : __assert_fail ("Mask && \"Missing call preserved mask for calling convention\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/Target/Mips/MipsISelLowering.cpp"
, 2705, __PRETTY_FUNCTION__))
;
2706 if (Subtarget.inMips16HardFloat()) {
2707 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(CLI.Callee)) {
2708 llvm::StringRef Sym = G->getGlobal()->getName();
2709 Function *F = G->getGlobal()->getParent()->getFunction(Sym);
2710 if (F && F->hasFnAttribute("__Mips16RetHelper")) {
2711 Mask = MipsRegisterInfo::getMips16RetHelperMask();
2712 }
2713 }
2714 }
2715 Ops.push_back(CLI.DAG.getRegisterMask(Mask));
2716
2717 if (InFlag.getNode())
2718 Ops.push_back(InFlag);
2719}
2720
2721/// LowerCall - functions arguments are copied from virtual regs to
2722/// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
2723SDValue
2724MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2725 SmallVectorImpl<SDValue> &InVals) const {
2726 SelectionDAG &DAG = CLI.DAG;
2727 SDLoc DL = CLI.DL;
2728 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2729 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2730 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2731 SDValue Chain = CLI.Chain;
2732 SDValue Callee = CLI.Callee;
2733 bool &IsTailCall = CLI.IsTailCall;
2734 CallingConv::ID CallConv = CLI.CallConv;
2735 bool IsVarArg = CLI.IsVarArg;
2736
2737 MachineFunction &MF = DAG.getMachineFunction();
2738 MachineFrameInfo &MFI = MF.getFrameInfo();
2739 const TargetFrameLowering *TFL = Subtarget.getFrameLowering();
2740 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
2741 bool IsPIC = isPositionIndependent();
2742
2743 // Analyze operands of the call, assigning locations to each operand.
2744 SmallVector<CCValAssign, 16> ArgLocs;
2745 MipsCCState CCInfo(
2746 CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, *DAG.getContext(),
2747 MipsCCState::getSpecialCallingConvForCallee(Callee.getNode(), Subtarget));
2748
2749 // Allocate the reserved argument area. It seems strange to do this from the
2750 // caller side but removing it breaks the frame size calculation.
2751 CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(CallConv), 1);
2752
2753 CCInfo.AnalyzeCallOperands(Outs, CC_Mips, CLI.getArgs(), Callee.getNode());
2754
2755 // Get a count of how many bytes are to be pushed on the stack.
2756 unsigned NextStackOffset = CCInfo.getNextStackOffset();
2757
2758 // Check if it's really possible to do a tail call. Restrict it to functions
2759 // that are part of this compilation unit.
2760 bool InternalLinkage = false;
2761 if (IsTailCall) {
2762 IsTailCall = isEligibleForTailCallOptimization(
2763 CCInfo, NextStackOffset, *MF.getInfo<MipsFunctionInfo>());
2764 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2765 InternalLinkage = G->getGlobal()->hasInternalLinkage();
2766 IsTailCall &= (InternalLinkage || G->getGlobal()->hasLocalLinkage() ||
2767 G->getGlobal()->hasPrivateLinkage() ||
2768 G->getGlobal()->hasHiddenVisibility() ||
2769 G->getGlobal()->hasProtectedVisibility());
2770 }
2771 }
2772 if (!IsTailCall && CLI.CS && CLI.CS->isMustTailCall())
2773 report_fatal_error("failed to perform tail call elimination on a call "
2774 "site marked musttail");
2775
2776 if (IsTailCall)
2777 ++NumTailCalls;
2778
2779 // Chain is the output chain of the last Load/Store or CopyToReg node.
2780 // ByValChain is the output chain of the last Memcpy node created for copying
2781 // byval arguments to the stack.
2782 unsigned StackAlignment = TFL->getStackAlignment();
2783 NextStackOffset = alignTo(NextStackOffset, StackAlignment);
2784 SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, DL, true);
2785
2786 if (!IsTailCall)
2787 Chain = DAG.getCALLSEQ_START(Chain, NextStackOffsetVal, DL);
2788
2789 SDValue StackPtr =
2790 DAG.getCopyFromReg(Chain, DL, ABI.IsN64() ? Mips::SP_64 : Mips::SP,
2791 getPointerTy(DAG.getDataLayout()));
2792
2793 std::deque< std::pair<unsigned, SDValue> > RegsToPass;
2794 SmallVector<SDValue, 8> MemOpChains;
2795
2796 CCInfo.rewindByValRegsInfo();
2797
2798 // Walk the register/memloc assignments, inserting copies/loads.
2799 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2800 SDValue Arg = OutVals[i];
2801 CCValAssign &VA = ArgLocs[i];
2802 MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT();
2803 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2804 bool UseUpperBits = false;
2805
2806 // ByVal Arg.
2807 if (Flags.isByVal()) {
2808 unsigned FirstByValReg, LastByValReg;
2809 unsigned ByValIdx = CCInfo.getInRegsParamsProcessed();
2810 CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg);
2811
2812 assert(Flags.getByValSize() &&((Flags.getByValSize() && "ByVal args of size 0 should have been ignored by front-end."
) ? static_cast<void> (0) : __assert_fail ("Flags.getByValSize() && \"ByVal args of size 0 should have been ignored by front-end.\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/Target/Mips/MipsISelLowering.cpp"
, 2813, __PRETTY_FUNCTION__))
2813 "ByVal args of size 0 should have been ignored by front-end.")((Flags.getByValSize() && "ByVal args of size 0 should have been ignored by front-end."
) ? static_cast<void> (0) : __assert_fail ("Flags.getByValSize() && \"ByVal args of size 0 should have been ignored by front-end.\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/Target/Mips/MipsISelLowering.cpp"
, 2813, __PRETTY_FUNCTION__))
;
2814 assert(ByValIdx < CCInfo.getInRegsParamsCount())((ByValIdx < CCInfo.getInRegsParamsCount()) ? static_cast<
void> (0) : __assert_fail ("ByValIdx < CCInfo.getInRegsParamsCount()"
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/Target/Mips/MipsISelLowering.cpp"
, 2814, __PRETTY_FUNCTION__))
;
2815 assert(!IsTailCall &&((!IsTailCall && "Do not tail-call optimize if there is a byval argument."
) ? static_cast<void> (0) : __assert_fail ("!IsTailCall && \"Do not tail-call optimize if there is a byval argument.\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/Target/Mips/MipsISelLowering.cpp"
, 2816, __PRETTY_FUNCTION__))
2816 "Do not tail-call optimize if there is a byval argument.")((!IsTailCall && "Do not tail-call optimize if there is a byval argument."
) ? static_cast<void> (0) : __assert_fail ("!IsTailCall && \"Do not tail-call optimize if there is a byval argument.\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/Target/Mips/MipsISelLowering.cpp"
, 2816, __PRETTY_FUNCTION__))
;
2817 passByValArg(Chain, DL, RegsToPass, MemOpChains, StackPtr, MFI, DAG, Arg,
2818 FirstByValReg, LastByValReg, Flags, Subtarget.isLittle(),
2819 VA);
2820 CCInfo.nextInRegsParam();
2821 continue;
2822 }
2823
2824 // Promote the value if needed.
2825 switch (VA.getLocInfo()) {
2826 default:
2827 llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/Target/Mips/MipsISelLowering.cpp"
, 2827)
;
2828 case CCValAssign::Full:
2829 if (VA.isRegLoc()) {
2830 if ((ValVT == MVT::f32 && LocVT == MVT::i32) ||
2831 (ValVT == MVT::f64 && LocVT == MVT::i64) ||
2832 (ValVT == MVT::i64 && LocVT == MVT::f64))
2833 Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg);
2834 else if (ValVT == MVT::f64 && LocVT == MVT::i32) {
2835 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
2836 Arg, DAG.getConstant(0, DL, MVT::i32));
2837 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
2838 Arg, DAG.getConstant(1, DL, MVT::i32));
2839 if (!Subtarget.isLittle())
2840 std::swap(Lo, Hi);
2841 unsigned LocRegLo = VA.getLocReg();
2842 unsigned LocRegHigh = getNextIntArgReg(LocRegLo);
2843 RegsToPass.push_back(std::make_pair(LocRegLo, Lo));
2844 RegsToPass.push_back(std::make_pair(LocRegHigh, Hi));
2845 continue;
2846 }
2847 }
2848 break;
2849 case CCValAssign::BCvt:
2850 Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg);
2851 break;
2852 case CCValAssign::SExtUpper:
2853 UseUpperBits = true;
2854 LLVM_FALLTHROUGH[[clang::fallthrough]];
2855 case CCValAssign::SExt:
2856 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, LocVT, Arg);
2857 break;
2858 case CCValAssign::ZExtUpper:
2859 UseUpperBits = true;
2860 LLVM_FALLTHROUGH[[clang::fallthrough]];
2861 case CCValAssign::ZExt:
2862 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, LocVT, Arg);
2863 break;
2864 case CCValAssign::AExtUpper:
2865 UseUpperBits = true;
2866 LLVM_FALLTHROUGH[[clang::fallthrough]];
2867 case CCValAssign::AExt:
2868 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, LocVT, Arg);
2869 break;
2870 }
2871
2872 if (UseUpperBits) {
2873 unsigned ValSizeInBits = Outs[i].ArgVT.getSizeInBits();
2874 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
2875 Arg = DAG.getNode(
2876 ISD::SHL, DL, VA.getLocVT(), Arg,
2877 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT()));
2878 }
2879
2880 // Arguments that can be passed on register must be kept at
2881 // RegsToPass vector
2882 if (VA.isRegLoc()) {
2883 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2884 continue;
2885 }
2886
2887 // Register can't get to this point...
2888 assert(VA.isMemLoc())((VA.isMemLoc()) ? static_cast<void> (0) : __assert_fail
("VA.isMemLoc()", "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/Target/Mips/MipsISelLowering.cpp"
, 2888, __PRETTY_FUNCTION__))
;
2889
2890 // emit ISD::STORE whichs stores the
2891 // parameter value to a stack Location
2892 MemOpChains.push_back(passArgOnStack(StackPtr, VA.getLocMemOffset(),
2893 Chain, Arg, DL, IsTailCall, DAG));
2894 }
2895
2896 // Transform all store nodes into one single node because all store
2897 // nodes are independent of each other.
2898 if (!MemOpChains.empty())
2899 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
2900
2901 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
2902 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
2903 // node so that legalize doesn't hack it.
2904
2905 SDValue CalleeLo;
2906 EVT Ty = Callee.getValueType();
2907 bool GlobalOrExternal = false, IsCallReloc = false;
2908
2909 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2910 if (IsPIC) {
2911 const GlobalValue *Val = G->getGlobal();
2912 InternalLinkage = Val->hasInternalLinkage();
2913
2914 if (InternalLinkage)
2915 Callee = getAddrLocal(G, DL, Ty, DAG, ABI.IsN32() || ABI.IsN64());
2916 else if (LargeGOT) {
2917 Callee = getAddrGlobalLargeGOT(G, DL, Ty, DAG, MipsII::MO_CALL_HI16,
2918 MipsII::MO_CALL_LO16, Chain,
2919 FuncInfo->callPtrInfo(Val));
2920 IsCallReloc = true;
2921 } else {
2922 Callee = getAddrGlobal(G, DL, Ty, DAG, MipsII::MO_GOT_CALL, Chain,
2923 FuncInfo->callPtrInfo(Val));
2924 IsCallReloc = true;
2925 }
2926 } else
2927 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL,
2928 getPointerTy(DAG.getDataLayout()), 0,
2929 MipsII::MO_NO_FLAG);
2930 GlobalOrExternal = true;
2931 }
2932 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2933 const char *Sym = S->getSymbol();
2934
2935 if (!IsPIC) // static
2936 Callee = DAG.getTargetExternalSymbol(
2937 Sym, getPointerTy(DAG.getDataLayout()), MipsII::MO_NO_FLAG);
2938 else if (LargeGOT) {
2939 Callee = getAddrGlobalLargeGOT(S, DL, Ty, DAG, MipsII::MO_CALL_HI16,
2940 MipsII::MO_CALL_LO16, Chain,
2941 FuncInfo->callPtrInfo(Sym));
2942 IsCallReloc = true;
2943 } else { // PIC
2944 Callee = getAddrGlobal(S, DL, Ty, DAG, MipsII::MO_GOT_CALL, Chain,
2945 FuncInfo->callPtrInfo(Sym));
2946 IsCallReloc = true;
2947 }
2948
2949 GlobalOrExternal = true;
2950 }
2951
2952 SmallVector<SDValue, 8> Ops(1, Chain);
2953 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2954
2955 getOpndList(Ops, RegsToPass, IsPIC, GlobalOrExternal, InternalLinkage,
2956 IsCallReloc, CLI, Callee, Chain);
2957
2958 if (IsTailCall) {
2959 MF.getFrameInfo().setHasTailCall();
2960 return DAG.getNode(MipsISD::TailCall, DL, MVT::Other, Ops);
2961 }
2962
2963 Chain = DAG.getNode(MipsISD::JmpLink, DL, NodeTys, Ops);
2964 SDValue InFlag = Chain.getValue(1);
2965
2966 // Create the CALLSEQ_END node.
2967 Chain = DAG.getCALLSEQ_END(Chain, NextStackOffsetVal,
2968 DAG.getIntPtrConstant(0, DL, true), InFlag, DL);
2969 InFlag = Chain.getValue(1);
2970
2971 // Handle result values, copying them out of physregs into vregs that we
2972 // return.
2973 return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG,
2974 InVals, CLI);
2975}
2976
2977/// LowerCallResult - Lower the result values of a call into the
2978/// appropriate copies out of appropriate physical registers.
2979SDValue MipsTargetLowering::LowerCallResult(
2980 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool IsVarArg,
2981 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
2982 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals,
2983 TargetLowering::CallLoweringInfo &CLI) const {
2984 // Assign locations to each value returned by this call.
2985 SmallVector<CCValAssign, 16> RVLocs;
2986 MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
2987 *DAG.getContext());
2988 CCInfo.AnalyzeCallResult(Ins, RetCC_Mips, CLI);
2989
2990 // Copy all of the result registers out of their specified physreg.
2991 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2992 CCValAssign &VA = RVLocs[i];
2993 assert(VA.isRegLoc() && "Can only return in registers!")((VA.isRegLoc() && "Can only return in registers!") ?
static_cast<void> (0) : __assert_fail ("VA.isRegLoc() && \"Can only return in registers!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/Target/Mips/MipsISelLowering.cpp"
, 2993, __PRETTY_FUNCTION__))
;
2994
2995 SDValue Val = DAG.getCopyFromReg(Chain, DL, RVLocs[i].getLocReg(),
2996 RVLocs[i].getLocVT(), InFlag);
2997 Chain = Val.getValue(1);
2998 InFlag = Val.getValue(2);
2999
3000 if (VA.isUpperBitsInLoc()) {
3001 unsigned ValSizeInBits = Ins[i].ArgVT.getSizeInBits();
3002 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
3003 unsigned Shift =
3004 VA.getLocInfo() == CCValAssign::ZExtUpper ? ISD::SRL : ISD::SRA;
3005 Val = DAG.getNode(
3006 Shift, DL, VA.getLocVT(), Val,
3007 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT()));
3008 }
3009
3010 switch (VA.getLocInfo()) {
3011 default:
3012 llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/Target/Mips/MipsISelLowering.cpp"
, 3012)
;
3013 case CCValAssign::Full:
3014 break;
3015 case CCValAssign::BCvt:
3016 Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val);
3017 break;
3018 case CCValAssign::AExt:
3019 case CCValAssign::AExtUpper:
3020 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
3021 break;
3022 case CCValAssign::ZExt:
3023 case CCValAssign::ZExtUpper:
3024 Val = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Val,
3025 DAG.getValueType(VA.getValVT()));
3026 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
3027 break;
3028 case CCValAssign::SExt:
3029 case CCValAssign::SExtUpper:
3030 Val = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Val,
3031 DAG.getValueType(VA.getValVT()));
3032 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
3033 break;
3034 }
3035
3036 InVals.push_back(Val);
3037 }
3038
3039 return Chain;
3040}
3041
3042static SDValue UnpackFromArgumentSlot(SDValue Val, const CCValAssign &VA,
3043 EVT ArgVT, const SDLoc &DL,
3044 SelectionDAG &DAG) {
3045 MVT LocVT = VA.getLocVT();
3046 EVT ValVT = VA.getValVT();
3047
3048 // Shift into the upper bits if necessary.
3049 switch (VA.getLocInfo()) {
3050 default:
3051 break;
3052 case CCValAssign::AExtUpper:
3053 case CCValAssign::SExtUpper:
3054 case CCValAssign::ZExtUpper: {
3055 unsigned ValSizeInBits = ArgVT.getSizeInBits();
3056 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
3057 unsigned Opcode =
3058 VA.getLocInfo() == CCValAssign::ZExtUpper ? ISD::SRL : ISD::SRA;
3059 Val = DAG.getNode(
3060 Opcode, DL, VA.getLocVT(), Val,
3061 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT()));
3062 break;
3063 }
3064 }
3065
3066 // If this is an value smaller than the argument slot size (32-bit for O32,
3067 // 64-bit for N32/N64), it has been promoted in some way to the argument slot
3068 // size. Extract the value and insert any appropriate assertions regarding
3069 // sign/zero extension.
3070 switch (VA.getLocInfo()) {
3071 default:
3072 llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/Target/Mips/MipsISelLowering.cpp"
, 3072)
;
3073 case CCValAssign::Full:
3074 break;
3075 case CCValAssign::AExtUpper:
3076 case CCValAssign::AExt:
3077 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val);
3078 break;
3079 case CCValAssign::SExtUpper:
3080 case CCValAssign::SExt:
3081 Val = DAG.getNode(ISD::AssertSext, DL, LocVT, Val, DAG.getValueType(ValVT));
3082 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val);
3083 break;
3084 case CCValAssign::ZExtUpper:
3085 case CCValAssign::ZExt:
3086 Val = DAG.getNode(ISD::AssertZext, DL, LocVT, Val, DAG.getValueType(ValVT));
3087 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val);
3088 break;
3089 case CCValAssign::BCvt:
3090 Val = DAG.getNode(ISD::BITCAST, DL, ValVT, Val);
3091 break;
3092 }
3093
3094 return Val;
3095}
3096
3097//===----------------------------------------------------------------------===//
3098// Formal Arguments Calling Convention Implementation
3099//===----------------------------------------------------------------------===//
3100/// LowerFormalArguments - transform physical registers into virtual registers
3101/// and generate load operations for arguments places on the stack.
3102SDValue MipsTargetLowering::LowerFormalArguments(
3103 SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
3104 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
3105 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
3106 MachineFunction &MF = DAG.getMachineFunction();
3107 MachineFrameInfo &MFI = MF.getFrameInfo();
3108 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
3109
3110 MipsFI->setVarArgsFrameIndex(0);
3111
3112 // Used with vargs to acumulate store chains.
3113 std::vector<SDValue> OutChains;
3114
3115 // Assign locations to all of the incoming arguments.
3116 SmallVector<CCValAssign, 16> ArgLocs;
3117 MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
3118 *DAG.getContext());
3119 CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(CallConv), 1);
3120 const Function *Func = DAG.getMachineFunction().getFunction();
3121 Function::const_arg_iterator FuncArg = Func->arg_begin();
3122
3123 if (Func->hasFnAttribute("interrupt") && !Func->arg_empty())
3124 report_fatal_error(
3125 "Functions with the interrupt attribute cannot have arguments!");
3126
3127 CCInfo.AnalyzeFormalArguments(Ins, CC_Mips_FixedArg);
3128 MipsFI->setFormalArgInfo(CCInfo.getNextStackOffset(),
3129 CCInfo.getInRegsParamsCount() > 0);
3130
3131 unsigned CurArgIdx = 0;
3132 CCInfo.rewindByValRegsInfo();
3133
3134 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3135 CCValAssign &VA = ArgLocs[i];
3136 if (Ins[i].isOrigArg()) {
3137 std::advance(FuncArg, Ins[i].getOrigArgIndex() - CurArgIdx);
3138 CurArgIdx = Ins[i].getOrigArgIndex();
3139 }
3140 EVT ValVT = VA.getValVT();
3141 ISD::ArgFlagsTy Flags = Ins[i].Flags;
3142 bool IsRegLoc = VA.isRegLoc();
3143
3144 if (Flags.isByVal()) {
3145 assert(Ins[i].isOrigArg() && "Byval arguments cannot be implicit")((Ins[i].isOrigArg() && "Byval arguments cannot be implicit"
) ? static_cast<void> (0) : __assert_fail ("Ins[i].isOrigArg() && \"Byval arguments cannot be implicit\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/Target/Mips/MipsISelLowering.cpp"
, 3145, __PRETTY_FUNCTION__))
;
3146 unsigned FirstByValReg, LastByValReg;
3147 unsigned ByValIdx = CCInfo.getInRegsParamsProcessed();
3148 CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg);
3149
3150 assert(Flags.getByValSize() &&((Flags.getByValSize() && "ByVal args of size 0 should have been ignored by front-end."
) ? static_cast<void> (0) : __assert_fail ("Flags.getByValSize() && \"ByVal args of size 0 should have been ignored by front-end.\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/Target/Mips/MipsISelLowering.cpp"
, 3151, __PRETTY_FUNCTION__))
3151 "ByVal args of size 0 should have been ignored by front-end.")((Flags.getByValSize() && "ByVal args of size 0 should have been ignored by front-end."
) ? static_cast<void> (0) : __assert_fail ("Flags.getByValSize() && \"ByVal args of size 0 should have been ignored by front-end.\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/Target/Mips/MipsISelLowering.cpp"
, 3151, __PRETTY_FUNCTION__))
;
3152 assert(ByValIdx < CCInfo.getInRegsParamsCount())((ByValIdx < CCInfo.getInRegsParamsCount()) ? static_cast<
void> (0) : __assert_fail ("ByValIdx < CCInfo.getInRegsParamsCount()"
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/Target/Mips/MipsISelLowering.cpp"
, 3152, __PRETTY_FUNCTION__))
;
3153 copyByValRegs(Chain, DL, OutChains, DAG, Flags, InVals, &*FuncArg,
3154 FirstByValReg, LastByValReg, VA, CCInfo);
3155 CCInfo.nextInRegsParam();
3156 continue;
3157 }
3158
3159 // Arguments stored on registers
3160 if (IsRegLoc) {
3161 MVT RegVT = VA.getLocVT();
3162 unsigned ArgReg = VA.getLocReg();
3163 const TargetRegisterClass *RC = getRegClassFor(RegVT);
3164
3165 // Transform the arguments stored on
3166 // physical registers into virtual ones
3167 unsigned Reg = addLiveIn(DAG.getMachineFunction(), ArgReg, RC);
3168 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT);
3169
3170 ArgValue = UnpackFromArgumentSlot(ArgValue, VA, Ins[i].ArgVT, DL, DAG);
3171
3172 // Handle floating point arguments passed in integer registers and
3173 // long double arguments passed in floating point registers.
3174 if ((RegVT == MVT::i32 && ValVT == MVT::f32) ||
3175 (RegVT == MVT::i64 && ValVT == MVT::f64) ||
3176 (RegVT == MVT::f64 && ValVT == MVT::i64))
3177 ArgValue = DAG.getNode(ISD::BITCAST, DL, ValVT, ArgValue);
3178 else if (ABI.IsO32() && RegVT == MVT::i32 &&
3179 ValVT == MVT::f64) {
3180 unsigned Reg2 = addLiveIn(DAG.getMachineFunction(),
3181 getNextIntArgReg(ArgReg), RC);
3182 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, DL, Reg2, RegVT);
3183 if (!Subtarget.isLittle())
3184 std::swap(ArgValue, ArgValue2);
3185 ArgValue = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64,
3186 ArgValue, ArgValue2);
3187 }
3188
3189 InVals.push_back(ArgValue);
3190 } else { // VA.isRegLoc()
3191 MVT LocVT = VA.getLocVT();
3192
3193 if (ABI.IsO32()) {
3194 // We ought to be able to use LocVT directly but O32 sets it to i32
3195 // when allocating floating point values to integer registers.
3196 // This shouldn't influence how we load the value into registers unless
3197 // we are targeting softfloat.
3198 if (VA.getValVT().isFloatingPoint() && !Subtarget.useSoftFloat())
3199 LocVT = VA.getValVT();
3200 }
3201
3202 // sanity check
3203 assert(VA.isMemLoc())((VA.isMemLoc()) ? static_cast<void> (0) : __assert_fail
("VA.isMemLoc()", "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/Target/Mips/MipsISelLowering.cpp"
, 3203, __PRETTY_FUNCTION__))
;
3204
3205 // The stack pointer offset is relative to the caller stack frame.
3206 int FI = MFI.CreateFixedObject(LocVT.getSizeInBits() / 8,
3207 VA.getLocMemOffset(), true);
3208
3209 // Create load nodes to retrieve arguments from the stack
3210 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
3211 SDValue ArgValue = DAG.getLoad(
3212 LocVT, DL, Chain, FIN,
3213 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI));
3214 OutChains.push_back(ArgValue.getValue(1));
3215
3216 ArgValue = UnpackFromArgumentSlot(ArgValue, VA, Ins[i].ArgVT, DL, DAG);
3217
3218 InVals.push_back(ArgValue);
3219 }
3220 }
3221
3222 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3223 // The mips ABIs for returning structs by value requires that we copy
3224 // the sret argument into $v0 for the return. Save the argument into
3225 // a virtual register so that we can access it from the return points.
3226 if (Ins[i].Flags.isSRet()) {
3227 unsigned Reg = MipsFI->getSRetReturnReg();
3228 if (!Reg) {
3229 Reg = MF.getRegInfo().createVirtualRegister(
3230 getRegClassFor(ABI.IsN64() ? MVT::i64 : MVT::i32));
3231 MipsFI->setSRetReturnReg(Reg);
3232 }
3233 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), DL, Reg, InVals[i]);
3234 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Copy, Chain);
3235 break;
3236 }
3237 }
3238
3239 if (IsVarArg)
3240 writeVarArgRegs(OutChains, Chain, DL, DAG, CCInfo);
3241
3242 // All stores are grouped in one node to allow the matching between
3243 // the size of Ins and InVals. This only happens when on varg functions
3244 if (!OutChains.empty()) {
3245 OutChains.push_back(Chain);
3246 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains);
3247 }
3248
3249 return Chain;
3250}
3251
3252//===----------------------------------------------------------------------===//
3253// Return Value Calling Convention Implementation
3254//===----------------------------------------------------------------------===//
3255
3256bool
3257MipsTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
3258 MachineFunction &MF, bool IsVarArg,
3259 const SmallVectorImpl<ISD::OutputArg> &Outs,
3260 LLVMContext &Context) const {
3261 SmallVector<CCValAssign, 16> RVLocs;
3262 MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
3263 return CCInfo.CheckReturn(Outs, RetCC_Mips);
3264}
3265
3266bool
3267MipsTargetLowering::shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const {
3268 if (Subtarget.hasMips3() && Subtarget.useSoftFloat()) {
3269 if (Type == MVT::i32)
3270 return true;
3271 }
3272 return IsSigned;
3273}
3274
3275SDValue
3276MipsTargetLowering::LowerInterruptReturn(SmallVectorImpl<SDValue> &RetOps,
3277 const SDLoc &DL,
3278 SelectionDAG &DAG) const {
3279
3280 MachineFunction &MF = DAG.getMachineFunction();
3281 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
3282
3283 MipsFI->setISR();
3284
3285 return DAG.getNode(MipsISD::ERet, DL, MVT::Other, RetOps);
3286}
3287
3288SDValue
3289MipsTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
3290 bool IsVarArg,
3291 const SmallVectorImpl<ISD::OutputArg> &Outs,
3292 const SmallVectorImpl<SDValue> &OutVals,
3293 const SDLoc &DL, SelectionDAG &DAG) const {
3294 // CCValAssign - represent the assignment of
3295 // the return value to a location
3296 SmallVector<CCValAssign, 16> RVLocs;
3297 MachineFunction &MF = DAG.getMachineFunction();
3298
3299 // CCState - Info about the registers and stack slot.
3300 MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext());
3301
3302 // Analyze return values.
3303 CCInfo.AnalyzeReturn(Outs, RetCC_Mips);
3304
3305 SDValue Flag;
3306 SmallVector<SDValue, 4> RetOps(1, Chain);
3307
3308 // Copy the result values into the output registers.
3309 for (unsigned i = 0; i != RVLocs.size(); ++i) {
3310 SDValue Val = OutVals[i];
3311 CCValAssign &VA = RVLocs[i];
3312 assert(VA.isRegLoc() && "Can only return in registers!")((VA.isRegLoc() && "Can only return in registers!") ?
static_cast<void> (0) : __assert_fail ("VA.isRegLoc() && \"Can only return in registers!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/Target/Mips/MipsISelLowering.cpp"
, 3312, __PRETTY_FUNCTION__))
;
3313 bool UseUpperBits = false;
3314
3315 switch (VA.getLocInfo()) {
3316 default:
3317 llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/Target/Mips/MipsISelLowering.cpp"
, 3317)
;
3318 case CCValAssign::Full:
3319 break;
3320 case CCValAssign::BCvt:
3321 Val = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Val);
3322 break;
3323 case CCValAssign::AExtUpper:
3324 UseUpperBits = true;
3325 LLVM_FALLTHROUGH[[clang::fallthrough]];
3326 case CCValAssign::AExt:
3327 Val = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Val);
3328 break;
3329 case CCValAssign::ZExtUpper:
3330 UseUpperBits = true;
3331 LLVM_FALLTHROUGH[[clang::fallthrough]];
3332 case CCValAssign::ZExt:
3333 Val = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Val);
3334 break;
3335 case CCValAssign::SExtUpper:
3336 UseUpperBits = true;
3337 LLVM_FALLTHROUGH[[clang::fallthrough]];
3338 case CCValAssign::SExt:
3339 Val = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Val);
3340 break;
3341 }
3342
3343 if (UseUpperBits) {
3344 unsigned ValSizeInBits = Outs[i].ArgVT.getSizeInBits();
3345 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
3346 Val = DAG.getNode(
3347 ISD::SHL, DL, VA.getLocVT(), Val,
3348 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT()));
3349 }
3350
3351 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Flag);
3352
3353 // Guarantee that all emitted copies are stuck together with flags.
3354 Flag = Chain.getValue(1);
3355 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
3356 }
3357
3358 // The mips ABIs for returning structs by value requires that we copy
3359 // the sret argument into $v0 for the return. We saved the argument into
3360 // a virtual register in the entry block, so now we copy the value out
3361 // and into $v0.
3362 if (MF.getFunction()->hasStructRetAttr()) {
3363 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
3364 unsigned Reg = MipsFI->getSRetReturnReg();
3365
3366 if (!Reg)
3367 llvm_unreachable("sret virtual register not created in the entry block")::llvm::llvm_unreachable_internal("sret virtual register not created in the entry block"
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/Target/Mips/MipsISelLowering.cpp"
, 3367)
;
3368 SDValue Val =
3369 DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(DAG.getDataLayout()));
3370 unsigned V0 = ABI.IsN64() ? Mips::V0_64 : Mips::V0;
3371
3372 Chain = DAG.getCopyToReg(Chain, DL, V0, Val, Flag);
3373 Flag = Chain.getValue(1);
3374 RetOps.push_back(DAG.getRegister(V0, getPointerTy(DAG.getDataLayout())));
3375 }
3376
3377 RetOps[0] = Chain; // Update chain.
3378
3379 // Add the flag if we have it.
3380 if (Flag.getNode())
3381 RetOps.push_back(Flag);
3382
3383 // ISRs must use "eret".
3384 if (DAG.getMachineFunction().getFunction()->hasFnAttribute("interrupt"))
3385 return LowerInterruptReturn(RetOps, DL, DAG);
3386
3387 // Standard return on Mips is a "jr $ra"
3388 return DAG.getNode(MipsISD::Ret, DL, MVT::Other, RetOps);
3389}
3390
3391//===----------------------------------------------------------------------===//
3392// Mips Inline Assembly Support
3393//===----------------------------------------------------------------------===//
3394
3395/// getConstraintType - Given a constraint letter, return the type of
3396/// constraint it is for this target.
3397MipsTargetLowering::ConstraintType
3398MipsTargetLowering::getConstraintType(StringRef Constraint) const {
3399 // Mips specific constraints
3400 // GCC config/mips/constraints.md
3401 //
3402 // 'd' : An address register. Equivalent to r
3403 // unless generating MIPS16 code.
3404 // 'y' : Equivalent to r; retained for
3405 // backwards compatibility.
3406 // 'c' : A register suitable for use in an indirect
3407 // jump. This will always be $25 for -mabicalls.
3408 // 'l' : The lo register. 1 word storage.
3409 // 'x' : The hilo register pair. Double word storage.
3410 if (Constraint.size() == 1) {
3411 switch (Constraint[0]) {
3412 default : break;
3413 case 'd':
3414 case 'y':
3415 case 'f':
3416 case 'c':
3417 case 'l':
3418 case 'x':
3419 return C_RegisterClass;
3420 case 'R':
3421 return C_Memory;
3422 }
3423 }
3424
3425 if (Constraint == "ZC")
3426 return C_Memory;
3427
3428 return TargetLowering::getConstraintType(Constraint);
3429}
3430
3431/// Examine constraint type and operand type and determine a weight value.
3432/// This object must already have been set up with the operand type
3433/// and the current alternative constraint selected.
3434TargetLowering::ConstraintWeight
3435MipsTargetLowering::getSingleConstraintMatchWeight(
3436 AsmOperandInfo &info, const char *constraint) const {
3437 ConstraintWeight weight = CW_Invalid;
3438 Value *CallOperandVal = info.CallOperandVal;
3439 // If we don't have a value, we can't do a match,
3440 // but allow it at the lowest weight.
3441 if (!CallOperandVal)
3442 return CW_Default;
3443 Type *type = CallOperandVal->getType();
3444 // Look at the constraint type.
3445 switch (*constraint) {
3446 default:
3447 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
3448 break;
3449 case 'd':
3450 case 'y':
3451 if (type->isIntegerTy())
3452 weight = CW_Register;
3453 break;
3454 case 'f': // FPU or MSA register
3455 if (Subtarget.hasMSA() && type->isVectorTy() &&
3456 cast<VectorType>(type)->getBitWidth() == 128)
3457 weight = CW_Register;
3458 else if (type->isFloatTy())
3459 weight = CW_Register;
3460 break;
3461 case 'c': // $25 for indirect jumps
3462 case 'l': // lo register
3463 case 'x': // hilo register pair
3464 if (type->isIntegerTy())
3465 weight = CW_SpecificReg;
3466 break;
3467 case 'I': // signed 16 bit immediate
3468 case 'J': // integer zero
3469 case 'K': // unsigned 16 bit immediate
3470 case 'L': // signed 32 bit immediate where lower 16 bits are 0
3471 case 'N': // immediate in the range of -65535 to -1 (inclusive)
3472 case 'O': // signed 15 bit immediate (+- 16383)
3473 case 'P': // immediate in the range of 65535 to 1 (inclusive)
3474 if (isa<ConstantInt>(CallOperandVal))
3475 weight = CW_Constant;
3476 break;
3477 case 'R':
3478 weight = CW_Memory;
3479 break;
3480 }
3481 return weight;
3482}
3483
3484/// This is a helper function to parse a physical register string and split it
3485/// into non-numeric and numeric parts (Prefix and Reg). The first boolean flag
3486/// that is returned indicates whether parsing was successful. The second flag
3487/// is true if the numeric part exists.
3488static std::pair<bool, bool> parsePhysicalReg(StringRef C, StringRef &Prefix,
3489 unsigned long long &Reg) {
3490 if (C.front() != '{' || C.back() != '}')
3491 return std::make_pair(false, false);
3492
3493 // Search for the first numeric character.
3494 StringRef::const_iterator I, B = C.begin() + 1, E = C.end() - 1;
3495 I = std::find_if(B, E, isdigit);
3496
3497 Prefix = StringRef(B, I - B);
3498
3499 // The second flag is set to false if no numeric characters were found.
3500 if (I == E)
3501 return std::make_pair(true, false);
3502
3503 // Parse the numeric characters.
3504 return std::make_pair(!getAsUnsignedInteger(StringRef(I, E - I), 10, Reg),
3505 true);
3506}
3507
3508std::pair<unsigned, const TargetRegisterClass *> MipsTargetLowering::
3509parseRegForInlineAsmConstraint(StringRef C, MVT VT) const {
3510 const TargetRegisterInfo *TRI =
3511 Subtarget.getRegisterInfo();
3512 const TargetRegisterClass *RC;
3513 StringRef Prefix;
3514 unsigned long long Reg;
3515
3516 std::pair<bool, bool> R = parsePhysicalReg(C, Prefix, Reg);
3517
3518 if (!R.first)
3519 return std::make_pair(0U, nullptr);
3520
3521 if ((Prefix == "hi" || Prefix == "lo")) { // Parse hi/lo.
3522 // No numeric characters follow "hi" or "lo".
3523 if (R.second)
3524 return std::make_pair(0U, nullptr);
3525
3526 RC = TRI->getRegClass(Prefix == "hi" ?
3527 Mips::HI32RegClassID : Mips::LO32RegClassID);
3528 return std::make_pair(*(RC->begin()), RC);
3529 } else if (Prefix.startswith("$msa")) {
3530 // Parse $msa(ir|csr|access|save|modify|request|map|unmap)
3531
3532 // No numeric characters follow the name.
3533 if (R.second)
3534 return std::make_pair(0U, nullptr);
3535
3536 Reg = StringSwitch<unsigned long long>(Prefix)
3537 .Case("$msair", Mips::MSAIR)
3538 .Case("$msacsr", Mips::MSACSR)
3539 .Case("$msaaccess", Mips::MSAAccess)
3540 .Case("$msasave", Mips::MSASave)
3541 .Case("$msamodify", Mips::MSAModify)
3542 .Case("$msarequest", Mips::MSARequest)
3543 .Case("$msamap", Mips::MSAMap)
3544 .Case("$msaunmap", Mips::MSAUnmap)
3545 .Default(0);
3546
3547 if (!Reg)
3548 return std::make_pair(0U, nullptr);
3549
3550 RC = TRI->getRegClass(Mips::MSACtrlRegClassID);
3551 return std::make_pair(Reg, RC);
3552 }
3553
3554 if (!R.second)
3555 return std::make_pair(0U, nullptr);
3556
3557 if (Prefix == "$f") { // Parse $f0-$f31.
3558 // If the size of FP registers is 64-bit or Reg is an even number, select
3559 // the 64-bit register class. Otherwise, select the 32-bit register class.
3560 if (VT == MVT::Other)
3561 VT = (Subtarget.isFP64bit() || !(Reg % 2)) ? MVT::f64 : MVT::f32;
3562
3563 RC = getRegClassFor(VT);
3564
3565 if (RC == &Mips::AFGR64RegClass) {
3566 assert(Reg % 2 == 0)((Reg % 2 == 0) ? static_cast<void> (0) : __assert_fail
("Reg % 2 == 0", "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/Target/Mips/MipsISelLowering.cpp"
, 3566, __PRETTY_FUNCTION__))
;
3567 Reg >>= 1;
3568 }
3569 } else if (Prefix == "$fcc") // Parse $fcc0-$fcc7.
3570 RC = TRI->getRegClass(Mips::FCCRegClassID);
3571 else if (Prefix == "$w") { // Parse $w0-$w31.
3572 RC = getRegClassFor((VT == MVT::Other) ? MVT::v16i8 : VT);
3573 } else { // Parse $0-$31.
3574 assert(Prefix == "$")((Prefix == "$") ? static_cast<void> (0) : __assert_fail
("Prefix == \"$\"", "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/Target/Mips/MipsISelLowering.cpp"
, 3574, __PRETTY_FUNCTION__))
;
3575 RC = getRegClassFor((VT == MVT::Other) ? MVT::i32 : VT);
3576 }
3577
3578 assert(Reg < RC->getNumRegs())((Reg < RC->getNumRegs()) ? static_cast<void> (0)
: __assert_fail ("Reg < RC->getNumRegs()", "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/Target/Mips/MipsISelLowering.cpp"
, 3578, __PRETTY_FUNCTION__))
;
3579 return std::make_pair(*(RC->begin() + Reg), RC);
3580}
3581
3582/// Given a register class constraint, like 'r', if this corresponds directly
3583/// to an LLVM register class, return a register of 0 and the register class
3584/// pointer.
3585std::pair<unsigned, const TargetRegisterClass *>
3586MipsTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
3587 StringRef Constraint,
3588 MVT VT) const {
3589 if (Constraint.size() == 1) {
3590 switch (Constraint[0]) {
3591 case 'd': // Address register. Same as 'r' unless generating MIPS16 code.
3592 case 'y': // Same as 'r'. Exists for compatibility.
3593 case 'r':
3594 if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) {
3595 if (Subtarget.inMips16Mode())
3596 return std::make_pair(0U, &Mips::CPU16RegsRegClass);
3597 return std::make_pair(0U, &Mips::GPR32RegClass);
3598 }
3599 if (VT == MVT::i64 && !Subtarget.isGP64bit())
3600 return std::make_pair(0U, &Mips::GPR32RegClass);
3601 if (VT == MVT::i64 && Subtarget.isGP64bit())
3602 return std::make_pair(0U, &Mips::GPR64RegClass);
3603 // This will generate an error message
3604 return std::make_pair(0U, nullptr);
3605 case 'f': // FPU or MSA register
3606 if (VT == MVT::v16i8)
3607 return std::make_pair(0U, &Mips::MSA128BRegClass);
3608 else if (VT == MVT::v8i16 || VT == MVT::v8f16)
3609 return std::make_pair(0U, &Mips::MSA128HRegClass);
3610 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
3611 return std::make_pair(0U, &Mips::MSA128WRegClass);
3612 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
3613 return std::make_pair(0U, &Mips::MSA128DRegClass);
3614 else if (VT == MVT::f32)
3615 return std::make_pair(0U, &Mips::FGR32RegClass);
3616 else if ((VT == MVT::f64) && (!Subtarget.isSingleFloat())) {
3617 if (Subtarget.isFP64bit())
3618 return std::make_pair(0U, &Mips::FGR64RegClass);
3619 return std::make_pair(0U, &Mips::AFGR64RegClass);
3620 }
3621 break;
3622 case 'c': // register suitable for indirect jump
3623 if (VT == MVT::i32)
3624 return std::make_pair((unsigned)Mips::T9, &Mips::GPR32RegClass);
3625 assert(VT == MVT::i64 && "Unexpected type.")((VT == MVT::i64 && "Unexpected type.") ? static_cast
<void> (0) : __assert_fail ("VT == MVT::i64 && \"Unexpected type.\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/Target/Mips/MipsISelLowering.cpp"
, 3625, __PRETTY_FUNCTION__))
;
3626 return std::make_pair((unsigned)Mips::T9_64, &Mips::GPR64RegClass);
3627 case 'l': // register suitable for indirect jump
3628 if (VT == MVT::i32)
3629 return std::make_pair((unsigned)Mips::LO0, &Mips::LO32RegClass);
3630 return std::make_pair((unsigned)Mips::LO0_64, &Mips::LO64RegClass);
3631 case 'x': // register suitable for indirect jump
3632 // Fixme: Not triggering the use of both hi and low
3633 // This will generate an error message
3634 return std::make_pair(0U, nullptr);
3635 }
3636 }
3637
3638 std::pair<unsigned, const TargetRegisterClass *> R;
3639 R = parseRegForInlineAsmConstraint(Constraint, VT);
3640
3641 if (R.second)
3642 return R;
3643
3644 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
3645}
3646
3647/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
3648/// vector. If it is invalid, don't add anything to Ops.
3649void MipsTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
3650 std::string &Constraint,
3651 std::vector<SDValue>&Ops,
3652 SelectionDAG &DAG) const {
3653 SDLoc DL(Op);
3654 SDValue Result;
3655
3656 // Only support length 1 constraints for now.
3657 if (Constraint.length() > 1) return;
3658
3659 char ConstraintLetter = Constraint[0];
3660 switch (ConstraintLetter) {
3661 default: break; // This will fall through to the generic implementation
3662 case 'I': // Signed 16 bit constant
3663 // If this fails, the parent routine will give an error
3664 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3665 EVT Type = Op.getValueType();
3666 int64_t Val = C->getSExtValue();
3667 if (isInt<16>(Val)) {
3668 Result = DAG.getTargetConstant(Val, DL, Type);
3669 break;
3670 }
3671 }
3672 return;
3673 case 'J': // integer zero
3674 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3675 EVT Type = Op.getValueType();
3676 int64_t Val = C->getZExtValue();
3677 if (Val == 0) {
3678 Result = DAG.getTargetConstant(0, DL, Type);
3679 break;
3680 }
3681 }
3682 return;
3683 case 'K': // unsigned 16 bit immediate
3684 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3685 EVT Type = Op.getValueType();
3686 uint64_t Val = (uint64_t)C->getZExtValue();
3687 if (isUInt<16>(Val)) {
3688 Result = DAG.getTargetConstant(Val, DL, Type);
3689 break;
3690 }
3691 }
3692 return;
3693 case 'L': // signed 32 bit immediate where lower 16 bits are 0
3694 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3695 EVT Type = Op.getValueType();
3696 int64_t Val = C->getSExtValue();
3697 if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)){
3698 Result = DAG.getTargetConstant(Val, DL, Type);
3699 break;
3700 }
3701 }
3702 return;
3703 case 'N': // immediate in the range of -65535 to -1 (inclusive)
3704 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3705 EVT Type = Op.getValueType();
3706 int64_t Val = C->getSExtValue();
3707 if ((Val >= -65535) && (Val <= -1)) {
3708 Result = DAG.getTargetConstant(Val, DL, Type);
3709 break;
3710 }
3711 }
3712 return;
3713 case 'O': // signed 15 bit immediate
3714 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3715 EVT Type = Op.getValueType();
3716 int64_t Val = C->getSExtValue();
3717 if ((isInt<15>(Val))) {
3718 Result = DAG.getTargetConstant(Val, DL, Type);
3719 break;
3720 }
3721 }
3722 return;
3723 case 'P': // immediate in the range of 1 to 65535 (inclusive)
3724 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3725 EVT Type = Op.getValueType();
3726 int64_t Val = C->getSExtValue();
3727 if ((Val <= 65535) && (Val >= 1)) {
3728 Result = DAG.getTargetConstant(Val, DL, Type);
3729 break;
3730 }
3731 }
3732 return;
3733 }
3734
3735 if (Result.getNode()) {
3736 Ops.push_back(Result);
3737 return;
3738 }
3739
3740 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
3741}
3742
3743bool MipsTargetLowering::isLegalAddressingMode(const DataLayout &DL,
3744 const AddrMode &AM, Type *Ty,
3745 unsigned AS) const {
3746 // No global is ever allowed as a base.
3747 if (AM.BaseGV)
3748 return false;
3749
3750 switch (AM.Scale) {
3751 case 0: // "r+i" or just "i", depending on HasBaseReg.
3752 break;
3753 case 1:
3754 if (!AM.HasBaseReg) // allow "r+i".
3755 break;
3756 return false; // disallow "r+r" or "r+r+i".
3757 default:
3758 return false;
3759 }
3760
3761 return true;
3762}
3763
3764bool
3765MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
3766 // The Mips target isn't yet aware of offsets.
3767 return false;
3768}
3769
3770EVT MipsTargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
3771 unsigned SrcAlign,
3772 bool IsMemset, bool ZeroMemset,
3773 bool MemcpyStrSrc,
3774 MachineFunction &MF) const {
3775 if (Subtarget.hasMips64())
3776 return MVT::i64;
3777
3778 return MVT::i32;
3779}
3780
3781bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3782 if (VT != MVT::f32 && VT != MVT::f64)
3783 return false;
3784 if (Imm.isNegZero())
3785 return false;
3786 return Imm.isZero();
3787}
3788
3789unsigned MipsTargetLowering::getJumpTableEncoding() const {
3790
3791 // FIXME: For space reasons this should be: EK_GPRel32BlockAddress.
3792 if (ABI.IsN64() && isPositionIndependent())
3793 return MachineJumpTableInfo::EK_GPRel64BlockAddress;
3794
3795 return TargetLowering::getJumpTableEncoding();
3796}
3797
3798bool MipsTargetLowering::useSoftFloat() const {
3799 return Subtarget.useSoftFloat();
3800}
3801
3802void MipsTargetLowering::copyByValRegs(
3803 SDValue Chain, const SDLoc &DL, std::vector<SDValue> &OutChains,
3804 SelectionDAG &DAG, const ISD::ArgFlagsTy &Flags,
3805 SmallVectorImpl<SDValue> &InVals, const Argument *FuncArg,
3806 unsigned FirstReg, unsigned LastReg, const CCValAssign &VA,
3807 MipsCCState &State) const {
3808 MachineFunction &MF = DAG.getMachineFunction();
3809 MachineFrameInfo &MFI = MF.getFrameInfo();
3810 unsigned GPRSizeInBytes = Subtarget.getGPRSizeInBytes();
3811 unsigned NumRegs = LastReg - FirstReg;
3812 unsigned RegAreaSize = NumRegs * GPRSizeInBytes;
3813 unsigned FrameObjSize = std::max(Flags.getByValSize(), RegAreaSize);
3814 int FrameObjOffset;
3815 ArrayRef<MCPhysReg> ByValArgRegs = ABI.GetByValArgRegs();
3816
3817 if (RegAreaSize)
3818 FrameObjOffset =
3819 (int)ABI.GetCalleeAllocdArgSizeInBytes(State.getCallingConv()) -
3820 (int)((ByValArgRegs.size() - FirstReg) * GPRSizeInBytes);
3821 else
3822 FrameObjOffset = VA.getLocMemOffset();
3823
3824 // Create frame object.
3825 EVT PtrTy = getPointerTy(DAG.getDataLayout());
3826 int FI = MFI.CreateFixedObject(FrameObjSize, FrameObjOffset, true);
3827 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
3828 InVals.push_back(FIN);
3829
3830 if (!NumRegs)
3831 return;
3832
3833 // Copy arg registers.
3834 MVT RegTy = MVT::getIntegerVT(GPRSizeInBytes * 8);
3835 const TargetRegisterClass *RC = getRegClassFor(RegTy);
3836
3837 for (unsigned I = 0; I < NumRegs; ++I) {
3838 unsigned ArgReg = ByValArgRegs[FirstReg + I];
3839 unsigned VReg = addLiveIn(MF, ArgReg, RC);
3840 unsigned Offset = I * GPRSizeInBytes;
3841 SDValue StorePtr = DAG.getNode(ISD::ADD, DL, PtrTy, FIN,
3842 DAG.getConstant(Offset, DL, PtrTy));
3843 SDValue Store = DAG.getStore(Chain, DL, DAG.getRegister(VReg, RegTy),
3844 StorePtr, MachinePointerInfo(FuncArg, Offset));
3845 OutChains.push_back(Store);
3846 }
3847}
3848
3849// Copy byVal arg to registers and stack.
3850void MipsTargetLowering::passByValArg(
3851 SDValue Chain, const SDLoc &DL,
3852 std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
3853 SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr,
3854 MachineFrameInfo &MFI, SelectionDAG &DAG, SDValue Arg, unsigned FirstReg,
3855 unsigned LastReg, const ISD::ArgFlagsTy &Flags, bool isLittle,
3856 const CCValAssign &VA) const {
3857 unsigned ByValSizeInBytes = Flags.getByValSize();
3858 unsigned OffsetInBytes = 0; // From beginning of struct
3859 unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes();
3860 unsigned Alignment = std::min(Flags.getByValAlign(), RegSizeInBytes);
3861 EVT PtrTy = getPointerTy(DAG.getDataLayout()),
3862 RegTy = MVT::getIntegerVT(RegSizeInBytes * 8);
3863 unsigned NumRegs = LastReg - FirstReg;
3864
3865 if (NumRegs) {
3866 ArrayRef<MCPhysReg> ArgRegs = ABI.GetByValArgRegs();
3867 bool LeftoverBytes = (NumRegs * RegSizeInBytes > ByValSizeInBytes);
3868 unsigned I = 0;
3869
3870 // Copy words to registers.
3871 for (; I < NumRegs - LeftoverBytes; ++I, OffsetInBytes += RegSizeInBytes) {
3872 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
3873 DAG.getConstant(OffsetInBytes, DL, PtrTy));
3874 SDValue LoadVal = DAG.getLoad(RegTy, DL, Chain, LoadPtr,
3875 MachinePointerInfo(), Alignment);
3876 MemOpChains.push_back(LoadVal.getValue(1));
3877 unsigned ArgReg = ArgRegs[FirstReg + I];
3878 RegsToPass.push_back(std::make_pair(ArgReg, LoadVal));
3879 }
3880
3881 // Return if the struct has been fully copied.
3882 if (ByValSizeInBytes == OffsetInBytes)
3883 return;
3884
3885 // Copy the remainder of the byval argument with sub-word loads and shifts.
3886 if (LeftoverBytes) {
3887 SDValue Val;
3888
3889 for (unsigned LoadSizeInBytes = RegSizeInBytes / 2, TotalBytesLoaded = 0;
3890 OffsetInBytes < ByValSizeInBytes; LoadSizeInBytes /= 2) {
3891 unsigned RemainingSizeInBytes = ByValSizeInBytes - OffsetInBytes;
3892
3893 if (RemainingSizeInBytes < LoadSizeInBytes)
3894 continue;
3895
3896 // Load subword.
3897 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
3898 DAG.getConstant(OffsetInBytes, DL,
3899 PtrTy));
3900 SDValue LoadVal = DAG.getExtLoad(
3901 ISD::ZEXTLOAD, DL, RegTy, Chain, LoadPtr, MachinePointerInfo(),
3902 MVT::getIntegerVT(LoadSizeInBytes * 8), Alignment);
3903 MemOpChains.push_back(LoadVal.getValue(1));
3904
3905 // Shift the loaded value.
3906 unsigned Shamt;
3907
3908 if (isLittle)
3909 Shamt = TotalBytesLoaded * 8;
3910 else
3911 Shamt = (RegSizeInBytes - (TotalBytesLoaded + LoadSizeInBytes)) * 8;
3912
3913 SDValue Shift = DAG.getNode(ISD::SHL, DL, RegTy, LoadVal,
3914 DAG.getConstant(Shamt, DL, MVT::i32));
3915
3916 if (Val.getNode())
3917 Val = DAG.getNode(ISD::OR, DL, RegTy, Val, Shift);
3918 else
3919 Val = Shift;
3920
3921 OffsetInBytes += LoadSizeInBytes;
3922 TotalBytesLoaded += LoadSizeInBytes;
3923 Alignment = std::min(Alignment, LoadSizeInBytes);
3924 }
3925
3926 unsigned ArgReg = ArgRegs[FirstReg + I];
3927 RegsToPass.push_back(std::make_pair(ArgReg, Val));
3928 return;
3929 }
3930 }
3931
3932 // Copy remainder of byval arg to it with memcpy.
3933 unsigned MemCpySize = ByValSizeInBytes - OffsetInBytes;
3934 SDValue Src = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
3935 DAG.getConstant(OffsetInBytes, DL, PtrTy));
3936 SDValue Dst = DAG.getNode(ISD::ADD, DL, PtrTy, StackPtr,
3937 DAG.getIntPtrConstant(VA.getLocMemOffset(), DL));
3938 Chain = DAG.getMemcpy(Chain, DL, Dst, Src,
3939 DAG.getConstant(MemCpySize, DL, PtrTy),
3940 Alignment, /*isVolatile=*/false, /*AlwaysInline=*/false,
3941 /*isTailCall=*/false,
3942 MachinePointerInfo(), MachinePointerInfo());
3943 MemOpChains.push_back(Chain);
3944}
3945
3946void MipsTargetLowering::writeVarArgRegs(std::vector<SDValue> &OutChains,
3947 SDValue Chain, const SDLoc &DL,
3948 SelectionDAG &DAG,
3949 CCState &State) const {
3950 ArrayRef<MCPhysReg> ArgRegs = ABI.GetVarArgRegs();
3951 unsigned Idx = State.getFirstUnallocated(ArgRegs);
3952 unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes();
3953 MVT RegTy = MVT::getIntegerVT(RegSizeInBytes * 8);
3954 const TargetRegisterClass *RC = getRegClassFor(RegTy);
3955 MachineFunction &MF = DAG.getMachineFunction();
3956 MachineFrameInfo &MFI = MF.getFrameInfo();
3957 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
3958
3959 // Offset of the first variable argument from stack pointer.
3960 int VaArgOffset;
3961
3962 if (ArgRegs.size() == Idx)
3963 VaArgOffset = alignTo(State.getNextStackOffset(), RegSizeInBytes);
3964 else {
3965 VaArgOffset =
3966 (int)ABI.GetCalleeAllocdArgSizeInBytes(State.getCallingConv()) -
3967 (int)(RegSizeInBytes * (ArgRegs.size() - Idx));
3968 }
3969
3970 // Record the frame index of the first variable argument
3971 // which is a value necessary to VASTART.
3972 int FI = MFI.CreateFixedObject(RegSizeInBytes, VaArgOffset, true);
3973 MipsFI->setVarArgsFrameIndex(FI);
3974
3975 // Copy the integer registers that have not been used for argument passing
3976 // to the argument register save area. For O32, the save area is allocated
3977 // in the caller's stack frame, while for N32/64, it is allocated in the
3978 // callee's stack frame.
3979 for (unsigned I = Idx; I < ArgRegs.size();
3980 ++I, VaArgOffset += RegSizeInBytes) {
3981 unsigned Reg = addLiveIn(MF, ArgRegs[I], RC);
3982 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegTy);
3983 FI = MFI.CreateFixedObject(RegSizeInBytes, VaArgOffset, true);
3984 SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
3985 SDValue Store =
3986 DAG.getStore(Chain, DL, ArgValue, PtrOff, MachinePointerInfo());
3987 cast<StoreSDNode>(Store.getNode())->getMemOperand()->setValue(
3988 (Value *)nullptr);
3989 OutChains.push_back(Store);
3990 }
3991}
3992
3993void MipsTargetLowering::HandleByVal(CCState *State, unsigned &Size,
3994 unsigned Align) const {
3995 const TargetFrameLowering *TFL = Subtarget.getFrameLowering();
3996
3997 assert(Size && "Byval argument's size shouldn't be 0.")((Size && "Byval argument's size shouldn't be 0.") ? static_cast
<void> (0) : __assert_fail ("Size && \"Byval argument's size shouldn't be 0.\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/Target/Mips/MipsISelLowering.cpp"
, 3997, __PRETTY_FUNCTION__))
;
3998
3999 Align = std::min(Align, TFL->getStackAlignment());
4000
4001 unsigned FirstReg = 0;
4002 unsigned NumRegs = 0;
4003
4004 if (State->getCallingConv() != CallingConv::Fast) {
4005 unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes();
4006 ArrayRef<MCPhysReg> IntArgRegs = ABI.GetByValArgRegs();
4007 // FIXME: The O32 case actually describes no shadow registers.
4008 const MCPhysReg *ShadowRegs =
4009 ABI.IsO32() ? IntArgRegs.data() : Mips64DPRegs;
4010
4011 // We used to check the size as well but we can't do that anymore since
4012 // CCState::HandleByVal() rounds up the size after calling this function.
4013 assert(!(Align % RegSizeInBytes) &&((!(Align % RegSizeInBytes) && "Byval argument's alignment should be a multiple of"
"RegSizeInBytes.") ? static_cast<void> (0) : __assert_fail
("!(Align % RegSizeInBytes) && \"Byval argument's alignment should be a multiple of\" \"RegSizeInBytes.\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/Target/Mips/MipsISelLowering.cpp"
, 4015, __PRETTY_FUNCTION__))
4014 "Byval argument's alignment should be a multiple of"((!(Align % RegSizeInBytes) && "Byval argument's alignment should be a multiple of"
"RegSizeInBytes.") ? static_cast<void> (0) : __assert_fail
("!(Align % RegSizeInBytes) && \"Byval argument's alignment should be a multiple of\" \"RegSizeInBytes.\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/Target/Mips/MipsISelLowering.cpp"
, 4015, __PRETTY_FUNCTION__))
4015 "RegSizeInBytes.")((!(Align % RegSizeInBytes) && "Byval argument's alignment should be a multiple of"
"RegSizeInBytes.") ? static_cast<void> (0) : __assert_fail
("!(Align % RegSizeInBytes) && \"Byval argument's alignment should be a multiple of\" \"RegSizeInBytes.\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/Target/Mips/MipsISelLowering.cpp"
, 4015, __PRETTY_FUNCTION__))
;
4016
4017 FirstReg = State->getFirstUnallocated(IntArgRegs);
4018
4019 // If Align > RegSizeInBytes, the first arg register must be even.
4020 // FIXME: This condition happens to do the right thing but it's not the
4021 // right way to test it. We want to check that the stack frame offset
4022 // of the register is aligned.
4023 if ((Align > RegSizeInBytes) && (FirstReg % 2)) {
4024 State->AllocateReg(IntArgRegs[FirstReg], ShadowRegs[FirstReg]);
4025 ++FirstReg;
4026 }
4027
4028 // Mark the registers allocated.
4029 Size = alignTo(Size, RegSizeInBytes);
4030 for (unsigned I = FirstReg; Size > 0 && (I < IntArgRegs.size());
4031 Size -= RegSizeInBytes, ++I, ++NumRegs)
4032 State->AllocateReg(IntArgRegs[I], ShadowRegs[I]);
4033 }
4034
4035 State->addInRegsParamInfo(FirstReg, FirstReg + NumRegs);
4036}
4037
4038MachineBasicBlock *MipsTargetLowering::emitPseudoSELECT(MachineInstr &MI,
4039 MachineBasicBlock *BB,
4040 bool isFPCmp,
4041 unsigned Opc) const {
4042 assert(!(Subtarget.hasMips4() || Subtarget.hasMips32()) &&((!(Subtarget.hasMips4() || Subtarget.hasMips32()) &&
"Subtarget already supports SELECT nodes with the use of" "conditional-move instructions."
) ? static_cast<void> (0) : __assert_fail ("!(Subtarget.hasMips4() || Subtarget.hasMips32()) && \"Subtarget already supports SELECT nodes with the use of\" \"conditional-move instructions.\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/Target/Mips/MipsISelLowering.cpp"
, 4044, __PRETTY_FUNCTION__))
4043 "Subtarget already supports SELECT nodes with the use of"((!(Subtarget.hasMips4() || Subtarget.hasMips32()) &&
"Subtarget already supports SELECT nodes with the use of" "conditional-move instructions."
) ? static_cast<void> (0) : __assert_fail ("!(Subtarget.hasMips4() || Subtarget.hasMips32()) && \"Subtarget already supports SELECT nodes with the use of\" \"conditional-move instructions.\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/Target/Mips/MipsISelLowering.cpp"
, 4044, __PRETTY_FUNCTION__))
4044 "conditional-move instructions.")((!(Subtarget.hasMips4() || Subtarget.hasMips32()) &&
"Subtarget already supports SELECT nodes with the use of" "conditional-move instructions."
) ? static_cast<void> (0) : __assert_fail ("!(Subtarget.hasMips4() || Subtarget.hasMips32()) && \"Subtarget already supports SELECT nodes with the use of\" \"conditional-move instructions.\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/Target/Mips/MipsISelLowering.cpp"
, 4044, __PRETTY_FUNCTION__))
;
4045
4046 const TargetInstrInfo *TII =
4047 Subtarget.getInstrInfo();
4048 DebugLoc DL = MI.getDebugLoc();
4049
4050 // To "insert" a SELECT instruction, we actually have to insert the
4051 // diamond control-flow pattern. The incoming instruction knows the
4052 // destination vreg to set, the condition code register to branch on, the
4053 // true/false values to select between, and a branch opcode to use.
4054 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4055 MachineFunction::iterator It = ++BB->getIterator();
4056
4057 // thisMBB:
4058 // ...
4059 // TrueVal = ...
4060 // setcc r1, r2, r3
4061 // bNE r1, r0, copy1MBB
4062 // fallthrough --> copy0MBB
4063 MachineBasicBlock *thisMBB = BB;
4064 MachineFunction *F = BB->getParent();
4065 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
4066 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
4067 F->insert(It, copy0MBB);
4068 F->insert(It, sinkMBB);
4069
4070 // Transfer the remainder of BB and its successor edges to sinkMBB.
4071 sinkMBB->splice(sinkMBB->begin(), BB,
4072 std::next(MachineBasicBlock::iterator(MI)), BB->end());
4073 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
4074
4075 // Next, add the true and fallthrough blocks as its successors.
4076 BB->addSuccessor(copy0MBB);
4077 BB->addSuccessor(sinkMBB);
4078
4079 if (isFPCmp) {
4080 // bc1[tf] cc, sinkMBB
4081 BuildMI(BB, DL, TII->get(Opc))
4082 .addReg(MI.getOperand(1).getReg())
4083 .addMBB(sinkMBB);
4084 } else {
4085 // bne rs, $0, sinkMBB
4086 BuildMI(BB, DL, TII->get(Opc))
4087 .addReg(MI.getOperand(1).getReg())
4088 .addReg(Mips::ZERO)
4089 .addMBB(sinkMBB);
4090 }
4091
4092 // copy0MBB:
4093 // %FalseValue = ...
4094 // # fallthrough to sinkMBB
4095 BB = copy0MBB;
4096
4097 // Update machine-CFG edges
4098 BB->addSuccessor(sinkMBB);
4099
4100 // sinkMBB:
4101 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
4102 // ...
4103 BB = sinkMBB;
4104
4105 BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(0).getReg())
4106 .addReg(MI.getOperand(2).getReg())
4107 .addMBB(thisMBB)
4108 .addReg(MI.getOperand(3).getReg())
4109 .addMBB(copy0MBB);
4110
4111 MI.eraseFromParent(); // The pseudo instruction is gone now.
4112
4113 return BB;
4114}
4115
4116// FIXME? Maybe this could be a TableGen attribute on some registers and
4117// this table could be generated automatically from RegInfo.
4118unsigned MipsTargetLowering::getRegisterByName(const char* RegName, EVT VT,
4119 SelectionDAG &DAG) const {
4120 // Named registers is expected to be fairly rare. For now, just support $28
4121 // since the linux kernel uses it.
4122 if (Subtarget.isGP64bit()) {
4123 unsigned Reg = StringSwitch<unsigned>(RegName)
4124 .Case("$28", Mips::GP_64)
4125 .Default(0);
4126 if (Reg)
4127 return Reg;
4128 } else {
4129 unsigned Reg = StringSwitch<unsigned>(RegName)
4130 .Case("$28", Mips::GP)
4131 .Default(0);
4132 if (Reg)
4133 return Reg;
4134 }
4135 report_fatal_error("Invalid register name global variable");
4136}