File: | lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp |
Location: | line 196, column 7 |
Description: | Value stored to 'Opcode' is never read |
1 | //===-- MipsMCCodeEmitter.cpp - Convert Mips Code to Machine Code ---------===// |
2 | // |
3 | // The LLVM Compiler Infrastructure |
4 | // |
5 | // This file is distributed under the University of Illinois Open Source |
6 | // License. See LICENSE.TXT for details. |
7 | // |
8 | //===----------------------------------------------------------------------===// |
9 | // |
10 | // This file implements the MipsMCCodeEmitter class. |
11 | // |
12 | //===----------------------------------------------------------------------===// |
13 | // |
14 | |
15 | #include "MipsMCCodeEmitter.h" |
16 | #include "MCTargetDesc/MipsFixupKinds.h" |
17 | #include "MCTargetDesc/MipsMCExpr.h" |
18 | #include "MCTargetDesc/MipsMCTargetDesc.h" |
19 | #include "llvm/ADT/APFloat.h" |
20 | #include "llvm/ADT/SmallVector.h" |
21 | #include "llvm/MC/MCContext.h" |
22 | #include "llvm/MC/MCExpr.h" |
23 | #include "llvm/MC/MCFixup.h" |
24 | #include "llvm/MC/MCInst.h" |
25 | #include "llvm/MC/MCInstrInfo.h" |
26 | #include "llvm/MC/MCSubtargetInfo.h" |
27 | #include "llvm/Support/raw_ostream.h" |
28 | |
29 | #define DEBUG_TYPE"mccodeemitter" "mccodeemitter" |
30 | |
31 | #define GET_INSTRMAP_INFO |
32 | #include "MipsGenInstrInfo.inc" |
33 | #undef GET_INSTRMAP_INFO |
34 | |
35 | namespace llvm { |
36 | MCCodeEmitter *createMipsMCCodeEmitterEB(const MCInstrInfo &MCII, |
37 | const MCRegisterInfo &MRI, |
38 | MCContext &Ctx) { |
39 | return new MipsMCCodeEmitter(MCII, Ctx, false); |
40 | } |
41 | |
42 | MCCodeEmitter *createMipsMCCodeEmitterEL(const MCInstrInfo &MCII, |
43 | const MCRegisterInfo &MRI, |
44 | MCContext &Ctx) { |
45 | return new MipsMCCodeEmitter(MCII, Ctx, true); |
46 | } |
47 | } // End of namespace llvm. |
48 | |
49 | // If the D<shift> instruction has a shift amount that is greater |
50 | // than 31 (checked in calling routine), lower it to a D<shift>32 instruction |
51 | static void LowerLargeShift(MCInst& Inst) { |
52 | |
53 | assert(Inst.getNumOperands() == 3 && "Invalid no. of operands for shift!")((Inst.getNumOperands() == 3 && "Invalid no. of operands for shift!" ) ? static_cast<void> (0) : __assert_fail ("Inst.getNumOperands() == 3 && \"Invalid no. of operands for shift!\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn236768/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 53, __PRETTY_FUNCTION__)); |
54 | assert(Inst.getOperand(2).isImm())((Inst.getOperand(2).isImm()) ? static_cast<void> (0) : __assert_fail ("Inst.getOperand(2).isImm()", "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn236768/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 54, __PRETTY_FUNCTION__)); |
55 | |
56 | int64_t Shift = Inst.getOperand(2).getImm(); |
57 | if (Shift <= 31) |
58 | return; // Do nothing |
59 | Shift -= 32; |
60 | |
61 | // saminus32 |
62 | Inst.getOperand(2).setImm(Shift); |
63 | |
64 | switch (Inst.getOpcode()) { |
65 | default: |
66 | // Calling function is not synchronized |
67 | llvm_unreachable("Unexpected shift instruction")::llvm::llvm_unreachable_internal("Unexpected shift instruction" , "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn236768/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 67); |
68 | case Mips::DSLL: |
69 | Inst.setOpcode(Mips::DSLL32); |
70 | return; |
71 | case Mips::DSRL: |
72 | Inst.setOpcode(Mips::DSRL32); |
73 | return; |
74 | case Mips::DSRA: |
75 | Inst.setOpcode(Mips::DSRA32); |
76 | return; |
77 | case Mips::DROTR: |
78 | Inst.setOpcode(Mips::DROTR32); |
79 | return; |
80 | } |
81 | } |
82 | |
83 | // Pick a DEXT or DINS instruction variant based on the pos and size operands |
84 | static void LowerDextDins(MCInst& InstIn) { |
85 | int Opcode = InstIn.getOpcode(); |
86 | |
87 | if (Opcode == Mips::DEXT) |
88 | assert(InstIn.getNumOperands() == 4 &&((InstIn.getNumOperands() == 4 && "Invalid no. of machine operands for DEXT!" ) ? static_cast<void> (0) : __assert_fail ("InstIn.getNumOperands() == 4 && \"Invalid no. of machine operands for DEXT!\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn236768/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 89, __PRETTY_FUNCTION__)) |
89 | "Invalid no. of machine operands for DEXT!")((InstIn.getNumOperands() == 4 && "Invalid no. of machine operands for DEXT!" ) ? static_cast<void> (0) : __assert_fail ("InstIn.getNumOperands() == 4 && \"Invalid no. of machine operands for DEXT!\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn236768/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 89, __PRETTY_FUNCTION__)); |
90 | else // Only DEXT and DINS are possible |
91 | assert(InstIn.getNumOperands() == 5 &&((InstIn.getNumOperands() == 5 && "Invalid no. of machine operands for DINS!" ) ? static_cast<void> (0) : __assert_fail ("InstIn.getNumOperands() == 5 && \"Invalid no. of machine operands for DINS!\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn236768/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 92, __PRETTY_FUNCTION__)) |
92 | "Invalid no. of machine operands for DINS!")((InstIn.getNumOperands() == 5 && "Invalid no. of machine operands for DINS!" ) ? static_cast<void> (0) : __assert_fail ("InstIn.getNumOperands() == 5 && \"Invalid no. of machine operands for DINS!\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn236768/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 92, __PRETTY_FUNCTION__)); |
93 | |
94 | assert(InstIn.getOperand(2).isImm())((InstIn.getOperand(2).isImm()) ? static_cast<void> (0) : __assert_fail ("InstIn.getOperand(2).isImm()", "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn236768/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 94, __PRETTY_FUNCTION__)); |
95 | int64_t pos = InstIn.getOperand(2).getImm(); |
96 | assert(InstIn.getOperand(3).isImm())((InstIn.getOperand(3).isImm()) ? static_cast<void> (0) : __assert_fail ("InstIn.getOperand(3).isImm()", "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn236768/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 96, __PRETTY_FUNCTION__)); |
97 | int64_t size = InstIn.getOperand(3).getImm(); |
98 | |
99 | if (size <= 32) { |
100 | if (pos < 32) // DEXT/DINS, do nothing |
101 | return; |
102 | // DEXTU/DINSU |
103 | InstIn.getOperand(2).setImm(pos - 32); |
104 | InstIn.setOpcode((Opcode == Mips::DEXT) ? Mips::DEXTU : Mips::DINSU); |
105 | return; |
106 | } |
107 | // DEXTM/DINSM |
108 | assert(pos < 32 && "DEXT/DINS cannot have both size and pos > 32")((pos < 32 && "DEXT/DINS cannot have both size and pos > 32" ) ? static_cast<void> (0) : __assert_fail ("pos < 32 && \"DEXT/DINS cannot have both size and pos > 32\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn236768/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 108, __PRETTY_FUNCTION__)); |
109 | InstIn.getOperand(3).setImm(size - 32); |
110 | InstIn.setOpcode((Opcode == Mips::DEXT) ? Mips::DEXTM : Mips::DINSM); |
111 | return; |
112 | } |
113 | |
114 | bool MipsMCCodeEmitter::isMicroMips(const MCSubtargetInfo &STI) const { |
115 | return STI.getFeatureBits() & Mips::FeatureMicroMips; |
116 | } |
117 | |
118 | bool MipsMCCodeEmitter::isMips32r6(const MCSubtargetInfo &STI) const { |
119 | return STI.getFeatureBits() & Mips::FeatureMips32r6; |
120 | } |
121 | |
122 | void MipsMCCodeEmitter::EmitByte(unsigned char C, raw_ostream &OS) const { |
123 | OS << (char)C; |
124 | } |
125 | |
126 | void MipsMCCodeEmitter::EmitInstruction(uint64_t Val, unsigned Size, |
127 | const MCSubtargetInfo &STI, |
128 | raw_ostream &OS) const { |
129 | // Output the instruction encoding in little endian byte order. |
130 | // Little-endian byte ordering: |
131 | // mips32r2: 4 | 3 | 2 | 1 |
132 | // microMIPS: 2 | 1 | 4 | 3 |
133 | if (IsLittleEndian && Size == 4 && isMicroMips(STI)) { |
134 | EmitInstruction(Val >> 16, 2, STI, OS); |
135 | EmitInstruction(Val, 2, STI, OS); |
136 | } else { |
137 | for (unsigned i = 0; i < Size; ++i) { |
138 | unsigned Shift = IsLittleEndian ? i * 8 : (Size - 1 - i) * 8; |
139 | EmitByte((Val >> Shift) & 0xff, OS); |
140 | } |
141 | } |
142 | } |
143 | |
144 | /// EncodeInstruction - Emit the instruction. |
145 | /// Size the instruction with Desc.getSize(). |
146 | void MipsMCCodeEmitter:: |
147 | EncodeInstruction(const MCInst &MI, raw_ostream &OS, |
148 | SmallVectorImpl<MCFixup> &Fixups, |
149 | const MCSubtargetInfo &STI) const |
150 | { |
151 | |
152 | // Non-pseudo instructions that get changed for direct object |
153 | // only based on operand values. |
154 | // If this list of instructions get much longer we will move |
155 | // the check to a function call. Until then, this is more efficient. |
156 | MCInst TmpInst = MI; |
157 | switch (MI.getOpcode()) { |
158 | // If shift amount is >= 32 it the inst needs to be lowered further |
159 | case Mips::DSLL: |
160 | case Mips::DSRL: |
161 | case Mips::DSRA: |
162 | case Mips::DROTR: |
163 | LowerLargeShift(TmpInst); |
164 | break; |
165 | // Double extract instruction is chosen by pos and size operands |
166 | case Mips::DEXT: |
167 | case Mips::DINS: |
168 | LowerDextDins(TmpInst); |
169 | } |
170 | |
171 | unsigned long N = Fixups.size(); |
172 | uint32_t Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI); |
173 | |
174 | // Check for unimplemented opcodes. |
175 | // Unfortunately in MIPS both NOP and SLL will come in with Binary == 0 |
176 | // so we have to special check for them. |
177 | unsigned Opcode = TmpInst.getOpcode(); |
178 | if ((Opcode != Mips::NOP) && (Opcode != Mips::SLL) && |
179 | (Opcode != Mips::SLL_MM) && !Binary) |
180 | llvm_unreachable("unimplemented opcode in EncodeInstruction()")::llvm::llvm_unreachable_internal("unimplemented opcode in EncodeInstruction()" , "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn236768/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 180); |
181 | |
182 | int NewOpcode = -1; |
183 | if (isMicroMips(STI)) { |
184 | if (isMips32r6(STI)) { |
185 | NewOpcode = Mips::MipsR62MicroMipsR6(Opcode, Mips::Arch_micromipsr6); |
186 | if (NewOpcode == -1) |
187 | NewOpcode = Mips::Std2MicroMipsR6(Opcode, Mips::Arch_micromipsr6); |
188 | } |
189 | else |
190 | NewOpcode = Mips::Std2MicroMips(Opcode, Mips::Arch_micromips); |
191 | |
192 | if (NewOpcode != -1) { |
193 | if (Fixups.size() > N) |
194 | Fixups.pop_back(); |
195 | |
196 | Opcode = NewOpcode; |
Value stored to 'Opcode' is never read | |
197 | TmpInst.setOpcode (NewOpcode); |
198 | Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI); |
199 | } |
200 | } |
201 | |
202 | const MCInstrDesc &Desc = MCII.get(TmpInst.getOpcode()); |
203 | |
204 | // Get byte count of instruction |
205 | unsigned Size = Desc.getSize(); |
206 | if (!Size) |
207 | llvm_unreachable("Desc.getSize() returns 0")::llvm::llvm_unreachable_internal("Desc.getSize() returns 0", "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn236768/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 207); |
208 | |
209 | EmitInstruction(Binary, Size, STI, OS); |
210 | } |
211 | |
212 | /// getBranchTargetOpValue - Return binary encoding of the branch |
213 | /// target operand. If the machine operand requires relocation, |
214 | /// record the relocation and return zero. |
215 | unsigned MipsMCCodeEmitter:: |
216 | getBranchTargetOpValue(const MCInst &MI, unsigned OpNo, |
217 | SmallVectorImpl<MCFixup> &Fixups, |
218 | const MCSubtargetInfo &STI) const { |
219 | |
220 | const MCOperand &MO = MI.getOperand(OpNo); |
221 | |
222 | // If the destination is an immediate, divide by 4. |
223 | if (MO.isImm()) return MO.getImm() >> 2; |
224 | |
225 | assert(MO.isExpr() &&((MO.isExpr() && "getBranchTargetOpValue expects only expressions or immediates" ) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getBranchTargetOpValue expects only expressions or immediates\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn236768/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 226, __PRETTY_FUNCTION__)) |
226 | "getBranchTargetOpValue expects only expressions or immediates")((MO.isExpr() && "getBranchTargetOpValue expects only expressions or immediates" ) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getBranchTargetOpValue expects only expressions or immediates\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn236768/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 226, __PRETTY_FUNCTION__)); |
227 | |
228 | const MCExpr *Expr = MO.getExpr(); |
229 | Fixups.push_back(MCFixup::Create(0, Expr, |
230 | MCFixupKind(Mips::fixup_Mips_PC16))); |
231 | return 0; |
232 | } |
233 | |
234 | /// getBranchTarget7OpValueMM - Return binary encoding of the microMIPS branch |
235 | /// target operand. If the machine operand requires relocation, |
236 | /// record the relocation and return zero. |
237 | unsigned MipsMCCodeEmitter:: |
238 | getBranchTarget7OpValueMM(const MCInst &MI, unsigned OpNo, |
239 | SmallVectorImpl<MCFixup> &Fixups, |
240 | const MCSubtargetInfo &STI) const { |
241 | |
242 | const MCOperand &MO = MI.getOperand(OpNo); |
243 | |
244 | // If the destination is an immediate, divide by 2. |
245 | if (MO.isImm()) return MO.getImm() >> 1; |
246 | |
247 | assert(MO.isExpr() &&((MO.isExpr() && "getBranchTargetOpValueMM expects only expressions or immediates" ) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getBranchTargetOpValueMM expects only expressions or immediates\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn236768/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 248, __PRETTY_FUNCTION__)) |
248 | "getBranchTargetOpValueMM expects only expressions or immediates")((MO.isExpr() && "getBranchTargetOpValueMM expects only expressions or immediates" ) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getBranchTargetOpValueMM expects only expressions or immediates\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn236768/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 248, __PRETTY_FUNCTION__)); |
249 | |
250 | const MCExpr *Expr = MO.getExpr(); |
251 | Fixups.push_back(MCFixup::Create(0, Expr, |
252 | MCFixupKind(Mips::fixup_MICROMIPS_PC7_S1))); |
253 | return 0; |
254 | } |
255 | |
256 | /// getBranchTargetOpValueMMPC10 - Return binary encoding of the microMIPS |
257 | /// 10-bit branch target operand. If the machine operand requires relocation, |
258 | /// record the relocation and return zero. |
259 | unsigned MipsMCCodeEmitter:: |
260 | getBranchTargetOpValueMMPC10(const MCInst &MI, unsigned OpNo, |
261 | SmallVectorImpl<MCFixup> &Fixups, |
262 | const MCSubtargetInfo &STI) const { |
263 | |
264 | const MCOperand &MO = MI.getOperand(OpNo); |
265 | |
266 | // If the destination is an immediate, divide by 2. |
267 | if (MO.isImm()) return MO.getImm() >> 1; |
268 | |
269 | assert(MO.isExpr() &&((MO.isExpr() && "getBranchTargetOpValuePC10 expects only expressions or immediates" ) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getBranchTargetOpValuePC10 expects only expressions or immediates\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn236768/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 270, __PRETTY_FUNCTION__)) |
270 | "getBranchTargetOpValuePC10 expects only expressions or immediates")((MO.isExpr() && "getBranchTargetOpValuePC10 expects only expressions or immediates" ) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getBranchTargetOpValuePC10 expects only expressions or immediates\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn236768/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 270, __PRETTY_FUNCTION__)); |
271 | |
272 | const MCExpr *Expr = MO.getExpr(); |
273 | Fixups.push_back(MCFixup::Create(0, Expr, |
274 | MCFixupKind(Mips::fixup_MICROMIPS_PC10_S1))); |
275 | return 0; |
276 | } |
277 | |
278 | /// getBranchTargetOpValue - Return binary encoding of the microMIPS branch |
279 | /// target operand. If the machine operand requires relocation, |
280 | /// record the relocation and return zero. |
281 | unsigned MipsMCCodeEmitter:: |
282 | getBranchTargetOpValueMM(const MCInst &MI, unsigned OpNo, |
283 | SmallVectorImpl<MCFixup> &Fixups, |
284 | const MCSubtargetInfo &STI) const { |
285 | |
286 | const MCOperand &MO = MI.getOperand(OpNo); |
287 | |
288 | // If the destination is an immediate, divide by 2. |
289 | if (MO.isImm()) return MO.getImm() >> 1; |
290 | |
291 | assert(MO.isExpr() &&((MO.isExpr() && "getBranchTargetOpValueMM expects only expressions or immediates" ) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getBranchTargetOpValueMM expects only expressions or immediates\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn236768/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 292, __PRETTY_FUNCTION__)) |
292 | "getBranchTargetOpValueMM expects only expressions or immediates")((MO.isExpr() && "getBranchTargetOpValueMM expects only expressions or immediates" ) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getBranchTargetOpValueMM expects only expressions or immediates\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn236768/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 292, __PRETTY_FUNCTION__)); |
293 | |
294 | const MCExpr *Expr = MO.getExpr(); |
295 | Fixups.push_back(MCFixup::Create(0, Expr, |
296 | MCFixupKind(Mips:: |
297 | fixup_MICROMIPS_PC16_S1))); |
298 | return 0; |
299 | } |
300 | |
301 | /// getBranchTarget21OpValue - Return binary encoding of the branch |
302 | /// target operand. If the machine operand requires relocation, |
303 | /// record the relocation and return zero. |
304 | unsigned MipsMCCodeEmitter:: |
305 | getBranchTarget21OpValue(const MCInst &MI, unsigned OpNo, |
306 | SmallVectorImpl<MCFixup> &Fixups, |
307 | const MCSubtargetInfo &STI) const { |
308 | |
309 | const MCOperand &MO = MI.getOperand(OpNo); |
310 | |
311 | // If the destination is an immediate, divide by 4. |
312 | if (MO.isImm()) return MO.getImm() >> 2; |
313 | |
314 | assert(MO.isExpr() &&((MO.isExpr() && "getBranchTarget21OpValue expects only expressions or immediates" ) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getBranchTarget21OpValue expects only expressions or immediates\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn236768/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 315, __PRETTY_FUNCTION__)) |
315 | "getBranchTarget21OpValue expects only expressions or immediates")((MO.isExpr() && "getBranchTarget21OpValue expects only expressions or immediates" ) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getBranchTarget21OpValue expects only expressions or immediates\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn236768/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 315, __PRETTY_FUNCTION__)); |
316 | |
317 | const MCExpr *Expr = MO.getExpr(); |
318 | Fixups.push_back(MCFixup::Create(0, Expr, |
319 | MCFixupKind(Mips::fixup_MIPS_PC21_S2))); |
320 | return 0; |
321 | } |
322 | |
323 | /// getBranchTarget26OpValue - Return binary encoding of the branch |
324 | /// target operand. If the machine operand requires relocation, |
325 | /// record the relocation and return zero. |
326 | unsigned MipsMCCodeEmitter:: |
327 | getBranchTarget26OpValue(const MCInst &MI, unsigned OpNo, |
328 | SmallVectorImpl<MCFixup> &Fixups, |
329 | const MCSubtargetInfo &STI) const { |
330 | |
331 | const MCOperand &MO = MI.getOperand(OpNo); |
332 | |
333 | // If the destination is an immediate, divide by 4. |
334 | if (MO.isImm()) return MO.getImm() >> 2; |
335 | |
336 | assert(MO.isExpr() &&((MO.isExpr() && "getBranchTarget26OpValue expects only expressions or immediates" ) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getBranchTarget26OpValue expects only expressions or immediates\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn236768/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 337, __PRETTY_FUNCTION__)) |
337 | "getBranchTarget26OpValue expects only expressions or immediates")((MO.isExpr() && "getBranchTarget26OpValue expects only expressions or immediates" ) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getBranchTarget26OpValue expects only expressions or immediates\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn236768/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 337, __PRETTY_FUNCTION__)); |
338 | |
339 | const MCExpr *Expr = MO.getExpr(); |
340 | Fixups.push_back(MCFixup::Create(0, Expr, |
341 | MCFixupKind(Mips::fixup_MIPS_PC26_S2))); |
342 | return 0; |
343 | } |
344 | |
345 | /// getJumpOffset16OpValue - Return binary encoding of the jump |
346 | /// target operand. If the machine operand requires relocation, |
347 | /// record the relocation and return zero. |
348 | unsigned MipsMCCodeEmitter:: |
349 | getJumpOffset16OpValue(const MCInst &MI, unsigned OpNo, |
350 | SmallVectorImpl<MCFixup> &Fixups, |
351 | const MCSubtargetInfo &STI) const { |
352 | |
353 | const MCOperand &MO = MI.getOperand(OpNo); |
354 | |
355 | if (MO.isImm()) return MO.getImm(); |
356 | |
357 | assert(MO.isExpr() &&((MO.isExpr() && "getJumpOffset16OpValue expects only expressions or an immediate" ) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getJumpOffset16OpValue expects only expressions or an immediate\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn236768/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 358, __PRETTY_FUNCTION__)) |
358 | "getJumpOffset16OpValue expects only expressions or an immediate")((MO.isExpr() && "getJumpOffset16OpValue expects only expressions or an immediate" ) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getJumpOffset16OpValue expects only expressions or an immediate\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn236768/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 358, __PRETTY_FUNCTION__)); |
359 | |
360 | // TODO: Push fixup. |
361 | return 0; |
362 | } |
363 | |
364 | /// getJumpTargetOpValue - Return binary encoding of the jump |
365 | /// target operand. If the machine operand requires relocation, |
366 | /// record the relocation and return zero. |
367 | unsigned MipsMCCodeEmitter:: |
368 | getJumpTargetOpValue(const MCInst &MI, unsigned OpNo, |
369 | SmallVectorImpl<MCFixup> &Fixups, |
370 | const MCSubtargetInfo &STI) const { |
371 | |
372 | const MCOperand &MO = MI.getOperand(OpNo); |
373 | // If the destination is an immediate, divide by 4. |
374 | if (MO.isImm()) return MO.getImm()>>2; |
375 | |
376 | assert(MO.isExpr() &&((MO.isExpr() && "getJumpTargetOpValue expects only expressions or an immediate" ) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getJumpTargetOpValue expects only expressions or an immediate\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn236768/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 377, __PRETTY_FUNCTION__)) |
377 | "getJumpTargetOpValue expects only expressions or an immediate")((MO.isExpr() && "getJumpTargetOpValue expects only expressions or an immediate" ) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getJumpTargetOpValue expects only expressions or an immediate\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn236768/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 377, __PRETTY_FUNCTION__)); |
378 | |
379 | const MCExpr *Expr = MO.getExpr(); |
380 | Fixups.push_back(MCFixup::Create(0, Expr, |
381 | MCFixupKind(Mips::fixup_Mips_26))); |
382 | return 0; |
383 | } |
384 | |
385 | unsigned MipsMCCodeEmitter:: |
386 | getJumpTargetOpValueMM(const MCInst &MI, unsigned OpNo, |
387 | SmallVectorImpl<MCFixup> &Fixups, |
388 | const MCSubtargetInfo &STI) const { |
389 | |
390 | const MCOperand &MO = MI.getOperand(OpNo); |
391 | // If the destination is an immediate, divide by 2. |
392 | if (MO.isImm()) return MO.getImm() >> 1; |
393 | |
394 | assert(MO.isExpr() &&((MO.isExpr() && "getJumpTargetOpValueMM expects only expressions or an immediate" ) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getJumpTargetOpValueMM expects only expressions or an immediate\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn236768/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 395, __PRETTY_FUNCTION__)) |
395 | "getJumpTargetOpValueMM expects only expressions or an immediate")((MO.isExpr() && "getJumpTargetOpValueMM expects only expressions or an immediate" ) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getJumpTargetOpValueMM expects only expressions or an immediate\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn236768/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 395, __PRETTY_FUNCTION__)); |
396 | |
397 | const MCExpr *Expr = MO.getExpr(); |
398 | Fixups.push_back(MCFixup::Create(0, Expr, |
399 | MCFixupKind(Mips::fixup_MICROMIPS_26_S1))); |
400 | return 0; |
401 | } |
402 | |
403 | unsigned MipsMCCodeEmitter:: |
404 | getUImm5Lsl2Encoding(const MCInst &MI, unsigned OpNo, |
405 | SmallVectorImpl<MCFixup> &Fixups, |
406 | const MCSubtargetInfo &STI) const { |
407 | |
408 | const MCOperand &MO = MI.getOperand(OpNo); |
409 | if (MO.isImm()) { |
410 | // The immediate is encoded as 'immediate << 2'. |
411 | unsigned Res = getMachineOpValue(MI, MO, Fixups, STI); |
412 | assert((Res & 3) == 0)(((Res & 3) == 0) ? static_cast<void> (0) : __assert_fail ("(Res & 3) == 0", "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn236768/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 412, __PRETTY_FUNCTION__)); |
413 | return Res >> 2; |
414 | } |
415 | |
416 | assert(MO.isExpr() &&((MO.isExpr() && "getUImm5Lsl2Encoding expects only expressions or an immediate" ) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getUImm5Lsl2Encoding expects only expressions or an immediate\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn236768/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 417, __PRETTY_FUNCTION__)) |
417 | "getUImm5Lsl2Encoding expects only expressions or an immediate")((MO.isExpr() && "getUImm5Lsl2Encoding expects only expressions or an immediate" ) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getUImm5Lsl2Encoding expects only expressions or an immediate\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn236768/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 417, __PRETTY_FUNCTION__)); |
418 | |
419 | return 0; |
420 | } |
421 | |
422 | unsigned MipsMCCodeEmitter:: |
423 | getSImm3Lsa2Value(const MCInst &MI, unsigned OpNo, |
424 | SmallVectorImpl<MCFixup> &Fixups, |
425 | const MCSubtargetInfo &STI) const { |
426 | |
427 | const MCOperand &MO = MI.getOperand(OpNo); |
428 | if (MO.isImm()) { |
429 | int Value = MO.getImm(); |
430 | return Value >> 2; |
431 | } |
432 | |
433 | return 0; |
434 | } |
435 | |
436 | unsigned MipsMCCodeEmitter:: |
437 | getUImm6Lsl2Encoding(const MCInst &MI, unsigned OpNo, |
438 | SmallVectorImpl<MCFixup> &Fixups, |
439 | const MCSubtargetInfo &STI) const { |
440 | |
441 | const MCOperand &MO = MI.getOperand(OpNo); |
442 | if (MO.isImm()) { |
443 | unsigned Value = MO.getImm(); |
444 | return Value >> 2; |
445 | } |
446 | |
447 | return 0; |
448 | } |
449 | |
450 | unsigned MipsMCCodeEmitter:: |
451 | getSImm9AddiuspValue(const MCInst &MI, unsigned OpNo, |
452 | SmallVectorImpl<MCFixup> &Fixups, |
453 | const MCSubtargetInfo &STI) const { |
454 | |
455 | const MCOperand &MO = MI.getOperand(OpNo); |
456 | if (MO.isImm()) { |
457 | unsigned Binary = (MO.getImm() >> 2) & 0x0000ffff; |
458 | return (((Binary & 0x8000) >> 7) | (Binary & 0x00ff)); |
459 | } |
460 | |
461 | return 0; |
462 | } |
463 | |
464 | unsigned MipsMCCodeEmitter:: |
465 | getExprOpValue(const MCExpr *Expr, SmallVectorImpl<MCFixup> &Fixups, |
466 | const MCSubtargetInfo &STI) const { |
467 | int64_t Res; |
468 | |
469 | if (Expr->EvaluateAsAbsolute(Res)) |
470 | return Res; |
471 | |
472 | MCExpr::ExprKind Kind = Expr->getKind(); |
473 | if (Kind == MCExpr::Constant) { |
474 | return cast<MCConstantExpr>(Expr)->getValue(); |
475 | } |
476 | |
477 | if (Kind == MCExpr::Binary) { |
478 | unsigned Res = getExprOpValue(cast<MCBinaryExpr>(Expr)->getLHS(), Fixups, STI); |
479 | Res += getExprOpValue(cast<MCBinaryExpr>(Expr)->getRHS(), Fixups, STI); |
480 | return Res; |
481 | } |
482 | |
483 | if (Kind == MCExpr::Target) { |
484 | const MipsMCExpr *MipsExpr = cast<MipsMCExpr>(Expr); |
485 | |
486 | Mips::Fixups FixupKind = Mips::Fixups(0); |
487 | switch (MipsExpr->getKind()) { |
488 | default: llvm_unreachable("Unsupported fixup kind for target expression!")::llvm::llvm_unreachable_internal("Unsupported fixup kind for target expression!" , "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn236768/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 488); |
489 | case MipsMCExpr::VK_Mips_HIGHEST: |
490 | FixupKind = Mips::fixup_Mips_HIGHEST; |
491 | break; |
492 | case MipsMCExpr::VK_Mips_HIGHER: |
493 | FixupKind = Mips::fixup_Mips_HIGHER; |
494 | break; |
495 | case MipsMCExpr::VK_Mips_HI: |
496 | FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_HI16 |
497 | : Mips::fixup_Mips_HI16; |
498 | break; |
499 | case MipsMCExpr::VK_Mips_LO: |
500 | FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_LO16 |
501 | : Mips::fixup_Mips_LO16; |
502 | break; |
503 | } |
504 | Fixups.push_back(MCFixup::Create(0, MipsExpr, MCFixupKind(FixupKind))); |
505 | return 0; |
506 | } |
507 | |
508 | if (Kind == MCExpr::SymbolRef) { |
509 | Mips::Fixups FixupKind = Mips::Fixups(0); |
510 | |
511 | switch(cast<MCSymbolRefExpr>(Expr)->getKind()) { |
512 | default: llvm_unreachable("Unknown fixup kind!")::llvm::llvm_unreachable_internal("Unknown fixup kind!", "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn236768/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 512); |
513 | break; |
514 | case MCSymbolRefExpr::VK_None: |
515 | FixupKind = Mips::fixup_Mips_32; // FIXME: This is ok for O32/N32 but not N64. |
516 | break; |
517 | case MCSymbolRefExpr::VK_Mips_GPOFF_HI : |
518 | FixupKind = Mips::fixup_Mips_GPOFF_HI; |
519 | break; |
520 | case MCSymbolRefExpr::VK_Mips_GPOFF_LO : |
521 | FixupKind = Mips::fixup_Mips_GPOFF_LO; |
522 | break; |
523 | case MCSymbolRefExpr::VK_Mips_GOT_PAGE : |
524 | FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT_PAGE |
525 | : Mips::fixup_Mips_GOT_PAGE; |
526 | break; |
527 | case MCSymbolRefExpr::VK_Mips_GOT_OFST : |
528 | FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT_OFST |
529 | : Mips::fixup_Mips_GOT_OFST; |
530 | break; |
531 | case MCSymbolRefExpr::VK_Mips_GOT_DISP : |
532 | FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT_DISP |
533 | : Mips::fixup_Mips_GOT_DISP; |
534 | break; |
535 | case MCSymbolRefExpr::VK_Mips_GPREL: |
536 | FixupKind = Mips::fixup_Mips_GPREL16; |
537 | break; |
538 | case MCSymbolRefExpr::VK_Mips_GOT_CALL: |
539 | FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_CALL16 |
540 | : Mips::fixup_Mips_CALL16; |
541 | break; |
542 | case MCSymbolRefExpr::VK_Mips_GOT16: |
543 | FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT16 |
544 | : Mips::fixup_Mips_GOT_Global; |
545 | break; |
546 | case MCSymbolRefExpr::VK_Mips_GOT: |
547 | FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT16 |
548 | : Mips::fixup_Mips_GOT_Local; |
549 | break; |
550 | case MCSymbolRefExpr::VK_Mips_ABS_HI: |
551 | FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_HI16 |
552 | : Mips::fixup_Mips_HI16; |
553 | break; |
554 | case MCSymbolRefExpr::VK_Mips_ABS_LO: |
555 | FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_LO16 |
556 | : Mips::fixup_Mips_LO16; |
557 | break; |
558 | case MCSymbolRefExpr::VK_Mips_TLSGD: |
559 | FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_GD |
560 | : Mips::fixup_Mips_TLSGD; |
561 | break; |
562 | case MCSymbolRefExpr::VK_Mips_TLSLDM: |
563 | FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_LDM |
564 | : Mips::fixup_Mips_TLSLDM; |
565 | break; |
566 | case MCSymbolRefExpr::VK_Mips_DTPREL_HI: |
567 | FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_DTPREL_HI16 |
568 | : Mips::fixup_Mips_DTPREL_HI; |
569 | break; |
570 | case MCSymbolRefExpr::VK_Mips_DTPREL_LO: |
571 | FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_DTPREL_LO16 |
572 | : Mips::fixup_Mips_DTPREL_LO; |
573 | break; |
574 | case MCSymbolRefExpr::VK_Mips_GOTTPREL: |
575 | FixupKind = Mips::fixup_Mips_GOTTPREL; |
576 | break; |
577 | case MCSymbolRefExpr::VK_Mips_TPREL_HI: |
578 | FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_TPREL_HI16 |
579 | : Mips::fixup_Mips_TPREL_HI; |
580 | break; |
581 | case MCSymbolRefExpr::VK_Mips_TPREL_LO: |
582 | FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_TPREL_LO16 |
583 | : Mips::fixup_Mips_TPREL_LO; |
584 | break; |
585 | case MCSymbolRefExpr::VK_Mips_HIGHER: |
586 | FixupKind = Mips::fixup_Mips_HIGHER; |
587 | break; |
588 | case MCSymbolRefExpr::VK_Mips_HIGHEST: |
589 | FixupKind = Mips::fixup_Mips_HIGHEST; |
590 | break; |
591 | case MCSymbolRefExpr::VK_Mips_GOT_HI16: |
592 | FixupKind = Mips::fixup_Mips_GOT_HI16; |
593 | break; |
594 | case MCSymbolRefExpr::VK_Mips_GOT_LO16: |
595 | FixupKind = Mips::fixup_Mips_GOT_LO16; |
596 | break; |
597 | case MCSymbolRefExpr::VK_Mips_CALL_HI16: |
598 | FixupKind = Mips::fixup_Mips_CALL_HI16; |
599 | break; |
600 | case MCSymbolRefExpr::VK_Mips_CALL_LO16: |
601 | FixupKind = Mips::fixup_Mips_CALL_LO16; |
602 | break; |
603 | case MCSymbolRefExpr::VK_Mips_PCREL_HI16: |
604 | FixupKind = Mips::fixup_MIPS_PCHI16; |
605 | break; |
606 | case MCSymbolRefExpr::VK_Mips_PCREL_LO16: |
607 | FixupKind = Mips::fixup_MIPS_PCLO16; |
608 | break; |
609 | } // switch |
610 | |
611 | Fixups.push_back(MCFixup::Create(0, Expr, MCFixupKind(FixupKind))); |
612 | return 0; |
613 | } |
614 | return 0; |
615 | } |
616 | |
617 | /// getMachineOpValue - Return binary encoding of operand. If the machine |
618 | /// operand requires relocation, record the relocation and return zero. |
619 | unsigned MipsMCCodeEmitter:: |
620 | getMachineOpValue(const MCInst &MI, const MCOperand &MO, |
621 | SmallVectorImpl<MCFixup> &Fixups, |
622 | const MCSubtargetInfo &STI) const { |
623 | if (MO.isReg()) { |
624 | unsigned Reg = MO.getReg(); |
625 | unsigned RegNo = Ctx.getRegisterInfo()->getEncodingValue(Reg); |
626 | return RegNo; |
627 | } else if (MO.isImm()) { |
628 | return static_cast<unsigned>(MO.getImm()); |
629 | } else if (MO.isFPImm()) { |
630 | return static_cast<unsigned>(APFloat(MO.getFPImm()) |
631 | .bitcastToAPInt().getHiBits(32).getLimitedValue()); |
632 | } |
633 | // MO must be an Expr. |
634 | assert(MO.isExpr())((MO.isExpr()) ? static_cast<void> (0) : __assert_fail ( "MO.isExpr()", "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn236768/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 634, __PRETTY_FUNCTION__)); |
635 | return getExprOpValue(MO.getExpr(),Fixups, STI); |
636 | } |
637 | |
638 | /// getMSAMemEncoding - Return binary encoding of memory operand for LD/ST |
639 | /// instructions. |
640 | unsigned |
641 | MipsMCCodeEmitter::getMSAMemEncoding(const MCInst &MI, unsigned OpNo, |
642 | SmallVectorImpl<MCFixup> &Fixups, |
643 | const MCSubtargetInfo &STI) const { |
644 | // Base register is encoded in bits 20-16, offset is encoded in bits 15-0. |
645 | assert(MI.getOperand(OpNo).isReg())((MI.getOperand(OpNo).isReg()) ? static_cast<void> (0) : __assert_fail ("MI.getOperand(OpNo).isReg()", "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn236768/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 645, __PRETTY_FUNCTION__)); |
646 | unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),Fixups, STI) << 16; |
647 | unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI); |
648 | |
649 | // The immediate field of an LD/ST instruction is scaled which means it must |
650 | // be divided (when encoding) by the size (in bytes) of the instructions' |
651 | // data format. |
652 | // .b - 1 byte |
653 | // .h - 2 bytes |
654 | // .w - 4 bytes |
655 | // .d - 8 bytes |
656 | switch(MI.getOpcode()) |
657 | { |
658 | default: |
659 | assert (0 && "Unexpected instruction")((0 && "Unexpected instruction") ? static_cast<void > (0) : __assert_fail ("0 && \"Unexpected instruction\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn236768/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 659, __PRETTY_FUNCTION__)); |
660 | break; |
661 | case Mips::LD_B: |
662 | case Mips::ST_B: |
663 | // We don't need to scale the offset in this case |
664 | break; |
665 | case Mips::LD_H: |
666 | case Mips::ST_H: |
667 | OffBits >>= 1; |
668 | break; |
669 | case Mips::LD_W: |
670 | case Mips::ST_W: |
671 | OffBits >>= 2; |
672 | break; |
673 | case Mips::LD_D: |
674 | case Mips::ST_D: |
675 | OffBits >>= 3; |
676 | break; |
677 | } |
678 | |
679 | return (OffBits & 0xFFFF) | RegBits; |
680 | } |
681 | |
682 | /// getMemEncoding - Return binary encoding of memory related operand. |
683 | /// If the offset operand requires relocation, record the relocation. |
684 | unsigned |
685 | MipsMCCodeEmitter::getMemEncoding(const MCInst &MI, unsigned OpNo, |
686 | SmallVectorImpl<MCFixup> &Fixups, |
687 | const MCSubtargetInfo &STI) const { |
688 | // Base register is encoded in bits 20-16, offset is encoded in bits 15-0. |
689 | assert(MI.getOperand(OpNo).isReg())((MI.getOperand(OpNo).isReg()) ? static_cast<void> (0) : __assert_fail ("MI.getOperand(OpNo).isReg()", "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn236768/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 689, __PRETTY_FUNCTION__)); |
690 | unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),Fixups, STI) << 16; |
691 | unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI); |
692 | |
693 | return (OffBits & 0xFFFF) | RegBits; |
694 | } |
695 | |
696 | unsigned MipsMCCodeEmitter:: |
697 | getMemEncodingMMImm4(const MCInst &MI, unsigned OpNo, |
698 | SmallVectorImpl<MCFixup> &Fixups, |
699 | const MCSubtargetInfo &STI) const { |
700 | // Base register is encoded in bits 6-4, offset is encoded in bits 3-0. |
701 | assert(MI.getOperand(OpNo).isReg())((MI.getOperand(OpNo).isReg()) ? static_cast<void> (0) : __assert_fail ("MI.getOperand(OpNo).isReg()", "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn236768/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 701, __PRETTY_FUNCTION__)); |
702 | unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), |
703 | Fixups, STI) << 4; |
704 | unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), |
705 | Fixups, STI); |
706 | |
707 | return (OffBits & 0xF) | RegBits; |
708 | } |
709 | |
710 | unsigned MipsMCCodeEmitter:: |
711 | getMemEncodingMMImm4Lsl1(const MCInst &MI, unsigned OpNo, |
712 | SmallVectorImpl<MCFixup> &Fixups, |
713 | const MCSubtargetInfo &STI) const { |
714 | // Base register is encoded in bits 6-4, offset is encoded in bits 3-0. |
715 | assert(MI.getOperand(OpNo).isReg())((MI.getOperand(OpNo).isReg()) ? static_cast<void> (0) : __assert_fail ("MI.getOperand(OpNo).isReg()", "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn236768/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 715, __PRETTY_FUNCTION__)); |
716 | unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), |
717 | Fixups, STI) << 4; |
718 | unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), |
719 | Fixups, STI) >> 1; |
720 | |
721 | return (OffBits & 0xF) | RegBits; |
722 | } |
723 | |
724 | unsigned MipsMCCodeEmitter:: |
725 | getMemEncodingMMImm4Lsl2(const MCInst &MI, unsigned OpNo, |
726 | SmallVectorImpl<MCFixup> &Fixups, |
727 | const MCSubtargetInfo &STI) const { |
728 | // Base register is encoded in bits 6-4, offset is encoded in bits 3-0. |
729 | assert(MI.getOperand(OpNo).isReg())((MI.getOperand(OpNo).isReg()) ? static_cast<void> (0) : __assert_fail ("MI.getOperand(OpNo).isReg()", "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn236768/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 729, __PRETTY_FUNCTION__)); |
730 | unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), |
731 | Fixups, STI) << 4; |
732 | unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), |
733 | Fixups, STI) >> 2; |
734 | |
735 | return (OffBits & 0xF) | RegBits; |
736 | } |
737 | |
738 | unsigned MipsMCCodeEmitter:: |
739 | getMemEncodingMMSPImm5Lsl2(const MCInst &MI, unsigned OpNo, |
740 | SmallVectorImpl<MCFixup> &Fixups, |
741 | const MCSubtargetInfo &STI) const { |
742 | // Register is encoded in bits 9-5, offset is encoded in bits 4-0. |
743 | assert(MI.getOperand(OpNo).isReg() &&((MI.getOperand(OpNo).isReg() && MI.getOperand(OpNo). getReg() == Mips::SP && "Unexpected base register!") ? static_cast<void> (0) : __assert_fail ("MI.getOperand(OpNo).isReg() && MI.getOperand(OpNo).getReg() == Mips::SP && \"Unexpected base register!\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn236768/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 745, __PRETTY_FUNCTION__)) |
744 | MI.getOperand(OpNo).getReg() == Mips::SP &&((MI.getOperand(OpNo).isReg() && MI.getOperand(OpNo). getReg() == Mips::SP && "Unexpected base register!") ? static_cast<void> (0) : __assert_fail ("MI.getOperand(OpNo).isReg() && MI.getOperand(OpNo).getReg() == Mips::SP && \"Unexpected base register!\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn236768/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 745, __PRETTY_FUNCTION__)) |
745 | "Unexpected base register!")((MI.getOperand(OpNo).isReg() && MI.getOperand(OpNo). getReg() == Mips::SP && "Unexpected base register!") ? static_cast<void> (0) : __assert_fail ("MI.getOperand(OpNo).isReg() && MI.getOperand(OpNo).getReg() == Mips::SP && \"Unexpected base register!\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn236768/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 745, __PRETTY_FUNCTION__)); |
746 | unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), |
747 | Fixups, STI) >> 2; |
748 | |
749 | return OffBits & 0x1F; |
750 | } |
751 | |
752 | unsigned MipsMCCodeEmitter:: |
753 | getMemEncodingMMGPImm7Lsl2(const MCInst &MI, unsigned OpNo, |
754 | SmallVectorImpl<MCFixup> &Fixups, |
755 | const MCSubtargetInfo &STI) const { |
756 | // Register is encoded in bits 9-7, offset is encoded in bits 6-0. |
757 | assert(MI.getOperand(OpNo).isReg() &&((MI.getOperand(OpNo).isReg() && MI.getOperand(OpNo). getReg() == Mips::GP && "Unexpected base register!") ? static_cast<void> (0) : __assert_fail ("MI.getOperand(OpNo).isReg() && MI.getOperand(OpNo).getReg() == Mips::GP && \"Unexpected base register!\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn236768/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 759, __PRETTY_FUNCTION__)) |
758 | MI.getOperand(OpNo).getReg() == Mips::GP &&((MI.getOperand(OpNo).isReg() && MI.getOperand(OpNo). getReg() == Mips::GP && "Unexpected base register!") ? static_cast<void> (0) : __assert_fail ("MI.getOperand(OpNo).isReg() && MI.getOperand(OpNo).getReg() == Mips::GP && \"Unexpected base register!\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn236768/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 759, __PRETTY_FUNCTION__)) |
759 | "Unexpected base register!")((MI.getOperand(OpNo).isReg() && MI.getOperand(OpNo). getReg() == Mips::GP && "Unexpected base register!") ? static_cast<void> (0) : __assert_fail ("MI.getOperand(OpNo).isReg() && MI.getOperand(OpNo).getReg() == Mips::GP && \"Unexpected base register!\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn236768/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 759, __PRETTY_FUNCTION__)); |
760 | |
761 | unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), |
762 | Fixups, STI) >> 2; |
763 | |
764 | return OffBits & 0x7F; |
765 | } |
766 | |
767 | unsigned MipsMCCodeEmitter:: |
768 | getMemEncodingMMImm12(const MCInst &MI, unsigned OpNo, |
769 | SmallVectorImpl<MCFixup> &Fixups, |
770 | const MCSubtargetInfo &STI) const { |
771 | // opNum can be invalid if instruction had reglist as operand. |
772 | // MemOperand is always last operand of instruction (base + offset). |
773 | switch (MI.getOpcode()) { |
774 | default: |
775 | break; |
776 | case Mips::SWM32_MM: |
777 | case Mips::LWM32_MM: |
778 | OpNo = MI.getNumOperands() - 2; |
779 | break; |
780 | } |
781 | |
782 | // Base register is encoded in bits 20-16, offset is encoded in bits 11-0. |
783 | assert(MI.getOperand(OpNo).isReg())((MI.getOperand(OpNo).isReg()) ? static_cast<void> (0) : __assert_fail ("MI.getOperand(OpNo).isReg()", "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn236768/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 783, __PRETTY_FUNCTION__)); |
784 | unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI) << 16; |
785 | unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI); |
786 | |
787 | return (OffBits & 0x0FFF) | RegBits; |
788 | } |
789 | |
790 | unsigned MipsMCCodeEmitter:: |
791 | getMemEncodingMMImm4sp(const MCInst &MI, unsigned OpNo, |
792 | SmallVectorImpl<MCFixup> &Fixups, |
793 | const MCSubtargetInfo &STI) const { |
794 | // opNum can be invalid if instruction had reglist as operand |
795 | // MemOperand is always last operand of instruction (base + offset) |
796 | switch (MI.getOpcode()) { |
797 | default: |
798 | break; |
799 | case Mips::SWM16_MM: |
800 | case Mips::LWM16_MM: |
801 | OpNo = MI.getNumOperands() - 2; |
802 | break; |
803 | } |
804 | |
805 | // Offset is encoded in bits 4-0. |
806 | assert(MI.getOperand(OpNo).isReg())((MI.getOperand(OpNo).isReg()) ? static_cast<void> (0) : __assert_fail ("MI.getOperand(OpNo).isReg()", "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn236768/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 806, __PRETTY_FUNCTION__)); |
807 | // Base register is always SP - thus it is not encoded. |
808 | assert(MI.getOperand(OpNo+1).isImm())((MI.getOperand(OpNo+1).isImm()) ? static_cast<void> (0 ) : __assert_fail ("MI.getOperand(OpNo+1).isImm()", "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn236768/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 808, __PRETTY_FUNCTION__)); |
809 | unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI); |
810 | |
811 | return ((OffBits >> 2) & 0x0F); |
812 | } |
813 | |
814 | unsigned |
815 | MipsMCCodeEmitter::getSizeExtEncoding(const MCInst &MI, unsigned OpNo, |
816 | SmallVectorImpl<MCFixup> &Fixups, |
817 | const MCSubtargetInfo &STI) const { |
818 | assert(MI.getOperand(OpNo).isImm())((MI.getOperand(OpNo).isImm()) ? static_cast<void> (0) : __assert_fail ("MI.getOperand(OpNo).isImm()", "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn236768/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 818, __PRETTY_FUNCTION__)); |
819 | unsigned SizeEncoding = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI); |
820 | return SizeEncoding - 1; |
821 | } |
822 | |
823 | // FIXME: should be called getMSBEncoding |
824 | // |
825 | unsigned |
826 | MipsMCCodeEmitter::getSizeInsEncoding(const MCInst &MI, unsigned OpNo, |
827 | SmallVectorImpl<MCFixup> &Fixups, |
828 | const MCSubtargetInfo &STI) const { |
829 | assert(MI.getOperand(OpNo-1).isImm())((MI.getOperand(OpNo-1).isImm()) ? static_cast<void> (0 ) : __assert_fail ("MI.getOperand(OpNo-1).isImm()", "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn236768/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 829, __PRETTY_FUNCTION__)); |
830 | assert(MI.getOperand(OpNo).isImm())((MI.getOperand(OpNo).isImm()) ? static_cast<void> (0) : __assert_fail ("MI.getOperand(OpNo).isImm()", "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn236768/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 830, __PRETTY_FUNCTION__)); |
831 | unsigned Position = getMachineOpValue(MI, MI.getOperand(OpNo-1), Fixups, STI); |
832 | unsigned Size = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI); |
833 | |
834 | return Position + Size - 1; |
835 | } |
836 | |
837 | unsigned |
838 | MipsMCCodeEmitter::getLSAImmEncoding(const MCInst &MI, unsigned OpNo, |
839 | SmallVectorImpl<MCFixup> &Fixups, |
840 | const MCSubtargetInfo &STI) const { |
841 | assert(MI.getOperand(OpNo).isImm())((MI.getOperand(OpNo).isImm()) ? static_cast<void> (0) : __assert_fail ("MI.getOperand(OpNo).isImm()", "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn236768/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 841, __PRETTY_FUNCTION__)); |
842 | // The immediate is encoded as 'immediate - 1'. |
843 | return getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI) - 1; |
844 | } |
845 | |
846 | unsigned |
847 | MipsMCCodeEmitter::getSimm19Lsl2Encoding(const MCInst &MI, unsigned OpNo, |
848 | SmallVectorImpl<MCFixup> &Fixups, |
849 | const MCSubtargetInfo &STI) const { |
850 | const MCOperand &MO = MI.getOperand(OpNo); |
851 | if (MO.isImm()) { |
852 | // The immediate is encoded as 'immediate << 2'. |
853 | unsigned Res = getMachineOpValue(MI, MO, Fixups, STI); |
854 | assert((Res & 3) == 0)(((Res & 3) == 0) ? static_cast<void> (0) : __assert_fail ("(Res & 3) == 0", "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn236768/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 854, __PRETTY_FUNCTION__)); |
855 | return Res >> 2; |
856 | } |
857 | |
858 | assert(MO.isExpr() &&((MO.isExpr() && "getSimm19Lsl2Encoding expects only expressions or an immediate" ) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getSimm19Lsl2Encoding expects only expressions or an immediate\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn236768/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 859, __PRETTY_FUNCTION__)) |
859 | "getSimm19Lsl2Encoding expects only expressions or an immediate")((MO.isExpr() && "getSimm19Lsl2Encoding expects only expressions or an immediate" ) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getSimm19Lsl2Encoding expects only expressions or an immediate\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn236768/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 859, __PRETTY_FUNCTION__)); |
860 | |
861 | const MCExpr *Expr = MO.getExpr(); |
862 | Fixups.push_back(MCFixup::Create(0, Expr, |
863 | MCFixupKind(Mips::fixup_MIPS_PC19_S2))); |
864 | return 0; |
865 | } |
866 | |
867 | unsigned |
868 | MipsMCCodeEmitter::getSimm18Lsl3Encoding(const MCInst &MI, unsigned OpNo, |
869 | SmallVectorImpl<MCFixup> &Fixups, |
870 | const MCSubtargetInfo &STI) const { |
871 | const MCOperand &MO = MI.getOperand(OpNo); |
872 | if (MO.isImm()) { |
873 | // The immediate is encoded as 'immediate << 3'. |
874 | unsigned Res = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI); |
875 | assert((Res & 7) == 0)(((Res & 7) == 0) ? static_cast<void> (0) : __assert_fail ("(Res & 7) == 0", "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn236768/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 875, __PRETTY_FUNCTION__)); |
876 | return Res >> 3; |
877 | } |
878 | |
879 | assert(MO.isExpr() &&((MO.isExpr() && "getSimm18Lsl2Encoding expects only expressions or an immediate" ) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getSimm18Lsl2Encoding expects only expressions or an immediate\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn236768/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 880, __PRETTY_FUNCTION__)) |
880 | "getSimm18Lsl2Encoding expects only expressions or an immediate")((MO.isExpr() && "getSimm18Lsl2Encoding expects only expressions or an immediate" ) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getSimm18Lsl2Encoding expects only expressions or an immediate\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn236768/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 880, __PRETTY_FUNCTION__)); |
881 | |
882 | const MCExpr *Expr = MO.getExpr(); |
883 | Fixups.push_back(MCFixup::Create(0, Expr, |
884 | MCFixupKind(Mips::fixup_MIPS_PC18_S3))); |
885 | return 0; |
886 | } |
887 | |
888 | unsigned |
889 | MipsMCCodeEmitter::getUImm3Mod8Encoding(const MCInst &MI, unsigned OpNo, |
890 | SmallVectorImpl<MCFixup> &Fixups, |
891 | const MCSubtargetInfo &STI) const { |
892 | assert(MI.getOperand(OpNo).isImm())((MI.getOperand(OpNo).isImm()) ? static_cast<void> (0) : __assert_fail ("MI.getOperand(OpNo).isImm()", "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn236768/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 892, __PRETTY_FUNCTION__)); |
893 | const MCOperand &MO = MI.getOperand(OpNo); |
894 | return MO.getImm() % 8; |
895 | } |
896 | |
897 | unsigned |
898 | MipsMCCodeEmitter::getUImm4AndValue(const MCInst &MI, unsigned OpNo, |
899 | SmallVectorImpl<MCFixup> &Fixups, |
900 | const MCSubtargetInfo &STI) const { |
901 | assert(MI.getOperand(OpNo).isImm())((MI.getOperand(OpNo).isImm()) ? static_cast<void> (0) : __assert_fail ("MI.getOperand(OpNo).isImm()", "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn236768/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 901, __PRETTY_FUNCTION__)); |
902 | const MCOperand &MO = MI.getOperand(OpNo); |
903 | unsigned Value = MO.getImm(); |
904 | switch (Value) { |
905 | case 128: return 0x0; |
906 | case 1: return 0x1; |
907 | case 2: return 0x2; |
908 | case 3: return 0x3; |
909 | case 4: return 0x4; |
910 | case 7: return 0x5; |
911 | case 8: return 0x6; |
912 | case 15: return 0x7; |
913 | case 16: return 0x8; |
914 | case 31: return 0x9; |
915 | case 32: return 0xa; |
916 | case 63: return 0xb; |
917 | case 64: return 0xc; |
918 | case 255: return 0xd; |
919 | case 32768: return 0xe; |
920 | case 65535: return 0xf; |
921 | } |
922 | llvm_unreachable("Unexpected value")::llvm::llvm_unreachable_internal("Unexpected value", "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn236768/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 922); |
923 | } |
924 | |
925 | unsigned |
926 | MipsMCCodeEmitter::getRegisterListOpValue(const MCInst &MI, unsigned OpNo, |
927 | SmallVectorImpl<MCFixup> &Fixups, |
928 | const MCSubtargetInfo &STI) const { |
929 | unsigned res = 0; |
930 | |
931 | // Register list operand is always first operand of instruction and it is |
932 | // placed before memory operand (register + imm). |
933 | |
934 | for (unsigned I = OpNo, E = MI.getNumOperands() - 2; I < E; ++I) { |
935 | unsigned Reg = MI.getOperand(I).getReg(); |
936 | unsigned RegNo = Ctx.getRegisterInfo()->getEncodingValue(Reg); |
937 | if (RegNo != 31) |
938 | res++; |
939 | else |
940 | res |= 0x10; |
941 | } |
942 | return res; |
943 | } |
944 | |
945 | unsigned |
946 | MipsMCCodeEmitter::getRegisterListOpValue16(const MCInst &MI, unsigned OpNo, |
947 | SmallVectorImpl<MCFixup> &Fixups, |
948 | const MCSubtargetInfo &STI) const { |
949 | return (MI.getNumOperands() - 4); |
950 | } |
951 | |
952 | unsigned |
953 | MipsMCCodeEmitter::getRegisterPairOpValue(const MCInst &MI, unsigned OpNo, |
954 | SmallVectorImpl<MCFixup> &Fixups, |
955 | const MCSubtargetInfo &STI) const { |
956 | return getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI); |
957 | } |
958 | |
959 | unsigned |
960 | MipsMCCodeEmitter::getMovePRegPairOpValue(const MCInst &MI, unsigned OpNo, |
961 | SmallVectorImpl<MCFixup> &Fixups, |
962 | const MCSubtargetInfo &STI) const { |
963 | unsigned res = 0; |
964 | |
965 | if (MI.getOperand(0).getReg() == Mips::A1 && |
966 | MI.getOperand(1).getReg() == Mips::A2) |
967 | res = 0; |
968 | else if (MI.getOperand(0).getReg() == Mips::A1 && |
969 | MI.getOperand(1).getReg() == Mips::A3) |
970 | res = 1; |
971 | else if (MI.getOperand(0).getReg() == Mips::A2 && |
972 | MI.getOperand(1).getReg() == Mips::A3) |
973 | res = 2; |
974 | else if (MI.getOperand(0).getReg() == Mips::A0 && |
975 | MI.getOperand(1).getReg() == Mips::S5) |
976 | res = 3; |
977 | else if (MI.getOperand(0).getReg() == Mips::A0 && |
978 | MI.getOperand(1).getReg() == Mips::S6) |
979 | res = 4; |
980 | else if (MI.getOperand(0).getReg() == Mips::A0 && |
981 | MI.getOperand(1).getReg() == Mips::A1) |
982 | res = 5; |
983 | else if (MI.getOperand(0).getReg() == Mips::A0 && |
984 | MI.getOperand(1).getReg() == Mips::A2) |
985 | res = 6; |
986 | else if (MI.getOperand(0).getReg() == Mips::A0 && |
987 | MI.getOperand(1).getReg() == Mips::A3) |
988 | res = 7; |
989 | |
990 | return res; |
991 | } |
992 | |
993 | unsigned |
994 | MipsMCCodeEmitter::getSimm23Lsl2Encoding(const MCInst &MI, unsigned OpNo, |
995 | SmallVectorImpl<MCFixup> &Fixups, |
996 | const MCSubtargetInfo &STI) const { |
997 | const MCOperand &MO = MI.getOperand(OpNo); |
998 | assert(MO.isImm() && "getSimm23Lsl2Encoding expects only an immediate")((MO.isImm() && "getSimm23Lsl2Encoding expects only an immediate" ) ? static_cast<void> (0) : __assert_fail ("MO.isImm() && \"getSimm23Lsl2Encoding expects only an immediate\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn236768/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 998, __PRETTY_FUNCTION__)); |
999 | // The immediate is encoded as 'immediate >> 2'. |
1000 | unsigned Res = static_cast<unsigned>(MO.getImm()); |
1001 | assert((Res & 3) == 0)(((Res & 3) == 0) ? static_cast<void> (0) : __assert_fail ("(Res & 3) == 0", "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn236768/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 1001, __PRETTY_FUNCTION__)); |
1002 | return Res >> 2; |
1003 | } |
1004 | |
1005 | #include "MipsGenMCCodeEmitter.inc" |