File: | lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp |
Location: | line 197, column 7 |
Description: | Value stored to 'Opcode' is never read |
1 | //===-- MipsMCCodeEmitter.cpp - Convert Mips Code to Machine Code ---------===// |
2 | // |
3 | // The LLVM Compiler Infrastructure |
4 | // |
5 | // This file is distributed under the University of Illinois Open Source |
6 | // License. See LICENSE.TXT for details. |
7 | // |
8 | //===----------------------------------------------------------------------===// |
9 | // |
10 | // This file implements the MipsMCCodeEmitter class. |
11 | // |
12 | //===----------------------------------------------------------------------===// |
13 | // |
14 | |
15 | #include "MipsMCCodeEmitter.h" |
16 | #include "MCTargetDesc/MipsFixupKinds.h" |
17 | #include "MCTargetDesc/MipsMCExpr.h" |
18 | #include "MCTargetDesc/MipsMCTargetDesc.h" |
19 | #include "llvm/ADT/APFloat.h" |
20 | #include "llvm/ADT/SmallVector.h" |
21 | #include "llvm/MC/MCContext.h" |
22 | #include "llvm/MC/MCExpr.h" |
23 | #include "llvm/MC/MCFixup.h" |
24 | #include "llvm/MC/MCInst.h" |
25 | #include "llvm/MC/MCInstrInfo.h" |
26 | #include "llvm/MC/MCRegisterInfo.h" |
27 | #include "llvm/MC/MCSubtargetInfo.h" |
28 | #include "llvm/Support/raw_ostream.h" |
29 | |
30 | #define DEBUG_TYPE"mccodeemitter" "mccodeemitter" |
31 | |
32 | #define GET_INSTRMAP_INFO |
33 | #include "MipsGenInstrInfo.inc" |
34 | #undef GET_INSTRMAP_INFO |
35 | |
36 | namespace llvm { |
37 | MCCodeEmitter *createMipsMCCodeEmitterEB(const MCInstrInfo &MCII, |
38 | const MCRegisterInfo &MRI, |
39 | MCContext &Ctx) { |
40 | return new MipsMCCodeEmitter(MCII, Ctx, false); |
41 | } |
42 | |
43 | MCCodeEmitter *createMipsMCCodeEmitterEL(const MCInstrInfo &MCII, |
44 | const MCRegisterInfo &MRI, |
45 | MCContext &Ctx) { |
46 | return new MipsMCCodeEmitter(MCII, Ctx, true); |
47 | } |
48 | } // End of namespace llvm. |
49 | |
50 | // If the D<shift> instruction has a shift amount that is greater |
51 | // than 31 (checked in calling routine), lower it to a D<shift>32 instruction |
52 | static void LowerLargeShift(MCInst& Inst) { |
53 | |
54 | assert(Inst.getNumOperands() == 3 && "Invalid no. of operands for shift!")((Inst.getNumOperands() == 3 && "Invalid no. of operands for shift!" ) ? static_cast<void> (0) : __assert_fail ("Inst.getNumOperands() == 3 && \"Invalid no. of operands for shift!\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn249994/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 54, __PRETTY_FUNCTION__)); |
55 | assert(Inst.getOperand(2).isImm())((Inst.getOperand(2).isImm()) ? static_cast<void> (0) : __assert_fail ("Inst.getOperand(2).isImm()", "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn249994/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 55, __PRETTY_FUNCTION__)); |
56 | |
57 | int64_t Shift = Inst.getOperand(2).getImm(); |
58 | if (Shift <= 31) |
59 | return; // Do nothing |
60 | Shift -= 32; |
61 | |
62 | // saminus32 |
63 | Inst.getOperand(2).setImm(Shift); |
64 | |
65 | switch (Inst.getOpcode()) { |
66 | default: |
67 | // Calling function is not synchronized |
68 | llvm_unreachable("Unexpected shift instruction")::llvm::llvm_unreachable_internal("Unexpected shift instruction" , "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn249994/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 68); |
69 | case Mips::DSLL: |
70 | Inst.setOpcode(Mips::DSLL32); |
71 | return; |
72 | case Mips::DSRL: |
73 | Inst.setOpcode(Mips::DSRL32); |
74 | return; |
75 | case Mips::DSRA: |
76 | Inst.setOpcode(Mips::DSRA32); |
77 | return; |
78 | case Mips::DROTR: |
79 | Inst.setOpcode(Mips::DROTR32); |
80 | return; |
81 | } |
82 | } |
83 | |
84 | // Pick a DEXT or DINS instruction variant based on the pos and size operands |
85 | static void LowerDextDins(MCInst& InstIn) { |
86 | int Opcode = InstIn.getOpcode(); |
87 | |
88 | if (Opcode == Mips::DEXT) |
89 | assert(InstIn.getNumOperands() == 4 &&((InstIn.getNumOperands() == 4 && "Invalid no. of machine operands for DEXT!" ) ? static_cast<void> (0) : __assert_fail ("InstIn.getNumOperands() == 4 && \"Invalid no. of machine operands for DEXT!\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn249994/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 90, __PRETTY_FUNCTION__)) |
90 | "Invalid no. of machine operands for DEXT!")((InstIn.getNumOperands() == 4 && "Invalid no. of machine operands for DEXT!" ) ? static_cast<void> (0) : __assert_fail ("InstIn.getNumOperands() == 4 && \"Invalid no. of machine operands for DEXT!\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn249994/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 90, __PRETTY_FUNCTION__)); |
91 | else // Only DEXT and DINS are possible |
92 | assert(InstIn.getNumOperands() == 5 &&((InstIn.getNumOperands() == 5 && "Invalid no. of machine operands for DINS!" ) ? static_cast<void> (0) : __assert_fail ("InstIn.getNumOperands() == 5 && \"Invalid no. of machine operands for DINS!\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn249994/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 93, __PRETTY_FUNCTION__)) |
93 | "Invalid no. of machine operands for DINS!")((InstIn.getNumOperands() == 5 && "Invalid no. of machine operands for DINS!" ) ? static_cast<void> (0) : __assert_fail ("InstIn.getNumOperands() == 5 && \"Invalid no. of machine operands for DINS!\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn249994/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 93, __PRETTY_FUNCTION__)); |
94 | |
95 | assert(InstIn.getOperand(2).isImm())((InstIn.getOperand(2).isImm()) ? static_cast<void> (0) : __assert_fail ("InstIn.getOperand(2).isImm()", "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn249994/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 95, __PRETTY_FUNCTION__)); |
96 | int64_t pos = InstIn.getOperand(2).getImm(); |
97 | assert(InstIn.getOperand(3).isImm())((InstIn.getOperand(3).isImm()) ? static_cast<void> (0) : __assert_fail ("InstIn.getOperand(3).isImm()", "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn249994/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 97, __PRETTY_FUNCTION__)); |
98 | int64_t size = InstIn.getOperand(3).getImm(); |
99 | |
100 | if (size <= 32) { |
101 | if (pos < 32) // DEXT/DINS, do nothing |
102 | return; |
103 | // DEXTU/DINSU |
104 | InstIn.getOperand(2).setImm(pos - 32); |
105 | InstIn.setOpcode((Opcode == Mips::DEXT) ? Mips::DEXTU : Mips::DINSU); |
106 | return; |
107 | } |
108 | // DEXTM/DINSM |
109 | assert(pos < 32 && "DEXT/DINS cannot have both size and pos > 32")((pos < 32 && "DEXT/DINS cannot have both size and pos > 32" ) ? static_cast<void> (0) : __assert_fail ("pos < 32 && \"DEXT/DINS cannot have both size and pos > 32\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn249994/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 109, __PRETTY_FUNCTION__)); |
110 | InstIn.getOperand(3).setImm(size - 32); |
111 | InstIn.setOpcode((Opcode == Mips::DEXT) ? Mips::DEXTM : Mips::DINSM); |
112 | return; |
113 | } |
114 | |
115 | bool MipsMCCodeEmitter::isMicroMips(const MCSubtargetInfo &STI) const { |
116 | return STI.getFeatureBits()[Mips::FeatureMicroMips]; |
117 | } |
118 | |
119 | bool MipsMCCodeEmitter::isMips32r6(const MCSubtargetInfo &STI) const { |
120 | return STI.getFeatureBits()[Mips::FeatureMips32r6]; |
121 | } |
122 | |
123 | void MipsMCCodeEmitter::EmitByte(unsigned char C, raw_ostream &OS) const { |
124 | OS << (char)C; |
125 | } |
126 | |
127 | void MipsMCCodeEmitter::EmitInstruction(uint64_t Val, unsigned Size, |
128 | const MCSubtargetInfo &STI, |
129 | raw_ostream &OS) const { |
130 | // Output the instruction encoding in little endian byte order. |
131 | // Little-endian byte ordering: |
132 | // mips32r2: 4 | 3 | 2 | 1 |
133 | // microMIPS: 2 | 1 | 4 | 3 |
134 | if (IsLittleEndian && Size == 4 && isMicroMips(STI)) { |
135 | EmitInstruction(Val >> 16, 2, STI, OS); |
136 | EmitInstruction(Val, 2, STI, OS); |
137 | } else { |
138 | for (unsigned i = 0; i < Size; ++i) { |
139 | unsigned Shift = IsLittleEndian ? i * 8 : (Size - 1 - i) * 8; |
140 | EmitByte((Val >> Shift) & 0xff, OS); |
141 | } |
142 | } |
143 | } |
144 | |
145 | /// encodeInstruction - Emit the instruction. |
146 | /// Size the instruction with Desc.getSize(). |
147 | void MipsMCCodeEmitter:: |
148 | encodeInstruction(const MCInst &MI, raw_ostream &OS, |
149 | SmallVectorImpl<MCFixup> &Fixups, |
150 | const MCSubtargetInfo &STI) const |
151 | { |
152 | |
153 | // Non-pseudo instructions that get changed for direct object |
154 | // only based on operand values. |
155 | // If this list of instructions get much longer we will move |
156 | // the check to a function call. Until then, this is more efficient. |
157 | MCInst TmpInst = MI; |
158 | switch (MI.getOpcode()) { |
159 | // If shift amount is >= 32 it the inst needs to be lowered further |
160 | case Mips::DSLL: |
161 | case Mips::DSRL: |
162 | case Mips::DSRA: |
163 | case Mips::DROTR: |
164 | LowerLargeShift(TmpInst); |
165 | break; |
166 | // Double extract instruction is chosen by pos and size operands |
167 | case Mips::DEXT: |
168 | case Mips::DINS: |
169 | LowerDextDins(TmpInst); |
170 | } |
171 | |
172 | unsigned long N = Fixups.size(); |
173 | uint32_t Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI); |
174 | |
175 | // Check for unimplemented opcodes. |
176 | // Unfortunately in MIPS both NOP and SLL will come in with Binary == 0 |
177 | // so we have to special check for them. |
178 | unsigned Opcode = TmpInst.getOpcode(); |
179 | if ((Opcode != Mips::NOP) && (Opcode != Mips::SLL) && |
180 | (Opcode != Mips::SLL_MM) && !Binary) |
181 | llvm_unreachable("unimplemented opcode in encodeInstruction()")::llvm::llvm_unreachable_internal("unimplemented opcode in encodeInstruction()" , "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn249994/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 181); |
182 | |
183 | int NewOpcode = -1; |
184 | if (isMicroMips(STI)) { |
185 | if (isMips32r6(STI)) { |
186 | NewOpcode = Mips::MipsR62MicroMipsR6(Opcode, Mips::Arch_micromipsr6); |
187 | if (NewOpcode == -1) |
188 | NewOpcode = Mips::Std2MicroMipsR6(Opcode, Mips::Arch_micromipsr6); |
189 | } |
190 | else |
191 | NewOpcode = Mips::Std2MicroMips(Opcode, Mips::Arch_micromips); |
192 | |
193 | if (NewOpcode != -1) { |
194 | if (Fixups.size() > N) |
195 | Fixups.pop_back(); |
196 | |
197 | Opcode = NewOpcode; |
Value stored to 'Opcode' is never read | |
198 | TmpInst.setOpcode (NewOpcode); |
199 | Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI); |
200 | } |
201 | } |
202 | |
203 | const MCInstrDesc &Desc = MCII.get(TmpInst.getOpcode()); |
204 | |
205 | // Get byte count of instruction |
206 | unsigned Size = Desc.getSize(); |
207 | if (!Size) |
208 | llvm_unreachable("Desc.getSize() returns 0")::llvm::llvm_unreachable_internal("Desc.getSize() returns 0", "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn249994/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 208); |
209 | |
210 | EmitInstruction(Binary, Size, STI, OS); |
211 | } |
212 | |
213 | /// getBranchTargetOpValue - Return binary encoding of the branch |
214 | /// target operand. If the machine operand requires relocation, |
215 | /// record the relocation and return zero. |
216 | unsigned MipsMCCodeEmitter:: |
217 | getBranchTargetOpValue(const MCInst &MI, unsigned OpNo, |
218 | SmallVectorImpl<MCFixup> &Fixups, |
219 | const MCSubtargetInfo &STI) const { |
220 | |
221 | const MCOperand &MO = MI.getOperand(OpNo); |
222 | |
223 | // If the destination is an immediate, divide by 4. |
224 | if (MO.isImm()) return MO.getImm() >> 2; |
225 | |
226 | assert(MO.isExpr() &&((MO.isExpr() && "getBranchTargetOpValue expects only expressions or immediates" ) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getBranchTargetOpValue expects only expressions or immediates\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn249994/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 227, __PRETTY_FUNCTION__)) |
227 | "getBranchTargetOpValue expects only expressions or immediates")((MO.isExpr() && "getBranchTargetOpValue expects only expressions or immediates" ) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getBranchTargetOpValue expects only expressions or immediates\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn249994/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 227, __PRETTY_FUNCTION__)); |
228 | |
229 | const MCExpr *FixupExpression = MCBinaryExpr::createAdd( |
230 | MO.getExpr(), MCConstantExpr::create(-4, Ctx), Ctx); |
231 | Fixups.push_back(MCFixup::create(0, FixupExpression, |
232 | MCFixupKind(Mips::fixup_Mips_PC16))); |
233 | return 0; |
234 | } |
235 | |
236 | /// getBranchTarget7OpValueMM - Return binary encoding of the microMIPS branch |
237 | /// target operand. If the machine operand requires relocation, |
238 | /// record the relocation and return zero. |
239 | unsigned MipsMCCodeEmitter:: |
240 | getBranchTarget7OpValueMM(const MCInst &MI, unsigned OpNo, |
241 | SmallVectorImpl<MCFixup> &Fixups, |
242 | const MCSubtargetInfo &STI) const { |
243 | |
244 | const MCOperand &MO = MI.getOperand(OpNo); |
245 | |
246 | // If the destination is an immediate, divide by 2. |
247 | if (MO.isImm()) return MO.getImm() >> 1; |
248 | |
249 | assert(MO.isExpr() &&((MO.isExpr() && "getBranchTargetOpValueMM expects only expressions or immediates" ) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getBranchTargetOpValueMM expects only expressions or immediates\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn249994/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 250, __PRETTY_FUNCTION__)) |
250 | "getBranchTargetOpValueMM expects only expressions or immediates")((MO.isExpr() && "getBranchTargetOpValueMM expects only expressions or immediates" ) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getBranchTargetOpValueMM expects only expressions or immediates\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn249994/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 250, __PRETTY_FUNCTION__)); |
251 | |
252 | const MCExpr *Expr = MO.getExpr(); |
253 | Fixups.push_back(MCFixup::create(0, Expr, |
254 | MCFixupKind(Mips::fixup_MICROMIPS_PC7_S1))); |
255 | return 0; |
256 | } |
257 | |
258 | /// getBranchTargetOpValueMMPC10 - Return binary encoding of the microMIPS |
259 | /// 10-bit branch target operand. If the machine operand requires relocation, |
260 | /// record the relocation and return zero. |
261 | unsigned MipsMCCodeEmitter:: |
262 | getBranchTargetOpValueMMPC10(const MCInst &MI, unsigned OpNo, |
263 | SmallVectorImpl<MCFixup> &Fixups, |
264 | const MCSubtargetInfo &STI) const { |
265 | |
266 | const MCOperand &MO = MI.getOperand(OpNo); |
267 | |
268 | // If the destination is an immediate, divide by 2. |
269 | if (MO.isImm()) return MO.getImm() >> 1; |
270 | |
271 | assert(MO.isExpr() &&((MO.isExpr() && "getBranchTargetOpValuePC10 expects only expressions or immediates" ) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getBranchTargetOpValuePC10 expects only expressions or immediates\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn249994/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 272, __PRETTY_FUNCTION__)) |
272 | "getBranchTargetOpValuePC10 expects only expressions or immediates")((MO.isExpr() && "getBranchTargetOpValuePC10 expects only expressions or immediates" ) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getBranchTargetOpValuePC10 expects only expressions or immediates\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn249994/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 272, __PRETTY_FUNCTION__)); |
273 | |
274 | const MCExpr *Expr = MO.getExpr(); |
275 | Fixups.push_back(MCFixup::create(0, Expr, |
276 | MCFixupKind(Mips::fixup_MICROMIPS_PC10_S1))); |
277 | return 0; |
278 | } |
279 | |
280 | /// getBranchTargetOpValue - Return binary encoding of the microMIPS branch |
281 | /// target operand. If the machine operand requires relocation, |
282 | /// record the relocation and return zero. |
283 | unsigned MipsMCCodeEmitter:: |
284 | getBranchTargetOpValueMM(const MCInst &MI, unsigned OpNo, |
285 | SmallVectorImpl<MCFixup> &Fixups, |
286 | const MCSubtargetInfo &STI) const { |
287 | |
288 | const MCOperand &MO = MI.getOperand(OpNo); |
289 | |
290 | // If the destination is an immediate, divide by 2. |
291 | if (MO.isImm()) return MO.getImm() >> 1; |
292 | |
293 | assert(MO.isExpr() &&((MO.isExpr() && "getBranchTargetOpValueMM expects only expressions or immediates" ) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getBranchTargetOpValueMM expects only expressions or immediates\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn249994/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 294, __PRETTY_FUNCTION__)) |
294 | "getBranchTargetOpValueMM expects only expressions or immediates")((MO.isExpr() && "getBranchTargetOpValueMM expects only expressions or immediates" ) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getBranchTargetOpValueMM expects only expressions or immediates\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn249994/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 294, __PRETTY_FUNCTION__)); |
295 | |
296 | const MCExpr *Expr = MO.getExpr(); |
297 | Fixups.push_back(MCFixup::create(0, Expr, |
298 | MCFixupKind(Mips:: |
299 | fixup_MICROMIPS_PC16_S1))); |
300 | return 0; |
301 | } |
302 | |
303 | /// getBranchTarget21OpValue - Return binary encoding of the branch |
304 | /// target operand. If the machine operand requires relocation, |
305 | /// record the relocation and return zero. |
306 | unsigned MipsMCCodeEmitter:: |
307 | getBranchTarget21OpValue(const MCInst &MI, unsigned OpNo, |
308 | SmallVectorImpl<MCFixup> &Fixups, |
309 | const MCSubtargetInfo &STI) const { |
310 | |
311 | const MCOperand &MO = MI.getOperand(OpNo); |
312 | |
313 | // If the destination is an immediate, divide by 4. |
314 | if (MO.isImm()) return MO.getImm() >> 2; |
315 | |
316 | assert(MO.isExpr() &&((MO.isExpr() && "getBranchTarget21OpValue expects only expressions or immediates" ) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getBranchTarget21OpValue expects only expressions or immediates\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn249994/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 317, __PRETTY_FUNCTION__)) |
317 | "getBranchTarget21OpValue expects only expressions or immediates")((MO.isExpr() && "getBranchTarget21OpValue expects only expressions or immediates" ) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getBranchTarget21OpValue expects only expressions or immediates\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn249994/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 317, __PRETTY_FUNCTION__)); |
318 | |
319 | const MCExpr *FixupExpression = MCBinaryExpr::createAdd( |
320 | MO.getExpr(), MCConstantExpr::create(-4, Ctx), Ctx); |
321 | Fixups.push_back(MCFixup::create(0, FixupExpression, |
322 | MCFixupKind(Mips::fixup_MIPS_PC21_S2))); |
323 | return 0; |
324 | } |
325 | |
326 | /// getBranchTarget26OpValue - Return binary encoding of the branch |
327 | /// target operand. If the machine operand requires relocation, |
328 | /// record the relocation and return zero. |
329 | unsigned MipsMCCodeEmitter:: |
330 | getBranchTarget26OpValue(const MCInst &MI, unsigned OpNo, |
331 | SmallVectorImpl<MCFixup> &Fixups, |
332 | const MCSubtargetInfo &STI) const { |
333 | |
334 | const MCOperand &MO = MI.getOperand(OpNo); |
335 | |
336 | // If the destination is an immediate, divide by 4. |
337 | if (MO.isImm()) return MO.getImm() >> 2; |
338 | |
339 | assert(MO.isExpr() &&((MO.isExpr() && "getBranchTarget26OpValue expects only expressions or immediates" ) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getBranchTarget26OpValue expects only expressions or immediates\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn249994/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 340, __PRETTY_FUNCTION__)) |
340 | "getBranchTarget26OpValue expects only expressions or immediates")((MO.isExpr() && "getBranchTarget26OpValue expects only expressions or immediates" ) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getBranchTarget26OpValue expects only expressions or immediates\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn249994/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 340, __PRETTY_FUNCTION__)); |
341 | |
342 | const MCExpr *FixupExpression = MCBinaryExpr::createAdd( |
343 | MO.getExpr(), MCConstantExpr::create(-4, Ctx), Ctx); |
344 | Fixups.push_back(MCFixup::create(0, FixupExpression, |
345 | MCFixupKind(Mips::fixup_MIPS_PC26_S2))); |
346 | return 0; |
347 | } |
348 | |
349 | /// getJumpOffset16OpValue - Return binary encoding of the jump |
350 | /// target operand. If the machine operand requires relocation, |
351 | /// record the relocation and return zero. |
352 | unsigned MipsMCCodeEmitter:: |
353 | getJumpOffset16OpValue(const MCInst &MI, unsigned OpNo, |
354 | SmallVectorImpl<MCFixup> &Fixups, |
355 | const MCSubtargetInfo &STI) const { |
356 | |
357 | const MCOperand &MO = MI.getOperand(OpNo); |
358 | |
359 | if (MO.isImm()) return MO.getImm(); |
360 | |
361 | assert(MO.isExpr() &&((MO.isExpr() && "getJumpOffset16OpValue expects only expressions or an immediate" ) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getJumpOffset16OpValue expects only expressions or an immediate\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn249994/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 362, __PRETTY_FUNCTION__)) |
362 | "getJumpOffset16OpValue expects only expressions or an immediate")((MO.isExpr() && "getJumpOffset16OpValue expects only expressions or an immediate" ) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getJumpOffset16OpValue expects only expressions or an immediate\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn249994/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 362, __PRETTY_FUNCTION__)); |
363 | |
364 | // TODO: Push fixup. |
365 | return 0; |
366 | } |
367 | |
368 | /// getJumpTargetOpValue - Return binary encoding of the jump |
369 | /// target operand. If the machine operand requires relocation, |
370 | /// record the relocation and return zero. |
371 | unsigned MipsMCCodeEmitter:: |
372 | getJumpTargetOpValue(const MCInst &MI, unsigned OpNo, |
373 | SmallVectorImpl<MCFixup> &Fixups, |
374 | const MCSubtargetInfo &STI) const { |
375 | |
376 | const MCOperand &MO = MI.getOperand(OpNo); |
377 | // If the destination is an immediate, divide by 4. |
378 | if (MO.isImm()) return MO.getImm()>>2; |
379 | |
380 | assert(MO.isExpr() &&((MO.isExpr() && "getJumpTargetOpValue expects only expressions or an immediate" ) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getJumpTargetOpValue expects only expressions or an immediate\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn249994/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 381, __PRETTY_FUNCTION__)) |
381 | "getJumpTargetOpValue expects only expressions or an immediate")((MO.isExpr() && "getJumpTargetOpValue expects only expressions or an immediate" ) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getJumpTargetOpValue expects only expressions or an immediate\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn249994/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 381, __PRETTY_FUNCTION__)); |
382 | |
383 | const MCExpr *Expr = MO.getExpr(); |
384 | Fixups.push_back(MCFixup::create(0, Expr, |
385 | MCFixupKind(Mips::fixup_Mips_26))); |
386 | return 0; |
387 | } |
388 | |
389 | unsigned MipsMCCodeEmitter:: |
390 | getJumpTargetOpValueMM(const MCInst &MI, unsigned OpNo, |
391 | SmallVectorImpl<MCFixup> &Fixups, |
392 | const MCSubtargetInfo &STI) const { |
393 | |
394 | const MCOperand &MO = MI.getOperand(OpNo); |
395 | // If the destination is an immediate, divide by 2. |
396 | if (MO.isImm()) return MO.getImm() >> 1; |
397 | |
398 | assert(MO.isExpr() &&((MO.isExpr() && "getJumpTargetOpValueMM expects only expressions or an immediate" ) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getJumpTargetOpValueMM expects only expressions or an immediate\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn249994/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 399, __PRETTY_FUNCTION__)) |
399 | "getJumpTargetOpValueMM expects only expressions or an immediate")((MO.isExpr() && "getJumpTargetOpValueMM expects only expressions or an immediate" ) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getJumpTargetOpValueMM expects only expressions or an immediate\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn249994/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 399, __PRETTY_FUNCTION__)); |
400 | |
401 | const MCExpr *Expr = MO.getExpr(); |
402 | Fixups.push_back(MCFixup::create(0, Expr, |
403 | MCFixupKind(Mips::fixup_MICROMIPS_26_S1))); |
404 | return 0; |
405 | } |
406 | |
407 | unsigned MipsMCCodeEmitter:: |
408 | getUImm5Lsl2Encoding(const MCInst &MI, unsigned OpNo, |
409 | SmallVectorImpl<MCFixup> &Fixups, |
410 | const MCSubtargetInfo &STI) const { |
411 | |
412 | const MCOperand &MO = MI.getOperand(OpNo); |
413 | if (MO.isImm()) { |
414 | // The immediate is encoded as 'immediate << 2'. |
415 | unsigned Res = getMachineOpValue(MI, MO, Fixups, STI); |
416 | assert((Res & 3) == 0)(((Res & 3) == 0) ? static_cast<void> (0) : __assert_fail ("(Res & 3) == 0", "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn249994/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 416, __PRETTY_FUNCTION__)); |
417 | return Res >> 2; |
418 | } |
419 | |
420 | assert(MO.isExpr() &&((MO.isExpr() && "getUImm5Lsl2Encoding expects only expressions or an immediate" ) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getUImm5Lsl2Encoding expects only expressions or an immediate\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn249994/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 421, __PRETTY_FUNCTION__)) |
421 | "getUImm5Lsl2Encoding expects only expressions or an immediate")((MO.isExpr() && "getUImm5Lsl2Encoding expects only expressions or an immediate" ) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getUImm5Lsl2Encoding expects only expressions or an immediate\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn249994/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 421, __PRETTY_FUNCTION__)); |
422 | |
423 | return 0; |
424 | } |
425 | |
426 | unsigned MipsMCCodeEmitter:: |
427 | getSImm3Lsa2Value(const MCInst &MI, unsigned OpNo, |
428 | SmallVectorImpl<MCFixup> &Fixups, |
429 | const MCSubtargetInfo &STI) const { |
430 | |
431 | const MCOperand &MO = MI.getOperand(OpNo); |
432 | if (MO.isImm()) { |
433 | int Value = MO.getImm(); |
434 | return Value >> 2; |
435 | } |
436 | |
437 | return 0; |
438 | } |
439 | |
440 | unsigned MipsMCCodeEmitter:: |
441 | getUImm6Lsl2Encoding(const MCInst &MI, unsigned OpNo, |
442 | SmallVectorImpl<MCFixup> &Fixups, |
443 | const MCSubtargetInfo &STI) const { |
444 | |
445 | const MCOperand &MO = MI.getOperand(OpNo); |
446 | if (MO.isImm()) { |
447 | unsigned Value = MO.getImm(); |
448 | return Value >> 2; |
449 | } |
450 | |
451 | return 0; |
452 | } |
453 | |
454 | unsigned MipsMCCodeEmitter:: |
455 | getSImm9AddiuspValue(const MCInst &MI, unsigned OpNo, |
456 | SmallVectorImpl<MCFixup> &Fixups, |
457 | const MCSubtargetInfo &STI) const { |
458 | |
459 | const MCOperand &MO = MI.getOperand(OpNo); |
460 | if (MO.isImm()) { |
461 | unsigned Binary = (MO.getImm() >> 2) & 0x0000ffff; |
462 | return (((Binary & 0x8000) >> 7) | (Binary & 0x00ff)); |
463 | } |
464 | |
465 | return 0; |
466 | } |
467 | |
468 | unsigned MipsMCCodeEmitter:: |
469 | getExprOpValue(const MCExpr *Expr, SmallVectorImpl<MCFixup> &Fixups, |
470 | const MCSubtargetInfo &STI) const { |
471 | int64_t Res; |
472 | |
473 | if (Expr->evaluateAsAbsolute(Res)) |
474 | return Res; |
475 | |
476 | MCExpr::ExprKind Kind = Expr->getKind(); |
477 | if (Kind == MCExpr::Constant) { |
478 | return cast<MCConstantExpr>(Expr)->getValue(); |
479 | } |
480 | |
481 | if (Kind == MCExpr::Binary) { |
482 | unsigned Res = getExprOpValue(cast<MCBinaryExpr>(Expr)->getLHS(), Fixups, STI); |
483 | Res += getExprOpValue(cast<MCBinaryExpr>(Expr)->getRHS(), Fixups, STI); |
484 | return Res; |
485 | } |
486 | |
487 | if (Kind == MCExpr::Target) { |
488 | const MipsMCExpr *MipsExpr = cast<MipsMCExpr>(Expr); |
489 | |
490 | Mips::Fixups FixupKind = Mips::Fixups(0); |
491 | switch (MipsExpr->getKind()) { |
492 | default: llvm_unreachable("Unsupported fixup kind for target expression!")::llvm::llvm_unreachable_internal("Unsupported fixup kind for target expression!" , "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn249994/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 492); |
493 | case MipsMCExpr::VK_Mips_HIGHEST: |
494 | FixupKind = Mips::fixup_Mips_HIGHEST; |
495 | break; |
496 | case MipsMCExpr::VK_Mips_HIGHER: |
497 | FixupKind = Mips::fixup_Mips_HIGHER; |
498 | break; |
499 | case MipsMCExpr::VK_Mips_HI: |
500 | FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_HI16 |
501 | : Mips::fixup_Mips_HI16; |
502 | break; |
503 | case MipsMCExpr::VK_Mips_LO: |
504 | FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_LO16 |
505 | : Mips::fixup_Mips_LO16; |
506 | break; |
507 | } |
508 | Fixups.push_back(MCFixup::create(0, MipsExpr, MCFixupKind(FixupKind))); |
509 | return 0; |
510 | } |
511 | |
512 | if (Kind == MCExpr::SymbolRef) { |
513 | Mips::Fixups FixupKind = Mips::Fixups(0); |
514 | |
515 | switch(cast<MCSymbolRefExpr>(Expr)->getKind()) { |
516 | default: llvm_unreachable("Unknown fixup kind!")::llvm::llvm_unreachable_internal("Unknown fixup kind!", "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn249994/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 516); |
517 | break; |
518 | case MCSymbolRefExpr::VK_None: |
519 | FixupKind = Mips::fixup_Mips_32; // FIXME: This is ok for O32/N32 but not N64. |
520 | break; |
521 | case MCSymbolRefExpr::VK_Mips_GPOFF_HI : |
522 | FixupKind = Mips::fixup_Mips_GPOFF_HI; |
523 | break; |
524 | case MCSymbolRefExpr::VK_Mips_GPOFF_LO : |
525 | FixupKind = Mips::fixup_Mips_GPOFF_LO; |
526 | break; |
527 | case MCSymbolRefExpr::VK_Mips_GOT_PAGE : |
528 | FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT_PAGE |
529 | : Mips::fixup_Mips_GOT_PAGE; |
530 | break; |
531 | case MCSymbolRefExpr::VK_Mips_GOT_OFST : |
532 | FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT_OFST |
533 | : Mips::fixup_Mips_GOT_OFST; |
534 | break; |
535 | case MCSymbolRefExpr::VK_Mips_GOT_DISP : |
536 | FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT_DISP |
537 | : Mips::fixup_Mips_GOT_DISP; |
538 | break; |
539 | case MCSymbolRefExpr::VK_Mips_GPREL: |
540 | FixupKind = Mips::fixup_Mips_GPREL16; |
541 | break; |
542 | case MCSymbolRefExpr::VK_Mips_GOT_CALL: |
543 | FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_CALL16 |
544 | : Mips::fixup_Mips_CALL16; |
545 | break; |
546 | case MCSymbolRefExpr::VK_Mips_GOT16: |
547 | FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT16 |
548 | : Mips::fixup_Mips_GOT_Global; |
549 | break; |
550 | case MCSymbolRefExpr::VK_Mips_GOT: |
551 | FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT16 |
552 | : Mips::fixup_Mips_GOT_Local; |
553 | break; |
554 | case MCSymbolRefExpr::VK_Mips_ABS_HI: |
555 | FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_HI16 |
556 | : Mips::fixup_Mips_HI16; |
557 | break; |
558 | case MCSymbolRefExpr::VK_Mips_ABS_LO: |
559 | FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_LO16 |
560 | : Mips::fixup_Mips_LO16; |
561 | break; |
562 | case MCSymbolRefExpr::VK_Mips_TLSGD: |
563 | FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_GD |
564 | : Mips::fixup_Mips_TLSGD; |
565 | break; |
566 | case MCSymbolRefExpr::VK_Mips_TLSLDM: |
567 | FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_LDM |
568 | : Mips::fixup_Mips_TLSLDM; |
569 | break; |
570 | case MCSymbolRefExpr::VK_Mips_DTPREL_HI: |
571 | FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_DTPREL_HI16 |
572 | : Mips::fixup_Mips_DTPREL_HI; |
573 | break; |
574 | case MCSymbolRefExpr::VK_Mips_DTPREL_LO: |
575 | FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_DTPREL_LO16 |
576 | : Mips::fixup_Mips_DTPREL_LO; |
577 | break; |
578 | case MCSymbolRefExpr::VK_Mips_GOTTPREL: |
579 | FixupKind = Mips::fixup_Mips_GOTTPREL; |
580 | break; |
581 | case MCSymbolRefExpr::VK_Mips_TPREL_HI: |
582 | FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_TPREL_HI16 |
583 | : Mips::fixup_Mips_TPREL_HI; |
584 | break; |
585 | case MCSymbolRefExpr::VK_Mips_TPREL_LO: |
586 | FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_TPREL_LO16 |
587 | : Mips::fixup_Mips_TPREL_LO; |
588 | break; |
589 | case MCSymbolRefExpr::VK_Mips_HIGHER: |
590 | FixupKind = Mips::fixup_Mips_HIGHER; |
591 | break; |
592 | case MCSymbolRefExpr::VK_Mips_HIGHEST: |
593 | FixupKind = Mips::fixup_Mips_HIGHEST; |
594 | break; |
595 | case MCSymbolRefExpr::VK_Mips_GOT_HI16: |
596 | FixupKind = Mips::fixup_Mips_GOT_HI16; |
597 | break; |
598 | case MCSymbolRefExpr::VK_Mips_GOT_LO16: |
599 | FixupKind = Mips::fixup_Mips_GOT_LO16; |
600 | break; |
601 | case MCSymbolRefExpr::VK_Mips_CALL_HI16: |
602 | FixupKind = Mips::fixup_Mips_CALL_HI16; |
603 | break; |
604 | case MCSymbolRefExpr::VK_Mips_CALL_LO16: |
605 | FixupKind = Mips::fixup_Mips_CALL_LO16; |
606 | break; |
607 | case MCSymbolRefExpr::VK_Mips_PCREL_HI16: |
608 | FixupKind = Mips::fixup_MIPS_PCHI16; |
609 | break; |
610 | case MCSymbolRefExpr::VK_Mips_PCREL_LO16: |
611 | FixupKind = Mips::fixup_MIPS_PCLO16; |
612 | break; |
613 | } // switch |
614 | |
615 | Fixups.push_back(MCFixup::create(0, Expr, MCFixupKind(FixupKind))); |
616 | return 0; |
617 | } |
618 | return 0; |
619 | } |
620 | |
621 | /// getMachineOpValue - Return binary encoding of operand. If the machine |
622 | /// operand requires relocation, record the relocation and return zero. |
623 | unsigned MipsMCCodeEmitter:: |
624 | getMachineOpValue(const MCInst &MI, const MCOperand &MO, |
625 | SmallVectorImpl<MCFixup> &Fixups, |
626 | const MCSubtargetInfo &STI) const { |
627 | if (MO.isReg()) { |
628 | unsigned Reg = MO.getReg(); |
629 | unsigned RegNo = Ctx.getRegisterInfo()->getEncodingValue(Reg); |
630 | return RegNo; |
631 | } else if (MO.isImm()) { |
632 | return static_cast<unsigned>(MO.getImm()); |
633 | } else if (MO.isFPImm()) { |
634 | return static_cast<unsigned>(APFloat(MO.getFPImm()) |
635 | .bitcastToAPInt().getHiBits(32).getLimitedValue()); |
636 | } |
637 | // MO must be an Expr. |
638 | assert(MO.isExpr())((MO.isExpr()) ? static_cast<void> (0) : __assert_fail ( "MO.isExpr()", "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn249994/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 638, __PRETTY_FUNCTION__)); |
639 | return getExprOpValue(MO.getExpr(),Fixups, STI); |
640 | } |
641 | |
642 | /// getMSAMemEncoding - Return binary encoding of memory operand for LD/ST |
643 | /// instructions. |
644 | unsigned |
645 | MipsMCCodeEmitter::getMSAMemEncoding(const MCInst &MI, unsigned OpNo, |
646 | SmallVectorImpl<MCFixup> &Fixups, |
647 | const MCSubtargetInfo &STI) const { |
648 | // Base register is encoded in bits 20-16, offset is encoded in bits 15-0. |
649 | assert(MI.getOperand(OpNo).isReg())((MI.getOperand(OpNo).isReg()) ? static_cast<void> (0) : __assert_fail ("MI.getOperand(OpNo).isReg()", "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn249994/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 649, __PRETTY_FUNCTION__)); |
650 | unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),Fixups, STI) << 16; |
651 | unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI); |
652 | |
653 | // The immediate field of an LD/ST instruction is scaled which means it must |
654 | // be divided (when encoding) by the size (in bytes) of the instructions' |
655 | // data format. |
656 | // .b - 1 byte |
657 | // .h - 2 bytes |
658 | // .w - 4 bytes |
659 | // .d - 8 bytes |
660 | switch(MI.getOpcode()) |
661 | { |
662 | default: |
663 | assert (0 && "Unexpected instruction")((0 && "Unexpected instruction") ? static_cast<void > (0) : __assert_fail ("0 && \"Unexpected instruction\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn249994/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 663, __PRETTY_FUNCTION__)); |
664 | break; |
665 | case Mips::LD_B: |
666 | case Mips::ST_B: |
667 | // We don't need to scale the offset in this case |
668 | break; |
669 | case Mips::LD_H: |
670 | case Mips::ST_H: |
671 | OffBits >>= 1; |
672 | break; |
673 | case Mips::LD_W: |
674 | case Mips::ST_W: |
675 | OffBits >>= 2; |
676 | break; |
677 | case Mips::LD_D: |
678 | case Mips::ST_D: |
679 | OffBits >>= 3; |
680 | break; |
681 | } |
682 | |
683 | return (OffBits & 0xFFFF) | RegBits; |
684 | } |
685 | |
686 | /// getMemEncoding - Return binary encoding of memory related operand. |
687 | /// If the offset operand requires relocation, record the relocation. |
688 | unsigned |
689 | MipsMCCodeEmitter::getMemEncoding(const MCInst &MI, unsigned OpNo, |
690 | SmallVectorImpl<MCFixup> &Fixups, |
691 | const MCSubtargetInfo &STI) const { |
692 | // Base register is encoded in bits 20-16, offset is encoded in bits 15-0. |
693 | assert(MI.getOperand(OpNo).isReg())((MI.getOperand(OpNo).isReg()) ? static_cast<void> (0) : __assert_fail ("MI.getOperand(OpNo).isReg()", "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn249994/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 693, __PRETTY_FUNCTION__)); |
694 | unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),Fixups, STI) << 16; |
695 | unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI); |
696 | |
697 | return (OffBits & 0xFFFF) | RegBits; |
698 | } |
699 | |
700 | unsigned MipsMCCodeEmitter:: |
701 | getMemEncodingMMImm4(const MCInst &MI, unsigned OpNo, |
702 | SmallVectorImpl<MCFixup> &Fixups, |
703 | const MCSubtargetInfo &STI) const { |
704 | // Base register is encoded in bits 6-4, offset is encoded in bits 3-0. |
705 | assert(MI.getOperand(OpNo).isReg())((MI.getOperand(OpNo).isReg()) ? static_cast<void> (0) : __assert_fail ("MI.getOperand(OpNo).isReg()", "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn249994/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 705, __PRETTY_FUNCTION__)); |
706 | unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), |
707 | Fixups, STI) << 4; |
708 | unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), |
709 | Fixups, STI); |
710 | |
711 | return (OffBits & 0xF) | RegBits; |
712 | } |
713 | |
714 | unsigned MipsMCCodeEmitter:: |
715 | getMemEncodingMMImm4Lsl1(const MCInst &MI, unsigned OpNo, |
716 | SmallVectorImpl<MCFixup> &Fixups, |
717 | const MCSubtargetInfo &STI) const { |
718 | // Base register is encoded in bits 6-4, offset is encoded in bits 3-0. |
719 | assert(MI.getOperand(OpNo).isReg())((MI.getOperand(OpNo).isReg()) ? static_cast<void> (0) : __assert_fail ("MI.getOperand(OpNo).isReg()", "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn249994/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 719, __PRETTY_FUNCTION__)); |
720 | unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), |
721 | Fixups, STI) << 4; |
722 | unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), |
723 | Fixups, STI) >> 1; |
724 | |
725 | return (OffBits & 0xF) | RegBits; |
726 | } |
727 | |
728 | unsigned MipsMCCodeEmitter:: |
729 | getMemEncodingMMImm4Lsl2(const MCInst &MI, unsigned OpNo, |
730 | SmallVectorImpl<MCFixup> &Fixups, |
731 | const MCSubtargetInfo &STI) const { |
732 | // Base register is encoded in bits 6-4, offset is encoded in bits 3-0. |
733 | assert(MI.getOperand(OpNo).isReg())((MI.getOperand(OpNo).isReg()) ? static_cast<void> (0) : __assert_fail ("MI.getOperand(OpNo).isReg()", "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn249994/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 733, __PRETTY_FUNCTION__)); |
734 | unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), |
735 | Fixups, STI) << 4; |
736 | unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), |
737 | Fixups, STI) >> 2; |
738 | |
739 | return (OffBits & 0xF) | RegBits; |
740 | } |
741 | |
742 | unsigned MipsMCCodeEmitter:: |
743 | getMemEncodingMMSPImm5Lsl2(const MCInst &MI, unsigned OpNo, |
744 | SmallVectorImpl<MCFixup> &Fixups, |
745 | const MCSubtargetInfo &STI) const { |
746 | // Register is encoded in bits 9-5, offset is encoded in bits 4-0. |
747 | assert(MI.getOperand(OpNo).isReg() &&((MI.getOperand(OpNo).isReg() && (MI.getOperand(OpNo) .getReg() == Mips::SP || MI.getOperand(OpNo).getReg() == Mips ::SP_64) && "Unexpected base register!") ? static_cast <void> (0) : __assert_fail ("MI.getOperand(OpNo).isReg() && (MI.getOperand(OpNo).getReg() == Mips::SP || MI.getOperand(OpNo).getReg() == Mips::SP_64) && \"Unexpected base register!\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn249994/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 750, __PRETTY_FUNCTION__)) |
748 | (MI.getOperand(OpNo).getReg() == Mips::SP ||((MI.getOperand(OpNo).isReg() && (MI.getOperand(OpNo) .getReg() == Mips::SP || MI.getOperand(OpNo).getReg() == Mips ::SP_64) && "Unexpected base register!") ? static_cast <void> (0) : __assert_fail ("MI.getOperand(OpNo).isReg() && (MI.getOperand(OpNo).getReg() == Mips::SP || MI.getOperand(OpNo).getReg() == Mips::SP_64) && \"Unexpected base register!\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn249994/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 750, __PRETTY_FUNCTION__)) |
749 | MI.getOperand(OpNo).getReg() == Mips::SP_64) &&((MI.getOperand(OpNo).isReg() && (MI.getOperand(OpNo) .getReg() == Mips::SP || MI.getOperand(OpNo).getReg() == Mips ::SP_64) && "Unexpected base register!") ? static_cast <void> (0) : __assert_fail ("MI.getOperand(OpNo).isReg() && (MI.getOperand(OpNo).getReg() == Mips::SP || MI.getOperand(OpNo).getReg() == Mips::SP_64) && \"Unexpected base register!\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn249994/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 750, __PRETTY_FUNCTION__)) |
750 | "Unexpected base register!")((MI.getOperand(OpNo).isReg() && (MI.getOperand(OpNo) .getReg() == Mips::SP || MI.getOperand(OpNo).getReg() == Mips ::SP_64) && "Unexpected base register!") ? static_cast <void> (0) : __assert_fail ("MI.getOperand(OpNo).isReg() && (MI.getOperand(OpNo).getReg() == Mips::SP || MI.getOperand(OpNo).getReg() == Mips::SP_64) && \"Unexpected base register!\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn249994/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 750, __PRETTY_FUNCTION__)); |
751 | unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), |
752 | Fixups, STI) >> 2; |
753 | |
754 | return OffBits & 0x1F; |
755 | } |
756 | |
757 | unsigned MipsMCCodeEmitter:: |
758 | getMemEncodingMMGPImm7Lsl2(const MCInst &MI, unsigned OpNo, |
759 | SmallVectorImpl<MCFixup> &Fixups, |
760 | const MCSubtargetInfo &STI) const { |
761 | // Register is encoded in bits 9-7, offset is encoded in bits 6-0. |
762 | assert(MI.getOperand(OpNo).isReg() &&((MI.getOperand(OpNo).isReg() && MI.getOperand(OpNo). getReg() == Mips::GP && "Unexpected base register!") ? static_cast<void> (0) : __assert_fail ("MI.getOperand(OpNo).isReg() && MI.getOperand(OpNo).getReg() == Mips::GP && \"Unexpected base register!\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn249994/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 764, __PRETTY_FUNCTION__)) |
763 | MI.getOperand(OpNo).getReg() == Mips::GP &&((MI.getOperand(OpNo).isReg() && MI.getOperand(OpNo). getReg() == Mips::GP && "Unexpected base register!") ? static_cast<void> (0) : __assert_fail ("MI.getOperand(OpNo).isReg() && MI.getOperand(OpNo).getReg() == Mips::GP && \"Unexpected base register!\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn249994/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 764, __PRETTY_FUNCTION__)) |
764 | "Unexpected base register!")((MI.getOperand(OpNo).isReg() && MI.getOperand(OpNo). getReg() == Mips::GP && "Unexpected base register!") ? static_cast<void> (0) : __assert_fail ("MI.getOperand(OpNo).isReg() && MI.getOperand(OpNo).getReg() == Mips::GP && \"Unexpected base register!\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn249994/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 764, __PRETTY_FUNCTION__)); |
765 | |
766 | unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), |
767 | Fixups, STI) >> 2; |
768 | |
769 | return OffBits & 0x7F; |
770 | } |
771 | |
772 | unsigned MipsMCCodeEmitter:: |
773 | getMemEncodingMMImm9(const MCInst &MI, unsigned OpNo, |
774 | SmallVectorImpl<MCFixup> &Fixups, |
775 | const MCSubtargetInfo &STI) const { |
776 | // Base register is encoded in bits 20-16, offset is encoded in bits 8-0. |
777 | assert(MI.getOperand(OpNo).isReg())((MI.getOperand(OpNo).isReg()) ? static_cast<void> (0) : __assert_fail ("MI.getOperand(OpNo).isReg()", "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn249994/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 777, __PRETTY_FUNCTION__)); |
778 | unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, |
779 | STI) << 16; |
780 | unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo + 1), Fixups, STI); |
781 | |
782 | return (OffBits & 0x1FF) | RegBits; |
783 | } |
784 | |
785 | unsigned MipsMCCodeEmitter:: |
786 | getMemEncodingMMImm12(const MCInst &MI, unsigned OpNo, |
787 | SmallVectorImpl<MCFixup> &Fixups, |
788 | const MCSubtargetInfo &STI) const { |
789 | // opNum can be invalid if instruction had reglist as operand. |
790 | // MemOperand is always last operand of instruction (base + offset). |
791 | switch (MI.getOpcode()) { |
792 | default: |
793 | break; |
794 | case Mips::SWM32_MM: |
795 | case Mips::LWM32_MM: |
796 | OpNo = MI.getNumOperands() - 2; |
797 | break; |
798 | } |
799 | |
800 | // Base register is encoded in bits 20-16, offset is encoded in bits 11-0. |
801 | assert(MI.getOperand(OpNo).isReg())((MI.getOperand(OpNo).isReg()) ? static_cast<void> (0) : __assert_fail ("MI.getOperand(OpNo).isReg()", "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn249994/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 801, __PRETTY_FUNCTION__)); |
802 | unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI) << 16; |
803 | unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI); |
804 | |
805 | return (OffBits & 0x0FFF) | RegBits; |
806 | } |
807 | |
808 | unsigned MipsMCCodeEmitter:: |
809 | getMemEncodingMMImm4sp(const MCInst &MI, unsigned OpNo, |
810 | SmallVectorImpl<MCFixup> &Fixups, |
811 | const MCSubtargetInfo &STI) const { |
812 | // opNum can be invalid if instruction had reglist as operand |
813 | // MemOperand is always last operand of instruction (base + offset) |
814 | switch (MI.getOpcode()) { |
815 | default: |
816 | break; |
817 | case Mips::SWM16_MM: |
818 | case Mips::LWM16_MM: |
819 | OpNo = MI.getNumOperands() - 2; |
820 | break; |
821 | } |
822 | |
823 | // Offset is encoded in bits 4-0. |
824 | assert(MI.getOperand(OpNo).isReg())((MI.getOperand(OpNo).isReg()) ? static_cast<void> (0) : __assert_fail ("MI.getOperand(OpNo).isReg()", "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn249994/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 824, __PRETTY_FUNCTION__)); |
825 | // Base register is always SP - thus it is not encoded. |
826 | assert(MI.getOperand(OpNo+1).isImm())((MI.getOperand(OpNo+1).isImm()) ? static_cast<void> (0 ) : __assert_fail ("MI.getOperand(OpNo+1).isImm()", "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn249994/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 826, __PRETTY_FUNCTION__)); |
827 | unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI); |
828 | |
829 | return ((OffBits >> 2) & 0x0F); |
830 | } |
831 | |
832 | unsigned |
833 | MipsMCCodeEmitter::getSizeExtEncoding(const MCInst &MI, unsigned OpNo, |
834 | SmallVectorImpl<MCFixup> &Fixups, |
835 | const MCSubtargetInfo &STI) const { |
836 | assert(MI.getOperand(OpNo).isImm())((MI.getOperand(OpNo).isImm()) ? static_cast<void> (0) : __assert_fail ("MI.getOperand(OpNo).isImm()", "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn249994/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 836, __PRETTY_FUNCTION__)); |
837 | unsigned SizeEncoding = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI); |
838 | return SizeEncoding - 1; |
839 | } |
840 | |
841 | // FIXME: should be called getMSBEncoding |
842 | // |
843 | unsigned |
844 | MipsMCCodeEmitter::getSizeInsEncoding(const MCInst &MI, unsigned OpNo, |
845 | SmallVectorImpl<MCFixup> &Fixups, |
846 | const MCSubtargetInfo &STI) const { |
847 | assert(MI.getOperand(OpNo-1).isImm())((MI.getOperand(OpNo-1).isImm()) ? static_cast<void> (0 ) : __assert_fail ("MI.getOperand(OpNo-1).isImm()", "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn249994/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 847, __PRETTY_FUNCTION__)); |
848 | assert(MI.getOperand(OpNo).isImm())((MI.getOperand(OpNo).isImm()) ? static_cast<void> (0) : __assert_fail ("MI.getOperand(OpNo).isImm()", "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn249994/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 848, __PRETTY_FUNCTION__)); |
849 | unsigned Position = getMachineOpValue(MI, MI.getOperand(OpNo-1), Fixups, STI); |
850 | unsigned Size = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI); |
851 | |
852 | return Position + Size - 1; |
853 | } |
854 | |
855 | unsigned |
856 | MipsMCCodeEmitter::getLSAImmEncoding(const MCInst &MI, unsigned OpNo, |
857 | SmallVectorImpl<MCFixup> &Fixups, |
858 | const MCSubtargetInfo &STI) const { |
859 | assert(MI.getOperand(OpNo).isImm())((MI.getOperand(OpNo).isImm()) ? static_cast<void> (0) : __assert_fail ("MI.getOperand(OpNo).isImm()", "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn249994/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 859, __PRETTY_FUNCTION__)); |
860 | // The immediate is encoded as 'immediate - 1'. |
861 | return getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI) - 1; |
862 | } |
863 | |
864 | unsigned |
865 | MipsMCCodeEmitter::getSimm19Lsl2Encoding(const MCInst &MI, unsigned OpNo, |
866 | SmallVectorImpl<MCFixup> &Fixups, |
867 | const MCSubtargetInfo &STI) const { |
868 | const MCOperand &MO = MI.getOperand(OpNo); |
869 | if (MO.isImm()) { |
870 | // The immediate is encoded as 'immediate << 2'. |
871 | unsigned Res = getMachineOpValue(MI, MO, Fixups, STI); |
872 | assert((Res & 3) == 0)(((Res & 3) == 0) ? static_cast<void> (0) : __assert_fail ("(Res & 3) == 0", "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn249994/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 872, __PRETTY_FUNCTION__)); |
873 | return Res >> 2; |
874 | } |
875 | |
876 | assert(MO.isExpr() &&((MO.isExpr() && "getSimm19Lsl2Encoding expects only expressions or an immediate" ) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getSimm19Lsl2Encoding expects only expressions or an immediate\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn249994/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 877, __PRETTY_FUNCTION__)) |
877 | "getSimm19Lsl2Encoding expects only expressions or an immediate")((MO.isExpr() && "getSimm19Lsl2Encoding expects only expressions or an immediate" ) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getSimm19Lsl2Encoding expects only expressions or an immediate\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn249994/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 877, __PRETTY_FUNCTION__)); |
878 | |
879 | const MCExpr *Expr = MO.getExpr(); |
880 | Fixups.push_back(MCFixup::create(0, Expr, |
881 | MCFixupKind(Mips::fixup_MIPS_PC19_S2))); |
882 | return 0; |
883 | } |
884 | |
885 | unsigned |
886 | MipsMCCodeEmitter::getSimm18Lsl3Encoding(const MCInst &MI, unsigned OpNo, |
887 | SmallVectorImpl<MCFixup> &Fixups, |
888 | const MCSubtargetInfo &STI) const { |
889 | const MCOperand &MO = MI.getOperand(OpNo); |
890 | if (MO.isImm()) { |
891 | // The immediate is encoded as 'immediate << 3'. |
892 | unsigned Res = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI); |
893 | assert((Res & 7) == 0)(((Res & 7) == 0) ? static_cast<void> (0) : __assert_fail ("(Res & 7) == 0", "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn249994/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 893, __PRETTY_FUNCTION__)); |
894 | return Res >> 3; |
895 | } |
896 | |
897 | assert(MO.isExpr() &&((MO.isExpr() && "getSimm18Lsl2Encoding expects only expressions or an immediate" ) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getSimm18Lsl2Encoding expects only expressions or an immediate\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn249994/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 898, __PRETTY_FUNCTION__)) |
898 | "getSimm18Lsl2Encoding expects only expressions or an immediate")((MO.isExpr() && "getSimm18Lsl2Encoding expects only expressions or an immediate" ) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getSimm18Lsl2Encoding expects only expressions or an immediate\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn249994/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 898, __PRETTY_FUNCTION__)); |
899 | |
900 | const MCExpr *Expr = MO.getExpr(); |
901 | Fixups.push_back(MCFixup::create(0, Expr, |
902 | MCFixupKind(Mips::fixup_MIPS_PC18_S3))); |
903 | return 0; |
904 | } |
905 | |
906 | unsigned |
907 | MipsMCCodeEmitter::getUImm3Mod8Encoding(const MCInst &MI, unsigned OpNo, |
908 | SmallVectorImpl<MCFixup> &Fixups, |
909 | const MCSubtargetInfo &STI) const { |
910 | assert(MI.getOperand(OpNo).isImm())((MI.getOperand(OpNo).isImm()) ? static_cast<void> (0) : __assert_fail ("MI.getOperand(OpNo).isImm()", "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn249994/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 910, __PRETTY_FUNCTION__)); |
911 | const MCOperand &MO = MI.getOperand(OpNo); |
912 | return MO.getImm() % 8; |
913 | } |
914 | |
915 | unsigned |
916 | MipsMCCodeEmitter::getUImm4AndValue(const MCInst &MI, unsigned OpNo, |
917 | SmallVectorImpl<MCFixup> &Fixups, |
918 | const MCSubtargetInfo &STI) const { |
919 | assert(MI.getOperand(OpNo).isImm())((MI.getOperand(OpNo).isImm()) ? static_cast<void> (0) : __assert_fail ("MI.getOperand(OpNo).isImm()", "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn249994/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 919, __PRETTY_FUNCTION__)); |
920 | const MCOperand &MO = MI.getOperand(OpNo); |
921 | unsigned Value = MO.getImm(); |
922 | switch (Value) { |
923 | case 128: return 0x0; |
924 | case 1: return 0x1; |
925 | case 2: return 0x2; |
926 | case 3: return 0x3; |
927 | case 4: return 0x4; |
928 | case 7: return 0x5; |
929 | case 8: return 0x6; |
930 | case 15: return 0x7; |
931 | case 16: return 0x8; |
932 | case 31: return 0x9; |
933 | case 32: return 0xa; |
934 | case 63: return 0xb; |
935 | case 64: return 0xc; |
936 | case 255: return 0xd; |
937 | case 32768: return 0xe; |
938 | case 65535: return 0xf; |
939 | } |
940 | llvm_unreachable("Unexpected value")::llvm::llvm_unreachable_internal("Unexpected value", "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn249994/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 940); |
941 | } |
942 | |
943 | unsigned |
944 | MipsMCCodeEmitter::getRegisterListOpValue(const MCInst &MI, unsigned OpNo, |
945 | SmallVectorImpl<MCFixup> &Fixups, |
946 | const MCSubtargetInfo &STI) const { |
947 | unsigned res = 0; |
948 | |
949 | // Register list operand is always first operand of instruction and it is |
950 | // placed before memory operand (register + imm). |
951 | |
952 | for (unsigned I = OpNo, E = MI.getNumOperands() - 2; I < E; ++I) { |
953 | unsigned Reg = MI.getOperand(I).getReg(); |
954 | unsigned RegNo = Ctx.getRegisterInfo()->getEncodingValue(Reg); |
955 | if (RegNo != 31) |
956 | res++; |
957 | else |
958 | res |= 0x10; |
959 | } |
960 | return res; |
961 | } |
962 | |
963 | unsigned |
964 | MipsMCCodeEmitter::getRegisterListOpValue16(const MCInst &MI, unsigned OpNo, |
965 | SmallVectorImpl<MCFixup> &Fixups, |
966 | const MCSubtargetInfo &STI) const { |
967 | return (MI.getNumOperands() - 4); |
968 | } |
969 | |
970 | unsigned |
971 | MipsMCCodeEmitter::getRegisterPairOpValue(const MCInst &MI, unsigned OpNo, |
972 | SmallVectorImpl<MCFixup> &Fixups, |
973 | const MCSubtargetInfo &STI) const { |
974 | return getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI); |
975 | } |
976 | |
977 | unsigned |
978 | MipsMCCodeEmitter::getMovePRegPairOpValue(const MCInst &MI, unsigned OpNo, |
979 | SmallVectorImpl<MCFixup> &Fixups, |
980 | const MCSubtargetInfo &STI) const { |
981 | unsigned res = 0; |
982 | |
983 | if (MI.getOperand(0).getReg() == Mips::A1 && |
984 | MI.getOperand(1).getReg() == Mips::A2) |
985 | res = 0; |
986 | else if (MI.getOperand(0).getReg() == Mips::A1 && |
987 | MI.getOperand(1).getReg() == Mips::A3) |
988 | res = 1; |
989 | else if (MI.getOperand(0).getReg() == Mips::A2 && |
990 | MI.getOperand(1).getReg() == Mips::A3) |
991 | res = 2; |
992 | else if (MI.getOperand(0).getReg() == Mips::A0 && |
993 | MI.getOperand(1).getReg() == Mips::S5) |
994 | res = 3; |
995 | else if (MI.getOperand(0).getReg() == Mips::A0 && |
996 | MI.getOperand(1).getReg() == Mips::S6) |
997 | res = 4; |
998 | else if (MI.getOperand(0).getReg() == Mips::A0 && |
999 | MI.getOperand(1).getReg() == Mips::A1) |
1000 | res = 5; |
1001 | else if (MI.getOperand(0).getReg() == Mips::A0 && |
1002 | MI.getOperand(1).getReg() == Mips::A2) |
1003 | res = 6; |
1004 | else if (MI.getOperand(0).getReg() == Mips::A0 && |
1005 | MI.getOperand(1).getReg() == Mips::A3) |
1006 | res = 7; |
1007 | |
1008 | return res; |
1009 | } |
1010 | |
1011 | unsigned |
1012 | MipsMCCodeEmitter::getSimm23Lsl2Encoding(const MCInst &MI, unsigned OpNo, |
1013 | SmallVectorImpl<MCFixup> &Fixups, |
1014 | const MCSubtargetInfo &STI) const { |
1015 | const MCOperand &MO = MI.getOperand(OpNo); |
1016 | assert(MO.isImm() && "getSimm23Lsl2Encoding expects only an immediate")((MO.isImm() && "getSimm23Lsl2Encoding expects only an immediate" ) ? static_cast<void> (0) : __assert_fail ("MO.isImm() && \"getSimm23Lsl2Encoding expects only an immediate\"" , "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn249994/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 1016, __PRETTY_FUNCTION__)); |
1017 | // The immediate is encoded as 'immediate >> 2'. |
1018 | unsigned Res = static_cast<unsigned>(MO.getImm()); |
1019 | assert((Res & 3) == 0)(((Res & 3) == 0) ? static_cast<void> (0) : __assert_fail ("(Res & 3) == 0", "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn249994/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp" , 1019, __PRETTY_FUNCTION__)); |
1020 | return Res >> 2; |
1021 | } |
1022 | |
1023 | #include "MipsGenMCCodeEmitter.inc" |