Bug Summary

File:lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
Location:line 201, column 7
Description:Value stored to 'Opcode' is never read

Annotated Source Code

1//===-- MipsMCCodeEmitter.cpp - Convert Mips Code to Machine Code ---------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the MipsMCCodeEmitter class.
11//
12//===----------------------------------------------------------------------===//
13//
14
15#include "MipsMCCodeEmitter.h"
16#include "MCTargetDesc/MipsFixupKinds.h"
17#include "MCTargetDesc/MipsMCExpr.h"
18#include "MCTargetDesc/MipsMCTargetDesc.h"
19#include "llvm/ADT/APFloat.h"
20#include "llvm/ADT/SmallVector.h"
21#include "llvm/MC/MCContext.h"
22#include "llvm/MC/MCExpr.h"
23#include "llvm/MC/MCFixup.h"
24#include "llvm/MC/MCInst.h"
25#include "llvm/MC/MCInstrInfo.h"
26#include "llvm/MC/MCRegisterInfo.h"
27#include "llvm/MC/MCSubtargetInfo.h"
28#include "llvm/Support/raw_ostream.h"
29
30#define DEBUG_TYPE"mccodeemitter" "mccodeemitter"
31
32#define GET_INSTRMAP_INFO
33#include "MipsGenInstrInfo.inc"
34#undef GET_INSTRMAP_INFO
35
36namespace llvm {
37MCCodeEmitter *createMipsMCCodeEmitterEB(const MCInstrInfo &MCII,
38 const MCRegisterInfo &MRI,
39 MCContext &Ctx) {
40 return new MipsMCCodeEmitter(MCII, Ctx, false);
41}
42
43MCCodeEmitter *createMipsMCCodeEmitterEL(const MCInstrInfo &MCII,
44 const MCRegisterInfo &MRI,
45 MCContext &Ctx) {
46 return new MipsMCCodeEmitter(MCII, Ctx, true);
47}
48} // End of namespace llvm.
49
50// If the D<shift> instruction has a shift amount that is greater
51// than 31 (checked in calling routine), lower it to a D<shift>32 instruction
52static void LowerLargeShift(MCInst& Inst) {
53
54 assert(Inst.getNumOperands() == 3 && "Invalid no. of operands for shift!")((Inst.getNumOperands() == 3 && "Invalid no. of operands for shift!"
) ? static_cast<void> (0) : __assert_fail ("Inst.getNumOperands() == 3 && \"Invalid no. of operands for shift!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn257205/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 54, __PRETTY_FUNCTION__));
55 assert(Inst.getOperand(2).isImm())((Inst.getOperand(2).isImm()) ? static_cast<void> (0) :
__assert_fail ("Inst.getOperand(2).isImm()", "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn257205/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 55, __PRETTY_FUNCTION__));
56
57 int64_t Shift = Inst.getOperand(2).getImm();
58 if (Shift <= 31)
59 return; // Do nothing
60 Shift -= 32;
61
62 // saminus32
63 Inst.getOperand(2).setImm(Shift);
64
65 switch (Inst.getOpcode()) {
66 default:
67 // Calling function is not synchronized
68 llvm_unreachable("Unexpected shift instruction")::llvm::llvm_unreachable_internal("Unexpected shift instruction"
, "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn257205/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 68);
69 case Mips::DSLL:
70 Inst.setOpcode(Mips::DSLL32);
71 return;
72 case Mips::DSRL:
73 Inst.setOpcode(Mips::DSRL32);
74 return;
75 case Mips::DSRA:
76 Inst.setOpcode(Mips::DSRA32);
77 return;
78 case Mips::DROTR:
79 Inst.setOpcode(Mips::DROTR32);
80 return;
81 }
82}
83
84// Pick a DEXT or DINS instruction variant based on the pos and size operands
85static void LowerDextDins(MCInst& InstIn) {
86 int Opcode = InstIn.getOpcode();
87
88 if (Opcode == Mips::DEXT)
89 assert(InstIn.getNumOperands() == 4 &&((InstIn.getNumOperands() == 4 && "Invalid no. of machine operands for DEXT!"
) ? static_cast<void> (0) : __assert_fail ("InstIn.getNumOperands() == 4 && \"Invalid no. of machine operands for DEXT!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn257205/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 90, __PRETTY_FUNCTION__))
90 "Invalid no. of machine operands for DEXT!")((InstIn.getNumOperands() == 4 && "Invalid no. of machine operands for DEXT!"
) ? static_cast<void> (0) : __assert_fail ("InstIn.getNumOperands() == 4 && \"Invalid no. of machine operands for DEXT!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn257205/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 90, __PRETTY_FUNCTION__));
91 else // Only DEXT and DINS are possible
92 assert(InstIn.getNumOperands() == 5 &&((InstIn.getNumOperands() == 5 && "Invalid no. of machine operands for DINS!"
) ? static_cast<void> (0) : __assert_fail ("InstIn.getNumOperands() == 5 && \"Invalid no. of machine operands for DINS!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn257205/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 93, __PRETTY_FUNCTION__))
93 "Invalid no. of machine operands for DINS!")((InstIn.getNumOperands() == 5 && "Invalid no. of machine operands for DINS!"
) ? static_cast<void> (0) : __assert_fail ("InstIn.getNumOperands() == 5 && \"Invalid no. of machine operands for DINS!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn257205/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 93, __PRETTY_FUNCTION__));
94
95 assert(InstIn.getOperand(2).isImm())((InstIn.getOperand(2).isImm()) ? static_cast<void> (0)
: __assert_fail ("InstIn.getOperand(2).isImm()", "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn257205/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 95, __PRETTY_FUNCTION__));
96 int64_t pos = InstIn.getOperand(2).getImm();
97 assert(InstIn.getOperand(3).isImm())((InstIn.getOperand(3).isImm()) ? static_cast<void> (0)
: __assert_fail ("InstIn.getOperand(3).isImm()", "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn257205/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 97, __PRETTY_FUNCTION__));
98 int64_t size = InstIn.getOperand(3).getImm();
99
100 if (size <= 32) {
101 if (pos < 32) // DEXT/DINS, do nothing
102 return;
103 // DEXTU/DINSU
104 InstIn.getOperand(2).setImm(pos - 32);
105 InstIn.setOpcode((Opcode == Mips::DEXT) ? Mips::DEXTU : Mips::DINSU);
106 return;
107 }
108 // DEXTM/DINSM
109 assert(pos < 32 && "DEXT/DINS cannot have both size and pos > 32")((pos < 32 && "DEXT/DINS cannot have both size and pos > 32"
) ? static_cast<void> (0) : __assert_fail ("pos < 32 && \"DEXT/DINS cannot have both size and pos > 32\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn257205/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 109, __PRETTY_FUNCTION__));
110 InstIn.getOperand(3).setImm(size - 32);
111 InstIn.setOpcode((Opcode == Mips::DEXT) ? Mips::DEXTM : Mips::DINSM);
112 return;
113}
114
115bool MipsMCCodeEmitter::isMicroMips(const MCSubtargetInfo &STI) const {
116 return STI.getFeatureBits()[Mips::FeatureMicroMips];
117}
118
119bool MipsMCCodeEmitter::isMips32r6(const MCSubtargetInfo &STI) const {
120 return STI.getFeatureBits()[Mips::FeatureMips32r6];
121}
122
123void MipsMCCodeEmitter::EmitByte(unsigned char C, raw_ostream &OS) const {
124 OS << (char)C;
125}
126
127void MipsMCCodeEmitter::EmitInstruction(uint64_t Val, unsigned Size,
128 const MCSubtargetInfo &STI,
129 raw_ostream &OS) const {
130 // Output the instruction encoding in little endian byte order.
131 // Little-endian byte ordering:
132 // mips32r2: 4 | 3 | 2 | 1
133 // microMIPS: 2 | 1 | 4 | 3
134 if (IsLittleEndian && Size == 4 && isMicroMips(STI)) {
135 EmitInstruction(Val >> 16, 2, STI, OS);
136 EmitInstruction(Val, 2, STI, OS);
137 } else {
138 for (unsigned i = 0; i < Size; ++i) {
139 unsigned Shift = IsLittleEndian ? i * 8 : (Size - 1 - i) * 8;
140 EmitByte((Val >> Shift) & 0xff, OS);
141 }
142 }
143}
144
145/// encodeInstruction - Emit the instruction.
146/// Size the instruction with Desc.getSize().
147void MipsMCCodeEmitter::
148encodeInstruction(const MCInst &MI, raw_ostream &OS,
149 SmallVectorImpl<MCFixup> &Fixups,
150 const MCSubtargetInfo &STI) const
151{
152
153 // Non-pseudo instructions that get changed for direct object
154 // only based on operand values.
155 // If this list of instructions get much longer we will move
156 // the check to a function call. Until then, this is more efficient.
157 MCInst TmpInst = MI;
158 switch (MI.getOpcode()) {
159 // If shift amount is >= 32 it the inst needs to be lowered further
160 case Mips::DSLL:
161 case Mips::DSRL:
162 case Mips::DSRA:
163 case Mips::DROTR:
164 LowerLargeShift(TmpInst);
165 break;
166 // Double extract instruction is chosen by pos and size operands
167 case Mips::DEXT:
168 case Mips::DINS:
169 LowerDextDins(TmpInst);
170 }
171
172 unsigned long N = Fixups.size();
173 uint32_t Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
174
175 // Check for unimplemented opcodes.
176 // Unfortunately in MIPS both NOP and SLL will come in with Binary == 0
177 // so we have to special check for them.
178 unsigned Opcode = TmpInst.getOpcode();
179 if ((Opcode != Mips::NOP) && (Opcode != Mips::SLL) &&
180 (Opcode != Mips::SLL_MM) && !Binary)
181 llvm_unreachable("unimplemented opcode in encodeInstruction()")::llvm::llvm_unreachable_internal("unimplemented opcode in encodeInstruction()"
, "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn257205/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 181);
182
183 int NewOpcode = -1;
184 if (isMicroMips(STI)) {
185 if (isMips32r6(STI)) {
186 NewOpcode = Mips::MipsR62MicroMipsR6(Opcode, Mips::Arch_micromipsr6);
187 if (NewOpcode == -1)
188 NewOpcode = Mips::Std2MicroMipsR6(Opcode, Mips::Arch_micromipsr6);
189 }
190 else
191 NewOpcode = Mips::Std2MicroMips(Opcode, Mips::Arch_micromips);
192
193 // Check whether it is Dsp instruction.
194 if (NewOpcode == -1)
195 NewOpcode = Mips::Dsp2MicroMips(Opcode, Mips::Arch_mmdsp);
196
197 if (NewOpcode != -1) {
198 if (Fixups.size() > N)
199 Fixups.pop_back();
200
201 Opcode = NewOpcode;
Value stored to 'Opcode' is never read
202 TmpInst.setOpcode (NewOpcode);
203 Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
204 }
205 }
206
207 const MCInstrDesc &Desc = MCII.get(TmpInst.getOpcode());
208
209 // Get byte count of instruction
210 unsigned Size = Desc.getSize();
211 if (!Size)
212 llvm_unreachable("Desc.getSize() returns 0")::llvm::llvm_unreachable_internal("Desc.getSize() returns 0",
"/tmp/buildd/llvm-toolchain-snapshot-3.8~svn257205/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 212);
213
214 EmitInstruction(Binary, Size, STI, OS);
215}
216
217/// getBranchTargetOpValue - Return binary encoding of the branch
218/// target operand. If the machine operand requires relocation,
219/// record the relocation and return zero.
220unsigned MipsMCCodeEmitter::
221getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
222 SmallVectorImpl<MCFixup> &Fixups,
223 const MCSubtargetInfo &STI) const {
224
225 const MCOperand &MO = MI.getOperand(OpNo);
226
227 // If the destination is an immediate, divide by 4.
228 if (MO.isImm()) return MO.getImm() >> 2;
229
230 assert(MO.isExpr() &&((MO.isExpr() && "getBranchTargetOpValue expects only expressions or immediates"
) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getBranchTargetOpValue expects only expressions or immediates\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn257205/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 231, __PRETTY_FUNCTION__))
231 "getBranchTargetOpValue expects only expressions or immediates")((MO.isExpr() && "getBranchTargetOpValue expects only expressions or immediates"
) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getBranchTargetOpValue expects only expressions or immediates\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn257205/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 231, __PRETTY_FUNCTION__));
232
233 const MCExpr *FixupExpression = MCBinaryExpr::createAdd(
234 MO.getExpr(), MCConstantExpr::create(-4, Ctx), Ctx);
235 Fixups.push_back(MCFixup::create(0, FixupExpression,
236 MCFixupKind(Mips::fixup_Mips_PC16)));
237 return 0;
238}
239
240/// getBranchTarget7OpValueMM - Return binary encoding of the microMIPS branch
241/// target operand. If the machine operand requires relocation,
242/// record the relocation and return zero.
243unsigned MipsMCCodeEmitter::
244getBranchTarget7OpValueMM(const MCInst &MI, unsigned OpNo,
245 SmallVectorImpl<MCFixup> &Fixups,
246 const MCSubtargetInfo &STI) const {
247
248 const MCOperand &MO = MI.getOperand(OpNo);
249
250 // If the destination is an immediate, divide by 2.
251 if (MO.isImm()) return MO.getImm() >> 1;
252
253 assert(MO.isExpr() &&((MO.isExpr() && "getBranchTargetOpValueMM expects only expressions or immediates"
) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getBranchTargetOpValueMM expects only expressions or immediates\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn257205/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 254, __PRETTY_FUNCTION__))
254 "getBranchTargetOpValueMM expects only expressions or immediates")((MO.isExpr() && "getBranchTargetOpValueMM expects only expressions or immediates"
) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getBranchTargetOpValueMM expects only expressions or immediates\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn257205/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 254, __PRETTY_FUNCTION__));
255
256 const MCExpr *Expr = MO.getExpr();
257 Fixups.push_back(MCFixup::create(0, Expr,
258 MCFixupKind(Mips::fixup_MICROMIPS_PC7_S1)));
259 return 0;
260}
261
262/// getBranchTargetOpValueMMPC10 - Return binary encoding of the microMIPS
263/// 10-bit branch target operand. If the machine operand requires relocation,
264/// record the relocation and return zero.
265unsigned MipsMCCodeEmitter::
266getBranchTargetOpValueMMPC10(const MCInst &MI, unsigned OpNo,
267 SmallVectorImpl<MCFixup> &Fixups,
268 const MCSubtargetInfo &STI) const {
269
270 const MCOperand &MO = MI.getOperand(OpNo);
271
272 // If the destination is an immediate, divide by 2.
273 if (MO.isImm()) return MO.getImm() >> 1;
274
275 assert(MO.isExpr() &&((MO.isExpr() && "getBranchTargetOpValuePC10 expects only expressions or immediates"
) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getBranchTargetOpValuePC10 expects only expressions or immediates\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn257205/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 276, __PRETTY_FUNCTION__))
276 "getBranchTargetOpValuePC10 expects only expressions or immediates")((MO.isExpr() && "getBranchTargetOpValuePC10 expects only expressions or immediates"
) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getBranchTargetOpValuePC10 expects only expressions or immediates\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn257205/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 276, __PRETTY_FUNCTION__));
277
278 const MCExpr *Expr = MO.getExpr();
279 Fixups.push_back(MCFixup::create(0, Expr,
280 MCFixupKind(Mips::fixup_MICROMIPS_PC10_S1)));
281 return 0;
282}
283
284/// getBranchTargetOpValue - Return binary encoding of the microMIPS branch
285/// target operand. If the machine operand requires relocation,
286/// record the relocation and return zero.
287unsigned MipsMCCodeEmitter::
288getBranchTargetOpValueMM(const MCInst &MI, unsigned OpNo,
289 SmallVectorImpl<MCFixup> &Fixups,
290 const MCSubtargetInfo &STI) const {
291
292 const MCOperand &MO = MI.getOperand(OpNo);
293
294 // If the destination is an immediate, divide by 2.
295 if (MO.isImm()) return MO.getImm() >> 1;
296
297 assert(MO.isExpr() &&((MO.isExpr() && "getBranchTargetOpValueMM expects only expressions or immediates"
) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getBranchTargetOpValueMM expects only expressions or immediates\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn257205/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 298, __PRETTY_FUNCTION__))
298 "getBranchTargetOpValueMM expects only expressions or immediates")((MO.isExpr() && "getBranchTargetOpValueMM expects only expressions or immediates"
) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getBranchTargetOpValueMM expects only expressions or immediates\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn257205/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 298, __PRETTY_FUNCTION__));
299
300 const MCExpr *Expr = MO.getExpr();
301 Fixups.push_back(MCFixup::create(0, Expr,
302 MCFixupKind(Mips::
303 fixup_MICROMIPS_PC16_S1)));
304 return 0;
305}
306
307/// getBranchTarget21OpValue - Return binary encoding of the branch
308/// target operand. If the machine operand requires relocation,
309/// record the relocation and return zero.
310unsigned MipsMCCodeEmitter::
311getBranchTarget21OpValue(const MCInst &MI, unsigned OpNo,
312 SmallVectorImpl<MCFixup> &Fixups,
313 const MCSubtargetInfo &STI) const {
314
315 const MCOperand &MO = MI.getOperand(OpNo);
316
317 // If the destination is an immediate, divide by 4.
318 if (MO.isImm()) return MO.getImm() >> 2;
319
320 assert(MO.isExpr() &&((MO.isExpr() && "getBranchTarget21OpValue expects only expressions or immediates"
) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getBranchTarget21OpValue expects only expressions or immediates\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn257205/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 321, __PRETTY_FUNCTION__))
321 "getBranchTarget21OpValue expects only expressions or immediates")((MO.isExpr() && "getBranchTarget21OpValue expects only expressions or immediates"
) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getBranchTarget21OpValue expects only expressions or immediates\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn257205/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 321, __PRETTY_FUNCTION__));
322
323 const MCExpr *FixupExpression = MCBinaryExpr::createAdd(
324 MO.getExpr(), MCConstantExpr::create(-4, Ctx), Ctx);
325 Fixups.push_back(MCFixup::create(0, FixupExpression,
326 MCFixupKind(Mips::fixup_MIPS_PC21_S2)));
327 return 0;
328}
329
330/// getBranchTarget26OpValue - Return binary encoding of the branch
331/// target operand. If the machine operand requires relocation,
332/// record the relocation and return zero.
333unsigned MipsMCCodeEmitter::
334getBranchTarget26OpValue(const MCInst &MI, unsigned OpNo,
335 SmallVectorImpl<MCFixup> &Fixups,
336 const MCSubtargetInfo &STI) const {
337
338 const MCOperand &MO = MI.getOperand(OpNo);
339
340 // If the destination is an immediate, divide by 4.
341 if (MO.isImm()) return MO.getImm() >> 2;
342
343 assert(MO.isExpr() &&((MO.isExpr() && "getBranchTarget26OpValue expects only expressions or immediates"
) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getBranchTarget26OpValue expects only expressions or immediates\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn257205/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 344, __PRETTY_FUNCTION__))
344 "getBranchTarget26OpValue expects only expressions or immediates")((MO.isExpr() && "getBranchTarget26OpValue expects only expressions or immediates"
) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getBranchTarget26OpValue expects only expressions or immediates\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn257205/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 344, __PRETTY_FUNCTION__));
345
346 const MCExpr *FixupExpression = MCBinaryExpr::createAdd(
347 MO.getExpr(), MCConstantExpr::create(-4, Ctx), Ctx);
348 Fixups.push_back(MCFixup::create(0, FixupExpression,
349 MCFixupKind(Mips::fixup_MIPS_PC26_S2)));
350 return 0;
351}
352
353/// getBranchTarget26OpValueMM - Return binary encoding of the branch
354/// target operand. If the machine operand requires relocation,
355/// record the relocation and return zero.
356unsigned MipsMCCodeEmitter::getBranchTarget26OpValueMM(
357 const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups,
358 const MCSubtargetInfo &STI) const {
359
360 const MCOperand &MO = MI.getOperand(OpNo);
361
362 // If the destination is an immediate, divide by 2.
363 if (MO.isImm())
364 return MO.getImm() >> 1;
365
366 // TODO: Push 26 PC fixup.
367 return 0;
368}
369
370/// getJumpOffset16OpValue - Return binary encoding of the jump
371/// target operand. If the machine operand requires relocation,
372/// record the relocation and return zero.
373unsigned MipsMCCodeEmitter::
374getJumpOffset16OpValue(const MCInst &MI, unsigned OpNo,
375 SmallVectorImpl<MCFixup> &Fixups,
376 const MCSubtargetInfo &STI) const {
377
378 const MCOperand &MO = MI.getOperand(OpNo);
379
380 if (MO.isImm()) return MO.getImm();
381
382 assert(MO.isExpr() &&((MO.isExpr() && "getJumpOffset16OpValue expects only expressions or an immediate"
) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getJumpOffset16OpValue expects only expressions or an immediate\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn257205/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 383, __PRETTY_FUNCTION__))
383 "getJumpOffset16OpValue expects only expressions or an immediate")((MO.isExpr() && "getJumpOffset16OpValue expects only expressions or an immediate"
) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getJumpOffset16OpValue expects only expressions or an immediate\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn257205/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 383, __PRETTY_FUNCTION__));
384
385 // TODO: Push fixup.
386 return 0;
387}
388
389/// getJumpTargetOpValue - Return binary encoding of the jump
390/// target operand. If the machine operand requires relocation,
391/// record the relocation and return zero.
392unsigned MipsMCCodeEmitter::
393getJumpTargetOpValue(const MCInst &MI, unsigned OpNo,
394 SmallVectorImpl<MCFixup> &Fixups,
395 const MCSubtargetInfo &STI) const {
396
397 const MCOperand &MO = MI.getOperand(OpNo);
398 // If the destination is an immediate, divide by 4.
399 if (MO.isImm()) return MO.getImm()>>2;
400
401 assert(MO.isExpr() &&((MO.isExpr() && "getJumpTargetOpValue expects only expressions or an immediate"
) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getJumpTargetOpValue expects only expressions or an immediate\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn257205/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 402, __PRETTY_FUNCTION__))
402 "getJumpTargetOpValue expects only expressions or an immediate")((MO.isExpr() && "getJumpTargetOpValue expects only expressions or an immediate"
) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getJumpTargetOpValue expects only expressions or an immediate\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn257205/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 402, __PRETTY_FUNCTION__));
403
404 const MCExpr *Expr = MO.getExpr();
405 Fixups.push_back(MCFixup::create(0, Expr,
406 MCFixupKind(Mips::fixup_Mips_26)));
407 return 0;
408}
409
410unsigned MipsMCCodeEmitter::
411getJumpTargetOpValueMM(const MCInst &MI, unsigned OpNo,
412 SmallVectorImpl<MCFixup> &Fixups,
413 const MCSubtargetInfo &STI) const {
414
415 const MCOperand &MO = MI.getOperand(OpNo);
416 // If the destination is an immediate, divide by 2.
417 if (MO.isImm()) return MO.getImm() >> 1;
418
419 assert(MO.isExpr() &&((MO.isExpr() && "getJumpTargetOpValueMM expects only expressions or an immediate"
) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getJumpTargetOpValueMM expects only expressions or an immediate\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn257205/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 420, __PRETTY_FUNCTION__))
420 "getJumpTargetOpValueMM expects only expressions or an immediate")((MO.isExpr() && "getJumpTargetOpValueMM expects only expressions or an immediate"
) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getJumpTargetOpValueMM expects only expressions or an immediate\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn257205/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 420, __PRETTY_FUNCTION__));
421
422 const MCExpr *Expr = MO.getExpr();
423 Fixups.push_back(MCFixup::create(0, Expr,
424 MCFixupKind(Mips::fixup_MICROMIPS_26_S1)));
425 return 0;
426}
427
428unsigned MipsMCCodeEmitter::
429getUImm5Lsl2Encoding(const MCInst &MI, unsigned OpNo,
430 SmallVectorImpl<MCFixup> &Fixups,
431 const MCSubtargetInfo &STI) const {
432
433 const MCOperand &MO = MI.getOperand(OpNo);
434 if (MO.isImm()) {
435 // The immediate is encoded as 'immediate << 2'.
436 unsigned Res = getMachineOpValue(MI, MO, Fixups, STI);
437 assert((Res & 3) == 0)(((Res & 3) == 0) ? static_cast<void> (0) : __assert_fail
("(Res & 3) == 0", "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn257205/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 437, __PRETTY_FUNCTION__));
438 return Res >> 2;
439 }
440
441 assert(MO.isExpr() &&((MO.isExpr() && "getUImm5Lsl2Encoding expects only expressions or an immediate"
) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getUImm5Lsl2Encoding expects only expressions or an immediate\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn257205/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 442, __PRETTY_FUNCTION__))
442 "getUImm5Lsl2Encoding expects only expressions or an immediate")((MO.isExpr() && "getUImm5Lsl2Encoding expects only expressions or an immediate"
) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getUImm5Lsl2Encoding expects only expressions or an immediate\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn257205/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 442, __PRETTY_FUNCTION__));
443
444 return 0;
445}
446
447unsigned MipsMCCodeEmitter::
448getSImm3Lsa2Value(const MCInst &MI, unsigned OpNo,
449 SmallVectorImpl<MCFixup> &Fixups,
450 const MCSubtargetInfo &STI) const {
451
452 const MCOperand &MO = MI.getOperand(OpNo);
453 if (MO.isImm()) {
454 int Value = MO.getImm();
455 return Value >> 2;
456 }
457
458 return 0;
459}
460
461unsigned MipsMCCodeEmitter::
462getUImm6Lsl2Encoding(const MCInst &MI, unsigned OpNo,
463 SmallVectorImpl<MCFixup> &Fixups,
464 const MCSubtargetInfo &STI) const {
465
466 const MCOperand &MO = MI.getOperand(OpNo);
467 if (MO.isImm()) {
468 unsigned Value = MO.getImm();
469 return Value >> 2;
470 }
471
472 return 0;
473}
474
475unsigned MipsMCCodeEmitter::
476getSImm9AddiuspValue(const MCInst &MI, unsigned OpNo,
477 SmallVectorImpl<MCFixup> &Fixups,
478 const MCSubtargetInfo &STI) const {
479
480 const MCOperand &MO = MI.getOperand(OpNo);
481 if (MO.isImm()) {
482 unsigned Binary = (MO.getImm() >> 2) & 0x0000ffff;
483 return (((Binary & 0x8000) >> 7) | (Binary & 0x00ff));
484 }
485
486 return 0;
487}
488
489unsigned MipsMCCodeEmitter::
490getExprOpValue(const MCExpr *Expr, SmallVectorImpl<MCFixup> &Fixups,
491 const MCSubtargetInfo &STI) const {
492 int64_t Res;
493
494 if (Expr->evaluateAsAbsolute(Res))
495 return Res;
496
497 MCExpr::ExprKind Kind = Expr->getKind();
498 if (Kind == MCExpr::Constant) {
499 return cast<MCConstantExpr>(Expr)->getValue();
500 }
501
502 if (Kind == MCExpr::Binary) {
503 unsigned Res = getExprOpValue(cast<MCBinaryExpr>(Expr)->getLHS(), Fixups, STI);
504 Res += getExprOpValue(cast<MCBinaryExpr>(Expr)->getRHS(), Fixups, STI);
505 return Res;
506 }
507
508 if (Kind == MCExpr::Target) {
509 const MipsMCExpr *MipsExpr = cast<MipsMCExpr>(Expr);
510
511 Mips::Fixups FixupKind = Mips::Fixups(0);
512 switch (MipsExpr->getKind()) {
513 default: llvm_unreachable("Unsupported fixup kind for target expression!")::llvm::llvm_unreachable_internal("Unsupported fixup kind for target expression!"
, "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn257205/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 513);
514 case MipsMCExpr::VK_Mips_HIGHEST:
515 FixupKind = Mips::fixup_Mips_HIGHEST;
516 break;
517 case MipsMCExpr::VK_Mips_HIGHER:
518 FixupKind = Mips::fixup_Mips_HIGHER;
519 break;
520 case MipsMCExpr::VK_Mips_HI:
521 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_HI16
522 : Mips::fixup_Mips_HI16;
523 break;
524 case MipsMCExpr::VK_Mips_LO:
525 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_LO16
526 : Mips::fixup_Mips_LO16;
527 break;
528 }
529 Fixups.push_back(MCFixup::create(0, MipsExpr, MCFixupKind(FixupKind)));
530 return 0;
531 }
532
533 if (Kind == MCExpr::SymbolRef) {
534 Mips::Fixups FixupKind = Mips::Fixups(0);
535
536 switch(cast<MCSymbolRefExpr>(Expr)->getKind()) {
537 default: llvm_unreachable("Unknown fixup kind!")::llvm::llvm_unreachable_internal("Unknown fixup kind!", "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn257205/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 537);
538 break;
539 case MCSymbolRefExpr::VK_None:
540 FixupKind = Mips::fixup_Mips_32; // FIXME: This is ok for O32/N32 but not N64.
541 break;
542 case MCSymbolRefExpr::VK_Mips_GPOFF_HI :
543 FixupKind = Mips::fixup_Mips_GPOFF_HI;
544 break;
545 case MCSymbolRefExpr::VK_Mips_GPOFF_LO :
546 FixupKind = Mips::fixup_Mips_GPOFF_LO;
547 break;
548 case MCSymbolRefExpr::VK_Mips_GOT_PAGE :
549 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT_PAGE
550 : Mips::fixup_Mips_GOT_PAGE;
551 break;
552 case MCSymbolRefExpr::VK_Mips_GOT_OFST :
553 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT_OFST
554 : Mips::fixup_Mips_GOT_OFST;
555 break;
556 case MCSymbolRefExpr::VK_Mips_GOT_DISP :
557 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT_DISP
558 : Mips::fixup_Mips_GOT_DISP;
559 break;
560 case MCSymbolRefExpr::VK_Mips_GPREL:
561 FixupKind = Mips::fixup_Mips_GPREL16;
562 break;
563 case MCSymbolRefExpr::VK_Mips_GOT_CALL:
564 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_CALL16
565 : Mips::fixup_Mips_CALL16;
566 break;
567 case MCSymbolRefExpr::VK_Mips_GOT16:
568 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT16
569 : Mips::fixup_Mips_GOT_Global;
570 break;
571 case MCSymbolRefExpr::VK_Mips_GOT:
572 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT16
573 : Mips::fixup_Mips_GOT_Local;
574 break;
575 case MCSymbolRefExpr::VK_Mips_ABS_HI:
576 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_HI16
577 : Mips::fixup_Mips_HI16;
578 break;
579 case MCSymbolRefExpr::VK_Mips_ABS_LO:
580 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_LO16
581 : Mips::fixup_Mips_LO16;
582 break;
583 case MCSymbolRefExpr::VK_Mips_TLSGD:
584 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_GD
585 : Mips::fixup_Mips_TLSGD;
586 break;
587 case MCSymbolRefExpr::VK_Mips_TLSLDM:
588 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_LDM
589 : Mips::fixup_Mips_TLSLDM;
590 break;
591 case MCSymbolRefExpr::VK_Mips_DTPREL_HI:
592 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_DTPREL_HI16
593 : Mips::fixup_Mips_DTPREL_HI;
594 break;
595 case MCSymbolRefExpr::VK_Mips_DTPREL_LO:
596 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_DTPREL_LO16
597 : Mips::fixup_Mips_DTPREL_LO;
598 break;
599 case MCSymbolRefExpr::VK_Mips_GOTTPREL:
600 FixupKind = Mips::fixup_Mips_GOTTPREL;
601 break;
602 case MCSymbolRefExpr::VK_Mips_TPREL_HI:
603 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_TPREL_HI16
604 : Mips::fixup_Mips_TPREL_HI;
605 break;
606 case MCSymbolRefExpr::VK_Mips_TPREL_LO:
607 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_TPREL_LO16
608 : Mips::fixup_Mips_TPREL_LO;
609 break;
610 case MCSymbolRefExpr::VK_Mips_HIGHER:
611 FixupKind = Mips::fixup_Mips_HIGHER;
612 break;
613 case MCSymbolRefExpr::VK_Mips_HIGHEST:
614 FixupKind = Mips::fixup_Mips_HIGHEST;
615 break;
616 case MCSymbolRefExpr::VK_Mips_GOT_HI16:
617 FixupKind = Mips::fixup_Mips_GOT_HI16;
618 break;
619 case MCSymbolRefExpr::VK_Mips_GOT_LO16:
620 FixupKind = Mips::fixup_Mips_GOT_LO16;
621 break;
622 case MCSymbolRefExpr::VK_Mips_CALL_HI16:
623 FixupKind = Mips::fixup_Mips_CALL_HI16;
624 break;
625 case MCSymbolRefExpr::VK_Mips_CALL_LO16:
626 FixupKind = Mips::fixup_Mips_CALL_LO16;
627 break;
628 case MCSymbolRefExpr::VK_Mips_PCREL_HI16:
629 FixupKind = Mips::fixup_MIPS_PCHI16;
630 break;
631 case MCSymbolRefExpr::VK_Mips_PCREL_LO16:
632 FixupKind = Mips::fixup_MIPS_PCLO16;
633 break;
634 } // switch
635
636 Fixups.push_back(MCFixup::create(0, Expr, MCFixupKind(FixupKind)));
637 return 0;
638 }
639 return 0;
640}
641
642/// getMachineOpValue - Return binary encoding of operand. If the machine
643/// operand requires relocation, record the relocation and return zero.
644unsigned MipsMCCodeEmitter::
645getMachineOpValue(const MCInst &MI, const MCOperand &MO,
646 SmallVectorImpl<MCFixup> &Fixups,
647 const MCSubtargetInfo &STI) const {
648 if (MO.isReg()) {
649 unsigned Reg = MO.getReg();
650 unsigned RegNo = Ctx.getRegisterInfo()->getEncodingValue(Reg);
651 return RegNo;
652 } else if (MO.isImm()) {
653 return static_cast<unsigned>(MO.getImm());
654 } else if (MO.isFPImm()) {
655 return static_cast<unsigned>(APFloat(MO.getFPImm())
656 .bitcastToAPInt().getHiBits(32).getLimitedValue());
657 }
658 // MO must be an Expr.
659 assert(MO.isExpr())((MO.isExpr()) ? static_cast<void> (0) : __assert_fail (
"MO.isExpr()", "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn257205/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 659, __PRETTY_FUNCTION__));
660 return getExprOpValue(MO.getExpr(),Fixups, STI);
661}
662
663/// getMSAMemEncoding - Return binary encoding of memory operand for LD/ST
664/// instructions.
665unsigned
666MipsMCCodeEmitter::getMSAMemEncoding(const MCInst &MI, unsigned OpNo,
667 SmallVectorImpl<MCFixup> &Fixups,
668 const MCSubtargetInfo &STI) const {
669 // Base register is encoded in bits 20-16, offset is encoded in bits 15-0.
670 assert(MI.getOperand(OpNo).isReg())((MI.getOperand(OpNo).isReg()) ? static_cast<void> (0) :
__assert_fail ("MI.getOperand(OpNo).isReg()", "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn257205/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 670, __PRETTY_FUNCTION__));
671 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),Fixups, STI) << 16;
672 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
673
674 // The immediate field of an LD/ST instruction is scaled which means it must
675 // be divided (when encoding) by the size (in bytes) of the instructions'
676 // data format.
677 // .b - 1 byte
678 // .h - 2 bytes
679 // .w - 4 bytes
680 // .d - 8 bytes
681 switch(MI.getOpcode())
682 {
683 default:
684 assert (0 && "Unexpected instruction")((0 && "Unexpected instruction") ? static_cast<void
> (0) : __assert_fail ("0 && \"Unexpected instruction\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn257205/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 684, __PRETTY_FUNCTION__));
685 break;
686 case Mips::LD_B:
687 case Mips::ST_B:
688 // We don't need to scale the offset in this case
689 break;
690 case Mips::LD_H:
691 case Mips::ST_H:
692 OffBits >>= 1;
693 break;
694 case Mips::LD_W:
695 case Mips::ST_W:
696 OffBits >>= 2;
697 break;
698 case Mips::LD_D:
699 case Mips::ST_D:
700 OffBits >>= 3;
701 break;
702 }
703
704 return (OffBits & 0xFFFF) | RegBits;
705}
706
707/// getMemEncoding - Return binary encoding of memory related operand.
708/// If the offset operand requires relocation, record the relocation.
709unsigned
710MipsMCCodeEmitter::getMemEncoding(const MCInst &MI, unsigned OpNo,
711 SmallVectorImpl<MCFixup> &Fixups,
712 const MCSubtargetInfo &STI) const {
713 // Base register is encoded in bits 20-16, offset is encoded in bits 15-0.
714 assert(MI.getOperand(OpNo).isReg())((MI.getOperand(OpNo).isReg()) ? static_cast<void> (0) :
__assert_fail ("MI.getOperand(OpNo).isReg()", "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn257205/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 714, __PRETTY_FUNCTION__));
715 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),Fixups, STI) << 16;
716 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
717
718 return (OffBits & 0xFFFF) | RegBits;
719}
720
721unsigned MipsMCCodeEmitter::
722getMemEncodingMMImm4(const MCInst &MI, unsigned OpNo,
723 SmallVectorImpl<MCFixup> &Fixups,
724 const MCSubtargetInfo &STI) const {
725 // Base register is encoded in bits 6-4, offset is encoded in bits 3-0.
726 assert(MI.getOperand(OpNo).isReg())((MI.getOperand(OpNo).isReg()) ? static_cast<void> (0) :
__assert_fail ("MI.getOperand(OpNo).isReg()", "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn257205/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 726, __PRETTY_FUNCTION__));
727 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),
728 Fixups, STI) << 4;
729 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
730 Fixups, STI);
731
732 return (OffBits & 0xF) | RegBits;
733}
734
735unsigned MipsMCCodeEmitter::
736getMemEncodingMMImm4Lsl1(const MCInst &MI, unsigned OpNo,
737 SmallVectorImpl<MCFixup> &Fixups,
738 const MCSubtargetInfo &STI) const {
739 // Base register is encoded in bits 6-4, offset is encoded in bits 3-0.
740 assert(MI.getOperand(OpNo).isReg())((MI.getOperand(OpNo).isReg()) ? static_cast<void> (0) :
__assert_fail ("MI.getOperand(OpNo).isReg()", "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn257205/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 740, __PRETTY_FUNCTION__));
741 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),
742 Fixups, STI) << 4;
743 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
744 Fixups, STI) >> 1;
745
746 return (OffBits & 0xF) | RegBits;
747}
748
749unsigned MipsMCCodeEmitter::
750getMemEncodingMMImm4Lsl2(const MCInst &MI, unsigned OpNo,
751 SmallVectorImpl<MCFixup> &Fixups,
752 const MCSubtargetInfo &STI) const {
753 // Base register is encoded in bits 6-4, offset is encoded in bits 3-0.
754 assert(MI.getOperand(OpNo).isReg())((MI.getOperand(OpNo).isReg()) ? static_cast<void> (0) :
__assert_fail ("MI.getOperand(OpNo).isReg()", "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn257205/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 754, __PRETTY_FUNCTION__));
755 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),
756 Fixups, STI) << 4;
757 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
758 Fixups, STI) >> 2;
759
760 return (OffBits & 0xF) | RegBits;
761}
762
763unsigned MipsMCCodeEmitter::
764getMemEncodingMMSPImm5Lsl2(const MCInst &MI, unsigned OpNo,
765 SmallVectorImpl<MCFixup> &Fixups,
766 const MCSubtargetInfo &STI) const {
767 // Register is encoded in bits 9-5, offset is encoded in bits 4-0.
768 assert(MI.getOperand(OpNo).isReg() &&((MI.getOperand(OpNo).isReg() && (MI.getOperand(OpNo)
.getReg() == Mips::SP || MI.getOperand(OpNo).getReg() == Mips
::SP_64) && "Unexpected base register!") ? static_cast
<void> (0) : __assert_fail ("MI.getOperand(OpNo).isReg() && (MI.getOperand(OpNo).getReg() == Mips::SP || MI.getOperand(OpNo).getReg() == Mips::SP_64) && \"Unexpected base register!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn257205/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 771, __PRETTY_FUNCTION__))
769 (MI.getOperand(OpNo).getReg() == Mips::SP ||((MI.getOperand(OpNo).isReg() && (MI.getOperand(OpNo)
.getReg() == Mips::SP || MI.getOperand(OpNo).getReg() == Mips
::SP_64) && "Unexpected base register!") ? static_cast
<void> (0) : __assert_fail ("MI.getOperand(OpNo).isReg() && (MI.getOperand(OpNo).getReg() == Mips::SP || MI.getOperand(OpNo).getReg() == Mips::SP_64) && \"Unexpected base register!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn257205/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 771, __PRETTY_FUNCTION__))
770 MI.getOperand(OpNo).getReg() == Mips::SP_64) &&((MI.getOperand(OpNo).isReg() && (MI.getOperand(OpNo)
.getReg() == Mips::SP || MI.getOperand(OpNo).getReg() == Mips
::SP_64) && "Unexpected base register!") ? static_cast
<void> (0) : __assert_fail ("MI.getOperand(OpNo).isReg() && (MI.getOperand(OpNo).getReg() == Mips::SP || MI.getOperand(OpNo).getReg() == Mips::SP_64) && \"Unexpected base register!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn257205/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 771, __PRETTY_FUNCTION__))
771 "Unexpected base register!")((MI.getOperand(OpNo).isReg() && (MI.getOperand(OpNo)
.getReg() == Mips::SP || MI.getOperand(OpNo).getReg() == Mips
::SP_64) && "Unexpected base register!") ? static_cast
<void> (0) : __assert_fail ("MI.getOperand(OpNo).isReg() && (MI.getOperand(OpNo).getReg() == Mips::SP || MI.getOperand(OpNo).getReg() == Mips::SP_64) && \"Unexpected base register!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn257205/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 771, __PRETTY_FUNCTION__));
772 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
773 Fixups, STI) >> 2;
774
775 return OffBits & 0x1F;
776}
777
778unsigned MipsMCCodeEmitter::
779getMemEncodingMMGPImm7Lsl2(const MCInst &MI, unsigned OpNo,
780 SmallVectorImpl<MCFixup> &Fixups,
781 const MCSubtargetInfo &STI) const {
782 // Register is encoded in bits 9-7, offset is encoded in bits 6-0.
783 assert(MI.getOperand(OpNo).isReg() &&((MI.getOperand(OpNo).isReg() && MI.getOperand(OpNo).
getReg() == Mips::GP && "Unexpected base register!") ?
static_cast<void> (0) : __assert_fail ("MI.getOperand(OpNo).isReg() && MI.getOperand(OpNo).getReg() == Mips::GP && \"Unexpected base register!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn257205/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 785, __PRETTY_FUNCTION__))
784 MI.getOperand(OpNo).getReg() == Mips::GP &&((MI.getOperand(OpNo).isReg() && MI.getOperand(OpNo).
getReg() == Mips::GP && "Unexpected base register!") ?
static_cast<void> (0) : __assert_fail ("MI.getOperand(OpNo).isReg() && MI.getOperand(OpNo).getReg() == Mips::GP && \"Unexpected base register!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn257205/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 785, __PRETTY_FUNCTION__))
785 "Unexpected base register!")((MI.getOperand(OpNo).isReg() && MI.getOperand(OpNo).
getReg() == Mips::GP && "Unexpected base register!") ?
static_cast<void> (0) : __assert_fail ("MI.getOperand(OpNo).isReg() && MI.getOperand(OpNo).getReg() == Mips::GP && \"Unexpected base register!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn257205/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 785, __PRETTY_FUNCTION__));
786
787 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
788 Fixups, STI) >> 2;
789
790 return OffBits & 0x7F;
791}
792
793unsigned MipsMCCodeEmitter::
794getMemEncodingMMImm9(const MCInst &MI, unsigned OpNo,
795 SmallVectorImpl<MCFixup> &Fixups,
796 const MCSubtargetInfo &STI) const {
797 // Base register is encoded in bits 20-16, offset is encoded in bits 8-0.
798 assert(MI.getOperand(OpNo).isReg())((MI.getOperand(OpNo).isReg()) ? static_cast<void> (0) :
__assert_fail ("MI.getOperand(OpNo).isReg()", "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn257205/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 798, __PRETTY_FUNCTION__));
799 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups,
800 STI) << 16;
801 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo + 1), Fixups, STI);
802
803 return (OffBits & 0x1FF) | RegBits;
804}
805
806unsigned MipsMCCodeEmitter::
807getMemEncodingMMImm12(const MCInst &MI, unsigned OpNo,
808 SmallVectorImpl<MCFixup> &Fixups,
809 const MCSubtargetInfo &STI) const {
810 // opNum can be invalid if instruction had reglist as operand.
811 // MemOperand is always last operand of instruction (base + offset).
812 switch (MI.getOpcode()) {
813 default:
814 break;
815 case Mips::SWM32_MM:
816 case Mips::LWM32_MM:
817 OpNo = MI.getNumOperands() - 2;
818 break;
819 }
820
821 // Base register is encoded in bits 20-16, offset is encoded in bits 11-0.
822 assert(MI.getOperand(OpNo).isReg())((MI.getOperand(OpNo).isReg()) ? static_cast<void> (0) :
__assert_fail ("MI.getOperand(OpNo).isReg()", "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn257205/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 822, __PRETTY_FUNCTION__));
823 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI) << 16;
824 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
825
826 return (OffBits & 0x0FFF) | RegBits;
827}
828
829unsigned MipsMCCodeEmitter::
830getMemEncodingMMImm16(const MCInst &MI, unsigned OpNo,
831 SmallVectorImpl<MCFixup> &Fixups,
832 const MCSubtargetInfo &STI) const {
833 // Base register is encoded in bits 20-16, offset is encoded in bits 15-0.
834 assert(MI.getOperand(OpNo).isReg())((MI.getOperand(OpNo).isReg()) ? static_cast<void> (0) :
__assert_fail ("MI.getOperand(OpNo).isReg()", "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn257205/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 834, __PRETTY_FUNCTION__));
835 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups,
836 STI) << 16;
837 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
838
839 return (OffBits & 0xFFFF) | RegBits;
840}
841
842unsigned MipsMCCodeEmitter::
843getMemEncodingMMImm4sp(const MCInst &MI, unsigned OpNo,
844 SmallVectorImpl<MCFixup> &Fixups,
845 const MCSubtargetInfo &STI) const {
846 // opNum can be invalid if instruction had reglist as operand
847 // MemOperand is always last operand of instruction (base + offset)
848 switch (MI.getOpcode()) {
849 default:
850 break;
851 case Mips::SWM16_MM:
852 case Mips::SWM16_MMR6:
853 case Mips::LWM16_MM:
854 case Mips::LWM16_MMR6:
855 OpNo = MI.getNumOperands() - 2;
856 break;
857 }
858
859 // Offset is encoded in bits 4-0.
860 assert(MI.getOperand(OpNo).isReg())((MI.getOperand(OpNo).isReg()) ? static_cast<void> (0) :
__assert_fail ("MI.getOperand(OpNo).isReg()", "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn257205/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 860, __PRETTY_FUNCTION__));
861 // Base register is always SP - thus it is not encoded.
862 assert(MI.getOperand(OpNo+1).isImm())((MI.getOperand(OpNo+1).isImm()) ? static_cast<void> (0
) : __assert_fail ("MI.getOperand(OpNo+1).isImm()", "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn257205/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 862, __PRETTY_FUNCTION__));
863 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
864
865 return ((OffBits >> 2) & 0x0F);
866}
867
868// FIXME: should be called getMSBEncoding
869//
870unsigned
871MipsMCCodeEmitter::getSizeInsEncoding(const MCInst &MI, unsigned OpNo,
872 SmallVectorImpl<MCFixup> &Fixups,
873 const MCSubtargetInfo &STI) const {
874 assert(MI.getOperand(OpNo-1).isImm())((MI.getOperand(OpNo-1).isImm()) ? static_cast<void> (0
) : __assert_fail ("MI.getOperand(OpNo-1).isImm()", "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn257205/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 874, __PRETTY_FUNCTION__));
875 assert(MI.getOperand(OpNo).isImm())((MI.getOperand(OpNo).isImm()) ? static_cast<void> (0) :
__assert_fail ("MI.getOperand(OpNo).isImm()", "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn257205/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 875, __PRETTY_FUNCTION__));
876 unsigned Position = getMachineOpValue(MI, MI.getOperand(OpNo-1), Fixups, STI);
877 unsigned Size = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI);
878
879 return Position + Size - 1;
880}
881
882template <unsigned Bits, int Offset>
883unsigned
884MipsMCCodeEmitter::getUImmWithOffsetEncoding(const MCInst &MI, unsigned OpNo,
885 SmallVectorImpl<MCFixup> &Fixups,
886 const MCSubtargetInfo &STI) const {
887 assert(MI.getOperand(OpNo).isImm())((MI.getOperand(OpNo).isImm()) ? static_cast<void> (0) :
__assert_fail ("MI.getOperand(OpNo).isImm()", "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn257205/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 887, __PRETTY_FUNCTION__));
888 unsigned Value = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI);
889 Value -= Offset;
890 return Value;
891}
892
893unsigned
894MipsMCCodeEmitter::getSimm19Lsl2Encoding(const MCInst &MI, unsigned OpNo,
895 SmallVectorImpl<MCFixup> &Fixups,
896 const MCSubtargetInfo &STI) const {
897 const MCOperand &MO = MI.getOperand(OpNo);
898 if (MO.isImm()) {
899 // The immediate is encoded as 'immediate << 2'.
900 unsigned Res = getMachineOpValue(MI, MO, Fixups, STI);
901 assert((Res & 3) == 0)(((Res & 3) == 0) ? static_cast<void> (0) : __assert_fail
("(Res & 3) == 0", "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn257205/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 901, __PRETTY_FUNCTION__));
902 return Res >> 2;
903 }
904
905 assert(MO.isExpr() &&((MO.isExpr() && "getSimm19Lsl2Encoding expects only expressions or an immediate"
) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getSimm19Lsl2Encoding expects only expressions or an immediate\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn257205/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 906, __PRETTY_FUNCTION__))
906 "getSimm19Lsl2Encoding expects only expressions or an immediate")((MO.isExpr() && "getSimm19Lsl2Encoding expects only expressions or an immediate"
) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getSimm19Lsl2Encoding expects only expressions or an immediate\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn257205/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 906, __PRETTY_FUNCTION__));
907
908 const MCExpr *Expr = MO.getExpr();
909 Fixups.push_back(MCFixup::create(0, Expr,
910 MCFixupKind(Mips::fixup_MIPS_PC19_S2)));
911 return 0;
912}
913
914unsigned
915MipsMCCodeEmitter::getSimm18Lsl3Encoding(const MCInst &MI, unsigned OpNo,
916 SmallVectorImpl<MCFixup> &Fixups,
917 const MCSubtargetInfo &STI) const {
918 const MCOperand &MO = MI.getOperand(OpNo);
919 if (MO.isImm()) {
920 // The immediate is encoded as 'immediate << 3'.
921 unsigned Res = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI);
922 assert((Res & 7) == 0)(((Res & 7) == 0) ? static_cast<void> (0) : __assert_fail
("(Res & 7) == 0", "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn257205/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 922, __PRETTY_FUNCTION__));
923 return Res >> 3;
924 }
925
926 assert(MO.isExpr() &&((MO.isExpr() && "getSimm18Lsl2Encoding expects only expressions or an immediate"
) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getSimm18Lsl2Encoding expects only expressions or an immediate\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn257205/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 927, __PRETTY_FUNCTION__))
927 "getSimm18Lsl2Encoding expects only expressions or an immediate")((MO.isExpr() && "getSimm18Lsl2Encoding expects only expressions or an immediate"
) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getSimm18Lsl2Encoding expects only expressions or an immediate\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn257205/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 927, __PRETTY_FUNCTION__));
928
929 const MCExpr *Expr = MO.getExpr();
930 Fixups.push_back(MCFixup::create(0, Expr,
931 MCFixupKind(Mips::fixup_MIPS_PC18_S3)));
932 return 0;
933}
934
935unsigned
936MipsMCCodeEmitter::getUImm3Mod8Encoding(const MCInst &MI, unsigned OpNo,
937 SmallVectorImpl<MCFixup> &Fixups,
938 const MCSubtargetInfo &STI) const {
939 assert(MI.getOperand(OpNo).isImm())((MI.getOperand(OpNo).isImm()) ? static_cast<void> (0) :
__assert_fail ("MI.getOperand(OpNo).isImm()", "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn257205/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 939, __PRETTY_FUNCTION__));
940 const MCOperand &MO = MI.getOperand(OpNo);
941 return MO.getImm() % 8;
942}
943
944unsigned
945MipsMCCodeEmitter::getUImm4AndValue(const MCInst &MI, unsigned OpNo,
946 SmallVectorImpl<MCFixup> &Fixups,
947 const MCSubtargetInfo &STI) const {
948 assert(MI.getOperand(OpNo).isImm())((MI.getOperand(OpNo).isImm()) ? static_cast<void> (0) :
__assert_fail ("MI.getOperand(OpNo).isImm()", "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn257205/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 948, __PRETTY_FUNCTION__));
949 const MCOperand &MO = MI.getOperand(OpNo);
950 unsigned Value = MO.getImm();
951 switch (Value) {
952 case 128: return 0x0;
953 case 1: return 0x1;
954 case 2: return 0x2;
955 case 3: return 0x3;
956 case 4: return 0x4;
957 case 7: return 0x5;
958 case 8: return 0x6;
959 case 15: return 0x7;
960 case 16: return 0x8;
961 case 31: return 0x9;
962 case 32: return 0xa;
963 case 63: return 0xb;
964 case 64: return 0xc;
965 case 255: return 0xd;
966 case 32768: return 0xe;
967 case 65535: return 0xf;
968 }
969 llvm_unreachable("Unexpected value")::llvm::llvm_unreachable_internal("Unexpected value", "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn257205/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 969);
970}
971
972unsigned
973MipsMCCodeEmitter::getRegisterListOpValue(const MCInst &MI, unsigned OpNo,
974 SmallVectorImpl<MCFixup> &Fixups,
975 const MCSubtargetInfo &STI) const {
976 unsigned res = 0;
977
978 // Register list operand is always first operand of instruction and it is
979 // placed before memory operand (register + imm).
980
981 for (unsigned I = OpNo, E = MI.getNumOperands() - 2; I < E; ++I) {
982 unsigned Reg = MI.getOperand(I).getReg();
983 unsigned RegNo = Ctx.getRegisterInfo()->getEncodingValue(Reg);
984 if (RegNo != 31)
985 res++;
986 else
987 res |= 0x10;
988 }
989 return res;
990}
991
992unsigned
993MipsMCCodeEmitter::getRegisterListOpValue16(const MCInst &MI, unsigned OpNo,
994 SmallVectorImpl<MCFixup> &Fixups,
995 const MCSubtargetInfo &STI) const {
996 return (MI.getNumOperands() - 4);
997}
998
999unsigned
1000MipsMCCodeEmitter::getRegisterPairOpValue(const MCInst &MI, unsigned OpNo,
1001 SmallVectorImpl<MCFixup> &Fixups,
1002 const MCSubtargetInfo &STI) const {
1003 return getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI);
1004}
1005
1006unsigned
1007MipsMCCodeEmitter::getMovePRegPairOpValue(const MCInst &MI, unsigned OpNo,
1008 SmallVectorImpl<MCFixup> &Fixups,
1009 const MCSubtargetInfo &STI) const {
1010 unsigned res = 0;
1011
1012 if (MI.getOperand(0).getReg() == Mips::A1 &&
1013 MI.getOperand(1).getReg() == Mips::A2)
1014 res = 0;
1015 else if (MI.getOperand(0).getReg() == Mips::A1 &&
1016 MI.getOperand(1).getReg() == Mips::A3)
1017 res = 1;
1018 else if (MI.getOperand(0).getReg() == Mips::A2 &&
1019 MI.getOperand(1).getReg() == Mips::A3)
1020 res = 2;
1021 else if (MI.getOperand(0).getReg() == Mips::A0 &&
1022 MI.getOperand(1).getReg() == Mips::S5)
1023 res = 3;
1024 else if (MI.getOperand(0).getReg() == Mips::A0 &&
1025 MI.getOperand(1).getReg() == Mips::S6)
1026 res = 4;
1027 else if (MI.getOperand(0).getReg() == Mips::A0 &&
1028 MI.getOperand(1).getReg() == Mips::A1)
1029 res = 5;
1030 else if (MI.getOperand(0).getReg() == Mips::A0 &&
1031 MI.getOperand(1).getReg() == Mips::A2)
1032 res = 6;
1033 else if (MI.getOperand(0).getReg() == Mips::A0 &&
1034 MI.getOperand(1).getReg() == Mips::A3)
1035 res = 7;
1036
1037 return res;
1038}
1039
1040unsigned
1041MipsMCCodeEmitter::getSimm23Lsl2Encoding(const MCInst &MI, unsigned OpNo,
1042 SmallVectorImpl<MCFixup> &Fixups,
1043 const MCSubtargetInfo &STI) const {
1044 const MCOperand &MO = MI.getOperand(OpNo);
1045 assert(MO.isImm() && "getSimm23Lsl2Encoding expects only an immediate")((MO.isImm() && "getSimm23Lsl2Encoding expects only an immediate"
) ? static_cast<void> (0) : __assert_fail ("MO.isImm() && \"getSimm23Lsl2Encoding expects only an immediate\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn257205/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 1045, __PRETTY_FUNCTION__));
1046 // The immediate is encoded as 'immediate >> 2'.
1047 unsigned Res = static_cast<unsigned>(MO.getImm());
1048 assert((Res & 3) == 0)(((Res & 3) == 0) ? static_cast<void> (0) : __assert_fail
("(Res & 3) == 0", "/tmp/buildd/llvm-toolchain-snapshot-3.8~svn257205/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 1048, __PRETTY_FUNCTION__));
1049 return Res >> 2;
1050}
1051
1052#include "MipsGenMCCodeEmitter.inc"