Bug Summary

File:lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
Location:line 219, column 7
Description:Value stored to 'Opcode' is never read

Annotated Source Code

1//===-- MipsMCCodeEmitter.cpp - Convert Mips Code to Machine Code ---------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the MipsMCCodeEmitter class.
11//
12//===----------------------------------------------------------------------===//
13//
14
15#include "MipsMCCodeEmitter.h"
16#include "MCTargetDesc/MipsFixupKinds.h"
17#include "MCTargetDesc/MipsMCExpr.h"
18#include "MCTargetDesc/MipsMCTargetDesc.h"
19#include "llvm/ADT/APFloat.h"
20#include "llvm/ADT/SmallVector.h"
21#include "llvm/MC/MCContext.h"
22#include "llvm/MC/MCExpr.h"
23#include "llvm/MC/MCFixup.h"
24#include "llvm/MC/MCInst.h"
25#include "llvm/MC/MCInstrInfo.h"
26#include "llvm/MC/MCRegisterInfo.h"
27#include "llvm/MC/MCSubtargetInfo.h"
28#include "llvm/Support/raw_ostream.h"
29
30#define DEBUG_TYPE"mccodeemitter" "mccodeemitter"
31
32#define GET_INSTRMAP_INFO
33#include "MipsGenInstrInfo.inc"
34#undef GET_INSTRMAP_INFO
35
36namespace llvm {
37MCCodeEmitter *createMipsMCCodeEmitterEB(const MCInstrInfo &MCII,
38 const MCRegisterInfo &MRI,
39 MCContext &Ctx) {
40 return new MipsMCCodeEmitter(MCII, Ctx, false);
41}
42
43MCCodeEmitter *createMipsMCCodeEmitterEL(const MCInstrInfo &MCII,
44 const MCRegisterInfo &MRI,
45 MCContext &Ctx) {
46 return new MipsMCCodeEmitter(MCII, Ctx, true);
47}
48} // End of namespace llvm.
49
50// If the D<shift> instruction has a shift amount that is greater
51// than 31 (checked in calling routine), lower it to a D<shift>32 instruction
52static void LowerLargeShift(MCInst& Inst) {
53
54 assert(Inst.getNumOperands() == 3 && "Invalid no. of operands for shift!")((Inst.getNumOperands() == 3 && "Invalid no. of operands for shift!"
) ? static_cast<void> (0) : __assert_fail ("Inst.getNumOperands() == 3 && \"Invalid no. of operands for shift!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 54, __PRETTY_FUNCTION__));
55 assert(Inst.getOperand(2).isImm())((Inst.getOperand(2).isImm()) ? static_cast<void> (0) :
__assert_fail ("Inst.getOperand(2).isImm()", "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 55, __PRETTY_FUNCTION__));
56
57 int64_t Shift = Inst.getOperand(2).getImm();
58 if (Shift <= 31)
59 return; // Do nothing
60 Shift -= 32;
61
62 // saminus32
63 Inst.getOperand(2).setImm(Shift);
64
65 switch (Inst.getOpcode()) {
66 default:
67 // Calling function is not synchronized
68 llvm_unreachable("Unexpected shift instruction")::llvm::llvm_unreachable_internal("Unexpected shift instruction"
, "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 68);
69 case Mips::DSLL:
70 Inst.setOpcode(Mips::DSLL32);
71 return;
72 case Mips::DSRL:
73 Inst.setOpcode(Mips::DSRL32);
74 return;
75 case Mips::DSRA:
76 Inst.setOpcode(Mips::DSRA32);
77 return;
78 case Mips::DROTR:
79 Inst.setOpcode(Mips::DROTR32);
80 return;
81 }
82}
83
84// Pick a DINS instruction variant based on the pos and size operands
85static void LowerDins(MCInst& InstIn) {
86 assert(InstIn.getNumOperands() == 5 &&((InstIn.getNumOperands() == 5 && "Invalid no. of machine operands for DINS!"
) ? static_cast<void> (0) : __assert_fail ("InstIn.getNumOperands() == 5 && \"Invalid no. of machine operands for DINS!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 87, __PRETTY_FUNCTION__))
87 "Invalid no. of machine operands for DINS!")((InstIn.getNumOperands() == 5 && "Invalid no. of machine operands for DINS!"
) ? static_cast<void> (0) : __assert_fail ("InstIn.getNumOperands() == 5 && \"Invalid no. of machine operands for DINS!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 87, __PRETTY_FUNCTION__));
88
89 assert(InstIn.getOperand(2).isImm())((InstIn.getOperand(2).isImm()) ? static_cast<void> (0)
: __assert_fail ("InstIn.getOperand(2).isImm()", "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 89, __PRETTY_FUNCTION__));
90 int64_t pos = InstIn.getOperand(2).getImm();
91 assert(InstIn.getOperand(3).isImm())((InstIn.getOperand(3).isImm()) ? static_cast<void> (0)
: __assert_fail ("InstIn.getOperand(3).isImm()", "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 91, __PRETTY_FUNCTION__));
92 int64_t size = InstIn.getOperand(3).getImm();
93
94 if (size <= 32) {
95 if (pos < 32) // DINS, do nothing
96 return;
97 // DINSU
98 InstIn.getOperand(2).setImm(pos - 32);
99 InstIn.setOpcode(Mips::DINSU);
100 return;
101 }
102 // DINSM
103 assert(pos < 32 && "DINS cannot have both size and pos > 32")((pos < 32 && "DINS cannot have both size and pos > 32"
) ? static_cast<void> (0) : __assert_fail ("pos < 32 && \"DINS cannot have both size and pos > 32\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 103, __PRETTY_FUNCTION__));
104 InstIn.getOperand(3).setImm(size - 32);
105 InstIn.setOpcode(Mips::DINSM);
106 return;
107}
108
109// Fix a bad compact branch encoding for beqc/bnec.
110void MipsMCCodeEmitter::LowerCompactBranch(MCInst& Inst) const {
111
112 // Encoding may be illegal !(rs < rt), but this situation is
113 // easily fixed.
114 unsigned RegOp0 = Inst.getOperand(0).getReg();
115 unsigned RegOp1 = Inst.getOperand(1).getReg();
116
117 unsigned Reg0 = Ctx.getRegisterInfo()->getEncodingValue(RegOp0);
118 unsigned Reg1 = Ctx.getRegisterInfo()->getEncodingValue(RegOp1);
119
120 assert(Reg0 != Reg1 && "Instruction has bad operands ($rs == $rt)!")((Reg0 != Reg1 && "Instruction has bad operands ($rs == $rt)!"
) ? static_cast<void> (0) : __assert_fail ("Reg0 != Reg1 && \"Instruction has bad operands ($rs == $rt)!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 120, __PRETTY_FUNCTION__));
121 if (Reg0 < Reg1)
122 return;
123
124 Inst.getOperand(0).setReg(RegOp1);
125 Inst.getOperand(1).setReg(RegOp0);
126
127}
128
129bool MipsMCCodeEmitter::isMicroMips(const MCSubtargetInfo &STI) const {
130 return STI.getFeatureBits()[Mips::FeatureMicroMips];
131}
132
133bool MipsMCCodeEmitter::isMips32r6(const MCSubtargetInfo &STI) const {
134 return STI.getFeatureBits()[Mips::FeatureMips32r6];
135}
136
137void MipsMCCodeEmitter::EmitByte(unsigned char C, raw_ostream &OS) const {
138 OS << (char)C;
139}
140
141void MipsMCCodeEmitter::EmitInstruction(uint64_t Val, unsigned Size,
142 const MCSubtargetInfo &STI,
143 raw_ostream &OS) const {
144 // Output the instruction encoding in little endian byte order.
145 // Little-endian byte ordering:
146 // mips32r2: 4 | 3 | 2 | 1
147 // microMIPS: 2 | 1 | 4 | 3
148 if (IsLittleEndian && Size == 4 && isMicroMips(STI)) {
149 EmitInstruction(Val >> 16, 2, STI, OS);
150 EmitInstruction(Val, 2, STI, OS);
151 } else {
152 for (unsigned i = 0; i < Size; ++i) {
153 unsigned Shift = IsLittleEndian ? i * 8 : (Size - 1 - i) * 8;
154 EmitByte((Val >> Shift) & 0xff, OS);
155 }
156 }
157}
158
159/// encodeInstruction - Emit the instruction.
160/// Size the instruction with Desc.getSize().
161void MipsMCCodeEmitter::
162encodeInstruction(const MCInst &MI, raw_ostream &OS,
163 SmallVectorImpl<MCFixup> &Fixups,
164 const MCSubtargetInfo &STI) const
165{
166
167 // Non-pseudo instructions that get changed for direct object
168 // only based on operand values.
169 // If this list of instructions get much longer we will move
170 // the check to a function call. Until then, this is more efficient.
171 MCInst TmpInst = MI;
172 switch (MI.getOpcode()) {
173 // If shift amount is >= 32 it the inst needs to be lowered further
174 case Mips::DSLL:
175 case Mips::DSRL:
176 case Mips::DSRA:
177 case Mips::DROTR:
178 LowerLargeShift(TmpInst);
179 break;
180 // Double extract instruction is chosen by pos and size operands
181 case Mips::DINS:
182 LowerDins(TmpInst);
183 break;
184 // Compact branches.
185 case Mips::BEQC:
186 case Mips::BNEC:
187 LowerCompactBranch(TmpInst);
188 }
189
190 unsigned long N = Fixups.size();
191 uint32_t Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
192
193 // Check for unimplemented opcodes.
194 // Unfortunately in MIPS both NOP and SLL will come in with Binary == 0
195 // so we have to special check for them.
196 unsigned Opcode = TmpInst.getOpcode();
197 if ((Opcode != Mips::NOP) && (Opcode != Mips::SLL) &&
198 (Opcode != Mips::SLL_MM) && !Binary)
199 llvm_unreachable("unimplemented opcode in encodeInstruction()")::llvm::llvm_unreachable_internal("unimplemented opcode in encodeInstruction()"
, "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 199);
200
201 int NewOpcode = -1;
202 if (isMicroMips(STI)) {
203 if (isMips32r6(STI)) {
204 NewOpcode = Mips::MipsR62MicroMipsR6(Opcode, Mips::Arch_micromipsr6);
205 if (NewOpcode == -1)
206 NewOpcode = Mips::Std2MicroMipsR6(Opcode, Mips::Arch_micromipsr6);
207 }
208 else
209 NewOpcode = Mips::Std2MicroMips(Opcode, Mips::Arch_micromips);
210
211 // Check whether it is Dsp instruction.
212 if (NewOpcode == -1)
213 NewOpcode = Mips::Dsp2MicroMips(Opcode, Mips::Arch_mmdsp);
214
215 if (NewOpcode != -1) {
216 if (Fixups.size() > N)
217 Fixups.pop_back();
218
219 Opcode = NewOpcode;
Value stored to 'Opcode' is never read
220 TmpInst.setOpcode (NewOpcode);
221 Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
222 }
223 }
224
225 const MCInstrDesc &Desc = MCII.get(TmpInst.getOpcode());
226
227 // Get byte count of instruction
228 unsigned Size = Desc.getSize();
229 if (!Size)
230 llvm_unreachable("Desc.getSize() returns 0")::llvm::llvm_unreachable_internal("Desc.getSize() returns 0",
"/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 230);
231
232 EmitInstruction(Binary, Size, STI, OS);
233}
234
235/// getBranchTargetOpValue - Return binary encoding of the branch
236/// target operand. If the machine operand requires relocation,
237/// record the relocation and return zero.
238unsigned MipsMCCodeEmitter::
239getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
240 SmallVectorImpl<MCFixup> &Fixups,
241 const MCSubtargetInfo &STI) const {
242
243 const MCOperand &MO = MI.getOperand(OpNo);
244
245 // If the destination is an immediate, divide by 4.
246 if (MO.isImm()) return MO.getImm() >> 2;
247
248 assert(MO.isExpr() &&((MO.isExpr() && "getBranchTargetOpValue expects only expressions or immediates"
) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getBranchTargetOpValue expects only expressions or immediates\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 249, __PRETTY_FUNCTION__))
249 "getBranchTargetOpValue expects only expressions or immediates")((MO.isExpr() && "getBranchTargetOpValue expects only expressions or immediates"
) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getBranchTargetOpValue expects only expressions or immediates\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 249, __PRETTY_FUNCTION__));
250
251 const MCExpr *FixupExpression = MCBinaryExpr::createAdd(
252 MO.getExpr(), MCConstantExpr::create(-4, Ctx), Ctx);
253 Fixups.push_back(MCFixup::create(0, FixupExpression,
254 MCFixupKind(Mips::fixup_Mips_PC16)));
255 return 0;
256}
257
258/// getBranchTargetOpValue1SImm16 - Return binary encoding of the branch
259/// target operand. If the machine operand requires relocation,
260/// record the relocation and return zero.
261unsigned MipsMCCodeEmitter::
262getBranchTargetOpValue1SImm16(const MCInst &MI, unsigned OpNo,
263 SmallVectorImpl<MCFixup> &Fixups,
264 const MCSubtargetInfo &STI) const {
265
266 const MCOperand &MO = MI.getOperand(OpNo);
267
268 // If the destination is an immediate, divide by 2.
269 if (MO.isImm()) return MO.getImm() >> 1;
270
271 assert(MO.isExpr() &&((MO.isExpr() && "getBranchTargetOpValue expects only expressions or immediates"
) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getBranchTargetOpValue expects only expressions or immediates\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 272, __PRETTY_FUNCTION__))
272 "getBranchTargetOpValue expects only expressions or immediates")((MO.isExpr() && "getBranchTargetOpValue expects only expressions or immediates"
) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getBranchTargetOpValue expects only expressions or immediates\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 272, __PRETTY_FUNCTION__));
273
274 const MCExpr *FixupExpression = MCBinaryExpr::createAdd(
275 MO.getExpr(), MCConstantExpr::create(-4, Ctx), Ctx);
276 Fixups.push_back(MCFixup::create(0, FixupExpression,
277 MCFixupKind(Mips::fixup_Mips_PC16)));
278 return 0;
279}
280
281/// getBranchTarget7OpValueMM - Return binary encoding of the microMIPS branch
282/// target operand. If the machine operand requires relocation,
283/// record the relocation and return zero.
284unsigned MipsMCCodeEmitter::
285getBranchTarget7OpValueMM(const MCInst &MI, unsigned OpNo,
286 SmallVectorImpl<MCFixup> &Fixups,
287 const MCSubtargetInfo &STI) const {
288
289 const MCOperand &MO = MI.getOperand(OpNo);
290
291 // If the destination is an immediate, divide by 2.
292 if (MO.isImm()) return MO.getImm() >> 1;
293
294 assert(MO.isExpr() &&((MO.isExpr() && "getBranchTargetOpValueMM expects only expressions or immediates"
) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getBranchTargetOpValueMM expects only expressions or immediates\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 295, __PRETTY_FUNCTION__))
295 "getBranchTargetOpValueMM expects only expressions or immediates")((MO.isExpr() && "getBranchTargetOpValueMM expects only expressions or immediates"
) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getBranchTargetOpValueMM expects only expressions or immediates\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 295, __PRETTY_FUNCTION__));
296
297 const MCExpr *Expr = MO.getExpr();
298 Fixups.push_back(MCFixup::create(0, Expr,
299 MCFixupKind(Mips::fixup_MICROMIPS_PC7_S1)));
300 return 0;
301}
302
303/// getBranchTargetOpValueMMPC10 - Return binary encoding of the microMIPS
304/// 10-bit branch target operand. If the machine operand requires relocation,
305/// record the relocation and return zero.
306unsigned MipsMCCodeEmitter::
307getBranchTargetOpValueMMPC10(const MCInst &MI, unsigned OpNo,
308 SmallVectorImpl<MCFixup> &Fixups,
309 const MCSubtargetInfo &STI) const {
310
311 const MCOperand &MO = MI.getOperand(OpNo);
312
313 // If the destination is an immediate, divide by 2.
314 if (MO.isImm()) return MO.getImm() >> 1;
315
316 assert(MO.isExpr() &&((MO.isExpr() && "getBranchTargetOpValuePC10 expects only expressions or immediates"
) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getBranchTargetOpValuePC10 expects only expressions or immediates\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 317, __PRETTY_FUNCTION__))
317 "getBranchTargetOpValuePC10 expects only expressions or immediates")((MO.isExpr() && "getBranchTargetOpValuePC10 expects only expressions or immediates"
) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getBranchTargetOpValuePC10 expects only expressions or immediates\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 317, __PRETTY_FUNCTION__));
318
319 const MCExpr *Expr = MO.getExpr();
320 Fixups.push_back(MCFixup::create(0, Expr,
321 MCFixupKind(Mips::fixup_MICROMIPS_PC10_S1)));
322 return 0;
323}
324
325/// getBranchTargetOpValue - Return binary encoding of the microMIPS branch
326/// target operand. If the machine operand requires relocation,
327/// record the relocation and return zero.
328unsigned MipsMCCodeEmitter::
329getBranchTargetOpValueMM(const MCInst &MI, unsigned OpNo,
330 SmallVectorImpl<MCFixup> &Fixups,
331 const MCSubtargetInfo &STI) const {
332
333 const MCOperand &MO = MI.getOperand(OpNo);
334
335 // If the destination is an immediate, divide by 2.
336 if (MO.isImm()) return MO.getImm() >> 1;
337
338 assert(MO.isExpr() &&((MO.isExpr() && "getBranchTargetOpValueMM expects only expressions or immediates"
) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getBranchTargetOpValueMM expects only expressions or immediates\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 339, __PRETTY_FUNCTION__))
339 "getBranchTargetOpValueMM expects only expressions or immediates")((MO.isExpr() && "getBranchTargetOpValueMM expects only expressions or immediates"
) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getBranchTargetOpValueMM expects only expressions or immediates\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 339, __PRETTY_FUNCTION__));
340
341 const MCExpr *Expr = MO.getExpr();
342 Fixups.push_back(MCFixup::create(0, Expr,
343 MCFixupKind(Mips::
344 fixup_MICROMIPS_PC16_S1)));
345 return 0;
346}
347
348/// getBranchTarget21OpValue - Return binary encoding of the branch
349/// target operand. If the machine operand requires relocation,
350/// record the relocation and return zero.
351unsigned MipsMCCodeEmitter::
352getBranchTarget21OpValue(const MCInst &MI, unsigned OpNo,
353 SmallVectorImpl<MCFixup> &Fixups,
354 const MCSubtargetInfo &STI) const {
355
356 const MCOperand &MO = MI.getOperand(OpNo);
357
358 // If the destination is an immediate, divide by 4.
359 if (MO.isImm()) return MO.getImm() >> 2;
360
361 assert(MO.isExpr() &&((MO.isExpr() && "getBranchTarget21OpValue expects only expressions or immediates"
) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getBranchTarget21OpValue expects only expressions or immediates\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 362, __PRETTY_FUNCTION__))
362 "getBranchTarget21OpValue expects only expressions or immediates")((MO.isExpr() && "getBranchTarget21OpValue expects only expressions or immediates"
) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getBranchTarget21OpValue expects only expressions or immediates\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 362, __PRETTY_FUNCTION__));
363
364 const MCExpr *FixupExpression = MCBinaryExpr::createAdd(
365 MO.getExpr(), MCConstantExpr::create(-4, Ctx), Ctx);
366 Fixups.push_back(MCFixup::create(0, FixupExpression,
367 MCFixupKind(Mips::fixup_MIPS_PC21_S2)));
368 return 0;
369}
370
371/// getBranchTarget21OpValueMM - Return binary encoding of the branch
372/// target operand for microMIPS. If the machine operand requires
373/// relocation, record the relocation and return zero.
374unsigned MipsMCCodeEmitter::
375getBranchTarget21OpValueMM(const MCInst &MI, unsigned OpNo,
376 SmallVectorImpl<MCFixup> &Fixups,
377 const MCSubtargetInfo &STI) const {
378
379 const MCOperand &MO = MI.getOperand(OpNo);
380
381 // If the destination is an immediate, divide by 2.
382 if (MO.isImm()) return MO.getImm() >> 1;
383
384 assert(MO.isExpr() &&((MO.isExpr() && "getBranchTarget21OpValueMM expects only expressions or immediates"
) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getBranchTarget21OpValueMM expects only expressions or immediates\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 385, __PRETTY_FUNCTION__))
385 "getBranchTarget21OpValueMM expects only expressions or immediates")((MO.isExpr() && "getBranchTarget21OpValueMM expects only expressions or immediates"
) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getBranchTarget21OpValueMM expects only expressions or immediates\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 385, __PRETTY_FUNCTION__));
386
387 const MCExpr *FixupExpression = MCBinaryExpr::createAdd(
388 MO.getExpr(), MCConstantExpr::create(-4, Ctx), Ctx);
389 Fixups.push_back(MCFixup::create(0, FixupExpression,
390 MCFixupKind(Mips::fixup_MICROMIPS_PC21_S1)));
391 return 0;
392}
393
394/// getBranchTarget26OpValue - Return binary encoding of the branch
395/// target operand. If the machine operand requires relocation,
396/// record the relocation and return zero.
397unsigned MipsMCCodeEmitter::
398getBranchTarget26OpValue(const MCInst &MI, unsigned OpNo,
399 SmallVectorImpl<MCFixup> &Fixups,
400 const MCSubtargetInfo &STI) const {
401
402 const MCOperand &MO = MI.getOperand(OpNo);
403
404 // If the destination is an immediate, divide by 4.
405 if (MO.isImm()) return MO.getImm() >> 2;
406
407 assert(MO.isExpr() &&((MO.isExpr() && "getBranchTarget26OpValue expects only expressions or immediates"
) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getBranchTarget26OpValue expects only expressions or immediates\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 408, __PRETTY_FUNCTION__))
408 "getBranchTarget26OpValue expects only expressions or immediates")((MO.isExpr() && "getBranchTarget26OpValue expects only expressions or immediates"
) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getBranchTarget26OpValue expects only expressions or immediates\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 408, __PRETTY_FUNCTION__));
409
410 const MCExpr *FixupExpression = MCBinaryExpr::createAdd(
411 MO.getExpr(), MCConstantExpr::create(-4, Ctx), Ctx);
412 Fixups.push_back(MCFixup::create(0, FixupExpression,
413 MCFixupKind(Mips::fixup_MIPS_PC26_S2)));
414 return 0;
415}
416
417/// getBranchTarget26OpValueMM - Return binary encoding of the branch
418/// target operand. If the machine operand requires relocation,
419/// record the relocation and return zero.
420unsigned MipsMCCodeEmitter::getBranchTarget26OpValueMM(
421 const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups,
422 const MCSubtargetInfo &STI) const {
423
424 const MCOperand &MO = MI.getOperand(OpNo);
425
426 // If the destination is an immediate, divide by 2.
427 if (MO.isImm())
428 return MO.getImm() >> 1;
429
430 assert(MO.isExpr() &&((MO.isExpr() && "getBranchTarget26OpValueMM expects only expressions or immediates"
) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getBranchTarget26OpValueMM expects only expressions or immediates\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 431, __PRETTY_FUNCTION__))
431 "getBranchTarget26OpValueMM expects only expressions or immediates")((MO.isExpr() && "getBranchTarget26OpValueMM expects only expressions or immediates"
) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getBranchTarget26OpValueMM expects only expressions or immediates\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 431, __PRETTY_FUNCTION__));
432
433 const MCExpr *FixupExpression = MCBinaryExpr::createAdd(
434 MO.getExpr(), MCConstantExpr::create(-4, Ctx), Ctx);
435 Fixups.push_back(MCFixup::create(0, FixupExpression,
436 MCFixupKind(Mips::fixup_MICROMIPS_PC26_S1)));
437 return 0;
438}
439
440/// getJumpOffset16OpValue - Return binary encoding of the jump
441/// target operand. If the machine operand requires relocation,
442/// record the relocation and return zero.
443unsigned MipsMCCodeEmitter::
444getJumpOffset16OpValue(const MCInst &MI, unsigned OpNo,
445 SmallVectorImpl<MCFixup> &Fixups,
446 const MCSubtargetInfo &STI) const {
447
448 const MCOperand &MO = MI.getOperand(OpNo);
449
450 if (MO.isImm()) return MO.getImm();
451
452 assert(MO.isExpr() &&((MO.isExpr() && "getJumpOffset16OpValue expects only expressions or an immediate"
) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getJumpOffset16OpValue expects only expressions or an immediate\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 453, __PRETTY_FUNCTION__))
453 "getJumpOffset16OpValue expects only expressions or an immediate")((MO.isExpr() && "getJumpOffset16OpValue expects only expressions or an immediate"
) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getJumpOffset16OpValue expects only expressions or an immediate\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 453, __PRETTY_FUNCTION__));
454
455 // TODO: Push fixup.
456 return 0;
457}
458
459/// getJumpTargetOpValue - Return binary encoding of the jump
460/// target operand. If the machine operand requires relocation,
461/// record the relocation and return zero.
462unsigned MipsMCCodeEmitter::
463getJumpTargetOpValue(const MCInst &MI, unsigned OpNo,
464 SmallVectorImpl<MCFixup> &Fixups,
465 const MCSubtargetInfo &STI) const {
466
467 const MCOperand &MO = MI.getOperand(OpNo);
468 // If the destination is an immediate, divide by 4.
469 if (MO.isImm()) return MO.getImm()>>2;
470
471 assert(MO.isExpr() &&((MO.isExpr() && "getJumpTargetOpValue expects only expressions or an immediate"
) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getJumpTargetOpValue expects only expressions or an immediate\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 472, __PRETTY_FUNCTION__))
472 "getJumpTargetOpValue expects only expressions or an immediate")((MO.isExpr() && "getJumpTargetOpValue expects only expressions or an immediate"
) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getJumpTargetOpValue expects only expressions or an immediate\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 472, __PRETTY_FUNCTION__));
473
474 const MCExpr *Expr = MO.getExpr();
475 Fixups.push_back(MCFixup::create(0, Expr,
476 MCFixupKind(Mips::fixup_Mips_26)));
477 return 0;
478}
479
480unsigned MipsMCCodeEmitter::
481getJumpTargetOpValueMM(const MCInst &MI, unsigned OpNo,
482 SmallVectorImpl<MCFixup> &Fixups,
483 const MCSubtargetInfo &STI) const {
484
485 const MCOperand &MO = MI.getOperand(OpNo);
486 // If the destination is an immediate, divide by 2.
487 if (MO.isImm()) return MO.getImm() >> 1;
488
489 assert(MO.isExpr() &&((MO.isExpr() && "getJumpTargetOpValueMM expects only expressions or an immediate"
) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getJumpTargetOpValueMM expects only expressions or an immediate\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 490, __PRETTY_FUNCTION__))
490 "getJumpTargetOpValueMM expects only expressions or an immediate")((MO.isExpr() && "getJumpTargetOpValueMM expects only expressions or an immediate"
) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getJumpTargetOpValueMM expects only expressions or an immediate\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 490, __PRETTY_FUNCTION__));
491
492 const MCExpr *Expr = MO.getExpr();
493 Fixups.push_back(MCFixup::create(0, Expr,
494 MCFixupKind(Mips::fixup_MICROMIPS_26_S1)));
495 return 0;
496}
497
498unsigned MipsMCCodeEmitter::
499getUImm5Lsl2Encoding(const MCInst &MI, unsigned OpNo,
500 SmallVectorImpl<MCFixup> &Fixups,
501 const MCSubtargetInfo &STI) const {
502
503 const MCOperand &MO = MI.getOperand(OpNo);
504 if (MO.isImm()) {
505 // The immediate is encoded as 'immediate << 2'.
506 unsigned Res = getMachineOpValue(MI, MO, Fixups, STI);
507 assert((Res & 3) == 0)(((Res & 3) == 0) ? static_cast<void> (0) : __assert_fail
("(Res & 3) == 0", "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 507, __PRETTY_FUNCTION__));
508 return Res >> 2;
509 }
510
511 assert(MO.isExpr() &&((MO.isExpr() && "getUImm5Lsl2Encoding expects only expressions or an immediate"
) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getUImm5Lsl2Encoding expects only expressions or an immediate\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 512, __PRETTY_FUNCTION__))
512 "getUImm5Lsl2Encoding expects only expressions or an immediate")((MO.isExpr() && "getUImm5Lsl2Encoding expects only expressions or an immediate"
) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getUImm5Lsl2Encoding expects only expressions or an immediate\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 512, __PRETTY_FUNCTION__));
513
514 return 0;
515}
516
517unsigned MipsMCCodeEmitter::
518getSImm3Lsa2Value(const MCInst &MI, unsigned OpNo,
519 SmallVectorImpl<MCFixup> &Fixups,
520 const MCSubtargetInfo &STI) const {
521
522 const MCOperand &MO = MI.getOperand(OpNo);
523 if (MO.isImm()) {
524 int Value = MO.getImm();
525 return Value >> 2;
526 }
527
528 return 0;
529}
530
531unsigned MipsMCCodeEmitter::
532getUImm6Lsl2Encoding(const MCInst &MI, unsigned OpNo,
533 SmallVectorImpl<MCFixup> &Fixups,
534 const MCSubtargetInfo &STI) const {
535
536 const MCOperand &MO = MI.getOperand(OpNo);
537 if (MO.isImm()) {
538 unsigned Value = MO.getImm();
539 return Value >> 2;
540 }
541
542 return 0;
543}
544
545unsigned MipsMCCodeEmitter::
546getSImm9AddiuspValue(const MCInst &MI, unsigned OpNo,
547 SmallVectorImpl<MCFixup> &Fixups,
548 const MCSubtargetInfo &STI) const {
549
550 const MCOperand &MO = MI.getOperand(OpNo);
551 if (MO.isImm()) {
552 unsigned Binary = (MO.getImm() >> 2) & 0x0000ffff;
553 return (((Binary & 0x8000) >> 7) | (Binary & 0x00ff));
554 }
555
556 return 0;
557}
558
559unsigned MipsMCCodeEmitter::
560getExprOpValue(const MCExpr *Expr, SmallVectorImpl<MCFixup> &Fixups,
561 const MCSubtargetInfo &STI) const {
562 int64_t Res;
563
564 if (Expr->evaluateAsAbsolute(Res))
565 return Res;
566
567 MCExpr::ExprKind Kind = Expr->getKind();
568 if (Kind == MCExpr::Constant) {
569 return cast<MCConstantExpr>(Expr)->getValue();
570 }
571
572 if (Kind == MCExpr::Binary) {
573 unsigned Res = getExprOpValue(cast<MCBinaryExpr>(Expr)->getLHS(), Fixups, STI);
574 Res += getExprOpValue(cast<MCBinaryExpr>(Expr)->getRHS(), Fixups, STI);
575 return Res;
576 }
577
578 if (Kind == MCExpr::Target) {
579 const MipsMCExpr *MipsExpr = cast<MipsMCExpr>(Expr);
580
581 Mips::Fixups FixupKind = Mips::Fixups(0);
582 switch (MipsExpr->getKind()) {
583 case MipsMCExpr::MEK_NEG:
584 case MipsMCExpr::MEK_None:
585 case MipsMCExpr::MEK_Special:
586 llvm_unreachable("Unhandled fixup kind!")::llvm::llvm_unreachable_internal("Unhandled fixup kind!", "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 586);
587 break;
588 case MipsMCExpr::MEK_CALL_HI16:
589 FixupKind = Mips::fixup_Mips_CALL_HI16;
590 break;
591 case MipsMCExpr::MEK_CALL_LO16:
592 FixupKind = Mips::fixup_Mips_CALL_LO16;
593 break;
594 case MipsMCExpr::MEK_DTPREL_HI:
595 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_DTPREL_HI16
596 : Mips::fixup_Mips_DTPREL_HI;
597 break;
598 case MipsMCExpr::MEK_DTPREL_LO:
599 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_DTPREL_LO16
600 : Mips::fixup_Mips_DTPREL_LO;
601 break;
602 case MipsMCExpr::MEK_GOTTPREL:
603 FixupKind = Mips::fixup_Mips_GOTTPREL;
604 break;
605 case MipsMCExpr::MEK_GOT:
606 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT16
607 : Mips::fixup_Mips_GOT;
608 break;
609 case MipsMCExpr::MEK_GOT_CALL:
610 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_CALL16
611 : Mips::fixup_Mips_CALL16;
612 break;
613 case MipsMCExpr::MEK_GOT_DISP:
614 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT_DISP
615 : Mips::fixup_Mips_GOT_DISP;
616 break;
617 case MipsMCExpr::MEK_GOT_HI16:
618 FixupKind = Mips::fixup_Mips_GOT_HI16;
619 break;
620 case MipsMCExpr::MEK_GOT_LO16:
621 FixupKind = Mips::fixup_Mips_GOT_LO16;
622 break;
623 case MipsMCExpr::MEK_GOT_PAGE:
624 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT_PAGE
625 : Mips::fixup_Mips_GOT_PAGE;
626 break;
627 case MipsMCExpr::MEK_GOT_OFST:
628 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT_OFST
629 : Mips::fixup_Mips_GOT_OFST;
630 break;
631 case MipsMCExpr::MEK_GPREL:
632 FixupKind = Mips::fixup_Mips_GPREL16;
633 break;
634 case MipsMCExpr::MEK_LO: {
635 // Check for %lo(%neg(%gp_rel(X)))
636 if (MipsExpr->isGpOff()) {
637 FixupKind = Mips::fixup_Mips_GPOFF_LO;
638 break;
639 }
640 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_LO16
641 : Mips::fixup_Mips_LO16;
642 break;
643 }
644 case MipsMCExpr::MEK_HIGHEST:
645 FixupKind = Mips::fixup_Mips_HIGHEST;
646 break;
647 case MipsMCExpr::MEK_HIGHER:
648 FixupKind = Mips::fixup_Mips_HIGHER;
649 break;
650 case MipsMCExpr::MEK_HI:
651 // Check for %hi(%neg(%gp_rel(X)))
652 if (MipsExpr->isGpOff()) {
653 FixupKind = Mips::fixup_Mips_GPOFF_HI;
654 break;
655 }
656 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_HI16
657 : Mips::fixup_Mips_HI16;
658 break;
659 case MipsMCExpr::MEK_PCREL_HI16:
660 FixupKind = Mips::fixup_MIPS_PCHI16;
661 break;
662 case MipsMCExpr::MEK_PCREL_LO16:
663 FixupKind = Mips::fixup_MIPS_PCLO16;
664 break;
665 case MipsMCExpr::MEK_TLSGD:
666 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_GD
667 : Mips::fixup_Mips_TLSGD;
668 break;
669 case MipsMCExpr::MEK_TLSLDM:
670 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_LDM
671 : Mips::fixup_Mips_TLSLDM;
672 break;
673 case MipsMCExpr::MEK_TPREL_HI:
674 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_TPREL_HI16
675 : Mips::fixup_Mips_TPREL_HI;
676 break;
677 case MipsMCExpr::MEK_TPREL_LO:
678 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_TPREL_LO16
679 : Mips::fixup_Mips_TPREL_LO;
680 break;
681 }
682 Fixups.push_back(MCFixup::create(0, MipsExpr, MCFixupKind(FixupKind)));
683 return 0;
684 }
685
686 if (Kind == MCExpr::SymbolRef) {
687 Mips::Fixups FixupKind = Mips::Fixups(0);
688
689 switch(cast<MCSymbolRefExpr>(Expr)->getKind()) {
690 default: llvm_unreachable("Unknown fixup kind!")::llvm::llvm_unreachable_internal("Unknown fixup kind!", "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 690);
691 break;
692 case MCSymbolRefExpr::VK_None:
693 FixupKind = Mips::fixup_Mips_32; // FIXME: This is ok for O32/N32 but not N64.
694 break;
695 } // switch
696
697 Fixups.push_back(MCFixup::create(0, Expr, MCFixupKind(FixupKind)));
698 return 0;
699 }
700 return 0;
701}
702
703/// getMachineOpValue - Return binary encoding of operand. If the machine
704/// operand requires relocation, record the relocation and return zero.
705unsigned MipsMCCodeEmitter::
706getMachineOpValue(const MCInst &MI, const MCOperand &MO,
707 SmallVectorImpl<MCFixup> &Fixups,
708 const MCSubtargetInfo &STI) const {
709 if (MO.isReg()) {
710 unsigned Reg = MO.getReg();
711 unsigned RegNo = Ctx.getRegisterInfo()->getEncodingValue(Reg);
712 return RegNo;
713 } else if (MO.isImm()) {
714 return static_cast<unsigned>(MO.getImm());
715 } else if (MO.isFPImm()) {
716 return static_cast<unsigned>(APFloat(MO.getFPImm())
717 .bitcastToAPInt().getHiBits(32).getLimitedValue());
718 }
719 // MO must be an Expr.
720 assert(MO.isExpr())((MO.isExpr()) ? static_cast<void> (0) : __assert_fail (
"MO.isExpr()", "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 720, __PRETTY_FUNCTION__));
721 return getExprOpValue(MO.getExpr(),Fixups, STI);
722}
723
724/// Return binary encoding of memory related operand.
725/// If the offset operand requires relocation, record the relocation.
726template <unsigned ShiftAmount>
727unsigned MipsMCCodeEmitter::getMemEncoding(const MCInst &MI, unsigned OpNo,
728 SmallVectorImpl<MCFixup> &Fixups,
729 const MCSubtargetInfo &STI) const {
730 // Base register is encoded in bits 20-16, offset is encoded in bits 15-0.
731 assert(MI.getOperand(OpNo).isReg())((MI.getOperand(OpNo).isReg()) ? static_cast<void> (0) :
__assert_fail ("MI.getOperand(OpNo).isReg()", "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 731, __PRETTY_FUNCTION__));
732 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),Fixups, STI) << 16;
733 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
734
735 // Apply the scale factor if there is one.
736 OffBits >>= ShiftAmount;
737
738 return (OffBits & 0xFFFF) | RegBits;
739}
740
741unsigned MipsMCCodeEmitter::
742getMemEncodingMMImm4(const MCInst &MI, unsigned OpNo,
743 SmallVectorImpl<MCFixup> &Fixups,
744 const MCSubtargetInfo &STI) const {
745 // Base register is encoded in bits 6-4, offset is encoded in bits 3-0.
746 assert(MI.getOperand(OpNo).isReg())((MI.getOperand(OpNo).isReg()) ? static_cast<void> (0) :
__assert_fail ("MI.getOperand(OpNo).isReg()", "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 746, __PRETTY_FUNCTION__));
747 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),
748 Fixups, STI) << 4;
749 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
750 Fixups, STI);
751
752 return (OffBits & 0xF) | RegBits;
753}
754
755unsigned MipsMCCodeEmitter::
756getMemEncodingMMImm4Lsl1(const MCInst &MI, unsigned OpNo,
757 SmallVectorImpl<MCFixup> &Fixups,
758 const MCSubtargetInfo &STI) const {
759 // Base register is encoded in bits 6-4, offset is encoded in bits 3-0.
760 assert(MI.getOperand(OpNo).isReg())((MI.getOperand(OpNo).isReg()) ? static_cast<void> (0) :
__assert_fail ("MI.getOperand(OpNo).isReg()", "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 760, __PRETTY_FUNCTION__));
761 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),
762 Fixups, STI) << 4;
763 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
764 Fixups, STI) >> 1;
765
766 return (OffBits & 0xF) | RegBits;
767}
768
769unsigned MipsMCCodeEmitter::
770getMemEncodingMMImm4Lsl2(const MCInst &MI, unsigned OpNo,
771 SmallVectorImpl<MCFixup> &Fixups,
772 const MCSubtargetInfo &STI) const {
773 // Base register is encoded in bits 6-4, offset is encoded in bits 3-0.
774 assert(MI.getOperand(OpNo).isReg())((MI.getOperand(OpNo).isReg()) ? static_cast<void> (0) :
__assert_fail ("MI.getOperand(OpNo).isReg()", "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 774, __PRETTY_FUNCTION__));
775 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),
776 Fixups, STI) << 4;
777 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
778 Fixups, STI) >> 2;
779
780 return (OffBits & 0xF) | RegBits;
781}
782
783unsigned MipsMCCodeEmitter::
784getMemEncodingMMSPImm5Lsl2(const MCInst &MI, unsigned OpNo,
785 SmallVectorImpl<MCFixup> &Fixups,
786 const MCSubtargetInfo &STI) const {
787 // Register is encoded in bits 9-5, offset is encoded in bits 4-0.
788 assert(MI.getOperand(OpNo).isReg() &&((MI.getOperand(OpNo).isReg() && (MI.getOperand(OpNo)
.getReg() == Mips::SP || MI.getOperand(OpNo).getReg() == Mips
::SP_64) && "Unexpected base register!") ? static_cast
<void> (0) : __assert_fail ("MI.getOperand(OpNo).isReg() && (MI.getOperand(OpNo).getReg() == Mips::SP || MI.getOperand(OpNo).getReg() == Mips::SP_64) && \"Unexpected base register!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 791, __PRETTY_FUNCTION__))
789 (MI.getOperand(OpNo).getReg() == Mips::SP ||((MI.getOperand(OpNo).isReg() && (MI.getOperand(OpNo)
.getReg() == Mips::SP || MI.getOperand(OpNo).getReg() == Mips
::SP_64) && "Unexpected base register!") ? static_cast
<void> (0) : __assert_fail ("MI.getOperand(OpNo).isReg() && (MI.getOperand(OpNo).getReg() == Mips::SP || MI.getOperand(OpNo).getReg() == Mips::SP_64) && \"Unexpected base register!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 791, __PRETTY_FUNCTION__))
790 MI.getOperand(OpNo).getReg() == Mips::SP_64) &&((MI.getOperand(OpNo).isReg() && (MI.getOperand(OpNo)
.getReg() == Mips::SP || MI.getOperand(OpNo).getReg() == Mips
::SP_64) && "Unexpected base register!") ? static_cast
<void> (0) : __assert_fail ("MI.getOperand(OpNo).isReg() && (MI.getOperand(OpNo).getReg() == Mips::SP || MI.getOperand(OpNo).getReg() == Mips::SP_64) && \"Unexpected base register!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 791, __PRETTY_FUNCTION__))
791 "Unexpected base register!")((MI.getOperand(OpNo).isReg() && (MI.getOperand(OpNo)
.getReg() == Mips::SP || MI.getOperand(OpNo).getReg() == Mips
::SP_64) && "Unexpected base register!") ? static_cast
<void> (0) : __assert_fail ("MI.getOperand(OpNo).isReg() && (MI.getOperand(OpNo).getReg() == Mips::SP || MI.getOperand(OpNo).getReg() == Mips::SP_64) && \"Unexpected base register!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 791, __PRETTY_FUNCTION__));
792 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
793 Fixups, STI) >> 2;
794
795 return OffBits & 0x1F;
796}
797
798unsigned MipsMCCodeEmitter::
799getMemEncodingMMGPImm7Lsl2(const MCInst &MI, unsigned OpNo,
800 SmallVectorImpl<MCFixup> &Fixups,
801 const MCSubtargetInfo &STI) const {
802 // Register is encoded in bits 9-7, offset is encoded in bits 6-0.
803 assert(MI.getOperand(OpNo).isReg() &&((MI.getOperand(OpNo).isReg() && MI.getOperand(OpNo).
getReg() == Mips::GP && "Unexpected base register!") ?
static_cast<void> (0) : __assert_fail ("MI.getOperand(OpNo).isReg() && MI.getOperand(OpNo).getReg() == Mips::GP && \"Unexpected base register!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 805, __PRETTY_FUNCTION__))
804 MI.getOperand(OpNo).getReg() == Mips::GP &&((MI.getOperand(OpNo).isReg() && MI.getOperand(OpNo).
getReg() == Mips::GP && "Unexpected base register!") ?
static_cast<void> (0) : __assert_fail ("MI.getOperand(OpNo).isReg() && MI.getOperand(OpNo).getReg() == Mips::GP && \"Unexpected base register!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 805, __PRETTY_FUNCTION__))
805 "Unexpected base register!")((MI.getOperand(OpNo).isReg() && MI.getOperand(OpNo).
getReg() == Mips::GP && "Unexpected base register!") ?
static_cast<void> (0) : __assert_fail ("MI.getOperand(OpNo).isReg() && MI.getOperand(OpNo).getReg() == Mips::GP && \"Unexpected base register!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 805, __PRETTY_FUNCTION__));
806
807 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
808 Fixups, STI) >> 2;
809
810 return OffBits & 0x7F;
811}
812
813unsigned MipsMCCodeEmitter::
814getMemEncodingMMImm9(const MCInst &MI, unsigned OpNo,
815 SmallVectorImpl<MCFixup> &Fixups,
816 const MCSubtargetInfo &STI) const {
817 // Base register is encoded in bits 20-16, offset is encoded in bits 8-0.
818 assert(MI.getOperand(OpNo).isReg())((MI.getOperand(OpNo).isReg()) ? static_cast<void> (0) :
__assert_fail ("MI.getOperand(OpNo).isReg()", "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 818, __PRETTY_FUNCTION__));
819 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups,
820 STI) << 16;
821 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo + 1), Fixups, STI);
822
823 return (OffBits & 0x1FF) | RegBits;
824}
825
826unsigned MipsMCCodeEmitter::
827getMemEncodingMMImm12(const MCInst &MI, unsigned OpNo,
828 SmallVectorImpl<MCFixup> &Fixups,
829 const MCSubtargetInfo &STI) const {
830 // opNum can be invalid if instruction had reglist as operand.
831 // MemOperand is always last operand of instruction (base + offset).
832 switch (MI.getOpcode()) {
833 default:
834 break;
835 case Mips::SWM32_MM:
836 case Mips::LWM32_MM:
837 OpNo = MI.getNumOperands() - 2;
838 break;
839 }
840
841 // Base register is encoded in bits 20-16, offset is encoded in bits 11-0.
842 assert(MI.getOperand(OpNo).isReg())((MI.getOperand(OpNo).isReg()) ? static_cast<void> (0) :
__assert_fail ("MI.getOperand(OpNo).isReg()", "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 842, __PRETTY_FUNCTION__));
843 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI) << 16;
844 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
845
846 return (OffBits & 0x0FFF) | RegBits;
847}
848
849unsigned MipsMCCodeEmitter::
850getMemEncodingMMImm16(const MCInst &MI, unsigned OpNo,
851 SmallVectorImpl<MCFixup> &Fixups,
852 const MCSubtargetInfo &STI) const {
853 // Base register is encoded in bits 20-16, offset is encoded in bits 15-0.
854 assert(MI.getOperand(OpNo).isReg())((MI.getOperand(OpNo).isReg()) ? static_cast<void> (0) :
__assert_fail ("MI.getOperand(OpNo).isReg()", "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 854, __PRETTY_FUNCTION__));
855 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups,
856 STI) << 16;
857 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
858
859 return (OffBits & 0xFFFF) | RegBits;
860}
861
862unsigned MipsMCCodeEmitter::
863getMemEncodingMMImm4sp(const MCInst &MI, unsigned OpNo,
864 SmallVectorImpl<MCFixup> &Fixups,
865 const MCSubtargetInfo &STI) const {
866 // opNum can be invalid if instruction had reglist as operand
867 // MemOperand is always last operand of instruction (base + offset)
868 switch (MI.getOpcode()) {
869 default:
870 break;
871 case Mips::SWM16_MM:
872 case Mips::SWM16_MMR6:
873 case Mips::LWM16_MM:
874 case Mips::LWM16_MMR6:
875 OpNo = MI.getNumOperands() - 2;
876 break;
877 }
878
879 // Offset is encoded in bits 4-0.
880 assert(MI.getOperand(OpNo).isReg())((MI.getOperand(OpNo).isReg()) ? static_cast<void> (0) :
__assert_fail ("MI.getOperand(OpNo).isReg()", "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 880, __PRETTY_FUNCTION__));
881 // Base register is always SP - thus it is not encoded.
882 assert(MI.getOperand(OpNo+1).isImm())((MI.getOperand(OpNo+1).isImm()) ? static_cast<void> (0
) : __assert_fail ("MI.getOperand(OpNo+1).isImm()", "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 882, __PRETTY_FUNCTION__));
883 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
884
885 return ((OffBits >> 2) & 0x0F);
886}
887
888// FIXME: should be called getMSBEncoding
889//
890unsigned
891MipsMCCodeEmitter::getSizeInsEncoding(const MCInst &MI, unsigned OpNo,
892 SmallVectorImpl<MCFixup> &Fixups,
893 const MCSubtargetInfo &STI) const {
894 assert(MI.getOperand(OpNo-1).isImm())((MI.getOperand(OpNo-1).isImm()) ? static_cast<void> (0
) : __assert_fail ("MI.getOperand(OpNo-1).isImm()", "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 894, __PRETTY_FUNCTION__));
895 assert(MI.getOperand(OpNo).isImm())((MI.getOperand(OpNo).isImm()) ? static_cast<void> (0) :
__assert_fail ("MI.getOperand(OpNo).isImm()", "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 895, __PRETTY_FUNCTION__));
896 unsigned Position = getMachineOpValue(MI, MI.getOperand(OpNo-1), Fixups, STI);
897 unsigned Size = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI);
898
899 return Position + Size - 1;
900}
901
902template <unsigned Bits, int Offset>
903unsigned
904MipsMCCodeEmitter::getUImmWithOffsetEncoding(const MCInst &MI, unsigned OpNo,
905 SmallVectorImpl<MCFixup> &Fixups,
906 const MCSubtargetInfo &STI) const {
907 assert(MI.getOperand(OpNo).isImm())((MI.getOperand(OpNo).isImm()) ? static_cast<void> (0) :
__assert_fail ("MI.getOperand(OpNo).isImm()", "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 907, __PRETTY_FUNCTION__));
908 unsigned Value = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI);
909 Value -= Offset;
910 return Value;
911}
912
913unsigned
914MipsMCCodeEmitter::getSimm19Lsl2Encoding(const MCInst &MI, unsigned OpNo,
915 SmallVectorImpl<MCFixup> &Fixups,
916 const MCSubtargetInfo &STI) const {
917 const MCOperand &MO = MI.getOperand(OpNo);
918 if (MO.isImm()) {
919 // The immediate is encoded as 'immediate << 2'.
920 unsigned Res = getMachineOpValue(MI, MO, Fixups, STI);
921 assert((Res & 3) == 0)(((Res & 3) == 0) ? static_cast<void> (0) : __assert_fail
("(Res & 3) == 0", "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 921, __PRETTY_FUNCTION__));
922 return Res >> 2;
923 }
924
925 assert(MO.isExpr() &&((MO.isExpr() && "getSimm19Lsl2Encoding expects only expressions or an immediate"
) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getSimm19Lsl2Encoding expects only expressions or an immediate\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 926, __PRETTY_FUNCTION__))
926 "getSimm19Lsl2Encoding expects only expressions or an immediate")((MO.isExpr() && "getSimm19Lsl2Encoding expects only expressions or an immediate"
) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getSimm19Lsl2Encoding expects only expressions or an immediate\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 926, __PRETTY_FUNCTION__));
927
928 const MCExpr *Expr = MO.getExpr();
929 Mips::Fixups FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_PC19_S2
930 : Mips::fixup_MIPS_PC19_S2;
931 Fixups.push_back(MCFixup::create(0, Expr, MCFixupKind(FixupKind)));
932 return 0;
933}
934
935unsigned
936MipsMCCodeEmitter::getSimm18Lsl3Encoding(const MCInst &MI, unsigned OpNo,
937 SmallVectorImpl<MCFixup> &Fixups,
938 const MCSubtargetInfo &STI) const {
939 const MCOperand &MO = MI.getOperand(OpNo);
940 if (MO.isImm()) {
941 // The immediate is encoded as 'immediate << 3'.
942 unsigned Res = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI);
943 assert((Res & 7) == 0)(((Res & 7) == 0) ? static_cast<void> (0) : __assert_fail
("(Res & 7) == 0", "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 943, __PRETTY_FUNCTION__));
944 return Res >> 3;
945 }
946
947 assert(MO.isExpr() &&((MO.isExpr() && "getSimm18Lsl2Encoding expects only expressions or an immediate"
) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getSimm18Lsl2Encoding expects only expressions or an immediate\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 948, __PRETTY_FUNCTION__))
948 "getSimm18Lsl2Encoding expects only expressions or an immediate")((MO.isExpr() && "getSimm18Lsl2Encoding expects only expressions or an immediate"
) ? static_cast<void> (0) : __assert_fail ("MO.isExpr() && \"getSimm18Lsl2Encoding expects only expressions or an immediate\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 948, __PRETTY_FUNCTION__));
949
950 const MCExpr *Expr = MO.getExpr();
951 Mips::Fixups FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_PC18_S3
952 : Mips::fixup_MIPS_PC18_S3;
953 Fixups.push_back(MCFixup::create(0, Expr, MCFixupKind(FixupKind)));
954 return 0;
955}
956
957unsigned
958MipsMCCodeEmitter::getUImm3Mod8Encoding(const MCInst &MI, unsigned OpNo,
959 SmallVectorImpl<MCFixup> &Fixups,
960 const MCSubtargetInfo &STI) const {
961 assert(MI.getOperand(OpNo).isImm())((MI.getOperand(OpNo).isImm()) ? static_cast<void> (0) :
__assert_fail ("MI.getOperand(OpNo).isImm()", "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 961, __PRETTY_FUNCTION__));
962 const MCOperand &MO = MI.getOperand(OpNo);
963 return MO.getImm() % 8;
964}
965
966unsigned
967MipsMCCodeEmitter::getUImm4AndValue(const MCInst &MI, unsigned OpNo,
968 SmallVectorImpl<MCFixup> &Fixups,
969 const MCSubtargetInfo &STI) const {
970 assert(MI.getOperand(OpNo).isImm())((MI.getOperand(OpNo).isImm()) ? static_cast<void> (0) :
__assert_fail ("MI.getOperand(OpNo).isImm()", "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 970, __PRETTY_FUNCTION__));
971 const MCOperand &MO = MI.getOperand(OpNo);
972 unsigned Value = MO.getImm();
973 switch (Value) {
974 case 128: return 0x0;
975 case 1: return 0x1;
976 case 2: return 0x2;
977 case 3: return 0x3;
978 case 4: return 0x4;
979 case 7: return 0x5;
980 case 8: return 0x6;
981 case 15: return 0x7;
982 case 16: return 0x8;
983 case 31: return 0x9;
984 case 32: return 0xa;
985 case 63: return 0xb;
986 case 64: return 0xc;
987 case 255: return 0xd;
988 case 32768: return 0xe;
989 case 65535: return 0xf;
990 }
991 llvm_unreachable("Unexpected value")::llvm::llvm_unreachable_internal("Unexpected value", "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 991);
992}
993
994unsigned
995MipsMCCodeEmitter::getRegisterListOpValue(const MCInst &MI, unsigned OpNo,
996 SmallVectorImpl<MCFixup> &Fixups,
997 const MCSubtargetInfo &STI) const {
998 unsigned res = 0;
999
1000 // Register list operand is always first operand of instruction and it is
1001 // placed before memory operand (register + imm).
1002
1003 for (unsigned I = OpNo, E = MI.getNumOperands() - 2; I < E; ++I) {
1004 unsigned Reg = MI.getOperand(I).getReg();
1005 unsigned RegNo = Ctx.getRegisterInfo()->getEncodingValue(Reg);
1006 if (RegNo != 31)
1007 res++;
1008 else
1009 res |= 0x10;
1010 }
1011 return res;
1012}
1013
1014unsigned
1015MipsMCCodeEmitter::getRegisterListOpValue16(const MCInst &MI, unsigned OpNo,
1016 SmallVectorImpl<MCFixup> &Fixups,
1017 const MCSubtargetInfo &STI) const {
1018 return (MI.getNumOperands() - 4);
1019}
1020
1021unsigned
1022MipsMCCodeEmitter::getRegisterPairOpValue(const MCInst &MI, unsigned OpNo,
1023 SmallVectorImpl<MCFixup> &Fixups,
1024 const MCSubtargetInfo &STI) const {
1025 return getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI);
1026}
1027
1028unsigned
1029MipsMCCodeEmitter::getMovePRegPairOpValue(const MCInst &MI, unsigned OpNo,
1030 SmallVectorImpl<MCFixup> &Fixups,
1031 const MCSubtargetInfo &STI) const {
1032 unsigned res = 0;
1033
1034 if (MI.getOperand(0).getReg() == Mips::A1 &&
1035 MI.getOperand(1).getReg() == Mips::A2)
1036 res = 0;
1037 else if (MI.getOperand(0).getReg() == Mips::A1 &&
1038 MI.getOperand(1).getReg() == Mips::A3)
1039 res = 1;
1040 else if (MI.getOperand(0).getReg() == Mips::A2 &&
1041 MI.getOperand(1).getReg() == Mips::A3)
1042 res = 2;
1043 else if (MI.getOperand(0).getReg() == Mips::A0 &&
1044 MI.getOperand(1).getReg() == Mips::S5)
1045 res = 3;
1046 else if (MI.getOperand(0).getReg() == Mips::A0 &&
1047 MI.getOperand(1).getReg() == Mips::S6)
1048 res = 4;
1049 else if (MI.getOperand(0).getReg() == Mips::A0 &&
1050 MI.getOperand(1).getReg() == Mips::A1)
1051 res = 5;
1052 else if (MI.getOperand(0).getReg() == Mips::A0 &&
1053 MI.getOperand(1).getReg() == Mips::A2)
1054 res = 6;
1055 else if (MI.getOperand(0).getReg() == Mips::A0 &&
1056 MI.getOperand(1).getReg() == Mips::A3)
1057 res = 7;
1058
1059 return res;
1060}
1061
1062unsigned
1063MipsMCCodeEmitter::getSimm23Lsl2Encoding(const MCInst &MI, unsigned OpNo,
1064 SmallVectorImpl<MCFixup> &Fixups,
1065 const MCSubtargetInfo &STI) const {
1066 const MCOperand &MO = MI.getOperand(OpNo);
1067 assert(MO.isImm() && "getSimm23Lsl2Encoding expects only an immediate")((MO.isImm() && "getSimm23Lsl2Encoding expects only an immediate"
) ? static_cast<void> (0) : __assert_fail ("MO.isImm() && \"getSimm23Lsl2Encoding expects only an immediate\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 1067, __PRETTY_FUNCTION__));
1068 // The immediate is encoded as 'immediate >> 2'.
1069 unsigned Res = static_cast<unsigned>(MO.getImm());
1070 assert((Res & 3) == 0)(((Res & 3) == 0) ? static_cast<void> (0) : __assert_fail
("(Res & 3) == 0", "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn271203/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp"
, 1070, __PRETTY_FUNCTION__));
1071 return Res >> 2;
1072}
1073
1074#include "MipsGenMCCodeEmitter.inc"