Bug Summary

File:lib/Target/Mips/MipsSEISelDAGToDAG.cpp
Warning:line 1125, column 15
1st function call argument is an uninitialized value

Annotated Source Code

1//===-- MipsSEISelDAGToDAG.cpp - A Dag to Dag Inst Selector for MipsSE ----===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Subclass of MipsDAGToDAGISel specialized for mips32/64.
11//
12//===----------------------------------------------------------------------===//
13
14#include "MipsSEISelDAGToDAG.h"
15#include "MCTargetDesc/MipsBaseInfo.h"
16#include "Mips.h"
17#include "MipsAnalyzeImmediate.h"
18#include "MipsMachineFunction.h"
19#include "MipsRegisterInfo.h"
20#include "llvm/CodeGen/MachineConstantPool.h"
21#include "llvm/CodeGen/MachineFrameInfo.h"
22#include "llvm/CodeGen/MachineFunction.h"
23#include "llvm/CodeGen/MachineInstrBuilder.h"
24#include "llvm/CodeGen/MachineRegisterInfo.h"
25#include "llvm/CodeGen/SelectionDAGNodes.h"
26#include "llvm/IR/CFG.h"
27#include "llvm/IR/Dominators.h"
28#include "llvm/IR/GlobalValue.h"
29#include "llvm/IR/Instructions.h"
30#include "llvm/IR/Intrinsics.h"
31#include "llvm/IR/Type.h"
32#include "llvm/Support/Debug.h"
33#include "llvm/Support/ErrorHandling.h"
34#include "llvm/Support/raw_ostream.h"
35#include "llvm/Target/TargetMachine.h"
36using namespace llvm;
37
38#define DEBUG_TYPE"mips-isel" "mips-isel"
39
40bool MipsSEDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
41 Subtarget = &static_cast<const MipsSubtarget &>(MF.getSubtarget());
42 if (Subtarget->inMips16Mode())
43 return false;
44 return MipsDAGToDAGISel::runOnMachineFunction(MF);
45}
46
47void MipsSEDAGToDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
48 AU.addRequired<DominatorTreeWrapperPass>();
49 SelectionDAGISel::getAnalysisUsage(AU);
50}
51
52void MipsSEDAGToDAGISel::addDSPCtrlRegOperands(bool IsDef, MachineInstr &MI,
53 MachineFunction &MF) {
54 MachineInstrBuilder MIB(MF, &MI);
55 unsigned Mask = MI.getOperand(1).getImm();
56 unsigned Flag =
57 IsDef ? RegState::ImplicitDefine : RegState::Implicit | RegState::Undef;
58
59 if (Mask & 1)
60 MIB.addReg(Mips::DSPPos, Flag);
61
62 if (Mask & 2)
63 MIB.addReg(Mips::DSPSCount, Flag);
64
65 if (Mask & 4)
66 MIB.addReg(Mips::DSPCarry, Flag);
67
68 if (Mask & 8)
69 MIB.addReg(Mips::DSPOutFlag, Flag);
70
71 if (Mask & 16)
72 MIB.addReg(Mips::DSPCCond, Flag);
73
74 if (Mask & 32)
75 MIB.addReg(Mips::DSPEFI, Flag);
76}
77
78unsigned MipsSEDAGToDAGISel::getMSACtrlReg(const SDValue RegIdx) const {
79 switch (cast<ConstantSDNode>(RegIdx)->getZExtValue()) {
80 default:
81 llvm_unreachable("Could not map int to register")::llvm::llvm_unreachable_internal("Could not map int to register"
, "/build/llvm-toolchain-snapshot-6.0~svn318882/lib/Target/Mips/MipsSEISelDAGToDAG.cpp"
, 81)
;
82 case 0: return Mips::MSAIR;
83 case 1: return Mips::MSACSR;
84 case 2: return Mips::MSAAccess;
85 case 3: return Mips::MSASave;
86 case 4: return Mips::MSAModify;
87 case 5: return Mips::MSARequest;
88 case 6: return Mips::MSAMap;
89 case 7: return Mips::MSAUnmap;
90 }
91}
92
93bool MipsSEDAGToDAGISel::replaceUsesWithZeroReg(MachineRegisterInfo *MRI,
94 const MachineInstr& MI) {
95 unsigned DstReg = 0, ZeroReg = 0;
96
97 // Check if MI is "addiu $dst, $zero, 0" or "daddiu $dst, $zero, 0".
98 if ((MI.getOpcode() == Mips::ADDiu) &&
99 (MI.getOperand(1).getReg() == Mips::ZERO) &&
100 (MI.getOperand(2).isImm()) &&
101 (MI.getOperand(2).getImm() == 0)) {
102 DstReg = MI.getOperand(0).getReg();
103 ZeroReg = Mips::ZERO;
104 } else if ((MI.getOpcode() == Mips::DADDiu) &&
105 (MI.getOperand(1).getReg() == Mips::ZERO_64) &&
106 (MI.getOperand(2).isImm()) &&
107 (MI.getOperand(2).getImm() == 0)) {
108 DstReg = MI.getOperand(0).getReg();
109 ZeroReg = Mips::ZERO_64;
110 }
111
112 if (!DstReg)
113 return false;
114
115 // Replace uses with ZeroReg.
116 for (MachineRegisterInfo::use_iterator U = MRI->use_begin(DstReg),
117 E = MRI->use_end(); U != E;) {
118 MachineOperand &MO = *U;
119 unsigned OpNo = U.getOperandNo();
120 MachineInstr *MI = MO.getParent();
121 ++U;
122
123 // Do not replace if it is a phi's operand or is tied to def operand.
124 if (MI->isPHI() || MI->isRegTiedToDefOperand(OpNo) || MI->isPseudo())
125 continue;
126
127 // Also, we have to check that the register class of the operand
128 // contains the zero register.
129 if (!MRI->getRegClass(MO.getReg())->contains(ZeroReg))
130 continue;
131
132 MO.setReg(ZeroReg);
133 }
134
135 return true;
136}
137
138void MipsSEDAGToDAGISel::initGlobalBaseReg(MachineFunction &MF) {
139 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
140
141 if (!MipsFI->globalBaseRegSet())
142 return;
143
144 MachineBasicBlock &MBB = MF.front();
145 MachineBasicBlock::iterator I = MBB.begin();
146 MachineRegisterInfo &RegInfo = MF.getRegInfo();
147 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
148 DebugLoc DL;
149 unsigned V0, V1, GlobalBaseReg = MipsFI->getGlobalBaseReg();
150 const TargetRegisterClass *RC;
151 const MipsABIInfo &ABI = static_cast<const MipsTargetMachine &>(TM).getABI();
152 RC = (ABI.IsN64()) ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
153
154 V0 = RegInfo.createVirtualRegister(RC);
155 V1 = RegInfo.createVirtualRegister(RC);
156
157 if (ABI.IsN64()) {
158 MF.getRegInfo().addLiveIn(Mips::T9_64);
159 MBB.addLiveIn(Mips::T9_64);
160
161 // lui $v0, %hi(%neg(%gp_rel(fname)))
162 // daddu $v1, $v0, $t9
163 // daddiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname)))
164 const GlobalValue *FName = MF.getFunction();
165 BuildMI(MBB, I, DL, TII.get(Mips::LUi64), V0)
166 .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_HI);
167 BuildMI(MBB, I, DL, TII.get(Mips::DADDu), V1).addReg(V0)
168 .addReg(Mips::T9_64);
169 BuildMI(MBB, I, DL, TII.get(Mips::DADDiu), GlobalBaseReg).addReg(V1)
170 .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_LO);
171 return;
172 }
173
174 if (!MF.getTarget().isPositionIndependent()) {
175 // Set global register to __gnu_local_gp.
176 //
177 // lui $v0, %hi(__gnu_local_gp)
178 // addiu $globalbasereg, $v0, %lo(__gnu_local_gp)
179 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
180 .addExternalSymbol("__gnu_local_gp", MipsII::MO_ABS_HI);
181 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V0)
182 .addExternalSymbol("__gnu_local_gp", MipsII::MO_ABS_LO);
183 return;
184 }
185
186 MF.getRegInfo().addLiveIn(Mips::T9);
187 MBB.addLiveIn(Mips::T9);
188
189 if (ABI.IsN32()) {
190 // lui $v0, %hi(%neg(%gp_rel(fname)))
191 // addu $v1, $v0, $t9
192 // addiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname)))
193 const GlobalValue *FName = MF.getFunction();
194 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
195 .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_HI);
196 BuildMI(MBB, I, DL, TII.get(Mips::ADDu), V1).addReg(V0).addReg(Mips::T9);
197 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V1)
198 .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_LO);
199 return;
200 }
201
202 assert(ABI.IsO32())(static_cast <bool> (ABI.IsO32()) ? void (0) : __assert_fail
("ABI.IsO32()", "/build/llvm-toolchain-snapshot-6.0~svn318882/lib/Target/Mips/MipsSEISelDAGToDAG.cpp"
, 202, __extension__ __PRETTY_FUNCTION__))
;
203
204 // For O32 ABI, the following instruction sequence is emitted to initialize
205 // the global base register:
206 //
207 // 0. lui $2, %hi(_gp_disp)
208 // 1. addiu $2, $2, %lo(_gp_disp)
209 // 2. addu $globalbasereg, $2, $t9
210 //
211 // We emit only the last instruction here.
212 //
213 // GNU linker requires that the first two instructions appear at the beginning
214 // of a function and no instructions be inserted before or between them.
215 // The two instructions are emitted during lowering to MC layer in order to
216 // avoid any reordering.
217 //
218 // Register $2 (Mips::V0) is added to the list of live-in registers to ensure
219 // the value instruction 1 (addiu) defines is valid when instruction 2 (addu)
220 // reads it.
221 MF.getRegInfo().addLiveIn(Mips::V0);
222 MBB.addLiveIn(Mips::V0);
223 BuildMI(MBB, I, DL, TII.get(Mips::ADDu), GlobalBaseReg)
224 .addReg(Mips::V0).addReg(Mips::T9);
225}
226
227void MipsSEDAGToDAGISel::processFunctionAfterISel(MachineFunction &MF) {
228 initGlobalBaseReg(MF);
229
230 MachineRegisterInfo *MRI = &MF.getRegInfo();
231
232 for (auto &MBB: MF) {
233 for (auto &MI: MBB) {
234 switch (MI.getOpcode()) {
235 case Mips::RDDSP:
236 addDSPCtrlRegOperands(false, MI, MF);
237 break;
238 case Mips::WRDSP:
239 addDSPCtrlRegOperands(true, MI, MF);
240 break;
241 default:
242 replaceUsesWithZeroReg(MRI, MI);
243 }
244 }
245 }
246}
247
248void MipsSEDAGToDAGISel::selectAddE(SDNode *Node, const SDLoc &DL) const {
249 SDValue InFlag = Node->getOperand(2);
250 unsigned Opc = InFlag.getOpcode();
251 SDValue LHS = Node->getOperand(0), RHS = Node->getOperand(1);
252 EVT VT = LHS.getValueType();
253
254 // In the base case, we can rely on the carry bit from the addsc
255 // instruction.
256 if (Opc == ISD::ADDC) {
257 SDValue Ops[3] = {LHS, RHS, InFlag};
258 CurDAG->SelectNodeTo(Node, Mips::ADDWC, VT, MVT::Glue, Ops);
259 return;
260 }
261
262 assert(Opc == ISD::ADDE && "ISD::ADDE not in a chain of ADDE nodes!")(static_cast <bool> (Opc == ISD::ADDE && "ISD::ADDE not in a chain of ADDE nodes!"
) ? void (0) : __assert_fail ("Opc == ISD::ADDE && \"ISD::ADDE not in a chain of ADDE nodes!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318882/lib/Target/Mips/MipsSEISelDAGToDAG.cpp"
, 262, __extension__ __PRETTY_FUNCTION__))
;
263
264 // The more complex case is when there is a chain of ISD::ADDE nodes like:
265 // (adde (adde (adde (addc a b) c) d) e).
266 //
267 // The addwc instruction does not write to the carry bit, instead it writes
268 // to bit 20 of the dsp control register. To match this series of nodes, each
269 // intermediate adde node must be expanded to write the carry bit before the
270 // addition.
271
272 // Start by reading the overflow field for addsc and moving the value to the
273 // carry field. The usage of 1 here with MipsISD::RDDSP / Mips::WRDSP
274 // corresponds to reading/writing the entire control register to/from a GPR.
275
276 SDValue CstOne = CurDAG->getTargetConstant(1, DL, MVT::i32);
277
278 SDValue OuFlag = CurDAG->getTargetConstant(20, DL, MVT::i32);
279
280 SDNode *DSPCtrlField =
281 CurDAG->getMachineNode(Mips::RDDSP, DL, MVT::i32, MVT::Glue, CstOne, InFlag);
282
283 SDNode *Carry = CurDAG->getMachineNode(
284 Mips::EXT, DL, MVT::i32, SDValue(DSPCtrlField, 0), OuFlag, CstOne);
285
286 SDValue Ops[4] = {SDValue(DSPCtrlField, 0),
287 CurDAG->getTargetConstant(6, DL, MVT::i32), CstOne,
288 SDValue(Carry, 0)};
289 SDNode *DSPCFWithCarry = CurDAG->getMachineNode(Mips::INS, DL, MVT::i32, Ops);
290
291 // My reading of the the MIPS DSP 3.01 specification isn't as clear as I
292 // would like about whether bit 20 always gets overwritten by addwc.
293 // Hence take an extremely conservative view and presume it's sticky. We
294 // therefore need to clear it.
295
296 SDValue Zero = CurDAG->getRegister(Mips::ZERO, MVT::i32);
297
298 SDValue InsOps[4] = {Zero, OuFlag, CstOne, SDValue(DSPCFWithCarry, 0)};
299 SDNode *DSPCtrlFinal = CurDAG->getMachineNode(Mips::INS, DL, MVT::i32, InsOps);
300
301 SDNode *WrDSP = CurDAG->getMachineNode(Mips::WRDSP, DL, MVT::Glue,
302 SDValue(DSPCtrlFinal, 0), CstOne);
303
304 SDValue Operands[3] = {LHS, RHS, SDValue(WrDSP, 0)};
305 CurDAG->SelectNodeTo(Node, Mips::ADDWC, VT, MVT::Glue, Operands);
306}
307
308/// Match frameindex
309bool MipsSEDAGToDAGISel::selectAddrFrameIndex(SDValue Addr, SDValue &Base,
310 SDValue &Offset) const {
311 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
312 EVT ValTy = Addr.getValueType();
313
314 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
315 Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), ValTy);
316 return true;
317 }
318 return false;
319}
320
321/// Match frameindex+offset and frameindex|offset
322bool MipsSEDAGToDAGISel::selectAddrFrameIndexOffset(
323 SDValue Addr, SDValue &Base, SDValue &Offset, unsigned OffsetBits,
324 unsigned ShiftAmount = 0) const {
325 if (CurDAG->isBaseWithConstantOffset(Addr)) {
326 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1));
327 if (isIntN(OffsetBits + ShiftAmount, CN->getSExtValue())) {
328 EVT ValTy = Addr.getValueType();
329
330 // If the first operand is a FI, get the TargetFI Node
331 if (FrameIndexSDNode *FIN =
332 dyn_cast<FrameIndexSDNode>(Addr.getOperand(0)))
333 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
334 else {
335 Base = Addr.getOperand(0);
336 // If base is a FI, additional offset calculation is done in
337 // eliminateFrameIndex, otherwise we need to check the alignment
338 if (OffsetToAlignment(CN->getZExtValue(), 1ull << ShiftAmount) != 0)
339 return false;
340 }
341
342 Offset = CurDAG->getTargetConstant(CN->getZExtValue(), SDLoc(Addr),
343 ValTy);
344 return true;
345 }
346 }
347 return false;
348}
349
350/// ComplexPattern used on MipsInstrInfo
351/// Used on Mips Load/Store instructions
352bool MipsSEDAGToDAGISel::selectAddrRegImm(SDValue Addr, SDValue &Base,
353 SDValue &Offset) const {
354 // if Address is FI, get the TargetFrameIndex.
355 if (selectAddrFrameIndex(Addr, Base, Offset))
356 return true;
357
358 // on PIC code Load GA
359 if (Addr.getOpcode() == MipsISD::Wrapper) {
360 Base = Addr.getOperand(0);
361 Offset = Addr.getOperand(1);
362 return true;
363 }
364
365 if (!TM.isPositionIndependent()) {
366 if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
367 Addr.getOpcode() == ISD::TargetGlobalAddress))
368 return false;
369 }
370
371 // Addresses of the form FI+const or FI|const
372 if (selectAddrFrameIndexOffset(Addr, Base, Offset, 16))
373 return true;
374
375 // Operand is a result from an ADD.
376 if (Addr.getOpcode() == ISD::ADD) {
377 // When loading from constant pools, load the lower address part in
378 // the instruction itself. Example, instead of:
379 // lui $2, %hi($CPI1_0)
380 // addiu $2, $2, %lo($CPI1_0)
381 // lwc1 $f0, 0($2)
382 // Generate:
383 // lui $2, %hi($CPI1_0)
384 // lwc1 $f0, %lo($CPI1_0)($2)
385 if (Addr.getOperand(1).getOpcode() == MipsISD::Lo ||
386 Addr.getOperand(1).getOpcode() == MipsISD::GPRel) {
387 SDValue Opnd0 = Addr.getOperand(1).getOperand(0);
388 if (isa<ConstantPoolSDNode>(Opnd0) || isa<GlobalAddressSDNode>(Opnd0) ||
389 isa<JumpTableSDNode>(Opnd0)) {
390 Base = Addr.getOperand(0);
391 Offset = Opnd0;
392 return true;
393 }
394 }
395 }
396
397 return false;
398}
399
400/// ComplexPattern used on MipsInstrInfo
401/// Used on Mips Load/Store instructions
402bool MipsSEDAGToDAGISel::selectAddrDefault(SDValue Addr, SDValue &Base,
403 SDValue &Offset) const {
404 Base = Addr;
405 Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), Addr.getValueType());
406 return true;
407}
408
409bool MipsSEDAGToDAGISel::selectIntAddr(SDValue Addr, SDValue &Base,
410 SDValue &Offset) const {
411 return selectAddrRegImm(Addr, Base, Offset) ||
412 selectAddrDefault(Addr, Base, Offset);
413}
414
415bool MipsSEDAGToDAGISel::selectAddrRegImm9(SDValue Addr, SDValue &Base,
416 SDValue &Offset) const {
417 if (selectAddrFrameIndex(Addr, Base, Offset))
418 return true;
419
420 if (selectAddrFrameIndexOffset(Addr, Base, Offset, 9))
421 return true;
422
423 return false;
424}
425
426/// Used on microMIPS LWC2, LDC2, SWC2 and SDC2 instructions (11-bit offset)
427bool MipsSEDAGToDAGISel::selectAddrRegImm11(SDValue Addr, SDValue &Base,
428 SDValue &Offset) const {
429 if (selectAddrFrameIndex(Addr, Base, Offset))
430 return true;
431
432 if (selectAddrFrameIndexOffset(Addr, Base, Offset, 11))
433 return true;
434
435 return false;
436}
437
438/// Used on microMIPS Load/Store unaligned instructions (12-bit offset)
439bool MipsSEDAGToDAGISel::selectAddrRegImm12(SDValue Addr, SDValue &Base,
440 SDValue &Offset) const {
441 if (selectAddrFrameIndex(Addr, Base, Offset))
442 return true;
443
444 if (selectAddrFrameIndexOffset(Addr, Base, Offset, 12))
445 return true;
446
447 return false;
448}
449
450bool MipsSEDAGToDAGISel::selectAddrRegImm16(SDValue Addr, SDValue &Base,
451 SDValue &Offset) const {
452 if (selectAddrFrameIndex(Addr, Base, Offset))
453 return true;
454
455 if (selectAddrFrameIndexOffset(Addr, Base, Offset, 16))
456 return true;
457
458 return false;
459}
460
461bool MipsSEDAGToDAGISel::selectIntAddr11MM(SDValue Addr, SDValue &Base,
462 SDValue &Offset) const {
463 return selectAddrRegImm11(Addr, Base, Offset) ||
464 selectAddrDefault(Addr, Base, Offset);
465}
466
467bool MipsSEDAGToDAGISel::selectIntAddr12MM(SDValue Addr, SDValue &Base,
468 SDValue &Offset) const {
469 return selectAddrRegImm12(Addr, Base, Offset) ||
470 selectAddrDefault(Addr, Base, Offset);
471}
472
473bool MipsSEDAGToDAGISel::selectIntAddr16MM(SDValue Addr, SDValue &Base,
474 SDValue &Offset) const {
475 return selectAddrRegImm16(Addr, Base, Offset) ||
476 selectAddrDefault(Addr, Base, Offset);
477}
478
479bool MipsSEDAGToDAGISel::selectIntAddrLSL2MM(SDValue Addr, SDValue &Base,
480 SDValue &Offset) const {
481 if (selectAddrFrameIndexOffset(Addr, Base, Offset, 7)) {
482 if (isa<FrameIndexSDNode>(Base))
483 return false;
484
485 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Offset)) {
486 unsigned CnstOff = CN->getZExtValue();
487 return (CnstOff == (CnstOff & 0x3c));
488 }
489
490 return false;
491 }
492
493 // For all other cases where "lw" would be selected, don't select "lw16"
494 // because it would result in additional instructions to prepare operands.
495 if (selectAddrRegImm(Addr, Base, Offset))
496 return false;
497
498 return selectAddrDefault(Addr, Base, Offset);
499}
500
501bool MipsSEDAGToDAGISel::selectIntAddrSImm10(SDValue Addr, SDValue &Base,
502 SDValue &Offset) const {
503
504 if (selectAddrFrameIndex(Addr, Base, Offset))
505 return true;
506
507 if (selectAddrFrameIndexOffset(Addr, Base, Offset, 10))
508 return true;
509
510 return selectAddrDefault(Addr, Base, Offset);
511}
512
513bool MipsSEDAGToDAGISel::selectIntAddrSImm10Lsl1(SDValue Addr, SDValue &Base,
514 SDValue &Offset) const {
515 if (selectAddrFrameIndex(Addr, Base, Offset))
516 return true;
517
518 if (selectAddrFrameIndexOffset(Addr, Base, Offset, 10, 1))
519 return true;
520
521 return selectAddrDefault(Addr, Base, Offset);
522}
523
524bool MipsSEDAGToDAGISel::selectIntAddrSImm10Lsl2(SDValue Addr, SDValue &Base,
525 SDValue &Offset) const {
526 if (selectAddrFrameIndex(Addr, Base, Offset))
527 return true;
528
529 if (selectAddrFrameIndexOffset(Addr, Base, Offset, 10, 2))
530 return true;
531
532 return selectAddrDefault(Addr, Base, Offset);
533}
534
535bool MipsSEDAGToDAGISel::selectIntAddrSImm10Lsl3(SDValue Addr, SDValue &Base,
536 SDValue &Offset) const {
537 if (selectAddrFrameIndex(Addr, Base, Offset))
538 return true;
539
540 if (selectAddrFrameIndexOffset(Addr, Base, Offset, 10, 3))
541 return true;
542
543 return selectAddrDefault(Addr, Base, Offset);
544}
545
546// Select constant vector splats.
547//
548// Returns true and sets Imm if:
549// * MSA is enabled
550// * N is a ISD::BUILD_VECTOR representing a constant splat
551bool MipsSEDAGToDAGISel::selectVSplat(SDNode *N, APInt &Imm,
552 unsigned MinSizeInBits) const {
553 if (!Subtarget->hasMSA())
554 return false;
555
556 BuildVectorSDNode *Node = dyn_cast<BuildVectorSDNode>(N);
557
558 if (!Node)
559 return false;
560
561 APInt SplatValue, SplatUndef;
562 unsigned SplatBitSize;
563 bool HasAnyUndefs;
564
565 if (!Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs,
566 MinSizeInBits, !Subtarget->isLittle()))
567 return false;
568
569 Imm = SplatValue;
570
571 return true;
572}
573
574// Select constant vector splats.
575//
576// In addition to the requirements of selectVSplat(), this function returns
577// true and sets Imm if:
578// * The splat value is the same width as the elements of the vector
579// * The splat value fits in an integer with the specified signed-ness and
580// width.
581//
582// This function looks through ISD::BITCAST nodes.
583// TODO: This might not be appropriate for big-endian MSA since BITCAST is
584// sometimes a shuffle in big-endian mode.
585//
586// It's worth noting that this function is not used as part of the selection
587// of ldi.[bhwd] since it does not permit using the wrong-typed ldi.[bhwd]
588// instruction to achieve the desired bit pattern. ldi.[bhwd] is selected in
589// MipsSEDAGToDAGISel::selectNode.
590bool MipsSEDAGToDAGISel::
591selectVSplatCommon(SDValue N, SDValue &Imm, bool Signed,
592 unsigned ImmBitSize) const {
593 APInt ImmValue;
594 EVT EltTy = N->getValueType(0).getVectorElementType();
595
596 if (N->getOpcode() == ISD::BITCAST)
597 N = N->getOperand(0);
598
599 if (selectVSplat(N.getNode(), ImmValue, EltTy.getSizeInBits()) &&
600 ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
601
602 if (( Signed && ImmValue.isSignedIntN(ImmBitSize)) ||
603 (!Signed && ImmValue.isIntN(ImmBitSize))) {
604 Imm = CurDAG->getTargetConstant(ImmValue, SDLoc(N), EltTy);
605 return true;
606 }
607 }
608
609 return false;
610}
611
612// Select constant vector splats.
613bool MipsSEDAGToDAGISel::
614selectVSplatUimm1(SDValue N, SDValue &Imm) const {
615 return selectVSplatCommon(N, Imm, false, 1);
616}
617
618bool MipsSEDAGToDAGISel::
619selectVSplatUimm2(SDValue N, SDValue &Imm) const {
620 return selectVSplatCommon(N, Imm, false, 2);
621}
622
623bool MipsSEDAGToDAGISel::
624selectVSplatUimm3(SDValue N, SDValue &Imm) const {
625 return selectVSplatCommon(N, Imm, false, 3);
626}
627
628// Select constant vector splats.
629bool MipsSEDAGToDAGISel::
630selectVSplatUimm4(SDValue N, SDValue &Imm) const {
631 return selectVSplatCommon(N, Imm, false, 4);
632}
633
634// Select constant vector splats.
635bool MipsSEDAGToDAGISel::
636selectVSplatUimm5(SDValue N, SDValue &Imm) const {
637 return selectVSplatCommon(N, Imm, false, 5);
638}
639
640// Select constant vector splats.
641bool MipsSEDAGToDAGISel::
642selectVSplatUimm6(SDValue N, SDValue &Imm) const {
643 return selectVSplatCommon(N, Imm, false, 6);
644}
645
646// Select constant vector splats.
647bool MipsSEDAGToDAGISel::
648selectVSplatUimm8(SDValue N, SDValue &Imm) const {
649 return selectVSplatCommon(N, Imm, false, 8);
650}
651
652// Select constant vector splats.
653bool MipsSEDAGToDAGISel::
654selectVSplatSimm5(SDValue N, SDValue &Imm) const {
655 return selectVSplatCommon(N, Imm, true, 5);
656}
657
658// Select constant vector splats whose value is a power of 2.
659//
660// In addition to the requirements of selectVSplat(), this function returns
661// true and sets Imm if:
662// * The splat value is the same width as the elements of the vector
663// * The splat value is a power of two.
664//
665// This function looks through ISD::BITCAST nodes.
666// TODO: This might not be appropriate for big-endian MSA since BITCAST is
667// sometimes a shuffle in big-endian mode.
668bool MipsSEDAGToDAGISel::selectVSplatUimmPow2(SDValue N, SDValue &Imm) const {
669 APInt ImmValue;
670 EVT EltTy = N->getValueType(0).getVectorElementType();
671
672 if (N->getOpcode() == ISD::BITCAST)
673 N = N->getOperand(0);
674
675 if (selectVSplat(N.getNode(), ImmValue, EltTy.getSizeInBits()) &&
676 ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
677 int32_t Log2 = ImmValue.exactLogBase2();
678
679 if (Log2 != -1) {
680 Imm = CurDAG->getTargetConstant(Log2, SDLoc(N), EltTy);
681 return true;
682 }
683 }
684
685 return false;
686}
687
688// Select constant vector splats whose value only has a consecutive sequence
689// of left-most bits set (e.g. 0b11...1100...00).
690//
691// In addition to the requirements of selectVSplat(), this function returns
692// true and sets Imm if:
693// * The splat value is the same width as the elements of the vector
694// * The splat value is a consecutive sequence of left-most bits.
695//
696// This function looks through ISD::BITCAST nodes.
697// TODO: This might not be appropriate for big-endian MSA since BITCAST is
698// sometimes a shuffle in big-endian mode.
699bool MipsSEDAGToDAGISel::selectVSplatMaskL(SDValue N, SDValue &Imm) const {
700 APInt ImmValue;
701 EVT EltTy = N->getValueType(0).getVectorElementType();
702
703 if (N->getOpcode() == ISD::BITCAST)
704 N = N->getOperand(0);
705
706 if (selectVSplat(N.getNode(), ImmValue, EltTy.getSizeInBits()) &&
707 ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
708 // Extract the run of set bits starting with bit zero from the bitwise
709 // inverse of ImmValue, and test that the inverse of this is the same
710 // as the original value.
711 if (ImmValue == ~(~ImmValue & ~(~ImmValue + 1))) {
712
713 Imm = CurDAG->getTargetConstant(ImmValue.countPopulation() - 1, SDLoc(N),
714 EltTy);
715 return true;
716 }
717 }
718
719 return false;
720}
721
722// Select constant vector splats whose value only has a consecutive sequence
723// of right-most bits set (e.g. 0b00...0011...11).
724//
725// In addition to the requirements of selectVSplat(), this function returns
726// true and sets Imm if:
727// * The splat value is the same width as the elements of the vector
728// * The splat value is a consecutive sequence of right-most bits.
729//
730// This function looks through ISD::BITCAST nodes.
731// TODO: This might not be appropriate for big-endian MSA since BITCAST is
732// sometimes a shuffle in big-endian mode.
733bool MipsSEDAGToDAGISel::selectVSplatMaskR(SDValue N, SDValue &Imm) const {
734 APInt ImmValue;
735 EVT EltTy = N->getValueType(0).getVectorElementType();
736
737 if (N->getOpcode() == ISD::BITCAST)
738 N = N->getOperand(0);
739
740 if (selectVSplat(N.getNode(), ImmValue, EltTy.getSizeInBits()) &&
741 ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
742 // Extract the run of set bits starting with bit zero, and test that the
743 // result is the same as the original value
744 if (ImmValue == (ImmValue & ~(ImmValue + 1))) {
745 Imm = CurDAG->getTargetConstant(ImmValue.countPopulation() - 1, SDLoc(N),
746 EltTy);
747 return true;
748 }
749 }
750
751 return false;
752}
753
754bool MipsSEDAGToDAGISel::selectVSplatUimmInvPow2(SDValue N,
755 SDValue &Imm) const {
756 APInt ImmValue;
757 EVT EltTy = N->getValueType(0).getVectorElementType();
758
759 if (N->getOpcode() == ISD::BITCAST)
760 N = N->getOperand(0);
761
762 if (selectVSplat(N.getNode(), ImmValue, EltTy.getSizeInBits()) &&
763 ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
764 int32_t Log2 = (~ImmValue).exactLogBase2();
765
766 if (Log2 != -1) {
767 Imm = CurDAG->getTargetConstant(Log2, SDLoc(N), EltTy);
768 return true;
769 }
770 }
771
772 return false;
773}
774
775bool MipsSEDAGToDAGISel::trySelect(SDNode *Node) {
776 unsigned Opcode = Node->getOpcode();
777 SDLoc DL(Node);
778
779 ///
780 // Instruction Selection not handled by the auto-generated
781 // tablegen selection should be handled here.
782 ///
783 switch(Opcode) {
1
Control jumps to 'case BUILD_VECTOR:' at line 989
784 default: break;
785
786 case ISD::ADDE: {
787 selectAddE(Node, DL);
788 return true;
789 }
790
791 case ISD::ConstantFP: {
792 ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(Node);
793 if (Node->getValueType(0) == MVT::f64 && CN->isExactlyValue(+0.0)) {
794 if (Subtarget->isGP64bit()) {
795 SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
796 Mips::ZERO_64, MVT::i64);
797 ReplaceNode(Node,
798 CurDAG->getMachineNode(Mips::DMTC1, DL, MVT::f64, Zero));
799 } else if (Subtarget->isFP64bit()) {
800 SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
801 Mips::ZERO, MVT::i32);
802 ReplaceNode(Node, CurDAG->getMachineNode(Mips::BuildPairF64_64, DL,
803 MVT::f64, Zero, Zero));
804 } else {
805 SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
806 Mips::ZERO, MVT::i32);
807 ReplaceNode(Node, CurDAG->getMachineNode(Mips::BuildPairF64, DL,
808 MVT::f64, Zero, Zero));
809 }
810 return true;
811 }
812 break;
813 }
814
815 case ISD::Constant: {
816 const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Node);
817 int64_t Imm = CN->getSExtValue();
818 unsigned Size = CN->getValueSizeInBits(0);
819
820 if (isInt<32>(Imm))
821 break;
822
823 MipsAnalyzeImmediate AnalyzeImm;
824
825 const MipsAnalyzeImmediate::InstSeq &Seq =
826 AnalyzeImm.Analyze(Imm, Size, false);
827
828 MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin();
829 SDLoc DL(CN);
830 SDNode *RegOpnd;
831 SDValue ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd),
832 DL, MVT::i64);
833
834 // The first instruction can be a LUi which is different from other
835 // instructions (ADDiu, ORI and SLL) in that it does not have a register
836 // operand.
837 if (Inst->Opc == Mips::LUi64)
838 RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64, ImmOpnd);
839 else
840 RegOpnd =
841 CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64,
842 CurDAG->getRegister(Mips::ZERO_64, MVT::i64),
843 ImmOpnd);
844
845 // The remaining instructions in the sequence are handled here.
846 for (++Inst; Inst != Seq.end(); ++Inst) {
847 ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd), DL,
848 MVT::i64);
849 RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64,
850 SDValue(RegOpnd, 0), ImmOpnd);
851 }
852
853 ReplaceNode(Node, RegOpnd);
854 return true;
855 }
856
857 case ISD::INTRINSIC_W_CHAIN: {
858 switch (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
859 default:
860 break;
861
862 case Intrinsic::mips_cfcmsa: {
863 SDValue ChainIn = Node->getOperand(0);
864 SDValue RegIdx = Node->getOperand(2);
865 SDValue Reg = CurDAG->getCopyFromReg(ChainIn, DL,
866 getMSACtrlReg(RegIdx), MVT::i32);
867 ReplaceNode(Node, Reg.getNode());
868 return true;
869 }
870 }
871 break;
872 }
873
874 case ISD::INTRINSIC_WO_CHAIN: {
875 switch (cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue()) {
876 default:
877 break;
878
879 case Intrinsic::mips_move_v:
880 // Like an assignment but will always produce a move.v even if
881 // unnecessary.
882 ReplaceNode(Node, CurDAG->getMachineNode(Mips::MOVE_V, DL,
883 Node->getValueType(0),
884 Node->getOperand(1)));
885 return true;
886 }
887 break;
888 }
889
890 case ISD::INTRINSIC_VOID: {
891 switch (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
892 default:
893 break;
894
895 case Intrinsic::mips_ctcmsa: {
896 SDValue ChainIn = Node->getOperand(0);
897 SDValue RegIdx = Node->getOperand(2);
898 SDValue Value = Node->getOperand(3);
899 SDValue ChainOut = CurDAG->getCopyToReg(ChainIn, DL,
900 getMSACtrlReg(RegIdx), Value);
901 ReplaceNode(Node, ChainOut.getNode());
902 return true;
903 }
904 }
905 break;
906 }
907
908 // Manually match MipsISD::Ins nodes to get the correct instruction. It has
909 // to be done in this fashion so that we respect the differences between
910 // dins and dinsm, as the difference is that the size operand has the range
911 // 0 < size <= 32 for dins while dinsm has the range 2 <= size <= 64 which
912 // means SelectionDAGISel would have to test all the operands at once to
913 // match the instruction.
914 case MipsISD::Ins: {
915
916 // Sanity checking for the node operands.
917 if (Node->getValueType(0) != MVT::i32 && Node->getValueType(0) != MVT::i64)
918 return false;
919
920 if (Node->getNumOperands() != 4)
921 return false;
922
923 if (Node->getOperand(1)->getOpcode() != ISD::Constant ||
924 Node->getOperand(2)->getOpcode() != ISD::Constant)
925 return false;
926
927 MVT ResTy = Node->getSimpleValueType(0);
928 uint64_t Pos = Node->getConstantOperandVal(1);
929 uint64_t Size = Node->getConstantOperandVal(2);
930
931 // Size has to be >0 for 'ins', 'dins' and 'dinsu'.
932 if (!Size)
933 return false;
934
935 if (Pos + Size > 64)
936 return false;
937
938 if (ResTy != MVT::i32 && ResTy != MVT::i64)
939 return false;
940
941 unsigned Opcode = 0;
942 if (ResTy == MVT::i32) {
943 if (Pos + Size <= 32)
944 Opcode = Mips::INS;
945 } else {
946 if (Pos + Size <= 32)
947 Opcode = Mips::DINS;
948 else if (Pos < 32 && 1 < Size)
949 Opcode = Mips::DINSM;
950 else
951 Opcode = Mips::DINSU;
952 }
953
954 if (Opcode) {
955 SDValue Ops[4] = {
956 Node->getOperand(0), CurDAG->getTargetConstant(Pos, DL, MVT::i32),
957 CurDAG->getTargetConstant(Size, DL, MVT::i32), Node->getOperand(3)};
958
959 ReplaceNode(Node, CurDAG->getMachineNode(Opcode, DL, ResTy, Ops));
960 return true;
961 }
962
963 return false;
964 }
965
966 case MipsISD::ThreadPointer: {
967 EVT PtrVT = getTargetLowering()->getPointerTy(CurDAG->getDataLayout());
968 unsigned RdhwrOpc, DestReg;
969
970 if (PtrVT == MVT::i32) {
971 RdhwrOpc = Mips::RDHWR;
972 DestReg = Mips::V1;
973 } else {
974 RdhwrOpc = Mips::RDHWR64;
975 DestReg = Mips::V1_64;
976 }
977
978 SDNode *Rdhwr =
979 CurDAG->getMachineNode(RdhwrOpc, DL,
980 Node->getValueType(0),
981 CurDAG->getRegister(Mips::HWR29, MVT::i32));
982 SDValue Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), DL, DestReg,
983 SDValue(Rdhwr, 0));
984 SDValue ResNode = CurDAG->getCopyFromReg(Chain, DL, DestReg, PtrVT);
985 ReplaceNode(Node, ResNode.getNode());
986 return true;
987 }
988
989 case ISD::BUILD_VECTOR: {
990 // Select appropriate ldi.[bhwd] instructions for constant splats of
991 // 128-bit when MSA is enabled. Fixup any register class mismatches that
992 // occur as a result.
993 //
994 // This allows the compiler to use a wider range of immediates than would
995 // otherwise be allowed. If, for example, v4i32 could only use ldi.h then
996 // it would not be possible to load { 0x01010101, 0x01010101, 0x01010101,
997 // 0x01010101 } without using a constant pool. This would be sub-optimal
998 // when // 'ldi.b wd, 1' is capable of producing that bit-pattern in the
999 // same set/ of registers. Similarly, ldi.h isn't capable of producing {
1000 // 0x00000000, 0x00000001, 0x00000000, 0x00000001 } but 'ldi.d wd, 1' can.
1001
1002 const MipsABIInfo &ABI =
1003 static_cast<const MipsTargetMachine &>(TM).getABI();
1004
1005 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Node);
1006 APInt SplatValue, SplatUndef;
1007 unsigned SplatBitSize;
1008 bool HasAnyUndefs;
1009 unsigned LdiOp;
1010 EVT ResVecTy = BVN->getValueType(0);
1011 EVT ViaVecTy;
1012
1013 if (!Subtarget->hasMSA() || !BVN->getValueType(0).is128BitVector())
2
Assuming the condition is false
3
Assuming the condition is false
4
Taking false branch
1014 return false;
1015
1016 if (!BVN->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
6
Assuming the condition is false
7
Taking false branch
1017 HasAnyUndefs, 8,
1018 !Subtarget->isLittle()))
5
Assuming the condition is false
1019 return false;
1020
1021 switch (SplatBitSize) {
8
Control jumps to 'case 64:' at line 1036
1022 default:
1023 return false;
1024 case 8:
1025 LdiOp = Mips::LDI_B;
1026 ViaVecTy = MVT::v16i8;
1027 break;
1028 case 16:
1029 LdiOp = Mips::LDI_H;
1030 ViaVecTy = MVT::v8i16;
1031 break;
1032 case 32:
1033 LdiOp = Mips::LDI_W;
1034 ViaVecTy = MVT::v4i32;
1035 break;
1036 case 64:
1037 LdiOp = Mips::LDI_D;
1038 ViaVecTy = MVT::v2i64;
1039 break;
9
Execution continues on line 1042
1040 }
1041
1042 SDNode *Res;
10
'Res' declared without an initial value
1043
1044 // If we have a signed 10 bit integer, we can splat it directly.
1045 //
1046 // If we have something bigger we can synthesize the value into a GPR and
1047 // splat from there.
1048 if (SplatValue.isSignedIntN(10)) {
11
Taking false branch
1049 SDValue Imm = CurDAG->getTargetConstant(SplatValue, DL,
1050 ViaVecTy.getVectorElementType());
1051
1052 Res = CurDAG->getMachineNode(LdiOp, DL, ViaVecTy, Imm);
1053 } else if (SplatValue.isSignedIntN(16) &&
1054 ((ABI.IsO32() && SplatBitSize < 64) ||
1055 (ABI.IsN32() || ABI.IsN64()))) {
1056 // Only handle signed 16 bit values when the element size is GPR width.
1057 // MIPS64 can handle all the cases but MIPS32 would need to handle
1058 // negative cases specifically here. Instead, handle those cases as
1059 // 64bit values.
1060
1061 bool Is32BitSplat = ABI.IsO32() || SplatBitSize < 64;
1062 const unsigned ADDiuOp = Is32BitSplat ? Mips::ADDiu : Mips::DADDiu;
1063 const MVT SplatMVT = Is32BitSplat ? MVT::i32 : MVT::i64;
1064 SDValue ZeroVal = CurDAG->getRegister(
1065 Is32BitSplat ? Mips::ZERO : Mips::ZERO_64, SplatMVT);
1066
1067 const unsigned FILLOp =
1068 SplatBitSize == 16
1069 ? Mips::FILL_H
1070 : (SplatBitSize == 32 ? Mips::FILL_W
1071 : (SplatBitSize == 64 ? Mips::FILL_D : 0));
1072
1073 assert(FILLOp != 0 && "Unknown FILL Op for splat synthesis!")(static_cast <bool> (FILLOp != 0 && "Unknown FILL Op for splat synthesis!"
) ? void (0) : __assert_fail ("FILLOp != 0 && \"Unknown FILL Op for splat synthesis!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318882/lib/Target/Mips/MipsSEISelDAGToDAG.cpp"
, 1073, __extension__ __PRETTY_FUNCTION__))
;
1074 assert((!ABI.IsO32() || (FILLOp != Mips::FILL_D)) &&(static_cast <bool> ((!ABI.IsO32() || (FILLOp != Mips::
FILL_D)) && "Attempting to use fill.d on MIPS32!") ? void
(0) : __assert_fail ("(!ABI.IsO32() || (FILLOp != Mips::FILL_D)) && \"Attempting to use fill.d on MIPS32!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318882/lib/Target/Mips/MipsSEISelDAGToDAG.cpp"
, 1075, __extension__ __PRETTY_FUNCTION__))
1075 "Attempting to use fill.d on MIPS32!")(static_cast <bool> ((!ABI.IsO32() || (FILLOp != Mips::
FILL_D)) && "Attempting to use fill.d on MIPS32!") ? void
(0) : __assert_fail ("(!ABI.IsO32() || (FILLOp != Mips::FILL_D)) && \"Attempting to use fill.d on MIPS32!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318882/lib/Target/Mips/MipsSEISelDAGToDAG.cpp"
, 1075, __extension__ __PRETTY_FUNCTION__))
;
1076
1077 const unsigned Lo = SplatValue.getLoBits(16).getZExtValue();
1078 SDValue LoVal = CurDAG->getTargetConstant(Lo, DL, SplatMVT);
1079
1080 Res = CurDAG->getMachineNode(ADDiuOp, DL, SplatMVT, ZeroVal, LoVal);
1081 Res = CurDAG->getMachineNode(FILLOp, DL, ViaVecTy, SDValue(Res, 0));
1082
1083 } else if (SplatValue.isSignedIntN(32) && SplatBitSize == 32) {
1084 // Only handle the cases where the splat size agrees with the size
1085 // of the SplatValue here.
1086 const unsigned Lo = SplatValue.getLoBits(16).getZExtValue();
1087 const unsigned Hi = SplatValue.lshr(16).getLoBits(16).getZExtValue();
1088 SDValue ZeroVal = CurDAG->getRegister(Mips::ZERO, MVT::i32);
1089
1090 SDValue LoVal = CurDAG->getTargetConstant(Lo, DL, MVT::i32);
1091 SDValue HiVal = CurDAG->getTargetConstant(Hi, DL, MVT::i32);
1092
1093 if (Hi)
1094 Res = CurDAG->getMachineNode(Mips::LUi, DL, MVT::i32, HiVal);
1095
1096 if (Lo)
1097 Res = CurDAG->getMachineNode(Mips::ORi, DL, MVT::i32,
1098 Hi ? SDValue(Res, 0) : ZeroVal, LoVal);
1099
1100 assert((Hi || Lo) && "Zero case reached 32 bit case splat synthesis!")(static_cast <bool> ((Hi || Lo) && "Zero case reached 32 bit case splat synthesis!"
) ? void (0) : __assert_fail ("(Hi || Lo) && \"Zero case reached 32 bit case splat synthesis!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318882/lib/Target/Mips/MipsSEISelDAGToDAG.cpp"
, 1100, __extension__ __PRETTY_FUNCTION__))
;
1101 Res = CurDAG->getMachineNode(Mips::FILL_W, DL, MVT::v4i32, SDValue(Res, 0));
1102
1103 } else if (SplatValue.isSignedIntN(32) && SplatBitSize == 64 &&
1104 (ABI.IsN32() || ABI.IsN64())) {
1105 // N32 and N64 can perform some tricks that O32 can't for signed 32 bit
1106 // integers due to having 64bit registers. lui will cause the necessary
1107 // zero/sign extension.
1108 const unsigned Lo = SplatValue.getLoBits(16).getZExtValue();
1109 const unsigned Hi = SplatValue.lshr(16).getLoBits(16).getZExtValue();
1110 SDValue ZeroVal = CurDAG->getRegister(Mips::ZERO, MVT::i32);
1111
1112 SDValue LoVal = CurDAG->getTargetConstant(Lo, DL, MVT::i32);
1113 SDValue HiVal = CurDAG->getTargetConstant(Hi, DL, MVT::i32);
1114
1115 if (Hi)
12
Assuming 'Hi' is 0
13
Taking false branch
1116 Res = CurDAG->getMachineNode(Mips::LUi, DL, MVT::i32, HiVal);
1117
1118 if (Lo)
14
Assuming 'Lo' is 0
15
Taking false branch
1119 Res = CurDAG->getMachineNode(Mips::ORi, DL, MVT::i32,
1120 Hi ? SDValue(Res, 0) : ZeroVal, LoVal);
1121
1122 Res = CurDAG->getMachineNode(
1123 Mips::SUBREG_TO_REG, DL, MVT::i64,
1124 CurDAG->getTargetConstant(((Hi >> 15) & 0x1), DL, MVT::i64),
1125 SDValue(Res, 0),
16
1st function call argument is an uninitialized value
1126 CurDAG->getTargetConstant(Mips::sub_32, DL, MVT::i64));
1127
1128 Res =
1129 CurDAG->getMachineNode(Mips::FILL_D, DL, MVT::v2i64, SDValue(Res, 0));
1130
1131 } else if (SplatValue.isSignedIntN(64)) {
1132 // If we have a 64 bit Splat value, we perform a similar sequence to the
1133 // above:
1134 //
1135 // MIPS32: MIPS64:
1136 // lui $res, %highest(val) lui $res, %highest(val)
1137 // ori $res, $res, %higher(val) ori $res, $res, %higher(val)
1138 // lui $res2, %hi(val) lui $res2, %hi(val)
1139 // ori $res2, %res2, %lo(val) ori $res2, %res2, %lo(val)
1140 // $res3 = fill $res2 dinsu $res, $res2, 0, 32
1141 // $res4 = insert.w $res3[1], $res fill.d $res
1142 // splat.d $res4, 0
1143 //
1144 // The ability to use dinsu is guaranteed as MSA requires MIPSR5. This saves
1145 // having to materialize the value by shifts and ors.
1146 //
1147 // FIXME: Implement the preferred sequence for MIPS64R6:
1148 //
1149 // MIPS64R6:
1150 // ori $res, $zero, %lo(val)
1151 // daui $res, $res, %hi(val)
1152 // dahi $res, $res, %higher(val)
1153 // dati $res, $res, %highest(cal)
1154 // fill.d $res
1155 //
1156
1157 const unsigned Lo = SplatValue.getLoBits(16).getZExtValue();
1158 const unsigned Hi = SplatValue.lshr(16).getLoBits(16).getZExtValue();
1159 const unsigned Higher = SplatValue.lshr(32).getLoBits(16).getZExtValue();
1160 const unsigned Highest = SplatValue.lshr(48).getLoBits(16).getZExtValue();
1161
1162 SDValue LoVal = CurDAG->getTargetConstant(Lo, DL, MVT::i32);
1163 SDValue HiVal = CurDAG->getTargetConstant(Hi, DL, MVT::i32);
1164 SDValue HigherVal = CurDAG->getTargetConstant(Higher, DL, MVT::i32);
1165 SDValue HighestVal = CurDAG->getTargetConstant(Highest, DL, MVT::i32);
1166 SDValue ZeroVal = CurDAG->getRegister(Mips::ZERO, MVT::i32);
1167
1168 // Independent of whether we're targeting MIPS64 or not, the basic
1169 // operations are the same. Also, directly use the $zero register if
1170 // the 16 bit chunk is zero.
1171 //
1172 // For optimization purposes we always synthesize the splat value as
1173 // an i32 value, then if we're targetting MIPS64, use SUBREG_TO_REG
1174 // just before combining the values with dinsu to produce an i64. This
1175 // enables SelectionDAG to aggressively share components of splat values
1176 // where possible.
1177 //
1178 // FIXME: This is the general constant synthesis problem. This code
1179 // should be factored out into a class shared between all the
1180 // classes that need it. Specifically, for a splat size of 64
1181 // bits that's a negative number we can do better than LUi/ORi
1182 // for the upper 32bits.
1183
1184 if (Hi)
1185 Res = CurDAG->getMachineNode(Mips::LUi, DL, MVT::i32, HiVal);
1186
1187 if (Lo)
1188 Res = CurDAG->getMachineNode(Mips::ORi, DL, MVT::i32,
1189 Hi ? SDValue(Res, 0) : ZeroVal, LoVal);
1190
1191 SDNode *HiRes;
1192 if (Highest)
1193 HiRes = CurDAG->getMachineNode(Mips::LUi, DL, MVT::i32, HighestVal);
1194
1195 if (Higher)
1196 HiRes = CurDAG->getMachineNode(Mips::ORi, DL, MVT::i32,
1197 Highest ? SDValue(HiRes, 0) : ZeroVal,
1198 HigherVal);
1199
1200
1201 if (ABI.IsO32()) {
1202 Res = CurDAG->getMachineNode(Mips::FILL_W, DL, MVT::v4i32,
1203 (Hi || Lo) ? SDValue(Res, 0) : ZeroVal);
1204
1205 Res = CurDAG->getMachineNode(
1206 Mips::INSERT_W, DL, MVT::v4i32, SDValue(Res, 0),
1207 (Highest || Higher) ? SDValue(HiRes, 0) : ZeroVal,
1208 CurDAG->getTargetConstant(1, DL, MVT::i32));
1209
1210 const TargetLowering *TLI = getTargetLowering();
1211 const TargetRegisterClass *RC =
1212 TLI->getRegClassFor(ViaVecTy.getSimpleVT());
1213
1214 Res = CurDAG->getMachineNode(
1215 Mips::COPY_TO_REGCLASS, DL, ViaVecTy, SDValue(Res, 0),
1216 CurDAG->getTargetConstant(RC->getID(), DL, MVT::i32));
1217
1218 Res = CurDAG->getMachineNode(
1219 Mips::SPLATI_D, DL, MVT::v2i64, SDValue(Res, 0),
1220 CurDAG->getTargetConstant(0, DL, MVT::i32));
1221 } else if (ABI.IsN64() || ABI.IsN32()) {
1222
1223 SDValue Zero64Val = CurDAG->getRegister(Mips::ZERO_64, MVT::i64);
1224 const bool HiResNonZero = Highest || Higher;
1225 const bool ResNonZero = Hi || Lo;
1226
1227 if (HiResNonZero)
1228 HiRes = CurDAG->getMachineNode(
1229 Mips::SUBREG_TO_REG, DL, MVT::i64,
1230 CurDAG->getTargetConstant(((Highest >> 15) & 0x1), DL, MVT::i64),
1231 SDValue(HiRes, 0),
1232 CurDAG->getTargetConstant(Mips::sub_32, DL, MVT::i64));
1233
1234 if (ResNonZero)
1235 Res = CurDAG->getMachineNode(
1236 Mips::SUBREG_TO_REG, DL, MVT::i64,
1237 CurDAG->getTargetConstant(((Hi >> 15) & 0x1), DL, MVT::i64),
1238 SDValue(Res, 0),
1239 CurDAG->getTargetConstant(Mips::sub_32, DL, MVT::i64));
1240
1241 // We have 3 cases:
1242 // The HiRes is nonzero but Res is $zero => dsll32 HiRes, 0
1243 // The Res is nonzero but HiRes is $zero => dinsu Res, $zero, 32, 32
1244 // Both are non zero => dinsu Res, HiRes, 32, 32
1245 //
1246 // The obvious "missing" case is when both are zero, but that case is
1247 // handled by the ldi case.
1248 if (ResNonZero) {
1249 IntegerType *Int32Ty =
1250 IntegerType::get(MF->getFunction()->getContext(), 32);
1251 const ConstantInt *Const32 = ConstantInt::get(Int32Ty, 32);
1252 SDValue Ops[4] = {HiResNonZero ? SDValue(HiRes, 0) : Zero64Val,
1253 CurDAG->getConstant(*Const32, DL, MVT::i32),
1254 CurDAG->getConstant(*Const32, DL, MVT::i32),
1255 SDValue(Res, 0)};
1256
1257 Res = CurDAG->getMachineNode(Mips::DINSU, DL, MVT::i64, Ops);
1258 } else if (HiResNonZero) {
1259 Res = CurDAG->getMachineNode(
1260 Mips::DSLL32, DL, MVT::i64, SDValue(HiRes, 0),
1261 CurDAG->getTargetConstant(0, DL, MVT::i32));
1262 } else
1263 llvm_unreachable(::llvm::llvm_unreachable_internal("Zero splat value handled by non-zero 64bit splat synthesis!"
, "/build/llvm-toolchain-snapshot-6.0~svn318882/lib/Target/Mips/MipsSEISelDAGToDAG.cpp"
, 1264)
1264 "Zero splat value handled by non-zero 64bit splat synthesis!")::llvm::llvm_unreachable_internal("Zero splat value handled by non-zero 64bit splat synthesis!"
, "/build/llvm-toolchain-snapshot-6.0~svn318882/lib/Target/Mips/MipsSEISelDAGToDAG.cpp"
, 1264)
;
1265
1266 Res = CurDAG->getMachineNode(Mips::FILL_D, DL, MVT::v2i64, SDValue(Res, 0));
1267 } else
1268 llvm_unreachable("Unknown ABI in MipsISelDAGToDAG!")::llvm::llvm_unreachable_internal("Unknown ABI in MipsISelDAGToDAG!"
, "/build/llvm-toolchain-snapshot-6.0~svn318882/lib/Target/Mips/MipsSEISelDAGToDAG.cpp"
, 1268)
;
1269
1270 } else
1271 return false;
1272
1273 if (ResVecTy != ViaVecTy) {
1274 // If LdiOp is writing to a different register class to ResVecTy, then
1275 // fix it up here. This COPY_TO_REGCLASS should never cause a move.v
1276 // since the source and destination register sets contain the same
1277 // registers.
1278 const TargetLowering *TLI = getTargetLowering();
1279 MVT ResVecTySimple = ResVecTy.getSimpleVT();
1280 const TargetRegisterClass *RC = TLI->getRegClassFor(ResVecTySimple);
1281 Res = CurDAG->getMachineNode(Mips::COPY_TO_REGCLASS, DL,
1282 ResVecTy, SDValue(Res, 0),
1283 CurDAG->getTargetConstant(RC->getID(), DL,
1284 MVT::i32));
1285 }
1286
1287 ReplaceNode(Node, Res);
1288 return true;
1289 }
1290
1291 }
1292
1293 return false;
1294}
1295
1296bool MipsSEDAGToDAGISel::
1297SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
1298 std::vector<SDValue> &OutOps) {
1299 SDValue Base, Offset;
1300
1301 switch(ConstraintID) {
1302 default:
1303 llvm_unreachable("Unexpected asm memory constraint")::llvm::llvm_unreachable_internal("Unexpected asm memory constraint"
, "/build/llvm-toolchain-snapshot-6.0~svn318882/lib/Target/Mips/MipsSEISelDAGToDAG.cpp"
, 1303)
;
1304 // All memory constraints can at least accept raw pointers.
1305 case InlineAsm::Constraint_i:
1306 OutOps.push_back(Op);
1307 OutOps.push_back(CurDAG->getTargetConstant(0, SDLoc(Op), MVT::i32));
1308 return false;
1309 case InlineAsm::Constraint_m:
1310 if (selectAddrRegImm16(Op, Base, Offset)) {
1311 OutOps.push_back(Base);
1312 OutOps.push_back(Offset);
1313 return false;
1314 }
1315 OutOps.push_back(Op);
1316 OutOps.push_back(CurDAG->getTargetConstant(0, SDLoc(Op), MVT::i32));
1317 return false;
1318 case InlineAsm::Constraint_R:
1319 // The 'R' constraint is supposed to be much more complicated than this.
1320 // However, it's becoming less useful due to architectural changes and
1321 // ought to be replaced by other constraints such as 'ZC'.
1322 // For now, support 9-bit signed offsets which is supportable by all
1323 // subtargets for all instructions.
1324 if (selectAddrRegImm9(Op, Base, Offset)) {
1325 OutOps.push_back(Base);
1326 OutOps.push_back(Offset);
1327 return false;
1328 }
1329 OutOps.push_back(Op);
1330 OutOps.push_back(CurDAG->getTargetConstant(0, SDLoc(Op), MVT::i32));
1331 return false;
1332 case InlineAsm::Constraint_ZC:
1333 // ZC matches whatever the pref, ll, and sc instructions can handle for the
1334 // given subtarget.
1335 if (Subtarget->inMicroMipsMode()) {
1336 // On microMIPS, they can handle 12-bit offsets.
1337 if (selectAddrRegImm12(Op, Base, Offset)) {
1338 OutOps.push_back(Base);
1339 OutOps.push_back(Offset);
1340 return false;
1341 }
1342 } else if (Subtarget->hasMips32r6()) {
1343 // On MIPS32r6/MIPS64r6, they can only handle 9-bit offsets.
1344 if (selectAddrRegImm9(Op, Base, Offset)) {
1345 OutOps.push_back(Base);
1346 OutOps.push_back(Offset);
1347 return false;
1348 }
1349 } else if (selectAddrRegImm16(Op, Base, Offset)) {
1350 // Prior to MIPS32r6/MIPS64r6, they can handle 16-bit offsets.
1351 OutOps.push_back(Base);
1352 OutOps.push_back(Offset);
1353 return false;
1354 }
1355 // In all cases, 0-bit offsets are acceptable.
1356 OutOps.push_back(Op);
1357 OutOps.push_back(CurDAG->getTargetConstant(0, SDLoc(Op), MVT::i32));
1358 return false;
1359 }
1360 return true;
1361}
1362
1363FunctionPass *llvm::createMipsSEISelDag(MipsTargetMachine &TM,
1364 CodeGenOpt::Level OptLevel) {
1365 return new MipsSEDAGToDAGISel(TM, OptLevel);
1366}