Bug Summary

File:lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
Location:line 4842, column 57
Description:The result of the '>>' expression is undefined

Annotated Source Code

1//===-- NVPTXISelDAGToDAG.cpp - A dag to dag inst selector for NVPTX ------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines an instruction selector for the NVPTX target.
11//
12//===----------------------------------------------------------------------===//
13
14#include "NVPTXISelDAGToDAG.h"
15#include "llvm/IR/GlobalValue.h"
16#include "llvm/IR/Instructions.h"
17#include "llvm/Support/CommandLine.h"
18#include "llvm/Support/Debug.h"
19#include "llvm/Support/ErrorHandling.h"
20#include "llvm/Support/raw_ostream.h"
21#include "llvm/Target/TargetIntrinsicInfo.h"
22
23using namespace llvm;
24
25#define DEBUG_TYPE"nvptx-isel" "nvptx-isel"
26
27static cl::opt<int> UsePrecDivF32(
28 "nvptx-prec-divf32", cl::ZeroOrMore, cl::Hidden,
29 cl::desc("NVPTX Specifies: 0 use div.approx, 1 use div.full, 2 use"
30 " IEEE Compliant F32 div.rnd if available."),
31 cl::init(2));
32
33static cl::opt<bool>
34UsePrecSqrtF32("nvptx-prec-sqrtf32", cl::Hidden,
35 cl::desc("NVPTX Specific: 0 use sqrt.approx, 1 use sqrt.rn."),
36 cl::init(true));
37
38static cl::opt<bool>
39FtzEnabled("nvptx-f32ftz", cl::ZeroOrMore, cl::Hidden,
40 cl::desc("NVPTX Specific: Flush f32 subnormals to sign-preserving zero."),
41 cl::init(false));
42
43
44/// createNVPTXISelDag - This pass converts a legalized DAG into a
45/// NVPTX-specific DAG, ready for instruction scheduling.
46FunctionPass *llvm::createNVPTXISelDag(NVPTXTargetMachine &TM,
47 llvm::CodeGenOpt::Level OptLevel) {
48 return new NVPTXDAGToDAGISel(TM, OptLevel);
49}
50
51NVPTXDAGToDAGISel::NVPTXDAGToDAGISel(NVPTXTargetMachine &tm,
52 CodeGenOpt::Level OptLevel)
53 : SelectionDAGISel(tm, OptLevel),
54 Subtarget(tm.getSubtarget<NVPTXSubtarget>()) {
55 doMulWide = (OptLevel > 0);
56}
57
58int NVPTXDAGToDAGISel::getDivF32Level() const {
59 if (UsePrecDivF32.getNumOccurrences() > 0) {
60 // If nvptx-prec-div32=N is used on the command-line, always honor it
61 return UsePrecDivF32;
62 } else {
63 // Otherwise, use div.approx if fast math is enabled
64 if (TM.Options.UnsafeFPMath)
65 return 0;
66 else
67 return 2;
68 }
69}
70
71bool NVPTXDAGToDAGISel::usePrecSqrtF32() const {
72 if (UsePrecSqrtF32.getNumOccurrences() > 0) {
73 // If nvptx-prec-sqrtf32 is used on the command-line, always honor it
74 return UsePrecSqrtF32;
75 } else {
76 // Otherwise, use sqrt.approx if fast math is enabled
77 if (TM.Options.UnsafeFPMath)
78 return false;
79 else
80 return true;
81 }
82}
83
84bool NVPTXDAGToDAGISel::useF32FTZ() const {
85 if (FtzEnabled.getNumOccurrences() > 0) {
86 // If nvptx-f32ftz is used on the command-line, always honor it
87 return FtzEnabled;
88 } else {
89 const Function *F = MF->getFunction();
90 // Otherwise, check for an nvptx-f32ftz attribute on the function
91 if (F->hasFnAttribute("nvptx-f32ftz"))
92 return (F->getAttributes().getAttribute(AttributeSet::FunctionIndex,
93 "nvptx-f32ftz")
94 .getValueAsString() == "true");
95 else
96 return false;
97 }
98}
99
100bool NVPTXDAGToDAGISel::allowFMA() const {
101 const NVPTXTargetLowering *TL = Subtarget.getTargetLowering();
102 return TL->allowFMA(*MF, OptLevel);
103}
104
105/// Select - Select instructions not customized! Used for
106/// expanded, promoted and normal instructions.
107SDNode *NVPTXDAGToDAGISel::Select(SDNode *N) {
108
109 if (N->isMachineOpcode()) {
110 N->setNodeId(-1);
111 return nullptr; // Already selected.
112 }
113
114 SDNode *ResNode = nullptr;
115 switch (N->getOpcode()) {
116 case ISD::LOAD:
117 ResNode = SelectLoad(N);
118 break;
119 case ISD::STORE:
120 ResNode = SelectStore(N);
121 break;
122 case NVPTXISD::LoadV2:
123 case NVPTXISD::LoadV4:
124 ResNode = SelectLoadVector(N);
125 break;
126 case NVPTXISD::LDGV2:
127 case NVPTXISD::LDGV4:
128 case NVPTXISD::LDUV2:
129 case NVPTXISD::LDUV4:
130 ResNode = SelectLDGLDU(N);
131 break;
132 case NVPTXISD::StoreV2:
133 case NVPTXISD::StoreV4:
134 ResNode = SelectStoreVector(N);
135 break;
136 case NVPTXISD::LoadParam:
137 case NVPTXISD::LoadParamV2:
138 case NVPTXISD::LoadParamV4:
139 ResNode = SelectLoadParam(N);
140 break;
141 case NVPTXISD::StoreRetval:
142 case NVPTXISD::StoreRetvalV2:
143 case NVPTXISD::StoreRetvalV4:
144 ResNode = SelectStoreRetval(N);
145 break;
146 case NVPTXISD::StoreParam:
147 case NVPTXISD::StoreParamV2:
148 case NVPTXISD::StoreParamV4:
149 case NVPTXISD::StoreParamS32:
150 case NVPTXISD::StoreParamU32:
151 ResNode = SelectStoreParam(N);
152 break;
153 case ISD::INTRINSIC_WO_CHAIN:
154 ResNode = SelectIntrinsicNoChain(N);
155 break;
156 case ISD::INTRINSIC_W_CHAIN:
157 ResNode = SelectIntrinsicChain(N);
158 break;
159 case NVPTXISD::Tex1DFloatS32:
160 case NVPTXISD::Tex1DFloatFloat:
161 case NVPTXISD::Tex1DFloatFloatLevel:
162 case NVPTXISD::Tex1DFloatFloatGrad:
163 case NVPTXISD::Tex1DS32S32:
164 case NVPTXISD::Tex1DS32Float:
165 case NVPTXISD::Tex1DS32FloatLevel:
166 case NVPTXISD::Tex1DS32FloatGrad:
167 case NVPTXISD::Tex1DU32S32:
168 case NVPTXISD::Tex1DU32Float:
169 case NVPTXISD::Tex1DU32FloatLevel:
170 case NVPTXISD::Tex1DU32FloatGrad:
171 case NVPTXISD::Tex1DArrayFloatS32:
172 case NVPTXISD::Tex1DArrayFloatFloat:
173 case NVPTXISD::Tex1DArrayFloatFloatLevel:
174 case NVPTXISD::Tex1DArrayFloatFloatGrad:
175 case NVPTXISD::Tex1DArrayS32S32:
176 case NVPTXISD::Tex1DArrayS32Float:
177 case NVPTXISD::Tex1DArrayS32FloatLevel:
178 case NVPTXISD::Tex1DArrayS32FloatGrad:
179 case NVPTXISD::Tex1DArrayU32S32:
180 case NVPTXISD::Tex1DArrayU32Float:
181 case NVPTXISD::Tex1DArrayU32FloatLevel:
182 case NVPTXISD::Tex1DArrayU32FloatGrad:
183 case NVPTXISD::Tex2DFloatS32:
184 case NVPTXISD::Tex2DFloatFloat:
185 case NVPTXISD::Tex2DFloatFloatLevel:
186 case NVPTXISD::Tex2DFloatFloatGrad:
187 case NVPTXISD::Tex2DS32S32:
188 case NVPTXISD::Tex2DS32Float:
189 case NVPTXISD::Tex2DS32FloatLevel:
190 case NVPTXISD::Tex2DS32FloatGrad:
191 case NVPTXISD::Tex2DU32S32:
192 case NVPTXISD::Tex2DU32Float:
193 case NVPTXISD::Tex2DU32FloatLevel:
194 case NVPTXISD::Tex2DU32FloatGrad:
195 case NVPTXISD::Tex2DArrayFloatS32:
196 case NVPTXISD::Tex2DArrayFloatFloat:
197 case NVPTXISD::Tex2DArrayFloatFloatLevel:
198 case NVPTXISD::Tex2DArrayFloatFloatGrad:
199 case NVPTXISD::Tex2DArrayS32S32:
200 case NVPTXISD::Tex2DArrayS32Float:
201 case NVPTXISD::Tex2DArrayS32FloatLevel:
202 case NVPTXISD::Tex2DArrayS32FloatGrad:
203 case NVPTXISD::Tex2DArrayU32S32:
204 case NVPTXISD::Tex2DArrayU32Float:
205 case NVPTXISD::Tex2DArrayU32FloatLevel:
206 case NVPTXISD::Tex2DArrayU32FloatGrad:
207 case NVPTXISD::Tex3DFloatS32:
208 case NVPTXISD::Tex3DFloatFloat:
209 case NVPTXISD::Tex3DFloatFloatLevel:
210 case NVPTXISD::Tex3DFloatFloatGrad:
211 case NVPTXISD::Tex3DS32S32:
212 case NVPTXISD::Tex3DS32Float:
213 case NVPTXISD::Tex3DS32FloatLevel:
214 case NVPTXISD::Tex3DS32FloatGrad:
215 case NVPTXISD::Tex3DU32S32:
216 case NVPTXISD::Tex3DU32Float:
217 case NVPTXISD::Tex3DU32FloatLevel:
218 case NVPTXISD::Tex3DU32FloatGrad:
219 case NVPTXISD::TexCubeFloatFloat:
220 case NVPTXISD::TexCubeFloatFloatLevel:
221 case NVPTXISD::TexCubeS32Float:
222 case NVPTXISD::TexCubeS32FloatLevel:
223 case NVPTXISD::TexCubeU32Float:
224 case NVPTXISD::TexCubeU32FloatLevel:
225 case NVPTXISD::TexCubeArrayFloatFloat:
226 case NVPTXISD::TexCubeArrayFloatFloatLevel:
227 case NVPTXISD::TexCubeArrayS32Float:
228 case NVPTXISD::TexCubeArrayS32FloatLevel:
229 case NVPTXISD::TexCubeArrayU32Float:
230 case NVPTXISD::TexCubeArrayU32FloatLevel:
231 case NVPTXISD::Tld4R2DFloatFloat:
232 case NVPTXISD::Tld4G2DFloatFloat:
233 case NVPTXISD::Tld4B2DFloatFloat:
234 case NVPTXISD::Tld4A2DFloatFloat:
235 case NVPTXISD::Tld4R2DS64Float:
236 case NVPTXISD::Tld4G2DS64Float:
237 case NVPTXISD::Tld4B2DS64Float:
238 case NVPTXISD::Tld4A2DS64Float:
239 case NVPTXISD::Tld4R2DU64Float:
240 case NVPTXISD::Tld4G2DU64Float:
241 case NVPTXISD::Tld4B2DU64Float:
242 case NVPTXISD::Tld4A2DU64Float:
243 case NVPTXISD::TexUnified1DFloatS32:
244 case NVPTXISD::TexUnified1DFloatFloat:
245 case NVPTXISD::TexUnified1DFloatFloatLevel:
246 case NVPTXISD::TexUnified1DFloatFloatGrad:
247 case NVPTXISD::TexUnified1DS32S32:
248 case NVPTXISD::TexUnified1DS32Float:
249 case NVPTXISD::TexUnified1DS32FloatLevel:
250 case NVPTXISD::TexUnified1DS32FloatGrad:
251 case NVPTXISD::TexUnified1DU32S32:
252 case NVPTXISD::TexUnified1DU32Float:
253 case NVPTXISD::TexUnified1DU32FloatLevel:
254 case NVPTXISD::TexUnified1DU32FloatGrad:
255 case NVPTXISD::TexUnified1DArrayFloatS32:
256 case NVPTXISD::TexUnified1DArrayFloatFloat:
257 case NVPTXISD::TexUnified1DArrayFloatFloatLevel:
258 case NVPTXISD::TexUnified1DArrayFloatFloatGrad:
259 case NVPTXISD::TexUnified1DArrayS32S32:
260 case NVPTXISD::TexUnified1DArrayS32Float:
261 case NVPTXISD::TexUnified1DArrayS32FloatLevel:
262 case NVPTXISD::TexUnified1DArrayS32FloatGrad:
263 case NVPTXISD::TexUnified1DArrayU32S32:
264 case NVPTXISD::TexUnified1DArrayU32Float:
265 case NVPTXISD::TexUnified1DArrayU32FloatLevel:
266 case NVPTXISD::TexUnified1DArrayU32FloatGrad:
267 case NVPTXISD::TexUnified2DFloatS32:
268 case NVPTXISD::TexUnified2DFloatFloat:
269 case NVPTXISD::TexUnified2DFloatFloatLevel:
270 case NVPTXISD::TexUnified2DFloatFloatGrad:
271 case NVPTXISD::TexUnified2DS32S32:
272 case NVPTXISD::TexUnified2DS32Float:
273 case NVPTXISD::TexUnified2DS32FloatLevel:
274 case NVPTXISD::TexUnified2DS32FloatGrad:
275 case NVPTXISD::TexUnified2DU32S32:
276 case NVPTXISD::TexUnified2DU32Float:
277 case NVPTXISD::TexUnified2DU32FloatLevel:
278 case NVPTXISD::TexUnified2DU32FloatGrad:
279 case NVPTXISD::TexUnified2DArrayFloatS32:
280 case NVPTXISD::TexUnified2DArrayFloatFloat:
281 case NVPTXISD::TexUnified2DArrayFloatFloatLevel:
282 case NVPTXISD::TexUnified2DArrayFloatFloatGrad:
283 case NVPTXISD::TexUnified2DArrayS32S32:
284 case NVPTXISD::TexUnified2DArrayS32Float:
285 case NVPTXISD::TexUnified2DArrayS32FloatLevel:
286 case NVPTXISD::TexUnified2DArrayS32FloatGrad:
287 case NVPTXISD::TexUnified2DArrayU32S32:
288 case NVPTXISD::TexUnified2DArrayU32Float:
289 case NVPTXISD::TexUnified2DArrayU32FloatLevel:
290 case NVPTXISD::TexUnified2DArrayU32FloatGrad:
291 case NVPTXISD::TexUnified3DFloatS32:
292 case NVPTXISD::TexUnified3DFloatFloat:
293 case NVPTXISD::TexUnified3DFloatFloatLevel:
294 case NVPTXISD::TexUnified3DFloatFloatGrad:
295 case NVPTXISD::TexUnified3DS32S32:
296 case NVPTXISD::TexUnified3DS32Float:
297 case NVPTXISD::TexUnified3DS32FloatLevel:
298 case NVPTXISD::TexUnified3DS32FloatGrad:
299 case NVPTXISD::TexUnified3DU32S32:
300 case NVPTXISD::TexUnified3DU32Float:
301 case NVPTXISD::TexUnified3DU32FloatLevel:
302 case NVPTXISD::TexUnified3DU32FloatGrad:
303 case NVPTXISD::TexUnifiedCubeFloatFloat:
304 case NVPTXISD::TexUnifiedCubeFloatFloatLevel:
305 case NVPTXISD::TexUnifiedCubeS32Float:
306 case NVPTXISD::TexUnifiedCubeS32FloatLevel:
307 case NVPTXISD::TexUnifiedCubeU32Float:
308 case NVPTXISD::TexUnifiedCubeU32FloatLevel:
309 case NVPTXISD::TexUnifiedCubeArrayFloatFloat:
310 case NVPTXISD::TexUnifiedCubeArrayFloatFloatLevel:
311 case NVPTXISD::TexUnifiedCubeArrayS32Float:
312 case NVPTXISD::TexUnifiedCubeArrayS32FloatLevel:
313 case NVPTXISD::TexUnifiedCubeArrayU32Float:
314 case NVPTXISD::TexUnifiedCubeArrayU32FloatLevel:
315 case NVPTXISD::Tld4UnifiedR2DFloatFloat:
316 case NVPTXISD::Tld4UnifiedG2DFloatFloat:
317 case NVPTXISD::Tld4UnifiedB2DFloatFloat:
318 case NVPTXISD::Tld4UnifiedA2DFloatFloat:
319 case NVPTXISD::Tld4UnifiedR2DS64Float:
320 case NVPTXISD::Tld4UnifiedG2DS64Float:
321 case NVPTXISD::Tld4UnifiedB2DS64Float:
322 case NVPTXISD::Tld4UnifiedA2DS64Float:
323 case NVPTXISD::Tld4UnifiedR2DU64Float:
324 case NVPTXISD::Tld4UnifiedG2DU64Float:
325 case NVPTXISD::Tld4UnifiedB2DU64Float:
326 case NVPTXISD::Tld4UnifiedA2DU64Float:
327 ResNode = SelectTextureIntrinsic(N);
328 break;
329 case NVPTXISD::Suld1DI8Clamp:
330 case NVPTXISD::Suld1DI16Clamp:
331 case NVPTXISD::Suld1DI32Clamp:
332 case NVPTXISD::Suld1DI64Clamp:
333 case NVPTXISD::Suld1DV2I8Clamp:
334 case NVPTXISD::Suld1DV2I16Clamp:
335 case NVPTXISD::Suld1DV2I32Clamp:
336 case NVPTXISD::Suld1DV2I64Clamp:
337 case NVPTXISD::Suld1DV4I8Clamp:
338 case NVPTXISD::Suld1DV4I16Clamp:
339 case NVPTXISD::Suld1DV4I32Clamp:
340 case NVPTXISD::Suld1DArrayI8Clamp:
341 case NVPTXISD::Suld1DArrayI16Clamp:
342 case NVPTXISD::Suld1DArrayI32Clamp:
343 case NVPTXISD::Suld1DArrayI64Clamp:
344 case NVPTXISD::Suld1DArrayV2I8Clamp:
345 case NVPTXISD::Suld1DArrayV2I16Clamp:
346 case NVPTXISD::Suld1DArrayV2I32Clamp:
347 case NVPTXISD::Suld1DArrayV2I64Clamp:
348 case NVPTXISD::Suld1DArrayV4I8Clamp:
349 case NVPTXISD::Suld1DArrayV4I16Clamp:
350 case NVPTXISD::Suld1DArrayV4I32Clamp:
351 case NVPTXISD::Suld2DI8Clamp:
352 case NVPTXISD::Suld2DI16Clamp:
353 case NVPTXISD::Suld2DI32Clamp:
354 case NVPTXISD::Suld2DI64Clamp:
355 case NVPTXISD::Suld2DV2I8Clamp:
356 case NVPTXISD::Suld2DV2I16Clamp:
357 case NVPTXISD::Suld2DV2I32Clamp:
358 case NVPTXISD::Suld2DV2I64Clamp:
359 case NVPTXISD::Suld2DV4I8Clamp:
360 case NVPTXISD::Suld2DV4I16Clamp:
361 case NVPTXISD::Suld2DV4I32Clamp:
362 case NVPTXISD::Suld2DArrayI8Clamp:
363 case NVPTXISD::Suld2DArrayI16Clamp:
364 case NVPTXISD::Suld2DArrayI32Clamp:
365 case NVPTXISD::Suld2DArrayI64Clamp:
366 case NVPTXISD::Suld2DArrayV2I8Clamp:
367 case NVPTXISD::Suld2DArrayV2I16Clamp:
368 case NVPTXISD::Suld2DArrayV2I32Clamp:
369 case NVPTXISD::Suld2DArrayV2I64Clamp:
370 case NVPTXISD::Suld2DArrayV4I8Clamp:
371 case NVPTXISD::Suld2DArrayV4I16Clamp:
372 case NVPTXISD::Suld2DArrayV4I32Clamp:
373 case NVPTXISD::Suld3DI8Clamp:
374 case NVPTXISD::Suld3DI16Clamp:
375 case NVPTXISD::Suld3DI32Clamp:
376 case NVPTXISD::Suld3DI64Clamp:
377 case NVPTXISD::Suld3DV2I8Clamp:
378 case NVPTXISD::Suld3DV2I16Clamp:
379 case NVPTXISD::Suld3DV2I32Clamp:
380 case NVPTXISD::Suld3DV2I64Clamp:
381 case NVPTXISD::Suld3DV4I8Clamp:
382 case NVPTXISD::Suld3DV4I16Clamp:
383 case NVPTXISD::Suld3DV4I32Clamp:
384 case NVPTXISD::Suld1DI8Trap:
385 case NVPTXISD::Suld1DI16Trap:
386 case NVPTXISD::Suld1DI32Trap:
387 case NVPTXISD::Suld1DI64Trap:
388 case NVPTXISD::Suld1DV2I8Trap:
389 case NVPTXISD::Suld1DV2I16Trap:
390 case NVPTXISD::Suld1DV2I32Trap:
391 case NVPTXISD::Suld1DV2I64Trap:
392 case NVPTXISD::Suld1DV4I8Trap:
393 case NVPTXISD::Suld1DV4I16Trap:
394 case NVPTXISD::Suld1DV4I32Trap:
395 case NVPTXISD::Suld1DArrayI8Trap:
396 case NVPTXISD::Suld1DArrayI16Trap:
397 case NVPTXISD::Suld1DArrayI32Trap:
398 case NVPTXISD::Suld1DArrayI64Trap:
399 case NVPTXISD::Suld1DArrayV2I8Trap:
400 case NVPTXISD::Suld1DArrayV2I16Trap:
401 case NVPTXISD::Suld1DArrayV2I32Trap:
402 case NVPTXISD::Suld1DArrayV2I64Trap:
403 case NVPTXISD::Suld1DArrayV4I8Trap:
404 case NVPTXISD::Suld1DArrayV4I16Trap:
405 case NVPTXISD::Suld1DArrayV4I32Trap:
406 case NVPTXISD::Suld2DI8Trap:
407 case NVPTXISD::Suld2DI16Trap:
408 case NVPTXISD::Suld2DI32Trap:
409 case NVPTXISD::Suld2DI64Trap:
410 case NVPTXISD::Suld2DV2I8Trap:
411 case NVPTXISD::Suld2DV2I16Trap:
412 case NVPTXISD::Suld2DV2I32Trap:
413 case NVPTXISD::Suld2DV2I64Trap:
414 case NVPTXISD::Suld2DV4I8Trap:
415 case NVPTXISD::Suld2DV4I16Trap:
416 case NVPTXISD::Suld2DV4I32Trap:
417 case NVPTXISD::Suld2DArrayI8Trap:
418 case NVPTXISD::Suld2DArrayI16Trap:
419 case NVPTXISD::Suld2DArrayI32Trap:
420 case NVPTXISD::Suld2DArrayI64Trap:
421 case NVPTXISD::Suld2DArrayV2I8Trap:
422 case NVPTXISD::Suld2DArrayV2I16Trap:
423 case NVPTXISD::Suld2DArrayV2I32Trap:
424 case NVPTXISD::Suld2DArrayV2I64Trap:
425 case NVPTXISD::Suld2DArrayV4I8Trap:
426 case NVPTXISD::Suld2DArrayV4I16Trap:
427 case NVPTXISD::Suld2DArrayV4I32Trap:
428 case NVPTXISD::Suld3DI8Trap:
429 case NVPTXISD::Suld3DI16Trap:
430 case NVPTXISD::Suld3DI32Trap:
431 case NVPTXISD::Suld3DI64Trap:
432 case NVPTXISD::Suld3DV2I8Trap:
433 case NVPTXISD::Suld3DV2I16Trap:
434 case NVPTXISD::Suld3DV2I32Trap:
435 case NVPTXISD::Suld3DV2I64Trap:
436 case NVPTXISD::Suld3DV4I8Trap:
437 case NVPTXISD::Suld3DV4I16Trap:
438 case NVPTXISD::Suld3DV4I32Trap:
439 case NVPTXISD::Suld1DI8Zero:
440 case NVPTXISD::Suld1DI16Zero:
441 case NVPTXISD::Suld1DI32Zero:
442 case NVPTXISD::Suld1DI64Zero:
443 case NVPTXISD::Suld1DV2I8Zero:
444 case NVPTXISD::Suld1DV2I16Zero:
445 case NVPTXISD::Suld1DV2I32Zero:
446 case NVPTXISD::Suld1DV2I64Zero:
447 case NVPTXISD::Suld1DV4I8Zero:
448 case NVPTXISD::Suld1DV4I16Zero:
449 case NVPTXISD::Suld1DV4I32Zero:
450 case NVPTXISD::Suld1DArrayI8Zero:
451 case NVPTXISD::Suld1DArrayI16Zero:
452 case NVPTXISD::Suld1DArrayI32Zero:
453 case NVPTXISD::Suld1DArrayI64Zero:
454 case NVPTXISD::Suld1DArrayV2I8Zero:
455 case NVPTXISD::Suld1DArrayV2I16Zero:
456 case NVPTXISD::Suld1DArrayV2I32Zero:
457 case NVPTXISD::Suld1DArrayV2I64Zero:
458 case NVPTXISD::Suld1DArrayV4I8Zero:
459 case NVPTXISD::Suld1DArrayV4I16Zero:
460 case NVPTXISD::Suld1DArrayV4I32Zero:
461 case NVPTXISD::Suld2DI8Zero:
462 case NVPTXISD::Suld2DI16Zero:
463 case NVPTXISD::Suld2DI32Zero:
464 case NVPTXISD::Suld2DI64Zero:
465 case NVPTXISD::Suld2DV2I8Zero:
466 case NVPTXISD::Suld2DV2I16Zero:
467 case NVPTXISD::Suld2DV2I32Zero:
468 case NVPTXISD::Suld2DV2I64Zero:
469 case NVPTXISD::Suld2DV4I8Zero:
470 case NVPTXISD::Suld2DV4I16Zero:
471 case NVPTXISD::Suld2DV4I32Zero:
472 case NVPTXISD::Suld2DArrayI8Zero:
473 case NVPTXISD::Suld2DArrayI16Zero:
474 case NVPTXISD::Suld2DArrayI32Zero:
475 case NVPTXISD::Suld2DArrayI64Zero:
476 case NVPTXISD::Suld2DArrayV2I8Zero:
477 case NVPTXISD::Suld2DArrayV2I16Zero:
478 case NVPTXISD::Suld2DArrayV2I32Zero:
479 case NVPTXISD::Suld2DArrayV2I64Zero:
480 case NVPTXISD::Suld2DArrayV4I8Zero:
481 case NVPTXISD::Suld2DArrayV4I16Zero:
482 case NVPTXISD::Suld2DArrayV4I32Zero:
483 case NVPTXISD::Suld3DI8Zero:
484 case NVPTXISD::Suld3DI16Zero:
485 case NVPTXISD::Suld3DI32Zero:
486 case NVPTXISD::Suld3DI64Zero:
487 case NVPTXISD::Suld3DV2I8Zero:
488 case NVPTXISD::Suld3DV2I16Zero:
489 case NVPTXISD::Suld3DV2I32Zero:
490 case NVPTXISD::Suld3DV2I64Zero:
491 case NVPTXISD::Suld3DV4I8Zero:
492 case NVPTXISD::Suld3DV4I16Zero:
493 case NVPTXISD::Suld3DV4I32Zero:
494 ResNode = SelectSurfaceIntrinsic(N);
495 break;
496 case ISD::AND:
497 case ISD::SRA:
498 case ISD::SRL:
499 // Try to select BFE
500 ResNode = SelectBFE(N);
501 break;
502 case ISD::ADDRSPACECAST:
503 ResNode = SelectAddrSpaceCast(N);
504 break;
505 default:
506 break;
507 }
508 if (ResNode)
509 return ResNode;
510 return SelectCode(N);
511}
512
513SDNode *NVPTXDAGToDAGISel::SelectIntrinsicChain(SDNode *N) {
514 unsigned IID = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
515 switch (IID) {
516 default:
517 return NULL__null;
518 case Intrinsic::nvvm_ldg_global_f:
519 case Intrinsic::nvvm_ldg_global_i:
520 case Intrinsic::nvvm_ldg_global_p:
521 case Intrinsic::nvvm_ldu_global_f:
522 case Intrinsic::nvvm_ldu_global_i:
523 case Intrinsic::nvvm_ldu_global_p:
524 return SelectLDGLDU(N);
525 }
526}
527
528static unsigned int getCodeAddrSpace(MemSDNode *N,
529 const NVPTXSubtarget &Subtarget) {
530 const Value *Src = N->getMemOperand()->getValue();
531
532 if (!Src)
533 return NVPTX::PTXLdStInstCode::GENERIC;
534
535 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType())) {
536 switch (PT->getAddressSpace()) {
537 case llvm::ADDRESS_SPACE_LOCAL: return NVPTX::PTXLdStInstCode::LOCAL;
538 case llvm::ADDRESS_SPACE_GLOBAL: return NVPTX::PTXLdStInstCode::GLOBAL;
539 case llvm::ADDRESS_SPACE_SHARED: return NVPTX::PTXLdStInstCode::SHARED;
540 case llvm::ADDRESS_SPACE_GENERIC: return NVPTX::PTXLdStInstCode::GENERIC;
541 case llvm::ADDRESS_SPACE_PARAM: return NVPTX::PTXLdStInstCode::PARAM;
542 case llvm::ADDRESS_SPACE_CONST: return NVPTX::PTXLdStInstCode::CONSTANT;
543 default: break;
544 }
545 }
546 return NVPTX::PTXLdStInstCode::GENERIC;
547}
548
549SDNode *NVPTXDAGToDAGISel::SelectIntrinsicNoChain(SDNode *N) {
550 unsigned IID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
551 switch (IID) {
552 default:
553 return nullptr;
554 case Intrinsic::nvvm_texsurf_handle_internal:
555 return SelectTexSurfHandle(N);
556 }
557}
558
559SDNode *NVPTXDAGToDAGISel::SelectTexSurfHandle(SDNode *N) {
560 // Op 0 is the intrinsic ID
561 SDValue Wrapper = N->getOperand(1);
562 SDValue GlobalVal = Wrapper.getOperand(0);
563 return CurDAG->getMachineNode(NVPTX::texsurf_handles, SDLoc(N), MVT::i64,
564 GlobalVal);
565}
566
567SDNode *NVPTXDAGToDAGISel::SelectAddrSpaceCast(SDNode *N) {
568 SDValue Src = N->getOperand(0);
569 AddrSpaceCastSDNode *CastN = cast<AddrSpaceCastSDNode>(N);
570 unsigned SrcAddrSpace = CastN->getSrcAddressSpace();
571 unsigned DstAddrSpace = CastN->getDestAddressSpace();
572
573 assert(SrcAddrSpace != DstAddrSpace &&((SrcAddrSpace != DstAddrSpace && "addrspacecast must be between different address spaces"
) ? static_cast<void> (0) : __assert_fail ("SrcAddrSpace != DstAddrSpace && \"addrspacecast must be between different address spaces\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.6~svn224369/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp"
, 574, __PRETTY_FUNCTION__))
574 "addrspacecast must be between different address spaces")((SrcAddrSpace != DstAddrSpace && "addrspacecast must be between different address spaces"
) ? static_cast<void> (0) : __assert_fail ("SrcAddrSpace != DstAddrSpace && \"addrspacecast must be between different address spaces\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.6~svn224369/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp"
, 574, __PRETTY_FUNCTION__))
;
575
576 if (DstAddrSpace == ADDRESS_SPACE_GENERIC) {
577 // Specific to generic
578 unsigned Opc;
579 switch (SrcAddrSpace) {
580 default: report_fatal_error("Bad address space in addrspacecast");
581 case ADDRESS_SPACE_GLOBAL:
582 Opc = Subtarget.is64Bit() ? NVPTX::cvta_global_yes_64
583 : NVPTX::cvta_global_yes;
584 break;
585 case ADDRESS_SPACE_SHARED:
586 Opc = Subtarget.is64Bit() ? NVPTX::cvta_shared_yes_64
587 : NVPTX::cvta_shared_yes;
588 break;
589 case ADDRESS_SPACE_CONST:
590 Opc = Subtarget.is64Bit() ? NVPTX::cvta_const_yes_64
591 : NVPTX::cvta_const_yes;
592 break;
593 case ADDRESS_SPACE_LOCAL:
594 Opc = Subtarget.is64Bit() ? NVPTX::cvta_local_yes_64
595 : NVPTX::cvta_local_yes;
596 break;
597 }
598 return CurDAG->getMachineNode(Opc, SDLoc(N), N->getValueType(0), Src);
599 } else {
600 // Generic to specific
601 if (SrcAddrSpace != 0)
602 report_fatal_error("Cannot cast between two non-generic address spaces");
603 unsigned Opc;
604 switch (DstAddrSpace) {
605 default: report_fatal_error("Bad address space in addrspacecast");
606 case ADDRESS_SPACE_GLOBAL:
607 Opc = Subtarget.is64Bit() ? NVPTX::cvta_to_global_yes_64
608 : NVPTX::cvta_to_global_yes;
609 break;
610 case ADDRESS_SPACE_SHARED:
611 Opc = Subtarget.is64Bit() ? NVPTX::cvta_to_shared_yes_64
612 : NVPTX::cvta_to_shared_yes;
613 break;
614 case ADDRESS_SPACE_CONST:
615 Opc = Subtarget.is64Bit() ? NVPTX::cvta_to_const_yes_64
616 : NVPTX::cvta_to_const_yes;
617 break;
618 case ADDRESS_SPACE_LOCAL:
619 Opc = Subtarget.is64Bit() ? NVPTX::cvta_to_local_yes_64
620 : NVPTX::cvta_to_local_yes;
621 break;
622 }
623 return CurDAG->getMachineNode(Opc, SDLoc(N), N->getValueType(0), Src);
624 }
625}
626
627SDNode *NVPTXDAGToDAGISel::SelectLoad(SDNode *N) {
628 SDLoc dl(N);
629 LoadSDNode *LD = cast<LoadSDNode>(N);
630 EVT LoadedVT = LD->getMemoryVT();
631 SDNode *NVPTXLD = nullptr;
632
633 // do not support pre/post inc/dec
634 if (LD->isIndexed())
635 return nullptr;
636
637 if (!LoadedVT.isSimple())
638 return nullptr;
639
640 // Address Space Setting
641 unsigned int codeAddrSpace = getCodeAddrSpace(LD, Subtarget);
642
643 // Volatile Setting
644 // - .volatile is only availalble for .global and .shared
645 bool isVolatile = LD->isVolatile();
646 if (codeAddrSpace != NVPTX::PTXLdStInstCode::GLOBAL &&
647 codeAddrSpace != NVPTX::PTXLdStInstCode::SHARED &&
648 codeAddrSpace != NVPTX::PTXLdStInstCode::GENERIC)
649 isVolatile = false;
650
651 // Vector Setting
652 MVT SimpleVT = LoadedVT.getSimpleVT();
653 unsigned vecType = NVPTX::PTXLdStInstCode::Scalar;
654 if (SimpleVT.isVector()) {
655 unsigned num = SimpleVT.getVectorNumElements();
656 if (num == 2)
657 vecType = NVPTX::PTXLdStInstCode::V2;
658 else if (num == 4)
659 vecType = NVPTX::PTXLdStInstCode::V4;
660 else
661 return nullptr;
662 }
663
664 // Type Setting: fromType + fromTypeWidth
665 //
666 // Sign : ISD::SEXTLOAD
667 // Unsign : ISD::ZEXTLOAD, ISD::NON_EXTLOAD or ISD::EXTLOAD and the
668 // type is integer
669 // Float : ISD::NON_EXTLOAD or ISD::EXTLOAD and the type is float
670 MVT ScalarVT = SimpleVT.getScalarType();
671 // Read at least 8 bits (predicates are stored as 8-bit values)
672 unsigned fromTypeWidth = std::max(8U, ScalarVT.getSizeInBits());
673 unsigned int fromType;
674 if ((LD->getExtensionType() == ISD::SEXTLOAD))
675 fromType = NVPTX::PTXLdStInstCode::Signed;
676 else if (ScalarVT.isFloatingPoint())
677 fromType = NVPTX::PTXLdStInstCode::Float;
678 else
679 fromType = NVPTX::PTXLdStInstCode::Unsigned;
680
681 // Create the machine instruction DAG
682 SDValue Chain = N->getOperand(0);
683 SDValue N1 = N->getOperand(1);
684 SDValue Addr;
685 SDValue Offset, Base;
686 unsigned Opcode;
687 MVT::SimpleValueType TargetVT = LD->getSimpleValueType(0).SimpleTy;
688
689 if (SelectDirectAddr(N1, Addr)) {
690 switch (TargetVT) {
691 case MVT::i8:
692 Opcode = NVPTX::LD_i8_avar;
693 break;
694 case MVT::i16:
695 Opcode = NVPTX::LD_i16_avar;
696 break;
697 case MVT::i32:
698 Opcode = NVPTX::LD_i32_avar;
699 break;
700 case MVT::i64:
701 Opcode = NVPTX::LD_i64_avar;
702 break;
703 case MVT::f32:
704 Opcode = NVPTX::LD_f32_avar;
705 break;
706 case MVT::f64:
707 Opcode = NVPTX::LD_f64_avar;
708 break;
709 default:
710 return nullptr;
711 }
712 SDValue Ops[] = { getI32Imm(isVolatile), getI32Imm(codeAddrSpace),
713 getI32Imm(vecType), getI32Imm(fromType),
714 getI32Imm(fromTypeWidth), Addr, Chain };
715 NVPTXLD = CurDAG->getMachineNode(Opcode, dl, TargetVT, MVT::Other, Ops);
716 } else if (Subtarget.is64Bit()
717 ? SelectADDRsi64(N1.getNode(), N1, Base, Offset)
718 : SelectADDRsi(N1.getNode(), N1, Base, Offset)) {
719 switch (TargetVT) {
720 case MVT::i8:
721 Opcode = NVPTX::LD_i8_asi;
722 break;
723 case MVT::i16:
724 Opcode = NVPTX::LD_i16_asi;
725 break;
726 case MVT::i32:
727 Opcode = NVPTX::LD_i32_asi;
728 break;
729 case MVT::i64:
730 Opcode = NVPTX::LD_i64_asi;
731 break;
732 case MVT::f32:
733 Opcode = NVPTX::LD_f32_asi;
734 break;
735 case MVT::f64:
736 Opcode = NVPTX::LD_f64_asi;
737 break;
738 default:
739 return nullptr;
740 }
741 SDValue Ops[] = { getI32Imm(isVolatile), getI32Imm(codeAddrSpace),
742 getI32Imm(vecType), getI32Imm(fromType),
743 getI32Imm(fromTypeWidth), Base, Offset, Chain };
744 NVPTXLD = CurDAG->getMachineNode(Opcode, dl, TargetVT, MVT::Other, Ops);
745 } else if (Subtarget.is64Bit()
746 ? SelectADDRri64(N1.getNode(), N1, Base, Offset)
747 : SelectADDRri(N1.getNode(), N1, Base, Offset)) {
748 if (Subtarget.is64Bit()) {
749 switch (TargetVT) {
750 case MVT::i8:
751 Opcode = NVPTX::LD_i8_ari_64;
752 break;
753 case MVT::i16:
754 Opcode = NVPTX::LD_i16_ari_64;
755 break;
756 case MVT::i32:
757 Opcode = NVPTX::LD_i32_ari_64;
758 break;
759 case MVT::i64:
760 Opcode = NVPTX::LD_i64_ari_64;
761 break;
762 case MVT::f32:
763 Opcode = NVPTX::LD_f32_ari_64;
764 break;
765 case MVT::f64:
766 Opcode = NVPTX::LD_f64_ari_64;
767 break;
768 default:
769 return nullptr;
770 }
771 } else {
772 switch (TargetVT) {
773 case MVT::i8:
774 Opcode = NVPTX::LD_i8_ari;
775 break;
776 case MVT::i16:
777 Opcode = NVPTX::LD_i16_ari;
778 break;
779 case MVT::i32:
780 Opcode = NVPTX::LD_i32_ari;
781 break;
782 case MVT::i64:
783 Opcode = NVPTX::LD_i64_ari;
784 break;
785 case MVT::f32:
786 Opcode = NVPTX::LD_f32_ari;
787 break;
788 case MVT::f64:
789 Opcode = NVPTX::LD_f64_ari;
790 break;
791 default:
792 return nullptr;
793 }
794 }
795 SDValue Ops[] = { getI32Imm(isVolatile), getI32Imm(codeAddrSpace),
796 getI32Imm(vecType), getI32Imm(fromType),
797 getI32Imm(fromTypeWidth), Base, Offset, Chain };
798 NVPTXLD = CurDAG->getMachineNode(Opcode, dl, TargetVT, MVT::Other, Ops);
799 } else {
800 if (Subtarget.is64Bit()) {
801 switch (TargetVT) {
802 case MVT::i8:
803 Opcode = NVPTX::LD_i8_areg_64;
804 break;
805 case MVT::i16:
806 Opcode = NVPTX::LD_i16_areg_64;
807 break;
808 case MVT::i32:
809 Opcode = NVPTX::LD_i32_areg_64;
810 break;
811 case MVT::i64:
812 Opcode = NVPTX::LD_i64_areg_64;
813 break;
814 case MVT::f32:
815 Opcode = NVPTX::LD_f32_areg_64;
816 break;
817 case MVT::f64:
818 Opcode = NVPTX::LD_f64_areg_64;
819 break;
820 default:
821 return nullptr;
822 }
823 } else {
824 switch (TargetVT) {
825 case MVT::i8:
826 Opcode = NVPTX::LD_i8_areg;
827 break;
828 case MVT::i16:
829 Opcode = NVPTX::LD_i16_areg;
830 break;
831 case MVT::i32:
832 Opcode = NVPTX::LD_i32_areg;
833 break;
834 case MVT::i64:
835 Opcode = NVPTX::LD_i64_areg;
836 break;
837 case MVT::f32:
838 Opcode = NVPTX::LD_f32_areg;
839 break;
840 case MVT::f64:
841 Opcode = NVPTX::LD_f64_areg;
842 break;
843 default:
844 return nullptr;
845 }
846 }
847 SDValue Ops[] = { getI32Imm(isVolatile), getI32Imm(codeAddrSpace),
848 getI32Imm(vecType), getI32Imm(fromType),
849 getI32Imm(fromTypeWidth), N1, Chain };
850 NVPTXLD = CurDAG->getMachineNode(Opcode, dl, TargetVT, MVT::Other, Ops);
851 }
852
853 if (NVPTXLD) {
854 MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
855 MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
856 cast<MachineSDNode>(NVPTXLD)->setMemRefs(MemRefs0, MemRefs0 + 1);
857 }
858
859 return NVPTXLD;
860}
861
862SDNode *NVPTXDAGToDAGISel::SelectLoadVector(SDNode *N) {
863
864 SDValue Chain = N->getOperand(0);
865 SDValue Op1 = N->getOperand(1);
866 SDValue Addr, Offset, Base;
867 unsigned Opcode;
868 SDLoc DL(N);
869 SDNode *LD;
870 MemSDNode *MemSD = cast<MemSDNode>(N);
871 EVT LoadedVT = MemSD->getMemoryVT();
872
873 if (!LoadedVT.isSimple())
874 return nullptr;
875
876 // Address Space Setting
877 unsigned int CodeAddrSpace = getCodeAddrSpace(MemSD, Subtarget);
878
879 // Volatile Setting
880 // - .volatile is only availalble for .global and .shared
881 bool IsVolatile = MemSD->isVolatile();
882 if (CodeAddrSpace != NVPTX::PTXLdStInstCode::GLOBAL &&
883 CodeAddrSpace != NVPTX::PTXLdStInstCode::SHARED &&
884 CodeAddrSpace != NVPTX::PTXLdStInstCode::GENERIC)
885 IsVolatile = false;
886
887 // Vector Setting
888 MVT SimpleVT = LoadedVT.getSimpleVT();
889
890 // Type Setting: fromType + fromTypeWidth
891 //
892 // Sign : ISD::SEXTLOAD
893 // Unsign : ISD::ZEXTLOAD, ISD::NON_EXTLOAD or ISD::EXTLOAD and the
894 // type is integer
895 // Float : ISD::NON_EXTLOAD or ISD::EXTLOAD and the type is float
896 MVT ScalarVT = SimpleVT.getScalarType();
897 // Read at least 8 bits (predicates are stored as 8-bit values)
898 unsigned FromTypeWidth = std::max(8U, ScalarVT.getSizeInBits());
899 unsigned int FromType;
900 // The last operand holds the original LoadSDNode::getExtensionType() value
901 unsigned ExtensionType = cast<ConstantSDNode>(
902 N->getOperand(N->getNumOperands() - 1))->getZExtValue();
903 if (ExtensionType == ISD::SEXTLOAD)
904 FromType = NVPTX::PTXLdStInstCode::Signed;
905 else if (ScalarVT.isFloatingPoint())
906 FromType = NVPTX::PTXLdStInstCode::Float;
907 else
908 FromType = NVPTX::PTXLdStInstCode::Unsigned;
909
910 unsigned VecType;
911
912 switch (N->getOpcode()) {
913 case NVPTXISD::LoadV2:
914 VecType = NVPTX::PTXLdStInstCode::V2;
915 break;
916 case NVPTXISD::LoadV4:
917 VecType = NVPTX::PTXLdStInstCode::V4;
918 break;
919 default:
920 return nullptr;
921 }
922
923 EVT EltVT = N->getValueType(0);
924
925 if (SelectDirectAddr(Op1, Addr)) {
926 switch (N->getOpcode()) {
927 default:
928 return nullptr;
929 case NVPTXISD::LoadV2:
930 switch (EltVT.getSimpleVT().SimpleTy) {
931 default:
932 return nullptr;
933 case MVT::i8:
934 Opcode = NVPTX::LDV_i8_v2_avar;
935 break;
936 case MVT::i16:
937 Opcode = NVPTX::LDV_i16_v2_avar;
938 break;
939 case MVT::i32:
940 Opcode = NVPTX::LDV_i32_v2_avar;
941 break;
942 case MVT::i64:
943 Opcode = NVPTX::LDV_i64_v2_avar;
944 break;
945 case MVT::f32:
946 Opcode = NVPTX::LDV_f32_v2_avar;
947 break;
948 case MVT::f64:
949 Opcode = NVPTX::LDV_f64_v2_avar;
950 break;
951 }
952 break;
953 case NVPTXISD::LoadV4:
954 switch (EltVT.getSimpleVT().SimpleTy) {
955 default:
956 return nullptr;
957 case MVT::i8:
958 Opcode = NVPTX::LDV_i8_v4_avar;
959 break;
960 case MVT::i16:
961 Opcode = NVPTX::LDV_i16_v4_avar;
962 break;
963 case MVT::i32:
964 Opcode = NVPTX::LDV_i32_v4_avar;
965 break;
966 case MVT::f32:
967 Opcode = NVPTX::LDV_f32_v4_avar;
968 break;
969 }
970 break;
971 }
972
973 SDValue Ops[] = { getI32Imm(IsVolatile), getI32Imm(CodeAddrSpace),
974 getI32Imm(VecType), getI32Imm(FromType),
975 getI32Imm(FromTypeWidth), Addr, Chain };
976 LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(), Ops);
977 } else if (Subtarget.is64Bit()
978 ? SelectADDRsi64(Op1.getNode(), Op1, Base, Offset)
979 : SelectADDRsi(Op1.getNode(), Op1, Base, Offset)) {
980 switch (N->getOpcode()) {
981 default:
982 return nullptr;
983 case NVPTXISD::LoadV2:
984 switch (EltVT.getSimpleVT().SimpleTy) {
985 default:
986 return nullptr;
987 case MVT::i8:
988 Opcode = NVPTX::LDV_i8_v2_asi;
989 break;
990 case MVT::i16:
991 Opcode = NVPTX::LDV_i16_v2_asi;
992 break;
993 case MVT::i32:
994 Opcode = NVPTX::LDV_i32_v2_asi;
995 break;
996 case MVT::i64:
997 Opcode = NVPTX::LDV_i64_v2_asi;
998 break;
999 case MVT::f32:
1000 Opcode = NVPTX::LDV_f32_v2_asi;
1001 break;
1002 case MVT::f64:
1003 Opcode = NVPTX::LDV_f64_v2_asi;
1004 break;
1005 }
1006 break;
1007 case NVPTXISD::LoadV4:
1008 switch (EltVT.getSimpleVT().SimpleTy) {
1009 default:
1010 return nullptr;
1011 case MVT::i8:
1012 Opcode = NVPTX::LDV_i8_v4_asi;
1013 break;
1014 case MVT::i16:
1015 Opcode = NVPTX::LDV_i16_v4_asi;
1016 break;
1017 case MVT::i32:
1018 Opcode = NVPTX::LDV_i32_v4_asi;
1019 break;
1020 case MVT::f32:
1021 Opcode = NVPTX::LDV_f32_v4_asi;
1022 break;
1023 }
1024 break;
1025 }
1026
1027 SDValue Ops[] = { getI32Imm(IsVolatile), getI32Imm(CodeAddrSpace),
1028 getI32Imm(VecType), getI32Imm(FromType),
1029 getI32Imm(FromTypeWidth), Base, Offset, Chain };
1030 LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(), Ops);
1031 } else if (Subtarget.is64Bit()
1032 ? SelectADDRri64(Op1.getNode(), Op1, Base, Offset)
1033 : SelectADDRri(Op1.getNode(), Op1, Base, Offset)) {
1034 if (Subtarget.is64Bit()) {
1035 switch (N->getOpcode()) {
1036 default:
1037 return nullptr;
1038 case NVPTXISD::LoadV2:
1039 switch (EltVT.getSimpleVT().SimpleTy) {
1040 default:
1041 return nullptr;
1042 case MVT::i8:
1043 Opcode = NVPTX::LDV_i8_v2_ari_64;
1044 break;
1045 case MVT::i16:
1046 Opcode = NVPTX::LDV_i16_v2_ari_64;
1047 break;
1048 case MVT::i32:
1049 Opcode = NVPTX::LDV_i32_v2_ari_64;
1050 break;
1051 case MVT::i64:
1052 Opcode = NVPTX::LDV_i64_v2_ari_64;
1053 break;
1054 case MVT::f32:
1055 Opcode = NVPTX::LDV_f32_v2_ari_64;
1056 break;
1057 case MVT::f64:
1058 Opcode = NVPTX::LDV_f64_v2_ari_64;
1059 break;
1060 }
1061 break;
1062 case NVPTXISD::LoadV4:
1063 switch (EltVT.getSimpleVT().SimpleTy) {
1064 default:
1065 return nullptr;
1066 case MVT::i8:
1067 Opcode = NVPTX::LDV_i8_v4_ari_64;
1068 break;
1069 case MVT::i16:
1070 Opcode = NVPTX::LDV_i16_v4_ari_64;
1071 break;
1072 case MVT::i32:
1073 Opcode = NVPTX::LDV_i32_v4_ari_64;
1074 break;
1075 case MVT::f32:
1076 Opcode = NVPTX::LDV_f32_v4_ari_64;
1077 break;
1078 }
1079 break;
1080 }
1081 } else {
1082 switch (N->getOpcode()) {
1083 default:
1084 return nullptr;
1085 case NVPTXISD::LoadV2:
1086 switch (EltVT.getSimpleVT().SimpleTy) {
1087 default:
1088 return nullptr;
1089 case MVT::i8:
1090 Opcode = NVPTX::LDV_i8_v2_ari;
1091 break;
1092 case MVT::i16:
1093 Opcode = NVPTX::LDV_i16_v2_ari;
1094 break;
1095 case MVT::i32:
1096 Opcode = NVPTX::LDV_i32_v2_ari;
1097 break;
1098 case MVT::i64:
1099 Opcode = NVPTX::LDV_i64_v2_ari;
1100 break;
1101 case MVT::f32:
1102 Opcode = NVPTX::LDV_f32_v2_ari;
1103 break;
1104 case MVT::f64:
1105 Opcode = NVPTX::LDV_f64_v2_ari;
1106 break;
1107 }
1108 break;
1109 case NVPTXISD::LoadV4:
1110 switch (EltVT.getSimpleVT().SimpleTy) {
1111 default:
1112 return nullptr;
1113 case MVT::i8:
1114 Opcode = NVPTX::LDV_i8_v4_ari;
1115 break;
1116 case MVT::i16:
1117 Opcode = NVPTX::LDV_i16_v4_ari;
1118 break;
1119 case MVT::i32:
1120 Opcode = NVPTX::LDV_i32_v4_ari;
1121 break;
1122 case MVT::f32:
1123 Opcode = NVPTX::LDV_f32_v4_ari;
1124 break;
1125 }
1126 break;
1127 }
1128 }
1129
1130 SDValue Ops[] = { getI32Imm(IsVolatile), getI32Imm(CodeAddrSpace),
1131 getI32Imm(VecType), getI32Imm(FromType),
1132 getI32Imm(FromTypeWidth), Base, Offset, Chain };
1133
1134 LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(), Ops);
1135 } else {
1136 if (Subtarget.is64Bit()) {
1137 switch (N->getOpcode()) {
1138 default:
1139 return nullptr;
1140 case NVPTXISD::LoadV2:
1141 switch (EltVT.getSimpleVT().SimpleTy) {
1142 default:
1143 return nullptr;
1144 case MVT::i8:
1145 Opcode = NVPTX::LDV_i8_v2_areg_64;
1146 break;
1147 case MVT::i16:
1148 Opcode = NVPTX::LDV_i16_v2_areg_64;
1149 break;
1150 case MVT::i32:
1151 Opcode = NVPTX::LDV_i32_v2_areg_64;
1152 break;
1153 case MVT::i64:
1154 Opcode = NVPTX::LDV_i64_v2_areg_64;
1155 break;
1156 case MVT::f32:
1157 Opcode = NVPTX::LDV_f32_v2_areg_64;
1158 break;
1159 case MVT::f64:
1160 Opcode = NVPTX::LDV_f64_v2_areg_64;
1161 break;
1162 }
1163 break;
1164 case NVPTXISD::LoadV4:
1165 switch (EltVT.getSimpleVT().SimpleTy) {
1166 default:
1167 return nullptr;
1168 case MVT::i8:
1169 Opcode = NVPTX::LDV_i8_v4_areg_64;
1170 break;
1171 case MVT::i16:
1172 Opcode = NVPTX::LDV_i16_v4_areg_64;
1173 break;
1174 case MVT::i32:
1175 Opcode = NVPTX::LDV_i32_v4_areg_64;
1176 break;
1177 case MVT::f32:
1178 Opcode = NVPTX::LDV_f32_v4_areg_64;
1179 break;
1180 }
1181 break;
1182 }
1183 } else {
1184 switch (N->getOpcode()) {
1185 default:
1186 return nullptr;
1187 case NVPTXISD::LoadV2:
1188 switch (EltVT.getSimpleVT().SimpleTy) {
1189 default:
1190 return nullptr;
1191 case MVT::i8:
1192 Opcode = NVPTX::LDV_i8_v2_areg;
1193 break;
1194 case MVT::i16:
1195 Opcode = NVPTX::LDV_i16_v2_areg;
1196 break;
1197 case MVT::i32:
1198 Opcode = NVPTX::LDV_i32_v2_areg;
1199 break;
1200 case MVT::i64:
1201 Opcode = NVPTX::LDV_i64_v2_areg;
1202 break;
1203 case MVT::f32:
1204 Opcode = NVPTX::LDV_f32_v2_areg;
1205 break;
1206 case MVT::f64:
1207 Opcode = NVPTX::LDV_f64_v2_areg;
1208 break;
1209 }
1210 break;
1211 case NVPTXISD::LoadV4:
1212 switch (EltVT.getSimpleVT().SimpleTy) {
1213 default:
1214 return nullptr;
1215 case MVT::i8:
1216 Opcode = NVPTX::LDV_i8_v4_areg;
1217 break;
1218 case MVT::i16:
1219 Opcode = NVPTX::LDV_i16_v4_areg;
1220 break;
1221 case MVT::i32:
1222 Opcode = NVPTX::LDV_i32_v4_areg;
1223 break;
1224 case MVT::f32:
1225 Opcode = NVPTX::LDV_f32_v4_areg;
1226 break;
1227 }
1228 break;
1229 }
1230 }
1231
1232 SDValue Ops[] = { getI32Imm(IsVolatile), getI32Imm(CodeAddrSpace),
1233 getI32Imm(VecType), getI32Imm(FromType),
1234 getI32Imm(FromTypeWidth), Op1, Chain };
1235 LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(), Ops);
1236 }
1237
1238 MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
1239 MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
1240 cast<MachineSDNode>(LD)->setMemRefs(MemRefs0, MemRefs0 + 1);
1241
1242 return LD;
1243}
1244
1245SDNode *NVPTXDAGToDAGISel::SelectLDGLDU(SDNode *N) {
1246
1247 SDValue Chain = N->getOperand(0);
1248 SDValue Op1;
1249 MemSDNode *Mem;
1250 bool IsLDG = true;
1251
1252 // If this is an LDG intrinsic, the address is the third operand. Its its an
1253 // LDG/LDU SD node (from custom vector handling), then its the second operand
1254 if (N->getOpcode() == ISD::INTRINSIC_W_CHAIN) {
1255 Op1 = N->getOperand(2);
1256 Mem = cast<MemIntrinsicSDNode>(N);
1257 unsigned IID = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
1258 switch (IID) {
1259 default:
1260 return NULL__null;
1261 case Intrinsic::nvvm_ldg_global_f:
1262 case Intrinsic::nvvm_ldg_global_i:
1263 case Intrinsic::nvvm_ldg_global_p:
1264 IsLDG = true;
1265 break;
1266 case Intrinsic::nvvm_ldu_global_f:
1267 case Intrinsic::nvvm_ldu_global_i:
1268 case Intrinsic::nvvm_ldu_global_p:
1269 IsLDG = false;
1270 break;
1271 }
1272 } else {
1273 Op1 = N->getOperand(1);
1274 Mem = cast<MemSDNode>(N);
1275 }
1276
1277 unsigned Opcode;
1278 SDLoc DL(N);
1279 SDNode *LD;
1280 SDValue Base, Offset, Addr;
1281
1282 EVT EltVT = Mem->getMemoryVT();
1283 if (EltVT.isVector()) {
1284 EltVT = EltVT.getVectorElementType();
1285 }
1286
1287 if (SelectDirectAddr(Op1, Addr)) {
1288 switch (N->getOpcode()) {
1289 default:
1290 return nullptr;
1291 case ISD::INTRINSIC_W_CHAIN:
1292 if (IsLDG) {
1293 switch (EltVT.getSimpleVT().SimpleTy) {
1294 default:
1295 return nullptr;
1296 case MVT::i8:
1297 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i8avar;
1298 break;
1299 case MVT::i16:
1300 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i16avar;
1301 break;
1302 case MVT::i32:
1303 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i32avar;
1304 break;
1305 case MVT::i64:
1306 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i64avar;
1307 break;
1308 case MVT::f32:
1309 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_f32avar;
1310 break;
1311 case MVT::f64:
1312 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_f64avar;
1313 break;
1314 }
1315 } else {
1316 switch (EltVT.getSimpleVT().SimpleTy) {
1317 default:
1318 return nullptr;
1319 case MVT::i8:
1320 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i8avar;
1321 break;
1322 case MVT::i16:
1323 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i16avar;
1324 break;
1325 case MVT::i32:
1326 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i32avar;
1327 break;
1328 case MVT::i64:
1329 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i64avar;
1330 break;
1331 case MVT::f32:
1332 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_f32avar;
1333 break;
1334 case MVT::f64:
1335 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_f64avar;
1336 break;
1337 }
1338 }
1339 break;
1340 case NVPTXISD::LDGV2:
1341 switch (EltVT.getSimpleVT().SimpleTy) {
1342 default:
1343 return nullptr;
1344 case MVT::i8:
1345 Opcode = NVPTX::INT_PTX_LDG_G_v2i8_ELE_avar;
1346 break;
1347 case MVT::i16:
1348 Opcode = NVPTX::INT_PTX_LDG_G_v2i16_ELE_avar;
1349 break;
1350 case MVT::i32:
1351 Opcode = NVPTX::INT_PTX_LDG_G_v2i32_ELE_avar;
1352 break;
1353 case MVT::i64:
1354 Opcode = NVPTX::INT_PTX_LDG_G_v2i64_ELE_avar;
1355 break;
1356 case MVT::f32:
1357 Opcode = NVPTX::INT_PTX_LDG_G_v2f32_ELE_avar;
1358 break;
1359 case MVT::f64:
1360 Opcode = NVPTX::INT_PTX_LDG_G_v2f64_ELE_avar;
1361 break;
1362 }
1363 break;
1364 case NVPTXISD::LDUV2:
1365 switch (EltVT.getSimpleVT().SimpleTy) {
1366 default:
1367 return nullptr;
1368 case MVT::i8:
1369 Opcode = NVPTX::INT_PTX_LDU_G_v2i8_ELE_avar;
1370 break;
1371 case MVT::i16:
1372 Opcode = NVPTX::INT_PTX_LDU_G_v2i16_ELE_avar;
1373 break;
1374 case MVT::i32:
1375 Opcode = NVPTX::INT_PTX_LDU_G_v2i32_ELE_avar;
1376 break;
1377 case MVT::i64:
1378 Opcode = NVPTX::INT_PTX_LDU_G_v2i64_ELE_avar;
1379 break;
1380 case MVT::f32:
1381 Opcode = NVPTX::INT_PTX_LDU_G_v2f32_ELE_avar;
1382 break;
1383 case MVT::f64:
1384 Opcode = NVPTX::INT_PTX_LDU_G_v2f64_ELE_avar;
1385 break;
1386 }
1387 break;
1388 case NVPTXISD::LDGV4:
1389 switch (EltVT.getSimpleVT().SimpleTy) {
1390 default:
1391 return nullptr;
1392 case MVT::i8:
1393 Opcode = NVPTX::INT_PTX_LDG_G_v4i8_ELE_avar;
1394 break;
1395 case MVT::i16:
1396 Opcode = NVPTX::INT_PTX_LDG_G_v4i16_ELE_avar;
1397 break;
1398 case MVT::i32:
1399 Opcode = NVPTX::INT_PTX_LDG_G_v4i32_ELE_avar;
1400 break;
1401 case MVT::f32:
1402 Opcode = NVPTX::INT_PTX_LDG_G_v4f32_ELE_avar;
1403 break;
1404 }
1405 break;
1406 case NVPTXISD::LDUV4:
1407 switch (EltVT.getSimpleVT().SimpleTy) {
1408 default:
1409 return nullptr;
1410 case MVT::i8:
1411 Opcode = NVPTX::INT_PTX_LDU_G_v4i8_ELE_avar;
1412 break;
1413 case MVT::i16:
1414 Opcode = NVPTX::INT_PTX_LDU_G_v4i16_ELE_avar;
1415 break;
1416 case MVT::i32:
1417 Opcode = NVPTX::INT_PTX_LDU_G_v4i32_ELE_avar;
1418 break;
1419 case MVT::f32:
1420 Opcode = NVPTX::INT_PTX_LDU_G_v4f32_ELE_avar;
1421 break;
1422 }
1423 break;
1424 }
1425
1426 SDValue Ops[] = { Addr, Chain };
1427 LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(), Ops);
1428 } else if (Subtarget.is64Bit()
1429 ? SelectADDRri64(Op1.getNode(), Op1, Base, Offset)
1430 : SelectADDRri(Op1.getNode(), Op1, Base, Offset)) {
1431 if (Subtarget.is64Bit()) {
1432 switch (N->getOpcode()) {
1433 default:
1434 return nullptr;
1435 case ISD::INTRINSIC_W_CHAIN:
1436 if (IsLDG) {
1437 switch (EltVT.getSimpleVT().SimpleTy) {
1438 default:
1439 return nullptr;
1440 case MVT::i8:
1441 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i8ari64;
1442 break;
1443 case MVT::i16:
1444 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i16ari64;
1445 break;
1446 case MVT::i32:
1447 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i32ari64;
1448 break;
1449 case MVT::i64:
1450 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i64ari64;
1451 break;
1452 case MVT::f32:
1453 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_f32ari64;
1454 break;
1455 case MVT::f64:
1456 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_f64ari64;
1457 break;
1458 }
1459 } else {
1460 switch (EltVT.getSimpleVT().SimpleTy) {
1461 default:
1462 return nullptr;
1463 case MVT::i8:
1464 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i8ari64;
1465 break;
1466 case MVT::i16:
1467 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i16ari64;
1468 break;
1469 case MVT::i32:
1470 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i32ari64;
1471 break;
1472 case MVT::i64:
1473 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i64ari64;
1474 break;
1475 case MVT::f32:
1476 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_f32ari64;
1477 break;
1478 case MVT::f64:
1479 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_f64ari64;
1480 break;
1481 }
1482 }
1483 break;
1484 case NVPTXISD::LDGV2:
1485 switch (EltVT.getSimpleVT().SimpleTy) {
1486 default:
1487 return nullptr;
1488 case MVT::i8:
1489 Opcode = NVPTX::INT_PTX_LDG_G_v2i8_ELE_ari64;
1490 break;
1491 case MVT::i16:
1492 Opcode = NVPTX::INT_PTX_LDG_G_v2i16_ELE_ari64;
1493 break;
1494 case MVT::i32:
1495 Opcode = NVPTX::INT_PTX_LDG_G_v2i32_ELE_ari64;
1496 break;
1497 case MVT::i64:
1498 Opcode = NVPTX::INT_PTX_LDG_G_v2i64_ELE_ari64;
1499 break;
1500 case MVT::f32:
1501 Opcode = NVPTX::INT_PTX_LDG_G_v2f32_ELE_ari64;
1502 break;
1503 case MVT::f64:
1504 Opcode = NVPTX::INT_PTX_LDG_G_v2f64_ELE_ari64;
1505 break;
1506 }
1507 break;
1508 case NVPTXISD::LDUV2:
1509 switch (EltVT.getSimpleVT().SimpleTy) {
1510 default:
1511 return nullptr;
1512 case MVT::i8:
1513 Opcode = NVPTX::INT_PTX_LDU_G_v2i8_ELE_ari64;
1514 break;
1515 case MVT::i16:
1516 Opcode = NVPTX::INT_PTX_LDU_G_v2i16_ELE_ari64;
1517 break;
1518 case MVT::i32:
1519 Opcode = NVPTX::INT_PTX_LDU_G_v2i32_ELE_ari64;
1520 break;
1521 case MVT::i64:
1522 Opcode = NVPTX::INT_PTX_LDU_G_v2i64_ELE_ari64;
1523 break;
1524 case MVT::f32:
1525 Opcode = NVPTX::INT_PTX_LDU_G_v2f32_ELE_ari64;
1526 break;
1527 case MVT::f64:
1528 Opcode = NVPTX::INT_PTX_LDU_G_v2f64_ELE_ari64;
1529 break;
1530 }
1531 break;
1532 case NVPTXISD::LDGV4:
1533 switch (EltVT.getSimpleVT().SimpleTy) {
1534 default:
1535 return nullptr;
1536 case MVT::i8:
1537 Opcode = NVPTX::INT_PTX_LDG_G_v4i8_ELE_ari64;
1538 break;
1539 case MVT::i16:
1540 Opcode = NVPTX::INT_PTX_LDG_G_v4i16_ELE_ari64;
1541 break;
1542 case MVT::i32:
1543 Opcode = NVPTX::INT_PTX_LDG_G_v4i32_ELE_ari64;
1544 break;
1545 case MVT::f32:
1546 Opcode = NVPTX::INT_PTX_LDG_G_v4f32_ELE_ari64;
1547 break;
1548 }
1549 break;
1550 case NVPTXISD::LDUV4:
1551 switch (EltVT.getSimpleVT().SimpleTy) {
1552 default:
1553 return nullptr;
1554 case MVT::i8:
1555 Opcode = NVPTX::INT_PTX_LDU_G_v4i8_ELE_ari64;
1556 break;
1557 case MVT::i16:
1558 Opcode = NVPTX::INT_PTX_LDU_G_v4i16_ELE_ari64;
1559 break;
1560 case MVT::i32:
1561 Opcode = NVPTX::INT_PTX_LDU_G_v4i32_ELE_ari64;
1562 break;
1563 case MVT::f32:
1564 Opcode = NVPTX::INT_PTX_LDU_G_v4f32_ELE_ari64;
1565 break;
1566 }
1567 break;
1568 }
1569 } else {
1570 switch (N->getOpcode()) {
1571 default:
1572 return nullptr;
1573 case ISD::INTRINSIC_W_CHAIN:
1574 if (IsLDG) {
1575 switch (EltVT.getSimpleVT().SimpleTy) {
1576 default:
1577 return nullptr;
1578 case MVT::i8:
1579 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i8ari;
1580 break;
1581 case MVT::i16:
1582 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i16ari;
1583 break;
1584 case MVT::i32:
1585 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i32ari;
1586 break;
1587 case MVT::i64:
1588 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i64ari;
1589 break;
1590 case MVT::f32:
1591 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_f32ari;
1592 break;
1593 case MVT::f64:
1594 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_f64ari;
1595 break;
1596 }
1597 } else {
1598 switch (EltVT.getSimpleVT().SimpleTy) {
1599 default:
1600 return nullptr;
1601 case MVT::i8:
1602 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i8ari;
1603 break;
1604 case MVT::i16:
1605 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i16ari;
1606 break;
1607 case MVT::i32:
1608 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i32ari;
1609 break;
1610 case MVT::i64:
1611 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i64ari;
1612 break;
1613 case MVT::f32:
1614 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_f32ari;
1615 break;
1616 case MVT::f64:
1617 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_f64ari;
1618 break;
1619 }
1620 }
1621 break;
1622 case NVPTXISD::LDGV2:
1623 switch (EltVT.getSimpleVT().SimpleTy) {
1624 default:
1625 return nullptr;
1626 case MVT::i8:
1627 Opcode = NVPTX::INT_PTX_LDG_G_v2i8_ELE_ari32;
1628 break;
1629 case MVT::i16:
1630 Opcode = NVPTX::INT_PTX_LDG_G_v2i16_ELE_ari32;
1631 break;
1632 case MVT::i32:
1633 Opcode = NVPTX::INT_PTX_LDG_G_v2i32_ELE_ari32;
1634 break;
1635 case MVT::i64:
1636 Opcode = NVPTX::INT_PTX_LDG_G_v2i64_ELE_ari32;
1637 break;
1638 case MVT::f32:
1639 Opcode = NVPTX::INT_PTX_LDG_G_v2f32_ELE_ari32;
1640 break;
1641 case MVT::f64:
1642 Opcode = NVPTX::INT_PTX_LDG_G_v2f64_ELE_ari32;
1643 break;
1644 }
1645 break;
1646 case NVPTXISD::LDUV2:
1647 switch (EltVT.getSimpleVT().SimpleTy) {
1648 default:
1649 return nullptr;
1650 case MVT::i8:
1651 Opcode = NVPTX::INT_PTX_LDU_G_v2i8_ELE_ari32;
1652 break;
1653 case MVT::i16:
1654 Opcode = NVPTX::INT_PTX_LDU_G_v2i16_ELE_ari32;
1655 break;
1656 case MVT::i32:
1657 Opcode = NVPTX::INT_PTX_LDU_G_v2i32_ELE_ari32;
1658 break;
1659 case MVT::i64:
1660 Opcode = NVPTX::INT_PTX_LDU_G_v2i64_ELE_ari32;
1661 break;
1662 case MVT::f32:
1663 Opcode = NVPTX::INT_PTX_LDU_G_v2f32_ELE_ari32;
1664 break;
1665 case MVT::f64:
1666 Opcode = NVPTX::INT_PTX_LDU_G_v2f64_ELE_ari32;
1667 break;
1668 }
1669 break;
1670 case NVPTXISD::LDGV4:
1671 switch (EltVT.getSimpleVT().SimpleTy) {
1672 default:
1673 return nullptr;
1674 case MVT::i8:
1675 Opcode = NVPTX::INT_PTX_LDG_G_v4i8_ELE_ari32;
1676 break;
1677 case MVT::i16:
1678 Opcode = NVPTX::INT_PTX_LDG_G_v4i16_ELE_ari32;
1679 break;
1680 case MVT::i32:
1681 Opcode = NVPTX::INT_PTX_LDG_G_v4i32_ELE_ari32;
1682 break;
1683 case MVT::f32:
1684 Opcode = NVPTX::INT_PTX_LDG_G_v4f32_ELE_ari32;
1685 break;
1686 }
1687 break;
1688 case NVPTXISD::LDUV4:
1689 switch (EltVT.getSimpleVT().SimpleTy) {
1690 default:
1691 return nullptr;
1692 case MVT::i8:
1693 Opcode = NVPTX::INT_PTX_LDU_G_v4i8_ELE_ari32;
1694 break;
1695 case MVT::i16:
1696 Opcode = NVPTX::INT_PTX_LDU_G_v4i16_ELE_ari32;
1697 break;
1698 case MVT::i32:
1699 Opcode = NVPTX::INT_PTX_LDU_G_v4i32_ELE_ari32;
1700 break;
1701 case MVT::f32:
1702 Opcode = NVPTX::INT_PTX_LDU_G_v4f32_ELE_ari32;
1703 break;
1704 }
1705 break;
1706 }
1707 }
1708
1709 SDValue Ops[] = { Base, Offset, Chain };
1710
1711 LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(), Ops);
1712 } else {
1713 if (Subtarget.is64Bit()) {
1714 switch (N->getOpcode()) {
1715 default:
1716 return nullptr;
1717 case ISD::INTRINSIC_W_CHAIN:
1718 if (IsLDG) {
1719 switch (EltVT.getSimpleVT().SimpleTy) {
1720 default:
1721 return nullptr;
1722 case MVT::i8:
1723 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i8areg64;
1724 break;
1725 case MVT::i16:
1726 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i16areg64;
1727 break;
1728 case MVT::i32:
1729 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i32areg64;
1730 break;
1731 case MVT::i64:
1732 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i64areg64;
1733 break;
1734 case MVT::f32:
1735 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_f32areg64;
1736 break;
1737 case MVT::f64:
1738 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_f64areg64;
1739 break;
1740 }
1741 } else {
1742 switch (EltVT.getSimpleVT().SimpleTy) {
1743 default:
1744 return nullptr;
1745 case MVT::i8:
1746 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i8areg64;
1747 break;
1748 case MVT::i16:
1749 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i16areg64;
1750 break;
1751 case MVT::i32:
1752 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i32areg64;
1753 break;
1754 case MVT::i64:
1755 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i64areg64;
1756 break;
1757 case MVT::f32:
1758 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_f32areg64;
1759 break;
1760 case MVT::f64:
1761 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_f64areg64;
1762 break;
1763 }
1764 }
1765 break;
1766 case NVPTXISD::LDGV2:
1767 switch (EltVT.getSimpleVT().SimpleTy) {
1768 default:
1769 return nullptr;
1770 case MVT::i8:
1771 Opcode = NVPTX::INT_PTX_LDG_G_v2i8_ELE_areg64;
1772 break;
1773 case MVT::i16:
1774 Opcode = NVPTX::INT_PTX_LDG_G_v2i16_ELE_areg64;
1775 break;
1776 case MVT::i32:
1777 Opcode = NVPTX::INT_PTX_LDG_G_v2i32_ELE_areg64;
1778 break;
1779 case MVT::i64:
1780 Opcode = NVPTX::INT_PTX_LDG_G_v2i64_ELE_areg64;
1781 break;
1782 case MVT::f32:
1783 Opcode = NVPTX::INT_PTX_LDG_G_v2f32_ELE_areg64;
1784 break;
1785 case MVT::f64:
1786 Opcode = NVPTX::INT_PTX_LDG_G_v2f64_ELE_areg64;
1787 break;
1788 }
1789 break;
1790 case NVPTXISD::LDUV2:
1791 switch (EltVT.getSimpleVT().SimpleTy) {
1792 default:
1793 return nullptr;
1794 case MVT::i8:
1795 Opcode = NVPTX::INT_PTX_LDU_G_v2i8_ELE_areg64;
1796 break;
1797 case MVT::i16:
1798 Opcode = NVPTX::INT_PTX_LDU_G_v2i16_ELE_areg64;
1799 break;
1800 case MVT::i32:
1801 Opcode = NVPTX::INT_PTX_LDU_G_v2i32_ELE_areg64;
1802 break;
1803 case MVT::i64:
1804 Opcode = NVPTX::INT_PTX_LDU_G_v2i64_ELE_areg64;
1805 break;
1806 case MVT::f32:
1807 Opcode = NVPTX::INT_PTX_LDU_G_v2f32_ELE_areg64;
1808 break;
1809 case MVT::f64:
1810 Opcode = NVPTX::INT_PTX_LDU_G_v2f64_ELE_areg64;
1811 break;
1812 }
1813 break;
1814 case NVPTXISD::LDGV4:
1815 switch (EltVT.getSimpleVT().SimpleTy) {
1816 default:
1817 return nullptr;
1818 case MVT::i8:
1819 Opcode = NVPTX::INT_PTX_LDG_G_v4i8_ELE_areg64;
1820 break;
1821 case MVT::i16:
1822 Opcode = NVPTX::INT_PTX_LDG_G_v4i16_ELE_areg64;
1823 break;
1824 case MVT::i32:
1825 Opcode = NVPTX::INT_PTX_LDG_G_v4i32_ELE_areg64;
1826 break;
1827 case MVT::f32:
1828 Opcode = NVPTX::INT_PTX_LDG_G_v4f32_ELE_areg64;
1829 break;
1830 }
1831 break;
1832 case NVPTXISD::LDUV4:
1833 switch (EltVT.getSimpleVT().SimpleTy) {
1834 default:
1835 return nullptr;
1836 case MVT::i8:
1837 Opcode = NVPTX::INT_PTX_LDU_G_v4i8_ELE_areg64;
1838 break;
1839 case MVT::i16:
1840 Opcode = NVPTX::INT_PTX_LDU_G_v4i16_ELE_areg64;
1841 break;
1842 case MVT::i32:
1843 Opcode = NVPTX::INT_PTX_LDU_G_v4i32_ELE_areg64;
1844 break;
1845 case MVT::f32:
1846 Opcode = NVPTX::INT_PTX_LDU_G_v4f32_ELE_areg64;
1847 break;
1848 }
1849 break;
1850 }
1851 } else {
1852 switch (N->getOpcode()) {
1853 default:
1854 return nullptr;
1855 case ISD::INTRINSIC_W_CHAIN:
1856 if (IsLDG) {
1857 switch (EltVT.getSimpleVT().SimpleTy) {
1858 default:
1859 return nullptr;
1860 case MVT::i8:
1861 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i8areg;
1862 break;
1863 case MVT::i16:
1864 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i16areg;
1865 break;
1866 case MVT::i32:
1867 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i32areg;
1868 break;
1869 case MVT::i64:
1870 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i64areg;
1871 break;
1872 case MVT::f32:
1873 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_f32areg;
1874 break;
1875 case MVT::f64:
1876 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_f64areg;
1877 break;
1878 }
1879 } else {
1880 switch (EltVT.getSimpleVT().SimpleTy) {
1881 default:
1882 return nullptr;
1883 case MVT::i8:
1884 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i8areg;
1885 break;
1886 case MVT::i16:
1887 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i16areg;
1888 break;
1889 case MVT::i32:
1890 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i32areg;
1891 break;
1892 case MVT::i64:
1893 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i64areg;
1894 break;
1895 case MVT::f32:
1896 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_f32areg;
1897 break;
1898 case MVT::f64:
1899 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_f64areg;
1900 break;
1901 }
1902 }
1903 break;
1904 case NVPTXISD::LDGV2:
1905 switch (EltVT.getSimpleVT().SimpleTy) {
1906 default:
1907 return nullptr;
1908 case MVT::i8:
1909 Opcode = NVPTX::INT_PTX_LDG_G_v2i8_ELE_areg32;
1910 break;
1911 case MVT::i16:
1912 Opcode = NVPTX::INT_PTX_LDG_G_v2i16_ELE_areg32;
1913 break;
1914 case MVT::i32:
1915 Opcode = NVPTX::INT_PTX_LDG_G_v2i32_ELE_areg32;
1916 break;
1917 case MVT::i64:
1918 Opcode = NVPTX::INT_PTX_LDG_G_v2i64_ELE_areg32;
1919 break;
1920 case MVT::f32:
1921 Opcode = NVPTX::INT_PTX_LDG_G_v2f32_ELE_areg32;
1922 break;
1923 case MVT::f64:
1924 Opcode = NVPTX::INT_PTX_LDG_G_v2f64_ELE_areg32;
1925 break;
1926 }
1927 break;
1928 case NVPTXISD::LDUV2:
1929 switch (EltVT.getSimpleVT().SimpleTy) {
1930 default:
1931 return nullptr;
1932 case MVT::i8:
1933 Opcode = NVPTX::INT_PTX_LDU_G_v2i8_ELE_areg32;
1934 break;
1935 case MVT::i16:
1936 Opcode = NVPTX::INT_PTX_LDU_G_v2i16_ELE_areg32;
1937 break;
1938 case MVT::i32:
1939 Opcode = NVPTX::INT_PTX_LDU_G_v2i32_ELE_areg32;
1940 break;
1941 case MVT::i64:
1942 Opcode = NVPTX::INT_PTX_LDU_G_v2i64_ELE_areg32;
1943 break;
1944 case MVT::f32:
1945 Opcode = NVPTX::INT_PTX_LDU_G_v2f32_ELE_areg32;
1946 break;
1947 case MVT::f64:
1948 Opcode = NVPTX::INT_PTX_LDU_G_v2f64_ELE_areg32;
1949 break;
1950 }
1951 break;
1952 case NVPTXISD::LDGV4:
1953 switch (EltVT.getSimpleVT().SimpleTy) {
1954 default:
1955 return nullptr;
1956 case MVT::i8:
1957 Opcode = NVPTX::INT_PTX_LDG_G_v4i8_ELE_areg32;
1958 break;
1959 case MVT::i16:
1960 Opcode = NVPTX::INT_PTX_LDG_G_v4i16_ELE_areg32;
1961 break;
1962 case MVT::i32:
1963 Opcode = NVPTX::INT_PTX_LDG_G_v4i32_ELE_areg32;
1964 break;
1965 case MVT::f32:
1966 Opcode = NVPTX::INT_PTX_LDG_G_v4f32_ELE_areg32;
1967 break;
1968 }
1969 break;
1970 case NVPTXISD::LDUV4:
1971 switch (EltVT.getSimpleVT().SimpleTy) {
1972 default:
1973 return nullptr;
1974 case MVT::i8:
1975 Opcode = NVPTX::INT_PTX_LDU_G_v4i8_ELE_areg32;
1976 break;
1977 case MVT::i16:
1978 Opcode = NVPTX::INT_PTX_LDU_G_v4i16_ELE_areg32;
1979 break;
1980 case MVT::i32:
1981 Opcode = NVPTX::INT_PTX_LDU_G_v4i32_ELE_areg32;
1982 break;
1983 case MVT::f32:
1984 Opcode = NVPTX::INT_PTX_LDU_G_v4f32_ELE_areg32;
1985 break;
1986 }
1987 break;
1988 }
1989 }
1990
1991 SDValue Ops[] = { Op1, Chain };
1992 LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(), Ops);
1993 }
1994
1995 MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
1996 MemRefs0[0] = Mem->getMemOperand();
1997 cast<MachineSDNode>(LD)->setMemRefs(MemRefs0, MemRefs0 + 1);
1998
1999 return LD;
2000}
2001
2002SDNode *NVPTXDAGToDAGISel::SelectStore(SDNode *N) {
2003 SDLoc dl(N);
2004 StoreSDNode *ST = cast<StoreSDNode>(N);
2005 EVT StoreVT = ST->getMemoryVT();
2006 SDNode *NVPTXST = nullptr;
2007
2008 // do not support pre/post inc/dec
2009 if (ST->isIndexed())
2010 return nullptr;
2011
2012 if (!StoreVT.isSimple())
2013 return nullptr;
2014
2015 // Address Space Setting
2016 unsigned int codeAddrSpace = getCodeAddrSpace(ST, Subtarget);
2017
2018 // Volatile Setting
2019 // - .volatile is only availalble for .global and .shared
2020 bool isVolatile = ST->isVolatile();
2021 if (codeAddrSpace != NVPTX::PTXLdStInstCode::GLOBAL &&
2022 codeAddrSpace != NVPTX::PTXLdStInstCode::SHARED &&
2023 codeAddrSpace != NVPTX::PTXLdStInstCode::GENERIC)
2024 isVolatile = false;
2025
2026 // Vector Setting
2027 MVT SimpleVT = StoreVT.getSimpleVT();
2028 unsigned vecType = NVPTX::PTXLdStInstCode::Scalar;
2029 if (SimpleVT.isVector()) {
2030 unsigned num = SimpleVT.getVectorNumElements();
2031 if (num == 2)
2032 vecType = NVPTX::PTXLdStInstCode::V2;
2033 else if (num == 4)
2034 vecType = NVPTX::PTXLdStInstCode::V4;
2035 else
2036 return nullptr;
2037 }
2038
2039 // Type Setting: toType + toTypeWidth
2040 // - for integer type, always use 'u'
2041 //
2042 MVT ScalarVT = SimpleVT.getScalarType();
2043 unsigned toTypeWidth = ScalarVT.getSizeInBits();
2044 unsigned int toType;
2045 if (ScalarVT.isFloatingPoint())
2046 toType = NVPTX::PTXLdStInstCode::Float;
2047 else
2048 toType = NVPTX::PTXLdStInstCode::Unsigned;
2049
2050 // Create the machine instruction DAG
2051 SDValue Chain = N->getOperand(0);
2052 SDValue N1 = N->getOperand(1);
2053 SDValue N2 = N->getOperand(2);
2054 SDValue Addr;
2055 SDValue Offset, Base;
2056 unsigned Opcode;
2057 MVT::SimpleValueType SourceVT = N1.getNode()->getSimpleValueType(0).SimpleTy;
2058
2059 if (SelectDirectAddr(N2, Addr)) {
2060 switch (SourceVT) {
2061 case MVT::i8:
2062 Opcode = NVPTX::ST_i8_avar;
2063 break;
2064 case MVT::i16:
2065 Opcode = NVPTX::ST_i16_avar;
2066 break;
2067 case MVT::i32:
2068 Opcode = NVPTX::ST_i32_avar;
2069 break;
2070 case MVT::i64:
2071 Opcode = NVPTX::ST_i64_avar;
2072 break;
2073 case MVT::f32:
2074 Opcode = NVPTX::ST_f32_avar;
2075 break;
2076 case MVT::f64:
2077 Opcode = NVPTX::ST_f64_avar;
2078 break;
2079 default:
2080 return nullptr;
2081 }
2082 SDValue Ops[] = { N1, getI32Imm(isVolatile), getI32Imm(codeAddrSpace),
2083 getI32Imm(vecType), getI32Imm(toType),
2084 getI32Imm(toTypeWidth), Addr, Chain };
2085 NVPTXST = CurDAG->getMachineNode(Opcode, dl, MVT::Other, Ops);
2086 } else if (Subtarget.is64Bit()
2087 ? SelectADDRsi64(N2.getNode(), N2, Base, Offset)
2088 : SelectADDRsi(N2.getNode(), N2, Base, Offset)) {
2089 switch (SourceVT) {
2090 case MVT::i8:
2091 Opcode = NVPTX::ST_i8_asi;
2092 break;
2093 case MVT::i16:
2094 Opcode = NVPTX::ST_i16_asi;
2095 break;
2096 case MVT::i32:
2097 Opcode = NVPTX::ST_i32_asi;
2098 break;
2099 case MVT::i64:
2100 Opcode = NVPTX::ST_i64_asi;
2101 break;
2102 case MVT::f32:
2103 Opcode = NVPTX::ST_f32_asi;
2104 break;
2105 case MVT::f64:
2106 Opcode = NVPTX::ST_f64_asi;
2107 break;
2108 default:
2109 return nullptr;
2110 }
2111 SDValue Ops[] = { N1, getI32Imm(isVolatile), getI32Imm(codeAddrSpace),
2112 getI32Imm(vecType), getI32Imm(toType),
2113 getI32Imm(toTypeWidth), Base, Offset, Chain };
2114 NVPTXST = CurDAG->getMachineNode(Opcode, dl, MVT::Other, Ops);
2115 } else if (Subtarget.is64Bit()
2116 ? SelectADDRri64(N2.getNode(), N2, Base, Offset)
2117 : SelectADDRri(N2.getNode(), N2, Base, Offset)) {
2118 if (Subtarget.is64Bit()) {
2119 switch (SourceVT) {
2120 case MVT::i8:
2121 Opcode = NVPTX::ST_i8_ari_64;
2122 break;
2123 case MVT::i16:
2124 Opcode = NVPTX::ST_i16_ari_64;
2125 break;
2126 case MVT::i32:
2127 Opcode = NVPTX::ST_i32_ari_64;
2128 break;
2129 case MVT::i64:
2130 Opcode = NVPTX::ST_i64_ari_64;
2131 break;
2132 case MVT::f32:
2133 Opcode = NVPTX::ST_f32_ari_64;
2134 break;
2135 case MVT::f64:
2136 Opcode = NVPTX::ST_f64_ari_64;
2137 break;
2138 default:
2139 return nullptr;
2140 }
2141 } else {
2142 switch (SourceVT) {
2143 case MVT::i8:
2144 Opcode = NVPTX::ST_i8_ari;
2145 break;
2146 case MVT::i16:
2147 Opcode = NVPTX::ST_i16_ari;
2148 break;
2149 case MVT::i32:
2150 Opcode = NVPTX::ST_i32_ari;
2151 break;
2152 case MVT::i64:
2153 Opcode = NVPTX::ST_i64_ari;
2154 break;
2155 case MVT::f32:
2156 Opcode = NVPTX::ST_f32_ari;
2157 break;
2158 case MVT::f64:
2159 Opcode = NVPTX::ST_f64_ari;
2160 break;
2161 default:
2162 return nullptr;
2163 }
2164 }
2165 SDValue Ops[] = { N1, getI32Imm(isVolatile), getI32Imm(codeAddrSpace),
2166 getI32Imm(vecType), getI32Imm(toType),
2167 getI32Imm(toTypeWidth), Base, Offset, Chain };
2168 NVPTXST = CurDAG->getMachineNode(Opcode, dl, MVT::Other, Ops);
2169 } else {
2170 if (Subtarget.is64Bit()) {
2171 switch (SourceVT) {
2172 case MVT::i8:
2173 Opcode = NVPTX::ST_i8_areg_64;
2174 break;
2175 case MVT::i16:
2176 Opcode = NVPTX::ST_i16_areg_64;
2177 break;
2178 case MVT::i32:
2179 Opcode = NVPTX::ST_i32_areg_64;
2180 break;
2181 case MVT::i64:
2182 Opcode = NVPTX::ST_i64_areg_64;
2183 break;
2184 case MVT::f32:
2185 Opcode = NVPTX::ST_f32_areg_64;
2186 break;
2187 case MVT::f64:
2188 Opcode = NVPTX::ST_f64_areg_64;
2189 break;
2190 default:
2191 return nullptr;
2192 }
2193 } else {
2194 switch (SourceVT) {
2195 case MVT::i8:
2196 Opcode = NVPTX::ST_i8_areg;
2197 break;
2198 case MVT::i16:
2199 Opcode = NVPTX::ST_i16_areg;
2200 break;
2201 case MVT::i32:
2202 Opcode = NVPTX::ST_i32_areg;
2203 break;
2204 case MVT::i64:
2205 Opcode = NVPTX::ST_i64_areg;
2206 break;
2207 case MVT::f32:
2208 Opcode = NVPTX::ST_f32_areg;
2209 break;
2210 case MVT::f64:
2211 Opcode = NVPTX::ST_f64_areg;
2212 break;
2213 default:
2214 return nullptr;
2215 }
2216 }
2217 SDValue Ops[] = { N1, getI32Imm(isVolatile), getI32Imm(codeAddrSpace),
2218 getI32Imm(vecType), getI32Imm(toType),
2219 getI32Imm(toTypeWidth), N2, Chain };
2220 NVPTXST = CurDAG->getMachineNode(Opcode, dl, MVT::Other, Ops);
2221 }
2222
2223 if (NVPTXST) {
2224 MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
2225 MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
2226 cast<MachineSDNode>(NVPTXST)->setMemRefs(MemRefs0, MemRefs0 + 1);
2227 }
2228
2229 return NVPTXST;
2230}
2231
2232SDNode *NVPTXDAGToDAGISel::SelectStoreVector(SDNode *N) {
2233 SDValue Chain = N->getOperand(0);
2234 SDValue Op1 = N->getOperand(1);
2235 SDValue Addr, Offset, Base;
2236 unsigned Opcode;
2237 SDLoc DL(N);
2238 SDNode *ST;
2239 EVT EltVT = Op1.getValueType();
2240 MemSDNode *MemSD = cast<MemSDNode>(N);
2241 EVT StoreVT = MemSD->getMemoryVT();
2242
2243 // Address Space Setting
2244 unsigned CodeAddrSpace = getCodeAddrSpace(MemSD, Subtarget);
2245
2246 if (CodeAddrSpace == NVPTX::PTXLdStInstCode::CONSTANT) {
2247 report_fatal_error("Cannot store to pointer that points to constant "
2248 "memory space");
2249 }
2250
2251 // Volatile Setting
2252 // - .volatile is only availalble for .global and .shared
2253 bool IsVolatile = MemSD->isVolatile();
2254 if (CodeAddrSpace != NVPTX::PTXLdStInstCode::GLOBAL &&
2255 CodeAddrSpace != NVPTX::PTXLdStInstCode::SHARED &&
2256 CodeAddrSpace != NVPTX::PTXLdStInstCode::GENERIC)
2257 IsVolatile = false;
2258
2259 // Type Setting: toType + toTypeWidth
2260 // - for integer type, always use 'u'
2261 assert(StoreVT.isSimple() && "Store value is not simple")((StoreVT.isSimple() && "Store value is not simple") ?
static_cast<void> (0) : __assert_fail ("StoreVT.isSimple() && \"Store value is not simple\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.6~svn224369/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp"
, 2261, __PRETTY_FUNCTION__))
;
2262 MVT ScalarVT = StoreVT.getSimpleVT().getScalarType();
2263 unsigned ToTypeWidth = ScalarVT.getSizeInBits();
2264 unsigned ToType;
2265 if (ScalarVT.isFloatingPoint())
2266 ToType = NVPTX::PTXLdStInstCode::Float;
2267 else
2268 ToType = NVPTX::PTXLdStInstCode::Unsigned;
2269
2270 SmallVector<SDValue, 12> StOps;
2271 SDValue N2;
2272 unsigned VecType;
2273
2274 switch (N->getOpcode()) {
2275 case NVPTXISD::StoreV2:
2276 VecType = NVPTX::PTXLdStInstCode::V2;
2277 StOps.push_back(N->getOperand(1));
2278 StOps.push_back(N->getOperand(2));
2279 N2 = N->getOperand(3);
2280 break;
2281 case NVPTXISD::StoreV4:
2282 VecType = NVPTX::PTXLdStInstCode::V4;
2283 StOps.push_back(N->getOperand(1));
2284 StOps.push_back(N->getOperand(2));
2285 StOps.push_back(N->getOperand(3));
2286 StOps.push_back(N->getOperand(4));
2287 N2 = N->getOperand(5);
2288 break;
2289 default:
2290 return nullptr;
2291 }
2292
2293 StOps.push_back(getI32Imm(IsVolatile));
2294 StOps.push_back(getI32Imm(CodeAddrSpace));
2295 StOps.push_back(getI32Imm(VecType));
2296 StOps.push_back(getI32Imm(ToType));
2297 StOps.push_back(getI32Imm(ToTypeWidth));
2298
2299 if (SelectDirectAddr(N2, Addr)) {
2300 switch (N->getOpcode()) {
2301 default:
2302 return nullptr;
2303 case NVPTXISD::StoreV2:
2304 switch (EltVT.getSimpleVT().SimpleTy) {
2305 default:
2306 return nullptr;
2307 case MVT::i8:
2308 Opcode = NVPTX::STV_i8_v2_avar;
2309 break;
2310 case MVT::i16:
2311 Opcode = NVPTX::STV_i16_v2_avar;
2312 break;
2313 case MVT::i32:
2314 Opcode = NVPTX::STV_i32_v2_avar;
2315 break;
2316 case MVT::i64:
2317 Opcode = NVPTX::STV_i64_v2_avar;
2318 break;
2319 case MVT::f32:
2320 Opcode = NVPTX::STV_f32_v2_avar;
2321 break;
2322 case MVT::f64:
2323 Opcode = NVPTX::STV_f64_v2_avar;
2324 break;
2325 }
2326 break;
2327 case NVPTXISD::StoreV4:
2328 switch (EltVT.getSimpleVT().SimpleTy) {
2329 default:
2330 return nullptr;
2331 case MVT::i8:
2332 Opcode = NVPTX::STV_i8_v4_avar;
2333 break;
2334 case MVT::i16:
2335 Opcode = NVPTX::STV_i16_v4_avar;
2336 break;
2337 case MVT::i32:
2338 Opcode = NVPTX::STV_i32_v4_avar;
2339 break;
2340 case MVT::f32:
2341 Opcode = NVPTX::STV_f32_v4_avar;
2342 break;
2343 }
2344 break;
2345 }
2346 StOps.push_back(Addr);
2347 } else if (Subtarget.is64Bit()
2348 ? SelectADDRsi64(N2.getNode(), N2, Base, Offset)
2349 : SelectADDRsi(N2.getNode(), N2, Base, Offset)) {
2350 switch (N->getOpcode()) {
2351 default:
2352 return nullptr;
2353 case NVPTXISD::StoreV2:
2354 switch (EltVT.getSimpleVT().SimpleTy) {
2355 default:
2356 return nullptr;
2357 case MVT::i8:
2358 Opcode = NVPTX::STV_i8_v2_asi;
2359 break;
2360 case MVT::i16:
2361 Opcode = NVPTX::STV_i16_v2_asi;
2362 break;
2363 case MVT::i32:
2364 Opcode = NVPTX::STV_i32_v2_asi;
2365 break;
2366 case MVT::i64:
2367 Opcode = NVPTX::STV_i64_v2_asi;
2368 break;
2369 case MVT::f32:
2370 Opcode = NVPTX::STV_f32_v2_asi;
2371 break;
2372 case MVT::f64:
2373 Opcode = NVPTX::STV_f64_v2_asi;
2374 break;
2375 }
2376 break;
2377 case NVPTXISD::StoreV4:
2378 switch (EltVT.getSimpleVT().SimpleTy) {
2379 default:
2380 return nullptr;
2381 case MVT::i8:
2382 Opcode = NVPTX::STV_i8_v4_asi;
2383 break;
2384 case MVT::i16:
2385 Opcode = NVPTX::STV_i16_v4_asi;
2386 break;
2387 case MVT::i32:
2388 Opcode = NVPTX::STV_i32_v4_asi;
2389 break;
2390 case MVT::f32:
2391 Opcode = NVPTX::STV_f32_v4_asi;
2392 break;
2393 }
2394 break;
2395 }
2396 StOps.push_back(Base);
2397 StOps.push_back(Offset);
2398 } else if (Subtarget.is64Bit()
2399 ? SelectADDRri64(N2.getNode(), N2, Base, Offset)
2400 : SelectADDRri(N2.getNode(), N2, Base, Offset)) {
2401 if (Subtarget.is64Bit()) {
2402 switch (N->getOpcode()) {
2403 default:
2404 return nullptr;
2405 case NVPTXISD::StoreV2:
2406 switch (EltVT.getSimpleVT().SimpleTy) {
2407 default:
2408 return nullptr;
2409 case MVT::i8:
2410 Opcode = NVPTX::STV_i8_v2_ari_64;
2411 break;
2412 case MVT::i16:
2413 Opcode = NVPTX::STV_i16_v2_ari_64;
2414 break;
2415 case MVT::i32:
2416 Opcode = NVPTX::STV_i32_v2_ari_64;
2417 break;
2418 case MVT::i64:
2419 Opcode = NVPTX::STV_i64_v2_ari_64;
2420 break;
2421 case MVT::f32:
2422 Opcode = NVPTX::STV_f32_v2_ari_64;
2423 break;
2424 case MVT::f64:
2425 Opcode = NVPTX::STV_f64_v2_ari_64;
2426 break;
2427 }
2428 break;
2429 case NVPTXISD::StoreV4:
2430 switch (EltVT.getSimpleVT().SimpleTy) {
2431 default:
2432 return nullptr;
2433 case MVT::i8:
2434 Opcode = NVPTX::STV_i8_v4_ari_64;
2435 break;
2436 case MVT::i16:
2437 Opcode = NVPTX::STV_i16_v4_ari_64;
2438 break;
2439 case MVT::i32:
2440 Opcode = NVPTX::STV_i32_v4_ari_64;
2441 break;
2442 case MVT::f32:
2443 Opcode = NVPTX::STV_f32_v4_ari_64;
2444 break;
2445 }
2446 break;
2447 }
2448 } else {
2449 switch (N->getOpcode()) {
2450 default:
2451 return nullptr;
2452 case NVPTXISD::StoreV2:
2453 switch (EltVT.getSimpleVT().SimpleTy) {
2454 default:
2455 return nullptr;
2456 case MVT::i8:
2457 Opcode = NVPTX::STV_i8_v2_ari;
2458 break;
2459 case MVT::i16:
2460 Opcode = NVPTX::STV_i16_v2_ari;
2461 break;
2462 case MVT::i32:
2463 Opcode = NVPTX::STV_i32_v2_ari;
2464 break;
2465 case MVT::i64:
2466 Opcode = NVPTX::STV_i64_v2_ari;
2467 break;
2468 case MVT::f32:
2469 Opcode = NVPTX::STV_f32_v2_ari;
2470 break;
2471 case MVT::f64:
2472 Opcode = NVPTX::STV_f64_v2_ari;
2473 break;
2474 }
2475 break;
2476 case NVPTXISD::StoreV4:
2477 switch (EltVT.getSimpleVT().SimpleTy) {
2478 default:
2479 return nullptr;
2480 case MVT::i8:
2481 Opcode = NVPTX::STV_i8_v4_ari;
2482 break;
2483 case MVT::i16:
2484 Opcode = NVPTX::STV_i16_v4_ari;
2485 break;
2486 case MVT::i32:
2487 Opcode = NVPTX::STV_i32_v4_ari;
2488 break;
2489 case MVT::f32:
2490 Opcode = NVPTX::STV_f32_v4_ari;
2491 break;
2492 }
2493 break;
2494 }
2495 }
2496 StOps.push_back(Base);
2497 StOps.push_back(Offset);
2498 } else {
2499 if (Subtarget.is64Bit()) {
2500 switch (N->getOpcode()) {
2501 default:
2502 return nullptr;
2503 case NVPTXISD::StoreV2:
2504 switch (EltVT.getSimpleVT().SimpleTy) {
2505 default:
2506 return nullptr;
2507 case MVT::i8:
2508 Opcode = NVPTX::STV_i8_v2_areg_64;
2509 break;
2510 case MVT::i16:
2511 Opcode = NVPTX::STV_i16_v2_areg_64;
2512 break;
2513 case MVT::i32:
2514 Opcode = NVPTX::STV_i32_v2_areg_64;
2515 break;
2516 case MVT::i64:
2517 Opcode = NVPTX::STV_i64_v2_areg_64;
2518 break;
2519 case MVT::f32:
2520 Opcode = NVPTX::STV_f32_v2_areg_64;
2521 break;
2522 case MVT::f64:
2523 Opcode = NVPTX::STV_f64_v2_areg_64;
2524 break;
2525 }
2526 break;
2527 case NVPTXISD::StoreV4:
2528 switch (EltVT.getSimpleVT().SimpleTy) {
2529 default:
2530 return nullptr;
2531 case MVT::i8:
2532 Opcode = NVPTX::STV_i8_v4_areg_64;
2533 break;
2534 case MVT::i16:
2535 Opcode = NVPTX::STV_i16_v4_areg_64;
2536 break;
2537 case MVT::i32:
2538 Opcode = NVPTX::STV_i32_v4_areg_64;
2539 break;
2540 case MVT::f32:
2541 Opcode = NVPTX::STV_f32_v4_areg_64;
2542 break;
2543 }
2544 break;
2545 }
2546 } else {
2547 switch (N->getOpcode()) {
2548 default:
2549 return nullptr;
2550 case NVPTXISD::StoreV2:
2551 switch (EltVT.getSimpleVT().SimpleTy) {
2552 default:
2553 return nullptr;
2554 case MVT::i8:
2555 Opcode = NVPTX::STV_i8_v2_areg;
2556 break;
2557 case MVT::i16:
2558 Opcode = NVPTX::STV_i16_v2_areg;
2559 break;
2560 case MVT::i32:
2561 Opcode = NVPTX::STV_i32_v2_areg;
2562 break;
2563 case MVT::i64:
2564 Opcode = NVPTX::STV_i64_v2_areg;
2565 break;
2566 case MVT::f32:
2567 Opcode = NVPTX::STV_f32_v2_areg;
2568 break;
2569 case MVT::f64:
2570 Opcode = NVPTX::STV_f64_v2_areg;
2571 break;
2572 }
2573 break;
2574 case NVPTXISD::StoreV4:
2575 switch (EltVT.getSimpleVT().SimpleTy) {
2576 default:
2577 return nullptr;
2578 case MVT::i8:
2579 Opcode = NVPTX::STV_i8_v4_areg;
2580 break;
2581 case MVT::i16:
2582 Opcode = NVPTX::STV_i16_v4_areg;
2583 break;
2584 case MVT::i32:
2585 Opcode = NVPTX::STV_i32_v4_areg;
2586 break;
2587 case MVT::f32:
2588 Opcode = NVPTX::STV_f32_v4_areg;
2589 break;
2590 }
2591 break;
2592 }
2593 }
2594 StOps.push_back(N2);
2595 }
2596
2597 StOps.push_back(Chain);
2598
2599 ST = CurDAG->getMachineNode(Opcode, DL, MVT::Other, StOps);
2600
2601 MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
2602 MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
2603 cast<MachineSDNode>(ST)->setMemRefs(MemRefs0, MemRefs0 + 1);
2604
2605 return ST;
2606}
2607
2608SDNode *NVPTXDAGToDAGISel::SelectLoadParam(SDNode *Node) {
2609 SDValue Chain = Node->getOperand(0);
2610 SDValue Offset = Node->getOperand(2);
2611 SDValue Flag = Node->getOperand(3);
2612 SDLoc DL(Node);
2613 MemSDNode *Mem = cast<MemSDNode>(Node);
2614
2615 unsigned VecSize;
2616 switch (Node->getOpcode()) {
2617 default:
2618 return nullptr;
2619 case NVPTXISD::LoadParam:
2620 VecSize = 1;
2621 break;
2622 case NVPTXISD::LoadParamV2:
2623 VecSize = 2;
2624 break;
2625 case NVPTXISD::LoadParamV4:
2626 VecSize = 4;
2627 break;
2628 }
2629
2630 EVT EltVT = Node->getValueType(0);
2631 EVT MemVT = Mem->getMemoryVT();
2632
2633 unsigned Opc = 0;
2634
2635 switch (VecSize) {
2636 default:
2637 return nullptr;
2638 case 1:
2639 switch (MemVT.getSimpleVT().SimpleTy) {
2640 default:
2641 return nullptr;
2642 case MVT::i1:
2643 Opc = NVPTX::LoadParamMemI8;
2644 break;
2645 case MVT::i8:
2646 Opc = NVPTX::LoadParamMemI8;
2647 break;
2648 case MVT::i16:
2649 Opc = NVPTX::LoadParamMemI16;
2650 break;
2651 case MVT::i32:
2652 Opc = NVPTX::LoadParamMemI32;
2653 break;
2654 case MVT::i64:
2655 Opc = NVPTX::LoadParamMemI64;
2656 break;
2657 case MVT::f32:
2658 Opc = NVPTX::LoadParamMemF32;
2659 break;
2660 case MVT::f64:
2661 Opc = NVPTX::LoadParamMemF64;
2662 break;
2663 }
2664 break;
2665 case 2:
2666 switch (MemVT.getSimpleVT().SimpleTy) {
2667 default:
2668 return nullptr;
2669 case MVT::i1:
2670 Opc = NVPTX::LoadParamMemV2I8;
2671 break;
2672 case MVT::i8:
2673 Opc = NVPTX::LoadParamMemV2I8;
2674 break;
2675 case MVT::i16:
2676 Opc = NVPTX::LoadParamMemV2I16;
2677 break;
2678 case MVT::i32:
2679 Opc = NVPTX::LoadParamMemV2I32;
2680 break;
2681 case MVT::i64:
2682 Opc = NVPTX::LoadParamMemV2I64;
2683 break;
2684 case MVT::f32:
2685 Opc = NVPTX::LoadParamMemV2F32;
2686 break;
2687 case MVT::f64:
2688 Opc = NVPTX::LoadParamMemV2F64;
2689 break;
2690 }
2691 break;
2692 case 4:
2693 switch (MemVT.getSimpleVT().SimpleTy) {
2694 default:
2695 return nullptr;
2696 case MVT::i1:
2697 Opc = NVPTX::LoadParamMemV4I8;
2698 break;
2699 case MVT::i8:
2700 Opc = NVPTX::LoadParamMemV4I8;
2701 break;
2702 case MVT::i16:
2703 Opc = NVPTX::LoadParamMemV4I16;
2704 break;
2705 case MVT::i32:
2706 Opc = NVPTX::LoadParamMemV4I32;
2707 break;
2708 case MVT::f32:
2709 Opc = NVPTX::LoadParamMemV4F32;
2710 break;
2711 }
2712 break;
2713 }
2714
2715 SDVTList VTs;
2716 if (VecSize == 1) {
2717 VTs = CurDAG->getVTList(EltVT, MVT::Other, MVT::Glue);
2718 } else if (VecSize == 2) {
2719 VTs = CurDAG->getVTList(EltVT, EltVT, MVT::Other, MVT::Glue);
2720 } else {
2721 EVT EVTs[] = { EltVT, EltVT, EltVT, EltVT, MVT::Other, MVT::Glue };
2722 VTs = CurDAG->getVTList(EVTs);
2723 }
2724
2725 unsigned OffsetVal = cast<ConstantSDNode>(Offset)->getZExtValue();
2726
2727 SmallVector<SDValue, 2> Ops;
2728 Ops.push_back(CurDAG->getTargetConstant(OffsetVal, MVT::i32));
2729 Ops.push_back(Chain);
2730 Ops.push_back(Flag);
2731
2732 SDNode *Ret =
2733 CurDAG->getMachineNode(Opc, DL, VTs, Ops);
2734 return Ret;
2735}
2736
2737SDNode *NVPTXDAGToDAGISel::SelectStoreRetval(SDNode *N) {
2738 SDLoc DL(N);
2739 SDValue Chain = N->getOperand(0);
2740 SDValue Offset = N->getOperand(1);
2741 unsigned OffsetVal = cast<ConstantSDNode>(Offset)->getZExtValue();
2742 MemSDNode *Mem = cast<MemSDNode>(N);
2743
2744 // How many elements do we have?
2745 unsigned NumElts = 1;
2746 switch (N->getOpcode()) {
2747 default:
2748 return nullptr;
2749 case NVPTXISD::StoreRetval:
2750 NumElts = 1;
2751 break;
2752 case NVPTXISD::StoreRetvalV2:
2753 NumElts = 2;
2754 break;
2755 case NVPTXISD::StoreRetvalV4:
2756 NumElts = 4;
2757 break;
2758 }
2759
2760 // Build vector of operands
2761 SmallVector<SDValue, 6> Ops;
2762 for (unsigned i = 0; i < NumElts; ++i)
2763 Ops.push_back(N->getOperand(i + 2));
2764 Ops.push_back(CurDAG->getTargetConstant(OffsetVal, MVT::i32));
2765 Ops.push_back(Chain);
2766
2767 // Determine target opcode
2768 // If we have an i1, use an 8-bit store. The lowering code in
2769 // NVPTXISelLowering will have already emitted an upcast.
2770 unsigned Opcode = 0;
2771 switch (NumElts) {
2772 default:
2773 return nullptr;
2774 case 1:
2775 switch (Mem->getMemoryVT().getSimpleVT().SimpleTy) {
2776 default:
2777 return nullptr;
2778 case MVT::i1:
2779 Opcode = NVPTX::StoreRetvalI8;
2780 break;
2781 case MVT::i8:
2782 Opcode = NVPTX::StoreRetvalI8;
2783 break;
2784 case MVT::i16:
2785 Opcode = NVPTX::StoreRetvalI16;
2786 break;
2787 case MVT::i32:
2788 Opcode = NVPTX::StoreRetvalI32;
2789 break;
2790 case MVT::i64:
2791 Opcode = NVPTX::StoreRetvalI64;
2792 break;
2793 case MVT::f32:
2794 Opcode = NVPTX::StoreRetvalF32;
2795 break;
2796 case MVT::f64:
2797 Opcode = NVPTX::StoreRetvalF64;
2798 break;
2799 }
2800 break;
2801 case 2:
2802 switch (Mem->getMemoryVT().getSimpleVT().SimpleTy) {
2803 default:
2804 return nullptr;
2805 case MVT::i1:
2806 Opcode = NVPTX::StoreRetvalV2I8;
2807 break;
2808 case MVT::i8:
2809 Opcode = NVPTX::StoreRetvalV2I8;
2810 break;
2811 case MVT::i16:
2812 Opcode = NVPTX::StoreRetvalV2I16;
2813 break;
2814 case MVT::i32:
2815 Opcode = NVPTX::StoreRetvalV2I32;
2816 break;
2817 case MVT::i64:
2818 Opcode = NVPTX::StoreRetvalV2I64;
2819 break;
2820 case MVT::f32:
2821 Opcode = NVPTX::StoreRetvalV2F32;
2822 break;
2823 case MVT::f64:
2824 Opcode = NVPTX::StoreRetvalV2F64;
2825 break;
2826 }
2827 break;
2828 case 4:
2829 switch (Mem->getMemoryVT().getSimpleVT().SimpleTy) {
2830 default:
2831 return nullptr;
2832 case MVT::i1:
2833 Opcode = NVPTX::StoreRetvalV4I8;
2834 break;
2835 case MVT::i8:
2836 Opcode = NVPTX::StoreRetvalV4I8;
2837 break;
2838 case MVT::i16:
2839 Opcode = NVPTX::StoreRetvalV4I16;
2840 break;
2841 case MVT::i32:
2842 Opcode = NVPTX::StoreRetvalV4I32;
2843 break;
2844 case MVT::f32:
2845 Opcode = NVPTX::StoreRetvalV4F32;
2846 break;
2847 }
2848 break;
2849 }
2850
2851 SDNode *Ret =
2852 CurDAG->getMachineNode(Opcode, DL, MVT::Other, Ops);
2853 MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
2854 MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
2855 cast<MachineSDNode>(Ret)->setMemRefs(MemRefs0, MemRefs0 + 1);
2856
2857 return Ret;
2858}
2859
2860SDNode *NVPTXDAGToDAGISel::SelectStoreParam(SDNode *N) {
2861 SDLoc DL(N);
2862 SDValue Chain = N->getOperand(0);
2863 SDValue Param = N->getOperand(1);
2864 unsigned ParamVal = cast<ConstantSDNode>(Param)->getZExtValue();
2865 SDValue Offset = N->getOperand(2);
2866 unsigned OffsetVal = cast<ConstantSDNode>(Offset)->getZExtValue();
2867 MemSDNode *Mem = cast<MemSDNode>(N);
2868 SDValue Flag = N->getOperand(N->getNumOperands() - 1);
2869
2870 // How many elements do we have?
2871 unsigned NumElts = 1;
2872 switch (N->getOpcode()) {
2873 default:
2874 return nullptr;
2875 case NVPTXISD::StoreParamU32:
2876 case NVPTXISD::StoreParamS32:
2877 case NVPTXISD::StoreParam:
2878 NumElts = 1;
2879 break;
2880 case NVPTXISD::StoreParamV2:
2881 NumElts = 2;
2882 break;
2883 case NVPTXISD::StoreParamV4:
2884 NumElts = 4;
2885 break;
2886 }
2887
2888 // Build vector of operands
2889 SmallVector<SDValue, 8> Ops;
2890 for (unsigned i = 0; i < NumElts; ++i)
2891 Ops.push_back(N->getOperand(i + 3));
2892 Ops.push_back(CurDAG->getTargetConstant(ParamVal, MVT::i32));
2893 Ops.push_back(CurDAG->getTargetConstant(OffsetVal, MVT::i32));
2894 Ops.push_back(Chain);
2895 Ops.push_back(Flag);
2896
2897 // Determine target opcode
2898 // If we have an i1, use an 8-bit store. The lowering code in
2899 // NVPTXISelLowering will have already emitted an upcast.
2900 unsigned Opcode = 0;
2901 switch (N->getOpcode()) {
2902 default:
2903 switch (NumElts) {
2904 default:
2905 return nullptr;
2906 case 1:
2907 switch (Mem->getMemoryVT().getSimpleVT().SimpleTy) {
2908 default:
2909 return nullptr;
2910 case MVT::i1:
2911 Opcode = NVPTX::StoreParamI8;
2912 break;
2913 case MVT::i8:
2914 Opcode = NVPTX::StoreParamI8;
2915 break;
2916 case MVT::i16:
2917 Opcode = NVPTX::StoreParamI16;
2918 break;
2919 case MVT::i32:
2920 Opcode = NVPTX::StoreParamI32;
2921 break;
2922 case MVT::i64:
2923 Opcode = NVPTX::StoreParamI64;
2924 break;
2925 case MVT::f32:
2926 Opcode = NVPTX::StoreParamF32;
2927 break;
2928 case MVT::f64:
2929 Opcode = NVPTX::StoreParamF64;
2930 break;
2931 }
2932 break;
2933 case 2:
2934 switch (Mem->getMemoryVT().getSimpleVT().SimpleTy) {
2935 default:
2936 return nullptr;
2937 case MVT::i1:
2938 Opcode = NVPTX::StoreParamV2I8;
2939 break;
2940 case MVT::i8:
2941 Opcode = NVPTX::StoreParamV2I8;
2942 break;
2943 case MVT::i16:
2944 Opcode = NVPTX::StoreParamV2I16;
2945 break;
2946 case MVT::i32:
2947 Opcode = NVPTX::StoreParamV2I32;
2948 break;
2949 case MVT::i64:
2950 Opcode = NVPTX::StoreParamV2I64;
2951 break;
2952 case MVT::f32:
2953 Opcode = NVPTX::StoreParamV2F32;
2954 break;
2955 case MVT::f64:
2956 Opcode = NVPTX::StoreParamV2F64;
2957 break;
2958 }
2959 break;
2960 case 4:
2961 switch (Mem->getMemoryVT().getSimpleVT().SimpleTy) {
2962 default:
2963 return nullptr;
2964 case MVT::i1:
2965 Opcode = NVPTX::StoreParamV4I8;
2966 break;
2967 case MVT::i8:
2968 Opcode = NVPTX::StoreParamV4I8;
2969 break;
2970 case MVT::i16:
2971 Opcode = NVPTX::StoreParamV4I16;
2972 break;
2973 case MVT::i32:
2974 Opcode = NVPTX::StoreParamV4I32;
2975 break;
2976 case MVT::f32:
2977 Opcode = NVPTX::StoreParamV4F32;
2978 break;
2979 }
2980 break;
2981 }
2982 break;
2983 // Special case: if we have a sign-extend/zero-extend node, insert the
2984 // conversion instruction first, and use that as the value operand to
2985 // the selected StoreParam node.
2986 case NVPTXISD::StoreParamU32: {
2987 Opcode = NVPTX::StoreParamI32;
2988 SDValue CvtNone = CurDAG->getTargetConstant(NVPTX::PTXCvtMode::NONE,
2989 MVT::i32);
2990 SDNode *Cvt = CurDAG->getMachineNode(NVPTX::CVT_u32_u16, DL,
2991 MVT::i32, Ops[0], CvtNone);
2992 Ops[0] = SDValue(Cvt, 0);
2993 break;
2994 }
2995 case NVPTXISD::StoreParamS32: {
2996 Opcode = NVPTX::StoreParamI32;
2997 SDValue CvtNone = CurDAG->getTargetConstant(NVPTX::PTXCvtMode::NONE,
2998 MVT::i32);
2999 SDNode *Cvt = CurDAG->getMachineNode(NVPTX::CVT_s32_s16, DL,
3000 MVT::i32, Ops[0], CvtNone);
3001 Ops[0] = SDValue(Cvt, 0);
3002 break;
3003 }
3004 }
3005
3006 SDVTList RetVTs = CurDAG->getVTList(MVT::Other, MVT::Glue);
3007 SDNode *Ret =
3008 CurDAG->getMachineNode(Opcode, DL, RetVTs, Ops);
3009 MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
3010 MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
3011 cast<MachineSDNode>(Ret)->setMemRefs(MemRefs0, MemRefs0 + 1);
3012
3013 return Ret;
3014}
3015
3016SDNode *NVPTXDAGToDAGISel::SelectTextureIntrinsic(SDNode *N) {
3017 SDValue Chain = N->getOperand(0);
3018 SDNode *Ret = nullptr;
3019 unsigned Opc = 0;
3020 SmallVector<SDValue, 8> Ops;
3021
3022 switch (N->getOpcode()) {
3023 default: return nullptr;
3024 case NVPTXISD::Tex1DFloatS32:
3025 Opc = NVPTX::TEX_1D_F32_S32;
3026 break;
3027 case NVPTXISD::Tex1DFloatFloat:
3028 Opc = NVPTX::TEX_1D_F32_F32;
3029 break;
3030 case NVPTXISD::Tex1DFloatFloatLevel:
3031 Opc = NVPTX::TEX_1D_F32_F32_LEVEL;
3032 break;
3033 case NVPTXISD::Tex1DFloatFloatGrad:
3034 Opc = NVPTX::TEX_1D_F32_F32_GRAD;
3035 break;
3036 case NVPTXISD::Tex1DS32S32:
3037 Opc = NVPTX::TEX_1D_S32_S32;
3038 break;
3039 case NVPTXISD::Tex1DS32Float:
3040 Opc = NVPTX::TEX_1D_S32_F32;
3041 break;
3042 case NVPTXISD::Tex1DS32FloatLevel:
3043 Opc = NVPTX::TEX_1D_S32_F32_LEVEL;
3044 break;
3045 case NVPTXISD::Tex1DS32FloatGrad:
3046 Opc = NVPTX::TEX_1D_S32_F32_GRAD;
3047 break;
3048 case NVPTXISD::Tex1DU32S32:
3049 Opc = NVPTX::TEX_1D_U32_S32;
3050 break;
3051 case NVPTXISD::Tex1DU32Float:
3052 Opc = NVPTX::TEX_1D_U32_F32;
3053 break;
3054 case NVPTXISD::Tex1DU32FloatLevel:
3055 Opc = NVPTX::TEX_1D_U32_F32_LEVEL;
3056 break;
3057 case NVPTXISD::Tex1DU32FloatGrad:
3058 Opc = NVPTX::TEX_1D_U32_F32_GRAD;
3059 break;
3060 case NVPTXISD::Tex1DArrayFloatS32:
3061 Opc = NVPTX::TEX_1D_ARRAY_F32_S32;
3062 break;
3063 case NVPTXISD::Tex1DArrayFloatFloat:
3064 Opc = NVPTX::TEX_1D_ARRAY_F32_F32;
3065 break;
3066 case NVPTXISD::Tex1DArrayFloatFloatLevel:
3067 Opc = NVPTX::TEX_1D_ARRAY_F32_F32_LEVEL;
3068 break;
3069 case NVPTXISD::Tex1DArrayFloatFloatGrad:
3070 Opc = NVPTX::TEX_1D_ARRAY_F32_F32_GRAD;
3071 break;
3072 case NVPTXISD::Tex1DArrayS32S32:
3073 Opc = NVPTX::TEX_1D_ARRAY_S32_S32;
3074 break;
3075 case NVPTXISD::Tex1DArrayS32Float:
3076 Opc = NVPTX::TEX_1D_ARRAY_S32_F32;
3077 break;
3078 case NVPTXISD::Tex1DArrayS32FloatLevel:
3079 Opc = NVPTX::TEX_1D_ARRAY_S32_F32_LEVEL;
3080 break;
3081 case NVPTXISD::Tex1DArrayS32FloatGrad:
3082 Opc = NVPTX::TEX_1D_ARRAY_S32_F32_GRAD;
3083 break;
3084 case NVPTXISD::Tex1DArrayU32S32:
3085 Opc = NVPTX::TEX_1D_ARRAY_U32_S32;
3086 break;
3087 case NVPTXISD::Tex1DArrayU32Float:
3088 Opc = NVPTX::TEX_1D_ARRAY_U32_F32;
3089 break;
3090 case NVPTXISD::Tex1DArrayU32FloatLevel:
3091 Opc = NVPTX::TEX_1D_ARRAY_U32_F32_LEVEL;
3092 break;
3093 case NVPTXISD::Tex1DArrayU32FloatGrad:
3094 Opc = NVPTX::TEX_1D_ARRAY_U32_F32_GRAD;
3095 break;
3096 case NVPTXISD::Tex2DFloatS32:
3097 Opc = NVPTX::TEX_2D_F32_S32;
3098 break;
3099 case NVPTXISD::Tex2DFloatFloat:
3100 Opc = NVPTX::TEX_2D_F32_F32;
3101 break;
3102 case NVPTXISD::Tex2DFloatFloatLevel:
3103 Opc = NVPTX::TEX_2D_F32_F32_LEVEL;
3104 break;
3105 case NVPTXISD::Tex2DFloatFloatGrad:
3106 Opc = NVPTX::TEX_2D_F32_F32_GRAD;
3107 break;
3108 case NVPTXISD::Tex2DS32S32:
3109 Opc = NVPTX::TEX_2D_S32_S32;
3110 break;
3111 case NVPTXISD::Tex2DS32Float:
3112 Opc = NVPTX::TEX_2D_S32_F32;
3113 break;
3114 case NVPTXISD::Tex2DS32FloatLevel:
3115 Opc = NVPTX::TEX_2D_S32_F32_LEVEL;
3116 break;
3117 case NVPTXISD::Tex2DS32FloatGrad:
3118 Opc = NVPTX::TEX_2D_S32_F32_GRAD;
3119 break;
3120 case NVPTXISD::Tex2DU32S32:
3121 Opc = NVPTX::TEX_2D_U32_S32;
3122 break;
3123 case NVPTXISD::Tex2DU32Float:
3124 Opc = NVPTX::TEX_2D_U32_F32;
3125 break;
3126 case NVPTXISD::Tex2DU32FloatLevel:
3127 Opc = NVPTX::TEX_2D_U32_F32_LEVEL;
3128 break;
3129 case NVPTXISD::Tex2DU32FloatGrad:
3130 Opc = NVPTX::TEX_2D_U32_F32_GRAD;
3131 break;
3132 case NVPTXISD::Tex2DArrayFloatS32:
3133 Opc = NVPTX::TEX_2D_ARRAY_F32_S32;
3134 break;
3135 case NVPTXISD::Tex2DArrayFloatFloat:
3136 Opc = NVPTX::TEX_2D_ARRAY_F32_F32;
3137 break;
3138 case NVPTXISD::Tex2DArrayFloatFloatLevel:
3139 Opc = NVPTX::TEX_2D_ARRAY_F32_F32_LEVEL;
3140 break;
3141 case NVPTXISD::Tex2DArrayFloatFloatGrad:
3142 Opc = NVPTX::TEX_2D_ARRAY_F32_F32_GRAD;
3143 break;
3144 case NVPTXISD::Tex2DArrayS32S32:
3145 Opc = NVPTX::TEX_2D_ARRAY_S32_S32;
3146 break;
3147 case NVPTXISD::Tex2DArrayS32Float:
3148 Opc = NVPTX::TEX_2D_ARRAY_S32_F32;
3149 break;
3150 case NVPTXISD::Tex2DArrayS32FloatLevel:
3151 Opc = NVPTX::TEX_2D_ARRAY_S32_F32_LEVEL;
3152 break;
3153 case NVPTXISD::Tex2DArrayS32FloatGrad:
3154 Opc = NVPTX::TEX_2D_ARRAY_S32_F32_GRAD;
3155 break;
3156 case NVPTXISD::Tex2DArrayU32S32:
3157 Opc = NVPTX::TEX_2D_ARRAY_U32_S32;
3158 break;
3159 case NVPTXISD::Tex2DArrayU32Float:
3160 Opc = NVPTX::TEX_2D_ARRAY_U32_F32;
3161 break;
3162 case NVPTXISD::Tex2DArrayU32FloatLevel:
3163 Opc = NVPTX::TEX_2D_ARRAY_U32_F32_LEVEL;
3164 break;
3165 case NVPTXISD::Tex2DArrayU32FloatGrad:
3166 Opc = NVPTX::TEX_2D_ARRAY_U32_F32_GRAD;
3167 break;
3168 case NVPTXISD::Tex3DFloatS32:
3169 Opc = NVPTX::TEX_3D_F32_S32;
3170 break;
3171 case NVPTXISD::Tex3DFloatFloat:
3172 Opc = NVPTX::TEX_3D_F32_F32;
3173 break;
3174 case NVPTXISD::Tex3DFloatFloatLevel:
3175 Opc = NVPTX::TEX_3D_F32_F32_LEVEL;
3176 break;
3177 case NVPTXISD::Tex3DFloatFloatGrad:
3178 Opc = NVPTX::TEX_3D_F32_F32_GRAD;
3179 break;
3180 case NVPTXISD::Tex3DS32S32:
3181 Opc = NVPTX::TEX_3D_S32_S32;
3182 break;
3183 case NVPTXISD::Tex3DS32Float:
3184 Opc = NVPTX::TEX_3D_S32_F32;
3185 break;
3186 case NVPTXISD::Tex3DS32FloatLevel:
3187 Opc = NVPTX::TEX_3D_S32_F32_LEVEL;
3188 break;
3189 case NVPTXISD::Tex3DS32FloatGrad:
3190 Opc = NVPTX::TEX_3D_S32_F32_GRAD;
3191 break;
3192 case NVPTXISD::Tex3DU32S32:
3193 Opc = NVPTX::TEX_3D_U32_S32;
3194 break;
3195 case NVPTXISD::Tex3DU32Float:
3196 Opc = NVPTX::TEX_3D_U32_F32;
3197 break;
3198 case NVPTXISD::Tex3DU32FloatLevel:
3199 Opc = NVPTX::TEX_3D_U32_F32_LEVEL;
3200 break;
3201 case NVPTXISD::Tex3DU32FloatGrad:
3202 Opc = NVPTX::TEX_3D_U32_F32_GRAD;
3203 break;
3204 case NVPTXISD::TexCubeFloatFloat:
3205 Opc = NVPTX::TEX_CUBE_F32_F32;
3206 break;
3207 case NVPTXISD::TexCubeFloatFloatLevel:
3208 Opc = NVPTX::TEX_CUBE_F32_F32_LEVEL;
3209 break;
3210 case NVPTXISD::TexCubeS32Float:
3211 Opc = NVPTX::TEX_CUBE_S32_F32;
3212 break;
3213 case NVPTXISD::TexCubeS32FloatLevel:
3214 Opc = NVPTX::TEX_CUBE_S32_F32_LEVEL;
3215 break;
3216 case NVPTXISD::TexCubeU32Float:
3217 Opc = NVPTX::TEX_CUBE_U32_F32;
3218 break;
3219 case NVPTXISD::TexCubeU32FloatLevel:
3220 Opc = NVPTX::TEX_CUBE_U32_F32_LEVEL;
3221 break;
3222 case NVPTXISD::TexCubeArrayFloatFloat:
3223 Opc = NVPTX::TEX_CUBE_ARRAY_F32_F32;
3224 break;
3225 case NVPTXISD::TexCubeArrayFloatFloatLevel:
3226 Opc = NVPTX::TEX_CUBE_ARRAY_F32_F32_LEVEL;
3227 break;
3228 case NVPTXISD::TexCubeArrayS32Float:
3229 Opc = NVPTX::TEX_CUBE_ARRAY_S32_F32;
3230 break;
3231 case NVPTXISD::TexCubeArrayS32FloatLevel:
3232 Opc = NVPTX::TEX_CUBE_ARRAY_S32_F32_LEVEL;
3233 break;
3234 case NVPTXISD::TexCubeArrayU32Float:
3235 Opc = NVPTX::TEX_CUBE_ARRAY_U32_F32;
3236 break;
3237 case NVPTXISD::TexCubeArrayU32FloatLevel:
3238 Opc = NVPTX::TEX_CUBE_ARRAY_U32_F32_LEVEL;
3239 break;
3240 case NVPTXISD::Tld4R2DFloatFloat:
3241 Opc = NVPTX::TLD4_R_2D_F32_F32;
3242 break;
3243 case NVPTXISD::Tld4G2DFloatFloat:
3244 Opc = NVPTX::TLD4_G_2D_F32_F32;
3245 break;
3246 case NVPTXISD::Tld4B2DFloatFloat:
3247 Opc = NVPTX::TLD4_B_2D_F32_F32;
3248 break;
3249 case NVPTXISD::Tld4A2DFloatFloat:
3250 Opc = NVPTX::TLD4_A_2D_F32_F32;
3251 break;
3252 case NVPTXISD::Tld4R2DS64Float:
3253 Opc = NVPTX::TLD4_R_2D_S32_F32;
3254 break;
3255 case NVPTXISD::Tld4G2DS64Float:
3256 Opc = NVPTX::TLD4_G_2D_S32_F32;
3257 break;
3258 case NVPTXISD::Tld4B2DS64Float:
3259 Opc = NVPTX::TLD4_B_2D_S32_F32;
3260 break;
3261 case NVPTXISD::Tld4A2DS64Float:
3262 Opc = NVPTX::TLD4_A_2D_S32_F32;
3263 break;
3264 case NVPTXISD::Tld4R2DU64Float:
3265 Opc = NVPTX::TLD4_R_2D_U32_F32;
3266 break;
3267 case NVPTXISD::Tld4G2DU64Float:
3268 Opc = NVPTX::TLD4_G_2D_U32_F32;
3269 break;
3270 case NVPTXISD::Tld4B2DU64Float:
3271 Opc = NVPTX::TLD4_B_2D_U32_F32;
3272 break;
3273 case NVPTXISD::Tld4A2DU64Float:
3274 Opc = NVPTX::TLD4_A_2D_U32_F32;
3275 break;
3276 case NVPTXISD::TexUnified1DFloatS32:
3277 Opc = NVPTX::TEX_UNIFIED_1D_F32_S32;
3278 break;
3279 case NVPTXISD::TexUnified1DFloatFloat:
3280 Opc = NVPTX::TEX_UNIFIED_1D_F32_F32;
3281 break;
3282 case NVPTXISD::TexUnified1DFloatFloatLevel:
3283 Opc = NVPTX::TEX_UNIFIED_1D_F32_F32_LEVEL;
3284 break;
3285 case NVPTXISD::TexUnified1DFloatFloatGrad:
3286 Opc = NVPTX::TEX_UNIFIED_1D_F32_F32_GRAD;
3287 break;
3288 case NVPTXISD::TexUnified1DS32S32:
3289 Opc = NVPTX::TEX_UNIFIED_1D_S32_S32;
3290 break;
3291 case NVPTXISD::TexUnified1DS32Float:
3292 Opc = NVPTX::TEX_UNIFIED_1D_S32_F32;
3293 break;
3294 case NVPTXISD::TexUnified1DS32FloatLevel:
3295 Opc = NVPTX::TEX_UNIFIED_1D_S32_F32_LEVEL;
3296 break;
3297 case NVPTXISD::TexUnified1DS32FloatGrad:
3298 Opc = NVPTX::TEX_UNIFIED_1D_S32_F32_GRAD;
3299 break;
3300 case NVPTXISD::TexUnified1DU32S32:
3301 Opc = NVPTX::TEX_UNIFIED_1D_U32_S32;
3302 break;
3303 case NVPTXISD::TexUnified1DU32Float:
3304 Opc = NVPTX::TEX_UNIFIED_1D_U32_F32;
3305 break;
3306 case NVPTXISD::TexUnified1DU32FloatLevel:
3307 Opc = NVPTX::TEX_UNIFIED_1D_U32_F32_LEVEL;
3308 break;
3309 case NVPTXISD::TexUnified1DU32FloatGrad:
3310 Opc = NVPTX::TEX_UNIFIED_1D_U32_F32_GRAD;
3311 break;
3312 case NVPTXISD::TexUnified1DArrayFloatS32:
3313 Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_F32_S32;
3314 break;
3315 case NVPTXISD::TexUnified1DArrayFloatFloat:
3316 Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_F32_F32;
3317 break;
3318 case NVPTXISD::TexUnified1DArrayFloatFloatLevel:
3319 Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_F32_F32_LEVEL;
3320 break;
3321 case NVPTXISD::TexUnified1DArrayFloatFloatGrad:
3322 Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_F32_F32_GRAD;
3323 break;
3324 case NVPTXISD::TexUnified1DArrayS32S32:
3325 Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_S32_S32;
3326 break;
3327 case NVPTXISD::TexUnified1DArrayS32Float:
3328 Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_S32_F32;
3329 break;
3330 case NVPTXISD::TexUnified1DArrayS32FloatLevel:
3331 Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_S32_F32_LEVEL;
3332 break;
3333 case NVPTXISD::TexUnified1DArrayS32FloatGrad:
3334 Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_S32_F32_GRAD;
3335 break;
3336 case NVPTXISD::TexUnified1DArrayU32S32:
3337 Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_U32_S32;
3338 break;
3339 case NVPTXISD::TexUnified1DArrayU32Float:
3340 Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_U32_F32;
3341 break;
3342 case NVPTXISD::TexUnified1DArrayU32FloatLevel:
3343 Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_U32_F32_LEVEL;
3344 break;
3345 case NVPTXISD::TexUnified1DArrayU32FloatGrad:
3346 Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_U32_F32_GRAD;
3347 break;
3348 case NVPTXISD::TexUnified2DFloatS32:
3349 Opc = NVPTX::TEX_UNIFIED_2D_F32_S32;
3350 break;
3351 case NVPTXISD::TexUnified2DFloatFloat:
3352 Opc = NVPTX::TEX_UNIFIED_2D_F32_F32;
3353 break;
3354 case NVPTXISD::TexUnified2DFloatFloatLevel:
3355 Opc = NVPTX::TEX_UNIFIED_2D_F32_F32_LEVEL;
3356 break;
3357 case NVPTXISD::TexUnified2DFloatFloatGrad:
3358 Opc = NVPTX::TEX_UNIFIED_2D_F32_F32_GRAD;
3359 break;
3360 case NVPTXISD::TexUnified2DS32S32:
3361 Opc = NVPTX::TEX_UNIFIED_2D_S32_S32;
3362 break;
3363 case NVPTXISD::TexUnified2DS32Float:
3364 Opc = NVPTX::TEX_UNIFIED_2D_S32_F32;
3365 break;
3366 case NVPTXISD::TexUnified2DS32FloatLevel:
3367 Opc = NVPTX::TEX_UNIFIED_2D_S32_F32_LEVEL;
3368 break;
3369 case NVPTXISD::TexUnified2DS32FloatGrad:
3370 Opc = NVPTX::TEX_UNIFIED_2D_S32_F32_GRAD;
3371 break;
3372 case NVPTXISD::TexUnified2DU32S32:
3373 Opc = NVPTX::TEX_UNIFIED_2D_U32_S32;
3374 break;
3375 case NVPTXISD::TexUnified2DU32Float:
3376 Opc = NVPTX::TEX_UNIFIED_2D_U32_F32;
3377 break;
3378 case NVPTXISD::TexUnified2DU32FloatLevel:
3379 Opc = NVPTX::TEX_UNIFIED_2D_U32_F32_LEVEL;
3380 break;
3381 case NVPTXISD::TexUnified2DU32FloatGrad:
3382 Opc = NVPTX::TEX_UNIFIED_2D_U32_F32_GRAD;
3383 break;
3384 case NVPTXISD::TexUnified2DArrayFloatS32:
3385 Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_F32_S32;
3386 break;
3387 case NVPTXISD::TexUnified2DArrayFloatFloat:
3388 Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_F32_F32;
3389 break;
3390 case NVPTXISD::TexUnified2DArrayFloatFloatLevel:
3391 Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_F32_F32_LEVEL;
3392 break;
3393 case NVPTXISD::TexUnified2DArrayFloatFloatGrad:
3394 Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_F32_F32_GRAD;
3395 break;
3396 case NVPTXISD::TexUnified2DArrayS32S32:
3397 Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_S32_S32;
3398 break;
3399 case NVPTXISD::TexUnified2DArrayS32Float:
3400 Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_S32_F32;
3401 break;
3402 case NVPTXISD::TexUnified2DArrayS32FloatLevel:
3403 Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_S32_F32_LEVEL;
3404 break;
3405 case NVPTXISD::TexUnified2DArrayS32FloatGrad:
3406 Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_S32_F32_GRAD;
3407 break;
3408 case NVPTXISD::TexUnified2DArrayU32S32:
3409 Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_U32_S32;
3410 break;
3411 case NVPTXISD::TexUnified2DArrayU32Float:
3412 Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_U32_F32;
3413 break;
3414 case NVPTXISD::TexUnified2DArrayU32FloatLevel:
3415 Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_U32_F32_LEVEL;
3416 break;
3417 case NVPTXISD::TexUnified2DArrayU32FloatGrad:
3418 Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_U32_F32_GRAD;
3419 break;
3420 case NVPTXISD::TexUnified3DFloatS32:
3421 Opc = NVPTX::TEX_UNIFIED_3D_F32_S32;
3422 break;
3423 case NVPTXISD::TexUnified3DFloatFloat:
3424 Opc = NVPTX::TEX_UNIFIED_3D_F32_F32;
3425 break;
3426 case NVPTXISD::TexUnified3DFloatFloatLevel:
3427 Opc = NVPTX::TEX_UNIFIED_3D_F32_F32_LEVEL;
3428 break;
3429 case NVPTXISD::TexUnified3DFloatFloatGrad:
3430 Opc = NVPTX::TEX_UNIFIED_3D_F32_F32_GRAD;
3431 break;
3432 case NVPTXISD::TexUnified3DS32S32:
3433 Opc = NVPTX::TEX_UNIFIED_3D_S32_S32;
3434 break;
3435 case NVPTXISD::TexUnified3DS32Float:
3436 Opc = NVPTX::TEX_UNIFIED_3D_S32_F32;
3437 break;
3438 case NVPTXISD::TexUnified3DS32FloatLevel:
3439 Opc = NVPTX::TEX_UNIFIED_3D_S32_F32_LEVEL;
3440 break;
3441 case NVPTXISD::TexUnified3DS32FloatGrad:
3442 Opc = NVPTX::TEX_UNIFIED_3D_S32_F32_GRAD;
3443 break;
3444 case NVPTXISD::TexUnified3DU32S32:
3445 Opc = NVPTX::TEX_UNIFIED_3D_U32_S32;
3446 break;
3447 case NVPTXISD::TexUnified3DU32Float:
3448 Opc = NVPTX::TEX_UNIFIED_3D_U32_F32;
3449 break;
3450 case NVPTXISD::TexUnified3DU32FloatLevel:
3451 Opc = NVPTX::TEX_UNIFIED_3D_U32_F32_LEVEL;
3452 break;
3453 case NVPTXISD::TexUnified3DU32FloatGrad:
3454 Opc = NVPTX::TEX_UNIFIED_3D_U32_F32_GRAD;
3455 break;
3456 case NVPTXISD::TexUnifiedCubeFloatFloat:
3457 Opc = NVPTX::TEX_UNIFIED_CUBE_F32_F32;
3458 break;
3459 case NVPTXISD::TexUnifiedCubeFloatFloatLevel:
3460 Opc = NVPTX::TEX_UNIFIED_CUBE_F32_F32_LEVEL;
3461 break;
3462 case NVPTXISD::TexUnifiedCubeS32Float:
3463 Opc = NVPTX::TEX_UNIFIED_CUBE_S32_F32;
3464 break;
3465 case NVPTXISD::TexUnifiedCubeS32FloatLevel:
3466 Opc = NVPTX::TEX_UNIFIED_CUBE_S32_F32_LEVEL;
3467 break;
3468 case NVPTXISD::TexUnifiedCubeU32Float:
3469 Opc = NVPTX::TEX_UNIFIED_CUBE_U32_F32;
3470 break;
3471 case NVPTXISD::TexUnifiedCubeU32FloatLevel:
3472 Opc = NVPTX::TEX_UNIFIED_CUBE_U32_F32_LEVEL;
3473 break;
3474 case NVPTXISD::TexUnifiedCubeArrayFloatFloat:
3475 Opc = NVPTX::TEX_UNIFIED_CUBE_ARRAY_F32_F32;
3476 break;
3477 case NVPTXISD::TexUnifiedCubeArrayFloatFloatLevel:
3478 Opc = NVPTX::TEX_UNIFIED_CUBE_ARRAY_F32_F32_LEVEL;
3479 break;
3480 case NVPTXISD::TexUnifiedCubeArrayS32Float:
3481 Opc = NVPTX::TEX_UNIFIED_CUBE_ARRAY_S32_F32;
3482 break;
3483 case NVPTXISD::TexUnifiedCubeArrayS32FloatLevel:
3484 Opc = NVPTX::TEX_UNIFIED_CUBE_ARRAY_S32_F32_LEVEL;
3485 break;
3486 case NVPTXISD::TexUnifiedCubeArrayU32Float:
3487 Opc = NVPTX::TEX_UNIFIED_CUBE_ARRAY_U32_F32;
3488 break;
3489 case NVPTXISD::TexUnifiedCubeArrayU32FloatLevel:
3490 Opc = NVPTX::TEX_UNIFIED_CUBE_ARRAY_U32_F32_LEVEL;
3491 break;
3492 case NVPTXISD::Tld4UnifiedR2DFloatFloat:
3493 Opc = NVPTX::TLD4_UNIFIED_R_2D_F32_F32;
3494 break;
3495 case NVPTXISD::Tld4UnifiedG2DFloatFloat:
3496 Opc = NVPTX::TLD4_UNIFIED_G_2D_F32_F32;
3497 break;
3498 case NVPTXISD::Tld4UnifiedB2DFloatFloat:
3499 Opc = NVPTX::TLD4_UNIFIED_B_2D_F32_F32;
3500 break;
3501 case NVPTXISD::Tld4UnifiedA2DFloatFloat:
3502 Opc = NVPTX::TLD4_UNIFIED_A_2D_F32_F32;
3503 break;
3504 case NVPTXISD::Tld4UnifiedR2DS64Float:
3505 Opc = NVPTX::TLD4_UNIFIED_R_2D_S32_F32;
3506 break;
3507 case NVPTXISD::Tld4UnifiedG2DS64Float:
3508 Opc = NVPTX::TLD4_UNIFIED_G_2D_S32_F32;
3509 break;
3510 case NVPTXISD::Tld4UnifiedB2DS64Float:
3511 Opc = NVPTX::TLD4_UNIFIED_B_2D_S32_F32;
3512 break;
3513 case NVPTXISD::Tld4UnifiedA2DS64Float:
3514 Opc = NVPTX::TLD4_UNIFIED_A_2D_S32_F32;
3515 break;
3516 case NVPTXISD::Tld4UnifiedR2DU64Float:
3517 Opc = NVPTX::TLD4_UNIFIED_R_2D_U32_F32;
3518 break;
3519 case NVPTXISD::Tld4UnifiedG2DU64Float:
3520 Opc = NVPTX::TLD4_UNIFIED_G_2D_U32_F32;
3521 break;
3522 case NVPTXISD::Tld4UnifiedB2DU64Float:
3523 Opc = NVPTX::TLD4_UNIFIED_B_2D_U32_F32;
3524 break;
3525 case NVPTXISD::Tld4UnifiedA2DU64Float:
3526 Opc = NVPTX::TLD4_UNIFIED_A_2D_U32_F32;
3527 break;
3528 }
3529
3530 // Copy over operands
3531 for (unsigned i = 1; i < N->getNumOperands(); ++i) {
3532 Ops.push_back(N->getOperand(i));
3533 }
3534
3535 Ops.push_back(Chain);
3536 Ret = CurDAG->getMachineNode(Opc, SDLoc(N), N->getVTList(), Ops);
3537 return Ret;
3538}
3539
3540SDNode *NVPTXDAGToDAGISel::SelectSurfaceIntrinsic(SDNode *N) {
3541 SDValue Chain = N->getOperand(0);
3542 SDValue TexHandle = N->getOperand(1);
3543 SDNode *Ret = nullptr;
3544 unsigned Opc = 0;
3545 SmallVector<SDValue, 8> Ops;
3546 switch (N->getOpcode()) {
3547 default: return nullptr;
3548 case NVPTXISD::Suld1DI8Clamp:
3549 Opc = NVPTX::SULD_1D_I8_CLAMP;
3550 Ops.push_back(TexHandle);
3551 Ops.push_back(N->getOperand(2));
3552 Ops.push_back(Chain);
3553 break;
3554 case NVPTXISD::Suld1DI16Clamp:
3555 Opc = NVPTX::SULD_1D_I16_CLAMP;
3556 Ops.push_back(TexHandle);
3557 Ops.push_back(N->getOperand(2));
3558 Ops.push_back(Chain);
3559 break;
3560 case NVPTXISD::Suld1DI32Clamp:
3561 Opc = NVPTX::SULD_1D_I32_CLAMP;
3562 Ops.push_back(TexHandle);
3563 Ops.push_back(N->getOperand(2));
3564 Ops.push_back(Chain);
3565 break;
3566 case NVPTXISD::Suld1DI64Clamp:
3567 Opc = NVPTX::SULD_1D_I64_CLAMP;
3568 Ops.push_back(TexHandle);
3569 Ops.push_back(N->getOperand(2));
3570 Ops.push_back(Chain);
3571 break;
3572 case NVPTXISD::Suld1DV2I8Clamp:
3573 Opc = NVPTX::SULD_1D_V2I8_CLAMP;
3574 Ops.push_back(TexHandle);
3575 Ops.push_back(N->getOperand(2));
3576 Ops.push_back(Chain);
3577 break;
3578 case NVPTXISD::Suld1DV2I16Clamp:
3579 Opc = NVPTX::SULD_1D_V2I16_CLAMP;
3580 Ops.push_back(TexHandle);
3581 Ops.push_back(N->getOperand(2));
3582 Ops.push_back(Chain);
3583 break;
3584 case NVPTXISD::Suld1DV2I32Clamp:
3585 Opc = NVPTX::SULD_1D_V2I32_CLAMP;
3586 Ops.push_back(TexHandle);
3587 Ops.push_back(N->getOperand(2));
3588 Ops.push_back(Chain);
3589 break;
3590 case NVPTXISD::Suld1DV2I64Clamp:
3591 Opc = NVPTX::SULD_1D_V2I64_CLAMP;
3592 Ops.push_back(TexHandle);
3593 Ops.push_back(N->getOperand(2));
3594 Ops.push_back(Chain);
3595 break;
3596 case NVPTXISD::Suld1DV4I8Clamp:
3597 Opc = NVPTX::SULD_1D_V4I8_CLAMP;
3598 Ops.push_back(TexHandle);
3599 Ops.push_back(N->getOperand(2));
3600 Ops.push_back(Chain);
3601 break;
3602 case NVPTXISD::Suld1DV4I16Clamp:
3603 Opc = NVPTX::SULD_1D_V4I16_CLAMP;
3604 Ops.push_back(TexHandle);
3605 Ops.push_back(N->getOperand(2));
3606 Ops.push_back(Chain);
3607 break;
3608 case NVPTXISD::Suld1DV4I32Clamp:
3609 Opc = NVPTX::SULD_1D_V4I32_CLAMP;
3610 Ops.push_back(TexHandle);
3611 Ops.push_back(N->getOperand(2));
3612 Ops.push_back(Chain);
3613 break;
3614 case NVPTXISD::Suld1DArrayI8Clamp:
3615 Opc = NVPTX::SULD_1D_ARRAY_I8_CLAMP;
3616 Ops.push_back(TexHandle);
3617 Ops.push_back(N->getOperand(2));
3618 Ops.push_back(N->getOperand(3));
3619 Ops.push_back(Chain);
3620 break;
3621 case NVPTXISD::Suld1DArrayI16Clamp:
3622 Opc = NVPTX::SULD_1D_ARRAY_I16_CLAMP;
3623 Ops.push_back(TexHandle);
3624 Ops.push_back(N->getOperand(2));
3625 Ops.push_back(N->getOperand(3));
3626 Ops.push_back(Chain);
3627 break;
3628 case NVPTXISD::Suld1DArrayI32Clamp:
3629 Opc = NVPTX::SULD_1D_ARRAY_I32_CLAMP;
3630 Ops.push_back(TexHandle);
3631 Ops.push_back(N->getOperand(2));
3632 Ops.push_back(N->getOperand(3));
3633 Ops.push_back(Chain);
3634 break;
3635 case NVPTXISD::Suld1DArrayI64Clamp:
3636 Opc = NVPTX::SULD_1D_ARRAY_I64_CLAMP;
3637 Ops.push_back(TexHandle);
3638 Ops.push_back(N->getOperand(2));
3639 Ops.push_back(N->getOperand(3));
3640 Ops.push_back(Chain);
3641 break;
3642 case NVPTXISD::Suld1DArrayV2I8Clamp:
3643 Opc = NVPTX::SULD_1D_ARRAY_V2I8_CLAMP;
3644 Ops.push_back(TexHandle);
3645 Ops.push_back(N->getOperand(2));
3646 Ops.push_back(N->getOperand(3));
3647 Ops.push_back(Chain);
3648 break;
3649 case NVPTXISD::Suld1DArrayV2I16Clamp:
3650 Opc = NVPTX::SULD_1D_ARRAY_V2I16_CLAMP;
3651 Ops.push_back(TexHandle);
3652 Ops.push_back(N->getOperand(2));
3653 Ops.push_back(N->getOperand(3));
3654 Ops.push_back(Chain);
3655 break;
3656 case NVPTXISD::Suld1DArrayV2I32Clamp:
3657 Opc = NVPTX::SULD_1D_ARRAY_V2I32_CLAMP;
3658 Ops.push_back(TexHandle);
3659 Ops.push_back(N->getOperand(2));
3660 Ops.push_back(N->getOperand(3));
3661 Ops.push_back(Chain);
3662 break;
3663 case NVPTXISD::Suld1DArrayV2I64Clamp:
3664 Opc = NVPTX::SULD_1D_ARRAY_V2I64_CLAMP;
3665 Ops.push_back(TexHandle);
3666 Ops.push_back(N->getOperand(2));
3667 Ops.push_back(N->getOperand(3));
3668 Ops.push_back(Chain);
3669 break;
3670 case NVPTXISD::Suld1DArrayV4I8Clamp:
3671 Opc = NVPTX::SULD_1D_ARRAY_V4I8_CLAMP;
3672 Ops.push_back(TexHandle);
3673 Ops.push_back(N->getOperand(2));
3674 Ops.push_back(N->getOperand(3));
3675 Ops.push_back(Chain);
3676 break;
3677 case NVPTXISD::Suld1DArrayV4I16Clamp:
3678 Opc = NVPTX::SULD_1D_ARRAY_V4I16_CLAMP;
3679 Ops.push_back(TexHandle);
3680 Ops.push_back(N->getOperand(2));
3681 Ops.push_back(N->getOperand(3));
3682 Ops.push_back(Chain);
3683 break;
3684 case NVPTXISD::Suld1DArrayV4I32Clamp:
3685 Opc = NVPTX::SULD_1D_ARRAY_V4I32_CLAMP;
3686 Ops.push_back(TexHandle);
3687 Ops.push_back(N->getOperand(2));
3688 Ops.push_back(N->getOperand(3));
3689 Ops.push_back(Chain);
3690 break;
3691 case NVPTXISD::Suld2DI8Clamp:
3692 Opc = NVPTX::SULD_2D_I8_CLAMP;
3693 Ops.push_back(TexHandle);
3694 Ops.push_back(N->getOperand(2));
3695 Ops.push_back(N->getOperand(3));
3696 Ops.push_back(Chain);
3697 break;
3698 case NVPTXISD::Suld2DI16Clamp:
3699 Opc = NVPTX::SULD_2D_I16_CLAMP;
3700 Ops.push_back(TexHandle);
3701 Ops.push_back(N->getOperand(2));
3702 Ops.push_back(N->getOperand(3));
3703 Ops.push_back(Chain);
3704 break;
3705 case NVPTXISD::Suld2DI32Clamp:
3706 Opc = NVPTX::SULD_2D_I32_CLAMP;
3707 Ops.push_back(TexHandle);
3708 Ops.push_back(N->getOperand(2));
3709 Ops.push_back(N->getOperand(3));
3710 Ops.push_back(Chain);
3711 break;
3712 case NVPTXISD::Suld2DI64Clamp:
3713 Opc = NVPTX::SULD_2D_I64_CLAMP;
3714 Ops.push_back(TexHandle);
3715 Ops.push_back(N->getOperand(2));
3716 Ops.push_back(N->getOperand(3));
3717 Ops.push_back(Chain);
3718 break;
3719 case NVPTXISD::Suld2DV2I8Clamp:
3720 Opc = NVPTX::SULD_2D_V2I8_CLAMP;
3721 Ops.push_back(TexHandle);
3722 Ops.push_back(N->getOperand(2));
3723 Ops.push_back(N->getOperand(3));
3724 Ops.push_back(Chain);
3725 break;
3726 case NVPTXISD::Suld2DV2I16Clamp:
3727 Opc = NVPTX::SULD_2D_V2I16_CLAMP;
3728 Ops.push_back(TexHandle);
3729 Ops.push_back(N->getOperand(2));
3730 Ops.push_back(N->getOperand(3));
3731 Ops.push_back(Chain);
3732 break;
3733 case NVPTXISD::Suld2DV2I32Clamp:
3734 Opc = NVPTX::SULD_2D_V2I32_CLAMP;
3735 Ops.push_back(TexHandle);
3736 Ops.push_back(N->getOperand(2));
3737 Ops.push_back(N->getOperand(3));
3738 Ops.push_back(Chain);
3739 break;
3740 case NVPTXISD::Suld2DV2I64Clamp:
3741 Opc = NVPTX::SULD_2D_V2I64_CLAMP;
3742 Ops.push_back(TexHandle);
3743 Ops.push_back(N->getOperand(2));
3744 Ops.push_back(N->getOperand(3));
3745 Ops.push_back(Chain);
3746 break;
3747 case NVPTXISD::Suld2DV4I8Clamp:
3748 Opc = NVPTX::SULD_2D_V4I8_CLAMP;
3749 Ops.push_back(TexHandle);
3750 Ops.push_back(N->getOperand(2));
3751 Ops.push_back(N->getOperand(3));
3752 Ops.push_back(Chain);
3753 break;
3754 case NVPTXISD::Suld2DV4I16Clamp:
3755 Opc = NVPTX::SULD_2D_V4I16_CLAMP;
3756 Ops.push_back(TexHandle);
3757 Ops.push_back(N->getOperand(2));
3758 Ops.push_back(N->getOperand(3));
3759 Ops.push_back(Chain);
3760 break;
3761 case NVPTXISD::Suld2DV4I32Clamp:
3762 Opc = NVPTX::SULD_2D_V4I32_CLAMP;
3763 Ops.push_back(TexHandle);
3764 Ops.push_back(N->getOperand(2));
3765 Ops.push_back(N->getOperand(3));
3766 Ops.push_back(Chain);
3767 break;
3768 case NVPTXISD::Suld2DArrayI8Clamp:
3769 Opc = NVPTX::SULD_2D_ARRAY_I8_CLAMP;
3770 Ops.push_back(TexHandle);
3771 Ops.push_back(N->getOperand(2));
3772 Ops.push_back(N->getOperand(3));
3773 Ops.push_back(N->getOperand(4));
3774 Ops.push_back(Chain);
3775 break;
3776 case NVPTXISD::Suld2DArrayI16Clamp:
3777 Opc = NVPTX::SULD_2D_ARRAY_I16_CLAMP;
3778 Ops.push_back(TexHandle);
3779 Ops.push_back(N->getOperand(2));
3780 Ops.push_back(N->getOperand(3));
3781 Ops.push_back(N->getOperand(4));
3782 Ops.push_back(Chain);
3783 break;
3784 case NVPTXISD::Suld2DArrayI32Clamp:
3785 Opc = NVPTX::SULD_2D_ARRAY_I32_CLAMP;
3786 Ops.push_back(TexHandle);
3787 Ops.push_back(N->getOperand(2));
3788 Ops.push_back(N->getOperand(3));
3789 Ops.push_back(N->getOperand(4));
3790 Ops.push_back(Chain);
3791 break;
3792 case NVPTXISD::Suld2DArrayI64Clamp:
3793 Opc = NVPTX::SULD_2D_ARRAY_I64_CLAMP;
3794 Ops.push_back(TexHandle);
3795 Ops.push_back(N->getOperand(2));
3796 Ops.push_back(N->getOperand(3));
3797 Ops.push_back(N->getOperand(4));
3798 Ops.push_back(Chain);
3799 break;
3800 case NVPTXISD::Suld2DArrayV2I8Clamp:
3801 Opc = NVPTX::SULD_2D_ARRAY_V2I8_CLAMP;
3802 Ops.push_back(TexHandle);
3803 Ops.push_back(N->getOperand(2));
3804 Ops.push_back(N->getOperand(3));
3805 Ops.push_back(N->getOperand(4));
3806 Ops.push_back(Chain);
3807 break;
3808 case NVPTXISD::Suld2DArrayV2I16Clamp:
3809 Opc = NVPTX::SULD_2D_ARRAY_V2I16_CLAMP;
3810 Ops.push_back(TexHandle);
3811 Ops.push_back(N->getOperand(2));
3812 Ops.push_back(N->getOperand(3));
3813 Ops.push_back(N->getOperand(4));
3814 Ops.push_back(Chain);
3815 break;
3816 case NVPTXISD::Suld2DArrayV2I32Clamp:
3817 Opc = NVPTX::SULD_2D_ARRAY_V2I32_CLAMP;
3818 Ops.push_back(TexHandle);
3819 Ops.push_back(N->getOperand(2));
3820 Ops.push_back(N->getOperand(3));
3821 Ops.push_back(N->getOperand(4));
3822 Ops.push_back(Chain);
3823 break;
3824 case NVPTXISD::Suld2DArrayV2I64Clamp:
3825 Opc = NVPTX::SULD_2D_ARRAY_V2I64_CLAMP;
3826 Ops.push_back(TexHandle);
3827 Ops.push_back(N->getOperand(2));
3828 Ops.push_back(N->getOperand(3));
3829 Ops.push_back(N->getOperand(4));
3830 Ops.push_back(Chain);
3831 break;
3832 case NVPTXISD::Suld2DArrayV4I8Clamp:
3833 Opc = NVPTX::SULD_2D_ARRAY_V4I8_CLAMP;
3834 Ops.push_back(TexHandle);
3835 Ops.push_back(N->getOperand(2));
3836 Ops.push_back(N->getOperand(3));
3837 Ops.push_back(N->getOperand(4));
3838 Ops.push_back(Chain);
3839 break;
3840 case NVPTXISD::Suld2DArrayV4I16Clamp:
3841 Opc = NVPTX::SULD_2D_ARRAY_V4I16_CLAMP;
3842 Ops.push_back(TexHandle);
3843 Ops.push_back(N->getOperand(2));
3844 Ops.push_back(N->getOperand(3));
3845 Ops.push_back(N->getOperand(4));
3846 Ops.push_back(Chain);
3847 break;
3848 case NVPTXISD::Suld2DArrayV4I32Clamp:
3849 Opc = NVPTX::SULD_2D_ARRAY_V4I32_CLAMP;
3850 Ops.push_back(TexHandle);
3851 Ops.push_back(N->getOperand(2));
3852 Ops.push_back(N->getOperand(3));
3853 Ops.push_back(N->getOperand(4));
3854 Ops.push_back(Chain);
3855 break;
3856 case NVPTXISD::Suld3DI8Clamp:
3857 Opc = NVPTX::SULD_3D_I8_CLAMP;
3858 Ops.push_back(TexHandle);
3859 Ops.push_back(N->getOperand(2));
3860 Ops.push_back(N->getOperand(3));
3861 Ops.push_back(N->getOperand(4));
3862 Ops.push_back(Chain);
3863 break;
3864 case NVPTXISD::Suld3DI16Clamp:
3865 Opc = NVPTX::SULD_3D_I16_CLAMP;
3866 Ops.push_back(TexHandle);
3867 Ops.push_back(N->getOperand(2));
3868 Ops.push_back(N->getOperand(3));
3869 Ops.push_back(N->getOperand(4));
3870 Ops.push_back(Chain);
3871 break;
3872 case NVPTXISD::Suld3DI32Clamp:
3873 Opc = NVPTX::SULD_3D_I32_CLAMP;
3874 Ops.push_back(TexHandle);
3875 Ops.push_back(N->getOperand(2));
3876 Ops.push_back(N->getOperand(3));
3877 Ops.push_back(N->getOperand(4));
3878 Ops.push_back(Chain);
3879 break;
3880 case NVPTXISD::Suld3DI64Clamp:
3881 Opc = NVPTX::SULD_3D_I64_CLAMP;
3882 Ops.push_back(TexHandle);
3883 Ops.push_back(N->getOperand(2));
3884 Ops.push_back(N->getOperand(3));
3885 Ops.push_back(N->getOperand(4));
3886 Ops.push_back(Chain);
3887 break;
3888 case NVPTXISD::Suld3DV2I8Clamp:
3889 Opc = NVPTX::SULD_3D_V2I8_CLAMP;
3890 Ops.push_back(TexHandle);
3891 Ops.push_back(N->getOperand(2));
3892 Ops.push_back(N->getOperand(3));
3893 Ops.push_back(N->getOperand(4));
3894 Ops.push_back(Chain);
3895 break;
3896 case NVPTXISD::Suld3DV2I16Clamp:
3897 Opc = NVPTX::SULD_3D_V2I16_CLAMP;
3898 Ops.push_back(TexHandle);
3899 Ops.push_back(N->getOperand(2));
3900 Ops.push_back(N->getOperand(3));
3901 Ops.push_back(N->getOperand(4));
3902 Ops.push_back(Chain);
3903 break;
3904 case NVPTXISD::Suld3DV2I32Clamp:
3905 Opc = NVPTX::SULD_3D_V2I32_CLAMP;
3906 Ops.push_back(TexHandle);
3907 Ops.push_back(N->getOperand(2));
3908 Ops.push_back(N->getOperand(3));
3909 Ops.push_back(N->getOperand(4));
3910 Ops.push_back(Chain);
3911 break;
3912 case NVPTXISD::Suld3DV2I64Clamp:
3913 Opc = NVPTX::SULD_3D_V2I64_CLAMP;
3914 Ops.push_back(TexHandle);
3915 Ops.push_back(N->getOperand(2));
3916 Ops.push_back(N->getOperand(3));
3917 Ops.push_back(N->getOperand(4));
3918 Ops.push_back(Chain);
3919 break;
3920 case NVPTXISD::Suld3DV4I8Clamp:
3921 Opc = NVPTX::SULD_3D_V4I8_CLAMP;
3922 Ops.push_back(TexHandle);
3923 Ops.push_back(N->getOperand(2));
3924 Ops.push_back(N->getOperand(3));
3925 Ops.push_back(N->getOperand(4));
3926 Ops.push_back(Chain);
3927 break;
3928 case NVPTXISD::Suld3DV4I16Clamp:
3929 Opc = NVPTX::SULD_3D_V4I16_CLAMP;
3930 Ops.push_back(TexHandle);
3931 Ops.push_back(N->getOperand(2));
3932 Ops.push_back(N->getOperand(3));
3933 Ops.push_back(N->getOperand(4));
3934 Ops.push_back(Chain);
3935 break;
3936 case NVPTXISD::Suld3DV4I32Clamp:
3937 Opc = NVPTX::SULD_3D_V4I32_CLAMP;
3938 Ops.push_back(TexHandle);
3939 Ops.push_back(N->getOperand(2));
3940 Ops.push_back(N->getOperand(3));
3941 Ops.push_back(N->getOperand(4));
3942 Ops.push_back(Chain);
3943 break;
3944 case NVPTXISD::Suld1DI8Trap:
3945 Opc = NVPTX::SULD_1D_I8_TRAP;
3946 Ops.push_back(TexHandle);
3947 Ops.push_back(N->getOperand(2));
3948 Ops.push_back(Chain);
3949 break;
3950 case NVPTXISD::Suld1DI16Trap:
3951 Opc = NVPTX::SULD_1D_I16_TRAP;
3952 Ops.push_back(TexHandle);
3953 Ops.push_back(N->getOperand(2));
3954 Ops.push_back(Chain);
3955 break;
3956 case NVPTXISD::Suld1DI32Trap:
3957 Opc = NVPTX::SULD_1D_I32_TRAP;
3958 Ops.push_back(TexHandle);
3959 Ops.push_back(N->getOperand(2));
3960 Ops.push_back(Chain);
3961 break;
3962 case NVPTXISD::Suld1DI64Trap:
3963 Opc = NVPTX::SULD_1D_I64_TRAP;
3964 Ops.push_back(TexHandle);
3965 Ops.push_back(N->getOperand(2));
3966 Ops.push_back(Chain);
3967 break;
3968 case NVPTXISD::Suld1DV2I8Trap:
3969 Opc = NVPTX::SULD_1D_V2I8_TRAP;
3970 Ops.push_back(TexHandle);
3971 Ops.push_back(N->getOperand(2));
3972 Ops.push_back(Chain);
3973 break;
3974 case NVPTXISD::Suld1DV2I16Trap:
3975 Opc = NVPTX::SULD_1D_V2I16_TRAP;
3976 Ops.push_back(TexHandle);
3977 Ops.push_back(N->getOperand(2));
3978 Ops.push_back(Chain);
3979 break;
3980 case NVPTXISD::Suld1DV2I32Trap:
3981 Opc = NVPTX::SULD_1D_V2I32_TRAP;
3982 Ops.push_back(TexHandle);
3983 Ops.push_back(N->getOperand(2));
3984 Ops.push_back(Chain);
3985 break;
3986 case NVPTXISD::Suld1DV2I64Trap:
3987 Opc = NVPTX::SULD_1D_V2I64_TRAP;
3988 Ops.push_back(TexHandle);
3989 Ops.push_back(N->getOperand(2));
3990 Ops.push_back(Chain);
3991 break;
3992 case NVPTXISD::Suld1DV4I8Trap:
3993 Opc = NVPTX::SULD_1D_V4I8_TRAP;
3994 Ops.push_back(TexHandle);
3995 Ops.push_back(N->getOperand(2));
3996 Ops.push_back(Chain);
3997 break;
3998 case NVPTXISD::Suld1DV4I16Trap:
3999 Opc = NVPTX::SULD_1D_V4I16_TRAP;
4000 Ops.push_back(TexHandle);
4001 Ops.push_back(N->getOperand(2));
4002 Ops.push_back(Chain);
4003 break;
4004 case NVPTXISD::Suld1DV4I32Trap:
4005 Opc = NVPTX::SULD_1D_V4I32_TRAP;
4006 Ops.push_back(TexHandle);
4007 Ops.push_back(N->getOperand(2));
4008 Ops.push_back(Chain);
4009 break;
4010 case NVPTXISD::Suld1DArrayI8Trap:
4011 Opc = NVPTX::SULD_1D_ARRAY_I8_TRAP;
4012 Ops.push_back(TexHandle);
4013 Ops.push_back(N->getOperand(2));
4014 Ops.push_back(N->getOperand(3));
4015 Ops.push_back(Chain);
4016 break;
4017 case NVPTXISD::Suld1DArrayI16Trap:
4018 Opc = NVPTX::SULD_1D_ARRAY_I16_TRAP;
4019 Ops.push_back(TexHandle);
4020 Ops.push_back(N->getOperand(2));
4021 Ops.push_back(N->getOperand(3));
4022 Ops.push_back(Chain);
4023 break;
4024 case NVPTXISD::Suld1DArrayI32Trap:
4025 Opc = NVPTX::SULD_1D_ARRAY_I32_TRAP;
4026 Ops.push_back(TexHandle);
4027 Ops.push_back(N->getOperand(2));
4028 Ops.push_back(N->getOperand(3));
4029 Ops.push_back(Chain);
4030 break;
4031 case NVPTXISD::Suld1DArrayI64Trap:
4032 Opc = NVPTX::SULD_1D_ARRAY_I64_TRAP;
4033 Ops.push_back(TexHandle);
4034 Ops.push_back(N->getOperand(2));
4035 Ops.push_back(N->getOperand(3));
4036 Ops.push_back(Chain);
4037 break;
4038 case NVPTXISD::Suld1DArrayV2I8Trap:
4039 Opc = NVPTX::SULD_1D_ARRAY_V2I8_TRAP;
4040 Ops.push_back(TexHandle);
4041 Ops.push_back(N->getOperand(2));
4042 Ops.push_back(N->getOperand(3));
4043 Ops.push_back(Chain);
4044 break;
4045 case NVPTXISD::Suld1DArrayV2I16Trap:
4046 Opc = NVPTX::SULD_1D_ARRAY_V2I16_TRAP;
4047 Ops.push_back(TexHandle);
4048 Ops.push_back(N->getOperand(2));
4049 Ops.push_back(N->getOperand(3));
4050 Ops.push_back(Chain);
4051 break;
4052 case NVPTXISD::Suld1DArrayV2I32Trap:
4053 Opc = NVPTX::SULD_1D_ARRAY_V2I32_TRAP;
4054 Ops.push_back(TexHandle);
4055 Ops.push_back(N->getOperand(2));
4056 Ops.push_back(N->getOperand(3));
4057 Ops.push_back(Chain);
4058 break;
4059 case NVPTXISD::Suld1DArrayV2I64Trap:
4060 Opc = NVPTX::SULD_1D_ARRAY_V2I64_TRAP;
4061 Ops.push_back(TexHandle);
4062 Ops.push_back(N->getOperand(2));
4063 Ops.push_back(N->getOperand(3));
4064 Ops.push_back(Chain);
4065 break;
4066 case NVPTXISD::Suld1DArrayV4I8Trap:
4067 Opc = NVPTX::SULD_1D_ARRAY_V4I8_TRAP;
4068 Ops.push_back(TexHandle);
4069 Ops.push_back(N->getOperand(2));
4070 Ops.push_back(N->getOperand(3));
4071 Ops.push_back(Chain);
4072 break;
4073 case NVPTXISD::Suld1DArrayV4I16Trap:
4074 Opc = NVPTX::SULD_1D_ARRAY_V4I16_TRAP;
4075 Ops.push_back(TexHandle);
4076 Ops.push_back(N->getOperand(2));
4077 Ops.push_back(N->getOperand(3));
4078 Ops.push_back(Chain);
4079 break;
4080 case NVPTXISD::Suld1DArrayV4I32Trap:
4081 Opc = NVPTX::SULD_1D_ARRAY_V4I32_TRAP;
4082 Ops.push_back(TexHandle);
4083 Ops.push_back(N->getOperand(2));
4084 Ops.push_back(N->getOperand(3));
4085 Ops.push_back(Chain);
4086 break;
4087 case NVPTXISD::Suld2DI8Trap:
4088 Opc = NVPTX::SULD_2D_I8_TRAP;
4089 Ops.push_back(TexHandle);
4090 Ops.push_back(N->getOperand(2));
4091 Ops.push_back(N->getOperand(3));
4092 Ops.push_back(Chain);
4093 break;
4094 case NVPTXISD::Suld2DI16Trap:
4095 Opc = NVPTX::SULD_2D_I16_TRAP;
4096 Ops.push_back(TexHandle);
4097 Ops.push_back(N->getOperand(2));
4098 Ops.push_back(N->getOperand(3));
4099 Ops.push_back(Chain);
4100 break;
4101 case NVPTXISD::Suld2DI32Trap:
4102 Opc = NVPTX::SULD_2D_I32_TRAP;
4103 Ops.push_back(TexHandle);
4104 Ops.push_back(N->getOperand(2));
4105 Ops.push_back(N->getOperand(3));
4106 Ops.push_back(Chain);
4107 break;
4108 case NVPTXISD::Suld2DI64Trap:
4109 Opc = NVPTX::SULD_2D_I64_TRAP;
4110 Ops.push_back(TexHandle);
4111 Ops.push_back(N->getOperand(2));
4112 Ops.push_back(N->getOperand(3));
4113 Ops.push_back(Chain);
4114 break;
4115 case NVPTXISD::Suld2DV2I8Trap:
4116 Opc = NVPTX::SULD_2D_V2I8_TRAP;
4117 Ops.push_back(TexHandle);
4118 Ops.push_back(N->getOperand(2));
4119 Ops.push_back(N->getOperand(3));
4120 Ops.push_back(Chain);
4121 break;
4122 case NVPTXISD::Suld2DV2I16Trap:
4123 Opc = NVPTX::SULD_2D_V2I16_TRAP;
4124 Ops.push_back(TexHandle);
4125 Ops.push_back(N->getOperand(2));
4126 Ops.push_back(N->getOperand(3));
4127 Ops.push_back(Chain);
4128 break;
4129 case NVPTXISD::Suld2DV2I32Trap:
4130 Opc = NVPTX::SULD_2D_V2I32_TRAP;
4131 Ops.push_back(TexHandle);
4132 Ops.push_back(N->getOperand(2));
4133 Ops.push_back(N->getOperand(3));
4134 Ops.push_back(Chain);
4135 break;
4136 case NVPTXISD::Suld2DV2I64Trap:
4137 Opc = NVPTX::SULD_2D_V2I64_TRAP;
4138 Ops.push_back(TexHandle);
4139 Ops.push_back(N->getOperand(2));
4140 Ops.push_back(N->getOperand(3));
4141 Ops.push_back(Chain);
4142 break;
4143 case NVPTXISD::Suld2DV4I8Trap:
4144 Opc = NVPTX::SULD_2D_V4I8_TRAP;
4145 Ops.push_back(TexHandle);
4146 Ops.push_back(N->getOperand(2));
4147 Ops.push_back(N->getOperand(3));
4148 Ops.push_back(Chain);
4149 break;
4150 case NVPTXISD::Suld2DV4I16Trap:
4151 Opc = NVPTX::SULD_2D_V4I16_TRAP;
4152 Ops.push_back(TexHandle);
4153 Ops.push_back(N->getOperand(2));
4154 Ops.push_back(N->getOperand(3));
4155 Ops.push_back(Chain);
4156 break;
4157 case NVPTXISD::Suld2DV4I32Trap:
4158 Opc = NVPTX::SULD_2D_V4I32_TRAP;
4159 Ops.push_back(TexHandle);
4160 Ops.push_back(N->getOperand(2));
4161 Ops.push_back(N->getOperand(3));
4162 Ops.push_back(Chain);
4163 break;
4164 case NVPTXISD::Suld2DArrayI8Trap:
4165 Opc = NVPTX::SULD_2D_ARRAY_I8_TRAP;
4166 Ops.push_back(TexHandle);
4167 Ops.push_back(N->getOperand(2));
4168 Ops.push_back(N->getOperand(3));
4169 Ops.push_back(N->getOperand(4));
4170 Ops.push_back(Chain);
4171 break;
4172 case NVPTXISD::Suld2DArrayI16Trap:
4173 Opc = NVPTX::SULD_2D_ARRAY_I16_TRAP;
4174 Ops.push_back(TexHandle);
4175 Ops.push_back(N->getOperand(2));
4176 Ops.push_back(N->getOperand(3));
4177 Ops.push_back(N->getOperand(4));
4178 Ops.push_back(Chain);
4179 break;
4180 case NVPTXISD::Suld2DArrayI32Trap:
4181 Opc = NVPTX::SULD_2D_ARRAY_I32_TRAP;
4182 Ops.push_back(TexHandle);
4183 Ops.push_back(N->getOperand(2));
4184 Ops.push_back(N->getOperand(3));
4185 Ops.push_back(N->getOperand(4));
4186 Ops.push_back(Chain);
4187 break;
4188 case NVPTXISD::Suld2DArrayI64Trap:
4189 Opc = NVPTX::SULD_2D_ARRAY_I64_TRAP;
4190 Ops.push_back(TexHandle);
4191 Ops.push_back(N->getOperand(2));
4192 Ops.push_back(N->getOperand(3));
4193 Ops.push_back(N->getOperand(4));
4194 Ops.push_back(Chain);
4195 break;
4196 case NVPTXISD::Suld2DArrayV2I8Trap:
4197 Opc = NVPTX::SULD_2D_ARRAY_V2I8_TRAP;
4198 Ops.push_back(TexHandle);
4199 Ops.push_back(N->getOperand(2));
4200 Ops.push_back(N->getOperand(3));
4201 Ops.push_back(N->getOperand(4));
4202 Ops.push_back(Chain);
4203 break;
4204 case NVPTXISD::Suld2DArrayV2I16Trap:
4205 Opc = NVPTX::SULD_2D_ARRAY_V2I16_TRAP;
4206 Ops.push_back(TexHandle);
4207 Ops.push_back(N->getOperand(2));
4208 Ops.push_back(N->getOperand(3));
4209 Ops.push_back(N->getOperand(4));
4210 Ops.push_back(Chain);
4211 break;
4212 case NVPTXISD::Suld2DArrayV2I32Trap:
4213 Opc = NVPTX::SULD_2D_ARRAY_V2I32_TRAP;
4214 Ops.push_back(TexHandle);
4215 Ops.push_back(N->getOperand(2));
4216 Ops.push_back(N->getOperand(3));
4217 Ops.push_back(N->getOperand(4));
4218 Ops.push_back(Chain);
4219 break;
4220 case NVPTXISD::Suld2DArrayV2I64Trap:
4221 Opc = NVPTX::SULD_2D_ARRAY_V2I64_TRAP;
4222 Ops.push_back(TexHandle);
4223 Ops.push_back(N->getOperand(2));
4224 Ops.push_back(N->getOperand(3));
4225 Ops.push_back(N->getOperand(4));
4226 Ops.push_back(Chain);
4227 break;
4228 case NVPTXISD::Suld2DArrayV4I8Trap:
4229 Opc = NVPTX::SULD_2D_ARRAY_V4I8_TRAP;
4230 Ops.push_back(TexHandle);
4231 Ops.push_back(N->getOperand(2));
4232 Ops.push_back(N->getOperand(3));
4233 Ops.push_back(N->getOperand(4));
4234 Ops.push_back(Chain);
4235 break;
4236 case NVPTXISD::Suld2DArrayV4I16Trap:
4237 Opc = NVPTX::SULD_2D_ARRAY_V4I16_TRAP;
4238 Ops.push_back(TexHandle);
4239 Ops.push_back(N->getOperand(2));
4240 Ops.push_back(N->getOperand(3));
4241 Ops.push_back(N->getOperand(4));
4242 Ops.push_back(Chain);
4243 break;
4244 case NVPTXISD::Suld2DArrayV4I32Trap:
4245 Opc = NVPTX::SULD_2D_ARRAY_V4I32_TRAP;
4246 Ops.push_back(TexHandle);
4247 Ops.push_back(N->getOperand(2));
4248 Ops.push_back(N->getOperand(3));
4249 Ops.push_back(N->getOperand(4));
4250 Ops.push_back(Chain);
4251 break;
4252 case NVPTXISD::Suld3DI8Trap:
4253 Opc = NVPTX::SULD_3D_I8_TRAP;
4254 Ops.push_back(TexHandle);
4255 Ops.push_back(N->getOperand(2));
4256 Ops.push_back(N->getOperand(3));
4257 Ops.push_back(N->getOperand(4));
4258 Ops.push_back(Chain);
4259 break;
4260 case NVPTXISD::Suld3DI16Trap:
4261 Opc = NVPTX::SULD_3D_I16_TRAP;
4262 Ops.push_back(TexHandle);
4263 Ops.push_back(N->getOperand(2));
4264 Ops.push_back(N->getOperand(3));
4265 Ops.push_back(N->getOperand(4));
4266 Ops.push_back(Chain);
4267 break;
4268 case NVPTXISD::Suld3DI32Trap:
4269 Opc = NVPTX::SULD_3D_I32_TRAP;
4270 Ops.push_back(TexHandle);
4271 Ops.push_back(N->getOperand(2));
4272 Ops.push_back(N->getOperand(3));
4273 Ops.push_back(N->getOperand(4));
4274 Ops.push_back(Chain);
4275 break;
4276 case NVPTXISD::Suld3DI64Trap:
4277 Opc = NVPTX::SULD_3D_I64_TRAP;
4278 Ops.push_back(TexHandle);
4279 Ops.push_back(N->getOperand(2));
4280 Ops.push_back(N->getOperand(3));
4281 Ops.push_back(N->getOperand(4));
4282 Ops.push_back(Chain);
4283 break;
4284 case NVPTXISD::Suld3DV2I8Trap:
4285 Opc = NVPTX::SULD_3D_V2I8_TRAP;
4286 Ops.push_back(TexHandle);
4287 Ops.push_back(N->getOperand(2));
4288 Ops.push_back(N->getOperand(3));
4289 Ops.push_back(N->getOperand(4));
4290 Ops.push_back(Chain);
4291 break;
4292 case NVPTXISD::Suld3DV2I16Trap:
4293 Opc = NVPTX::SULD_3D_V2I16_TRAP;
4294 Ops.push_back(TexHandle);
4295 Ops.push_back(N->getOperand(2));
4296 Ops.push_back(N->getOperand(3));
4297 Ops.push_back(N->getOperand(4));
4298 Ops.push_back(Chain);
4299 break;
4300 case NVPTXISD::Suld3DV2I32Trap:
4301 Opc = NVPTX::SULD_3D_V2I32_TRAP;
4302 Ops.push_back(TexHandle);
4303 Ops.push_back(N->getOperand(2));
4304 Ops.push_back(N->getOperand(3));
4305 Ops.push_back(N->getOperand(4));
4306 Ops.push_back(Chain);
4307 break;
4308 case NVPTXISD::Suld3DV2I64Trap:
4309 Opc = NVPTX::SULD_3D_V2I64_TRAP;
4310 Ops.push_back(TexHandle);
4311 Ops.push_back(N->getOperand(2));
4312 Ops.push_back(N->getOperand(3));
4313 Ops.push_back(N->getOperand(4));
4314 Ops.push_back(Chain);
4315 break;
4316 case NVPTXISD::Suld3DV4I8Trap:
4317 Opc = NVPTX::SULD_3D_V4I8_TRAP;
4318 Ops.push_back(TexHandle);
4319 Ops.push_back(N->getOperand(2));
4320 Ops.push_back(N->getOperand(3));
4321 Ops.push_back(N->getOperand(4));
4322 Ops.push_back(Chain);
4323 break;
4324 case NVPTXISD::Suld3DV4I16Trap:
4325 Opc = NVPTX::SULD_3D_V4I16_TRAP;
4326 Ops.push_back(TexHandle);
4327 Ops.push_back(N->getOperand(2));
4328 Ops.push_back(N->getOperand(3));
4329 Ops.push_back(N->getOperand(4));
4330 Ops.push_back(Chain);
4331 break;
4332 case NVPTXISD::Suld3DV4I32Trap:
4333 Opc = NVPTX::SULD_3D_V4I32_TRAP;
4334 Ops.push_back(TexHandle);
4335 Ops.push_back(N->getOperand(2));
4336 Ops.push_back(N->getOperand(3));
4337 Ops.push_back(N->getOperand(4));
4338 Ops.push_back(Chain);
4339 break;
4340 case NVPTXISD::Suld1DI8Zero:
4341 Opc = NVPTX::SULD_1D_I8_ZERO;
4342 Ops.push_back(TexHandle);
4343 Ops.push_back(N->getOperand(2));
4344 Ops.push_back(Chain);
4345 break;
4346 case NVPTXISD::Suld1DI16Zero:
4347 Opc = NVPTX::SULD_1D_I16_ZERO;
4348 Ops.push_back(TexHandle);
4349 Ops.push_back(N->getOperand(2));
4350 Ops.push_back(Chain);
4351 break;
4352 case NVPTXISD::Suld1DI32Zero:
4353 Opc = NVPTX::SULD_1D_I32_ZERO;
4354 Ops.push_back(TexHandle);
4355 Ops.push_back(N->getOperand(2));
4356 Ops.push_back(Chain);
4357 break;
4358 case NVPTXISD::Suld1DI64Zero:
4359 Opc = NVPTX::SULD_1D_I64_ZERO;
4360 Ops.push_back(TexHandle);
4361 Ops.push_back(N->getOperand(2));
4362 Ops.push_back(Chain);
4363 break;
4364 case NVPTXISD::Suld1DV2I8Zero:
4365 Opc = NVPTX::SULD_1D_V2I8_ZERO;
4366 Ops.push_back(TexHandle);
4367 Ops.push_back(N->getOperand(2));
4368 Ops.push_back(Chain);
4369 break;
4370 case NVPTXISD::Suld1DV2I16Zero:
4371 Opc = NVPTX::SULD_1D_V2I16_ZERO;
4372 Ops.push_back(TexHandle);
4373 Ops.push_back(N->getOperand(2));
4374 Ops.push_back(Chain);
4375 break;
4376 case NVPTXISD::Suld1DV2I32Zero:
4377 Opc = NVPTX::SULD_1D_V2I32_ZERO;
4378 Ops.push_back(TexHandle);
4379 Ops.push_back(N->getOperand(2));
4380 Ops.push_back(Chain);
4381 break;
4382 case NVPTXISD::Suld1DV2I64Zero:
4383 Opc = NVPTX::SULD_1D_V2I64_ZERO;
4384 Ops.push_back(TexHandle);
4385 Ops.push_back(N->getOperand(2));
4386 Ops.push_back(Chain);
4387 break;
4388 case NVPTXISD::Suld1DV4I8Zero:
4389 Opc = NVPTX::SULD_1D_V4I8_ZERO;
4390 Ops.push_back(TexHandle);
4391 Ops.push_back(N->getOperand(2));
4392 Ops.push_back(Chain);
4393 break;
4394 case NVPTXISD::Suld1DV4I16Zero:
4395 Opc = NVPTX::SULD_1D_V4I16_ZERO;
4396 Ops.push_back(TexHandle);
4397 Ops.push_back(N->getOperand(2));
4398 Ops.push_back(Chain);
4399 break;
4400 case NVPTXISD::Suld1DV4I32Zero:
4401 Opc = NVPTX::SULD_1D_V4I32_ZERO;
4402 Ops.push_back(TexHandle);
4403 Ops.push_back(N->getOperand(2));
4404 Ops.push_back(Chain);
4405 break;
4406 case NVPTXISD::Suld1DArrayI8Zero:
4407 Opc = NVPTX::SULD_1D_ARRAY_I8_ZERO;
4408 Ops.push_back(TexHandle);
4409 Ops.push_back(N->getOperand(2));
4410 Ops.push_back(N->getOperand(3));
4411 Ops.push_back(Chain);
4412 break;
4413 case NVPTXISD::Suld1DArrayI16Zero:
4414 Opc = NVPTX::SULD_1D_ARRAY_I16_ZERO;
4415 Ops.push_back(TexHandle);
4416 Ops.push_back(N->getOperand(2));
4417 Ops.push_back(N->getOperand(3));
4418 Ops.push_back(Chain);
4419 break;
4420 case NVPTXISD::Suld1DArrayI32Zero:
4421 Opc = NVPTX::SULD_1D_ARRAY_I32_ZERO;
4422 Ops.push_back(TexHandle);
4423 Ops.push_back(N->getOperand(2));
4424 Ops.push_back(N->getOperand(3));
4425 Ops.push_back(Chain);
4426 break;
4427 case NVPTXISD::Suld1DArrayI64Zero:
4428 Opc = NVPTX::SULD_1D_ARRAY_I64_ZERO;
4429 Ops.push_back(TexHandle);
4430 Ops.push_back(N->getOperand(2));
4431 Ops.push_back(N->getOperand(3));
4432 Ops.push_back(Chain);
4433 break;
4434 case NVPTXISD::Suld1DArrayV2I8Zero:
4435 Opc = NVPTX::SULD_1D_ARRAY_V2I8_ZERO;
4436 Ops.push_back(TexHandle);
4437 Ops.push_back(N->getOperand(2));
4438 Ops.push_back(N->getOperand(3));
4439 Ops.push_back(Chain);
4440 break;
4441 case NVPTXISD::Suld1DArrayV2I16Zero:
4442 Opc = NVPTX::SULD_1D_ARRAY_V2I16_ZERO;
4443 Ops.push_back(TexHandle);
4444 Ops.push_back(N->getOperand(2));
4445 Ops.push_back(N->getOperand(3));
4446 Ops.push_back(Chain);
4447 break;
4448 case NVPTXISD::Suld1DArrayV2I32Zero:
4449 Opc = NVPTX::SULD_1D_ARRAY_V2I32_ZERO;
4450 Ops.push_back(TexHandle);
4451 Ops.push_back(N->getOperand(2));
4452 Ops.push_back(N->getOperand(3));
4453 Ops.push_back(Chain);
4454 break;
4455 case NVPTXISD::Suld1DArrayV2I64Zero:
4456 Opc = NVPTX::SULD_1D_ARRAY_V2I64_ZERO;
4457 Ops.push_back(TexHandle);
4458 Ops.push_back(N->getOperand(2));
4459 Ops.push_back(N->getOperand(3));
4460 Ops.push_back(Chain);
4461 break;
4462 case NVPTXISD::Suld1DArrayV4I8Zero:
4463 Opc = NVPTX::SULD_1D_ARRAY_V4I8_ZERO;
4464 Ops.push_back(TexHandle);
4465 Ops.push_back(N->getOperand(2));
4466 Ops.push_back(N->getOperand(3));
4467 Ops.push_back(Chain);
4468 break;
4469 case NVPTXISD::Suld1DArrayV4I16Zero:
4470 Opc = NVPTX::SULD_1D_ARRAY_V4I16_ZERO;
4471 Ops.push_back(TexHandle);
4472 Ops.push_back(N->getOperand(2));
4473 Ops.push_back(N->getOperand(3));
4474 Ops.push_back(Chain);
4475 break;
4476 case NVPTXISD::Suld1DArrayV4I32Zero:
4477 Opc = NVPTX::SULD_1D_ARRAY_V4I32_ZERO;
4478 Ops.push_back(TexHandle);
4479 Ops.push_back(N->getOperand(2));
4480 Ops.push_back(N->getOperand(3));
4481 Ops.push_back(Chain);
4482 break;
4483 case NVPTXISD::Suld2DI8Zero:
4484 Opc = NVPTX::SULD_2D_I8_ZERO;
4485 Ops.push_back(TexHandle);
4486 Ops.push_back(N->getOperand(2));
4487 Ops.push_back(N->getOperand(3));
4488 Ops.push_back(Chain);
4489 break;
4490 case NVPTXISD::Suld2DI16Zero:
4491 Opc = NVPTX::SULD_2D_I16_ZERO;
4492 Ops.push_back(TexHandle);
4493 Ops.push_back(N->getOperand(2));
4494 Ops.push_back(N->getOperand(3));
4495 Ops.push_back(Chain);
4496 break;
4497 case NVPTXISD::Suld2DI32Zero:
4498 Opc = NVPTX::SULD_2D_I32_ZERO;
4499 Ops.push_back(TexHandle);
4500 Ops.push_back(N->getOperand(2));
4501 Ops.push_back(N->getOperand(3));
4502 Ops.push_back(Chain);
4503 break;
4504 case NVPTXISD::Suld2DI64Zero:
4505 Opc = NVPTX::SULD_2D_I64_ZERO;
4506 Ops.push_back(TexHandle);
4507 Ops.push_back(N->getOperand(2));
4508 Ops.push_back(N->getOperand(3));
4509 Ops.push_back(Chain);
4510 break;
4511 case NVPTXISD::Suld2DV2I8Zero:
4512 Opc = NVPTX::SULD_2D_V2I8_ZERO;
4513 Ops.push_back(TexHandle);
4514 Ops.push_back(N->getOperand(2));
4515 Ops.push_back(N->getOperand(3));
4516 Ops.push_back(Chain);
4517 break;
4518 case NVPTXISD::Suld2DV2I16Zero:
4519 Opc = NVPTX::SULD_2D_V2I16_ZERO;
4520 Ops.push_back(TexHandle);
4521 Ops.push_back(N->getOperand(2));
4522 Ops.push_back(N->getOperand(3));
4523 Ops.push_back(Chain);
4524 break;
4525 case NVPTXISD::Suld2DV2I32Zero:
4526 Opc = NVPTX::SULD_2D_V2I32_ZERO;
4527 Ops.push_back(TexHandle);
4528 Ops.push_back(N->getOperand(2));
4529 Ops.push_back(N->getOperand(3));
4530 Ops.push_back(Chain);
4531 break;
4532 case NVPTXISD::Suld2DV2I64Zero:
4533 Opc = NVPTX::SULD_2D_V2I64_ZERO;
4534 Ops.push_back(TexHandle);
4535 Ops.push_back(N->getOperand(2));
4536 Ops.push_back(N->getOperand(3));
4537 Ops.push_back(Chain);
4538 break;
4539 case NVPTXISD::Suld2DV4I8Zero:
4540 Opc = NVPTX::SULD_2D_V4I8_ZERO;
4541 Ops.push_back(TexHandle);
4542 Ops.push_back(N->getOperand(2));
4543 Ops.push_back(N->getOperand(3));
4544 Ops.push_back(Chain);
4545 break;
4546 case NVPTXISD::Suld2DV4I16Zero:
4547 Opc = NVPTX::SULD_2D_V4I16_ZERO;
4548 Ops.push_back(TexHandle);
4549 Ops.push_back(N->getOperand(2));
4550 Ops.push_back(N->getOperand(3));
4551 Ops.push_back(Chain);
4552 break;
4553 case NVPTXISD::Suld2DV4I32Zero:
4554 Opc = NVPTX::SULD_2D_V4I32_ZERO;
4555 Ops.push_back(TexHandle);
4556 Ops.push_back(N->getOperand(2));
4557 Ops.push_back(N->getOperand(3));
4558 Ops.push_back(Chain);
4559 break;
4560 case NVPTXISD::Suld2DArrayI8Zero:
4561 Opc = NVPTX::SULD_2D_ARRAY_I8_ZERO;
4562 Ops.push_back(TexHandle);
4563 Ops.push_back(N->getOperand(2));
4564 Ops.push_back(N->getOperand(3));
4565 Ops.push_back(N->getOperand(4));
4566 Ops.push_back(Chain);
4567 break;
4568 case NVPTXISD::Suld2DArrayI16Zero:
4569 Opc = NVPTX::SULD_2D_ARRAY_I16_ZERO;
4570 Ops.push_back(TexHandle);
4571 Ops.push_back(N->getOperand(2));
4572 Ops.push_back(N->getOperand(3));
4573 Ops.push_back(N->getOperand(4));
4574 Ops.push_back(Chain);
4575 break;
4576 case NVPTXISD::Suld2DArrayI32Zero:
4577 Opc = NVPTX::SULD_2D_ARRAY_I32_ZERO;
4578 Ops.push_back(TexHandle);
4579 Ops.push_back(N->getOperand(2));
4580 Ops.push_back(N->getOperand(3));
4581 Ops.push_back(N->getOperand(4));
4582 Ops.push_back(Chain);
4583 break;
4584 case NVPTXISD::Suld2DArrayI64Zero:
4585 Opc = NVPTX::SULD_2D_ARRAY_I64_ZERO;
4586 Ops.push_back(TexHandle);
4587 Ops.push_back(N->getOperand(2));
4588 Ops.push_back(N->getOperand(3));
4589 Ops.push_back(N->getOperand(4));
4590 Ops.push_back(Chain);
4591 break;
4592 case NVPTXISD::Suld2DArrayV2I8Zero:
4593 Opc = NVPTX::SULD_2D_ARRAY_V2I8_ZERO;
4594 Ops.push_back(TexHandle);
4595 Ops.push_back(N->getOperand(2));
4596 Ops.push_back(N->getOperand(3));
4597 Ops.push_back(N->getOperand(4));
4598 Ops.push_back(Chain);
4599 break;
4600 case NVPTXISD::Suld2DArrayV2I16Zero:
4601 Opc = NVPTX::SULD_2D_ARRAY_V2I16_ZERO;
4602 Ops.push_back(TexHandle);
4603 Ops.push_back(N->getOperand(2));
4604 Ops.push_back(N->getOperand(3));
4605 Ops.push_back(N->getOperand(4));
4606 Ops.push_back(Chain);
4607 break;
4608 case NVPTXISD::Suld2DArrayV2I32Zero:
4609 Opc = NVPTX::SULD_2D_ARRAY_V2I32_ZERO;
4610 Ops.push_back(TexHandle);
4611 Ops.push_back(N->getOperand(2));
4612 Ops.push_back(N->getOperand(3));
4613 Ops.push_back(N->getOperand(4));
4614 Ops.push_back(Chain);
4615 break;
4616 case NVPTXISD::Suld2DArrayV2I64Zero:
4617 Opc = NVPTX::SULD_2D_ARRAY_V2I64_ZERO;
4618 Ops.push_back(TexHandle);
4619 Ops.push_back(N->getOperand(2));
4620 Ops.push_back(N->getOperand(3));
4621 Ops.push_back(N->getOperand(4));
4622 Ops.push_back(Chain);
4623 break;
4624 case NVPTXISD::Suld2DArrayV4I8Zero:
4625 Opc = NVPTX::SULD_2D_ARRAY_V4I8_ZERO;
4626 Ops.push_back(TexHandle);
4627 Ops.push_back(N->getOperand(2));
4628 Ops.push_back(N->getOperand(3));
4629 Ops.push_back(N->getOperand(4));
4630 Ops.push_back(Chain);
4631 break;
4632 case NVPTXISD::Suld2DArrayV4I16Zero:
4633 Opc = NVPTX::SULD_2D_ARRAY_V4I16_ZERO;
4634 Ops.push_back(TexHandle);
4635 Ops.push_back(N->getOperand(2));
4636 Ops.push_back(N->getOperand(3));
4637 Ops.push_back(N->getOperand(4));
4638 Ops.push_back(Chain);
4639 break;
4640 case NVPTXISD::Suld2DArrayV4I32Zero:
4641 Opc = NVPTX::SULD_2D_ARRAY_V4I32_ZERO;
4642 Ops.push_back(TexHandle);
4643 Ops.push_back(N->getOperand(2));
4644 Ops.push_back(N->getOperand(3));
4645 Ops.push_back(N->getOperand(4));
4646 Ops.push_back(Chain);
4647 break;
4648 case NVPTXISD::Suld3DI8Zero:
4649 Opc = NVPTX::SULD_3D_I8_ZERO;
4650 Ops.push_back(TexHandle);
4651 Ops.push_back(N->getOperand(2));
4652 Ops.push_back(N->getOperand(3));
4653 Ops.push_back(N->getOperand(4));
4654 Ops.push_back(Chain);
4655 break;
4656 case NVPTXISD::Suld3DI16Zero:
4657 Opc = NVPTX::SULD_3D_I16_ZERO;
4658 Ops.push_back(TexHandle);
4659 Ops.push_back(N->getOperand(2));
4660 Ops.push_back(N->getOperand(3));
4661 Ops.push_back(N->getOperand(4));
4662 Ops.push_back(Chain);
4663 break;
4664 case NVPTXISD::Suld3DI32Zero:
4665 Opc = NVPTX::SULD_3D_I32_ZERO;
4666 Ops.push_back(TexHandle);
4667 Ops.push_back(N->getOperand(2));
4668 Ops.push_back(N->getOperand(3));
4669 Ops.push_back(N->getOperand(4));
4670 Ops.push_back(Chain);
4671 break;
4672 case NVPTXISD::Suld3DI64Zero:
4673 Opc = NVPTX::SULD_3D_I64_ZERO;
4674 Ops.push_back(TexHandle);
4675 Ops.push_back(N->getOperand(2));
4676 Ops.push_back(N->getOperand(3));
4677 Ops.push_back(N->getOperand(4));
4678 Ops.push_back(Chain);
4679 break;
4680 case NVPTXISD::Suld3DV2I8Zero:
4681 Opc = NVPTX::SULD_3D_V2I8_ZERO;
4682 Ops.push_back(TexHandle);
4683 Ops.push_back(N->getOperand(2));
4684 Ops.push_back(N->getOperand(3));
4685 Ops.push_back(N->getOperand(4));
4686 Ops.push_back(Chain);
4687 break;
4688 case NVPTXISD::Suld3DV2I16Zero:
4689 Opc = NVPTX::SULD_3D_V2I16_ZERO;
4690 Ops.push_back(TexHandle);
4691 Ops.push_back(N->getOperand(2));
4692 Ops.push_back(N->getOperand(3));
4693 Ops.push_back(N->getOperand(4));
4694 Ops.push_back(Chain);
4695 break;
4696 case NVPTXISD::Suld3DV2I32Zero:
4697 Opc = NVPTX::SULD_3D_V2I32_ZERO;
4698 Ops.push_back(TexHandle);
4699 Ops.push_back(N->getOperand(2));
4700 Ops.push_back(N->getOperand(3));
4701 Ops.push_back(N->getOperand(4));
4702 Ops.push_back(Chain);
4703 break;
4704 case NVPTXISD::Suld3DV2I64Zero:
4705 Opc = NVPTX::SULD_3D_V2I64_ZERO;
4706 Ops.push_back(TexHandle);
4707 Ops.push_back(N->getOperand(2));
4708 Ops.push_back(N->getOperand(3));
4709 Ops.push_back(N->getOperand(4));
4710 Ops.push_back(Chain);
4711 break;
4712 case NVPTXISD::Suld3DV4I8Zero:
4713 Opc = NVPTX::SULD_3D_V4I8_ZERO;
4714 Ops.push_back(TexHandle);
4715 Ops.push_back(N->getOperand(2));
4716 Ops.push_back(N->getOperand(3));
4717 Ops.push_back(N->getOperand(4));
4718 Ops.push_back(Chain);
4719 break;
4720 case NVPTXISD::Suld3DV4I16Zero:
4721 Opc = NVPTX::SULD_3D_V4I16_ZERO;
4722 Ops.push_back(TexHandle);
4723 Ops.push_back(N->getOperand(2));
4724 Ops.push_back(N->getOperand(3));
4725 Ops.push_back(N->getOperand(4));
4726 Ops.push_back(Chain);
4727 break;
4728 case NVPTXISD::Suld3DV4I32Zero:
4729 Opc = NVPTX::SULD_3D_V4I32_ZERO;
4730 Ops.push_back(TexHandle);
4731 Ops.push_back(N->getOperand(2));
4732 Ops.push_back(N->getOperand(3));
4733 Ops.push_back(N->getOperand(4));
4734 Ops.push_back(Chain);
4735 break;
4736 }
4737 Ret = CurDAG->getMachineNode(Opc, SDLoc(N), N->getVTList(), Ops);
4738 return Ret;
4739}
4740
4741
4742/// SelectBFE - Look for instruction sequences that can be made more efficient
4743/// by using the 'bfe' (bit-field extract) PTX instruction
4744SDNode *NVPTXDAGToDAGISel::SelectBFE(SDNode *N) {
4745 SDValue LHS = N->getOperand(0);
4746 SDValue RHS = N->getOperand(1);
4747 SDValue Len;
4748 SDValue Start;
4749 SDValue Val;
4750 bool IsSigned = false;
4751
4752 if (N->getOpcode() == ISD::AND) {
1
Taking false branch
4753 // Canonicalize the operands
4754 // We want 'and %val, %mask'
4755 if (isa<ConstantSDNode>(LHS) && !isa<ConstantSDNode>(RHS)) {
4756 std::swap(LHS, RHS);
4757 }
4758
4759 ConstantSDNode *Mask = dyn_cast<ConstantSDNode>(RHS);
4760 if (!Mask) {
4761 // We need a constant mask on the RHS of the AND
4762 return NULL__null;
4763 }
4764
4765 // Extract the mask bits
4766 uint64_t MaskVal = Mask->getZExtValue();
4767 if (!isMask_64(MaskVal)) {
4768 // We *could* handle shifted masks here, but doing so would require an
4769 // 'and' operation to fix up the low-order bits so we would trade
4770 // shr+and for bfe+and, which has the same throughput
4771 return NULL__null;
4772 }
4773
4774 // How many bits are in our mask?
4775 uint64_t NumBits = CountTrailingOnes_64(MaskVal);
4776 Len = CurDAG->getTargetConstant(NumBits, MVT::i32);
4777
4778 if (LHS.getOpcode() == ISD::SRL || LHS.getOpcode() == ISD::SRA) {
4779 // We have a 'srl/and' pair, extract the effective start bit and length
4780 Val = LHS.getNode()->getOperand(0);
4781 Start = LHS.getNode()->getOperand(1);
4782 ConstantSDNode *StartConst = dyn_cast<ConstantSDNode>(Start);
4783 if (StartConst) {
4784 uint64_t StartVal = StartConst->getZExtValue();
4785 // How many "good" bits do we have left? "good" is defined here as bits
4786 // that exist in the original value, not shifted in.
4787 uint64_t GoodBits = Start.getValueType().getSizeInBits() - StartVal;
4788 if (NumBits > GoodBits) {
4789 // Do not handle the case where bits have been shifted in. In theory
4790 // we could handle this, but the cost is likely higher than just
4791 // emitting the srl/and pair.
4792 return NULL__null;
4793 }
4794 Start = CurDAG->getTargetConstant(StartVal, MVT::i32);
4795 } else {
4796 // Do not handle the case where the shift amount (can be zero if no srl
4797 // was found) is not constant. We could handle this case, but it would
4798 // require run-time logic that would be more expensive than just
4799 // emitting the srl/and pair.
4800 return NULL__null;
4801 }
4802 } else {
4803 // Do not handle the case where the LHS of the and is not a shift. While
4804 // it would be trivial to handle this case, it would just transform
4805 // 'and' -> 'bfe', but 'and' has higher-throughput.
4806 return NULL__null;
4807 }
4808 } else if (N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) {
4809 if (LHS->getOpcode() == ISD::AND) {
2
Taking true branch
4810 ConstantSDNode *ShiftCnst = dyn_cast<ConstantSDNode>(RHS);
4811 if (!ShiftCnst) {
3
Assuming 'ShiftCnst' is non-null
4
Taking false branch
4812 // Shift amount must be constant
4813 return NULL__null;
4814 }
4815
4816 uint64_t ShiftAmt = ShiftCnst->getZExtValue();
4817
4818 SDValue AndLHS = LHS->getOperand(0);
4819 SDValue AndRHS = LHS->getOperand(1);
4820
4821 // Canonicalize the AND to have the mask on the RHS
4822 if (isa<ConstantSDNode>(AndLHS)) {
5
Taking false branch
4823 std::swap(AndLHS, AndRHS);
4824 }
4825
4826 ConstantSDNode *MaskCnst = dyn_cast<ConstantSDNode>(AndRHS);
4827 if (!MaskCnst) {
6
Assuming 'MaskCnst' is non-null
7
Taking false branch
4828 // Mask must be constant
4829 return NULL__null;
4830 }
4831
4832 uint64_t MaskVal = MaskCnst->getZExtValue();
4833 uint64_t NumZeros;
4834 uint64_t NumBits;
4835 if (isMask_64(MaskVal)) {
8
Taking false branch
4836 NumZeros = 0;
4837 // The number of bits in the result bitfield will be the number of
4838 // trailing ones (the AND) minus the number of bits we shift off
4839 NumBits = CountTrailingOnes_64(MaskVal) - ShiftAmt;
4840 } else if (isShiftedMask_64(MaskVal)) {
9
Taking true branch
4841 NumZeros = countTrailingZeros(MaskVal);
4842 unsigned NumOnes = CountTrailingOnes_64(MaskVal >> NumZeros);
10
The result of the '>>' expression is undefined
4843 // The number of bits in the result bitfield will be the number of
4844 // trailing zeros plus the number of set bits in the mask minus the
4845 // number of bits we shift off
4846 NumBits = NumZeros + NumOnes - ShiftAmt;
4847 } else {
4848 // This is not a mask we can handle
4849 return NULL__null;
4850 }
4851
4852 if (ShiftAmt < NumZeros) {
4853 // Handling this case would require extra logic that would make this
4854 // transformation non-profitable
4855 return NULL__null;
4856 }
4857
4858 Val = AndLHS;
4859 Start = CurDAG->getTargetConstant(ShiftAmt, MVT::i32);
4860 Len = CurDAG->getTargetConstant(NumBits, MVT::i32);
4861 } else if (LHS->getOpcode() == ISD::SHL) {
4862 // Here, we have a pattern like:
4863 //
4864 // (sra (shl val, NN), MM)
4865 // or
4866 // (srl (shl val, NN), MM)
4867 //
4868 // If MM >= NN, we can efficiently optimize this with bfe
4869 Val = LHS->getOperand(0);
4870
4871 SDValue ShlRHS = LHS->getOperand(1);
4872 ConstantSDNode *ShlCnst = dyn_cast<ConstantSDNode>(ShlRHS);
4873 if (!ShlCnst) {
4874 // Shift amount must be constant
4875 return NULL__null;
4876 }
4877 uint64_t InnerShiftAmt = ShlCnst->getZExtValue();
4878
4879 SDValue ShrRHS = RHS;
4880 ConstantSDNode *ShrCnst = dyn_cast<ConstantSDNode>(ShrRHS);
4881 if (!ShrCnst) {
4882 // Shift amount must be constant
4883 return NULL__null;
4884 }
4885 uint64_t OuterShiftAmt = ShrCnst->getZExtValue();
4886
4887 // To avoid extra codegen and be profitable, we need Outer >= Inner
4888 if (OuterShiftAmt < InnerShiftAmt) {
4889 return NULL__null;
4890 }
4891
4892 // If the outer shift is more than the type size, we have no bitfield to
4893 // extract (since we also check that the inner shift is <= the outer shift
4894 // then this also implies that the inner shift is < the type size)
4895 if (OuterShiftAmt >= Val.getValueType().getSizeInBits()) {
4896 return NULL__null;
4897 }
4898
4899 Start =
4900 CurDAG->getTargetConstant(OuterShiftAmt - InnerShiftAmt, MVT::i32);
4901 Len =
4902 CurDAG->getTargetConstant(Val.getValueType().getSizeInBits() -
4903 OuterShiftAmt, MVT::i32);
4904
4905 if (N->getOpcode() == ISD::SRA) {
4906 // If we have a arithmetic right shift, we need to use the signed bfe
4907 // variant
4908 IsSigned = true;
4909 }
4910 } else {
4911 // No can do...
4912 return NULL__null;
4913 }
4914 } else {
4915 // No can do...
4916 return NULL__null;
4917 }
4918
4919
4920 unsigned Opc;
4921 // For the BFE operations we form here from "and" and "srl", always use the
4922 // unsigned variants.
4923 if (Val.getValueType() == MVT::i32) {
4924 if (IsSigned) {
4925 Opc = NVPTX::BFE_S32rii;
4926 } else {
4927 Opc = NVPTX::BFE_U32rii;
4928 }
4929 } else if (Val.getValueType() == MVT::i64) {
4930 if (IsSigned) {
4931 Opc = NVPTX::BFE_S64rii;
4932 } else {
4933 Opc = NVPTX::BFE_U64rii;
4934 }
4935 } else {
4936 // We cannot handle this type
4937 return NULL__null;
4938 }
4939
4940 SDValue Ops[] = {
4941 Val, Start, Len
4942 };
4943
4944 SDNode *Ret =
4945 CurDAG->getMachineNode(Opc, SDLoc(N), N->getVTList(), Ops);
4946
4947 return Ret;
4948}
4949
4950// SelectDirectAddr - Match a direct address for DAG.
4951// A direct address could be a globaladdress or externalsymbol.
4952bool NVPTXDAGToDAGISel::SelectDirectAddr(SDValue N, SDValue &Address) {
4953 // Return true if TGA or ES.
4954 if (N.getOpcode() == ISD::TargetGlobalAddress ||
4955 N.getOpcode() == ISD::TargetExternalSymbol) {
4956 Address = N;
4957 return true;
4958 }
4959 if (N.getOpcode() == NVPTXISD::Wrapper) {
4960 Address = N.getOperand(0);
4961 return true;
4962 }
4963 if (N.getOpcode() == ISD::INTRINSIC_WO_CHAIN) {
4964 unsigned IID = cast<ConstantSDNode>(N.getOperand(0))->getZExtValue();
4965 if (IID == Intrinsic::nvvm_ptr_gen_to_param)
4966 if (N.getOperand(1).getOpcode() == NVPTXISD::MoveParam)
4967 return (SelectDirectAddr(N.getOperand(1).getOperand(0), Address));
4968 }
4969 return false;
4970}
4971
4972// symbol+offset
4973bool NVPTXDAGToDAGISel::SelectADDRsi_imp(
4974 SDNode *OpNode, SDValue Addr, SDValue &Base, SDValue &Offset, MVT mvt) {
4975 if (Addr.getOpcode() == ISD::ADD) {
4976 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
4977 SDValue base = Addr.getOperand(0);
4978 if (SelectDirectAddr(base, Base)) {
4979 Offset = CurDAG->getTargetConstant(CN->getZExtValue(), mvt);
4980 return true;
4981 }
4982 }
4983 }
4984 return false;
4985}
4986
4987// symbol+offset
4988bool NVPTXDAGToDAGISel::SelectADDRsi(SDNode *OpNode, SDValue Addr,
4989 SDValue &Base, SDValue &Offset) {
4990 return SelectADDRsi_imp(OpNode, Addr, Base, Offset, MVT::i32);
4991}
4992
4993// symbol+offset
4994bool NVPTXDAGToDAGISel::SelectADDRsi64(SDNode *OpNode, SDValue Addr,
4995 SDValue &Base, SDValue &Offset) {
4996 return SelectADDRsi_imp(OpNode, Addr, Base, Offset, MVT::i64);
4997}
4998
4999// register+offset
5000bool NVPTXDAGToDAGISel::SelectADDRri_imp(
5001 SDNode *OpNode, SDValue Addr, SDValue &Base, SDValue &Offset, MVT mvt) {
5002 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
5003 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), mvt);
5004 Offset = CurDAG->getTargetConstant(0, mvt);
5005 return true;
5006 }
5007 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
5008 Addr.getOpcode() == ISD::TargetGlobalAddress)
5009 return false; // direct calls.
5010
5011 if (Addr.getOpcode() == ISD::ADD) {
5012 if (SelectDirectAddr(Addr.getOperand(0), Addr)) {
5013 return false;
5014 }
5015 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
5016 if (FrameIndexSDNode *FIN =
5017 dyn_cast<FrameIndexSDNode>(Addr.getOperand(0)))
5018 // Constant offset from frame ref.
5019 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), mvt);
5020 else
5021 Base = Addr.getOperand(0);
5022 Offset = CurDAG->getTargetConstant(CN->getZExtValue(), mvt);
5023 return true;
5024 }
5025 }
5026 return false;
5027}
5028
5029// register+offset
5030bool NVPTXDAGToDAGISel::SelectADDRri(SDNode *OpNode, SDValue Addr,
5031 SDValue &Base, SDValue &Offset) {
5032 return SelectADDRri_imp(OpNode, Addr, Base, Offset, MVT::i32);
5033}
5034
5035// register+offset
5036bool NVPTXDAGToDAGISel::SelectADDRri64(SDNode *OpNode, SDValue Addr,
5037 SDValue &Base, SDValue &Offset) {
5038 return SelectADDRri_imp(OpNode, Addr, Base, Offset, MVT::i64);
5039}
5040
5041bool NVPTXDAGToDAGISel::ChkMemSDNodeAddressSpace(SDNode *N,
5042 unsigned int spN) const {
5043 const Value *Src = nullptr;
5044 if (MemSDNode *mN = dyn_cast<MemSDNode>(N)) {
5045 if (spN == 0 && mN->getMemOperand()->getPseudoValue())
5046 return true;
5047 Src = mN->getMemOperand()->getValue();
5048 }
5049 if (!Src)
5050 return false;
5051 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
5052 return (PT->getAddressSpace() == spN);
5053 return false;
5054}
5055
5056/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
5057/// inline asm expressions.
5058bool NVPTXDAGToDAGISel::SelectInlineAsmMemoryOperand(
5059 const SDValue &Op, char ConstraintCode, std::vector<SDValue> &OutOps) {
5060 SDValue Op0, Op1;
5061 switch (ConstraintCode) {
5062 default:
5063 return true;
5064 case 'm': // memory
5065 if (SelectDirectAddr(Op, Op0)) {
5066 OutOps.push_back(Op0);
5067 OutOps.push_back(CurDAG->getTargetConstant(0, MVT::i32));
5068 return false;
5069 }
5070 if (SelectADDRri(Op.getNode(), Op, Op0, Op1)) {
5071 OutOps.push_back(Op0);
5072 OutOps.push_back(Op1);
5073 return false;
5074 }
5075 break;
5076 }
5077 return true;
5078}