Bug Summary

File:lib/Target/NVPTX/NVPTXISelLowering.cpp
Warning:line 242, column 33
Division by zero

Annotated Source Code

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clang -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name NVPTXISelLowering.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-eagerly-assume -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -mrelocation-model pic -pic-level 2 -mthread-model posix -fmath-errno -masm-verbose -mconstructor-aliases -munwind-tables -fuse-init-array -target-cpu x86-64 -dwarf-column-info -debugger-tuning=gdb -momit-leaf-frame-pointer -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-7/lib/clang/7.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-7~svn329677/build-llvm/lib/Target/NVPTX -I /build/llvm-toolchain-snapshot-7~svn329677/lib/Target/NVPTX -I /build/llvm-toolchain-snapshot-7~svn329677/build-llvm/include -I /build/llvm-toolchain-snapshot-7~svn329677/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/7.3.0/../../../../include/c++/7.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/7.3.0/../../../../include/x86_64-linux-gnu/c++/7.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/7.3.0/../../../../include/x86_64-linux-gnu/c++/7.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/7.3.0/../../../../include/c++/7.3.0/backward -internal-isystem /usr/include/clang/7.0.0/include/ -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-7/lib/clang/7.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++11 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-7~svn329677/build-llvm/lib/Target/NVPTX -ferror-limit 19 -fmessage-length 0 -fvisibility-inlines-hidden -fobjc-runtime=gcc -fdiagnostics-show-option -vectorize-loops -vectorize-slp -analyzer-checker optin.performance.Padding -analyzer-output=html -analyzer-config stable-report-filename=true -o /tmp/scan-build-2018-04-11-031539-24776-1 -x c++ /build/llvm-toolchain-snapshot-7~svn329677/lib/Target/NVPTX/NVPTXISelLowering.cpp
1//===-- NVPTXISelLowering.cpp - NVPTX DAG Lowering Implementation ---------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that NVPTX uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#include "NVPTXISelLowering.h"
16#include "MCTargetDesc/NVPTXBaseInfo.h"
17#include "NVPTX.h"
18#include "NVPTXSection.h"
19#include "NVPTXSubtarget.h"
20#include "NVPTXTargetMachine.h"
21#include "NVPTXTargetObjectFile.h"
22#include "NVPTXUtilities.h"
23#include "llvm/ADT/APInt.h"
24#include "llvm/ADT/SmallVector.h"
25#include "llvm/ADT/StringRef.h"
26#include "llvm/CodeGen/Analysis.h"
27#include "llvm/CodeGen/MachineFunction.h"
28#include "llvm/CodeGen/MachineMemOperand.h"
29#include "llvm/CodeGen/SelectionDAG.h"
30#include "llvm/CodeGen/SelectionDAGNodes.h"
31#include "llvm/CodeGen/TargetCallingConv.h"
32#include "llvm/CodeGen/TargetLowering.h"
33#include "llvm/CodeGen/ValueTypes.h"
34#include "llvm/IR/Argument.h"
35#include "llvm/IR/Attributes.h"
36#include "llvm/IR/CallSite.h"
37#include "llvm/IR/Constants.h"
38#include "llvm/IR/DataLayout.h"
39#include "llvm/IR/DerivedTypes.h"
40#include "llvm/IR/Function.h"
41#include "llvm/IR/GlobalValue.h"
42#include "llvm/IR/Instruction.h"
43#include "llvm/IR/Instructions.h"
44#include "llvm/IR/Module.h"
45#include "llvm/IR/Type.h"
46#include "llvm/IR/Value.h"
47#include "llvm/Support/Casting.h"
48#include "llvm/Support/CodeGen.h"
49#include "llvm/Support/CommandLine.h"
50#include "llvm/Support/ErrorHandling.h"
51#include "llvm/Support/MachineValueType.h"
52#include "llvm/Support/MathExtras.h"
53#include "llvm/Support/raw_ostream.h"
54#include "llvm/Target/TargetMachine.h"
55#include "llvm/Target/TargetOptions.h"
56#include <algorithm>
57#include <cassert>
58#include <cstdint>
59#include <iterator>
60#include <sstream>
61#include <string>
62#include <utility>
63#include <vector>
64
65#define DEBUG_TYPE"nvptx-lower" "nvptx-lower"
66
67using namespace llvm;
68
69static unsigned int uniqueCallSite = 0;
70
71static cl::opt<bool> sched4reg(
72 "nvptx-sched4reg",
73 cl::desc("NVPTX Specific: schedule for register pressue"), cl::init(false));
74
75static cl::opt<unsigned>
76FMAContractLevelOpt("nvptx-fma-level", cl::ZeroOrMore, cl::Hidden,
77 cl::desc("NVPTX Specific: FMA contraction (0: don't do it"
78 " 1: do it 2: do it aggressively"),
79 cl::init(2));
80
81static cl::opt<int> UsePrecDivF32(
82 "nvptx-prec-divf32", cl::ZeroOrMore, cl::Hidden,
83 cl::desc("NVPTX Specifies: 0 use div.approx, 1 use div.full, 2 use"
84 " IEEE Compliant F32 div.rnd if available."),
85 cl::init(2));
86
87static cl::opt<bool> UsePrecSqrtF32(
88 "nvptx-prec-sqrtf32", cl::Hidden,
89 cl::desc("NVPTX Specific: 0 use sqrt.approx, 1 use sqrt.rn."),
90 cl::init(true));
91
92static cl::opt<bool> FtzEnabled(
93 "nvptx-f32ftz", cl::ZeroOrMore, cl::Hidden,
94 cl::desc("NVPTX Specific: Flush f32 subnormals to sign-preserving zero."),
95 cl::init(false));
96
97int NVPTXTargetLowering::getDivF32Level() const {
98 if (UsePrecDivF32.getNumOccurrences() > 0) {
99 // If nvptx-prec-div32=N is used on the command-line, always honor it
100 return UsePrecDivF32;
101 } else {
102 // Otherwise, use div.approx if fast math is enabled
103 if (getTargetMachine().Options.UnsafeFPMath)
104 return 0;
105 else
106 return 2;
107 }
108}
109
110bool NVPTXTargetLowering::usePrecSqrtF32() const {
111 if (UsePrecSqrtF32.getNumOccurrences() > 0) {
112 // If nvptx-prec-sqrtf32 is used on the command-line, always honor it
113 return UsePrecSqrtF32;
114 } else {
115 // Otherwise, use sqrt.approx if fast math is enabled
116 return !getTargetMachine().Options.UnsafeFPMath;
117 }
118}
119
120bool NVPTXTargetLowering::useF32FTZ(const MachineFunction &MF) const {
121 // TODO: Get rid of this flag; there can be only one way to do this.
122 if (FtzEnabled.getNumOccurrences() > 0) {
123 // If nvptx-f32ftz is used on the command-line, always honor it
124 return FtzEnabled;
125 } else {
126 const Function &F = MF.getFunction();
127 // Otherwise, check for an nvptx-f32ftz attribute on the function
128 if (F.hasFnAttribute("nvptx-f32ftz"))
129 return F.getFnAttribute("nvptx-f32ftz").getValueAsString() == "true";
130 else
131 return false;
132 }
133}
134
135static bool IsPTXVectorType(MVT VT) {
136 switch (VT.SimpleTy) {
137 default:
138 return false;
139 case MVT::v2i1:
140 case MVT::v4i1:
141 case MVT::v2i8:
142 case MVT::v4i8:
143 case MVT::v2i16:
144 case MVT::v4i16:
145 case MVT::v2i32:
146 case MVT::v4i32:
147 case MVT::v2i64:
148 case MVT::v2f16:
149 case MVT::v4f16:
150 case MVT::v8f16: // <4 x f16x2>
151 case MVT::v2f32:
152 case MVT::v4f32:
153 case MVT::v2f64:
154 return true;
155 }
156}
157
158/// ComputePTXValueVTs - For the given Type \p Ty, returns the set of primitive
159/// EVTs that compose it. Unlike ComputeValueVTs, this will break apart vectors
160/// into their primitive components.
161/// NOTE: This is a band-aid for code that expects ComputeValueVTs to return the
162/// same number of types as the Ins/Outs arrays in LowerFormalArguments,
163/// LowerCall, and LowerReturn.
164static void ComputePTXValueVTs(const TargetLowering &TLI, const DataLayout &DL,
165 Type *Ty, SmallVectorImpl<EVT> &ValueVTs,
166 SmallVectorImpl<uint64_t> *Offsets = nullptr,
167 uint64_t StartingOffset = 0) {
168 SmallVector<EVT, 16> TempVTs;
169 SmallVector<uint64_t, 16> TempOffsets;
170
171 // Special case for i128 - decompose to (i64, i64)
172 if (Ty->isIntegerTy(128)) {
173 ValueVTs.push_back(EVT(MVT::i64));
174 ValueVTs.push_back(EVT(MVT::i64));
175
176 if (Offsets) {
177 Offsets->push_back(StartingOffset + 0);
178 Offsets->push_back(StartingOffset + 8);
179 }
180
181 return;
182 }
183
184 ComputeValueVTs(TLI, DL, Ty, TempVTs, &TempOffsets, StartingOffset);
185 for (unsigned i = 0, e = TempVTs.size(); i != e; ++i) {
186 EVT VT = TempVTs[i];
187 uint64_t Off = TempOffsets[i];
188 // Split vectors into individual elements, except for v2f16, which
189 // we will pass as a single scalar.
190 if (VT.isVector()) {
191 unsigned NumElts = VT.getVectorNumElements();
192 EVT EltVT = VT.getVectorElementType();
193 // Vectors with an even number of f16 elements will be passed to
194 // us as an array of v2f16 elements. We must match this so we
195 // stay in sync with Ins/Outs.
196 if (EltVT == MVT::f16 && NumElts % 2 == 0) {
197 EltVT = MVT::v2f16;
198 NumElts /= 2;
199 }
200 for (unsigned j = 0; j != NumElts; ++j) {
201 ValueVTs.push_back(EltVT);
202 if (Offsets)
203 Offsets->push_back(Off + j * EltVT.getStoreSize());
204 }
205 } else {
206 ValueVTs.push_back(VT);
207 if (Offsets)
208 Offsets->push_back(Off);
209 }
210 }
211}
212
213// Check whether we can merge loads/stores of some of the pieces of a
214// flattened function parameter or return value into a single vector
215// load/store.
216//
217// The flattened parameter is represented as a list of EVTs and
218// offsets, and the whole structure is aligned to ParamAlignment. This
219// function determines whether we can load/store pieces of the
220// parameter starting at index Idx using a single vectorized op of
221// size AccessSize. If so, it returns the number of param pieces
222// covered by the vector op. Otherwise, it returns 1.
223static unsigned CanMergeParamLoadStoresStartingAt(
224 unsigned Idx, uint32_t AccessSize, const SmallVectorImpl<EVT> &ValueVTs,
225 const SmallVectorImpl<uint64_t> &Offsets, unsigned ParamAlignment) {
226 assert(isPowerOf2_32(AccessSize) && "must be a power of 2!")(static_cast <bool> (isPowerOf2_32(AccessSize) &&
"must be a power of 2!") ? void (0) : __assert_fail ("isPowerOf2_32(AccessSize) && \"must be a power of 2!\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/NVPTX/NVPTXISelLowering.cpp"
, 226, __extension__ __PRETTY_FUNCTION__))
;
227
228 // Can't vectorize if param alignment is not sufficient.
229 if (AccessSize > ParamAlignment)
10
Assuming 'AccessSize' is <= 'ParamAlignment'
11
Taking false branch
230 return 1;
231 // Can't vectorize if offset is not aligned.
232 if (Offsets[Idx] & (AccessSize - 1))
12
Taking false branch
233 return 1;
234
235 EVT EltVT = ValueVTs[Idx];
236 unsigned EltSize = EltVT.getStoreSize();
13
Calling 'EVT::getStoreSize'
14
Returning from 'EVT::getStoreSize'
15
'EltSize' initialized here
237
238 // Element is too large to vectorize.
239 if (EltSize >= AccessSize)
16
Assuming 'EltSize' is < 'AccessSize'
17
Taking false branch
240 return 1;
241
242 unsigned NumElts = AccessSize / EltSize;
18
Division by zero
243 // Can't vectorize if AccessBytes if not a multiple of EltSize.
244 if (AccessSize != EltSize * NumElts)
245 return 1;
246
247 // We don't have enough elements to vectorize.
248 if (Idx + NumElts > ValueVTs.size())
249 return 1;
250
251 // PTX ISA can only deal with 2- and 4-element vector ops.
252 if (NumElts != 4 && NumElts != 2)
253 return 1;
254
255 for (unsigned j = Idx + 1; j < Idx + NumElts; ++j) {
256 // Types do not match.
257 if (ValueVTs[j] != EltVT)
258 return 1;
259
260 // Elements are not contiguous.
261 if (Offsets[j] - Offsets[j - 1] != EltSize)
262 return 1;
263 }
264 // OK. We can vectorize ValueVTs[i..i+NumElts)
265 return NumElts;
266}
267
268// Flags for tracking per-element vectorization state of loads/stores
269// of a flattened function parameter or return value.
270enum ParamVectorizationFlags {
271 PVF_INNER = 0x0, // Middle elements of a vector.
272 PVF_FIRST = 0x1, // First element of the vector.
273 PVF_LAST = 0x2, // Last element of the vector.
274 // Scalar is effectively a 1-element vector.
275 PVF_SCALAR = PVF_FIRST | PVF_LAST
276};
277
278// Computes whether and how we can vectorize the loads/stores of a
279// flattened function parameter or return value.
280//
281// The flattened parameter is represented as the list of ValueVTs and
282// Offsets, and is aligned to ParamAlignment bytes. We return a vector
283// of the same size as ValueVTs indicating how each piece should be
284// loaded/stored (i.e. as a scalar, or as part of a vector
285// load/store).
286static SmallVector<ParamVectorizationFlags, 16>
287VectorizePTXValueVTs(const SmallVectorImpl<EVT> &ValueVTs,
288 const SmallVectorImpl<uint64_t> &Offsets,
289 unsigned ParamAlignment) {
290 // Set vector size to match ValueVTs and mark all elements as
291 // scalars by default.
292 SmallVector<ParamVectorizationFlags, 16> VectorInfo;
293 VectorInfo.assign(ValueVTs.size(), PVF_SCALAR);
294
295 // Check what we can vectorize using 128/64/32-bit accesses.
296 for (int I = 0, E = ValueVTs.size(); I != E; ++I) {
6
Assuming 'I' is not equal to 'E'
7
Loop condition is true. Entering loop body
297 // Skip elements we've already processed.
298 assert(VectorInfo[I] == PVF_SCALAR && "Unexpected vector info state.")(static_cast <bool> (VectorInfo[I] == PVF_SCALAR &&
"Unexpected vector info state.") ? void (0) : __assert_fail (
"VectorInfo[I] == PVF_SCALAR && \"Unexpected vector info state.\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/NVPTX/NVPTXISelLowering.cpp"
, 298, __extension__ __PRETTY_FUNCTION__))
;
299 for (unsigned AccessSize : {16, 8, 4, 2}) {
8
Assuming '__begin2' is not equal to '__end2'
300 unsigned NumElts = CanMergeParamLoadStoresStartingAt(
9
Calling 'CanMergeParamLoadStoresStartingAt'
301 I, AccessSize, ValueVTs, Offsets, ParamAlignment);
302 // Mark vectorized elements.
303 switch (NumElts) {
304 default:
305 llvm_unreachable("Unexpected return value")::llvm::llvm_unreachable_internal("Unexpected return value", "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/NVPTX/NVPTXISelLowering.cpp"
, 305)
;
306 case 1:
307 // Can't vectorize using this size, try next smaller size.
308 continue;
309 case 2:
310 assert(I + 1 < E && "Not enough elements.")(static_cast <bool> (I + 1 < E && "Not enough elements."
) ? void (0) : __assert_fail ("I + 1 < E && \"Not enough elements.\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/NVPTX/NVPTXISelLowering.cpp"
, 310, __extension__ __PRETTY_FUNCTION__))
;
311 VectorInfo[I] = PVF_FIRST;
312 VectorInfo[I + 1] = PVF_LAST;
313 I += 1;
314 break;
315 case 4:
316 assert(I + 3 < E && "Not enough elements.")(static_cast <bool> (I + 3 < E && "Not enough elements."
) ? void (0) : __assert_fail ("I + 3 < E && \"Not enough elements.\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/NVPTX/NVPTXISelLowering.cpp"
, 316, __extension__ __PRETTY_FUNCTION__))
;
317 VectorInfo[I] = PVF_FIRST;
318 VectorInfo[I + 1] = PVF_INNER;
319 VectorInfo[I + 2] = PVF_INNER;
320 VectorInfo[I + 3] = PVF_LAST;
321 I += 3;
322 break;
323 }
324 // Break out of the inner loop because we've already succeeded
325 // using largest possible AccessSize.
326 break;
327 }
328 }
329 return VectorInfo;
330}
331
332// NVPTXTargetLowering Constructor.
333NVPTXTargetLowering::NVPTXTargetLowering(const NVPTXTargetMachine &TM,
334 const NVPTXSubtarget &STI)
335 : TargetLowering(TM), nvTM(&TM), STI(STI) {
336 // always lower memset, memcpy, and memmove intrinsics to load/store
337 // instructions, rather
338 // then generating calls to memset, mempcy or memmove.
339 MaxStoresPerMemset = (unsigned) 0xFFFFFFFF;
340 MaxStoresPerMemcpy = (unsigned) 0xFFFFFFFF;
341 MaxStoresPerMemmove = (unsigned) 0xFFFFFFFF;
342
343 setBooleanContents(ZeroOrNegativeOneBooleanContent);
344 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
345
346 // Jump is Expensive. Don't create extra control flow for 'and', 'or'
347 // condition branches.
348 setJumpIsExpensive(true);
349
350 // Wide divides are _very_ slow. Try to reduce the width of the divide if
351 // possible.
352 addBypassSlowDiv(64, 32);
353
354 // By default, use the Source scheduling
355 if (sched4reg)
356 setSchedulingPreference(Sched::RegPressure);
357 else
358 setSchedulingPreference(Sched::Source);
359
360 auto setFP16OperationAction = [&](unsigned Op, MVT VT, LegalizeAction Action,
361 LegalizeAction NoF16Action) {
362 setOperationAction(Op, VT, STI.allowFP16Math() ? Action : NoF16Action);
363 };
364
365 addRegisterClass(MVT::i1, &NVPTX::Int1RegsRegClass);
366 addRegisterClass(MVT::i16, &NVPTX::Int16RegsRegClass);
367 addRegisterClass(MVT::i32, &NVPTX::Int32RegsRegClass);
368 addRegisterClass(MVT::i64, &NVPTX::Int64RegsRegClass);
369 addRegisterClass(MVT::f32, &NVPTX::Float32RegsRegClass);
370 addRegisterClass(MVT::f64, &NVPTX::Float64RegsRegClass);
371 addRegisterClass(MVT::f16, &NVPTX::Float16RegsRegClass);
372 addRegisterClass(MVT::v2f16, &NVPTX::Float16x2RegsRegClass);
373
374 // Conversion to/from FP16/FP16x2 is always legal.
375 setOperationAction(ISD::SINT_TO_FP, MVT::f16, Legal);
376 setOperationAction(ISD::FP_TO_SINT, MVT::f16, Legal);
377 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f16, Custom);
378 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f16, Custom);
379
380 setFP16OperationAction(ISD::SETCC, MVT::f16, Legal, Promote);
381 setFP16OperationAction(ISD::SETCC, MVT::v2f16, Legal, Expand);
382
383 // Operations not directly supported by NVPTX.
384 setOperationAction(ISD::SELECT_CC, MVT::f16, Expand);
385 setOperationAction(ISD::SELECT_CC, MVT::v2f16, Expand);
386 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
387 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
388 setOperationAction(ISD::SELECT_CC, MVT::i1, Expand);
389 setOperationAction(ISD::SELECT_CC, MVT::i8, Expand);
390 setOperationAction(ISD::SELECT_CC, MVT::i16, Expand);
391 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
392 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
393 setOperationAction(ISD::BR_CC, MVT::f16, Expand);
394 setOperationAction(ISD::BR_CC, MVT::v2f16, Expand);
395 setOperationAction(ISD::BR_CC, MVT::f32, Expand);
396 setOperationAction(ISD::BR_CC, MVT::f64, Expand);
397 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
398 setOperationAction(ISD::BR_CC, MVT::i8, Expand);
399 setOperationAction(ISD::BR_CC, MVT::i16, Expand);
400 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
401 setOperationAction(ISD::BR_CC, MVT::i64, Expand);
402 // Some SIGN_EXTEND_INREG can be done using cvt instruction.
403 // For others we will expand to a SHL/SRA pair.
404 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i64, Legal);
405 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
406 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Legal);
407 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
408 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
409
410 setOperationAction(ISD::SHL_PARTS, MVT::i32 , Custom);
411 setOperationAction(ISD::SRA_PARTS, MVT::i32 , Custom);
412 setOperationAction(ISD::SRL_PARTS, MVT::i32 , Custom);
413 setOperationAction(ISD::SHL_PARTS, MVT::i64 , Custom);
414 setOperationAction(ISD::SRA_PARTS, MVT::i64 , Custom);
415 setOperationAction(ISD::SRL_PARTS, MVT::i64 , Custom);
416
417 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
418 setOperationAction(ISD::BITREVERSE, MVT::i64, Legal);
419
420 // TODO: we may consider expanding ROTL/ROTR on older GPUs. Currently on GPUs
421 // that don't have h/w rotation we lower them to multi-instruction assembly.
422 // See ROT*_sw in NVPTXIntrInfo.td
423 setOperationAction(ISD::ROTL, MVT::i64, Legal);
424 setOperationAction(ISD::ROTR, MVT::i64, Legal);
425 setOperationAction(ISD::ROTL, MVT::i32, Legal);
426 setOperationAction(ISD::ROTR, MVT::i32, Legal);
427
428 setOperationAction(ISD::ROTL, MVT::i16, Expand);
429 setOperationAction(ISD::ROTR, MVT::i16, Expand);
430 setOperationAction(ISD::ROTL, MVT::i8, Expand);
431 setOperationAction(ISD::ROTR, MVT::i8, Expand);
432 setOperationAction(ISD::BSWAP, MVT::i16, Expand);
433 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
434 setOperationAction(ISD::BSWAP, MVT::i64, Expand);
435
436 // Indirect branch is not supported.
437 // This also disables Jump Table creation.
438 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
439 setOperationAction(ISD::BRIND, MVT::Other, Expand);
440
441 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
442 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
443
444 // We want to legalize constant related memmove and memcopy
445 // intrinsics.
446 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
447
448 // Turn FP extload into load/fpextend
449 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
450 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
451 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand);
452 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, MVT::v2f16, Expand);
453 setLoadExtAction(ISD::EXTLOAD, MVT::v2f64, MVT::v2f16, Expand);
454 setLoadExtAction(ISD::EXTLOAD, MVT::v2f64, MVT::v2f32, Expand);
455 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, MVT::v4f16, Expand);
456 setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f16, Expand);
457 setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f32, Expand);
458 // Turn FP truncstore into trunc + store.
459 // FIXME: vector types should also be expanded
460 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
461 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
462 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
463
464 // PTX does not support load / store predicate registers
465 setOperationAction(ISD::LOAD, MVT::i1, Custom);
466 setOperationAction(ISD::STORE, MVT::i1, Custom);
467
468 for (MVT VT : MVT::integer_valuetypes()) {
469 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
470 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
471 setTruncStoreAction(VT, MVT::i1, Expand);
472 }
473
474 // This is legal in NVPTX
475 setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
476 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
477 setOperationAction(ISD::ConstantFP, MVT::f16, Legal);
478
479 // TRAP can be lowered to PTX trap
480 setOperationAction(ISD::TRAP, MVT::Other, Legal);
481
482 setOperationAction(ISD::ADDC, MVT::i64, Expand);
483 setOperationAction(ISD::ADDE, MVT::i64, Expand);
484
485 // Register custom handling for vector loads/stores
486 for (MVT VT : MVT::vector_valuetypes()) {
487 if (IsPTXVectorType(VT)) {
488 setOperationAction(ISD::LOAD, VT, Custom);
489 setOperationAction(ISD::STORE, VT, Custom);
490 setOperationAction(ISD::INTRINSIC_W_CHAIN, VT, Custom);
491 }
492 }
493
494 // Custom handling for i8 intrinsics
495 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i8, Custom);
496
497 for (const auto& Ty : {MVT::i16, MVT::i32, MVT::i64}) {
498 setOperationAction(ISD::ABS, Ty, Legal);
499 setOperationAction(ISD::SMIN, Ty, Legal);
500 setOperationAction(ISD::SMAX, Ty, Legal);
501 setOperationAction(ISD::UMIN, Ty, Legal);
502 setOperationAction(ISD::UMAX, Ty, Legal);
503
504 setOperationAction(ISD::CTPOP, Ty, Legal);
505 setOperationAction(ISD::CTLZ, Ty, Legal);
506 }
507
508 setOperationAction(ISD::CTTZ, MVT::i16, Expand);
509 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
510 setOperationAction(ISD::CTTZ, MVT::i64, Expand);
511
512 // PTX does not directly support SELP of i1, so promote to i32 first
513 setOperationAction(ISD::SELECT, MVT::i1, Custom);
514
515 // PTX cannot multiply two i64s in a single instruction.
516 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
517 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
518
519 // We have some custom DAG combine patterns for these nodes
520 setTargetDAGCombine(ISD::ADD);
521 setTargetDAGCombine(ISD::AND);
522 setTargetDAGCombine(ISD::FADD);
523 setTargetDAGCombine(ISD::MUL);
524 setTargetDAGCombine(ISD::SHL);
525 setTargetDAGCombine(ISD::SREM);
526 setTargetDAGCombine(ISD::UREM);
527
528 // setcc for f16x2 needs special handling to prevent legalizer's
529 // attempt to scalarize it due to v2i1 not being legal.
530 if (STI.allowFP16Math())
531 setTargetDAGCombine(ISD::SETCC);
532
533 // Promote fp16 arithmetic if fp16 hardware isn't available or the
534 // user passed --nvptx-no-fp16-math. The flag is useful because,
535 // although sm_53+ GPUs have some sort of FP16 support in
536 // hardware, only sm_53 and sm_60 have full implementation. Others
537 // only have token amount of hardware and are likely to run faster
538 // by using fp32 units instead.
539 for (const auto &Op : {ISD::FADD, ISD::FMUL, ISD::FSUB, ISD::FMA}) {
540 setFP16OperationAction(Op, MVT::f16, Legal, Promote);
541 setFP16OperationAction(Op, MVT::v2f16, Legal, Expand);
542 }
543
544 // There's no neg.f16 instruction. Expand to (0-x).
545 setOperationAction(ISD::FNEG, MVT::f16, Expand);
546 setOperationAction(ISD::FNEG, MVT::v2f16, Expand);
547
548 // (would be) Library functions.
549
550 // These map to conversion instructions for scalar FP types.
551 for (const auto &Op : {ISD::FCEIL, ISD::FFLOOR, ISD::FNEARBYINT, ISD::FRINT,
552 ISD::FROUND, ISD::FTRUNC}) {
553 setOperationAction(Op, MVT::f16, Legal);
554 setOperationAction(Op, MVT::f32, Legal);
555 setOperationAction(Op, MVT::f64, Legal);
556 setOperationAction(Op, MVT::v2f16, Expand);
557 }
558
559 // 'Expand' implements FCOPYSIGN without calling an external library.
560 setOperationAction(ISD::FCOPYSIGN, MVT::f16, Expand);
561 setOperationAction(ISD::FCOPYSIGN, MVT::v2f16, Expand);
562 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
563 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
564
565 // These map to corresponding instructions for f32/f64. f16 must be
566 // promoted to f32. v2f16 is expanded to f16, which is then promoted
567 // to f32.
568 for (const auto &Op : {ISD::FDIV, ISD::FREM, ISD::FSQRT, ISD::FSIN, ISD::FCOS,
569 ISD::FABS, ISD::FMINNUM, ISD::FMAXNUM}) {
570 setOperationAction(Op, MVT::f16, Promote);
571 setOperationAction(Op, MVT::f32, Legal);
572 setOperationAction(Op, MVT::f64, Legal);
573 setOperationAction(Op, MVT::v2f16, Expand);
574 }
575 setOperationAction(ISD::FMINNUM, MVT::f16, Promote);
576 setOperationAction(ISD::FMAXNUM, MVT::f16, Promote);
577 setOperationAction(ISD::FMINNAN, MVT::f16, Promote);
578 setOperationAction(ISD::FMAXNAN, MVT::f16, Promote);
579
580 // No FEXP2, FLOG2. The PTX ex2 and log2 functions are always approximate.
581 // No FPOW or FREM in PTX.
582
583 // Now deduce the information based on the above mentioned
584 // actions
585 computeRegisterProperties(STI.getRegisterInfo());
586}
587
588const char *NVPTXTargetLowering::getTargetNodeName(unsigned Opcode) const {
589 switch ((NVPTXISD::NodeType)Opcode) {
590 case NVPTXISD::FIRST_NUMBER:
591 break;
592 case NVPTXISD::CALL:
593 return "NVPTXISD::CALL";
594 case NVPTXISD::RET_FLAG:
595 return "NVPTXISD::RET_FLAG";
596 case NVPTXISD::LOAD_PARAM:
597 return "NVPTXISD::LOAD_PARAM";
598 case NVPTXISD::Wrapper:
599 return "NVPTXISD::Wrapper";
600 case NVPTXISD::DeclareParam:
601 return "NVPTXISD::DeclareParam";
602 case NVPTXISD::DeclareScalarParam:
603 return "NVPTXISD::DeclareScalarParam";
604 case NVPTXISD::DeclareRet:
605 return "NVPTXISD::DeclareRet";
606 case NVPTXISD::DeclareScalarRet:
607 return "NVPTXISD::DeclareScalarRet";
608 case NVPTXISD::DeclareRetParam:
609 return "NVPTXISD::DeclareRetParam";
610 case NVPTXISD::PrintCall:
611 return "NVPTXISD::PrintCall";
612 case NVPTXISD::PrintConvergentCall:
613 return "NVPTXISD::PrintConvergentCall";
614 case NVPTXISD::PrintCallUni:
615 return "NVPTXISD::PrintCallUni";
616 case NVPTXISD::PrintConvergentCallUni:
617 return "NVPTXISD::PrintConvergentCallUni";
618 case NVPTXISD::LoadParam:
619 return "NVPTXISD::LoadParam";
620 case NVPTXISD::LoadParamV2:
621 return "NVPTXISD::LoadParamV2";
622 case NVPTXISD::LoadParamV4:
623 return "NVPTXISD::LoadParamV4";
624 case NVPTXISD::StoreParam:
625 return "NVPTXISD::StoreParam";
626 case NVPTXISD::StoreParamV2:
627 return "NVPTXISD::StoreParamV2";
628 case NVPTXISD::StoreParamV4:
629 return "NVPTXISD::StoreParamV4";
630 case NVPTXISD::StoreParamS32:
631 return "NVPTXISD::StoreParamS32";
632 case NVPTXISD::StoreParamU32:
633 return "NVPTXISD::StoreParamU32";
634 case NVPTXISD::CallArgBegin:
635 return "NVPTXISD::CallArgBegin";
636 case NVPTXISD::CallArg:
637 return "NVPTXISD::CallArg";
638 case NVPTXISD::LastCallArg:
639 return "NVPTXISD::LastCallArg";
640 case NVPTXISD::CallArgEnd:
641 return "NVPTXISD::CallArgEnd";
642 case NVPTXISD::CallVoid:
643 return "NVPTXISD::CallVoid";
644 case NVPTXISD::CallVal:
645 return "NVPTXISD::CallVal";
646 case NVPTXISD::CallSymbol:
647 return "NVPTXISD::CallSymbol";
648 case NVPTXISD::Prototype:
649 return "NVPTXISD::Prototype";
650 case NVPTXISD::MoveParam:
651 return "NVPTXISD::MoveParam";
652 case NVPTXISD::StoreRetval:
653 return "NVPTXISD::StoreRetval";
654 case NVPTXISD::StoreRetvalV2:
655 return "NVPTXISD::StoreRetvalV2";
656 case NVPTXISD::StoreRetvalV4:
657 return "NVPTXISD::StoreRetvalV4";
658 case NVPTXISD::PseudoUseParam:
659 return "NVPTXISD::PseudoUseParam";
660 case NVPTXISD::RETURN:
661 return "NVPTXISD::RETURN";
662 case NVPTXISD::CallSeqBegin:
663 return "NVPTXISD::CallSeqBegin";
664 case NVPTXISD::CallSeqEnd:
665 return "NVPTXISD::CallSeqEnd";
666 case NVPTXISD::CallPrototype:
667 return "NVPTXISD::CallPrototype";
668 case NVPTXISD::LoadV2:
669 return "NVPTXISD::LoadV2";
670 case NVPTXISD::LoadV4:
671 return "NVPTXISD::LoadV4";
672 case NVPTXISD::LDGV2:
673 return "NVPTXISD::LDGV2";
674 case NVPTXISD::LDGV4:
675 return "NVPTXISD::LDGV4";
676 case NVPTXISD::LDUV2:
677 return "NVPTXISD::LDUV2";
678 case NVPTXISD::LDUV4:
679 return "NVPTXISD::LDUV4";
680 case NVPTXISD::StoreV2:
681 return "NVPTXISD::StoreV2";
682 case NVPTXISD::StoreV4:
683 return "NVPTXISD::StoreV4";
684 case NVPTXISD::FUN_SHFL_CLAMP:
685 return "NVPTXISD::FUN_SHFL_CLAMP";
686 case NVPTXISD::FUN_SHFR_CLAMP:
687 return "NVPTXISD::FUN_SHFR_CLAMP";
688 case NVPTXISD::IMAD:
689 return "NVPTXISD::IMAD";
690 case NVPTXISD::SETP_F16X2:
691 return "NVPTXISD::SETP_F16X2";
692 case NVPTXISD::Dummy:
693 return "NVPTXISD::Dummy";
694 case NVPTXISD::MUL_WIDE_SIGNED:
695 return "NVPTXISD::MUL_WIDE_SIGNED";
696 case NVPTXISD::MUL_WIDE_UNSIGNED:
697 return "NVPTXISD::MUL_WIDE_UNSIGNED";
698 case NVPTXISD::Tex1DFloatS32: return "NVPTXISD::Tex1DFloatS32";
699 case NVPTXISD::Tex1DFloatFloat: return "NVPTXISD::Tex1DFloatFloat";
700 case NVPTXISD::Tex1DFloatFloatLevel:
701 return "NVPTXISD::Tex1DFloatFloatLevel";
702 case NVPTXISD::Tex1DFloatFloatGrad:
703 return "NVPTXISD::Tex1DFloatFloatGrad";
704 case NVPTXISD::Tex1DS32S32: return "NVPTXISD::Tex1DS32S32";
705 case NVPTXISD::Tex1DS32Float: return "NVPTXISD::Tex1DS32Float";
706 case NVPTXISD::Tex1DS32FloatLevel:
707 return "NVPTXISD::Tex1DS32FloatLevel";
708 case NVPTXISD::Tex1DS32FloatGrad:
709 return "NVPTXISD::Tex1DS32FloatGrad";
710 case NVPTXISD::Tex1DU32S32: return "NVPTXISD::Tex1DU32S32";
711 case NVPTXISD::Tex1DU32Float: return "NVPTXISD::Tex1DU32Float";
712 case NVPTXISD::Tex1DU32FloatLevel:
713 return "NVPTXISD::Tex1DU32FloatLevel";
714 case NVPTXISD::Tex1DU32FloatGrad:
715 return "NVPTXISD::Tex1DU32FloatGrad";
716 case NVPTXISD::Tex1DArrayFloatS32: return "NVPTXISD::Tex1DArrayFloatS32";
717 case NVPTXISD::Tex1DArrayFloatFloat: return "NVPTXISD::Tex1DArrayFloatFloat";
718 case NVPTXISD::Tex1DArrayFloatFloatLevel:
719 return "NVPTXISD::Tex1DArrayFloatFloatLevel";
720 case NVPTXISD::Tex1DArrayFloatFloatGrad:
721 return "NVPTXISD::Tex1DArrayFloatFloatGrad";
722 case NVPTXISD::Tex1DArrayS32S32: return "NVPTXISD::Tex1DArrayS32S32";
723 case NVPTXISD::Tex1DArrayS32Float: return "NVPTXISD::Tex1DArrayS32Float";
724 case NVPTXISD::Tex1DArrayS32FloatLevel:
725 return "NVPTXISD::Tex1DArrayS32FloatLevel";
726 case NVPTXISD::Tex1DArrayS32FloatGrad:
727 return "NVPTXISD::Tex1DArrayS32FloatGrad";
728 case NVPTXISD::Tex1DArrayU32S32: return "NVPTXISD::Tex1DArrayU32S32";
729 case NVPTXISD::Tex1DArrayU32Float: return "NVPTXISD::Tex1DArrayU32Float";
730 case NVPTXISD::Tex1DArrayU32FloatLevel:
731 return "NVPTXISD::Tex1DArrayU32FloatLevel";
732 case NVPTXISD::Tex1DArrayU32FloatGrad:
733 return "NVPTXISD::Tex1DArrayU32FloatGrad";
734 case NVPTXISD::Tex2DFloatS32: return "NVPTXISD::Tex2DFloatS32";
735 case NVPTXISD::Tex2DFloatFloat: return "NVPTXISD::Tex2DFloatFloat";
736 case NVPTXISD::Tex2DFloatFloatLevel:
737 return "NVPTXISD::Tex2DFloatFloatLevel";
738 case NVPTXISD::Tex2DFloatFloatGrad:
739 return "NVPTXISD::Tex2DFloatFloatGrad";
740 case NVPTXISD::Tex2DS32S32: return "NVPTXISD::Tex2DS32S32";
741 case NVPTXISD::Tex2DS32Float: return "NVPTXISD::Tex2DS32Float";
742 case NVPTXISD::Tex2DS32FloatLevel:
743 return "NVPTXISD::Tex2DS32FloatLevel";
744 case NVPTXISD::Tex2DS32FloatGrad:
745 return "NVPTXISD::Tex2DS32FloatGrad";
746 case NVPTXISD::Tex2DU32S32: return "NVPTXISD::Tex2DU32S32";
747 case NVPTXISD::Tex2DU32Float: return "NVPTXISD::Tex2DU32Float";
748 case NVPTXISD::Tex2DU32FloatLevel:
749 return "NVPTXISD::Tex2DU32FloatLevel";
750 case NVPTXISD::Tex2DU32FloatGrad:
751 return "NVPTXISD::Tex2DU32FloatGrad";
752 case NVPTXISD::Tex2DArrayFloatS32: return "NVPTXISD::Tex2DArrayFloatS32";
753 case NVPTXISD::Tex2DArrayFloatFloat: return "NVPTXISD::Tex2DArrayFloatFloat";
754 case NVPTXISD::Tex2DArrayFloatFloatLevel:
755 return "NVPTXISD::Tex2DArrayFloatFloatLevel";
756 case NVPTXISD::Tex2DArrayFloatFloatGrad:
757 return "NVPTXISD::Tex2DArrayFloatFloatGrad";
758 case NVPTXISD::Tex2DArrayS32S32: return "NVPTXISD::Tex2DArrayS32S32";
759 case NVPTXISD::Tex2DArrayS32Float: return "NVPTXISD::Tex2DArrayS32Float";
760 case NVPTXISD::Tex2DArrayS32FloatLevel:
761 return "NVPTXISD::Tex2DArrayS32FloatLevel";
762 case NVPTXISD::Tex2DArrayS32FloatGrad:
763 return "NVPTXISD::Tex2DArrayS32FloatGrad";
764 case NVPTXISD::Tex2DArrayU32S32: return "NVPTXISD::Tex2DArrayU32S32";
765 case NVPTXISD::Tex2DArrayU32Float: return "NVPTXISD::Tex2DArrayU32Float";
766 case NVPTXISD::Tex2DArrayU32FloatLevel:
767 return "NVPTXISD::Tex2DArrayU32FloatLevel";
768 case NVPTXISD::Tex2DArrayU32FloatGrad:
769 return "NVPTXISD::Tex2DArrayU32FloatGrad";
770 case NVPTXISD::Tex3DFloatS32: return "NVPTXISD::Tex3DFloatS32";
771 case NVPTXISD::Tex3DFloatFloat: return "NVPTXISD::Tex3DFloatFloat";
772 case NVPTXISD::Tex3DFloatFloatLevel:
773 return "NVPTXISD::Tex3DFloatFloatLevel";
774 case NVPTXISD::Tex3DFloatFloatGrad:
775 return "NVPTXISD::Tex3DFloatFloatGrad";
776 case NVPTXISD::Tex3DS32S32: return "NVPTXISD::Tex3DS32S32";
777 case NVPTXISD::Tex3DS32Float: return "NVPTXISD::Tex3DS32Float";
778 case NVPTXISD::Tex3DS32FloatLevel:
779 return "NVPTXISD::Tex3DS32FloatLevel";
780 case NVPTXISD::Tex3DS32FloatGrad:
781 return "NVPTXISD::Tex3DS32FloatGrad";
782 case NVPTXISD::Tex3DU32S32: return "NVPTXISD::Tex3DU32S32";
783 case NVPTXISD::Tex3DU32Float: return "NVPTXISD::Tex3DU32Float";
784 case NVPTXISD::Tex3DU32FloatLevel:
785 return "NVPTXISD::Tex3DU32FloatLevel";
786 case NVPTXISD::Tex3DU32FloatGrad:
787 return "NVPTXISD::Tex3DU32FloatGrad";
788 case NVPTXISD::TexCubeFloatFloat: return "NVPTXISD::TexCubeFloatFloat";
789 case NVPTXISD::TexCubeFloatFloatLevel:
790 return "NVPTXISD::TexCubeFloatFloatLevel";
791 case NVPTXISD::TexCubeS32Float: return "NVPTXISD::TexCubeS32Float";
792 case NVPTXISD::TexCubeS32FloatLevel:
793 return "NVPTXISD::TexCubeS32FloatLevel";
794 case NVPTXISD::TexCubeU32Float: return "NVPTXISD::TexCubeU32Float";
795 case NVPTXISD::TexCubeU32FloatLevel:
796 return "NVPTXISD::TexCubeU32FloatLevel";
797 case NVPTXISD::TexCubeArrayFloatFloat:
798 return "NVPTXISD::TexCubeArrayFloatFloat";
799 case NVPTXISD::TexCubeArrayFloatFloatLevel:
800 return "NVPTXISD::TexCubeArrayFloatFloatLevel";
801 case NVPTXISD::TexCubeArrayS32Float:
802 return "NVPTXISD::TexCubeArrayS32Float";
803 case NVPTXISD::TexCubeArrayS32FloatLevel:
804 return "NVPTXISD::TexCubeArrayS32FloatLevel";
805 case NVPTXISD::TexCubeArrayU32Float:
806 return "NVPTXISD::TexCubeArrayU32Float";
807 case NVPTXISD::TexCubeArrayU32FloatLevel:
808 return "NVPTXISD::TexCubeArrayU32FloatLevel";
809 case NVPTXISD::Tld4R2DFloatFloat:
810 return "NVPTXISD::Tld4R2DFloatFloat";
811 case NVPTXISD::Tld4G2DFloatFloat:
812 return "NVPTXISD::Tld4G2DFloatFloat";
813 case NVPTXISD::Tld4B2DFloatFloat:
814 return "NVPTXISD::Tld4B2DFloatFloat";
815 case NVPTXISD::Tld4A2DFloatFloat:
816 return "NVPTXISD::Tld4A2DFloatFloat";
817 case NVPTXISD::Tld4R2DS64Float:
818 return "NVPTXISD::Tld4R2DS64Float";
819 case NVPTXISD::Tld4G2DS64Float:
820 return "NVPTXISD::Tld4G2DS64Float";
821 case NVPTXISD::Tld4B2DS64Float:
822 return "NVPTXISD::Tld4B2DS64Float";
823 case NVPTXISD::Tld4A2DS64Float:
824 return "NVPTXISD::Tld4A2DS64Float";
825 case NVPTXISD::Tld4R2DU64Float:
826 return "NVPTXISD::Tld4R2DU64Float";
827 case NVPTXISD::Tld4G2DU64Float:
828 return "NVPTXISD::Tld4G2DU64Float";
829 case NVPTXISD::Tld4B2DU64Float:
830 return "NVPTXISD::Tld4B2DU64Float";
831 case NVPTXISD::Tld4A2DU64Float:
832 return "NVPTXISD::Tld4A2DU64Float";
833
834 case NVPTXISD::TexUnified1DFloatS32:
835 return "NVPTXISD::TexUnified1DFloatS32";
836 case NVPTXISD::TexUnified1DFloatFloat:
837 return "NVPTXISD::TexUnified1DFloatFloat";
838 case NVPTXISD::TexUnified1DFloatFloatLevel:
839 return "NVPTXISD::TexUnified1DFloatFloatLevel";
840 case NVPTXISD::TexUnified1DFloatFloatGrad:
841 return "NVPTXISD::TexUnified1DFloatFloatGrad";
842 case NVPTXISD::TexUnified1DS32S32:
843 return "NVPTXISD::TexUnified1DS32S32";
844 case NVPTXISD::TexUnified1DS32Float:
845 return "NVPTXISD::TexUnified1DS32Float";
846 case NVPTXISD::TexUnified1DS32FloatLevel:
847 return "NVPTXISD::TexUnified1DS32FloatLevel";
848 case NVPTXISD::TexUnified1DS32FloatGrad:
849 return "NVPTXISD::TexUnified1DS32FloatGrad";
850 case NVPTXISD::TexUnified1DU32S32:
851 return "NVPTXISD::TexUnified1DU32S32";
852 case NVPTXISD::TexUnified1DU32Float:
853 return "NVPTXISD::TexUnified1DU32Float";
854 case NVPTXISD::TexUnified1DU32FloatLevel:
855 return "NVPTXISD::TexUnified1DU32FloatLevel";
856 case NVPTXISD::TexUnified1DU32FloatGrad:
857 return "NVPTXISD::TexUnified1DU32FloatGrad";
858 case NVPTXISD::TexUnified1DArrayFloatS32:
859 return "NVPTXISD::TexUnified1DArrayFloatS32";
860 case NVPTXISD::TexUnified1DArrayFloatFloat:
861 return "NVPTXISD::TexUnified1DArrayFloatFloat";
862 case NVPTXISD::TexUnified1DArrayFloatFloatLevel:
863 return "NVPTXISD::TexUnified1DArrayFloatFloatLevel";
864 case NVPTXISD::TexUnified1DArrayFloatFloatGrad:
865 return "NVPTXISD::TexUnified1DArrayFloatFloatGrad";
866 case NVPTXISD::TexUnified1DArrayS32S32:
867 return "NVPTXISD::TexUnified1DArrayS32S32";
868 case NVPTXISD::TexUnified1DArrayS32Float:
869 return "NVPTXISD::TexUnified1DArrayS32Float";
870 case NVPTXISD::TexUnified1DArrayS32FloatLevel:
871 return "NVPTXISD::TexUnified1DArrayS32FloatLevel";
872 case NVPTXISD::TexUnified1DArrayS32FloatGrad:
873 return "NVPTXISD::TexUnified1DArrayS32FloatGrad";
874 case NVPTXISD::TexUnified1DArrayU32S32:
875 return "NVPTXISD::TexUnified1DArrayU32S32";
876 case NVPTXISD::TexUnified1DArrayU32Float:
877 return "NVPTXISD::TexUnified1DArrayU32Float";
878 case NVPTXISD::TexUnified1DArrayU32FloatLevel:
879 return "NVPTXISD::TexUnified1DArrayU32FloatLevel";
880 case NVPTXISD::TexUnified1DArrayU32FloatGrad:
881 return "NVPTXISD::TexUnified1DArrayU32FloatGrad";
882 case NVPTXISD::TexUnified2DFloatS32:
883 return "NVPTXISD::TexUnified2DFloatS32";
884 case NVPTXISD::TexUnified2DFloatFloat:
885 return "NVPTXISD::TexUnified2DFloatFloat";
886 case NVPTXISD::TexUnified2DFloatFloatLevel:
887 return "NVPTXISD::TexUnified2DFloatFloatLevel";
888 case NVPTXISD::TexUnified2DFloatFloatGrad:
889 return "NVPTXISD::TexUnified2DFloatFloatGrad";
890 case NVPTXISD::TexUnified2DS32S32:
891 return "NVPTXISD::TexUnified2DS32S32";
892 case NVPTXISD::TexUnified2DS32Float:
893 return "NVPTXISD::TexUnified2DS32Float";
894 case NVPTXISD::TexUnified2DS32FloatLevel:
895 return "NVPTXISD::TexUnified2DS32FloatLevel";
896 case NVPTXISD::TexUnified2DS32FloatGrad:
897 return "NVPTXISD::TexUnified2DS32FloatGrad";
898 case NVPTXISD::TexUnified2DU32S32:
899 return "NVPTXISD::TexUnified2DU32S32";
900 case NVPTXISD::TexUnified2DU32Float:
901 return "NVPTXISD::TexUnified2DU32Float";
902 case NVPTXISD::TexUnified2DU32FloatLevel:
903 return "NVPTXISD::TexUnified2DU32FloatLevel";
904 case NVPTXISD::TexUnified2DU32FloatGrad:
905 return "NVPTXISD::TexUnified2DU32FloatGrad";
906 case NVPTXISD::TexUnified2DArrayFloatS32:
907 return "NVPTXISD::TexUnified2DArrayFloatS32";
908 case NVPTXISD::TexUnified2DArrayFloatFloat:
909 return "NVPTXISD::TexUnified2DArrayFloatFloat";
910 case NVPTXISD::TexUnified2DArrayFloatFloatLevel:
911 return "NVPTXISD::TexUnified2DArrayFloatFloatLevel";
912 case NVPTXISD::TexUnified2DArrayFloatFloatGrad:
913 return "NVPTXISD::TexUnified2DArrayFloatFloatGrad";
914 case NVPTXISD::TexUnified2DArrayS32S32:
915 return "NVPTXISD::TexUnified2DArrayS32S32";
916 case NVPTXISD::TexUnified2DArrayS32Float:
917 return "NVPTXISD::TexUnified2DArrayS32Float";
918 case NVPTXISD::TexUnified2DArrayS32FloatLevel:
919 return "NVPTXISD::TexUnified2DArrayS32FloatLevel";
920 case NVPTXISD::TexUnified2DArrayS32FloatGrad:
921 return "NVPTXISD::TexUnified2DArrayS32FloatGrad";
922 case NVPTXISD::TexUnified2DArrayU32S32:
923 return "NVPTXISD::TexUnified2DArrayU32S32";
924 case NVPTXISD::TexUnified2DArrayU32Float:
925 return "NVPTXISD::TexUnified2DArrayU32Float";
926 case NVPTXISD::TexUnified2DArrayU32FloatLevel:
927 return "NVPTXISD::TexUnified2DArrayU32FloatLevel";
928 case NVPTXISD::TexUnified2DArrayU32FloatGrad:
929 return "NVPTXISD::TexUnified2DArrayU32FloatGrad";
930 case NVPTXISD::TexUnified3DFloatS32:
931 return "NVPTXISD::TexUnified3DFloatS32";
932 case NVPTXISD::TexUnified3DFloatFloat:
933 return "NVPTXISD::TexUnified3DFloatFloat";
934 case NVPTXISD::TexUnified3DFloatFloatLevel:
935 return "NVPTXISD::TexUnified3DFloatFloatLevel";
936 case NVPTXISD::TexUnified3DFloatFloatGrad:
937 return "NVPTXISD::TexUnified3DFloatFloatGrad";
938 case NVPTXISD::TexUnified3DS32S32:
939 return "NVPTXISD::TexUnified3DS32S32";
940 case NVPTXISD::TexUnified3DS32Float:
941 return "NVPTXISD::TexUnified3DS32Float";
942 case NVPTXISD::TexUnified3DS32FloatLevel:
943 return "NVPTXISD::TexUnified3DS32FloatLevel";
944 case NVPTXISD::TexUnified3DS32FloatGrad:
945 return "NVPTXISD::TexUnified3DS32FloatGrad";
946 case NVPTXISD::TexUnified3DU32S32:
947 return "NVPTXISD::TexUnified3DU32S32";
948 case NVPTXISD::TexUnified3DU32Float:
949 return "NVPTXISD::TexUnified3DU32Float";
950 case NVPTXISD::TexUnified3DU32FloatLevel:
951 return "NVPTXISD::TexUnified3DU32FloatLevel";
952 case NVPTXISD::TexUnified3DU32FloatGrad:
953 return "NVPTXISD::TexUnified3DU32FloatGrad";
954 case NVPTXISD::TexUnifiedCubeFloatFloat:
955 return "NVPTXISD::TexUnifiedCubeFloatFloat";
956 case NVPTXISD::TexUnifiedCubeFloatFloatLevel:
957 return "NVPTXISD::TexUnifiedCubeFloatFloatLevel";
958 case NVPTXISD::TexUnifiedCubeS32Float:
959 return "NVPTXISD::TexUnifiedCubeS32Float";
960 case NVPTXISD::TexUnifiedCubeS32FloatLevel:
961 return "NVPTXISD::TexUnifiedCubeS32FloatLevel";
962 case NVPTXISD::TexUnifiedCubeU32Float:
963 return "NVPTXISD::TexUnifiedCubeU32Float";
964 case NVPTXISD::TexUnifiedCubeU32FloatLevel:
965 return "NVPTXISD::TexUnifiedCubeU32FloatLevel";
966 case NVPTXISD::TexUnifiedCubeArrayFloatFloat:
967 return "NVPTXISD::TexUnifiedCubeArrayFloatFloat";
968 case NVPTXISD::TexUnifiedCubeArrayFloatFloatLevel:
969 return "NVPTXISD::TexUnifiedCubeArrayFloatFloatLevel";
970 case NVPTXISD::TexUnifiedCubeArrayS32Float:
971 return "NVPTXISD::TexUnifiedCubeArrayS32Float";
972 case NVPTXISD::TexUnifiedCubeArrayS32FloatLevel:
973 return "NVPTXISD::TexUnifiedCubeArrayS32FloatLevel";
974 case NVPTXISD::TexUnifiedCubeArrayU32Float:
975 return "NVPTXISD::TexUnifiedCubeArrayU32Float";
976 case NVPTXISD::TexUnifiedCubeArrayU32FloatLevel:
977 return "NVPTXISD::TexUnifiedCubeArrayU32FloatLevel";
978 case NVPTXISD::Tld4UnifiedR2DFloatFloat:
979 return "NVPTXISD::Tld4UnifiedR2DFloatFloat";
980 case NVPTXISD::Tld4UnifiedG2DFloatFloat:
981 return "NVPTXISD::Tld4UnifiedG2DFloatFloat";
982 case NVPTXISD::Tld4UnifiedB2DFloatFloat:
983 return "NVPTXISD::Tld4UnifiedB2DFloatFloat";
984 case NVPTXISD::Tld4UnifiedA2DFloatFloat:
985 return "NVPTXISD::Tld4UnifiedA2DFloatFloat";
986 case NVPTXISD::Tld4UnifiedR2DS64Float:
987 return "NVPTXISD::Tld4UnifiedR2DS64Float";
988 case NVPTXISD::Tld4UnifiedG2DS64Float:
989 return "NVPTXISD::Tld4UnifiedG2DS64Float";
990 case NVPTXISD::Tld4UnifiedB2DS64Float:
991 return "NVPTXISD::Tld4UnifiedB2DS64Float";
992 case NVPTXISD::Tld4UnifiedA2DS64Float:
993 return "NVPTXISD::Tld4UnifiedA2DS64Float";
994 case NVPTXISD::Tld4UnifiedR2DU64Float:
995 return "NVPTXISD::Tld4UnifiedR2DU64Float";
996 case NVPTXISD::Tld4UnifiedG2DU64Float:
997 return "NVPTXISD::Tld4UnifiedG2DU64Float";
998 case NVPTXISD::Tld4UnifiedB2DU64Float:
999 return "NVPTXISD::Tld4UnifiedB2DU64Float";
1000 case NVPTXISD::Tld4UnifiedA2DU64Float:
1001 return "NVPTXISD::Tld4UnifiedA2DU64Float";
1002
1003 case NVPTXISD::Suld1DI8Clamp: return "NVPTXISD::Suld1DI8Clamp";
1004 case NVPTXISD::Suld1DI16Clamp: return "NVPTXISD::Suld1DI16Clamp";
1005 case NVPTXISD::Suld1DI32Clamp: return "NVPTXISD::Suld1DI32Clamp";
1006 case NVPTXISD::Suld1DI64Clamp: return "NVPTXISD::Suld1DI64Clamp";
1007 case NVPTXISD::Suld1DV2I8Clamp: return "NVPTXISD::Suld1DV2I8Clamp";
1008 case NVPTXISD::Suld1DV2I16Clamp: return "NVPTXISD::Suld1DV2I16Clamp";
1009 case NVPTXISD::Suld1DV2I32Clamp: return "NVPTXISD::Suld1DV2I32Clamp";
1010 case NVPTXISD::Suld1DV2I64Clamp: return "NVPTXISD::Suld1DV2I64Clamp";
1011 case NVPTXISD::Suld1DV4I8Clamp: return "NVPTXISD::Suld1DV4I8Clamp";
1012 case NVPTXISD::Suld1DV4I16Clamp: return "NVPTXISD::Suld1DV4I16Clamp";
1013 case NVPTXISD::Suld1DV4I32Clamp: return "NVPTXISD::Suld1DV4I32Clamp";
1014
1015 case NVPTXISD::Suld1DArrayI8Clamp: return "NVPTXISD::Suld1DArrayI8Clamp";
1016 case NVPTXISD::Suld1DArrayI16Clamp: return "NVPTXISD::Suld1DArrayI16Clamp";
1017 case NVPTXISD::Suld1DArrayI32Clamp: return "NVPTXISD::Suld1DArrayI32Clamp";
1018 case NVPTXISD::Suld1DArrayI64Clamp: return "NVPTXISD::Suld1DArrayI64Clamp";
1019 case NVPTXISD::Suld1DArrayV2I8Clamp: return "NVPTXISD::Suld1DArrayV2I8Clamp";
1020 case NVPTXISD::Suld1DArrayV2I16Clamp:return "NVPTXISD::Suld1DArrayV2I16Clamp";
1021 case NVPTXISD::Suld1DArrayV2I32Clamp:return "NVPTXISD::Suld1DArrayV2I32Clamp";
1022 case NVPTXISD::Suld1DArrayV2I64Clamp:return "NVPTXISD::Suld1DArrayV2I64Clamp";
1023 case NVPTXISD::Suld1DArrayV4I8Clamp: return "NVPTXISD::Suld1DArrayV4I8Clamp";
1024 case NVPTXISD::Suld1DArrayV4I16Clamp:return "NVPTXISD::Suld1DArrayV4I16Clamp";
1025 case NVPTXISD::Suld1DArrayV4I32Clamp:return "NVPTXISD::Suld1DArrayV4I32Clamp";
1026
1027 case NVPTXISD::Suld2DI8Clamp: return "NVPTXISD::Suld2DI8Clamp";
1028 case NVPTXISD::Suld2DI16Clamp: return "NVPTXISD::Suld2DI16Clamp";
1029 case NVPTXISD::Suld2DI32Clamp: return "NVPTXISD::Suld2DI32Clamp";
1030 case NVPTXISD::Suld2DI64Clamp: return "NVPTXISD::Suld2DI64Clamp";
1031 case NVPTXISD::Suld2DV2I8Clamp: return "NVPTXISD::Suld2DV2I8Clamp";
1032 case NVPTXISD::Suld2DV2I16Clamp: return "NVPTXISD::Suld2DV2I16Clamp";
1033 case NVPTXISD::Suld2DV2I32Clamp: return "NVPTXISD::Suld2DV2I32Clamp";
1034 case NVPTXISD::Suld2DV2I64Clamp: return "NVPTXISD::Suld2DV2I64Clamp";
1035 case NVPTXISD::Suld2DV4I8Clamp: return "NVPTXISD::Suld2DV4I8Clamp";
1036 case NVPTXISD::Suld2DV4I16Clamp: return "NVPTXISD::Suld2DV4I16Clamp";
1037 case NVPTXISD::Suld2DV4I32Clamp: return "NVPTXISD::Suld2DV4I32Clamp";
1038
1039 case NVPTXISD::Suld2DArrayI8Clamp: return "NVPTXISD::Suld2DArrayI8Clamp";
1040 case NVPTXISD::Suld2DArrayI16Clamp: return "NVPTXISD::Suld2DArrayI16Clamp";
1041 case NVPTXISD::Suld2DArrayI32Clamp: return "NVPTXISD::Suld2DArrayI32Clamp";
1042 case NVPTXISD::Suld2DArrayI64Clamp: return "NVPTXISD::Suld2DArrayI64Clamp";
1043 case NVPTXISD::Suld2DArrayV2I8Clamp: return "NVPTXISD::Suld2DArrayV2I8Clamp";
1044 case NVPTXISD::Suld2DArrayV2I16Clamp:return "NVPTXISD::Suld2DArrayV2I16Clamp";
1045 case NVPTXISD::Suld2DArrayV2I32Clamp:return "NVPTXISD::Suld2DArrayV2I32Clamp";
1046 case NVPTXISD::Suld2DArrayV2I64Clamp:return "NVPTXISD::Suld2DArrayV2I64Clamp";
1047 case NVPTXISD::Suld2DArrayV4I8Clamp: return "NVPTXISD::Suld2DArrayV4I8Clamp";
1048 case NVPTXISD::Suld2DArrayV4I16Clamp:return "NVPTXISD::Suld2DArrayV4I16Clamp";
1049 case NVPTXISD::Suld2DArrayV4I32Clamp:return "NVPTXISD::Suld2DArrayV4I32Clamp";
1050
1051 case NVPTXISD::Suld3DI8Clamp: return "NVPTXISD::Suld3DI8Clamp";
1052 case NVPTXISD::Suld3DI16Clamp: return "NVPTXISD::Suld3DI16Clamp";
1053 case NVPTXISD::Suld3DI32Clamp: return "NVPTXISD::Suld3DI32Clamp";
1054 case NVPTXISD::Suld3DI64Clamp: return "NVPTXISD::Suld3DI64Clamp";
1055 case NVPTXISD::Suld3DV2I8Clamp: return "NVPTXISD::Suld3DV2I8Clamp";
1056 case NVPTXISD::Suld3DV2I16Clamp: return "NVPTXISD::Suld3DV2I16Clamp";
1057 case NVPTXISD::Suld3DV2I32Clamp: return "NVPTXISD::Suld3DV2I32Clamp";
1058 case NVPTXISD::Suld3DV2I64Clamp: return "NVPTXISD::Suld3DV2I64Clamp";
1059 case NVPTXISD::Suld3DV4I8Clamp: return "NVPTXISD::Suld3DV4I8Clamp";
1060 case NVPTXISD::Suld3DV4I16Clamp: return "NVPTXISD::Suld3DV4I16Clamp";
1061 case NVPTXISD::Suld3DV4I32Clamp: return "NVPTXISD::Suld3DV4I32Clamp";
1062
1063 case NVPTXISD::Suld1DI8Trap: return "NVPTXISD::Suld1DI8Trap";
1064 case NVPTXISD::Suld1DI16Trap: return "NVPTXISD::Suld1DI16Trap";
1065 case NVPTXISD::Suld1DI32Trap: return "NVPTXISD::Suld1DI32Trap";
1066 case NVPTXISD::Suld1DI64Trap: return "NVPTXISD::Suld1DI64Trap";
1067 case NVPTXISD::Suld1DV2I8Trap: return "NVPTXISD::Suld1DV2I8Trap";
1068 case NVPTXISD::Suld1DV2I16Trap: return "NVPTXISD::Suld1DV2I16Trap";
1069 case NVPTXISD::Suld1DV2I32Trap: return "NVPTXISD::Suld1DV2I32Trap";
1070 case NVPTXISD::Suld1DV2I64Trap: return "NVPTXISD::Suld1DV2I64Trap";
1071 case NVPTXISD::Suld1DV4I8Trap: return "NVPTXISD::Suld1DV4I8Trap";
1072 case NVPTXISD::Suld1DV4I16Trap: return "NVPTXISD::Suld1DV4I16Trap";
1073 case NVPTXISD::Suld1DV4I32Trap: return "NVPTXISD::Suld1DV4I32Trap";
1074
1075 case NVPTXISD::Suld1DArrayI8Trap: return "NVPTXISD::Suld1DArrayI8Trap";
1076 case NVPTXISD::Suld1DArrayI16Trap: return "NVPTXISD::Suld1DArrayI16Trap";
1077 case NVPTXISD::Suld1DArrayI32Trap: return "NVPTXISD::Suld1DArrayI32Trap";
1078 case NVPTXISD::Suld1DArrayI64Trap: return "NVPTXISD::Suld1DArrayI64Trap";
1079 case NVPTXISD::Suld1DArrayV2I8Trap: return "NVPTXISD::Suld1DArrayV2I8Trap";
1080 case NVPTXISD::Suld1DArrayV2I16Trap: return "NVPTXISD::Suld1DArrayV2I16Trap";
1081 case NVPTXISD::Suld1DArrayV2I32Trap: return "NVPTXISD::Suld1DArrayV2I32Trap";
1082 case NVPTXISD::Suld1DArrayV2I64Trap: return "NVPTXISD::Suld1DArrayV2I64Trap";
1083 case NVPTXISD::Suld1DArrayV4I8Trap: return "NVPTXISD::Suld1DArrayV4I8Trap";
1084 case NVPTXISD::Suld1DArrayV4I16Trap: return "NVPTXISD::Suld1DArrayV4I16Trap";
1085 case NVPTXISD::Suld1DArrayV4I32Trap: return "NVPTXISD::Suld1DArrayV4I32Trap";
1086
1087 case NVPTXISD::Suld2DI8Trap: return "NVPTXISD::Suld2DI8Trap";
1088 case NVPTXISD::Suld2DI16Trap: return "NVPTXISD::Suld2DI16Trap";
1089 case NVPTXISD::Suld2DI32Trap: return "NVPTXISD::Suld2DI32Trap";
1090 case NVPTXISD::Suld2DI64Trap: return "NVPTXISD::Suld2DI64Trap";
1091 case NVPTXISD::Suld2DV2I8Trap: return "NVPTXISD::Suld2DV2I8Trap";
1092 case NVPTXISD::Suld2DV2I16Trap: return "NVPTXISD::Suld2DV2I16Trap";
1093 case NVPTXISD::Suld2DV2I32Trap: return "NVPTXISD::Suld2DV2I32Trap";
1094 case NVPTXISD::Suld2DV2I64Trap: return "NVPTXISD::Suld2DV2I64Trap";
1095 case NVPTXISD::Suld2DV4I8Trap: return "NVPTXISD::Suld2DV4I8Trap";
1096 case NVPTXISD::Suld2DV4I16Trap: return "NVPTXISD::Suld2DV4I16Trap";
1097 case NVPTXISD::Suld2DV4I32Trap: return "NVPTXISD::Suld2DV4I32Trap";
1098
1099 case NVPTXISD::Suld2DArrayI8Trap: return "NVPTXISD::Suld2DArrayI8Trap";
1100 case NVPTXISD::Suld2DArrayI16Trap: return "NVPTXISD::Suld2DArrayI16Trap";
1101 case NVPTXISD::Suld2DArrayI32Trap: return "NVPTXISD::Suld2DArrayI32Trap";
1102 case NVPTXISD::Suld2DArrayI64Trap: return "NVPTXISD::Suld2DArrayI64Trap";
1103 case NVPTXISD::Suld2DArrayV2I8Trap: return "NVPTXISD::Suld2DArrayV2I8Trap";
1104 case NVPTXISD::Suld2DArrayV2I16Trap: return "NVPTXISD::Suld2DArrayV2I16Trap";
1105 case NVPTXISD::Suld2DArrayV2I32Trap: return "NVPTXISD::Suld2DArrayV2I32Trap";
1106 case NVPTXISD::Suld2DArrayV2I64Trap: return "NVPTXISD::Suld2DArrayV2I64Trap";
1107 case NVPTXISD::Suld2DArrayV4I8Trap: return "NVPTXISD::Suld2DArrayV4I8Trap";
1108 case NVPTXISD::Suld2DArrayV4I16Trap: return "NVPTXISD::Suld2DArrayV4I16Trap";
1109 case NVPTXISD::Suld2DArrayV4I32Trap: return "NVPTXISD::Suld2DArrayV4I32Trap";
1110
1111 case NVPTXISD::Suld3DI8Trap: return "NVPTXISD::Suld3DI8Trap";
1112 case NVPTXISD::Suld3DI16Trap: return "NVPTXISD::Suld3DI16Trap";
1113 case NVPTXISD::Suld3DI32Trap: return "NVPTXISD::Suld3DI32Trap";
1114 case NVPTXISD::Suld3DI64Trap: return "NVPTXISD::Suld3DI64Trap";
1115 case NVPTXISD::Suld3DV2I8Trap: return "NVPTXISD::Suld3DV2I8Trap";
1116 case NVPTXISD::Suld3DV2I16Trap: return "NVPTXISD::Suld3DV2I16Trap";
1117 case NVPTXISD::Suld3DV2I32Trap: return "NVPTXISD::Suld3DV2I32Trap";
1118 case NVPTXISD::Suld3DV2I64Trap: return "NVPTXISD::Suld3DV2I64Trap";
1119 case NVPTXISD::Suld3DV4I8Trap: return "NVPTXISD::Suld3DV4I8Trap";
1120 case NVPTXISD::Suld3DV4I16Trap: return "NVPTXISD::Suld3DV4I16Trap";
1121 case NVPTXISD::Suld3DV4I32Trap: return "NVPTXISD::Suld3DV4I32Trap";
1122
1123 case NVPTXISD::Suld1DI8Zero: return "NVPTXISD::Suld1DI8Zero";
1124 case NVPTXISD::Suld1DI16Zero: return "NVPTXISD::Suld1DI16Zero";
1125 case NVPTXISD::Suld1DI32Zero: return "NVPTXISD::Suld1DI32Zero";
1126 case NVPTXISD::Suld1DI64Zero: return "NVPTXISD::Suld1DI64Zero";
1127 case NVPTXISD::Suld1DV2I8Zero: return "NVPTXISD::Suld1DV2I8Zero";
1128 case NVPTXISD::Suld1DV2I16Zero: return "NVPTXISD::Suld1DV2I16Zero";
1129 case NVPTXISD::Suld1DV2I32Zero: return "NVPTXISD::Suld1DV2I32Zero";
1130 case NVPTXISD::Suld1DV2I64Zero: return "NVPTXISD::Suld1DV2I64Zero";
1131 case NVPTXISD::Suld1DV4I8Zero: return "NVPTXISD::Suld1DV4I8Zero";
1132 case NVPTXISD::Suld1DV4I16Zero: return "NVPTXISD::Suld1DV4I16Zero";
1133 case NVPTXISD::Suld1DV4I32Zero: return "NVPTXISD::Suld1DV4I32Zero";
1134
1135 case NVPTXISD::Suld1DArrayI8Zero: return "NVPTXISD::Suld1DArrayI8Zero";
1136 case NVPTXISD::Suld1DArrayI16Zero: return "NVPTXISD::Suld1DArrayI16Zero";
1137 case NVPTXISD::Suld1DArrayI32Zero: return "NVPTXISD::Suld1DArrayI32Zero";
1138 case NVPTXISD::Suld1DArrayI64Zero: return "NVPTXISD::Suld1DArrayI64Zero";
1139 case NVPTXISD::Suld1DArrayV2I8Zero: return "NVPTXISD::Suld1DArrayV2I8Zero";
1140 case NVPTXISD::Suld1DArrayV2I16Zero: return "NVPTXISD::Suld1DArrayV2I16Zero";
1141 case NVPTXISD::Suld1DArrayV2I32Zero: return "NVPTXISD::Suld1DArrayV2I32Zero";
1142 case NVPTXISD::Suld1DArrayV2I64Zero: return "NVPTXISD::Suld1DArrayV2I64Zero";
1143 case NVPTXISD::Suld1DArrayV4I8Zero: return "NVPTXISD::Suld1DArrayV4I8Zero";
1144 case NVPTXISD::Suld1DArrayV4I16Zero: return "NVPTXISD::Suld1DArrayV4I16Zero";
1145 case NVPTXISD::Suld1DArrayV4I32Zero: return "NVPTXISD::Suld1DArrayV4I32Zero";
1146
1147 case NVPTXISD::Suld2DI8Zero: return "NVPTXISD::Suld2DI8Zero";
1148 case NVPTXISD::Suld2DI16Zero: return "NVPTXISD::Suld2DI16Zero";
1149 case NVPTXISD::Suld2DI32Zero: return "NVPTXISD::Suld2DI32Zero";
1150 case NVPTXISD::Suld2DI64Zero: return "NVPTXISD::Suld2DI64Zero";
1151 case NVPTXISD::Suld2DV2I8Zero: return "NVPTXISD::Suld2DV2I8Zero";
1152 case NVPTXISD::Suld2DV2I16Zero: return "NVPTXISD::Suld2DV2I16Zero";
1153 case NVPTXISD::Suld2DV2I32Zero: return "NVPTXISD::Suld2DV2I32Zero";
1154 case NVPTXISD::Suld2DV2I64Zero: return "NVPTXISD::Suld2DV2I64Zero";
1155 case NVPTXISD::Suld2DV4I8Zero: return "NVPTXISD::Suld2DV4I8Zero";
1156 case NVPTXISD::Suld2DV4I16Zero: return "NVPTXISD::Suld2DV4I16Zero";
1157 case NVPTXISD::Suld2DV4I32Zero: return "NVPTXISD::Suld2DV4I32Zero";
1158
1159 case NVPTXISD::Suld2DArrayI8Zero: return "NVPTXISD::Suld2DArrayI8Zero";
1160 case NVPTXISD::Suld2DArrayI16Zero: return "NVPTXISD::Suld2DArrayI16Zero";
1161 case NVPTXISD::Suld2DArrayI32Zero: return "NVPTXISD::Suld2DArrayI32Zero";
1162 case NVPTXISD::Suld2DArrayI64Zero: return "NVPTXISD::Suld2DArrayI64Zero";
1163 case NVPTXISD::Suld2DArrayV2I8Zero: return "NVPTXISD::Suld2DArrayV2I8Zero";
1164 case NVPTXISD::Suld2DArrayV2I16Zero: return "NVPTXISD::Suld2DArrayV2I16Zero";
1165 case NVPTXISD::Suld2DArrayV2I32Zero: return "NVPTXISD::Suld2DArrayV2I32Zero";
1166 case NVPTXISD::Suld2DArrayV2I64Zero: return "NVPTXISD::Suld2DArrayV2I64Zero";
1167 case NVPTXISD::Suld2DArrayV4I8Zero: return "NVPTXISD::Suld2DArrayV4I8Zero";
1168 case NVPTXISD::Suld2DArrayV4I16Zero: return "NVPTXISD::Suld2DArrayV4I16Zero";
1169 case NVPTXISD::Suld2DArrayV4I32Zero: return "NVPTXISD::Suld2DArrayV4I32Zero";
1170
1171 case NVPTXISD::Suld3DI8Zero: return "NVPTXISD::Suld3DI8Zero";
1172 case NVPTXISD::Suld3DI16Zero: return "NVPTXISD::Suld3DI16Zero";
1173 case NVPTXISD::Suld3DI32Zero: return "NVPTXISD::Suld3DI32Zero";
1174 case NVPTXISD::Suld3DI64Zero: return "NVPTXISD::Suld3DI64Zero";
1175 case NVPTXISD::Suld3DV2I8Zero: return "NVPTXISD::Suld3DV2I8Zero";
1176 case NVPTXISD::Suld3DV2I16Zero: return "NVPTXISD::Suld3DV2I16Zero";
1177 case NVPTXISD::Suld3DV2I32Zero: return "NVPTXISD::Suld3DV2I32Zero";
1178 case NVPTXISD::Suld3DV2I64Zero: return "NVPTXISD::Suld3DV2I64Zero";
1179 case NVPTXISD::Suld3DV4I8Zero: return "NVPTXISD::Suld3DV4I8Zero";
1180 case NVPTXISD::Suld3DV4I16Zero: return "NVPTXISD::Suld3DV4I16Zero";
1181 case NVPTXISD::Suld3DV4I32Zero: return "NVPTXISD::Suld3DV4I32Zero";
1182 }
1183 return nullptr;
1184}
1185
1186TargetLoweringBase::LegalizeTypeAction
1187NVPTXTargetLowering::getPreferredVectorAction(EVT VT) const {
1188 if (VT.getVectorNumElements() != 1 && VT.getScalarType() == MVT::i1)
1189 return TypeSplitVector;
1190 if (VT == MVT::v2f16)
1191 return TypeLegal;
1192 return TargetLoweringBase::getPreferredVectorAction(VT);
1193}
1194
1195SDValue NVPTXTargetLowering::getSqrtEstimate(SDValue Operand, SelectionDAG &DAG,
1196 int Enabled, int &ExtraSteps,
1197 bool &UseOneConst,
1198 bool Reciprocal) const {
1199 if (!(Enabled == ReciprocalEstimate::Enabled ||
1200 (Enabled == ReciprocalEstimate::Unspecified && !usePrecSqrtF32())))
1201 return SDValue();
1202
1203 if (ExtraSteps == ReciprocalEstimate::Unspecified)
1204 ExtraSteps = 0;
1205
1206 SDLoc DL(Operand);
1207 EVT VT = Operand.getValueType();
1208 bool Ftz = useF32FTZ(DAG.getMachineFunction());
1209
1210 auto MakeIntrinsicCall = [&](Intrinsic::ID IID) {
1211 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
1212 DAG.getConstant(IID, DL, MVT::i32), Operand);
1213 };
1214
1215 // The sqrt and rsqrt refinement processes assume we always start out with an
1216 // approximation of the rsqrt. Therefore, if we're going to do any refinement
1217 // (i.e. ExtraSteps > 0), we must return an rsqrt. But if we're *not* doing
1218 // any refinement, we must return a regular sqrt.
1219 if (Reciprocal || ExtraSteps > 0) {
1220 if (VT == MVT::f32)
1221 return MakeIntrinsicCall(Ftz ? Intrinsic::nvvm_rsqrt_approx_ftz_f
1222 : Intrinsic::nvvm_rsqrt_approx_f);
1223 else if (VT == MVT::f64)
1224 return MakeIntrinsicCall(Intrinsic::nvvm_rsqrt_approx_d);
1225 else
1226 return SDValue();
1227 } else {
1228 if (VT == MVT::f32)
1229 return MakeIntrinsicCall(Ftz ? Intrinsic::nvvm_sqrt_approx_ftz_f
1230 : Intrinsic::nvvm_sqrt_approx_f);
1231 else {
1232 // There's no sqrt.approx.f64 instruction, so we emit
1233 // reciprocal(rsqrt(x)). This is faster than
1234 // select(x == 0, 0, x * rsqrt(x)). (In fact, it's faster than plain
1235 // x * rsqrt(x).)
1236 return DAG.getNode(
1237 ISD::INTRINSIC_WO_CHAIN, DL, VT,
1238 DAG.getConstant(Intrinsic::nvvm_rcp_approx_ftz_d, DL, MVT::i32),
1239 MakeIntrinsicCall(Intrinsic::nvvm_rsqrt_approx_d));
1240 }
1241 }
1242}
1243
1244SDValue
1245NVPTXTargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
1246 SDLoc dl(Op);
1247 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1248 auto PtrVT = getPointerTy(DAG.getDataLayout());
1249 Op = DAG.getTargetGlobalAddress(GV, dl, PtrVT);
1250 return DAG.getNode(NVPTXISD::Wrapper, dl, PtrVT, Op);
1251}
1252
1253std::string NVPTXTargetLowering::getPrototype(
1254 const DataLayout &DL, Type *retTy, const ArgListTy &Args,
1255 const SmallVectorImpl<ISD::OutputArg> &Outs, unsigned retAlignment,
1256 ImmutableCallSite CS) const {
1257 auto PtrVT = getPointerTy(DL);
1258
1259 bool isABI = (STI.getSmVersion() >= 20);
1260 assert(isABI && "Non-ABI compilation is not supported")(static_cast <bool> (isABI && "Non-ABI compilation is not supported"
) ? void (0) : __assert_fail ("isABI && \"Non-ABI compilation is not supported\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/NVPTX/NVPTXISelLowering.cpp"
, 1260, __extension__ __PRETTY_FUNCTION__))
;
1261 if (!isABI)
1262 return "";
1263
1264 std::stringstream O;
1265 O << "prototype_" << uniqueCallSite << " : .callprototype ";
1266
1267 if (retTy->getTypeID() == Type::VoidTyID) {
1268 O << "()";
1269 } else {
1270 O << "(";
1271 if (retTy->isFloatingPointTy() || (retTy->isIntegerTy() && !retTy->isIntegerTy(128))) {
1272 unsigned size = 0;
1273 if (auto *ITy = dyn_cast<IntegerType>(retTy)) {
1274 size = ITy->getBitWidth();
1275 } else {
1276 assert(retTy->isFloatingPointTy() &&(static_cast <bool> (retTy->isFloatingPointTy() &&
"Floating point type expected here") ? void (0) : __assert_fail
("retTy->isFloatingPointTy() && \"Floating point type expected here\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/NVPTX/NVPTXISelLowering.cpp"
, 1277, __extension__ __PRETTY_FUNCTION__))
1277 "Floating point type expected here")(static_cast <bool> (retTy->isFloatingPointTy() &&
"Floating point type expected here") ? void (0) : __assert_fail
("retTy->isFloatingPointTy() && \"Floating point type expected here\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/NVPTX/NVPTXISelLowering.cpp"
, 1277, __extension__ __PRETTY_FUNCTION__))
;
1278 size = retTy->getPrimitiveSizeInBits();
1279 }
1280 // PTX ABI requires all scalar return values to be at least 32
1281 // bits in size. fp16 normally uses .b16 as its storage type in
1282 // PTX, so its size must be adjusted here, too.
1283 if (size < 32)
1284 size = 32;
1285
1286 O << ".param .b" << size << " _";
1287 } else if (isa<PointerType>(retTy)) {
1288 O << ".param .b" << PtrVT.getSizeInBits() << " _";
1289 } else if (retTy->isAggregateType() || retTy->isVectorTy() || retTy->isIntegerTy(128)) {
1290 auto &DL = CS.getCalledFunction()->getParent()->getDataLayout();
1291 O << ".param .align " << retAlignment << " .b8 _["
1292 << DL.getTypeAllocSize(retTy) << "]";
1293 } else {
1294 llvm_unreachable("Unknown return type")::llvm::llvm_unreachable_internal("Unknown return type", "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/NVPTX/NVPTXISelLowering.cpp"
, 1294)
;
1295 }
1296 O << ") ";
1297 }
1298 O << "_ (";
1299
1300 bool first = true;
1301
1302 unsigned OIdx = 0;
1303 for (unsigned i = 0, e = Args.size(); i != e; ++i, ++OIdx) {
1304 Type *Ty = Args[i].Ty;
1305 if (!first) {
1306 O << ", ";
1307 }
1308 first = false;
1309
1310 if (!Outs[OIdx].Flags.isByVal()) {
1311 if (Ty->isAggregateType() || Ty->isVectorTy() || Ty->isIntegerTy(128)) {
1312 unsigned align = 0;
1313 const CallInst *CallI = cast<CallInst>(CS.getInstruction());
1314 // +1 because index 0 is reserved for return type alignment
1315 if (!getAlign(*CallI, i + 1, align))
1316 align = DL.getABITypeAlignment(Ty);
1317 unsigned sz = DL.getTypeAllocSize(Ty);
1318 O << ".param .align " << align << " .b8 ";
1319 O << "_";
1320 O << "[" << sz << "]";
1321 // update the index for Outs
1322 SmallVector<EVT, 16> vtparts;
1323 ComputeValueVTs(*this, DL, Ty, vtparts);
1324 if (unsigned len = vtparts.size())
1325 OIdx += len - 1;
1326 continue;
1327 }
1328 // i8 types in IR will be i16 types in SDAG
1329 assert((getValueType(DL, Ty) == Outs[OIdx].VT ||(static_cast <bool> ((getValueType(DL, Ty) == Outs[OIdx
].VT || (getValueType(DL, Ty) == MVT::i8 && Outs[OIdx
].VT == MVT::i16)) && "type mismatch between callee prototype and arguments"
) ? void (0) : __assert_fail ("(getValueType(DL, Ty) == Outs[OIdx].VT || (getValueType(DL, Ty) == MVT::i8 && Outs[OIdx].VT == MVT::i16)) && \"type mismatch between callee prototype and arguments\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/NVPTX/NVPTXISelLowering.cpp"
, 1331, __extension__ __PRETTY_FUNCTION__))
1330 (getValueType(DL, Ty) == MVT::i8 && Outs[OIdx].VT == MVT::i16)) &&(static_cast <bool> ((getValueType(DL, Ty) == Outs[OIdx
].VT || (getValueType(DL, Ty) == MVT::i8 && Outs[OIdx
].VT == MVT::i16)) && "type mismatch between callee prototype and arguments"
) ? void (0) : __assert_fail ("(getValueType(DL, Ty) == Outs[OIdx].VT || (getValueType(DL, Ty) == MVT::i8 && Outs[OIdx].VT == MVT::i16)) && \"type mismatch between callee prototype and arguments\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/NVPTX/NVPTXISelLowering.cpp"
, 1331, __extension__ __PRETTY_FUNCTION__))
1331 "type mismatch between callee prototype and arguments")(static_cast <bool> ((getValueType(DL, Ty) == Outs[OIdx
].VT || (getValueType(DL, Ty) == MVT::i8 && Outs[OIdx
].VT == MVT::i16)) && "type mismatch between callee prototype and arguments"
) ? void (0) : __assert_fail ("(getValueType(DL, Ty) == Outs[OIdx].VT || (getValueType(DL, Ty) == MVT::i8 && Outs[OIdx].VT == MVT::i16)) && \"type mismatch between callee prototype and arguments\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/NVPTX/NVPTXISelLowering.cpp"
, 1331, __extension__ __PRETTY_FUNCTION__))
;
1332 // scalar type
1333 unsigned sz = 0;
1334 if (isa<IntegerType>(Ty)) {
1335 sz = cast<IntegerType>(Ty)->getBitWidth();
1336 if (sz < 32)
1337 sz = 32;
1338 } else if (isa<PointerType>(Ty)) {
1339 sz = PtrVT.getSizeInBits();
1340 } else if (Ty->isHalfTy())
1341 // PTX ABI requires all scalar parameters to be at least 32
1342 // bits in size. fp16 normally uses .b16 as its storage type
1343 // in PTX, so its size must be adjusted here, too.
1344 sz = 32;
1345 else
1346 sz = Ty->getPrimitiveSizeInBits();
1347 O << ".param .b" << sz << " ";
1348 O << "_";
1349 continue;
1350 }
1351 auto *PTy = dyn_cast<PointerType>(Ty);
1352 assert(PTy && "Param with byval attribute should be a pointer type")(static_cast <bool> (PTy && "Param with byval attribute should be a pointer type"
) ? void (0) : __assert_fail ("PTy && \"Param with byval attribute should be a pointer type\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/NVPTX/NVPTXISelLowering.cpp"
, 1352, __extension__ __PRETTY_FUNCTION__))
;
1353 Type *ETy = PTy->getElementType();
1354
1355 unsigned align = Outs[OIdx].Flags.getByValAlign();
1356 unsigned sz = DL.getTypeAllocSize(ETy);
1357 O << ".param .align " << align << " .b8 ";
1358 O << "_";
1359 O << "[" << sz << "]";
1360 }
1361 O << ");";
1362 return O.str();
1363}
1364
1365unsigned NVPTXTargetLowering::getArgumentAlignment(SDValue Callee,
1366 ImmutableCallSite CS,
1367 Type *Ty, unsigned Idx,
1368 const DataLayout &DL) const {
1369 if (!CS) {
1370 // CallSite is zero, fallback to ABI type alignment
1371 return DL.getABITypeAlignment(Ty);
1372 }
1373
1374 unsigned Align = 0;
1375 const Value *DirectCallee = CS.getCalledFunction();
1376
1377 if (!DirectCallee) {
1378 // We don't have a direct function symbol, but that may be because of
1379 // constant cast instructions in the call.
1380 const Instruction *CalleeI = CS.getInstruction();
1381 assert(CalleeI && "Call target is not a function or derived value?")(static_cast <bool> (CalleeI && "Call target is not a function or derived value?"
) ? void (0) : __assert_fail ("CalleeI && \"Call target is not a function or derived value?\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/NVPTX/NVPTXISelLowering.cpp"
, 1381, __extension__ __PRETTY_FUNCTION__))
;
1382
1383 // With bitcast'd call targets, the instruction will be the call
1384 if (isa<CallInst>(CalleeI)) {
1385 // Check if we have call alignment metadata
1386 if (getAlign(*cast<CallInst>(CalleeI), Idx, Align))
1387 return Align;
1388
1389 const Value *CalleeV = cast<CallInst>(CalleeI)->getCalledValue();
1390 // Ignore any bitcast instructions
1391 while (isa<ConstantExpr>(CalleeV)) {
1392 const ConstantExpr *CE = cast<ConstantExpr>(CalleeV);
1393 if (!CE->isCast())
1394 break;
1395 // Look through the bitcast
1396 CalleeV = cast<ConstantExpr>(CalleeV)->getOperand(0);
1397 }
1398
1399 // We have now looked past all of the bitcasts. Do we finally have a
1400 // Function?
1401 if (isa<Function>(CalleeV))
1402 DirectCallee = CalleeV;
1403 }
1404 }
1405
1406 // Check for function alignment information if we found that the
1407 // ultimate target is a Function
1408 if (DirectCallee)
1409 if (getAlign(*cast<Function>(DirectCallee), Idx, Align))
1410 return Align;
1411
1412 // Call is indirect or alignment information is not available, fall back to
1413 // the ABI type alignment
1414 return DL.getABITypeAlignment(Ty);
1415}
1416
1417SDValue NVPTXTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
1418 SmallVectorImpl<SDValue> &InVals) const {
1419 SelectionDAG &DAG = CLI.DAG;
1420 SDLoc dl = CLI.DL;
1421 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
1422 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
1423 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
1424 SDValue Chain = CLI.Chain;
1425 SDValue Callee = CLI.Callee;
1426 bool &isTailCall = CLI.IsTailCall;
1427 ArgListTy &Args = CLI.getArgs();
1428 Type *RetTy = CLI.RetTy;
1429 ImmutableCallSite CS = CLI.CS;
1430 const DataLayout &DL = DAG.getDataLayout();
1431
1432 bool isABI = (STI.getSmVersion() >= 20);
1433 assert(isABI && "Non-ABI compilation is not supported")(static_cast <bool> (isABI && "Non-ABI compilation is not supported"
) ? void (0) : __assert_fail ("isABI && \"Non-ABI compilation is not supported\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/NVPTX/NVPTXISelLowering.cpp"
, 1433, __extension__ __PRETTY_FUNCTION__))
;
1434 if (!isABI)
1435 return Chain;
1436
1437 SDValue tempChain = Chain;
1438 Chain = DAG.getCALLSEQ_START(Chain, uniqueCallSite, 0, dl);
1439 SDValue InFlag = Chain.getValue(1);
1440
1441 unsigned paramCount = 0;
1442 // Args.size() and Outs.size() need not match.
1443 // Outs.size() will be larger
1444 // * if there is an aggregate argument with multiple fields (each field
1445 // showing up separately in Outs)
1446 // * if there is a vector argument with more than typical vector-length
1447 // elements (generally if more than 4) where each vector element is
1448 // individually present in Outs.
1449 // So a different index should be used for indexing into Outs/OutVals.
1450 // See similar issue in LowerFormalArguments.
1451 unsigned OIdx = 0;
1452 // Declare the .params or .reg need to pass values
1453 // to the function
1454 for (unsigned i = 0, e = Args.size(); i != e; ++i, ++OIdx) {
1455 EVT VT = Outs[OIdx].VT;
1456 Type *Ty = Args[i].Ty;
1457
1458 if (!Outs[OIdx].Flags.isByVal()) {
1459 SmallVector<EVT, 16> VTs;
1460 SmallVector<uint64_t, 16> Offsets;
1461 ComputePTXValueVTs(*this, DL, Ty, VTs, &Offsets);
1462 unsigned ArgAlign =
1463 getArgumentAlignment(Callee, CS, Ty, paramCount + 1, DL);
1464 unsigned AllocSize = DL.getTypeAllocSize(Ty);
1465 SDVTList DeclareParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1466 bool NeedAlign; // Does argument declaration specify alignment?
1467 if (Ty->isAggregateType() || Ty->isVectorTy() || Ty->isIntegerTy(128)) {
1468 // declare .param .align <align> .b8 .param<n>[<size>];
1469 SDValue DeclareParamOps[] = {
1470 Chain, DAG.getConstant(ArgAlign, dl, MVT::i32),
1471 DAG.getConstant(paramCount, dl, MVT::i32),
1472 DAG.getConstant(AllocSize, dl, MVT::i32), InFlag};
1473 Chain = DAG.getNode(NVPTXISD::DeclareParam, dl, DeclareParamVTs,
1474 DeclareParamOps);
1475 NeedAlign = true;
1476 } else {
1477 // declare .param .b<size> .param<n>;
1478 if ((VT.isInteger() || VT.isFloatingPoint()) && AllocSize < 4) {
1479 // PTX ABI requires integral types to be at least 32 bits in
1480 // size. FP16 is loaded/stored using i16, so it's handled
1481 // here as well.
1482 AllocSize = 4;
1483 }
1484 SDValue DeclareScalarParamOps[] = {
1485 Chain, DAG.getConstant(paramCount, dl, MVT::i32),
1486 DAG.getConstant(AllocSize * 8, dl, MVT::i32),
1487 DAG.getConstant(0, dl, MVT::i32), InFlag};
1488 Chain = DAG.getNode(NVPTXISD::DeclareScalarParam, dl, DeclareParamVTs,
1489 DeclareScalarParamOps);
1490 NeedAlign = false;
1491 }
1492 InFlag = Chain.getValue(1);
1493
1494 // PTX Interoperability Guide 3.3(A): [Integer] Values shorter
1495 // than 32-bits are sign extended or zero extended, depending on
1496 // whether they are signed or unsigned types. This case applies
1497 // only to scalar parameters and not to aggregate values.
1498 bool ExtendIntegerParam =
1499 Ty->isIntegerTy() && DL.getTypeAllocSizeInBits(Ty) < 32;
1500
1501 auto VectorInfo = VectorizePTXValueVTs(VTs, Offsets, ArgAlign);
1502 SmallVector<SDValue, 6> StoreOperands;
1503 for (unsigned j = 0, je = VTs.size(); j != je; ++j) {
1504 // New store.
1505 if (VectorInfo[j] & PVF_FIRST) {
1506 assert(StoreOperands.empty() && "Unfinished preceeding store.")(static_cast <bool> (StoreOperands.empty() && "Unfinished preceeding store."
) ? void (0) : __assert_fail ("StoreOperands.empty() && \"Unfinished preceeding store.\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/NVPTX/NVPTXISelLowering.cpp"
, 1506, __extension__ __PRETTY_FUNCTION__))
;
1507 StoreOperands.push_back(Chain);
1508 StoreOperands.push_back(DAG.getConstant(paramCount, dl, MVT::i32));
1509 StoreOperands.push_back(DAG.getConstant(Offsets[j], dl, MVT::i32));
1510 }
1511
1512 EVT EltVT = VTs[j];
1513 SDValue StVal = OutVals[OIdx];
1514 if (ExtendIntegerParam) {
1515 assert(VTs.size() == 1 && "Scalar can't have multiple parts.")(static_cast <bool> (VTs.size() == 1 && "Scalar can't have multiple parts."
) ? void (0) : __assert_fail ("VTs.size() == 1 && \"Scalar can't have multiple parts.\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/NVPTX/NVPTXISelLowering.cpp"
, 1515, __extension__ __PRETTY_FUNCTION__))
;
1516 // zext/sext to i32
1517 StVal = DAG.getNode(Outs[OIdx].Flags.isSExt() ? ISD::SIGN_EXTEND
1518 : ISD::ZERO_EXTEND,
1519 dl, MVT::i32, StVal);
1520 } else if (EltVT.getSizeInBits() < 16) {
1521 // Use 16-bit registers for small stores as it's the
1522 // smallest general purpose register size supported by NVPTX.
1523 StVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i16, StVal);
1524 }
1525
1526 // Record the value to store.
1527 StoreOperands.push_back(StVal);
1528
1529 if (VectorInfo[j] & PVF_LAST) {
1530 unsigned NumElts = StoreOperands.size() - 3;
1531 NVPTXISD::NodeType Op;
1532 switch (NumElts) {
1533 case 1:
1534 Op = NVPTXISD::StoreParam;
1535 break;
1536 case 2:
1537 Op = NVPTXISD::StoreParamV2;
1538 break;
1539 case 4:
1540 Op = NVPTXISD::StoreParamV4;
1541 break;
1542 default:
1543 llvm_unreachable("Invalid vector info.")::llvm::llvm_unreachable_internal("Invalid vector info.", "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/NVPTX/NVPTXISelLowering.cpp"
, 1543)
;
1544 }
1545
1546 StoreOperands.push_back(InFlag);
1547
1548 // Adjust type of the store op if we've extended the scalar
1549 // return value.
1550 EVT TheStoreType = ExtendIntegerParam ? MVT::i32 : VTs[j];
1551 unsigned EltAlign =
1552 NeedAlign ? GreatestCommonDivisor64(ArgAlign, Offsets[j]) : 0;
1553
1554 Chain = DAG.getMemIntrinsicNode(
1555 Op, dl, DAG.getVTList(MVT::Other, MVT::Glue), StoreOperands,
1556 TheStoreType, MachinePointerInfo(), EltAlign,
1557 MachineMemOperand::MOStore);
1558 InFlag = Chain.getValue(1);
1559
1560 // Cleanup.
1561 StoreOperands.clear();
1562 }
1563 ++OIdx;
1564 }
1565 assert(StoreOperands.empty() && "Unfinished parameter store.")(static_cast <bool> (StoreOperands.empty() && "Unfinished parameter store."
) ? void (0) : __assert_fail ("StoreOperands.empty() && \"Unfinished parameter store.\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/NVPTX/NVPTXISelLowering.cpp"
, 1565, __extension__ __PRETTY_FUNCTION__))
;
1566 if (VTs.size() > 0)
1567 --OIdx;
1568 ++paramCount;
1569 continue;
1570 }
1571
1572 // ByVal arguments
1573 SmallVector<EVT, 16> VTs;
1574 SmallVector<uint64_t, 16> Offsets;
1575 auto *PTy = dyn_cast<PointerType>(Args[i].Ty);
1576 assert(PTy && "Type of a byval parameter should be pointer")(static_cast <bool> (PTy && "Type of a byval parameter should be pointer"
) ? void (0) : __assert_fail ("PTy && \"Type of a byval parameter should be pointer\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/NVPTX/NVPTXISelLowering.cpp"
, 1576, __extension__ __PRETTY_FUNCTION__))
;
1577 ComputePTXValueVTs(*this, DL, PTy->getElementType(), VTs, &Offsets, 0);
1578
1579 // declare .param .align <align> .b8 .param<n>[<size>];
1580 unsigned sz = Outs[OIdx].Flags.getByValSize();
1581 SDVTList DeclareParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1582 unsigned ArgAlign = Outs[OIdx].Flags.getByValAlign();
1583 // The ByValAlign in the Outs[OIdx].Flags is alway set at this point,
1584 // so we don't need to worry about natural alignment or not.
1585 // See TargetLowering::LowerCallTo().
1586
1587 // Enforce minumum alignment of 4 to work around ptxas miscompile
1588 // for sm_50+. See corresponding alignment adjustment in
1589 // emitFunctionParamList() for details.
1590 if (ArgAlign < 4)
1591 ArgAlign = 4;
1592 SDValue DeclareParamOps[] = {Chain, DAG.getConstant(ArgAlign, dl, MVT::i32),
1593 DAG.getConstant(paramCount, dl, MVT::i32),
1594 DAG.getConstant(sz, dl, MVT::i32), InFlag};
1595 Chain = DAG.getNode(NVPTXISD::DeclareParam, dl, DeclareParamVTs,
1596 DeclareParamOps);
1597 InFlag = Chain.getValue(1);
1598 for (unsigned j = 0, je = VTs.size(); j != je; ++j) {
1599 EVT elemtype = VTs[j];
1600 int curOffset = Offsets[j];
1601 unsigned PartAlign = GreatestCommonDivisor64(ArgAlign, curOffset);
1602 auto PtrVT = getPointerTy(DL);
1603 SDValue srcAddr = DAG.getNode(ISD::ADD, dl, PtrVT, OutVals[OIdx],
1604 DAG.getConstant(curOffset, dl, PtrVT));
1605 SDValue theVal = DAG.getLoad(elemtype, dl, tempChain, srcAddr,
1606 MachinePointerInfo(), PartAlign);
1607 if (elemtype.getSizeInBits() < 16) {
1608 theVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i16, theVal);
1609 }
1610 SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1611 SDValue CopyParamOps[] = { Chain,
1612 DAG.getConstant(paramCount, dl, MVT::i32),
1613 DAG.getConstant(curOffset, dl, MVT::i32),
1614 theVal, InFlag };
1615 Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreParam, dl, CopyParamVTs,
1616 CopyParamOps, elemtype,
1617 MachinePointerInfo(), /* Align */ 0,
1618 MachineMemOperand::MOStore);
1619
1620 InFlag = Chain.getValue(1);
1621 }
1622 ++paramCount;
1623 }
1624
1625 GlobalAddressSDNode *Func = dyn_cast<GlobalAddressSDNode>(Callee.getNode());
1626 unsigned retAlignment = 0;
1627
1628 // Handle Result
1629 if (Ins.size() > 0) {
1630 SmallVector<EVT, 16> resvtparts;
1631 ComputeValueVTs(*this, DL, RetTy, resvtparts);
1632
1633 // Declare
1634 // .param .align 16 .b8 retval0[<size-in-bytes>], or
1635 // .param .b<size-in-bits> retval0
1636 unsigned resultsz = DL.getTypeAllocSizeInBits(RetTy);
1637 // Emit ".param .b<size-in-bits> retval0" instead of byte arrays only for
1638 // these three types to match the logic in
1639 // NVPTXAsmPrinter::printReturnValStr and NVPTXTargetLowering::getPrototype.
1640 // Plus, this behavior is consistent with nvcc's.
1641 if (RetTy->isFloatingPointTy() || RetTy->isPointerTy() ||
1642 (RetTy->isIntegerTy() && !RetTy->isIntegerTy(128))) {
1643 // Scalar needs to be at least 32bit wide
1644 if (resultsz < 32)
1645 resultsz = 32;
1646 SDVTList DeclareRetVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1647 SDValue DeclareRetOps[] = { Chain, DAG.getConstant(1, dl, MVT::i32),
1648 DAG.getConstant(resultsz, dl, MVT::i32),
1649 DAG.getConstant(0, dl, MVT::i32), InFlag };
1650 Chain = DAG.getNode(NVPTXISD::DeclareRet, dl, DeclareRetVTs,
1651 DeclareRetOps);
1652 InFlag = Chain.getValue(1);
1653 } else {
1654 retAlignment = getArgumentAlignment(Callee, CS, RetTy, 0, DL);
1655 SDVTList DeclareRetVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1656 SDValue DeclareRetOps[] = { Chain,
1657 DAG.getConstant(retAlignment, dl, MVT::i32),
1658 DAG.getConstant(resultsz / 8, dl, MVT::i32),
1659 DAG.getConstant(0, dl, MVT::i32), InFlag };
1660 Chain = DAG.getNode(NVPTXISD::DeclareRetParam, dl, DeclareRetVTs,
1661 DeclareRetOps);
1662 InFlag = Chain.getValue(1);
1663 }
1664 }
1665
1666 if (!Func) {
1667 // This is indirect function call case : PTX requires a prototype of the
1668 // form
1669 // proto_0 : .callprototype(.param .b32 _) _ (.param .b32 _);
1670 // to be emitted, and the label has to used as the last arg of call
1671 // instruction.
1672 // The prototype is embedded in a string and put as the operand for a
1673 // CallPrototype SDNode which will print out to the value of the string.
1674 SDVTList ProtoVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1675 std::string Proto = getPrototype(DL, RetTy, Args, Outs, retAlignment, CS);
1676 const char *ProtoStr =
1677 nvTM->getManagedStrPool()->getManagedString(Proto.c_str())->c_str();
1678 SDValue ProtoOps[] = {
1679 Chain, DAG.getTargetExternalSymbol(ProtoStr, MVT::i32), InFlag,
1680 };
1681 Chain = DAG.getNode(NVPTXISD::CallPrototype, dl, ProtoVTs, ProtoOps);
1682 InFlag = Chain.getValue(1);
1683 }
1684 // Op to just print "call"
1685 SDVTList PrintCallVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1686 SDValue PrintCallOps[] = {
1687 Chain, DAG.getConstant((Ins.size() == 0) ? 0 : 1, dl, MVT::i32), InFlag
1688 };
1689 // We model convergent calls as separate opcodes.
1690 unsigned Opcode = Func ? NVPTXISD::PrintCallUni : NVPTXISD::PrintCall;
1691 if (CLI.IsConvergent)
1692 Opcode = Opcode == NVPTXISD::PrintCallUni ? NVPTXISD::PrintConvergentCallUni
1693 : NVPTXISD::PrintConvergentCall;
1694 Chain = DAG.getNode(Opcode, dl, PrintCallVTs, PrintCallOps);
1695 InFlag = Chain.getValue(1);
1696
1697 // Ops to print out the function name
1698 SDVTList CallVoidVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1699 SDValue CallVoidOps[] = { Chain, Callee, InFlag };
1700 Chain = DAG.getNode(NVPTXISD::CallVoid, dl, CallVoidVTs, CallVoidOps);
1701 InFlag = Chain.getValue(1);
1702
1703 // Ops to print out the param list
1704 SDVTList CallArgBeginVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1705 SDValue CallArgBeginOps[] = { Chain, InFlag };
1706 Chain = DAG.getNode(NVPTXISD::CallArgBegin, dl, CallArgBeginVTs,
1707 CallArgBeginOps);
1708 InFlag = Chain.getValue(1);
1709
1710 for (unsigned i = 0, e = paramCount; i != e; ++i) {
1711 unsigned opcode;
1712 if (i == (e - 1))
1713 opcode = NVPTXISD::LastCallArg;
1714 else
1715 opcode = NVPTXISD::CallArg;
1716 SDVTList CallArgVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1717 SDValue CallArgOps[] = { Chain, DAG.getConstant(1, dl, MVT::i32),
1718 DAG.getConstant(i, dl, MVT::i32), InFlag };
1719 Chain = DAG.getNode(opcode, dl, CallArgVTs, CallArgOps);
1720 InFlag = Chain.getValue(1);
1721 }
1722 SDVTList CallArgEndVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1723 SDValue CallArgEndOps[] = { Chain,
1724 DAG.getConstant(Func ? 1 : 0, dl, MVT::i32),
1725 InFlag };
1726 Chain = DAG.getNode(NVPTXISD::CallArgEnd, dl, CallArgEndVTs, CallArgEndOps);
1727 InFlag = Chain.getValue(1);
1728
1729 if (!Func) {
1730 SDVTList PrototypeVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1731 SDValue PrototypeOps[] = { Chain,
1732 DAG.getConstant(uniqueCallSite, dl, MVT::i32),
1733 InFlag };
1734 Chain = DAG.getNode(NVPTXISD::Prototype, dl, PrototypeVTs, PrototypeOps);
1735 InFlag = Chain.getValue(1);
1736 }
1737
1738 // Generate loads from param memory/moves from registers for result
1739 if (Ins.size() > 0) {
1740 SmallVector<EVT, 16> VTs;
1741 SmallVector<uint64_t, 16> Offsets;
1742 ComputePTXValueVTs(*this, DL, RetTy, VTs, &Offsets, 0);
1743 assert(VTs.size() == Ins.size() && "Bad value decomposition")(static_cast <bool> (VTs.size() == Ins.size() &&
"Bad value decomposition") ? void (0) : __assert_fail ("VTs.size() == Ins.size() && \"Bad value decomposition\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/NVPTX/NVPTXISelLowering.cpp"
, 1743, __extension__ __PRETTY_FUNCTION__))
;
1744
1745 unsigned RetAlign = getArgumentAlignment(Callee, CS, RetTy, 0, DL);
1746 auto VectorInfo = VectorizePTXValueVTs(VTs, Offsets, RetAlign);
1747
1748 SmallVector<EVT, 6> LoadVTs;
1749 int VecIdx = -1; // Index of the first element of the vector.
1750
1751 // PTX Interoperability Guide 3.3(A): [Integer] Values shorter than
1752 // 32-bits are sign extended or zero extended, depending on whether
1753 // they are signed or unsigned types.
1754 bool ExtendIntegerRetVal =
1755 RetTy->isIntegerTy() && DL.getTypeAllocSizeInBits(RetTy) < 32;
1756
1757 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
1758 bool needTruncate = false;
1759 EVT TheLoadType = VTs[i];
1760 EVT EltType = Ins[i].VT;
1761 unsigned EltAlign = GreatestCommonDivisor64(RetAlign, Offsets[i]);
1762 if (ExtendIntegerRetVal) {
1763 TheLoadType = MVT::i32;
1764 EltType = MVT::i32;
1765 needTruncate = true;
1766 } else if (TheLoadType.getSizeInBits() < 16) {
1767 if (VTs[i].isInteger())
1768 needTruncate = true;
1769 EltType = MVT::i16;
1770 }
1771
1772 // Record index of the very first element of the vector.
1773 if (VectorInfo[i] & PVF_FIRST) {
1774 assert(VecIdx == -1 && LoadVTs.empty() && "Orphaned operand list.")(static_cast <bool> (VecIdx == -1 && LoadVTs.empty
() && "Orphaned operand list.") ? void (0) : __assert_fail
("VecIdx == -1 && LoadVTs.empty() && \"Orphaned operand list.\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/NVPTX/NVPTXISelLowering.cpp"
, 1774, __extension__ __PRETTY_FUNCTION__))
;
1775 VecIdx = i;
1776 }
1777
1778 LoadVTs.push_back(EltType);
1779
1780 if (VectorInfo[i] & PVF_LAST) {
1781 unsigned NumElts = LoadVTs.size();
1782 LoadVTs.push_back(MVT::Other);
1783 LoadVTs.push_back(MVT::Glue);
1784 NVPTXISD::NodeType Op;
1785 switch (NumElts) {
1786 case 1:
1787 Op = NVPTXISD::LoadParam;
1788 break;
1789 case 2:
1790 Op = NVPTXISD::LoadParamV2;
1791 break;
1792 case 4:
1793 Op = NVPTXISD::LoadParamV4;
1794 break;
1795 default:
1796 llvm_unreachable("Invalid vector info.")::llvm::llvm_unreachable_internal("Invalid vector info.", "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/NVPTX/NVPTXISelLowering.cpp"
, 1796)
;
1797 }
1798
1799 SDValue LoadOperands[] = {
1800 Chain, DAG.getConstant(1, dl, MVT::i32),
1801 DAG.getConstant(Offsets[VecIdx], dl, MVT::i32), InFlag};
1802 SDValue RetVal = DAG.getMemIntrinsicNode(
1803 Op, dl, DAG.getVTList(LoadVTs), LoadOperands, TheLoadType,
1804 MachinePointerInfo(), EltAlign,
1805 MachineMemOperand::MOLoad);
1806
1807 for (unsigned j = 0; j < NumElts; ++j) {
1808 SDValue Ret = RetVal.getValue(j);
1809 if (needTruncate)
1810 Ret = DAG.getNode(ISD::TRUNCATE, dl, Ins[VecIdx + j].VT, Ret);
1811 InVals.push_back(Ret);
1812 }
1813 Chain = RetVal.getValue(NumElts);
1814 InFlag = RetVal.getValue(NumElts + 1);
1815
1816 // Cleanup
1817 VecIdx = -1;
1818 LoadVTs.clear();
1819 }
1820 }
1821 }
1822
1823 Chain = DAG.getCALLSEQ_END(Chain,
1824 DAG.getIntPtrConstant(uniqueCallSite, dl, true),
1825 DAG.getIntPtrConstant(uniqueCallSite + 1, dl,
1826 true),
1827 InFlag, dl);
1828 uniqueCallSite++;
1829
1830 // set isTailCall to false for now, until we figure out how to express
1831 // tail call optimization in PTX
1832 isTailCall = false;
1833 return Chain;
1834}
1835
1836// By default CONCAT_VECTORS is lowered by ExpandVectorBuildThroughStack()
1837// (see LegalizeDAG.cpp). This is slow and uses local memory.
1838// We use extract/insert/build vector just as what LegalizeOp() does in llvm 2.5
1839SDValue
1840NVPTXTargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const {
1841 SDNode *Node = Op.getNode();
1842 SDLoc dl(Node);
1843 SmallVector<SDValue, 8> Ops;
1844 unsigned NumOperands = Node->getNumOperands();
1845 for (unsigned i = 0; i < NumOperands; ++i) {
1846 SDValue SubOp = Node->getOperand(i);
1847 EVT VVT = SubOp.getNode()->getValueType(0);
1848 EVT EltVT = VVT.getVectorElementType();
1849 unsigned NumSubElem = VVT.getVectorNumElements();
1850 for (unsigned j = 0; j < NumSubElem; ++j) {
1851 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, SubOp,
1852 DAG.getIntPtrConstant(j, dl)));
1853 }
1854 }
1855 return DAG.getBuildVector(Node->getValueType(0), dl, Ops);
1856}
1857
1858// We can init constant f16x2 with a single .b32 move. Normally it
1859// would get lowered as two constant loads and vector-packing move.
1860// mov.b16 %h1, 0x4000;
1861// mov.b16 %h2, 0x3C00;
1862// mov.b32 %hh2, {%h2, %h1};
1863// Instead we want just a constant move:
1864// mov.b32 %hh2, 0x40003C00
1865//
1866// This results in better SASS code with CUDA 7.x. Ptxas in CUDA 8.0
1867// generates good SASS in both cases.
1868SDValue NVPTXTargetLowering::LowerBUILD_VECTOR(SDValue Op,
1869 SelectionDAG &DAG) const {
1870 //return Op;
1871 if (!(Op->getValueType(0) == MVT::v2f16 &&
1872 isa<ConstantFPSDNode>(Op->getOperand(0)) &&
1873 isa<ConstantFPSDNode>(Op->getOperand(1))))
1874 return Op;
1875
1876 APInt E0 =
1877 cast<ConstantFPSDNode>(Op->getOperand(0))->getValueAPF().bitcastToAPInt();
1878 APInt E1 =
1879 cast<ConstantFPSDNode>(Op->getOperand(1))->getValueAPF().bitcastToAPInt();
1880 SDValue Const =
1881 DAG.getConstant(E1.zext(32).shl(16) | E0.zext(32), SDLoc(Op), MVT::i32);
1882 return DAG.getNode(ISD::BITCAST, SDLoc(Op), MVT::v2f16, Const);
1883}
1884
1885SDValue NVPTXTargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
1886 SelectionDAG &DAG) const {
1887 SDValue Index = Op->getOperand(1);
1888 // Constant index will be matched by tablegen.
1889 if (isa<ConstantSDNode>(Index.getNode()))
1890 return Op;
1891
1892 // Extract individual elements and select one of them.
1893 SDValue Vector = Op->getOperand(0);
1894 EVT VectorVT = Vector.getValueType();
1895 assert(VectorVT == MVT::v2f16 && "Unexpected vector type.")(static_cast <bool> (VectorVT == MVT::v2f16 && "Unexpected vector type."
) ? void (0) : __assert_fail ("VectorVT == MVT::v2f16 && \"Unexpected vector type.\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/NVPTX/NVPTXISelLowering.cpp"
, 1895, __extension__ __PRETTY_FUNCTION__))
;
1896 EVT EltVT = VectorVT.getVectorElementType();
1897
1898 SDLoc dl(Op.getNode());
1899 SDValue E0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Vector,
1900 DAG.getIntPtrConstant(0, dl));
1901 SDValue E1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Vector,
1902 DAG.getIntPtrConstant(1, dl));
1903 return DAG.getSelectCC(dl, Index, DAG.getIntPtrConstant(0, dl), E0, E1,
1904 ISD::CondCode::SETEQ);
1905}
1906
1907/// LowerShiftRightParts - Lower SRL_PARTS, SRA_PARTS, which
1908/// 1) returns two i32 values and take a 2 x i32 value to shift plus a shift
1909/// amount, or
1910/// 2) returns two i64 values and take a 2 x i64 value to shift plus a shift
1911/// amount.
1912SDValue NVPTXTargetLowering::LowerShiftRightParts(SDValue Op,
1913 SelectionDAG &DAG) const {
1914 assert(Op.getNumOperands() == 3 && "Not a double-shift!")(static_cast <bool> (Op.getNumOperands() == 3 &&
"Not a double-shift!") ? void (0) : __assert_fail ("Op.getNumOperands() == 3 && \"Not a double-shift!\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/NVPTX/NVPTXISelLowering.cpp"
, 1914, __extension__ __PRETTY_FUNCTION__))
;
1915 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS)(static_cast <bool> (Op.getOpcode() == ISD::SRA_PARTS ||
Op.getOpcode() == ISD::SRL_PARTS) ? void (0) : __assert_fail
("Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS"
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/NVPTX/NVPTXISelLowering.cpp"
, 1915, __extension__ __PRETTY_FUNCTION__))
;
1916
1917 EVT VT = Op.getValueType();
1918 unsigned VTBits = VT.getSizeInBits();
1919 SDLoc dl(Op);
1920 SDValue ShOpLo = Op.getOperand(0);
1921 SDValue ShOpHi = Op.getOperand(1);
1922 SDValue ShAmt = Op.getOperand(2);
1923 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
1924
1925 if (VTBits == 32 && STI.getSmVersion() >= 35) {
1926 // For 32bit and sm35, we can use the funnel shift 'shf' instruction.
1927 // {dHi, dLo} = {aHi, aLo} >> Amt
1928 // dHi = aHi >> Amt
1929 // dLo = shf.r.clamp aLo, aHi, Amt
1930
1931 SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
1932 SDValue Lo = DAG.getNode(NVPTXISD::FUN_SHFR_CLAMP, dl, VT, ShOpLo, ShOpHi,
1933 ShAmt);
1934
1935 SDValue Ops[2] = { Lo, Hi };
1936 return DAG.getMergeValues(Ops, dl);
1937 }
1938 else {
1939 // {dHi, dLo} = {aHi, aLo} >> Amt
1940 // - if (Amt>=size) then
1941 // dLo = aHi >> (Amt-size)
1942 // dHi = aHi >> Amt (this is either all 0 or all 1)
1943 // else
1944 // dLo = (aLo >>logic Amt) | (aHi << (size-Amt))
1945 // dHi = aHi >> Amt
1946
1947 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
1948 DAG.getConstant(VTBits, dl, MVT::i32),
1949 ShAmt);
1950 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
1951 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
1952 DAG.getConstant(VTBits, dl, MVT::i32));
1953 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
1954 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
1955 SDValue TrueVal = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
1956
1957 SDValue Cmp = DAG.getSetCC(dl, MVT::i1, ShAmt,
1958 DAG.getConstant(VTBits, dl, MVT::i32),
1959 ISD::SETGE);
1960 SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
1961 SDValue Lo = DAG.getNode(ISD::SELECT, dl, VT, Cmp, TrueVal, FalseVal);
1962
1963 SDValue Ops[2] = { Lo, Hi };
1964 return DAG.getMergeValues(Ops, dl);
1965 }
1966}
1967
1968/// LowerShiftLeftParts - Lower SHL_PARTS, which
1969/// 1) returns two i32 values and take a 2 x i32 value to shift plus a shift
1970/// amount, or
1971/// 2) returns two i64 values and take a 2 x i64 value to shift plus a shift
1972/// amount.
1973SDValue NVPTXTargetLowering::LowerShiftLeftParts(SDValue Op,
1974 SelectionDAG &DAG) const {
1975 assert(Op.getNumOperands() == 3 && "Not a double-shift!")(static_cast <bool> (Op.getNumOperands() == 3 &&
"Not a double-shift!") ? void (0) : __assert_fail ("Op.getNumOperands() == 3 && \"Not a double-shift!\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/NVPTX/NVPTXISelLowering.cpp"
, 1975, __extension__ __PRETTY_FUNCTION__))
;
1976 assert(Op.getOpcode() == ISD::SHL_PARTS)(static_cast <bool> (Op.getOpcode() == ISD::SHL_PARTS) ?
void (0) : __assert_fail ("Op.getOpcode() == ISD::SHL_PARTS"
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/NVPTX/NVPTXISelLowering.cpp"
, 1976, __extension__ __PRETTY_FUNCTION__))
;
1977
1978 EVT VT = Op.getValueType();
1979 unsigned VTBits = VT.getSizeInBits();
1980 SDLoc dl(Op);
1981 SDValue ShOpLo = Op.getOperand(0);
1982 SDValue ShOpHi = Op.getOperand(1);
1983 SDValue ShAmt = Op.getOperand(2);
1984
1985 if (VTBits == 32 && STI.getSmVersion() >= 35) {
1986 // For 32bit and sm35, we can use the funnel shift 'shf' instruction.
1987 // {dHi, dLo} = {aHi, aLo} << Amt
1988 // dHi = shf.l.clamp aLo, aHi, Amt
1989 // dLo = aLo << Amt
1990
1991 SDValue Hi = DAG.getNode(NVPTXISD::FUN_SHFL_CLAMP, dl, VT, ShOpLo, ShOpHi,
1992 ShAmt);
1993 SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
1994
1995 SDValue Ops[2] = { Lo, Hi };
1996 return DAG.getMergeValues(Ops, dl);
1997 }
1998 else {
1999 // {dHi, dLo} = {aHi, aLo} << Amt
2000 // - if (Amt>=size) then
2001 // dLo = aLo << Amt (all 0)
2002 // dLo = aLo << (Amt-size)
2003 // else
2004 // dLo = aLo << Amt
2005 // dHi = (aHi << Amt) | (aLo >> (size-Amt))
2006
2007 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
2008 DAG.getConstant(VTBits, dl, MVT::i32),
2009 ShAmt);
2010 SDValue Tmp1 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
2011 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
2012 DAG.getConstant(VTBits, dl, MVT::i32));
2013 SDValue Tmp2 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
2014 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2015 SDValue TrueVal = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
2016
2017 SDValue Cmp = DAG.getSetCC(dl, MVT::i1, ShAmt,
2018 DAG.getConstant(VTBits, dl, MVT::i32),
2019 ISD::SETGE);
2020 SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
2021 SDValue Hi = DAG.getNode(ISD::SELECT, dl, VT, Cmp, TrueVal, FalseVal);
2022
2023 SDValue Ops[2] = { Lo, Hi };
2024 return DAG.getMergeValues(Ops, dl);
2025 }
2026}
2027
2028SDValue
2029NVPTXTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
2030 switch (Op.getOpcode()) {
2031 case ISD::RETURNADDR:
2032 return SDValue();
2033 case ISD::FRAMEADDR:
2034 return SDValue();
2035 case ISD::GlobalAddress:
2036 return LowerGlobalAddress(Op, DAG);
2037 case ISD::INTRINSIC_W_CHAIN:
2038 return Op;
2039 case ISD::BUILD_VECTOR:
2040 return LowerBUILD_VECTOR(Op, DAG);
2041 case ISD::EXTRACT_SUBVECTOR:
2042 return Op;
2043 case ISD::EXTRACT_VECTOR_ELT:
2044 return LowerEXTRACT_VECTOR_ELT(Op, DAG);
2045 case ISD::CONCAT_VECTORS:
2046 return LowerCONCAT_VECTORS(Op, DAG);
2047 case ISD::STORE:
2048 return LowerSTORE(Op, DAG);
2049 case ISD::LOAD:
2050 return LowerLOAD(Op, DAG);
2051 case ISD::SHL_PARTS:
2052 return LowerShiftLeftParts(Op, DAG);
2053 case ISD::SRA_PARTS:
2054 case ISD::SRL_PARTS:
2055 return LowerShiftRightParts(Op, DAG);
2056 case ISD::SELECT:
2057 return LowerSelect(Op, DAG);
2058 default:
2059 llvm_unreachable("Custom lowering not defined for operation")::llvm::llvm_unreachable_internal("Custom lowering not defined for operation"
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/NVPTX/NVPTXISelLowering.cpp"
, 2059)
;
2060 }
2061}
2062
2063SDValue NVPTXTargetLowering::LowerSelect(SDValue Op, SelectionDAG &DAG) const {
2064 SDValue Op0 = Op->getOperand(0);
2065 SDValue Op1 = Op->getOperand(1);
2066 SDValue Op2 = Op->getOperand(2);
2067 SDLoc DL(Op.getNode());
2068
2069 assert(Op.getValueType() == MVT::i1 && "Custom lowering enabled only for i1")(static_cast <bool> (Op.getValueType() == MVT::i1 &&
"Custom lowering enabled only for i1") ? void (0) : __assert_fail
("Op.getValueType() == MVT::i1 && \"Custom lowering enabled only for i1\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/NVPTX/NVPTXISelLowering.cpp"
, 2069, __extension__ __PRETTY_FUNCTION__))
;
2070
2071 Op1 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, Op1);
2072 Op2 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, Op2);
2073 SDValue Select = DAG.getNode(ISD::SELECT, DL, MVT::i32, Op0, Op1, Op2);
2074 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Select);
2075
2076 return Trunc;
2077}
2078
2079SDValue NVPTXTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
2080 if (Op.getValueType() == MVT::i1)
2081 return LowerLOADi1(Op, DAG);
2082
2083 // v2f16 is legal, so we can't rely on legalizer to handle unaligned
2084 // loads and have to handle it here.
2085 if (Op.getValueType() == MVT::v2f16) {
2086 LoadSDNode *Load = cast<LoadSDNode>(Op);
2087 EVT MemVT = Load->getMemoryVT();
2088 if (!allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), MemVT,
2089 Load->getAddressSpace(), Load->getAlignment())) {
2090 SDValue Ops[2];
2091 std::tie(Ops[0], Ops[1]) = expandUnalignedLoad(Load, DAG);
2092 return DAG.getMergeValues(Ops, SDLoc(Op));
2093 }
2094 }
2095
2096 return SDValue();
2097}
2098
2099// v = ld i1* addr
2100// =>
2101// v1 = ld i8* addr (-> i16)
2102// v = trunc i16 to i1
2103SDValue NVPTXTargetLowering::LowerLOADi1(SDValue Op, SelectionDAG &DAG) const {
2104 SDNode *Node = Op.getNode();
2105 LoadSDNode *LD = cast<LoadSDNode>(Node);
2106 SDLoc dl(Node);
2107 assert(LD->getExtensionType() == ISD::NON_EXTLOAD)(static_cast <bool> (LD->getExtensionType() == ISD::
NON_EXTLOAD) ? void (0) : __assert_fail ("LD->getExtensionType() == ISD::NON_EXTLOAD"
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/NVPTX/NVPTXISelLowering.cpp"
, 2107, __extension__ __PRETTY_FUNCTION__))
;
2108 assert(Node->getValueType(0) == MVT::i1 &&(static_cast <bool> (Node->getValueType(0) == MVT::i1
&& "Custom lowering for i1 load only") ? void (0) : __assert_fail
("Node->getValueType(0) == MVT::i1 && \"Custom lowering for i1 load only\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/NVPTX/NVPTXISelLowering.cpp"
, 2109, __extension__ __PRETTY_FUNCTION__))
2109 "Custom lowering for i1 load only")(static_cast <bool> (Node->getValueType(0) == MVT::i1
&& "Custom lowering for i1 load only") ? void (0) : __assert_fail
("Node->getValueType(0) == MVT::i1 && \"Custom lowering for i1 load only\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/NVPTX/NVPTXISelLowering.cpp"
, 2109, __extension__ __PRETTY_FUNCTION__))
;
2110 SDValue newLD = DAG.getLoad(MVT::i16, dl, LD->getChain(), LD->getBasePtr(),
2111 LD->getPointerInfo(), LD->getAlignment(),
2112 LD->getMemOperand()->getFlags());
2113 SDValue result = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, newLD);
2114 // The legalizer (the caller) is expecting two values from the legalized
2115 // load, so we build a MergeValues node for it. See ExpandUnalignedLoad()
2116 // in LegalizeDAG.cpp which also uses MergeValues.
2117 SDValue Ops[] = { result, LD->getChain() };
2118 return DAG.getMergeValues(Ops, dl);
2119}
2120
2121SDValue NVPTXTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
2122 StoreSDNode *Store = cast<StoreSDNode>(Op);
2123 EVT VT = Store->getMemoryVT();
2124
2125 if (VT == MVT::i1)
2126 return LowerSTOREi1(Op, DAG);
2127
2128 // v2f16 is legal, so we can't rely on legalizer to handle unaligned
2129 // stores and have to handle it here.
2130 if (VT == MVT::v2f16 &&
2131 !allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), VT,
2132 Store->getAddressSpace(), Store->getAlignment()))
2133 return expandUnalignedStore(Store, DAG);
2134
2135 if (VT.isVector())
2136 return LowerSTOREVector(Op, DAG);
2137
2138 return SDValue();
2139}
2140
2141SDValue
2142NVPTXTargetLowering::LowerSTOREVector(SDValue Op, SelectionDAG &DAG) const {
2143 SDNode *N = Op.getNode();
2144 SDValue Val = N->getOperand(1);
2145 SDLoc DL(N);
2146 EVT ValVT = Val.getValueType();
2147
2148 if (ValVT.isVector()) {
2149 // We only handle "native" vector sizes for now, e.g. <4 x double> is not
2150 // legal. We can (and should) split that into 2 stores of <2 x double> here
2151 // but I'm leaving that as a TODO for now.
2152 if (!ValVT.isSimple())
2153 return SDValue();
2154 switch (ValVT.getSimpleVT().SimpleTy) {
2155 default:
2156 return SDValue();
2157 case MVT::v2i8:
2158 case MVT::v2i16:
2159 case MVT::v2i32:
2160 case MVT::v2i64:
2161 case MVT::v2f16:
2162 case MVT::v2f32:
2163 case MVT::v2f64:
2164 case MVT::v4i8:
2165 case MVT::v4i16:
2166 case MVT::v4i32:
2167 case MVT::v4f16:
2168 case MVT::v4f32:
2169 case MVT::v8f16: // <4 x f16x2>
2170 // This is a "native" vector type
2171 break;
2172 }
2173
2174 MemSDNode *MemSD = cast<MemSDNode>(N);
2175 const DataLayout &TD = DAG.getDataLayout();
2176
2177 unsigned Align = MemSD->getAlignment();
2178 unsigned PrefAlign =
2179 TD.getPrefTypeAlignment(ValVT.getTypeForEVT(*DAG.getContext()));
2180 if (Align < PrefAlign) {
2181 // This store is not sufficiently aligned, so bail out and let this vector
2182 // store be scalarized. Note that we may still be able to emit smaller
2183 // vector stores. For example, if we are storing a <4 x float> with an
2184 // alignment of 8, this check will fail but the legalizer will try again
2185 // with 2 x <2 x float>, which will succeed with an alignment of 8.
2186 return SDValue();
2187 }
2188
2189 unsigned Opcode = 0;
2190 EVT EltVT = ValVT.getVectorElementType();
2191 unsigned NumElts = ValVT.getVectorNumElements();
2192
2193 // Since StoreV2 is a target node, we cannot rely on DAG type legalization.
2194 // Therefore, we must ensure the type is legal. For i1 and i8, we set the
2195 // stored type to i16 and propagate the "real" type as the memory type.
2196 bool NeedExt = false;
2197 if (EltVT.getSizeInBits() < 16)
2198 NeedExt = true;
2199
2200 bool StoreF16x2 = false;
2201 switch (NumElts) {
2202 default:
2203 return SDValue();
2204 case 2:
2205 Opcode = NVPTXISD::StoreV2;
2206 break;
2207 case 4:
2208 Opcode = NVPTXISD::StoreV4;
2209 break;
2210 case 8:
2211 // v8f16 is a special case. PTX doesn't have st.v8.f16
2212 // instruction. Instead, we split the vector into v2f16 chunks and
2213 // store them with st.v4.b32.
2214 assert(EltVT == MVT::f16 && "Wrong type for the vector.")(static_cast <bool> (EltVT == MVT::f16 && "Wrong type for the vector."
) ? void (0) : __assert_fail ("EltVT == MVT::f16 && \"Wrong type for the vector.\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/NVPTX/NVPTXISelLowering.cpp"
, 2214, __extension__ __PRETTY_FUNCTION__))
;
2215 Opcode = NVPTXISD::StoreV4;
2216 StoreF16x2 = true;
2217 break;
2218 }
2219
2220 SmallVector<SDValue, 8> Ops;
2221
2222 // First is the chain
2223 Ops.push_back(N->getOperand(0));
2224
2225 if (StoreF16x2) {
2226 // Combine f16,f16 -> v2f16
2227 NumElts /= 2;
2228 for (unsigned i = 0; i < NumElts; ++i) {
2229 SDValue E0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f16, Val,
2230 DAG.getIntPtrConstant(i * 2, DL));
2231 SDValue E1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f16, Val,
2232 DAG.getIntPtrConstant(i * 2 + 1, DL));
2233 SDValue V2 = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v2f16, E0, E1);
2234 Ops.push_back(V2);
2235 }
2236 } else {
2237 // Then the split values
2238 for (unsigned i = 0; i < NumElts; ++i) {
2239 SDValue ExtVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, Val,
2240 DAG.getIntPtrConstant(i, DL));
2241 if (NeedExt)
2242 ExtVal = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i16, ExtVal);
2243 Ops.push_back(ExtVal);
2244 }
2245 }
2246
2247 // Then any remaining arguments
2248 Ops.append(N->op_begin() + 2, N->op_end());
2249
2250 SDValue NewSt =
2251 DAG.getMemIntrinsicNode(Opcode, DL, DAG.getVTList(MVT::Other), Ops,
2252 MemSD->getMemoryVT(), MemSD->getMemOperand());
2253
2254 // return DCI.CombineTo(N, NewSt, true);
2255 return NewSt;
2256 }
2257
2258 return SDValue();
2259}
2260
2261// st i1 v, addr
2262// =>
2263// v1 = zxt v to i16
2264// st.u8 i16, addr
2265SDValue NVPTXTargetLowering::LowerSTOREi1(SDValue Op, SelectionDAG &DAG) const {
2266 SDNode *Node = Op.getNode();
2267 SDLoc dl(Node);
2268 StoreSDNode *ST = cast<StoreSDNode>(Node);
2269 SDValue Tmp1 = ST->getChain();
2270 SDValue Tmp2 = ST->getBasePtr();
2271 SDValue Tmp3 = ST->getValue();
2272 assert(Tmp3.getValueType() == MVT::i1 && "Custom lowering for i1 store only")(static_cast <bool> (Tmp3.getValueType() == MVT::i1 &&
"Custom lowering for i1 store only") ? void (0) : __assert_fail
("Tmp3.getValueType() == MVT::i1 && \"Custom lowering for i1 store only\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/NVPTX/NVPTXISelLowering.cpp"
, 2272, __extension__ __PRETTY_FUNCTION__))
;
2273 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Tmp3);
2274 SDValue Result =
2275 DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(), MVT::i8,
2276 ST->getAlignment(), ST->getMemOperand()->getFlags());
2277 return Result;
2278}
2279
2280SDValue
2281NVPTXTargetLowering::getParamSymbol(SelectionDAG &DAG, int idx, EVT v) const {
2282 std::string ParamSym;
2283 raw_string_ostream ParamStr(ParamSym);
2284
2285 ParamStr << DAG.getMachineFunction().getName() << "_param_" << idx;
2286 ParamStr.flush();
2287
2288 std::string *SavedStr =
2289 nvTM->getManagedStrPool()->getManagedString(ParamSym.c_str());
2290 return DAG.getTargetExternalSymbol(SavedStr->c_str(), v);
2291}
2292
2293// Check to see if the kernel argument is image*_t or sampler_t
2294
2295static bool isImageOrSamplerVal(const Value *arg, const Module *context) {
2296 static const char *const specialTypes[] = { "struct._image2d_t",
2297 "struct._image3d_t",
2298 "struct._sampler_t" };
2299
2300 Type *Ty = arg->getType();
2301 auto *PTy = dyn_cast<PointerType>(Ty);
2302
2303 if (!PTy)
2304 return false;
2305
2306 if (!context)
2307 return false;
2308
2309 auto *STy = dyn_cast<StructType>(PTy->getElementType());
2310 if (!STy || STy->isLiteral())
2311 return false;
2312
2313 return std::find(std::begin(specialTypes), std::end(specialTypes),
2314 STy->getName()) != std::end(specialTypes);
2315}
2316
2317SDValue NVPTXTargetLowering::LowerFormalArguments(
2318 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
2319 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
2320 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
2321 MachineFunction &MF = DAG.getMachineFunction();
2322 const DataLayout &DL = DAG.getDataLayout();
2323 auto PtrVT = getPointerTy(DAG.getDataLayout());
2324
2325 const Function *F = &MF.getFunction();
2326 const AttributeList &PAL = F->getAttributes();
2327 const TargetLowering *TLI = STI.getTargetLowering();
2328
2329 SDValue Root = DAG.getRoot();
2330 std::vector<SDValue> OutChains;
2331
2332 bool isABI = (STI.getSmVersion() >= 20);
2333 assert(isABI && "Non-ABI compilation is not supported")(static_cast <bool> (isABI && "Non-ABI compilation is not supported"
) ? void (0) : __assert_fail ("isABI && \"Non-ABI compilation is not supported\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/NVPTX/NVPTXISelLowering.cpp"
, 2333, __extension__ __PRETTY_FUNCTION__))
;
2334 if (!isABI)
2335 return Chain;
2336
2337 std::vector<Type *> argTypes;
2338 std::vector<const Argument *> theArgs;
2339 for (const Argument &I : F->args()) {
2340 theArgs.push_back(&I);
2341 argTypes.push_back(I.getType());
2342 }
2343 // argTypes.size() (or theArgs.size()) and Ins.size() need not match.
2344 // Ins.size() will be larger
2345 // * if there is an aggregate argument with multiple fields (each field
2346 // showing up separately in Ins)
2347 // * if there is a vector argument with more than typical vector-length
2348 // elements (generally if more than 4) where each vector element is
2349 // individually present in Ins.
2350 // So a different index should be used for indexing into Ins.
2351 // See similar issue in LowerCall.
2352 unsigned InsIdx = 0;
2353
2354 int idx = 0;
2355 for (unsigned i = 0, e = theArgs.size(); i != e; ++i, ++idx, ++InsIdx) {
2356 Type *Ty = argTypes[i];
2357
2358 // If the kernel argument is image*_t or sampler_t, convert it to
2359 // a i32 constant holding the parameter position. This can later
2360 // matched in the AsmPrinter to output the correct mangled name.
2361 if (isImageOrSamplerVal(
2362 theArgs[i],
2363 (theArgs[i]->getParent() ? theArgs[i]->getParent()->getParent()
2364 : nullptr))) {
2365 assert(isKernelFunction(*F) &&(static_cast <bool> (isKernelFunction(*F) && "Only kernels can have image/sampler params"
) ? void (0) : __assert_fail ("isKernelFunction(*F) && \"Only kernels can have image/sampler params\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/NVPTX/NVPTXISelLowering.cpp"
, 2366, __extension__ __PRETTY_FUNCTION__))
2366 "Only kernels can have image/sampler params")(static_cast <bool> (isKernelFunction(*F) && "Only kernels can have image/sampler params"
) ? void (0) : __assert_fail ("isKernelFunction(*F) && \"Only kernels can have image/sampler params\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/NVPTX/NVPTXISelLowering.cpp"
, 2366, __extension__ __PRETTY_FUNCTION__))
;
2367 InVals.push_back(DAG.getConstant(i + 1, dl, MVT::i32));
2368 continue;
2369 }
2370
2371 if (theArgs[i]->use_empty()) {
2372 // argument is dead
2373 if (Ty->isAggregateType() || Ty->isIntegerTy(128)) {
2374 SmallVector<EVT, 16> vtparts;
2375
2376 ComputePTXValueVTs(*this, DAG.getDataLayout(), Ty, vtparts);
2377 assert(vtparts.size() > 0 && "empty aggregate type not expected")(static_cast <bool> (vtparts.size() > 0 && "empty aggregate type not expected"
) ? void (0) : __assert_fail ("vtparts.size() > 0 && \"empty aggregate type not expected\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/NVPTX/NVPTXISelLowering.cpp"
, 2377, __extension__ __PRETTY_FUNCTION__))
;
2378 for (unsigned parti = 0, parte = vtparts.size(); parti != parte;
2379 ++parti) {
2380 InVals.push_back(DAG.getNode(ISD::UNDEF, dl, Ins[InsIdx].VT));
2381 ++InsIdx;
2382 }
2383 if (vtparts.size() > 0)
2384 --InsIdx;
2385 continue;
2386 }
2387 if (Ty->isVectorTy()) {
2388 EVT ObjectVT = getValueType(DL, Ty);
2389 unsigned NumRegs = TLI->getNumRegisters(F->getContext(), ObjectVT);
2390 for (unsigned parti = 0; parti < NumRegs; ++parti) {
2391 InVals.push_back(DAG.getNode(ISD::UNDEF, dl, Ins[InsIdx].VT));
2392 ++InsIdx;
2393 }
2394 if (NumRegs > 0)
2395 --InsIdx;
2396 continue;
2397 }
2398 InVals.push_back(DAG.getNode(ISD::UNDEF, dl, Ins[InsIdx].VT));
2399 continue;
2400 }
2401
2402 // In the following cases, assign a node order of "idx+1"
2403 // to newly created nodes. The SDNodes for params have to
2404 // appear in the same order as their order of appearance
2405 // in the original function. "idx+1" holds that order.
2406 if (!PAL.hasParamAttribute(i, Attribute::ByVal)) {
2407 bool aggregateIsPacked = false;
2408 if (StructType *STy = dyn_cast<StructType>(Ty))
2409 aggregateIsPacked = STy->isPacked();
2410
2411 SmallVector<EVT, 16> VTs;
2412 SmallVector<uint64_t, 16> Offsets;
2413 ComputePTXValueVTs(*this, DL, Ty, VTs, &Offsets, 0);
2414 assert(VTs.size() > 0 && "Unexpected empty type.")(static_cast <bool> (VTs.size() > 0 && "Unexpected empty type."
) ? void (0) : __assert_fail ("VTs.size() > 0 && \"Unexpected empty type.\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/NVPTX/NVPTXISelLowering.cpp"
, 2414, __extension__ __PRETTY_FUNCTION__))
;
2415 auto VectorInfo =
2416 VectorizePTXValueVTs(VTs, Offsets, DL.getABITypeAlignment(Ty));
2417
2418 SDValue Arg = getParamSymbol(DAG, idx, PtrVT);
2419 int VecIdx = -1; // Index of the first element of the current vector.
2420 for (unsigned parti = 0, parte = VTs.size(); parti != parte; ++parti) {
2421 if (VectorInfo[parti] & PVF_FIRST) {
2422 assert(VecIdx == -1 && "Orphaned vector.")(static_cast <bool> (VecIdx == -1 && "Orphaned vector."
) ? void (0) : __assert_fail ("VecIdx == -1 && \"Orphaned vector.\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/NVPTX/NVPTXISelLowering.cpp"
, 2422, __extension__ __PRETTY_FUNCTION__))
;
2423 VecIdx = parti;
2424 }
2425
2426 // That's the last element of this store op.
2427 if (VectorInfo[parti] & PVF_LAST) {
2428 unsigned NumElts = parti - VecIdx + 1;
2429 EVT EltVT = VTs[parti];
2430 // i1 is loaded/stored as i8.
2431 EVT LoadVT = EltVT;
2432 if (EltVT == MVT::i1)
2433 LoadVT = MVT::i8;
2434 else if (EltVT == MVT::v2f16)
2435 // getLoad needs a vector type, but it can't handle
2436 // vectors which contain v2f16 elements. So we must load
2437 // using i32 here and then bitcast back.
2438 LoadVT = MVT::i32;
2439
2440 EVT VecVT = EVT::getVectorVT(F->getContext(), LoadVT, NumElts);
2441 SDValue VecAddr =
2442 DAG.getNode(ISD::ADD, dl, PtrVT, Arg,
2443 DAG.getConstant(Offsets[VecIdx], dl, PtrVT));
2444 Value *srcValue = Constant::getNullValue(PointerType::get(
2445 EltVT.getTypeForEVT(F->getContext()), ADDRESS_SPACE_PARAM));
2446 SDValue P =
2447 DAG.getLoad(VecVT, dl, Root, VecAddr,
2448 MachinePointerInfo(srcValue), aggregateIsPacked,
2449 MachineMemOperand::MODereferenceable |
2450 MachineMemOperand::MOInvariant);
2451 if (P.getNode())
2452 P.getNode()->setIROrder(idx + 1);
2453 for (unsigned j = 0; j < NumElts; ++j) {
2454 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, LoadVT, P,
2455 DAG.getIntPtrConstant(j, dl));
2456 // We've loaded i1 as an i8 and now must truncate it back to i1
2457 if (EltVT == MVT::i1)
2458 Elt = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Elt);
2459 // v2f16 was loaded as an i32. Now we must bitcast it back.
2460 else if (EltVT == MVT::v2f16)
2461 Elt = DAG.getNode(ISD::BITCAST, dl, MVT::v2f16, Elt);
2462 // Extend the element if necessary (e.g. an i8 is loaded
2463 // into an i16 register)
2464 if (Ins[InsIdx].VT.isInteger() &&
2465 Ins[InsIdx].VT.getSizeInBits() > LoadVT.getSizeInBits()) {
2466 unsigned Extend = Ins[InsIdx].Flags.isSExt() ? ISD::SIGN_EXTEND
2467 : ISD::ZERO_EXTEND;
2468 Elt = DAG.getNode(Extend, dl, Ins[InsIdx].VT, Elt);
2469 }
2470 InVals.push_back(Elt);
2471 }
2472
2473 // Reset vector tracking state.
2474 VecIdx = -1;
2475 }
2476 ++InsIdx;
2477 }
2478 if (VTs.size() > 0)
2479 --InsIdx;
2480 continue;
2481 }
2482
2483 // Param has ByVal attribute
2484 // Return MoveParam(param symbol).
2485 // Ideally, the param symbol can be returned directly,
2486 // but when SDNode builder decides to use it in a CopyToReg(),
2487 // machine instruction fails because TargetExternalSymbol
2488 // (not lowered) is target dependent, and CopyToReg assumes
2489 // the source is lowered.
2490 EVT ObjectVT = getValueType(DL, Ty);
2491 assert(ObjectVT == Ins[InsIdx].VT &&(static_cast <bool> (ObjectVT == Ins[InsIdx].VT &&
"Ins type did not match function type") ? void (0) : __assert_fail
("ObjectVT == Ins[InsIdx].VT && \"Ins type did not match function type\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/NVPTX/NVPTXISelLowering.cpp"
, 2492, __extension__ __PRETTY_FUNCTION__))
2492 "Ins type did not match function type")(static_cast <bool> (ObjectVT == Ins[InsIdx].VT &&
"Ins type did not match function type") ? void (0) : __assert_fail
("ObjectVT == Ins[InsIdx].VT && \"Ins type did not match function type\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/NVPTX/NVPTXISelLowering.cpp"
, 2492, __extension__ __PRETTY_FUNCTION__))
;
2493 SDValue Arg = getParamSymbol(DAG, idx, PtrVT);
2494 SDValue p = DAG.getNode(NVPTXISD::MoveParam, dl, ObjectVT, Arg);
2495 if (p.getNode())
2496 p.getNode()->setIROrder(idx + 1);
2497 InVals.push_back(p);
2498 }
2499
2500 // Clang will check explicit VarArg and issue error if any. However, Clang
2501 // will let code with
2502 // implicit var arg like f() pass. See bug 617733.
2503 // We treat this case as if the arg list is empty.
2504 // if (F.isVarArg()) {
2505 // assert(0 && "VarArg not supported yet!");
2506 //}
2507
2508 if (!OutChains.empty())
2509 DAG.setRoot(DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains));
2510
2511 return Chain;
2512}
2513
2514SDValue
2515NVPTXTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
2516 bool isVarArg,
2517 const SmallVectorImpl<ISD::OutputArg> &Outs,
2518 const SmallVectorImpl<SDValue> &OutVals,
2519 const SDLoc &dl, SelectionDAG &DAG) const {
2520 MachineFunction &MF = DAG.getMachineFunction();
2521 Type *RetTy = MF.getFunction().getReturnType();
2522
2523 bool isABI = (STI.getSmVersion() >= 20);
1
Assuming the condition is true
2524 assert(isABI && "Non-ABI compilation is not supported")(static_cast <bool> (isABI && "Non-ABI compilation is not supported"
) ? void (0) : __assert_fail ("isABI && \"Non-ABI compilation is not supported\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/NVPTX/NVPTXISelLowering.cpp"
, 2524, __extension__ __PRETTY_FUNCTION__))
;
2525 if (!isABI)
2
Taking false branch
2526 return Chain;
2527
2528 const DataLayout DL = DAG.getDataLayout();
2529 SmallVector<EVT, 16> VTs;
2530 SmallVector<uint64_t, 16> Offsets;
2531 ComputePTXValueVTs(*this, DL, RetTy, VTs, &Offsets);
2532 assert(VTs.size() == OutVals.size() && "Bad return value decomposition")(static_cast <bool> (VTs.size() == OutVals.size() &&
"Bad return value decomposition") ? void (0) : __assert_fail
("VTs.size() == OutVals.size() && \"Bad return value decomposition\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/NVPTX/NVPTXISelLowering.cpp"
, 2532, __extension__ __PRETTY_FUNCTION__))
;
2533
2534 auto VectorInfo = VectorizePTXValueVTs(
5
Calling 'VectorizePTXValueVTs'
2535 VTs, Offsets, RetTy->isSized() ? DL.getABITypeAlignment(RetTy) : 1);
3
Assuming the condition is false
4
'?' condition is false
2536
2537 // PTX Interoperability Guide 3.3(A): [Integer] Values shorter than
2538 // 32-bits are sign extended or zero extended, depending on whether
2539 // they are signed or unsigned types.
2540 bool ExtendIntegerRetVal =
2541 RetTy->isIntegerTy() && DL.getTypeAllocSizeInBits(RetTy) < 32;
2542
2543 SmallVector<SDValue, 6> StoreOperands;
2544 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
2545 // New load/store. Record chain and offset operands.
2546 if (VectorInfo[i] & PVF_FIRST) {
2547 assert(StoreOperands.empty() && "Orphaned operand list.")(static_cast <bool> (StoreOperands.empty() && "Orphaned operand list."
) ? void (0) : __assert_fail ("StoreOperands.empty() && \"Orphaned operand list.\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/NVPTX/NVPTXISelLowering.cpp"
, 2547, __extension__ __PRETTY_FUNCTION__))
;
2548 StoreOperands.push_back(Chain);
2549 StoreOperands.push_back(DAG.getConstant(Offsets[i], dl, MVT::i32));
2550 }
2551
2552 SDValue RetVal = OutVals[i];
2553 if (ExtendIntegerRetVal) {
2554 RetVal = DAG.getNode(Outs[i].Flags.isSExt() ? ISD::SIGN_EXTEND
2555 : ISD::ZERO_EXTEND,
2556 dl, MVT::i32, RetVal);
2557 } else if (RetVal.getValueSizeInBits() < 16) {
2558 // Use 16-bit registers for small load-stores as it's the
2559 // smallest general purpose register size supported by NVPTX.
2560 RetVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i16, RetVal);
2561 }
2562
2563 // Record the value to return.
2564 StoreOperands.push_back(RetVal);
2565
2566 // That's the last element of this store op.
2567 if (VectorInfo[i] & PVF_LAST) {
2568 NVPTXISD::NodeType Op;
2569 unsigned NumElts = StoreOperands.size() - 2;
2570 switch (NumElts) {
2571 case 1:
2572 Op = NVPTXISD::StoreRetval;
2573 break;
2574 case 2:
2575 Op = NVPTXISD::StoreRetvalV2;
2576 break;
2577 case 4:
2578 Op = NVPTXISD::StoreRetvalV4;
2579 break;
2580 default:
2581 llvm_unreachable("Invalid vector info.")::llvm::llvm_unreachable_internal("Invalid vector info.", "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/NVPTX/NVPTXISelLowering.cpp"
, 2581)
;
2582 }
2583
2584 // Adjust type of load/store op if we've extended the scalar
2585 // return value.
2586 EVT TheStoreType = ExtendIntegerRetVal ? MVT::i32 : VTs[i];
2587 Chain = DAG.getMemIntrinsicNode(Op, dl, DAG.getVTList(MVT::Other),
2588 StoreOperands, TheStoreType,
2589 MachinePointerInfo(), /* Align */ 1,
2590 MachineMemOperand::MOStore);
2591 // Cleanup vector state.
2592 StoreOperands.clear();
2593 }
2594 }
2595
2596 return DAG.getNode(NVPTXISD::RET_FLAG, dl, MVT::Other, Chain);
2597}
2598
2599void NVPTXTargetLowering::LowerAsmOperandForConstraint(
2600 SDValue Op, std::string &Constraint, std::vector<SDValue> &Ops,
2601 SelectionDAG &DAG) const {
2602 if (Constraint.length() > 1)
2603 return;
2604 else
2605 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
2606}
2607
2608static unsigned getOpcForTextureInstr(unsigned Intrinsic) {
2609 switch (Intrinsic) {
2610 default:
2611 return 0;
2612
2613 case Intrinsic::nvvm_tex_1d_v4f32_s32:
2614 return NVPTXISD::Tex1DFloatS32;
2615 case Intrinsic::nvvm_tex_1d_v4f32_f32:
2616 return NVPTXISD::Tex1DFloatFloat;
2617 case Intrinsic::nvvm_tex_1d_level_v4f32_f32:
2618 return NVPTXISD::Tex1DFloatFloatLevel;
2619 case Intrinsic::nvvm_tex_1d_grad_v4f32_f32:
2620 return NVPTXISD::Tex1DFloatFloatGrad;
2621 case Intrinsic::nvvm_tex_1d_v4s32_s32:
2622 return NVPTXISD::Tex1DS32S32;
2623 case Intrinsic::nvvm_tex_1d_v4s32_f32:
2624 return NVPTXISD::Tex1DS32Float;
2625 case Intrinsic::nvvm_tex_1d_level_v4s32_f32:
2626 return NVPTXISD::Tex1DS32FloatLevel;
2627 case Intrinsic::nvvm_tex_1d_grad_v4s32_f32:
2628 return NVPTXISD::Tex1DS32FloatGrad;
2629 case Intrinsic::nvvm_tex_1d_v4u32_s32:
2630 return NVPTXISD::Tex1DU32S32;
2631 case Intrinsic::nvvm_tex_1d_v4u32_f32:
2632 return NVPTXISD::Tex1DU32Float;
2633 case Intrinsic::nvvm_tex_1d_level_v4u32_f32:
2634 return NVPTXISD::Tex1DU32FloatLevel;
2635 case Intrinsic::nvvm_tex_1d_grad_v4u32_f32:
2636 return NVPTXISD::Tex1DU32FloatGrad;
2637
2638 case Intrinsic::nvvm_tex_1d_array_v4f32_s32:
2639 return NVPTXISD::Tex1DArrayFloatS32;
2640 case Intrinsic::nvvm_tex_1d_array_v4f32_f32:
2641 return NVPTXISD::Tex1DArrayFloatFloat;
2642 case Intrinsic::nvvm_tex_1d_array_level_v4f32_f32:
2643 return NVPTXISD::Tex1DArrayFloatFloatLevel;
2644 case Intrinsic::nvvm_tex_1d_array_grad_v4f32_f32:
2645 return NVPTXISD::Tex1DArrayFloatFloatGrad;
2646 case Intrinsic::nvvm_tex_1d_array_v4s32_s32:
2647 return NVPTXISD::Tex1DArrayS32S32;
2648 case Intrinsic::nvvm_tex_1d_array_v4s32_f32:
2649 return NVPTXISD::Tex1DArrayS32Float;
2650 case Intrinsic::nvvm_tex_1d_array_level_v4s32_f32:
2651 return NVPTXISD::Tex1DArrayS32FloatLevel;
2652 case Intrinsic::nvvm_tex_1d_array_grad_v4s32_f32:
2653 return NVPTXISD::Tex1DArrayS32FloatGrad;
2654 case Intrinsic::nvvm_tex_1d_array_v4u32_s32:
2655 return NVPTXISD::Tex1DArrayU32S32;
2656 case Intrinsic::nvvm_tex_1d_array_v4u32_f32:
2657 return NVPTXISD::Tex1DArrayU32Float;
2658 case Intrinsic::nvvm_tex_1d_array_level_v4u32_f32:
2659 return NVPTXISD::Tex1DArrayU32FloatLevel;
2660 case Intrinsic::nvvm_tex_1d_array_grad_v4u32_f32:
2661 return NVPTXISD::Tex1DArrayU32FloatGrad;
2662
2663 case Intrinsic::nvvm_tex_2d_v4f32_s32:
2664 return NVPTXISD::Tex2DFloatS32;
2665 case Intrinsic::nvvm_tex_2d_v4f32_f32:
2666 return NVPTXISD::Tex2DFloatFloat;
2667 case Intrinsic::nvvm_tex_2d_level_v4f32_f32:
2668 return NVPTXISD::Tex2DFloatFloatLevel;
2669 case Intrinsic::nvvm_tex_2d_grad_v4f32_f32:
2670 return NVPTXISD::Tex2DFloatFloatGrad;
2671 case Intrinsic::nvvm_tex_2d_v4s32_s32:
2672 return NVPTXISD::Tex2DS32S32;
2673 case Intrinsic::nvvm_tex_2d_v4s32_f32:
2674 return NVPTXISD::Tex2DS32Float;
2675 case Intrinsic::nvvm_tex_2d_level_v4s32_f32:
2676 return NVPTXISD::Tex2DS32FloatLevel;
2677 case Intrinsic::nvvm_tex_2d_grad_v4s32_f32:
2678 return NVPTXISD::Tex2DS32FloatGrad;
2679 case Intrinsic::nvvm_tex_2d_v4u32_s32:
2680 return NVPTXISD::Tex2DU32S32;
2681 case Intrinsic::nvvm_tex_2d_v4u32_f32:
2682 return NVPTXISD::Tex2DU32Float;
2683 case Intrinsic::nvvm_tex_2d_level_v4u32_f32:
2684 return NVPTXISD::Tex2DU32FloatLevel;
2685 case Intrinsic::nvvm_tex_2d_grad_v4u32_f32:
2686 return NVPTXISD::Tex2DU32FloatGrad;
2687
2688 case Intrinsic::nvvm_tex_2d_array_v4f32_s32:
2689 return NVPTXISD::Tex2DArrayFloatS32;
2690 case Intrinsic::nvvm_tex_2d_array_v4f32_f32:
2691 return NVPTXISD::Tex2DArrayFloatFloat;
2692 case Intrinsic::nvvm_tex_2d_array_level_v4f32_f32:
2693 return NVPTXISD::Tex2DArrayFloatFloatLevel;
2694 case Intrinsic::nvvm_tex_2d_array_grad_v4f32_f32:
2695 return NVPTXISD::Tex2DArrayFloatFloatGrad;
2696 case Intrinsic::nvvm_tex_2d_array_v4s32_s32:
2697 return NVPTXISD::Tex2DArrayS32S32;
2698 case Intrinsic::nvvm_tex_2d_array_v4s32_f32:
2699 return NVPTXISD::Tex2DArrayS32Float;
2700 case Intrinsic::nvvm_tex_2d_array_level_v4s32_f32:
2701 return NVPTXISD::Tex2DArrayS32FloatLevel;
2702 case Intrinsic::nvvm_tex_2d_array_grad_v4s32_f32:
2703 return NVPTXISD::Tex2DArrayS32FloatGrad;
2704 case Intrinsic::nvvm_tex_2d_array_v4u32_s32:
2705 return NVPTXISD::Tex2DArrayU32S32;
2706 case Intrinsic::nvvm_tex_2d_array_v4u32_f32:
2707 return NVPTXISD::Tex2DArrayU32Float;
2708 case Intrinsic::nvvm_tex_2d_array_level_v4u32_f32:
2709 return NVPTXISD::Tex2DArrayU32FloatLevel;
2710 case Intrinsic::nvvm_tex_2d_array_grad_v4u32_f32:
2711 return NVPTXISD::Tex2DArrayU32FloatGrad;
2712
2713 case Intrinsic::nvvm_tex_3d_v4f32_s32:
2714 return NVPTXISD::Tex3DFloatS32;
2715 case Intrinsic::nvvm_tex_3d_v4f32_f32:
2716 return NVPTXISD::Tex3DFloatFloat;
2717 case Intrinsic::nvvm_tex_3d_level_v4f32_f32:
2718 return NVPTXISD::Tex3DFloatFloatLevel;
2719 case Intrinsic::nvvm_tex_3d_grad_v4f32_f32:
2720 return NVPTXISD::Tex3DFloatFloatGrad;
2721 case Intrinsic::nvvm_tex_3d_v4s32_s32:
2722 return NVPTXISD::Tex3DS32S32;
2723 case Intrinsic::nvvm_tex_3d_v4s32_f32:
2724 return NVPTXISD::Tex3DS32Float;
2725 case Intrinsic::nvvm_tex_3d_level_v4s32_f32:
2726 return NVPTXISD::Tex3DS32FloatLevel;
2727 case Intrinsic::nvvm_tex_3d_grad_v4s32_f32:
2728 return NVPTXISD::Tex3DS32FloatGrad;
2729 case Intrinsic::nvvm_tex_3d_v4u32_s32:
2730 return NVPTXISD::Tex3DU32S32;
2731 case Intrinsic::nvvm_tex_3d_v4u32_f32:
2732 return NVPTXISD::Tex3DU32Float;
2733 case Intrinsic::nvvm_tex_3d_level_v4u32_f32:
2734 return NVPTXISD::Tex3DU32FloatLevel;
2735 case Intrinsic::nvvm_tex_3d_grad_v4u32_f32:
2736 return NVPTXISD::Tex3DU32FloatGrad;
2737
2738 case Intrinsic::nvvm_tex_cube_v4f32_f32:
2739 return NVPTXISD::TexCubeFloatFloat;
2740 case Intrinsic::nvvm_tex_cube_level_v4f32_f32:
2741 return NVPTXISD::TexCubeFloatFloatLevel;
2742 case Intrinsic::nvvm_tex_cube_v4s32_f32:
2743 return NVPTXISD::TexCubeS32Float;
2744 case Intrinsic::nvvm_tex_cube_level_v4s32_f32:
2745 return NVPTXISD::TexCubeS32FloatLevel;
2746 case Intrinsic::nvvm_tex_cube_v4u32_f32:
2747 return NVPTXISD::TexCubeU32Float;
2748 case Intrinsic::nvvm_tex_cube_level_v4u32_f32:
2749 return NVPTXISD::TexCubeU32FloatLevel;
2750
2751 case Intrinsic::nvvm_tex_cube_array_v4f32_f32:
2752 return NVPTXISD::TexCubeArrayFloatFloat;
2753 case Intrinsic::nvvm_tex_cube_array_level_v4f32_f32:
2754 return NVPTXISD::TexCubeArrayFloatFloatLevel;
2755 case Intrinsic::nvvm_tex_cube_array_v4s32_f32:
2756 return NVPTXISD::TexCubeArrayS32Float;
2757 case Intrinsic::nvvm_tex_cube_array_level_v4s32_f32:
2758 return NVPTXISD::TexCubeArrayS32FloatLevel;
2759 case Intrinsic::nvvm_tex_cube_array_v4u32_f32:
2760 return NVPTXISD::TexCubeArrayU32Float;
2761 case Intrinsic::nvvm_tex_cube_array_level_v4u32_f32:
2762 return NVPTXISD::TexCubeArrayU32FloatLevel;
2763
2764 case Intrinsic::nvvm_tld4_r_2d_v4f32_f32:
2765 return NVPTXISD::Tld4R2DFloatFloat;
2766 case Intrinsic::nvvm_tld4_g_2d_v4f32_f32:
2767 return NVPTXISD::Tld4G2DFloatFloat;
2768 case Intrinsic::nvvm_tld4_b_2d_v4f32_f32:
2769 return NVPTXISD::Tld4B2DFloatFloat;
2770 case Intrinsic::nvvm_tld4_a_2d_v4f32_f32:
2771 return NVPTXISD::Tld4A2DFloatFloat;
2772 case Intrinsic::nvvm_tld4_r_2d_v4s32_f32:
2773 return NVPTXISD::Tld4R2DS64Float;
2774 case Intrinsic::nvvm_tld4_g_2d_v4s32_f32:
2775 return NVPTXISD::Tld4G2DS64Float;
2776 case Intrinsic::nvvm_tld4_b_2d_v4s32_f32:
2777 return NVPTXISD::Tld4B2DS64Float;
2778 case Intrinsic::nvvm_tld4_a_2d_v4s32_f32:
2779 return NVPTXISD::Tld4A2DS64Float;
2780 case Intrinsic::nvvm_tld4_r_2d_v4u32_f32:
2781 return NVPTXISD::Tld4R2DU64Float;
2782 case Intrinsic::nvvm_tld4_g_2d_v4u32_f32:
2783 return NVPTXISD::Tld4G2DU64Float;
2784 case Intrinsic::nvvm_tld4_b_2d_v4u32_f32:
2785 return NVPTXISD::Tld4B2DU64Float;
2786 case Intrinsic::nvvm_tld4_a_2d_v4u32_f32:
2787 return NVPTXISD::Tld4A2DU64Float;
2788
2789 case Intrinsic::nvvm_tex_unified_1d_v4f32_s32:
2790 return NVPTXISD::TexUnified1DFloatS32;
2791 case Intrinsic::nvvm_tex_unified_1d_v4f32_f32:
2792 return NVPTXISD::TexUnified1DFloatFloat;
2793 case Intrinsic::nvvm_tex_unified_1d_level_v4f32_f32:
2794 return NVPTXISD::TexUnified1DFloatFloatLevel;
2795 case Intrinsic::nvvm_tex_unified_1d_grad_v4f32_f32:
2796 return NVPTXISD::TexUnified1DFloatFloatGrad;
2797 case Intrinsic::nvvm_tex_unified_1d_v4s32_s32:
2798 return NVPTXISD::TexUnified1DS32S32;
2799 case Intrinsic::nvvm_tex_unified_1d_v4s32_f32:
2800 return NVPTXISD::TexUnified1DS32Float;
2801 case Intrinsic::nvvm_tex_unified_1d_level_v4s32_f32:
2802 return NVPTXISD::TexUnified1DS32FloatLevel;
2803 case Intrinsic::nvvm_tex_unified_1d_grad_v4s32_f32:
2804 return NVPTXISD::TexUnified1DS32FloatGrad;
2805 case Intrinsic::nvvm_tex_unified_1d_v4u32_s32:
2806 return NVPTXISD::TexUnified1DU32S32;
2807 case Intrinsic::nvvm_tex_unified_1d_v4u32_f32:
2808 return NVPTXISD::TexUnified1DU32Float;
2809 case Intrinsic::nvvm_tex_unified_1d_level_v4u32_f32:
2810 return NVPTXISD::TexUnified1DU32FloatLevel;
2811 case Intrinsic::nvvm_tex_unified_1d_grad_v4u32_f32:
2812 return NVPTXISD::TexUnified1DU32FloatGrad;
2813
2814 case Intrinsic::nvvm_tex_unified_1d_array_v4f32_s32:
2815 return NVPTXISD::TexUnified1DArrayFloatS32;
2816 case Intrinsic::nvvm_tex_unified_1d_array_v4f32_f32:
2817 return NVPTXISD::TexUnified1DArrayFloatFloat;
2818 case Intrinsic::nvvm_tex_unified_1d_array_level_v4f32_f32:
2819 return NVPTXISD::TexUnified1DArrayFloatFloatLevel;
2820 case Intrinsic::nvvm_tex_unified_1d_array_grad_v4f32_f32:
2821 return NVPTXISD::TexUnified1DArrayFloatFloatGrad;
2822 case Intrinsic::nvvm_tex_unified_1d_array_v4s32_s32:
2823 return NVPTXISD::TexUnified1DArrayS32S32;
2824 case Intrinsic::nvvm_tex_unified_1d_array_v4s32_f32:
2825 return NVPTXISD::TexUnified1DArrayS32Float;
2826 case Intrinsic::nvvm_tex_unified_1d_array_level_v4s32_f32:
2827 return NVPTXISD::TexUnified1DArrayS32FloatLevel;
2828 case Intrinsic::nvvm_tex_unified_1d_array_grad_v4s32_f32:
2829 return NVPTXISD::TexUnified1DArrayS32FloatGrad;
2830 case Intrinsic::nvvm_tex_unified_1d_array_v4u32_s32:
2831 return NVPTXISD::TexUnified1DArrayU32S32;
2832 case Intrinsic::nvvm_tex_unified_1d_array_v4u32_f32:
2833 return NVPTXISD::TexUnified1DArrayU32Float;
2834 case Intrinsic::nvvm_tex_unified_1d_array_level_v4u32_f32:
2835 return NVPTXISD::TexUnified1DArrayU32FloatLevel;
2836 case Intrinsic::nvvm_tex_unified_1d_array_grad_v4u32_f32:
2837 return NVPTXISD::TexUnified1DArrayU32FloatGrad;
2838
2839 case Intrinsic::nvvm_tex_unified_2d_v4f32_s32:
2840 return NVPTXISD::TexUnified2DFloatS32;
2841 case Intrinsic::nvvm_tex_unified_2d_v4f32_f32:
2842 return NVPTXISD::TexUnified2DFloatFloat;
2843 case Intrinsic::nvvm_tex_unified_2d_level_v4f32_f32:
2844 return NVPTXISD::TexUnified2DFloatFloatLevel;
2845 case Intrinsic::nvvm_tex_unified_2d_grad_v4f32_f32:
2846 return NVPTXISD::TexUnified2DFloatFloatGrad;
2847 case Intrinsic::nvvm_tex_unified_2d_v4s32_s32:
2848 return NVPTXISD::TexUnified2DS32S32;
2849 case Intrinsic::nvvm_tex_unified_2d_v4s32_f32:
2850 return NVPTXISD::TexUnified2DS32Float;
2851 case Intrinsic::nvvm_tex_unified_2d_level_v4s32_f32:
2852 return NVPTXISD::TexUnified2DS32FloatLevel;
2853 case Intrinsic::nvvm_tex_unified_2d_grad_v4s32_f32:
2854 return NVPTXISD::TexUnified2DS32FloatGrad;
2855 case Intrinsic::nvvm_tex_unified_2d_v4u32_s32:
2856 return NVPTXISD::TexUnified2DU32S32;
2857 case Intrinsic::nvvm_tex_unified_2d_v4u32_f32:
2858 return NVPTXISD::TexUnified2DU32Float;
2859 case Intrinsic::nvvm_tex_unified_2d_level_v4u32_f32:
2860 return NVPTXISD::TexUnified2DU32FloatLevel;
2861 case Intrinsic::nvvm_tex_unified_2d_grad_v4u32_f32:
2862 return NVPTXISD::TexUnified2DU32FloatGrad;
2863
2864 case Intrinsic::nvvm_tex_unified_2d_array_v4f32_s32:
2865 return NVPTXISD::TexUnified2DArrayFloatS32;
2866 case Intrinsic::nvvm_tex_unified_2d_array_v4f32_f32:
2867 return NVPTXISD::TexUnified2DArrayFloatFloat;
2868 case Intrinsic::nvvm_tex_unified_2d_array_level_v4f32_f32:
2869 return NVPTXISD::TexUnified2DArrayFloatFloatLevel;
2870 case Intrinsic::nvvm_tex_unified_2d_array_grad_v4f32_f32:
2871 return NVPTXISD::TexUnified2DArrayFloatFloatGrad;
2872 case Intrinsic::nvvm_tex_unified_2d_array_v4s32_s32:
2873 return NVPTXISD::TexUnified2DArrayS32S32;
2874 case Intrinsic::nvvm_tex_unified_2d_array_v4s32_f32:
2875 return NVPTXISD::TexUnified2DArrayS32Float;
2876 case Intrinsic::nvvm_tex_unified_2d_array_level_v4s32_f32:
2877 return NVPTXISD::TexUnified2DArrayS32FloatLevel;
2878 case Intrinsic::nvvm_tex_unified_2d_array_grad_v4s32_f32:
2879 return NVPTXISD::TexUnified2DArrayS32FloatGrad;
2880 case Intrinsic::nvvm_tex_unified_2d_array_v4u32_s32:
2881 return NVPTXISD::TexUnified2DArrayU32S32;
2882 case Intrinsic::nvvm_tex_unified_2d_array_v4u32_f32:
2883 return NVPTXISD::TexUnified2DArrayU32Float;
2884 case Intrinsic::nvvm_tex_unified_2d_array_level_v4u32_f32:
2885 return NVPTXISD::TexUnified2DArrayU32FloatLevel;
2886 case Intrinsic::nvvm_tex_unified_2d_array_grad_v4u32_f32:
2887 return NVPTXISD::TexUnified2DArrayU32FloatGrad;
2888
2889 case Intrinsic::nvvm_tex_unified_3d_v4f32_s32:
2890 return NVPTXISD::TexUnified3DFloatS32;
2891 case Intrinsic::nvvm_tex_unified_3d_v4f32_f32:
2892 return NVPTXISD::TexUnified3DFloatFloat;
2893 case Intrinsic::nvvm_tex_unified_3d_level_v4f32_f32:
2894 return NVPTXISD::TexUnified3DFloatFloatLevel;
2895 case Intrinsic::nvvm_tex_unified_3d_grad_v4f32_f32:
2896 return NVPTXISD::TexUnified3DFloatFloatGrad;
2897 case Intrinsic::nvvm_tex_unified_3d_v4s32_s32:
2898 return NVPTXISD::TexUnified3DS32S32;
2899 case Intrinsic::nvvm_tex_unified_3d_v4s32_f32:
2900 return NVPTXISD::TexUnified3DS32Float;
2901 case Intrinsic::nvvm_tex_unified_3d_level_v4s32_f32:
2902 return NVPTXISD::TexUnified3DS32FloatLevel;
2903 case Intrinsic::nvvm_tex_unified_3d_grad_v4s32_f32:
2904 return NVPTXISD::TexUnified3DS32FloatGrad;
2905 case Intrinsic::nvvm_tex_unified_3d_v4u32_s32:
2906 return NVPTXISD::TexUnified3DU32S32;
2907 case Intrinsic::nvvm_tex_unified_3d_v4u32_f32:
2908 return NVPTXISD::TexUnified3DU32Float;
2909 case Intrinsic::nvvm_tex_unified_3d_level_v4u32_f32:
2910 return NVPTXISD::TexUnified3DU32FloatLevel;
2911 case Intrinsic::nvvm_tex_unified_3d_grad_v4u32_f32:
2912 return NVPTXISD::TexUnified3DU32FloatGrad;
2913
2914 case Intrinsic::nvvm_tex_unified_cube_v4f32_f32:
2915 return NVPTXISD::TexUnifiedCubeFloatFloat;
2916 case Intrinsic::nvvm_tex_unified_cube_level_v4f32_f32:
2917 return NVPTXISD::TexUnifiedCubeFloatFloatLevel;
2918 case Intrinsic::nvvm_tex_unified_cube_v4s32_f32:
2919 return NVPTXISD::TexUnifiedCubeS32Float;
2920 case Intrinsic::nvvm_tex_unified_cube_level_v4s32_f32:
2921 return NVPTXISD::TexUnifiedCubeS32FloatLevel;
2922 case Intrinsic::nvvm_tex_unified_cube_v4u32_f32:
2923 return NVPTXISD::TexUnifiedCubeU32Float;
2924 case Intrinsic::nvvm_tex_unified_cube_level_v4u32_f32:
2925 return NVPTXISD::TexUnifiedCubeU32FloatLevel;
2926
2927 case Intrinsic::nvvm_tex_unified_cube_array_v4f32_f32:
2928 return NVPTXISD::TexUnifiedCubeArrayFloatFloat;
2929 case Intrinsic::nvvm_tex_unified_cube_array_level_v4f32_f32:
2930 return NVPTXISD::TexUnifiedCubeArrayFloatFloatLevel;
2931 case Intrinsic::nvvm_tex_unified_cube_array_v4s32_f32:
2932 return NVPTXISD::TexUnifiedCubeArrayS32Float;
2933 case Intrinsic::nvvm_tex_unified_cube_array_level_v4s32_f32:
2934 return NVPTXISD::TexUnifiedCubeArrayS32FloatLevel;
2935 case Intrinsic::nvvm_tex_unified_cube_array_v4u32_f32:
2936 return NVPTXISD::TexUnifiedCubeArrayU32Float;
2937 case Intrinsic::nvvm_tex_unified_cube_array_level_v4u32_f32:
2938 return NVPTXISD::TexUnifiedCubeArrayU32FloatLevel;
2939
2940 case Intrinsic::nvvm_tld4_unified_r_2d_v4f32_f32:
2941 return NVPTXISD::Tld4UnifiedR2DFloatFloat;
2942 case Intrinsic::nvvm_tld4_unified_g_2d_v4f32_f32:
2943 return NVPTXISD::Tld4UnifiedG2DFloatFloat;
2944 case Intrinsic::nvvm_tld4_unified_b_2d_v4f32_f32:
2945 return NVPTXISD::Tld4UnifiedB2DFloatFloat;
2946 case Intrinsic::nvvm_tld4_unified_a_2d_v4f32_f32:
2947 return NVPTXISD::Tld4UnifiedA2DFloatFloat;
2948 case Intrinsic::nvvm_tld4_unified_r_2d_v4s32_f32:
2949 return NVPTXISD::Tld4UnifiedR2DS64Float;
2950 case Intrinsic::nvvm_tld4_unified_g_2d_v4s32_f32:
2951 return NVPTXISD::Tld4UnifiedG2DS64Float;
2952 case Intrinsic::nvvm_tld4_unified_b_2d_v4s32_f32:
2953 return NVPTXISD::Tld4UnifiedB2DS64Float;
2954 case Intrinsic::nvvm_tld4_unified_a_2d_v4s32_f32:
2955 return NVPTXISD::Tld4UnifiedA2DS64Float;
2956 case Intrinsic::nvvm_tld4_unified_r_2d_v4u32_f32:
2957 return NVPTXISD::Tld4UnifiedR2DU64Float;
2958 case Intrinsic::nvvm_tld4_unified_g_2d_v4u32_f32:
2959 return NVPTXISD::Tld4UnifiedG2DU64Float;
2960 case Intrinsic::nvvm_tld4_unified_b_2d_v4u32_f32:
2961 return NVPTXISD::Tld4UnifiedB2DU64Float;
2962 case Intrinsic::nvvm_tld4_unified_a_2d_v4u32_f32:
2963 return NVPTXISD::Tld4UnifiedA2DU64Float;
2964 }
2965}
2966
2967static unsigned getOpcForSurfaceInstr(unsigned Intrinsic) {
2968 switch (Intrinsic) {
2969 default:
2970 return 0;
2971 case Intrinsic::nvvm_suld_1d_i8_clamp:
2972 return NVPTXISD::Suld1DI8Clamp;
2973 case Intrinsic::nvvm_suld_1d_i16_clamp:
2974 return NVPTXISD::Suld1DI16Clamp;
2975 case Intrinsic::nvvm_suld_1d_i32_clamp:
2976 return NVPTXISD::Suld1DI32Clamp;
2977 case Intrinsic::nvvm_suld_1d_i64_clamp:
2978 return NVPTXISD::Suld1DI64Clamp;
2979 case Intrinsic::nvvm_suld_1d_v2i8_clamp:
2980 return NVPTXISD::Suld1DV2I8Clamp;
2981 case Intrinsic::nvvm_suld_1d_v2i16_clamp:
2982 return NVPTXISD::Suld1DV2I16Clamp;
2983 case Intrinsic::nvvm_suld_1d_v2i32_clamp:
2984 return NVPTXISD::Suld1DV2I32Clamp;
2985 case Intrinsic::nvvm_suld_1d_v2i64_clamp:
2986 return NVPTXISD::Suld1DV2I64Clamp;
2987 case Intrinsic::nvvm_suld_1d_v4i8_clamp:
2988 return NVPTXISD::Suld1DV4I8Clamp;
2989 case Intrinsic::nvvm_suld_1d_v4i16_clamp:
2990 return NVPTXISD::Suld1DV4I16Clamp;
2991 case Intrinsic::nvvm_suld_1d_v4i32_clamp:
2992 return NVPTXISD::Suld1DV4I32Clamp;
2993 case Intrinsic::nvvm_suld_1d_array_i8_clamp:
2994 return NVPTXISD::Suld1DArrayI8Clamp;
2995 case Intrinsic::nvvm_suld_1d_array_i16_clamp:
2996 return NVPTXISD::Suld1DArrayI16Clamp;
2997 case Intrinsic::nvvm_suld_1d_array_i32_clamp:
2998 return NVPTXISD::Suld1DArrayI32Clamp;
2999 case Intrinsic::nvvm_suld_1d_array_i64_clamp:
3000 return NVPTXISD::Suld1DArrayI64Clamp;
3001 case Intrinsic::nvvm_suld_1d_array_v2i8_clamp:
3002 return NVPTXISD::Suld1DArrayV2I8Clamp;
3003 case Intrinsic::nvvm_suld_1d_array_v2i16_clamp:
3004 return NVPTXISD::Suld1DArrayV2I16Clamp;
3005 case Intrinsic::nvvm_suld_1d_array_v2i32_clamp:
3006 return NVPTXISD::Suld1DArrayV2I32Clamp;
3007 case Intrinsic::nvvm_suld_1d_array_v2i64_clamp:
3008 return NVPTXISD::Suld1DArrayV2I64Clamp;
3009 case Intrinsic::nvvm_suld_1d_array_v4i8_clamp:
3010 return NVPTXISD::Suld1DArrayV4I8Clamp;
3011 case Intrinsic::nvvm_suld_1d_array_v4i16_clamp:
3012 return NVPTXISD::Suld1DArrayV4I16Clamp;
3013 case Intrinsic::nvvm_suld_1d_array_v4i32_clamp:
3014 return NVPTXISD::Suld1DArrayV4I32Clamp;
3015 case Intrinsic::nvvm_suld_2d_i8_clamp:
3016 return NVPTXISD::Suld2DI8Clamp;
3017 case Intrinsic::nvvm_suld_2d_i16_clamp:
3018 return NVPTXISD::Suld2DI16Clamp;
3019 case Intrinsic::nvvm_suld_2d_i32_clamp:
3020 return NVPTXISD::Suld2DI32Clamp;
3021 case Intrinsic::nvvm_suld_2d_i64_clamp:
3022 return NVPTXISD::Suld2DI64Clamp;
3023 case Intrinsic::nvvm_suld_2d_v2i8_clamp:
3024 return NVPTXISD::Suld2DV2I8Clamp;
3025 case Intrinsic::nvvm_suld_2d_v2i16_clamp:
3026 return NVPTXISD::Suld2DV2I16Clamp;
3027 case Intrinsic::nvvm_suld_2d_v2i32_clamp:
3028 return NVPTXISD::Suld2DV2I32Clamp;
3029 case Intrinsic::nvvm_suld_2d_v2i64_clamp:
3030 return NVPTXISD::Suld2DV2I64Clamp;
3031 case Intrinsic::nvvm_suld_2d_v4i8_clamp:
3032 return NVPTXISD::Suld2DV4I8Clamp;
3033 case Intrinsic::nvvm_suld_2d_v4i16_clamp:
3034 return NVPTXISD::Suld2DV4I16Clamp;
3035 case Intrinsic::nvvm_suld_2d_v4i32_clamp:
3036 return NVPTXISD::Suld2DV4I32Clamp;
3037 case Intrinsic::nvvm_suld_2d_array_i8_clamp:
3038 return NVPTXISD::Suld2DArrayI8Clamp;
3039 case Intrinsic::nvvm_suld_2d_array_i16_clamp:
3040 return NVPTXISD::Suld2DArrayI16Clamp;
3041 case Intrinsic::nvvm_suld_2d_array_i32_clamp:
3042 return NVPTXISD::Suld2DArrayI32Clamp;
3043 case Intrinsic::nvvm_suld_2d_array_i64_clamp:
3044 return NVPTXISD::Suld2DArrayI64Clamp;
3045 case Intrinsic::nvvm_suld_2d_array_v2i8_clamp:
3046 return NVPTXISD::Suld2DArrayV2I8Clamp;
3047 case Intrinsic::nvvm_suld_2d_array_v2i16_clamp:
3048 return NVPTXISD::Suld2DArrayV2I16Clamp;
3049 case Intrinsic::nvvm_suld_2d_array_v2i32_clamp:
3050 return NVPTXISD::Suld2DArrayV2I32Clamp;
3051 case Intrinsic::nvvm_suld_2d_array_v2i64_clamp:
3052 return NVPTXISD::Suld2DArrayV2I64Clamp;
3053 case Intrinsic::nvvm_suld_2d_array_v4i8_clamp:
3054 return NVPTXISD::Suld2DArrayV4I8Clamp;
3055 case Intrinsic::nvvm_suld_2d_array_v4i16_clamp:
3056 return NVPTXISD::Suld2DArrayV4I16Clamp;
3057 case Intrinsic::nvvm_suld_2d_array_v4i32_clamp:
3058 return NVPTXISD::Suld2DArrayV4I32Clamp;
3059 case Intrinsic::nvvm_suld_3d_i8_clamp:
3060 return NVPTXISD::Suld3DI8Clamp;
3061 case Intrinsic::nvvm_suld_3d_i16_clamp:
3062 return NVPTXISD::Suld3DI16Clamp;
3063 case Intrinsic::nvvm_suld_3d_i32_clamp:
3064 return NVPTXISD::Suld3DI32Clamp;
3065 case Intrinsic::nvvm_suld_3d_i64_clamp:
3066 return NVPTXISD::Suld3DI64Clamp;
3067 case Intrinsic::nvvm_suld_3d_v2i8_clamp:
3068 return NVPTXISD::Suld3DV2I8Clamp;
3069 case Intrinsic::nvvm_suld_3d_v2i16_clamp:
3070 return NVPTXISD::Suld3DV2I16Clamp;
3071 case Intrinsic::nvvm_suld_3d_v2i32_clamp:
3072 return NVPTXISD::Suld3DV2I32Clamp;
3073 case Intrinsic::nvvm_suld_3d_v2i64_clamp:
3074 return NVPTXISD::Suld3DV2I64Clamp;
3075 case Intrinsic::nvvm_suld_3d_v4i8_clamp:
3076 return NVPTXISD::Suld3DV4I8Clamp;
3077 case Intrinsic::nvvm_suld_3d_v4i16_clamp:
3078 return NVPTXISD::Suld3DV4I16Clamp;
3079 case Intrinsic::nvvm_suld_3d_v4i32_clamp:
3080 return NVPTXISD::Suld3DV4I32Clamp;
3081 case Intrinsic::nvvm_suld_1d_i8_trap:
3082 return NVPTXISD::Suld1DI8Trap;
3083 case Intrinsic::nvvm_suld_1d_i16_trap:
3084 return NVPTXISD::Suld1DI16Trap;
3085 case Intrinsic::nvvm_suld_1d_i32_trap:
3086 return NVPTXISD::Suld1DI32Trap;
3087 case Intrinsic::nvvm_suld_1d_i64_trap:
3088 return NVPTXISD::Suld1DI64Trap;
3089 case Intrinsic::nvvm_suld_1d_v2i8_trap:
3090 return NVPTXISD::Suld1DV2I8Trap;
3091 case Intrinsic::nvvm_suld_1d_v2i16_trap:
3092 return NVPTXISD::Suld1DV2I16Trap;
3093 case Intrinsic::nvvm_suld_1d_v2i32_trap:
3094 return NVPTXISD::Suld1DV2I32Trap;
3095 case Intrinsic::nvvm_suld_1d_v2i64_trap:
3096 return NVPTXISD::Suld1DV2I64Trap;
3097 case Intrinsic::nvvm_suld_1d_v4i8_trap:
3098 return NVPTXISD::Suld1DV4I8Trap;
3099 case Intrinsic::nvvm_suld_1d_v4i16_trap:
3100 return NVPTXISD::Suld1DV4I16Trap;
3101 case Intrinsic::nvvm_suld_1d_v4i32_trap:
3102 return NVPTXISD::Suld1DV4I32Trap;
3103 case Intrinsic::nvvm_suld_1d_array_i8_trap:
3104 return NVPTXISD::Suld1DArrayI8Trap;
3105 case Intrinsic::nvvm_suld_1d_array_i16_trap:
3106 return NVPTXISD::Suld1DArrayI16Trap;
3107 case Intrinsic::nvvm_suld_1d_array_i32_trap:
3108 return NVPTXISD::Suld1DArrayI32Trap;
3109 case Intrinsic::nvvm_suld_1d_array_i64_trap:
3110 return NVPTXISD::Suld1DArrayI64Trap;
3111 case Intrinsic::nvvm_suld_1d_array_v2i8_trap:
3112 return NVPTXISD::Suld1DArrayV2I8Trap;
3113 case Intrinsic::nvvm_suld_1d_array_v2i16_trap:
3114 return NVPTXISD::Suld1DArrayV2I16Trap;
3115 case Intrinsic::nvvm_suld_1d_array_v2i32_trap:
3116 return NVPTXISD::Suld1DArrayV2I32Trap;
3117 case Intrinsic::nvvm_suld_1d_array_v2i64_trap:
3118 return NVPTXISD::Suld1DArrayV2I64Trap;
3119 case Intrinsic::nvvm_suld_1d_array_v4i8_trap:
3120 return NVPTXISD::Suld1DArrayV4I8Trap;
3121 case Intrinsic::nvvm_suld_1d_array_v4i16_trap:
3122 return NVPTXISD::Suld1DArrayV4I16Trap;
3123 case Intrinsic::nvvm_suld_1d_array_v4i32_trap:
3124 return NVPTXISD::Suld1DArrayV4I32Trap;
3125 case Intrinsic::nvvm_suld_2d_i8_trap:
3126 return NVPTXISD::Suld2DI8Trap;
3127 case Intrinsic::nvvm_suld_2d_i16_trap:
3128 return NVPTXISD::Suld2DI16Trap;
3129 case Intrinsic::nvvm_suld_2d_i32_trap:
3130 return NVPTXISD::Suld2DI32Trap;
3131 case Intrinsic::nvvm_suld_2d_i64_trap:
3132 return NVPTXISD::Suld2DI64Trap;
3133 case Intrinsic::nvvm_suld_2d_v2i8_trap:
3134 return NVPTXISD::Suld2DV2I8Trap;
3135 case Intrinsic::nvvm_suld_2d_v2i16_trap:
3136 return NVPTXISD::Suld2DV2I16Trap;
3137 case Intrinsic::nvvm_suld_2d_v2i32_trap:
3138 return NVPTXISD::Suld2DV2I32Trap;
3139 case Intrinsic::nvvm_suld_2d_v2i64_trap:
3140 return NVPTXISD::Suld2DV2I64Trap;
3141 case Intrinsic::nvvm_suld_2d_v4i8_trap:
3142 return NVPTXISD::Suld2DV4I8Trap;
3143 case Intrinsic::nvvm_suld_2d_v4i16_trap:
3144 return NVPTXISD::Suld2DV4I16Trap;
3145 case Intrinsic::nvvm_suld_2d_v4i32_trap:
3146 return NVPTXISD::Suld2DV4I32Trap;
3147 case Intrinsic::nvvm_suld_2d_array_i8_trap:
3148 return NVPTXISD::Suld2DArrayI8Trap;
3149 case Intrinsic::nvvm_suld_2d_array_i16_trap:
3150 return NVPTXISD::Suld2DArrayI16Trap;
3151 case Intrinsic::nvvm_suld_2d_array_i32_trap:
3152 return NVPTXISD::Suld2DArrayI32Trap;
3153 case Intrinsic::nvvm_suld_2d_array_i64_trap:
3154 return NVPTXISD::Suld2DArrayI64Trap;
3155 case Intrinsic::nvvm_suld_2d_array_v2i8_trap:
3156 return NVPTXISD::Suld2DArrayV2I8Trap;
3157 case Intrinsic::nvvm_suld_2d_array_v2i16_trap:
3158 return NVPTXISD::Suld2DArrayV2I16Trap;
3159 case Intrinsic::nvvm_suld_2d_array_v2i32_trap:
3160 return NVPTXISD::Suld2DArrayV2I32Trap;
3161 case Intrinsic::nvvm_suld_2d_array_v2i64_trap:
3162 return NVPTXISD::Suld2DArrayV2I64Trap;
3163 case Intrinsic::nvvm_suld_2d_array_v4i8_trap:
3164 return NVPTXISD::Suld2DArrayV4I8Trap;
3165 case Intrinsic::nvvm_suld_2d_array_v4i16_trap:
3166 return NVPTXISD::Suld2DArrayV4I16Trap;
3167 case Intrinsic::nvvm_suld_2d_array_v4i32_trap:
3168 return NVPTXISD::Suld2DArrayV4I32Trap;
3169 case Intrinsic::nvvm_suld_3d_i8_trap:
3170 return NVPTXISD::Suld3DI8Trap;
3171 case Intrinsic::nvvm_suld_3d_i16_trap:
3172 return NVPTXISD::Suld3DI16Trap;
3173 case Intrinsic::nvvm_suld_3d_i32_trap:
3174 return NVPTXISD::Suld3DI32Trap;
3175 case Intrinsic::nvvm_suld_3d_i64_trap:
3176 return NVPTXISD::Suld3DI64Trap;
3177 case Intrinsic::nvvm_suld_3d_v2i8_trap:
3178 return NVPTXISD::Suld3DV2I8Trap;
3179 case Intrinsic::nvvm_suld_3d_v2i16_trap:
3180 return NVPTXISD::Suld3DV2I16Trap;
3181 case Intrinsic::nvvm_suld_3d_v2i32_trap:
3182 return NVPTXISD::Suld3DV2I32Trap;
3183 case Intrinsic::nvvm_suld_3d_v2i64_trap:
3184 return NVPTXISD::Suld3DV2I64Trap;
3185 case Intrinsic::nvvm_suld_3d_v4i8_trap:
3186 return NVPTXISD::Suld3DV4I8Trap;
3187 case Intrinsic::nvvm_suld_3d_v4i16_trap:
3188 return NVPTXISD::Suld3DV4I16Trap;
3189 case Intrinsic::nvvm_suld_3d_v4i32_trap:
3190 return NVPTXISD::Suld3DV4I32Trap;
3191 case Intrinsic::nvvm_suld_1d_i8_zero:
3192 return NVPTXISD::Suld1DI8Zero;
3193 case Intrinsic::nvvm_suld_1d_i16_zero:
3194 return NVPTXISD::Suld1DI16Zero;
3195 case Intrinsic::nvvm_suld_1d_i32_zero:
3196 return NVPTXISD::Suld1DI32Zero;
3197 case Intrinsic::nvvm_suld_1d_i64_zero:
3198 return NVPTXISD::Suld1DI64Zero;
3199 case Intrinsic::nvvm_suld_1d_v2i8_zero:
3200 return NVPTXISD::Suld1DV2I8Zero;
3201 case Intrinsic::nvvm_suld_1d_v2i16_zero:
3202 return NVPTXISD::Suld1DV2I16Zero;
3203 case Intrinsic::nvvm_suld_1d_v2i32_zero:
3204 return NVPTXISD::Suld1DV2I32Zero;
3205 case Intrinsic::nvvm_suld_1d_v2i64_zero:
3206 return NVPTXISD::Suld1DV2I64Zero;
3207 case Intrinsic::nvvm_suld_1d_v4i8_zero:
3208 return NVPTXISD::Suld1DV4I8Zero;
3209 case Intrinsic::nvvm_suld_1d_v4i16_zero:
3210 return NVPTXISD::Suld1DV4I16Zero;
3211 case Intrinsic::nvvm_suld_1d_v4i32_zero:
3212 return NVPTXISD::Suld1DV4I32Zero;
3213 case Intrinsic::nvvm_suld_1d_array_i8_zero:
3214 return NVPTXISD::Suld1DArrayI8Zero;
3215 case Intrinsic::nvvm_suld_1d_array_i16_zero:
3216 return NVPTXISD::Suld1DArrayI16Zero;
3217 case Intrinsic::nvvm_suld_1d_array_i32_zero:
3218 return NVPTXISD::Suld1DArrayI32Zero;
3219 case Intrinsic::nvvm_suld_1d_array_i64_zero:
3220 return NVPTXISD::Suld1DArrayI64Zero;
3221 case Intrinsic::nvvm_suld_1d_array_v2i8_zero:
3222 return NVPTXISD::Suld1DArrayV2I8Zero;
3223 case Intrinsic::nvvm_suld_1d_array_v2i16_zero:
3224 return NVPTXISD::Suld1DArrayV2I16Zero;
3225 case Intrinsic::nvvm_suld_1d_array_v2i32_zero:
3226 return NVPTXISD::Suld1DArrayV2I32Zero;
3227 case Intrinsic::nvvm_suld_1d_array_v2i64_zero:
3228 return NVPTXISD::Suld1DArrayV2I64Zero;
3229 case Intrinsic::nvvm_suld_1d_array_v4i8_zero:
3230 return NVPTXISD::Suld1DArrayV4I8Zero;
3231 case Intrinsic::nvvm_suld_1d_array_v4i16_zero:
3232 return NVPTXISD::Suld1DArrayV4I16Zero;
3233 case Intrinsic::nvvm_suld_1d_array_v4i32_zero:
3234 return NVPTXISD::Suld1DArrayV4I32Zero;
3235 case Intrinsic::nvvm_suld_2d_i8_zero:
3236 return NVPTXISD::Suld2DI8Zero;
3237 case Intrinsic::nvvm_suld_2d_i16_zero:
3238 return NVPTXISD::Suld2DI16Zero;
3239 case Intrinsic::nvvm_suld_2d_i32_zero:
3240 return NVPTXISD::Suld2DI32Zero;
3241 case Intrinsic::nvvm_suld_2d_i64_zero:
3242 return NVPTXISD::Suld2DI64Zero;
3243 case Intrinsic::nvvm_suld_2d_v2i8_zero:
3244 return NVPTXISD::Suld2DV2I8Zero;
3245 case Intrinsic::nvvm_suld_2d_v2i16_zero:
3246 return NVPTXISD::Suld2DV2I16Zero;
3247 case Intrinsic::nvvm_suld_2d_v2i32_zero:
3248 return NVPTXISD::Suld2DV2I32Zero;
3249 case Intrinsic::nvvm_suld_2d_v2i64_zero:
3250 return NVPTXISD::Suld2DV2I64Zero;
3251 case Intrinsic::nvvm_suld_2d_v4i8_zero:
3252 return NVPTXISD::Suld2DV4I8Zero;
3253 case Intrinsic::nvvm_suld_2d_v4i16_zero:
3254 return NVPTXISD::Suld2DV4I16Zero;
3255 case Intrinsic::nvvm_suld_2d_v4i32_zero:
3256 return NVPTXISD::Suld2DV4I32Zero;
3257 case Intrinsic::nvvm_suld_2d_array_i8_zero:
3258 return NVPTXISD::Suld2DArrayI8Zero;
3259 case Intrinsic::nvvm_suld_2d_array_i16_zero:
3260 return NVPTXISD::Suld2DArrayI16Zero;
3261 case Intrinsic::nvvm_suld_2d_array_i32_zero:
3262 return NVPTXISD::Suld2DArrayI32Zero;
3263 case Intrinsic::nvvm_suld_2d_array_i64_zero:
3264 return NVPTXISD::Suld2DArrayI64Zero;
3265 case Intrinsic::nvvm_suld_2d_array_v2i8_zero:
3266 return NVPTXISD::Suld2DArrayV2I8Zero;
3267 case Intrinsic::nvvm_suld_2d_array_v2i16_zero:
3268 return NVPTXISD::Suld2DArrayV2I16Zero;
3269 case Intrinsic::nvvm_suld_2d_array_v2i32_zero:
3270 return NVPTXISD::Suld2DArrayV2I32Zero;
3271 case Intrinsic::nvvm_suld_2d_array_v2i64_zero:
3272 return NVPTXISD::Suld2DArrayV2I64Zero;
3273 case Intrinsic::nvvm_suld_2d_array_v4i8_zero:
3274 return NVPTXISD::Suld2DArrayV4I8Zero;
3275 case Intrinsic::nvvm_suld_2d_array_v4i16_zero:
3276 return NVPTXISD::Suld2DArrayV4I16Zero;
3277 case Intrinsic::nvvm_suld_2d_array_v4i32_zero:
3278 return NVPTXISD::Suld2DArrayV4I32Zero;
3279 case Intrinsic::nvvm_suld_3d_i8_zero:
3280 return NVPTXISD::Suld3DI8Zero;
3281 case Intrinsic::nvvm_suld_3d_i16_zero:
3282 return NVPTXISD::Suld3DI16Zero;
3283 case Intrinsic::nvvm_suld_3d_i32_zero:
3284 return NVPTXISD::Suld3DI32Zero;
3285 case Intrinsic::nvvm_suld_3d_i64_zero:
3286 return NVPTXISD::Suld3DI64Zero;
3287 case Intrinsic::nvvm_suld_3d_v2i8_zero:
3288 return NVPTXISD::Suld3DV2I8Zero;
3289 case Intrinsic::nvvm_suld_3d_v2i16_zero:
3290 return NVPTXISD::Suld3DV2I16Zero;
3291 case Intrinsic::nvvm_suld_3d_v2i32_zero:
3292 return NVPTXISD::Suld3DV2I32Zero;
3293 case Intrinsic::nvvm_suld_3d_v2i64_zero:
3294 return NVPTXISD::Suld3DV2I64Zero;
3295 case Intrinsic::nvvm_suld_3d_v4i8_zero:
3296 return NVPTXISD::Suld3DV4I8Zero;
3297 case Intrinsic::nvvm_suld_3d_v4i16_zero:
3298 return NVPTXISD::Suld3DV4I16Zero;
3299 case Intrinsic::nvvm_suld_3d_v4i32_zero:
3300 return NVPTXISD::Suld3DV4I32Zero;
3301 }
3302}
3303
3304// llvm.ptx.memcpy.const and llvm.ptx.memmove.const need to be modeled as
3305// TgtMemIntrinsic
3306// because we need the information that is only available in the "Value" type
3307// of destination
3308// pointer. In particular, the address space information.
3309bool NVPTXTargetLowering::getTgtMemIntrinsic(
3310 IntrinsicInfo &Info, const CallInst &I,
3311 MachineFunction &MF, unsigned Intrinsic) const {
3312 switch (Intrinsic) {
3313 default:
3314 return false;
3315 case Intrinsic::nvvm_match_all_sync_i32p:
3316 case Intrinsic::nvvm_match_all_sync_i64p:
3317 Info.opc = ISD::INTRINSIC_W_CHAIN;
3318 // memVT is bogus. These intrinsics have IntrInaccessibleMemOnly attribute
3319 // in order to model data exchange with other threads, but perform no real
3320 // memory accesses.
3321 Info.memVT = MVT::i1;
3322
3323 // Our result depends on both our and other thread's arguments.
3324 Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore;
3325 return true;
3326 case Intrinsic::nvvm_wmma_m16n16k16_load_a_f16_col:
3327 case Intrinsic::nvvm_wmma_m16n16k16_load_a_f16_row:
3328 case Intrinsic::nvvm_wmma_m16n16k16_load_a_f16_col_stride:
3329 case Intrinsic::nvvm_wmma_m16n16k16_load_a_f16_row_stride:
3330 case Intrinsic::nvvm_wmma_m16n16k16_load_b_f16_col:
3331 case Intrinsic::nvvm_wmma_m16n16k16_load_b_f16_row:
3332 case Intrinsic::nvvm_wmma_m16n16k16_load_b_f16_col_stride:
3333 case Intrinsic::nvvm_wmma_m16n16k16_load_b_f16_row_stride: {
3334 Info.opc = ISD::INTRINSIC_W_CHAIN;
3335 Info.memVT = MVT::v8f16;
3336 Info.ptrVal = I.getArgOperand(0);
3337 Info.offset = 0;
3338 Info.flags = MachineMemOperand::MOLoad;
3339 Info.align = 16;
3340 return true;
3341 }
3342
3343 case Intrinsic::nvvm_wmma_m16n16k16_load_c_f16_col:
3344 case Intrinsic::nvvm_wmma_m16n16k16_load_c_f16_row:
3345 case Intrinsic::nvvm_wmma_m16n16k16_load_c_f16_col_stride:
3346 case Intrinsic::nvvm_wmma_m16n16k16_load_c_f16_row_stride: {
3347 Info.opc = ISD::INTRINSIC_W_CHAIN;
3348 Info.memVT = MVT::v4f16;
3349 Info.ptrVal = I.getArgOperand(0);
3350 Info.offset = 0;
3351 Info.flags = MachineMemOperand::MOLoad;
3352 Info.align = 16;
3353 return true;
3354 }
3355
3356 case Intrinsic::nvvm_wmma_m16n16k16_load_c_f32_col:
3357 case Intrinsic::nvvm_wmma_m16n16k16_load_c_f32_row:
3358 case Intrinsic::nvvm_wmma_m16n16k16_load_c_f32_col_stride:
3359 case Intrinsic::nvvm_wmma_m16n16k16_load_c_f32_row_stride: {
3360 Info.opc = ISD::INTRINSIC_W_CHAIN;
3361 Info.memVT = MVT::v8f32;
3362 Info.ptrVal = I.getArgOperand(0);
3363 Info.offset = 0;
3364 Info.flags = MachineMemOperand::MOLoad;
3365 Info.align = 16;
3366 return true;
3367 }
3368
3369 case Intrinsic::nvvm_wmma_m16n16k16_store_d_f16_col:
3370 case Intrinsic::nvvm_wmma_m16n16k16_store_d_f16_row:
3371 case Intrinsic::nvvm_wmma_m16n16k16_store_d_f16_col_stride:
3372 case Intrinsic::nvvm_wmma_m16n16k16_store_d_f16_row_stride: {
3373 Info.opc = ISD::INTRINSIC_VOID;
3374 Info.memVT = MVT::v4f16;
3375 Info.ptrVal = I.getArgOperand(0);
3376 Info.offset = 0;
3377 Info.flags = MachineMemOperand::MOStore;
3378 Info.align = 16;
3379 return true;
3380 }
3381
3382 case Intrinsic::nvvm_wmma_m16n16k16_store_d_f32_col:
3383 case Intrinsic::nvvm_wmma_m16n16k16_store_d_f32_row:
3384 case Intrinsic::nvvm_wmma_m16n16k16_store_d_f32_col_stride:
3385 case Intrinsic::nvvm_wmma_m16n16k16_store_d_f32_row_stride: {
3386 Info.opc = ISD::INTRINSIC_VOID;
3387 Info.memVT = MVT::v8f32;
3388 Info.ptrVal = I.getArgOperand(0);
3389 Info.offset = 0;
3390 Info.flags = MachineMemOperand::MOStore;
3391 Info.align = 16;
3392 return true;
3393 }
3394
3395 case Intrinsic::nvvm_atomic_load_add_f32:
3396 case Intrinsic::nvvm_atomic_load_add_f64:
3397 case Intrinsic::nvvm_atomic_load_inc_32:
3398 case Intrinsic::nvvm_atomic_load_dec_32:
3399
3400 case Intrinsic::nvvm_atomic_add_gen_f_cta:
3401 case Intrinsic::nvvm_atomic_add_gen_f_sys:
3402 case Intrinsic::nvvm_atomic_add_gen_i_cta:
3403 case Intrinsic::nvvm_atomic_add_gen_i_sys:
3404 case Intrinsic::nvvm_atomic_and_gen_i_cta:
3405 case Intrinsic::nvvm_atomic_and_gen_i_sys:
3406 case Intrinsic::nvvm_atomic_cas_gen_i_cta:
3407 case Intrinsic::nvvm_atomic_cas_gen_i_sys:
3408 case Intrinsic::nvvm_atomic_dec_gen_i_cta:
3409 case Intrinsic::nvvm_atomic_dec_gen_i_sys:
3410 case Intrinsic::nvvm_atomic_inc_gen_i_cta:
3411 case Intrinsic::nvvm_atomic_inc_gen_i_sys:
3412 case Intrinsic::nvvm_atomic_max_gen_i_cta:
3413 case Intrinsic::nvvm_atomic_max_gen_i_sys:
3414 case Intrinsic::nvvm_atomic_min_gen_i_cta:
3415 case Intrinsic::nvvm_atomic_min_gen_i_sys:
3416 case Intrinsic::nvvm_atomic_or_gen_i_cta:
3417 case Intrinsic::nvvm_atomic_or_gen_i_sys:
3418 case Intrinsic::nvvm_atomic_exch_gen_i_cta:
3419 case Intrinsic::nvvm_atomic_exch_gen_i_sys:
3420 case Intrinsic::nvvm_atomic_xor_gen_i_cta:
3421 case Intrinsic::nvvm_atomic_xor_gen_i_sys: {
3422 auto &DL = I.getModule()->getDataLayout();
3423 Info.opc = ISD::INTRINSIC_W_CHAIN;
3424 Info.memVT = getValueType(DL, I.getType());
3425 Info.ptrVal = I.getArgOperand(0);
3426 Info.offset = 0;
3427 Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore;
3428 Info.align = 0;
3429 return true;
3430 }
3431
3432 case Intrinsic::nvvm_ldu_global_i:
3433 case Intrinsic::nvvm_ldu_global_f:
3434 case Intrinsic::nvvm_ldu_global_p: {
3435 auto &DL = I.getModule()->getDataLayout();
3436 Info.opc = ISD::INTRINSIC_W_CHAIN;
3437 if (Intrinsic == Intrinsic::nvvm_ldu_global_i)
3438 Info.memVT = getValueType(DL, I.getType());
3439 else if(Intrinsic == Intrinsic::nvvm_ldu_global_p)
3440 Info.memVT = getPointerTy(DL);
3441 else
3442 Info.memVT = getValueType(DL, I.getType());
3443 Info.ptrVal = I.getArgOperand(0);
3444 Info.offset = 0;
3445 Info.flags = MachineMemOperand::MOLoad;
3446 Info.align = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
3447
3448 return true;
3449 }
3450 case Intrinsic::nvvm_ldg_global_i:
3451 case Intrinsic::nvvm_ldg_global_f:
3452 case Intrinsic::nvvm_ldg_global_p: {
3453 auto &DL = I.getModule()->getDataLayout();
3454
3455 Info.opc = ISD::INTRINSIC_W_CHAIN;
3456 if (Intrinsic == Intrinsic::nvvm_ldg_global_i)
3457 Info.memVT = getValueType(DL, I.getType());
3458 else if(Intrinsic == Intrinsic::nvvm_ldg_global_p)
3459 Info.memVT = getPointerTy(DL);
3460 else
3461 Info.memVT = getValueType(DL, I.getType());
3462 Info.ptrVal = I.getArgOperand(0);
3463 Info.offset = 0;
3464 Info.flags = MachineMemOperand::MOLoad;
3465 Info.align = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
3466
3467 return true;
3468 }
3469
3470 case Intrinsic::nvvm_tex_1d_v4f32_s32:
3471 case Intrinsic::nvvm_tex_1d_v4f32_f32:
3472 case Intrinsic::nvvm_tex_1d_level_v4f32_f32:
3473 case Intrinsic::nvvm_tex_1d_grad_v4f32_f32:
3474 case Intrinsic::nvvm_tex_1d_array_v4f32_s32:
3475 case Intrinsic::nvvm_tex_1d_array_v4f32_f32:
3476 case Intrinsic::nvvm_tex_1d_array_level_v4f32_f32:
3477 case Intrinsic::nvvm_tex_1d_array_grad_v4f32_f32:
3478 case Intrinsic::nvvm_tex_2d_v4f32_s32:
3479 case Intrinsic::nvvm_tex_2d_v4f32_f32:
3480 case Intrinsic::nvvm_tex_2d_level_v4f32_f32:
3481 case Intrinsic::nvvm_tex_2d_grad_v4f32_f32:
3482 case Intrinsic::nvvm_tex_2d_array_v4f32_s32:
3483 case Intrinsic::nvvm_tex_2d_array_v4f32_f32:
3484 case Intrinsic::nvvm_tex_2d_array_level_v4f32_f32:
3485 case Intrinsic::nvvm_tex_2d_array_grad_v4f32_f32:
3486 case Intrinsic::nvvm_tex_3d_v4f32_s32:
3487 case Intrinsic::nvvm_tex_3d_v4f32_f32:
3488 case Intrinsic::nvvm_tex_3d_level_v4f32_f32:
3489 case Intrinsic::nvvm_tex_3d_grad_v4f32_f32:
3490 case Intrinsic::nvvm_tex_cube_v4f32_f32:
3491 case Intrinsic::nvvm_tex_cube_level_v4f32_f32:
3492 case Intrinsic::nvvm_tex_cube_array_v4f32_f32:
3493 case Intrinsic::nvvm_tex_cube_array_level_v4f32_f32:
3494 case Intrinsic::nvvm_tld4_r_2d_v4f32_f32:
3495 case Intrinsic::nvvm_tld4_g_2d_v4f32_f32:
3496 case Intrinsic::nvvm_tld4_b_2d_v4f32_f32:
3497 case Intrinsic::nvvm_tld4_a_2d_v4f32_f32:
3498 case Intrinsic::nvvm_tex_unified_1d_v4f32_s32:
3499 case Intrinsic::nvvm_tex_unified_1d_v4f32_f32:
3500 case Intrinsic::nvvm_tex_unified_1d_level_v4f32_f32:
3501 case Intrinsic::nvvm_tex_unified_1d_grad_v4f32_f32:
3502 case Intrinsic::nvvm_tex_unified_1d_array_v4f32_s32:
3503 case Intrinsic::nvvm_tex_unified_1d_array_v4f32_f32:
3504 case Intrinsic::nvvm_tex_unified_1d_array_level_v4f32_f32:
3505 case Intrinsic::nvvm_tex_unified_1d_array_grad_v4f32_f32:
3506 case Intrinsic::nvvm_tex_unified_2d_v4f32_s32:
3507 case Intrinsic::nvvm_tex_unified_2d_v4f32_f32:
3508 case Intrinsic::nvvm_tex_unified_2d_level_v4f32_f32:
3509 case Intrinsic::nvvm_tex_unified_2d_grad_v4f32_f32:
3510 case Intrinsic::nvvm_tex_unified_2d_array_v4f32_s32:
3511 case Intrinsic::nvvm_tex_unified_2d_array_v4f32_f32:
3512 case Intrinsic::nvvm_tex_unified_2d_array_level_v4f32_f32:
3513 case Intrinsic::nvvm_tex_unified_2d_array_grad_v4f32_f32:
3514 case Intrinsic::nvvm_tex_unified_3d_v4f32_s32:
3515 case Intrinsic::nvvm_tex_unified_3d_v4f32_f32:
3516 case Intrinsic::nvvm_tex_unified_3d_level_v4f32_f32:
3517 case Intrinsic::nvvm_tex_unified_3d_grad_v4f32_f32:
3518 case Intrinsic::nvvm_tex_unified_cube_v4f32_f32:
3519 case Intrinsic::nvvm_tex_unified_cube_level_v4f32_f32:
3520 case Intrinsic::nvvm_tex_unified_cube_array_v4f32_f32:
3521 case Intrinsic::nvvm_tex_unified_cube_array_level_v4f32_f32:
3522 case Intrinsic::nvvm_tld4_unified_r_2d_v4f32_f32:
3523 case Intrinsic::nvvm_tld4_unified_g_2d_v4f32_f32:
3524 case Intrinsic::nvvm_tld4_unified_b_2d_v4f32_f32:
3525 case Intrinsic::nvvm_tld4_unified_a_2d_v4f32_f32:
3526 Info.opc = getOpcForTextureInstr(Intrinsic);
3527 Info.memVT = MVT::v4f32;
3528 Info.ptrVal = nullptr;
3529 Info.offset = 0;
3530 Info.flags = MachineMemOperand::MOLoad;
3531 Info.align = 16;
3532 return true;
3533
3534 case Intrinsic::nvvm_tex_1d_v4s32_s32:
3535 case Intrinsic::nvvm_tex_1d_v4s32_f32:
3536 case Intrinsic::nvvm_tex_1d_level_v4s32_f32:
3537 case Intrinsic::nvvm_tex_1d_grad_v4s32_f32:
3538 case Intrinsic::nvvm_tex_1d_array_v4s32_s32:
3539 case Intrinsic::nvvm_tex_1d_array_v4s32_f32:
3540 case Intrinsic::nvvm_tex_1d_array_level_v4s32_f32:
3541 case Intrinsic::nvvm_tex_1d_array_grad_v4s32_f32:
3542 case Intrinsic::nvvm_tex_2d_v4s32_s32:
3543 case Intrinsic::nvvm_tex_2d_v4s32_f32:
3544 case Intrinsic::nvvm_tex_2d_level_v4s32_f32:
3545 case Intrinsic::nvvm_tex_2d_grad_v4s32_f32:
3546 case Intrinsic::nvvm_tex_2d_array_v4s32_s32:
3547 case Intrinsic::nvvm_tex_2d_array_v4s32_f32:
3548 case Intrinsic::nvvm_tex_2d_array_level_v4s32_f32:
3549 case Intrinsic::nvvm_tex_2d_array_grad_v4s32_f32:
3550 case Intrinsic::nvvm_tex_3d_v4s32_s32:
3551 case Intrinsic::nvvm_tex_3d_v4s32_f32:
3552 case Intrinsic::nvvm_tex_3d_level_v4s32_f32:
3553 case Intrinsic::nvvm_tex_3d_grad_v4s32_f32:
3554 case Intrinsic::nvvm_tex_cube_v4s32_f32:
3555 case Intrinsic::nvvm_tex_cube_level_v4s32_f32:
3556 case Intrinsic::nvvm_tex_cube_array_v4s32_f32:
3557 case Intrinsic::nvvm_tex_cube_array_level_v4s32_f32:
3558 case Intrinsic::nvvm_tex_cube_v4u32_f32:
3559 case Intrinsic::nvvm_tex_cube_level_v4u32_f32:
3560 case Intrinsic::nvvm_tex_cube_array_v4u32_f32:
3561 case Intrinsic::nvvm_tex_cube_array_level_v4u32_f32:
3562 case Intrinsic::nvvm_tex_1d_v4u32_s32:
3563 case Intrinsic::nvvm_tex_1d_v4u32_f32:
3564 case Intrinsic::nvvm_tex_1d_level_v4u32_f32:
3565 case Intrinsic::nvvm_tex_1d_grad_v4u32_f32:
3566 case Intrinsic::nvvm_tex_1d_array_v4u32_s32:
3567 case Intrinsic::nvvm_tex_1d_array_v4u32_f32:
3568 case Intrinsic::nvvm_tex_1d_array_level_v4u32_f32:
3569 case Intrinsic::nvvm_tex_1d_array_grad_v4u32_f32:
3570 case Intrinsic::nvvm_tex_2d_v4u32_s32:
3571 case Intrinsic::nvvm_tex_2d_v4u32_f32:
3572 case Intrinsic::nvvm_tex_2d_level_v4u32_f32:
3573 case Intrinsic::nvvm_tex_2d_grad_v4u32_f32:
3574 case Intrinsic::nvvm_tex_2d_array_v4u32_s32:
3575 case Intrinsic::nvvm_tex_2d_array_v4u32_f32:
3576 case Intrinsic::nvvm_tex_2d_array_level_v4u32_f32:
3577 case Intrinsic::nvvm_tex_2d_array_grad_v4u32_f32:
3578 case Intrinsic::nvvm_tex_3d_v4u32_s32:
3579 case Intrinsic::nvvm_tex_3d_v4u32_f32:
3580 case Intrinsic::nvvm_tex_3d_level_v4u32_f32:
3581 case Intrinsic::nvvm_tex_3d_grad_v4u32_f32:
3582 case Intrinsic::nvvm_tld4_r_2d_v4s32_f32:
3583 case Intrinsic::nvvm_tld4_g_2d_v4s32_f32:
3584 case Intrinsic::nvvm_tld4_b_2d_v4s32_f32:
3585 case Intrinsic::nvvm_tld4_a_2d_v4s32_f32:
3586 case Intrinsic::nvvm_tld4_r_2d_v4u32_f32:
3587 case Intrinsic::nvvm_tld4_g_2d_v4u32_f32:
3588 case Intrinsic::nvvm_tld4_b_2d_v4u32_f32:
3589 case Intrinsic::nvvm_tld4_a_2d_v4u32_f32:
3590 case Intrinsic::nvvm_tex_unified_1d_v4s32_s32:
3591 case Intrinsic::nvvm_tex_unified_1d_v4s32_f32:
3592 case Intrinsic::nvvm_tex_unified_1d_level_v4s32_f32:
3593 case Intrinsic::nvvm_tex_unified_1d_grad_v4s32_f32:
3594 case Intrinsic::nvvm_tex_unified_1d_array_v4s32_s32:
3595 case Intrinsic::nvvm_tex_unified_1d_array_v4s32_f32:
3596 case Intrinsic::nvvm_tex_unified_1d_array_level_v4s32_f32:
3597 case Intrinsic::nvvm_tex_unified_1d_array_grad_v4s32_f32:
3598 case Intrinsic::nvvm_tex_unified_2d_v4s32_s32:
3599 case Intrinsic::nvvm_tex_unified_2d_v4s32_f32:
3600 case Intrinsic::nvvm_tex_unified_2d_level_v4s32_f32:
3601 case Intrinsic::nvvm_tex_unified_2d_grad_v4s32_f32:
3602 case Intrinsic::nvvm_tex_unified_2d_array_v4s32_s32:
3603 case Intrinsic::nvvm_tex_unified_2d_array_v4s32_f32:
3604 case Intrinsic::nvvm_tex_unified_2d_array_level_v4s32_f32:
3605 case Intrinsic::nvvm_tex_unified_2d_array_grad_v4s32_f32:
3606 case Intrinsic::nvvm_tex_unified_3d_v4s32_s32:
3607 case Intrinsic::nvvm_tex_unified_3d_v4s32_f32:
3608 case Intrinsic::nvvm_tex_unified_3d_level_v4s32_f32:
3609 case Intrinsic::nvvm_tex_unified_3d_grad_v4s32_f32:
3610 case Intrinsic::nvvm_tex_unified_1d_v4u32_s32:
3611 case Intrinsic::nvvm_tex_unified_1d_v4u32_f32:
3612 case Intrinsic::nvvm_tex_unified_1d_level_v4u32_f32:
3613 case Intrinsic::nvvm_tex_unified_1d_grad_v4u32_f32:
3614 case Intrinsic::nvvm_tex_unified_1d_array_v4u32_s32:
3615 case Intrinsic::nvvm_tex_unified_1d_array_v4u32_f32:
3616 case Intrinsic::nvvm_tex_unified_1d_array_level_v4u32_f32:
3617 case Intrinsic::nvvm_tex_unified_1d_array_grad_v4u32_f32:
3618 case Intrinsic::nvvm_tex_unified_2d_v4u32_s32:
3619 case Intrinsic::nvvm_tex_unified_2d_v4u32_f32:
3620 case Intrinsic::nvvm_tex_unified_2d_level_v4u32_f32:
3621 case Intrinsic::nvvm_tex_unified_2d_grad_v4u32_f32:
3622 case Intrinsic::nvvm_tex_unified_2d_array_v4u32_s32:
3623 case Intrinsic::nvvm_tex_unified_2d_array_v4u32_f32:
3624 case Intrinsic::nvvm_tex_unified_2d_array_level_v4u32_f32:
3625 case Intrinsic::nvvm_tex_unified_2d_array_grad_v4u32_f32:
3626 case Intrinsic::nvvm_tex_unified_3d_v4u32_s32:
3627 case Intrinsic::nvvm_tex_unified_3d_v4u32_f32:
3628 case Intrinsic::nvvm_tex_unified_3d_level_v4u32_f32:
3629 case Intrinsic::nvvm_tex_unified_3d_grad_v4u32_f32:
3630 case Intrinsic::nvvm_tex_unified_cube_v4s32_f32:
3631 case Intrinsic::nvvm_tex_unified_cube_level_v4s32_f32:
3632 case Intrinsic::nvvm_tex_unified_cube_array_v4s32_f32:
3633 case Intrinsic::nvvm_tex_unified_cube_array_level_v4s32_f32:
3634 case Intrinsic::nvvm_tex_unified_cube_v4u32_f32:
3635 case Intrinsic::nvvm_tex_unified_cube_level_v4u32_f32:
3636 case Intrinsic::nvvm_tex_unified_cube_array_v4u32_f32:
3637 case Intrinsic::nvvm_tex_unified_cube_array_level_v4u32_f32:
3638 case Intrinsic::nvvm_tld4_unified_r_2d_v4s32_f32:
3639 case Intrinsic::nvvm_tld4_unified_g_2d_v4s32_f32:
3640 case Intrinsic::nvvm_tld4_unified_b_2d_v4s32_f32:
3641 case Intrinsic::nvvm_tld4_unified_a_2d_v4s32_f32:
3642 case Intrinsic::nvvm_tld4_unified_r_2d_v4u32_f32:
3643 case Intrinsic::nvvm_tld4_unified_g_2d_v4u32_f32:
3644 case Intrinsic::nvvm_tld4_unified_b_2d_v4u32_f32:
3645 case Intrinsic::nvvm_tld4_unified_a_2d_v4u32_f32:
3646 Info.opc = getOpcForTextureInstr(Intrinsic);
3647 Info.memVT = MVT::v4i32;
3648 Info.ptrVal = nullptr;
3649 Info.offset = 0;
3650 Info.flags = MachineMemOperand::MOLoad;
3651 Info.align = 16;
3652 return true;
3653
3654 case Intrinsic::nvvm_suld_1d_i8_clamp:
3655 case Intrinsic::nvvm_suld_1d_v2i8_clamp:
3656 case Intrinsic::nvvm_suld_1d_v4i8_clamp:
3657 case Intrinsic::nvvm_suld_1d_array_i8_clamp:
3658 case Intrinsic::nvvm_suld_1d_array_v2i8_clamp:
3659 case Intrinsic::nvvm_suld_1d_array_v4i8_clamp:
3660 case Intrinsic::nvvm_suld_2d_i8_clamp:
3661 case Intrinsic::nvvm_suld_2d_v2i8_clamp:
3662 case Intrinsic::nvvm_suld_2d_v4i8_clamp:
3663 case Intrinsic::nvvm_suld_2d_array_i8_clamp:
3664 case Intrinsic::nvvm_suld_2d_array_v2i8_clamp:
3665 case Intrinsic::nvvm_suld_2d_array_v4i8_clamp:
3666 case Intrinsic::nvvm_suld_3d_i8_clamp:
3667 case Intrinsic::nvvm_suld_3d_v2i8_clamp:
3668 case Intrinsic::nvvm_suld_3d_v4i8_clamp:
3669 case Intrinsic::nvvm_suld_1d_i8_trap:
3670 case Intrinsic::nvvm_suld_1d_v2i8_trap:
3671 case Intrinsic::nvvm_suld_1d_v4i8_trap:
3672 case Intrinsic::nvvm_suld_1d_array_i8_trap:
3673 case Intrinsic::nvvm_suld_1d_array_v2i8_trap:
3674 case Intrinsic::nvvm_suld_1d_array_v4i8_trap:
3675 case Intrinsic::nvvm_suld_2d_i8_trap:
3676 case Intrinsic::nvvm_suld_2d_v2i8_trap:
3677 case Intrinsic::nvvm_suld_2d_v4i8_trap:
3678 case Intrinsic::nvvm_suld_2d_array_i8_trap:
3679 case Intrinsic::nvvm_suld_2d_array_v2i8_trap:
3680 case Intrinsic::nvvm_suld_2d_array_v4i8_trap:
3681 case Intrinsic::nvvm_suld_3d_i8_trap:
3682 case Intrinsic::nvvm_suld_3d_v2i8_trap:
3683 case Intrinsic::nvvm_suld_3d_v4i8_trap:
3684 case Intrinsic::nvvm_suld_1d_i8_zero:
3685 case Intrinsic::nvvm_suld_1d_v2i8_zero:
3686 case Intrinsic::nvvm_suld_1d_v4i8_zero:
3687 case Intrinsic::nvvm_suld_1d_array_i8_zero:
3688 case Intrinsic::nvvm_suld_1d_array_v2i8_zero:
3689 case Intrinsic::nvvm_suld_1d_array_v4i8_zero:
3690 case Intrinsic::nvvm_suld_2d_i8_zero:
3691 case Intrinsic::nvvm_suld_2d_v2i8_zero:
3692 case Intrinsic::nvvm_suld_2d_v4i8_zero:
3693 case Intrinsic::nvvm_suld_2d_array_i8_zero:
3694 case Intrinsic::nvvm_suld_2d_array_v2i8_zero:
3695 case Intrinsic::nvvm_suld_2d_array_v4i8_zero:
3696 case Intrinsic::nvvm_suld_3d_i8_zero:
3697 case Intrinsic::nvvm_suld_3d_v2i8_zero:
3698 case Intrinsic::nvvm_suld_3d_v4i8_zero:
3699 Info.opc = getOpcForSurfaceInstr(Intrinsic);
3700 Info.memVT = MVT::i8;
3701 Info.ptrVal = nullptr;
3702 Info.offset = 0;
3703 Info.flags = MachineMemOperand::MOLoad;
3704 Info.align = 16;
3705 return true;
3706
3707 case Intrinsic::nvvm_suld_1d_i16_clamp:
3708 case Intrinsic::nvvm_suld_1d_v2i16_clamp:
3709 case Intrinsic::nvvm_suld_1d_v4i16_clamp:
3710 case Intrinsic::nvvm_suld_1d_array_i16_clamp:
3711 case Intrinsic::nvvm_suld_1d_array_v2i16_clamp:
3712 case Intrinsic::nvvm_suld_1d_array_v4i16_clamp:
3713 case Intrinsic::nvvm_suld_2d_i16_clamp:
3714 case Intrinsic::nvvm_suld_2d_v2i16_clamp:
3715 case Intrinsic::nvvm_suld_2d_v4i16_clamp:
3716 case Intrinsic::nvvm_suld_2d_array_i16_clamp:
3717 case Intrinsic::nvvm_suld_2d_array_v2i16_clamp:
3718 case Intrinsic::nvvm_suld_2d_array_v4i16_clamp:
3719 case Intrinsic::nvvm_suld_3d_i16_clamp:
3720 case Intrinsic::nvvm_suld_3d_v2i16_clamp:
3721 case Intrinsic::nvvm_suld_3d_v4i16_clamp:
3722 case Intrinsic::nvvm_suld_1d_i16_trap:
3723 case Intrinsic::nvvm_suld_1d_v2i16_trap:
3724 case Intrinsic::nvvm_suld_1d_v4i16_trap:
3725 case Intrinsic::nvvm_suld_1d_array_i16_trap:
3726 case Intrinsic::nvvm_suld_1d_array_v2i16_trap:
3727 case Intrinsic::nvvm_suld_1d_array_v4i16_trap:
3728 case Intrinsic::nvvm_suld_2d_i16_trap:
3729 case Intrinsic::nvvm_suld_2d_v2i16_trap:
3730 case Intrinsic::nvvm_suld_2d_v4i16_trap:
3731 case Intrinsic::nvvm_suld_2d_array_i16_trap:
3732 case Intrinsic::nvvm_suld_2d_array_v2i16_trap:
3733 case Intrinsic::nvvm_suld_2d_array_v4i16_trap:
3734 case Intrinsic::nvvm_suld_3d_i16_trap:
3735 case Intrinsic::nvvm_suld_3d_v2i16_trap:
3736 case Intrinsic::nvvm_suld_3d_v4i16_trap:
3737 case Intrinsic::nvvm_suld_1d_i16_zero:
3738 case Intrinsic::nvvm_suld_1d_v2i16_zero:
3739 case Intrinsic::nvvm_suld_1d_v4i16_zero:
3740 case Intrinsic::nvvm_suld_1d_array_i16_zero:
3741 case Intrinsic::nvvm_suld_1d_array_v2i16_zero:
3742 case Intrinsic::nvvm_suld_1d_array_v4i16_zero:
3743 case Intrinsic::nvvm_suld_2d_i16_zero:
3744 case Intrinsic::nvvm_suld_2d_v2i16_zero:
3745 case Intrinsic::nvvm_suld_2d_v4i16_zero:
3746 case Intrinsic::nvvm_suld_2d_array_i16_zero:
3747 case Intrinsic::nvvm_suld_2d_array_v2i16_zero:
3748 case Intrinsic::nvvm_suld_2d_array_v4i16_zero:
3749 case Intrinsic::nvvm_suld_3d_i16_zero:
3750 case Intrinsic::nvvm_suld_3d_v2i16_zero:
3751 case Intrinsic::nvvm_suld_3d_v4i16_zero:
3752 Info.opc = getOpcForSurfaceInstr(Intrinsic);
3753 Info.memVT = MVT::i16;
3754 Info.ptrVal = nullptr;
3755 Info.offset = 0;
3756 Info.flags = MachineMemOperand::MOLoad;
3757 Info.align = 16;
3758 return true;
3759
3760 case Intrinsic::nvvm_suld_1d_i32_clamp:
3761 case Intrinsic::nvvm_suld_1d_v2i32_clamp:
3762 case Intrinsic::nvvm_suld_1d_v4i32_clamp:
3763 case Intrinsic::nvvm_suld_1d_array_i32_clamp:
3764 case Intrinsic::nvvm_suld_1d_array_v2i32_clamp:
3765 case Intrinsic::nvvm_suld_1d_array_v4i32_clamp:
3766 case Intrinsic::nvvm_suld_2d_i32_clamp:
3767 case Intrinsic::nvvm_suld_2d_v2i32_clamp:
3768 case Intrinsic::nvvm_suld_2d_v4i32_clamp:
3769 case Intrinsic::nvvm_suld_2d_array_i32_clamp:
3770 case Intrinsic::nvvm_suld_2d_array_v2i32_clamp:
3771 case Intrinsic::nvvm_suld_2d_array_v4i32_clamp:
3772 case Intrinsic::nvvm_suld_3d_i32_clamp:
3773 case Intrinsic::nvvm_suld_3d_v2i32_clamp:
3774 case Intrinsic::nvvm_suld_3d_v4i32_clamp:
3775 case Intrinsic::nvvm_suld_1d_i32_trap:
3776 case Intrinsic::nvvm_suld_1d_v2i32_trap:
3777 case Intrinsic::nvvm_suld_1d_v4i32_trap:
3778 case Intrinsic::nvvm_suld_1d_array_i32_trap:
3779 case Intrinsic::nvvm_suld_1d_array_v2i32_trap:
3780 case Intrinsic::nvvm_suld_1d_array_v4i32_trap:
3781 case Intrinsic::nvvm_suld_2d_i32_trap:
3782 case Intrinsic::nvvm_suld_2d_v2i32_trap:
3783 case Intrinsic::nvvm_suld_2d_v4i32_trap:
3784 case Intrinsic::nvvm_suld_2d_array_i32_trap:
3785 case Intrinsic::nvvm_suld_2d_array_v2i32_trap:
3786 case Intrinsic::nvvm_suld_2d_array_v4i32_trap:
3787 case Intrinsic::nvvm_suld_3d_i32_trap:
3788 case Intrinsic::nvvm_suld_3d_v2i32_trap:
3789 case Intrinsic::nvvm_suld_3d_v4i32_trap:
3790 case Intrinsic::nvvm_suld_1d_i32_zero:
3791 case Intrinsic::nvvm_suld_1d_v2i32_zero:
3792 case Intrinsic::nvvm_suld_1d_v4i32_zero:
3793 case Intrinsic::nvvm_suld_1d_array_i32_zero:
3794 case Intrinsic::nvvm_suld_1d_array_v2i32_zero:
3795 case Intrinsic::nvvm_suld_1d_array_v4i32_zero:
3796 case Intrinsic::nvvm_suld_2d_i32_zero:
3797 case Intrinsic::nvvm_suld_2d_v2i32_zero:
3798 case Intrinsic::nvvm_suld_2d_v4i32_zero:
3799 case Intrinsic::nvvm_suld_2d_array_i32_zero:
3800 case Intrinsic::nvvm_suld_2d_array_v2i32_zero:
3801 case Intrinsic::nvvm_suld_2d_array_v4i32_zero:
3802 case Intrinsic::nvvm_suld_3d_i32_zero:
3803 case Intrinsic::nvvm_suld_3d_v2i32_zero:
3804 case Intrinsic::nvvm_suld_3d_v4i32_zero:
3805 Info.opc = getOpcForSurfaceInstr(Intrinsic);
3806 Info.memVT = MVT::i32;
3807 Info.ptrVal = nullptr;
3808 Info.offset = 0;
3809 Info.flags = MachineMemOperand::MOLoad;
3810 Info.align = 16;
3811 return true;
3812
3813 case Intrinsic::nvvm_suld_1d_i64_clamp:
3814 case Intrinsic::nvvm_suld_1d_v2i64_clamp:
3815 case Intrinsic::nvvm_suld_1d_array_i64_clamp:
3816 case Intrinsic::nvvm_suld_1d_array_v2i64_clamp:
3817 case Intrinsic::nvvm_suld_2d_i64_clamp:
3818 case Intrinsic::nvvm_suld_2d_v2i64_clamp:
3819 case Intrinsic::nvvm_suld_2d_array_i64_clamp:
3820 case Intrinsic::nvvm_suld_2d_array_v2i64_clamp:
3821 case Intrinsic::nvvm_suld_3d_i64_clamp:
3822 case Intrinsic::nvvm_suld_3d_v2i64_clamp:
3823 case Intrinsic::nvvm_suld_1d_i64_trap:
3824 case Intrinsic::nvvm_suld_1d_v2i64_trap:
3825 case Intrinsic::nvvm_suld_1d_array_i64_trap:
3826 case Intrinsic::nvvm_suld_1d_array_v2i64_trap:
3827 case Intrinsic::nvvm_suld_2d_i64_trap:
3828 case Intrinsic::nvvm_suld_2d_v2i64_trap:
3829 case Intrinsic::nvvm_suld_2d_array_i64_trap:
3830 case Intrinsic::nvvm_suld_2d_array_v2i64_trap:
3831 case Intrinsic::nvvm_suld_3d_i64_trap:
3832 case Intrinsic::nvvm_suld_3d_v2i64_trap:
3833 case Intrinsic::nvvm_suld_1d_i64_zero:
3834 case Intrinsic::nvvm_suld_1d_v2i64_zero:
3835 case Intrinsic::nvvm_suld_1d_array_i64_zero:
3836 case Intrinsic::nvvm_suld_1d_array_v2i64_zero:
3837 case Intrinsic::nvvm_suld_2d_i64_zero:
3838 case Intrinsic::nvvm_suld_2d_v2i64_zero:
3839 case Intrinsic::nvvm_suld_2d_array_i64_zero:
3840 case Intrinsic::nvvm_suld_2d_array_v2i64_zero:
3841 case Intrinsic::nvvm_suld_3d_i64_zero:
3842 case Intrinsic::nvvm_suld_3d_v2i64_zero:
3843 Info.opc = getOpcForSurfaceInstr(Intrinsic);
3844 Info.memVT = MVT::i64;
3845 Info.ptrVal = nullptr;
3846 Info.offset = 0;
3847 Info.flags = MachineMemOperand::MOLoad;
3848 Info.align = 16;
3849 return true;
3850 }
3851 return false;
3852}
3853
3854/// isLegalAddressingMode - Return true if the addressing mode represented
3855/// by AM is legal for this target, for a load/store of the specified type.
3856/// Used to guide target specific optimizations, like loop strength reduction
3857/// (LoopStrengthReduce.cpp) and memory optimization for address mode
3858/// (CodeGenPrepare.cpp)
3859bool NVPTXTargetLowering::isLegalAddressingMode(const DataLayout &DL,
3860 const AddrMode &AM, Type *Ty,
3861 unsigned AS, Instruction *I) const {
3862 // AddrMode - This represents an addressing mode of:
3863 // BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
3864 //
3865 // The legal address modes are
3866 // - [avar]
3867 // - [areg]
3868 // - [areg+immoff]
3869 // - [immAddr]
3870
3871 if (AM.BaseGV) {
3872 return !AM.BaseOffs && !AM.HasBaseReg && !AM.Scale;
3873 }
3874
3875 switch (AM.Scale) {
3876 case 0: // "r", "r+i" or "i" is allowed
3877 break;
3878 case 1:
3879 if (AM.HasBaseReg) // "r+r+i" or "r+r" is not allowed.
3880 return false;
3881 // Otherwise we have r+i.
3882 break;
3883 default:
3884 // No scale > 1 is allowed
3885 return false;
3886 }
3887 return true;
3888}
3889
3890//===----------------------------------------------------------------------===//
3891// NVPTX Inline Assembly Support
3892//===----------------------------------------------------------------------===//
3893
3894/// getConstraintType - Given a constraint letter, return the type of
3895/// constraint it is for this target.
3896NVPTXTargetLowering::ConstraintType
3897NVPTXTargetLowering::getConstraintType(StringRef Constraint) const {
3898 if (Constraint.size() == 1) {
3899 switch (Constraint[0]) {
3900 default:
3901 break;
3902 case 'b':
3903 case 'r':
3904 case 'h':
3905 case 'c':
3906 case 'l':
3907 case 'f':
3908 case 'd':
3909 case '0':
3910 case 'N':
3911 return C_RegisterClass;
3912 }
3913 }
3914 return TargetLowering::getConstraintType(Constraint);
3915}
3916
3917std::pair<unsigned, const TargetRegisterClass *>
3918NVPTXTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
3919 StringRef Constraint,
3920 MVT VT) const {
3921 if (Constraint.size() == 1) {
3922 switch (Constraint[0]) {
3923 case 'b':
3924 return std::make_pair(0U, &NVPTX::Int1RegsRegClass);
3925 case 'c':
3926 return std::make_pair(0U, &NVPTX::Int16RegsRegClass);
3927 case 'h':
3928 return std::make_pair(0U, &NVPTX::Int16RegsRegClass);
3929 case 'r':
3930 return std::make_pair(0U, &NVPTX::Int32RegsRegClass);
3931 case 'l':
3932 case 'N':
3933 return std::make_pair(0U, &NVPTX::Int64RegsRegClass);
3934 case 'f':
3935 return std::make_pair(0U, &NVPTX::Float32RegsRegClass);
3936 case 'd':
3937 return std::make_pair(0U, &NVPTX::Float64RegsRegClass);
3938 }
3939 }
3940 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
3941}
3942
3943//===----------------------------------------------------------------------===//
3944// NVPTX DAG Combining
3945//===----------------------------------------------------------------------===//
3946
3947bool NVPTXTargetLowering::allowFMA(MachineFunction &MF,
3948 CodeGenOpt::Level OptLevel) const {
3949 // Always honor command-line argument
3950 if (FMAContractLevelOpt.getNumOccurrences() > 0)
3951 return FMAContractLevelOpt > 0;
3952
3953 // Do not contract if we're not optimizing the code.
3954 if (OptLevel == 0)
3955 return false;
3956
3957 // Honor TargetOptions flags that explicitly say fusion is okay.
3958 if (MF.getTarget().Options.AllowFPOpFusion == FPOpFusion::Fast)
3959 return true;
3960
3961 return allowUnsafeFPMath(MF);
3962}
3963
3964bool NVPTXTargetLowering::allowUnsafeFPMath(MachineFunction &MF) const {
3965 // Honor TargetOptions flags that explicitly say unsafe math is okay.
3966 if (MF.getTarget().Options.UnsafeFPMath)
3967 return true;
3968
3969 // Allow unsafe math if unsafe-fp-math attribute explicitly says so.
3970 const Function &F = MF.getFunction();
3971 if (F.hasFnAttribute("unsafe-fp-math")) {
3972 Attribute Attr = F.getFnAttribute("unsafe-fp-math");
3973 StringRef Val = Attr.getValueAsString();
3974 if (Val == "true")
3975 return true;
3976 }
3977
3978 return false;
3979}
3980
3981/// PerformADDCombineWithOperands - Try DAG combinations for an ADD with
3982/// operands N0 and N1. This is a helper for PerformADDCombine that is
3983/// called with the default operands, and if that fails, with commuted
3984/// operands.
3985static SDValue PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1,
3986 TargetLowering::DAGCombinerInfo &DCI,
3987 const NVPTXSubtarget &Subtarget,
3988 CodeGenOpt::Level OptLevel) {
3989 SelectionDAG &DAG = DCI.DAG;
3990 // Skip non-integer, non-scalar case
3991 EVT VT=N0.getValueType();
3992 if (VT.isVector())
3993 return SDValue();
3994
3995 // fold (add (mul a, b), c) -> (mad a, b, c)
3996 //
3997 if (N0.getOpcode() == ISD::MUL) {
3998 assert (VT.isInteger())(static_cast <bool> (VT.isInteger()) ? void (0) : __assert_fail
("VT.isInteger()", "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/NVPTX/NVPTXISelLowering.cpp"
, 3998, __extension__ __PRETTY_FUNCTION__))
;
3999 // For integer:
4000 // Since integer multiply-add costs the same as integer multiply
4001 // but is more costly than integer add, do the fusion only when
4002 // the mul is only used in the add.
4003 if (OptLevel==CodeGenOpt::None || VT != MVT::i32 ||
4004 !N0.getNode()->hasOneUse())
4005 return SDValue();
4006
4007 // Do the folding
4008 return DAG.getNode(NVPTXISD::IMAD, SDLoc(N), VT,
4009 N0.getOperand(0), N0.getOperand(1), N1);
4010 }
4011 else if (N0.getOpcode() == ISD::FMUL) {
4012 if (VT == MVT::f32 || VT == MVT::f64) {
4013 const auto *TLI = static_cast<const NVPTXTargetLowering *>(
4014 &DAG.getTargetLoweringInfo());
4015 if (!TLI->allowFMA(DAG.getMachineFunction(), OptLevel))
4016 return SDValue();
4017
4018 // For floating point:
4019 // Do the fusion only when the mul has less than 5 uses and all
4020 // are add.
4021 // The heuristic is that if a use is not an add, then that use
4022 // cannot be fused into fma, therefore mul is still needed anyway.
4023 // If there are more than 4 uses, even if they are all add, fusing
4024 // them will increase register pressue.
4025 //
4026 int numUses = 0;
4027 int nonAddCount = 0;
4028 for (SDNode::use_iterator UI = N0.getNode()->use_begin(),
4029 UE = N0.getNode()->use_end();
4030 UI != UE; ++UI) {
4031 numUses++;
4032 SDNode *User = *UI;
4033 if (User->getOpcode() != ISD::FADD)
4034 ++nonAddCount;
4035 }
4036 if (numUses >= 5)
4037 return SDValue();
4038 if (nonAddCount) {
4039 int orderNo = N->getIROrder();
4040 int orderNo2 = N0.getNode()->getIROrder();
4041 // simple heuristics here for considering potential register
4042 // pressure, the logics here is that the differnce are used
4043 // to measure the distance between def and use, the longer distance
4044 // more likely cause register pressure.
4045 if (orderNo - orderNo2 < 500)
4046 return SDValue();
4047
4048 // Now, check if at least one of the FMUL's operands is live beyond the node N,
4049 // which guarantees that the FMA will not increase register pressure at node N.
4050 bool opIsLive = false;
4051 const SDNode *left = N0.getOperand(0).getNode();
4052 const SDNode *right = N0.getOperand(1).getNode();
4053
4054 if (isa<ConstantSDNode>(left) || isa<ConstantSDNode>(right))
4055 opIsLive = true;
4056
4057 if (!opIsLive)
4058 for (SDNode::use_iterator UI = left->use_begin(), UE = left->use_end(); UI != UE; ++UI) {
4059 SDNode *User = *UI;
4060 int orderNo3 = User->getIROrder();
4061 if (orderNo3 > orderNo) {
4062 opIsLive = true;
4063 break;
4064 }
4065 }
4066
4067 if (!opIsLive)
4068 for (SDNode::use_iterator UI = right->use_begin(), UE = right->use_end(); UI != UE; ++UI) {
4069 SDNode *User = *UI;
4070 int orderNo3 = User->getIROrder();
4071 if (orderNo3 > orderNo) {
4072 opIsLive = true;
4073 break;
4074 }
4075 }
4076
4077 if (!opIsLive)
4078 return SDValue();
4079 }
4080
4081 return DAG.getNode(ISD::FMA, SDLoc(N), VT,
4082 N0.getOperand(0), N0.getOperand(1), N1);
4083 }
4084 }
4085
4086 return SDValue();
4087}
4088
4089/// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.
4090///
4091static SDValue PerformADDCombine(SDNode *N,
4092 TargetLowering::DAGCombinerInfo &DCI,
4093 const NVPTXSubtarget &Subtarget,
4094 CodeGenOpt::Level OptLevel) {
4095 SDValue N0 = N->getOperand(0);
4096 SDValue N1 = N->getOperand(1);
4097
4098 // First try with the default operand order.
4099 if (SDValue Result =
4100 PerformADDCombineWithOperands(N, N0, N1, DCI, Subtarget, OptLevel))
4101 return Result;
4102
4103 // If that didn't work, try again with the operands commuted.
4104 return PerformADDCombineWithOperands(N, N1, N0, DCI, Subtarget, OptLevel);
4105}
4106
4107static SDValue PerformANDCombine(SDNode *N,
4108 TargetLowering::DAGCombinerInfo &DCI) {
4109 // The type legalizer turns a vector load of i8 values into a zextload to i16
4110 // registers, optionally ANY_EXTENDs it (if target type is integer),
4111 // and ANDs off the high 8 bits. Since we turn this load into a
4112 // target-specific DAG node, the DAG combiner fails to eliminate these AND
4113 // nodes. Do that here.
4114 SDValue Val = N->getOperand(0);
4115 SDValue Mask = N->getOperand(1);
4116
4117 if (isa<ConstantSDNode>(Val)) {
4118 std::swap(Val, Mask);
4119 }
4120
4121 SDValue AExt;
4122 // Generally, we will see zextload -> IMOV16rr -> ANY_EXTEND -> and
4123 if (Val.getOpcode() == ISD::ANY_EXTEND) {
4124 AExt = Val;
4125 Val = Val->getOperand(0);
4126 }
4127
4128 if (Val->isMachineOpcode() && Val->getMachineOpcode() == NVPTX::IMOV16rr) {
4129 Val = Val->getOperand(0);
4130 }
4131
4132 if (Val->getOpcode() == NVPTXISD::LoadV2 ||
4133 Val->getOpcode() == NVPTXISD::LoadV4) {
4134 ConstantSDNode *MaskCnst = dyn_cast<ConstantSDNode>(Mask);
4135 if (!MaskCnst) {
4136 // Not an AND with a constant
4137 return SDValue();
4138 }
4139
4140 uint64_t MaskVal = MaskCnst->getZExtValue();
4141 if (MaskVal != 0xff) {
4142 // Not an AND that chops off top 8 bits
4143 return SDValue();
4144 }
4145
4146 MemSDNode *Mem = dyn_cast<MemSDNode>(Val);
4147 if (!Mem) {
4148 // Not a MemSDNode?!?
4149 return SDValue();
4150 }
4151
4152 EVT MemVT = Mem->getMemoryVT();
4153 if (MemVT != MVT::v2i8 && MemVT != MVT::v4i8) {
4154 // We only handle the i8 case
4155 return SDValue();
4156 }
4157
4158 unsigned ExtType =
4159 cast<ConstantSDNode>(Val->getOperand(Val->getNumOperands()-1))->
4160 getZExtValue();
4161 if (ExtType == ISD::SEXTLOAD) {
4162 // If for some reason the load is a sextload, the and is needed to zero
4163 // out the high 8 bits
4164 return SDValue();
4165 }
4166
4167 bool AddTo = false;
4168 if (AExt.getNode() != nullptr) {
4169 // Re-insert the ext as a zext.
4170 Val = DCI.DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N),
4171 AExt.getValueType(), Val);
4172 AddTo = true;
4173 }
4174
4175 // If we get here, the AND is unnecessary. Just replace it with the load
4176 DCI.CombineTo(N, Val, AddTo);
4177 }
4178
4179 return SDValue();
4180}
4181
4182static SDValue PerformREMCombine(SDNode *N,
4183 TargetLowering::DAGCombinerInfo &DCI,
4184 CodeGenOpt::Level OptLevel) {
4185 assert(N->getOpcode() == ISD::SREM || N->getOpcode() == ISD::UREM)(static_cast <bool> (N->getOpcode() == ISD::SREM || N
->getOpcode() == ISD::UREM) ? void (0) : __assert_fail ("N->getOpcode() == ISD::SREM || N->getOpcode() == ISD::UREM"
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/NVPTX/NVPTXISelLowering.cpp"
, 4185, __extension__ __PRETTY_FUNCTION__))
;
4186
4187 // Don't do anything at less than -O2.
4188 if (OptLevel < CodeGenOpt::Default)
4189 return SDValue();
4190
4191 SelectionDAG &DAG = DCI.DAG;
4192 SDLoc DL(N);
4193 EVT VT = N->getValueType(0);
4194 bool IsSigned = N->getOpcode() == ISD::SREM;
4195 unsigned DivOpc = IsSigned ? ISD::SDIV : ISD::UDIV;
4196
4197 const SDValue &Num = N->getOperand(0);
4198 const SDValue &Den = N->getOperand(1);
4199
4200 for (const SDNode *U : Num->uses()) {
4201 if (U->getOpcode() == DivOpc && U->getOperand(0) == Num &&
4202 U->getOperand(1) == Den) {
4203 // Num % Den -> Num - (Num / Den) * Den
4204 return DAG.getNode(ISD::SUB, DL, VT, Num,
4205 DAG.getNode(ISD::MUL, DL, VT,
4206 DAG.getNode(DivOpc, DL, VT, Num, Den),
4207 Den));
4208 }
4209 }
4210 return SDValue();
4211}
4212
4213enum OperandSignedness {
4214 Signed = 0,
4215 Unsigned,
4216 Unknown
4217};
4218
4219/// IsMulWideOperandDemotable - Checks if the provided DAG node is an operand
4220/// that can be demoted to \p OptSize bits without loss of information. The
4221/// signedness of the operand, if determinable, is placed in \p S.
4222static bool IsMulWideOperandDemotable(SDValue Op,
4223 unsigned OptSize,
4224 OperandSignedness &S) {
4225 S = Unknown;
4226
4227 if (Op.getOpcode() == ISD::SIGN_EXTEND ||
4228 Op.getOpcode() == ISD::SIGN_EXTEND_INREG) {
4229 EVT OrigVT = Op.getOperand(0).getValueType();
4230 if (OrigVT.getSizeInBits() <= OptSize) {
4231 S = Signed;
4232 return true;
4233 }
4234 } else if (Op.getOpcode() == ISD::ZERO_EXTEND) {
4235 EVT OrigVT = Op.getOperand(0).getValueType();
4236 if (OrigVT.getSizeInBits() <= OptSize) {
4237 S = Unsigned;
4238 return true;
4239 }
4240 }
4241
4242 return false;
4243}
4244
4245/// AreMulWideOperandsDemotable - Checks if the given LHS and RHS operands can
4246/// be demoted to \p OptSize bits without loss of information. If the operands
4247/// contain a constant, it should appear as the RHS operand. The signedness of
4248/// the operands is placed in \p IsSigned.
4249static bool AreMulWideOperandsDemotable(SDValue LHS, SDValue RHS,
4250 unsigned OptSize,
4251 bool &IsSigned) {
4252 OperandSignedness LHSSign;
4253
4254 // The LHS operand must be a demotable op
4255 if (!IsMulWideOperandDemotable(LHS, OptSize, LHSSign))
4256 return false;
4257
4258 // We should have been able to determine the signedness from the LHS
4259 if (LHSSign == Unknown)
4260 return false;
4261
4262 IsSigned = (LHSSign == Signed);
4263
4264 // The RHS can be a demotable op or a constant
4265 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(RHS)) {
4266 const APInt &Val = CI->getAPIntValue();
4267 if (LHSSign == Unsigned) {
4268 return Val.isIntN(OptSize);
4269 } else {
4270 return Val.isSignedIntN(OptSize);
4271 }
4272 } else {
4273 OperandSignedness RHSSign;
4274 if (!IsMulWideOperandDemotable(RHS, OptSize, RHSSign))
4275 return false;
4276
4277 return LHSSign == RHSSign;
4278 }
4279}
4280
4281/// TryMULWIDECombine - Attempt to replace a multiply of M bits with a multiply
4282/// of M/2 bits that produces an M-bit result (i.e. mul.wide). This transform
4283/// works on both multiply DAG nodes and SHL DAG nodes with a constant shift
4284/// amount.
4285static SDValue TryMULWIDECombine(SDNode *N,
4286 TargetLowering::DAGCombinerInfo &DCI) {
4287 EVT MulType = N->getValueType(0);
4288 if (MulType != MVT::i32 && MulType != MVT::i64) {
4289 return SDValue();
4290 }
4291
4292 SDLoc DL(N);
4293 unsigned OptSize = MulType.getSizeInBits() >> 1;
4294 SDValue LHS = N->getOperand(0);
4295 SDValue RHS = N->getOperand(1);
4296
4297 // Canonicalize the multiply so the constant (if any) is on the right
4298 if (N->getOpcode() == ISD::MUL) {
4299 if (isa<ConstantSDNode>(LHS)) {
4300 std::swap(LHS, RHS);
4301 }
4302 }
4303
4304 // If we have a SHL, determine the actual multiply amount
4305 if (N->getOpcode() == ISD::SHL) {
4306 ConstantSDNode *ShlRHS = dyn_cast<ConstantSDNode>(RHS);
4307 if (!ShlRHS) {
4308 return SDValue();
4309 }
4310
4311 APInt ShiftAmt = ShlRHS->getAPIntValue();
4312 unsigned BitWidth = MulType.getSizeInBits();
4313 if (ShiftAmt.sge(0) && ShiftAmt.slt(BitWidth)) {
4314 APInt MulVal = APInt(BitWidth, 1) << ShiftAmt;
4315 RHS = DCI.DAG.getConstant(MulVal, DL, MulType);
4316 } else {
4317 return SDValue();
4318 }
4319 }
4320
4321 bool Signed;
4322 // Verify that our operands are demotable
4323 if (!AreMulWideOperandsDemotable(LHS, RHS, OptSize, Signed)) {
4324 return SDValue();
4325 }
4326
4327 EVT DemotedVT;
4328 if (MulType == MVT::i32) {
4329 DemotedVT = MVT::i16;
4330 } else {
4331 DemotedVT = MVT::i32;
4332 }
4333
4334 // Truncate the operands to the correct size. Note that these are just for
4335 // type consistency and will (likely) be eliminated in later phases.
4336 SDValue TruncLHS =
4337 DCI.DAG.getNode(ISD::TRUNCATE, DL, DemotedVT, LHS);
4338 SDValue TruncRHS =
4339 DCI.DAG.getNode(ISD::TRUNCATE, DL, DemotedVT, RHS);
4340
4341 unsigned Opc;
4342 if (Signed) {
4343 Opc = NVPTXISD::MUL_WIDE_SIGNED;
4344 } else {
4345 Opc = NVPTXISD::MUL_WIDE_UNSIGNED;
4346 }
4347
4348 return DCI.DAG.getNode(Opc, DL, MulType, TruncLHS, TruncRHS);
4349}
4350
4351/// PerformMULCombine - Runs PTX-specific DAG combine patterns on MUL nodes.
4352static SDValue PerformMULCombine(SDNode *N,
4353 TargetLowering::DAGCombinerInfo &DCI,
4354 CodeGenOpt::Level OptLevel) {
4355 if (OptLevel > 0) {
4356 // Try mul.wide combining at OptLevel > 0
4357 if (SDValue Ret = TryMULWIDECombine(N, DCI))
4358 return Ret;
4359 }
4360
4361 return SDValue();
4362}
4363
4364/// PerformSHLCombine - Runs PTX-specific DAG combine patterns on SHL nodes.
4365static SDValue PerformSHLCombine(SDNode *N,
4366 TargetLowering::DAGCombinerInfo &DCI,
4367 CodeGenOpt::Level OptLevel) {
4368 if (OptLevel > 0) {
4369 // Try mul.wide combining at OptLevel > 0
4370 if (SDValue Ret = TryMULWIDECombine(N, DCI))
4371 return Ret;
4372 }
4373
4374 return SDValue();
4375}
4376
4377static SDValue PerformSETCCCombine(SDNode *N,
4378 TargetLowering::DAGCombinerInfo &DCI) {
4379 EVT CCType = N->getValueType(0);
4380 SDValue A = N->getOperand(0);
4381 SDValue B = N->getOperand(1);
4382
4383 if (CCType != MVT::v2i1 || A.getValueType() != MVT::v2f16)
4384 return SDValue();
4385
4386 SDLoc DL(N);
4387 // setp.f16x2 returns two scalar predicates, which we need to
4388 // convert back to v2i1. The returned result will be scalarized by
4389 // the legalizer, but the comparison will remain a single vector
4390 // instruction.
4391 SDValue CCNode = DCI.DAG.getNode(NVPTXISD::SETP_F16X2, DL,
4392 DCI.DAG.getVTList(MVT::i1, MVT::i1),
4393 {A, B, N->getOperand(2)});
4394 return DCI.DAG.getNode(ISD::BUILD_VECTOR, DL, CCType, CCNode.getValue(0),
4395 CCNode.getValue(1));
4396}
4397
4398SDValue NVPTXTargetLowering::PerformDAGCombine(SDNode *N,
4399 DAGCombinerInfo &DCI) const {
4400 CodeGenOpt::Level OptLevel = getTargetMachine().getOptLevel();
4401 switch (N->getOpcode()) {
4402 default: break;
4403 case ISD::ADD:
4404 case ISD::FADD:
4405 return PerformADDCombine(N, DCI, STI, OptLevel);
4406 case ISD::MUL:
4407 return PerformMULCombine(N, DCI, OptLevel);
4408 case ISD::SHL:
4409 return PerformSHLCombine(N, DCI, OptLevel);
4410 case ISD::AND:
4411 return PerformANDCombine(N, DCI);
4412 case ISD::UREM:
4413 case ISD::SREM:
4414 return PerformREMCombine(N, DCI, OptLevel);
4415 case ISD::SETCC:
4416 return PerformSETCCCombine(N, DCI);
4417 }
4418 return SDValue();
4419}
4420
4421/// ReplaceVectorLoad - Convert vector loads into multi-output scalar loads.
4422static void ReplaceLoadVector(SDNode *N, SelectionDAG &DAG,
4423 SmallVectorImpl<SDValue> &Results) {
4424 EVT ResVT = N->getValueType(0);
4425 SDLoc DL(N);
4426
4427 assert(ResVT.isVector() && "Vector load must have vector type")(static_cast <bool> (ResVT.isVector() && "Vector load must have vector type"
) ? void (0) : __assert_fail ("ResVT.isVector() && \"Vector load must have vector type\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/NVPTX/NVPTXISelLowering.cpp"
, 4427, __extension__ __PRETTY_FUNCTION__))
;
4428
4429 // We only handle "native" vector sizes for now, e.g. <4 x double> is not
4430 // legal. We can (and should) split that into 2 loads of <2 x double> here
4431 // but I'm leaving that as a TODO for now.
4432 assert(ResVT.isSimple() && "Can only handle simple types")(static_cast <bool> (ResVT.isSimple() && "Can only handle simple types"
) ? void (0) : __assert_fail ("ResVT.isSimple() && \"Can only handle simple types\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/NVPTX/NVPTXISelLowering.cpp"
, 4432, __extension__ __PRETTY_FUNCTION__))
;
4433 switch (ResVT.getSimpleVT().SimpleTy) {
4434 default:
4435 return;
4436 case MVT::v2i8:
4437 case MVT::v2i16:
4438 case MVT::v2i32:
4439 case MVT::v2i64:
4440 case MVT::v2f16:
4441 case MVT::v2f32:
4442 case MVT::v2f64:
4443 case MVT::v4i8:
4444 case MVT::v4i16:
4445 case MVT::v4i32:
4446 case MVT::v4f16:
4447 case MVT::v4f32:
4448 case MVT::v8f16: // <4 x f16x2>
4449 // This is a "native" vector type
4450 break;
4451 }
4452
4453 LoadSDNode *LD = cast<LoadSDNode>(N);
4454
4455 unsigned Align = LD->getAlignment();
4456 auto &TD = DAG.getDataLayout();
4457 unsigned PrefAlign =
4458 TD.getPrefTypeAlignment(ResVT.getTypeForEVT(*DAG.getContext()));
4459 if (Align < PrefAlign) {
4460 // This load is not sufficiently aligned, so bail out and let this vector
4461 // load be scalarized. Note that we may still be able to emit smaller
4462 // vector loads. For example, if we are loading a <4 x float> with an
4463 // alignment of 8, this check will fail but the legalizer will try again
4464 // with 2 x <2 x float>, which will succeed with an alignment of 8.
4465 return;
4466 }
4467
4468 EVT EltVT = ResVT.getVectorElementType();
4469 unsigned NumElts = ResVT.getVectorNumElements();
4470
4471 // Since LoadV2 is a target node, we cannot rely on DAG type legalization.
4472 // Therefore, we must ensure the type is legal. For i1 and i8, we set the
4473 // loaded type to i16 and propagate the "real" type as the memory type.
4474 bool NeedTrunc = false;
4475 if (EltVT.getSizeInBits() < 16) {
4476 EltVT = MVT::i16;
4477 NeedTrunc = true;
4478 }
4479
4480 unsigned Opcode = 0;
4481 SDVTList LdResVTs;
4482 bool LoadF16x2 = false;
4483
4484 switch (NumElts) {
4485 default:
4486 return;
4487 case 2:
4488 Opcode = NVPTXISD::LoadV2;
4489 LdResVTs = DAG.getVTList(EltVT, EltVT, MVT::Other);
4490 break;
4491 case 4: {
4492 Opcode = NVPTXISD::LoadV4;
4493 EVT ListVTs[] = { EltVT, EltVT, EltVT, EltVT, MVT::Other };
4494 LdResVTs = DAG.getVTList(ListVTs);
4495 break;
4496 }
4497 case 8: {
4498 // v8f16 is a special case. PTX doesn't have ld.v8.f16
4499 // instruction. Instead, we split the vector into v2f16 chunks and
4500 // load them with ld.v4.b32.
4501 assert(EltVT == MVT::f16 && "Unsupported v8 vector type.")(static_cast <bool> (EltVT == MVT::f16 && "Unsupported v8 vector type."
) ? void (0) : __assert_fail ("EltVT == MVT::f16 && \"Unsupported v8 vector type.\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/NVPTX/NVPTXISelLowering.cpp"
, 4501, __extension__ __PRETTY_FUNCTION__))
;
4502 LoadF16x2 = true;
4503 Opcode = NVPTXISD::LoadV4;
4504 EVT ListVTs[] = {MVT::v2f16, MVT::v2f16, MVT::v2f16, MVT::v2f16,
4505 MVT::Other};
4506 LdResVTs = DAG.getVTList(ListVTs);
4507 break;
4508 }
4509 }
4510
4511 // Copy regular operands
4512 SmallVector<SDValue, 8> OtherOps(N->op_begin(), N->op_end());
4513
4514 // The select routine does not have access to the LoadSDNode instance, so
4515 // pass along the extension information
4516 OtherOps.push_back(DAG.getIntPtrConstant(LD->getExtensionType(), DL));
4517
4518 SDValue NewLD = DAG.getMemIntrinsicNode(Opcode, DL, LdResVTs, OtherOps,
4519 LD->getMemoryVT(),
4520 LD->getMemOperand());
4521
4522 SmallVector<SDValue, 8> ScalarRes;
4523 if (LoadF16x2) {
4524 // Split v2f16 subvectors back into individual elements.
4525 NumElts /= 2;
4526 for (unsigned i = 0; i < NumElts; ++i) {
4527 SDValue SubVector = NewLD.getValue(i);
4528 SDValue E0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, SubVector,
4529 DAG.getIntPtrConstant(0, DL));
4530 SDValue E1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, SubVector,
4531 DAG.getIntPtrConstant(1, DL));
4532 ScalarRes.push_back(E0);
4533 ScalarRes.push_back(E1);
4534 }
4535 } else {
4536 for (unsigned i = 0; i < NumElts; ++i) {
4537 SDValue Res = NewLD.getValue(i);
4538 if (NeedTrunc)
4539 Res = DAG.getNode(ISD::TRUNCATE, DL, ResVT.getVectorElementType(), Res);
4540 ScalarRes.push_back(Res);
4541 }
4542 }
4543
4544 SDValue LoadChain = NewLD.getValue(NumElts);
4545
4546 SDValue BuildVec = DAG.getBuildVector(ResVT, DL, ScalarRes);
4547
4548 Results.push_back(BuildVec);
4549 Results.push_back(LoadChain);
4550}
4551
4552static void ReplaceINTRINSIC_W_CHAIN(SDNode *N, SelectionDAG &DAG,
4553 SmallVectorImpl<SDValue> &Results) {
4554 SDValue Chain = N->getOperand(0);
4555 SDValue Intrin = N->getOperand(1);
4556 SDLoc DL(N);
4557
4558 // Get the intrinsic ID
4559 unsigned IntrinNo = cast<ConstantSDNode>(Intrin.getNode())->getZExtValue();
4560 switch (IntrinNo) {
4561 default:
4562 return;
4563 case Intrinsic::nvvm_ldg_global_i:
4564 case Intrinsic::nvvm_ldg_global_f:
4565 case Intrinsic::nvvm_ldg_global_p:
4566 case Intrinsic::nvvm_ldu_global_i:
4567 case Intrinsic::nvvm_ldu_global_f:
4568 case Intrinsic::nvvm_ldu_global_p: {
4569 EVT ResVT = N->getValueType(0);
4570
4571 if (ResVT.isVector()) {
4572 // Vector LDG/LDU
4573
4574 unsigned NumElts = ResVT.getVectorNumElements();
4575 EVT EltVT = ResVT.getVectorElementType();
4576
4577 // Since LDU/LDG are target nodes, we cannot rely on DAG type
4578 // legalization.
4579 // Therefore, we must ensure the type is legal. For i1 and i8, we set the
4580 // loaded type to i16 and propagate the "real" type as the memory type.
4581 bool NeedTrunc = false;
4582 if (EltVT.getSizeInBits() < 16) {
4583 EltVT = MVT::i16;
4584 NeedTrunc = true;
4585 }
4586
4587 unsigned Opcode = 0;
4588 SDVTList LdResVTs;
4589
4590 switch (NumElts) {
4591 default:
4592 return;
4593 case 2:
4594 switch (IntrinNo) {
4595 default:
4596 return;
4597 case Intrinsic::nvvm_ldg_global_i:
4598 case Intrinsic::nvvm_ldg_global_f:
4599 case Intrinsic::nvvm_ldg_global_p:
4600 Opcode = NVPTXISD::LDGV2;
4601 break;
4602 case Intrinsic::nvvm_ldu_global_i:
4603 case Intrinsic::nvvm_ldu_global_f:
4604 case Intrinsic::nvvm_ldu_global_p:
4605 Opcode = NVPTXISD::LDUV2;
4606 break;
4607 }
4608 LdResVTs = DAG.getVTList(EltVT, EltVT, MVT::Other);
4609 break;
4610 case 4: {
4611 switch (IntrinNo) {
4612 default:
4613 return;
4614 case Intrinsic::nvvm_ldg_global_i:
4615 case Intrinsic::nvvm_ldg_global_f:
4616 case Intrinsic::nvvm_ldg_global_p:
4617 Opcode = NVPTXISD::LDGV4;
4618 break;
4619 case Intrinsic::nvvm_ldu_global_i:
4620 case Intrinsic::nvvm_ldu_global_f:
4621 case Intrinsic::nvvm_ldu_global_p:
4622 Opcode = NVPTXISD::LDUV4;
4623 break;
4624 }
4625 EVT ListVTs[] = { EltVT, EltVT, EltVT, EltVT, MVT::Other };
4626 LdResVTs = DAG.getVTList(ListVTs);
4627 break;
4628 }
4629 }
4630
4631 SmallVector<SDValue, 8> OtherOps;
4632
4633 // Copy regular operands
4634
4635 OtherOps.push_back(Chain); // Chain
4636 // Skip operand 1 (intrinsic ID)
4637 // Others
4638 OtherOps.append(N->op_begin() + 2, N->op_end());
4639
4640 MemIntrinsicSDNode *MemSD = cast<MemIntrinsicSDNode>(N);
4641
4642 SDValue NewLD = DAG.getMemIntrinsicNode(Opcode, DL, LdResVTs, OtherOps,
4643 MemSD->getMemoryVT(),
4644 MemSD->getMemOperand());
4645
4646 SmallVector<SDValue, 4> ScalarRes;
4647
4648 for (unsigned i = 0; i < NumElts; ++i) {
4649 SDValue Res = NewLD.getValue(i);
4650 if (NeedTrunc)
4651 Res =
4652 DAG.getNode(ISD::TRUNCATE, DL, ResVT.getVectorElementType(), Res);
4653 ScalarRes.push_back(Res);
4654 }
4655
4656 SDValue LoadChain = NewLD.getValue(NumElts);
4657
4658 SDValue BuildVec =
4659 DAG.getBuildVector(ResVT, DL, ScalarRes);
4660
4661 Results.push_back(BuildVec);
4662 Results.push_back(LoadChain);
4663 } else {
4664 // i8 LDG/LDU
4665 assert(ResVT.isSimple() && ResVT.getSimpleVT().SimpleTy == MVT::i8 &&(static_cast <bool> (ResVT.isSimple() && ResVT.
getSimpleVT().SimpleTy == MVT::i8 && "Custom handling of non-i8 ldu/ldg?"
) ? void (0) : __assert_fail ("ResVT.isSimple() && ResVT.getSimpleVT().SimpleTy == MVT::i8 && \"Custom handling of non-i8 ldu/ldg?\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/NVPTX/NVPTXISelLowering.cpp"
, 4666, __extension__ __PRETTY_FUNCTION__))
4666 "Custom handling of non-i8 ldu/ldg?")(static_cast <bool> (ResVT.isSimple() && ResVT.
getSimpleVT().SimpleTy == MVT::i8 && "Custom handling of non-i8 ldu/ldg?"
) ? void (0) : __assert_fail ("ResVT.isSimple() && ResVT.getSimpleVT().SimpleTy == MVT::i8 && \"Custom handling of non-i8 ldu/ldg?\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/NVPTX/NVPTXISelLowering.cpp"
, 4666, __extension__ __PRETTY_FUNCTION__))
;
4667
4668 // Just copy all operands as-is
4669 SmallVector<SDValue, 4> Ops(N->op_begin(), N->op_end());
4670
4671 // Force output to i16
4672 SDVTList LdResVTs = DAG.getVTList(MVT::i16, MVT::Other);
4673
4674 MemIntrinsicSDNode *MemSD = cast<MemIntrinsicSDNode>(N);
4675
4676 // We make sure the memory type is i8, which will be used during isel
4677 // to select the proper instruction.
4678 SDValue NewLD =
4679 DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, DL, LdResVTs, Ops,
4680 MVT::i8, MemSD->getMemOperand());
4681
4682 Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i8,
4683 NewLD.getValue(0)));
4684 Results.push_back(NewLD.getValue(1));
4685 }
4686 }
4687 }
4688}
4689
4690void NVPTXTargetLowering::ReplaceNodeResults(
4691 SDNode *N, SmallVectorImpl<SDValue> &Results, SelectionDAG &DAG) const {
4692 switch (N->getOpcode()) {
4693 default:
4694 report_fatal_error("Unhandled custom legalization");
4695 case ISD::LOAD:
4696 ReplaceLoadVector(N, DAG, Results);
4697 return;
4698 case ISD::INTRINSIC_W_CHAIN:
4699 ReplaceINTRINSIC_W_CHAIN(N, DAG, Results);
4700 return;
4701 }
4702}
4703
4704// Pin NVPTXSection's and NVPTXTargetObjectFile's vtables to this file.
4705void NVPTXSection::anchor() {}
4706
4707NVPTXTargetObjectFile::~NVPTXTargetObjectFile() {
4708 delete static_cast<NVPTXSection *>(TextSection);
4709 delete static_cast<NVPTXSection *>(DataSection);
4710 delete static_cast<NVPTXSection *>(BSSSection);
4711 delete static_cast<NVPTXSection *>(ReadOnlySection);
4712
4713 delete static_cast<NVPTXSection *>(StaticCtorSection);
4714 delete static_cast<NVPTXSection *>(StaticDtorSection);
4715 delete static_cast<NVPTXSection *>(LSDASection);
4716 delete static_cast<NVPTXSection *>(EHFrameSection);
4717 delete static_cast<NVPTXSection *>(DwarfAbbrevSection);
4718 delete static_cast<NVPTXSection *>(DwarfInfoSection);
4719 delete static_cast<NVPTXSection *>(DwarfLineSection);
4720 delete static_cast<NVPTXSection *>(DwarfFrameSection);
4721 delete static_cast<NVPTXSection *>(DwarfPubTypesSection);
4722 delete static_cast<const NVPTXSection *>(DwarfDebugInlineSection);
4723 delete static_cast<NVPTXSection *>(DwarfStrSection);
4724 delete static_cast<NVPTXSection *>(DwarfLocSection);
4725 delete static_cast<NVPTXSection *>(DwarfARangesSection);
4726 delete static_cast<NVPTXSection *>(DwarfRangesSection);
4727 delete static_cast<NVPTXSection *>(DwarfMacinfoSection);
4728}
4729
4730MCSection *NVPTXTargetObjectFile::SelectSectionForGlobal(
4731 const GlobalObject *GO, SectionKind Kind, const TargetMachine &TM) const {
4732 return getDataSection();
4733}