Bug Summary

File:lib/Target/PowerPC/PPCFrameLowering.cpp
Location:line 1169, column 9
Description:Value stored to 'PBPSI' during its initialization is never read

Annotated Source Code

1//===-- PPCFrameLowering.cpp - PPC Frame Information ----------------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the PPC implementation of TargetFrameLowering class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "PPCFrameLowering.h"
15#include "PPCInstrBuilder.h"
16#include "PPCInstrInfo.h"
17#include "PPCMachineFunctionInfo.h"
18#include "PPCSubtarget.h"
19#include "llvm/CodeGen/MachineFrameInfo.h"
20#include "llvm/CodeGen/MachineFunction.h"
21#include "llvm/CodeGen/MachineInstrBuilder.h"
22#include "llvm/CodeGen/MachineModuleInfo.h"
23#include "llvm/CodeGen/MachineRegisterInfo.h"
24#include "llvm/CodeGen/RegisterScavenging.h"
25#include "llvm/IR/Function.h"
26#include "llvm/Target/TargetOptions.h"
27
28using namespace llvm;
29
30/// VRRegNo - Map from a numbered VR register to its enum value.
31///
32static const uint16_t VRRegNo[] = {
33 PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 ,
34 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15,
35 PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23,
36 PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31
37};
38
39PPCFrameLowering::PPCFrameLowering(const PPCSubtarget &STI)
40 : TargetFrameLowering(TargetFrameLowering::StackGrowsDown,
41 (STI.hasQPX() || STI.isBGQ()) ? 32 : 16, 0),
42 Subtarget(STI) {}
43
44// With the SVR4 ABI, callee-saved registers have fixed offsets on the stack.
45const PPCFrameLowering::SpillSlot *PPCFrameLowering::getCalleeSavedSpillSlots(
46 unsigned &NumEntries) const {
47 if (Subtarget.isDarwinABI()) {
48 NumEntries = 1;
49 if (Subtarget.isPPC64()) {
50 static const SpillSlot darwin64Offsets = {PPC::X31, -8};
51 return &darwin64Offsets;
52 } else {
53 static const SpillSlot darwinOffsets = {PPC::R31, -4};
54 return &darwinOffsets;
55 }
56 }
57
58 // Early exit if not using the SVR4 ABI.
59 if (!Subtarget.isSVR4ABI()) {
60 NumEntries = 0;
61 return nullptr;
62 }
63
64 // Note that the offsets here overlap, but this is fixed up in
65 // processFunctionBeforeFrameFinalized.
66
67 static const SpillSlot Offsets[] = {
68 // Floating-point register save area offsets.
69 {PPC::F31, -8},
70 {PPC::F30, -16},
71 {PPC::F29, -24},
72 {PPC::F28, -32},
73 {PPC::F27, -40},
74 {PPC::F26, -48},
75 {PPC::F25, -56},
76 {PPC::F24, -64},
77 {PPC::F23, -72},
78 {PPC::F22, -80},
79 {PPC::F21, -88},
80 {PPC::F20, -96},
81 {PPC::F19, -104},
82 {PPC::F18, -112},
83 {PPC::F17, -120},
84 {PPC::F16, -128},
85 {PPC::F15, -136},
86 {PPC::F14, -144},
87
88 // General register save area offsets.
89 {PPC::R31, -4},
90 {PPC::R30, -8},
91 {PPC::R29, -12},
92 {PPC::R28, -16},
93 {PPC::R27, -20},
94 {PPC::R26, -24},
95 {PPC::R25, -28},
96 {PPC::R24, -32},
97 {PPC::R23, -36},
98 {PPC::R22, -40},
99 {PPC::R21, -44},
100 {PPC::R20, -48},
101 {PPC::R19, -52},
102 {PPC::R18, -56},
103 {PPC::R17, -60},
104 {PPC::R16, -64},
105 {PPC::R15, -68},
106 {PPC::R14, -72},
107
108 // CR save area offset. We map each of the nonvolatile CR fields
109 // to the slot for CR2, which is the first of the nonvolatile CR
110 // fields to be assigned, so that we only allocate one save slot.
111 // See PPCRegisterInfo::hasReservedSpillSlot() for more information.
112 {PPC::CR2, -4},
113
114 // VRSAVE save area offset.
115 {PPC::VRSAVE, -4},
116
117 // Vector register save area
118 {PPC::V31, -16},
119 {PPC::V30, -32},
120 {PPC::V29, -48},
121 {PPC::V28, -64},
122 {PPC::V27, -80},
123 {PPC::V26, -96},
124 {PPC::V25, -112},
125 {PPC::V24, -128},
126 {PPC::V23, -144},
127 {PPC::V22, -160},
128 {PPC::V21, -176},
129 {PPC::V20, -192}};
130
131 static const SpillSlot Offsets64[] = {
132 // Floating-point register save area offsets.
133 {PPC::F31, -8},
134 {PPC::F30, -16},
135 {PPC::F29, -24},
136 {PPC::F28, -32},
137 {PPC::F27, -40},
138 {PPC::F26, -48},
139 {PPC::F25, -56},
140 {PPC::F24, -64},
141 {PPC::F23, -72},
142 {PPC::F22, -80},
143 {PPC::F21, -88},
144 {PPC::F20, -96},
145 {PPC::F19, -104},
146 {PPC::F18, -112},
147 {PPC::F17, -120},
148 {PPC::F16, -128},
149 {PPC::F15, -136},
150 {PPC::F14, -144},
151
152 // General register save area offsets.
153 {PPC::X31, -8},
154 {PPC::X30, -16},
155 {PPC::X29, -24},
156 {PPC::X28, -32},
157 {PPC::X27, -40},
158 {PPC::X26, -48},
159 {PPC::X25, -56},
160 {PPC::X24, -64},
161 {PPC::X23, -72},
162 {PPC::X22, -80},
163 {PPC::X21, -88},
164 {PPC::X20, -96},
165 {PPC::X19, -104},
166 {PPC::X18, -112},
167 {PPC::X17, -120},
168 {PPC::X16, -128},
169 {PPC::X15, -136},
170 {PPC::X14, -144},
171
172 // VRSAVE save area offset.
173 {PPC::VRSAVE, -4},
174
175 // Vector register save area
176 {PPC::V31, -16},
177 {PPC::V30, -32},
178 {PPC::V29, -48},
179 {PPC::V28, -64},
180 {PPC::V27, -80},
181 {PPC::V26, -96},
182 {PPC::V25, -112},
183 {PPC::V24, -128},
184 {PPC::V23, -144},
185 {PPC::V22, -160},
186 {PPC::V21, -176},
187 {PPC::V20, -192}};
188
189 if (Subtarget.isPPC64()) {
190 NumEntries = array_lengthof(Offsets64);
191
192 return Offsets64;
193 } else {
194 NumEntries = array_lengthof(Offsets);
195
196 return Offsets;
197 }
198}
199
200/// RemoveVRSaveCode - We have found that this function does not need any code
201/// to manipulate the VRSAVE register, even though it uses vector registers.
202/// This can happen when the only registers used are known to be live in or out
203/// of the function. Remove all of the VRSAVE related code from the function.
204/// FIXME: The removal of the code results in a compile failure at -O0 when the
205/// function contains a function call, as the GPR containing original VRSAVE
206/// contents is spilled and reloaded around the call. Without the prolog code,
207/// the spill instruction refers to an undefined register. This code needs
208/// to account for all uses of that GPR.
209static void RemoveVRSaveCode(MachineInstr *MI) {
210 MachineBasicBlock *Entry = MI->getParent();
211 MachineFunction *MF = Entry->getParent();
212
213 // We know that the MTVRSAVE instruction immediately follows MI. Remove it.
214 MachineBasicBlock::iterator MBBI = MI;
215 ++MBBI;
216 assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE)((MBBI != Entry->end() && MBBI->getOpcode() == PPC
::MTVRSAVE) ? static_cast<void> (0) : __assert_fail ("MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE"
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn228917/lib/Target/PowerPC/PPCFrameLowering.cpp"
, 216, __PRETTY_FUNCTION__));
217 MBBI->eraseFromParent();
218
219 bool RemovedAllMTVRSAVEs = true;
220 // See if we can find and remove the MTVRSAVE instruction from all of the
221 // epilog blocks.
222 for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) {
223 // If last instruction is a return instruction, add an epilogue
224 if (!I->empty() && I->back().isReturn()) {
225 bool FoundIt = false;
226 for (MBBI = I->end(); MBBI != I->begin(); ) {
227 --MBBI;
228 if (MBBI->getOpcode() == PPC::MTVRSAVE) {
229 MBBI->eraseFromParent(); // remove it.
230 FoundIt = true;
231 break;
232 }
233 }
234 RemovedAllMTVRSAVEs &= FoundIt;
235 }
236 }
237
238 // If we found and removed all MTVRSAVE instructions, remove the read of
239 // VRSAVE as well.
240 if (RemovedAllMTVRSAVEs) {
241 MBBI = MI;
242 assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?")((MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?"
) ? static_cast<void> (0) : __assert_fail ("MBBI != Entry->begin() && \"UPDATE_VRSAVE is first instr in block?\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn228917/lib/Target/PowerPC/PPCFrameLowering.cpp"
, 242, __PRETTY_FUNCTION__));
243 --MBBI;
244 assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?")((MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?"
) ? static_cast<void> (0) : __assert_fail ("MBBI->getOpcode() == PPC::MFVRSAVE && \"VRSAVE instrs wandered?\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn228917/lib/Target/PowerPC/PPCFrameLowering.cpp"
, 244, __PRETTY_FUNCTION__));
245 MBBI->eraseFromParent();
246 }
247
248 // Finally, nuke the UPDATE_VRSAVE.
249 MI->eraseFromParent();
250}
251
252// HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the
253// instruction selector. Based on the vector registers that have been used,
254// transform this into the appropriate ORI instruction.
255static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) {
256 MachineFunction *MF = MI->getParent()->getParent();
257 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
258 DebugLoc dl = MI->getDebugLoc();
259
260 unsigned UsedRegMask = 0;
261 for (unsigned i = 0; i != 32; ++i)
262 if (MF->getRegInfo().isPhysRegUsed(VRRegNo[i]))
263 UsedRegMask |= 1 << (31-i);
264
265 // Live in and live out values already must be in the mask, so don't bother
266 // marking them.
267 for (MachineRegisterInfo::livein_iterator
268 I = MF->getRegInfo().livein_begin(),
269 E = MF->getRegInfo().livein_end(); I != E; ++I) {
270 unsigned RegNo = TRI->getEncodingValue(I->first);
271 if (VRRegNo[RegNo] == I->first) // If this really is a vector reg.
272 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked.
273 }
274
275 // Live out registers appear as use operands on return instructions.
276 for (MachineFunction::const_iterator BI = MF->begin(), BE = MF->end();
277 UsedRegMask != 0 && BI != BE; ++BI) {
278 const MachineBasicBlock &MBB = *BI;
279 if (MBB.empty() || !MBB.back().isReturn())
280 continue;
281 const MachineInstr &Ret = MBB.back();
282 for (unsigned I = 0, E = Ret.getNumOperands(); I != E; ++I) {
283 const MachineOperand &MO = Ret.getOperand(I);
284 if (!MO.isReg() || !PPC::VRRCRegClass.contains(MO.getReg()))
285 continue;
286 unsigned RegNo = TRI->getEncodingValue(MO.getReg());
287 UsedRegMask &= ~(1 << (31-RegNo));
288 }
289 }
290
291 // If no registers are used, turn this into a copy.
292 if (UsedRegMask == 0) {
293 // Remove all VRSAVE code.
294 RemoveVRSaveCode(MI);
295 return;
296 }
297
298 unsigned SrcReg = MI->getOperand(1).getReg();
299 unsigned DstReg = MI->getOperand(0).getReg();
300
301 if ((UsedRegMask & 0xFFFF) == UsedRegMask) {
302 if (DstReg != SrcReg)
303 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
304 .addReg(SrcReg)
305 .addImm(UsedRegMask);
306 else
307 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
308 .addReg(SrcReg, RegState::Kill)
309 .addImm(UsedRegMask);
310 } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) {
311 if (DstReg != SrcReg)
312 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
313 .addReg(SrcReg)
314 .addImm(UsedRegMask >> 16);
315 else
316 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
317 .addReg(SrcReg, RegState::Kill)
318 .addImm(UsedRegMask >> 16);
319 } else {
320 if (DstReg != SrcReg)
321 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
322 .addReg(SrcReg)
323 .addImm(UsedRegMask >> 16);
324 else
325 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
326 .addReg(SrcReg, RegState::Kill)
327 .addImm(UsedRegMask >> 16);
328
329 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
330 .addReg(DstReg, RegState::Kill)
331 .addImm(UsedRegMask & 0xFFFF);
332 }
333
334 // Remove the old UPDATE_VRSAVE instruction.
335 MI->eraseFromParent();
336}
337
338static bool spillsCR(const MachineFunction &MF) {
339 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
340 return FuncInfo->isCRSpilled();
341}
342
343static bool spillsVRSAVE(const MachineFunction &MF) {
344 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
345 return FuncInfo->isVRSAVESpilled();
346}
347
348static bool hasSpills(const MachineFunction &MF) {
349 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
350 return FuncInfo->hasSpills();
351}
352
353static bool hasNonRISpills(const MachineFunction &MF) {
354 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
355 return FuncInfo->hasNonRISpills();
356}
357
358/// MustSaveLR - Return true if this function requires that we save the LR
359/// register onto the stack in the prolog and restore it in the epilog of the
360/// function.
361static bool MustSaveLR(const MachineFunction &MF, unsigned LR) {
362 const PPCFunctionInfo *MFI = MF.getInfo<PPCFunctionInfo>();
363
364 // We need a save/restore of LR if there is any def of LR (which is
365 // defined by calls, including the PIC setup sequence), or if there is
366 // some use of the LR stack slot (e.g. for builtin_return_address).
367 // (LR comes in 32 and 64 bit versions.)
368 MachineRegisterInfo::def_iterator RI = MF.getRegInfo().def_begin(LR);
369 return RI !=MF.getRegInfo().def_end() || MFI->isLRStoreRequired();
370}
371
372/// determineFrameLayout - Determine the size of the frame and maximum call
373/// frame size.
374unsigned PPCFrameLowering::determineFrameLayout(MachineFunction &MF,
375 bool UpdateMF,
376 bool UseEstimate) const {
377 MachineFrameInfo *MFI = MF.getFrameInfo();
378
379 // Get the number of bytes to allocate from the FrameInfo
380 unsigned FrameSize =
381 UseEstimate ? MFI->estimateStackSize(MF) : MFI->getStackSize();
382
383 // Get stack alignments. The frame must be aligned to the greatest of these:
384 unsigned TargetAlign = getStackAlignment(); // alignment required per the ABI
385 unsigned MaxAlign = MFI->getMaxAlignment(); // algmt required by data in frame
386 unsigned AlignMask = std::max(MaxAlign, TargetAlign) - 1;
387
388 const PPCRegisterInfo *RegInfo =
389 static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo());
390
391 // If we are a leaf function, and use up to 224 bytes of stack space,
392 // don't have a frame pointer, calls, or dynamic alloca then we do not need
393 // to adjust the stack pointer (we fit in the Red Zone).
394 // The 32-bit SVR4 ABI has no Red Zone. However, it can still generate
395 // stackless code if all local vars are reg-allocated.
396 bool DisableRedZone = MF.getFunction()->getAttributes().
397 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoRedZone);
398 unsigned LR = RegInfo->getRARegister();
399 if (!DisableRedZone &&
400 (Subtarget.isPPC64() || // 32-bit SVR4, no stack-
401 !Subtarget.isSVR4ABI() || // allocated locals.
402 FrameSize == 0) &&
403 FrameSize <= 224 && // Fits in red zone.
404 !MFI->hasVarSizedObjects() && // No dynamic alloca.
405 !MFI->adjustsStack() && // No calls.
406 !MustSaveLR(MF, LR) &&
407 !RegInfo->hasBasePointer(MF)) { // No special alignment.
408 // No need for frame
409 if (UpdateMF)
410 MFI->setStackSize(0);
411 return 0;
412 }
413
414 // Get the maximum call frame size of all the calls.
415 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
416
417 // Maximum call frame needs to be at least big enough for linkage area.
418 unsigned minCallFrameSize = getLinkageSize(Subtarget.isPPC64(),
419 Subtarget.isDarwinABI(),
420 Subtarget.isELFv2ABI());
421 maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize);
422
423 // If we have dynamic alloca then maxCallFrameSize needs to be aligned so
424 // that allocations will be aligned.
425 if (MFI->hasVarSizedObjects())
426 maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask;
427
428 // Update maximum call frame size.
429 if (UpdateMF)
430 MFI->setMaxCallFrameSize(maxCallFrameSize);
431
432 // Include call frame size in total.
433 FrameSize += maxCallFrameSize;
434
435 // Make sure the frame is aligned.
436 FrameSize = (FrameSize + AlignMask) & ~AlignMask;
437
438 // Update frame info.
439 if (UpdateMF)
440 MFI->setStackSize(FrameSize);
441
442 return FrameSize;
443}
444
445// hasFP - Return true if the specified function actually has a dedicated frame
446// pointer register.
447bool PPCFrameLowering::hasFP(const MachineFunction &MF) const {
448 const MachineFrameInfo *MFI = MF.getFrameInfo();
449 // FIXME: This is pretty much broken by design: hasFP() might be called really
450 // early, before the stack layout was calculated and thus hasFP() might return
451 // true or false here depending on the time of call.
452 return (MFI->getStackSize()) && needsFP(MF);
453}
454
455// needsFP - Return true if the specified function should have a dedicated frame
456// pointer register. This is true if the function has variable sized allocas or
457// if frame pointer elimination is disabled.
458bool PPCFrameLowering::needsFP(const MachineFunction &MF) const {
459 const MachineFrameInfo *MFI = MF.getFrameInfo();
460
461 // Naked functions have no stack frame pushed, so we don't have a frame
462 // pointer.
463 if (MF.getFunction()->getAttributes().hasAttribute(
464 AttributeSet::FunctionIndex, Attribute::Naked))
465 return false;
466
467 return MF.getTarget().Options.DisableFramePointerElim(MF) ||
468 MFI->hasVarSizedObjects() ||
469 MFI->hasStackMap() || MFI->hasPatchPoint() ||
470 (MF.getTarget().Options.GuaranteedTailCallOpt &&
471 MF.getInfo<PPCFunctionInfo>()->hasFastCall());
472}
473
474void PPCFrameLowering::replaceFPWithRealFP(MachineFunction &MF) const {
475 bool is31 = needsFP(MF);
476 unsigned FPReg = is31 ? PPC::R31 : PPC::R1;
477 unsigned FP8Reg = is31 ? PPC::X31 : PPC::X1;
478
479 const PPCRegisterInfo *RegInfo =
480 static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo());
481 bool HasBP = RegInfo->hasBasePointer(MF);
482 unsigned BPReg = HasBP ? (unsigned) RegInfo->getBaseRegister(MF) : FPReg;
483 unsigned BP8Reg = HasBP ? (unsigned) PPC::X30 : FPReg;
484
485 for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
486 BI != BE; ++BI)
487 for (MachineBasicBlock::iterator MBBI = BI->end(); MBBI != BI->begin(); ) {
488 --MBBI;
489 for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I) {
490 MachineOperand &MO = MBBI->getOperand(I);
491 if (!MO.isReg())
492 continue;
493
494 switch (MO.getReg()) {
495 case PPC::FP:
496 MO.setReg(FPReg);
497 break;
498 case PPC::FP8:
499 MO.setReg(FP8Reg);
500 break;
501 case PPC::BP:
502 MO.setReg(BPReg);
503 break;
504 case PPC::BP8:
505 MO.setReg(BP8Reg);
506 break;
507
508 }
509 }
510 }
511}
512
513void PPCFrameLowering::emitPrologue(MachineFunction &MF) const {
514 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
515 MachineBasicBlock::iterator MBBI = MBB.begin();
516 MachineFrameInfo *MFI = MF.getFrameInfo();
517 const PPCInstrInfo &TII =
518 *static_cast<const PPCInstrInfo *>(Subtarget.getInstrInfo());
519 const PPCRegisterInfo *RegInfo =
520 static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo());
521
522 MachineModuleInfo &MMI = MF.getMMI();
523 const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
524 DebugLoc dl;
525 bool needsCFI = MMI.hasDebugInfo() ||
526 MF.getFunction()->needsUnwindTableEntry();
527 bool isPIC = MF.getTarget().getRelocationModel() == Reloc::PIC_;
528
529 // Get processor type.
530 bool isPPC64 = Subtarget.isPPC64();
531 // Get the ABI.
532 bool isDarwinABI = Subtarget.isDarwinABI();
533 bool isSVR4ABI = Subtarget.isSVR4ABI();
534 bool isELFv2ABI = Subtarget.isELFv2ABI();
535 assert((isDarwinABI || isSVR4ABI) &&(((isDarwinABI || isSVR4ABI) && "Currently only Darwin and SVR4 ABIs are supported for PowerPC."
) ? static_cast<void> (0) : __assert_fail ("(isDarwinABI || isSVR4ABI) && \"Currently only Darwin and SVR4 ABIs are supported for PowerPC.\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn228917/lib/Target/PowerPC/PPCFrameLowering.cpp"
, 536, __PRETTY_FUNCTION__))
536 "Currently only Darwin and SVR4 ABIs are supported for PowerPC.")(((isDarwinABI || isSVR4ABI) && "Currently only Darwin and SVR4 ABIs are supported for PowerPC."
) ? static_cast<void> (0) : __assert_fail ("(isDarwinABI || isSVR4ABI) && \"Currently only Darwin and SVR4 ABIs are supported for PowerPC.\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn228917/lib/Target/PowerPC/PPCFrameLowering.cpp"
, 536, __PRETTY_FUNCTION__));
537
538 // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it,
539 // process it.
540 if (!isSVR4ABI)
541 for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) {
542 if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) {
543 HandleVRSaveUpdate(MBBI, TII);
544 break;
545 }
546 }
547
548 // Move MBBI back to the beginning of the function.
549 MBBI = MBB.begin();
550
551 // Work out frame sizes.
552 unsigned FrameSize = determineFrameLayout(MF);
553 int NegFrameSize = -FrameSize;
554 if (!isInt<32>(NegFrameSize))
555 llvm_unreachable("Unhandled stack size!")::llvm::llvm_unreachable_internal("Unhandled stack size!", "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn228917/lib/Target/PowerPC/PPCFrameLowering.cpp"
, 555);
556
557 if (MFI->isFrameAddressTaken())
558 replaceFPWithRealFP(MF);
559
560 // Check if the link register (LR) must be saved.
561 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
562 bool MustSaveLR = FI->mustSaveLR();
563 const SmallVectorImpl<unsigned> &MustSaveCRs = FI->getMustSaveCRs();
564 // Do we have a frame pointer and/or base pointer for this function?
565 bool HasFP = hasFP(MF);
566 bool HasBP = RegInfo->hasBasePointer(MF);
567
568 unsigned SPReg = isPPC64 ? PPC::X1 : PPC::R1;
569 unsigned BPReg = RegInfo->getBaseRegister(MF);
570 unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31;
571 unsigned LRReg = isPPC64 ? PPC::LR8 : PPC::LR;
572 unsigned ScratchReg = isPPC64 ? PPC::X0 : PPC::R0;
573 unsigned TempReg = isPPC64 ? PPC::X12 : PPC::R12; // another scratch reg
574 // ...(R12/X12 is volatile in both Darwin & SVR4, & can't be a function arg.)
575 const MCInstrDesc& MFLRInst = TII.get(isPPC64 ? PPC::MFLR8
576 : PPC::MFLR );
577 const MCInstrDesc& StoreInst = TII.get(isPPC64 ? PPC::STD
578 : PPC::STW );
579 const MCInstrDesc& StoreUpdtInst = TII.get(isPPC64 ? PPC::STDU
580 : PPC::STWU );
581 const MCInstrDesc& StoreUpdtIdxInst = TII.get(isPPC64 ? PPC::STDUX
582 : PPC::STWUX);
583 const MCInstrDesc& LoadImmShiftedInst = TII.get(isPPC64 ? PPC::LIS8
584 : PPC::LIS );
585 const MCInstrDesc& OrImmInst = TII.get(isPPC64 ? PPC::ORI8
586 : PPC::ORI );
587 const MCInstrDesc& OrInst = TII.get(isPPC64 ? PPC::OR8
588 : PPC::OR );
589 const MCInstrDesc& SubtractCarryingInst = TII.get(isPPC64 ? PPC::SUBFC8
590 : PPC::SUBFC);
591 const MCInstrDesc& SubtractImmCarryingInst = TII.get(isPPC64 ? PPC::SUBFIC8
592 : PPC::SUBFIC);
593
594 // Regarding this assert: Even though LR is saved in the caller's frame (i.e.,
595 // LROffset is positive), that slot is callee-owned. Because PPC32 SVR4 has no
596 // Red Zone, an asynchronous event (a form of "callee") could claim a frame &
597 // overwrite it, so PPC32 SVR4 must claim at least a minimal frame to save LR.
598 assert((isPPC64 || !isSVR4ABI || !(!FrameSize && (MustSaveLR || HasFP))) &&(((isPPC64 || !isSVR4ABI || !(!FrameSize && (MustSaveLR
|| HasFP))) && "FrameSize must be >0 to save/restore the FP or LR for 32-bit SVR4."
) ? static_cast<void> (0) : __assert_fail ("(isPPC64 || !isSVR4ABI || !(!FrameSize && (MustSaveLR || HasFP))) && \"FrameSize must be >0 to save/restore the FP or LR for 32-bit SVR4.\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn228917/lib/Target/PowerPC/PPCFrameLowering.cpp"
, 599, __PRETTY_FUNCTION__))
599 "FrameSize must be >0 to save/restore the FP or LR for 32-bit SVR4.")(((isPPC64 || !isSVR4ABI || !(!FrameSize && (MustSaveLR
|| HasFP))) && "FrameSize must be >0 to save/restore the FP or LR for 32-bit SVR4."
) ? static_cast<void> (0) : __assert_fail ("(isPPC64 || !isSVR4ABI || !(!FrameSize && (MustSaveLR || HasFP))) && \"FrameSize must be >0 to save/restore the FP or LR for 32-bit SVR4.\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn228917/lib/Target/PowerPC/PPCFrameLowering.cpp"
, 599, __PRETTY_FUNCTION__));
600
601 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI);
602
603 int FPOffset = 0;
604 if (HasFP) {
605 if (isSVR4ABI) {
606 MachineFrameInfo *FFI = MF.getFrameInfo();
607 int FPIndex = FI->getFramePointerSaveIndex();
608 assert(FPIndex && "No Frame Pointer Save Slot!")((FPIndex && "No Frame Pointer Save Slot!") ? static_cast
<void> (0) : __assert_fail ("FPIndex && \"No Frame Pointer Save Slot!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn228917/lib/Target/PowerPC/PPCFrameLowering.cpp"
, 608, __PRETTY_FUNCTION__));
609 FPOffset = FFI->getObjectOffset(FPIndex);
610 } else {
611 FPOffset =
612 PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
613 }
614 }
615
616 int BPOffset = 0;
617 if (HasBP) {
618 if (isSVR4ABI) {
619 MachineFrameInfo *FFI = MF.getFrameInfo();
620 int BPIndex = FI->getBasePointerSaveIndex();
621 assert(BPIndex && "No Base Pointer Save Slot!")((BPIndex && "No Base Pointer Save Slot!") ? static_cast
<void> (0) : __assert_fail ("BPIndex && \"No Base Pointer Save Slot!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn228917/lib/Target/PowerPC/PPCFrameLowering.cpp"
, 621, __PRETTY_FUNCTION__));
622 BPOffset = FFI->getObjectOffset(BPIndex);
623 } else {
624 BPOffset =
625 PPCFrameLowering::getBasePointerSaveOffset(isPPC64,
626 isDarwinABI,
627 isPIC);
628 }
629 }
630
631 int PBPOffset = 0;
632 if (FI->usesPICBase()) {
633 MachineFrameInfo *FFI = MF.getFrameInfo();
634 int PBPIndex = FI->getPICBasePointerSaveIndex();
635 assert(PBPIndex && "No PIC Base Pointer Save Slot!")((PBPIndex && "No PIC Base Pointer Save Slot!") ? static_cast
<void> (0) : __assert_fail ("PBPIndex && \"No PIC Base Pointer Save Slot!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn228917/lib/Target/PowerPC/PPCFrameLowering.cpp"
, 635, __PRETTY_FUNCTION__));
636 PBPOffset = FFI->getObjectOffset(PBPIndex);
637 }
638
639 // Get stack alignments.
640 unsigned MaxAlign = MFI->getMaxAlignment();
641 if (HasBP && MaxAlign > 1)
642 assert(isPowerOf2_32(MaxAlign) && isInt<16>(MaxAlign) &&((isPowerOf2_32(MaxAlign) && isInt<16>(MaxAlign
) && "Invalid alignment!") ? static_cast<void> (
0) : __assert_fail ("isPowerOf2_32(MaxAlign) && isInt<16>(MaxAlign) && \"Invalid alignment!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn228917/lib/Target/PowerPC/PPCFrameLowering.cpp"
, 643, __PRETTY_FUNCTION__))
643 "Invalid alignment!")((isPowerOf2_32(MaxAlign) && isInt<16>(MaxAlign
) && "Invalid alignment!") ? static_cast<void> (
0) : __assert_fail ("isPowerOf2_32(MaxAlign) && isInt<16>(MaxAlign) && \"Invalid alignment!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn228917/lib/Target/PowerPC/PPCFrameLowering.cpp"
, 643, __PRETTY_FUNCTION__));
644
645 // Frames of 32KB & larger require special handling because they cannot be
646 // indexed into with a simple STDU/STWU/STD/STW immediate offset operand.
647 bool isLargeFrame = !isInt<16>(NegFrameSize);
648
649 if (MustSaveLR)
650 BuildMI(MBB, MBBI, dl, MFLRInst, ScratchReg);
651
652 assert((isPPC64 || MustSaveCRs.empty()) &&(((isPPC64 || MustSaveCRs.empty()) && "Prologue CR saving supported only in 64-bit mode"
) ? static_cast<void> (0) : __assert_fail ("(isPPC64 || MustSaveCRs.empty()) && \"Prologue CR saving supported only in 64-bit mode\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn228917/lib/Target/PowerPC/PPCFrameLowering.cpp"
, 653, __PRETTY_FUNCTION__))
653 "Prologue CR saving supported only in 64-bit mode")(((isPPC64 || MustSaveCRs.empty()) && "Prologue CR saving supported only in 64-bit mode"
) ? static_cast<void> (0) : __assert_fail ("(isPPC64 || MustSaveCRs.empty()) && \"Prologue CR saving supported only in 64-bit mode\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn228917/lib/Target/PowerPC/PPCFrameLowering.cpp"
, 653, __PRETTY_FUNCTION__));
654
655 if (!MustSaveCRs.empty()) { // will only occur for PPC64
656 // FIXME: In the ELFv2 ABI, we are not required to save all CR fields.
657 // If only one or two CR fields are clobbered, it could be more
658 // efficient to use mfocrf to selectively save just those fields.
659 MachineInstrBuilder MIB =
660 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFCR8), TempReg);
661 for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i)
662 MIB.addReg(MustSaveCRs[i], RegState::ImplicitKill);
663 }
664
665 if (HasFP)
666 // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe.
667 BuildMI(MBB, MBBI, dl, StoreInst)
668 .addReg(FPReg)
669 .addImm(FPOffset)
670 .addReg(SPReg);
671
672 if (FI->usesPICBase())
673 // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe.
674 BuildMI(MBB, MBBI, dl, StoreInst)
675 .addReg(PPC::R30)
676 .addImm(PBPOffset)
677 .addReg(SPReg);
678
679 if (HasBP)
680 // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe.
681 BuildMI(MBB, MBBI, dl, StoreInst)
682 .addReg(BPReg)
683 .addImm(BPOffset)
684 .addReg(SPReg);
685
686 if (MustSaveLR)
687 // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe.
688 BuildMI(MBB, MBBI, dl, StoreInst)
689 .addReg(ScratchReg)
690 .addImm(LROffset)
691 .addReg(SPReg);
692
693 if (!MustSaveCRs.empty()) // will only occur for PPC64
694 BuildMI(MBB, MBBI, dl, TII.get(PPC::STW8))
695 .addReg(TempReg, getKillRegState(true))
696 .addImm(8)
697 .addReg(SPReg);
698
699 // Skip the rest if this is a leaf function & all spills fit in the Red Zone.
700 if (!FrameSize) return;
701
702 // Adjust stack pointer: r1 += NegFrameSize.
703 // If there is a preferred stack alignment, align R1 now
704
705 if (HasBP) {
706 // Save a copy of r1 as the base pointer.
707 BuildMI(MBB, MBBI, dl, OrInst, BPReg)
708 .addReg(SPReg)
709 .addReg(SPReg);
710 }
711
712 if (HasBP && MaxAlign > 1) {
713 if (isPPC64)
714 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLDICL), ScratchReg)
715 .addReg(SPReg)
716 .addImm(0)
717 .addImm(64 - Log2_32(MaxAlign));
718 else // PPC32...
719 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLWINM), ScratchReg)
720 .addReg(SPReg)
721 .addImm(0)
722 .addImm(32 - Log2_32(MaxAlign))
723 .addImm(31);
724 if (!isLargeFrame) {
725 BuildMI(MBB, MBBI, dl, SubtractImmCarryingInst, ScratchReg)
726 .addReg(ScratchReg, RegState::Kill)
727 .addImm(NegFrameSize);
728 } else {
729 BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, TempReg)
730 .addImm(NegFrameSize >> 16);
731 BuildMI(MBB, MBBI, dl, OrImmInst, TempReg)
732 .addReg(TempReg, RegState::Kill)
733 .addImm(NegFrameSize & 0xFFFF);
734 BuildMI(MBB, MBBI, dl, SubtractCarryingInst, ScratchReg)
735 .addReg(ScratchReg, RegState::Kill)
736 .addReg(TempReg, RegState::Kill);
737 }
738 BuildMI(MBB, MBBI, dl, StoreUpdtIdxInst, SPReg)
739 .addReg(SPReg, RegState::Kill)
740 .addReg(SPReg)
741 .addReg(ScratchReg);
742
743 } else if (!isLargeFrame) {
744 BuildMI(MBB, MBBI, dl, StoreUpdtInst, SPReg)
745 .addReg(SPReg)
746 .addImm(NegFrameSize)
747 .addReg(SPReg);
748
749 } else {
750 BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg)
751 .addImm(NegFrameSize >> 16);
752 BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg)
753 .addReg(ScratchReg, RegState::Kill)
754 .addImm(NegFrameSize & 0xFFFF);
755 BuildMI(MBB, MBBI, dl, StoreUpdtIdxInst, SPReg)
756 .addReg(SPReg, RegState::Kill)
757 .addReg(SPReg)
758 .addReg(ScratchReg);
759 }
760
761 // Add Call Frame Information for the instructions we generated above.
762 if (needsCFI) {
763 unsigned CFIIndex;
764
765 if (HasBP) {
766 // Define CFA in terms of BP. Do this in preference to using FP/SP,
767 // because if the stack needed aligning then CFA won't be at a fixed
768 // offset from FP/SP.
769 unsigned Reg = MRI->getDwarfRegNum(BPReg, true);
770 CFIIndex = MMI.addFrameInst(
771 MCCFIInstruction::createDefCfaRegister(nullptr, Reg));
772 } else {
773 // Adjust the definition of CFA to account for the change in SP.
774 assert(NegFrameSize)((NegFrameSize) ? static_cast<void> (0) : __assert_fail
("NegFrameSize", "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn228917/lib/Target/PowerPC/PPCFrameLowering.cpp"
, 774, __PRETTY_FUNCTION__));
775 CFIIndex = MMI.addFrameInst(
776 MCCFIInstruction::createDefCfaOffset(nullptr, NegFrameSize));
777 }
778 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
779 .addCFIIndex(CFIIndex);
780
781 if (HasFP) {
782 // Describe where FP was saved, at a fixed offset from CFA.
783 unsigned Reg = MRI->getDwarfRegNum(FPReg, true);
784 CFIIndex = MMI.addFrameInst(
785 MCCFIInstruction::createOffset(nullptr, Reg, FPOffset));
786 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
787 .addCFIIndex(CFIIndex);
788 }
789
790 if (FI->usesPICBase()) {
791 // Describe where FP was saved, at a fixed offset from CFA.
792 unsigned Reg = MRI->getDwarfRegNum(PPC::R30, true);
793 CFIIndex = MMI.addFrameInst(
794 MCCFIInstruction::createOffset(nullptr, Reg, PBPOffset));
795 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
796 .addCFIIndex(CFIIndex);
797 }
798
799 if (HasBP) {
800 // Describe where BP was saved, at a fixed offset from CFA.
801 unsigned Reg = MRI->getDwarfRegNum(BPReg, true);
802 CFIIndex = MMI.addFrameInst(
803 MCCFIInstruction::createOffset(nullptr, Reg, BPOffset));
804 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
805 .addCFIIndex(CFIIndex);
806 }
807
808 if (MustSaveLR) {
809 // Describe where LR was saved, at a fixed offset from CFA.
810 unsigned Reg = MRI->getDwarfRegNum(LRReg, true);
811 CFIIndex = MMI.addFrameInst(
812 MCCFIInstruction::createOffset(nullptr, Reg, LROffset));
813 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
814 .addCFIIndex(CFIIndex);
815 }
816 }
817
818 // If there is a frame pointer, copy R1 into R31
819 if (HasFP) {
820 BuildMI(MBB, MBBI, dl, OrInst, FPReg)
821 .addReg(SPReg)
822 .addReg(SPReg);
823
824 if (!HasBP && needsCFI) {
825 // Change the definition of CFA from SP+offset to FP+offset, because SP
826 // will change at every alloca.
827 unsigned Reg = MRI->getDwarfRegNum(FPReg, true);
828 unsigned CFIIndex = MMI.addFrameInst(
829 MCCFIInstruction::createDefCfaRegister(nullptr, Reg));
830
831 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
832 .addCFIIndex(CFIIndex);
833 }
834 }
835
836 if (needsCFI) {
837 // Describe where callee saved registers were saved, at fixed offsets from
838 // CFA.
839 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
840 for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
841 unsigned Reg = CSI[I].getReg();
842 if (Reg == PPC::LR || Reg == PPC::LR8 || Reg == PPC::RM) continue;
843
844 // This is a bit of a hack: CR2LT, CR2GT, CR2EQ and CR2UN are just
845 // subregisters of CR2. We just need to emit a move of CR2.
846 if (PPC::CRBITRCRegClass.contains(Reg))
847 continue;
848
849 // For SVR4, don't emit a move for the CR spill slot if we haven't
850 // spilled CRs.
851 if (isSVR4ABI && (PPC::CR2 <= Reg && Reg <= PPC::CR4)
852 && MustSaveCRs.empty())
853 continue;
854
855 // For 64-bit SVR4 when we have spilled CRs, the spill location
856 // is SP+8, not a frame-relative slot.
857 if (isSVR4ABI && isPPC64 && (PPC::CR2 <= Reg && Reg <= PPC::CR4)) {
858 // In the ELFv1 ABI, only CR2 is noted in CFI and stands in for
859 // the whole CR word. In the ELFv2 ABI, every CR that was
860 // actually saved gets its own CFI record.
861 unsigned CRReg = isELFv2ABI? Reg : (unsigned) PPC::CR2;
862 unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
863 nullptr, MRI->getDwarfRegNum(CRReg, true), 8));
864 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
865 .addCFIIndex(CFIIndex);
866 continue;
867 }
868
869 int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
870 unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
871 nullptr, MRI->getDwarfRegNum(Reg, true), Offset));
872 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
873 .addCFIIndex(CFIIndex);
874 }
875 }
876}
877
878void PPCFrameLowering::emitEpilogue(MachineFunction &MF,
879 MachineBasicBlock &MBB) const {
880 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
881 assert(MBBI != MBB.end() && "Returning block has no terminator")((MBBI != MBB.end() && "Returning block has no terminator"
) ? static_cast<void> (0) : __assert_fail ("MBBI != MBB.end() && \"Returning block has no terminator\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn228917/lib/Target/PowerPC/PPCFrameLowering.cpp"
, 881, __PRETTY_FUNCTION__));
882 const PPCInstrInfo &TII =
883 *static_cast<const PPCInstrInfo *>(Subtarget.getInstrInfo());
884 const PPCRegisterInfo *RegInfo =
885 static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo());
886
887 unsigned RetOpcode = MBBI->getOpcode();
888 DebugLoc dl;
889
890 assert((RetOpcode == PPC::BLR ||(((RetOpcode == PPC::BLR || RetOpcode == PPC::BLR8 || RetOpcode
== PPC::TCRETURNri || RetOpcode == PPC::TCRETURNdi || RetOpcode
== PPC::TCRETURNai || RetOpcode == PPC::TCRETURNri8 || RetOpcode
== PPC::TCRETURNdi8 || RetOpcode == PPC::TCRETURNai8) &&
"Can only insert epilog into returning blocks") ? static_cast
<void> (0) : __assert_fail ("(RetOpcode == PPC::BLR || RetOpcode == PPC::BLR8 || RetOpcode == PPC::TCRETURNri || RetOpcode == PPC::TCRETURNdi || RetOpcode == PPC::TCRETURNai || RetOpcode == PPC::TCRETURNri8 || RetOpcode == PPC::TCRETURNdi8 || RetOpcode == PPC::TCRETURNai8) && \"Can only insert epilog into returning blocks\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn228917/lib/Target/PowerPC/PPCFrameLowering.cpp"
, 898, __PRETTY_FUNCTION__))
891 RetOpcode == PPC::BLR8 ||(((RetOpcode == PPC::BLR || RetOpcode == PPC::BLR8 || RetOpcode
== PPC::TCRETURNri || RetOpcode == PPC::TCRETURNdi || RetOpcode
== PPC::TCRETURNai || RetOpcode == PPC::TCRETURNri8 || RetOpcode
== PPC::TCRETURNdi8 || RetOpcode == PPC::TCRETURNai8) &&
"Can only insert epilog into returning blocks") ? static_cast
<void> (0) : __assert_fail ("(RetOpcode == PPC::BLR || RetOpcode == PPC::BLR8 || RetOpcode == PPC::TCRETURNri || RetOpcode == PPC::TCRETURNdi || RetOpcode == PPC::TCRETURNai || RetOpcode == PPC::TCRETURNri8 || RetOpcode == PPC::TCRETURNdi8 || RetOpcode == PPC::TCRETURNai8) && \"Can only insert epilog into returning blocks\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn228917/lib/Target/PowerPC/PPCFrameLowering.cpp"
, 898, __PRETTY_FUNCTION__))
892 RetOpcode == PPC::TCRETURNri ||(((RetOpcode == PPC::BLR || RetOpcode == PPC::BLR8 || RetOpcode
== PPC::TCRETURNri || RetOpcode == PPC::TCRETURNdi || RetOpcode
== PPC::TCRETURNai || RetOpcode == PPC::TCRETURNri8 || RetOpcode
== PPC::TCRETURNdi8 || RetOpcode == PPC::TCRETURNai8) &&
"Can only insert epilog into returning blocks") ? static_cast
<void> (0) : __assert_fail ("(RetOpcode == PPC::BLR || RetOpcode == PPC::BLR8 || RetOpcode == PPC::TCRETURNri || RetOpcode == PPC::TCRETURNdi || RetOpcode == PPC::TCRETURNai || RetOpcode == PPC::TCRETURNri8 || RetOpcode == PPC::TCRETURNdi8 || RetOpcode == PPC::TCRETURNai8) && \"Can only insert epilog into returning blocks\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn228917/lib/Target/PowerPC/PPCFrameLowering.cpp"
, 898, __PRETTY_FUNCTION__))
893 RetOpcode == PPC::TCRETURNdi ||(((RetOpcode == PPC::BLR || RetOpcode == PPC::BLR8 || RetOpcode
== PPC::TCRETURNri || RetOpcode == PPC::TCRETURNdi || RetOpcode
== PPC::TCRETURNai || RetOpcode == PPC::TCRETURNri8 || RetOpcode
== PPC::TCRETURNdi8 || RetOpcode == PPC::TCRETURNai8) &&
"Can only insert epilog into returning blocks") ? static_cast
<void> (0) : __assert_fail ("(RetOpcode == PPC::BLR || RetOpcode == PPC::BLR8 || RetOpcode == PPC::TCRETURNri || RetOpcode == PPC::TCRETURNdi || RetOpcode == PPC::TCRETURNai || RetOpcode == PPC::TCRETURNri8 || RetOpcode == PPC::TCRETURNdi8 || RetOpcode == PPC::TCRETURNai8) && \"Can only insert epilog into returning blocks\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn228917/lib/Target/PowerPC/PPCFrameLowering.cpp"
, 898, __PRETTY_FUNCTION__))
894 RetOpcode == PPC::TCRETURNai ||(((RetOpcode == PPC::BLR || RetOpcode == PPC::BLR8 || RetOpcode
== PPC::TCRETURNri || RetOpcode == PPC::TCRETURNdi || RetOpcode
== PPC::TCRETURNai || RetOpcode == PPC::TCRETURNri8 || RetOpcode
== PPC::TCRETURNdi8 || RetOpcode == PPC::TCRETURNai8) &&
"Can only insert epilog into returning blocks") ? static_cast
<void> (0) : __assert_fail ("(RetOpcode == PPC::BLR || RetOpcode == PPC::BLR8 || RetOpcode == PPC::TCRETURNri || RetOpcode == PPC::TCRETURNdi || RetOpcode == PPC::TCRETURNai || RetOpcode == PPC::TCRETURNri8 || RetOpcode == PPC::TCRETURNdi8 || RetOpcode == PPC::TCRETURNai8) && \"Can only insert epilog into returning blocks\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn228917/lib/Target/PowerPC/PPCFrameLowering.cpp"
, 898, __PRETTY_FUNCTION__))
895 RetOpcode == PPC::TCRETURNri8 ||(((RetOpcode == PPC::BLR || RetOpcode == PPC::BLR8 || RetOpcode
== PPC::TCRETURNri || RetOpcode == PPC::TCRETURNdi || RetOpcode
== PPC::TCRETURNai || RetOpcode == PPC::TCRETURNri8 || RetOpcode
== PPC::TCRETURNdi8 || RetOpcode == PPC::TCRETURNai8) &&
"Can only insert epilog into returning blocks") ? static_cast
<void> (0) : __assert_fail ("(RetOpcode == PPC::BLR || RetOpcode == PPC::BLR8 || RetOpcode == PPC::TCRETURNri || RetOpcode == PPC::TCRETURNdi || RetOpcode == PPC::TCRETURNai || RetOpcode == PPC::TCRETURNri8 || RetOpcode == PPC::TCRETURNdi8 || RetOpcode == PPC::TCRETURNai8) && \"Can only insert epilog into returning blocks\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn228917/lib/Target/PowerPC/PPCFrameLowering.cpp"
, 898, __PRETTY_FUNCTION__))
896 RetOpcode == PPC::TCRETURNdi8 ||(((RetOpcode == PPC::BLR || RetOpcode == PPC::BLR8 || RetOpcode
== PPC::TCRETURNri || RetOpcode == PPC::TCRETURNdi || RetOpcode
== PPC::TCRETURNai || RetOpcode == PPC::TCRETURNri8 || RetOpcode
== PPC::TCRETURNdi8 || RetOpcode == PPC::TCRETURNai8) &&
"Can only insert epilog into returning blocks") ? static_cast
<void> (0) : __assert_fail ("(RetOpcode == PPC::BLR || RetOpcode == PPC::BLR8 || RetOpcode == PPC::TCRETURNri || RetOpcode == PPC::TCRETURNdi || RetOpcode == PPC::TCRETURNai || RetOpcode == PPC::TCRETURNri8 || RetOpcode == PPC::TCRETURNdi8 || RetOpcode == PPC::TCRETURNai8) && \"Can only insert epilog into returning blocks\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn228917/lib/Target/PowerPC/PPCFrameLowering.cpp"
, 898, __PRETTY_FUNCTION__))
897 RetOpcode == PPC::TCRETURNai8) &&(((RetOpcode == PPC::BLR || RetOpcode == PPC::BLR8 || RetOpcode
== PPC::TCRETURNri || RetOpcode == PPC::TCRETURNdi || RetOpcode
== PPC::TCRETURNai || RetOpcode == PPC::TCRETURNri8 || RetOpcode
== PPC::TCRETURNdi8 || RetOpcode == PPC::TCRETURNai8) &&
"Can only insert epilog into returning blocks") ? static_cast
<void> (0) : __assert_fail ("(RetOpcode == PPC::BLR || RetOpcode == PPC::BLR8 || RetOpcode == PPC::TCRETURNri || RetOpcode == PPC::TCRETURNdi || RetOpcode == PPC::TCRETURNai || RetOpcode == PPC::TCRETURNri8 || RetOpcode == PPC::TCRETURNdi8 || RetOpcode == PPC::TCRETURNai8) && \"Can only insert epilog into returning blocks\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn228917/lib/Target/PowerPC/PPCFrameLowering.cpp"
, 898, __PRETTY_FUNCTION__))
898 "Can only insert epilog into returning blocks")(((RetOpcode == PPC::BLR || RetOpcode == PPC::BLR8 || RetOpcode
== PPC::TCRETURNri || RetOpcode == PPC::TCRETURNdi || RetOpcode
== PPC::TCRETURNai || RetOpcode == PPC::TCRETURNri8 || RetOpcode
== PPC::TCRETURNdi8 || RetOpcode == PPC::TCRETURNai8) &&
"Can only insert epilog into returning blocks") ? static_cast
<void> (0) : __assert_fail ("(RetOpcode == PPC::BLR || RetOpcode == PPC::BLR8 || RetOpcode == PPC::TCRETURNri || RetOpcode == PPC::TCRETURNdi || RetOpcode == PPC::TCRETURNai || RetOpcode == PPC::TCRETURNri8 || RetOpcode == PPC::TCRETURNdi8 || RetOpcode == PPC::TCRETURNai8) && \"Can only insert epilog into returning blocks\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn228917/lib/Target/PowerPC/PPCFrameLowering.cpp"
, 898, __PRETTY_FUNCTION__));
899
900 // Get alignment info so we know how to restore the SP.
901 const MachineFrameInfo *MFI = MF.getFrameInfo();
902
903 // Get the number of bytes allocated from the FrameInfo.
904 int FrameSize = MFI->getStackSize();
905
906 // Get processor type.
907 bool isPPC64 = Subtarget.isPPC64();
908 // Get the ABI.
909 bool isDarwinABI = Subtarget.isDarwinABI();
910 bool isSVR4ABI = Subtarget.isSVR4ABI();
911 bool isPIC = MF.getTarget().getRelocationModel() == Reloc::PIC_;
912
913 // Check if the link register (LR) has been saved.
914 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
915 bool MustSaveLR = FI->mustSaveLR();
916 const SmallVectorImpl<unsigned> &MustSaveCRs = FI->getMustSaveCRs();
917 // Do we have a frame pointer and/or base pointer for this function?
918 bool HasFP = hasFP(MF);
919 bool HasBP = RegInfo->hasBasePointer(MF);
920
921 unsigned SPReg = isPPC64 ? PPC::X1 : PPC::R1;
922 unsigned BPReg = RegInfo->getBaseRegister(MF);
923 unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31;
924 unsigned ScratchReg = isPPC64 ? PPC::X0 : PPC::R0;
925 unsigned TempReg = isPPC64 ? PPC::X12 : PPC::R12; // another scratch reg
926 const MCInstrDesc& MTLRInst = TII.get( isPPC64 ? PPC::MTLR8
927 : PPC::MTLR );
928 const MCInstrDesc& LoadInst = TII.get( isPPC64 ? PPC::LD
929 : PPC::LWZ );
930 const MCInstrDesc& LoadImmShiftedInst = TII.get( isPPC64 ? PPC::LIS8
931 : PPC::LIS );
932 const MCInstrDesc& OrImmInst = TII.get( isPPC64 ? PPC::ORI8
933 : PPC::ORI );
934 const MCInstrDesc& AddImmInst = TII.get( isPPC64 ? PPC::ADDI8
935 : PPC::ADDI );
936 const MCInstrDesc& AddInst = TII.get( isPPC64 ? PPC::ADD8
937 : PPC::ADD4 );
938
939 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI);
940
941 int FPOffset = 0;
942 if (HasFP) {
943 if (isSVR4ABI) {
944 MachineFrameInfo *FFI = MF.getFrameInfo();
945 int FPIndex = FI->getFramePointerSaveIndex();
946 assert(FPIndex && "No Frame Pointer Save Slot!")((FPIndex && "No Frame Pointer Save Slot!") ? static_cast
<void> (0) : __assert_fail ("FPIndex && \"No Frame Pointer Save Slot!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn228917/lib/Target/PowerPC/PPCFrameLowering.cpp"
, 946, __PRETTY_FUNCTION__));
947 FPOffset = FFI->getObjectOffset(FPIndex);
948 } else {
949 FPOffset =
950 PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
951 }
952 }
953
954 int BPOffset = 0;
955 if (HasBP) {
956 if (isSVR4ABI) {
957 MachineFrameInfo *FFI = MF.getFrameInfo();
958 int BPIndex = FI->getBasePointerSaveIndex();
959 assert(BPIndex && "No Base Pointer Save Slot!")((BPIndex && "No Base Pointer Save Slot!") ? static_cast
<void> (0) : __assert_fail ("BPIndex && \"No Base Pointer Save Slot!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn228917/lib/Target/PowerPC/PPCFrameLowering.cpp"
, 959, __PRETTY_FUNCTION__));
960 BPOffset = FFI->getObjectOffset(BPIndex);
961 } else {
962 BPOffset =
963 PPCFrameLowering::getBasePointerSaveOffset(isPPC64,
964 isDarwinABI,
965 isPIC);
966 }
967 }
968
969 int PBPOffset = 0;
970 if (FI->usesPICBase()) {
971 MachineFrameInfo *FFI = MF.getFrameInfo();
972 int PBPIndex = FI->getPICBasePointerSaveIndex();
973 assert(PBPIndex && "No PIC Base Pointer Save Slot!")((PBPIndex && "No PIC Base Pointer Save Slot!") ? static_cast
<void> (0) : __assert_fail ("PBPIndex && \"No PIC Base Pointer Save Slot!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn228917/lib/Target/PowerPC/PPCFrameLowering.cpp"
, 973, __PRETTY_FUNCTION__));
974 PBPOffset = FFI->getObjectOffset(PBPIndex);
975 }
976
977 bool UsesTCRet = RetOpcode == PPC::TCRETURNri ||
978 RetOpcode == PPC::TCRETURNdi ||
979 RetOpcode == PPC::TCRETURNai ||
980 RetOpcode == PPC::TCRETURNri8 ||
981 RetOpcode == PPC::TCRETURNdi8 ||
982 RetOpcode == PPC::TCRETURNai8;
983
984 if (UsesTCRet) {
985 int MaxTCRetDelta = FI->getTailCallSPDelta();
986 MachineOperand &StackAdjust = MBBI->getOperand(1);
987 assert(StackAdjust.isImm() && "Expecting immediate value.")((StackAdjust.isImm() && "Expecting immediate value."
) ? static_cast<void> (0) : __assert_fail ("StackAdjust.isImm() && \"Expecting immediate value.\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn228917/lib/Target/PowerPC/PPCFrameLowering.cpp"
, 987, __PRETTY_FUNCTION__));
988 // Adjust stack pointer.
989 int StackAdj = StackAdjust.getImm();
990 int Delta = StackAdj - MaxTCRetDelta;
991 assert((Delta >= 0) && "Delta must be positive")(((Delta >= 0) && "Delta must be positive") ? static_cast
<void> (0) : __assert_fail ("(Delta >= 0) && \"Delta must be positive\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn228917/lib/Target/PowerPC/PPCFrameLowering.cpp"
, 991, __PRETTY_FUNCTION__));
992 if (MaxTCRetDelta>0)
993 FrameSize += (StackAdj +Delta);
994 else
995 FrameSize += StackAdj;
996 }
997
998 // Frames of 32KB & larger require special handling because they cannot be
999 // indexed into with a simple LD/LWZ immediate offset operand.
1000 bool isLargeFrame = !isInt<16>(FrameSize);
1001
1002 if (FrameSize) {
1003 // In the prologue, the loaded (or persistent) stack pointer value is offset
1004 // by the STDU/STDUX/STWU/STWUX instruction. Add this offset back now.
1005
1006 // If this function contained a fastcc call and GuaranteedTailCallOpt is
1007 // enabled (=> hasFastCall()==true) the fastcc call might contain a tail
1008 // call which invalidates the stack pointer value in SP(0). So we use the
1009 // value of R31 in this case.
1010 if (FI->hasFastCall()) {
1011 assert(HasFP && "Expecting a valid frame pointer.")((HasFP && "Expecting a valid frame pointer.") ? static_cast
<void> (0) : __assert_fail ("HasFP && \"Expecting a valid frame pointer.\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn228917/lib/Target/PowerPC/PPCFrameLowering.cpp"
, 1011, __PRETTY_FUNCTION__));
1012 if (!isLargeFrame) {
1013 BuildMI(MBB, MBBI, dl, AddImmInst, SPReg)
1014 .addReg(FPReg).addImm(FrameSize);
1015 } else {
1016 BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg)
1017 .addImm(FrameSize >> 16);
1018 BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg)
1019 .addReg(ScratchReg, RegState::Kill)
1020 .addImm(FrameSize & 0xFFFF);
1021 BuildMI(MBB, MBBI, dl, AddInst)
1022 .addReg(SPReg)
1023 .addReg(FPReg)
1024 .addReg(ScratchReg);
1025 }
1026 } else if (!isLargeFrame && !HasBP && !MFI->hasVarSizedObjects()) {
1027 BuildMI(MBB, MBBI, dl, AddImmInst, SPReg)
1028 .addReg(SPReg)
1029 .addImm(FrameSize);
1030 } else {
1031 BuildMI(MBB, MBBI, dl, LoadInst, SPReg)
1032 .addImm(0)
1033 .addReg(SPReg);
1034 }
1035
1036 }
1037
1038 if (MustSaveLR)
1039 BuildMI(MBB, MBBI, dl, LoadInst, ScratchReg)
1040 .addImm(LROffset)
1041 .addReg(SPReg);
1042
1043 assert((isPPC64 || MustSaveCRs.empty()) &&(((isPPC64 || MustSaveCRs.empty()) && "Epilogue CR restoring supported only in 64-bit mode"
) ? static_cast<void> (0) : __assert_fail ("(isPPC64 || MustSaveCRs.empty()) && \"Epilogue CR restoring supported only in 64-bit mode\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn228917/lib/Target/PowerPC/PPCFrameLowering.cpp"
, 1044, __PRETTY_FUNCTION__))
1044 "Epilogue CR restoring supported only in 64-bit mode")(((isPPC64 || MustSaveCRs.empty()) && "Epilogue CR restoring supported only in 64-bit mode"
) ? static_cast<void> (0) : __assert_fail ("(isPPC64 || MustSaveCRs.empty()) && \"Epilogue CR restoring supported only in 64-bit mode\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn228917/lib/Target/PowerPC/PPCFrameLowering.cpp"
, 1044, __PRETTY_FUNCTION__));
1045
1046 if (!MustSaveCRs.empty()) // will only occur for PPC64
1047 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ8), TempReg)
1048 .addImm(8)
1049 .addReg(SPReg);
1050
1051 if (HasFP)
1052 BuildMI(MBB, MBBI, dl, LoadInst, FPReg)
1053 .addImm(FPOffset)
1054 .addReg(SPReg);
1055
1056 if (FI->usesPICBase())
1057 // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe.
1058 BuildMI(MBB, MBBI, dl, LoadInst)
1059 .addReg(PPC::R30)
1060 .addImm(PBPOffset)
1061 .addReg(SPReg);
1062
1063 if (HasBP)
1064 BuildMI(MBB, MBBI, dl, LoadInst, BPReg)
1065 .addImm(BPOffset)
1066 .addReg(SPReg);
1067
1068 if (!MustSaveCRs.empty()) // will only occur for PPC64
1069 for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i)
1070 BuildMI(MBB, MBBI, dl, TII.get(PPC::MTOCRF8), MustSaveCRs[i])
1071 .addReg(TempReg, getKillRegState(i == e-1));
1072
1073 if (MustSaveLR)
1074 BuildMI(MBB, MBBI, dl, MTLRInst).addReg(ScratchReg);
1075
1076 // Callee pop calling convention. Pop parameter/linkage area. Used for tail
1077 // call optimization
1078 if (MF.getTarget().Options.GuaranteedTailCallOpt &&
1079 (RetOpcode == PPC::BLR || RetOpcode == PPC::BLR8) &&
1080 MF.getFunction()->getCallingConv() == CallingConv::Fast) {
1081 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
1082 unsigned CallerAllocatedAmt = FI->getMinReservedArea();
1083
1084 if (CallerAllocatedAmt && isInt<16>(CallerAllocatedAmt)) {
1085 BuildMI(MBB, MBBI, dl, AddImmInst, SPReg)
1086 .addReg(SPReg).addImm(CallerAllocatedAmt);
1087 } else {
1088 BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg)
1089 .addImm(CallerAllocatedAmt >> 16);
1090 BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg)
1091 .addReg(ScratchReg, RegState::Kill)
1092 .addImm(CallerAllocatedAmt & 0xFFFF);
1093 BuildMI(MBB, MBBI, dl, AddInst)
1094 .addReg(SPReg)
1095 .addReg(FPReg)
1096 .addReg(ScratchReg);
1097 }
1098 } else if (RetOpcode == PPC::TCRETURNdi) {
1099 MBBI = MBB.getLastNonDebugInstr();
1100 MachineOperand &JumpTarget = MBBI->getOperand(0);
1101 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB)).
1102 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
1103 } else if (RetOpcode == PPC::TCRETURNri) {
1104 MBBI = MBB.getLastNonDebugInstr();
1105 assert(MBBI->getOperand(0).isReg() && "Expecting register operand.")((MBBI->getOperand(0).isReg() && "Expecting register operand."
) ? static_cast<void> (0) : __assert_fail ("MBBI->getOperand(0).isReg() && \"Expecting register operand.\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn228917/lib/Target/PowerPC/PPCFrameLowering.cpp"
, 1105, __PRETTY_FUNCTION__));
1106 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR));
1107 } else if (RetOpcode == PPC::TCRETURNai) {
1108 MBBI = MBB.getLastNonDebugInstr();
1109 MachineOperand &JumpTarget = MBBI->getOperand(0);
1110 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA)).addImm(JumpTarget.getImm());
1111 } else if (RetOpcode == PPC::TCRETURNdi8) {
1112 MBBI = MBB.getLastNonDebugInstr();
1113 MachineOperand &JumpTarget = MBBI->getOperand(0);
1114 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB8)).
1115 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
1116 } else if (RetOpcode == PPC::TCRETURNri8) {
1117 MBBI = MBB.getLastNonDebugInstr();
1118 assert(MBBI->getOperand(0).isReg() && "Expecting register operand.")((MBBI->getOperand(0).isReg() && "Expecting register operand."
) ? static_cast<void> (0) : __assert_fail ("MBBI->getOperand(0).isReg() && \"Expecting register operand.\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn228917/lib/Target/PowerPC/PPCFrameLowering.cpp"
, 1118, __PRETTY_FUNCTION__));
1119 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR8));
1120 } else if (RetOpcode == PPC::TCRETURNai8) {
1121 MBBI = MBB.getLastNonDebugInstr();
1122 MachineOperand &JumpTarget = MBBI->getOperand(0);
1123 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA8)).addImm(JumpTarget.getImm());
1124 }
1125}
1126
1127void
1128PPCFrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
1129 RegScavenger *) const {
1130 const PPCRegisterInfo *RegInfo =
1131 static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo());
1132
1133 // Save and clear the LR state.
1134 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
1135 unsigned LR = RegInfo->getRARegister();
1136 FI->setMustSaveLR(MustSaveLR(MF, LR));
1137 MachineRegisterInfo &MRI = MF.getRegInfo();
1138 MRI.setPhysRegUnused(LR);
1139
1140 // Save R31 if necessary
1141 int FPSI = FI->getFramePointerSaveIndex();
1142 bool isPPC64 = Subtarget.isPPC64();
1143 bool isDarwinABI = Subtarget.isDarwinABI();
1144 bool isPIC = MF.getTarget().getRelocationModel() == Reloc::PIC_;
1145 MachineFrameInfo *MFI = MF.getFrameInfo();
1146
1147 // If the frame pointer save index hasn't been defined yet.
1148 if (!FPSI && needsFP(MF)) {
1149 // Find out what the fix offset of the frame pointer save area.
1150 int FPOffset = getFramePointerSaveOffset(isPPC64, isDarwinABI);
1151 // Allocate the frame index for frame pointer save area.
1152 FPSI = MFI->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
1153 // Save the result.
1154 FI->setFramePointerSaveIndex(FPSI);
1155 }
1156
1157 int BPSI = FI->getBasePointerSaveIndex();
1158 if (!BPSI && RegInfo->hasBasePointer(MF)) {
1159 int BPOffset = getBasePointerSaveOffset(isPPC64, isDarwinABI, isPIC);
1160 // Allocate the frame index for the base pointer save area.
1161 BPSI = MFI->CreateFixedObject(isPPC64? 8 : 4, BPOffset, true);
1162 // Save the result.
1163 FI->setBasePointerSaveIndex(BPSI);
1164 }
1165
1166 // Reserve stack space for the PIC Base register (R30).
1167 // Only used in SVR4 32-bit.
1168 if (FI->usesPICBase()) {
1169 int PBPSI = FI->getPICBasePointerSaveIndex();
Value stored to 'PBPSI' during its initialization is never read
1170 PBPSI = MFI->CreateFixedObject(4, -8, true);
1171 FI->setPICBasePointerSaveIndex(PBPSI);
1172 }
1173
1174 // Reserve stack space to move the linkage area to in case of a tail call.
1175 int TCSPDelta = 0;
1176 if (MF.getTarget().Options.GuaranteedTailCallOpt &&
1177 (TCSPDelta = FI->getTailCallSPDelta()) < 0) {
1178 MFI->CreateFixedObject(-1 * TCSPDelta, TCSPDelta, true);
1179 }
1180
1181 // For 32-bit SVR4, allocate the nonvolatile CR spill slot iff the
1182 // function uses CR 2, 3, or 4.
1183 if (!isPPC64 && !isDarwinABI &&
1184 (MRI.isPhysRegUsed(PPC::CR2) ||
1185 MRI.isPhysRegUsed(PPC::CR3) ||
1186 MRI.isPhysRegUsed(PPC::CR4))) {
1187 int FrameIdx = MFI->CreateFixedObject((uint64_t)4, (int64_t)-4, true);
1188 FI->setCRSpillFrameIndex(FrameIdx);
1189 }
1190}
1191
1192void PPCFrameLowering::processFunctionBeforeFrameFinalized(MachineFunction &MF,
1193 RegScavenger *RS) const {
1194 // Early exit if not using the SVR4 ABI.
1195 if (!Subtarget.isSVR4ABI()) {
1196 addScavengingSpillSlot(MF, RS);
1197 return;
1198 }
1199
1200 // Get callee saved register information.
1201 MachineFrameInfo *FFI = MF.getFrameInfo();
1202 const std::vector<CalleeSavedInfo> &CSI = FFI->getCalleeSavedInfo();
1203
1204 // Early exit if no callee saved registers are modified!
1205 if (CSI.empty() && !needsFP(MF)) {
1206 addScavengingSpillSlot(MF, RS);
1207 return;
1208 }
1209
1210 unsigned MinGPR = PPC::R31;
1211 unsigned MinG8R = PPC::X31;
1212 unsigned MinFPR = PPC::F31;
1213 unsigned MinVR = PPC::V31;
1214
1215 bool HasGPSaveArea = false;
1216 bool HasG8SaveArea = false;
1217 bool HasFPSaveArea = false;
1218 bool HasVRSAVESaveArea = false;
1219 bool HasVRSaveArea = false;
1220
1221 SmallVector<CalleeSavedInfo, 18> GPRegs;
1222 SmallVector<CalleeSavedInfo, 18> G8Regs;
1223 SmallVector<CalleeSavedInfo, 18> FPRegs;
1224 SmallVector<CalleeSavedInfo, 18> VRegs;
1225
1226 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1227 unsigned Reg = CSI[i].getReg();
1228 if (PPC::GPRCRegClass.contains(Reg)) {
1229 HasGPSaveArea = true;
1230
1231 GPRegs.push_back(CSI[i]);
1232
1233 if (Reg < MinGPR) {
1234 MinGPR = Reg;
1235 }
1236 } else if (PPC::G8RCRegClass.contains(Reg)) {
1237 HasG8SaveArea = true;
1238
1239 G8Regs.push_back(CSI[i]);
1240
1241 if (Reg < MinG8R) {
1242 MinG8R = Reg;
1243 }
1244 } else if (PPC::F8RCRegClass.contains(Reg)) {
1245 HasFPSaveArea = true;
1246
1247 FPRegs.push_back(CSI[i]);
1248
1249 if (Reg < MinFPR) {
1250 MinFPR = Reg;
1251 }
1252 } else if (PPC::CRBITRCRegClass.contains(Reg) ||
1253 PPC::CRRCRegClass.contains(Reg)) {
1254 ; // do nothing, as we already know whether CRs are spilled
1255 } else if (PPC::VRSAVERCRegClass.contains(Reg)) {
1256 HasVRSAVESaveArea = true;
1257 } else if (PPC::VRRCRegClass.contains(Reg)) {
1258 HasVRSaveArea = true;
1259
1260 VRegs.push_back(CSI[i]);
1261
1262 if (Reg < MinVR) {
1263 MinVR = Reg;
1264 }
1265 } else {
1266 llvm_unreachable("Unknown RegisterClass!")::llvm::llvm_unreachable_internal("Unknown RegisterClass!", "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn228917/lib/Target/PowerPC/PPCFrameLowering.cpp"
, 1266);
1267 }
1268 }
1269
1270 PPCFunctionInfo *PFI = MF.getInfo<PPCFunctionInfo>();
1271 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
1272
1273 int64_t LowerBound = 0;
1274
1275 // Take into account stack space reserved for tail calls.
1276 int TCSPDelta = 0;
1277 if (MF.getTarget().Options.GuaranteedTailCallOpt &&
1278 (TCSPDelta = PFI->getTailCallSPDelta()) < 0) {
1279 LowerBound = TCSPDelta;
1280 }
1281
1282 // The Floating-point register save area is right below the back chain word
1283 // of the previous stack frame.
1284 if (HasFPSaveArea) {
1285 for (unsigned i = 0, e = FPRegs.size(); i != e; ++i) {
1286 int FI = FPRegs[i].getFrameIdx();
1287
1288 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1289 }
1290
1291 LowerBound -= (31 - TRI->getEncodingValue(MinFPR) + 1) * 8;
1292 }
1293
1294 // Check whether the frame pointer register is allocated. If so, make sure it
1295 // is spilled to the correct offset.
1296 if (needsFP(MF)) {
1297 HasGPSaveArea = true;
1298
1299 int FI = PFI->getFramePointerSaveIndex();
1300 assert(FI && "No Frame Pointer Save Slot!")((FI && "No Frame Pointer Save Slot!") ? static_cast<
void> (0) : __assert_fail ("FI && \"No Frame Pointer Save Slot!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn228917/lib/Target/PowerPC/PPCFrameLowering.cpp"
, 1300, __PRETTY_FUNCTION__));
1301
1302 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1303 }
1304
1305 if (PFI->usesPICBase()) {
1306 HasGPSaveArea = true;
1307
1308 int FI = PFI->getPICBasePointerSaveIndex();
1309 assert(FI && "No PIC Base Pointer Save Slot!")((FI && "No PIC Base Pointer Save Slot!") ? static_cast
<void> (0) : __assert_fail ("FI && \"No PIC Base Pointer Save Slot!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn228917/lib/Target/PowerPC/PPCFrameLowering.cpp"
, 1309, __PRETTY_FUNCTION__));
1310
1311 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1312 }
1313
1314 const PPCRegisterInfo *RegInfo =
1315 static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo());
1316 if (RegInfo->hasBasePointer(MF)) {
1317 HasGPSaveArea = true;
1318
1319 int FI = PFI->getBasePointerSaveIndex();
1320 assert(FI && "No Base Pointer Save Slot!")((FI && "No Base Pointer Save Slot!") ? static_cast<
void> (0) : __assert_fail ("FI && \"No Base Pointer Save Slot!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn228917/lib/Target/PowerPC/PPCFrameLowering.cpp"
, 1320, __PRETTY_FUNCTION__));
1321
1322 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1323 }
1324
1325 // General register save area starts right below the Floating-point
1326 // register save area.
1327 if (HasGPSaveArea || HasG8SaveArea) {
1328 // Move general register save area spill slots down, taking into account
1329 // the size of the Floating-point register save area.
1330 for (unsigned i = 0, e = GPRegs.size(); i != e; ++i) {
1331 int FI = GPRegs[i].getFrameIdx();
1332
1333 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1334 }
1335
1336 // Move general register save area spill slots down, taking into account
1337 // the size of the Floating-point register save area.
1338 for (unsigned i = 0, e = G8Regs.size(); i != e; ++i) {
1339 int FI = G8Regs[i].getFrameIdx();
1340
1341 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1342 }
1343
1344 unsigned MinReg =
1345 std::min<unsigned>(TRI->getEncodingValue(MinGPR),
1346 TRI->getEncodingValue(MinG8R));
1347
1348 if (Subtarget.isPPC64()) {
1349 LowerBound -= (31 - MinReg + 1) * 8;
1350 } else {
1351 LowerBound -= (31 - MinReg + 1) * 4;
1352 }
1353 }
1354
1355 // For 32-bit only, the CR save area is below the general register
1356 // save area. For 64-bit SVR4, the CR save area is addressed relative
1357 // to the stack pointer and hence does not need an adjustment here.
1358 // Only CR2 (the first nonvolatile spilled) has an associated frame
1359 // index so that we have a single uniform save area.
1360 if (spillsCR(MF) && !(Subtarget.isPPC64() && Subtarget.isSVR4ABI())) {
1361 // Adjust the frame index of the CR spill slot.
1362 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1363 unsigned Reg = CSI[i].getReg();
1364
1365 if ((Subtarget.isSVR4ABI() && Reg == PPC::CR2)
1366 // Leave Darwin logic as-is.
1367 || (!Subtarget.isSVR4ABI() &&
1368 (PPC::CRBITRCRegClass.contains(Reg) ||
1369 PPC::CRRCRegClass.contains(Reg)))) {
1370 int FI = CSI[i].getFrameIdx();
1371
1372 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1373 }
1374 }
1375
1376 LowerBound -= 4; // The CR save area is always 4 bytes long.
1377 }
1378
1379 if (HasVRSAVESaveArea) {
1380 // FIXME SVR4: Is it actually possible to have multiple elements in CSI
1381 // which have the VRSAVE register class?
1382 // Adjust the frame index of the VRSAVE spill slot.
1383 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1384 unsigned Reg = CSI[i].getReg();
1385
1386 if (PPC::VRSAVERCRegClass.contains(Reg)) {
1387 int FI = CSI[i].getFrameIdx();
1388
1389 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1390 }
1391 }
1392
1393 LowerBound -= 4; // The VRSAVE save area is always 4 bytes long.
1394 }
1395
1396 if (HasVRSaveArea) {
1397 // Insert alignment padding, we need 16-byte alignment.
1398 LowerBound = (LowerBound - 15) & ~(15);
1399
1400 for (unsigned i = 0, e = VRegs.size(); i != e; ++i) {
1401 int FI = VRegs[i].getFrameIdx();
1402
1403 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1404 }
1405 }
1406
1407 addScavengingSpillSlot(MF, RS);
1408}
1409
1410void
1411PPCFrameLowering::addScavengingSpillSlot(MachineFunction &MF,
1412 RegScavenger *RS) const {
1413 // Reserve a slot closest to SP or frame pointer if we have a dynalloc or
1414 // a large stack, which will require scavenging a register to materialize a
1415 // large offset.
1416
1417 // We need to have a scavenger spill slot for spills if the frame size is
1418 // large. In case there is no free register for large-offset addressing,
1419 // this slot is used for the necessary emergency spill. Also, we need the
1420 // slot for dynamic stack allocations.
1421
1422 // The scavenger might be invoked if the frame offset does not fit into
1423 // the 16-bit immediate. We don't know the complete frame size here
1424 // because we've not yet computed callee-saved register spills or the
1425 // needed alignment padding.
1426 unsigned StackSize = determineFrameLayout(MF, false, true);
1427 MachineFrameInfo *MFI = MF.getFrameInfo();
1428 if (MFI->hasVarSizedObjects() || spillsCR(MF) || spillsVRSAVE(MF) ||
1429 hasNonRISpills(MF) || (hasSpills(MF) && !isInt<16>(StackSize))) {
1430 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
1431 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
1432 const TargetRegisterClass *RC = Subtarget.isPPC64() ? G8RC : GPRC;
1433 RS->addScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
1434 RC->getAlignment(),
1435 false));
1436
1437 // Might we have over-aligned allocas?
1438 bool HasAlVars = MFI->hasVarSizedObjects() &&
1439 MFI->getMaxAlignment() > getStackAlignment();
1440
1441 // These kinds of spills might need two registers.
1442 if (spillsCR(MF) || spillsVRSAVE(MF) || HasAlVars)
1443 RS->addScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
1444 RC->getAlignment(),
1445 false));
1446
1447 }
1448}
1449
1450bool
1451PPCFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
1452 MachineBasicBlock::iterator MI,
1453 const std::vector<CalleeSavedInfo> &CSI,
1454 const TargetRegisterInfo *TRI) const {
1455
1456 // Currently, this function only handles SVR4 32- and 64-bit ABIs.
1457 // Return false otherwise to maintain pre-existing behavior.
1458 if (!Subtarget.isSVR4ABI())
1459 return false;
1460
1461 MachineFunction *MF = MBB.getParent();
1462 const PPCInstrInfo &TII =
1463 *static_cast<const PPCInstrInfo *>(Subtarget.getInstrInfo());
1464 DebugLoc DL;
1465 bool CRSpilled = false;
1466 MachineInstrBuilder CRMIB;
1467
1468 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1469 unsigned Reg = CSI[i].getReg();
1470 // Only Darwin actually uses the VRSAVE register, but it can still appear
1471 // here if, for example, @llvm.eh.unwind.init() is used. If we're not on
1472 // Darwin, ignore it.
1473 if (Reg == PPC::VRSAVE && !Subtarget.isDarwinABI())
1474 continue;
1475
1476 // CR2 through CR4 are the nonvolatile CR fields.
1477 bool IsCRField = PPC::CR2 <= Reg && Reg <= PPC::CR4;
1478
1479 // Add the callee-saved register as live-in; it's killed at the spill.
1480 MBB.addLiveIn(Reg);
1481
1482 if (CRSpilled && IsCRField) {
1483 CRMIB.addReg(Reg, RegState::ImplicitKill);
1484 continue;
1485 }
1486
1487 // Insert the spill to the stack frame.
1488 if (IsCRField) {
1489 PPCFunctionInfo *FuncInfo = MF->getInfo<PPCFunctionInfo>();
1490 if (Subtarget.isPPC64()) {
1491 // The actual spill will happen at the start of the prologue.
1492 FuncInfo->addMustSaveCR(Reg);
1493 } else {
1494 CRSpilled = true;
1495 FuncInfo->setSpillsCR();
1496
1497 // 32-bit: FP-relative. Note that we made sure CR2-CR4 all have
1498 // the same frame index in PPCRegisterInfo::hasReservedSpillSlot.
1499 CRMIB = BuildMI(*MF, DL, TII.get(PPC::MFCR), PPC::R12)
1500 .addReg(Reg, RegState::ImplicitKill);
1501
1502 MBB.insert(MI, CRMIB);
1503 MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::STW))
1504 .addReg(PPC::R12,
1505 getKillRegState(true)),
1506 CSI[i].getFrameIdx()));
1507 }
1508 } else {
1509 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1510 TII.storeRegToStackSlot(MBB, MI, Reg, true,
1511 CSI[i].getFrameIdx(), RC, TRI);
1512 }
1513 }
1514 return true;
1515}
1516
1517static void
1518restoreCRs(bool isPPC64, bool is31,
1519 bool CR2Spilled, bool CR3Spilled, bool CR4Spilled,
1520 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
1521 const std::vector<CalleeSavedInfo> &CSI, unsigned CSIIndex) {
1522
1523 MachineFunction *MF = MBB.getParent();
1524 const PPCInstrInfo &TII = *MF->getSubtarget<PPCSubtarget>().getInstrInfo();
1525 DebugLoc DL;
1526 unsigned RestoreOp, MoveReg;
1527
1528 if (isPPC64)
1529 // This is handled during epilogue generation.
1530 return;
1531 else {
1532 // 32-bit: FP-relative
1533 MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::LWZ),
1534 PPC::R12),
1535 CSI[CSIIndex].getFrameIdx()));
1536 RestoreOp = PPC::MTOCRF;
1537 MoveReg = PPC::R12;
1538 }
1539
1540 if (CR2Spilled)
1541 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR2)
1542 .addReg(MoveReg, getKillRegState(!CR3Spilled && !CR4Spilled)));
1543
1544 if (CR3Spilled)
1545 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR3)
1546 .addReg(MoveReg, getKillRegState(!CR4Spilled)));
1547
1548 if (CR4Spilled)
1549 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR4)
1550 .addReg(MoveReg, getKillRegState(true)));
1551}
1552
1553void PPCFrameLowering::
1554eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
1555 MachineBasicBlock::iterator I) const {
1556 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1557 if (MF.getTarget().Options.GuaranteedTailCallOpt &&
1558 I->getOpcode() == PPC::ADJCALLSTACKUP) {
1559 // Add (actually subtract) back the amount the callee popped on return.
1560 if (int CalleeAmt = I->getOperand(1).getImm()) {
1561 bool is64Bit = Subtarget.isPPC64();
1562 CalleeAmt *= -1;
1563 unsigned StackReg = is64Bit ? PPC::X1 : PPC::R1;
1564 unsigned TmpReg = is64Bit ? PPC::X0 : PPC::R0;
1565 unsigned ADDIInstr = is64Bit ? PPC::ADDI8 : PPC::ADDI;
1566 unsigned ADDInstr = is64Bit ? PPC::ADD8 : PPC::ADD4;
1567 unsigned LISInstr = is64Bit ? PPC::LIS8 : PPC::LIS;
1568 unsigned ORIInstr = is64Bit ? PPC::ORI8 : PPC::ORI;
1569 MachineInstr *MI = I;
1570 DebugLoc dl = MI->getDebugLoc();
1571
1572 if (isInt<16>(CalleeAmt)) {
1573 BuildMI(MBB, I, dl, TII.get(ADDIInstr), StackReg)
1574 .addReg(StackReg, RegState::Kill)
1575 .addImm(CalleeAmt);
1576 } else {
1577 MachineBasicBlock::iterator MBBI = I;
1578 BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg)
1579 .addImm(CalleeAmt >> 16);
1580 BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg)
1581 .addReg(TmpReg, RegState::Kill)
1582 .addImm(CalleeAmt & 0xFFFF);
1583 BuildMI(MBB, MBBI, dl, TII.get(ADDInstr), StackReg)
1584 .addReg(StackReg, RegState::Kill)
1585 .addReg(TmpReg);
1586 }
1587 }
1588 }
1589 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
1590 MBB.erase(I);
1591}
1592
1593bool
1594PPCFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
1595 MachineBasicBlock::iterator MI,
1596 const std::vector<CalleeSavedInfo> &CSI,
1597 const TargetRegisterInfo *TRI) const {
1598
1599 // Currently, this function only handles SVR4 32- and 64-bit ABIs.
1600 // Return false otherwise to maintain pre-existing behavior.
1601 if (!Subtarget.isSVR4ABI())
1602 return false;
1603
1604 MachineFunction *MF = MBB.getParent();
1605 const PPCInstrInfo &TII =
1606 *static_cast<const PPCInstrInfo *>(Subtarget.getInstrInfo());
1607 bool CR2Spilled = false;
1608 bool CR3Spilled = false;
1609 bool CR4Spilled = false;
1610 unsigned CSIIndex = 0;
1611
1612 // Initialize insertion-point logic; we will be restoring in reverse
1613 // order of spill.
1614 MachineBasicBlock::iterator I = MI, BeforeI = I;
1615 bool AtStart = I == MBB.begin();
1616
1617 if (!AtStart)
1618 --BeforeI;
1619
1620 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1621 unsigned Reg = CSI[i].getReg();
1622
1623 // Only Darwin actually uses the VRSAVE register, but it can still appear
1624 // here if, for example, @llvm.eh.unwind.init() is used. If we're not on
1625 // Darwin, ignore it.
1626 if (Reg == PPC::VRSAVE && !Subtarget.isDarwinABI())
1627 continue;
1628
1629 if (Reg == PPC::CR2) {
1630 CR2Spilled = true;
1631 // The spill slot is associated only with CR2, which is the
1632 // first nonvolatile spilled. Save it here.
1633 CSIIndex = i;
1634 continue;
1635 } else if (Reg == PPC::CR3) {
1636 CR3Spilled = true;
1637 continue;
1638 } else if (Reg == PPC::CR4) {
1639 CR4Spilled = true;
1640 continue;
1641 } else {
1642 // When we first encounter a non-CR register after seeing at
1643 // least one CR register, restore all spilled CRs together.
1644 if ((CR2Spilled || CR3Spilled || CR4Spilled)
1645 && !(PPC::CR2 <= Reg && Reg <= PPC::CR4)) {
1646 bool is31 = needsFP(*MF);
1647 restoreCRs(Subtarget.isPPC64(), is31,
1648 CR2Spilled, CR3Spilled, CR4Spilled,
1649 MBB, I, CSI, CSIIndex);
1650 CR2Spilled = CR3Spilled = CR4Spilled = false;
1651 }
1652
1653 // Default behavior for non-CR saves.
1654 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1655 TII.loadRegFromStackSlot(MBB, I, Reg, CSI[i].getFrameIdx(),
1656 RC, TRI);
1657 assert(I != MBB.begin() &&((I != MBB.begin() && "loadRegFromStackSlot didn't insert any code!"
) ? static_cast<void> (0) : __assert_fail ("I != MBB.begin() && \"loadRegFromStackSlot didn't insert any code!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn228917/lib/Target/PowerPC/PPCFrameLowering.cpp"
, 1658, __PRETTY_FUNCTION__))
1658 "loadRegFromStackSlot didn't insert any code!")((I != MBB.begin() && "loadRegFromStackSlot didn't insert any code!"
) ? static_cast<void> (0) : __assert_fail ("I != MBB.begin() && \"loadRegFromStackSlot didn't insert any code!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn228917/lib/Target/PowerPC/PPCFrameLowering.cpp"
, 1658, __PRETTY_FUNCTION__));
1659 }
1660
1661 // Insert in reverse order.
1662 if (AtStart)
1663 I = MBB.begin();
1664 else {
1665 I = BeforeI;
1666 ++I;
1667 }
1668 }
1669
1670 // If we haven't yet spilled the CRs, do so now.
1671 if (CR2Spilled || CR3Spilled || CR4Spilled) {
1672 bool is31 = needsFP(*MF);
1673 restoreCRs(Subtarget.isPPC64(), is31, CR2Spilled, CR3Spilled, CR4Spilled,
1674 MBB, I, CSI, CSIIndex);
1675 }
1676
1677 return true;
1678}