Bug Summary

File:lib/Target/PowerPC/PPCISelLowering.cpp
Warning:line 8623, column 31
1st function call argument is an uninitialized value

Annotated Source Code

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clang -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name PPCISelLowering.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mthread-model posix -fmath-errno -masm-verbose -mconstructor-aliases -munwind-tables -fuse-init-array -target-cpu x86-64 -dwarf-column-info -debugger-tuning=gdb -momit-leaf-frame-pointer -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-9/lib/clang/9.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-9~svn362543/build-llvm/lib/Target/PowerPC -I /build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC -I /build/llvm-toolchain-snapshot-9~svn362543/build-llvm/include -I /build/llvm-toolchain-snapshot-9~svn362543/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0/backward -internal-isystem /usr/include/clang/9.0.0/include/ -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-9/lib/clang/9.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++11 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-9~svn362543/build-llvm/lib/Target/PowerPC -fdebug-prefix-map=/build/llvm-toolchain-snapshot-9~svn362543=. -ferror-limit 19 -fmessage-length 0 -fvisibility-inlines-hidden -stack-protector 2 -fobjc-runtime=gcc -fdiagnostics-show-option -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -o /tmp/scan-build-2019-06-05-060531-1271-1 -x c++ /build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCISelLowering.cpp -faddrsig
1//===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the PPCISelLowering class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "PPCISelLowering.h"
14#include "MCTargetDesc/PPCPredicates.h"
15#include "PPC.h"
16#include "PPCCCState.h"
17#include "PPCCallingConv.h"
18#include "PPCFrameLowering.h"
19#include "PPCInstrInfo.h"
20#include "PPCMachineFunctionInfo.h"
21#include "PPCPerfectShuffle.h"
22#include "PPCRegisterInfo.h"
23#include "PPCSubtarget.h"
24#include "PPCTargetMachine.h"
25#include "llvm/ADT/APFloat.h"
26#include "llvm/ADT/APInt.h"
27#include "llvm/ADT/ArrayRef.h"
28#include "llvm/ADT/DenseMap.h"
29#include "llvm/ADT/None.h"
30#include "llvm/ADT/STLExtras.h"
31#include "llvm/ADT/SmallPtrSet.h"
32#include "llvm/ADT/SmallSet.h"
33#include "llvm/ADT/SmallVector.h"
34#include "llvm/ADT/Statistic.h"
35#include "llvm/ADT/StringRef.h"
36#include "llvm/ADT/StringSwitch.h"
37#include "llvm/CodeGen/CallingConvLower.h"
38#include "llvm/CodeGen/ISDOpcodes.h"
39#include "llvm/CodeGen/MachineBasicBlock.h"
40#include "llvm/CodeGen/MachineFrameInfo.h"
41#include "llvm/CodeGen/MachineFunction.h"
42#include "llvm/CodeGen/MachineInstr.h"
43#include "llvm/CodeGen/MachineInstrBuilder.h"
44#include "llvm/CodeGen/MachineJumpTableInfo.h"
45#include "llvm/CodeGen/MachineLoopInfo.h"
46#include "llvm/CodeGen/MachineMemOperand.h"
47#include "llvm/CodeGen/MachineOperand.h"
48#include "llvm/CodeGen/MachineRegisterInfo.h"
49#include "llvm/CodeGen/RuntimeLibcalls.h"
50#include "llvm/CodeGen/SelectionDAG.h"
51#include "llvm/CodeGen/SelectionDAGNodes.h"
52#include "llvm/CodeGen/TargetInstrInfo.h"
53#include "llvm/CodeGen/TargetLowering.h"
54#include "llvm/CodeGen/TargetRegisterInfo.h"
55#include "llvm/CodeGen/ValueTypes.h"
56#include "llvm/IR/CallSite.h"
57#include "llvm/IR/CallingConv.h"
58#include "llvm/IR/Constant.h"
59#include "llvm/IR/Constants.h"
60#include "llvm/IR/DataLayout.h"
61#include "llvm/IR/DebugLoc.h"
62#include "llvm/IR/DerivedTypes.h"
63#include "llvm/IR/Function.h"
64#include "llvm/IR/GlobalValue.h"
65#include "llvm/IR/IRBuilder.h"
66#include "llvm/IR/Instructions.h"
67#include "llvm/IR/Intrinsics.h"
68#include "llvm/IR/Module.h"
69#include "llvm/IR/Type.h"
70#include "llvm/IR/Use.h"
71#include "llvm/IR/Value.h"
72#include "llvm/MC/MCExpr.h"
73#include "llvm/MC/MCRegisterInfo.h"
74#include "llvm/Support/AtomicOrdering.h"
75#include "llvm/Support/BranchProbability.h"
76#include "llvm/Support/Casting.h"
77#include "llvm/Support/CodeGen.h"
78#include "llvm/Support/CommandLine.h"
79#include "llvm/Support/Compiler.h"
80#include "llvm/Support/Debug.h"
81#include "llvm/Support/ErrorHandling.h"
82#include "llvm/Support/Format.h"
83#include "llvm/Support/KnownBits.h"
84#include "llvm/Support/MachineValueType.h"
85#include "llvm/Support/MathExtras.h"
86#include "llvm/Support/raw_ostream.h"
87#include "llvm/Target/TargetMachine.h"
88#include "llvm/Target/TargetOptions.h"
89#include <algorithm>
90#include <cassert>
91#include <cstdint>
92#include <iterator>
93#include <list>
94#include <utility>
95#include <vector>
96
97using namespace llvm;
98
99#define DEBUG_TYPE"ppc-lowering" "ppc-lowering"
100
101static cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc",
102cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden);
103
104static cl::opt<bool> DisableILPPref("disable-ppc-ilp-pref",
105cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden);
106
107static cl::opt<bool> DisablePPCUnaligned("disable-ppc-unaligned",
108cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden);
109
110static cl::opt<bool> DisableSCO("disable-ppc-sco",
111cl::desc("disable sibling call optimization on ppc"), cl::Hidden);
112
113static cl::opt<bool> EnableQuadPrecision("enable-ppc-quad-precision",
114cl::desc("enable quad precision float support on ppc"), cl::Hidden);
115
116STATISTIC(NumTailCalls, "Number of tail calls")static llvm::Statistic NumTailCalls = {"ppc-lowering", "NumTailCalls"
, "Number of tail calls", {0}, {false}}
;
117STATISTIC(NumSiblingCalls, "Number of sibling calls")static llvm::Statistic NumSiblingCalls = {"ppc-lowering", "NumSiblingCalls"
, "Number of sibling calls", {0}, {false}}
;
118
119static bool isNByteElemShuffleMask(ShuffleVectorSDNode *, unsigned, int);
120
121static SDValue widenVec(SelectionDAG &DAG, SDValue Vec, const SDLoc &dl);
122
123// FIXME: Remove this once the bug has been fixed!
124extern cl::opt<bool> ANDIGlueBug;
125
126PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
127 const PPCSubtarget &STI)
128 : TargetLowering(TM), Subtarget(STI) {
129 // Use _setjmp/_longjmp instead of setjmp/longjmp.
130 setUseUnderscoreSetJmp(true);
131 setUseUnderscoreLongJmp(true);
132
133 // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all
134 // arguments are at least 4/8 bytes aligned.
135 bool isPPC64 = Subtarget.isPPC64();
136 setMinStackArgumentAlignment(isPPC64 ? 8:4);
137
138 // Set up the register classes.
139 addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
140 if (!useSoftFloat()) {
141 if (hasSPE()) {
142 addRegisterClass(MVT::f32, &PPC::SPE4RCRegClass);
143 addRegisterClass(MVT::f64, &PPC::SPERCRegClass);
144 } else {
145 addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
146 addRegisterClass(MVT::f64, &PPC::F8RCRegClass);
147 }
148 }
149
150 // Match BITREVERSE to customized fast code sequence in the td file.
151 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
152 setOperationAction(ISD::BITREVERSE, MVT::i64, Legal);
153
154 // Sub-word ATOMIC_CMP_SWAP need to ensure that the input is zero-extended.
155 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom);
156
157 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD.
158 for (MVT VT : MVT::integer_valuetypes()) {
159 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
160 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand);
161 }
162
163 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
164
165 // PowerPC has pre-inc load and store's.
166 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
167 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
168 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
169 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
170 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
171 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
172 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
173 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
174 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
175 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
176 if (!Subtarget.hasSPE()) {
177 setIndexedLoadAction(ISD::PRE_INC, MVT::f32, Legal);
178 setIndexedLoadAction(ISD::PRE_INC, MVT::f64, Legal);
179 setIndexedStoreAction(ISD::PRE_INC, MVT::f32, Legal);
180 setIndexedStoreAction(ISD::PRE_INC, MVT::f64, Legal);
181 }
182
183 // PowerPC uses ADDC/ADDE/SUBC/SUBE to propagate carry.
184 const MVT ScalarIntVTs[] = { MVT::i32, MVT::i64 };
185 for (MVT VT : ScalarIntVTs) {
186 setOperationAction(ISD::ADDC, VT, Legal);
187 setOperationAction(ISD::ADDE, VT, Legal);
188 setOperationAction(ISD::SUBC, VT, Legal);
189 setOperationAction(ISD::SUBE, VT, Legal);
190 }
191
192 if (Subtarget.useCRBits()) {
193 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
194
195 if (isPPC64 || Subtarget.hasFPCVT()) {
196 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote);
197 AddPromotedToType (ISD::SINT_TO_FP, MVT::i1,
198 isPPC64 ? MVT::i64 : MVT::i32);
199 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote);
200 AddPromotedToType(ISD::UINT_TO_FP, MVT::i1,
201 isPPC64 ? MVT::i64 : MVT::i32);
202 } else {
203 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Custom);
204 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Custom);
205 }
206
207 // PowerPC does not support direct load/store of condition registers.
208 setOperationAction(ISD::LOAD, MVT::i1, Custom);
209 setOperationAction(ISD::STORE, MVT::i1, Custom);
210
211 // FIXME: Remove this once the ANDI glue bug is fixed:
212 if (ANDIGlueBug)
213 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
214
215 for (MVT VT : MVT::integer_valuetypes()) {
216 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
217 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
218 setTruncStoreAction(VT, MVT::i1, Expand);
219 }
220
221 addRegisterClass(MVT::i1, &PPC::CRBITRCRegClass);
222 }
223
224 // Expand ppcf128 to i32 by hand for the benefit of llvm-gcc bootstrap on
225 // PPC (the libcall is not available).
226 setOperationAction(ISD::FP_TO_SINT, MVT::ppcf128, Custom);
227 setOperationAction(ISD::FP_TO_UINT, MVT::ppcf128, Custom);
228
229 // We do not currently implement these libm ops for PowerPC.
230 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand);
231 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand);
232 setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand);
233 setOperationAction(ISD::FRINT, MVT::ppcf128, Expand);
234 setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand);
235 setOperationAction(ISD::FREM, MVT::ppcf128, Expand);
236
237 // PowerPC has no SREM/UREM instructions unless we are on P9
238 // On P9 we may use a hardware instruction to compute the remainder.
239 // The instructions are not legalized directly because in the cases where the
240 // result of both the remainder and the division is required it is more
241 // efficient to compute the remainder from the result of the division rather
242 // than use the remainder instruction.
243 if (Subtarget.isISA3_0()) {
244 setOperationAction(ISD::SREM, MVT::i32, Custom);
245 setOperationAction(ISD::UREM, MVT::i32, Custom);
246 setOperationAction(ISD::SREM, MVT::i64, Custom);
247 setOperationAction(ISD::UREM, MVT::i64, Custom);
248 } else {
249 setOperationAction(ISD::SREM, MVT::i32, Expand);
250 setOperationAction(ISD::UREM, MVT::i32, Expand);
251 setOperationAction(ISD::SREM, MVT::i64, Expand);
252 setOperationAction(ISD::UREM, MVT::i64, Expand);
253 }
254
255 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
256 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
257 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
258 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
259 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
260 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
261 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
262 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
263 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
264
265 // We don't support sin/cos/sqrt/fmod/pow
266 setOperationAction(ISD::FSIN , MVT::f64, Expand);
267 setOperationAction(ISD::FCOS , MVT::f64, Expand);
268 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
269 setOperationAction(ISD::FREM , MVT::f64, Expand);
270 setOperationAction(ISD::FPOW , MVT::f64, Expand);
271 setOperationAction(ISD::FSIN , MVT::f32, Expand);
272 setOperationAction(ISD::FCOS , MVT::f32, Expand);
273 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
274 setOperationAction(ISD::FREM , MVT::f32, Expand);
275 setOperationAction(ISD::FPOW , MVT::f32, Expand);
276 if (Subtarget.hasSPE()) {
277 setOperationAction(ISD::FMA , MVT::f64, Expand);
278 setOperationAction(ISD::FMA , MVT::f32, Expand);
279 } else {
280 setOperationAction(ISD::FMA , MVT::f64, Legal);
281 setOperationAction(ISD::FMA , MVT::f32, Legal);
282 }
283
284 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
285
286 // If we're enabling GP optimizations, use hardware square root
287 if (!Subtarget.hasFSQRT() &&
288 !(TM.Options.UnsafeFPMath && Subtarget.hasFRSQRTE() &&
289 Subtarget.hasFRE()))
290 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
291
292 if (!Subtarget.hasFSQRT() &&
293 !(TM.Options.UnsafeFPMath && Subtarget.hasFRSQRTES() &&
294 Subtarget.hasFRES()))
295 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
296
297 if (Subtarget.hasFCPSGN()) {
298 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Legal);
299 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Legal);
300 } else {
301 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
302 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
303 }
304
305 if (Subtarget.hasFPRND()) {
306 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
307 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
308 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
309 setOperationAction(ISD::FROUND, MVT::f64, Legal);
310
311 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
312 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
313 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
314 setOperationAction(ISD::FROUND, MVT::f32, Legal);
315 }
316
317 // PowerPC does not have BSWAP, but we can use vector BSWAP instruction xxbrd
318 // to speed up scalar BSWAP64.
319 // CTPOP or CTTZ were introduced in P8/P9 respectively
320 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
321 if (Subtarget.hasP9Vector())
322 setOperationAction(ISD::BSWAP, MVT::i64 , Custom);
323 else
324 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
325 if (Subtarget.isISA3_0()) {
326 setOperationAction(ISD::CTTZ , MVT::i32 , Legal);
327 setOperationAction(ISD::CTTZ , MVT::i64 , Legal);
328 } else {
329 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
330 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
331 }
332
333 if (Subtarget.hasPOPCNTD() == PPCSubtarget::POPCNTD_Fast) {
334 setOperationAction(ISD::CTPOP, MVT::i32 , Legal);
335 setOperationAction(ISD::CTPOP, MVT::i64 , Legal);
336 } else {
337 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
338 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
339 }
340
341 // PowerPC does not have ROTR
342 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
343 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
344
345 if (!Subtarget.useCRBits()) {
346 // PowerPC does not have Select
347 setOperationAction(ISD::SELECT, MVT::i32, Expand);
348 setOperationAction(ISD::SELECT, MVT::i64, Expand);
349 setOperationAction(ISD::SELECT, MVT::f32, Expand);
350 setOperationAction(ISD::SELECT, MVT::f64, Expand);
351 }
352
353 // PowerPC wants to turn select_cc of FP into fsel when possible.
354 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
355 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
356
357 // PowerPC wants to optimize integer setcc a bit
358 if (!Subtarget.useCRBits())
359 setOperationAction(ISD::SETCC, MVT::i32, Custom);
360
361 // PowerPC does not have BRCOND which requires SetCC
362 if (!Subtarget.useCRBits())
363 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
364
365 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
366
367 if (Subtarget.hasSPE()) {
368 // SPE has built-in conversions
369 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
370 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
371 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
372 } else {
373 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
374 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
375
376 // PowerPC does not have [U|S]INT_TO_FP
377 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
378 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
379 }
380
381 if (Subtarget.hasDirectMove() && isPPC64) {
382 setOperationAction(ISD::BITCAST, MVT::f32, Legal);
383 setOperationAction(ISD::BITCAST, MVT::i32, Legal);
384 setOperationAction(ISD::BITCAST, MVT::i64, Legal);
385 setOperationAction(ISD::BITCAST, MVT::f64, Legal);
386 } else {
387 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
388 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
389 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
390 setOperationAction(ISD::BITCAST, MVT::f64, Expand);
391 }
392
393 // We cannot sextinreg(i1). Expand to shifts.
394 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
395
396 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
397 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
398 // support continuation, user-level threading, and etc.. As a result, no
399 // other SjLj exception interfaces are implemented and please don't build
400 // your own exception handling based on them.
401 // LLVM/Clang supports zero-cost DWARF exception handling.
402 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
403 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
404
405 // We want to legalize GlobalAddress and ConstantPool nodes into the
406 // appropriate instructions to materialize the address.
407 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
408 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
409 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
410 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
411 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
412 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
413 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
414 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
415 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
416 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
417
418 // TRAP is legal.
419 setOperationAction(ISD::TRAP, MVT::Other, Legal);
420
421 // TRAMPOLINE is custom lowered.
422 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
423 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
424
425 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
426 setOperationAction(ISD::VASTART , MVT::Other, Custom);
427
428 if (Subtarget.isSVR4ABI()) {
429 if (isPPC64) {
430 // VAARG always uses double-word chunks, so promote anything smaller.
431 setOperationAction(ISD::VAARG, MVT::i1, Promote);
432 AddPromotedToType (ISD::VAARG, MVT::i1, MVT::i64);
433 setOperationAction(ISD::VAARG, MVT::i8, Promote);
434 AddPromotedToType (ISD::VAARG, MVT::i8, MVT::i64);
435 setOperationAction(ISD::VAARG, MVT::i16, Promote);
436 AddPromotedToType (ISD::VAARG, MVT::i16, MVT::i64);
437 setOperationAction(ISD::VAARG, MVT::i32, Promote);
438 AddPromotedToType (ISD::VAARG, MVT::i32, MVT::i64);
439 setOperationAction(ISD::VAARG, MVT::Other, Expand);
440 } else {
441 // VAARG is custom lowered with the 32-bit SVR4 ABI.
442 setOperationAction(ISD::VAARG, MVT::Other, Custom);
443 setOperationAction(ISD::VAARG, MVT::i64, Custom);
444 }
445 } else
446 setOperationAction(ISD::VAARG, MVT::Other, Expand);
447
448 if (Subtarget.isSVR4ABI() && !isPPC64)
449 // VACOPY is custom lowered with the 32-bit SVR4 ABI.
450 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
451 else
452 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
453
454 // Use the default implementation.
455 setOperationAction(ISD::VAEND , MVT::Other, Expand);
456 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
457 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
458 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
459 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
460 setOperationAction(ISD::GET_DYNAMIC_AREA_OFFSET, MVT::i32, Custom);
461 setOperationAction(ISD::GET_DYNAMIC_AREA_OFFSET, MVT::i64, Custom);
462 setOperationAction(ISD::EH_DWARF_CFA, MVT::i32, Custom);
463 setOperationAction(ISD::EH_DWARF_CFA, MVT::i64, Custom);
464
465 // We want to custom lower some of our intrinsics.
466 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
467
468 // To handle counter-based loop conditions.
469 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i1, Custom);
470
471 setOperationAction(ISD::INTRINSIC_VOID, MVT::i8, Custom);
472 setOperationAction(ISD::INTRINSIC_VOID, MVT::i16, Custom);
473 setOperationAction(ISD::INTRINSIC_VOID, MVT::i32, Custom);
474 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
475
476 // Comparisons that require checking two conditions.
477 if (Subtarget.hasSPE()) {
478 setCondCodeAction(ISD::SETO, MVT::f32, Expand);
479 setCondCodeAction(ISD::SETO, MVT::f64, Expand);
480 setCondCodeAction(ISD::SETUO, MVT::f32, Expand);
481 setCondCodeAction(ISD::SETUO, MVT::f64, Expand);
482 }
483 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
484 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
485 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
486 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
487 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
488 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
489 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
490 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
491 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
492 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
493 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
494 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
495
496 if (Subtarget.has64BitSupport()) {
497 // They also have instructions for converting between i64 and fp.
498 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
499 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
500 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
501 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
502 // This is just the low 32 bits of a (signed) fp->i64 conversion.
503 // We cannot do this with Promote because i64 is not a legal type.
504 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
505
506 if (Subtarget.hasLFIWAX() || Subtarget.isPPC64())
507 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
508 } else {
509 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
510 if (Subtarget.hasSPE())
511 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
512 else
513 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
514 }
515
516 // With the instructions enabled under FPCVT, we can do everything.
517 if (Subtarget.hasFPCVT()) {
518 if (Subtarget.has64BitSupport()) {
519 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
520 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
521 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
522 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
523 }
524
525 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
526 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
527 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
528 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
529 }
530
531 if (Subtarget.use64BitRegs()) {
532 // 64-bit PowerPC implementations can support i64 types directly
533 addRegisterClass(MVT::i64, &PPC::G8RCRegClass);
534 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
535 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
536 // 64-bit PowerPC wants to expand i128 shifts itself.
537 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
538 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
539 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
540 } else {
541 // 32-bit PowerPC wants to expand i64 shifts itself.
542 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
543 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
544 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
545 }
546
547 if (Subtarget.hasAltivec()) {
548 // First set operation action for all vector types to expand. Then we
549 // will selectively turn on ones that can be effectively codegen'd.
550 for (MVT VT : MVT::vector_valuetypes()) {
551 // add/sub are legal for all supported vector VT's.
552 setOperationAction(ISD::ADD, VT, Legal);
553 setOperationAction(ISD::SUB, VT, Legal);
554
555 // Vector instructions introduced in P8
556 if (Subtarget.hasP8Altivec() && (VT.SimpleTy != MVT::v1i128)) {
557 setOperationAction(ISD::CTPOP, VT, Legal);
558 setOperationAction(ISD::CTLZ, VT, Legal);
559 }
560 else {
561 setOperationAction(ISD::CTPOP, VT, Expand);
562 setOperationAction(ISD::CTLZ, VT, Expand);
563 }
564
565 // Vector instructions introduced in P9
566 if (Subtarget.hasP9Altivec() && (VT.SimpleTy != MVT::v1i128))
567 setOperationAction(ISD::CTTZ, VT, Legal);
568 else
569 setOperationAction(ISD::CTTZ, VT, Expand);
570
571 // We promote all shuffles to v16i8.
572 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
573 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
574
575 // We promote all non-typed operations to v4i32.
576 setOperationAction(ISD::AND , VT, Promote);
577 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
578 setOperationAction(ISD::OR , VT, Promote);
579 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
580 setOperationAction(ISD::XOR , VT, Promote);
581 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
582 setOperationAction(ISD::LOAD , VT, Promote);
583 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
584 setOperationAction(ISD::SELECT, VT, Promote);
585 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
586 setOperationAction(ISD::VSELECT, VT, Legal);
587 setOperationAction(ISD::SELECT_CC, VT, Promote);
588 AddPromotedToType (ISD::SELECT_CC, VT, MVT::v4i32);
589 setOperationAction(ISD::STORE, VT, Promote);
590 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
591
592 // No other operations are legal.
593 setOperationAction(ISD::MUL , VT, Expand);
594 setOperationAction(ISD::SDIV, VT, Expand);
595 setOperationAction(ISD::SREM, VT, Expand);
596 setOperationAction(ISD::UDIV, VT, Expand);
597 setOperationAction(ISD::UREM, VT, Expand);
598 setOperationAction(ISD::FDIV, VT, Expand);
599 setOperationAction(ISD::FREM, VT, Expand);
600 setOperationAction(ISD::FNEG, VT, Expand);
601 setOperationAction(ISD::FSQRT, VT, Expand);
602 setOperationAction(ISD::FLOG, VT, Expand);
603 setOperationAction(ISD::FLOG10, VT, Expand);
604 setOperationAction(ISD::FLOG2, VT, Expand);
605 setOperationAction(ISD::FEXP, VT, Expand);
606 setOperationAction(ISD::FEXP2, VT, Expand);
607 setOperationAction(ISD::FSIN, VT, Expand);
608 setOperationAction(ISD::FCOS, VT, Expand);
609 setOperationAction(ISD::FABS, VT, Expand);
610 setOperationAction(ISD::FFLOOR, VT, Expand);
611 setOperationAction(ISD::FCEIL, VT, Expand);
612 setOperationAction(ISD::FTRUNC, VT, Expand);
613 setOperationAction(ISD::FRINT, VT, Expand);
614 setOperationAction(ISD::FNEARBYINT, VT, Expand);
615 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
616 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
617 setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
618 setOperationAction(ISD::MULHU, VT, Expand);
619 setOperationAction(ISD::MULHS, VT, Expand);
620 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
621 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
622 setOperationAction(ISD::UDIVREM, VT, Expand);
623 setOperationAction(ISD::SDIVREM, VT, Expand);
624 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
625 setOperationAction(ISD::FPOW, VT, Expand);
626 setOperationAction(ISD::BSWAP, VT, Expand);
627 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
628 setOperationAction(ISD::ROTL, VT, Expand);
629 setOperationAction(ISD::ROTR, VT, Expand);
630
631 for (MVT InnerVT : MVT::vector_valuetypes()) {
632 setTruncStoreAction(VT, InnerVT, Expand);
633 setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand);
634 setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand);
635 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand);
636 }
637 }
638
639 for (auto VT : {MVT::v2i64, MVT::v4i32, MVT::v8i16, MVT::v16i8})
640 setOperationAction(ISD::ABS, VT, Custom);
641
642 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
643 // with merges, splats, etc.
644 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
645
646 // Vector truncates to sub-word integer that fit in an Altivec/VSX register
647 // are cheap, so handle them before they get expanded to scalar.
648 setOperationAction(ISD::TRUNCATE, MVT::v8i8, Custom);
649 setOperationAction(ISD::TRUNCATE, MVT::v4i8, Custom);
650 setOperationAction(ISD::TRUNCATE, MVT::v2i8, Custom);
651 setOperationAction(ISD::TRUNCATE, MVT::v4i16, Custom);
652 setOperationAction(ISD::TRUNCATE, MVT::v2i16, Custom);
653
654 setOperationAction(ISD::AND , MVT::v4i32, Legal);
655 setOperationAction(ISD::OR , MVT::v4i32, Legal);
656 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
657 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
658 setOperationAction(ISD::SELECT, MVT::v4i32,
659 Subtarget.useCRBits() ? Legal : Expand);
660 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
661 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
662 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
663 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
664 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
665 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
666 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
667 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
668 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
669
670 // Without hasP8Altivec set, v2i64 SMAX isn't available.
671 // But ABS custom lowering requires SMAX support.
672 if (!Subtarget.hasP8Altivec())
673 setOperationAction(ISD::ABS, MVT::v2i64, Expand);
674
675 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
676 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass);
677 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass);
678 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass);
679
680 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
681 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
682
683 if (TM.Options.UnsafeFPMath || Subtarget.hasVSX()) {
684 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
685 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
686 }
687
688 if (Subtarget.hasP8Altivec())
689 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
690 else
691 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
692
693 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
694 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
695
696 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
697 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
698
699 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
700 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
701 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
702 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
703
704 // Altivec does not contain unordered floating-point compare instructions
705 setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand);
706 setCondCodeAction(ISD::SETUEQ, MVT::v4f32, Expand);
707 setCondCodeAction(ISD::SETO, MVT::v4f32, Expand);
708 setCondCodeAction(ISD::SETONE, MVT::v4f32, Expand);
709
710 if (Subtarget.hasVSX()) {
711 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal);
712 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal);
713 if (Subtarget.hasP8Vector()) {
714 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Legal);
715 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Legal);
716 }
717 if (Subtarget.hasDirectMove() && isPPC64) {
718 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Legal);
719 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Legal);
720 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Legal);
721 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i64, Legal);
722 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Legal);
723 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Legal);
724 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Legal);
725 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal);
726 }
727 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal);
728
729 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
730 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
731 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
732 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
733 setOperationAction(ISD::FROUND, MVT::v2f64, Legal);
734
735 setOperationAction(ISD::FROUND, MVT::v4f32, Legal);
736
737 setOperationAction(ISD::MUL, MVT::v2f64, Legal);
738 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
739
740 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
741 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
742
743 // Share the Altivec comparison restrictions.
744 setCondCodeAction(ISD::SETUO, MVT::v2f64, Expand);
745 setCondCodeAction(ISD::SETUEQ, MVT::v2f64, Expand);
746 setCondCodeAction(ISD::SETO, MVT::v2f64, Expand);
747 setCondCodeAction(ISD::SETONE, MVT::v2f64, Expand);
748
749 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
750 setOperationAction(ISD::STORE, MVT::v2f64, Legal);
751
752 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Legal);
753
754 if (Subtarget.hasP8Vector())
755 addRegisterClass(MVT::f32, &PPC::VSSRCRegClass);
756
757 addRegisterClass(MVT::f64, &PPC::VSFRCRegClass);
758
759 addRegisterClass(MVT::v4i32, &PPC::VSRCRegClass);
760 addRegisterClass(MVT::v4f32, &PPC::VSRCRegClass);
761 addRegisterClass(MVT::v2f64, &PPC::VSRCRegClass);
762
763 if (Subtarget.hasP8Altivec()) {
764 setOperationAction(ISD::SHL, MVT::v2i64, Legal);
765 setOperationAction(ISD::SRA, MVT::v2i64, Legal);
766 setOperationAction(ISD::SRL, MVT::v2i64, Legal);
767
768 // 128 bit shifts can be accomplished via 3 instructions for SHL and
769 // SRL, but not for SRA because of the instructions available:
770 // VS{RL} and VS{RL}O. However due to direct move costs, it's not worth
771 // doing
772 setOperationAction(ISD::SHL, MVT::v1i128, Expand);
773 setOperationAction(ISD::SRL, MVT::v1i128, Expand);
774 setOperationAction(ISD::SRA, MVT::v1i128, Expand);
775
776 setOperationAction(ISD::SETCC, MVT::v2i64, Legal);
777 }
778 else {
779 setOperationAction(ISD::SHL, MVT::v2i64, Expand);
780 setOperationAction(ISD::SRA, MVT::v2i64, Expand);
781 setOperationAction(ISD::SRL, MVT::v2i64, Expand);
782
783 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
784
785 // VSX v2i64 only supports non-arithmetic operations.
786 setOperationAction(ISD::ADD, MVT::v2i64, Expand);
787 setOperationAction(ISD::SUB, MVT::v2i64, Expand);
788 }
789
790 setOperationAction(ISD::LOAD, MVT::v2i64, Promote);
791 AddPromotedToType (ISD::LOAD, MVT::v2i64, MVT::v2f64);
792 setOperationAction(ISD::STORE, MVT::v2i64, Promote);
793 AddPromotedToType (ISD::STORE, MVT::v2i64, MVT::v2f64);
794
795 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Legal);
796
797 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
798 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
799 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
800 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
801
802 // Custom handling for partial vectors of integers converted to
803 // floating point. We already have optimal handling for v2i32 through
804 // the DAG combine, so those aren't necessary.
805 setOperationAction(ISD::UINT_TO_FP, MVT::v2i8, Custom);
806 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
807 setOperationAction(ISD::UINT_TO_FP, MVT::v2i16, Custom);
808 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
809 setOperationAction(ISD::SINT_TO_FP, MVT::v2i8, Custom);
810 setOperationAction(ISD::SINT_TO_FP, MVT::v4i8, Custom);
811 setOperationAction(ISD::SINT_TO_FP, MVT::v2i16, Custom);
812 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom);
813
814 setOperationAction(ISD::FNEG, MVT::v4f32, Legal);
815 setOperationAction(ISD::FNEG, MVT::v2f64, Legal);
816 setOperationAction(ISD::FABS, MVT::v4f32, Legal);
817 setOperationAction(ISD::FABS, MVT::v2f64, Legal);
818
819 if (Subtarget.hasDirectMove())
820 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
821 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
822
823 addRegisterClass(MVT::v2i64, &PPC::VSRCRegClass);
824 }
825
826 if (Subtarget.hasP8Altivec()) {
827 addRegisterClass(MVT::v2i64, &PPC::VRRCRegClass);
828 addRegisterClass(MVT::v1i128, &PPC::VRRCRegClass);
829 }
830
831 if (Subtarget.hasP9Vector()) {
832 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
833 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
834
835 // 128 bit shifts can be accomplished via 3 instructions for SHL and
836 // SRL, but not for SRA because of the instructions available:
837 // VS{RL} and VS{RL}O.
838 setOperationAction(ISD::SHL, MVT::v1i128, Legal);
839 setOperationAction(ISD::SRL, MVT::v1i128, Legal);
840 setOperationAction(ISD::SRA, MVT::v1i128, Expand);
841
842 if (EnableQuadPrecision) {
843 addRegisterClass(MVT::f128, &PPC::VRRCRegClass);
844 setOperationAction(ISD::FADD, MVT::f128, Legal);
845 setOperationAction(ISD::FSUB, MVT::f128, Legal);
846 setOperationAction(ISD::FDIV, MVT::f128, Legal);
847 setOperationAction(ISD::FMUL, MVT::f128, Legal);
848 setOperationAction(ISD::FP_EXTEND, MVT::f128, Legal);
849 // No extending loads to f128 on PPC.
850 for (MVT FPT : MVT::fp_valuetypes())
851 setLoadExtAction(ISD::EXTLOAD, MVT::f128, FPT, Expand);
852 setOperationAction(ISD::FMA, MVT::f128, Legal);
853 setCondCodeAction(ISD::SETULT, MVT::f128, Expand);
854 setCondCodeAction(ISD::SETUGT, MVT::f128, Expand);
855 setCondCodeAction(ISD::SETUEQ, MVT::f128, Expand);
856 setCondCodeAction(ISD::SETOGE, MVT::f128, Expand);
857 setCondCodeAction(ISD::SETOLE, MVT::f128, Expand);
858 setCondCodeAction(ISD::SETONE, MVT::f128, Expand);
859
860 setOperationAction(ISD::FTRUNC, MVT::f128, Legal);
861 setOperationAction(ISD::FRINT, MVT::f128, Legal);
862 setOperationAction(ISD::FFLOOR, MVT::f128, Legal);
863 setOperationAction(ISD::FCEIL, MVT::f128, Legal);
864 setOperationAction(ISD::FNEARBYINT, MVT::f128, Legal);
865 setOperationAction(ISD::FROUND, MVT::f128, Legal);
866
867 setOperationAction(ISD::SELECT, MVT::f128, Expand);
868 setOperationAction(ISD::FP_ROUND, MVT::f64, Legal);
869 setOperationAction(ISD::FP_ROUND, MVT::f32, Legal);
870 setTruncStoreAction(MVT::f128, MVT::f64, Expand);
871 setTruncStoreAction(MVT::f128, MVT::f32, Expand);
872 setOperationAction(ISD::BITCAST, MVT::i128, Custom);
873 // No implementation for these ops for PowerPC.
874 setOperationAction(ISD::FSIN , MVT::f128, Expand);
875 setOperationAction(ISD::FCOS , MVT::f128, Expand);
876 setOperationAction(ISD::FPOW, MVT::f128, Expand);
877 setOperationAction(ISD::FPOWI, MVT::f128, Expand);
878 setOperationAction(ISD::FREM, MVT::f128, Expand);
879 }
880 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
881
882 }
883
884 if (Subtarget.hasP9Altivec()) {
885 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
886 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
887 }
888 }
889
890 if (Subtarget.hasQPX()) {
891 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
892 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
893 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
894 setOperationAction(ISD::FREM, MVT::v4f64, Expand);
895
896 setOperationAction(ISD::FCOPYSIGN, MVT::v4f64, Legal);
897 setOperationAction(ISD::FGETSIGN, MVT::v4f64, Expand);
898
899 setOperationAction(ISD::LOAD , MVT::v4f64, Custom);
900 setOperationAction(ISD::STORE , MVT::v4f64, Custom);
901
902 setTruncStoreAction(MVT::v4f64, MVT::v4f32, Custom);
903 setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f32, Custom);
904
905 if (!Subtarget.useCRBits())
906 setOperationAction(ISD::SELECT, MVT::v4f64, Expand);
907 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal);
908
909 setOperationAction(ISD::EXTRACT_VECTOR_ELT , MVT::v4f64, Legal);
910 setOperationAction(ISD::INSERT_VECTOR_ELT , MVT::v4f64, Expand);
911 setOperationAction(ISD::CONCAT_VECTORS , MVT::v4f64, Expand);
912 setOperationAction(ISD::EXTRACT_SUBVECTOR , MVT::v4f64, Expand);
913 setOperationAction(ISD::VECTOR_SHUFFLE , MVT::v4f64, Custom);
914 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f64, Legal);
915 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f64, Custom);
916
917 setOperationAction(ISD::FP_TO_SINT , MVT::v4f64, Legal);
918 setOperationAction(ISD::FP_TO_UINT , MVT::v4f64, Expand);
919
920 setOperationAction(ISD::FP_ROUND , MVT::v4f32, Legal);
921 setOperationAction(ISD::FP_ROUND_INREG , MVT::v4f32, Expand);
922 setOperationAction(ISD::FP_EXTEND, MVT::v4f64, Legal);
923
924 setOperationAction(ISD::FNEG , MVT::v4f64, Legal);
925 setOperationAction(ISD::FABS , MVT::v4f64, Legal);
926 setOperationAction(ISD::FSIN , MVT::v4f64, Expand);
927 setOperationAction(ISD::FCOS , MVT::v4f64, Expand);
928 setOperationAction(ISD::FPOW , MVT::v4f64, Expand);
929 setOperationAction(ISD::FLOG , MVT::v4f64, Expand);
930 setOperationAction(ISD::FLOG2 , MVT::v4f64, Expand);
931 setOperationAction(ISD::FLOG10 , MVT::v4f64, Expand);
932 setOperationAction(ISD::FEXP , MVT::v4f64, Expand);
933 setOperationAction(ISD::FEXP2 , MVT::v4f64, Expand);
934
935 setOperationAction(ISD::FMINNUM, MVT::v4f64, Legal);
936 setOperationAction(ISD::FMAXNUM, MVT::v4f64, Legal);
937
938 setIndexedLoadAction(ISD::PRE_INC, MVT::v4f64, Legal);
939 setIndexedStoreAction(ISD::PRE_INC, MVT::v4f64, Legal);
940
941 addRegisterClass(MVT::v4f64, &PPC::QFRCRegClass);
942
943 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
944 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
945 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
946 setOperationAction(ISD::FREM, MVT::v4f32, Expand);
947
948 setOperationAction(ISD::FCOPYSIGN, MVT::v4f32, Legal);
949 setOperationAction(ISD::FGETSIGN, MVT::v4f32, Expand);
950
951 setOperationAction(ISD::LOAD , MVT::v4f32, Custom);
952 setOperationAction(ISD::STORE , MVT::v4f32, Custom);
953
954 if (!Subtarget.useCRBits())
955 setOperationAction(ISD::SELECT, MVT::v4f32, Expand);
956 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
957
958 setOperationAction(ISD::EXTRACT_VECTOR_ELT , MVT::v4f32, Legal);
959 setOperationAction(ISD::INSERT_VECTOR_ELT , MVT::v4f32, Expand);
960 setOperationAction(ISD::CONCAT_VECTORS , MVT::v4f32, Expand);
961 setOperationAction(ISD::EXTRACT_SUBVECTOR , MVT::v4f32, Expand);
962 setOperationAction(ISD::VECTOR_SHUFFLE , MVT::v4f32, Custom);
963 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Legal);
964 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
965
966 setOperationAction(ISD::FP_TO_SINT , MVT::v4f32, Legal);
967 setOperationAction(ISD::FP_TO_UINT , MVT::v4f32, Expand);
968
969 setOperationAction(ISD::FNEG , MVT::v4f32, Legal);
970 setOperationAction(ISD::FABS , MVT::v4f32, Legal);
971 setOperationAction(ISD::FSIN , MVT::v4f32, Expand);
972 setOperationAction(ISD::FCOS , MVT::v4f32, Expand);
973 setOperationAction(ISD::FPOW , MVT::v4f32, Expand);
974 setOperationAction(ISD::FLOG , MVT::v4f32, Expand);
975 setOperationAction(ISD::FLOG2 , MVT::v4f32, Expand);
976 setOperationAction(ISD::FLOG10 , MVT::v4f32, Expand);
977 setOperationAction(ISD::FEXP , MVT::v4f32, Expand);
978 setOperationAction(ISD::FEXP2 , MVT::v4f32, Expand);
979
980 setOperationAction(ISD::FMINNUM, MVT::v4f32, Legal);
981 setOperationAction(ISD::FMAXNUM, MVT::v4f32, Legal);
982
983 setIndexedLoadAction(ISD::PRE_INC, MVT::v4f32, Legal);
984 setIndexedStoreAction(ISD::PRE_INC, MVT::v4f32, Legal);
985
986 addRegisterClass(MVT::v4f32, &PPC::QSRCRegClass);
987
988 setOperationAction(ISD::AND , MVT::v4i1, Legal);
989 setOperationAction(ISD::OR , MVT::v4i1, Legal);
990 setOperationAction(ISD::XOR , MVT::v4i1, Legal);
991
992 if (!Subtarget.useCRBits())
993 setOperationAction(ISD::SELECT, MVT::v4i1, Expand);
994 setOperationAction(ISD::VSELECT, MVT::v4i1, Legal);
995
996 setOperationAction(ISD::LOAD , MVT::v4i1, Custom);
997 setOperationAction(ISD::STORE , MVT::v4i1, Custom);
998
999 setOperationAction(ISD::EXTRACT_VECTOR_ELT , MVT::v4i1, Custom);
1000 setOperationAction(ISD::INSERT_VECTOR_ELT , MVT::v4i1, Expand);
1001 setOperationAction(ISD::CONCAT_VECTORS , MVT::v4i1, Expand);
1002 setOperationAction(ISD::EXTRACT_SUBVECTOR , MVT::v4i1, Expand);
1003 setOperationAction(ISD::VECTOR_SHUFFLE , MVT::v4i1, Custom);
1004 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i1, Expand);
1005 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i1, Custom);
1006
1007 setOperationAction(ISD::SINT_TO_FP, MVT::v4i1, Custom);
1008 setOperationAction(ISD::UINT_TO_FP, MVT::v4i1, Custom);
1009
1010 addRegisterClass(MVT::v4i1, &PPC::QBRCRegClass);
1011
1012 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1013 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1014 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1015 setOperationAction(ISD::FROUND, MVT::v4f64, Legal);
1016
1017 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1018 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1019 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1020 setOperationAction(ISD::FROUND, MVT::v4f32, Legal);
1021
1022 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Expand);
1023 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Expand);
1024
1025 // These need to set FE_INEXACT, and so cannot be vectorized here.
1026 setOperationAction(ISD::FRINT, MVT::v4f64, Expand);
1027 setOperationAction(ISD::FRINT, MVT::v4f32, Expand);
1028
1029 if (TM.Options.UnsafeFPMath) {
1030 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1031 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1032
1033 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
1034 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
1035 } else {
1036 setOperationAction(ISD::FDIV, MVT::v4f64, Expand);
1037 setOperationAction(ISD::FSQRT, MVT::v4f64, Expand);
1038
1039 setOperationAction(ISD::FDIV, MVT::v4f32, Expand);
1040 setOperationAction(ISD::FSQRT, MVT::v4f32, Expand);
1041 }
1042 }
1043
1044 if (Subtarget.has64BitSupport())
1045 setOperationAction(ISD::PREFETCH, MVT::Other, Legal);
1046
1047 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, isPPC64 ? Legal : Custom);
1048
1049 if (!isPPC64) {
1050 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
1051 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
1052 }
1053
1054 setBooleanContents(ZeroOrOneBooleanContent);
1055
1056 if (Subtarget.hasAltivec()) {
1057 // Altivec instructions set fields to all zeros or all ones.
1058 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
1059 }
1060
1061 if (!isPPC64) {
1062 // These libcalls are not available in 32-bit.
1063 setLibcallName(RTLIB::SHL_I128, nullptr);
1064 setLibcallName(RTLIB::SRL_I128, nullptr);
1065 setLibcallName(RTLIB::SRA_I128, nullptr);
1066 }
1067
1068 setStackPointerRegisterToSaveRestore(isPPC64 ? PPC::X1 : PPC::R1);
1069
1070 // We have target-specific dag combine patterns for the following nodes:
1071 setTargetDAGCombine(ISD::ADD);
1072 setTargetDAGCombine(ISD::SHL);
1073 setTargetDAGCombine(ISD::SRA);
1074 setTargetDAGCombine(ISD::SRL);
1075 setTargetDAGCombine(ISD::MUL);
1076 setTargetDAGCombine(ISD::SINT_TO_FP);
1077 setTargetDAGCombine(ISD::BUILD_VECTOR);
1078 if (Subtarget.hasFPCVT())
1079 setTargetDAGCombine(ISD::UINT_TO_FP);
1080 setTargetDAGCombine(ISD::LOAD);
1081 setTargetDAGCombine(ISD::STORE);
1082 setTargetDAGCombine(ISD::BR_CC);
1083 if (Subtarget.useCRBits())
1084 setTargetDAGCombine(ISD::BRCOND);
1085 setTargetDAGCombine(ISD::BSWAP);
1086 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1087 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
1088 setTargetDAGCombine(ISD::INTRINSIC_VOID);
1089
1090 setTargetDAGCombine(ISD::SIGN_EXTEND);
1091 setTargetDAGCombine(ISD::ZERO_EXTEND);
1092 setTargetDAGCombine(ISD::ANY_EXTEND);
1093
1094 setTargetDAGCombine(ISD::TRUNCATE);
1095
1096 if (Subtarget.useCRBits()) {
1097 setTargetDAGCombine(ISD::TRUNCATE);
1098 setTargetDAGCombine(ISD::SETCC);
1099 setTargetDAGCombine(ISD::SELECT_CC);
1100 }
1101
1102 // Use reciprocal estimates.
1103 if (TM.Options.UnsafeFPMath) {
1104 setTargetDAGCombine(ISD::FDIV);
1105 setTargetDAGCombine(ISD::FSQRT);
1106 }
1107
1108 if (Subtarget.hasP9Altivec()) {
1109 setTargetDAGCombine(ISD::ABS);
1110 setTargetDAGCombine(ISD::VSELECT);
1111 }
1112
1113 // Darwin long double math library functions have $LDBL128 appended.
1114 if (Subtarget.isDarwin()) {
1115 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
1116 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
1117 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
1118 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
1119 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
1120 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128");
1121 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128");
1122 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128");
1123 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128");
1124 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128");
1125 }
1126
1127 if (EnableQuadPrecision) {
1128 setLibcallName(RTLIB::LOG_F128, "logf128");
1129 setLibcallName(RTLIB::LOG2_F128, "log2f128");
1130 setLibcallName(RTLIB::LOG10_F128, "log10f128");
1131 setLibcallName(RTLIB::EXP_F128, "expf128");
1132 setLibcallName(RTLIB::EXP2_F128, "exp2f128");
1133 setLibcallName(RTLIB::SIN_F128, "sinf128");
1134 setLibcallName(RTLIB::COS_F128, "cosf128");
1135 setLibcallName(RTLIB::POW_F128, "powf128");
1136 setLibcallName(RTLIB::FMIN_F128, "fminf128");
1137 setLibcallName(RTLIB::FMAX_F128, "fmaxf128");
1138 setLibcallName(RTLIB::POWI_F128, "__powikf2");
1139 setLibcallName(RTLIB::REM_F128, "fmodf128");
1140 }
1141
1142 // With 32 condition bits, we don't need to sink (and duplicate) compares
1143 // aggressively in CodeGenPrep.
1144 if (Subtarget.useCRBits()) {
1145 setHasMultipleConditionRegisters();
1146 setJumpIsExpensive();
1147 }
1148
1149 setMinFunctionAlignment(2);
1150 if (Subtarget.isDarwin())
1151 setPrefFunctionAlignment(4);
1152
1153 switch (Subtarget.getDarwinDirective()) {
1154 default: break;
1155 case PPC::DIR_970:
1156 case PPC::DIR_A2:
1157 case PPC::DIR_E500:
1158 case PPC::DIR_E500mc:
1159 case PPC::DIR_E5500:
1160 case PPC::DIR_PWR4:
1161 case PPC::DIR_PWR5:
1162 case PPC::DIR_PWR5X:
1163 case PPC::DIR_PWR6:
1164 case PPC::DIR_PWR6X:
1165 case PPC::DIR_PWR7:
1166 case PPC::DIR_PWR8:
1167 case PPC::DIR_PWR9:
1168 setPrefFunctionAlignment(4);
1169 setPrefLoopAlignment(4);
1170 break;
1171 }
1172
1173 if (Subtarget.enableMachineScheduler())
1174 setSchedulingPreference(Sched::Source);
1175 else
1176 setSchedulingPreference(Sched::Hybrid);
1177
1178 computeRegisterProperties(STI.getRegisterInfo());
1179
1180 // The Freescale cores do better with aggressive inlining of memcpy and
1181 // friends. GCC uses same threshold of 128 bytes (= 32 word stores).
1182 if (Subtarget.getDarwinDirective() == PPC::DIR_E500mc ||
1183 Subtarget.getDarwinDirective() == PPC::DIR_E5500) {
1184 MaxStoresPerMemset = 32;
1185 MaxStoresPerMemsetOptSize = 16;
1186 MaxStoresPerMemcpy = 32;
1187 MaxStoresPerMemcpyOptSize = 8;
1188 MaxStoresPerMemmove = 32;
1189 MaxStoresPerMemmoveOptSize = 8;
1190 } else if (Subtarget.getDarwinDirective() == PPC::DIR_A2) {
1191 // The A2 also benefits from (very) aggressive inlining of memcpy and
1192 // friends. The overhead of a the function call, even when warm, can be
1193 // over one hundred cycles.
1194 MaxStoresPerMemset = 128;
1195 MaxStoresPerMemcpy = 128;
1196 MaxStoresPerMemmove = 128;
1197 MaxLoadsPerMemcmp = 128;
1198 } else {
1199 MaxLoadsPerMemcmp = 8;
1200 MaxLoadsPerMemcmpOptSize = 4;
1201 }
1202}
1203
1204/// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1205/// the desired ByVal argument alignment.
1206static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign,
1207 unsigned MaxMaxAlign) {
1208 if (MaxAlign == MaxMaxAlign)
1209 return;
1210 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1211 if (MaxMaxAlign >= 32 && VTy->getBitWidth() >= 256)
1212 MaxAlign = 32;
1213 else if (VTy->getBitWidth() >= 128 && MaxAlign < 16)
1214 MaxAlign = 16;
1215 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1216 unsigned EltAlign = 0;
1217 getMaxByValAlign(ATy->getElementType(), EltAlign, MaxMaxAlign);
1218 if (EltAlign > MaxAlign)
1219 MaxAlign = EltAlign;
1220 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1221 for (auto *EltTy : STy->elements()) {
1222 unsigned EltAlign = 0;
1223 getMaxByValAlign(EltTy, EltAlign, MaxMaxAlign);
1224 if (EltAlign > MaxAlign)
1225 MaxAlign = EltAlign;
1226 if (MaxAlign == MaxMaxAlign)
1227 break;
1228 }
1229 }
1230}
1231
1232/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1233/// function arguments in the caller parameter area.
1234unsigned PPCTargetLowering::getByValTypeAlignment(Type *Ty,
1235 const DataLayout &DL) const {
1236 // Darwin passes everything on 4 byte boundary.
1237 if (Subtarget.isDarwin())
1238 return 4;
1239
1240 // 16byte and wider vectors are passed on 16byte boundary.
1241 // The rest is 8 on PPC64 and 4 on PPC32 boundary.
1242 unsigned Align = Subtarget.isPPC64() ? 8 : 4;
1243 if (Subtarget.hasAltivec() || Subtarget.hasQPX())
1244 getMaxByValAlign(Ty, Align, Subtarget.hasQPX() ? 32 : 16);
1245 return Align;
1246}
1247
1248unsigned PPCTargetLowering::getNumRegistersForCallingConv(LLVMContext &Context,
1249 CallingConv:: ID CC,
1250 EVT VT) const {
1251 if (Subtarget.hasSPE() && VT == MVT::f64)
1252 return 2;
1253 return PPCTargetLowering::getNumRegisters(Context, VT);
1254}
1255
1256MVT PPCTargetLowering::getRegisterTypeForCallingConv(LLVMContext &Context,
1257 CallingConv:: ID CC,
1258 EVT VT) const {
1259 if (Subtarget.hasSPE() && VT == MVT::f64)
1260 return MVT::i32;
1261 return PPCTargetLowering::getRegisterType(Context, VT);
1262}
1263
1264bool PPCTargetLowering::useSoftFloat() const {
1265 return Subtarget.useSoftFloat();
1266}
1267
1268bool PPCTargetLowering::hasSPE() const {
1269 return Subtarget.hasSPE();
1270}
1271
1272const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
1273 switch ((PPCISD::NodeType)Opcode) {
1274 case PPCISD::FIRST_NUMBER: break;
1275 case PPCISD::FSEL: return "PPCISD::FSEL";
1276 case PPCISD::FCFID: return "PPCISD::FCFID";
1277 case PPCISD::FCFIDU: return "PPCISD::FCFIDU";
1278 case PPCISD::FCFIDS: return "PPCISD::FCFIDS";
1279 case PPCISD::FCFIDUS: return "PPCISD::FCFIDUS";
1280 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
1281 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
1282 case PPCISD::FCTIDUZ: return "PPCISD::FCTIDUZ";
1283 case PPCISD::FCTIWUZ: return "PPCISD::FCTIWUZ";
1284 case PPCISD::FP_TO_UINT_IN_VSR:
1285 return "PPCISD::FP_TO_UINT_IN_VSR,";
1286 case PPCISD::FP_TO_SINT_IN_VSR:
1287 return "PPCISD::FP_TO_SINT_IN_VSR";
1288 case PPCISD::FRE: return "PPCISD::FRE";
1289 case PPCISD::FRSQRTE: return "PPCISD::FRSQRTE";
1290 case PPCISD::STFIWX: return "PPCISD::STFIWX";
1291 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
1292 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
1293 case PPCISD::VPERM: return "PPCISD::VPERM";
1294 case PPCISD::XXSPLT: return "PPCISD::XXSPLT";
1295 case PPCISD::VECINSERT: return "PPCISD::VECINSERT";
1296 case PPCISD::XXREVERSE: return "PPCISD::XXREVERSE";
1297 case PPCISD::XXPERMDI: return "PPCISD::XXPERMDI";
1298 case PPCISD::VECSHL: return "PPCISD::VECSHL";
1299 case PPCISD::CMPB: return "PPCISD::CMPB";
1300 case PPCISD::Hi: return "PPCISD::Hi";
1301 case PPCISD::Lo: return "PPCISD::Lo";
1302 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY";
1303 case PPCISD::ATOMIC_CMP_SWAP_8: return "PPCISD::ATOMIC_CMP_SWAP_8";
1304 case PPCISD::ATOMIC_CMP_SWAP_16: return "PPCISD::ATOMIC_CMP_SWAP_16";
1305 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
1306 case PPCISD::DYNAREAOFFSET: return "PPCISD::DYNAREAOFFSET";
1307 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
1308 case PPCISD::SRL: return "PPCISD::SRL";
1309 case PPCISD::SRA: return "PPCISD::SRA";
1310 case PPCISD::SHL: return "PPCISD::SHL";
1311 case PPCISD::SRA_ADDZE: return "PPCISD::SRA_ADDZE";
1312 case PPCISD::CALL: return "PPCISD::CALL";
1313 case PPCISD::CALL_NOP: return "PPCISD::CALL_NOP";
1314 case PPCISD::MTCTR: return "PPCISD::MTCTR";
1315 case PPCISD::BCTRL: return "PPCISD::BCTRL";
1316 case PPCISD::BCTRL_LOAD_TOC: return "PPCISD::BCTRL_LOAD_TOC";
1317 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
1318 case PPCISD::READ_TIME_BASE: return "PPCISD::READ_TIME_BASE";
1319 case PPCISD::EH_SJLJ_SETJMP: return "PPCISD::EH_SJLJ_SETJMP";
1320 case PPCISD::EH_SJLJ_LONGJMP: return "PPCISD::EH_SJLJ_LONGJMP";
1321 case PPCISD::MFOCRF: return "PPCISD::MFOCRF";
1322 case PPCISD::MFVSR: return "PPCISD::MFVSR";
1323 case PPCISD::MTVSRA: return "PPCISD::MTVSRA";
1324 case PPCISD::MTVSRZ: return "PPCISD::MTVSRZ";
1325 case PPCISD::SINT_VEC_TO_FP: return "PPCISD::SINT_VEC_TO_FP";
1326 case PPCISD::UINT_VEC_TO_FP: return "PPCISD::UINT_VEC_TO_FP";
1327 case PPCISD::ANDIo_1_EQ_BIT: return "PPCISD::ANDIo_1_EQ_BIT";
1328 case PPCISD::ANDIo_1_GT_BIT: return "PPCISD::ANDIo_1_GT_BIT";
1329 case PPCISD::VCMP: return "PPCISD::VCMP";
1330 case PPCISD::VCMPo: return "PPCISD::VCMPo";
1331 case PPCISD::LBRX: return "PPCISD::LBRX";
1332 case PPCISD::STBRX: return "PPCISD::STBRX";
1333 case PPCISD::LFIWAX: return "PPCISD::LFIWAX";
1334 case PPCISD::LFIWZX: return "PPCISD::LFIWZX";
1335 case PPCISD::LXSIZX: return "PPCISD::LXSIZX";
1336 case PPCISD::STXSIX: return "PPCISD::STXSIX";
1337 case PPCISD::VEXTS: return "PPCISD::VEXTS";
1338 case PPCISD::SExtVElems: return "PPCISD::SExtVElems";
1339 case PPCISD::LXVD2X: return "PPCISD::LXVD2X";
1340 case PPCISD::STXVD2X: return "PPCISD::STXVD2X";
1341 case PPCISD::ST_VSR_SCAL_INT:
1342 return "PPCISD::ST_VSR_SCAL_INT";
1343 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
1344 case PPCISD::BDNZ: return "PPCISD::BDNZ";
1345 case PPCISD::BDZ: return "PPCISD::BDZ";
1346 case PPCISD::MFFS: return "PPCISD::MFFS";
1347 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
1348 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
1349 case PPCISD::CR6SET: return "PPCISD::CR6SET";
1350 case PPCISD::CR6UNSET: return "PPCISD::CR6UNSET";
1351 case PPCISD::PPC32_GOT: return "PPCISD::PPC32_GOT";
1352 case PPCISD::PPC32_PICGOT: return "PPCISD::PPC32_PICGOT";
1353 case PPCISD::ADDIS_GOT_TPREL_HA: return "PPCISD::ADDIS_GOT_TPREL_HA";
1354 case PPCISD::LD_GOT_TPREL_L: return "PPCISD::LD_GOT_TPREL_L";
1355 case PPCISD::ADD_TLS: return "PPCISD::ADD_TLS";
1356 case PPCISD::ADDIS_TLSGD_HA: return "PPCISD::ADDIS_TLSGD_HA";
1357 case PPCISD::ADDI_TLSGD_L: return "PPCISD::ADDI_TLSGD_L";
1358 case PPCISD::GET_TLS_ADDR: return "PPCISD::GET_TLS_ADDR";
1359 case PPCISD::ADDI_TLSGD_L_ADDR: return "PPCISD::ADDI_TLSGD_L_ADDR";
1360 case PPCISD::ADDIS_TLSLD_HA: return "PPCISD::ADDIS_TLSLD_HA";
1361 case PPCISD::ADDI_TLSLD_L: return "PPCISD::ADDI_TLSLD_L";
1362 case PPCISD::GET_TLSLD_ADDR: return "PPCISD::GET_TLSLD_ADDR";
1363 case PPCISD::ADDI_TLSLD_L_ADDR: return "PPCISD::ADDI_TLSLD_L_ADDR";
1364 case PPCISD::ADDIS_DTPREL_HA: return "PPCISD::ADDIS_DTPREL_HA";
1365 case PPCISD::ADDI_DTPREL_L: return "PPCISD::ADDI_DTPREL_L";
1366 case PPCISD::VADD_SPLAT: return "PPCISD::VADD_SPLAT";
1367 case PPCISD::SC: return "PPCISD::SC";
1368 case PPCISD::CLRBHRB: return "PPCISD::CLRBHRB";
1369 case PPCISD::MFBHRBE: return "PPCISD::MFBHRBE";
1370 case PPCISD::RFEBB: return "PPCISD::RFEBB";
1371 case PPCISD::XXSWAPD: return "PPCISD::XXSWAPD";
1372 case PPCISD::SWAP_NO_CHAIN: return "PPCISD::SWAP_NO_CHAIN";
1373 case PPCISD::VABSD: return "PPCISD::VABSD";
1374 case PPCISD::QVFPERM: return "PPCISD::QVFPERM";
1375 case PPCISD::QVGPCI: return "PPCISD::QVGPCI";
1376 case PPCISD::QVALIGNI: return "PPCISD::QVALIGNI";
1377 case PPCISD::QVESPLATI: return "PPCISD::QVESPLATI";
1378 case PPCISD::QBFLT: return "PPCISD::QBFLT";
1379 case PPCISD::QVLFSb: return "PPCISD::QVLFSb";
1380 case PPCISD::BUILD_FP128: return "PPCISD::BUILD_FP128";
1381 case PPCISD::EXTSWSLI: return "PPCISD::EXTSWSLI";
1382 case PPCISD::LD_VSX_LH: return "PPCISD::LD_VSX_LH";
1383 case PPCISD::FP_EXTEND_LH: return "PPCISD::FP_EXTEND_LH";
1384 }
1385 return nullptr;
1386}
1387
1388EVT PPCTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &C,
1389 EVT VT) const {
1390 if (!VT.isVector())
1391 return Subtarget.useCRBits() ? MVT::i1 : MVT::i32;
1392
1393 if (Subtarget.hasQPX())
1394 return EVT::getVectorVT(C, MVT::i1, VT.getVectorNumElements());
1395
1396 return VT.changeVectorElementTypeToInteger();
1397}
1398
1399bool PPCTargetLowering::enableAggressiveFMAFusion(EVT VT) const {
1400 assert(VT.isFloatingPoint() && "Non-floating-point FMA?")((VT.isFloatingPoint() && "Non-floating-point FMA?") ?
static_cast<void> (0) : __assert_fail ("VT.isFloatingPoint() && \"Non-floating-point FMA?\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCISelLowering.cpp"
, 1400, __PRETTY_FUNCTION__))
;
1401 return true;
1402}
1403
1404//===----------------------------------------------------------------------===//
1405// Node matching predicates, for use by the tblgen matching code.
1406//===----------------------------------------------------------------------===//
1407
1408/// isFloatingPointZero - Return true if this is 0.0 or -0.0.
1409static bool isFloatingPointZero(SDValue Op) {
1410 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
1411 return CFP->getValueAPF().isZero();
1412 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
1413 // Maybe this has already been legalized into the constant pool?
1414 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
1415 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
1416 return CFP->getValueAPF().isZero();
1417 }
1418 return false;
1419}
1420
1421/// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
1422/// true if Op is undef or if it matches the specified value.
1423static bool isConstantOrUndef(int Op, int Val) {
1424 return Op < 0 || Op == Val;
1425}
1426
1427/// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
1428/// VPKUHUM instruction.
1429/// The ShuffleKind distinguishes between big-endian operations with
1430/// two different inputs (0), either-endian operations with two identical
1431/// inputs (1), and little-endian operations with two different inputs (2).
1432/// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
1433bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
1434 SelectionDAG &DAG) {
1435 bool IsLE = DAG.getDataLayout().isLittleEndian();
1436 if (ShuffleKind == 0) {
1437 if (IsLE)
1438 return false;
1439 for (unsigned i = 0; i != 16; ++i)
1440 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1))
1441 return false;
1442 } else if (ShuffleKind == 2) {
1443 if (!IsLE)
1444 return false;
1445 for (unsigned i = 0; i != 16; ++i)
1446 if (!isConstantOrUndef(N->getMaskElt(i), i*2))
1447 return false;
1448 } else if (ShuffleKind == 1) {
1449 unsigned j = IsLE ? 0 : 1;
1450 for (unsigned i = 0; i != 8; ++i)
1451 if (!isConstantOrUndef(N->getMaskElt(i), i*2+j) ||
1452 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j))
1453 return false;
1454 }
1455 return true;
1456}
1457
1458/// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
1459/// VPKUWUM instruction.
1460/// The ShuffleKind distinguishes between big-endian operations with
1461/// two different inputs (0), either-endian operations with two identical
1462/// inputs (1), and little-endian operations with two different inputs (2).
1463/// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
1464bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
1465 SelectionDAG &DAG) {
1466 bool IsLE = DAG.getDataLayout().isLittleEndian();
1467 if (ShuffleKind == 0) {
1468 if (IsLE)
1469 return false;
1470 for (unsigned i = 0; i != 16; i += 2)
1471 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
1472 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3))
1473 return false;
1474 } else if (ShuffleKind == 2) {
1475 if (!IsLE)
1476 return false;
1477 for (unsigned i = 0; i != 16; i += 2)
1478 if (!isConstantOrUndef(N->getMaskElt(i ), i*2) ||
1479 !isConstantOrUndef(N->getMaskElt(i+1), i*2+1))
1480 return false;
1481 } else if (ShuffleKind == 1) {
1482 unsigned j = IsLE ? 0 : 2;
1483 for (unsigned i = 0; i != 8; i += 2)
1484 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
1485 !isConstantOrUndef(N->getMaskElt(i+1), i*2+j+1) ||
1486 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j) ||
1487 !isConstantOrUndef(N->getMaskElt(i+9), i*2+j+1))
1488 return false;
1489 }
1490 return true;
1491}
1492
1493/// isVPKUDUMShuffleMask - Return true if this is the shuffle mask for a
1494/// VPKUDUM instruction, AND the VPKUDUM instruction exists for the
1495/// current subtarget.
1496///
1497/// The ShuffleKind distinguishes between big-endian operations with
1498/// two different inputs (0), either-endian operations with two identical
1499/// inputs (1), and little-endian operations with two different inputs (2).
1500/// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
1501bool PPC::isVPKUDUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
1502 SelectionDAG &DAG) {
1503 const PPCSubtarget& Subtarget =
1504 static_cast<const PPCSubtarget&>(DAG.getSubtarget());
1505 if (!Subtarget.hasP8Vector())
1506 return false;
1507
1508 bool IsLE = DAG.getDataLayout().isLittleEndian();
1509 if (ShuffleKind == 0) {
1510 if (IsLE)
1511 return false;
1512 for (unsigned i = 0; i != 16; i += 4)
1513 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+4) ||
1514 !isConstantOrUndef(N->getMaskElt(i+1), i*2+5) ||
1515 !isConstantOrUndef(N->getMaskElt(i+2), i*2+6) ||
1516 !isConstantOrUndef(N->getMaskElt(i+3), i*2+7))
1517 return false;
1518 } else if (ShuffleKind == 2) {
1519 if (!IsLE)
1520 return false;
1521 for (unsigned i = 0; i != 16; i += 4)
1522 if (!isConstantOrUndef(N->getMaskElt(i ), i*2) ||
1523 !isConstantOrUndef(N->getMaskElt(i+1), i*2+1) ||
1524 !isConstantOrUndef(N->getMaskElt(i+2), i*2+2) ||
1525 !isConstantOrUndef(N->getMaskElt(i+3), i*2+3))
1526 return false;
1527 } else if (ShuffleKind == 1) {
1528 unsigned j = IsLE ? 0 : 4;
1529 for (unsigned i = 0; i != 8; i += 4)
1530 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
1531 !isConstantOrUndef(N->getMaskElt(i+1), i*2+j+1) ||
1532 !isConstantOrUndef(N->getMaskElt(i+2), i*2+j+2) ||
1533 !isConstantOrUndef(N->getMaskElt(i+3), i*2+j+3) ||
1534 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j) ||
1535 !isConstantOrUndef(N->getMaskElt(i+9), i*2+j+1) ||
1536 !isConstantOrUndef(N->getMaskElt(i+10), i*2+j+2) ||
1537 !isConstantOrUndef(N->getMaskElt(i+11), i*2+j+3))
1538 return false;
1539 }
1540 return true;
1541}
1542
1543/// isVMerge - Common function, used to match vmrg* shuffles.
1544///
1545static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
1546 unsigned LHSStart, unsigned RHSStart) {
1547 if (N->getValueType(0) != MVT::v16i8)
1548 return false;
1549 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&(((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
"Unsupported merge size!") ? static_cast<void> (0) : __assert_fail
("(UnitSize == 1 || UnitSize == 2 || UnitSize == 4) && \"Unsupported merge size!\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCISelLowering.cpp"
, 1550, __PRETTY_FUNCTION__))
1550 "Unsupported merge size!")(((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
"Unsupported merge size!") ? static_cast<void> (0) : __assert_fail
("(UnitSize == 1 || UnitSize == 2 || UnitSize == 4) && \"Unsupported merge size!\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCISelLowering.cpp"
, 1550, __PRETTY_FUNCTION__))
;
1551
1552 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
1553 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
1554 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j),
1555 LHSStart+j+i*UnitSize) ||
1556 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j),
1557 RHSStart+j+i*UnitSize))
1558 return false;
1559 }
1560 return true;
1561}
1562
1563/// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
1564/// a VMRGL* instruction with the specified unit size (1,2 or 4 bytes).
1565/// The ShuffleKind distinguishes between big-endian merges with two
1566/// different inputs (0), either-endian merges with two identical inputs (1),
1567/// and little-endian merges with two different inputs (2). For the latter,
1568/// the input operands are swapped (see PPCInstrAltivec.td).
1569bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
1570 unsigned ShuffleKind, SelectionDAG &DAG) {
1571 if (DAG.getDataLayout().isLittleEndian()) {
1572 if (ShuffleKind == 1) // unary
1573 return isVMerge(N, UnitSize, 0, 0);
1574 else if (ShuffleKind == 2) // swapped
1575 return isVMerge(N, UnitSize, 0, 16);
1576 else
1577 return false;
1578 } else {
1579 if (ShuffleKind == 1) // unary
1580 return isVMerge(N, UnitSize, 8, 8);
1581 else if (ShuffleKind == 0) // normal
1582 return isVMerge(N, UnitSize, 8, 24);
1583 else
1584 return false;
1585 }
1586}
1587
1588/// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
1589/// a VMRGH* instruction with the specified unit size (1,2 or 4 bytes).
1590/// The ShuffleKind distinguishes between big-endian merges with two
1591/// different inputs (0), either-endian merges with two identical inputs (1),
1592/// and little-endian merges with two different inputs (2). For the latter,
1593/// the input operands are swapped (see PPCInstrAltivec.td).
1594bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
1595 unsigned ShuffleKind, SelectionDAG &DAG) {
1596 if (DAG.getDataLayout().isLittleEndian()) {
1597 if (ShuffleKind == 1) // unary
1598 return isVMerge(N, UnitSize, 8, 8);
1599 else if (ShuffleKind == 2) // swapped
1600 return isVMerge(N, UnitSize, 8, 24);
1601 else
1602 return false;
1603 } else {
1604 if (ShuffleKind == 1) // unary
1605 return isVMerge(N, UnitSize, 0, 0);
1606 else if (ShuffleKind == 0) // normal
1607 return isVMerge(N, UnitSize, 0, 16);
1608 else
1609 return false;
1610 }
1611}
1612
1613/**
1614 * Common function used to match vmrgew and vmrgow shuffles
1615 *
1616 * The indexOffset determines whether to look for even or odd words in
1617 * the shuffle mask. This is based on the of the endianness of the target
1618 * machine.
1619 * - Little Endian:
1620 * - Use offset of 0 to check for odd elements
1621 * - Use offset of 4 to check for even elements
1622 * - Big Endian:
1623 * - Use offset of 0 to check for even elements
1624 * - Use offset of 4 to check for odd elements
1625 * A detailed description of the vector element ordering for little endian and
1626 * big endian can be found at
1627 * http://www.ibm.com/developerworks/library/l-ibm-xl-c-cpp-compiler/index.html
1628 * Targeting your applications - what little endian and big endian IBM XL C/C++
1629 * compiler differences mean to you
1630 *
1631 * The mask to the shuffle vector instruction specifies the indices of the
1632 * elements from the two input vectors to place in the result. The elements are
1633 * numbered in array-access order, starting with the first vector. These vectors
1634 * are always of type v16i8, thus each vector will contain 16 elements of size
1635 * 8. More info on the shuffle vector can be found in the
1636 * http://llvm.org/docs/LangRef.html#shufflevector-instruction
1637 * Language Reference.
1638 *
1639 * The RHSStartValue indicates whether the same input vectors are used (unary)
1640 * or two different input vectors are used, based on the following:
1641 * - If the instruction uses the same vector for both inputs, the range of the
1642 * indices will be 0 to 15. In this case, the RHSStart value passed should
1643 * be 0.
1644 * - If the instruction has two different vectors then the range of the
1645 * indices will be 0 to 31. In this case, the RHSStart value passed should
1646 * be 16 (indices 0-15 specify elements in the first vector while indices 16
1647 * to 31 specify elements in the second vector).
1648 *
1649 * \param[in] N The shuffle vector SD Node to analyze
1650 * \param[in] IndexOffset Specifies whether to look for even or odd elements
1651 * \param[in] RHSStartValue Specifies the starting index for the righthand input
1652 * vector to the shuffle_vector instruction
1653 * \return true iff this shuffle vector represents an even or odd word merge
1654 */
1655static bool isVMerge(ShuffleVectorSDNode *N, unsigned IndexOffset,
1656 unsigned RHSStartValue) {
1657 if (N->getValueType(0) != MVT::v16i8)
1658 return false;
1659
1660 for (unsigned i = 0; i < 2; ++i)
1661 for (unsigned j = 0; j < 4; ++j)
1662 if (!isConstantOrUndef(N->getMaskElt(i*4+j),
1663 i*RHSStartValue+j+IndexOffset) ||
1664 !isConstantOrUndef(N->getMaskElt(i*4+j+8),
1665 i*RHSStartValue+j+IndexOffset+8))
1666 return false;
1667 return true;
1668}
1669
1670/**
1671 * Determine if the specified shuffle mask is suitable for the vmrgew or
1672 * vmrgow instructions.
1673 *
1674 * \param[in] N The shuffle vector SD Node to analyze
1675 * \param[in] CheckEven Check for an even merge (true) or an odd merge (false)
1676 * \param[in] ShuffleKind Identify the type of merge:
1677 * - 0 = big-endian merge with two different inputs;
1678 * - 1 = either-endian merge with two identical inputs;
1679 * - 2 = little-endian merge with two different inputs (inputs are swapped for
1680 * little-endian merges).
1681 * \param[in] DAG The current SelectionDAG
1682 * \return true iff this shuffle mask
1683 */
1684bool PPC::isVMRGEOShuffleMask(ShuffleVectorSDNode *N, bool CheckEven,
1685 unsigned ShuffleKind, SelectionDAG &DAG) {
1686 if (DAG.getDataLayout().isLittleEndian()) {
1687 unsigned indexOffset = CheckEven ? 4 : 0;
1688 if (ShuffleKind == 1) // Unary
1689 return isVMerge(N, indexOffset, 0);
1690 else if (ShuffleKind == 2) // swapped
1691 return isVMerge(N, indexOffset, 16);
1692 else
1693 return false;
1694 }
1695 else {
1696 unsigned indexOffset = CheckEven ? 0 : 4;
1697 if (ShuffleKind == 1) // Unary
1698 return isVMerge(N, indexOffset, 0);
1699 else if (ShuffleKind == 0) // Normal
1700 return isVMerge(N, indexOffset, 16);
1701 else
1702 return false;
1703 }
1704 return false;
1705}
1706
1707/// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
1708/// amount, otherwise return -1.
1709/// The ShuffleKind distinguishes between big-endian operations with two
1710/// different inputs (0), either-endian operations with two identical inputs
1711/// (1), and little-endian operations with two different inputs (2). For the
1712/// latter, the input operands are swapped (see PPCInstrAltivec.td).
1713int PPC::isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind,
1714 SelectionDAG &DAG) {
1715 if (N->getValueType(0) != MVT::v16i8)
1716 return -1;
1717
1718 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1719
1720 // Find the first non-undef value in the shuffle mask.
1721 unsigned i;
1722 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i)
1723 /*search*/;
1724
1725 if (i == 16) return -1; // all undef.
1726
1727 // Otherwise, check to see if the rest of the elements are consecutively
1728 // numbered from this value.
1729 unsigned ShiftAmt = SVOp->getMaskElt(i);
1730 if (ShiftAmt < i) return -1;
1731
1732 ShiftAmt -= i;
1733 bool isLE = DAG.getDataLayout().isLittleEndian();
1734
1735 if ((ShuffleKind == 0 && !isLE) || (ShuffleKind == 2 && isLE)) {
1736 // Check the rest of the elements to see if they are consecutive.
1737 for (++i; i != 16; ++i)
1738 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
1739 return -1;
1740 } else if (ShuffleKind == 1) {
1741 // Check the rest of the elements to see if they are consecutive.
1742 for (++i; i != 16; ++i)
1743 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
1744 return -1;
1745 } else
1746 return -1;
1747
1748 if (isLE)
1749 ShiftAmt = 16 - ShiftAmt;
1750
1751 return ShiftAmt;
1752}
1753
1754/// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
1755/// specifies a splat of a single element that is suitable for input to
1756/// VSPLTB/VSPLTH/VSPLTW.
1757bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) {
1758 assert(N->getValueType(0) == MVT::v16i8 &&((N->getValueType(0) == MVT::v16i8 && (EltSize == 1
|| EltSize == 2 || EltSize == 4)) ? static_cast<void> (
0) : __assert_fail ("N->getValueType(0) == MVT::v16i8 && (EltSize == 1 || EltSize == 2 || EltSize == 4)"
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCISelLowering.cpp"
, 1759, __PRETTY_FUNCTION__))
1759 (EltSize == 1 || EltSize == 2 || EltSize == 4))((N->getValueType(0) == MVT::v16i8 && (EltSize == 1
|| EltSize == 2 || EltSize == 4)) ? static_cast<void> (
0) : __assert_fail ("N->getValueType(0) == MVT::v16i8 && (EltSize == 1 || EltSize == 2 || EltSize == 4)"
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCISelLowering.cpp"
, 1759, __PRETTY_FUNCTION__))
;
1760
1761 // The consecutive indices need to specify an element, not part of two
1762 // different elements. So abandon ship early if this isn't the case.
1763 if (N->getMaskElt(0) % EltSize != 0)
1764 return false;
1765
1766 // This is a splat operation if each element of the permute is the same, and
1767 // if the value doesn't reference the second vector.
1768 unsigned ElementBase = N->getMaskElt(0);
1769
1770 // FIXME: Handle UNDEF elements too!
1771 if (ElementBase >= 16)
1772 return false;
1773
1774 // Check that the indices are consecutive, in the case of a multi-byte element
1775 // splatted with a v16i8 mask.
1776 for (unsigned i = 1; i != EltSize; ++i)
1777 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase))
1778 return false;
1779
1780 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
1781 if (N->getMaskElt(i) < 0) continue;
1782 for (unsigned j = 0; j != EltSize; ++j)
1783 if (N->getMaskElt(i+j) != N->getMaskElt(j))
1784 return false;
1785 }
1786 return true;
1787}
1788
1789/// Check that the mask is shuffling N byte elements. Within each N byte
1790/// element of the mask, the indices could be either in increasing or
1791/// decreasing order as long as they are consecutive.
1792/// \param[in] N the shuffle vector SD Node to analyze
1793/// \param[in] Width the element width in bytes, could be 2/4/8/16 (HalfWord/
1794/// Word/DoubleWord/QuadWord).
1795/// \param[in] StepLen the delta indices number among the N byte element, if
1796/// the mask is in increasing/decreasing order then it is 1/-1.
1797/// \return true iff the mask is shuffling N byte elements.
1798static bool isNByteElemShuffleMask(ShuffleVectorSDNode *N, unsigned Width,
1799 int StepLen) {
1800 assert((Width == 2 || Width == 4 || Width == 8 || Width == 16) &&(((Width == 2 || Width == 4 || Width == 8 || Width == 16) &&
"Unexpected element width.") ? static_cast<void> (0) :
__assert_fail ("(Width == 2 || Width == 4 || Width == 8 || Width == 16) && \"Unexpected element width.\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCISelLowering.cpp"
, 1801, __PRETTY_FUNCTION__))
1801 "Unexpected element width.")(((Width == 2 || Width == 4 || Width == 8 || Width == 16) &&
"Unexpected element width.") ? static_cast<void> (0) :
__assert_fail ("(Width == 2 || Width == 4 || Width == 8 || Width == 16) && \"Unexpected element width.\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCISelLowering.cpp"
, 1801, __PRETTY_FUNCTION__))
;
1802 assert((StepLen == 1 || StepLen == -1) && "Unexpected element width.")(((StepLen == 1 || StepLen == -1) && "Unexpected element width."
) ? static_cast<void> (0) : __assert_fail ("(StepLen == 1 || StepLen == -1) && \"Unexpected element width.\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCISelLowering.cpp"
, 1802, __PRETTY_FUNCTION__))
;
1803
1804 unsigned NumOfElem = 16 / Width;
1805 unsigned MaskVal[16]; // Width is never greater than 16
1806 for (unsigned i = 0; i < NumOfElem; ++i) {
1807 MaskVal[0] = N->getMaskElt(i * Width);
1808 if ((StepLen == 1) && (MaskVal[0] % Width)) {
1809 return false;
1810 } else if ((StepLen == -1) && ((MaskVal[0] + 1) % Width)) {
1811 return false;
1812 }
1813
1814 for (unsigned int j = 1; j < Width; ++j) {
1815 MaskVal[j] = N->getMaskElt(i * Width + j);
1816 if (MaskVal[j] != MaskVal[j-1] + StepLen) {
1817 return false;
1818 }
1819 }
1820 }
1821
1822 return true;
1823}
1824
1825bool PPC::isXXINSERTWMask(ShuffleVectorSDNode *N, unsigned &ShiftElts,
1826 unsigned &InsertAtByte, bool &Swap, bool IsLE) {
1827 if (!isNByteElemShuffleMask(N, 4, 1))
1828 return false;
1829
1830 // Now we look at mask elements 0,4,8,12
1831 unsigned M0 = N->getMaskElt(0) / 4;
1832 unsigned M1 = N->getMaskElt(4) / 4;
1833 unsigned M2 = N->getMaskElt(8) / 4;
1834 unsigned M3 = N->getMaskElt(12) / 4;
1835 unsigned LittleEndianShifts[] = { 2, 1, 0, 3 };
1836 unsigned BigEndianShifts[] = { 3, 0, 1, 2 };
1837
1838 // Below, let H and L be arbitrary elements of the shuffle mask
1839 // where H is in the range [4,7] and L is in the range [0,3].
1840 // H, 1, 2, 3 or L, 5, 6, 7
1841 if ((M0 > 3 && M1 == 1 && M2 == 2 && M3 == 3) ||
1842 (M0 < 4 && M1 == 5 && M2 == 6 && M3 == 7)) {
1843 ShiftElts = IsLE ? LittleEndianShifts[M0 & 0x3] : BigEndianShifts[M0 & 0x3];
1844 InsertAtByte = IsLE ? 12 : 0;
1845 Swap = M0 < 4;
1846 return true;
1847 }
1848 // 0, H, 2, 3 or 4, L, 6, 7
1849 if ((M1 > 3 && M0 == 0 && M2 == 2 && M3 == 3) ||
1850 (M1 < 4 && M0 == 4 && M2 == 6 && M3 == 7)) {
1851 ShiftElts = IsLE ? LittleEndianShifts[M1 & 0x3] : BigEndianShifts[M1 & 0x3];
1852 InsertAtByte = IsLE ? 8 : 4;
1853 Swap = M1 < 4;
1854 return true;
1855 }
1856 // 0, 1, H, 3 or 4, 5, L, 7
1857 if ((M2 > 3 && M0 == 0 && M1 == 1 && M3 == 3) ||
1858 (M2 < 4 && M0 == 4 && M1 == 5 && M3 == 7)) {
1859 ShiftElts = IsLE ? LittleEndianShifts[M2 & 0x3] : BigEndianShifts[M2 & 0x3];
1860 InsertAtByte = IsLE ? 4 : 8;
1861 Swap = M2 < 4;
1862 return true;
1863 }
1864 // 0, 1, 2, H or 4, 5, 6, L
1865 if ((M3 > 3 && M0 == 0 && M1 == 1 && M2 == 2) ||
1866 (M3 < 4 && M0 == 4 && M1 == 5 && M2 == 6)) {
1867 ShiftElts = IsLE ? LittleEndianShifts[M3 & 0x3] : BigEndianShifts[M3 & 0x3];
1868 InsertAtByte = IsLE ? 0 : 12;
1869 Swap = M3 < 4;
1870 return true;
1871 }
1872
1873 // If both vector operands for the shuffle are the same vector, the mask will
1874 // contain only elements from the first one and the second one will be undef.
1875 if (N->getOperand(1).isUndef()) {
1876 ShiftElts = 0;
1877 Swap = true;
1878 unsigned XXINSERTWSrcElem = IsLE ? 2 : 1;
1879 if (M0 == XXINSERTWSrcElem && M1 == 1 && M2 == 2 && M3 == 3) {
1880 InsertAtByte = IsLE ? 12 : 0;
1881 return true;
1882 }
1883 if (M0 == 0 && M1 == XXINSERTWSrcElem && M2 == 2 && M3 == 3) {
1884 InsertAtByte = IsLE ? 8 : 4;
1885 return true;
1886 }
1887 if (M0 == 0 && M1 == 1 && M2 == XXINSERTWSrcElem && M3 == 3) {
1888 InsertAtByte = IsLE ? 4 : 8;
1889 return true;
1890 }
1891 if (M0 == 0 && M1 == 1 && M2 == 2 && M3 == XXINSERTWSrcElem) {
1892 InsertAtByte = IsLE ? 0 : 12;
1893 return true;
1894 }
1895 }
1896
1897 return false;
1898}
1899
1900bool PPC::isXXSLDWIShuffleMask(ShuffleVectorSDNode *N, unsigned &ShiftElts,
1901 bool &Swap, bool IsLE) {
1902 assert(N->getValueType(0) == MVT::v16i8 && "Shuffle vector expects v16i8")((N->getValueType(0) == MVT::v16i8 && "Shuffle vector expects v16i8"
) ? static_cast<void> (0) : __assert_fail ("N->getValueType(0) == MVT::v16i8 && \"Shuffle vector expects v16i8\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCISelLowering.cpp"
, 1902, __PRETTY_FUNCTION__))
;
7
'?' condition is true
1903 // Ensure each byte index of the word is consecutive.
1904 if (!isNByteElemShuffleMask(N, 4, 1))
8
Assuming the condition is false
9
Taking false branch
1905 return false;
1906
1907 // Now we look at mask elements 0,4,8,12, which are the beginning of words.
1908 unsigned M0 = N->getMaskElt(0) / 4;
1909 unsigned M1 = N->getMaskElt(4) / 4;
1910 unsigned M2 = N->getMaskElt(8) / 4;
1911 unsigned M3 = N->getMaskElt(12) / 4;
1912
1913 // If both vector operands for the shuffle are the same vector, the mask will
1914 // contain only elements from the first one and the second one will be undef.
1915 if (N->getOperand(1).isUndef()) {
10
Taking false branch
1916 assert(M0 < 4 && "Indexing into an undef vector?")((M0 < 4 && "Indexing into an undef vector?") ? static_cast
<void> (0) : __assert_fail ("M0 < 4 && \"Indexing into an undef vector?\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCISelLowering.cpp"
, 1916, __PRETTY_FUNCTION__))
;
1917 if (M1 != (M0 + 1) % 4 || M2 != (M1 + 1) % 4 || M3 != (M2 + 1) % 4)
1918 return false;
1919
1920 ShiftElts = IsLE ? (4 - M0) % 4 : M0;
1921 Swap = false;
1922 return true;
1923 }
1924
1925 // Ensure each word index of the ShuffleVector Mask is consecutive.
1926 if (M1 != (M0 + 1) % 8 || M2 != (M1 + 1) % 8 || M3 != (M2 + 1) % 8)
11
Assuming the condition is false
12
Assuming the condition is false
13
Assuming the condition is false
14
Taking false branch
1927 return false;
1928
1929 if (IsLE) {
15
Assuming 'IsLE' is 0
16
Taking false branch
1930 if (M0 == 0 || M0 == 7 || M0 == 6 || M0 == 5) {
1931 // Input vectors don't need to be swapped if the leading element
1932 // of the result is one of the 3 left elements of the second vector
1933 // (or if there is no shift to be done at all).
1934 Swap = false;
1935 ShiftElts = (8 - M0) % 8;
1936 } else if (M0 == 4 || M0 == 3 || M0 == 2 || M0 == 1) {
1937 // Input vectors need to be swapped if the leading element
1938 // of the result is one of the 3 left elements of the first vector
1939 // (or if we're shifting by 4 - thereby simply swapping the vectors).
1940 Swap = true;
1941 ShiftElts = (4 - M0) % 4;
1942 }
1943
1944 return true;
1945 } else { // BE
1946 if (M0 == 0 || M0 == 1 || M0 == 2 || M0 == 3) {
17
Assuming 'M0' is not equal to 0
18
Assuming 'M0' is not equal to 1
19
Assuming 'M0' is not equal to 2
20
Assuming 'M0' is not equal to 3
21
Taking false branch
1947 // Input vectors don't need to be swapped if the leading element
1948 // of the result is one of the 4 elements of the first vector.
1949 Swap = false;
1950 ShiftElts = M0;
1951 } else if (M0 == 4 || M0 == 5 || M0 == 6 || M0 == 7) {
22
Assuming 'M0' is not equal to 4
23
Assuming 'M0' is not equal to 5
24
Assuming 'M0' is not equal to 6
25
Assuming 'M0' is not equal to 7
26
Taking false branch
1952 // Input vectors need to be swapped if the leading element
1953 // of the result is one of the 4 elements of the right vector.
1954 Swap = true;
1955 ShiftElts = M0 - 4;
1956 }
1957
1958 return true;
27
Returning without writing to 'ShiftElts'
1959 }
1960}
1961
1962bool static isXXBRShuffleMaskHelper(ShuffleVectorSDNode *N, int Width) {
1963 assert(N->getValueType(0) == MVT::v16i8 && "Shuffle vector expects v16i8")((N->getValueType(0) == MVT::v16i8 && "Shuffle vector expects v16i8"
) ? static_cast<void> (0) : __assert_fail ("N->getValueType(0) == MVT::v16i8 && \"Shuffle vector expects v16i8\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCISelLowering.cpp"
, 1963, __PRETTY_FUNCTION__))
;
1964
1965 if (!isNByteElemShuffleMask(N, Width, -1))
1966 return false;
1967
1968 for (int i = 0; i < 16; i += Width)
1969 if (N->getMaskElt(i) != i + Width - 1)
1970 return false;
1971
1972 return true;
1973}
1974
1975bool PPC::isXXBRHShuffleMask(ShuffleVectorSDNode *N) {
1976 return isXXBRShuffleMaskHelper(N, 2);
1977}
1978
1979bool PPC::isXXBRWShuffleMask(ShuffleVectorSDNode *N) {
1980 return isXXBRShuffleMaskHelper(N, 4);
1981}
1982
1983bool PPC::isXXBRDShuffleMask(ShuffleVectorSDNode *N) {
1984 return isXXBRShuffleMaskHelper(N, 8);
1985}
1986
1987bool PPC::isXXBRQShuffleMask(ShuffleVectorSDNode *N) {
1988 return isXXBRShuffleMaskHelper(N, 16);
1989}
1990
1991/// Can node \p N be lowered to an XXPERMDI instruction? If so, set \p Swap
1992/// if the inputs to the instruction should be swapped and set \p DM to the
1993/// value for the immediate.
1994/// Specifically, set \p Swap to true only if \p N can be lowered to XXPERMDI
1995/// AND element 0 of the result comes from the first input (LE) or second input
1996/// (BE). Set \p DM to the calculated result (0-3) only if \p N can be lowered.
1997/// \return true iff the given mask of shuffle node \p N is a XXPERMDI shuffle
1998/// mask.
1999bool PPC::isXXPERMDIShuffleMask(ShuffleVectorSDNode *N, unsigned &DM,
2000 bool &Swap, bool IsLE) {
2001 assert(N->getValueType(0) == MVT::v16i8 && "Shuffle vector expects v16i8")((N->getValueType(0) == MVT::v16i8 && "Shuffle vector expects v16i8"
) ? static_cast<void> (0) : __assert_fail ("N->getValueType(0) == MVT::v16i8 && \"Shuffle vector expects v16i8\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2001, __PRETTY_FUNCTION__))
;
2002
2003 // Ensure each byte index of the double word is consecutive.
2004 if (!isNByteElemShuffleMask(N, 8, 1))
2005 return false;
2006
2007 unsigned M0 = N->getMaskElt(0) / 8;
2008 unsigned M1 = N->getMaskElt(8) / 8;
2009 assert(((M0 | M1) < 4) && "A mask element out of bounds?")((((M0 | M1) < 4) && "A mask element out of bounds?"
) ? static_cast<void> (0) : __assert_fail ("((M0 | M1) < 4) && \"A mask element out of bounds?\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2009, __PRETTY_FUNCTION__))
;
2010
2011 // If both vector operands for the shuffle are the same vector, the mask will
2012 // contain only elements from the first one and the second one will be undef.
2013 if (N->getOperand(1).isUndef()) {
2014 if ((M0 | M1) < 2) {
2015 DM = IsLE ? (((~M1) & 1) << 1) + ((~M0) & 1) : (M0 << 1) + (M1 & 1);
2016 Swap = false;
2017 return true;
2018 } else
2019 return false;
2020 }
2021
2022 if (IsLE) {
2023 if (M0 > 1 && M1 < 2) {
2024 Swap = false;
2025 } else if (M0 < 2 && M1 > 1) {
2026 M0 = (M0 + 2) % 4;
2027 M1 = (M1 + 2) % 4;
2028 Swap = true;
2029 } else
2030 return false;
2031
2032 // Note: if control flow comes here that means Swap is already set above
2033 DM = (((~M1) & 1) << 1) + ((~M0) & 1);
2034 return true;
2035 } else { // BE
2036 if (M0 < 2 && M1 > 1) {
2037 Swap = false;
2038 } else if (M0 > 1 && M1 < 2) {
2039 M0 = (M0 + 2) % 4;
2040 M1 = (M1 + 2) % 4;
2041 Swap = true;
2042 } else
2043 return false;
2044
2045 // Note: if control flow comes here that means Swap is already set above
2046 DM = (M0 << 1) + (M1 & 1);
2047 return true;
2048 }
2049}
2050
2051
2052/// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
2053/// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
2054unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize,
2055 SelectionDAG &DAG) {
2056 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
2057 assert(isSplatShuffleMask(SVOp, EltSize))((isSplatShuffleMask(SVOp, EltSize)) ? static_cast<void>
(0) : __assert_fail ("isSplatShuffleMask(SVOp, EltSize)", "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2057, __PRETTY_FUNCTION__))
;
2058 if (DAG.getDataLayout().isLittleEndian())
2059 return (16 / EltSize) - 1 - (SVOp->getMaskElt(0) / EltSize);
2060 else
2061 return SVOp->getMaskElt(0) / EltSize;
2062}
2063
2064/// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
2065/// by using a vspltis[bhw] instruction of the specified element size, return
2066/// the constant being splatted. The ByteSize field indicates the number of
2067/// bytes of each element [124] -> [bhw].
2068SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
2069 SDValue OpVal(nullptr, 0);
2070
2071 // If ByteSize of the splat is bigger than the element size of the
2072 // build_vector, then we have a case where we are checking for a splat where
2073 // multiple elements of the buildvector are folded together into a single
2074 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
2075 unsigned EltSize = 16/N->getNumOperands();
2076 if (EltSize < ByteSize) {
2077 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
2078 SDValue UniquedVals[4];
2079 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?")((Multiple > 1 && Multiple <= 4 && "How can this happen?"
) ? static_cast<void> (0) : __assert_fail ("Multiple > 1 && Multiple <= 4 && \"How can this happen?\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2079, __PRETTY_FUNCTION__))
;
2080
2081 // See if all of the elements in the buildvector agree across.
2082 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
2083 if (N->getOperand(i).isUndef()) continue;
2084 // If the element isn't a constant, bail fully out.
2085 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
2086
2087 if (!UniquedVals[i&(Multiple-1)].getNode())
2088 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
2089 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
2090 return SDValue(); // no match.
2091 }
2092
2093 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
2094 // either constant or undef values that are identical for each chunk. See
2095 // if these chunks can form into a larger vspltis*.
2096
2097 // Check to see if all of the leading entries are either 0 or -1. If
2098 // neither, then this won't fit into the immediate field.
2099 bool LeadingZero = true;
2100 bool LeadingOnes = true;
2101 for (unsigned i = 0; i != Multiple-1; ++i) {
2102 if (!UniquedVals[i].getNode()) continue; // Must have been undefs.
2103
2104 LeadingZero &= isNullConstant(UniquedVals[i]);
2105 LeadingOnes &= isAllOnesConstant(UniquedVals[i]);
2106 }
2107 // Finally, check the least significant entry.
2108 if (LeadingZero) {
2109 if (!UniquedVals[Multiple-1].getNode())
2110 return DAG.getTargetConstant(0, SDLoc(N), MVT::i32); // 0,0,0,undef
2111 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
2112 if (Val < 16) // 0,0,0,4 -> vspltisw(4)
2113 return DAG.getTargetConstant(Val, SDLoc(N), MVT::i32);
2114 }
2115 if (LeadingOnes) {
2116 if (!UniquedVals[Multiple-1].getNode())
2117 return DAG.getTargetConstant(~0U, SDLoc(N), MVT::i32); // -1,-1,-1,undef
2118 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
2119 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
2120 return DAG.getTargetConstant(Val, SDLoc(N), MVT::i32);
2121 }
2122
2123 return SDValue();
2124 }
2125
2126 // Check to see if this buildvec has a single non-undef value in its elements.
2127 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
2128 if (N->getOperand(i).isUndef()) continue;
2129 if (!OpVal.getNode())
2130 OpVal = N->getOperand(i);
2131 else if (OpVal != N->getOperand(i))
2132 return SDValue();
2133 }
2134
2135 if (!OpVal.getNode()) return SDValue(); // All UNDEF: use implicit def.
2136
2137 unsigned ValSizeInBytes = EltSize;
2138 uint64_t Value = 0;
2139 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
2140 Value = CN->getZExtValue();
2141 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
2142 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!")((CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!"
) ? static_cast<void> (0) : __assert_fail ("CN->getValueType(0) == MVT::f32 && \"Only one legal FP vector type!\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2142, __PRETTY_FUNCTION__))
;
2143 Value = FloatToBits(CN->getValueAPF().convertToFloat());
2144 }
2145
2146 // If the splat value is larger than the element value, then we can never do
2147 // this splat. The only case that we could fit the replicated bits into our
2148 // immediate field for would be zero, and we prefer to use vxor for it.
2149 if (ValSizeInBytes < ByteSize) return SDValue();
2150
2151 // If the element value is larger than the splat value, check if it consists
2152 // of a repeated bit pattern of size ByteSize.
2153 if (!APInt(ValSizeInBytes * 8, Value).isSplat(ByteSize * 8))
2154 return SDValue();
2155
2156 // Properly sign extend the value.
2157 int MaskVal = SignExtend32(Value, ByteSize * 8);
2158
2159 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
2160 if (MaskVal == 0) return SDValue();
2161
2162 // Finally, if this value fits in a 5 bit sext field, return it
2163 if (SignExtend32<5>(MaskVal) == MaskVal)
2164 return DAG.getTargetConstant(MaskVal, SDLoc(N), MVT::i32);
2165 return SDValue();
2166}
2167
2168/// isQVALIGNIShuffleMask - If this is a qvaligni shuffle mask, return the shift
2169/// amount, otherwise return -1.
2170int PPC::isQVALIGNIShuffleMask(SDNode *N) {
2171 EVT VT = N->getValueType(0);
2172 if (VT != MVT::v4f64 && VT != MVT::v4f32 && VT != MVT::v4i1)
2173 return -1;
2174
2175 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
2176
2177 // Find the first non-undef value in the shuffle mask.
2178 unsigned i;
2179 for (i = 0; i != 4 && SVOp->getMaskElt(i) < 0; ++i)
2180 /*search*/;
2181
2182 if (i == 4) return -1; // all undef.
2183
2184 // Otherwise, check to see if the rest of the elements are consecutively
2185 // numbered from this value.
2186 unsigned ShiftAmt = SVOp->getMaskElt(i);
2187 if (ShiftAmt < i) return -1;
2188 ShiftAmt -= i;
2189
2190 // Check the rest of the elements to see if they are consecutive.
2191 for (++i; i != 4; ++i)
2192 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
2193 return -1;
2194
2195 return ShiftAmt;
2196}
2197
2198//===----------------------------------------------------------------------===//
2199// Addressing Mode Selection
2200//===----------------------------------------------------------------------===//
2201
2202/// isIntS16Immediate - This method tests to see if the node is either a 32-bit
2203/// or 64-bit immediate, and if the value can be accurately represented as a
2204/// sign extension from a 16-bit value. If so, this returns true and the
2205/// immediate.
2206bool llvm::isIntS16Immediate(SDNode *N, int16_t &Imm) {
2207 if (!isa<ConstantSDNode>(N))
2208 return false;
2209
2210 Imm = (int16_t)cast<ConstantSDNode>(N)->getZExtValue();
2211 if (N->getValueType(0) == MVT::i32)
2212 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
2213 else
2214 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
2215}
2216bool llvm::isIntS16Immediate(SDValue Op, int16_t &Imm) {
2217 return isIntS16Immediate(Op.getNode(), Imm);
2218}
2219
2220/// SelectAddressRegReg - Given the specified addressed, check to see if it
2221/// can be represented as an indexed [r+r] operation. Returns false if it
2222/// can be more efficiently represented as [r+imm]. If \p EncodingAlignment is
2223/// non-zero and N can be represented by a base register plus a signed 16-bit
2224/// displacement, make a more precise judgement by checking (displacement % \p
2225/// EncodingAlignment).
2226bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base,
2227 SDValue &Index, SelectionDAG &DAG,
2228 unsigned EncodingAlignment) const {
2229 int16_t imm = 0;
2230 if (N.getOpcode() == ISD::ADD) {
2231 if (isIntS16Immediate(N.getOperand(1), imm) &&
2232 (!EncodingAlignment || !(imm % EncodingAlignment)))
2233 return false; // r+i
2234 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
2235 return false; // r+i
2236
2237 Base = N.getOperand(0);
2238 Index = N.getOperand(1);
2239 return true;
2240 } else if (N.getOpcode() == ISD::OR) {
2241 if (isIntS16Immediate(N.getOperand(1), imm) &&
2242 (!EncodingAlignment || !(imm % EncodingAlignment)))
2243 return false; // r+i can fold it if we can.
2244
2245 // If this is an or of disjoint bitfields, we can codegen this as an add
2246 // (for better address arithmetic) if the LHS and RHS of the OR are provably
2247 // disjoint.
2248 KnownBits LHSKnown = DAG.computeKnownBits(N.getOperand(0));
2249
2250 if (LHSKnown.Zero.getBoolValue()) {
2251 KnownBits RHSKnown = DAG.computeKnownBits(N.getOperand(1));
2252 // If all of the bits are known zero on the LHS or RHS, the add won't
2253 // carry.
2254 if (~(LHSKnown.Zero | RHSKnown.Zero) == 0) {
2255 Base = N.getOperand(0);
2256 Index = N.getOperand(1);
2257 return true;
2258 }
2259 }
2260 }
2261
2262 return false;
2263}
2264
2265// If we happen to be doing an i64 load or store into a stack slot that has
2266// less than a 4-byte alignment, then the frame-index elimination may need to
2267// use an indexed load or store instruction (because the offset may not be a
2268// multiple of 4). The extra register needed to hold the offset comes from the
2269// register scavenger, and it is possible that the scavenger will need to use
2270// an emergency spill slot. As a result, we need to make sure that a spill slot
2271// is allocated when doing an i64 load/store into a less-than-4-byte-aligned
2272// stack slot.
2273static void fixupFuncForFI(SelectionDAG &DAG, int FrameIdx, EVT VT) {
2274 // FIXME: This does not handle the LWA case.
2275 if (VT != MVT::i64)
2276 return;
2277
2278 // NOTE: We'll exclude negative FIs here, which come from argument
2279 // lowering, because there are no known test cases triggering this problem
2280 // using packed structures (or similar). We can remove this exclusion if
2281 // we find such a test case. The reason why this is so test-case driven is
2282 // because this entire 'fixup' is only to prevent crashes (from the
2283 // register scavenger) on not-really-valid inputs. For example, if we have:
2284 // %a = alloca i1
2285 // %b = bitcast i1* %a to i64*
2286 // store i64* a, i64 b
2287 // then the store should really be marked as 'align 1', but is not. If it
2288 // were marked as 'align 1' then the indexed form would have been
2289 // instruction-selected initially, and the problem this 'fixup' is preventing
2290 // won't happen regardless.
2291 if (FrameIdx < 0)
2292 return;
2293
2294 MachineFunction &MF = DAG.getMachineFunction();
2295 MachineFrameInfo &MFI = MF.getFrameInfo();
2296
2297 unsigned Align = MFI.getObjectAlignment(FrameIdx);
2298 if (Align >= 4)
2299 return;
2300
2301 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2302 FuncInfo->setHasNonRISpills();
2303}
2304
2305/// Returns true if the address N can be represented by a base register plus
2306/// a signed 16-bit displacement [r+imm], and if it is not better
2307/// represented as reg+reg. If \p EncodingAlignment is non-zero, only accept
2308/// displacements that are multiples of that value.
2309bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp,
2310 SDValue &Base,
2311 SelectionDAG &DAG,
2312 unsigned EncodingAlignment) const {
2313 // FIXME dl should come from parent load or store, not from address
2314 SDLoc dl(N);
2315 // If this can be more profitably realized as r+r, fail.
2316 if (SelectAddressRegReg(N, Disp, Base, DAG, EncodingAlignment))
2317 return false;
2318
2319 if (N.getOpcode() == ISD::ADD) {
2320 int16_t imm = 0;
2321 if (isIntS16Immediate(N.getOperand(1), imm) &&
2322 (!EncodingAlignment || (imm % EncodingAlignment) == 0)) {
2323 Disp = DAG.getTargetConstant(imm, dl, N.getValueType());
2324 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
2325 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
2326 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
2327 } else {
2328 Base = N.getOperand(0);
2329 }
2330 return true; // [r+i]
2331 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
2332 // Match LOAD (ADD (X, Lo(G))).
2333 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()((!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->
getZExtValue() && "Cannot handle constant offsets yet!"
) ? static_cast<void> (0) : __assert_fail ("!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue() && \"Cannot handle constant offsets yet!\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2334, __PRETTY_FUNCTION__))
2334 && "Cannot handle constant offsets yet!")((!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->
getZExtValue() && "Cannot handle constant offsets yet!"
) ? static_cast<void> (0) : __assert_fail ("!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue() && \"Cannot handle constant offsets yet!\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2334, __PRETTY_FUNCTION__))
;
2335 Disp = N.getOperand(1).getOperand(0); // The global address.
2336 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||((Disp.getOpcode() == ISD::TargetGlobalAddress || Disp.getOpcode
() == ISD::TargetGlobalTLSAddress || Disp.getOpcode() == ISD::
TargetConstantPool || Disp.getOpcode() == ISD::TargetJumpTable
) ? static_cast<void> (0) : __assert_fail ("Disp.getOpcode() == ISD::TargetGlobalAddress || Disp.getOpcode() == ISD::TargetGlobalTLSAddress || Disp.getOpcode() == ISD::TargetConstantPool || Disp.getOpcode() == ISD::TargetJumpTable"
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2339, __PRETTY_FUNCTION__))
2337 Disp.getOpcode() == ISD::TargetGlobalTLSAddress ||((Disp.getOpcode() == ISD::TargetGlobalAddress || Disp.getOpcode
() == ISD::TargetGlobalTLSAddress || Disp.getOpcode() == ISD::
TargetConstantPool || Disp.getOpcode() == ISD::TargetJumpTable
) ? static_cast<void> (0) : __assert_fail ("Disp.getOpcode() == ISD::TargetGlobalAddress || Disp.getOpcode() == ISD::TargetGlobalTLSAddress || Disp.getOpcode() == ISD::TargetConstantPool || Disp.getOpcode() == ISD::TargetJumpTable"
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2339, __PRETTY_FUNCTION__))
2338 Disp.getOpcode() == ISD::TargetConstantPool ||((Disp.getOpcode() == ISD::TargetGlobalAddress || Disp.getOpcode
() == ISD::TargetGlobalTLSAddress || Disp.getOpcode() == ISD::
TargetConstantPool || Disp.getOpcode() == ISD::TargetJumpTable
) ? static_cast<void> (0) : __assert_fail ("Disp.getOpcode() == ISD::TargetGlobalAddress || Disp.getOpcode() == ISD::TargetGlobalTLSAddress || Disp.getOpcode() == ISD::TargetConstantPool || Disp.getOpcode() == ISD::TargetJumpTable"
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2339, __PRETTY_FUNCTION__))
2339 Disp.getOpcode() == ISD::TargetJumpTable)((Disp.getOpcode() == ISD::TargetGlobalAddress || Disp.getOpcode
() == ISD::TargetGlobalTLSAddress || Disp.getOpcode() == ISD::
TargetConstantPool || Disp.getOpcode() == ISD::TargetJumpTable
) ? static_cast<void> (0) : __assert_fail ("Disp.getOpcode() == ISD::TargetGlobalAddress || Disp.getOpcode() == ISD::TargetGlobalTLSAddress || Disp.getOpcode() == ISD::TargetConstantPool || Disp.getOpcode() == ISD::TargetJumpTable"
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2339, __PRETTY_FUNCTION__))
;
2340 Base = N.getOperand(0);
2341 return true; // [&g+r]
2342 }
2343 } else if (N.getOpcode() == ISD::OR) {
2344 int16_t imm = 0;
2345 if (isIntS16Immediate(N.getOperand(1), imm) &&
2346 (!EncodingAlignment || (imm % EncodingAlignment) == 0)) {
2347 // If this is an or of disjoint bitfields, we can codegen this as an add
2348 // (for better address arithmetic) if the LHS and RHS of the OR are
2349 // provably disjoint.
2350 KnownBits LHSKnown = DAG.computeKnownBits(N.getOperand(0));
2351
2352 if ((LHSKnown.Zero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
2353 // If all of the bits are known zero on the LHS or RHS, the add won't
2354 // carry.
2355 if (FrameIndexSDNode *FI =
2356 dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
2357 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
2358 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
2359 } else {
2360 Base = N.getOperand(0);
2361 }
2362 Disp = DAG.getTargetConstant(imm, dl, N.getValueType());
2363 return true;
2364 }
2365 }
2366 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
2367 // Loading from a constant address.
2368
2369 // If this address fits entirely in a 16-bit sext immediate field, codegen
2370 // this as "d, 0"
2371 int16_t Imm;
2372 if (isIntS16Immediate(CN, Imm) &&
2373 (!EncodingAlignment || (Imm % EncodingAlignment) == 0)) {
2374 Disp = DAG.getTargetConstant(Imm, dl, CN->getValueType(0));
2375 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
2376 CN->getValueType(0));
2377 return true;
2378 }
2379
2380 // Handle 32-bit sext immediates with LIS + addr mode.
2381 if ((CN->getValueType(0) == MVT::i32 ||
2382 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) &&
2383 (!EncodingAlignment || (CN->getZExtValue() % EncodingAlignment) == 0)) {
2384 int Addr = (int)CN->getZExtValue();
2385
2386 // Otherwise, break this down into an LIS + disp.
2387 Disp = DAG.getTargetConstant((short)Addr, dl, MVT::i32);
2388
2389 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, dl,
2390 MVT::i32);
2391 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
2392 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0);
2393 return true;
2394 }
2395 }
2396
2397 Disp = DAG.getTargetConstant(0, dl, getPointerTy(DAG.getDataLayout()));
2398 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) {
2399 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
2400 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
2401 } else
2402 Base = N;
2403 return true; // [r+0]
2404}
2405
2406/// SelectAddressRegRegOnly - Given the specified addressed, force it to be
2407/// represented as an indexed [r+r] operation.
2408bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
2409 SDValue &Index,
2410 SelectionDAG &DAG) const {
2411 // Check to see if we can easily represent this as an [r+r] address. This
2412 // will fail if it thinks that the address is more profitably represented as
2413 // reg+imm, e.g. where imm = 0.
2414 if (SelectAddressRegReg(N, Base, Index, DAG))
2415 return true;
2416
2417 // If the address is the result of an add, we will utilize the fact that the
2418 // address calculation includes an implicit add. However, we can reduce
2419 // register pressure if we do not materialize a constant just for use as the
2420 // index register. We only get rid of the add if it is not an add of a
2421 // value and a 16-bit signed constant and both have a single use.
2422 int16_t imm = 0;
2423 if (N.getOpcode() == ISD::ADD &&
2424 (!isIntS16Immediate(N.getOperand(1), imm) ||
2425 !N.getOperand(1).hasOneUse() || !N.getOperand(0).hasOneUse())) {
2426 Base = N.getOperand(0);
2427 Index = N.getOperand(1);
2428 return true;
2429 }
2430
2431 // Otherwise, do it the hard way, using R0 as the base register.
2432 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
2433 N.getValueType());
2434 Index = N;
2435 return true;
2436}
2437
2438/// Returns true if we should use a direct load into vector instruction
2439/// (such as lxsd or lfd), instead of a load into gpr + direct move sequence.
2440static bool usePartialVectorLoads(SDNode *N, const PPCSubtarget& ST) {
2441
2442 // If there are any other uses other than scalar to vector, then we should
2443 // keep it as a scalar load -> direct move pattern to prevent multiple
2444 // loads.
2445 LoadSDNode *LD = dyn_cast<LoadSDNode>(N);
2446 if (!LD)
2447 return false;
2448
2449 EVT MemVT = LD->getMemoryVT();
2450 if (!MemVT.isSimple())
2451 return false;
2452 switch(MemVT.getSimpleVT().SimpleTy) {
2453 case MVT::i64:
2454 break;
2455 case MVT::i32:
2456 if (!ST.hasP8Vector())
2457 return false;
2458 break;
2459 case MVT::i16:
2460 case MVT::i8:
2461 if (!ST.hasP9Vector())
2462 return false;
2463 break;
2464 default:
2465 return false;
2466 }
2467
2468 SDValue LoadedVal(N, 0);
2469 if (!LoadedVal.hasOneUse())
2470 return false;
2471
2472 for (SDNode::use_iterator UI = LD->use_begin(), UE = LD->use_end();
2473 UI != UE; ++UI)
2474 if (UI.getUse().get().getResNo() == 0 &&
2475 UI->getOpcode() != ISD::SCALAR_TO_VECTOR)
2476 return false;
2477
2478 return true;
2479}
2480
2481/// getPreIndexedAddressParts - returns true by value, base pointer and
2482/// offset pointer and addressing mode by reference if the node's address
2483/// can be legally represented as pre-indexed load / store address.
2484bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
2485 SDValue &Offset,
2486 ISD::MemIndexedMode &AM,
2487 SelectionDAG &DAG) const {
2488 if (DisablePPCPreinc) return false;
2489
2490 bool isLoad = true;
2491 SDValue Ptr;
2492 EVT VT;
2493 unsigned Alignment;
2494 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
2495 Ptr = LD->getBasePtr();
2496 VT = LD->getMemoryVT();
2497 Alignment = LD->getAlignment();
2498 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
2499 Ptr = ST->getBasePtr();
2500 VT = ST->getMemoryVT();
2501 Alignment = ST->getAlignment();
2502 isLoad = false;
2503 } else
2504 return false;
2505
2506 // Do not generate pre-inc forms for specific loads that feed scalar_to_vector
2507 // instructions because we can fold these into a more efficient instruction
2508 // instead, (such as LXSD).
2509 if (isLoad && usePartialVectorLoads(N, Subtarget)) {
2510 return false;
2511 }
2512
2513 // PowerPC doesn't have preinc load/store instructions for vectors (except
2514 // for QPX, which does have preinc r+r forms).
2515 if (VT.isVector()) {
2516 if (!Subtarget.hasQPX() || (VT != MVT::v4f64 && VT != MVT::v4f32)) {
2517 return false;
2518 } else if (SelectAddressRegRegOnly(Ptr, Offset, Base, DAG)) {
2519 AM = ISD::PRE_INC;
2520 return true;
2521 }
2522 }
2523
2524 if (SelectAddressRegReg(Ptr, Base, Offset, DAG)) {
2525 // Common code will reject creating a pre-inc form if the base pointer
2526 // is a frame index, or if N is a store and the base pointer is either
2527 // the same as or a predecessor of the value being stored. Check for
2528 // those situations here, and try with swapped Base/Offset instead.
2529 bool Swap = false;
2530
2531 if (isa<FrameIndexSDNode>(Base) || isa<RegisterSDNode>(Base))
2532 Swap = true;
2533 else if (!isLoad) {
2534 SDValue Val = cast<StoreSDNode>(N)->getValue();
2535 if (Val == Base || Base.getNode()->isPredecessorOf(Val.getNode()))
2536 Swap = true;
2537 }
2538
2539 if (Swap)
2540 std::swap(Base, Offset);
2541
2542 AM = ISD::PRE_INC;
2543 return true;
2544 }
2545
2546 // LDU/STU can only handle immediates that are a multiple of 4.
2547 if (VT != MVT::i64) {
2548 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, 0))
2549 return false;
2550 } else {
2551 // LDU/STU need an address with at least 4-byte alignment.
2552 if (Alignment < 4)
2553 return false;
2554
2555 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, 4))
2556 return false;
2557 }
2558
2559 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
2560 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
2561 // sext i32 to i64 when addr mode is r+i.
2562 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
2563 LD->getExtensionType() == ISD::SEXTLOAD &&
2564 isa<ConstantSDNode>(Offset))
2565 return false;
2566 }
2567
2568 AM = ISD::PRE_INC;
2569 return true;
2570}
2571
2572//===----------------------------------------------------------------------===//
2573// LowerOperation implementation
2574//===----------------------------------------------------------------------===//
2575
2576/// Return true if we should reference labels using a PICBase, set the HiOpFlags
2577/// and LoOpFlags to the target MO flags.
2578static void getLabelAccessInfo(bool IsPIC, const PPCSubtarget &Subtarget,
2579 unsigned &HiOpFlags, unsigned &LoOpFlags,
2580 const GlobalValue *GV = nullptr) {
2581 HiOpFlags = PPCII::MO_HA;
2582 LoOpFlags = PPCII::MO_LO;
2583
2584 // Don't use the pic base if not in PIC relocation model.
2585 if (IsPIC) {
2586 HiOpFlags |= PPCII::MO_PIC_FLAG;
2587 LoOpFlags |= PPCII::MO_PIC_FLAG;
2588 }
2589
2590 // If this is a reference to a global value that requires a non-lazy-ptr, make
2591 // sure that instruction lowering adds it.
2592 if (GV && Subtarget.hasLazyResolverStub(GV)) {
2593 HiOpFlags |= PPCII::MO_NLP_FLAG;
2594 LoOpFlags |= PPCII::MO_NLP_FLAG;
2595
2596 if (GV->hasHiddenVisibility()) {
2597 HiOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
2598 LoOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
2599 }
2600 }
2601}
2602
2603static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC,
2604 SelectionDAG &DAG) {
2605 SDLoc DL(HiPart);
2606 EVT PtrVT = HiPart.getValueType();
2607 SDValue Zero = DAG.getConstant(0, DL, PtrVT);
2608
2609 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero);
2610 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, LoPart, Zero);
2611
2612 // With PIC, the first instruction is actually "GR+hi(&G)".
2613 if (isPIC)
2614 Hi = DAG.getNode(ISD::ADD, DL, PtrVT,
2615 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT), Hi);
2616
2617 // Generate non-pic code that has direct accesses to the constant pool.
2618 // The address of the global is just (hi(&g)+lo(&g)).
2619 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
2620}
2621
2622static void setUsesTOCBasePtr(MachineFunction &MF) {
2623 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2624 FuncInfo->setUsesTOCBasePtr();
2625}
2626
2627static void setUsesTOCBasePtr(SelectionDAG &DAG) {
2628 setUsesTOCBasePtr(DAG.getMachineFunction());
2629}
2630
2631static SDValue getTOCEntry(SelectionDAG &DAG, const SDLoc &dl, bool Is64Bit,
2632 SDValue GA) {
2633 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
2634 SDValue Reg = Is64Bit ? DAG.getRegister(PPC::X2, VT) :
2635 DAG.getNode(PPCISD::GlobalBaseReg, dl, VT);
2636
2637 SDValue Ops[] = { GA, Reg };
2638 return DAG.getMemIntrinsicNode(
2639 PPCISD::TOC_ENTRY, dl, DAG.getVTList(VT, MVT::Other), Ops, VT,
2640 MachinePointerInfo::getGOT(DAG.getMachineFunction()), 0,
2641 MachineMemOperand::MOLoad);
2642}
2643
2644SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
2645 SelectionDAG &DAG) const {
2646 EVT PtrVT = Op.getValueType();
2647 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
2648 const Constant *C = CP->getConstVal();
2649
2650 // 64-bit SVR4 ABI code is always position-independent.
2651 // The actual address of the GlobalValue is stored in the TOC.
2652 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
2653 setUsesTOCBasePtr(DAG);
2654 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0);
2655 return getTOCEntry(DAG, SDLoc(CP), true, GA);
2656 }
2657
2658 unsigned MOHiFlag, MOLoFlag;
2659 bool IsPIC = isPositionIndependent();
2660 getLabelAccessInfo(IsPIC, Subtarget, MOHiFlag, MOLoFlag);
2661
2662 if (IsPIC && Subtarget.isSVR4ABI()) {
2663 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(),
2664 PPCII::MO_PIC_FLAG);
2665 return getTOCEntry(DAG, SDLoc(CP), false, GA);
2666 }
2667
2668 SDValue CPIHi =
2669 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOHiFlag);
2670 SDValue CPILo =
2671 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOLoFlag);
2672 return LowerLabelRef(CPIHi, CPILo, IsPIC, DAG);
2673}
2674
2675// For 64-bit PowerPC, prefer the more compact relative encodings.
2676// This trades 32 bits per jump table entry for one or two instructions
2677// on the jump site.
2678unsigned PPCTargetLowering::getJumpTableEncoding() const {
2679 if (isJumpTableRelative())
2680 return MachineJumpTableInfo::EK_LabelDifference32;
2681
2682 return TargetLowering::getJumpTableEncoding();
2683}
2684
2685bool PPCTargetLowering::isJumpTableRelative() const {
2686 if (Subtarget.isPPC64())
2687 return true;
2688 return TargetLowering::isJumpTableRelative();
2689}
2690
2691SDValue PPCTargetLowering::getPICJumpTableRelocBase(SDValue Table,
2692 SelectionDAG &DAG) const {
2693 if (!Subtarget.isPPC64())
2694 return TargetLowering::getPICJumpTableRelocBase(Table, DAG);
2695
2696 switch (getTargetMachine().getCodeModel()) {
2697 case CodeModel::Small:
2698 case CodeModel::Medium:
2699 return TargetLowering::getPICJumpTableRelocBase(Table, DAG);
2700 default:
2701 return DAG.getNode(PPCISD::GlobalBaseReg, SDLoc(),
2702 getPointerTy(DAG.getDataLayout()));
2703 }
2704}
2705
2706const MCExpr *
2707PPCTargetLowering::getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
2708 unsigned JTI,
2709 MCContext &Ctx) const {
2710 if (!Subtarget.isPPC64())
2711 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
2712
2713 switch (getTargetMachine().getCodeModel()) {
2714 case CodeModel::Small:
2715 case CodeModel::Medium:
2716 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
2717 default:
2718 return MCSymbolRefExpr::create(MF->getPICBaseSymbol(), Ctx);
2719 }
2720}
2721
2722SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
2723 EVT PtrVT = Op.getValueType();
2724 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
2725
2726 // 64-bit SVR4 ABI code is always position-independent.
2727 // The actual address of the GlobalValue is stored in the TOC.
2728 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
2729 setUsesTOCBasePtr(DAG);
2730 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
2731 return getTOCEntry(DAG, SDLoc(JT), true, GA);
2732 }
2733
2734 unsigned MOHiFlag, MOLoFlag;
2735 bool IsPIC = isPositionIndependent();
2736 getLabelAccessInfo(IsPIC, Subtarget, MOHiFlag, MOLoFlag);
2737
2738 if (IsPIC && Subtarget.isSVR4ABI()) {
2739 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
2740 PPCII::MO_PIC_FLAG);
2741 return getTOCEntry(DAG, SDLoc(GA), false, GA);
2742 }
2743
2744 SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag);
2745 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag);
2746 return LowerLabelRef(JTIHi, JTILo, IsPIC, DAG);
2747}
2748
2749SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op,
2750 SelectionDAG &DAG) const {
2751 EVT PtrVT = Op.getValueType();
2752 BlockAddressSDNode *BASDN = cast<BlockAddressSDNode>(Op);
2753 const BlockAddress *BA = BASDN->getBlockAddress();
2754
2755 // 64-bit SVR4 ABI code is always position-independent.
2756 // The actual BlockAddress is stored in the TOC.
2757 if (Subtarget.isSVR4ABI() &&
2758 (Subtarget.isPPC64() || isPositionIndependent())) {
2759 if (Subtarget.isPPC64())
2760 setUsesTOCBasePtr(DAG);
2761 SDValue GA = DAG.getTargetBlockAddress(BA, PtrVT, BASDN->getOffset());
2762 return getTOCEntry(DAG, SDLoc(BASDN), Subtarget.isPPC64(), GA);
2763 }
2764
2765 unsigned MOHiFlag, MOLoFlag;
2766 bool IsPIC = isPositionIndependent();
2767 getLabelAccessInfo(IsPIC, Subtarget, MOHiFlag, MOLoFlag);
2768 SDValue TgtBAHi = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOHiFlag);
2769 SDValue TgtBALo = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOLoFlag);
2770 return LowerLabelRef(TgtBAHi, TgtBALo, IsPIC, DAG);
2771}
2772
2773SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
2774 SelectionDAG &DAG) const {
2775 // FIXME: TLS addresses currently use medium model code sequences,
2776 // which is the most useful form. Eventually support for small and
2777 // large models could be added if users need it, at the cost of
2778 // additional complexity.
2779 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
2780 if (DAG.getTarget().useEmulatedTLS())
2781 return LowerToTLSEmulatedModel(GA, DAG);
2782
2783 SDLoc dl(GA);
2784 const GlobalValue *GV = GA->getGlobal();
2785 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2786 bool is64bit = Subtarget.isPPC64();
2787 const Module *M = DAG.getMachineFunction().getFunction().getParent();
2788 PICLevel::Level picLevel = M->getPICLevel();
2789
2790 const TargetMachine &TM = getTargetMachine();
2791 TLSModel::Model Model = TM.getTLSModel(GV);
2792
2793 if (Model == TLSModel::LocalExec) {
2794 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
2795 PPCII::MO_TPREL_HA);
2796 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
2797 PPCII::MO_TPREL_LO);
2798 SDValue TLSReg = is64bit ? DAG.getRegister(PPC::X13, MVT::i64)
2799 : DAG.getRegister(PPC::R2, MVT::i32);
2800
2801 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, TGAHi, TLSReg);
2802 return DAG.getNode(PPCISD::Lo, dl, PtrVT, TGALo, Hi);
2803 }
2804
2805 if (Model == TLSModel::InitialExec) {
2806 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
2807 SDValue TGATLS = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
2808 PPCII::MO_TLS);
2809 SDValue GOTPtr;
2810 if (is64bit) {
2811 setUsesTOCBasePtr(DAG);
2812 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
2813 GOTPtr = DAG.getNode(PPCISD::ADDIS_GOT_TPREL_HA, dl,
2814 PtrVT, GOTReg, TGA);
2815 } else {
2816 if (!TM.isPositionIndependent())
2817 GOTPtr = DAG.getNode(PPCISD::PPC32_GOT, dl, PtrVT);
2818 else if (picLevel == PICLevel::SmallPIC)
2819 GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT);
2820 else
2821 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
2822 }
2823 SDValue TPOffset = DAG.getNode(PPCISD::LD_GOT_TPREL_L, dl,
2824 PtrVT, TGA, GOTPtr);
2825 return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TPOffset, TGATLS);
2826 }
2827
2828 if (Model == TLSModel::GeneralDynamic) {
2829 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
2830 SDValue GOTPtr;
2831 if (is64bit) {
2832 setUsesTOCBasePtr(DAG);
2833 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
2834 GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSGD_HA, dl, PtrVT,
2835 GOTReg, TGA);
2836 } else {
2837 if (picLevel == PICLevel::SmallPIC)
2838 GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT);
2839 else
2840 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
2841 }
2842 return DAG.getNode(PPCISD::ADDI_TLSGD_L_ADDR, dl, PtrVT,
2843 GOTPtr, TGA, TGA);
2844 }
2845
2846 if (Model == TLSModel::LocalDynamic) {
2847 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
2848 SDValue GOTPtr;
2849 if (is64bit) {
2850 setUsesTOCBasePtr(DAG);
2851 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
2852 GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSLD_HA, dl, PtrVT,
2853 GOTReg, TGA);
2854 } else {
2855 if (picLevel == PICLevel::SmallPIC)
2856 GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT);
2857 else
2858 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
2859 }
2860 SDValue TLSAddr = DAG.getNode(PPCISD::ADDI_TLSLD_L_ADDR, dl,
2861 PtrVT, GOTPtr, TGA, TGA);
2862 SDValue DtvOffsetHi = DAG.getNode(PPCISD::ADDIS_DTPREL_HA, dl,
2863 PtrVT, TLSAddr, TGA);
2864 return DAG.getNode(PPCISD::ADDI_DTPREL_L, dl, PtrVT, DtvOffsetHi, TGA);
2865 }
2866
2867 llvm_unreachable("Unknown TLS model!")::llvm::llvm_unreachable_internal("Unknown TLS model!", "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2867)
;
2868}
2869
2870SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
2871 SelectionDAG &DAG) const {
2872 EVT PtrVT = Op.getValueType();
2873 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
2874 SDLoc DL(GSDN);
2875 const GlobalValue *GV = GSDN->getGlobal();
2876
2877 // 64-bit SVR4 ABI code is always position-independent.
2878 // The actual address of the GlobalValue is stored in the TOC.
2879 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
2880 setUsesTOCBasePtr(DAG);
2881 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset());
2882 return getTOCEntry(DAG, DL, true, GA);
2883 }
2884
2885 unsigned MOHiFlag, MOLoFlag;
2886 bool IsPIC = isPositionIndependent();
2887 getLabelAccessInfo(IsPIC, Subtarget, MOHiFlag, MOLoFlag, GV);
2888
2889 if (IsPIC && Subtarget.isSVR4ABI()) {
2890 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT,
2891 GSDN->getOffset(),
2892 PPCII::MO_PIC_FLAG);
2893 return getTOCEntry(DAG, DL, false, GA);
2894 }
2895
2896 SDValue GAHi =
2897 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag);
2898 SDValue GALo =
2899 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag);
2900
2901 SDValue Ptr = LowerLabelRef(GAHi, GALo, IsPIC, DAG);
2902
2903 // If the global reference is actually to a non-lazy-pointer, we have to do an
2904 // extra load to get the address of the global.
2905 if (MOHiFlag & PPCII::MO_NLP_FLAG)
2906 Ptr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo());
2907 return Ptr;
2908}
2909
2910SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
2911 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
2912 SDLoc dl(Op);
2913
2914 if (Op.getValueType() == MVT::v2i64) {
2915 // When the operands themselves are v2i64 values, we need to do something
2916 // special because VSX has no underlying comparison operations for these.
2917 if (Op.getOperand(0).getValueType() == MVT::v2i64) {
2918 // Equality can be handled by casting to the legal type for Altivec
2919 // comparisons, everything else needs to be expanded.
2920 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
2921 return DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
2922 DAG.getSetCC(dl, MVT::v4i32,
2923 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0)),
2924 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(1)),
2925 CC));
2926 }
2927
2928 return SDValue();
2929 }
2930
2931 // We handle most of these in the usual way.
2932 return Op;
2933 }
2934
2935 // If we're comparing for equality to zero, expose the fact that this is
2936 // implemented as a ctlz/srl pair on ppc, so that the dag combiner can
2937 // fold the new nodes.
2938 if (SDValue V = lowerCmpEqZeroToCtlzSrl(Op, DAG))
2939 return V;
2940
2941 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
2942 // Leave comparisons against 0 and -1 alone for now, since they're usually
2943 // optimized. FIXME: revisit this when we can custom lower all setcc
2944 // optimizations.
2945 if (C->isAllOnesValue() || C->isNullValue())
2946 return SDValue();
2947 }
2948
2949 // If we have an integer seteq/setne, turn it into a compare against zero
2950 // by xor'ing the rhs with the lhs, which is faster than setting a
2951 // condition register, reading it back out, and masking the correct bit. The
2952 // normal approach here uses sub to do this instead of xor. Using xor exposes
2953 // the result to other bit-twiddling opportunities.
2954 EVT LHSVT = Op.getOperand(0).getValueType();
2955 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
2956 EVT VT = Op.getValueType();
2957 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0),
2958 Op.getOperand(1));
2959 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, dl, LHSVT), CC);
2960 }
2961 return SDValue();
2962}
2963
2964SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
2965 SDNode *Node = Op.getNode();
2966 EVT VT = Node->getValueType(0);
2967 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2968 SDValue InChain = Node->getOperand(0);
2969 SDValue VAListPtr = Node->getOperand(1);
2970 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
2971 SDLoc dl(Node);
2972
2973 assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only")((!Subtarget.isPPC64() && "LowerVAARG is PPC32 only")
? static_cast<void> (0) : __assert_fail ("!Subtarget.isPPC64() && \"LowerVAARG is PPC32 only\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2973, __PRETTY_FUNCTION__))
;
2974
2975 // gpr_index
2976 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
2977 VAListPtr, MachinePointerInfo(SV), MVT::i8);
2978 InChain = GprIndex.getValue(1);
2979
2980 if (VT == MVT::i64) {
2981 // Check if GprIndex is even
2982 SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex,
2983 DAG.getConstant(1, dl, MVT::i32));
2984 SDValue CC64 = DAG.getSetCC(dl, MVT::i32, GprAnd,
2985 DAG.getConstant(0, dl, MVT::i32), ISD::SETNE);
2986 SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex,
2987 DAG.getConstant(1, dl, MVT::i32));
2988 // Align GprIndex to be even if it isn't
2989 GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne,
2990 GprIndex);
2991 }
2992
2993 // fpr index is 1 byte after gpr
2994 SDValue FprPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
2995 DAG.getConstant(1, dl, MVT::i32));
2996
2997 // fpr
2998 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
2999 FprPtr, MachinePointerInfo(SV), MVT::i8);
3000 InChain = FprIndex.getValue(1);
3001
3002 SDValue RegSaveAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
3003 DAG.getConstant(8, dl, MVT::i32));
3004
3005 SDValue OverflowAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
3006 DAG.getConstant(4, dl, MVT::i32));
3007
3008 // areas
3009 SDValue OverflowArea =
3010 DAG.getLoad(MVT::i32, dl, InChain, OverflowAreaPtr, MachinePointerInfo());
3011 InChain = OverflowArea.getValue(1);
3012
3013 SDValue RegSaveArea =
3014 DAG.getLoad(MVT::i32, dl, InChain, RegSaveAreaPtr, MachinePointerInfo());
3015 InChain = RegSaveArea.getValue(1);
3016
3017 // select overflow_area if index > 8
3018 SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex,
3019 DAG.getConstant(8, dl, MVT::i32), ISD::SETLT);
3020
3021 // adjustment constant gpr_index * 4/8
3022 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32,
3023 VT.isInteger() ? GprIndex : FprIndex,
3024 DAG.getConstant(VT.isInteger() ? 4 : 8, dl,
3025 MVT::i32));
3026
3027 // OurReg = RegSaveArea + RegConstant
3028 SDValue OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, RegSaveArea,
3029 RegConstant);
3030
3031 // Floating types are 32 bytes into RegSaveArea
3032 if (VT.isFloatingPoint())
3033 OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, OurReg,
3034 DAG.getConstant(32, dl, MVT::i32));
3035
3036 // increase {f,g}pr_index by 1 (or 2 if VT is i64)
3037 SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3038 VT.isInteger() ? GprIndex : FprIndex,
3039 DAG.getConstant(VT == MVT::i64 ? 2 : 1, dl,
3040 MVT::i32));
3041
3042 InChain = DAG.getTruncStore(InChain, dl, IndexPlus1,
3043 VT.isInteger() ? VAListPtr : FprPtr,
3044 MachinePointerInfo(SV), MVT::i8);
3045
3046 // determine if we should load from reg_save_area or overflow_area
3047 SDValue Result = DAG.getNode(ISD::SELECT, dl, PtrVT, CC, OurReg, OverflowArea);
3048
3049 // increase overflow_area by 4/8 if gpr/fpr > 8
3050 SDValue OverflowAreaPlusN = DAG.getNode(ISD::ADD, dl, PtrVT, OverflowArea,
3051 DAG.getConstant(VT.isInteger() ? 4 : 8,
3052 dl, MVT::i32));
3053
3054 OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea,
3055 OverflowAreaPlusN);
3056
3057 InChain = DAG.getTruncStore(InChain, dl, OverflowArea, OverflowAreaPtr,
3058 MachinePointerInfo(), MVT::i32);
3059
3060 return DAG.getLoad(VT, dl, InChain, Result, MachinePointerInfo());
3061}
3062
3063SDValue PPCTargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const {
3064 assert(!Subtarget.isPPC64() && "LowerVACOPY is PPC32 only")((!Subtarget.isPPC64() && "LowerVACOPY is PPC32 only"
) ? static_cast<void> (0) : __assert_fail ("!Subtarget.isPPC64() && \"LowerVACOPY is PPC32 only\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCISelLowering.cpp"
, 3064, __PRETTY_FUNCTION__))
;
3065
3066 // We have to copy the entire va_list struct:
3067 // 2*sizeof(char) + 2 Byte alignment + 2*sizeof(char*) = 12 Byte
3068 return DAG.getMemcpy(Op.getOperand(0), Op,
3069 Op.getOperand(1), Op.getOperand(2),
3070 DAG.getConstant(12, SDLoc(Op), MVT::i32), 8, false, true,
3071 false, MachinePointerInfo(), MachinePointerInfo());
3072}
3073
3074SDValue PPCTargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
3075 SelectionDAG &DAG) const {
3076 return Op.getOperand(0);
3077}
3078
3079SDValue PPCTargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
3080 SelectionDAG &DAG) const {
3081 SDValue Chain = Op.getOperand(0);
3082 SDValue Trmp = Op.getOperand(1); // trampoline
3083 SDValue FPtr = Op.getOperand(2); // nested function
3084 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
3085 SDLoc dl(Op);
3086
3087 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3088 bool isPPC64 = (PtrVT == MVT::i64);
3089 Type *IntPtrTy = DAG.getDataLayout().getIntPtrType(*DAG.getContext());
3090
3091 TargetLowering::ArgListTy Args;
3092 TargetLowering::ArgListEntry Entry;
3093
3094 Entry.Ty = IntPtrTy;
3095 Entry.Node = Trmp; Args.push_back(Entry);
3096
3097 // TrampSize == (isPPC64 ? 48 : 40);
3098 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40, dl,
3099 isPPC64 ? MVT::i64 : MVT::i32);
3100 Args.push_back(Entry);
3101
3102 Entry.Node = FPtr; Args.push_back(Entry);
3103 Entry.Node = Nest; Args.push_back(Entry);
3104
3105 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
3106 TargetLowering::CallLoweringInfo CLI(DAG);
3107 CLI.setDebugLoc(dl).setChain(Chain).setLibCallee(
3108 CallingConv::C, Type::getVoidTy(*DAG.getContext()),
3109 DAG.getExternalSymbol("__trampoline_setup", PtrVT), std::move(Args));
3110
3111 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
3112 return CallResult.second;
3113}
3114
3115SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
3116 MachineFunction &MF = DAG.getMachineFunction();
3117 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
3118 EVT PtrVT = getPointerTy(MF.getDataLayout());
3119
3120 SDLoc dl(Op);
3121
3122 if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) {
3123 // vastart just stores the address of the VarArgsFrameIndex slot into the
3124 // memory location argument.
3125 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
3126 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3127 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
3128 MachinePointerInfo(SV));
3129 }
3130
3131 // For the 32-bit SVR4 ABI we follow the layout of the va_list struct.
3132 // We suppose the given va_list is already allocated.
3133 //
3134 // typedef struct {
3135 // char gpr; /* index into the array of 8 GPRs
3136 // * stored in the register save area
3137 // * gpr=0 corresponds to r3,
3138 // * gpr=1 to r4, etc.
3139 // */
3140 // char fpr; /* index into the array of 8 FPRs
3141 // * stored in the register save area
3142 // * fpr=0 corresponds to f1,
3143 // * fpr=1 to f2, etc.
3144 // */
3145 // char *overflow_arg_area;
3146 // /* location on stack that holds
3147 // * the next overflow argument
3148 // */
3149 // char *reg_save_area;
3150 // /* where r3:r10 and f1:f8 (if saved)
3151 // * are stored
3152 // */
3153 // } va_list[1];
3154
3155 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), dl, MVT::i32);
3156 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), dl, MVT::i32);
3157 SDValue StackOffsetFI = DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(),
3158 PtrVT);
3159 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
3160 PtrVT);
3161
3162 uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
3163 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, dl, PtrVT);
3164
3165 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
3166 SDValue ConstStackOffset = DAG.getConstant(StackOffset, dl, PtrVT);
3167
3168 uint64_t FPROffset = 1;
3169 SDValue ConstFPROffset = DAG.getConstant(FPROffset, dl, PtrVT);
3170
3171 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3172
3173 // Store first byte : number of int regs
3174 SDValue firstStore =
3175 DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR, Op.getOperand(1),
3176 MachinePointerInfo(SV), MVT::i8);
3177 uint64_t nextOffset = FPROffset;
3178 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
3179 ConstFPROffset);
3180
3181 // Store second byte : number of float regs
3182 SDValue secondStore =
3183 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr,
3184 MachinePointerInfo(SV, nextOffset), MVT::i8);
3185 nextOffset += StackOffset;
3186 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
3187
3188 // Store second word : arguments given on stack
3189 SDValue thirdStore = DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr,
3190 MachinePointerInfo(SV, nextOffset));
3191 nextOffset += FrameOffset;
3192 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
3193
3194 // Store third word : arguments given in registers
3195 return DAG.getStore(thirdStore, dl, FR, nextPtr,
3196 MachinePointerInfo(SV, nextOffset));
3197}
3198
3199/// FPR - The set of FP registers that should be allocated for arguments,
3200/// on Darwin.
3201static const MCPhysReg FPR[] = {PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5,
3202 PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10,
3203 PPC::F11, PPC::F12, PPC::F13};
3204
3205/// QFPR - The set of QPX registers that should be allocated for arguments.
3206static const MCPhysReg QFPR[] = {
3207 PPC::QF1, PPC::QF2, PPC::QF3, PPC::QF4, PPC::QF5, PPC::QF6, PPC::QF7,
3208 PPC::QF8, PPC::QF9, PPC::QF10, PPC::QF11, PPC::QF12, PPC::QF13};
3209
3210/// CalculateStackSlotSize - Calculates the size reserved for this argument on
3211/// the stack.
3212static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags,
3213 unsigned PtrByteSize) {
3214 unsigned ArgSize = ArgVT.getStoreSize();
3215 if (Flags.isByVal())
3216 ArgSize = Flags.getByValSize();
3217
3218 // Round up to multiples of the pointer size, except for array members,
3219 // which are always packed.
3220 if (!Flags.isInConsecutiveRegs())
3221 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3222
3223 return ArgSize;
3224}
3225
3226/// CalculateStackSlotAlignment - Calculates the alignment of this argument
3227/// on the stack.
3228static unsigned CalculateStackSlotAlignment(EVT ArgVT, EVT OrigVT,
3229 ISD::ArgFlagsTy Flags,
3230 unsigned PtrByteSize) {
3231 unsigned Align = PtrByteSize;
3232
3233 // Altivec parameters are padded to a 16 byte boundary.
3234 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
3235 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
3236 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64 ||
3237 ArgVT == MVT::v1i128 || ArgVT == MVT::f128)
3238 Align = 16;
3239 // QPX vector types stored in double-precision are padded to a 32 byte
3240 // boundary.
3241 else if (ArgVT == MVT::v4f64 || ArgVT == MVT::v4i1)
3242 Align = 32;
3243
3244 // ByVal parameters are aligned as requested.
3245 if (Flags.isByVal()) {
3246 unsigned BVAlign = Flags.getByValAlign();
3247 if (BVAlign > PtrByteSize) {
3248 if (BVAlign % PtrByteSize != 0)
3249 llvm_unreachable(::llvm::llvm_unreachable_internal("ByVal alignment is not a multiple of the pointer size"
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCISelLowering.cpp"
, 3250)
3250 "ByVal alignment is not a multiple of the pointer size")::llvm::llvm_unreachable_internal("ByVal alignment is not a multiple of the pointer size"
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCISelLowering.cpp"
, 3250)
;
3251
3252 Align = BVAlign;
3253 }
3254 }
3255
3256 // Array members are always packed to their original alignment.
3257 if (Flags.isInConsecutiveRegs()) {
3258 // If the array member was split into multiple registers, the first
3259 // needs to be aligned to the size of the full type. (Except for
3260 // ppcf128, which is only aligned as its f64 components.)
3261 if (Flags.isSplit() && OrigVT != MVT::ppcf128)
3262 Align = OrigVT.getStoreSize();
3263 else
3264 Align = ArgVT.getStoreSize();
3265 }
3266
3267 return Align;
3268}
3269
3270/// CalculateStackSlotUsed - Return whether this argument will use its
3271/// stack slot (instead of being passed in registers). ArgOffset,
3272/// AvailableFPRs, and AvailableVRs must hold the current argument
3273/// position, and will be updated to account for this argument.
3274static bool CalculateStackSlotUsed(EVT ArgVT, EVT OrigVT,
3275 ISD::ArgFlagsTy Flags,
3276 unsigned PtrByteSize,
3277 unsigned LinkageSize,
3278 unsigned ParamAreaSize,
3279 unsigned &ArgOffset,
3280 unsigned &AvailableFPRs,
3281 unsigned &AvailableVRs, bool HasQPX) {
3282 bool UseMemory = false;
3283
3284 // Respect alignment of argument on the stack.
3285 unsigned Align =
3286 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
3287 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
3288 // If there's no space left in the argument save area, we must
3289 // use memory (this check also catches zero-sized arguments).
3290 if (ArgOffset >= LinkageSize + ParamAreaSize)
3291 UseMemory = true;
3292
3293 // Allocate argument on the stack.
3294 ArgOffset += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
3295 if (Flags.isInConsecutiveRegsLast())
3296 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3297 // If we overran the argument save area, we must use memory
3298 // (this check catches arguments passed partially in memory)
3299 if (ArgOffset > LinkageSize + ParamAreaSize)
3300 UseMemory = true;
3301
3302 // However, if the argument is actually passed in an FPR or a VR,
3303 // we don't use memory after all.
3304 if (!Flags.isByVal()) {
3305 if (ArgVT == MVT::f32 || ArgVT == MVT::f64 ||
3306 // QPX registers overlap with the scalar FP registers.
3307 (HasQPX && (ArgVT == MVT::v4f32 ||
3308 ArgVT == MVT::v4f64 ||
3309 ArgVT == MVT::v4i1)))
3310 if (AvailableFPRs > 0) {
3311 --AvailableFPRs;
3312 return false;
3313 }
3314 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
3315 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
3316 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64 ||
3317 ArgVT == MVT::v1i128 || ArgVT == MVT::f128)
3318 if (AvailableVRs > 0) {
3319 --AvailableVRs;
3320 return false;
3321 }
3322 }
3323
3324 return UseMemory;
3325}
3326
3327/// EnsureStackAlignment - Round stack frame size up from NumBytes to
3328/// ensure minimum alignment required for target.
3329static unsigned EnsureStackAlignment(const PPCFrameLowering *Lowering,
3330 unsigned NumBytes) {
3331 unsigned TargetAlign = Lowering->getStackAlignment();
3332 unsigned AlignMask = TargetAlign - 1;
3333 NumBytes = (NumBytes + AlignMask) & ~AlignMask;
3334 return NumBytes;
3335}
3336
3337SDValue PPCTargetLowering::LowerFormalArguments(
3338 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
3339 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
3340 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
3341 if (Subtarget.isSVR4ABI()) {
3342 if (Subtarget.isPPC64())
3343 return LowerFormalArguments_64SVR4(Chain, CallConv, isVarArg, Ins,
3344 dl, DAG, InVals);
3345 else
3346 return LowerFormalArguments_32SVR4(Chain, CallConv, isVarArg, Ins,
3347 dl, DAG, InVals);
3348 } else {
3349 return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins,
3350 dl, DAG, InVals);
3351 }
3352}
3353
3354SDValue PPCTargetLowering::LowerFormalArguments_32SVR4(
3355 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
3356 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
3357 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
3358
3359 // 32-bit SVR4 ABI Stack Frame Layout:
3360 // +-----------------------------------+
3361 // +--> | Back chain |
3362 // | +-----------------------------------+
3363 // | | Floating-point register save area |
3364 // | +-----------------------------------+
3365 // | | General register save area |
3366 // | +-----------------------------------+
3367 // | | CR save word |
3368 // | +-----------------------------------+
3369 // | | VRSAVE save word |
3370 // | +-----------------------------------+
3371 // | | Alignment padding |
3372 // | +-----------------------------------+
3373 // | | Vector register save area |
3374 // | +-----------------------------------+
3375 // | | Local variable space |
3376 // | +-----------------------------------+
3377 // | | Parameter list area |
3378 // | +-----------------------------------+
3379 // | | LR save word |
3380 // | +-----------------------------------+
3381 // SP--> +--- | Back chain |
3382 // +-----------------------------------+
3383 //
3384 // Specifications:
3385 // System V Application Binary Interface PowerPC Processor Supplement
3386 // AltiVec Technology Programming Interface Manual
3387
3388 MachineFunction &MF = DAG.getMachineFunction();
3389 MachineFrameInfo &MFI = MF.getFrameInfo();
3390 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
3391
3392 EVT PtrVT = getPointerTy(MF.getDataLayout());
3393 // Potential tail calls could cause overwriting of argument stack slots.
3394 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
3395 (CallConv == CallingConv::Fast));
3396 unsigned PtrByteSize = 4;
3397
3398 // Assign locations to all of the incoming arguments.
3399 SmallVector<CCValAssign, 16> ArgLocs;
3400 PPCCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
3401 *DAG.getContext());
3402
3403 // Reserve space for the linkage area on the stack.
3404 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
3405 CCInfo.AllocateStack(LinkageSize, PtrByteSize);
3406 if (useSoftFloat() || hasSPE())
3407 CCInfo.PreAnalyzeFormalArguments(Ins);
3408
3409 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4);
3410 CCInfo.clearWasPPCF128();
3411
3412 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3413 CCValAssign &VA = ArgLocs[i];
3414
3415 // Arguments stored in registers.
3416 if (VA.isRegLoc()) {
3417 const TargetRegisterClass *RC;
3418 EVT ValVT = VA.getValVT();
3419
3420 switch (ValVT.getSimpleVT().SimpleTy) {
3421 default:
3422 llvm_unreachable("ValVT not supported by formal arguments Lowering")::llvm::llvm_unreachable_internal("ValVT not supported by formal arguments Lowering"
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCISelLowering.cpp"
, 3422)
;
3423 case MVT::i1:
3424 case MVT::i32:
3425 RC = &PPC::GPRCRegClass;
3426 break;
3427 case MVT::f32:
3428 if (Subtarget.hasP8Vector())
3429 RC = &PPC::VSSRCRegClass;
3430 else if (Subtarget.hasSPE())
3431 RC = &PPC::SPE4RCRegClass;
3432 else
3433 RC = &PPC::F4RCRegClass;
3434 break;
3435 case MVT::f64:
3436 if (Subtarget.hasVSX())
3437 RC = &PPC::VSFRCRegClass;
3438 else if (Subtarget.hasSPE())
3439 RC = &PPC::SPERCRegClass;
3440 else
3441 RC = &PPC::F8RCRegClass;
3442 break;
3443 case MVT::v16i8:
3444 case MVT::v8i16:
3445 case MVT::v4i32:
3446 RC = &PPC::VRRCRegClass;
3447 break;
3448 case MVT::v4f32:
3449 RC = Subtarget.hasQPX() ? &PPC::QSRCRegClass : &PPC::VRRCRegClass;
3450 break;
3451 case MVT::v2f64:
3452 case MVT::v2i64:
3453 RC = &PPC::VRRCRegClass;
3454 break;
3455 case MVT::v4f64:
3456 RC = &PPC::QFRCRegClass;
3457 break;
3458 case MVT::v4i1:
3459 RC = &PPC::QBRCRegClass;
3460 break;
3461 }
3462
3463 // Transform the arguments stored in physical registers into virtual ones.
3464 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
3465 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg,
3466 ValVT == MVT::i1 ? MVT::i32 : ValVT);
3467
3468 if (ValVT == MVT::i1)
3469 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgValue);
3470
3471 InVals.push_back(ArgValue);
3472 } else {
3473 // Argument stored in memory.
3474 assert(VA.isMemLoc())((VA.isMemLoc()) ? static_cast<void> (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCISelLowering.cpp"
, 3474, __PRETTY_FUNCTION__))
;
3475
3476 // Get the extended size of the argument type in stack
3477 unsigned ArgSize = VA.getLocVT().getStoreSize();
3478 // Get the actual size of the argument type
3479 unsigned ObjSize = VA.getValVT().getStoreSize();
3480 unsigned ArgOffset = VA.getLocMemOffset();
3481 // Stack objects in PPC32 are right justified.
3482 ArgOffset += ArgSize - ObjSize;
3483 int FI = MFI.CreateFixedObject(ArgSize, ArgOffset, isImmutable);
3484
3485 // Create load nodes to retrieve arguments from the stack.
3486 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3487 InVals.push_back(
3488 DAG.getLoad(VA.getValVT(), dl, Chain, FIN, MachinePointerInfo()));
3489 }
3490 }
3491
3492 // Assign locations to all of the incoming aggregate by value arguments.
3493 // Aggregates passed by value are stored in the local variable space of the
3494 // caller's stack frame, right above the parameter list area.
3495 SmallVector<CCValAssign, 16> ByValArgLocs;
3496 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3497 ByValArgLocs, *DAG.getContext());
3498
3499 // Reserve stack space for the allocations in CCInfo.
3500 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
3501
3502 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4_ByVal);
3503
3504 // Area that is at least reserved in the caller of this function.
3505 unsigned MinReservedArea = CCByValInfo.getNextStackOffset();
3506 MinReservedArea = std::max(MinReservedArea, LinkageSize);
3507
3508 // Set the size that is at least reserved in caller of this function. Tail
3509 // call optimized function's reserved stack space needs to be aligned so that
3510 // taking the difference between two stack areas will result in an aligned
3511 // stack.
3512 MinReservedArea =
3513 EnsureStackAlignment(Subtarget.getFrameLowering(), MinReservedArea);
3514 FuncInfo->setMinReservedArea(MinReservedArea);
3515
3516 SmallVector<SDValue, 8> MemOps;
3517
3518 // If the function takes variable number of arguments, make a frame index for
3519 // the start of the first vararg value... for expansion of llvm.va_start.
3520 if (isVarArg) {
3521 static const MCPhysReg GPArgRegs[] = {
3522 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
3523 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
3524 };
3525 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
3526
3527 static const MCPhysReg FPArgRegs[] = {
3528 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
3529 PPC::F8
3530 };
3531 unsigned NumFPArgRegs = array_lengthof(FPArgRegs);
3532
3533 if (useSoftFloat() || hasSPE())
3534 NumFPArgRegs = 0;
3535
3536 FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs));
3537 FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs));
3538
3539 // Make room for NumGPArgRegs and NumFPArgRegs.
3540 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 +
3541 NumFPArgRegs * MVT(MVT::f64).getSizeInBits()/8;
3542
3543 FuncInfo->setVarArgsStackOffset(
3544 MFI.CreateFixedObject(PtrVT.getSizeInBits()/8,
3545 CCInfo.getNextStackOffset(), true));
3546
3547 FuncInfo->setVarArgsFrameIndex(MFI.CreateStackObject(Depth, 8, false));
3548 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
3549
3550 // The fixed integer arguments of a variadic function are stored to the
3551 // VarArgsFrameIndex on the stack so that they may be loaded by
3552 // dereferencing the result of va_next.
3553 for (unsigned GPRIndex = 0; GPRIndex != NumGPArgRegs; ++GPRIndex) {
3554 // Get an existing live-in vreg, or add a new one.
3555 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]);
3556 if (!VReg)
3557 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
3558
3559 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3560 SDValue Store =
3561 DAG.getStore(Val.getValue(1), dl, Val, FIN, MachinePointerInfo());
3562 MemOps.push_back(Store);
3563 // Increment the address by four for the next argument to store
3564 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, dl, PtrVT);
3565 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
3566 }
3567
3568 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6
3569 // is set.
3570 // The double arguments are stored to the VarArgsFrameIndex
3571 // on the stack.
3572 for (unsigned FPRIndex = 0; FPRIndex != NumFPArgRegs; ++FPRIndex) {
3573 // Get an existing live-in vreg, or add a new one.
3574 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]);
3575 if (!VReg)
3576 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
3577
3578 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
3579 SDValue Store =
3580 DAG.getStore(Val.getValue(1), dl, Val, FIN, MachinePointerInfo());
3581 MemOps.push_back(Store);
3582 // Increment the address by eight for the next argument to store
3583 SDValue PtrOff = DAG.getConstant(MVT(MVT::f64).getSizeInBits()/8, dl,
3584 PtrVT);
3585 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
3586 }
3587 }
3588
3589 if (!MemOps.empty())
3590 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
3591
3592 return Chain;
3593}
3594
3595// PPC64 passes i8, i16, and i32 values in i64 registers. Promote
3596// value to MVT::i64 and then truncate to the correct register size.
3597SDValue PPCTargetLowering::extendArgForPPC64(ISD::ArgFlagsTy Flags,
3598 EVT ObjectVT, SelectionDAG &DAG,
3599 SDValue ArgVal,
3600 const SDLoc &dl) const {
3601 if (Flags.isSExt())
3602 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
3603 DAG.getValueType(ObjectVT));
3604 else if (Flags.isZExt())
3605 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
3606 DAG.getValueType(ObjectVT));
3607
3608 return DAG.getNode(ISD::TRUNCATE, dl, ObjectVT, ArgVal);
3609}
3610
3611SDValue PPCTargetLowering::LowerFormalArguments_64SVR4(
3612 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
3613 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
3614 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
3615 // TODO: add description of PPC stack frame format, or at least some docs.
3616 //
3617 bool isELFv2ABI = Subtarget.isELFv2ABI();
3618 bool isLittleEndian = Subtarget.isLittleEndian();
3619 MachineFunction &MF = DAG.getMachineFunction();
3620 MachineFrameInfo &MFI = MF.getFrameInfo();
3621 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
3622
3623 assert(!(CallConv == CallingConv::Fast && isVarArg) &&((!(CallConv == CallingConv::Fast && isVarArg) &&
"fastcc not supported on varargs functions") ? static_cast<
void> (0) : __assert_fail ("!(CallConv == CallingConv::Fast && isVarArg) && \"fastcc not supported on varargs functions\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCISelLowering.cpp"
, 3624, __PRETTY_FUNCTION__))
3624 "fastcc not supported on varargs functions")((!(CallConv == CallingConv::Fast && isVarArg) &&
"fastcc not supported on varargs functions") ? static_cast<
void> (0) : __assert_fail ("!(CallConv == CallingConv::Fast && isVarArg) && \"fastcc not supported on varargs functions\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCISelLowering.cpp"
, 3624, __PRETTY_FUNCTION__))
;
3625
3626 EVT PtrVT = getPointerTy(MF.getDataLayout());
3627 // Potential tail calls could cause overwriting of argument stack slots.
3628 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
3629 (CallConv == CallingConv::Fast));
3630 unsigned PtrByteSize = 8;
3631 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
3632
3633 static const MCPhysReg GPR[] = {
3634 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
3635 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
3636 };
3637 static const MCPhysReg VR[] = {
3638 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
3639 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
3640 };
3641
3642 const unsigned Num_GPR_Regs = array_lengthof(GPR);
3643 const unsigned Num_FPR_Regs = useSoftFloat() ? 0 : 13;
3644 const unsigned Num_VR_Regs = array_lengthof(VR);
3645 const unsigned Num_QFPR_Regs = Num_FPR_Regs;
3646
3647 // Do a first pass over the arguments to determine whether the ABI
3648 // guarantees that our caller has allocated the parameter save area
3649 // on its stack frame. In the ELFv1 ABI, this is always the case;
3650 // in the ELFv2 ABI, it is true if this is a vararg function or if
3651 // any parameter is located in a stack slot.
3652
3653 bool HasParameterArea = !isELFv2ABI || isVarArg;
3654 unsigned ParamAreaSize = Num_GPR_Regs * PtrByteSize;
3655 unsigned NumBytes = LinkageSize;
3656 unsigned AvailableFPRs = Num_FPR_Regs;
3657 unsigned AvailableVRs = Num_VR_Regs;
3658 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3659 if (Ins[i].Flags.isNest())
3660 continue;
3661
3662 if (CalculateStackSlotUsed(Ins[i].VT, Ins[i].ArgVT, Ins[i].Flags,
3663 PtrByteSize, LinkageSize, ParamAreaSize,
3664 NumBytes, AvailableFPRs, AvailableVRs,
3665 Subtarget.hasQPX()))
3666 HasParameterArea = true;
3667 }
3668
3669 // Add DAG nodes to load the arguments or copy them out of registers. On
3670 // entry to a function on PPC, the arguments start after the linkage area,
3671 // although the first ones are often in registers.
3672
3673 unsigned ArgOffset = LinkageSize;
3674 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
3675 unsigned &QFPR_idx = FPR_idx;
3676 SmallVector<SDValue, 8> MemOps;
3677 Function::const_arg_iterator FuncArg = MF.getFunction().arg_begin();
3678 unsigned CurArgIdx = 0;
3679 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
3680 SDValue ArgVal;
3681 bool needsLoad = false;
3682 EVT ObjectVT = Ins[ArgNo].VT;
3683 EVT OrigVT = Ins[ArgNo].ArgVT;
3684 unsigned ObjSize = ObjectVT.getStoreSize();
3685 unsigned ArgSize = ObjSize;
3686 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
3687 if (Ins[ArgNo].isOrigArg()) {
3688 std::advance(FuncArg, Ins[ArgNo].getOrigArgIndex() - CurArgIdx);
3689 CurArgIdx = Ins[ArgNo].getOrigArgIndex();
3690 }
3691 // We re-align the argument offset for each argument, except when using the
3692 // fast calling convention, when we need to make sure we do that only when
3693 // we'll actually use a stack slot.
3694 unsigned CurArgOffset, Align;
3695 auto ComputeArgOffset = [&]() {
3696 /* Respect alignment of argument on the stack. */
3697 Align = CalculateStackSlotAlignment(ObjectVT, OrigVT, Flags, PtrByteSize);
3698 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
3699 CurArgOffset = ArgOffset;
3700 };
3701
3702 if (CallConv != CallingConv::Fast) {
3703 ComputeArgOffset();
3704
3705 /* Compute GPR index associated with argument offset. */
3706 GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
3707 GPR_idx = std::min(GPR_idx, Num_GPR_Regs);
3708 }
3709
3710 // FIXME the codegen can be much improved in some cases.
3711 // We do not have to keep everything in memory.
3712 if (Flags.isByVal()) {
3713 assert(Ins[ArgNo].isOrigArg() && "Byval arguments cannot be implicit")((Ins[ArgNo].isOrigArg() && "Byval arguments cannot be implicit"
) ? static_cast<void> (0) : __assert_fail ("Ins[ArgNo].isOrigArg() && \"Byval arguments cannot be implicit\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCISelLowering.cpp"
, 3713, __PRETTY_FUNCTION__))
;
3714
3715 if (CallConv == CallingConv::Fast)
3716 ComputeArgOffset();
3717
3718 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
3719 ObjSize = Flags.getByValSize();
3720 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3721 // Empty aggregate parameters do not take up registers. Examples:
3722 // struct { } a;
3723 // union { } b;
3724 // int c[0];
3725 // etc. However, we have to provide a place-holder in InVals, so
3726 // pretend we have an 8-byte item at the current address for that
3727 // purpose.
3728 if (!ObjSize) {
3729 int FI = MFI.CreateFixedObject(PtrByteSize, ArgOffset, true);
3730 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3731 InVals.push_back(FIN);
3732 continue;
3733 }
3734
3735 // Create a stack object covering all stack doublewords occupied
3736 // by the argument. If the argument is (fully or partially) on
3737 // the stack, or if the argument is fully in registers but the
3738 // caller has allocated the parameter save anyway, we can refer
3739 // directly to the caller's stack frame. Otherwise, create a
3740 // local copy in our own frame.
3741 int FI;
3742 if (HasParameterArea ||
3743 ArgSize + ArgOffset > LinkageSize + Num_GPR_Regs * PtrByteSize)
3744 FI = MFI.CreateFixedObject(ArgSize, ArgOffset, false, true);
3745 else
3746 FI = MFI.CreateStackObject(ArgSize, Align, false);
3747 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3748
3749 // Handle aggregates smaller than 8 bytes.
3750 if (ObjSize < PtrByteSize) {
3751 // The value of the object is its address, which differs from the
3752 // address of the enclosing doubleword on big-endian systems.
3753 SDValue Arg = FIN;
3754 if (!isLittleEndian) {
3755 SDValue ArgOff = DAG.getConstant(PtrByteSize - ObjSize, dl, PtrVT);
3756 Arg = DAG.getNode(ISD::ADD, dl, ArgOff.getValueType(), Arg, ArgOff);
3757 }
3758 InVals.push_back(Arg);
3759
3760 if (GPR_idx != Num_GPR_Regs) {
3761 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
3762 FuncInfo->addLiveInAttr(VReg, Flags);
3763 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3764 SDValue Store;
3765
3766 if (ObjSize==1 || ObjSize==2 || ObjSize==4) {
3767 EVT ObjType = (ObjSize == 1 ? MVT::i8 :
3768 (ObjSize == 2 ? MVT::i16 : MVT::i32));
3769 Store = DAG.getTruncStore(Val.getValue(1), dl, Val, Arg,
3770 MachinePointerInfo(&*FuncArg), ObjType);
3771 } else {
3772 // For sizes that don't fit a truncating store (3, 5, 6, 7),
3773 // store the whole register as-is to the parameter save area
3774 // slot.
3775 Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3776 MachinePointerInfo(&*FuncArg));
3777 }
3778
3779 MemOps.push_back(Store);
3780 }
3781 // Whether we copied from a register or not, advance the offset
3782 // into the parameter save area by a full doubleword.
3783 ArgOffset += PtrByteSize;
3784 continue;
3785 }
3786
3787 // The value of the object is its address, which is the address of
3788 // its first stack doubleword.
3789 InVals.push_back(FIN);
3790
3791 // Store whatever pieces of the object are in registers to memory.
3792 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
3793 if (GPR_idx == Num_GPR_Regs)
3794 break;
3795
3796 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3797 FuncInfo->addLiveInAttr(VReg, Flags);
3798 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3799 SDValue Addr = FIN;
3800 if (j) {
3801 SDValue Off = DAG.getConstant(j, dl, PtrVT);
3802 Addr = DAG.getNode(ISD::ADD, dl, Off.getValueType(), Addr, Off);
3803 }
3804 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, Addr,
3805 MachinePointerInfo(&*FuncArg, j));
3806 MemOps.push_back(Store);
3807 ++GPR_idx;
3808 }
3809 ArgOffset += ArgSize;
3810 continue;
3811 }
3812
3813 switch (ObjectVT.getSimpleVT().SimpleTy) {
3814 default: llvm_unreachable("Unhandled argument type!")::llvm::llvm_unreachable_internal("Unhandled argument type!",
"/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCISelLowering.cpp"
, 3814)
;
3815 case MVT::i1:
3816 case MVT::i32:
3817 case MVT::i64:
3818 if (Flags.isNest()) {
3819 // The 'nest' parameter, if any, is passed in R11.
3820 unsigned VReg = MF.addLiveIn(PPC::X11, &PPC::G8RCRegClass);
3821 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
3822
3823 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
3824 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
3825
3826 break;
3827 }
3828
3829 // These can be scalar arguments or elements of an integer array type
3830 // passed directly. Clang may use those instead of "byval" aggregate
3831 // types to avoid forcing arguments to memory unnecessarily.
3832 if (GPR_idx != Num_GPR_Regs) {
3833 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
3834 FuncInfo->addLiveInAttr(VReg, Flags);
3835 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
3836
3837 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
3838 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
3839 // value to MVT::i64 and then truncate to the correct register size.
3840 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
3841 } else {
3842 if (CallConv == CallingConv::Fast)
3843 ComputeArgOffset();
3844
3845 needsLoad = true;
3846 ArgSize = PtrByteSize;
3847 }
3848 if (CallConv != CallingConv::Fast || needsLoad)
3849 ArgOffset += 8;
3850 break;
3851
3852 case MVT::f32:
3853 case MVT::f64:
3854 // These can be scalar arguments or elements of a float array type
3855 // passed directly. The latter are used to implement ELFv2 homogenous
3856 // float aggregates.
3857 if (FPR_idx != Num_FPR_Regs) {
3858 unsigned VReg;
3859
3860 if (ObjectVT == MVT::f32)
3861 VReg = MF.addLiveIn(FPR[FPR_idx],
3862 Subtarget.hasP8Vector()
3863 ? &PPC::VSSRCRegClass
3864 : &PPC::F4RCRegClass);
3865 else
3866 VReg = MF.addLiveIn(FPR[FPR_idx], Subtarget.hasVSX()
3867 ? &PPC::VSFRCRegClass
3868 : &PPC::F8RCRegClass);
3869
3870 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3871 ++FPR_idx;
3872 } else if (GPR_idx != Num_GPR_Regs && CallConv != CallingConv::Fast) {
3873 // FIXME: We may want to re-enable this for CallingConv::Fast on the P8
3874 // once we support fp <-> gpr moves.
3875
3876 // This can only ever happen in the presence of f32 array types,
3877 // since otherwise we never run out of FPRs before running out
3878 // of GPRs.
3879 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
3880 FuncInfo->addLiveInAttr(VReg, Flags);
3881 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
3882
3883 if (ObjectVT == MVT::f32) {
3884 if ((ArgOffset % PtrByteSize) == (isLittleEndian ? 4 : 0))
3885 ArgVal = DAG.getNode(ISD::SRL, dl, MVT::i64, ArgVal,
3886 DAG.getConstant(32, dl, MVT::i32));
3887 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal);
3888 }
3889
3890 ArgVal = DAG.getNode(ISD::BITCAST, dl, ObjectVT, ArgVal);
3891 } else {
3892 if (CallConv == CallingConv::Fast)
3893 ComputeArgOffset();
3894
3895 needsLoad = true;
3896 }
3897
3898 // When passing an array of floats, the array occupies consecutive
3899 // space in the argument area; only round up to the next doubleword
3900 // at the end of the array. Otherwise, each float takes 8 bytes.
3901 if (CallConv != CallingConv::Fast || needsLoad) {
3902 ArgSize = Flags.isInConsecutiveRegs() ? ObjSize : PtrByteSize;
3903 ArgOffset += ArgSize;
3904 if (Flags.isInConsecutiveRegsLast())
3905 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3906 }
3907 break;
3908 case MVT::v4f32:
3909 case MVT::v4i32:
3910 case MVT::v8i16:
3911 case MVT::v16i8:
3912 case MVT::v2f64:
3913 case MVT::v2i64:
3914 case MVT::v1i128:
3915 case MVT::f128:
3916 if (!Subtarget.hasQPX()) {
3917 // These can be scalar arguments or elements of a vector array type
3918 // passed directly. The latter are used to implement ELFv2 homogenous
3919 // vector aggregates.
3920 if (VR_idx != Num_VR_Regs) {
3921 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
3922 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3923 ++VR_idx;
3924 } else {
3925 if (CallConv == CallingConv::Fast)
3926 ComputeArgOffset();
3927 needsLoad = true;
3928 }
3929 if (CallConv != CallingConv::Fast || needsLoad)
3930 ArgOffset += 16;
3931 break;
3932 } // not QPX
3933
3934 assert(ObjectVT.getSimpleVT().SimpleTy == MVT::v4f32 &&((ObjectVT.getSimpleVT().SimpleTy == MVT::v4f32 && "Invalid QPX parameter type"
) ? static_cast<void> (0) : __assert_fail ("ObjectVT.getSimpleVT().SimpleTy == MVT::v4f32 && \"Invalid QPX parameter type\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCISelLowering.cpp"
, 3935, __PRETTY_FUNCTION__))
3935 "Invalid QPX parameter type")((ObjectVT.getSimpleVT().SimpleTy == MVT::v4f32 && "Invalid QPX parameter type"
) ? static_cast<void> (0) : __assert_fail ("ObjectVT.getSimpleVT().SimpleTy == MVT::v4f32 && \"Invalid QPX parameter type\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCISelLowering.cpp"
, 3935, __PRETTY_FUNCTION__))
;
3936 LLVM_FALLTHROUGH[[clang::fallthrough]];
3937
3938 case MVT::v4f64:
3939 case MVT::v4i1:
3940 // QPX vectors are treated like their scalar floating-point subregisters
3941 // (except that they're larger).
3942 unsigned Sz = ObjectVT.getSimpleVT().SimpleTy == MVT::v4f32 ? 16 : 32;
3943 if (QFPR_idx != Num_QFPR_Regs) {
3944 const TargetRegisterClass *RC;
3945 switch (ObjectVT.getSimpleVT().SimpleTy) {
3946 case MVT::v4f64: RC = &PPC::QFRCRegClass; break;
3947 case MVT::v4f32: RC = &PPC::QSRCRegClass; break;
3948 default: RC = &PPC::QBRCRegClass; break;
3949 }
3950
3951 unsigned VReg = MF.addLiveIn(QFPR[QFPR_idx], RC);
3952 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3953 ++QFPR_idx;
3954 } else {
3955 if (CallConv == CallingConv::Fast)
3956 ComputeArgOffset();
3957 needsLoad = true;
3958 }
3959 if (CallConv != CallingConv::Fast || needsLoad)
3960 ArgOffset += Sz;
3961 break;
3962 }
3963
3964 // We need to load the argument to a virtual register if we determined
3965 // above that we ran out of physical registers of the appropriate type.
3966 if (needsLoad) {
3967 if (ObjSize < ArgSize && !isLittleEndian)
3968 CurArgOffset += ArgSize - ObjSize;
3969 int FI = MFI.CreateFixedObject(ObjSize, CurArgOffset, isImmutable);
3970 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3971 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo());
3972 }
3973
3974 InVals.push_back(ArgVal);
3975 }
3976
3977 // Area that is at least reserved in the caller of this function.
3978 unsigned MinReservedArea;
3979 if (HasParameterArea)
3980 MinReservedArea = std::max(ArgOffset, LinkageSize + 8 * PtrByteSize);
3981 else
3982 MinReservedArea = LinkageSize;
3983
3984 // Set the size that is at least reserved in caller of this function. Tail
3985 // call optimized functions' reserved stack space needs to be aligned so that
3986 // taking the difference between two stack areas will result in an aligned
3987 // stack.
3988 MinReservedArea =
3989 EnsureStackAlignment(Subtarget.getFrameLowering(), MinReservedArea);
3990 FuncInfo->setMinReservedArea(MinReservedArea);
3991
3992 // If the function takes variable number of arguments, make a frame index for
3993 // the start of the first vararg value... for expansion of llvm.va_start.
3994 if (isVarArg) {
3995 int Depth = ArgOffset;
3996
3997 FuncInfo->setVarArgsFrameIndex(
3998 MFI.CreateFixedObject(PtrByteSize, Depth, true));
3999 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
4000
4001 // If this function is vararg, store any remaining integer argument regs
4002 // to their spots on the stack so that they may be loaded by dereferencing
4003 // the result of va_next.
4004 for (GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
4005 GPR_idx < Num_GPR_Regs; ++GPR_idx) {
4006 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
4007 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
4008 SDValue Store =
4009 DAG.getStore(Val.getValue(1), dl, Val, FIN, MachinePointerInfo());
4010 MemOps.push_back(Store);
4011 // Increment the address by four for the next argument to store
4012 SDValue PtrOff = DAG.getConstant(PtrByteSize, dl, PtrVT);
4013 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
4014 }
4015 }
4016
4017 if (!MemOps.empty())
4018 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
4019
4020 return Chain;
4021}
4022
4023SDValue PPCTargetLowering::LowerFormalArguments_Darwin(
4024 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
4025 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
4026 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
4027 // TODO: add description of PPC stack frame format, or at least some docs.
4028 //
4029 MachineFunction &MF = DAG.getMachineFunction();
4030 MachineFrameInfo &MFI = MF.getFrameInfo();
4031 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
4032
4033 EVT PtrVT = getPointerTy(MF.getDataLayout());
4034 bool isPPC64 = PtrVT == MVT::i64;
4035 // Potential tail calls could cause overwriting of argument stack slots.
4036 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
4037 (CallConv == CallingConv::Fast));
4038 unsigned PtrByteSize = isPPC64 ? 8 : 4;
4039 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
4040 unsigned ArgOffset = LinkageSize;
4041 // Area that is at least reserved in caller of this function.
4042 unsigned MinReservedArea = ArgOffset;
4043
4044 static const MCPhysReg GPR_32[] = { // 32-bit registers.
4045 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
4046 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
4047 };
4048 static const MCPhysReg GPR_64[] = { // 64-bit registers.
4049 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4050 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4051 };
4052 static const MCPhysReg VR[] = {
4053 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4054 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4055 };
4056
4057 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
4058 const unsigned Num_FPR_Regs = useSoftFloat() ? 0 : 13;
4059 const unsigned Num_VR_Regs = array_lengthof( VR);
4060
4061 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
4062
4063 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
4064
4065 // In 32-bit non-varargs functions, the stack space for vectors is after the
4066 // stack space for non-vectors. We do not use this space unless we have
4067 // too many vectors to fit in registers, something that only occurs in
4068 // constructed examples:), but we have to walk the arglist to figure
4069 // that out...for the pathological case, compute VecArgOffset as the
4070 // start of the vector parameter area. Computing VecArgOffset is the
4071 // entire point of the following loop.
4072 unsigned VecArgOffset = ArgOffset;
4073 if (!isVarArg && !isPPC64) {
4074 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e;
4075 ++ArgNo) {
4076 EVT ObjectVT = Ins[ArgNo].VT;
4077 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
4078
4079 if (Flags.isByVal()) {
4080 // ObjSize is the true size, ArgSize rounded up to multiple of regs.
4081 unsigned ObjSize = Flags.getByValSize();
4082 unsigned ArgSize =
4083 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
4084 VecArgOffset += ArgSize;
4085 continue;
4086 }
4087
4088 switch(ObjectVT.getSimpleVT().SimpleTy) {
4089 default: llvm_unreachable("Unhandled argument type!")::llvm::llvm_unreachable_internal("Unhandled argument type!",
"/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCISelLowering.cpp"
, 4089)
;
4090 case MVT::i1:
4091 case MVT::i32:
4092 case MVT::f32:
4093 VecArgOffset += 4;
4094 break;
4095 case MVT::i64: // PPC64
4096 case MVT::f64:
4097 // FIXME: We are guaranteed to be !isPPC64 at this point.
4098 // Does MVT::i64 apply?
4099 VecArgOffset += 8;
4100 break;
4101 case MVT::v4f32:
4102 case MVT::v4i32:
4103 case MVT::v8i16:
4104 case MVT::v16i8:
4105 // Nothing to do, we're only looking at Nonvector args here.
4106 break;
4107 }
4108 }
4109 }
4110 // We've found where the vector parameter area in memory is. Skip the
4111 // first 12 parameters; these don't use that memory.
4112 VecArgOffset = ((VecArgOffset+15)/16)*16;
4113 VecArgOffset += 12*16;
4114
4115 // Add DAG nodes to load the arguments or copy them out of registers. On
4116 // entry to a function on PPC, the arguments start after the linkage area,
4117 // although the first ones are often in registers.
4118
4119 SmallVector<SDValue, 8> MemOps;
4120 unsigned nAltivecParamsAtEnd = 0;
4121 Function::const_arg_iterator FuncArg = MF.getFunction().arg_begin();
4122 unsigned CurArgIdx = 0;
4123 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
4124 SDValue ArgVal;
4125 bool needsLoad = false;
4126 EVT ObjectVT = Ins[ArgNo].VT;
4127 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
4128 unsigned ArgSize = ObjSize;
4129 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
4130 if (Ins[ArgNo].isOrigArg()) {
4131 std::advance(FuncArg, Ins[ArgNo].getOrigArgIndex() - CurArgIdx);
4132 CurArgIdx = Ins[ArgNo].getOrigArgIndex();
4133 }
4134 unsigned CurArgOffset = ArgOffset;
4135
4136 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
4137 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
4138 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
4139 if (isVarArg || isPPC64) {
4140 MinReservedArea = ((MinReservedArea+15)/16)*16;
4141 MinReservedArea += CalculateStackSlotSize(ObjectVT,
4142 Flags,
4143 PtrByteSize);
4144 } else nAltivecParamsAtEnd++;
4145 } else
4146 // Calculate min reserved area.
4147 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
4148 Flags,
4149 PtrByteSize);
4150
4151 // FIXME the codegen can be much improved in some cases.
4152 // We do not have to keep everything in memory.
4153 if (Flags.isByVal()) {
4154 assert(Ins[ArgNo].isOrigArg() && "Byval arguments cannot be implicit")((Ins[ArgNo].isOrigArg() && "Byval arguments cannot be implicit"
) ? static_cast<void> (0) : __assert_fail ("Ins[ArgNo].isOrigArg() && \"Byval arguments cannot be implicit\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCISelLowering.cpp"
, 4154, __PRETTY_FUNCTION__))
;
4155
4156 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
4157 ObjSize = Flags.getByValSize();
4158 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
4159 // Objects of size 1 and 2 are right justified, everything else is
4160 // left justified. This means the memory address is adjusted forwards.
4161 if (ObjSize==1 || ObjSize==2) {
4162 CurArgOffset = CurArgOffset + (4 - ObjSize);
4163 }
4164 // The value of the object is its address.
4165 int FI = MFI.CreateFixedObject(ObjSize, CurArgOffset, false, true);
4166 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
4167 InVals.push_back(FIN);
4168 if (ObjSize==1 || ObjSize==2) {
4169 if (GPR_idx != Num_GPR_Regs) {
4170 unsigned VReg;
4171 if (isPPC64)
4172 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
4173 else
4174 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
4175 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
4176 EVT ObjType = ObjSize == 1 ? MVT::i8 : MVT::i16;
4177 SDValue Store =
4178 DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
4179 MachinePointerInfo(&*FuncArg), ObjType);
4180 MemOps.push_back(Store);
4181 ++GPR_idx;
4182 }
4183
4184 ArgOffset += PtrByteSize;
4185
4186 continue;
4187 }
4188 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
4189 // Store whatever pieces of the object are in registers
4190 // to memory. ArgOffset will be the address of the beginning
4191 // of the object.
4192 if (GPR_idx != Num_GPR_Regs) {
4193 unsigned VReg;
4194 if (isPPC64)
4195 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
4196 else
4197 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
4198 int FI = MFI.CreateFixedObject(PtrByteSize, ArgOffset, true);
4199 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
4200 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
4201 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
4202 MachinePointerInfo(&*FuncArg, j));
4203 MemOps.push_back(Store);
4204 ++GPR_idx;
4205 ArgOffset += PtrByteSize;
4206 } else {
4207 ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
4208 break;
4209 }
4210 }
4211 continue;
4212 }
4213
4214 switch (ObjectVT.getSimpleVT().SimpleTy) {
4215 default: llvm_unreachable("Unhandled argument type!")::llvm::llvm_unreachable_internal("Unhandled argument type!",
"/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCISelLowering.cpp"
, 4215)
;
4216 case MVT::i1:
4217 case MVT::i32:
4218 if (!isPPC64) {
4219 if (GPR_idx != Num_GPR_Regs) {
4220 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
4221 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
4222
4223 if (ObjectVT == MVT::i1)
4224 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgVal);
4225
4226 ++GPR_idx;
4227 } else {
4228 needsLoad = true;
4229 ArgSize = PtrByteSize;
4230 }
4231 // All int arguments reserve stack space in the Darwin ABI.
4232 ArgOffset += PtrByteSize;
4233 break;
4234 }
4235 LLVM_FALLTHROUGH[[clang::fallthrough]];
4236 case MVT::i64: // PPC64
4237 if (GPR_idx != Num_GPR_Regs) {
4238 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
4239 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
4240
4241 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
4242 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
4243 // value to MVT::i64 and then truncate to the correct register size.
4244 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
4245
4246 ++GPR_idx;
4247 } else {
4248 needsLoad = true;
4249 ArgSize = PtrByteSize;
4250 }
4251 // All int arguments reserve stack space in the Darwin ABI.
4252 ArgOffset += 8;
4253 break;
4254
4255 case MVT::f32:
4256 case MVT::f64:
4257 // Every 4 bytes of argument space consumes one of the GPRs available for
4258 // argument passing.
4259 if (GPR_idx != Num_GPR_Regs) {
4260 ++GPR_idx;
4261 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
4262 ++GPR_idx;
4263 }
4264 if (FPR_idx != Num_FPR_Regs) {
4265 unsigned VReg;
4266
4267 if (ObjectVT == MVT::f32)
4268 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
4269 else
4270 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
4271
4272 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
4273 ++FPR_idx;
4274 } else {
4275 needsLoad = true;
4276 }
4277
4278 // All FP arguments reserve stack space in the Darwin ABI.
4279 ArgOffset += isPPC64 ? 8 : ObjSize;
4280 break;
4281 case MVT::v4f32:
4282 case MVT::v4i32:
4283 case MVT::v8i16:
4284 case MVT::v16i8:
4285 // Note that vector arguments in registers don't reserve stack space,
4286 // except in varargs functions.
4287 if (VR_idx != Num_VR_Regs) {
4288 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
4289 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
4290 if (isVarArg) {
4291 while ((ArgOffset % 16) != 0) {
4292 ArgOffset += PtrByteSize;
4293 if (GPR_idx != Num_GPR_Regs)
4294 GPR_idx++;
4295 }
4296 ArgOffset += 16;
4297 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
4298 }
4299 ++VR_idx;
4300 } else {
4301 if (!isVarArg && !isPPC64) {
4302 // Vectors go after all the nonvectors.
4303 CurArgOffset = VecArgOffset;
4304 VecArgOffset += 16;
4305 } else {
4306 // Vectors are aligned.
4307 ArgOffset = ((ArgOffset+15)/16)*16;
4308 CurArgOffset = ArgOffset;
4309 ArgOffset += 16;
4310 }
4311 needsLoad = true;
4312 }
4313 break;
4314 }
4315
4316 // We need to load the argument to a virtual register if we determined above
4317 // that we ran out of physical registers of the appropriate type.
4318 if (needsLoad) {
4319 int FI = MFI.CreateFixedObject(ObjSize,
4320 CurArgOffset + (ArgSize - ObjSize),
4321 isImmutable);
4322 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
4323 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo());
4324 }
4325
4326 InVals.push_back(ArgVal);
4327 }
4328
4329 // Allow for Altivec parameters at the end, if needed.
4330 if (nAltivecParamsAtEnd) {
4331 MinReservedArea = ((MinReservedArea+15)/16)*16;
4332 MinReservedArea += 16*nAltivecParamsAtEnd;
4333 }
4334
4335 // Area that is at least reserved in the caller of this function.
4336 MinReservedArea = std::max(MinReservedArea, LinkageSize + 8 * PtrByteSize);
4337
4338 // Set the size that is at least reserved in caller of this function. Tail
4339 // call optimized functions' reserved stack space needs to be aligned so that
4340 // taking the difference between two stack areas will result in an aligned
4341 // stack.
4342 MinReservedArea =
4343 EnsureStackAlignment(Subtarget.getFrameLowering(), MinReservedArea);
4344 FuncInfo->setMinReservedArea(MinReservedArea);
4345
4346 // If the function takes variable number of arguments, make a frame index for
4347 // the start of the first vararg value... for expansion of llvm.va_start.
4348 if (isVarArg) {
4349 int Depth = ArgOffset;
4350
4351 FuncInfo->setVarArgsFrameIndex(
4352 MFI.CreateFixedObject(PtrVT.getSizeInBits()/8,
4353 Depth, true));
4354 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
4355
4356 // If this function is vararg, store any remaining integer argument regs
4357 // to their spots on the stack so that they may be loaded by dereferencing
4358 // the result of va_next.
4359 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
4360 unsigned VReg;
4361
4362 if (isPPC64)
4363 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
4364 else
4365 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
4366
4367 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
4368 SDValue Store =
4369 DAG.getStore(Val.getValue(1), dl, Val, FIN, MachinePointerInfo());
4370 MemOps.push_back(Store);
4371 // Increment the address by four for the next argument to store
4372 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, dl, PtrVT);
4373 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
4374 }
4375 }
4376
4377 if (!MemOps.empty())
4378 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
4379
4380 return Chain;
4381}
4382
4383/// CalculateTailCallSPDiff - Get the amount the stack pointer has to be
4384/// adjusted to accommodate the arguments for the tailcall.
4385static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall,
4386 unsigned ParamSize) {
4387
4388 if (!isTailCall) return 0;
4389
4390 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>();
4391 unsigned CallerMinReservedArea = FI->getMinReservedArea();
4392 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
4393 // Remember only if the new adjustment is bigger.
4394 if (SPDiff < FI->getTailCallSPDelta())
4395 FI->setTailCallSPDelta(SPDiff);
4396
4397 return SPDiff;
4398}
4399
4400static bool isFunctionGlobalAddress(SDValue Callee);
4401
4402static bool
4403callsShareTOCBase(const Function *Caller, SDValue Callee,
4404 const TargetMachine &TM) {
4405 // If !G, Callee can be an external symbol.
4406 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
4407 if (!G)
4408 return false;
4409
4410 // The medium and large code models are expected to provide a sufficiently
4411 // large TOC to provide all data addressing needs of a module with a
4412 // single TOC. Since each module will be addressed with a single TOC then we
4413 // only need to check that caller and callee don't cross dso boundaries.
4414 if (CodeModel::Medium == TM.getCodeModel() ||
4415 CodeModel::Large == TM.getCodeModel())
4416 return TM.shouldAssumeDSOLocal(*Caller->getParent(), G->getGlobal());
4417
4418 // Otherwise we need to ensure callee and caller are in the same section,
4419 // since the linker may allocate multiple TOCs, and we don't know which
4420 // sections will belong to the same TOC base.
4421
4422 const GlobalValue *GV = G->getGlobal();
4423 if (!GV->isStrongDefinitionForLinker())
4424 return false;
4425
4426 // Any explicitly-specified sections and section prefixes must also match.
4427 // Also, if we're using -ffunction-sections, then each function is always in
4428 // a different section (the same is true for COMDAT functions).
4429 if (TM.getFunctionSections() || GV->hasComdat() || Caller->hasComdat() ||
4430 GV->getSection() != Caller->getSection())
4431 return false;
4432 if (const auto *F = dyn_cast<Function>(GV)) {
4433 if (F->getSectionPrefix() != Caller->getSectionPrefix())
4434 return false;
4435 }
4436
4437 // If the callee might be interposed, then we can't assume the ultimate call
4438 // target will be in the same section. Even in cases where we can assume that
4439 // interposition won't happen, in any case where the linker might insert a
4440 // stub to allow for interposition, we must generate code as though
4441 // interposition might occur. To understand why this matters, consider a
4442 // situation where: a -> b -> c where the arrows indicate calls. b and c are
4443 // in the same section, but a is in a different module (i.e. has a different
4444 // TOC base pointer). If the linker allows for interposition between b and c,
4445 // then it will generate a stub for the call edge between b and c which will
4446 // save the TOC pointer into the designated stack slot allocated by b. If we
4447 // return true here, and therefore allow a tail call between b and c, that
4448 // stack slot won't exist and the b -> c stub will end up saving b'c TOC base
4449 // pointer into the stack slot allocated by a (where the a -> b stub saved
4450 // a's TOC base pointer). If we're not considering a tail call, but rather,
4451 // whether a nop is needed after the call instruction in b, because the linker
4452 // will insert a stub, it might complain about a missing nop if we omit it
4453 // (although many don't complain in this case).
4454 if (!TM.shouldAssumeDSOLocal(*Caller->getParent(), GV))
4455 return false;
4456
4457 return true;
4458}
4459
4460static bool
4461needStackSlotPassParameters(const PPCSubtarget &Subtarget,
4462 const SmallVectorImpl<ISD::OutputArg> &Outs) {
4463 assert(Subtarget.isSVR4ABI() && Subtarget.isPPC64())((Subtarget.isSVR4ABI() && Subtarget.isPPC64()) ? static_cast
<void> (0) : __assert_fail ("Subtarget.isSVR4ABI() && Subtarget.isPPC64()"
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCISelLowering.cpp"
, 4463, __PRETTY_FUNCTION__))
;
4464
4465 const unsigned PtrByteSize = 8;
4466 const unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
4467
4468 static const MCPhysReg GPR[] = {
4469 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4470 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4471 };
4472 static const MCPhysReg VR[] = {
4473 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4474 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4475 };
4476
4477 const unsigned NumGPRs = array_lengthof(GPR);
4478 const unsigned NumFPRs = 13;
4479 const unsigned NumVRs = array_lengthof(VR);
4480 const unsigned ParamAreaSize = NumGPRs * PtrByteSize;
4481
4482 unsigned NumBytes = LinkageSize;
4483 unsigned AvailableFPRs = NumFPRs;
4484 unsigned AvailableVRs = NumVRs;
4485
4486 for (const ISD::OutputArg& Param : Outs) {
4487 if (Param.Flags.isNest()) continue;
4488
4489 if (CalculateStackSlotUsed(Param.VT, Param.ArgVT, Param.Flags,
4490 PtrByteSize, LinkageSize, ParamAreaSize,
4491 NumBytes, AvailableFPRs, AvailableVRs,
4492 Subtarget.hasQPX()))
4493 return true;
4494 }
4495 return false;
4496}
4497
4498static bool
4499hasSameArgumentList(const Function *CallerFn, ImmutableCallSite CS) {
4500 if (CS.arg_size() != CallerFn->arg_size())
4501 return false;
4502
4503 ImmutableCallSite::arg_iterator CalleeArgIter = CS.arg_begin();
4504 ImmutableCallSite::arg_iterator CalleeArgEnd = CS.arg_end();
4505 Function::const_arg_iterator CallerArgIter = CallerFn->arg_begin();
4506
4507 for (; CalleeArgIter != CalleeArgEnd; ++CalleeArgIter, ++CallerArgIter) {
4508 const Value* CalleeArg = *CalleeArgIter;
4509 const Value* CallerArg = &(*CallerArgIter);
4510 if (CalleeArg == CallerArg)
4511 continue;
4512
4513 // e.g. @caller([4 x i64] %a, [4 x i64] %b) {
4514 // tail call @callee([4 x i64] undef, [4 x i64] %b)
4515 // }
4516 // 1st argument of callee is undef and has the same type as caller.
4517 if (CalleeArg->getType() == CallerArg->getType() &&
4518 isa<UndefValue>(CalleeArg))
4519 continue;
4520
4521 return false;
4522 }
4523
4524 return true;
4525}
4526
4527// Returns true if TCO is possible between the callers and callees
4528// calling conventions.
4529static bool
4530areCallingConvEligibleForTCO_64SVR4(CallingConv::ID CallerCC,
4531 CallingConv::ID CalleeCC) {
4532 // Tail calls are possible with fastcc and ccc.
4533 auto isTailCallableCC = [] (CallingConv::ID CC){
4534 return CC == CallingConv::C || CC == CallingConv::Fast;
4535 };
4536 if (!isTailCallableCC(CallerCC) || !isTailCallableCC(CalleeCC))
4537 return false;
4538
4539 // We can safely tail call both fastcc and ccc callees from a c calling
4540 // convention caller. If the caller is fastcc, we may have less stack space
4541 // than a non-fastcc caller with the same signature so disable tail-calls in
4542 // that case.
4543 return CallerCC == CallingConv::C || CallerCC == CalleeCC;
4544}
4545
4546bool
4547PPCTargetLowering::IsEligibleForTailCallOptimization_64SVR4(
4548 SDValue Callee,
4549 CallingConv::ID CalleeCC,
4550 ImmutableCallSite CS,
4551 bool isVarArg,
4552 const SmallVectorImpl<ISD::OutputArg> &Outs,
4553 const SmallVectorImpl<ISD::InputArg> &Ins,
4554 SelectionDAG& DAG) const {
4555 bool TailCallOpt = getTargetMachine().Options.GuaranteedTailCallOpt;
4556
4557 if (DisableSCO && !TailCallOpt) return false;
4558
4559 // Variadic argument functions are not supported.
4560 if (isVarArg) return false;
4561
4562 auto &Caller = DAG.getMachineFunction().getFunction();
4563 // Check that the calling conventions are compatible for tco.
4564 if (!areCallingConvEligibleForTCO_64SVR4(Caller.getCallingConv(), CalleeCC))
4565 return false;
4566
4567 // Caller contains any byval parameter is not supported.
4568 if (any_of(Ins, [](const ISD::InputArg &IA) { return IA.Flags.isByVal(); }))
4569 return false;
4570
4571 // Callee contains any byval parameter is not supported, too.
4572 // Note: This is a quick work around, because in some cases, e.g.
4573 // caller's stack size > callee's stack size, we are still able to apply
4574 // sibling call optimization. For example, gcc is able to do SCO for caller1
4575 // in the following example, but not for caller2.
4576 // struct test {
4577 // long int a;
4578 // char ary[56];
4579 // } gTest;
4580 // __attribute__((noinline)) int callee(struct test v, struct test *b) {
4581 // b->a = v.a;
4582 // return 0;
4583 // }
4584 // void caller1(struct test a, struct test c, struct test *b) {
4585 // callee(gTest, b); }
4586 // void caller2(struct test *b) { callee(gTest, b); }
4587 if (any_of(Outs, [](const ISD::OutputArg& OA) { return OA.Flags.isByVal(); }))
4588 return false;
4589
4590 // If callee and caller use different calling conventions, we cannot pass
4591 // parameters on stack since offsets for the parameter area may be different.
4592 if (Caller.getCallingConv() != CalleeCC &&
4593 needStackSlotPassParameters(Subtarget, Outs))
4594 return false;
4595
4596 // No TCO/SCO on indirect call because Caller have to restore its TOC
4597 if (!isFunctionGlobalAddress(Callee) &&
4598 !isa<ExternalSymbolSDNode>(Callee))
4599 return false;
4600
4601 // If the caller and callee potentially have different TOC bases then we
4602 // cannot tail call since we need to restore the TOC pointer after the call.
4603 // ref: https://bugzilla.mozilla.org/show_bug.cgi?id=973977
4604 if (!callsShareTOCBase(&Caller, Callee, getTargetMachine()))
4605 return false;
4606
4607 // TCO allows altering callee ABI, so we don't have to check further.
4608 if (CalleeCC == CallingConv::Fast && TailCallOpt)
4609 return true;
4610
4611 if (DisableSCO) return false;
4612
4613 // If callee use the same argument list that caller is using, then we can
4614 // apply SCO on this case. If it is not, then we need to check if callee needs
4615 // stack for passing arguments.
4616 if (!hasSameArgumentList(&Caller, CS) &&
4617 needStackSlotPassParameters(Subtarget, Outs)) {
4618 return false;
4619 }
4620
4621 return true;
4622}
4623
4624/// IsEligibleForTailCallOptimization - Check whether the call is eligible
4625/// for tail call optimization. Targets which want to do tail call
4626/// optimization should implement this function.
4627bool
4628PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
4629 CallingConv::ID CalleeCC,
4630 bool isVarArg,
4631 const SmallVectorImpl<ISD::InputArg> &Ins,
4632 SelectionDAG& DAG) const {
4633 if (!getTargetMachine().Options.GuaranteedTailCallOpt)
4634 return false;
4635
4636 // Variable argument functions are not supported.
4637 if (isVarArg)
4638 return false;
4639
4640 MachineFunction &MF = DAG.getMachineFunction();
4641 CallingConv::ID CallerCC = MF.getFunction().getCallingConv();
4642 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
4643 // Functions containing by val parameters are not supported.
4644 for (unsigned i = 0; i != Ins.size(); i++) {
4645 ISD::ArgFlagsTy Flags = Ins[i].Flags;
4646 if (Flags.isByVal()) return false;
4647 }
4648
4649 // Non-PIC/GOT tail calls are supported.
4650 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
4651 return true;
4652
4653 // At the moment we can only do local tail calls (in same module, hidden
4654 // or protected) if we are generating PIC.
4655 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
4656 return G->getGlobal()->hasHiddenVisibility()
4657 || G->getGlobal()->hasProtectedVisibility();
4658 }
4659
4660 return false;
4661}
4662
4663/// isCallCompatibleAddress - Return the immediate to use if the specified
4664/// 32-bit value is representable in the immediate field of a BxA instruction.
4665static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
4666 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
4667 if (!C) return nullptr;
4668
4669 int Addr = C->getZExtValue();
4670 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
4671 SignExtend32<26>(Addr) != Addr)
4672 return nullptr; // Top 6 bits have to be sext of immediate.
4673
4674 return DAG
4675 .getConstant(
4676 (int)C->getZExtValue() >> 2, SDLoc(Op),
4677 DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout()))
4678 .getNode();
4679}
4680
4681namespace {
4682
4683struct TailCallArgumentInfo {
4684 SDValue Arg;
4685 SDValue FrameIdxOp;
4686 int FrameIdx = 0;
4687
4688 TailCallArgumentInfo() = default;
4689};
4690
4691} // end anonymous namespace
4692
4693/// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
4694static void StoreTailCallArgumentsToStackSlot(
4695 SelectionDAG &DAG, SDValue Chain,
4696 const SmallVectorImpl<TailCallArgumentInfo> &TailCallArgs,
4697 SmallVectorImpl<SDValue> &MemOpChains, const SDLoc &dl) {
4698 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {
4699 SDValue Arg = TailCallArgs[i].Arg;
4700 SDValue FIN = TailCallArgs[i].FrameIdxOp;
4701 int FI = TailCallArgs[i].FrameIdx;
4702 // Store relative to framepointer.
4703 MemOpChains.push_back(DAG.getStore(
4704 Chain, dl, Arg, FIN,
4705 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI)));
4706 }
4707}
4708
4709/// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to
4710/// the appropriate stack slot for the tail call optimized function call.
4711static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG, SDValue Chain,
4712 SDValue OldRetAddr, SDValue OldFP,
4713 int SPDiff, const SDLoc &dl) {
4714 if (SPDiff) {
4715 // Calculate the new stack slot for the return address.
4716 MachineFunction &MF = DAG.getMachineFunction();
4717 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
4718 const PPCFrameLowering *FL = Subtarget.getFrameLowering();
4719 bool isPPC64 = Subtarget.isPPC64();
4720 int SlotSize = isPPC64 ? 8 : 4;
4721 int NewRetAddrLoc = SPDiff + FL->getReturnSaveOffset();
4722 int NewRetAddr = MF.getFrameInfo().CreateFixedObject(SlotSize,
4723 NewRetAddrLoc, true);
4724 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
4725 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
4726 Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx,
4727 MachinePointerInfo::getFixedStack(MF, NewRetAddr));
4728
4729 // When using the 32/64-bit SVR4 ABI there is no need to move the FP stack
4730 // slot as the FP is never overwritten.
4731 if (Subtarget.isDarwinABI()) {
4732 int NewFPLoc = SPDiff + FL->getFramePointerSaveOffset();
4733 int NewFPIdx = MF.getFrameInfo().CreateFixedObject(SlotSize, NewFPLoc,
4734 true);
4735 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
4736 Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx,
4737 MachinePointerInfo::getFixedStack(
4738 DAG.getMachineFunction(), NewFPIdx));
4739 }
4740 }
4741 return Chain;
4742}
4743
4744/// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
4745/// the position of the argument.
4746static void
4747CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
4748 SDValue Arg, int SPDiff, unsigned ArgOffset,
4749 SmallVectorImpl<TailCallArgumentInfo>& TailCallArguments) {
4750 int Offset = ArgOffset + SPDiff;
4751 uint32_t OpSize = (Arg.getValueSizeInBits() + 7) / 8;
4752 int FI = MF.getFrameInfo().CreateFixedObject(OpSize, Offset, true);
4753 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
4754 SDValue FIN = DAG.getFrameIndex(FI, VT);
4755 TailCallArgumentInfo Info;
4756 Info.Arg = Arg;
4757 Info.FrameIdxOp = FIN;
4758 Info.FrameIdx = FI;
4759 TailCallArguments.push_back(Info);
4760}
4761
4762/// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address
4763/// stack slot. Returns the chain as result and the loaded frame pointers in
4764/// LROpOut/FPOpout. Used when tail calling.
4765SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(
4766 SelectionDAG &DAG, int SPDiff, SDValue Chain, SDValue &LROpOut,
4767 SDValue &FPOpOut, const SDLoc &dl) const {
4768 if (SPDiff) {
4769 // Load the LR and FP stack slot for later adjusting.
4770 EVT VT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32;
4771 LROpOut = getReturnAddrFrameIndex(DAG);
4772 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo());
4773 Chain = SDValue(LROpOut.getNode(), 1);
4774
4775 // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack
4776 // slot as the FP is never overwritten.
4777 if (Subtarget.isDarwinABI()) {
4778 FPOpOut = getFramePointerFrameIndex(DAG);
4779 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, MachinePointerInfo());
4780 Chain = SDValue(FPOpOut.getNode(), 1);
4781 }
4782 }
4783 return Chain;
4784}
4785
4786/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
4787/// by "Src" to address "Dst" of size "Size". Alignment information is
4788/// specified by the specific parameter attribute. The copy will be passed as
4789/// a byval function parameter.
4790/// Sometimes what we are copying is the end of a larger object, the part that
4791/// does not fit in registers.
4792static SDValue CreateCopyOfByValArgument(SDValue Src, SDValue Dst,
4793 SDValue Chain, ISD::ArgFlagsTy Flags,
4794 SelectionDAG &DAG, const SDLoc &dl) {
4795 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
4796 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
4797 false, false, false, MachinePointerInfo(),
4798 MachinePointerInfo());
4799}
4800
4801/// LowerMemOpCallTo - Store the argument to the stack or remember it in case of
4802/// tail calls.
4803static void LowerMemOpCallTo(
4804 SelectionDAG &DAG, MachineFunction &MF, SDValue Chain, SDValue Arg,
4805 SDValue PtrOff, int SPDiff, unsigned ArgOffset, bool isPPC64,
4806 bool isTailCall, bool isVector, SmallVectorImpl<SDValue> &MemOpChains,
4807 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments, const SDLoc &dl) {
4808 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
4809 if (!isTailCall) {
4810 if (isVector) {
4811 SDValue StackPtr;
4812 if (isPPC64)
4813 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4814 else
4815 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4816 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
4817 DAG.getConstant(ArgOffset, dl, PtrVT));
4818 }
4819 MemOpChains.push_back(
4820 DAG.getStore(Chain, dl, Arg, PtrOff, MachinePointerInfo()));
4821 // Calculate and remember argument location.
4822 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
4823 TailCallArguments);
4824}
4825
4826static void
4827PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain,
4828 const SDLoc &dl, int SPDiff, unsigned NumBytes, SDValue LROp,
4829 SDValue FPOp,
4830 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments) {
4831 // Emit a sequence of copyto/copyfrom virtual registers for arguments that
4832 // might overwrite each other in case of tail call optimization.
4833 SmallVector<SDValue, 8> MemOpChains2;
4834 // Do not flag preceding copytoreg stuff together with the following stuff.
4835 InFlag = SDValue();
4836 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
4837 MemOpChains2, dl);
4838 if (!MemOpChains2.empty())
4839 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
4840
4841 // Store the return address to the appropriate stack slot.
4842 Chain = EmitTailCallStoreFPAndRetAddr(DAG, Chain, LROp, FPOp, SPDiff, dl);
4843
4844 // Emit callseq_end just before tailcall node.
4845 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
4846 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
4847 InFlag = Chain.getValue(1);
4848}
4849
4850// Is this global address that of a function that can be called by name? (as
4851// opposed to something that must hold a descriptor for an indirect call).
4852static bool isFunctionGlobalAddress(SDValue Callee) {
4853 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
4854 if (Callee.getOpcode() == ISD::GlobalTLSAddress ||
4855 Callee.getOpcode() == ISD::TargetGlobalTLSAddress)
4856 return false;
4857
4858 return G->getGlobal()->getValueType()->isFunctionTy();
4859 }
4860
4861 return false;
4862}
4863
4864static unsigned
4865PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag, SDValue &Chain,
4866 SDValue CallSeqStart, const SDLoc &dl, int SPDiff, bool isTailCall,
4867 bool isPatchPoint, bool hasNest,
4868 SmallVectorImpl<std::pair<unsigned, SDValue>> &RegsToPass,
4869 SmallVectorImpl<SDValue> &Ops, std::vector<EVT> &NodeTys,
4870 ImmutableCallSite CS, const PPCSubtarget &Subtarget) {
4871 bool isPPC64 = Subtarget.isPPC64();
4872 bool isSVR4ABI = Subtarget.isSVR4ABI();
4873 bool isELFv2ABI = Subtarget.isELFv2ABI();
4874
4875 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
4876 NodeTys.push_back(MVT::Other); // Returns a chain
4877 NodeTys.push_back(MVT::Glue); // Returns a flag for retval copy to use.
4878
4879 unsigned CallOpc = PPCISD::CALL;
4880
4881 bool needIndirectCall = true;
4882 if (!isSVR4ABI || !isPPC64)
4883 if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) {
4884 // If this is an absolute destination address, use the munged value.
4885 Callee = SDValue(Dest, 0);
4886 needIndirectCall = false;
4887 }
4888
4889 // PC-relative references to external symbols should go through $stub, unless
4890 // we're building with the leopard linker or later, which automatically
4891 // synthesizes these stubs.
4892 const TargetMachine &TM = DAG.getTarget();
4893 const Module *Mod = DAG.getMachineFunction().getFunction().getParent();
4894 const GlobalValue *GV = nullptr;
4895 if (auto *G = dyn_cast<GlobalAddressSDNode>(Callee))
4896 GV = G->getGlobal();
4897 bool Local = TM.shouldAssumeDSOLocal(*Mod, GV);
4898 bool UsePlt = !Local && Subtarget.isTargetELF() && !isPPC64;
4899
4900 if (isFunctionGlobalAddress(Callee)) {
4901 GlobalAddressSDNode *G = cast<GlobalAddressSDNode>(Callee);
4902 // A call to a TLS address is actually an indirect call to a
4903 // thread-specific pointer.
4904 unsigned OpFlags = 0;
4905 if (UsePlt)
4906 OpFlags = PPCII::MO_PLT;
4907
4908 // If the callee is a GlobalAddress/ExternalSymbol node (quite common,
4909 // every direct call is) turn it into a TargetGlobalAddress /
4910 // TargetExternalSymbol node so that legalize doesn't hack it.
4911 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
4912 Callee.getValueType(), 0, OpFlags);
4913 needIndirectCall = false;
4914 }
4915
4916 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
4917 unsigned char OpFlags = 0;
4918
4919 if (UsePlt)
4920 OpFlags = PPCII::MO_PLT;
4921
4922 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType(),
4923 OpFlags);
4924 needIndirectCall = false;
4925 }
4926
4927 if (isPatchPoint) {
4928 // We'll form an invalid direct call when lowering a patchpoint; the full
4929 // sequence for an indirect call is complicated, and many of the
4930 // instructions introduced might have side effects (and, thus, can't be
4931 // removed later). The call itself will be removed as soon as the
4932 // argument/return lowering is complete, so the fact that it has the wrong
4933 // kind of operands should not really matter.
4934 needIndirectCall = false;
4935 }
4936
4937 if (needIndirectCall) {
4938 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
4939 // to do the call, we can't use PPCISD::CALL.
4940 SDValue MTCTROps[] = {Chain, Callee, InFlag};
4941
4942 if (isSVR4ABI && isPPC64 && !isELFv2ABI) {
4943 // Function pointers in the 64-bit SVR4 ABI do not point to the function
4944 // entry point, but to the function descriptor (the function entry point
4945 // address is part of the function descriptor though).
4946 // The function descriptor is a three doubleword structure with the
4947 // following fields: function entry point, TOC base address and
4948 // environment pointer.
4949 // Thus for a call through a function pointer, the following actions need
4950 // to be performed:
4951 // 1. Save the TOC of the caller in the TOC save area of its stack
4952 // frame (this is done in LowerCall_Darwin() or LowerCall_64SVR4()).
4953 // 2. Load the address of the function entry point from the function
4954 // descriptor.
4955 // 3. Load the TOC of the callee from the function descriptor into r2.
4956 // 4. Load the environment pointer from the function descriptor into
4957 // r11.
4958 // 5. Branch to the function entry point address.
4959 // 6. On return of the callee, the TOC of the caller needs to be
4960 // restored (this is done in FinishCall()).
4961 //
4962 // The loads are scheduled at the beginning of the call sequence, and the
4963 // register copies are flagged together to ensure that no other
4964 // operations can be scheduled in between. E.g. without flagging the
4965 // copies together, a TOC access in the caller could be scheduled between
4966 // the assignment of the callee TOC and the branch to the callee, which
4967 // results in the TOC access going through the TOC of the callee instead
4968 // of going through the TOC of the caller, which leads to incorrect code.
4969
4970 // Load the address of the function entry point from the function
4971 // descriptor.
4972 SDValue LDChain = CallSeqStart.getValue(CallSeqStart->getNumValues()-1);
4973 if (LDChain.getValueType() == MVT::Glue)
4974 LDChain = CallSeqStart.getValue(CallSeqStart->getNumValues()-2);
4975
4976 auto MMOFlags = Subtarget.hasInvariantFunctionDescriptors()
4977 ? (MachineMemOperand::MODereferenceable |
4978 MachineMemOperand::MOInvariant)
4979 : MachineMemOperand::MONone;
4980
4981 MachinePointerInfo MPI(CS ? CS.getCalledValue() : nullptr);
4982 SDValue LoadFuncPtr = DAG.getLoad(MVT::i64, dl, LDChain, Callee, MPI,
4983 /* Alignment = */ 8, MMOFlags);
4984
4985 // Load environment pointer into r11.
4986 SDValue PtrOff = DAG.getIntPtrConstant(16, dl);
4987 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff);
4988 SDValue LoadEnvPtr =
4989 DAG.getLoad(MVT::i64, dl, LDChain, AddPtr, MPI.getWithOffset(16),
4990 /* Alignment = */ 8, MMOFlags);
4991
4992 SDValue TOCOff = DAG.getIntPtrConstant(8, dl);
4993 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, TOCOff);
4994 SDValue TOCPtr =
4995 DAG.getLoad(MVT::i64, dl, LDChain, AddTOC, MPI.getWithOffset(8),
4996 /* Alignment = */ 8, MMOFlags);
4997
4998 setUsesTOCBasePtr(DAG);
4999 SDValue TOCVal = DAG.getCopyToReg(Chain, dl, PPC::X2, TOCPtr,
5000 InFlag);
5001 Chain = TOCVal.getValue(0);
5002 InFlag = TOCVal.getValue(1);
5003
5004 // If the function call has an explicit 'nest' parameter, it takes the
5005 // place of the environment pointer.
5006 if (!hasNest) {
5007 SDValue EnvVal = DAG.getCopyToReg(Chain, dl, PPC::X11, LoadEnvPtr,
5008 InFlag);
5009
5010 Chain = EnvVal.getValue(0);
5011 InFlag = EnvVal.getValue(1);
5012 }
5013
5014 MTCTROps[0] = Chain;
5015 MTCTROps[1] = LoadFuncPtr;
5016 MTCTROps[2] = InFlag;
5017 }
5018
5019 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys,
5020 makeArrayRef(MTCTROps, InFlag.getNode() ? 3 : 2));
5021 InFlag = Chain.getValue(1);
5022
5023 NodeTys.clear();
5024 NodeTys.push_back(MVT::Other);
5025 NodeTys.push_back(MVT::Glue);
5026 Ops.push_back(Chain);
5027 CallOpc = PPCISD::BCTRL;
5028 Callee.setNode(nullptr);
5029 // Add use of X11 (holding environment pointer)
5030 if (isSVR4ABI && isPPC64 && !isELFv2ABI && !hasNest)
5031 Ops.push_back(DAG.getRegister(PPC::X11, PtrVT));
5032 // Add CTR register as callee so a bctr can be emitted later.
5033 if (isTailCall)
5034 Ops.push_back(DAG.getRegister(isPPC64 ? PPC::CTR8 : PPC::CTR, PtrVT));
5035 }
5036
5037 // If this is a direct call, pass the chain and the callee.
5038 if (Callee.getNode()) {
5039 Ops.push_back(Chain);
5040 Ops.push_back(Callee);
5041 }
5042 // If this is a tail call add stack pointer delta.
5043 if (isTailCall)
5044 Ops.push_back(DAG.getConstant(SPDiff, dl, MVT::i32));
5045
5046 // Add argument registers to the end of the list so that they are known live
5047 // into the call.
5048 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
5049 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
5050 RegsToPass[i].second.getValueType()));
5051
5052 // All calls, in both the ELF V1 and V2 ABIs, need the TOC register live
5053 // into the call.
5054 // We do need to reserve X2 to appease the verifier for the PATCHPOINT.
5055 if (isSVR4ABI && isPPC64) {
5056 setUsesTOCBasePtr(DAG);
5057
5058 // We cannot add X2 as an operand here for PATCHPOINT, because there is no
5059 // way to mark dependencies as implicit here. We will add the X2 dependency
5060 // in EmitInstrWithCustomInserter.
5061 if (!isPatchPoint)
5062 Ops.push_back(DAG.getRegister(PPC::X2, PtrVT));
5063 }
5064
5065 return CallOpc;
5066}
5067
5068SDValue PPCTargetLowering::LowerCallResult(
5069 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
5070 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
5071 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
5072 SmallVector<CCValAssign, 16> RVLocs;
5073 CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
5074 *DAG.getContext());
5075
5076 CCRetInfo.AnalyzeCallResult(
5077 Ins, (Subtarget.isSVR4ABI() && CallConv == CallingConv::Cold)
5078 ? RetCC_PPC_Cold
5079 : RetCC_PPC);
5080
5081 // Copy all of the result registers out of their specified physreg.
5082 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
5083 CCValAssign &VA = RVLocs[i];
5084 assert(VA.isRegLoc() && "Can only return in registers!")((VA.isRegLoc() && "Can only return in registers!") ?
static_cast<void> (0) : __assert_fail ("VA.isRegLoc() && \"Can only return in registers!\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5084, __PRETTY_FUNCTION__))
;
5085
5086 SDValue Val = DAG.getCopyFromReg(Chain, dl,
5087 VA.getLocReg(), VA.getLocVT(), InFlag);
5088 Chain = Val.getValue(1);
5089 InFlag = Val.getValue(2);
5090
5091 switch (VA.getLocInfo()) {
5092 default: llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5092)
;
5093 case CCValAssign::Full: break;
5094 case CCValAssign::AExt:
5095 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
5096 break;
5097 case CCValAssign::ZExt:
5098 Val = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), Val,
5099 DAG.getValueType(VA.getValVT()));
5100 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
5101 break;
5102 case CCValAssign::SExt:
5103 Val = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), Val,
5104 DAG.getValueType(VA.getValVT()));
5105 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
5106 break;
5107 }
5108
5109 InVals.push_back(Val);
5110 }
5111
5112 return Chain;
5113}
5114
5115SDValue PPCTargetLowering::FinishCall(
5116 CallingConv::ID CallConv, const SDLoc &dl, bool isTailCall, bool isVarArg,
5117 bool isPatchPoint, bool hasNest, SelectionDAG &DAG,
5118 SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass, SDValue InFlag,
5119 SDValue Chain, SDValue CallSeqStart, SDValue &Callee, int SPDiff,
5120 unsigned NumBytes, const SmallVectorImpl<ISD::InputArg> &Ins,
5121 SmallVectorImpl<SDValue> &InVals, ImmutableCallSite CS) const {
5122 std::vector<EVT> NodeTys;
5123 SmallVector<SDValue, 8> Ops;
5124 unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, CallSeqStart, dl,
5125 SPDiff, isTailCall, isPatchPoint, hasNest,
5126 RegsToPass, Ops, NodeTys, CS, Subtarget);
5127
5128 // Add implicit use of CR bit 6 for 32-bit SVR4 vararg calls
5129 if (isVarArg && Subtarget.isSVR4ABI() && !Subtarget.isPPC64())
5130 Ops.push_back(DAG.getRegister(PPC::CR1EQ, MVT::i32));
5131
5132 // When performing tail call optimization the callee pops its arguments off
5133 // the stack. Account for this here so these bytes can be pushed back on in
5134 // PPCFrameLowering::eliminateCallFramePseudoInstr.
5135 int BytesCalleePops =
5136 (CallConv == CallingConv::Fast &&
5137 getTargetMachine().Options.GuaranteedTailCallOpt) ? NumBytes : 0;
5138
5139 // Add a register mask operand representing the call-preserved registers.
5140 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
5141 const uint32_t *Mask =
5142 TRI->getCallPreservedMask(DAG.getMachineFunction(), CallConv);
5143 assert(Mask && "Missing call preserved mask for calling convention")((Mask && "Missing call preserved mask for calling convention"
) ? static_cast<void> (0) : __assert_fail ("Mask && \"Missing call preserved mask for calling convention\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5143, __PRETTY_FUNCTION__))
;
5144 Ops.push_back(DAG.getRegisterMask(Mask));
5145
5146 if (InFlag.getNode())
5147 Ops.push_back(InFlag);
5148
5149 // Emit tail call.
5150 if (isTailCall) {
5151 assert(((Callee.getOpcode() == ISD::Register &&((((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode
>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() ==
ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress
|| isa<ConstantSDNode>(Callee)) && "Expecting an global address, external symbol, absolute value or register"
) ? static_cast<void> (0) : __assert_fail ("((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress || isa<ConstantSDNode>(Callee)) && \"Expecting an global address, external symbol, absolute value or register\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5156, __PRETTY_FUNCTION__))
5152 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) ||((((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode
>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() ==
ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress
|| isa<ConstantSDNode>(Callee)) && "Expecting an global address, external symbol, absolute value or register"
) ? static_cast<void> (0) : __assert_fail ("((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress || isa<ConstantSDNode>(Callee)) && \"Expecting an global address, external symbol, absolute value or register\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5156, __PRETTY_FUNCTION__))
5153 Callee.getOpcode() == ISD::TargetExternalSymbol ||((((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode
>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() ==
ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress
|| isa<ConstantSDNode>(Callee)) && "Expecting an global address, external symbol, absolute value or register"
) ? static_cast<void> (0) : __assert_fail ("((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress || isa<ConstantSDNode>(Callee)) && \"Expecting an global address, external symbol, absolute value or register\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5156, __PRETTY_FUNCTION__))
5154 Callee.getOpcode() == ISD::TargetGlobalAddress ||((((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode
>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() ==
ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress
|| isa<ConstantSDNode>(Callee)) && "Expecting an global address, external symbol, absolute value or register"
) ? static_cast<void> (0) : __assert_fail ("((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress || isa<ConstantSDNode>(Callee)) && \"Expecting an global address, external symbol, absolute value or register\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5156, __PRETTY_FUNCTION__))
5155 isa<ConstantSDNode>(Callee)) &&((((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode
>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() ==
ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress
|| isa<ConstantSDNode>(Callee)) && "Expecting an global address, external symbol, absolute value or register"
) ? static_cast<void> (0) : __assert_fail ("((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress || isa<ConstantSDNode>(Callee)) && \"Expecting an global address, external symbol, absolute value or register\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5156, __PRETTY_FUNCTION__))
5156 "Expecting an global address, external symbol, absolute value or register")((((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode
>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() ==
ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress
|| isa<ConstantSDNode>(Callee)) && "Expecting an global address, external symbol, absolute value or register"
) ? static_cast<void> (0) : __assert_fail ("((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress || isa<ConstantSDNode>(Callee)) && \"Expecting an global address, external symbol, absolute value or register\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5156, __PRETTY_FUNCTION__))
;
5157
5158 DAG.getMachineFunction().getFrameInfo().setHasTailCall();
5159 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, Ops);
5160 }
5161
5162 // Add a NOP immediately after the branch instruction when using the 64-bit
5163 // SVR4 or the AIX ABI.
5164 // At link time, if caller and callee are in a different module and
5165 // thus have a different TOC, the call will be replaced with a call to a stub
5166 // function which saves the current TOC, loads the TOC of the callee and
5167 // branches to the callee. The NOP will be replaced with a load instruction
5168 // which restores the TOC of the caller from the TOC save slot of the current
5169 // stack frame. If caller and callee belong to the same module (and have the
5170 // same TOC), the NOP will remain unchanged, or become some other NOP.
5171
5172 MachineFunction &MF = DAG.getMachineFunction();
5173 if (!isTailCall && !isPatchPoint &&
5174 ((Subtarget.isSVR4ABI() && Subtarget.isPPC64()) ||
5175 Subtarget.isAIXABI())) {
5176 if (CallOpc == PPCISD::BCTRL) {
5177 if (Subtarget.isAIXABI())
5178 report_fatal_error("Indirect call on AIX is not implemented.");
5179
5180 // This is a call through a function pointer.
5181 // Restore the caller TOC from the save area into R2.
5182 // See PrepareCall() for more information about calls through function
5183 // pointers in the 64-bit SVR4 ABI.
5184 // We are using a target-specific load with r2 hard coded, because the
5185 // result of a target-independent load would never go directly into r2,
5186 // since r2 is a reserved register (which prevents the register allocator
5187 // from allocating it), resulting in an additional register being
5188 // allocated and an unnecessary move instruction being generated.
5189 CallOpc = PPCISD::BCTRL_LOAD_TOC;
5190
5191 EVT PtrVT = getPointerTy(DAG.getDataLayout());
5192 SDValue StackPtr = DAG.getRegister(PPC::X1, PtrVT);
5193 unsigned TOCSaveOffset = Subtarget.getFrameLowering()->getTOCSaveOffset();
5194 SDValue TOCOff = DAG.getIntPtrConstant(TOCSaveOffset, dl);
5195 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, StackPtr, TOCOff);
5196
5197 // The address needs to go after the chain input but before the flag (or
5198 // any other variadic arguments).
5199 Ops.insert(std::next(Ops.begin()), AddTOC);
5200 } else if (CallOpc == PPCISD::CALL &&
5201 !callsShareTOCBase(&MF.getFunction(), Callee, DAG.getTarget())) {
5202 // Otherwise insert NOP for non-local calls.
5203 CallOpc = PPCISD::CALL_NOP;
5204 }
5205 }
5206
5207 Chain = DAG.getNode(CallOpc, dl, NodeTys, Ops);
5208 InFlag = Chain.getValue(1);
5209
5210 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
5211 DAG.getIntPtrConstant(BytesCalleePops, dl, true),
5212 InFlag, dl);
5213 if (!Ins.empty())
5214 InFlag = Chain.getValue(1);
5215
5216 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
5217 Ins, dl, DAG, InVals);
5218}
5219
5220SDValue
5221PPCTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
5222 SmallVectorImpl<SDValue> &InVals) const {
5223 SelectionDAG &DAG = CLI.DAG;
5224 SDLoc &dl = CLI.DL;
5225 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
5226 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
5227 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
5228 SDValue Chain = CLI.Chain;
5229 SDValue Callee = CLI.Callee;
5230 bool &isTailCall = CLI.IsTailCall;
5231 CallingConv::ID CallConv = CLI.CallConv;
5232 bool isVarArg = CLI.IsVarArg;
5233 bool isPatchPoint = CLI.IsPatchPoint;
5234 ImmutableCallSite CS = CLI.CS;
5235
5236 if (isTailCall) {
5237 if (Subtarget.useLongCalls() && !(CS && CS.isMustTailCall()))
5238 isTailCall = false;
5239 else if (Subtarget.isSVR4ABI() && Subtarget.isPPC64())
5240 isTailCall =
5241 IsEligibleForTailCallOptimization_64SVR4(Callee, CallConv, CS,
5242 isVarArg, Outs, Ins, DAG);
5243 else
5244 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg,
5245 Ins, DAG);
5246 if (isTailCall) {
5247 ++NumTailCalls;
5248 if (!getTargetMachine().Options.GuaranteedTailCallOpt)
5249 ++NumSiblingCalls;
5250
5251 assert(isa<GlobalAddressSDNode>(Callee) &&((isa<GlobalAddressSDNode>(Callee) && "Callee should be an llvm::Function object."
) ? static_cast<void> (0) : __assert_fail ("isa<GlobalAddressSDNode>(Callee) && \"Callee should be an llvm::Function object.\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5252, __PRETTY_FUNCTION__))
5252 "Callee should be an llvm::Function object.")((isa<GlobalAddressSDNode>(Callee) && "Callee should be an llvm::Function object."
) ? static_cast<void> (0) : __assert_fail ("isa<GlobalAddressSDNode>(Callee) && \"Callee should be an llvm::Function object.\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5252, __PRETTY_FUNCTION__))
;
5253 LLVM_DEBUG(do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("ppc-lowering")) { const GlobalValue *GV = cast<GlobalAddressSDNode
>(Callee)->getGlobal(); const unsigned Width = 80 - strlen
("TCO caller: ") - strlen(", callee linkage: 0, 0"); dbgs() <<
"TCO caller: " << left_justify(DAG.getMachineFunction(
).getName(), Width) << ", callee linkage: " << GV
->getVisibility() << ", " << GV->getLinkage
() << "\n"; } } while (false)
5254 const GlobalValue *GV =do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("ppc-lowering")) { const GlobalValue *GV = cast<GlobalAddressSDNode
>(Callee)->getGlobal(); const unsigned Width = 80 - strlen
("TCO caller: ") - strlen(", callee linkage: 0, 0"); dbgs() <<
"TCO caller: " << left_justify(DAG.getMachineFunction(
).getName(), Width) << ", callee linkage: " << GV
->getVisibility() << ", " << GV->getLinkage
() << "\n"; } } while (false)
5255 cast<GlobalAddressSDNode>(Callee)->getGlobal();do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("ppc-lowering")) { const GlobalValue *GV = cast<GlobalAddressSDNode
>(Callee)->getGlobal(); const unsigned Width = 80 - strlen
("TCO caller: ") - strlen(", callee linkage: 0, 0"); dbgs() <<
"TCO caller: " << left_justify(DAG.getMachineFunction(
).getName(), Width) << ", callee linkage: " << GV
->getVisibility() << ", " << GV->getLinkage
() << "\n"; } } while (false)
5256 const unsigned Width =do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("ppc-lowering")) { const GlobalValue *GV = cast<GlobalAddressSDNode
>(Callee)->getGlobal(); const unsigned Width = 80 - strlen
("TCO caller: ") - strlen(", callee linkage: 0, 0"); dbgs() <<
"TCO caller: " << left_justify(DAG.getMachineFunction(
).getName(), Width) << ", callee linkage: " << GV
->getVisibility() << ", " << GV->getLinkage
() << "\n"; } } while (false)
5257 80 - strlen("TCO caller: ") - strlen(", callee linkage: 0, 0");do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("ppc-lowering")) { const GlobalValue *GV = cast<GlobalAddressSDNode
>(Callee)->getGlobal(); const unsigned Width = 80 - strlen
("TCO caller: ") - strlen(", callee linkage: 0, 0"); dbgs() <<
"TCO caller: " << left_justify(DAG.getMachineFunction(
).getName(), Width) << ", callee linkage: " << GV
->getVisibility() << ", " << GV->getLinkage
() << "\n"; } } while (false)
5258 dbgs() << "TCO caller: "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("ppc-lowering")) { const GlobalValue *GV = cast<GlobalAddressSDNode
>(Callee)->getGlobal(); const unsigned Width = 80 - strlen
("TCO caller: ") - strlen(", callee linkage: 0, 0"); dbgs() <<
"TCO caller: " << left_justify(DAG.getMachineFunction(
).getName(), Width) << ", callee linkage: " << GV
->getVisibility() << ", " << GV->getLinkage
() << "\n"; } } while (false)
5259 << left_justify(DAG.getMachineFunction().getName(), Width)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("ppc-lowering")) { const GlobalValue *GV = cast<GlobalAddressSDNode
>(Callee)->getGlobal(); const unsigned Width = 80 - strlen
("TCO caller: ") - strlen(", callee linkage: 0, 0"); dbgs() <<
"TCO caller: " << left_justify(DAG.getMachineFunction(
).getName(), Width) << ", callee linkage: " << GV
->getVisibility() << ", " << GV->getLinkage
() << "\n"; } } while (false)
5260 << ", callee linkage: " << GV->getVisibility() << ", "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("ppc-lowering")) { const GlobalValue *GV = cast<GlobalAddressSDNode
>(Callee)->getGlobal(); const unsigned Width = 80 - strlen
("TCO caller: ") - strlen(", callee linkage: 0, 0"); dbgs() <<
"TCO caller: " << left_justify(DAG.getMachineFunction(
).getName(), Width) << ", callee linkage: " << GV
->getVisibility() << ", " << GV->getLinkage
() << "\n"; } } while (false)
5261 << GV->getLinkage() << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("ppc-lowering")) { const GlobalValue *GV = cast<GlobalAddressSDNode
>(Callee)->getGlobal(); const unsigned Width = 80 - strlen
("TCO caller: ") - strlen(", callee linkage: 0, 0"); dbgs() <<
"TCO caller: " << left_justify(DAG.getMachineFunction(
).getName(), Width) << ", callee linkage: " << GV
->getVisibility() << ", " << GV->getLinkage
() << "\n"; } } while (false)
;
5262 }
5263 }
5264
5265 if (!isTailCall && CS && CS.isMustTailCall())
5266 report_fatal_error("failed to perform tail call elimination on a call "
5267 "site marked musttail");
5268
5269 // When long calls (i.e. indirect calls) are always used, calls are always
5270 // made via function pointer. If we have a function name, first translate it
5271 // into a pointer.
5272 if (Subtarget.useLongCalls() && isa<GlobalAddressSDNode>(Callee) &&
5273 !isTailCall)
5274 Callee = LowerGlobalAddress(Callee, DAG);
5275
5276 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64())
5277 return LowerCall_64SVR4(Chain, Callee, CallConv, isVarArg,
5278 isTailCall, isPatchPoint, Outs, OutVals, Ins,
5279 dl, DAG, InVals, CS);
5280
5281 if (Subtarget.isSVR4ABI())
5282 return LowerCall_32SVR4(Chain, Callee, CallConv, isVarArg,
5283 isTailCall, isPatchPoint, Outs, OutVals, Ins,
5284 dl, DAG, InVals, CS);
5285
5286 if (Subtarget.isAIXABI())
5287 return LowerCall_AIX(Chain, Callee, CallConv, isVarArg,
5288 isTailCall, isPatchPoint, Outs, OutVals, Ins,
5289 dl, DAG, InVals, CS);
5290
5291 return LowerCall_Darwin(Chain, Callee, CallConv, isVarArg,
5292 isTailCall, isPatchPoint, Outs, OutVals, Ins,
5293 dl, DAG, InVals, CS);
5294}
5295
5296SDValue PPCTargetLowering::LowerCall_32SVR4(
5297 SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg,
5298 bool isTailCall, bool isPatchPoint,
5299 const SmallVectorImpl<ISD::OutputArg> &Outs,
5300 const SmallVectorImpl<SDValue> &OutVals,
5301 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
5302 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals,
5303 ImmutableCallSite CS) const {
5304 // See PPCTargetLowering::LowerFormalArguments_32SVR4() for a description
5305 // of the 32-bit SVR4 ABI stack frame layout.
5306
5307 assert((CallConv == CallingConv::C ||(((CallConv == CallingConv::C || CallConv == CallingConv::Cold
|| CallConv == CallingConv::Fast) && "Unknown calling convention!"
) ? static_cast<void> (0) : __assert_fail ("(CallConv == CallingConv::C || CallConv == CallingConv::Cold || CallConv == CallingConv::Fast) && \"Unknown calling convention!\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5309, __PRETTY_FUNCTION__))
5308 CallConv == CallingConv::Cold ||(((CallConv == CallingConv::C || CallConv == CallingConv::Cold
|| CallConv == CallingConv::Fast) && "Unknown calling convention!"
) ? static_cast<void> (0) : __assert_fail ("(CallConv == CallingConv::C || CallConv == CallingConv::Cold || CallConv == CallingConv::Fast) && \"Unknown calling convention!\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5309, __PRETTY_FUNCTION__))
5309 CallConv == CallingConv::Fast) && "Unknown calling convention!")(((CallConv == CallingConv::C || CallConv == CallingConv::Cold
|| CallConv == CallingConv::Fast) && "Unknown calling convention!"
) ? static_cast<void> (0) : __assert_fail ("(CallConv == CallingConv::C || CallConv == CallingConv::Cold || CallConv == CallingConv::Fast) && \"Unknown calling convention!\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5309, __PRETTY_FUNCTION__))
;
5310
5311 unsigned PtrByteSize = 4;
5312
5313 MachineFunction &MF = DAG.getMachineFunction();
5314
5315 // Mark this function as potentially containing a function that contains a
5316 // tail call. As a consequence the frame pointer will be used for dynamicalloc
5317 // and restoring the callers stack pointer in this functions epilog. This is
5318 // done because by tail calling the called function might overwrite the value
5319 // in this function's (MF) stack pointer stack slot 0(SP).
5320 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
5321 CallConv == CallingConv::Fast)
5322 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
5323
5324 // Count how many bytes are to be pushed on the stack, including the linkage
5325 // area, parameter list area and the part of the local variable space which
5326 // contains copies of aggregates which are passed by value.
5327
5328 // Assign locations to all of the outgoing arguments.
5329 SmallVector<CCValAssign, 16> ArgLocs;
5330 PPCCCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
5331
5332 // Reserve space for the linkage area on the stack.
5333 CCInfo.AllocateStack(Subtarget.getFrameLowering()->getLinkageSize(),
5334 PtrByteSize);
5335 if (useSoftFloat())
5336 CCInfo.PreAnalyzeCallOperands(Outs);
5337
5338 if (isVarArg) {
5339 // Handle fixed and variable vector arguments differently.
5340 // Fixed vector arguments go into registers as long as registers are
5341 // available. Variable vector arguments always go into memory.
5342 unsigned NumArgs = Outs.size();
5343
5344 for (unsigned i = 0; i != NumArgs; ++i) {
5345 MVT ArgVT = Outs[i].VT;
5346 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
5347 bool Result;
5348
5349 if (Outs[i].IsFixed) {
5350 Result = CC_PPC32_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags,
5351 CCInfo);
5352 } else {
5353 Result = CC_PPC32_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full,
5354 ArgFlags, CCInfo);
5355 }
5356
5357 if (Result) {
5358#ifndef NDEBUG
5359 errs() << "Call operand #" << i << " has unhandled type "
5360 << EVT(ArgVT).getEVTString() << "\n";
5361#endif
5362 llvm_unreachable(nullptr)::llvm::llvm_unreachable_internal(nullptr, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5362)
;
5363 }
5364 }
5365 } else {
5366 // All arguments are treated the same.
5367 CCInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4);
5368 }
5369 CCInfo.clearWasPPCF128();
5370
5371 // Assign locations to all of the outgoing aggregate by value arguments.
5372 SmallVector<CCValAssign, 16> ByValArgLocs;
5373 CCState CCByValInfo(CallConv, isVarArg, MF, ByValArgLocs, *DAG.getContext());
5374
5375 // Reserve stack space for the allocations in CCInfo.
5376 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
5377
5378 CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4_ByVal);
5379
5380 // Size of the linkage area, parameter list area and the part of the local
5381 // space variable where copies of aggregates which are passed by value are
5382 // stored.
5383 unsigned NumBytes = CCByValInfo.getNextStackOffset();
5384
5385 // Calculate by how many bytes the stack has to be adjusted in case of tail
5386 // call optimization.
5387 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
5388
5389 // Adjust the stack pointer for the new arguments...
5390 // These operations are automatically eliminated by the prolog/epilog pass
5391 Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, dl);
5392 SDValue CallSeqStart = Chain;
5393
5394 // Load the return address and frame pointer so it can be moved somewhere else
5395 // later.
5396 SDValue LROp, FPOp;
5397 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, dl);
5398
5399 // Set up a copy of the stack pointer for use loading and storing any
5400 // arguments that may not fit in the registers available for argument
5401 // passing.
5402 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
5403
5404 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
5405 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
5406 SmallVector<SDValue, 8> MemOpChains;
5407
5408 bool seenFloatArg = false;
5409 // Walk the register/memloc assignments, inserting copies/loads.
5410 for (unsigned i = 0, j = 0, e = ArgLocs.size();
5411 i != e;
5412 ++i) {
5413 CCValAssign &VA = ArgLocs[i];
5414 SDValue Arg = OutVals[i];
5415 ISD::ArgFlagsTy Flags = Outs[i].Flags;
5416
5417 if (Flags.isByVal()) {
5418 // Argument is an aggregate which is passed by value, thus we need to
5419 // create a copy of it in the local variable space of the current stack
5420 // frame (which is the stack frame of the caller) and pass the address of
5421 // this copy to the callee.
5422 assert((j < ByValArgLocs.size()) && "Index out of bounds!")(((j < ByValArgLocs.size()) && "Index out of bounds!"
) ? static_cast<void> (0) : __assert_fail ("(j < ByValArgLocs.size()) && \"Index out of bounds!\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5422, __PRETTY_FUNCTION__))
;
5423 CCValAssign &ByValVA = ByValArgLocs[j++];
5424 assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!")(((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!"
) ? static_cast<void> (0) : __assert_fail ("(VA.getValNo() == ByValVA.getValNo()) && \"ValNo mismatch!\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5424, __PRETTY_FUNCTION__))
;
5425
5426 // Memory reserved in the local variable space of the callers stack frame.
5427 unsigned LocMemOffset = ByValVA.getLocMemOffset();
5428
5429 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
5430 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(MF.getDataLayout()),
5431 StackPtr, PtrOff);
5432
5433 // Create a copy of the argument in the local area of the current
5434 // stack frame.
5435 SDValue MemcpyCall =
5436 CreateCopyOfByValArgument(Arg, PtrOff,
5437 CallSeqStart.getNode()->getOperand(0),
5438 Flags, DAG, dl);
5439
5440 // This must go outside the CALLSEQ_START..END.
5441 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall, NumBytes, 0,
5442 SDLoc(MemcpyCall));
5443 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
5444 NewCallSeqStart.getNode());
5445 Chain = CallSeqStart = NewCallSeqStart;
5446
5447 // Pass the address of the aggregate copy on the stack either in a
5448 // physical register or in the parameter list area of the current stack
5449 // frame to the callee.
5450 Arg = PtrOff;
5451 }
5452
5453 // When useCRBits() is true, there can be i1 arguments.
5454 // It is because getRegisterType(MVT::i1) => MVT::i1,
5455 // and for other integer types getRegisterType() => MVT::i32.
5456 // Extend i1 and ensure callee will get i32.
5457 if (Arg.getValueType() == MVT::i1)
5458 Arg = DAG.getNode(Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
5459 dl, MVT::i32, Arg);
5460
5461 if (VA.isRegLoc()) {
5462 seenFloatArg |= VA.getLocVT().isFloatingPoint();
5463 // Put argument in a physical register.
5464 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
5465 } else {
5466 // Put argument in the parameter list area of the current stack frame.
5467 assert(VA.isMemLoc())((VA.isMemLoc()) ? static_cast<void> (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5467, __PRETTY_FUNCTION__))
;
5468 unsigned LocMemOffset = VA.getLocMemOffset();
5469
5470 if (!isTailCall) {
5471 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
5472 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(MF.getDataLayout()),
5473 StackPtr, PtrOff);
5474
5475 MemOpChains.push_back(
5476 DAG.getStore(Chain, dl, Arg, PtrOff, MachinePointerInfo()));
5477 } else {
5478 // Calculate and remember argument location.
5479 CalculateTailCallArgDest(DAG, MF, false, Arg, SPDiff, LocMemOffset,
5480 TailCallArguments);
5481 }
5482 }
5483 }
5484
5485 if (!MemOpChains.empty())
5486 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
5487
5488 // Build a sequence of copy-to-reg nodes chained together with token chain
5489 // and flag operands which copy the outgoing args into the appropriate regs.
5490 SDValue InFlag;
5491 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
5492 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
5493 RegsToPass[i].second, InFlag);
5494 InFlag = Chain.getValue(1);
5495 }
5496
5497 // Set CR bit 6 to true if this is a vararg call with floating args passed in
5498 // registers.
5499 if (isVarArg) {
5500 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
5501 SDValue Ops[] = { Chain, InFlag };
5502
5503 Chain = DAG.getNode(seenFloatArg ? PPCISD::CR6SET : PPCISD::CR6UNSET,
5504 dl, VTs, makeArrayRef(Ops, InFlag.getNode() ? 2 : 1));
5505
5506 InFlag = Chain.getValue(1);
5507 }
5508
5509 if (isTailCall)
5510 PrepareTailCall(DAG, InFlag, Chain, dl, SPDiff, NumBytes, LROp, FPOp,
5511 TailCallArguments);
5512
5513 return FinishCall(CallConv, dl, isTailCall, isVarArg, isPatchPoint,
5514 /* unused except on PPC64 ELFv1 */ false, DAG,
5515 RegsToPass, InFlag, Chain, CallSeqStart, Callee, SPDiff,
5516 NumBytes, Ins, InVals, CS);
5517}
5518
5519// Copy an argument into memory, being careful to do this outside the
5520// call sequence for the call to which the argument belongs.
5521SDValue PPCTargetLowering::createMemcpyOutsideCallSeq(
5522 SDValue Arg, SDValue PtrOff, SDValue CallSeqStart, ISD::ArgFlagsTy Flags,
5523 SelectionDAG &DAG, const SDLoc &dl) const {
5524 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
5525 CallSeqStart.getNode()->getOperand(0),
5526 Flags, DAG, dl);
5527 // The MEMCPY must go outside the CALLSEQ_START..END.
5528 int64_t FrameSize = CallSeqStart.getConstantOperandVal(1);
5529 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall, FrameSize, 0,
5530 SDLoc(MemcpyCall));
5531 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
5532 NewCallSeqStart.getNode());
5533 return NewCallSeqStart;
5534}
5535
5536SDValue PPCTargetLowering::LowerCall_64SVR4(
5537 SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg,
5538 bool isTailCall, bool isPatchPoint,
5539 const SmallVectorImpl<ISD::OutputArg> &Outs,
5540 const SmallVectorImpl<SDValue> &OutVals,
5541 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
5542 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals,
5543 ImmutableCallSite CS) const {
5544 bool isELFv2ABI = Subtarget.isELFv2ABI();
5545 bool isLittleEndian = Subtarget.isLittleEndian();
5546 unsigned NumOps = Outs.size();
5547 bool hasNest = false;
5548 bool IsSibCall = false;
5549
5550 EVT PtrVT = getPointerTy(DAG.getDataLayout());
5551 unsigned PtrByteSize = 8;
5552
5553 MachineFunction &MF = DAG.getMachineFunction();
5554
5555 if (isTailCall && !getTargetMachine().Options.GuaranteedTailCallOpt)
5556 IsSibCall = true;
5557
5558 // Mark this function as potentially containing a function that contains a
5559 // tail call. As a consequence the frame pointer will be used for dynamicalloc
5560 // and restoring the callers stack pointer in this functions epilog. This is
5561 // done because by tail calling the called function might overwrite the value
5562 // in this function's (MF) stack pointer stack slot 0(SP).
5563 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
5564 CallConv == CallingConv::Fast)
5565 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
5566
5567 assert(!(CallConv == CallingConv::Fast && isVarArg) &&((!(CallConv == CallingConv::Fast && isVarArg) &&
"fastcc not supported on varargs functions") ? static_cast<
void> (0) : __assert_fail ("!(CallConv == CallingConv::Fast && isVarArg) && \"fastcc not supported on varargs functions\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5568, __PRETTY_FUNCTION__))
5568 "fastcc not supported on varargs functions")((!(CallConv == CallingConv::Fast && isVarArg) &&
"fastcc not supported on varargs functions") ? static_cast<
void> (0) : __assert_fail ("!(CallConv == CallingConv::Fast && isVarArg) && \"fastcc not supported on varargs functions\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5568, __PRETTY_FUNCTION__))
;
5569
5570 // Count how many bytes are to be pushed on the stack, including the linkage
5571 // area, and parameter passing area. On ELFv1, the linkage area is 48 bytes
5572 // reserved space for [SP][CR][LR][2 x unused][TOC]; on ELFv2, the linkage
5573 // area is 32 bytes reserved space for [SP][CR][LR][TOC].
5574 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
5575 unsigned NumBytes = LinkageSize;
5576 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
5577 unsigned &QFPR_idx = FPR_idx;
5578
5579 static const MCPhysReg GPR[] = {
5580 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
5581 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
5582 };
5583 static const MCPhysReg VR[] = {
5584 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
5585 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
5586 };
5587
5588 const unsigned NumGPRs = array_lengthof(GPR);
5589 const unsigned NumFPRs = useSoftFloat() ? 0 : 13;
5590 const unsigned NumVRs = array_lengthof(VR);
5591 const unsigned NumQFPRs = NumFPRs;
5592
5593 // On ELFv2, we can avoid allocating the parameter area if all the arguments
5594 // can be passed to the callee in registers.
5595 // For the fast calling convention, there is another check below.
5596 // Note: We should keep consistent with LowerFormalArguments_64SVR4()
5597 bool HasParameterArea = !isELFv2ABI || isVarArg || CallConv == CallingConv::Fast;
5598 if (!HasParameterArea) {
5599 unsigned ParamAreaSize = NumGPRs * PtrByteSize;
5600 unsigned AvailableFPRs = NumFPRs;
5601 unsigned AvailableVRs = NumVRs;
5602 unsigned NumBytesTmp = NumBytes;
5603 for (unsigned i = 0; i != NumOps; ++i) {
5604 if (Outs[i].Flags.isNest()) continue;
5605 if (CalculateStackSlotUsed(Outs[i].VT, Outs[i].ArgVT, Outs[i].Flags,
5606 PtrByteSize, LinkageSize, ParamAreaSize,
5607 NumBytesTmp, AvailableFPRs, AvailableVRs,
5608 Subtarget.hasQPX()))
5609 HasParameterArea = true;
5610 }
5611 }
5612
5613 // When using the fast calling convention, we don't provide backing for
5614 // arguments that will be in registers.
5615 unsigned NumGPRsUsed = 0, NumFPRsUsed = 0, NumVRsUsed = 0;
5616
5617 // Avoid allocating parameter area for fastcc functions if all the arguments
5618 // can be passed in the registers.
5619 if (CallConv == CallingConv::Fast)
5620 HasParameterArea = false;
5621
5622 // Add up all the space actually used.
5623 for (unsigned i = 0; i != NumOps; ++i) {
5624 ISD::ArgFlagsTy Flags = Outs[i].Flags;
5625 EVT ArgVT = Outs[i].VT;
5626 EVT OrigVT = Outs[i].ArgVT;
5627
5628 if (Flags.isNest())
5629 continue;
5630
5631 if (CallConv == CallingConv::Fast) {
5632 if (Flags.isByVal()) {
5633 NumGPRsUsed += (Flags.getByValSize()+7)/8;
5634 if (NumGPRsUsed > NumGPRs)
5635 HasParameterArea = true;
5636 } else {
5637 switch (ArgVT.getSimpleVT().SimpleTy) {
5638 default: llvm_unreachable("Unexpected ValueType for argument!")::llvm::llvm_unreachable_internal("Unexpected ValueType for argument!"
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5638)
;
5639 case MVT::i1:
5640 case MVT::i32:
5641 case MVT::i64:
5642 if (++NumGPRsUsed <= NumGPRs)
5643 continue;
5644 break;
5645 case MVT::v4i32:
5646 case MVT::v8i16:
5647 case MVT::v16i8:
5648 case MVT::v2f64:
5649 case MVT::v2i64:
5650 case MVT::v1i128:
5651 case MVT::f128:
5652 if (++NumVRsUsed <= NumVRs)
5653 continue;
5654 break;
5655 case MVT::v4f32:
5656 // When using QPX, this is handled like a FP register, otherwise, it
5657 // is an Altivec register.
5658 if (Subtarget.hasQPX()) {
5659 if (++NumFPRsUsed <= NumFPRs)
5660 continue;
5661 } else {
5662 if (++NumVRsUsed <= NumVRs)
5663 continue;
5664 }
5665 break;
5666 case MVT::f32:
5667 case MVT::f64:
5668 case MVT::v4f64: // QPX
5669 case MVT::v4i1: // QPX
5670 if (++NumFPRsUsed <= NumFPRs)
5671 continue;
5672 break;
5673 }
5674 HasParameterArea = true;
5675 }
5676 }
5677
5678 /* Respect alignment of argument on the stack. */
5679 unsigned Align =
5680 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
5681 NumBytes = ((NumBytes + Align - 1) / Align) * Align;
5682
5683 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
5684 if (Flags.isInConsecutiveRegsLast())
5685 NumBytes = ((NumBytes + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
5686 }
5687
5688 unsigned NumBytesActuallyUsed = NumBytes;
5689
5690 // In the old ELFv1 ABI,
5691 // the prolog code of the callee may store up to 8 GPR argument registers to
5692 // the stack, allowing va_start to index over them in memory if its varargs.
5693 // Because we cannot tell if this is needed on the caller side, we have to
5694 // conservatively assume that it is needed. As such, make sure we have at
5695 // least enough stack space for the caller to store the 8 GPRs.
5696 // In the ELFv2 ABI, we allocate the parameter area iff a callee
5697 // really requires memory operands, e.g. a vararg function.
5698 if (HasParameterArea)
5699 NumBytes = std::max(NumBytes, LinkageSize + 8 * PtrByteSize);
5700 else
5701 NumBytes = LinkageSize;
5702
5703 // Tail call needs the stack to be aligned.
5704 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
5705 CallConv == CallingConv::Fast)
5706 NumBytes = EnsureStackAlignment(Subtarget.getFrameLowering(), NumBytes);
5707
5708 int SPDiff = 0;
5709
5710 // Calculate by how many bytes the stack has to be adjusted in case of tail
5711 // call optimization.
5712 if (!IsSibCall)
5713 SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
5714
5715 // To protect arguments on the stack from being clobbered in a tail call,
5716 // force all the loads to happen before doing any other lowering.
5717 if (isTailCall)
5718 Chain = DAG.getStackArgumentTokenFactor(Chain);
5719
5720 // Adjust the stack pointer for the new arguments...
5721 // These operations are automatically eliminated by the prolog/epilog pass
5722 if (!IsSibCall)
5723 Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, dl);
5724 SDValue CallSeqStart = Chain;
5725
5726 // Load the return address and frame pointer so it can be move somewhere else
5727 // later.
5728 SDValue LROp, FPOp;
5729 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, dl);
5730
5731 // Set up a copy of the stack pointer for use loading and storing any
5732 // arguments that may not fit in the registers available for argument
5733 // passing.
5734 SDValue StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
5735
5736 // Figure out which arguments are going to go in registers, and which in
5737 // memory. Also, if this is a vararg function, floating point operations
5738 // must be stored to our stack, and loaded into integer regs as well, if
5739 // any integer regs are available for argument passing.
5740 unsigned ArgOffset = LinkageSize;
5741
5742 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
5743 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
5744
5745 SmallVector<SDValue, 8> MemOpChains;
5746 for (unsigned i = 0; i != NumOps; ++i) {
5747 SDValue Arg = OutVals[i];
5748 ISD::ArgFlagsTy Flags = Outs[i].Flags;
5749 EVT ArgVT = Outs[i].VT;
5750 EVT OrigVT = Outs[i].ArgVT;
5751
5752 // PtrOff will be used to store the current argument to the stack if a
5753 // register cannot be found for it.
5754 SDValue PtrOff;
5755
5756 // We re-align the argument offset for each argument, except when using the
5757 // fast calling convention, when we need to make sure we do that only when
5758 // we'll actually use a stack slot.
5759 auto ComputePtrOff = [&]() {
5760 /* Respect alignment of argument on the stack. */
5761 unsigned Align =
5762 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
5763 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
5764
5765 PtrOff = DAG.getConstant(ArgOffset, dl, StackPtr.getValueType());
5766
5767 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
5768 };
5769
5770 if (CallConv != CallingConv::Fast) {
5771 ComputePtrOff();
5772
5773 /* Compute GPR index associated with argument offset. */
5774 GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
5775 GPR_idx = std::min(GPR_idx, NumGPRs);
5776 }
5777
5778 // Promote integers to 64-bit values.
5779 if (Arg.getValueType() == MVT::i32 || Arg.getValueType() == MVT::i1) {
5780 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
5781 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
5782 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
5783 }
5784
5785 // FIXME memcpy is used way more than necessary. Correctness first.
5786 // Note: "by value" is code for passing a structure by value, not
5787 // basic types.
5788 if (Flags.isByVal()) {
5789 // Note: Size includes alignment padding, so
5790 // struct x { short a; char b; }
5791 // will have Size = 4. With #pragma pack(1), it will have Size = 3.
5792 // These are the proper values we need for right-justifying the
5793 // aggregate in a parameter register.
5794 unsigned Size = Flags.getByValSize();
5795
5796 // An empty aggregate parameter takes up no storage and no
5797 // registers.
5798 if (Size == 0)
5799 continue;
5800
5801 if (CallConv == CallingConv::Fast)
5802 ComputePtrOff();
5803
5804 // All aggregates smaller than 8 bytes must be passed right-justified.
5805 if (Size==1 || Size==2 || Size==4) {
5806 EVT VT = (Size==1) ? MVT::i8 : ((Size==2) ? MVT::i16 : MVT::i32);
5807 if (GPR_idx != NumGPRs) {
5808 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
5809 MachinePointerInfo(), VT);
5810 MemOpChains.push_back(Load.getValue(1));
5811 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5812
5813 ArgOffset += PtrByteSize;
5814 continue;
5815 }
5816 }
5817
5818 if (GPR_idx == NumGPRs && Size < 8) {
5819 SDValue AddPtr = PtrOff;
5820 if (!isLittleEndian) {
5821 SDValue Const = DAG.getConstant(PtrByteSize - Size, dl,
5822 PtrOff.getValueType());
5823 AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
5824 }
5825 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
5826 CallSeqStart,
5827 Flags, DAG, dl);
5828 ArgOffset += PtrByteSize;
5829 continue;
5830 }
5831 // Copy entire object into memory. There are cases where gcc-generated
5832 // code assumes it is there, even if it could be put entirely into
5833 // registers. (This is not what the doc says.)
5834
5835 // FIXME: The above statement is likely due to a misunderstanding of the
5836 // documents. All arguments must be copied into the parameter area BY
5837 // THE CALLEE in the event that the callee takes the address of any
5838 // formal argument. That has not yet been implemented. However, it is
5839 // reasonable to use the stack area as a staging area for the register
5840 // load.
5841
5842 // Skip this for small aggregates, as we will use the same slot for a
5843 // right-justified copy, below.
5844 if (Size >= 8)
5845 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
5846 CallSeqStart,
5847 Flags, DAG, dl);
5848
5849 // When a register is available, pass a small aggregate right-justified.
5850 if (Size < 8 && GPR_idx != NumGPRs) {
5851 // The easiest way to get this right-justified in a register
5852 // is to copy the structure into the rightmost portion of a
5853 // local variable slot, then load the whole slot into the
5854 // register.
5855 // FIXME: The memcpy seems to produce pretty awful code for
5856 // small aggregates, particularly for packed ones.
5857 // FIXME: It would be preferable to use the slot in the
5858 // parameter save area instead of a new local variable.
5859 SDValue AddPtr = PtrOff;
5860 if (!isLittleEndian) {
5861 SDValue Const = DAG.getConstant(8 - Size, dl, PtrOff.getValueType());
5862 AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
5863 }
5864 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
5865 CallSeqStart,
5866 Flags, DAG, dl);
5867
5868 // Load the slot into the register.
5869 SDValue Load =
5870 DAG.getLoad(PtrVT, dl, Chain, PtrOff, MachinePointerInfo());
5871 MemOpChains.push_back(Load.getValue(1));
5872 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5873
5874 // Done with this argument.
5875 ArgOffset += PtrByteSize;
5876 continue;
5877 }
5878
5879 // For aggregates larger than PtrByteSize, copy the pieces of the
5880 // object that fit into registers from the parameter save area.
5881 for (unsigned j=0; j<Size; j+=PtrByteSize) {
5882 SDValue Const = DAG.getConstant(j, dl, PtrOff.getValueType());
5883 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
5884 if (GPR_idx != NumGPRs) {
5885 SDValue Load =
5886 DAG.getLoad(PtrVT, dl, Chain, AddArg, MachinePointerInfo());
5887 MemOpChains.push_back(Load.getValue(1));
5888 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5889 ArgOffset += PtrByteSize;
5890 } else {
5891 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
5892 break;
5893 }
5894 }
5895 continue;
5896 }
5897
5898 switch (Arg.getSimpleValueType().SimpleTy) {
5899 default: llvm_unreachable("Unexpected ValueType for argument!")::llvm::llvm_unreachable_internal("Unexpected ValueType for argument!"
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5899)
;
5900 case MVT::i1:
5901 case MVT::i32:
5902 case MVT::i64:
5903 if (Flags.isNest()) {
5904 // The 'nest' parameter, if any, is passed in R11.
5905 RegsToPass.push_back(std::make_pair(PPC::X11, Arg));
5906 hasNest = true;
5907 break;
5908 }
5909
5910 // These can be scalar arguments or elements of an integer array type
5911 // passed directly. Clang may use those instead of "byval" aggregate
5912 // types to avoid forcing arguments to memory unnecessarily.
5913 if (GPR_idx != NumGPRs) {
5914 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
5915 } else {
5916 if (CallConv == CallingConv::Fast)
5917 ComputePtrOff();
5918
5919 assert(HasParameterArea &&((HasParameterArea && "Parameter area must exist to pass an argument in memory."
) ? static_cast<void> (0) : __assert_fail ("HasParameterArea && \"Parameter area must exist to pass an argument in memory.\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5920, __PRETTY_FUNCTION__))
5920 "Parameter area must exist to pass an argument in memory.")((HasParameterArea && "Parameter area must exist to pass an argument in memory."
) ? static_cast<void> (0) : __assert_fail ("HasParameterArea && \"Parameter area must exist to pass an argument in memory.\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5920, __PRETTY_FUNCTION__))
;
5921 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5922 true, isTailCall, false, MemOpChains,
5923 TailCallArguments, dl);
5924 if (CallConv == CallingConv::Fast)
5925</