Bug Summary

File:lib/Target/PowerPC/PPCISelLowering.cpp
Warning:line 8274, column 31
1st function call argument is an uninitialized value

Annotated Source Code

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clang -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name PPCISelLowering.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-eagerly-assume -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -mrelocation-model pic -pic-level 2 -mthread-model posix -fmath-errno -masm-verbose -mconstructor-aliases -munwind-tables -fuse-init-array -target-cpu x86-64 -dwarf-column-info -debugger-tuning=gdb -momit-leaf-frame-pointer -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-7/lib/clang/7.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-7~svn329677/build-llvm/lib/Target/PowerPC -I /build/llvm-toolchain-snapshot-7~svn329677/lib/Target/PowerPC -I /build/llvm-toolchain-snapshot-7~svn329677/build-llvm/include -I /build/llvm-toolchain-snapshot-7~svn329677/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/7.3.0/../../../../include/c++/7.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/7.3.0/../../../../include/x86_64-linux-gnu/c++/7.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/7.3.0/../../../../include/x86_64-linux-gnu/c++/7.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/7.3.0/../../../../include/c++/7.3.0/backward -internal-isystem /usr/include/clang/7.0.0/include/ -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-7/lib/clang/7.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++11 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-7~svn329677/build-llvm/lib/Target/PowerPC -ferror-limit 19 -fmessage-length 0 -fvisibility-inlines-hidden -fobjc-runtime=gcc -fdiagnostics-show-option -vectorize-loops -vectorize-slp -analyzer-checker optin.performance.Padding -analyzer-output=html -analyzer-config stable-report-filename=true -o /tmp/scan-build-2018-04-11-031539-24776-1 -x c++ /build/llvm-toolchain-snapshot-7~svn329677/lib/Target/PowerPC/PPCISelLowering.cpp
1//===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the PPCISelLowering class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "PPCISelLowering.h"
15#include "MCTargetDesc/PPCPredicates.h"
16#include "PPC.h"
17#include "PPCCCState.h"
18#include "PPCCallingConv.h"
19#include "PPCFrameLowering.h"
20#include "PPCInstrInfo.h"
21#include "PPCMachineFunctionInfo.h"
22#include "PPCPerfectShuffle.h"
23#include "PPCRegisterInfo.h"
24#include "PPCSubtarget.h"
25#include "PPCTargetMachine.h"
26#include "llvm/ADT/APFloat.h"
27#include "llvm/ADT/APInt.h"
28#include "llvm/ADT/ArrayRef.h"
29#include "llvm/ADT/DenseMap.h"
30#include "llvm/ADT/None.h"
31#include "llvm/ADT/STLExtras.h"
32#include "llvm/ADT/SmallPtrSet.h"
33#include "llvm/ADT/SmallSet.h"
34#include "llvm/ADT/SmallVector.h"
35#include "llvm/ADT/Statistic.h"
36#include "llvm/ADT/StringRef.h"
37#include "llvm/ADT/StringSwitch.h"
38#include "llvm/CodeGen/CallingConvLower.h"
39#include "llvm/CodeGen/ISDOpcodes.h"
40#include "llvm/CodeGen/MachineBasicBlock.h"
41#include "llvm/CodeGen/MachineFrameInfo.h"
42#include "llvm/CodeGen/MachineFunction.h"
43#include "llvm/CodeGen/MachineInstr.h"
44#include "llvm/CodeGen/MachineInstrBuilder.h"
45#include "llvm/CodeGen/MachineJumpTableInfo.h"
46#include "llvm/CodeGen/MachineLoopInfo.h"
47#include "llvm/CodeGen/MachineMemOperand.h"
48#include "llvm/CodeGen/MachineOperand.h"
49#include "llvm/CodeGen/MachineRegisterInfo.h"
50#include "llvm/CodeGen/RuntimeLibcalls.h"
51#include "llvm/CodeGen/SelectionDAG.h"
52#include "llvm/CodeGen/SelectionDAGNodes.h"
53#include "llvm/CodeGen/TargetInstrInfo.h"
54#include "llvm/CodeGen/TargetLowering.h"
55#include "llvm/CodeGen/TargetRegisterInfo.h"
56#include "llvm/CodeGen/ValueTypes.h"
57#include "llvm/IR/CallSite.h"
58#include "llvm/IR/CallingConv.h"
59#include "llvm/IR/Constant.h"
60#include "llvm/IR/Constants.h"
61#include "llvm/IR/DataLayout.h"
62#include "llvm/IR/DebugLoc.h"
63#include "llvm/IR/DerivedTypes.h"
64#include "llvm/IR/Function.h"
65#include "llvm/IR/GlobalValue.h"
66#include "llvm/IR/IRBuilder.h"
67#include "llvm/IR/Instructions.h"
68#include "llvm/IR/Intrinsics.h"
69#include "llvm/IR/Module.h"
70#include "llvm/IR/Type.h"
71#include "llvm/IR/Use.h"
72#include "llvm/IR/Value.h"
73#include "llvm/MC/MCExpr.h"
74#include "llvm/MC/MCRegisterInfo.h"
75#include "llvm/Support/AtomicOrdering.h"
76#include "llvm/Support/BranchProbability.h"
77#include "llvm/Support/Casting.h"
78#include "llvm/Support/CodeGen.h"
79#include "llvm/Support/CommandLine.h"
80#include "llvm/Support/Compiler.h"
81#include "llvm/Support/Debug.h"
82#include "llvm/Support/ErrorHandling.h"
83#include "llvm/Support/Format.h"
84#include "llvm/Support/KnownBits.h"
85#include "llvm/Support/MachineValueType.h"
86#include "llvm/Support/MathExtras.h"
87#include "llvm/Support/raw_ostream.h"
88#include "llvm/Target/TargetMachine.h"
89#include "llvm/Target/TargetOptions.h"
90#include <algorithm>
91#include <cassert>
92#include <cstdint>
93#include <iterator>
94#include <list>
95#include <utility>
96#include <vector>
97
98using namespace llvm;
99
100#define DEBUG_TYPE"ppc-lowering" "ppc-lowering"
101
102static cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc",
103cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden);
104
105static cl::opt<bool> DisableILPPref("disable-ppc-ilp-pref",
106cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden);
107
108static cl::opt<bool> DisablePPCUnaligned("disable-ppc-unaligned",
109cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden);
110
111static cl::opt<bool> DisableSCO("disable-ppc-sco",
112cl::desc("disable sibling call optimization on ppc"), cl::Hidden);
113
114static cl::opt<bool> EnableQuadPrecision("enable-ppc-quad-precision",
115cl::desc("enable quad precision float support on ppc"), cl::Hidden);
116
117STATISTIC(NumTailCalls, "Number of tail calls")static llvm::Statistic NumTailCalls = {"ppc-lowering", "NumTailCalls"
, "Number of tail calls", {0}, {false}}
;
118STATISTIC(NumSiblingCalls, "Number of sibling calls")static llvm::Statistic NumSiblingCalls = {"ppc-lowering", "NumSiblingCalls"
, "Number of sibling calls", {0}, {false}}
;
119
120static bool isNByteElemShuffleMask(ShuffleVectorSDNode *, unsigned, int);
121
122// FIXME: Remove this once the bug has been fixed!
123extern cl::opt<bool> ANDIGlueBug;
124
125PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
126 const PPCSubtarget &STI)
127 : TargetLowering(TM), Subtarget(STI) {
128 // Use _setjmp/_longjmp instead of setjmp/longjmp.
129 setUseUnderscoreSetJmp(true);
130 setUseUnderscoreLongJmp(true);
131
132 // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all
133 // arguments are at least 4/8 bytes aligned.
134 bool isPPC64 = Subtarget.isPPC64();
135 setMinStackArgumentAlignment(isPPC64 ? 8:4);
136
137 // Set up the register classes.
138 addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
139 if (!useSoftFloat()) {
140 addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
141 addRegisterClass(MVT::f64, &PPC::F8RCRegClass);
142 }
143
144 // Match BITREVERSE to customized fast code sequence in the td file.
145 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
146 setOperationAction(ISD::BITREVERSE, MVT::i64, Legal);
147
148 // Sub-word ATOMIC_CMP_SWAP need to ensure that the input is zero-extended.
149 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom);
150
151 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD.
152 for (MVT VT : MVT::integer_valuetypes()) {
153 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
154 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand);
155 }
156
157 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
158
159 // PowerPC has pre-inc load and store's.
160 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
161 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
162 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
163 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
164 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
165 setIndexedLoadAction(ISD::PRE_INC, MVT::f32, Legal);
166 setIndexedLoadAction(ISD::PRE_INC, MVT::f64, Legal);
167 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
168 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
169 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
170 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
171 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
172 setIndexedStoreAction(ISD::PRE_INC, MVT::f32, Legal);
173 setIndexedStoreAction(ISD::PRE_INC, MVT::f64, Legal);
174
175 if (Subtarget.useCRBits()) {
176 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
177
178 if (isPPC64 || Subtarget.hasFPCVT()) {
179 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote);
180 AddPromotedToType (ISD::SINT_TO_FP, MVT::i1,
181 isPPC64 ? MVT::i64 : MVT::i32);
182 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote);
183 AddPromotedToType(ISD::UINT_TO_FP, MVT::i1,
184 isPPC64 ? MVT::i64 : MVT::i32);
185 } else {
186 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Custom);
187 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Custom);
188 }
189
190 // PowerPC does not support direct load/store of condition registers.
191 setOperationAction(ISD::LOAD, MVT::i1, Custom);
192 setOperationAction(ISD::STORE, MVT::i1, Custom);
193
194 // FIXME: Remove this once the ANDI glue bug is fixed:
195 if (ANDIGlueBug)
196 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
197
198 for (MVT VT : MVT::integer_valuetypes()) {
199 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
200 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
201 setTruncStoreAction(VT, MVT::i1, Expand);
202 }
203
204 addRegisterClass(MVT::i1, &PPC::CRBITRCRegClass);
205 }
206
207 // Expand ppcf128 to i32 by hand for the benefit of llvm-gcc bootstrap on
208 // PPC (the libcall is not available).
209 setOperationAction(ISD::FP_TO_SINT, MVT::ppcf128, Custom);
210 setOperationAction(ISD::FP_TO_UINT, MVT::ppcf128, Custom);
211
212 // We do not currently implement these libm ops for PowerPC.
213 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand);
214 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand);
215 setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand);
216 setOperationAction(ISD::FRINT, MVT::ppcf128, Expand);
217 setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand);
218 setOperationAction(ISD::FREM, MVT::ppcf128, Expand);
219
220 // PowerPC has no SREM/UREM instructions unless we are on P9
221 // On P9 we may use a hardware instruction to compute the remainder.
222 // The instructions are not legalized directly because in the cases where the
223 // result of both the remainder and the division is required it is more
224 // efficient to compute the remainder from the result of the division rather
225 // than use the remainder instruction.
226 if (Subtarget.isISA3_0()) {
227 setOperationAction(ISD::SREM, MVT::i32, Custom);
228 setOperationAction(ISD::UREM, MVT::i32, Custom);
229 setOperationAction(ISD::SREM, MVT::i64, Custom);
230 setOperationAction(ISD::UREM, MVT::i64, Custom);
231 } else {
232 setOperationAction(ISD::SREM, MVT::i32, Expand);
233 setOperationAction(ISD::UREM, MVT::i32, Expand);
234 setOperationAction(ISD::SREM, MVT::i64, Expand);
235 setOperationAction(ISD::UREM, MVT::i64, Expand);
236 }
237
238 if (Subtarget.hasP9Vector()) {
239 setOperationAction(ISD::ABS, MVT::v4i32, Legal);
240 setOperationAction(ISD::ABS, MVT::v8i16, Legal);
241 setOperationAction(ISD::ABS, MVT::v16i8, Legal);
242 }
243
244 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
245 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
246 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
247 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
248 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
249 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
250 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
251 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
252 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
253
254 // We don't support sin/cos/sqrt/fmod/pow
255 setOperationAction(ISD::FSIN , MVT::f64, Expand);
256 setOperationAction(ISD::FCOS , MVT::f64, Expand);
257 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
258 setOperationAction(ISD::FREM , MVT::f64, Expand);
259 setOperationAction(ISD::FPOW , MVT::f64, Expand);
260 setOperationAction(ISD::FMA , MVT::f64, Legal);
261 setOperationAction(ISD::FSIN , MVT::f32, Expand);
262 setOperationAction(ISD::FCOS , MVT::f32, Expand);
263 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
264 setOperationAction(ISD::FREM , MVT::f32, Expand);
265 setOperationAction(ISD::FPOW , MVT::f32, Expand);
266 setOperationAction(ISD::FMA , MVT::f32, Legal);
267
268 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
269
270 // If we're enabling GP optimizations, use hardware square root
271 if (!Subtarget.hasFSQRT() &&
272 !(TM.Options.UnsafeFPMath && Subtarget.hasFRSQRTE() &&
273 Subtarget.hasFRE()))
274 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
275
276 if (!Subtarget.hasFSQRT() &&
277 !(TM.Options.UnsafeFPMath && Subtarget.hasFRSQRTES() &&
278 Subtarget.hasFRES()))
279 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
280
281 if (Subtarget.hasFCPSGN()) {
282 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Legal);
283 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Legal);
284 } else {
285 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
286 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
287 }
288
289 if (Subtarget.hasFPRND()) {
290 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
291 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
292 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
293 setOperationAction(ISD::FROUND, MVT::f64, Legal);
294
295 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
296 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
297 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
298 setOperationAction(ISD::FROUND, MVT::f32, Legal);
299 }
300
301 // PowerPC does not have BSWAP, but we can use vector BSWAP instruction xxbrd
302 // to speed up scalar BSWAP64.
303 // CTPOP or CTTZ were introduced in P8/P9 respectivelly
304 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
305 if (Subtarget.isISA3_0()) {
306 setOperationAction(ISD::BSWAP, MVT::i64 , Custom);
307 setOperationAction(ISD::CTTZ , MVT::i32 , Legal);
308 setOperationAction(ISD::CTTZ , MVT::i64 , Legal);
309 } else {
310 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
311 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
312 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
313 }
314
315 if (Subtarget.hasPOPCNTD() == PPCSubtarget::POPCNTD_Fast) {
316 setOperationAction(ISD::CTPOP, MVT::i32 , Legal);
317 setOperationAction(ISD::CTPOP, MVT::i64 , Legal);
318 } else {
319 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
320 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
321 }
322
323 // PowerPC does not have ROTR
324 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
325 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
326
327 if (!Subtarget.useCRBits()) {
328 // PowerPC does not have Select
329 setOperationAction(ISD::SELECT, MVT::i32, Expand);
330 setOperationAction(ISD::SELECT, MVT::i64, Expand);
331 setOperationAction(ISD::SELECT, MVT::f32, Expand);
332 setOperationAction(ISD::SELECT, MVT::f64, Expand);
333 }
334
335 // PowerPC wants to turn select_cc of FP into fsel when possible.
336 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
337 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
338
339 // PowerPC wants to optimize integer setcc a bit
340 if (!Subtarget.useCRBits())
341 setOperationAction(ISD::SETCC, MVT::i32, Custom);
342
343 // PowerPC does not have BRCOND which requires SetCC
344 if (!Subtarget.useCRBits())
345 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
346
347 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
348
349 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
350 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
351
352 // PowerPC does not have [U|S]INT_TO_FP
353 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
354 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
355
356 if (Subtarget.hasDirectMove() && isPPC64) {
357 setOperationAction(ISD::BITCAST, MVT::f32, Legal);
358 setOperationAction(ISD::BITCAST, MVT::i32, Legal);
359 setOperationAction(ISD::BITCAST, MVT::i64, Legal);
360 setOperationAction(ISD::BITCAST, MVT::f64, Legal);
361 } else {
362 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
363 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
364 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
365 setOperationAction(ISD::BITCAST, MVT::f64, Expand);
366 }
367
368 // We cannot sextinreg(i1). Expand to shifts.
369 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
370
371 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
372 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
373 // support continuation, user-level threading, and etc.. As a result, no
374 // other SjLj exception interfaces are implemented and please don't build
375 // your own exception handling based on them.
376 // LLVM/Clang supports zero-cost DWARF exception handling.
377 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
378 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
379
380 // We want to legalize GlobalAddress and ConstantPool nodes into the
381 // appropriate instructions to materialize the address.
382 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
383 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
384 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
385 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
386 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
387 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
388 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
389 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
390 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
391 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
392
393 // TRAP is legal.
394 setOperationAction(ISD::TRAP, MVT::Other, Legal);
395
396 // TRAMPOLINE is custom lowered.
397 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
398 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
399
400 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
401 setOperationAction(ISD::VASTART , MVT::Other, Custom);
402
403 if (Subtarget.isSVR4ABI()) {
404 if (isPPC64) {
405 // VAARG always uses double-word chunks, so promote anything smaller.
406 setOperationAction(ISD::VAARG, MVT::i1, Promote);
407 AddPromotedToType (ISD::VAARG, MVT::i1, MVT::i64);
408 setOperationAction(ISD::VAARG, MVT::i8, Promote);
409 AddPromotedToType (ISD::VAARG, MVT::i8, MVT::i64);
410 setOperationAction(ISD::VAARG, MVT::i16, Promote);
411 AddPromotedToType (ISD::VAARG, MVT::i16, MVT::i64);
412 setOperationAction(ISD::VAARG, MVT::i32, Promote);
413 AddPromotedToType (ISD::VAARG, MVT::i32, MVT::i64);
414 setOperationAction(ISD::VAARG, MVT::Other, Expand);
415 } else {
416 // VAARG is custom lowered with the 32-bit SVR4 ABI.
417 setOperationAction(ISD::VAARG, MVT::Other, Custom);
418 setOperationAction(ISD::VAARG, MVT::i64, Custom);
419 }
420 } else
421 setOperationAction(ISD::VAARG, MVT::Other, Expand);
422
423 if (Subtarget.isSVR4ABI() && !isPPC64)
424 // VACOPY is custom lowered with the 32-bit SVR4 ABI.
425 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
426 else
427 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
428
429 // Use the default implementation.
430 setOperationAction(ISD::VAEND , MVT::Other, Expand);
431 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
432 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
433 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
434 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
435 setOperationAction(ISD::GET_DYNAMIC_AREA_OFFSET, MVT::i32, Custom);
436 setOperationAction(ISD::GET_DYNAMIC_AREA_OFFSET, MVT::i64, Custom);
437 setOperationAction(ISD::EH_DWARF_CFA, MVT::i32, Custom);
438 setOperationAction(ISD::EH_DWARF_CFA, MVT::i64, Custom);
439
440 // We want to custom lower some of our intrinsics.
441 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
442
443 // To handle counter-based loop conditions.
444 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i1, Custom);
445
446 setOperationAction(ISD::INTRINSIC_VOID, MVT::i8, Custom);
447 setOperationAction(ISD::INTRINSIC_VOID, MVT::i16, Custom);
448 setOperationAction(ISD::INTRINSIC_VOID, MVT::i32, Custom);
449 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
450
451 // Comparisons that require checking two conditions.
452 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
453 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
454 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
455 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
456 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
457 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
458 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
459 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
460 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
461 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
462 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
463 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
464
465 if (Subtarget.has64BitSupport()) {
466 // They also have instructions for converting between i64 and fp.
467 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
468 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
469 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
470 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
471 // This is just the low 32 bits of a (signed) fp->i64 conversion.
472 // We cannot do this with Promote because i64 is not a legal type.
473 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
474
475 if (Subtarget.hasLFIWAX() || Subtarget.isPPC64())
476 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
477 } else {
478 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
479 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
480 }
481
482 // With the instructions enabled under FPCVT, we can do everything.
483 if (Subtarget.hasFPCVT()) {
484 if (Subtarget.has64BitSupport()) {
485 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
486 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
487 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
488 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
489 }
490
491 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
492 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
493 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
494 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
495 }
496
497 if (Subtarget.use64BitRegs()) {
498 // 64-bit PowerPC implementations can support i64 types directly
499 addRegisterClass(MVT::i64, &PPC::G8RCRegClass);
500 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
501 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
502 // 64-bit PowerPC wants to expand i128 shifts itself.
503 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
504 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
505 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
506 } else {
507 // 32-bit PowerPC wants to expand i64 shifts itself.
508 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
509 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
510 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
511 }
512
513 if (Subtarget.hasAltivec()) {
514 // First set operation action for all vector types to expand. Then we
515 // will selectively turn on ones that can be effectively codegen'd.
516 for (MVT VT : MVT::vector_valuetypes()) {
517 // add/sub are legal for all supported vector VT's.
518 setOperationAction(ISD::ADD, VT, Legal);
519 setOperationAction(ISD::SUB, VT, Legal);
520
521 // Vector instructions introduced in P8
522 if (Subtarget.hasP8Altivec() && (VT.SimpleTy != MVT::v1i128)) {
523 setOperationAction(ISD::CTPOP, VT, Legal);
524 setOperationAction(ISD::CTLZ, VT, Legal);
525 }
526 else {
527 setOperationAction(ISD::CTPOP, VT, Expand);
528 setOperationAction(ISD::CTLZ, VT, Expand);
529 }
530
531 // Vector instructions introduced in P9
532 if (Subtarget.hasP9Altivec() && (VT.SimpleTy != MVT::v1i128))
533 setOperationAction(ISD::CTTZ, VT, Legal);
534 else
535 setOperationAction(ISD::CTTZ, VT, Expand);
536
537 // We promote all shuffles to v16i8.
538 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
539 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
540
541 // We promote all non-typed operations to v4i32.
542 setOperationAction(ISD::AND , VT, Promote);
543 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
544 setOperationAction(ISD::OR , VT, Promote);
545 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
546 setOperationAction(ISD::XOR , VT, Promote);
547 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
548 setOperationAction(ISD::LOAD , VT, Promote);
549 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
550 setOperationAction(ISD::SELECT, VT, Promote);
551 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
552 setOperationAction(ISD::SELECT_CC, VT, Promote);
553 AddPromotedToType (ISD::SELECT_CC, VT, MVT::v4i32);
554 setOperationAction(ISD::STORE, VT, Promote);
555 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
556
557 // No other operations are legal.
558 setOperationAction(ISD::MUL , VT, Expand);
559 setOperationAction(ISD::SDIV, VT, Expand);
560 setOperationAction(ISD::SREM, VT, Expand);
561 setOperationAction(ISD::UDIV, VT, Expand);
562 setOperationAction(ISD::UREM, VT, Expand);
563 setOperationAction(ISD::FDIV, VT, Expand);
564 setOperationAction(ISD::FREM, VT, Expand);
565 setOperationAction(ISD::FNEG, VT, Expand);
566 setOperationAction(ISD::FSQRT, VT, Expand);
567 setOperationAction(ISD::FLOG, VT, Expand);
568 setOperationAction(ISD::FLOG10, VT, Expand);
569 setOperationAction(ISD::FLOG2, VT, Expand);
570 setOperationAction(ISD::FEXP, VT, Expand);
571 setOperationAction(ISD::FEXP2, VT, Expand);
572 setOperationAction(ISD::FSIN, VT, Expand);
573 setOperationAction(ISD::FCOS, VT, Expand);
574 setOperationAction(ISD::FABS, VT, Expand);
575 setOperationAction(ISD::FFLOOR, VT, Expand);
576 setOperationAction(ISD::FCEIL, VT, Expand);
577 setOperationAction(ISD::FTRUNC, VT, Expand);
578 setOperationAction(ISD::FRINT, VT, Expand);
579 setOperationAction(ISD::FNEARBYINT, VT, Expand);
580 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
581 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
582 setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
583 setOperationAction(ISD::MULHU, VT, Expand);
584 setOperationAction(ISD::MULHS, VT, Expand);
585 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
586 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
587 setOperationAction(ISD::UDIVREM, VT, Expand);
588 setOperationAction(ISD::SDIVREM, VT, Expand);
589 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
590 setOperationAction(ISD::FPOW, VT, Expand);
591 setOperationAction(ISD::BSWAP, VT, Expand);
592 setOperationAction(ISD::VSELECT, VT, Expand);
593 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
594 setOperationAction(ISD::ROTL, VT, Expand);
595 setOperationAction(ISD::ROTR, VT, Expand);
596
597 for (MVT InnerVT : MVT::vector_valuetypes()) {
598 setTruncStoreAction(VT, InnerVT, Expand);
599 setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand);
600 setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand);
601 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand);
602 }
603 }
604
605 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
606 // with merges, splats, etc.
607 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
608
609 setOperationAction(ISD::AND , MVT::v4i32, Legal);
610 setOperationAction(ISD::OR , MVT::v4i32, Legal);
611 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
612 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
613 setOperationAction(ISD::SELECT, MVT::v4i32,
614 Subtarget.useCRBits() ? Legal : Expand);
615 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
616 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
617 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
618 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
619 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
620 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
621 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
622 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
623 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
624
625 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
626 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass);
627 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass);
628 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass);
629
630 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
631 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
632
633 if (TM.Options.UnsafeFPMath || Subtarget.hasVSX()) {
634 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
635 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
636 }
637
638 if (Subtarget.hasP8Altivec())
639 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
640 else
641 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
642
643 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
644 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
645
646 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
647 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
648
649 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
650 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
651 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
652 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
653
654 // Altivec does not contain unordered floating-point compare instructions
655 setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand);
656 setCondCodeAction(ISD::SETUEQ, MVT::v4f32, Expand);
657 setCondCodeAction(ISD::SETO, MVT::v4f32, Expand);
658 setCondCodeAction(ISD::SETONE, MVT::v4f32, Expand);
659
660 if (Subtarget.hasVSX()) {
661 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal);
662 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal);
663 if (Subtarget.hasP8Vector()) {
664 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Legal);
665 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Legal);
666 }
667 if (Subtarget.hasDirectMove() && isPPC64) {
668 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Legal);
669 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Legal);
670 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Legal);
671 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i64, Legal);
672 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Legal);
673 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Legal);
674 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Legal);
675 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal);
676 }
677 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal);
678
679 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
680 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
681 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
682 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
683 setOperationAction(ISD::FROUND, MVT::v2f64, Legal);
684
685 setOperationAction(ISD::FROUND, MVT::v4f32, Legal);
686
687 setOperationAction(ISD::MUL, MVT::v2f64, Legal);
688 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
689
690 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
691 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
692
693 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
694 setOperationAction(ISD::VSELECT, MVT::v8i16, Legal);
695 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
696 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
697 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
698
699 // Share the Altivec comparison restrictions.
700 setCondCodeAction(ISD::SETUO, MVT::v2f64, Expand);
701 setCondCodeAction(ISD::SETUEQ, MVT::v2f64, Expand);
702 setCondCodeAction(ISD::SETO, MVT::v2f64, Expand);
703 setCondCodeAction(ISD::SETONE, MVT::v2f64, Expand);
704
705 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
706 setOperationAction(ISD::STORE, MVT::v2f64, Legal);
707
708 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Legal);
709
710 if (Subtarget.hasP8Vector())
711 addRegisterClass(MVT::f32, &PPC::VSSRCRegClass);
712
713 addRegisterClass(MVT::f64, &PPC::VSFRCRegClass);
714
715 addRegisterClass(MVT::v4i32, &PPC::VSRCRegClass);
716 addRegisterClass(MVT::v4f32, &PPC::VSRCRegClass);
717 addRegisterClass(MVT::v2f64, &PPC::VSRCRegClass);
718
719 if (Subtarget.hasP8Altivec()) {
720 setOperationAction(ISD::SHL, MVT::v2i64, Legal);
721 setOperationAction(ISD::SRA, MVT::v2i64, Legal);
722 setOperationAction(ISD::SRL, MVT::v2i64, Legal);
723
724 // 128 bit shifts can be accomplished via 3 instructions for SHL and
725 // SRL, but not for SRA because of the instructions available:
726 // VS{RL} and VS{RL}O. However due to direct move costs, it's not worth
727 // doing
728 setOperationAction(ISD::SHL, MVT::v1i128, Expand);
729 setOperationAction(ISD::SRL, MVT::v1i128, Expand);
730 setOperationAction(ISD::SRA, MVT::v1i128, Expand);
731
732 setOperationAction(ISD::SETCC, MVT::v2i64, Legal);
733 }
734 else {
735 setOperationAction(ISD::SHL, MVT::v2i64, Expand);
736 setOperationAction(ISD::SRA, MVT::v2i64, Expand);
737 setOperationAction(ISD::SRL, MVT::v2i64, Expand);
738
739 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
740
741 // VSX v2i64 only supports non-arithmetic operations.
742 setOperationAction(ISD::ADD, MVT::v2i64, Expand);
743 setOperationAction(ISD::SUB, MVT::v2i64, Expand);
744 }
745
746 setOperationAction(ISD::LOAD, MVT::v2i64, Promote);
747 AddPromotedToType (ISD::LOAD, MVT::v2i64, MVT::v2f64);
748 setOperationAction(ISD::STORE, MVT::v2i64, Promote);
749 AddPromotedToType (ISD::STORE, MVT::v2i64, MVT::v2f64);
750
751 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Legal);
752
753 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
754 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
755 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
756 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
757
758 // Vector operation legalization checks the result type of
759 // SIGN_EXTEND_INREG, overall legalization checks the inner type.
760 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i64, Legal);
761 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Legal);
762 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom);
763 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom);
764
765 setOperationAction(ISD::FNEG, MVT::v4f32, Legal);
766 setOperationAction(ISD::FNEG, MVT::v2f64, Legal);
767 setOperationAction(ISD::FABS, MVT::v4f32, Legal);
768 setOperationAction(ISD::FABS, MVT::v2f64, Legal);
769
770 if (Subtarget.hasDirectMove())
771 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
772 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
773
774 addRegisterClass(MVT::v2i64, &PPC::VSRCRegClass);
775 }
776
777 if (Subtarget.hasP8Altivec()) {
778 addRegisterClass(MVT::v2i64, &PPC::VRRCRegClass);
779 addRegisterClass(MVT::v1i128, &PPC::VRRCRegClass);
780 }
781
782 if (Subtarget.hasP9Vector()) {
783 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
784 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
785
786 // 128 bit shifts can be accomplished via 3 instructions for SHL and
787 // SRL, but not for SRA because of the instructions available:
788 // VS{RL} and VS{RL}O.
789 setOperationAction(ISD::SHL, MVT::v1i128, Legal);
790 setOperationAction(ISD::SRL, MVT::v1i128, Legal);
791 setOperationAction(ISD::SRA, MVT::v1i128, Expand);
792
793 if (EnableQuadPrecision) {
794 addRegisterClass(MVT::f128, &PPC::VRRCRegClass);
795 setOperationAction(ISD::FADD, MVT::f128, Legal);
796 setOperationAction(ISD::FSUB, MVT::f128, Legal);
797 setOperationAction(ISD::FDIV, MVT::f128, Legal);
798 setOperationAction(ISD::FMUL, MVT::f128, Legal);
799 setOperationAction(ISD::FP_EXTEND, MVT::f128, Legal);
800 setLoadExtAction(ISD::EXTLOAD, MVT::f128, MVT::f64, Expand);
801 setOperationAction(ISD::FMA, MVT::f128, Legal);
802 }
803
804 }
805
806 if (Subtarget.hasP9Altivec()) {
807 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
808 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
809 }
810 }
811
812 if (Subtarget.hasQPX()) {
813 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
814 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
815 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
816 setOperationAction(ISD::FREM, MVT::v4f64, Expand);
817
818 setOperationAction(ISD::FCOPYSIGN, MVT::v4f64, Legal);
819 setOperationAction(ISD::FGETSIGN, MVT::v4f64, Expand);
820
821 setOperationAction(ISD::LOAD , MVT::v4f64, Custom);
822 setOperationAction(ISD::STORE , MVT::v4f64, Custom);
823
824 setTruncStoreAction(MVT::v4f64, MVT::v4f32, Custom);
825 setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f32, Custom);
826
827 if (!Subtarget.useCRBits())
828 setOperationAction(ISD::SELECT, MVT::v4f64, Expand);
829 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal);
830
831 setOperationAction(ISD::EXTRACT_VECTOR_ELT , MVT::v4f64, Legal);
832 setOperationAction(ISD::INSERT_VECTOR_ELT , MVT::v4f64, Expand);
833 setOperationAction(ISD::CONCAT_VECTORS , MVT::v4f64, Expand);
834 setOperationAction(ISD::EXTRACT_SUBVECTOR , MVT::v4f64, Expand);
835 setOperationAction(ISD::VECTOR_SHUFFLE , MVT::v4f64, Custom);
836 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f64, Legal);
837 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f64, Custom);
838
839 setOperationAction(ISD::FP_TO_SINT , MVT::v4f64, Legal);
840 setOperationAction(ISD::FP_TO_UINT , MVT::v4f64, Expand);
841
842 setOperationAction(ISD::FP_ROUND , MVT::v4f32, Legal);
843 setOperationAction(ISD::FP_ROUND_INREG , MVT::v4f32, Expand);
844 setOperationAction(ISD::FP_EXTEND, MVT::v4f64, Legal);
845
846 setOperationAction(ISD::FNEG , MVT::v4f64, Legal);
847 setOperationAction(ISD::FABS , MVT::v4f64, Legal);
848 setOperationAction(ISD::FSIN , MVT::v4f64, Expand);
849 setOperationAction(ISD::FCOS , MVT::v4f64, Expand);
850 setOperationAction(ISD::FPOW , MVT::v4f64, Expand);
851 setOperationAction(ISD::FLOG , MVT::v4f64, Expand);
852 setOperationAction(ISD::FLOG2 , MVT::v4f64, Expand);
853 setOperationAction(ISD::FLOG10 , MVT::v4f64, Expand);
854 setOperationAction(ISD::FEXP , MVT::v4f64, Expand);
855 setOperationAction(ISD::FEXP2 , MVT::v4f64, Expand);
856
857 setOperationAction(ISD::FMINNUM, MVT::v4f64, Legal);
858 setOperationAction(ISD::FMAXNUM, MVT::v4f64, Legal);
859
860 setIndexedLoadAction(ISD::PRE_INC, MVT::v4f64, Legal);
861 setIndexedStoreAction(ISD::PRE_INC, MVT::v4f64, Legal);
862
863 addRegisterClass(MVT::v4f64, &PPC::QFRCRegClass);
864
865 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
866 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
867 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
868 setOperationAction(ISD::FREM, MVT::v4f32, Expand);
869
870 setOperationAction(ISD::FCOPYSIGN, MVT::v4f32, Legal);
871 setOperationAction(ISD::FGETSIGN, MVT::v4f32, Expand);
872
873 setOperationAction(ISD::LOAD , MVT::v4f32, Custom);
874 setOperationAction(ISD::STORE , MVT::v4f32, Custom);
875
876 if (!Subtarget.useCRBits())
877 setOperationAction(ISD::SELECT, MVT::v4f32, Expand);
878 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
879
880 setOperationAction(ISD::EXTRACT_VECTOR_ELT , MVT::v4f32, Legal);
881 setOperationAction(ISD::INSERT_VECTOR_ELT , MVT::v4f32, Expand);
882 setOperationAction(ISD::CONCAT_VECTORS , MVT::v4f32, Expand);
883 setOperationAction(ISD::EXTRACT_SUBVECTOR , MVT::v4f32, Expand);
884 setOperationAction(ISD::VECTOR_SHUFFLE , MVT::v4f32, Custom);
885 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Legal);
886 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
887
888 setOperationAction(ISD::FP_TO_SINT , MVT::v4f32, Legal);
889 setOperationAction(ISD::FP_TO_UINT , MVT::v4f32, Expand);
890
891 setOperationAction(ISD::FNEG , MVT::v4f32, Legal);
892 setOperationAction(ISD::FABS , MVT::v4f32, Legal);
893 setOperationAction(ISD::FSIN , MVT::v4f32, Expand);
894 setOperationAction(ISD::FCOS , MVT::v4f32, Expand);
895 setOperationAction(ISD::FPOW , MVT::v4f32, Expand);
896 setOperationAction(ISD::FLOG , MVT::v4f32, Expand);
897 setOperationAction(ISD::FLOG2 , MVT::v4f32, Expand);
898 setOperationAction(ISD::FLOG10 , MVT::v4f32, Expand);
899 setOperationAction(ISD::FEXP , MVT::v4f32, Expand);
900 setOperationAction(ISD::FEXP2 , MVT::v4f32, Expand);
901
902 setOperationAction(ISD::FMINNUM, MVT::v4f32, Legal);
903 setOperationAction(ISD::FMAXNUM, MVT::v4f32, Legal);
904
905 setIndexedLoadAction(ISD::PRE_INC, MVT::v4f32, Legal);
906 setIndexedStoreAction(ISD::PRE_INC, MVT::v4f32, Legal);
907
908 addRegisterClass(MVT::v4f32, &PPC::QSRCRegClass);
909
910 setOperationAction(ISD::AND , MVT::v4i1, Legal);
911 setOperationAction(ISD::OR , MVT::v4i1, Legal);
912 setOperationAction(ISD::XOR , MVT::v4i1, Legal);
913
914 if (!Subtarget.useCRBits())
915 setOperationAction(ISD::SELECT, MVT::v4i1, Expand);
916 setOperationAction(ISD::VSELECT, MVT::v4i1, Legal);
917
918 setOperationAction(ISD::LOAD , MVT::v4i1, Custom);
919 setOperationAction(ISD::STORE , MVT::v4i1, Custom);
920
921 setOperationAction(ISD::EXTRACT_VECTOR_ELT , MVT::v4i1, Custom);
922 setOperationAction(ISD::INSERT_VECTOR_ELT , MVT::v4i1, Expand);
923 setOperationAction(ISD::CONCAT_VECTORS , MVT::v4i1, Expand);
924 setOperationAction(ISD::EXTRACT_SUBVECTOR , MVT::v4i1, Expand);
925 setOperationAction(ISD::VECTOR_SHUFFLE , MVT::v4i1, Custom);
926 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i1, Expand);
927 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i1, Custom);
928
929 setOperationAction(ISD::SINT_TO_FP, MVT::v4i1, Custom);
930 setOperationAction(ISD::UINT_TO_FP, MVT::v4i1, Custom);
931
932 addRegisterClass(MVT::v4i1, &PPC::QBRCRegClass);
933
934 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
935 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
936 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
937 setOperationAction(ISD::FROUND, MVT::v4f64, Legal);
938
939 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
940 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
941 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
942 setOperationAction(ISD::FROUND, MVT::v4f32, Legal);
943
944 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Expand);
945 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Expand);
946
947 // These need to set FE_INEXACT, and so cannot be vectorized here.
948 setOperationAction(ISD::FRINT, MVT::v4f64, Expand);
949 setOperationAction(ISD::FRINT, MVT::v4f32, Expand);
950
951 if (TM.Options.UnsafeFPMath) {
952 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
953 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
954
955 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
956 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
957 } else {
958 setOperationAction(ISD::FDIV, MVT::v4f64, Expand);
959 setOperationAction(ISD::FSQRT, MVT::v4f64, Expand);
960
961 setOperationAction(ISD::FDIV, MVT::v4f32, Expand);
962 setOperationAction(ISD::FSQRT, MVT::v4f32, Expand);
963 }
964 }
965
966 if (Subtarget.has64BitSupport())
967 setOperationAction(ISD::PREFETCH, MVT::Other, Legal);
968
969 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, isPPC64 ? Legal : Custom);
970
971 if (!isPPC64) {
972 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
973 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
974 }
975
976 setBooleanContents(ZeroOrOneBooleanContent);
977
978 if (Subtarget.hasAltivec()) {
979 // Altivec instructions set fields to all zeros or all ones.
980 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
981 }
982
983 if (!isPPC64) {
984 // These libcalls are not available in 32-bit.
985 setLibcallName(RTLIB::SHL_I128, nullptr);
986 setLibcallName(RTLIB::SRL_I128, nullptr);
987 setLibcallName(RTLIB::SRA_I128, nullptr);
988 }
989
990 setStackPointerRegisterToSaveRestore(isPPC64 ? PPC::X1 : PPC::R1);
991
992 // We have target-specific dag combine patterns for the following nodes:
993 setTargetDAGCombine(ISD::SHL);
994 setTargetDAGCombine(ISD::SRA);
995 setTargetDAGCombine(ISD::SRL);
996 setTargetDAGCombine(ISD::SINT_TO_FP);
997 setTargetDAGCombine(ISD::BUILD_VECTOR);
998 if (Subtarget.hasFPCVT())
999 setTargetDAGCombine(ISD::UINT_TO_FP);
1000 setTargetDAGCombine(ISD::LOAD);
1001 setTargetDAGCombine(ISD::STORE);
1002 setTargetDAGCombine(ISD::BR_CC);
1003 if (Subtarget.useCRBits())
1004 setTargetDAGCombine(ISD::BRCOND);
1005 setTargetDAGCombine(ISD::BSWAP);
1006 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1007 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
1008 setTargetDAGCombine(ISD::INTRINSIC_VOID);
1009
1010 setTargetDAGCombine(ISD::SIGN_EXTEND);
1011 setTargetDAGCombine(ISD::ZERO_EXTEND);
1012 setTargetDAGCombine(ISD::ANY_EXTEND);
1013
1014 if (Subtarget.useCRBits()) {
1015 setTargetDAGCombine(ISD::TRUNCATE);
1016 setTargetDAGCombine(ISD::SETCC);
1017 setTargetDAGCombine(ISD::SELECT_CC);
1018 }
1019
1020 // Use reciprocal estimates.
1021 if (TM.Options.UnsafeFPMath) {
1022 setTargetDAGCombine(ISD::FDIV);
1023 setTargetDAGCombine(ISD::FSQRT);
1024 }
1025
1026 // Darwin long double math library functions have $LDBL128 appended.
1027 if (Subtarget.isDarwin()) {
1028 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
1029 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
1030 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
1031 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
1032 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
1033 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128");
1034 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128");
1035 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128");
1036 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128");
1037 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128");
1038 }
1039
1040 // With 32 condition bits, we don't need to sink (and duplicate) compares
1041 // aggressively in CodeGenPrep.
1042 if (Subtarget.useCRBits()) {
1043 setHasMultipleConditionRegisters();
1044 setJumpIsExpensive();
1045 }
1046
1047 setMinFunctionAlignment(2);
1048 if (Subtarget.isDarwin())
1049 setPrefFunctionAlignment(4);
1050
1051 switch (Subtarget.getDarwinDirective()) {
1052 default: break;
1053 case PPC::DIR_970:
1054 case PPC::DIR_A2:
1055 case PPC::DIR_E500mc:
1056 case PPC::DIR_E5500:
1057 case PPC::DIR_PWR4:
1058 case PPC::DIR_PWR5:
1059 case PPC::DIR_PWR5X:
1060 case PPC::DIR_PWR6:
1061 case PPC::DIR_PWR6X:
1062 case PPC::DIR_PWR7:
1063 case PPC::DIR_PWR8:
1064 case PPC::DIR_PWR9:
1065 setPrefFunctionAlignment(4);
1066 setPrefLoopAlignment(4);
1067 break;
1068 }
1069
1070 if (Subtarget.enableMachineScheduler())
1071 setSchedulingPreference(Sched::Source);
1072 else
1073 setSchedulingPreference(Sched::Hybrid);
1074
1075 computeRegisterProperties(STI.getRegisterInfo());
1076
1077 // The Freescale cores do better with aggressive inlining of memcpy and
1078 // friends. GCC uses same threshold of 128 bytes (= 32 word stores).
1079 if (Subtarget.getDarwinDirective() == PPC::DIR_E500mc ||
1080 Subtarget.getDarwinDirective() == PPC::DIR_E5500) {
1081 MaxStoresPerMemset = 32;
1082 MaxStoresPerMemsetOptSize = 16;
1083 MaxStoresPerMemcpy = 32;
1084 MaxStoresPerMemcpyOptSize = 8;
1085 MaxStoresPerMemmove = 32;
1086 MaxStoresPerMemmoveOptSize = 8;
1087 } else if (Subtarget.getDarwinDirective() == PPC::DIR_A2) {
1088 // The A2 also benefits from (very) aggressive inlining of memcpy and
1089 // friends. The overhead of a the function call, even when warm, can be
1090 // over one hundred cycles.
1091 MaxStoresPerMemset = 128;
1092 MaxStoresPerMemcpy = 128;
1093 MaxStoresPerMemmove = 128;
1094 MaxLoadsPerMemcmp = 128;
1095 } else {
1096 MaxLoadsPerMemcmp = 8;
1097 MaxLoadsPerMemcmpOptSize = 4;
1098 }
1099}
1100
1101/// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1102/// the desired ByVal argument alignment.
1103static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign,
1104 unsigned MaxMaxAlign) {
1105 if (MaxAlign == MaxMaxAlign)
1106 return;
1107 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1108 if (MaxMaxAlign >= 32 && VTy->getBitWidth() >= 256)
1109 MaxAlign = 32;
1110 else if (VTy->getBitWidth() >= 128 && MaxAlign < 16)
1111 MaxAlign = 16;
1112 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1113 unsigned EltAlign = 0;
1114 getMaxByValAlign(ATy->getElementType(), EltAlign, MaxMaxAlign);
1115 if (EltAlign > MaxAlign)
1116 MaxAlign = EltAlign;
1117 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1118 for (auto *EltTy : STy->elements()) {
1119 unsigned EltAlign = 0;
1120 getMaxByValAlign(EltTy, EltAlign, MaxMaxAlign);
1121 if (EltAlign > MaxAlign)
1122 MaxAlign = EltAlign;
1123 if (MaxAlign == MaxMaxAlign)
1124 break;
1125 }
1126 }
1127}
1128
1129/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1130/// function arguments in the caller parameter area.
1131unsigned PPCTargetLowering::getByValTypeAlignment(Type *Ty,
1132 const DataLayout &DL) const {
1133 // Darwin passes everything on 4 byte boundary.
1134 if (Subtarget.isDarwin())
1135 return 4;
1136
1137 // 16byte and wider vectors are passed on 16byte boundary.
1138 // The rest is 8 on PPC64 and 4 on PPC32 boundary.
1139 unsigned Align = Subtarget.isPPC64() ? 8 : 4;
1140 if (Subtarget.hasAltivec() || Subtarget.hasQPX())
1141 getMaxByValAlign(Ty, Align, Subtarget.hasQPX() ? 32 : 16);
1142 return Align;
1143}
1144
1145bool PPCTargetLowering::useSoftFloat() const {
1146 return Subtarget.useSoftFloat();
1147}
1148
1149const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
1150 switch ((PPCISD::NodeType)Opcode) {
1151 case PPCISD::FIRST_NUMBER: break;
1152 case PPCISD::FSEL: return "PPCISD::FSEL";
1153 case PPCISD::FCFID: return "PPCISD::FCFID";
1154 case PPCISD::FCFIDU: return "PPCISD::FCFIDU";
1155 case PPCISD::FCFIDS: return "PPCISD::FCFIDS";
1156 case PPCISD::FCFIDUS: return "PPCISD::FCFIDUS";
1157 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
1158 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
1159 case PPCISD::FCTIDUZ: return "PPCISD::FCTIDUZ";
1160 case PPCISD::FCTIWUZ: return "PPCISD::FCTIWUZ";
1161 case PPCISD::FRE: return "PPCISD::FRE";
1162 case PPCISD::FRSQRTE: return "PPCISD::FRSQRTE";
1163 case PPCISD::STFIWX: return "PPCISD::STFIWX";
1164 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
1165 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
1166 case PPCISD::VPERM: return "PPCISD::VPERM";
1167 case PPCISD::XXSPLT: return "PPCISD::XXSPLT";
1168 case PPCISD::VECINSERT: return "PPCISD::VECINSERT";
1169 case PPCISD::XXREVERSE: return "PPCISD::XXREVERSE";
1170 case PPCISD::XXPERMDI: return "PPCISD::XXPERMDI";
1171 case PPCISD::VECSHL: return "PPCISD::VECSHL";
1172 case PPCISD::CMPB: return "PPCISD::CMPB";
1173 case PPCISD::Hi: return "PPCISD::Hi";
1174 case PPCISD::Lo: return "PPCISD::Lo";
1175 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY";
1176 case PPCISD::ATOMIC_CMP_SWAP_8: return "PPCISD::ATOMIC_CMP_SWAP_8";
1177 case PPCISD::ATOMIC_CMP_SWAP_16: return "PPCISD::ATOMIC_CMP_SWAP_16";
1178 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
1179 case PPCISD::DYNAREAOFFSET: return "PPCISD::DYNAREAOFFSET";
1180 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
1181 case PPCISD::SRL: return "PPCISD::SRL";
1182 case PPCISD::SRA: return "PPCISD::SRA";
1183 case PPCISD::SHL: return "PPCISD::SHL";
1184 case PPCISD::SRA_ADDZE: return "PPCISD::SRA_ADDZE";
1185 case PPCISD::CALL: return "PPCISD::CALL";
1186 case PPCISD::CALL_NOP: return "PPCISD::CALL_NOP";
1187 case PPCISD::MTCTR: return "PPCISD::MTCTR";
1188 case PPCISD::BCTRL: return "PPCISD::BCTRL";
1189 case PPCISD::BCTRL_LOAD_TOC: return "PPCISD::BCTRL_LOAD_TOC";
1190 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
1191 case PPCISD::READ_TIME_BASE: return "PPCISD::READ_TIME_BASE";
1192 case PPCISD::EH_SJLJ_SETJMP: return "PPCISD::EH_SJLJ_SETJMP";
1193 case PPCISD::EH_SJLJ_LONGJMP: return "PPCISD::EH_SJLJ_LONGJMP";
1194 case PPCISD::MFOCRF: return "PPCISD::MFOCRF";
1195 case PPCISD::MFVSR: return "PPCISD::MFVSR";
1196 case PPCISD::MTVSRA: return "PPCISD::MTVSRA";
1197 case PPCISD::MTVSRZ: return "PPCISD::MTVSRZ";
1198 case PPCISD::SINT_VEC_TO_FP: return "PPCISD::SINT_VEC_TO_FP";
1199 case PPCISD::UINT_VEC_TO_FP: return "PPCISD::UINT_VEC_TO_FP";
1200 case PPCISD::ANDIo_1_EQ_BIT: return "PPCISD::ANDIo_1_EQ_BIT";
1201 case PPCISD::ANDIo_1_GT_BIT: return "PPCISD::ANDIo_1_GT_BIT";
1202 case PPCISD::VCMP: return "PPCISD::VCMP";
1203 case PPCISD::VCMPo: return "PPCISD::VCMPo";
1204 case PPCISD::LBRX: return "PPCISD::LBRX";
1205 case PPCISD::STBRX: return "PPCISD::STBRX";
1206 case PPCISD::LFIWAX: return "PPCISD::LFIWAX";
1207 case PPCISD::LFIWZX: return "PPCISD::LFIWZX";
1208 case PPCISD::LXSIZX: return "PPCISD::LXSIZX";
1209 case PPCISD::STXSIX: return "PPCISD::STXSIX";
1210 case PPCISD::VEXTS: return "PPCISD::VEXTS";
1211 case PPCISD::SExtVElems: return "PPCISD::SExtVElems";
1212 case PPCISD::LXVD2X: return "PPCISD::LXVD2X";
1213 case PPCISD::STXVD2X: return "PPCISD::STXVD2X";
1214 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
1215 case PPCISD::BDNZ: return "PPCISD::BDNZ";
1216 case PPCISD::BDZ: return "PPCISD::BDZ";
1217 case PPCISD::MFFS: return "PPCISD::MFFS";
1218 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
1219 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
1220 case PPCISD::CR6SET: return "PPCISD::CR6SET";
1221 case PPCISD::CR6UNSET: return "PPCISD::CR6UNSET";
1222 case PPCISD::PPC32_GOT: return "PPCISD::PPC32_GOT";
1223 case PPCISD::PPC32_PICGOT: return "PPCISD::PPC32_PICGOT";
1224 case PPCISD::ADDIS_GOT_TPREL_HA: return "PPCISD::ADDIS_GOT_TPREL_HA";
1225 case PPCISD::LD_GOT_TPREL_L: return "PPCISD::LD_GOT_TPREL_L";
1226 case PPCISD::ADD_TLS: return "PPCISD::ADD_TLS";
1227 case PPCISD::ADDIS_TLSGD_HA: return "PPCISD::ADDIS_TLSGD_HA";
1228 case PPCISD::ADDI_TLSGD_L: return "PPCISD::ADDI_TLSGD_L";
1229 case PPCISD::GET_TLS_ADDR: return "PPCISD::GET_TLS_ADDR";
1230 case PPCISD::ADDI_TLSGD_L_ADDR: return "PPCISD::ADDI_TLSGD_L_ADDR";
1231 case PPCISD::ADDIS_TLSLD_HA: return "PPCISD::ADDIS_TLSLD_HA";
1232 case PPCISD::ADDI_TLSLD_L: return "PPCISD::ADDI_TLSLD_L";
1233 case PPCISD::GET_TLSLD_ADDR: return "PPCISD::GET_TLSLD_ADDR";
1234 case PPCISD::ADDI_TLSLD_L_ADDR: return "PPCISD::ADDI_TLSLD_L_ADDR";
1235 case PPCISD::ADDIS_DTPREL_HA: return "PPCISD::ADDIS_DTPREL_HA";
1236 case PPCISD::ADDI_DTPREL_L: return "PPCISD::ADDI_DTPREL_L";
1237 case PPCISD::VADD_SPLAT: return "PPCISD::VADD_SPLAT";
1238 case PPCISD::SC: return "PPCISD::SC";
1239 case PPCISD::CLRBHRB: return "PPCISD::CLRBHRB";
1240 case PPCISD::MFBHRBE: return "PPCISD::MFBHRBE";
1241 case PPCISD::RFEBB: return "PPCISD::RFEBB";
1242 case PPCISD::XXSWAPD: return "PPCISD::XXSWAPD";
1243 case PPCISD::SWAP_NO_CHAIN: return "PPCISD::SWAP_NO_CHAIN";
1244 case PPCISD::QVFPERM: return "PPCISD::QVFPERM";
1245 case PPCISD::QVGPCI: return "PPCISD::QVGPCI";
1246 case PPCISD::QVALIGNI: return "PPCISD::QVALIGNI";
1247 case PPCISD::QVESPLATI: return "PPCISD::QVESPLATI";
1248 case PPCISD::QBFLT: return "PPCISD::QBFLT";
1249 case PPCISD::QVLFSb: return "PPCISD::QVLFSb";
1250 }
1251 return nullptr;
1252}
1253
1254EVT PPCTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &C,
1255 EVT VT) const {
1256 if (!VT.isVector())
1257 return Subtarget.useCRBits() ? MVT::i1 : MVT::i32;
1258
1259 if (Subtarget.hasQPX())
1260 return EVT::getVectorVT(C, MVT::i1, VT.getVectorNumElements());
1261
1262 return VT.changeVectorElementTypeToInteger();
1263}
1264
1265bool PPCTargetLowering::enableAggressiveFMAFusion(EVT VT) const {
1266 assert(VT.isFloatingPoint() && "Non-floating-point FMA?")(static_cast <bool> (VT.isFloatingPoint() && "Non-floating-point FMA?"
) ? void (0) : __assert_fail ("VT.isFloatingPoint() && \"Non-floating-point FMA?\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/PowerPC/PPCISelLowering.cpp"
, 1266, __extension__ __PRETTY_FUNCTION__))
;
1267 return true;
1268}
1269
1270//===----------------------------------------------------------------------===//
1271// Node matching predicates, for use by the tblgen matching code.
1272//===----------------------------------------------------------------------===//
1273
1274/// isFloatingPointZero - Return true if this is 0.0 or -0.0.
1275static bool isFloatingPointZero(SDValue Op) {
1276 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
1277 return CFP->getValueAPF().isZero();
1278 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
1279 // Maybe this has already been legalized into the constant pool?
1280 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
1281 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
1282 return CFP->getValueAPF().isZero();
1283 }
1284 return false;
1285}
1286
1287/// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
1288/// true if Op is undef or if it matches the specified value.
1289static bool isConstantOrUndef(int Op, int Val) {
1290 return Op < 0 || Op == Val;
1291}
1292
1293/// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
1294/// VPKUHUM instruction.
1295/// The ShuffleKind distinguishes between big-endian operations with
1296/// two different inputs (0), either-endian operations with two identical
1297/// inputs (1), and little-endian operations with two different inputs (2).
1298/// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
1299bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
1300 SelectionDAG &DAG) {
1301 bool IsLE = DAG.getDataLayout().isLittleEndian();
1302 if (ShuffleKind == 0) {
1303 if (IsLE)
1304 return false;
1305 for (unsigned i = 0; i != 16; ++i)
1306 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1))
1307 return false;
1308 } else if (ShuffleKind == 2) {
1309 if (!IsLE)
1310 return false;
1311 for (unsigned i = 0; i != 16; ++i)
1312 if (!isConstantOrUndef(N->getMaskElt(i), i*2))
1313 return false;
1314 } else if (ShuffleKind == 1) {
1315 unsigned j = IsLE ? 0 : 1;
1316 for (unsigned i = 0; i != 8; ++i)
1317 if (!isConstantOrUndef(N->getMaskElt(i), i*2+j) ||
1318 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j))
1319 return false;
1320 }
1321 return true;
1322}
1323
1324/// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
1325/// VPKUWUM instruction.
1326/// The ShuffleKind distinguishes between big-endian operations with
1327/// two different inputs (0), either-endian operations with two identical
1328/// inputs (1), and little-endian operations with two different inputs (2).
1329/// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
1330bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
1331 SelectionDAG &DAG) {
1332 bool IsLE = DAG.getDataLayout().isLittleEndian();
1333 if (ShuffleKind == 0) {
1334 if (IsLE)
1335 return false;
1336 for (unsigned i = 0; i != 16; i += 2)
1337 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
1338 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3))
1339 return false;
1340 } else if (ShuffleKind == 2) {
1341 if (!IsLE)
1342 return false;
1343 for (unsigned i = 0; i != 16; i += 2)
1344 if (!isConstantOrUndef(N->getMaskElt(i ), i*2) ||
1345 !isConstantOrUndef(N->getMaskElt(i+1), i*2+1))
1346 return false;
1347 } else if (ShuffleKind == 1) {
1348 unsigned j = IsLE ? 0 : 2;
1349 for (unsigned i = 0; i != 8; i += 2)
1350 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
1351 !isConstantOrUndef(N->getMaskElt(i+1), i*2+j+1) ||
1352 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j) ||
1353 !isConstantOrUndef(N->getMaskElt(i+9), i*2+j+1))
1354 return false;
1355 }
1356 return true;
1357}
1358
1359/// isVPKUDUMShuffleMask - Return true if this is the shuffle mask for a
1360/// VPKUDUM instruction, AND the VPKUDUM instruction exists for the
1361/// current subtarget.
1362///
1363/// The ShuffleKind distinguishes between big-endian operations with
1364/// two different inputs (0), either-endian operations with two identical
1365/// inputs (1), and little-endian operations with two different inputs (2).
1366/// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
1367bool PPC::isVPKUDUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
1368 SelectionDAG &DAG) {
1369 const PPCSubtarget& Subtarget =
1370 static_cast<const PPCSubtarget&>(DAG.getSubtarget());
1371 if (!Subtarget.hasP8Vector())
1372 return false;
1373
1374 bool IsLE = DAG.getDataLayout().isLittleEndian();
1375 if (ShuffleKind == 0) {
1376 if (IsLE)
1377 return false;
1378 for (unsigned i = 0; i != 16; i += 4)
1379 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+4) ||
1380 !isConstantOrUndef(N->getMaskElt(i+1), i*2+5) ||
1381 !isConstantOrUndef(N->getMaskElt(i+2), i*2+6) ||
1382 !isConstantOrUndef(N->getMaskElt(i+3), i*2+7))
1383 return false;
1384 } else if (ShuffleKind == 2) {
1385 if (!IsLE)
1386 return false;
1387 for (unsigned i = 0; i != 16; i += 4)
1388 if (!isConstantOrUndef(N->getMaskElt(i ), i*2) ||
1389 !isConstantOrUndef(N->getMaskElt(i+1), i*2+1) ||
1390 !isConstantOrUndef(N->getMaskElt(i+2), i*2+2) ||
1391 !isConstantOrUndef(N->getMaskElt(i+3), i*2+3))
1392 return false;
1393 } else if (ShuffleKind == 1) {
1394 unsigned j = IsLE ? 0 : 4;
1395 for (unsigned i = 0; i != 8; i += 4)
1396 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
1397 !isConstantOrUndef(N->getMaskElt(i+1), i*2+j+1) ||
1398 !isConstantOrUndef(N->getMaskElt(i+2), i*2+j+2) ||
1399 !isConstantOrUndef(N->getMaskElt(i+3), i*2+j+3) ||
1400 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j) ||
1401 !isConstantOrUndef(N->getMaskElt(i+9), i*2+j+1) ||
1402 !isConstantOrUndef(N->getMaskElt(i+10), i*2+j+2) ||
1403 !isConstantOrUndef(N->getMaskElt(i+11), i*2+j+3))
1404 return false;
1405 }
1406 return true;
1407}
1408
1409/// isVMerge - Common function, used to match vmrg* shuffles.
1410///
1411static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
1412 unsigned LHSStart, unsigned RHSStart) {
1413 if (N->getValueType(0) != MVT::v16i8)
1414 return false;
1415 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&(static_cast <bool> ((UnitSize == 1 || UnitSize == 2 ||
UnitSize == 4) && "Unsupported merge size!") ? void (
0) : __assert_fail ("(UnitSize == 1 || UnitSize == 2 || UnitSize == 4) && \"Unsupported merge size!\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/PowerPC/PPCISelLowering.cpp"
, 1416, __extension__ __PRETTY_FUNCTION__))
1416 "Unsupported merge size!")(static_cast <bool> ((UnitSize == 1 || UnitSize == 2 ||
UnitSize == 4) && "Unsupported merge size!") ? void (
0) : __assert_fail ("(UnitSize == 1 || UnitSize == 2 || UnitSize == 4) && \"Unsupported merge size!\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/PowerPC/PPCISelLowering.cpp"
, 1416, __extension__ __PRETTY_FUNCTION__))
;
1417
1418 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
1419 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
1420 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j),
1421 LHSStart+j+i*UnitSize) ||
1422 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j),
1423 RHSStart+j+i*UnitSize))
1424 return false;
1425 }
1426 return true;
1427}
1428
1429/// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
1430/// a VMRGL* instruction with the specified unit size (1,2 or 4 bytes).
1431/// The ShuffleKind distinguishes between big-endian merges with two
1432/// different inputs (0), either-endian merges with two identical inputs (1),
1433/// and little-endian merges with two different inputs (2). For the latter,
1434/// the input operands are swapped (see PPCInstrAltivec.td).
1435bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
1436 unsigned ShuffleKind, SelectionDAG &DAG) {
1437 if (DAG.getDataLayout().isLittleEndian()) {
1438 if (ShuffleKind == 1) // unary
1439 return isVMerge(N, UnitSize, 0, 0);
1440 else if (ShuffleKind == 2) // swapped
1441 return isVMerge(N, UnitSize, 0, 16);
1442 else
1443 return false;
1444 } else {
1445 if (ShuffleKind == 1) // unary
1446 return isVMerge(N, UnitSize, 8, 8);
1447 else if (ShuffleKind == 0) // normal
1448 return isVMerge(N, UnitSize, 8, 24);
1449 else
1450 return false;
1451 }
1452}
1453
1454/// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
1455/// a VMRGH* instruction with the specified unit size (1,2 or 4 bytes).
1456/// The ShuffleKind distinguishes between big-endian merges with two
1457/// different inputs (0), either-endian merges with two identical inputs (1),
1458/// and little-endian merges with two different inputs (2). For the latter,
1459/// the input operands are swapped (see PPCInstrAltivec.td).
1460bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
1461 unsigned ShuffleKind, SelectionDAG &DAG) {
1462 if (DAG.getDataLayout().isLittleEndian()) {
1463 if (ShuffleKind == 1) // unary
1464 return isVMerge(N, UnitSize, 8, 8);
1465 else if (ShuffleKind == 2) // swapped
1466 return isVMerge(N, UnitSize, 8, 24);
1467 else
1468 return false;
1469 } else {
1470 if (ShuffleKind == 1) // unary
1471 return isVMerge(N, UnitSize, 0, 0);
1472 else if (ShuffleKind == 0) // normal
1473 return isVMerge(N, UnitSize, 0, 16);
1474 else
1475 return false;
1476 }
1477}
1478
1479/**
1480 * \brief Common function used to match vmrgew and vmrgow shuffles
1481 *
1482 * The indexOffset determines whether to look for even or odd words in
1483 * the shuffle mask. This is based on the of the endianness of the target
1484 * machine.
1485 * - Little Endian:
1486 * - Use offset of 0 to check for odd elements
1487 * - Use offset of 4 to check for even elements
1488 * - Big Endian:
1489 * - Use offset of 0 to check for even elements
1490 * - Use offset of 4 to check for odd elements
1491 * A detailed description of the vector element ordering for little endian and
1492 * big endian can be found at
1493 * http://www.ibm.com/developerworks/library/l-ibm-xl-c-cpp-compiler/index.html
1494 * Targeting your applications - what little endian and big endian IBM XL C/C++
1495 * compiler differences mean to you
1496 *
1497 * The mask to the shuffle vector instruction specifies the indices of the
1498 * elements from the two input vectors to place in the result. The elements are
1499 * numbered in array-access order, starting with the first vector. These vectors
1500 * are always of type v16i8, thus each vector will contain 16 elements of size
1501 * 8. More info on the shuffle vector can be found in the
1502 * http://llvm.org/docs/LangRef.html#shufflevector-instruction
1503 * Language Reference.
1504 *
1505 * The RHSStartValue indicates whether the same input vectors are used (unary)
1506 * or two different input vectors are used, based on the following:
1507 * - If the instruction uses the same vector for both inputs, the range of the
1508 * indices will be 0 to 15. In this case, the RHSStart value passed should
1509 * be 0.
1510 * - If the instruction has two different vectors then the range of the
1511 * indices will be 0 to 31. In this case, the RHSStart value passed should
1512 * be 16 (indices 0-15 specify elements in the first vector while indices 16
1513 * to 31 specify elements in the second vector).
1514 *
1515 * \param[in] N The shuffle vector SD Node to analyze
1516 * \param[in] IndexOffset Specifies whether to look for even or odd elements
1517 * \param[in] RHSStartValue Specifies the starting index for the righthand input
1518 * vector to the shuffle_vector instruction
1519 * \return true iff this shuffle vector represents an even or odd word merge
1520 */
1521static bool isVMerge(ShuffleVectorSDNode *N, unsigned IndexOffset,
1522 unsigned RHSStartValue) {
1523 if (N->getValueType(0) != MVT::v16i8)
1524 return false;
1525
1526 for (unsigned i = 0; i < 2; ++i)
1527 for (unsigned j = 0; j < 4; ++j)
1528 if (!isConstantOrUndef(N->getMaskElt(i*4+j),
1529 i*RHSStartValue+j+IndexOffset) ||
1530 !isConstantOrUndef(N->getMaskElt(i*4+j+8),
1531 i*RHSStartValue+j+IndexOffset+8))
1532 return false;
1533 return true;
1534}
1535
1536/**
1537 * \brief Determine if the specified shuffle mask is suitable for the vmrgew or
1538 * vmrgow instructions.
1539 *
1540 * \param[in] N The shuffle vector SD Node to analyze
1541 * \param[in] CheckEven Check for an even merge (true) or an odd merge (false)
1542 * \param[in] ShuffleKind Identify the type of merge:
1543 * - 0 = big-endian merge with two different inputs;
1544 * - 1 = either-endian merge with two identical inputs;
1545 * - 2 = little-endian merge with two different inputs (inputs are swapped for
1546 * little-endian merges).
1547 * \param[in] DAG The current SelectionDAG
1548 * \return true iff this shuffle mask
1549 */
1550bool PPC::isVMRGEOShuffleMask(ShuffleVectorSDNode *N, bool CheckEven,
1551 unsigned ShuffleKind, SelectionDAG &DAG) {
1552 if (DAG.getDataLayout().isLittleEndian()) {
1553 unsigned indexOffset = CheckEven ? 4 : 0;
1554 if (ShuffleKind == 1) // Unary
1555 return isVMerge(N, indexOffset, 0);
1556 else if (ShuffleKind == 2) // swapped
1557 return isVMerge(N, indexOffset, 16);
1558 else
1559 return false;
1560 }
1561 else {
1562 unsigned indexOffset = CheckEven ? 0 : 4;
1563 if (ShuffleKind == 1) // Unary
1564 return isVMerge(N, indexOffset, 0);
1565 else if (ShuffleKind == 0) // Normal
1566 return isVMerge(N, indexOffset, 16);
1567 else
1568 return false;
1569 }
1570 return false;
1571}
1572
1573/// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
1574/// amount, otherwise return -1.
1575/// The ShuffleKind distinguishes between big-endian operations with two
1576/// different inputs (0), either-endian operations with two identical inputs
1577/// (1), and little-endian operations with two different inputs (2). For the
1578/// latter, the input operands are swapped (see PPCInstrAltivec.td).
1579int PPC::isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind,
1580 SelectionDAG &DAG) {
1581 if (N->getValueType(0) != MVT::v16i8)
1582 return -1;
1583
1584 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1585
1586 // Find the first non-undef value in the shuffle mask.
1587 unsigned i;
1588 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i)
1589 /*search*/;
1590
1591 if (i == 16) return -1; // all undef.
1592
1593 // Otherwise, check to see if the rest of the elements are consecutively
1594 // numbered from this value.
1595 unsigned ShiftAmt = SVOp->getMaskElt(i);
1596 if (ShiftAmt < i) return -1;
1597
1598 ShiftAmt -= i;
1599 bool isLE = DAG.getDataLayout().isLittleEndian();
1600
1601 if ((ShuffleKind == 0 && !isLE) || (ShuffleKind == 2 && isLE)) {
1602 // Check the rest of the elements to see if they are consecutive.
1603 for (++i; i != 16; ++i)
1604 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
1605 return -1;
1606 } else if (ShuffleKind == 1) {
1607 // Check the rest of the elements to see if they are consecutive.
1608 for (++i; i != 16; ++i)
1609 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
1610 return -1;
1611 } else
1612 return -1;
1613
1614 if (isLE)
1615 ShiftAmt = 16 - ShiftAmt;
1616
1617 return ShiftAmt;
1618}
1619
1620/// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
1621/// specifies a splat of a single element that is suitable for input to
1622/// VSPLTB/VSPLTH/VSPLTW.
1623bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) {
1624 assert(N->getValueType(0) == MVT::v16i8 &&(static_cast <bool> (N->getValueType(0) == MVT::v16i8
&& (EltSize == 1 || EltSize == 2 || EltSize == 4)) ?
void (0) : __assert_fail ("N->getValueType(0) == MVT::v16i8 && (EltSize == 1 || EltSize == 2 || EltSize == 4)"
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/PowerPC/PPCISelLowering.cpp"
, 1625, __extension__ __PRETTY_FUNCTION__))
1625 (EltSize == 1 || EltSize == 2 || EltSize == 4))(static_cast <bool> (N->getValueType(0) == MVT::v16i8
&& (EltSize == 1 || EltSize == 2 || EltSize == 4)) ?
void (0) : __assert_fail ("N->getValueType(0) == MVT::v16i8 && (EltSize == 1 || EltSize == 2 || EltSize == 4)"
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/PowerPC/PPCISelLowering.cpp"
, 1625, __extension__ __PRETTY_FUNCTION__))
;
1626
1627 // The consecutive indices need to specify an element, not part of two
1628 // different elements. So abandon ship early if this isn't the case.
1629 if (N->getMaskElt(0) % EltSize != 0)
1630 return false;
1631
1632 // This is a splat operation if each element of the permute is the same, and
1633 // if the value doesn't reference the second vector.
1634 unsigned ElementBase = N->getMaskElt(0);
1635
1636 // FIXME: Handle UNDEF elements too!
1637 if (ElementBase >= 16)
1638 return false;
1639
1640 // Check that the indices are consecutive, in the case of a multi-byte element
1641 // splatted with a v16i8 mask.
1642 for (unsigned i = 1; i != EltSize; ++i)
1643 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase))
1644 return false;
1645
1646 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
1647 if (N->getMaskElt(i) < 0) continue;
1648 for (unsigned j = 0; j != EltSize; ++j)
1649 if (N->getMaskElt(i+j) != N->getMaskElt(j))
1650 return false;
1651 }
1652 return true;
1653}
1654
1655/// Check that the mask is shuffling N byte elements. Within each N byte
1656/// element of the mask, the indices could be either in increasing or
1657/// decreasing order as long as they are consecutive.
1658/// \param[in] N the shuffle vector SD Node to analyze
1659/// \param[in] Width the element width in bytes, could be 2/4/8/16 (HalfWord/
1660/// Word/DoubleWord/QuadWord).
1661/// \param[in] StepLen the delta indices number among the N byte element, if
1662/// the mask is in increasing/decreasing order then it is 1/-1.
1663/// \return true iff the mask is shuffling N byte elements.
1664static bool isNByteElemShuffleMask(ShuffleVectorSDNode *N, unsigned Width,
1665 int StepLen) {
1666 assert((Width == 2 || Width == 4 || Width == 8 || Width == 16) &&(static_cast <bool> ((Width == 2 || Width == 4 || Width
== 8 || Width == 16) && "Unexpected element width.")
? void (0) : __assert_fail ("(Width == 2 || Width == 4 || Width == 8 || Width == 16) && \"Unexpected element width.\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/PowerPC/PPCISelLowering.cpp"
, 1667, __extension__ __PRETTY_FUNCTION__))
1667 "Unexpected element width.")(static_cast <bool> ((Width == 2 || Width == 4 || Width
== 8 || Width == 16) && "Unexpected element width.")
? void (0) : __assert_fail ("(Width == 2 || Width == 4 || Width == 8 || Width == 16) && \"Unexpected element width.\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/PowerPC/PPCISelLowering.cpp"
, 1667, __extension__ __PRETTY_FUNCTION__))
;
1668 assert((StepLen == 1 || StepLen == -1) && "Unexpected element width.")(static_cast <bool> ((StepLen == 1 || StepLen == -1) &&
"Unexpected element width.") ? void (0) : __assert_fail ("(StepLen == 1 || StepLen == -1) && \"Unexpected element width.\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/PowerPC/PPCISelLowering.cpp"
, 1668, __extension__ __PRETTY_FUNCTION__))
;
1669
1670 unsigned NumOfElem = 16 / Width;
1671 unsigned MaskVal[16]; // Width is never greater than 16
1672 for (unsigned i = 0; i < NumOfElem; ++i) {
1673 MaskVal[0] = N->getMaskElt(i * Width);
1674 if ((StepLen == 1) && (MaskVal[0] % Width)) {
1675 return false;
1676 } else if ((StepLen == -1) && ((MaskVal[0] + 1) % Width)) {
1677 return false;
1678 }
1679
1680 for (unsigned int j = 1; j < Width; ++j) {
1681 MaskVal[j] = N->getMaskElt(i * Width + j);
1682 if (MaskVal[j] != MaskVal[j-1] + StepLen) {
1683 return false;
1684 }
1685 }
1686 }
1687
1688 return true;
1689}
1690
1691bool PPC::isXXINSERTWMask(ShuffleVectorSDNode *N, unsigned &ShiftElts,
1692 unsigned &InsertAtByte, bool &Swap, bool IsLE) {
1693 if (!isNByteElemShuffleMask(N, 4, 1))
1694 return false;
1695
1696 // Now we look at mask elements 0,4,8,12
1697 unsigned M0 = N->getMaskElt(0) / 4;
1698 unsigned M1 = N->getMaskElt(4) / 4;
1699 unsigned M2 = N->getMaskElt(8) / 4;
1700 unsigned M3 = N->getMaskElt(12) / 4;
1701 unsigned LittleEndianShifts[] = { 2, 1, 0, 3 };
1702 unsigned BigEndianShifts[] = { 3, 0, 1, 2 };
1703
1704 // Below, let H and L be arbitrary elements of the shuffle mask
1705 // where H is in the range [4,7] and L is in the range [0,3].
1706 // H, 1, 2, 3 or L, 5, 6, 7
1707 if ((M0 > 3 && M1 == 1 && M2 == 2 && M3 == 3) ||
1708 (M0 < 4 && M1 == 5 && M2 == 6 && M3 == 7)) {
1709 ShiftElts = IsLE ? LittleEndianShifts[M0 & 0x3] : BigEndianShifts[M0 & 0x3];
1710 InsertAtByte = IsLE ? 12 : 0;
1711 Swap = M0 < 4;
1712 return true;
1713 }
1714 // 0, H, 2, 3 or 4, L, 6, 7
1715 if ((M1 > 3 && M0 == 0 && M2 == 2 && M3 == 3) ||
1716 (M1 < 4 && M0 == 4 && M2 == 6 && M3 == 7)) {
1717 ShiftElts = IsLE ? LittleEndianShifts[M1 & 0x3] : BigEndianShifts[M1 & 0x3];
1718 InsertAtByte = IsLE ? 8 : 4;
1719 Swap = M1 < 4;
1720 return true;
1721 }
1722 // 0, 1, H, 3 or 4, 5, L, 7
1723 if ((M2 > 3 && M0 == 0 && M1 == 1 && M3 == 3) ||
1724 (M2 < 4 && M0 == 4 && M1 == 5 && M3 == 7)) {
1725 ShiftElts = IsLE ? LittleEndianShifts[M2 & 0x3] : BigEndianShifts[M2 & 0x3];
1726 InsertAtByte = IsLE ? 4 : 8;
1727 Swap = M2 < 4;
1728 return true;
1729 }
1730 // 0, 1, 2, H or 4, 5, 6, L
1731 if ((M3 > 3 && M0 == 0 && M1 == 1 && M2 == 2) ||
1732 (M3 < 4 && M0 == 4 && M1 == 5 && M2 == 6)) {
1733 ShiftElts = IsLE ? LittleEndianShifts[M3 & 0x3] : BigEndianShifts[M3 & 0x3];
1734 InsertAtByte = IsLE ? 0 : 12;
1735 Swap = M3 < 4;
1736 return true;
1737 }
1738
1739 // If both vector operands for the shuffle are the same vector, the mask will
1740 // contain only elements from the first one and the second one will be undef.
1741 if (N->getOperand(1).isUndef()) {
1742 ShiftElts = 0;
1743 Swap = true;
1744 unsigned XXINSERTWSrcElem = IsLE ? 2 : 1;
1745 if (M0 == XXINSERTWSrcElem && M1 == 1 && M2 == 2 && M3 == 3) {
1746 InsertAtByte = IsLE ? 12 : 0;
1747 return true;
1748 }
1749 if (M0 == 0 && M1 == XXINSERTWSrcElem && M2 == 2 && M3 == 3) {
1750 InsertAtByte = IsLE ? 8 : 4;
1751 return true;
1752 }
1753 if (M0 == 0 && M1 == 1 && M2 == XXINSERTWSrcElem && M3 == 3) {
1754 InsertAtByte = IsLE ? 4 : 8;
1755 return true;
1756 }
1757 if (M0 == 0 && M1 == 1 && M2 == 2 && M3 == XXINSERTWSrcElem) {
1758 InsertAtByte = IsLE ? 0 : 12;
1759 return true;
1760 }
1761 }
1762
1763 return false;
1764}
1765
1766bool PPC::isXXSLDWIShuffleMask(ShuffleVectorSDNode *N, unsigned &ShiftElts,
1767 bool &Swap, bool IsLE) {
1768 assert(N->getValueType(0) == MVT::v16i8 && "Shuffle vector expects v16i8")(static_cast <bool> (N->getValueType(0) == MVT::v16i8
&& "Shuffle vector expects v16i8") ? void (0) : __assert_fail
("N->getValueType(0) == MVT::v16i8 && \"Shuffle vector expects v16i8\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/PowerPC/PPCISelLowering.cpp"
, 1768, __extension__ __PRETTY_FUNCTION__))
;
9
Within the expansion of the macro 'assert':
1769 // Ensure each byte index of the word is consecutive.
1770 if (!isNByteElemShuffleMask(N, 4, 1))
10
Assuming the condition is false
11
Taking false branch
1771 return false;
1772
1773 // Now we look at mask elements 0,4,8,12, which are the beginning of words.
1774 unsigned M0 = N->getMaskElt(0) / 4;
1775 unsigned M1 = N->getMaskElt(4) / 4;
1776 unsigned M2 = N->getMaskElt(8) / 4;
1777 unsigned M3 = N->getMaskElt(12) / 4;
1778
1779 // If both vector operands for the shuffle are the same vector, the mask will
1780 // contain only elements from the first one and the second one will be undef.
1781 if (N->getOperand(1).isUndef()) {
12
Taking false branch
1782 assert(M0 < 4 && "Indexing into an undef vector?")(static_cast <bool> (M0 < 4 && "Indexing into an undef vector?"
) ? void (0) : __assert_fail ("M0 < 4 && \"Indexing into an undef vector?\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/PowerPC/PPCISelLowering.cpp"
, 1782, __extension__ __PRETTY_FUNCTION__))
;
1783 if (M1 != (M0 + 1) % 4 || M2 != (M1 + 1) % 4 || M3 != (M2 + 1) % 4)
1784 return false;
1785
1786 ShiftElts = IsLE ? (4 - M0) % 4 : M0;
1787 Swap = false;
1788 return true;
1789 }
1790
1791 // Ensure each word index of the ShuffleVector Mask is consecutive.
1792 if (M1 != (M0 + 1) % 8 || M2 != (M1 + 1) % 8 || M3 != (M2 + 1) % 8)
13
Taking false branch
1793 return false;
1794
1795 if (IsLE) {
14
Assuming 'IsLE' is 0
15
Taking false branch
1796 if (M0 == 0 || M0 == 7 || M0 == 6 || M0 == 5) {
1797 // Input vectors don't need to be swapped if the leading element
1798 // of the result is one of the 3 left elements of the second vector
1799 // (or if there is no shift to be done at all).
1800 Swap = false;
1801 ShiftElts = (8 - M0) % 8;
1802 } else if (M0 == 4 || M0 == 3 || M0 == 2 || M0 == 1) {
1803 // Input vectors need to be swapped if the leading element
1804 // of the result is one of the 3 left elements of the first vector
1805 // (or if we're shifting by 4 - thereby simply swapping the vectors).
1806 Swap = true;
1807 ShiftElts = (4 - M0) % 4;
1808 }
1809
1810 return true;
1811 } else { // BE
1812 if (M0 == 0 || M0 == 1 || M0 == 2 || M0 == 3) {
16
Assuming 'M0' is not equal to 0
17
Assuming 'M0' is not equal to 1
18
Assuming 'M0' is not equal to 2
19
Assuming 'M0' is not equal to 3
20
Taking false branch
1813 // Input vectors don't need to be swapped if the leading element
1814 // of the result is one of the 4 elements of the first vector.
1815 Swap = false;
1816 ShiftElts = M0;
1817 } else if (M0 == 4 || M0 == 5 || M0 == 6 || M0 == 7) {
21
Assuming 'M0' is not equal to 4
22
Assuming 'M0' is not equal to 5
23
Assuming 'M0' is not equal to 6
24
Assuming 'M0' is not equal to 7
25
Taking false branch
1818 // Input vectors need to be swapped if the leading element
1819 // of the result is one of the 4 elements of the right vector.
1820 Swap = true;
1821 ShiftElts = M0 - 4;
1822 }
1823
1824 return true;
26
Returning without writing to 'ShiftElts'
1825 }
1826}
1827
1828bool static isXXBRShuffleMaskHelper(ShuffleVectorSDNode *N, int Width) {
1829 assert(N->getValueType(0) == MVT::v16i8 && "Shuffle vector expects v16i8")(static_cast <bool> (N->getValueType(0) == MVT::v16i8
&& "Shuffle vector expects v16i8") ? void (0) : __assert_fail
("N->getValueType(0) == MVT::v16i8 && \"Shuffle vector expects v16i8\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/PowerPC/PPCISelLowering.cpp"
, 1829, __extension__ __PRETTY_FUNCTION__))
;
1830
1831 if (!isNByteElemShuffleMask(N, Width, -1))
1832 return false;
1833
1834 for (int i = 0; i < 16; i += Width)
1835 if (N->getMaskElt(i) != i + Width - 1)
1836 return false;
1837
1838 return true;
1839}
1840
1841bool PPC::isXXBRHShuffleMask(ShuffleVectorSDNode *N) {
1842 return isXXBRShuffleMaskHelper(N, 2);
1843}
1844
1845bool PPC::isXXBRWShuffleMask(ShuffleVectorSDNode *N) {
1846 return isXXBRShuffleMaskHelper(N, 4);
1847}
1848
1849bool PPC::isXXBRDShuffleMask(ShuffleVectorSDNode *N) {
1850 return isXXBRShuffleMaskHelper(N, 8);
1851}
1852
1853bool PPC::isXXBRQShuffleMask(ShuffleVectorSDNode *N) {
1854 return isXXBRShuffleMaskHelper(N, 16);
1855}
1856
1857/// Can node \p N be lowered to an XXPERMDI instruction? If so, set \p Swap
1858/// if the inputs to the instruction should be swapped and set \p DM to the
1859/// value for the immediate.
1860/// Specifically, set \p Swap to true only if \p N can be lowered to XXPERMDI
1861/// AND element 0 of the result comes from the first input (LE) or second input
1862/// (BE). Set \p DM to the calculated result (0-3) only if \p N can be lowered.
1863/// \return true iff the given mask of shuffle node \p N is a XXPERMDI shuffle
1864/// mask.
1865bool PPC::isXXPERMDIShuffleMask(ShuffleVectorSDNode *N, unsigned &DM,
1866 bool &Swap, bool IsLE) {
1867 assert(N->getValueType(0) == MVT::v16i8 && "Shuffle vector expects v16i8")(static_cast <bool> (N->getValueType(0) == MVT::v16i8
&& "Shuffle vector expects v16i8") ? void (0) : __assert_fail
("N->getValueType(0) == MVT::v16i8 && \"Shuffle vector expects v16i8\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/PowerPC/PPCISelLowering.cpp"
, 1867, __extension__ __PRETTY_FUNCTION__))
;
1868
1869 // Ensure each byte index of the double word is consecutive.
1870 if (!isNByteElemShuffleMask(N, 8, 1))
1871 return false;
1872
1873 unsigned M0 = N->getMaskElt(0) / 8;
1874 unsigned M1 = N->getMaskElt(8) / 8;
1875 assert(((M0 | M1) < 4) && "A mask element out of bounds?")(static_cast <bool> (((M0 | M1) < 4) && "A mask element out of bounds?"
) ? void (0) : __assert_fail ("((M0 | M1) < 4) && \"A mask element out of bounds?\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/PowerPC/PPCISelLowering.cpp"
, 1875, __extension__ __PRETTY_FUNCTION__))
;
1876
1877 // If both vector operands for the shuffle are the same vector, the mask will
1878 // contain only elements from the first one and the second one will be undef.
1879 if (N->getOperand(1).isUndef()) {
1880 if ((M0 | M1) < 2) {
1881 DM = IsLE ? (((~M1) & 1) << 1) + ((~M0) & 1) : (M0 << 1) + (M1 & 1);
1882 Swap = false;
1883 return true;
1884 } else
1885 return false;
1886 }
1887
1888 if (IsLE) {
1889 if (M0 > 1 && M1 < 2) {
1890 Swap = false;
1891 } else if (M0 < 2 && M1 > 1) {
1892 M0 = (M0 + 2) % 4;
1893 M1 = (M1 + 2) % 4;
1894 Swap = true;
1895 } else
1896 return false;
1897
1898 // Note: if control flow comes here that means Swap is already set above
1899 DM = (((~M1) & 1) << 1) + ((~M0) & 1);
1900 return true;
1901 } else { // BE
1902 if (M0 < 2 && M1 > 1) {
1903 Swap = false;
1904 } else if (M0 > 1 && M1 < 2) {
1905 M0 = (M0 + 2) % 4;
1906 M1 = (M1 + 2) % 4;
1907 Swap = true;
1908 } else
1909 return false;
1910
1911 // Note: if control flow comes here that means Swap is already set above
1912 DM = (M0 << 1) + (M1 & 1);
1913 return true;
1914 }
1915}
1916
1917
1918/// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
1919/// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
1920unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize,
1921 SelectionDAG &DAG) {
1922 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1923 assert(isSplatShuffleMask(SVOp, EltSize))(static_cast <bool> (isSplatShuffleMask(SVOp, EltSize))
? void (0) : __assert_fail ("isSplatShuffleMask(SVOp, EltSize)"
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/PowerPC/PPCISelLowering.cpp"
, 1923, __extension__ __PRETTY_FUNCTION__))
;
1924 if (DAG.getDataLayout().isLittleEndian())
1925 return (16 / EltSize) - 1 - (SVOp->getMaskElt(0) / EltSize);
1926 else
1927 return SVOp->getMaskElt(0) / EltSize;
1928}
1929
1930/// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
1931/// by using a vspltis[bhw] instruction of the specified element size, return
1932/// the constant being splatted. The ByteSize field indicates the number of
1933/// bytes of each element [124] -> [bhw].
1934SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
1935 SDValue OpVal(nullptr, 0);
1936
1937 // If ByteSize of the splat is bigger than the element size of the
1938 // build_vector, then we have a case where we are checking for a splat where
1939 // multiple elements of the buildvector are folded together into a single
1940 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
1941 unsigned EltSize = 16/N->getNumOperands();
1942 if (EltSize < ByteSize) {
1943 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
1944 SDValue UniquedVals[4];
1945 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?")(static_cast <bool> (Multiple > 1 && Multiple
<= 4 && "How can this happen?") ? void (0) : __assert_fail
("Multiple > 1 && Multiple <= 4 && \"How can this happen?\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/PowerPC/PPCISelLowering.cpp"
, 1945, __extension__ __PRETTY_FUNCTION__))
;
1946
1947 // See if all of the elements in the buildvector agree across.
1948 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1949 if (N->getOperand(i).isUndef()) continue;
1950 // If the element isn't a constant, bail fully out.
1951 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
1952
1953 if (!UniquedVals[i&(Multiple-1)].getNode())
1954 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
1955 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
1956 return SDValue(); // no match.
1957 }
1958
1959 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
1960 // either constant or undef values that are identical for each chunk. See
1961 // if these chunks can form into a larger vspltis*.
1962
1963 // Check to see if all of the leading entries are either 0 or -1. If
1964 // neither, then this won't fit into the immediate field.
1965 bool LeadingZero = true;
1966 bool LeadingOnes = true;
1967 for (unsigned i = 0; i != Multiple-1; ++i) {
1968 if (!UniquedVals[i].getNode()) continue; // Must have been undefs.
1969
1970 LeadingZero &= isNullConstant(UniquedVals[i]);
1971 LeadingOnes &= isAllOnesConstant(UniquedVals[i]);
1972 }
1973 // Finally, check the least significant entry.
1974 if (LeadingZero) {
1975 if (!UniquedVals[Multiple-1].getNode())
1976 return DAG.getTargetConstant(0, SDLoc(N), MVT::i32); // 0,0,0,undef
1977 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
1978 if (Val < 16) // 0,0,0,4 -> vspltisw(4)
1979 return DAG.getTargetConstant(Val, SDLoc(N), MVT::i32);
1980 }
1981 if (LeadingOnes) {
1982 if (!UniquedVals[Multiple-1].getNode())
1983 return DAG.getTargetConstant(~0U, SDLoc(N), MVT::i32); // -1,-1,-1,undef
1984 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
1985 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
1986 return DAG.getTargetConstant(Val, SDLoc(N), MVT::i32);
1987 }
1988
1989 return SDValue();
1990 }
1991
1992 // Check to see if this buildvec has a single non-undef value in its elements.
1993 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1994 if (N->getOperand(i).isUndef()) continue;
1995 if (!OpVal.getNode())
1996 OpVal = N->getOperand(i);
1997 else if (OpVal != N->getOperand(i))
1998 return SDValue();
1999 }
2000
2001 if (!OpVal.getNode()) return SDValue(); // All UNDEF: use implicit def.
2002
2003 unsigned ValSizeInBytes = EltSize;
2004 uint64_t Value = 0;
2005 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
2006 Value = CN->getZExtValue();
2007 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
2008 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!")(static_cast <bool> (CN->getValueType(0) == MVT::f32
&& "Only one legal FP vector type!") ? void (0) : __assert_fail
("CN->getValueType(0) == MVT::f32 && \"Only one legal FP vector type!\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2008, __extension__ __PRETTY_FUNCTION__))
;
2009 Value = FloatToBits(CN->getValueAPF().convertToFloat());
2010 }
2011
2012 // If the splat value is larger than the element value, then we can never do
2013 // this splat. The only case that we could fit the replicated bits into our
2014 // immediate field for would be zero, and we prefer to use vxor for it.
2015 if (ValSizeInBytes < ByteSize) return SDValue();
2016
2017 // If the element value is larger than the splat value, check if it consists
2018 // of a repeated bit pattern of size ByteSize.
2019 if (!APInt(ValSizeInBytes * 8, Value).isSplat(ByteSize * 8))
2020 return SDValue();
2021
2022 // Properly sign extend the value.
2023 int MaskVal = SignExtend32(Value, ByteSize * 8);
2024
2025 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
2026 if (MaskVal == 0) return SDValue();
2027
2028 // Finally, if this value fits in a 5 bit sext field, return it
2029 if (SignExtend32<5>(MaskVal) == MaskVal)
2030 return DAG.getTargetConstant(MaskVal, SDLoc(N), MVT::i32);
2031 return SDValue();
2032}
2033
2034/// isQVALIGNIShuffleMask - If this is a qvaligni shuffle mask, return the shift
2035/// amount, otherwise return -1.
2036int PPC::isQVALIGNIShuffleMask(SDNode *N) {
2037 EVT VT = N->getValueType(0);
2038 if (VT != MVT::v4f64 && VT != MVT::v4f32 && VT != MVT::v4i1)
2039 return -1;
2040
2041 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
2042
2043 // Find the first non-undef value in the shuffle mask.
2044 unsigned i;
2045 for (i = 0; i != 4 && SVOp->getMaskElt(i) < 0; ++i)
2046 /*search*/;
2047
2048 if (i == 4) return -1; // all undef.
2049
2050 // Otherwise, check to see if the rest of the elements are consecutively
2051 // numbered from this value.
2052 unsigned ShiftAmt = SVOp->getMaskElt(i);
2053 if (ShiftAmt < i) return -1;
2054 ShiftAmt -= i;
2055
2056 // Check the rest of the elements to see if they are consecutive.
2057 for (++i; i != 4; ++i)
2058 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
2059 return -1;
2060
2061 return ShiftAmt;
2062}
2063
2064//===----------------------------------------------------------------------===//
2065// Addressing Mode Selection
2066//===----------------------------------------------------------------------===//
2067
2068/// isIntS16Immediate - This method tests to see if the node is either a 32-bit
2069/// or 64-bit immediate, and if the value can be accurately represented as a
2070/// sign extension from a 16-bit value. If so, this returns true and the
2071/// immediate.
2072bool llvm::isIntS16Immediate(SDNode *N, int16_t &Imm) {
2073 if (!isa<ConstantSDNode>(N))
2074 return false;
2075
2076 Imm = (int16_t)cast<ConstantSDNode>(N)->getZExtValue();
2077 if (N->getValueType(0) == MVT::i32)
2078 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
2079 else
2080 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
2081}
2082bool llvm::isIntS16Immediate(SDValue Op, int16_t &Imm) {
2083 return isIntS16Immediate(Op.getNode(), Imm);
2084}
2085
2086/// SelectAddressRegReg - Given the specified addressed, check to see if it
2087/// can be represented as an indexed [r+r] operation. Returns false if it
2088/// can be more efficiently represented with [r+imm].
2089bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base,
2090 SDValue &Index,
2091 SelectionDAG &DAG) const {
2092 int16_t imm = 0;
2093 if (N.getOpcode() == ISD::ADD) {
2094 if (isIntS16Immediate(N.getOperand(1), imm))
2095 return false; // r+i
2096 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
2097 return false; // r+i
2098
2099 Base = N.getOperand(0);
2100 Index = N.getOperand(1);
2101 return true;
2102 } else if (N.getOpcode() == ISD::OR) {
2103 if (isIntS16Immediate(N.getOperand(1), imm))
2104 return false; // r+i can fold it if we can.
2105
2106 // If this is an or of disjoint bitfields, we can codegen this as an add
2107 // (for better address arithmetic) if the LHS and RHS of the OR are provably
2108 // disjoint.
2109 KnownBits LHSKnown, RHSKnown;
2110 DAG.computeKnownBits(N.getOperand(0), LHSKnown);
2111
2112 if (LHSKnown.Zero.getBoolValue()) {
2113 DAG.computeKnownBits(N.getOperand(1), RHSKnown);
2114 // If all of the bits are known zero on the LHS or RHS, the add won't
2115 // carry.
2116 if (~(LHSKnown.Zero | RHSKnown.Zero) == 0) {
2117 Base = N.getOperand(0);
2118 Index = N.getOperand(1);
2119 return true;
2120 }
2121 }
2122 }
2123
2124 return false;
2125}
2126
2127// If we happen to be doing an i64 load or store into a stack slot that has
2128// less than a 4-byte alignment, then the frame-index elimination may need to
2129// use an indexed load or store instruction (because the offset may not be a
2130// multiple of 4). The extra register needed to hold the offset comes from the
2131// register scavenger, and it is possible that the scavenger will need to use
2132// an emergency spill slot. As a result, we need to make sure that a spill slot
2133// is allocated when doing an i64 load/store into a less-than-4-byte-aligned
2134// stack slot.
2135static void fixupFuncForFI(SelectionDAG &DAG, int FrameIdx, EVT VT) {
2136 // FIXME: This does not handle the LWA case.
2137 if (VT != MVT::i64)
2138 return;
2139
2140 // NOTE: We'll exclude negative FIs here, which come from argument
2141 // lowering, because there are no known test cases triggering this problem
2142 // using packed structures (or similar). We can remove this exclusion if
2143 // we find such a test case. The reason why this is so test-case driven is
2144 // because this entire 'fixup' is only to prevent crashes (from the
2145 // register scavenger) on not-really-valid inputs. For example, if we have:
2146 // %a = alloca i1
2147 // %b = bitcast i1* %a to i64*
2148 // store i64* a, i64 b
2149 // then the store should really be marked as 'align 1', but is not. If it
2150 // were marked as 'align 1' then the indexed form would have been
2151 // instruction-selected initially, and the problem this 'fixup' is preventing
2152 // won't happen regardless.
2153 if (FrameIdx < 0)
2154 return;
2155
2156 MachineFunction &MF = DAG.getMachineFunction();
2157 MachineFrameInfo &MFI = MF.getFrameInfo();
2158
2159 unsigned Align = MFI.getObjectAlignment(FrameIdx);
2160 if (Align >= 4)
2161 return;
2162
2163 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2164 FuncInfo->setHasNonRISpills();
2165}
2166
2167/// Returns true if the address N can be represented by a base register plus
2168/// a signed 16-bit displacement [r+imm], and if it is not better
2169/// represented as reg+reg. If \p Alignment is non-zero, only accept
2170/// displacements that are multiples of that value.
2171bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp,
2172 SDValue &Base,
2173 SelectionDAG &DAG,
2174 unsigned Alignment) const {
2175 // FIXME dl should come from parent load or store, not from address
2176 SDLoc dl(N);
2177 // If this can be more profitably realized as r+r, fail.
2178 if (SelectAddressRegReg(N, Disp, Base, DAG))
2179 return false;
2180
2181 if (N.getOpcode() == ISD::ADD) {
2182 int16_t imm = 0;
2183 if (isIntS16Immediate(N.getOperand(1), imm) &&
2184 (!Alignment || (imm % Alignment) == 0)) {
2185 Disp = DAG.getTargetConstant(imm, dl, N.getValueType());
2186 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
2187 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
2188 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
2189 } else {
2190 Base = N.getOperand(0);
2191 }
2192 return true; // [r+i]
2193 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
2194 // Match LOAD (ADD (X, Lo(G))).
2195 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()(static_cast <bool> (!cast<ConstantSDNode>(N.getOperand
(1).getOperand(1))->getZExtValue() && "Cannot handle constant offsets yet!"
) ? void (0) : __assert_fail ("!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue() && \"Cannot handle constant offsets yet!\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2196, __extension__ __PRETTY_FUNCTION__))
2196 && "Cannot handle constant offsets yet!")(static_cast <bool> (!cast<ConstantSDNode>(N.getOperand
(1).getOperand(1))->getZExtValue() && "Cannot handle constant offsets yet!"
) ? void (0) : __assert_fail ("!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue() && \"Cannot handle constant offsets yet!\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2196, __extension__ __PRETTY_FUNCTION__))
;
2197 Disp = N.getOperand(1).getOperand(0); // The global address.
2198 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||(static_cast <bool> (Disp.getOpcode() == ISD::TargetGlobalAddress
|| Disp.getOpcode() == ISD::TargetGlobalTLSAddress || Disp.getOpcode
() == ISD::TargetConstantPool || Disp.getOpcode() == ISD::TargetJumpTable
) ? void (0) : __assert_fail ("Disp.getOpcode() == ISD::TargetGlobalAddress || Disp.getOpcode() == ISD::TargetGlobalTLSAddress || Disp.getOpcode() == ISD::TargetConstantPool || Disp.getOpcode() == ISD::TargetJumpTable"
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2201, __extension__ __PRETTY_FUNCTION__))
2199 Disp.getOpcode() == ISD::TargetGlobalTLSAddress ||(static_cast <bool> (Disp.getOpcode() == ISD::TargetGlobalAddress
|| Disp.getOpcode() == ISD::TargetGlobalTLSAddress || Disp.getOpcode
() == ISD::TargetConstantPool || Disp.getOpcode() == ISD::TargetJumpTable
) ? void (0) : __assert_fail ("Disp.getOpcode() == ISD::TargetGlobalAddress || Disp.getOpcode() == ISD::TargetGlobalTLSAddress || Disp.getOpcode() == ISD::TargetConstantPool || Disp.getOpcode() == ISD::TargetJumpTable"
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2201, __extension__ __PRETTY_FUNCTION__))
2200 Disp.getOpcode() == ISD::TargetConstantPool ||(static_cast <bool> (Disp.getOpcode() == ISD::TargetGlobalAddress
|| Disp.getOpcode() == ISD::TargetGlobalTLSAddress || Disp.getOpcode
() == ISD::TargetConstantPool || Disp.getOpcode() == ISD::TargetJumpTable
) ? void (0) : __assert_fail ("Disp.getOpcode() == ISD::TargetGlobalAddress || Disp.getOpcode() == ISD::TargetGlobalTLSAddress || Disp.getOpcode() == ISD::TargetConstantPool || Disp.getOpcode() == ISD::TargetJumpTable"
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2201, __extension__ __PRETTY_FUNCTION__))
2201 Disp.getOpcode() == ISD::TargetJumpTable)(static_cast <bool> (Disp.getOpcode() == ISD::TargetGlobalAddress
|| Disp.getOpcode() == ISD::TargetGlobalTLSAddress || Disp.getOpcode
() == ISD::TargetConstantPool || Disp.getOpcode() == ISD::TargetJumpTable
) ? void (0) : __assert_fail ("Disp.getOpcode() == ISD::TargetGlobalAddress || Disp.getOpcode() == ISD::TargetGlobalTLSAddress || Disp.getOpcode() == ISD::TargetConstantPool || Disp.getOpcode() == ISD::TargetJumpTable"
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2201, __extension__ __PRETTY_FUNCTION__))
;
2202 Base = N.getOperand(0);
2203 return true; // [&g+r]
2204 }
2205 } else if (N.getOpcode() == ISD::OR) {
2206 int16_t imm = 0;
2207 if (isIntS16Immediate(N.getOperand(1), imm) &&
2208 (!Alignment || (imm % Alignment) == 0)) {
2209 // If this is an or of disjoint bitfields, we can codegen this as an add
2210 // (for better address arithmetic) if the LHS and RHS of the OR are
2211 // provably disjoint.
2212 KnownBits LHSKnown;
2213 DAG.computeKnownBits(N.getOperand(0), LHSKnown);
2214
2215 if ((LHSKnown.Zero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
2216 // If all of the bits are known zero on the LHS or RHS, the add won't
2217 // carry.
2218 if (FrameIndexSDNode *FI =
2219 dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
2220 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
2221 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
2222 } else {
2223 Base = N.getOperand(0);
2224 }
2225 Disp = DAG.getTargetConstant(imm, dl, N.getValueType());
2226 return true;
2227 }
2228 }
2229 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
2230 // Loading from a constant address.
2231
2232 // If this address fits entirely in a 16-bit sext immediate field, codegen
2233 // this as "d, 0"
2234 int16_t Imm;
2235 if (isIntS16Immediate(CN, Imm) && (!Alignment || (Imm % Alignment) == 0)) {
2236 Disp = DAG.getTargetConstant(Imm, dl, CN->getValueType(0));
2237 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
2238 CN->getValueType(0));
2239 return true;
2240 }
2241
2242 // Handle 32-bit sext immediates with LIS + addr mode.
2243 if ((CN->getValueType(0) == MVT::i32 ||
2244 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) &&
2245 (!Alignment || (CN->getZExtValue() % Alignment) == 0)) {
2246 int Addr = (int)CN->getZExtValue();
2247
2248 // Otherwise, break this down into an LIS + disp.
2249 Disp = DAG.getTargetConstant((short)Addr, dl, MVT::i32);
2250
2251 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, dl,
2252 MVT::i32);
2253 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
2254 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0);
2255 return true;
2256 }
2257 }
2258
2259 Disp = DAG.getTargetConstant(0, dl, getPointerTy(DAG.getDataLayout()));
2260 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) {
2261 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
2262 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
2263 } else
2264 Base = N;
2265 return true; // [r+0]
2266}
2267
2268/// SelectAddressRegRegOnly - Given the specified addressed, force it to be
2269/// represented as an indexed [r+r] operation.
2270bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
2271 SDValue &Index,
2272 SelectionDAG &DAG) const {
2273 // Check to see if we can easily represent this as an [r+r] address. This
2274 // will fail if it thinks that the address is more profitably represented as
2275 // reg+imm, e.g. where imm = 0.
2276 if (SelectAddressRegReg(N, Base, Index, DAG))
2277 return true;
2278
2279 // If the address is the result of an add, we will utilize the fact that the
2280 // address calculation includes an implicit add. However, we can reduce
2281 // register pressure if we do not materialize a constant just for use as the
2282 // index register. We only get rid of the add if it is not an add of a
2283 // value and a 16-bit signed constant and both have a single use.
2284 int16_t imm = 0;
2285 if (N.getOpcode() == ISD::ADD &&
2286 (!isIntS16Immediate(N.getOperand(1), imm) ||
2287 !N.getOperand(1).hasOneUse() || !N.getOperand(0).hasOneUse())) {
2288 Base = N.getOperand(0);
2289 Index = N.getOperand(1);
2290 return true;
2291 }
2292
2293 // Otherwise, do it the hard way, using R0 as the base register.
2294 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
2295 N.getValueType());
2296 Index = N;
2297 return true;
2298}
2299
2300/// getPreIndexedAddressParts - returns true by value, base pointer and
2301/// offset pointer and addressing mode by reference if the node's address
2302/// can be legally represented as pre-indexed load / store address.
2303bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
2304 SDValue &Offset,
2305 ISD::MemIndexedMode &AM,
2306 SelectionDAG &DAG) const {
2307 if (DisablePPCPreinc) return false;
2308
2309 bool isLoad = true;
2310 SDValue Ptr;
2311 EVT VT;
2312 unsigned Alignment;
2313 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
2314 Ptr = LD->getBasePtr();
2315 VT = LD->getMemoryVT();
2316 Alignment = LD->getAlignment();
2317 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
2318 Ptr = ST->getBasePtr();
2319 VT = ST->getMemoryVT();
2320 Alignment = ST->getAlignment();
2321 isLoad = false;
2322 } else
2323 return false;
2324
2325 // PowerPC doesn't have preinc load/store instructions for vectors (except
2326 // for QPX, which does have preinc r+r forms).
2327 if (VT.isVector()) {
2328 if (!Subtarget.hasQPX() || (VT != MVT::v4f64 && VT != MVT::v4f32)) {
2329 return false;
2330 } else if (SelectAddressRegRegOnly(Ptr, Offset, Base, DAG)) {
2331 AM = ISD::PRE_INC;
2332 return true;
2333 }
2334 }
2335
2336 if (SelectAddressRegReg(Ptr, Base, Offset, DAG)) {
2337 // Common code will reject creating a pre-inc form if the base pointer
2338 // is a frame index, or if N is a store and the base pointer is either
2339 // the same as or a predecessor of the value being stored. Check for
2340 // those situations here, and try with swapped Base/Offset instead.
2341 bool Swap = false;
2342
2343 if (isa<FrameIndexSDNode>(Base) || isa<RegisterSDNode>(Base))
2344 Swap = true;
2345 else if (!isLoad) {
2346 SDValue Val = cast<StoreSDNode>(N)->getValue();
2347 if (Val == Base || Base.getNode()->isPredecessorOf(Val.getNode()))
2348 Swap = true;
2349 }
2350
2351 if (Swap)
2352 std::swap(Base, Offset);
2353
2354 AM = ISD::PRE_INC;
2355 return true;
2356 }
2357
2358 // LDU/STU can only handle immediates that are a multiple of 4.
2359 if (VT != MVT::i64) {
2360 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, 0))
2361 return false;
2362 } else {
2363 // LDU/STU need an address with at least 4-byte alignment.
2364 if (Alignment < 4)
2365 return false;
2366
2367 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, 4))
2368 return false;
2369 }
2370
2371 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
2372 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
2373 // sext i32 to i64 when addr mode is r+i.
2374 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
2375 LD->getExtensionType() == ISD::SEXTLOAD &&
2376 isa<ConstantSDNode>(Offset))
2377 return false;
2378 }
2379
2380 AM = ISD::PRE_INC;
2381 return true;
2382}
2383
2384//===----------------------------------------------------------------------===//
2385// LowerOperation implementation
2386//===----------------------------------------------------------------------===//
2387
2388/// Return true if we should reference labels using a PICBase, set the HiOpFlags
2389/// and LoOpFlags to the target MO flags.
2390static void getLabelAccessInfo(bool IsPIC, const PPCSubtarget &Subtarget,
2391 unsigned &HiOpFlags, unsigned &LoOpFlags,
2392 const GlobalValue *GV = nullptr) {
2393 HiOpFlags = PPCII::MO_HA;
2394 LoOpFlags = PPCII::MO_LO;
2395
2396 // Don't use the pic base if not in PIC relocation model.
2397 if (IsPIC) {
2398 HiOpFlags |= PPCII::MO_PIC_FLAG;
2399 LoOpFlags |= PPCII::MO_PIC_FLAG;
2400 }
2401
2402 // If this is a reference to a global value that requires a non-lazy-ptr, make
2403 // sure that instruction lowering adds it.
2404 if (GV && Subtarget.hasLazyResolverStub(GV)) {
2405 HiOpFlags |= PPCII::MO_NLP_FLAG;
2406 LoOpFlags |= PPCII::MO_NLP_FLAG;
2407
2408 if (GV->hasHiddenVisibility()) {
2409 HiOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
2410 LoOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
2411 }
2412 }
2413}
2414
2415static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC,
2416 SelectionDAG &DAG) {
2417 SDLoc DL(HiPart);
2418 EVT PtrVT = HiPart.getValueType();
2419 SDValue Zero = DAG.getConstant(0, DL, PtrVT);
2420
2421 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero);
2422 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, LoPart, Zero);
2423
2424 // With PIC, the first instruction is actually "GR+hi(&G)".
2425 if (isPIC)
2426 Hi = DAG.getNode(ISD::ADD, DL, PtrVT,
2427 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT), Hi);
2428
2429 // Generate non-pic code that has direct accesses to the constant pool.
2430 // The address of the global is just (hi(&g)+lo(&g)).
2431 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
2432}
2433
2434static void setUsesTOCBasePtr(MachineFunction &MF) {
2435 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2436 FuncInfo->setUsesTOCBasePtr();
2437}
2438
2439static void setUsesTOCBasePtr(SelectionDAG &DAG) {
2440 setUsesTOCBasePtr(DAG.getMachineFunction());
2441}
2442
2443static SDValue getTOCEntry(SelectionDAG &DAG, const SDLoc &dl, bool Is64Bit,
2444 SDValue GA) {
2445 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
2446 SDValue Reg = Is64Bit ? DAG.getRegister(PPC::X2, VT) :
2447 DAG.getNode(PPCISD::GlobalBaseReg, dl, VT);
2448
2449 SDValue Ops[] = { GA, Reg };
2450 return DAG.getMemIntrinsicNode(
2451 PPCISD::TOC_ENTRY, dl, DAG.getVTList(VT, MVT::Other), Ops, VT,
2452 MachinePointerInfo::getGOT(DAG.getMachineFunction()), 0,
2453 MachineMemOperand::MOLoad);
2454}
2455
2456SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
2457 SelectionDAG &DAG) const {
2458 EVT PtrVT = Op.getValueType();
2459 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
2460 const Constant *C = CP->getConstVal();
2461
2462 // 64-bit SVR4 ABI code is always position-independent.
2463 // The actual address of the GlobalValue is stored in the TOC.
2464 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
2465 setUsesTOCBasePtr(DAG);
2466 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0);
2467 return getTOCEntry(DAG, SDLoc(CP), true, GA);
2468 }
2469
2470 unsigned MOHiFlag, MOLoFlag;
2471 bool IsPIC = isPositionIndependent();
2472 getLabelAccessInfo(IsPIC, Subtarget, MOHiFlag, MOLoFlag);
2473
2474 if (IsPIC && Subtarget.isSVR4ABI()) {
2475 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(),
2476 PPCII::MO_PIC_FLAG);
2477 return getTOCEntry(DAG, SDLoc(CP), false, GA);
2478 }
2479
2480 SDValue CPIHi =
2481 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOHiFlag);
2482 SDValue CPILo =
2483 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOLoFlag);
2484 return LowerLabelRef(CPIHi, CPILo, IsPIC, DAG);
2485}
2486
2487// For 64-bit PowerPC, prefer the more compact relative encodings.
2488// This trades 32 bits per jump table entry for one or two instructions
2489// on the jump site.
2490unsigned PPCTargetLowering::getJumpTableEncoding() const {
2491 if (isJumpTableRelative())
2492 return MachineJumpTableInfo::EK_LabelDifference32;
2493
2494 return TargetLowering::getJumpTableEncoding();
2495}
2496
2497bool PPCTargetLowering::isJumpTableRelative() const {
2498 if (Subtarget.isPPC64())
2499 return true;
2500 return TargetLowering::isJumpTableRelative();
2501}
2502
2503SDValue PPCTargetLowering::getPICJumpTableRelocBase(SDValue Table,
2504 SelectionDAG &DAG) const {
2505 if (!Subtarget.isPPC64())
2506 return TargetLowering::getPICJumpTableRelocBase(Table, DAG);
2507
2508 switch (getTargetMachine().getCodeModel()) {
2509 case CodeModel::Small:
2510 case CodeModel::Medium:
2511 return TargetLowering::getPICJumpTableRelocBase(Table, DAG);
2512 default:
2513 return DAG.getNode(PPCISD::GlobalBaseReg, SDLoc(),
2514 getPointerTy(DAG.getDataLayout()));
2515 }
2516}
2517
2518const MCExpr *
2519PPCTargetLowering::getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
2520 unsigned JTI,
2521 MCContext &Ctx) const {
2522 if (!Subtarget.isPPC64())
2523 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
2524
2525 switch (getTargetMachine().getCodeModel()) {
2526 case CodeModel::Small:
2527 case CodeModel::Medium:
2528 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
2529 default:
2530 return MCSymbolRefExpr::create(MF->getPICBaseSymbol(), Ctx);
2531 }
2532}
2533
2534SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
2535 EVT PtrVT = Op.getValueType();
2536 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
2537
2538 // 64-bit SVR4 ABI code is always position-independent.
2539 // The actual address of the GlobalValue is stored in the TOC.
2540 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
2541 setUsesTOCBasePtr(DAG);
2542 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
2543 return getTOCEntry(DAG, SDLoc(JT), true, GA);
2544 }
2545
2546 unsigned MOHiFlag, MOLoFlag;
2547 bool IsPIC = isPositionIndependent();
2548 getLabelAccessInfo(IsPIC, Subtarget, MOHiFlag, MOLoFlag);
2549
2550 if (IsPIC && Subtarget.isSVR4ABI()) {
2551 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
2552 PPCII::MO_PIC_FLAG);
2553 return getTOCEntry(DAG, SDLoc(GA), false, GA);
2554 }
2555
2556 SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag);
2557 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag);
2558 return LowerLabelRef(JTIHi, JTILo, IsPIC, DAG);
2559}
2560
2561SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op,
2562 SelectionDAG &DAG) const {
2563 EVT PtrVT = Op.getValueType();
2564 BlockAddressSDNode *BASDN = cast<BlockAddressSDNode>(Op);
2565 const BlockAddress *BA = BASDN->getBlockAddress();
2566
2567 // 64-bit SVR4 ABI code is always position-independent.
2568 // The actual BlockAddress is stored in the TOC.
2569 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
2570 setUsesTOCBasePtr(DAG);
2571 SDValue GA = DAG.getTargetBlockAddress(BA, PtrVT, BASDN->getOffset());
2572 return getTOCEntry(DAG, SDLoc(BASDN), true, GA);
2573 }
2574
2575 unsigned MOHiFlag, MOLoFlag;
2576 bool IsPIC = isPositionIndependent();
2577 getLabelAccessInfo(IsPIC, Subtarget, MOHiFlag, MOLoFlag);
2578 SDValue TgtBAHi = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOHiFlag);
2579 SDValue TgtBALo = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOLoFlag);
2580 return LowerLabelRef(TgtBAHi, TgtBALo, IsPIC, DAG);
2581}
2582
2583SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
2584 SelectionDAG &DAG) const {
2585 // FIXME: TLS addresses currently use medium model code sequences,
2586 // which is the most useful form. Eventually support for small and
2587 // large models could be added if users need it, at the cost of
2588 // additional complexity.
2589 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
2590 if (DAG.getTarget().useEmulatedTLS())
2591 return LowerToTLSEmulatedModel(GA, DAG);
2592
2593 SDLoc dl(GA);
2594 const GlobalValue *GV = GA->getGlobal();
2595 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2596 bool is64bit = Subtarget.isPPC64();
2597 const Module *M = DAG.getMachineFunction().getFunction().getParent();
2598 PICLevel::Level picLevel = M->getPICLevel();
2599
2600 TLSModel::Model Model = getTargetMachine().getTLSModel(GV);
2601
2602 if (Model == TLSModel::LocalExec) {
2603 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
2604 PPCII::MO_TPREL_HA);
2605 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
2606 PPCII::MO_TPREL_LO);
2607 SDValue TLSReg = is64bit ? DAG.getRegister(PPC::X13, MVT::i64)
2608 : DAG.getRegister(PPC::R2, MVT::i32);
2609
2610 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, TGAHi, TLSReg);
2611 return DAG.getNode(PPCISD::Lo, dl, PtrVT, TGALo, Hi);
2612 }
2613
2614 if (Model == TLSModel::InitialExec) {
2615 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
2616 SDValue TGATLS = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
2617 PPCII::MO_TLS);
2618 SDValue GOTPtr;
2619 if (is64bit) {
2620 setUsesTOCBasePtr(DAG);
2621 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
2622 GOTPtr = DAG.getNode(PPCISD::ADDIS_GOT_TPREL_HA, dl,
2623 PtrVT, GOTReg, TGA);
2624 } else
2625 GOTPtr = DAG.getNode(PPCISD::PPC32_GOT, dl, PtrVT);
2626 SDValue TPOffset = DAG.getNode(PPCISD::LD_GOT_TPREL_L, dl,
2627 PtrVT, TGA, GOTPtr);
2628 return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TPOffset, TGATLS);
2629 }
2630
2631 if (Model == TLSModel::GeneralDynamic) {
2632 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
2633 SDValue GOTPtr;
2634 if (is64bit) {
2635 setUsesTOCBasePtr(DAG);
2636 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
2637 GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSGD_HA, dl, PtrVT,
2638 GOTReg, TGA);
2639 } else {
2640 if (picLevel == PICLevel::SmallPIC)
2641 GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT);
2642 else
2643 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
2644 }
2645 return DAG.getNode(PPCISD::ADDI_TLSGD_L_ADDR, dl, PtrVT,
2646 GOTPtr, TGA, TGA);
2647 }
2648
2649 if (Model == TLSModel::LocalDynamic) {
2650 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
2651 SDValue GOTPtr;
2652 if (is64bit) {
2653 setUsesTOCBasePtr(DAG);
2654 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
2655 GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSLD_HA, dl, PtrVT,
2656 GOTReg, TGA);
2657 } else {
2658 if (picLevel == PICLevel::SmallPIC)
2659 GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT);
2660 else
2661 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
2662 }
2663 SDValue TLSAddr = DAG.getNode(PPCISD::ADDI_TLSLD_L_ADDR, dl,
2664 PtrVT, GOTPtr, TGA, TGA);
2665 SDValue DtvOffsetHi = DAG.getNode(PPCISD::ADDIS_DTPREL_HA, dl,
2666 PtrVT, TLSAddr, TGA);
2667 return DAG.getNode(PPCISD::ADDI_DTPREL_L, dl, PtrVT, DtvOffsetHi, TGA);
2668 }
2669
2670 llvm_unreachable("Unknown TLS model!")::llvm::llvm_unreachable_internal("Unknown TLS model!", "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2670)
;
2671}
2672
2673SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
2674 SelectionDAG &DAG) const {
2675 EVT PtrVT = Op.getValueType();
2676 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
2677 SDLoc DL(GSDN);
2678 const GlobalValue *GV = GSDN->getGlobal();
2679
2680 // 64-bit SVR4 ABI code is always position-independent.
2681 // The actual address of the GlobalValue is stored in the TOC.
2682 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
2683 setUsesTOCBasePtr(DAG);
2684 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset());
2685 return getTOCEntry(DAG, DL, true, GA);
2686 }
2687
2688 unsigned MOHiFlag, MOLoFlag;
2689 bool IsPIC = isPositionIndependent();
2690 getLabelAccessInfo(IsPIC, Subtarget, MOHiFlag, MOLoFlag, GV);
2691
2692 if (IsPIC && Subtarget.isSVR4ABI()) {
2693 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT,
2694 GSDN->getOffset(),
2695 PPCII::MO_PIC_FLAG);
2696 return getTOCEntry(DAG, DL, false, GA);
2697 }
2698
2699 SDValue GAHi =
2700 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag);
2701 SDValue GALo =
2702 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag);
2703
2704 SDValue Ptr = LowerLabelRef(GAHi, GALo, IsPIC, DAG);
2705
2706 // If the global reference is actually to a non-lazy-pointer, we have to do an
2707 // extra load to get the address of the global.
2708 if (MOHiFlag & PPCII::MO_NLP_FLAG)
2709 Ptr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo());
2710 return Ptr;
2711}
2712
2713SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
2714 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
2715 SDLoc dl(Op);
2716
2717 if (Op.getValueType() == MVT::v2i64) {
2718 // When the operands themselves are v2i64 values, we need to do something
2719 // special because VSX has no underlying comparison operations for these.
2720 if (Op.getOperand(0).getValueType() == MVT::v2i64) {
2721 // Equality can be handled by casting to the legal type for Altivec
2722 // comparisons, everything else needs to be expanded.
2723 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
2724 return DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
2725 DAG.getSetCC(dl, MVT::v4i32,
2726 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0)),
2727 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(1)),
2728 CC));
2729 }
2730
2731 return SDValue();
2732 }
2733
2734 // We handle most of these in the usual way.
2735 return Op;
2736 }
2737
2738 // If we're comparing for equality to zero, expose the fact that this is
2739 // implemented as a ctlz/srl pair on ppc, so that the dag combiner can
2740 // fold the new nodes.
2741 if (SDValue V = lowerCmpEqZeroToCtlzSrl(Op, DAG))
2742 return V;
2743
2744 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
2745 // Leave comparisons against 0 and -1 alone for now, since they're usually
2746 // optimized. FIXME: revisit this when we can custom lower all setcc
2747 // optimizations.
2748 if (C->isAllOnesValue() || C->isNullValue())
2749 return SDValue();
2750 }
2751
2752 // If we have an integer seteq/setne, turn it into a compare against zero
2753 // by xor'ing the rhs with the lhs, which is faster than setting a
2754 // condition register, reading it back out, and masking the correct bit. The
2755 // normal approach here uses sub to do this instead of xor. Using xor exposes
2756 // the result to other bit-twiddling opportunities.
2757 EVT LHSVT = Op.getOperand(0).getValueType();
2758 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
2759 EVT VT = Op.getValueType();
2760 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0),
2761 Op.getOperand(1));
2762 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, dl, LHSVT), CC);
2763 }
2764 return SDValue();
2765}
2766
2767SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
2768 SDNode *Node = Op.getNode();
2769 EVT VT = Node->getValueType(0);
2770 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2771 SDValue InChain = Node->getOperand(0);
2772 SDValue VAListPtr = Node->getOperand(1);
2773 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
2774 SDLoc dl(Node);
2775
2776 assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only")(static_cast <bool> (!Subtarget.isPPC64() && "LowerVAARG is PPC32 only"
) ? void (0) : __assert_fail ("!Subtarget.isPPC64() && \"LowerVAARG is PPC32 only\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2776, __extension__ __PRETTY_FUNCTION__))
;
2777
2778 // gpr_index
2779 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
2780 VAListPtr, MachinePointerInfo(SV), MVT::i8);
2781 InChain = GprIndex.getValue(1);
2782
2783 if (VT == MVT::i64) {
2784 // Check if GprIndex is even
2785 SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex,
2786 DAG.getConstant(1, dl, MVT::i32));
2787 SDValue CC64 = DAG.getSetCC(dl, MVT::i32, GprAnd,
2788 DAG.getConstant(0, dl, MVT::i32), ISD::SETNE);
2789 SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex,
2790 DAG.getConstant(1, dl, MVT::i32));
2791 // Align GprIndex to be even if it isn't
2792 GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne,
2793 GprIndex);
2794 }
2795
2796 // fpr index is 1 byte after gpr
2797 SDValue FprPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
2798 DAG.getConstant(1, dl, MVT::i32));
2799
2800 // fpr
2801 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
2802 FprPtr, MachinePointerInfo(SV), MVT::i8);
2803 InChain = FprIndex.getValue(1);
2804
2805 SDValue RegSaveAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
2806 DAG.getConstant(8, dl, MVT::i32));
2807
2808 SDValue OverflowAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
2809 DAG.getConstant(4, dl, MVT::i32));
2810
2811 // areas
2812 SDValue OverflowArea =
2813 DAG.getLoad(MVT::i32, dl, InChain, OverflowAreaPtr, MachinePointerInfo());
2814 InChain = OverflowArea.getValue(1);
2815
2816 SDValue RegSaveArea =
2817 DAG.getLoad(MVT::i32, dl, InChain, RegSaveAreaPtr, MachinePointerInfo());
2818 InChain = RegSaveArea.getValue(1);
2819
2820 // select overflow_area if index > 8
2821 SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex,
2822 DAG.getConstant(8, dl, MVT::i32), ISD::SETLT);
2823
2824 // adjustment constant gpr_index * 4/8
2825 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32,
2826 VT.isInteger() ? GprIndex : FprIndex,
2827 DAG.getConstant(VT.isInteger() ? 4 : 8, dl,
2828 MVT::i32));
2829
2830 // OurReg = RegSaveArea + RegConstant
2831 SDValue OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, RegSaveArea,
2832 RegConstant);
2833
2834 // Floating types are 32 bytes into RegSaveArea
2835 if (VT.isFloatingPoint())
2836 OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, OurReg,
2837 DAG.getConstant(32, dl, MVT::i32));
2838
2839 // increase {f,g}pr_index by 1 (or 2 if VT is i64)
2840 SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32,
2841 VT.isInteger() ? GprIndex : FprIndex,
2842 DAG.getConstant(VT == MVT::i64 ? 2 : 1, dl,
2843 MVT::i32));
2844
2845 InChain = DAG.getTruncStore(InChain, dl, IndexPlus1,
2846 VT.isInteger() ? VAListPtr : FprPtr,
2847 MachinePointerInfo(SV), MVT::i8);
2848
2849 // determine if we should load from reg_save_area or overflow_area
2850 SDValue Result = DAG.getNode(ISD::SELECT, dl, PtrVT, CC, OurReg, OverflowArea);
2851
2852 // increase overflow_area by 4/8 if gpr/fpr > 8
2853 SDValue OverflowAreaPlusN = DAG.getNode(ISD::ADD, dl, PtrVT, OverflowArea,
2854 DAG.getConstant(VT.isInteger() ? 4 : 8,
2855 dl, MVT::i32));
2856
2857 OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea,
2858 OverflowAreaPlusN);
2859
2860 InChain = DAG.getTruncStore(InChain, dl, OverflowArea, OverflowAreaPtr,
2861 MachinePointerInfo(), MVT::i32);
2862
2863 return DAG.getLoad(VT, dl, InChain, Result, MachinePointerInfo());
2864}
2865
2866SDValue PPCTargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const {
2867 assert(!Subtarget.isPPC64() && "LowerVACOPY is PPC32 only")(static_cast <bool> (!Subtarget.isPPC64() && "LowerVACOPY is PPC32 only"
) ? void (0) : __assert_fail ("!Subtarget.isPPC64() && \"LowerVACOPY is PPC32 only\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2867, __extension__ __PRETTY_FUNCTION__))
;
2868
2869 // We have to copy the entire va_list struct:
2870 // 2*sizeof(char) + 2 Byte alignment + 2*sizeof(char*) = 12 Byte
2871 return DAG.getMemcpy(Op.getOperand(0), Op,
2872 Op.getOperand(1), Op.getOperand(2),
2873 DAG.getConstant(12, SDLoc(Op), MVT::i32), 8, false, true,
2874 false, MachinePointerInfo(), MachinePointerInfo());
2875}
2876
2877SDValue PPCTargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
2878 SelectionDAG &DAG) const {
2879 return Op.getOperand(0);
2880}
2881
2882SDValue PPCTargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
2883 SelectionDAG &DAG) const {
2884 SDValue Chain = Op.getOperand(0);
2885 SDValue Trmp = Op.getOperand(1); // trampoline
2886 SDValue FPtr = Op.getOperand(2); // nested function
2887 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
2888 SDLoc dl(Op);
2889
2890 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2891 bool isPPC64 = (PtrVT == MVT::i64);
2892 Type *IntPtrTy = DAG.getDataLayout().getIntPtrType(*DAG.getContext());
2893
2894 TargetLowering::ArgListTy Args;
2895 TargetLowering::ArgListEntry Entry;
2896
2897 Entry.Ty = IntPtrTy;
2898 Entry.Node = Trmp; Args.push_back(Entry);
2899
2900 // TrampSize == (isPPC64 ? 48 : 40);
2901 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40, dl,
2902 isPPC64 ? MVT::i64 : MVT::i32);
2903 Args.push_back(Entry);
2904
2905 Entry.Node = FPtr; Args.push_back(Entry);
2906 Entry.Node = Nest; Args.push_back(Entry);
2907
2908 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
2909 TargetLowering::CallLoweringInfo CLI(DAG);
2910 CLI.setDebugLoc(dl).setChain(Chain).setLibCallee(
2911 CallingConv::C, Type::getVoidTy(*DAG.getContext()),
2912 DAG.getExternalSymbol("__trampoline_setup", PtrVT), std::move(Args));
2913
2914 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
2915 return CallResult.second;
2916}
2917
2918SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
2919 MachineFunction &MF = DAG.getMachineFunction();
2920 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2921 EVT PtrVT = getPointerTy(MF.getDataLayout());
2922
2923 SDLoc dl(Op);
2924
2925 if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) {
2926 // vastart just stores the address of the VarArgsFrameIndex slot into the
2927 // memory location argument.
2928 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2929 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2930 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
2931 MachinePointerInfo(SV));
2932 }
2933
2934 // For the 32-bit SVR4 ABI we follow the layout of the va_list struct.
2935 // We suppose the given va_list is already allocated.
2936 //
2937 // typedef struct {
2938 // char gpr; /* index into the array of 8 GPRs
2939 // * stored in the register save area
2940 // * gpr=0 corresponds to r3,
2941 // * gpr=1 to r4, etc.
2942 // */
2943 // char fpr; /* index into the array of 8 FPRs
2944 // * stored in the register save area
2945 // * fpr=0 corresponds to f1,
2946 // * fpr=1 to f2, etc.
2947 // */
2948 // char *overflow_arg_area;
2949 // /* location on stack that holds
2950 // * the next overflow argument
2951 // */
2952 // char *reg_save_area;
2953 // /* where r3:r10 and f1:f8 (if saved)
2954 // * are stored
2955 // */
2956 // } va_list[1];
2957
2958 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), dl, MVT::i32);
2959 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), dl, MVT::i32);
2960 SDValue StackOffsetFI = DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(),
2961 PtrVT);
2962 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
2963 PtrVT);
2964
2965 uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
2966 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, dl, PtrVT);
2967
2968 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
2969 SDValue ConstStackOffset = DAG.getConstant(StackOffset, dl, PtrVT);
2970
2971 uint64_t FPROffset = 1;
2972 SDValue ConstFPROffset = DAG.getConstant(FPROffset, dl, PtrVT);
2973
2974 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2975
2976 // Store first byte : number of int regs
2977 SDValue firstStore =
2978 DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR, Op.getOperand(1),
2979 MachinePointerInfo(SV), MVT::i8);
2980 uint64_t nextOffset = FPROffset;
2981 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
2982 ConstFPROffset);
2983
2984 // Store second byte : number of float regs
2985 SDValue secondStore =
2986 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr,
2987 MachinePointerInfo(SV, nextOffset), MVT::i8);
2988 nextOffset += StackOffset;
2989 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
2990
2991 // Store second word : arguments given on stack
2992 SDValue thirdStore = DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr,
2993 MachinePointerInfo(SV, nextOffset));
2994 nextOffset += FrameOffset;
2995 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
2996
2997 // Store third word : arguments given in registers
2998 return DAG.getStore(thirdStore, dl, FR, nextPtr,
2999 MachinePointerInfo(SV, nextOffset));
3000}
3001
3002#include "PPCGenCallingConv.inc"
3003
3004// Function whose sole purpose is to kill compiler warnings
3005// stemming from unused functions included from PPCGenCallingConv.inc.
3006CCAssignFn *PPCTargetLowering::useFastISelCCs(unsigned Flag) const {
3007 return Flag ? CC_PPC64_ELF_FIS : RetCC_PPC64_ELF_FIS;
3008}
3009
3010bool llvm::CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
3011 CCValAssign::LocInfo &LocInfo,
3012 ISD::ArgFlagsTy &ArgFlags,
3013 CCState &State) {
3014 return true;
3015}
3016
3017bool llvm::CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
3018 MVT &LocVT,
3019 CCValAssign::LocInfo &LocInfo,
3020 ISD::ArgFlagsTy &ArgFlags,
3021 CCState &State) {
3022 static const MCPhysReg ArgRegs[] = {
3023 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
3024 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
3025 };
3026 const unsigned NumArgRegs = array_lengthof(ArgRegs);
3027
3028 unsigned RegNum = State.getFirstUnallocated(ArgRegs);
3029
3030 // Skip one register if the first unallocated register has an even register
3031 // number and there are still argument registers available which have not been
3032 // allocated yet. RegNum is actually an index into ArgRegs, which means we
3033 // need to skip a register if RegNum is odd.
3034 if (RegNum != NumArgRegs && RegNum % 2 == 1) {
3035 State.AllocateReg(ArgRegs[RegNum]);
3036 }
3037
3038 // Always return false here, as this function only makes sure that the first
3039 // unallocated register has an odd register number and does not actually
3040 // allocate a register for the current argument.
3041 return false;
3042}
3043
3044bool
3045llvm::CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128(unsigned &ValNo, MVT &ValVT,
3046 MVT &LocVT,
3047 CCValAssign::LocInfo &LocInfo,
3048 ISD::ArgFlagsTy &ArgFlags,
3049 CCState &State) {
3050 static const MCPhysReg ArgRegs[] = {
3051 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
3052 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
3053 };
3054 const unsigned NumArgRegs = array_lengthof(ArgRegs);
3055
3056 unsigned RegNum = State.getFirstUnallocated(ArgRegs);
3057 int RegsLeft = NumArgRegs - RegNum;
3058
3059 // Skip if there is not enough registers left for long double type (4 gpr regs
3060 // in soft float mode) and put long double argument on the stack.
3061 if (RegNum != NumArgRegs && RegsLeft < 4) {
3062 for (int i = 0; i < RegsLeft; i++) {
3063 State.AllocateReg(ArgRegs[RegNum + i]);
3064 }
3065 }
3066
3067 return false;
3068}
3069
3070bool llvm::CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
3071 MVT &LocVT,
3072 CCValAssign::LocInfo &LocInfo,
3073 ISD::ArgFlagsTy &ArgFlags,
3074 CCState &State) {
3075 static const MCPhysReg ArgRegs[] = {
3076 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
3077 PPC::F8
3078 };
3079
3080 const unsigned NumArgRegs = array_lengthof(ArgRegs);
3081
3082 unsigned RegNum = State.getFirstUnallocated(ArgRegs);
3083
3084 // If there is only one Floating-point register left we need to put both f64
3085 // values of a split ppc_fp128 value on the stack.
3086 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) {
3087 State.AllocateReg(ArgRegs[RegNum]);
3088 }
3089
3090 // Always return false here, as this function only makes sure that the two f64
3091 // values a ppc_fp128 value is split into are both passed in registers or both
3092 // passed on the stack and does not actually allocate a register for the
3093 // current argument.
3094 return false;
3095}
3096
3097/// FPR - The set of FP registers that should be allocated for arguments,
3098/// on Darwin.
3099static const MCPhysReg FPR[] = {PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5,
3100 PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10,
3101 PPC::F11, PPC::F12, PPC::F13};
3102
3103/// QFPR - The set of QPX registers that should be allocated for arguments.
3104static const MCPhysReg QFPR[] = {
3105 PPC::QF1, PPC::QF2, PPC::QF3, PPC::QF4, PPC::QF5, PPC::QF6, PPC::QF7,
3106 PPC::QF8, PPC::QF9, PPC::QF10, PPC::QF11, PPC::QF12, PPC::QF13};
3107
3108/// CalculateStackSlotSize - Calculates the size reserved for this argument on
3109/// the stack.
3110static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags,
3111 unsigned PtrByteSize) {
3112 unsigned ArgSize = ArgVT.getStoreSize();
3113 if (Flags.isByVal())
3114 ArgSize = Flags.getByValSize();
3115
3116 // Round up to multiples of the pointer size, except for array members,
3117 // which are always packed.
3118 if (!Flags.isInConsecutiveRegs())
3119 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3120
3121 return ArgSize;
3122}
3123
3124/// CalculateStackSlotAlignment - Calculates the alignment of this argument
3125/// on the stack.
3126static unsigned CalculateStackSlotAlignment(EVT ArgVT, EVT OrigVT,
3127 ISD::ArgFlagsTy Flags,
3128 unsigned PtrByteSize) {
3129 unsigned Align = PtrByteSize;
3130
3131 // Altivec parameters are padded to a 16 byte boundary.
3132 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
3133 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
3134 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64 ||
3135 ArgVT == MVT::v1i128)
3136 Align = 16;
3137 // QPX vector types stored in double-precision are padded to a 32 byte
3138 // boundary.
3139 else if (ArgVT == MVT::v4f64 || ArgVT == MVT::v4i1)
3140 Align = 32;
3141
3142 // ByVal parameters are aligned as requested.
3143 if (Flags.isByVal()) {
3144 unsigned BVAlign = Flags.getByValAlign();
3145 if (BVAlign > PtrByteSize) {
3146 if (BVAlign % PtrByteSize != 0)
3147 llvm_unreachable(::llvm::llvm_unreachable_internal("ByVal alignment is not a multiple of the pointer size"
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/PowerPC/PPCISelLowering.cpp"
, 3148)
3148 "ByVal alignment is not a multiple of the pointer size")::llvm::llvm_unreachable_internal("ByVal alignment is not a multiple of the pointer size"
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/PowerPC/PPCISelLowering.cpp"
, 3148)
;
3149
3150 Align = BVAlign;
3151 }
3152 }
3153
3154 // Array members are always packed to their original alignment.
3155 if (Flags.isInConsecutiveRegs()) {
3156 // If the array member was split into multiple registers, the first
3157 // needs to be aligned to the size of the full type. (Except for
3158 // ppcf128, which is only aligned as its f64 components.)
3159 if (Flags.isSplit() && OrigVT != MVT::ppcf128)
3160 Align = OrigVT.getStoreSize();
3161 else
3162 Align = ArgVT.getStoreSize();
3163 }
3164
3165 return Align;
3166}
3167
3168/// CalculateStackSlotUsed - Return whether this argument will use its
3169/// stack slot (instead of being passed in registers). ArgOffset,
3170/// AvailableFPRs, and AvailableVRs must hold the current argument
3171/// position, and will be updated to account for this argument.
3172static bool CalculateStackSlotUsed(EVT ArgVT, EVT OrigVT,
3173 ISD::ArgFlagsTy Flags,
3174 unsigned PtrByteSize,
3175 unsigned LinkageSize,
3176 unsigned ParamAreaSize,
3177 unsigned &ArgOffset,
3178 unsigned &AvailableFPRs,
3179 unsigned &AvailableVRs, bool HasQPX) {
3180 bool UseMemory = false;
3181
3182 // Respect alignment of argument on the stack.
3183 unsigned Align =
3184 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
3185 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
3186 // If there's no space left in the argument save area, we must
3187 // use memory (this check also catches zero-sized arguments).
3188 if (ArgOffset >= LinkageSize + ParamAreaSize)
3189 UseMemory = true;
3190
3191 // Allocate argument on the stack.
3192 ArgOffset += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
3193 if (Flags.isInConsecutiveRegsLast())
3194 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3195 // If we overran the argument save area, we must use memory
3196 // (this check catches arguments passed partially in memory)
3197 if (ArgOffset > LinkageSize + ParamAreaSize)
3198 UseMemory = true;
3199
3200 // However, if the argument is actually passed in an FPR or a VR,
3201 // we don't use memory after all.
3202 if (!Flags.isByVal()) {
3203 if (ArgVT == MVT::f32 || ArgVT == MVT::f64 ||
3204 // QPX registers overlap with the scalar FP registers.
3205 (HasQPX && (ArgVT == MVT::v4f32 ||
3206 ArgVT == MVT::v4f64 ||
3207 ArgVT == MVT::v4i1)))
3208 if (AvailableFPRs > 0) {
3209 --AvailableFPRs;
3210 return false;
3211 }
3212 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
3213 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
3214 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64 ||
3215 ArgVT == MVT::v1i128)
3216 if (AvailableVRs > 0) {
3217 --AvailableVRs;
3218 return false;
3219 }
3220 }
3221
3222 return UseMemory;
3223}
3224
3225/// EnsureStackAlignment - Round stack frame size up from NumBytes to
3226/// ensure minimum alignment required for target.
3227static unsigned EnsureStackAlignment(const PPCFrameLowering *Lowering,
3228 unsigned NumBytes) {
3229 unsigned TargetAlign = Lowering->getStackAlignment();
3230 unsigned AlignMask = TargetAlign - 1;
3231 NumBytes = (NumBytes + AlignMask) & ~AlignMask;
3232 return NumBytes;
3233}
3234
3235SDValue PPCTargetLowering::LowerFormalArguments(
3236 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
3237 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
3238 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
3239 if (Subtarget.isSVR4ABI()) {
3240 if (Subtarget.isPPC64())
3241 return LowerFormalArguments_64SVR4(Chain, CallConv, isVarArg, Ins,
3242 dl, DAG, InVals);
3243 else
3244 return LowerFormalArguments_32SVR4(Chain, CallConv, isVarArg, Ins,
3245 dl, DAG, InVals);
3246 } else {
3247 return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins,
3248 dl, DAG, InVals);
3249 }
3250}
3251
3252SDValue PPCTargetLowering::LowerFormalArguments_32SVR4(
3253 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
3254 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
3255 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
3256
3257 // 32-bit SVR4 ABI Stack Frame Layout:
3258 // +-----------------------------------+
3259 // +--> | Back chain |
3260 // | +-----------------------------------+
3261 // | | Floating-point register save area |
3262 // | +-----------------------------------+
3263 // | | General register save area |
3264 // | +-----------------------------------+
3265 // | | CR save word |
3266 // | +-----------------------------------+
3267 // | | VRSAVE save word |
3268 // | +-----------------------------------+
3269 // | | Alignment padding |
3270 // | +-----------------------------------+
3271 // | | Vector register save area |
3272 // | +-----------------------------------+
3273 // | | Local variable space |
3274 // | +-----------------------------------+
3275 // | | Parameter list area |
3276 // | +-----------------------------------+
3277 // | | LR save word |
3278 // | +-----------------------------------+
3279 // SP--> +--- | Back chain |
3280 // +-----------------------------------+
3281 //
3282 // Specifications:
3283 // System V Application Binary Interface PowerPC Processor Supplement
3284 // AltiVec Technology Programming Interface Manual
3285
3286 MachineFunction &MF = DAG.getMachineFunction();
3287 MachineFrameInfo &MFI = MF.getFrameInfo();
3288 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
3289
3290 EVT PtrVT = getPointerTy(MF.getDataLayout());
3291 // Potential tail calls could cause overwriting of argument stack slots.
3292 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
3293 (CallConv == CallingConv::Fast));
3294 unsigned PtrByteSize = 4;
3295
3296 // Assign locations to all of the incoming arguments.
3297 SmallVector<CCValAssign, 16> ArgLocs;
3298 PPCCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
3299 *DAG.getContext());
3300
3301 // Reserve space for the linkage area on the stack.
3302 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
3303 CCInfo.AllocateStack(LinkageSize, PtrByteSize);
3304 if (useSoftFloat())
3305 CCInfo.PreAnalyzeFormalArguments(Ins);
3306
3307 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4);
3308 CCInfo.clearWasPPCF128();
3309
3310 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3311 CCValAssign &VA = ArgLocs[i];
3312
3313 // Arguments stored in registers.
3314 if (VA.isRegLoc()) {
3315 const TargetRegisterClass *RC;
3316 EVT ValVT = VA.getValVT();
3317
3318 switch (ValVT.getSimpleVT().SimpleTy) {
3319 default:
3320 llvm_unreachable("ValVT not supported by formal arguments Lowering")::llvm::llvm_unreachable_internal("ValVT not supported by formal arguments Lowering"
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/PowerPC/PPCISelLowering.cpp"
, 3320)
;
3321 case MVT::i1:
3322 case MVT::i32:
3323 RC = &PPC::GPRCRegClass;
3324 break;
3325 case MVT::f32:
3326 if (Subtarget.hasP8Vector())
3327 RC = &PPC::VSSRCRegClass;
3328 else
3329 RC = &PPC::F4RCRegClass;
3330 break;
3331 case MVT::f64:
3332 if (Subtarget.hasVSX())
3333 RC = &PPC::VSFRCRegClass;
3334 else
3335 RC = &PPC::F8RCRegClass;
3336 break;
3337 case MVT::v16i8:
3338 case MVT::v8i16:
3339 case MVT::v4i32:
3340 RC = &PPC::VRRCRegClass;
3341 break;
3342 case MVT::v4f32:
3343 RC = Subtarget.hasQPX() ? &PPC::QSRCRegClass : &PPC::VRRCRegClass;
3344 break;
3345 case MVT::v2f64:
3346 case MVT::v2i64:
3347 RC = &PPC::VRRCRegClass;
3348 break;
3349 case MVT::v4f64:
3350 RC = &PPC::QFRCRegClass;
3351 break;
3352 case MVT::v4i1:
3353 RC = &PPC::QBRCRegClass;
3354 break;
3355 }
3356
3357 // Transform the arguments stored in physical registers into virtual ones.
3358 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
3359 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg,
3360 ValVT == MVT::i1 ? MVT::i32 : ValVT);
3361
3362 if (ValVT == MVT::i1)
3363 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgValue);
3364
3365 InVals.push_back(ArgValue);
3366 } else {
3367 // Argument stored in memory.
3368 assert(VA.isMemLoc())(static_cast <bool> (VA.isMemLoc()) ? void (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/PowerPC/PPCISelLowering.cpp"
, 3368, __extension__ __PRETTY_FUNCTION__))
;
3369
3370 unsigned ArgSize = VA.getLocVT().getStoreSize();
3371 int FI = MFI.CreateFixedObject(ArgSize, VA.getLocMemOffset(),
3372 isImmutable);
3373
3374 // Create load nodes to retrieve arguments from the stack.
3375 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3376 InVals.push_back(
3377 DAG.getLoad(VA.getValVT(), dl, Chain, FIN, MachinePointerInfo()));
3378 }
3379 }
3380
3381 // Assign locations to all of the incoming aggregate by value arguments.
3382 // Aggregates passed by value are stored in the local variable space of the
3383 // caller's stack frame, right above the parameter list area.
3384 SmallVector<CCValAssign, 16> ByValArgLocs;
3385 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3386 ByValArgLocs, *DAG.getContext());
3387
3388 // Reserve stack space for the allocations in CCInfo.
3389 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
3390
3391 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4_ByVal);
3392
3393 // Area that is at least reserved in the caller of this function.
3394 unsigned MinReservedArea = CCByValInfo.getNextStackOffset();
3395 MinReservedArea = std::max(MinReservedArea, LinkageSize);
3396
3397 // Set the size that is at least reserved in caller of this function. Tail
3398 // call optimized function's reserved stack space needs to be aligned so that
3399 // taking the difference between two stack areas will result in an aligned
3400 // stack.
3401 MinReservedArea =
3402 EnsureStackAlignment(Subtarget.getFrameLowering(), MinReservedArea);
3403 FuncInfo->setMinReservedArea(MinReservedArea);
3404
3405 SmallVector<SDValue, 8> MemOps;
3406
3407 // If the function takes variable number of arguments, make a frame index for
3408 // the start of the first vararg value... for expansion of llvm.va_start.
3409 if (isVarArg) {
3410 static const MCPhysReg GPArgRegs[] = {
3411 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
3412 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
3413 };
3414 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
3415
3416 static const MCPhysReg FPArgRegs[] = {
3417 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
3418 PPC::F8
3419 };
3420 unsigned NumFPArgRegs = array_lengthof(FPArgRegs);
3421
3422 if (useSoftFloat())
3423 NumFPArgRegs = 0;
3424
3425 FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs));
3426 FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs));
3427
3428 // Make room for NumGPArgRegs and NumFPArgRegs.
3429 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 +
3430 NumFPArgRegs * MVT(MVT::f64).getSizeInBits()/8;
3431
3432 FuncInfo->setVarArgsStackOffset(
3433 MFI.CreateFixedObject(PtrVT.getSizeInBits()/8,
3434 CCInfo.getNextStackOffset(), true));
3435
3436 FuncInfo->setVarArgsFrameIndex(MFI.CreateStackObject(Depth, 8, false));
3437 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
3438
3439 // The fixed integer arguments of a variadic function are stored to the
3440 // VarArgsFrameIndex on the stack so that they may be loaded by
3441 // dereferencing the result of va_next.
3442 for (unsigned GPRIndex = 0; GPRIndex != NumGPArgRegs; ++GPRIndex) {
3443 // Get an existing live-in vreg, or add a new one.
3444 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]);
3445 if (!VReg)
3446 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
3447
3448 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3449 SDValue Store =
3450 DAG.getStore(Val.getValue(1), dl, Val, FIN, MachinePointerInfo());
3451 MemOps.push_back(Store);
3452 // Increment the address by four for the next argument to store
3453 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, dl, PtrVT);
3454 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
3455 }
3456
3457 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6
3458 // is set.
3459 // The double arguments are stored to the VarArgsFrameIndex
3460 // on the stack.
3461 for (unsigned FPRIndex = 0; FPRIndex != NumFPArgRegs; ++FPRIndex) {
3462 // Get an existing live-in vreg, or add a new one.
3463 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]);
3464 if (!VReg)
3465 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
3466
3467 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
3468 SDValue Store =
3469 DAG.getStore(Val.getValue(1), dl, Val, FIN, MachinePointerInfo());
3470 MemOps.push_back(Store);
3471 // Increment the address by eight for the next argument to store
3472 SDValue PtrOff = DAG.getConstant(MVT(MVT::f64).getSizeInBits()/8, dl,
3473 PtrVT);
3474 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
3475 }
3476 }
3477
3478 if (!MemOps.empty())
3479 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
3480
3481 return Chain;
3482}
3483
3484// PPC64 passes i8, i16, and i32 values in i64 registers. Promote
3485// value to MVT::i64 and then truncate to the correct register size.
3486SDValue PPCTargetLowering::extendArgForPPC64(ISD::ArgFlagsTy Flags,
3487 EVT ObjectVT, SelectionDAG &DAG,
3488 SDValue ArgVal,
3489 const SDLoc &dl) const {
3490 if (Flags.isSExt())
3491 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
3492 DAG.getValueType(ObjectVT));
3493 else if (Flags.isZExt())
3494 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
3495 DAG.getValueType(ObjectVT));
3496
3497 return DAG.getNode(ISD::TRUNCATE, dl, ObjectVT, ArgVal);
3498}
3499
3500SDValue PPCTargetLowering::LowerFormalArguments_64SVR4(
3501 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
3502 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
3503 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
3504 // TODO: add description of PPC stack frame format, or at least some docs.
3505 //
3506 bool isELFv2ABI = Subtarget.isELFv2ABI();
3507 bool isLittleEndian = Subtarget.isLittleEndian();
3508 MachineFunction &MF = DAG.getMachineFunction();
3509 MachineFrameInfo &MFI = MF.getFrameInfo();
3510 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
3511
3512 assert(!(CallConv == CallingConv::Fast && isVarArg) &&(static_cast <bool> (!(CallConv == CallingConv::Fast &&
isVarArg) && "fastcc not supported on varargs functions"
) ? void (0) : __assert_fail ("!(CallConv == CallingConv::Fast && isVarArg) && \"fastcc not supported on varargs functions\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/PowerPC/PPCISelLowering.cpp"
, 3513, __extension__ __PRETTY_FUNCTION__))
3513 "fastcc not supported on varargs functions")(static_cast <bool> (!(CallConv == CallingConv::Fast &&
isVarArg) && "fastcc not supported on varargs functions"
) ? void (0) : __assert_fail ("!(CallConv == CallingConv::Fast && isVarArg) && \"fastcc not supported on varargs functions\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/PowerPC/PPCISelLowering.cpp"
, 3513, __extension__ __PRETTY_FUNCTION__))
;
3514
3515 EVT PtrVT = getPointerTy(MF.getDataLayout());
3516 // Potential tail calls could cause overwriting of argument stack slots.
3517 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
3518 (CallConv == CallingConv::Fast));
3519 unsigned PtrByteSize = 8;
3520 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
3521
3522 static const MCPhysReg GPR[] = {
3523 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
3524 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
3525 };
3526 static const MCPhysReg VR[] = {
3527 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
3528 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
3529 };
3530
3531 const unsigned Num_GPR_Regs = array_lengthof(GPR);
3532 const unsigned Num_FPR_Regs = useSoftFloat() ? 0 : 13;
3533 const unsigned Num_VR_Regs = array_lengthof(VR);
3534 const unsigned Num_QFPR_Regs = Num_FPR_Regs;
3535
3536 // Do a first pass over the arguments to determine whether the ABI
3537 // guarantees that our caller has allocated the parameter save area
3538 // on its stack frame. In the ELFv1 ABI, this is always the case;
3539 // in the ELFv2 ABI, it is true if this is a vararg function or if
3540 // any parameter is located in a stack slot.
3541
3542 bool HasParameterArea = !isELFv2ABI || isVarArg;
3543 unsigned ParamAreaSize = Num_GPR_Regs * PtrByteSize;
3544 unsigned NumBytes = LinkageSize;
3545 unsigned AvailableFPRs = Num_FPR_Regs;
3546 unsigned AvailableVRs = Num_VR_Regs;
3547 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3548 if (Ins[i].Flags.isNest())
3549 continue;
3550
3551 if (CalculateStackSlotUsed(Ins[i].VT, Ins[i].ArgVT, Ins[i].Flags,
3552 PtrByteSize, LinkageSize, ParamAreaSize,
3553 NumBytes, AvailableFPRs, AvailableVRs,
3554 Subtarget.hasQPX()))
3555 HasParameterArea = true;
3556 }
3557
3558 // Add DAG nodes to load the arguments or copy them out of registers. On
3559 // entry to a function on PPC, the arguments start after the linkage area,
3560 // although the first ones are often in registers.
3561
3562 unsigned ArgOffset = LinkageSize;
3563 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
3564 unsigned &QFPR_idx = FPR_idx;
3565 SmallVector<SDValue, 8> MemOps;
3566 Function::const_arg_iterator FuncArg = MF.getFunction().arg_begin();
3567 unsigned CurArgIdx = 0;
3568 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
3569 SDValue ArgVal;
3570 bool needsLoad = false;
3571 EVT ObjectVT = Ins[ArgNo].VT;
3572 EVT OrigVT = Ins[ArgNo].ArgVT;
3573 unsigned ObjSize = ObjectVT.getStoreSize();
3574 unsigned ArgSize = ObjSize;
3575 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
3576 if (Ins[ArgNo].isOrigArg()) {
3577 std::advance(FuncArg, Ins[ArgNo].getOrigArgIndex() - CurArgIdx);
3578 CurArgIdx = Ins[ArgNo].getOrigArgIndex();
3579 }
3580 // We re-align the argument offset for each argument, except when using the
3581 // fast calling convention, when we need to make sure we do that only when
3582 // we'll actually use a stack slot.
3583 unsigned CurArgOffset, Align;
3584 auto ComputeArgOffset = [&]() {
3585 /* Respect alignment of argument on the stack. */
3586 Align = CalculateStackSlotAlignment(ObjectVT, OrigVT, Flags, PtrByteSize);
3587 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
3588 CurArgOffset = ArgOffset;
3589 };
3590
3591 if (CallConv != CallingConv::Fast) {
3592 ComputeArgOffset();
3593
3594 /* Compute GPR index associated with argument offset. */
3595 GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
3596 GPR_idx = std::min(GPR_idx, Num_GPR_Regs);
3597 }
3598
3599 // FIXME the codegen can be much improved in some cases.
3600 // We do not have to keep everything in memory.
3601 if (Flags.isByVal()) {
3602 assert(Ins[ArgNo].isOrigArg() && "Byval arguments cannot be implicit")(static_cast <bool> (Ins[ArgNo].isOrigArg() && "Byval arguments cannot be implicit"
) ? void (0) : __assert_fail ("Ins[ArgNo].isOrigArg() && \"Byval arguments cannot be implicit\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/PowerPC/PPCISelLowering.cpp"
, 3602, __extension__ __PRETTY_FUNCTION__))
;
3603
3604 if (CallConv == CallingConv::Fast)
3605 ComputeArgOffset();
3606
3607 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
3608 ObjSize = Flags.getByValSize();
3609 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3610 // Empty aggregate parameters do not take up registers. Examples:
3611 // struct { } a;
3612 // union { } b;
3613 // int c[0];
3614 // etc. However, we have to provide a place-holder in InVals, so
3615 // pretend we have an 8-byte item at the current address for that
3616 // purpose.
3617 if (!ObjSize) {
3618 int FI = MFI.CreateFixedObject(PtrByteSize, ArgOffset, true);
3619 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3620 InVals.push_back(FIN);
3621 continue;
3622 }
3623
3624 // Create a stack object covering all stack doublewords occupied
3625 // by the argument. If the argument is (fully or partially) on
3626 // the stack, or if the argument is fully in registers but the
3627 // caller has allocated the parameter save anyway, we can refer
3628 // directly to the caller's stack frame. Otherwise, create a
3629 // local copy in our own frame.
3630 int FI;
3631 if (HasParameterArea ||
3632 ArgSize + ArgOffset > LinkageSize + Num_GPR_Regs * PtrByteSize)
3633 FI = MFI.CreateFixedObject(ArgSize, ArgOffset, false, true);
3634 else
3635 FI = MFI.CreateStackObject(ArgSize, Align, false);
3636 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3637
3638 // Handle aggregates smaller than 8 bytes.
3639 if (ObjSize < PtrByteSize) {
3640 // The value of the object is its address, which differs from the
3641 // address of the enclosing doubleword on big-endian systems.
3642 SDValue Arg = FIN;
3643 if (!isLittleEndian) {
3644 SDValue ArgOff = DAG.getConstant(PtrByteSize - ObjSize, dl, PtrVT);
3645 Arg = DAG.getNode(ISD::ADD, dl, ArgOff.getValueType(), Arg, ArgOff);
3646 }
3647 InVals.push_back(Arg);
3648
3649 if (GPR_idx != Num_GPR_Regs) {
3650 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
3651 FuncInfo->addLiveInAttr(VReg, Flags);
3652 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3653 SDValue Store;
3654
3655 if (ObjSize==1 || ObjSize==2 || ObjSize==4) {
3656 EVT ObjType = (ObjSize == 1 ? MVT::i8 :
3657 (ObjSize == 2 ? MVT::i16 : MVT::i32));
3658 Store = DAG.getTruncStore(Val.getValue(1), dl, Val, Arg,
3659 MachinePointerInfo(&*FuncArg), ObjType);
3660 } else {
3661 // For sizes that don't fit a truncating store (3, 5, 6, 7),
3662 // store the whole register as-is to the parameter save area
3663 // slot.
3664 Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3665 MachinePointerInfo(&*FuncArg));
3666 }
3667
3668 MemOps.push_back(Store);
3669 }
3670 // Whether we copied from a register or not, advance the offset
3671 // into the parameter save area by a full doubleword.
3672 ArgOffset += PtrByteSize;
3673 continue;
3674 }
3675
3676 // The value of the object is its address, which is the address of
3677 // its first stack doubleword.
3678 InVals.push_back(FIN);
3679
3680 // Store whatever pieces of the object are in registers to memory.
3681 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
3682 if (GPR_idx == Num_GPR_Regs)
3683 break;
3684
3685 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3686 FuncInfo->addLiveInAttr(VReg, Flags);
3687 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3688 SDValue Addr = FIN;
3689 if (j) {
3690 SDValue Off = DAG.getConstant(j, dl, PtrVT);
3691 Addr = DAG.getNode(ISD::ADD, dl, Off.getValueType(), Addr, Off);
3692 }
3693 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, Addr,
3694 MachinePointerInfo(&*FuncArg, j));
3695 MemOps.push_back(Store);
3696 ++GPR_idx;
3697 }
3698 ArgOffset += ArgSize;
3699 continue;
3700 }
3701
3702 switch (ObjectVT.getSimpleVT().SimpleTy) {
3703 default: llvm_unreachable("Unhandled argument type!")::llvm::llvm_unreachable_internal("Unhandled argument type!",
"/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/PowerPC/PPCISelLowering.cpp"
, 3703)
;
3704 case MVT::i1:
3705 case MVT::i32:
3706 case MVT::i64:
3707 if (Flags.isNest()) {
3708 // The 'nest' parameter, if any, is passed in R11.
3709 unsigned VReg = MF.addLiveIn(PPC::X11, &PPC::G8RCRegClass);
3710 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
3711
3712 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
3713 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
3714
3715 break;
3716 }
3717
3718 // These can be scalar arguments or elements of an integer array type
3719 // passed directly. Clang may use those instead of "byval" aggregate
3720 // types to avoid forcing arguments to memory unnecessarily.
3721 if (GPR_idx != Num_GPR_Regs) {
3722 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
3723 FuncInfo->addLiveInAttr(VReg, Flags);
3724 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
3725
3726 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
3727 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
3728 // value to MVT::i64 and then truncate to the correct register size.
3729 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
3730 } else {
3731 if (CallConv == CallingConv::Fast)
3732 ComputeArgOffset();
3733
3734 needsLoad = true;
3735 ArgSize = PtrByteSize;
3736 }
3737 if (CallConv != CallingConv::Fast || needsLoad)
3738 ArgOffset += 8;
3739 break;
3740
3741 case MVT::f32:
3742 case MVT::f64:
3743 // These can be scalar arguments or elements of a float array type
3744 // passed directly. The latter are used to implement ELFv2 homogenous
3745 // float aggregates.
3746 if (FPR_idx != Num_FPR_Regs) {
3747 unsigned VReg;
3748
3749 if (ObjectVT == MVT::f32)
3750 VReg = MF.addLiveIn(FPR[FPR_idx],
3751 Subtarget.hasP8Vector()
3752 ? &PPC::VSSRCRegClass
3753 : &PPC::F4RCRegClass);
3754 else
3755 VReg = MF.addLiveIn(FPR[FPR_idx], Subtarget.hasVSX()
3756 ? &PPC::VSFRCRegClass
3757 : &PPC::F8RCRegClass);
3758
3759 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3760 ++FPR_idx;
3761 } else if (GPR_idx != Num_GPR_Regs && CallConv != CallingConv::Fast) {
3762 // FIXME: We may want to re-enable this for CallingConv::Fast on the P8
3763 // once we support fp <-> gpr moves.
3764
3765 // This can only ever happen in the presence of f32 array types,
3766 // since otherwise we never run out of FPRs before running out
3767 // of GPRs.
3768 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
3769 FuncInfo->addLiveInAttr(VReg, Flags);
3770 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
3771
3772 if (ObjectVT == MVT::f32) {
3773 if ((ArgOffset % PtrByteSize) == (isLittleEndian ? 4 : 0))
3774 ArgVal = DAG.getNode(ISD::SRL, dl, MVT::i64, ArgVal,
3775 DAG.getConstant(32, dl, MVT::i32));
3776 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal);
3777 }
3778
3779 ArgVal = DAG.getNode(ISD::BITCAST, dl, ObjectVT, ArgVal);
3780 } else {
3781 if (CallConv == CallingConv::Fast)
3782 ComputeArgOffset();
3783
3784 needsLoad = true;
3785 }
3786
3787 // When passing an array of floats, the array occupies consecutive
3788 // space in the argument area; only round up to the next doubleword
3789 // at the end of the array. Otherwise, each float takes 8 bytes.
3790 if (CallConv != CallingConv::Fast || needsLoad) {
3791 ArgSize = Flags.isInConsecutiveRegs() ? ObjSize : PtrByteSize;
3792 ArgOffset += ArgSize;
3793 if (Flags.isInConsecutiveRegsLast())
3794 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3795 }
3796 break;
3797 case MVT::v4f32:
3798 case MVT::v4i32:
3799 case MVT::v8i16:
3800 case MVT::v16i8:
3801 case MVT::v2f64:
3802 case MVT::v2i64:
3803 case MVT::v1i128:
3804 if (!Subtarget.hasQPX()) {
3805 // These can be scalar arguments or elements of a vector array type
3806 // passed directly. The latter are used to implement ELFv2 homogenous
3807 // vector aggregates.
3808 if (VR_idx != Num_VR_Regs) {
3809 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
3810 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3811 ++VR_idx;
3812 } else {
3813 if (CallConv == CallingConv::Fast)
3814 ComputeArgOffset();
3815 needsLoad = true;
3816 }
3817 if (CallConv != CallingConv::Fast || needsLoad)
3818 ArgOffset += 16;
3819 break;
3820 } // not QPX
3821
3822 assert(ObjectVT.getSimpleVT().SimpleTy == MVT::v4f32 &&(static_cast <bool> (ObjectVT.getSimpleVT().SimpleTy ==
MVT::v4f32 && "Invalid QPX parameter type") ? void (
0) : __assert_fail ("ObjectVT.getSimpleVT().SimpleTy == MVT::v4f32 && \"Invalid QPX parameter type\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/PowerPC/PPCISelLowering.cpp"
, 3823, __extension__ __PRETTY_FUNCTION__))
3823 "Invalid QPX parameter type")(static_cast <bool> (ObjectVT.getSimpleVT().SimpleTy ==
MVT::v4f32 && "Invalid QPX parameter type") ? void (
0) : __assert_fail ("ObjectVT.getSimpleVT().SimpleTy == MVT::v4f32 && \"Invalid QPX parameter type\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/PowerPC/PPCISelLowering.cpp"
, 3823, __extension__ __PRETTY_FUNCTION__))
;
3824 /* fall through */
3825
3826 case MVT::v4f64:
3827 case MVT::v4i1:
3828 // QPX vectors are treated like their scalar floating-point subregisters
3829 // (except that they're larger).
3830 unsigned Sz = ObjectVT.getSimpleVT().SimpleTy == MVT::v4f32 ? 16 : 32;
3831 if (QFPR_idx != Num_QFPR_Regs) {
3832 const TargetRegisterClass *RC;
3833 switch (ObjectVT.getSimpleVT().SimpleTy) {
3834 case MVT::v4f64: RC = &PPC::QFRCRegClass; break;
3835 case MVT::v4f32: RC = &PPC::QSRCRegClass; break;
3836 default: RC = &PPC::QBRCRegClass; break;
3837 }
3838
3839 unsigned VReg = MF.addLiveIn(QFPR[QFPR_idx], RC);
3840 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3841 ++QFPR_idx;
3842 } else {
3843 if (CallConv == CallingConv::Fast)
3844 ComputeArgOffset();
3845 needsLoad = true;
3846 }
3847 if (CallConv != CallingConv::Fast || needsLoad)
3848 ArgOffset += Sz;
3849 break;
3850 }
3851
3852 // We need to load the argument to a virtual register if we determined
3853 // above that we ran out of physical registers of the appropriate type.
3854 if (needsLoad) {
3855 if (ObjSize < ArgSize && !isLittleEndian)
3856 CurArgOffset += ArgSize - ObjSize;
3857 int FI = MFI.CreateFixedObject(ObjSize, CurArgOffset, isImmutable);
3858 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3859 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo());
3860 }
3861
3862 InVals.push_back(ArgVal);
3863 }
3864
3865 // Area that is at least reserved in the caller of this function.
3866 unsigned MinReservedArea;
3867 if (HasParameterArea)
3868 MinReservedArea = std::max(ArgOffset, LinkageSize + 8 * PtrByteSize);
3869 else
3870 MinReservedArea = LinkageSize;
3871
3872 // Set the size that is at least reserved in caller of this function. Tail
3873 // call optimized functions' reserved stack space needs to be aligned so that
3874 // taking the difference between two stack areas will result in an aligned
3875 // stack.
3876 MinReservedArea =
3877 EnsureStackAlignment(Subtarget.getFrameLowering(), MinReservedArea);
3878 FuncInfo->setMinReservedArea(MinReservedArea);
3879
3880 // If the function takes variable number of arguments, make a frame index for
3881 // the start of the first vararg value... for expansion of llvm.va_start.
3882 if (isVarArg) {
3883 int Depth = ArgOffset;
3884
3885 FuncInfo->setVarArgsFrameIndex(
3886 MFI.CreateFixedObject(PtrByteSize, Depth, true));
3887 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
3888
3889 // If this function is vararg, store any remaining integer argument regs
3890 // to their spots on the stack so that they may be loaded by dereferencing
3891 // the result of va_next.
3892 for (GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
3893 GPR_idx < Num_GPR_Regs; ++GPR_idx) {
3894 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3895 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3896 SDValue Store =
3897 DAG.getStore(Val.getValue(1), dl, Val, FIN, MachinePointerInfo());
3898 MemOps.push_back(Store);
3899 // Increment the address by four for the next argument to store
3900 SDValue PtrOff = DAG.getConstant(PtrByteSize, dl, PtrVT);
3901 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
3902 }
3903 }
3904
3905 if (!MemOps.empty())
3906 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
3907
3908 return Chain;
3909}
3910
3911SDValue PPCTargetLowering::LowerFormalArguments_Darwin(
3912 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
3913 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
3914 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
3915 // TODO: add description of PPC stack frame format, or at least some docs.
3916 //
3917 MachineFunction &MF = DAG.getMachineFunction();
3918 MachineFrameInfo &MFI = MF.getFrameInfo();
3919 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
3920
3921 EVT PtrVT = getPointerTy(MF.getDataLayout());
3922 bool isPPC64 = PtrVT == MVT::i64;
3923 // Potential tail calls could cause overwriting of argument stack slots.
3924 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
3925 (CallConv == CallingConv::Fast));
3926 unsigned PtrByteSize = isPPC64 ? 8 : 4;
3927 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
3928 unsigned ArgOffset = LinkageSize;
3929 // Area that is at least reserved in caller of this function.
3930 unsigned MinReservedArea = ArgOffset;
3931
3932 static const MCPhysReg GPR_32[] = { // 32-bit registers.
3933 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
3934 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
3935 };
3936 static const MCPhysReg GPR_64[] = { // 64-bit registers.
3937 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
3938 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
3939 };
3940 static const MCPhysReg VR[] = {
3941 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
3942 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
3943 };
3944
3945 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
3946 const unsigned Num_FPR_Regs = useSoftFloat() ? 0 : 13;
3947 const unsigned Num_VR_Regs = array_lengthof( VR);
3948
3949 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
3950
3951 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
3952
3953 // In 32-bit non-varargs functions, the stack space for vectors is after the
3954 // stack space for non-vectors. We do not use this space unless we have
3955 // too many vectors to fit in registers, something that only occurs in
3956 // constructed examples:), but we have to walk the arglist to figure
3957 // that out...for the pathological case, compute VecArgOffset as the
3958 // start of the vector parameter area. Computing VecArgOffset is the
3959 // entire point of the following loop.
3960 unsigned VecArgOffset = ArgOffset;
3961 if (!isVarArg && !isPPC64) {
3962 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e;
3963 ++ArgNo) {
3964 EVT ObjectVT = Ins[ArgNo].VT;
3965 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
3966
3967 if (Flags.isByVal()) {
3968 // ObjSize is the true size, ArgSize rounded up to multiple of regs.
3969 unsigned ObjSize = Flags.getByValSize();
3970 unsigned ArgSize =
3971 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3972 VecArgOffset += ArgSize;
3973 continue;
3974 }
3975
3976 switch(ObjectVT.getSimpleVT().SimpleTy) {
3977 default: llvm_unreachable("Unhandled argument type!")::llvm::llvm_unreachable_internal("Unhandled argument type!",
"/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/PowerPC/PPCISelLowering.cpp"
, 3977)
;
3978 case MVT::i1:
3979 case MVT::i32:
3980 case MVT::f32:
3981 VecArgOffset += 4;
3982 break;
3983 case MVT::i64: // PPC64
3984 case MVT::f64:
3985 // FIXME: We are guaranteed to be !isPPC64 at this point.
3986 // Does MVT::i64 apply?
3987 VecArgOffset += 8;
3988 break;
3989 case MVT::v4f32:
3990 case MVT::v4i32:
3991 case MVT::v8i16:
3992 case MVT::v16i8:
3993 // Nothing to do, we're only looking at Nonvector args here.
3994 break;
3995 }
3996 }
3997 }
3998 // We've found where the vector parameter area in memory is. Skip the
3999 // first 12 parameters; these don't use that memory.
4000 VecArgOffset = ((VecArgOffset+15)/16)*16;
4001 VecArgOffset += 12*16;
4002
4003 // Add DAG nodes to load the arguments or copy them out of registers. On
4004 // entry to a function on PPC, the arguments start after the linkage area,
4005 // although the first ones are often in registers.
4006
4007 SmallVector<SDValue, 8> MemOps;
4008 unsigned nAltivecParamsAtEnd = 0;
4009 Function::const_arg_iterator FuncArg = MF.getFunction().arg_begin();
4010 unsigned CurArgIdx = 0;
4011 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
4012 SDValue ArgVal;
4013 bool needsLoad = false;
4014 EVT ObjectVT = Ins[ArgNo].VT;
4015 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
4016 unsigned ArgSize = ObjSize;
4017 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
4018 if (Ins[ArgNo].isOrigArg()) {
4019 std::advance(FuncArg, Ins[ArgNo].getOrigArgIndex() - CurArgIdx);
4020 CurArgIdx = Ins[ArgNo].getOrigArgIndex();
4021 }
4022 unsigned CurArgOffset = ArgOffset;
4023
4024 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
4025 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
4026 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
4027 if (isVarArg || isPPC64) {
4028 MinReservedArea = ((MinReservedArea+15)/16)*16;
4029 MinReservedArea += CalculateStackSlotSize(ObjectVT,
4030 Flags,
4031 PtrByteSize);
4032 } else nAltivecParamsAtEnd++;
4033 } else
4034 // Calculate min reserved area.
4035 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
4036 Flags,
4037 PtrByteSize);
4038
4039 // FIXME the codegen can be much improved in some cases.
4040 // We do not have to keep everything in memory.
4041 if (Flags.isByVal()) {
4042 assert(Ins[ArgNo].isOrigArg() && "Byval arguments cannot be implicit")(static_cast <bool> (Ins[ArgNo].isOrigArg() && "Byval arguments cannot be implicit"
) ? void (0) : __assert_fail ("Ins[ArgNo].isOrigArg() && \"Byval arguments cannot be implicit\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/PowerPC/PPCISelLowering.cpp"
, 4042, __extension__ __PRETTY_FUNCTION__))
;
4043
4044 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
4045 ObjSize = Flags.getByValSize();
4046 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
4047 // Objects of size 1 and 2 are right justified, everything else is
4048 // left justified. This means the memory address is adjusted forwards.
4049 if (ObjSize==1 || ObjSize==2) {
4050 CurArgOffset = CurArgOffset + (4 - ObjSize);
4051 }
4052 // The value of the object is its address.
4053 int FI = MFI.CreateFixedObject(ObjSize, CurArgOffset, false, true);
4054 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
4055 InVals.push_back(FIN);
4056 if (ObjSize==1 || ObjSize==2) {
4057 if (GPR_idx != Num_GPR_Regs) {
4058 unsigned VReg;
4059 if (isPPC64)
4060 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
4061 else
4062 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
4063 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
4064 EVT ObjType = ObjSize == 1 ? MVT::i8 : MVT::i16;
4065 SDValue Store =
4066 DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
4067 MachinePointerInfo(&*FuncArg), ObjType);
4068 MemOps.push_back(Store);
4069 ++GPR_idx;
4070 }
4071
4072 ArgOffset += PtrByteSize;
4073
4074 continue;
4075 }
4076 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
4077 // Store whatever pieces of the object are in registers
4078 // to memory. ArgOffset will be the address of the beginning
4079 // of the object.
4080 if (GPR_idx != Num_GPR_Regs) {
4081 unsigned VReg;
4082 if (isPPC64)
4083 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
4084 else
4085 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
4086 int FI = MFI.CreateFixedObject(PtrByteSize, ArgOffset, true);
4087 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
4088 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
4089 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
4090 MachinePointerInfo(&*FuncArg, j));
4091 MemOps.push_back(Store);
4092 ++GPR_idx;
4093 ArgOffset += PtrByteSize;
4094 } else {
4095 ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
4096 break;
4097 }
4098 }
4099 continue;
4100 }
4101
4102 switch (ObjectVT.getSimpleVT().SimpleTy) {
4103 default: llvm_unreachable("Unhandled argument type!")::llvm::llvm_unreachable_internal("Unhandled argument type!",
"/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/PowerPC/PPCISelLowering.cpp"
, 4103)
;
4104 case MVT::i1:
4105 case MVT::i32:
4106 if (!isPPC64) {
4107 if (GPR_idx != Num_GPR_Regs) {
4108 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
4109 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
4110
4111 if (ObjectVT == MVT::i1)
4112 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgVal);
4113
4114 ++GPR_idx;
4115 } else {
4116 needsLoad = true;
4117 ArgSize = PtrByteSize;
4118 }
4119 // All int arguments reserve stack space in the Darwin ABI.
4120 ArgOffset += PtrByteSize;
4121 break;
4122 }
4123 LLVM_FALLTHROUGH[[clang::fallthrough]];
4124 case MVT::i64: // PPC64
4125 if (GPR_idx != Num_GPR_Regs) {
4126 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
4127 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
4128
4129 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
4130 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
4131 // value to MVT::i64 and then truncate to the correct register size.
4132 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
4133
4134 ++GPR_idx;
4135 } else {
4136 needsLoad = true;
4137 ArgSize = PtrByteSize;
4138 }
4139 // All int arguments reserve stack space in the Darwin ABI.
4140 ArgOffset += 8;
4141 break;
4142
4143 case MVT::f32:
4144 case MVT::f64:
4145 // Every 4 bytes of argument space consumes one of the GPRs available for
4146 // argument passing.
4147 if (GPR_idx != Num_GPR_Regs) {
4148 ++GPR_idx;
4149 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
4150 ++GPR_idx;
4151 }
4152 if (FPR_idx != Num_FPR_Regs) {
4153 unsigned VReg;
4154
4155 if (ObjectVT == MVT::f32)
4156 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
4157 else
4158 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
4159
4160 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
4161 ++FPR_idx;
4162 } else {
4163 needsLoad = true;
4164 }
4165
4166 // All FP arguments reserve stack space in the Darwin ABI.
4167 ArgOffset += isPPC64 ? 8 : ObjSize;
4168 break;
4169 case MVT::v4f32:
4170 case MVT::v4i32:
4171 case MVT::v8i16:
4172 case MVT::v16i8:
4173 // Note that vector arguments in registers don't reserve stack space,
4174 // except in varargs functions.
4175 if (VR_idx != Num_VR_Regs) {
4176 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
4177 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
4178 if (isVarArg) {
4179 while ((ArgOffset % 16) != 0) {
4180 ArgOffset += PtrByteSize;
4181 if (GPR_idx != Num_GPR_Regs)
4182 GPR_idx++;
4183 }
4184 ArgOffset += 16;
4185 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
4186 }
4187 ++VR_idx;
4188 } else {
4189 if (!isVarArg && !isPPC64) {
4190 // Vectors go after all the nonvectors.
4191 CurArgOffset = VecArgOffset;
4192 VecArgOffset += 16;
4193 } else {
4194 // Vectors are aligned.
4195 ArgOffset = ((ArgOffset+15)/16)*16;
4196 CurArgOffset = ArgOffset;
4197 ArgOffset += 16;
4198 }
4199 needsLoad = true;
4200 }
4201 break;
4202 }
4203
4204 // We need to load the argument to a virtual register if we determined above
4205 // that we ran out of physical registers of the appropriate type.
4206 if (needsLoad) {
4207 int FI = MFI.CreateFixedObject(ObjSize,
4208 CurArgOffset + (ArgSize - ObjSize),
4209 isImmutable);
4210 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
4211 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo());
4212 }
4213
4214 InVals.push_back(ArgVal);
4215 }
4216
4217 // Allow for Altivec parameters at the end, if needed.
4218 if (nAltivecParamsAtEnd) {
4219 MinReservedArea = ((MinReservedArea+15)/16)*16;
4220 MinReservedArea += 16*nAltivecParamsAtEnd;
4221 }
4222
4223 // Area that is at least reserved in the caller of this function.
4224 MinReservedArea = std::max(MinReservedArea, LinkageSize + 8 * PtrByteSize);
4225
4226 // Set the size that is at least reserved in caller of this function. Tail
4227 // call optimized functions' reserved stack space needs to be aligned so that
4228 // taking the difference between two stack areas will result in an aligned
4229 // stack.
4230 MinReservedArea =
4231 EnsureStackAlignment(Subtarget.getFrameLowering(), MinReservedArea);
4232 FuncInfo->setMinReservedArea(MinReservedArea);
4233
4234 // If the function takes variable number of arguments, make a frame index for
4235 // the start of the first vararg value... for expansion of llvm.va_start.
4236 if (isVarArg) {
4237 int Depth = ArgOffset;
4238
4239 FuncInfo->setVarArgsFrameIndex(
4240 MFI.CreateFixedObject(PtrVT.getSizeInBits()/8,
4241 Depth, true));
4242 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
4243
4244 // If this function is vararg, store any remaining integer argument regs
4245 // to their spots on the stack so that they may be loaded by dereferencing
4246 // the result of va_next.
4247 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
4248 unsigned VReg;
4249
4250 if (isPPC64)
4251 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
4252 else
4253 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
4254
4255 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
4256 SDValue Store =
4257 DAG.getStore(Val.getValue(1), dl, Val, FIN, MachinePointerInfo());
4258 MemOps.push_back(Store);
4259 // Increment the address by four for the next argument to store
4260 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, dl, PtrVT);
4261 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
4262 }
4263 }
4264
4265 if (!MemOps.empty())
4266 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
4267
4268 return Chain;
4269}
4270
4271/// CalculateTailCallSPDiff - Get the amount the stack pointer has to be
4272/// adjusted to accommodate the arguments for the tailcall.
4273static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall,
4274 unsigned ParamSize) {
4275
4276 if (!isTailCall) return 0;
4277
4278 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>();
4279 unsigned CallerMinReservedArea = FI->getMinReservedArea();
4280 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
4281 // Remember only if the new adjustement is bigger.
4282 if (SPDiff < FI->getTailCallSPDelta())
4283 FI->setTailCallSPDelta(SPDiff);
4284
4285 return SPDiff;
4286}
4287
4288static bool isFunctionGlobalAddress(SDValue Callee);
4289
4290static bool
4291callsShareTOCBase(const Function *Caller, SDValue Callee,
4292 const TargetMachine &TM) {
4293 // If !G, Callee can be an external symbol.
4294 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
4295 if (!G)
4296 return false;
4297
4298 // The medium and large code models are expected to provide a sufficiently
4299 // large TOC to provide all data addressing needs of a module with a
4300 // single TOC. Since each module will be addressed with a single TOC then we
4301 // only need to check that caller and callee don't cross dso boundaries.
4302 if (CodeModel::Medium == TM.getCodeModel() ||
4303 CodeModel::Large == TM.getCodeModel())
4304 return TM.shouldAssumeDSOLocal(*Caller->getParent(), G->getGlobal());
4305
4306 // Otherwise we need to ensure callee and caller are in the same section,
4307 // since the linker may allocate multiple TOCs, and we don't know which
4308 // sections will belong to the same TOC base.
4309
4310 const GlobalValue *GV = G->getGlobal();
4311 if (!GV->isStrongDefinitionForLinker())
4312 return false;
4313
4314 // Any explicitly-specified sections and section prefixes must also match.
4315 // Also, if we're using -ffunction-sections, then each function is always in
4316 // a different section (the same is true for COMDAT functions).
4317 if (TM.getFunctionSections() || GV->hasComdat() || Caller->hasComdat() ||
4318 GV->getSection() != Caller->getSection())
4319 return false;
4320 if (const auto *F = dyn_cast<Function>(GV)) {
4321 if (F->getSectionPrefix() != Caller->getSectionPrefix())
4322 return false;
4323 }
4324
4325 // If the callee might be interposed, then we can't assume the ultimate call
4326 // target will be in the same section. Even in cases where we can assume that
4327 // interposition won't happen, in any case where the linker might insert a
4328 // stub to allow for interposition, we must generate code as though
4329 // interposition might occur. To understand why this matters, consider a
4330 // situation where: a -> b -> c where the arrows indicate calls. b and c are
4331 // in the same section, but a is in a different module (i.e. has a different
4332 // TOC base pointer). If the linker allows for interposition between b and c,
4333 // then it will generate a stub for the call edge between b and c which will
4334 // save the TOC pointer into the designated stack slot allocated by b. If we
4335 // return true here, and therefore allow a tail call between b and c, that
4336 // stack slot won't exist and the b -> c stub will end up saving b'c TOC base
4337 // pointer into the stack slot allocated by a (where the a -> b stub saved
4338 // a's TOC base pointer). If we're not considering a tail call, but rather,
4339 // whether a nop is needed after the call instruction in b, because the linker
4340 // will insert a stub, it might complain about a missing nop if we omit it
4341 // (although many don't complain in this case).
4342 if (!TM.shouldAssumeDSOLocal(*Caller->getParent(), GV))
4343 return false;
4344
4345 return true;
4346}
4347
4348static bool
4349needStackSlotPassParameters(const PPCSubtarget &Subtarget,
4350 const SmallVectorImpl<ISD::OutputArg> &Outs) {
4351 assert(Subtarget.isSVR4ABI() && Subtarget.isPPC64())(static_cast <bool> (Subtarget.isSVR4ABI() && Subtarget
.isPPC64()) ? void (0) : __assert_fail ("Subtarget.isSVR4ABI() && Subtarget.isPPC64()"
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/PowerPC/PPCISelLowering.cpp"
, 4351, __extension__ __PRETTY_FUNCTION__))
;
4352
4353 const unsigned PtrByteSize = 8;
4354 const unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
4355
4356 static const MCPhysReg GPR[] = {
4357 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4358 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4359 };
4360 static const MCPhysReg VR[] = {
4361 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4362 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4363 };
4364
4365 const unsigned NumGPRs = array_lengthof(GPR);
4366 const unsigned NumFPRs = 13;
4367 const unsigned NumVRs = array_lengthof(VR);
4368 const unsigned ParamAreaSize = NumGPRs * PtrByteSize;
4369
4370 unsigned NumBytes = LinkageSize;
4371 unsigned AvailableFPRs = NumFPRs;
4372 unsigned AvailableVRs = NumVRs;
4373
4374 for (const ISD::OutputArg& Param : Outs) {
4375 if (Param.Flags.isNest()) continue;
4376
4377 if (CalculateStackSlotUsed(Param.VT, Param.ArgVT, Param.Flags,
4378 PtrByteSize, LinkageSize, ParamAreaSize,
4379 NumBytes, AvailableFPRs, AvailableVRs,
4380 Subtarget.hasQPX()))
4381 return true;
4382 }
4383 return false;
4384}
4385
4386static bool
4387hasSameArgumentList(const Function *CallerFn, ImmutableCallSite CS) {
4388 if (CS.arg_size() != CallerFn->arg_size())
4389 return false;
4390
4391 ImmutableCallSite::arg_iterator CalleeArgIter = CS.arg_begin();
4392 ImmutableCallSite::arg_iterator CalleeArgEnd = CS.arg_end();
4393 Function::const_arg_iterator CallerArgIter = CallerFn->arg_begin();
4394
4395 for (; CalleeArgIter != CalleeArgEnd; ++CalleeArgIter, ++CallerArgIter) {
4396 const Value* CalleeArg = *CalleeArgIter;
4397 const Value* CallerArg = &(*CallerArgIter);
4398 if (CalleeArg == CallerArg)
4399 continue;
4400
4401 // e.g. @caller([4 x i64] %a, [4 x i64] %b) {
4402 // tail call @callee([4 x i64] undef, [4 x i64] %b)
4403 // }
4404 // 1st argument of callee is undef and has the same type as caller.
4405 if (CalleeArg->getType() == CallerArg->getType() &&
4406 isa<UndefValue>(CalleeArg))
4407 continue;
4408
4409 return false;
4410 }
4411
4412 return true;
4413}
4414
4415// Returns true if TCO is possible between the callers and callees
4416// calling conventions.
4417static bool
4418areCallingConvEligibleForTCO_64SVR4(CallingConv::ID CallerCC,
4419 CallingConv::ID CalleeCC) {
4420 // Tail calls are possible with fastcc and ccc.
4421 auto isTailCallableCC = [] (CallingConv::ID CC){
4422 return CC == CallingConv::C || CC == CallingConv::Fast;
4423 };
4424 if (!isTailCallableCC(CallerCC) || !isTailCallableCC(CalleeCC))
4425 return false;
4426
4427 // We can safely tail call both fastcc and ccc callees from a c calling
4428 // convention caller. If the caller is fastcc, we may have less stack space
4429 // than a non-fastcc caller with the same signature so disable tail-calls in
4430 // that case.
4431 return CallerCC == CallingConv::C || CallerCC == CalleeCC;
4432}
4433
4434bool
4435PPCTargetLowering::IsEligibleForTailCallOptimization_64SVR4(
4436 SDValue Callee,
4437 CallingConv::ID CalleeCC,
4438 ImmutableCallSite CS,
4439 bool isVarArg,
4440 const SmallVectorImpl<ISD::OutputArg> &Outs,
4441 const SmallVectorImpl<ISD::InputArg> &Ins,
4442 SelectionDAG& DAG) const {
4443 bool TailCallOpt = getTargetMachine().Options.GuaranteedTailCallOpt;
4444
4445 if (DisableSCO && !TailCallOpt) return false;
4446
4447 // Variadic argument functions are not supported.
4448 if (isVarArg) return false;
4449
4450 auto &Caller = DAG.getMachineFunction().getFunction();
4451 // Check that the calling conventions are compatible for tco.
4452 if (!areCallingConvEligibleForTCO_64SVR4(Caller.getCallingConv(), CalleeCC))
4453 return false;
4454
4455 // Caller contains any byval parameter is not supported.
4456 if (any_of(Ins, [](const ISD::InputArg &IA) { return IA.Flags.isByVal(); }))
4457 return false;
4458
4459 // Callee contains any byval parameter is not supported, too.
4460 // Note: This is a quick work around, because in some cases, e.g.
4461 // caller's stack size > callee's stack size, we are still able to apply
4462 // sibling call optimization. For example, gcc is able to do SCO for caller1
4463 // in the following example, but not for caller2.
4464 // struct test {
4465 // long int a;
4466 // char ary[56];
4467 // } gTest;
4468 // __attribute__((noinline)) int callee(struct test v, struct test *b) {
4469 // b->a = v.a;
4470 // return 0;
4471 // }
4472 // void caller1(struct test a, struct test c, struct test *b) {
4473 // callee(gTest, b); }
4474 // void caller2(struct test *b) { callee(gTest, b); }
4475 if (any_of(Outs, [](const ISD::OutputArg& OA) { return OA.Flags.isByVal(); }))
4476 return false;
4477
4478 // If callee and caller use different calling conventions, we cannot pass
4479 // parameters on stack since offsets for the parameter area may be different.
4480 if (Caller.getCallingConv() != CalleeCC &&
4481 needStackSlotPassParameters(Subtarget, Outs))
4482 return false;
4483
4484 // No TCO/SCO on indirect call because Caller have to restore its TOC
4485 if (!isFunctionGlobalAddress(Callee) &&
4486 !isa<ExternalSymbolSDNode>(Callee))
4487 return false;
4488
4489 // If the caller and callee potentially have different TOC bases then we
4490 // cannot tail call since we need to restore the TOC pointer after the call.
4491 // ref: https://bugzilla.mozilla.org/show_bug.cgi?id=973977
4492 if (!callsShareTOCBase(&Caller, Callee, getTargetMachine()))
4493 return false;
4494
4495 // TCO allows altering callee ABI, so we don't have to check further.
4496 if (CalleeCC == CallingConv::Fast && TailCallOpt)
4497 return true;
4498
4499 if (DisableSCO) return false;
4500
4501 // If callee use the same argument list that caller is using, then we can
4502 // apply SCO on this case. If it is not, then we need to check if callee needs
4503 // stack for passing arguments.
4504 if (!hasSameArgumentList(&Caller, CS) &&
4505 needStackSlotPassParameters(Subtarget, Outs)) {
4506 return false;
4507 }
4508
4509 return true;
4510}
4511
4512/// IsEligibleForTailCallOptimization - Check whether the call is eligible
4513/// for tail call optimization. Targets which want to do tail call
4514/// optimization should implement this function.
4515bool
4516PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
4517 CallingConv::ID CalleeCC,
4518 bool isVarArg,
4519 const SmallVectorImpl<ISD::InputArg> &Ins,
4520 SelectionDAG& DAG) const {
4521 if (!getTargetMachine().Options.GuaranteedTailCallOpt)
4522 return false;
4523
4524 // Variable argument functions are not supported.
4525 if (isVarArg)
4526 return false;
4527
4528 MachineFunction &MF = DAG.getMachineFunction();
4529 CallingConv::ID CallerCC = MF.getFunction().getCallingConv();
4530 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
4531 // Functions containing by val parameters are not supported.
4532 for (unsigned i = 0; i != Ins.size(); i++) {
4533 ISD::ArgFlagsTy Flags = Ins[i].Flags;
4534 if (Flags.isByVal()) return false;
4535 }
4536
4537 // Non-PIC/GOT tail calls are supported.
4538 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
4539 return true;
4540
4541 // At the moment we can only do local tail calls (in same module, hidden
4542 // or protected) if we are generating PIC.
4543 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
4544 return G->getGlobal()->hasHiddenVisibility()
4545 || G->getGlobal()->hasProtectedVisibility();
4546 }
4547
4548 return false;
4549}
4550
4551/// isCallCompatibleAddress - Return the immediate to use if the specified
4552/// 32-bit value is representable in the immediate field of a BxA instruction.
4553static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
4554 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
4555 if (!C) return nullptr;
4556
4557 int Addr = C->getZExtValue();
4558 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
4559 SignExtend32<26>(Addr) != Addr)
4560 return nullptr; // Top 6 bits have to be sext of immediate.
4561
4562 return DAG
4563 .getConstant(
4564 (int)C->getZExtValue() >> 2, SDLoc(Op),
4565 DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout()))
4566 .getNode();
4567}
4568
4569namespace {
4570
4571struct TailCallArgumentInfo {
4572 SDValue Arg;
4573 SDValue FrameIdxOp;
4574 int FrameIdx = 0;
4575
4576 TailCallArgumentInfo() = default;
4577};
4578
4579} // end anonymous namespace
4580
4581/// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
4582static void StoreTailCallArgumentsToStackSlot(
4583 SelectionDAG &DAG, SDValue Chain,
4584 const SmallVectorImpl<TailCallArgumentInfo> &TailCallArgs,
4585 SmallVectorImpl<SDValue> &MemOpChains, const SDLoc &dl) {
4586 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {
4587 SDValue Arg = TailCallArgs[i].Arg;
4588 SDValue FIN = TailCallArgs[i].FrameIdxOp;
4589 int FI = TailCallArgs[i].FrameIdx;
4590 // Store relative to framepointer.
4591 MemOpChains.push_back(DAG.getStore(
4592 Chain, dl, Arg, FIN,
4593 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI)));
4594 }
4595}
4596
4597/// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to
4598/// the appropriate stack slot for the tail call optimized function call.
4599static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG, SDValue Chain,
4600 SDValue OldRetAddr, SDValue OldFP,
4601 int SPDiff, const SDLoc &dl) {
4602 if (SPDiff) {
4603 // Calculate the new stack slot for the return address.
4604 MachineFunction &MF = DAG.getMachineFunction();
4605 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
4606 const PPCFrameLowering *FL = Subtarget.getFrameLowering();
4607 bool isPPC64 = Subtarget.isPPC64();
4608 int SlotSize = isPPC64 ? 8 : 4;
4609 int NewRetAddrLoc = SPDiff + FL->getReturnSaveOffset();
4610 int NewRetAddr = MF.getFrameInfo().CreateFixedObject(SlotSize,
4611 NewRetAddrLoc, true);
4612 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
4613 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
4614 Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx,
4615 MachinePointerInfo::getFixedStack(MF, NewRetAddr));
4616
4617 // When using the 32/64-bit SVR4 ABI there is no need to move the FP stack
4618 // slot as the FP is never overwritten.
4619 if (Subtarget.isDarwinABI()) {
4620 int NewFPLoc = SPDiff + FL->getFramePointerSaveOffset();
4621 int NewFPIdx = MF.getFrameInfo().CreateFixedObject(SlotSize, NewFPLoc,
4622 true);
4623 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
4624 Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx,
4625 MachinePointerInfo::getFixedStack(
4626 DAG.getMachineFunction(), NewFPIdx));
4627 }
4628 }
4629 return Chain;
4630}
4631
4632/// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
4633/// the position of the argument.
4634static void
4635CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
4636 SDValue Arg, int SPDiff, unsigned ArgOffset,
4637 SmallVectorImpl<TailCallArgumentInfo>& TailCallArguments) {
4638 int Offset = ArgOffset + SPDiff;
4639 uint32_t OpSize = (Arg.getValueSizeInBits() + 7) / 8;
4640 int FI = MF.getFrameInfo().CreateFixedObject(OpSize, Offset, true);
4641 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
4642 SDValue FIN = DAG.getFrameIndex(FI, VT);
4643 TailCallArgumentInfo Info;
4644 Info.Arg = Arg;
4645 Info.FrameIdxOp = FIN;
4646 Info.FrameIdx = FI;
4647 TailCallArguments.push_back(Info);
4648}
4649
4650/// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address
4651/// stack slot. Returns the chain as result and the loaded frame pointers in
4652/// LROpOut/FPOpout. Used when tail calling.
4653SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(
4654 SelectionDAG &DAG, int SPDiff, SDValue Chain, SDValue &LROpOut,
4655 SDValue &FPOpOut, const SDLoc &dl) const {
4656 if (SPDiff) {
4657 // Load the LR and FP stack slot for later adjusting.
4658 EVT VT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32;
4659 LROpOut = getReturnAddrFrameIndex(DAG);
4660 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo());
4661 Chain = SDValue(LROpOut.getNode(), 1);
4662
4663 // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack
4664 // slot as the FP is never overwritten.
4665 if (Subtarget.isDarwinABI()) {
4666 FPOpOut = getFramePointerFrameIndex(DAG);
4667 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, MachinePointerInfo());
4668 Chain = SDValue(FPOpOut.getNode(), 1);
4669 }
4670 }
4671 return Chain;
4672}
4673
4674/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
4675/// by "Src" to address "Dst" of size "Size". Alignment information is
4676/// specified by the specific parameter attribute. The copy will be passed as
4677/// a byval function parameter.
4678/// Sometimes what we are copying is the end of a larger object, the part that
4679/// does not fit in registers.
4680static SDValue CreateCopyOfByValArgument(SDValue Src, SDValue Dst,
4681 SDValue Chain, ISD::ArgFlagsTy Flags,
4682 SelectionDAG &DAG, const SDLoc &dl) {
4683 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
4684 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
4685 false, false, false, MachinePointerInfo(),
4686 MachinePointerInfo());
4687}
4688
4689/// LowerMemOpCallTo - Store the argument to the stack or remember it in case of
4690/// tail calls.
4691static void LowerMemOpCallTo(
4692 SelectionDAG &DAG, MachineFunction &MF, SDValue Chain, SDValue Arg,
4693 SDValue PtrOff, int SPDiff, unsigned ArgOffset, bool isPPC64,
4694 bool isTailCall, bool isVector, SmallVectorImpl<SDValue> &MemOpChains,
4695 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments, const SDLoc &dl) {
4696 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
4697 if (!isTailCall) {
4698 if (isVector) {
4699 SDValue StackPtr;
4700 if (isPPC64)
4701 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4702 else
4703 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4704 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
4705 DAG.getConstant(ArgOffset, dl, PtrVT));
4706 }
4707 MemOpChains.push_back(
4708 DAG.getStore(Chain, dl, Arg, PtrOff, MachinePointerInfo()));
4709 // Calculate and remember argument location.
4710 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
4711 TailCallArguments);
4712}
4713
4714static void
4715PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain,
4716 const SDLoc &dl, int SPDiff, unsigned NumBytes, SDValue LROp,
4717 SDValue FPOp,
4718 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments) {
4719 // Emit a sequence of copyto/copyfrom virtual registers for arguments that
4720 // might overwrite each other in case of tail call optimization.
4721 SmallVector<SDValue, 8> MemOpChains2;
4722 // Do not flag preceding copytoreg stuff together with the following stuff.
4723 InFlag = SDValue();
4724 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
4725 MemOpChains2, dl);
4726 if (!MemOpChains2.empty())
4727 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
4728
4729 // Store the return address to the appropriate stack slot.
4730 Chain = EmitTailCallStoreFPAndRetAddr(DAG, Chain, LROp, FPOp, SPDiff, dl);
4731
4732 // Emit callseq_end just before tailcall node.
4733 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
4734 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
4735 InFlag = Chain.getValue(1);
4736}
4737
4738// Is this global address that of a function that can be called by name? (as
4739// opposed to something that must hold a descriptor for an indirect call).
4740static bool isFunctionGlobalAddress(SDValue Callee) {
4741 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
4742 if (Callee.getOpcode() == ISD::GlobalTLSAddress ||
4743 Callee.getOpcode() == ISD::TargetGlobalTLSAddress)
4744 return false;
4745
4746 return G->getGlobal()->getValueType()->isFunctionTy();
4747 }
4748
4749 return false;
4750}
4751
4752static unsigned
4753PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag, SDValue &Chain,
4754 SDValue CallSeqStart, const SDLoc &dl, int SPDiff, bool isTailCall,
4755 bool isPatchPoint, bool hasNest,
4756 SmallVectorImpl<std::pair<unsigned, SDValue>> &RegsToPass,
4757 SmallVectorImpl<SDValue> &Ops, std::vector<EVT> &NodeTys,
4758 ImmutableCallSite CS, const PPCSubtarget &Subtarget) {
4759 bool isPPC64 = Subtarget.isPPC64();
4760 bool isSVR4ABI = Subtarget.isSVR4ABI();
4761 bool isELFv2ABI = Subtarget.isELFv2ABI();
4762
4763 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
4764 NodeTys.push_back(MVT::Other); // Returns a chain
4765 NodeTys.push_back(MVT::Glue); // Returns a flag for retval copy to use.
4766
4767 unsigned CallOpc = PPCISD::CALL;
4768
4769 bool needIndirectCall = true;
4770 if (!isSVR4ABI || !isPPC64)
4771 if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) {
4772 // If this is an absolute destination address, use the munged value.
4773 Callee = SDValue(Dest, 0);
4774 needIndirectCall = false;
4775 }
4776
4777 // PC-relative references to external symbols should go through $stub, unless
4778 // we're building with the leopard linker or later, which automatically
4779 // synthesizes these stubs.
4780 const TargetMachine &TM = DAG.getTarget();
4781 const Module *Mod = DAG.getMachineFunction().getFunction().getParent();
4782 const GlobalValue *GV = nullptr;
4783 if (auto *G = dyn_cast<GlobalAddressSDNode>(Callee))
4784 GV = G->getGlobal();
4785 bool Local = TM.shouldAssumeDSOLocal(*Mod, GV);
4786 bool UsePlt = !Local && Subtarget.isTargetELF() && !isPPC64;
4787
4788 if (isFunctionGlobalAddress(Callee)) {
4789 GlobalAddressSDNode *G = cast<GlobalAddressSDNode>(Callee);
4790 // A call to a TLS address is actually an indirect call to a
4791 // thread-specific pointer.
4792 unsigned OpFlags = 0;
4793 if (UsePlt)
4794 OpFlags = PPCII::MO_PLT;
4795
4796 // If the callee is a GlobalAddress/ExternalSymbol node (quite common,
4797 // every direct call is) turn it into a TargetGlobalAddress /
4798 // TargetExternalSymbol node so that legalize doesn't hack it.
4799 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
4800 Callee.getValueType(), 0, OpFlags);
4801 needIndirectCall = false;
4802 }
4803
4804 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
4805 unsigned char OpFlags = 0;
4806
4807 if (UsePlt)
4808 OpFlags = PPCII::MO_PLT;
4809
4810 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType(),
4811 OpFlags);
4812 needIndirectCall = false;
4813 }
4814
4815 if (isPatchPoint) {
4816 // We'll form an invalid direct call when lowering a patchpoint; the full
4817 // sequence for an indirect call is complicated, and many of the
4818 // instructions introduced might have side effects (and, thus, can't be
4819 // removed later). The call itself will be removed as soon as the
4820 // argument/return lowering is complete, so the fact that it has the wrong
4821 // kind of operands should not really matter.
4822 needIndirectCall = false;
4823 }
4824
4825 if (needIndirectCall) {
4826 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
4827 // to do the call, we can't use PPCISD::CALL.
4828 SDValue MTCTROps[] = {Chain, Callee, InFlag};
4829
4830 if (isSVR4ABI && isPPC64 && !isELFv2ABI) {
4831 // Function pointers in the 64-bit SVR4 ABI do not point to the function
4832 // entry point, but to the function descriptor (the function entry point
4833 // address is part of the function descriptor though).
4834 // The function descriptor is a three doubleword structure with the
4835 // following fields: function entry point, TOC base address and
4836 // environment pointer.
4837 // Thus for a call through a function pointer, the following actions need
4838 // to be performed:
4839 // 1. Save the TOC of the caller in the TOC save area of its stack
4840 // frame (this is done in LowerCall_Darwin() or LowerCall_64SVR4()).
4841 // 2. Load the address of the function entry point from the function
4842 // descriptor.
4843 // 3. Load the TOC of the callee from the function descriptor into r2.
4844 // 4. Load the environment pointer from the function descriptor into
4845 // r11.
4846 // 5. Branch to the function entry point address.
4847 // 6. On return of the callee, the TOC of the caller needs to be
4848 // restored (this is done in FinishCall()).
4849 //
4850 // The loads are scheduled at the beginning of the call sequence, and the
4851 // register copies are flagged together to ensure that no other
4852 // operations can be scheduled in between. E.g. without flagging the
4853 // copies together, a TOC access in the caller could be scheduled between
4854 // the assignment of the callee TOC and the branch to the callee, which
4855 // results in the TOC access going through the TOC of the callee instead
4856 // of going through the TOC of the caller, which leads to incorrect code.
4857
4858 // Load the address of the function entry point from the function
4859 // descriptor.
4860 SDValue LDChain = CallSeqStart.getValue(CallSeqStart->getNumValues()-1);
4861 if (LDChain.getValueType() == MVT::Glue)
4862 LDChain = CallSeqStart.getValue(CallSeqStart->getNumValues()-2);
4863
4864 auto MMOFlags = Subtarget.hasInvariantFunctionDescriptors()
4865 ? (MachineMemOperand::MODereferenceable |
4866 MachineMemOperand::MOInvariant)
4867 : MachineMemOperand::MONone;
4868
4869 MachinePointerInfo MPI(CS ? CS.getCalledValue() : nullptr);
4870 SDValue LoadFuncPtr = DAG.getLoad(MVT::i64, dl, LDChain, Callee, MPI,
4871 /* Alignment = */ 8, MMOFlags);
4872
4873 // Load environment pointer into r11.
4874 SDValue PtrOff = DAG.getIntPtrConstant(16, dl);
4875 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff);
4876 SDValue LoadEnvPtr =
4877 DAG.getLoad(MVT::i64, dl, LDChain, AddPtr, MPI.getWithOffset(16),
4878 /* Alignment = */ 8, MMOFlags);
4879
4880 SDValue TOCOff = DAG.getIntPtrConstant(8, dl);
4881 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, TOCOff);
4882 SDValue TOCPtr =
4883 DAG.getLoad(MVT::i64, dl, LDChain, AddTOC, MPI.getWithOffset(8),
4884 /* Alignment = */ 8, MMOFlags);
4885
4886 setUsesTOCBasePtr(DAG);
4887 SDValue TOCVal = DAG.getCopyToReg(Chain, dl, PPC::X2, TOCPtr,
4888 InFlag);
4889 Chain = TOCVal.getValue(0);
4890 InFlag = TOCVal.getValue(1);
4891
4892 // If the function call has an explicit 'nest' parameter, it takes the
4893 // place of the environment pointer.
4894 if (!hasNest) {
4895 SDValue EnvVal = DAG.getCopyToReg(Chain, dl, PPC::X11, LoadEnvPtr,
4896 InFlag);
4897
4898 Chain = EnvVal.getValue(0);
4899 InFlag = EnvVal.getValue(1);
4900 }
4901
4902 MTCTROps[0] = Chain;
4903 MTCTROps[1] = LoadFuncPtr;
4904 MTCTROps[2] = InFlag;
4905 }
4906
4907 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys,
4908 makeArrayRef(MTCTROps, InFlag.getNode() ? 3 : 2));
4909 InFlag = Chain.getValue(1);
4910
4911 NodeTys.clear();
4912 NodeTys.push_back(MVT::Other);
4913 NodeTys.push_back(MVT::Glue);
4914 Ops.push_back(Chain);
4915 CallOpc = PPCISD::BCTRL;
4916 Callee.setNode(nullptr);
4917 // Add use of X11 (holding environment pointer)
4918 if (isSVR4ABI && isPPC64 && !isELFv2ABI && !hasNest)
4919 Ops.push_back(DAG.getRegister(PPC::X11, PtrVT));
4920 // Add CTR register as callee so a bctr can be emitted later.
4921 if (isTailCall)
4922 Ops.push_back(DAG.getRegister(isPPC64 ? PPC::CTR8 : PPC::CTR, PtrVT));
4923 }
4924
4925 // If this is a direct call, pass the chain and the callee.
4926 if (Callee.getNode()) {
4927 Ops.push_back(Chain);
4928 Ops.push_back(Callee);
4929 }
4930 // If this is a tail call add stack pointer delta.
4931 if (isTailCall)
4932 Ops.push_back(DAG.getConstant(SPDiff, dl, MVT::i32));
4933
4934 // Add argument registers to the end of the list so that they are known live
4935 // into the call.
4936 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
4937 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
4938 RegsToPass[i].second.getValueType()));
4939
4940 // All calls, in both the ELF V1 and V2 ABIs, need the TOC register live
4941 // into the call.
4942 if (isSVR4ABI && isPPC64 && !isPatchPoint) {
4943 setUsesTOCBasePtr(DAG);
4944 Ops.push_back(DAG.getRegister(PPC::X2, PtrVT));
4945 }
4946
4947 return CallOpc;
4948}
4949
4950SDValue PPCTargetLowering::LowerCallResult(
4951 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
4952 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
4953 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
4954 SmallVector<CCValAssign, 16> RVLocs;
4955 CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
4956 *DAG.getContext());
4957
4958 CCRetInfo.AnalyzeCallResult(
4959 Ins, (Subtarget.isSVR4ABI() && CallConv == CallingConv::Cold)
4960 ? RetCC_PPC_Cold
4961 : RetCC_PPC);
4962
4963 // Copy all of the result registers out of their specified physreg.
4964 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
4965 CCValAssign &VA = RVLocs[i];
4966 assert(VA.isRegLoc() && "Can only return in registers!")(static_cast <bool> (VA.isRegLoc() && "Can only return in registers!"
) ? void (0) : __assert_fail ("VA.isRegLoc() && \"Can only return in registers!\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/PowerPC/PPCISelLowering.cpp"
, 4966, __extension__ __PRETTY_FUNCTION__))
;
4967
4968 SDValue Val = DAG.getCopyFromReg(Chain, dl,
4969 VA.getLocReg(), VA.getLocVT(), InFlag);
4970 Chain = Val.getValue(1);
4971 InFlag = Val.getValue(2);
4972
4973 switch (VA.getLocInfo()) {
4974 default: llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/PowerPC/PPCISelLowering.cpp"
, 4974)
;
4975 case CCValAssign::Full: break;
4976 case CCValAssign::AExt:
4977 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
4978 break;
4979 case CCValAssign::ZExt:
4980 Val = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), Val,
4981 DAG.getValueType(VA.getValVT()));
4982 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
4983 break;
4984 case CCValAssign::SExt:
4985 Val = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), Val,
4986 DAG.getValueType(VA.getValVT()));
4987 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
4988 break;
4989 }
4990
4991 InVals.push_back(Val);
4992 }
4993
4994 return Chain;
4995}
4996
4997SDValue PPCTargetLowering::FinishCall(
4998 CallingConv::ID CallConv, const SDLoc &dl, bool isTailCall, bool isVarArg,
4999 bool isPatchPoint, bool hasNest, SelectionDAG &DAG,
5000 SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass, SDValue InFlag,
5001 SDValue Chain, SDValue CallSeqStart, SDValue &Callee, int SPDiff,
5002 unsigned NumBytes, const SmallVectorImpl<ISD::InputArg> &Ins,
5003 SmallVectorImpl<SDValue> &InVals, ImmutableCallSite CS) const {
5004 std::vector<EVT> NodeTys;
5005 SmallVector<SDValue, 8> Ops;
5006 unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, CallSeqStart, dl,
5007 SPDiff, isTailCall, isPatchPoint, hasNest,
5008 RegsToPass, Ops, NodeTys, CS, Subtarget);
5009
5010 // Add implicit use of CR bit 6 for 32-bit SVR4 vararg calls
5011 if (isVarArg && Subtarget.isSVR4ABI() && !Subtarget.isPPC64())
5012 Ops.push_back(DAG.getRegister(PPC::CR1EQ, MVT::i32));
5013
5014 // When performing tail call optimization the callee pops its arguments off
5015 // the stack. Account for this here so these bytes can be pushed back on in
5016 // PPCFrameLowering::eliminateCallFramePseudoInstr.
5017 int BytesCalleePops =
5018 (CallConv == CallingConv::Fast &&
5019 getTargetMachine().Options.GuaranteedTailCallOpt) ? NumBytes : 0;
5020
5021 // Add a register mask operand representing the call-preserved registers.
5022 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
5023 const uint32_t *Mask =
5024 TRI->getCallPreservedMask(DAG.getMachineFunction(), CallConv);
5025 assert(Mask && "Missing call preserved mask for calling convention")(static_cast <bool> (Mask && "Missing call preserved mask for calling convention"
) ? void (0) : __assert_fail ("Mask && \"Missing call preserved mask for calling convention\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5025, __extension__ __PRETTY_FUNCTION__))
;
5026 Ops.push_back(DAG.getRegisterMask(Mask));
5027
5028 if (InFlag.getNode())
5029 Ops.push_back(InFlag);
5030
5031 // Emit tail call.
5032 if (isTailCall) {
5033 assert(((Callee.getOpcode() == ISD::Register &&(static_cast <bool> (((Callee.getOpcode() == ISD::Register
&& cast<RegisterSDNode>(Callee)->getReg() ==
PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol
|| Callee.getOpcode() == ISD::TargetGlobalAddress || isa<
ConstantSDNode>(Callee)) && "Expecting an global address, external symbol, absolute value or register"
) ? void (0) : __assert_fail ("((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress || isa<ConstantSDNode>(Callee)) && \"Expecting an global address, external symbol, absolute value or register\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5038, __extension__ __PRETTY_FUNCTION__))
5034 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) ||(static_cast <bool> (((Callee.getOpcode() == ISD::Register
&& cast<RegisterSDNode>(Callee)->getReg() ==
PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol
|| Callee.getOpcode() == ISD::TargetGlobalAddress || isa<
ConstantSDNode>(Callee)) && "Expecting an global address, external symbol, absolute value or register"
) ? void (0) : __assert_fail ("((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress || isa<ConstantSDNode>(Callee)) && \"Expecting an global address, external symbol, absolute value or register\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5038, __extension__ __PRETTY_FUNCTION__))
5035 Callee.getOpcode() == ISD::TargetExternalSymbol ||(static_cast <bool> (((Callee.getOpcode() == ISD::Register
&& cast<RegisterSDNode>(Callee)->getReg() ==
PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol
|| Callee.getOpcode() == ISD::TargetGlobalAddress || isa<
ConstantSDNode>(Callee)) && "Expecting an global address, external symbol, absolute value or register"
) ? void (0) : __assert_fail ("((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress || isa<ConstantSDNode>(Callee)) && \"Expecting an global address, external symbol, absolute value or register\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5038, __extension__ __PRETTY_FUNCTION__))
5036 Callee.getOpcode() == ISD::TargetGlobalAddress ||(static_cast <bool> (((Callee.getOpcode() == ISD::Register
&& cast<RegisterSDNode>(Callee)->getReg() ==
PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol
|| Callee.getOpcode() == ISD::TargetGlobalAddress || isa<
ConstantSDNode>(Callee)) && "Expecting an global address, external symbol, absolute value or register"
) ? void (0) : __assert_fail ("((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress || isa<ConstantSDNode>(Callee)) && \"Expecting an global address, external symbol, absolute value or register\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5038, __extension__ __PRETTY_FUNCTION__))
5037 isa<ConstantSDNode>(Callee)) &&(static_cast <bool> (((Callee.getOpcode() == ISD::Register
&& cast<RegisterSDNode>(Callee)->getReg() ==
PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol
|| Callee.getOpcode() == ISD::TargetGlobalAddress || isa<
ConstantSDNode>(Callee)) && "Expecting an global address, external symbol, absolute value or register"
) ? void (0) : __assert_fail ("((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress || isa<ConstantSDNode>(Callee)) && \"Expecting an global address, external symbol, absolute value or register\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5038, __extension__ __PRETTY_FUNCTION__))
5038 "Expecting an global address, external symbol, absolute value or register")(static_cast <bool> (((Callee.getOpcode() == ISD::Register
&& cast<RegisterSDNode>(Callee)->getReg() ==
PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol
|| Callee.getOpcode() == ISD::TargetGlobalAddress || isa<
ConstantSDNode>(Callee)) && "Expecting an global address, external symbol, absolute value or register"
) ? void (0) : __assert_fail ("((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress || isa<ConstantSDNode>(Callee)) && \"Expecting an global address, external symbol, absolute value or register\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5038, __extension__ __PRETTY_FUNCTION__))
;
5039
5040 DAG.getMachineFunction().getFrameInfo().setHasTailCall();
5041 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, Ops);
5042 }
5043
5044 // Add a NOP immediately after the branch instruction when using the 64-bit
5045 // SVR4 ABI. At link time, if caller and callee are in a different module and
5046 // thus have a different TOC, the call will be replaced with a call to a stub
5047 // function which saves the current TOC, loads the TOC of the callee and
5048 // branches to the callee. The NOP will be replaced with a load instruction
5049 // which restores the TOC of the caller from the TOC save slot of the current
5050 // stack frame. If caller and callee belong to the same module (and have the
5051 // same TOC), the NOP will remain unchanged.
5052
5053 MachineFunction &MF = DAG.getMachineFunction();
5054 if (!isTailCall && Subtarget.isSVR4ABI()&& Subtarget.isPPC64() &&
5055 !isPatchPoint) {
5056 if (CallOpc == PPCISD::BCTRL) {
5057 // This is a call through a function pointer.
5058 // Restore the caller TOC from the save area into R2.
5059 // See PrepareCall() for more information about calls through function
5060 // pointers in the 64-bit SVR4 ABI.
5061 // We are using a target-specific load with r2 hard coded, because the
5062 // result of a target-independent load would never go directly into r2,
5063 // since r2 is a reserved register (which prevents the register allocator
5064 // from allocating it), resulting in an additional register being
5065 // allocated and an unnecessary move instruction being generated.
5066 CallOpc = PPCISD::BCTRL_LOAD_TOC;
5067
5068 EVT PtrVT = getPointerTy(DAG.getDataLayout());
5069 SDValue StackPtr = DAG.getRegister(PPC::X1, PtrVT);
5070 unsigned TOCSaveOffset = Subtarget.getFrameLowering()->getTOCSaveOffset();
5071 SDValue TOCOff = DAG.getIntPtrConstant(TOCSaveOffset, dl);
5072 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, StackPtr, TOCOff);
5073
5074 // The address needs to go after the chain input but before the flag (or
5075 // any other variadic arguments).
5076 Ops.insert(std::next(Ops.begin()), AddTOC);
5077 } else if (CallOpc == PPCISD::CALL &&
5078 !callsShareTOCBase(&MF.getFunction(), Callee, DAG.getTarget())) {
5079 // Otherwise insert NOP for non-local calls.
5080 CallOpc = PPCISD::CALL_NOP;
5081 }
5082 }
5083
5084 Chain = DAG.getNode(CallOpc, dl, NodeTys, Ops);
5085 InFlag = Chain.getValue(1);
5086
5087 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
5088 DAG.getIntPtrConstant(BytesCalleePops, dl, true),
5089 InFlag, dl);
5090 if (!Ins.empty())
5091 InFlag = Chain.getValue(1);
5092
5093 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
5094 Ins, dl, DAG, InVals);
5095}
5096
5097SDValue
5098PPCTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
5099 SmallVectorImpl<SDValue> &InVals) const {
5100 SelectionDAG &DAG = CLI.DAG;
5101 SDLoc &dl = CLI.DL;
5102 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
5103 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
5104 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
5105 SDValue Chain = CLI.Chain;
5106 SDValue Callee = CLI.Callee;
5107 bool &isTailCall = CLI.IsTailCall;
5108 CallingConv::ID CallConv = CLI.CallConv;
5109 bool isVarArg = CLI.IsVarArg;
5110 bool isPatchPoint = CLI.IsPatchPoint;
5111 ImmutableCallSite CS = CLI.CS;
5112
5113 if (isTailCall) {
5114 if (Subtarget.useLongCalls() && !(CS && CS.isMustTailCall()))
5115 isTailCall = false;
5116 else if (Subtarget.isSVR4ABI() && Subtarget.isPPC64())
5117 isTailCall =
5118 IsEligibleForTailCallOptimization_64SVR4(Callee, CallConv, CS,
5119 isVarArg, Outs, Ins, DAG);
5120 else
5121 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg,
5122 Ins, DAG);
5123 if (isTailCall) {
5124 ++NumTailCalls;
5125 if (!getTargetMachine().Options.GuaranteedTailCallOpt)
5126 ++NumSiblingCalls;
5127
5128 assert(isa<GlobalAddressSDNode>(Callee) &&(static_cast <bool> (isa<GlobalAddressSDNode>(Callee
) && "Callee should be an llvm::Function object.") ? void
(0) : __assert_fail ("isa<GlobalAddressSDNode>(Callee) && \"Callee should be an llvm::Function object.\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5129, __extension__ __PRETTY_FUNCTION__))
5129 "Callee should be an llvm::Function object.")(static_cast <bool> (isa<GlobalAddressSDNode>(Callee
) && "Callee should be an llvm::Function object.") ? void
(0) : __assert_fail ("isa<GlobalAddressSDNode>(Callee) && \"Callee should be an llvm::Function object.\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5129, __extension__ __PRETTY_FUNCTION__))
;
5130 DEBUG(do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("ppc-lowering")) { const GlobalValue *GV = cast<GlobalAddressSDNode
>(Callee)->getGlobal(); const unsigned Width = 80 - strlen
("TCO caller: ") - strlen(", callee linkage: 0, 0"); dbgs() <<
"TCO caller: " << left_justify(DAG.getMachineFunction(
).getName(), Width) << ", callee linkage: " << GV
->getVisibility() << ", " << GV->getLinkage
() << "\n"; } } while (false)
5131 const GlobalValue *GV = cast<GlobalAddressSDNode>(Callee)->getGlobal();do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("ppc-lowering")) { const GlobalValue *GV = cast<GlobalAddressSDNode
>(Callee)->getGlobal(); const unsigned Width = 80 - strlen
("TCO caller: ") - strlen(", callee linkage: 0, 0"); dbgs() <<
"TCO caller: " << left_justify(DAG.getMachineFunction(
).getName(), Width) << ", callee linkage: " << GV
->getVisibility() << ", " << GV->getLinkage
() << "\n"; } } while (false)
5132 const unsigned Width = 80 - strlen("TCO caller: ")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("ppc-lowering")) { const GlobalValue *GV = cast<GlobalAddressSDNode
>(Callee)->getGlobal(); const unsigned Width = 80 - strlen
("TCO caller: ") - strlen(", callee linkage: 0, 0"); dbgs() <<
"TCO caller: " << left_justify(DAG.getMachineFunction(
).getName(), Width) << ", callee linkage: " << GV
->getVisibility() << ", " << GV->getLinkage
() << "\n"; } } while (false)
5133 - strlen(", callee linkage: 0, 0");do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("ppc-lowering")) { const GlobalValue *GV = cast<GlobalAddressSDNode
>(Callee)->getGlobal(); const unsigned Width = 80 - strlen
("TCO caller: ") - strlen(", callee linkage: 0, 0"); dbgs() <<
"TCO caller: " << left_justify(DAG.getMachineFunction(
).getName(), Width) << ", callee linkage: " << GV
->getVisibility() << ", " << GV->getLinkage
() << "\n"; } } while (false)
5134 dbgs() << "TCO caller: "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("ppc-lowering")) { const GlobalValue *GV = cast<GlobalAddressSDNode
>(Callee)->getGlobal(); const unsigned Width = 80 - strlen
("TCO caller: ") - strlen(", callee linkage: 0, 0"); dbgs() <<
"TCO caller: " << left_justify(DAG.getMachineFunction(
).getName(), Width) << ", callee linkage: " << GV
->getVisibility() << ", " << GV->getLinkage
() << "\n"; } } while (false)
5135 << left_justify(DAG.getMachineFunction().getName(), Width)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("ppc-lowering")) { const GlobalValue *GV = cast<GlobalAddressSDNode
>(Callee)->getGlobal(); const unsigned Width = 80 - strlen
("TCO caller: ") - strlen(", callee linkage: 0, 0"); dbgs() <<
"TCO caller: " << left_justify(DAG.getMachineFunction(
).getName(), Width) << ", callee linkage: " << GV
->getVisibility() << ", " << GV->getLinkage
() << "\n"; } } while (false)
5136 << ", callee linkage: "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("ppc-lowering")) { const GlobalValue *GV = cast<GlobalAddressSDNode
>(Callee)->getGlobal(); const unsigned Width = 80 - strlen
("TCO caller: ") - strlen(", callee linkage: 0, 0"); dbgs() <<
"TCO caller: " << left_justify(DAG.getMachineFunction(
).getName(), Width) << ", callee linkage: " << GV
->getVisibility() << ", " << GV->getLinkage
() << "\n"; } } while (false)
5137 << GV->getVisibility() << ", " << GV->getLinkage() << "\n"do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("ppc-lowering")) { const GlobalValue *GV = cast<GlobalAddressSDNode
>(Callee)->getGlobal(); const unsigned Width = 80 - strlen
("TCO caller: ") - strlen(", callee linkage: 0, 0"); dbgs() <<
"TCO caller: " << left_justify(DAG.getMachineFunction(
).getName(), Width) << ", callee linkage: " << GV
->getVisibility() << ", " << GV->getLinkage
() << "\n"; } } while (false)
5138 )do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("ppc-lowering")) { const GlobalValue *GV = cast<GlobalAddressSDNode
>(Callee)->getGlobal(); const unsigned Width = 80 - strlen
("TCO caller: ") - strlen(", callee linkage: 0, 0"); dbgs() <<
"TCO caller: " << left_justify(DAG.getMachineFunction(
).getName(), Width) << ", callee linkage: " << GV
->getVisibility() << ", " << GV->getLinkage
() << "\n"; } } while (false)
;
5139 }
5140 }
5141
5142 if (!isTailCall && CS && CS.isMustTailCall())
5143 report_fatal_error("failed to perform tail call elimination on a call "
5144 "site marked musttail");
5145
5146 // When long calls (i.e. indirect calls) are always used, calls are always
5147 // made via function pointer. If we have a function name, first translate it
5148 // into a pointer.
5149 if (Subtarget.useLongCalls() && isa<GlobalAddressSDNode>(Callee) &&
5150 !isTailCall)
5151 Callee = LowerGlobalAddress(Callee, DAG);
5152
5153 if (Subtarget.isSVR4ABI()) {
5154 if (Subtarget.isPPC64())
5155 return LowerCall_64SVR4(Chain, Callee, CallConv, isVarArg,
5156 isTailCall, isPatchPoint, Outs, OutVals, Ins,
5157 dl, DAG, InVals, CS);
5158 else
5159 return LowerCall_32SVR4(Chain, Callee, CallConv, isVarArg,
5160 isTailCall, isPatchPoint, Outs, OutVals, Ins,
5161 dl, DAG, InVals, CS);
5162 }
5163
5164 return LowerCall_Darwin(Chain, Callee, CallConv, isVarArg,
5165 isTailCall, isPatchPoint, Outs, OutVals, Ins,
5166 dl, DAG, InVals, CS);
5167}
5168
5169SDValue PPCTargetLowering::LowerCall_32SVR4(
5170 SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg,
5171 bool isTailCall, bool isPatchPoint,
5172 const SmallVectorImpl<ISD::OutputArg> &Outs,
5173 const SmallVectorImpl<SDValue> &OutVals,
5174 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
5175 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals,
5176 ImmutableCallSite CS) const {
5177 // See PPCTargetLowering::LowerFormalArguments_32SVR4() for a description
5178 // of the 32-bit SVR4 ABI stack frame layout.
5179
5180 assert((CallConv == CallingConv::C ||(static_cast <bool> ((CallConv == CallingConv::C || CallConv
== CallingConv::Cold || CallConv == CallingConv::Fast) &&
"Unknown calling convention!") ? void (0) : __assert_fail ("(CallConv == CallingConv::C || CallConv == CallingConv::Cold || CallConv == CallingConv::Fast) && \"Unknown calling convention!\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5182, __extension__ __PRETTY_FUNCTION__))
5181 CallConv == CallingConv::Cold ||(static_cast <bool> ((CallConv == CallingConv::C || CallConv
== CallingConv::Cold || CallConv == CallingConv::Fast) &&
"Unknown calling convention!") ? void (0) : __assert_fail ("(CallConv == CallingConv::C || CallConv == CallingConv::Cold || CallConv == CallingConv::Fast) && \"Unknown calling convention!\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5182, __extension__ __PRETTY_FUNCTION__))
5182 CallConv == CallingConv::Fast) && "Unknown calling convention!")(static_cast <bool> ((CallConv == CallingConv::C || CallConv
== CallingConv::Cold || CallConv == CallingConv::Fast) &&
"Unknown calling convention!") ? void (0) : __assert_fail ("(CallConv == CallingConv::C || CallConv == CallingConv::Cold || CallConv == CallingConv::Fast) && \"Unknown calling convention!\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5182, __extension__ __PRETTY_FUNCTION__))
;
5183
5184 unsigned PtrByteSize = 4;
5185
5186 MachineFunction &MF = DAG.getMachineFunction();
5187
5188 // Mark this function as potentially containing a function that contains a
5189 // tail call. As a consequence the frame pointer will be used for dynamicalloc
5190 // and restoring the callers stack pointer in this functions epilog. This is
5191 // done because by tail calling the called function might overwrite the value
5192 // in this function's (MF) stack pointer stack slot 0(SP).
5193 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
5194 CallConv == CallingConv::Fast)
5195 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
5196
5197 // Count how many bytes are to be pushed on the stack, including the linkage
5198 // area, parameter list area and the part of the local variable space which
5199 // contains copies of aggregates which are passed by value.
5200
5201 // Assign locations to all of the outgoing arguments.
5202 SmallVector<CCValAssign, 16> ArgLocs;
5203 PPCCCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
5204
5205 // Reserve space for the linkage area on the stack.
5206 CCInfo.AllocateStack(Subtarget.getFrameLowering()->getLinkageSize(),
5207 PtrByteSize);
5208 if (useSoftFloat())
5209 CCInfo.PreAnalyzeCallOperands(Outs);
5210
5211 if (isVarArg) {
5212 // Handle fixed and variable vector arguments differently.
5213 // Fixed vector arguments go into registers as long as registers are
5214 // available. Variable vector arguments always go into memory.
5215 unsigned NumArgs = Outs.size();
5216
5217 for (unsigned i = 0; i != NumArgs; ++i) {
5218 MVT ArgVT = Outs[i].VT;
5219 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
5220 bool Result;
5221
5222 if (Outs[i].IsFixed) {
5223 Result = CC_PPC32_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags,
5224 CCInfo);
5225 } else {
5226 Result = CC_PPC32_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full,
5227 ArgFlags, CCInfo);
5228 }
5229
5230 if (Result) {
5231#ifndef NDEBUG
5232 errs() << "Call operand #" << i << " has unhandled type "
5233 << EVT(ArgVT).getEVTString() << "\n";
5234#endif
5235 llvm_unreachable(nullptr)::llvm::llvm_unreachable_internal(nullptr, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5235)
;
5236 }
5237 }
5238 } else {
5239 // All arguments are treated the same.
5240 CCInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4);
5241 }
5242 CCInfo.clearWasPPCF128();
5243
5244 // Assign locations to all of the outgoing aggregate by value arguments.
5245 SmallVector<CCValAssign, 16> ByValArgLocs;
5246 CCState CCByValInfo(CallConv, isVarArg, MF, ByValArgLocs, *DAG.getContext());
5247
5248 // Reserve stack space for the allocations in CCInfo.
5249 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
5250
5251 CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4_ByVal);
5252
5253 // Size of the linkage area, parameter list area and the part of the local
5254 // space variable where copies of aggregates which are passed by value are
5255 // stored.
5256 unsigned NumBytes = CCByValInfo.getNextStackOffset();
5257
5258 // Calculate by how many bytes the stack has to be adjusted in case of tail
5259 // call optimization.
5260 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
5261
5262 // Adjust the stack pointer for the new arguments...
5263 // These operations are automatically eliminated by the prolog/epilog pass
5264 Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, dl);
5265 SDValue CallSeqStart = Chain;
5266
5267 // Load the return address and frame pointer so it can be moved somewhere else
5268 // later.
5269 SDValue LROp, FPOp;
5270 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, dl);
5271
5272 // Set up a copy of the stack pointer for use loading and storing any
5273 // arguments that may not fit in the registers available for argument
5274 // passing.
5275 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
5276
5277 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
5278 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
5279 SmallVector<SDValue, 8> MemOpChains;
5280
5281 bool seenFloatArg = false;
5282 // Walk the register/memloc assignments, inserting copies/loads.
5283 for (unsigned i = 0, j = 0, e = ArgLocs.size();
5284 i != e;
5285 ++i) {
5286 CCValAssign &VA = ArgLocs[i];
5287 SDValue Arg = OutVals[i];
5288 ISD::ArgFlagsTy Flags = Outs[i].Flags;
5289
5290 if (Flags.isByVal()) {
5291 // Argument is an aggregate which is passed by value, thus we need to
5292 // create a copy of it in the local variable space of the current stack
5293 // frame (which is the stack frame of the caller) and pass the address of
5294 // this copy to the callee.
5295 assert((j < ByValArgLocs.size()) && "Index out of bounds!")(static_cast <bool> ((j < ByValArgLocs.size()) &&
"Index out of bounds!") ? void (0) : __assert_fail ("(j < ByValArgLocs.size()) && \"Index out of bounds!\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5295, __extension__ __PRETTY_FUNCTION__))
;
5296 CCValAssign &ByValVA = ByValArgLocs[j++];
5297 assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!")(static_cast <bool> ((VA.getValNo() == ByValVA.getValNo
()) && "ValNo mismatch!") ? void (0) : __assert_fail (
"(VA.getValNo() == ByValVA.getValNo()) && \"ValNo mismatch!\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5297, __extension__ __PRETTY_FUNCTION__))
;
5298
5299 // Memory reserved in the local variable space of the callers stack frame.
5300 unsigned LocMemOffset = ByValVA.getLocMemOffset();
5301
5302 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
5303 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(MF.getDataLayout()),
5304 StackPtr, PtrOff);
5305
5306 // Create a copy of the argument in the local area of the current
5307 // stack frame.
5308 SDValue MemcpyCall =
5309 CreateCopyOfByValArgument(Arg, PtrOff,
5310 CallSeqStart.getNode()->getOperand(0),
5311 Flags, DAG, dl);
5312
5313 // This must go outside the CALLSEQ_START..END.
5314 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall, NumBytes, 0,
5315 SDLoc(MemcpyCall));
5316 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
5317 NewCallSeqStart.getNode());
5318 Chain = CallSeqStart = NewCallSeqStart;
5319
5320 // Pass the address of the aggregate copy on the stack either in a
5321 // physical register or in the parameter list area of the current stack
5322 // frame to the callee.
5323 Arg = PtrOff;
5324 }
5325
5326 if (VA.isRegLoc()) {
5327 if (Arg.getValueType() == MVT::i1)
5328 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Arg);
5329
5330 seenFloatArg |= VA.getLocVT().isFloatingPoint();
5331 // Put argument in a physical register.
5332 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
5333 } else {
5334 // Put argument in the parameter list area of the current stack frame.
5335 assert(VA.isMemLoc())(static_cast <bool> (VA.isMemLoc()) ? void (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5335, __extension__ __PRETTY_FUNCTION__))
;
5336 unsigned LocMemOffset = VA.getLocMemOffset();
5337
5338 if (!isTailCall) {
5339 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
5340 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(MF.getDataLayout()),
5341 StackPtr, PtrOff);
5342
5343 MemOpChains.push_back(
5344 DAG.getStore(Chain, dl, Arg, PtrOff, MachinePointerInfo()));
5345 } else {
5346 // Calculate and remember argument location.
5347 CalculateTailCallArgDest(DAG, MF, false, Arg, SPDiff, LocMemOffset,
5348 TailCallArguments);
5349 }
5350 }
5351 }
5352
5353 if (!MemOpChains.empty())
5354 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
5355
5356 // Build a sequence of copy-to-reg nodes chained together with token chain
5357 // and flag operands which copy the outgoing args into the appropriate regs.
5358 SDValue InFlag;
5359 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
5360 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
5361 RegsToPass[i].second, InFlag);
5362 InFlag = Chain.getValue(1);
5363 }
5364
5365 // Set CR bit 6 to true if this is a vararg call with floating args passed in
5366 // registers.
5367 if (isVarArg) {
5368 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
5369 SDValue Ops[] = { Chain, InFlag };
5370
5371 Chain = DAG.getNode(seenFloatArg ? PPCISD::CR6SET : PPCISD::CR6UNSET,
5372 dl, VTs, makeArrayRef(Ops, InFlag.getNode() ? 2 : 1));
5373
5374 InFlag = Chain.getValue(1);
5375 }
5376
5377 if (isTailCall)
5378 PrepareTailCall(DAG, InFlag, Chain, dl, SPDiff, NumBytes, LROp, FPOp,
5379 TailCallArguments);
5380
5381 return FinishCall(CallConv, dl, isTailCall, isVarArg, isPatchPoint,
5382 /* unused except on PPC64 ELFv1 */ false, DAG,
5383 RegsToPass, InFlag, Chain, CallSeqStart, Callee, SPDiff,
5384 NumBytes, Ins, InVals, CS);
5385}
5386
5387// Copy an argument into memory, being careful to do this outside the
5388// call sequence for the call to which the argument belongs.
5389SDValue PPCTargetLowering::createMemcpyOutsideCallSeq(
5390 SDValue Arg, SDValue PtrOff, SDValue CallSeqStart, ISD::ArgFlagsTy Flags,
5391 SelectionDAG &DAG, const SDLoc &dl) const {
5392 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
5393 CallSeqStart.getNode()->getOperand(0),
5394 Flags, DAG, dl);
5395 // The MEMCPY must go outside the CALLSEQ_START..END.
5396 int64_t FrameSize = CallSeqStart.getConstantOperandVal(1);
5397 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall, FrameSize, 0,
5398 SDLoc(MemcpyCall));
5399 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
5400 NewCallSeqStart.getNode());
5401 return NewCallSeqStart;
5402}
5403
5404SDValue PPCTargetLowering::LowerCall_64SVR4(
5405 SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg,
5406 bool isTailCall, bool isPatchPoint,
5407 const SmallVectorImpl<ISD::OutputArg> &Outs,
5408 const SmallVectorImpl<SDValue> &OutVals,
5409 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
5410 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals,
5411 ImmutableCallSite CS) const {
5412 bool isELFv2ABI = Subtarget.isELFv2ABI();
5413 bool isLittleEndian = Subtarget.isLittleEndian();
5414 unsigned NumOps = Outs.size();
5415 bool hasNest = false;
5416 bool IsSibCall = false;
5417
5418 EVT PtrVT = getPointerTy(DAG.getDataLayout());
5419 unsigned PtrByteSize = 8;
5420
5421 MachineFunction &MF = DAG.getMachineFunction();
5422
5423 if (isTailCall && !getTargetMachine().Options.GuaranteedTailCallOpt)
5424 IsSibCall = true;
5425
5426 // Mark this function as potentially containing a function that contains a
5427 // tail call. As a consequence the frame pointer will be used for dynamicalloc
5428 // and restoring the callers stack pointer in this functions epilog. This is
5429 // done because by tail calling the called function might overwrite the value
5430 // in this function's (MF) stack pointer stack slot 0(SP).
5431 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
5432 CallConv == CallingConv::Fast)
5433 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
5434
5435 assert(!(CallConv == CallingConv::Fast && isVarArg) &&(static_cast <bool> (!(CallConv == CallingConv::Fast &&
isVarArg) && "fastcc not supported on varargs functions"
) ? void (0) : __assert_fail ("!(CallConv == CallingConv::Fast && isVarArg) && \"fastcc not supported on varargs functions\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5436, __extension__ __PRETTY_FUNCTION__))
5436 "fastcc not supported on varargs functions")(static_cast <bool> (!(CallConv == CallingConv::Fast &&
isVarArg) && "fastcc not supported on varargs functions"
) ? void (0) : __assert_fail ("!(CallConv == CallingConv::Fast && isVarArg) && \"fastcc not supported on varargs functions\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5436, __extension__ __PRETTY_FUNCTION__))
;
5437
5438 // Count how many bytes are to be pushed on the stack, including the linkage
5439 // area, and parameter passing area. On ELFv1, the linkage area is 48 bytes
5440 // reserved space for [SP][CR][LR][2 x unused][TOC]; on ELFv2, the linkage
5441 // area is 32 bytes reserved space for [SP][CR][LR][TOC].
5442 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
5443 unsigned NumBytes = LinkageSize;
5444 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
5445 unsigned &QFPR_idx = FPR_idx;
5446
5447 static const MCPhysReg GPR[] = {
5448 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
5449 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
5450 };
5451 static const MCPhysReg VR[] = {
5452 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
5453 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
5454 };
5455
5456 const unsigned NumGPRs = array_lengthof(GPR);
5457 const unsigned NumFPRs = useSoftFloat() ? 0 : 13;
5458 const unsigned NumVRs = array_lengthof(VR);
5459 const unsigned NumQFPRs = NumFPRs;
5460
5461 // On ELFv2, we can avoid allocating the parameter area if all the arguments
5462 // can be passed to the callee in registers.
5463 // For the fast calling convention, there is another check below.
5464 // Note: We should keep consistent with LowerFormalArguments_64SVR4()
5465 bool HasParameterArea = !isELFv2ABI || isVarArg || CallConv == CallingConv::Fast;
5466 if (!HasParameterArea) {
5467 unsigned ParamAreaSize = NumGPRs * PtrByteSize;
5468 unsigned AvailableFPRs = NumFPRs;
5469 unsigned AvailableVRs = NumVRs;
5470 unsigned NumBytesTmp = NumBytes;
5471 for (unsigned i = 0; i != NumOps; ++i) {
5472 if (Outs[i].Flags.isNest()) continue;
5473 if (CalculateStackSlotUsed(Outs[i].VT, Outs[i].ArgVT, Outs[i].Flags,
5474 PtrByteSize, LinkageSize, ParamAreaSize,
5475 NumBytesTmp, AvailableFPRs, AvailableVRs,
5476 Subtarget.hasQPX()))
5477 HasParameterArea = true;
5478 }
5479 }
5480
5481 // When using the fast calling convention, we don't provide backing for
5482 // arguments that will be in registers.
5483 unsigned NumGPRsUsed = 0, NumFPRsUsed = 0, NumVRsUsed = 0;
5484
5485 // Avoid allocating parameter area for fastcc functions if all the arguments
5486 // can be passed in the registers.
5487 if (CallConv == CallingConv::Fast)
5488 HasParameterArea = false;
5489
5490 // Add up all the space actually used.
5491 for (unsigned i = 0; i != NumOps; ++i) {
5492 ISD::ArgFlagsTy Flags = Outs[i].Flags;
5493 EVT ArgVT = Outs[i].VT;
5494 EVT OrigVT = Outs[i].ArgVT;
5495
5496 if (Flags.isNest())
5497 continue;
5498
5499 if (CallConv == CallingConv::Fast) {
5500 if (Flags.isByVal()) {
5501 NumGPRsUsed += (Flags.getByValSize()+7)/8;
5502 if (NumGPRsUsed > NumGPRs)
5503 HasParameterArea = true;
5504 } else {
5505 switch (ArgVT.getSimpleVT().SimpleTy) {
5506 default: llvm_unreachable("Unexpected ValueType for argument!")::llvm::llvm_unreachable_internal("Unexpected ValueType for argument!"
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5506)
;
5507 case MVT::i1:
5508 case MVT::i32:
5509 case MVT::i64:
5510 if (++NumGPRsUsed <= NumGPRs)
5511 continue;
5512 break;
5513 case MVT::v4i32:
5514 case MVT::v8i16:
5515 case MVT::v16i8:
5516 case MVT::v2f64:
5517 case MVT::v2i64:
5518 case MVT::v1i128:
5519 if (++NumVRsUsed <= NumVRs)
5520 continue;
5521 break;
5522 case MVT::v4f32:
5523 // When using QPX, this is handled like a FP register, otherwise, it
5524 // is an Altivec register.
5525 if (Subtarget.hasQPX()) {
5526 if (++NumFPRsUsed <= NumFPRs)
5527 continue;
5528 } else {
5529 if (++NumVRsUsed <= NumVRs)
5530 continue;
5531 }
5532 break;
5533 case MVT::f32:
5534 case MVT::f64:
5535 case MVT::v4f64: // QPX
5536 case MVT::v4i1: // QPX
5537 if (++NumFPRsUsed <= NumFPRs)
5538 continue;
5539 break;
5540 }
5541 HasParameterArea = true;
5542 }
5543 }
5544
5545 /* Respect alignment of argument on the stack. */
5546 unsigned Align =
5547 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
5548 NumBytes = ((NumBytes + Align - 1) / Align) * Align;
5549
5550 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
5551 if (Flags.isInConsecutiveRegsLast())
5552 NumBytes = ((NumBytes + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
5553 }
5554
5555 unsigned NumBytesActuallyUsed = NumBytes;
5556
5557 // In the old ELFv1 ABI,
5558 // the prolog code of the callee may store up to 8 GPR argument registers to
5559 // the stack, allowing va_start to index over them in memory if its varargs.
5560 // Because we cannot tell if this is needed on the caller side, we have to
5561 // conservatively assume that it is needed. As such, make sure we have at
5562 // least enough stack space for the caller to store the 8 GPRs.
5563 // In the ELFv2 ABI, we allocate the parameter area iff a callee
5564 // really requires memory operands, e.g. a vararg function.
5565 if (HasParameterArea)
5566 NumBytes = std::max(NumBytes, LinkageSize + 8 * PtrByteSize);
5567 else
5568 NumBytes = LinkageSize;
5569
5570 // Tail call needs the stack to be aligned.
5571 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
5572 CallConv == CallingConv::Fast)
5573 NumBytes = EnsureStackAlignment(Subtarget.getFrameLowering(), NumBytes);
5574
5575 int SPDiff = 0;
5576
5577 // Calculate by how many bytes the stack has to be adjusted in case of tail
5578 // call optimization.
5579 if (!IsSibCall)
5580 SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
5581
5582 // To protect arguments on the stack from being clobbered in a tail call,
5583 // force all the loads to happen before doing any other lowering.
5584 if (isTailCall)
5585 Chain = DAG.getStackArgumentTokenFactor(Chain);
5586
5587 // Adjust the stack pointer for the new arguments...
5588 // These operations are automatically eliminated by the prolog/epilog pass
5589 if (!IsSibCall)
5590 Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, dl);
5591 SDValue CallSeqStart = Chain;
5592
5593 // Load the return address and frame pointer so it can be move somewhere else
5594 // later.
5595 SDValue LROp, FPOp;
5596 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, dl);
5597
5598 // Set up a copy of the stack pointer for use loading and storing any
5599 // arguments that may not fit in the registers available for argument
5600 // passing.
5601 SDValue StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
5602
5603 // Figure out which arguments are going to go in registers, and which in
5604 // memory. Also, if this is a vararg function, floating point operations
5605 // must be stored to our stack, and loaded into integer regs as well, if
5606 // any integer regs are available for argument passing.
5607 unsigned ArgOffset = LinkageSize;
5608
5609 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
5610 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
5611
5612 SmallVector<SDValue, 8> MemOpChains;
5613 for (unsigned i = 0; i != NumOps; ++i) {
5614 SDValue Arg = OutVals[i];
5615 ISD::ArgFlagsTy Flags = Outs[i].Flags;
5616 EVT ArgVT = Outs[i].VT;
5617 EVT OrigVT = Outs[i].ArgVT;
5618
5619 // PtrOff will be used to store the current argument to the stack if a
5620 // register cannot be found for it.
5621 SDValue PtrOff;
5622
5623 // We re-align the argument offset for each argument, except when using the
5624 // fast calling convention, when we need to make sure we do that only when
5625 // we'll actually use a stack slot.
5626 auto ComputePtrOff = [&]() {
5627 /* Respect alignment of argument on the stack. */
5628 unsigned Align =
5629 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
5630 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
5631
5632 PtrOff = DAG.getConstant(ArgOffset, dl, StackPtr.getValueType());
5633
5634 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
5635 };
5636
5637 if (CallConv != CallingConv::Fast) {
5638 ComputePtrOff();
5639
5640 /* Compute GPR index associated with argument offset. */
5641 GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
5642 GPR_idx = std::min(GPR_idx, NumGPRs);
5643 }
5644
5645 // Promote integers to 64-bit values.
5646 if (Arg.getValueType() == MVT::i32 || Arg.getValueType() == MVT::i1) {
5647 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
5648 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
5649 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
5650 }
5651
5652 // FIXME memcpy is used way more than necessary. Correctness first.
5653 // Note: "by value" is code for passing a structure by value, not
5654 // basic types.
5655 if (Flags.isByVal()) {
5656 // Note: Size includes alignment padding, so
5657 // struct x { short a; char b; }
5658 // will have Size = 4. With #pragma pack(1), it will have Size = 3.
5659 // These are the proper values we need for right-justifying the
5660 // aggregate in a parameter register.
5661 unsigned Size = Flags.getByValSize();
5662
5663 // An empty aggregate parameter takes up no storage and no
5664 // registers.
5665 if (Size == 0)
5666 continue;
5667
5668 if (CallConv == CallingConv::Fast)
5669 ComputePtrOff();
5670
5671 // All aggregates smaller than 8 bytes must be passed right-justified.
5672 if (Size==1 || Size==2 || Size==4) {
5673 EVT VT = (Size==1) ? MVT::i8 : ((Size==2) ? MVT::i16 : MVT::i32);
5674 if (GPR_idx != NumGPRs) {
5675 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
5676 MachinePointerInfo(), VT);
5677 MemOpChains.push_back(Load.getValue(1));
5678 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5679
5680 ArgOffset += PtrByteSize;
5681 continue;
5682 }
5683 }
5684
5685 if (GPR_idx == NumGPRs && Size < 8) {
5686 SDValue AddPtr = PtrOff;
5687 if (!isLittleEndian) {
5688 SDValue Const = DAG.getConstant(PtrByteSize - Size, dl,
5689 PtrOff.getValueType());
5690 AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
5691 }
5692 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
5693 CallSeqStart,
5694 Flags, DAG, dl);
5695 ArgOffset += PtrByteSize;
5696 continue;
5697 }
5698 // Copy entire object into memory. There are cases where gcc-generated
5699 // code assumes it is there, even if it could be put entirely into
5700 // registers. (This is not what the doc says.)
5701
5702 // FIXME: The above statement is likely due to a misunderstanding of the
5703 // documents. All arguments must be copied into the parameter area BY
5704 // THE CALLEE in the event that the callee takes the address of any
5705 // formal argument. That has not yet been implemented. However, it is
5706 // reasonable to use the stack area as a staging area for the register
5707 // load.
5708
5709 // Skip this for small aggregates, as we will use the same slot for a
5710 // right-justified copy, below.
5711 if (Size >= 8)
5712 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
5713 CallSeqStart,
5714 Flags, DAG, dl);
5715
5716 // When a register is available, pass a small aggregate right-justified.
5717 if (Size < 8 && GPR_idx != NumGPRs) {
5718 // The easiest way to get this right-justified in a register
5719 // is to copy the structure into the rightmost portion of a
5720 // local variable slot, then load the whole slot into the
5721 // register.
5722 // FIXME: The memcpy seems to produce pretty awful code for
5723 // small aggregates, particularly for packed ones.
5724 // FIXME: It would be preferable to use the slot in the
5725 // parameter save area instead of a new local variable.
5726 SDValue AddPtr = PtrOff;
5727 if (!isLittleEndian) {
5728 SDValue Const = DAG.getConstant(8 - Size, dl, PtrOff.getValueType());
5729 AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
5730 }
5731 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
5732 CallSeqStart,
5733 Flags, DAG, dl);
5734
5735 // Load the slot into the register.
5736 SDValue Load =
5737 DAG.getLoad(PtrVT, dl, Chain, PtrOff, MachinePointerInfo());
5738 MemOpChains.push_back(Load.getValue(1));
5739 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5740
5741 // Done with this argument.
5742 ArgOffset += PtrByteSize;
5743 continue;
5744 }
5745
5746 // For aggregates larger than PtrByteSize, copy the pieces of the
5747 // object that fit into registers from the parameter save area.
5748 for (unsigned j=0; j<Size; j+=PtrByteSize) {
5749 SDValue Const = DAG.getConstant(j, dl, PtrOff.getValueType());
5750 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
5751 if (GPR_idx != NumGPRs) {
5752 SDValue Load =
5753 DAG.getLoad(PtrVT, dl, Chain, AddArg, MachinePointerInfo());
5754 MemOpChains.push_back(Load.getValue(1));
5755 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5756 ArgOffset += PtrByteSize;
5757 } else {
5758 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
5759 break;
5760 }
5761 }
5762 continue;
5763 }
5764
5765 switch (Arg.getSimpleValueType().SimpleTy) {
5766 default: llvm_unreachable("Unexpected ValueType for argument!")::llvm::llvm_unreachable_internal("Unexpected ValueType for argument!"
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5766)
;
5767 case MVT::i1:
5768 case MVT::i32:
5769 case MVT::i64:
5770 if (Flags.isNest()) {
5771 // The 'nest' parameter, if any, is passed in R11.
5772 RegsToPass.push_back(std::make_pair(PPC::X11, Arg));
5773 hasNest = true;
5774 break;
5775 }
5776
5777 // These can be scalar arguments or elements of an integer array type
5778 // passed directly. Clang may use those instead of "byval" aggregate
5779 // types to avoid forcing arguments to memory unnecessarily.
5780 if (GPR_idx != NumGPRs) {
5781 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
5782 } else {
5783 if (CallConv == CallingConv::Fast)
5784 ComputePtrOff();
5785
5786 assert(HasParameterArea &&(static_cast <bool> (HasParameterArea && "Parameter area must exist to pass an argument in memory."
) ? void (0) : __assert_fail ("HasParameterArea && \"Parameter area must exist to pass an argument in memory.\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5787, __extension__ __PRETTY_FUNCTION__))
5787 "Parameter area must exist to pass an argument in memory.")(static_cast <bool> (HasParameterArea && "Parameter area must exist to pass an argument in memory."
) ? void (0) : __assert_fail ("HasParameterArea && \"Parameter area must exist to pass an argument in memory.\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5787, __extension__ __PRETTY_FUNCTION__))
;
5788 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5789 true, isTailCall, false, MemOpChains,
5790 TailCallArguments, dl);
5791 if (CallConv == CallingConv::Fast)
5792 ArgOffset += PtrByteSize;
5793 }
5794 if (CallConv != CallingConv::Fast)
5795 ArgOffset += PtrByteSize;
5796 break;
5797 case MVT::f32:
5798 case MVT::f64: {
5799 // These can be scalar arguments or elements of a float array type
5800 // passed directly. The latter are used to implement ELFv2 homogenous
5801 // float aggregates.
5802
5803 // Named arguments go into FPRs first, and once they overflow, the
5804 // remaining arguments go into GPRs and then the parameter save area.
5805 // Unnamed arguments for vararg functions always go to GPRs and
5806 // then the parameter save area. For now, put all arguments to vararg
5807 // routines always in both locations (FPR *and* GPR or stack slot).
5808 bool NeedGPROrStack = isVarArg || FPR_idx == NumFPRs;
5809 bool NeededLoad = false;
5810
5811 // First load the argument into the next available FPR.
5812 if (FPR_idx != NumFPRs)
5813 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
5814
5815 // Next, load the argument into GPR or stack slot if needed.
5816 if (!NeedGPROrStack)
5817 ;
5818 else if (GPR_idx != NumGPRs && CallConv != CallingConv::Fast) {
5819 // FIXME: We may want to re-enable this for CallingConv::Fast on the P8
5820 // once we support fp <-> gpr moves.
5821
5822 // In the non-vararg case, this can only ever happen in the
5823 // presence of f32 array types, since otherwise we never run
5824 // out of FPRs before running out of GPRs.
5825 SDValue ArgVal;
5826
5827 // Double values are always passed in a single GPR.
5828 if (Arg.getValueType() != MVT::f32) {
5829 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
5830
5831 // Non-array float values are extended and passed in a GPR.
5832 } else if (!Flags.isInConsecutiveRegs()) {
5833 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
5834 ArgVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, ArgVal);
5835
5836 // If we have an array of floats, we collect every odd element
5837 // together with its predecessor into one GPR.
5838 } else if (ArgOffset % PtrByteSize != 0) {
5839 SDValue Lo, Hi;
5840 Lo = DAG.getNode(ISD::BITCAST, dl, MVT::i32, OutVals[i - 1]);
5841 Hi = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
5842 if (!isLittleEndian)
5843 std::swap(Lo, Hi);
5844 ArgVal = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
5845
5846 // The final element, if even, goes into the first half of a GPR.
5847 } else if (Flags.isInConsecutiveRegsLast()) {
5848 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
5849 ArgVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, ArgVal);
5850 if (!isLittleEndian)
5851 ArgVal = DAG.getNode(ISD::SHL, dl, MVT::i64, ArgVal,
5852 DAG.getConstant(32, dl, MVT::i32));
5853
5854 // Non-final even elements are skipped; they will be handled
5855 // together the with subsequent argument on the next go-around.
5856 } else
5857 ArgVal = SDValue();
5858
5859 if (ArgVal.getNode())
5860 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], ArgVal));
5861 } else {
5862 if (CallConv == CallingConv::Fast)
5863 ComputePtrOff();
5864
5865 // Single-precision floating-point values are mapped to the
5866 // second (rightmost) word of the stack doubleword.
5867 if (Arg.getValueType() == MVT::f32 &&
5868 !isLittleEndian && !Flags.isInConsecutiveRegs()) {
5869 SDValue ConstFour = DAG.getConstant(4, dl, PtrOff.getValueType());
5870 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
5871 }
5872
5873 assert(HasParameterArea &&(static_cast <bool> (HasParameterArea && "Parameter area must exist to pass an argument in memory."
) ? void (0) : __assert_fail ("HasParameterArea && \"Parameter area must exist to pass an argument in memory.\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5874, __extension__ __PRETTY_FUNCTION__))
5874 "Parameter area must exist to pass an argument in memory.")(static_cast <bool> (HasParameterArea && "Parameter area must exist to pass an argument in memory."
) ? void (0) : __assert_fail ("HasParameterArea && \"Parameter area must exist to pass an argument in memory.\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5874, __extension__ __PRETTY_FUNCTION__))
;
5875 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5876 true, isTailCall, false, MemOpChains,
5877 TailCallArguments, dl);
5878
5879 NeededLoad = true;
5880 }
5881 // When passing an array of floats, the array occupies consecutive
5882 // space in the argument area; only round up to the next doubleword
5883 // at the end of the array. Otherwise, each float takes 8 bytes.
5884 if (CallConv != CallingConv::Fast || NeededLoad) {
5885 ArgOffset += (Arg.getValueType() == MVT::f32 &&
5886 Flags.isInConsecutiveRegs()) ? 4 : 8;
5887 if (Flags.isInConsecutiveRegsLast())
5888 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
5889 }
5890 break;
5891 }
5892 case MVT::v4f32:
5893 case MVT::v4i32:
5894 case MVT::v8i16:
5895 case MVT::v16i8:
5896 case MVT::v2f64:
5897 case MVT::v2i64:
5898 case MVT::v1i128:
5899 if (!Subtarget.hasQPX()) {
5900 // These can be scalar arguments or elements of a vector array type
5901 // passed directly. The latter are used to implement ELFv2 homogenous
5902 // vector aggregates.
5903
5904 // For a varargs call, named arguments go into VRs or on the stack as
5905 // usual; unnamed arguments always go to the stack or the corresponding
5906 // GPRs when within range. For now, we always put the value in both
5907 // locations (or even all three).
5908 if (isVarArg) {
5909 assert(HasParameterArea &&(static_cast <bool> (HasParameterArea && "Parameter area must exist if we have a varargs call."
) ? void (0) : __assert_fail ("HasParameterArea && \"Parameter area must exist if we have a varargs call.\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5910, __extension__ __PRETTY_FUNCTION__))
5910 "Parameter area must exist if we have a varargs call.")(static_cast <bool> (HasParameterArea && "Parameter area must exist if we have a varargs call."
) ? void (0) : __assert_fail ("HasParameterArea && \"Parameter area must exist if we have a varargs call.\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5910, __extension__ __PRETTY_FUNCTION__))
;
5911 // We could elide this store in the case where the object fits
5912 // entirely in R registers. Maybe later.
5913 SDValue Store =
5914 DAG.getStore(Chain, dl, Arg, PtrOff, MachinePointerInfo());
5915 MemOpChains.push_back(Store);
5916 if (VR_idx != NumVRs) {
5917