Bug Summary

File:llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Warning:line 16138, column 9
Assigned value is garbage or undefined

Annotated Source Code

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clang -cc1 -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name PPCISelLowering.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mframe-pointer=none -fmath-errno -fno-rounding-math -mconstructor-aliases -munwind-tables -target-cpu x86-64 -tune-cpu generic -fno-split-dwarf-inlining -debugger-tuning=gdb -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-12/lib/clang/12.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-12~++20201124111112+7b5254223ac/build-llvm/lib/Target/PowerPC -I /build/llvm-toolchain-snapshot-12~++20201124111112+7b5254223ac/llvm/lib/Target/PowerPC -I /build/llvm-toolchain-snapshot-12~++20201124111112+7b5254223ac/build-llvm/include -I /build/llvm-toolchain-snapshot-12~++20201124111112+7b5254223ac/llvm/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0/backward -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-12/lib/clang/12.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++14 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-12~++20201124111112+7b5254223ac/build-llvm/lib/Target/PowerPC -fdebug-prefix-map=/build/llvm-toolchain-snapshot-12~++20201124111112+7b5254223ac=. -ferror-limit 19 -fvisibility hidden -fvisibility-inlines-hidden -stack-protector 2 -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -o /tmp/scan-build-2020-11-24-172238-38865-1 -x c++ /build/llvm-toolchain-snapshot-12~++20201124111112+7b5254223ac/llvm/lib/Target/PowerPC/PPCISelLowering.cpp

/build/llvm-toolchain-snapshot-12~++20201124111112+7b5254223ac/llvm/lib/Target/PowerPC/PPCISelLowering.cpp

1//===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the PPCISelLowering class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "PPCISelLowering.h"
14#include "MCTargetDesc/PPCPredicates.h"
15#include "PPC.h"
16#include "PPCCCState.h"
17#include "PPCCallingConv.h"
18#include "PPCFrameLowering.h"
19#include "PPCInstrInfo.h"
20#include "PPCMachineFunctionInfo.h"
21#include "PPCPerfectShuffle.h"
22#include "PPCRegisterInfo.h"
23#include "PPCSubtarget.h"
24#include "PPCTargetMachine.h"
25#include "llvm/ADT/APFloat.h"
26#include "llvm/ADT/APInt.h"
27#include "llvm/ADT/ArrayRef.h"
28#include "llvm/ADT/DenseMap.h"
29#include "llvm/ADT/None.h"
30#include "llvm/ADT/STLExtras.h"
31#include "llvm/ADT/SmallPtrSet.h"
32#include "llvm/ADT/SmallSet.h"
33#include "llvm/ADT/SmallVector.h"
34#include "llvm/ADT/Statistic.h"
35#include "llvm/ADT/StringRef.h"
36#include "llvm/ADT/StringSwitch.h"
37#include "llvm/CodeGen/CallingConvLower.h"
38#include "llvm/CodeGen/ISDOpcodes.h"
39#include "llvm/CodeGen/MachineBasicBlock.h"
40#include "llvm/CodeGen/MachineFrameInfo.h"
41#include "llvm/CodeGen/MachineFunction.h"
42#include "llvm/CodeGen/MachineInstr.h"
43#include "llvm/CodeGen/MachineInstrBuilder.h"
44#include "llvm/CodeGen/MachineJumpTableInfo.h"
45#include "llvm/CodeGen/MachineLoopInfo.h"
46#include "llvm/CodeGen/MachineMemOperand.h"
47#include "llvm/CodeGen/MachineModuleInfo.h"
48#include "llvm/CodeGen/MachineOperand.h"
49#include "llvm/CodeGen/MachineRegisterInfo.h"
50#include "llvm/CodeGen/RuntimeLibcalls.h"
51#include "llvm/CodeGen/SelectionDAG.h"
52#include "llvm/CodeGen/SelectionDAGNodes.h"
53#include "llvm/CodeGen/TargetInstrInfo.h"
54#include "llvm/CodeGen/TargetLowering.h"
55#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
56#include "llvm/CodeGen/TargetRegisterInfo.h"
57#include "llvm/CodeGen/ValueTypes.h"
58#include "llvm/IR/CallingConv.h"
59#include "llvm/IR/Constant.h"
60#include "llvm/IR/Constants.h"
61#include "llvm/IR/DataLayout.h"
62#include "llvm/IR/DebugLoc.h"
63#include "llvm/IR/DerivedTypes.h"
64#include "llvm/IR/Function.h"
65#include "llvm/IR/GlobalValue.h"
66#include "llvm/IR/IRBuilder.h"
67#include "llvm/IR/Instructions.h"
68#include "llvm/IR/Intrinsics.h"
69#include "llvm/IR/IntrinsicsPowerPC.h"
70#include "llvm/IR/Module.h"
71#include "llvm/IR/Type.h"
72#include "llvm/IR/Use.h"
73#include "llvm/IR/Value.h"
74#include "llvm/MC/MCContext.h"
75#include "llvm/MC/MCExpr.h"
76#include "llvm/MC/MCRegisterInfo.h"
77#include "llvm/MC/MCSectionXCOFF.h"
78#include "llvm/MC/MCSymbolXCOFF.h"
79#include "llvm/Support/AtomicOrdering.h"
80#include "llvm/Support/BranchProbability.h"
81#include "llvm/Support/Casting.h"
82#include "llvm/Support/CodeGen.h"
83#include "llvm/Support/CommandLine.h"
84#include "llvm/Support/Compiler.h"
85#include "llvm/Support/Debug.h"
86#include "llvm/Support/ErrorHandling.h"
87#include "llvm/Support/Format.h"
88#include "llvm/Support/KnownBits.h"
89#include "llvm/Support/MachineValueType.h"
90#include "llvm/Support/MathExtras.h"
91#include "llvm/Support/raw_ostream.h"
92#include "llvm/Target/TargetMachine.h"
93#include "llvm/Target/TargetOptions.h"
94#include <algorithm>
95#include <cassert>
96#include <cstdint>
97#include <iterator>
98#include <list>
99#include <utility>
100#include <vector>
101
102using namespace llvm;
103
104#define DEBUG_TYPE"ppc-lowering" "ppc-lowering"
105
106static cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc",
107cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden);
108
109static cl::opt<bool> DisableILPPref("disable-ppc-ilp-pref",
110cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden);
111
112static cl::opt<bool> DisablePPCUnaligned("disable-ppc-unaligned",
113cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden);
114
115static cl::opt<bool> DisableSCO("disable-ppc-sco",
116cl::desc("disable sibling call optimization on ppc"), cl::Hidden);
117
118static cl::opt<bool> DisableInnermostLoopAlign32("disable-ppc-innermost-loop-align32",
119cl::desc("don't always align innermost loop to 32 bytes on ppc"), cl::Hidden);
120
121static cl::opt<bool> UseAbsoluteJumpTables("ppc-use-absolute-jumptables",
122cl::desc("use absolute jump tables on ppc"), cl::Hidden);
123
124STATISTIC(NumTailCalls, "Number of tail calls")static llvm::Statistic NumTailCalls = {"ppc-lowering", "NumTailCalls"
, "Number of tail calls"}
;
125STATISTIC(NumSiblingCalls, "Number of sibling calls")static llvm::Statistic NumSiblingCalls = {"ppc-lowering", "NumSiblingCalls"
, "Number of sibling calls"}
;
126STATISTIC(ShufflesHandledWithVPERM, "Number of shuffles lowered to a VPERM")static llvm::Statistic ShufflesHandledWithVPERM = {"ppc-lowering"
, "ShufflesHandledWithVPERM", "Number of shuffles lowered to a VPERM"
}
;
127STATISTIC(NumDynamicAllocaProbed, "Number of dynamic stack allocation probed")static llvm::Statistic NumDynamicAllocaProbed = {"ppc-lowering"
, "NumDynamicAllocaProbed", "Number of dynamic stack allocation probed"
}
;
128
129static bool isNByteElemShuffleMask(ShuffleVectorSDNode *, unsigned, int);
130
131static SDValue widenVec(SelectionDAG &DAG, SDValue Vec, const SDLoc &dl);
132
133// FIXME: Remove this once the bug has been fixed!
134extern cl::opt<bool> ANDIGlueBug;
135
136PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
137 const PPCSubtarget &STI)
138 : TargetLowering(TM), Subtarget(STI) {
139 // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all
140 // arguments are at least 4/8 bytes aligned.
141 bool isPPC64 = Subtarget.isPPC64();
142 setMinStackArgumentAlignment(isPPC64 ? Align(8) : Align(4));
143
144 // Set up the register classes.
145 addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
146 if (!useSoftFloat()) {
147 if (hasSPE()) {
148 addRegisterClass(MVT::f32, &PPC::GPRCRegClass);
149 addRegisterClass(MVT::f64, &PPC::SPERCRegClass);
150 } else {
151 addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
152 addRegisterClass(MVT::f64, &PPC::F8RCRegClass);
153 }
154 }
155
156 // Match BITREVERSE to customized fast code sequence in the td file.
157 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
158 setOperationAction(ISD::BITREVERSE, MVT::i64, Legal);
159
160 // Sub-word ATOMIC_CMP_SWAP need to ensure that the input is zero-extended.
161 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom);
162
163 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD.
164 for (MVT VT : MVT::integer_valuetypes()) {
165 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
166 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand);
167 }
168
169 if (Subtarget.isISA3_0()) {
170 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Legal);
171 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Legal);
172 setTruncStoreAction(MVT::f64, MVT::f16, Legal);
173 setTruncStoreAction(MVT::f32, MVT::f16, Legal);
174 } else {
175 // No extending loads from f16 or HW conversions back and forth.
176 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
177 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
178 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
179 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
180 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
181 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
182 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
183 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
184 }
185
186 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
187
188 // PowerPC has pre-inc load and store's.
189 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
190 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
191 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
192 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
193 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
194 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
195 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
196 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
197 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
198 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
199 if (!Subtarget.hasSPE()) {
200 setIndexedLoadAction(ISD::PRE_INC, MVT::f32, Legal);
201 setIndexedLoadAction(ISD::PRE_INC, MVT::f64, Legal);
202 setIndexedStoreAction(ISD::PRE_INC, MVT::f32, Legal);
203 setIndexedStoreAction(ISD::PRE_INC, MVT::f64, Legal);
204 }
205
206 // PowerPC uses ADDC/ADDE/SUBC/SUBE to propagate carry.
207 const MVT ScalarIntVTs[] = { MVT::i32, MVT::i64 };
208 for (MVT VT : ScalarIntVTs) {
209 setOperationAction(ISD::ADDC, VT, Legal);
210 setOperationAction(ISD::ADDE, VT, Legal);
211 setOperationAction(ISD::SUBC, VT, Legal);
212 setOperationAction(ISD::SUBE, VT, Legal);
213 }
214
215 if (Subtarget.useCRBits()) {
216 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
217
218 if (isPPC64 || Subtarget.hasFPCVT()) {
219 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i1, Promote);
220 AddPromotedToType(ISD::STRICT_SINT_TO_FP, MVT::i1,
221 isPPC64 ? MVT::i64 : MVT::i32);
222 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i1, Promote);
223 AddPromotedToType(ISD::STRICT_UINT_TO_FP, MVT::i1,
224 isPPC64 ? MVT::i64 : MVT::i32);
225
226 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote);
227 AddPromotedToType (ISD::SINT_TO_FP, MVT::i1,
228 isPPC64 ? MVT::i64 : MVT::i32);
229 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote);
230 AddPromotedToType(ISD::UINT_TO_FP, MVT::i1,
231 isPPC64 ? MVT::i64 : MVT::i32);
232 } else {
233 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i1, Custom);
234 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i1, Custom);
235 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Custom);
236 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Custom);
237 }
238
239 // PowerPC does not support direct load/store of condition registers.
240 setOperationAction(ISD::LOAD, MVT::i1, Custom);
241 setOperationAction(ISD::STORE, MVT::i1, Custom);
242
243 // FIXME: Remove this once the ANDI glue bug is fixed:
244 if (ANDIGlueBug)
245 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
246
247 for (MVT VT : MVT::integer_valuetypes()) {
248 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
249 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
250 setTruncStoreAction(VT, MVT::i1, Expand);
251 }
252
253 addRegisterClass(MVT::i1, &PPC::CRBITRCRegClass);
254 }
255
256 // Expand ppcf128 to i32 by hand for the benefit of llvm-gcc bootstrap on
257 // PPC (the libcall is not available).
258 setOperationAction(ISD::FP_TO_SINT, MVT::ppcf128, Custom);
259 setOperationAction(ISD::FP_TO_UINT, MVT::ppcf128, Custom);
260 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::ppcf128, Custom);
261 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::ppcf128, Custom);
262
263 // We do not currently implement these libm ops for PowerPC.
264 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand);
265 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand);
266 setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand);
267 setOperationAction(ISD::FRINT, MVT::ppcf128, Expand);
268 setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand);
269 setOperationAction(ISD::FREM, MVT::ppcf128, Expand);
270
271 // PowerPC has no SREM/UREM instructions unless we are on P9
272 // On P9 we may use a hardware instruction to compute the remainder.
273 // When the result of both the remainder and the division is required it is
274 // more efficient to compute the remainder from the result of the division
275 // rather than use the remainder instruction. The instructions are legalized
276 // directly because the DivRemPairsPass performs the transformation at the IR
277 // level.
278 if (Subtarget.isISA3_0()) {
279 setOperationAction(ISD::SREM, MVT::i32, Legal);
280 setOperationAction(ISD::UREM, MVT::i32, Legal);
281 setOperationAction(ISD::SREM, MVT::i64, Legal);
282 setOperationAction(ISD::UREM, MVT::i64, Legal);
283 } else {
284 setOperationAction(ISD::SREM, MVT::i32, Expand);
285 setOperationAction(ISD::UREM, MVT::i32, Expand);
286 setOperationAction(ISD::SREM, MVT::i64, Expand);
287 setOperationAction(ISD::UREM, MVT::i64, Expand);
288 }
289
290 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
291 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
292 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
293 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
294 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
295 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
296 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
297 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
298 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
299
300 // Handle constrained floating-point operations of scalar.
301 // TODO: Handle SPE specific operation.
302 setOperationAction(ISD::STRICT_FADD, MVT::f32, Legal);
303 setOperationAction(ISD::STRICT_FSUB, MVT::f32, Legal);
304 setOperationAction(ISD::STRICT_FMUL, MVT::f32, Legal);
305 setOperationAction(ISD::STRICT_FDIV, MVT::f32, Legal);
306 setOperationAction(ISD::STRICT_FMA, MVT::f32, Legal);
307 setOperationAction(ISD::STRICT_FP_ROUND, MVT::f32, Legal);
308
309 setOperationAction(ISD::STRICT_FADD, MVT::f64, Legal);
310 setOperationAction(ISD::STRICT_FSUB, MVT::f64, Legal);
311 setOperationAction(ISD::STRICT_FMUL, MVT::f64, Legal);
312 setOperationAction(ISD::STRICT_FDIV, MVT::f64, Legal);
313 setOperationAction(ISD::STRICT_FMA, MVT::f64, Legal);
314 if (Subtarget.hasVSX()) {
315 setOperationAction(ISD::STRICT_FRINT, MVT::f32, Legal);
316 setOperationAction(ISD::STRICT_FRINT, MVT::f64, Legal);
317 }
318
319 if (Subtarget.hasFSQRT()) {
320 setOperationAction(ISD::STRICT_FSQRT, MVT::f32, Legal);
321 setOperationAction(ISD::STRICT_FSQRT, MVT::f64, Legal);
322 }
323
324 if (Subtarget.hasFPRND()) {
325 setOperationAction(ISD::STRICT_FFLOOR, MVT::f32, Legal);
326 setOperationAction(ISD::STRICT_FCEIL, MVT::f32, Legal);
327 setOperationAction(ISD::STRICT_FTRUNC, MVT::f32, Legal);
328 setOperationAction(ISD::STRICT_FROUND, MVT::f32, Legal);
329
330 setOperationAction(ISD::STRICT_FFLOOR, MVT::f64, Legal);
331 setOperationAction(ISD::STRICT_FCEIL, MVT::f64, Legal);
332 setOperationAction(ISD::STRICT_FTRUNC, MVT::f64, Legal);
333 setOperationAction(ISD::STRICT_FROUND, MVT::f64, Legal);
334 }
335
336 // We don't support sin/cos/sqrt/fmod/pow
337 setOperationAction(ISD::FSIN , MVT::f64, Expand);
338 setOperationAction(ISD::FCOS , MVT::f64, Expand);
339 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
340 setOperationAction(ISD::FREM , MVT::f64, Expand);
341 setOperationAction(ISD::FPOW , MVT::f64, Expand);
342 setOperationAction(ISD::FSIN , MVT::f32, Expand);
343 setOperationAction(ISD::FCOS , MVT::f32, Expand);
344 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
345 setOperationAction(ISD::FREM , MVT::f32, Expand);
346 setOperationAction(ISD::FPOW , MVT::f32, Expand);
347 if (Subtarget.hasSPE()) {
348 setOperationAction(ISD::FMA , MVT::f64, Expand);
349 setOperationAction(ISD::FMA , MVT::f32, Expand);
350 } else {
351 setOperationAction(ISD::FMA , MVT::f64, Legal);
352 setOperationAction(ISD::FMA , MVT::f32, Legal);
353 }
354
355 if (Subtarget.hasSPE())
356 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand);
357
358 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
359
360 // If we're enabling GP optimizations, use hardware square root
361 if (!Subtarget.hasFSQRT() &&
362 !(TM.Options.UnsafeFPMath && Subtarget.hasFRSQRTE() &&
363 Subtarget.hasFRE()))
364 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
365
366 if (!Subtarget.hasFSQRT() &&
367 !(TM.Options.UnsafeFPMath && Subtarget.hasFRSQRTES() &&
368 Subtarget.hasFRES()))
369 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
370
371 if (Subtarget.hasFCPSGN()) {
372 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Legal);
373 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Legal);
374 } else {
375 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
376 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
377 }
378
379 if (Subtarget.hasFPRND()) {
380 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
381 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
382 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
383 setOperationAction(ISD::FROUND, MVT::f64, Legal);
384
385 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
386 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
387 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
388 setOperationAction(ISD::FROUND, MVT::f32, Legal);
389 }
390
391 // PowerPC does not have BSWAP, but we can use vector BSWAP instruction xxbrd
392 // to speed up scalar BSWAP64.
393 // CTPOP or CTTZ were introduced in P8/P9 respectively
394 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
395 if (Subtarget.hasP9Vector())
396 setOperationAction(ISD::BSWAP, MVT::i64 , Custom);
397 else
398 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
399 if (Subtarget.isISA3_0()) {
400 setOperationAction(ISD::CTTZ , MVT::i32 , Legal);
401 setOperationAction(ISD::CTTZ , MVT::i64 , Legal);
402 } else {
403 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
404 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
405 }
406
407 if (Subtarget.hasPOPCNTD() == PPCSubtarget::POPCNTD_Fast) {
408 setOperationAction(ISD::CTPOP, MVT::i32 , Legal);
409 setOperationAction(ISD::CTPOP, MVT::i64 , Legal);
410 } else {
411 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
412 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
413 }
414
415 // PowerPC does not have ROTR
416 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
417 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
418
419 if (!Subtarget.useCRBits()) {
420 // PowerPC does not have Select
421 setOperationAction(ISD::SELECT, MVT::i32, Expand);
422 setOperationAction(ISD::SELECT, MVT::i64, Expand);
423 setOperationAction(ISD::SELECT, MVT::f32, Expand);
424 setOperationAction(ISD::SELECT, MVT::f64, Expand);
425 }
426
427 // PowerPC wants to turn select_cc of FP into fsel when possible.
428 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
429 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
430
431 // PowerPC wants to optimize integer setcc a bit
432 if (!Subtarget.useCRBits())
433 setOperationAction(ISD::SETCC, MVT::i32, Custom);
434
435 if (Subtarget.hasFPU()) {
436 setOperationAction(ISD::STRICT_FSETCC, MVT::f32, Legal);
437 setOperationAction(ISD::STRICT_FSETCC, MVT::f64, Legal);
438 setOperationAction(ISD::STRICT_FSETCC, MVT::f128, Legal);
439
440 setOperationAction(ISD::STRICT_FSETCCS, MVT::f32, Legal);
441 setOperationAction(ISD::STRICT_FSETCCS, MVT::f64, Legal);
442 setOperationAction(ISD::STRICT_FSETCCS, MVT::f128, Legal);
443 }
444
445 // PowerPC does not have BRCOND which requires SetCC
446 if (!Subtarget.useCRBits())
447 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
448
449 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
450
451 if (Subtarget.hasSPE()) {
452 // SPE has built-in conversions
453 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i32, Legal);
454 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i32, Legal);
455 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i32, Legal);
456 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
457 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
458 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
459 } else {
460 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
461 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i32, Custom);
462 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
463
464 // PowerPC does not have [U|S]INT_TO_FP
465 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i32, Expand);
466 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i32, Expand);
467 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
468 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
469 }
470
471 if (Subtarget.hasDirectMove() && isPPC64) {
472 setOperationAction(ISD::BITCAST, MVT::f32, Legal);
473 setOperationAction(ISD::BITCAST, MVT::i32, Legal);
474 setOperationAction(ISD::BITCAST, MVT::i64, Legal);
475 setOperationAction(ISD::BITCAST, MVT::f64, Legal);
476 if (TM.Options.UnsafeFPMath) {
477 setOperationAction(ISD::LRINT, MVT::f64, Legal);
478 setOperationAction(ISD::LRINT, MVT::f32, Legal);
479 setOperationAction(ISD::LLRINT, MVT::f64, Legal);
480 setOperationAction(ISD::LLRINT, MVT::f32, Legal);
481 setOperationAction(ISD::LROUND, MVT::f64, Legal);
482 setOperationAction(ISD::LROUND, MVT::f32, Legal);
483 setOperationAction(ISD::LLROUND, MVT::f64, Legal);
484 setOperationAction(ISD::LLROUND, MVT::f32, Legal);
485 }
486 } else {
487 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
488 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
489 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
490 setOperationAction(ISD::BITCAST, MVT::f64, Expand);
491 }
492
493 // We cannot sextinreg(i1). Expand to shifts.
494 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
495
496 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
497 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
498 // support continuation, user-level threading, and etc.. As a result, no
499 // other SjLj exception interfaces are implemented and please don't build
500 // your own exception handling based on them.
501 // LLVM/Clang supports zero-cost DWARF exception handling.
502 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
503 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
504
505 // We want to legalize GlobalAddress and ConstantPool nodes into the
506 // appropriate instructions to materialize the address.
507 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
508 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
509 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
510 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
511 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
512 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
513 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
514 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
515 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
516 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
517
518 // TRAP is legal.
519 setOperationAction(ISD::TRAP, MVT::Other, Legal);
520
521 // TRAMPOLINE is custom lowered.
522 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
523 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
524
525 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
526 setOperationAction(ISD::VASTART , MVT::Other, Custom);
527
528 if (Subtarget.is64BitELFABI()) {
529 // VAARG always uses double-word chunks, so promote anything smaller.
530 setOperationAction(ISD::VAARG, MVT::i1, Promote);
531 AddPromotedToType(ISD::VAARG, MVT::i1, MVT::i64);
532 setOperationAction(ISD::VAARG, MVT::i8, Promote);
533 AddPromotedToType(ISD::VAARG, MVT::i8, MVT::i64);
534 setOperationAction(ISD::VAARG, MVT::i16, Promote);
535 AddPromotedToType(ISD::VAARG, MVT::i16, MVT::i64);
536 setOperationAction(ISD::VAARG, MVT::i32, Promote);
537 AddPromotedToType(ISD::VAARG, MVT::i32, MVT::i64);
538 setOperationAction(ISD::VAARG, MVT::Other, Expand);
539 } else if (Subtarget.is32BitELFABI()) {
540 // VAARG is custom lowered with the 32-bit SVR4 ABI.
541 setOperationAction(ISD::VAARG, MVT::Other, Custom);
542 setOperationAction(ISD::VAARG, MVT::i64, Custom);
543 } else
544 setOperationAction(ISD::VAARG, MVT::Other, Expand);
545
546 // VACOPY is custom lowered with the 32-bit SVR4 ABI.
547 if (Subtarget.is32BitELFABI())
548 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
549 else
550 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
551
552 // Use the default implementation.
553 setOperationAction(ISD::VAEND , MVT::Other, Expand);
554 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
555 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
556 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
557 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
558 setOperationAction(ISD::GET_DYNAMIC_AREA_OFFSET, MVT::i32, Custom);
559 setOperationAction(ISD::GET_DYNAMIC_AREA_OFFSET, MVT::i64, Custom);
560 setOperationAction(ISD::EH_DWARF_CFA, MVT::i32, Custom);
561 setOperationAction(ISD::EH_DWARF_CFA, MVT::i64, Custom);
562
563 // We want to custom lower some of our intrinsics.
564 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
565
566 // To handle counter-based loop conditions.
567 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i1, Custom);
568
569 setOperationAction(ISD::INTRINSIC_VOID, MVT::i8, Custom);
570 setOperationAction(ISD::INTRINSIC_VOID, MVT::i16, Custom);
571 setOperationAction(ISD::INTRINSIC_VOID, MVT::i32, Custom);
572 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
573
574 // Comparisons that require checking two conditions.
575 if (Subtarget.hasSPE()) {
576 setCondCodeAction(ISD::SETO, MVT::f32, Expand);
577 setCondCodeAction(ISD::SETO, MVT::f64, Expand);
578 setCondCodeAction(ISD::SETUO, MVT::f32, Expand);
579 setCondCodeAction(ISD::SETUO, MVT::f64, Expand);
580 }
581 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
582 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
583 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
584 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
585 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
586 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
587 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
588 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
589 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
590 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
591 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
592 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
593
594 if (Subtarget.has64BitSupport()) {
595 // They also have instructions for converting between i64 and fp.
596 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i64, Custom);
597 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i64, Expand);
598 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i64, Custom);
599 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i64, Expand);
600 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
601 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
602 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
603 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
604 // This is just the low 32 bits of a (signed) fp->i64 conversion.
605 // We cannot do this with Promote because i64 is not a legal type.
606 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i32, Custom);
607 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
608
609 if (Subtarget.hasLFIWAX() || Subtarget.isPPC64()) {
610 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
611 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i32, Custom);
612 }
613 } else {
614 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
615 if (Subtarget.hasSPE()) {
616 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i32, Legal);
617 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
618 } else {
619 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i32, Expand);
620 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
621 }
622 }
623
624 // With the instructions enabled under FPCVT, we can do everything.
625 if (Subtarget.hasFPCVT()) {
626 if (Subtarget.has64BitSupport()) {
627 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i64, Custom);
628 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i64, Custom);
629 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i64, Custom);
630 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i64, Custom);
631 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
632 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
633 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
634 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
635 }
636
637 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i32, Custom);
638 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i32, Custom);
639 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i32, Custom);
640 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i32, Custom);
641 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
642 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
643 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
644 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
645 }
646
647 if (Subtarget.use64BitRegs()) {
648 // 64-bit PowerPC implementations can support i64 types directly
649 addRegisterClass(MVT::i64, &PPC::G8RCRegClass);
650 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
651 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
652 // 64-bit PowerPC wants to expand i128 shifts itself.
653 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
654 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
655 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
656 } else {
657 // 32-bit PowerPC wants to expand i64 shifts itself.
658 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
659 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
660 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
661 }
662
663 // PowerPC has better expansions for funnel shifts than the generic
664 // TargetLowering::expandFunnelShift.
665 if (Subtarget.has64BitSupport()) {
666 setOperationAction(ISD::FSHL, MVT::i64, Custom);
667 setOperationAction(ISD::FSHR, MVT::i64, Custom);
668 }
669 setOperationAction(ISD::FSHL, MVT::i32, Custom);
670 setOperationAction(ISD::FSHR, MVT::i32, Custom);
671
672 if (Subtarget.hasVSX()) {
673 setOperationAction(ISD::FMAXNUM_IEEE, MVT::f64, Legal);
674 setOperationAction(ISD::FMAXNUM_IEEE, MVT::f32, Legal);
675 setOperationAction(ISD::FMINNUM_IEEE, MVT::f64, Legal);
676 setOperationAction(ISD::FMINNUM_IEEE, MVT::f32, Legal);
677 }
678
679 if (Subtarget.hasAltivec()) {
680 for (MVT VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32 }) {
681 setOperationAction(ISD::SADDSAT, VT, Legal);
682 setOperationAction(ISD::SSUBSAT, VT, Legal);
683 setOperationAction(ISD::UADDSAT, VT, Legal);
684 setOperationAction(ISD::USUBSAT, VT, Legal);
685 }
686 // First set operation action for all vector types to expand. Then we
687 // will selectively turn on ones that can be effectively codegen'd.
688 for (MVT VT : MVT::fixedlen_vector_valuetypes()) {
689 // add/sub are legal for all supported vector VT's.
690 setOperationAction(ISD::ADD, VT, Legal);
691 setOperationAction(ISD::SUB, VT, Legal);
692
693 // For v2i64, these are only valid with P8Vector. This is corrected after
694 // the loop.
695 if (VT.getSizeInBits() <= 128 && VT.getScalarSizeInBits() <= 64) {
696 setOperationAction(ISD::SMAX, VT, Legal);
697 setOperationAction(ISD::SMIN, VT, Legal);
698 setOperationAction(ISD::UMAX, VT, Legal);
699 setOperationAction(ISD::UMIN, VT, Legal);
700 }
701 else {
702 setOperationAction(ISD::SMAX, VT, Expand);
703 setOperationAction(ISD::SMIN, VT, Expand);
704 setOperationAction(ISD::UMAX, VT, Expand);
705 setOperationAction(ISD::UMIN, VT, Expand);
706 }
707
708 if (Subtarget.hasVSX()) {
709 setOperationAction(ISD::FMAXNUM, VT, Legal);
710 setOperationAction(ISD::FMINNUM, VT, Legal);
711 }
712
713 // Vector instructions introduced in P8
714 if (Subtarget.hasP8Altivec() && (VT.SimpleTy != MVT::v1i128)) {
715 setOperationAction(ISD::CTPOP, VT, Legal);
716 setOperationAction(ISD::CTLZ, VT, Legal);
717 }
718 else {
719 setOperationAction(ISD::CTPOP, VT, Expand);
720 setOperationAction(ISD::CTLZ, VT, Expand);
721 }
722
723 // Vector instructions introduced in P9
724 if (Subtarget.hasP9Altivec() && (VT.SimpleTy != MVT::v1i128))
725 setOperationAction(ISD::CTTZ, VT, Legal);
726 else
727 setOperationAction(ISD::CTTZ, VT, Expand);
728
729 // We promote all shuffles to v16i8.
730 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
731 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
732
733 // We promote all non-typed operations to v4i32.
734 setOperationAction(ISD::AND , VT, Promote);
735 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
736 setOperationAction(ISD::OR , VT, Promote);
737 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
738 setOperationAction(ISD::XOR , VT, Promote);
739 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
740 setOperationAction(ISD::LOAD , VT, Promote);
741 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
742 setOperationAction(ISD::SELECT, VT, Promote);
743 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
744 setOperationAction(ISD::VSELECT, VT, Legal);
745 setOperationAction(ISD::SELECT_CC, VT, Promote);
746 AddPromotedToType (ISD::SELECT_CC, VT, MVT::v4i32);
747 setOperationAction(ISD::STORE, VT, Promote);
748 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
749
750 // No other operations are legal.
751 setOperationAction(ISD::MUL , VT, Expand);
752 setOperationAction(ISD::SDIV, VT, Expand);
753 setOperationAction(ISD::SREM, VT, Expand);
754 setOperationAction(ISD::UDIV, VT, Expand);
755 setOperationAction(ISD::UREM, VT, Expand);
756 setOperationAction(ISD::FDIV, VT, Expand);
757 setOperationAction(ISD::FREM, VT, Expand);
758 setOperationAction(ISD::FNEG, VT, Expand);
759 setOperationAction(ISD::FSQRT, VT, Expand);
760 setOperationAction(ISD::FLOG, VT, Expand);
761 setOperationAction(ISD::FLOG10, VT, Expand);
762 setOperationAction(ISD::FLOG2, VT, Expand);
763 setOperationAction(ISD::FEXP, VT, Expand);
764 setOperationAction(ISD::FEXP2, VT, Expand);
765 setOperationAction(ISD::FSIN, VT, Expand);
766 setOperationAction(ISD::FCOS, VT, Expand);
767 setOperationAction(ISD::FABS, VT, Expand);
768 setOperationAction(ISD::FFLOOR, VT, Expand);
769 setOperationAction(ISD::FCEIL, VT, Expand);
770 setOperationAction(ISD::FTRUNC, VT, Expand);
771 setOperationAction(ISD::FRINT, VT, Expand);
772 setOperationAction(ISD::FNEARBYINT, VT, Expand);
773 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
774 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
775 setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
776 setOperationAction(ISD::MULHU, VT, Expand);
777 setOperationAction(ISD::MULHS, VT, Expand);
778 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
779 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
780 setOperationAction(ISD::UDIVREM, VT, Expand);
781 setOperationAction(ISD::SDIVREM, VT, Expand);
782 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
783 setOperationAction(ISD::FPOW, VT, Expand);
784 setOperationAction(ISD::BSWAP, VT, Expand);
785 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
786 setOperationAction(ISD::ROTL, VT, Expand);
787 setOperationAction(ISD::ROTR, VT, Expand);
788
789 for (MVT InnerVT : MVT::fixedlen_vector_valuetypes()) {
790 setTruncStoreAction(VT, InnerVT, Expand);
791 setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand);
792 setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand);
793 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand);
794 }
795 }
796 setOperationAction(ISD::SELECT_CC, MVT::v4i32, Expand);
797 if (!Subtarget.hasP8Vector()) {
798 setOperationAction(ISD::SMAX, MVT::v2i64, Expand);
799 setOperationAction(ISD::SMIN, MVT::v2i64, Expand);
800 setOperationAction(ISD::UMAX, MVT::v2i64, Expand);
801 setOperationAction(ISD::UMIN, MVT::v2i64, Expand);
802 }
803
804 for (auto VT : {MVT::v2i64, MVT::v4i32, MVT::v8i16, MVT::v16i8})
805 setOperationAction(ISD::ABS, VT, Custom);
806
807 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
808 // with merges, splats, etc.
809 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
810
811 // Vector truncates to sub-word integer that fit in an Altivec/VSX register
812 // are cheap, so handle them before they get expanded to scalar.
813 setOperationAction(ISD::TRUNCATE, MVT::v8i8, Custom);
814 setOperationAction(ISD::TRUNCATE, MVT::v4i8, Custom);
815 setOperationAction(ISD::TRUNCATE, MVT::v2i8, Custom);
816 setOperationAction(ISD::TRUNCATE, MVT::v4i16, Custom);
817 setOperationAction(ISD::TRUNCATE, MVT::v2i16, Custom);
818
819 setOperationAction(ISD::AND , MVT::v4i32, Legal);
820 setOperationAction(ISD::OR , MVT::v4i32, Legal);
821 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
822 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
823 setOperationAction(ISD::SELECT, MVT::v4i32,
824 Subtarget.useCRBits() ? Legal : Expand);
825 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
826 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::v4i32, Legal);
827 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::v4i32, Legal);
828 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v4i32, Legal);
829 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v4i32, Legal);
830 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
831 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
832 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
833 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
834 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
835 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
836 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
837 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
838
839 // Without hasP8Altivec set, v2i64 SMAX isn't available.
840 // But ABS custom lowering requires SMAX support.
841 if (!Subtarget.hasP8Altivec())
842 setOperationAction(ISD::ABS, MVT::v2i64, Expand);
843
844 // Custom lowering ROTL v1i128 to VECTOR_SHUFFLE v16i8.
845 setOperationAction(ISD::ROTL, MVT::v1i128, Custom);
846 // With hasAltivec set, we can lower ISD::ROTL to vrl(b|h|w).
847 if (Subtarget.hasAltivec())
848 for (auto VT : {MVT::v4i32, MVT::v8i16, MVT::v16i8})
849 setOperationAction(ISD::ROTL, VT, Legal);
850 // With hasP8Altivec set, we can lower ISD::ROTL to vrld.
851 if (Subtarget.hasP8Altivec())
852 setOperationAction(ISD::ROTL, MVT::v2i64, Legal);
853
854 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
855 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass);
856 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass);
857 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass);
858
859 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
860 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
861
862 if (Subtarget.hasVSX()) {
863 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
864 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
865 }
866
867 if (Subtarget.hasP8Altivec())
868 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
869 else
870 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
871
872 if (Subtarget.isISA3_1()) {
873 setOperationAction(ISD::MUL, MVT::v2i64, Legal);
874 setOperationAction(ISD::MULHS, MVT::v2i64, Legal);
875 setOperationAction(ISD::MULHU, MVT::v2i64, Legal);
876 setOperationAction(ISD::MULHS, MVT::v4i32, Legal);
877 setOperationAction(ISD::MULHU, MVT::v4i32, Legal);
878 setOperationAction(ISD::UDIV, MVT::v2i64, Legal);
879 setOperationAction(ISD::SDIV, MVT::v2i64, Legal);
880 setOperationAction(ISD::UDIV, MVT::v4i32, Legal);
881 setOperationAction(ISD::SDIV, MVT::v4i32, Legal);
882 setOperationAction(ISD::UREM, MVT::v2i64, Legal);
883 setOperationAction(ISD::SREM, MVT::v2i64, Legal);
884 setOperationAction(ISD::UREM, MVT::v4i32, Legal);
885 setOperationAction(ISD::SREM, MVT::v4i32, Legal);
886 setOperationAction(ISD::UREM, MVT::v1i128, Legal);
887 setOperationAction(ISD::SREM, MVT::v1i128, Legal);
888 setOperationAction(ISD::UDIV, MVT::v1i128, Legal);
889 setOperationAction(ISD::SDIV, MVT::v1i128, Legal);
890 setOperationAction(ISD::ROTL, MVT::v1i128, Legal);
891 }
892
893 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
894 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
895
896 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
897 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
898
899 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
900 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
901 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
902 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
903
904 // Altivec does not contain unordered floating-point compare instructions
905 setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand);
906 setCondCodeAction(ISD::SETUEQ, MVT::v4f32, Expand);
907 setCondCodeAction(ISD::SETO, MVT::v4f32, Expand);
908 setCondCodeAction(ISD::SETONE, MVT::v4f32, Expand);
909
910 if (Subtarget.hasVSX()) {
911 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal);
912 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal);
913 if (Subtarget.hasP8Vector()) {
914 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Legal);
915 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Legal);
916 }
917 if (Subtarget.hasDirectMove() && isPPC64) {
918 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Legal);
919 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Legal);
920 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Legal);
921 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i64, Legal);
922 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Legal);
923 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Legal);
924 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Legal);
925 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal);
926 }
927 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal);
928
929 // The nearbyint variants are not allowed to raise the inexact exception
930 // so we can only code-gen them with unsafe math.
931 if (TM.Options.UnsafeFPMath) {
932 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
933 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
934 }
935
936 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
937 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
938 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
939 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
940 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
941 setOperationAction(ISD::FROUND, MVT::v2f64, Legal);
942 setOperationAction(ISD::FROUND, MVT::f64, Legal);
943 setOperationAction(ISD::FRINT, MVT::f64, Legal);
944
945 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
946 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
947 setOperationAction(ISD::FROUND, MVT::v4f32, Legal);
948 setOperationAction(ISD::FROUND, MVT::f32, Legal);
949 setOperationAction(ISD::FRINT, MVT::f32, Legal);
950
951 setOperationAction(ISD::MUL, MVT::v2f64, Legal);
952 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
953
954 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
955 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
956
957 // Share the Altivec comparison restrictions.
958 setCondCodeAction(ISD::SETUO, MVT::v2f64, Expand);
959 setCondCodeAction(ISD::SETUEQ, MVT::v2f64, Expand);
960 setCondCodeAction(ISD::SETO, MVT::v2f64, Expand);
961 setCondCodeAction(ISD::SETONE, MVT::v2f64, Expand);
962
963 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
964 setOperationAction(ISD::STORE, MVT::v2f64, Legal);
965
966 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Legal);
967
968 if (Subtarget.hasP8Vector())
969 addRegisterClass(MVT::f32, &PPC::VSSRCRegClass);
970
971 addRegisterClass(MVT::f64, &PPC::VSFRCRegClass);
972
973 addRegisterClass(MVT::v4i32, &PPC::VSRCRegClass);
974 addRegisterClass(MVT::v4f32, &PPC::VSRCRegClass);
975 addRegisterClass(MVT::v2f64, &PPC::VSRCRegClass);
976
977 if (Subtarget.hasP8Altivec()) {
978 setOperationAction(ISD::SHL, MVT::v2i64, Legal);
979 setOperationAction(ISD::SRA, MVT::v2i64, Legal);
980 setOperationAction(ISD::SRL, MVT::v2i64, Legal);
981
982 // 128 bit shifts can be accomplished via 3 instructions for SHL and
983 // SRL, but not for SRA because of the instructions available:
984 // VS{RL} and VS{RL}O. However due to direct move costs, it's not worth
985 // doing
986 setOperationAction(ISD::SHL, MVT::v1i128, Expand);
987 setOperationAction(ISD::SRL, MVT::v1i128, Expand);
988 setOperationAction(ISD::SRA, MVT::v1i128, Expand);
989
990 setOperationAction(ISD::SETCC, MVT::v2i64, Legal);
991 }
992 else {
993 setOperationAction(ISD::SHL, MVT::v2i64, Expand);
994 setOperationAction(ISD::SRA, MVT::v2i64, Expand);
995 setOperationAction(ISD::SRL, MVT::v2i64, Expand);
996
997 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
998
999 // VSX v2i64 only supports non-arithmetic operations.
1000 setOperationAction(ISD::ADD, MVT::v2i64, Expand);
1001 setOperationAction(ISD::SUB, MVT::v2i64, Expand);
1002 }
1003
1004 if (Subtarget.isISA3_1())
1005 setOperationAction(ISD::SETCC, MVT::v1i128, Legal);
1006 else
1007 setOperationAction(ISD::SETCC, MVT::v1i128, Expand);
1008
1009 setOperationAction(ISD::LOAD, MVT::v2i64, Promote);
1010 AddPromotedToType (ISD::LOAD, MVT::v2i64, MVT::v2f64);
1011 setOperationAction(ISD::STORE, MVT::v2i64, Promote);
1012 AddPromotedToType (ISD::STORE, MVT::v2i64, MVT::v2f64);
1013
1014 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Legal);
1015
1016 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v2i64, Legal);
1017 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v2i64, Legal);
1018 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::v2i64, Legal);
1019 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::v2i64, Legal);
1020 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
1021 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
1022 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
1023 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
1024
1025 // Custom handling for partial vectors of integers converted to
1026 // floating point. We already have optimal handling for v2i32 through
1027 // the DAG combine, so those aren't necessary.
1028 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v2i8, Custom);
1029 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v4i8, Custom);
1030 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v2i16, Custom);
1031 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v4i16, Custom);
1032 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v2i8, Custom);
1033 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v4i8, Custom);
1034 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v2i16, Custom);
1035 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v4i16, Custom);
1036 setOperationAction(ISD::UINT_TO_FP, MVT::v2i8, Custom);
1037 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1038 setOperationAction(ISD::UINT_TO_FP, MVT::v2i16, Custom);
1039 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1040 setOperationAction(ISD::SINT_TO_FP, MVT::v2i8, Custom);
1041 setOperationAction(ISD::SINT_TO_FP, MVT::v4i8, Custom);
1042 setOperationAction(ISD::SINT_TO_FP, MVT::v2i16, Custom);
1043 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom);
1044
1045 setOperationAction(ISD::FNEG, MVT::v4f32, Legal);
1046 setOperationAction(ISD::FNEG, MVT::v2f64, Legal);
1047 setOperationAction(ISD::FABS, MVT::v4f32, Legal);
1048 setOperationAction(ISD::FABS, MVT::v2f64, Legal);
1049 setOperationAction(ISD::FCOPYSIGN, MVT::v4f32, Legal);
1050 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Legal);
1051
1052 if (Subtarget.hasDirectMove())
1053 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
1054 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
1055
1056 // Handle constrained floating-point operations of vector.
1057 // The predictor is `hasVSX` because altivec instruction has
1058 // no exception but VSX vector instruction has.
1059 setOperationAction(ISD::STRICT_FADD, MVT::v4f32, Legal);
1060 setOperationAction(ISD::STRICT_FSUB, MVT::v4f32, Legal);
1061 setOperationAction(ISD::STRICT_FMUL, MVT::v4f32, Legal);
1062 setOperationAction(ISD::STRICT_FDIV, MVT::v4f32, Legal);
1063 setOperationAction(ISD::STRICT_FMA, MVT::v4f32, Legal);
1064 setOperationAction(ISD::STRICT_FSQRT, MVT::v4f32, Legal);
1065 setOperationAction(ISD::STRICT_FMAXNUM, MVT::v4f32, Legal);
1066 setOperationAction(ISD::STRICT_FMINNUM, MVT::v4f32, Legal);
1067 setOperationAction(ISD::STRICT_FRINT, MVT::v4f32, Legal);
1068 setOperationAction(ISD::STRICT_FFLOOR, MVT::v4f32, Legal);
1069 setOperationAction(ISD::STRICT_FCEIL, MVT::v4f32, Legal);
1070 setOperationAction(ISD::STRICT_FTRUNC, MVT::v4f32, Legal);
1071 setOperationAction(ISD::STRICT_FROUND, MVT::v4f32, Legal);
1072
1073 setOperationAction(ISD::STRICT_FADD, MVT::v2f64, Legal);
1074 setOperationAction(ISD::STRICT_FSUB, MVT::v2f64, Legal);
1075 setOperationAction(ISD::STRICT_FMUL, MVT::v2f64, Legal);
1076 setOperationAction(ISD::STRICT_FDIV, MVT::v2f64, Legal);
1077 setOperationAction(ISD::STRICT_FMA, MVT::v2f64, Legal);
1078 setOperationAction(ISD::STRICT_FSQRT, MVT::v2f64, Legal);
1079 setOperationAction(ISD::STRICT_FMAXNUM, MVT::v2f64, Legal);
1080 setOperationAction(ISD::STRICT_FMINNUM, MVT::v2f64, Legal);
1081 setOperationAction(ISD::STRICT_FRINT, MVT::v2f64, Legal);
1082 setOperationAction(ISD::STRICT_FFLOOR, MVT::v2f64, Legal);
1083 setOperationAction(ISD::STRICT_FCEIL, MVT::v2f64, Legal);
1084 setOperationAction(ISD::STRICT_FTRUNC, MVT::v2f64, Legal);
1085 setOperationAction(ISD::STRICT_FROUND, MVT::v2f64, Legal);
1086
1087 addRegisterClass(MVT::v2i64, &PPC::VSRCRegClass);
1088 }
1089
1090 if (Subtarget.hasP8Altivec()) {
1091 addRegisterClass(MVT::v2i64, &PPC::VRRCRegClass);
1092 addRegisterClass(MVT::v1i128, &PPC::VRRCRegClass);
1093 }
1094
1095 if (Subtarget.hasP9Vector()) {
1096 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1097 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1098
1099 // 128 bit shifts can be accomplished via 3 instructions for SHL and
1100 // SRL, but not for SRA because of the instructions available:
1101 // VS{RL} and VS{RL}O.
1102 setOperationAction(ISD::SHL, MVT::v1i128, Legal);
1103 setOperationAction(ISD::SRL, MVT::v1i128, Legal);
1104 setOperationAction(ISD::SRA, MVT::v1i128, Expand);
1105
1106 addRegisterClass(MVT::f128, &PPC::VRRCRegClass);
1107 setOperationAction(ISD::FADD, MVT::f128, Legal);
1108 setOperationAction(ISD::FSUB, MVT::f128, Legal);
1109 setOperationAction(ISD::FDIV, MVT::f128, Legal);
1110 setOperationAction(ISD::FMUL, MVT::f128, Legal);
1111 setOperationAction(ISD::FP_EXTEND, MVT::f128, Legal);
1112 // No extending loads to f128 on PPC.
1113 for (MVT FPT : MVT::fp_valuetypes())
1114 setLoadExtAction(ISD::EXTLOAD, MVT::f128, FPT, Expand);
1115 setOperationAction(ISD::FMA, MVT::f128, Legal);
1116 setCondCodeAction(ISD::SETULT, MVT::f128, Expand);
1117 setCondCodeAction(ISD::SETUGT, MVT::f128, Expand);
1118 setCondCodeAction(ISD::SETUEQ, MVT::f128, Expand);
1119 setCondCodeAction(ISD::SETOGE, MVT::f128, Expand);
1120 setCondCodeAction(ISD::SETOLE, MVT::f128, Expand);
1121 setCondCodeAction(ISD::SETONE, MVT::f128, Expand);
1122
1123 setOperationAction(ISD::FTRUNC, MVT::f128, Legal);
1124 setOperationAction(ISD::FRINT, MVT::f128, Legal);
1125 setOperationAction(ISD::FFLOOR, MVT::f128, Legal);
1126 setOperationAction(ISD::FCEIL, MVT::f128, Legal);
1127 setOperationAction(ISD::FNEARBYINT, MVT::f128, Legal);
1128 setOperationAction(ISD::FROUND, MVT::f128, Legal);
1129
1130 setOperationAction(ISD::SELECT, MVT::f128, Expand);
1131 setOperationAction(ISD::FP_ROUND, MVT::f64, Legal);
1132 setOperationAction(ISD::FP_ROUND, MVT::f32, Legal);
1133 setTruncStoreAction(MVT::f128, MVT::f64, Expand);
1134 setTruncStoreAction(MVT::f128, MVT::f32, Expand);
1135 setOperationAction(ISD::BITCAST, MVT::i128, Custom);
1136 // No implementation for these ops for PowerPC.
1137 setOperationAction(ISD::FSIN, MVT::f128, Expand);
1138 setOperationAction(ISD::FCOS, MVT::f128, Expand);
1139 setOperationAction(ISD::FPOW, MVT::f128, Expand);
1140 setOperationAction(ISD::FPOWI, MVT::f128, Expand);
1141 setOperationAction(ISD::FREM, MVT::f128, Expand);
1142
1143 // Handle constrained floating-point operations of fp128
1144 setOperationAction(ISD::STRICT_FADD, MVT::f128, Legal);
1145 setOperationAction(ISD::STRICT_FSUB, MVT::f128, Legal);
1146 setOperationAction(ISD::STRICT_FMUL, MVT::f128, Legal);
1147 setOperationAction(ISD::STRICT_FDIV, MVT::f128, Legal);
1148 setOperationAction(ISD::STRICT_FMA, MVT::f128, Legal);
1149 setOperationAction(ISD::STRICT_FSQRT, MVT::f128, Legal);
1150 setOperationAction(ISD::STRICT_FP_EXTEND, MVT::f128, Legal);
1151 setOperationAction(ISD::STRICT_FP_ROUND, MVT::f64, Legal);
1152 setOperationAction(ISD::STRICT_FP_ROUND, MVT::f32, Legal);
1153 setOperationAction(ISD::STRICT_FRINT, MVT::f128, Legal);
1154 setOperationAction(ISD::STRICT_FNEARBYINT, MVT::f128, Legal);
1155 setOperationAction(ISD::STRICT_FFLOOR, MVT::f128, Legal);
1156 setOperationAction(ISD::STRICT_FCEIL, MVT::f128, Legal);
1157 setOperationAction(ISD::STRICT_FTRUNC, MVT::f128, Legal);
1158 setOperationAction(ISD::STRICT_FROUND, MVT::f128, Legal);
1159 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1160 setOperationAction(ISD::BSWAP, MVT::v8i16, Legal);
1161 setOperationAction(ISD::BSWAP, MVT::v4i32, Legal);
1162 setOperationAction(ISD::BSWAP, MVT::v2i64, Legal);
1163 setOperationAction(ISD::BSWAP, MVT::v1i128, Legal);
1164 }
1165
1166 if (Subtarget.hasP9Altivec()) {
1167 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1168 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1169
1170 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Legal);
1171 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Legal);
1172 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i32, Legal);
1173 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Legal);
1174 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Legal);
1175 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Legal);
1176 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i64, Legal);
1177 }
1178 }
1179
1180 if (Subtarget.pairedVectorMemops()) {
1181 addRegisterClass(MVT::v256i1, &PPC::VSRpRCRegClass);
1182 setOperationAction(ISD::LOAD, MVT::v256i1, Custom);
1183 setOperationAction(ISD::STORE, MVT::v256i1, Custom);
1184 }
1185 if (Subtarget.hasMMA()) {
1186 addRegisterClass(MVT::v512i1, &PPC::UACCRCRegClass);
1187 setOperationAction(ISD::LOAD, MVT::v512i1, Custom);
1188 setOperationAction(ISD::STORE, MVT::v512i1, Custom);
1189 setOperationAction(ISD::BUILD_VECTOR, MVT::v512i1, Custom);
1190 }
1191
1192 if (Subtarget.has64BitSupport())
1193 setOperationAction(ISD::PREFETCH, MVT::Other, Legal);
1194
1195 if (Subtarget.isISA3_1())
1196 setOperationAction(ISD::SRA, MVT::v1i128, Legal);
1197
1198 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, isPPC64 ? Legal : Custom);
1199
1200 if (!isPPC64) {
1201 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
1202 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
1203 }
1204
1205 setBooleanContents(ZeroOrOneBooleanContent);
1206
1207 if (Subtarget.hasAltivec()) {
1208 // Altivec instructions set fields to all zeros or all ones.
1209 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
1210 }
1211
1212 if (!isPPC64) {
1213 // These libcalls are not available in 32-bit.
1214 setLibcallName(RTLIB::SHL_I128, nullptr);
1215 setLibcallName(RTLIB::SRL_I128, nullptr);
1216 setLibcallName(RTLIB::SRA_I128, nullptr);
1217 }
1218
1219 if (!isPPC64)
1220 setMaxAtomicSizeInBitsSupported(32);
1221
1222 setStackPointerRegisterToSaveRestore(isPPC64 ? PPC::X1 : PPC::R1);
1223
1224 // We have target-specific dag combine patterns for the following nodes:
1225 setTargetDAGCombine(ISD::ADD);
1226 setTargetDAGCombine(ISD::SHL);
1227 setTargetDAGCombine(ISD::SRA);
1228 setTargetDAGCombine(ISD::SRL);
1229 setTargetDAGCombine(ISD::MUL);
1230 setTargetDAGCombine(ISD::FMA);
1231 setTargetDAGCombine(ISD::SINT_TO_FP);
1232 setTargetDAGCombine(ISD::BUILD_VECTOR);
1233 if (Subtarget.hasFPCVT())
1234 setTargetDAGCombine(ISD::UINT_TO_FP);
1235 setTargetDAGCombine(ISD::LOAD);
1236 setTargetDAGCombine(ISD::STORE);
1237 setTargetDAGCombine(ISD::BR_CC);
1238 if (Subtarget.useCRBits())
1239 setTargetDAGCombine(ISD::BRCOND);
1240 setTargetDAGCombine(ISD::BSWAP);
1241 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1242 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
1243 setTargetDAGCombine(ISD::INTRINSIC_VOID);
1244
1245 setTargetDAGCombine(ISD::SIGN_EXTEND);
1246 setTargetDAGCombine(ISD::ZERO_EXTEND);
1247 setTargetDAGCombine(ISD::ANY_EXTEND);
1248
1249 setTargetDAGCombine(ISD::TRUNCATE);
1250 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1251
1252
1253 if (Subtarget.useCRBits()) {
1254 setTargetDAGCombine(ISD::TRUNCATE);
1255 setTargetDAGCombine(ISD::SETCC);
1256 setTargetDAGCombine(ISD::SELECT_CC);
1257 }
1258
1259 if (Subtarget.hasP9Altivec()) {
1260 setTargetDAGCombine(ISD::ABS);
1261 setTargetDAGCombine(ISD::VSELECT);
1262 }
1263
1264 setLibcallName(RTLIB::LOG_F128, "logf128");
1265 setLibcallName(RTLIB::LOG2_F128, "log2f128");
1266 setLibcallName(RTLIB::LOG10_F128, "log10f128");
1267 setLibcallName(RTLIB::EXP_F128, "expf128");
1268 setLibcallName(RTLIB::EXP2_F128, "exp2f128");
1269 setLibcallName(RTLIB::SIN_F128, "sinf128");
1270 setLibcallName(RTLIB::COS_F128, "cosf128");
1271 setLibcallName(RTLIB::POW_F128, "powf128");
1272 setLibcallName(RTLIB::FMIN_F128, "fminf128");
1273 setLibcallName(RTLIB::FMAX_F128, "fmaxf128");
1274 setLibcallName(RTLIB::POWI_F128, "__powikf2");
1275 setLibcallName(RTLIB::REM_F128, "fmodf128");
1276
1277 // With 32 condition bits, we don't need to sink (and duplicate) compares
1278 // aggressively in CodeGenPrep.
1279 if (Subtarget.useCRBits()) {
1280 setHasMultipleConditionRegisters();
1281 setJumpIsExpensive();
1282 }
1283
1284 setMinFunctionAlignment(Align(4));
1285
1286 switch (Subtarget.getCPUDirective()) {
1287 default: break;
1288 case PPC::DIR_970:
1289 case PPC::DIR_A2:
1290 case PPC::DIR_E500:
1291 case PPC::DIR_E500mc:
1292 case PPC::DIR_E5500:
1293 case PPC::DIR_PWR4:
1294 case PPC::DIR_PWR5:
1295 case PPC::DIR_PWR5X:
1296 case PPC::DIR_PWR6:
1297 case PPC::DIR_PWR6X:
1298 case PPC::DIR_PWR7:
1299 case PPC::DIR_PWR8:
1300 case PPC::DIR_PWR9:
1301 case PPC::DIR_PWR10:
1302 case PPC::DIR_PWR_FUTURE:
1303 setPrefLoopAlignment(Align(16));
1304 setPrefFunctionAlignment(Align(16));
1305 break;
1306 }
1307
1308 if (Subtarget.enableMachineScheduler())
1309 setSchedulingPreference(Sched::Source);
1310 else
1311 setSchedulingPreference(Sched::Hybrid);
1312
1313 computeRegisterProperties(STI.getRegisterInfo());
1314
1315 // The Freescale cores do better with aggressive inlining of memcpy and
1316 // friends. GCC uses same threshold of 128 bytes (= 32 word stores).
1317 if (Subtarget.getCPUDirective() == PPC::DIR_E500mc ||
1318 Subtarget.getCPUDirective() == PPC::DIR_E5500) {
1319 MaxStoresPerMemset = 32;
1320 MaxStoresPerMemsetOptSize = 16;
1321 MaxStoresPerMemcpy = 32;
1322 MaxStoresPerMemcpyOptSize = 8;
1323 MaxStoresPerMemmove = 32;
1324 MaxStoresPerMemmoveOptSize = 8;
1325 } else if (Subtarget.getCPUDirective() == PPC::DIR_A2) {
1326 // The A2 also benefits from (very) aggressive inlining of memcpy and
1327 // friends. The overhead of a the function call, even when warm, can be
1328 // over one hundred cycles.
1329 MaxStoresPerMemset = 128;
1330 MaxStoresPerMemcpy = 128;
1331 MaxStoresPerMemmove = 128;
1332 MaxLoadsPerMemcmp = 128;
1333 } else {
1334 MaxLoadsPerMemcmp = 8;
1335 MaxLoadsPerMemcmpOptSize = 4;
1336 }
1337
1338 IsStrictFPEnabled = true;
1339
1340 // Let the subtarget (CPU) decide if a predictable select is more expensive
1341 // than the corresponding branch. This information is used in CGP to decide
1342 // when to convert selects into branches.
1343 PredictableSelectIsExpensive = Subtarget.isPredictableSelectIsExpensive();
1344}
1345
1346/// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1347/// the desired ByVal argument alignment.
1348static void getMaxByValAlign(Type *Ty, Align &MaxAlign, Align MaxMaxAlign) {
1349 if (MaxAlign == MaxMaxAlign)
1350 return;
1351 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1352 if (MaxMaxAlign >= 32 &&
1353 VTy->getPrimitiveSizeInBits().getFixedSize() >= 256)
1354 MaxAlign = Align(32);
1355 else if (VTy->getPrimitiveSizeInBits().getFixedSize() >= 128 &&
1356 MaxAlign < 16)
1357 MaxAlign = Align(16);
1358 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1359 Align EltAlign;
1360 getMaxByValAlign(ATy->getElementType(), EltAlign, MaxMaxAlign);
1361 if (EltAlign > MaxAlign)
1362 MaxAlign = EltAlign;
1363 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1364 for (auto *EltTy : STy->elements()) {
1365 Align EltAlign;
1366 getMaxByValAlign(EltTy, EltAlign, MaxMaxAlign);
1367 if (EltAlign > MaxAlign)
1368 MaxAlign = EltAlign;
1369 if (MaxAlign == MaxMaxAlign)
1370 break;
1371 }
1372 }
1373}
1374
1375/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1376/// function arguments in the caller parameter area.
1377unsigned PPCTargetLowering::getByValTypeAlignment(Type *Ty,
1378 const DataLayout &DL) const {
1379 // 16byte and wider vectors are passed on 16byte boundary.
1380 // The rest is 8 on PPC64 and 4 on PPC32 boundary.
1381 Align Alignment = Subtarget.isPPC64() ? Align(8) : Align(4);
1382 if (Subtarget.hasAltivec())
1383 getMaxByValAlign(Ty, Alignment, Align(16));
1384 return Alignment.value();
1385}
1386
1387bool PPCTargetLowering::useSoftFloat() const {
1388 return Subtarget.useSoftFloat();
1389}
1390
1391bool PPCTargetLowering::hasSPE() const {
1392 return Subtarget.hasSPE();
1393}
1394
1395bool PPCTargetLowering::preferIncOfAddToSubOfNot(EVT VT) const {
1396 return VT.isScalarInteger();
1397}
1398
1399const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
1400 switch ((PPCISD::NodeType)Opcode) {
1401 case PPCISD::FIRST_NUMBER: break;
1402 case PPCISD::FSEL: return "PPCISD::FSEL";
1403 case PPCISD::XSMAXCDP: return "PPCISD::XSMAXCDP";
1404 case PPCISD::XSMINCDP: return "PPCISD::XSMINCDP";
1405 case PPCISD::FCFID: return "PPCISD::FCFID";
1406 case PPCISD::FCFIDU: return "PPCISD::FCFIDU";
1407 case PPCISD::FCFIDS: return "PPCISD::FCFIDS";
1408 case PPCISD::FCFIDUS: return "PPCISD::FCFIDUS";
1409 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
1410 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
1411 case PPCISD::FCTIDUZ: return "PPCISD::FCTIDUZ";
1412 case PPCISD::FCTIWUZ: return "PPCISD::FCTIWUZ";
1413 case PPCISD::FP_TO_UINT_IN_VSR:
1414 return "PPCISD::FP_TO_UINT_IN_VSR,";
1415 case PPCISD::FP_TO_SINT_IN_VSR:
1416 return "PPCISD::FP_TO_SINT_IN_VSR";
1417 case PPCISD::FRE: return "PPCISD::FRE";
1418 case PPCISD::FRSQRTE: return "PPCISD::FRSQRTE";
1419 case PPCISD::STFIWX: return "PPCISD::STFIWX";
1420 case PPCISD::VPERM: return "PPCISD::VPERM";
1421 case PPCISD::XXSPLT: return "PPCISD::XXSPLT";
1422 case PPCISD::XXSPLTI_SP_TO_DP:
1423 return "PPCISD::XXSPLTI_SP_TO_DP";
1424 case PPCISD::XXSPLTI32DX:
1425 return "PPCISD::XXSPLTI32DX";
1426 case PPCISD::VECINSERT: return "PPCISD::VECINSERT";
1427 case PPCISD::XXPERMDI: return "PPCISD::XXPERMDI";
1428 case PPCISD::VECSHL: return "PPCISD::VECSHL";
1429 case PPCISD::CMPB: return "PPCISD::CMPB";
1430 case PPCISD::Hi: return "PPCISD::Hi";
1431 case PPCISD::Lo: return "PPCISD::Lo";
1432 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY";
1433 case PPCISD::ATOMIC_CMP_SWAP_8: return "PPCISD::ATOMIC_CMP_SWAP_8";
1434 case PPCISD::ATOMIC_CMP_SWAP_16: return "PPCISD::ATOMIC_CMP_SWAP_16";
1435 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
1436 case PPCISD::DYNAREAOFFSET: return "PPCISD::DYNAREAOFFSET";
1437 case PPCISD::PROBED_ALLOCA: return "PPCISD::PROBED_ALLOCA";
1438 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
1439 case PPCISD::SRL: return "PPCISD::SRL";
1440 case PPCISD::SRA: return "PPCISD::SRA";
1441 case PPCISD::SHL: return "PPCISD::SHL";
1442 case PPCISD::SRA_ADDZE: return "PPCISD::SRA_ADDZE";
1443 case PPCISD::CALL: return "PPCISD::CALL";
1444 case PPCISD::CALL_NOP: return "PPCISD::CALL_NOP";
1445 case PPCISD::CALL_NOTOC: return "PPCISD::CALL_NOTOC";
1446 case PPCISD::MTCTR: return "PPCISD::MTCTR";
1447 case PPCISD::BCTRL: return "PPCISD::BCTRL";
1448 case PPCISD::BCTRL_LOAD_TOC: return "PPCISD::BCTRL_LOAD_TOC";
1449 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
1450 case PPCISD::READ_TIME_BASE: return "PPCISD::READ_TIME_BASE";
1451 case PPCISD::EH_SJLJ_SETJMP: return "PPCISD::EH_SJLJ_SETJMP";
1452 case PPCISD::EH_SJLJ_LONGJMP: return "PPCISD::EH_SJLJ_LONGJMP";
1453 case PPCISD::MFOCRF: return "PPCISD::MFOCRF";
1454 case PPCISD::MFVSR: return "PPCISD::MFVSR";
1455 case PPCISD::MTVSRA: return "PPCISD::MTVSRA";
1456 case PPCISD::MTVSRZ: return "PPCISD::MTVSRZ";
1457 case PPCISD::SINT_VEC_TO_FP: return "PPCISD::SINT_VEC_TO_FP";
1458 case PPCISD::UINT_VEC_TO_FP: return "PPCISD::UINT_VEC_TO_FP";
1459 case PPCISD::SCALAR_TO_VECTOR_PERMUTED:
1460 return "PPCISD::SCALAR_TO_VECTOR_PERMUTED";
1461 case PPCISD::ANDI_rec_1_EQ_BIT:
1462 return "PPCISD::ANDI_rec_1_EQ_BIT";
1463 case PPCISD::ANDI_rec_1_GT_BIT:
1464 return "PPCISD::ANDI_rec_1_GT_BIT";
1465 case PPCISD::VCMP: return "PPCISD::VCMP";
1466 case PPCISD::VCMP_rec: return "PPCISD::VCMP_rec";
1467 case PPCISD::LBRX: return "PPCISD::LBRX";
1468 case PPCISD::STBRX: return "PPCISD::STBRX";
1469 case PPCISD::LFIWAX: return "PPCISD::LFIWAX";
1470 case PPCISD::LFIWZX: return "PPCISD::LFIWZX";
1471 case PPCISD::LXSIZX: return "PPCISD::LXSIZX";
1472 case PPCISD::STXSIX: return "PPCISD::STXSIX";
1473 case PPCISD::VEXTS: return "PPCISD::VEXTS";
1474 case PPCISD::LXVD2X: return "PPCISD::LXVD2X";
1475 case PPCISD::STXVD2X: return "PPCISD::STXVD2X";
1476 case PPCISD::LOAD_VEC_BE: return "PPCISD::LOAD_VEC_BE";
1477 case PPCISD::STORE_VEC_BE: return "PPCISD::STORE_VEC_BE";
1478 case PPCISD::ST_VSR_SCAL_INT:
1479 return "PPCISD::ST_VSR_SCAL_INT";
1480 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
1481 case PPCISD::BDNZ: return "PPCISD::BDNZ";
1482 case PPCISD::BDZ: return "PPCISD::BDZ";
1483 case PPCISD::MFFS: return "PPCISD::MFFS";
1484 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
1485 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
1486 case PPCISD::CR6SET: return "PPCISD::CR6SET";
1487 case PPCISD::CR6UNSET: return "PPCISD::CR6UNSET";
1488 case PPCISD::PPC32_GOT: return "PPCISD::PPC32_GOT";
1489 case PPCISD::PPC32_PICGOT: return "PPCISD::PPC32_PICGOT";
1490 case PPCISD::ADDIS_GOT_TPREL_HA: return "PPCISD::ADDIS_GOT_TPREL_HA";
1491 case PPCISD::LD_GOT_TPREL_L: return "PPCISD::LD_GOT_TPREL_L";
1492 case PPCISD::ADD_TLS: return "PPCISD::ADD_TLS";
1493 case PPCISD::ADDIS_TLSGD_HA: return "PPCISD::ADDIS_TLSGD_HA";
1494 case PPCISD::ADDI_TLSGD_L: return "PPCISD::ADDI_TLSGD_L";
1495 case PPCISD::GET_TLS_ADDR: return "PPCISD::GET_TLS_ADDR";
1496 case PPCISD::ADDI_TLSGD_L_ADDR: return "PPCISD::ADDI_TLSGD_L_ADDR";
1497 case PPCISD::ADDIS_TLSLD_HA: return "PPCISD::ADDIS_TLSLD_HA";
1498 case PPCISD::ADDI_TLSLD_L: return "PPCISD::ADDI_TLSLD_L";
1499 case PPCISD::GET_TLSLD_ADDR: return "PPCISD::GET_TLSLD_ADDR";
1500 case PPCISD::ADDI_TLSLD_L_ADDR: return "PPCISD::ADDI_TLSLD_L_ADDR";
1501 case PPCISD::ADDIS_DTPREL_HA: return "PPCISD::ADDIS_DTPREL_HA";
1502 case PPCISD::ADDI_DTPREL_L: return "PPCISD::ADDI_DTPREL_L";
1503 case PPCISD::PADDI_DTPREL:
1504 return "PPCISD::PADDI_DTPREL";
1505 case PPCISD::VADD_SPLAT: return "PPCISD::VADD_SPLAT";
1506 case PPCISD::SC: return "PPCISD::SC";
1507 case PPCISD::CLRBHRB: return "PPCISD::CLRBHRB";
1508 case PPCISD::MFBHRBE: return "PPCISD::MFBHRBE";
1509 case PPCISD::RFEBB: return "PPCISD::RFEBB";
1510 case PPCISD::XXSWAPD: return "PPCISD::XXSWAPD";
1511 case PPCISD::SWAP_NO_CHAIN: return "PPCISD::SWAP_NO_CHAIN";
1512 case PPCISD::VABSD: return "PPCISD::VABSD";
1513 case PPCISD::BUILD_FP128: return "PPCISD::BUILD_FP128";
1514 case PPCISD::BUILD_SPE64: return "PPCISD::BUILD_SPE64";
1515 case PPCISD::EXTRACT_SPE: return "PPCISD::EXTRACT_SPE";
1516 case PPCISD::EXTSWSLI: return "PPCISD::EXTSWSLI";
1517 case PPCISD::LD_VSX_LH: return "PPCISD::LD_VSX_LH";
1518 case PPCISD::FP_EXTEND_HALF: return "PPCISD::FP_EXTEND_HALF";
1519 case PPCISD::MAT_PCREL_ADDR: return "PPCISD::MAT_PCREL_ADDR";
1520 case PPCISD::TLS_DYNAMIC_MAT_PCREL_ADDR:
1521 return "PPCISD::TLS_DYNAMIC_MAT_PCREL_ADDR";
1522 case PPCISD::TLS_LOCAL_EXEC_MAT_ADDR:
1523 return "PPCISD::TLS_LOCAL_EXEC_MAT_ADDR";
1524 case PPCISD::ACC_BUILD: return "PPCISD::ACC_BUILD";
1525 case PPCISD::PAIR_BUILD: return "PPCISD::PAIR_BUILD";
1526 case PPCISD::EXTRACT_VSX_REG: return "PPCISD::EXTRACT_VSX_REG";
1527 case PPCISD::XXMFACC: return "PPCISD::XXMFACC";
1528 case PPCISD::LD_SPLAT: return "PPCISD::LD_SPLAT";
1529 case PPCISD::FNMSUB: return "PPCISD::FNMSUB";
1530 case PPCISD::STRICT_FADDRTZ:
1531 return "PPCISD::STRICT_FADDRTZ";
1532 case PPCISD::STRICT_FCTIDZ:
1533 return "PPCISD::STRICT_FCTIDZ";
1534 case PPCISD::STRICT_FCTIWZ:
1535 return "PPCISD::STRICT_FCTIWZ";
1536 case PPCISD::STRICT_FCTIDUZ:
1537 return "PPCISD::STRICT_FCTIDUZ";
1538 case PPCISD::STRICT_FCTIWUZ:
1539 return "PPCISD::STRICT_FCTIWUZ";
1540 case PPCISD::STRICT_FCFID:
1541 return "PPCISD::STRICT_FCFID";
1542 case PPCISD::STRICT_FCFIDU:
1543 return "PPCISD::STRICT_FCFIDU";
1544 case PPCISD::STRICT_FCFIDS:
1545 return "PPCISD::STRICT_FCFIDS";
1546 case PPCISD::STRICT_FCFIDUS:
1547 return "PPCISD::STRICT_FCFIDUS";
1548 case PPCISD::LXVRZX: return "PPCISD::LXVRZX";
1549 }
1550 return nullptr;
1551}
1552
1553EVT PPCTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &C,
1554 EVT VT) const {
1555 if (!VT.isVector())
1556 return Subtarget.useCRBits() ? MVT::i1 : MVT::i32;
1557
1558 return VT.changeVectorElementTypeToInteger();
1559}
1560
1561bool PPCTargetLowering::enableAggressiveFMAFusion(EVT VT) const {
1562 assert(VT.isFloatingPoint() && "Non-floating-point FMA?")((VT.isFloatingPoint() && "Non-floating-point FMA?") ?
static_cast<void> (0) : __assert_fail ("VT.isFloatingPoint() && \"Non-floating-point FMA?\""
, "/build/llvm-toolchain-snapshot-12~++20201124111112+7b5254223ac/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 1562, __PRETTY_FUNCTION__))
;
1563 return true;
1564}
1565
1566//===----------------------------------------------------------------------===//
1567// Node matching predicates, for use by the tblgen matching code.
1568//===----------------------------------------------------------------------===//
1569
1570/// isFloatingPointZero - Return true if this is 0.0 or -0.0.
1571static bool isFloatingPointZero(SDValue Op) {
1572 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
1573 return CFP->getValueAPF().isZero();
1574 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
1575 // Maybe this has already been legalized into the constant pool?
1576 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
1577 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
1578 return CFP->getValueAPF().isZero();
1579 }
1580 return false;
1581}
1582
1583/// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
1584/// true if Op is undef or if it matches the specified value.
1585static bool isConstantOrUndef(int Op, int Val) {
1586 return Op < 0 || Op == Val;
1587}
1588
1589/// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
1590/// VPKUHUM instruction.
1591/// The ShuffleKind distinguishes between big-endian operations with
1592/// two different inputs (0), either-endian operations with two identical
1593/// inputs (1), and little-endian operations with two different inputs (2).
1594/// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
1595bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
1596 SelectionDAG &DAG) {
1597 bool IsLE = DAG.getDataLayout().isLittleEndian();
1598 if (ShuffleKind == 0) {
1599 if (IsLE)
1600 return false;
1601 for (unsigned i = 0; i != 16; ++i)
1602 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1))
1603 return false;
1604 } else if (ShuffleKind == 2) {
1605 if (!IsLE)
1606 return false;
1607 for (unsigned i = 0; i != 16; ++i)
1608 if (!isConstantOrUndef(N->getMaskElt(i), i*2))
1609 return false;
1610 } else if (ShuffleKind == 1) {
1611 unsigned j = IsLE ? 0 : 1;
1612 for (unsigned i = 0; i != 8; ++i)
1613 if (!isConstantOrUndef(N->getMaskElt(i), i*2+j) ||
1614 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j))
1615 return false;
1616 }
1617 return true;
1618}
1619
1620/// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
1621/// VPKUWUM instruction.
1622/// The ShuffleKind distinguishes between big-endian operations with
1623/// two different inputs (0), either-endian operations with two identical
1624/// inputs (1), and little-endian operations with two different inputs (2).
1625/// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
1626bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
1627 SelectionDAG &DAG) {
1628 bool IsLE = DAG.getDataLayout().isLittleEndian();
1629 if (ShuffleKind == 0) {
1630 if (IsLE)
1631 return false;
1632 for (unsigned i = 0; i != 16; i += 2)
1633 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
1634 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3))
1635 return false;
1636 } else if (ShuffleKind == 2) {
1637 if (!IsLE)
1638 return false;
1639 for (unsigned i = 0; i != 16; i += 2)
1640 if (!isConstantOrUndef(N->getMaskElt(i ), i*2) ||
1641 !isConstantOrUndef(N->getMaskElt(i+1), i*2+1))
1642 return false;
1643 } else if (ShuffleKind == 1) {
1644 unsigned j = IsLE ? 0 : 2;
1645 for (unsigned i = 0; i != 8; i += 2)
1646 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
1647 !isConstantOrUndef(N->getMaskElt(i+1), i*2+j+1) ||
1648 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j) ||
1649 !isConstantOrUndef(N->getMaskElt(i+9), i*2+j+1))
1650 return false;
1651 }
1652 return true;
1653}
1654
1655/// isVPKUDUMShuffleMask - Return true if this is the shuffle mask for a
1656/// VPKUDUM instruction, AND the VPKUDUM instruction exists for the
1657/// current subtarget.
1658///
1659/// The ShuffleKind distinguishes between big-endian operations with
1660/// two different inputs (0), either-endian operations with two identical
1661/// inputs (1), and little-endian operations with two different inputs (2).
1662/// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
1663bool PPC::isVPKUDUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
1664 SelectionDAG &DAG) {
1665 const PPCSubtarget& Subtarget =
1666 static_cast<const PPCSubtarget&>(DAG.getSubtarget());
1667 if (!Subtarget.hasP8Vector())
1668 return false;
1669
1670 bool IsLE = DAG.getDataLayout().isLittleEndian();
1671 if (ShuffleKind == 0) {
1672 if (IsLE)
1673 return false;
1674 for (unsigned i = 0; i != 16; i += 4)
1675 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+4) ||
1676 !isConstantOrUndef(N->getMaskElt(i+1), i*2+5) ||
1677 !isConstantOrUndef(N->getMaskElt(i+2), i*2+6) ||
1678 !isConstantOrUndef(N->getMaskElt(i+3), i*2+7))
1679 return false;
1680 } else if (ShuffleKind == 2) {
1681 if (!IsLE)
1682 return false;
1683 for (unsigned i = 0; i != 16; i += 4)
1684 if (!isConstantOrUndef(N->getMaskElt(i ), i*2) ||
1685 !isConstantOrUndef(N->getMaskElt(i+1), i*2+1) ||
1686 !isConstantOrUndef(N->getMaskElt(i+2), i*2+2) ||
1687 !isConstantOrUndef(N->getMaskElt(i+3), i*2+3))
1688 return false;
1689 } else if (ShuffleKind == 1) {
1690 unsigned j = IsLE ? 0 : 4;
1691 for (unsigned i = 0; i != 8; i += 4)
1692 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
1693 !isConstantOrUndef(N->getMaskElt(i+1), i*2+j+1) ||
1694 !isConstantOrUndef(N->getMaskElt(i+2), i*2+j+2) ||
1695 !isConstantOrUndef(N->getMaskElt(i+3), i*2+j+3) ||
1696 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j) ||
1697 !isConstantOrUndef(N->getMaskElt(i+9), i*2+j+1) ||
1698 !isConstantOrUndef(N->getMaskElt(i+10), i*2+j+2) ||
1699 !isConstantOrUndef(N->getMaskElt(i+11), i*2+j+3))
1700 return false;
1701 }
1702 return true;
1703}
1704
1705/// isVMerge - Common function, used to match vmrg* shuffles.
1706///
1707static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
1708 unsigned LHSStart, unsigned RHSStart) {
1709 if (N->getValueType(0) != MVT::v16i8)
1710 return false;
1711 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&(((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
"Unsupported merge size!") ? static_cast<void> (0) : __assert_fail
("(UnitSize == 1 || UnitSize == 2 || UnitSize == 4) && \"Unsupported merge size!\""
, "/build/llvm-toolchain-snapshot-12~++20201124111112+7b5254223ac/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 1712, __PRETTY_FUNCTION__))
1712 "Unsupported merge size!")(((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
"Unsupported merge size!") ? static_cast<void> (0) : __assert_fail
("(UnitSize == 1 || UnitSize == 2 || UnitSize == 4) && \"Unsupported merge size!\""
, "/build/llvm-toolchain-snapshot-12~++20201124111112+7b5254223ac/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 1712, __PRETTY_FUNCTION__))
;
1713
1714 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
1715 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
1716 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j),
1717 LHSStart+j+i*UnitSize) ||
1718 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j),
1719 RHSStart+j+i*UnitSize))
1720 return false;
1721 }
1722 return true;
1723}
1724
1725/// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
1726/// a VMRGL* instruction with the specified unit size (1,2 or 4 bytes).
1727/// The ShuffleKind distinguishes between big-endian merges with two
1728/// different inputs (0), either-endian merges with two identical inputs (1),
1729/// and little-endian merges with two different inputs (2). For the latter,
1730/// the input operands are swapped (see PPCInstrAltivec.td).
1731bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
1732 unsigned ShuffleKind, SelectionDAG &DAG) {
1733 if (DAG.getDataLayout().isLittleEndian()) {
1734 if (ShuffleKind == 1) // unary
1735 return isVMerge(N, UnitSize, 0, 0);
1736 else if (ShuffleKind == 2) // swapped
1737 return isVMerge(N, UnitSize, 0, 16);
1738 else
1739 return false;
1740 } else {
1741 if (ShuffleKind == 1) // unary
1742 return isVMerge(N, UnitSize, 8, 8);
1743 else if (ShuffleKind == 0) // normal
1744 return isVMerge(N, UnitSize, 8, 24);
1745 else
1746 return false;
1747 }
1748}
1749
1750/// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
1751/// a VMRGH* instruction with the specified unit size (1,2 or 4 bytes).
1752/// The ShuffleKind distinguishes between big-endian merges with two
1753/// different inputs (0), either-endian merges with two identical inputs (1),
1754/// and little-endian merges with two different inputs (2). For the latter,
1755/// the input operands are swapped (see PPCInstrAltivec.td).
1756bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
1757 unsigned ShuffleKind, SelectionDAG &DAG) {
1758 if (DAG.getDataLayout().isLittleEndian()) {
1759 if (ShuffleKind == 1) // unary
1760 return isVMerge(N, UnitSize, 8, 8);
1761 else if (ShuffleKind == 2) // swapped
1762 return isVMerge(N, UnitSize, 8, 24);
1763 else
1764 return false;
1765 } else {
1766 if (ShuffleKind == 1) // unary
1767 return isVMerge(N, UnitSize, 0, 0);
1768 else if (ShuffleKind == 0) // normal
1769 return isVMerge(N, UnitSize, 0, 16);
1770 else
1771 return false;
1772 }
1773}
1774
1775/**
1776 * Common function used to match vmrgew and vmrgow shuffles
1777 *
1778 * The indexOffset determines whether to look for even or odd words in
1779 * the shuffle mask. This is based on the of the endianness of the target
1780 * machine.
1781 * - Little Endian:
1782 * - Use offset of 0 to check for odd elements
1783 * - Use offset of 4 to check for even elements
1784 * - Big Endian:
1785 * - Use offset of 0 to check for even elements
1786 * - Use offset of 4 to check for odd elements
1787 * A detailed description of the vector element ordering for little endian and
1788 * big endian can be found at
1789 * http://www.ibm.com/developerworks/library/l-ibm-xl-c-cpp-compiler/index.html
1790 * Targeting your applications - what little endian and big endian IBM XL C/C++
1791 * compiler differences mean to you
1792 *
1793 * The mask to the shuffle vector instruction specifies the indices of the
1794 * elements from the two input vectors to place in the result. The elements are
1795 * numbered in array-access order, starting with the first vector. These vectors
1796 * are always of type v16i8, thus each vector will contain 16 elements of size
1797 * 8. More info on the shuffle vector can be found in the
1798 * http://llvm.org/docs/LangRef.html#shufflevector-instruction
1799 * Language Reference.
1800 *
1801 * The RHSStartValue indicates whether the same input vectors are used (unary)
1802 * or two different input vectors are used, based on the following:
1803 * - If the instruction uses the same vector for both inputs, the range of the
1804 * indices will be 0 to 15. In this case, the RHSStart value passed should
1805 * be 0.
1806 * - If the instruction has two different vectors then the range of the
1807 * indices will be 0 to 31. In this case, the RHSStart value passed should
1808 * be 16 (indices 0-15 specify elements in the first vector while indices 16
1809 * to 31 specify elements in the second vector).
1810 *
1811 * \param[in] N The shuffle vector SD Node to analyze
1812 * \param[in] IndexOffset Specifies whether to look for even or odd elements
1813 * \param[in] RHSStartValue Specifies the starting index for the righthand input
1814 * vector to the shuffle_vector instruction
1815 * \return true iff this shuffle vector represents an even or odd word merge
1816 */
1817static bool isVMerge(ShuffleVectorSDNode *N, unsigned IndexOffset,
1818 unsigned RHSStartValue) {
1819 if (N->getValueType(0) != MVT::v16i8)
1820 return false;
1821
1822 for (unsigned i = 0; i < 2; ++i)
1823 for (unsigned j = 0; j < 4; ++j)
1824 if (!isConstantOrUndef(N->getMaskElt(i*4+j),
1825 i*RHSStartValue+j+IndexOffset) ||
1826 !isConstantOrUndef(N->getMaskElt(i*4+j+8),
1827 i*RHSStartValue+j+IndexOffset+8))
1828 return false;
1829 return true;
1830}
1831
1832/**
1833 * Determine if the specified shuffle mask is suitable for the vmrgew or
1834 * vmrgow instructions.
1835 *
1836 * \param[in] N The shuffle vector SD Node to analyze
1837 * \param[in] CheckEven Check for an even merge (true) or an odd merge (false)
1838 * \param[in] ShuffleKind Identify the type of merge:
1839 * - 0 = big-endian merge with two different inputs;
1840 * - 1 = either-endian merge with two identical inputs;
1841 * - 2 = little-endian merge with two different inputs (inputs are swapped for
1842 * little-endian merges).
1843 * \param[in] DAG The current SelectionDAG
1844 * \return true iff this shuffle mask
1845 */
1846bool PPC::isVMRGEOShuffleMask(ShuffleVectorSDNode *N, bool CheckEven,
1847 unsigned ShuffleKind, SelectionDAG &DAG) {
1848 if (DAG.getDataLayout().isLittleEndian()) {
1849 unsigned indexOffset = CheckEven ? 4 : 0;
1850 if (ShuffleKind == 1) // Unary
1851 return isVMerge(N, indexOffset, 0);
1852 else if (ShuffleKind == 2) // swapped
1853 return isVMerge(N, indexOffset, 16);
1854 else
1855 return false;
1856 }
1857 else {
1858 unsigned indexOffset = CheckEven ? 0 : 4;
1859 if (ShuffleKind == 1) // Unary
1860 return isVMerge(N, indexOffset, 0);
1861 else if (ShuffleKind == 0) // Normal
1862 return isVMerge(N, indexOffset, 16);
1863 else
1864 return false;
1865 }
1866 return false;
1867}
1868
1869/// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
1870/// amount, otherwise return -1.
1871/// The ShuffleKind distinguishes between big-endian operations with two
1872/// different inputs (0), either-endian operations with two identical inputs
1873/// (1), and little-endian operations with two different inputs (2). For the
1874/// latter, the input operands are swapped (see PPCInstrAltivec.td).
1875int PPC::isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind,
1876 SelectionDAG &DAG) {
1877 if (N->getValueType(0) != MVT::v16i8)
1878 return -1;
1879
1880 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1881
1882 // Find the first non-undef value in the shuffle mask.
1883 unsigned i;
1884 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i)
1885 /*search*/;
1886
1887 if (i == 16) return -1; // all undef.
1888
1889 // Otherwise, check to see if the rest of the elements are consecutively
1890 // numbered from this value.
1891 unsigned ShiftAmt = SVOp->getMaskElt(i);
1892 if (ShiftAmt < i) return -1;
1893
1894 ShiftAmt -= i;
1895 bool isLE = DAG.getDataLayout().isLittleEndian();
1896
1897 if ((ShuffleKind == 0 && !isLE) || (ShuffleKind == 2 && isLE)) {
1898 // Check the rest of the elements to see if they are consecutive.
1899 for (++i; i != 16; ++i)
1900 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
1901 return -1;
1902 } else if (ShuffleKind == 1) {
1903 // Check the rest of the elements to see if they are consecutive.
1904 for (++i; i != 16; ++i)
1905 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
1906 return -1;
1907 } else
1908 return -1;
1909
1910 if (isLE)
1911 ShiftAmt = 16 - ShiftAmt;
1912
1913 return ShiftAmt;
1914}
1915
1916/// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
1917/// specifies a splat of a single element that is suitable for input to
1918/// one of the splat operations (VSPLTB/VSPLTH/VSPLTW/XXSPLTW/LXVDSX/etc.).
1919bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) {
1920 assert(N->getValueType(0) == MVT::v16i8 && isPowerOf2_32(EltSize) &&((N->getValueType(0) == MVT::v16i8 && isPowerOf2_32
(EltSize) && EltSize <= 8 && "Can only handle 1,2,4,8 byte element sizes"
) ? static_cast<void> (0) : __assert_fail ("N->getValueType(0) == MVT::v16i8 && isPowerOf2_32(EltSize) && EltSize <= 8 && \"Can only handle 1,2,4,8 byte element sizes\""
, "/build/llvm-toolchain-snapshot-12~++20201124111112+7b5254223ac/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 1921, __PRETTY_FUNCTION__))
1921 EltSize <= 8 && "Can only handle 1,2,4,8 byte element sizes")((N->getValueType(0) == MVT::v16i8 && isPowerOf2_32
(EltSize) && EltSize <= 8 && "Can only handle 1,2,4,8 byte element sizes"
) ? static_cast<void> (0) : __assert_fail ("N->getValueType(0) == MVT::v16i8 && isPowerOf2_32(EltSize) && EltSize <= 8 && \"Can only handle 1,2,4,8 byte element sizes\""
, "/build/llvm-toolchain-snapshot-12~++20201124111112+7b5254223ac/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 1921, __PRETTY_FUNCTION__))
;
1922
1923 // The consecutive indices need to specify an element, not part of two
1924 // different elements. So abandon ship early if this isn't the case.
1925 if (N->getMaskElt(0) % EltSize != 0)
1926 return false;
1927
1928 // This is a splat operation if each element of the permute is the same, and
1929 // if the value doesn't reference the second vector.
1930 unsigned ElementBase = N->getMaskElt(0);
1931
1932 // FIXME: Handle UNDEF elements too!
1933 if (ElementBase >= 16)
1934 return false;
1935
1936 // Check that the indices are consecutive, in the case of a multi-byte element
1937 // splatted with a v16i8 mask.
1938 for (unsigned i = 1; i != EltSize; ++i)
1939 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase))
1940 return false;
1941
1942 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
1943 if (N->getMaskElt(i) < 0) continue;
1944 for (unsigned j = 0; j != EltSize; ++j)
1945 if (N->getMaskElt(i+j) != N->getMaskElt(j))
1946 return false;
1947 }
1948 return true;
1949}
1950
1951/// Check that the mask is shuffling N byte elements. Within each N byte
1952/// element of the mask, the indices could be either in increasing or
1953/// decreasing order as long as they are consecutive.
1954/// \param[in] N the shuffle vector SD Node to analyze
1955/// \param[in] Width the element width in bytes, could be 2/4/8/16 (HalfWord/
1956/// Word/DoubleWord/QuadWord).
1957/// \param[in] StepLen the delta indices number among the N byte element, if
1958/// the mask is in increasing/decreasing order then it is 1/-1.
1959/// \return true iff the mask is shuffling N byte elements.
1960static bool isNByteElemShuffleMask(ShuffleVectorSDNode *N, unsigned Width,
1961 int StepLen) {
1962 assert((Width == 2 || Width == 4 || Width == 8 || Width == 16) &&(((Width == 2 || Width == 4 || Width == 8 || Width == 16) &&
"Unexpected element width.") ? static_cast<void> (0) :
__assert_fail ("(Width == 2 || Width == 4 || Width == 8 || Width == 16) && \"Unexpected element width.\""
, "/build/llvm-toolchain-snapshot-12~++20201124111112+7b5254223ac/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 1963, __PRETTY_FUNCTION__))
1963 "Unexpected element width.")(((Width == 2 || Width == 4 || Width == 8 || Width == 16) &&
"Unexpected element width.") ? static_cast<void> (0) :
__assert_fail ("(Width == 2 || Width == 4 || Width == 8 || Width == 16) && \"Unexpected element width.\""
, "/build/llvm-toolchain-snapshot-12~++20201124111112+7b5254223ac/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 1963, __PRETTY_FUNCTION__))
;
1964 assert((StepLen == 1 || StepLen == -1) && "Unexpected element width.")(((StepLen == 1 || StepLen == -1) && "Unexpected element width."
) ? static_cast<void> (0) : __assert_fail ("(StepLen == 1 || StepLen == -1) && \"Unexpected element width.\""
, "/build/llvm-toolchain-snapshot-12~++20201124111112+7b5254223ac/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 1964, __PRETTY_FUNCTION__))
;
1965
1966 unsigned NumOfElem = 16 / Width;
1967 unsigned MaskVal[16]; // Width is never greater than 16
1968 for (unsigned i = 0; i < NumOfElem; ++i) {
1969 MaskVal[0] = N->getMaskElt(i * Width);
1970 if ((StepLen == 1) && (MaskVal[0] % Width)) {
1971 return false;
1972 } else if ((StepLen == -1) && ((MaskVal[0] + 1) % Width)) {
1973 return false;
1974 }
1975
1976 for (unsigned int j = 1; j < Width; ++j) {
1977 MaskVal[j] = N->getMaskElt(i * Width + j);
1978 if (MaskVal[j] != MaskVal[j-1] + StepLen) {
1979 return false;
1980 }
1981 }
1982 }
1983
1984 return true;
1985}
1986
1987bool PPC::isXXINSERTWMask(ShuffleVectorSDNode *N, unsigned &ShiftElts,
1988 unsigned &InsertAtByte, bool &Swap, bool IsLE) {
1989 if (!isNByteElemShuffleMask(N, 4, 1))
1990 return false;
1991
1992 // Now we look at mask elements 0,4,8,12
1993 unsigned M0 = N->getMaskElt(0) / 4;
1994 unsigned M1 = N->getMaskElt(4) / 4;
1995 unsigned M2 = N->getMaskElt(8) / 4;
1996 unsigned M3 = N->getMaskElt(12) / 4;
1997 unsigned LittleEndianShifts[] = { 2, 1, 0, 3 };
1998 unsigned BigEndianShifts[] = { 3, 0, 1, 2 };
1999
2000 // Below, let H and L be arbitrary elements of the shuffle mask
2001 // where H is in the range [4,7] and L is in the range [0,3].
2002 // H, 1, 2, 3 or L, 5, 6, 7
2003 if ((M0 > 3 && M1 == 1 && M2 == 2 && M3 == 3) ||
2004 (M0 < 4 && M1 == 5 && M2 == 6 && M3 == 7)) {
2005 ShiftElts = IsLE ? LittleEndianShifts[M0 & 0x3] : BigEndianShifts[M0 & 0x3];
2006 InsertAtByte = IsLE ? 12 : 0;
2007 Swap = M0 < 4;
2008 return true;
2009 }
2010 // 0, H, 2, 3 or 4, L, 6, 7
2011 if ((M1 > 3 && M0 == 0 && M2 == 2 && M3 == 3) ||
2012 (M1 < 4 && M0 == 4 && M2 == 6 && M3 == 7)) {
2013 ShiftElts = IsLE ? LittleEndianShifts[M1 & 0x3] : BigEndianShifts[M1 & 0x3];
2014 InsertAtByte = IsLE ? 8 : 4;
2015 Swap = M1 < 4;
2016 return true;
2017 }
2018 // 0, 1, H, 3 or 4, 5, L, 7
2019 if ((M2 > 3 && M0 == 0 && M1 == 1 && M3 == 3) ||
2020 (M2 < 4 && M0 == 4 && M1 == 5 && M3 == 7)) {
2021 ShiftElts = IsLE ? LittleEndianShifts[M2 & 0x3] : BigEndianShifts[M2 & 0x3];
2022 InsertAtByte = IsLE ? 4 : 8;
2023 Swap = M2 < 4;
2024 return true;
2025 }
2026 // 0, 1, 2, H or 4, 5, 6, L
2027 if ((M3 > 3 && M0 == 0 && M1 == 1 && M2 == 2) ||
2028 (M3 < 4 && M0 == 4 && M1 == 5 && M2 == 6)) {
2029 ShiftElts = IsLE ? LittleEndianShifts[M3 & 0x3] : BigEndianShifts[M3 & 0x3];
2030 InsertAtByte = IsLE ? 0 : 12;
2031 Swap = M3 < 4;
2032 return true;
2033 }
2034
2035 // If both vector operands for the shuffle are the same vector, the mask will
2036 // contain only elements from the first one and the second one will be undef.
2037 if (N->getOperand(1).isUndef()) {
2038 ShiftElts = 0;
2039 Swap = true;
2040 unsigned XXINSERTWSrcElem = IsLE ? 2 : 1;
2041 if (M0 == XXINSERTWSrcElem && M1 == 1 && M2 == 2 && M3 == 3) {
2042 InsertAtByte = IsLE ? 12 : 0;
2043 return true;
2044 }
2045 if (M0 == 0 && M1 == XXINSERTWSrcElem && M2 == 2 && M3 == 3) {
2046 InsertAtByte = IsLE ? 8 : 4;
2047 return true;
2048 }
2049 if (M0 == 0 && M1 == 1 && M2 == XXINSERTWSrcElem && M3 == 3) {
2050 InsertAtByte = IsLE ? 4 : 8;
2051 return true;
2052 }
2053 if (M0 == 0 && M1 == 1 && M2 == 2 && M3 == XXINSERTWSrcElem) {
2054 InsertAtByte = IsLE ? 0 : 12;
2055 return true;
2056 }
2057 }
2058
2059 return false;
2060}
2061
2062bool PPC::isXXSLDWIShuffleMask(ShuffleVectorSDNode *N, unsigned &ShiftElts,
2063 bool &Swap, bool IsLE) {
2064 assert(N->getValueType(0) == MVT::v16i8 && "Shuffle vector expects v16i8")((N->getValueType(0) == MVT::v16i8 && "Shuffle vector expects v16i8"
) ? static_cast<void> (0) : __assert_fail ("N->getValueType(0) == MVT::v16i8 && \"Shuffle vector expects v16i8\""
, "/build/llvm-toolchain-snapshot-12~++20201124111112+7b5254223ac/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2064, __PRETTY_FUNCTION__))
;
2065 // Ensure each byte index of the word is consecutive.
2066 if (!isNByteElemShuffleMask(N, 4, 1))
2067 return false;
2068
2069 // Now we look at mask elements 0,4,8,12, which are the beginning of words.
2070 unsigned M0 = N->getMaskElt(0) / 4;
2071 unsigned M1 = N->getMaskElt(4) / 4;
2072 unsigned M2 = N->getMaskElt(8) / 4;
2073 unsigned M3 = N->getMaskElt(12) / 4;
2074
2075 // If both vector operands for the shuffle are the same vector, the mask will
2076 // contain only elements from the first one and the second one will be undef.
2077 if (N->getOperand(1).isUndef()) {
2078 assert(M0 < 4 && "Indexing into an undef vector?")((M0 < 4 && "Indexing into an undef vector?") ? static_cast
<void> (0) : __assert_fail ("M0 < 4 && \"Indexing into an undef vector?\""
, "/build/llvm-toolchain-snapshot-12~++20201124111112+7b5254223ac/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2078, __PRETTY_FUNCTION__))
;
2079 if (M1 != (M0 + 1) % 4 || M2 != (M1 + 1) % 4 || M3 != (M2 + 1) % 4)
2080 return false;
2081
2082 ShiftElts = IsLE ? (4 - M0) % 4 : M0;
2083 Swap = false;
2084 return true;
2085 }
2086
2087 // Ensure each word index of the ShuffleVector Mask is consecutive.
2088 if (M1 != (M0 + 1) % 8 || M2 != (M1 + 1) % 8 || M3 != (M2 + 1) % 8)
2089 return false;
2090
2091 if (IsLE) {
2092 if (M0 == 0 || M0 == 7 || M0 == 6 || M0 == 5) {
2093 // Input vectors don't need to be swapped if the leading element
2094 // of the result is one of the 3 left elements of the second vector
2095 // (or if there is no shift to be done at all).
2096 Swap = false;
2097 ShiftElts = (8 - M0) % 8;
2098 } else if (M0 == 4 || M0 == 3 || M0 == 2 || M0 == 1) {
2099 // Input vectors need to be swapped if the leading element
2100 // of the result is one of the 3 left elements of the first vector
2101 // (or if we're shifting by 4 - thereby simply swapping the vectors).
2102 Swap = true;
2103 ShiftElts = (4 - M0) % 4;
2104 }
2105
2106 return true;
2107 } else { // BE
2108 if (M0 == 0 || M0 == 1 || M0 == 2 || M0 == 3) {
2109 // Input vectors don't need to be swapped if the leading element
2110 // of the result is one of the 4 elements of the first vector.
2111 Swap = false;
2112 ShiftElts = M0;
2113 } else if (M0 == 4 || M0 == 5 || M0 == 6 || M0 == 7) {
2114 // Input vectors need to be swapped if the leading element
2115 // of the result is one of the 4 elements of the right vector.
2116 Swap = true;
2117 ShiftElts = M0 - 4;
2118 }
2119
2120 return true;
2121 }
2122}
2123
2124bool static isXXBRShuffleMaskHelper(ShuffleVectorSDNode *N, int Width) {
2125 assert(N->getValueType(0) == MVT::v16i8 && "Shuffle vector expects v16i8")((N->getValueType(0) == MVT::v16i8 && "Shuffle vector expects v16i8"
) ? static_cast<void> (0) : __assert_fail ("N->getValueType(0) == MVT::v16i8 && \"Shuffle vector expects v16i8\""
, "/build/llvm-toolchain-snapshot-12~++20201124111112+7b5254223ac/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2125, __PRETTY_FUNCTION__))
;
2126
2127 if (!isNByteElemShuffleMask(N, Width, -1))
2128 return false;
2129
2130 for (int i = 0; i < 16; i += Width)
2131 if (N->getMaskElt(i) != i + Width - 1)
2132 return false;
2133
2134 return true;
2135}
2136
2137bool PPC::isXXBRHShuffleMask(ShuffleVectorSDNode *N) {
2138 return isXXBRShuffleMaskHelper(N, 2);
2139}
2140
2141bool PPC::isXXBRWShuffleMask(ShuffleVectorSDNode *N) {
2142 return isXXBRShuffleMaskHelper(N, 4);
2143}
2144
2145bool PPC::isXXBRDShuffleMask(ShuffleVectorSDNode *N) {
2146 return isXXBRShuffleMaskHelper(N, 8);
2147}
2148
2149bool PPC::isXXBRQShuffleMask(ShuffleVectorSDNode *N) {
2150 return isXXBRShuffleMaskHelper(N, 16);
2151}
2152
2153/// Can node \p N be lowered to an XXPERMDI instruction? If so, set \p Swap
2154/// if the inputs to the instruction should be swapped and set \p DM to the
2155/// value for the immediate.
2156/// Specifically, set \p Swap to true only if \p N can be lowered to XXPERMDI
2157/// AND element 0 of the result comes from the first input (LE) or second input
2158/// (BE). Set \p DM to the calculated result (0-3) only if \p N can be lowered.
2159/// \return true iff the given mask of shuffle node \p N is a XXPERMDI shuffle
2160/// mask.
2161bool PPC::isXXPERMDIShuffleMask(ShuffleVectorSDNode *N, unsigned &DM,
2162 bool &Swap, bool IsLE) {
2163 assert(N->getValueType(0) == MVT::v16i8 && "Shuffle vector expects v16i8")((N->getValueType(0) == MVT::v16i8 && "Shuffle vector expects v16i8"
) ? static_cast<void> (0) : __assert_fail ("N->getValueType(0) == MVT::v16i8 && \"Shuffle vector expects v16i8\""
, "/build/llvm-toolchain-snapshot-12~++20201124111112+7b5254223ac/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2163, __PRETTY_FUNCTION__))
;
2164
2165 // Ensure each byte index of the double word is consecutive.
2166 if (!isNByteElemShuffleMask(N, 8, 1))
2167 return false;
2168
2169 unsigned M0 = N->getMaskElt(0) / 8;
2170 unsigned M1 = N->getMaskElt(8) / 8;
2171 assert(((M0 | M1) < 4) && "A mask element out of bounds?")((((M0 | M1) < 4) && "A mask element out of bounds?"
) ? static_cast<void> (0) : __assert_fail ("((M0 | M1) < 4) && \"A mask element out of bounds?\""
, "/build/llvm-toolchain-snapshot-12~++20201124111112+7b5254223ac/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2171, __PRETTY_FUNCTION__))
;
2172
2173 // If both vector operands for the shuffle are the same vector, the mask will
2174 // contain only elements from the first one and the second one will be undef.
2175 if (N->getOperand(1).isUndef()) {
2176 if ((M0 | M1) < 2) {
2177 DM = IsLE ? (((~M1) & 1) << 1) + ((~M0) & 1) : (M0 << 1) + (M1 & 1);
2178 Swap = false;
2179 return true;
2180 } else
2181 return false;
2182 }
2183
2184 if (IsLE) {
2185 if (M0 > 1 && M1 < 2) {
2186 Swap = false;
2187 } else if (M0 < 2 && M1 > 1) {
2188 M0 = (M0 + 2) % 4;
2189 M1 = (M1 + 2) % 4;
2190 Swap = true;
2191 } else
2192 return false;
2193
2194 // Note: if control flow comes here that means Swap is already set above
2195 DM = (((~M1) & 1) << 1) + ((~M0) & 1);
2196 return true;
2197 } else { // BE
2198 if (M0 < 2 && M1 > 1) {
2199 Swap = false;
2200 } else if (M0 > 1 && M1 < 2) {
2201 M0 = (M0 + 2) % 4;
2202 M1 = (M1 + 2) % 4;
2203 Swap = true;
2204 } else
2205 return false;
2206
2207 // Note: if control flow comes here that means Swap is already set above
2208 DM = (M0 << 1) + (M1 & 1);
2209 return true;
2210 }
2211}
2212
2213
2214/// getSplatIdxForPPCMnemonics - Return the splat index as a value that is
2215/// appropriate for PPC mnemonics (which have a big endian bias - namely
2216/// elements are counted from the left of the vector register).
2217unsigned PPC::getSplatIdxForPPCMnemonics(SDNode *N, unsigned EltSize,
2218 SelectionDAG &DAG) {
2219 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
2220 assert(isSplatShuffleMask(SVOp, EltSize))((isSplatShuffleMask(SVOp, EltSize)) ? static_cast<void>
(0) : __assert_fail ("isSplatShuffleMask(SVOp, EltSize)", "/build/llvm-toolchain-snapshot-12~++20201124111112+7b5254223ac/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2220, __PRETTY_FUNCTION__))
;
2221 if (DAG.getDataLayout().isLittleEndian())
2222 return (16 / EltSize) - 1 - (SVOp->getMaskElt(0) / EltSize);
2223 else
2224 return SVOp->getMaskElt(0) / EltSize;
2225}
2226
2227/// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
2228/// by using a vspltis[bhw] instruction of the specified element size, return
2229/// the constant being splatted. The ByteSize field indicates the number of
2230/// bytes of each element [124] -> [bhw].
2231SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
2232 SDValue OpVal(nullptr, 0);
2233
2234 // If ByteSize of the splat is bigger than the element size of the
2235 // build_vector, then we have a case where we are checking for a splat where
2236 // multiple elements of the buildvector are folded together into a single
2237 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
2238 unsigned EltSize = 16/N->getNumOperands();
2239 if (EltSize < ByteSize) {
2240 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
2241 SDValue UniquedVals[4];
2242 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?")((Multiple > 1 && Multiple <= 4 && "How can this happen?"
) ? static_cast<void> (0) : __assert_fail ("Multiple > 1 && Multiple <= 4 && \"How can this happen?\""
, "/build/llvm-toolchain-snapshot-12~++20201124111112+7b5254223ac/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2242, __PRETTY_FUNCTION__))
;
2243
2244 // See if all of the elements in the buildvector agree across.
2245 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
2246 if (N->getOperand(i).isUndef()) continue;
2247 // If the element isn't a constant, bail fully out.
2248 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
2249
2250 if (!UniquedVals[i&(Multiple-1)].getNode())
2251 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
2252 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
2253 return SDValue(); // no match.
2254 }
2255
2256 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
2257 // either constant or undef values that are identical for each chunk. See
2258 // if these chunks can form into a larger vspltis*.
2259
2260 // Check to see if all of the leading entries are either 0 or -1. If
2261 // neither, then this won't fit into the immediate field.
2262 bool LeadingZero = true;
2263 bool LeadingOnes = true;
2264 for (unsigned i = 0; i != Multiple-1; ++i) {
2265 if (!UniquedVals[i].getNode()) continue; // Must have been undefs.
2266
2267 LeadingZero &= isNullConstant(UniquedVals[i]);
2268 LeadingOnes &= isAllOnesConstant(UniquedVals[i]);
2269 }
2270 // Finally, check the least significant entry.
2271 if (LeadingZero) {
2272 if (!UniquedVals[Multiple-1].getNode())
2273 return DAG.getTargetConstant(0, SDLoc(N), MVT::i32); // 0,0,0,undef
2274 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
2275 if (Val < 16) // 0,0,0,4 -> vspltisw(4)
2276 return DAG.getTargetConstant(Val, SDLoc(N), MVT::i32);
2277 }
2278 if (LeadingOnes) {
2279 if (!UniquedVals[Multiple-1].getNode())
2280 return DAG.getTargetConstant(~0U, SDLoc(N), MVT::i32); // -1,-1,-1,undef
2281 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
2282 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
2283 return DAG.getTargetConstant(Val, SDLoc(N), MVT::i32);
2284 }
2285
2286 return SDValue();
2287 }
2288
2289 // Check to see if this buildvec has a single non-undef value in its elements.
2290 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
2291 if (N->getOperand(i).isUndef()) continue;
2292 if (!OpVal.getNode())
2293 OpVal = N->getOperand(i);
2294 else if (OpVal != N->getOperand(i))
2295 return SDValue();
2296 }
2297
2298 if (!OpVal.getNode()) return SDValue(); // All UNDEF: use implicit def.
2299
2300 unsigned ValSizeInBytes = EltSize;
2301 uint64_t Value = 0;
2302 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
2303 Value = CN->getZExtValue();
2304 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
2305 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!")((CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!"
) ? static_cast<void> (0) : __assert_fail ("CN->getValueType(0) == MVT::f32 && \"Only one legal FP vector type!\""
, "/build/llvm-toolchain-snapshot-12~++20201124111112+7b5254223ac/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2305, __PRETTY_FUNCTION__))
;
2306 Value = FloatToBits(CN->getValueAPF().convertToFloat());
2307 }
2308
2309 // If the splat value is larger than the element value, then we can never do
2310 // this splat. The only case that we could fit the replicated bits into our
2311 // immediate field for would be zero, and we prefer to use vxor for it.
2312 if (ValSizeInBytes < ByteSize) return SDValue();
2313
2314 // If the element value is larger than the splat value, check if it consists
2315 // of a repeated bit pattern of size ByteSize.
2316 if (!APInt(ValSizeInBytes * 8, Value).isSplat(ByteSize * 8))
2317 return SDValue();
2318
2319 // Properly sign extend the value.
2320 int MaskVal = SignExtend32(Value, ByteSize * 8);
2321
2322 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
2323 if (MaskVal == 0) return SDValue();
2324
2325 // Finally, if this value fits in a 5 bit sext field, return it
2326 if (SignExtend32<5>(MaskVal) == MaskVal)
2327 return DAG.getTargetConstant(MaskVal, SDLoc(N), MVT::i32);
2328 return SDValue();
2329}
2330
2331/// isQVALIGNIShuffleMask - If this is a qvaligni shuffle mask, return the shift
2332/// amount, otherwise return -1.
2333int PPC::isQVALIGNIShuffleMask(SDNode *N) {
2334 EVT VT = N->getValueType(0);
2335 if (VT != MVT::v4f64 && VT != MVT::v4f32 && VT != MVT::v4i1)
2336 return -1;
2337
2338 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
2339
2340 // Find the first non-undef value in the shuffle mask.
2341 unsigned i;
2342 for (i = 0; i != 4 && SVOp->getMaskElt(i) < 0; ++i)
2343 /*search*/;
2344
2345 if (i == 4) return -1; // all undef.
2346
2347 // Otherwise, check to see if the rest of the elements are consecutively
2348 // numbered from this value.
2349 unsigned ShiftAmt = SVOp->getMaskElt(i);
2350 if (ShiftAmt < i) return -1;
2351 ShiftAmt -= i;
2352
2353 // Check the rest of the elements to see if they are consecutive.
2354 for (++i; i != 4; ++i)
2355 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
2356 return -1;
2357
2358 return ShiftAmt;
2359}
2360
2361//===----------------------------------------------------------------------===//
2362// Addressing Mode Selection
2363//===----------------------------------------------------------------------===//
2364
2365/// isIntS16Immediate - This method tests to see if the node is either a 32-bit
2366/// or 64-bit immediate, and if the value can be accurately represented as a
2367/// sign extension from a 16-bit value. If so, this returns true and the
2368/// immediate.
2369bool llvm::isIntS16Immediate(SDNode *N, int16_t &Imm) {
2370 if (!isa<ConstantSDNode>(N))
2371 return false;
2372
2373 Imm = (int16_t)cast<ConstantSDNode>(N)->getZExtValue();
2374 if (N->getValueType(0) == MVT::i32)
2375 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
2376 else
2377 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
2378}
2379bool llvm::isIntS16Immediate(SDValue Op, int16_t &Imm) {
2380 return isIntS16Immediate(Op.getNode(), Imm);
2381}
2382
2383
2384/// SelectAddressEVXRegReg - Given the specified address, check to see if it can
2385/// be represented as an indexed [r+r] operation.
2386bool PPCTargetLowering::SelectAddressEVXRegReg(SDValue N, SDValue &Base,
2387 SDValue &Index,
2388 SelectionDAG &DAG) const {
2389 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end();
2390 UI != E; ++UI) {
2391 if (MemSDNode *Memop = dyn_cast<MemSDNode>(*UI)) {
2392 if (Memop->getMemoryVT() == MVT::f64) {
2393 Base = N.getOperand(0);
2394 Index = N.getOperand(1);
2395 return true;
2396 }
2397 }
2398 }
2399 return false;
2400}
2401
2402/// isIntS34Immediate - This method tests if value of node given can be
2403/// accurately represented as a sign extension from a 34-bit value. If so,
2404/// this returns true and the immediate.
2405bool llvm::isIntS34Immediate(SDNode *N, int64_t &Imm) {
2406 if (!isa<ConstantSDNode>(N))
2407 return false;
2408
2409 Imm = (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
2410 return isInt<34>(Imm);
2411}
2412bool llvm::isIntS34Immediate(SDValue Op, int64_t &Imm) {
2413 return isIntS34Immediate(Op.getNode(), Imm);
2414}
2415
2416/// SelectAddressRegReg - Given the specified addressed, check to see if it
2417/// can be represented as an indexed [r+r] operation. Returns false if it
2418/// can be more efficiently represented as [r+imm]. If \p EncodingAlignment is
2419/// non-zero and N can be represented by a base register plus a signed 16-bit
2420/// displacement, make a more precise judgement by checking (displacement % \p
2421/// EncodingAlignment).
2422bool PPCTargetLowering::SelectAddressRegReg(
2423 SDValue N, SDValue &Base, SDValue &Index, SelectionDAG &DAG,
2424 MaybeAlign EncodingAlignment) const {
2425 // If we have a PC Relative target flag don't select as [reg+reg]. It will be
2426 // a [pc+imm].
2427 if (SelectAddressPCRel(N, Base))
2428 return false;
2429
2430 int16_t Imm = 0;
2431 if (N.getOpcode() == ISD::ADD) {
2432 // Is there any SPE load/store (f64), which can't handle 16bit offset?
2433 // SPE load/store can only handle 8-bit offsets.
2434 if (hasSPE() && SelectAddressEVXRegReg(N, Base, Index, DAG))
2435 return true;
2436 if (isIntS16Immediate(N.getOperand(1), Imm) &&
2437 (!EncodingAlignment || isAligned(*EncodingAlignment, Imm)))
2438 return false; // r+i
2439 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
2440 return false; // r+i
2441
2442 Base = N.getOperand(0);
2443 Index = N.getOperand(1);
2444 return true;
2445 } else if (N.getOpcode() == ISD::OR) {
2446 if (isIntS16Immediate(N.getOperand(1), Imm) &&
2447 (!EncodingAlignment || isAligned(*EncodingAlignment, Imm)))
2448 return false; // r+i can fold it if we can.
2449
2450 // If this is an or of disjoint bitfields, we can codegen this as an add
2451 // (for better address arithmetic) if the LHS and RHS of the OR are provably
2452 // disjoint.
2453 KnownBits LHSKnown = DAG.computeKnownBits(N.getOperand(0));
2454
2455 if (LHSKnown.Zero.getBoolValue()) {
2456 KnownBits RHSKnown = DAG.computeKnownBits(N.getOperand(1));
2457 // If all of the bits are known zero on the LHS or RHS, the add won't
2458 // carry.
2459 if (~(LHSKnown.Zero | RHSKnown.Zero) == 0) {
2460 Base = N.getOperand(0);
2461 Index = N.getOperand(1);
2462 return true;
2463 }
2464 }
2465 }
2466
2467 return false;
2468}
2469
2470// If we happen to be doing an i64 load or store into a stack slot that has
2471// less than a 4-byte alignment, then the frame-index elimination may need to
2472// use an indexed load or store instruction (because the offset may not be a
2473// multiple of 4). The extra register needed to hold the offset comes from the
2474// register scavenger, and it is possible that the scavenger will need to use
2475// an emergency spill slot. As a result, we need to make sure that a spill slot
2476// is allocated when doing an i64 load/store into a less-than-4-byte-aligned
2477// stack slot.
2478static void fixupFuncForFI(SelectionDAG &DAG, int FrameIdx, EVT VT) {
2479 // FIXME: This does not handle the LWA case.
2480 if (VT != MVT::i64)
2481 return;
2482
2483 // NOTE: We'll exclude negative FIs here, which come from argument
2484 // lowering, because there are no known test cases triggering this problem
2485 // using packed structures (or similar). We can remove this exclusion if
2486 // we find such a test case. The reason why this is so test-case driven is
2487 // because this entire 'fixup' is only to prevent crashes (from the
2488 // register scavenger) on not-really-valid inputs. For example, if we have:
2489 // %a = alloca i1
2490 // %b = bitcast i1* %a to i64*
2491 // store i64* a, i64 b
2492 // then the store should really be marked as 'align 1', but is not. If it
2493 // were marked as 'align 1' then the indexed form would have been
2494 // instruction-selected initially, and the problem this 'fixup' is preventing
2495 // won't happen regardless.
2496 if (FrameIdx < 0)
2497 return;
2498
2499 MachineFunction &MF = DAG.getMachineFunction();
2500 MachineFrameInfo &MFI = MF.getFrameInfo();
2501
2502 if (MFI.getObjectAlign(FrameIdx) >= Align(4))
2503 return;
2504
2505 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2506 FuncInfo->setHasNonRISpills();
2507}
2508
2509/// Returns true if the address N can be represented by a base register plus
2510/// a signed 16-bit displacement [r+imm], and if it is not better
2511/// represented as reg+reg. If \p EncodingAlignment is non-zero, only accept
2512/// displacements that are multiples of that value.
2513bool PPCTargetLowering::SelectAddressRegImm(
2514 SDValue N, SDValue &Disp, SDValue &Base, SelectionDAG &DAG,
2515 MaybeAlign EncodingAlignment) const {
2516 // FIXME dl should come from parent load or store, not from address
2517 SDLoc dl(N);
2518
2519 // If we have a PC Relative target flag don't select as [reg+imm]. It will be
2520 // a [pc+imm].
2521 if (SelectAddressPCRel(N, Base))
2522 return false;
2523
2524 // If this can be more profitably realized as r+r, fail.
2525 if (SelectAddressRegReg(N, Disp, Base, DAG, EncodingAlignment))
2526 return false;
2527
2528 if (N.getOpcode() == ISD::ADD) {
2529 int16_t imm = 0;
2530 if (isIntS16Immediate(N.getOperand(1), imm) &&
2531 (!EncodingAlignment || isAligned(*EncodingAlignment, imm))) {
2532 Disp = DAG.getTargetConstant(imm, dl, N.getValueType());
2533 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
2534 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
2535 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
2536 } else {
2537 Base = N.getOperand(0);
2538 }
2539 return true; // [r+i]
2540 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
2541 // Match LOAD (ADD (X, Lo(G))).
2542 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()((!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->
getZExtValue() && "Cannot handle constant offsets yet!"
) ? static_cast<void> (0) : __assert_fail ("!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue() && \"Cannot handle constant offsets yet!\""
, "/build/llvm-toolchain-snapshot-12~++20201124111112+7b5254223ac/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2543, __PRETTY_FUNCTION__))
2543 && "Cannot handle constant offsets yet!")((!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->
getZExtValue() && "Cannot handle constant offsets yet!"
) ? static_cast<void> (0) : __assert_fail ("!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue() && \"Cannot handle constant offsets yet!\""
, "/build/llvm-toolchain-snapshot-12~++20201124111112+7b5254223ac/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2543, __PRETTY_FUNCTION__))
;
2544 Disp = N.getOperand(1).getOperand(0); // The global address.
2545 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||((Disp.getOpcode() == ISD::TargetGlobalAddress || Disp.getOpcode
() == ISD::TargetGlobalTLSAddress || Disp.getOpcode() == ISD::
TargetConstantPool || Disp.getOpcode() == ISD::TargetJumpTable
) ? static_cast<void> (0) : __assert_fail ("Disp.getOpcode() == ISD::TargetGlobalAddress || Disp.getOpcode() == ISD::TargetGlobalTLSAddress || Disp.getOpcode() == ISD::TargetConstantPool || Disp.getOpcode() == ISD::TargetJumpTable"
, "/build/llvm-toolchain-snapshot-12~++20201124111112+7b5254223ac/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2548, __PRETTY_FUNCTION__))
2546 Disp.getOpcode() == ISD::TargetGlobalTLSAddress ||((Disp.getOpcode() == ISD::TargetGlobalAddress || Disp.getOpcode
() == ISD::TargetGlobalTLSAddress || Disp.getOpcode() == ISD::
TargetConstantPool || Disp.getOpcode() == ISD::TargetJumpTable
) ? static_cast<void> (0) : __assert_fail ("Disp.getOpcode() == ISD::TargetGlobalAddress || Disp.getOpcode() == ISD::TargetGlobalTLSAddress || Disp.getOpcode() == ISD::TargetConstantPool || Disp.getOpcode() == ISD::TargetJumpTable"
, "/build/llvm-toolchain-snapshot-12~++20201124111112+7b5254223ac/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2548, __PRETTY_FUNCTION__))
2547 Disp.getOpcode() == ISD::TargetConstantPool ||((Disp.getOpcode() == ISD::TargetGlobalAddress || Disp.getOpcode
() == ISD::TargetGlobalTLSAddress || Disp.getOpcode() == ISD::
TargetConstantPool || Disp.getOpcode() == ISD::TargetJumpTable
) ? static_cast<void> (0) : __assert_fail ("Disp.getOpcode() == ISD::TargetGlobalAddress || Disp.getOpcode() == ISD::TargetGlobalTLSAddress || Disp.getOpcode() == ISD::TargetConstantPool || Disp.getOpcode() == ISD::TargetJumpTable"
, "/build/llvm-toolchain-snapshot-12~++20201124111112+7b5254223ac/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2548, __PRETTY_FUNCTION__))
2548 Disp.getOpcode() == ISD::TargetJumpTable)((Disp.getOpcode() == ISD::TargetGlobalAddress || Disp.getOpcode
() == ISD::TargetGlobalTLSAddress || Disp.getOpcode() == ISD::
TargetConstantPool || Disp.getOpcode() == ISD::TargetJumpTable
) ? static_cast<void> (0) : __assert_fail ("Disp.getOpcode() == ISD::TargetGlobalAddress || Disp.getOpcode() == ISD::TargetGlobalTLSAddress || Disp.getOpcode() == ISD::TargetConstantPool || Disp.getOpcode() == ISD::TargetJumpTable"
, "/build/llvm-toolchain-snapshot-12~++20201124111112+7b5254223ac/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2548, __PRETTY_FUNCTION__))
;
2549 Base = N.getOperand(0);
2550 return true; // [&g+r]
2551 }
2552 } else if (N.getOpcode() == ISD::OR) {
2553 int16_t imm = 0;
2554 if (isIntS16Immediate(N.getOperand(1), imm) &&
2555 (!EncodingAlignment || isAligned(*EncodingAlignment, imm))) {
2556 // If this is an or of disjoint bitfields, we can codegen this as an add
2557 // (for better address arithmetic) if the LHS and RHS of the OR are
2558 // provably disjoint.
2559 KnownBits LHSKnown = DAG.computeKnownBits(N.getOperand(0));
2560
2561 if ((LHSKnown.Zero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
2562 // If all of the bits are known zero on the LHS or RHS, the add won't
2563 // carry.
2564 if (FrameIndexSDNode *FI =
2565 dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
2566 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
2567 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
2568 } else {
2569 Base = N.getOperand(0);
2570 }
2571 Disp = DAG.getTargetConstant(imm, dl, N.getValueType());
2572 return true;
2573 }
2574 }
2575 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
2576 // Loading from a constant address.
2577
2578 // If this address fits entirely in a 16-bit sext immediate field, codegen
2579 // this as "d, 0"
2580 int16_t Imm;
2581 if (isIntS16Immediate(CN, Imm) &&
2582 (!EncodingAlignment || isAligned(*EncodingAlignment, Imm))) {
2583 Disp = DAG.getTargetConstant(Imm, dl, CN->getValueType(0));
2584 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
2585 CN->getValueType(0));
2586 return true;
2587 }
2588
2589 // Handle 32-bit sext immediates with LIS + addr mode.
2590 if ((CN->getValueType(0) == MVT::i32 ||
2591 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) &&
2592 (!EncodingAlignment ||
2593 isAligned(*EncodingAlignment, CN->getZExtValue()))) {
2594 int Addr = (int)CN->getZExtValue();
2595
2596 // Otherwise, break this down into an LIS + disp.
2597 Disp = DAG.getTargetConstant((short)Addr, dl, MVT::i32);
2598
2599 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, dl,
2600 MVT::i32);
2601 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
2602 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0);
2603 return true;
2604 }
2605 }
2606
2607 Disp = DAG.getTargetConstant(0, dl, getPointerTy(DAG.getDataLayout()));
2608 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) {
2609 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
2610 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
2611 } else
2612 Base = N;
2613 return true; // [r+0]
2614}
2615
2616/// Similar to the 16-bit case but for instructions that take a 34-bit
2617/// displacement field (prefixed loads/stores).
2618bool PPCTargetLowering::SelectAddressRegImm34(SDValue N, SDValue &Disp,
2619 SDValue &Base,
2620 SelectionDAG &DAG) const {
2621 // Only on 64-bit targets.
2622 if (N.getValueType() != MVT::i64)
2623 return false;
2624
2625 SDLoc dl(N);
2626 int64_t Imm = 0;
2627
2628 if (N.getOpcode() == ISD::ADD) {
2629 if (!isIntS34Immediate(N.getOperand(1), Imm))
2630 return false;
2631 Disp = DAG.getTargetConstant(Imm, dl, N.getValueType());
2632 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0)))
2633 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
2634 else
2635 Base = N.getOperand(0);
2636 return true;
2637 }
2638
2639 if (N.getOpcode() == ISD::OR) {
2640 if (!isIntS34Immediate(N.getOperand(1), Imm))
2641 return false;
2642 // If this is an or of disjoint bitfields, we can codegen this as an add
2643 // (for better address arithmetic) if the LHS and RHS of the OR are
2644 // provably disjoint.
2645 KnownBits LHSKnown = DAG.computeKnownBits(N.getOperand(0));
2646 if ((LHSKnown.Zero.getZExtValue() | ~(uint64_t)Imm) != ~0ULL)
2647 return false;
2648 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0)))
2649 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
2650 else
2651 Base = N.getOperand(0);
2652 Disp = DAG.getTargetConstant(Imm, dl, N.getValueType());
2653 return true;
2654 }
2655
2656 if (isIntS34Immediate(N, Imm)) { // If the address is a 34-bit const.
2657 Disp = DAG.getTargetConstant(Imm, dl, N.getValueType());
2658 Base = DAG.getRegister(PPC::ZERO8, N.getValueType());
2659 return true;
2660 }
2661
2662 return false;
2663}
2664
2665/// SelectAddressRegRegOnly - Given the specified addressed, force it to be
2666/// represented as an indexed [r+r] operation.
2667bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
2668 SDValue &Index,
2669 SelectionDAG &DAG) const {
2670 // Check to see if we can easily represent this as an [r+r] address. This
2671 // will fail if it thinks that the address is more profitably represented as
2672 // reg+imm, e.g. where imm = 0.
2673 if (SelectAddressRegReg(N, Base, Index, DAG))
2674 return true;
2675
2676 // If the address is the result of an add, we will utilize the fact that the
2677 // address calculation includes an implicit add. However, we can reduce
2678 // register pressure if we do not materialize a constant just for use as the
2679 // index register. We only get rid of the add if it is not an add of a
2680 // value and a 16-bit signed constant and both have a single use.
2681 int16_t imm = 0;
2682 if (N.getOpcode() == ISD::ADD &&
2683 (!isIntS16Immediate(N.getOperand(1), imm) ||
2684 !N.getOperand(1).hasOneUse() || !N.getOperand(0).hasOneUse())) {
2685 Base = N.getOperand(0);
2686 Index = N.getOperand(1);
2687 return true;
2688 }
2689
2690 // Otherwise, do it the hard way, using R0 as the base register.
2691 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
2692 N.getValueType());
2693 Index = N;
2694 return true;
2695}
2696
2697template <typename Ty> static bool isValidPCRelNode(SDValue N) {
2698 Ty *PCRelCand = dyn_cast<Ty>(N);
2699 return PCRelCand && (PCRelCand->getTargetFlags() & PPCII::MO_PCREL_FLAG);
2700}
2701
2702/// Returns true if this address is a PC Relative address.
2703/// PC Relative addresses are marked with the flag PPCII::MO_PCREL_FLAG
2704/// or if the node opcode is PPCISD::MAT_PCREL_ADDR.
2705bool PPCTargetLowering::SelectAddressPCRel(SDValue N, SDValue &Base) const {
2706 // This is a materialize PC Relative node. Always select this as PC Relative.
2707 Base = N;
2708 if (N.getOpcode() == PPCISD::MAT_PCREL_ADDR)
2709 return true;
2710 if (isValidPCRelNode<ConstantPoolSDNode>(N) ||
2711 isValidPCRelNode<GlobalAddressSDNode>(N) ||
2712 isValidPCRelNode<JumpTableSDNode>(N) ||
2713 isValidPCRelNode<BlockAddressSDNode>(N))
2714 return true;
2715 return false;
2716}
2717
2718/// Returns true if we should use a direct load into vector instruction
2719/// (such as lxsd or lfd), instead of a load into gpr + direct move sequence.
2720static bool usePartialVectorLoads(SDNode *N, const PPCSubtarget& ST) {
2721
2722 // If there are any other uses other than scalar to vector, then we should
2723 // keep it as a scalar load -> direct move pattern to prevent multiple
2724 // loads.
2725 LoadSDNode *LD = dyn_cast<LoadSDNode>(N);
2726 if (!LD)
2727 return false;
2728
2729 EVT MemVT = LD->getMemoryVT();
2730 if (!MemVT.isSimple())
2731 return false;
2732 switch(MemVT.getSimpleVT().SimpleTy) {
2733 case MVT::i64:
2734 break;
2735 case MVT::i32:
2736 if (!ST.hasP8Vector())
2737 return false;
2738 break;
2739 case MVT::i16:
2740 case MVT::i8:
2741 if (!ST.hasP9Vector())
2742 return false;
2743 break;
2744 default:
2745 return false;
2746 }
2747
2748 SDValue LoadedVal(N, 0);
2749 if (!LoadedVal.hasOneUse())
2750 return false;
2751
2752 for (SDNode::use_iterator UI = LD->use_begin(), UE = LD->use_end();
2753 UI != UE; ++UI)
2754 if (UI.getUse().get().getResNo() == 0 &&
2755 UI->getOpcode() != ISD::SCALAR_TO_VECTOR &&
2756 UI->getOpcode() != PPCISD::SCALAR_TO_VECTOR_PERMUTED)
2757 return false;
2758
2759 return true;
2760}
2761
2762/// getPreIndexedAddressParts - returns true by value, base pointer and
2763/// offset pointer and addressing mode by reference if the node's address
2764/// can be legally represented as pre-indexed load / store address.
2765bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
2766 SDValue &Offset,
2767 ISD::MemIndexedMode &AM,
2768 SelectionDAG &DAG) const {
2769 if (DisablePPCPreinc) return false;
2770
2771 bool isLoad = true;
2772 SDValue Ptr;
2773 EVT VT;
2774 unsigned Alignment;
2775 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
2776 Ptr = LD->getBasePtr();
2777 VT = LD->getMemoryVT();
2778 Alignment = LD->getAlignment();
2779 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
2780 Ptr = ST->getBasePtr();
2781 VT = ST->getMemoryVT();
2782 Alignment = ST->getAlignment();
2783 isLoad = false;
2784 } else
2785 return false;
2786
2787 // Do not generate pre-inc forms for specific loads that feed scalar_to_vector
2788 // instructions because we can fold these into a more efficient instruction
2789 // instead, (such as LXSD).
2790 if (isLoad && usePartialVectorLoads(N, Subtarget)) {
2791 return false;
2792 }
2793
2794 // PowerPC doesn't have preinc load/store instructions for vectors
2795 if (VT.isVector())
2796 return false;
2797
2798 if (SelectAddressRegReg(Ptr, Base, Offset, DAG)) {
2799 // Common code will reject creating a pre-inc form if the base pointer
2800 // is a frame index, or if N is a store and the base pointer is either
2801 // the same as or a predecessor of the value being stored. Check for
2802 // those situations here, and try with swapped Base/Offset instead.
2803 bool Swap = false;
2804
2805 if (isa<FrameIndexSDNode>(Base) || isa<RegisterSDNode>(Base))
2806 Swap = true;
2807 else if (!isLoad) {
2808 SDValue Val = cast<StoreSDNode>(N)->getValue();
2809 if (Val == Base || Base.getNode()->isPredecessorOf(Val.getNode()))
2810 Swap = true;
2811 }
2812
2813 if (Swap)
2814 std::swap(Base, Offset);
2815
2816 AM = ISD::PRE_INC;
2817 return true;
2818 }
2819
2820 // LDU/STU can only handle immediates that are a multiple of 4.
2821 if (VT != MVT::i64) {
2822 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, None))
2823 return false;
2824 } else {
2825 // LDU/STU need an address with at least 4-byte alignment.
2826 if (Alignment < 4)
2827 return false;
2828
2829 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, Align(4)))
2830 return false;
2831 }
2832
2833 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
2834 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
2835 // sext i32 to i64 when addr mode is r+i.
2836 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
2837 LD->getExtensionType() == ISD::SEXTLOAD &&
2838 isa<ConstantSDNode>(Offset))
2839 return false;
2840 }
2841
2842 AM = ISD::PRE_INC;
2843 return true;
2844}
2845
2846//===----------------------------------------------------------------------===//
2847// LowerOperation implementation
2848//===----------------------------------------------------------------------===//
2849
2850/// Return true if we should reference labels using a PICBase, set the HiOpFlags
2851/// and LoOpFlags to the target MO flags.
2852static void getLabelAccessInfo(bool IsPIC, const PPCSubtarget &Subtarget,
2853 unsigned &HiOpFlags, unsigned &LoOpFlags,
2854 const GlobalValue *GV = nullptr) {
2855 HiOpFlags = PPCII::MO_HA;
2856 LoOpFlags = PPCII::MO_LO;
2857
2858 // Don't use the pic base if not in PIC relocation model.
2859 if (IsPIC) {
2860 HiOpFlags |= PPCII::MO_PIC_FLAG;
2861 LoOpFlags |= PPCII::MO_PIC_FLAG;
2862 }
2863}
2864
2865static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC,
2866 SelectionDAG &DAG) {
2867 SDLoc DL(HiPart);
2868 EVT PtrVT = HiPart.getValueType();
2869 SDValue Zero = DAG.getConstant(0, DL, PtrVT);
2870
2871 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero);
2872 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, LoPart, Zero);
2873
2874 // With PIC, the first instruction is actually "GR+hi(&G)".
2875 if (isPIC)
2876 Hi = DAG.getNode(ISD::ADD, DL, PtrVT,
2877 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT), Hi);
2878
2879 // Generate non-pic code that has direct accesses to the constant pool.
2880 // The address of the global is just (hi(&g)+lo(&g)).
2881 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
2882}
2883
2884static void setUsesTOCBasePtr(MachineFunction &MF) {
2885 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2886 FuncInfo->setUsesTOCBasePtr();
2887}
2888
2889static void setUsesTOCBasePtr(SelectionDAG &DAG) {
2890 setUsesTOCBasePtr(DAG.getMachineFunction());
2891}
2892
2893SDValue PPCTargetLowering::getTOCEntry(SelectionDAG &DAG, const SDLoc &dl,
2894 SDValue GA) const {
2895 const bool Is64Bit = Subtarget.isPPC64();
2896 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
2897 SDValue Reg = Is64Bit ? DAG.getRegister(PPC::X2, VT)
2898 : Subtarget.isAIXABI()
2899 ? DAG.getRegister(PPC::R2, VT)
2900 : DAG.getNode(PPCISD::GlobalBaseReg, dl, VT);
2901 SDValue Ops[] = { GA, Reg };
2902 return DAG.getMemIntrinsicNode(
2903 PPCISD::TOC_ENTRY, dl, DAG.getVTList(VT, MVT::Other), Ops, VT,
2904 MachinePointerInfo::getGOT(DAG.getMachineFunction()), None,
2905 MachineMemOperand::MOLoad);
2906}
2907
2908SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
2909 SelectionDAG &DAG) const {
2910 EVT PtrVT = Op.getValueType();
2911 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
2912 const Constant *C = CP->getConstVal();
2913
2914 // 64-bit SVR4 ABI and AIX ABI code are always position-independent.
2915 // The actual address of the GlobalValue is stored in the TOC.
2916 if (Subtarget.is64BitELFABI() || Subtarget.isAIXABI()) {
2917 if (Subtarget.isUsingPCRelativeCalls()) {
2918 SDLoc DL(CP);
2919 EVT Ty = getPointerTy(DAG.getDataLayout());
2920 SDValue ConstPool = DAG.getTargetConstantPool(
2921 C, Ty, CP->getAlign(), CP->getOffset(), PPCII::MO_PCREL_FLAG);
2922 return DAG.getNode(PPCISD::MAT_PCREL_ADDR, DL, Ty, ConstPool);
2923 }
2924 setUsesTOCBasePtr(DAG);
2925 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlign(), 0);
2926 return getTOCEntry(DAG, SDLoc(CP), GA);
2927 }
2928
2929 unsigned MOHiFlag, MOLoFlag;
2930 bool IsPIC = isPositionIndependent();
2931 getLabelAccessInfo(IsPIC, Subtarget, MOHiFlag, MOLoFlag);
2932
2933 if (IsPIC && Subtarget.isSVR4ABI()) {
2934 SDValue GA =
2935 DAG.getTargetConstantPool(C, PtrVT, CP->getAlign(), PPCII::MO_PIC_FLAG);
2936 return getTOCEntry(DAG, SDLoc(CP), GA);
2937 }
2938
2939 SDValue CPIHi =
2940 DAG.getTargetConstantPool(C, PtrVT, CP->getAlign(), 0, MOHiFlag);
2941 SDValue CPILo =
2942 DAG.getTargetConstantPool(C, PtrVT, CP->getAlign(), 0, MOLoFlag);
2943 return LowerLabelRef(CPIHi, CPILo, IsPIC, DAG);
2944}
2945
2946// For 64-bit PowerPC, prefer the more compact relative encodings.
2947// This trades 32 bits per jump table entry for one or two instructions
2948// on the jump site.
2949unsigned PPCTargetLowering::getJumpTableEncoding() const {
2950 if (isJumpTableRelative())
2951 return MachineJumpTableInfo::EK_LabelDifference32;
2952
2953 return TargetLowering::getJumpTableEncoding();
2954}
2955
2956bool PPCTargetLowering::isJumpTableRelative() const {
2957 if (UseAbsoluteJumpTables)
2958 return false;
2959 if (Subtarget.isPPC64() || Subtarget.isAIXABI())
2960 return true;
2961 return TargetLowering::isJumpTableRelative();
2962}
2963
2964SDValue PPCTargetLowering::getPICJumpTableRelocBase(SDValue Table,
2965 SelectionDAG &DAG) const {
2966 if (!Subtarget.isPPC64() || Subtarget.isAIXABI())
2967 return TargetLowering::getPICJumpTableRelocBase(Table, DAG);
2968
2969 switch (getTargetMachine().getCodeModel()) {
2970 case CodeModel::Small:
2971 case CodeModel::Medium:
2972 return TargetLowering::getPICJumpTableRelocBase(Table, DAG);
2973 default:
2974 return DAG.getNode(PPCISD::GlobalBaseReg, SDLoc(),
2975 getPointerTy(DAG.getDataLayout()));
2976 }
2977}
2978
2979const MCExpr *
2980PPCTargetLowering::getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
2981 unsigned JTI,
2982 MCContext &Ctx) const {
2983 if (!Subtarget.isPPC64() || Subtarget.isAIXABI())
2984 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
2985
2986 switch (getTargetMachine().getCodeModel()) {
2987 case CodeModel::Small:
2988 case CodeModel::Medium:
2989 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
2990 default:
2991 return MCSymbolRefExpr::create(MF->getPICBaseSymbol(), Ctx);
2992 }
2993}
2994
2995SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
2996 EVT PtrVT = Op.getValueType();
2997 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
2998
2999 // isUsingPCRelativeCalls() returns true when PCRelative is enabled
3000 if (Subtarget.isUsingPCRelativeCalls()) {
3001 SDLoc DL(JT);
3002 EVT Ty = getPointerTy(DAG.getDataLayout());
3003 SDValue GA =
3004 DAG.getTargetJumpTable(JT->getIndex(), Ty, PPCII::MO_PCREL_FLAG);
3005 SDValue MatAddr = DAG.getNode(PPCISD::MAT_PCREL_ADDR, DL, Ty, GA);
3006 return MatAddr;
3007 }
3008
3009 // 64-bit SVR4 ABI and AIX ABI code are always position-independent.
3010 // The actual address of the GlobalValue is stored in the TOC.
3011 if (Subtarget.is64BitELFABI() || Subtarget.isAIXABI()) {
3012 setUsesTOCBasePtr(DAG);
3013 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
3014 return getTOCEntry(DAG, SDLoc(JT), GA);
3015 }
3016
3017 unsigned MOHiFlag, MOLoFlag;
3018 bool IsPIC = isPositionIndependent();
3019 getLabelAccessInfo(IsPIC, Subtarget, MOHiFlag, MOLoFlag);
3020
3021 if (IsPIC && Subtarget.isSVR4ABI()) {
3022 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
3023 PPCII::MO_PIC_FLAG);
3024 return getTOCEntry(DAG, SDLoc(GA), GA);
3025 }
3026
3027 SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag);
3028 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag);
3029 return LowerLabelRef(JTIHi, JTILo, IsPIC, DAG);
3030}
3031
3032SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op,
3033 SelectionDAG &DAG) const {
3034 EVT PtrVT = Op.getValueType();
3035 BlockAddressSDNode *BASDN = cast<BlockAddressSDNode>(Op);
3036 const BlockAddress *BA = BASDN->getBlockAddress();
3037
3038 // isUsingPCRelativeCalls() returns true when PCRelative is enabled
3039 if (Subtarget.isUsingPCRelativeCalls()) {
3040 SDLoc DL(BASDN);
3041 EVT Ty = getPointerTy(DAG.getDataLayout());
3042 SDValue GA = DAG.getTargetBlockAddress(BA, Ty, BASDN->getOffset(),
3043 PPCII::MO_PCREL_FLAG);
3044 SDValue MatAddr = DAG.getNode(PPCISD::MAT_PCREL_ADDR, DL, Ty, GA);
3045 return MatAddr;
3046 }
3047
3048 // 64-bit SVR4 ABI and AIX ABI code are always position-independent.
3049 // The actual BlockAddress is stored in the TOC.
3050 if (Subtarget.is64BitELFABI() || Subtarget.isAIXABI()) {
3051 setUsesTOCBasePtr(DAG);
3052 SDValue GA = DAG.getTargetBlockAddress(BA, PtrVT, BASDN->getOffset());
3053 return getTOCEntry(DAG, SDLoc(BASDN), GA);
3054 }
3055
3056 // 32-bit position-independent ELF stores the BlockAddress in the .got.
3057 if (Subtarget.is32BitELFABI() && isPositionIndependent())
3058 return getTOCEntry(
3059 DAG, SDLoc(BASDN),
3060 DAG.getTargetBlockAddress(BA, PtrVT, BASDN->getOffset()));
3061
3062 unsigned MOHiFlag, MOLoFlag;
3063 bool IsPIC = isPositionIndependent();
3064 getLabelAccessInfo(IsPIC, Subtarget, MOHiFlag, MOLoFlag);
3065 SDValue TgtBAHi = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOHiFlag);
3066 SDValue TgtBALo = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOLoFlag);
3067 return LowerLabelRef(TgtBAHi, TgtBALo, IsPIC, DAG);
3068}
3069
3070SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
3071 SelectionDAG &DAG) const {
3072 // FIXME: TLS addresses currently use medium model code sequences,
3073 // which is the most useful form. Eventually support for small and
3074 // large models could be added if users need it, at the cost of
3075 // additional complexity.
3076 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
3077 if (DAG.getTarget().useEmulatedTLS())
3078 return LowerToTLSEmulatedModel(GA, DAG);
3079
3080 SDLoc dl(GA);
3081 const GlobalValue *GV = GA->getGlobal();
3082 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3083 bool is64bit = Subtarget.isPPC64();
3084 const Module *M = DAG.getMachineFunction().getFunction().getParent();
3085 PICLevel::Level picLevel = M->getPICLevel();
3086
3087 const TargetMachine &TM = getTargetMachine();
3088 TLSModel::Model Model = TM.getTLSModel(GV);
3089
3090 if (Model == TLSModel::LocalExec) {
3091 if (Subtarget.isUsingPCRelativeCalls()) {
3092 SDValue TLSReg = DAG.getRegister(PPC::X13, MVT::i64);
3093 SDValue TGA = DAG.getTargetGlobalAddress(
3094 GV, dl, PtrVT, 0, (PPCII::MO_PCREL_FLAG | PPCII::MO_TPREL_FLAG));
3095 SDValue MatAddr =
3096 DAG.getNode(PPCISD::TLS_LOCAL_EXEC_MAT_ADDR, dl, PtrVT, TGA);
3097 return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TLSReg, MatAddr);
3098 }
3099
3100 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
3101 PPCII::MO_TPREL_HA);
3102 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
3103 PPCII::MO_TPREL_LO);
3104 SDValue TLSReg = is64bit ? DAG.getRegister(PPC::X13, MVT::i64)
3105 : DAG.getRegister(PPC::R2, MVT::i32);
3106
3107 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, TGAHi, TLSReg);
3108 return DAG.getNode(PPCISD::Lo, dl, PtrVT, TGALo, Hi);
3109 }
3110
3111 if (Model == TLSModel::InitialExec) {
3112 bool IsPCRel = Subtarget.isUsingPCRelativeCalls();
3113 SDValue TGA = DAG.getTargetGlobalAddress(
3114 GV, dl, PtrVT, 0, IsPCRel ? PPCII::MO_GOT_TPREL_PCREL_FLAG : 0);
3115 SDValue TGATLS = DAG.getTargetGlobalAddress(
3116 GV, dl, PtrVT, 0,
3117 IsPCRel ? (PPCII::MO_TLS | PPCII::MO_PCREL_FLAG) : PPCII::MO_TLS);
3118 SDValue TPOffset;
3119 if (IsPCRel) {
3120 SDValue MatPCRel = DAG.getNode(PPCISD::MAT_PCREL_ADDR, dl, PtrVT, TGA);
3121 TPOffset = DAG.getLoad(MVT::i64, dl, DAG.getEntryNode(), MatPCRel,
3122 MachinePointerInfo());
3123 } else {
3124 SDValue GOTPtr;
3125 if (is64bit) {
3126 setUsesTOCBasePtr(DAG);
3127 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
3128 GOTPtr =
3129 DAG.getNode(PPCISD::ADDIS_GOT_TPREL_HA, dl, PtrVT, GOTReg, TGA);
3130 } else {
3131 if (!TM.isPositionIndependent())
3132 GOTPtr = DAG.getNode(PPCISD::PPC32_GOT, dl, PtrVT);
3133 else if (picLevel == PICLevel::SmallPIC)
3134 GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT);
3135 else
3136 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
3137 }
3138 TPOffset = DAG.getNode(PPCISD::LD_GOT_TPREL_L, dl, PtrVT, TGA, GOTPtr);
3139 }
3140 return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TPOffset, TGATLS);
3141 }
3142
3143 if (Model == TLSModel::GeneralDynamic) {
3144 if (Subtarget.isUsingPCRelativeCalls()) {
3145 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
3146 PPCII::MO_GOT_TLSGD_PCREL_FLAG);
3147 return DAG.getNode(PPCISD::TLS_DYNAMIC_MAT_PCREL_ADDR, dl, PtrVT, TGA);
3148 }
3149
3150 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
3151 SDValue GOTPtr;
3152 if (is64bit) {
3153 setUsesTOCBasePtr(DAG);
3154 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
3155 GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSGD_HA, dl, PtrVT,
3156 GOTReg, TGA);
3157 } else {
3158 if (picLevel == PICLevel::SmallPIC)
3159 GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT);
3160 else
3161 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
3162 }
3163 return DAG.getNode(PPCISD::ADDI_TLSGD_L_ADDR, dl, PtrVT,
3164 GOTPtr, TGA, TGA);
3165 }
3166
3167 if (Model == TLSModel::LocalDynamic) {
3168 if (Subtarget.isUsingPCRelativeCalls()) {
3169 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
3170 PPCII::MO_GOT_TLSLD_PCREL_FLAG);
3171 SDValue MatPCRel =
3172 DAG.getNode(PPCISD::TLS_DYNAMIC_MAT_PCREL_ADDR, dl, PtrVT, TGA);
3173 return DAG.getNode(PPCISD::PADDI_DTPREL, dl, PtrVT, MatPCRel, TGA);
3174 }
3175
3176 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
3177 SDValue GOTPtr;
3178 if (is64bit) {
3179 setUsesTOCBasePtr(DAG);
3180 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
3181 GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSLD_HA, dl, PtrVT,
3182 GOTReg, TGA);
3183 } else {
3184 if (picLevel == PICLevel::SmallPIC)
3185 GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT);
3186 else
3187 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
3188 }
3189 SDValue TLSAddr = DAG.getNode(PPCISD::ADDI_TLSLD_L_ADDR, dl,
3190 PtrVT, GOTPtr, TGA, TGA);
3191 SDValue DtvOffsetHi = DAG.getNode(PPCISD::ADDIS_DTPREL_HA, dl,
3192 PtrVT, TLSAddr, TGA);
3193 return DAG.getNode(PPCISD::ADDI_DTPREL_L, dl, PtrVT, DtvOffsetHi, TGA);
3194 }
3195
3196 llvm_unreachable("Unknown TLS model!")::llvm::llvm_unreachable_internal("Unknown TLS model!", "/build/llvm-toolchain-snapshot-12~++20201124111112+7b5254223ac/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 3196)
;
3197}
3198
3199SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
3200 SelectionDAG &DAG) const {
3201 EVT PtrVT = Op.getValueType();
3202 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
3203 SDLoc DL(GSDN);
3204 const GlobalValue *GV = GSDN->getGlobal();
3205
3206 // 64-bit SVR4 ABI & AIX ABI code is always position-independent.
3207 // The actual address of the GlobalValue is stored in the TOC.
3208 if (Subtarget.is64BitELFABI() || Subtarget.isAIXABI()) {
3209 if (Subtarget.isUsingPCRelativeCalls()) {
3210 EVT Ty = getPointerTy(DAG.getDataLayout());
3211 if (isAccessedAsGotIndirect(Op)) {
3212 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, Ty, GSDN->getOffset(),
3213 PPCII::MO_PCREL_FLAG |
3214 PPCII::MO_GOT_FLAG);
3215 SDValue MatPCRel = DAG.getNode(PPCISD::MAT_PCREL_ADDR, DL, Ty, GA);
3216 SDValue Load = DAG.getLoad(MVT::i64, DL, DAG.getEntryNode(), MatPCRel,
3217 MachinePointerInfo());
3218 return Load;
3219 } else {
3220 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, Ty, GSDN->getOffset(),
3221 PPCII::MO_PCREL_FLAG);
3222 return DAG.getNode(PPCISD::MAT_PCREL_ADDR, DL, Ty, GA);
3223 }
3224 }
3225 setUsesTOCBasePtr(DAG);
3226 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset());
3227 return getTOCEntry(DAG, DL, GA);
3228 }
3229
3230 unsigned MOHiFlag, MOLoFlag;
3231 bool IsPIC = isPositionIndependent();
3232 getLabelAccessInfo(IsPIC, Subtarget, MOHiFlag, MOLoFlag, GV);
3233
3234 if (IsPIC && Subtarget.isSVR4ABI()) {
3235 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT,
3236 GSDN->getOffset(),
3237 PPCII::MO_PIC_FLAG);
3238 return getTOCEntry(DAG, DL, GA);
3239 }
3240
3241 SDValue GAHi =
3242 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag);
3243 SDValue GALo =
3244 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag);
3245
3246 return LowerLabelRef(GAHi, GALo, IsPIC, DAG);
3247}
3248
3249SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
3250 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
3251 SDLoc dl(Op);
3252
3253 if (Op.getValueType() == MVT::v2i64) {
3254 // When the operands themselves are v2i64 values, we need to do something
3255 // special because VSX has no underlying comparison operations for these.
3256 if (Op.getOperand(0).getValueType() == MVT::v2i64) {
3257 // Equality can be handled by casting to the legal type for Altivec
3258 // comparisons, everything else needs to be expanded.
3259 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
3260 return DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
3261 DAG.getSetCC(dl, MVT::v4i32,
3262 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0)),
3263 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(1)),
3264 CC));
3265 }
3266
3267 return SDValue();
3268 }
3269
3270 // We handle most of these in the usual way.
3271 return Op;
3272 }
3273
3274 // If we're comparing for equality to zero, expose the fact that this is
3275 // implemented as a ctlz/srl pair on ppc, so that the dag combiner can
3276 // fold the new nodes.
3277 if (SDValue V = lowerCmpEqZeroToCtlzSrl(Op, DAG))
3278 return V;
3279
3280 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
3281 // Leave comparisons against 0 and -1 alone for now, since they're usually
3282 // optimized. FIXME: revisit this when we can custom lower all setcc
3283 // optimizations.
3284 if (C->isAllOnesValue() || C->isNullValue())
3285 return SDValue();
3286 }
3287
3288 // If we have an integer seteq/setne, turn it into a compare against zero
3289 // by xor'ing the rhs with the lhs, which is faster than setting a
3290 // condition register, reading it back out, and masking the correct bit. The
3291 // normal approach here uses sub to do this instead of xor. Using xor exposes
3292 // the result to other bit-twiddling opportunities.
3293 EVT LHSVT = Op.getOperand(0).getValueType();
3294 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
3295 EVT VT = Op.getValueType();
3296 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0),
3297 Op.getOperand(1));
3298 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, dl, LHSVT), CC);
3299 }
3300 return SDValue();
3301}
3302
3303SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
3304 SDNode *Node = Op.getNode();
3305 EVT VT = Node->getValueType(0);
3306 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3307 SDValue InChain = Node->getOperand(0);
3308 SDValue VAListPtr = Node->getOperand(1);
3309 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
3310 SDLoc dl(Node);
3311
3312 assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only")((!Subtarget.isPPC64() && "LowerVAARG is PPC32 only")
? static_cast<void> (0) : __assert_fail ("!Subtarget.isPPC64() && \"LowerVAARG is PPC32 only\""
, "/build/llvm-toolchain-snapshot-12~++20201124111112+7b5254223ac/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 3312, __PRETTY_FUNCTION__))
;
3313
3314 // gpr_index
3315 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
3316 VAListPtr, MachinePointerInfo(SV), MVT::i8);
3317 InChain = GprIndex.getValue(1);
3318
3319 if (VT == MVT::i64) {
3320 // Check if GprIndex is even
3321 SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex,
3322 DAG.getConstant(1, dl, MVT::i32));
3323 SDValue CC64 = DAG.getSetCC(dl, MVT::i32, GprAnd,
3324 DAG.getConstant(0, dl, MVT::i32), ISD::SETNE);
3325 SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex,
3326 DAG.getConstant(1, dl, MVT::i32));
3327 // Align GprIndex to be even if it isn't
3328 GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne,
3329 GprIndex);
3330 }
3331
3332 // fpr index is 1 byte after gpr
3333 SDValue FprPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
3334 DAG.getConstant(1, dl, MVT::i32));
3335
3336 // fpr
3337 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
3338 FprPtr, MachinePointerInfo(SV), MVT::i8);
3339 InChain = FprIndex.getValue(1);
3340
3341 SDValue RegSaveAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
3342 DAG.getConstant(8, dl, MVT::i32));
3343
3344 SDValue OverflowAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
3345 DAG.getConstant(4, dl, MVT::i32));
3346
3347 // areas
3348 SDValue OverflowArea =
3349 DAG.getLoad(MVT::i32, dl, InChain, OverflowAreaPtr, MachinePointerInfo());
3350 InChain = OverflowArea.getValue(1);
3351
3352 SDValue RegSaveArea =
3353 DAG.getLoad(MVT::i32, dl, InChain, RegSaveAreaPtr, MachinePointerInfo());
3354 InChain = RegSaveArea.getValue(1);
3355
3356 // select overflow_area if index > 8
3357 SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex,
3358 DAG.getConstant(8, dl, MVT::i32), ISD::SETLT);
3359
3360 // adjustment constant gpr_index * 4/8
3361 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32,
3362 VT.isInteger() ? GprIndex : FprIndex,
3363 DAG.getConstant(VT.isInteger() ? 4 : 8, dl,
3364 MVT::i32));
3365
3366 // OurReg = RegSaveArea + RegConstant
3367 SDValue OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, RegSaveArea,
3368 RegConstant);
3369
3370 // Floating types are 32 bytes into RegSaveArea
3371 if (VT.isFloatingPoint())
3372 OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, OurReg,
3373 DAG.getConstant(32, dl, MVT::i32));
3374
3375 // increase {f,g}pr_index by 1 (or 2 if VT is i64)
3376 SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3377 VT.isInteger() ? GprIndex : FprIndex,
3378 DAG.getConstant(VT == MVT::i64 ? 2 : 1, dl,
3379 MVT::i32));
3380
3381 InChain = DAG.getTruncStore(InChain, dl, IndexPlus1,
3382 VT.isInteger() ? VAListPtr : FprPtr,
3383 MachinePointerInfo(SV), MVT::i8);
3384
3385 // determine if we should load from reg_save_area or overflow_area
3386 SDValue Result = DAG.getNode(ISD::SELECT, dl, PtrVT, CC, OurReg, OverflowArea);
3387
3388 // increase overflow_area by 4/8 if gpr/fpr > 8
3389 SDValue OverflowAreaPlusN = DAG.getNode(ISD::ADD, dl, PtrVT, OverflowArea,
3390 DAG.getConstant(VT.isInteger() ? 4 : 8,
3391 dl, MVT::i32));
3392
3393 OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea,
3394 OverflowAreaPlusN);
3395
3396 InChain = DAG.getTruncStore(InChain, dl, OverflowArea, OverflowAreaPtr,
3397 MachinePointerInfo(), MVT::i32);
3398
3399 return DAG.getLoad(VT, dl, InChain, Result, MachinePointerInfo());
3400}
3401
3402SDValue PPCTargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const {
3403 assert(!Subtarget.isPPC64() && "LowerVACOPY is PPC32 only")((!Subtarget.isPPC64() && "LowerVACOPY is PPC32 only"
) ? static_cast<void> (0) : __assert_fail ("!Subtarget.isPPC64() && \"LowerVACOPY is PPC32 only\""
, "/build/llvm-toolchain-snapshot-12~++20201124111112+7b5254223ac/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 3403, __PRETTY_FUNCTION__))
;
3404
3405 // We have to copy the entire va_list struct:
3406 // 2*sizeof(char) + 2 Byte alignment + 2*sizeof(char*) = 12 Byte
3407 return DAG.getMemcpy(Op.getOperand(0), Op, Op.getOperand(1), Op.getOperand(2),
3408 DAG.getConstant(12, SDLoc(Op), MVT::i32), Align(8),
3409 false, true, false, MachinePointerInfo(),
3410 MachinePointerInfo());
3411}
3412
3413SDValue PPCTargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
3414 SelectionDAG &DAG) const {
3415 if (Subtarget.isAIXABI())
3416 report_fatal_error("ADJUST_TRAMPOLINE operation is not supported on AIX.");
3417
3418 return Op.getOperand(0);
3419}
3420
3421SDValue PPCTargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
3422 SelectionDAG &DAG) const {
3423 if (Subtarget.isAIXABI())
3424 report_fatal_error("INIT_TRAMPOLINE operation is not supported on AIX.");
3425
3426 SDValue Chain = Op.getOperand(0);
3427 SDValue Trmp = Op.getOperand(1); // trampoline
3428 SDValue FPtr = Op.getOperand(2); // nested function
3429 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
3430 SDLoc dl(Op);
3431
3432 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3433 bool isPPC64 = (PtrVT == MVT::i64);
3434 Type *IntPtrTy = DAG.getDataLayout().getIntPtrType(*DAG.getContext());
3435
3436 TargetLowering::ArgListTy Args;
3437 TargetLowering::ArgListEntry Entry;
3438
3439 Entry.Ty = IntPtrTy;
3440 Entry.Node = Trmp; Args.push_back(Entry);
3441
3442 // TrampSize == (isPPC64 ? 48 : 40);
3443 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40, dl,
3444 isPPC64 ? MVT::i64 : MVT::i32);
3445 Args.push_back(Entry);
3446
3447 Entry.Node = FPtr; Args.push_back(Entry);
3448 Entry.Node = Nest; Args.push_back(Entry);
3449
3450 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
3451 TargetLowering::CallLoweringInfo CLI(DAG);
3452 CLI.setDebugLoc(dl).setChain(Chain).setLibCallee(
3453 CallingConv::C, Type::getVoidTy(*DAG.getContext()),
3454 DAG.getExternalSymbol("__trampoline_setup", PtrVT), std::move(Args));
3455
3456 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
3457 return CallResult.second;
3458}
3459
3460SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
3461 MachineFunction &MF = DAG.getMachineFunction();
3462 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
3463 EVT PtrVT = getPointerTy(MF.getDataLayout());
3464
3465 SDLoc dl(Op);
3466
3467 if (Subtarget.isPPC64() || Subtarget.isAIXABI()) {
3468 // vastart just stores the address of the VarArgsFrameIndex slot into the
3469 // memory location argument.
3470 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
3471 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3472 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
3473 MachinePointerInfo(SV));
3474 }
3475
3476 // For the 32-bit SVR4 ABI we follow the layout of the va_list struct.
3477 // We suppose the given va_list is already allocated.
3478 //
3479 // typedef struct {
3480 // char gpr; /* index into the array of 8 GPRs
3481 // * stored in the register save area
3482 // * gpr=0 corresponds to r3,
3483 // * gpr=1 to r4, etc.
3484 // */
3485 // char fpr; /* index into the array of 8 FPRs
3486 // * stored in the register save area
3487 // * fpr=0 corresponds to f1,
3488 // * fpr=1 to f2, etc.
3489 // */
3490 // char *overflow_arg_area;
3491 // /* location on stack that holds
3492 // * the next overflow argument
3493 // */
3494 // char *reg_save_area;
3495 // /* where r3:r10 and f1:f8 (if saved)
3496 // * are stored
3497 // */
3498 // } va_list[1];
3499
3500 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), dl, MVT::i32);
3501 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), dl, MVT::i32);
3502 SDValue StackOffsetFI = DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(),
3503 PtrVT);
3504 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
3505 PtrVT);
3506
3507 uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
3508 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, dl, PtrVT);
3509
3510 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
3511 SDValue ConstStackOffset = DAG.getConstant(StackOffset, dl, PtrVT);
3512
3513 uint64_t FPROffset = 1;
3514 SDValue ConstFPROffset = DAG.getConstant(FPROffset, dl, PtrVT);
3515
3516 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3517
3518 // Store first byte : number of int regs
3519 SDValue firstStore =
3520 DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR, Op.getOperand(1),
3521 MachinePointerInfo(SV), MVT::i8);
3522 uint64_t nextOffset = FPROffset;
3523 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
3524 ConstFPROffset);
3525
3526 // Store second byte : number of float regs
3527 SDValue secondStore =
3528 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr,
3529 MachinePointerInfo(SV, nextOffset), MVT::i8);
3530 nextOffset += StackOffset;
3531 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
3532
3533 // Store second word : arguments given on stack
3534 SDValue thirdStore = DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr,
3535 MachinePointerInfo(SV, nextOffset));
3536 nextOffset += FrameOffset;
3537 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
3538
3539 // Store third word : arguments given in registers
3540 return DAG.getStore(thirdStore, dl, FR, nextPtr,
3541 MachinePointerInfo(SV, nextOffset));
3542}
3543
3544/// FPR - The set of FP registers that should be allocated for arguments
3545/// on Darwin and AIX.
3546static const MCPhysReg FPR[] = {PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5,
3547 PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10,
3548 PPC::F11, PPC::F12, PPC::F13};
3549
3550/// CalculateStackSlotSize - Calculates the size reserved for this argument on
3551/// the stack.
3552static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags,
3553 unsigned PtrByteSize) {
3554 unsigned ArgSize = ArgVT.getStoreSize();
3555 if (Flags.isByVal())
3556 ArgSize = Flags.getByValSize();
3557
3558 // Round up to multiples of the pointer size, except for array members,
3559 // which are always packed.
3560 if (!Flags.isInConsecutiveRegs())
3561 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3562
3563 return ArgSize;
3564}
3565
3566/// CalculateStackSlotAlignment - Calculates the alignment of this argument
3567/// on the stack.
3568static Align CalculateStackSlotAlignment(EVT ArgVT, EVT OrigVT,
3569 ISD::ArgFlagsTy Flags,
3570 unsigned PtrByteSize) {
3571 Align Alignment(PtrByteSize);
3572
3573 // Altivec parameters are padded to a 16 byte boundary.
3574 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
3575 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
3576 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64 ||
3577 ArgVT == MVT::v1i128 || ArgVT == MVT::f128)
3578 Alignment = Align(16);
3579
3580 // ByVal parameters are aligned as requested.
3581 if (Flags.isByVal()) {
3582 auto BVAlign = Flags.getNonZeroByValAlign();
3583 if (BVAlign > PtrByteSize) {
3584 if (BVAlign.value() % PtrByteSize != 0)
3585 llvm_unreachable(::llvm::llvm_unreachable_internal("ByVal alignment is not a multiple of the pointer size"
, "/build/llvm-toolchain-snapshot-12~++20201124111112+7b5254223ac/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 3586)
3586 "ByVal alignment is not a multiple of the pointer size")::llvm::llvm_unreachable_internal("ByVal alignment is not a multiple of the pointer size"
, "/build/llvm-toolchain-snapshot-12~++20201124111112+7b5254223ac/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 3586)
;
3587
3588 Alignment = BVAlign;
3589 }
3590 }
3591
3592 // Array members are always packed to their original alignment.
3593 if (Flags.isInConsecutiveRegs()) {
3594 // If the array member was split into multiple registers, the first
3595 // needs to be aligned to the size of the full type. (Except for
3596 // ppcf128, which is only aligned as its f64 components.)
3597 if (Flags.isSplit() && OrigVT != MVT::ppcf128)
3598 Alignment = Align(OrigVT.getStoreSize());
3599 else
3600 Alignment = Align(ArgVT.getStoreSize());
3601 }
3602
3603 return Alignment;
3604}
3605
3606/// CalculateStackSlotUsed - Return whether this argument will use its
3607/// stack slot (instead of being passed in registers). ArgOffset,
3608/// AvailableFPRs, and AvailableVRs must hold the current argument
3609/// position, and will be updated to account for this argument.
3610static bool CalculateStackSlotUsed(EVT ArgVT, EVT OrigVT, ISD::ArgFlagsTy Flags,
3611 unsigned PtrByteSize, unsigned LinkageSize,
3612 unsigned ParamAreaSize, unsigned &ArgOffset,
3613 unsigned &AvailableFPRs,
3614 unsigned &AvailableVRs) {
3615 bool UseMemory = false;
3616
3617 // Respect alignment of argument on the stack.
3618 Align Alignment =
3619 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
3620 ArgOffset = alignTo(ArgOffset, Alignment);
3621 // If there's no space left in the argument save area, we must
3622 // use memory (this check also catches zero-sized arguments).
3623 if (ArgOffset >= LinkageSize + ParamAreaSize)
3624 UseMemory = true;
3625
3626 // Allocate argument on the stack.
3627 ArgOffset += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
3628 if (Flags.isInConsecutiveRegsLast())
3629 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3630 // If we overran the argument save area, we must use memory
3631 // (this check catches arguments passed partially in memory)
3632 if (ArgOffset > LinkageSize + ParamAreaSize)
3633 UseMemory = true;
3634
3635 // However, if the argument is actually passed in an FPR or a VR,
3636 // we don't use memory after all.
3637 if (!Flags.isByVal()) {
3638 if (ArgVT == MVT::f32 || ArgVT == MVT::f64)
3639 if (AvailableFPRs > 0) {
3640 --AvailableFPRs;
3641 return false;
3642 }
3643 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
3644 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
3645 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64 ||
3646 ArgVT == MVT::v1i128 || ArgVT == MVT::f128)
3647 if (AvailableVRs > 0) {
3648 --AvailableVRs;
3649 return false;
3650 }
3651 }
3652
3653 return UseMemory;
3654}
3655
3656/// EnsureStackAlignment - Round stack frame size up from NumBytes to
3657/// ensure minimum alignment required for target.
3658static unsigned EnsureStackAlignment(const PPCFrameLowering *Lowering,
3659 unsigned NumBytes) {
3660 return alignTo(NumBytes, Lowering->getStackAlign());
3661}
3662
3663SDValue PPCTargetLowering::LowerFormalArguments(
3664 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
3665 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
3666 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
3667 if (Subtarget.isAIXABI())
3668 return LowerFormalArguments_AIX(Chain, CallConv, isVarArg, Ins, dl, DAG,
3669 InVals);
3670 if (Subtarget.is64BitELFABI())
3671 return LowerFormalArguments_64SVR4(Chain, CallConv, isVarArg, Ins, dl, DAG,
3672 InVals);
3673 if (Subtarget.is32BitELFABI())
3674 return LowerFormalArguments_32SVR4(Chain, CallConv, isVarArg, Ins, dl, DAG,
3675 InVals);
3676
3677 return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins, dl, DAG,
3678 InVals);
3679}
3680
3681SDValue PPCTargetLowering::LowerFormalArguments_32SVR4(
3682 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
3683 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
3684 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
3685
3686 // 32-bit SVR4 ABI Stack Frame Layout:
3687 // +-----------------------------------+
3688 // +--> | Back chain |
3689 // | +-----------------------------------+
3690 // | | Floating-point register save area |
3691 // | +-----------------------------------+
3692 // | | General register save area |
3693 // | +-----------------------------------+
3694 // | | CR save word |
3695 // | +-----------------------------------+
3696 // | | VRSAVE save word |
3697 // | +-----------------------------------+
3698 // | | Alignment padding |
3699 // | +-----------------------------------+
3700 // | | Vector register save area |
3701 // | +-----------------------------------+
3702 // | | Local variable space |
3703 // | +-----------------------------------+
3704 // | | Parameter list area |
3705 // | +-----------------------------------+
3706 // | | LR save word |
3707 // | +-----------------------------------+
3708 // SP--> +--- | Back chain |
3709 // +-----------------------------------+
3710 //
3711 // Specifications:
3712 // System V Application Binary Interface PowerPC Processor Supplement
3713 // AltiVec Technology Programming Interface Manual
3714
3715 MachineFunction &MF = DAG.getMachineFunction();
3716 MachineFrameInfo &MFI = MF.getFrameInfo();
3717 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
3718
3719 EVT PtrVT = getPointerTy(MF.getDataLayout());
3720 // Potential tail calls could cause overwriting of argument stack slots.
3721 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
3722 (CallConv == CallingConv::Fast));
3723 const Align PtrAlign(4);
3724
3725 // Assign locations to all of the incoming arguments.
3726 SmallVector<CCValAssign, 16> ArgLocs;
3727 PPCCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
3728 *DAG.getContext());
3729
3730 // Reserve space for the linkage area on the stack.
3731 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
3732 CCInfo.AllocateStack(LinkageSize, PtrAlign);
3733 if (useSoftFloat())
3734 CCInfo.PreAnalyzeFormalArguments(Ins);
3735
3736 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4);
3737 CCInfo.clearWasPPCF128();
3738
3739 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3740 CCValAssign &VA = ArgLocs[i];
3741
3742 // Arguments stored in registers.
3743 if (VA.isRegLoc()) {
3744 const TargetRegisterClass *RC;
3745 EVT ValVT = VA.getValVT();
3746
3747 switch (ValVT.getSimpleVT().SimpleTy) {
3748 default:
3749 llvm_unreachable("ValVT not supported by formal arguments Lowering")::llvm::llvm_unreachable_internal("ValVT not supported by formal arguments Lowering"
, "/build/llvm-toolchain-snapshot-12~++20201124111112+7b5254223ac/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 3749)
;
3750 case MVT::i1:
3751 case MVT::i32:
3752 RC = &PPC::GPRCRegClass;
3753 break;
3754 case MVT::f32:
3755 if (Subtarget.hasP8Vector())
3756 RC = &PPC::VSSRCRegClass;
3757 else if (Subtarget.hasSPE())
3758 RC = &PPC::GPRCRegClass;
3759 else
3760 RC = &PPC::F4RCRegClass;
3761 break;
3762 case MVT::f64:
3763 if (Subtarget.hasVSX())
3764 RC = &PPC::VSFRCRegClass;
3765 else if (Subtarget.hasSPE())
3766 // SPE passes doubles in GPR pairs.
3767 RC = &PPC::GPRCRegClass;
3768 else
3769 RC = &PPC::F8RCRegClass;
3770 break;
3771 case MVT::v16i8:
3772 case MVT::v8i16:
3773 case MVT::v4i32:
3774 RC = &PPC::VRRCRegClass;
3775 break;
3776 case MVT::v4f32:
3777 RC = &PPC::VRRCRegClass;
3778 break;
3779 case MVT::v2f64:
3780 case MVT::v2i64:
3781 RC = &PPC::VRRCRegClass;
3782 break;
3783 }
3784
3785 SDValue ArgValue;
3786 // Transform the arguments stored in physical registers into
3787 // virtual ones.
3788 if (VA.getLocVT() == MVT::f64 && Subtarget.hasSPE()) {
3789 assert(i + 1 < e && "No second half of double precision argument")((i + 1 < e && "No second half of double precision argument"
) ? static_cast<void> (0) : __assert_fail ("i + 1 < e && \"No second half of double precision argument\""
, "/build/llvm-toolchain-snapshot-12~++20201124111112+7b5254223ac/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 3789, __PRETTY_FUNCTION__))
;
3790 unsigned RegLo = MF.addLiveIn(VA.getLocReg(), RC);
3791 unsigned RegHi = MF.addLiveIn(ArgLocs[++i].getLocReg(), RC);
3792 SDValue ArgValueLo = DAG.getCopyFromReg(Chain, dl, RegLo, MVT::i32);
3793 SDValue ArgValueHi = DAG.getCopyFromReg(Chain, dl, RegHi, MVT::i32);
3794 if (!Subtarget.isLittleEndian())
3795 std::swap (ArgValueLo, ArgValueHi);
3796 ArgValue = DAG.getNode(PPCISD::BUILD_SPE64, dl, MVT::f64, ArgValueLo,
3797 ArgValueHi);
3798 } else {
3799 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
3800 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg,
3801 ValVT == MVT::i1 ? MVT::i32 : ValVT);
3802 if (ValVT == MVT::i1)
3803 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgValue);
3804 }
3805
3806 InVals.push_back(ArgValue);
3807 } else {
3808 // Argument stored in memory.
3809 assert(VA.isMemLoc())((VA.isMemLoc()) ? static_cast<void> (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-12~++20201124111112+7b5254223ac/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 3809, __PRETTY_FUNCTION__))
;
3810
3811 // Get the extended size of the argument type in stack
3812 unsigned ArgSize = VA.getLocVT().getStoreSize();
3813 // Get the actual size of the argument type
3814 unsigned ObjSize = VA.getValVT().getStoreSize();
3815 unsigned ArgOffset = VA.getLocMemOffset();
3816 // Stack objects in PPC32 are right justified.
3817 ArgOffset += ArgSize - ObjSize;
3818 int FI = MFI.CreateFixedObject(ArgSize, ArgOffset, isImmutable);
3819
3820 // Create load nodes to retrieve arguments from the stack.
3821 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3822 InVals.push_back(
3823 DAG.getLoad(VA.getValVT(), dl, Chain, FIN, MachinePointerInfo()));
3824 }
3825 }
3826
3827 // Assign locations to all of the incoming aggregate by value arguments.
3828 // Aggregates passed by value are stored in the local variable space of the
3829 // caller's stack frame, right above the parameter list area.
3830 SmallVector<CCValAssign, 16> ByValArgLocs;
3831 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3832 ByValArgLocs, *DAG.getContext());
3833
3834 // Reserve stack space for the allocations in CCInfo.
3835 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrAlign);
3836
3837 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4_ByVal);
3838
3839 // Area that is at least reserved in the caller of this function.
3840 unsigned MinReservedArea = CCByValInfo.getNextStackOffset();
3841 MinReservedArea = std::max(MinReservedArea, LinkageSize);
3842
3843 // Set the size that is at least reserved in caller of this function. Tail
3844 // call optimized function's reserved stack space needs to be aligned so that
3845 // taking the difference between two stack areas will result in an aligned
3846 // stack.
3847 MinReservedArea =
3848 EnsureStackAlignment(Subtarget.getFrameLowering(), MinReservedArea);
3849 FuncInfo->setMinReservedArea(MinReservedArea);
3850
3851 SmallVector<SDValue, 8> MemOps;
3852
3853 // If the function takes variable number of arguments, make a frame index for
3854 // the start of the first vararg value... for expansion of llvm.va_start.
3855 if (isVarArg) {
3856 static const MCPhysReg GPArgRegs[] = {
3857 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
3858 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
3859 };
3860 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
3861
3862 static const MCPhysReg FPArgRegs[] = {
3863 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
3864 PPC::F8
3865 };
3866 unsigned NumFPArgRegs = array_lengthof(FPArgRegs);
3867
3868 if (useSoftFloat() || hasSPE())
3869 NumFPArgRegs = 0;
3870
3871 FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs));
3872 FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs));
3873
3874 // Make room for NumGPArgRegs and NumFPArgRegs.
3875 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 +
3876 NumFPArgRegs * MVT(MVT::f64).getSizeInBits()/8;
3877
3878 FuncInfo->setVarArgsStackOffset(
3879 MFI.CreateFixedObject(PtrVT.getSizeInBits()/8,
3880 CCInfo.getNextStackOffset(), true));
3881
3882 FuncInfo->setVarArgsFrameIndex(
3883 MFI.CreateStackObject(Depth, Align(8), false));
3884 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
3885
3886 // The fixed integer arguments of a variadic function are stored to the
3887 // VarArgsFrameIndex on the stack so that they may be loaded by
3888 // dereferencing the result of va_next.
3889 for (unsigned GPRIndex = 0; GPRIndex != NumGPArgRegs; ++GPRIndex) {
3890 // Get an existing live-in vreg, or add a new one.
3891 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]);
3892 if (!VReg)
3893 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
3894
3895 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3896 SDValue Store =
3897 DAG.getStore(Val.getValue(1), dl, Val, FIN, MachinePointerInfo());
3898 MemOps.push_back(Store);
3899 // Increment the address by four for the next argument to store
3900 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, dl, PtrVT);
3901 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
3902 }
3903
3904 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6
3905 // is set.
3906 // The double arguments are stored to the VarArgsFrameIndex
3907 // on the stack.
3908 for (unsigned FPRIndex = 0; FPRIndex != NumFPArgRegs; ++FPRIndex) {
3909 // Get an existing live-in vreg, or add a new one.
3910 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]);
3911 if (!VReg)
3912 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
3913
3914 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
3915 SDValue Store =
3916 DAG.getStore(Val.getValue(1), dl, Val, FIN, MachinePointerInfo());
3917 MemOps.push_back(Store);
3918 // Increment the address by eight for the next argument to store
3919 SDValue PtrOff = DAG.getConstant(MVT(MVT::f64).getSizeInBits()/8, dl,
3920 PtrVT);
3921 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
3922 }
3923 }
3924
3925 if (!MemOps.empty())
3926 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
3927
3928 return Chain;
3929}
3930
3931// PPC64 passes i8, i16, and i32 values in i64 registers. Promote
3932// value to MVT::i64 and then truncate to the correct register size.
3933SDValue PPCTargetLowering::extendArgForPPC64(ISD::ArgFlagsTy Flags,
3934 EVT ObjectVT, SelectionDAG &DAG,
3935 SDValue ArgVal,
3936 const SDLoc &dl) const {
3937 if (Flags.isSExt())
3938 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
3939 DAG.getValueType(ObjectVT));
3940 else if (Flags.isZExt())
3941 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
3942 DAG.getValueType(ObjectVT));
3943
3944 return DAG.getNode(ISD::TRUNCATE, dl, ObjectVT, ArgVal);
3945}
3946
3947SDValue PPCTargetLowering::LowerFormalArguments_64SVR4(
3948 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
3949 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
3950 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
3951 // TODO: add description of PPC stack frame format, or at least some docs.
3952 //
3953 bool isELFv2ABI = Subtarget.isELFv2ABI();
3954 bool isLittleEndian = Subtarget.isLittleEndian();
3955 MachineFunction &MF = DAG.getMachineFunction();
3956 MachineFrameInfo &MFI = MF.getFrameInfo();
3957 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
3958
3959 assert(!(CallConv == CallingConv::Fast && isVarArg) &&((!(CallConv == CallingConv::Fast && isVarArg) &&
"fastcc not supported on varargs functions") ? static_cast<
void> (0) : __assert_fail ("!(CallConv == CallingConv::Fast && isVarArg) && \"fastcc not supported on varargs functions\""
, "/build/llvm-toolchain-snapshot-12~++20201124111112+7b5254223ac/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 3960, __PRETTY_FUNCTION__))
3960 "fastcc not supported on varargs functions")((!(CallConv == CallingConv::Fast && isVarArg) &&
"fastcc not supported on varargs functions") ? static_cast<
void> (0) : __assert_fail ("!(CallConv == CallingConv::Fast && isVarArg) && \"fastcc not supported on varargs functions\""
, "/build/llvm-toolchain-snapshot-12~++20201124111112+7b5254223ac/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 3960, __PRETTY_FUNCTION__))
;
3961
3962 EVT PtrVT = getPointerTy(MF.getDataLayout());
3963 // Potential tail calls could cause overwriting of argument stack slots.
3964 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
3965 (CallConv == CallingConv::Fast));
3966 unsigned PtrByteSize = 8;
3967 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
3968
3969 static const MCPhysReg GPR[] = {
3970 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
3971 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
3972 };
3973 static const MCPhysReg VR[] = {
3974 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
3975 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
3976 };
3977
3978 const unsigned Num_GPR_Regs = array_lengthof(GPR);
3979 const unsigned Num_FPR_Regs = useSoftFloat() ? 0 : 13;
3980 const unsigned Num_VR_Regs = array_lengthof(VR);
3981
3982 // Do a first pass over the arguments to determine whether the ABI
3983 // guarantees that our caller has allocated the parameter save area
3984 // on its stack frame. In the ELFv1 ABI, this is always the case;
3985 // in the ELFv2 ABI, it is true if this is a vararg function or if
3986 // any parameter is located in a stack slot.
3987
3988 bool HasParameterArea = !isELFv2ABI || isVarArg;
3989 unsigned ParamAreaSize = Num_GPR_Regs * PtrByteSize;
3990 unsigned NumBytes = LinkageSize;
3991 unsigned AvailableFPRs = Num_FPR_Regs;
3992 unsigned AvailableVRs = Num_VR_Regs;
3993 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3994 if (Ins[i].Flags.isNest())
3995 continue;
3996
3997 if (CalculateStackSlotUsed(Ins[i].VT, Ins[i].ArgVT, Ins[i].Flags,
3998 PtrByteSize, LinkageSize, ParamAreaSize,
3999 NumBytes, AvailableFPRs, AvailableVRs))
4000 HasParameterArea = true;
4001 }
4002
4003 // Add DAG nodes to load the arguments or copy them out of registers. On
4004 // entry to a function on PPC, the arguments start after the linkage area,
4005 // although the first ones are often in registers.
4006
4007 unsigned ArgOffset = LinkageSize;
4008 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
4009 SmallVector<SDValue, 8> MemOps;
4010 Function::const_arg_iterator FuncArg = MF.getFunction().arg_begin();
4011 unsigned CurArgIdx = 0;
4012 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
4013 SDValue ArgVal;
4014 bool needsLoad = false;
4015 EVT ObjectVT = Ins[ArgNo].VT;
4016 EVT OrigVT = Ins[ArgNo].ArgVT;
4017 unsigned ObjSize = ObjectVT.getStoreSize();
4018 unsigned ArgSize = ObjSize;
4019 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
4020 if (Ins[ArgNo].isOrigArg()) {
4021 std::advance(FuncArg, Ins[ArgNo].getOrigArgIndex() - CurArgIdx);
4022 CurArgIdx = Ins[ArgNo].getOrigArgIndex();
4023 }
4024 // We re-align the argument offset for each argument, except when using the
4025 // fast calling convention, when we need to make sure we do that only when
4026 // we'll actually use a stack slot.
4027 unsigned CurArgOffset;
4028 Align Alignment;
4029 auto ComputeArgOffset = [&]() {
4030 /* Respect alignment of argument on the stack. */
4031 Alignment =
4032 CalculateStackSlotAlignment(ObjectVT, OrigVT, Flags, PtrByteSize);
4033 ArgOffset = alignTo(ArgOffset, Alignment);
4034 CurArgOffset = ArgOffset;
4035 };
4036
4037 if (CallConv != CallingConv::Fast) {
4038 ComputeArgOffset();
4039
4040 /* Compute GPR index associated with argument offset. */
4041 GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
4042 GPR_idx = std::min(GPR_idx, Num_GPR_Regs);
4043 }
4044
4045 // FIXME the codegen can be much improved in some cases.
4046 // We do not have to keep everything in memory.
4047 if (Flags.isByVal()) {
4048 assert(Ins[ArgNo].isOrigArg() && "Byval arguments cannot be implicit")((Ins[ArgNo].isOrigArg() && "Byval arguments cannot be implicit"
) ? static_cast<void> (0) : __assert_fail ("Ins[ArgNo].isOrigArg() && \"Byval arguments cannot be implicit\""
, "/build/llvm-toolchain-snapshot-12~++20201124111112+7b5254223ac/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 4048, __PRETTY_FUNCTION__))
;
4049
4050 if (CallConv == CallingConv::Fast)
4051 ComputeArgOffset();
4052
4053 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
4054 ObjSize = Flags.getByValSize();
4055 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
4056 // Empty aggregate parameters do not take up registers. Examples:
4057 // struct { } a;
4058 // union { } b;
4059 // int c[0];
4060 // etc. However, we have to provide a place-holder in InVals, so
4061 // pretend we have an 8-byte item at the current address for that
4062 // purpose.
4063 if (!ObjSize) {
4064 int FI = MFI.CreateFixedObject(PtrByteSize, ArgOffset, true);
4065 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
4066 InVals.push_back(FIN);
4067 continue;
4068 }
4069
4070 // Create a stack object covering all stack doublewords occupied
4071 // by the argument. If the argument is (fully or partially) on
4072 // the stack, or if the argument is fully in registers but the
4073 // caller has allocated the parameter save anyway, we can refer
4074 // directly to the caller's stack frame. Otherwise, create a
4075 // local copy in our own frame.
4076 int FI;
4077 if (HasParameterArea ||
4078 ArgSize + ArgOffset > LinkageSize + Num_GPR_Regs * PtrByteSize)
4079 FI = MFI.CreateFixedObject(ArgSize, ArgOffset, false, true);
4080 else
4081 FI = MFI.CreateStackObject(ArgSize, Alignment, false);
4082 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
4083
4084 // Handle aggregates smaller than 8 bytes.
4085 if (ObjSize < PtrByteSize) {
4086 // The value of the object is its address, which differs from the
4087 // address of the enclosing doubleword on big-endian systems.
4088 SDValue Arg = FIN;
4089 if (!isLittleEndian) {
4090 SDValue ArgOff = DAG.getConstant(PtrByteSize - ObjSize, dl, PtrVT);
4091 Arg = DAG.getNode(ISD::ADD, dl, ArgOff.getValueType(), Arg, ArgOff);
4092 }
4093 InVals.push_back(Arg);
4094
4095 if (GPR_idx != Num_GPR_Regs) {
4096 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
4097 FuncInfo->addLiveInAttr(VReg, Flags);
4098 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
4099 SDValue Store;
4100
4101 if (ObjSize==1 || ObjSize==2 || ObjSize==4) {
4102 EVT ObjType = (ObjSize == 1 ? MVT::i8 :
4103 (ObjSize == 2 ? MVT::i16 : MVT::i32));
4104 Store = DAG.getTruncStore(Val.getValue(1), dl, Val, Arg,
4105 MachinePointerInfo(&*FuncArg), ObjType);
4106 } else {
4107 // For sizes that don't fit a truncating store (3, 5, 6, 7),
4108 // store the whole register as-is to the parameter save area
4109 // slot.
4110 Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
4111 MachinePointerInfo(&*FuncArg));
4112 }
4113
4114 MemOps.push_back(Store);
4115 }
4116 // Whether we copied from a register or not, advance the offset
4117 // into the parameter save area by a full doubleword.
4118 ArgOffset += PtrByteSize;
4119 continue;
4120 }
4121
4122 // The value of the object is its address, which is the address of
4123 // its first stack doubleword.
4124 InVals.push_back(FIN);
4125
4126 // Store whatever pieces of the object are in registers to memory.
4127 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
4128 if (GPR_idx == Num_GPR_Regs)
4129 break;
4130
4131 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
4132 FuncInfo->addLiveInAttr(VReg, Flags);
4133 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
4134 SDValue Addr = FIN;
4135 if (j) {
4136 SDValue Off = DAG.getConstant(j, dl, PtrVT);
4137 Addr = DAG.getNode(ISD::ADD, dl, Off.getValueType(), Addr, Off);
4138 }
4139 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, Addr,
4140 MachinePointerInfo(&*FuncArg, j));
4141 MemOps.push_back(Store);
4142 ++GPR_idx;
4143 }
4144 ArgOffset += ArgSize;
4145 continue;
4146 }
4147
4148 switch (ObjectVT.getSimpleVT().SimpleTy) {
4149 default: llvm_unreachable("Unhandled argument type!")::llvm::llvm_unreachable_internal("Unhandled argument type!",
"/build/llvm-toolchain-snapshot-12~++20201124111112+7b5254223ac/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 4149)
;
4150 case MVT::i1:
4151 case MVT::i32:
4152 case MVT::i64:
4153 if (Flags.isNest()) {
4154 // The 'nest' parameter, if any, is passed in R11.
4155 unsigned VReg = MF.addLiveIn(PPC::X11, &PPC::G8RCRegClass);
4156 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
4157
4158 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
4159 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
4160
4161 break;
4162 }
4163
4164 // These can be scalar arguments or elements of an integer array type
4165 // passed directly. Clang may use those instead of "byval" aggregate
4166 // types to avoid forcing arguments to memory unnecessarily.
4167 if (GPR_idx != Num_GPR_Regs) {
4168 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
4169 FuncInfo->addLiveInAttr(VReg, Flags);
4170 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
4171
4172 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
4173 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
4174 // value to MVT::i64 and then truncate to the correct register size.
4175 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
4176 } else {
4177 if (CallConv == CallingConv::Fast)
4178 ComputeArgOffset();
4179
4180 needsLoad = true;
4181 ArgSize = PtrByteSize;
4182 }
4183 if (CallConv != CallingConv::Fast || needsLoad)
4184 ArgOffset += 8;
4185 break;
4186
4187 case MVT::f32:
4188 case MVT::f64:
4189 // These can be scalar arguments or elements of a float array type
4190 // passed directly. The latter are used to implement ELFv2 homogenous
4191 // float aggregates.
4192 if (FPR_idx != Num_FPR_Regs) {
4193 unsigned VReg;
4194
4195 if (ObjectVT == MVT::f32)
4196 VReg = MF.addLiveIn(FPR[FPR_idx],
4197 Subtarget.hasP8Vector()
4198 ? &PPC::VSSRCRegClass
4199 : &PPC::F4RCRegClass);
4200 else
4201 VReg = MF.addLiveIn(FPR[FPR_idx], Subtarget.hasVSX()
4202 ? &PPC::VSFRCRegClass
4203 : &PPC::F8RCRegClass);
4204
4205 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
4206 ++FPR_idx;
4207 } else if (GPR_idx != Num_GPR_Regs && CallConv != CallingConv::Fast) {
4208 // FIXME: We may want to re-enable this for CallingConv::Fast on the P8
4209 // once we support fp <-> gpr moves.
4210
4211 // This can only ever happen in the presence of f32 array types,
4212 // since otherwise we never run out of FPRs before running out
4213 // of GPRs.
4214 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
4215 FuncInfo->addLiveInAttr(VReg, Flags);
4216 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
4217
4218 if (ObjectVT == MVT::f32) {
4219 if ((ArgOffset % PtrByteSize) == (isLittleEndian ? 4 : 0))
4220 ArgVal = DAG.getNode(ISD::SRL, dl, MVT::i64, ArgVal,
4221 DAG.getConstant(32, dl, MVT::i32));
4222 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal);
4223 }
4224
4225 ArgVal = DAG.getNode(ISD::BITCAST, dl, ObjectVT, ArgVal);
4226 } else {
4227 if (CallConv == CallingConv::Fast)
4228 ComputeArgOffset();
4229
4230 needsLoad = true;
4231 }
4232
4233 // When passing an array of floats, the array occupies consecutive
4234 // space in the argument area; only round up to the next doubleword
4235 // at the end of the array. Otherwise, each float takes 8 bytes.
4236 if (CallConv != CallingConv::Fast || needsLoad) {
4237 ArgSize = Flags.isInConsecutiveRegs() ? ObjSize : PtrByteSize;
4238 ArgOffset += ArgSize;
4239 if (Flags.isInConsecutiveRegsLast())
4240 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
4241 }
4242 break;
4243 case MVT::v4f32:
4244 case MVT::v4i32:
4245 case MVT::v8i16:
4246 case MVT::v16i8:
4247 case MVT::v2f64:
4248 case MVT::v2i64:
4249 case MVT::v1i128:
4250 case MVT::f128:
4251 // These can be scalar arguments or elements of a vector array type
4252 // passed directly. The latter are used to implement ELFv2 homogenous
4253 // vector aggregates.
4254 if (VR_idx != Num_VR_Regs) {
4255 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
4256 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
4257 ++VR_idx;
4258 } else {
4259 if (CallConv == CallingConv::Fast)
4260 ComputeArgOffset();
4261 needsLoad = true;
4262 }
4263 if (CallConv != CallingConv::Fast || needsLoad)
4264 ArgOffset += 16;
4265 break;
4266 }
4267
4268 // We need to load the argument to a virtual register if we determined
4269 // above that we ran out of physical registers of the appropriate type.
4270 if (needsLoad) {
4271 if (ObjSize < ArgSize && !isLittleEndian)
4272 CurArgOffset += ArgSize - ObjSize;
4273 int FI = MFI.CreateFixedObject(ObjSize, CurArgOffset, isImmutable);
4274 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
4275 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo());
4276 }
4277
4278 InVals.push_back(ArgVal);
4279 }
4280
4281 // Area that is at least reserved in the caller of this function.
4282 unsigned MinReservedArea;
4283 if (HasParameterArea)
4284 MinReservedArea = std::max(ArgOffset, LinkageSize + 8 * PtrByteSize);
4285 else
4286 MinReservedArea = LinkageSize;
4287
4288 // Set the size that is at least reserved in caller of this function. Tail
4289 // call optimized functions' reserved stack space needs to be aligned so that
4290 // taking the difference between two stack areas will result in an aligned
4291 // stack.
4292 MinReservedArea =
4293 EnsureStackAlignment(Subtarget.getFrameLowering(), MinReservedArea);
4294 FuncInfo->setMinReservedArea(MinReservedArea);
4295
4296 // If the function takes variable number of arguments, make a frame index for
4297 // the start of the first vararg value... for expansion of llvm.va_start.
4298 // On ELFv2ABI spec, it writes:
4299 // C programs that are intended to be *portable* across different compilers
4300 // and architectures must use the header file <stdarg.h> to deal with variable
4301 // argument lists.
4302 if (isVarArg && MFI.hasVAStart()) {
4303 int Depth = ArgOffset;
4304
4305 FuncInfo->setVarArgsFrameIndex(
4306 MFI.CreateFixedObject(PtrByteSize, Depth, true));
4307 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
4308
4309 // If this function is vararg, store any remaining integer argument regs
4310 // to their spots on the stack so that they may be loaded by dereferencing
4311 // the result of va_next.
4312 for (GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
4313 GPR_idx < Num_GPR_Regs; ++GPR_idx) {
4314 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
4315 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
4316 SDValue Store =
4317 DAG.getStore(Val.getValue(1), dl, Val, FIN, MachinePointerInfo());
4318 MemOps.push_back(Store);
4319 // Increment the address by four for the next argument to store
4320 SDValue PtrOff = DAG.getConstant(PtrByteSize, dl, PtrVT);
4321 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
4322 }
4323 }
4324
4325 if (!MemOps.empty())
4326 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
4327
4328 return Chain;
4329}
4330
4331SDValue PPCTargetLowering::LowerFormalArguments_Darwin(
4332 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
4333 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
4334 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
4335 // TODO: add description of PPC stack frame format, or at least some docs.
4336 //
4337 MachineFunction &MF = DAG.getMachineFunction();
4338 MachineFrameInfo &MFI = MF.getFrameInfo();
4339 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
4340
4341 EVT PtrVT = getPointerTy(MF.getDataLayout());
4342 bool isPPC64 = PtrVT == MVT::i64;
4343 // Potential tail calls could cause overwriting of argument stack slots.
4344 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
4345 (CallConv == CallingConv::Fast));
4346 unsigned PtrByteSize = isPPC64 ? 8 : 4;
4347 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
4348 unsigned ArgOffset = LinkageSize;
4349 // Area that is at least reserved in caller of this function.
4350 unsigned MinReservedArea = ArgOffset;
4351
4352 static const MCPhysReg GPR_32[] = { // 32-bit registers.
4353 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
4354 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
4355 };
4356 static const MCPhysReg GPR_64[] = { // 64-bit registers.
4357 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4358 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4359 };
4360 static const MCPhysReg VR[] = {
4361 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4362 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4363 };
4364
4365 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
4366 const unsigned Num_FPR_Regs = useSoftFloat() ? 0 : 13;
4367 const unsigned Num_VR_Regs = array_lengthof( VR);
4368
4369 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
4370
4371 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
4372
4373 // In 32-bit non-varargs functions, the stack space for vectors is after the
4374 // stack space for non-vectors. We do not use this space unless we have
4375 // too many vectors to fit in registers, something that only occurs in
4376 // constructed examples:), but we have to walk the arglist to figure
4377 // that out...for the pathological case, compute VecArgOffset as the
4378 // start of the vector parameter area. Computing VecArgOffset is the
4379 // entire point of the following loop.
4380 unsigned VecArgOffset = ArgOffset;
4381 if (!isVarArg && !isPPC64) {
4382 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e;
4383 ++ArgNo) {
4384 EVT ObjectVT = Ins[ArgNo].VT;
4385 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
4386
4387 if (Flags.isByVal()) {
4388 // ObjSize is the true size, ArgSize rounded up to multiple of regs.
4389 unsigned ObjSize = Flags.getByValSize();
4390 unsigned ArgSize =
4391 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
4392 VecArgOffset += ArgSize;
4393 continue;
4394 }
4395
4396 switch(ObjectVT.getSimpleVT().SimpleTy) {
4397 default: llvm_unreachable("Unhandled argument type!")::llvm::llvm_unreachable_internal("Unhandled argument type!",
"/build/llvm-toolchain-snapshot-12~++20201124111112+7b5254223ac/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 4397)
;
4398 case MVT::i1:
4399 case MVT::i32:
4400 case MVT::f32:
4401 VecArgOffset += 4;
4402 break;
4403 case MVT::i64: // PPC64
4404 case MVT::f64:
4405 // FIXME: We are guaranteed to be !isPPC64 at this point.
4406 // Does MVT::i64 apply?
4407 VecArgOffset += 8;
4408 break;
4409 case MVT::v4f32:
4410 case MVT::v4i32:
4411 case MVT::v8i16:
4412 case MVT::v16i8:
4413 // Nothing to do, we're only looking at Nonvector args here.
4414 break;
4415 }
4416 }
4417 }
4418 // We've found where the vector parameter area in memory is. Skip the
4419 // first 12 parameters; these don't use that memory.
4420 VecArgOffset = ((VecArgOffset+15)/16)*16;
4421 VecArgOffset += 12*16;
4422
4423 // Add DAG nodes to load the arguments or copy them out of registers. On
4424 // entry to a function on PPC, the arguments start after the linkage area,
4425 // although the first ones are often in registers.
4426
4427 SmallVector<SDValue, 8> MemOps;
4428 unsigned nAltivecParamsAtEnd = 0;
4429 Function::const_arg_iterator FuncArg = MF.getFunction().arg_begin();
4430 unsigned CurArgIdx = 0;
4431 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
4432 SDValue ArgVal;
4433 bool needsLoad = false;
4434 EVT ObjectVT = Ins[ArgNo].VT;
4435 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
4436 unsigned ArgSize = ObjSize;
4437 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
4438 if (Ins[ArgNo].isOrigArg()) {
4439 std::advance(FuncArg, Ins[ArgNo].getOrigArgIndex() - CurArgIdx);
4440 CurArgIdx = Ins[ArgNo].getOrigArgIndex();
4441 }
4442 unsigned CurArgOffset = ArgOffset;
4443
4444 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
4445 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
4446 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
4447 if (isVarArg || isPPC64) {
4448 MinReservedArea = ((MinReservedArea+15)/16)*16;
4449 MinReservedArea += CalculateStackSlotSize(ObjectVT,
4450 Flags,
4451 PtrByteSize);
4452 } else nAltivecParamsAtEnd++;
4453 } else
4454 // Calculate min reserved area.
4455 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
4456 Flags,
4457 PtrByteSize);
4458
4459 // FIXME the codegen can be much improved in some cases.
4460 // We do not have to keep everything in memory.
4461 if (Flags.isByVal()) {
4462 assert(Ins[ArgNo].isOrigArg() && "Byval arguments cannot be implicit")((Ins[ArgNo].isOrigArg() && "Byval arguments cannot be implicit"
) ? static_cast<void> (0) : __assert_fail ("Ins[ArgNo].isOrigArg() && \"Byval arguments cannot be implicit\""
, "/build/llvm-toolchain-snapshot-12~++20201124111112+7b5254223ac/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 4462, __PRETTY_FUNCTION__))
;
4463
4464 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
4465 ObjSize = Flags.getByValSize();
4466 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
4467 // Objects of size 1 and 2 are right justified, everything else is
4468 // left justified. This means the memory address is adjusted forwards.
4469 if (ObjSize==1 || ObjSize==2) {
4470 CurArgOffset = CurArgOffset + (4 - ObjSize);
4471 }
4472 // The value of the object is its address.
4473 int FI = MFI.CreateFixedObject(ObjSize, CurArgOffset, false, true);
4474 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
4475 InVals.push_back(FIN);
4476 if (ObjSize==1 || ObjSize==2) {
4477 if (GPR_idx != Num_GPR_Regs) {
4478 unsigned VReg;
4479 if (isPPC64)
4480 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
4481 else
4482 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
4483 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
4484 EVT ObjType = ObjSize == 1 ? MVT::i8 : MVT::i16;
4485 SDValue Store =
4486 DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
4487 MachinePointerInfo(&*FuncArg), ObjType);
4488 MemOps.push_back(Store);
4489 ++GPR_idx;
4490 }
4491
4492 ArgOffset += PtrByteSize;
4493
4494 continue;
4495 }
4496 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
4497 // Store whatever pieces of the object are in registers
4498 // to memory. ArgOffset will be the address of the beginning
4499 // of the object.
4500 if (GPR_idx != Num_GPR_Regs) {
4501 unsigned VReg;
4502 if (isPPC64)
4503 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
4504 else
4505 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
4506 int FI = MFI.CreateFixedObject(PtrByteSize, ArgOffset, true);
4507 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
4508 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
4509 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
4510 MachinePointerInfo(&*FuncArg, j));
4511 MemOps.push_back(Store);
4512 ++GPR_idx;
4513 ArgOffset += PtrByteSize;
4514 } else {
4515 ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
4516 break;
4517 }
4518 }
4519 continue;
4520 }
4521
4522 switch (ObjectVT.getSimpleVT().SimpleTy) {
4523 default: llvm_unreachable("Unhandled argument type!")::llvm::llvm_unreachable_internal("Unhandled argument type!",
"/build/llvm-toolchain-snapshot-12~++20201124111112+7b5254223ac/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 4523)
;
4524 case MVT::i1:
4525 case MVT::i32:
4526 if (!isPPC64) {
4527 if (GPR_idx != Num_GPR_Regs) {
4528 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
4529 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
4530
4531 if (ObjectVT == MVT::i1)
4532 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgVal);
4533
4534 ++GPR_idx;
4535 } else {
4536 needsLoad = true;
4537 ArgSize = PtrByteSize;
4538 }
4539 // All int arguments reserve stack space in the Darwin ABI.
4540 ArgOffset += PtrByteSize;
4541 break;
4542 }
4543 LLVM_FALLTHROUGH[[gnu::fallthrough]];
4544 case MVT::i64: // PPC64
4545 if (GPR_idx != Num_GPR_Regs) {
4546 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
4547 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
4548
4549 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
4550 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
4551 // value to MVT::i64 and then truncate to the correct register size.
4552 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
4553
4554 ++GPR_idx;
4555 } else {
4556 needsLoad = true;
4557 ArgSize = PtrByteSize;
4558 }
4559 // All int arguments reserve stack space in the Darwin ABI.
4560 ArgOffset += 8;
4561 break;
4562
4563 case MVT::f32:
4564 case MVT::f64:
4565 // Every 4 bytes of argument space consumes one of the GPRs available for
4566 // argument passing.
4567 if (GPR_idx != Num_GPR_Regs) {
4568 ++GPR_idx;
4569 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
4570 ++GPR_idx;
4571 }
4572 if (FPR_idx != Num_FPR_Regs) {
4573 unsigned VReg;
4574
4575 if (ObjectVT == MVT::f32)
4576 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
4577 else
4578 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
4579
4580 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
4581 ++FPR_idx;
4582 } else {
4583 needsLoad = true;
4584 }
4585
4586 // All FP arguments reserve stack space in the Darwin ABI.
4587 ArgOffset += isPPC64 ? 8 : ObjSize;
4588 break;
4589 case MVT::v4f32:
4590 case MVT::v4i32:
4591 case MVT::v8i16:
4592 case MVT::v16i8:
4593 // Note that vector arguments in registers don't reserve stack space,
4594 // except in varargs functions.
4595 if (VR_idx != Num_VR_Regs) {
4596 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
4597 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
4598 if (isVarArg) {
4599 while ((ArgOffset % 16) != 0) {
4600 ArgOffset += PtrByteSize;
4601 if (GPR_idx != Num_GPR_Regs)
4602 GPR_idx++;
4603 }
4604 ArgOffset += 16;
4605 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
4606 }
4607 ++VR_idx;
4608 } else {
4609 if (!isVarArg && !isPPC64) {
4610 // Vectors go after all the nonvectors.
4611 CurArgOffset = VecArgOffset;
4612 VecArgOffset += 16;
4613 } else {
4614 // Vectors are aligned.
4615 ArgOffset = ((ArgOffset+15)/16)*16;
4616 CurArgOffset = ArgOffset;
4617 ArgOffset += 16;
4618 }
4619 needsLoad = true;
4620 }
4621 break;
4622 }
4623
4624 // We need to load the argument to a virtual register if we determined above
4625 // that we ran out of physical registers of the appropriate type.
4626 if (needsLoad) {
4627 int FI = MFI.CreateFixedObject(ObjSize,
4628 CurArgOffset + (ArgSize - ObjSize),
4629 isImmutable);
4630 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
4631 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo());
4632 }
4633
4634 InVals.push_back(ArgVal);
4635 }
4636
4637 // Allow for Altivec parameters at the end, if needed.
4638 if (nAltivecParamsAtEnd) {
4639 MinReservedArea = ((MinReservedArea+15)/16)*16;
4640 MinReservedArea += 16*nAltivecParamsAtEnd;
4641 }
4642
4643 // Area that is at least reserved in the caller of this function.
4644 MinReservedArea = std::max(MinReservedArea, LinkageSize + 8 * PtrByteSize);
4645
4646 // Set the size that is at least reserved in caller of this function. Tail
4647 // call optimized functions' reserved stack space needs to be aligned so that
4648 // taking the difference between two stack areas will result in an aligned
4649 // stack.
4650 MinReservedArea =
4651 EnsureStackAlignment(Subtarget.getFrameLowering(), MinReservedArea);
4652 FuncInfo->setMinReservedArea(MinReservedArea);
4653
4654 // If the function takes variable number of arguments, make a frame index for
4655 // the start of the first vararg value... for expansion of llvm.va_start.
4656 if (isVarArg) {
4657 int Depth = ArgOffset;
4658
4659 FuncInfo->setVarArgsFrameIndex(
4660 MFI.CreateFixedObject(PtrVT.getSizeInBits()/8,
4661 Depth, true));
4662 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
4663
4664 // If this function is vararg, store any remaining integer argument regs
4665 // to their spots on the stack so that they may be loaded by dereferencing
4666 // the result of va_next.
4667 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
4668 unsigned VReg;
4669
4670 if (isPPC64)
4671 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
4672 else
4673 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
4674
4675 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
4676 SDValue Store =
4677 DAG.getStore(Val.getValue(1), dl, Val, FIN, MachinePointerInfo());
4678 MemOps.push_back(Store);
4679 // Increment the address by four for the next argument to store
4680 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, dl, PtrVT);
4681 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
4682 }
4683 }
4684
4685 if (!MemOps.empty())
4686 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
4687
4688 return Chain;
4689}
4690
4691/// CalculateTailCallSPDiff - Get the amount the stack pointer has to be
4692/// adjusted to accommodate the arguments for the tailcall.
4693static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall,
4694 unsigned ParamSize) {
4695
4696 if (!isTailCall) return 0;
4697
4698 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>();
4699 unsigned CallerMinReservedArea = FI->getMinReservedArea();
4700 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
4701 // Remember only if the new adjustment is bigger.
4702 if (SPDiff < FI->getTailCallSPDelta())
4703 FI->setTailCallSPDelta(SPDiff);
4704
4705 return SPDiff;
4706}
4707
4708static bool isFunctionGlobalAddress(SDValue Callee);
4709
4710static bool callsShareTOCBase(const Function *Caller, SDValue Callee,
4711 const TargetMachine &TM) {
4712 // It does not make sense to call callsShareTOCBase() with a caller that
4713 // is PC Relative since PC Relative callers do not have a TOC.
4714#ifndef NDEBUG
4715 const PPCSubtarget *STICaller = &TM.getSubtarget<PPCSubtarget>(*Caller);
4716 assert(!STICaller->isUsingPCRelativeCalls() &&((!STICaller->isUsingPCRelativeCalls() && "PC Relative callers do not have a TOC and cannot share a TOC Base"
) ? static_cast<void> (0) : __assert_fail ("!STICaller->isUsingPCRelativeCalls() && \"PC Relative callers do not have a TOC and cannot share a TOC Base\""
, "/build/llvm-toolchain-snapshot-12~++20201124111112+7b5254223ac/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 4717, __PRETTY_FUNCTION__))
4717 "PC Relative callers do not have a TOC and cannot share a TOC Base")((!STICaller->isUsingPCRelativeCalls() && "PC Relative callers do not have a TOC and cannot share a TOC Base"
) ? static_cast<void> (0) : __assert_fail ("!STICaller->isUsingPCRelativeCalls() && \"PC Relative callers do not have a TOC and cannot share a TOC Base\""
, "/build/llvm-toolchain-snapshot-12~++20201124111112+7b5254223ac/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 4717, __PRETTY_FUNCTION__))
;
4718#endif
4719
4720 // Callee is either a GlobalAddress or an ExternalSymbol. ExternalSymbols
4721 // don't have enough information to determine if the caller and callee share
4722 // the same TOC base, so we have to pessimistically assume they don't for
4723 // correctness.
4724 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
4725 if (!G)
4726 return false;
4727
4728 const GlobalValue *GV = G->getGlobal();
4729
4730 // If the callee is preemptable, then the static linker will use a plt-stub
4731 // which saves the toc to the stack, and needs a nop after the call
4732 // instruction to convert to a toc-restore.
4733 if (!TM.shouldAssumeDSOLocal(*Caller->getParent(), GV))
4734 return false;
4735
4736 // Functions with PC Relative enabled may clobber the TOC in the same DSO.
4737 // We may need a TOC restore in the situation where the caller requires a
4738 // valid TOC but the callee is PC Relative and does not.
4739 const Function *F = dyn_cast<Function>(GV);
4740 const GlobalAlias *Alias = dyn_cast<GlobalAlias>(GV);
4741
4742 // If we have an Alias we can try to get the function from there.
4743 if (Alias) {
4744 const GlobalObject *GlobalObj = Alias->getBaseObject();
4745 F = dyn_cast<Function>(GlobalObj);
4746 }
4747
4748 // If we still have no valid function pointer we do not have enough
4749 // information to determine if the callee uses PC Relative calls so we must
4750 // assume that it does.
4751 if (!F)
4752 return false;
4753
4754 // If the callee uses PC Relative we cannot guarantee that the callee won't
4755 // clobber the TOC of the caller and so we must assume that the two
4756 // functions do not share a TOC base.
4757 const PPCSubtarget *STICallee = &TM.getSubtarget<PPCSubtarget>(*F);
4758 if (STICallee->isUsingPCRelativeCalls())
4759 return false;
4760
4761 // The medium and large code models are expected to provide a sufficiently
4762 // large TOC to provide all data addressing needs of a module with a
4763 // single TOC.
4764 if (CodeModel::Medium == TM.getCodeModel() ||
4765 CodeModel::Large == TM.getCodeModel())
4766 return true;
4767
4768 // Otherwise we need to ensure callee and caller are in the same section,
4769 // since the linker may allocate multiple TOCs, and we don't know which
4770 // sections will belong to the same TOC base.
4771 if (!GV->isStrongDefinitionForLinker())
4772 return false;
4773
4774 // Any explicitly-specified sections and section prefixes must also match.
4775 // Also, if we're using -ffunction-sections, then each function is always in
4776 // a different section (the same is true for COMDAT functions).
4777 if (TM.getFunctionSections() || GV->hasComdat() || Caller->hasComdat() ||
4778 GV->getSection() != Caller->getSection())
4779 return false;
4780 if (const auto *F = dyn_cast<Function>(GV)) {
4781 if (F->getSectionPrefix() != Caller->getSectionPrefix())
4782 return false;
4783 }
4784
4785 return true;
4786}
4787
4788static bool
4789needStackSlotPassParameters(const PPCSubtarget &Subtarget,
4790 const SmallVectorImpl<ISD::OutputArg> &Outs) {
4791 assert(Subtarget.is64BitELFABI())((Subtarget.is64BitELFABI()) ? static_cast<void> (0) : __assert_fail
("Subtarget.is64BitELFABI()", "/build/llvm-toolchain-snapshot-12~++20201124111112+7b5254223ac/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 4791, __PRETTY_FUNCTION__))
;
4792
4793 const unsigned PtrByteSize = 8;
4794 const unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
4795
4796 static const MCPhysReg GPR[] = {
4797 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4798 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4799 };
4800 static const MCPhysReg VR[] = {
4801 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4802 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4803 };
4804
4805 const unsigned NumGPRs = array_lengthof(GPR);
4806 const unsigned NumFPRs = 13;
4807 const unsigned NumVRs = array_lengthof(VR);
4808 const unsigned ParamAreaSize = NumGPRs * PtrByteSize;
4809
4810 unsigned NumBytes = LinkageSize;
4811 unsigned AvailableFPRs = NumFPRs;
4812 unsigned AvailableVRs = NumVRs;
4813
4814 for (const ISD::OutputArg& Param : Outs) {
4815 if (Param.Flags.isNest()) continue;
4816
4817 if (CalculateStackSlotUsed(Param.VT, Param.ArgVT, Param.Flags, PtrByteSize,
4818 LinkageSize, ParamAreaSize, NumBytes,
4819 AvailableFPRs, AvailableVRs))
4820 return true;
4821 }
4822 return false;
4823}
4824
4825static bool hasSameArgumentList(const Function *CallerFn, const CallBase &CB) {
4826 if (CB.arg_size() != CallerFn->arg_size())
4827 return false;
4828
4829 auto CalleeArgIter = CB.arg_begin();
4830 auto CalleeArgEnd = CB.arg_end();
4831 Function::const_arg_iterator CallerArgIter = CallerFn->arg_begin();
4832
4833 for (; CalleeArgIter != CalleeArgEnd; ++CalleeArgIter, ++CallerArgIter) {
4834 const Value* CalleeArg = *CalleeArgIter;
4835 const Value* CallerArg = &(*CallerArgIter);
4836 if (CalleeArg == CallerArg)
4837 continue;
4838
4839 // e.g. @caller([4 x i64] %a, [4 x i64] %b) {
4840 // tail call @callee([4 x i64] undef, [4 x i64] %b)
4841 // }
4842 // 1st argument of callee is undef and has the same type as caller.
4843 if (CalleeArg->getType() == CallerArg->getType() &&
4844 isa<UndefValue>(CalleeArg))
4845 continue;
4846
4847 return false;
4848 }
4849
4850 return true;
4851}
4852
4853// Returns true if TCO is possible between the callers and callees
4854// calling conventions.
4855static bool
4856areCallingConvEligibleForTCO_64SVR4(CallingConv::ID CallerCC,
4857 CallingConv::ID CalleeCC) {
4858 // Tail calls are possible with fastcc and ccc.
4859 auto isTailCallableCC = [] (CallingConv::ID CC){
4860 return CC == CallingConv::C || CC == CallingConv::Fast;
4861 };
4862 if (!isTailCallableCC(CallerCC) || !isTailCallableCC(CalleeCC))
4863 return false;
4864
4865 // We can safely tail call both fastcc and ccc callees from a c calling
4866 // convention caller. If the caller is fastcc, we may have less stack space
4867 // than a non-fastcc caller with the same signature so disable tail-calls in
4868 // that case.
4869 return CallerCC == CallingConv::C || CallerCC == CalleeCC;
4870}
4871
4872bool PPCTargetLowering::IsEligibleForTailCallOptimization_64SVR4(
4873 SDValue Callee, CallingConv::ID CalleeCC, const CallBase *CB, bool isVarArg,
4874 const SmallVectorImpl<ISD::OutputArg> &Outs,
4875 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const {
4876 bool TailCallOpt = getTargetMachine().Options.GuaranteedTailCallOpt;
4877
4878 if (DisableSCO && !TailCallOpt) return false;
4879
4880 // Variadic argument functions are not supported.
4881 if (isVarArg) return false;
4882
4883 auto &Caller = DAG.getMachineFunction().getFunction();
4884 // Check that the calling conventions are compatible for tco.
4885 if (!areCallingConvEligibleForTCO_64SVR4(Caller.getCallingConv(), CalleeCC))
4886 return false;
4887
4888 // Caller contains any byval parameter is not supported.
4889 if (any_of(Ins, [](const ISD::InputArg &IA) { return IA.Flags.isByVal(); }))
4890 return false;
4891
4892 // Callee contains any byval parameter is not supported, too.
4893 // Note: This is a quick work around, because in some cases, e.g.
4894 // caller's stack size > callee's stack size, we are still able to apply
4895 // sibling call optimization. For example, gcc is able to do SCO for caller1
4896 // in the following example, but not for caller2.
4897 // struct test {
4898 // long int a;
4899 // char ary[56];
4900 // } gTest;
4901 // __attribute__((noinline)) int callee(struct test v, struct test *b) {
4902 // b->a = v.a;
4903 // return 0;
4904 // }
4905 // void caller1(struct test a, struct test c, struct test *b) {
4906 // callee(gTest, b); }
4907 // void caller2(struct test *b) { callee(gTest, b); }
4908 if (any_of(Outs, [](const ISD::OutputArg& OA) { return OA.Flags.isByVal(); }))
4909 return false;
4910
4911 // If callee and caller use different calling conventions, we cannot pass
4912 // parameters on stack since offsets for the parameter area may be different.
4913 if (Caller.getCallingConv() != CalleeCC &&
4914 needStackSlotPassParameters(Subtarget, Outs))
4915 return false;
4916
4917 // All variants of 64-bit ELF ABIs without PC-Relative addressing require that
4918 // the caller and callee share the same TOC for TCO/SCO. If the caller and
4919 // callee potentially have different TOC bases then we cannot tail call since
4920 // we need to restore the TOC pointer after the call.
4921 // ref: https://bugzilla.mozilla.org/show_bug.cgi?id=973977
4922 // We cannot guarantee this for indirect calls or calls to external functions.
4923 // When PC-Relative addressing is used, the concept of the TOC is no longer
4924 // applicable so this check is not required.
4925 // Check first for indirect calls.
4926 if (!Subtarget.isUsingPCRelativeCalls() &&
4927 !isFunctionGlobalAddress(Callee) && !isa<ExternalSymbolSDNode>(Callee))
4928 return false;
4929
4930 // Check if we share the TOC base.
4931 if (!Subtarget.isUsingPCRelativeCalls() &&
4932 !callsShareTOCBase(&Caller, Callee, getTargetMachine()))
4933 return false;
4934
4935 // TCO allows altering callee ABI, so we don't have to check further.
4936 if (CalleeCC == CallingConv::Fast && TailCallOpt)
4937 return true;
4938
4939 if (DisableSCO) return false;
4940
4941 // If callee use the same argument list that caller is using, then we can
4942 // apply SCO on this case. If it is not, then we need to check if callee needs
4943 // stack for passing arguments.
4944 // PC Relative tail calls may not have a CallBase.
4945 // If there is no CallBase we cannot verify if we have the same argument
4946 // list so assume that we don't have the same argument list.
4947 if (CB && !hasSameArgumentList(&Caller, *CB) &&
4948 needStackSlotPassParameters(Subtarget, Outs))
4949 return false;
4950 else if (!CB && needStackSlotPassParameters(Subtarget, Outs))
4951 return false;
4952
4953 return true;
4954}
4955
4956/// IsEligibleForTailCallOptimization - Check whether the call is eligible
4957/// for tail call optimization. Targets which want to do tail call
4958/// optimization should implement this function.
4959bool
4960PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
4961 CallingConv::ID CalleeCC,
4962 bool isVarArg,
4963 const SmallVectorImpl<ISD::InputArg> &Ins,
4964 SelectionDAG& DAG) const {
4965 if (!getTargetMachine().Options.GuaranteedTailCallOpt)
4966 return false;
4967
4968 // Variable argument functions are not supported.
4969 if (isVarArg)
4970 return false;
4971
4972 MachineFunction &MF = DAG.getMachineFunction();
4973 CallingConv::ID CallerCC = MF.getFunction().getCallingConv();
4974 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
4975 // Functions containing by val parameters are not supported.
4976 for (unsigned i = 0; i != Ins.size(); i++) {
4977 ISD::ArgFlagsTy Flags = Ins[i].Flags;
4978 if (Flags.isByVal()) return false;
4979 }
4980
4981 // Non-PIC/GOT tail calls are supported.
4982 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
4983 return true;
4984
4985 // At the moment we can only do local tail calls (in same module, hidden
4986 // or protected) if we are generating PIC.
4987 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
4988 return G->getGlobal()->hasHiddenVisibility()
4989 || G->getGlobal()->hasProtectedVisibility();
4990 }
4991
4992 return false;
4993}
4994
4995/// isCallCompatibleAddress - Return the immediate to use if the specified
4996/// 32-bit value is representable in the immediate field of a BxA instruction.
4997static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
4998 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
4999 if (!C) return nullptr;
5000
5001 int Addr = C->getZExtValue();
5002 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
5003 SignExtend32<26>(Addr) != Addr)
5004 return nullptr; // Top 6 bits have to be sext of immediate.
5005
5006 return DAG
5007 .getConstant(
5008 (int)C->getZExtValue() >> 2, SDLoc(Op),
5009 DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout()))
5010 .getNode();
5011}
5012
5013namespace {
5014
5015struct TailCallArgumentInfo {
5016 SDValue Arg;
5017 SDValue FrameIdxOp;
5018 int FrameIdx = 0;
5019
5020 TailCallArgumentInfo() = default;
5021};
5022
5023} // end anonymous namespace
5024
5025/// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
5026static void StoreTailCallArgumentsToStackSlot(
5027 SelectionDAG &DAG, SDValue Chain,
5028 const SmallVectorImpl<TailCallArgumentInfo> &TailCallArgs,
5029 SmallVectorImpl<SDValue> &MemOpChains, const SDLoc &dl) {
5030 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {
5031 SDValue Arg = TailCallArgs[i].Arg;
5032 SDValue FIN = TailCallArgs[i].FrameIdxOp;
5033 int FI = TailCallArgs[i].FrameIdx;
5034 // Store relative to framepointer.
5035 MemOpChains.push_back(DAG.getStore(
5036 Chain, dl, Arg, FIN,
5037 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI)));
5038 }
5039}
5040
5041/// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to
5042/// the appropriate stack slot for the tail call optimized function call.
5043static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG, SDValue Chain,
5044 SDValue OldRetAddr, SDValue OldFP,
5045 int SPDiff, const SDLoc &dl) {
5046 if (SPDiff) {
5047 // Calculate the new stack slot for the return address.
5048 MachineFunction &MF = DAG.getMachineFunction();
5049 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
5050 const PPCFrameLowering *FL = Subtarget.getFrameLowering();
5051 bool isPPC64 = Subtarget.isPPC64();
5052 int SlotSize = isPPC64 ? 8 : 4;
5053 int NewRetAddrLoc = SPDiff + FL->getReturnSaveOffset();
5054 int NewRetAddr = MF.getFrameInfo().CreateFixedObject(SlotSize,
5055 NewRetAddrLoc, true);
5056 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
5057 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
5058 Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx,
5059 MachinePointerInfo::getFixedStack(MF, NewRetAddr));
5060 }
5061 return Chain;
5062}
5063
5064/// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
5065/// the position of the argument.
5066static void
5067CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
5068 SDValue Arg, int SPDiff, unsigned ArgOffset,
5069 SmallVectorImpl<TailCallArgumentInfo>& TailCallArguments) {
5070 int Offset = ArgOffset + SPDiff;
5071 uint32_t OpSize = (Arg.getValueSizeInBits() + 7) / 8;
5072 int FI = MF.getFrameInfo().CreateFixedObject(OpSize, Offset, true);
5073 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
5074 SDValue FIN = DAG.getFrameIndex(FI, VT);
5075 TailCallArgumentInfo Info;
5076 Info.Arg = Arg;
5077 Info.FrameIdxOp = FIN;
5078 Info.FrameIdx = FI;
5079 TailCallArguments.push_back(Info);
5080}
5081
5082/// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address
5083/// stack slot. Returns the chain as result and the loaded frame pointers in
5084/// LROpOut/FPOpout. Used when tail calling.
5085SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(
5086 SelectionDAG &DAG, int SPDiff, SDValue Chain, SDValue &LROpOut,
5087 SDValue &FPOpOut, const SDLoc &dl) const {
5088 if (SPDiff) {
5089 // Load the LR and FP stack slot for later adjusting.
5090 EVT VT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32;
5091 LROpOut = getReturnAddrFrameIndex(DAG);
5092 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo());
5093 Chain = SDValue(LROpOut.getNode(), 1);
5094 }
5095 return Chain;
5096}
5097
5098/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
5099/// by "Src" to address "Dst" of size "Size". Alignment information is
5100/// specified by the specific parameter attribute. The copy will be passed as
5101/// a byval function parameter.
5102/// Sometimes what we are copying is the end of a larger object, the part that
5103/// does not fit in registers.
5104static SDValue CreateCopyOfByValArgument(SDValue Src, SDValue Dst,
5105 SDValue Chain, ISD::ArgFlagsTy Flags,
5106 SelectionDAG &DAG, const SDLoc &dl) {
5107 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
5108 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode,
5109 Flags.getNonZeroByValAlign(), false, false, false,
5110 MachinePointerInfo(), MachinePointerInfo());
5111}
5112
5113/// LowerMemOpCallTo - Store the argument to the stack or remember it in case of
5114/// tail calls.
5115static void LowerMemOpCallTo(
5116 SelectionDAG &DAG, MachineFunction &MF, SDValue Chain, SDValue Arg,
5117 SDValue PtrOff, int SPDiff, unsigned ArgOffset, bool isPPC64,
5118 bool isTailCall, bool isVector, SmallVectorImpl<SDValue> &MemOpChains,
5119 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments, const SDLoc &dl) {
5120 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
5121 if (!isTailCall) {
5122 if (isVector) {
5123 SDValue StackPtr;
5124 if (isPPC64)
5125 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
5126 else
5127 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
5128 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
5129 DAG.getConstant(ArgOffset, dl, PtrVT));
5130 }
5131 MemOpChains.push_back(
5132 DAG.getStore(Chain, dl, Arg, PtrOff, MachinePointerInfo()));
5133 // Calculate and remember argument location.
5134 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
5135 TailCallArguments);
5136}
5137
5138static void
5139PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain,
5140 const SDLoc &dl, int SPDiff, unsigned NumBytes, SDValue LROp,
5141 SDValue FPOp,
5142 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments) {
5143 // Emit a sequence of copyto/copyfrom virtual registers for arguments that
5144 // might overwrite each other in case of tail call optimization.
5145 SmallVector<SDValue, 8> MemOpChains2;
5146 // Do not flag preceding copytoreg stuff together with the following stuff.
5147 InFlag = SDValue();
5148 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
5149 MemOpChains2, dl);
5150 if (!MemOpChains2.empty())
5151 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
5152
5153 // Store the return address to the appropriate stack slot.
5154 Chain = EmitTailCallStoreFPAndRetAddr(DAG, Chain, LROp, FPOp, SPDiff, dl);
5155
5156 // Emit callseq_end just before tailcall node.
5157 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
5158 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
5159 InFlag = Chain.getValue(1);
5160}
5161
5162// Is this global address that of a function that can be called by name? (as
5163// opposed to something that must hold a descriptor for an indirect call).
5164static bool isFunctionGlobalAddress(SDValue Callee) {
5165 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
5166 if (Callee.getOpcode() == ISD::GlobalTLSAddress ||
5167 Callee.getOpcode() == ISD::TargetGlobalTLSAddress)
5168 return false;
5169
5170 return G->getGlobal()->getValueType()->isFunctionTy();
5171 }
5172
5173 return false;
5174}
5175
5176SDValue PPCTargetLowering::LowerCallResult(
5177 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
5178 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
5179 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
5180 SmallVector<CCValAssign, 16> RVLocs;
5181 CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
5182 *DAG.getContext());
5183
5184 CCRetInfo.AnalyzeCallResult(
5185 Ins, (Subtarget.isSVR4ABI() && CallConv == CallingConv::Cold)
5186 ? RetCC_PPC_Cold
5187 : RetCC_PPC);
5188
5189 // Copy all of the result registers out of their specified physreg.
5190 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
5191 CCValAssign &VA = RVLocs[i];
5192 assert(VA.isRegLoc() && "Can only return in registers!")((VA.isRegLoc() && "Can only return in registers!") ?
static_cast<void> (0) : __assert_fail ("VA.isRegLoc() && \"Can only return in registers!\""
, "/build/llvm-toolchain-snapshot-12~++20201124111112+7b5254223ac/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5192, __PRETTY_FUNCTION__))
;
5193
5194 SDValue Val;
5195
5196 if (Subtarget.hasSPE() && VA.getLocVT() == MVT::f64) {
5197 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
5198 InFlag);
5199 Chain = Lo.getValue(1);
5200 InFlag = Lo.getValue(2);
5201 VA = RVLocs[++i]; // skip ahead to next loc
5202 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
5203 InFlag);
5204 Chain = Hi.getValue(1);
5205 InFlag = Hi.getValue(2);
5206 if (!Subtarget.isLittleEndian())
5207 std::swap (Lo, Hi);
5208 Val = DAG.getNode(PPCISD::BUILD_SPE64, dl, MVT::f64, Lo, Hi);
5209 } else {
5210 Val = DAG.getCopyFromReg(Chain, dl,
5211 VA.getLocReg(), VA.getLocVT(), InFlag);
5212 Chain = Val.getValue(1);
5213 InFlag = Val.getValue(2);
5214 }
5215
5216 switch (VA.getLocInfo()) {
5217 default: llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-12~++20201124111112+7b5254223ac/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5217)
;
5218 case CCValAssign::Full: break;
5219 case CCValAssign::AExt:
5220 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
5221 break;
5222 case CCValAssign::ZExt:
5223 Val = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), Val,
5224 DAG.getValueType(VA.getValVT()));
5225 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
5226 break;
5227 case CCValAssign::SExt:
5228 Val = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), Val,
5229 DAG.getValueType(VA.getValVT()));
5230 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
5231 break;
5232 }
5233
5234 InVals.push_back(Val);
5235 }
5236
5237 return Chain;
5238}
5239
5240static bool isIndirectCall(const SDValue &Callee, SelectionDAG &DAG,
5241 const PPCSubtarget &Subtarget, bool isPatchPoint) {
5242 // PatchPoint calls are not indirect.
5243 if (isPatchPoint)
5244 return false;
5245
5246 if (isFunctionGlobalAddress(Callee) || dyn_cast<ExternalSymbolSDNode>(Callee))
5247 return false;
5248
5249 // Darwin, and 32-bit ELF can use a BLA. The descriptor based ABIs can not
5250 // becuase the immediate function pointer points to a descriptor instead of
5251 // a function entry point. The ELFv2 ABI cannot use a BLA because the function
5252 // pointer immediate points to the global entry point, while the BLA would
5253 // need to jump to the local entry point (see rL211174).
5254 if (!Subtarget.usesFunctionDescriptors() && !Subtarget.isELFv2ABI() &&
5255 isBLACompatibleAddress(Callee, DAG))
5256 return false;
5257
5258 return true;
5259}
5260
5261// AIX and 64-bit ELF ABIs w/o PCRel require a TOC save/restore around calls.
5262static inline bool isTOCSaveRestoreRequired(const PPCSubtarget &Subtarget) {
5263 return Subtarget.isAIXABI() ||
5264 (Subtarget.is64BitELFABI() && !Subtarget.isUsingPCRelativeCalls());
5265}
5266
5267static unsigned getCallOpcode(PPCTargetLowering::CallFlags CFlags,
5268 const Function &Caller,
5269 const SDValue &Callee,
5270 const PPCSubtarget &Subtarget,
5271 const TargetMachine &TM) {
5272 if (CFlags.IsTailCall)
5273 return PPCISD::TC_RETURN;
5274
5275 // This is a call through a function pointer.
5276 if (CFlags.IsIndirect) {
5277 // AIX and the 64-bit ELF ABIs need to maintain the TOC pointer accross
5278 // indirect calls. The save of the caller's TOC pointer to the stack will be
5279 // inserted into the DAG as part of call lowering. The restore of the TOC
5280 // pointer is modeled by using a pseudo instruction for the call opcode that
5281 // represents the 2 instruction sequence of an indirect branch and link,
5282 // immediately followed by a load of the TOC pointer from the the stack save
5283 // slot into gpr2. For 64-bit ELFv2 ABI with PCRel, do not restore the TOC
5284 // as it is not saved or used.
5285 return isTOCSaveRestoreRequired(Subtarget) ? PPCISD::BCTRL_LOAD_TOC
5286 : PPCISD::BCTRL;
5287 }
5288
5289 if (Subtarget.isUsingPCRelativeCalls()) {
5290 assert(Subtarget.is64BitELFABI() && "PC Relative is only on ELF ABI.")((Subtarget.is64BitELFABI() && "PC Relative is only on ELF ABI."
) ? static_cast<void> (0) : __assert_fail ("Subtarget.is64BitELFABI() && \"PC Relative is only on ELF ABI.\""
, "/build/llvm-toolchain-snapshot-12~++20201124111112+7b5254223ac/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5290, __PRETTY_FUNCTION__))
;
5291 return PPCISD::CALL_NOTOC;
5292 }
5293
5294 // The ABIs that maintain a TOC pointer accross calls need to have a nop
5295 // immediately following the call instruction if the caller and callee may
5296 // have different TOC bases. At link time if the linker determines the calls
5297 // may not share a TOC base, the call is redirected to a trampoline inserted
5298 // by the linker. The trampoline will (among other things) save the callers
5299 // TOC pointer at an ABI designated offset in the linkage area and the linker
5300 // will rewrite the nop to be a load of the TOC pointer from the linkage area
5301 // into gpr2.
5302 if (Subtarget.isAIXABI() || Subtarget.is64BitELFABI())
5303 return callsShareTOCBase(&Caller, Callee, TM) ? PPCISD::CALL
5304 : PPCISD::CALL_NOP;
5305
5306 return PPCISD::CALL;
5307}
5308
5309static SDValue transformCallee(const SDValue &Callee, SelectionDAG &DAG,
5310 const SDLoc &dl, const PPCSubtarget &Subtarget) {
5311 if (!Subtarget.usesFunctionDescriptors() && !Subtarget.isELFv2ABI())
5312 if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG))
5313 return SDValue(Dest, 0);
5314
5315 // Returns true if the callee is local, and false otherwise.
5316 auto isLocalCallee = [&]() {
5317 const GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
5318 const Module *Mod = DAG.getMachineFunction().getFunction().getParent();
5319 const GlobalValue *GV = G ? G->getGlobal() : nullptr;
5320
5321 return DAG.getTarget().shouldAssumeDSOLocal(*Mod, GV) &&
5322 !dyn_cast_or_null<GlobalIFunc>(GV);
5323 };
5324
5325 // The PLT is only used in 32-bit ELF PIC mode. Attempting to use the PLT in
5326 // a static relocation model causes some versions of GNU LD (2.17.50, at
5327 // least) to force BSS-PLT, instead of secure-PLT, even if all objects are
5328 // built with secure-PLT.
5329 bool UsePlt =
5330 Subtarget.is32BitELFABI() && !isLocalCallee() &&
5331 Subtarget.getTargetMachine().getRelocationModel() == Reloc::PIC_;
5332
5333 const auto getAIXFuncEntryPointSymbolSDNode = [&](const GlobalValue *GV) {
5334 const TargetMachine &TM = Subtarget.getTargetMachine();
5335 const TargetLoweringObjectFile *TLOF = TM.getObjFileLowering();
5336 MCSymbolXCOFF *S =
5337 cast<MCSymbolXCOFF>(TLOF->getFunctionEntryPointSymbol(GV, TM));
5338
5339 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
5340 return DAG.getMCSymbol(S, PtrVT);
5341 };
5342
5343 if (isFunctionGlobalAddress(Callee)) {
5344 const GlobalValue *GV = cast<GlobalAddressSDNode>(Callee)->getGlobal();
5345
5346 if (Subtarget.isAIXABI()) {
5347 assert(!isa<GlobalIFunc>(GV) && "IFunc is not supported on AIX.")((!isa<GlobalIFunc>(GV) && "IFunc is not supported on AIX."
) ? static_cast<void> (0) : __assert_fail ("!isa<GlobalIFunc>(GV) && \"IFunc is not supported on AIX.\""
, "/build/llvm-toolchain-snapshot-12~++20201124111112+7b5254223ac/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5347, __PRETTY_FUNCTION__))
;
5348 return getAIXFuncEntryPointSymbolSDNode(GV);
5349 }
5350 return DAG.getTargetGlobalAddress(GV, dl, Callee.getValueType(), 0,
5351 UsePlt ? PPCII::MO_PLT : 0);
5352 }
5353
5354 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
5355 const char *SymName = S->getSymbol();
5356 if (Subtarget.isAIXABI()) {
5357 // If there exists a user-declared function whose name is the same as the
5358 // ExternalSymbol's, then we pick up the user-declared version.
5359 const Module *Mod = DAG.getMachineFunction().getFunction().getParent();
5360 if (const Function *F =
5361 dyn_cast_or_null<Function>(Mod->getNamedValue(SymName)))
5362 return getAIXFuncEntryPointSymbolSDNode(F);
5363
5364 // On AIX, direct function calls reference the symbol for the function's
5365 // entry point, which is named by prepending a "." before the function's
5366 // C-linkage name. A Qualname is returned here because an external
5367 // function entry point is a csect with XTY_ER property.
5368 const auto getExternalFunctionEntryPointSymbol = [&](StringRef SymName) {
5369 auto &Context = DAG.getMachineFunction().getMMI().getContext();
5370 MCSectionXCOFF *Sec = Context.getXCOFFSection(
5371 (Twine(".") + Twine(SymName)).str(), XCOFF::XMC_PR, XCOFF::XTY_ER,
5372 SectionKind::getMetadata());
5373 return Sec->getQualNameSymbol();
5374 };
5375
5376 SymName = getExternalFunctionEntryPointSymbol(SymName)->getName().data();
5377 }
5378 return DAG.getTargetExternalSymbol(SymName, Callee.getValueType(),
5379 UsePlt ? PPCII::MO_PLT : 0);
5380 }
5381
5382 // No transformation needed.
5383 assert(Callee.getNode() && "What no callee?")((Callee.getNode() && "What no callee?") ? static_cast
<void> (0) : __assert_fail ("Callee.getNode() && \"What no callee?\""
, "/build/llvm-toolchain-snapshot-12~++20201124111112+7b5254223ac/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5383, __PRETTY_FUNCTION__))
;
5384 return Callee;
5385}
5386
5387static SDValue getOutputChainFromCallSeq(SDValue CallSeqStart) {
5388 assert(CallSeqStart.getOpcode() == ISD::CALLSEQ_START &&((CallSeqStart.getOpcode() == ISD::CALLSEQ_START && "Expected a CALLSEQ_STARTSDNode."
) ? static_cast<void> (0) : __assert_fail ("CallSeqStart.getOpcode() == ISD::CALLSEQ_START && \"Expected a CALLSEQ_STARTSDNode.\""
, "/build/llvm-toolchain-snapshot-12~++20201124111112+7b5254223ac/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5389, __PRETTY_FUNCTION__))
5389 "Expected a CALLSEQ_STARTSDNode.")((CallSeqStart.getOpcode() == ISD::CALLSEQ_START && "Expected a CALLSEQ_STARTSDNode."
) ? static_cast<void> (0) : __assert_fail ("CallSeqStart.getOpcode() == ISD::CALLSEQ_START && \"Expected a CALLSEQ_STARTSDNode.\""
, "/build/llvm-toolchain-snapshot-12~++20201124111112+7b5254223ac/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5389, __PRETTY_FUNCTION__))
;
5390
5391 // The last operand is the chain, except when the node has glue. If the node
5392 // has glue, then the last operand is the glue, and the chain is the second
5393 // last operand.
5394 SDValue LastValue = CallSeqStart.getValue(CallSeqStart->getNumValues() - 1);
5395 if (LastValue.getValueType() != MVT::Glue)
5396 return LastValue;
5397
5398 return CallSeqStart.getValue(CallSeqStart->getNumValues() - 2);
5399}
5400
5401// Creates the node that moves a functions address into the count register
5402// to prepare for an indirect call instruction.
5403static void prepareIndirectCall(SelectionDAG &DAG, SDValue &Callee,
5404 SDValue &Glue, SDValue &Chain,
5405 const SDLoc &dl) {
5406 SDValue MTCTROps[] = {Chain, Callee, Glue};
5407 EVT ReturnTypes[] = {MVT::Other, MVT::Glue};
5408 Chain = DAG.getNode(PPCISD::MTCTR, dl, makeArrayRef(ReturnTypes, 2),
5409 makeArrayRef(MTCTROps, Glue.getNode() ? 3 : 2));
5410 // The glue is the second value produced.
5411 Glue = Chain.getValue(1);
5412}
5413
5414static void prepareDescriptorIndirectCall(SelectionDAG &DAG, SDValue &Callee,
5415 SDValue &Glue, SDValue &Chain,
5416 SDValue CallSeqStart,
5417 const CallBase *CB, const SDLoc &dl,
5418 bool hasNest,
5419 const PPCSubtarget &Subtarget) {
5420 // Function pointers in the 64-bit SVR4 ABI do not point to the function
5421 // entry point, but to the function descriptor (the function entry point
5422 // address is part of the function descriptor though).
5423 // The function descriptor is a three doubleword structure with the
5424 // following fields: function entry point, TOC base address and
5425 // environment pointer.
5426 // Thus for a call through a function pointer, the following actions need
5427 // to be performed:
5428 // 1. Save the TOC of the caller in the TOC save area of its stack
5429 // frame (this is done in LowerCall_Darwin() or LowerCall_64SVR4()).
5430 // 2. Load the address of the function entry point from the function
5431 // descriptor.
5432 // 3. Load the TOC of the callee from the function descriptor into r2.
5433 // 4. Load the environment pointer from the function descriptor into
5434 // r11.
5435 // 5. Branch to the function entry point address.
5436 // 6. On return of the callee, the TOC of the caller needs to be
5437 // restored (this is done in FinishCall()).
5438 //
5439 // The loads are scheduled at the beginning of the call sequence, and the
5440 // register copies are flagged together to ensure that no other
5441 // operations can be scheduled in between. E.g. without flagging the
5442 // copies together, a TOC access in the caller could be scheduled between
5443 // the assignment of the callee TOC and the branch to the callee, which leads
5444 // to incorrect code.
5445
5446 // Start by loading the function address from the descriptor.
5447 SDValue LDChain = getOutputChainFromCallSeq(CallSeqStart);
5448 auto MMOFlags = Subtarget.hasInvariantFunctionDescriptors()
5449 ? (MachineMemOperand::MODereferenceable |
5450 MachineMemOperand::MOInvariant)
5451 : MachineMemOperand::MONone;
5452
5453 MachinePointerInfo MPI(CB ? CB->getCalledOperand() : nullptr);
5454
5455 // Registers used in building the DAG.
5456 const MCRegister EnvPtrReg = Subtarget.getEnvironmentPointerRegister();
5457 const MCRegister TOCReg = Subtarget.getTOCPointerRegister();
5458
5459 // Offsets of descriptor members.
5460 const unsigned TOCAnchorOffset = Subtarget.descriptorTOCAnchorOffset();
5461 const unsigned EnvPtrOffset = Subtarget.descriptorEnvironmentPointerOffset();
5462
5463 const MVT RegVT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32;
5464 const unsigned Alignment = Subtarget.isPPC64() ? 8 : 4;
5465
5466 // One load for the functions entry point address.
5467 SDValue LoadFuncPtr = DAG.getLoad(RegVT, dl, LDChain, Callee, MPI,
5468 Alignment, MMOFlags);
5469
5470 // One for loading the TOC anchor for the module that contains the called
5471 // function.
5472 SDValue TOCOff = DAG.getIntPtrConstant(TOCAnchorOffset, dl);
5473 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, RegVT, Callee, TOCOff);
5474 SDValue TOCPtr =
5475 DAG.getLoad(RegVT, dl, LDChain, AddTOC,
5476 MPI.getWithOffset(TOCAnchorOffset), Alignment, MMOFlags);
5477
5478 // One for loading the environment pointer.
5479 SDValue PtrOff = DAG.getIntPtrConstant(EnvPtrOffset, dl);
5480 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, RegVT, Callee, PtrOff);
5481 SDValue LoadEnvPtr =
5482 DAG.getLoad(RegVT, dl, LDChain, AddPtr,
5483 MPI.getWithOffset(EnvPtrOffset), Alignment, MMOFlags);
5484
5485
5486 // Then copy the newly loaded TOC anchor to the TOC pointer.
5487 SDValue TOCVal = DAG.getCopyToReg(Chain, dl, TOCReg, TOCPtr, Glue);
5488 Chain = TOCVal.getValue(0);
5489 Glue = TOCVal.getValue(1);
5490
5491 // If the function call has an explicit 'nest' parameter, it takes the
5492 // place of the environment pointer.
5493 assert((!hasNest || !Subtarget.isAIXABI()) &&(((!hasNest || !Subtarget.isAIXABI()) && "Nest parameter is not supported on AIX."
) ? static_cast<void> (0) : __assert_fail ("(!hasNest || !Subtarget.isAIXABI()) && \"Nest parameter is not supported on AIX.\""
, "/build/llvm-toolchain-snapshot-12~++20201124111112+7b5254223ac/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5494, __PRETTY_FUNCTION__))
5494 "Nest parameter is not supported on AIX.")(((!hasNest || !Subtarget.isAIXABI()) && "Nest parameter is not supported on AIX."
) ? static_cast<void> (0) : __assert_fail ("(!hasNest || !Subtarget.isAIXABI()) && \"Nest parameter is not supported on AIX.\""
, "/build/llvm-toolchain-snapshot-12~++20201124111112+7b5254223ac/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5494, __PRETTY_FUNCTION__))
;
5495 if (!hasNest) {
5496 SDValue EnvVal = DAG.getCopyToReg(Chain, dl, EnvPtrReg, LoadEnvPtr, Glue);
5497 Chain = EnvVal.getValue(0);
5498 Glue = EnvVal.getValue(1);
5499 }
5500
5501 // The rest of the indirect call sequence is the same as the non-descriptor
5502 // DAG.
5503 prepareIndirectCall(DAG, LoadFuncPtr, Glue, Chain, dl);
5504}
5505
5506static void
5507buildCallOperands(SmallVectorImpl<SDValue> &Ops,
5508 PPCTargetLowering::CallFlags CFlags, const SDLoc &dl,
5509 SelectionDAG &DAG,
5510 SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass,
5511 SDValue Glue, SDValue Chain, SDValue &Callee, int SPDiff,
5512 const PPCSubtarget &Subtarget) {
5513 const bool IsPPC64 = Subtarget.isPPC64();
5514 // MVT for a general purpose register.
5515 const MVT RegVT = IsPPC64 ? MVT::i64 : MVT::i32;
5516
5517 // First operand is always the chain.
5518 Ops.push_back(Chain);
5519
5520 // If it's a direct call pass the callee as the second operand.
5521 if (!CFlags.IsIndirect)
5522 Ops.push_back(Callee);
5523 else {
5524 assert(!CFlags.IsPatchPoint && "Patch point calls are not indirect.")((!CFlags.IsPatchPoint && "Patch point calls are not indirect."
) ? static_cast<void> (0) : __assert_fail ("!CFlags.IsPatchPoint && \"Patch point calls are not indirect.\""
, "/build/llvm-toolchain-snapshot-12~++20201124111112+7b5254223ac/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5524, __PRETTY_FUNCTION__))
;
5525
5526 // For the TOC based ABIs, we have saved the TOC pointer to the linkage area
5527 // on the stack (this would have been done in `LowerCall_64SVR4` or
5528 // `LowerCall_AIX`). The call instruction is a pseudo instruction that
5529 // represents both the indirect branch and a load that restores the TOC
5530 // pointer from the linkage area. The operand for the TOC restore is an add
5531 // of the TOC save offset to the stack pointer. This must be the second
5532 // operand: after the chain input but before any other variadic arguments.
5533 // For 64-bit ELFv2 ABI with PCRel, do not restore the TOC as it is not
5534 // saved or used.
5535 if (isTOCSaveRestoreRequired(Subtarget)) {
5536 const MCRegister StackPtrReg = Subtarget.getStackPointerRegister();
5537
5538 SDValue StackPtr = DAG.getRegister(StackPtrReg, RegVT);
5539 unsigned TOCSaveOffset = Subtarget.getFrameLowering()->getTOCSaveOffset();
5540 SDValue TOCOff = DAG.getIntPtrConstant(TOCSaveOffset, dl);
5541 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, RegVT, StackPtr, TOCOff);
5542 Ops.push_back(AddTOC);
5543 }
5544
5545 // Add the register used for the environment pointer.
5546 if (Subtarget.usesFunctionDescriptors() && !CFlags.HasNest)
5547 Ops.push_back(DAG.getRegister(Subtarget.getEnvironmentPointerRegister(),
5548 RegVT));
5549
5550
5551 // Add CTR register as callee so a bctr can be emitted later.
5552 if (CFlags.IsTailCall)
5553 Ops.push_back(DAG.getRegister(IsPPC64 ? PPC::CTR8 : PPC::CTR, RegVT));
5554 }
5555
5556 // If this is a tail call add stack pointer delta.
5557 if (CFlags.IsTailCall)
5558 Ops.push_back(DAG.getConstant(SPDiff, dl, MVT::i32));
5559
5560 // Add argument registers to the end of the list so that they are known live
5561 // into the call.
5562 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
5563 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
5564 RegsToPass[i].second.getValueType()));
5565
5566 // We cannot add R2/X2 as an operand here for PATCHPOINT, because there is
5567 // no way to mark dependencies as implicit here.
5568 // We will add the R2/X2 dependency in EmitInstrWithCustomInserter.
5569 if ((Subtarget.is64BitELFABI() || Subtarget.isAIXABI()) &&
5570 !CFlags.IsPatchPoint && !Subtarget.isUsingPCRelativeCalls())
5571 Ops.push_back(DAG.getRegister(Subtarget.getTOCPointerRegister(), RegVT));
5572
5573 // Add implicit use of CR bit 6 for 32-bit SVR4 vararg calls
5574 if (CFlags.IsVarArg && Subtarget.is32BitELFABI())
5575 Ops.push_back(DAG.getRegister(PPC::CR1EQ, MVT::i32));
5576
5577 // Add a register mask operand representing the call-preserved registers.
5578 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
5579 const uint32_t *Mask =
5580 TRI->getCallPreservedMask(DAG.getMachineFunction(), CFlags.CallConv);
5581 assert(Mask && "Missing call preserved mask for calling convention")((Mask && "Missing call preserved mask for calling convention"
) ? static_cast<void> (0) : __assert_fail ("Mask && \"Missing call preserved mask for calling convention\""
, "/build/llvm-toolchain-snapshot-12~++20201124111112+7b5254223ac/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5581, __PRETTY_FUNCTION__))
;
5582 Ops.push_back(DAG.getRegisterMask(Mask));
5583
5584 // If the glue is valid, it is the last operand.
5585 if (Glue.getNode())
5586 Ops.push_back(Glue);
5587}
5588
5589SDValue PPCTargetLowering::FinishCall(
5590 CallFlags CFlags, const SDLoc &dl, SelectionDAG &DAG,
5591 SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass, SDValue Glue,
5592 SDValue Chain, SDValue CallSeqStart, SDValue &Callee, int SPDiff,
5593 unsigned NumBytes, const SmallVectorImpl<ISD::InputArg> &Ins,
5594 SmallVectorImpl<SDValue> &InVals, const CallBase *CB) const {
5595
5596 if ((Subtarget.is64BitELFABI() && !Subtarget.isUsingPCRelativeCalls()) ||
5597 Subtarget.isAIXABI())
5598 setUsesTOCBasePtr(DAG);
5599
5600 unsigned CallOpc =
5601 getCallOpcode(CFlags, DAG.getMachineFunction().getFunction(), Callee,
5602 Subtarget, DAG.getTarget());
5603
5604 if (!CFlags.IsIndirect)
5605 Callee = transformCallee(Callee, DAG, dl, Subtarget);
5606 else if (Subtarget.usesFunctionDescriptors())
5607 prepareDescriptorIndirectCall(DAG, Callee, Glue, Chain, CallSeqStart, CB,
5608 dl, CFlags.HasNest, Subtarget);
5609 else
5610 prepareIndirectCall(DAG, Callee, Glue, Chain, dl);
5611
5612 // Build the operand list for the call instruction.
5613 SmallVector<SDValue, 8> Ops;
5614 buildCallOperands(Ops, CFlags, dl, DAG, RegsToPass, Glue, Chain, Callee,
5615 SPDiff, Subtarget);
5616
5617 // Emit tail call.
5618 if (CFlags.IsTailCall) {
5619 // Indirect tail call when using PC Relative calls do not have the same
5620 // constraints.
5621 assert(((Callee.getOpcode() == ISD::Register &&((((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode
>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() ==
ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress
|| isa<ConstantSDNode>(Callee) || (CFlags.IsIndirect &&
Subtarget.isUsingPCRelativeCalls())) && "Expecting a global address, external symbol, absolute value, "
"register or an indirect tail call when PC Relative calls are "
"used.") ? static_cast<void> (0) : __assert_fail ("((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress || isa<ConstantSDNode>(Callee) || (CFlags.IsIndirect && Subtarget.isUsingPCRelativeCalls())) && \"Expecting a global address, external symbol, absolute value, \" \"register or an indirect tail call when PC Relative calls are \" \"used.\""
, "/build/llvm-toolchain-snapshot-12~++20201124111112+7b5254223ac/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5629, __PRETTY_FUNCTION__))
5622 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) ||((((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode
>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() ==
ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress
|| isa<ConstantSDNode>(Callee) || (CFlags.IsIndirect &&
Subtarget.isUsingPCRelativeCalls())) && "Expecting a global address, external symbol, absolute value, "
"register or an indirect tail call when PC Relative calls are "
"used.") ? static_cast<void> (0) : __assert_fail ("((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress || isa<ConstantSDNode>(Callee) || (CFlags.IsIndirect && Subtarget.isUsingPCRelativeCalls())) && \"Expecting a global address, external symbol, absolute value, \" \"register or an indirect tail call when PC Relative calls are \" \"used.\""
, "/build/llvm-toolchain-snapshot-12~++20201124111112+7b5254223ac/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5629, __PRETTY_FUNCTION__))
5623 Callee.getOpcode() == ISD::TargetExternalSymbol ||((((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode
>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() ==
ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress
|| isa<ConstantSDNode>(Callee) || (CFlags.IsIndirect &&
Subtarget.isUsingPCRelativeCalls())) && "Expecting a global address, external symbol, absolute value, "
"register or an indirect tail call when PC Relative calls are "
"used.") ? static_cast<void> (0) : __assert_fail ("((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress || isa<ConstantSDNode>(Callee) || (CFlags.IsIndirect && Subtarget.isUsingPCRelativeCalls())) && \"Expecting a global address, external symbol, absolute value, \" \"register or an indirect tail call when PC Relative calls are \" \"used.\""
, "/build/llvm-toolchain-snapshot-12~++20201124111112+7b5254223ac/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5629, __PRETTY_FUNCTION__))
5624 Callee.getOpcode() == ISD::TargetGlobalAddress ||((((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode
>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() ==
ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress
|| isa<ConstantSDNode>(Callee) || (CFlags.IsIndirect &&
Subtarget.isUsingPCRelativeCalls())) && "Expecting a global address, external symbol, absolute value, "
"register or an indirect tail call when PC Relative calls are "
"used.") ? static_cast<void> (0) : __assert_fail ("((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress || isa<ConstantSDNode>(Callee) || (CFlags.IsIndirect && Subtarget.isUsingPCRelativeCalls())) && \"Expecting a global address, external symbol, absolute value, \" \"register or an indirect tail call when PC Relative calls are \" \"used.\""
, "/build/llvm-toolchain-snapshot-12~++20201124111112+7b5254223ac/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5629, __PRETTY_FUNCTION__))
5625 isa<ConstantSDNode>(Callee) ||((((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode
>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() ==
ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress
|| isa<ConstantSDNode>(Callee) || (CFlags.IsIndirect &&
Subtarget.isUsingPCRelativeCalls())) && "Expecting a global address, external symbol, absolute value, "
"register or an indirect tail call when PC Relative calls are "
"used.") ? static_cast<void> (0) : __assert_fail ("((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress || isa<ConstantSDNode>(Callee) || (CFlags.IsIndirect && Subtarget.isUsingPCRelativeCalls())) && \"Expecting a global address, external symbol, absolute value, \" \"register or an indirect tail call when PC Relative calls are \" \"used.\""
, "/build/llvm-toolchain-snapshot-12~++20201124111112+7b5254223ac/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5629, __PRETTY_FUNCTION__))
5626 (CFlags.IsIndirect && Subtarget.isUsingPCRelativeCalls())) &&((((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode
>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() ==
ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress
|| isa<ConstantSDNode>(Callee) || (CFlags.IsIndirect &&
Subtarget.isUsingPCRelativeCalls())) && "Expecting a global address, external symbol, absolute value, "
"register or an indirect tail call when PC Relative calls are "
"used.") ? static_cast<void> (0) : __assert_fail ("((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress || isa<ConstantSDNode>(Callee) || (CFlags.IsIndirect && Subtarget.isUsingPCRelativeCalls())) && \"Expecting a global address, external symbol, absolute value, \" \"register or an indirect tail call when PC Relative calls are \" \"used.\""
, "/build/llvm-toolchain-snapshot-12~++20201124111112+7b5254223ac/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5629, __PRETTY_FUNCTION__))
5627 "Expecting a global address, external symbol, absolute value, "((((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode
>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() ==
ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress
|| isa<ConstantSDNode>(Callee) || (CFlags.IsIndirect &&
Subtarget.isUsingPCRelativeCalls())) && "Expecting a global address, external symbol, absolute value, "
"register or an indirect tail call when PC Relative calls are "
"used.") ? static_cast<void> (0) : __assert_fail ("((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress || isa<ConstantSDNode>(Callee) || (CFlags.IsIndirect && Subtarget.isUsingPCRelativeCalls())) && \"Expecting a global address, external symbol, absolute value, \" \"register or an indirect tail call when PC Relative calls are \" \"used.\""
, "/build/llvm-toolchain-snapshot-12~++20201124111112+7b5254223ac/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5629, __PRETTY_FUNCTION__))
5628 "register or an indirect tail call when PC Relative calls are "((((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode
>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() ==
ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress
|| isa<ConstantSDNode>(Callee) || (CFlags.IsIndirect &&
Subtarget.isUsingPCRelativeCalls())) && "Expecting a global address, external symbol, absolute value, "
"register or an indirect tail call when PC Relative calls are "
"used.") ? static_cast<void> (0) : __assert_fail ("((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress || isa<ConstantSDNode>(Callee) || (CFlags.IsIndirect && Subtarget.isUsingPCRelativeCalls())) && \"Expecting a global address, external symbol, absolute value, \" \"register or an indirect tail call when PC Relative calls are \" \"used.\""
, "/build/llvm-toolchain-snapshot-12~++20201124111112+7b5254223ac/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5629, __PRETTY_FUNCTION__))
5629 "used.")((((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode
>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() ==
ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress
|| isa<ConstantSDNode>(Callee) || (CFlags.IsIndirect &&
Subtarget.isUsingPCRelativeCalls())) && "Expecting a global address, external symbol, absolute value, "
"register or an indirect tail call when PC Relative calls are "
"used.") ? static_cast<void> (0) : __assert_fail ("((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress || isa<ConstantSDNode>(Callee) || (CFlags.IsIndirect && Subtarget.isUsingPCRelativeCalls())) && \"Expecting a global address, external symbol, absolute value, \" \"register or an indirect tail call when PC Relative calls are \" \"used.\""
, "/build/llvm-toolchain-snapshot-12~++20201124111112+7b5254223ac/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5629, __PRETTY_FUNCTION__))
;
5630 // PC Relative calls also use TC_RETURN as the way to mark tail calls.
5631 assert(CallOpc == PPCISD::TC_RETURN &&((CallOpc == PPCISD::TC_RETURN && "Unexpected call opcode for a tail call."
) ? static_cast<void> (0) : __assert_fail ("CallOpc == PPCISD::TC_RETURN && \"Unexpected call opcode for a tail call.\""
, "/build/llvm-toolchain-snapshot-12~++20201124111112+7b5254223ac/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5632, __PRETTY_FUNCTION__))
5632 "Unexpected call opcode for a tail call.")((CallOpc == PPCISD::TC_RETURN && "Unexpected call opcode for a tail call."
) ? static_cast<void> (0) : __assert_fail ("CallOpc == PPCISD::TC_RETURN && \"Unexpected call opcode for a tail call.\""
, "/build/llvm-toolchain-snapshot-12~++20201124111112+7b5254223ac/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5632, __PRETTY_FUNCTION__))
;
5633 DAG.getMachineFunction().getFrameInfo().setHasTailCall();
5634 return DAG.getNode(CallOpc, dl, MVT::Other, Ops);
5635 }
5636
5637 std::array<EVT, 2> ReturnTypes = {{MVT::Other, MVT::Glue}};
5638 Chain = DAG.getNode(CallOpc, dl, ReturnTypes, Ops);
5639 DAG.addNoMergeSiteInfo(Chain.getNode(), CFlags.NoMerge);
5640 Glue = Chain.getValue(1);
5641
5642 // When performing tail call optimization the callee pops its arguments off
5643 // the stack. Account for this here so these bytes can be pushed back on in
5644 // PPCFrameLowering::eliminateCallFramePseudoInstr.
5645 int BytesCalleePops = (CFlags.CallConv == CallingConv::Fast &&
5646 getTargetMachine().Options.GuaranteedTailCallOpt)
5647 ? NumBytes
5648 : 0;
5649
5650 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
5651 DAG.getIntPtrConstant(BytesCalleePops, dl, true),
5652 Glue, dl);
5653 Glue = Chain.getValue(1);
5654
5655 return LowerCallResult(Chain, Glue, CFlags.CallConv, CFlags.IsVarArg, Ins, dl,
5656 DAG, InVals);
5657}
5658
5659SDValue
5660PPCTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
5661 SmallVectorImpl<SDValue> &InVals) const {
5662 SelectionDAG &DAG = CLI.DAG;
5663 SDLoc &dl = CLI.DL;
5664 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
5665 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
5666 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
5667 SDValue Chain = CLI.Chain;
5668 SDValue Callee = CLI.Callee;
5669 bool &isTailCall = CLI.IsTailCall;
5670 CallingConv::ID CallConv = CLI.CallConv;
5671 bool isVarArg = CLI.IsVarArg;
5672 bool isPatchPoint = CLI.IsPatchPoint;
5673 const CallBase *CB = CLI.CB;
5674
5675 if (isTailCall) {
5676 if (Subtarget.useLongCalls() && !(CB && CB->isMustTailCall()))
5677 isTailCall = false;
5678 else if (Subtarget.isSVR4ABI() && Subtarget.isPPC64())
5679 isTailCall = IsEligibleForTailCallOptimization_64SVR4(
5680 Callee, CallConv, CB, isVarArg, Outs, Ins, DAG);
5681 else
5682 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg,
5683 Ins, DAG);
5684 if (isTailCall) {
5685 ++NumTailCalls;
5686 if (!getTargetMachine().Options.GuaranteedTailCallOpt)
5687 ++NumSiblingCalls;
5688
5689 // PC Relative calls no longer guarantee that the callee is a Global
5690 // Address Node. The callee could be an indirect tail call in which
5691 // case the SDValue for the callee could be a load (to load the address
5692 // of a function pointer) or it may be a register copy (to move the
5693 // address of the callee from a function parameter into a virtual
5694 // register). It may also be an ExternalSymbolSDNode (ex memcopy).
5695 assert((Subtarget.isUsingPCRelativeCalls() ||(((Subtarget.isUsingPCRelativeCalls() || isa<GlobalAddressSDNode
>(Callee)) && "Callee should be an llvm::Function object."
) ? static_cast<void> (0) : __assert_fail ("(Subtarget.isUsingPCRelativeCalls() || isa<GlobalAddressSDNode>(Callee)) && \"Callee should be an llvm::Function object.\""
, "/build/llvm-toolchain-snapshot-12~++20201124111112+7b5254223ac/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5697, __PRETTY_FUNCTION__))
5696 isa<GlobalAddressSDNode>(Callee)) &&(((Subtarget.isUsingPCRelativeCalls() || isa<GlobalAddressSDNode
>(Callee)) && "Callee should be an llvm::Function object."
) ? static_cast<void> (0) : __assert_fail ("(Subtarget.isUsingPCRelativeCalls() || isa<GlobalAddressSDNode>(Callee)) && \"Callee should be an llvm::Function object.\""
, "/build/llvm-toolchain-snapshot-12~++20201124111112+7b5254223ac/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5697, __PRETTY_FUNCTION__))
5697 "Callee should be an llvm::Function object.")(((Subtarget.isUsingPCRelativeCalls() || isa<GlobalAddressSDNode
>(Callee)) && "Callee should be an llvm::Function object."
) ? static_cast<void> (0) : __assert_fail ("(Subtarget.isUsingPCRelativeCalls() || isa<GlobalAddressSDNode>(Callee)) && \"Callee should be an llvm::Function object.\""
, "/build/llvm-toolchain-snapshot-12~++20201124111112+7b5254223ac/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5697, __PRETTY_FUNCTION__))
;
5698
5699 LLVM_DEBUG(dbgs() << "TCO caller: " << DAG.getMachineFunction().getName()do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("ppc-lowering")) { dbgs() << "TCO caller: " << DAG
.getMachineFunction().getName() << "\nTCO callee: "; } }
while (false)
5700 << "\nTCO callee: ")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("ppc-lowering")) { dbgs() << "TCO caller: " << DAG
.getMachineFunction().getName() << "\nTCO callee: "; } }
while (false)
;
5701 LLVM_DEBUG(Callee.dump())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("ppc-lowering")) { Callee.dump(); } } while (false)
;
5702 }
5703 }
5704
5705 if (!isTailCall && CB && CB->isMustTailCall())
5706 report_fatal_error("failed to perform tail call elimination on a call "
5707 "site marked musttail");
5708
5709 // When long calls (i.e. indirect calls) are always used, calls are always
5710 // made via function pointer. If we have a function name, first translate it
5711 // into a pointer.
5712 if (Subtarget.useLongCalls() && isa<GlobalAddressSDNode>(Callee) &&
5713 !isTailCall)
5714 Callee = LowerGlobalAddress(Callee, DAG);
5715
5716 CallFlags CFlags(
5717 CallConv, isTailCall, isVarArg, isPatchPoint,
5718 isIndirectCall(Callee, DAG, Subtarget, isPatchPoint),
5719 // hasNest
5720 Subtarget.is64BitELFABI() &&
5721 any_of(Outs, [](ISD::OutputArg Arg) { return Arg.Flags.isNest(); }),
5722 CLI.NoMerge);
5723
5724 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64())
5725 return LowerCall_64SVR4(Chain, Callee, CFlags, Outs, OutVals, Ins, dl, DAG,
5726 InVals, CB);
5727
5728 if (Subtarget.isSVR4ABI())
5729 return LowerCall_32SVR4(Chain, Callee, CFlags, Outs, OutVals, Ins, dl, DAG,
5730 InVals, CB);
5731
5732 if (Subtarget.isAIXABI())
5733 return LowerCall_AIX(Chain, Callee, CFlags, Outs, OutVals, Ins, dl, DAG,
5734 InVals, CB);
5735
5736 return LowerCall_Darwin(Chain, Callee, CFlags, Outs, OutVals, Ins, dl, DAG,
5737 InVals, CB);
5738}
5739
5740SDValue PPCTargetLowering::LowerCall_32SVR4(
5741 SDValue Chain, SDValue Callee, CallFlags CFlags,
5742 const SmallVectorImpl<ISD::OutputArg> &Outs,
5743 const SmallVectorImpl<SDValue> &OutVals,
5744 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
5745 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals,
5746 const CallBase *CB) const {
5747 // See PPCTargetLowering::LowerFormalArguments_32SVR4() for a description
5748 // of the 32-bit SVR4 ABI stack frame layout.
5749
5750 const CallingConv::ID CallConv = CFlags.CallConv;
5751 const bool IsVarArg = CFlags.IsVarArg;
5752 const bool IsTailCall = CFlags.IsTailCall;
5753
5754 assert((CallConv == CallingConv::C ||(((CallConv == CallingConv::C || CallConv == CallingConv::Cold
|| CallConv == CallingConv::Fast) && "Unknown calling convention!"
) ? static_cast<void> (0) : __assert_fail ("(CallConv == CallingConv::C || CallConv == CallingConv::Cold || CallConv == CallingConv::Fast) && \"Unknown calling convention!\""
, "/build/llvm-toolchain-snapshot-12~++20201124111112+7b5254223ac/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5756, __PRETTY_FUNCTION__))
5755 CallConv == CallingConv::Cold ||(((CallConv == CallingConv::C || CallConv == CallingConv::Cold
|| CallConv == CallingConv::Fast) && "Unknown calling convention!"
) ? static_cast<void> (0) : __assert_fail ("(CallConv == CallingConv::C || CallConv == CallingConv::Cold || CallConv == CallingConv::Fast) && \"Unknown calling convention!\""
, "/build/llvm-toolchain-snapshot-12~++20201124111112+7b5254223ac/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5756, __PRETTY_FUNCTION__))
5756 CallConv == CallingConv::Fast) && "Unknown calling convention!")(((CallConv == CallingConv::C || CallConv == CallingConv::Cold
|| CallConv == CallingConv::Fast) && "Unknown calling convention!"
) ? static_cast<void> (0) : __assert_fail ("(CallConv == CallingConv::C || CallConv == CallingConv::Cold || CallConv == CallingConv::Fast) && \"Unknown calling convention!\""
, "/build/llvm-toolchain-snapshot-12~++20201124111112+7b5254223ac/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5756, __PRETTY_FUNCTION__))
;
5757
5758 const Align PtrAlign(4);
5759
5760 MachineFunction &MF = DAG.getMachineFunction();
5761
5762 // Mark this function as potentially containing a function that contains a
5763 // tail call. As a consequence the frame pointer will be used for dynamicalloc
5764 // and restoring the callers stack pointer in this functions epilog. This is
5765 // done because by tail calling the called function might overwrite the value
5766 // in this function's (MF) stack pointer stack slot 0(SP).
5767 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
5768 CallConv == CallingConv::Fast)
5769 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
5770
5771 // Count how many bytes are to be pushed on the stack, including the linkage
5772 // area, parameter list area and the part of the local variable space which
5773 // contains copies of aggregates which are passed by value.
5774
5775 // Assign locations to all of the outgoing arguments.
5776 SmallVector<CCValAssign, 16> ArgLocs;
5777 PPCCCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
5778
5779 // Reserve space for the linkage area on the stack.
5780 CCInfo.AllocateStack(Subtarget.getFrameLowering()->getLinkageSize(),
5781 PtrAlign);
5782 if (useSoftFloat())
5783 CCInfo.PreAnalyzeCallOperands(Outs);
5784
5785 if (IsVarArg) {
5786 // Handle fixed and variable vector arguments differently.
5787 // Fixed vector arguments go into registers as long as registers are
5788 // available. Variable vector arguments always go into memory.
5789 unsigned NumArgs = Outs.size();
5790
5791 for (unsigned i = 0; i != NumArgs; ++i) {
5792 MVT ArgVT = Outs[i].VT;
5793 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
5794 bool Result;
5795
5796 if (Outs[i].IsFixed) {
5797 Result = CC_PPC32_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags,
5798 CCInfo);
5799 } else {
5800 Result = CC_PPC32_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full,
5801 ArgFlags, CCInfo);
5802 }
5803
5804 if (Result) {
5805#ifndef NDEBUG
5806 errs() << "Call operand #" << i << " has unhandled type "
5807 << EVT(ArgVT).getEVTString() << "\n";
5808#endif
5809 llvm_unreachable(nullptr)::llvm::llvm_unreachable_internal(nullptr, "/build/llvm-toolchain-snapshot-12~++20201124111112+7b5254223ac/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5809)
;
5810 }
5811 }
5812 } else {
5813 // All arguments are treated the same.
5814 CCInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4);
5815 }
5816 CCInfo.clearWasPPCF128();
5817
5818 // Assign locations to all of the outgoing aggregate by value arguments.
5819 SmallVector<CCValAssign, 16> ByValArgLocs;
5820 CCState CCByValInfo(CallConv, IsVarArg, MF, ByValArgLocs, *DAG.getContext());
5821
5822 // Reserve stack space for the allocations in CCInfo.
5823 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrAlign);
5824
5825 CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4_ByVal);
5826
5827 // Size of the linkage area, parameter list area and the part of the local
5828 // space variable where copies of aggregates which are passed by value are
5829 // stored.
5830 unsigned NumBytes = CCByValInfo.getNextStackOffset();
5831
5832 // Calculate by how many bytes the stack has to be adjusted in case of tail
5833 // call optimization.
5834 int SPDiff = CalculateTailCallSPDiff(DAG, IsTailCall, NumBytes);
5835
5836 // Adjust the stack pointer for the new arguments...
5837 // These operations are automatically eliminated by the prolog/epilog pass
5838 Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, dl);
5839 SDValue CallSeqStart = Chain;
5840
5841 // Load the return address and frame pointer so it can be moved somewhere else
5842 // later.
5843 SDValue LROp, FPOp;
5844 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, dl);
5845
5846 // Set up a copy of the stack pointer for use loading and storing any
5847 // arguments that may not fit in the registers available for argument
5848 // passing.
5849 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
5850
5851 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
5852 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
5853 SmallVector<SDValue, 8> MemOpChains;
5854
5855 bool seenFloatArg = false;
5856 // Walk the register/memloc assignments, inserting copies/loads.
5857 // i - Tracks the index into the list of registers allocated for the call
5858 // RealArgIdx - Tracks the index into the list of actual function arguments
5859 // j - Tracks the index into the list of byval arguments
5860 for (unsigned i = 0, RealArgIdx = 0, j = 0, e = ArgLocs.size();
5861 i != e;
5862 ++i, ++RealArgIdx) {
5863 CCValAssign &VA = ArgLocs[i];
5864 SDValue Arg = OutVals[RealArgIdx];
5865 ISD::ArgFlagsTy Flags = Outs[RealArgIdx].Flags;
5866
5867 if (Flags.isByVal()) {
5868 // Argument is an aggregate which is passed by value, thus we need to
5869 // create a copy of it in the local variable space of the current stack
5870 // frame (which is the stack frame of the caller) and pass the address of
5871 // this copy to the callee.
5872 assert((j < ByValArgLocs.size()) && "Index out of bounds!")(((j < ByValArgLocs.size()) && "Index out of bounds!"
) ? static_cast<void> (0) : __assert_fail ("(j < ByValArgLocs.size()) && \"Index out of bounds!\""
, "/build/llvm-toolchain-snapshot-12~++20201124111112+7b5254223ac/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5872, __PRETTY_FUNCTION__))
;
5873 CCValAssign &ByValVA = ByValArgLocs[j++];
5874 assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!")(((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!"
) ? static_cast<void> (0) : __assert_fail ("(VA.getValNo() == ByValVA.getValNo()) && \"ValNo mismatch!\""
, "/build/llvm-toolchain-snapshot-12~++20201124111112+7b5254223ac/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5874, __PRETTY_FUNCTION__))
;
5875
5876 // Memory reserved in the local variable space of the callers stack frame.
5877 unsigned LocMemOffset = ByValVA.getLocMemOffset();
5878
5879 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
5880 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(MF.getDataLayout()),
5881 StackPtr, PtrOff);
5882
5883 // Create a copy of the argument in the local area of the current
5884 // stack frame.
5885 SDValue MemcpyCall =
5886 CreateCopyOfByValArgument(Arg, PtrOff,
5887 CallSeqStart.getNode()->getOperand(0),
5888 Flags, DAG, dl);
5889
5890 // This must go outside the CALLSEQ_START..END.
5891 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall, NumBytes, 0,
5892 SDLoc(MemcpyCall));
5893 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
5894 NewCallSeqStart.getNode());
5895 Chain = CallSeqStart = NewCallSeqStart;
5896
5897 // Pass the address of the aggregate copy on the stack either in a
5898 // physical register or in the parameter list area of the current stack
5899 // frame to the callee.
5900 Arg = PtrOff;
5901 }
5902
5903 // When useCRBits() is true, there can be i1 arguments.
5904 // It is because getRegisterType(MVT::i1) => MVT::i1,
5905 // and for other integer types getRegisterType() => MVT::i32.
5906 // Extend i1 and ensure callee will get i32.
5907 if (Arg.getValueType() == MVT::i1)
5908 Arg = DAG.getNode(Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
5909 dl, MVT::i32, Arg);
5910
5911 if (VA.isRegLoc()) {
5912 seenFloatArg |= VA.getLocVT().isFloatingPoint();
5913 // Put argument in a physical register.
5914 if (Subtarget.hasSPE() && Arg.getValueType() == MVT::f64) {
5915 bool IsLE = Subtarget.isLittleEndian();
5916 SDValue SVal = DAG.getNode(PPCISD::EXTRACT_SPE, dl, MVT::i32, Arg,
5917 DAG.getIntPtrConstant(IsLE ? 0 : 1, dl));
5918 RegsToPass.push_back(std::make_pair(VA.getLocReg(), SVal.getValue(0)));
5919 SVal = DAG.getNode(PPCISD::EXTRACT_SPE, dl, MVT::i32, Arg,
5920 DAG.getIntPtrConstant(IsLE ? 1 : 0, dl));
5921 RegsToPass.push_back(std::make_pair(ArgLocs[++i]