Bug Summary

File:lib/Target/PowerPC/PPCInstrInfo.cpp
Warning:line 1752, column 20
Value stored to 'NewPred' during its initialization is never read

Annotated Source Code

Press '?' to see keyboard shortcuts

clang -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name PPCInstrInfo.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-eagerly-assume -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -mrelocation-model pic -pic-level 2 -mthread-model posix -fmath-errno -masm-verbose -mconstructor-aliases -munwind-tables -fuse-init-array -target-cpu x86-64 -dwarf-column-info -debugger-tuning=gdb -momit-leaf-frame-pointer -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-7/lib/clang/7.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-7~svn338205/build-llvm/lib/Target/PowerPC -I /build/llvm-toolchain-snapshot-7~svn338205/lib/Target/PowerPC -I /build/llvm-toolchain-snapshot-7~svn338205/build-llvm/include -I /build/llvm-toolchain-snapshot-7~svn338205/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/8/../../../../include/c++/8 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/8/../../../../include/x86_64-linux-gnu/c++/8 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/8/../../../../include/x86_64-linux-gnu/c++/8 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/8/../../../../include/c++/8/backward -internal-isystem /usr/include/clang/7.0.0/include/ -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-7/lib/clang/7.0.0/include -internal-externc-isystem /usr/lib/gcc/x86_64-linux-gnu/8/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-class-memaccess -Wno-comment -std=c++11 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-7~svn338205/build-llvm/lib/Target/PowerPC -ferror-limit 19 -fmessage-length 0 -fvisibility-inlines-hidden -fobjc-runtime=gcc -fdiagnostics-show-option -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -o /tmp/scan-build-2018-07-29-043837-17923-1 -x c++ /build/llvm-toolchain-snapshot-7~svn338205/lib/Target/PowerPC/PPCInstrInfo.cpp -faddrsig
1//===-- PPCInstrInfo.cpp - PowerPC Instruction Information ----------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the PowerPC implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "PPCInstrInfo.h"
15#include "MCTargetDesc/PPCPredicates.h"
16#include "PPC.h"
17#include "PPCHazardRecognizers.h"
18#include "PPCInstrBuilder.h"
19#include "PPCMachineFunctionInfo.h"
20#include "PPCTargetMachine.h"
21#include "llvm/ADT/STLExtras.h"
22#include "llvm/ADT/Statistic.h"
23#include "llvm/CodeGen/LiveIntervals.h"
24#include "llvm/CodeGen/MachineFrameInfo.h"
25#include "llvm/CodeGen/MachineFunctionPass.h"
26#include "llvm/CodeGen/MachineInstrBuilder.h"
27#include "llvm/CodeGen/MachineMemOperand.h"
28#include "llvm/CodeGen/MachineRegisterInfo.h"
29#include "llvm/CodeGen/PseudoSourceValue.h"
30#include "llvm/CodeGen/ScheduleDAG.h"
31#include "llvm/CodeGen/SlotIndexes.h"
32#include "llvm/CodeGen/StackMaps.h"
33#include "llvm/MC/MCAsmInfo.h"
34#include "llvm/MC/MCInst.h"
35#include "llvm/Support/CommandLine.h"
36#include "llvm/Support/Debug.h"
37#include "llvm/Support/ErrorHandling.h"
38#include "llvm/Support/TargetRegistry.h"
39#include "llvm/Support/raw_ostream.h"
40
41using namespace llvm;
42
43#define DEBUG_TYPE"ppc-instr-info" "ppc-instr-info"
44
45#define GET_INSTRMAP_INFO
46#define GET_INSTRINFO_CTOR_DTOR
47#include "PPCGenInstrInfo.inc"
48
49STATISTIC(NumStoreSPILLVSRRCAsVec,static llvm::Statistic NumStoreSPILLVSRRCAsVec = {"ppc-instr-info"
, "NumStoreSPILLVSRRCAsVec", "Number of spillvsrrc spilled to stack as vec"
, {0}, {false}}
50 "Number of spillvsrrc spilled to stack as vec")static llvm::Statistic NumStoreSPILLVSRRCAsVec = {"ppc-instr-info"
, "NumStoreSPILLVSRRCAsVec", "Number of spillvsrrc spilled to stack as vec"
, {0}, {false}}
;
51STATISTIC(NumStoreSPILLVSRRCAsGpr,static llvm::Statistic NumStoreSPILLVSRRCAsGpr = {"ppc-instr-info"
, "NumStoreSPILLVSRRCAsGpr", "Number of spillvsrrc spilled to stack as gpr"
, {0}, {false}}
52 "Number of spillvsrrc spilled to stack as gpr")static llvm::Statistic NumStoreSPILLVSRRCAsGpr = {"ppc-instr-info"
, "NumStoreSPILLVSRRCAsGpr", "Number of spillvsrrc spilled to stack as gpr"
, {0}, {false}}
;
53STATISTIC(NumGPRtoVSRSpill, "Number of gpr spills to spillvsrrc")static llvm::Statistic NumGPRtoVSRSpill = {"ppc-instr-info", "NumGPRtoVSRSpill"
, "Number of gpr spills to spillvsrrc", {0}, {false}}
;
54STATISTIC(CmpIselsConverted,static llvm::Statistic CmpIselsConverted = {"ppc-instr-info",
"CmpIselsConverted", "Number of ISELs that depend on comparison of constants converted"
, {0}, {false}}
55 "Number of ISELs that depend on comparison of constants converted")static llvm::Statistic CmpIselsConverted = {"ppc-instr-info",
"CmpIselsConverted", "Number of ISELs that depend on comparison of constants converted"
, {0}, {false}}
;
56STATISTIC(MissedConvertibleImmediateInstrs,static llvm::Statistic MissedConvertibleImmediateInstrs = {"ppc-instr-info"
, "MissedConvertibleImmediateInstrs", "Number of compare-immediate instructions fed by constants"
, {0}, {false}}
57 "Number of compare-immediate instructions fed by constants")static llvm::Statistic MissedConvertibleImmediateInstrs = {"ppc-instr-info"
, "MissedConvertibleImmediateInstrs", "Number of compare-immediate instructions fed by constants"
, {0}, {false}}
;
58STATISTIC(NumRcRotatesConvertedToRcAnd,static llvm::Statistic NumRcRotatesConvertedToRcAnd = {"ppc-instr-info"
, "NumRcRotatesConvertedToRcAnd", "Number of record-form rotates converted to record-form andi"
, {0}, {false}}
59 "Number of record-form rotates converted to record-form andi")static llvm::Statistic NumRcRotatesConvertedToRcAnd = {"ppc-instr-info"
, "NumRcRotatesConvertedToRcAnd", "Number of record-form rotates converted to record-form andi"
, {0}, {false}}
;
60
61static cl::
62opt<bool> DisableCTRLoopAnal("disable-ppc-ctrloop-analysis", cl::Hidden,
63 cl::desc("Disable analysis for CTR loops"));
64
65static cl::opt<bool> DisableCmpOpt("disable-ppc-cmp-opt",
66cl::desc("Disable compare instruction optimization"), cl::Hidden);
67
68static cl::opt<bool> VSXSelfCopyCrash("crash-on-ppc-vsx-self-copy",
69cl::desc("Causes the backend to crash instead of generating a nop VSX copy"),
70cl::Hidden);
71
72static cl::opt<bool>
73UseOldLatencyCalc("ppc-old-latency-calc", cl::Hidden,
74 cl::desc("Use the old (incorrect) instruction latency calculation"));
75
76// Index into the OpcodesForSpill array.
77enum SpillOpcodeKey {
78 SOK_Int4Spill,
79 SOK_Int8Spill,
80 SOK_Float8Spill,
81 SOK_Float4Spill,
82 SOK_CRSpill,
83 SOK_CRBitSpill,
84 SOK_VRVectorSpill,
85 SOK_VSXVectorSpill,
86 SOK_VectorFloat8Spill,
87 SOK_VectorFloat4Spill,
88 SOK_VRSaveSpill,
89 SOK_QuadFloat8Spill,
90 SOK_QuadFloat4Spill,
91 SOK_QuadBitSpill,
92 SOK_SpillToVSR,
93 SOK_SPESpill,
94 SOK_SPE4Spill,
95 SOK_LastOpcodeSpill // This must be last on the enum.
96};
97
98// Pin the vtable to this file.
99void PPCInstrInfo::anchor() {}
100
101PPCInstrInfo::PPCInstrInfo(PPCSubtarget &STI)
102 : PPCGenInstrInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP,
103 /* CatchRetOpcode */ -1,
104 STI.isPPC64() ? PPC::BLR8 : PPC::BLR),
105 Subtarget(STI), RI(STI.getTargetMachine()) {}
106
107/// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
108/// this target when scheduling the DAG.
109ScheduleHazardRecognizer *
110PPCInstrInfo::CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,
111 const ScheduleDAG *DAG) const {
112 unsigned Directive =
113 static_cast<const PPCSubtarget *>(STI)->getDarwinDirective();
114 if (Directive == PPC::DIR_440 || Directive == PPC::DIR_A2 ||
115 Directive == PPC::DIR_E500mc || Directive == PPC::DIR_E5500) {
116 const InstrItineraryData *II =
117 static_cast<const PPCSubtarget *>(STI)->getInstrItineraryData();
118 return new ScoreboardHazardRecognizer(II, DAG);
119 }
120
121 return TargetInstrInfo::CreateTargetHazardRecognizer(STI, DAG);
122}
123
124/// CreateTargetPostRAHazardRecognizer - Return the postRA hazard recognizer
125/// to use for this target when scheduling the DAG.
126ScheduleHazardRecognizer *
127PPCInstrInfo::CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
128 const ScheduleDAG *DAG) const {
129 unsigned Directive =
130 DAG->MF.getSubtarget<PPCSubtarget>().getDarwinDirective();
131
132 // FIXME: Leaving this as-is until we have POWER9 scheduling info
133 if (Directive == PPC::DIR_PWR7 || Directive == PPC::DIR_PWR8)
134 return new PPCDispatchGroupSBHazardRecognizer(II, DAG);
135
136 // Most subtargets use a PPC970 recognizer.
137 if (Directive != PPC::DIR_440 && Directive != PPC::DIR_A2 &&
138 Directive != PPC::DIR_E500mc && Directive != PPC::DIR_E5500) {
139 assert(DAG->TII && "No InstrInfo?")(static_cast <bool> (DAG->TII && "No InstrInfo?"
) ? void (0) : __assert_fail ("DAG->TII && \"No InstrInfo?\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 139, __extension__ __PRETTY_FUNCTION__))
;
140
141 return new PPCHazardRecognizer970(*DAG);
142 }
143
144 return new ScoreboardHazardRecognizer(II, DAG);
145}
146
147unsigned PPCInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
148 const MachineInstr &MI,
149 unsigned *PredCost) const {
150 if (!ItinData || UseOldLatencyCalc)
151 return PPCGenInstrInfo::getInstrLatency(ItinData, MI, PredCost);
152
153 // The default implementation of getInstrLatency calls getStageLatency, but
154 // getStageLatency does not do the right thing for us. While we have
155 // itinerary, most cores are fully pipelined, and so the itineraries only
156 // express the first part of the pipeline, not every stage. Instead, we need
157 // to use the listed output operand cycle number (using operand 0 here, which
158 // is an output).
159
160 unsigned Latency = 1;
161 unsigned DefClass = MI.getDesc().getSchedClass();
162 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
163 const MachineOperand &MO = MI.getOperand(i);
164 if (!MO.isReg() || !MO.isDef() || MO.isImplicit())
165 continue;
166
167 int Cycle = ItinData->getOperandCycle(DefClass, i);
168 if (Cycle < 0)
169 continue;
170
171 Latency = std::max(Latency, (unsigned) Cycle);
172 }
173
174 return Latency;
175}
176
177int PPCInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
178 const MachineInstr &DefMI, unsigned DefIdx,
179 const MachineInstr &UseMI,
180 unsigned UseIdx) const {
181 int Latency = PPCGenInstrInfo::getOperandLatency(ItinData, DefMI, DefIdx,
182 UseMI, UseIdx);
183
184 if (!DefMI.getParent())
185 return Latency;
186
187 const MachineOperand &DefMO = DefMI.getOperand(DefIdx);
188 unsigned Reg = DefMO.getReg();
189
190 bool IsRegCR;
191 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
192 const MachineRegisterInfo *MRI =
193 &DefMI.getParent()->getParent()->getRegInfo();
194 IsRegCR = MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRRCRegClass) ||
195 MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRBITRCRegClass);
196 } else {
197 IsRegCR = PPC::CRRCRegClass.contains(Reg) ||
198 PPC::CRBITRCRegClass.contains(Reg);
199 }
200
201 if (UseMI.isBranch() && IsRegCR) {
202 if (Latency < 0)
203 Latency = getInstrLatency(ItinData, DefMI);
204
205 // On some cores, there is an additional delay between writing to a condition
206 // register, and using it from a branch.
207 unsigned Directive = Subtarget.getDarwinDirective();
208 switch (Directive) {
209 default: break;
210 case PPC::DIR_7400:
211 case PPC::DIR_750:
212 case PPC::DIR_970:
213 case PPC::DIR_E5500:
214 case PPC::DIR_PWR4:
215 case PPC::DIR_PWR5:
216 case PPC::DIR_PWR5X:
217 case PPC::DIR_PWR6:
218 case PPC::DIR_PWR6X:
219 case PPC::DIR_PWR7:
220 case PPC::DIR_PWR8:
221 // FIXME: Is this needed for POWER9?
222 Latency += 2;
223 break;
224 }
225 }
226
227 return Latency;
228}
229
230// This function does not list all associative and commutative operations, but
231// only those worth feeding through the machine combiner in an attempt to
232// reduce the critical path. Mostly, this means floating-point operations,
233// because they have high latencies (compared to other operations, such and
234// and/or, which are also associative and commutative, but have low latencies).
235bool PPCInstrInfo::isAssociativeAndCommutative(const MachineInstr &Inst) const {
236 switch (Inst.getOpcode()) {
237 // FP Add:
238 case PPC::FADD:
239 case PPC::FADDS:
240 // FP Multiply:
241 case PPC::FMUL:
242 case PPC::FMULS:
243 // Altivec Add:
244 case PPC::VADDFP:
245 // VSX Add:
246 case PPC::XSADDDP:
247 case PPC::XVADDDP:
248 case PPC::XVADDSP:
249 case PPC::XSADDSP:
250 // VSX Multiply:
251 case PPC::XSMULDP:
252 case PPC::XVMULDP:
253 case PPC::XVMULSP:
254 case PPC::XSMULSP:
255 // QPX Add:
256 case PPC::QVFADD:
257 case PPC::QVFADDS:
258 case PPC::QVFADDSs:
259 // QPX Multiply:
260 case PPC::QVFMUL:
261 case PPC::QVFMULS:
262 case PPC::QVFMULSs:
263 return true;
264 default:
265 return false;
266 }
267}
268
269bool PPCInstrInfo::getMachineCombinerPatterns(
270 MachineInstr &Root,
271 SmallVectorImpl<MachineCombinerPattern> &Patterns) const {
272 // Using the machine combiner in this way is potentially expensive, so
273 // restrict to when aggressive optimizations are desired.
274 if (Subtarget.getTargetMachine().getOptLevel() != CodeGenOpt::Aggressive)
275 return false;
276
277 // FP reassociation is only legal when we don't need strict IEEE semantics.
278 if (!Root.getParent()->getParent()->getTarget().Options.UnsafeFPMath)
279 return false;
280
281 return TargetInstrInfo::getMachineCombinerPatterns(Root, Patterns);
282}
283
284// Detect 32 -> 64-bit extensions where we may reuse the low sub-register.
285bool PPCInstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
286 unsigned &SrcReg, unsigned &DstReg,
287 unsigned &SubIdx) const {
288 switch (MI.getOpcode()) {
289 default: return false;
290 case PPC::EXTSW:
291 case PPC::EXTSW_32:
292 case PPC::EXTSW_32_64:
293 SrcReg = MI.getOperand(1).getReg();
294 DstReg = MI.getOperand(0).getReg();
295 SubIdx = PPC::sub_32;
296 return true;
297 }
298}
299
300unsigned PPCInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
301 int &FrameIndex) const {
302 unsigned Opcode = MI.getOpcode();
303 const unsigned *OpcodesForSpill = getLoadOpcodesForSpillArray();
304 const unsigned *End = OpcodesForSpill + SOK_LastOpcodeSpill;
305
306 if (End != std::find(OpcodesForSpill, End, Opcode)) {
307 // Check for the operands added by addFrameReference (the immediate is the
308 // offset which defaults to 0).
309 if (MI.getOperand(1).isImm() && !MI.getOperand(1).getImm() &&
310 MI.getOperand(2).isFI()) {
311 FrameIndex = MI.getOperand(2).getIndex();
312 return MI.getOperand(0).getReg();
313 }
314 }
315 return 0;
316}
317
318// For opcodes with the ReMaterializable flag set, this function is called to
319// verify the instruction is really rematable.
320bool PPCInstrInfo::isReallyTriviallyReMaterializable(const MachineInstr &MI,
321 AliasAnalysis *AA) const {
322 switch (MI.getOpcode()) {
323 default:
324 // This function should only be called for opcodes with the ReMaterializable
325 // flag set.
326 llvm_unreachable("Unknown rematerializable operation!")::llvm::llvm_unreachable_internal("Unknown rematerializable operation!"
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 326)
;
327 break;
328 case PPC::LI:
329 case PPC::LI8:
330 case PPC::LIS:
331 case PPC::LIS8:
332 case PPC::QVGPCI:
333 case PPC::ADDIStocHA:
334 case PPC::ADDItocL:
335 case PPC::LOAD_STACK_GUARD:
336 return true;
337 }
338 return false;
339}
340
341unsigned PPCInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
342 int &FrameIndex) const {
343 unsigned Opcode = MI.getOpcode();
344 const unsigned *OpcodesForSpill = getStoreOpcodesForSpillArray();
345 const unsigned *End = OpcodesForSpill + SOK_LastOpcodeSpill;
346
347 if (End != std::find(OpcodesForSpill, End, Opcode)) {
348 if (MI.getOperand(1).isImm() && !MI.getOperand(1).getImm() &&
349 MI.getOperand(2).isFI()) {
350 FrameIndex = MI.getOperand(2).getIndex();
351 return MI.getOperand(0).getReg();
352 }
353 }
354 return 0;
355}
356
357MachineInstr *PPCInstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI,
358 unsigned OpIdx1,
359 unsigned OpIdx2) const {
360 MachineFunction &MF = *MI.getParent()->getParent();
361
362 // Normal instructions can be commuted the obvious way.
363 if (MI.getOpcode() != PPC::RLWIMI && MI.getOpcode() != PPC::RLWIMIo)
364 return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
365 // Note that RLWIMI can be commuted as a 32-bit instruction, but not as a
366 // 64-bit instruction (so we don't handle PPC::RLWIMI8 here), because
367 // changing the relative order of the mask operands might change what happens
368 // to the high-bits of the mask (and, thus, the result).
369
370 // Cannot commute if it has a non-zero rotate count.
371 if (MI.getOperand(3).getImm() != 0)
372 return nullptr;
373
374 // If we have a zero rotate count, we have:
375 // M = mask(MB,ME)
376 // Op0 = (Op1 & ~M) | (Op2 & M)
377 // Change this to:
378 // M = mask((ME+1)&31, (MB-1)&31)
379 // Op0 = (Op2 & ~M) | (Op1 & M)
380
381 // Swap op1/op2
382 assert(((OpIdx1 == 1 && OpIdx2 == 2) || (OpIdx1 == 2 && OpIdx2 == 1)) &&(static_cast <bool> (((OpIdx1 == 1 && OpIdx2 ==
2) || (OpIdx1 == 2 && OpIdx2 == 1)) && "Only the operands 1 and 2 can be swapped in RLSIMI/RLWIMIo."
) ? void (0) : __assert_fail ("((OpIdx1 == 1 && OpIdx2 == 2) || (OpIdx1 == 2 && OpIdx2 == 1)) && \"Only the operands 1 and 2 can be swapped in RLSIMI/RLWIMIo.\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 383, __extension__ __PRETTY_FUNCTION__))
383 "Only the operands 1 and 2 can be swapped in RLSIMI/RLWIMIo.")(static_cast <bool> (((OpIdx1 == 1 && OpIdx2 ==
2) || (OpIdx1 == 2 && OpIdx2 == 1)) && "Only the operands 1 and 2 can be swapped in RLSIMI/RLWIMIo."
) ? void (0) : __assert_fail ("((OpIdx1 == 1 && OpIdx2 == 2) || (OpIdx1 == 2 && OpIdx2 == 1)) && \"Only the operands 1 and 2 can be swapped in RLSIMI/RLWIMIo.\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 383, __extension__ __PRETTY_FUNCTION__))
;
384 unsigned Reg0 = MI.getOperand(0).getReg();
385 unsigned Reg1 = MI.getOperand(1).getReg();
386 unsigned Reg2 = MI.getOperand(2).getReg();
387 unsigned SubReg1 = MI.getOperand(1).getSubReg();
388 unsigned SubReg2 = MI.getOperand(2).getSubReg();
389 bool Reg1IsKill = MI.getOperand(1).isKill();
390 bool Reg2IsKill = MI.getOperand(2).isKill();
391 bool ChangeReg0 = false;
392 // If machine instrs are no longer in two-address forms, update
393 // destination register as well.
394 if (Reg0 == Reg1) {
395 // Must be two address instruction!
396 assert(MI.getDesc().getOperandConstraint(0, MCOI::TIED_TO) &&(static_cast <bool> (MI.getDesc().getOperandConstraint(
0, MCOI::TIED_TO) && "Expecting a two-address instruction!"
) ? void (0) : __assert_fail ("MI.getDesc().getOperandConstraint(0, MCOI::TIED_TO) && \"Expecting a two-address instruction!\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 397, __extension__ __PRETTY_FUNCTION__))
397 "Expecting a two-address instruction!")(static_cast <bool> (MI.getDesc().getOperandConstraint(
0, MCOI::TIED_TO) && "Expecting a two-address instruction!"
) ? void (0) : __assert_fail ("MI.getDesc().getOperandConstraint(0, MCOI::TIED_TO) && \"Expecting a two-address instruction!\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 397, __extension__ __PRETTY_FUNCTION__))
;
398 assert(MI.getOperand(0).getSubReg() == SubReg1 && "Tied subreg mismatch")(static_cast <bool> (MI.getOperand(0).getSubReg() == SubReg1
&& "Tied subreg mismatch") ? void (0) : __assert_fail
("MI.getOperand(0).getSubReg() == SubReg1 && \"Tied subreg mismatch\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 398, __extension__ __PRETTY_FUNCTION__))
;
399 Reg2IsKill = false;
400 ChangeReg0 = true;
401 }
402
403 // Masks.
404 unsigned MB = MI.getOperand(4).getImm();
405 unsigned ME = MI.getOperand(5).getImm();
406
407 // We can't commute a trivial mask (there is no way to represent an all-zero
408 // mask).
409 if (MB == 0 && ME == 31)
410 return nullptr;
411
412 if (NewMI) {
413 // Create a new instruction.
414 unsigned Reg0 = ChangeReg0 ? Reg2 : MI.getOperand(0).getReg();
415 bool Reg0IsDead = MI.getOperand(0).isDead();
416 return BuildMI(MF, MI.getDebugLoc(), MI.getDesc())
417 .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead))
418 .addReg(Reg2, getKillRegState(Reg2IsKill))
419 .addReg(Reg1, getKillRegState(Reg1IsKill))
420 .addImm((ME + 1) & 31)
421 .addImm((MB - 1) & 31);
422 }
423
424 if (ChangeReg0) {
425 MI.getOperand(0).setReg(Reg2);
426 MI.getOperand(0).setSubReg(SubReg2);
427 }
428 MI.getOperand(2).setReg(Reg1);
429 MI.getOperand(1).setReg(Reg2);
430 MI.getOperand(2).setSubReg(SubReg1);
431 MI.getOperand(1).setSubReg(SubReg2);
432 MI.getOperand(2).setIsKill(Reg1IsKill);
433 MI.getOperand(1).setIsKill(Reg2IsKill);
434
435 // Swap the mask around.
436 MI.getOperand(4).setImm((ME + 1) & 31);
437 MI.getOperand(5).setImm((MB - 1) & 31);
438 return &MI;
439}
440
441bool PPCInstrInfo::findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1,
442 unsigned &SrcOpIdx2) const {
443 // For VSX A-Type FMA instructions, it is the first two operands that can be
444 // commuted, however, because the non-encoded tied input operand is listed
445 // first, the operands to swap are actually the second and third.
446
447 int AltOpc = PPC::getAltVSXFMAOpcode(MI.getOpcode());
448 if (AltOpc == -1)
449 return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
450
451 // The commutable operand indices are 2 and 3. Return them in SrcOpIdx1
452 // and SrcOpIdx2.
453 return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 2, 3);
454}
455
456void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB,
457 MachineBasicBlock::iterator MI) const {
458 // This function is used for scheduling, and the nop wanted here is the type
459 // that terminates dispatch groups on the POWER cores.
460 unsigned Directive = Subtarget.getDarwinDirective();
461 unsigned Opcode;
462 switch (Directive) {
463 default: Opcode = PPC::NOP; break;
464 case PPC::DIR_PWR6: Opcode = PPC::NOP_GT_PWR6; break;
465 case PPC::DIR_PWR7: Opcode = PPC::NOP_GT_PWR7; break;
466 case PPC::DIR_PWR8: Opcode = PPC::NOP_GT_PWR7; break; /* FIXME: Update when P8 InstrScheduling model is ready */
467 // FIXME: Update when POWER9 scheduling model is ready.
468 case PPC::DIR_PWR9: Opcode = PPC::NOP_GT_PWR7; break;
469 }
470
471 DebugLoc DL;
472 BuildMI(MBB, MI, DL, get(Opcode));
473}
474
475/// Return the noop instruction to use for a noop.
476void PPCInstrInfo::getNoop(MCInst &NopInst) const {
477 NopInst.setOpcode(PPC::NOP);
478}
479
480// Branch analysis.
481// Note: If the condition register is set to CTR or CTR8 then this is a
482// BDNZ (imm == 1) or BDZ (imm == 0) branch.
483bool PPCInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
484 MachineBasicBlock *&TBB,
485 MachineBasicBlock *&FBB,
486 SmallVectorImpl<MachineOperand> &Cond,
487 bool AllowModify) const {
488 bool isPPC64 = Subtarget.isPPC64();
489
490 // If the block has no terminators, it just falls into the block after it.
491 MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
492 if (I == MBB.end())
493 return false;
494
495 if (!isUnpredicatedTerminator(*I))
496 return false;
497
498 if (AllowModify) {
499 // If the BB ends with an unconditional branch to the fallthrough BB,
500 // we eliminate the branch instruction.
501 if (I->getOpcode() == PPC::B &&
502 MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
503 I->eraseFromParent();
504
505 // We update iterator after deleting the last branch.
506 I = MBB.getLastNonDebugInstr();
507 if (I == MBB.end() || !isUnpredicatedTerminator(*I))
508 return false;
509 }
510 }
511
512 // Get the last instruction in the block.
513 MachineInstr &LastInst = *I;
514
515 // If there is only one terminator instruction, process it.
516 if (I == MBB.begin() || !isUnpredicatedTerminator(*--I)) {
517 if (LastInst.getOpcode() == PPC::B) {
518 if (!LastInst.getOperand(0).isMBB())
519 return true;
520 TBB = LastInst.getOperand(0).getMBB();
521 return false;
522 } else if (LastInst.getOpcode() == PPC::BCC) {
523 if (!LastInst.getOperand(2).isMBB())
524 return true;
525 // Block ends with fall-through condbranch.
526 TBB = LastInst.getOperand(2).getMBB();
527 Cond.push_back(LastInst.getOperand(0));
528 Cond.push_back(LastInst.getOperand(1));
529 return false;
530 } else if (LastInst.getOpcode() == PPC::BC) {
531 if (!LastInst.getOperand(1).isMBB())
532 return true;
533 // Block ends with fall-through condbranch.
534 TBB = LastInst.getOperand(1).getMBB();
535 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET));
536 Cond.push_back(LastInst.getOperand(0));
537 return false;
538 } else if (LastInst.getOpcode() == PPC::BCn) {
539 if (!LastInst.getOperand(1).isMBB())
540 return true;
541 // Block ends with fall-through condbranch.
542 TBB = LastInst.getOperand(1).getMBB();
543 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_UNSET));
544 Cond.push_back(LastInst.getOperand(0));
545 return false;
546 } else if (LastInst.getOpcode() == PPC::BDNZ8 ||
547 LastInst.getOpcode() == PPC::BDNZ) {
548 if (!LastInst.getOperand(0).isMBB())
549 return true;
550 if (DisableCTRLoopAnal)
551 return true;
552 TBB = LastInst.getOperand(0).getMBB();
553 Cond.push_back(MachineOperand::CreateImm(1));
554 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
555 true));
556 return false;
557 } else if (LastInst.getOpcode() == PPC::BDZ8 ||
558 LastInst.getOpcode() == PPC::BDZ) {
559 if (!LastInst.getOperand(0).isMBB())
560 return true;
561 if (DisableCTRLoopAnal)
562 return true;
563 TBB = LastInst.getOperand(0).getMBB();
564 Cond.push_back(MachineOperand::CreateImm(0));
565 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
566 true));
567 return false;
568 }
569
570 // Otherwise, don't know what this is.
571 return true;
572 }
573
574 // Get the instruction before it if it's a terminator.
575 MachineInstr &SecondLastInst = *I;
576
577 // If there are three terminators, we don't know what sort of block this is.
578 if (I != MBB.begin() && isUnpredicatedTerminator(*--I))
579 return true;
580
581 // If the block ends with PPC::B and PPC:BCC, handle it.
582 if (SecondLastInst.getOpcode() == PPC::BCC &&
583 LastInst.getOpcode() == PPC::B) {
584 if (!SecondLastInst.getOperand(2).isMBB() ||
585 !LastInst.getOperand(0).isMBB())
586 return true;
587 TBB = SecondLastInst.getOperand(2).getMBB();
588 Cond.push_back(SecondLastInst.getOperand(0));
589 Cond.push_back(SecondLastInst.getOperand(1));
590 FBB = LastInst.getOperand(0).getMBB();
591 return false;
592 } else if (SecondLastInst.getOpcode() == PPC::BC &&
593 LastInst.getOpcode() == PPC::B) {
594 if (!SecondLastInst.getOperand(1).isMBB() ||
595 !LastInst.getOperand(0).isMBB())
596 return true;
597 TBB = SecondLastInst.getOperand(1).getMBB();
598 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET));
599 Cond.push_back(SecondLastInst.getOperand(0));
600 FBB = LastInst.getOperand(0).getMBB();
601 return false;
602 } else if (SecondLastInst.getOpcode() == PPC::BCn &&
603 LastInst.getOpcode() == PPC::B) {
604 if (!SecondLastInst.getOperand(1).isMBB() ||
605 !LastInst.getOperand(0).isMBB())
606 return true;
607 TBB = SecondLastInst.getOperand(1).getMBB();
608 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_UNSET));
609 Cond.push_back(SecondLastInst.getOperand(0));
610 FBB = LastInst.getOperand(0).getMBB();
611 return false;
612 } else if ((SecondLastInst.getOpcode() == PPC::BDNZ8 ||
613 SecondLastInst.getOpcode() == PPC::BDNZ) &&
614 LastInst.getOpcode() == PPC::B) {
615 if (!SecondLastInst.getOperand(0).isMBB() ||
616 !LastInst.getOperand(0).isMBB())
617 return true;
618 if (DisableCTRLoopAnal)
619 return true;
620 TBB = SecondLastInst.getOperand(0).getMBB();
621 Cond.push_back(MachineOperand::CreateImm(1));
622 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
623 true));
624 FBB = LastInst.getOperand(0).getMBB();
625 return false;
626 } else if ((SecondLastInst.getOpcode() == PPC::BDZ8 ||
627 SecondLastInst.getOpcode() == PPC::BDZ) &&
628 LastInst.getOpcode() == PPC::B) {
629 if (!SecondLastInst.getOperand(0).isMBB() ||
630 !LastInst.getOperand(0).isMBB())
631 return true;
632 if (DisableCTRLoopAnal)
633 return true;
634 TBB = SecondLastInst.getOperand(0).getMBB();
635 Cond.push_back(MachineOperand::CreateImm(0));
636 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
637 true));
638 FBB = LastInst.getOperand(0).getMBB();
639 return false;
640 }
641
642 // If the block ends with two PPC:Bs, handle it. The second one is not
643 // executed, so remove it.
644 if (SecondLastInst.getOpcode() == PPC::B && LastInst.getOpcode() == PPC::B) {
645 if (!SecondLastInst.getOperand(0).isMBB())
646 return true;
647 TBB = SecondLastInst.getOperand(0).getMBB();
648 I = LastInst;
649 if (AllowModify)
650 I->eraseFromParent();
651 return false;
652 }
653
654 // Otherwise, can't handle this.
655 return true;
656}
657
658unsigned PPCInstrInfo::removeBranch(MachineBasicBlock &MBB,
659 int *BytesRemoved) const {
660 assert(!BytesRemoved && "code size not handled")(static_cast <bool> (!BytesRemoved && "code size not handled"
) ? void (0) : __assert_fail ("!BytesRemoved && \"code size not handled\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 660, __extension__ __PRETTY_FUNCTION__))
;
661
662 MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
663 if (I == MBB.end())
664 return 0;
665
666 if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC &&
667 I->getOpcode() != PPC::BC && I->getOpcode() != PPC::BCn &&
668 I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ &&
669 I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ)
670 return 0;
671
672 // Remove the branch.
673 I->eraseFromParent();
674
675 I = MBB.end();
676
677 if (I == MBB.begin()) return 1;
678 --I;
679 if (I->getOpcode() != PPC::BCC &&
680 I->getOpcode() != PPC::BC && I->getOpcode() != PPC::BCn &&
681 I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ &&
682 I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ)
683 return 1;
684
685 // Remove the branch.
686 I->eraseFromParent();
687 return 2;
688}
689
690unsigned PPCInstrInfo::insertBranch(MachineBasicBlock &MBB,
691 MachineBasicBlock *TBB,
692 MachineBasicBlock *FBB,
693 ArrayRef<MachineOperand> Cond,
694 const DebugLoc &DL,
695 int *BytesAdded) const {
696 // Shouldn't be a fall through.
697 assert(TBB && "insertBranch must not be told to insert a fallthrough")(static_cast <bool> (TBB && "insertBranch must not be told to insert a fallthrough"
) ? void (0) : __assert_fail ("TBB && \"insertBranch must not be told to insert a fallthrough\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 697, __extension__ __PRETTY_FUNCTION__))
;
698 assert((Cond.size() == 2 || Cond.size() == 0) &&(static_cast <bool> ((Cond.size() == 2 || Cond.size() ==
0) && "PPC branch conditions have two components!") ?
void (0) : __assert_fail ("(Cond.size() == 2 || Cond.size() == 0) && \"PPC branch conditions have two components!\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 699, __extension__ __PRETTY_FUNCTION__))
699 "PPC branch conditions have two components!")(static_cast <bool> ((Cond.size() == 2 || Cond.size() ==
0) && "PPC branch conditions have two components!") ?
void (0) : __assert_fail ("(Cond.size() == 2 || Cond.size() == 0) && \"PPC branch conditions have two components!\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 699, __extension__ __PRETTY_FUNCTION__))
;
700 assert(!BytesAdded && "code size not handled")(static_cast <bool> (!BytesAdded && "code size not handled"
) ? void (0) : __assert_fail ("!BytesAdded && \"code size not handled\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 700, __extension__ __PRETTY_FUNCTION__))
;
701
702 bool isPPC64 = Subtarget.isPPC64();
703
704 // One-way branch.
705 if (!FBB) {
706 if (Cond.empty()) // Unconditional branch
707 BuildMI(&MBB, DL, get(PPC::B)).addMBB(TBB);
708 else if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
709 BuildMI(&MBB, DL, get(Cond[0].getImm() ?
710 (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
711 (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB);
712 else if (Cond[0].getImm() == PPC::PRED_BIT_SET)
713 BuildMI(&MBB, DL, get(PPC::BC)).add(Cond[1]).addMBB(TBB);
714 else if (Cond[0].getImm() == PPC::PRED_BIT_UNSET)
715 BuildMI(&MBB, DL, get(PPC::BCn)).add(Cond[1]).addMBB(TBB);
716 else // Conditional branch
717 BuildMI(&MBB, DL, get(PPC::BCC))
718 .addImm(Cond[0].getImm())
719 .add(Cond[1])
720 .addMBB(TBB);
721 return 1;
722 }
723
724 // Two-way Conditional Branch.
725 if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
726 BuildMI(&MBB, DL, get(Cond[0].getImm() ?
727 (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
728 (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB);
729 else if (Cond[0].getImm() == PPC::PRED_BIT_SET)
730 BuildMI(&MBB, DL, get(PPC::BC)).add(Cond[1]).addMBB(TBB);
731 else if (Cond[0].getImm() == PPC::PRED_BIT_UNSET)
732 BuildMI(&MBB, DL, get(PPC::BCn)).add(Cond[1]).addMBB(TBB);
733 else
734 BuildMI(&MBB, DL, get(PPC::BCC))
735 .addImm(Cond[0].getImm())
736 .add(Cond[1])
737 .addMBB(TBB);
738 BuildMI(&MBB, DL, get(PPC::B)).addMBB(FBB);
739 return 2;
740}
741
742// Select analysis.
743bool PPCInstrInfo::canInsertSelect(const MachineBasicBlock &MBB,
744 ArrayRef<MachineOperand> Cond,
745 unsigned TrueReg, unsigned FalseReg,
746 int &CondCycles, int &TrueCycles, int &FalseCycles) const {
747 if (Cond.size() != 2)
748 return false;
749
750 // If this is really a bdnz-like condition, then it cannot be turned into a
751 // select.
752 if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
753 return false;
754
755 // Check register classes.
756 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
757 const TargetRegisterClass *RC =
758 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
759 if (!RC)
760 return false;
761
762 // isel is for regular integer GPRs only.
763 if (!PPC::GPRCRegClass.hasSubClassEq(RC) &&
764 !PPC::GPRC_NOR0RegClass.hasSubClassEq(RC) &&
765 !PPC::G8RCRegClass.hasSubClassEq(RC) &&
766 !PPC::G8RC_NOX0RegClass.hasSubClassEq(RC))
767 return false;
768
769 // FIXME: These numbers are for the A2, how well they work for other cores is
770 // an open question. On the A2, the isel instruction has a 2-cycle latency
771 // but single-cycle throughput. These numbers are used in combination with
772 // the MispredictPenalty setting from the active SchedMachineModel.
773 CondCycles = 1;
774 TrueCycles = 1;
775 FalseCycles = 1;
776
777 return true;
778}
779
780void PPCInstrInfo::insertSelect(MachineBasicBlock &MBB,
781 MachineBasicBlock::iterator MI,
782 const DebugLoc &dl, unsigned DestReg,
783 ArrayRef<MachineOperand> Cond, unsigned TrueReg,
784 unsigned FalseReg) const {
785 assert(Cond.size() == 2 &&(static_cast <bool> (Cond.size() == 2 && "PPC branch conditions have two components!"
) ? void (0) : __assert_fail ("Cond.size() == 2 && \"PPC branch conditions have two components!\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 786, __extension__ __PRETTY_FUNCTION__))
786 "PPC branch conditions have two components!")(static_cast <bool> (Cond.size() == 2 && "PPC branch conditions have two components!"
) ? void (0) : __assert_fail ("Cond.size() == 2 && \"PPC branch conditions have two components!\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 786, __extension__ __PRETTY_FUNCTION__))
;
787
788 // Get the register classes.
789 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
790 const TargetRegisterClass *RC =
791 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
792 assert(RC && "TrueReg and FalseReg must have overlapping register classes")(static_cast <bool> (RC && "TrueReg and FalseReg must have overlapping register classes"
) ? void (0) : __assert_fail ("RC && \"TrueReg and FalseReg must have overlapping register classes\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 792, __extension__ __PRETTY_FUNCTION__))
;
793
794 bool Is64Bit = PPC::G8RCRegClass.hasSubClassEq(RC) ||
795 PPC::G8RC_NOX0RegClass.hasSubClassEq(RC);
796 assert((Is64Bit ||(static_cast <bool> ((Is64Bit || PPC::GPRCRegClass.hasSubClassEq
(RC) || PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) && "isel is for regular integer GPRs only"
) ? void (0) : __assert_fail ("(Is64Bit || PPC::GPRCRegClass.hasSubClassEq(RC) || PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) && \"isel is for regular integer GPRs only\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 799, __extension__ __PRETTY_FUNCTION__))
797 PPC::GPRCRegClass.hasSubClassEq(RC) ||(static_cast <bool> ((Is64Bit || PPC::GPRCRegClass.hasSubClassEq
(RC) || PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) && "isel is for regular integer GPRs only"
) ? void (0) : __assert_fail ("(Is64Bit || PPC::GPRCRegClass.hasSubClassEq(RC) || PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) && \"isel is for regular integer GPRs only\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 799, __extension__ __PRETTY_FUNCTION__))
798 PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) &&(static_cast <bool> ((Is64Bit || PPC::GPRCRegClass.hasSubClassEq
(RC) || PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) && "isel is for regular integer GPRs only"
) ? void (0) : __assert_fail ("(Is64Bit || PPC::GPRCRegClass.hasSubClassEq(RC) || PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) && \"isel is for regular integer GPRs only\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 799, __extension__ __PRETTY_FUNCTION__))
799 "isel is for regular integer GPRs only")(static_cast <bool> ((Is64Bit || PPC::GPRCRegClass.hasSubClassEq
(RC) || PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) && "isel is for regular integer GPRs only"
) ? void (0) : __assert_fail ("(Is64Bit || PPC::GPRCRegClass.hasSubClassEq(RC) || PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) && \"isel is for regular integer GPRs only\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 799, __extension__ __PRETTY_FUNCTION__))
;
800
801 unsigned OpCode = Is64Bit ? PPC::ISEL8 : PPC::ISEL;
802 auto SelectPred = static_cast<PPC::Predicate>(Cond[0].getImm());
803
804 unsigned SubIdx = 0;
805 bool SwapOps = false;
806 switch (SelectPred) {
807 case PPC::PRED_EQ:
808 case PPC::PRED_EQ_MINUS:
809 case PPC::PRED_EQ_PLUS:
810 SubIdx = PPC::sub_eq; SwapOps = false; break;
811 case PPC::PRED_NE:
812 case PPC::PRED_NE_MINUS:
813 case PPC::PRED_NE_PLUS:
814 SubIdx = PPC::sub_eq; SwapOps = true; break;
815 case PPC::PRED_LT:
816 case PPC::PRED_LT_MINUS:
817 case PPC::PRED_LT_PLUS:
818 SubIdx = PPC::sub_lt; SwapOps = false; break;
819 case PPC::PRED_GE:
820 case PPC::PRED_GE_MINUS:
821 case PPC::PRED_GE_PLUS:
822 SubIdx = PPC::sub_lt; SwapOps = true; break;
823 case PPC::PRED_GT:
824 case PPC::PRED_GT_MINUS:
825 case PPC::PRED_GT_PLUS:
826 SubIdx = PPC::sub_gt; SwapOps = false; break;
827 case PPC::PRED_LE:
828 case PPC::PRED_LE_MINUS:
829 case PPC::PRED_LE_PLUS:
830 SubIdx = PPC::sub_gt; SwapOps = true; break;
831 case PPC::PRED_UN:
832 case PPC::PRED_UN_MINUS:
833 case PPC::PRED_UN_PLUS:
834 SubIdx = PPC::sub_un; SwapOps = false; break;
835 case PPC::PRED_NU:
836 case PPC::PRED_NU_MINUS:
837 case PPC::PRED_NU_PLUS:
838 SubIdx = PPC::sub_un; SwapOps = true; break;
839 case PPC::PRED_BIT_SET: SubIdx = 0; SwapOps = false; break;
840 case PPC::PRED_BIT_UNSET: SubIdx = 0; SwapOps = true; break;
841 }
842
843 unsigned FirstReg = SwapOps ? FalseReg : TrueReg,
844 SecondReg = SwapOps ? TrueReg : FalseReg;
845
846 // The first input register of isel cannot be r0. If it is a member
847 // of a register class that can be r0, then copy it first (the
848 // register allocator should eliminate the copy).
849 if (MRI.getRegClass(FirstReg)->contains(PPC::R0) ||
850 MRI.getRegClass(FirstReg)->contains(PPC::X0)) {
851 const TargetRegisterClass *FirstRC =
852 MRI.getRegClass(FirstReg)->contains(PPC::X0) ?
853 &PPC::G8RC_NOX0RegClass : &PPC::GPRC_NOR0RegClass;
854 unsigned OldFirstReg = FirstReg;
855 FirstReg = MRI.createVirtualRegister(FirstRC);
856 BuildMI(MBB, MI, dl, get(TargetOpcode::COPY), FirstReg)
857 .addReg(OldFirstReg);
858 }
859
860 BuildMI(MBB, MI, dl, get(OpCode), DestReg)
861 .addReg(FirstReg).addReg(SecondReg)
862 .addReg(Cond[1].getReg(), 0, SubIdx);
863}
864
865static unsigned getCRBitValue(unsigned CRBit) {
866 unsigned Ret = 4;
867 if (CRBit == PPC::CR0LT || CRBit == PPC::CR1LT ||
868 CRBit == PPC::CR2LT || CRBit == PPC::CR3LT ||
869 CRBit == PPC::CR4LT || CRBit == PPC::CR5LT ||
870 CRBit == PPC::CR6LT || CRBit == PPC::CR7LT)
871 Ret = 3;
872 if (CRBit == PPC::CR0GT || CRBit == PPC::CR1GT ||
873 CRBit == PPC::CR2GT || CRBit == PPC::CR3GT ||
874 CRBit == PPC::CR4GT || CRBit == PPC::CR5GT ||
875 CRBit == PPC::CR6GT || CRBit == PPC::CR7GT)
876 Ret = 2;
877 if (CRBit == PPC::CR0EQ || CRBit == PPC::CR1EQ ||
878 CRBit == PPC::CR2EQ || CRBit == PPC::CR3EQ ||
879 CRBit == PPC::CR4EQ || CRBit == PPC::CR5EQ ||
880 CRBit == PPC::CR6EQ || CRBit == PPC::CR7EQ)
881 Ret = 1;
882 if (CRBit == PPC::CR0UN || CRBit == PPC::CR1UN ||
883 CRBit == PPC::CR2UN || CRBit == PPC::CR3UN ||
884 CRBit == PPC::CR4UN || CRBit == PPC::CR5UN ||
885 CRBit == PPC::CR6UN || CRBit == PPC::CR7UN)
886 Ret = 0;
887
888 assert(Ret != 4 && "Invalid CR bit register")(static_cast <bool> (Ret != 4 && "Invalid CR bit register"
) ? void (0) : __assert_fail ("Ret != 4 && \"Invalid CR bit register\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 888, __extension__ __PRETTY_FUNCTION__))
;
889 return Ret;
890}
891
892void PPCInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
893 MachineBasicBlock::iterator I,
894 const DebugLoc &DL, unsigned DestReg,
895 unsigned SrcReg, bool KillSrc) const {
896 // We can end up with self copies and similar things as a result of VSX copy
897 // legalization. Promote them here.
898 const TargetRegisterInfo *TRI = &getRegisterInfo();
899 if (PPC::F8RCRegClass.contains(DestReg) &&
900 PPC::VSRCRegClass.contains(SrcReg)) {
901 unsigned SuperReg =
902 TRI->getMatchingSuperReg(DestReg, PPC::sub_64, &PPC::VSRCRegClass);
903
904 if (VSXSelfCopyCrash && SrcReg == SuperReg)
905 llvm_unreachable("nop VSX copy")::llvm::llvm_unreachable_internal("nop VSX copy", "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 905)
;
906
907 DestReg = SuperReg;
908 } else if (PPC::F8RCRegClass.contains(SrcReg) &&
909 PPC::VSRCRegClass.contains(DestReg)) {
910 unsigned SuperReg =
911 TRI->getMatchingSuperReg(SrcReg, PPC::sub_64, &PPC::VSRCRegClass);
912
913 if (VSXSelfCopyCrash && DestReg == SuperReg)
914 llvm_unreachable("nop VSX copy")::llvm::llvm_unreachable_internal("nop VSX copy", "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 914)
;
915
916 SrcReg = SuperReg;
917 }
918
919 // Different class register copy
920 if (PPC::CRBITRCRegClass.contains(SrcReg) &&
921 PPC::GPRCRegClass.contains(DestReg)) {
922 unsigned CRReg = getCRFromCRBit(SrcReg);
923 BuildMI(MBB, I, DL, get(PPC::MFOCRF), DestReg).addReg(CRReg);
924 getKillRegState(KillSrc);
925 // Rotate the CR bit in the CR fields to be the least significant bit and
926 // then mask with 0x1 (MB = ME = 31).
927 BuildMI(MBB, I, DL, get(PPC::RLWINM), DestReg)
928 .addReg(DestReg, RegState::Kill)
929 .addImm(TRI->getEncodingValue(CRReg) * 4 + (4 - getCRBitValue(SrcReg)))
930 .addImm(31)
931 .addImm(31);
932 return;
933 } else if (PPC::CRRCRegClass.contains(SrcReg) &&
934 PPC::G8RCRegClass.contains(DestReg)) {
935 BuildMI(MBB, I, DL, get(PPC::MFOCRF8), DestReg).addReg(SrcReg);
936 getKillRegState(KillSrc);
937 return;
938 } else if (PPC::CRRCRegClass.contains(SrcReg) &&
939 PPC::GPRCRegClass.contains(DestReg)) {
940 BuildMI(MBB, I, DL, get(PPC::MFOCRF), DestReg).addReg(SrcReg);
941 getKillRegState(KillSrc);
942 return;
943 } else if (PPC::G8RCRegClass.contains(SrcReg) &&
944 PPC::VSFRCRegClass.contains(DestReg)) {
945 BuildMI(MBB, I, DL, get(PPC::MTVSRD), DestReg).addReg(SrcReg);
946 NumGPRtoVSRSpill++;
947 getKillRegState(KillSrc);
948 return;
949 } else if (PPC::VSFRCRegClass.contains(SrcReg) &&
950 PPC::G8RCRegClass.contains(DestReg)) {
951 BuildMI(MBB, I, DL, get(PPC::MFVSRD), DestReg).addReg(SrcReg);
952 getKillRegState(KillSrc);
953 return;
954 } else if (PPC::SPERCRegClass.contains(SrcReg) &&
955 PPC::SPE4RCRegClass.contains(DestReg)) {
956 BuildMI(MBB, I, DL, get(PPC::EFSCFD), DestReg).addReg(SrcReg);
957 getKillRegState(KillSrc);
958 return;
959 } else if (PPC::SPE4RCRegClass.contains(SrcReg) &&
960 PPC::SPERCRegClass.contains(DestReg)) {
961 BuildMI(MBB, I, DL, get(PPC::EFDCFS), DestReg).addReg(SrcReg);
962 getKillRegState(KillSrc);
963 return;
964 }
965
966
967 unsigned Opc;
968 if (PPC::GPRCRegClass.contains(DestReg, SrcReg))
969 Opc = PPC::OR;
970 else if (PPC::G8RCRegClass.contains(DestReg, SrcReg))
971 Opc = PPC::OR8;
972 else if (PPC::F4RCRegClass.contains(DestReg, SrcReg))
973 Opc = PPC::FMR;
974 else if (PPC::CRRCRegClass.contains(DestReg, SrcReg))
975 Opc = PPC::MCRF;
976 else if (PPC::VRRCRegClass.contains(DestReg, SrcReg))
977 Opc = PPC::VOR;
978 else if (PPC::VSRCRegClass.contains(DestReg, SrcReg))
979 // There are two different ways this can be done:
980 // 1. xxlor : This has lower latency (on the P7), 2 cycles, but can only
981 // issue in VSU pipeline 0.
982 // 2. xmovdp/xmovsp: This has higher latency (on the P7), 6 cycles, but
983 // can go to either pipeline.
984 // We'll always use xxlor here, because in practically all cases where
985 // copies are generated, they are close enough to some use that the
986 // lower-latency form is preferable.
987 Opc = PPC::XXLOR;
988 else if (PPC::VSFRCRegClass.contains(DestReg, SrcReg) ||
989 PPC::VSSRCRegClass.contains(DestReg, SrcReg))
990 Opc = PPC::XXLORf;
991 else if (PPC::QFRCRegClass.contains(DestReg, SrcReg))
992 Opc = PPC::QVFMR;
993 else if (PPC::QSRCRegClass.contains(DestReg, SrcReg))
994 Opc = PPC::QVFMRs;
995 else if (PPC::QBRCRegClass.contains(DestReg, SrcReg))
996 Opc = PPC::QVFMRb;
997 else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg))
998 Opc = PPC::CROR;
999 else if (PPC::SPERCRegClass.contains(DestReg, SrcReg))
1000 Opc = PPC::EVOR;
1001 else
1002 llvm_unreachable("Impossible reg-to-reg copy")::llvm::llvm_unreachable_internal("Impossible reg-to-reg copy"
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 1002)
;
1003
1004 const MCInstrDesc &MCID = get(Opc);
1005 if (MCID.getNumOperands() == 3)
1006 BuildMI(MBB, I, DL, MCID, DestReg)
1007 .addReg(SrcReg).addReg(SrcReg, getKillRegState(KillSrc));
1008 else
1009 BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc));
1010}
1011
1012unsigned PPCInstrInfo::getStoreOpcodeForSpill(unsigned Reg,
1013 const TargetRegisterClass *RC)
1014 const {
1015 const unsigned *OpcodesForSpill = getStoreOpcodesForSpillArray();
1016 int OpcodeIndex = 0;
1017
1018 if (RC != nullptr) {
1019 if (PPC::GPRCRegClass.hasSubClassEq(RC) ||
1020 PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) {
1021 OpcodeIndex = SOK_Int4Spill;
1022 } else if (PPC::G8RCRegClass.hasSubClassEq(RC) ||
1023 PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) {
1024 OpcodeIndex = SOK_Int8Spill;
1025 } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
1026 OpcodeIndex = SOK_Float8Spill;
1027 } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
1028 OpcodeIndex = SOK_Float4Spill;
1029 } else if (PPC::SPERCRegClass.hasSubClassEq(RC)) {
1030 OpcodeIndex = SOK_SPESpill;
1031 } else if (PPC::SPE4RCRegClass.hasSubClassEq(RC)) {
1032 OpcodeIndex = SOK_SPE4Spill;
1033 } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
1034 OpcodeIndex = SOK_CRSpill;
1035 } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
1036 OpcodeIndex = SOK_CRBitSpill;
1037 } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
1038 OpcodeIndex = SOK_VRVectorSpill;
1039 } else if (PPC::VSRCRegClass.hasSubClassEq(RC)) {
1040 OpcodeIndex = SOK_VSXVectorSpill;
1041 } else if (PPC::VSFRCRegClass.hasSubClassEq(RC)) {
1042 OpcodeIndex = SOK_VectorFloat8Spill;
1043 } else if (PPC::VSSRCRegClass.hasSubClassEq(RC)) {
1044 OpcodeIndex = SOK_VectorFloat4Spill;
1045 } else if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) {
1046 OpcodeIndex = SOK_VRSaveSpill;
1047 } else if (PPC::QFRCRegClass.hasSubClassEq(RC)) {
1048 OpcodeIndex = SOK_QuadFloat8Spill;
1049 } else if (PPC::QSRCRegClass.hasSubClassEq(RC)) {
1050 OpcodeIndex = SOK_QuadFloat4Spill;
1051 } else if (PPC::QBRCRegClass.hasSubClassEq(RC)) {
1052 OpcodeIndex = SOK_QuadBitSpill;
1053 } else if (PPC::SPILLTOVSRRCRegClass.hasSubClassEq(RC)) {
1054 OpcodeIndex = SOK_SpillToVSR;
1055 } else {
1056 llvm_unreachable("Unknown regclass!")::llvm::llvm_unreachable_internal("Unknown regclass!", "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 1056)
;
1057 }
1058 } else {
1059 if (PPC::GPRCRegClass.contains(Reg) ||
1060 PPC::GPRC_NOR0RegClass.contains(Reg)) {
1061 OpcodeIndex = SOK_Int4Spill;
1062 } else if (PPC::G8RCRegClass.contains(Reg) ||
1063 PPC::G8RC_NOX0RegClass.contains(Reg)) {
1064 OpcodeIndex = SOK_Int8Spill;
1065 } else if (PPC::F8RCRegClass.contains(Reg)) {
1066 OpcodeIndex = SOK_Float8Spill;
1067 } else if (PPC::F4RCRegClass.contains(Reg)) {
1068 OpcodeIndex = SOK_Float4Spill;
1069 } else if (PPC::CRRCRegClass.contains(Reg)) {
1070 OpcodeIndex = SOK_CRSpill;
1071 } else if (PPC::CRBITRCRegClass.contains(Reg)) {
1072 OpcodeIndex = SOK_CRBitSpill;
1073 } else if (PPC::VRRCRegClass.contains(Reg)) {
1074 OpcodeIndex = SOK_VRVectorSpill;
1075 } else if (PPC::VSRCRegClass.contains(Reg)) {
1076 OpcodeIndex = SOK_VSXVectorSpill;
1077 } else if (PPC::VSFRCRegClass.contains(Reg)) {
1078 OpcodeIndex = SOK_VectorFloat8Spill;
1079 } else if (PPC::VSSRCRegClass.contains(Reg)) {
1080 OpcodeIndex = SOK_VectorFloat4Spill;
1081 } else if (PPC::VRSAVERCRegClass.contains(Reg)) {
1082 OpcodeIndex = SOK_VRSaveSpill;
1083 } else if (PPC::QFRCRegClass.contains(Reg)) {
1084 OpcodeIndex = SOK_QuadFloat8Spill;
1085 } else if (PPC::QSRCRegClass.contains(Reg)) {
1086 OpcodeIndex = SOK_QuadFloat4Spill;
1087 } else if (PPC::QBRCRegClass.contains(Reg)) {
1088 OpcodeIndex = SOK_QuadBitSpill;
1089 } else if (PPC::SPILLTOVSRRCRegClass.contains(Reg)) {
1090 OpcodeIndex = SOK_SpillToVSR;
1091 } else {
1092 llvm_unreachable("Unknown regclass!")::llvm::llvm_unreachable_internal("Unknown regclass!", "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 1092)
;
1093 }
1094 }
1095 return OpcodesForSpill[OpcodeIndex];
1096}
1097
1098unsigned
1099PPCInstrInfo::getLoadOpcodeForSpill(unsigned Reg,
1100 const TargetRegisterClass *RC) const {
1101 const unsigned *OpcodesForSpill = getLoadOpcodesForSpillArray();
1102 int OpcodeIndex = 0;
1103
1104 if (RC != nullptr) {
1105 if (PPC::GPRCRegClass.hasSubClassEq(RC) ||
1106 PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) {
1107 OpcodeIndex = SOK_Int4Spill;
1108 } else if (PPC::G8RCRegClass.hasSubClassEq(RC) ||
1109 PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) {
1110 OpcodeIndex = SOK_Int8Spill;
1111 } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
1112 OpcodeIndex = SOK_Float8Spill;
1113 } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
1114 OpcodeIndex = SOK_Float4Spill;
1115 } else if (PPC::SPERCRegClass.hasSubClassEq(RC)) {
1116 OpcodeIndex = SOK_SPESpill;
1117 } else if (PPC::SPE4RCRegClass.hasSubClassEq(RC)) {
1118 OpcodeIndex = SOK_SPE4Spill;
1119 } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
1120 OpcodeIndex = SOK_CRSpill;
1121 } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
1122 OpcodeIndex = SOK_CRBitSpill;
1123 } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
1124 OpcodeIndex = SOK_VRVectorSpill;
1125 } else if (PPC::VSRCRegClass.hasSubClassEq(RC)) {
1126 OpcodeIndex = SOK_VSXVectorSpill;
1127 } else if (PPC::VSFRCRegClass.hasSubClassEq(RC)) {
1128 OpcodeIndex = SOK_VectorFloat8Spill;
1129 } else if (PPC::VSSRCRegClass.hasSubClassEq(RC)) {
1130 OpcodeIndex = SOK_VectorFloat4Spill;
1131 } else if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) {
1132 OpcodeIndex = SOK_VRSaveSpill;
1133 } else if (PPC::QFRCRegClass.hasSubClassEq(RC)) {
1134 OpcodeIndex = SOK_QuadFloat8Spill;
1135 } else if (PPC::QSRCRegClass.hasSubClassEq(RC)) {
1136 OpcodeIndex = SOK_QuadFloat4Spill;
1137 } else if (PPC::QBRCRegClass.hasSubClassEq(RC)) {
1138 OpcodeIndex = SOK_QuadBitSpill;
1139 } else if (PPC::SPILLTOVSRRCRegClass.hasSubClassEq(RC)) {
1140 OpcodeIndex = SOK_SpillToVSR;
1141 } else {
1142 llvm_unreachable("Unknown regclass!")::llvm::llvm_unreachable_internal("Unknown regclass!", "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 1142)
;
1143 }
1144 } else {
1145 if (PPC::GPRCRegClass.contains(Reg) ||
1146 PPC::GPRC_NOR0RegClass.contains(Reg)) {
1147 OpcodeIndex = SOK_Int4Spill;
1148 } else if (PPC::G8RCRegClass.contains(Reg) ||
1149 PPC::G8RC_NOX0RegClass.contains(Reg)) {
1150 OpcodeIndex = SOK_Int8Spill;
1151 } else if (PPC::F8RCRegClass.contains(Reg)) {
1152 OpcodeIndex = SOK_Float8Spill;
1153 } else if (PPC::F4RCRegClass.contains(Reg)) {
1154 OpcodeIndex = SOK_Float4Spill;
1155 } else if (PPC::CRRCRegClass.contains(Reg)) {
1156 OpcodeIndex = SOK_CRSpill;
1157 } else if (PPC::CRBITRCRegClass.contains(Reg)) {
1158 OpcodeIndex = SOK_CRBitSpill;
1159 } else if (PPC::VRRCRegClass.contains(Reg)) {
1160 OpcodeIndex = SOK_VRVectorSpill;
1161 } else if (PPC::VSRCRegClass.contains(Reg)) {
1162 OpcodeIndex = SOK_VSXVectorSpill;
1163 } else if (PPC::VSFRCRegClass.contains(Reg)) {
1164 OpcodeIndex = SOK_VectorFloat8Spill;
1165 } else if (PPC::VSSRCRegClass.contains(Reg)) {
1166 OpcodeIndex = SOK_VectorFloat4Spill;
1167 } else if (PPC::VRSAVERCRegClass.contains(Reg)) {
1168 OpcodeIndex = SOK_VRSaveSpill;
1169 } else if (PPC::QFRCRegClass.contains(Reg)) {
1170 OpcodeIndex = SOK_QuadFloat8Spill;
1171 } else if (PPC::QSRCRegClass.contains(Reg)) {
1172 OpcodeIndex = SOK_QuadFloat4Spill;
1173 } else if (PPC::QBRCRegClass.contains(Reg)) {
1174 OpcodeIndex = SOK_QuadBitSpill;
1175 } else if (PPC::SPILLTOVSRRCRegClass.contains(Reg)) {
1176 OpcodeIndex = SOK_SpillToVSR;
1177 } else {
1178 llvm_unreachable("Unknown regclass!")::llvm::llvm_unreachable_internal("Unknown regclass!", "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 1178)
;
1179 }
1180 }
1181 return OpcodesForSpill[OpcodeIndex];
1182}
1183
1184void PPCInstrInfo::StoreRegToStackSlot(
1185 MachineFunction &MF, unsigned SrcReg, bool isKill, int FrameIdx,
1186 const TargetRegisterClass *RC,
1187 SmallVectorImpl<MachineInstr *> &NewMIs) const {
1188 unsigned Opcode = getStoreOpcodeForSpill(PPC::NoRegister, RC);
1189 DebugLoc DL;
1190
1191 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1192 FuncInfo->setHasSpills();
1193
1194 NewMIs.push_back(addFrameReference(
1195 BuildMI(MF, DL, get(Opcode)).addReg(SrcReg, getKillRegState(isKill)),
1196 FrameIdx));
1197
1198 if (PPC::CRRCRegClass.hasSubClassEq(RC) ||
1199 PPC::CRBITRCRegClass.hasSubClassEq(RC))
1200 FuncInfo->setSpillsCR();
1201
1202 if (PPC::VRSAVERCRegClass.hasSubClassEq(RC))
1203 FuncInfo->setSpillsVRSAVE();
1204
1205 if (isXFormMemOp(Opcode))
1206 FuncInfo->setHasNonRISpills();
1207}
1208
1209void PPCInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
1210 MachineBasicBlock::iterator MI,
1211 unsigned SrcReg, bool isKill,
1212 int FrameIdx,
1213 const TargetRegisterClass *RC,
1214 const TargetRegisterInfo *TRI) const {
1215 MachineFunction &MF = *MBB.getParent();
1216 SmallVector<MachineInstr *, 4> NewMIs;
1217
1218 // We need to avoid a situation in which the value from a VRRC register is
1219 // spilled using an Altivec instruction and reloaded into a VSRC register
1220 // using a VSX instruction. The issue with this is that the VSX
1221 // load/store instructions swap the doublewords in the vector and the Altivec
1222 // ones don't. The register classes on the spill/reload may be different if
1223 // the register is defined using an Altivec instruction and is then used by a
1224 // VSX instruction.
1225 RC = updatedRC(RC);
1226
1227 StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs);
1228
1229 for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
1230 MBB.insert(MI, NewMIs[i]);
1231
1232 const MachineFrameInfo &MFI = MF.getFrameInfo();
1233 MachineMemOperand *MMO = MF.getMachineMemOperand(
1234 MachinePointerInfo::getFixedStack(MF, FrameIdx),
1235 MachineMemOperand::MOStore, MFI.getObjectSize(FrameIdx),
1236 MFI.getObjectAlignment(FrameIdx));
1237 NewMIs.back()->addMemOperand(MF, MMO);
1238}
1239
1240void PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, const DebugLoc &DL,
1241 unsigned DestReg, int FrameIdx,
1242 const TargetRegisterClass *RC,
1243 SmallVectorImpl<MachineInstr *> &NewMIs)
1244 const {
1245 unsigned Opcode = getLoadOpcodeForSpill(PPC::NoRegister, RC);
1246 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(Opcode), DestReg),
1247 FrameIdx));
1248 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1249
1250 if (PPC::CRRCRegClass.hasSubClassEq(RC) ||
1251 PPC::CRBITRCRegClass.hasSubClassEq(RC))
1252 FuncInfo->setSpillsCR();
1253
1254 if (PPC::VRSAVERCRegClass.hasSubClassEq(RC))
1255 FuncInfo->setSpillsVRSAVE();
1256
1257 if (isXFormMemOp(Opcode))
1258 FuncInfo->setHasNonRISpills();
1259}
1260
1261void
1262PPCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
1263 MachineBasicBlock::iterator MI,
1264 unsigned DestReg, int FrameIdx,
1265 const TargetRegisterClass *RC,
1266 const TargetRegisterInfo *TRI) const {
1267 MachineFunction &MF = *MBB.getParent();
1268 SmallVector<MachineInstr*, 4> NewMIs;
1269 DebugLoc DL;
1270 if (MI != MBB.end()) DL = MI->getDebugLoc();
1271
1272 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1273 FuncInfo->setHasSpills();
1274
1275 // We need to avoid a situation in which the value from a VRRC register is
1276 // spilled using an Altivec instruction and reloaded into a VSRC register
1277 // using a VSX instruction. The issue with this is that the VSX
1278 // load/store instructions swap the doublewords in the vector and the Altivec
1279 // ones don't. The register classes on the spill/reload may be different if
1280 // the register is defined using an Altivec instruction and is then used by a
1281 // VSX instruction.
1282 if (Subtarget.hasVSX() && RC == &PPC::VRRCRegClass)
1283 RC = &PPC::VSRCRegClass;
1284
1285 LoadRegFromStackSlot(MF, DL, DestReg, FrameIdx, RC, NewMIs);
1286
1287 for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
1288 MBB.insert(MI, NewMIs[i]);
1289
1290 const MachineFrameInfo &MFI = MF.getFrameInfo();
1291 MachineMemOperand *MMO = MF.getMachineMemOperand(
1292 MachinePointerInfo::getFixedStack(MF, FrameIdx),
1293 MachineMemOperand::MOLoad, MFI.getObjectSize(FrameIdx),
1294 MFI.getObjectAlignment(FrameIdx));
1295 NewMIs.back()->addMemOperand(MF, MMO);
1296}
1297
1298bool PPCInstrInfo::
1299reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
1300 assert(Cond.size() == 2 && "Invalid PPC branch opcode!")(static_cast <bool> (Cond.size() == 2 && "Invalid PPC branch opcode!"
) ? void (0) : __assert_fail ("Cond.size() == 2 && \"Invalid PPC branch opcode!\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 1300, __extension__ __PRETTY_FUNCTION__))
;
1301 if (Cond[1].getReg() == PPC::CTR8 || Cond[1].getReg() == PPC::CTR)
1302 Cond[0].setImm(Cond[0].getImm() == 0 ? 1 : 0);
1303 else
1304 // Leave the CR# the same, but invert the condition.
1305 Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm()));
1306 return false;
1307}
1308
1309bool PPCInstrInfo::FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
1310 unsigned Reg, MachineRegisterInfo *MRI) const {
1311 // For some instructions, it is legal to fold ZERO into the RA register field.
1312 // A zero immediate should always be loaded with a single li.
1313 unsigned DefOpc = DefMI.getOpcode();
1314 if (DefOpc != PPC::LI && DefOpc != PPC::LI8)
1315 return false;
1316 if (!DefMI.getOperand(1).isImm())
1317 return false;
1318 if (DefMI.getOperand(1).getImm() != 0)
1319 return false;
1320
1321 // Note that we cannot here invert the arguments of an isel in order to fold
1322 // a ZERO into what is presented as the second argument. All we have here
1323 // is the condition bit, and that might come from a CR-logical bit operation.
1324
1325 const MCInstrDesc &UseMCID = UseMI.getDesc();
1326
1327 // Only fold into real machine instructions.
1328 if (UseMCID.isPseudo())
1329 return false;
1330
1331 unsigned UseIdx;
1332 for (UseIdx = 0; UseIdx < UseMI.getNumOperands(); ++UseIdx)
1333 if (UseMI.getOperand(UseIdx).isReg() &&
1334 UseMI.getOperand(UseIdx).getReg() == Reg)
1335 break;
1336
1337 assert(UseIdx < UseMI.getNumOperands() && "Cannot find Reg in UseMI")(static_cast <bool> (UseIdx < UseMI.getNumOperands()
&& "Cannot find Reg in UseMI") ? void (0) : __assert_fail
("UseIdx < UseMI.getNumOperands() && \"Cannot find Reg in UseMI\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 1337, __extension__ __PRETTY_FUNCTION__))
;
1338 assert(UseIdx < UseMCID.getNumOperands() && "No operand description for Reg")(static_cast <bool> (UseIdx < UseMCID.getNumOperands
() && "No operand description for Reg") ? void (0) : __assert_fail
("UseIdx < UseMCID.getNumOperands() && \"No operand description for Reg\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 1338, __extension__ __PRETTY_FUNCTION__))
;
1339
1340 const MCOperandInfo *UseInfo = &UseMCID.OpInfo[UseIdx];
1341
1342 // We can fold the zero if this register requires a GPRC_NOR0/G8RC_NOX0
1343 // register (which might also be specified as a pointer class kind).
1344 if (UseInfo->isLookupPtrRegClass()) {
1345 if (UseInfo->RegClass /* Kind */ != 1)
1346 return false;
1347 } else {
1348 if (UseInfo->RegClass != PPC::GPRC_NOR0RegClassID &&
1349 UseInfo->RegClass != PPC::G8RC_NOX0RegClassID)
1350 return false;
1351 }
1352
1353 // Make sure this is not tied to an output register (or otherwise
1354 // constrained). This is true for ST?UX registers, for example, which
1355 // are tied to their output registers.
1356 if (UseInfo->Constraints != 0)
1357 return false;
1358
1359 unsigned ZeroReg;
1360 if (UseInfo->isLookupPtrRegClass()) {
1361 bool isPPC64 = Subtarget.isPPC64();
1362 ZeroReg = isPPC64 ? PPC::ZERO8 : PPC::ZERO;
1363 } else {
1364 ZeroReg = UseInfo->RegClass == PPC::G8RC_NOX0RegClassID ?
1365 PPC::ZERO8 : PPC::ZERO;
1366 }
1367
1368 bool DeleteDef = MRI->hasOneNonDBGUse(Reg);
1369 UseMI.getOperand(UseIdx).setReg(ZeroReg);
1370
1371 if (DeleteDef)
1372 DefMI.eraseFromParent();
1373
1374 return true;
1375}
1376
1377static bool MBBDefinesCTR(MachineBasicBlock &MBB) {
1378 for (MachineBasicBlock::iterator I = MBB.begin(), IE = MBB.end();
1379 I != IE; ++I)
1380 if (I->definesRegister(PPC::CTR) || I->definesRegister(PPC::CTR8))
1381 return true;
1382 return false;
1383}
1384
1385// We should make sure that, if we're going to predicate both sides of a
1386// condition (a diamond), that both sides don't define the counter register. We
1387// can predicate counter-decrement-based branches, but while that predicates
1388// the branching, it does not predicate the counter decrement. If we tried to
1389// merge the triangle into one predicated block, we'd decrement the counter
1390// twice.
1391bool PPCInstrInfo::isProfitableToIfCvt(MachineBasicBlock &TMBB,
1392 unsigned NumT, unsigned ExtraT,
1393 MachineBasicBlock &FMBB,
1394 unsigned NumF, unsigned ExtraF,
1395 BranchProbability Probability) const {
1396 return !(MBBDefinesCTR(TMBB) && MBBDefinesCTR(FMBB));
1397}
1398
1399
1400bool PPCInstrInfo::isPredicated(const MachineInstr &MI) const {
1401 // The predicated branches are identified by their type, not really by the
1402 // explicit presence of a predicate. Furthermore, some of them can be
1403 // predicated more than once. Because if conversion won't try to predicate
1404 // any instruction which already claims to be predicated (by returning true
1405 // here), always return false. In doing so, we let isPredicable() be the
1406 // final word on whether not the instruction can be (further) predicated.
1407
1408 return false;
1409}
1410
1411bool PPCInstrInfo::isUnpredicatedTerminator(const MachineInstr &MI) const {
1412 if (!MI.isTerminator())
1413 return false;
1414
1415 // Conditional branch is a special case.
1416 if (MI.isBranch() && !MI.isBarrier())
1417 return true;
1418
1419 return !isPredicated(MI);
1420}
1421
1422bool PPCInstrInfo::PredicateInstruction(MachineInstr &MI,
1423 ArrayRef<MachineOperand> Pred) const {
1424 unsigned OpC = MI.getOpcode();
1425 if (OpC == PPC::BLR || OpC == PPC::BLR8) {
1426 if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) {
1427 bool isPPC64 = Subtarget.isPPC64();
1428 MI.setDesc(get(Pred[0].getImm() ? (isPPC64 ? PPC::BDNZLR8 : PPC::BDNZLR)
1429 : (isPPC64 ? PPC::BDZLR8 : PPC::BDZLR)));
1430 } else if (Pred[0].getImm() == PPC::PRED_BIT_SET) {
1431 MI.setDesc(get(PPC::BCLR));
1432 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
1433 .addReg(Pred[1].getReg());
1434 } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) {
1435 MI.setDesc(get(PPC::BCLRn));
1436 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
1437 .addReg(Pred[1].getReg());
1438 } else {
1439 MI.setDesc(get(PPC::BCCLR));
1440 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
1441 .addImm(Pred[0].getImm())
1442 .addReg(Pred[1].getReg());
1443 }
1444
1445 return true;
1446 } else if (OpC == PPC::B) {
1447 if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) {
1448 bool isPPC64 = Subtarget.isPPC64();
1449 MI.setDesc(get(Pred[0].getImm() ? (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ)
1450 : (isPPC64 ? PPC::BDZ8 : PPC::BDZ)));
1451 } else if (Pred[0].getImm() == PPC::PRED_BIT_SET) {
1452 MachineBasicBlock *MBB = MI.getOperand(0).getMBB();
1453 MI.RemoveOperand(0);
1454
1455 MI.setDesc(get(PPC::BC));
1456 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
1457 .addReg(Pred[1].getReg())
1458 .addMBB(MBB);
1459 } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) {
1460 MachineBasicBlock *MBB = MI.getOperand(0).getMBB();
1461 MI.RemoveOperand(0);
1462
1463 MI.setDesc(get(PPC::BCn));
1464 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
1465 .addReg(Pred[1].getReg())
1466 .addMBB(MBB);
1467 } else {
1468 MachineBasicBlock *MBB = MI.getOperand(0).getMBB();
1469 MI.RemoveOperand(0);
1470
1471 MI.setDesc(get(PPC::BCC));
1472 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
1473 .addImm(Pred[0].getImm())
1474 .addReg(Pred[1].getReg())
1475 .addMBB(MBB);
1476 }
1477
1478 return true;
1479 } else if (OpC == PPC::BCTR || OpC == PPC::BCTR8 ||
1480 OpC == PPC::BCTRL || OpC == PPC::BCTRL8) {
1481 if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR)
1482 llvm_unreachable("Cannot predicate bctr[l] on the ctr register")::llvm::llvm_unreachable_internal("Cannot predicate bctr[l] on the ctr register"
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 1482)
;
1483
1484 bool setLR = OpC == PPC::BCTRL || OpC == PPC::BCTRL8;
1485 bool isPPC64 = Subtarget.isPPC64();
1486
1487 if (Pred[0].getImm() == PPC::PRED_BIT_SET) {
1488 MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8 : PPC::BCCTR8)
1489 : (setLR ? PPC::BCCTRL : PPC::BCCTR)));
1490 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
1491 .addReg(Pred[1].getReg());
1492 return true;
1493 } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) {
1494 MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8n : PPC::BCCTR8n)
1495 : (setLR ? PPC::BCCTRLn : PPC::BCCTRn)));
1496 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
1497 .addReg(Pred[1].getReg());
1498 return true;
1499 }
1500
1501 MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCCTRL8 : PPC::BCCCTR8)
1502 : (setLR ? PPC::BCCCTRL : PPC::BCCCTR)));
1503 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
1504 .addImm(Pred[0].getImm())
1505 .addReg(Pred[1].getReg());
1506 return true;
1507 }
1508
1509 return false;
1510}
1511
1512bool PPCInstrInfo::SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
1513 ArrayRef<MachineOperand> Pred2) const {
1514 assert(Pred1.size() == 2 && "Invalid PPC first predicate")(static_cast <bool> (Pred1.size() == 2 && "Invalid PPC first predicate"
) ? void (0) : __assert_fail ("Pred1.size() == 2 && \"Invalid PPC first predicate\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 1514, __extension__ __PRETTY_FUNCTION__))
;
1515 assert(Pred2.size() == 2 && "Invalid PPC second predicate")(static_cast <bool> (Pred2.size() == 2 && "Invalid PPC second predicate"
) ? void (0) : __assert_fail ("Pred2.size() == 2 && \"Invalid PPC second predicate\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 1515, __extension__ __PRETTY_FUNCTION__))
;
1516
1517 if (Pred1[1].getReg() == PPC::CTR8 || Pred1[1].getReg() == PPC::CTR)
1518 return false;
1519 if (Pred2[1].getReg() == PPC::CTR8 || Pred2[1].getReg() == PPC::CTR)
1520 return false;
1521
1522 // P1 can only subsume P2 if they test the same condition register.
1523 if (Pred1[1].getReg() != Pred2[1].getReg())
1524 return false;
1525
1526 PPC::Predicate P1 = (PPC::Predicate) Pred1[0].getImm();
1527 PPC::Predicate P2 = (PPC::Predicate) Pred2[0].getImm();
1528
1529 if (P1 == P2)
1530 return true;
1531
1532 // Does P1 subsume P2, e.g. GE subsumes GT.
1533 if (P1 == PPC::PRED_LE &&
1534 (P2 == PPC::PRED_LT || P2 == PPC::PRED_EQ))
1535 return true;
1536 if (P1 == PPC::PRED_GE &&
1537 (P2 == PPC::PRED_GT || P2 == PPC::PRED_EQ))
1538 return true;
1539
1540 return false;
1541}
1542
1543bool PPCInstrInfo::DefinesPredicate(MachineInstr &MI,
1544 std::vector<MachineOperand> &Pred) const {
1545 // Note: At the present time, the contents of Pred from this function is
1546 // unused by IfConversion. This implementation follows ARM by pushing the
1547 // CR-defining operand. Because the 'DZ' and 'DNZ' count as types of
1548 // predicate, instructions defining CTR or CTR8 are also included as
1549 // predicate-defining instructions.
1550
1551 const TargetRegisterClass *RCs[] =
1552 { &PPC::CRRCRegClass, &PPC::CRBITRCRegClass,
1553 &PPC::CTRRCRegClass, &PPC::CTRRC8RegClass };
1554
1555 bool Found = false;
1556 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
1557 const MachineOperand &MO = MI.getOperand(i);
1558 for (unsigned c = 0; c < array_lengthof(RCs) && !Found; ++c) {
1559 const TargetRegisterClass *RC = RCs[c];
1560 if (MO.isReg()) {
1561 if (MO.isDef() && RC->contains(MO.getReg())) {
1562 Pred.push_back(MO);
1563 Found = true;
1564 }
1565 } else if (MO.isRegMask()) {
1566 for (TargetRegisterClass::iterator I = RC->begin(),
1567 IE = RC->end(); I != IE; ++I)
1568 if (MO.clobbersPhysReg(*I)) {
1569 Pred.push_back(MO);
1570 Found = true;
1571 }
1572 }
1573 }
1574 }
1575
1576 return Found;
1577}
1578
1579bool PPCInstrInfo::isPredicable(const MachineInstr &MI) const {
1580 unsigned OpC = MI.getOpcode();
1581 switch (OpC) {
1582 default:
1583 return false;
1584 case PPC::B:
1585 case PPC::BLR:
1586 case PPC::BLR8:
1587 case PPC::BCTR:
1588 case PPC::BCTR8:
1589 case PPC::BCTRL:
1590 case PPC::BCTRL8:
1591 return true;
1592 }
1593}
1594
1595bool PPCInstrInfo::analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
1596 unsigned &SrcReg2, int &Mask,
1597 int &Value) const {
1598 unsigned Opc = MI.getOpcode();
1599
1600 switch (Opc) {
1601 default: return false;
1602 case PPC::CMPWI:
1603 case PPC::CMPLWI:
1604 case PPC::CMPDI:
1605 case PPC::CMPLDI:
1606 SrcReg = MI.getOperand(1).getReg();
1607 SrcReg2 = 0;
1608 Value = MI.getOperand(2).getImm();
1609 Mask = 0xFFFF;
1610 return true;
1611 case PPC::CMPW:
1612 case PPC::CMPLW:
1613 case PPC::CMPD:
1614 case PPC::CMPLD:
1615 case PPC::FCMPUS:
1616 case PPC::FCMPUD:
1617 SrcReg = MI.getOperand(1).getReg();
1618 SrcReg2 = MI.getOperand(2).getReg();
1619 Value = 0;
1620 Mask = 0;
1621 return true;
1622 }
1623}
1624
1625bool PPCInstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
1626 unsigned SrcReg2, int Mask, int Value,
1627 const MachineRegisterInfo *MRI) const {
1628 if (DisableCmpOpt)
1629 return false;
1630
1631 int OpC = CmpInstr.getOpcode();
1632 unsigned CRReg = CmpInstr.getOperand(0).getReg();
1633
1634 // FP record forms set CR1 based on the exception status bits, not a
1635 // comparison with zero.
1636 if (OpC == PPC::FCMPUS || OpC == PPC::FCMPUD)
1637 return false;
1638
1639 // The record forms set the condition register based on a signed comparison
1640 // with zero (so says the ISA manual). This is not as straightforward as it
1641 // seems, however, because this is always a 64-bit comparison on PPC64, even
1642 // for instructions that are 32-bit in nature (like slw for example).
1643 // So, on PPC32, for unsigned comparisons, we can use the record forms only
1644 // for equality checks (as those don't depend on the sign). On PPC64,
1645 // we are restricted to equality for unsigned 64-bit comparisons and for
1646 // signed 32-bit comparisons the applicability is more restricted.
1647 bool isPPC64 = Subtarget.isPPC64();
1648 bool is32BitSignedCompare = OpC == PPC::CMPWI || OpC == PPC::CMPW;
1649 bool is32BitUnsignedCompare = OpC == PPC::CMPLWI || OpC == PPC::CMPLW;
1650 bool is64BitUnsignedCompare = OpC == PPC::CMPLDI || OpC == PPC::CMPLD;
1651
1652 // Get the unique definition of SrcReg.
1653 MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
1654 if (!MI) return false;
1655
1656 bool equalityOnly = false;
1657 bool noSub = false;
1658 if (isPPC64) {
1659 if (is32BitSignedCompare) {
1660 // We can perform this optimization only if MI is sign-extending.
1661 if (isSignExtended(*MI))
1662 noSub = true;
1663 else
1664 return false;
1665 } else if (is32BitUnsignedCompare) {
1666 // We can perform this optimization, equality only, if MI is
1667 // zero-extending.
1668 if (isZeroExtended(*MI)) {
1669 noSub = true;
1670 equalityOnly = true;
1671 } else
1672 return false;
1673 } else
1674 equalityOnly = is64BitUnsignedCompare;
1675 } else
1676 equalityOnly = is32BitUnsignedCompare;
1677
1678 if (equalityOnly) {
1679 // We need to check the uses of the condition register in order to reject
1680 // non-equality comparisons.
1681 for (MachineRegisterInfo::use_instr_iterator
1682 I = MRI->use_instr_begin(CRReg), IE = MRI->use_instr_end();
1683 I != IE; ++I) {
1684 MachineInstr *UseMI = &*I;
1685 if (UseMI->getOpcode() == PPC::BCC) {
1686 PPC::Predicate Pred = (PPC::Predicate)UseMI->getOperand(0).getImm();
1687 unsigned PredCond = PPC::getPredicateCondition(Pred);
1688 // We ignore hint bits when checking for non-equality comparisons.
1689 if (PredCond != PPC::PRED_EQ && PredCond != PPC::PRED_NE)
1690 return false;
1691 } else if (UseMI->getOpcode() == PPC::ISEL ||
1692 UseMI->getOpcode() == PPC::ISEL8) {
1693 unsigned SubIdx = UseMI->getOperand(3).getSubReg();
1694 if (SubIdx != PPC::sub_eq)
1695 return false;
1696 } else
1697 return false;
1698 }
1699 }
1700
1701 MachineBasicBlock::iterator I = CmpInstr;
1702
1703 // Scan forward to find the first use of the compare.
1704 for (MachineBasicBlock::iterator EL = CmpInstr.getParent()->end(); I != EL;
1705 ++I) {
1706 bool FoundUse = false;
1707 for (MachineRegisterInfo::use_instr_iterator
1708 J = MRI->use_instr_begin(CRReg), JE = MRI->use_instr_end();
1709 J != JE; ++J)
1710 if (&*J == &*I) {
1711 FoundUse = true;
1712 break;
1713 }
1714
1715 if (FoundUse)
1716 break;
1717 }
1718
1719 SmallVector<std::pair<MachineOperand*, PPC::Predicate>, 4> PredsToUpdate;
1720 SmallVector<std::pair<MachineOperand*, unsigned>, 4> SubRegsToUpdate;
1721
1722 // There are two possible candidates which can be changed to set CR[01].
1723 // One is MI, the other is a SUB instruction.
1724 // For CMPrr(r1,r2), we are looking for SUB(r1,r2) or SUB(r2,r1).
1725 MachineInstr *Sub = nullptr;
1726 if (SrcReg2 != 0)
1727 // MI is not a candidate for CMPrr.
1728 MI = nullptr;
1729 // FIXME: Conservatively refuse to convert an instruction which isn't in the
1730 // same BB as the comparison. This is to allow the check below to avoid calls
1731 // (and other explicit clobbers); instead we should really check for these
1732 // more explicitly (in at least a few predecessors).
1733 else if (MI->getParent() != CmpInstr.getParent())
1734 return false;
1735 else if (Value != 0) {
1736 // The record-form instructions set CR bit based on signed comparison
1737 // against 0. We try to convert a compare against 1 or -1 into a compare
1738 // against 0 to exploit record-form instructions. For example, we change
1739 // the condition "greater than -1" into "greater than or equal to 0"
1740 // and "less than 1" into "less than or equal to 0".
1741
1742 // Since we optimize comparison based on a specific branch condition,
1743 // we don't optimize if condition code is used by more than once.
1744 if (equalityOnly || !MRI->hasOneUse(CRReg))
1745 return false;
1746
1747 MachineInstr *UseMI = &*MRI->use_instr_begin(CRReg);
1748 if (UseMI->getOpcode() != PPC::BCC)
1749 return false;
1750
1751 PPC::Predicate Pred = (PPC::Predicate)UseMI->getOperand(0).getImm();
1752 PPC::Predicate NewPred = Pred;
Value stored to 'NewPred' during its initialization is never read
1753 unsigned PredCond = PPC::getPredicateCondition(Pred);
1754 unsigned PredHint = PPC::getPredicateHint(Pred);
1755 int16_t Immed = (int16_t)Value;
1756
1757 // When modifying the condition in the predicate, we propagate hint bits
1758 // from the original predicate to the new one.
1759 if (Immed == -1 && PredCond == PPC::PRED_GT)
1760 // We convert "greater than -1" into "greater than or equal to 0",
1761 // since we are assuming signed comparison by !equalityOnly
1762 NewPred = PPC::getPredicate(PPC::PRED_GE, PredHint);
1763 else if (Immed == -1 && PredCond == PPC::PRED_LE)
1764 // We convert "less than or equal to -1" into "less than 0".
1765 NewPred = PPC::getPredicate(PPC::PRED_LT, PredHint);
1766 else if (Immed == 1 && PredCond == PPC::PRED_LT)
1767 // We convert "less than 1" into "less than or equal to 0".
1768 NewPred = PPC::getPredicate(PPC::PRED_LE, PredHint);
1769 else if (Immed == 1 && PredCond == PPC::PRED_GE)
1770 // We convert "greater than or equal to 1" into "greater than 0".
1771 NewPred = PPC::getPredicate(PPC::PRED_GT, PredHint);
1772 else
1773 return false;
1774
1775 PredsToUpdate.push_back(std::make_pair(&(UseMI->getOperand(0)),
1776 NewPred));
1777 }
1778
1779 // Search for Sub.
1780 const TargetRegisterInfo *TRI = &getRegisterInfo();
1781 --I;
1782
1783 // Get ready to iterate backward from CmpInstr.
1784 MachineBasicBlock::iterator E = MI, B = CmpInstr.getParent()->begin();
1785
1786 for (; I != E && !noSub; --I) {
1787 const MachineInstr &Instr = *I;
1788 unsigned IOpC = Instr.getOpcode();
1789
1790 if (&*I != &CmpInstr && (Instr.modifiesRegister(PPC::CR0, TRI) ||
1791 Instr.readsRegister(PPC::CR0, TRI)))
1792 // This instruction modifies or uses the record condition register after
1793 // the one we want to change. While we could do this transformation, it
1794 // would likely not be profitable. This transformation removes one
1795 // instruction, and so even forcing RA to generate one move probably
1796 // makes it unprofitable.
1797 return false;
1798
1799 // Check whether CmpInstr can be made redundant by the current instruction.
1800 if ((OpC == PPC::CMPW || OpC == PPC::CMPLW ||
1801 OpC == PPC::CMPD || OpC == PPC::CMPLD) &&
1802 (IOpC == PPC::SUBF || IOpC == PPC::SUBF8) &&
1803 ((Instr.getOperand(1).getReg() == SrcReg &&
1804 Instr.getOperand(2).getReg() == SrcReg2) ||
1805 (Instr.getOperand(1).getReg() == SrcReg2 &&
1806 Instr.getOperand(2).getReg() == SrcReg))) {
1807 Sub = &*I;
1808 break;
1809 }
1810
1811 if (I == B)
1812 // The 'and' is below the comparison instruction.
1813 return false;
1814 }
1815
1816 // Return false if no candidates exist.
1817 if (!MI && !Sub)
1818 return false;
1819
1820 // The single candidate is called MI.
1821 if (!MI) MI = Sub;
1822
1823 int NewOpC = -1;
1824 int MIOpC = MI->getOpcode();
1825 if (MIOpC == PPC::ANDIo || MIOpC == PPC::ANDIo8)
1826 NewOpC = MIOpC;
1827 else {
1828 NewOpC = PPC::getRecordFormOpcode(MIOpC);
1829 if (NewOpC == -1 && PPC::getNonRecordFormOpcode(MIOpC) != -1)
1830 NewOpC = MIOpC;
1831 }
1832
1833 // FIXME: On the non-embedded POWER architectures, only some of the record
1834 // forms are fast, and we should use only the fast ones.
1835
1836 // The defining instruction has a record form (or is already a record
1837 // form). It is possible, however, that we'll need to reverse the condition
1838 // code of the users.
1839 if (NewOpC == -1)
1840 return false;
1841
1842 // If we have SUB(r1, r2) and CMP(r2, r1), the condition code based on CMP
1843 // needs to be updated to be based on SUB. Push the condition code
1844 // operands to OperandsToUpdate. If it is safe to remove CmpInstr, the
1845 // condition code of these operands will be modified.
1846 // Here, Value == 0 means we haven't converted comparison against 1 or -1 to
1847 // comparison against 0, which may modify predicate.
1848 bool ShouldSwap = false;
1849 if (Sub && Value == 0) {
1850 ShouldSwap = SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
1851 Sub->getOperand(2).getReg() == SrcReg;
1852
1853 // The operands to subf are the opposite of sub, so only in the fixed-point
1854 // case, invert the order.
1855 ShouldSwap = !ShouldSwap;
1856 }
1857
1858 if (ShouldSwap)
1859 for (MachineRegisterInfo::use_instr_iterator
1860 I = MRI->use_instr_begin(CRReg), IE = MRI->use_instr_end();
1861 I != IE; ++I) {
1862 MachineInstr *UseMI = &*I;
1863 if (UseMI->getOpcode() == PPC::BCC) {
1864 PPC::Predicate Pred = (PPC::Predicate) UseMI->getOperand(0).getImm();
1865 unsigned PredCond = PPC::getPredicateCondition(Pred);
1866 assert((!equalityOnly ||(static_cast <bool> ((!equalityOnly || PredCond == PPC::
PRED_EQ || PredCond == PPC::PRED_NE) && "Invalid predicate for equality-only optimization"
) ? void (0) : __assert_fail ("(!equalityOnly || PredCond == PPC::PRED_EQ || PredCond == PPC::PRED_NE) && \"Invalid predicate for equality-only optimization\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 1868, __extension__ __PRETTY_FUNCTION__))
1867 PredCond == PPC::PRED_EQ || PredCond == PPC::PRED_NE) &&(static_cast <bool> ((!equalityOnly || PredCond == PPC::
PRED_EQ || PredCond == PPC::PRED_NE) && "Invalid predicate for equality-only optimization"
) ? void (0) : __assert_fail ("(!equalityOnly || PredCond == PPC::PRED_EQ || PredCond == PPC::PRED_NE) && \"Invalid predicate for equality-only optimization\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 1868, __extension__ __PRETTY_FUNCTION__))
1868 "Invalid predicate for equality-only optimization")(static_cast <bool> ((!equalityOnly || PredCond == PPC::
PRED_EQ || PredCond == PPC::PRED_NE) && "Invalid predicate for equality-only optimization"
) ? void (0) : __assert_fail ("(!equalityOnly || PredCond == PPC::PRED_EQ || PredCond == PPC::PRED_NE) && \"Invalid predicate for equality-only optimization\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 1868, __extension__ __PRETTY_FUNCTION__))
;
1869 (void)PredCond; // To suppress warning in release build.
1870 PredsToUpdate.push_back(std::make_pair(&(UseMI->getOperand(0)),
1871 PPC::getSwappedPredicate(Pred)));
1872 } else if (UseMI->getOpcode() == PPC::ISEL ||
1873 UseMI->getOpcode() == PPC::ISEL8) {
1874 unsigned NewSubReg = UseMI->getOperand(3).getSubReg();
1875 assert((!equalityOnly || NewSubReg == PPC::sub_eq) &&(static_cast <bool> ((!equalityOnly || NewSubReg == PPC
::sub_eq) && "Invalid CR bit for equality-only optimization"
) ? void (0) : __assert_fail ("(!equalityOnly || NewSubReg == PPC::sub_eq) && \"Invalid CR bit for equality-only optimization\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 1876, __extension__ __PRETTY_FUNCTION__))
1876 "Invalid CR bit for equality-only optimization")(static_cast <bool> ((!equalityOnly || NewSubReg == PPC
::sub_eq) && "Invalid CR bit for equality-only optimization"
) ? void (0) : __assert_fail ("(!equalityOnly || NewSubReg == PPC::sub_eq) && \"Invalid CR bit for equality-only optimization\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 1876, __extension__ __PRETTY_FUNCTION__))
;
1877
1878 if (NewSubReg == PPC::sub_lt)
1879 NewSubReg = PPC::sub_gt;
1880 else if (NewSubReg == PPC::sub_gt)
1881 NewSubReg = PPC::sub_lt;
1882
1883 SubRegsToUpdate.push_back(std::make_pair(&(UseMI->getOperand(3)),
1884 NewSubReg));
1885 } else // We need to abort on a user we don't understand.
1886 return false;
1887 }
1888 assert(!(Value != 0 && ShouldSwap) &&(static_cast <bool> (!(Value != 0 && ShouldSwap
) && "Non-zero immediate support and ShouldSwap" "may conflict in updating predicate"
) ? void (0) : __assert_fail ("!(Value != 0 && ShouldSwap) && \"Non-zero immediate support and ShouldSwap\" \"may conflict in updating predicate\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 1890, __extension__ __PRETTY_FUNCTION__))
1889 "Non-zero immediate support and ShouldSwap"(static_cast <bool> (!(Value != 0 && ShouldSwap
) && "Non-zero immediate support and ShouldSwap" "may conflict in updating predicate"
) ? void (0) : __assert_fail ("!(Value != 0 && ShouldSwap) && \"Non-zero immediate support and ShouldSwap\" \"may conflict in updating predicate\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 1890, __extension__ __PRETTY_FUNCTION__))
1890 "may conflict in updating predicate")(static_cast <bool> (!(Value != 0 && ShouldSwap
) && "Non-zero immediate support and ShouldSwap" "may conflict in updating predicate"
) ? void (0) : __assert_fail ("!(Value != 0 && ShouldSwap) && \"Non-zero immediate support and ShouldSwap\" \"may conflict in updating predicate\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 1890, __extension__ __PRETTY_FUNCTION__))
;
1891
1892 // Create a new virtual register to hold the value of the CR set by the
1893 // record-form instruction. If the instruction was not previously in
1894 // record form, then set the kill flag on the CR.
1895 CmpInstr.eraseFromParent();
1896
1897 MachineBasicBlock::iterator MII = MI;
1898 BuildMI(*MI->getParent(), std::next(MII), MI->getDebugLoc(),
1899 get(TargetOpcode::COPY), CRReg)
1900 .addReg(PPC::CR0, MIOpC != NewOpC ? RegState::Kill : 0);
1901
1902 // Even if CR0 register were dead before, it is alive now since the
1903 // instruction we just built uses it.
1904 MI->clearRegisterDeads(PPC::CR0);
1905
1906 if (MIOpC != NewOpC) {
1907 // We need to be careful here: we're replacing one instruction with
1908 // another, and we need to make sure that we get all of the right
1909 // implicit uses and defs. On the other hand, the caller may be holding
1910 // an iterator to this instruction, and so we can't delete it (this is
1911 // specifically the case if this is the instruction directly after the
1912 // compare).
1913
1914 // Rotates are expensive instructions. If we're emitting a record-form
1915 // rotate that can just be an andi, we should just emit the andi.
1916 if ((MIOpC == PPC::RLWINM || MIOpC == PPC::RLWINM8) &&
1917 MI->getOperand(2).getImm() == 0) {
1918 int64_t MB = MI->getOperand(3).getImm();
1919 int64_t ME = MI->getOperand(4).getImm();
1920 if (MB < ME && MB >= 16) {
1921 uint64_t Mask = ((1LLU << (32 - MB)) - 1) & ~((1LLU << (31 - ME)) - 1);
1922 NewOpC = MIOpC == PPC::RLWINM ? PPC::ANDIo : PPC::ANDIo8;
1923 MI->RemoveOperand(4);
1924 MI->RemoveOperand(3);
1925 MI->getOperand(2).setImm(Mask);
1926 NumRcRotatesConvertedToRcAnd++;
1927 }
1928 } else if (MIOpC == PPC::RLDICL && MI->getOperand(2).getImm() == 0) {
1929 int64_t MB = MI->getOperand(3).getImm();
1930 if (MB >= 48) {
1931 uint64_t Mask = (1LLU << (63 - MB + 1)) - 1;
1932 NewOpC = PPC::ANDIo8;
1933 MI->RemoveOperand(3);
1934 MI->getOperand(2).setImm(Mask);
1935 NumRcRotatesConvertedToRcAnd++;
1936 }
1937 }
1938
1939 const MCInstrDesc &NewDesc = get(NewOpC);
1940 MI->setDesc(NewDesc);
1941
1942 if (NewDesc.ImplicitDefs)
1943 for (const MCPhysReg *ImpDefs = NewDesc.getImplicitDefs();
1944 *ImpDefs; ++ImpDefs)
1945 if (!MI->definesRegister(*ImpDefs))
1946 MI->addOperand(*MI->getParent()->getParent(),
1947 MachineOperand::CreateReg(*ImpDefs, true, true));
1948 if (NewDesc.ImplicitUses)
1949 for (const MCPhysReg *ImpUses = NewDesc.getImplicitUses();
1950 *ImpUses; ++ImpUses)
1951 if (!MI->readsRegister(*ImpUses))
1952 MI->addOperand(*MI->getParent()->getParent(),
1953 MachineOperand::CreateReg(*ImpUses, false, true));
1954 }
1955 assert(MI->definesRegister(PPC::CR0) &&(static_cast <bool> (MI->definesRegister(PPC::CR0) &&
"Record-form instruction does not define cr0?") ? void (0) :
__assert_fail ("MI->definesRegister(PPC::CR0) && \"Record-form instruction does not define cr0?\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 1956, __extension__ __PRETTY_FUNCTION__))
1956 "Record-form instruction does not define cr0?")(static_cast <bool> (MI->definesRegister(PPC::CR0) &&
"Record-form instruction does not define cr0?") ? void (0) :
__assert_fail ("MI->definesRegister(PPC::CR0) && \"Record-form instruction does not define cr0?\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 1956, __extension__ __PRETTY_FUNCTION__))
;
1957
1958 // Modify the condition code of operands in OperandsToUpdate.
1959 // Since we have SUB(r1, r2) and CMP(r2, r1), the condition code needs to
1960 // be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
1961 for (unsigned i = 0, e = PredsToUpdate.size(); i < e; i++)
1962 PredsToUpdate[i].first->setImm(PredsToUpdate[i].second);
1963
1964 for (unsigned i = 0, e = SubRegsToUpdate.size(); i < e; i++)
1965 SubRegsToUpdate[i].first->setSubReg(SubRegsToUpdate[i].second);
1966
1967 return true;
1968}
1969
1970/// GetInstSize - Return the number of bytes of code the specified
1971/// instruction may be. This returns the maximum number of bytes.
1972///
1973unsigned PPCInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
1974 unsigned Opcode = MI.getOpcode();
1975
1976 if (Opcode == PPC::INLINEASM) {
1977 const MachineFunction *MF = MI.getParent()->getParent();
1978 const char *AsmStr = MI.getOperand(0).getSymbolName();
1979 return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
1980 } else if (Opcode == TargetOpcode::STACKMAP) {
1981 StackMapOpers Opers(&MI);
1982 return Opers.getNumPatchBytes();
1983 } else if (Opcode == TargetOpcode::PATCHPOINT) {
1984 PatchPointOpers Opers(&MI);
1985 return Opers.getNumPatchBytes();
1986 } else {
1987 return get(Opcode).getSize();
1988 }
1989}
1990
1991std::pair<unsigned, unsigned>
1992PPCInstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
1993 const unsigned Mask = PPCII::MO_ACCESS_MASK;
1994 return std::make_pair(TF & Mask, TF & ~Mask);
1995}
1996
1997ArrayRef<std::pair<unsigned, const char *>>
1998PPCInstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
1999 using namespace PPCII;
2000 static const std::pair<unsigned, const char *> TargetFlags[] = {
2001 {MO_LO, "ppc-lo"},
2002 {MO_HA, "ppc-ha"},
2003 {MO_TPREL_LO, "ppc-tprel-lo"},
2004 {MO_TPREL_HA, "ppc-tprel-ha"},
2005 {MO_DTPREL_LO, "ppc-dtprel-lo"},
2006 {MO_TLSLD_LO, "ppc-tlsld-lo"},
2007 {MO_TOC_LO, "ppc-toc-lo"},
2008 {MO_TLS, "ppc-tls"}};
2009 return makeArrayRef(TargetFlags);
2010}
2011
2012ArrayRef<std::pair<unsigned, const char *>>
2013PPCInstrInfo::getSerializableBitmaskMachineOperandTargetFlags() const {
2014 using namespace PPCII;
2015 static const std::pair<unsigned, const char *> TargetFlags[] = {
2016 {MO_PLT, "ppc-plt"},
2017 {MO_PIC_FLAG, "ppc-pic"},
2018 {MO_NLP_FLAG, "ppc-nlp"},
2019 {MO_NLP_HIDDEN_FLAG, "ppc-nlp-hidden"}};
2020 return makeArrayRef(TargetFlags);
2021}
2022
2023// Expand VSX Memory Pseudo instruction to either a VSX or a FP instruction.
2024// The VSX versions have the advantage of a full 64-register target whereas
2025// the FP ones have the advantage of lower latency and higher throughput. So
2026// what we are after is using the faster instructions in low register pressure
2027// situations and using the larger register file in high register pressure
2028// situations.
2029bool PPCInstrInfo::expandVSXMemPseudo(MachineInstr &MI) const {
2030 unsigned UpperOpcode, LowerOpcode;
2031 switch (MI.getOpcode()) {
2032 case PPC::DFLOADf32:
2033 UpperOpcode = PPC::LXSSP;
2034 LowerOpcode = PPC::LFS;
2035 break;
2036 case PPC::DFLOADf64:
2037 UpperOpcode = PPC::LXSD;
2038 LowerOpcode = PPC::LFD;
2039 break;
2040 case PPC::DFSTOREf32:
2041 UpperOpcode = PPC::STXSSP;
2042 LowerOpcode = PPC::STFS;
2043 break;
2044 case PPC::DFSTOREf64:
2045 UpperOpcode = PPC::STXSD;
2046 LowerOpcode = PPC::STFD;
2047 break;
2048 case PPC::XFLOADf32:
2049 UpperOpcode = PPC::LXSSPX;
2050 LowerOpcode = PPC::LFSX;
2051 break;
2052 case PPC::XFLOADf64:
2053 UpperOpcode = PPC::LXSDX;
2054 LowerOpcode = PPC::LFDX;
2055 break;
2056 case PPC::XFSTOREf32:
2057 UpperOpcode = PPC::STXSSPX;
2058 LowerOpcode = PPC::STFSX;
2059 break;
2060 case PPC::XFSTOREf64:
2061 UpperOpcode = PPC::STXSDX;
2062 LowerOpcode = PPC::STFDX;
2063 break;
2064 case PPC::LIWAX:
2065 UpperOpcode = PPC::LXSIWAX;
2066 LowerOpcode = PPC::LFIWAX;
2067 break;
2068 case PPC::LIWZX:
2069 UpperOpcode = PPC::LXSIWZX;
2070 LowerOpcode = PPC::LFIWZX;
2071 break;
2072 case PPC::STIWX:
2073 UpperOpcode = PPC::STXSIWX;
2074 LowerOpcode = PPC::STFIWX;
2075 break;
2076 default:
2077 llvm_unreachable("Unknown Operation!")::llvm::llvm_unreachable_internal("Unknown Operation!", "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 2077)
;
2078 }
2079
2080 unsigned TargetReg = MI.getOperand(0).getReg();
2081 unsigned Opcode;
2082 if ((TargetReg >= PPC::F0 && TargetReg <= PPC::F31) ||
2083 (TargetReg >= PPC::VSL0 && TargetReg <= PPC::VSL31))
2084 Opcode = LowerOpcode;
2085 else
2086 Opcode = UpperOpcode;
2087 MI.setDesc(get(Opcode));
2088 return true;
2089}
2090
2091#ifndef NDEBUG
2092static bool isAnImmediateOperand(const MachineOperand &MO) {
2093 return MO.isCPI() || MO.isGlobal() || MO.isImm();
2094}
2095#endif
2096
2097bool PPCInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
2098 auto &MBB = *MI.getParent();
2099 auto DL = MI.getDebugLoc();
2100
2101 switch (MI.getOpcode()) {
2102 case TargetOpcode::LOAD_STACK_GUARD: {
2103 assert(Subtarget.isTargetLinux() &&(static_cast <bool> (Subtarget.isTargetLinux() &&
"Only Linux target is expected to contain LOAD_STACK_GUARD")
? void (0) : __assert_fail ("Subtarget.isTargetLinux() && \"Only Linux target is expected to contain LOAD_STACK_GUARD\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 2104, __extension__ __PRETTY_FUNCTION__))
2104 "Only Linux target is expected to contain LOAD_STACK_GUARD")(static_cast <bool> (Subtarget.isTargetLinux() &&
"Only Linux target is expected to contain LOAD_STACK_GUARD")
? void (0) : __assert_fail ("Subtarget.isTargetLinux() && \"Only Linux target is expected to contain LOAD_STACK_GUARD\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 2104, __extension__ __PRETTY_FUNCTION__))
;
2105 const int64_t Offset = Subtarget.isPPC64() ? -0x7010 : -0x7008;
2106 const unsigned Reg = Subtarget.isPPC64() ? PPC::X13 : PPC::R2;
2107 MI.setDesc(get(Subtarget.isPPC64() ? PPC::LD : PPC::LWZ));
2108 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
2109 .addImm(Offset)
2110 .addReg(Reg);
2111 return true;
2112 }
2113 case PPC::DFLOADf32:
2114 case PPC::DFLOADf64:
2115 case PPC::DFSTOREf32:
2116 case PPC::DFSTOREf64: {
2117 assert(Subtarget.hasP9Vector() &&(static_cast <bool> (Subtarget.hasP9Vector() &&
"Invalid D-Form Pseudo-ops on Pre-P9 target.") ? void (0) : __assert_fail
("Subtarget.hasP9Vector() && \"Invalid D-Form Pseudo-ops on Pre-P9 target.\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 2118, __extension__ __PRETTY_FUNCTION__))
2118 "Invalid D-Form Pseudo-ops on Pre-P9 target.")(static_cast <bool> (Subtarget.hasP9Vector() &&
"Invalid D-Form Pseudo-ops on Pre-P9 target.") ? void (0) : __assert_fail
("Subtarget.hasP9Vector() && \"Invalid D-Form Pseudo-ops on Pre-P9 target.\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 2118, __extension__ __PRETTY_FUNCTION__))
;
2119 assert(MI.getOperand(2).isReg() &&(static_cast <bool> (MI.getOperand(2).isReg() &&
isAnImmediateOperand(MI.getOperand(1)) && "D-form op must have register and immediate operands"
) ? void (0) : __assert_fail ("MI.getOperand(2).isReg() && isAnImmediateOperand(MI.getOperand(1)) && \"D-form op must have register and immediate operands\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 2121, __extension__ __PRETTY_FUNCTION__))
2120 isAnImmediateOperand(MI.getOperand(1)) &&(static_cast <bool> (MI.getOperand(2).isReg() &&
isAnImmediateOperand(MI.getOperand(1)) && "D-form op must have register and immediate operands"
) ? void (0) : __assert_fail ("MI.getOperand(2).isReg() && isAnImmediateOperand(MI.getOperand(1)) && \"D-form op must have register and immediate operands\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 2121, __extension__ __PRETTY_FUNCTION__))
2121 "D-form op must have register and immediate operands")(static_cast <bool> (MI.getOperand(2).isReg() &&
isAnImmediateOperand(MI.getOperand(1)) && "D-form op must have register and immediate operands"
) ? void (0) : __assert_fail ("MI.getOperand(2).isReg() && isAnImmediateOperand(MI.getOperand(1)) && \"D-form op must have register and immediate operands\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 2121, __extension__ __PRETTY_FUNCTION__))
;
2122 return expandVSXMemPseudo(MI);
2123 }
2124 case PPC::XFLOADf32:
2125 case PPC::XFSTOREf32:
2126 case PPC::LIWAX:
2127 case PPC::LIWZX:
2128 case PPC::STIWX: {
2129 assert(Subtarget.hasP8Vector() &&(static_cast <bool> (Subtarget.hasP8Vector() &&
"Invalid X-Form Pseudo-ops on Pre-P8 target.") ? void (0) : __assert_fail
("Subtarget.hasP8Vector() && \"Invalid X-Form Pseudo-ops on Pre-P8 target.\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 2130, __extension__ __PRETTY_FUNCTION__))
2130 "Invalid X-Form Pseudo-ops on Pre-P8 target.")(static_cast <bool> (Subtarget.hasP8Vector() &&
"Invalid X-Form Pseudo-ops on Pre-P8 target.") ? void (0) : __assert_fail
("Subtarget.hasP8Vector() && \"Invalid X-Form Pseudo-ops on Pre-P8 target.\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 2130, __extension__ __PRETTY_FUNCTION__))
;
2131 assert(MI.getOperand(2).isReg() && MI.getOperand(1).isReg() &&(static_cast <bool> (MI.getOperand(2).isReg() &&
MI.getOperand(1).isReg() && "X-form op must have register and register operands"
) ? void (0) : __assert_fail ("MI.getOperand(2).isReg() && MI.getOperand(1).isReg() && \"X-form op must have register and register operands\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 2132, __extension__ __PRETTY_FUNCTION__))
2132 "X-form op must have register and register operands")(static_cast <bool> (MI.getOperand(2).isReg() &&
MI.getOperand(1).isReg() && "X-form op must have register and register operands"
) ? void (0) : __assert_fail ("MI.getOperand(2).isReg() && MI.getOperand(1).isReg() && \"X-form op must have register and register operands\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 2132, __extension__ __PRETTY_FUNCTION__))
;
2133 return expandVSXMemPseudo(MI);
2134 }
2135 case PPC::XFLOADf64:
2136 case PPC::XFSTOREf64: {
2137 assert(Subtarget.hasVSX() &&(static_cast <bool> (Subtarget.hasVSX() && "Invalid X-Form Pseudo-ops on target that has no VSX."
) ? void (0) : __assert_fail ("Subtarget.hasVSX() && \"Invalid X-Form Pseudo-ops on target that has no VSX.\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 2138, __extension__ __PRETTY_FUNCTION__))
2138 "Invalid X-Form Pseudo-ops on target that has no VSX.")(static_cast <bool> (Subtarget.hasVSX() && "Invalid X-Form Pseudo-ops on target that has no VSX."
) ? void (0) : __assert_fail ("Subtarget.hasVSX() && \"Invalid X-Form Pseudo-ops on target that has no VSX.\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 2138, __extension__ __PRETTY_FUNCTION__))
;
2139 assert(MI.getOperand(2).isReg() && MI.getOperand(1).isReg() &&(static_cast <bool> (MI.getOperand(2).isReg() &&
MI.getOperand(1).isReg() && "X-form op must have register and register operands"
) ? void (0) : __assert_fail ("MI.getOperand(2).isReg() && MI.getOperand(1).isReg() && \"X-form op must have register and register operands\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 2140, __extension__ __PRETTY_FUNCTION__))
2140 "X-form op must have register and register operands")(static_cast <bool> (MI.getOperand(2).isReg() &&
MI.getOperand(1).isReg() && "X-form op must have register and register operands"
) ? void (0) : __assert_fail ("MI.getOperand(2).isReg() && MI.getOperand(1).isReg() && \"X-form op must have register and register operands\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 2140, __extension__ __PRETTY_FUNCTION__))
;
2141 return expandVSXMemPseudo(MI);
2142 }
2143 case PPC::SPILLTOVSR_LD: {
2144 unsigned TargetReg = MI.getOperand(0).getReg();
2145 if (PPC::VSFRCRegClass.contains(TargetReg)) {
2146 MI.setDesc(get(PPC::DFLOADf64));
2147 return expandPostRAPseudo(MI);
2148 }
2149 else
2150 MI.setDesc(get(PPC::LD));
2151 return true;
2152 }
2153 case PPC::SPILLTOVSR_ST: {
2154 unsigned SrcReg = MI.getOperand(0).getReg();
2155 if (PPC::VSFRCRegClass.contains(SrcReg)) {
2156 NumStoreSPILLVSRRCAsVec++;
2157 MI.setDesc(get(PPC::DFSTOREf64));
2158 return expandPostRAPseudo(MI);
2159 } else {
2160 NumStoreSPILLVSRRCAsGpr++;
2161 MI.setDesc(get(PPC::STD));
2162 }
2163 return true;
2164 }
2165 case PPC::SPILLTOVSR_LDX: {
2166 unsigned TargetReg = MI.getOperand(0).getReg();
2167 if (PPC::VSFRCRegClass.contains(TargetReg))
2168 MI.setDesc(get(PPC::LXSDX));
2169 else
2170 MI.setDesc(get(PPC::LDX));
2171 return true;
2172 }
2173 case PPC::SPILLTOVSR_STX: {
2174 unsigned SrcReg = MI.getOperand(0).getReg();
2175 if (PPC::VSFRCRegClass.contains(SrcReg)) {
2176 NumStoreSPILLVSRRCAsVec++;
2177 MI.setDesc(get(PPC::STXSDX));
2178 } else {
2179 NumStoreSPILLVSRRCAsGpr++;
2180 MI.setDesc(get(PPC::STDX));
2181 }
2182 return true;
2183 }
2184
2185 case PPC::CFENCE8: {
2186 auto Val = MI.getOperand(0).getReg();
2187 BuildMI(MBB, MI, DL, get(PPC::CMPD), PPC::CR7).addReg(Val).addReg(Val);
2188 BuildMI(MBB, MI, DL, get(PPC::CTRL_DEP))
2189 .addImm(PPC::PRED_NE_MINUS)
2190 .addReg(PPC::CR7)
2191 .addImm(1);
2192 MI.setDesc(get(PPC::ISYNC));
2193 MI.RemoveOperand(0);
2194 return true;
2195 }
2196 }
2197 return false;
2198}
2199
2200// Essentially a compile-time implementation of a compare->isel sequence.
2201// It takes two constants to compare, along with the true/false registers
2202// and the comparison type (as a subreg to a CR field) and returns one
2203// of the true/false registers, depending on the comparison results.
2204static unsigned selectReg(int64_t Imm1, int64_t Imm2, unsigned CompareOpc,
2205 unsigned TrueReg, unsigned FalseReg,
2206 unsigned CRSubReg) {
2207 // Signed comparisons. The immediates are assumed to be sign-extended.
2208 if (CompareOpc == PPC::CMPWI || CompareOpc == PPC::CMPDI) {
2209 switch (CRSubReg) {
2210 default: llvm_unreachable("Unknown integer comparison type.")::llvm::llvm_unreachable_internal("Unknown integer comparison type."
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 2210)
;
2211 case PPC::sub_lt:
2212 return Imm1 < Imm2 ? TrueReg : FalseReg;
2213 case PPC::sub_gt:
2214 return Imm1 > Imm2 ? TrueReg : FalseReg;
2215 case PPC::sub_eq:
2216 return Imm1 == Imm2 ? TrueReg : FalseReg;
2217 }
2218 }
2219 // Unsigned comparisons.
2220 else if (CompareOpc == PPC::CMPLWI || CompareOpc == PPC::CMPLDI) {
2221 switch (CRSubReg) {
2222 default: llvm_unreachable("Unknown integer comparison type.")::llvm::llvm_unreachable_internal("Unknown integer comparison type."
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 2222)
;
2223 case PPC::sub_lt:
2224 return (uint64_t)Imm1 < (uint64_t)Imm2 ? TrueReg : FalseReg;
2225 case PPC::sub_gt:
2226 return (uint64_t)Imm1 > (uint64_t)Imm2 ? TrueReg : FalseReg;
2227 case PPC::sub_eq:
2228 return Imm1 == Imm2 ? TrueReg : FalseReg;
2229 }
2230 }
2231 return PPC::NoRegister;
2232}
2233
2234// Replace an instruction with one that materializes a constant (and sets
2235// CR0 if the original instruction was a record-form instruction).
2236void PPCInstrInfo::replaceInstrWithLI(MachineInstr &MI,
2237 const LoadImmediateInfo &LII) const {
2238 // Remove existing operands.
2239 int OperandToKeep = LII.SetCR ? 1 : 0;
2240 for (int i = MI.getNumOperands() - 1; i > OperandToKeep; i--)
2241 MI.RemoveOperand(i);
2242
2243 // Replace the instruction.
2244 if (LII.SetCR) {
2245 MI.setDesc(get(LII.Is64Bit ? PPC::ANDIo8 : PPC::ANDIo));
2246 // Set the immediate.
2247 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
2248 .addImm(LII.Imm).addReg(PPC::CR0, RegState::ImplicitDefine);
2249 return;
2250 }
2251 else
2252 MI.setDesc(get(LII.Is64Bit ? PPC::LI8 : PPC::LI));
2253
2254 // Set the immediate.
2255 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
2256 .addImm(LII.Imm);
2257}
2258
2259MachineInstr *PPCInstrInfo::getConstantDefMI(MachineInstr &MI,
2260 unsigned &ConstOp,
2261 bool &SeenIntermediateUse) const {
2262 ConstOp = ~0U;
2263 MachineInstr *DefMI = nullptr;
2264 MachineRegisterInfo *MRI = &MI.getParent()->getParent()->getRegInfo();
2265 const TargetRegisterInfo *TRI = &getRegisterInfo();
2266 // If we're in SSA, get the defs through the MRI. Otherwise, only look
2267 // within the basic block to see if the register is defined using an LI/LI8.
2268 if (MRI->isSSA()) {
2269 for (int i = 1, e = MI.getNumOperands(); i < e; i++) {
2270 if (!MI.getOperand(i).isReg())
2271 continue;
2272 unsigned Reg = MI.getOperand(i).getReg();
2273 if (!TargetRegisterInfo::isVirtualRegister(Reg))
2274 continue;
2275 unsigned TrueReg = TRI->lookThruCopyLike(Reg, MRI);
2276 if (TargetRegisterInfo::isVirtualRegister(TrueReg)) {
2277 DefMI = MRI->getVRegDef(TrueReg);
2278 if (DefMI->getOpcode() == PPC::LI || DefMI->getOpcode() == PPC::LI8) {
2279 ConstOp = i;
2280 break;
2281 }
2282 }
2283 }
2284 } else {
2285 // Looking back through the definition for each operand could be expensive,
2286 // so exit early if this isn't an instruction that either has an immediate
2287 // form or is already an immediate form that we can handle.
2288 ImmInstrInfo III;
2289 unsigned Opc = MI.getOpcode();
2290 bool ConvertibleImmForm =
2291 Opc == PPC::CMPWI || Opc == PPC::CMPLWI ||
2292 Opc == PPC::CMPDI || Opc == PPC::CMPLDI ||
2293 Opc == PPC::ADDI || Opc == PPC::ADDI8 ||
2294 Opc == PPC::ORI || Opc == PPC::ORI8 ||
2295 Opc == PPC::XORI || Opc == PPC::XORI8 ||
2296 Opc == PPC::RLDICL || Opc == PPC::RLDICLo ||
2297 Opc == PPC::RLDICL_32 || Opc == PPC::RLDICL_32_64 ||
2298 Opc == PPC::RLWINM || Opc == PPC::RLWINMo ||
2299 Opc == PPC::RLWINM8 || Opc == PPC::RLWINM8o;
2300 if (!instrHasImmForm(MI, III) && !ConvertibleImmForm)
2301 return nullptr;
2302
2303 // Don't convert or %X, %Y, %Y since that's just a register move.
2304 if ((Opc == PPC::OR || Opc == PPC::OR8) &&
2305 MI.getOperand(1).getReg() == MI.getOperand(2).getReg())
2306 return nullptr;
2307 for (int i = 1, e = MI.getNumOperands(); i < e; i++) {
2308 MachineOperand &MO = MI.getOperand(i);
2309 SeenIntermediateUse = false;
2310 if (MO.isReg() && MO.isUse() && !MO.isImplicit()) {
2311 MachineBasicBlock::reverse_iterator E = MI.getParent()->rend(), It = MI;
2312 It++;
2313 unsigned Reg = MI.getOperand(i).getReg();
2314 // MachineInstr::readsRegister only returns true if the machine
2315 // instruction reads the exact register or its super-register. It
2316 // does not consider uses of sub-registers which seems like strange
2317 // behaviour. Nonetheless, if we end up with a 64-bit register here,
2318 // get the corresponding 32-bit register to check.
2319 if (PPC::G8RCRegClass.contains(Reg))
2320 Reg = Reg - PPC::X0 + PPC::R0;
2321
2322 // Is this register defined by a load-immediate in this block?
2323 for ( ; It != E; ++It) {
2324 if (It->modifiesRegister(Reg, &getRegisterInfo())) {
2325 if (It->getOpcode() == PPC::LI || It->getOpcode() == PPC::LI8) {
2326 ConstOp = i;
2327 return &*It;
2328 } else
2329 break;
2330 } else if (It->readsRegister(Reg, &getRegisterInfo()))
2331 // If we see another use of this reg between the def and the MI,
2332 // we want to flat it so the def isn't deleted.
2333 SeenIntermediateUse = true;
2334 }
2335 }
2336 }
2337 }
2338 return ConstOp == ~0U ? nullptr : DefMI;
2339}
2340
2341const unsigned *PPCInstrInfo::getStoreOpcodesForSpillArray() const {
2342 static const unsigned OpcodesForSpill[2][SOK_LastOpcodeSpill] = {
2343 // Power 8
2344 {PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR,
2345 PPC::SPILL_CRBIT, PPC::STVX, PPC::STXVD2X, PPC::STXSDX, PPC::STXSSPX,
2346 PPC::SPILL_VRSAVE, PPC::QVSTFDX, PPC::QVSTFSXs, PPC::QVSTFDXb,
2347 PPC::SPILLTOVSR_ST, PPC::EVSTDD, PPC::SPESTW},
2348 // Power 9
2349 {PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR,
2350 PPC::SPILL_CRBIT, PPC::STVX, PPC::STXV, PPC::DFSTOREf64, PPC::DFSTOREf32,
2351 PPC::SPILL_VRSAVE, PPC::QVSTFDX, PPC::QVSTFSXs, PPC::QVSTFDXb,
2352 PPC::SPILLTOVSR_ST}};
2353
2354 return OpcodesForSpill[(Subtarget.hasP9Vector()) ? 1 : 0];
2355}
2356
2357const unsigned *PPCInstrInfo::getLoadOpcodesForSpillArray() const {
2358 static const unsigned OpcodesForSpill[2][SOK_LastOpcodeSpill] = {
2359 // Power 8
2360 {PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR,
2361 PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXVD2X, PPC::LXSDX, PPC::LXSSPX,
2362 PPC::RESTORE_VRSAVE, PPC::QVLFDX, PPC::QVLFSXs, PPC::QVLFDXb,
2363 PPC::SPILLTOVSR_LD, PPC::EVLDD, PPC::SPELWZ},
2364 // Power 9
2365 {PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR,
2366 PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXV, PPC::DFLOADf64, PPC::DFLOADf32,
2367 PPC::RESTORE_VRSAVE, PPC::QVLFDX, PPC::QVLFSXs, PPC::QVLFDXb,
2368 PPC::SPILLTOVSR_LD}};
2369
2370 return OpcodesForSpill[(Subtarget.hasP9Vector()) ? 1 : 0];
2371}
2372
2373// If this instruction has an immediate form and one of its operands is a
2374// result of a load-immediate, convert it to the immediate form if the constant
2375// is in range.
2376bool PPCInstrInfo::convertToImmediateForm(MachineInstr &MI,
2377 MachineInstr **KilledDef) const {
2378 MachineFunction *MF = MI.getParent()->getParent();
2379 MachineRegisterInfo *MRI = &MF->getRegInfo();
2380 bool PostRA = !MRI->isSSA();
2381 bool SeenIntermediateUse = true;
2382 unsigned ConstantOperand = ~0U;
2383 MachineInstr *DefMI = getConstantDefMI(MI, ConstantOperand,
2384 SeenIntermediateUse);
2385 if (!DefMI || !DefMI->getOperand(1).isImm())
2386 return false;
2387 assert(ConstantOperand < MI.getNumOperands() &&(static_cast <bool> (ConstantOperand < MI.getNumOperands
() && "The constant operand needs to be valid at this point"
) ? void (0) : __assert_fail ("ConstantOperand < MI.getNumOperands() && \"The constant operand needs to be valid at this point\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 2388, __extension__ __PRETTY_FUNCTION__))
2388 "The constant operand needs to be valid at this point")(static_cast <bool> (ConstantOperand < MI.getNumOperands
() && "The constant operand needs to be valid at this point"
) ? void (0) : __assert_fail ("ConstantOperand < MI.getNumOperands() && \"The constant operand needs to be valid at this point\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 2388, __extension__ __PRETTY_FUNCTION__))
;
2389
2390 int64_t Immediate = DefMI->getOperand(1).getImm();
2391 // Sign-extend to 64-bits.
2392 int64_t SExtImm = ((uint64_t)Immediate & ~0x7FFFuLL) != 0 ?
2393 (Immediate | 0xFFFFFFFFFFFF0000) : Immediate;
2394
2395 if (KilledDef && MI.getOperand(ConstantOperand).isKill() &&
2396 !SeenIntermediateUse)
2397 *KilledDef = DefMI;
2398
2399 // If this is a reg+reg instruction that has a reg+imm form, convert it now.
2400 ImmInstrInfo III;
2401 if (instrHasImmForm(MI, III))
2402 return transformToImmForm(MI, III, ConstantOperand, SExtImm);
2403
2404 bool ReplaceWithLI = false;
2405 bool Is64BitLI = false;
2406 int64_t NewImm = 0;
2407 bool SetCR = false;
2408 unsigned Opc = MI.getOpcode();
2409 switch (Opc) {
2410 default: return false;
2411
2412 // FIXME: Any branches conditional on such a comparison can be made
2413 // unconditional. At this time, this happens too infrequently to be worth
2414 // the implementation effort, but if that ever changes, we could convert
2415 // such a pattern here.
2416 case PPC::CMPWI:
2417 case PPC::CMPLWI:
2418 case PPC::CMPDI:
2419 case PPC::CMPLDI: {
2420 // Doing this post-RA would require dataflow analysis to reliably find uses
2421 // of the CR register set by the compare.
2422 if (PostRA)
2423 return false;
2424 // If a compare-immediate is fed by an immediate and is itself an input of
2425 // an ISEL (the most common case) into a COPY of the correct register.
2426 bool Changed = false;
2427 unsigned DefReg = MI.getOperand(0).getReg();
2428 int64_t Comparand = MI.getOperand(2).getImm();
2429 int64_t SExtComparand = ((uint64_t)Comparand & ~0x7FFFuLL) != 0 ?
2430 (Comparand | 0xFFFFFFFFFFFF0000) : Comparand;
2431
2432 for (auto &CompareUseMI : MRI->use_instructions(DefReg)) {
2433 unsigned UseOpc = CompareUseMI.getOpcode();
2434 if (UseOpc != PPC::ISEL && UseOpc != PPC::ISEL8)
2435 continue;
2436 unsigned CRSubReg = CompareUseMI.getOperand(3).getSubReg();
2437 unsigned TrueReg = CompareUseMI.getOperand(1).getReg();
2438 unsigned FalseReg = CompareUseMI.getOperand(2).getReg();
2439 unsigned RegToCopy = selectReg(SExtImm, SExtComparand, Opc, TrueReg,
2440 FalseReg, CRSubReg);
2441 if (RegToCopy == PPC::NoRegister)
2442 continue;
2443 // Can't use PPC::COPY to copy PPC::ZERO[8]. Convert it to LI[8] 0.
2444 if (RegToCopy == PPC::ZERO || RegToCopy == PPC::ZERO8) {
2445 CompareUseMI.setDesc(get(UseOpc == PPC::ISEL8 ? PPC::LI8 : PPC::LI));
2446 CompareUseMI.getOperand(1).ChangeToImmediate(0);
2447 CompareUseMI.RemoveOperand(3);
2448 CompareUseMI.RemoveOperand(2);
2449 continue;
2450 }
2451 LLVM_DEBUG(do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("ppc-instr-info")) { dbgs() << "Found LI -> CMPI -> ISEL, replacing with a copy.\n"
; } } while (false)
2452 dbgs() << "Found LI -> CMPI -> ISEL, replacing with a copy.\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("ppc-instr-info")) { dbgs() << "Found LI -> CMPI -> ISEL, replacing with a copy.\n"
; } } while (false)
;
2453 LLVM_DEBUG(DefMI->dump(); MI.dump(); CompareUseMI.dump())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("ppc-instr-info")) { DefMI->dump(); MI.dump(); CompareUseMI
.dump(); } } while (false)
;
2454 LLVM_DEBUG(dbgs() << "Is converted to:\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("ppc-instr-info")) { dbgs() << "Is converted to:\n"; }
} while (false)
;
2455 // Convert to copy and remove unneeded operands.
2456 CompareUseMI.setDesc(get(PPC::COPY));
2457 CompareUseMI.RemoveOperand(3);
2458 CompareUseMI.RemoveOperand(RegToCopy == TrueReg ? 2 : 1);
2459 CmpIselsConverted++;
2460 Changed = true;
2461 LLVM_DEBUG(CompareUseMI.dump())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("ppc-instr-info")) { CompareUseMI.dump(); } } while (false)
;
2462 }
2463 if (Changed)
2464 return true;
2465 // This may end up incremented multiple times since this function is called
2466 // during a fixed-point transformation, but it is only meant to indicate the
2467 // presence of this opportunity.
2468 MissedConvertibleImmediateInstrs++;
2469 return false;
2470 }
2471
2472 // Immediate forms - may simply be convertable to an LI.
2473 case PPC::ADDI:
2474 case PPC::ADDI8: {
2475 // Does the sum fit in a 16-bit signed field?
2476 int64_t Addend = MI.getOperand(2).getImm();
2477 if (isInt<16>(Addend + SExtImm)) {
2478 ReplaceWithLI = true;
2479 Is64BitLI = Opc == PPC::ADDI8;
2480 NewImm = Addend + SExtImm;
2481 break;
2482 }
2483 return false;
2484 }
2485 case PPC::RLDICL:
2486 case PPC::RLDICLo:
2487 case PPC::RLDICL_32:
2488 case PPC::RLDICL_32_64: {
2489 // Use APInt's rotate function.
2490 int64_t SH = MI.getOperand(2).getImm();
2491 int64_t MB = MI.getOperand(3).getImm();
2492 APInt InVal((Opc == PPC::RLDICL || Opc == PPC::RLDICLo) ?
2493 64 : 32, SExtImm, true);
2494 InVal = InVal.rotl(SH);
2495 uint64_t Mask = (1LLU << (63 - MB + 1)) - 1;
2496 InVal &= Mask;
2497 // Can't replace negative values with an LI as that will sign-extend
2498 // and not clear the left bits. If we're setting the CR bit, we will use
2499 // ANDIo which won't sign extend, so that's safe.
2500 if (isUInt<15>(InVal.getSExtValue()) ||
2501 (Opc == PPC::RLDICLo && isUInt<16>(InVal.getSExtValue()))) {
2502 ReplaceWithLI = true;
2503 Is64BitLI = Opc != PPC::RLDICL_32;
2504 NewImm = InVal.getSExtValue();
2505 SetCR = Opc == PPC::RLDICLo;
2506 break;
2507 }
2508 return false;
2509 }
2510 case PPC::RLWINM:
2511 case PPC::RLWINM8:
2512 case PPC::RLWINMo:
2513 case PPC::RLWINM8o: {
2514 int64_t SH = MI.getOperand(2).getImm();
2515 int64_t MB = MI.getOperand(3).getImm();
2516 int64_t ME = MI.getOperand(4).getImm();
2517 APInt InVal(32, SExtImm, true);
2518 InVal = InVal.rotl(SH);
2519 // Set the bits ( MB + 32 ) to ( ME + 32 ).
2520 uint64_t Mask = ((1LLU << (32 - MB)) - 1) & ~((1LLU << (31 - ME)) - 1);
2521 InVal &= Mask;
2522 // Can't replace negative values with an LI as that will sign-extend
2523 // and not clear the left bits. If we're setting the CR bit, we will use
2524 // ANDIo which won't sign extend, so that's safe.
2525 bool ValueFits = isUInt<15>(InVal.getSExtValue());
2526 ValueFits |= ((Opc == PPC::RLWINMo || Opc == PPC::RLWINM8o) &&
2527 isUInt<16>(InVal.getSExtValue()));
2528 if (ValueFits) {
2529 ReplaceWithLI = true;
2530 Is64BitLI = Opc == PPC::RLWINM8 || Opc == PPC::RLWINM8o;
2531 NewImm = InVal.getSExtValue();
2532 SetCR = Opc == PPC::RLWINMo || Opc == PPC::RLWINM8o;
2533 break;
2534 }
2535 return false;
2536 }
2537 case PPC::ORI:
2538 case PPC::ORI8:
2539 case PPC::XORI:
2540 case PPC::XORI8: {
2541 int64_t LogicalImm = MI.getOperand(2).getImm();
2542 int64_t Result = 0;
2543 if (Opc == PPC::ORI || Opc == PPC::ORI8)
2544 Result = LogicalImm | SExtImm;
2545 else
2546 Result = LogicalImm ^ SExtImm;
2547 if (isInt<16>(Result)) {
2548 ReplaceWithLI = true;
2549 Is64BitLI = Opc == PPC::ORI8 || Opc == PPC::XORI8;
2550 NewImm = Result;
2551 break;
2552 }
2553 return false;
2554 }
2555 }
2556
2557 if (ReplaceWithLI) {
2558 // We need to be careful with CR-setting instructions we're replacing.
2559 if (SetCR) {
2560 // We don't know anything about uses when we're out of SSA, so only
2561 // replace if the new immediate will be reproduced.
2562 bool ImmChanged = (SExtImm & NewImm) != NewImm;
2563 if (PostRA && ImmChanged)
2564 return false;
2565
2566 if (!PostRA) {
2567 // If the defining load-immediate has no other uses, we can just replace
2568 // the immediate with the new immediate.
2569 if (MRI->hasOneUse(DefMI->getOperand(0).getReg()))
2570 DefMI->getOperand(1).setImm(NewImm);
2571
2572 // If we're not using the GPR result of the CR-setting instruction, we
2573 // just need to and with zero/non-zero depending on the new immediate.
2574 else if (MRI->use_empty(MI.getOperand(0).getReg())) {
2575 if (NewImm) {
2576 assert(Immediate && "Transformation converted zero to non-zero?")(static_cast <bool> (Immediate && "Transformation converted zero to non-zero?"
) ? void (0) : __assert_fail ("Immediate && \"Transformation converted zero to non-zero?\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 2576, __extension__ __PRETTY_FUNCTION__))
;
2577 NewImm = Immediate;
2578 }
2579 }
2580 else if (ImmChanged)
2581 return false;
2582 }
2583 }
2584
2585 LLVM_DEBUG(dbgs() << "Replacing instruction:\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("ppc-instr-info")) { dbgs() << "Replacing instruction:\n"
; } } while (false)
;
2586 LLVM_DEBUG(MI.dump())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("ppc-instr-info")) { MI.dump(); } } while (false)
;
2587 LLVM_DEBUG(dbgs() << "Fed by:\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("ppc-instr-info")) { dbgs() << "Fed by:\n"; } } while (
false)
;
2588 LLVM_DEBUG(DefMI->dump())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("ppc-instr-info")) { DefMI->dump(); } } while (false)
;
2589 LoadImmediateInfo LII;
2590 LII.Imm = NewImm;
2591 LII.Is64Bit = Is64BitLI;
2592 LII.SetCR = SetCR;
2593 // If we're setting the CR, the original load-immediate must be kept (as an
2594 // operand to ANDIo/ANDI8o).
2595 if (KilledDef && SetCR)
2596 *KilledDef = nullptr;
2597 replaceInstrWithLI(MI, LII);
2598 LLVM_DEBUG(dbgs() << "With:\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("ppc-instr-info")) { dbgs() << "With:\n"; } } while (false
)
;
2599 LLVM_DEBUG(MI.dump())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("ppc-instr-info")) { MI.dump(); } } while (false)
;
2600 return true;
2601 }
2602 return false;
2603}
2604
2605bool PPCInstrInfo::instrHasImmForm(const MachineInstr &MI,
2606 ImmInstrInfo &III) const {
2607 unsigned Opc = MI.getOpcode();
2608 // The vast majority of the instructions would need their operand 2 replaced
2609 // with an immediate when switching to the reg+imm form. A marked exception
2610 // are the update form loads/stores for which a constant operand 2 would need
2611 // to turn into a displacement and move operand 1 to the operand 2 position.
2612 III.ImmOpNo = 2;
2613 III.ConstantOpNo = 2;
2614 III.ImmWidth = 16;
2615 III.ImmMustBeMultipleOf = 1;
2616 III.TruncateImmTo = 0;
2617 switch (Opc) {
2618 default: return false;
2619 case PPC::ADD4:
2620 case PPC::ADD8:
2621 III.SignedImm = true;
2622 III.ZeroIsSpecialOrig = 0;
2623 III.ZeroIsSpecialNew = 1;
2624 III.IsCommutative = true;
2625 III.ImmOpcode = Opc == PPC::ADD4 ? PPC::ADDI : PPC::ADDI8;
2626 break;
2627 case PPC::ADDC:
2628 case PPC::ADDC8:
2629 III.SignedImm = true;
2630 III.ZeroIsSpecialOrig = 0;
2631 III.ZeroIsSpecialNew = 0;
2632 III.IsCommutative = true;
2633 III.ImmOpcode = Opc == PPC::ADDC ? PPC::ADDIC : PPC::ADDIC8;
2634 break;
2635 case PPC::ADDCo:
2636 III.SignedImm = true;
2637 III.ZeroIsSpecialOrig = 0;
2638 III.ZeroIsSpecialNew = 0;
2639 III.IsCommutative = true;
2640 III.ImmOpcode = PPC::ADDICo;
2641 break;
2642 case PPC::SUBFC:
2643 case PPC::SUBFC8:
2644 III.SignedImm = true;
2645 III.ZeroIsSpecialOrig = 0;
2646 III.ZeroIsSpecialNew = 0;
2647 III.IsCommutative = false;
2648 III.ImmOpcode = Opc == PPC::SUBFC ? PPC::SUBFIC : PPC::SUBFIC8;
2649 break;
2650 case PPC::CMPW:
2651 case PPC::CMPD:
2652 III.SignedImm = true;
2653 III.ZeroIsSpecialOrig = 0;
2654 III.ZeroIsSpecialNew = 0;
2655 III.IsCommutative = false;
2656 III.ImmOpcode = Opc == PPC::CMPW ? PPC::CMPWI : PPC::CMPDI;
2657 break;
2658 case PPC::CMPLW:
2659 case PPC::CMPLD:
2660 III.SignedImm = false;
2661 III.ZeroIsSpecialOrig = 0;
2662 III.ZeroIsSpecialNew = 0;
2663 III.IsCommutative = false;
2664 III.ImmOpcode = Opc == PPC::CMPLW ? PPC::CMPLWI : PPC::CMPLDI;
2665 break;
2666 case PPC::ANDo:
2667 case PPC::AND8o:
2668 case PPC::OR:
2669 case PPC::OR8:
2670 case PPC::XOR:
2671 case PPC::XOR8:
2672 III.SignedImm = false;
2673 III.ZeroIsSpecialOrig = 0;
2674 III.ZeroIsSpecialNew = 0;
2675 III.IsCommutative = true;
2676 switch(Opc) {
2677 default: llvm_unreachable("Unknown opcode")::llvm::llvm_unreachable_internal("Unknown opcode", "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 2677)
;
2678 case PPC::ANDo: III.ImmOpcode = PPC::ANDIo; break;
2679 case PPC::AND8o: III.ImmOpcode = PPC::ANDIo8; break;
2680 case PPC::OR: III.ImmOpcode = PPC::ORI; break;
2681 case PPC::OR8: III.ImmOpcode = PPC::ORI8; break;
2682 case PPC::XOR: III.ImmOpcode = PPC::XORI; break;
2683 case PPC::XOR8: III.ImmOpcode = PPC::XORI8; break;
2684 }
2685 break;
2686 case PPC::RLWNM:
2687 case PPC::RLWNM8:
2688 case PPC::RLWNMo:
2689 case PPC::RLWNM8o:
2690 case PPC::SLW:
2691 case PPC::SLW8:
2692 case PPC::SLWo:
2693 case PPC::SLW8o:
2694 case PPC::SRW:
2695 case PPC::SRW8:
2696 case PPC::SRWo:
2697 case PPC::SRW8o:
2698 case PPC::SRAW:
2699 case PPC::SRAWo:
2700 III.SignedImm = false;
2701 III.ZeroIsSpecialOrig = 0;
2702 III.ZeroIsSpecialNew = 0;
2703 III.IsCommutative = false;
2704 // This isn't actually true, but the instructions ignore any of the
2705 // upper bits, so any immediate loaded with an LI is acceptable.
2706 // This does not apply to shift right algebraic because a value
2707 // out of range will produce a -1/0.
2708 III.ImmWidth = 16;
2709 if (Opc == PPC::RLWNM || Opc == PPC::RLWNM8 ||
2710 Opc == PPC::RLWNMo || Opc == PPC::RLWNM8o)
2711 III.TruncateImmTo = 5;
2712 else
2713 III.TruncateImmTo = 6;
2714 switch(Opc) {
2715 default: llvm_unreachable("Unknown opcode")::llvm::llvm_unreachable_internal("Unknown opcode", "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 2715)
;
2716 case PPC::RLWNM: III.ImmOpcode = PPC::RLWINM; break;
2717 case PPC::RLWNM8: III.ImmOpcode = PPC::RLWINM8; break;
2718 case PPC::RLWNMo: III.ImmOpcode = PPC::RLWINMo; break;
2719 case PPC::RLWNM8o: III.ImmOpcode = PPC::RLWINM8o; break;
2720 case PPC::SLW: III.ImmOpcode = PPC::RLWINM; break;
2721 case PPC::SLW8: III.ImmOpcode = PPC::RLWINM8; break;
2722 case PPC::SLWo: III.ImmOpcode = PPC::RLWINMo; break;
2723 case PPC::SLW8o: III.ImmOpcode = PPC::RLWINM8o; break;
2724 case PPC::SRW: III.ImmOpcode = PPC::RLWINM; break;
2725 case PPC::SRW8: III.ImmOpcode = PPC::RLWINM8; break;
2726 case PPC::SRWo: III.ImmOpcode = PPC::RLWINMo; break;
2727 case PPC::SRW8o: III.ImmOpcode = PPC::RLWINM8o; break;
2728 case PPC::SRAW:
2729 III.ImmWidth = 5;
2730 III.TruncateImmTo = 0;
2731 III.ImmOpcode = PPC::SRAWI;
2732 break;
2733 case PPC::SRAWo:
2734 III.ImmWidth = 5;
2735 III.TruncateImmTo = 0;
2736 III.ImmOpcode = PPC::SRAWIo;
2737 break;
2738 }
2739 break;
2740 case PPC::RLDCL:
2741 case PPC::RLDCLo:
2742 case PPC::RLDCR:
2743 case PPC::RLDCRo:
2744 case PPC::SLD:
2745 case PPC::SLDo:
2746 case PPC::SRD:
2747 case PPC::SRDo:
2748 case PPC::SRAD:
2749 case PPC::SRADo:
2750 III.SignedImm = false;
2751 III.ZeroIsSpecialOrig = 0;
2752 III.ZeroIsSpecialNew = 0;
2753 III.IsCommutative = false;
2754 // This isn't actually true, but the instructions ignore any of the
2755 // upper bits, so any immediate loaded with an LI is acceptable.
2756 // This does not apply to shift right algebraic because a value
2757 // out of range will produce a -1/0.
2758 III.ImmWidth = 16;
2759 if (Opc == PPC::RLDCL || Opc == PPC::RLDCLo ||
2760 Opc == PPC::RLDCR || Opc == PPC::RLDCRo)
2761 III.TruncateImmTo = 6;
2762 else
2763 III.TruncateImmTo = 7;
2764 switch(Opc) {
2765 default: llvm_unreachable("Unknown opcode")::llvm::llvm_unreachable_internal("Unknown opcode", "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 2765)
;
2766 case PPC::RLDCL: III.ImmOpcode = PPC::RLDICL; break;
2767 case PPC::RLDCLo: III.ImmOpcode = PPC::RLDICLo; break;
2768 case PPC::RLDCR: III.ImmOpcode = PPC::RLDICR; break;
2769 case PPC::RLDCRo: III.ImmOpcode = PPC::RLDICRo; break;
2770 case PPC::SLD: III.ImmOpcode = PPC::RLDICR; break;
2771 case PPC::SLDo: III.ImmOpcode = PPC::RLDICRo; break;
2772 case PPC::SRD: III.ImmOpcode = PPC::RLDICL; break;
2773 case PPC::SRDo: III.ImmOpcode = PPC::RLDICLo; break;
2774 case PPC::SRAD:
2775 III.ImmWidth = 6;
2776 III.TruncateImmTo = 0;
2777 III.ImmOpcode = PPC::SRADI;
2778 break;
2779 case PPC::SRADo:
2780 III.ImmWidth = 6;
2781 III.TruncateImmTo = 0;
2782 III.ImmOpcode = PPC::SRADIo;
2783 break;
2784 }
2785 break;
2786 // Loads and stores:
2787 case PPC::LBZX:
2788 case PPC::LBZX8:
2789 case PPC::LHZX:
2790 case PPC::LHZX8:
2791 case PPC::LHAX:
2792 case PPC::LHAX8:
2793 case PPC::LWZX:
2794 case PPC::LWZX8:
2795 case PPC::LWAX:
2796 case PPC::LDX:
2797 case PPC::LFSX:
2798 case PPC::LFDX:
2799 case PPC::STBX:
2800 case PPC::STBX8:
2801 case PPC::STHX:
2802 case PPC::STHX8:
2803 case PPC::STWX:
2804 case PPC::STWX8:
2805 case PPC::STDX:
2806 case PPC::STFSX:
2807 case PPC::STFDX:
2808 III.SignedImm = true;
2809 III.ZeroIsSpecialOrig = 1;
2810 III.ZeroIsSpecialNew = 2;
2811 III.IsCommutative = true;
2812 III.ImmOpNo = 1;
2813 III.ConstantOpNo = 2;
2814 switch(Opc) {
2815 default: llvm_unreachable("Unknown opcode")::llvm::llvm_unreachable_internal("Unknown opcode", "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 2815)
;
2816 case PPC::LBZX: III.ImmOpcode = PPC::LBZ; break;
2817 case PPC::LBZX8: III.ImmOpcode = PPC::LBZ8; break;
2818 case PPC::LHZX: III.ImmOpcode = PPC::LHZ; break;
2819 case PPC::LHZX8: III.ImmOpcode = PPC::LHZ8; break;
2820 case PPC::LHAX: III.ImmOpcode = PPC::LHA; break;
2821 case PPC::LHAX8: III.ImmOpcode = PPC::LHA8; break;
2822 case PPC::LWZX: III.ImmOpcode = PPC::LWZ; break;
2823 case PPC::LWZX8: III.ImmOpcode = PPC::LWZ8; break;
2824 case PPC::LWAX:
2825 III.ImmOpcode = PPC::LWA;
2826 III.ImmMustBeMultipleOf = 4;
2827 break;
2828 case PPC::LDX: III.ImmOpcode = PPC::LD; III.ImmMustBeMultipleOf = 4; break;
2829 case PPC::LFSX: III.ImmOpcode = PPC::LFS; break;
2830 case PPC::LFDX: III.ImmOpcode = PPC::LFD; break;
2831 case PPC::STBX: III.ImmOpcode = PPC::STB; break;
2832 case PPC::STBX8: III.ImmOpcode = PPC::STB8; break;
2833 case PPC::STHX: III.ImmOpcode = PPC::STH; break;
2834 case PPC::STHX8: III.ImmOpcode = PPC::STH8; break;
2835 case PPC::STWX: III.ImmOpcode = PPC::STW; break;
2836 case PPC::STWX8: III.ImmOpcode = PPC::STW8; break;
2837 case PPC::STDX:
2838 III.ImmOpcode = PPC::STD;
2839 III.ImmMustBeMultipleOf = 4;
2840 break;
2841 case PPC::STFSX: III.ImmOpcode = PPC::STFS; break;
2842 case PPC::STFDX: III.ImmOpcode = PPC::STFD; break;
2843 }
2844 break;
2845 case PPC::LBZUX:
2846 case PPC::LBZUX8:
2847 case PPC::LHZUX:
2848 case PPC::LHZUX8:
2849 case PPC::LHAUX:
2850 case PPC::LHAUX8:
2851 case PPC::LWZUX:
2852 case PPC::LWZUX8:
2853 case PPC::LDUX:
2854 case PPC::LFSUX:
2855 case PPC::LFDUX:
2856 case PPC::STBUX:
2857 case PPC::STBUX8:
2858 case PPC::STHUX:
2859 case PPC::STHUX8:
2860 case PPC::STWUX:
2861 case PPC::STWUX8:
2862 case PPC::STDUX:
2863 case PPC::STFSUX:
2864 case PPC::STFDUX:
2865 III.SignedImm = true;
2866 III.ZeroIsSpecialOrig = 2;
2867 III.ZeroIsSpecialNew = 3;
2868 III.IsCommutative = false;
2869 III.ImmOpNo = 2;
2870 III.ConstantOpNo = 3;
2871 switch(Opc) {
2872 default: llvm_unreachable("Unknown opcode")::llvm::llvm_unreachable_internal("Unknown opcode", "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 2872)
;
2873 case PPC::LBZUX: III.ImmOpcode = PPC::LBZU; break;
2874 case PPC::LBZUX8: III.ImmOpcode = PPC::LBZU8; break;
2875 case PPC::LHZUX: III.ImmOpcode = PPC::LHZU; break;
2876 case PPC::LHZUX8: III.ImmOpcode = PPC::LHZU8; break;
2877 case PPC::LHAUX: III.ImmOpcode = PPC::LHAU; break;
2878 case PPC::LHAUX8: III.ImmOpcode = PPC::LHAU8; break;
2879 case PPC::LWZUX: III.ImmOpcode = PPC::LWZU; break;
2880 case PPC::LWZUX8: III.ImmOpcode = PPC::LWZU8; break;
2881 case PPC::LDUX:
2882 III.ImmOpcode = PPC::LDU;
2883 III.ImmMustBeMultipleOf = 4;
2884 break;
2885 case PPC::LFSUX: III.ImmOpcode = PPC::LFSU; break;
2886 case PPC::LFDUX: III.ImmOpcode = PPC::LFDU; break;
2887 case PPC::STBUX: III.ImmOpcode = PPC::STBU; break;
2888 case PPC::STBUX8: III.ImmOpcode = PPC::STBU8; break;
2889 case PPC::STHUX: III.ImmOpcode = PPC::STHU; break;
2890 case PPC::STHUX8: III.ImmOpcode = PPC::STHU8; break;
2891 case PPC::STWUX: III.ImmOpcode = PPC::STWU; break;
2892 case PPC::STWUX8: III.ImmOpcode = PPC::STWU8; break;
2893 case PPC::STDUX:
2894 III.ImmOpcode = PPC::STDU;
2895 III.ImmMustBeMultipleOf = 4;
2896 break;
2897 case PPC::STFSUX: III.ImmOpcode = PPC::STFSU; break;
2898 case PPC::STFDUX: III.ImmOpcode = PPC::STFDU; break;
2899 }
2900 break;
2901 // Power9 only.
2902 case PPC::LXVX:
2903 case PPC::LXSSPX:
2904 case PPC::LXSDX:
2905 case PPC::STXVX:
2906 case PPC::STXSSPX:
2907 case PPC::STXSDX:
2908 if (!Subtarget.hasP9Vector())
2909 return false;
2910 III.SignedImm = true;
2911 III.ZeroIsSpecialOrig = 1;
2912 III.ZeroIsSpecialNew = 2;
2913 III.IsCommutative = true;
2914 III.ImmOpNo = 1;
2915 III.ConstantOpNo = 2;
2916 switch(Opc) {
2917 default: llvm_unreachable("Unknown opcode")::llvm::llvm_unreachable_internal("Unknown opcode", "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 2917)
;
2918 case PPC::LXVX:
2919 III.ImmOpcode = PPC::LXV;
2920 III.ImmMustBeMultipleOf = 16;
2921 break;
2922 case PPC::LXSSPX:
2923 III.ImmOpcode = PPC::LXSSP;
2924 III.ImmMustBeMultipleOf = 4;
2925 break;
2926 case PPC::LXSDX:
2927 III.ImmOpcode = PPC::LXSD;
2928 III.ImmMustBeMultipleOf = 4;
2929 break;
2930 case PPC::STXVX:
2931 III.ImmOpcode = PPC::STXV;
2932 III.ImmMustBeMultipleOf = 16;
2933 break;
2934 case PPC::STXSSPX:
2935 III.ImmOpcode = PPC::STXSSP;
2936 III.ImmMustBeMultipleOf = 4;
2937 break;
2938 case PPC::STXSDX:
2939 III.ImmOpcode = PPC::STXSD;
2940 III.ImmMustBeMultipleOf = 4;
2941 break;
2942 }
2943 break;
2944 }
2945 return true;
2946}
2947
2948// Utility function for swaping two arbitrary operands of an instruction.
2949static void swapMIOperands(MachineInstr &MI, unsigned Op1, unsigned Op2) {
2950 assert(Op1 != Op2 && "Cannot swap operand with itself.")(static_cast <bool> (Op1 != Op2 && "Cannot swap operand with itself."
) ? void (0) : __assert_fail ("Op1 != Op2 && \"Cannot swap operand with itself.\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 2950, __extension__ __PRETTY_FUNCTION__))
;
2951
2952 unsigned MaxOp = std::max(Op1, Op2);
2953 unsigned MinOp = std::min(Op1, Op2);
2954 MachineOperand MOp1 = MI.getOperand(MinOp);
2955 MachineOperand MOp2 = MI.getOperand(MaxOp);
2956 MI.RemoveOperand(std::max(Op1, Op2));
2957 MI.RemoveOperand(std::min(Op1, Op2));
2958
2959 // If the operands we are swapping are the two at the end (the common case)
2960 // we can just remove both and add them in the opposite order.
2961 if (MaxOp - MinOp == 1 && MI.getNumOperands() == MinOp) {
2962 MI.addOperand(MOp2);
2963 MI.addOperand(MOp1);
2964 } else {
2965 // Store all operands in a temporary vector, remove them and re-add in the
2966 // right order.
2967 SmallVector<MachineOperand, 2> MOps;
2968 unsigned TotalOps = MI.getNumOperands() + 2; // We've already removed 2 ops.
2969 for (unsigned i = MI.getNumOperands() - 1; i >= MinOp; i--) {
2970 MOps.push_back(MI.getOperand(i));
2971 MI.RemoveOperand(i);
2972 }
2973 // MOp2 needs to be added next.
2974 MI.addOperand(MOp2);
2975 // Now add the rest.
2976 for (unsigned i = MI.getNumOperands(); i < TotalOps; i++) {
2977 if (i == MaxOp)
2978 MI.addOperand(MOp1);
2979 else {
2980 MI.addOperand(MOps.back());
2981 MOps.pop_back();
2982 }
2983 }
2984 }
2985}
2986
2987bool PPCInstrInfo::transformToImmForm(MachineInstr &MI, const ImmInstrInfo &III,
2988 unsigned ConstantOpNo,
2989 int64_t Imm) const {
2990 MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
2991 bool PostRA = !MRI.isSSA();
2992 // Exit early if we can't convert this.
2993 if ((ConstantOpNo != III.ConstantOpNo) && !III.IsCommutative)
2994 return false;
2995 if (Imm % III.ImmMustBeMultipleOf)
2996 return false;
2997 if (III.TruncateImmTo)
2998 Imm &= ((1 << III.TruncateImmTo) - 1);
2999 if (III.SignedImm) {
3000 APInt ActualValue(64, Imm, true);
3001 if (!ActualValue.isSignedIntN(III.ImmWidth))
3002 return false;
3003 } else {
3004 uint64_t UnsignedMax = (1 << III.ImmWidth) - 1;
3005 if ((uint64_t)Imm > UnsignedMax)
3006 return false;
3007 }
3008
3009 // If we're post-RA, the instructions don't agree on whether register zero is
3010 // special, we can transform this as long as the register operand that will
3011 // end up in the location where zero is special isn't R0.
3012 if (PostRA && III.ZeroIsSpecialOrig != III.ZeroIsSpecialNew) {
3013 unsigned PosForOrigZero = III.ZeroIsSpecialOrig ? III.ZeroIsSpecialOrig :
3014 III.ZeroIsSpecialNew + 1;
3015 unsigned OrigZeroReg = MI.getOperand(PosForOrigZero).getReg();
3016 unsigned NewZeroReg = MI.getOperand(III.ZeroIsSpecialNew).getReg();
3017 // If R0 is in the operand where zero is special for the new instruction,
3018 // it is unsafe to transform if the constant operand isn't that operand.
3019 if ((NewZeroReg == PPC::R0 || NewZeroReg == PPC::X0) &&
3020 ConstantOpNo != III.ZeroIsSpecialNew)
3021 return false;
3022 if ((OrigZeroReg == PPC::R0 || OrigZeroReg == PPC::X0) &&
3023 ConstantOpNo != PosForOrigZero)
3024 return false;
3025 }
3026
3027 unsigned Opc = MI.getOpcode();
3028 bool SpecialShift32 =
3029 Opc == PPC::SLW || Opc == PPC::SLWo || Opc == PPC::SRW || Opc == PPC::SRWo;
3030 bool SpecialShift64 =
3031 Opc == PPC::SLD || Opc == PPC::SLDo || Opc == PPC::SRD || Opc == PPC::SRDo;
3032 bool SetCR = Opc == PPC::SLWo || Opc == PPC::SRWo ||
3033 Opc == PPC::SLDo || Opc == PPC::SRDo;
3034 bool RightShift =
3035 Opc == PPC::SRW || Opc == PPC::SRWo || Opc == PPC::SRD || Opc == PPC::SRDo;
3036
3037 MI.setDesc(get(III.ImmOpcode));
3038 if (ConstantOpNo == III.ConstantOpNo) {
3039 // Converting shifts to immediate form is a bit tricky since they may do
3040 // one of three things:
3041 // 1. If the shift amount is between OpSize and 2*OpSize, the result is zero
3042 // 2. If the shift amount is zero, the result is unchanged (save for maybe
3043 // setting CR0)
3044 // 3. If the shift amount is in [1, OpSize), it's just a shift
3045 if (SpecialShift32 || SpecialShift64) {
3046 LoadImmediateInfo LII;
3047 LII.Imm = 0;
3048 LII.SetCR = SetCR;
3049 LII.Is64Bit = SpecialShift64;
3050 uint64_t ShAmt = Imm & (SpecialShift32 ? 0x1F : 0x3F);
3051 if (Imm & (SpecialShift32 ? 0x20 : 0x40))
3052 replaceInstrWithLI(MI, LII);
3053 // Shifts by zero don't change the value. If we don't need to set CR0,
3054 // just convert this to a COPY. Can't do this post-RA since we've already
3055 // cleaned up the copies.
3056 else if (!SetCR && ShAmt == 0 && !PostRA) {
3057 MI.RemoveOperand(2);
3058 MI.setDesc(get(PPC::COPY));
3059 } else {
3060 // The 32 bit and 64 bit instructions are quite different.
3061 if (SpecialShift32) {
3062 // Left shifts use (N, 0, 31-N), right shifts use (32-N, N, 31).
3063 uint64_t SH = RightShift ? 32 - ShAmt : ShAmt;
3064 uint64_t MB = RightShift ? ShAmt : 0;
3065 uint64_t ME = RightShift ? 31 : 31 - ShAmt;
3066 MI.getOperand(III.ConstantOpNo).ChangeToImmediate(SH);
3067 MachineInstrBuilder(*MI.getParent()->getParent(), MI).addImm(MB)
3068 .addImm(ME);
3069 } else {
3070 // Left shifts use (N, 63-N), right shifts use (64-N, N).
3071 uint64_t SH = RightShift ? 64 - ShAmt : ShAmt;
3072 uint64_t ME = RightShift ? ShAmt : 63 - ShAmt;
3073 MI.getOperand(III.ConstantOpNo).ChangeToImmediate(SH);
3074 MachineInstrBuilder(*MI.getParent()->getParent(), MI).addImm(ME);
3075 }
3076 }
3077 } else
3078 MI.getOperand(ConstantOpNo).ChangeToImmediate(Imm);
3079 }
3080 // Convert commutative instructions (switch the operands and convert the
3081 // desired one to an immediate.
3082 else if (III.IsCommutative) {
3083 MI.getOperand(ConstantOpNo).ChangeToImmediate(Imm);
3084 swapMIOperands(MI, ConstantOpNo, III.ConstantOpNo);
3085 } else
3086 llvm_unreachable("Should have exited early!")::llvm::llvm_unreachable_internal("Should have exited early!"
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 3086)
;
3087
3088 // For instructions for which the constant register replaces a different
3089 // operand than where the immediate goes, we need to swap them.
3090 if (III.ConstantOpNo != III.ImmOpNo)
3091 swapMIOperands(MI, III.ConstantOpNo, III.ImmOpNo);
3092
3093 // If the R0/X0 register is special for the original instruction and not for
3094 // the new instruction (or vice versa), we need to fix up the register class.
3095 if (!PostRA && III.ZeroIsSpecialOrig != III.ZeroIsSpecialNew) {
3096 if (!III.ZeroIsSpecialOrig) {
3097 unsigned RegToModify = MI.getOperand(III.ZeroIsSpecialNew).getReg();
3098 const TargetRegisterClass *NewRC =
3099 MRI.getRegClass(RegToModify)->hasSuperClassEq(&PPC::GPRCRegClass) ?
3100 &PPC::GPRC_and_GPRC_NOR0RegClass : &PPC::G8RC_and_G8RC_NOX0RegClass;
3101 MRI.setRegClass(RegToModify, NewRC);
3102 }
3103 }
3104 return true;
3105}
3106
3107const TargetRegisterClass *
3108PPCInstrInfo::updatedRC(const TargetRegisterClass *RC) const {
3109 if (Subtarget.hasVSX() && RC == &PPC::VRRCRegClass)
3110 return &PPC::VSRCRegClass;
3111 return RC;
3112}
3113
3114int PPCInstrInfo::getRecordFormOpcode(unsigned Opcode) {
3115 return PPC::getRecordFormOpcode(Opcode);
3116}
3117
3118// This function returns true if the machine instruction
3119// always outputs a value by sign-extending a 32 bit value,
3120// i.e. 0 to 31-th bits are same as 32-th bit.
3121static bool isSignExtendingOp(const MachineInstr &MI) {
3122 int Opcode = MI.getOpcode();
3123 if (Opcode == PPC::LI || Opcode == PPC::LI8 ||
3124 Opcode == PPC::LIS || Opcode == PPC::LIS8 ||
3125 Opcode == PPC::SRAW || Opcode == PPC::SRAWo ||
3126 Opcode == PPC::SRAWI || Opcode == PPC::SRAWIo ||
3127 Opcode == PPC::LWA || Opcode == PPC::LWAX ||
3128 Opcode == PPC::LWA_32 || Opcode == PPC::LWAX_32 ||
3129 Opcode == PPC::LHA || Opcode == PPC::LHAX ||
3130 Opcode == PPC::LHA8 || Opcode == PPC::LHAX8 ||
3131 Opcode == PPC::LBZ || Opcode == PPC::LBZX ||
3132 Opcode == PPC::LBZ8 || Opcode == PPC::LBZX8 ||
3133 Opcode == PPC::LBZU || Opcode == PPC::LBZUX ||
3134 Opcode == PPC::LBZU8 || Opcode == PPC::LBZUX8 ||
3135 Opcode == PPC::LHZ || Opcode == PPC::LHZX ||
3136 Opcode == PPC::LHZ8 || Opcode == PPC::LHZX8 ||
3137 Opcode == PPC::LHZU || Opcode == PPC::LHZUX ||
3138 Opcode == PPC::LHZU8 || Opcode == PPC::LHZUX8 ||
3139 Opcode == PPC::EXTSB || Opcode == PPC::EXTSBo ||
3140 Opcode == PPC::EXTSH || Opcode == PPC::EXTSHo ||
3141 Opcode == PPC::EXTSB8 || Opcode == PPC::EXTSH8 ||
3142 Opcode == PPC::EXTSW || Opcode == PPC::EXTSWo ||
3143 Opcode == PPC::EXTSH8_32_64 || Opcode == PPC::EXTSW_32_64 ||
3144 Opcode == PPC::EXTSB8_32_64)
3145 return true;
3146
3147 if (Opcode == PPC::RLDICL && MI.getOperand(3).getImm() >= 33)
3148 return true;
3149
3150 if ((Opcode == PPC::RLWINM || Opcode == PPC::RLWINMo ||
3151 Opcode == PPC::RLWNM || Opcode == PPC::RLWNMo) &&
3152 MI.getOperand(3).getImm() > 0 &&
3153 MI.getOperand(3).getImm() <= MI.getOperand(4).getImm())
3154 return true;
3155
3156 return false;
3157}
3158
3159// This function returns true if the machine instruction
3160// always outputs zeros in higher 32 bits.
3161static bool isZeroExtendingOp(const MachineInstr &MI) {
3162 int Opcode = MI.getOpcode();
3163 // The 16-bit immediate is sign-extended in li/lis.
3164 // If the most significant bit is zero, all higher bits are zero.
3165 if (Opcode == PPC::LI || Opcode == PPC::LI8 ||
3166 Opcode == PPC::LIS || Opcode == PPC::LIS8) {
3167 int64_t Imm = MI.getOperand(1).getImm();
3168 if (((uint64_t)Imm & ~0x7FFFuLL) == 0)
3169 return true;
3170 }
3171
3172 // We have some variations of rotate-and-mask instructions
3173 // that clear higher 32-bits.
3174 if ((Opcode == PPC::RLDICL || Opcode == PPC::RLDICLo ||
3175 Opcode == PPC::RLDCL || Opcode == PPC::RLDCLo ||
3176 Opcode == PPC::RLDICL_32_64) &&
3177 MI.getOperand(3).getImm() >= 32)
3178 return true;
3179
3180 if ((Opcode == PPC::RLDIC || Opcode == PPC::RLDICo) &&
3181 MI.getOperand(3).getImm() >= 32 &&
3182 MI.getOperand(3).getImm() <= 63 - MI.getOperand(2).getImm())
3183 return true;
3184
3185 if ((Opcode == PPC::RLWINM || Opcode == PPC::RLWINMo ||
3186 Opcode == PPC::RLWNM || Opcode == PPC::RLWNMo ||
3187 Opcode == PPC::RLWINM8 || Opcode == PPC::RLWNM8) &&
3188 MI.getOperand(3).getImm() <= MI.getOperand(4).getImm())
3189 return true;
3190
3191 // There are other instructions that clear higher 32-bits.
3192 if (Opcode == PPC::CNTLZW || Opcode == PPC::CNTLZWo ||
3193 Opcode == PPC::CNTTZW || Opcode == PPC::CNTTZWo ||
3194 Opcode == PPC::CNTLZW8 || Opcode == PPC::CNTTZW8 ||
3195 Opcode == PPC::CNTLZD || Opcode == PPC::CNTLZDo ||
3196 Opcode == PPC::CNTTZD || Opcode == PPC::CNTTZDo ||
3197 Opcode == PPC::POPCNTD || Opcode == PPC::POPCNTW ||
3198 Opcode == PPC::SLW || Opcode == PPC::SLWo ||
3199 Opcode == PPC::SRW || Opcode == PPC::SRWo ||
3200 Opcode == PPC::SLW8 || Opcode == PPC::SRW8 ||
3201 Opcode == PPC::SLWI || Opcode == PPC::SLWIo ||
3202 Opcode == PPC::SRWI || Opcode == PPC::SRWIo ||
3203 Opcode == PPC::LWZ || Opcode == PPC::LWZX ||
3204 Opcode == PPC::LWZU || Opcode == PPC::LWZUX ||
3205 Opcode == PPC::LWBRX || Opcode == PPC::LHBRX ||
3206 Opcode == PPC::LHZ || Opcode == PPC::LHZX ||
3207 Opcode == PPC::LHZU || Opcode == PPC::LHZUX ||
3208 Opcode == PPC::LBZ || Opcode == PPC::LBZX ||
3209 Opcode == PPC::LBZU || Opcode == PPC::LBZUX ||
3210 Opcode == PPC::LWZ8 || Opcode == PPC::LWZX8 ||
3211 Opcode == PPC::LWZU8 || Opcode == PPC::LWZUX8 ||
3212 Opcode == PPC::LWBRX8 || Opcode == PPC::LHBRX8 ||
3213 Opcode == PPC::LHZ8 || Opcode == PPC::LHZX8 ||
3214 Opcode == PPC::LHZU8 || Opcode == PPC::LHZUX8 ||
3215 Opcode == PPC::LBZ8 || Opcode == PPC::LBZX8 ||
3216 Opcode == PPC::LBZU8 || Opcode == PPC::LBZUX8 ||
3217 Opcode == PPC::ANDIo || Opcode == PPC::ANDISo ||
3218 Opcode == PPC::ROTRWI || Opcode == PPC::ROTRWIo ||
3219 Opcode == PPC::EXTLWI || Opcode == PPC::EXTLWIo ||
3220 Opcode == PPC::MFVSRWZ)
3221 return true;
3222
3223 return false;
3224}
3225
3226// This function returns true if the input MachineInstr is a TOC save
3227// instruction.
3228bool PPCInstrInfo::isTOCSaveMI(const MachineInstr &MI) const {
3229 if (!MI.getOperand(1).isImm() || !MI.getOperand(2).isReg())
3230 return false;
3231 unsigned TOCSaveOffset = Subtarget.getFrameLowering()->getTOCSaveOffset();
3232 unsigned StackOffset = MI.getOperand(1).getImm();
3233 unsigned StackReg = MI.getOperand(2).getReg();
3234 if (StackReg == PPC::X1 && StackOffset == TOCSaveOffset)
3235 return true;
3236
3237 return false;
3238}
3239
3240// We limit the max depth to track incoming values of PHIs or binary ops
3241// (e.g. AND) to avoid excessive cost.
3242const unsigned MAX_DEPTH = 1;
3243
3244bool
3245PPCInstrInfo::isSignOrZeroExtended(const MachineInstr &MI, bool SignExt,
3246 const unsigned Depth) const {
3247 const MachineFunction *MF = MI.getParent()->getParent();
3248 const MachineRegisterInfo *MRI = &MF->getRegInfo();
3249
3250 // If we know this instruction returns sign- or zero-extended result,
3251 // return true.
3252 if (SignExt ? isSignExtendingOp(MI):
3253 isZeroExtendingOp(MI))
3254 return true;
3255
3256 switch (MI.getOpcode()) {
3257 case PPC::COPY: {
3258 unsigned SrcReg = MI.getOperand(1).getReg();
3259
3260 // In both ELFv1 and v2 ABI, method parameters and the return value
3261 // are sign- or zero-extended.
3262 if (MF->getSubtarget<PPCSubtarget>().isSVR4ABI()) {
3263 const PPCFunctionInfo *FuncInfo = MF->getInfo<PPCFunctionInfo>();
3264 // We check the ZExt/SExt flags for a method parameter.
3265 if (MI.getParent()->getBasicBlock() ==
3266 &MF->getFunction().getEntryBlock()) {
3267 unsigned VReg = MI.getOperand(0).getReg();
3268 if (MF->getRegInfo().isLiveIn(VReg))
3269 return SignExt ? FuncInfo->isLiveInSExt(VReg) :
3270 FuncInfo->isLiveInZExt(VReg);
3271 }
3272
3273 // For a method return value, we check the ZExt/SExt flags in attribute.
3274 // We assume the following code sequence for method call.
3275 // ADJCALLSTACKDOWN 32, implicit dead %r1, implicit %r1
3276 // BL8_NOP @func,...
3277 // ADJCALLSTACKUP 32, 0, implicit dead %r1, implicit %r1
3278 // %5 = COPY %x3; G8RC:%5
3279 if (SrcReg == PPC::X3) {
3280 const MachineBasicBlock *MBB = MI.getParent();
3281 MachineBasicBlock::const_instr_iterator II =
3282 MachineBasicBlock::const_instr_iterator(&MI);
3283 if (II != MBB->instr_begin() &&
3284 (--II)->getOpcode() == PPC::ADJCALLSTACKUP) {
3285 const MachineInstr &CallMI = *(--II);
3286 if (CallMI.isCall() && CallMI.getOperand(0).isGlobal()) {
3287 const Function *CalleeFn =
3288 dyn_cast<Function>(CallMI.getOperand(0).getGlobal());
3289 if (!CalleeFn)
3290 return false;
3291 const IntegerType *IntTy =
3292 dyn_cast<IntegerType>(CalleeFn->getReturnType());
3293 const AttributeSet &Attrs =
3294 CalleeFn->getAttributes().getRetAttributes();
3295 if (IntTy && IntTy->getBitWidth() <= 32)
3296 return Attrs.hasAttribute(SignExt ? Attribute::SExt :
3297 Attribute::ZExt);
3298 }
3299 }
3300 }
3301 }
3302
3303 // If this is a copy from another register, we recursively check source.
3304 if (!TargetRegisterInfo::isVirtualRegister(SrcReg))
3305 return false;
3306 const MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
3307 if (SrcMI != NULL__null)
3308 return isSignOrZeroExtended(*SrcMI, SignExt, Depth);
3309
3310 return false;
3311 }
3312
3313 case PPC::ANDIo:
3314 case PPC::ANDISo:
3315 case PPC::ORI:
3316 case PPC::ORIS:
3317 case PPC::XORI:
3318 case PPC::XORIS:
3319 case PPC::ANDIo8:
3320 case PPC::ANDISo8:
3321 case PPC::ORI8:
3322 case PPC::ORIS8:
3323 case PPC::XORI8:
3324 case PPC::XORIS8: {
3325 // logical operation with 16-bit immediate does not change the upper bits.
3326 // So, we track the operand register as we do for register copy.
3327 unsigned SrcReg = MI.getOperand(1).getReg();
3328 if (!TargetRegisterInfo::isVirtualRegister(SrcReg))
3329 return false;
3330 const MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
3331 if (SrcMI != NULL__null)
3332 return isSignOrZeroExtended(*SrcMI, SignExt, Depth);
3333
3334 return false;
3335 }
3336
3337 // If all incoming values are sign-/zero-extended,
3338 // the output of OR, ISEL or PHI is also sign-/zero-extended.
3339 case PPC::OR:
3340 case PPC::OR8:
3341 case PPC::ISEL:
3342 case PPC::PHI: {
3343 if (Depth >= MAX_DEPTH)
3344 return false;
3345
3346 // The input registers for PHI are operand 1, 3, ...
3347 // The input registers for others are operand 1 and 2.
3348 unsigned E = 3, D = 1;
3349 if (MI.getOpcode() == PPC::PHI) {
3350 E = MI.getNumOperands();
3351 D = 2;
3352 }
3353
3354 for (unsigned I = 1; I != E; I += D) {
3355 if (MI.getOperand(I).isReg()) {
3356 unsigned SrcReg = MI.getOperand(I).getReg();
3357 if (!TargetRegisterInfo::isVirtualRegister(SrcReg))
3358 return false;
3359 const MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
3360 if (SrcMI == NULL__null || !isSignOrZeroExtended(*SrcMI, SignExt, Depth+1))
3361 return false;
3362 }
3363 else
3364 return false;
3365 }
3366 return true;
3367 }
3368
3369 // If at least one of the incoming values of an AND is zero extended
3370 // then the output is also zero-extended. If both of the incoming values
3371 // are sign-extended then the output is also sign extended.
3372 case PPC::AND:
3373 case PPC::AND8: {
3374 if (Depth >= MAX_DEPTH)
3375 return false;
3376
3377 assert(MI.getOperand(1).isReg() && MI.getOperand(2).isReg())(static_cast <bool> (MI.getOperand(1).isReg() &&
MI.getOperand(2).isReg()) ? void (0) : __assert_fail ("MI.getOperand(1).isReg() && MI.getOperand(2).isReg()"
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 3377, __extension__ __PRETTY_FUNCTION__))
;
3378
3379 unsigned SrcReg1 = MI.getOperand(1).getReg();
3380 unsigned SrcReg2 = MI.getOperand(2).getReg();
3381
3382 if (!TargetRegisterInfo::isVirtualRegister(SrcReg1) ||
3383 !TargetRegisterInfo::isVirtualRegister(SrcReg2))
3384 return false;
3385
3386 const MachineInstr *MISrc1 = MRI->getVRegDef(SrcReg1);
3387 const MachineInstr *MISrc2 = MRI->getVRegDef(SrcReg2);
3388 if (!MISrc1 || !MISrc2)
3389 return false;
3390
3391 if(SignExt)
3392 return isSignOrZeroExtended(*MISrc1, SignExt, Depth+1) &&
3393 isSignOrZeroExtended(*MISrc2, SignExt, Depth+1);
3394 else
3395 return isSignOrZeroExtended(*MISrc1, SignExt, Depth+1) ||
3396 isSignOrZeroExtended(*MISrc2, SignExt, Depth+1);
3397 }
3398
3399 default:
3400 break;
3401 }
3402 return false;
3403}