Bug Summary

File:lib/Target/PowerPC/PPCInstrInfo.cpp
Warning:line 1738, column 20
Value stored to 'NewPred' during its initialization is never read

Annotated Source Code

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clang -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name PPCInstrInfo.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-eagerly-assume -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -mrelocation-model pic -pic-level 2 -mthread-model posix -fmath-errno -masm-verbose -mconstructor-aliases -munwind-tables -fuse-init-array -target-cpu x86-64 -dwarf-column-info -debugger-tuning=gdb -momit-leaf-frame-pointer -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-7/lib/clang/7.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-7~svn325874/build-llvm/lib/Target/PowerPC -I /build/llvm-toolchain-snapshot-7~svn325874/lib/Target/PowerPC -I /build/llvm-toolchain-snapshot-7~svn325874/build-llvm/include -I /build/llvm-toolchain-snapshot-7~svn325874/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/7.3.0/../../../../include/c++/7.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/7.3.0/../../../../include/x86_64-linux-gnu/c++/7.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/7.3.0/../../../../include/x86_64-linux-gnu/c++/7.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/7.3.0/../../../../include/c++/7.3.0/backward -internal-isystem /usr/include/clang/7.0.0/include/ -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-7/lib/clang/7.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++11 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-7~svn325874/build-llvm/lib/Target/PowerPC -ferror-limit 19 -fmessage-length 0 -fvisibility-inlines-hidden -fobjc-runtime=gcc -fdiagnostics-show-option -vectorize-loops -vectorize-slp -analyzer-checker optin.performance.Padding -analyzer-output=html -analyzer-config stable-report-filename=true -o /tmp/scan-build-2018-02-23-163436-368-1 -x c++ /build/llvm-toolchain-snapshot-7~svn325874/lib/Target/PowerPC/PPCInstrInfo.cpp
1//===-- PPCInstrInfo.cpp - PowerPC Instruction Information ----------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the PowerPC implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "PPCInstrInfo.h"
15#include "MCTargetDesc/PPCPredicates.h"
16#include "PPC.h"
17#include "PPCHazardRecognizers.h"
18#include "PPCInstrBuilder.h"
19#include "PPCMachineFunctionInfo.h"
20#include "PPCTargetMachine.h"
21#include "llvm/ADT/STLExtras.h"
22#include "llvm/ADT/Statistic.h"
23#include "llvm/CodeGen/LiveIntervals.h"
24#include "llvm/CodeGen/MachineFrameInfo.h"
25#include "llvm/CodeGen/MachineFunctionPass.h"
26#include "llvm/CodeGen/MachineInstrBuilder.h"
27#include "llvm/CodeGen/MachineMemOperand.h"
28#include "llvm/CodeGen/MachineRegisterInfo.h"
29#include "llvm/CodeGen/PseudoSourceValue.h"
30#include "llvm/CodeGen/ScheduleDAG.h"
31#include "llvm/CodeGen/SlotIndexes.h"
32#include "llvm/CodeGen/StackMaps.h"
33#include "llvm/MC/MCAsmInfo.h"
34#include "llvm/MC/MCInst.h"
35#include "llvm/Support/CommandLine.h"
36#include "llvm/Support/Debug.h"
37#include "llvm/Support/ErrorHandling.h"
38#include "llvm/Support/TargetRegistry.h"
39#include "llvm/Support/raw_ostream.h"
40
41using namespace llvm;
42
43#define DEBUG_TYPE"ppc-instr-info" "ppc-instr-info"
44
45#define GET_INSTRMAP_INFO
46#define GET_INSTRINFO_CTOR_DTOR
47#include "PPCGenInstrInfo.inc"
48
49STATISTIC(NumStoreSPILLVSRRCAsVec,static llvm::Statistic NumStoreSPILLVSRRCAsVec = {"ppc-instr-info"
, "NumStoreSPILLVSRRCAsVec", "Number of spillvsrrc spilled to stack as vec"
, {0}, {false}}
50 "Number of spillvsrrc spilled to stack as vec")static llvm::Statistic NumStoreSPILLVSRRCAsVec = {"ppc-instr-info"
, "NumStoreSPILLVSRRCAsVec", "Number of spillvsrrc spilled to stack as vec"
, {0}, {false}}
;
51STATISTIC(NumStoreSPILLVSRRCAsGpr,static llvm::Statistic NumStoreSPILLVSRRCAsGpr = {"ppc-instr-info"
, "NumStoreSPILLVSRRCAsGpr", "Number of spillvsrrc spilled to stack as gpr"
, {0}, {false}}
52 "Number of spillvsrrc spilled to stack as gpr")static llvm::Statistic NumStoreSPILLVSRRCAsGpr = {"ppc-instr-info"
, "NumStoreSPILLVSRRCAsGpr", "Number of spillvsrrc spilled to stack as gpr"
, {0}, {false}}
;
53STATISTIC(NumGPRtoVSRSpill, "Number of gpr spills to spillvsrrc")static llvm::Statistic NumGPRtoVSRSpill = {"ppc-instr-info", "NumGPRtoVSRSpill"
, "Number of gpr spills to spillvsrrc", {0}, {false}}
;
54STATISTIC(CmpIselsConverted,static llvm::Statistic CmpIselsConverted = {"ppc-instr-info",
"CmpIselsConverted", "Number of ISELs that depend on comparison of constants converted"
, {0}, {false}}
55 "Number of ISELs that depend on comparison of constants converted")static llvm::Statistic CmpIselsConverted = {"ppc-instr-info",
"CmpIselsConverted", "Number of ISELs that depend on comparison of constants converted"
, {0}, {false}}
;
56STATISTIC(MissedConvertibleImmediateInstrs,static llvm::Statistic MissedConvertibleImmediateInstrs = {"ppc-instr-info"
, "MissedConvertibleImmediateInstrs", "Number of compare-immediate instructions fed by constants"
, {0}, {false}}
57 "Number of compare-immediate instructions fed by constants")static llvm::Statistic MissedConvertibleImmediateInstrs = {"ppc-instr-info"
, "MissedConvertibleImmediateInstrs", "Number of compare-immediate instructions fed by constants"
, {0}, {false}}
;
58
59static cl::
60opt<bool> DisableCTRLoopAnal("disable-ppc-ctrloop-analysis", cl::Hidden,
61 cl::desc("Disable analysis for CTR loops"));
62
63static cl::opt<bool> DisableCmpOpt("disable-ppc-cmp-opt",
64cl::desc("Disable compare instruction optimization"), cl::Hidden);
65
66static cl::opt<bool> VSXSelfCopyCrash("crash-on-ppc-vsx-self-copy",
67cl::desc("Causes the backend to crash instead of generating a nop VSX copy"),
68cl::Hidden);
69
70static cl::opt<bool>
71UseOldLatencyCalc("ppc-old-latency-calc", cl::Hidden,
72 cl::desc("Use the old (incorrect) instruction latency calculation"));
73
74// Pin the vtable to this file.
75void PPCInstrInfo::anchor() {}
76
77PPCInstrInfo::PPCInstrInfo(PPCSubtarget &STI)
78 : PPCGenInstrInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP,
79 /* CatchRetOpcode */ -1,
80 STI.isPPC64() ? PPC::BLR8 : PPC::BLR),
81 Subtarget(STI), RI(STI.getTargetMachine()) {}
82
83/// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
84/// this target when scheduling the DAG.
85ScheduleHazardRecognizer *
86PPCInstrInfo::CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,
87 const ScheduleDAG *DAG) const {
88 unsigned Directive =
89 static_cast<const PPCSubtarget *>(STI)->getDarwinDirective();
90 if (Directive == PPC::DIR_440 || Directive == PPC::DIR_A2 ||
91 Directive == PPC::DIR_E500mc || Directive == PPC::DIR_E5500) {
92 const InstrItineraryData *II =
93 static_cast<const PPCSubtarget *>(STI)->getInstrItineraryData();
94 return new ScoreboardHazardRecognizer(II, DAG);
95 }
96
97 return TargetInstrInfo::CreateTargetHazardRecognizer(STI, DAG);
98}
99
100/// CreateTargetPostRAHazardRecognizer - Return the postRA hazard recognizer
101/// to use for this target when scheduling the DAG.
102ScheduleHazardRecognizer *
103PPCInstrInfo::CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
104 const ScheduleDAG *DAG) const {
105 unsigned Directive =
106 DAG->MF.getSubtarget<PPCSubtarget>().getDarwinDirective();
107
108 // FIXME: Leaving this as-is until we have POWER9 scheduling info
109 if (Directive == PPC::DIR_PWR7 || Directive == PPC::DIR_PWR8)
110 return new PPCDispatchGroupSBHazardRecognizer(II, DAG);
111
112 // Most subtargets use a PPC970 recognizer.
113 if (Directive != PPC::DIR_440 && Directive != PPC::DIR_A2 &&
114 Directive != PPC::DIR_E500mc && Directive != PPC::DIR_E5500) {
115 assert(DAG->TII && "No InstrInfo?")(static_cast <bool> (DAG->TII && "No InstrInfo?"
) ? void (0) : __assert_fail ("DAG->TII && \"No InstrInfo?\""
, "/build/llvm-toolchain-snapshot-7~svn325874/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 115, __extension__ __PRETTY_FUNCTION__))
;
116
117 return new PPCHazardRecognizer970(*DAG);
118 }
119
120 return new ScoreboardHazardRecognizer(II, DAG);
121}
122
123unsigned PPCInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
124 const MachineInstr &MI,
125 unsigned *PredCost) const {
126 if (!ItinData || UseOldLatencyCalc)
127 return PPCGenInstrInfo::getInstrLatency(ItinData, MI, PredCost);
128
129 // The default implementation of getInstrLatency calls getStageLatency, but
130 // getStageLatency does not do the right thing for us. While we have
131 // itinerary, most cores are fully pipelined, and so the itineraries only
132 // express the first part of the pipeline, not every stage. Instead, we need
133 // to use the listed output operand cycle number (using operand 0 here, which
134 // is an output).
135
136 unsigned Latency = 1;
137 unsigned DefClass = MI.getDesc().getSchedClass();
138 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
139 const MachineOperand &MO = MI.getOperand(i);
140 if (!MO.isReg() || !MO.isDef() || MO.isImplicit())
141 continue;
142
143 int Cycle = ItinData->getOperandCycle(DefClass, i);
144 if (Cycle < 0)
145 continue;
146
147 Latency = std::max(Latency, (unsigned) Cycle);
148 }
149
150 return Latency;
151}
152
153int PPCInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
154 const MachineInstr &DefMI, unsigned DefIdx,
155 const MachineInstr &UseMI,
156 unsigned UseIdx) const {
157 int Latency = PPCGenInstrInfo::getOperandLatency(ItinData, DefMI, DefIdx,
158 UseMI, UseIdx);
159
160 if (!DefMI.getParent())
161 return Latency;
162
163 const MachineOperand &DefMO = DefMI.getOperand(DefIdx);
164 unsigned Reg = DefMO.getReg();
165
166 bool IsRegCR;
167 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
168 const MachineRegisterInfo *MRI =
169 &DefMI.getParent()->getParent()->getRegInfo();
170 IsRegCR = MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRRCRegClass) ||
171 MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRBITRCRegClass);
172 } else {
173 IsRegCR = PPC::CRRCRegClass.contains(Reg) ||
174 PPC::CRBITRCRegClass.contains(Reg);
175 }
176
177 if (UseMI.isBranch() && IsRegCR) {
178 if (Latency < 0)
179 Latency = getInstrLatency(ItinData, DefMI);
180
181 // On some cores, there is an additional delay between writing to a condition
182 // register, and using it from a branch.
183 unsigned Directive = Subtarget.getDarwinDirective();
184 switch (Directive) {
185 default: break;
186 case PPC::DIR_7400:
187 case PPC::DIR_750:
188 case PPC::DIR_970:
189 case PPC::DIR_E5500:
190 case PPC::DIR_PWR4:
191 case PPC::DIR_PWR5:
192 case PPC::DIR_PWR5X:
193 case PPC::DIR_PWR6:
194 case PPC::DIR_PWR6X:
195 case PPC::DIR_PWR7:
196 case PPC::DIR_PWR8:
197 // FIXME: Is this needed for POWER9?
198 Latency += 2;
199 break;
200 }
201 }
202
203 return Latency;
204}
205
206// This function does not list all associative and commutative operations, but
207// only those worth feeding through the machine combiner in an attempt to
208// reduce the critical path. Mostly, this means floating-point operations,
209// because they have high latencies (compared to other operations, such and
210// and/or, which are also associative and commutative, but have low latencies).
211bool PPCInstrInfo::isAssociativeAndCommutative(const MachineInstr &Inst) const {
212 switch (Inst.getOpcode()) {
213 // FP Add:
214 case PPC::FADD:
215 case PPC::FADDS:
216 // FP Multiply:
217 case PPC::FMUL:
218 case PPC::FMULS:
219 // Altivec Add:
220 case PPC::VADDFP:
221 // VSX Add:
222 case PPC::XSADDDP:
223 case PPC::XVADDDP:
224 case PPC::XVADDSP:
225 case PPC::XSADDSP:
226 // VSX Multiply:
227 case PPC::XSMULDP:
228 case PPC::XVMULDP:
229 case PPC::XVMULSP:
230 case PPC::XSMULSP:
231 // QPX Add:
232 case PPC::QVFADD:
233 case PPC::QVFADDS:
234 case PPC::QVFADDSs:
235 // QPX Multiply:
236 case PPC::QVFMUL:
237 case PPC::QVFMULS:
238 case PPC::QVFMULSs:
239 return true;
240 default:
241 return false;
242 }
243}
244
245bool PPCInstrInfo::getMachineCombinerPatterns(
246 MachineInstr &Root,
247 SmallVectorImpl<MachineCombinerPattern> &Patterns) const {
248 // Using the machine combiner in this way is potentially expensive, so
249 // restrict to when aggressive optimizations are desired.
250 if (Subtarget.getTargetMachine().getOptLevel() != CodeGenOpt::Aggressive)
251 return false;
252
253 // FP reassociation is only legal when we don't need strict IEEE semantics.
254 if (!Root.getParent()->getParent()->getTarget().Options.UnsafeFPMath)
255 return false;
256
257 return TargetInstrInfo::getMachineCombinerPatterns(Root, Patterns);
258}
259
260// Detect 32 -> 64-bit extensions where we may reuse the low sub-register.
261bool PPCInstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
262 unsigned &SrcReg, unsigned &DstReg,
263 unsigned &SubIdx) const {
264 switch (MI.getOpcode()) {
265 default: return false;
266 case PPC::EXTSW:
267 case PPC::EXTSW_32:
268 case PPC::EXTSW_32_64:
269 SrcReg = MI.getOperand(1).getReg();
270 DstReg = MI.getOperand(0).getReg();
271 SubIdx = PPC::sub_32;
272 return true;
273 }
274}
275
276unsigned PPCInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
277 int &FrameIndex) const {
278 // Note: This list must be kept consistent with LoadRegFromStackSlot.
279 switch (MI.getOpcode()) {
280 default: break;
281 case PPC::LD:
282 case PPC::LWZ:
283 case PPC::LFS:
284 case PPC::LFD:
285 case PPC::RESTORE_CR:
286 case PPC::RESTORE_CRBIT:
287 case PPC::LVX:
288 case PPC::LXVD2X:
289 case PPC::LXV:
290 case PPC::QVLFDX:
291 case PPC::QVLFSXs:
292 case PPC::QVLFDXb:
293 case PPC::RESTORE_VRSAVE:
294 case PPC::SPILLTOVSR_LD:
295 // Check for the operands added by addFrameReference (the immediate is the
296 // offset which defaults to 0).
297 if (MI.getOperand(1).isImm() && !MI.getOperand(1).getImm() &&
298 MI.getOperand(2).isFI()) {
299 FrameIndex = MI.getOperand(2).getIndex();
300 return MI.getOperand(0).getReg();
301 }
302 break;
303 }
304 return 0;
305}
306
307// For opcodes with the ReMaterializable flag set, this function is called to
308// verify the instruction is really rematable.
309bool PPCInstrInfo::isReallyTriviallyReMaterializable(const MachineInstr &MI,
310 AliasAnalysis *AA) const {
311 switch (MI.getOpcode()) {
312 default:
313 // This function should only be called for opcodes with the ReMaterializable
314 // flag set.
315 llvm_unreachable("Unknown rematerializable operation!")::llvm::llvm_unreachable_internal("Unknown rematerializable operation!"
, "/build/llvm-toolchain-snapshot-7~svn325874/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 315)
;
316 break;
317 case PPC::LI:
318 case PPC::LI8:
319 case PPC::LIS:
320 case PPC::LIS8:
321 case PPC::QVGPCI:
322 case PPC::ADDIStocHA:
323 case PPC::ADDItocL:
324 case PPC::LOAD_STACK_GUARD:
325 return true;
326 }
327 return false;
328}
329
330unsigned PPCInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
331 int &FrameIndex) const {
332 // Note: This list must be kept consistent with StoreRegToStackSlot.
333 switch (MI.getOpcode()) {
334 default: break;
335 case PPC::STD:
336 case PPC::STW:
337 case PPC::STFS:
338 case PPC::STFD:
339 case PPC::SPILL_CR:
340 case PPC::SPILL_CRBIT:
341 case PPC::STVX:
342 case PPC::STXVD2X:
343 case PPC::STXV:
344 case PPC::QVSTFDX:
345 case PPC::QVSTFSXs:
346 case PPC::QVSTFDXb:
347 case PPC::SPILL_VRSAVE:
348 case PPC::SPILLTOVSR_ST:
349 // Check for the operands added by addFrameReference (the immediate is the
350 // offset which defaults to 0).
351 if (MI.getOperand(1).isImm() && !MI.getOperand(1).getImm() &&
352 MI.getOperand(2).isFI()) {
353 FrameIndex = MI.getOperand(2).getIndex();
354 return MI.getOperand(0).getReg();
355 }
356 break;
357 }
358 return 0;
359}
360
361MachineInstr *PPCInstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI,
362 unsigned OpIdx1,
363 unsigned OpIdx2) const {
364 MachineFunction &MF = *MI.getParent()->getParent();
365
366 // Normal instructions can be commuted the obvious way.
367 if (MI.getOpcode() != PPC::RLWIMI && MI.getOpcode() != PPC::RLWIMIo)
368 return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
369 // Note that RLWIMI can be commuted as a 32-bit instruction, but not as a
370 // 64-bit instruction (so we don't handle PPC::RLWIMI8 here), because
371 // changing the relative order of the mask operands might change what happens
372 // to the high-bits of the mask (and, thus, the result).
373
374 // Cannot commute if it has a non-zero rotate count.
375 if (MI.getOperand(3).getImm() != 0)
376 return nullptr;
377
378 // If we have a zero rotate count, we have:
379 // M = mask(MB,ME)
380 // Op0 = (Op1 & ~M) | (Op2 & M)
381 // Change this to:
382 // M = mask((ME+1)&31, (MB-1)&31)
383 // Op0 = (Op2 & ~M) | (Op1 & M)
384
385 // Swap op1/op2
386 assert(((OpIdx1 == 1 && OpIdx2 == 2) || (OpIdx1 == 2 && OpIdx2 == 1)) &&(static_cast <bool> (((OpIdx1 == 1 && OpIdx2 ==
2) || (OpIdx1 == 2 && OpIdx2 == 1)) && "Only the operands 1 and 2 can be swapped in RLSIMI/RLWIMIo."
) ? void (0) : __assert_fail ("((OpIdx1 == 1 && OpIdx2 == 2) || (OpIdx1 == 2 && OpIdx2 == 1)) && \"Only the operands 1 and 2 can be swapped in RLSIMI/RLWIMIo.\""
, "/build/llvm-toolchain-snapshot-7~svn325874/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 387, __extension__ __PRETTY_FUNCTION__))
387 "Only the operands 1 and 2 can be swapped in RLSIMI/RLWIMIo.")(static_cast <bool> (((OpIdx1 == 1 && OpIdx2 ==
2) || (OpIdx1 == 2 && OpIdx2 == 1)) && "Only the operands 1 and 2 can be swapped in RLSIMI/RLWIMIo."
) ? void (0) : __assert_fail ("((OpIdx1 == 1 && OpIdx2 == 2) || (OpIdx1 == 2 && OpIdx2 == 1)) && \"Only the operands 1 and 2 can be swapped in RLSIMI/RLWIMIo.\""
, "/build/llvm-toolchain-snapshot-7~svn325874/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 387, __extension__ __PRETTY_FUNCTION__))
;
388 unsigned Reg0 = MI.getOperand(0).getReg();
389 unsigned Reg1 = MI.getOperand(1).getReg();
390 unsigned Reg2 = MI.getOperand(2).getReg();
391 unsigned SubReg1 = MI.getOperand(1).getSubReg();
392 unsigned SubReg2 = MI.getOperand(2).getSubReg();
393 bool Reg1IsKill = MI.getOperand(1).isKill();
394 bool Reg2IsKill = MI.getOperand(2).isKill();
395 bool ChangeReg0 = false;
396 // If machine instrs are no longer in two-address forms, update
397 // destination register as well.
398 if (Reg0 == Reg1) {
399 // Must be two address instruction!
400 assert(MI.getDesc().getOperandConstraint(0, MCOI::TIED_TO) &&(static_cast <bool> (MI.getDesc().getOperandConstraint(
0, MCOI::TIED_TO) && "Expecting a two-address instruction!"
) ? void (0) : __assert_fail ("MI.getDesc().getOperandConstraint(0, MCOI::TIED_TO) && \"Expecting a two-address instruction!\""
, "/build/llvm-toolchain-snapshot-7~svn325874/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 401, __extension__ __PRETTY_FUNCTION__))
401 "Expecting a two-address instruction!")(static_cast <bool> (MI.getDesc().getOperandConstraint(
0, MCOI::TIED_TO) && "Expecting a two-address instruction!"
) ? void (0) : __assert_fail ("MI.getDesc().getOperandConstraint(0, MCOI::TIED_TO) && \"Expecting a two-address instruction!\""
, "/build/llvm-toolchain-snapshot-7~svn325874/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 401, __extension__ __PRETTY_FUNCTION__))
;
402 assert(MI.getOperand(0).getSubReg() == SubReg1 && "Tied subreg mismatch")(static_cast <bool> (MI.getOperand(0).getSubReg() == SubReg1
&& "Tied subreg mismatch") ? void (0) : __assert_fail
("MI.getOperand(0).getSubReg() == SubReg1 && \"Tied subreg mismatch\""
, "/build/llvm-toolchain-snapshot-7~svn325874/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 402, __extension__ __PRETTY_FUNCTION__))
;
403 Reg2IsKill = false;
404 ChangeReg0 = true;
405 }
406
407 // Masks.
408 unsigned MB = MI.getOperand(4).getImm();
409 unsigned ME = MI.getOperand(5).getImm();
410
411 // We can't commute a trivial mask (there is no way to represent an all-zero
412 // mask).
413 if (MB == 0 && ME == 31)
414 return nullptr;
415
416 if (NewMI) {
417 // Create a new instruction.
418 unsigned Reg0 = ChangeReg0 ? Reg2 : MI.getOperand(0).getReg();
419 bool Reg0IsDead = MI.getOperand(0).isDead();
420 return BuildMI(MF, MI.getDebugLoc(), MI.getDesc())
421 .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead))
422 .addReg(Reg2, getKillRegState(Reg2IsKill))
423 .addReg(Reg1, getKillRegState(Reg1IsKill))
424 .addImm((ME + 1) & 31)
425 .addImm((MB - 1) & 31);
426 }
427
428 if (ChangeReg0) {
429 MI.getOperand(0).setReg(Reg2);
430 MI.getOperand(0).setSubReg(SubReg2);
431 }
432 MI.getOperand(2).setReg(Reg1);
433 MI.getOperand(1).setReg(Reg2);
434 MI.getOperand(2).setSubReg(SubReg1);
435 MI.getOperand(1).setSubReg(SubReg2);
436 MI.getOperand(2).setIsKill(Reg1IsKill);
437 MI.getOperand(1).setIsKill(Reg2IsKill);
438
439 // Swap the mask around.
440 MI.getOperand(4).setImm((ME + 1) & 31);
441 MI.getOperand(5).setImm((MB - 1) & 31);
442 return &MI;
443}
444
445bool PPCInstrInfo::findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1,
446 unsigned &SrcOpIdx2) const {
447 // For VSX A-Type FMA instructions, it is the first two operands that can be
448 // commuted, however, because the non-encoded tied input operand is listed
449 // first, the operands to swap are actually the second and third.
450
451 int AltOpc = PPC::getAltVSXFMAOpcode(MI.getOpcode());
452 if (AltOpc == -1)
453 return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
454
455 // The commutable operand indices are 2 and 3. Return them in SrcOpIdx1
456 // and SrcOpIdx2.
457 return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 2, 3);
458}
459
460void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB,
461 MachineBasicBlock::iterator MI) const {
462 // This function is used for scheduling, and the nop wanted here is the type
463 // that terminates dispatch groups on the POWER cores.
464 unsigned Directive = Subtarget.getDarwinDirective();
465 unsigned Opcode;
466 switch (Directive) {
467 default: Opcode = PPC::NOP; break;
468 case PPC::DIR_PWR6: Opcode = PPC::NOP_GT_PWR6; break;
469 case PPC::DIR_PWR7: Opcode = PPC::NOP_GT_PWR7; break;
470 case PPC::DIR_PWR8: Opcode = PPC::NOP_GT_PWR7; break; /* FIXME: Update when P8 InstrScheduling model is ready */
471 // FIXME: Update when POWER9 scheduling model is ready.
472 case PPC::DIR_PWR9: Opcode = PPC::NOP_GT_PWR7; break;
473 }
474
475 DebugLoc DL;
476 BuildMI(MBB, MI, DL, get(Opcode));
477}
478
479/// Return the noop instruction to use for a noop.
480void PPCInstrInfo::getNoop(MCInst &NopInst) const {
481 NopInst.setOpcode(PPC::NOP);
482}
483
484// Branch analysis.
485// Note: If the condition register is set to CTR or CTR8 then this is a
486// BDNZ (imm == 1) or BDZ (imm == 0) branch.
487bool PPCInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
488 MachineBasicBlock *&TBB,
489 MachineBasicBlock *&FBB,
490 SmallVectorImpl<MachineOperand> &Cond,
491 bool AllowModify) const {
492 bool isPPC64 = Subtarget.isPPC64();
493
494 // If the block has no terminators, it just falls into the block after it.
495 MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
496 if (I == MBB.end())
497 return false;
498
499 if (!isUnpredicatedTerminator(*I))
500 return false;
501
502 if (AllowModify) {
503 // If the BB ends with an unconditional branch to the fallthrough BB,
504 // we eliminate the branch instruction.
505 if (I->getOpcode() == PPC::B &&
506 MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
507 I->eraseFromParent();
508
509 // We update iterator after deleting the last branch.
510 I = MBB.getLastNonDebugInstr();
511 if (I == MBB.end() || !isUnpredicatedTerminator(*I))
512 return false;
513 }
514 }
515
516 // Get the last instruction in the block.
517 MachineInstr &LastInst = *I;
518
519 // If there is only one terminator instruction, process it.
520 if (I == MBB.begin() || !isUnpredicatedTerminator(*--I)) {
521 if (LastInst.getOpcode() == PPC::B) {
522 if (!LastInst.getOperand(0).isMBB())
523 return true;
524 TBB = LastInst.getOperand(0).getMBB();
525 return false;
526 } else if (LastInst.getOpcode() == PPC::BCC) {
527 if (!LastInst.getOperand(2).isMBB())
528 return true;
529 // Block ends with fall-through condbranch.
530 TBB = LastInst.getOperand(2).getMBB();
531 Cond.push_back(LastInst.getOperand(0));
532 Cond.push_back(LastInst.getOperand(1));
533 return false;
534 } else if (LastInst.getOpcode() == PPC::BC) {
535 if (!LastInst.getOperand(1).isMBB())
536 return true;
537 // Block ends with fall-through condbranch.
538 TBB = LastInst.getOperand(1).getMBB();
539 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET));
540 Cond.push_back(LastInst.getOperand(0));
541 return false;
542 } else if (LastInst.getOpcode() == PPC::BCn) {
543 if (!LastInst.getOperand(1).isMBB())
544 return true;
545 // Block ends with fall-through condbranch.
546 TBB = LastInst.getOperand(1).getMBB();
547 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_UNSET));
548 Cond.push_back(LastInst.getOperand(0));
549 return false;
550 } else if (LastInst.getOpcode() == PPC::BDNZ8 ||
551 LastInst.getOpcode() == PPC::BDNZ) {
552 if (!LastInst.getOperand(0).isMBB())
553 return true;
554 if (DisableCTRLoopAnal)
555 return true;
556 TBB = LastInst.getOperand(0).getMBB();
557 Cond.push_back(MachineOperand::CreateImm(1));
558 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
559 true));
560 return false;
561 } else if (LastInst.getOpcode() == PPC::BDZ8 ||
562 LastInst.getOpcode() == PPC::BDZ) {
563 if (!LastInst.getOperand(0).isMBB())
564 return true;
565 if (DisableCTRLoopAnal)
566 return true;
567 TBB = LastInst.getOperand(0).getMBB();
568 Cond.push_back(MachineOperand::CreateImm(0));
569 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
570 true));
571 return false;
572 }
573
574 // Otherwise, don't know what this is.
575 return true;
576 }
577
578 // Get the instruction before it if it's a terminator.
579 MachineInstr &SecondLastInst = *I;
580
581 // If there are three terminators, we don't know what sort of block this is.
582 if (I != MBB.begin() && isUnpredicatedTerminator(*--I))
583 return true;
584
585 // If the block ends with PPC::B and PPC:BCC, handle it.
586 if (SecondLastInst.getOpcode() == PPC::BCC &&
587 LastInst.getOpcode() == PPC::B) {
588 if (!SecondLastInst.getOperand(2).isMBB() ||
589 !LastInst.getOperand(0).isMBB())
590 return true;
591 TBB = SecondLastInst.getOperand(2).getMBB();
592 Cond.push_back(SecondLastInst.getOperand(0));
593 Cond.push_back(SecondLastInst.getOperand(1));
594 FBB = LastInst.getOperand(0).getMBB();
595 return false;
596 } else if (SecondLastInst.getOpcode() == PPC::BC &&
597 LastInst.getOpcode() == PPC::B) {
598 if (!SecondLastInst.getOperand(1).isMBB() ||
599 !LastInst.getOperand(0).isMBB())
600 return true;
601 TBB = SecondLastInst.getOperand(1).getMBB();
602 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET));
603 Cond.push_back(SecondLastInst.getOperand(0));
604 FBB = LastInst.getOperand(0).getMBB();
605 return false;
606 } else if (SecondLastInst.getOpcode() == PPC::BCn &&
607 LastInst.getOpcode() == PPC::B) {
608 if (!SecondLastInst.getOperand(1).isMBB() ||
609 !LastInst.getOperand(0).isMBB())
610 return true;
611 TBB = SecondLastInst.getOperand(1).getMBB();
612 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_UNSET));
613 Cond.push_back(SecondLastInst.getOperand(0));
614 FBB = LastInst.getOperand(0).getMBB();
615 return false;
616 } else if ((SecondLastInst.getOpcode() == PPC::BDNZ8 ||
617 SecondLastInst.getOpcode() == PPC::BDNZ) &&
618 LastInst.getOpcode() == PPC::B) {
619 if (!SecondLastInst.getOperand(0).isMBB() ||
620 !LastInst.getOperand(0).isMBB())
621 return true;
622 if (DisableCTRLoopAnal)
623 return true;
624 TBB = SecondLastInst.getOperand(0).getMBB();
625 Cond.push_back(MachineOperand::CreateImm(1));
626 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
627 true));
628 FBB = LastInst.getOperand(0).getMBB();
629 return false;
630 } else if ((SecondLastInst.getOpcode() == PPC::BDZ8 ||
631 SecondLastInst.getOpcode() == PPC::BDZ) &&
632 LastInst.getOpcode() == PPC::B) {
633 if (!SecondLastInst.getOperand(0).isMBB() ||
634 !LastInst.getOperand(0).isMBB())
635 return true;
636 if (DisableCTRLoopAnal)
637 return true;
638 TBB = SecondLastInst.getOperand(0).getMBB();
639 Cond.push_back(MachineOperand::CreateImm(0));
640 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
641 true));
642 FBB = LastInst.getOperand(0).getMBB();
643 return false;
644 }
645
646 // If the block ends with two PPC:Bs, handle it. The second one is not
647 // executed, so remove it.
648 if (SecondLastInst.getOpcode() == PPC::B && LastInst.getOpcode() == PPC::B) {
649 if (!SecondLastInst.getOperand(0).isMBB())
650 return true;
651 TBB = SecondLastInst.getOperand(0).getMBB();
652 I = LastInst;
653 if (AllowModify)
654 I->eraseFromParent();
655 return false;
656 }
657
658 // Otherwise, can't handle this.
659 return true;
660}
661
662unsigned PPCInstrInfo::removeBranch(MachineBasicBlock &MBB,
663 int *BytesRemoved) const {
664 assert(!BytesRemoved && "code size not handled")(static_cast <bool> (!BytesRemoved && "code size not handled"
) ? void (0) : __assert_fail ("!BytesRemoved && \"code size not handled\""
, "/build/llvm-toolchain-snapshot-7~svn325874/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 664, __extension__ __PRETTY_FUNCTION__))
;
665
666 MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
667 if (I == MBB.end())
668 return 0;
669
670 if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC &&
671 I->getOpcode() != PPC::BC && I->getOpcode() != PPC::BCn &&
672 I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ &&
673 I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ)
674 return 0;
675
676 // Remove the branch.
677 I->eraseFromParent();
678
679 I = MBB.end();
680
681 if (I == MBB.begin()) return 1;
682 --I;
683 if (I->getOpcode() != PPC::BCC &&
684 I->getOpcode() != PPC::BC && I->getOpcode() != PPC::BCn &&
685 I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ &&
686 I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ)
687 return 1;
688
689 // Remove the branch.
690 I->eraseFromParent();
691 return 2;
692}
693
694unsigned PPCInstrInfo::insertBranch(MachineBasicBlock &MBB,
695 MachineBasicBlock *TBB,
696 MachineBasicBlock *FBB,
697 ArrayRef<MachineOperand> Cond,
698 const DebugLoc &DL,
699 int *BytesAdded) const {
700 // Shouldn't be a fall through.
701 assert(TBB && "insertBranch must not be told to insert a fallthrough")(static_cast <bool> (TBB && "insertBranch must not be told to insert a fallthrough"
) ? void (0) : __assert_fail ("TBB && \"insertBranch must not be told to insert a fallthrough\""
, "/build/llvm-toolchain-snapshot-7~svn325874/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 701, __extension__ __PRETTY_FUNCTION__))
;
702 assert((Cond.size() == 2 || Cond.size() == 0) &&(static_cast <bool> ((Cond.size() == 2 || Cond.size() ==
0) && "PPC branch conditions have two components!") ?
void (0) : __assert_fail ("(Cond.size() == 2 || Cond.size() == 0) && \"PPC branch conditions have two components!\""
, "/build/llvm-toolchain-snapshot-7~svn325874/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 703, __extension__ __PRETTY_FUNCTION__))
703 "PPC branch conditions have two components!")(static_cast <bool> ((Cond.size() == 2 || Cond.size() ==
0) && "PPC branch conditions have two components!") ?
void (0) : __assert_fail ("(Cond.size() == 2 || Cond.size() == 0) && \"PPC branch conditions have two components!\""
, "/build/llvm-toolchain-snapshot-7~svn325874/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 703, __extension__ __PRETTY_FUNCTION__))
;
704 assert(!BytesAdded && "code size not handled")(static_cast <bool> (!BytesAdded && "code size not handled"
) ? void (0) : __assert_fail ("!BytesAdded && \"code size not handled\""
, "/build/llvm-toolchain-snapshot-7~svn325874/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 704, __extension__ __PRETTY_FUNCTION__))
;
705
706 bool isPPC64 = Subtarget.isPPC64();
707
708 // One-way branch.
709 if (!FBB) {
710 if (Cond.empty()) // Unconditional branch
711 BuildMI(&MBB, DL, get(PPC::B)).addMBB(TBB);
712 else if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
713 BuildMI(&MBB, DL, get(Cond[0].getImm() ?
714 (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
715 (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB);
716 else if (Cond[0].getImm() == PPC::PRED_BIT_SET)
717 BuildMI(&MBB, DL, get(PPC::BC)).add(Cond[1]).addMBB(TBB);
718 else if (Cond[0].getImm() == PPC::PRED_BIT_UNSET)
719 BuildMI(&MBB, DL, get(PPC::BCn)).add(Cond[1]).addMBB(TBB);
720 else // Conditional branch
721 BuildMI(&MBB, DL, get(PPC::BCC))
722 .addImm(Cond[0].getImm())
723 .add(Cond[1])
724 .addMBB(TBB);
725 return 1;
726 }
727
728 // Two-way Conditional Branch.
729 if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
730 BuildMI(&MBB, DL, get(Cond[0].getImm() ?
731 (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
732 (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB);
733 else if (Cond[0].getImm() == PPC::PRED_BIT_SET)
734 BuildMI(&MBB, DL, get(PPC::BC)).add(Cond[1]).addMBB(TBB);
735 else if (Cond[0].getImm() == PPC::PRED_BIT_UNSET)
736 BuildMI(&MBB, DL, get(PPC::BCn)).add(Cond[1]).addMBB(TBB);
737 else
738 BuildMI(&MBB, DL, get(PPC::BCC))
739 .addImm(Cond[0].getImm())
740 .add(Cond[1])
741 .addMBB(TBB);
742 BuildMI(&MBB, DL, get(PPC::B)).addMBB(FBB);
743 return 2;
744}
745
746// Select analysis.
747bool PPCInstrInfo::canInsertSelect(const MachineBasicBlock &MBB,
748 ArrayRef<MachineOperand> Cond,
749 unsigned TrueReg, unsigned FalseReg,
750 int &CondCycles, int &TrueCycles, int &FalseCycles) const {
751 if (Cond.size() != 2)
752 return false;
753
754 // If this is really a bdnz-like condition, then it cannot be turned into a
755 // select.
756 if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
757 return false;
758
759 // Check register classes.
760 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
761 const TargetRegisterClass *RC =
762 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
763 if (!RC)
764 return false;
765
766 // isel is for regular integer GPRs only.
767 if (!PPC::GPRCRegClass.hasSubClassEq(RC) &&
768 !PPC::GPRC_NOR0RegClass.hasSubClassEq(RC) &&
769 !PPC::G8RCRegClass.hasSubClassEq(RC) &&
770 !PPC::G8RC_NOX0RegClass.hasSubClassEq(RC))
771 return false;
772
773 // FIXME: These numbers are for the A2, how well they work for other cores is
774 // an open question. On the A2, the isel instruction has a 2-cycle latency
775 // but single-cycle throughput. These numbers are used in combination with
776 // the MispredictPenalty setting from the active SchedMachineModel.
777 CondCycles = 1;
778 TrueCycles = 1;
779 FalseCycles = 1;
780
781 return true;
782}
783
784void PPCInstrInfo::insertSelect(MachineBasicBlock &MBB,
785 MachineBasicBlock::iterator MI,
786 const DebugLoc &dl, unsigned DestReg,
787 ArrayRef<MachineOperand> Cond, unsigned TrueReg,
788 unsigned FalseReg) const {
789 assert(Cond.size() == 2 &&(static_cast <bool> (Cond.size() == 2 && "PPC branch conditions have two components!"
) ? void (0) : __assert_fail ("Cond.size() == 2 && \"PPC branch conditions have two components!\""
, "/build/llvm-toolchain-snapshot-7~svn325874/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 790, __extension__ __PRETTY_FUNCTION__))
790 "PPC branch conditions have two components!")(static_cast <bool> (Cond.size() == 2 && "PPC branch conditions have two components!"
) ? void (0) : __assert_fail ("Cond.size() == 2 && \"PPC branch conditions have two components!\""
, "/build/llvm-toolchain-snapshot-7~svn325874/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 790, __extension__ __PRETTY_FUNCTION__))
;
791
792 // Get the register classes.
793 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
794 const TargetRegisterClass *RC =
795 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
796 assert(RC && "TrueReg and FalseReg must have overlapping register classes")(static_cast <bool> (RC && "TrueReg and FalseReg must have overlapping register classes"
) ? void (0) : __assert_fail ("RC && \"TrueReg and FalseReg must have overlapping register classes\""
, "/build/llvm-toolchain-snapshot-7~svn325874/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 796, __extension__ __PRETTY_FUNCTION__))
;
797
798 bool Is64Bit = PPC::G8RCRegClass.hasSubClassEq(RC) ||
799 PPC::G8RC_NOX0RegClass.hasSubClassEq(RC);
800 assert((Is64Bit ||(static_cast <bool> ((Is64Bit || PPC::GPRCRegClass.hasSubClassEq
(RC) || PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) && "isel is for regular integer GPRs only"
) ? void (0) : __assert_fail ("(Is64Bit || PPC::GPRCRegClass.hasSubClassEq(RC) || PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) && \"isel is for regular integer GPRs only\""
, "/build/llvm-toolchain-snapshot-7~svn325874/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 803, __extension__ __PRETTY_FUNCTION__))
801 PPC::GPRCRegClass.hasSubClassEq(RC) ||(static_cast <bool> ((Is64Bit || PPC::GPRCRegClass.hasSubClassEq
(RC) || PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) && "isel is for regular integer GPRs only"
) ? void (0) : __assert_fail ("(Is64Bit || PPC::GPRCRegClass.hasSubClassEq(RC) || PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) && \"isel is for regular integer GPRs only\""
, "/build/llvm-toolchain-snapshot-7~svn325874/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 803, __extension__ __PRETTY_FUNCTION__))
802 PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) &&(static_cast <bool> ((Is64Bit || PPC::GPRCRegClass.hasSubClassEq
(RC) || PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) && "isel is for regular integer GPRs only"
) ? void (0) : __assert_fail ("(Is64Bit || PPC::GPRCRegClass.hasSubClassEq(RC) || PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) && \"isel is for regular integer GPRs only\""
, "/build/llvm-toolchain-snapshot-7~svn325874/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 803, __extension__ __PRETTY_FUNCTION__))
803 "isel is for regular integer GPRs only")(static_cast <bool> ((Is64Bit || PPC::GPRCRegClass.hasSubClassEq
(RC) || PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) && "isel is for regular integer GPRs only"
) ? void (0) : __assert_fail ("(Is64Bit || PPC::GPRCRegClass.hasSubClassEq(RC) || PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) && \"isel is for regular integer GPRs only\""
, "/build/llvm-toolchain-snapshot-7~svn325874/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 803, __extension__ __PRETTY_FUNCTION__))
;
804
805 unsigned OpCode = Is64Bit ? PPC::ISEL8 : PPC::ISEL;
806 auto SelectPred = static_cast<PPC::Predicate>(Cond[0].getImm());
807
808 unsigned SubIdx = 0;
809 bool SwapOps = false;
810 switch (SelectPred) {
811 case PPC::PRED_EQ:
812 case PPC::PRED_EQ_MINUS:
813 case PPC::PRED_EQ_PLUS:
814 SubIdx = PPC::sub_eq; SwapOps = false; break;
815 case PPC::PRED_NE:
816 case PPC::PRED_NE_MINUS:
817 case PPC::PRED_NE_PLUS:
818 SubIdx = PPC::sub_eq; SwapOps = true; break;
819 case PPC::PRED_LT:
820 case PPC::PRED_LT_MINUS:
821 case PPC::PRED_LT_PLUS:
822 SubIdx = PPC::sub_lt; SwapOps = false; break;
823 case PPC::PRED_GE:
824 case PPC::PRED_GE_MINUS:
825 case PPC::PRED_GE_PLUS:
826 SubIdx = PPC::sub_lt; SwapOps = true; break;
827 case PPC::PRED_GT:
828 case PPC::PRED_GT_MINUS:
829 case PPC::PRED_GT_PLUS:
830 SubIdx = PPC::sub_gt; SwapOps = false; break;
831 case PPC::PRED_LE:
832 case PPC::PRED_LE_MINUS:
833 case PPC::PRED_LE_PLUS:
834 SubIdx = PPC::sub_gt; SwapOps = true; break;
835 case PPC::PRED_UN:
836 case PPC::PRED_UN_MINUS:
837 case PPC::PRED_UN_PLUS:
838 SubIdx = PPC::sub_un; SwapOps = false; break;
839 case PPC::PRED_NU:
840 case PPC::PRED_NU_MINUS:
841 case PPC::PRED_NU_PLUS:
842 SubIdx = PPC::sub_un; SwapOps = true; break;
843 case PPC::PRED_BIT_SET: SubIdx = 0; SwapOps = false; break;
844 case PPC::PRED_BIT_UNSET: SubIdx = 0; SwapOps = true; break;
845 }
846
847 unsigned FirstReg = SwapOps ? FalseReg : TrueReg,
848 SecondReg = SwapOps ? TrueReg : FalseReg;
849
850 // The first input register of isel cannot be r0. If it is a member
851 // of a register class that can be r0, then copy it first (the
852 // register allocator should eliminate the copy).
853 if (MRI.getRegClass(FirstReg)->contains(PPC::R0) ||
854 MRI.getRegClass(FirstReg)->contains(PPC::X0)) {
855 const TargetRegisterClass *FirstRC =
856 MRI.getRegClass(FirstReg)->contains(PPC::X0) ?
857 &PPC::G8RC_NOX0RegClass : &PPC::GPRC_NOR0RegClass;
858 unsigned OldFirstReg = FirstReg;
859 FirstReg = MRI.createVirtualRegister(FirstRC);
860 BuildMI(MBB, MI, dl, get(TargetOpcode::COPY), FirstReg)
861 .addReg(OldFirstReg);
862 }
863
864 BuildMI(MBB, MI, dl, get(OpCode), DestReg)
865 .addReg(FirstReg).addReg(SecondReg)
866 .addReg(Cond[1].getReg(), 0, SubIdx);
867}
868
869static unsigned getCRBitValue(unsigned CRBit) {
870 unsigned Ret = 4;
871 if (CRBit == PPC::CR0LT || CRBit == PPC::CR1LT ||
872 CRBit == PPC::CR2LT || CRBit == PPC::CR3LT ||
873 CRBit == PPC::CR4LT || CRBit == PPC::CR5LT ||
874 CRBit == PPC::CR6LT || CRBit == PPC::CR7LT)
875 Ret = 3;
876 if (CRBit == PPC::CR0GT || CRBit == PPC::CR1GT ||
877 CRBit == PPC::CR2GT || CRBit == PPC::CR3GT ||
878 CRBit == PPC::CR4GT || CRBit == PPC::CR5GT ||
879 CRBit == PPC::CR6GT || CRBit == PPC::CR7GT)
880 Ret = 2;
881 if (CRBit == PPC::CR0EQ || CRBit == PPC::CR1EQ ||
882 CRBit == PPC::CR2EQ || CRBit == PPC::CR3EQ ||
883 CRBit == PPC::CR4EQ || CRBit == PPC::CR5EQ ||
884 CRBit == PPC::CR6EQ || CRBit == PPC::CR7EQ)
885 Ret = 1;
886 if (CRBit == PPC::CR0UN || CRBit == PPC::CR1UN ||
887 CRBit == PPC::CR2UN || CRBit == PPC::CR3UN ||
888 CRBit == PPC::CR4UN || CRBit == PPC::CR5UN ||
889 CRBit == PPC::CR6UN || CRBit == PPC::CR7UN)
890 Ret = 0;
891
892 assert(Ret != 4 && "Invalid CR bit register")(static_cast <bool> (Ret != 4 && "Invalid CR bit register"
) ? void (0) : __assert_fail ("Ret != 4 && \"Invalid CR bit register\""
, "/build/llvm-toolchain-snapshot-7~svn325874/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 892, __extension__ __PRETTY_FUNCTION__))
;
893 return Ret;
894}
895
896void PPCInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
897 MachineBasicBlock::iterator I,
898 const DebugLoc &DL, unsigned DestReg,
899 unsigned SrcReg, bool KillSrc) const {
900 // We can end up with self copies and similar things as a result of VSX copy
901 // legalization. Promote them here.
902 const TargetRegisterInfo *TRI = &getRegisterInfo();
903 if (PPC::F8RCRegClass.contains(DestReg) &&
904 PPC::VSRCRegClass.contains(SrcReg)) {
905 unsigned SuperReg =
906 TRI->getMatchingSuperReg(DestReg, PPC::sub_64, &PPC::VSRCRegClass);
907
908 if (VSXSelfCopyCrash && SrcReg == SuperReg)
909 llvm_unreachable("nop VSX copy")::llvm::llvm_unreachable_internal("nop VSX copy", "/build/llvm-toolchain-snapshot-7~svn325874/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 909)
;
910
911 DestReg = SuperReg;
912 } else if (PPC::F8RCRegClass.contains(SrcReg) &&
913 PPC::VSRCRegClass.contains(DestReg)) {
914 unsigned SuperReg =
915 TRI->getMatchingSuperReg(SrcReg, PPC::sub_64, &PPC::VSRCRegClass);
916
917 if (VSXSelfCopyCrash && DestReg == SuperReg)
918 llvm_unreachable("nop VSX copy")::llvm::llvm_unreachable_internal("nop VSX copy", "/build/llvm-toolchain-snapshot-7~svn325874/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 918)
;
919
920 SrcReg = SuperReg;
921 }
922
923 // Different class register copy
924 if (PPC::CRBITRCRegClass.contains(SrcReg) &&
925 PPC::GPRCRegClass.contains(DestReg)) {
926 unsigned CRReg = getCRFromCRBit(SrcReg);
927 BuildMI(MBB, I, DL, get(PPC::MFOCRF), DestReg).addReg(CRReg);
928 getKillRegState(KillSrc);
929 // Rotate the CR bit in the CR fields to be the least significant bit and
930 // then mask with 0x1 (MB = ME = 31).
931 BuildMI(MBB, I, DL, get(PPC::RLWINM), DestReg)
932 .addReg(DestReg, RegState::Kill)
933 .addImm(TRI->getEncodingValue(CRReg) * 4 + (4 - getCRBitValue(SrcReg)))
934 .addImm(31)
935 .addImm(31);
936 return;
937 } else if (PPC::CRRCRegClass.contains(SrcReg) &&
938 PPC::G8RCRegClass.contains(DestReg)) {
939 BuildMI(MBB, I, DL, get(PPC::MFOCRF8), DestReg).addReg(SrcReg);
940 getKillRegState(KillSrc);
941 return;
942 } else if (PPC::CRRCRegClass.contains(SrcReg) &&
943 PPC::GPRCRegClass.contains(DestReg)) {
944 BuildMI(MBB, I, DL, get(PPC::MFOCRF), DestReg).addReg(SrcReg);
945 getKillRegState(KillSrc);
946 return;
947 } else if (PPC::G8RCRegClass.contains(SrcReg) &&
948 PPC::VSFRCRegClass.contains(DestReg)) {
949 BuildMI(MBB, I, DL, get(PPC::MTVSRD), DestReg).addReg(SrcReg);
950 NumGPRtoVSRSpill++;
951 getKillRegState(KillSrc);
952 return;
953 } else if (PPC::VSFRCRegClass.contains(SrcReg) &&
954 PPC::G8RCRegClass.contains(DestReg)) {
955 BuildMI(MBB, I, DL, get(PPC::MFVSRD), DestReg).addReg(SrcReg);
956 getKillRegState(KillSrc);
957 return;
958 }
959
960 unsigned Opc;
961 if (PPC::GPRCRegClass.contains(DestReg, SrcReg))
962 Opc = PPC::OR;
963 else if (PPC::G8RCRegClass.contains(DestReg, SrcReg))
964 Opc = PPC::OR8;
965 else if (PPC::F4RCRegClass.contains(DestReg, SrcReg))
966 Opc = PPC::FMR;
967 else if (PPC::CRRCRegClass.contains(DestReg, SrcReg))
968 Opc = PPC::MCRF;
969 else if (PPC::VRRCRegClass.contains(DestReg, SrcReg))
970 Opc = PPC::VOR;
971 else if (PPC::VSRCRegClass.contains(DestReg, SrcReg))
972 // There are two different ways this can be done:
973 // 1. xxlor : This has lower latency (on the P7), 2 cycles, but can only
974 // issue in VSU pipeline 0.
975 // 2. xmovdp/xmovsp: This has higher latency (on the P7), 6 cycles, but
976 // can go to either pipeline.
977 // We'll always use xxlor here, because in practically all cases where
978 // copies are generated, they are close enough to some use that the
979 // lower-latency form is preferable.
980 Opc = PPC::XXLOR;
981 else if (PPC::VSFRCRegClass.contains(DestReg, SrcReg) ||
982 PPC::VSSRCRegClass.contains(DestReg, SrcReg))
983 Opc = PPC::XXLORf;
984 else if (PPC::QFRCRegClass.contains(DestReg, SrcReg))
985 Opc = PPC::QVFMR;
986 else if (PPC::QSRCRegClass.contains(DestReg, SrcReg))
987 Opc = PPC::QVFMRs;
988 else if (PPC::QBRCRegClass.contains(DestReg, SrcReg))
989 Opc = PPC::QVFMRb;
990 else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg))
991 Opc = PPC::CROR;
992 else
993 llvm_unreachable("Impossible reg-to-reg copy")::llvm::llvm_unreachable_internal("Impossible reg-to-reg copy"
, "/build/llvm-toolchain-snapshot-7~svn325874/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 993)
;
994
995 const MCInstrDesc &MCID = get(Opc);
996 if (MCID.getNumOperands() == 3)
997 BuildMI(MBB, I, DL, MCID, DestReg)
998 .addReg(SrcReg).addReg(SrcReg, getKillRegState(KillSrc));
999 else
1000 BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc));
1001}
1002
1003// This function returns true if a CR spill is necessary and false otherwise.
1004bool
1005PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF,
1006 unsigned SrcReg, bool isKill,
1007 int FrameIdx,
1008 const TargetRegisterClass *RC,
1009 SmallVectorImpl<MachineInstr*> &NewMIs,
1010 bool &NonRI, bool &SpillsVRS) const{
1011 // Note: If additional store instructions are added here,
1012 // update isStoreToStackSlot.
1013
1014 DebugLoc DL;
1015 if (PPC::GPRCRegClass.hasSubClassEq(RC) ||
1016 PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) {
1017 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
1018 .addReg(SrcReg,
1019 getKillRegState(isKill)),
1020 FrameIdx));
1021 } else if (PPC::G8RCRegClass.hasSubClassEq(RC) ||
1022 PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) {
1023 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD))
1024 .addReg(SrcReg,
1025 getKillRegState(isKill)),
1026 FrameIdx));
1027 } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
1028 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFD))
1029 .addReg(SrcReg,
1030 getKillRegState(isKill)),
1031 FrameIdx));
1032 } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
1033 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFS))
1034 .addReg(SrcReg,
1035 getKillRegState(isKill)),
1036 FrameIdx));
1037 } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
1038 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CR))
1039 .addReg(SrcReg,
1040 getKillRegState(isKill)),
1041 FrameIdx));
1042 return true;
1043 } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
1044 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CRBIT))
1045 .addReg(SrcReg,
1046 getKillRegState(isKill)),
1047 FrameIdx));
1048 return true;
1049 } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
1050 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STVX))
1051 .addReg(SrcReg,
1052 getKillRegState(isKill)),
1053 FrameIdx));
1054 NonRI = true;
1055 } else if (PPC::VSRCRegClass.hasSubClassEq(RC)) {
1056 unsigned Op = Subtarget.hasP9Vector() ? PPC::STXV : PPC::STXVD2X;
1057 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(Op))
1058 .addReg(SrcReg,
1059 getKillRegState(isKill)),
1060 FrameIdx));
1061 NonRI = true;
1062 } else if (PPC::VSFRCRegClass.hasSubClassEq(RC)) {
1063 unsigned Opc = Subtarget.hasP9Vector() ? PPC::DFSTOREf64 : PPC::STXSDX;
1064 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(Opc))
1065 .addReg(SrcReg,
1066 getKillRegState(isKill)),
1067 FrameIdx));
1068 NonRI = true;
1069 } else if (PPC::VSSRCRegClass.hasSubClassEq(RC)) {
1070 unsigned Opc = Subtarget.hasP9Vector() ? PPC::DFSTOREf32 : PPC::STXSSPX;
1071 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(Opc))
1072 .addReg(SrcReg,
1073 getKillRegState(isKill)),
1074 FrameIdx));
1075 NonRI = true;
1076 } else if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) {
1077 assert(Subtarget.isDarwin() &&(static_cast <bool> (Subtarget.isDarwin() && "VRSAVE only needs spill/restore on Darwin"
) ? void (0) : __assert_fail ("Subtarget.isDarwin() && \"VRSAVE only needs spill/restore on Darwin\""
, "/build/llvm-toolchain-snapshot-7~svn325874/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 1078, __extension__ __PRETTY_FUNCTION__))
1078 "VRSAVE only needs spill/restore on Darwin")(static_cast <bool> (Subtarget.isDarwin() && "VRSAVE only needs spill/restore on Darwin"
) ? void (0) : __assert_fail ("Subtarget.isDarwin() && \"VRSAVE only needs spill/restore on Darwin\""
, "/build/llvm-toolchain-snapshot-7~svn325874/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 1078, __extension__ __PRETTY_FUNCTION__))
;
1079 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_VRSAVE))
1080 .addReg(SrcReg,
1081 getKillRegState(isKill)),
1082 FrameIdx));
1083 SpillsVRS = true;
1084 } else if (PPC::QFRCRegClass.hasSubClassEq(RC)) {
1085 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::QVSTFDX))
1086 .addReg(SrcReg,
1087 getKillRegState(isKill)),
1088 FrameIdx));
1089 NonRI = true;
1090 } else if (PPC::QSRCRegClass.hasSubClassEq(RC)) {
1091 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::QVSTFSXs))
1092 .addReg(SrcReg,
1093 getKillRegState(isKill)),
1094 FrameIdx));
1095 NonRI = true;
1096 } else if (PPC::QBRCRegClass.hasSubClassEq(RC)) {
1097 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::QVSTFDXb))
1098 .addReg(SrcReg,
1099 getKillRegState(isKill)),
1100 FrameIdx));
1101 NonRI = true;
1102 } else if (PPC::SPILLTOVSRRCRegClass.hasSubClassEq(RC)) {
1103 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILLTOVSR_ST))
1104 .addReg(SrcReg,
1105 getKillRegState(isKill)),
1106 FrameIdx));
1107 } else {
1108 llvm_unreachable("Unknown regclass!")::llvm::llvm_unreachable_internal("Unknown regclass!", "/build/llvm-toolchain-snapshot-7~svn325874/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 1108)
;
1109 }
1110
1111 return false;
1112}
1113
1114void
1115PPCInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
1116 MachineBasicBlock::iterator MI,
1117 unsigned SrcReg, bool isKill, int FrameIdx,
1118 const TargetRegisterClass *RC,
1119 const TargetRegisterInfo *TRI) const {
1120 MachineFunction &MF = *MBB.getParent();
1121 SmallVector<MachineInstr*, 4> NewMIs;
1122
1123 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1124 FuncInfo->setHasSpills();
1125
1126 // We need to avoid a situation in which the value from a VRRC register is
1127 // spilled using an Altivec instruction and reloaded into a VSRC register
1128 // using a VSX instruction. The issue with this is that the VSX
1129 // load/store instructions swap the doublewords in the vector and the Altivec
1130 // ones don't. The register classes on the spill/reload may be different if
1131 // the register is defined using an Altivec instruction and is then used by a
1132 // VSX instruction.
1133 RC = updatedRC(RC);
1134
1135 bool NonRI = false, SpillsVRS = false;
1136 if (StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs,
1137 NonRI, SpillsVRS))
1138 FuncInfo->setSpillsCR();
1139
1140 if (SpillsVRS)
1141 FuncInfo->setSpillsVRSAVE();
1142
1143 if (NonRI)
1144 FuncInfo->setHasNonRISpills();
1145
1146 for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
1147 MBB.insert(MI, NewMIs[i]);
1148
1149 const MachineFrameInfo &MFI = MF.getFrameInfo();
1150 MachineMemOperand *MMO = MF.getMachineMemOperand(
1151 MachinePointerInfo::getFixedStack(MF, FrameIdx),
1152 MachineMemOperand::MOStore, MFI.getObjectSize(FrameIdx),
1153 MFI.getObjectAlignment(FrameIdx));
1154 NewMIs.back()->addMemOperand(MF, MMO);
1155}
1156
1157bool PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, const DebugLoc &DL,
1158 unsigned DestReg, int FrameIdx,
1159 const TargetRegisterClass *RC,
1160 SmallVectorImpl<MachineInstr *> &NewMIs,
1161 bool &NonRI, bool &SpillsVRS) const {
1162 // Note: If additional load instructions are added here,
1163 // update isLoadFromStackSlot.
1164
1165 if (PPC::GPRCRegClass.hasSubClassEq(RC) ||
1166 PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) {
1167 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
1168 DestReg), FrameIdx));
1169 } else if (PPC::G8RCRegClass.hasSubClassEq(RC) ||
1170 PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) {
1171 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD), DestReg),
1172 FrameIdx));
1173 } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
1174 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFD), DestReg),
1175 FrameIdx));
1176 } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
1177 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFS), DestReg),
1178 FrameIdx));
1179 } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
1180 NewMIs.push_back(addFrameReference(BuildMI(MF, DL,
1181 get(PPC::RESTORE_CR), DestReg),
1182 FrameIdx));
1183 return true;
1184 } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
1185 NewMIs.push_back(addFrameReference(BuildMI(MF, DL,
1186 get(PPC::RESTORE_CRBIT), DestReg),
1187 FrameIdx));
1188 return true;
1189 } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
1190 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LVX), DestReg),
1191 FrameIdx));
1192 NonRI = true;
1193 } else if (PPC::VSRCRegClass.hasSubClassEq(RC)) {
1194 unsigned Op = Subtarget.hasP9Vector() ? PPC::LXV : PPC::LXVD2X;
1195 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(Op), DestReg),
1196 FrameIdx));
1197 NonRI = true;
1198 } else if (PPC::VSFRCRegClass.hasSubClassEq(RC)) {
1199 unsigned Opc = Subtarget.hasP9Vector() ? PPC::DFLOADf64 : PPC::LXSDX;
1200 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(Opc),
1201 DestReg), FrameIdx));
1202 NonRI = true;
1203 } else if (PPC::VSSRCRegClass.hasSubClassEq(RC)) {
1204 unsigned Opc = Subtarget.hasP9Vector() ? PPC::DFLOADf32 : PPC::LXSSPX;
1205 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(Opc),
1206 DestReg), FrameIdx));
1207 NonRI = true;
1208 } else if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) {
1209 assert(Subtarget.isDarwin() &&(static_cast <bool> (Subtarget.isDarwin() && "VRSAVE only needs spill/restore on Darwin"
) ? void (0) : __assert_fail ("Subtarget.isDarwin() && \"VRSAVE only needs spill/restore on Darwin\""
, "/build/llvm-toolchain-snapshot-7~svn325874/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 1210, __extension__ __PRETTY_FUNCTION__))
1210 "VRSAVE only needs spill/restore on Darwin")(static_cast <bool> (Subtarget.isDarwin() && "VRSAVE only needs spill/restore on Darwin"
) ? void (0) : __assert_fail ("Subtarget.isDarwin() && \"VRSAVE only needs spill/restore on Darwin\""
, "/build/llvm-toolchain-snapshot-7~svn325874/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 1210, __extension__ __PRETTY_FUNCTION__))
;
1211 NewMIs.push_back(addFrameReference(BuildMI(MF, DL,
1212 get(PPC::RESTORE_VRSAVE),
1213 DestReg),
1214 FrameIdx));
1215 SpillsVRS = true;
1216 } else if (PPC::QFRCRegClass.hasSubClassEq(RC)) {
1217 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::QVLFDX), DestReg),
1218 FrameIdx));
1219 NonRI = true;
1220 } else if (PPC::QSRCRegClass.hasSubClassEq(RC)) {
1221 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::QVLFSXs), DestReg),
1222 FrameIdx));
1223 NonRI = true;
1224 } else if (PPC::QBRCRegClass.hasSubClassEq(RC)) {
1225 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::QVLFDXb), DestReg),
1226 FrameIdx));
1227 NonRI = true;
1228 } else if (PPC::SPILLTOVSRRCRegClass.hasSubClassEq(RC)) {
1229 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILLTOVSR_LD),
1230 DestReg), FrameIdx));
1231 } else {
1232 llvm_unreachable("Unknown regclass!")::llvm::llvm_unreachable_internal("Unknown regclass!", "/build/llvm-toolchain-snapshot-7~svn325874/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 1232)
;
1233 }
1234
1235 return false;
1236}
1237
1238void
1239PPCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
1240 MachineBasicBlock::iterator MI,
1241 unsigned DestReg, int FrameIdx,
1242 const TargetRegisterClass *RC,
1243 const TargetRegisterInfo *TRI) const {
1244 MachineFunction &MF = *MBB.getParent();
1245 SmallVector<MachineInstr*, 4> NewMIs;
1246 DebugLoc DL;
1247 if (MI != MBB.end()) DL = MI->getDebugLoc();
1248
1249 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1250 FuncInfo->setHasSpills();
1251
1252 // We need to avoid a situation in which the value from a VRRC register is
1253 // spilled using an Altivec instruction and reloaded into a VSRC register
1254 // using a VSX instruction. The issue with this is that the VSX
1255 // load/store instructions swap the doublewords in the vector and the Altivec
1256 // ones don't. The register classes on the spill/reload may be different if
1257 // the register is defined using an Altivec instruction and is then used by a
1258 // VSX instruction.
1259 if (Subtarget.hasVSX() && RC == &PPC::VRRCRegClass)
1260 RC = &PPC::VSRCRegClass;
1261
1262 bool NonRI = false, SpillsVRS = false;
1263 if (LoadRegFromStackSlot(MF, DL, DestReg, FrameIdx, RC, NewMIs,
1264 NonRI, SpillsVRS))
1265 FuncInfo->setSpillsCR();
1266
1267 if (SpillsVRS)
1268 FuncInfo->setSpillsVRSAVE();
1269
1270 if (NonRI)
1271 FuncInfo->setHasNonRISpills();
1272
1273 for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
1274 MBB.insert(MI, NewMIs[i]);
1275
1276 const MachineFrameInfo &MFI = MF.getFrameInfo();
1277 MachineMemOperand *MMO = MF.getMachineMemOperand(
1278 MachinePointerInfo::getFixedStack(MF, FrameIdx),
1279 MachineMemOperand::MOLoad, MFI.getObjectSize(FrameIdx),
1280 MFI.getObjectAlignment(FrameIdx));
1281 NewMIs.back()->addMemOperand(MF, MMO);
1282}
1283
1284bool PPCInstrInfo::
1285reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
1286 assert(Cond.size() == 2 && "Invalid PPC branch opcode!")(static_cast <bool> (Cond.size() == 2 && "Invalid PPC branch opcode!"
) ? void (0) : __assert_fail ("Cond.size() == 2 && \"Invalid PPC branch opcode!\""
, "/build/llvm-toolchain-snapshot-7~svn325874/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 1286, __extension__ __PRETTY_FUNCTION__))
;
1287 if (Cond[1].getReg() == PPC::CTR8 || Cond[1].getReg() == PPC::CTR)
1288 Cond[0].setImm(Cond[0].getImm() == 0 ? 1 : 0);
1289 else
1290 // Leave the CR# the same, but invert the condition.
1291 Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm()));
1292 return false;
1293}
1294
1295bool PPCInstrInfo::FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
1296 unsigned Reg, MachineRegisterInfo *MRI) const {
1297 // For some instructions, it is legal to fold ZERO into the RA register field.
1298 // A zero immediate should always be loaded with a single li.
1299 unsigned DefOpc = DefMI.getOpcode();
1300 if (DefOpc != PPC::LI && DefOpc != PPC::LI8)
1301 return false;
1302 if (!DefMI.getOperand(1).isImm())
1303 return false;
1304 if (DefMI.getOperand(1).getImm() != 0)
1305 return false;
1306
1307 // Note that we cannot here invert the arguments of an isel in order to fold
1308 // a ZERO into what is presented as the second argument. All we have here
1309 // is the condition bit, and that might come from a CR-logical bit operation.
1310
1311 const MCInstrDesc &UseMCID = UseMI.getDesc();
1312
1313 // Only fold into real machine instructions.
1314 if (UseMCID.isPseudo())
1315 return false;
1316
1317 unsigned UseIdx;
1318 for (UseIdx = 0; UseIdx < UseMI.getNumOperands(); ++UseIdx)
1319 if (UseMI.getOperand(UseIdx).isReg() &&
1320 UseMI.getOperand(UseIdx).getReg() == Reg)
1321 break;
1322
1323 assert(UseIdx < UseMI.getNumOperands() && "Cannot find Reg in UseMI")(static_cast <bool> (UseIdx < UseMI.getNumOperands()
&& "Cannot find Reg in UseMI") ? void (0) : __assert_fail
("UseIdx < UseMI.getNumOperands() && \"Cannot find Reg in UseMI\""
, "/build/llvm-toolchain-snapshot-7~svn325874/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 1323, __extension__ __PRETTY_FUNCTION__))
;
1324 assert(UseIdx < UseMCID.getNumOperands() && "No operand description for Reg")(static_cast <bool> (UseIdx < UseMCID.getNumOperands
() && "No operand description for Reg") ? void (0) : __assert_fail
("UseIdx < UseMCID.getNumOperands() && \"No operand description for Reg\""
, "/build/llvm-toolchain-snapshot-7~svn325874/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 1324, __extension__ __PRETTY_FUNCTION__))
;
1325
1326 const MCOperandInfo *UseInfo = &UseMCID.OpInfo[UseIdx];
1327
1328 // We can fold the zero if this register requires a GPRC_NOR0/G8RC_NOX0
1329 // register (which might also be specified as a pointer class kind).
1330 if (UseInfo->isLookupPtrRegClass()) {
1331 if (UseInfo->RegClass /* Kind */ != 1)
1332 return false;
1333 } else {
1334 if (UseInfo->RegClass != PPC::GPRC_NOR0RegClassID &&
1335 UseInfo->RegClass != PPC::G8RC_NOX0RegClassID)
1336 return false;
1337 }
1338
1339 // Make sure this is not tied to an output register (or otherwise
1340 // constrained). This is true for ST?UX registers, for example, which
1341 // are tied to their output registers.
1342 if (UseInfo->Constraints != 0)
1343 return false;
1344
1345 unsigned ZeroReg;
1346 if (UseInfo->isLookupPtrRegClass()) {
1347 bool isPPC64 = Subtarget.isPPC64();
1348 ZeroReg = isPPC64 ? PPC::ZERO8 : PPC::ZERO;
1349 } else {
1350 ZeroReg = UseInfo->RegClass == PPC::G8RC_NOX0RegClassID ?
1351 PPC::ZERO8 : PPC::ZERO;
1352 }
1353
1354 bool DeleteDef = MRI->hasOneNonDBGUse(Reg);
1355 UseMI.getOperand(UseIdx).setReg(ZeroReg);
1356
1357 if (DeleteDef)
1358 DefMI.eraseFromParent();
1359
1360 return true;
1361}
1362
1363static bool MBBDefinesCTR(MachineBasicBlock &MBB) {
1364 for (MachineBasicBlock::iterator I = MBB.begin(), IE = MBB.end();
1365 I != IE; ++I)
1366 if (I->definesRegister(PPC::CTR) || I->definesRegister(PPC::CTR8))
1367 return true;
1368 return false;
1369}
1370
1371// We should make sure that, if we're going to predicate both sides of a
1372// condition (a diamond), that both sides don't define the counter register. We
1373// can predicate counter-decrement-based branches, but while that predicates
1374// the branching, it does not predicate the counter decrement. If we tried to
1375// merge the triangle into one predicated block, we'd decrement the counter
1376// twice.
1377bool PPCInstrInfo::isProfitableToIfCvt(MachineBasicBlock &TMBB,
1378 unsigned NumT, unsigned ExtraT,
1379 MachineBasicBlock &FMBB,
1380 unsigned NumF, unsigned ExtraF,
1381 BranchProbability Probability) const {
1382 return !(MBBDefinesCTR(TMBB) && MBBDefinesCTR(FMBB));
1383}
1384
1385
1386bool PPCInstrInfo::isPredicated(const MachineInstr &MI) const {
1387 // The predicated branches are identified by their type, not really by the
1388 // explicit presence of a predicate. Furthermore, some of them can be
1389 // predicated more than once. Because if conversion won't try to predicate
1390 // any instruction which already claims to be predicated (by returning true
1391 // here), always return false. In doing so, we let isPredicable() be the
1392 // final word on whether not the instruction can be (further) predicated.
1393
1394 return false;
1395}
1396
1397bool PPCInstrInfo::isUnpredicatedTerminator(const MachineInstr &MI) const {
1398 if (!MI.isTerminator())
1399 return false;
1400
1401 // Conditional branch is a special case.
1402 if (MI.isBranch() && !MI.isBarrier())
1403 return true;
1404
1405 return !isPredicated(MI);
1406}
1407
1408bool PPCInstrInfo::PredicateInstruction(MachineInstr &MI,
1409 ArrayRef<MachineOperand> Pred) const {
1410 unsigned OpC = MI.getOpcode();
1411 if (OpC == PPC::BLR || OpC == PPC::BLR8) {
1412 if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) {
1413 bool isPPC64 = Subtarget.isPPC64();
1414 MI.setDesc(get(Pred[0].getImm() ? (isPPC64 ? PPC::BDNZLR8 : PPC::BDNZLR)
1415 : (isPPC64 ? PPC::BDZLR8 : PPC::BDZLR)));
1416 } else if (Pred[0].getImm() == PPC::PRED_BIT_SET) {
1417 MI.setDesc(get(PPC::BCLR));
1418 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
1419 .addReg(Pred[1].getReg());
1420 } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) {
1421 MI.setDesc(get(PPC::BCLRn));
1422 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
1423 .addReg(Pred[1].getReg());
1424 } else {
1425 MI.setDesc(get(PPC::BCCLR));
1426 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
1427 .addImm(Pred[0].getImm())
1428 .addReg(Pred[1].getReg());
1429 }
1430
1431 return true;
1432 } else if (OpC == PPC::B) {
1433 if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) {
1434 bool isPPC64 = Subtarget.isPPC64();
1435 MI.setDesc(get(Pred[0].getImm() ? (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ)
1436 : (isPPC64 ? PPC::BDZ8 : PPC::BDZ)));
1437 } else if (Pred[0].getImm() == PPC::PRED_BIT_SET) {
1438 MachineBasicBlock *MBB = MI.getOperand(0).getMBB();
1439 MI.RemoveOperand(0);
1440
1441 MI.setDesc(get(PPC::BC));
1442 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
1443 .addReg(Pred[1].getReg())
1444 .addMBB(MBB);
1445 } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) {
1446 MachineBasicBlock *MBB = MI.getOperand(0).getMBB();
1447 MI.RemoveOperand(0);
1448
1449 MI.setDesc(get(PPC::BCn));
1450 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
1451 .addReg(Pred[1].getReg())
1452 .addMBB(MBB);
1453 } else {
1454 MachineBasicBlock *MBB = MI.getOperand(0).getMBB();
1455 MI.RemoveOperand(0);
1456
1457 MI.setDesc(get(PPC::BCC));
1458 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
1459 .addImm(Pred[0].getImm())
1460 .addReg(Pred[1].getReg())
1461 .addMBB(MBB);
1462 }
1463
1464 return true;
1465 } else if (OpC == PPC::BCTR || OpC == PPC::BCTR8 ||
1466 OpC == PPC::BCTRL || OpC == PPC::BCTRL8) {
1467 if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR)
1468 llvm_unreachable("Cannot predicate bctr[l] on the ctr register")::llvm::llvm_unreachable_internal("Cannot predicate bctr[l] on the ctr register"
, "/build/llvm-toolchain-snapshot-7~svn325874/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 1468)
;
1469
1470 bool setLR = OpC == PPC::BCTRL || OpC == PPC::BCTRL8;
1471 bool isPPC64 = Subtarget.isPPC64();
1472
1473 if (Pred[0].getImm() == PPC::PRED_BIT_SET) {
1474 MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8 : PPC::BCCTR8)
1475 : (setLR ? PPC::BCCTRL : PPC::BCCTR)));
1476 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
1477 .addReg(Pred[1].getReg());
1478 return true;
1479 } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) {
1480 MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8n : PPC::BCCTR8n)
1481 : (setLR ? PPC::BCCTRLn : PPC::BCCTRn)));
1482 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
1483 .addReg(Pred[1].getReg());
1484 return true;
1485 }
1486
1487 MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCCTRL8 : PPC::BCCCTR8)
1488 : (setLR ? PPC::BCCCTRL : PPC::BCCCTR)));
1489 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
1490 .addImm(Pred[0].getImm())
1491 .addReg(Pred[1].getReg());
1492 return true;
1493 }
1494
1495 return false;
1496}
1497
1498bool PPCInstrInfo::SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
1499 ArrayRef<MachineOperand> Pred2) const {
1500 assert(Pred1.size() == 2 && "Invalid PPC first predicate")(static_cast <bool> (Pred1.size() == 2 && "Invalid PPC first predicate"
) ? void (0) : __assert_fail ("Pred1.size() == 2 && \"Invalid PPC first predicate\""
, "/build/llvm-toolchain-snapshot-7~svn325874/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 1500, __extension__ __PRETTY_FUNCTION__))
;
1501 assert(Pred2.size() == 2 && "Invalid PPC second predicate")(static_cast <bool> (Pred2.size() == 2 && "Invalid PPC second predicate"
) ? void (0) : __assert_fail ("Pred2.size() == 2 && \"Invalid PPC second predicate\""
, "/build/llvm-toolchain-snapshot-7~svn325874/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 1501, __extension__ __PRETTY_FUNCTION__))
;
1502
1503 if (Pred1[1].getReg() == PPC::CTR8 || Pred1[1].getReg() == PPC::CTR)
1504 return false;
1505 if (Pred2[1].getReg() == PPC::CTR8 || Pred2[1].getReg() == PPC::CTR)
1506 return false;
1507
1508 // P1 can only subsume P2 if they test the same condition register.
1509 if (Pred1[1].getReg() != Pred2[1].getReg())
1510 return false;
1511
1512 PPC::Predicate P1 = (PPC::Predicate) Pred1[0].getImm();
1513 PPC::Predicate P2 = (PPC::Predicate) Pred2[0].getImm();
1514
1515 if (P1 == P2)
1516 return true;
1517
1518 // Does P1 subsume P2, e.g. GE subsumes GT.
1519 if (P1 == PPC::PRED_LE &&
1520 (P2 == PPC::PRED_LT || P2 == PPC::PRED_EQ))
1521 return true;
1522 if (P1 == PPC::PRED_GE &&
1523 (P2 == PPC::PRED_GT || P2 == PPC::PRED_EQ))
1524 return true;
1525
1526 return false;
1527}
1528
1529bool PPCInstrInfo::DefinesPredicate(MachineInstr &MI,
1530 std::vector<MachineOperand> &Pred) const {
1531 // Note: At the present time, the contents of Pred from this function is
1532 // unused by IfConversion. This implementation follows ARM by pushing the
1533 // CR-defining operand. Because the 'DZ' and 'DNZ' count as types of
1534 // predicate, instructions defining CTR or CTR8 are also included as
1535 // predicate-defining instructions.
1536
1537 const TargetRegisterClass *RCs[] =
1538 { &PPC::CRRCRegClass, &PPC::CRBITRCRegClass,
1539 &PPC::CTRRCRegClass, &PPC::CTRRC8RegClass };
1540
1541 bool Found = false;
1542 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
1543 const MachineOperand &MO = MI.getOperand(i);
1544 for (unsigned c = 0; c < array_lengthof(RCs) && !Found; ++c) {
1545 const TargetRegisterClass *RC = RCs[c];
1546 if (MO.isReg()) {
1547 if (MO.isDef() && RC->contains(MO.getReg())) {
1548 Pred.push_back(MO);
1549 Found = true;
1550 }
1551 } else if (MO.isRegMask()) {
1552 for (TargetRegisterClass::iterator I = RC->begin(),
1553 IE = RC->end(); I != IE; ++I)
1554 if (MO.clobbersPhysReg(*I)) {
1555 Pred.push_back(MO);
1556 Found = true;
1557 }
1558 }
1559 }
1560 }
1561
1562 return Found;
1563}
1564
1565bool PPCInstrInfo::isPredicable(const MachineInstr &MI) const {
1566 unsigned OpC = MI.getOpcode();
1567 switch (OpC) {
1568 default:
1569 return false;
1570 case PPC::B:
1571 case PPC::BLR:
1572 case PPC::BLR8:
1573 case PPC::BCTR:
1574 case PPC::BCTR8:
1575 case PPC::BCTRL:
1576 case PPC::BCTRL8:
1577 return true;
1578 }
1579}
1580
1581bool PPCInstrInfo::analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
1582 unsigned &SrcReg2, int &Mask,
1583 int &Value) const {
1584 unsigned Opc = MI.getOpcode();
1585
1586 switch (Opc) {
1587 default: return false;
1588 case PPC::CMPWI:
1589 case PPC::CMPLWI:
1590 case PPC::CMPDI:
1591 case PPC::CMPLDI:
1592 SrcReg = MI.getOperand(1).getReg();
1593 SrcReg2 = 0;
1594 Value = MI.getOperand(2).getImm();
1595 Mask = 0xFFFF;
1596 return true;
1597 case PPC::CMPW:
1598 case PPC::CMPLW:
1599 case PPC::CMPD:
1600 case PPC::CMPLD:
1601 case PPC::FCMPUS:
1602 case PPC::FCMPUD:
1603 SrcReg = MI.getOperand(1).getReg();
1604 SrcReg2 = MI.getOperand(2).getReg();
1605 Value = 0;
1606 Mask = 0;
1607 return true;
1608 }
1609}
1610
1611bool PPCInstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
1612 unsigned SrcReg2, int Mask, int Value,
1613 const MachineRegisterInfo *MRI) const {
1614 if (DisableCmpOpt)
1615 return false;
1616
1617 int OpC = CmpInstr.getOpcode();
1618 unsigned CRReg = CmpInstr.getOperand(0).getReg();
1619
1620 // FP record forms set CR1 based on the execption status bits, not a
1621 // comparison with zero.
1622 if (OpC == PPC::FCMPUS || OpC == PPC::FCMPUD)
1623 return false;
1624
1625 // The record forms set the condition register based on a signed comparison
1626 // with zero (so says the ISA manual). This is not as straightforward as it
1627 // seems, however, because this is always a 64-bit comparison on PPC64, even
1628 // for instructions that are 32-bit in nature (like slw for example).
1629 // So, on PPC32, for unsigned comparisons, we can use the record forms only
1630 // for equality checks (as those don't depend on the sign). On PPC64,
1631 // we are restricted to equality for unsigned 64-bit comparisons and for
1632 // signed 32-bit comparisons the applicability is more restricted.
1633 bool isPPC64 = Subtarget.isPPC64();
1634 bool is32BitSignedCompare = OpC == PPC::CMPWI || OpC == PPC::CMPW;
1635 bool is32BitUnsignedCompare = OpC == PPC::CMPLWI || OpC == PPC::CMPLW;
1636 bool is64BitUnsignedCompare = OpC == PPC::CMPLDI || OpC == PPC::CMPLD;
1637
1638 // Get the unique definition of SrcReg.
1639 MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
1640 if (!MI) return false;
1641
1642 bool equalityOnly = false;
1643 bool noSub = false;
1644 if (isPPC64) {
1645 if (is32BitSignedCompare) {
1646 // We can perform this optimization only if MI is sign-extending.
1647 if (isSignExtended(*MI))
1648 noSub = true;
1649 else
1650 return false;
1651 } else if (is32BitUnsignedCompare) {
1652 // We can perform this optimization, equality only, if MI is
1653 // zero-extending.
1654 if (isZeroExtended(*MI)) {
1655 noSub = true;
1656 equalityOnly = true;
1657 } else
1658 return false;
1659 } else
1660 equalityOnly = is64BitUnsignedCompare;
1661 } else
1662 equalityOnly = is32BitUnsignedCompare;
1663
1664 if (equalityOnly) {
1665 // We need to check the uses of the condition register in order to reject
1666 // non-equality comparisons.
1667 for (MachineRegisterInfo::use_instr_iterator
1668 I = MRI->use_instr_begin(CRReg), IE = MRI->use_instr_end();
1669 I != IE; ++I) {
1670 MachineInstr *UseMI = &*I;
1671 if (UseMI->getOpcode() == PPC::BCC) {
1672 PPC::Predicate Pred = (PPC::Predicate)UseMI->getOperand(0).getImm();
1673 unsigned PredCond = PPC::getPredicateCondition(Pred);
1674 // We ignore hint bits when checking for non-equality comparisons.
1675 if (PredCond != PPC::PRED_EQ && PredCond != PPC::PRED_NE)
1676 return false;
1677 } else if (UseMI->getOpcode() == PPC::ISEL ||
1678 UseMI->getOpcode() == PPC::ISEL8) {
1679 unsigned SubIdx = UseMI->getOperand(3).getSubReg();
1680 if (SubIdx != PPC::sub_eq)
1681 return false;
1682 } else
1683 return false;
1684 }
1685 }
1686
1687 MachineBasicBlock::iterator I = CmpInstr;
1688
1689 // Scan forward to find the first use of the compare.
1690 for (MachineBasicBlock::iterator EL = CmpInstr.getParent()->end(); I != EL;
1691 ++I) {
1692 bool FoundUse = false;
1693 for (MachineRegisterInfo::use_instr_iterator
1694 J = MRI->use_instr_begin(CRReg), JE = MRI->use_instr_end();
1695 J != JE; ++J)
1696 if (&*J == &*I) {
1697 FoundUse = true;
1698 break;
1699 }
1700
1701 if (FoundUse)
1702 break;
1703 }
1704
1705 SmallVector<std::pair<MachineOperand*, PPC::Predicate>, 4> PredsToUpdate;
1706 SmallVector<std::pair<MachineOperand*, unsigned>, 4> SubRegsToUpdate;
1707
1708 // There are two possible candidates which can be changed to set CR[01].
1709 // One is MI, the other is a SUB instruction.
1710 // For CMPrr(r1,r2), we are looking for SUB(r1,r2) or SUB(r2,r1).
1711 MachineInstr *Sub = nullptr;
1712 if (SrcReg2 != 0)
1713 // MI is not a candidate for CMPrr.
1714 MI = nullptr;
1715 // FIXME: Conservatively refuse to convert an instruction which isn't in the
1716 // same BB as the comparison. This is to allow the check below to avoid calls
1717 // (and other explicit clobbers); instead we should really check for these
1718 // more explicitly (in at least a few predecessors).
1719 else if (MI->getParent() != CmpInstr.getParent())
1720 return false;
1721 else if (Value != 0) {
1722 // The record-form instructions set CR bit based on signed comparison
1723 // against 0. We try to convert a compare against 1 or -1 into a compare
1724 // against 0 to exploit record-form instructions. For example, we change
1725 // the condition "greater than -1" into "greater than or equal to 0"
1726 // and "less than 1" into "less than or equal to 0".
1727
1728 // Since we optimize comparison based on a specific branch condition,
1729 // we don't optimize if condition code is used by more than once.
1730 if (equalityOnly || !MRI->hasOneUse(CRReg))
1731 return false;
1732
1733 MachineInstr *UseMI = &*MRI->use_instr_begin(CRReg);
1734 if (UseMI->getOpcode() != PPC::BCC)
1735 return false;
1736
1737 PPC::Predicate Pred = (PPC::Predicate)UseMI->getOperand(0).getImm();
1738 PPC::Predicate NewPred = Pred;
Value stored to 'NewPred' during its initialization is never read
1739 unsigned PredCond = PPC::getPredicateCondition(Pred);
1740 unsigned PredHint = PPC::getPredicateHint(Pred);
1741 int16_t Immed = (int16_t)Value;
1742
1743 // When modyfing the condition in the predicate, we propagate hint bits
1744 // from the original predicate to the new one.
1745 if (Immed == -1 && PredCond == PPC::PRED_GT)
1746 // We convert "greater than -1" into "greater than or equal to 0",
1747 // since we are assuming signed comparison by !equalityOnly
1748 NewPred = PPC::getPredicate(PPC::PRED_GE, PredHint);
1749 else if (Immed == -1 && PredCond == PPC::PRED_LE)
1750 // We convert "less than or equal to -1" into "less than 0".
1751 NewPred = PPC::getPredicate(PPC::PRED_LT, PredHint);
1752 else if (Immed == 1 && PredCond == PPC::PRED_LT)
1753 // We convert "less than 1" into "less than or equal to 0".
1754 NewPred = PPC::getPredicate(PPC::PRED_LE, PredHint);
1755 else if (Immed == 1 && PredCond == PPC::PRED_GE)
1756 // We convert "greater than or equal to 1" into "greater than 0".
1757 NewPred = PPC::getPredicate(PPC::PRED_GT, PredHint);
1758 else
1759 return false;
1760
1761 PredsToUpdate.push_back(std::make_pair(&(UseMI->getOperand(0)),
1762 NewPred));
1763 }
1764
1765 // Search for Sub.
1766 const TargetRegisterInfo *TRI = &getRegisterInfo();
1767 --I;
1768
1769 // Get ready to iterate backward from CmpInstr.
1770 MachineBasicBlock::iterator E = MI, B = CmpInstr.getParent()->begin();
1771
1772 for (; I != E && !noSub; --I) {
1773 const MachineInstr &Instr = *I;
1774 unsigned IOpC = Instr.getOpcode();
1775
1776 if (&*I != &CmpInstr && (Instr.modifiesRegister(PPC::CR0, TRI) ||
1777 Instr.readsRegister(PPC::CR0, TRI)))
1778 // This instruction modifies or uses the record condition register after
1779 // the one we want to change. While we could do this transformation, it
1780 // would likely not be profitable. This transformation removes one
1781 // instruction, and so even forcing RA to generate one move probably
1782 // makes it unprofitable.
1783 return false;
1784
1785 // Check whether CmpInstr can be made redundant by the current instruction.
1786 if ((OpC == PPC::CMPW || OpC == PPC::CMPLW ||
1787 OpC == PPC::CMPD || OpC == PPC::CMPLD) &&
1788 (IOpC == PPC::SUBF || IOpC == PPC::SUBF8) &&
1789 ((Instr.getOperand(1).getReg() == SrcReg &&
1790 Instr.getOperand(2).getReg() == SrcReg2) ||
1791 (Instr.getOperand(1).getReg() == SrcReg2 &&
1792 Instr.getOperand(2).getReg() == SrcReg))) {
1793 Sub = &*I;
1794 break;
1795 }
1796
1797 if (I == B)
1798 // The 'and' is below the comparison instruction.
1799 return false;
1800 }
1801
1802 // Return false if no candidates exist.
1803 if (!MI && !Sub)
1804 return false;
1805
1806 // The single candidate is called MI.
1807 if (!MI) MI = Sub;
1808
1809 int NewOpC = -1;
1810 int MIOpC = MI->getOpcode();
1811 if (MIOpC == PPC::ANDIo || MIOpC == PPC::ANDIo8)
1812 NewOpC = MIOpC;
1813 else {
1814 NewOpC = PPC::getRecordFormOpcode(MIOpC);
1815 if (NewOpC == -1 && PPC::getNonRecordFormOpcode(MIOpC) != -1)
1816 NewOpC = MIOpC;
1817 }
1818
1819 // FIXME: On the non-embedded POWER architectures, only some of the record
1820 // forms are fast, and we should use only the fast ones.
1821
1822 // The defining instruction has a record form (or is already a record
1823 // form). It is possible, however, that we'll need to reverse the condition
1824 // code of the users.
1825 if (NewOpC == -1)
1826 return false;
1827
1828 // If we have SUB(r1, r2) and CMP(r2, r1), the condition code based on CMP
1829 // needs to be updated to be based on SUB. Push the condition code
1830 // operands to OperandsToUpdate. If it is safe to remove CmpInstr, the
1831 // condition code of these operands will be modified.
1832 // Here, Value == 0 means we haven't converted comparison against 1 or -1 to
1833 // comparison against 0, which may modify predicate.
1834 bool ShouldSwap = false;
1835 if (Sub && Value == 0) {
1836 ShouldSwap = SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
1837 Sub->getOperand(2).getReg() == SrcReg;
1838
1839 // The operands to subf are the opposite of sub, so only in the fixed-point
1840 // case, invert the order.
1841 ShouldSwap = !ShouldSwap;
1842 }
1843
1844 if (ShouldSwap)
1845 for (MachineRegisterInfo::use_instr_iterator
1846 I = MRI->use_instr_begin(CRReg), IE = MRI->use_instr_end();
1847 I != IE; ++I) {
1848 MachineInstr *UseMI = &*I;
1849 if (UseMI->getOpcode() == PPC::BCC) {
1850 PPC::Predicate Pred = (PPC::Predicate) UseMI->getOperand(0).getImm();
1851 unsigned PredCond = PPC::getPredicateCondition(Pred);
1852 assert((!equalityOnly ||(static_cast <bool> ((!equalityOnly || PredCond == PPC::
PRED_EQ || PredCond == PPC::PRED_NE) && "Invalid predicate for equality-only optimization"
) ? void (0) : __assert_fail ("(!equalityOnly || PredCond == PPC::PRED_EQ || PredCond == PPC::PRED_NE) && \"Invalid predicate for equality-only optimization\""
, "/build/llvm-toolchain-snapshot-7~svn325874/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 1854, __extension__ __PRETTY_FUNCTION__))
1853 PredCond == PPC::PRED_EQ || PredCond == PPC::PRED_NE) &&(static_cast <bool> ((!equalityOnly || PredCond == PPC::
PRED_EQ || PredCond == PPC::PRED_NE) && "Invalid predicate for equality-only optimization"
) ? void (0) : __assert_fail ("(!equalityOnly || PredCond == PPC::PRED_EQ || PredCond == PPC::PRED_NE) && \"Invalid predicate for equality-only optimization\""
, "/build/llvm-toolchain-snapshot-7~svn325874/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 1854, __extension__ __PRETTY_FUNCTION__))
1854 "Invalid predicate for equality-only optimization")(static_cast <bool> ((!equalityOnly || PredCond == PPC::
PRED_EQ || PredCond == PPC::PRED_NE) && "Invalid predicate for equality-only optimization"
) ? void (0) : __assert_fail ("(!equalityOnly || PredCond == PPC::PRED_EQ || PredCond == PPC::PRED_NE) && \"Invalid predicate for equality-only optimization\""
, "/build/llvm-toolchain-snapshot-7~svn325874/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 1854, __extension__ __PRETTY_FUNCTION__))
;
1855 (void)PredCond; // To suppress warning in release build.
1856 PredsToUpdate.push_back(std::make_pair(&(UseMI->getOperand(0)),
1857 PPC::getSwappedPredicate(Pred)));
1858 } else if (UseMI->getOpcode() == PPC::ISEL ||
1859 UseMI->getOpcode() == PPC::ISEL8) {
1860 unsigned NewSubReg = UseMI->getOperand(3).getSubReg();
1861 assert((!equalityOnly || NewSubReg == PPC::sub_eq) &&(static_cast <bool> ((!equalityOnly || NewSubReg == PPC
::sub_eq) && "Invalid CR bit for equality-only optimization"
) ? void (0) : __assert_fail ("(!equalityOnly || NewSubReg == PPC::sub_eq) && \"Invalid CR bit for equality-only optimization\""
, "/build/llvm-toolchain-snapshot-7~svn325874/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 1862, __extension__ __PRETTY_FUNCTION__))
1862 "Invalid CR bit for equality-only optimization")(static_cast <bool> ((!equalityOnly || NewSubReg == PPC
::sub_eq) && "Invalid CR bit for equality-only optimization"
) ? void (0) : __assert_fail ("(!equalityOnly || NewSubReg == PPC::sub_eq) && \"Invalid CR bit for equality-only optimization\""
, "/build/llvm-toolchain-snapshot-7~svn325874/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 1862, __extension__ __PRETTY_FUNCTION__))
;
1863
1864 if (NewSubReg == PPC::sub_lt)
1865 NewSubReg = PPC::sub_gt;
1866 else if (NewSubReg == PPC::sub_gt)
1867 NewSubReg = PPC::sub_lt;
1868
1869 SubRegsToUpdate.push_back(std::make_pair(&(UseMI->getOperand(3)),
1870 NewSubReg));
1871 } else // We need to abort on a user we don't understand.
1872 return false;
1873 }
1874 assert(!(Value != 0 && ShouldSwap) &&(static_cast <bool> (!(Value != 0 && ShouldSwap
) && "Non-zero immediate support and ShouldSwap" "may conflict in updating predicate"
) ? void (0) : __assert_fail ("!(Value != 0 && ShouldSwap) && \"Non-zero immediate support and ShouldSwap\" \"may conflict in updating predicate\""
, "/build/llvm-toolchain-snapshot-7~svn325874/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 1876, __extension__ __PRETTY_FUNCTION__))
1875 "Non-zero immediate support and ShouldSwap"(static_cast <bool> (!(Value != 0 && ShouldSwap
) && "Non-zero immediate support and ShouldSwap" "may conflict in updating predicate"
) ? void (0) : __assert_fail ("!(Value != 0 && ShouldSwap) && \"Non-zero immediate support and ShouldSwap\" \"may conflict in updating predicate\""
, "/build/llvm-toolchain-snapshot-7~svn325874/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 1876, __extension__ __PRETTY_FUNCTION__))
1876 "may conflict in updating predicate")(static_cast <bool> (!(Value != 0 && ShouldSwap
) && "Non-zero immediate support and ShouldSwap" "may conflict in updating predicate"
) ? void (0) : __assert_fail ("!(Value != 0 && ShouldSwap) && \"Non-zero immediate support and ShouldSwap\" \"may conflict in updating predicate\""
, "/build/llvm-toolchain-snapshot-7~svn325874/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 1876, __extension__ __PRETTY_FUNCTION__))
;
1877
1878 // Create a new virtual register to hold the value of the CR set by the
1879 // record-form instruction. If the instruction was not previously in
1880 // record form, then set the kill flag on the CR.
1881 CmpInstr.eraseFromParent();
1882
1883 MachineBasicBlock::iterator MII = MI;
1884 BuildMI(*MI->getParent(), std::next(MII), MI->getDebugLoc(),
1885 get(TargetOpcode::COPY), CRReg)
1886 .addReg(PPC::CR0, MIOpC != NewOpC ? RegState::Kill : 0);
1887
1888 // Even if CR0 register were dead before, it is alive now since the
1889 // instruction we just built uses it.
1890 MI->clearRegisterDeads(PPC::CR0);
1891
1892 if (MIOpC != NewOpC) {
1893 // We need to be careful here: we're replacing one instruction with
1894 // another, and we need to make sure that we get all of the right
1895 // implicit uses and defs. On the other hand, the caller may be holding
1896 // an iterator to this instruction, and so we can't delete it (this is
1897 // specifically the case if this is the instruction directly after the
1898 // compare).
1899
1900 const MCInstrDesc &NewDesc = get(NewOpC);
1901 MI->setDesc(NewDesc);
1902
1903 if (NewDesc.ImplicitDefs)
1904 for (const MCPhysReg *ImpDefs = NewDesc.getImplicitDefs();
1905 *ImpDefs; ++ImpDefs)
1906 if (!MI->definesRegister(*ImpDefs))
1907 MI->addOperand(*MI->getParent()->getParent(),
1908 MachineOperand::CreateReg(*ImpDefs, true, true));
1909 if (NewDesc.ImplicitUses)
1910 for (const MCPhysReg *ImpUses = NewDesc.getImplicitUses();
1911 *ImpUses; ++ImpUses)
1912 if (!MI->readsRegister(*ImpUses))
1913 MI->addOperand(*MI->getParent()->getParent(),
1914 MachineOperand::CreateReg(*ImpUses, false, true));
1915 }
1916 assert(MI->definesRegister(PPC::CR0) &&(static_cast <bool> (MI->definesRegister(PPC::CR0) &&
"Record-form instruction does not define cr0?") ? void (0) :
__assert_fail ("MI->definesRegister(PPC::CR0) && \"Record-form instruction does not define cr0?\""
, "/build/llvm-toolchain-snapshot-7~svn325874/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 1917, __extension__ __PRETTY_FUNCTION__))
1917 "Record-form instruction does not define cr0?")(static_cast <bool> (MI->definesRegister(PPC::CR0) &&
"Record-form instruction does not define cr0?") ? void (0) :
__assert_fail ("MI->definesRegister(PPC::CR0) && \"Record-form instruction does not define cr0?\""
, "/build/llvm-toolchain-snapshot-7~svn325874/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 1917, __extension__ __PRETTY_FUNCTION__))
;
1918
1919 // Modify the condition code of operands in OperandsToUpdate.
1920 // Since we have SUB(r1, r2) and CMP(r2, r1), the condition code needs to
1921 // be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
1922 for (unsigned i = 0, e = PredsToUpdate.size(); i < e; i++)
1923 PredsToUpdate[i].first->setImm(PredsToUpdate[i].second);
1924
1925 for (unsigned i = 0, e = SubRegsToUpdate.size(); i < e; i++)
1926 SubRegsToUpdate[i].first->setSubReg(SubRegsToUpdate[i].second);
1927
1928 return true;
1929}
1930
1931/// GetInstSize - Return the number of bytes of code the specified
1932/// instruction may be. This returns the maximum number of bytes.
1933///
1934unsigned PPCInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
1935 unsigned Opcode = MI.getOpcode();
1936
1937 if (Opcode == PPC::INLINEASM) {
1938 const MachineFunction *MF = MI.getParent()->getParent();
1939 const char *AsmStr = MI.getOperand(0).getSymbolName();
1940 return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
1941 } else if (Opcode == TargetOpcode::STACKMAP) {
1942 StackMapOpers Opers(&MI);
1943 return Opers.getNumPatchBytes();
1944 } else if (Opcode == TargetOpcode::PATCHPOINT) {
1945 PatchPointOpers Opers(&MI);
1946 return Opers.getNumPatchBytes();
1947 } else {
1948 return get(Opcode).getSize();
1949 }
1950}
1951
1952std::pair<unsigned, unsigned>
1953PPCInstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
1954 const unsigned Mask = PPCII::MO_ACCESS_MASK;
1955 return std::make_pair(TF & Mask, TF & ~Mask);
1956}
1957
1958ArrayRef<std::pair<unsigned, const char *>>
1959PPCInstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
1960 using namespace PPCII;
1961 static const std::pair<unsigned, const char *> TargetFlags[] = {
1962 {MO_LO, "ppc-lo"},
1963 {MO_HA, "ppc-ha"},
1964 {MO_TPREL_LO, "ppc-tprel-lo"},
1965 {MO_TPREL_HA, "ppc-tprel-ha"},
1966 {MO_DTPREL_LO, "ppc-dtprel-lo"},
1967 {MO_TLSLD_LO, "ppc-tlsld-lo"},
1968 {MO_TOC_LO, "ppc-toc-lo"},
1969 {MO_TLS, "ppc-tls"}};
1970 return makeArrayRef(TargetFlags);
1971}
1972
1973ArrayRef<std::pair<unsigned, const char *>>
1974PPCInstrInfo::getSerializableBitmaskMachineOperandTargetFlags() const {
1975 using namespace PPCII;
1976 static const std::pair<unsigned, const char *> TargetFlags[] = {
1977 {MO_PLT, "ppc-plt"},
1978 {MO_PIC_FLAG, "ppc-pic"},
1979 {MO_NLP_FLAG, "ppc-nlp"},
1980 {MO_NLP_HIDDEN_FLAG, "ppc-nlp-hidden"}};
1981 return makeArrayRef(TargetFlags);
1982}
1983
1984// Expand VSX Memory Pseudo instruction to either a VSX or a FP instruction.
1985// The VSX versions have the advantage of a full 64-register target whereas
1986// the FP ones have the advantage of lower latency and higher throughput. So
1987// what we are after is using the faster instructions in low register pressure
1988// situations and using the larger register file in high register pressure
1989// situations.
1990bool PPCInstrInfo::expandVSXMemPseudo(MachineInstr &MI) const {
1991 unsigned UpperOpcode, LowerOpcode;
1992 switch (MI.getOpcode()) {
1993 case PPC::DFLOADf32:
1994 UpperOpcode = PPC::LXSSP;
1995 LowerOpcode = PPC::LFS;
1996 break;
1997 case PPC::DFLOADf64:
1998 UpperOpcode = PPC::LXSD;
1999 LowerOpcode = PPC::LFD;
2000 break;
2001 case PPC::DFSTOREf32:
2002 UpperOpcode = PPC::STXSSP;
2003 LowerOpcode = PPC::STFS;
2004 break;
2005 case PPC::DFSTOREf64:
2006 UpperOpcode = PPC::STXSD;
2007 LowerOpcode = PPC::STFD;
2008 break;
2009 case PPC::XFLOADf32:
2010 UpperOpcode = PPC::LXSSPX;
2011 LowerOpcode = PPC::LFSX;
2012 break;
2013 case PPC::XFLOADf64:
2014 UpperOpcode = PPC::LXSDX;
2015 LowerOpcode = PPC::LFDX;
2016 break;
2017 case PPC::XFSTOREf32:
2018 UpperOpcode = PPC::STXSSPX;
2019 LowerOpcode = PPC::STFSX;
2020 break;
2021 case PPC::XFSTOREf64:
2022 UpperOpcode = PPC::STXSDX;
2023 LowerOpcode = PPC::STFDX;
2024 break;
2025 case PPC::LIWAX:
2026 UpperOpcode = PPC::LXSIWAX;
2027 LowerOpcode = PPC::LFIWAX;
2028 break;
2029 case PPC::LIWZX:
2030 UpperOpcode = PPC::LXSIWZX;
2031 LowerOpcode = PPC::LFIWZX;
2032 break;
2033 case PPC::STIWX:
2034 UpperOpcode = PPC::STXSIWX;
2035 LowerOpcode = PPC::STFIWX;
2036 break;
2037 default:
2038 llvm_unreachable("Unknown Operation!")::llvm::llvm_unreachable_internal("Unknown Operation!", "/build/llvm-toolchain-snapshot-7~svn325874/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 2038)
;
2039 }
2040
2041 unsigned TargetReg = MI.getOperand(0).getReg();
2042 unsigned Opcode;
2043 if ((TargetReg >= PPC::F0 && TargetReg <= PPC::F31) ||
2044 (TargetReg >= PPC::VSL0 && TargetReg <= PPC::VSL31))
2045 Opcode = LowerOpcode;
2046 else
2047 Opcode = UpperOpcode;
2048 MI.setDesc(get(Opcode));
2049 return true;
2050}
2051
2052bool PPCInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
2053 auto &MBB = *MI.getParent();
2054 auto DL = MI.getDebugLoc();
2055
2056 switch (MI.getOpcode()) {
2057 case TargetOpcode::LOAD_STACK_GUARD: {
2058 assert(Subtarget.isTargetLinux() &&(static_cast <bool> (Subtarget.isTargetLinux() &&
"Only Linux target is expected to contain LOAD_STACK_GUARD")
? void (0) : __assert_fail ("Subtarget.isTargetLinux() && \"Only Linux target is expected to contain LOAD_STACK_GUARD\""
, "/build/llvm-toolchain-snapshot-7~svn325874/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 2059, __extension__ __PRETTY_FUNCTION__))
2059 "Only Linux target is expected to contain LOAD_STACK_GUARD")(static_cast <bool> (Subtarget.isTargetLinux() &&
"Only Linux target is expected to contain LOAD_STACK_GUARD")
? void (0) : __assert_fail ("Subtarget.isTargetLinux() && \"Only Linux target is expected to contain LOAD_STACK_GUARD\""
, "/build/llvm-toolchain-snapshot-7~svn325874/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 2059, __extension__ __PRETTY_FUNCTION__))
;
2060 const int64_t Offset = Subtarget.isPPC64() ? -0x7010 : -0x7008;
2061 const unsigned Reg = Subtarget.isPPC64() ? PPC::X13 : PPC::R2;
2062 MI.setDesc(get(Subtarget.isPPC64() ? PPC::LD : PPC::LWZ));
2063 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
2064 .addImm(Offset)
2065 .addReg(Reg);
2066 return true;
2067 }
2068 case PPC::DFLOADf32:
2069 case PPC::DFLOADf64:
2070 case PPC::DFSTOREf32:
2071 case PPC::DFSTOREf64: {
2072 assert(Subtarget.hasP9Vector() &&(static_cast <bool> (Subtarget.hasP9Vector() &&
"Invalid D-Form Pseudo-ops on Pre-P9 target.") ? void (0) : __assert_fail
("Subtarget.hasP9Vector() && \"Invalid D-Form Pseudo-ops on Pre-P9 target.\""
, "/build/llvm-toolchain-snapshot-7~svn325874/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 2073, __extension__ __PRETTY_FUNCTION__))
2073 "Invalid D-Form Pseudo-ops on Pre-P9 target.")(static_cast <bool> (Subtarget.hasP9Vector() &&
"Invalid D-Form Pseudo-ops on Pre-P9 target.") ? void (0) : __assert_fail
("Subtarget.hasP9Vector() && \"Invalid D-Form Pseudo-ops on Pre-P9 target.\""
, "/build/llvm-toolchain-snapshot-7~svn325874/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 2073, __extension__ __PRETTY_FUNCTION__))
;
2074 assert(MI.getOperand(2).isReg() && MI.getOperand(1).isImm() &&(static_cast <bool> (MI.getOperand(2).isReg() &&
MI.getOperand(1).isImm() && "D-form op must have register and immediate operands"
) ? void (0) : __assert_fail ("MI.getOperand(2).isReg() && MI.getOperand(1).isImm() && \"D-form op must have register and immediate operands\""
, "/build/llvm-toolchain-snapshot-7~svn325874/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 2075, __extension__ __PRETTY_FUNCTION__))
2075 "D-form op must have register and immediate operands")(static_cast <bool> (MI.getOperand(2).isReg() &&
MI.getOperand(1).isImm() && "D-form op must have register and immediate operands"
) ? void (0) : __assert_fail ("MI.getOperand(2).isReg() && MI.getOperand(1).isImm() && \"D-form op must have register and immediate operands\""
, "/build/llvm-toolchain-snapshot-7~svn325874/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 2075, __extension__ __PRETTY_FUNCTION__))
;
2076 return expandVSXMemPseudo(MI);
2077 }
2078 case PPC::XFLOADf32:
2079 case PPC::XFSTOREf32:
2080 case PPC::LIWAX:
2081 case PPC::LIWZX:
2082 case PPC::STIWX: {
2083 assert(Subtarget.hasP8Vector() &&(static_cast <bool> (Subtarget.hasP8Vector() &&
"Invalid X-Form Pseudo-ops on Pre-P8 target.") ? void (0) : __assert_fail
("Subtarget.hasP8Vector() && \"Invalid X-Form Pseudo-ops on Pre-P8 target.\""
, "/build/llvm-toolchain-snapshot-7~svn325874/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 2084, __extension__ __PRETTY_FUNCTION__))
2084 "Invalid X-Form Pseudo-ops on Pre-P8 target.")(static_cast <bool> (Subtarget.hasP8Vector() &&
"Invalid X-Form Pseudo-ops on Pre-P8 target.") ? void (0) : __assert_fail
("Subtarget.hasP8Vector() && \"Invalid X-Form Pseudo-ops on Pre-P8 target.\""
, "/build/llvm-toolchain-snapshot-7~svn325874/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 2084, __extension__ __PRETTY_FUNCTION__))
;
2085 assert(MI.getOperand(2).isReg() && MI.getOperand(1).isReg() &&(static_cast <bool> (MI.getOperand(2).isReg() &&
MI.getOperand(1).isReg() && "X-form op must have register and register operands"
) ? void (0) : __assert_fail ("MI.getOperand(2).isReg() && MI.getOperand(1).isReg() && \"X-form op must have register and register operands\""
, "/build/llvm-toolchain-snapshot-7~svn325874/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 2086, __extension__ __PRETTY_FUNCTION__))
2086 "X-form op must have register and register operands")(static_cast <bool> (MI.getOperand(2).isReg() &&
MI.getOperand(1).isReg() && "X-form op must have register and register operands"
) ? void (0) : __assert_fail ("MI.getOperand(2).isReg() && MI.getOperand(1).isReg() && \"X-form op must have register and register operands\""
, "/build/llvm-toolchain-snapshot-7~svn325874/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 2086, __extension__ __PRETTY_FUNCTION__))
;
2087 return expandVSXMemPseudo(MI);
2088 }
2089 case PPC::XFLOADf64:
2090 case PPC::XFSTOREf64: {
2091 assert(Subtarget.hasVSX() &&(static_cast <bool> (Subtarget.hasVSX() && "Invalid X-Form Pseudo-ops on target that has no VSX."
) ? void (0) : __assert_fail ("Subtarget.hasVSX() && \"Invalid X-Form Pseudo-ops on target that has no VSX.\""
, "/build/llvm-toolchain-snapshot-7~svn325874/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 2092, __extension__ __PRETTY_FUNCTION__))
2092 "Invalid X-Form Pseudo-ops on target that has no VSX.")(static_cast <bool> (Subtarget.hasVSX() && "Invalid X-Form Pseudo-ops on target that has no VSX."
) ? void (0) : __assert_fail ("Subtarget.hasVSX() && \"Invalid X-Form Pseudo-ops on target that has no VSX.\""
, "/build/llvm-toolchain-snapshot-7~svn325874/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 2092, __extension__ __PRETTY_FUNCTION__))
;
2093 assert(MI.getOperand(2).isReg() && MI.getOperand(1).isReg() &&(static_cast <bool> (MI.getOperand(2).isReg() &&
MI.getOperand(1).isReg() && "X-form op must have register and register operands"
) ? void (0) : __assert_fail ("MI.getOperand(2).isReg() && MI.getOperand(1).isReg() && \"X-form op must have register and register operands\""
, "/build/llvm-toolchain-snapshot-7~svn325874/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 2094, __extension__ __PRETTY_FUNCTION__))
2094 "X-form op must have register and register operands")(static_cast <bool> (MI.getOperand(2).isReg() &&
MI.getOperand(1).isReg() && "X-form op must have register and register operands"
) ? void (0) : __assert_fail ("MI.getOperand(2).isReg() && MI.getOperand(1).isReg() && \"X-form op must have register and register operands\""
, "/build/llvm-toolchain-snapshot-7~svn325874/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 2094, __extension__ __PRETTY_FUNCTION__))
;
2095 return expandVSXMemPseudo(MI);
2096 }
2097 case PPC::SPILLTOVSR_LD: {
2098 unsigned TargetReg = MI.getOperand(0).getReg();
2099 if (PPC::VSFRCRegClass.contains(TargetReg)) {
2100 MI.setDesc(get(PPC::DFLOADf64));
2101 return expandPostRAPseudo(MI);
2102 }
2103 else
2104 MI.setDesc(get(PPC::LD));
2105 return true;
2106 }
2107 case PPC::SPILLTOVSR_ST: {
2108 unsigned SrcReg = MI.getOperand(0).getReg();
2109 if (PPC::VSFRCRegClass.contains(SrcReg)) {
2110 NumStoreSPILLVSRRCAsVec++;
2111 MI.setDesc(get(PPC::DFSTOREf64));
2112 return expandPostRAPseudo(MI);
2113 } else {
2114 NumStoreSPILLVSRRCAsGpr++;
2115 MI.setDesc(get(PPC::STD));
2116 }
2117 return true;
2118 }
2119 case PPC::SPILLTOVSR_LDX: {
2120 unsigned TargetReg = MI.getOperand(0).getReg();
2121 if (PPC::VSFRCRegClass.contains(TargetReg))
2122 MI.setDesc(get(PPC::LXSDX));
2123 else
2124 MI.setDesc(get(PPC::LDX));
2125 return true;
2126 }
2127 case PPC::SPILLTOVSR_STX: {
2128 unsigned SrcReg = MI.getOperand(0).getReg();
2129 if (PPC::VSFRCRegClass.contains(SrcReg)) {
2130 NumStoreSPILLVSRRCAsVec++;
2131 MI.setDesc(get(PPC::STXSDX));
2132 } else {
2133 NumStoreSPILLVSRRCAsGpr++;
2134 MI.setDesc(get(PPC::STDX));
2135 }
2136 return true;
2137 }
2138
2139 case PPC::CFENCE8: {
2140 auto Val = MI.getOperand(0).getReg();
2141 BuildMI(MBB, MI, DL, get(PPC::CMPD), PPC::CR7).addReg(Val).addReg(Val);
2142 BuildMI(MBB, MI, DL, get(PPC::CTRL_DEP))
2143 .addImm(PPC::PRED_NE_MINUS)
2144 .addReg(PPC::CR7)
2145 .addImm(1);
2146 MI.setDesc(get(PPC::ISYNC));
2147 MI.RemoveOperand(0);
2148 return true;
2149 }
2150 }
2151 return false;
2152}
2153
2154unsigned PPCInstrInfo::lookThruCopyLike(unsigned SrcReg,
2155 const MachineRegisterInfo *MRI) {
2156 while (true) {
2157 MachineInstr *MI = MRI->getVRegDef(SrcReg);
2158 if (!MI->isCopyLike())
2159 return SrcReg;
2160
2161 unsigned CopySrcReg;
2162 if (MI->isCopy())
2163 CopySrcReg = MI->getOperand(1).getReg();
2164 else {
2165 assert(MI->isSubregToReg() && "Bad opcode for lookThruCopyLike")(static_cast <bool> (MI->isSubregToReg() && "Bad opcode for lookThruCopyLike"
) ? void (0) : __assert_fail ("MI->isSubregToReg() && \"Bad opcode for lookThruCopyLike\""
, "/build/llvm-toolchain-snapshot-7~svn325874/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 2165, __extension__ __PRETTY_FUNCTION__))
;
2166 CopySrcReg = MI->getOperand(2).getReg();
2167 }
2168
2169 if (!TargetRegisterInfo::isVirtualRegister(CopySrcReg))
2170 return CopySrcReg;
2171
2172 SrcReg = CopySrcReg;
2173 }
2174}
2175
2176// Essentially a compile-time implementation of a compare->isel sequence.
2177// It takes two constants to compare, along with the true/false registers
2178// and the comparison type (as a subreg to a CR field) and returns one
2179// of the true/false registers, depending on the comparison results.
2180static unsigned selectReg(int64_t Imm1, int64_t Imm2, unsigned CompareOpc,
2181 unsigned TrueReg, unsigned FalseReg,
2182 unsigned CRSubReg) {
2183 // Signed comparisons. The immediates are assumed to be sign-extended.
2184 if (CompareOpc == PPC::CMPWI || CompareOpc == PPC::CMPDI) {
2185 switch (CRSubReg) {
2186 default: llvm_unreachable("Unknown integer comparison type.")::llvm::llvm_unreachable_internal("Unknown integer comparison type."
, "/build/llvm-toolchain-snapshot-7~svn325874/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 2186)
;
2187 case PPC::sub_lt:
2188 return Imm1 < Imm2 ? TrueReg : FalseReg;
2189 case PPC::sub_gt:
2190 return Imm1 > Imm2 ? TrueReg : FalseReg;
2191 case PPC::sub_eq:
2192 return Imm1 == Imm2 ? TrueReg : FalseReg;
2193 }
2194 }
2195 // Unsigned comparisons.
2196 else if (CompareOpc == PPC::CMPLWI || CompareOpc == PPC::CMPLDI) {
2197 switch (CRSubReg) {
2198 default: llvm_unreachable("Unknown integer comparison type.")::llvm::llvm_unreachable_internal("Unknown integer comparison type."
, "/build/llvm-toolchain-snapshot-7~svn325874/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 2198)
;
2199 case PPC::sub_lt:
2200 return (uint64_t)Imm1 < (uint64_t)Imm2 ? TrueReg : FalseReg;
2201 case PPC::sub_gt:
2202 return (uint64_t)Imm1 > (uint64_t)Imm2 ? TrueReg : FalseReg;
2203 case PPC::sub_eq:
2204 return Imm1 == Imm2 ? TrueReg : FalseReg;
2205 }
2206 }
2207 return PPC::NoRegister;
2208}
2209
2210// Replace an instruction with one that materializes a constant (and sets
2211// CR0 if the original instruction was a record-form instruction).
2212void PPCInstrInfo::replaceInstrWithLI(MachineInstr &MI,
2213 const LoadImmediateInfo &LII) const {
2214 // Remove existing operands.
2215 int OperandToKeep = LII.SetCR ? 1 : 0;
2216 for (int i = MI.getNumOperands() - 1; i > OperandToKeep; i--)
2217 MI.RemoveOperand(i);
2218
2219 // Replace the instruction.
2220 if (LII.SetCR) {
2221 MI.setDesc(get(LII.Is64Bit ? PPC::ANDIo8 : PPC::ANDIo));
2222 // Set the immediate.
2223 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
2224 .addImm(LII.Imm).addReg(PPC::CR0, RegState::ImplicitDefine);
2225 return;
2226 }
2227 else
2228 MI.setDesc(get(LII.Is64Bit ? PPC::LI8 : PPC::LI));
2229
2230 // Set the immediate.
2231 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
2232 .addImm(LII.Imm);
2233}
2234
2235MachineInstr *PPCInstrInfo::getConstantDefMI(MachineInstr &MI,
2236 unsigned &ConstOp,
2237 bool &SeenIntermediateUse) const {
2238 ConstOp = ~0U;
2239 MachineInstr *DefMI = nullptr;
2240 MachineRegisterInfo *MRI = &MI.getParent()->getParent()->getRegInfo();
2241 // If we'ere in SSA, get the defs through the MRI. Otherwise, only look
2242 // within the basic block to see if the register is defined using an LI/LI8.
2243 if (MRI->isSSA()) {
2244 for (int i = 1, e = MI.getNumOperands(); i < e; i++) {
2245 if (!MI.getOperand(i).isReg())
2246 continue;
2247 unsigned Reg = MI.getOperand(i).getReg();
2248 if (!TargetRegisterInfo::isVirtualRegister(Reg))
2249 continue;
2250 unsigned TrueReg = lookThruCopyLike(Reg, MRI);
2251 if (TargetRegisterInfo::isVirtualRegister(TrueReg)) {
2252 DefMI = MRI->getVRegDef(TrueReg);
2253 if (DefMI->getOpcode() == PPC::LI || DefMI->getOpcode() == PPC::LI8) {
2254 ConstOp = i;
2255 break;
2256 }
2257 }
2258 }
2259 } else {
2260 // Looking back through the definition for each operand could be expensive,
2261 // so exit early if this isn't an instruction that either has an immediate
2262 // form or is already an immediate form that we can handle.
2263 ImmInstrInfo III;
2264 unsigned Opc = MI.getOpcode();
2265 bool ConvertibleImmForm =
2266 Opc == PPC::CMPWI || Opc == PPC::CMPLWI ||
2267 Opc == PPC::CMPDI || Opc == PPC::CMPLDI ||
2268 Opc == PPC::ADDI || Opc == PPC::ADDI8 ||
2269 Opc == PPC::ORI || Opc == PPC::ORI8 ||
2270 Opc == PPC::XORI || Opc == PPC::XORI8 ||
2271 Opc == PPC::RLDICL || Opc == PPC::RLDICLo ||
2272 Opc == PPC::RLDICL_32 || Opc == PPC::RLDICL_32_64 ||
2273 Opc == PPC::RLWINM || Opc == PPC::RLWINMo ||
2274 Opc == PPC::RLWINM8 || Opc == PPC::RLWINM8o;
2275 if (!instrHasImmForm(MI, III) && !ConvertibleImmForm)
2276 return nullptr;
2277
2278 // Don't convert or %X, %Y, %Y since that's just a register move.
2279 if ((Opc == PPC::OR || Opc == PPC::OR8) &&
2280 MI.getOperand(1).getReg() == MI.getOperand(2).getReg())
2281 return nullptr;
2282 for (int i = 1, e = MI.getNumOperands(); i < e; i++) {
2283 MachineOperand &MO = MI.getOperand(i);
2284 SeenIntermediateUse = false;
2285 if (MO.isReg() && MO.isUse() && !MO.isImplicit()) {
2286 MachineBasicBlock::reverse_iterator E = MI.getParent()->rend(), It = MI;
2287 It++;
2288 unsigned Reg = MI.getOperand(i).getReg();
2289 // MachineInstr::readsRegister only returns true if the machine
2290 // instruction reads the exact register or its super-register. It
2291 // does not consider uses of sub-registers which seems like strange
2292 // behaviour. Nonetheless, if we end up with a 64-bit register here,
2293 // get the corresponding 32-bit register to check.
2294 if (PPC::G8RCRegClass.contains(Reg))
2295 Reg = Reg - PPC::X0 + PPC::R0;
2296
2297 // Is this register defined by a load-immediate in this block?
2298 for ( ; It != E; ++It) {
2299 if (It->modifiesRegister(Reg, &getRegisterInfo())) {
2300 if (It->getOpcode() == PPC::LI || It->getOpcode() == PPC::LI8) {
2301 ConstOp = i;
2302 return &*It;
2303 } else
2304 break;
2305 } else if (It->readsRegister(Reg, &getRegisterInfo()))
2306 // If we see another use of this reg between the def and the MI,
2307 // we want to flat it so the def isn't deleted.
2308 SeenIntermediateUse = true;
2309 }
2310 }
2311 }
2312 }
2313 return ConstOp == ~0U ? nullptr : DefMI;
2314}
2315
2316// If this instruction has an immediate form and one of its operands is a
2317// result of a load-immediate, convert it to the immediate form if the constant
2318// is in range.
2319bool PPCInstrInfo::convertToImmediateForm(MachineInstr &MI,
2320 MachineInstr **KilledDef) const {
2321 MachineFunction *MF = MI.getParent()->getParent();
2322 MachineRegisterInfo *MRI = &MF->getRegInfo();
2323 bool PostRA = !MRI->isSSA();
2324 bool SeenIntermediateUse = true;
2325 unsigned ConstantOperand = ~0U;
2326 MachineInstr *DefMI = getConstantDefMI(MI, ConstantOperand,
2327 SeenIntermediateUse);
2328 if (!DefMI || !DefMI->getOperand(1).isImm())
2329 return false;
2330 assert(ConstantOperand < MI.getNumOperands() &&(static_cast <bool> (ConstantOperand < MI.getNumOperands
() && "The constant operand needs to be valid at this point"
) ? void (0) : __assert_fail ("ConstantOperand < MI.getNumOperands() && \"The constant operand needs to be valid at this point\""
, "/build/llvm-toolchain-snapshot-7~svn325874/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 2331, __extension__ __PRETTY_FUNCTION__))
2331 "The constant operand needs to be valid at this point")(static_cast <bool> (ConstantOperand < MI.getNumOperands
() && "The constant operand needs to be valid at this point"
) ? void (0) : __assert_fail ("ConstantOperand < MI.getNumOperands() && \"The constant operand needs to be valid at this point\""
, "/build/llvm-toolchain-snapshot-7~svn325874/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 2331, __extension__ __PRETTY_FUNCTION__))
;
2332
2333 int64_t Immediate = DefMI->getOperand(1).getImm();
2334 // Sign-extend to 64-bits.
2335 int64_t SExtImm = ((uint64_t)Immediate & ~0x7FFFuLL) != 0 ?
2336 (Immediate | 0xFFFFFFFFFFFF0000) : Immediate;
2337
2338 if (KilledDef && MI.getOperand(ConstantOperand).isKill() &&
2339 !SeenIntermediateUse)
2340 *KilledDef = DefMI;
2341
2342 // If this is a reg+reg instruction that has a reg+imm form, convert it now.
2343 ImmInstrInfo III;
2344 if (instrHasImmForm(MI, III))
2345 return transformToImmForm(MI, III, ConstantOperand, SExtImm);
2346
2347 bool ReplaceWithLI = false;
2348 bool Is64BitLI = false;
2349 int64_t NewImm = 0;
2350 bool SetCR = false;
2351 unsigned Opc = MI.getOpcode();
2352 switch (Opc) {
2353 default: return false;
2354
2355 // FIXME: Any branches conditional on such a comparison can be made
2356 // unconditional. At this time, this happens too infrequently to be worth
2357 // the implementation effort, but if that ever changes, we could convert
2358 // such a pattern here.
2359 case PPC::CMPWI:
2360 case PPC::CMPLWI:
2361 case PPC::CMPDI:
2362 case PPC::CMPLDI: {
2363 // Doing this post-RA would require dataflow analysis to reliably find uses
2364 // of the CR register set by the compare.
2365 if (PostRA)
2366 return false;
2367 // If a compare-immediate is fed by an immediate and is itself an input of
2368 // an ISEL (the most common case) into a COPY of the correct register.
2369 bool Changed = false;
2370 unsigned DefReg = MI.getOperand(0).getReg();
2371 int64_t Comparand = MI.getOperand(2).getImm();
2372 int64_t SExtComparand = ((uint64_t)Comparand & ~0x7FFFuLL) != 0 ?
2373 (Comparand | 0xFFFFFFFFFFFF0000) : Comparand;
2374
2375 for (auto &CompareUseMI : MRI->use_instructions(DefReg)) {
2376 unsigned UseOpc = CompareUseMI.getOpcode();
2377 if (UseOpc != PPC::ISEL && UseOpc != PPC::ISEL8)
2378 continue;
2379 unsigned CRSubReg = CompareUseMI.getOperand(3).getSubReg();
2380 unsigned TrueReg = CompareUseMI.getOperand(1).getReg();
2381 unsigned FalseReg = CompareUseMI.getOperand(2).getReg();
2382 unsigned RegToCopy = selectReg(SExtImm, SExtComparand, Opc, TrueReg,
2383 FalseReg, CRSubReg);
2384 if (RegToCopy == PPC::NoRegister)
2385 continue;
2386 // Can't use PPC::COPY to copy PPC::ZERO[8]. Convert it to LI[8] 0.
2387 if (RegToCopy == PPC::ZERO || RegToCopy == PPC::ZERO8) {
2388 CompareUseMI.setDesc(get(UseOpc == PPC::ISEL8 ? PPC::LI8 : PPC::LI));
2389 CompareUseMI.getOperand(1).ChangeToImmediate(0);
2390 CompareUseMI.RemoveOperand(3);
2391 CompareUseMI.RemoveOperand(2);
2392 continue;
2393 }
2394 DEBUG(dbgs() << "Found LI -> CMPI -> ISEL, replacing with a copy.\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("ppc-instr-info")) { dbgs() << "Found LI -> CMPI -> ISEL, replacing with a copy.\n"
; } } while (false)
;
2395 DEBUG(DefMI->dump(); MI.dump(); CompareUseMI.dump())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("ppc-instr-info")) { DefMI->dump(); MI.dump(); CompareUseMI
.dump(); } } while (false)
;
2396 DEBUG(dbgs() << "Is converted to:\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("ppc-instr-info")) { dbgs() << "Is converted to:\n"; }
} while (false)
;
2397 // Convert to copy and remove unneeded operands.
2398 CompareUseMI.setDesc(get(PPC::COPY));
2399 CompareUseMI.RemoveOperand(3);
2400 CompareUseMI.RemoveOperand(RegToCopy == TrueReg ? 2 : 1);
2401 CmpIselsConverted++;
2402 Changed = true;
2403 DEBUG(CompareUseMI.dump())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("ppc-instr-info")) { CompareUseMI.dump(); } } while (false)
;
2404 }
2405 if (Changed)
2406 return true;
2407 // This may end up incremented multiple times since this function is called
2408 // during a fixed-point transformation, but it is only meant to indicate the
2409 // presence of this opportunity.
2410 MissedConvertibleImmediateInstrs++;
2411 return false;
2412 }
2413
2414 // Immediate forms - may simply be convertable to an LI.
2415 case PPC::ADDI:
2416 case PPC::ADDI8: {
2417 // Does the sum fit in a 16-bit signed field?
2418 int64_t Addend = MI.getOperand(2).getImm();
2419 if (isInt<16>(Addend + SExtImm)) {
2420 ReplaceWithLI = true;
2421 Is64BitLI = Opc == PPC::ADDI8;
2422 NewImm = Addend + SExtImm;
2423 break;
2424 }
2425 return false;
2426 }
2427 case PPC::RLDICL:
2428 case PPC::RLDICLo:
2429 case PPC::RLDICL_32:
2430 case PPC::RLDICL_32_64: {
2431 // Use APInt's rotate function.
2432 int64_t SH = MI.getOperand(2).getImm();
2433 int64_t MB = MI.getOperand(3).getImm();
2434 APInt InVal(Opc == PPC::RLDICL ? 64 : 32, SExtImm, true);
2435 InVal = InVal.rotl(SH);
2436 uint64_t Mask = (1LLU << (63 - MB + 1)) - 1;
2437 InVal &= Mask;
2438 // Can't replace negative values with an LI as that will sign-extend
2439 // and not clear the left bits. If we're setting the CR bit, we will use
2440 // ANDIo which won't sign extend, so that's safe.
2441 if (isUInt<15>(InVal.getSExtValue()) ||
2442 (Opc == PPC::RLDICLo && isUInt<16>(InVal.getSExtValue()))) {
2443 ReplaceWithLI = true;
2444 Is64BitLI = Opc != PPC::RLDICL_32;
2445 NewImm = InVal.getSExtValue();
2446 SetCR = Opc == PPC::RLDICLo;
2447 if (SetCR && (SExtImm & NewImm) != NewImm)
2448 return false;
2449 break;
2450 }
2451 return false;
2452 }
2453 case PPC::RLWINM:
2454 case PPC::RLWINM8:
2455 case PPC::RLWINMo:
2456 case PPC::RLWINM8o: {
2457 int64_t SH = MI.getOperand(2).getImm();
2458 int64_t MB = MI.getOperand(3).getImm();
2459 int64_t ME = MI.getOperand(4).getImm();
2460 APInt InVal(32, SExtImm, true);
2461 InVal = InVal.rotl(SH);
2462 // Set the bits ( MB + 32 ) to ( ME + 32 ).
2463 uint64_t Mask = ((1LLU << (32 - MB)) - 1) & ~((1LLU << (31 - ME)) - 1);
2464 InVal &= Mask;
2465 // Can't replace negative values with an LI as that will sign-extend
2466 // and not clear the left bits. If we're setting the CR bit, we will use
2467 // ANDIo which won't sign extend, so that's safe.
2468 bool ValueFits = isUInt<15>(InVal.getSExtValue());
2469 ValueFits |= ((Opc == PPC::RLWINMo || Opc == PPC::RLWINM8o) &&
2470 isUInt<16>(InVal.getSExtValue()));
2471 if (ValueFits) {
2472 ReplaceWithLI = true;
2473 Is64BitLI = Opc == PPC::RLWINM8 || Opc == PPC::RLWINM8o;
2474 NewImm = InVal.getSExtValue();
2475 SetCR = Opc == PPC::RLWINMo || Opc == PPC::RLWINM8o;
2476 if (SetCR && (SExtImm & NewImm) != NewImm)
2477 return false;
2478 break;
2479 }
2480 return false;
2481 }
2482 case PPC::ORI:
2483 case PPC::ORI8:
2484 case PPC::XORI:
2485 case PPC::XORI8: {
2486 int64_t LogicalImm = MI.getOperand(2).getImm();
2487 int64_t Result = 0;
2488 if (Opc == PPC::ORI || Opc == PPC::ORI8)
2489 Result = LogicalImm | SExtImm;
2490 else
2491 Result = LogicalImm ^ SExtImm;
2492 if (isInt<16>(Result)) {
2493 ReplaceWithLI = true;
2494 Is64BitLI = Opc == PPC::ORI8 || Opc == PPC::XORI8;
2495 NewImm = Result;
2496 break;
2497 }
2498 return false;
2499 }
2500 }
2501
2502 if (ReplaceWithLI) {
2503 DEBUG(dbgs() << "Replacing instruction:\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("ppc-instr-info")) { dbgs() << "Replacing instruction:\n"
; } } while (false)
;
2504 DEBUG(MI.dump())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("ppc-instr-info")) { MI.dump(); } } while (false)
;
2505 DEBUG(dbgs() << "Fed by:\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("ppc-instr-info")) { dbgs() << "Fed by:\n"; } } while (
false)
;
2506 DEBUG(DefMI->dump())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("ppc-instr-info")) { DefMI->dump(); } } while (false)
;
2507 LoadImmediateInfo LII;
2508 LII.Imm = NewImm;
2509 LII.Is64Bit = Is64BitLI;
2510 LII.SetCR = SetCR;
2511 // If we're setting the CR, the original load-immediate must be kept (as an
2512 // operand to ANDIo/ANDI8o).
2513 if (KilledDef && SetCR)
2514 *KilledDef = nullptr;
2515 replaceInstrWithLI(MI, LII);
2516 DEBUG(dbgs() << "With:\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("ppc-instr-info")) { dbgs() << "With:\n"; } } while (false
)
;
2517 DEBUG(MI.dump())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("ppc-instr-info")) { MI.dump(); } } while (false)
;
2518 return true;
2519 }
2520 return false;
2521}
2522
2523bool PPCInstrInfo::instrHasImmForm(const MachineInstr &MI,
2524 ImmInstrInfo &III) const {
2525 unsigned Opc = MI.getOpcode();
2526 // The vast majority of the instructions would need their operand 2 replaced
2527 // with an immediate when switching to the reg+imm form. A marked exception
2528 // are the update form loads/stores for which a constant operand 2 would need
2529 // to turn into a displacement and move operand 1 to the operand 2 position.
2530 III.ImmOpNo = 2;
2531 III.ConstantOpNo = 2;
2532 III.ImmWidth = 16;
2533 III.ImmMustBeMultipleOf = 1;
2534 III.TruncateImmTo = 0;
2535 switch (Opc) {
2536 default: return false;
2537 case PPC::ADD4:
2538 case PPC::ADD8:
2539 III.SignedImm = true;
2540 III.ZeroIsSpecialOrig = 0;
2541 III.ZeroIsSpecialNew = 1;
2542 III.IsCommutative = true;
2543 III.ImmOpcode = Opc == PPC::ADD4 ? PPC::ADDI : PPC::ADDI8;
2544 break;
2545 case PPC::ADDC:
2546 case PPC::ADDC8:
2547 III.SignedImm = true;
2548 III.ZeroIsSpecialOrig = 0;
2549 III.ZeroIsSpecialNew = 0;
2550 III.IsCommutative = true;
2551 III.ImmOpcode = Opc == PPC::ADDC ? PPC::ADDIC : PPC::ADDIC8;
2552 break;
2553 case PPC::ADDCo:
2554 III.SignedImm = true;
2555 III.ZeroIsSpecialOrig = 0;
2556 III.ZeroIsSpecialNew = 0;
2557 III.IsCommutative = true;
2558 III.ImmOpcode = PPC::ADDICo;
2559 break;
2560 case PPC::SUBFC:
2561 case PPC::SUBFC8:
2562 III.SignedImm = true;
2563 III.ZeroIsSpecialOrig = 0;
2564 III.ZeroIsSpecialNew = 0;
2565 III.IsCommutative = false;
2566 III.ImmOpcode = Opc == PPC::SUBFC ? PPC::SUBFIC : PPC::SUBFIC8;
2567 break;
2568 case PPC::CMPW:
2569 case PPC::CMPD:
2570 III.SignedImm = true;
2571 III.ZeroIsSpecialOrig = 0;
2572 III.ZeroIsSpecialNew = 0;
2573 III.IsCommutative = false;
2574 III.ImmOpcode = Opc == PPC::CMPW ? PPC::CMPWI : PPC::CMPDI;
2575 break;
2576 case PPC::CMPLW:
2577 case PPC::CMPLD:
2578 III.SignedImm = false;
2579 III.ZeroIsSpecialOrig = 0;
2580 III.ZeroIsSpecialNew = 0;
2581 III.IsCommutative = false;
2582 III.ImmOpcode = Opc == PPC::CMPLW ? PPC::CMPLWI : PPC::CMPLDI;
2583 break;
2584 case PPC::ANDo:
2585 case PPC::AND8o:
2586 case PPC::OR:
2587 case PPC::OR8:
2588 case PPC::XOR:
2589 case PPC::XOR8:
2590 III.SignedImm = false;
2591 III.ZeroIsSpecialOrig = 0;
2592 III.ZeroIsSpecialNew = 0;
2593 III.IsCommutative = true;
2594 switch(Opc) {
2595 default: llvm_unreachable("Unknown opcode")::llvm::llvm_unreachable_internal("Unknown opcode", "/build/llvm-toolchain-snapshot-7~svn325874/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 2595)
;
2596 case PPC::ANDo: III.ImmOpcode = PPC::ANDIo; break;
2597 case PPC::AND8o: III.ImmOpcode = PPC::ANDIo8; break;
2598 case PPC::OR: III.ImmOpcode = PPC::ORI; break;
2599 case PPC::OR8: III.ImmOpcode = PPC::ORI8; break;
2600 case PPC::XOR: III.ImmOpcode = PPC::XORI; break;
2601 case PPC::XOR8: III.ImmOpcode = PPC::XORI8; break;
2602 }
2603 break;
2604 case PPC::RLWNM:
2605 case PPC::RLWNM8:
2606 case PPC::RLWNMo:
2607 case PPC::RLWNM8o:
2608 case PPC::SLW:
2609 case PPC::SLW8:
2610 case PPC::SLWo:
2611 case PPC::SLW8o:
2612 case PPC::SRW:
2613 case PPC::SRW8:
2614 case PPC::SRWo:
2615 case PPC::SRW8o:
2616 case PPC::SRAW:
2617 case PPC::SRAWo:
2618 III.SignedImm = false;
2619 III.ZeroIsSpecialOrig = 0;
2620 III.ZeroIsSpecialNew = 0;
2621 III.IsCommutative = false;
2622 // This isn't actually true, but the instructions ignore any of the
2623 // upper bits, so any immediate loaded with an LI is acceptable.
2624 // This does not apply to shift right algebraic because a value
2625 // out of range will produce a -1/0.
2626 III.ImmWidth = 16;
2627 if (Opc == PPC::RLWNM || Opc == PPC::RLWNM8 ||
2628 Opc == PPC::RLWNMo || Opc == PPC::RLWNM8o)
2629 III.TruncateImmTo = 5;
2630 else
2631 III.TruncateImmTo = 6;
2632 switch(Opc) {
2633 default: llvm_unreachable("Unknown opcode")::llvm::llvm_unreachable_internal("Unknown opcode", "/build/llvm-toolchain-snapshot-7~svn325874/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 2633)
;
2634 case PPC::RLWNM: III.ImmOpcode = PPC::RLWINM; break;
2635 case PPC::RLWNM8: III.ImmOpcode = PPC::RLWINM8; break;
2636 case PPC::RLWNMo: III.ImmOpcode = PPC::RLWINMo; break;
2637 case PPC::RLWNM8o: III.ImmOpcode = PPC::RLWINM8o; break;
2638 case PPC::SLW: III.ImmOpcode = PPC::RLWINM; break;
2639 case PPC::SLW8: III.ImmOpcode = PPC::RLWINM8; break;
2640 case PPC::SLWo: III.ImmOpcode = PPC::RLWINMo; break;
2641 case PPC::SLW8o: III.ImmOpcode = PPC::RLWINM8o; break;
2642 case PPC::SRW: III.ImmOpcode = PPC::RLWINM; break;
2643 case PPC::SRW8: III.ImmOpcode = PPC::RLWINM8; break;
2644 case PPC::SRWo: III.ImmOpcode = PPC::RLWINMo; break;
2645 case PPC::SRW8o: III.ImmOpcode = PPC::RLWINM8o; break;
2646 case PPC::SRAW:
2647 III.ImmWidth = 5;
2648 III.TruncateImmTo = 0;
2649 III.ImmOpcode = PPC::SRAWI;
2650 break;
2651 case PPC::SRAWo:
2652 III.ImmWidth = 5;
2653 III.TruncateImmTo = 0;
2654 III.ImmOpcode = PPC::SRAWIo;
2655 break;
2656 }
2657 break;
2658 case PPC::RLDCL:
2659 case PPC::RLDCLo:
2660 case PPC::RLDCR:
2661 case PPC::RLDCRo:
2662 case PPC::SLD:
2663 case PPC::SLDo:
2664 case PPC::SRD:
2665 case PPC::SRDo:
2666 case PPC::SRAD:
2667 case PPC::SRADo:
2668 III.SignedImm = false;
2669 III.ZeroIsSpecialOrig = 0;
2670 III.ZeroIsSpecialNew = 0;
2671 III.IsCommutative = false;
2672 // This isn't actually true, but the instructions ignore any of the
2673 // upper bits, so any immediate loaded with an LI is acceptable.
2674 // This does not apply to shift right algebraic because a value
2675 // out of range will produce a -1/0.
2676 III.ImmWidth = 16;
2677 if (Opc == PPC::RLDCL || Opc == PPC::RLDCLo ||
2678 Opc == PPC::RLDCR || Opc == PPC::RLDCRo)
2679 III.TruncateImmTo = 6;
2680 else
2681 III.TruncateImmTo = 7;
2682 switch(Opc) {
2683 default: llvm_unreachable("Unknown opcode")::llvm::llvm_unreachable_internal("Unknown opcode", "/build/llvm-toolchain-snapshot-7~svn325874/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 2683)
;
2684 case PPC::RLDCL: III.ImmOpcode = PPC::RLDICL; break;
2685 case PPC::RLDCLo: III.ImmOpcode = PPC::RLDICLo; break;
2686 case PPC::RLDCR: III.ImmOpcode = PPC::RLDICR; break;
2687 case PPC::RLDCRo: III.ImmOpcode = PPC::RLDICRo; break;
2688 case PPC::SLD: III.ImmOpcode = PPC::RLDICR; break;
2689 case PPC::SLDo: III.ImmOpcode = PPC::RLDICRo; break;
2690 case PPC::SRD: III.ImmOpcode = PPC::RLDICL; break;
2691 case PPC::SRDo: III.ImmOpcode = PPC::RLDICLo; break;
2692 case PPC::SRAD:
2693 III.ImmWidth = 6;
2694 III.TruncateImmTo = 0;
2695 III.ImmOpcode = PPC::SRADI;
2696 break;
2697 case PPC::SRADo:
2698 III.ImmWidth = 6;
2699 III.TruncateImmTo = 0;
2700 III.ImmOpcode = PPC::SRADIo;
2701 break;
2702 }
2703 break;
2704 // Loads and stores:
2705 case PPC::LBZX:
2706 case PPC::LBZX8:
2707 case PPC::LHZX:
2708 case PPC::LHZX8:
2709 case PPC::LHAX:
2710 case PPC::LHAX8:
2711 case PPC::LWZX:
2712 case PPC::LWZX8:
2713 case PPC::LWAX:
2714 case PPC::LDX:
2715 case PPC::LFSX:
2716 case PPC::LFDX:
2717 case PPC::STBX:
2718 case PPC::STBX8:
2719 case PPC::STHX:
2720 case PPC::STHX8:
2721 case PPC::STWX:
2722 case PPC::STWX8:
2723 case PPC::STDX:
2724 case PPC::STFSX:
2725 case PPC::STFDX:
2726 III.SignedImm = true;
2727 III.ZeroIsSpecialOrig = 1;
2728 III.ZeroIsSpecialNew = 2;
2729 III.IsCommutative = true;
2730 III.ImmOpNo = 1;
2731 III.ConstantOpNo = 2;
2732 switch(Opc) {
2733 default: llvm_unreachable("Unknown opcode")::llvm::llvm_unreachable_internal("Unknown opcode", "/build/llvm-toolchain-snapshot-7~svn325874/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 2733)
;
2734 case PPC::LBZX: III.ImmOpcode = PPC::LBZ; break;
2735 case PPC::LBZX8: III.ImmOpcode = PPC::LBZ8; break;
2736 case PPC::LHZX: III.ImmOpcode = PPC::LHZ; break;
2737 case PPC::LHZX8: III.ImmOpcode = PPC::LHZ8; break;
2738 case PPC::LHAX: III.ImmOpcode = PPC::LHA; break;
2739 case PPC::LHAX8: III.ImmOpcode = PPC::LHA8; break;
2740 case PPC::LWZX: III.ImmOpcode = PPC::LWZ; break;
2741 case PPC::LWZX8: III.ImmOpcode = PPC::LWZ8; break;
2742 case PPC::LWAX:
2743 III.ImmOpcode = PPC::LWA;
2744 III.ImmMustBeMultipleOf = 4;
2745 break;
2746 case PPC::LDX: III.ImmOpcode = PPC::LD; III.ImmMustBeMultipleOf = 4; break;
2747 case PPC::LFSX: III.ImmOpcode = PPC::LFS; break;
2748 case PPC::LFDX: III.ImmOpcode = PPC::LFD; break;
2749 case PPC::STBX: III.ImmOpcode = PPC::STB; break;
2750 case PPC::STBX8: III.ImmOpcode = PPC::STB8; break;
2751 case PPC::STHX: III.ImmOpcode = PPC::STH; break;
2752 case PPC::STHX8: III.ImmOpcode = PPC::STH8; break;
2753 case PPC::STWX: III.ImmOpcode = PPC::STW; break;
2754 case PPC::STWX8: III.ImmOpcode = PPC::STW8; break;
2755 case PPC::STDX:
2756 III.ImmOpcode = PPC::STD;
2757 III.ImmMustBeMultipleOf = 4;
2758 break;
2759 case PPC::STFSX: III.ImmOpcode = PPC::STFS; break;
2760 case PPC::STFDX: III.ImmOpcode = PPC::STFD; break;
2761 }
2762 break;
2763 case PPC::LBZUX:
2764 case PPC::LBZUX8:
2765 case PPC::LHZUX:
2766 case PPC::LHZUX8:
2767 case PPC::LHAUX:
2768 case PPC::LHAUX8:
2769 case PPC::LWZUX:
2770 case PPC::LWZUX8:
2771 case PPC::LDUX:
2772 case PPC::LFSUX:
2773 case PPC::LFDUX:
2774 case PPC::STBUX:
2775 case PPC::STBUX8:
2776 case PPC::STHUX:
2777 case PPC::STHUX8:
2778 case PPC::STWUX:
2779 case PPC::STWUX8:
2780 case PPC::STDUX:
2781 case PPC::STFSUX:
2782 case PPC::STFDUX:
2783 III.SignedImm = true;
2784 III.ZeroIsSpecialOrig = 2;
2785 III.ZeroIsSpecialNew = 3;
2786 III.IsCommutative = false;
2787 III.ImmOpNo = 2;
2788 III.ConstantOpNo = 3;
2789 switch(Opc) {
2790 default: llvm_unreachable("Unknown opcode")::llvm::llvm_unreachable_internal("Unknown opcode", "/build/llvm-toolchain-snapshot-7~svn325874/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 2790)
;
2791 case PPC::LBZUX: III.ImmOpcode = PPC::LBZU; break;
2792 case PPC::LBZUX8: III.ImmOpcode = PPC::LBZU8; break;
2793 case PPC::LHZUX: III.ImmOpcode = PPC::LHZU; break;
2794 case PPC::LHZUX8: III.ImmOpcode = PPC::LHZU8; break;
2795 case PPC::LHAUX: III.ImmOpcode = PPC::LHAU; break;
2796 case PPC::LHAUX8: III.ImmOpcode = PPC::LHAU8; break;
2797 case PPC::LWZUX: III.ImmOpcode = PPC::LWZU; break;
2798 case PPC::LWZUX8: III.ImmOpcode = PPC::LWZU8; break;
2799 case PPC::LDUX:
2800 III.ImmOpcode = PPC::LDU;
2801 III.ImmMustBeMultipleOf = 4;
2802 break;
2803 case PPC::LFSUX: III.ImmOpcode = PPC::LFSU; break;
2804 case PPC::LFDUX: III.ImmOpcode = PPC::LFDU; break;
2805 case PPC::STBUX: III.ImmOpcode = PPC::STBU; break;
2806 case PPC::STBUX8: III.ImmOpcode = PPC::STBU8; break;
2807 case PPC::STHUX: III.ImmOpcode = PPC::STHU; break;
2808 case PPC::STHUX8: III.ImmOpcode = PPC::STHU8; break;
2809 case PPC::STWUX: III.ImmOpcode = PPC::STWU; break;
2810 case PPC::STWUX8: III.ImmOpcode = PPC::STWU8; break;
2811 case PPC::STDUX:
2812 III.ImmOpcode = PPC::STDU;
2813 III.ImmMustBeMultipleOf = 4;
2814 break;
2815 case PPC::STFSUX: III.ImmOpcode = PPC::STFSU; break;
2816 case PPC::STFDUX: III.ImmOpcode = PPC::STFDU; break;
2817 }
2818 break;
2819 // Power9 only.
2820 case PPC::LXVX:
2821 case PPC::LXSSPX:
2822 case PPC::LXSDX:
2823 case PPC::STXVX:
2824 case PPC::STXSSPX:
2825 case PPC::STXSDX:
2826 if (!Subtarget.hasP9Vector())
2827 return false;
2828 III.SignedImm = true;
2829 III.ZeroIsSpecialOrig = 1;
2830 III.ZeroIsSpecialNew = 2;
2831 III.IsCommutative = true;
2832 III.ImmOpNo = 1;
2833 III.ConstantOpNo = 2;
2834 switch(Opc) {
2835 default: llvm_unreachable("Unknown opcode")::llvm::llvm_unreachable_internal("Unknown opcode", "/build/llvm-toolchain-snapshot-7~svn325874/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 2835)
;
2836 case PPC::LXVX:
2837 III.ImmOpcode = PPC::LXV;
2838 III.ImmMustBeMultipleOf = 16;
2839 break;
2840 case PPC::LXSSPX:
2841 III.ImmOpcode = PPC::LXSSP;
2842 III.ImmMustBeMultipleOf = 4;
2843 break;
2844 case PPC::LXSDX:
2845 III.ImmOpcode = PPC::LXSD;
2846 III.ImmMustBeMultipleOf = 4;
2847 break;
2848 case PPC::STXVX:
2849 III.ImmOpcode = PPC::STXV;
2850 III.ImmMustBeMultipleOf = 16;
2851 break;
2852 case PPC::STXSSPX:
2853 III.ImmOpcode = PPC::STXSSP;
2854 III.ImmMustBeMultipleOf = 4;
2855 break;
2856 case PPC::STXSDX:
2857 III.ImmOpcode = PPC::STXSD;
2858 III.ImmMustBeMultipleOf = 4;
2859 break;
2860 }
2861 break;
2862 }
2863 return true;
2864}
2865
2866// Utility function for swaping two arbitrary operands of an instruction.
2867static void swapMIOperands(MachineInstr &MI, unsigned Op1, unsigned Op2) {
2868 assert(Op1 != Op2 && "Cannot swap operand with itself.")(static_cast <bool> (Op1 != Op2 && "Cannot swap operand with itself."
) ? void (0) : __assert_fail ("Op1 != Op2 && \"Cannot swap operand with itself.\""
, "/build/llvm-toolchain-snapshot-7~svn325874/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 2868, __extension__ __PRETTY_FUNCTION__))
;
2869
2870 unsigned MaxOp = std::max(Op1, Op2);
2871 unsigned MinOp = std::min(Op1, Op2);
2872 MachineOperand MOp1 = MI.getOperand(MinOp);
2873 MachineOperand MOp2 = MI.getOperand(MaxOp);
2874 MI.RemoveOperand(std::max(Op1, Op2));
2875 MI.RemoveOperand(std::min(Op1, Op2));
2876
2877 // If the operands we are swapping are the two at the end (the common case)
2878 // we can just remove both and add them in the opposite order.
2879 if (MaxOp - MinOp == 1 && MI.getNumOperands() == MinOp) {
2880 MI.addOperand(MOp2);
2881 MI.addOperand(MOp1);
2882 } else {
2883 // Store all operands in a temporary vector, remove them and re-add in the
2884 // right order.
2885 SmallVector<MachineOperand, 2> MOps;
2886 unsigned TotalOps = MI.getNumOperands() + 2; // We've already removed 2 ops.
2887 for (unsigned i = MI.getNumOperands() - 1; i >= MinOp; i--) {
2888 MOps.push_back(MI.getOperand(i));
2889 MI.RemoveOperand(i);
2890 }
2891 // MOp2 needs to be added next.
2892 MI.addOperand(MOp2);
2893 // Now add the rest.
2894 for (unsigned i = MI.getNumOperands(); i < TotalOps; i++) {
2895 if (i == MaxOp)
2896 MI.addOperand(MOp1);
2897 else {
2898 MI.addOperand(MOps.back());
2899 MOps.pop_back();
2900 }
2901 }
2902 }
2903}
2904
2905bool PPCInstrInfo::transformToImmForm(MachineInstr &MI, const ImmInstrInfo &III,
2906 unsigned ConstantOpNo,
2907 int64_t Imm) const {
2908 MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
2909 bool PostRA = !MRI.isSSA();
2910 // Exit early if we can't convert this.
2911 if ((ConstantOpNo != III.ConstantOpNo) && !III.IsCommutative)
2912 return false;
2913 if (Imm % III.ImmMustBeMultipleOf)
2914 return false;
2915 if (III.TruncateImmTo)
2916 Imm &= ((1 << III.TruncateImmTo) - 1);
2917 if (III.SignedImm) {
2918 APInt ActualValue(64, Imm, true);
2919 if (!ActualValue.isSignedIntN(III.ImmWidth))
2920 return false;
2921 } else {
2922 uint64_t UnsignedMax = (1 << III.ImmWidth) - 1;
2923 if ((uint64_t)Imm > UnsignedMax)
2924 return false;
2925 }
2926
2927 // If we're post-RA, the instructions don't agree on whether register zero is
2928 // special, we can transform this as long as the register operand that will
2929 // end up in the location where zero is special isn't R0.
2930 if (PostRA && III.ZeroIsSpecialOrig != III.ZeroIsSpecialNew) {
2931 unsigned PosForOrigZero = III.ZeroIsSpecialOrig ? III.ZeroIsSpecialOrig :
2932 III.ZeroIsSpecialNew + 1;
2933 unsigned OrigZeroReg = MI.getOperand(PosForOrigZero).getReg();
2934 unsigned NewZeroReg = MI.getOperand(III.ZeroIsSpecialNew).getReg();
2935 // If R0 is in the operand where zero is special for the new instruction,
2936 // it is unsafe to transform if the constant operand isn't that operand.
2937 if ((NewZeroReg == PPC::R0 || NewZeroReg == PPC::X0) &&
2938 ConstantOpNo != III.ZeroIsSpecialNew)
2939 return false;
2940 if ((OrigZeroReg == PPC::R0 || OrigZeroReg == PPC::X0) &&
2941 ConstantOpNo != PosForOrigZero)
2942 return false;
2943 }
2944
2945 unsigned Opc = MI.getOpcode();
2946 bool SpecialShift32 =
2947 Opc == PPC::SLW || Opc == PPC::SLWo || Opc == PPC::SRW || Opc == PPC::SRWo;
2948 bool SpecialShift64 =
2949 Opc == PPC::SLD || Opc == PPC::SLDo || Opc == PPC::SRD || Opc == PPC::SRDo;
2950 bool SetCR = Opc == PPC::SLWo || Opc == PPC::SRWo ||
2951 Opc == PPC::SLDo || Opc == PPC::SRDo;
2952 bool RightShift =
2953 Opc == PPC::SRW || Opc == PPC::SRWo || Opc == PPC::SRD || Opc == PPC::SRDo;
2954
2955 MI.setDesc(get(III.ImmOpcode));
2956 if (ConstantOpNo == III.ConstantOpNo) {
2957 // Converting shifts to immediate form is a bit tricky since they may do
2958 // one of three things:
2959 // 1. If the shift amount is between OpSize and 2*OpSize, the result is zero
2960 // 2. If the shift amount is zero, the result is unchanged (save for maybe
2961 // setting CR0)
2962 // 3. If the shift amount is in [1, OpSize), it's just a shift
2963 if (SpecialShift32 || SpecialShift64) {
2964 LoadImmediateInfo LII;
2965 LII.Imm = 0;
2966 LII.SetCR = SetCR;
2967 LII.Is64Bit = SpecialShift64;
2968 uint64_t ShAmt = Imm & (SpecialShift32 ? 0x1F : 0x3F);
2969 if (Imm & (SpecialShift32 ? 0x20 : 0x40))
2970 replaceInstrWithLI(MI, LII);
2971 // Shifts by zero don't change the value. If we don't need to set CR0,
2972 // just convert this to a COPY. Can't do this post-RA since we've already
2973 // cleaned up the copies.
2974 else if (!SetCR && ShAmt == 0 && !PostRA) {
2975 MI.RemoveOperand(2);
2976 MI.setDesc(get(PPC::COPY));
2977 } else {
2978 // The 32 bit and 64 bit instructions are quite different.
2979 if (SpecialShift32) {
2980 // Left shifts use (N, 0, 31-N), right shifts use (32-N, N, 31).
2981 uint64_t SH = RightShift ? 32 - ShAmt : ShAmt;
2982 uint64_t MB = RightShift ? ShAmt : 0;
2983 uint64_t ME = RightShift ? 31 : 31 - ShAmt;
2984 MI.getOperand(III.ConstantOpNo).ChangeToImmediate(SH);
2985 MachineInstrBuilder(*MI.getParent()->getParent(), MI).addImm(MB)
2986 .addImm(ME);
2987 } else {
2988 // Left shifts use (N, 63-N), right shifts use (64-N, N).
2989 uint64_t SH = RightShift ? 64 - ShAmt : ShAmt;
2990 uint64_t ME = RightShift ? ShAmt : 63 - ShAmt;
2991 MI.getOperand(III.ConstantOpNo).ChangeToImmediate(SH);
2992 MachineInstrBuilder(*MI.getParent()->getParent(), MI).addImm(ME);
2993 }
2994 }
2995 } else
2996 MI.getOperand(ConstantOpNo).ChangeToImmediate(Imm);
2997 }
2998 // Convert commutative instructions (switch the operands and convert the
2999 // desired one to an immediate.
3000 else if (III.IsCommutative) {
3001 MI.getOperand(ConstantOpNo).ChangeToImmediate(Imm);
3002 swapMIOperands(MI, ConstantOpNo, III.ConstantOpNo);
3003 } else
3004 llvm_unreachable("Should have exited early!")::llvm::llvm_unreachable_internal("Should have exited early!"
, "/build/llvm-toolchain-snapshot-7~svn325874/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 3004)
;
3005
3006 // For instructions for which the constant register replaces a different
3007 // operand than where the immediate goes, we need to swap them.
3008 if (III.ConstantOpNo != III.ImmOpNo)
3009 swapMIOperands(MI, III.ConstantOpNo, III.ImmOpNo);
3010
3011 // If the R0/X0 register is special for the original instruction and not for
3012 // the new instruction (or vice versa), we need to fix up the register class.
3013 if (!PostRA && III.ZeroIsSpecialOrig != III.ZeroIsSpecialNew) {
3014 if (!III.ZeroIsSpecialOrig) {
3015 unsigned RegToModify = MI.getOperand(III.ZeroIsSpecialNew).getReg();
3016 const TargetRegisterClass *NewRC =
3017 MRI.getRegClass(RegToModify)->hasSuperClassEq(&PPC::GPRCRegClass) ?
3018 &PPC::GPRC_and_GPRC_NOR0RegClass : &PPC::G8RC_and_G8RC_NOX0RegClass;
3019 MRI.setRegClass(RegToModify, NewRC);
3020 }
3021 }
3022 return true;
3023}
3024
3025const TargetRegisterClass *
3026PPCInstrInfo::updatedRC(const TargetRegisterClass *RC) const {
3027 if (Subtarget.hasVSX() && RC == &PPC::VRRCRegClass)
3028 return &PPC::VSRCRegClass;
3029 return RC;
3030}
3031
3032int PPCInstrInfo::getRecordFormOpcode(unsigned Opcode) {
3033 return PPC::getRecordFormOpcode(Opcode);
3034}
3035
3036// This function returns true if the machine instruction
3037// always outputs a value by sign-extending a 32 bit value,
3038// i.e. 0 to 31-th bits are same as 32-th bit.
3039static bool isSignExtendingOp(const MachineInstr &MI) {
3040 int Opcode = MI.getOpcode();
3041 if (Opcode == PPC::LI || Opcode == PPC::LI8 ||
3042 Opcode == PPC::LIS || Opcode == PPC::LIS8 ||
3043 Opcode == PPC::SRAW || Opcode == PPC::SRAWo ||
3044 Opcode == PPC::SRAWI || Opcode == PPC::SRAWIo ||
3045 Opcode == PPC::LWA || Opcode == PPC::LWAX ||
3046 Opcode == PPC::LWA_32 || Opcode == PPC::LWAX_32 ||
3047 Opcode == PPC::LHA || Opcode == PPC::LHAX ||
3048 Opcode == PPC::LHA8 || Opcode == PPC::LHAX8 ||
3049 Opcode == PPC::LBZ || Opcode == PPC::LBZX ||
3050 Opcode == PPC::LBZ8 || Opcode == PPC::LBZX8 ||
3051 Opcode == PPC::LBZU || Opcode == PPC::LBZUX ||
3052 Opcode == PPC::LBZU8 || Opcode == PPC::LBZUX8 ||
3053 Opcode == PPC::LHZ || Opcode == PPC::LHZX ||
3054 Opcode == PPC::LHZ8 || Opcode == PPC::LHZX8 ||
3055 Opcode == PPC::LHZU || Opcode == PPC::LHZUX ||
3056 Opcode == PPC::LHZU8 || Opcode == PPC::LHZUX8 ||
3057 Opcode == PPC::EXTSB || Opcode == PPC::EXTSBo ||
3058 Opcode == PPC::EXTSH || Opcode == PPC::EXTSHo ||
3059 Opcode == PPC::EXTSB8 || Opcode == PPC::EXTSH8 ||
3060 Opcode == PPC::EXTSW || Opcode == PPC::EXTSWo ||
3061 Opcode == PPC::EXTSH8_32_64 || Opcode == PPC::EXTSW_32_64 ||
3062 Opcode == PPC::EXTSB8_32_64)
3063 return true;
3064
3065 if (Opcode == PPC::RLDICL && MI.getOperand(3).getImm() >= 33)
3066 return true;
3067
3068 if ((Opcode == PPC::RLWINM || Opcode == PPC::RLWINMo ||
3069 Opcode == PPC::RLWNM || Opcode == PPC::RLWNMo) &&
3070 MI.getOperand(3).getImm() > 0 &&
3071 MI.getOperand(3).getImm() <= MI.getOperand(4).getImm())
3072 return true;
3073
3074 return false;
3075}
3076
3077// This function returns true if the machine instruction
3078// always outputs zeros in higher 32 bits.
3079static bool isZeroExtendingOp(const MachineInstr &MI) {
3080 int Opcode = MI.getOpcode();
3081 // The 16-bit immediate is sign-extended in li/lis.
3082 // If the most significant bit is zero, all higher bits are zero.
3083 if (Opcode == PPC::LI || Opcode == PPC::LI8 ||
3084 Opcode == PPC::LIS || Opcode == PPC::LIS8) {
3085 int64_t Imm = MI.getOperand(1).getImm();
3086 if (((uint64_t)Imm & ~0x7FFFuLL) == 0)
3087 return true;
3088 }
3089
3090 // We have some variations of rotate-and-mask instructions
3091 // that clear higher 32-bits.
3092 if ((Opcode == PPC::RLDICL || Opcode == PPC::RLDICLo ||
3093 Opcode == PPC::RLDCL || Opcode == PPC::RLDCLo ||
3094 Opcode == PPC::RLDICL_32_64) &&
3095 MI.getOperand(3).getImm() >= 32)
3096 return true;
3097
3098 if ((Opcode == PPC::RLDIC || Opcode == PPC::RLDICo) &&
3099 MI.getOperand(3).getImm() >= 32 &&
3100 MI.getOperand(3).getImm() <= 63 - MI.getOperand(2).getImm())
3101 return true;
3102
3103 if ((Opcode == PPC::RLWINM || Opcode == PPC::RLWINMo ||
3104 Opcode == PPC::RLWNM || Opcode == PPC::RLWNMo ||
3105 Opcode == PPC::RLWINM8 || Opcode == PPC::RLWNM8) &&
3106 MI.getOperand(3).getImm() <= MI.getOperand(4).getImm())
3107 return true;
3108
3109 // There are other instructions that clear higher 32-bits.
3110 if (Opcode == PPC::CNTLZW || Opcode == PPC::CNTLZWo ||
3111 Opcode == PPC::CNTTZW || Opcode == PPC::CNTTZWo ||
3112 Opcode == PPC::CNTLZW8 || Opcode == PPC::CNTTZW8 ||
3113 Opcode == PPC::CNTLZD || Opcode == PPC::CNTLZDo ||
3114 Opcode == PPC::CNTTZD || Opcode == PPC::CNTTZDo ||
3115 Opcode == PPC::POPCNTD || Opcode == PPC::POPCNTW ||
3116 Opcode == PPC::SLW || Opcode == PPC::SLWo ||
3117 Opcode == PPC::SRW || Opcode == PPC::SRWo ||
3118 Opcode == PPC::SLW8 || Opcode == PPC::SRW8 ||
3119 Opcode == PPC::SLWI || Opcode == PPC::SLWIo ||
3120 Opcode == PPC::SRWI || Opcode == PPC::SRWIo ||
3121 Opcode == PPC::LWZ || Opcode == PPC::LWZX ||
3122 Opcode == PPC::LWZU || Opcode == PPC::LWZUX ||
3123 Opcode == PPC::LWBRX || Opcode == PPC::LHBRX ||
3124 Opcode == PPC::LHZ || Opcode == PPC::LHZX ||
3125 Opcode == PPC::LHZU || Opcode == PPC::LHZUX ||
3126 Opcode == PPC::LBZ || Opcode == PPC::LBZX ||
3127 Opcode == PPC::LBZU || Opcode == PPC::LBZUX ||
3128 Opcode == PPC::LWZ8 || Opcode == PPC::LWZX8 ||
3129 Opcode == PPC::LWZU8 || Opcode == PPC::LWZUX8 ||
3130 Opcode == PPC::LWBRX8 || Opcode == PPC::LHBRX8 ||
3131 Opcode == PPC::LHZ8 || Opcode == PPC::LHZX8 ||
3132 Opcode == PPC::LHZU8 || Opcode == PPC::LHZUX8 ||
3133 Opcode == PPC::LBZ8 || Opcode == PPC::LBZX8 ||
3134 Opcode == PPC::LBZU8 || Opcode == PPC::LBZUX8 ||
3135 Opcode == PPC::ANDIo || Opcode == PPC::ANDISo ||
3136 Opcode == PPC::ROTRWI || Opcode == PPC::ROTRWIo ||
3137 Opcode == PPC::EXTLWI || Opcode == PPC::EXTLWIo ||
3138 Opcode == PPC::MFVSRWZ)
3139 return true;
3140
3141 return false;
3142}
3143
3144// This function returns true if the input MachineInstr is a TOC save
3145// instruction.
3146bool PPCInstrInfo::isTOCSaveMI(const MachineInstr &MI) const {
3147 if (!MI.getOperand(1).isImm() || !MI.getOperand(2).isReg())
3148 return false;
3149 unsigned TOCSaveOffset = Subtarget.getFrameLowering()->getTOCSaveOffset();
3150 unsigned StackOffset = MI.getOperand(1).getImm();
3151 unsigned StackReg = MI.getOperand(2).getReg();
3152 if (StackReg == PPC::X1 && StackOffset == TOCSaveOffset)
3153 return true;
3154
3155 return false;
3156}
3157
3158// We limit the max depth to track incoming values of PHIs or binary ops
3159// (e.g. AND) to avoid exsessive cost.
3160const unsigned MAX_DEPTH = 1;
3161
3162bool
3163PPCInstrInfo::isSignOrZeroExtended(const MachineInstr &MI, bool SignExt,
3164 const unsigned Depth) const {
3165 const MachineFunction *MF = MI.getParent()->getParent();
3166 const MachineRegisterInfo *MRI = &MF->getRegInfo();
3167
3168 // If we know this instruction returns sign- or zero-extended result,
3169 // return true.
3170 if (SignExt ? isSignExtendingOp(MI):
3171 isZeroExtendingOp(MI))
3172 return true;
3173
3174 switch (MI.getOpcode()) {
3175 case PPC::COPY: {
3176 unsigned SrcReg = MI.getOperand(1).getReg();
3177
3178 // In both ELFv1 and v2 ABI, method parameters and the return value
3179 // are sign- or zero-extended.
3180 if (MF->getSubtarget<PPCSubtarget>().isSVR4ABI()) {
3181 const PPCFunctionInfo *FuncInfo = MF->getInfo<PPCFunctionInfo>();
3182 // We check the ZExt/SExt flags for a method parameter.
3183 if (MI.getParent()->getBasicBlock() ==
3184 &MF->getFunction().getEntryBlock()) {
3185 unsigned VReg = MI.getOperand(0).getReg();
3186 if (MF->getRegInfo().isLiveIn(VReg))
3187 return SignExt ? FuncInfo->isLiveInSExt(VReg) :
3188 FuncInfo->isLiveInZExt(VReg);
3189 }
3190
3191 // For a method return value, we check the ZExt/SExt flags in attribute.
3192 // We assume the following code sequence for method call.
3193 // ADJCALLSTACKDOWN 32, implicit dead %r1, implicit %r1
3194 // BL8_NOP @func,...
3195 // ADJCALLSTACKUP 32, 0, implicit dead %r1, implicit %r1
3196 // %5 = COPY %x3; G8RC:%5
3197 if (SrcReg == PPC::X3) {
3198 const MachineBasicBlock *MBB = MI.getParent();
3199 MachineBasicBlock::const_instr_iterator II =
3200 MachineBasicBlock::const_instr_iterator(&MI);
3201 if (II != MBB->instr_begin() &&
3202 (--II)->getOpcode() == PPC::ADJCALLSTACKUP) {
3203 const MachineInstr &CallMI = *(--II);
3204 if (CallMI.isCall() && CallMI.getOperand(0).isGlobal()) {
3205 const Function *CalleeFn =
3206 dyn_cast<Function>(CallMI.getOperand(0).getGlobal());
3207 if (!CalleeFn)
3208 return false;
3209 const IntegerType *IntTy =
3210 dyn_cast<IntegerType>(CalleeFn->getReturnType());
3211 const AttributeSet &Attrs =
3212 CalleeFn->getAttributes().getRetAttributes();
3213 if (IntTy && IntTy->getBitWidth() <= 32)
3214 return Attrs.hasAttribute(SignExt ? Attribute::SExt :
3215 Attribute::ZExt);
3216 }
3217 }
3218 }
3219 }
3220
3221 // If this is a copy from another register, we recursively check source.
3222 if (!TargetRegisterInfo::isVirtualRegister(SrcReg))
3223 return false;
3224 const MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
3225 if (SrcMI != NULL__null)
3226 return isSignOrZeroExtended(*SrcMI, SignExt, Depth);
3227
3228 return false;
3229 }
3230
3231 case PPC::ANDIo:
3232 case PPC::ANDISo:
3233 case PPC::ORI:
3234 case PPC::ORIS:
3235 case PPC::XORI:
3236 case PPC::XORIS:
3237 case PPC::ANDIo8:
3238 case PPC::ANDISo8:
3239 case PPC::ORI8:
3240 case PPC::ORIS8:
3241 case PPC::XORI8:
3242 case PPC::XORIS8: {
3243 // logical operation with 16-bit immediate does not change the upper bits.
3244 // So, we track the operand register as we do for register copy.
3245 unsigned SrcReg = MI.getOperand(1).getReg();
3246 if (!TargetRegisterInfo::isVirtualRegister(SrcReg))
3247 return false;
3248 const MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
3249 if (SrcMI != NULL__null)
3250 return isSignOrZeroExtended(*SrcMI, SignExt, Depth);
3251
3252 return false;
3253 }
3254
3255 // If all incoming values are sign-/zero-extended,
3256 // the output of OR, ISEL or PHI is also sign-/zero-extended.
3257 case PPC::OR:
3258 case PPC::OR8:
3259 case PPC::ISEL:
3260 case PPC::PHI: {
3261 if (Depth >= MAX_DEPTH)
3262 return false;
3263
3264 // The input registers for PHI are operand 1, 3, ...
3265 // The input registers for others are operand 1 and 2.
3266 unsigned E = 3, D = 1;
3267 if (MI.getOpcode() == PPC::PHI) {
3268 E = MI.getNumOperands();
3269 D = 2;
3270 }
3271
3272 for (unsigned I = 1; I != E; I += D) {
3273 if (MI.getOperand(I).isReg()) {
3274 unsigned SrcReg = MI.getOperand(I).getReg();
3275 if (!TargetRegisterInfo::isVirtualRegister(SrcReg))
3276 return false;
3277 const MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
3278 if (SrcMI == NULL__null || !isSignOrZeroExtended(*SrcMI, SignExt, Depth+1))
3279 return false;
3280 }
3281 else
3282 return false;
3283 }
3284 return true;
3285 }
3286
3287 // If at least one of the incoming values of an AND is zero extended
3288 // then the output is also zero-extended. If both of the incoming values
3289 // are sign-extended then the output is also sign extended.
3290 case PPC::AND:
3291 case PPC::AND8: {
3292 if (Depth >= MAX_DEPTH)
3293 return false;
3294
3295 assert(MI.getOperand(1).isReg() && MI.getOperand(2).isReg())(static_cast <bool> (MI.getOperand(1).isReg() &&
MI.getOperand(2).isReg()) ? void (0) : __assert_fail ("MI.getOperand(1).isReg() && MI.getOperand(2).isReg()"
, "/build/llvm-toolchain-snapshot-7~svn325874/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 3295, __extension__ __PRETTY_FUNCTION__))
;
3296
3297 unsigned SrcReg1 = MI.getOperand(1).getReg();
3298 unsigned SrcReg2 = MI.getOperand(2).getReg();
3299
3300 if (!TargetRegisterInfo::isVirtualRegister(SrcReg1) ||
3301 !TargetRegisterInfo::isVirtualRegister(SrcReg2))
3302 return false;
3303
3304 const MachineInstr *MISrc1 = MRI->getVRegDef(SrcReg1);
3305 const MachineInstr *MISrc2 = MRI->getVRegDef(SrcReg2);
3306 if (!MISrc1 || !MISrc2)
3307 return false;
3308
3309 if(SignExt)
3310 return isSignOrZeroExtended(*MISrc1, SignExt, Depth+1) &&
3311 isSignOrZeroExtended(*MISrc2, SignExt, Depth+1);
3312 else
3313 return isSignOrZeroExtended(*MISrc1, SignExt, Depth+1) ||
3314 isSignOrZeroExtended(*MISrc2, SignExt, Depth+1);
3315 }
3316
3317 default:
3318 break;
3319 }
3320 return false;
3321}