Bug Summary

File:lib/CodeGen/PeepholeOptimizer.cpp
Warning:line 543, column 30
Called C++ object pointer is null

Annotated Source Code

Press '?' to see keyboard shortcuts

clang -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name PeepholeOptimizer.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-eagerly-assume -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -mrelocation-model pic -pic-level 2 -mthread-model posix -fmath-errno -masm-verbose -mconstructor-aliases -munwind-tables -fuse-init-array -target-cpu x86-64 -dwarf-column-info -debugger-tuning=gdb -momit-leaf-frame-pointer -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-7/lib/clang/7.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-7~svn329677/build-llvm/lib/CodeGen -I /build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen -I /build/llvm-toolchain-snapshot-7~svn329677/build-llvm/include -I /build/llvm-toolchain-snapshot-7~svn329677/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/7.3.0/../../../../include/c++/7.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/7.3.0/../../../../include/x86_64-linux-gnu/c++/7.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/7.3.0/../../../../include/x86_64-linux-gnu/c++/7.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/7.3.0/../../../../include/c++/7.3.0/backward -internal-isystem /usr/include/clang/7.0.0/include/ -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-7/lib/clang/7.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++11 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-7~svn329677/build-llvm/lib/CodeGen -ferror-limit 19 -fmessage-length 0 -fvisibility-inlines-hidden -fobjc-runtime=gcc -fdiagnostics-show-option -vectorize-loops -vectorize-slp -analyzer-checker optin.performance.Padding -analyzer-output=html -analyzer-config stable-report-filename=true -o /tmp/scan-build-2018-04-11-031539-24776-1 -x c++ /build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/PeepholeOptimizer.cpp
1//===- PeepholeOptimizer.cpp - Peephole Optimizations ---------------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Perform peephole optimizations on the machine code:
11//
12// - Optimize Extensions
13//
14// Optimization of sign / zero extension instructions. It may be extended to
15// handle other instructions with similar properties.
16//
17// On some targets, some instructions, e.g. X86 sign / zero extension, may
18// leave the source value in the lower part of the result. This optimization
19// will replace some uses of the pre-extension value with uses of the
20// sub-register of the results.
21//
22// - Optimize Comparisons
23//
24// Optimization of comparison instructions. For instance, in this code:
25//
26// sub r1, 1
27// cmp r1, 0
28// bz L1
29//
30// If the "sub" instruction all ready sets (or could be modified to set) the
31// same flag that the "cmp" instruction sets and that "bz" uses, then we can
32// eliminate the "cmp" instruction.
33//
34// Another instance, in this code:
35//
36// sub r1, r3 | sub r1, imm
37// cmp r3, r1 or cmp r1, r3 | cmp r1, imm
38// bge L1
39//
40// If the branch instruction can use flag from "sub", then we can replace
41// "sub" with "subs" and eliminate the "cmp" instruction.
42//
43// - Optimize Loads:
44//
45// Loads that can be folded into a later instruction. A load is foldable
46// if it loads to virtual registers and the virtual register defined has
47// a single use.
48//
49// - Optimize Copies and Bitcast (more generally, target specific copies):
50//
51// Rewrite copies and bitcasts to avoid cross register bank copies
52// when possible.
53// E.g., Consider the following example, where capital and lower
54// letters denote different register file:
55// b = copy A <-- cross-bank copy
56// C = copy b <-- cross-bank copy
57// =>
58// b = copy A <-- cross-bank copy
59// C = copy A <-- same-bank copy
60//
61// E.g., for bitcast:
62// b = bitcast A <-- cross-bank copy
63// C = bitcast b <-- cross-bank copy
64// =>
65// b = bitcast A <-- cross-bank copy
66// C = copy A <-- same-bank copy
67//===----------------------------------------------------------------------===//
68
69#include "llvm/ADT/DenseMap.h"
70#include "llvm/ADT/Optional.h"
71#include "llvm/ADT/SmallPtrSet.h"
72#include "llvm/ADT/SmallSet.h"
73#include "llvm/ADT/SmallVector.h"
74#include "llvm/ADT/Statistic.h"
75#include "llvm/CodeGen/MachineBasicBlock.h"
76#include "llvm/CodeGen/MachineDominators.h"
77#include "llvm/CodeGen/MachineFunction.h"
78#include "llvm/CodeGen/MachineFunctionPass.h"
79#include "llvm/CodeGen/MachineInstr.h"
80#include "llvm/CodeGen/MachineInstrBuilder.h"
81#include "llvm/CodeGen/MachineLoopInfo.h"
82#include "llvm/CodeGen/MachineOperand.h"
83#include "llvm/CodeGen/MachineRegisterInfo.h"
84#include "llvm/CodeGen/TargetInstrInfo.h"
85#include "llvm/CodeGen/TargetOpcodes.h"
86#include "llvm/CodeGen/TargetRegisterInfo.h"
87#include "llvm/CodeGen/TargetSubtargetInfo.h"
88#include "llvm/MC/LaneBitmask.h"
89#include "llvm/MC/MCInstrDesc.h"
90#include "llvm/Pass.h"
91#include "llvm/Support/CommandLine.h"
92#include "llvm/Support/Debug.h"
93#include "llvm/Support/ErrorHandling.h"
94#include "llvm/Support/raw_ostream.h"
95#include <cassert>
96#include <cstdint>
97#include <memory>
98#include <utility>
99
100using namespace llvm;
101using RegSubRegPair = TargetInstrInfo::RegSubRegPair;
102using RegSubRegPairAndIdx = TargetInstrInfo::RegSubRegPairAndIdx;
103
104#define DEBUG_TYPE"peephole-opt" "peephole-opt"
105
106// Optimize Extensions
107static cl::opt<bool>
108Aggressive("aggressive-ext-opt", cl::Hidden,
109 cl::desc("Aggressive extension optimization"));
110
111static cl::opt<bool>
112DisablePeephole("disable-peephole", cl::Hidden, cl::init(false),
113 cl::desc("Disable the peephole optimizer"));
114
115/// Specifiy whether or not the value tracking looks through
116/// complex instructions. When this is true, the value tracker
117/// bails on everything that is not a copy or a bitcast.
118static cl::opt<bool>
119DisableAdvCopyOpt("disable-adv-copy-opt", cl::Hidden, cl::init(false),
120 cl::desc("Disable advanced copy optimization"));
121
122static cl::opt<bool> DisableNAPhysCopyOpt(
123 "disable-non-allocatable-phys-copy-opt", cl::Hidden, cl::init(false),
124 cl::desc("Disable non-allocatable physical register copy optimization"));
125
126// Limit the number of PHI instructions to process
127// in PeepholeOptimizer::getNextSource.
128static cl::opt<unsigned> RewritePHILimit(
129 "rewrite-phi-limit", cl::Hidden, cl::init(10),
130 cl::desc("Limit the length of PHI chains to lookup"));
131
132// Limit the length of recurrence chain when evaluating the benefit of
133// commuting operands.
134static cl::opt<unsigned> MaxRecurrenceChain(
135 "recurrence-chain-limit", cl::Hidden, cl::init(3),
136 cl::desc("Maximum length of recurrence chain when evaluating the benefit "
137 "of commuting operands"));
138
139
140STATISTIC(NumReuse, "Number of extension results reused")static llvm::Statistic NumReuse = {"peephole-opt", "NumReuse"
, "Number of extension results reused", {0}, {false}}
;
141STATISTIC(NumCmps, "Number of compares eliminated")static llvm::Statistic NumCmps = {"peephole-opt", "NumCmps", "Number of compares eliminated"
, {0}, {false}}
;
142STATISTIC(NumImmFold, "Number of move immediate folded")static llvm::Statistic NumImmFold = {"peephole-opt", "NumImmFold"
, "Number of move immediate folded", {0}, {false}}
;
143STATISTIC(NumLoadFold, "Number of loads folded")static llvm::Statistic NumLoadFold = {"peephole-opt", "NumLoadFold"
, "Number of loads folded", {0}, {false}}
;
144STATISTIC(NumSelects, "Number of selects optimized")static llvm::Statistic NumSelects = {"peephole-opt", "NumSelects"
, "Number of selects optimized", {0}, {false}}
;
145STATISTIC(NumUncoalescableCopies, "Number of uncoalescable copies optimized")static llvm::Statistic NumUncoalescableCopies = {"peephole-opt"
, "NumUncoalescableCopies", "Number of uncoalescable copies optimized"
, {0}, {false}}
;
146STATISTIC(NumRewrittenCopies, "Number of copies rewritten")static llvm::Statistic NumRewrittenCopies = {"peephole-opt", "NumRewrittenCopies"
, "Number of copies rewritten", {0}, {false}}
;
147STATISTIC(NumNAPhysCopies, "Number of non-allocatable physical copies removed")static llvm::Statistic NumNAPhysCopies = {"peephole-opt", "NumNAPhysCopies"
, "Number of non-allocatable physical copies removed", {0}, {
false}}
;
148
149namespace {
150
151 class ValueTrackerResult;
152 class RecurrenceInstr;
153
154 class PeepholeOptimizer : public MachineFunctionPass {
155 const TargetInstrInfo *TII;
156 const TargetRegisterInfo *TRI;
157 MachineRegisterInfo *MRI;
158 MachineDominatorTree *DT; // Machine dominator tree
159 MachineLoopInfo *MLI;
160
161 public:
162 static char ID; // Pass identification
163
164 PeepholeOptimizer() : MachineFunctionPass(ID) {
165 initializePeepholeOptimizerPass(*PassRegistry::getPassRegistry());
166 }
167
168 bool runOnMachineFunction(MachineFunction &MF) override;
169
170 void getAnalysisUsage(AnalysisUsage &AU) const override {
171 AU.setPreservesCFG();
172 MachineFunctionPass::getAnalysisUsage(AU);
173 AU.addRequired<MachineLoopInfo>();
174 AU.addPreserved<MachineLoopInfo>();
175 if (Aggressive) {
176 AU.addRequired<MachineDominatorTree>();
177 AU.addPreserved<MachineDominatorTree>();
178 }
179 }
180
181 /// Track Def -> Use info used for rewriting copies.
182 using RewriteMapTy = SmallDenseMap<RegSubRegPair, ValueTrackerResult>;
183
184 /// Sequence of instructions that formulate recurrence cycle.
185 using RecurrenceCycle = SmallVector<RecurrenceInstr, 4>;
186
187 private:
188 bool optimizeCmpInstr(MachineInstr &MI);
189 bool optimizeExtInstr(MachineInstr &MI, MachineBasicBlock &MBB,
190 SmallPtrSetImpl<MachineInstr*> &LocalMIs);
191 bool optimizeSelect(MachineInstr &MI,
192 SmallPtrSetImpl<MachineInstr *> &LocalMIs);
193 bool optimizeCondBranch(MachineInstr &MI);
194 bool optimizeCoalescableCopy(MachineInstr &MI);
195 bool optimizeUncoalescableCopy(MachineInstr &MI,
196 SmallPtrSetImpl<MachineInstr *> &LocalMIs);
197 bool optimizeRecurrence(MachineInstr &PHI);
198 bool findNextSource(RegSubRegPair RegSubReg, RewriteMapTy &RewriteMap);
199 bool isMoveImmediate(MachineInstr &MI,
200 SmallSet<unsigned, 4> &ImmDefRegs,
201 DenseMap<unsigned, MachineInstr*> &ImmDefMIs);
202 bool foldImmediate(MachineInstr &MI, SmallSet<unsigned, 4> &ImmDefRegs,
203 DenseMap<unsigned, MachineInstr*> &ImmDefMIs);
204
205 /// \brief Finds recurrence cycles, but only ones that formulated around
206 /// a def operand and a use operand that are tied. If there is a use
207 /// operand commutable with the tied use operand, find recurrence cycle
208 /// along that operand as well.
209 bool findTargetRecurrence(unsigned Reg,
210 const SmallSet<unsigned, 2> &TargetReg,
211 RecurrenceCycle &RC);
212
213 /// \brief If copy instruction \p MI is a virtual register copy, track it in
214 /// the set \p CopySrcRegs and \p CopyMIs. If this virtual register was
215 /// previously seen as a copy, replace the uses of this copy with the
216 /// previously seen copy's destination register.
217 bool foldRedundantCopy(MachineInstr &MI,
218 SmallSet<unsigned, 4> &CopySrcRegs,
219 DenseMap<unsigned, MachineInstr *> &CopyMIs);
220
221 /// Is the register \p Reg a non-allocatable physical register?
222 bool isNAPhysCopy(unsigned Reg);
223
224 /// \brief If copy instruction \p MI is a non-allocatable virtual<->physical
225 /// register copy, track it in the \p NAPhysToVirtMIs map. If this
226 /// non-allocatable physical register was previously copied to a virtual
227 /// registered and hasn't been clobbered, the virt->phys copy can be
228 /// deleted.
229 bool foldRedundantNAPhysCopy(MachineInstr &MI,
230 DenseMap<unsigned, MachineInstr *> &NAPhysToVirtMIs);
231
232 bool isLoadFoldable(MachineInstr &MI,
233 SmallSet<unsigned, 16> &FoldAsLoadDefCandidates);
234
235 /// \brief Check whether \p MI is understood by the register coalescer
236 /// but may require some rewriting.
237 bool isCoalescableCopy(const MachineInstr &MI) {
238 // SubregToRegs are not interesting, because they are already register
239 // coalescer friendly.
240 return MI.isCopy() || (!DisableAdvCopyOpt &&
241 (MI.isRegSequence() || MI.isInsertSubreg() ||
242 MI.isExtractSubreg()));
243 }
244
245 /// \brief Check whether \p MI is a copy like instruction that is
246 /// not recognized by the register coalescer.
247 bool isUncoalescableCopy(const MachineInstr &MI) {
248 return MI.isBitcast() ||
249 (!DisableAdvCopyOpt &&
250 (MI.isRegSequenceLike() || MI.isInsertSubregLike() ||
251 MI.isExtractSubregLike()));
252 }
253
254 MachineInstr &rewriteSource(MachineInstr &CopyLike,
255 RegSubRegPair Def, RewriteMapTy &RewriteMap);
256 };
257
258 /// Helper class to hold instructions that are inside recurrence cycles.
259 /// The recurrence cycle is formulated around 1) a def operand and its
260 /// tied use operand, or 2) a def operand and a use operand that is commutable
261 /// with another use operand which is tied to the def operand. In the latter
262 /// case, index of the tied use operand and the commutable use operand are
263 /// maintained with CommutePair.
264 class RecurrenceInstr {
265 public:
266 using IndexPair = std::pair<unsigned, unsigned>;
267
268 RecurrenceInstr(MachineInstr *MI) : MI(MI) {}
269 RecurrenceInstr(MachineInstr *MI, unsigned Idx1, unsigned Idx2)
270 : MI(MI), CommutePair(std::make_pair(Idx1, Idx2)) {}
271
272 MachineInstr *getMI() const { return MI; }
273 Optional<IndexPair> getCommutePair() const { return CommutePair; }
274
275 private:
276 MachineInstr *MI;
277 Optional<IndexPair> CommutePair;
278 };
279
280 /// Helper class to hold a reply for ValueTracker queries.
281 /// Contains the returned sources for a given search and the instructions
282 /// where the sources were tracked from.
283 class ValueTrackerResult {
284 private:
285 /// Track all sources found by one ValueTracker query.
286 SmallVector<RegSubRegPair, 2> RegSrcs;
287
288 /// Instruction using the sources in 'RegSrcs'.
289 const MachineInstr *Inst = nullptr;
290
291 public:
292 ValueTrackerResult() = default;
293
294 ValueTrackerResult(unsigned Reg, unsigned SubReg) {
295 addSource(Reg, SubReg);
296 }
297
298 bool isValid() const { return getNumSources() > 0; }
299
300 void setInst(const MachineInstr *I) { Inst = I; }
301 const MachineInstr *getInst() const { return Inst; }
302
303 void clear() {
304 RegSrcs.clear();
305 Inst = nullptr;
306 }
307
308 void addSource(unsigned SrcReg, unsigned SrcSubReg) {
309 RegSrcs.push_back(RegSubRegPair(SrcReg, SrcSubReg));
310 }
311
312 void setSource(int Idx, unsigned SrcReg, unsigned SrcSubReg) {
313 assert(Idx < getNumSources() && "Reg pair source out of index")(static_cast <bool> (Idx < getNumSources() &&
"Reg pair source out of index") ? void (0) : __assert_fail (
"Idx < getNumSources() && \"Reg pair source out of index\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/PeepholeOptimizer.cpp"
, 313, __extension__ __PRETTY_FUNCTION__))
;
314 RegSrcs[Idx] = RegSubRegPair(SrcReg, SrcSubReg);
315 }
316
317 int getNumSources() const { return RegSrcs.size(); }
318
319 RegSubRegPair getSrc(int Idx) const {
320 return RegSrcs[Idx];
321 }
322
323 unsigned getSrcReg(int Idx) const {
324 assert(Idx < getNumSources() && "Reg source out of index")(static_cast <bool> (Idx < getNumSources() &&
"Reg source out of index") ? void (0) : __assert_fail ("Idx < getNumSources() && \"Reg source out of index\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/PeepholeOptimizer.cpp"
, 324, __extension__ __PRETTY_FUNCTION__))
;
325 return RegSrcs[Idx].Reg;
326 }
327
328 unsigned getSrcSubReg(int Idx) const {
329 assert(Idx < getNumSources() && "SubReg source out of index")(static_cast <bool> (Idx < getNumSources() &&
"SubReg source out of index") ? void (0) : __assert_fail ("Idx < getNumSources() && \"SubReg source out of index\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/PeepholeOptimizer.cpp"
, 329, __extension__ __PRETTY_FUNCTION__))
;
330 return RegSrcs[Idx].SubReg;
331 }
332
333 bool operator==(const ValueTrackerResult &Other) {
334 if (Other.getInst() != getInst())
335 return false;
336
337 if (Other.getNumSources() != getNumSources())
338 return false;
339
340 for (int i = 0, e = Other.getNumSources(); i != e; ++i)
341 if (Other.getSrcReg(i) != getSrcReg(i) ||
342 Other.getSrcSubReg(i) != getSrcSubReg(i))
343 return false;
344 return true;
345 }
346 };
347
348 /// \brief Helper class to track the possible sources of a value defined by
349 /// a (chain of) copy related instructions.
350 /// Given a definition (instruction and definition index), this class
351 /// follows the use-def chain to find successive suitable sources.
352 /// The given source can be used to rewrite the definition into
353 /// def = COPY src.
354 ///
355 /// For instance, let us consider the following snippet:
356 /// v0 =
357 /// v2 = INSERT_SUBREG v1, v0, sub0
358 /// def = COPY v2.sub0
359 ///
360 /// Using a ValueTracker for def = COPY v2.sub0 will give the following
361 /// suitable sources:
362 /// v2.sub0 and v0.
363 /// Then, def can be rewritten into def = COPY v0.
364 class ValueTracker {
365 private:
366 /// The current point into the use-def chain.
367 const MachineInstr *Def = nullptr;
368
369 /// The index of the definition in Def.
370 unsigned DefIdx = 0;
371
372 /// The sub register index of the definition.
373 unsigned DefSubReg;
374
375 /// The register where the value can be found.
376 unsigned Reg;
377
378 /// MachineRegisterInfo used to perform tracking.
379 const MachineRegisterInfo &MRI;
380
381 /// Optional TargetInstrInfo used to perform some complex tracking.
382 const TargetInstrInfo *TII;
383
384 /// Dispatcher to the right underlying implementation of getNextSource.
385 ValueTrackerResult getNextSourceImpl();
386
387 /// Specialized version of getNextSource for Copy instructions.
388 ValueTrackerResult getNextSourceFromCopy();
389
390 /// Specialized version of getNextSource for Bitcast instructions.
391 ValueTrackerResult getNextSourceFromBitcast();
392
393 /// Specialized version of getNextSource for RegSequence instructions.
394 ValueTrackerResult getNextSourceFromRegSequence();
395
396 /// Specialized version of getNextSource for InsertSubreg instructions.
397 ValueTrackerResult getNextSourceFromInsertSubreg();
398
399 /// Specialized version of getNextSource for ExtractSubreg instructions.
400 ValueTrackerResult getNextSourceFromExtractSubreg();
401
402 /// Specialized version of getNextSource for SubregToReg instructions.
403 ValueTrackerResult getNextSourceFromSubregToReg();
404
405 /// Specialized version of getNextSource for PHI instructions.
406 ValueTrackerResult getNextSourceFromPHI();
407
408 public:
409 /// Create a ValueTracker instance for the value defined by \p Reg.
410 /// \p DefSubReg represents the sub register index the value tracker will
411 /// track. It does not need to match the sub register index used in the
412 /// definition of \p Reg.
413 /// If \p Reg is a physical register, a value tracker constructed with
414 /// this constructor will not find any alternative source.
415 /// Indeed, when \p Reg is a physical register that constructor does not
416 /// know which definition of \p Reg it should track.
417 /// Use the next constructor to track a physical register.
418 ValueTracker(unsigned Reg, unsigned DefSubReg,
419 const MachineRegisterInfo &MRI,
420 const TargetInstrInfo *TII = nullptr)
421 : DefSubReg(DefSubReg), Reg(Reg), MRI(MRI), TII(TII) {
422 if (!TargetRegisterInfo::isPhysicalRegister(Reg)) {
423 Def = MRI.getVRegDef(Reg);
424 DefIdx = MRI.def_begin(Reg).getOperandNo();
425 }
426 }
427
428 /// \brief Following the use-def chain, get the next available source
429 /// for the tracked value.
430 /// \return A ValueTrackerResult containing a set of registers
431 /// and sub registers with tracked values. A ValueTrackerResult with
432 /// an empty set of registers means no source was found.
433 ValueTrackerResult getNextSource();
434 };
435
436} // end anonymous namespace
437
438char PeepholeOptimizer::ID = 0;
439
440char &llvm::PeepholeOptimizerID = PeepholeOptimizer::ID;
441
442INITIALIZE_PASS_BEGIN(PeepholeOptimizer, DEBUG_TYPE,static void *initializePeepholeOptimizerPassOnce(PassRegistry
&Registry) {
443 "Peephole Optimizations", false, false)static void *initializePeepholeOptimizerPassOnce(PassRegistry
&Registry) {
444INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)initializeMachineDominatorTreePass(Registry);
445INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo)initializeMachineLoopInfoPass(Registry);
446INITIALIZE_PASS_END(PeepholeOptimizer, DEBUG_TYPE,PassInfo *PI = new PassInfo( "Peephole Optimizations", "peephole-opt"
, &PeepholeOptimizer::ID, PassInfo::NormalCtor_t(callDefaultCtor
<PeepholeOptimizer>), false, false); Registry.registerPass
(*PI, true); return PI; } static llvm::once_flag InitializePeepholeOptimizerPassFlag
; void llvm::initializePeepholeOptimizerPass(PassRegistry &
Registry) { llvm::call_once(InitializePeepholeOptimizerPassFlag
, initializePeepholeOptimizerPassOnce, std::ref(Registry)); }
447 "Peephole Optimizations", false, false)PassInfo *PI = new PassInfo( "Peephole Optimizations", "peephole-opt"
, &PeepholeOptimizer::ID, PassInfo::NormalCtor_t(callDefaultCtor
<PeepholeOptimizer>), false, false); Registry.registerPass
(*PI, true); return PI; } static llvm::once_flag InitializePeepholeOptimizerPassFlag
; void llvm::initializePeepholeOptimizerPass(PassRegistry &
Registry) { llvm::call_once(InitializePeepholeOptimizerPassFlag
, initializePeepholeOptimizerPassOnce, std::ref(Registry)); }
448
449/// If instruction is a copy-like instruction, i.e. it reads a single register
450/// and writes a single register and it does not modify the source, and if the
451/// source value is preserved as a sub-register of the result, then replace all
452/// reachable uses of the source with the subreg of the result.
453///
454/// Do not generate an EXTRACT that is used only in a debug use, as this changes
455/// the code. Since this code does not currently share EXTRACTs, just ignore all
456/// debug uses.
457bool PeepholeOptimizer::
458optimizeExtInstr(MachineInstr &MI, MachineBasicBlock &MBB,
459 SmallPtrSetImpl<MachineInstr*> &LocalMIs) {
460 unsigned SrcReg, DstReg, SubIdx;
461 if (!TII->isCoalescableExtInstr(MI, SrcReg, DstReg, SubIdx))
20
Assuming the condition is false
21
Taking false branch
462 return false;
463
464 if (TargetRegisterInfo::isPhysicalRegister(DstReg) ||
22
Taking false branch
465 TargetRegisterInfo::isPhysicalRegister(SrcReg))
466 return false;
467
468 if (MRI->hasOneNonDBGUse(SrcReg))
23
Assuming the condition is false
24
Taking false branch
469 // No other uses.
470 return false;
471
472 // Ensure DstReg can get a register class that actually supports
473 // sub-registers. Don't change the class until we commit.
474 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg);
475 DstRC = TRI->getSubClassWithSubReg(DstRC, SubIdx);
476 if (!DstRC)
25
Assuming 'DstRC' is non-null
26
Taking false branch
477 return false;
478
479 // The ext instr may be operating on a sub-register of SrcReg as well.
480 // PPC::EXTSW is a 32 -> 64-bit sign extension, but it reads a 64-bit
481 // register.
482 // If UseSrcSubIdx is Set, SubIdx also applies to SrcReg, and only uses of
483 // SrcReg:SubIdx should be replaced.
484 bool UseSrcSubIdx =
485 TRI->getSubClassWithSubReg(MRI->getRegClass(SrcReg), SubIdx) != nullptr;
27
Assuming the condition is false
486
487 // The source has other uses. See if we can replace the other uses with use of
488 // the result of the extension.
489 SmallPtrSet<MachineBasicBlock*, 4> ReachedBBs;
490 for (MachineInstr &UI : MRI->use_nodbg_instructions(DstReg))
491 ReachedBBs.insert(UI.getParent());
492
493 // Uses that are in the same BB of uses of the result of the instruction.
494 SmallVector<MachineOperand*, 8> Uses;
495
496 // Uses that the result of the instruction can reach.
497 SmallVector<MachineOperand*, 8> ExtendedUses;
498
499 bool ExtendLife = true;
500 for (MachineOperand &UseMO : MRI->use_nodbg_operands(SrcReg)) {
501 MachineInstr *UseMI = UseMO.getParent();
502 if (UseMI == &MI)
28
Assuming the condition is false
29
Taking false branch
503 continue;
504
505 if (UseMI->isPHI()) {
30
Taking false branch
506 ExtendLife = false;
507 continue;
508 }
509
510 // Only accept uses of SrcReg:SubIdx.
511 if (UseSrcSubIdx && UseMO.getSubReg() != SubIdx)
512 continue;
513
514 // It's an error to translate this:
515 //
516 // %reg1025 = <sext> %reg1024
517 // ...
518 // %reg1026 = SUBREG_TO_REG 0, %reg1024, 4
519 //
520 // into this:
521 //
522 // %reg1025 = <sext> %reg1024
523 // ...
524 // %reg1027 = COPY %reg1025:4
525 // %reg1026 = SUBREG_TO_REG 0, %reg1027, 4
526 //
527 // The problem here is that SUBREG_TO_REG is there to assert that an
528 // implicit zext occurs. It doesn't insert a zext instruction. If we allow
529 // the COPY here, it will give us the value after the <sext>, not the
530 // original value of %reg1024 before <sext>.
531 if (UseMI->getOpcode() == TargetOpcode::SUBREG_TO_REG)
31
Assuming the condition is false
32
Taking false branch
532 continue;
533
534 MachineBasicBlock *UseMBB = UseMI->getParent();
535 if (UseMBB == &MBB) {
33
Assuming the condition is false
34
Taking false branch
536 // Local uses that come after the extension.
537 if (!LocalMIs.count(UseMI))
538 Uses.push_back(&UseMO);
539 } else if (ReachedBBs.count(UseMBB)) {
35
Assuming the condition is false
36
Taking false branch
540 // Non-local uses where the result of the extension is used. Always
541 // replace these unless it's a PHI.
542 Uses.push_back(&UseMO);
543 } else if (Aggressive && DT->dominates(&MBB, UseMBB)) {
37
Assuming the condition is true
38
Called C++ object pointer is null
544 // We may want to extend the live range of the extension result in order
545 // to replace these uses.
546 ExtendedUses.push_back(&UseMO);
547 } else {
548 // Both will be live out of the def MBB anyway. Don't extend live range of
549 // the extension result.
550 ExtendLife = false;
551 break;
552 }
553 }
554
555 if (ExtendLife && !ExtendedUses.empty())
556 // Extend the liveness of the extension result.
557 Uses.append(ExtendedUses.begin(), ExtendedUses.end());
558
559 // Now replace all uses.
560 bool Changed = false;
561 if (!Uses.empty()) {
562 SmallPtrSet<MachineBasicBlock*, 4> PHIBBs;
563
564 // Look for PHI uses of the extended result, we don't want to extend the
565 // liveness of a PHI input. It breaks all kinds of assumptions down
566 // stream. A PHI use is expected to be the kill of its source values.
567 for (MachineInstr &UI : MRI->use_nodbg_instructions(DstReg))
568 if (UI.isPHI())
569 PHIBBs.insert(UI.getParent());
570
571 const TargetRegisterClass *RC = MRI->getRegClass(SrcReg);
572 for (unsigned i = 0, e = Uses.size(); i != e; ++i) {
573 MachineOperand *UseMO = Uses[i];
574 MachineInstr *UseMI = UseMO->getParent();
575 MachineBasicBlock *UseMBB = UseMI->getParent();
576 if (PHIBBs.count(UseMBB))
577 continue;
578
579 // About to add uses of DstReg, clear DstReg's kill flags.
580 if (!Changed) {
581 MRI->clearKillFlags(DstReg);
582 MRI->constrainRegClass(DstReg, DstRC);
583 }
584
585 unsigned NewVR = MRI->createVirtualRegister(RC);
586 MachineInstr *Copy = BuildMI(*UseMBB, UseMI, UseMI->getDebugLoc(),
587 TII->get(TargetOpcode::COPY), NewVR)
588 .addReg(DstReg, 0, SubIdx);
589 // SubIdx applies to both SrcReg and DstReg when UseSrcSubIdx is set.
590 if (UseSrcSubIdx) {
591 Copy->getOperand(0).setSubReg(SubIdx);
592 Copy->getOperand(0).setIsUndef();
593 }
594 UseMO->setReg(NewVR);
595 ++NumReuse;
596 Changed = true;
597 }
598 }
599
600 return Changed;
601}
602
603/// If the instruction is a compare and the previous instruction it's comparing
604/// against already sets (or could be modified to set) the same flag as the
605/// compare, then we can remove the comparison and use the flag from the
606/// previous instruction.
607bool PeepholeOptimizer::optimizeCmpInstr(MachineInstr &MI) {
608 // If this instruction is a comparison against zero and isn't comparing a
609 // physical register, we can try to optimize it.
610 unsigned SrcReg, SrcReg2;
611 int CmpMask, CmpValue;
612 if (!TII->analyzeCompare(MI, SrcReg, SrcReg2, CmpMask, CmpValue) ||
613 TargetRegisterInfo::isPhysicalRegister(SrcReg) ||
614 (SrcReg2 != 0 && TargetRegisterInfo::isPhysicalRegister(SrcReg2)))
615 return false;
616
617 // Attempt to optimize the comparison instruction.
618 if (TII->optimizeCompareInstr(MI, SrcReg, SrcReg2, CmpMask, CmpValue, MRI)) {
619 ++NumCmps;
620 return true;
621 }
622
623 return false;
624}
625
626/// Optimize a select instruction.
627bool PeepholeOptimizer::optimizeSelect(MachineInstr &MI,
628 SmallPtrSetImpl<MachineInstr *> &LocalMIs) {
629 unsigned TrueOp = 0;
630 unsigned FalseOp = 0;
631 bool Optimizable = false;
632 SmallVector<MachineOperand, 4> Cond;
633 if (TII->analyzeSelect(MI, Cond, TrueOp, FalseOp, Optimizable))
634 return false;
635 if (!Optimizable)
636 return false;
637 if (!TII->optimizeSelect(MI, LocalMIs))
638 return false;
639 MI.eraseFromParent();
640 ++NumSelects;
641 return true;
642}
643
644/// Check if a simpler conditional branch can be generated.
645bool PeepholeOptimizer::optimizeCondBranch(MachineInstr &MI) {
646 return TII->optimizeCondBranch(MI);
647}
648
649/// \brief Try to find the next source that share the same register file
650/// for the value defined by \p Reg and \p SubReg.
651/// When true is returned, the \p RewriteMap can be used by the client to
652/// retrieve all Def -> Use along the way up to the next source. Any found
653/// Use that is not itself a key for another entry, is the next source to
654/// use. During the search for the next source, multiple sources can be found
655/// given multiple incoming sources of a PHI instruction. In this case, we
656/// look in each PHI source for the next source; all found next sources must
657/// share the same register file as \p Reg and \p SubReg. The client should
658/// then be capable to rewrite all intermediate PHIs to get the next source.
659/// \return False if no alternative sources are available. True otherwise.
660bool PeepholeOptimizer::findNextSource(RegSubRegPair RegSubReg,
661 RewriteMapTy &RewriteMap) {
662 // Do not try to find a new source for a physical register.
663 // So far we do not have any motivating example for doing that.
664 // Thus, instead of maintaining untested code, we will revisit that if
665 // that changes at some point.
666 unsigned Reg = RegSubReg.Reg;
667 if (TargetRegisterInfo::isPhysicalRegister(Reg))
668 return false;
669 const TargetRegisterClass *DefRC = MRI->getRegClass(Reg);
670
671 SmallVector<RegSubRegPair, 4> SrcToLook;
672 RegSubRegPair CurSrcPair = RegSubReg;
673 SrcToLook.push_back(CurSrcPair);
674
675 unsigned PHICount = 0;
676 do {
677 CurSrcPair = SrcToLook.pop_back_val();
678 // As explained above, do not handle physical registers
679 if (TargetRegisterInfo::isPhysicalRegister(CurSrcPair.Reg))
680 return false;
681
682 ValueTracker ValTracker(CurSrcPair.Reg, CurSrcPair.SubReg, *MRI, TII);
683
684 // Follow the chain of copies until we find a more suitable source, a phi
685 // or have to abort.
686 while (true) {
687 ValueTrackerResult Res = ValTracker.getNextSource();
688 // Abort at the end of a chain (without finding a suitable source).
689 if (!Res.isValid())
690 return false;
691
692 // Insert the Def -> Use entry for the recently found source.
693 ValueTrackerResult CurSrcRes = RewriteMap.lookup(CurSrcPair);
694 if (CurSrcRes.isValid()) {
695 assert(CurSrcRes == Res && "ValueTrackerResult found must match")(static_cast <bool> (CurSrcRes == Res && "ValueTrackerResult found must match"
) ? void (0) : __assert_fail ("CurSrcRes == Res && \"ValueTrackerResult found must match\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/PeepholeOptimizer.cpp"
, 695, __extension__ __PRETTY_FUNCTION__))
;
696 // An existent entry with multiple sources is a PHI cycle we must avoid.
697 // Otherwise it's an entry with a valid next source we already found.
698 if (CurSrcRes.getNumSources() > 1) {
699 DEBUG(dbgs() << "findNextSource: found PHI cycle, aborting...\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("peephole-opt")) { dbgs() << "findNextSource: found PHI cycle, aborting...\n"
; } } while (false)
;
700 return false;
701 }
702 break;
703 }
704 RewriteMap.insert(std::make_pair(CurSrcPair, Res));
705
706 // ValueTrackerResult usually have one source unless it's the result from
707 // a PHI instruction. Add the found PHI edges to be looked up further.
708 unsigned NumSrcs = Res.getNumSources();
709 if (NumSrcs > 1) {
710 PHICount++;
711 if (PHICount >= RewritePHILimit) {
712 DEBUG(dbgs() << "findNextSource: PHI limit reached\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("peephole-opt")) { dbgs() << "findNextSource: PHI limit reached\n"
; } } while (false)
;
713 return false;
714 }
715
716 for (unsigned i = 0; i < NumSrcs; ++i)
717 SrcToLook.push_back(Res.getSrc(i));
718 break;
719 }
720
721 CurSrcPair = Res.getSrc(0);
722 // Do not extend the live-ranges of physical registers as they add
723 // constraints to the register allocator. Moreover, if we want to extend
724 // the live-range of a physical register, unlike SSA virtual register,
725 // we will have to check that they aren't redefine before the related use.
726 if (TargetRegisterInfo::isPhysicalRegister(CurSrcPair.Reg))
727 return false;
728
729 // Keep following the chain if the value isn't any better yet.
730 const TargetRegisterClass *SrcRC = MRI->getRegClass(CurSrcPair.Reg);
731 if (!TRI->shouldRewriteCopySrc(DefRC, RegSubReg.SubReg, SrcRC,
732 CurSrcPair.SubReg))
733 continue;
734
735 // We currently cannot deal with subreg operands on PHI instructions
736 // (see insertPHI()).
737 if (PHICount > 0 && CurSrcPair.SubReg != 0)
738 continue;
739
740 // We found a suitable source, and are done with this chain.
741 break;
742 }
743 } while (!SrcToLook.empty());
744
745 // If we did not find a more suitable source, there is nothing to optimize.
746 return CurSrcPair.Reg != Reg;
747}
748
749/// \brief Insert a PHI instruction with incoming edges \p SrcRegs that are
750/// guaranteed to have the same register class. This is necessary whenever we
751/// successfully traverse a PHI instruction and find suitable sources coming
752/// from its edges. By inserting a new PHI, we provide a rewritten PHI def
753/// suitable to be used in a new COPY instruction.
754static MachineInstr &
755insertPHI(MachineRegisterInfo &MRI, const TargetInstrInfo &TII,
756 const SmallVectorImpl<RegSubRegPair> &SrcRegs,
757 MachineInstr &OrigPHI) {
758 assert(!SrcRegs.empty() && "No sources to create a PHI instruction?")(static_cast <bool> (!SrcRegs.empty() && "No sources to create a PHI instruction?"
) ? void (0) : __assert_fail ("!SrcRegs.empty() && \"No sources to create a PHI instruction?\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/PeepholeOptimizer.cpp"
, 758, __extension__ __PRETTY_FUNCTION__))
;
759
760 const TargetRegisterClass *NewRC = MRI.getRegClass(SrcRegs[0].Reg);
761 // NewRC is only correct if no subregisters are involved. findNextSource()
762 // should have rejected those cases already.
763 assert(SrcRegs[0].SubReg == 0 && "should not have subreg operand")(static_cast <bool> (SrcRegs[0].SubReg == 0 && "should not have subreg operand"
) ? void (0) : __assert_fail ("SrcRegs[0].SubReg == 0 && \"should not have subreg operand\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/PeepholeOptimizer.cpp"
, 763, __extension__ __PRETTY_FUNCTION__))
;
764 unsigned NewVR = MRI.createVirtualRegister(NewRC);
765 MachineBasicBlock *MBB = OrigPHI.getParent();
766 MachineInstrBuilder MIB = BuildMI(*MBB, &OrigPHI, OrigPHI.getDebugLoc(),
767 TII.get(TargetOpcode::PHI), NewVR);
768
769 unsigned MBBOpIdx = 2;
770 for (const RegSubRegPair &RegPair : SrcRegs) {
771 MIB.addReg(RegPair.Reg, 0, RegPair.SubReg);
772 MIB.addMBB(OrigPHI.getOperand(MBBOpIdx).getMBB());
773 // Since we're extended the lifetime of RegPair.Reg, clear the
774 // kill flags to account for that and make RegPair.Reg reaches
775 // the new PHI.
776 MRI.clearKillFlags(RegPair.Reg);
777 MBBOpIdx += 2;
778 }
779
780 return *MIB;
781}
782
783namespace {
784
785/// Interface to query instructions amenable to copy rewriting.
786class Rewriter {
787protected:
788 MachineInstr &CopyLike;
789 unsigned CurrentSrcIdx = 0; ///< The index of the source being rewritten.
790public:
791 Rewriter(MachineInstr &CopyLike) : CopyLike(CopyLike) {}
792 virtual ~Rewriter() {}
793
794 /// \brief Get the next rewritable source (SrcReg, SrcSubReg) and
795 /// the related value that it affects (DstReg, DstSubReg).
796 /// A source is considered rewritable if its register class and the
797 /// register class of the related DstReg may not be register
798 /// coalescer friendly. In other words, given a copy-like instruction
799 /// not all the arguments may be returned at rewritable source, since
800 /// some arguments are none to be register coalescer friendly.
801 ///
802 /// Each call of this method moves the current source to the next
803 /// rewritable source.
804 /// For instance, let CopyLike be the instruction to rewrite.
805 /// CopyLike has one definition and one source:
806 /// dst.dstSubIdx = CopyLike src.srcSubIdx.
807 ///
808 /// The first call will give the first rewritable source, i.e.,
809 /// the only source this instruction has:
810 /// (SrcReg, SrcSubReg) = (src, srcSubIdx).
811 /// This source defines the whole definition, i.e.,
812 /// (DstReg, DstSubReg) = (dst, dstSubIdx).
813 ///
814 /// The second and subsequent calls will return false, as there is only one
815 /// rewritable source.
816 ///
817 /// \return True if a rewritable source has been found, false otherwise.
818 /// The output arguments are valid if and only if true is returned.
819 virtual bool getNextRewritableSource(RegSubRegPair &Src,
820 RegSubRegPair &Dst) = 0;
821
822 /// Rewrite the current source with \p NewReg and \p NewSubReg if possible.
823 /// \return True if the rewriting was possible, false otherwise.
824 virtual bool RewriteCurrentSource(unsigned NewReg, unsigned NewSubReg) = 0;
825};
826
827/// Rewriter for COPY instructions.
828class CopyRewriter : public Rewriter {
829public:
830 CopyRewriter(MachineInstr &MI) : Rewriter(MI) {
831 assert(MI.isCopy() && "Expected copy instruction")(static_cast <bool> (MI.isCopy() && "Expected copy instruction"
) ? void (0) : __assert_fail ("MI.isCopy() && \"Expected copy instruction\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/PeepholeOptimizer.cpp"
, 831, __extension__ __PRETTY_FUNCTION__))
;
832 }
833 virtual ~CopyRewriter() = default;
834
835 bool getNextRewritableSource(RegSubRegPair &Src,
836 RegSubRegPair &Dst) override {
837 // CurrentSrcIdx > 0 means this function has already been called.
838 if (CurrentSrcIdx > 0)
839 return false;
840 // This is the first call to getNextRewritableSource.
841 // Move the CurrentSrcIdx to remember that we made that call.
842 CurrentSrcIdx = 1;
843 // The rewritable source is the argument.
844 const MachineOperand &MOSrc = CopyLike.getOperand(1);
845 Src = RegSubRegPair(MOSrc.getReg(), MOSrc.getSubReg());
846 // What we track are the alternative sources of the definition.
847 const MachineOperand &MODef = CopyLike.getOperand(0);
848 Dst = RegSubRegPair(MODef.getReg(), MODef.getSubReg());
849 return true;
850 }
851
852 bool RewriteCurrentSource(unsigned NewReg, unsigned NewSubReg) override {
853 if (CurrentSrcIdx != 1)
854 return false;
855 MachineOperand &MOSrc = CopyLike.getOperand(CurrentSrcIdx);
856 MOSrc.setReg(NewReg);
857 MOSrc.setSubReg(NewSubReg);
858 return true;
859 }
860};
861
862/// \brief Helper class to rewrite uncoalescable copy like instructions
863/// into new COPY (coalescable friendly) instructions.
864class UncoalescableRewriter : public Rewriter {
865 unsigned NumDefs; ///< Number of defs in the bitcast.
866
867public:
868 UncoalescableRewriter(MachineInstr &MI) : Rewriter(MI) {
869 NumDefs = MI.getDesc().getNumDefs();
870 }
871
872 /// \see See Rewriter::getNextRewritableSource()
873 /// All such sources need to be considered rewritable in order to
874 /// rewrite a uncoalescable copy-like instruction. This method return
875 /// each definition that must be checked if rewritable.
876 bool getNextRewritableSource(RegSubRegPair &Src,
877 RegSubRegPair &Dst) override {
878 // Find the next non-dead definition and continue from there.
879 if (CurrentSrcIdx == NumDefs)
880 return false;
881
882 while (CopyLike.getOperand(CurrentSrcIdx).isDead()) {
883 ++CurrentSrcIdx;
884 if (CurrentSrcIdx == NumDefs)
885 return false;
886 }
887
888 // What we track are the alternative sources of the definition.
889 Src = RegSubRegPair(0, 0);
890 const MachineOperand &MODef = CopyLike.getOperand(CurrentSrcIdx);
891 Dst = RegSubRegPair(MODef.getReg(), MODef.getSubReg());
892
893 CurrentSrcIdx++;
894 return true;
895 }
896
897 bool RewriteCurrentSource(unsigned NewReg, unsigned NewSubReg) override {
898 return false;
899 }
900};
901
902/// Specialized rewriter for INSERT_SUBREG instruction.
903class InsertSubregRewriter : public Rewriter {
904public:
905 InsertSubregRewriter(MachineInstr &MI) : Rewriter(MI) {
906 assert(MI.isInsertSubreg() && "Invalid instruction")(static_cast <bool> (MI.isInsertSubreg() && "Invalid instruction"
) ? void (0) : __assert_fail ("MI.isInsertSubreg() && \"Invalid instruction\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/PeepholeOptimizer.cpp"
, 906, __extension__ __PRETTY_FUNCTION__))
;
907 }
908
909 /// \see See Rewriter::getNextRewritableSource()
910 /// Here CopyLike has the following form:
911 /// dst = INSERT_SUBREG Src1, Src2.src2SubIdx, subIdx.
912 /// Src1 has the same register class has dst, hence, there is
913 /// nothing to rewrite.
914 /// Src2.src2SubIdx, may not be register coalescer friendly.
915 /// Therefore, the first call to this method returns:
916 /// (SrcReg, SrcSubReg) = (Src2, src2SubIdx).
917 /// (DstReg, DstSubReg) = (dst, subIdx).
918 ///
919 /// Subsequence calls will return false.
920 bool getNextRewritableSource(RegSubRegPair &Src,
921 RegSubRegPair &Dst) override {
922 // If we already get the only source we can rewrite, return false.
923 if (CurrentSrcIdx == 2)
924 return false;
925 // We are looking at v2 = INSERT_SUBREG v0, v1, sub0.
926 CurrentSrcIdx = 2;
927 const MachineOperand &MOInsertedReg = CopyLike.getOperand(2);
928 Src = RegSubRegPair(MOInsertedReg.getReg(), MOInsertedReg.getSubReg());
929 const MachineOperand &MODef = CopyLike.getOperand(0);
930
931 // We want to track something that is compatible with the
932 // partial definition.
933 if (MODef.getSubReg())
934 // Bail if we have to compose sub-register indices.
935 return false;
936 Dst = RegSubRegPair(MODef.getReg(),
937 (unsigned)CopyLike.getOperand(3).getImm());
938 return true;
939 }
940
941 bool RewriteCurrentSource(unsigned NewReg, unsigned NewSubReg) override {
942 if (CurrentSrcIdx != 2)
943 return false;
944 // We are rewriting the inserted reg.
945 MachineOperand &MO = CopyLike.getOperand(CurrentSrcIdx);
946 MO.setReg(NewReg);
947 MO.setSubReg(NewSubReg);
948 return true;
949 }
950};
951
952/// Specialized rewriter for EXTRACT_SUBREG instruction.
953class ExtractSubregRewriter : public Rewriter {
954 const TargetInstrInfo &TII;
955
956public:
957 ExtractSubregRewriter(MachineInstr &MI, const TargetInstrInfo &TII)
958 : Rewriter(MI), TII(TII) {
959 assert(MI.isExtractSubreg() && "Invalid instruction")(static_cast <bool> (MI.isExtractSubreg() && "Invalid instruction"
) ? void (0) : __assert_fail ("MI.isExtractSubreg() && \"Invalid instruction\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/PeepholeOptimizer.cpp"
, 959, __extension__ __PRETTY_FUNCTION__))
;
960 }
961
962 /// \see Rewriter::getNextRewritableSource()
963 /// Here CopyLike has the following form:
964 /// dst.dstSubIdx = EXTRACT_SUBREG Src, subIdx.
965 /// There is only one rewritable source: Src.subIdx,
966 /// which defines dst.dstSubIdx.
967 bool getNextRewritableSource(RegSubRegPair &Src,
968 RegSubRegPair &Dst) override {
969 // If we already get the only source we can rewrite, return false.
970 if (CurrentSrcIdx == 1)
971 return false;
972 // We are looking at v1 = EXTRACT_SUBREG v0, sub0.
973 CurrentSrcIdx = 1;
974 const MachineOperand &MOExtractedReg = CopyLike.getOperand(1);
975 // If we have to compose sub-register indices, bail out.
976 if (MOExtractedReg.getSubReg())
977 return false;
978
979 Src = RegSubRegPair(MOExtractedReg.getReg(),
980 CopyLike.getOperand(2).getImm());
981
982 // We want to track something that is compatible with the definition.
983 const MachineOperand &MODef = CopyLike.getOperand(0);
984 Dst = RegSubRegPair(MODef.getReg(), MODef.getSubReg());
985 return true;
986 }
987
988 bool RewriteCurrentSource(unsigned NewReg, unsigned NewSubReg) override {
989 // The only source we can rewrite is the input register.
990 if (CurrentSrcIdx != 1)
991 return false;
992
993 CopyLike.getOperand(CurrentSrcIdx).setReg(NewReg);
994
995 // If we find a source that does not require to extract something,
996 // rewrite the operation with a copy.
997 if (!NewSubReg) {
998 // Move the current index to an invalid position.
999 // We do not want another call to this method to be able
1000 // to do any change.
1001 CurrentSrcIdx = -1;
1002 // Rewrite the operation as a COPY.
1003 // Get rid of the sub-register index.
1004 CopyLike.RemoveOperand(2);
1005 // Morph the operation into a COPY.
1006 CopyLike.setDesc(TII.get(TargetOpcode::COPY));
1007 return true;
1008 }
1009 CopyLike.getOperand(CurrentSrcIdx + 1).setImm(NewSubReg);
1010 return true;
1011 }
1012};
1013
1014/// Specialized rewriter for REG_SEQUENCE instruction.
1015class RegSequenceRewriter : public Rewriter {
1016public:
1017 RegSequenceRewriter(MachineInstr &MI) : Rewriter(MI) {
1018 assert(MI.isRegSequence() && "Invalid instruction")(static_cast <bool> (MI.isRegSequence() && "Invalid instruction"
) ? void (0) : __assert_fail ("MI.isRegSequence() && \"Invalid instruction\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/PeepholeOptimizer.cpp"
, 1018, __extension__ __PRETTY_FUNCTION__))
;
1019 }
1020
1021 /// \see Rewriter::getNextRewritableSource()
1022 /// Here CopyLike has the following form:
1023 /// dst = REG_SEQUENCE Src1.src1SubIdx, subIdx1, Src2.src2SubIdx, subIdx2.
1024 /// Each call will return a different source, walking all the available
1025 /// source.
1026 ///
1027 /// The first call returns:
1028 /// (SrcReg, SrcSubReg) = (Src1, src1SubIdx).
1029 /// (DstReg, DstSubReg) = (dst, subIdx1).
1030 ///
1031 /// The second call returns:
1032 /// (SrcReg, SrcSubReg) = (Src2, src2SubIdx).
1033 /// (DstReg, DstSubReg) = (dst, subIdx2).
1034 ///
1035 /// And so on, until all the sources have been traversed, then
1036 /// it returns false.
1037 bool getNextRewritableSource(RegSubRegPair &Src,
1038 RegSubRegPair &Dst) override {
1039 // We are looking at v0 = REG_SEQUENCE v1, sub1, v2, sub2, etc.
1040
1041 // If this is the first call, move to the first argument.
1042 if (CurrentSrcIdx == 0) {
1043 CurrentSrcIdx = 1;
1044 } else {
1045 // Otherwise, move to the next argument and check that it is valid.
1046 CurrentSrcIdx += 2;
1047 if (CurrentSrcIdx >= CopyLike.getNumOperands())
1048 return false;
1049 }
1050 const MachineOperand &MOInsertedReg = CopyLike.getOperand(CurrentSrcIdx);
1051 Src.Reg = MOInsertedReg.getReg();
1052 // If we have to compose sub-register indices, bail out.
1053 if ((Src.SubReg = MOInsertedReg.getSubReg()))
1054 return false;
1055
1056 // We want to track something that is compatible with the related
1057 // partial definition.
1058 Dst.SubReg = CopyLike.getOperand(CurrentSrcIdx + 1).getImm();
1059
1060 const MachineOperand &MODef = CopyLike.getOperand(0);
1061 Dst.Reg = MODef.getReg();
1062 // If we have to compose sub-registers, bail.
1063 return MODef.getSubReg() == 0;
1064 }
1065
1066 bool RewriteCurrentSource(unsigned NewReg, unsigned NewSubReg) override {
1067 // We cannot rewrite out of bound operands.
1068 // Moreover, rewritable sources are at odd positions.
1069 if ((CurrentSrcIdx & 1) != 1 || CurrentSrcIdx > CopyLike.getNumOperands())
1070 return false;
1071
1072 MachineOperand &MO = CopyLike.getOperand(CurrentSrcIdx);
1073 MO.setReg(NewReg);
1074 MO.setSubReg(NewSubReg);
1075 return true;
1076 }
1077};
1078
1079} // end anonymous namespace
1080
1081/// Get the appropriated Rewriter for \p MI.
1082/// \return A pointer to a dynamically allocated Rewriter or nullptr if no
1083/// rewriter works for \p MI.
1084static Rewriter *getCopyRewriter(MachineInstr &MI, const TargetInstrInfo &TII) {
1085 // Handle uncoalescable copy-like instructions.
1086 if (MI.isBitcast() || MI.isRegSequenceLike() || MI.isInsertSubregLike() ||
1087 MI.isExtractSubregLike())
1088 return new UncoalescableRewriter(MI);
1089
1090 switch (MI.getOpcode()) {
1091 default:
1092 return nullptr;
1093 case TargetOpcode::COPY:
1094 return new CopyRewriter(MI);
1095 case TargetOpcode::INSERT_SUBREG:
1096 return new InsertSubregRewriter(MI);
1097 case TargetOpcode::EXTRACT_SUBREG:
1098 return new ExtractSubregRewriter(MI, TII);
1099 case TargetOpcode::REG_SEQUENCE:
1100 return new RegSequenceRewriter(MI);
1101 }
1102}
1103
1104/// \brief Given a \p Def.Reg and Def.SubReg pair, use \p RewriteMap to find
1105/// the new source to use for rewrite. If \p HandleMultipleSources is true and
1106/// multiple sources for a given \p Def are found along the way, we found a
1107/// PHI instructions that needs to be rewritten.
1108/// TODO: HandleMultipleSources should be removed once we test PHI handling
1109/// with coalescable copies.
1110static RegSubRegPair
1111getNewSource(MachineRegisterInfo *MRI, const TargetInstrInfo *TII,
1112 RegSubRegPair Def,
1113 const PeepholeOptimizer::RewriteMapTy &RewriteMap,
1114 bool HandleMultipleSources = true) {
1115 RegSubRegPair LookupSrc(Def.Reg, Def.SubReg);
1116 while (true) {
1117 ValueTrackerResult Res = RewriteMap.lookup(LookupSrc);
1118 // If there are no entries on the map, LookupSrc is the new source.
1119 if (!Res.isValid())
1120 return LookupSrc;
1121
1122 // There's only one source for this definition, keep searching...
1123 unsigned NumSrcs = Res.getNumSources();
1124 if (NumSrcs == 1) {
1125 LookupSrc.Reg = Res.getSrcReg(0);
1126 LookupSrc.SubReg = Res.getSrcSubReg(0);
1127 continue;
1128 }
1129
1130 // TODO: Remove once multiple srcs w/ coalescable copies are supported.
1131 if (!HandleMultipleSources)
1132 break;
1133
1134 // Multiple sources, recurse into each source to find a new source
1135 // for it. Then, rewrite the PHI accordingly to its new edges.
1136 SmallVector<RegSubRegPair, 4> NewPHISrcs;
1137 for (unsigned i = 0; i < NumSrcs; ++i) {
1138 RegSubRegPair PHISrc(Res.getSrcReg(i), Res.getSrcSubReg(i));
1139 NewPHISrcs.push_back(
1140 getNewSource(MRI, TII, PHISrc, RewriteMap, HandleMultipleSources));
1141 }
1142
1143 // Build the new PHI node and return its def register as the new source.
1144 MachineInstr &OrigPHI = const_cast<MachineInstr &>(*Res.getInst());
1145 MachineInstr &NewPHI = insertPHI(*MRI, *TII, NewPHISrcs, OrigPHI);
1146 DEBUG(dbgs() << "-- getNewSource\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("peephole-opt")) { dbgs() << "-- getNewSource\n"; } } while
(false)
;
1147 DEBUG(dbgs() << " Replacing: " << OrigPHI)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("peephole-opt")) { dbgs() << " Replacing: " <<
OrigPHI; } } while (false)
;
1148 DEBUG(dbgs() << " With: " << NewPHI)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("peephole-opt")) { dbgs() << " With: " <<
NewPHI; } } while (false)
;
1149 const MachineOperand &MODef = NewPHI.getOperand(0);
1150 return RegSubRegPair(MODef.getReg(), MODef.getSubReg());
1151 }
1152
1153 return RegSubRegPair(0, 0);
1154}
1155
1156/// Optimize generic copy instructions to avoid cross register bank copy.
1157/// The optimization looks through a chain of copies and tries to find a source
1158/// that has a compatible register class.
1159/// Two register classes are considered to be compatible if they share the same
1160/// register bank.
1161/// New copies issued by this optimization are register allocator
1162/// friendly. This optimization does not remove any copy as it may
1163/// overconstrain the register allocator, but replaces some operands
1164/// when possible.
1165/// \pre isCoalescableCopy(*MI) is true.
1166/// \return True, when \p MI has been rewritten. False otherwise.
1167bool PeepholeOptimizer::optimizeCoalescableCopy(MachineInstr &MI) {
1168 assert(isCoalescableCopy(MI) && "Invalid argument")(static_cast <bool> (isCoalescableCopy(MI) && "Invalid argument"
) ? void (0) : __assert_fail ("isCoalescableCopy(MI) && \"Invalid argument\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/PeepholeOptimizer.cpp"
, 1168, __extension__ __PRETTY_FUNCTION__))
;
1169 assert(MI.getDesc().getNumDefs() == 1 &&(static_cast <bool> (MI.getDesc().getNumDefs() == 1 &&
"Coalescer can understand multiple defs?!") ? void (0) : __assert_fail
("MI.getDesc().getNumDefs() == 1 && \"Coalescer can understand multiple defs?!\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/PeepholeOptimizer.cpp"
, 1170, __extension__ __PRETTY_FUNCTION__))
1170 "Coalescer can understand multiple defs?!")(static_cast <bool> (MI.getDesc().getNumDefs() == 1 &&
"Coalescer can understand multiple defs?!") ? void (0) : __assert_fail
("MI.getDesc().getNumDefs() == 1 && \"Coalescer can understand multiple defs?!\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/PeepholeOptimizer.cpp"
, 1170, __extension__ __PRETTY_FUNCTION__))
;
1171 const MachineOperand &MODef = MI.getOperand(0);
1172 // Do not rewrite physical definitions.
1173 if (TargetRegisterInfo::isPhysicalRegister(MODef.getReg()))
1174 return false;
1175
1176 bool Changed = false;
1177 // Get the right rewriter for the current copy.
1178 std::unique_ptr<Rewriter> CpyRewriter(getCopyRewriter(MI, *TII));
1179 // If none exists, bail out.
1180 if (!CpyRewriter)
1181 return false;
1182 // Rewrite each rewritable source.
1183 RegSubRegPair Src;
1184 RegSubRegPair TrackPair;
1185 while (CpyRewriter->getNextRewritableSource(Src, TrackPair)) {
1186 // Keep track of PHI nodes and its incoming edges when looking for sources.
1187 RewriteMapTy RewriteMap;
1188 // Try to find a more suitable source. If we failed to do so, or get the
1189 // actual source, move to the next source.
1190 if (!findNextSource(TrackPair, RewriteMap))
1191 continue;
1192
1193 // Get the new source to rewrite. TODO: Only enable handling of multiple
1194 // sources (PHIs) once we have a motivating example and testcases for it.
1195 RegSubRegPair NewSrc = getNewSource(MRI, TII, TrackPair, RewriteMap,
1196 /*HandleMultipleSources=*/false);
1197 if (Src.Reg == NewSrc.Reg || NewSrc.Reg == 0)
1198 continue;
1199
1200 // Rewrite source.
1201 if (CpyRewriter->RewriteCurrentSource(NewSrc.Reg, NewSrc.SubReg)) {
1202 // We may have extended the live-range of NewSrc, account for that.
1203 MRI->clearKillFlags(NewSrc.Reg);
1204 Changed = true;
1205 }
1206 }
1207 // TODO: We could have a clean-up method to tidy the instruction.
1208 // E.g., v0 = INSERT_SUBREG v1, v1.sub0, sub0
1209 // => v0 = COPY v1
1210 // Currently we haven't seen motivating example for that and we
1211 // want to avoid untested code.
1212 NumRewrittenCopies += Changed;
1213 return Changed;
1214}
1215
1216/// \brief Rewrite the source found through \p Def, by using the \p RewriteMap
1217/// and create a new COPY instruction. More info about RewriteMap in
1218/// PeepholeOptimizer::findNextSource. Right now this is only used to handle
1219/// Uncoalescable copies, since they are copy like instructions that aren't
1220/// recognized by the register allocator.
1221MachineInstr &
1222PeepholeOptimizer::rewriteSource(MachineInstr &CopyLike,
1223 RegSubRegPair Def, RewriteMapTy &RewriteMap) {
1224 assert(!TargetRegisterInfo::isPhysicalRegister(Def.Reg) &&(static_cast <bool> (!TargetRegisterInfo::isPhysicalRegister
(Def.Reg) && "We do not rewrite physical registers") ?
void (0) : __assert_fail ("!TargetRegisterInfo::isPhysicalRegister(Def.Reg) && \"We do not rewrite physical registers\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/PeepholeOptimizer.cpp"
, 1225, __extension__ __PRETTY_FUNCTION__))
1225 "We do not rewrite physical registers")(static_cast <bool> (!TargetRegisterInfo::isPhysicalRegister
(Def.Reg) && "We do not rewrite physical registers") ?
void (0) : __assert_fail ("!TargetRegisterInfo::isPhysicalRegister(Def.Reg) && \"We do not rewrite physical registers\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/PeepholeOptimizer.cpp"
, 1225, __extension__ __PRETTY_FUNCTION__))
;
1226
1227 // Find the new source to use in the COPY rewrite.
1228 RegSubRegPair NewSrc = getNewSource(MRI, TII, Def, RewriteMap);
1229
1230 // Insert the COPY.
1231 const TargetRegisterClass *DefRC = MRI->getRegClass(Def.Reg);
1232 unsigned NewVReg = MRI->createVirtualRegister(DefRC);
1233
1234 MachineInstr *NewCopy =
1235 BuildMI(*CopyLike.getParent(), &CopyLike, CopyLike.getDebugLoc(),
1236 TII->get(TargetOpcode::COPY), NewVReg)
1237 .addReg(NewSrc.Reg, 0, NewSrc.SubReg);
1238
1239 if (Def.SubReg) {
1240 NewCopy->getOperand(0).setSubReg(Def.SubReg);
1241 NewCopy->getOperand(0).setIsUndef();
1242 }
1243
1244 DEBUG(dbgs() << "-- RewriteSource\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("peephole-opt")) { dbgs() << "-- RewriteSource\n"; } }
while (false)
;
1245 DEBUG(dbgs() << " Replacing: " << CopyLike)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("peephole-opt")) { dbgs() << " Replacing: " <<
CopyLike; } } while (false)
;
1246 DEBUG(dbgs() << " With: " << *NewCopy)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("peephole-opt")) { dbgs() << " With: " <<
*NewCopy; } } while (false)
;
1247 MRI->replaceRegWith(Def.Reg, NewVReg);
1248 MRI->clearKillFlags(NewVReg);
1249
1250 // We extended the lifetime of NewSrc.Reg, clear the kill flags to
1251 // account for that.
1252 MRI->clearKillFlags(NewSrc.Reg);
1253
1254 return *NewCopy;
1255}
1256
1257/// \brief Optimize copy-like instructions to create
1258/// register coalescer friendly instruction.
1259/// The optimization tries to kill-off the \p MI by looking
1260/// through a chain of copies to find a source that has a compatible
1261/// register class.
1262/// If such a source is found, it replace \p MI by a generic COPY
1263/// operation.
1264/// \pre isUncoalescableCopy(*MI) is true.
1265/// \return True, when \p MI has been optimized. In that case, \p MI has
1266/// been removed from its parent.
1267/// All COPY instructions created, are inserted in \p LocalMIs.
1268bool PeepholeOptimizer::optimizeUncoalescableCopy(
1269 MachineInstr &MI, SmallPtrSetImpl<MachineInstr *> &LocalMIs) {
1270 assert(isUncoalescableCopy(MI) && "Invalid argument")(static_cast <bool> (isUncoalescableCopy(MI) &&
"Invalid argument") ? void (0) : __assert_fail ("isUncoalescableCopy(MI) && \"Invalid argument\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/PeepholeOptimizer.cpp"
, 1270, __extension__ __PRETTY_FUNCTION__))
;
1271 UncoalescableRewriter CpyRewriter(MI);
1272
1273 // Rewrite each rewritable source by generating new COPYs. This works
1274 // differently from optimizeCoalescableCopy since it first makes sure that all
1275 // definitions can be rewritten.
1276 RewriteMapTy RewriteMap;
1277 RegSubRegPair Src;
1278 RegSubRegPair Def;
1279 SmallVector<RegSubRegPair, 4> RewritePairs;
1280 while (CpyRewriter.getNextRewritableSource(Src, Def)) {
1281 // If a physical register is here, this is probably for a good reason.
1282 // Do not rewrite that.
1283 if (TargetRegisterInfo::isPhysicalRegister(Def.Reg))
1284 return false;
1285
1286 // If we do not know how to rewrite this definition, there is no point
1287 // in trying to kill this instruction.
1288 if (!findNextSource(Def, RewriteMap))
1289 return false;
1290
1291 RewritePairs.push_back(Def);
1292 }
1293
1294 // The change is possible for all defs, do it.
1295 for (const RegSubRegPair &Def : RewritePairs) {
1296 // Rewrite the "copy" in a way the register coalescer understands.
1297 MachineInstr &NewCopy = rewriteSource(MI, Def, RewriteMap);
1298 LocalMIs.insert(&NewCopy);
1299 }
1300
1301 // MI is now dead.
1302 MI.eraseFromParent();
1303 ++NumUncoalescableCopies;
1304 return true;
1305}
1306
1307/// Check whether MI is a candidate for folding into a later instruction.
1308/// We only fold loads to virtual registers and the virtual register defined
1309/// has a single use.
1310bool PeepholeOptimizer::isLoadFoldable(
1311 MachineInstr &MI, SmallSet<unsigned, 16> &FoldAsLoadDefCandidates) {
1312 if (!MI.canFoldAsLoad() || !MI.mayLoad())
1313 return false;
1314 const MCInstrDesc &MCID = MI.getDesc();
1315 if (MCID.getNumDefs() != 1)
1316 return false;
1317
1318 unsigned Reg = MI.getOperand(0).getReg();
1319 // To reduce compilation time, we check MRI->hasOneNonDBGUse when inserting
1320 // loads. It should be checked when processing uses of the load, since
1321 // uses can be removed during peephole.
1322 if (!MI.getOperand(0).getSubReg() &&
1323 TargetRegisterInfo::isVirtualRegister(Reg) &&
1324 MRI->hasOneNonDBGUse(Reg)) {
1325 FoldAsLoadDefCandidates.insert(Reg);
1326 return true;
1327 }
1328 return false;
1329}
1330
1331bool PeepholeOptimizer::isMoveImmediate(
1332 MachineInstr &MI, SmallSet<unsigned, 4> &ImmDefRegs,
1333 DenseMap<unsigned, MachineInstr *> &ImmDefMIs) {
1334 const MCInstrDesc &MCID = MI.getDesc();
1335 if (!MI.isMoveImmediate())
1336 return false;
1337 if (MCID.getNumDefs() != 1)
1338 return false;
1339 unsigned Reg = MI.getOperand(0).getReg();
1340 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
1341 ImmDefMIs.insert(std::make_pair(Reg, &MI));
1342 ImmDefRegs.insert(Reg);
1343 return true;
1344 }
1345
1346 return false;
1347}
1348
1349/// Try folding register operands that are defined by move immediate
1350/// instructions, i.e. a trivial constant folding optimization, if
1351/// and only if the def and use are in the same BB.
1352bool PeepholeOptimizer::foldImmediate(MachineInstr &MI,
1353 SmallSet<unsigned, 4> &ImmDefRegs,
1354 DenseMap<unsigned, MachineInstr *> &ImmDefMIs) {
1355 for (unsigned i = 0, e = MI.getDesc().getNumOperands(); i != e; ++i) {
1356 MachineOperand &MO = MI.getOperand(i);
1357 if (!MO.isReg() || MO.isDef())
1358 continue;
1359 // Ignore dead implicit defs.
1360 if (MO.isImplicit() && MO.isDead())
1361 continue;
1362 unsigned Reg = MO.getReg();
1363 if (!TargetRegisterInfo::isVirtualRegister(Reg))
1364 continue;
1365 if (ImmDefRegs.count(Reg) == 0)
1366 continue;
1367 DenseMap<unsigned, MachineInstr*>::iterator II = ImmDefMIs.find(Reg);
1368 assert(II != ImmDefMIs.end() && "couldn't find immediate definition")(static_cast <bool> (II != ImmDefMIs.end() && "couldn't find immediate definition"
) ? void (0) : __assert_fail ("II != ImmDefMIs.end() && \"couldn't find immediate definition\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/PeepholeOptimizer.cpp"
, 1368, __extension__ __PRETTY_FUNCTION__))
;
1369 if (TII->FoldImmediate(MI, *II->second, Reg, MRI)) {
1370 ++NumImmFold;
1371 return true;
1372 }
1373 }
1374 return false;
1375}
1376
1377// FIXME: This is very simple and misses some cases which should be handled when
1378// motivating examples are found.
1379//
1380// The copy rewriting logic should look at uses as well as defs and be able to
1381// eliminate copies across blocks.
1382//
1383// Later copies that are subregister extracts will also not be eliminated since
1384// only the first copy is considered.
1385//
1386// e.g.
1387// %1 = COPY %0
1388// %2 = COPY %0:sub1
1389//
1390// Should replace %2 uses with %1:sub1
1391bool PeepholeOptimizer::foldRedundantCopy(MachineInstr &MI,
1392 SmallSet<unsigned, 4> &CopySrcRegs,
1393 DenseMap<unsigned, MachineInstr *> &CopyMIs) {
1394 assert(MI.isCopy() && "expected a COPY machine instruction")(static_cast <bool> (MI.isCopy() && "expected a COPY machine instruction"
) ? void (0) : __assert_fail ("MI.isCopy() && \"expected a COPY machine instruction\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/PeepholeOptimizer.cpp"
, 1394, __extension__ __PRETTY_FUNCTION__))
;
1395
1396 unsigned SrcReg = MI.getOperand(1).getReg();
1397 if (!TargetRegisterInfo::isVirtualRegister(SrcReg))
1398 return false;
1399
1400 unsigned DstReg = MI.getOperand(0).getReg();
1401 if (!TargetRegisterInfo::isVirtualRegister(DstReg))
1402 return false;
1403
1404 if (CopySrcRegs.insert(SrcReg).second) {
1405 // First copy of this reg seen.
1406 CopyMIs.insert(std::make_pair(SrcReg, &MI));
1407 return false;
1408 }
1409
1410 MachineInstr *PrevCopy = CopyMIs.find(SrcReg)->second;
1411
1412 unsigned SrcSubReg = MI.getOperand(1).getSubReg();
1413 unsigned PrevSrcSubReg = PrevCopy->getOperand(1).getSubReg();
1414
1415 // Can't replace different subregister extracts.
1416 if (SrcSubReg != PrevSrcSubReg)
1417 return false;
1418
1419 unsigned PrevDstReg = PrevCopy->getOperand(0).getReg();
1420
1421 // Only replace if the copy register class is the same.
1422 //
1423 // TODO: If we have multiple copies to different register classes, we may want
1424 // to track multiple copies of the same source register.
1425 if (MRI->getRegClass(DstReg) != MRI->getRegClass(PrevDstReg))
1426 return false;
1427
1428 MRI->replaceRegWith(DstReg, PrevDstReg);
1429
1430 // Lifetime of the previous copy has been extended.
1431 MRI->clearKillFlags(PrevDstReg);
1432 return true;
1433}
1434
1435bool PeepholeOptimizer::isNAPhysCopy(unsigned Reg) {
1436 return TargetRegisterInfo::isPhysicalRegister(Reg) &&
1437 !MRI->isAllocatable(Reg);
1438}
1439
1440bool PeepholeOptimizer::foldRedundantNAPhysCopy(
1441 MachineInstr &MI, DenseMap<unsigned, MachineInstr *> &NAPhysToVirtMIs) {
1442 assert(MI.isCopy() && "expected a COPY machine instruction")(static_cast <bool> (MI.isCopy() && "expected a COPY machine instruction"
) ? void (0) : __assert_fail ("MI.isCopy() && \"expected a COPY machine instruction\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/PeepholeOptimizer.cpp"
, 1442, __extension__ __PRETTY_FUNCTION__))
;
1443
1444 if (DisableNAPhysCopyOpt)
1445 return false;
1446
1447 unsigned DstReg = MI.getOperand(0).getReg();
1448 unsigned SrcReg = MI.getOperand(1).getReg();
1449 if (isNAPhysCopy(SrcReg) && TargetRegisterInfo::isVirtualRegister(DstReg)) {
1450 // %vreg = COPY %physreg
1451 // Avoid using a datastructure which can track multiple live non-allocatable
1452 // phys->virt copies since LLVM doesn't seem to do this.
1453 NAPhysToVirtMIs.insert({SrcReg, &MI});
1454 return false;
1455 }
1456
1457 if (!(TargetRegisterInfo::isVirtualRegister(SrcReg) && isNAPhysCopy(DstReg)))
1458 return false;
1459
1460 // %physreg = COPY %vreg
1461 auto PrevCopy = NAPhysToVirtMIs.find(DstReg);
1462 if (PrevCopy == NAPhysToVirtMIs.end()) {
1463 // We can't remove the copy: there was an intervening clobber of the
1464 // non-allocatable physical register after the copy to virtual.
1465 DEBUG(dbgs() << "NAPhysCopy: intervening clobber forbids erasing " << MI)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("peephole-opt")) { dbgs() << "NAPhysCopy: intervening clobber forbids erasing "
<< MI; } } while (false)
;
1466 return false;
1467 }
1468
1469 unsigned PrevDstReg = PrevCopy->second->getOperand(0).getReg();
1470 if (PrevDstReg == SrcReg) {
1471 // Remove the virt->phys copy: we saw the virtual register definition, and
1472 // the non-allocatable physical register's state hasn't changed since then.
1473 DEBUG(dbgs() << "NAPhysCopy: erasing " << MI)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("peephole-opt")) { dbgs() << "NAPhysCopy: erasing " <<
MI; } } while (false)
;
1474 ++NumNAPhysCopies;
1475 return true;
1476 }
1477
1478 // Potential missed optimization opportunity: we saw a different virtual
1479 // register get a copy of the non-allocatable physical register, and we only
1480 // track one such copy. Avoid getting confused by this new non-allocatable
1481 // physical register definition, and remove it from the tracked copies.
1482 DEBUG(dbgs() << "NAPhysCopy: missed opportunity " << MI)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("peephole-opt")) { dbgs() << "NAPhysCopy: missed opportunity "
<< MI; } } while (false)
;
1483 NAPhysToVirtMIs.erase(PrevCopy);
1484 return false;
1485}
1486
1487/// \bried Returns true if \p MO is a virtual register operand.
1488static bool isVirtualRegisterOperand(MachineOperand &MO) {
1489 if (!MO.isReg())
1490 return false;
1491 return TargetRegisterInfo::isVirtualRegister(MO.getReg());
1492}
1493
1494bool PeepholeOptimizer::findTargetRecurrence(
1495 unsigned Reg, const SmallSet<unsigned, 2> &TargetRegs,
1496 RecurrenceCycle &RC) {
1497 // Recurrence found if Reg is in TargetRegs.
1498 if (TargetRegs.count(Reg))
1499 return true;
1500
1501 // TODO: Curerntly, we only allow the last instruction of the recurrence
1502 // cycle (the instruction that feeds the PHI instruction) to have more than
1503 // one uses to guarantee that commuting operands does not tie registers
1504 // with overlapping live range. Once we have actual live range info of
1505 // each register, this constraint can be relaxed.
1506 if (!MRI->hasOneNonDBGUse(Reg))
1507 return false;
1508
1509 // Give up if the reccurrence chain length is longer than the limit.
1510 if (RC.size() >= MaxRecurrenceChain)
1511 return false;
1512
1513 MachineInstr &MI = *(MRI->use_instr_nodbg_begin(Reg));
1514 unsigned Idx = MI.findRegisterUseOperandIdx(Reg);
1515
1516 // Only interested in recurrences whose instructions have only one def, which
1517 // is a virtual register.
1518 if (MI.getDesc().getNumDefs() != 1)
1519 return false;
1520
1521 MachineOperand &DefOp = MI.getOperand(0);
1522 if (!isVirtualRegisterOperand(DefOp))
1523 return false;
1524
1525 // Check if def operand of MI is tied to any use operand. We are only
1526 // interested in the case that all the instructions in the recurrence chain
1527 // have there def operand tied with one of the use operand.
1528 unsigned TiedUseIdx;
1529 if (!MI.isRegTiedToUseOperand(0, &TiedUseIdx))
1530 return false;
1531
1532 if (Idx == TiedUseIdx) {
1533 RC.push_back(RecurrenceInstr(&MI));
1534 return findTargetRecurrence(DefOp.getReg(), TargetRegs, RC);
1535 } else {
1536 // If Idx is not TiedUseIdx, check if Idx is commutable with TiedUseIdx.
1537 unsigned CommIdx = TargetInstrInfo::CommuteAnyOperandIndex;
1538 if (TII->findCommutedOpIndices(MI, Idx, CommIdx) && CommIdx == TiedUseIdx) {
1539 RC.push_back(RecurrenceInstr(&MI, Idx, CommIdx));
1540 return findTargetRecurrence(DefOp.getReg(), TargetRegs, RC);
1541 }
1542 }
1543
1544 return false;
1545}
1546
1547/// Phi instructions will eventually be lowered to copy instructions.
1548/// If phi is in a loop header, a recurrence may formulated around the source
1549/// and destination of the phi. For such case commuting operands of the
1550/// instructions in the recurrence may enable coalescing of the copy instruction
1551/// generated from the phi. For example, if there is a recurrence of
1552///
1553/// LoopHeader:
1554/// %1 = phi(%0, %100)
1555/// LoopLatch:
1556/// %0<def, tied1> = ADD %2<def, tied0>, %1
1557///
1558/// , the fact that %0 and %2 are in the same tied operands set makes
1559/// the coalescing of copy instruction generated from the phi in
1560/// LoopHeader(i.e. %1 = COPY %0) impossible, because %1 and
1561/// %2 have overlapping live range. This introduces additional move
1562/// instruction to the final assembly. However, if we commute %2 and
1563/// %1 of ADD instruction, the redundant move instruction can be
1564/// avoided.
1565bool PeepholeOptimizer::optimizeRecurrence(MachineInstr &PHI) {
1566 SmallSet<unsigned, 2> TargetRegs;
1567 for (unsigned Idx = 1; Idx < PHI.getNumOperands(); Idx += 2) {
1568 MachineOperand &MO = PHI.getOperand(Idx);
1569 assert(isVirtualRegisterOperand(MO) && "Invalid PHI instruction")(static_cast <bool> (isVirtualRegisterOperand(MO) &&
"Invalid PHI instruction") ? void (0) : __assert_fail ("isVirtualRegisterOperand(MO) && \"Invalid PHI instruction\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/PeepholeOptimizer.cpp"
, 1569, __extension__ __PRETTY_FUNCTION__))
;
1570 TargetRegs.insert(MO.getReg());
1571 }
1572
1573 bool Changed = false;
1574 RecurrenceCycle RC;
1575 if (findTargetRecurrence(PHI.getOperand(0).getReg(), TargetRegs, RC)) {
1576 // Commutes operands of instructions in RC if necessary so that the copy to
1577 // be generated from PHI can be coalesced.
1578 DEBUG(dbgs() << "Optimize recurrence chain from " << PHI)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("peephole-opt")) { dbgs() << "Optimize recurrence chain from "
<< PHI; } } while (false)
;
1579 for (auto &RI : RC) {
1580 DEBUG(dbgs() << "\tInst: " << *(RI.getMI()))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("peephole-opt")) { dbgs() << "\tInst: " << *(RI.
getMI()); } } while (false)
;
1581 auto CP = RI.getCommutePair();
1582 if (CP) {
1583 Changed = true;
1584 TII->commuteInstruction(*(RI.getMI()), false, (*CP).first,
1585 (*CP).second);
1586 DEBUG(dbgs() << "\t\tCommuted: " << *(RI.getMI()))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("peephole-opt")) { dbgs() << "\t\tCommuted: " <<
*(RI.getMI()); } } while (false)
;
1587 }
1588 }
1589 }
1590
1591 return Changed;
1592}
1593
1594bool PeepholeOptimizer::runOnMachineFunction(MachineFunction &MF) {
1595 if (skipFunction(MF.getFunction()))
1
Assuming the condition is false
2
Taking false branch
1596 return false;
1597
1598 DEBUG(dbgs() << "********** PEEPHOLE OPTIMIZER **********\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("peephole-opt")) { dbgs() << "********** PEEPHOLE OPTIMIZER **********\n"
; } } while (false)
;
1599 DEBUG(dbgs() << "********** Function: " << MF.getName() << '\n')do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("peephole-opt")) { dbgs() << "********** Function: " <<
MF.getName() << '\n'; } } while (false)
;
1600
1601 if (DisablePeephole)
3
Assuming the condition is false
4
Taking false branch
1602 return false;
1603
1604 TII = MF.getSubtarget().getInstrInfo();
1605 TRI = MF.getSubtarget().getRegisterInfo();
1606 MRI = &MF.getRegInfo();
1607 DT = Aggressive ? &getAnalysis<MachineDominatorTree>() : nullptr;
5
Assuming the condition is false
6
'?' condition is false
7
Null pointer value stored to field 'DT'
1608 MLI = &getAnalysis<MachineLoopInfo>();
1609
1610 bool Changed = false;
1611
1612 for (MachineBasicBlock &MBB : MF) {
1613 bool SeenMoveImm = false;
1614
1615 // During this forward scan, at some point it needs to answer the question
1616 // "given a pointer to an MI in the current BB, is it located before or
1617 // after the current instruction".
1618 // To perform this, the following set keeps track of the MIs already seen
1619 // during the scan, if a MI is not in the set, it is assumed to be located
1620 // after. Newly created MIs have to be inserted in the set as well.
1621 SmallPtrSet<MachineInstr*, 16> LocalMIs;
1622 SmallSet<unsigned, 4> ImmDefRegs;
1623 DenseMap<unsigned, MachineInstr*> ImmDefMIs;
1624 SmallSet<unsigned, 16> FoldAsLoadDefCandidates;
1625
1626 // Track when a non-allocatable physical register is copied to a virtual
1627 // register so that useless moves can be removed.
1628 //
1629 // %physreg is the map index; MI is the last valid `%vreg = COPY %physreg`
1630 // without any intervening re-definition of %physreg.
1631 DenseMap<unsigned, MachineInstr *> NAPhysToVirtMIs;
1632
1633 // Set of virtual registers that are copied from.
1634 SmallSet<unsigned, 4> CopySrcRegs;
1635 DenseMap<unsigned, MachineInstr *> CopySrcMIs;
1636
1637 bool IsLoopHeader = MLI->isLoopHeader(&MBB);
1638
1639 for (MachineBasicBlock::iterator MII = MBB.begin(), MIE = MBB.end();
8
Loop condition is true. Entering loop body
1640 MII != MIE; ) {
1641 MachineInstr *MI = &*MII;
1642 // We may be erasing MI below, increment MII now.
1643 ++MII;
1644 LocalMIs.insert(MI);
1645
1646 // Skip debug values. They should not affect this peephole optimization.
1647 if (MI->isDebugValue())
9
Taking false branch
1648 continue;
1649
1650 if (MI->isPosition())
10
Taking false branch
1651 continue;
1652
1653 if (IsLoopHeader && MI->isPHI()) {
11
Assuming 'IsLoopHeader' is 0
1654 if (optimizeRecurrence(*MI)) {
1655 Changed = true;
1656 continue;
1657 }
1658 }
1659
1660 if (!MI->isCopy()) {
12
Taking false branch
1661 for (const MachineOperand &MO : MI->operands()) {
1662 // Visit all operands: definitions can be implicit or explicit.
1663 if (MO.isReg()) {
1664 unsigned Reg = MO.getReg();
1665 if (MO.isDef() && isNAPhysCopy(Reg)) {
1666 const auto &Def = NAPhysToVirtMIs.find(Reg);
1667 if (Def != NAPhysToVirtMIs.end()) {
1668 // A new definition of the non-allocatable physical register
1669 // invalidates previous copies.
1670 DEBUG(dbgs() << "NAPhysCopy: invalidating because of " << *MI)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("peephole-opt")) { dbgs() << "NAPhysCopy: invalidating because of "
<< *MI; } } while (false)
;
1671 NAPhysToVirtMIs.erase(Def);
1672 }
1673 }
1674 } else if (MO.isRegMask()) {
1675 const uint32_t *RegMask = MO.getRegMask();
1676 for (auto &RegMI : NAPhysToVirtMIs) {
1677 unsigned Def = RegMI.first;
1678 if (MachineOperand::clobbersPhysReg(RegMask, Def)) {
1679 DEBUG(dbgs() << "NAPhysCopy: invalidating because of " << *MI)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("peephole-opt")) { dbgs() << "NAPhysCopy: invalidating because of "
<< *MI; } } while (false)
;
1680 NAPhysToVirtMIs.erase(Def);
1681 }
1682 }
1683 }
1684 }
1685 }
1686
1687 if (MI->isImplicitDef() || MI->isKill())
13
Taking false branch
1688 continue;
1689
1690 if (MI->isInlineAsm() || MI->hasUnmodeledSideEffects()) {
14
Assuming the condition is false
15
Taking false branch
1691 // Blow away all non-allocatable physical registers knowledge since we
1692 // don't know what's correct anymore.
1693 //
1694 // FIXME: handle explicit asm clobbers.
1695 DEBUG(dbgs() << "NAPhysCopy: blowing away all info due to " << *MI)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("peephole-opt")) { dbgs() << "NAPhysCopy: blowing away all info due to "
<< *MI; } } while (false)
;
1696 NAPhysToVirtMIs.clear();
1697 }
1698
1699 if ((isUncoalescableCopy(*MI) &&
1700 optimizeUncoalescableCopy(*MI, LocalMIs)) ||
1701 (MI->isCompare() && optimizeCmpInstr(*MI)) ||
16
Assuming the condition is false
1702 (MI->isSelect() && optimizeSelect(*MI, LocalMIs))) {
17
Assuming the condition is false
1703 // MI is deleted.
1704 LocalMIs.erase(MI);
1705 Changed = true;
1706 continue;
1707 }
1708
1709 if (MI->isConditionalBranch() && optimizeCondBranch(*MI)) {
1710 Changed = true;
1711 continue;
1712 }
1713
1714 if (isCoalescableCopy(*MI) && optimizeCoalescableCopy(*MI)) {
1715 // MI is just rewritten.
1716 Changed = true;
1717 continue;
1718 }
1719
1720 if (MI->isCopy() &&
1721 (foldRedundantCopy(*MI, CopySrcRegs, CopySrcMIs) ||
1722 foldRedundantNAPhysCopy(*MI, NAPhysToVirtMIs))) {
1723 LocalMIs.erase(MI);
1724 MI->eraseFromParent();
1725 Changed = true;
1726 continue;
1727 }
1728
1729 if (isMoveImmediate(*MI, ImmDefRegs, ImmDefMIs)) {
18
Taking false branch
1730 SeenMoveImm = true;
1731 } else {
1732 Changed |= optimizeExtInstr(*MI, MBB, LocalMIs);
19
Calling 'PeepholeOptimizer::optimizeExtInstr'
1733 // optimizeExtInstr might have created new instructions after MI
1734 // and before the already incremented MII. Adjust MII so that the
1735 // next iteration sees the new instructions.
1736 MII = MI;
1737 ++MII;
1738 if (SeenMoveImm)
1739 Changed |= foldImmediate(*MI, ImmDefRegs, ImmDefMIs);
1740 }
1741
1742 // Check whether MI is a load candidate for folding into a later
1743 // instruction. If MI is not a candidate, check whether we can fold an
1744 // earlier load into MI.
1745 if (!isLoadFoldable(*MI, FoldAsLoadDefCandidates) &&
1746 !FoldAsLoadDefCandidates.empty()) {
1747
1748 // We visit each operand even after successfully folding a previous
1749 // one. This allows us to fold multiple loads into a single
1750 // instruction. We do assume that optimizeLoadInstr doesn't insert
1751 // foldable uses earlier in the argument list. Since we don't restart
1752 // iteration, we'd miss such cases.
1753 const MCInstrDesc &MIDesc = MI->getDesc();
1754 for (unsigned i = MIDesc.getNumDefs(); i != MI->getNumOperands();
1755 ++i) {
1756 const MachineOperand &MOp = MI->getOperand(i);
1757 if (!MOp.isReg())
1758 continue;
1759 unsigned FoldAsLoadDefReg = MOp.getReg();
1760 if (FoldAsLoadDefCandidates.count(FoldAsLoadDefReg)) {
1761 // We need to fold load after optimizeCmpInstr, since
1762 // optimizeCmpInstr can enable folding by converting SUB to CMP.
1763 // Save FoldAsLoadDefReg because optimizeLoadInstr() resets it and
1764 // we need it for markUsesInDebugValueAsUndef().
1765 unsigned FoldedReg = FoldAsLoadDefReg;
1766 MachineInstr *DefMI = nullptr;
1767 if (MachineInstr *FoldMI =
1768 TII->optimizeLoadInstr(*MI, MRI, FoldAsLoadDefReg, DefMI)) {
1769 // Update LocalMIs since we replaced MI with FoldMI and deleted
1770 // DefMI.
1771 DEBUG(dbgs() << "Replacing: " << *MI)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("peephole-opt")) { dbgs() << "Replacing: " << *MI
; } } while (false)
;
1772 DEBUG(dbgs() << " With: " << *FoldMI)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("peephole-opt")) { dbgs() << " With: " << *FoldMI
; } } while (false)
;
1773 LocalMIs.erase(MI);
1774 LocalMIs.erase(DefMI);
1775 LocalMIs.insert(FoldMI);
1776 MI->eraseFromParent();
1777 DefMI->eraseFromParent();
1778 MRI->markUsesInDebugValueAsUndef(FoldedReg);
1779 FoldAsLoadDefCandidates.erase(FoldedReg);
1780 ++NumLoadFold;
1781
1782 // MI is replaced with FoldMI so we can continue trying to fold
1783 Changed = true;
1784 MI = FoldMI;
1785 }
1786 }
1787 }
1788 }
1789
1790 // If we run into an instruction we can't fold across, discard
1791 // the load candidates. Note: We might be able to fold *into* this
1792 // instruction, so this needs to be after the folding logic.
1793 if (MI->isLoadFoldBarrier()) {
1794 DEBUG(dbgs() << "Encountered load fold barrier on " << *MI)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("peephole-opt")) { dbgs() << "Encountered load fold barrier on "
<< *MI; } } while (false)
;
1795 FoldAsLoadDefCandidates.clear();
1796 }
1797 }
1798 }
1799
1800 return Changed;
1801}
1802
1803ValueTrackerResult ValueTracker::getNextSourceFromCopy() {
1804 assert(Def->isCopy() && "Invalid definition")(static_cast <bool> (Def->isCopy() && "Invalid definition"
) ? void (0) : __assert_fail ("Def->isCopy() && \"Invalid definition\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/PeepholeOptimizer.cpp"
, 1804, __extension__ __PRETTY_FUNCTION__))
;
1805 // Copy instruction are supposed to be: Def = Src.
1806 // If someone breaks this assumption, bad things will happen everywhere.
1807 assert(Def->getNumOperands() == 2 && "Invalid number of operands")(static_cast <bool> (Def->getNumOperands() == 2 &&
"Invalid number of operands") ? void (0) : __assert_fail ("Def->getNumOperands() == 2 && \"Invalid number of operands\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/PeepholeOptimizer.cpp"
, 1807, __extension__ __PRETTY_FUNCTION__))
;
1808
1809 if (Def->getOperand(DefIdx).getSubReg() != DefSubReg)
1810 // If we look for a different subreg, it means we want a subreg of src.
1811 // Bails as we do not support composing subregs yet.
1812 return ValueTrackerResult();
1813 // Otherwise, we want the whole source.
1814 const MachineOperand &Src = Def->getOperand(1);
1815 if (Src.isUndef())
1816 return ValueTrackerResult();
1817 return ValueTrackerResult(Src.getReg(), Src.getSubReg());
1818}
1819
1820ValueTrackerResult ValueTracker::getNextSourceFromBitcast() {
1821 assert(Def->isBitcast() && "Invalid definition")(static_cast <bool> (Def->isBitcast() && "Invalid definition"
) ? void (0) : __assert_fail ("Def->isBitcast() && \"Invalid definition\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/PeepholeOptimizer.cpp"
, 1821, __extension__ __PRETTY_FUNCTION__))
;
1822
1823 // Bail if there are effects that a plain copy will not expose.
1824 if (Def->hasUnmodeledSideEffects())
1825 return ValueTrackerResult();
1826
1827 // Bitcasts with more than one def are not supported.
1828 if (Def->getDesc().getNumDefs() != 1)
1829 return ValueTrackerResult();
1830 const MachineOperand DefOp = Def->getOperand(DefIdx);
1831 if (DefOp.getSubReg() != DefSubReg)
1832 // If we look for a different subreg, it means we want a subreg of the src.
1833 // Bails as we do not support composing subregs yet.
1834 return ValueTrackerResult();
1835
1836 unsigned SrcIdx = Def->getNumOperands();
1837 for (unsigned OpIdx = DefIdx + 1, EndOpIdx = SrcIdx; OpIdx != EndOpIdx;
1838 ++OpIdx) {
1839 const MachineOperand &MO = Def->getOperand(OpIdx);
1840 if (!MO.isReg() || !MO.getReg())
1841 continue;
1842 // Ignore dead implicit defs.
1843 if (MO.isImplicit() && MO.isDead())
1844 continue;
1845 assert(!MO.isDef() && "We should have skipped all the definitions by now")(static_cast <bool> (!MO.isDef() && "We should have skipped all the definitions by now"
) ? void (0) : __assert_fail ("!MO.isDef() && \"We should have skipped all the definitions by now\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/PeepholeOptimizer.cpp"
, 1845, __extension__ __PRETTY_FUNCTION__))
;
1846 if (SrcIdx != EndOpIdx)
1847 // Multiple sources?
1848 return ValueTrackerResult();
1849 SrcIdx = OpIdx;
1850 }
1851
1852 // Stop when any user of the bitcast is a SUBREG_TO_REG, replacing with a COPY
1853 // will break the assumed guarantees for the upper bits.
1854 for (const MachineInstr &UseMI : MRI.use_nodbg_instructions(DefOp.getReg())) {
1855 if (UseMI.isSubregToReg())
1856 return ValueTrackerResult();
1857 }
1858
1859 const MachineOperand &Src = Def->getOperand(SrcIdx);
1860 if (Src.isUndef())
1861 return ValueTrackerResult();
1862 return ValueTrackerResult(Src.getReg(), Src.getSubReg());
1863}
1864
1865ValueTrackerResult ValueTracker::getNextSourceFromRegSequence() {
1866 assert((Def->isRegSequence() || Def->isRegSequenceLike()) &&(static_cast <bool> ((Def->isRegSequence() || Def->
isRegSequenceLike()) && "Invalid definition") ? void (
0) : __assert_fail ("(Def->isRegSequence() || Def->isRegSequenceLike()) && \"Invalid definition\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/PeepholeOptimizer.cpp"
, 1867, __extension__ __PRETTY_FUNCTION__))
1867 "Invalid definition")(static_cast <bool> ((Def->isRegSequence() || Def->
isRegSequenceLike()) && "Invalid definition") ? void (
0) : __assert_fail ("(Def->isRegSequence() || Def->isRegSequenceLike()) && \"Invalid definition\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/PeepholeOptimizer.cpp"
, 1867, __extension__ __PRETTY_FUNCTION__))
;
1868
1869 if (Def->getOperand(DefIdx).getSubReg())
1870 // If we are composing subregs, bail out.
1871 // The case we are checking is Def.<subreg> = REG_SEQUENCE.
1872 // This should almost never happen as the SSA property is tracked at
1873 // the register level (as opposed to the subreg level).
1874 // I.e.,
1875 // Def.sub0 =
1876 // Def.sub1 =
1877 // is a valid SSA representation for Def.sub0 and Def.sub1, but not for
1878 // Def. Thus, it must not be generated.
1879 // However, some code could theoretically generates a single
1880 // Def.sub0 (i.e, not defining the other subregs) and we would
1881 // have this case.
1882 // If we can ascertain (or force) that this never happens, we could
1883 // turn that into an assertion.
1884 return ValueTrackerResult();
1885
1886 if (!TII)
1887 // We could handle the REG_SEQUENCE here, but we do not want to
1888 // duplicate the code from the generic TII.
1889 return ValueTrackerResult();
1890
1891 SmallVector<RegSubRegPairAndIdx, 8> RegSeqInputRegs;
1892 if (!TII->getRegSequenceInputs(*Def, DefIdx, RegSeqInputRegs))
1893 return ValueTrackerResult();
1894
1895 // We are looking at:
1896 // Def = REG_SEQUENCE v0, sub0, v1, sub1, ...
1897 // Check if one of the operand defines the subreg we are interested in.
1898 for (const RegSubRegPairAndIdx &RegSeqInput : RegSeqInputRegs) {
1899 if (RegSeqInput.SubIdx == DefSubReg) {
1900 if (RegSeqInput.SubReg)
1901 // Bail if we have to compose sub registers.
1902 return ValueTrackerResult();
1903
1904 return ValueTrackerResult(RegSeqInput.Reg, RegSeqInput.SubReg);
1905 }
1906 }
1907
1908 // If the subreg we are tracking is super-defined by another subreg,
1909 // we could follow this value. However, this would require to compose
1910 // the subreg and we do not do that for now.
1911 return ValueTrackerResult();
1912}
1913
1914ValueTrackerResult ValueTracker::getNextSourceFromInsertSubreg() {
1915 assert((Def->isInsertSubreg() || Def->isInsertSubregLike()) &&(static_cast <bool> ((Def->isInsertSubreg() || Def->
isInsertSubregLike()) && "Invalid definition") ? void
(0) : __assert_fail ("(Def->isInsertSubreg() || Def->isInsertSubregLike()) && \"Invalid definition\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/PeepholeOptimizer.cpp"
, 1916, __extension__ __PRETTY_FUNCTION__))
1916 "Invalid definition")(static_cast <bool> ((Def->isInsertSubreg() || Def->
isInsertSubregLike()) && "Invalid definition") ? void
(0) : __assert_fail ("(Def->isInsertSubreg() || Def->isInsertSubregLike()) && \"Invalid definition\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/PeepholeOptimizer.cpp"
, 1916, __extension__ __PRETTY_FUNCTION__))
;
1917
1918 if (Def->getOperand(DefIdx).getSubReg())
1919 // If we are composing subreg, bail out.
1920 // Same remark as getNextSourceFromRegSequence.
1921 // I.e., this may be turned into an assert.
1922 return ValueTrackerResult();
1923
1924 if (!TII)
1925 // We could handle the REG_SEQUENCE here, but we do not want to
1926 // duplicate the code from the generic TII.
1927 return ValueTrackerResult();
1928
1929 RegSubRegPair BaseReg;
1930 RegSubRegPairAndIdx InsertedReg;
1931 if (!TII->getInsertSubregInputs(*Def, DefIdx, BaseReg, InsertedReg))
1932 return ValueTrackerResult();
1933
1934 // We are looking at:
1935 // Def = INSERT_SUBREG v0, v1, sub1
1936 // There are two cases:
1937 // 1. DefSubReg == sub1, get v1.
1938 // 2. DefSubReg != sub1, the value may be available through v0.
1939
1940 // #1 Check if the inserted register matches the required sub index.
1941 if (InsertedReg.SubIdx == DefSubReg) {
1942 return ValueTrackerResult(InsertedReg.Reg, InsertedReg.SubReg);
1943 }
1944 // #2 Otherwise, if the sub register we are looking for is not partial
1945 // defined by the inserted element, we can look through the main
1946 // register (v0).
1947 const MachineOperand &MODef = Def->getOperand(DefIdx);
1948 // If the result register (Def) and the base register (v0) do not
1949 // have the same register class or if we have to compose
1950 // subregisters, bail out.
1951 if (MRI.getRegClass(MODef.getReg()) != MRI.getRegClass(BaseReg.Reg) ||
1952 BaseReg.SubReg)
1953 return ValueTrackerResult();
1954
1955 // Get the TRI and check if the inserted sub-register overlaps with the
1956 // sub-register we are tracking.
1957 const TargetRegisterInfo *TRI = MRI.getTargetRegisterInfo();
1958 if (!TRI ||
1959 !(TRI->getSubRegIndexLaneMask(DefSubReg) &
1960 TRI->getSubRegIndexLaneMask(InsertedReg.SubIdx)).none())
1961 return ValueTrackerResult();
1962 // At this point, the value is available in v0 via the same subreg
1963 // we used for Def.
1964 return ValueTrackerResult(BaseReg.Reg, DefSubReg);
1965}
1966
1967ValueTrackerResult ValueTracker::getNextSourceFromExtractSubreg() {
1968 assert((Def->isExtractSubreg() ||(static_cast <bool> ((Def->isExtractSubreg() || Def->
isExtractSubregLike()) && "Invalid definition") ? void
(0) : __assert_fail ("(Def->isExtractSubreg() || Def->isExtractSubregLike()) && \"Invalid definition\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/PeepholeOptimizer.cpp"
, 1969, __extension__ __PRETTY_FUNCTION__))
1969 Def->isExtractSubregLike()) && "Invalid definition")(static_cast <bool> ((Def->isExtractSubreg() || Def->
isExtractSubregLike()) && "Invalid definition") ? void
(0) : __assert_fail ("(Def->isExtractSubreg() || Def->isExtractSubregLike()) && \"Invalid definition\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/PeepholeOptimizer.cpp"
, 1969, __extension__ __PRETTY_FUNCTION__))
;
1970 // We are looking at:
1971 // Def = EXTRACT_SUBREG v0, sub0
1972
1973 // Bail if we have to compose sub registers.
1974 // Indeed, if DefSubReg != 0, we would have to compose it with sub0.
1975 if (DefSubReg)
1976 return ValueTrackerResult();
1977
1978 if (!TII)
1979 // We could handle the EXTRACT_SUBREG here, but we do not want to
1980 // duplicate the code from the generic TII.
1981 return ValueTrackerResult();
1982
1983 RegSubRegPairAndIdx ExtractSubregInputReg;
1984 if (!TII->getExtractSubregInputs(*Def, DefIdx, ExtractSubregInputReg))
1985 return ValueTrackerResult();
1986
1987 // Bail if we have to compose sub registers.
1988 // Likewise, if v0.subreg != 0, we would have to compose v0.subreg with sub0.
1989 if (ExtractSubregInputReg.SubReg)
1990 return ValueTrackerResult();
1991 // Otherwise, the value is available in the v0.sub0.
1992 return ValueTrackerResult(ExtractSubregInputReg.Reg,
1993 ExtractSubregInputReg.SubIdx);
1994}
1995
1996ValueTrackerResult ValueTracker::getNextSourceFromSubregToReg() {
1997 assert(Def->isSubregToReg() && "Invalid definition")(static_cast <bool> (Def->isSubregToReg() &&
"Invalid definition") ? void (0) : __assert_fail ("Def->isSubregToReg() && \"Invalid definition\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/PeepholeOptimizer.cpp"
, 1997, __extension__ __PRETTY_FUNCTION__))
;
1998 // We are looking at:
1999 // Def = SUBREG_TO_REG Imm, v0, sub0
2000
2001 // Bail if we have to compose sub registers.
2002 // If DefSubReg != sub0, we would have to check that all the bits
2003 // we track are included in sub0 and if yes, we would have to
2004 // determine the right subreg in v0.
2005 if (DefSubReg != Def->getOperand(3).getImm())
2006 return ValueTrackerResult();
2007 // Bail if we have to compose sub registers.
2008 // Likewise, if v0.subreg != 0, we would have to compose it with sub0.
2009 if (Def->getOperand(2).getSubReg())
2010 return ValueTrackerResult();
2011
2012 return ValueTrackerResult(Def->getOperand(2).getReg(),
2013 Def->getOperand(3).getImm());
2014}
2015
2016/// Explore each PHI incoming operand and return its sources.
2017ValueTrackerResult ValueTracker::getNextSourceFromPHI() {
2018 assert(Def->isPHI() && "Invalid definition")(static_cast <bool> (Def->isPHI() && "Invalid definition"
) ? void (0) : __assert_fail ("Def->isPHI() && \"Invalid definition\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/PeepholeOptimizer.cpp"
, 2018, __extension__ __PRETTY_FUNCTION__))
;
2019 ValueTrackerResult Res;
2020
2021 // If we look for a different subreg, bail as we do not support composing
2022 // subregs yet.
2023 if (Def->getOperand(0).getSubReg() != DefSubReg)
2024 return ValueTrackerResult();
2025
2026 // Return all register sources for PHI instructions.
2027 for (unsigned i = 1, e = Def->getNumOperands(); i < e; i += 2) {
2028 const MachineOperand &MO = Def->getOperand(i);
2029 assert(MO.isReg() && "Invalid PHI instruction")(static_cast <bool> (MO.isReg() && "Invalid PHI instruction"
) ? void (0) : __assert_fail ("MO.isReg() && \"Invalid PHI instruction\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/PeepholeOptimizer.cpp"
, 2029, __extension__ __PRETTY_FUNCTION__))
;
2030 // We have no code to deal with undef operands. They shouldn't happen in
2031 // normal programs anyway.
2032 if (MO.isUndef())
2033 return ValueTrackerResult();
2034 Res.addSource(MO.getReg(), MO.getSubReg());
2035 }
2036
2037 return Res;
2038}
2039
2040ValueTrackerResult ValueTracker::getNextSourceImpl() {
2041 assert(Def && "This method needs a valid definition")(static_cast <bool> (Def && "This method needs a valid definition"
) ? void (0) : __assert_fail ("Def && \"This method needs a valid definition\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/PeepholeOptimizer.cpp"
, 2041, __extension__ __PRETTY_FUNCTION__))
;
2042
2043 assert(((Def->getOperand(DefIdx).isDef() &&(static_cast <bool> (((Def->getOperand(DefIdx).isDef
() && (DefIdx < Def->getDesc().getNumDefs() || Def
->getDesc().isVariadic())) || Def->getOperand(DefIdx).isImplicit
()) && "Invalid DefIdx") ? void (0) : __assert_fail (
"((Def->getOperand(DefIdx).isDef() && (DefIdx < Def->getDesc().getNumDefs() || Def->getDesc().isVariadic())) || Def->getOperand(DefIdx).isImplicit()) && \"Invalid DefIdx\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/PeepholeOptimizer.cpp"
, 2047, __extension__ __PRETTY_FUNCTION__))
2044 (DefIdx < Def->getDesc().getNumDefs() ||(static_cast <bool> (((Def->getOperand(DefIdx).isDef
() && (DefIdx < Def->getDesc().getNumDefs() || Def
->getDesc().isVariadic())) || Def->getOperand(DefIdx).isImplicit
()) && "Invalid DefIdx") ? void (0) : __assert_fail (
"((Def->getOperand(DefIdx).isDef() && (DefIdx < Def->getDesc().getNumDefs() || Def->getDesc().isVariadic())) || Def->getOperand(DefIdx).isImplicit()) && \"Invalid DefIdx\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/PeepholeOptimizer.cpp"
, 2047, __extension__ __PRETTY_FUNCTION__))
2045 Def->getDesc().isVariadic())) ||(static_cast <bool> (((Def->getOperand(DefIdx).isDef
() && (DefIdx < Def->getDesc().getNumDefs() || Def
->getDesc().isVariadic())) || Def->getOperand(DefIdx).isImplicit
()) && "Invalid DefIdx") ? void (0) : __assert_fail (
"((Def->getOperand(DefIdx).isDef() && (DefIdx < Def->getDesc().getNumDefs() || Def->getDesc().isVariadic())) || Def->getOperand(DefIdx).isImplicit()) && \"Invalid DefIdx\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/PeepholeOptimizer.cpp"
, 2047, __extension__ __PRETTY_FUNCTION__))
2046 Def->getOperand(DefIdx).isImplicit()) &&(static_cast <bool> (((Def->getOperand(DefIdx).isDef
() && (DefIdx < Def->getDesc().getNumDefs() || Def
->getDesc().isVariadic())) || Def->getOperand(DefIdx).isImplicit
()) && "Invalid DefIdx") ? void (0) : __assert_fail (
"((Def->getOperand(DefIdx).isDef() && (DefIdx < Def->getDesc().getNumDefs() || Def->getDesc().isVariadic())) || Def->getOperand(DefIdx).isImplicit()) && \"Invalid DefIdx\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/PeepholeOptimizer.cpp"
, 2047, __extension__ __PRETTY_FUNCTION__))
2047 "Invalid DefIdx")(static_cast <bool> (((Def->getOperand(DefIdx).isDef
() && (DefIdx < Def->getDesc().getNumDefs() || Def
->getDesc().isVariadic())) || Def->getOperand(DefIdx).isImplicit
()) && "Invalid DefIdx") ? void (0) : __assert_fail (
"((Def->getOperand(DefIdx).isDef() && (DefIdx < Def->getDesc().getNumDefs() || Def->getDesc().isVariadic())) || Def->getOperand(DefIdx).isImplicit()) && \"Invalid DefIdx\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/PeepholeOptimizer.cpp"
, 2047, __extension__ __PRETTY_FUNCTION__))
;
2048 if (Def->isCopy())
2049 return getNextSourceFromCopy();
2050 if (Def->isBitcast())
2051 return getNextSourceFromBitcast();
2052 // All the remaining cases involve "complex" instructions.
2053 // Bail if we did not ask for the advanced tracking.
2054 if (DisableAdvCopyOpt)
2055 return ValueTrackerResult();
2056 if (Def->isRegSequence() || Def->isRegSequenceLike())
2057 return getNextSourceFromRegSequence();
2058 if (Def->isInsertSubreg() || Def->isInsertSubregLike())
2059 return getNextSourceFromInsertSubreg();
2060 if (Def->isExtractSubreg() || Def->isExtractSubregLike())
2061 return getNextSourceFromExtractSubreg();
2062 if (Def->isSubregToReg())
2063 return getNextSourceFromSubregToReg();
2064 if (Def->isPHI())
2065 return getNextSourceFromPHI();
2066 return ValueTrackerResult();
2067}
2068
2069ValueTrackerResult ValueTracker::getNextSource() {
2070 // If we reach a point where we cannot move up in the use-def chain,
2071 // there is nothing we can get.
2072 if (!Def)
2073 return ValueTrackerResult();
2074
2075 ValueTrackerResult Res = getNextSourceImpl();
2076 if (Res.isValid()) {
2077 // Update definition, definition index, and subregister for the
2078 // next call of getNextSource.
2079 // Update the current register.
2080 bool OneRegSrc = Res.getNumSources() == 1;
2081 if (OneRegSrc)
2082 Reg = Res.getSrcReg(0);
2083 // Update the result before moving up in the use-def chain
2084 // with the instruction containing the last found sources.
2085 Res.setInst(Def);
2086
2087 // If we can still move up in the use-def chain, move to the next
2088 // definition.
2089 if (!TargetRegisterInfo::isPhysicalRegister(Reg) && OneRegSrc) {
2090 MachineRegisterInfo::def_iterator DI = MRI.def_begin(Reg);
2091 if (DI != MRI.def_end()) {
2092 Def = DI->getParent();
2093 DefIdx = DI.getOperandNo();
2094 DefSubReg = Res.getSrcSubReg(0);
2095 } else {
2096 Def = nullptr;
2097 }
2098 return Res;
2099 }
2100 }
2101 // If we end up here, this means we will not be able to find another source
2102 // for the next iteration. Make sure any new call to getNextSource bails out
2103 // early by cutting the use-def chain.
2104 Def = nullptr;
2105 return Res;
2106}