Bug Summary

File:include/llvm/CodeGen/SelectionDAGNodes.h
Warning:line 1163, column 10
Called C++ object pointer is null

Annotated Source Code

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clang -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name RISCVISelLowering.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mthread-model posix -mframe-pointer=none -fmath-errno -masm-verbose -mconstructor-aliases -munwind-tables -fuse-init-array -target-cpu x86-64 -dwarf-column-info -debugger-tuning=gdb -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-10/lib/clang/10.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-10~svn374814/build-llvm/lib/Target/RISCV -I /build/llvm-toolchain-snapshot-10~svn374814/lib/Target/RISCV -I /build/llvm-toolchain-snapshot-10~svn374814/build-llvm/include -I /build/llvm-toolchain-snapshot-10~svn374814/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0/backward -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-10/lib/clang/10.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++14 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-10~svn374814/build-llvm/lib/Target/RISCV -fdebug-prefix-map=/build/llvm-toolchain-snapshot-10~svn374814=. -ferror-limit 19 -fmessage-length 0 -fvisibility-inlines-hidden -stack-protector 2 -fgnuc-version=4.2.1 -fobjc-runtime=gcc -fdiagnostics-show-option -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -o /tmp/scan-build-2019-10-15-035155-28452-1 -x c++ /build/llvm-toolchain-snapshot-10~svn374814/lib/Target/RISCV/RISCVISelLowering.cpp

/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/RISCV/RISCVISelLowering.cpp

1//===-- RISCVISelLowering.cpp - RISCV DAG Lowering Implementation --------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the interfaces that RISCV uses to lower LLVM code into a
10// selection DAG.
11//
12//===----------------------------------------------------------------------===//
13
14#include "RISCVISelLowering.h"
15#include "RISCV.h"
16#include "RISCVMachineFunctionInfo.h"
17#include "RISCVRegisterInfo.h"
18#include "RISCVSubtarget.h"
19#include "RISCVTargetMachine.h"
20#include "Utils/RISCVMatInt.h"
21#include "llvm/ADT/SmallSet.h"
22#include "llvm/ADT/Statistic.h"
23#include "llvm/CodeGen/CallingConvLower.h"
24#include "llvm/CodeGen/MachineFrameInfo.h"
25#include "llvm/CodeGen/MachineFunction.h"
26#include "llvm/CodeGen/MachineInstrBuilder.h"
27#include "llvm/CodeGen/MachineRegisterInfo.h"
28#include "llvm/CodeGen/SelectionDAGISel.h"
29#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
30#include "llvm/CodeGen/ValueTypes.h"
31#include "llvm/IR/DiagnosticInfo.h"
32#include "llvm/IR/DiagnosticPrinter.h"
33#include "llvm/Support/Debug.h"
34#include "llvm/Support/ErrorHandling.h"
35#include "llvm/Support/raw_ostream.h"
36
37using namespace llvm;
38
39#define DEBUG_TYPE"riscv-lower" "riscv-lower"
40
41STATISTIC(NumTailCalls, "Number of tail calls")static llvm::Statistic NumTailCalls = {"riscv-lower", "NumTailCalls"
, "Number of tail calls"}
;
42
43RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
44 const RISCVSubtarget &STI)
45 : TargetLowering(TM), Subtarget(STI) {
46
47 if (Subtarget.isRV32E())
48 report_fatal_error("Codegen not yet implemented for RV32E");
49
50 RISCVABI::ABI ABI = Subtarget.getTargetABI();
51 assert(ABI != RISCVABI::ABI_Unknown && "Improperly initialised target ABI")((ABI != RISCVABI::ABI_Unknown && "Improperly initialised target ABI"
) ? static_cast<void> (0) : __assert_fail ("ABI != RISCVABI::ABI_Unknown && \"Improperly initialised target ABI\""
, "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/RISCV/RISCVISelLowering.cpp"
, 51, __PRETTY_FUNCTION__))
;
52
53 switch (ABI) {
54 default:
55 report_fatal_error("Don't know how to lower this ABI");
56 case RISCVABI::ABI_ILP32:
57 case RISCVABI::ABI_ILP32F:
58 case RISCVABI::ABI_ILP32D:
59 case RISCVABI::ABI_LP64:
60 case RISCVABI::ABI_LP64F:
61 case RISCVABI::ABI_LP64D:
62 break;
63 }
64
65 MVT XLenVT = Subtarget.getXLenVT();
66
67 // Set up the register classes.
68 addRegisterClass(XLenVT, &RISCV::GPRRegClass);
69
70 if (Subtarget.hasStdExtF())
71 addRegisterClass(MVT::f32, &RISCV::FPR32RegClass);
72 if (Subtarget.hasStdExtD())
73 addRegisterClass(MVT::f64, &RISCV::FPR64RegClass);
74
75 // Compute derived properties from the register classes.
76 computeRegisterProperties(STI.getRegisterInfo());
77
78 setStackPointerRegisterToSaveRestore(RISCV::X2);
79
80 for (auto N : {ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD})
81 setLoadExtAction(N, XLenVT, MVT::i1, Promote);
82
83 // TODO: add all necessary setOperationAction calls.
84 setOperationAction(ISD::DYNAMIC_STACKALLOC, XLenVT, Expand);
85
86 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
87 setOperationAction(ISD::BR_CC, XLenVT, Expand);
88 setOperationAction(ISD::SELECT, XLenVT, Custom);
89 setOperationAction(ISD::SELECT_CC, XLenVT, Expand);
90
91 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
92 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
93
94 setOperationAction(ISD::VASTART, MVT::Other, Custom);
95 setOperationAction(ISD::VAARG, MVT::Other, Expand);
96 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
97 setOperationAction(ISD::VAEND, MVT::Other, Expand);
98
99 for (auto VT : {MVT::i1, MVT::i8, MVT::i16})
100 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
101
102 if (Subtarget.is64Bit()) {
103 setOperationAction(ISD::ADD, MVT::i32, Custom);
104 setOperationAction(ISD::SUB, MVT::i32, Custom);
105 setOperationAction(ISD::SHL, MVT::i32, Custom);
106 setOperationAction(ISD::SRA, MVT::i32, Custom);
107 setOperationAction(ISD::SRL, MVT::i32, Custom);
108 }
109
110 if (!Subtarget.hasStdExtM()) {
111 setOperationAction(ISD::MUL, XLenVT, Expand);
112 setOperationAction(ISD::MULHS, XLenVT, Expand);
113 setOperationAction(ISD::MULHU, XLenVT, Expand);
114 setOperationAction(ISD::SDIV, XLenVT, Expand);
115 setOperationAction(ISD::UDIV, XLenVT, Expand);
116 setOperationAction(ISD::SREM, XLenVT, Expand);
117 setOperationAction(ISD::UREM, XLenVT, Expand);
118 }
119
120 if (Subtarget.is64Bit() && Subtarget.hasStdExtM()) {
121 setOperationAction(ISD::MUL, MVT::i32, Custom);
122 setOperationAction(ISD::SDIV, MVT::i32, Custom);
123 setOperationAction(ISD::UDIV, MVT::i32, Custom);
124 setOperationAction(ISD::UREM, MVT::i32, Custom);
125 }
126
127 setOperationAction(ISD::SDIVREM, XLenVT, Expand);
128 setOperationAction(ISD::UDIVREM, XLenVT, Expand);
129 setOperationAction(ISD::SMUL_LOHI, XLenVT, Expand);
130 setOperationAction(ISD::UMUL_LOHI, XLenVT, Expand);
131
132 setOperationAction(ISD::SHL_PARTS, XLenVT, Custom);
133 setOperationAction(ISD::SRL_PARTS, XLenVT, Custom);
134 setOperationAction(ISD::SRA_PARTS, XLenVT, Custom);
135
136 setOperationAction(ISD::ROTL, XLenVT, Expand);
137 setOperationAction(ISD::ROTR, XLenVT, Expand);
138 setOperationAction(ISD::BSWAP, XLenVT, Expand);
139 setOperationAction(ISD::CTTZ, XLenVT, Expand);
140 setOperationAction(ISD::CTLZ, XLenVT, Expand);
141 setOperationAction(ISD::CTPOP, XLenVT, Expand);
142
143 ISD::CondCode FPCCToExtend[] = {
144 ISD::SETOGT, ISD::SETOGE, ISD::SETONE, ISD::SETUEQ, ISD::SETUGT,
145 ISD::SETUGE, ISD::SETULT, ISD::SETULE, ISD::SETUNE, ISD::SETGT,
146 ISD::SETGE, ISD::SETNE};
147
148 ISD::NodeType FPOpToExtend[] = {
149 ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOW, ISD::FREM};
150
151 if (Subtarget.hasStdExtF()) {
152 setOperationAction(ISD::FMINNUM, MVT::f32, Legal);
153 setOperationAction(ISD::FMAXNUM, MVT::f32, Legal);
154 for (auto CC : FPCCToExtend)
155 setCondCodeAction(CC, MVT::f32, Expand);
156 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
157 setOperationAction(ISD::SELECT, MVT::f32, Custom);
158 setOperationAction(ISD::BR_CC, MVT::f32, Expand);
159 for (auto Op : FPOpToExtend)
160 setOperationAction(Op, MVT::f32, Expand);
161 }
162
163 if (Subtarget.hasStdExtF() && Subtarget.is64Bit())
164 setOperationAction(ISD::BITCAST, MVT::i32, Custom);
165
166 if (Subtarget.hasStdExtD()) {
167 setOperationAction(ISD::FMINNUM, MVT::f64, Legal);
168 setOperationAction(ISD::FMAXNUM, MVT::f64, Legal);
169 for (auto CC : FPCCToExtend)
170 setCondCodeAction(CC, MVT::f64, Expand);
171 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
172 setOperationAction(ISD::SELECT, MVT::f64, Custom);
173 setOperationAction(ISD::BR_CC, MVT::f64, Expand);
174 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand);
175 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
176 for (auto Op : FPOpToExtend)
177 setOperationAction(Op, MVT::f64, Expand);
178 }
179
180 setOperationAction(ISD::GlobalAddress, XLenVT, Custom);
181 setOperationAction(ISD::BlockAddress, XLenVT, Custom);
182 setOperationAction(ISD::ConstantPool, XLenVT, Custom);
183
184 setOperationAction(ISD::GlobalTLSAddress, XLenVT, Custom);
185
186 // TODO: On M-mode only targets, the cycle[h] CSR may not be present.
187 // Unfortunately this can't be determined just from the ISA naming string.
188 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64,
189 Subtarget.is64Bit() ? Legal : Custom);
190
191 if (Subtarget.hasStdExtA()) {
192 setMaxAtomicSizeInBitsSupported(Subtarget.getXLen());
193 setMinCmpXchgSizeInBits(32);
194 } else {
195 setMaxAtomicSizeInBitsSupported(0);
196 }
197
198 setBooleanContents(ZeroOrOneBooleanContent);
199
200 // Function alignments.
201 const Align FunctionAlignment(Subtarget.hasStdExtC() ? 2 : 4);
202 setMinFunctionAlignment(FunctionAlignment);
203 setPrefFunctionAlignment(FunctionAlignment);
204
205 // Effectively disable jump table generation.
206 setMinimumJumpTableEntries(INT_MAX2147483647);
207}
208
209EVT RISCVTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,
210 EVT VT) const {
211 if (!VT.isVector())
212 return getPointerTy(DL);
213 return VT.changeVectorElementTypeToInteger();
214}
215
216bool RISCVTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
217 const CallInst &I,
218 MachineFunction &MF,
219 unsigned Intrinsic) const {
220 switch (Intrinsic) {
221 default:
222 return false;
223 case Intrinsic::riscv_masked_atomicrmw_xchg_i32:
224 case Intrinsic::riscv_masked_atomicrmw_add_i32:
225 case Intrinsic::riscv_masked_atomicrmw_sub_i32:
226 case Intrinsic::riscv_masked_atomicrmw_nand_i32:
227 case Intrinsic::riscv_masked_atomicrmw_max_i32:
228 case Intrinsic::riscv_masked_atomicrmw_min_i32:
229 case Intrinsic::riscv_masked_atomicrmw_umax_i32:
230 case Intrinsic::riscv_masked_atomicrmw_umin_i32:
231 case Intrinsic::riscv_masked_cmpxchg_i32:
232 PointerType *PtrTy = cast<PointerType>(I.getArgOperand(0)->getType());
233 Info.opc = ISD::INTRINSIC_W_CHAIN;
234 Info.memVT = MVT::getVT(PtrTy->getElementType());
235 Info.ptrVal = I.getArgOperand(0);
236 Info.offset = 0;
237 Info.align = Align(4);
238 Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore |
239 MachineMemOperand::MOVolatile;
240 return true;
241 }
242}
243
244bool RISCVTargetLowering::isLegalAddressingMode(const DataLayout &DL,
245 const AddrMode &AM, Type *Ty,
246 unsigned AS,
247 Instruction *I) const {
248 // No global is ever allowed as a base.
249 if (AM.BaseGV)
250 return false;
251
252 // Require a 12-bit signed offset.
253 if (!isInt<12>(AM.BaseOffs))
254 return false;
255
256 switch (AM.Scale) {
257 case 0: // "r+i" or just "i", depending on HasBaseReg.
258 break;
259 case 1:
260 if (!AM.HasBaseReg) // allow "r+i".
261 break;
262 return false; // disallow "r+r" or "r+r+i".
263 default:
264 return false;
265 }
266
267 return true;
268}
269
270bool RISCVTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
271 return isInt<12>(Imm);
272}
273
274bool RISCVTargetLowering::isLegalAddImmediate(int64_t Imm) const {
275 return isInt<12>(Imm);
276}
277
278// On RV32, 64-bit integers are split into their high and low parts and held
279// in two different registers, so the trunc is free since the low register can
280// just be used.
281bool RISCVTargetLowering::isTruncateFree(Type *SrcTy, Type *DstTy) const {
282 if (Subtarget.is64Bit() || !SrcTy->isIntegerTy() || !DstTy->isIntegerTy())
283 return false;
284 unsigned SrcBits = SrcTy->getPrimitiveSizeInBits();
285 unsigned DestBits = DstTy->getPrimitiveSizeInBits();
286 return (SrcBits == 64 && DestBits == 32);
287}
288
289bool RISCVTargetLowering::isTruncateFree(EVT SrcVT, EVT DstVT) const {
290 if (Subtarget.is64Bit() || SrcVT.isVector() || DstVT.isVector() ||
291 !SrcVT.isInteger() || !DstVT.isInteger())
292 return false;
293 unsigned SrcBits = SrcVT.getSizeInBits();
294 unsigned DestBits = DstVT.getSizeInBits();
295 return (SrcBits == 64 && DestBits == 32);
296}
297
298bool RISCVTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
299 // Zexts are free if they can be combined with a load.
300 if (auto *LD = dyn_cast<LoadSDNode>(Val)) {
1
Assuming 'LD' is null
2
Taking false branch
301 EVT MemVT = LD->getMemoryVT();
302 if ((MemVT == MVT::i8 || MemVT == MVT::i16 ||
303 (Subtarget.is64Bit() && MemVT == MVT::i32)) &&
304 (LD->getExtensionType() == ISD::NON_EXTLOAD ||
305 LD->getExtensionType() == ISD::ZEXTLOAD))
306 return true;
307 }
308
309 return TargetLowering::isZExtFree(Val, VT2);
3
Value assigned to 'Val.Node'
4
Calling 'TargetLoweringBase::isZExtFree'
310}
311
312bool RISCVTargetLowering::isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const {
313 return Subtarget.is64Bit() && SrcVT == MVT::i32 && DstVT == MVT::i64;
314}
315
316bool RISCVTargetLowering::hasBitPreservingFPLogic(EVT VT) const {
317 return (VT == MVT::f32 && Subtarget.hasStdExtF()) ||
318 (VT == MVT::f64 && Subtarget.hasStdExtD());
319}
320
321// Changes the condition code and swaps operands if necessary, so the SetCC
322// operation matches one of the comparisons supported directly in the RISC-V
323// ISA.
324static void normaliseSetCC(SDValue &LHS, SDValue &RHS, ISD::CondCode &CC) {
325 switch (CC) {
326 default:
327 break;
328 case ISD::SETGT:
329 case ISD::SETLE:
330 case ISD::SETUGT:
331 case ISD::SETULE:
332 CC = ISD::getSetCCSwappedOperands(CC);
333 std::swap(LHS, RHS);
334 break;
335 }
336}
337
338// Return the RISC-V branch opcode that matches the given DAG integer
339// condition code. The CondCode must be one of those supported by the RISC-V
340// ISA (see normaliseSetCC).
341static unsigned getBranchOpcodeForIntCondCode(ISD::CondCode CC) {
342 switch (CC) {
343 default:
344 llvm_unreachable("Unsupported CondCode")::llvm::llvm_unreachable_internal("Unsupported CondCode", "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/RISCV/RISCVISelLowering.cpp"
, 344)
;
345 case ISD::SETEQ:
346 return RISCV::BEQ;
347 case ISD::SETNE:
348 return RISCV::BNE;
349 case ISD::SETLT:
350 return RISCV::BLT;
351 case ISD::SETGE:
352 return RISCV::BGE;
353 case ISD::SETULT:
354 return RISCV::BLTU;
355 case ISD::SETUGE:
356 return RISCV::BGEU;
357 }
358}
359
360SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
361 SelectionDAG &DAG) const {
362 switch (Op.getOpcode()) {
363 default:
364 report_fatal_error("unimplemented operand");
365 case ISD::GlobalAddress:
366 return lowerGlobalAddress(Op, DAG);
367 case ISD::BlockAddress:
368 return lowerBlockAddress(Op, DAG);
369 case ISD::ConstantPool:
370 return lowerConstantPool(Op, DAG);
371 case ISD::GlobalTLSAddress:
372 return lowerGlobalTLSAddress(Op, DAG);
373 case ISD::SELECT:
374 return lowerSELECT(Op, DAG);
375 case ISD::VASTART:
376 return lowerVASTART(Op, DAG);
377 case ISD::FRAMEADDR:
378 return lowerFRAMEADDR(Op, DAG);
379 case ISD::RETURNADDR:
380 return lowerRETURNADDR(Op, DAG);
381 case ISD::SHL_PARTS:
382 return lowerShiftLeftParts(Op, DAG);
383 case ISD::SRA_PARTS:
384 return lowerShiftRightParts(Op, DAG, true);
385 case ISD::SRL_PARTS:
386 return lowerShiftRightParts(Op, DAG, false);
387 case ISD::BITCAST: {
388 assert(Subtarget.is64Bit() && Subtarget.hasStdExtF() &&((Subtarget.is64Bit() && Subtarget.hasStdExtF() &&
"Unexpected custom legalisation") ? static_cast<void> (
0) : __assert_fail ("Subtarget.is64Bit() && Subtarget.hasStdExtF() && \"Unexpected custom legalisation\""
, "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/RISCV/RISCVISelLowering.cpp"
, 389, __PRETTY_FUNCTION__))
389 "Unexpected custom legalisation")((Subtarget.is64Bit() && Subtarget.hasStdExtF() &&
"Unexpected custom legalisation") ? static_cast<void> (
0) : __assert_fail ("Subtarget.is64Bit() && Subtarget.hasStdExtF() && \"Unexpected custom legalisation\""
, "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/RISCV/RISCVISelLowering.cpp"
, 389, __PRETTY_FUNCTION__))
;
390 SDLoc DL(Op);
391 SDValue Op0 = Op.getOperand(0);
392 if (Op.getValueType() != MVT::f32 || Op0.getValueType() != MVT::i32)
393 return SDValue();
394 SDValue NewOp0 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op0);
395 SDValue FPConv = DAG.getNode(RISCVISD::FMV_W_X_RV64, DL, MVT::f32, NewOp0);
396 return FPConv;
397 }
398 }
399}
400
401static SDValue getTargetNode(GlobalAddressSDNode *N, SDLoc DL, EVT Ty,
402 SelectionDAG &DAG, unsigned Flags) {
403 return DAG.getTargetGlobalAddress(N->getGlobal(), DL, Ty, 0, Flags);
404}
405
406static SDValue getTargetNode(BlockAddressSDNode *N, SDLoc DL, EVT Ty,
407 SelectionDAG &DAG, unsigned Flags) {
408 return DAG.getTargetBlockAddress(N->getBlockAddress(), Ty, N->getOffset(),
409 Flags);
410}
411
412static SDValue getTargetNode(ConstantPoolSDNode *N, SDLoc DL, EVT Ty,
413 SelectionDAG &DAG, unsigned Flags) {
414 return DAG.getTargetConstantPool(N->getConstVal(), Ty, N->getAlignment(),
415 N->getOffset(), Flags);
416}
417
418template <class NodeTy>
419SDValue RISCVTargetLowering::getAddr(NodeTy *N, SelectionDAG &DAG,
420 bool IsLocal) const {
421 SDLoc DL(N);
422 EVT Ty = getPointerTy(DAG.getDataLayout());
423
424 if (isPositionIndependent()) {
425 SDValue Addr = getTargetNode(N, DL, Ty, DAG, 0);
426 if (IsLocal)
427 // Use PC-relative addressing to access the symbol. This generates the
428 // pattern (PseudoLLA sym), which expands to (addi (auipc %pcrel_hi(sym))
429 // %pcrel_lo(auipc)).
430 return SDValue(DAG.getMachineNode(RISCV::PseudoLLA, DL, Ty, Addr), 0);
431
432 // Use PC-relative addressing to access the GOT for this symbol, then load
433 // the address from the GOT. This generates the pattern (PseudoLA sym),
434 // which expands to (ld (addi (auipc %got_pcrel_hi(sym)) %pcrel_lo(auipc))).
435 return SDValue(DAG.getMachineNode(RISCV::PseudoLA, DL, Ty, Addr), 0);
436 }
437
438 switch (getTargetMachine().getCodeModel()) {
439 default:
440 report_fatal_error("Unsupported code model for lowering");
441 case CodeModel::Small: {
442 // Generate a sequence for accessing addresses within the first 2 GiB of
443 // address space. This generates the pattern (addi (lui %hi(sym)) %lo(sym)).
444 SDValue AddrHi = getTargetNode(N, DL, Ty, DAG, RISCVII::MO_HI);
445 SDValue AddrLo = getTargetNode(N, DL, Ty, DAG, RISCVII::MO_LO);
446 SDValue MNHi = SDValue(DAG.getMachineNode(RISCV::LUI, DL, Ty, AddrHi), 0);
447 return SDValue(DAG.getMachineNode(RISCV::ADDI, DL, Ty, MNHi, AddrLo), 0);
448 }
449 case CodeModel::Medium: {
450 // Generate a sequence for accessing addresses within any 2GiB range within
451 // the address space. This generates the pattern (PseudoLLA sym), which
452 // expands to (addi (auipc %pcrel_hi(sym)) %pcrel_lo(auipc)).
453 SDValue Addr = getTargetNode(N, DL, Ty, DAG, 0);
454 return SDValue(DAG.getMachineNode(RISCV::PseudoLLA, DL, Ty, Addr), 0);
455 }
456 }
457}
458
459SDValue RISCVTargetLowering::lowerGlobalAddress(SDValue Op,
460 SelectionDAG &DAG) const {
461 SDLoc DL(Op);
462 EVT Ty = Op.getValueType();
463 GlobalAddressSDNode *N = cast<GlobalAddressSDNode>(Op);
464 int64_t Offset = N->getOffset();
465 MVT XLenVT = Subtarget.getXLenVT();
466
467 const GlobalValue *GV = N->getGlobal();
468 bool IsLocal = getTargetMachine().shouldAssumeDSOLocal(*GV->getParent(), GV);
469 SDValue Addr = getAddr(N, DAG, IsLocal);
470
471 // In order to maximise the opportunity for common subexpression elimination,
472 // emit a separate ADD node for the global address offset instead of folding
473 // it in the global address node. Later peephole optimisations may choose to
474 // fold it back in when profitable.
475 if (Offset != 0)
476 return DAG.getNode(ISD::ADD, DL, Ty, Addr,
477 DAG.getConstant(Offset, DL, XLenVT));
478 return Addr;
479}
480
481SDValue RISCVTargetLowering::lowerBlockAddress(SDValue Op,
482 SelectionDAG &DAG) const {
483 BlockAddressSDNode *N = cast<BlockAddressSDNode>(Op);
484
485 return getAddr(N, DAG);
486}
487
488SDValue RISCVTargetLowering::lowerConstantPool(SDValue Op,
489 SelectionDAG &DAG) const {
490 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
491
492 return getAddr(N, DAG);
493}
494
495SDValue RISCVTargetLowering::getStaticTLSAddr(GlobalAddressSDNode *N,
496 SelectionDAG &DAG,
497 bool UseGOT) const {
498 SDLoc DL(N);
499 EVT Ty = getPointerTy(DAG.getDataLayout());
500 const GlobalValue *GV = N->getGlobal();
501 MVT XLenVT = Subtarget.getXLenVT();
502
503 if (UseGOT) {
504 // Use PC-relative addressing to access the GOT for this TLS symbol, then
505 // load the address from the GOT and add the thread pointer. This generates
506 // the pattern (PseudoLA_TLS_IE sym), which expands to
507 // (ld (auipc %tls_ie_pcrel_hi(sym)) %pcrel_lo(auipc)).
508 SDValue Addr = DAG.getTargetGlobalAddress(GV, DL, Ty, 0, 0);
509 SDValue Load =
510 SDValue(DAG.getMachineNode(RISCV::PseudoLA_TLS_IE, DL, Ty, Addr), 0);
511
512 // Add the thread pointer.
513 SDValue TPReg = DAG.getRegister(RISCV::X4, XLenVT);
514 return DAG.getNode(ISD::ADD, DL, Ty, Load, TPReg);
515 }
516
517 // Generate a sequence for accessing the address relative to the thread
518 // pointer, with the appropriate adjustment for the thread pointer offset.
519 // This generates the pattern
520 // (add (add_tprel (lui %tprel_hi(sym)) tp %tprel_add(sym)) %tprel_lo(sym))
521 SDValue AddrHi =
522 DAG.getTargetGlobalAddress(GV, DL, Ty, 0, RISCVII::MO_TPREL_HI);
523 SDValue AddrAdd =
524 DAG.getTargetGlobalAddress(GV, DL, Ty, 0, RISCVII::MO_TPREL_ADD);
525 SDValue AddrLo =
526 DAG.getTargetGlobalAddress(GV, DL, Ty, 0, RISCVII::MO_TPREL_LO);
527
528 SDValue MNHi = SDValue(DAG.getMachineNode(RISCV::LUI, DL, Ty, AddrHi), 0);
529 SDValue TPReg = DAG.getRegister(RISCV::X4, XLenVT);
530 SDValue MNAdd = SDValue(
531 DAG.getMachineNode(RISCV::PseudoAddTPRel, DL, Ty, MNHi, TPReg, AddrAdd),
532 0);
533 return SDValue(DAG.getMachineNode(RISCV::ADDI, DL, Ty, MNAdd, AddrLo), 0);
534}
535
536SDValue RISCVTargetLowering::getDynamicTLSAddr(GlobalAddressSDNode *N,
537 SelectionDAG &DAG) const {
538 SDLoc DL(N);
539 EVT Ty = getPointerTy(DAG.getDataLayout());
540 IntegerType *CallTy = Type::getIntNTy(*DAG.getContext(), Ty.getSizeInBits());
541 const GlobalValue *GV = N->getGlobal();
542
543 // Use a PC-relative addressing mode to access the global dynamic GOT address.
544 // This generates the pattern (PseudoLA_TLS_GD sym), which expands to
545 // (addi (auipc %tls_gd_pcrel_hi(sym)) %pcrel_lo(auipc)).
546 SDValue Addr = DAG.getTargetGlobalAddress(GV, DL, Ty, 0, 0);
547 SDValue Load =
548 SDValue(DAG.getMachineNode(RISCV::PseudoLA_TLS_GD, DL, Ty, Addr), 0);
549
550 // Prepare argument list to generate call.
551 ArgListTy Args;
552 ArgListEntry Entry;
553 Entry.Node = Load;
554 Entry.Ty = CallTy;
555 Args.push_back(Entry);
556
557 // Setup call to __tls_get_addr.
558 TargetLowering::CallLoweringInfo CLI(DAG);
559 CLI.setDebugLoc(DL)
560 .setChain(DAG.getEntryNode())
561 .setLibCallee(CallingConv::C, CallTy,
562 DAG.getExternalSymbol("__tls_get_addr", Ty),
563 std::move(Args));
564
565 return LowerCallTo(CLI).first;
566}
567
568SDValue RISCVTargetLowering::lowerGlobalTLSAddress(SDValue Op,
569 SelectionDAG &DAG) const {
570 SDLoc DL(Op);
571 EVT Ty = Op.getValueType();
572 GlobalAddressSDNode *N = cast<GlobalAddressSDNode>(Op);
573 int64_t Offset = N->getOffset();
574 MVT XLenVT = Subtarget.getXLenVT();
575
576 // Non-PIC TLS lowering should always use the LocalExec model.
577 TLSModel::Model Model = isPositionIndependent()
578 ? getTargetMachine().getTLSModel(N->getGlobal())
579 : TLSModel::LocalExec;
580
581 SDValue Addr;
582 switch (Model) {
583 case TLSModel::LocalExec:
584 Addr = getStaticTLSAddr(N, DAG, /*UseGOT=*/false);
585 break;
586 case TLSModel::InitialExec:
587 Addr = getStaticTLSAddr(N, DAG, /*UseGOT=*/true);
588 break;
589 case TLSModel::LocalDynamic:
590 case TLSModel::GeneralDynamic:
591 Addr = getDynamicTLSAddr(N, DAG);
592 break;
593 }
594
595 // In order to maximise the opportunity for common subexpression elimination,
596 // emit a separate ADD node for the global address offset instead of folding
597 // it in the global address node. Later peephole optimisations may choose to
598 // fold it back in when profitable.
599 if (Offset != 0)
600 return DAG.getNode(ISD::ADD, DL, Ty, Addr,
601 DAG.getConstant(Offset, DL, XLenVT));
602 return Addr;
603}
604
605SDValue RISCVTargetLowering::lowerSELECT(SDValue Op, SelectionDAG &DAG) const {
606 SDValue CondV = Op.getOperand(0);
607 SDValue TrueV = Op.getOperand(1);
608 SDValue FalseV = Op.getOperand(2);
609 SDLoc DL(Op);
610 MVT XLenVT = Subtarget.getXLenVT();
611
612 // If the result type is XLenVT and CondV is the output of a SETCC node
613 // which also operated on XLenVT inputs, then merge the SETCC node into the
614 // lowered RISCVISD::SELECT_CC to take advantage of the integer
615 // compare+branch instructions. i.e.:
616 // (select (setcc lhs, rhs, cc), truev, falsev)
617 // -> (riscvisd::select_cc lhs, rhs, cc, truev, falsev)
618 if (Op.getSimpleValueType() == XLenVT && CondV.getOpcode() == ISD::SETCC &&
619 CondV.getOperand(0).getSimpleValueType() == XLenVT) {
620 SDValue LHS = CondV.getOperand(0);
621 SDValue RHS = CondV.getOperand(1);
622 auto CC = cast<CondCodeSDNode>(CondV.getOperand(2));
623 ISD::CondCode CCVal = CC->get();
624
625 normaliseSetCC(LHS, RHS, CCVal);
626
627 SDValue TargetCC = DAG.getConstant(CCVal, DL, XLenVT);
628 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
629 SDValue Ops[] = {LHS, RHS, TargetCC, TrueV, FalseV};
630 return DAG.getNode(RISCVISD::SELECT_CC, DL, VTs, Ops);
631 }
632
633 // Otherwise:
634 // (select condv, truev, falsev)
635 // -> (riscvisd::select_cc condv, zero, setne, truev, falsev)
636 SDValue Zero = DAG.getConstant(0, DL, XLenVT);
637 SDValue SetNE = DAG.getConstant(ISD::SETNE, DL, XLenVT);
638
639 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
640 SDValue Ops[] = {CondV, Zero, SetNE, TrueV, FalseV};
641
642 return DAG.getNode(RISCVISD::SELECT_CC, DL, VTs, Ops);
643}
644
645SDValue RISCVTargetLowering::lowerVASTART(SDValue Op, SelectionDAG &DAG) const {
646 MachineFunction &MF = DAG.getMachineFunction();
647 RISCVMachineFunctionInfo *FuncInfo = MF.getInfo<RISCVMachineFunctionInfo>();
648
649 SDLoc DL(Op);
650 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
651 getPointerTy(MF.getDataLayout()));
652
653 // vastart just stores the address of the VarArgsFrameIndex slot into the
654 // memory location argument.
655 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
656 return DAG.getStore(Op.getOperand(0), DL, FI, Op.getOperand(1),
657 MachinePointerInfo(SV));
658}
659
660SDValue RISCVTargetLowering::lowerFRAMEADDR(SDValue Op,
661 SelectionDAG &DAG) const {
662 const RISCVRegisterInfo &RI = *Subtarget.getRegisterInfo();
663 MachineFunction &MF = DAG.getMachineFunction();
664 MachineFrameInfo &MFI = MF.getFrameInfo();
665 MFI.setFrameAddressIsTaken(true);
666 Register FrameReg = RI.getFrameRegister(MF);
667 int XLenInBytes = Subtarget.getXLen() / 8;
668
669 EVT VT = Op.getValueType();
670 SDLoc DL(Op);
671 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), DL, FrameReg, VT);
672 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
673 while (Depth--) {
674 int Offset = -(XLenInBytes * 2);
675 SDValue Ptr = DAG.getNode(ISD::ADD, DL, VT, FrameAddr,
676 DAG.getIntPtrConstant(Offset, DL));
677 FrameAddr =
678 DAG.getLoad(VT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo());
679 }
680 return FrameAddr;
681}
682
683SDValue RISCVTargetLowering::lowerRETURNADDR(SDValue Op,
684 SelectionDAG &DAG) const {
685 const RISCVRegisterInfo &RI = *Subtarget.getRegisterInfo();
686 MachineFunction &MF = DAG.getMachineFunction();
687 MachineFrameInfo &MFI = MF.getFrameInfo();
688 MFI.setReturnAddressIsTaken(true);
689 MVT XLenVT = Subtarget.getXLenVT();
690 int XLenInBytes = Subtarget.getXLen() / 8;
691
692 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
693 return SDValue();
694
695 EVT VT = Op.getValueType();
696 SDLoc DL(Op);
697 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
698 if (Depth) {
699 int Off = -XLenInBytes;
700 SDValue FrameAddr = lowerFRAMEADDR(Op, DAG);
701 SDValue Offset = DAG.getConstant(Off, DL, VT);
702 return DAG.getLoad(VT, DL, DAG.getEntryNode(),
703 DAG.getNode(ISD::ADD, DL, VT, FrameAddr, Offset),
704 MachinePointerInfo());
705 }
706
707 // Return the value of the return address register, marking it an implicit
708 // live-in.
709 Register Reg = MF.addLiveIn(RI.getRARegister(), getRegClassFor(XLenVT));
710 return DAG.getCopyFromReg(DAG.getEntryNode(), DL, Reg, XLenVT);
711}
712
713SDValue RISCVTargetLowering::lowerShiftLeftParts(SDValue Op,
714 SelectionDAG &DAG) const {
715 SDLoc DL(Op);
716 SDValue Lo = Op.getOperand(0);
717 SDValue Hi = Op.getOperand(1);
718 SDValue Shamt = Op.getOperand(2);
719 EVT VT = Lo.getValueType();
720
721 // if Shamt-XLEN < 0: // Shamt < XLEN
722 // Lo = Lo << Shamt
723 // Hi = (Hi << Shamt) | ((Lo >>u 1) >>u (XLEN-1 - Shamt))
724 // else:
725 // Lo = 0
726 // Hi = Lo << (Shamt-XLEN)
727
728 SDValue Zero = DAG.getConstant(0, DL, VT);
729 SDValue One = DAG.getConstant(1, DL, VT);
730 SDValue MinusXLen = DAG.getConstant(-(int)Subtarget.getXLen(), DL, VT);
731 SDValue XLenMinus1 = DAG.getConstant(Subtarget.getXLen() - 1, DL, VT);
732 SDValue ShamtMinusXLen = DAG.getNode(ISD::ADD, DL, VT, Shamt, MinusXLen);
733 SDValue XLenMinus1Shamt = DAG.getNode(ISD::SUB, DL, VT, XLenMinus1, Shamt);
734
735 SDValue LoTrue = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt);
736 SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, VT, Lo, One);
737 SDValue ShiftRightLo =
738 DAG.getNode(ISD::SRL, DL, VT, ShiftRight1Lo, XLenMinus1Shamt);
739 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, Hi, Shamt);
740 SDValue HiTrue = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo);
741 SDValue HiFalse = DAG.getNode(ISD::SHL, DL, VT, Lo, ShamtMinusXLen);
742
743 SDValue CC = DAG.getSetCC(DL, VT, ShamtMinusXLen, Zero, ISD::SETLT);
744
745 Lo = DAG.getNode(ISD::SELECT, DL, VT, CC, LoTrue, Zero);
746 Hi = DAG.getNode(ISD::SELECT, DL, VT, CC, HiTrue, HiFalse);
747
748 SDValue Parts[2] = {Lo, Hi};
749 return DAG.getMergeValues(Parts, DL);
750}
751
752SDValue RISCVTargetLowering::lowerShiftRightParts(SDValue Op, SelectionDAG &DAG,
753 bool IsSRA) const {
754 SDLoc DL(Op);
755 SDValue Lo = Op.getOperand(0);
756 SDValue Hi = Op.getOperand(1);
757 SDValue Shamt = Op.getOperand(2);
758 EVT VT = Lo.getValueType();
759
760 // SRA expansion:
761 // if Shamt-XLEN < 0: // Shamt < XLEN
762 // Lo = (Lo >>u Shamt) | ((Hi << 1) << (XLEN-1 - Shamt))
763 // Hi = Hi >>s Shamt
764 // else:
765 // Lo = Hi >>s (Shamt-XLEN);
766 // Hi = Hi >>s (XLEN-1)
767 //
768 // SRL expansion:
769 // if Shamt-XLEN < 0: // Shamt < XLEN
770 // Lo = (Lo >>u Shamt) | ((Hi << 1) << (XLEN-1 - Shamt))
771 // Hi = Hi >>u Shamt
772 // else:
773 // Lo = Hi >>u (Shamt-XLEN);
774 // Hi = 0;
775
776 unsigned ShiftRightOp = IsSRA ? ISD::SRA : ISD::SRL;
777
778 SDValue Zero = DAG.getConstant(0, DL, VT);
779 SDValue One = DAG.getConstant(1, DL, VT);
780 SDValue MinusXLen = DAG.getConstant(-(int)Subtarget.getXLen(), DL, VT);
781 SDValue XLenMinus1 = DAG.getConstant(Subtarget.getXLen() - 1, DL, VT);
782 SDValue ShamtMinusXLen = DAG.getNode(ISD::ADD, DL, VT, Shamt, MinusXLen);
783 SDValue XLenMinus1Shamt = DAG.getNode(ISD::SUB, DL, VT, XLenMinus1, Shamt);
784
785 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, Lo, Shamt);
786 SDValue ShiftLeftHi1 = DAG.getNode(ISD::SHL, DL, VT, Hi, One);
787 SDValue ShiftLeftHi =
788 DAG.getNode(ISD::SHL, DL, VT, ShiftLeftHi1, XLenMinus1Shamt);
789 SDValue LoTrue = DAG.getNode(ISD::OR, DL, VT, ShiftRightLo, ShiftLeftHi);
790 SDValue HiTrue = DAG.getNode(ShiftRightOp, DL, VT, Hi, Shamt);
791 SDValue LoFalse = DAG.getNode(ShiftRightOp, DL, VT, Hi, ShamtMinusXLen);
792 SDValue HiFalse =
793 IsSRA ? DAG.getNode(ISD::SRA, DL, VT, Hi, XLenMinus1) : Zero;
794
795 SDValue CC = DAG.getSetCC(DL, VT, ShamtMinusXLen, Zero, ISD::SETLT);
796
797 Lo = DAG.getNode(ISD::SELECT, DL, VT, CC, LoTrue, LoFalse);
798 Hi = DAG.getNode(ISD::SELECT, DL, VT, CC, HiTrue, HiFalse);
799
800 SDValue Parts[2] = {Lo, Hi};
801 return DAG.getMergeValues(Parts, DL);
802}
803
804// Returns the opcode of the target-specific SDNode that implements the 32-bit
805// form of the given Opcode.
806static RISCVISD::NodeType getRISCVWOpcode(unsigned Opcode) {
807 switch (Opcode) {
808 default:
809 llvm_unreachable("Unexpected opcode")::llvm::llvm_unreachable_internal("Unexpected opcode", "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/RISCV/RISCVISelLowering.cpp"
, 809)
;
810 case ISD::SHL:
811 return RISCVISD::SLLW;
812 case ISD::SRA:
813 return RISCVISD::SRAW;
814 case ISD::SRL:
815 return RISCVISD::SRLW;
816 case ISD::SDIV:
817 return RISCVISD::DIVW;
818 case ISD::UDIV:
819 return RISCVISD::DIVUW;
820 case ISD::UREM:
821 return RISCVISD::REMUW;
822 }
823}
824
825// Converts the given 32-bit operation to a target-specific SelectionDAG node.
826// Because i32 isn't a legal type for RV64, these operations would otherwise
827// be promoted to i64, making it difficult to select the SLLW/DIVUW/.../*W
828// later one because the fact the operation was originally of type i32 is
829// lost.
830static SDValue customLegalizeToWOp(SDNode *N, SelectionDAG &DAG) {
831 SDLoc DL(N);
832 RISCVISD::NodeType WOpcode = getRISCVWOpcode(N->getOpcode());
833 SDValue NewOp0 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(0));
834 SDValue NewOp1 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(1));
835 SDValue NewRes = DAG.getNode(WOpcode, DL, MVT::i64, NewOp0, NewOp1);
836 // ReplaceNodeResults requires we maintain the same type for the return value.
837 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, NewRes);
838}
839
840// Converts the given 32-bit operation to a i64 operation with signed extension
841// semantic to reduce the signed extension instructions.
842static SDValue customLegalizeToWOpWithSExt(SDNode *N, SelectionDAG &DAG) {
843 SDLoc DL(N);
844 SDValue NewOp0 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(0));
845 SDValue NewOp1 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(1));
846 SDValue NewWOp = DAG.getNode(N->getOpcode(), DL, MVT::i64, NewOp0, NewOp1);
847 SDValue NewRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i64, NewWOp,
848 DAG.getValueType(MVT::i32));
849 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, NewRes);
850}
851
852void RISCVTargetLowering::ReplaceNodeResults(SDNode *N,
853 SmallVectorImpl<SDValue> &Results,
854 SelectionDAG &DAG) const {
855 SDLoc DL(N);
856 switch (N->getOpcode()) {
857 default:
858 llvm_unreachable("Don't know how to custom type legalize this operation!")::llvm::llvm_unreachable_internal("Don't know how to custom type legalize this operation!"
, "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/RISCV/RISCVISelLowering.cpp"
, 858)
;
859 case ISD::READCYCLECOUNTER: {
860 assert(!Subtarget.is64Bit() &&((!Subtarget.is64Bit() && "READCYCLECOUNTER only has custom type legalization on riscv32"
) ? static_cast<void> (0) : __assert_fail ("!Subtarget.is64Bit() && \"READCYCLECOUNTER only has custom type legalization on riscv32\""
, "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/RISCV/RISCVISelLowering.cpp"
, 861, __PRETTY_FUNCTION__))
861 "READCYCLECOUNTER only has custom type legalization on riscv32")((!Subtarget.is64Bit() && "READCYCLECOUNTER only has custom type legalization on riscv32"
) ? static_cast<void> (0) : __assert_fail ("!Subtarget.is64Bit() && \"READCYCLECOUNTER only has custom type legalization on riscv32\""
, "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/RISCV/RISCVISelLowering.cpp"
, 861, __PRETTY_FUNCTION__))
;
862
863 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
864 SDValue RCW =
865 DAG.getNode(RISCVISD::READ_CYCLE_WIDE, DL, VTs, N->getOperand(0));
866
867 Results.push_back(RCW);
868 Results.push_back(RCW.getValue(1));
869 Results.push_back(RCW.getValue(2));
870 break;
871 }
872 case ISD::ADD:
873 case ISD::SUB:
874 case ISD::MUL:
875 assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() &&((N->getValueType(0) == MVT::i32 && Subtarget.is64Bit
() && "Unexpected custom legalisation") ? static_cast
<void> (0) : __assert_fail ("N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() && \"Unexpected custom legalisation\""
, "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/RISCV/RISCVISelLowering.cpp"
, 876, __PRETTY_FUNCTION__))
876 "Unexpected custom legalisation")((N->getValueType(0) == MVT::i32 && Subtarget.is64Bit
() && "Unexpected custom legalisation") ? static_cast
<void> (0) : __assert_fail ("N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() && \"Unexpected custom legalisation\""
, "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/RISCV/RISCVISelLowering.cpp"
, 876, __PRETTY_FUNCTION__))
;
877 if (N->getOperand(1).getOpcode() == ISD::Constant)
878 return;
879 Results.push_back(customLegalizeToWOpWithSExt(N, DAG));
880 break;
881 case ISD::SHL:
882 case ISD::SRA:
883 case ISD::SRL:
884 assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() &&((N->getValueType(0) == MVT::i32 && Subtarget.is64Bit
() && "Unexpected custom legalisation") ? static_cast
<void> (0) : __assert_fail ("N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() && \"Unexpected custom legalisation\""
, "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/RISCV/RISCVISelLowering.cpp"
, 885, __PRETTY_FUNCTION__))
885 "Unexpected custom legalisation")((N->getValueType(0) == MVT::i32 && Subtarget.is64Bit
() && "Unexpected custom legalisation") ? static_cast
<void> (0) : __assert_fail ("N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() && \"Unexpected custom legalisation\""
, "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/RISCV/RISCVISelLowering.cpp"
, 885, __PRETTY_FUNCTION__))
;
886 if (N->getOperand(1).getOpcode() == ISD::Constant)
887 return;
888 Results.push_back(customLegalizeToWOp(N, DAG));
889 break;
890 case ISD::SDIV:
891 case ISD::UDIV:
892 case ISD::UREM:
893 assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() &&((N->getValueType(0) == MVT::i32 && Subtarget.is64Bit
() && Subtarget.hasStdExtM() && "Unexpected custom legalisation"
) ? static_cast<void> (0) : __assert_fail ("N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() && Subtarget.hasStdExtM() && \"Unexpected custom legalisation\""
, "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/RISCV/RISCVISelLowering.cpp"
, 894, __PRETTY_FUNCTION__))
894 Subtarget.hasStdExtM() && "Unexpected custom legalisation")((N->getValueType(0) == MVT::i32 && Subtarget.is64Bit
() && Subtarget.hasStdExtM() && "Unexpected custom legalisation"
) ? static_cast<void> (0) : __assert_fail ("N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() && Subtarget.hasStdExtM() && \"Unexpected custom legalisation\""
, "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/RISCV/RISCVISelLowering.cpp"
, 894, __PRETTY_FUNCTION__))
;
895 if (N->getOperand(0).getOpcode() == ISD::Constant ||
896 N->getOperand(1).getOpcode() == ISD::Constant)
897 return;
898 Results.push_back(customLegalizeToWOp(N, DAG));
899 break;
900 case ISD::BITCAST: {
901 assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() &&((N->getValueType(0) == MVT::i32 && Subtarget.is64Bit
() && Subtarget.hasStdExtF() && "Unexpected custom legalisation"
) ? static_cast<void> (0) : __assert_fail ("N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() && Subtarget.hasStdExtF() && \"Unexpected custom legalisation\""
, "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/RISCV/RISCVISelLowering.cpp"
, 902, __PRETTY_FUNCTION__))
902 Subtarget.hasStdExtF() && "Unexpected custom legalisation")((N->getValueType(0) == MVT::i32 && Subtarget.is64Bit
() && Subtarget.hasStdExtF() && "Unexpected custom legalisation"
) ? static_cast<void> (0) : __assert_fail ("N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() && Subtarget.hasStdExtF() && \"Unexpected custom legalisation\""
, "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/RISCV/RISCVISelLowering.cpp"
, 902, __PRETTY_FUNCTION__))
;
903 SDLoc DL(N);
904 SDValue Op0 = N->getOperand(0);
905 if (Op0.getValueType() != MVT::f32)
906 return;
907 SDValue FPConv =
908 DAG.getNode(RISCVISD::FMV_X_ANYEXTW_RV64, DL, MVT::i64, Op0);
909 Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, FPConv));
910 break;
911 }
912 }
913}
914
915SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
916 DAGCombinerInfo &DCI) const {
917 SelectionDAG &DAG = DCI.DAG;
918
919 switch (N->getOpcode()) {
920 default:
921 break;
922 case RISCVISD::SplitF64: {
923 SDValue Op0 = N->getOperand(0);
924 // If the input to SplitF64 is just BuildPairF64 then the operation is
925 // redundant. Instead, use BuildPairF64's operands directly.
926 if (Op0->getOpcode() == RISCVISD::BuildPairF64)
927 return DCI.CombineTo(N, Op0.getOperand(0), Op0.getOperand(1));
928
929 SDLoc DL(N);
930
931 // It's cheaper to materialise two 32-bit integers than to load a double
932 // from the constant pool and transfer it to integer registers through the
933 // stack.
934 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Op0)) {
935 APInt V = C->getValueAPF().bitcastToAPInt();
936 SDValue Lo = DAG.getConstant(V.trunc(32), DL, MVT::i32);
937 SDValue Hi = DAG.getConstant(V.lshr(32).trunc(32), DL, MVT::i32);
938 return DCI.CombineTo(N, Lo, Hi);
939 }
940
941 // This is a target-specific version of a DAGCombine performed in
942 // DAGCombiner::visitBITCAST. It performs the equivalent of:
943 // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit)
944 // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit))
945 if (!(Op0.getOpcode() == ISD::FNEG || Op0.getOpcode() == ISD::FABS) ||
946 !Op0.getNode()->hasOneUse())
947 break;
948 SDValue NewSplitF64 =
949 DAG.getNode(RISCVISD::SplitF64, DL, DAG.getVTList(MVT::i32, MVT::i32),
950 Op0.getOperand(0));
951 SDValue Lo = NewSplitF64.getValue(0);
952 SDValue Hi = NewSplitF64.getValue(1);
953 APInt SignBit = APInt::getSignMask(32);
954 if (Op0.getOpcode() == ISD::FNEG) {
955 SDValue NewHi = DAG.getNode(ISD::XOR, DL, MVT::i32, Hi,
956 DAG.getConstant(SignBit, DL, MVT::i32));
957 return DCI.CombineTo(N, Lo, NewHi);
958 }
959 assert(Op0.getOpcode() == ISD::FABS)((Op0.getOpcode() == ISD::FABS) ? static_cast<void> (0)
: __assert_fail ("Op0.getOpcode() == ISD::FABS", "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/RISCV/RISCVISelLowering.cpp"
, 959, __PRETTY_FUNCTION__))
;
960 SDValue NewHi = DAG.getNode(ISD::AND, DL, MVT::i32, Hi,
961 DAG.getConstant(~SignBit, DL, MVT::i32));
962 return DCI.CombineTo(N, Lo, NewHi);
963 }
964 case RISCVISD::SLLW:
965 case RISCVISD::SRAW:
966 case RISCVISD::SRLW: {
967 // Only the lower 32 bits of LHS and lower 5 bits of RHS are read.
968 SDValue LHS = N->getOperand(0);
969 SDValue RHS = N->getOperand(1);
970 APInt LHSMask = APInt::getLowBitsSet(LHS.getValueSizeInBits(), 32);
971 APInt RHSMask = APInt::getLowBitsSet(RHS.getValueSizeInBits(), 5);
972 if ((SimplifyDemandedBits(N->getOperand(0), LHSMask, DCI)) ||
973 (SimplifyDemandedBits(N->getOperand(1), RHSMask, DCI)))
974 return SDValue();
975 break;
976 }
977 case RISCVISD::FMV_X_ANYEXTW_RV64: {
978 SDLoc DL(N);
979 SDValue Op0 = N->getOperand(0);
980 // If the input to FMV_X_ANYEXTW_RV64 is just FMV_W_X_RV64 then the
981 // conversion is unnecessary and can be replaced with an ANY_EXTEND
982 // of the FMV_W_X_RV64 operand.
983 if (Op0->getOpcode() == RISCVISD::FMV_W_X_RV64) {
984 SDValue AExtOp =
985 DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op0.getOperand(0));
986 return DCI.CombineTo(N, AExtOp);
987 }
988
989 // This is a target-specific version of a DAGCombine performed in
990 // DAGCombiner::visitBITCAST. It performs the equivalent of:
991 // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit)
992 // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit))
993 if (!(Op0.getOpcode() == ISD::FNEG || Op0.getOpcode() == ISD::FABS) ||
994 !Op0.getNode()->hasOneUse())
995 break;
996 SDValue NewFMV = DAG.getNode(RISCVISD::FMV_X_ANYEXTW_RV64, DL, MVT::i64,
997 Op0.getOperand(0));
998 APInt SignBit = APInt::getSignMask(32).sext(64);
999 if (Op0.getOpcode() == ISD::FNEG) {
1000 return DCI.CombineTo(N,
1001 DAG.getNode(ISD::XOR, DL, MVT::i64, NewFMV,
1002 DAG.getConstant(SignBit, DL, MVT::i64)));
1003 }
1004 assert(Op0.getOpcode() == ISD::FABS)((Op0.getOpcode() == ISD::FABS) ? static_cast<void> (0)
: __assert_fail ("Op0.getOpcode() == ISD::FABS", "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/RISCV/RISCVISelLowering.cpp"
, 1004, __PRETTY_FUNCTION__))
;
1005 return DCI.CombineTo(N,
1006 DAG.getNode(ISD::AND, DL, MVT::i64, NewFMV,
1007 DAG.getConstant(~SignBit, DL, MVT::i64)));
1008 }
1009 }
1010
1011 return SDValue();
1012}
1013
1014bool RISCVTargetLowering::isDesirableToCommuteWithShift(
1015 const SDNode *N, CombineLevel Level) const {
1016 // The following folds are only desirable if `(OP _, c1 << c2)` can be
1017 // materialised in fewer instructions than `(OP _, c1)`:
1018 //
1019 // (shl (add x, c1), c2) -> (add (shl x, c2), c1 << c2)
1020 // (shl (or x, c1), c2) -> (or (shl x, c2), c1 << c2)
1021 SDValue N0 = N->getOperand(0);
1022 EVT Ty = N0.getValueType();
1023 if (Ty.isScalarInteger() &&
1024 (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::OR)) {
1025 auto *C1 = dyn_cast<ConstantSDNode>(N0->getOperand(1));
1026 auto *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1));
1027 if (C1 && C2) {
1028 APInt C1Int = C1->getAPIntValue();
1029 APInt ShiftedC1Int = C1Int << C2->getAPIntValue();
1030
1031 // We can materialise `c1 << c2` into an add immediate, so it's "free",
1032 // and the combine should happen, to potentially allow further combines
1033 // later.
1034 if (ShiftedC1Int.getMinSignedBits() <= 64 &&
1035 isLegalAddImmediate(ShiftedC1Int.getSExtValue()))
1036 return true;
1037
1038 // We can materialise `c1` in an add immediate, so it's "free", and the
1039 // combine should be prevented.
1040 if (C1Int.getMinSignedBits() <= 64 &&
1041 isLegalAddImmediate(C1Int.getSExtValue()))
1042 return false;
1043
1044 // Neither constant will fit into an immediate, so find materialisation
1045 // costs.
1046 int C1Cost = RISCVMatInt::getIntMatCost(C1Int, Ty.getSizeInBits(),
1047 Subtarget.is64Bit());
1048 int ShiftedC1Cost = RISCVMatInt::getIntMatCost(
1049 ShiftedC1Int, Ty.getSizeInBits(), Subtarget.is64Bit());
1050
1051 // Materialising `c1` is cheaper than materialising `c1 << c2`, so the
1052 // combine should be prevented.
1053 if (C1Cost < ShiftedC1Cost)
1054 return false;
1055 }
1056 }
1057 return true;
1058}
1059
1060unsigned RISCVTargetLowering::ComputeNumSignBitsForTargetNode(
1061 SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG,
1062 unsigned Depth) const {
1063 switch (Op.getOpcode()) {
1064 default:
1065 break;
1066 case RISCVISD::SLLW:
1067 case RISCVISD::SRAW:
1068 case RISCVISD::SRLW:
1069 case RISCVISD::DIVW:
1070 case RISCVISD::DIVUW:
1071 case RISCVISD::REMUW:
1072 // TODO: As the result is sign-extended, this is conservatively correct. A
1073 // more precise answer could be calculated for SRAW depending on known
1074 // bits in the shift amount.
1075 return 33;
1076 }
1077
1078 return 1;
1079}
1080
1081static MachineBasicBlock *emitReadCycleWidePseudo(MachineInstr &MI,
1082 MachineBasicBlock *BB) {
1083 assert(MI.getOpcode() == RISCV::ReadCycleWide && "Unexpected instruction")((MI.getOpcode() == RISCV::ReadCycleWide && "Unexpected instruction"
) ? static_cast<void> (0) : __assert_fail ("MI.getOpcode() == RISCV::ReadCycleWide && \"Unexpected instruction\""
, "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/RISCV/RISCVISelLowering.cpp"
, 1083, __PRETTY_FUNCTION__))
;
1084
1085 // To read the 64-bit cycle CSR on a 32-bit target, we read the two halves.
1086 // Should the count have wrapped while it was being read, we need to try
1087 // again.
1088 // ...
1089 // read:
1090 // rdcycleh x3 # load high word of cycle
1091 // rdcycle x2 # load low word of cycle
1092 // rdcycleh x4 # load high word of cycle
1093 // bne x3, x4, read # check if high word reads match, otherwise try again
1094 // ...
1095
1096 MachineFunction &MF = *BB->getParent();
1097 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1098 MachineFunction::iterator It = ++BB->getIterator();
1099
1100 MachineBasicBlock *LoopMBB = MF.CreateMachineBasicBlock(LLVM_BB);
1101 MF.insert(It, LoopMBB);
1102
1103 MachineBasicBlock *DoneMBB = MF.CreateMachineBasicBlock(LLVM_BB);
1104 MF.insert(It, DoneMBB);
1105
1106 // Transfer the remainder of BB and its successor edges to DoneMBB.
1107 DoneMBB->splice(DoneMBB->begin(), BB,
1108 std::next(MachineBasicBlock::iterator(MI)), BB->end());
1109 DoneMBB->transferSuccessorsAndUpdatePHIs(BB);
1110
1111 BB->addSuccessor(LoopMBB);
1112
1113 MachineRegisterInfo &RegInfo = MF.getRegInfo();
1114 Register ReadAgainReg = RegInfo.createVirtualRegister(&RISCV::GPRRegClass);
1115 Register LoReg = MI.getOperand(0).getReg();
1116 Register HiReg = MI.getOperand(1).getReg();
1117 DebugLoc DL = MI.getDebugLoc();
1118
1119 const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
1120 BuildMI(LoopMBB, DL, TII->get(RISCV::CSRRS), HiReg)
1121 .addImm(RISCVSysReg::lookupSysRegByName("CYCLEH")->Encoding)
1122 .addReg(RISCV::X0);
1123 BuildMI(LoopMBB, DL, TII->get(RISCV::CSRRS), LoReg)
1124 .addImm(RISCVSysReg::lookupSysRegByName("CYCLE")->Encoding)
1125 .addReg(RISCV::X0);
1126 BuildMI(LoopMBB, DL, TII->get(RISCV::CSRRS), ReadAgainReg)
1127 .addImm(RISCVSysReg::lookupSysRegByName("CYCLEH")->Encoding)
1128 .addReg(RISCV::X0);
1129
1130 BuildMI(LoopMBB, DL, TII->get(RISCV::BNE))
1131 .addReg(HiReg)
1132 .addReg(ReadAgainReg)
1133 .addMBB(LoopMBB);
1134
1135 LoopMBB->addSuccessor(LoopMBB);
1136 LoopMBB->addSuccessor(DoneMBB);
1137
1138 MI.eraseFromParent();
1139
1140 return DoneMBB;
1141}
1142
1143static MachineBasicBlock *emitSplitF64Pseudo(MachineInstr &MI,
1144 MachineBasicBlock *BB) {
1145 assert(MI.getOpcode() == RISCV::SplitF64Pseudo && "Unexpected instruction")((MI.getOpcode() == RISCV::SplitF64Pseudo && "Unexpected instruction"
) ? static_cast<void> (0) : __assert_fail ("MI.getOpcode() == RISCV::SplitF64Pseudo && \"Unexpected instruction\""
, "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/RISCV/RISCVISelLowering.cpp"
, 1145, __PRETTY_FUNCTION__))
;
1146
1147 MachineFunction &MF = *BB->getParent();
1148 DebugLoc DL = MI.getDebugLoc();
1149 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
1150 const TargetRegisterInfo *RI = MF.getSubtarget().getRegisterInfo();
1151 Register LoReg = MI.getOperand(0).getReg();
1152 Register HiReg = MI.getOperand(1).getReg();
1153 Register SrcReg = MI.getOperand(2).getReg();
1154 const TargetRegisterClass *SrcRC = &RISCV::FPR64RegClass;
1155 int FI = MF.getInfo<RISCVMachineFunctionInfo>()->getMoveF64FrameIndex();
1156
1157 TII.storeRegToStackSlot(*BB, MI, SrcReg, MI.getOperand(2).isKill(), FI, SrcRC,
1158 RI);
1159 MachineMemOperand *MMO =
1160 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, FI),
1161 MachineMemOperand::MOLoad, 8, 8);
1162 BuildMI(*BB, MI, DL, TII.get(RISCV::LW), LoReg)
1163 .addFrameIndex(FI)
1164 .addImm(0)
1165 .addMemOperand(MMO);
1166 BuildMI(*BB, MI, DL, TII.get(RISCV::LW), HiReg)
1167 .addFrameIndex(FI)
1168 .addImm(4)
1169 .addMemOperand(MMO);
1170 MI.eraseFromParent(); // The pseudo instruction is gone now.
1171 return BB;
1172}
1173
1174static MachineBasicBlock *emitBuildPairF64Pseudo(MachineInstr &MI,
1175 MachineBasicBlock *BB) {
1176 assert(MI.getOpcode() == RISCV::BuildPairF64Pseudo &&((MI.getOpcode() == RISCV::BuildPairF64Pseudo && "Unexpected instruction"
) ? static_cast<void> (0) : __assert_fail ("MI.getOpcode() == RISCV::BuildPairF64Pseudo && \"Unexpected instruction\""
, "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/RISCV/RISCVISelLowering.cpp"
, 1177, __PRETTY_FUNCTION__))
1177 "Unexpected instruction")((MI.getOpcode() == RISCV::BuildPairF64Pseudo && "Unexpected instruction"
) ? static_cast<void> (0) : __assert_fail ("MI.getOpcode() == RISCV::BuildPairF64Pseudo && \"Unexpected instruction\""
, "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/RISCV/RISCVISelLowering.cpp"
, 1177, __PRETTY_FUNCTION__))
;
1178
1179 MachineFunction &MF = *BB->getParent();
1180 DebugLoc DL = MI.getDebugLoc();
1181 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
1182 const TargetRegisterInfo *RI = MF.getSubtarget().getRegisterInfo();
1183 Register DstReg = MI.getOperand(0).getReg();
1184 Register LoReg = MI.getOperand(1).getReg();
1185 Register HiReg = MI.getOperand(2).getReg();
1186 const TargetRegisterClass *DstRC = &RISCV::FPR64RegClass;
1187 int FI = MF.getInfo<RISCVMachineFunctionInfo>()->getMoveF64FrameIndex();
1188
1189 MachineMemOperand *MMO =
1190 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, FI),
1191 MachineMemOperand::MOStore, 8, 8);
1192 BuildMI(*BB, MI, DL, TII.get(RISCV::SW))
1193 .addReg(LoReg, getKillRegState(MI.getOperand(1).isKill()))
1194 .addFrameIndex(FI)
1195 .addImm(0)
1196 .addMemOperand(MMO);
1197 BuildMI(*BB, MI, DL, TII.get(RISCV::SW))
1198 .addReg(HiReg, getKillRegState(MI.getOperand(2).isKill()))
1199 .addFrameIndex(FI)
1200 .addImm(4)
1201 .addMemOperand(MMO);
1202 TII.loadRegFromStackSlot(*BB, MI, DstReg, FI, DstRC, RI);
1203 MI.eraseFromParent(); // The pseudo instruction is gone now.
1204 return BB;
1205}
1206
1207static bool isSelectPseudo(MachineInstr &MI) {
1208 switch (MI.getOpcode()) {
1209 default:
1210 return false;
1211 case RISCV::Select_GPR_Using_CC_GPR:
1212 case RISCV::Select_FPR32_Using_CC_GPR:
1213 case RISCV::Select_FPR64_Using_CC_GPR:
1214 return true;
1215 }
1216}
1217
1218static MachineBasicBlock *emitSelectPseudo(MachineInstr &MI,
1219 MachineBasicBlock *BB) {
1220 // To "insert" Select_* instructions, we actually have to insert the triangle
1221 // control-flow pattern. The incoming instructions know the destination vreg
1222 // to set, the condition code register to branch on, the true/false values to
1223 // select between, and the condcode to use to select the appropriate branch.
1224 //
1225 // We produce the following control flow:
1226 // HeadMBB
1227 // | \
1228 // | IfFalseMBB
1229 // | /
1230 // TailMBB
1231 //
1232 // When we find a sequence of selects we attempt to optimize their emission
1233 // by sharing the control flow. Currently we only handle cases where we have
1234 // multiple selects with the exact same condition (same LHS, RHS and CC).
1235 // The selects may be interleaved with other instructions if the other
1236 // instructions meet some requirements we deem safe:
1237 // - They are debug instructions. Otherwise,
1238 // - They do not have side-effects, do not access memory and their inputs do
1239 // not depend on the results of the select pseudo-instructions.
1240 // The TrueV/FalseV operands of the selects cannot depend on the result of
1241 // previous selects in the sequence.
1242 // These conditions could be further relaxed. See the X86 target for a
1243 // related approach and more information.
1244 Register LHS = MI.getOperand(1).getReg();
1245 Register RHS = MI.getOperand(2).getReg();
1246 auto CC = static_cast<ISD::CondCode>(MI.getOperand(3).getImm());
1247
1248 SmallVector<MachineInstr *, 4> SelectDebugValues;
1249 SmallSet<Register, 4> SelectDests;
1250 SelectDests.insert(MI.getOperand(0).getReg());
1251
1252 MachineInstr *LastSelectPseudo = &MI;
1253
1254 for (auto E = BB->end(), SequenceMBBI = MachineBasicBlock::iterator(MI);
1255 SequenceMBBI != E; ++SequenceMBBI) {
1256 if (SequenceMBBI->isDebugInstr())
1257 continue;
1258 else if (isSelectPseudo(*SequenceMBBI)) {
1259 if (SequenceMBBI->getOperand(1).getReg() != LHS ||
1260 SequenceMBBI->getOperand(2).getReg() != RHS ||
1261 SequenceMBBI->getOperand(3).getImm() != CC ||
1262 SelectDests.count(SequenceMBBI->getOperand(4).getReg()) ||
1263 SelectDests.count(SequenceMBBI->getOperand(5).getReg()))
1264 break;
1265 LastSelectPseudo = &*SequenceMBBI;
1266 SequenceMBBI->collectDebugValues(SelectDebugValues);
1267 SelectDests.insert(SequenceMBBI->getOperand(0).getReg());
1268 } else {
1269 if (SequenceMBBI->hasUnmodeledSideEffects() ||
1270 SequenceMBBI->mayLoadOrStore())
1271 break;
1272 if (llvm::any_of(SequenceMBBI->operands(), [&](MachineOperand &MO) {
1273 return MO.isReg() && MO.isUse() && SelectDests.count(MO.getReg());
1274 }))
1275 break;
1276 }
1277 }
1278
1279 const TargetInstrInfo &TII = *BB->getParent()->getSubtarget().getInstrInfo();
1280 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1281 DebugLoc DL = MI.getDebugLoc();
1282 MachineFunction::iterator I = ++BB->getIterator();
1283
1284 MachineBasicBlock *HeadMBB = BB;
1285 MachineFunction *F = BB->getParent();
1286 MachineBasicBlock *TailMBB = F->CreateMachineBasicBlock(LLVM_BB);
1287 MachineBasicBlock *IfFalseMBB = F->CreateMachineBasicBlock(LLVM_BB);
1288
1289 F->insert(I, IfFalseMBB);
1290 F->insert(I, TailMBB);
1291
1292 // Transfer debug instructions associated with the selects to TailMBB.
1293 for (MachineInstr *DebugInstr : SelectDebugValues) {
1294 TailMBB->push_back(DebugInstr->removeFromParent());
1295 }
1296
1297 // Move all instructions after the sequence to TailMBB.
1298 TailMBB->splice(TailMBB->end(), HeadMBB,
1299 std::next(LastSelectPseudo->getIterator()), HeadMBB->end());
1300 // Update machine-CFG edges by transferring all successors of the current
1301 // block to the new block which will contain the Phi nodes for the selects.
1302 TailMBB->transferSuccessorsAndUpdatePHIs(HeadMBB);
1303 // Set the successors for HeadMBB.
1304 HeadMBB->addSuccessor(IfFalseMBB);
1305 HeadMBB->addSuccessor(TailMBB);
1306
1307 // Insert appropriate branch.
1308 unsigned Opcode = getBranchOpcodeForIntCondCode(CC);
1309
1310 BuildMI(HeadMBB, DL, TII.get(Opcode))
1311 .addReg(LHS)
1312 .addReg(RHS)
1313 .addMBB(TailMBB);
1314
1315 // IfFalseMBB just falls through to TailMBB.
1316 IfFalseMBB->addSuccessor(TailMBB);
1317
1318 // Create PHIs for all of the select pseudo-instructions.
1319 auto SelectMBBI = MI.getIterator();
1320 auto SelectEnd = std::next(LastSelectPseudo->getIterator());
1321 auto InsertionPoint = TailMBB->begin();
1322 while (SelectMBBI != SelectEnd) {
1323 auto Next = std::next(SelectMBBI);
1324 if (isSelectPseudo(*SelectMBBI)) {
1325 // %Result = phi [ %TrueValue, HeadMBB ], [ %FalseValue, IfFalseMBB ]
1326 BuildMI(*TailMBB, InsertionPoint, SelectMBBI->getDebugLoc(),
1327 TII.get(RISCV::PHI), SelectMBBI->getOperand(0).getReg())
1328 .addReg(SelectMBBI->getOperand(4).getReg())
1329 .addMBB(HeadMBB)
1330 .addReg(SelectMBBI->getOperand(5).getReg())
1331 .addMBB(IfFalseMBB);
1332 SelectMBBI->eraseFromParent();
1333 }
1334 SelectMBBI = Next;
1335 }
1336
1337 F->getProperties().reset(MachineFunctionProperties::Property::NoPHIs);
1338 return TailMBB;
1339}
1340
1341MachineBasicBlock *
1342RISCVTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
1343 MachineBasicBlock *BB) const {
1344 switch (MI.getOpcode()) {
1345 default:
1346 llvm_unreachable("Unexpected instr type to insert")::llvm::llvm_unreachable_internal("Unexpected instr type to insert"
, "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/RISCV/RISCVISelLowering.cpp"
, 1346)
;
1347 case RISCV::ReadCycleWide:
1348 assert(!Subtarget.is64Bit() &&((!Subtarget.is64Bit() && "ReadCycleWrite is only to be used on riscv32"
) ? static_cast<void> (0) : __assert_fail ("!Subtarget.is64Bit() && \"ReadCycleWrite is only to be used on riscv32\""
, "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/RISCV/RISCVISelLowering.cpp"
, 1349, __PRETTY_FUNCTION__))
1349 "ReadCycleWrite is only to be used on riscv32")((!Subtarget.is64Bit() && "ReadCycleWrite is only to be used on riscv32"
) ? static_cast<void> (0) : __assert_fail ("!Subtarget.is64Bit() && \"ReadCycleWrite is only to be used on riscv32\""
, "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/RISCV/RISCVISelLowering.cpp"
, 1349, __PRETTY_FUNCTION__))
;
1350 return emitReadCycleWidePseudo(MI, BB);
1351 case RISCV::Select_GPR_Using_CC_GPR:
1352 case RISCV::Select_FPR32_Using_CC_GPR:
1353 case RISCV::Select_FPR64_Using_CC_GPR:
1354 return emitSelectPseudo(MI, BB);
1355 case RISCV::BuildPairF64Pseudo:
1356 return emitBuildPairF64Pseudo(MI, BB);
1357 case RISCV::SplitF64Pseudo:
1358 return emitSplitF64Pseudo(MI, BB);
1359 }
1360}
1361
1362// Calling Convention Implementation.
1363// The expectations for frontend ABI lowering vary from target to target.
1364// Ideally, an LLVM frontend would be able to avoid worrying about many ABI
1365// details, but this is a longer term goal. For now, we simply try to keep the
1366// role of the frontend as simple and well-defined as possible. The rules can
1367// be summarised as:
1368// * Never split up large scalar arguments. We handle them here.
1369// * If a hardfloat calling convention is being used, and the struct may be
1370// passed in a pair of registers (fp+fp, int+fp), and both registers are
1371// available, then pass as two separate arguments. If either the GPRs or FPRs
1372// are exhausted, then pass according to the rule below.
1373// * If a struct could never be passed in registers or directly in a stack
1374// slot (as it is larger than 2*XLEN and the floating point rules don't
1375// apply), then pass it using a pointer with the byval attribute.
1376// * If a struct is less than 2*XLEN, then coerce to either a two-element
1377// word-sized array or a 2*XLEN scalar (depending on alignment).
1378// * The frontend can determine whether a struct is returned by reference or
1379// not based on its size and fields. If it will be returned by reference, the
1380// frontend must modify the prototype so a pointer with the sret annotation is
1381// passed as the first argument. This is not necessary for large scalar
1382// returns.
1383// * Struct return values and varargs should be coerced to structs containing
1384// register-size fields in the same situations they would be for fixed
1385// arguments.
1386
1387static const MCPhysReg ArgGPRs[] = {
1388 RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13,
1389 RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17
1390};
1391static const MCPhysReg ArgFPR32s[] = {
1392 RISCV::F10_F, RISCV::F11_F, RISCV::F12_F, RISCV::F13_F,
1393 RISCV::F14_F, RISCV::F15_F, RISCV::F16_F, RISCV::F17_F
1394};
1395static const MCPhysReg ArgFPR64s[] = {
1396 RISCV::F10_D, RISCV::F11_D, RISCV::F12_D, RISCV::F13_D,
1397 RISCV::F14_D, RISCV::F15_D, RISCV::F16_D, RISCV::F17_D
1398};
1399
1400// Pass a 2*XLEN argument that has been split into two XLEN values through
1401// registers or the stack as necessary.
1402static bool CC_RISCVAssign2XLen(unsigned XLen, CCState &State, CCValAssign VA1,
1403 ISD::ArgFlagsTy ArgFlags1, unsigned ValNo2,
1404 MVT ValVT2, MVT LocVT2,
1405 ISD::ArgFlagsTy ArgFlags2) {
1406 unsigned XLenInBytes = XLen / 8;
1407 if (Register Reg = State.AllocateReg(ArgGPRs)) {
1408 // At least one half can be passed via register.
1409 State.addLoc(CCValAssign::getReg(VA1.getValNo(), VA1.getValVT(), Reg,
1410 VA1.getLocVT(), CCValAssign::Full));
1411 } else {
1412 // Both halves must be passed on the stack, with proper alignment.
1413 unsigned StackAlign = std::max(XLenInBytes, ArgFlags1.getOrigAlign());
1414 State.addLoc(
1415 CCValAssign::getMem(VA1.getValNo(), VA1.getValVT(),
1416 State.AllocateStack(XLenInBytes, StackAlign),
1417 VA1.getLocVT(), CCValAssign::Full));
1418 State.addLoc(CCValAssign::getMem(
1419 ValNo2, ValVT2, State.AllocateStack(XLenInBytes, XLenInBytes), LocVT2,
1420 CCValAssign::Full));
1421 return false;
1422 }
1423
1424 if (Register Reg = State.AllocateReg(ArgGPRs)) {
1425 // The second half can also be passed via register.
1426 State.addLoc(
1427 CCValAssign::getReg(ValNo2, ValVT2, Reg, LocVT2, CCValAssign::Full));
1428 } else {
1429 // The second half is passed via the stack, without additional alignment.
1430 State.addLoc(CCValAssign::getMem(
1431 ValNo2, ValVT2, State.AllocateStack(XLenInBytes, XLenInBytes), LocVT2,
1432 CCValAssign::Full));
1433 }
1434
1435 return false;
1436}
1437
1438// Implements the RISC-V calling convention. Returns true upon failure.
1439static bool CC_RISCV(const DataLayout &DL, RISCVABI::ABI ABI, unsigned ValNo,
1440 MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo,
1441 ISD::ArgFlagsTy ArgFlags, CCState &State, bool IsFixed,
1442 bool IsRet, Type *OrigTy) {
1443 unsigned XLen = DL.getLargestLegalIntTypeSizeInBits();
1444 assert(XLen == 32 || XLen == 64)((XLen == 32 || XLen == 64) ? static_cast<void> (0) : __assert_fail
("XLen == 32 || XLen == 64", "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/RISCV/RISCVISelLowering.cpp"
, 1444, __PRETTY_FUNCTION__))
;
1445 MVT XLenVT = XLen == 32 ? MVT::i32 : MVT::i64;
1446
1447 // Any return value split in to more than two values can't be returned
1448 // directly.
1449 if (IsRet && ValNo > 1)
1450 return true;
1451
1452 // UseGPRForF32 if targeting one of the soft-float ABIs, if passing a
1453 // variadic argument, or if no F32 argument registers are available.
1454 bool UseGPRForF32 = true;
1455 // UseGPRForF64 if targeting soft-float ABIs or an FLEN=32 ABI, if passing a
1456 // variadic argument, or if no F64 argument registers are available.
1457 bool UseGPRForF64 = true;
1458
1459 switch (ABI) {
1460 default:
1461 llvm_unreachable("Unexpected ABI")::llvm::llvm_unreachable_internal("Unexpected ABI", "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/RISCV/RISCVISelLowering.cpp"
, 1461)
;
1462 case RISCVABI::ABI_ILP32:
1463 case RISCVABI::ABI_LP64:
1464 break;
1465 case RISCVABI::ABI_ILP32F:
1466 case RISCVABI::ABI_LP64F:
1467 UseGPRForF32 = !IsFixed;
1468 break;
1469 case RISCVABI::ABI_ILP32D:
1470 case RISCVABI::ABI_LP64D:
1471 UseGPRForF32 = !IsFixed;
1472 UseGPRForF64 = !IsFixed;
1473 break;
1474 }
1475
1476 if (State.getFirstUnallocated(ArgFPR32s) == array_lengthof(ArgFPR32s))
1477 UseGPRForF32 = true;
1478 if (State.getFirstUnallocated(ArgFPR64s) == array_lengthof(ArgFPR64s))
1479 UseGPRForF64 = true;
1480
1481 // From this point on, rely on UseGPRForF32, UseGPRForF64 and similar local
1482 // variables rather than directly checking against the target ABI.
1483
1484 if (UseGPRForF32 && ValVT == MVT::f32) {
1485 LocVT = XLenVT;
1486 LocInfo = CCValAssign::BCvt;
1487 } else if (UseGPRForF64 && XLen == 64 && ValVT == MVT::f64) {
1488 LocVT = MVT::i64;
1489 LocInfo = CCValAssign::BCvt;
1490 }
1491
1492 // If this is a variadic argument, the RISC-V calling convention requires
1493 // that it is assigned an 'even' or 'aligned' register if it has 8-byte
1494 // alignment (RV32) or 16-byte alignment (RV64). An aligned register should
1495 // be used regardless of whether the original argument was split during
1496 // legalisation or not. The argument will not be passed by registers if the
1497 // original type is larger than 2*XLEN, so the register alignment rule does
1498 // not apply.
1499 unsigned TwoXLenInBytes = (2 * XLen) / 8;
1500 if (!IsFixed && ArgFlags.getOrigAlign() == TwoXLenInBytes &&
1501 DL.getTypeAllocSize(OrigTy) == TwoXLenInBytes) {
1502 unsigned RegIdx = State.getFirstUnallocated(ArgGPRs);
1503 // Skip 'odd' register if necessary.
1504 if (RegIdx != array_lengthof(ArgGPRs) && RegIdx % 2 == 1)
1505 State.AllocateReg(ArgGPRs);
1506 }
1507
1508 SmallVectorImpl<CCValAssign> &PendingLocs = State.getPendingLocs();
1509 SmallVectorImpl<ISD::ArgFlagsTy> &PendingArgFlags =
1510 State.getPendingArgFlags();
1511
1512 assert(PendingLocs.size() == PendingArgFlags.size() &&((PendingLocs.size() == PendingArgFlags.size() && "PendingLocs and PendingArgFlags out of sync"
) ? static_cast<void> (0) : __assert_fail ("PendingLocs.size() == PendingArgFlags.size() && \"PendingLocs and PendingArgFlags out of sync\""
, "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/RISCV/RISCVISelLowering.cpp"
, 1513, __PRETTY_FUNCTION__))
1513 "PendingLocs and PendingArgFlags out of sync")((PendingLocs.size() == PendingArgFlags.size() && "PendingLocs and PendingArgFlags out of sync"
) ? static_cast<void> (0) : __assert_fail ("PendingLocs.size() == PendingArgFlags.size() && \"PendingLocs and PendingArgFlags out of sync\""
, "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/RISCV/RISCVISelLowering.cpp"
, 1513, __PRETTY_FUNCTION__))
;
1514
1515 // Handle passing f64 on RV32D with a soft float ABI or when floating point
1516 // registers are exhausted.
1517 if (UseGPRForF64 && XLen == 32 && ValVT == MVT::f64) {
1518 assert(!ArgFlags.isSplit() && PendingLocs.empty() &&((!ArgFlags.isSplit() && PendingLocs.empty() &&
"Can't lower f64 if it is split") ? static_cast<void> (
0) : __assert_fail ("!ArgFlags.isSplit() && PendingLocs.empty() && \"Can't lower f64 if it is split\""
, "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/RISCV/RISCVISelLowering.cpp"
, 1519, __PRETTY_FUNCTION__))
1519 "Can't lower f64 if it is split")((!ArgFlags.isSplit() && PendingLocs.empty() &&
"Can't lower f64 if it is split") ? static_cast<void> (
0) : __assert_fail ("!ArgFlags.isSplit() && PendingLocs.empty() && \"Can't lower f64 if it is split\""
, "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/RISCV/RISCVISelLowering.cpp"
, 1519, __PRETTY_FUNCTION__))
;
1520 // Depending on available argument GPRS, f64 may be passed in a pair of
1521 // GPRs, split between a GPR and the stack, or passed completely on the
1522 // stack. LowerCall/LowerFormalArguments/LowerReturn must recognise these
1523 // cases.
1524 Register Reg = State.AllocateReg(ArgGPRs);
1525 LocVT = MVT::i32;
1526 if (!Reg) {
1527 unsigned StackOffset = State.AllocateStack(8, 8);
1528 State.addLoc(
1529 CCValAssign::getMem(ValNo, ValVT, StackOffset, LocVT, LocInfo));
1530 return false;
1531 }
1532 if (!State.AllocateReg(ArgGPRs))
1533 State.AllocateStack(4, 4);
1534 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1535 return false;
1536 }
1537
1538 // Split arguments might be passed indirectly, so keep track of the pending
1539 // values.
1540 if (ArgFlags.isSplit() || !PendingLocs.empty()) {
1541 LocVT = XLenVT;
1542 LocInfo = CCValAssign::Indirect;
1543 PendingLocs.push_back(
1544 CCValAssign::getPending(ValNo, ValVT, LocVT, LocInfo));
1545 PendingArgFlags.push_back(ArgFlags);
1546 if (!ArgFlags.isSplitEnd()) {
1547 return false;
1548 }
1549 }
1550
1551 // If the split argument only had two elements, it should be passed directly
1552 // in registers or on the stack.
1553 if (ArgFlags.isSplitEnd() && PendingLocs.size() <= 2) {
1554 assert(PendingLocs.size() == 2 && "Unexpected PendingLocs.size()")((PendingLocs.size() == 2 && "Unexpected PendingLocs.size()"
) ? static_cast<void> (0) : __assert_fail ("PendingLocs.size() == 2 && \"Unexpected PendingLocs.size()\""
, "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/RISCV/RISCVISelLowering.cpp"
, 1554, __PRETTY_FUNCTION__))
;
1555 // Apply the normal calling convention rules to the first half of the
1556 // split argument.
1557 CCValAssign VA = PendingLocs[0];
1558 ISD::ArgFlagsTy AF = PendingArgFlags[0];
1559 PendingLocs.clear();
1560 PendingArgFlags.clear();
1561 return CC_RISCVAssign2XLen(XLen, State, VA, AF, ValNo, ValVT, LocVT,
1562 ArgFlags);
1563 }
1564
1565 // Allocate to a register if possible, or else a stack slot.
1566 Register Reg;
1567 if (ValVT == MVT::f32 && !UseGPRForF32)
1568 Reg = State.AllocateReg(ArgFPR32s, ArgFPR64s);
1569 else if (ValVT == MVT::f64 && !UseGPRForF64)
1570 Reg = State.AllocateReg(ArgFPR64s, ArgFPR32s);
1571 else
1572 Reg = State.AllocateReg(ArgGPRs);
1573 unsigned StackOffset = Reg ? 0 : State.AllocateStack(XLen / 8, XLen / 8);
1574
1575 // If we reach this point and PendingLocs is non-empty, we must be at the
1576 // end of a split argument that must be passed indirectly.
1577 if (!PendingLocs.empty()) {
1578 assert(ArgFlags.isSplitEnd() && "Expected ArgFlags.isSplitEnd()")((ArgFlags.isSplitEnd() && "Expected ArgFlags.isSplitEnd()"
) ? static_cast<void> (0) : __assert_fail ("ArgFlags.isSplitEnd() && \"Expected ArgFlags.isSplitEnd()\""
, "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/RISCV/RISCVISelLowering.cpp"
, 1578, __PRETTY_FUNCTION__))
;
1579 assert(PendingLocs.size() > 2 && "Unexpected PendingLocs.size()")((PendingLocs.size() > 2 && "Unexpected PendingLocs.size()"
) ? static_cast<void> (0) : __assert_fail ("PendingLocs.size() > 2 && \"Unexpected PendingLocs.size()\""
, "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/RISCV/RISCVISelLowering.cpp"
, 1579, __PRETTY_FUNCTION__))
;
1580
1581 for (auto &It : PendingLocs) {
1582 if (Reg)
1583 It.convertToReg(Reg);
1584 else
1585 It.convertToMem(StackOffset);
1586 State.addLoc(It);
1587 }
1588 PendingLocs.clear();
1589 PendingArgFlags.clear();
1590 return false;
1591 }
1592
1593 assert((!UseGPRForF32 || !UseGPRForF64 || LocVT == XLenVT) &&(((!UseGPRForF32 || !UseGPRForF64 || LocVT == XLenVT) &&
"Expected an XLenVT at this stage") ? static_cast<void>
(0) : __assert_fail ("(!UseGPRForF32 || !UseGPRForF64 || LocVT == XLenVT) && \"Expected an XLenVT at this stage\""
, "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/RISCV/RISCVISelLowering.cpp"
, 1594, __PRETTY_FUNCTION__))
1594 "Expected an XLenVT at this stage")(((!UseGPRForF32 || !UseGPRForF64 || LocVT == XLenVT) &&
"Expected an XLenVT at this stage") ? static_cast<void>
(0) : __assert_fail ("(!UseGPRForF32 || !UseGPRForF64 || LocVT == XLenVT) && \"Expected an XLenVT at this stage\""
, "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/RISCV/RISCVISelLowering.cpp"
, 1594, __PRETTY_FUNCTION__))
;
1595
1596 if (Reg) {
1597 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1598 return false;
1599 }
1600
1601 // When an f32 or f64 is passed on the stack, no bit-conversion is needed.
1602 if (ValVT == MVT::f32 || ValVT == MVT::f64) {
1603 LocVT = ValVT;
1604 LocInfo = CCValAssign::Full;
1605 }
1606 State.addLoc(CCValAssign::getMem(ValNo, ValVT, StackOffset, LocVT, LocInfo));
1607 return false;
1608}
1609
1610void RISCVTargetLowering::analyzeInputArgs(
1611 MachineFunction &MF, CCState &CCInfo,
1612 const SmallVectorImpl<ISD::InputArg> &Ins, bool IsRet) const {
1613 unsigned NumArgs = Ins.size();
1614 FunctionType *FType = MF.getFunction().getFunctionType();
1615
1616 for (unsigned i = 0; i != NumArgs; ++i) {
1617 MVT ArgVT = Ins[i].VT;
1618 ISD::ArgFlagsTy ArgFlags = Ins[i].Flags;
1619
1620 Type *ArgTy = nullptr;
1621 if (IsRet)
1622 ArgTy = FType->getReturnType();
1623 else if (Ins[i].isOrigArg())
1624 ArgTy = FType->getParamType(Ins[i].getOrigArgIndex());
1625
1626 RISCVABI::ABI ABI = MF.getSubtarget<RISCVSubtarget>().getTargetABI();
1627 if (CC_RISCV(MF.getDataLayout(), ABI, i, ArgVT, ArgVT, CCValAssign::Full,
1628 ArgFlags, CCInfo, /*IsRet=*/true, IsRet, ArgTy)) {
1629 LLVM_DEBUG(dbgs() << "InputArg #" << i << " has unhandled type "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("riscv-lower")) { dbgs() << "InputArg #" << i <<
" has unhandled type " << EVT(ArgVT).getEVTString() <<
'\n'; } } while (false)
1630 << EVT(ArgVT).getEVTString() << '\n')do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("riscv-lower")) { dbgs() << "InputArg #" << i <<
" has unhandled type " << EVT(ArgVT).getEVTString() <<
'\n'; } } while (false)
;
1631 llvm_unreachable(nullptr)::llvm::llvm_unreachable_internal(nullptr, "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/RISCV/RISCVISelLowering.cpp"
, 1631)
;
1632 }
1633 }
1634}
1635
1636void RISCVTargetLowering::analyzeOutputArgs(
1637 MachineFunction &MF, CCState &CCInfo,
1638 const SmallVectorImpl<ISD::OutputArg> &Outs, bool IsRet,
1639 CallLoweringInfo *CLI) const {
1640 unsigned NumArgs = Outs.size();
1641
1642 for (unsigned i = 0; i != NumArgs; i++) {
1643 MVT ArgVT = Outs[i].VT;
1644 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
1645 Type *OrigTy = CLI ? CLI->getArgs()[Outs[i].OrigArgIndex].Ty : nullptr;
1646
1647 RISCVABI::ABI ABI = MF.getSubtarget<RISCVSubtarget>().getTargetABI();
1648 if (CC_RISCV(MF.getDataLayout(), ABI, i, ArgVT, ArgVT, CCValAssign::Full,
1649 ArgFlags, CCInfo, Outs[i].IsFixed, IsRet, OrigTy)) {
1650 LLVM_DEBUG(dbgs() << "OutputArg #" << i << " has unhandled type "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("riscv-lower")) { dbgs() << "OutputArg #" << i <<
" has unhandled type " << EVT(ArgVT).getEVTString() <<
"\n"; } } while (false)
1651 << EVT(ArgVT).getEVTString() << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("riscv-lower")) { dbgs() << "OutputArg #" << i <<
" has unhandled type " << EVT(ArgVT).getEVTString() <<
"\n"; } } while (false)
;
1652 llvm_unreachable(nullptr)::llvm::llvm_unreachable_internal(nullptr, "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/RISCV/RISCVISelLowering.cpp"
, 1652)
;
1653 }
1654 }
1655}
1656
1657// Convert Val to a ValVT. Should not be called for CCValAssign::Indirect
1658// values.
1659static SDValue convertLocVTToValVT(SelectionDAG &DAG, SDValue Val,
1660 const CCValAssign &VA, const SDLoc &DL) {
1661 switch (VA.getLocInfo()) {
1662 default:
1663 llvm_unreachable("Unexpected CCValAssign::LocInfo")::llvm::llvm_unreachable_internal("Unexpected CCValAssign::LocInfo"
, "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/RISCV/RISCVISelLowering.cpp"
, 1663)
;
1664 case CCValAssign::Full:
1665 break;
1666 case CCValAssign::BCvt:
1667 if (VA.getLocVT() == MVT::i64 && VA.getValVT() == MVT::f32) {
1668 Val = DAG.getNode(RISCVISD::FMV_W_X_RV64, DL, MVT::f32, Val);
1669 break;
1670 }
1671 Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val);
1672 break;
1673 }
1674 return Val;
1675}
1676
1677// The caller is responsible for loading the full value if the argument is
1678// passed with CCValAssign::Indirect.
1679static SDValue unpackFromRegLoc(SelectionDAG &DAG, SDValue Chain,
1680 const CCValAssign &VA, const SDLoc &DL) {
1681 MachineFunction &MF = DAG.getMachineFunction();
1682 MachineRegisterInfo &RegInfo = MF.getRegInfo();
1683 EVT LocVT = VA.getLocVT();
1684 SDValue Val;
1685 const TargetRegisterClass *RC;
1686
1687 switch (LocVT.getSimpleVT().SimpleTy) {
1688 default:
1689 llvm_unreachable("Unexpected register type")::llvm::llvm_unreachable_internal("Unexpected register type",
"/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/RISCV/RISCVISelLowering.cpp"
, 1689)
;
1690 case MVT::i32:
1691 case MVT::i64:
1692 RC = &RISCV::GPRRegClass;
1693 break;
1694 case MVT::f32:
1695 RC = &RISCV::FPR32RegClass;
1696 break;
1697 case MVT::f64:
1698 RC = &RISCV::FPR64RegClass;
1699 break;
1700 }
1701
1702 Register VReg = RegInfo.createVirtualRegister(RC);
1703 RegInfo.addLiveIn(VA.getLocReg(), VReg);
1704 Val = DAG.getCopyFromReg(Chain, DL, VReg, LocVT);
1705
1706 if (VA.getLocInfo() == CCValAssign::Indirect)
1707 return Val;
1708
1709 return convertLocVTToValVT(DAG, Val, VA, DL);
1710}
1711
1712static SDValue convertValVTToLocVT(SelectionDAG &DAG, SDValue Val,
1713 const CCValAssign &VA, const SDLoc &DL) {
1714 EVT LocVT = VA.getLocVT();
1715
1716 switch (VA.getLocInfo()) {
1717 default:
1718 llvm_unreachable("Unexpected CCValAssign::LocInfo")::llvm::llvm_unreachable_internal("Unexpected CCValAssign::LocInfo"
, "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/RISCV/RISCVISelLowering.cpp"
, 1718)
;
1719 case CCValAssign::Full:
1720 break;
1721 case CCValAssign::BCvt:
1722 if (VA.getLocVT() == MVT::i64 && VA.getValVT() == MVT::f32) {
1723 Val = DAG.getNode(RISCVISD::FMV_X_ANYEXTW_RV64, DL, MVT::i64, Val);
1724 break;
1725 }
1726 Val = DAG.getNode(ISD::BITCAST, DL, LocVT, Val);
1727 break;
1728 }
1729 return Val;
1730}
1731
1732// The caller is responsible for loading the full value if the argument is
1733// passed with CCValAssign::Indirect.
1734static SDValue unpackFromMemLoc(SelectionDAG &DAG, SDValue Chain,
1735 const CCValAssign &VA, const SDLoc &DL) {
1736 MachineFunction &MF = DAG.getMachineFunction();
1737 MachineFrameInfo &MFI = MF.getFrameInfo();
1738 EVT LocVT = VA.getLocVT();
1739 EVT ValVT = VA.getValVT();
1740 EVT PtrVT = MVT::getIntegerVT(DAG.getDataLayout().getPointerSizeInBits(0));
1741 int FI = MFI.CreateFixedObject(ValVT.getSizeInBits() / 8,
1742 VA.getLocMemOffset(), /*Immutable=*/true);
1743 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
1744 SDValue Val;
1745
1746 ISD::LoadExtType ExtType;
1747 switch (VA.getLocInfo()) {
1748 default:
1749 llvm_unreachable("Unexpected CCValAssign::LocInfo")::llvm::llvm_unreachable_internal("Unexpected CCValAssign::LocInfo"
, "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/RISCV/RISCVISelLowering.cpp"
, 1749)
;
1750 case CCValAssign::Full:
1751 case CCValAssign::Indirect:
1752 case CCValAssign::BCvt:
1753 ExtType = ISD::NON_EXTLOAD;
1754 break;
1755 }
1756 Val = DAG.getExtLoad(
1757 ExtType, DL, LocVT, Chain, FIN,
1758 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI), ValVT);
1759 return Val;
1760}
1761
1762static SDValue unpackF64OnRV32DSoftABI(SelectionDAG &DAG, SDValue Chain,
1763 const CCValAssign &VA, const SDLoc &DL) {
1764 assert(VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64 &&((VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::
f64 && "Unexpected VA") ? static_cast<void> (0)
: __assert_fail ("VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64 && \"Unexpected VA\""
, "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/RISCV/RISCVISelLowering.cpp"
, 1765, __PRETTY_FUNCTION__))
1765 "Unexpected VA")((VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::
f64 && "Unexpected VA") ? static_cast<void> (0)
: __assert_fail ("VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64 && \"Unexpected VA\""
, "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/RISCV/RISCVISelLowering.cpp"
, 1765, __PRETTY_FUNCTION__))
;
1766 MachineFunction &MF = DAG.getMachineFunction();
1767 MachineFrameInfo &MFI = MF.getFrameInfo();
1768 MachineRegisterInfo &RegInfo = MF.getRegInfo();
1769
1770 if (VA.isMemLoc()) {
1771 // f64 is passed on the stack.
1772 int FI = MFI.CreateFixedObject(8, VA.getLocMemOffset(), /*Immutable=*/true);
1773 SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
1774 return DAG.getLoad(MVT::f64, DL, Chain, FIN,
1775 MachinePointerInfo::getFixedStack(MF, FI));
1776 }
1777
1778 assert(VA.isRegLoc() && "Expected register VA assignment")((VA.isRegLoc() && "Expected register VA assignment")
? static_cast<void> (0) : __assert_fail ("VA.isRegLoc() && \"Expected register VA assignment\""
, "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/RISCV/RISCVISelLowering.cpp"
, 1778, __PRETTY_FUNCTION__))
;
1779
1780 Register LoVReg = RegInfo.createVirtualRegister(&RISCV::GPRRegClass);
1781 RegInfo.addLiveIn(VA.getLocReg(), LoVReg);
1782 SDValue Lo = DAG.getCopyFromReg(Chain, DL, LoVReg, MVT::i32);
1783 SDValue Hi;
1784 if (VA.getLocReg() == RISCV::X17) {
1785 // Second half of f64 is passed on the stack.
1786 int FI = MFI.CreateFixedObject(4, 0, /*Immutable=*/true);
1787 SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
1788 Hi = DAG.getLoad(MVT::i32, DL, Chain, FIN,
1789 MachinePointerInfo::getFixedStack(MF, FI));
1790 } else {
1791 // Second half of f64 is passed in another GPR.
1792 Register HiVReg = RegInfo.createVirtualRegister(&RISCV::GPRRegClass);
1793 RegInfo.addLiveIn(VA.getLocReg() + 1, HiVReg);
1794 Hi = DAG.getCopyFromReg(Chain, DL, HiVReg, MVT::i32);
1795 }
1796 return DAG.getNode(RISCVISD::BuildPairF64, DL, MVT::f64, Lo, Hi);
1797}
1798
1799// Transform physical registers into virtual registers.
1800SDValue RISCVTargetLowering::LowerFormalArguments(
1801 SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
1802 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
1803 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
1804
1805 switch (CallConv) {
1806 default:
1807 report_fatal_error("Unsupported calling convention");
1808 case CallingConv::C:
1809 case CallingConv::Fast:
1810 break;
1811 }
1812
1813 MachineFunction &MF = DAG.getMachineFunction();
1814
1815 const Function &Func = MF.getFunction();
1816 if (Func.hasFnAttribute("interrupt")) {
1817 if (!Func.arg_empty())
1818 report_fatal_error(
1819 "Functions with the interrupt attribute cannot have arguments!");
1820
1821 StringRef Kind =
1822 MF.getFunction().getFnAttribute("interrupt").getValueAsString();
1823
1824 if (!(Kind == "user" || Kind == "supervisor" || Kind == "machine"))
1825 report_fatal_error(
1826 "Function interrupt attribute argument not supported!");
1827 }
1828
1829 EVT PtrVT = getPointerTy(DAG.getDataLayout());
1830 MVT XLenVT = Subtarget.getXLenVT();
1831 unsigned XLenInBytes = Subtarget.getXLen() / 8;
1832 // Used with vargs to acumulate store chains.
1833 std::vector<SDValue> OutChains;
1834
1835 // Assign locations to all of the incoming arguments.
1836 SmallVector<CCValAssign, 16> ArgLocs;
1837 CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
1838 analyzeInputArgs(MF, CCInfo, Ins, /*IsRet=*/false);
1839
1840 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1841 CCValAssign &VA = ArgLocs[i];
1842 SDValue ArgValue;
1843 // Passing f64 on RV32D with a soft float ABI must be handled as a special
1844 // case.
1845 if (VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64)
1846 ArgValue = unpackF64OnRV32DSoftABI(DAG, Chain, VA, DL);
1847 else if (VA.isRegLoc())
1848 ArgValue = unpackFromRegLoc(DAG, Chain, VA, DL);
1849 else
1850 ArgValue = unpackFromMemLoc(DAG, Chain, VA, DL);
1851
1852 if (VA.getLocInfo() == CCValAssign::Indirect) {
1853 // If the original argument was split and passed by reference (e.g. i128
1854 // on RV32), we need to load all parts of it here (using the same
1855 // address).
1856 InVals.push_back(DAG.getLoad(VA.getValVT(), DL, Chain, ArgValue,
1857 MachinePointerInfo()));
1858 unsigned ArgIndex = Ins[i].OrigArgIndex;
1859 assert(Ins[i].PartOffset == 0)((Ins[i].PartOffset == 0) ? static_cast<void> (0) : __assert_fail
("Ins[i].PartOffset == 0", "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/RISCV/RISCVISelLowering.cpp"
, 1859, __PRETTY_FUNCTION__))
;
1860 while (i + 1 != e && Ins[i + 1].OrigArgIndex == ArgIndex) {
1861 CCValAssign &PartVA = ArgLocs[i + 1];
1862 unsigned PartOffset = Ins[i + 1].PartOffset;
1863 SDValue Address = DAG.getNode(ISD::ADD, DL, PtrVT, ArgValue,
1864 DAG.getIntPtrConstant(PartOffset, DL));
1865 InVals.push_back(DAG.getLoad(PartVA.getValVT(), DL, Chain, Address,
1866 MachinePointerInfo()));
1867 ++i;
1868 }
1869 continue;
1870 }
1871 InVals.push_back(ArgValue);
1872 }
1873
1874 if (IsVarArg) {
1875 ArrayRef<MCPhysReg> ArgRegs = makeArrayRef(ArgGPRs);
1876 unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs);
1877 const TargetRegisterClass *RC = &RISCV::GPRRegClass;
1878 MachineFrameInfo &MFI = MF.getFrameInfo();
1879 MachineRegisterInfo &RegInfo = MF.getRegInfo();
1880 RISCVMachineFunctionInfo *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
1881
1882 // Offset of the first variable argument from stack pointer, and size of
1883 // the vararg save area. For now, the varargs save area is either zero or
1884 // large enough to hold a0-a7.
1885 int VaArgOffset, VarArgsSaveSize;
1886
1887 // If all registers are allocated, then all varargs must be passed on the
1888 // stack and we don't need to save any argregs.
1889 if (ArgRegs.size() == Idx) {
1890 VaArgOffset = CCInfo.getNextStackOffset();
1891 VarArgsSaveSize = 0;
1892 } else {
1893 VarArgsSaveSize = XLenInBytes * (ArgRegs.size() - Idx);
1894 VaArgOffset = -VarArgsSaveSize;
1895 }
1896
1897 // Record the frame index of the first variable argument
1898 // which is a value necessary to VASTART.
1899 int FI = MFI.CreateFixedObject(XLenInBytes, VaArgOffset, true);
1900 RVFI->setVarArgsFrameIndex(FI);
1901
1902 // If saving an odd number of registers then create an extra stack slot to
1903 // ensure that the frame pointer is 2*XLEN-aligned, which in turn ensures
1904 // offsets to even-numbered registered remain 2*XLEN-aligned.
1905 if (Idx % 2) {
1906 MFI.CreateFixedObject(XLenInBytes, VaArgOffset - (int)XLenInBytes, true);
1907 VarArgsSaveSize += XLenInBytes;
1908 }
1909
1910 // Copy the integer registers that may have been used for passing varargs
1911 // to the vararg save area.
1912 for (unsigned I = Idx; I < ArgRegs.size();
1913 ++I, VaArgOffset += XLenInBytes) {
1914 const Register Reg = RegInfo.createVirtualRegister(RC);
1915 RegInfo.addLiveIn(ArgRegs[I], Reg);
1916 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, XLenVT);
1917 FI = MFI.CreateFixedObject(XLenInBytes, VaArgOffset, true);
1918 SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
1919 SDValue Store = DAG.getStore(Chain, DL, ArgValue, PtrOff,
1920 MachinePointerInfo::getFixedStack(MF, FI));
1921 cast<StoreSDNode>(Store.getNode())
1922 ->getMemOperand()
1923 ->setValue((Value *)nullptr);
1924 OutChains.push_back(Store);
1925 }
1926 RVFI->setVarArgsSaveSize(VarArgsSaveSize);
1927 }
1928
1929 // All stores are grouped in one node to allow the matching between
1930 // the size of Ins and InVals. This only happens for vararg functions.
1931 if (!OutChains.empty()) {
1932 OutChains.push_back(Chain);
1933 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains);
1934 }
1935
1936 return Chain;
1937}
1938
1939/// isEligibleForTailCallOptimization - Check whether the call is eligible
1940/// for tail call optimization.
1941/// Note: This is modelled after ARM's IsEligibleForTailCallOptimization.
1942bool RISCVTargetLowering::isEligibleForTailCallOptimization(
1943 CCState &CCInfo, CallLoweringInfo &CLI, MachineFunction &MF,
1944 const SmallVector<CCValAssign, 16> &ArgLocs) const {
1945
1946 auto &Callee = CLI.Callee;
1947 auto CalleeCC = CLI.CallConv;
1948 auto &Outs = CLI.Outs;
1949 auto &Caller = MF.getFunction();
1950 auto CallerCC = Caller.getCallingConv();
1951
1952 // Do not tail call opt functions with "disable-tail-calls" attribute.
1953 if (Caller.getFnAttribute("disable-tail-calls").getValueAsString() == "true")
1954 return false;
1955
1956 // Exception-handling functions need a special set of instructions to
1957 // indicate a return to the hardware. Tail-calling another function would
1958 // probably break this.
1959 // TODO: The "interrupt" attribute isn't currently defined by RISC-V. This
1960 // should be expanded as new function attributes are introduced.
1961 if (Caller.hasFnAttribute("interrupt"))
1962 return false;
1963
1964 // Do not tail call opt if the stack is used to pass parameters.
1965 if (CCInfo.getNextStackOffset() != 0)
1966 return false;
1967
1968 // Do not tail call opt if any parameters need to be passed indirectly.
1969 // Since long doubles (fp128) and i128 are larger than 2*XLEN, they are
1970 // passed indirectly. So the address of the value will be passed in a
1971 // register, or if not available, then the address is put on the stack. In
1972 // order to pass indirectly, space on the stack often needs to be allocated
1973 // in order to store the value. In this case the CCInfo.getNextStackOffset()
1974 // != 0 check is not enough and we need to check if any CCValAssign ArgsLocs
1975 // are passed CCValAssign::Indirect.
1976 for (auto &VA : ArgLocs)
1977 if (VA.getLocInfo() == CCValAssign::Indirect)
1978 return false;
1979
1980 // Do not tail call opt if either caller or callee uses struct return
1981 // semantics.
1982 auto IsCallerStructRet = Caller.hasStructRetAttr();
1983 auto IsCalleeStructRet = Outs.empty() ? false : Outs[0].Flags.isSRet();
1984 if (IsCallerStructRet || IsCalleeStructRet)
1985 return false;
1986
1987 // Externally-defined functions with weak linkage should not be
1988 // tail-called. The behaviour of branch instructions in this situation (as
1989 // used for tail calls) is implementation-defined, so we cannot rely on the
1990 // linker replacing the tail call with a return.
1991 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1992 const GlobalValue *GV = G->getGlobal();
1993 if (GV->hasExternalWeakLinkage())
1994 return false;
1995 }
1996
1997 // The callee has to preserve all registers the caller needs to preserve.
1998 const RISCVRegisterInfo *TRI = Subtarget.getRegisterInfo();
1999 const uint32_t *CallerPreserved = TRI->getCallPreservedMask(MF, CallerCC);
2000 if (CalleeCC != CallerCC) {
2001 const uint32_t *CalleePreserved = TRI->getCallPreservedMask(MF, CalleeCC);
2002 if (!TRI->regmaskSubsetEqual(CallerPreserved, CalleePreserved))
2003 return false;
2004 }
2005
2006 // Byval parameters hand the function a pointer directly into the stack area
2007 // we want to reuse during a tail call. Working around this *is* possible
2008 // but less efficient and uglier in LowerCall.
2009 for (auto &Arg : Outs)
2010 if (Arg.Flags.isByVal())
2011 return false;
2012
2013 return true;
2014}
2015
2016// Lower a call to a callseq_start + CALL + callseq_end chain, and add input
2017// and output parameter nodes.
2018SDValue RISCVTargetLowering::LowerCall(CallLoweringInfo &CLI,
2019 SmallVectorImpl<SDValue> &InVals) const {
2020 SelectionDAG &DAG = CLI.DAG;
2021 SDLoc &DL = CLI.DL;
2022 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2023 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2024 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2025 SDValue Chain = CLI.Chain;
2026 SDValue Callee = CLI.Callee;
2027 bool &IsTailCall = CLI.IsTailCall;
2028 CallingConv::ID CallConv = CLI.CallConv;
2029 bool IsVarArg = CLI.IsVarArg;
2030 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2031 MVT XLenVT = Subtarget.getXLenVT();
2032
2033 MachineFunction &MF = DAG.getMachineFunction();
2034
2035 // Analyze the operands of the call, assigning locations to each operand.
2036 SmallVector<CCValAssign, 16> ArgLocs;
2037 CCState ArgCCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
2038 analyzeOutputArgs(MF, ArgCCInfo, Outs, /*IsRet=*/false, &CLI);
2039
2040 // Check if it's really possible to do a tail call.
2041 if (IsTailCall)
2042 IsTailCall = isEligibleForTailCallOptimization(ArgCCInfo, CLI, MF, ArgLocs);
2043
2044 if (IsTailCall)
2045 ++NumTailCalls;
2046 else if (CLI.CS && CLI.CS.isMustTailCall())
2047 report_fatal_error("failed to perform tail call elimination on a call "
2048 "site marked musttail");
2049
2050 // Get a count of how many bytes are to be pushed on the stack.
2051 unsigned NumBytes = ArgCCInfo.getNextStackOffset();
2052
2053 // Create local copies for byval args
2054 SmallVector<SDValue, 8> ByValArgs;
2055 for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
2056 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2057 if (!Flags.isByVal())
2058 continue;
2059
2060 SDValue Arg = OutVals[i];
2061 unsigned Size = Flags.getByValSize();
2062 unsigned Align = Flags.getByValAlign();
2063
2064 int FI = MF.getFrameInfo().CreateStackObject(Size, Align, /*isSS=*/false);
2065 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
2066 SDValue SizeNode = DAG.getConstant(Size, DL, XLenVT);
2067
2068 Chain = DAG.getMemcpy(Chain, DL, FIPtr, Arg, SizeNode, Align,
2069 /*IsVolatile=*/false,
2070 /*AlwaysInline=*/false,
2071 IsTailCall, MachinePointerInfo(),
2072 MachinePointerInfo());
2073 ByValArgs.push_back(FIPtr);
2074 }
2075
2076 if (!IsTailCall)
2077 Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, CLI.DL);
2078
2079 // Copy argument values to their designated locations.
2080 SmallVector<std::pair<Register, SDValue>, 8> RegsToPass;
2081 SmallVector<SDValue, 8> MemOpChains;
2082 SDValue StackPtr;
2083 for (unsigned i = 0, j = 0, e = ArgLocs.size(); i != e; ++i) {
2084 CCValAssign &VA = ArgLocs[i];
2085 SDValue ArgValue = OutVals[i];
2086 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2087
2088 // Handle passing f64 on RV32D with a soft float ABI as a special case.
2089 bool IsF64OnRV32DSoftABI =
2090 VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64;
2091 if (IsF64OnRV32DSoftABI && VA.isRegLoc()) {
2092 SDValue SplitF64 = DAG.getNode(
2093 RISCVISD::SplitF64, DL, DAG.getVTList(MVT::i32, MVT::i32), ArgValue);
2094 SDValue Lo = SplitF64.getValue(0);
2095 SDValue Hi = SplitF64.getValue(1);
2096
2097 Register RegLo = VA.getLocReg();
2098 RegsToPass.push_back(std::make_pair(RegLo, Lo));
2099
2100 if (RegLo == RISCV::X17) {
2101 // Second half of f64 is passed on the stack.
2102 // Work out the address of the stack slot.
2103 if (!StackPtr.getNode())
2104 StackPtr = DAG.getCopyFromReg(Chain, DL, RISCV::X2, PtrVT);
2105 // Emit the store.
2106 MemOpChains.push_back(
2107 DAG.getStore(Chain, DL, Hi, StackPtr, MachinePointerInfo()));
2108 } else {
2109 // Second half of f64 is passed in another GPR.
2110 assert(RegLo < RISCV::X31 && "Invalid register pair")((RegLo < RISCV::X31 && "Invalid register pair") ?
static_cast<void> (0) : __assert_fail ("RegLo < RISCV::X31 && \"Invalid register pair\""
, "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/RISCV/RISCVISelLowering.cpp"
, 2110, __PRETTY_FUNCTION__))
;
2111 Register RegHigh = RegLo + 1;
2112 RegsToPass.push_back(std::make_pair(RegHigh, Hi));
2113 }
2114 continue;
2115 }
2116
2117 // IsF64OnRV32DSoftABI && VA.isMemLoc() is handled below in the same way
2118 // as any other MemLoc.
2119
2120 // Promote the value if needed.
2121 // For now, only handle fully promoted and indirect arguments.
2122 if (VA.getLocInfo() == CCValAssign::Indirect) {
2123 // Store the argument in a stack slot and pass its address.
2124 SDValue SpillSlot = DAG.CreateStackTemporary(Outs[i].ArgVT);
2125 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2126 MemOpChains.push_back(
2127 DAG.getStore(Chain, DL, ArgValue, SpillSlot,
2128 MachinePointerInfo::getFixedStack(MF, FI)));
2129 // If the original argument was split (e.g. i128), we need
2130 // to store all parts of it here (and pass just one address).
2131 unsigned ArgIndex = Outs[i].OrigArgIndex;
2132 assert(Outs[i].PartOffset == 0)((Outs[i].PartOffset == 0) ? static_cast<void> (0) : __assert_fail
("Outs[i].PartOffset == 0", "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/RISCV/RISCVISelLowering.cpp"
, 2132, __PRETTY_FUNCTION__))
;
2133 while (i + 1 != e && Outs[i + 1].OrigArgIndex == ArgIndex) {
2134 SDValue PartValue = OutVals[i + 1];
2135 unsigned PartOffset = Outs[i + 1].PartOffset;
2136 SDValue Address = DAG.getNode(ISD::ADD, DL, PtrVT, SpillSlot,
2137 DAG.getIntPtrConstant(PartOffset, DL));
2138 MemOpChains.push_back(
2139 DAG.getStore(Chain, DL, PartValue, Address,
2140 MachinePointerInfo::getFixedStack(MF, FI)));
2141 ++i;
2142 }
2143 ArgValue = SpillSlot;
2144 } else {
2145 ArgValue = convertValVTToLocVT(DAG, ArgValue, VA, DL);
2146 }
2147
2148 // Use local copy if it is a byval arg.
2149 if (Flags.isByVal())
2150 ArgValue = ByValArgs[j++];
2151
2152 if (VA.isRegLoc()) {
2153 // Queue up the argument copies and emit them at the end.
2154 RegsToPass.push_back(std::make_pair(VA.getLocReg(), ArgValue));
2155 } else {
2156 assert(VA.isMemLoc() && "Argument not register or memory")((VA.isMemLoc() && "Argument not register or memory")
? static_cast<void> (0) : __assert_fail ("VA.isMemLoc() && \"Argument not register or memory\""
, "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/RISCV/RISCVISelLowering.cpp"
, 2156, __PRETTY_FUNCTION__))
;
2157 assert(!IsTailCall && "Tail call not allowed if stack is used "((!IsTailCall && "Tail call not allowed if stack is used "
"for passing parameters") ? static_cast<void> (0) : __assert_fail
("!IsTailCall && \"Tail call not allowed if stack is used \" \"for passing parameters\""
, "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/RISCV/RISCVISelLowering.cpp"
, 2158, __PRETTY_FUNCTION__))
2158 "for passing parameters")((!IsTailCall && "Tail call not allowed if stack is used "
"for passing parameters") ? static_cast<void> (0) : __assert_fail
("!IsTailCall && \"Tail call not allowed if stack is used \" \"for passing parameters\""
, "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/RISCV/RISCVISelLowering.cpp"
, 2158, __PRETTY_FUNCTION__))
;
2159
2160 // Work out the address of the stack slot.
2161 if (!StackPtr.getNode())
2162 StackPtr = DAG.getCopyFromReg(Chain, DL, RISCV::X2, PtrVT);
2163 SDValue Address =
2164 DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr,
2165 DAG.getIntPtrConstant(VA.getLocMemOffset(), DL));
2166
2167 // Emit the store.
2168 MemOpChains.push_back(
2169 DAG.getStore(Chain, DL, ArgValue, Address, MachinePointerInfo()));
2170 }
2171 }
2172
2173 // Join the stores, which are independent of one another.
2174 if (!MemOpChains.empty())
2175 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
2176
2177 SDValue Glue;
2178
2179 // Build a sequence of copy-to-reg nodes, chained and glued together.
2180 for (auto &Reg : RegsToPass) {
2181 Chain = DAG.getCopyToReg(Chain, DL, Reg.first, Reg.second, Glue);
2182 Glue = Chain.getValue(1);
2183 }
2184
2185 // If the callee is a GlobalAddress/ExternalSymbol node, turn it into a
2186 // TargetGlobalAddress/TargetExternalSymbol node so that legalize won't
2187 // split it and then direct call can be matched by PseudoCALL.
2188 if (GlobalAddressSDNode *S = dyn_cast<GlobalAddressSDNode>(Callee)) {
2189 const GlobalValue *GV = S->getGlobal();
2190
2191 unsigned OpFlags = RISCVII::MO_CALL;
2192 if (!getTargetMachine().shouldAssumeDSOLocal(*GV->getParent(), GV))
2193 OpFlags = RISCVII::MO_PLT;
2194
2195 Callee = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, OpFlags);
2196 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2197 unsigned OpFlags = RISCVII::MO_CALL;
2198
2199 if (!getTargetMachine().shouldAssumeDSOLocal(*MF.getFunction().getParent(),
2200 nullptr))
2201 OpFlags = RISCVII::MO_PLT;
2202
2203 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), PtrVT, OpFlags);
2204 }
2205
2206 // The first call operand is the chain and the second is the target address.
2207 SmallVector<SDValue, 8> Ops;
2208 Ops.push_back(Chain);
2209 Ops.push_back(Callee);
2210
2211 // Add argument registers to the end of the list so that they are
2212 // known live into the call.
2213 for (auto &Reg : RegsToPass)
2214 Ops.push_back(DAG.getRegister(Reg.first, Reg.second.getValueType()));
2215
2216 if (!IsTailCall) {
2217 // Add a register mask operand representing the call-preserved registers.
2218 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
2219 const uint32_t *Mask = TRI->getCallPreservedMask(MF, CallConv);
2220 assert(Mask && "Missing call preserved mask for calling convention")((Mask && "Missing call preserved mask for calling convention"
) ? static_cast<void> (0) : __assert_fail ("Mask && \"Missing call preserved mask for calling convention\""
, "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/RISCV/RISCVISelLowering.cpp"
, 2220, __PRETTY_FUNCTION__))
;
2221 Ops.push_back(DAG.getRegisterMask(Mask));
2222 }
2223
2224 // Glue the call to the argument copies, if any.
2225 if (Glue.getNode())
2226 Ops.push_back(Glue);
2227
2228 // Emit the call.
2229 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2230
2231 if (IsTailCall) {
2232 MF.getFrameInfo().setHasTailCall();
2233 return DAG.getNode(RISCVISD::TAIL, DL, NodeTys, Ops);
2234 }
2235
2236 Chain = DAG.getNode(RISCVISD::CALL, DL, NodeTys, Ops);
2237 Glue = Chain.getValue(1);
2238
2239 // Mark the end of the call, which is glued to the call itself.
2240 Chain = DAG.getCALLSEQ_END(Chain,
2241 DAG.getConstant(NumBytes, DL, PtrVT, true),
2242 DAG.getConstant(0, DL, PtrVT, true),
2243 Glue, DL);
2244 Glue = Chain.getValue(1);
2245
2246 // Assign locations to each value returned by this call.
2247 SmallVector<CCValAssign, 16> RVLocs;
2248 CCState RetCCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext());
2249 analyzeInputArgs(MF, RetCCInfo, Ins, /*IsRet=*/true);
2250
2251 // Copy all of the result registers out of their specified physreg.
2252 for (auto &VA : RVLocs) {
2253 // Copy the value out
2254 SDValue RetValue =
2255 DAG.getCopyFromReg(Chain, DL, VA.getLocReg(), VA.getLocVT(), Glue);
2256 // Glue the RetValue to the end of the call sequence
2257 Chain = RetValue.getValue(1);
2258 Glue = RetValue.getValue(2);
2259
2260 if (VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64) {
2261 assert(VA.getLocReg() == ArgGPRs[0] && "Unexpected reg assignment")((VA.getLocReg() == ArgGPRs[0] && "Unexpected reg assignment"
) ? static_cast<void> (0) : __assert_fail ("VA.getLocReg() == ArgGPRs[0] && \"Unexpected reg assignment\""
, "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/RISCV/RISCVISelLowering.cpp"
, 2261, __PRETTY_FUNCTION__))
;
2262 SDValue RetValue2 =
2263 DAG.getCopyFromReg(Chain, DL, ArgGPRs[1], MVT::i32, Glue);
2264 Chain = RetValue2.getValue(1);
2265 Glue = RetValue2.getValue(2);
2266 RetValue = DAG.getNode(RISCVISD::BuildPairF64, DL, MVT::f64, RetValue,
2267 RetValue2);
2268 }
2269
2270 RetValue = convertLocVTToValVT(DAG, RetValue, VA, DL);
2271
2272 InVals.push_back(RetValue);
2273 }
2274
2275 return Chain;
2276}
2277
2278bool RISCVTargetLowering::CanLowerReturn(
2279 CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg,
2280 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
2281 SmallVector<CCValAssign, 16> RVLocs;
2282 CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
2283 for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
2284 MVT VT = Outs[i].VT;
2285 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
2286 RISCVABI::ABI ABI = MF.getSubtarget<RISCVSubtarget>().getTargetABI();
2287 if (CC_RISCV(MF.getDataLayout(), ABI, i, VT, VT, CCValAssign::Full,
2288 ArgFlags, CCInfo, /*IsFixed=*/true, /*IsRet=*/true, nullptr))
2289 return false;
2290 }
2291 return true;
2292}
2293
2294SDValue
2295RISCVTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
2296 bool IsVarArg,
2297 const SmallVectorImpl<ISD::OutputArg> &Outs,
2298 const SmallVectorImpl<SDValue> &OutVals,
2299 const SDLoc &DL, SelectionDAG &DAG) const {
2300 // Stores the assignment of the return value to a location.
2301 SmallVector<CCValAssign, 16> RVLocs;
2302
2303 // Info about the registers and stack slot.
2304 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
2305 *DAG.getContext());
2306
2307 analyzeOutputArgs(DAG.getMachineFunction(), CCInfo, Outs, /*IsRet=*/true,
2308 nullptr);
2309
2310 SDValue Glue;
2311 SmallVector<SDValue, 4> RetOps(1, Chain);
2312
2313 // Copy the result values into the output registers.
2314 for (unsigned i = 0, e = RVLocs.size(); i < e; ++i) {
2315 SDValue Val = OutVals[i];
2316 CCValAssign &VA = RVLocs[i];
2317 assert(VA.isRegLoc() && "Can only return in registers!")((VA.isRegLoc() && "Can only return in registers!") ?
static_cast<void> (0) : __assert_fail ("VA.isRegLoc() && \"Can only return in registers!\""
, "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/RISCV/RISCVISelLowering.cpp"
, 2317, __PRETTY_FUNCTION__))
;
2318
2319 if (VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64) {
2320 // Handle returning f64 on RV32D with a soft float ABI.
2321 assert(VA.isRegLoc() && "Expected return via registers")((VA.isRegLoc() && "Expected return via registers") ?
static_cast<void> (0) : __assert_fail ("VA.isRegLoc() && \"Expected return via registers\""
, "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/RISCV/RISCVISelLowering.cpp"
, 2321, __PRETTY_FUNCTION__))
;
2322 SDValue SplitF64 = DAG.getNode(RISCVISD::SplitF64, DL,
2323 DAG.getVTList(MVT::i32, MVT::i32), Val);
2324 SDValue Lo = SplitF64.getValue(0);
2325 SDValue Hi = SplitF64.getValue(1);
2326 Register RegLo = VA.getLocReg();
2327 assert(RegLo < RISCV::X31 && "Invalid register pair")((RegLo < RISCV::X31 && "Invalid register pair") ?
static_cast<void> (0) : __assert_fail ("RegLo < RISCV::X31 && \"Invalid register pair\""
, "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/RISCV/RISCVISelLowering.cpp"
, 2327, __PRETTY_FUNCTION__))
;
2328 Register RegHi = RegLo + 1;
2329 Chain = DAG.getCopyToReg(Chain, DL, RegLo, Lo, Glue);
2330 Glue = Chain.getValue(1);
2331 RetOps.push_back(DAG.getRegister(RegLo, MVT::i32));
2332 Chain = DAG.getCopyToReg(Chain, DL, RegHi, Hi, Glue);
2333 Glue = Chain.getValue(1);
2334 RetOps.push_back(DAG.getRegister(RegHi, MVT::i32));
2335 } else {
2336 // Handle a 'normal' return.
2337 Val = convertValVTToLocVT(DAG, Val, VA, DL);
2338 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Glue);
2339
2340 // Guarantee that all emitted copies are stuck together.
2341 Glue = Chain.getValue(1);
2342 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2343 }
2344 }
2345
2346 RetOps[0] = Chain; // Update chain.
2347
2348 // Add the glue node if we have it.
2349 if (Glue.getNode()) {
2350 RetOps.push_back(Glue);
2351 }
2352
2353 // Interrupt service routines use different return instructions.
2354 const Function &Func = DAG.getMachineFunction().getFunction();
2355 if (Func.hasFnAttribute("interrupt")) {
2356 if (!Func.getReturnType()->isVoidTy())
2357 report_fatal_error(
2358 "Functions with the interrupt attribute must have void return type!");
2359
2360 MachineFunction &MF = DAG.getMachineFunction();
2361 StringRef Kind =
2362 MF.getFunction().getFnAttribute("interrupt").getValueAsString();
2363
2364 unsigned RetOpc;
2365 if (Kind == "user")
2366 RetOpc = RISCVISD::URET_FLAG;
2367 else if (Kind == "supervisor")
2368 RetOpc = RISCVISD::SRET_FLAG;
2369 else
2370 RetOpc = RISCVISD::MRET_FLAG;
2371
2372 return DAG.getNode(RetOpc, DL, MVT::Other, RetOps);
2373 }
2374
2375 return DAG.getNode(RISCVISD::RET_FLAG, DL, MVT::Other, RetOps);
2376}
2377
2378const char *RISCVTargetLowering::getTargetNodeName(unsigned Opcode) const {
2379 switch ((RISCVISD::NodeType)Opcode) {
2380 case RISCVISD::FIRST_NUMBER:
2381 break;
2382 case RISCVISD::RET_FLAG:
2383 return "RISCVISD::RET_FLAG";
2384 case RISCVISD::URET_FLAG:
2385 return "RISCVISD::URET_FLAG";
2386 case RISCVISD::SRET_FLAG:
2387 return "RISCVISD::SRET_FLAG";
2388 case RISCVISD::MRET_FLAG:
2389 return "RISCVISD::MRET_FLAG";
2390 case RISCVISD::CALL:
2391 return "RISCVISD::CALL";
2392 case RISCVISD::SELECT_CC:
2393 return "RISCVISD::SELECT_CC";
2394 case RISCVISD::BuildPairF64:
2395 return "RISCVISD::BuildPairF64";
2396 case RISCVISD::SplitF64:
2397 return "RISCVISD::SplitF64";
2398 case RISCVISD::TAIL:
2399 return "RISCVISD::TAIL";
2400 case RISCVISD::SLLW:
2401 return "RISCVISD::SLLW";
2402 case RISCVISD::SRAW:
2403 return "RISCVISD::SRAW";
2404 case RISCVISD::SRLW:
2405 return "RISCVISD::SRLW";
2406 case RISCVISD::DIVW:
2407 return "RISCVISD::DIVW";
2408 case RISCVISD::DIVUW:
2409 return "RISCVISD::DIVUW";
2410 case RISCVISD::REMUW:
2411 return "RISCVISD::REMUW";
2412 case RISCVISD::FMV_W_X_RV64:
2413 return "RISCVISD::FMV_W_X_RV64";
2414 case RISCVISD::FMV_X_ANYEXTW_RV64:
2415 return "RISCVISD::FMV_X_ANYEXTW_RV64";
2416 case RISCVISD::READ_CYCLE_WIDE:
2417 return "RISCVISD::READ_CYCLE_WIDE";
2418 }
2419 return nullptr;
2420}
2421
2422/// getConstraintType - Given a constraint letter, return the type of
2423/// constraint it is for this target.
2424RISCVTargetLowering::ConstraintType
2425RISCVTargetLowering::getConstraintType(StringRef Constraint) const {
2426 if (Constraint.size() == 1) {
2427 switch (Constraint[0]) {
2428 default:
2429 break;
2430 case 'f':
2431 return C_RegisterClass;
2432 case 'I':
2433 case 'J':
2434 case 'K':
2435 return C_Immediate;
2436 case 'A':
2437 return C_Memory;
2438 }
2439 }
2440 return TargetLowering::getConstraintType(Constraint);
2441}
2442
2443std::pair<unsigned, const TargetRegisterClass *>
2444RISCVTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
2445 StringRef Constraint,
2446 MVT VT) const {
2447 // First, see if this is a constraint that directly corresponds to a
2448 // RISCV register class.
2449 if (Constraint.size() == 1) {
2450 switch (Constraint[0]) {
2451 case 'r':
2452 return std::make_pair(0U, &RISCV::GPRRegClass);
2453 case 'f':
2454 if (Subtarget.hasStdExtF() && VT == MVT::f32)
2455 return std::make_pair(0U, &RISCV::FPR32RegClass);
2456 if (Subtarget.hasStdExtD() && VT == MVT::f64)
2457 return std::make_pair(0U, &RISCV::FPR64RegClass);
2458 break;
2459 default:
2460 break;
2461 }
2462 }
2463
2464 // Clang will correctly decode the usage of register name aliases into their
2465 // official names. However, other frontends like `rustc` do not. This allows
2466 // users of these frontends to use the ABI names for registers in LLVM-style
2467 // register constraints.
2468 Register XRegFromAlias = StringSwitch<Register>(Constraint.lower())
2469 .Case("{zero}", RISCV::X0)
2470 .Case("{ra}", RISCV::X1)
2471 .Case("{sp}", RISCV::X2)
2472 .Case("{gp}", RISCV::X3)
2473 .Case("{tp}", RISCV::X4)
2474 .Case("{t0}", RISCV::X5)
2475 .Case("{t1}", RISCV::X6)
2476 .Case("{t2}", RISCV::X7)
2477 .Cases("{s0}", "{fp}", RISCV::X8)
2478 .Case("{s1}", RISCV::X9)
2479 .Case("{a0}", RISCV::X10)
2480 .Case("{a1}", RISCV::X11)
2481 .Case("{a2}", RISCV::X12)
2482 .Case("{a3}", RISCV::X13)
2483 .Case("{a4}", RISCV::X14)
2484 .Case("{a5}", RISCV::X15)
2485 .Case("{a6}", RISCV::X16)
2486 .Case("{a7}", RISCV::X17)
2487 .Case("{s2}", RISCV::X18)
2488 .Case("{s3}", RISCV::X19)
2489 .Case("{s4}", RISCV::X20)
2490 .Case("{s5}", RISCV::X21)
2491 .Case("{s6}", RISCV::X22)
2492 .Case("{s7}", RISCV::X23)
2493 .Case("{s8}", RISCV::X24)
2494 .Case("{s9}", RISCV::X25)
2495 .Case("{s10}", RISCV::X26)
2496 .Case("{s11}", RISCV::X27)
2497 .Case("{t3}", RISCV::X28)
2498 .Case("{t4}", RISCV::X29)
2499 .Case("{t5}", RISCV::X30)
2500 .Case("{t6}", RISCV::X31)
2501 .Default(RISCV::NoRegister);
2502 if (XRegFromAlias != RISCV::NoRegister)
2503 return std::make_pair(XRegFromAlias, &RISCV::GPRRegClass);
2504
2505 // Since TargetLowering::getRegForInlineAsmConstraint uses the name of the
2506 // TableGen record rather than the AsmName to choose registers for InlineAsm
2507 // constraints, plus we want to match those names to the widest floating point
2508 // register type available, manually select floating point registers here.
2509 //
2510 // The second case is the ABI name of the register, so that frontends can also
2511 // use the ABI names in register constraint lists.
2512 if (Subtarget.hasStdExtF() || Subtarget.hasStdExtD()) {
2513 std::pair<Register, Register> FReg =
2514 StringSwitch<std::pair<Register, Register>>(Constraint.lower())
2515 .Cases("{f0}", "{ft0}", {RISCV::F0_F, RISCV::F0_D})
2516 .Cases("{f1}", "{ft1}", {RISCV::F1_F, RISCV::F1_D})
2517 .Cases("{f2}", "{ft2}", {RISCV::F2_F, RISCV::F2_D})
2518 .Cases("{f3}", "{ft3}", {RISCV::F3_F, RISCV::F3_D})
2519 .Cases("{f4}", "{ft4}", {RISCV::F4_F, RISCV::F4_D})
2520 .Cases("{f5}", "{ft5}", {RISCV::F5_F, RISCV::F5_D})
2521 .Cases("{f6}", "{ft6}", {RISCV::F6_F, RISCV::F6_D})
2522 .Cases("{f7}", "{ft7}", {RISCV::F7_F, RISCV::F7_D})
2523 .Cases("{f8}", "{fs0}", {RISCV::F8_F, RISCV::F8_D})
2524 .Cases("{f9}", "{fs1}", {RISCV::F9_F, RISCV::F9_D})
2525 .Cases("{f10}", "{fa0}", {RISCV::F10_F, RISCV::F10_D})
2526 .Cases("{f11}", "{fa1}", {RISCV::F11_F, RISCV::F11_D})
2527 .Cases("{f12}", "{fa2}", {RISCV::F12_F, RISCV::F12_D})
2528 .Cases("{f13}", "{fa3}", {RISCV::F13_F, RISCV::F13_D})
2529 .Cases("{f14}", "{fa4}", {RISCV::F14_F, RISCV::F14_D})
2530 .Cases("{f15}", "{fa5}", {RISCV::F15_F, RISCV::F15_D})
2531 .Cases("{f16}", "{fa6}", {RISCV::F16_F, RISCV::F16_D})
2532 .Cases("{f17}", "{fa7}", {RISCV::F17_F, RISCV::F17_D})
2533 .Cases("{f18}", "{fs2}", {RISCV::F18_F, RISCV::F18_D})
2534 .Cases("{f19}", "{fs3}", {RISCV::F19_F, RISCV::F19_D})
2535 .Cases("{f20}", "{fs4}", {RISCV::F20_F, RISCV::F20_D})
2536 .Cases("{f21}", "{fs5}", {RISCV::F21_F, RISCV::F21_D})
2537 .Cases("{f22}", "{fs6}", {RISCV::F22_F, RISCV::F22_D})
2538 .Cases("{f23}", "{fs7}", {RISCV::F23_F, RISCV::F23_D})
2539 .Cases("{f24}", "{fs8}", {RISCV::F24_F, RISCV::F24_D})
2540 .Cases("{f25}", "{fs9}", {RISCV::F25_F, RISCV::F25_D})
2541 .Cases("{f26}", "{fs10}", {RISCV::F26_F, RISCV::F26_D})
2542 .Cases("{f27}", "{fs11}", {RISCV::F27_F, RISCV::F27_D})
2543 .Cases("{f28}", "{ft8}", {RISCV::F28_F, RISCV::F28_D})
2544 .Cases("{f29}", "{ft9}", {RISCV::F29_F, RISCV::F29_D})
2545 .Cases("{f30}", "{ft10}", {RISCV::F30_F, RISCV::F30_D})
2546 .Cases("{f31}", "{ft11}", {RISCV::F31_F, RISCV::F31_D})
2547 .Default({RISCV::NoRegister, RISCV::NoRegister});
2548 if (FReg.first != RISCV::NoRegister)
2549 return Subtarget.hasStdExtD()
2550 ? std::make_pair(FReg.second, &RISCV::FPR64RegClass)
2551 : std::make_pair(FReg.first, &RISCV::FPR32RegClass);
2552 }
2553
2554 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
2555}
2556
2557unsigned
2558RISCVTargetLowering::getInlineAsmMemConstraint(StringRef ConstraintCode) const {
2559 // Currently only support length 1 constraints.
2560 if (ConstraintCode.size() == 1) {
2561 switch (ConstraintCode[0]) {
2562 case 'A':
2563 return InlineAsm::Constraint_A;
2564 default:
2565 break;
2566 }
2567 }
2568
2569 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
2570}
2571
2572void RISCVTargetLowering::LowerAsmOperandForConstraint(
2573 SDValue Op, std::string &Constraint, std::vector<SDValue> &Ops,
2574 SelectionDAG &DAG) const {
2575 // Currently only support length 1 constraints.
2576 if (Constraint.length() == 1) {
2577 switch (Constraint[0]) {
2578 case 'I':
2579 // Validate & create a 12-bit signed immediate operand.
2580 if (auto *C = dyn_cast<ConstantSDNode>(Op)) {
2581 uint64_t CVal = C->getSExtValue();
2582 if (isInt<12>(CVal))
2583 Ops.push_back(
2584 DAG.getTargetConstant(CVal, SDLoc(Op), Subtarget.getXLenVT()));
2585 }
2586 return;
2587 case 'J':
2588 // Validate & create an integer zero operand.
2589 if (auto *C = dyn_cast<ConstantSDNode>(Op))
2590 if (C->getZExtValue() == 0)
2591 Ops.push_back(
2592 DAG.getTargetConstant(0, SDLoc(Op), Subtarget.getXLenVT()));
2593 return;
2594 case 'K':
2595 // Validate & create a 5-bit unsigned immediate operand.
2596 if (auto *C = dyn_cast<ConstantSDNode>(Op)) {
2597 uint64_t CVal = C->getZExtValue();
2598 if (isUInt<5>(CVal))
2599 Ops.push_back(
2600 DAG.getTargetConstant(CVal, SDLoc(Op), Subtarget.getXLenVT()));
2601 }
2602 return;
2603 default:
2604 break;
2605 }
2606 }
2607 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
2608}
2609
2610Instruction *RISCVTargetLowering::emitLeadingFence(IRBuilder<> &Builder,
2611 Instruction *Inst,
2612 AtomicOrdering Ord) const {
2613 if (isa<LoadInst>(Inst) && Ord == AtomicOrdering::SequentiallyConsistent)
2614 return Builder.CreateFence(Ord);
2615 if (isa<StoreInst>(Inst) && isReleaseOrStronger(Ord))
2616 return Builder.CreateFence(AtomicOrdering::Release);
2617 return nullptr;
2618}
2619
2620Instruction *RISCVTargetLowering::emitTrailingFence(IRBuilder<> &Builder,
2621 Instruction *Inst,
2622 AtomicOrdering Ord) const {
2623 if (isa<LoadInst>(Inst) && isAcquireOrStronger(Ord))
2624 return Builder.CreateFence(AtomicOrdering::Acquire);
2625 return nullptr;
2626}
2627
2628TargetLowering::AtomicExpansionKind
2629RISCVTargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
2630 // atomicrmw {fadd,fsub} must be expanded to use compare-exchange, as floating
2631 // point operations can't be used in an lr/sc sequence without breaking the
2632 // forward-progress guarantee.
2633 if (AI->isFloatingPointOperation())
2634 return AtomicExpansionKind::CmpXChg;
2635
2636 unsigned Size = AI->getType()->getPrimitiveSizeInBits();
2637 if (Size == 8 || Size == 16)
2638 return AtomicExpansionKind::MaskedIntrinsic;
2639 return AtomicExpansionKind::None;
2640}
2641
2642static Intrinsic::ID
2643getIntrinsicForMaskedAtomicRMWBinOp(unsigned XLen, AtomicRMWInst::BinOp BinOp) {
2644 if (XLen == 32) {
2645 switch (BinOp) {
2646 default:
2647 llvm_unreachable("Unexpected AtomicRMW BinOp")::llvm::llvm_unreachable_internal("Unexpected AtomicRMW BinOp"
, "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/RISCV/RISCVISelLowering.cpp"
, 2647)
;
2648 case AtomicRMWInst::Xchg:
2649 return Intrinsic::riscv_masked_atomicrmw_xchg_i32;
2650 case AtomicRMWInst::Add:
2651 return Intrinsic::riscv_masked_atomicrmw_add_i32;
2652 case AtomicRMWInst::Sub:
2653 return Intrinsic::riscv_masked_atomicrmw_sub_i32;
2654 case AtomicRMWInst::Nand:
2655 return Intrinsic::riscv_masked_atomicrmw_nand_i32;
2656 case AtomicRMWInst::Max:
2657 return Intrinsic::riscv_masked_atomicrmw_max_i32;
2658 case AtomicRMWInst::Min:
2659 return Intrinsic::riscv_masked_atomicrmw_min_i32;
2660 case AtomicRMWInst::UMax:
2661 return Intrinsic::riscv_masked_atomicrmw_umax_i32;
2662 case AtomicRMWInst::UMin:
2663 return Intrinsic::riscv_masked_atomicrmw_umin_i32;
2664 }
2665 }
2666
2667 if (XLen == 64) {
2668 switch (BinOp) {
2669 default:
2670 llvm_unreachable("Unexpected AtomicRMW BinOp")::llvm::llvm_unreachable_internal("Unexpected AtomicRMW BinOp"
, "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/RISCV/RISCVISelLowering.cpp"
, 2670)
;
2671 case AtomicRMWInst::Xchg:
2672 return Intrinsic::riscv_masked_atomicrmw_xchg_i64;
2673 case AtomicRMWInst::Add:
2674 return Intrinsic::riscv_masked_atomicrmw_add_i64;
2675 case AtomicRMWInst::Sub:
2676 return Intrinsic::riscv_masked_atomicrmw_sub_i64;
2677 case AtomicRMWInst::Nand:
2678 return Intrinsic::riscv_masked_atomicrmw_nand_i64;
2679 case AtomicRMWInst::Max:
2680 return Intrinsic::riscv_masked_atomicrmw_max_i64;
2681 case AtomicRMWInst::Min:
2682 return Intrinsic::riscv_masked_atomicrmw_min_i64;
2683 case AtomicRMWInst::UMax:
2684 return Intrinsic::riscv_masked_atomicrmw_umax_i64;
2685 case AtomicRMWInst::UMin:
2686 return Intrinsic::riscv_masked_atomicrmw_umin_i64;
2687 }
2688 }
2689
2690 llvm_unreachable("Unexpected XLen\n")::llvm::llvm_unreachable_internal("Unexpected XLen\n", "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/RISCV/RISCVISelLowering.cpp"
, 2690)
;
2691}
2692
2693Value *RISCVTargetLowering::emitMaskedAtomicRMWIntrinsic(
2694 IRBuilder<> &Builder, AtomicRMWInst *AI, Value *AlignedAddr, Value *Incr,
2695 Value *Mask, Value *ShiftAmt, AtomicOrdering Ord) const {
2696 unsigned XLen = Subtarget.getXLen();
2697 Value *Ordering =
2698 Builder.getIntN(XLen, static_cast<uint64_t>(AI->getOrdering()));
2699 Type *Tys[] = {AlignedAddr->getType()};
2700 Function *LrwOpScwLoop = Intrinsic::getDeclaration(
2701 AI->getModule(),
2702 getIntrinsicForMaskedAtomicRMWBinOp(XLen, AI->getOperation()), Tys);
2703
2704 if (XLen == 64) {
2705 Incr = Builder.CreateSExt(Incr, Builder.getInt64Ty());
2706 Mask = Builder.CreateSExt(Mask, Builder.getInt64Ty());
2707 ShiftAmt = Builder.CreateSExt(ShiftAmt, Builder.getInt64Ty());
2708 }
2709
2710 Value *Result;
2711
2712 // Must pass the shift amount needed to sign extend the loaded value prior
2713 // to performing a signed comparison for min/max. ShiftAmt is the number of
2714 // bits to shift the value into position. Pass XLen-ShiftAmt-ValWidth, which
2715 // is the number of bits to left+right shift the value in order to
2716 // sign-extend.
2717 if (AI->getOperation() == AtomicRMWInst::Min ||
2718 AI->getOperation() == AtomicRMWInst::Max) {
2719 const DataLayout &DL = AI->getModule()->getDataLayout();
2720 unsigned ValWidth =
2721 DL.getTypeStoreSizeInBits(AI->getValOperand()->getType());
2722 Value *SextShamt =
2723 Builder.CreateSub(Builder.getIntN(XLen, XLen - ValWidth), ShiftAmt);
2724 Result = Builder.CreateCall(LrwOpScwLoop,
2725 {AlignedAddr, Incr, Mask, SextShamt, Ordering});
2726 } else {
2727 Result =
2728 Builder.CreateCall(LrwOpScwLoop, {AlignedAddr, Incr, Mask, Ordering});
2729 }
2730
2731 if (XLen == 64)
2732 Result = Builder.CreateTrunc(Result, Builder.getInt32Ty());
2733 return Result;
2734}
2735
2736TargetLowering::AtomicExpansionKind
2737RISCVTargetLowering::shouldExpandAtomicCmpXchgInIR(
2738 AtomicCmpXchgInst *CI) const {
2739 unsigned Size = CI->getCompareOperand()->getType()->getPrimitiveSizeInBits();
2740 if (Size == 8 || Size == 16)
2741 return AtomicExpansionKind::MaskedIntrinsic;
2742 return AtomicExpansionKind::None;
2743}
2744
2745Value *RISCVTargetLowering::emitMaskedAtomicCmpXchgIntrinsic(
2746 IRBuilder<> &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr,
2747 Value *CmpVal, Value *NewVal, Value *Mask, AtomicOrdering Ord) const {
2748 unsigned XLen = Subtarget.getXLen();
2749 Value *Ordering = Builder.getIntN(XLen, static_cast<uint64_t>(Ord));
2750 Intrinsic::ID CmpXchgIntrID = Intrinsic::riscv_masked_cmpxchg_i32;
2751 if (XLen == 64) {
2752 CmpVal = Builder.CreateSExt(CmpVal, Builder.getInt64Ty());
2753 NewVal = Builder.CreateSExt(NewVal, Builder.getInt64Ty());
2754 Mask = Builder.CreateSExt(Mask, Builder.getInt64Ty());
2755 CmpXchgIntrID = Intrinsic::riscv_masked_cmpxchg_i64;
2756 }
2757 Type *Tys[] = {AlignedAddr->getType()};
2758 Function *MaskedCmpXchg =
2759 Intrinsic::getDeclaration(CI->getModule(), CmpXchgIntrID, Tys);
2760 Value *Result = Builder.CreateCall(
2761 MaskedCmpXchg, {AlignedAddr, CmpVal, NewVal, Mask, Ordering});
2762 if (XLen == 64)
2763 Result = Builder.CreateTrunc(Result, Builder.getInt32Ty());
2764 return Result;
2765}
2766
2767unsigned RISCVTargetLowering::getExceptionPointerRegister(
2768 const Constant *PersonalityFn) const {
2769 return RISCV::X10;
2770}
2771
2772unsigned RISCVTargetLowering::getExceptionSelectorRegister(
2773 const Constant *PersonalityFn) const {
2774 return RISCV::X11;
2775}
2776
2777bool RISCVTargetLowering::shouldExtendTypeInLibCall(EVT Type) const {
2778 // Return false to suppress the unnecessary extensions if the LibCall
2779 // arguments or return value is f32 type for LP64 ABI.
2780 RISCVABI::ABI ABI = Subtarget.getTargetABI();
2781 if (ABI == RISCVABI::ABI_LP64 && (Type == MVT::f32))
2782 return false;
2783
2784 return true;
2785}

/build/llvm-toolchain-snapshot-10~svn374814/include/llvm/CodeGen/TargetLowering.h

1//===- llvm/CodeGen/TargetLowering.h - Target Lowering Info -----*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8///
9/// \file
10/// This file describes how to lower LLVM code to machine code. This has two
11/// main components:
12///
13/// 1. Which ValueTypes are natively supported by the target.
14/// 2. Which operations are supported for supported ValueTypes.
15/// 3. Cost thresholds for alternative implementations of certain operations.
16///
17/// In addition it has a few other components, like information about FP
18/// immediates.
19///
20//===----------------------------------------------------------------------===//
21
22#ifndef LLVM_CODEGEN_TARGETLOWERING_H
23#define LLVM_CODEGEN_TARGETLOWERING_H
24
25#include "llvm/ADT/APInt.h"
26#include "llvm/ADT/ArrayRef.h"
27#include "llvm/ADT/DenseMap.h"
28#include "llvm/ADT/STLExtras.h"
29#include "llvm/ADT/SmallVector.h"
30#include "llvm/ADT/StringRef.h"
31#include "llvm/Analysis/LegacyDivergenceAnalysis.h"
32#include "llvm/CodeGen/DAGCombine.h"
33#include "llvm/CodeGen/ISDOpcodes.h"
34#include "llvm/CodeGen/RuntimeLibcalls.h"
35#include "llvm/CodeGen/SelectionDAG.h"
36#include "llvm/CodeGen/SelectionDAGNodes.h"
37#include "llvm/CodeGen/TargetCallingConv.h"
38#include "llvm/CodeGen/ValueTypes.h"
39#include "llvm/IR/Attributes.h"
40#include "llvm/IR/CallSite.h"
41#include "llvm/IR/CallingConv.h"
42#include "llvm/IR/DataLayout.h"
43#include "llvm/IR/DerivedTypes.h"
44#include "llvm/IR/Function.h"
45#include "llvm/IR/IRBuilder.h"
46#include "llvm/IR/InlineAsm.h"
47#include "llvm/IR/Instruction.h"
48#include "llvm/IR/Instructions.h"
49#include "llvm/IR/Type.h"
50#include "llvm/MC/MCRegisterInfo.h"
51#include "llvm/Support/Alignment.h"
52#include "llvm/Support/AtomicOrdering.h"
53#include "llvm/Support/Casting.h"
54#include "llvm/Support/ErrorHandling.h"
55#include "llvm/Support/MachineValueType.h"
56#include "llvm/Target/TargetMachine.h"
57#include <algorithm>
58#include <cassert>
59#include <climits>
60#include <cstdint>
61#include <iterator>
62#include <map>
63#include <string>
64#include <utility>
65#include <vector>
66
67namespace llvm {
68
69class BranchProbability;
70class CCState;
71class CCValAssign;
72class Constant;
73class FastISel;
74class FunctionLoweringInfo;
75class GlobalValue;
76class GISelKnownBits;
77class IntrinsicInst;
78struct KnownBits;
79class LLVMContext;
80class MachineBasicBlock;
81class MachineFunction;
82class MachineInstr;
83class MachineJumpTableInfo;
84class MachineLoop;
85class MachineRegisterInfo;
86class MCContext;
87class MCExpr;
88class Module;
89class TargetRegisterClass;
90class TargetLibraryInfo;
91class TargetRegisterInfo;
92class Value;
93
94namespace Sched {
95
96 enum Preference {
97 None, // No preference
98 Source, // Follow source order.
99 RegPressure, // Scheduling for lowest register pressure.
100 Hybrid, // Scheduling for both latency and register pressure.
101 ILP, // Scheduling for ILP in low register pressure mode.
102 VLIW // Scheduling for VLIW targets.
103 };
104
105} // end namespace Sched
106
107/// This base class for TargetLowering contains the SelectionDAG-independent
108/// parts that can be used from the rest of CodeGen.
109class TargetLoweringBase {
110public:
111 /// This enum indicates whether operations are valid for a target, and if not,
112 /// what action should be used to make them valid.
113 enum LegalizeAction : uint8_t {
114 Legal, // The target natively supports this operation.
115 Promote, // This operation should be executed in a larger type.
116 Expand, // Try to expand this to other ops, otherwise use a libcall.
117 LibCall, // Don't try to expand this to other ops, always use a libcall.
118 Custom // Use the LowerOperation hook to implement custom lowering.
119 };
120
121 /// This enum indicates whether a types are legal for a target, and if not,
122 /// what action should be used to make them valid.
123 enum LegalizeTypeAction : uint8_t {
124 TypeLegal, // The target natively supports this type.
125 TypePromoteInteger, // Replace this integer with a larger one.
126 TypeExpandInteger, // Split this integer into two of half the size.
127 TypeSoftenFloat, // Convert this float to a same size integer type.
128 TypeExpandFloat, // Split this float into two of half the size.
129 TypeScalarizeVector, // Replace this one-element vector with its element.
130 TypeSplitVector, // Split this vector into two of half the size.
131 TypeWidenVector, // This vector should be widened into a larger vector.
132 TypePromoteFloat // Replace this float with a larger one.
133 };
134
135 /// LegalizeKind holds the legalization kind that needs to happen to EVT
136 /// in order to type-legalize it.
137 using LegalizeKind = std::pair<LegalizeTypeAction, EVT>;
138
139 /// Enum that describes how the target represents true/false values.
140 enum BooleanContent {
141 UndefinedBooleanContent, // Only bit 0 counts, the rest can hold garbage.
142 ZeroOrOneBooleanContent, // All bits zero except for bit 0.
143 ZeroOrNegativeOneBooleanContent // All bits equal to bit 0.
144 };
145
146 /// Enum that describes what type of support for selects the target has.
147 enum SelectSupportKind {
148 ScalarValSelect, // The target supports scalar selects (ex: cmov).
149 ScalarCondVectorVal, // The target supports selects with a scalar condition
150 // and vector values (ex: cmov).
151 VectorMaskSelect // The target supports vector selects with a vector
152 // mask (ex: x86 blends).
153 };
154
155 /// Enum that specifies what an atomic load/AtomicRMWInst is expanded
156 /// to, if at all. Exists because different targets have different levels of
157 /// support for these atomic instructions, and also have different options
158 /// w.r.t. what they should expand to.
159 enum class AtomicExpansionKind {
160 None, // Don't expand the instruction.
161 LLSC, // Expand the instruction into loadlinked/storeconditional; used
162 // by ARM/AArch64.
163 LLOnly, // Expand the (load) instruction into just a load-linked, which has
164 // greater atomic guarantees than a normal load.
165 CmpXChg, // Expand the instruction into cmpxchg; used by at least X86.
166 MaskedIntrinsic, // Use a target-specific intrinsic for the LL/SC loop.
167 };
168
169 /// Enum that specifies when a multiplication should be expanded.
170 enum class MulExpansionKind {
171 Always, // Always expand the instruction.
172 OnlyLegalOrCustom, // Only expand when the resulting instructions are legal
173 // or custom.
174 };
175
176 class ArgListEntry {
177 public:
178 Value *Val = nullptr;
179 SDValue Node = SDValue();
180 Type *Ty = nullptr;
181 bool IsSExt : 1;
182 bool IsZExt : 1;
183 bool IsInReg : 1;
184 bool IsSRet : 1;
185 bool IsNest : 1;
186 bool IsByVal : 1;
187 bool IsInAlloca : 1;
188 bool IsReturned : 1;
189 bool IsSwiftSelf : 1;
190 bool IsSwiftError : 1;
191 uint16_t Alignment = 0;
192 Type *ByValType = nullptr;
193
194 ArgListEntry()
195 : IsSExt(false), IsZExt(false), IsInReg(false), IsSRet(false),
196 IsNest(false), IsByVal(false), IsInAlloca(false), IsReturned(false),
197 IsSwiftSelf(false), IsSwiftError(false) {}
198
199 void setAttributes(const CallBase *Call, unsigned ArgIdx);
200
201 void setAttributes(ImmutableCallSite *CS, unsigned ArgIdx) {
202 return setAttributes(cast<CallBase>(CS->getInstruction()), ArgIdx);
203 }
204 };
205 using ArgListTy = std::vector<ArgListEntry>;
206
207 virtual void markLibCallAttributes(MachineFunction *MF, unsigned CC,
208 ArgListTy &Args) const {};
209
210 static ISD::NodeType getExtendForContent(BooleanContent Content) {
211 switch (Content) {
212 case UndefinedBooleanContent:
213 // Extend by adding rubbish bits.
214 return ISD::ANY_EXTEND;
215 case ZeroOrOneBooleanContent:
216 // Extend by adding zero bits.
217 return ISD::ZERO_EXTEND;
218 case ZeroOrNegativeOneBooleanContent:
219 // Extend by copying the sign bit.
220 return ISD::SIGN_EXTEND;
221 }
222 llvm_unreachable("Invalid content kind")::llvm::llvm_unreachable_internal("Invalid content kind", "/build/llvm-toolchain-snapshot-10~svn374814/include/llvm/CodeGen/TargetLowering.h"
, 222)
;
223 }
224
225 /// NOTE: The TargetMachine owns TLOF.
226 explicit TargetLoweringBase(const TargetMachine &TM);
227 TargetLoweringBase(const TargetLoweringBase &) = delete;
228 TargetLoweringBase &operator=(const TargetLoweringBase &) = delete;
229 virtual ~TargetLoweringBase() = default;
230
231protected:
232 /// Initialize all of the actions to default values.
233 void initActions();
234
235public:
236 const TargetMachine &getTargetMachine() const { return TM; }
237
238 virtual bool useSoftFloat() const { return false; }
239
240 /// Return the pointer type for the given address space, defaults to
241 /// the pointer type from the data layout.
242 /// FIXME: The default needs to be removed once all the code is updated.
243 virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS = 0) const {
244 return MVT::getIntegerVT(DL.getPointerSizeInBits(AS));
245 }
246
247 /// Return the in-memory pointer type for the given address space, defaults to
248 /// the pointer type from the data layout. FIXME: The default needs to be
249 /// removed once all the code is updated.
250 MVT getPointerMemTy(const DataLayout &DL, uint32_t AS = 0) const {
251 return MVT::getIntegerVT(DL.getPointerSizeInBits(AS));
252 }
253
254 /// Return the type for frame index, which is determined by
255 /// the alloca address space specified through the data layout.
256 MVT getFrameIndexTy(const DataLayout &DL) const {
257 return getPointerTy(DL, DL.getAllocaAddrSpace());
258 }
259
260 /// Return the type for operands of fence.
261 /// TODO: Let fence operands be of i32 type and remove this.
262 virtual MVT getFenceOperandTy(const DataLayout &DL) const {
263 return getPointerTy(DL);
264 }
265
266 /// EVT is not used in-tree, but is used by out-of-tree target.
267 /// A documentation for this function would be nice...
268 virtual MVT getScalarShiftAmountTy(const DataLayout &, EVT) const;
269
270 EVT getShiftAmountTy(EVT LHSTy, const DataLayout &DL,
271 bool LegalTypes = true) const;
272
273 /// Returns the type to be used for the index operand of:
274 /// ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT,
275 /// ISD::INSERT_SUBVECTOR, and ISD::EXTRACT_SUBVECTOR
276 virtual MVT getVectorIdxTy(const DataLayout &DL) const {
277 return getPointerTy(DL);
278 }
279
280 virtual bool isSelectSupported(SelectSupportKind /*kind*/) const {
281 return true;
282 }
283
284 /// Return true if it is profitable to convert a select of FP constants into
285 /// a constant pool load whose address depends on the select condition. The
286 /// parameter may be used to differentiate a select with FP compare from
287 /// integer compare.
288 virtual bool reduceSelectOfFPConstantLoads(EVT CmpOpVT) const {
289 return true;
290 }
291
292 /// Return true if multiple condition registers are available.
293 bool hasMultipleConditionRegisters() const {
294 return HasMultipleConditionRegisters;
295 }
296
297 /// Return true if the target has BitExtract instructions.
298 bool hasExtractBitsInsn() const { return HasExtractBitsInsn; }
299
300 /// Return the preferred vector type legalization action.
301 virtual TargetLoweringBase::LegalizeTypeAction
302 getPreferredVectorAction(MVT VT) const {
303 // The default action for one element vectors is to scalarize
304 if (VT.getVectorNumElements() == 1)
305 return TypeScalarizeVector;
306 // The default action for an odd-width vector is to widen.
307 if (!VT.isPow2VectorType())
308 return TypeWidenVector;
309 // The default action for other vectors is to promote
310 return TypePromoteInteger;
311 }
312
313 // There are two general methods for expanding a BUILD_VECTOR node:
314 // 1. Use SCALAR_TO_VECTOR on the defined scalar values and then shuffle
315 // them together.
316 // 2. Build the vector on the stack and then load it.
317 // If this function returns true, then method (1) will be used, subject to
318 // the constraint that all of the necessary shuffles are legal (as determined
319 // by isShuffleMaskLegal). If this function returns false, then method (2) is
320 // always used. The vector type, and the number of defined values, are
321 // provided.
322 virtual bool
323 shouldExpandBuildVectorWithShuffles(EVT /* VT */,
324 unsigned DefinedValues) const {
325 return DefinedValues < 3;
326 }
327
328 /// Return true if integer divide is usually cheaper than a sequence of
329 /// several shifts, adds, and multiplies for this target.
330 /// The definition of "cheaper" may depend on whether we're optimizing
331 /// for speed or for size.
332 virtual bool isIntDivCheap(EVT VT, AttributeList Attr) const { return false; }
333
334 /// Return true if the target can handle a standalone remainder operation.
335 virtual bool hasStandaloneRem(EVT VT) const {
336 return true;
337 }
338
339 /// Return true if SQRT(X) shouldn't be replaced with X*RSQRT(X).
340 virtual bool isFsqrtCheap(SDValue X, SelectionDAG &DAG) const {
341 // Default behavior is to replace SQRT(X) with X*RSQRT(X).
342 return false;
343 }
344
345 /// Reciprocal estimate status values used by the functions below.
346 enum ReciprocalEstimate : int {
347 Unspecified = -1,
348 Disabled = 0,
349 Enabled = 1
350 };
351
352 /// Return a ReciprocalEstimate enum value for a square root of the given type
353 /// based on the function's attributes. If the operation is not overridden by
354 /// the function's attributes, "Unspecified" is returned and target defaults
355 /// are expected to be used for instruction selection.
356 int getRecipEstimateSqrtEnabled(EVT VT, MachineFunction &MF) const;
357
358 /// Return a ReciprocalEstimate enum value for a division of the given type
359 /// based on the function's attributes. If the operation is not overridden by
360 /// the function's attributes, "Unspecified" is returned and target defaults
361 /// are expected to be used for instruction selection.
362 int getRecipEstimateDivEnabled(EVT VT, MachineFunction &MF) const;
363
364 /// Return the refinement step count for a square root of the given type based
365 /// on the function's attributes. If the operation is not overridden by
366 /// the function's attributes, "Unspecified" is returned and target defaults
367 /// are expected to be used for instruction selection.
368 int getSqrtRefinementSteps(EVT VT, MachineFunction &MF) const;
369
370 /// Return the refinement step count for a division of the given type based
371 /// on the function's attributes. If the operation is not overridden by
372 /// the function's attributes, "Unspecified" is returned and target defaults
373 /// are expected to be used for instruction selection.
374 int getDivRefinementSteps(EVT VT, MachineFunction &MF) const;
375
376 /// Returns true if target has indicated at least one type should be bypassed.
377 bool isSlowDivBypassed() const { return !BypassSlowDivWidths.empty(); }
378
379 /// Returns map of slow types for division or remainder with corresponding
380 /// fast types
381 const DenseMap<unsigned int, unsigned int> &getBypassSlowDivWidths() const {
382 return BypassSlowDivWidths;
383 }
384
385 /// Return true if Flow Control is an expensive operation that should be
386 /// avoided.
387 bool isJumpExpensive() const { return JumpIsExpensive; }
388
389 /// Return true if selects are only cheaper than branches if the branch is
390 /// unlikely to be predicted right.
391 bool isPredictableSelectExpensive() const {
392 return PredictableSelectIsExpensive;
393 }
394
395 /// If a branch or a select condition is skewed in one direction by more than
396 /// this factor, it is very likely to be predicted correctly.
397 virtual BranchProbability getPredictableBranchThreshold() const;
398
399 /// Return true if the following transform is beneficial:
400 /// fold (conv (load x)) -> (load (conv*)x)
401 /// On architectures that don't natively support some vector loads
402 /// efficiently, casting the load to a smaller vector of larger types and
403 /// loading is more efficient, however, this can be undone by optimizations in
404 /// dag combiner.
405 virtual bool isLoadBitCastBeneficial(EVT LoadVT, EVT BitcastVT,
406 const SelectionDAG &DAG,
407 const MachineMemOperand &MMO) const {
408 // Don't do if we could do an indexed load on the original type, but not on
409 // the new one.
410 if (!LoadVT.isSimple() || !BitcastVT.isSimple())
411 return true;
412
413 MVT LoadMVT = LoadVT.getSimpleVT();
414
415 // Don't bother doing this if it's just going to be promoted again later, as
416 // doing so might interfere with other combines.
417 if (getOperationAction(ISD::LOAD, LoadMVT) == Promote &&
418 getTypeToPromoteTo(ISD::LOAD, LoadMVT) == BitcastVT.getSimpleVT())
419 return false;
420
421 bool Fast = false;
422 return allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), BitcastVT,
423 MMO, &Fast) && Fast;
424 }
425
426 /// Return true if the following transform is beneficial:
427 /// (store (y (conv x)), y*)) -> (store x, (x*))
428 virtual bool isStoreBitCastBeneficial(EVT StoreVT, EVT BitcastVT,
429 const SelectionDAG &DAG,
430 const MachineMemOperand &MMO) const {
431 // Default to the same logic as loads.
432 return isLoadBitCastBeneficial(StoreVT, BitcastVT, DAG, MMO);
433 }
434
435 /// Return true if it is expected to be cheaper to do a store of a non-zero
436 /// vector constant with the given size and type for the address space than to
437 /// store the individual scalar element constants.
438 virtual bool storeOfVectorConstantIsCheap(EVT MemVT,
439 unsigned NumElem,
440 unsigned AddrSpace) const {
441 return false;
442 }
443
444 /// Allow store merging for the specified type after legalization in addition
445 /// to before legalization. This may transform stores that do not exist
446 /// earlier (for example, stores created from intrinsics).
447 virtual bool mergeStoresAfterLegalization(EVT MemVT) const {
448 return true;
449 }
450
451 /// Returns if it's reasonable to merge stores to MemVT size.
452 virtual bool canMergeStoresTo(unsigned AS, EVT MemVT,
453 const SelectionDAG &DAG) const {
454 return true;
455 }
456
457 /// Return true if it is cheap to speculate a call to intrinsic cttz.
458 virtual bool isCheapToSpeculateCttz() const {
459 return false;
460 }
461
462 /// Return true if it is cheap to speculate a call to intrinsic ctlz.
463 virtual bool isCheapToSpeculateCtlz() const {
464 return false;
465 }
466
467 /// Return true if ctlz instruction is fast.
468 virtual bool isCtlzFast() const {
469 return false;
470 }
471
472 /// Return true if it is safe to transform an integer-domain bitwise operation
473 /// into the equivalent floating-point operation. This should be set to true
474 /// if the target has IEEE-754-compliant fabs/fneg operations for the input
475 /// type.
476 virtual bool hasBitPreservingFPLogic(EVT VT) const {
477 return false;
478 }
479
480 /// Return true if it is cheaper to split the store of a merged int val
481 /// from a pair of smaller values into multiple stores.
482 virtual bool isMultiStoresCheaperThanBitsMerge(EVT LTy, EVT HTy) const {
483 return false;
484 }
485
486 /// Return if the target supports combining a
487 /// chain like:
488 /// \code
489 /// %andResult = and %val1, #mask
490 /// %icmpResult = icmp %andResult, 0
491 /// \endcode
492 /// into a single machine instruction of a form like:
493 /// \code
494 /// cc = test %register, #mask
495 /// \endcode
496 virtual bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const {
497 return false;
498 }
499
500 /// Use bitwise logic to make pairs of compares more efficient. For example:
501 /// and (seteq A, B), (seteq C, D) --> seteq (or (xor A, B), (xor C, D)), 0
502 /// This should be true when it takes more than one instruction to lower
503 /// setcc (cmp+set on x86 scalar), when bitwise ops are faster than logic on
504 /// condition bits (crand on PowerPC), and/or when reducing cmp+br is a win.
505 virtual bool convertSetCCLogicToBitwiseLogic(EVT VT) const {
506 return false;
507 }
508
509 /// Return the preferred operand type if the target has a quick way to compare
510 /// integer values of the given size. Assume that any legal integer type can
511 /// be compared efficiently. Targets may override this to allow illegal wide
512 /// types to return a vector type if there is support to compare that type.
513 virtual MVT hasFastEqualityCompare(unsigned NumBits) const {
514 MVT VT = MVT::getIntegerVT(NumBits);
515 return isTypeLegal(VT) ? VT : MVT::INVALID_SIMPLE_VALUE_TYPE;
516 }
517
518 /// Return true if the target should transform:
519 /// (X & Y) == Y ---> (~X & Y) == 0
520 /// (X & Y) != Y ---> (~X & Y) != 0
521 ///
522 /// This may be profitable if the target has a bitwise and-not operation that
523 /// sets comparison flags. A target may want to limit the transformation based
524 /// on the type of Y or if Y is a constant.
525 ///
526 /// Note that the transform will not occur if Y is known to be a power-of-2
527 /// because a mask and compare of a single bit can be handled by inverting the
528 /// predicate, for example:
529 /// (X & 8) == 8 ---> (X & 8) != 0
530 virtual bool hasAndNotCompare(SDValue Y) const {
531 return false;
532 }
533
534 /// Return true if the target has a bitwise and-not operation:
535 /// X = ~A & B
536 /// This can be used to simplify select or other instructions.
537 virtual bool hasAndNot(SDValue X) const {
538 // If the target has the more complex version of this operation, assume that
539 // it has this operation too.
540 return hasAndNotCompare(X);
541 }
542
543 /// Return true if the target has a bit-test instruction:
544 /// (X & (1 << Y)) ==/!= 0
545 /// This knowledge can be used to prevent breaking the pattern,
546 /// or creating it if it could be recognized.
547 virtual bool hasBitTest(SDValue X, SDValue Y) const { return false; }
548
549 /// There are two ways to clear extreme bits (either low or high):
550 /// Mask: x & (-1 << y) (the instcombine canonical form)
551 /// Shifts: x >> y << y
552 /// Return true if the variant with 2 variable shifts is preferred.
553 /// Return false if there is no preference.
554 virtual bool shouldFoldMaskToVariableShiftPair(SDValue X) const {
555 // By default, let's assume that no one prefers shifts.
556 return false;
557 }
558
559 /// Return true if it is profitable to fold a pair of shifts into a mask.
560 /// This is usually true on most targets. But some targets, like Thumb1,
561 /// have immediate shift instructions, but no immediate "and" instruction;
562 /// this makes the fold unprofitable.
563 virtual bool shouldFoldConstantShiftPairToMask(const SDNode *N,
564 CombineLevel Level) const {
565 return true;
566 }
567
568 /// Should we tranform the IR-optimal check for whether given truncation
569 /// down into KeptBits would be truncating or not:
570 /// (add %x, (1 << (KeptBits-1))) srccond (1 << KeptBits)
571 /// Into it's more traditional form:
572 /// ((%x << C) a>> C) dstcond %x
573 /// Return true if we should transform.
574 /// Return false if there is no preference.
575 virtual bool shouldTransformSignedTruncationCheck(EVT XVT,
576 unsigned KeptBits) const {
577 // By default, let's assume that no one prefers shifts.
578 return false;
579 }
580
581 /// Given the pattern
582 /// (X & (C l>>/<< Y)) ==/!= 0
583 /// return true if it should be transformed into:
584 /// ((X <</l>> Y) & C) ==/!= 0
585 /// WARNING: if 'X' is a constant, the fold may deadlock!
586 /// FIXME: we could avoid passing XC, but we can't use isConstOrConstSplat()
587 /// here because it can end up being not linked in.
588 virtual bool shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd(
589 SDValue X, ConstantSDNode *XC, ConstantSDNode *CC, SDValue Y,
590 unsigned OldShiftOpcode, unsigned NewShiftOpcode,
591 SelectionDAG &DAG) const {
592 if (hasBitTest(X, Y)) {
593 // One interesting pattern that we'd want to form is 'bit test':
594 // ((1 << Y) & C) ==/!= 0
595 // But we also need to be careful not to try to reverse that fold.
596
597 // Is this '1 << Y' ?
598 if (OldShiftOpcode == ISD::SHL && CC->isOne())
599 return false; // Keep the 'bit test' pattern.
600
601 // Will it be '1 << Y' after the transform ?
602 if (XC && NewShiftOpcode == ISD::SHL && XC->isOne())
603 return true; // Do form the 'bit test' pattern.
604 }
605
606 // If 'X' is a constant, and we transform, then we will immediately
607 // try to undo the fold, thus causing endless combine loop.
608 // So by default, let's assume everyone prefers the fold
609 // iff 'X' is not a constant.
610 return !XC;
611 }
612
613 /// These two forms are equivalent:
614 /// sub %y, (xor %x, -1)
615 /// add (add %x, 1), %y
616 /// The variant with two add's is IR-canonical.
617 /// Some targets may prefer one to the other.
618 virtual bool preferIncOfAddToSubOfNot(EVT VT) const {
619 // By default, let's assume that everyone prefers the form with two add's.
620 return true;
621 }
622
623 /// Return true if the target wants to use the optimization that
624 /// turns ext(promotableInst1(...(promotableInstN(load)))) into
625 /// promotedInst1(...(promotedInstN(ext(load)))).
626 bool enableExtLdPromotion() const { return EnableExtLdPromotion; }
627
628 /// Return true if the target can combine store(extractelement VectorTy,
629 /// Idx).
630 /// \p Cost[out] gives the cost of that transformation when this is true.
631 virtual bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
632 unsigned &Cost) const {
633 return false;
634 }
635
636 /// Return true if inserting a scalar into a variable element of an undef
637 /// vector is more efficiently handled by splatting the scalar instead.
638 virtual bool shouldSplatInsEltVarIndex(EVT) const {
639 return false;
640 }
641
642 /// Return true if target always beneficiates from combining into FMA for a
643 /// given value type. This must typically return false on targets where FMA
644 /// takes more cycles to execute than FADD.
645 virtual bool enableAggressiveFMAFusion(EVT VT) const {
646 return false;
647 }
648
649 /// Return the ValueType of the result of SETCC operations.
650 virtual EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
651 EVT VT) const;
652
653 /// Return the ValueType for comparison libcalls. Comparions libcalls include
654 /// floating point comparion calls, and Ordered/Unordered check calls on
655 /// floating point numbers.
656 virtual
657 MVT::SimpleValueType getCmpLibcallReturnType() const;
658
659 /// For targets without i1 registers, this gives the nature of the high-bits
660 /// of boolean values held in types wider than i1.
661 ///
662 /// "Boolean values" are special true/false values produced by nodes like
663 /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND.
664 /// Not to be confused with general values promoted from i1. Some cpus
665 /// distinguish between vectors of boolean and scalars; the isVec parameter
666 /// selects between the two kinds. For example on X86 a scalar boolean should
667 /// be zero extended from i1, while the elements of a vector of booleans
668 /// should be sign extended from i1.
669 ///
670 /// Some cpus also treat floating point types the same way as they treat
671 /// vectors instead of the way they treat scalars.
672 BooleanContent getBooleanContents(bool isVec, bool isFloat) const {
673 if (isVec)
674 return BooleanVectorContents;
675 return isFloat ? BooleanFloatContents : BooleanContents;
676 }
677
678 BooleanContent getBooleanContents(EVT Type) const {
679 return getBooleanContents(Type.isVector(), Type.isFloatingPoint());
680 }
681
682 /// Return target scheduling preference.
683 Sched::Preference getSchedulingPreference() const {
684 return SchedPreferenceInfo;
685 }
686
687 /// Some scheduler, e.g. hybrid, can switch to different scheduling heuristics
688 /// for different nodes. This function returns the preference (or none) for
689 /// the given node.
690 virtual Sched::Preference getSchedulingPreference(SDNode *) const {
691 return Sched::None;
692 }
693
694 /// Return the register class that should be used for the specified value
695 /// type.
696 virtual const TargetRegisterClass *getRegClassFor(MVT VT, bool isDivergent = false) const {
697 (void)isDivergent;
698 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
699 assert(RC && "This value type is not natively supported!")((RC && "This value type is not natively supported!")
? static_cast<void> (0) : __assert_fail ("RC && \"This value type is not natively supported!\""
, "/build/llvm-toolchain-snapshot-10~svn374814/include/llvm/CodeGen/TargetLowering.h"
, 699, __PRETTY_FUNCTION__))
;
700 return RC;
701 }
702
703 /// Allows target to decide about the register class of the
704 /// specific value that is live outside the defining block.
705 /// Returns true if the value needs uniform register class.
706 virtual bool requiresUniformRegister(MachineFunction &MF,
707 const Value *) const {
708 return false;
709 }
710
711 /// Return the 'representative' register class for the specified value
712 /// type.
713 ///
714 /// The 'representative' register class is the largest legal super-reg
715 /// register class for the register class of the value type. For example, on
716 /// i386 the rep register class for i8, i16, and i32 are GR32; while the rep
717 /// register class is GR64 on x86_64.
718 virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const {
719 const TargetRegisterClass *RC = RepRegClassForVT[VT.SimpleTy];
720 return RC;
721 }
722
723 /// Return the cost of the 'representative' register class for the specified
724 /// value type.
725 virtual uint8_t getRepRegClassCostFor(MVT VT) const {
726 return RepRegClassCostForVT[VT.SimpleTy];
727 }
728
729 /// Return true if SHIFT instructions should be expanded to SHIFT_PARTS
730 /// instructions, and false if a library call is preferred (e.g for code-size
731 /// reasons).
732 virtual bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const {
733 return true;
734 }
735
736 /// Return true if the target has native support for the specified value type.
737 /// This means that it has a register that directly holds it without
738 /// promotions or expansions.
739 bool isTypeLegal(EVT VT) const {
740 assert(!VT.isSimple() ||((!VT.isSimple() || (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof
(RegClassForVT)) ? static_cast<void> (0) : __assert_fail
("!VT.isSimple() || (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT)"
, "/build/llvm-toolchain-snapshot-10~svn374814/include/llvm/CodeGen/TargetLowering.h"
, 741, __PRETTY_FUNCTION__))
741 (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT))((!VT.isSimple() || (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof
(RegClassForVT)) ? static_cast<void> (0) : __assert_fail
("!VT.isSimple() || (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT)"
, "/build/llvm-toolchain-snapshot-10~svn374814/include/llvm/CodeGen/TargetLowering.h"
, 741, __PRETTY_FUNCTION__))
;
742 return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != nullptr;
743 }
744
745 class ValueTypeActionImpl {
746 /// ValueTypeActions - For each value type, keep a LegalizeTypeAction enum
747 /// that indicates how instruction selection should deal with the type.
748 LegalizeTypeAction ValueTypeActions[MVT::LAST_VALUETYPE];
749
750 public:
751 ValueTypeActionImpl() {
752 std::fill(std::begin(ValueTypeActions), std::end(ValueTypeActions),
753 TypeLegal);
754 }
755
756 LegalizeTypeAction getTypeAction(MVT VT) const {
757 return ValueTypeActions[VT.SimpleTy];
758 }
759
760 void setTypeAction(MVT VT, LegalizeTypeAction Action) {
761 ValueTypeActions[VT.SimpleTy] = Action;
762 }
763 };
764
765 const ValueTypeActionImpl &getValueTypeActions() const {
766 return ValueTypeActions;
767 }
768
769 /// Return how we should legalize values of this type, either it is already
770 /// legal (return 'Legal') or we need to promote it to a larger type (return
771 /// 'Promote'), or we need to expand it into multiple registers of smaller
772 /// integer type (return 'Expand'). 'Custom' is not an option.
773 LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const {
774 return getTypeConversion(Context, VT).first;
775 }
776 LegalizeTypeAction getTypeAction(MVT VT) const {
777 return ValueTypeActions.getTypeAction(VT);
778 }
779
780 /// For types supported by the target, this is an identity function. For
781 /// types that must be promoted to larger types, this returns the larger type
782 /// to promote to. For integer types that are larger than the largest integer
783 /// register, this contains one step in the expansion to get to the smaller
784 /// register. For illegal floating point types, this returns the integer type
785 /// to transform to.
786 EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const {
787 return getTypeConversion(Context, VT).second;
788 }
789
790 /// For types supported by the target, this is an identity function. For
791 /// types that must be expanded (i.e. integer types that are larger than the
792 /// largest integer register or illegal floating point types), this returns
793 /// the largest legal type it will be expanded to.
794 EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const {
795 assert(!VT.isVector())((!VT.isVector()) ? static_cast<void> (0) : __assert_fail
("!VT.isVector()", "/build/llvm-toolchain-snapshot-10~svn374814/include/llvm/CodeGen/TargetLowering.h"
, 795, __PRETTY_FUNCTION__))
;
796 while (true) {
797 switch (getTypeAction(Context, VT)) {
798 case TypeLegal:
799 return VT;
800 case TypeExpandInteger:
801 VT = getTypeToTransformTo(Context, VT);
802 break;
803 default:
804 llvm_unreachable("Type is not legal nor is it to be expanded!")::llvm::llvm_unreachable_internal("Type is not legal nor is it to be expanded!"
, "/build/llvm-toolchain-snapshot-10~svn374814/include/llvm/CodeGen/TargetLowering.h"
, 804)
;
805 }
806 }
807 }
808
809 /// Vector types are broken down into some number of legal first class types.
810 /// For example, EVT::v8f32 maps to 2 EVT::v4f32 with Altivec or SSE1, or 8
811 /// promoted EVT::f64 values with the X86 FP stack. Similarly, EVT::v2i64
812 /// turns into 4 EVT::i32 values with both PPC and X86.
813 ///
814 /// This method returns the number of registers needed, and the VT for each
815 /// register. It also returns the VT and quantity of the intermediate values
816 /// before they are promoted/expanded.
817 unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
818 EVT &IntermediateVT,
819 unsigned &NumIntermediates,
820 MVT &RegisterVT) const;
821
822 /// Certain targets such as MIPS require that some types such as vectors are
823 /// always broken down into scalars in some contexts. This occurs even if the
824 /// vector type is legal.
825 virtual unsigned getVectorTypeBreakdownForCallingConv(
826 LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
827 unsigned &NumIntermediates, MVT &RegisterVT) const {
828 return getVectorTypeBreakdown(Context, VT, IntermediateVT, NumIntermediates,
829 RegisterVT);
830 }
831
832 struct IntrinsicInfo {
833 unsigned opc = 0; // target opcode
834 EVT memVT; // memory VT
835
836 // value representing memory location
837 PointerUnion<const Value *, const PseudoSourceValue *> ptrVal;
838
839 int offset = 0; // offset off of ptrVal
840 uint64_t size = 0; // the size of the memory location
841 // (taken from memVT if zero)
842 MaybeAlign align = Align::None(); // alignment
843
844 MachineMemOperand::Flags flags = MachineMemOperand::MONone;
845 IntrinsicInfo() = default;
846 };
847
848 /// Given an intrinsic, checks if on the target the intrinsic will need to map
849 /// to a MemIntrinsicNode (touches memory). If this is the case, it returns
850 /// true and store the intrinsic information into the IntrinsicInfo that was
851 /// passed to the function.
852 virtual bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &,
853 MachineFunction &,
854 unsigned /*Intrinsic*/) const {
855 return false;
856 }
857
858 /// Returns true if the target can instruction select the specified FP
859 /// immediate natively. If false, the legalizer will materialize the FP
860 /// immediate as a load from a constant pool.
861 virtual bool isFPImmLegal(const APFloat & /*Imm*/, EVT /*VT*/,
862 bool ForCodeSize = false) const {
863 return false;
864 }
865
866 /// Targets can use this to indicate that they only support *some*
867 /// VECTOR_SHUFFLE operations, those with specific masks. By default, if a
868 /// target supports the VECTOR_SHUFFLE node, all mask values are assumed to be
869 /// legal.
870 virtual bool isShuffleMaskLegal(ArrayRef<int> /*Mask*/, EVT /*VT*/) const {
871 return true;
872 }
873
874 /// Returns true if the operation can trap for the value type.
875 ///
876 /// VT must be a legal type. By default, we optimistically assume most
877 /// operations don't trap except for integer divide and remainder.
878 virtual bool canOpTrap(unsigned Op, EVT VT) const;
879
880 /// Similar to isShuffleMaskLegal. Targets can use this to indicate if there
881 /// is a suitable VECTOR_SHUFFLE that can be used to replace a VAND with a
882 /// constant pool entry.
883 virtual bool isVectorClearMaskLegal(ArrayRef<int> /*Mask*/,
884 EVT /*VT*/) const {
885 return false;
886 }
887
888 /// Return how this operation should be treated: either it is legal, needs to
889 /// be promoted to a larger size, needs to be expanded to some other code
890 /// sequence, or the target has a custom expander for it.
891 LegalizeAction getOperationAction(unsigned Op, EVT VT) const {
892 if (VT.isExtended()) return Expand;
893 // If a target-specific SDNode requires legalization, require the target
894 // to provide custom legalization for it.
895 if (Op >= array_lengthof(OpActions[0])) return Custom;
896 return OpActions[(unsigned)VT.getSimpleVT().SimpleTy][Op];
897 }
898
899 /// Custom method defined by each target to indicate if an operation which
900 /// may require a scale is supported natively by the target.
901 /// If not, the operation is illegal.
902 virtual bool isSupportedFixedPointOperation(unsigned Op, EVT VT,
903 unsigned Scale) const {
904 return false;
905 }
906
907 /// Some fixed point operations may be natively supported by the target but
908 /// only for specific scales. This method allows for checking
909 /// if the width is supported by the target for a given operation that may
910 /// depend on scale.
911 LegalizeAction getFixedPointOperationAction(unsigned Op, EVT VT,
912 unsigned Scale) const {
913 auto Action = getOperationAction(Op, VT);
914 if (Action != Legal)
915 return Action;
916
917 // This operation is supported in this type but may only work on specific
918 // scales.
919 bool Supported;
920 switch (Op) {
921 default:
922 llvm_unreachable("Unexpected fixed point operation.")::llvm::llvm_unreachable_internal("Unexpected fixed point operation."
, "/build/llvm-toolchain-snapshot-10~svn374814/include/llvm/CodeGen/TargetLowering.h"
, 922)
;
923 case ISD::SMULFIX:
924 case ISD::SMULFIXSAT:
925 case ISD::UMULFIX:
926 case ISD::UMULFIXSAT:
927 Supported = isSupportedFixedPointOperation(Op, VT, Scale);
928 break;
929 }
930
931 return Supported ? Action : Expand;
932 }
933
934 // If Op is a strict floating-point operation, return the result
935 // of getOperationAction for the equivalent non-strict operation.
936 LegalizeAction getStrictFPOperationAction(unsigned Op, EVT VT) const {
937 unsigned EqOpc;
938 switch (Op) {
939 default: llvm_unreachable("Unexpected FP pseudo-opcode")::llvm::llvm_unreachable_internal("Unexpected FP pseudo-opcode"
, "/build/llvm-toolchain-snapshot-10~svn374814/include/llvm/CodeGen/TargetLowering.h"
, 939)
;
940 case ISD::STRICT_FADD: EqOpc = ISD::FADD; break;
941 case ISD::STRICT_FSUB: EqOpc = ISD::FSUB; break;
942 case ISD::STRICT_FMUL: EqOpc = ISD::FMUL; break;
943 case ISD::STRICT_FDIV: EqOpc = ISD::FDIV; break;
944 case ISD::STRICT_FREM: EqOpc = ISD::FREM; break;
945 case ISD::STRICT_FSQRT: EqOpc = ISD::FSQRT; break;
946 case ISD::STRICT_FPOW: EqOpc = ISD::FPOW; break;
947 case ISD::STRICT_FPOWI: EqOpc = ISD::FPOWI; break;
948 case ISD::STRICT_FMA: EqOpc = ISD::FMA; break;
949 case ISD::STRICT_FSIN: EqOpc = ISD::FSIN; break;
950 case ISD::STRICT_FCOS: EqOpc = ISD::FCOS; break;
951 case ISD::STRICT_FEXP: EqOpc = ISD::FEXP; break;
952 case ISD::STRICT_FEXP2: EqOpc = ISD::FEXP2; break;
953 case ISD::STRICT_FLOG: EqOpc = ISD::FLOG; break;
954 case ISD::STRICT_FLOG10: EqOpc = ISD::FLOG10; break;
955 case ISD::STRICT_FLOG2: EqOpc = ISD::FLOG2; break;
956 case ISD::STRICT_LRINT: EqOpc = ISD::LRINT; break;
957 case ISD::STRICT_LLRINT: EqOpc = ISD::LLRINT; break;
958 case ISD::STRICT_FRINT: EqOpc = ISD::FRINT; break;
959 case ISD::STRICT_FNEARBYINT: EqOpc = ISD::FNEARBYINT; break;
960 case ISD::STRICT_FMAXNUM: EqOpc = ISD::FMAXNUM; break;
961 case ISD::STRICT_FMINNUM: EqOpc = ISD::FMINNUM; break;
962 case ISD::STRICT_FCEIL: EqOpc = ISD::FCEIL; break;
963 case ISD::STRICT_FFLOOR: EqOpc = ISD::FFLOOR; break;
964 case ISD::STRICT_LROUND: EqOpc = ISD::LROUND; break;
965 case ISD::STRICT_LLROUND: EqOpc = ISD::LLROUND; break;
966 case ISD::STRICT_FROUND: EqOpc = ISD::FROUND; break;
967 case ISD::STRICT_FTRUNC: EqOpc = ISD::FTRUNC; break;
968 case ISD::STRICT_FP_TO_SINT: EqOpc = ISD::FP_TO_SINT; break;
969 case ISD::STRICT_FP_TO_UINT: EqOpc = ISD::FP_TO_UINT; break;
970 case ISD::STRICT_FP_ROUND: EqOpc = ISD::FP_ROUND; break;
971 case ISD::STRICT_FP_EXTEND: EqOpc = ISD::FP_EXTEND; break;
972 }
973
974 return getOperationAction(EqOpc, VT);
975 }
976
977 /// Return true if the specified operation is legal on this target or can be
978 /// made legal with custom lowering. This is used to help guide high-level
979 /// lowering decisions.
980 bool isOperationLegalOrCustom(unsigned Op, EVT VT) const {
981 return (VT == MVT::Other || isTypeLegal(VT)) &&
982 (getOperationAction(Op, VT) == Legal ||
983 getOperationAction(Op, VT) == Custom);
984 }
985
986 /// Return true if the specified operation is legal on this target or can be
987 /// made legal using promotion. This is used to help guide high-level lowering
988 /// decisions.
989 bool isOperationLegalOrPromote(unsigned Op, EVT VT) const {
990 return (VT == MVT::Other || isTypeLegal(VT)) &&
991 (getOperationAction(Op, VT) == Legal ||
992 getOperationAction(Op, VT) == Promote);
993 }
994
995 /// Return true if the specified operation is legal on this target or can be
996 /// made legal with custom lowering or using promotion. This is used to help
997 /// guide high-level lowering decisions.
998 bool isOperationLegalOrCustomOrPromote(unsigned Op, EVT VT) const {
999 return (VT == MVT::Other || isTypeLegal(VT)) &&
1000 (getOperationAction(Op, VT) == Legal ||
1001 getOperationAction(Op, VT) == Custom ||
1002 getOperationAction(Op, VT) == Promote);
1003 }
1004
1005 /// Return true if the operation uses custom lowering, regardless of whether
1006 /// the type is legal or not.
1007 bool isOperationCustom(unsigned Op, EVT VT) const {
1008 return getOperationAction(Op, VT) == Custom;
1009 }
1010
1011 /// Return true if lowering to a jump table is allowed.
1012 virtual bool areJTsAllowed(const Function *Fn) const {
1013 if (Fn->getFnAttribute("no-jump-tables").getValueAsString() == "true")
1014 return false;
1015
1016 return isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
1017 isOperationLegalOrCustom(ISD::BRIND, MVT::Other);
1018 }
1019
1020 /// Check whether the range [Low,High] fits in a machine word.
1021 bool rangeFitsInWord(const APInt &Low, const APInt &High,
1022 const DataLayout &DL) const {
1023 // FIXME: Using the pointer type doesn't seem ideal.
1024 uint64_t BW = DL.getIndexSizeInBits(0u);
1025 uint64_t Range = (High - Low).getLimitedValue(UINT64_MAX(18446744073709551615UL) - 1) + 1;
1026 return Range <= BW;
1027 }
1028
1029 /// Return true if lowering to a jump table is suitable for a set of case
1030 /// clusters which may contain \p NumCases cases, \p Range range of values.
1031 virtual bool isSuitableForJumpTable(const SwitchInst *SI, uint64_t NumCases,
1032 uint64_t Range) const {
1033 // FIXME: This function check the maximum table size and density, but the
1034 // minimum size is not checked. It would be nice if the minimum size is
1035 // also combined within this function. Currently, the minimum size check is
1036 // performed in findJumpTable() in SelectionDAGBuiler and
1037 // getEstimatedNumberOfCaseClusters() in BasicTTIImpl.
1038 const bool OptForSize = SI->getParent()->getParent()->hasOptSize();
1039 const unsigned MinDensity = getMinimumJumpTableDensity(OptForSize);
1040 const unsigned MaxJumpTableSize = getMaximumJumpTableSize();
1041
1042 // Check whether the number of cases is small enough and
1043 // the range is dense enough for a jump table.
1044 if ((OptForSize || Range <= MaxJumpTableSize) &&
1045 (NumCases * 100 >= Range * MinDensity)) {
1046 return true;
1047 }
1048 return false;
1049 }
1050
1051 /// Return true if lowering to a bit test is suitable for a set of case
1052 /// clusters which contains \p NumDests unique destinations, \p Low and
1053 /// \p High as its lowest and highest case values, and expects \p NumCmps
1054 /// case value comparisons. Check if the number of destinations, comparison
1055 /// metric, and range are all suitable.
1056 bool isSuitableForBitTests(unsigned NumDests, unsigned NumCmps,
1057 const APInt &Low, const APInt &High,
1058 const DataLayout &DL) const {
1059 // FIXME: I don't think NumCmps is the correct metric: a single case and a
1060 // range of cases both require only one branch to lower. Just looking at the
1061 // number of clusters and destinations should be enough to decide whether to
1062 // build bit tests.
1063
1064 // To lower a range with bit tests, the range must fit the bitwidth of a
1065 // machine word.
1066 if (!rangeFitsInWord(Low, High, DL))
1067 return false;
1068
1069 // Decide whether it's profitable to lower this range with bit tests. Each
1070 // destination requires a bit test and branch, and there is an overall range
1071 // check branch. For a small number of clusters, separate comparisons might
1072 // be cheaper, and for many destinations, splitting the range might be
1073 // better.
1074 return (NumDests == 1 && NumCmps >= 3) || (NumDests == 2 && NumCmps >= 5) ||
1075 (NumDests == 3 && NumCmps >= 6);
1076 }
1077
1078 /// Return true if the specified operation is illegal on this target or
1079 /// unlikely to be made legal with custom lowering. This is used to help guide
1080 /// high-level lowering decisions.
1081 bool isOperationExpand(unsigned Op, EVT VT) const {
1082 return (!isTypeLegal(VT) || getOperationAction(Op, VT) == Expand);
1083 }
1084
1085 /// Return true if the specified operation is legal on this target.
1086 bool isOperationLegal(unsigned Op, EVT VT) const {
1087 return (VT == MVT::Other || isTypeLegal(VT)) &&
1088 getOperationAction(Op, VT) == Legal;
1089 }
1090
1091 /// Return how this load with extension should be treated: either it is legal,
1092 /// needs to be promoted to a larger size, needs to be expanded to some other
1093 /// code sequence, or the target has a custom expander for it.
1094 LegalizeAction getLoadExtAction(unsigned ExtType, EVT ValVT,
1095 EVT MemVT) const {
1096 if (ValVT.isExtended() || MemVT.isExtended()) return Expand;
1097 unsigned ValI = (unsigned) ValVT.getSimpleVT().SimpleTy;
1098 unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy;
1099 assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValI < MVT::LAST_VALUETYPE &&((ExtType < ISD::LAST_LOADEXT_TYPE && ValI < MVT
::LAST_VALUETYPE && MemI < MVT::LAST_VALUETYPE &&
"Table isn't big enough!") ? static_cast<void> (0) : __assert_fail
("ExtType < ISD::LAST_LOADEXT_TYPE && ValI < MVT::LAST_VALUETYPE && MemI < MVT::LAST_VALUETYPE && \"Table isn't big enough!\""
, "/build/llvm-toolchain-snapshot-10~svn374814/include/llvm/CodeGen/TargetLowering.h"
, 1100, __PRETTY_FUNCTION__))
1100 MemI < MVT::LAST_VALUETYPE && "Table isn't big enough!")((ExtType < ISD::LAST_LOADEXT_TYPE && ValI < MVT
::LAST_VALUETYPE && MemI < MVT::LAST_VALUETYPE &&
"Table isn't big enough!") ? static_cast<void> (0) : __assert_fail
("ExtType < ISD::LAST_LOADEXT_TYPE && ValI < MVT::LAST_VALUETYPE && MemI < MVT::LAST_VALUETYPE && \"Table isn't big enough!\""
, "/build/llvm-toolchain-snapshot-10~svn374814/include/llvm/CodeGen/TargetLowering.h"
, 1100, __PRETTY_FUNCTION__))
;
1101 unsigned Shift = 4 * ExtType;
1102 return (LegalizeAction)((LoadExtActions[ValI][MemI] >> Shift) & 0xf);
1103 }
1104
1105 /// Return true if the specified load with extension is legal on this target.
1106 bool isLoadExtLegal(unsigned ExtType, EVT ValVT, EVT MemVT) const {
1107 return getLoadExtAction(ExtType, ValVT, MemVT) == Legal;
1108 }
1109
1110 /// Return true if the specified load with extension is legal or custom
1111 /// on this target.
1112 bool isLoadExtLegalOrCustom(unsigned ExtType, EVT ValVT, EVT MemVT) const {
1113 return getLoadExtAction(ExtType, ValVT, MemVT) == Legal ||
1114 getLoadExtAction(ExtType, ValVT, MemVT) == Custom;
1115 }
1116
1117 /// Return how this store with truncation should be treated: either it is
1118 /// legal, needs to be promoted to a larger size, needs to be expanded to some
1119 /// other code sequence, or the target has a custom expander for it.
1120 LegalizeAction getTruncStoreAction(EVT ValVT, EVT MemVT) const {
1121 if (ValVT.isExtended() || MemVT.isExtended()) return Expand;
1122 unsigned ValI = (unsigned) ValVT.getSimpleVT().SimpleTy;
1123 unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy;
1124 assert(ValI < MVT::LAST_VALUETYPE && MemI < MVT::LAST_VALUETYPE &&((ValI < MVT::LAST_VALUETYPE && MemI < MVT::LAST_VALUETYPE
&& "Table isn't big enough!") ? static_cast<void>
(0) : __assert_fail ("ValI < MVT::LAST_VALUETYPE && MemI < MVT::LAST_VALUETYPE && \"Table isn't big enough!\""
, "/build/llvm-toolchain-snapshot-10~svn374814/include/llvm/CodeGen/TargetLowering.h"
, 1125, __PRETTY_FUNCTION__))
1125 "Table isn't big enough!")((ValI < MVT::LAST_VALUETYPE && MemI < MVT::LAST_VALUETYPE
&& "Table isn't big enough!") ? static_cast<void>
(0) : __assert_fail ("ValI < MVT::LAST_VALUETYPE && MemI < MVT::LAST_VALUETYPE && \"Table isn't big enough!\""
, "/build/llvm-toolchain-snapshot-10~svn374814/include/llvm/CodeGen/TargetLowering.h"
, 1125, __PRETTY_FUNCTION__))
;
1126 return TruncStoreActions[ValI][MemI];
1127 }
1128
1129 /// Return true if the specified store with truncation is legal on this
1130 /// target.
1131 bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const {
1132 return isTypeLegal(ValVT) && getTruncStoreAction(ValVT, MemVT) == Legal;
1133 }
1134
1135 /// Return true if the specified store with truncation has solution on this
1136 /// target.
1137 bool isTruncStoreLegalOrCustom(EVT ValVT, EVT MemVT) const {
1138 return isTypeLegal(ValVT) &&
1139 (getTruncStoreAction(ValVT, MemVT) == Legal ||
1140 getTruncStoreAction(ValVT, MemVT) == Custom);
1141 }
1142
1143 /// Return how the indexed load should be treated: either it is legal, needs
1144 /// to be promoted to a larger size, needs to be expanded to some other code
1145 /// sequence, or the target has a custom expander for it.
1146 LegalizeAction
1147 getIndexedLoadAction(unsigned IdxMode, MVT VT) const {
1148 assert(IdxMode < ISD::LAST_INDEXED_MODE && VT.isValid() &&((IdxMode < ISD::LAST_INDEXED_MODE && VT.isValid()
&& "Table isn't big enough!") ? static_cast<void>
(0) : __assert_fail ("IdxMode < ISD::LAST_INDEXED_MODE && VT.isValid() && \"Table isn't big enough!\""
, "/build/llvm-toolchain-snapshot-10~svn374814/include/llvm/CodeGen/TargetLowering.h"
, 1149, __PRETTY_FUNCTION__))
1149 "Table isn't big enough!")((IdxMode < ISD::LAST_INDEXED_MODE && VT.isValid()
&& "Table isn't big enough!") ? static_cast<void>
(0) : __assert_fail ("IdxMode < ISD::LAST_INDEXED_MODE && VT.isValid() && \"Table isn't big enough!\""
, "/build/llvm-toolchain-snapshot-10~svn374814/include/llvm/CodeGen/TargetLowering.h"
, 1149, __PRETTY_FUNCTION__))
;
1150 unsigned Ty = (unsigned)VT.SimpleTy;
1151 return (LegalizeAction)((IndexedModeActions[Ty][IdxMode] & 0xf0) >> 4);
1152 }
1153
1154 /// Return true if the specified indexed load is legal on this target.
1155 bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const {
1156 return VT.isSimple() &&
1157 (getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Legal ||
1158 getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Custom);
1159 }
1160
1161 /// Return how the indexed store should be treated: either it is legal, needs
1162 /// to be promoted to a larger size, needs to be expanded to some other code
1163 /// sequence, or the target has a custom expander for it.
1164 LegalizeAction
1165 getIndexedStoreAction(unsigned IdxMode, MVT VT) const {
1166 assert(IdxMode < ISD::LAST_INDEXED_MODE && VT.isValid() &&((IdxMode < ISD::LAST_INDEXED_MODE && VT.isValid()
&& "Table isn't big enough!") ? static_cast<void>
(0) : __assert_fail ("IdxMode < ISD::LAST_INDEXED_MODE && VT.isValid() && \"Table isn't big enough!\""
, "/build/llvm-toolchain-snapshot-10~svn374814/include/llvm/CodeGen/TargetLowering.h"
, 1167, __PRETTY_FUNCTION__))
1167 "Table isn't big enough!")((IdxMode < ISD::LAST_INDEXED_MODE && VT.isValid()
&& "Table isn't big enough!") ? static_cast<void>
(0) : __assert_fail ("IdxMode < ISD::LAST_INDEXED_MODE && VT.isValid() && \"Table isn't big enough!\""
, "/build/llvm-toolchain-snapshot-10~svn374814/include/llvm/CodeGen/TargetLowering.h"
, 1167, __PRETTY_FUNCTION__))
;
1168 unsigned Ty = (unsigned)VT.SimpleTy;
1169 return (LegalizeAction)(IndexedModeActions[Ty][IdxMode] & 0x0f);
1170 }
1171
1172 /// Return true if the specified indexed load is legal on this target.
1173 bool isIndexedStoreLegal(unsigned IdxMode, EVT VT) const {
1174 return VT.isSimple() &&
1175 (getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Legal ||
1176 getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Custom);
1177 }
1178
1179 /// Return how the condition code should be treated: either it is legal, needs
1180 /// to be expanded to some other code sequence, or the target has a custom
1181 /// expander for it.
1182 LegalizeAction
1183 getCondCodeAction(ISD::CondCode CC, MVT VT) const {
1184 assert((unsigned)CC < array_lengthof(CondCodeActions) &&(((unsigned)CC < array_lengthof(CondCodeActions) &&
((unsigned)VT.SimpleTy >> 3) < array_lengthof(CondCodeActions
[0]) && "Table isn't big enough!") ? static_cast<void
> (0) : __assert_fail ("(unsigned)CC < array_lengthof(CondCodeActions) && ((unsigned)VT.SimpleTy >> 3) < array_lengthof(CondCodeActions[0]) && \"Table isn't big enough!\""
, "/build/llvm-toolchain-snapshot-10~svn374814/include/llvm/CodeGen/TargetLowering.h"
, 1186, __PRETTY_FUNCTION__))
1185 ((unsigned)VT.SimpleTy >> 3) < array_lengthof(CondCodeActions[0]) &&(((unsigned)CC < array_lengthof(CondCodeActions) &&
((unsigned)VT.SimpleTy >> 3) < array_lengthof(CondCodeActions
[0]) && "Table isn't big enough!") ? static_cast<void
> (0) : __assert_fail ("(unsigned)CC < array_lengthof(CondCodeActions) && ((unsigned)VT.SimpleTy >> 3) < array_lengthof(CondCodeActions[0]) && \"Table isn't big enough!\""
, "/build/llvm-toolchain-snapshot-10~svn374814/include/llvm/CodeGen/TargetLowering.h"
, 1186, __PRETTY_FUNCTION__))
1186 "Table isn't big enough!")(((unsigned)CC < array_lengthof(CondCodeActions) &&
((unsigned)VT.SimpleTy >> 3) < array_lengthof(CondCodeActions
[0]) && "Table isn't big enough!") ? static_cast<void
> (0) : __assert_fail ("(unsigned)CC < array_lengthof(CondCodeActions) && ((unsigned)VT.SimpleTy >> 3) < array_lengthof(CondCodeActions[0]) && \"Table isn't big enough!\""
, "/build/llvm-toolchain-snapshot-10~svn374814/include/llvm/CodeGen/TargetLowering.h"
, 1186, __PRETTY_FUNCTION__))
;
1187 // See setCondCodeAction for how this is encoded.
1188 uint32_t Shift = 4 * (VT.SimpleTy & 0x7);
1189 uint32_t Value = CondCodeActions[CC][VT.SimpleTy >> 3];
1190 LegalizeAction Action = (LegalizeAction) ((Value >> Shift) & 0xF);
1191 assert(Action != Promote && "Can't promote condition code!")((Action != Promote && "Can't promote condition code!"
) ? static_cast<void> (0) : __assert_fail ("Action != Promote && \"Can't promote condition code!\""
, "/build/llvm-toolchain-snapshot-10~svn374814/include/llvm/CodeGen/TargetLowering.h"
, 1191, __PRETTY_FUNCTION__))
;
1192 return Action;
1193 }
1194
1195 /// Return true if the specified condition code is legal on this target.
1196 bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const {
1197 return getCondCodeAction(CC, VT) == Legal;
1198 }
1199
1200 /// Return true if the specified condition code is legal or custom on this
1201 /// target.
1202 bool isCondCodeLegalOrCustom(ISD::CondCode CC, MVT VT) const {
1203 return getCondCodeAction(CC, VT) == Legal ||
1204 getCondCodeAction(CC, VT) == Custom;
1205 }
1206
1207 /// If the action for this operation is to promote, this method returns the
1208 /// ValueType to promote to.
1209 MVT getTypeToPromoteTo(unsigned Op, MVT VT) const {
1210 assert(getOperationAction(Op, VT) == Promote &&((getOperationAction(Op, VT) == Promote && "This operation isn't promoted!"
) ? static_cast<void> (0) : __assert_fail ("getOperationAction(Op, VT) == Promote && \"This operation isn't promoted!\""
, "/build/llvm-toolchain-snapshot-10~svn374814/include/llvm/CodeGen/TargetLowering.h"
, 1211, __PRETTY_FUNCTION__))
1211 "This operation isn't promoted!")((getOperationAction(Op, VT) == Promote && "This operation isn't promoted!"
) ? static_cast<void> (0) : __assert_fail ("getOperationAction(Op, VT) == Promote && \"This operation isn't promoted!\""
, "/build/llvm-toolchain-snapshot-10~svn374814/include/llvm/CodeGen/TargetLowering.h"
, 1211, __PRETTY_FUNCTION__))
;
1212
1213 // See if this has an explicit type specified.
1214 std::map<std::pair<unsigned, MVT::SimpleValueType>,
1215 MVT::SimpleValueType>::const_iterator PTTI =
1216 PromoteToType.find(std::make_pair(Op, VT.SimpleTy));
1217 if (PTTI != PromoteToType.end()) return PTTI->second;
1218
1219 assert((VT.isInteger() || VT.isFloatingPoint()) &&(((VT.isInteger() || VT.isFloatingPoint()) && "Cannot autopromote this type, add it with AddPromotedToType."
) ? static_cast<void> (0) : __assert_fail ("(VT.isInteger() || VT.isFloatingPoint()) && \"Cannot autopromote this type, add it with AddPromotedToType.\""
, "/build/llvm-toolchain-snapshot-10~svn374814/include/llvm/CodeGen/TargetLowering.h"
, 1220, __PRETTY_FUNCTION__))
1220 "Cannot autopromote this type, add it with AddPromotedToType.")(((VT.isInteger() || VT.isFloatingPoint()) && "Cannot autopromote this type, add it with AddPromotedToType."
) ? static_cast<void> (0) : __assert_fail ("(VT.isInteger() || VT.isFloatingPoint()) && \"Cannot autopromote this type, add it with AddPromotedToType.\""
, "/build/llvm-toolchain-snapshot-10~svn374814/include/llvm/CodeGen/TargetLowering.h"
, 1220, __PRETTY_FUNCTION__))
;
1221
1222 MVT NVT = VT;
1223 do {
1224 NVT = (MVT::SimpleValueType)(NVT.SimpleTy+1);
1225 assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid &&((NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid
&& "Didn't find type to promote to!") ? static_cast<
void> (0) : __assert_fail ("NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid && \"Didn't find type to promote to!\""
, "/build/llvm-toolchain-snapshot-10~svn374814/include/llvm/CodeGen/TargetLowering.h"
, 1226, __PRETTY_FUNCTION__))
1226 "Didn't find type to promote to!")((NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid
&& "Didn't find type to promote to!") ? static_cast<
void> (0) : __assert_fail ("NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid && \"Didn't find type to promote to!\""
, "/build/llvm-toolchain-snapshot-10~svn374814/include/llvm/CodeGen/TargetLowering.h"
, 1226, __PRETTY_FUNCTION__))
;
1227 } while (!isTypeLegal(NVT) ||
1228 getOperationAction(Op, NVT) == Promote);
1229 return NVT;
1230 }
1231
1232 /// Return the EVT corresponding to this LLVM type. This is fixed by the LLVM
1233 /// operations except for the pointer size. If AllowUnknown is true, this
1234 /// will return MVT::Other for types with no EVT counterpart (e.g. structs),
1235 /// otherwise it will assert.
1236 EVT getValueType(const DataLayout &DL, Type *Ty,
1237 bool AllowUnknown = false) const {
1238 // Lower scalar pointers to native pointer types.
1239 if (auto *PTy = dyn_cast<PointerType>(Ty))
1240 return getPointerTy(DL, PTy->getAddressSpace());
1241
1242 if (auto *VTy = dyn_cast<VectorType>(Ty)) {
1243 Type *EltTy = VTy->getElementType();
1244 // Lower vectors of pointers to native pointer types.
1245 if (auto *PTy = dyn_cast<PointerType>(EltTy)) {
1246 EVT PointerTy(getPointerTy(DL, PTy->getAddressSpace()));
1247 EltTy = PointerTy.getTypeForEVT(Ty->getContext());
1248 }
1249 return EVT::getVectorVT(Ty->getContext(), EVT::getEVT(EltTy, false),
1250 VTy->getElementCount());
1251 }
1252
1253 return EVT::getEVT(Ty, AllowUnknown);
1254 }
1255
1256 EVT getMemValueType(const DataLayout &DL, Type *Ty,
1257 bool AllowUnknown = false) const {
1258 // Lower scalar pointers to native pointer types.
1259 if (PointerType *PTy = dyn_cast<PointerType>(Ty))
1260 return getPointerMemTy(DL, PTy->getAddressSpace());
1261 else if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1262 Type *Elm = VTy->getElementType();
1263 if (PointerType *PT = dyn_cast<PointerType>(Elm)) {
1264 EVT PointerTy(getPointerMemTy(DL, PT->getAddressSpace()));
1265 Elm = PointerTy.getTypeForEVT(Ty->getContext());
1266 }
1267 return EVT::getVectorVT(Ty->getContext(), EVT::getEVT(Elm, false),
1268 VTy->getNumElements());
1269 }
1270
1271 return getValueType(DL, Ty, AllowUnknown);
1272 }
1273
1274
1275 /// Return the MVT corresponding to this LLVM type. See getValueType.
1276 MVT getSimpleValueType(const DataLayout &DL, Type *Ty,
1277 bool AllowUnknown = false) const {
1278 return getValueType(DL, Ty, AllowUnknown).getSimpleVT();
1279 }
1280
1281 /// Return the desired alignment for ByVal or InAlloca aggregate function
1282 /// arguments in the caller parameter area. This is the actual alignment, not
1283 /// its logarithm.
1284 virtual unsigned getByValTypeAlignment(Type *Ty, const DataLayout &DL) const;
1285
1286 /// Return the type of registers that this ValueType will eventually require.
1287 MVT getRegisterType(MVT VT) const {
1288 assert((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT))(((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT
)) ? static_cast<void> (0) : __assert_fail ("(unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT)"
, "/build/llvm-toolchain-snapshot-10~svn374814/include/llvm/CodeGen/TargetLowering.h"
, 1288, __PRETTY_FUNCTION__))
;
1289 return RegisterTypeForVT[VT.SimpleTy];
1290 }
1291
1292 /// Return the type of registers that this ValueType will eventually require.
1293 MVT getRegisterType(LLVMContext &Context, EVT VT) const {
1294 if (VT.isSimple()) {
1295 assert((unsigned)VT.getSimpleVT().SimpleTy <(((unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegisterTypeForVT
)) ? static_cast<void> (0) : __assert_fail ("(unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegisterTypeForVT)"
, "/build/llvm-toolchain-snapshot-10~svn374814/include/llvm/CodeGen/TargetLowering.h"
, 1296, __PRETTY_FUNCTION__))
1296 array_lengthof(RegisterTypeForVT))(((unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegisterTypeForVT
)) ? static_cast<void> (0) : __assert_fail ("(unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegisterTypeForVT)"
, "/build/llvm-toolchain-snapshot-10~svn374814/include/llvm/CodeGen/TargetLowering.h"
, 1296, __PRETTY_FUNCTION__))
;
1297 return RegisterTypeForVT[VT.getSimpleVT().SimpleTy];
1298 }
1299 if (VT.isVector()) {
1300 EVT VT1;
1301 MVT RegisterVT;
1302 unsigned NumIntermediates;
1303 (void)getVectorTypeBreakdown(Context, VT, VT1,
1304 NumIntermediates, RegisterVT);
1305 return RegisterVT;
1306 }
1307 if (VT.isInteger()) {
1308 return getRegisterType(Context, getTypeToTransformTo(Context, VT));
1309 }
1310 llvm_unreachable("Unsupported extended type!")::llvm::llvm_unreachable_internal("Unsupported extended type!"
, "/build/llvm-toolchain-snapshot-10~svn374814/include/llvm/CodeGen/TargetLowering.h"
, 1310)
;
1311 }
1312
1313 /// Return the number of registers that this ValueType will eventually
1314 /// require.
1315 ///
1316 /// This is one for any types promoted to live in larger registers, but may be
1317 /// more than one for types (like i64) that are split into pieces. For types
1318 /// like i140, which are first promoted then expanded, it is the number of
1319 /// registers needed to hold all the bits of the original type. For an i140
1320 /// on a 32 bit machine this means 5 registers.
1321 unsigned getNumRegisters(LLVMContext &Context, EVT VT) const {
1322 if (VT.isSimple()) {
1323 assert((unsigned)VT.getSimpleVT().SimpleTy <(((unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(NumRegistersForVT
)) ? static_cast<void> (0) : __assert_fail ("(unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(NumRegistersForVT)"
, "/build/llvm-toolchain-snapshot-10~svn374814/include/llvm/CodeGen/TargetLowering.h"
, 1324, __PRETTY_FUNCTION__))
1324 array_lengthof(NumRegistersForVT))(((unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(NumRegistersForVT
)) ? static_cast<void> (0) : __assert_fail ("(unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(NumRegistersForVT)"
, "/build/llvm-toolchain-snapshot-10~svn374814/include/llvm/CodeGen/TargetLowering.h"
, 1324, __PRETTY_FUNCTION__))
;
1325 return NumRegistersForVT[VT.getSimpleVT().SimpleTy];
1326 }
1327 if (VT.isVector()) {
1328 EVT VT1;
1329 MVT VT2;
1330 unsigned NumIntermediates;
1331 return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2);
1332 }
1333 if (VT.isInteger()) {
1334 unsigned BitWidth = VT.getSizeInBits();
1335 unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits();
1336 return (BitWidth + RegWidth - 1) / RegWidth;
1337 }
1338 llvm_unreachable("Unsupported extended type!")::llvm::llvm_unreachable_internal("Unsupported extended type!"
, "/build/llvm-toolchain-snapshot-10~svn374814/include/llvm/CodeGen/TargetLowering.h"
, 1338)
;
1339 }
1340
1341 /// Certain combinations of ABIs, Targets and features require that types
1342 /// are legal for some operations and not for other operations.
1343 /// For MIPS all vector types must be passed through the integer register set.
1344 virtual MVT getRegisterTypeForCallingConv(LLVMContext &Context,
1345 CallingConv::ID CC, EVT VT) const {
1346 return getRegisterType(Context, VT);
1347 }
1348
1349 /// Certain targets require unusual breakdowns of certain types. For MIPS,
1350 /// this occurs when a vector type is used, as vector are passed through the
1351 /// integer register set.
1352 virtual unsigned getNumRegistersForCallingConv(LLVMContext &Context,
1353 CallingConv::ID CC,
1354 EVT VT) const {
1355 return getNumRegisters(Context, VT);
1356 }
1357
1358 /// Certain targets have context senstive alignment requirements, where one
1359 /// type has the alignment requirement of another type.
1360 virtual unsigned getABIAlignmentForCallingConv(Type *ArgTy,
1361 DataLayout DL) const {
1362 return DL.getABITypeAlignment(ArgTy);
1363 }
1364
1365 /// If true, then instruction selection should seek to shrink the FP constant
1366 /// of the specified type to a smaller type in order to save space and / or
1367 /// reduce runtime.
1368 virtual bool ShouldShrinkFPConstant(EVT) const { return true; }
1369
1370 /// Return true if it is profitable to reduce a load to a smaller type.
1371 /// Example: (i16 (trunc (i32 (load x))) -> i16 load x
1372 virtual bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy,
1373 EVT NewVT) const {
1374 // By default, assume that it is cheaper to extract a subvector from a wide
1375 // vector load rather than creating multiple narrow vector loads.
1376 if (NewVT.isVector() && !Load->hasOneUse())
1377 return false;
1378
1379 return true;
1380 }
1381
1382 /// When splitting a value of the specified type into parts, does the Lo
1383 /// or Hi part come first? This usually follows the endianness, except
1384 /// for ppcf128, where the Hi part always comes first.
1385 bool hasBigEndianPartOrdering(EVT VT, const DataLayout &DL) const {
1386 return DL.isBigEndian() || VT == MVT::ppcf128;
1387 }
1388
1389 /// If true, the target has custom DAG combine transformations that it can
1390 /// perform for the specified node.
1391 bool hasTargetDAGCombine(ISD::NodeType NT) const {
1392 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray))((unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray
)) ? static_cast<void> (0) : __assert_fail ("unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray)"
, "/build/llvm-toolchain-snapshot-10~svn374814/include/llvm/CodeGen/TargetLowering.h"
, 1392, __PRETTY_FUNCTION__))
;
1393 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
1394 }
1395
1396 unsigned getGatherAllAliasesMaxDepth() const {
1397 return GatherAllAliasesMaxDepth;
1398 }
1399
1400 /// Returns the size of the platform's va_list object.
1401 virtual unsigned getVaListSizeInBits(const DataLayout &DL) const {
1402 return getPointerTy(DL).getSizeInBits();
1403 }
1404
1405 /// Get maximum # of store operations permitted for llvm.memset
1406 ///
1407 /// This function returns the maximum number of store operations permitted
1408 /// to replace a call to llvm.memset. The value is set by the target at the
1409 /// performance threshold for such a replacement. If OptSize is true,
1410 /// return the limit for functions that have OptSize attribute.
1411 unsigned getMaxStoresPerMemset(bool OptSize) const {
1412 return OptSize ? MaxStoresPerMemsetOptSize : MaxStoresPerMemset;
1413 }
1414
1415 /// Get maximum # of store operations permitted for llvm.memcpy
1416 ///
1417 /// This function returns the maximum number of store operations permitted
1418 /// to replace a call to llvm.memcpy. The value is set by the target at the
1419 /// performance threshold for such a replacement. If OptSize is true,
1420 /// return the limit for functions that have OptSize attribute.
1421 unsigned getMaxStoresPerMemcpy(bool OptSize) const {
1422 return OptSize ? MaxStoresPerMemcpyOptSize : MaxStoresPerMemcpy;
1423 }
1424
1425 /// \brief Get maximum # of store operations to be glued together
1426 ///
1427 /// This function returns the maximum number of store operations permitted
1428 /// to glue together during lowering of llvm.memcpy. The value is set by
1429 // the target at the performance threshold for such a replacement.
1430 virtual unsigned getMaxGluedStoresPerMemcpy() const {
1431 return MaxGluedStoresPerMemcpy;
1432 }
1433
1434 /// Get maximum # of load operations permitted for memcmp
1435 ///
1436 /// This function returns the maximum number of load operations permitted
1437 /// to replace a call to memcmp. The value is set by the target at the
1438 /// performance threshold for such a replacement. If OptSize is true,
1439 /// return the limit for functions that have OptSize attribute.
1440 unsigned getMaxExpandSizeMemcmp(bool OptSize) const {
1441 return OptSize ? MaxLoadsPerMemcmpOptSize : MaxLoadsPerMemcmp;
1442 }
1443
1444 /// Get maximum # of store operations permitted for llvm.memmove
1445 ///
1446 /// This function returns the maximum number of store operations permitted
1447 /// to replace a call to llvm.memmove. The value is set by the target at the
1448 /// performance threshold for such a replacement. If OptSize is true,
1449 /// return the limit for functions that have OptSize attribute.
1450 unsigned getMaxStoresPerMemmove(bool OptSize) const {
1451 return OptSize ? MaxStoresPerMemmoveOptSize : MaxStoresPerMemmove;
1452 }
1453
1454 /// Determine if the target supports unaligned memory accesses.
1455 ///
1456 /// This function returns true if the target allows unaligned memory accesses
1457 /// of the specified type in the given address space. If true, it also returns
1458 /// whether the unaligned memory access is "fast" in the last argument by
1459 /// reference. This is used, for example, in situations where an array
1460 /// copy/move/set is converted to a sequence of store operations. Its use
1461 /// helps to ensure that such replacements don't generate code that causes an
1462 /// alignment error (trap) on the target machine.
1463 virtual bool allowsMisalignedMemoryAccesses(
1464 EVT, unsigned AddrSpace = 0, unsigned Align = 1,
1465 MachineMemOperand::Flags Flags = MachineMemOperand::MONone,
1466 bool * /*Fast*/ = nullptr) const {
1467 return false;
1468 }
1469
1470 /// LLT handling variant.
1471 virtual bool allowsMisalignedMemoryAccesses(
1472 LLT, unsigned AddrSpace = 0, unsigned Align = 1,
1473 MachineMemOperand::Flags Flags = MachineMemOperand::MONone,
1474 bool * /*Fast*/ = nullptr) const {
1475 return false;
1476 }
1477
1478 /// This function returns true if the memory access is aligned or if the
1479 /// target allows this specific unaligned memory access. If the access is
1480 /// allowed, the optional final parameter returns if the access is also fast
1481 /// (as defined by the target).
1482 bool allowsMemoryAccessForAlignment(
1483 LLVMContext &Context, const DataLayout &DL, EVT VT,
1484 unsigned AddrSpace = 0, unsigned Alignment = 1,
1485 MachineMemOperand::Flags Flags = MachineMemOperand::MONone,
1486 bool *Fast = nullptr) const;
1487
1488 /// Return true if the memory access of this type is aligned or if the target
1489 /// allows this specific unaligned access for the given MachineMemOperand.
1490 /// If the access is allowed, the optional final parameter returns if the
1491 /// access is also fast (as defined by the target).
1492 bool allowsMemoryAccessForAlignment(LLVMContext &Context,
1493 const DataLayout &DL, EVT VT,
1494 const MachineMemOperand &MMO,
1495 bool *Fast = nullptr) const;
1496
1497 /// Return true if the target supports a memory access of this type for the
1498 /// given address space and alignment. If the access is allowed, the optional
1499 /// final parameter returns if the access is also fast (as defined by the
1500 /// target).
1501 virtual bool
1502 allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT,
1503 unsigned AddrSpace = 0, unsigned Alignment = 1,
1504 MachineMemOperand::Flags Flags = MachineMemOperand::MONone,
1505 bool *Fast = nullptr) const;
1506
1507 /// Return true if the target supports a memory access of this type for the
1508 /// given MachineMemOperand. If the access is allowed, the optional
1509 /// final parameter returns if the access is also fast (as defined by the
1510 /// target).
1511 bool allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT,
1512 const MachineMemOperand &MMO,
1513 bool *Fast = nullptr) const;
1514
1515 /// Returns the target specific optimal type for load and store operations as
1516 /// a result of memset, memcpy, and memmove lowering.
1517 ///
1518 /// If DstAlign is zero that means it's safe to destination alignment can
1519 /// satisfy any constraint. Similarly if SrcAlign is zero it means there isn't
1520 /// a need to check it against alignment requirement, probably because the
1521 /// source does not need to be loaded. If 'IsMemset' is true, that means it's
1522 /// expanding a memset. If 'ZeroMemset' is true, that means it's a memset of
1523 /// zero. 'MemcpyStrSrc' indicates whether the memcpy source is constant so it
1524 /// does not need to be loaded. It returns EVT::Other if the type should be
1525 /// determined using generic target-independent logic.
1526 virtual EVT
1527 getOptimalMemOpType(uint64_t /*Size*/, unsigned /*DstAlign*/,
1528 unsigned /*SrcAlign*/, bool /*IsMemset*/,
1529 bool /*ZeroMemset*/, bool /*MemcpyStrSrc*/,
1530 const AttributeList & /*FuncAttributes*/) const {
1531 return MVT::Other;
1532 }
1533
1534
1535 /// LLT returning variant.
1536 virtual LLT
1537 getOptimalMemOpLLT(uint64_t /*Size*/, unsigned /*DstAlign*/,
1538 unsigned /*SrcAlign*/, bool /*IsMemset*/,
1539 bool /*ZeroMemset*/, bool /*MemcpyStrSrc*/,
1540 const AttributeList & /*FuncAttributes*/) const {
1541 return LLT();
1542 }
1543
1544 /// Returns true if it's safe to use load / store of the specified type to
1545 /// expand memcpy / memset inline.
1546 ///
1547 /// This is mostly true for all types except for some special cases. For
1548 /// example, on X86 targets without SSE2 f64 load / store are done with fldl /
1549 /// fstpl which also does type conversion. Note the specified type doesn't
1550 /// have to be legal as the hook is used before type legalization.
1551 virtual bool isSafeMemOpType(MVT /*VT*/) const { return true; }
1552
1553 /// Determine if we should use _setjmp or setjmp to implement llvm.setjmp.
1554 bool usesUnderscoreSetJmp() const {
1555 return UseUnderscoreSetJmp;
1556 }
1557
1558 /// Determine if we should use _longjmp or longjmp to implement llvm.longjmp.
1559 bool usesUnderscoreLongJmp() const {
1560 return UseUnderscoreLongJmp;
1561 }
1562
1563 /// Return lower limit for number of blocks in a jump table.
1564 virtual unsigned getMinimumJumpTableEntries() const;
1565
1566 /// Return lower limit of the density in a jump table.
1567 unsigned getMinimumJumpTableDensity(bool OptForSize) const;
1568
1569 /// Return upper limit for number of entries in a jump table.
1570 /// Zero if no limit.
1571 unsigned getMaximumJumpTableSize() const;
1572
1573 virtual bool isJumpTableRelative() const {
1574 return TM.isPositionIndependent();
1575 }
1576
1577 /// If a physical register, this specifies the register that
1578 /// llvm.savestack/llvm.restorestack should save and restore.
1579 unsigned getStackPointerRegisterToSaveRestore() const {
1580 return StackPointerRegisterToSaveRestore;
1581 }
1582
1583 /// If a physical register, this returns the register that receives the
1584 /// exception address on entry to an EH pad.
1585 virtual unsigned
1586 getExceptionPointerRegister(const Constant *PersonalityFn) const {
1587 // 0 is guaranteed to be the NoRegister value on all targets
1588 return 0;
1589 }
1590
1591 /// If a physical register, this returns the register that receives the
1592 /// exception typeid on entry to a landing pad.
1593 virtual unsigned
1594 getExceptionSelectorRegister(const Constant *PersonalityFn) const {
1595 // 0 is guaranteed to be the NoRegister value on all targets
1596 return 0;
1597 }
1598
1599 virtual bool needsFixedCatchObjects() const {
1600 report_fatal_error("Funclet EH is not implemented for this target");
1601 }
1602
1603 /// Return the minimum stack alignment of an argument.
1604 Align getMinStackArgumentAlignment() const {
1605 return MinStackArgumentAlignment;
1606 }
1607
1608 /// Return the minimum function alignment.
1609 Align getMinFunctionAlignment() const { return MinFunctionAlignment; }
1610
1611 /// Return the preferred function alignment.
1612 Align getPrefFunctionAlignment() const { return PrefFunctionAlignment; }
1613
1614 /// Return the preferred loop alignment.
1615 virtual Align getPrefLoopAlignment(MachineLoop *ML = nullptr) const {
1616 return PrefLoopAlignment;
1617 }
1618
1619 /// Should loops be aligned even when the function is marked OptSize (but not
1620 /// MinSize).
1621 virtual bool alignLoopsWithOptSize() const {
1622 return false;
1623 }
1624
1625 /// If the target has a standard location for the stack protector guard,
1626 /// returns the address of that location. Otherwise, returns nullptr.
1627 /// DEPRECATED: please override useLoadStackGuardNode and customize
1628 /// LOAD_STACK_GUARD, or customize \@llvm.stackguard().
1629 virtual Value *getIRStackGuard(IRBuilder<> &IRB) const;
1630
1631 /// Inserts necessary declarations for SSP (stack protection) purpose.
1632 /// Should be used only when getIRStackGuard returns nullptr.
1633 virtual void insertSSPDeclarations(Module &M) const;
1634
1635 /// Return the variable that's previously inserted by insertSSPDeclarations,
1636 /// if any, otherwise return nullptr. Should be used only when
1637 /// getIRStackGuard returns nullptr.
1638 virtual Value *getSDagStackGuard(const Module &M) const;
1639
1640 /// If this function returns true, stack protection checks should XOR the
1641 /// frame pointer (or whichever pointer is used to address locals) into the
1642 /// stack guard value before checking it. getIRStackGuard must return nullptr
1643 /// if this returns true.
1644 virtual bool useStackGuardXorFP() const { return false; }
1645
1646 /// If the target has a standard stack protection check function that
1647 /// performs validation and error handling, returns the function. Otherwise,
1648 /// returns nullptr. Must be previously inserted by insertSSPDeclarations.
1649 /// Should be used only when getIRStackGuard returns nullptr.
1650 virtual Function *getSSPStackGuardCheck(const Module &M) const;
1651
1652protected:
1653 Value *getDefaultSafeStackPointerLocation(IRBuilder<> &IRB,
1654 bool UseTLS) const;
1655
1656public:
1657 /// Returns the target-specific address of the unsafe stack pointer.
1658 virtual Value *getSafeStackPointerLocation(IRBuilder<> &IRB) const;
1659
1660 /// Returns the name of the symbol used to emit stack probes or the empty
1661 /// string if not applicable.
1662 virtual StringRef getStackProbeSymbolName(MachineFunction &MF) const {
1663 return "";
1664 }
1665
1666 /// Returns true if a cast between SrcAS and DestAS is a noop.
1667 virtual bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const {
1668 return false;
1669 }
1670
1671 /// Returns true if a cast from SrcAS to DestAS is "cheap", such that e.g. we
1672 /// are happy to sink it into basic blocks. A cast may be free, but not
1673 /// necessarily a no-op. e.g. a free truncate from a 64-bit to 32-bit pointer.
1674 virtual bool isFreeAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const {
1675 return isNoopAddrSpaceCast(SrcAS, DestAS);
1676 }
1677
1678 /// Return true if the pointer arguments to CI should be aligned by aligning
1679 /// the object whose address is being passed. If so then MinSize is set to the
1680 /// minimum size the object must be to be aligned and PrefAlign is set to the
1681 /// preferred alignment.
1682 virtual bool shouldAlignPointerArgs(CallInst * /*CI*/, unsigned & /*MinSize*/,
1683 unsigned & /*PrefAlign*/) const {
1684 return false;
1685 }
1686
1687 //===--------------------------------------------------------------------===//
1688 /// \name Helpers for TargetTransformInfo implementations
1689 /// @{
1690
1691 /// Get the ISD node that corresponds to the Instruction class opcode.
1692 int InstructionOpcodeToISD(unsigned Opcode) const;
1693
1694 /// Estimate the cost of type-legalization and the legalized type.
1695 std::pair<int, MVT> getTypeLegalizationCost(const DataLayout &DL,
1696 Type *Ty) const;
1697
1698 /// @}
1699
1700 //===--------------------------------------------------------------------===//
1701 /// \name Helpers for atomic expansion.
1702 /// @{
1703
1704 /// Returns the maximum atomic operation size (in bits) supported by
1705 /// the backend. Atomic operations greater than this size (as well
1706 /// as ones that are not naturally aligned), will be expanded by
1707 /// AtomicExpandPass into an __atomic_* library call.
1708 unsigned getMaxAtomicSizeInBitsSupported() const {
1709 return MaxAtomicSizeInBitsSupported;
1710 }
1711
1712 /// Returns the size of the smallest cmpxchg or ll/sc instruction
1713 /// the backend supports. Any smaller operations are widened in
1714 /// AtomicExpandPass.
1715 ///
1716 /// Note that *unlike* operations above the maximum size, atomic ops
1717 /// are still natively supported below the minimum; they just
1718 /// require a more complex expansion.
1719 unsigned getMinCmpXchgSizeInBits() const { return MinCmpXchgSizeInBits; }
1720
1721 /// Whether the target supports unaligned atomic operations.
1722 bool supportsUnalignedAtomics() const { return SupportsUnalignedAtomics; }
1723
1724 /// Whether AtomicExpandPass should automatically insert fences and reduce
1725 /// ordering for this atomic. This should be true for most architectures with
1726 /// weak memory ordering. Defaults to false.
1727 virtual bool shouldInsertFencesForAtomic(const Instruction *I) const {
1728 return false;
1729 }
1730
1731 /// Perform a load-linked operation on Addr, returning a "Value *" with the
1732 /// corresponding pointee type. This may entail some non-trivial operations to
1733 /// truncate or reconstruct types that will be illegal in the backend. See
1734 /// ARMISelLowering for an example implementation.
1735 virtual Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
1736 AtomicOrdering Ord) const {
1737 llvm_unreachable("Load linked unimplemented on this target")::llvm::llvm_unreachable_internal("Load linked unimplemented on this target"
, "/build/llvm-toolchain-snapshot-10~svn374814/include/llvm/CodeGen/TargetLowering.h"
, 1737)
;
1738 }
1739
1740 /// Perform a store-conditional operation to Addr. Return the status of the
1741 /// store. This should be 0 if the store succeeded, non-zero otherwise.
1742 virtual Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
1743 Value *Addr, AtomicOrdering Ord) const {
1744 llvm_unreachable("Store conditional unimplemented on this target")::llvm::llvm_unreachable_internal("Store conditional unimplemented on this target"
, "/build/llvm-toolchain-snapshot-10~svn374814/include/llvm/CodeGen/TargetLowering.h"
, 1744)
;
1745 }
1746
1747 /// Perform a masked atomicrmw using a target-specific intrinsic. This
1748 /// represents the core LL/SC loop which will be lowered at a late stage by
1749 /// the backend.
1750 virtual Value *emitMaskedAtomicRMWIntrinsic(IRBuilder<> &Builder,
1751 AtomicRMWInst *AI,
1752 Value *AlignedAddr, Value *Incr,
1753 Value *Mask, Value *ShiftAmt,
1754 AtomicOrdering Ord) const {
1755 llvm_unreachable("Masked atomicrmw expansion unimplemented on this target")::llvm::llvm_unreachable_internal("Masked atomicrmw expansion unimplemented on this target"
, "/build/llvm-toolchain-snapshot-10~svn374814/include/llvm/CodeGen/TargetLowering.h"
, 1755)
;
1756 }
1757
1758 /// Perform a masked cmpxchg using a target-specific intrinsic. This
1759 /// represents the core LL/SC loop which will be lowered at a late stage by
1760 /// the backend.
1761 virtual Value *emitMaskedAtomicCmpXchgIntrinsic(
1762 IRBuilder<> &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr,
1763 Value *CmpVal, Value *NewVal, Value *Mask, AtomicOrdering Ord) const {
1764 llvm_unreachable("Masked cmpxchg expansion unimplemented on this target")::llvm::llvm_unreachable_internal("Masked cmpxchg expansion unimplemented on this target"
, "/build/llvm-toolchain-snapshot-10~svn374814/include/llvm/CodeGen/TargetLowering.h"
, 1764)
;
1765 }
1766
1767 /// Inserts in the IR a target-specific intrinsic specifying a fence.
1768 /// It is called by AtomicExpandPass before expanding an
1769 /// AtomicRMW/AtomicCmpXchg/AtomicStore/AtomicLoad
1770 /// if shouldInsertFencesForAtomic returns true.
1771 ///
1772 /// Inst is the original atomic instruction, prior to other expansions that
1773 /// may be performed.
1774 ///
1775 /// This function should either return a nullptr, or a pointer to an IR-level
1776 /// Instruction*. Even complex fence sequences can be represented by a
1777 /// single Instruction* through an intrinsic to be lowered later.
1778 /// Backends should override this method to produce target-specific intrinsic
1779 /// for their fences.
1780 /// FIXME: Please note that the default implementation here in terms of
1781 /// IR-level fences exists for historical/compatibility reasons and is
1782 /// *unsound* ! Fences cannot, in general, be used to restore sequential
1783 /// consistency. For example, consider the following example:
1784 /// atomic<int> x = y = 0;
1785 /// int r1, r2, r3, r4;
1786 /// Thread 0:
1787 /// x.store(1);
1788 /// Thread 1:
1789 /// y.store(1);
1790 /// Thread 2:
1791 /// r1 = x.load();
1792 /// r2 = y.load();
1793 /// Thread 3:
1794 /// r3 = y.load();
1795 /// r4 = x.load();
1796 /// r1 = r3 = 1 and r2 = r4 = 0 is impossible as long as the accesses are all
1797 /// seq_cst. But if they are lowered to monotonic accesses, no amount of
1798 /// IR-level fences can prevent it.
1799 /// @{
1800 virtual Instruction *emitLeadingFence(IRBuilder<> &Builder, Instruction *Inst,
1801 AtomicOrdering Ord) const {
1802 if (isReleaseOrStronger(Ord) && Inst->hasAtomicStore())
1803 return Builder.CreateFence(Ord);
1804 else
1805 return nullptr;
1806 }
1807
1808 virtual Instruction *emitTrailingFence(IRBuilder<> &Builder,
1809 Instruction *Inst,
1810 AtomicOrdering Ord) const {
1811 if (isAcquireOrStronger(Ord))
1812 return Builder.CreateFence(Ord);
1813 else
1814 return nullptr;
1815 }
1816 /// @}
1817
1818 // Emits code that executes when the comparison result in the ll/sc
1819 // expansion of a cmpxchg instruction is such that the store-conditional will
1820 // not execute. This makes it possible to balance out the load-linked with
1821 // a dedicated instruction, if desired.
1822 // E.g., on ARM, if ldrex isn't followed by strex, the exclusive monitor would
1823 // be unnecessarily held, except if clrex, inserted by this hook, is executed.
1824 virtual void emitAtomicCmpXchgNoStoreLLBalance(IRBuilder<> &Builder) const {}
1825
1826 /// Returns true if the given (atomic) store should be expanded by the
1827 /// IR-level AtomicExpand pass into an "atomic xchg" which ignores its input.
1828 virtual bool shouldExpandAtomicStoreInIR(StoreInst *SI) const {
1829 return false;
1830 }
1831
1832 /// Returns true if arguments should be sign-extended in lib calls.
1833 virtual bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const {
1834 return IsSigned;
1835 }
1836
1837 /// Returns true if arguments should be extended in lib calls.
1838 virtual bool shouldExtendTypeInLibCall(EVT Type) const {
1839 return true;
1840 }
1841
1842 /// Returns how the given (atomic) load should be expanded by the
1843 /// IR-level AtomicExpand pass.
1844 virtual AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const {
1845 return AtomicExpansionKind::None;
1846 }
1847
1848 /// Returns how the given atomic cmpxchg should be expanded by the IR-level
1849 /// AtomicExpand pass.
1850 virtual AtomicExpansionKind
1851 shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const {
1852 return AtomicExpansionKind::None;
1853 }
1854
1855 /// Returns how the IR-level AtomicExpand pass should expand the given
1856 /// AtomicRMW, if at all. Default is to never expand.
1857 virtual AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *RMW) const {
1858 return RMW->isFloatingPointOperation() ?
1859 AtomicExpansionKind::CmpXChg : AtomicExpansionKind::None;
1860 }
1861
1862 /// On some platforms, an AtomicRMW that never actually modifies the value
1863 /// (such as fetch_add of 0) can be turned into a fence followed by an
1864 /// atomic load. This may sound useless, but it makes it possible for the
1865 /// processor to keep the cacheline shared, dramatically improving
1866 /// performance. And such idempotent RMWs are useful for implementing some
1867 /// kinds of locks, see for example (justification + benchmarks):
1868 /// http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf
1869 /// This method tries doing that transformation, returning the atomic load if
1870 /// it succeeds, and nullptr otherwise.
1871 /// If shouldExpandAtomicLoadInIR returns true on that load, it will undergo
1872 /// another round of expansion.
1873 virtual LoadInst *
1874 lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *RMWI) const {
1875 return nullptr;
1876 }
1877
1878 /// Returns how the platform's atomic operations are extended (ZERO_EXTEND,
1879 /// SIGN_EXTEND, or ANY_EXTEND).
1880 virtual ISD::NodeType getExtendForAtomicOps() const {
1881 return ISD::ZERO_EXTEND;
1882 }
1883
1884 /// @}
1885
1886 /// Returns true if we should normalize
1887 /// select(N0&N1, X, Y) => select(N0, select(N1, X, Y), Y) and
1888 /// select(N0|N1, X, Y) => select(N0, select(N1, X, Y, Y)) if it is likely
1889 /// that it saves us from materializing N0 and N1 in an integer register.
1890 /// Targets that are able to perform and/or on flags should return false here.
1891 virtual bool shouldNormalizeToSelectSequence(LLVMContext &Context,
1892 EVT VT) const {
1893 // If a target has multiple condition registers, then it likely has logical
1894 // operations on those registers.
1895 if (hasMultipleConditionRegisters())
1896 return false;
1897 // Only do the transform if the value won't be split into multiple
1898 // registers.
1899 LegalizeTypeAction Action = getTypeAction(Context, VT);
1900 return Action != TypeExpandInteger && Action != TypeExpandFloat &&
1901 Action != TypeSplitVector;
1902 }
1903
1904 virtual bool isProfitableToCombineMinNumMaxNum(EVT VT) const { return true; }
1905
1906 /// Return true if a select of constants (select Cond, C1, C2) should be
1907 /// transformed into simple math ops with the condition value. For example:
1908 /// select Cond, C1, C1-1 --> add (zext Cond), C1-1
1909 virtual bool convertSelectOfConstantsToMath(EVT VT) const {
1910 return false;
1911 }
1912
1913 /// Return true if it is profitable to transform an integer
1914 /// multiplication-by-constant into simpler operations like shifts and adds.
1915 /// This may be true if the target does not directly support the
1916 /// multiplication operation for the specified type or the sequence of simpler
1917 /// ops is faster than the multiply.
1918 virtual bool decomposeMulByConstant(LLVMContext &Context,
1919 EVT VT, SDValue C) const {
1920 return false;
1921 }
1922
1923 /// Return true if it is more correct/profitable to use strict FP_TO_INT
1924 /// conversion operations - canonicalizing the FP source value instead of
1925 /// converting all cases and then selecting based on value.
1926 /// This may be true if the target throws exceptions for out of bounds
1927 /// conversions or has fast FP CMOV.
1928 virtual bool shouldUseStrictFP_TO_INT(EVT FpVT, EVT IntVT,
1929 bool IsSigned) const {
1930 return false;
1931 }
1932
1933 //===--------------------------------------------------------------------===//
1934 // TargetLowering Configuration Methods - These methods should be invoked by
1935 // the derived class constructor to configure this object for the target.
1936 //
1937protected:
1938 /// Specify how the target extends the result of integer and floating point
1939 /// boolean values from i1 to a wider type. See getBooleanContents.
1940 void setBooleanContents(BooleanContent Ty) {
1941 BooleanContents = Ty;
1942 BooleanFloatContents = Ty;
1943 }
1944
1945 /// Specify how the target extends the result of integer and floating point
1946 /// boolean values from i1 to a wider type. See getBooleanContents.
1947 void setBooleanContents(BooleanContent IntTy, BooleanContent FloatTy) {
1948 BooleanContents = IntTy;
1949 BooleanFloatContents = FloatTy;
1950 }
1951
1952 /// Specify how the target extends the result of a vector boolean value from a
1953 /// vector of i1 to a wider type. See getBooleanContents.
1954 void setBooleanVectorContents(BooleanContent Ty) {
1955 BooleanVectorContents = Ty;
1956 }
1957
1958 /// Specify the target scheduling preference.
1959 void setSchedulingPreference(Sched::Preference Pref) {
1960 SchedPreferenceInfo = Pref;
1961 }
1962
1963 /// Indicate whether this target prefers to use _setjmp to implement
1964 /// llvm.setjmp or the version without _. Defaults to false.
1965 void setUseUnderscoreSetJmp(bool Val) {
1966 UseUnderscoreSetJmp = Val;
1967 }
1968
1969 /// Indicate whether this target prefers to use _longjmp to implement
1970 /// llvm.longjmp or the version without _. Defaults to false.
1971 void setUseUnderscoreLongJmp(bool Val) {
1972 UseUnderscoreLongJmp = Val;
1973 }
1974
1975 /// Indicate the minimum number of blocks to generate jump tables.
1976 void setMinimumJumpTableEntries(unsigned Val);
1977
1978 /// Indicate the maximum number of entries in jump tables.
1979 /// Set to zero to generate unlimited jump tables.
1980 void setMaximumJumpTableSize(unsigned);
1981
1982 /// If set to a physical register, this specifies the register that
1983 /// llvm.savestack/llvm.restorestack should save and restore.
1984 void setStackPointerRegisterToSaveRestore(unsigned R) {
1985 StackPointerRegisterToSaveRestore = R;
1986 }
1987
1988 /// Tells the code generator that the target has multiple (allocatable)
1989 /// condition registers that can be used to store the results of comparisons
1990 /// for use by selects and conditional branches. With multiple condition
1991 /// registers, the code generator will not aggressively sink comparisons into
1992 /// the blocks of their users.
1993 void setHasMultipleConditionRegisters(bool hasManyRegs = true) {
1994 HasMultipleConditionRegisters = hasManyRegs;
1995 }
1996
1997 /// Tells the code generator that the target has BitExtract instructions.
1998 /// The code generator will aggressively sink "shift"s into the blocks of
1999 /// their users if the users will generate "and" instructions which can be
2000 /// combined with "shift" to BitExtract instructions.
2001 void setHasExtractBitsInsn(bool hasExtractInsn = true) {
2002 HasExtractBitsInsn = hasExtractInsn;
2003 }
2004
2005 /// Tells the code generator not to expand logic operations on comparison
2006 /// predicates into separate sequences that increase the amount of flow
2007 /// control.
2008 void setJumpIsExpensive(bool isExpensive = true);
2009
2010 /// Tells the code generator which bitwidths to bypass.
2011 void addBypassSlowDiv(unsigned int SlowBitWidth, unsigned int FastBitWidth) {
2012 BypassSlowDivWidths[SlowBitWidth] = FastBitWidth;
2013 }
2014
2015 /// Add the specified register class as an available regclass for the
2016 /// specified value type. This indicates the selector can handle values of
2017 /// that class natively.
2018 void addRegisterClass(MVT VT, const TargetRegisterClass *RC) {
2019 assert((unsigned)VT.SimpleTy < array_lengthof(RegClassForVT))(((unsigned)VT.SimpleTy < array_lengthof(RegClassForVT)) ?
static_cast<void> (0) : __assert_fail ("(unsigned)VT.SimpleTy < array_lengthof(RegClassForVT)"
, "/build/llvm-toolchain-snapshot-10~svn374814/include/llvm/CodeGen/TargetLowering.h"
, 2019, __PRETTY_FUNCTION__))
;
2020 RegClassForVT[VT.SimpleTy] = RC;
2021 }
2022
2023 /// Return the largest legal super-reg register class of the register class
2024 /// for the specified type and its associated "cost".
2025 virtual std::pair<const TargetRegisterClass *, uint8_t>
2026 findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const;
2027
2028 /// Once all of the register classes are added, this allows us to compute
2029 /// derived properties we expose.
2030 void computeRegisterProperties(const TargetRegisterInfo *TRI);
2031
2032 /// Indicate that the specified operation does not work with the specified
2033 /// type and indicate what to do about it. Note that VT may refer to either
2034 /// the type of a result or that of an operand of Op.
2035 void setOperationAction(unsigned Op, MVT VT,
2036 LegalizeAction Action) {
2037 assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!")((Op < array_lengthof(OpActions[0]) && "Table isn't big enough!"
) ? static_cast<void> (0) : __assert_fail ("Op < array_lengthof(OpActions[0]) && \"Table isn't big enough!\""
, "/build/llvm-toolchain-snapshot-10~svn374814/include/llvm/CodeGen/TargetLowering.h"
, 2037, __PRETTY_FUNCTION__))
;
2038 OpActions[(unsigned)VT.SimpleTy][Op] = Action;
2039 }
2040
2041 /// Indicate that the specified load with extension does not work with the
2042 /// specified type and indicate what to do about it.
2043 void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT,
2044 LegalizeAction Action) {
2045 assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValVT.isValid() &&((ExtType < ISD::LAST_LOADEXT_TYPE && ValVT.isValid
() && MemVT.isValid() && "Table isn't big enough!"
) ? static_cast<void> (0) : __assert_fail ("ExtType < ISD::LAST_LOADEXT_TYPE && ValVT.isValid() && MemVT.isValid() && \"Table isn't big enough!\""
, "/build/llvm-toolchain-snapshot-10~svn374814/include/llvm/CodeGen/TargetLowering.h"
, 2046, __PRETTY_FUNCTION__))
2046 MemVT.isValid() && "Table isn't big enough!")((ExtType < ISD::LAST_LOADEXT_TYPE && ValVT.isValid
() && MemVT.isValid() && "Table isn't big enough!"
) ? static_cast<void> (0) : __assert_fail ("ExtType < ISD::LAST_LOADEXT_TYPE && ValVT.isValid() && MemVT.isValid() && \"Table isn't big enough!\""
, "/build/llvm-toolchain-snapshot-10~svn374814/include/llvm/CodeGen/TargetLowering.h"
, 2046, __PRETTY_FUNCTION__))
;
2047 assert((unsigned)Action < 0x10 && "too many bits for bitfield array")(((unsigned)Action < 0x10 && "too many bits for bitfield array"
) ? static_cast<void> (0) : __assert_fail ("(unsigned)Action < 0x10 && \"too many bits for bitfield array\""
, "/build/llvm-toolchain-snapshot-10~svn374814/include/llvm/CodeGen/TargetLowering.h"
, 2047, __PRETTY_FUNCTION__))
;
2048 unsigned Shift = 4 * ExtType;
2049 LoadExtActions[ValVT.SimpleTy][MemVT.SimpleTy] &= ~((uint16_t)0xF << Shift);
2050 LoadExtActions[ValVT.SimpleTy][MemVT.SimpleTy] |= (uint16_t)Action << Shift;
2051 }
2052
2053 /// Indicate that the specified truncating store does not work with the
2054 /// specified type and indicate what to do about it.
2055 void setTruncStoreAction(MVT ValVT, MVT MemVT,
2056 LegalizeAction Action) {
2057 assert(ValVT.isValid() && MemVT.isValid() && "Table isn't big enough!")((ValVT.isValid() && MemVT.isValid() && "Table isn't big enough!"
) ? static_cast<void> (0) : __assert_fail ("ValVT.isValid() && MemVT.isValid() && \"Table isn't big enough!\""
, "/build/llvm-toolchain-snapshot-10~svn374814/include/llvm/CodeGen/TargetLowering.h"
, 2057, __PRETTY_FUNCTION__))
;
2058 TruncStoreActions[(unsigned)ValVT.SimpleTy][MemVT.SimpleTy] = Action;
2059 }
2060
2061 /// Indicate that the specified indexed load does or does not work with the
2062 /// specified type and indicate what to do abort it.
2063 ///
2064 /// NOTE: All indexed mode loads are initialized to Expand in
2065 /// TargetLowering.cpp
2066 void setIndexedLoadAction(unsigned IdxMode, MVT VT,
2067 LegalizeAction Action) {
2068 assert(VT.isValid() && IdxMode < ISD::LAST_INDEXED_MODE &&((VT.isValid() && IdxMode < ISD::LAST_INDEXED_MODE
&& (unsigned)Action < 0xf && "Table isn't big enough!"
) ? static_cast<void> (0) : __assert_fail ("VT.isValid() && IdxMode < ISD::LAST_INDEXED_MODE && (unsigned)Action < 0xf && \"Table isn't big enough!\""
, "/build/llvm-toolchain-snapshot-10~svn374814/include/llvm/CodeGen/TargetLowering.h"
, 2069, __PRETTY_FUNCTION__))
2069 (unsigned)Action < 0xf && "Table isn't big enough!")((VT.isValid() && IdxMode < ISD::LAST_INDEXED_MODE
&& (unsigned)Action < 0xf && "Table isn't big enough!"
) ? static_cast<void> (0) : __assert_fail ("VT.isValid() && IdxMode < ISD::LAST_INDEXED_MODE && (unsigned)Action < 0xf && \"Table isn't big enough!\""
, "/build/llvm-toolchain-snapshot-10~svn374814/include/llvm/CodeGen/TargetLowering.h"
, 2069, __PRETTY_FUNCTION__))
;
2070 // Load action are kept in the upper half.
2071 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0xf0;
2072 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action) <<4;
2073 }
2074
2075 /// Indicate that the specified indexed store does or does not work with the
2076 /// specified type and indicate what to do about it.
2077 ///
2078 /// NOTE: All indexed mode stores are initialized to Expand in
2079 /// TargetLowering.cpp
2080 void setIndexedStoreAction(unsigned IdxMode, MVT VT,
2081 LegalizeAction Action) {
2082 assert(VT.isValid() && IdxMode < ISD::LAST_INDEXED_MODE &&((VT.isValid() && IdxMode < ISD::LAST_INDEXED_MODE
&& (unsigned)Action < 0xf && "Table isn't big enough!"
) ? static_cast<void> (0) : __assert_fail ("VT.isValid() && IdxMode < ISD::LAST_INDEXED_MODE && (unsigned)Action < 0xf && \"Table isn't big enough!\""
, "/build/llvm-toolchain-snapshot-10~svn374814/include/llvm/CodeGen/TargetLowering.h"
, 2083, __PRETTY_FUNCTION__))
2083 (unsigned)Action < 0xf && "Table isn't big enough!")((VT.isValid() && IdxMode < ISD::LAST_INDEXED_MODE
&& (unsigned)Action < 0xf && "Table isn't big enough!"
) ? static_cast<void> (0) : __assert_fail ("VT.isValid() && IdxMode < ISD::LAST_INDEXED_MODE && (unsigned)Action < 0xf && \"Table isn't big enough!\""
, "/build/llvm-toolchain-snapshot-10~svn374814/include/llvm/CodeGen/TargetLowering.h"
, 2083, __PRETTY_FUNCTION__))
;
2084 // Store action are kept in the lower half.
2085 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0x0f;
2086 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action);
2087 }
2088
2089 /// Indicate that the specified condition code is or isn't supported on the
2090 /// target and indicate what to do about it.
2091 void setCondCodeAction(ISD::CondCode CC, MVT VT,
2092 LegalizeAction Action) {
2093 assert(VT.isValid() && (unsigned)CC < array_lengthof(CondCodeActions) &&((VT.isValid() && (unsigned)CC < array_lengthof(CondCodeActions
) && "Table isn't big enough!") ? static_cast<void
> (0) : __assert_fail ("VT.isValid() && (unsigned)CC < array_lengthof(CondCodeActions) && \"Table isn't big enough!\""
, "/build/llvm-toolchain-snapshot-10~svn374814/include/llvm/CodeGen/TargetLowering.h"
, 2094, __PRETTY_FUNCTION__))
2094 "Table isn't big enough!")((VT.isValid() && (unsigned)CC < array_lengthof(CondCodeActions
) && "Table isn't big enough!") ? static_cast<void
> (0) : __assert_fail ("VT.isValid() && (unsigned)CC < array_lengthof(CondCodeActions) && \"Table isn't big enough!\""
, "/build/llvm-toolchain-snapshot-10~svn374814/include/llvm/CodeGen/TargetLowering.h"
, 2094, __PRETTY_FUNCTION__))
;
2095 assert((unsigned)Action < 0x10 && "too many bits for bitfield array")(((unsigned)Action < 0x10 && "too many bits for bitfield array"
) ? static_cast<void> (0) : __assert_fail ("(unsigned)Action < 0x10 && \"too many bits for bitfield array\""
, "/build/llvm-toolchain-snapshot-10~svn374814/include/llvm/CodeGen/TargetLowering.h"
, 2095, __PRETTY_FUNCTION__))
;
2096 /// The lower 3 bits of the SimpleTy index into Nth 4bit set from the 32-bit
2097 /// value and the upper 29 bits index into the second dimension of the array
2098 /// to select what 32-bit value to use.
2099 uint32_t Shift = 4 * (VT.SimpleTy & 0x7);
2100 CondCodeActions[CC][VT.SimpleTy >> 3] &= ~((uint32_t)0xF << Shift);
2101 CondCodeActions[CC][VT.SimpleTy >> 3] |= (uint32_t)Action << Shift;
2102 }
2103
2104 /// If Opc/OrigVT is specified as being promoted, the promotion code defaults
2105 /// to trying a larger integer/fp until it can find one that works. If that
2106 /// default is insufficient, this method can be used by the target to override
2107 /// the default.
2108 void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
2109 PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy;
2110 }
2111
2112 /// Convenience method to set an operation to Promote and specify the type
2113 /// in a single call.
2114 void setOperationPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
2115 setOperationAction(Opc, OrigVT, Promote);
2116 AddPromotedToType(Opc, OrigVT, DestVT);
2117 }
2118
2119 /// Targets should invoke this method for each target independent node that
2120 /// they want to provide a custom DAG combiner for by implementing the
2121 /// PerformDAGCombine virtual method.
2122 void setTargetDAGCombine(ISD::NodeType NT) {
2123 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray))((unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray
)) ? static_cast<void> (0) : __assert_fail ("unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray)"
, "/build/llvm-toolchain-snapshot-10~svn374814/include/llvm/CodeGen/TargetLowering.h"
, 2123, __PRETTY_FUNCTION__))
;
2124 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
2125 }
2126
2127 /// Set the target's minimum function alignment.
2128 void setMinFunctionAlignment(Align Alignment) {
2129 MinFunctionAlignment = Alignment;
2130 }
2131
2132 /// Set the target's preferred function alignment. This should be set if
2133 /// there is a performance benefit to higher-than-minimum alignment
2134 void setPrefFunctionAlignment(Align Alignment) {
2135 PrefFunctionAlignment = Alignment;
2136 }
2137
2138 /// Set the target's preferred loop alignment. Default alignment is one, it
2139 /// means the target does not care about loop alignment. The target may also
2140 /// override getPrefLoopAlignment to provide per-loop values.
2141 void setPrefLoopAlignment(Align Alignment) { PrefLoopAlignment = Alignment; }
2142
2143 /// Set the minimum stack alignment of an argument.
2144 void setMinStackArgumentAlignment(Align Alignment) {
2145 MinStackArgumentAlignment = Alignment;
2146 }
2147
2148 /// Set the maximum atomic operation size supported by the
2149 /// backend. Atomic operations greater than this size (as well as
2150 /// ones that are not naturally aligned), will be expanded by
2151 /// AtomicExpandPass into an __atomic_* library call.
2152 void setMaxAtomicSizeInBitsSupported(unsigned SizeInBits) {
2153 MaxAtomicSizeInBitsSupported = SizeInBits;
2154 }
2155
2156 /// Sets the minimum cmpxchg or ll/sc size supported by the backend.
2157 void setMinCmpXchgSizeInBits(unsigned SizeInBits) {
2158 MinCmpXchgSizeInBits = SizeInBits;
2159 }
2160
2161 /// Sets whether unaligned atomic operations are supported.
2162 void setSupportsUnalignedAtomics(bool UnalignedSupported) {
2163 SupportsUnalignedAtomics = UnalignedSupported;
2164 }
2165
2166public:
2167 //===--------------------------------------------------------------------===//
2168 // Addressing mode description hooks (used by LSR etc).
2169 //
2170
2171 /// CodeGenPrepare sinks address calculations into the same BB as Load/Store
2172 /// instructions reading the address. This allows as much computation as
2173 /// possible to be done in the address mode for that operand. This hook lets
2174 /// targets also pass back when this should be done on intrinsics which
2175 /// load/store.
2176 virtual bool getAddrModeArguments(IntrinsicInst * /*I*/,
2177 SmallVectorImpl<Value*> &/*Ops*/,
2178 Type *&/*AccessTy*/) const {
2179 return false;
2180 }
2181
2182 /// This represents an addressing mode of:
2183 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
2184 /// If BaseGV is null, there is no BaseGV.
2185 /// If BaseOffs is zero, there is no base offset.
2186 /// If HasBaseReg is false, there is no base register.
2187 /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with
2188 /// no scale.
2189 struct AddrMode {
2190 GlobalValue *BaseGV = nullptr;
2191 int64_t BaseOffs = 0;
2192 bool HasBaseReg = false;
2193 int64_t Scale = 0;
2194 AddrMode() = default;
2195 };
2196
2197 /// Return true if the addressing mode represented by AM is legal for this
2198 /// target, for a load/store of the specified type.
2199 ///
2200 /// The type may be VoidTy, in which case only return true if the addressing
2201 /// mode is legal for a load/store of any legal type. TODO: Handle
2202 /// pre/postinc as well.
2203 ///
2204 /// If the address space cannot be determined, it will be -1.
2205 ///
2206 /// TODO: Remove default argument
2207 virtual bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
2208 Type *Ty, unsigned AddrSpace,
2209 Instruction *I = nullptr) const;
2210
2211 /// Return the cost of the scaling factor used in the addressing mode
2212 /// represented by AM for this target, for a load/store of the specified type.
2213 ///
2214 /// If the AM is supported, the return value must be >= 0.
2215 /// If the AM is not supported, it returns a negative value.
2216 /// TODO: Handle pre/postinc as well.
2217 /// TODO: Remove default argument
2218 virtual int getScalingFactorCost(const DataLayout &DL, const AddrMode &AM,
2219 Type *Ty, unsigned AS = 0) const {
2220 // Default: assume that any scaling factor used in a legal AM is free.
2221 if (isLegalAddressingMode(DL, AM, Ty, AS))
2222 return 0;
2223 return -1;
2224 }
2225
2226 /// Return true if the specified immediate is legal icmp immediate, that is
2227 /// the target has icmp instructions which can compare a register against the
2228 /// immediate without having to materialize the immediate into a register.
2229 virtual bool isLegalICmpImmediate(int64_t) const {
2230 return true;
2231 }
2232
2233 /// Return true if the specified immediate is legal add immediate, that is the
2234 /// target has add instructions which can add a register with the immediate
2235 /// without having to materialize the immediate into a register.
2236 virtual bool isLegalAddImmediate(int64_t) const {
2237 return true;
2238 }
2239
2240 /// Return true if the specified immediate is legal for the value input of a
2241 /// store instruction.
2242 virtual bool isLegalStoreImmediate(int64_t Value) const {
2243 // Default implementation assumes that at least 0 works since it is likely
2244 // that a zero register exists or a zero immediate is allowed.
2245 return Value == 0;
2246 }
2247
2248 /// Return true if it's significantly cheaper to shift a vector by a uniform
2249 /// scalar than by an amount which will vary across each lane. On x86, for
2250 /// example, there is a "psllw" instruction for the former case, but no simple
2251 /// instruction for a general "a << b" operation on vectors.
2252 virtual bool isVectorShiftByScalarCheap(Type *Ty) const {
2253 return false;
2254 }
2255
2256 /// Returns true if the opcode is a commutative binary operation.
2257 virtual bool isCommutativeBinOp(unsigned Opcode) const {
2258 // FIXME: This should get its info from the td file.
2259 switch (Opcode) {
2260 case ISD::ADD:
2261 case ISD::SMIN:
2262 case ISD::SMAX:
2263 case ISD::UMIN:
2264 case ISD::UMAX:
2265 case ISD::MUL:
2266 case ISD::MULHU:
2267 case ISD::MULHS:
2268 case ISD::SMUL_LOHI:
2269 case ISD::UMUL_LOHI:
2270 case ISD::FADD:
2271 case ISD::FMUL:
2272 case ISD::AND:
2273 case ISD::OR:
2274 case ISD::XOR:
2275 case ISD::SADDO:
2276 case ISD::UADDO:
2277 case ISD::ADDC:
2278 case ISD::ADDE:
2279 case ISD::SADDSAT:
2280 case ISD::UADDSAT:
2281 case ISD::FMINNUM:
2282 case ISD::FMAXNUM:
2283 case ISD::FMINNUM_IEEE:
2284 case ISD::FMAXNUM_IEEE:
2285 case ISD::FMINIMUM:
2286 case ISD::FMAXIMUM:
2287 return true;
2288 default: return false;
2289 }
2290 }
2291
2292 /// Return true if the node is a math/logic binary operator.
2293 virtual bool isBinOp(unsigned Opcode) const {
2294 // A commutative binop must be a binop.
2295 if (isCommutativeBinOp(Opcode))
2296 return true;
2297 // These are non-commutative binops.
2298 switch (Opcode) {
2299 case ISD::SUB:
2300 case ISD::SHL:
2301 case ISD::SRL:
2302 case ISD::SRA:
2303 case ISD::SDIV:
2304 case ISD::UDIV:
2305 case ISD::SREM:
2306 case ISD::UREM:
2307 case ISD::FSUB:
2308 case ISD::FDIV:
2309 case ISD::FREM:
2310 return true;
2311 default:
2312 return false;
2313 }
2314 }
2315
2316 /// Return true if it's free to truncate a value of type FromTy to type
2317 /// ToTy. e.g. On x86 it's free to truncate a i32 value in register EAX to i16
2318 /// by referencing its sub-register AX.
2319 /// Targets must return false when FromTy <= ToTy.
2320 virtual bool isTruncateFree(Type *FromTy, Type *ToTy) const {
2321 return false;
2322 }
2323
2324 /// Return true if a truncation from FromTy to ToTy is permitted when deciding
2325 /// whether a call is in tail position. Typically this means that both results
2326 /// would be assigned to the same register or stack slot, but it could mean
2327 /// the target performs adequate checks of its own before proceeding with the
2328 /// tail call. Targets must return false when FromTy <= ToTy.
2329 virtual bool allowTruncateForTailCall(Type *FromTy, Type *ToTy) const {
2330 return false;
2331 }
2332
2333 virtual bool isTruncateFree(EVT FromVT, EVT ToVT) const {
2334 return false;
2335 }
2336
2337 virtual bool isProfitableToHoist(Instruction *I) const { return true; }
2338
2339 /// Return true if the extension represented by \p I is free.
2340 /// Unlikely the is[Z|FP]ExtFree family which is based on types,
2341 /// this method can use the context provided by \p I to decide
2342 /// whether or not \p I is free.
2343 /// This method extends the behavior of the is[Z|FP]ExtFree family.
2344 /// In other words, if is[Z|FP]Free returns true, then this method
2345 /// returns true as well. The converse is not true.
2346 /// The target can perform the adequate checks by overriding isExtFreeImpl.
2347 /// \pre \p I must be a sign, zero, or fp extension.
2348 bool isExtFree(const Instruction *I) const {
2349 switch (I->getOpcode()) {
2350 case Instruction::FPExt:
2351 if (isFPExtFree(EVT::getEVT(I->getType()),
2352 EVT::getEVT(I->getOperand(0)->getType())))
2353 return true;
2354 break;
2355 case Instruction::ZExt:
2356 if (isZExtFree(I->getOperand(0)->getType(), I->getType()))
2357 return true;
2358 break;
2359 case Instruction::SExt:
2360 break;
2361 default:
2362 llvm_unreachable("Instruction is not an extension")::llvm::llvm_unreachable_internal("Instruction is not an extension"
, "/build/llvm-toolchain-snapshot-10~svn374814/include/llvm/CodeGen/TargetLowering.h"
, 2362)
;
2363 }
2364 return isExtFreeImpl(I);
2365 }
2366
2367 /// Return true if \p Load and \p Ext can form an ExtLoad.
2368 /// For example, in AArch64
2369 /// %L = load i8, i8* %ptr
2370 /// %E = zext i8 %L to i32
2371 /// can be lowered into one load instruction
2372 /// ldrb w0, [x0]
2373 bool isExtLoad(const LoadInst *Load, const Instruction *Ext,
2374 const DataLayout &DL) const {
2375 EVT VT = getValueType(DL, Ext->getType());
2376 EVT LoadVT = getValueType(DL, Load->getType());
2377
2378 // If the load has other users and the truncate is not free, the ext
2379 // probably isn't free.
2380 if (!Load->hasOneUse() && (isTypeLegal(LoadVT) || !isTypeLegal(VT)) &&
2381 !isTruncateFree(Ext->getType(), Load->getType()))
2382 return false;
2383
2384 // Check whether the target supports casts folded into loads.
2385 unsigned LType;
2386 if (isa<ZExtInst>(Ext))
2387 LType = ISD::ZEXTLOAD;
2388 else {
2389 assert(isa<SExtInst>(Ext) && "Unexpected ext type!")((isa<SExtInst>(Ext) && "Unexpected ext type!")
? static_cast<void> (0) : __assert_fail ("isa<SExtInst>(Ext) && \"Unexpected ext type!\""
, "/build/llvm-toolchain-snapshot-10~svn374814/include/llvm/CodeGen/TargetLowering.h"
, 2389, __PRETTY_FUNCTION__))
;
2390 LType = ISD::SEXTLOAD;
2391 }
2392
2393 return isLoadExtLegal(LType, VT, LoadVT);
2394 }
2395
2396 /// Return true if any actual instruction that defines a value of type FromTy
2397 /// implicitly zero-extends the value to ToTy in the result register.
2398 ///
2399 /// The function should return true when it is likely that the truncate can
2400 /// be freely folded with an instruction defining a value of FromTy. If
2401 /// the defining instruction is unknown (because you're looking at a
2402 /// function argument, PHI, etc.) then the target may require an
2403 /// explicit truncate, which is not necessarily free, but this function
2404 /// does not deal with those cases.
2405 /// Targets must return false when FromTy >= ToTy.
2406 virtual bool isZExtFree(Type *FromTy, Type *ToTy) const {
2407 return false;
2408 }
2409
2410 virtual bool isZExtFree(EVT FromTy, EVT ToTy) const {
2411 return false;
2412 }
2413
2414 /// Return true if sign-extension from FromTy to ToTy is cheaper than
2415 /// zero-extension.
2416 virtual bool isSExtCheaperThanZExt(EVT FromTy, EVT ToTy) const {
2417 return false;
2418 }
2419
2420 /// Return true if sinking I's operands to the same basic block as I is
2421 /// profitable, e.g. because the operands can be folded into a target
2422 /// instruction during instruction selection. After calling the function
2423 /// \p Ops contains the Uses to sink ordered by dominance (dominating users
2424 /// come first).
2425 virtual bool shouldSinkOperands(Instruction *I,
2426 SmallVectorImpl<Use *> &Ops) const {
2427 return false;
2428 }
2429
2430 /// Return true if the target supplies and combines to a paired load
2431 /// two loaded values of type LoadedType next to each other in memory.
2432 /// RequiredAlignment gives the minimal alignment constraints that must be met
2433 /// to be able to select this paired load.
2434 ///
2435 /// This information is *not* used to generate actual paired loads, but it is
2436 /// used to generate a sequence of loads that is easier to combine into a
2437 /// paired load.
2438 /// For instance, something like this:
2439 /// a = load i64* addr
2440 /// b = trunc i64 a to i32
2441 /// c = lshr i64 a, 32
2442 /// d = trunc i64 c to i32
2443 /// will be optimized into:
2444 /// b = load i32* addr1
2445 /// d = load i32* addr2
2446 /// Where addr1 = addr2 +/- sizeof(i32).
2447 ///
2448 /// In other words, unless the target performs a post-isel load combining,
2449 /// this information should not be provided because it will generate more
2450 /// loads.
2451 virtual bool hasPairedLoad(EVT /*LoadedType*/,
2452 unsigned & /*RequiredAlignment*/) const {
2453 return false;
2454 }
2455
2456 /// Return true if the target has a vector blend instruction.
2457 virtual bool hasVectorBlend() const { return false; }
2458
2459 /// Get the maximum supported factor for interleaved memory accesses.
2460 /// Default to be the minimum interleave factor: 2.
2461 virtual unsigned getMaxSupportedInterleaveFactor() const { return 2; }
2462
2463 /// Lower an interleaved load to target specific intrinsics. Return
2464 /// true on success.
2465 ///
2466 /// \p LI is the vector load instruction.
2467 /// \p Shuffles is the shufflevector list to DE-interleave the loaded vector.
2468 /// \p Indices is the corresponding indices for each shufflevector.
2469 /// \p Factor is the interleave factor.
2470 virtual bool lowerInterleavedLoad(LoadInst *LI,
2471 ArrayRef<ShuffleVectorInst *> Shuffles,
2472 ArrayRef<unsigned> Indices,
2473 unsigned Factor) const {
2474 return false;
2475 }
2476
2477 /// Lower an interleaved store to target specific intrinsics. Return
2478 /// true on success.
2479 ///
2480 /// \p SI is the vector store instruction.
2481 /// \p SVI is the shufflevector to RE-interleave the stored vector.
2482 /// \p Factor is the interleave factor.
2483 virtual bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI,
2484 unsigned Factor) const {
2485 return false;
2486 }
2487
2488 /// Return true if zero-extending the specific node Val to type VT2 is free
2489 /// (either because it's implicitly zero-extended such as ARM ldrb / ldrh or
2490 /// because it's folded such as X86 zero-extending loads).
2491 virtual bool isZExtFree(SDValue Val, EVT VT2) const {
2492 return isZExtFree(Val.getValueType(), VT2);
5
Calling 'SDValue::getValueType'
2493 }
2494
2495 /// Return true if an fpext operation is free (for instance, because
2496 /// single-precision floating-point numbers are implicitly extended to
2497 /// double-precision).
2498 virtual bool isFPExtFree(EVT DestVT, EVT SrcVT) const {
2499 assert(SrcVT.isFloatingPoint() && DestVT.isFloatingPoint() &&((SrcVT.isFloatingPoint() && DestVT.isFloatingPoint()
&& "invalid fpext types") ? static_cast<void> (
0) : __assert_fail ("SrcVT.isFloatingPoint() && DestVT.isFloatingPoint() && \"invalid fpext types\""
, "/build/llvm-toolchain-snapshot-10~svn374814/include/llvm/CodeGen/TargetLowering.h"
, 2500, __PRETTY_FUNCTION__))
2500 "invalid fpext types")((SrcVT.isFloatingPoint() && DestVT.isFloatingPoint()
&& "invalid fpext types") ? static_cast<void> (
0) : __assert_fail ("SrcVT.isFloatingPoint() && DestVT.isFloatingPoint() && \"invalid fpext types\""
, "/build/llvm-toolchain-snapshot-10~svn374814/include/llvm/CodeGen/TargetLowering.h"
, 2500, __PRETTY_FUNCTION__))
;
2501 return false;
2502 }
2503
2504 /// Return true if an fpext operation input to an \p Opcode operation is free
2505 /// (for instance, because half-precision floating-point numbers are
2506 /// implicitly extended to float-precision) for an FMA instruction.
2507 virtual bool isFPExtFoldable(unsigned Opcode, EVT DestVT, EVT SrcVT) const {
2508 assert(DestVT.isFloatingPoint() && SrcVT.isFloatingPoint() &&((DestVT.isFloatingPoint() && SrcVT.isFloatingPoint()
&& "invalid fpext types") ? static_cast<void> (
0) : __assert_fail ("DestVT.isFloatingPoint() && SrcVT.isFloatingPoint() && \"invalid fpext types\""
, "/build/llvm-toolchain-snapshot-10~svn374814/include/llvm/CodeGen/TargetLowering.h"
, 2509, __PRETTY_FUNCTION__))
2509 "invalid fpext types")((DestVT.isFloatingPoint() && SrcVT.isFloatingPoint()
&& "invalid fpext types") ? static_cast<void> (
0) : __assert_fail ("DestVT.isFloatingPoint() && SrcVT.isFloatingPoint() && \"invalid fpext types\""
, "/build/llvm-toolchain-snapshot-10~svn374814/include/llvm/CodeGen/TargetLowering.h"
, 2509, __PRETTY_FUNCTION__))
;
2510 return isFPExtFree(DestVT, SrcVT);
2511 }
2512
2513 /// Return true if folding a vector load into ExtVal (a sign, zero, or any
2514 /// extend node) is profitable.
2515 virtual bool isVectorLoadExtDesirable(SDValue ExtVal) const { return false; }
2516
2517 /// Return true if an fneg operation is free to the point where it is never
2518 /// worthwhile to replace it with a bitwise operation.
2519 virtual bool isFNegFree(EVT VT) const {
2520 assert(VT.isFloatingPoint())((VT.isFloatingPoint()) ? static_cast<void> (0) : __assert_fail
("VT.isFloatingPoint()", "/build/llvm-toolchain-snapshot-10~svn374814/include/llvm/CodeGen/TargetLowering.h"
, 2520, __PRETTY_FUNCTION__))
;
2521 return false;
2522 }
2523
2524 /// Return true if an fabs operation is free to the point where it is never
2525 /// worthwhile to replace it with a bitwise operation.
2526 virtual bool isFAbsFree(EVT VT) const {
2527 assert(VT.isFloatingPoint())((VT.isFloatingPoint()) ? static_cast<void> (0) : __assert_fail
("VT.isFloatingPoint()", "/build/llvm-toolchain-snapshot-10~svn374814/include/llvm/CodeGen/TargetLowering.h"
, 2527, __PRETTY_FUNCTION__))
;
2528 return false;
2529 }
2530
2531 /// Return true if an FMA operation is faster than a pair of fmul and fadd
2532 /// instructions. fmuladd intrinsics will be expanded to FMAs when this method
2533 /// returns true, otherwise fmuladd is expanded to fmul + fadd.
2534 ///
2535 /// NOTE: This may be called before legalization on types for which FMAs are
2536 /// not legal, but should return true if those types will eventually legalize
2537 /// to types that support FMAs. After legalization, it will only be called on
2538 /// types that support FMAs (via Legal or Custom actions)
2539 virtual bool isFMAFasterThanFMulAndFAdd(EVT) const {
2540 return false;
2541 }
2542
2543 /// Return true if it's profitable to narrow operations of type VT1 to
2544 /// VT2. e.g. on x86, it's profitable to narrow from i32 to i8 but not from
2545 /// i32 to i16.
2546 virtual bool isNarrowingProfitable(EVT /*VT1*/, EVT /*VT2*/) const {
2547 return false;
2548 }
2549
2550 /// Return true if it is beneficial to convert a load of a constant to
2551 /// just the constant itself.
2552 /// On some targets it might be more efficient to use a combination of
2553 /// arithmetic instructions to materialize the constant instead of loading it
2554 /// from a constant pool.
2555 virtual bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
2556 Type *Ty) const {
2557 return false;
2558 }
2559
2560 /// Return true if EXTRACT_SUBVECTOR is cheap for extracting this result type
2561 /// from this source type with this index. This is needed because
2562 /// EXTRACT_SUBVECTOR usually has custom lowering that depends on the index of
2563 /// the first element, and only the target knows which lowering is cheap.
2564 virtual bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
2565 unsigned Index) const {
2566 return false;
2567 }
2568
2569 /// Try to convert an extract element of a vector binary operation into an
2570 /// extract element followed by a scalar operation.
2571 virtual bool shouldScalarizeBinop(SDValue VecOp) const {
2572 return false;
2573 }
2574
2575 /// Return true if extraction of a scalar element from the given vector type
2576 /// at the given index is cheap. For example, if scalar operations occur on
2577 /// the same register file as vector operations, then an extract element may
2578 /// be a sub-register rename rather than an actual instruction.
2579 virtual bool isExtractVecEltCheap(EVT VT, unsigned Index) const {
2580 return false;
2581 }
2582
2583 /// Try to convert math with an overflow comparison into the corresponding DAG
2584 /// node operation. Targets may want to override this independently of whether
2585 /// the operation is legal/custom for the given type because it may obscure
2586 /// matching of other patterns.
2587 virtual bool shouldFormOverflowOp(unsigned Opcode, EVT VT) const {
2588 // TODO: The default logic is inherited from code in CodeGenPrepare.
2589 // The opcode should not make a difference by default?
2590 if (Opcode != ISD::UADDO)
2591 return false;
2592
2593 // Allow the transform as long as we have an integer type that is not
2594 // obviously illegal and unsupported.
2595 if (VT.isVector())
2596 return false;
2597 return VT.isSimple() || !isOperationExpand(Opcode, VT);
2598 }
2599
2600 // Return true if it is profitable to use a scalar input to a BUILD_VECTOR
2601 // even if the vector itself has multiple uses.
2602 virtual bool aggressivelyPreferBuildVectorSources(EVT VecVT) const {
2603 return false;
2604 }
2605
2606 // Return true if CodeGenPrepare should consider splitting large offset of a
2607 // GEP to make the GEP fit into the addressing mode and can be sunk into the
2608 // same blocks of its users.
2609 virtual bool shouldConsiderGEPOffsetSplit() const { return false; }
2610
2611 //===--------------------------------------------------------------------===//
2612 // Runtime Library hooks
2613 //
2614
2615 /// Rename the default libcall routine name for the specified libcall.
2616 void setLibcallName(RTLIB::Libcall Call, const char *Name) {
2617 LibcallRoutineNames[Call] = Name;
2618 }
2619
2620 /// Get the libcall routine name for the specified libcall.
2621 const char *getLibcallName(RTLIB::Libcall Call) const {
2622 return LibcallRoutineNames[Call];
2623 }
2624
2625 /// Override the default CondCode to be used to test the result of the
2626 /// comparison libcall against zero.
2627 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) {
2628 CmpLibcallCCs[Call] = CC;
2629 }
2630
2631 /// Get the CondCode that's to be used to test the result of the comparison
2632 /// libcall against zero.
2633 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const {
2634 return CmpLibcallCCs[Call];
2635 }
2636
2637 /// Set the CallingConv that should be used for the specified libcall.
2638 void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC) {
2639 LibcallCallingConvs[Call] = CC;
2640 }
2641
2642 /// Get the CallingConv that should be used for the specified libcall.
2643 CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const {
2644 return LibcallCallingConvs[Call];
2645 }
2646
2647 /// Execute target specific actions to finalize target lowering.
2648 /// This is used to set extra flags in MachineFrameInformation and freezing
2649 /// the set of reserved registers.
2650 /// The default implementation just freezes the set of reserved registers.
2651 virtual void finalizeLowering(MachineFunction &MF) const;
2652
2653private:
2654 const TargetMachine &TM;
2655
2656 /// Tells the code generator that the target has multiple (allocatable)
2657 /// condition registers that can be used to store the results of comparisons
2658 /// for use by selects and conditional branches. With multiple condition
2659 /// registers, the code generator will not aggressively sink comparisons into
2660 /// the blocks of their users.
2661 bool HasMultipleConditionRegisters;
2662
2663 /// Tells the code generator that the target has BitExtract instructions.
2664 /// The code generator will aggressively sink "shift"s into the blocks of
2665 /// their users if the users will generate "and" instructions which can be
2666 /// combined with "shift" to BitExtract instructions.
2667 bool HasExtractBitsInsn;
2668
2669 /// Tells the code generator to bypass slow divide or remainder
2670 /// instructions. For example, BypassSlowDivWidths[32,8] tells the code
2671 /// generator to bypass 32-bit integer div/rem with an 8-bit unsigned integer
2672 /// div/rem when the operands are positive and less than 256.
2673 DenseMap <unsigned int, unsigned int> BypassSlowDivWidths;
2674
2675 /// Tells the code generator that it shouldn't generate extra flow control
2676 /// instructions and should attempt to combine flow control instructions via
2677 /// predication.
2678 bool JumpIsExpensive;
2679
2680 /// This target prefers to use _setjmp to implement llvm.setjmp.
2681 ///
2682 /// Defaults to false.
2683 bool UseUnderscoreSetJmp;
2684
2685 /// This target prefers to use _longjmp to implement llvm.longjmp.
2686 ///
2687 /// Defaults to false.
2688 bool UseUnderscoreLongJmp;
2689
2690 /// Information about the contents of the high-bits in boolean values held in
2691 /// a type wider than i1. See getBooleanContents.
2692 BooleanContent BooleanContents;
2693
2694 /// Information about the contents of the high-bits in boolean values held in
2695 /// a type wider than i1. See getBooleanContents.
2696 BooleanContent BooleanFloatContents;
2697
2698 /// Information about the contents of the high-bits in boolean vector values
2699 /// when the element type is wider than i1. See getBooleanContents.
2700 BooleanContent BooleanVectorContents;
2701
2702 /// The target scheduling preference: shortest possible total cycles or lowest
2703 /// register usage.
2704 Sched::Preference SchedPreferenceInfo;
2705
2706 /// The minimum alignment that any argument on the stack needs to have.
2707 Align MinStackArgumentAlignment;
2708
2709 /// The minimum function alignment (used when optimizing for size, and to
2710 /// prevent explicitly provided alignment from leading to incorrect code).
2711 Align MinFunctionAlignment;
2712
2713 /// The preferred function alignment (used when alignment unspecified and
2714 /// optimizing for speed).
2715 Align PrefFunctionAlignment;
2716
2717 /// The preferred loop alignment (in log2 bot in bytes).
2718 Align PrefLoopAlignment;
2719
2720 /// Size in bits of the maximum atomics size the backend supports.
2721 /// Accesses larger than this will be expanded by AtomicExpandPass.
2722 unsigned MaxAtomicSizeInBitsSupported;
2723
2724 /// Size in bits of the minimum cmpxchg or ll/sc operation the
2725 /// backend supports.
2726 unsigned MinCmpXchgSizeInBits;
2727
2728 /// This indicates if the target supports unaligned atomic operations.
2729 bool SupportsUnalignedAtomics;
2730
2731 /// If set to a physical register, this specifies the register that
2732 /// llvm.savestack/llvm.restorestack should save and restore.
2733 unsigned StackPointerRegisterToSaveRestore;
2734
2735 /// This indicates the default register class to use for each ValueType the
2736 /// target supports natively.
2737 const TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
2738 unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];
2739 MVT RegisterTypeForVT[MVT::LAST_VALUETYPE];
2740
2741 /// This indicates the "representative" register class to use for each
2742 /// ValueType the target supports natively. This information is used by the
2743 /// scheduler to track register pressure. By default, the representative
2744 /// register class is the largest legal super-reg register class of the
2745 /// register class of the specified type. e.g. On x86, i8, i16, and i32's
2746 /// representative class would be GR32.
2747 const TargetRegisterClass *RepRegClassForVT[MVT::LAST_VALUETYPE];
2748
2749 /// This indicates the "cost" of the "representative" register class for each
2750 /// ValueType. The cost is used by the scheduler to approximate register
2751 /// pressure.
2752 uint8_t RepRegClassCostForVT[MVT::LAST_VALUETYPE];
2753
2754 /// For any value types we are promoting or expanding, this contains the value
2755 /// type that we are changing to. For Expanded types, this contains one step
2756 /// of the expand (e.g. i64 -> i32), even if there are multiple steps required
2757 /// (e.g. i64 -> i16). For types natively supported by the system, this holds
2758 /// the same type (e.g. i32 -> i32).
2759 MVT TransformToType[MVT::LAST_VALUETYPE];
2760
2761 /// For each operation and each value type, keep a LegalizeAction that
2762 /// indicates how instruction selection should deal with the operation. Most
2763 /// operations are Legal (aka, supported natively by the target), but
2764 /// operations that are not should be described. Note that operations on
2765 /// non-legal value types are not described here.
2766 LegalizeAction OpActions[MVT::LAST_VALUETYPE][ISD::BUILTIN_OP_END];
2767
2768 /// For each load extension type and each value type, keep a LegalizeAction
2769 /// that indicates how instruction selection should deal with a load of a
2770 /// specific value type and extension type. Uses 4-bits to store the action
2771 /// for each of the 4 load ext types.
2772 uint16_t LoadExtActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE];
2773
2774 /// For each value type pair keep a LegalizeAction that indicates whether a
2775 /// truncating store of a specific value type and truncating type is legal.
2776 LegalizeAction TruncStoreActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE];
2777
2778 /// For each indexed mode and each value type, keep a pair of LegalizeAction
2779 /// that indicates how instruction selection should deal with the load /
2780 /// store.
2781 ///
2782 /// The first dimension is the value_type for the reference. The second
2783 /// dimension represents the various modes for load store.
2784 uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][ISD::LAST_INDEXED_MODE];
2785
2786 /// For each condition code (ISD::CondCode) keep a LegalizeAction that
2787 /// indicates how instruction selection should deal with the condition code.
2788 ///
2789 /// Because each CC action takes up 4 bits, we need to have the array size be
2790 /// large enough to fit all of the value types. This can be done by rounding
2791 /// up the MVT::LAST_VALUETYPE value to the next multiple of 8.
2792 uint32_t CondCodeActions[ISD::SETCC_INVALID][(MVT::LAST_VALUETYPE + 7) / 8];
2793
2794 ValueTypeActionImpl ValueTypeActions;
2795
2796private:
2797 LegalizeKind getTypeConversion(LLVMContext &Context, EVT VT) const;
2798
2799 /// Targets can specify ISD nodes that they would like PerformDAGCombine
2800 /// callbacks for by calling setTargetDAGCombine(), which sets a bit in this
2801 /// array.
2802 unsigned char
2803 TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT8-1)/CHAR_BIT8];
2804
2805 /// For operations that must be promoted to a specific type, this holds the
2806 /// destination type. This map should be sparse, so don't hold it as an
2807 /// array.
2808 ///
2809 /// Targets add entries to this map with AddPromotedToType(..), clients access
2810 /// this with getTypeToPromoteTo(..).
2811 std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType>
2812 PromoteToType;
2813
2814 /// Stores the name each libcall.
2815 const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL + 1];
2816
2817 /// The ISD::CondCode that should be used to test the result of each of the
2818 /// comparison libcall against zero.
2819 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL];
2820
2821 /// Stores the CallingConv that should be used for each libcall.
2822 CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL];
2823
2824 /// Set default libcall names and calling conventions.
2825 void InitLibcalls(const Triple &TT);
2826
2827protected:
2828 /// Return true if the extension represented by \p I is free.
2829 /// \pre \p I is a sign, zero, or fp extension and
2830 /// is[Z|FP]ExtFree of the related types is not true.
2831 virtual bool isExtFreeImpl(const Instruction *I) const { return false; }
2832
2833 /// Depth that GatherAllAliases should should continue looking for chain
2834 /// dependencies when trying to find a more preferable chain. As an
2835 /// approximation, this should be more than the number of consecutive stores
2836 /// expected to be merged.
2837 unsigned GatherAllAliasesMaxDepth;
2838
2839 /// \brief Specify maximum number of store instructions per memset call.
2840 ///
2841 /// When lowering \@llvm.memset this field specifies the maximum number of
2842 /// store operations that may be substituted for the call to memset. Targets
2843 /// must set this value based on the cost threshold for that target. Targets
2844 /// should assume that the memset will be done using as many of the largest
2845 /// store operations first, followed by smaller ones, if necessary, per
2846 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine
2847 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte
2848 /// store. This only applies to setting a constant array of a constant size.
2849 unsigned MaxStoresPerMemset;
2850 /// Likewise for functions with the OptSize attribute.
2851 unsigned MaxStoresPerMemsetOptSize;
2852
2853 /// \brief Specify maximum number of store instructions per memcpy call.
2854 ///
2855 /// When lowering \@llvm.memcpy this field specifies the maximum number of
2856 /// store operations that may be substituted for a call to memcpy. Targets
2857 /// must set this value based on the cost threshold for that target. Targets
2858 /// should assume that the memcpy will be done using as many of the largest
2859 /// store operations first, followed by smaller ones, if necessary, per
2860 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine
2861 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store
2862 /// and one 1-byte store. This only applies to copying a constant array of
2863 /// constant size.
2864 unsigned MaxStoresPerMemcpy;
2865 /// Likewise for functions with the OptSize attribute.
2866 unsigned MaxStoresPerMemcpyOptSize;
2867 /// \brief Specify max number of store instructions to glue in inlined memcpy.
2868 ///
2869 /// When memcpy is inlined based on MaxStoresPerMemcpy, specify maximum number
2870 /// of store instructions to keep together. This helps in pairing and
2871 // vectorization later on.
2872 unsigned MaxGluedStoresPerMemcpy = 0;
2873
2874 /// \brief Specify maximum number of load instructions per memcmp call.
2875 ///
2876 /// When lowering \@llvm.memcmp this field specifies the maximum number of
2877 /// pairs of load operations that may be substituted for a call to memcmp.
2878 /// Targets must set this value based on the cost threshold for that target.
2879 /// Targets should assume that the memcmp will be done using as many of the
2880 /// largest load operations first, followed by smaller ones, if necessary, per
2881 /// alignment restrictions. For example, loading 7 bytes on a 32-bit machine
2882 /// with 32-bit alignment would result in one 4-byte load, a one 2-byte load
2883 /// and one 1-byte load. This only applies to copying a constant array of
2884 /// constant size.
2885 unsigned MaxLoadsPerMemcmp;
2886 /// Likewise for functions with the OptSize attribute.
2887 unsigned MaxLoadsPerMemcmpOptSize;
2888
2889 /// \brief Specify maximum number of store instructions per memmove call.
2890 ///
2891 /// When lowering \@llvm.memmove this field specifies the maximum number of
2892 /// store instructions that may be substituted for a call to memmove. Targets
2893 /// must set this value based on the cost threshold for that target. Targets
2894 /// should assume that the memmove will be done using as many of the largest
2895 /// store operations first, followed by smaller ones, if necessary, per
2896 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine
2897 /// with 8-bit alignment would result in nine 1-byte stores. This only
2898 /// applies to copying a constant array of constant size.
2899 unsigned MaxStoresPerMemmove;
2900 /// Likewise for functions with the OptSize attribute.
2901 unsigned MaxStoresPerMemmoveOptSize;
2902
2903 /// Tells the code generator that select is more expensive than a branch if
2904 /// the branch is usually predicted right.
2905 bool PredictableSelectIsExpensive;
2906
2907 /// \see enableExtLdPromotion.
2908 bool EnableExtLdPromotion;
2909
2910 /// Return true if the value types that can be represented by the specified
2911 /// register class are all legal.
2912 bool isLegalRC(const TargetRegisterInfo &TRI,
2913 const TargetRegisterClass &RC) const;
2914
2915 /// Replace/modify any TargetFrameIndex operands with a targte-dependent
2916 /// sequence of memory operands that is recognized by PrologEpilogInserter.
2917 MachineBasicBlock *emitPatchPoint(MachineInstr &MI,
2918 MachineBasicBlock *MBB) const;
2919
2920 /// Replace/modify the XRay custom event operands with target-dependent
2921 /// details.
2922 MachineBasicBlock *emitXRayCustomEvent(MachineInstr &MI,
2923 MachineBasicBlock *MBB) const;
2924
2925 /// Replace/modify the XRay typed event operands with target-dependent
2926 /// details.
2927 MachineBasicBlock *emitXRayTypedEvent(MachineInstr &MI,
2928 MachineBasicBlock *MBB) const;
2929};
2930
2931/// This class defines information used to lower LLVM code to legal SelectionDAG
2932/// operators that the target instruction selector can accept natively.
2933///
2934/// This class also defines callbacks that targets must implement to lower
2935/// target-specific constructs to SelectionDAG operators.
2936class TargetLowering : public TargetLoweringBase {
2937public:
2938 struct DAGCombinerInfo;
2939 struct MakeLibCallOptions;
2940
2941 TargetLowering(const TargetLowering &) = delete;
2942 TargetLowering &operator=(const TargetLowering &) = delete;
2943
2944 /// NOTE: The TargetMachine owns TLOF.
2945 explicit TargetLowering(const TargetMachine &TM);
2946
2947 bool isPositionIndependent() const;
2948
2949 virtual bool isSDNodeSourceOfDivergence(const SDNode *N,
2950 FunctionLoweringInfo *FLI,
2951 LegacyDivergenceAnalysis *DA) const {
2952 return false;
2953 }
2954
2955 virtual bool isSDNodeAlwaysUniform(const SDNode * N) const {
2956 return false;
2957 }
2958
2959 /// Returns true by value, base pointer and offset pointer and addressing mode
2960 /// by reference if the node's address can be legally represented as
2961 /// pre-indexed load / store address.
2962 virtual bool getPreIndexedAddressParts(SDNode * /*N*/, SDValue &/*Base*/,
2963 SDValue &/*Offset*/,
2964 ISD::MemIndexedMode &/*AM*/,
2965 SelectionDAG &/*DAG*/) const {