Bug Summary

File:lib/CodeGen/RegisterClassInfo.cpp
Warning:line 189, column 24
Called C++ object pointer is null

Annotated Source Code

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clang -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name RegisterClassInfo.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-eagerly-assume -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -mrelocation-model pic -pic-level 2 -mthread-model posix -fmath-errno -masm-verbose -mconstructor-aliases -munwind-tables -fuse-init-array -target-cpu x86-64 -dwarf-column-info -debugger-tuning=gdb -momit-leaf-frame-pointer -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-7/lib/clang/7.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-7~svn337490/build-llvm/lib/CodeGen -I /build/llvm-toolchain-snapshot-7~svn337490/lib/CodeGen -I /build/llvm-toolchain-snapshot-7~svn337490/build-llvm/include -I /build/llvm-toolchain-snapshot-7~svn337490/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/8/../../../../include/c++/8 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/8/../../../../include/x86_64-linux-gnu/c++/8 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/8/../../../../include/x86_64-linux-gnu/c++/8 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/8/../../../../include/c++/8/backward -internal-isystem /usr/include/clang/7.0.0/include/ -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-7/lib/clang/7.0.0/include -internal-externc-isystem /usr/lib/gcc/x86_64-linux-gnu/8/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++11 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-7~svn337490/build-llvm/lib/CodeGen -ferror-limit 19 -fmessage-length 0 -fvisibility-inlines-hidden -fobjc-runtime=gcc -fdiagnostics-show-option -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -o /tmp/scan-build-2018-07-20-043646-20380-1 -x c++ /build/llvm-toolchain-snapshot-7~svn337490/lib/CodeGen/RegisterClassInfo.cpp -faddrsig
1//===- RegisterClassInfo.cpp - Dynamic Register Class Info ----------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the RegisterClassInfo class which provides dynamic
11// information about target register classes. Callee-saved vs. caller-saved and
12// reserved registers depend on calling conventions and other dynamic
13// information, so some things cannot be determined statically.
14//
15//===----------------------------------------------------------------------===//
16
17#include "llvm/CodeGen/RegisterClassInfo.h"
18#include "llvm/ADT/ArrayRef.h"
19#include "llvm/ADT/BitVector.h"
20#include "llvm/ADT/SmallVector.h"
21#include "llvm/CodeGen/MachineFunction.h"
22#include "llvm/CodeGen/MachineRegisterInfo.h"
23#include "llvm/CodeGen/TargetFrameLowering.h"
24#include "llvm/CodeGen/TargetRegisterInfo.h"
25#include "llvm/CodeGen/TargetSubtargetInfo.h"
26#include "llvm/MC/MCRegisterInfo.h"
27#include "llvm/Support/CommandLine.h"
28#include "llvm/Support/Debug.h"
29#include "llvm/Support/raw_ostream.h"
30#include <algorithm>
31#include <cassert>
32#include <cstdint>
33
34using namespace llvm;
35
36#define DEBUG_TYPE"regalloc" "regalloc"
37
38static cl::opt<unsigned>
39StressRA("stress-regalloc", cl::Hidden, cl::init(0), cl::value_desc("N"),
40 cl::desc("Limit all regclasses to N registers"));
41
42RegisterClassInfo::RegisterClassInfo() = default;
43
44void RegisterClassInfo::runOnMachineFunction(const MachineFunction &mf) {
45 bool Update = false;
46 MF = &mf;
47
48 // Allocate new array the first time we see a new target.
49 if (MF->getSubtarget().getRegisterInfo() != TRI) {
50 TRI = MF->getSubtarget().getRegisterInfo();
51 RegClass.reset(new RCInfo[TRI->getNumRegClasses()]);
52 Update = true;
53 }
54
55 // Does this MF have different CSRs?
56 assert(TRI && "no register info set")(static_cast <bool> (TRI && "no register info set"
) ? void (0) : __assert_fail ("TRI && \"no register info set\""
, "/build/llvm-toolchain-snapshot-7~svn337490/lib/CodeGen/RegisterClassInfo.cpp"
, 56, __extension__ __PRETTY_FUNCTION__))
;
57
58 // Get the callee saved registers.
59 const MCPhysReg *CSR = MF->getRegInfo().getCalleeSavedRegs();
60 if (Update || CSR != CalleeSavedRegs) {
61 // Build a CSRAlias map. Every CSR alias saves the last
62 // overlapping CSR.
63 CalleeSavedAliases.resize(TRI->getNumRegs(), 0);
64 for (const MCPhysReg *I = CSR; *I; ++I)
65 for (MCRegAliasIterator AI(*I, TRI, true); AI.isValid(); ++AI)
66 CalleeSavedAliases[*AI] = *I;
67
68 Update = true;
69 }
70 CalleeSavedRegs = CSR;
71
72 // Different reserved registers?
73 const BitVector &RR = MF->getRegInfo().getReservedRegs();
74 if (Reserved.size() != RR.size() || RR != Reserved) {
75 Update = true;
76 Reserved = RR;
77 }
78
79 // Invalidate cached information from previous function.
80 if (Update) {
81 unsigned NumPSets = TRI->getNumRegPressureSets();
82 PSetLimits.reset(new unsigned[NumPSets]);
83 std::fill(&PSetLimits[0], &PSetLimits[NumPSets], 0);
84 ++Tag;
85 }
86}
87
88/// compute - Compute the preferred allocation order for RC with reserved
89/// registers filtered out. Volatile registers come first followed by CSR
90/// aliases ordered according to the CSR order specified by the target.
91void RegisterClassInfo::compute(const TargetRegisterClass *RC) const {
92 assert(RC && "no register class given")(static_cast <bool> (RC && "no register class given"
) ? void (0) : __assert_fail ("RC && \"no register class given\""
, "/build/llvm-toolchain-snapshot-7~svn337490/lib/CodeGen/RegisterClassInfo.cpp"
, 92, __extension__ __PRETTY_FUNCTION__))
;
93 RCInfo &RCI = RegClass[RC->getID()];
94
95 // Raw register count, including all reserved regs.
96 unsigned NumRegs = RC->getNumRegs();
97
98 if (!RCI.Order)
99 RCI.Order.reset(new MCPhysReg[NumRegs]);
100
101 unsigned N = 0;
102 SmallVector<MCPhysReg, 16> CSRAlias;
103 unsigned MinCost = 0xff;
104 unsigned LastCost = ~0u;
105 unsigned LastCostChange = 0;
106
107 // FIXME: Once targets reserve registers instead of removing them from the
108 // allocation order, we can simply use begin/end here.
109 ArrayRef<MCPhysReg> RawOrder = RC->getRawAllocationOrder(*MF);
110 for (unsigned i = 0; i != RawOrder.size(); ++i) {
111 unsigned PhysReg = RawOrder[i];
112 // Remove reserved registers from the allocation order.
113 if (Reserved.test(PhysReg))
114 continue;
115 unsigned Cost = TRI->getCostPerUse(PhysReg);
116 MinCost = std::min(MinCost, Cost);
117
118 if (CalleeSavedAliases[PhysReg])
119 // PhysReg aliases a CSR, save it for later.
120 CSRAlias.push_back(PhysReg);
121 else {
122 if (Cost != LastCost)
123 LastCostChange = N;
124 RCI.Order[N++] = PhysReg;
125 LastCost = Cost;
126 }
127 }
128 RCI.NumRegs = N + CSRAlias.size();
129 assert(RCI.NumRegs <= NumRegs && "Allocation order larger than regclass")(static_cast <bool> (RCI.NumRegs <= NumRegs &&
"Allocation order larger than regclass") ? void (0) : __assert_fail
("RCI.NumRegs <= NumRegs && \"Allocation order larger than regclass\""
, "/build/llvm-toolchain-snapshot-7~svn337490/lib/CodeGen/RegisterClassInfo.cpp"
, 129, __extension__ __PRETTY_FUNCTION__))
;
130
131 // CSR aliases go after the volatile registers, preserve the target's order.
132 for (unsigned i = 0, e = CSRAlias.size(); i != e; ++i) {
133 unsigned PhysReg = CSRAlias[i];
134 unsigned Cost = TRI->getCostPerUse(PhysReg);
135 if (Cost != LastCost)
136 LastCostChange = N;
137 RCI.Order[N++] = PhysReg;
138 LastCost = Cost;
139 }
140
141 // Register allocator stress test. Clip register class to N registers.
142 if (StressRA && RCI.NumRegs > StressRA)
143 RCI.NumRegs = StressRA;
144
145 // Check if RC is a proper sub-class.
146 if (const TargetRegisterClass *Super =
147 TRI->getLargestLegalSuperClass(RC, *MF))
148 if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs)
149 RCI.ProperSubClass = true;
150
151 RCI.MinCost = uint8_t(MinCost);
152 RCI.LastCostChange = LastCostChange;
153
154 LLVM_DEBUG({do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "AllocationOrder(" <<
TRI->getRegClassName(RC) << ") = ["; for (unsigned I
= 0; I != RCI.NumRegs; ++I) dbgs() << ' ' << printReg
(RCI.Order[I], TRI); dbgs() << (RCI.ProperSubClass ? " ] (sub-class)\n"
: " ]\n"); }; } } while (false)
155 dbgs() << "AllocationOrder(" << TRI->getRegClassName(RC) << ") = [";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "AllocationOrder(" <<
TRI->getRegClassName(RC) << ") = ["; for (unsigned I
= 0; I != RCI.NumRegs; ++I) dbgs() << ' ' << printReg
(RCI.Order[I], TRI); dbgs() << (RCI.ProperSubClass ? " ] (sub-class)\n"
: " ]\n"); }; } } while (false)
156 for (unsigned I = 0; I != RCI.NumRegs; ++I)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "AllocationOrder(" <<
TRI->getRegClassName(RC) << ") = ["; for (unsigned I
= 0; I != RCI.NumRegs; ++I) dbgs() << ' ' << printReg
(RCI.Order[I], TRI); dbgs() << (RCI.ProperSubClass ? " ] (sub-class)\n"
: " ]\n"); }; } } while (false)
157 dbgs() << ' ' << printReg(RCI.Order[I], TRI);do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "AllocationOrder(" <<
TRI->getRegClassName(RC) << ") = ["; for (unsigned I
= 0; I != RCI.NumRegs; ++I) dbgs() << ' ' << printReg
(RCI.Order[I], TRI); dbgs() << (RCI.ProperSubClass ? " ] (sub-class)\n"
: " ]\n"); }; } } while (false)
158 dbgs() << (RCI.ProperSubClass ? " ] (sub-class)\n" : " ]\n");do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "AllocationOrder(" <<
TRI->getRegClassName(RC) << ") = ["; for (unsigned I
= 0; I != RCI.NumRegs; ++I) dbgs() << ' ' << printReg
(RCI.Order[I], TRI); dbgs() << (RCI.ProperSubClass ? " ] (sub-class)\n"
: " ]\n"); }; } } while (false)
159 })do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "AllocationOrder(" <<
TRI->getRegClassName(RC) << ") = ["; for (unsigned I
= 0; I != RCI.NumRegs; ++I) dbgs() << ' ' << printReg
(RCI.Order[I], TRI); dbgs() << (RCI.ProperSubClass ? " ] (sub-class)\n"
: " ]\n"); }; } } while (false)
;
160
161 // RCI is now up-to-date.
162 RCI.Tag = Tag;
163}
164
165/// This is not accurate because two overlapping register sets may have some
166/// nonoverlapping reserved registers. However, computing the allocation order
167/// for all register classes would be too expensive.
168unsigned RegisterClassInfo::computePSetLimit(unsigned Idx) const {
169 const TargetRegisterClass *RC = nullptr;
1
'RC' initialized to a null pointer value
170 unsigned NumRCUnits = 0;
171 for (const TargetRegisterClass *C : TRI->regclasses()) {
2
Assuming '__begin1' is not equal to '__end1'
172 const int *PSetID = TRI->getRegClassPressureSets(C);
173 for (; *PSetID != -1; ++PSetID) {
3
Assuming the condition is false
4
Loop condition is false. Execution continues on line 177
7
Assuming the condition is false
8
Loop condition is false. Execution continues on line 177
174 if ((unsigned)*PSetID == Idx)
175 break;
176 }
177 if (*PSetID == -1)
5
Taking true branch
9
Taking true branch
178 continue;
6
Execution continues on line 171
10
Execution continues on line 171
179
180 // Found a register class that counts against this pressure set.
181 // For efficiency, only compute the set order for the largest set.
182 unsigned NUnits = TRI->getRegClassWeight(C).WeightLimit;
183 if (!RC || NUnits > NumRCUnits) {
184 RC = C;
185 NumRCUnits = NUnits;
186 }
187 }
188 compute(RC);
189 unsigned NReserved = RC->getNumRegs() - getNumAllocatableRegs(RC);
11
Called C++ object pointer is null
190 return TRI->getRegPressureSetLimit(*MF, Idx) -
191 TRI->getRegClassWeight(RC).RegWeight * NReserved;
192}