Bug Summary

File:llvm/lib/Target/AMDGPU/SIAddIMGInit.cpp
Warning:line 86, column 27
Called C++ object pointer is null

Annotated Source Code

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clang -cc1 -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name SIAddIMGInit.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mframe-pointer=none -fmath-errno -fno-rounding-math -mconstructor-aliases -munwind-tables -target-cpu x86-64 -tune-cpu generic -fno-split-dwarf-inlining -debugger-tuning=gdb -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-12/lib/clang/12.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-12~++20200927111121+5811d723998/build-llvm/lib/Target/AMDGPU -I /build/llvm-toolchain-snapshot-12~++20200927111121+5811d723998/llvm/lib/Target/AMDGPU -I /build/llvm-toolchain-snapshot-12~++20200927111121+5811d723998/build-llvm/include -I /build/llvm-toolchain-snapshot-12~++20200927111121+5811d723998/llvm/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0/backward -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-12/lib/clang/12.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++14 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-12~++20200927111121+5811d723998/build-llvm/lib/Target/AMDGPU -fdebug-prefix-map=/build/llvm-toolchain-snapshot-12~++20200927111121+5811d723998=. -ferror-limit 19 -fvisibility hidden -fvisibility-inlines-hidden -stack-protector 2 -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -o /tmp/scan-build-2020-09-28-092409-31635-1 -x c++ /build/llvm-toolchain-snapshot-12~++20200927111121+5811d723998/llvm/lib/Target/AMDGPU/SIAddIMGInit.cpp

/build/llvm-toolchain-snapshot-12~++20200927111121+5811d723998/llvm/lib/Target/AMDGPU/SIAddIMGInit.cpp

1//===-- SIAddIMGInit.cpp - Add any required IMG inits ---------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file
10/// Any MIMG instructions that use tfe or lwe require an initialization of the
11/// result register that will be written in the case of a memory access failure
12/// The required code is also added to tie this init code to the result of the
13/// img instruction
14///
15//===----------------------------------------------------------------------===//
16//
17
18#include "AMDGPU.h"
19#include "AMDGPUSubtarget.h"
20#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
21#include "SIInstrInfo.h"
22#include "llvm/CodeGen/MachineFunctionPass.h"
23#include "llvm/CodeGen/MachineInstrBuilder.h"
24#include "llvm/CodeGen/MachineRegisterInfo.h"
25#include "llvm/IR/Function.h"
26#include "llvm/Support/Debug.h"
27#include "llvm/Target/TargetMachine.h"
28
29#define DEBUG_TYPE"si-img-init" "si-img-init"
30
31using namespace llvm;
32
33namespace {
34
35class SIAddIMGInit : public MachineFunctionPass {
36public:
37 static char ID;
38
39public:
40 SIAddIMGInit() : MachineFunctionPass(ID) {
41 initializeSIAddIMGInitPass(*PassRegistry::getPassRegistry());
42 }
43
44 bool runOnMachineFunction(MachineFunction &MF) override;
45
46 void getAnalysisUsage(AnalysisUsage &AU) const override {
47 AU.setPreservesCFG();
48 MachineFunctionPass::getAnalysisUsage(AU);
49 }
50};
51
52} // End anonymous namespace.
53
54INITIALIZE_PASS(SIAddIMGInit, DEBUG_TYPE, "SI Add IMG Init", false, false)static void *initializeSIAddIMGInitPassOnce(PassRegistry &
Registry) { PassInfo *PI = new PassInfo( "SI Add IMG Init", "si-img-init"
, &SIAddIMGInit::ID, PassInfo::NormalCtor_t(callDefaultCtor
<SIAddIMGInit>), false, false); Registry.registerPass(*
PI, true); return PI; } static llvm::once_flag InitializeSIAddIMGInitPassFlag
; void llvm::initializeSIAddIMGInitPass(PassRegistry &Registry
) { llvm::call_once(InitializeSIAddIMGInitPassFlag, initializeSIAddIMGInitPassOnce
, std::ref(Registry)); }
55
56char SIAddIMGInit::ID = 0;
57
58char &llvm::SIAddIMGInitID = SIAddIMGInit::ID;
59
60FunctionPass *llvm::createSIAddIMGInitPass() { return new SIAddIMGInit(); }
61
62bool SIAddIMGInit::runOnMachineFunction(MachineFunction &MF) {
63 MachineRegisterInfo &MRI = MF.getRegInfo();
64 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
65 const SIInstrInfo *TII = ST.getInstrInfo();
66 const SIRegisterInfo *RI = ST.getRegisterInfo();
67 bool Changed = false;
68
69 for (MachineFunction::iterator BI = MF.begin(), BE = MF.end(); BI != BE;
1
Calling 'operator!='
4
Returning from 'operator!='
5
Loop condition is true. Entering loop body
70 ++BI) {
71 MachineBasicBlock &MBB = *BI;
72 MachineBasicBlock::iterator I, Next;
73 for (I = MBB.begin(); I != MBB.end(); I = Next) {
6
Calling 'operator!='
15
Returning from 'operator!='
16
Loop condition is true. Entering loop body
74 Next = std::next(I);
75 MachineInstr &MI = *I;
76
77 auto Opcode = MI.getOpcode();
78 if (TII->isMIMG(Opcode) && !MI.mayStore()) {
17
Assuming the condition is true
18
Calling 'MachineInstr::mayStore'
31
Returning from 'MachineInstr::mayStore'
32
Assuming the condition is true
33
Taking true branch
79 MachineOperand *TFE = TII->getNamedOperand(MI, AMDGPU::OpName::tfe);
34
'TFE' initialized here
80 MachineOperand *LWE = TII->getNamedOperand(MI, AMDGPU::OpName::lwe);
81 MachineOperand *D16 = TII->getNamedOperand(MI, AMDGPU::OpName::d16);
82
83 if (!TFE && !LWE) // intersect_ray
35
Assuming 'TFE' is null
36
Assuming 'LWE' is non-null
37
Taking false branch
84 continue;
85
86 unsigned TFEVal = TFE->getImm();
38
Called C++ object pointer is null
87 unsigned LWEVal = LWE->getImm();
88 unsigned D16Val = D16 ? D16->getImm() : 0;
89
90 if (TFEVal || LWEVal) {
91 // At least one of TFE or LWE are non-zero
92 // We have to insert a suitable initialization of the result value and
93 // tie this to the dest of the image instruction.
94
95 const DebugLoc &DL = MI.getDebugLoc();
96
97 int DstIdx =
98 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vdata);
99
100 // Calculate which dword we have to initialize to 0.
101 MachineOperand *MO_Dmask =
102 TII->getNamedOperand(MI, AMDGPU::OpName::dmask);
103
104 // check that dmask operand is found.
105 assert(MO_Dmask && "Expected dmask operand in instruction")((MO_Dmask && "Expected dmask operand in instruction"
) ? static_cast<void> (0) : __assert_fail ("MO_Dmask && \"Expected dmask operand in instruction\""
, "/build/llvm-toolchain-snapshot-12~++20200927111121+5811d723998/llvm/lib/Target/AMDGPU/SIAddIMGInit.cpp"
, 105, __PRETTY_FUNCTION__))
;
106
107 unsigned dmask = MO_Dmask->getImm();
108 // Determine the number of active lanes taking into account the
109 // Gather4 special case
110 unsigned ActiveLanes =
111 TII->isGather4(Opcode) ? 4 : countPopulation(dmask);
112
113 bool Packed = !ST.hasUnpackedD16VMem();
114
115 unsigned InitIdx =
116 D16Val && Packed ? ((ActiveLanes + 1) >> 1) + 1 : ActiveLanes + 1;
117
118 // Abandon attempt if the dst size isn't large enough
119 // - this is in fact an error but this is picked up elsewhere and
120 // reported correctly.
121 uint32_t DstSize =
122 RI->getRegSizeInBits(*TII->getOpRegClass(MI, DstIdx)) / 32;
123 if (DstSize < InitIdx)
124 continue;
125
126 // Create a register for the intialization value.
127 Register PrevDst =
128 MRI.createVirtualRegister(TII->getOpRegClass(MI, DstIdx));
129 unsigned NewDst = 0; // Final initialized value will be in here
130
131 // If PRTStrictNull feature is enabled (the default) then initialize
132 // all the result registers to 0, otherwise just the error indication
133 // register (VGPRn+1)
134 unsigned SizeLeft = ST.usePRTStrictNull() ? InitIdx : 1;
135 unsigned CurrIdx = ST.usePRTStrictNull() ? 0 : (InitIdx - 1);
136
137 if (DstSize == 1) {
138 // In this case we can just initialize the result directly
139 BuildMI(MBB, MI, DL, TII->get(AMDGPU::V_MOV_B32_e32), PrevDst)
140 .addImm(0);
141 NewDst = PrevDst;
142 } else {
143 BuildMI(MBB, MI, DL, TII->get(AMDGPU::IMPLICIT_DEF), PrevDst);
144 for (; SizeLeft; SizeLeft--, CurrIdx++) {
145 NewDst =
146 MRI.createVirtualRegister(TII->getOpRegClass(MI, DstIdx));
147 // Initialize dword
148 Register SubReg =
149 MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
150 BuildMI(MBB, MI, DL, TII->get(AMDGPU::V_MOV_B32_e32), SubReg)
151 .addImm(0);
152 // Insert into the super-reg
153 BuildMI(MBB, I, DL, TII->get(TargetOpcode::INSERT_SUBREG), NewDst)
154 .addReg(PrevDst)
155 .addReg(SubReg)
156 .addImm(SIRegisterInfo::getSubRegFromChannel(CurrIdx));
157
158 PrevDst = NewDst;
159 }
160 }
161
162 // Add as an implicit operand
163 MachineInstrBuilder(MF, MI).addReg(NewDst, RegState::Implicit);
164
165 // Tie the just added implicit operand to the dst
166 MI.tieOperands(DstIdx, MI.getNumOperands() - 1);
167
168 Changed = true;
169 }
170 }
171 }
172 }
173
174 return Changed;
175}

/build/llvm-toolchain-snapshot-12~++20200927111121+5811d723998/llvm/include/llvm/ADT/ilist_iterator.h

1//===- llvm/ADT/ilist_iterator.h - Intrusive List Iterator ------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#ifndef LLVM_ADT_ILIST_ITERATOR_H
10#define LLVM_ADT_ILIST_ITERATOR_H
11
12#include "llvm/ADT/ilist_node.h"
13#include <cassert>
14#include <cstddef>
15#include <iterator>
16#include <type_traits>
17
18namespace llvm {
19
20namespace ilist_detail {
21
22/// Find const-correct node types.
23template <class OptionsT, bool IsConst> struct IteratorTraits;
24template <class OptionsT> struct IteratorTraits<OptionsT, false> {
25 using value_type = typename OptionsT::value_type;
26 using pointer = typename OptionsT::pointer;
27 using reference = typename OptionsT::reference;
28 using node_pointer = ilist_node_impl<OptionsT> *;
29 using node_reference = ilist_node_impl<OptionsT> &;
30};
31template <class OptionsT> struct IteratorTraits<OptionsT, true> {
32 using value_type = const typename OptionsT::value_type;
33 using pointer = typename OptionsT::const_pointer;
34 using reference = typename OptionsT::const_reference;
35 using node_pointer = const ilist_node_impl<OptionsT> *;
36 using node_reference = const ilist_node_impl<OptionsT> &;
37};
38
39template <bool IsReverse> struct IteratorHelper;
40template <> struct IteratorHelper<false> : ilist_detail::NodeAccess {
41 using Access = ilist_detail::NodeAccess;
42
43 template <class T> static void increment(T *&I) { I = Access::getNext(*I); }
44 template <class T> static void decrement(T *&I) { I = Access::getPrev(*I); }
45};
46template <> struct IteratorHelper<true> : ilist_detail::NodeAccess {
47 using Access = ilist_detail::NodeAccess;
48
49 template <class T> static void increment(T *&I) { I = Access::getPrev(*I); }
50 template <class T> static void decrement(T *&I) { I = Access::getNext(*I); }
51};
52
53} // end namespace ilist_detail
54
55/// Iterator for intrusive lists based on ilist_node.
56template <class OptionsT, bool IsReverse, bool IsConst>
57class ilist_iterator : ilist_detail::SpecificNodeAccess<OptionsT> {
58 friend ilist_iterator<OptionsT, IsReverse, !IsConst>;
59 friend ilist_iterator<OptionsT, !IsReverse, IsConst>;
60 friend ilist_iterator<OptionsT, !IsReverse, !IsConst>;
61
62 using Traits = ilist_detail::IteratorTraits<OptionsT, IsConst>;
63 using Access = ilist_detail::SpecificNodeAccess<OptionsT>;
64
65public:
66 using value_type = typename Traits::value_type;
67 using pointer = typename Traits::pointer;
68 using reference = typename Traits::reference;
69 using difference_type = ptrdiff_t;
70 using iterator_category = std::bidirectional_iterator_tag;
71 using const_pointer = typename OptionsT::const_pointer;
72 using const_reference = typename OptionsT::const_reference;
73
74private:
75 using node_pointer = typename Traits::node_pointer;
76 using node_reference = typename Traits::node_reference;
77
78 node_pointer NodePtr = nullptr;
79
80public:
81 /// Create from an ilist_node.
82 explicit ilist_iterator(node_reference N) : NodePtr(&N) {}
83
84 explicit ilist_iterator(pointer NP) : NodePtr(Access::getNodePtr(NP)) {}
85 explicit ilist_iterator(reference NR) : NodePtr(Access::getNodePtr(&NR)) {}
86 ilist_iterator() = default;
87
88 // This is templated so that we can allow constructing a const iterator from
89 // a nonconst iterator...
90 template <bool RHSIsConst>
91 ilist_iterator(const ilist_iterator<OptionsT, IsReverse, RHSIsConst> &RHS,
92 std::enable_if_t<IsConst || !RHSIsConst, void *> = nullptr)
93 : NodePtr(RHS.NodePtr) {}
94
95 // This is templated so that we can allow assigning to a const iterator from
96 // a nonconst iterator...
97 template <bool RHSIsConst>
98 std::enable_if_t<IsConst || !RHSIsConst, ilist_iterator &>
99 operator=(const ilist_iterator<OptionsT, IsReverse, RHSIsConst> &RHS) {
100 NodePtr = RHS.NodePtr;
101 return *this;
102 }
103
104 /// Explicit conversion between forward/reverse iterators.
105 ///
106 /// Translate between forward and reverse iterators without changing range
107 /// boundaries. The resulting iterator will dereference (and have a handle)
108 /// to the previous node, which is somewhat unexpected; but converting the
109 /// two endpoints in a range will give the same range in reverse.
110 ///
111 /// This matches std::reverse_iterator conversions.
112 explicit ilist_iterator(
113 const ilist_iterator<OptionsT, !IsReverse, IsConst> &RHS)
114 : ilist_iterator(++RHS.getReverse()) {}
115
116 /// Get a reverse iterator to the same node.
117 ///
118 /// Gives a reverse iterator that will dereference (and have a handle) to the
119 /// same node. Converting the endpoint iterators in a range will give a
120 /// different range; for range operations, use the explicit conversions.
121 ilist_iterator<OptionsT, !IsReverse, IsConst> getReverse() const {
122 if (NodePtr)
123 return ilist_iterator<OptionsT, !IsReverse, IsConst>(*NodePtr);
124 return ilist_iterator<OptionsT, !IsReverse, IsConst>();
125 }
126
127 /// Const-cast.
128 ilist_iterator<OptionsT, IsReverse, false> getNonConst() const {
129 if (NodePtr)
130 return ilist_iterator<OptionsT, IsReverse, false>(
131 const_cast<typename ilist_iterator<OptionsT, IsReverse,
132 false>::node_reference>(*NodePtr));
133 return ilist_iterator<OptionsT, IsReverse, false>();
134 }
135
136 // Accessors...
137 reference operator*() const {
138 assert(!NodePtr->isKnownSentinel())((!NodePtr->isKnownSentinel()) ? static_cast<void> (
0) : __assert_fail ("!NodePtr->isKnownSentinel()", "/build/llvm-toolchain-snapshot-12~++20200927111121+5811d723998/llvm/include/llvm/ADT/ilist_iterator.h"
, 138, __PRETTY_FUNCTION__))
;
139 return *Access::getValuePtr(NodePtr);
140 }
141 pointer operator->() const { return &operator*(); }
142
143 // Comparison operators
144 friend bool operator==(const ilist_iterator &LHS, const ilist_iterator &RHS) {
145 return LHS.NodePtr == RHS.NodePtr;
9
Assuming 'LHS.NodePtr' is not equal to 'RHS.NodePtr'
10
Returning zero, which participates in a condition later
146 }
147 friend bool operator!=(const ilist_iterator &LHS, const ilist_iterator &RHS) {
148 return LHS.NodePtr != RHS.NodePtr;
2
Assuming 'LHS.NodePtr' is not equal to 'RHS.NodePtr'
3
Returning the value 1, which participates in a condition later
149 }
150
151 // Increment and decrement operators...
152 ilist_iterator &operator--() {
153 NodePtr = IsReverse ? NodePtr->getNext() : NodePtr->getPrev();
154 return *this;
155 }
156 ilist_iterator &operator++() {
157 NodePtr = IsReverse ? NodePtr->getPrev() : NodePtr->getNext();
158 return *this;
159 }
160 ilist_iterator operator--(int) {
161 ilist_iterator tmp = *this;
162 --*this;
163 return tmp;
164 }
165 ilist_iterator operator++(int) {
166 ilist_iterator tmp = *this;
167 ++*this;
168 return tmp;
169 }
170
171 /// Get the underlying ilist_node.
172 node_pointer getNodePtr() const { return static_cast<node_pointer>(NodePtr); }
173
174 /// Check for end. Only valid if ilist_sentinel_tracking<true>.
175 bool isEnd() const { return NodePtr ? NodePtr->isSentinel() : false; }
176};
177
178template <typename From> struct simplify_type;
179
180/// Allow ilist_iterators to convert into pointers to a node automatically when
181/// used by the dyn_cast, cast, isa mechanisms...
182///
183/// FIXME: remove this, since there is no implicit conversion to NodeTy.
184template <class OptionsT, bool IsConst>
185struct simplify_type<ilist_iterator<OptionsT, false, IsConst>> {
186 using iterator = ilist_iterator<OptionsT, false, IsConst>;
187 using SimpleType = typename iterator::pointer;
188
189 static SimpleType getSimplifiedValue(const iterator &Node) { return &*Node; }
190};
191template <class OptionsT, bool IsConst>
192struct simplify_type<const ilist_iterator<OptionsT, false, IsConst>>
193 : simplify_type<ilist_iterator<OptionsT, false, IsConst>> {};
194
195} // end namespace llvm
196
197#endif // LLVM_ADT_ILIST_ITERATOR_H

/build/llvm-toolchain-snapshot-12~++20200927111121+5811d723998/llvm/include/llvm/CodeGen/MachineInstrBundleIterator.h

1//===- llvm/CodeGen/MachineInstrBundleIterator.h ----------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// Defines an iterator class that bundles MachineInstr.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_CODEGEN_MACHINEINSTRBUNDLEITERATOR_H
14#define LLVM_CODEGEN_MACHINEINSTRBUNDLEITERATOR_H
15
16#include "llvm/ADT/ilist.h"
17#include "llvm/ADT/simple_ilist.h"
18#include <cassert>
19#include <iterator>
20#include <type_traits>
21
22namespace llvm {
23
24template <class T, bool IsReverse> struct MachineInstrBundleIteratorTraits;
25template <class T> struct MachineInstrBundleIteratorTraits<T, false> {
26 using list_type = simple_ilist<T, ilist_sentinel_tracking<true>>;
27 using instr_iterator = typename list_type::iterator;
28 using nonconst_instr_iterator = typename list_type::iterator;
29 using const_instr_iterator = typename list_type::const_iterator;
30};
31template <class T> struct MachineInstrBundleIteratorTraits<T, true> {
32 using list_type = simple_ilist<T, ilist_sentinel_tracking<true>>;
33 using instr_iterator = typename list_type::reverse_iterator;
34 using nonconst_instr_iterator = typename list_type::reverse_iterator;
35 using const_instr_iterator = typename list_type::const_reverse_iterator;
36};
37template <class T> struct MachineInstrBundleIteratorTraits<const T, false> {
38 using list_type = simple_ilist<T, ilist_sentinel_tracking<true>>;
39 using instr_iterator = typename list_type::const_iterator;
40 using nonconst_instr_iterator = typename list_type::iterator;
41 using const_instr_iterator = typename list_type::const_iterator;
42};
43template <class T> struct MachineInstrBundleIteratorTraits<const T, true> {
44 using list_type = simple_ilist<T, ilist_sentinel_tracking<true>>;
45 using instr_iterator = typename list_type::const_reverse_iterator;
46 using nonconst_instr_iterator = typename list_type::reverse_iterator;
47 using const_instr_iterator = typename list_type::const_reverse_iterator;
48};
49
50template <bool IsReverse> struct MachineInstrBundleIteratorHelper;
51template <> struct MachineInstrBundleIteratorHelper<false> {
52 /// Get the beginning of the current bundle.
53 template <class Iterator> static Iterator getBundleBegin(Iterator I) {
54 if (!I.isEnd())
55 while (I->isBundledWithPred())
56 --I;
57 return I;
58 }
59
60 /// Get the final node of the current bundle.
61 template <class Iterator> static Iterator getBundleFinal(Iterator I) {
62 if (!I.isEnd())
63 while (I->isBundledWithSucc())
64 ++I;
65 return I;
66 }
67
68 /// Increment forward ilist iterator.
69 template <class Iterator> static void increment(Iterator &I) {
70 I = std::next(getBundleFinal(I));
71 }
72
73 /// Decrement forward ilist iterator.
74 template <class Iterator> static void decrement(Iterator &I) {
75 I = getBundleBegin(std::prev(I));
76 }
77};
78
79template <> struct MachineInstrBundleIteratorHelper<true> {
80 /// Get the beginning of the current bundle.
81 template <class Iterator> static Iterator getBundleBegin(Iterator I) {
82 return MachineInstrBundleIteratorHelper<false>::getBundleBegin(
83 I.getReverse())
84 .getReverse();
85 }
86
87 /// Get the final node of the current bundle.
88 template <class Iterator> static Iterator getBundleFinal(Iterator I) {
89 return MachineInstrBundleIteratorHelper<false>::getBundleFinal(
90 I.getReverse())
91 .getReverse();
92 }
93
94 /// Increment reverse ilist iterator.
95 template <class Iterator> static void increment(Iterator &I) {
96 I = getBundleBegin(std::next(I));
97 }
98
99 /// Decrement reverse ilist iterator.
100 template <class Iterator> static void decrement(Iterator &I) {
101 I = std::prev(getBundleFinal(I));
102 }
103};
104
105/// MachineBasicBlock iterator that automatically skips over MIs that are
106/// inside bundles (i.e. walk top level MIs only).
107template <typename Ty, bool IsReverse = false>
108class MachineInstrBundleIterator : MachineInstrBundleIteratorHelper<IsReverse> {
109 using Traits = MachineInstrBundleIteratorTraits<Ty, IsReverse>;
110 using instr_iterator = typename Traits::instr_iterator;
111
112 instr_iterator MII;
113
114public:
115 using value_type = typename instr_iterator::value_type;
116 using difference_type = typename instr_iterator::difference_type;
117 using pointer = typename instr_iterator::pointer;
118 using reference = typename instr_iterator::reference;
119 using const_pointer = typename instr_iterator::const_pointer;
120 using const_reference = typename instr_iterator::const_reference;
121 using iterator_category = std::bidirectional_iterator_tag;
122
123private:
124 using nonconst_instr_iterator = typename Traits::nonconst_instr_iterator;
125 using const_instr_iterator = typename Traits::const_instr_iterator;
126 using nonconst_iterator =
127 MachineInstrBundleIterator<typename nonconst_instr_iterator::value_type,
128 IsReverse>;
129 using reverse_iterator = MachineInstrBundleIterator<Ty, !IsReverse>;
130
131public:
132 MachineInstrBundleIterator(instr_iterator MI) : MII(MI) {
133 assert((!MI.getNodePtr() || MI.isEnd() || !MI->isBundledWithPred()) &&(((!MI.getNodePtr() || MI.isEnd() || !MI->isBundledWithPred
()) && "It's not legal to initialize MachineInstrBundleIterator with a "
"bundled MI") ? static_cast<void> (0) : __assert_fail (
"(!MI.getNodePtr() || MI.isEnd() || !MI->isBundledWithPred()) && \"It's not legal to initialize MachineInstrBundleIterator with a \" \"bundled MI\""
, "/build/llvm-toolchain-snapshot-12~++20200927111121+5811d723998/llvm/include/llvm/CodeGen/MachineInstrBundleIterator.h"
, 135, __PRETTY_FUNCTION__))
134 "It's not legal to initialize MachineInstrBundleIterator with a "(((!MI.getNodePtr() || MI.isEnd() || !MI->isBundledWithPred
()) && "It's not legal to initialize MachineInstrBundleIterator with a "
"bundled MI") ? static_cast<void> (0) : __assert_fail (
"(!MI.getNodePtr() || MI.isEnd() || !MI->isBundledWithPred()) && \"It's not legal to initialize MachineInstrBundleIterator with a \" \"bundled MI\""
, "/build/llvm-toolchain-snapshot-12~++20200927111121+5811d723998/llvm/include/llvm/CodeGen/MachineInstrBundleIterator.h"
, 135, __PRETTY_FUNCTION__))
135 "bundled MI")(((!MI.getNodePtr() || MI.isEnd() || !MI->isBundledWithPred
()) && "It's not legal to initialize MachineInstrBundleIterator with a "
"bundled MI") ? static_cast<void> (0) : __assert_fail (
"(!MI.getNodePtr() || MI.isEnd() || !MI->isBundledWithPred()) && \"It's not legal to initialize MachineInstrBundleIterator with a \" \"bundled MI\""
, "/build/llvm-toolchain-snapshot-12~++20200927111121+5811d723998/llvm/include/llvm/CodeGen/MachineInstrBundleIterator.h"
, 135, __PRETTY_FUNCTION__))
;
136 }
137
138 MachineInstrBundleIterator(reference MI) : MII(MI) {
139 assert(!MI.isBundledWithPred() && "It's not legal to initialize "((!MI.isBundledWithPred() && "It's not legal to initialize "
"MachineInstrBundleIterator with a " "bundled MI") ? static_cast
<void> (0) : __assert_fail ("!MI.isBundledWithPred() && \"It's not legal to initialize \" \"MachineInstrBundleIterator with a \" \"bundled MI\""
, "/build/llvm-toolchain-snapshot-12~++20200927111121+5811d723998/llvm/include/llvm/CodeGen/MachineInstrBundleIterator.h"
, 141, __PRETTY_FUNCTION__))
140 "MachineInstrBundleIterator with a "((!MI.isBundledWithPred() && "It's not legal to initialize "
"MachineInstrBundleIterator with a " "bundled MI") ? static_cast
<void> (0) : __assert_fail ("!MI.isBundledWithPred() && \"It's not legal to initialize \" \"MachineInstrBundleIterator with a \" \"bundled MI\""
, "/build/llvm-toolchain-snapshot-12~++20200927111121+5811d723998/llvm/include/llvm/CodeGen/MachineInstrBundleIterator.h"
, 141, __PRETTY_FUNCTION__))
141 "bundled MI")((!MI.isBundledWithPred() && "It's not legal to initialize "
"MachineInstrBundleIterator with a " "bundled MI") ? static_cast
<void> (0) : __assert_fail ("!MI.isBundledWithPred() && \"It's not legal to initialize \" \"MachineInstrBundleIterator with a \" \"bundled MI\""
, "/build/llvm-toolchain-snapshot-12~++20200927111121+5811d723998/llvm/include/llvm/CodeGen/MachineInstrBundleIterator.h"
, 141, __PRETTY_FUNCTION__))
;
142 }
143
144 MachineInstrBundleIterator(pointer MI) : MII(MI) {
145 // FIXME: This conversion should be explicit.
146 assert((!MI || !MI->isBundledWithPred()) && "It's not legal to initialize "(((!MI || !MI->isBundledWithPred()) && "It's not legal to initialize "
"MachineInstrBundleIterator " "with a bundled MI") ? static_cast
<void> (0) : __assert_fail ("(!MI || !MI->isBundledWithPred()) && \"It's not legal to initialize \" \"MachineInstrBundleIterator \" \"with a bundled MI\""
, "/build/llvm-toolchain-snapshot-12~++20200927111121+5811d723998/llvm/include/llvm/CodeGen/MachineInstrBundleIterator.h"
, 148, __PRETTY_FUNCTION__))
147 "MachineInstrBundleIterator "(((!MI || !MI->isBundledWithPred()) && "It's not legal to initialize "
"MachineInstrBundleIterator " "with a bundled MI") ? static_cast
<void> (0) : __assert_fail ("(!MI || !MI->isBundledWithPred()) && \"It's not legal to initialize \" \"MachineInstrBundleIterator \" \"with a bundled MI\""
, "/build/llvm-toolchain-snapshot-12~++20200927111121+5811d723998/llvm/include/llvm/CodeGen/MachineInstrBundleIterator.h"
, 148, __PRETTY_FUNCTION__))
148 "with a bundled MI")(((!MI || !MI->isBundledWithPred()) && "It's not legal to initialize "
"MachineInstrBundleIterator " "with a bundled MI") ? static_cast
<void> (0) : __assert_fail ("(!MI || !MI->isBundledWithPred()) && \"It's not legal to initialize \" \"MachineInstrBundleIterator \" \"with a bundled MI\""
, "/build/llvm-toolchain-snapshot-12~++20200927111121+5811d723998/llvm/include/llvm/CodeGen/MachineInstrBundleIterator.h"
, 148, __PRETTY_FUNCTION__))
;
149 }
150
151 // Template allows conversion from const to nonconst.
152 template <class OtherTy>
153 MachineInstrBundleIterator(
154 const MachineInstrBundleIterator<OtherTy, IsReverse> &I,
155 std::enable_if_t<std::is_convertible<OtherTy *, Ty *>::value, void *> =
156 nullptr)
157 : MII(I.getInstrIterator()) {}
158
159 MachineInstrBundleIterator() : MII(nullptr) {}
160
161 /// Explicit conversion between forward/reverse iterators.
162 ///
163 /// Translate between forward and reverse iterators without changing range
164 /// boundaries. The resulting iterator will dereference (and have a handle)
165 /// to the previous node, which is somewhat unexpected; but converting the
166 /// two endpoints in a range will give the same range in reverse.
167 ///
168 /// This matches std::reverse_iterator conversions.
169 explicit MachineInstrBundleIterator(
170 const MachineInstrBundleIterator<Ty, !IsReverse> &I)
171 : MachineInstrBundleIterator(++I.getReverse()) {}
172
173 /// Get the bundle iterator for the given instruction's bundle.
174 static MachineInstrBundleIterator getAtBundleBegin(instr_iterator MI) {
175 return MachineInstrBundleIteratorHelper<IsReverse>::getBundleBegin(MI);
176 }
177
178 reference operator*() const { return *MII; }
179 pointer operator->() const { return &operator*(); }
180
181 /// Check for null.
182 bool isValid() const { return MII.getNodePtr(); }
183
184 friend bool operator==(const MachineInstrBundleIterator &L,
185 const MachineInstrBundleIterator &R) {
186 return L.MII == R.MII;
8
Calling 'operator=='
11
Returning from 'operator=='
12
Returning zero, which participates in a condition later
187 }
188 friend bool operator==(const MachineInstrBundleIterator &L,
189 const const_instr_iterator &R) {
190 return L.MII == R; // Avoid assertion about validity of R.
191 }
192 friend bool operator==(const const_instr_iterator &L,
193 const MachineInstrBundleIterator &R) {
194 return L == R.MII; // Avoid assertion about validity of L.
195 }
196 friend bool operator==(const MachineInstrBundleIterator &L,
197 const nonconst_instr_iterator &R) {
198 return L.MII == R; // Avoid assertion about validity of R.
199 }
200 friend bool operator==(const nonconst_instr_iterator &L,
201 const MachineInstrBundleIterator &R) {
202 return L == R.MII; // Avoid assertion about validity of L.
203 }
204 friend bool operator==(const MachineInstrBundleIterator &L, const_pointer R) {
205 return L == const_instr_iterator(R); // Avoid assertion about validity of R.
206 }
207 friend bool operator==(const_pointer L, const MachineInstrBundleIterator &R) {
208 return const_instr_iterator(L) == R; // Avoid assertion about validity of L.
209 }
210 friend bool operator==(const MachineInstrBundleIterator &L,
211 const_reference R) {
212 return L == &R; // Avoid assertion about validity of R.
213 }
214 friend bool operator==(const_reference L,
215 const MachineInstrBundleIterator &R) {
216 return &L == R; // Avoid assertion about validity of L.
217 }
218
219 friend bool operator!=(const MachineInstrBundleIterator &L,
220 const MachineInstrBundleIterator &R) {
221 return !(L == R);
7
Calling 'operator=='
13
Returning from 'operator=='
14
Returning the value 1, which participates in a condition later
222 }
223 friend bool operator!=(const MachineInstrBundleIterator &L,
224 const const_instr_iterator &R) {
225 return !(L == R);
226 }
227 friend bool operator!=(const const_instr_iterator &L,
228 const MachineInstrBundleIterator &R) {
229 return !(L == R);
230 }
231 friend bool operator!=(const MachineInstrBundleIterator &L,
232 const nonconst_instr_iterator &R) {
233 return !(L == R);
234 }
235 friend bool operator!=(const nonconst_instr_iterator &L,
236 const MachineInstrBundleIterator &R) {
237 return !(L == R);
238 }
239 friend bool operator!=(const MachineInstrBundleIterator &L, const_pointer R) {
240 return !(L == R);
241 }
242 friend bool operator!=(const_pointer L, const MachineInstrBundleIterator &R) {
243 return !(L == R);
244 }
245 friend bool operator!=(const MachineInstrBundleIterator &L,
246 const_reference R) {
247 return !(L == R);
248 }
249 friend bool operator!=(const_reference L,
250 const MachineInstrBundleIterator &R) {
251 return !(L == R);
252 }
253
254 // Increment and decrement operators...
255 MachineInstrBundleIterator &operator--() {
256 this->decrement(MII);
257 return *this;
258 }
259 MachineInstrBundleIterator &operator++() {
260 this->increment(MII);
261 return *this;
262 }
263 MachineInstrBundleIterator operator--(int) {
264 MachineInstrBundleIterator Temp = *this;
265 --*this;
266 return Temp;
267 }
268 MachineInstrBundleIterator operator++(int) {
269 MachineInstrBundleIterator Temp = *this;
270 ++*this;
271 return Temp;
272 }
273
274 instr_iterator getInstrIterator() const { return MII; }
275
276 nonconst_iterator getNonConstIterator() const { return MII.getNonConst(); }
277
278 /// Get a reverse iterator to the same node.
279 ///
280 /// Gives a reverse iterator that will dereference (and have a handle) to the
281 /// same node. Converting the endpoint iterators in a range will give a
282 /// different range; for range operations, use the explicit conversions.
283 reverse_iterator getReverse() const { return MII.getReverse(); }
284};
285
286} // end namespace llvm
287
288#endif // LLVM_CODEGEN_MACHINEINSTRBUNDLEITERATOR_H

/build/llvm-toolchain-snapshot-12~++20200927111121+5811d723998/llvm/include/llvm/CodeGen/MachineInstr.h

1//===- llvm/CodeGen/MachineInstr.h - MachineInstr class ---------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the declaration of the MachineInstr class, which is the
10// basic representation for all target dependent machine instructions used by
11// the back end.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef LLVM_CODEGEN_MACHINEINSTR_H
16#define LLVM_CODEGEN_MACHINEINSTR_H
17
18#include "llvm/ADT/DenseMapInfo.h"
19#include "llvm/ADT/PointerSumType.h"
20#include "llvm/ADT/ilist.h"
21#include "llvm/ADT/ilist_node.h"
22#include "llvm/ADT/iterator_range.h"
23#include "llvm/CodeGen/MachineMemOperand.h"
24#include "llvm/CodeGen/MachineOperand.h"
25#include "llvm/CodeGen/TargetOpcodes.h"
26#include "llvm/IR/DebugLoc.h"
27#include "llvm/IR/InlineAsm.h"
28#include "llvm/MC/MCInstrDesc.h"
29#include "llvm/MC/MCSymbol.h"
30#include "llvm/Support/ArrayRecycler.h"
31#include "llvm/Support/TrailingObjects.h"
32#include <algorithm>
33#include <cassert>
34#include <cstdint>
35#include <utility>
36
37namespace llvm {
38
39class AAResults;
40template <typename T> class ArrayRef;
41class DIExpression;
42class DILocalVariable;
43class MachineBasicBlock;
44class MachineFunction;
45class MachineRegisterInfo;
46class ModuleSlotTracker;
47class raw_ostream;
48template <typename T> class SmallVectorImpl;
49class SmallBitVector;
50class StringRef;
51class TargetInstrInfo;
52class TargetRegisterClass;
53class TargetRegisterInfo;
54
55//===----------------------------------------------------------------------===//
56/// Representation of each machine instruction.
57///
58/// This class isn't a POD type, but it must have a trivial destructor. When a
59/// MachineFunction is deleted, all the contained MachineInstrs are deallocated
60/// without having their destructor called.
61///
62class MachineInstr
63 : public ilist_node_with_parent<MachineInstr, MachineBasicBlock,
64 ilist_sentinel_tracking<true>> {
65public:
66 using mmo_iterator = ArrayRef<MachineMemOperand *>::iterator;
67
68 /// Flags to specify different kinds of comments to output in
69 /// assembly code. These flags carry semantic information not
70 /// otherwise easily derivable from the IR text.
71 ///
72 enum CommentFlag {
73 ReloadReuse = 0x1, // higher bits are reserved for target dep comments.
74 NoSchedComment = 0x2,
75 TAsmComments = 0x4 // Target Asm comments should start from this value.
76 };
77
78 enum MIFlag {
79 NoFlags = 0,
80 FrameSetup = 1 << 0, // Instruction is used as a part of
81 // function frame setup code.
82 FrameDestroy = 1 << 1, // Instruction is used as a part of
83 // function frame destruction code.
84 BundledPred = 1 << 2, // Instruction has bundled predecessors.
85 BundledSucc = 1 << 3, // Instruction has bundled successors.
86 FmNoNans = 1 << 4, // Instruction does not support Fast
87 // math nan values.
88 FmNoInfs = 1 << 5, // Instruction does not support Fast
89 // math infinity values.
90 FmNsz = 1 << 6, // Instruction is not required to retain
91 // signed zero values.
92 FmArcp = 1 << 7, // Instruction supports Fast math
93 // reciprocal approximations.
94 FmContract = 1 << 8, // Instruction supports Fast math
95 // contraction operations like fma.
96 FmAfn = 1 << 9, // Instruction may map to Fast math
97 // instrinsic approximation.
98 FmReassoc = 1 << 10, // Instruction supports Fast math
99 // reassociation of operand order.
100 NoUWrap = 1 << 11, // Instruction supports binary operator
101 // no unsigned wrap.
102 NoSWrap = 1 << 12, // Instruction supports binary operator
103 // no signed wrap.
104 IsExact = 1 << 13, // Instruction supports division is
105 // known to be exact.
106 NoFPExcept = 1 << 14, // Instruction does not raise
107 // floatint-point exceptions.
108 NoMerge = 1 << 15, // Passes that drop source location info
109 // (e.g. branch folding) should skip
110 // this instruction.
111 };
112
113private:
114 const MCInstrDesc *MCID; // Instruction descriptor.
115 MachineBasicBlock *Parent = nullptr; // Pointer to the owning basic block.
116
117 // Operands are allocated by an ArrayRecycler.
118 MachineOperand *Operands = nullptr; // Pointer to the first operand.
119 unsigned NumOperands = 0; // Number of operands on instruction.
120
121 uint16_t Flags = 0; // Various bits of additional
122 // information about machine
123 // instruction.
124
125 uint8_t AsmPrinterFlags = 0; // Various bits of information used by
126 // the AsmPrinter to emit helpful
127 // comments. This is *not* semantic
128 // information. Do not use this for
129 // anything other than to convey comment
130 // information to AsmPrinter.
131
132 // OperandCapacity has uint8_t size, so it should be next to AsmPrinterFlags
133 // to properly pack.
134 using OperandCapacity = ArrayRecycler<MachineOperand>::Capacity;
135 OperandCapacity CapOperands; // Capacity of the Operands array.
136
137 /// Internal implementation detail class that provides out-of-line storage for
138 /// extra info used by the machine instruction when this info cannot be stored
139 /// in-line within the instruction itself.
140 ///
141 /// This has to be defined eagerly due to the implementation constraints of
142 /// `PointerSumType` where it is used.
143 class ExtraInfo final
144 : TrailingObjects<ExtraInfo, MachineMemOperand *, MCSymbol *, MDNode *> {
145 public:
146 static ExtraInfo *create(BumpPtrAllocator &Allocator,
147 ArrayRef<MachineMemOperand *> MMOs,
148 MCSymbol *PreInstrSymbol = nullptr,
149 MCSymbol *PostInstrSymbol = nullptr,
150 MDNode *HeapAllocMarker = nullptr) {
151 bool HasPreInstrSymbol = PreInstrSymbol != nullptr;
152 bool HasPostInstrSymbol = PostInstrSymbol != nullptr;
153 bool HasHeapAllocMarker = HeapAllocMarker != nullptr;
154 auto *Result = new (Allocator.Allocate(
155 totalSizeToAlloc<MachineMemOperand *, MCSymbol *, MDNode *>(
156 MMOs.size(), HasPreInstrSymbol + HasPostInstrSymbol,
157 HasHeapAllocMarker),
158 alignof(ExtraInfo)))
159 ExtraInfo(MMOs.size(), HasPreInstrSymbol, HasPostInstrSymbol,
160 HasHeapAllocMarker);
161
162 // Copy the actual data into the trailing objects.
163 std::copy(MMOs.begin(), MMOs.end(),
164 Result->getTrailingObjects<MachineMemOperand *>());
165
166 if (HasPreInstrSymbol)
167 Result->getTrailingObjects<MCSymbol *>()[0] = PreInstrSymbol;
168 if (HasPostInstrSymbol)
169 Result->getTrailingObjects<MCSymbol *>()[HasPreInstrSymbol] =
170 PostInstrSymbol;
171 if (HasHeapAllocMarker)
172 Result->getTrailingObjects<MDNode *>()[0] = HeapAllocMarker;
173
174 return Result;
175 }
176
177 ArrayRef<MachineMemOperand *> getMMOs() const {
178 return makeArrayRef(getTrailingObjects<MachineMemOperand *>(), NumMMOs);
179 }
180
181 MCSymbol *getPreInstrSymbol() const {
182 return HasPreInstrSymbol ? getTrailingObjects<MCSymbol *>()[0] : nullptr;
183 }
184
185 MCSymbol *getPostInstrSymbol() const {
186 return HasPostInstrSymbol
187 ? getTrailingObjects<MCSymbol *>()[HasPreInstrSymbol]
188 : nullptr;
189 }
190
191 MDNode *getHeapAllocMarker() const {
192 return HasHeapAllocMarker ? getTrailingObjects<MDNode *>()[0] : nullptr;
193 }
194
195 private:
196 friend TrailingObjects;
197
198 // Description of the extra info, used to interpret the actual optional
199 // data appended.
200 //
201 // Note that this is not terribly space optimized. This leaves a great deal
202 // of flexibility to fit more in here later.
203 const int NumMMOs;
204 const bool HasPreInstrSymbol;
205 const bool HasPostInstrSymbol;
206 const bool HasHeapAllocMarker;
207
208 // Implement the `TrailingObjects` internal API.
209 size_t numTrailingObjects(OverloadToken<MachineMemOperand *>) const {
210 return NumMMOs;
211 }
212 size_t numTrailingObjects(OverloadToken<MCSymbol *>) const {
213 return HasPreInstrSymbol + HasPostInstrSymbol;
214 }
215 size_t numTrailingObjects(OverloadToken<MDNode *>) const {
216 return HasHeapAllocMarker;
217 }
218
219 // Just a boring constructor to allow us to initialize the sizes. Always use
220 // the `create` routine above.
221 ExtraInfo(int NumMMOs, bool HasPreInstrSymbol, bool HasPostInstrSymbol,
222 bool HasHeapAllocMarker)
223 : NumMMOs(NumMMOs), HasPreInstrSymbol(HasPreInstrSymbol),
224 HasPostInstrSymbol(HasPostInstrSymbol),
225 HasHeapAllocMarker(HasHeapAllocMarker) {}
226 };
227
228 /// Enumeration of the kinds of inline extra info available. It is important
229 /// that the `MachineMemOperand` inline kind has a tag value of zero to make
230 /// it accessible as an `ArrayRef`.
231 enum ExtraInfoInlineKinds {
232 EIIK_MMO = 0,
233 EIIK_PreInstrSymbol,
234 EIIK_PostInstrSymbol,
235 EIIK_OutOfLine
236 };
237
238 // We store extra information about the instruction here. The common case is
239 // expected to be nothing or a single pointer (typically a MMO or a symbol).
240 // We work to optimize this common case by storing it inline here rather than
241 // requiring a separate allocation, but we fall back to an allocation when
242 // multiple pointers are needed.
243 PointerSumType<ExtraInfoInlineKinds,
244 PointerSumTypeMember<EIIK_MMO, MachineMemOperand *>,
245 PointerSumTypeMember<EIIK_PreInstrSymbol, MCSymbol *>,
246 PointerSumTypeMember<EIIK_PostInstrSymbol, MCSymbol *>,
247 PointerSumTypeMember<EIIK_OutOfLine, ExtraInfo *>>
248 Info;
249
250 DebugLoc debugLoc; // Source line information.
251
252 /// Unique instruction number. Used by DBG_INSTR_REFs to refer to the values
253 /// defined by this instruction.
254 unsigned DebugInstrNum;
255
256 // Intrusive list support
257 friend struct ilist_traits<MachineInstr>;
258 friend struct ilist_callback_traits<MachineBasicBlock>;
259 void setParent(MachineBasicBlock *P) { Parent = P; }
260
261 /// This constructor creates a copy of the given
262 /// MachineInstr in the given MachineFunction.
263 MachineInstr(MachineFunction &, const MachineInstr &);
264
265 /// This constructor create a MachineInstr and add the implicit operands.
266 /// It reserves space for number of operands specified by
267 /// MCInstrDesc. An explicit DebugLoc is supplied.
268 MachineInstr(MachineFunction &, const MCInstrDesc &tid, DebugLoc dl,
269 bool NoImp = false);
270
271 // MachineInstrs are pool-allocated and owned by MachineFunction.
272 friend class MachineFunction;
273
274 void
275 dumprImpl(const MachineRegisterInfo &MRI, unsigned Depth, unsigned MaxDepth,
276 SmallPtrSetImpl<const MachineInstr *> &AlreadySeenInstrs) const;
277
278public:
279 MachineInstr(const MachineInstr &) = delete;
280 MachineInstr &operator=(const MachineInstr &) = delete;
281 // Use MachineFunction::DeleteMachineInstr() instead.
282 ~MachineInstr() = delete;
283
284 const MachineBasicBlock* getParent() const { return Parent; }
285 MachineBasicBlock* getParent() { return Parent; }
286
287 /// Move the instruction before \p MovePos.
288 void moveBefore(MachineInstr *MovePos);
289
290 /// Return the function that contains the basic block that this instruction
291 /// belongs to.
292 ///
293 /// Note: this is undefined behaviour if the instruction does not have a
294 /// parent.
295 const MachineFunction *getMF() const;
296 MachineFunction *getMF() {
297 return const_cast<MachineFunction *>(
298 static_cast<const MachineInstr *>(this)->getMF());
299 }
300
301 /// Return the asm printer flags bitvector.
302 uint8_t getAsmPrinterFlags() const { return AsmPrinterFlags; }
303
304 /// Clear the AsmPrinter bitvector.
305 void clearAsmPrinterFlags() { AsmPrinterFlags = 0; }
306
307 /// Return whether an AsmPrinter flag is set.
308 bool getAsmPrinterFlag(CommentFlag Flag) const {
309 return AsmPrinterFlags & Flag;
310 }
311
312 /// Set a flag for the AsmPrinter.
313 void setAsmPrinterFlag(uint8_t Flag) {
314 AsmPrinterFlags |= Flag;
315 }
316
317 /// Clear specific AsmPrinter flags.
318 void clearAsmPrinterFlag(CommentFlag Flag) {
319 AsmPrinterFlags &= ~Flag;
320 }
321
322 /// Return the MI flags bitvector.
323 uint16_t getFlags() const {
324 return Flags;
325 }
326
327 /// Return whether an MI flag is set.
328 bool getFlag(MIFlag Flag) const {
329 return Flags & Flag;
330 }
331
332 /// Set a MI flag.
333 void setFlag(MIFlag Flag) {
334 Flags |= (uint16_t)Flag;
335 }
336
337 void setFlags(unsigned flags) {
338 // Filter out the automatically maintained flags.
339 unsigned Mask = BundledPred | BundledSucc;
340 Flags = (Flags & Mask) | (flags & ~Mask);
341 }
342
343 /// clearFlag - Clear a MI flag.
344 void clearFlag(MIFlag Flag) {
345 Flags &= ~((uint16_t)Flag);
346 }
347
348 /// Return true if MI is in a bundle (but not the first MI in a bundle).
349 ///
350 /// A bundle looks like this before it's finalized:
351 /// ----------------
352 /// | MI |
353 /// ----------------
354 /// |
355 /// ----------------
356 /// | MI * |
357 /// ----------------
358 /// |
359 /// ----------------
360 /// | MI * |
361 /// ----------------
362 /// In this case, the first MI starts a bundle but is not inside a bundle, the
363 /// next 2 MIs are considered "inside" the bundle.
364 ///
365 /// After a bundle is finalized, it looks like this:
366 /// ----------------
367 /// | Bundle |
368 /// ----------------
369 /// |
370 /// ----------------
371 /// | MI * |
372 /// ----------------
373 /// |
374 /// ----------------
375 /// | MI * |
376 /// ----------------
377 /// |
378 /// ----------------
379 /// | MI * |
380 /// ----------------
381 /// The first instruction has the special opcode "BUNDLE". It's not "inside"
382 /// a bundle, but the next three MIs are.
383 bool isInsideBundle() const {
384 return getFlag(BundledPred);
385 }
386
387 /// Return true if this instruction part of a bundle. This is true
388 /// if either itself or its following instruction is marked "InsideBundle".
389 bool isBundled() const {
390 return isBundledWithPred() || isBundledWithSucc();
391 }
392
393 /// Return true if this instruction is part of a bundle, and it is not the
394 /// first instruction in the bundle.
395 bool isBundledWithPred() const { return getFlag(BundledPred); }
396
397 /// Return true if this instruction is part of a bundle, and it is not the
398 /// last instruction in the bundle.
399 bool isBundledWithSucc() const { return getFlag(BundledSucc); }
400
401 /// Bundle this instruction with its predecessor. This can be an unbundled
402 /// instruction, or it can be the first instruction in a bundle.
403 void bundleWithPred();
404
405 /// Bundle this instruction with its successor. This can be an unbundled
406 /// instruction, or it can be the last instruction in a bundle.
407 void bundleWithSucc();
408
409 /// Break bundle above this instruction.
410 void unbundleFromPred();
411
412 /// Break bundle below this instruction.
413 void unbundleFromSucc();
414
415 /// Returns the debug location id of this MachineInstr.
416 const DebugLoc &getDebugLoc() const { return debugLoc; }
417
418 /// Return the operand containing the offset to be used if this DBG_VALUE
419 /// instruction is indirect; will be an invalid register if this value is
420 /// not indirect, and an immediate with value 0 otherwise.
421 const MachineOperand &getDebugOffset() const {
422 assert(isDebugValue() && "not a DBG_VALUE")((isDebugValue() && "not a DBG_VALUE") ? static_cast<
void> (0) : __assert_fail ("isDebugValue() && \"not a DBG_VALUE\""
, "/build/llvm-toolchain-snapshot-12~++20200927111121+5811d723998/llvm/include/llvm/CodeGen/MachineInstr.h"
, 422, __PRETTY_FUNCTION__))
;
423 return getOperand(1);
424 }
425 MachineOperand &getDebugOffset() {
426 assert(isDebugValue() && "not a DBG_VALUE")((isDebugValue() && "not a DBG_VALUE") ? static_cast<
void> (0) : __assert_fail ("isDebugValue() && \"not a DBG_VALUE\""
, "/build/llvm-toolchain-snapshot-12~++20200927111121+5811d723998/llvm/include/llvm/CodeGen/MachineInstr.h"
, 426, __PRETTY_FUNCTION__))
;
427 return getOperand(1);
428 }
429
430 /// Return the operand for the debug variable referenced by
431 /// this DBG_VALUE instruction.
432 const MachineOperand &getDebugVariableOp() const;
433 MachineOperand &getDebugVariableOp();
434
435 /// Return the debug variable referenced by
436 /// this DBG_VALUE instruction.
437 const DILocalVariable *getDebugVariable() const;
438
439 /// Return the operand for the complex address expression referenced by
440 /// this DBG_VALUE instruction.
441 MachineOperand &getDebugExpressionOp();
442
443 /// Return the complex address expression referenced by
444 /// this DBG_VALUE instruction.
445 const DIExpression *getDebugExpression() const;
446
447 /// Return the debug label referenced by
448 /// this DBG_LABEL instruction.
449 const DILabel *getDebugLabel() const;
450
451 /// Fetch the instruction number of this MachineInstr. If it does not have
452 /// one already, a new and unique number will be assigned.
453 unsigned getDebugInstrNum();
454
455 /// Examine the instruction number of this MachineInstr. May be zero if
456 /// it hasn't been assigned a number yet.
457 unsigned peekDebugInstrNum() const { return DebugInstrNum; }
458
459 /// Emit an error referring to the source location of this instruction.
460 /// This should only be used for inline assembly that is somehow
461 /// impossible to compile. Other errors should have been handled much
462 /// earlier.
463 ///
464 /// If this method returns, the caller should try to recover from the error.
465 void emitError(StringRef Msg) const;
466
467 /// Returns the target instruction descriptor of this MachineInstr.
468 const MCInstrDesc &getDesc() const { return *MCID; }
469
470 /// Returns the opcode of this MachineInstr.
471 unsigned getOpcode() const { return MCID->Opcode; }
472
473 /// Retuns the total number of operands.
474 unsigned getNumOperands() const { return NumOperands; }
475
476 /// Returns the total number of operands which are debug locations.
477 unsigned getNumDebugOperands() const {
478 return std::distance(debug_operands().begin(), debug_operands().end());
479 }
480
481 const MachineOperand& getOperand(unsigned i) const {
482 assert(i < getNumOperands() && "getOperand() out of range!")((i < getNumOperands() && "getOperand() out of range!"
) ? static_cast<void> (0) : __assert_fail ("i < getNumOperands() && \"getOperand() out of range!\""
, "/build/llvm-toolchain-snapshot-12~++20200927111121+5811d723998/llvm/include/llvm/CodeGen/MachineInstr.h"
, 482, __PRETTY_FUNCTION__))
;
483 return Operands[i];
484 }
485 MachineOperand& getOperand(unsigned i) {
486 assert(i < getNumOperands() && "getOperand() out of range!")((i < getNumOperands() && "getOperand() out of range!"
) ? static_cast<void> (0) : __assert_fail ("i < getNumOperands() && \"getOperand() out of range!\""
, "/build/llvm-toolchain-snapshot-12~++20200927111121+5811d723998/llvm/include/llvm/CodeGen/MachineInstr.h"
, 486, __PRETTY_FUNCTION__))
;
487 return Operands[i];
488 }
489
490 MachineOperand &getDebugOperand(unsigned Index) {
491 assert(Index < getNumDebugOperands() && "getDebugOperand() out of range!")((Index < getNumDebugOperands() && "getDebugOperand() out of range!"
) ? static_cast<void> (0) : __assert_fail ("Index < getNumDebugOperands() && \"getDebugOperand() out of range!\""
, "/build/llvm-toolchain-snapshot-12~++20200927111121+5811d723998/llvm/include/llvm/CodeGen/MachineInstr.h"
, 491, __PRETTY_FUNCTION__))
;
492 return *(debug_operands().begin() + Index);
493 }
494 const MachineOperand &getDebugOperand(unsigned Index) const {
495 assert(Index < getNumDebugOperands() && "getDebugOperand() out of range!")((Index < getNumDebugOperands() && "getDebugOperand() out of range!"
) ? static_cast<void> (0) : __assert_fail ("Index < getNumDebugOperands() && \"getDebugOperand() out of range!\""
, "/build/llvm-toolchain-snapshot-12~++20200927111121+5811d723998/llvm/include/llvm/CodeGen/MachineInstr.h"
, 495, __PRETTY_FUNCTION__))
;
496 return *(debug_operands().begin() + Index);
497 }
498
499 /// Returns a pointer to the operand corresponding to a debug use of Reg, or
500 /// nullptr if Reg is not used in any debug operand.
501 const MachineOperand *getDebugOperandForReg(Register Reg) const {
502 const MachineOperand *RegOp =
503 find_if(debug_operands(), [Reg](const MachineOperand &Op) {
504 return Op.isReg() && Op.getReg() == Reg;
505 });
506 return RegOp == adl_end(debug_operands()) ? nullptr : RegOp;
507 }
508 MachineOperand *getDebugOperandForReg(Register Reg) {
509 MachineOperand *RegOp =
510 find_if(debug_operands(), [Reg](const MachineOperand &Op) {
511 return Op.isReg() && Op.getReg() == Reg;
512 });
513 return RegOp == adl_end(debug_operands()) ? nullptr : RegOp;
514 }
515
516 unsigned getDebugOperandIndex(const MachineOperand *Op) const {
517 assert(Op >= adl_begin(debug_operands()) &&((Op >= adl_begin(debug_operands()) && Op <= adl_end
(debug_operands()) && "Expected a debug operand.") ? static_cast
<void> (0) : __assert_fail ("Op >= adl_begin(debug_operands()) && Op <= adl_end(debug_operands()) && \"Expected a debug operand.\""
, "/build/llvm-toolchain-snapshot-12~++20200927111121+5811d723998/llvm/include/llvm/CodeGen/MachineInstr.h"
, 518, __PRETTY_FUNCTION__))
518 Op <= adl_end(debug_operands()) && "Expected a debug operand.")((Op >= adl_begin(debug_operands()) && Op <= adl_end
(debug_operands()) && "Expected a debug operand.") ? static_cast
<void> (0) : __assert_fail ("Op >= adl_begin(debug_operands()) && Op <= adl_end(debug_operands()) && \"Expected a debug operand.\""
, "/build/llvm-toolchain-snapshot-12~++20200927111121+5811d723998/llvm/include/llvm/CodeGen/MachineInstr.h"
, 518, __PRETTY_FUNCTION__))
;
519 return std::distance(adl_begin(debug_operands()), Op);
520 }
521
522 /// Returns the total number of definitions.
523 unsigned getNumDefs() const {
524 return getNumExplicitDefs() + MCID->getNumImplicitDefs();
525 }
526
527 /// Returns true if the instruction has implicit definition.
528 bool hasImplicitDef() const {
529 for (unsigned I = getNumExplicitOperands(), E = getNumOperands();
530 I != E; ++I) {
531 const MachineOperand &MO = getOperand(I);
532 if (MO.isDef() && MO.isImplicit())
533 return true;
534 }
535 return false;
536 }
537
538 /// Returns the implicit operands number.
539 unsigned getNumImplicitOperands() const {
540 return getNumOperands() - getNumExplicitOperands();
541 }
542
543 /// Return true if operand \p OpIdx is a subregister index.
544 bool isOperandSubregIdx(unsigned OpIdx) const {
545 assert(getOperand(OpIdx).getType() == MachineOperand::MO_Immediate &&((getOperand(OpIdx).getType() == MachineOperand::MO_Immediate
&& "Expected MO_Immediate operand type.") ? static_cast
<void> (0) : __assert_fail ("getOperand(OpIdx).getType() == MachineOperand::MO_Immediate && \"Expected MO_Immediate operand type.\""
, "/build/llvm-toolchain-snapshot-12~++20200927111121+5811d723998/llvm/include/llvm/CodeGen/MachineInstr.h"
, 546, __PRETTY_FUNCTION__))
546 "Expected MO_Immediate operand type.")((getOperand(OpIdx).getType() == MachineOperand::MO_Immediate
&& "Expected MO_Immediate operand type.") ? static_cast
<void> (0) : __assert_fail ("getOperand(OpIdx).getType() == MachineOperand::MO_Immediate && \"Expected MO_Immediate operand type.\""
, "/build/llvm-toolchain-snapshot-12~++20200927111121+5811d723998/llvm/include/llvm/CodeGen/MachineInstr.h"
, 546, __PRETTY_FUNCTION__))
;
547 if (isExtractSubreg() && OpIdx == 2)
548 return true;
549 if (isInsertSubreg() && OpIdx == 3)
550 return true;
551 if (isRegSequence() && OpIdx > 1 && (OpIdx % 2) == 0)
552 return true;
553 if (isSubregToReg() && OpIdx == 3)
554 return true;
555 return false;
556 }
557
558 /// Returns the number of non-implicit operands.
559 unsigned getNumExplicitOperands() const;
560
561 /// Returns the number of non-implicit definitions.
562 unsigned getNumExplicitDefs() const;
563
564 /// iterator/begin/end - Iterate over all operands of a machine instruction.
565 using mop_iterator = MachineOperand *;
566 using const_mop_iterator = const MachineOperand *;
567
568 mop_iterator operands_begin() { return Operands; }
569 mop_iterator operands_end() { return Operands + NumOperands; }
570
571 const_mop_iterator operands_begin() const { return Operands; }
572 const_mop_iterator operands_end() const { return Operands + NumOperands; }
573
574 iterator_range<mop_iterator> operands() {
575 return make_range(operands_begin(), operands_end());
576 }
577 iterator_range<const_mop_iterator> operands() const {
578 return make_range(operands_begin(), operands_end());
579 }
580 iterator_range<mop_iterator> explicit_operands() {
581 return make_range(operands_begin(),
582 operands_begin() + getNumExplicitOperands());
583 }
584 iterator_range<const_mop_iterator> explicit_operands() const {
585 return make_range(operands_begin(),
586 operands_begin() + getNumExplicitOperands());
587 }
588 iterator_range<mop_iterator> implicit_operands() {
589 return make_range(explicit_operands().end(), operands_end());
590 }
591 iterator_range<const_mop_iterator> implicit_operands() const {
592 return make_range(explicit_operands().end(), operands_end());
593 }
594 /// Returns a range over all operands that are used to determine the variable
595 /// location for this DBG_VALUE instruction.
596 iterator_range<mop_iterator> debug_operands() {
597 assert(isDebugValue() && "Must be a debug value instruction.")((isDebugValue() && "Must be a debug value instruction."
) ? static_cast<void> (0) : __assert_fail ("isDebugValue() && \"Must be a debug value instruction.\""
, "/build/llvm-toolchain-snapshot-12~++20200927111121+5811d723998/llvm/include/llvm/CodeGen/MachineInstr.h"
, 597, __PRETTY_FUNCTION__))
;
598 return make_range(operands_begin(), operands_begin() + 1);
599 }
600 /// \copydoc debug_operands()
601 iterator_range<const_mop_iterator> debug_operands() const {
602 assert(isDebugValue() && "Must be a debug value instruction.")((isDebugValue() && "Must be a debug value instruction."
) ? static_cast<void> (0) : __assert_fail ("isDebugValue() && \"Must be a debug value instruction.\""
, "/build/llvm-toolchain-snapshot-12~++20200927111121+5811d723998/llvm/include/llvm/CodeGen/MachineInstr.h"
, 602, __PRETTY_FUNCTION__))
;
603 return make_range(operands_begin(), operands_begin() + 1);
604 }
605 /// Returns a range over all explicit operands that are register definitions.
606 /// Implicit definition are not included!
607 iterator_range<mop_iterator> defs() {
608 return make_range(operands_begin(),
609 operands_begin() + getNumExplicitDefs());
610 }
611 /// \copydoc defs()
612 iterator_range<const_mop_iterator> defs() const {
613 return make_range(operands_begin(),
614 operands_begin() + getNumExplicitDefs());
615 }
616 /// Returns a range that includes all operands that are register uses.
617 /// This may include unrelated operands which are not register uses.
618 iterator_range<mop_iterator> uses() {
619 return make_range(operands_begin() + getNumExplicitDefs(), operands_end());
620 }
621 /// \copydoc uses()
622 iterator_range<const_mop_iterator> uses() const {
623 return make_range(operands_begin() + getNumExplicitDefs(), operands_end());
624 }
625 iterator_range<mop_iterator> explicit_uses() {
626 return make_range(operands_begin() + getNumExplicitDefs(),
627 operands_begin() + getNumExplicitOperands());
628 }
629 iterator_range<const_mop_iterator> explicit_uses() const {
630 return make_range(operands_begin() + getNumExplicitDefs(),
631 operands_begin() + getNumExplicitOperands());
632 }
633
634 /// Returns the number of the operand iterator \p I points to.
635 unsigned getOperandNo(const_mop_iterator I) const {
636 return I - operands_begin();
637 }
638
639 /// Access to memory operands of the instruction. If there are none, that does
640 /// not imply anything about whether the function accesses memory. Instead,
641 /// the caller must behave conservatively.
642 ArrayRef<MachineMemOperand *> memoperands() const {
643 if (!Info)
644 return {};
645
646 if (Info.is<EIIK_MMO>())
647 return makeArrayRef(Info.getAddrOfZeroTagPointer(), 1);
648
649 if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
650 return EI->getMMOs();
651
652 return {};
653 }
654
655 /// Access to memory operands of the instruction.
656 ///
657 /// If `memoperands_begin() == memoperands_end()`, that does not imply
658 /// anything about whether the function accesses memory. Instead, the caller
659 /// must behave conservatively.
660 mmo_iterator memoperands_begin() const { return memoperands().begin(); }
661
662 /// Access to memory operands of the instruction.
663 ///
664 /// If `memoperands_begin() == memoperands_end()`, that does not imply
665 /// anything about whether the function accesses memory. Instead, the caller
666 /// must behave conservatively.
667 mmo_iterator memoperands_end() const { return memoperands().end(); }
668
669 /// Return true if we don't have any memory operands which described the
670 /// memory access done by this instruction. If this is true, calling code
671 /// must be conservative.
672 bool memoperands_empty() const { return memoperands().empty(); }
673
674 /// Return true if this instruction has exactly one MachineMemOperand.
675 bool hasOneMemOperand() const { return memoperands().size() == 1; }
676
677 /// Return the number of memory operands.
678 unsigned getNumMemOperands() const { return memoperands().size(); }
679
680 /// Helper to extract a pre-instruction symbol if one has been added.
681 MCSymbol *getPreInstrSymbol() const {
682 if (!Info)
683 return nullptr;
684 if (MCSymbol *S = Info.get<EIIK_PreInstrSymbol>())
685 return S;
686 if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
687 return EI->getPreInstrSymbol();
688
689 return nullptr;
690 }
691
692 /// Helper to extract a post-instruction symbol if one has been added.
693 MCSymbol *getPostInstrSymbol() const {
694 if (!Info)
695 return nullptr;
696 if (MCSymbol *S = Info.get<EIIK_PostInstrSymbol>())
697 return S;
698 if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
699 return EI->getPostInstrSymbol();
700
701 return nullptr;
702 }
703
704 /// Helper to extract a heap alloc marker if one has been added.
705 MDNode *getHeapAllocMarker() const {
706 if (!Info)
707 return nullptr;
708 if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
709 return EI->getHeapAllocMarker();
710
711 return nullptr;
712 }
713
714 /// API for querying MachineInstr properties. They are the same as MCInstrDesc
715 /// queries but they are bundle aware.
716
717 enum QueryType {
718 IgnoreBundle, // Ignore bundles
719 AnyInBundle, // Return true if any instruction in bundle has property
720 AllInBundle // Return true if all instructions in bundle have property
721 };
722
723 /// Return true if the instruction (or in the case of a bundle,
724 /// the instructions inside the bundle) has the specified property.
725 /// The first argument is the property being queried.
726 /// The second argument indicates whether the query should look inside
727 /// instruction bundles.
728 bool hasProperty(unsigned MCFlag, QueryType Type = AnyInBundle) const {
729 assert(MCFlag < 64 &&((MCFlag < 64 && "MCFlag out of range for bit mask in getFlags/hasPropertyInBundle."
) ? static_cast<void> (0) : __assert_fail ("MCFlag < 64 && \"MCFlag out of range for bit mask in getFlags/hasPropertyInBundle.\""
, "/build/llvm-toolchain-snapshot-12~++20200927111121+5811d723998/llvm/include/llvm/CodeGen/MachineInstr.h"
, 730, __PRETTY_FUNCTION__))
26
'?' condition is true
730 "MCFlag out of range for bit mask in getFlags/hasPropertyInBundle.")((MCFlag < 64 && "MCFlag out of range for bit mask in getFlags/hasPropertyInBundle."
) ? static_cast<void> (0) : __assert_fail ("MCFlag < 64 && \"MCFlag out of range for bit mask in getFlags/hasPropertyInBundle.\""
, "/build/llvm-toolchain-snapshot-12~++20200927111121+5811d723998/llvm/include/llvm/CodeGen/MachineInstr.h"
, 730, __PRETTY_FUNCTION__))
;
731 // Inline the fast path for unbundled or bundle-internal instructions.
732 if (Type
26.1
'Type' is not equal to IgnoreBundle
26.1
'Type' is not equal to IgnoreBundle
26.1
'Type' is not equal to IgnoreBundle
26.1
'Type' is not equal to IgnoreBundle
== IgnoreBundle || !isBundled() || isBundledWithPred())
27
Taking true branch
733 return getDesc().getFlags() & (1ULL << MCFlag);
28
Returning value, which participates in a condition later
734
735 // If this is the first instruction in a bundle, take the slow path.
736 return hasPropertyInBundle(1ULL << MCFlag, Type);
737 }
738
739 /// Return true if this is an instruction that should go through the usual
740 /// legalization steps.
741 bool isPreISelOpcode(QueryType Type = IgnoreBundle) const {
742 return hasProperty(MCID::PreISelOpcode, Type);
743 }
744
745 /// Return true if this instruction can have a variable number of operands.
746 /// In this case, the variable operands will be after the normal
747 /// operands but before the implicit definitions and uses (if any are
748 /// present).
749 bool isVariadic(QueryType Type = IgnoreBundle) const {
750 return hasProperty(MCID::Variadic, Type);
751 }
752
753 /// Set if this instruction has an optional definition, e.g.
754 /// ARM instructions which can set condition code if 's' bit is set.
755 bool hasOptionalDef(QueryType Type = IgnoreBundle) const {
756 return hasProperty(MCID::HasOptionalDef, Type);
757 }
758
759 /// Return true if this is a pseudo instruction that doesn't
760 /// correspond to a real machine instruction.
761 bool isPseudo(QueryType Type = IgnoreBundle) const {
762 return hasProperty(MCID::Pseudo, Type);
763 }
764
765 bool isReturn(QueryType Type = AnyInBundle) const {
766 return hasProperty(MCID::Return, Type);
767 }
768
769 /// Return true if this is an instruction that marks the end of an EH scope,
770 /// i.e., a catchpad or a cleanuppad instruction.
771 bool isEHScopeReturn(QueryType Type = AnyInBundle) const {
772 return hasProperty(MCID::EHScopeReturn, Type);
773 }
774
775 bool isCall(QueryType Type = AnyInBundle) const {
776 return hasProperty(MCID::Call, Type);
777 }
778
779 /// Return true if this is a call instruction that may have an associated
780 /// call site entry in the debug info.
781 bool isCandidateForCallSiteEntry(QueryType Type = IgnoreBundle) const;
782 /// Return true if copying, moving, or erasing this instruction requires
783 /// updating Call Site Info (see \ref copyCallSiteInfo, \ref moveCallSiteInfo,
784 /// \ref eraseCallSiteInfo).
785 bool shouldUpdateCallSiteInfo() const;
786
787 /// Returns true if the specified instruction stops control flow
788 /// from executing the instruction immediately following it. Examples include
789 /// unconditional branches and return instructions.
790 bool isBarrier(QueryType Type = AnyInBundle) const {
791 return hasProperty(MCID::Barrier, Type);
792 }
793
794 /// Returns true if this instruction part of the terminator for a basic block.
795 /// Typically this is things like return and branch instructions.
796 ///
797 /// Various passes use this to insert code into the bottom of a basic block,
798 /// but before control flow occurs.
799 bool isTerminator(QueryType Type = AnyInBundle) const {
800 return hasProperty(MCID::Terminator, Type);
801 }
802
803 /// Returns true if this is a conditional, unconditional, or indirect branch.
804 /// Predicates below can be used to discriminate between
805 /// these cases, and the TargetInstrInfo::analyzeBranch method can be used to
806 /// get more information.
807 bool isBranch(QueryType Type = AnyInBundle) const {
808 return hasProperty(MCID::Branch, Type);
809 }
810
811 /// Return true if this is an indirect branch, such as a
812 /// branch through a register.
813 bool isIndirectBranch(QueryType Type = AnyInBundle) const {
814 return hasProperty(MCID::IndirectBranch, Type);
815 }
816
817 /// Return true if this is a branch which may fall
818 /// through to the next instruction or may transfer control flow to some other
819 /// block. The TargetInstrInfo::analyzeBranch method can be used to get more
820 /// information about this branch.
821 bool isConditionalBranch(QueryType Type = AnyInBundle) const {
822 return isBranch(Type) && !isBarrier(Type) && !isIndirectBranch(Type);
823 }
824
825 /// Return true if this is a branch which always
826 /// transfers control flow to some other block. The
827 /// TargetInstrInfo::analyzeBranch method can be used to get more information
828 /// about this branch.
829 bool isUnconditionalBranch(QueryType Type = AnyInBundle) const {
830 return isBranch(Type) && isBarrier(Type) && !isIndirectBranch(Type);
831 }
832
833 /// Return true if this instruction has a predicate operand that
834 /// controls execution. It may be set to 'always', or may be set to other
835 /// values. There are various methods in TargetInstrInfo that can be used to
836 /// control and modify the predicate in this instruction.
837 bool isPredicable(QueryType Type = AllInBundle) const {
838 // If it's a bundle than all bundled instructions must be predicable for this
839 // to return true.
840 return hasProperty(MCID::Predicable, Type);
841 }
842
843 /// Return true if this instruction is a comparison.
844 bool isCompare(QueryType Type = IgnoreBundle) const {
845 return hasProperty(MCID::Compare, Type);
846 }
847
848 /// Return true if this instruction is a move immediate
849 /// (including conditional moves) instruction.
850 bool isMoveImmediate(QueryType Type = IgnoreBundle) const {
851 return hasProperty(MCID::MoveImm, Type);
852 }
853
854 /// Return true if this instruction is a register move.
855 /// (including moving values from subreg to reg)
856 bool isMoveReg(QueryType Type = IgnoreBundle) const {
857 return hasProperty(MCID::MoveReg, Type);
858 }
859
860 /// Return true if this instruction is a bitcast instruction.
861 bool isBitcast(QueryType Type = IgnoreBundle) const {
862 return hasProperty(MCID::Bitcast, Type);
863 }
864
865 /// Return true if this instruction is a select instruction.
866 bool isSelect(QueryType Type = IgnoreBundle) const {
867 return hasProperty(MCID::Select, Type);
868 }
869
870 /// Return true if this instruction cannot be safely duplicated.
871 /// For example, if the instruction has a unique labels attached
872 /// to it, duplicating it would cause multiple definition errors.
873 bool isNotDuplicable(QueryType Type = AnyInBundle) const {
874 return hasProperty(MCID::NotDuplicable, Type);
875 }
876
877 /// Return true if this instruction is convergent.
878 /// Convergent instructions can not be made control-dependent on any
879 /// additional values.
880 bool isConvergent(QueryType Type = AnyInBundle) const {
881 if (isInlineAsm()) {
882 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
883 if (ExtraInfo & InlineAsm::Extra_IsConvergent)
884 return true;
885 }
886 return hasProperty(MCID::Convergent, Type);
887 }
888
889 /// Returns true if the specified instruction has a delay slot
890 /// which must be filled by the code generator.
891 bool hasDelaySlot(QueryType Type = AnyInBundle) const {
892 return hasProperty(MCID::DelaySlot, Type);
893 }
894
895 /// Return true for instructions that can be folded as
896 /// memory operands in other instructions. The most common use for this
897 /// is instructions that are simple loads from memory that don't modify
898 /// the loaded value in any way, but it can also be used for instructions
899 /// that can be expressed as constant-pool loads, such as V_SETALLONES
900 /// on x86, to allow them to be folded when it is beneficial.
901 /// This should only be set on instructions that return a value in their
902 /// only virtual register definition.
903 bool canFoldAsLoad(QueryType Type = IgnoreBundle) const {
904 return hasProperty(MCID::FoldableAsLoad, Type);
905 }
906
907 /// Return true if this instruction behaves
908 /// the same way as the generic REG_SEQUENCE instructions.
909 /// E.g., on ARM,
910 /// dX VMOVDRR rY, rZ
911 /// is equivalent to
912 /// dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1.
913 ///
914 /// Note that for the optimizers to be able to take advantage of
915 /// this property, TargetInstrInfo::getRegSequenceLikeInputs has to be
916 /// override accordingly.
917 bool isRegSequenceLike(QueryType Type = IgnoreBundle) const {
918 return hasProperty(MCID::RegSequence, Type);
919 }
920
921 /// Return true if this instruction behaves
922 /// the same way as the generic EXTRACT_SUBREG instructions.
923 /// E.g., on ARM,
924 /// rX, rY VMOVRRD dZ
925 /// is equivalent to two EXTRACT_SUBREG:
926 /// rX = EXTRACT_SUBREG dZ, ssub_0
927 /// rY = EXTRACT_SUBREG dZ, ssub_1
928 ///
929 /// Note that for the optimizers to be able to take advantage of
930 /// this property, TargetInstrInfo::getExtractSubregLikeInputs has to be
931 /// override accordingly.
932 bool isExtractSubregLike(QueryType Type = IgnoreBundle) const {
933 return hasProperty(MCID::ExtractSubreg, Type);
934 }
935
936 /// Return true if this instruction behaves
937 /// the same way as the generic INSERT_SUBREG instructions.
938 /// E.g., on ARM,
939 /// dX = VSETLNi32 dY, rZ, Imm
940 /// is equivalent to a INSERT_SUBREG:
941 /// dX = INSERT_SUBREG dY, rZ, translateImmToSubIdx(Imm)
942 ///
943 /// Note that for the optimizers to be able to take advantage of
944 /// this property, TargetInstrInfo::getInsertSubregLikeInputs has to be
945 /// override accordingly.
946 bool isInsertSubregLike(QueryType Type = IgnoreBundle) const {
947 return hasProperty(MCID::InsertSubreg, Type);
948 }
949
950 //===--------------------------------------------------------------------===//
951 // Side Effect Analysis
952 //===--------------------------------------------------------------------===//
953
954 /// Return true if this instruction could possibly read memory.
955 /// Instructions with this flag set are not necessarily simple load
956 /// instructions, they may load a value and modify it, for example.
957 bool mayLoad(QueryType Type = AnyInBundle) const {
958 if (isInlineAsm()) {
959 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
960 if (ExtraInfo & InlineAsm::Extra_MayLoad)
961 return true;
962 }
963 return hasProperty(MCID::MayLoad, Type);
964 }
965
966 /// Return true if this instruction could possibly modify memory.
967 /// Instructions with this flag set are not necessarily simple store
968 /// instructions, they may store a modified value based on their operands, or
969 /// may not actually modify anything, for example.
970 bool mayStore(QueryType Type = AnyInBundle) const {
971 if (isInlineAsm()) {
19
Calling 'MachineInstr::isInlineAsm'
23
Returning from 'MachineInstr::isInlineAsm'
24
Taking false branch
972 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
973 if (ExtraInfo & InlineAsm::Extra_MayStore)
974 return true;
975 }
976 return hasProperty(MCID::MayStore, Type);
25
Calling 'MachineInstr::hasProperty'
29
Returning from 'MachineInstr::hasProperty'
30
Returning value, which participates in a condition later
977 }
978
979 /// Return true if this instruction could possibly read or modify memory.
980 bool mayLoadOrStore(QueryType Type = AnyInBundle) const {
981 return mayLoad(Type) || mayStore(Type);
982 }
983
984 /// Return true if this instruction could possibly raise a floating-point
985 /// exception. This is the case if the instruction is a floating-point
986 /// instruction that can in principle raise an exception, as indicated
987 /// by the MCID::MayRaiseFPException property, *and* at the same time,
988 /// the instruction is used in a context where we expect floating-point
989 /// exceptions are not disabled, as indicated by the NoFPExcept MI flag.
990 bool mayRaiseFPException() const {
991 return hasProperty(MCID::MayRaiseFPException) &&
992 !getFlag(MachineInstr::MIFlag::NoFPExcept);
993 }
994
995 //===--------------------------------------------------------------------===//
996 // Flags that indicate whether an instruction can be modified by a method.
997 //===--------------------------------------------------------------------===//
998
999 /// Return true if this may be a 2- or 3-address
1000 /// instruction (of the form "X = op Y, Z, ..."), which produces the same
1001 /// result if Y and Z are exchanged. If this flag is set, then the
1002 /// TargetInstrInfo::commuteInstruction method may be used to hack on the
1003 /// instruction.
1004 ///
1005 /// Note that this flag may be set on instructions that are only commutable
1006 /// sometimes. In these cases, the call to commuteInstruction will fail.
1007 /// Also note that some instructions require non-trivial modification to
1008 /// commute them.
1009 bool isCommutable(QueryType Type = IgnoreBundle) const {
1010 return hasProperty(MCID::Commutable, Type);
1011 }
1012
1013 /// Return true if this is a 2-address instruction
1014 /// which can be changed into a 3-address instruction if needed. Doing this
1015 /// transformation can be profitable in the register allocator, because it
1016 /// means that the instruction can use a 2-address form if possible, but
1017 /// degrade into a less efficient form if the source and dest register cannot
1018 /// be assigned to the same register. For example, this allows the x86
1019 /// backend to turn a "shl reg, 3" instruction into an LEA instruction, which
1020 /// is the same speed as the shift but has bigger code size.
1021 ///
1022 /// If this returns true, then the target must implement the
1023 /// TargetInstrInfo::convertToThreeAddress method for this instruction, which
1024 /// is allowed to fail if the transformation isn't valid for this specific
1025 /// instruction (e.g. shl reg, 4 on x86).
1026 ///
1027 bool isConvertibleTo3Addr(QueryType Type = IgnoreBundle) const {
1028 return hasProperty(MCID::ConvertibleTo3Addr, Type);
1029 }
1030
1031 /// Return true if this instruction requires
1032 /// custom insertion support when the DAG scheduler is inserting it into a
1033 /// machine basic block. If this is true for the instruction, it basically
1034 /// means that it is a pseudo instruction used at SelectionDAG time that is
1035 /// expanded out into magic code by the target when MachineInstrs are formed.
1036 ///
1037 /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
1038 /// is used to insert this into the MachineBasicBlock.
1039 bool usesCustomInsertionHook(QueryType Type = IgnoreBundle) const {
1040 return hasProperty(MCID::UsesCustomInserter, Type);
1041 }
1042
1043 /// Return true if this instruction requires *adjustment*
1044 /// after instruction selection by calling a target hook. For example, this
1045 /// can be used to fill in ARM 's' optional operand depending on whether
1046 /// the conditional flag register is used.
1047 bool hasPostISelHook(QueryType Type = IgnoreBundle) const {
1048 return hasProperty(MCID::HasPostISelHook, Type);
1049 }
1050
1051 /// Returns true if this instruction is a candidate for remat.
1052 /// This flag is deprecated, please don't use it anymore. If this
1053 /// flag is set, the isReallyTriviallyReMaterializable() method is called to
1054 /// verify the instruction is really rematable.
1055 bool isRematerializable(QueryType Type = AllInBundle) const {
1056 // It's only possible to re-mat a bundle if all bundled instructions are
1057 // re-materializable.
1058 return hasProperty(MCID::Rematerializable, Type);
1059 }
1060
1061 /// Returns true if this instruction has the same cost (or less) than a move
1062 /// instruction. This is useful during certain types of optimizations
1063 /// (e.g., remat during two-address conversion or machine licm)
1064 /// where we would like to remat or hoist the instruction, but not if it costs
1065 /// more than moving the instruction into the appropriate register. Note, we
1066 /// are not marking copies from and to the same register class with this flag.
1067 bool isAsCheapAsAMove(QueryType Type = AllInBundle) const {
1068 // Only returns true for a bundle if all bundled instructions are cheap.
1069 return hasProperty(MCID::CheapAsAMove, Type);
1070 }
1071
1072 /// Returns true if this instruction source operands
1073 /// have special register allocation requirements that are not captured by the
1074 /// operand register classes. e.g. ARM::STRD's two source registers must be an
1075 /// even / odd pair, ARM::STM registers have to be in ascending order.
1076 /// Post-register allocation passes should not attempt to change allocations
1077 /// for sources of instructions with this flag.
1078 bool hasExtraSrcRegAllocReq(QueryType Type = AnyInBundle) const {
1079 return hasProperty(MCID::ExtraSrcRegAllocReq, Type);
1080 }
1081
1082 /// Returns true if this instruction def operands
1083 /// have special register allocation requirements that are not captured by the
1084 /// operand register classes. e.g. ARM::LDRD's two def registers must be an
1085 /// even / odd pair, ARM::LDM registers have to be in ascending order.
1086 /// Post-register allocation passes should not attempt to change allocations
1087 /// for definitions of instructions with this flag.
1088 bool hasExtraDefRegAllocReq(QueryType Type = AnyInBundle) const {
1089 return hasProperty(MCID::ExtraDefRegAllocReq, Type);
1090 }
1091
1092 enum MICheckType {
1093 CheckDefs, // Check all operands for equality
1094 CheckKillDead, // Check all operands including kill / dead markers
1095 IgnoreDefs, // Ignore all definitions
1096 IgnoreVRegDefs // Ignore virtual register definitions
1097 };
1098
1099 /// Return true if this instruction is identical to \p Other.
1100 /// Two instructions are identical if they have the same opcode and all their
1101 /// operands are identical (with respect to MachineOperand::isIdenticalTo()).
1102 /// Note that this means liveness related flags (dead, undef, kill) do not
1103 /// affect the notion of identical.
1104 bool isIdenticalTo(const MachineInstr &Other,
1105 MICheckType Check = CheckDefs) const;
1106
1107 /// Unlink 'this' from the containing basic block, and return it without
1108 /// deleting it.
1109 ///
1110 /// This function can not be used on bundled instructions, use
1111 /// removeFromBundle() to remove individual instructions from a bundle.
1112 MachineInstr *removeFromParent();
1113
1114 /// Unlink this instruction from its basic block and return it without
1115 /// deleting it.
1116 ///
1117 /// If the instruction is part of a bundle, the other instructions in the
1118 /// bundle remain bundled.
1119 MachineInstr *removeFromBundle();
1120
1121 /// Unlink 'this' from the containing basic block and delete it.
1122 ///
1123 /// If this instruction is the header of a bundle, the whole bundle is erased.
1124 /// This function can not be used for instructions inside a bundle, use
1125 /// eraseFromBundle() to erase individual bundled instructions.
1126 void eraseFromParent();
1127
1128 /// Unlink 'this' from the containing basic block and delete it.
1129 ///
1130 /// For all definitions mark their uses in DBG_VALUE nodes
1131 /// as undefined. Otherwise like eraseFromParent().
1132 void eraseFromParentAndMarkDBGValuesForRemoval();
1133
1134 /// Unlink 'this' form its basic block and delete it.
1135 ///
1136 /// If the instruction is part of a bundle, the other instructions in the
1137 /// bundle remain bundled.
1138 void eraseFromBundle();
1139
1140 bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; }
1141 bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; }
1142 bool isAnnotationLabel() const {
1143 return getOpcode() == TargetOpcode::ANNOTATION_LABEL;
1144 }
1145
1146 /// Returns true if the MachineInstr represents a label.
1147 bool isLabel() const {
1148 return isEHLabel() || isGCLabel() || isAnnotationLabel();
1149 }
1150
1151 bool isCFIInstruction() const {
1152 return getOpcode() == TargetOpcode::CFI_INSTRUCTION;
1153 }
1154
1155 // True if the instruction represents a position in the function.
1156 bool isPosition() const { return isLabel() || isCFIInstruction(); }
1157
1158 bool isDebugValue() const { return getOpcode() == TargetOpcode::DBG_VALUE; }
1159 bool isDebugLabel() const { return getOpcode() == TargetOpcode::DBG_LABEL; }
1160 bool isDebugRef() const { return getOpcode() == TargetOpcode::DBG_INSTR_REF; }
1161 bool isDebugInstr() const {
1162 return isDebugValue() || isDebugLabel() || isDebugRef();
1163 }
1164
1165 bool isDebugOffsetImm() const { return getDebugOffset().isImm(); }
1166
1167 /// A DBG_VALUE is indirect iff the location operand is a register and
1168 /// the offset operand is an immediate.
1169 bool isIndirectDebugValue() const {
1170 return isDebugValue() && getDebugOperand(0).isReg() && isDebugOffsetImm();
1171 }
1172
1173 /// A DBG_VALUE is an entry value iff its debug expression contains the
1174 /// DW_OP_LLVM_entry_value operation.
1175 bool isDebugEntryValue() const;
1176
1177 /// Return true if the instruction is a debug value which describes a part of
1178 /// a variable as unavailable.
1179 bool isUndefDebugValue() const {
1180 return isDebugValue() && getDebugOperand(0).isReg() &&
1181 !getDebugOperand(0).getReg().isValid();
1182 }
1183
1184 bool isPHI() const {
1185 return getOpcode() == TargetOpcode::PHI ||
1186 getOpcode() == TargetOpcode::G_PHI;
1187 }
1188 bool isKill() const { return getOpcode() == TargetOpcode::KILL; }
1189 bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; }
1190 bool isInlineAsm() const {
1191 return getOpcode() == TargetOpcode::INLINEASM ||
20
Assuming the condition is false
22
Returning zero, which participates in a condition later
1192 getOpcode() == TargetOpcode::INLINEASM_BR;
21
Assuming the condition is false
1193 }
1194
1195 /// FIXME: Seems like a layering violation that the AsmDialect, which is X86
1196 /// specific, be attached to a generic MachineInstr.
1197 bool isMSInlineAsm() const {
1198 return isInlineAsm() && getInlineAsmDialect() == InlineAsm::AD_Intel;
1199 }
1200
1201 bool isStackAligningInlineAsm() const;
1202 InlineAsm::AsmDialect getInlineAsmDialect() const;
1203
1204 bool isInsertSubreg() const {
1205 return getOpcode() == TargetOpcode::INSERT_SUBREG;
1206 }
1207
1208 bool isSubregToReg() const {
1209 return getOpcode() == TargetOpcode::SUBREG_TO_REG;
1210 }
1211
1212 bool isRegSequence() const {
1213 return getOpcode() == TargetOpcode::REG_SEQUENCE;
1214 }
1215
1216 bool isBundle() const {
1217 return getOpcode() == TargetOpcode::BUNDLE;
1218 }
1219
1220 bool isCopy() const {
1221 return getOpcode() == TargetOpcode::COPY;
1222 }
1223
1224 bool isFullCopy() const {
1225 return isCopy() && !getOperand(0).getSubReg() && !getOperand(1).getSubReg();
1226 }
1227
1228 bool isExtractSubreg() const {
1229 return getOpcode() == TargetOpcode::EXTRACT_SUBREG;
1230 }
1231
1232 /// Return true if the instruction behaves like a copy.
1233 /// This does not include native copy instructions.
1234 bool isCopyLike() const {
1235 return isCopy() || isSubregToReg();
1236 }
1237
1238 /// Return true is the instruction is an identity copy.
1239 bool isIdentityCopy() const {
1240 return isCopy() && getOperand(0).getReg() == getOperand(1).getReg() &&
1241 getOperand(0).getSubReg() == getOperand(1).getSubReg();
1242 }
1243
1244 /// Return true if this instruction doesn't produce any output in the form of
1245 /// executable instructions.
1246 bool isMetaInstruction() const {
1247 switch (getOpcode()) {
1248 default:
1249 return false;
1250 case TargetOpcode::IMPLICIT_DEF:
1251 case TargetOpcode::KILL:
1252 case TargetOpcode::CFI_INSTRUCTION:
1253 case TargetOpcode::EH_LABEL:
1254 case TargetOpcode::GC_LABEL:
1255 case TargetOpcode::DBG_VALUE:
1256 case TargetOpcode::DBG_INSTR_REF:
1257 case TargetOpcode::DBG_LABEL:
1258 case TargetOpcode::LIFETIME_START:
1259 case TargetOpcode::LIFETIME_END:
1260 return true;
1261 }
1262 }
1263
1264 /// Return true if this is a transient instruction that is either very likely
1265 /// to be eliminated during register allocation (such as copy-like
1266 /// instructions), or if this instruction doesn't have an execution-time cost.
1267 bool isTransient() const {
1268 switch (getOpcode()) {
1269 default:
1270 return isMetaInstruction();
1271 // Copy-like instructions are usually eliminated during register allocation.
1272 case TargetOpcode::PHI:
1273 case TargetOpcode::G_PHI:
1274 case TargetOpcode::COPY:
1275 case TargetOpcode::INSERT_SUBREG:
1276 case TargetOpcode::SUBREG_TO_REG:
1277 case TargetOpcode::REG_SEQUENCE:
1278 return true;
1279 }
1280 }
1281
1282 /// Return the number of instructions inside the MI bundle, excluding the
1283 /// bundle header.
1284 ///
1285 /// This is the number of instructions that MachineBasicBlock::iterator
1286 /// skips, 0 for unbundled instructions.
1287 unsigned getBundleSize() const;
1288
1289 /// Return true if the MachineInstr reads the specified register.
1290 /// If TargetRegisterInfo is passed, then it also checks if there
1291 /// is a read of a super-register.
1292 /// This does not count partial redefines of virtual registers as reads:
1293 /// %reg1024:6 = OP.
1294 bool readsRegister(Register Reg,
1295 const TargetRegisterInfo *TRI = nullptr) const {
1296 return findRegisterUseOperandIdx(Reg, false, TRI) != -1;
1297 }
1298
1299 /// Return true if the MachineInstr reads the specified virtual register.
1300 /// Take into account that a partial define is a
1301 /// read-modify-write operation.
1302 bool readsVirtualRegister(Register Reg) const {
1303 return readsWritesVirtualRegister(Reg).first;
1304 }
1305
1306 /// Return a pair of bools (reads, writes) indicating if this instruction
1307 /// reads or writes Reg. This also considers partial defines.
1308 /// If Ops is not null, all operand indices for Reg are added.
1309 std::pair<bool,bool> readsWritesVirtualRegister(Register Reg,
1310 SmallVectorImpl<unsigned> *Ops = nullptr) const;
1311
1312 /// Return true if the MachineInstr kills the specified register.
1313 /// If TargetRegisterInfo is passed, then it also checks if there is
1314 /// a kill of a super-register.
1315 bool killsRegister(Register Reg,
1316 const TargetRegisterInfo *TRI = nullptr) const {
1317 return findRegisterUseOperandIdx(Reg, true, TRI) != -1;
1318 }
1319
1320 /// Return true if the MachineInstr fully defines the specified register.
1321 /// If TargetRegisterInfo is passed, then it also checks
1322 /// if there is a def of a super-register.
1323 /// NOTE: It's ignoring subreg indices on virtual registers.
1324 bool definesRegister(Register Reg,
1325 const TargetRegisterInfo *TRI = nullptr) const {
1326 return findRegisterDefOperandIdx(Reg, false, false, TRI) != -1;
1327 }
1328
1329 /// Return true if the MachineInstr modifies (fully define or partially
1330 /// define) the specified register.
1331 /// NOTE: It's ignoring subreg indices on virtual registers.
1332 bool modifiesRegister(Register Reg, const TargetRegisterInfo *TRI) const {
1333 return findRegisterDefOperandIdx(Reg, false, true, TRI) != -1;
1334 }
1335
1336 /// Returns true if the register is dead in this machine instruction.
1337 /// If TargetRegisterInfo is passed, then it also checks
1338 /// if there is a dead def of a super-register.
1339 bool registerDefIsDead(Register Reg,
1340 const TargetRegisterInfo *TRI = nullptr) const {
1341 return findRegisterDefOperandIdx(Reg, true, false, TRI) != -1;
1342 }
1343
1344 /// Returns true if the MachineInstr has an implicit-use operand of exactly
1345 /// the given register (not considering sub/super-registers).
1346 bool hasRegisterImplicitUseOperand(Register Reg) const;
1347
1348 /// Returns the operand index that is a use of the specific register or -1
1349 /// if it is not found. It further tightens the search criteria to a use
1350 /// that kills the register if isKill is true.
1351 int findRegisterUseOperandIdx(Register Reg, bool isKill = false,
1352 const TargetRegisterInfo *TRI = nullptr) const;
1353
1354 /// Wrapper for findRegisterUseOperandIdx, it returns
1355 /// a pointer to the MachineOperand rather than an index.
1356 MachineOperand *findRegisterUseOperand(Register Reg, bool isKill = false,
1357 const TargetRegisterInfo *TRI = nullptr) {
1358 int Idx = findRegisterUseOperandIdx(Reg, isKill, TRI);
1359 return (Idx == -1) ? nullptr : &getOperand(Idx);
1360 }
1361
1362 const MachineOperand *findRegisterUseOperand(
1363 Register Reg, bool isKill = false,
1364 const TargetRegisterInfo *TRI = nullptr) const {
1365 return const_cast<MachineInstr *>(this)->
1366 findRegisterUseOperand(Reg, isKill, TRI);
1367 }
1368
1369 /// Returns the operand index that is a def of the specified register or
1370 /// -1 if it is not found. If isDead is true, defs that are not dead are
1371 /// skipped. If Overlap is true, then it also looks for defs that merely
1372 /// overlap the specified register. If TargetRegisterInfo is non-null,
1373 /// then it also checks if there is a def of a super-register.
1374 /// This may also return a register mask operand when Overlap is true.
1375 int findRegisterDefOperandIdx(Register Reg,
1376 bool isDead = false, bool Overlap = false,
1377 const TargetRegisterInfo *TRI = nullptr) const;
1378
1379 /// Wrapper for findRegisterDefOperandIdx, it returns
1380 /// a pointer to the MachineOperand rather than an index.
1381 MachineOperand *
1382 findRegisterDefOperand(Register Reg, bool isDead = false,
1383 bool Overlap = false,
1384 const TargetRegisterInfo *TRI = nullptr) {
1385 int Idx = findRegisterDefOperandIdx(Reg, isDead, Overlap, TRI);
1386 return (Idx == -1) ? nullptr : &getOperand(Idx);
1387 }
1388
1389 const MachineOperand *
1390 findRegisterDefOperand(Register Reg, bool isDead = false,
1391 bool Overlap = false,
1392 const TargetRegisterInfo *TRI = nullptr) const {
1393 return const_cast<MachineInstr *>(this)->findRegisterDefOperand(
1394 Reg, isDead, Overlap, TRI);
1395 }
1396
1397 /// Find the index of the first operand in the
1398 /// operand list that is used to represent the predicate. It returns -1 if
1399 /// none is found.
1400 int findFirstPredOperandIdx() const;
1401
1402 /// Find the index of the flag word operand that
1403 /// corresponds to operand OpIdx on an inline asm instruction. Returns -1 if
1404 /// getOperand(OpIdx) does not belong to an inline asm operand group.
1405 ///
1406 /// If GroupNo is not NULL, it will receive the number of the operand group
1407 /// containing OpIdx.
1408 ///
1409 /// The flag operand is an immediate that can be decoded with methods like
1410 /// InlineAsm::hasRegClassConstraint().
1411 int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo = nullptr) const;
1412
1413 /// Compute the static register class constraint for operand OpIdx.
1414 /// For normal instructions, this is derived from the MCInstrDesc.
1415 /// For inline assembly it is derived from the flag words.
1416 ///
1417 /// Returns NULL if the static register class constraint cannot be
1418 /// determined.
1419 const TargetRegisterClass*
1420 getRegClassConstraint(unsigned OpIdx,
1421 const TargetInstrInfo *TII,
1422 const TargetRegisterInfo *TRI) const;
1423
1424 /// Applies the constraints (def/use) implied by this MI on \p Reg to
1425 /// the given \p CurRC.
1426 /// If \p ExploreBundle is set and MI is part of a bundle, all the
1427 /// instructions inside the bundle will be taken into account. In other words,
1428 /// this method accumulates all the constraints of the operand of this MI and
1429 /// the related bundle if MI is a bundle or inside a bundle.
1430 ///
1431 /// Returns the register class that satisfies both \p CurRC and the
1432 /// constraints set by MI. Returns NULL if such a register class does not
1433 /// exist.
1434 ///
1435 /// \pre CurRC must not be NULL.
1436 const TargetRegisterClass *getRegClassConstraintEffectForVReg(
1437 Register Reg, const TargetRegisterClass *CurRC,
1438 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI,
1439 bool ExploreBundle = false) const;
1440
1441 /// Applies the constraints (def/use) implied by the \p OpIdx operand
1442 /// to the given \p CurRC.
1443 ///
1444 /// Returns the register class that satisfies both \p CurRC and the
1445 /// constraints set by \p OpIdx MI. Returns NULL if such a register class
1446 /// does not exist.
1447 ///
1448 /// \pre CurRC must not be NULL.
1449 /// \pre The operand at \p OpIdx must be a register.
1450 const TargetRegisterClass *
1451 getRegClassConstraintEffect(unsigned OpIdx, const TargetRegisterClass *CurRC,
1452 const TargetInstrInfo *TII,
1453 const TargetRegisterInfo *TRI) const;
1454
1455 /// Add a tie between the register operands at DefIdx and UseIdx.
1456 /// The tie will cause the register allocator to ensure that the two
1457 /// operands are assigned the same physical register.
1458 ///
1459 /// Tied operands are managed automatically for explicit operands in the
1460 /// MCInstrDesc. This method is for exceptional cases like inline asm.
1461 void tieOperands(unsigned DefIdx, unsigned UseIdx);
1462
1463 /// Given the index of a tied register operand, find the
1464 /// operand it is tied to. Defs are tied to uses and vice versa. Returns the
1465 /// index of the tied operand which must exist.
1466 unsigned findTiedOperandIdx(unsigned OpIdx) const;
1467
1468 /// Given the index of a register def operand,
1469 /// check if the register def is tied to a source operand, due to either
1470 /// two-address elimination or inline assembly constraints. Returns the
1471 /// first tied use operand index by reference if UseOpIdx is not null.
1472 bool isRegTiedToUseOperand(unsigned DefOpIdx,
1473 unsigned *UseOpIdx = nullptr) const {
1474 const MachineOperand &MO = getOperand(DefOpIdx);
1475 if (!MO.isReg() || !MO.isDef() || !MO.isTied())
1476 return false;
1477 if (UseOpIdx)
1478 *UseOpIdx = findTiedOperandIdx(DefOpIdx);
1479 return true;
1480 }
1481
1482 /// Return true if the use operand of the specified index is tied to a def
1483 /// operand. It also returns the def operand index by reference if DefOpIdx
1484 /// is not null.
1485 bool isRegTiedToDefOperand(unsigned UseOpIdx,
1486 unsigned *DefOpIdx = nullptr) const {
1487 const MachineOperand &MO = getOperand(UseOpIdx);
1488 if (!MO.isReg() || !MO.isUse() || !MO.isTied())
1489 return false;
1490 if (DefOpIdx)
1491 *DefOpIdx = findTiedOperandIdx(UseOpIdx);
1492 return true;
1493 }
1494
1495 /// Clears kill flags on all operands.
1496 void clearKillInfo();
1497
1498 /// Replace all occurrences of FromReg with ToReg:SubIdx,
1499 /// properly composing subreg indices where necessary.
1500 void substituteRegister(Register FromReg, Register ToReg, unsigned SubIdx,
1501 const TargetRegisterInfo &RegInfo);
1502
1503 /// We have determined MI kills a register. Look for the
1504 /// operand that uses it and mark it as IsKill. If AddIfNotFound is true,
1505 /// add a implicit operand if it's not found. Returns true if the operand
1506 /// exists / is added.
1507 bool addRegisterKilled(Register IncomingReg,
1508 const TargetRegisterInfo *RegInfo,
1509 bool AddIfNotFound = false);
1510
1511 /// Clear all kill flags affecting Reg. If RegInfo is provided, this includes
1512 /// all aliasing registers.
1513 void clearRegisterKills(Register Reg, const TargetRegisterInfo *RegInfo);
1514
1515 /// We have determined MI defined a register without a use.
1516 /// Look for the operand that defines it and mark it as IsDead. If
1517 /// AddIfNotFound is true, add a implicit operand if it's not found. Returns
1518 /// true if the operand exists / is added.
1519 bool addRegisterDead(Register Reg, const TargetRegisterInfo *RegInfo,
1520 bool AddIfNotFound = false);
1521
1522 /// Clear all dead flags on operands defining register @p Reg.
1523 void clearRegisterDeads(Register Reg);
1524
1525 /// Mark all subregister defs of register @p Reg with the undef flag.
1526 /// This function is used when we determined to have a subregister def in an
1527 /// otherwise undefined super register.
1528 void setRegisterDefReadUndef(Register Reg, bool IsUndef = true);
1529
1530 /// We have determined MI defines a register. Make sure there is an operand
1531 /// defining Reg.
1532 void addRegisterDefined(Register Reg,
1533 const TargetRegisterInfo *RegInfo = nullptr);
1534
1535 /// Mark every physreg used by this instruction as
1536 /// dead except those in the UsedRegs list.
1537 ///
1538 /// On instructions with register mask operands, also add implicit-def
1539 /// operands for all registers in UsedRegs.
1540 void setPhysRegsDeadExcept(ArrayRef<Register> UsedRegs,
1541 const TargetRegisterInfo &TRI);
1542
1543 /// Return true if it is safe to move this instruction. If
1544 /// SawStore is set to true, it means that there is a store (or call) between
1545 /// the instruction's location and its intended destination.
1546 bool isSafeToMove(AAResults *AA, bool &SawStore) const;
1547
1548 /// Returns true if this instruction's memory access aliases the memory
1549 /// access of Other.
1550 //
1551 /// Assumes any physical registers used to compute addresses
1552 /// have the same value for both instructions. Returns false if neither
1553 /// instruction writes to memory.
1554 ///
1555 /// @param AA Optional alias analysis, used to compare memory operands.
1556 /// @param Other MachineInstr to check aliasing against.
1557 /// @param UseTBAA Whether to pass TBAA information to alias analysis.
1558 bool mayAlias(AAResults *AA, const MachineInstr &Other, bool UseTBAA) const;
1559
1560 /// Return true if this instruction may have an ordered
1561 /// or volatile memory reference, or if the information describing the memory
1562 /// reference is not available. Return false if it is known to have no
1563 /// ordered or volatile memory references.
1564 bool hasOrderedMemoryRef() const;
1565
1566 /// Return true if this load instruction never traps and points to a memory
1567 /// location whose value doesn't change during the execution of this function.
1568 ///
1569 /// Examples include loading a value from the constant pool or from the
1570 /// argument area of a function (if it does not change). If the instruction
1571 /// does multiple loads, this returns true only if all of the loads are
1572 /// dereferenceable and invariant.
1573 bool isDereferenceableInvariantLoad(AAResults *AA) const;
1574
1575 /// If the specified instruction is a PHI that always merges together the
1576 /// same virtual register, return the register, otherwise return 0.
1577 unsigned isConstantValuePHI() const;
1578
1579 /// Return true if this instruction has side effects that are not modeled
1580 /// by mayLoad / mayStore, etc.
1581 /// For all instructions, the property is encoded in MCInstrDesc::Flags
1582 /// (see MCInstrDesc::hasUnmodeledSideEffects(). The only exception is
1583 /// INLINEASM instruction, in which case the side effect property is encoded
1584 /// in one of its operands (see InlineAsm::Extra_HasSideEffect).
1585 ///
1586 bool hasUnmodeledSideEffects() const;
1587
1588 /// Returns true if it is illegal to fold a load across this instruction.
1589 bool isLoadFoldBarrier() const;
1590
1591 /// Return true if all the defs of this instruction are dead.
1592 bool allDefsAreDead() const;
1593
1594 /// Return a valid size if the instruction is a spill instruction.
1595 Optional<unsigned> getSpillSize(const TargetInstrInfo *TII) const;
1596
1597 /// Return a valid size if the instruction is a folded spill instruction.
1598 Optional<unsigned> getFoldedSpillSize(const TargetInstrInfo *TII) const;
1599
1600 /// Return a valid size if the instruction is a restore instruction.
1601 Optional<unsigned> getRestoreSize(const TargetInstrInfo *TII) const;
1602
1603 /// Return a valid size if the instruction is a folded restore instruction.
1604 Optional<unsigned>
1605 getFoldedRestoreSize(const TargetInstrInfo *TII) const;
1606
1607 /// Copy implicit register operands from specified
1608 /// instruction to this instruction.
1609 void copyImplicitOps(MachineFunction &MF, const MachineInstr &MI);
1610
1611 /// Debugging support
1612 /// @{
1613 /// Determine the generic type to be printed (if needed) on uses and defs.
1614 LLT getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes,
1615 const MachineRegisterInfo &MRI) const;
1616
1617 /// Return true when an instruction has tied register that can't be determined
1618 /// by the instruction's descriptor. This is useful for MIR printing, to
1619 /// determine whether we need to print the ties or not.
1620 bool hasComplexRegisterTies() const;
1621
1622 /// Print this MI to \p OS.
1623 /// Don't print information that can be inferred from other instructions if
1624 /// \p IsStandalone is false. It is usually true when only a fragment of the
1625 /// function is printed.
1626 /// Only print the defs and the opcode if \p SkipOpers is true.
1627 /// Otherwise, also print operands if \p SkipDebugLoc is true.
1628 /// Otherwise, also print the debug loc, with a terminating newline.
1629 /// \p TII is used to print the opcode name. If it's not present, but the
1630 /// MI is in a function, the opcode will be printed using the function's TII.
1631 void print(raw_ostream &OS, bool IsStandalone = true, bool SkipOpers = false,
1632 bool SkipDebugLoc = false, bool AddNewLine = true,
1633 const TargetInstrInfo *TII = nullptr) const;
1634 void print(raw_ostream &OS, ModuleSlotTracker &MST, bool IsStandalone = true,
1635 bool SkipOpers = false, bool SkipDebugLoc = false,
1636 bool AddNewLine = true,
1637 const TargetInstrInfo *TII = nullptr) const;
1638 void dump() const;
1639 /// Print on dbgs() the current instruction and the instructions defining its
1640 /// operands and so on until we reach \p MaxDepth.
1641 void dumpr(const MachineRegisterInfo &MRI,
1642 unsigned MaxDepth = UINT_MAX(2147483647 *2U +1U)) const;
1643 /// @}
1644
1645 //===--------------------------------------------------------------------===//
1646 // Accessors used to build up machine instructions.
1647
1648 /// Add the specified operand to the instruction. If it is an implicit
1649 /// operand, it is added to the end of the operand list. If it is an
1650 /// explicit operand it is added at the end of the explicit operand list
1651 /// (before the first implicit operand).
1652 ///
1653 /// MF must be the machine function that was used to allocate this
1654 /// instruction.
1655 ///
1656 /// MachineInstrBuilder provides a more convenient interface for creating
1657 /// instructions and adding operands.
1658 void addOperand(MachineFunction &MF, const MachineOperand &Op);
1659
1660 /// Add an operand without providing an MF reference. This only works for
1661 /// instructions that are inserted in a basic block.
1662 ///
1663 /// MachineInstrBuilder and the two-argument addOperand(MF, MO) should be
1664 /// preferred.
1665 void addOperand(const MachineOperand &Op);
1666
1667 /// Replace the instruction descriptor (thus opcode) of
1668 /// the current instruction with a new one.
1669 void setDesc(const MCInstrDesc &tid) { MCID = &tid; }
1670
1671 /// Replace current source information with new such.
1672 /// Avoid using this, the constructor argument is preferable.
1673 void setDebugLoc(DebugLoc dl) {
1674 debugLoc = std::move(dl);
1675 assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor")((debugLoc.hasTrivialDestructor() && "Expected trivial destructor"
) ? static_cast<void> (0) : __assert_fail ("debugLoc.hasTrivialDestructor() && \"Expected trivial destructor\""
, "/build/llvm-toolchain-snapshot-12~++20200927111121+5811d723998/llvm/include/llvm/CodeGen/MachineInstr.h"
, 1675, __PRETTY_FUNCTION__))
;
1676 }
1677
1678 /// Erase an operand from an instruction, leaving it with one
1679 /// fewer operand than it started with.
1680 void RemoveOperand(unsigned OpNo);
1681
1682 /// Clear this MachineInstr's memory reference descriptor list. This resets
1683 /// the memrefs to their most conservative state. This should be used only
1684 /// as a last resort since it greatly pessimizes our knowledge of the memory
1685 /// access performed by the instruction.
1686 void dropMemRefs(MachineFunction &MF);
1687
1688 /// Assign this MachineInstr's memory reference descriptor list.
1689 ///
1690 /// Unlike other methods, this *will* allocate them into a new array
1691 /// associated with the provided `MachineFunction`.
1692 void setMemRefs(MachineFunction &MF, ArrayRef<MachineMemOperand *> MemRefs);
1693
1694 /// Add a MachineMemOperand to the machine instruction.
1695 /// This function should be used only occasionally. The setMemRefs function
1696 /// is the primary method for setting up a MachineInstr's MemRefs list.
1697 void addMemOperand(MachineFunction &MF, MachineMemOperand *MO);
1698
1699 /// Clone another MachineInstr's memory reference descriptor list and replace
1700 /// ours with it.
1701 ///
1702 /// Note that `*this` may be the incoming MI!
1703 ///
1704 /// Prefer this API whenever possible as it can avoid allocations in common
1705 /// cases.
1706 void cloneMemRefs(MachineFunction &MF, const MachineInstr &MI);
1707
1708 /// Clone the merge of multiple MachineInstrs' memory reference descriptors
1709 /// list and replace ours with it.
1710 ///
1711 /// Note that `*this` may be one of the incoming MIs!
1712 ///
1713 /// Prefer this API whenever possible as it can avoid allocations in common
1714 /// cases.
1715 void cloneMergedMemRefs(MachineFunction &MF,
1716 ArrayRef<const MachineInstr *> MIs);
1717
1718 /// Set a symbol that will be emitted just prior to the instruction itself.
1719 ///
1720 /// Setting this to a null pointer will remove any such symbol.
1721 ///
1722 /// FIXME: This is not fully implemented yet.
1723 void setPreInstrSymbol(MachineFunction &MF, MCSymbol *Symbol);
1724
1725 /// Set a symbol that will be emitted just after the instruction itself.
1726 ///
1727 /// Setting this to a null pointer will remove any such symbol.
1728 ///
1729 /// FIXME: This is not fully implemented yet.
1730 void setPostInstrSymbol(MachineFunction &MF, MCSymbol *Symbol);
1731
1732 /// Clone another MachineInstr's pre- and post- instruction symbols and
1733 /// replace ours with it.
1734 void cloneInstrSymbols(MachineFunction &MF, const MachineInstr &MI);
1735
1736 /// Set a marker on instructions that denotes where we should create and emit
1737 /// heap alloc site labels. This waits until after instruction selection and
1738 /// optimizations to create the label, so it should still work if the
1739 /// instruction is removed or duplicated.
1740 void setHeapAllocMarker(MachineFunction &MF, MDNode *MD);
1741
1742 /// Return the MIFlags which represent both MachineInstrs. This
1743 /// should be used when merging two MachineInstrs into one. This routine does
1744 /// not modify the MIFlags of this MachineInstr.
1745 uint16_t mergeFlagsWith(const MachineInstr& Other) const;
1746
1747 static uint16_t copyFlagsFromInstruction(const Instruction &I);
1748
1749 /// Copy all flags to MachineInst MIFlags
1750 void copyIRFlags(const Instruction &I);
1751
1752 /// Break any tie involving OpIdx.
1753 void untieRegOperand(unsigned OpIdx) {
1754 MachineOperand &MO = getOperand(OpIdx);
1755 if (MO.isReg() && MO.isTied()) {
1756 getOperand(findTiedOperandIdx(OpIdx)).TiedTo = 0;
1757 MO.TiedTo = 0;
1758 }
1759 }
1760
1761 /// Add all implicit def and use operands to this instruction.
1762 void addImplicitDefUseOperands(MachineFunction &MF);
1763
1764 /// Scan instructions immediately following MI and collect any matching
1765 /// DBG_VALUEs.
1766 void collectDebugValues(SmallVectorImpl<MachineInstr *> &DbgValues);
1767
1768 /// Find all DBG_VALUEs that point to the register def in this instruction
1769 /// and point them to \p Reg instead.
1770 void changeDebugValuesDefReg(Register Reg);
1771
1772 /// Returns the Intrinsic::ID for this instruction.
1773 /// \pre Must have an intrinsic ID operand.
1774 unsigned getIntrinsicID() const {
1775 return getOperand(getNumExplicitDefs()).getIntrinsicID();
1776 }
1777
1778 /// Sets all register debug operands in this debug value instruction to be
1779 /// undef.
1780 void setDebugValueUndef() {
1781 assert(isDebugValue() && "Must be a debug value instruction.")((isDebugValue() && "Must be a debug value instruction."
) ? static_cast<void> (0) : __assert_fail ("isDebugValue() && \"Must be a debug value instruction.\""
, "/build/llvm-toolchain-snapshot-12~++20200927111121+5811d723998/llvm/include/llvm/CodeGen/MachineInstr.h"
, 1781, __PRETTY_FUNCTION__))
;
1782 for (MachineOperand &MO : debug_operands()) {
1783 if (MO.isReg())
1784 MO.setReg(0);
1785 }
1786 }
1787
1788private:
1789 /// If this instruction is embedded into a MachineFunction, return the
1790 /// MachineRegisterInfo object for the current function, otherwise
1791 /// return null.
1792 MachineRegisterInfo *getRegInfo();
1793
1794 /// Unlink all of the register operands in this instruction from their
1795 /// respective use lists. This requires that the operands already be on their
1796 /// use lists.
1797 void RemoveRegOperandsFromUseLists(MachineRegisterInfo&);
1798
1799 /// Add all of the register operands in this instruction from their
1800 /// respective use lists. This requires that the operands not be on their
1801 /// use lists yet.
1802 void AddRegOperandsToUseLists(MachineRegisterInfo&);
1803
1804 /// Slow path for hasProperty when we're dealing with a bundle.
1805 bool hasPropertyInBundle(uint64_t Mask, QueryType Type) const;
1806
1807 /// Implements the logic of getRegClassConstraintEffectForVReg for the
1808 /// this MI and the given operand index \p OpIdx.
1809 /// If the related operand does not constrained Reg, this returns CurRC.
1810 const TargetRegisterClass *getRegClassConstraintEffectForVRegImpl(
1811 unsigned OpIdx, Register Reg, const TargetRegisterClass *CurRC,
1812 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const;
1813
1814 /// Stores extra instruction information inline or allocates as ExtraInfo
1815 /// based on the number of pointers.
1816 void setExtraInfo(MachineFunction &MF, ArrayRef<MachineMemOperand *> MMOs,
1817 MCSymbol *PreInstrSymbol, MCSymbol *PostInstrSymbol,
1818 MDNode *HeapAllocMarker);
1819};
1820
1821/// Special DenseMapInfo traits to compare MachineInstr* by *value* of the
1822/// instruction rather than by pointer value.
1823/// The hashing and equality testing functions ignore definitions so this is
1824/// useful for CSE, etc.
1825struct MachineInstrExpressionTrait : DenseMapInfo<MachineInstr*> {
1826 static inline MachineInstr *getEmptyKey() {
1827 return nullptr;
1828 }
1829
1830 static inline MachineInstr *getTombstoneKey() {
1831 return reinterpret_cast<MachineInstr*>(-1);
1832 }
1833
1834 static unsigned getHashValue(const MachineInstr* const &MI);
1835
1836 static bool isEqual(const MachineInstr* const &LHS,
1837 const MachineInstr* const &RHS) {
1838 if (RHS == getEmptyKey() || RHS == getTombstoneKey() ||
1839 LHS == getEmptyKey() || LHS == getTombstoneKey())
1840 return LHS == RHS;
1841 return LHS->isIdenticalTo(*RHS, MachineInstr::IgnoreVRegDefs);
1842 }
1843};
1844
1845//===----------------------------------------------------------------------===//
1846// Debugging Support
1847
1848inline raw_ostream& operator<<(raw_ostream &OS, const MachineInstr &MI) {
1849 MI.print(OS);
1850 return OS;
1851}
1852
1853} // end namespace llvm
1854
1855#endif // LLVM_CODEGEN_MACHINEINSTR_H