Bug Summary

File:lib/Target/AMDGPU/SIFrameLowering.cpp
Warning:line 204, column 9
Value stored to 'HandledScratchWaveOffsetReg' is never read

Annotated Source Code

1//===----------------------- SIFrameLowering.cpp --------------------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//==-----------------------------------------------------------------------===//
9
10#include "SIFrameLowering.h"
11#include "SIInstrInfo.h"
12#include "SIMachineFunctionInfo.h"
13#include "SIRegisterInfo.h"
14#include "AMDGPUSubtarget.h"
15
16#include "llvm/CodeGen/MachineFrameInfo.h"
17#include "llvm/CodeGen/MachineFunction.h"
18#include "llvm/CodeGen/MachineInstrBuilder.h"
19#include "llvm/CodeGen/RegisterScavenging.h"
20
21using namespace llvm;
22
23
24static ArrayRef<MCPhysReg> getAllSGPR128(const SISubtarget &ST,
25 const MachineFunction &MF) {
26 return makeArrayRef(AMDGPU::SGPR_128RegClass.begin(),
27 ST.getMaxNumSGPRs(MF) / 4);
28}
29
30static ArrayRef<MCPhysReg> getAllSGPRs(const SISubtarget &ST,
31 const MachineFunction &MF) {
32 return makeArrayRef(AMDGPU::SGPR_32RegClass.begin(),
33 ST.getMaxNumSGPRs(MF));
34}
35
36void SIFrameLowering::emitFlatScratchInit(const SISubtarget &ST,
37 MachineFunction &MF,
38 MachineBasicBlock &MBB) const {
39 const SIInstrInfo *TII = ST.getInstrInfo();
40 const SIRegisterInfo* TRI = &TII->getRegisterInfo();
41
42 // We don't need this if we only have spills since there is no user facing
43 // scratch.
44
45 // TODO: If we know we don't have flat instructions earlier, we can omit
46 // this from the input registers.
47 //
48 // TODO: We only need to know if we access scratch space through a flat
49 // pointer. Because we only detect if flat instructions are used at all,
50 // this will be used more often than necessary on VI.
51
52 // Debug location must be unknown since the first debug location is used to
53 // determine the end of the prologue.
54 DebugLoc DL;
55 MachineBasicBlock::iterator I = MBB.begin();
56
57 unsigned FlatScratchInitReg
58 = TRI->getPreloadedValue(MF, SIRegisterInfo::FLAT_SCRATCH_INIT);
59
60 MachineRegisterInfo &MRI = MF.getRegInfo();
61 MRI.addLiveIn(FlatScratchInitReg);
62 MBB.addLiveIn(FlatScratchInitReg);
63
64 unsigned FlatScrInitLo = TRI->getSubReg(FlatScratchInitReg, AMDGPU::sub0);
65 unsigned FlatScrInitHi = TRI->getSubReg(FlatScratchInitReg, AMDGPU::sub1);
66
67 const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
68 unsigned ScratchWaveOffsetReg = MFI->getScratchWaveOffsetReg();
69
70 // Do a 64-bit pointer add.
71 if (ST.flatScratchIsPointer()) {
72 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_ADD_U32), AMDGPU::FLAT_SCR_LO)
73 .addReg(FlatScrInitLo)
74 .addReg(ScratchWaveOffsetReg);
75 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_ADDC_U32), AMDGPU::FLAT_SCR_HI)
76 .addReg(FlatScrInitHi)
77 .addImm(0);
78
79 return;
80 }
81
82 // Copy the size in bytes.
83 BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), AMDGPU::FLAT_SCR_LO)
84 .addReg(FlatScrInitHi, RegState::Kill);
85
86 // Add wave offset in bytes to private base offset.
87 // See comment in AMDKernelCodeT.h for enable_sgpr_flat_scratch_init.
88 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_ADD_U32), FlatScrInitLo)
89 .addReg(FlatScrInitLo)
90 .addReg(ScratchWaveOffsetReg);
91
92 // Convert offset to 256-byte units.
93 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_LSHR_B32), AMDGPU::FLAT_SCR_HI)
94 .addReg(FlatScrInitLo, RegState::Kill)
95 .addImm(8);
96}
97
98unsigned SIFrameLowering::getReservedPrivateSegmentBufferReg(
99 const SISubtarget &ST,
100 const SIInstrInfo *TII,
101 const SIRegisterInfo *TRI,
102 SIMachineFunctionInfo *MFI,
103 MachineFunction &MF) const {
104 MachineRegisterInfo &MRI = MF.getRegInfo();
105
106 // We need to insert initialization of the scratch resource descriptor.
107 unsigned ScratchRsrcReg = MFI->getScratchRSrcReg();
108 if (ScratchRsrcReg == AMDGPU::NoRegister ||
109 !MRI.isPhysRegUsed(ScratchRsrcReg))
110 return AMDGPU::NoRegister;
111
112 if (ST.hasSGPRInitBug() ||
113 ScratchRsrcReg != TRI->reservedPrivateSegmentBufferReg(MF))
114 return ScratchRsrcReg;
115
116 // We reserved the last registers for this. Shift it down to the end of those
117 // which were actually used.
118 //
119 // FIXME: It might be safer to use a pseudoregister before replacement.
120
121 // FIXME: We should be able to eliminate unused input registers. We only
122 // cannot do this for the resources required for scratch access. For now we
123 // skip over user SGPRs and may leave unused holes.
124
125 // We find the resource first because it has an alignment requirement.
126
127 unsigned NumPreloaded = (MFI->getNumPreloadedSGPRs() + 3) / 4;
128 ArrayRef<MCPhysReg> AllSGPR128s = getAllSGPR128(ST, MF);
129 AllSGPR128s = AllSGPR128s.slice(std::min(static_cast<unsigned>(AllSGPR128s.size()), NumPreloaded));
130
131 // Skip the last N reserved elements because they should have already been
132 // reserved for VCC etc.
133 for (MCPhysReg Reg : AllSGPR128s) {
134 // Pick the first unallocated one. Make sure we don't clobber the other
135 // reserved input we needed.
136 if (!MRI.isPhysRegUsed(Reg) && MRI.isAllocatable(Reg)) {
137 MRI.replaceRegWith(ScratchRsrcReg, Reg);
138 MFI->setScratchRSrcReg(Reg);
139 return Reg;
140 }
141 }
142
143 return ScratchRsrcReg;
144}
145
146// Shift down registers reserved for the scratch wave offset and stack pointer
147// SGPRs.
148std::pair<unsigned, unsigned>
149SIFrameLowering::getReservedPrivateSegmentWaveByteOffsetReg(
150 const SISubtarget &ST,
151 const SIInstrInfo *TII,
152 const SIRegisterInfo *TRI,
153 SIMachineFunctionInfo *MFI,
154 MachineFunction &MF) const {
155 MachineRegisterInfo &MRI = MF.getRegInfo();
156 unsigned ScratchWaveOffsetReg = MFI->getScratchWaveOffsetReg();
157
158 // No replacement necessary.
159 if (ScratchWaveOffsetReg == AMDGPU::NoRegister ||
160 !MRI.isPhysRegUsed(ScratchWaveOffsetReg)) {
161 assert(MFI->getStackPtrOffsetReg() == AMDGPU::NoRegister)((MFI->getStackPtrOffsetReg() == AMDGPU::NoRegister) ? static_cast
<void> (0) : __assert_fail ("MFI->getStackPtrOffsetReg() == AMDGPU::NoRegister"
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/Target/AMDGPU/SIFrameLowering.cpp"
, 161, __PRETTY_FUNCTION__))
;
162 return std::make_pair(AMDGPU::NoRegister, AMDGPU::NoRegister);
163 }
164
165 unsigned SPReg = MFI->getStackPtrOffsetReg();
166 if (ST.hasSGPRInitBug())
167 return std::make_pair(ScratchWaveOffsetReg, SPReg);
168
169 unsigned NumPreloaded = MFI->getNumPreloadedSGPRs();
170
171 ArrayRef<MCPhysReg> AllSGPRs = getAllSGPRs(ST, MF);
172 if (NumPreloaded > AllSGPRs.size())
173 return std::make_pair(ScratchWaveOffsetReg, SPReg);
174
175 AllSGPRs = AllSGPRs.slice(NumPreloaded);
176
177 // We need to drop register from the end of the list that we cannot use
178 // for the scratch wave offset.
179 // + 2 s102 and s103 do not exist on VI.
180 // + 2 for vcc
181 // + 2 for xnack_mask
182 // + 2 for flat_scratch
183 // + 4 for registers reserved for scratch resource register
184 // + 1 for register reserved for scratch wave offset. (By exluding this
185 // register from the list to consider, it means that when this
186 // register is being used for the scratch wave offset and there
187 // are no other free SGPRs, then the value will stay in this register.
188 // + 1 if stack pointer is used.
189 // ----
190 // 13 (+1)
191 unsigned ReservedRegCount = 13;
192
193 if (AllSGPRs.size() < ReservedRegCount)
194 return std::make_pair(ScratchWaveOffsetReg, SPReg);
195
196 bool HandledScratchWaveOffsetReg =
197 ScratchWaveOffsetReg != TRI->reservedPrivateSegmentWaveByteOffsetReg(MF);
198
199 for (MCPhysReg Reg : AllSGPRs.drop_back(ReservedRegCount)) {
200 // Pick the first unallocated SGPR. Be careful not to pick an alias of the
201 // scratch descriptor, since we haven’t added its uses yet.
202 if (!MRI.isPhysRegUsed(Reg) && MRI.isAllocatable(Reg)) {
203 if (!HandledScratchWaveOffsetReg) {
204 HandledScratchWaveOffsetReg = true;
Value stored to 'HandledScratchWaveOffsetReg' is never read
205
206 MRI.replaceRegWith(ScratchWaveOffsetReg, Reg);
207 MFI->setScratchWaveOffsetReg(Reg);
208 ScratchWaveOffsetReg = Reg;
209 break;
210 }
211 }
212 }
213
214 return std::make_pair(ScratchWaveOffsetReg, SPReg);
215}
216
217void SIFrameLowering::emitEntryFunctionPrologue(MachineFunction &MF,
218 MachineBasicBlock &MBB) const {
219 // Emit debugger prologue if "amdgpu-debugger-emit-prologue" attribute was
220 // specified.
221 const SISubtarget &ST = MF.getSubtarget<SISubtarget>();
222 auto AMDGPUASI = ST.getAMDGPUAS();
223 if (ST.debuggerEmitPrologue())
224 emitDebuggerPrologue(MF, MBB);
225
226 assert(&MF.front() == &MBB && "Shrink-wrapping not yet supported")((&MF.front() == &MBB && "Shrink-wrapping not yet supported"
) ? static_cast<void> (0) : __assert_fail ("&MF.front() == &MBB && \"Shrink-wrapping not yet supported\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/Target/AMDGPU/SIFrameLowering.cpp"
, 226, __PRETTY_FUNCTION__))
;
227
228 SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
229
230 // If we only have SGPR spills, we won't actually be using scratch memory
231 // since these spill to VGPRs.
232 //
233 // FIXME: We should be cleaning up these unused SGPR spill frame indices
234 // somewhere.
235
236 const SIInstrInfo *TII = ST.getInstrInfo();
237 const SIRegisterInfo *TRI = &TII->getRegisterInfo();
238 MachineRegisterInfo &MRI = MF.getRegInfo();
239
240 // We need to do the replacement of the private segment buffer and wave offset
241 // register even if there are no stack objects. There could be stores to undef
242 // or a constant without an associated object.
243
244 // FIXME: We still have implicit uses on SGPR spill instructions in case they
245 // need to spill to vector memory. It's likely that will not happen, but at
246 // this point it appears we need the setup. This part of the prolog should be
247 // emitted after frame indices are eliminated.
248
249 if (MF.getFrameInfo().hasStackObjects() && MFI->hasFlatScratchInit())
250 emitFlatScratchInit(ST, MF, MBB);
251
252 unsigned SPReg = MFI->getStackPtrOffsetReg();
253 if (SPReg != AMDGPU::NoRegister) {
254 DebugLoc DL;
255 int64_t StackSize = MF.getFrameInfo().getStackSize();
256
257 if (StackSize == 0) {
258 BuildMI(MBB, MBB.begin(), DL, TII->get(AMDGPU::COPY), SPReg)
259 .addReg(MFI->getScratchWaveOffsetReg());
260 } else {
261 BuildMI(MBB, MBB.begin(), DL, TII->get(AMDGPU::S_ADD_U32), SPReg)
262 .addReg(MFI->getScratchWaveOffsetReg())
263 .addImm(StackSize * ST.getWavefrontSize());
264 }
265 }
266
267 unsigned ScratchRsrcReg
268 = getReservedPrivateSegmentBufferReg(ST, TII, TRI, MFI, MF);
269
270 unsigned ScratchWaveOffsetReg;
271 std::tie(ScratchWaveOffsetReg, SPReg)
272 = getReservedPrivateSegmentWaveByteOffsetReg(ST, TII, TRI, MFI, MF);
273
274 // It's possible to have uses of only ScratchWaveOffsetReg without
275 // ScratchRsrcReg if it's only used for the initialization of flat_scratch,
276 // but the inverse is not true.
277 if (ScratchWaveOffsetReg == AMDGPU::NoRegister) {
278 assert(ScratchRsrcReg == AMDGPU::NoRegister)((ScratchRsrcReg == AMDGPU::NoRegister) ? static_cast<void
> (0) : __assert_fail ("ScratchRsrcReg == AMDGPU::NoRegister"
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/Target/AMDGPU/SIFrameLowering.cpp"
, 278, __PRETTY_FUNCTION__))
;
279 return;
280 }
281
282 // We need to insert initialization of the scratch resource descriptor.
283 unsigned PreloadedScratchWaveOffsetReg = TRI->getPreloadedValue(
284 MF, SIRegisterInfo::PRIVATE_SEGMENT_WAVE_BYTE_OFFSET);
285
286 unsigned PreloadedPrivateBufferReg = AMDGPU::NoRegister;
287 if (ST.isAmdCodeObjectV2(MF) || ST.isMesaGfxShader(MF)) {
288 PreloadedPrivateBufferReg = TRI->getPreloadedValue(
289 MF, SIRegisterInfo::PRIVATE_SEGMENT_BUFFER);
290 }
291
292 bool OffsetRegUsed = MRI.isPhysRegUsed(ScratchWaveOffsetReg);
293 bool ResourceRegUsed = ScratchRsrcReg != AMDGPU::NoRegister &&
294 MRI.isPhysRegUsed(ScratchRsrcReg);
295
296 // We added live-ins during argument lowering, but since they were not used
297 // they were deleted. We're adding the uses now, so add them back.
298 if (OffsetRegUsed) {
299 assert(PreloadedScratchWaveOffsetReg != AMDGPU::NoRegister &&((PreloadedScratchWaveOffsetReg != AMDGPU::NoRegister &&
"scratch wave offset input is required") ? static_cast<void
> (0) : __assert_fail ("PreloadedScratchWaveOffsetReg != AMDGPU::NoRegister && \"scratch wave offset input is required\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/Target/AMDGPU/SIFrameLowering.cpp"
, 300, __PRETTY_FUNCTION__))
300 "scratch wave offset input is required")((PreloadedScratchWaveOffsetReg != AMDGPU::NoRegister &&
"scratch wave offset input is required") ? static_cast<void
> (0) : __assert_fail ("PreloadedScratchWaveOffsetReg != AMDGPU::NoRegister && \"scratch wave offset input is required\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/Target/AMDGPU/SIFrameLowering.cpp"
, 300, __PRETTY_FUNCTION__))
;
301 MRI.addLiveIn(PreloadedScratchWaveOffsetReg);
302 MBB.addLiveIn(PreloadedScratchWaveOffsetReg);
303 }
304
305 if (ResourceRegUsed && PreloadedPrivateBufferReg != AMDGPU::NoRegister) {
306 assert(ST.isAmdCodeObjectV2(MF) || ST.isMesaGfxShader(MF))((ST.isAmdCodeObjectV2(MF) || ST.isMesaGfxShader(MF)) ? static_cast
<void> (0) : __assert_fail ("ST.isAmdCodeObjectV2(MF) || ST.isMesaGfxShader(MF)"
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/Target/AMDGPU/SIFrameLowering.cpp"
, 306, __PRETTY_FUNCTION__))
;
307 MRI.addLiveIn(PreloadedPrivateBufferReg);
308 MBB.addLiveIn(PreloadedPrivateBufferReg);
309 }
310
311 // Make the register selected live throughout the function.
312 for (MachineBasicBlock &OtherBB : MF) {
313 if (&OtherBB == &MBB)
314 continue;
315
316 if (OffsetRegUsed)
317 OtherBB.addLiveIn(ScratchWaveOffsetReg);
318
319 if (ResourceRegUsed)
320 OtherBB.addLiveIn(ScratchRsrcReg);
321 }
322
323 DebugLoc DL;
324 MachineBasicBlock::iterator I = MBB.begin();
325
326 // If we reserved the original input registers, we don't need to copy to the
327 // reserved registers.
328
329 bool CopyBuffer = ResourceRegUsed &&
330 PreloadedPrivateBufferReg != AMDGPU::NoRegister &&
331 ST.isAmdCodeObjectV2(MF) &&
332 ScratchRsrcReg != PreloadedPrivateBufferReg;
333
334 // This needs to be careful of the copying order to avoid overwriting one of
335 // the input registers before it's been copied to it's final
336 // destination. Usually the offset should be copied first.
337 bool CopyBufferFirst = TRI->isSubRegisterEq(PreloadedPrivateBufferReg,
338 ScratchWaveOffsetReg);
339 if (CopyBuffer && CopyBufferFirst) {
340 BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), ScratchRsrcReg)
341 .addReg(PreloadedPrivateBufferReg, RegState::Kill);
342 }
343
344 if (OffsetRegUsed &&
345 PreloadedScratchWaveOffsetReg != ScratchWaveOffsetReg) {
346 BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), ScratchWaveOffsetReg)
347 .addReg(PreloadedScratchWaveOffsetReg,
348 MRI.isPhysRegUsed(ScratchWaveOffsetReg) ? 0 : RegState::Kill);
349 }
350
351 if (CopyBuffer && !CopyBufferFirst) {
352 BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), ScratchRsrcReg)
353 .addReg(PreloadedPrivateBufferReg, RegState::Kill);
354 }
355
356 if (ResourceRegUsed && (ST.isMesaGfxShader(MF) || (PreloadedPrivateBufferReg == AMDGPU::NoRegister))) {
357 assert(!ST.isAmdCodeObjectV2(MF))((!ST.isAmdCodeObjectV2(MF)) ? static_cast<void> (0) : __assert_fail
("!ST.isAmdCodeObjectV2(MF)", "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/Target/AMDGPU/SIFrameLowering.cpp"
, 357, __PRETTY_FUNCTION__))
;
358 const MCInstrDesc &SMovB32 = TII->get(AMDGPU::S_MOV_B32);
359
360 unsigned Rsrc2 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub2);
361 unsigned Rsrc3 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub3);
362
363 // Use relocations to get the pointer, and setup the other bits manually.
364 uint64_t Rsrc23 = TII->getScratchRsrcWords23();
365
366 if (MFI->hasPrivateMemoryInputPtr()) {
367 unsigned Rsrc01 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0_sub1);
368
369 if (AMDGPU::isCompute(MF.getFunction()->getCallingConv())) {
370 const MCInstrDesc &Mov64 = TII->get(AMDGPU::S_MOV_B64);
371
372 BuildMI(MBB, I, DL, Mov64, Rsrc01)
373 .addReg(PreloadedPrivateBufferReg)
374 .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
375 } else {
376 const MCInstrDesc &LoadDwordX2 = TII->get(AMDGPU::S_LOAD_DWORDX2_IMM);
377
378 PointerType *PtrTy =
379 PointerType::get(Type::getInt64Ty(MF.getFunction()->getContext()),
380 AMDGPUASI.CONSTANT_ADDRESS);
381 MachinePointerInfo PtrInfo(UndefValue::get(PtrTy));
382 auto MMO = MF.getMachineMemOperand(PtrInfo,
383 MachineMemOperand::MOLoad |
384 MachineMemOperand::MOInvariant |
385 MachineMemOperand::MODereferenceable,
386 0, 0);
387 BuildMI(MBB, I, DL, LoadDwordX2, Rsrc01)
388 .addReg(PreloadedPrivateBufferReg)
389 .addImm(0) // offset
390 .addImm(0) // glc
391 .addMemOperand(MMO)
392 .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
393 }
394 } else {
395 unsigned Rsrc0 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0);
396 unsigned Rsrc1 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub1);
397
398 BuildMI(MBB, I, DL, SMovB32, Rsrc0)
399 .addExternalSymbol("SCRATCH_RSRC_DWORD0")
400 .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
401
402 BuildMI(MBB, I, DL, SMovB32, Rsrc1)
403 .addExternalSymbol("SCRATCH_RSRC_DWORD1")
404 .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
405
406 }
407
408 BuildMI(MBB, I, DL, SMovB32, Rsrc2)
409 .addImm(Rsrc23 & 0xffffffff)
410 .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
411
412 BuildMI(MBB, I, DL, SMovB32, Rsrc3)
413 .addImm(Rsrc23 >> 32)
414 .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
415 }
416}
417
418void SIFrameLowering::emitPrologue(MachineFunction &MF,
419 MachineBasicBlock &MBB) const {
420 const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
421 if (MFI->isEntryFunction())
422 emitEntryFunctionPrologue(MF, MBB);
423}
424
425void SIFrameLowering::emitEpilogue(MachineFunction &MF,
426 MachineBasicBlock &MBB) const {
427
428}
429
430static bool allStackObjectsAreDead(const MachineFrameInfo &MFI) {
431 for (int I = MFI.getObjectIndexBegin(), E = MFI.getObjectIndexEnd();
432 I != E; ++I) {
433 if (!MFI.isDeadObjectIndex(I))
434 return false;
435 }
436
437 return true;
438}
439
440int SIFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI,
441 unsigned &FrameReg) const {
442 const SIRegisterInfo *RI = MF.getSubtarget<SISubtarget>().getRegisterInfo();
443
444 FrameReg = RI->getFrameRegister(MF);
445 return MF.getFrameInfo().getObjectOffset(FI);
446}
447
448void SIFrameLowering::processFunctionBeforeFrameFinalized(
449 MachineFunction &MF,
450 RegScavenger *RS) const {
451 MachineFrameInfo &MFI = MF.getFrameInfo();
452
453 if (!MFI.hasStackObjects())
454 return;
455
456 const SISubtarget &ST = MF.getSubtarget<SISubtarget>();
457 const SIInstrInfo *TII = ST.getInstrInfo();
458 const SIRegisterInfo &TRI = TII->getRegisterInfo();
459 SIMachineFunctionInfo *FuncInfo = MF.getInfo<SIMachineFunctionInfo>();
460 bool AllSGPRSpilledToVGPRs = false;
461
462 if (TRI.spillSGPRToVGPR() && FuncInfo->hasSpilledSGPRs()) {
463 AllSGPRSpilledToVGPRs = true;
464
465 // Process all SGPR spills before frame offsets are finalized. Ideally SGPRs
466 // are spilled to VGPRs, in which case we can eliminate the stack usage.
467 //
468 // XXX - This operates under the assumption that only other SGPR spills are
469 // users of the frame index. I'm not 100% sure this is correct. The
470 // StackColoring pass has a comment saying a future improvement would be to
471 // merging of allocas with spill slots, but for now according to
472 // MachineFrameInfo isSpillSlot can't alias any other object.
473 for (MachineBasicBlock &MBB : MF) {
474 MachineBasicBlock::iterator Next;
475 for (auto I = MBB.begin(), E = MBB.end(); I != E; I = Next) {
476 MachineInstr &MI = *I;
477 Next = std::next(I);
478
479 if (TII->isSGPRSpill(MI)) {
480 int FI = TII->getNamedOperand(MI, AMDGPU::OpName::addr)->getIndex();
481 if (FuncInfo->allocateSGPRSpillToVGPR(MF, FI)) {
482 bool Spilled = TRI.eliminateSGPRToVGPRSpillFrameIndex(MI, FI, RS);
483 (void)Spilled;
484 assert(Spilled && "failed to spill SGPR to VGPR when allocated")((Spilled && "failed to spill SGPR to VGPR when allocated"
) ? static_cast<void> (0) : __assert_fail ("Spilled && \"failed to spill SGPR to VGPR when allocated\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/Target/AMDGPU/SIFrameLowering.cpp"
, 484, __PRETTY_FUNCTION__))
;
485 } else
486 AllSGPRSpilledToVGPRs = false;
487 }
488 }
489 }
490
491 FuncInfo->removeSGPRToVGPRFrameIndices(MFI);
492 }
493
494 // FIXME: The other checks should be redundant with allStackObjectsAreDead,
495 // but currently hasNonSpillStackObjects is set only from source
496 // allocas. Stack temps produced from legalization are not counted currently.
497 if (FuncInfo->hasNonSpillStackObjects() || FuncInfo->hasSpilledVGPRs() ||
498 !AllSGPRSpilledToVGPRs || !allStackObjectsAreDead(MFI)) {
499 assert(RS && "RegScavenger required if spilling")((RS && "RegScavenger required if spilling") ? static_cast
<void> (0) : __assert_fail ("RS && \"RegScavenger required if spilling\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/Target/AMDGPU/SIFrameLowering.cpp"
, 499, __PRETTY_FUNCTION__))
;
500
501 // We force this to be at offset 0 so no user object ever has 0 as an
502 // address, so we may use 0 as an invalid pointer value. This is because
503 // LLVM assumes 0 is an invalid pointer in address space 0. Because alloca
504 // is required to be address space 0, we are forced to accept this for
505 // now. Ideally we could have the stack in another address space with 0 as a
506 // valid pointer, and -1 as the null value.
507 //
508 // This will also waste additional space when user stack objects require > 4
509 // byte alignment.
510 //
511 // The main cost here is losing the offset for addressing modes. However
512 // this also ensures we shouldn't need a register for the offset when
513 // emergency scavenging.
514 int ScavengeFI = MFI.CreateFixedObject(
515 TRI.getSpillSize(AMDGPU::SGPR_32RegClass), 0, false);
516 RS->addScavengingFrameIndex(ScavengeFI);
517 }
518}
519
520void SIFrameLowering::emitDebuggerPrologue(MachineFunction &MF,
521 MachineBasicBlock &MBB) const {
522 const SISubtarget &ST = MF.getSubtarget<SISubtarget>();
523 const SIInstrInfo *TII = ST.getInstrInfo();
524 const SIRegisterInfo *TRI = &TII->getRegisterInfo();
525 const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
526
527 MachineBasicBlock::iterator I = MBB.begin();
528 DebugLoc DL;
529
530 // For each dimension:
531 for (unsigned i = 0; i < 3; ++i) {
532 // Get work group ID SGPR, and make it live-in again.
533 unsigned WorkGroupIDSGPR = MFI->getWorkGroupIDSGPR(i);
534 MF.getRegInfo().addLiveIn(WorkGroupIDSGPR);
535 MBB.addLiveIn(WorkGroupIDSGPR);
536
537 // Since SGPRs are spilled into VGPRs, copy work group ID SGPR to VGPR in
538 // order to spill it to scratch.
539 unsigned WorkGroupIDVGPR =
540 MF.getRegInfo().createVirtualRegister(&AMDGPU::VGPR_32RegClass);
541 BuildMI(MBB, I, DL, TII->get(AMDGPU::V_MOV_B32_e32), WorkGroupIDVGPR)
542 .addReg(WorkGroupIDSGPR);
543
544 // Spill work group ID.
545 int WorkGroupIDObjectIdx = MFI->getDebuggerWorkGroupIDStackObjectIndex(i);
546 TII->storeRegToStackSlot(MBB, I, WorkGroupIDVGPR, false,
547 WorkGroupIDObjectIdx, &AMDGPU::VGPR_32RegClass, TRI);
548
549 // Get work item ID VGPR, and make it live-in again.
550 unsigned WorkItemIDVGPR = MFI->getWorkItemIDVGPR(i);
551 MF.getRegInfo().addLiveIn(WorkItemIDVGPR);
552 MBB.addLiveIn(WorkItemIDVGPR);
553
554 // Spill work item ID.
555 int WorkItemIDObjectIdx = MFI->getDebuggerWorkItemIDStackObjectIndex(i);
556 TII->storeRegToStackSlot(MBB, I, WorkItemIDVGPR, false,
557 WorkItemIDObjectIdx, &AMDGPU::VGPR_32RegClass, TRI);
558 }
559}