Bug Summary

File:lib/Target/AMDGPU/SIFrameLowering.cpp
Warning:line 205, column 9
Value stored to 'HandledScratchWaveOffsetReg' is never read

Annotated Source Code

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clang -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name SIFrameLowering.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-eagerly-assume -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -mrelocation-model pic -pic-level 2 -mthread-model posix -fmath-errno -masm-verbose -mconstructor-aliases -munwind-tables -fuse-init-array -target-cpu x86-64 -dwarf-column-info -debugger-tuning=gdb -momit-leaf-frame-pointer -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-7/lib/clang/7.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-7~svn329677/build-llvm/lib/Target/AMDGPU -I /build/llvm-toolchain-snapshot-7~svn329677/lib/Target/AMDGPU -I /build/llvm-toolchain-snapshot-7~svn329677/build-llvm/include -I /build/llvm-toolchain-snapshot-7~svn329677/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/7.3.0/../../../../include/c++/7.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/7.3.0/../../../../include/x86_64-linux-gnu/c++/7.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/7.3.0/../../../../include/x86_64-linux-gnu/c++/7.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/7.3.0/../../../../include/c++/7.3.0/backward -internal-isystem /usr/include/clang/7.0.0/include/ -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-7/lib/clang/7.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++11 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-7~svn329677/build-llvm/lib/Target/AMDGPU -ferror-limit 19 -fmessage-length 0 -fvisibility-inlines-hidden -fobjc-runtime=gcc -fdiagnostics-show-option -vectorize-loops -vectorize-slp -analyzer-checker optin.performance.Padding -analyzer-output=html -analyzer-config stable-report-filename=true -o /tmp/scan-build-2018-04-11-031539-24776-1 -x c++ /build/llvm-toolchain-snapshot-7~svn329677/lib/Target/AMDGPU/SIFrameLowering.cpp
1//===----------------------- SIFrameLowering.cpp --------------------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//==-----------------------------------------------------------------------===//
9
10#include "SIFrameLowering.h"
11#include "AMDGPUSubtarget.h"
12#include "SIInstrInfo.h"
13#include "SIMachineFunctionInfo.h"
14#include "SIRegisterInfo.h"
15
16#include "llvm/CodeGen/LivePhysRegs.h"
17#include "llvm/CodeGen/MachineFrameInfo.h"
18#include "llvm/CodeGen/MachineFunction.h"
19#include "llvm/CodeGen/MachineInstrBuilder.h"
20#include "llvm/CodeGen/RegisterScavenging.h"
21
22using namespace llvm;
23
24
25static ArrayRef<MCPhysReg> getAllSGPR128(const SISubtarget &ST,
26 const MachineFunction &MF) {
27 return makeArrayRef(AMDGPU::SGPR_128RegClass.begin(),
28 ST.getMaxNumSGPRs(MF) / 4);
29}
30
31static ArrayRef<MCPhysReg> getAllSGPRs(const SISubtarget &ST,
32 const MachineFunction &MF) {
33 return makeArrayRef(AMDGPU::SGPR_32RegClass.begin(),
34 ST.getMaxNumSGPRs(MF));
35}
36
37void SIFrameLowering::emitFlatScratchInit(const SISubtarget &ST,
38 MachineFunction &MF,
39 MachineBasicBlock &MBB) const {
40 const SIInstrInfo *TII = ST.getInstrInfo();
41 const SIRegisterInfo* TRI = &TII->getRegisterInfo();
42 const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
43
44 // We don't need this if we only have spills since there is no user facing
45 // scratch.
46
47 // TODO: If we know we don't have flat instructions earlier, we can omit
48 // this from the input registers.
49 //
50 // TODO: We only need to know if we access scratch space through a flat
51 // pointer. Because we only detect if flat instructions are used at all,
52 // this will be used more often than necessary on VI.
53
54 // Debug location must be unknown since the first debug location is used to
55 // determine the end of the prologue.
56 DebugLoc DL;
57 MachineBasicBlock::iterator I = MBB.begin();
58
59 unsigned FlatScratchInitReg
60 = MFI->getPreloadedReg(AMDGPUFunctionArgInfo::FLAT_SCRATCH_INIT);
61
62 MachineRegisterInfo &MRI = MF.getRegInfo();
63 MRI.addLiveIn(FlatScratchInitReg);
64 MBB.addLiveIn(FlatScratchInitReg);
65
66 unsigned FlatScrInitLo = TRI->getSubReg(FlatScratchInitReg, AMDGPU::sub0);
67 unsigned FlatScrInitHi = TRI->getSubReg(FlatScratchInitReg, AMDGPU::sub1);
68
69 unsigned ScratchWaveOffsetReg = MFI->getScratchWaveOffsetReg();
70
71 // Do a 64-bit pointer add.
72 if (ST.flatScratchIsPointer()) {
73 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_ADD_U32), AMDGPU::FLAT_SCR_LO)
74 .addReg(FlatScrInitLo)
75 .addReg(ScratchWaveOffsetReg);
76 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_ADDC_U32), AMDGPU::FLAT_SCR_HI)
77 .addReg(FlatScrInitHi)
78 .addImm(0);
79
80 return;
81 }
82
83 // Copy the size in bytes.
84 BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), AMDGPU::FLAT_SCR_LO)
85 .addReg(FlatScrInitHi, RegState::Kill);
86
87 // Add wave offset in bytes to private base offset.
88 // See comment in AMDKernelCodeT.h for enable_sgpr_flat_scratch_init.
89 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_ADD_U32), FlatScrInitLo)
90 .addReg(FlatScrInitLo)
91 .addReg(ScratchWaveOffsetReg);
92
93 // Convert offset to 256-byte units.
94 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_LSHR_B32), AMDGPU::FLAT_SCR_HI)
95 .addReg(FlatScrInitLo, RegState::Kill)
96 .addImm(8);
97}
98
99unsigned SIFrameLowering::getReservedPrivateSegmentBufferReg(
100 const SISubtarget &ST,
101 const SIInstrInfo *TII,
102 const SIRegisterInfo *TRI,
103 SIMachineFunctionInfo *MFI,
104 MachineFunction &MF) const {
105 MachineRegisterInfo &MRI = MF.getRegInfo();
106
107 // We need to insert initialization of the scratch resource descriptor.
108 unsigned ScratchRsrcReg = MFI->getScratchRSrcReg();
109 if (ScratchRsrcReg == AMDGPU::NoRegister ||
110 !MRI.isPhysRegUsed(ScratchRsrcReg))
111 return AMDGPU::NoRegister;
112
113 if (ST.hasSGPRInitBug() ||
114 ScratchRsrcReg != TRI->reservedPrivateSegmentBufferReg(MF))
115 return ScratchRsrcReg;
116
117 // We reserved the last registers for this. Shift it down to the end of those
118 // which were actually used.
119 //
120 // FIXME: It might be safer to use a pseudoregister before replacement.
121
122 // FIXME: We should be able to eliminate unused input registers. We only
123 // cannot do this for the resources required for scratch access. For now we
124 // skip over user SGPRs and may leave unused holes.
125
126 // We find the resource first because it has an alignment requirement.
127
128 unsigned NumPreloaded = (MFI->getNumPreloadedSGPRs() + 3) / 4;
129 ArrayRef<MCPhysReg> AllSGPR128s = getAllSGPR128(ST, MF);
130 AllSGPR128s = AllSGPR128s.slice(std::min(static_cast<unsigned>(AllSGPR128s.size()), NumPreloaded));
131
132 // Skip the last N reserved elements because they should have already been
133 // reserved for VCC etc.
134 for (MCPhysReg Reg : AllSGPR128s) {
135 // Pick the first unallocated one. Make sure we don't clobber the other
136 // reserved input we needed.
137 if (!MRI.isPhysRegUsed(Reg) && MRI.isAllocatable(Reg)) {
138 MRI.replaceRegWith(ScratchRsrcReg, Reg);
139 MFI->setScratchRSrcReg(Reg);
140 return Reg;
141 }
142 }
143
144 return ScratchRsrcReg;
145}
146
147// Shift down registers reserved for the scratch wave offset and stack pointer
148// SGPRs.
149std::pair<unsigned, unsigned>
150SIFrameLowering::getReservedPrivateSegmentWaveByteOffsetReg(
151 const SISubtarget &ST,
152 const SIInstrInfo *TII,
153 const SIRegisterInfo *TRI,
154 SIMachineFunctionInfo *MFI,
155 MachineFunction &MF) const {
156 MachineRegisterInfo &MRI = MF.getRegInfo();
157 unsigned ScratchWaveOffsetReg = MFI->getScratchWaveOffsetReg();
158
159 // No replacement necessary.
160 if (ScratchWaveOffsetReg == AMDGPU::NoRegister ||
161 !MRI.isPhysRegUsed(ScratchWaveOffsetReg)) {
162 assert(MFI->getStackPtrOffsetReg() == AMDGPU::SP_REG)(static_cast <bool> (MFI->getStackPtrOffsetReg() == AMDGPU
::SP_REG) ? void (0) : __assert_fail ("MFI->getStackPtrOffsetReg() == AMDGPU::SP_REG"
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/AMDGPU/SIFrameLowering.cpp"
, 162, __extension__ __PRETTY_FUNCTION__))
;
163 return std::make_pair(AMDGPU::NoRegister, AMDGPU::NoRegister);
164 }
165
166 unsigned SPReg = MFI->getStackPtrOffsetReg();
167 if (ST.hasSGPRInitBug())
168 return std::make_pair(ScratchWaveOffsetReg, SPReg);
169
170 unsigned NumPreloaded = MFI->getNumPreloadedSGPRs();
171
172 ArrayRef<MCPhysReg> AllSGPRs = getAllSGPRs(ST, MF);
173 if (NumPreloaded > AllSGPRs.size())
174 return std::make_pair(ScratchWaveOffsetReg, SPReg);
175
176 AllSGPRs = AllSGPRs.slice(NumPreloaded);
177
178 // We need to drop register from the end of the list that we cannot use
179 // for the scratch wave offset.
180 // + 2 s102 and s103 do not exist on VI.
181 // + 2 for vcc
182 // + 2 for xnack_mask
183 // + 2 for flat_scratch
184 // + 4 for registers reserved for scratch resource register
185 // + 1 for register reserved for scratch wave offset. (By exluding this
186 // register from the list to consider, it means that when this
187 // register is being used for the scratch wave offset and there
188 // are no other free SGPRs, then the value will stay in this register.
189 // + 1 if stack pointer is used.
190 // ----
191 // 13 (+1)
192 unsigned ReservedRegCount = 13;
193
194 if (AllSGPRs.size() < ReservedRegCount)
195 return std::make_pair(ScratchWaveOffsetReg, SPReg);
196
197 bool HandledScratchWaveOffsetReg =
198 ScratchWaveOffsetReg != TRI->reservedPrivateSegmentWaveByteOffsetReg(MF);
199
200 for (MCPhysReg Reg : AllSGPRs.drop_back(ReservedRegCount)) {
201 // Pick the first unallocated SGPR. Be careful not to pick an alias of the
202 // scratch descriptor, since we haven’t added its uses yet.
203 if (!MRI.isPhysRegUsed(Reg) && MRI.isAllocatable(Reg)) {
204 if (!HandledScratchWaveOffsetReg) {
205 HandledScratchWaveOffsetReg = true;
Value stored to 'HandledScratchWaveOffsetReg' is never read
206
207 MRI.replaceRegWith(ScratchWaveOffsetReg, Reg);
208 MFI->setScratchWaveOffsetReg(Reg);
209 ScratchWaveOffsetReg = Reg;
210 break;
211 }
212 }
213 }
214
215 return std::make_pair(ScratchWaveOffsetReg, SPReg);
216}
217
218void SIFrameLowering::emitEntryFunctionPrologue(MachineFunction &MF,
219 MachineBasicBlock &MBB) const {
220 // Emit debugger prologue if "amdgpu-debugger-emit-prologue" attribute was
221 // specified.
222 const SISubtarget &ST = MF.getSubtarget<SISubtarget>();
223 if (ST.debuggerEmitPrologue())
224 emitDebuggerPrologue(MF, MBB);
225
226 assert(&MF.front() == &MBB && "Shrink-wrapping not yet supported")(static_cast <bool> (&MF.front() == &MBB &&
"Shrink-wrapping not yet supported") ? void (0) : __assert_fail
("&MF.front() == &MBB && \"Shrink-wrapping not yet supported\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/AMDGPU/SIFrameLowering.cpp"
, 226, __extension__ __PRETTY_FUNCTION__))
;
227
228 SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
229
230 // If we only have SGPR spills, we won't actually be using scratch memory
231 // since these spill to VGPRs.
232 //
233 // FIXME: We should be cleaning up these unused SGPR spill frame indices
234 // somewhere.
235
236 const SIInstrInfo *TII = ST.getInstrInfo();
237 const SIRegisterInfo *TRI = &TII->getRegisterInfo();
238 MachineRegisterInfo &MRI = MF.getRegInfo();
239
240 // We need to do the replacement of the private segment buffer and wave offset
241 // register even if there are no stack objects. There could be stores to undef
242 // or a constant without an associated object.
243
244 // FIXME: We still have implicit uses on SGPR spill instructions in case they
245 // need to spill to vector memory. It's likely that will not happen, but at
246 // this point it appears we need the setup. This part of the prolog should be
247 // emitted after frame indices are eliminated.
248
249 if (MFI->hasFlatScratchInit())
250 emitFlatScratchInit(ST, MF, MBB);
251
252 unsigned SPReg = MFI->getStackPtrOffsetReg();
253 if (SPReg != AMDGPU::SP_REG) {
254 assert(MRI.isReserved(SPReg) && "SPReg used but not reserved")(static_cast <bool> (MRI.isReserved(SPReg) && "SPReg used but not reserved"
) ? void (0) : __assert_fail ("MRI.isReserved(SPReg) && \"SPReg used but not reserved\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/AMDGPU/SIFrameLowering.cpp"
, 254, __extension__ __PRETTY_FUNCTION__))
;
255
256 DebugLoc DL;
257 const MachineFrameInfo &FrameInfo = MF.getFrameInfo();
258 int64_t StackSize = FrameInfo.getStackSize();
259
260 if (StackSize == 0) {
261 BuildMI(MBB, MBB.begin(), DL, TII->get(AMDGPU::COPY), SPReg)
262 .addReg(MFI->getScratchWaveOffsetReg());
263 } else {
264 BuildMI(MBB, MBB.begin(), DL, TII->get(AMDGPU::S_ADD_U32), SPReg)
265 .addReg(MFI->getScratchWaveOffsetReg())
266 .addImm(StackSize * ST.getWavefrontSize());
267 }
268 }
269
270 unsigned ScratchRsrcReg
271 = getReservedPrivateSegmentBufferReg(ST, TII, TRI, MFI, MF);
272
273 unsigned ScratchWaveOffsetReg;
274 std::tie(ScratchWaveOffsetReg, SPReg)
275 = getReservedPrivateSegmentWaveByteOffsetReg(ST, TII, TRI, MFI, MF);
276
277 // It's possible to have uses of only ScratchWaveOffsetReg without
278 // ScratchRsrcReg if it's only used for the initialization of flat_scratch,
279 // but the inverse is not true.
280 if (ScratchWaveOffsetReg == AMDGPU::NoRegister) {
281 assert(ScratchRsrcReg == AMDGPU::NoRegister)(static_cast <bool> (ScratchRsrcReg == AMDGPU::NoRegister
) ? void (0) : __assert_fail ("ScratchRsrcReg == AMDGPU::NoRegister"
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/AMDGPU/SIFrameLowering.cpp"
, 281, __extension__ __PRETTY_FUNCTION__))
;
282 return;
283 }
284
285 // We need to insert initialization of the scratch resource descriptor.
286 unsigned PreloadedScratchWaveOffsetReg = MFI->getPreloadedReg(
287 AMDGPUFunctionArgInfo::PRIVATE_SEGMENT_WAVE_BYTE_OFFSET);
288
289 unsigned PreloadedPrivateBufferReg = AMDGPU::NoRegister;
290 if (ST.isAmdCodeObjectV2(MF)) {
291 PreloadedPrivateBufferReg = MFI->getPreloadedReg(
292 AMDGPUFunctionArgInfo::PRIVATE_SEGMENT_BUFFER);
293 }
294
295 bool OffsetRegUsed = MRI.isPhysRegUsed(ScratchWaveOffsetReg);
296 bool ResourceRegUsed = ScratchRsrcReg != AMDGPU::NoRegister &&
297 MRI.isPhysRegUsed(ScratchRsrcReg);
298
299 // We added live-ins during argument lowering, but since they were not used
300 // they were deleted. We're adding the uses now, so add them back.
301 if (OffsetRegUsed) {
302 assert(PreloadedScratchWaveOffsetReg != AMDGPU::NoRegister &&(static_cast <bool> (PreloadedScratchWaveOffsetReg != AMDGPU
::NoRegister && "scratch wave offset input is required"
) ? void (0) : __assert_fail ("PreloadedScratchWaveOffsetReg != AMDGPU::NoRegister && \"scratch wave offset input is required\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/AMDGPU/SIFrameLowering.cpp"
, 303, __extension__ __PRETTY_FUNCTION__))
303 "scratch wave offset input is required")(static_cast <bool> (PreloadedScratchWaveOffsetReg != AMDGPU
::NoRegister && "scratch wave offset input is required"
) ? void (0) : __assert_fail ("PreloadedScratchWaveOffsetReg != AMDGPU::NoRegister && \"scratch wave offset input is required\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/AMDGPU/SIFrameLowering.cpp"
, 303, __extension__ __PRETTY_FUNCTION__))
;
304 MRI.addLiveIn(PreloadedScratchWaveOffsetReg);
305 MBB.addLiveIn(PreloadedScratchWaveOffsetReg);
306 }
307
308 if (ResourceRegUsed && PreloadedPrivateBufferReg != AMDGPU::NoRegister) {
309 assert(ST.isAmdCodeObjectV2(MF) || ST.isMesaGfxShader(MF))(static_cast <bool> (ST.isAmdCodeObjectV2(MF) || ST.isMesaGfxShader
(MF)) ? void (0) : __assert_fail ("ST.isAmdCodeObjectV2(MF) || ST.isMesaGfxShader(MF)"
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/AMDGPU/SIFrameLowering.cpp"
, 309, __extension__ __PRETTY_FUNCTION__))
;
310 MRI.addLiveIn(PreloadedPrivateBufferReg);
311 MBB.addLiveIn(PreloadedPrivateBufferReg);
312 }
313
314 // Make the register selected live throughout the function.
315 for (MachineBasicBlock &OtherBB : MF) {
316 if (&OtherBB == &MBB)
317 continue;
318
319 if (OffsetRegUsed)
320 OtherBB.addLiveIn(ScratchWaveOffsetReg);
321
322 if (ResourceRegUsed)
323 OtherBB.addLiveIn(ScratchRsrcReg);
324 }
325
326 DebugLoc DL;
327 MachineBasicBlock::iterator I = MBB.begin();
328
329 // If we reserved the original input registers, we don't need to copy to the
330 // reserved registers.
331
332 bool CopyBuffer = ResourceRegUsed &&
333 PreloadedPrivateBufferReg != AMDGPU::NoRegister &&
334 ST.isAmdCodeObjectV2(MF) &&
335 ScratchRsrcReg != PreloadedPrivateBufferReg;
336
337 // This needs to be careful of the copying order to avoid overwriting one of
338 // the input registers before it's been copied to it's final
339 // destination. Usually the offset should be copied first.
340 bool CopyBufferFirst = TRI->isSubRegisterEq(PreloadedPrivateBufferReg,
341 ScratchWaveOffsetReg);
342 if (CopyBuffer && CopyBufferFirst) {
343 BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), ScratchRsrcReg)
344 .addReg(PreloadedPrivateBufferReg, RegState::Kill);
345 }
346
347 if (OffsetRegUsed &&
348 PreloadedScratchWaveOffsetReg != ScratchWaveOffsetReg) {
349 BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), ScratchWaveOffsetReg)
350 .addReg(PreloadedScratchWaveOffsetReg,
351 MRI.isPhysRegUsed(ScratchWaveOffsetReg) ? 0 : RegState::Kill);
352 }
353
354 if (CopyBuffer && !CopyBufferFirst) {
355 BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), ScratchRsrcReg)
356 .addReg(PreloadedPrivateBufferReg, RegState::Kill);
357 }
358
359 if (ResourceRegUsed)
360 emitEntryFunctionScratchSetup(ST, MF, MBB, MFI, I,
361 PreloadedPrivateBufferReg, ScratchRsrcReg);
362}
363
364// Emit scratch setup code for AMDPAL or Mesa, assuming ResourceRegUsed is set.
365void SIFrameLowering::emitEntryFunctionScratchSetup(const SISubtarget &ST,
366 MachineFunction &MF, MachineBasicBlock &MBB, SIMachineFunctionInfo *MFI,
367 MachineBasicBlock::iterator I, unsigned PreloadedPrivateBufferReg,
368 unsigned ScratchRsrcReg) const {
369
370 const SIInstrInfo *TII = ST.getInstrInfo();
371 const SIRegisterInfo *TRI = &TII->getRegisterInfo();
372 DebugLoc DL;
373
374 if (ST.isAmdPalOS()) {
375 // The pointer to the GIT is formed from the offset passed in and either
376 // the amdgpu-git-ptr-high function attribute or the top part of the PC
377 unsigned RsrcLo = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0);
378 unsigned RsrcHi = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub1);
379 unsigned Rsrc01 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0_sub1);
380
381 const MCInstrDesc &SMovB32 = TII->get(AMDGPU::S_MOV_B32);
382
383 if (MFI->getGITPtrHigh() != 0xffffffff) {
384 BuildMI(MBB, I, DL, SMovB32, RsrcHi)
385 .addImm(MFI->getGITPtrHigh())
386 .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
387 } else {
388 const MCInstrDesc &GetPC64 = TII->get(AMDGPU::S_GETPC_B64);
389 BuildMI(MBB, I, DL, GetPC64, Rsrc01);
390 }
391 auto GitPtrLo = AMDGPU::SGPR0; // Low GIT address passed in
392 if (ST.hasMergedShaders()) {
393 switch (MF.getFunction().getCallingConv()) {
394 case CallingConv::AMDGPU_HS:
395 case CallingConv::AMDGPU_GS:
396 // Low GIT address is passed in s8 rather than s0 for an LS+HS or
397 // ES+GS merged shader on gfx9+.
398 GitPtrLo = AMDGPU::SGPR8;
399 break;
400 default:
401 break;
402 }
403 }
404 BuildMI(MBB, I, DL, SMovB32, RsrcLo)
405 .addReg(GitPtrLo)
406 .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
407
408 // We now have the GIT ptr - now get the scratch descriptor from the entry
409 // at offset 0.
410 PointerType *PtrTy =
411 PointerType::get(Type::getInt64Ty(MF.getFunction().getContext()),
412 AMDGPUAS::CONSTANT_ADDRESS);
413 MachinePointerInfo PtrInfo(UndefValue::get(PtrTy));
414 const MCInstrDesc &LoadDwordX4 = TII->get(AMDGPU::S_LOAD_DWORDX4_IMM);
415 auto MMO = MF.getMachineMemOperand(PtrInfo,
416 MachineMemOperand::MOLoad |
417 MachineMemOperand::MOInvariant |
418 MachineMemOperand::MODereferenceable,
419 0, 0);
420 BuildMI(MBB, I, DL, LoadDwordX4, ScratchRsrcReg)
421 .addReg(Rsrc01)
422 .addImm(0) // offset
423 .addImm(0) // glc
424 .addReg(ScratchRsrcReg, RegState::ImplicitDefine)
425 .addMemOperand(MMO);
426 return;
427 }
428 if (ST.isMesaGfxShader(MF)
429 || (PreloadedPrivateBufferReg == AMDGPU::NoRegister)) {
430 assert(!ST.isAmdCodeObjectV2(MF))(static_cast <bool> (!ST.isAmdCodeObjectV2(MF)) ? void (
0) : __assert_fail ("!ST.isAmdCodeObjectV2(MF)", "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/AMDGPU/SIFrameLowering.cpp"
, 430, __extension__ __PRETTY_FUNCTION__))
;
431 const MCInstrDesc &SMovB32 = TII->get(AMDGPU::S_MOV_B32);
432
433 unsigned Rsrc2 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub2);
434 unsigned Rsrc3 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub3);
435
436 // Use relocations to get the pointer, and setup the other bits manually.
437 uint64_t Rsrc23 = TII->getScratchRsrcWords23();
438
439 if (MFI->hasImplicitBufferPtr()) {
440 unsigned Rsrc01 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0_sub1);
441
442 if (AMDGPU::isCompute(MF.getFunction().getCallingConv())) {
443 const MCInstrDesc &Mov64 = TII->get(AMDGPU::S_MOV_B64);
444
445 BuildMI(MBB, I, DL, Mov64, Rsrc01)
446 .addReg(MFI->getImplicitBufferPtrUserSGPR())
447 .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
448 } else {
449 const MCInstrDesc &LoadDwordX2 = TII->get(AMDGPU::S_LOAD_DWORDX2_IMM);
450
451 PointerType *PtrTy =
452 PointerType::get(Type::getInt64Ty(MF.getFunction().getContext()),
453 AMDGPUAS::CONSTANT_ADDRESS);
454 MachinePointerInfo PtrInfo(UndefValue::get(PtrTy));
455 auto MMO = MF.getMachineMemOperand(PtrInfo,
456 MachineMemOperand::MOLoad |
457 MachineMemOperand::MOInvariant |
458 MachineMemOperand::MODereferenceable,
459 0, 0);
460 BuildMI(MBB, I, DL, LoadDwordX2, Rsrc01)
461 .addReg(MFI->getImplicitBufferPtrUserSGPR())
462 .addImm(0) // offset
463 .addImm(0) // glc
464 .addMemOperand(MMO)
465 .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
466 }
467 } else {
468 unsigned Rsrc0 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0);
469 unsigned Rsrc1 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub1);
470
471 BuildMI(MBB, I, DL, SMovB32, Rsrc0)
472 .addExternalSymbol("SCRATCH_RSRC_DWORD0")
473 .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
474
475 BuildMI(MBB, I, DL, SMovB32, Rsrc1)
476 .addExternalSymbol("SCRATCH_RSRC_DWORD1")
477 .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
478
479 }
480
481 BuildMI(MBB, I, DL, SMovB32, Rsrc2)
482 .addImm(Rsrc23 & 0xffffffff)
483 .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
484
485 BuildMI(MBB, I, DL, SMovB32, Rsrc3)
486 .addImm(Rsrc23 >> 32)
487 .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
488 }
489}
490
491// Find a scratch register that we can use at the start of the prologue to
492// re-align the stack pointer. We avoid using callee-save registers since they
493// may appear to be free when this is called from canUseAsPrologue (during
494// shrink wrapping), but then no longer be free when this is called from
495// emitPrologue.
496//
497// FIXME: This is a bit conservative, since in the above case we could use one
498// of the callee-save registers as a scratch temp to re-align the stack pointer,
499// but we would then have to make sure that we were in fact saving at least one
500// callee-save register in the prologue, which is additional complexity that
501// doesn't seem worth the benefit.
502static unsigned findScratchNonCalleeSaveRegister(MachineBasicBlock &MBB) {
503 MachineFunction *MF = MBB.getParent();
504
505 const SISubtarget &Subtarget = MF->getSubtarget<SISubtarget>();
506 const SIRegisterInfo &TRI = *Subtarget.getRegisterInfo();
507 LivePhysRegs LiveRegs(TRI);
508 LiveRegs.addLiveIns(MBB);
509
510 // Mark callee saved registers as used so we will not choose them.
511 const MCPhysReg *CSRegs = TRI.getCalleeSavedRegs(MF);
512 for (unsigned i = 0; CSRegs[i]; ++i)
513 LiveRegs.addReg(CSRegs[i]);
514
515 MachineRegisterInfo &MRI = MF->getRegInfo();
516
517 for (unsigned Reg : AMDGPU::SReg_32_XM0RegClass) {
518 if (LiveRegs.available(MRI, Reg))
519 return Reg;
520 }
521
522 return AMDGPU::NoRegister;
523}
524
525void SIFrameLowering::emitPrologue(MachineFunction &MF,
526 MachineBasicBlock &MBB) const {
527 SIMachineFunctionInfo *FuncInfo = MF.getInfo<SIMachineFunctionInfo>();
528 if (FuncInfo->isEntryFunction()) {
529 emitEntryFunctionPrologue(MF, MBB);
530 return;
531 }
532
533 const MachineFrameInfo &MFI = MF.getFrameInfo();
534 const SISubtarget &ST = MF.getSubtarget<SISubtarget>();
535 const SIInstrInfo *TII = ST.getInstrInfo();
536 const SIRegisterInfo &TRI = TII->getRegisterInfo();
537
538 unsigned StackPtrReg = FuncInfo->getStackPtrOffsetReg();
539 unsigned FramePtrReg = FuncInfo->getFrameOffsetReg();
540
541 MachineBasicBlock::iterator MBBI = MBB.begin();
542 DebugLoc DL;
543
544 // XXX - Is this the right predicate?
545
546 bool NeedFP = hasFP(MF);
547 uint32_t NumBytes = MFI.getStackSize();
548 uint32_t RoundedSize = NumBytes;
549 const bool NeedsRealignment = TRI.needsStackRealignment(MF);
550
551 if (NeedsRealignment) {
552 assert(NeedFP)(static_cast <bool> (NeedFP) ? void (0) : __assert_fail
("NeedFP", "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/AMDGPU/SIFrameLowering.cpp"
, 552, __extension__ __PRETTY_FUNCTION__))
;
553 const unsigned Alignment = MFI.getMaxAlignment();
554
555 RoundedSize += Alignment;
556
557 unsigned ScratchSPReg = findScratchNonCalleeSaveRegister(MBB);
558 assert(ScratchSPReg != AMDGPU::NoRegister)(static_cast <bool> (ScratchSPReg != AMDGPU::NoRegister
) ? void (0) : __assert_fail ("ScratchSPReg != AMDGPU::NoRegister"
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/AMDGPU/SIFrameLowering.cpp"
, 558, __extension__ __PRETTY_FUNCTION__))
;
559
560 // s_add_u32 tmp_reg, s32, NumBytes
561 // s_and_b32 s32, tmp_reg, 0b111...0000
562 BuildMI(MBB, MBBI, DL, TII->get(AMDGPU::S_ADD_U32), ScratchSPReg)
563 .addReg(StackPtrReg)
564 .addImm((Alignment - 1) * ST.getWavefrontSize())
565 .setMIFlag(MachineInstr::FrameSetup);
566 BuildMI(MBB, MBBI, DL, TII->get(AMDGPU::S_AND_B32), FramePtrReg)
567 .addReg(ScratchSPReg, RegState::Kill)
568 .addImm(-Alignment * ST.getWavefrontSize())
569 .setMIFlag(MachineInstr::FrameSetup);
570 FuncInfo->setIsStackRealigned(true);
571 } else if (NeedFP) {
572 // If we need a base pointer, set it up here. It's whatever the value of
573 // the stack pointer is at this point. Any variable size objects will be
574 // allocated after this, so we can still use the base pointer to reference
575 // locals.
576 BuildMI(MBB, MBBI, DL, TII->get(AMDGPU::COPY), FramePtrReg)
577 .addReg(StackPtrReg)
578 .setMIFlag(MachineInstr::FrameSetup);
579 }
580
581 if (RoundedSize != 0 && hasSP(MF)) {
582 BuildMI(MBB, MBBI, DL, TII->get(AMDGPU::S_ADD_U32), StackPtrReg)
583 .addReg(StackPtrReg)
584 .addImm(RoundedSize * ST.getWavefrontSize())
585 .setMIFlag(MachineInstr::FrameSetup);
586 }
587
588 for (const SIMachineFunctionInfo::SGPRSpillVGPRCSR &Reg
589 : FuncInfo->getSGPRSpillVGPRs()) {
590 if (!Reg.FI.hasValue())
591 continue;
592 TII->storeRegToStackSlot(MBB, MBBI, Reg.VGPR, true,
593 Reg.FI.getValue(), &AMDGPU::VGPR_32RegClass,
594 &TII->getRegisterInfo());
595 }
596}
597
598void SIFrameLowering::emitEpilogue(MachineFunction &MF,
599 MachineBasicBlock &MBB) const {
600 const SIMachineFunctionInfo *FuncInfo = MF.getInfo<SIMachineFunctionInfo>();
601 if (FuncInfo->isEntryFunction())
602 return;
603
604 const SISubtarget &ST = MF.getSubtarget<SISubtarget>();
605 const SIInstrInfo *TII = ST.getInstrInfo();
606 MachineBasicBlock::iterator MBBI = MBB.getFirstTerminator();
607
608 for (const SIMachineFunctionInfo::SGPRSpillVGPRCSR &Reg
609 : FuncInfo->getSGPRSpillVGPRs()) {
610 if (!Reg.FI.hasValue())
611 continue;
612 TII->loadRegFromStackSlot(MBB, MBBI, Reg.VGPR,
613 Reg.FI.getValue(), &AMDGPU::VGPR_32RegClass,
614 &TII->getRegisterInfo());
615 }
616
617 unsigned StackPtrReg = FuncInfo->getStackPtrOffsetReg();
618 if (StackPtrReg == AMDGPU::NoRegister)
619 return;
620
621 const MachineFrameInfo &MFI = MF.getFrameInfo();
622 uint32_t NumBytes = MFI.getStackSize();
623
624 DebugLoc DL;
625
626 // FIXME: Clarify distinction between no set SP and SP. For callee functions,
627 // it's really whether we need SP to be accurate or not.
628
629 if (NumBytes != 0 && hasSP(MF)) {
630 uint32_t RoundedSize = FuncInfo->isStackRealigned() ?
631 NumBytes + MFI.getMaxAlignment() : NumBytes;
632
633 BuildMI(MBB, MBBI, DL, TII->get(AMDGPU::S_SUB_U32), StackPtrReg)
634 .addReg(StackPtrReg)
635 .addImm(RoundedSize * ST.getWavefrontSize());
636 }
637}
638
639static bool allStackObjectsAreDead(const MachineFrameInfo &MFI) {
640 for (int I = MFI.getObjectIndexBegin(), E = MFI.getObjectIndexEnd();
641 I != E; ++I) {
642 if (!MFI.isDeadObjectIndex(I))
643 return false;
644 }
645
646 return true;
647}
648
649int SIFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI,
650 unsigned &FrameReg) const {
651 const SIRegisterInfo *RI = MF.getSubtarget<SISubtarget>().getRegisterInfo();
652
653 FrameReg = RI->getFrameRegister(MF);
654 return MF.getFrameInfo().getObjectOffset(FI);
655}
656
657void SIFrameLowering::processFunctionBeforeFrameFinalized(
658 MachineFunction &MF,
659 RegScavenger *RS) const {
660 MachineFrameInfo &MFI = MF.getFrameInfo();
661
662 if (!MFI.hasStackObjects())
663 return;
664
665 const SISubtarget &ST = MF.getSubtarget<SISubtarget>();
666 const SIInstrInfo *TII = ST.getInstrInfo();
667 const SIRegisterInfo &TRI = TII->getRegisterInfo();
668 SIMachineFunctionInfo *FuncInfo = MF.getInfo<SIMachineFunctionInfo>();
669 bool AllSGPRSpilledToVGPRs = false;
670
671 if (TRI.spillSGPRToVGPR() && FuncInfo->hasSpilledSGPRs()) {
672 AllSGPRSpilledToVGPRs = true;
673
674 // Process all SGPR spills before frame offsets are finalized. Ideally SGPRs
675 // are spilled to VGPRs, in which case we can eliminate the stack usage.
676 //
677 // XXX - This operates under the assumption that only other SGPR spills are
678 // users of the frame index. I'm not 100% sure this is correct. The
679 // StackColoring pass has a comment saying a future improvement would be to
680 // merging of allocas with spill slots, but for now according to
681 // MachineFrameInfo isSpillSlot can't alias any other object.
682 for (MachineBasicBlock &MBB : MF) {
683 MachineBasicBlock::iterator Next;
684 for (auto I = MBB.begin(), E = MBB.end(); I != E; I = Next) {
685 MachineInstr &MI = *I;
686 Next = std::next(I);
687
688 if (TII->isSGPRSpill(MI)) {
689 int FI = TII->getNamedOperand(MI, AMDGPU::OpName::addr)->getIndex();
690 if (FuncInfo->allocateSGPRSpillToVGPR(MF, FI)) {
691 bool Spilled = TRI.eliminateSGPRToVGPRSpillFrameIndex(MI, FI, RS);
692 (void)Spilled;
693 assert(Spilled && "failed to spill SGPR to VGPR when allocated")(static_cast <bool> (Spilled && "failed to spill SGPR to VGPR when allocated"
) ? void (0) : __assert_fail ("Spilled && \"failed to spill SGPR to VGPR when allocated\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/AMDGPU/SIFrameLowering.cpp"
, 693, __extension__ __PRETTY_FUNCTION__))
;
694 } else
695 AllSGPRSpilledToVGPRs = false;
696 }
697 }
698 }
699
700 FuncInfo->removeSGPRToVGPRFrameIndices(MFI);
701 }
702
703 // FIXME: The other checks should be redundant with allStackObjectsAreDead,
704 // but currently hasNonSpillStackObjects is set only from source
705 // allocas. Stack temps produced from legalization are not counted currently.
706 if (FuncInfo->hasNonSpillStackObjects() || FuncInfo->hasSpilledVGPRs() ||
707 !AllSGPRSpilledToVGPRs || !allStackObjectsAreDead(MFI)) {
708 assert(RS && "RegScavenger required if spilling")(static_cast <bool> (RS && "RegScavenger required if spilling"
) ? void (0) : __assert_fail ("RS && \"RegScavenger required if spilling\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/AMDGPU/SIFrameLowering.cpp"
, 708, __extension__ __PRETTY_FUNCTION__))
;
709
710 // We force this to be at offset 0 so no user object ever has 0 as an
711 // address, so we may use 0 as an invalid pointer value. This is because
712 // LLVM assumes 0 is an invalid pointer in address space 0. Because alloca
713 // is required to be address space 0, we are forced to accept this for
714 // now. Ideally we could have the stack in another address space with 0 as a
715 // valid pointer, and -1 as the null value.
716 //
717 // This will also waste additional space when user stack objects require > 4
718 // byte alignment.
719 //
720 // The main cost here is losing the offset for addressing modes. However
721 // this also ensures we shouldn't need a register for the offset when
722 // emergency scavenging.
723 int ScavengeFI = MFI.CreateFixedObject(
724 TRI.getSpillSize(AMDGPU::SGPR_32RegClass), 0, false);
725 RS->addScavengingFrameIndex(ScavengeFI);
726 }
727}
728
729void SIFrameLowering::determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs,
730 RegScavenger *RS) const {
731 TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
732 const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
733
734 // The SP is specifically managed and we don't want extra spills of it.
735 SavedRegs.reset(MFI->getStackPtrOffsetReg());
736}
737
738MachineBasicBlock::iterator SIFrameLowering::eliminateCallFramePseudoInstr(
739 MachineFunction &MF,
740 MachineBasicBlock &MBB,
741 MachineBasicBlock::iterator I) const {
742 int64_t Amount = I->getOperand(0).getImm();
743 if (Amount == 0)
744 return MBB.erase(I);
745
746 const SISubtarget &ST = MF.getSubtarget<SISubtarget>();
747 const SIInstrInfo *TII = ST.getInstrInfo();
748 const DebugLoc &DL = I->getDebugLoc();
749 unsigned Opc = I->getOpcode();
750 bool IsDestroy = Opc == TII->getCallFrameDestroyOpcode();
751 uint64_t CalleePopAmount = IsDestroy ? I->getOperand(1).getImm() : 0;
752
753 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
754 if (!TFI->hasReservedCallFrame(MF)) {
755 unsigned Align = getStackAlignment();
756
757 Amount = alignTo(Amount, Align);
758 assert(isUInt<32>(Amount) && "exceeded stack address space size")(static_cast <bool> (isUInt<32>(Amount) &&
"exceeded stack address space size") ? void (0) : __assert_fail
("isUInt<32>(Amount) && \"exceeded stack address space size\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/AMDGPU/SIFrameLowering.cpp"
, 758, __extension__ __PRETTY_FUNCTION__))
;
759 const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
760 unsigned SPReg = MFI->getStackPtrOffsetReg();
761
762 unsigned Op = IsDestroy ? AMDGPU::S_SUB_U32 : AMDGPU::S_ADD_U32;
763 BuildMI(MBB, I, DL, TII->get(Op), SPReg)
764 .addReg(SPReg)
765 .addImm(Amount * ST.getWavefrontSize());
766 } else if (CalleePopAmount != 0) {
767 llvm_unreachable("is this used?")::llvm::llvm_unreachable_internal("is this used?", "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/AMDGPU/SIFrameLowering.cpp"
, 767)
;
768 }
769
770 return MBB.erase(I);
771}
772
773void SIFrameLowering::emitDebuggerPrologue(MachineFunction &MF,
774 MachineBasicBlock &MBB) const {
775 const SISubtarget &ST = MF.getSubtarget<SISubtarget>();
776 const SIInstrInfo *TII = ST.getInstrInfo();
777 const SIRegisterInfo *TRI = &TII->getRegisterInfo();
778 const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
779
780 MachineBasicBlock::iterator I = MBB.begin();
781 DebugLoc DL;
782
783 // For each dimension:
784 for (unsigned i = 0; i < 3; ++i) {
785 // Get work group ID SGPR, and make it live-in again.
786 unsigned WorkGroupIDSGPR = MFI->getWorkGroupIDSGPR(i);
787 MF.getRegInfo().addLiveIn(WorkGroupIDSGPR);
788 MBB.addLiveIn(WorkGroupIDSGPR);
789
790 // Since SGPRs are spilled into VGPRs, copy work group ID SGPR to VGPR in
791 // order to spill it to scratch.
792 unsigned WorkGroupIDVGPR =
793 MF.getRegInfo().createVirtualRegister(&AMDGPU::VGPR_32RegClass);
794 BuildMI(MBB, I, DL, TII->get(AMDGPU::V_MOV_B32_e32), WorkGroupIDVGPR)
795 .addReg(WorkGroupIDSGPR);
796
797 // Spill work group ID.
798 int WorkGroupIDObjectIdx = MFI->getDebuggerWorkGroupIDStackObjectIndex(i);
799 TII->storeRegToStackSlot(MBB, I, WorkGroupIDVGPR, false,
800 WorkGroupIDObjectIdx, &AMDGPU::VGPR_32RegClass, TRI);
801
802 // Get work item ID VGPR, and make it live-in again.
803 unsigned WorkItemIDVGPR = MFI->getWorkItemIDVGPR(i);
804 MF.getRegInfo().addLiveIn(WorkItemIDVGPR);
805 MBB.addLiveIn(WorkItemIDVGPR);
806
807 // Spill work item ID.
808 int WorkItemIDObjectIdx = MFI->getDebuggerWorkItemIDStackObjectIndex(i);
809 TII->storeRegToStackSlot(MBB, I, WorkItemIDVGPR, false,
810 WorkItemIDObjectIdx, &AMDGPU::VGPR_32RegClass, TRI);
811 }
812}
813
814bool SIFrameLowering::hasFP(const MachineFunction &MF) const {
815 // All stack operations are relative to the frame offset SGPR.
816 // TODO: Still want to eliminate sometimes.
817 const MachineFrameInfo &MFI = MF.getFrameInfo();
818
819 // XXX - Is this only called after frame is finalized? Should be able to check
820 // frame size.
821 return MFI.hasStackObjects() && !allStackObjectsAreDead(MFI);
822}
823
824bool SIFrameLowering::hasSP(const MachineFunction &MF) const {
825 const SIRegisterInfo *TRI = MF.getSubtarget<SISubtarget>().getRegisterInfo();
826 // All stack operations are relative to the frame offset SGPR.
827 const MachineFrameInfo &MFI = MF.getFrameInfo();
828 return MFI.hasCalls() || MFI.hasVarSizedObjects() || TRI->needsStackRealignment(MF);
829}