Bug Summary

File:lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
Warning:line 1412, column 11
Access to field 'isAvailable' results in a dereference of a null pointer (loaded from variable 'BtSU')

Annotated Source Code

1//===----- ScheduleDAGRRList.cpp - Reg pressure reduction list scheduler --===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This implements bottom-up and top-down register pressure reduction list
11// schedulers, using standard algorithms. The basic approach uses a priority
12// queue of available nodes to schedule. One at a time, nodes are taken from
13// the priority queue (thus in priority order), checked for legality to
14// schedule, and emitted if legal.
15//
16//===----------------------------------------------------------------------===//
17
18#include "llvm/CodeGen/SchedulerRegistry.h"
19#include "ScheduleDAGSDNodes.h"
20#include "llvm/ADT/STLExtras.h"
21#include "llvm/ADT/SmallSet.h"
22#include "llvm/ADT/Statistic.h"
23#include "llvm/CodeGen/MachineRegisterInfo.h"
24#include "llvm/CodeGen/ScheduleHazardRecognizer.h"
25#include "llvm/CodeGen/SelectionDAGISel.h"
26#include "llvm/IR/DataLayout.h"
27#include "llvm/IR/InlineAsm.h"
28#include "llvm/Support/Debug.h"
29#include "llvm/Support/ErrorHandling.h"
30#include "llvm/Support/raw_ostream.h"
31#include "llvm/Target/TargetInstrInfo.h"
32#include "llvm/Target/TargetLowering.h"
33#include "llvm/Target/TargetRegisterInfo.h"
34#include "llvm/Target/TargetSubtargetInfo.h"
35#include <climits>
36using namespace llvm;
37
38#define DEBUG_TYPE"pre-RA-sched" "pre-RA-sched"
39
40STATISTIC(NumBacktracks, "Number of times scheduler backtracked")static llvm::Statistic NumBacktracks = {"pre-RA-sched", "NumBacktracks"
, "Number of times scheduler backtracked", {0}, false}
;
41STATISTIC(NumUnfolds, "Number of nodes unfolded")static llvm::Statistic NumUnfolds = {"pre-RA-sched", "NumUnfolds"
, "Number of nodes unfolded", {0}, false}
;
42STATISTIC(NumDups, "Number of duplicated nodes")static llvm::Statistic NumDups = {"pre-RA-sched", "NumDups", "Number of duplicated nodes"
, {0}, false}
;
43STATISTIC(NumPRCopies, "Number of physical register copies")static llvm::Statistic NumPRCopies = {"pre-RA-sched", "NumPRCopies"
, "Number of physical register copies", {0}, false}
;
44
45static RegisterScheduler
46 burrListDAGScheduler("list-burr",
47 "Bottom-up register reduction list scheduling",
48 createBURRListDAGScheduler);
49static RegisterScheduler
50 sourceListDAGScheduler("source",
51 "Similar to list-burr but schedules in source "
52 "order when possible",
53 createSourceListDAGScheduler);
54
55static RegisterScheduler
56 hybridListDAGScheduler("list-hybrid",
57 "Bottom-up register pressure aware list scheduling "
58 "which tries to balance latency and register pressure",
59 createHybridListDAGScheduler);
60
61static RegisterScheduler
62 ILPListDAGScheduler("list-ilp",
63 "Bottom-up register pressure aware list scheduling "
64 "which tries to balance ILP and register pressure",
65 createILPListDAGScheduler);
66
67static cl::opt<bool> DisableSchedCycles(
68 "disable-sched-cycles", cl::Hidden, cl::init(false),
69 cl::desc("Disable cycle-level precision during preRA scheduling"));
70
71// Temporary sched=list-ilp flags until the heuristics are robust.
72// Some options are also available under sched=list-hybrid.
73static cl::opt<bool> DisableSchedRegPressure(
74 "disable-sched-reg-pressure", cl::Hidden, cl::init(false),
75 cl::desc("Disable regpressure priority in sched=list-ilp"));
76static cl::opt<bool> DisableSchedLiveUses(
77 "disable-sched-live-uses", cl::Hidden, cl::init(true),
78 cl::desc("Disable live use priority in sched=list-ilp"));
79static cl::opt<bool> DisableSchedVRegCycle(
80 "disable-sched-vrcycle", cl::Hidden, cl::init(false),
81 cl::desc("Disable virtual register cycle interference checks"));
82static cl::opt<bool> DisableSchedPhysRegJoin(
83 "disable-sched-physreg-join", cl::Hidden, cl::init(false),
84 cl::desc("Disable physreg def-use affinity"));
85static cl::opt<bool> DisableSchedStalls(
86 "disable-sched-stalls", cl::Hidden, cl::init(true),
87 cl::desc("Disable no-stall priority in sched=list-ilp"));
88static cl::opt<bool> DisableSchedCriticalPath(
89 "disable-sched-critical-path", cl::Hidden, cl::init(false),
90 cl::desc("Disable critical path priority in sched=list-ilp"));
91static cl::opt<bool> DisableSchedHeight(
92 "disable-sched-height", cl::Hidden, cl::init(false),
93 cl::desc("Disable scheduled-height priority in sched=list-ilp"));
94static cl::opt<bool> Disable2AddrHack(
95 "disable-2addr-hack", cl::Hidden, cl::init(true),
96 cl::desc("Disable scheduler's two-address hack"));
97
98static cl::opt<int> MaxReorderWindow(
99 "max-sched-reorder", cl::Hidden, cl::init(6),
100 cl::desc("Number of instructions to allow ahead of the critical path "
101 "in sched=list-ilp"));
102
103static cl::opt<unsigned> AvgIPC(
104 "sched-avg-ipc", cl::Hidden, cl::init(1),
105 cl::desc("Average inst/cycle whan no target itinerary exists."));
106
107namespace {
108//===----------------------------------------------------------------------===//
109/// ScheduleDAGRRList - The actual register reduction list scheduler
110/// implementation. This supports both top-down and bottom-up scheduling.
111///
112class ScheduleDAGRRList : public ScheduleDAGSDNodes {
113private:
114 /// NeedLatency - True if the scheduler will make use of latency information.
115 ///
116 bool NeedLatency;
117
118 /// AvailableQueue - The priority queue to use for the available SUnits.
119 SchedulingPriorityQueue *AvailableQueue;
120
121 /// PendingQueue - This contains all of the instructions whose operands have
122 /// been issued, but their results are not ready yet (due to the latency of
123 /// the operation). Once the operands becomes available, the instruction is
124 /// added to the AvailableQueue.
125 std::vector<SUnit*> PendingQueue;
126
127 /// HazardRec - The hazard recognizer to use.
128 ScheduleHazardRecognizer *HazardRec;
129
130 /// CurCycle - The current scheduler state corresponds to this cycle.
131 unsigned CurCycle;
132
133 /// MinAvailableCycle - Cycle of the soonest available instruction.
134 unsigned MinAvailableCycle;
135
136 /// IssueCount - Count instructions issued in this cycle
137 /// Currently valid only for bottom-up scheduling.
138 unsigned IssueCount;
139
140 /// LiveRegDefs - A set of physical registers and their definition
141 /// that are "live". These nodes must be scheduled before any other nodes that
142 /// modifies the registers can be scheduled.
143 unsigned NumLiveRegs;
144 std::unique_ptr<SUnit*[]> LiveRegDefs;
145 std::unique_ptr<SUnit*[]> LiveRegGens;
146
147 // Collect interferences between physical register use/defs.
148 // Each interference is an SUnit and set of physical registers.
149 SmallVector<SUnit*, 4> Interferences;
150 typedef DenseMap<SUnit*, SmallVector<unsigned, 4> > LRegsMapT;
151 LRegsMapT LRegsMap;
152
153 /// Topo - A topological ordering for SUnits which permits fast IsReachable
154 /// and similar queries.
155 ScheduleDAGTopologicalSort Topo;
156
157 // Hack to keep track of the inverse of FindCallSeqStart without more crazy
158 // DAG crawling.
159 DenseMap<SUnit*, SUnit*> CallSeqEndForStart;
160
161public:
162 ScheduleDAGRRList(MachineFunction &mf, bool needlatency,
163 SchedulingPriorityQueue *availqueue,
164 CodeGenOpt::Level OptLevel)
165 : ScheduleDAGSDNodes(mf),
166 NeedLatency(needlatency), AvailableQueue(availqueue), CurCycle(0),
167 Topo(SUnits, nullptr) {
168
169 const TargetSubtargetInfo &STI = mf.getSubtarget();
170 if (DisableSchedCycles || !NeedLatency)
171 HazardRec = new ScheduleHazardRecognizer();
172 else
173 HazardRec = STI.getInstrInfo()->CreateTargetHazardRecognizer(&STI, this);
174 }
175
176 ~ScheduleDAGRRList() override {
177 delete HazardRec;
178 delete AvailableQueue;
179 }
180
181 void Schedule() override;
182
183 ScheduleHazardRecognizer *getHazardRec() { return HazardRec; }
184
185 /// IsReachable - Checks if SU is reachable from TargetSU.
186 bool IsReachable(const SUnit *SU, const SUnit *TargetSU) {
187 return Topo.IsReachable(SU, TargetSU);
188 }
189
190 /// WillCreateCycle - Returns true if adding an edge from SU to TargetSU will
191 /// create a cycle.
192 bool WillCreateCycle(SUnit *SU, SUnit *TargetSU) {
193 return Topo.WillCreateCycle(SU, TargetSU);
194 }
195
196 /// AddPred - adds a predecessor edge to SUnit SU.
197 /// This returns true if this is a new predecessor.
198 /// Updates the topological ordering if required.
199 void AddPred(SUnit *SU, const SDep &D) {
200 Topo.AddPred(SU, D.getSUnit());
201 SU->addPred(D);
202 }
203
204 /// RemovePred - removes a predecessor edge from SUnit SU.
205 /// This returns true if an edge was removed.
206 /// Updates the topological ordering if required.
207 void RemovePred(SUnit *SU, const SDep &D) {
208 Topo.RemovePred(SU, D.getSUnit());
209 SU->removePred(D);
210 }
211
212private:
213 bool isReady(SUnit *SU) {
214 return DisableSchedCycles || !AvailableQueue->hasReadyFilter() ||
215 AvailableQueue->isReady(SU);
216 }
217
218 void ReleasePred(SUnit *SU, const SDep *PredEdge);
219 void ReleasePredecessors(SUnit *SU);
220 void ReleasePending();
221 void AdvanceToCycle(unsigned NextCycle);
222 void AdvancePastStalls(SUnit *SU);
223 void EmitNode(SUnit *SU);
224 void ScheduleNodeBottomUp(SUnit*);
225 void CapturePred(SDep *PredEdge);
226 void UnscheduleNodeBottomUp(SUnit*);
227 void RestoreHazardCheckerBottomUp();
228 void BacktrackBottomUp(SUnit*, SUnit*);
229 SUnit *CopyAndMoveSuccessors(SUnit*);
230 void InsertCopiesAndMoveSuccs(SUnit*, unsigned,
231 const TargetRegisterClass*,
232 const TargetRegisterClass*,
233 SmallVectorImpl<SUnit*>&);
234 bool DelayForLiveRegsBottomUp(SUnit*, SmallVectorImpl<unsigned>&);
235
236 void releaseInterferences(unsigned Reg = 0);
237
238 SUnit *PickNodeToScheduleBottomUp();
239 void ListScheduleBottomUp();
240
241 /// CreateNewSUnit - Creates a new SUnit and returns a pointer to it.
242 /// Updates the topological ordering if required.
243 SUnit *CreateNewSUnit(SDNode *N) {
244 unsigned NumSUnits = SUnits.size();
245 SUnit *NewNode = newSUnit(N);
246 // Update the topological ordering.
247 if (NewNode->NodeNum >= NumSUnits)
248 Topo.InitDAGTopologicalSorting();
249 return NewNode;
250 }
251
252 /// CreateClone - Creates a new SUnit from an existing one.
253 /// Updates the topological ordering if required.
254 SUnit *CreateClone(SUnit *N) {
255 unsigned NumSUnits = SUnits.size();
256 SUnit *NewNode = Clone(N);
257 // Update the topological ordering.
258 if (NewNode->NodeNum >= NumSUnits)
259 Topo.InitDAGTopologicalSorting();
260 return NewNode;
261 }
262
263 /// forceUnitLatencies - Register-pressure-reducing scheduling doesn't
264 /// need actual latency information but the hybrid scheduler does.
265 bool forceUnitLatencies() const override {
266 return !NeedLatency;
267 }
268};
269} // end anonymous namespace
270
271/// GetCostForDef - Looks up the register class and cost for a given definition.
272/// Typically this just means looking up the representative register class,
273/// but for untyped values (MVT::Untyped) it means inspecting the node's
274/// opcode to determine what register class is being generated.
275static void GetCostForDef(const ScheduleDAGSDNodes::RegDefIter &RegDefPos,
276 const TargetLowering *TLI,
277 const TargetInstrInfo *TII,
278 const TargetRegisterInfo *TRI,
279 unsigned &RegClass, unsigned &Cost,
280 const MachineFunction &MF) {
281 MVT VT = RegDefPos.GetValue();
282
283 // Special handling for untyped values. These values can only come from
284 // the expansion of custom DAG-to-DAG patterns.
285 if (VT == MVT::Untyped) {
286 const SDNode *Node = RegDefPos.GetNode();
287
288 // Special handling for CopyFromReg of untyped values.
289 if (!Node->isMachineOpcode() && Node->getOpcode() == ISD::CopyFromReg) {
290 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
291 const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(Reg);
292 RegClass = RC->getID();
293 Cost = 1;
294 return;
295 }
296
297 unsigned Opcode = Node->getMachineOpcode();
298 if (Opcode == TargetOpcode::REG_SEQUENCE) {
299 unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue();
300 const TargetRegisterClass *RC = TRI->getRegClass(DstRCIdx);
301 RegClass = RC->getID();
302 Cost = 1;
303 return;
304 }
305
306 unsigned Idx = RegDefPos.GetIdx();
307 const MCInstrDesc Desc = TII->get(Opcode);
308 const TargetRegisterClass *RC = TII->getRegClass(Desc, Idx, TRI, MF);
309 RegClass = RC->getID();
310 // FIXME: Cost arbitrarily set to 1 because there doesn't seem to be a
311 // better way to determine it.
312 Cost = 1;
313 } else {
314 RegClass = TLI->getRepRegClassFor(VT)->getID();
315 Cost = TLI->getRepRegClassCostFor(VT);
316 }
317}
318
319/// Schedule - Schedule the DAG using list scheduling.
320void ScheduleDAGRRList::Schedule() {
321 DEBUG(dbgs()do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("pre-RA-sched")) { dbgs() << "********** List Scheduling BB#"
<< BB->getNumber() << " '" << BB->getName
() << "' **********\n"; } } while (false)
322 << "********** List Scheduling BB#" << BB->getNumber()do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("pre-RA-sched")) { dbgs() << "********** List Scheduling BB#"
<< BB->getNumber() << " '" << BB->getName
() << "' **********\n"; } } while (false)
323 << " '" << BB->getName() << "' **********\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("pre-RA-sched")) { dbgs() << "********** List Scheduling BB#"
<< BB->getNumber() << " '" << BB->getName
() << "' **********\n"; } } while (false)
;
324
325 CurCycle = 0;
326 IssueCount = 0;
327 MinAvailableCycle = DisableSchedCycles ? 0 : UINT_MAX(2147483647 *2U +1U);
328 NumLiveRegs = 0;
329 // Allocate slots for each physical register, plus one for a special register
330 // to track the virtual resource of a calling sequence.
331 LiveRegDefs.reset(new SUnit*[TRI->getNumRegs() + 1]());
332 LiveRegGens.reset(new SUnit*[TRI->getNumRegs() + 1]());
333 CallSeqEndForStart.clear();
334 assert(Interferences.empty() && LRegsMap.empty() && "stale Interferences")((Interferences.empty() && LRegsMap.empty() &&
"stale Interferences") ? static_cast<void> (0) : __assert_fail
("Interferences.empty() && LRegsMap.empty() && \"stale Interferences\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp"
, 334, __PRETTY_FUNCTION__))
;
335
336 // Build the scheduling graph.
337 BuildSchedGraph(nullptr);
338
339 DEBUG(for (SUnit &SU : SUnits)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("pre-RA-sched")) { for (SUnit &SU : SUnits) SU.dumpAll(this
); } } while (false)
340 SU.dumpAll(this))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("pre-RA-sched")) { for (SUnit &SU : SUnits) SU.dumpAll(this
); } } while (false)
;
341 Topo.InitDAGTopologicalSorting();
342
343 AvailableQueue->initNodes(SUnits);
344
345 HazardRec->Reset();
346
347 // Execute the actual scheduling loop.
348 ListScheduleBottomUp();
349
350 AvailableQueue->releaseState();
351
352 DEBUG({do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("pre-RA-sched")) { { dbgs() << "*** Final schedule ***\n"
; dumpSchedule(); dbgs() << '\n'; }; } } while (false)
353 dbgs() << "*** Final schedule ***\n";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("pre-RA-sched")) { { dbgs() << "*** Final schedule ***\n"
; dumpSchedule(); dbgs() << '\n'; }; } } while (false)
354 dumpSchedule();do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("pre-RA-sched")) { { dbgs() << "*** Final schedule ***\n"
; dumpSchedule(); dbgs() << '\n'; }; } } while (false)
355 dbgs() << '\n';do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("pre-RA-sched")) { { dbgs() << "*** Final schedule ***\n"
; dumpSchedule(); dbgs() << '\n'; }; } } while (false)
356 })do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("pre-RA-sched")) { { dbgs() << "*** Final schedule ***\n"
; dumpSchedule(); dbgs() << '\n'; }; } } while (false)
;
357}
358
359//===----------------------------------------------------------------------===//
360// Bottom-Up Scheduling
361//===----------------------------------------------------------------------===//
362
363/// ReleasePred - Decrement the NumSuccsLeft count of a predecessor. Add it to
364/// the AvailableQueue if the count reaches zero. Also update its cycle bound.
365void ScheduleDAGRRList::ReleasePred(SUnit *SU, const SDep *PredEdge) {
366 SUnit *PredSU = PredEdge->getSUnit();
367
368#ifndef NDEBUG
369 if (PredSU->NumSuccsLeft == 0) {
370 dbgs() << "*** Scheduling failed! ***\n";
371 PredSU->dump(this);
372 dbgs() << " has been released too many times!\n";
373 llvm_unreachable(nullptr)::llvm::llvm_unreachable_internal(nullptr, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp"
, 373)
;
374 }
375#endif
376 --PredSU->NumSuccsLeft;
377
378 if (!forceUnitLatencies()) {
379 // Updating predecessor's height. This is now the cycle when the
380 // predecessor can be scheduled without causing a pipeline stall.
381 PredSU->setHeightToAtLeast(SU->getHeight() + PredEdge->getLatency());
382 }
383
384 // If all the node's successors are scheduled, this node is ready
385 // to be scheduled. Ignore the special EntrySU node.
386 if (PredSU->NumSuccsLeft == 0 && PredSU != &EntrySU) {
387 PredSU->isAvailable = true;
388
389 unsigned Height = PredSU->getHeight();
390 if (Height < MinAvailableCycle)
391 MinAvailableCycle = Height;
392
393 if (isReady(PredSU)) {
394 AvailableQueue->push(PredSU);
395 }
396 // CapturePred and others may have left the node in the pending queue, avoid
397 // adding it twice.
398 else if (!PredSU->isPending) {
399 PredSU->isPending = true;
400 PendingQueue.push_back(PredSU);
401 }
402 }
403}
404
405/// IsChainDependent - Test if Outer is reachable from Inner through
406/// chain dependencies.
407static bool IsChainDependent(SDNode *Outer, SDNode *Inner,
408 unsigned NestLevel,
409 const TargetInstrInfo *TII) {
410 SDNode *N = Outer;
411 for (;;) {
412 if (N == Inner)
413 return true;
414 // For a TokenFactor, examine each operand. There may be multiple ways
415 // to get to the CALLSEQ_BEGIN, but we need to find the path with the
416 // most nesting in order to ensure that we find the corresponding match.
417 if (N->getOpcode() == ISD::TokenFactor) {
418 for (const SDValue &Op : N->op_values())
419 if (IsChainDependent(Op.getNode(), Inner, NestLevel, TII))
420 return true;
421 return false;
422 }
423 // Check for a lowered CALLSEQ_BEGIN or CALLSEQ_END.
424 if (N->isMachineOpcode()) {
425 if (N->getMachineOpcode() ==
426 (unsigned)TII->getCallFrameDestroyOpcode()) {
427 ++NestLevel;
428 } else if (N->getMachineOpcode() ==
429 (unsigned)TII->getCallFrameSetupOpcode()) {
430 if (NestLevel == 0)
431 return false;
432 --NestLevel;
433 }
434 }
435 // Otherwise, find the chain and continue climbing.
436 for (const SDValue &Op : N->op_values())
437 if (Op.getValueType() == MVT::Other) {
438 N = Op.getNode();
439 goto found_chain_operand;
440 }
441 return false;
442 found_chain_operand:;
443 if (N->getOpcode() == ISD::EntryToken)
444 return false;
445 }
446}
447
448/// FindCallSeqStart - Starting from the (lowered) CALLSEQ_END node, locate
449/// the corresponding (lowered) CALLSEQ_BEGIN node.
450///
451/// NestLevel and MaxNested are used in recursion to indcate the current level
452/// of nesting of CALLSEQ_BEGIN and CALLSEQ_END pairs, as well as the maximum
453/// level seen so far.
454///
455/// TODO: It would be better to give CALLSEQ_END an explicit operand to point
456/// to the corresponding CALLSEQ_BEGIN to avoid needing to search for it.
457static SDNode *
458FindCallSeqStart(SDNode *N, unsigned &NestLevel, unsigned &MaxNest,
459 const TargetInstrInfo *TII) {
460 for (;;) {
461 // For a TokenFactor, examine each operand. There may be multiple ways
462 // to get to the CALLSEQ_BEGIN, but we need to find the path with the
463 // most nesting in order to ensure that we find the corresponding match.
464 if (N->getOpcode() == ISD::TokenFactor) {
465 SDNode *Best = nullptr;
466 unsigned BestMaxNest = MaxNest;
467 for (const SDValue &Op : N->op_values()) {
468 unsigned MyNestLevel = NestLevel;
469 unsigned MyMaxNest = MaxNest;
470 if (SDNode *New = FindCallSeqStart(Op.getNode(),
471 MyNestLevel, MyMaxNest, TII))
472 if (!Best || (MyMaxNest > BestMaxNest)) {
473 Best = New;
474 BestMaxNest = MyMaxNest;
475 }
476 }
477 assert(Best)((Best) ? static_cast<void> (0) : __assert_fail ("Best"
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp"
, 477, __PRETTY_FUNCTION__))
;
478 MaxNest = BestMaxNest;
479 return Best;
480 }
481 // Check for a lowered CALLSEQ_BEGIN or CALLSEQ_END.
482 if (N->isMachineOpcode()) {
483 if (N->getMachineOpcode() ==
484 (unsigned)TII->getCallFrameDestroyOpcode()) {
485 ++NestLevel;
486 MaxNest = std::max(MaxNest, NestLevel);
487 } else if (N->getMachineOpcode() ==
488 (unsigned)TII->getCallFrameSetupOpcode()) {
489 assert(NestLevel != 0)((NestLevel != 0) ? static_cast<void> (0) : __assert_fail
("NestLevel != 0", "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp"
, 489, __PRETTY_FUNCTION__))
;
490 --NestLevel;
491 if (NestLevel == 0)
492 return N;
493 }
494 }
495 // Otherwise, find the chain and continue climbing.
496 for (const SDValue &Op : N->op_values())
497 if (Op.getValueType() == MVT::Other) {
498 N = Op.getNode();
499 goto found_chain_operand;
500 }
501 return nullptr;
502 found_chain_operand:;
503 if (N->getOpcode() == ISD::EntryToken)
504 return nullptr;
505 }
506}
507
508/// Call ReleasePred for each predecessor, then update register live def/gen.
509/// Always update LiveRegDefs for a register dependence even if the current SU
510/// also defines the register. This effectively create one large live range
511/// across a sequence of two-address node. This is important because the
512/// entire chain must be scheduled together. Example:
513///
514/// flags = (3) add
515/// flags = (2) addc flags
516/// flags = (1) addc flags
517///
518/// results in
519///
520/// LiveRegDefs[flags] = 3
521/// LiveRegGens[flags] = 1
522///
523/// If (2) addc is unscheduled, then (1) addc must also be unscheduled to avoid
524/// interference on flags.
525void ScheduleDAGRRList::ReleasePredecessors(SUnit *SU) {
526 // Bottom up: release predecessors
527 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
528 I != E; ++I) {
529 ReleasePred(SU, &*I);
530 if (I->isAssignedRegDep()) {
531 // This is a physical register dependency and it's impossible or
532 // expensive to copy the register. Make sure nothing that can
533 // clobber the register is scheduled between the predecessor and
534 // this node.
535 SUnit *RegDef = LiveRegDefs[I->getReg()]; (void)RegDef;
536 assert((!RegDef || RegDef == SU || RegDef == I->getSUnit()) &&(((!RegDef || RegDef == SU || RegDef == I->getSUnit()) &&
"interference on register dependence") ? static_cast<void
> (0) : __assert_fail ("(!RegDef || RegDef == SU || RegDef == I->getSUnit()) && \"interference on register dependence\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp"
, 537, __PRETTY_FUNCTION__))
537 "interference on register dependence")(((!RegDef || RegDef == SU || RegDef == I->getSUnit()) &&
"interference on register dependence") ? static_cast<void
> (0) : __assert_fail ("(!RegDef || RegDef == SU || RegDef == I->getSUnit()) && \"interference on register dependence\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp"
, 537, __PRETTY_FUNCTION__))
;
538 LiveRegDefs[I->getReg()] = I->getSUnit();
539 if (!LiveRegGens[I->getReg()]) {
540 ++NumLiveRegs;
541 LiveRegGens[I->getReg()] = SU;
542 }
543 }
544 }
545
546 // If we're scheduling a lowered CALLSEQ_END, find the corresponding
547 // CALLSEQ_BEGIN. Inject an artificial physical register dependence between
548 // these nodes, to prevent other calls from being interscheduled with them.
549 unsigned CallResource = TRI->getNumRegs();
550 if (!LiveRegDefs[CallResource])
551 for (SDNode *Node = SU->getNode(); Node; Node = Node->getGluedNode())
552 if (Node->isMachineOpcode() &&
553 Node->getMachineOpcode() == (unsigned)TII->getCallFrameDestroyOpcode()) {
554 unsigned NestLevel = 0;
555 unsigned MaxNest = 0;
556 SDNode *N = FindCallSeqStart(Node, NestLevel, MaxNest, TII);
557
558 SUnit *Def = &SUnits[N->getNodeId()];
559 CallSeqEndForStart[Def] = SU;
560
561 ++NumLiveRegs;
562 LiveRegDefs[CallResource] = Def;
563 LiveRegGens[CallResource] = SU;
564 break;
565 }
566}
567
568/// Check to see if any of the pending instructions are ready to issue. If
569/// so, add them to the available queue.
570void ScheduleDAGRRList::ReleasePending() {
571 if (DisableSchedCycles) {
572 assert(PendingQueue.empty() && "pending instrs not allowed in this mode")((PendingQueue.empty() && "pending instrs not allowed in this mode"
) ? static_cast<void> (0) : __assert_fail ("PendingQueue.empty() && \"pending instrs not allowed in this mode\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp"
, 572, __PRETTY_FUNCTION__))
;
573 return;
574 }
575
576 // If the available queue is empty, it is safe to reset MinAvailableCycle.
577 if (AvailableQueue->empty())
578 MinAvailableCycle = UINT_MAX(2147483647 *2U +1U);
579
580 // Check to see if any of the pending instructions are ready to issue. If
581 // so, add them to the available queue.
582 for (unsigned i = 0, e = PendingQueue.size(); i != e; ++i) {
583 unsigned ReadyCycle = PendingQueue[i]->getHeight();
584 if (ReadyCycle < MinAvailableCycle)
585 MinAvailableCycle = ReadyCycle;
586
587 if (PendingQueue[i]->isAvailable) {
588 if (!isReady(PendingQueue[i]))
589 continue;
590 AvailableQueue->push(PendingQueue[i]);
591 }
592 PendingQueue[i]->isPending = false;
593 PendingQueue[i] = PendingQueue.back();
594 PendingQueue.pop_back();
595 --i; --e;
596 }
597}
598
599/// Move the scheduler state forward by the specified number of Cycles.
600void ScheduleDAGRRList::AdvanceToCycle(unsigned NextCycle) {
601 if (NextCycle <= CurCycle)
602 return;
603
604 IssueCount = 0;
605 AvailableQueue->setCurCycle(NextCycle);
606 if (!HazardRec->isEnabled()) {
607 // Bypass lots of virtual calls in case of long latency.
608 CurCycle = NextCycle;
609 }
610 else {
611 for (; CurCycle != NextCycle; ++CurCycle) {
612 HazardRec->RecedeCycle();
613 }
614 }
615 // FIXME: Instead of visiting the pending Q each time, set a dirty flag on the
616 // available Q to release pending nodes at least once before popping.
617 ReleasePending();
618}
619
620/// Move the scheduler state forward until the specified node's dependents are
621/// ready and can be scheduled with no resource conflicts.
622void ScheduleDAGRRList::AdvancePastStalls(SUnit *SU) {
623 if (DisableSchedCycles)
624 return;
625
626 // FIXME: Nodes such as CopyFromReg probably should not advance the current
627 // cycle. Otherwise, we can wrongly mask real stalls. If the non-machine node
628 // has predecessors the cycle will be advanced when they are scheduled.
629 // But given the crude nature of modeling latency though such nodes, we
630 // currently need to treat these nodes like real instructions.
631 // if (!SU->getNode() || !SU->getNode()->isMachineOpcode()) return;
632
633 unsigned ReadyCycle = SU->getHeight();
634
635 // Bump CurCycle to account for latency. We assume the latency of other
636 // available instructions may be hidden by the stall (not a full pipe stall).
637 // This updates the hazard recognizer's cycle before reserving resources for
638 // this instruction.
639 AdvanceToCycle(ReadyCycle);
640
641 // Calls are scheduled in their preceding cycle, so don't conflict with
642 // hazards from instructions after the call. EmitNode will reset the
643 // scoreboard state before emitting the call.
644 if (SU->isCall)
645 return;
646
647 // FIXME: For resource conflicts in very long non-pipelined stages, we
648 // should probably skip ahead here to avoid useless scoreboard checks.
649 int Stalls = 0;
650 while (true) {
651 ScheduleHazardRecognizer::HazardType HT =
652 HazardRec->getHazardType(SU, -Stalls);
653
654 if (HT == ScheduleHazardRecognizer::NoHazard)
655 break;
656
657 ++Stalls;
658 }
659 AdvanceToCycle(CurCycle + Stalls);
660}
661
662/// Record this SUnit in the HazardRecognizer.
663/// Does not update CurCycle.
664void ScheduleDAGRRList::EmitNode(SUnit *SU) {
665 if (!HazardRec->isEnabled())
666 return;
667
668 // Check for phys reg copy.
669 if (!SU->getNode())
670 return;
671
672 switch (SU->getNode()->getOpcode()) {
673 default:
674 assert(SU->getNode()->isMachineOpcode() &&((SU->getNode()->isMachineOpcode() && "This target-independent node should not be scheduled."
) ? static_cast<void> (0) : __assert_fail ("SU->getNode()->isMachineOpcode() && \"This target-independent node should not be scheduled.\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp"
, 675, __PRETTY_FUNCTION__))
675 "This target-independent node should not be scheduled.")((SU->getNode()->isMachineOpcode() && "This target-independent node should not be scheduled."
) ? static_cast<void> (0) : __assert_fail ("SU->getNode()->isMachineOpcode() && \"This target-independent node should not be scheduled.\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp"
, 675, __PRETTY_FUNCTION__))
;
676 break;
677 case ISD::MERGE_VALUES:
678 case ISD::TokenFactor:
679 case ISD::LIFETIME_START:
680 case ISD::LIFETIME_END:
681 case ISD::CopyToReg:
682 case ISD::CopyFromReg:
683 case ISD::EH_LABEL:
684 // Noops don't affect the scoreboard state. Copies are likely to be
685 // removed.
686 return;
687 case ISD::INLINEASM:
688 // For inline asm, clear the pipeline state.
689 HazardRec->Reset();
690 return;
691 }
692 if (SU->isCall) {
693 // Calls are scheduled with their preceding instructions. For bottom-up
694 // scheduling, clear the pipeline state before emitting.
695 HazardRec->Reset();
696 }
697
698 HazardRec->EmitInstruction(SU);
699}
700
701static void resetVRegCycle(SUnit *SU);
702
703/// ScheduleNodeBottomUp - Add the node to the schedule. Decrement the pending
704/// count of its predecessors. If a predecessor pending count is zero, add it to
705/// the Available queue.
706void ScheduleDAGRRList::ScheduleNodeBottomUp(SUnit *SU) {
707 DEBUG(dbgs() << "\n*** Scheduling [" << CurCycle << "]: ")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("pre-RA-sched")) { dbgs() << "\n*** Scheduling [" <<
CurCycle << "]: "; } } while (false)
;
708 DEBUG(SU->dump(this))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("pre-RA-sched")) { SU->dump(this); } } while (false)
;
709
710#ifndef NDEBUG
711 if (CurCycle < SU->getHeight())
712 DEBUG(dbgs() << " Height [" << SU->getHeight()do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("pre-RA-sched")) { dbgs() << " Height [" << SU
->getHeight() << "] pipeline stall!\n"; } } while (false
)
713 << "] pipeline stall!\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("pre-RA-sched")) { dbgs() << " Height [" << SU
->getHeight() << "] pipeline stall!\n"; } } while (false
)
;
714#endif
715
716 // FIXME: Do not modify node height. It may interfere with
717 // backtracking. Instead add a "ready cycle" to SUnit. Before scheduling the
718 // node its ready cycle can aid heuristics, and after scheduling it can
719 // indicate the scheduled cycle.
720 SU->setHeightToAtLeast(CurCycle);
721
722 // Reserve resources for the scheduled instruction.
723 EmitNode(SU);
724
725 Sequence.push_back(SU);
726
727 AvailableQueue->scheduledNode(SU);
728
729 // If HazardRec is disabled, and each inst counts as one cycle, then
730 // advance CurCycle before ReleasePredecessors to avoid useless pushes to
731 // PendingQueue for schedulers that implement HasReadyFilter.
732 if (!HazardRec->isEnabled() && AvgIPC < 2)
733 AdvanceToCycle(CurCycle + 1);
734
735 // Update liveness of predecessors before successors to avoid treating a
736 // two-address node as a live range def.
737 ReleasePredecessors(SU);
738
739 // Release all the implicit physical register defs that are live.
740 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
741 I != E; ++I) {
742 // LiveRegDegs[I->getReg()] != SU when SU is a two-address node.
743 if (I->isAssignedRegDep() && LiveRegDefs[I->getReg()] == SU) {
744 assert(NumLiveRegs > 0 && "NumLiveRegs is already zero!")((NumLiveRegs > 0 && "NumLiveRegs is already zero!"
) ? static_cast<void> (0) : __assert_fail ("NumLiveRegs > 0 && \"NumLiveRegs is already zero!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp"
, 744, __PRETTY_FUNCTION__))
;
745 --NumLiveRegs;
746 LiveRegDefs[I->getReg()] = nullptr;
747 LiveRegGens[I->getReg()] = nullptr;
748 releaseInterferences(I->getReg());
749 }
750 }
751 // Release the special call resource dependence, if this is the beginning
752 // of a call.
753 unsigned CallResource = TRI->getNumRegs();
754 if (LiveRegDefs[CallResource] == SU)
755 for (const SDNode *SUNode = SU->getNode(); SUNode;
756 SUNode = SUNode->getGluedNode()) {
757 if (SUNode->isMachineOpcode() &&
758 SUNode->getMachineOpcode() == (unsigned)TII->getCallFrameSetupOpcode()) {
759 assert(NumLiveRegs > 0 && "NumLiveRegs is already zero!")((NumLiveRegs > 0 && "NumLiveRegs is already zero!"
) ? static_cast<void> (0) : __assert_fail ("NumLiveRegs > 0 && \"NumLiveRegs is already zero!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp"
, 759, __PRETTY_FUNCTION__))
;
760 --NumLiveRegs;
761 LiveRegDefs[CallResource] = nullptr;
762 LiveRegGens[CallResource] = nullptr;
763 releaseInterferences(CallResource);
764 }
765 }
766
767 resetVRegCycle(SU);
768
769 SU->isScheduled = true;
770
771 // Conditions under which the scheduler should eagerly advance the cycle:
772 // (1) No available instructions
773 // (2) All pipelines full, so available instructions must have hazards.
774 //
775 // If HazardRec is disabled, the cycle was pre-advanced before calling
776 // ReleasePredecessors. In that case, IssueCount should remain 0.
777 //
778 // Check AvailableQueue after ReleasePredecessors in case of zero latency.
779 if (HazardRec->isEnabled() || AvgIPC > 1) {
780 if (SU->getNode() && SU->getNode()->isMachineOpcode())
781 ++IssueCount;
782 if ((HazardRec->isEnabled() && HazardRec->atIssueLimit())
783 || (!HazardRec->isEnabled() && IssueCount == AvgIPC))
784 AdvanceToCycle(CurCycle + 1);
785 }
786}
787
788/// CapturePred - This does the opposite of ReleasePred. Since SU is being
789/// unscheduled, incrcease the succ left count of its predecessors. Remove
790/// them from AvailableQueue if necessary.
791void ScheduleDAGRRList::CapturePred(SDep *PredEdge) {
792 SUnit *PredSU = PredEdge->getSUnit();
793 if (PredSU->isAvailable) {
794 PredSU->isAvailable = false;
795 if (!PredSU->isPending)
796 AvailableQueue->remove(PredSU);
797 }
798
799 assert(PredSU->NumSuccsLeft < UINT_MAX && "NumSuccsLeft will overflow!")((PredSU->NumSuccsLeft < (2147483647 *2U +1U) &&
"NumSuccsLeft will overflow!") ? static_cast<void> (0)
: __assert_fail ("PredSU->NumSuccsLeft < UINT_MAX && \"NumSuccsLeft will overflow!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp"
, 799, __PRETTY_FUNCTION__))
;
800 ++PredSU->NumSuccsLeft;
801}
802
803/// UnscheduleNodeBottomUp - Remove the node from the schedule, update its and
804/// its predecessor states to reflect the change.
805void ScheduleDAGRRList::UnscheduleNodeBottomUp(SUnit *SU) {
806 DEBUG(dbgs() << "*** Unscheduling [" << SU->getHeight() << "]: ")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("pre-RA-sched")) { dbgs() << "*** Unscheduling [" <<
SU->getHeight() << "]: "; } } while (false)
;
807 DEBUG(SU->dump(this))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("pre-RA-sched")) { SU->dump(this); } } while (false)
;
808
809 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
810 I != E; ++I) {
811 CapturePred(&*I);
812 if (I->isAssignedRegDep() && SU == LiveRegGens[I->getReg()]){
813 assert(NumLiveRegs > 0 && "NumLiveRegs is already zero!")((NumLiveRegs > 0 && "NumLiveRegs is already zero!"
) ? static_cast<void> (0) : __assert_fail ("NumLiveRegs > 0 && \"NumLiveRegs is already zero!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp"
, 813, __PRETTY_FUNCTION__))
;
814 assert(LiveRegDefs[I->getReg()] == I->getSUnit() &&((LiveRegDefs[I->getReg()] == I->getSUnit() && "Physical register dependency violated?"
) ? static_cast<void> (0) : __assert_fail ("LiveRegDefs[I->getReg()] == I->getSUnit() && \"Physical register dependency violated?\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp"
, 815, __PRETTY_FUNCTION__))
815 "Physical register dependency violated?")((LiveRegDefs[I->getReg()] == I->getSUnit() && "Physical register dependency violated?"
) ? static_cast<void> (0) : __assert_fail ("LiveRegDefs[I->getReg()] == I->getSUnit() && \"Physical register dependency violated?\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp"
, 815, __PRETTY_FUNCTION__))
;
816 --NumLiveRegs;
817 LiveRegDefs[I->getReg()] = nullptr;
818 LiveRegGens[I->getReg()] = nullptr;
819 releaseInterferences(I->getReg());
820 }
821 }
822
823 // Reclaim the special call resource dependence, if this is the beginning
824 // of a call.
825 unsigned CallResource = TRI->getNumRegs();
826 for (const SDNode *SUNode = SU->getNode(); SUNode;
827 SUNode = SUNode->getGluedNode()) {
828 if (SUNode->isMachineOpcode() &&
829 SUNode->getMachineOpcode() == (unsigned)TII->getCallFrameSetupOpcode()) {
830 ++NumLiveRegs;
831 LiveRegDefs[CallResource] = SU;
832 LiveRegGens[CallResource] = CallSeqEndForStart[SU];
833 }
834 }
835
836 // Release the special call resource dependence, if this is the end
837 // of a call.
838 if (LiveRegGens[CallResource] == SU)
839 for (const SDNode *SUNode = SU->getNode(); SUNode;
840 SUNode = SUNode->getGluedNode()) {
841 if (SUNode->isMachineOpcode() &&
842 SUNode->getMachineOpcode() == (unsigned)TII->getCallFrameDestroyOpcode()) {
843 assert(NumLiveRegs > 0 && "NumLiveRegs is already zero!")((NumLiveRegs > 0 && "NumLiveRegs is already zero!"
) ? static_cast<void> (0) : __assert_fail ("NumLiveRegs > 0 && \"NumLiveRegs is already zero!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp"
, 843, __PRETTY_FUNCTION__))
;
844 --NumLiveRegs;
845 LiveRegDefs[CallResource] = nullptr;
846 LiveRegGens[CallResource] = nullptr;
847 releaseInterferences(CallResource);
848 }
849 }
850
851 for (auto &Succ : SU->Succs) {
852 if (Succ.isAssignedRegDep()) {
853 auto Reg = Succ.getReg();
854 if (!LiveRegDefs[Reg])
855 ++NumLiveRegs;
856 // This becomes the nearest def. Note that an earlier def may still be
857 // pending if this is a two-address node.
858 LiveRegDefs[Reg] = SU;
859
860 // Update LiveRegGen only if was empty before this unscheduling.
861 // This is to avoid incorrect updating LiveRegGen set in previous run.
862 if (!LiveRegGens[Reg]) {
863 // Find the successor with the lowest height.
864 LiveRegGens[Reg] = Succ.getSUnit();
865 for (auto &Succ2 : SU->Succs) {
866 if (Succ2.isAssignedRegDep() && Succ2.getReg() == Reg &&
867 Succ2.getSUnit()->getHeight() < LiveRegGens[Reg]->getHeight())
868 LiveRegGens[Reg] = Succ2.getSUnit();
869 }
870 }
871 }
872 }
873 if (SU->getHeight() < MinAvailableCycle)
874 MinAvailableCycle = SU->getHeight();
875
876 SU->setHeightDirty();
877 SU->isScheduled = false;
878 SU->isAvailable = true;
879 if (!DisableSchedCycles && AvailableQueue->hasReadyFilter()) {
880 // Don't make available until backtracking is complete.
881 SU->isPending = true;
882 PendingQueue.push_back(SU);
883 }
884 else {
885 AvailableQueue->push(SU);
886 }
887 AvailableQueue->unscheduledNode(SU);
888}
889
890/// After backtracking, the hazard checker needs to be restored to a state
891/// corresponding the current cycle.
892void ScheduleDAGRRList::RestoreHazardCheckerBottomUp() {
893 HazardRec->Reset();
894
895 unsigned LookAhead = std::min((unsigned)Sequence.size(),
896 HazardRec->getMaxLookAhead());
897 if (LookAhead == 0)
898 return;
899
900 std::vector<SUnit*>::const_iterator I = (Sequence.end() - LookAhead);
901 unsigned HazardCycle = (*I)->getHeight();
902 for (std::vector<SUnit*>::const_iterator E = Sequence.end(); I != E; ++I) {
903 SUnit *SU = *I;
904 for (; SU->getHeight() > HazardCycle; ++HazardCycle) {
905 HazardRec->RecedeCycle();
906 }
907 EmitNode(SU);
908 }
909}
910
911/// BacktrackBottomUp - Backtrack scheduling to a previous cycle specified in
912/// BTCycle in order to schedule a specific node.
913void ScheduleDAGRRList::BacktrackBottomUp(SUnit *SU, SUnit *BtSU) {
914 SUnit *OldSU = Sequence.back();
915 while (true) {
916 Sequence.pop_back();
917 // FIXME: use ready cycle instead of height
918 CurCycle = OldSU->getHeight();
919 UnscheduleNodeBottomUp(OldSU);
920 AvailableQueue->setCurCycle(CurCycle);
921 if (OldSU == BtSU)
922 break;
923 OldSU = Sequence.back();
924 }
925
926 assert(!SU->isSucc(OldSU) && "Something is wrong!")((!SU->isSucc(OldSU) && "Something is wrong!") ? static_cast
<void> (0) : __assert_fail ("!SU->isSucc(OldSU) && \"Something is wrong!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp"
, 926, __PRETTY_FUNCTION__))
;
927
928 RestoreHazardCheckerBottomUp();
929
930 ReleasePending();
931
932 ++NumBacktracks;
933}
934
935static bool isOperandOf(const SUnit *SU, SDNode *N) {
936 for (const SDNode *SUNode = SU->getNode(); SUNode;
937 SUNode = SUNode->getGluedNode()) {
938 if (SUNode->isOperandOf(N))
939 return true;
940 }
941 return false;
942}
943
944/// CopyAndMoveSuccessors - Clone the specified node and move its scheduled
945/// successors to the newly created node.
946SUnit *ScheduleDAGRRList::CopyAndMoveSuccessors(SUnit *SU) {
947 SDNode *N = SU->getNode();
948 if (!N)
949 return nullptr;
950
951 if (SU->getNode()->getGluedNode())
952 return nullptr;
953
954 SUnit *NewSU;
955 bool TryUnfold = false;
956 for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
957 MVT VT = N->getSimpleValueType(i);
958 if (VT == MVT::Glue)
959 return nullptr;
960 else if (VT == MVT::Other)
961 TryUnfold = true;
962 }
963 for (const SDValue &Op : N->op_values()) {
964 MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo());
965 if (VT == MVT::Glue)
966 return nullptr;
967 }
968
969 if (TryUnfold) {
970 SmallVector<SDNode*, 2> NewNodes;
971 if (!TII->unfoldMemoryOperand(*DAG, N, NewNodes))
972 return nullptr;
973
974 // unfolding an x86 DEC64m operation results in store, dec, load which
975 // can't be handled here so quit
976 if (NewNodes.size() == 3)
977 return nullptr;
978
979 DEBUG(dbgs() << "Unfolding SU #" << SU->NodeNum << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("pre-RA-sched")) { dbgs() << "Unfolding SU #" <<
SU->NodeNum << "\n"; } } while (false)
;
980 assert(NewNodes.size() == 2 && "Expected a load folding node!")((NewNodes.size() == 2 && "Expected a load folding node!"
) ? static_cast<void> (0) : __assert_fail ("NewNodes.size() == 2 && \"Expected a load folding node!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp"
, 980, __PRETTY_FUNCTION__))
;
981
982 N = NewNodes[1];
983 SDNode *LoadNode = NewNodes[0];
984 unsigned NumVals = N->getNumValues();
985 unsigned OldNumVals = SU->getNode()->getNumValues();
986 for (unsigned i = 0; i != NumVals; ++i)
987 DAG->ReplaceAllUsesOfValueWith(SDValue(SU->getNode(), i), SDValue(N, i));
988 DAG->ReplaceAllUsesOfValueWith(SDValue(SU->getNode(), OldNumVals-1),
989 SDValue(LoadNode, 1));
990
991 // LoadNode may already exist. This can happen when there is another
992 // load from the same location and producing the same type of value
993 // but it has different alignment or volatileness.
994 bool isNewLoad = true;
995 SUnit *LoadSU;
996 if (LoadNode->getNodeId() != -1) {
997 LoadSU = &SUnits[LoadNode->getNodeId()];
998 isNewLoad = false;
999 } else {
1000 LoadSU = CreateNewSUnit(LoadNode);
1001 LoadNode->setNodeId(LoadSU->NodeNum);
1002
1003 InitNumRegDefsLeft(LoadSU);
1004 computeLatency(LoadSU);
1005 }
1006
1007 SUnit *NewSU = CreateNewSUnit(N);
1008 assert(N->getNodeId() == -1 && "Node already inserted!")((N->getNodeId() == -1 && "Node already inserted!"
) ? static_cast<void> (0) : __assert_fail ("N->getNodeId() == -1 && \"Node already inserted!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp"
, 1008, __PRETTY_FUNCTION__))
;
1009 N->setNodeId(NewSU->NodeNum);
1010
1011 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
1012 for (unsigned i = 0; i != MCID.getNumOperands(); ++i) {
1013 if (MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1) {
1014 NewSU->isTwoAddress = true;
1015 break;
1016 }
1017 }
1018 if (MCID.isCommutable())
1019 NewSU->isCommutable = true;
1020
1021 InitNumRegDefsLeft(NewSU);
1022 computeLatency(NewSU);
1023
1024 // Record all the edges to and from the old SU, by category.
1025 SmallVector<SDep, 4> ChainPreds;
1026 SmallVector<SDep, 4> ChainSuccs;
1027 SmallVector<SDep, 4> LoadPreds;
1028 SmallVector<SDep, 4> NodePreds;
1029 SmallVector<SDep, 4> NodeSuccs;
1030 for (SDep &Pred : SU->Preds) {
1031 if (Pred.isCtrl())
1032 ChainPreds.push_back(Pred);
1033 else if (isOperandOf(Pred.getSUnit(), LoadNode))
1034 LoadPreds.push_back(Pred);
1035 else
1036 NodePreds.push_back(Pred);
1037 }
1038 for (SDep &Succ : SU->Succs) {
1039 if (Succ.isCtrl())
1040 ChainSuccs.push_back(Succ);
1041 else
1042 NodeSuccs.push_back(Succ);
1043 }
1044
1045 // Now assign edges to the newly-created nodes.
1046 for (const SDep &Pred : ChainPreds) {
1047 RemovePred(SU, Pred);
1048 if (isNewLoad)
1049 AddPred(LoadSU, Pred);
1050 }
1051 for (const SDep &Pred : LoadPreds) {
1052 RemovePred(SU, Pred);
1053 if (isNewLoad)
1054 AddPred(LoadSU, Pred);
1055 }
1056 for (const SDep &Pred : NodePreds) {
1057 RemovePred(SU, Pred);
1058 AddPred(NewSU, Pred);
1059 }
1060 for (SDep D : NodeSuccs) {
1061 SUnit *SuccDep = D.getSUnit();
1062 D.setSUnit(SU);
1063 RemovePred(SuccDep, D);
1064 D.setSUnit(NewSU);
1065 AddPred(SuccDep, D);
1066 // Balance register pressure.
1067 if (AvailableQueue->tracksRegPressure() && SuccDep->isScheduled
1068 && !D.isCtrl() && NewSU->NumRegDefsLeft > 0)
1069 --NewSU->NumRegDefsLeft;
1070 }
1071 for (SDep D : ChainSuccs) {
1072 SUnit *SuccDep = D.getSUnit();
1073 D.setSUnit(SU);
1074 RemovePred(SuccDep, D);
1075 if (isNewLoad) {
1076 D.setSUnit(LoadSU);
1077 AddPred(SuccDep, D);
1078 }
1079 }
1080
1081 // Add a data dependency to reflect that NewSU reads the value defined
1082 // by LoadSU.
1083 SDep D(LoadSU, SDep::Data, 0);
1084 D.setLatency(LoadSU->Latency);
1085 AddPred(NewSU, D);
1086
1087 if (isNewLoad)
1088 AvailableQueue->addNode(LoadSU);
1089 AvailableQueue->addNode(NewSU);
1090
1091 ++NumUnfolds;
1092
1093 if (NewSU->NumSuccsLeft == 0) {
1094 NewSU->isAvailable = true;
1095 return NewSU;
1096 }
1097 SU = NewSU;
1098 }
1099
1100 DEBUG(dbgs() << " Duplicating SU #" << SU->NodeNum << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("pre-RA-sched")) { dbgs() << " Duplicating SU #" <<
SU->NodeNum << "\n"; } } while (false)
;
1101 NewSU = CreateClone(SU);
1102
1103 // New SUnit has the exact same predecessors.
1104 for (SDep &Pred : SU->Preds)
1105 if (!Pred.isArtificial())
1106 AddPred(NewSU, Pred);
1107
1108 // Only copy scheduled successors. Cut them from old node's successor
1109 // list and move them over.
1110 SmallVector<std::pair<SUnit *, SDep>, 4> DelDeps;
1111 for (SDep &Succ : SU->Succs) {
1112 if (Succ.isArtificial())
1113 continue;
1114 SUnit *SuccSU = Succ.getSUnit();
1115 if (SuccSU->isScheduled) {
1116 SDep D = Succ;
1117 D.setSUnit(NewSU);
1118 AddPred(SuccSU, D);
1119 D.setSUnit(SU);
1120 DelDeps.push_back(std::make_pair(SuccSU, D));
1121 }
1122 }
1123 for (auto &DelDep : DelDeps)
1124 RemovePred(DelDep.first, DelDep.second);
1125
1126 AvailableQueue->updateNode(SU);
1127 AvailableQueue->addNode(NewSU);
1128
1129 ++NumDups;
1130 return NewSU;
1131}
1132
1133/// InsertCopiesAndMoveSuccs - Insert register copies and move all
1134/// scheduled successors of the given SUnit to the last copy.
1135void ScheduleDAGRRList::InsertCopiesAndMoveSuccs(SUnit *SU, unsigned Reg,
1136 const TargetRegisterClass *DestRC,
1137 const TargetRegisterClass *SrcRC,
1138 SmallVectorImpl<SUnit*> &Copies) {
1139 SUnit *CopyFromSU = CreateNewSUnit(nullptr);
1140 CopyFromSU->CopySrcRC = SrcRC;
1141 CopyFromSU->CopyDstRC = DestRC;
1142
1143 SUnit *CopyToSU = CreateNewSUnit(nullptr);
1144 CopyToSU->CopySrcRC = DestRC;
1145 CopyToSU->CopyDstRC = SrcRC;
1146
1147 // Only copy scheduled successors. Cut them from old node's successor
1148 // list and move them over.
1149 SmallVector<std::pair<SUnit *, SDep>, 4> DelDeps;
1150 for (SDep &Succ : SU->Succs) {
1151 if (Succ.isArtificial())
1152 continue;
1153 SUnit *SuccSU = Succ.getSUnit();
1154 if (SuccSU->isScheduled) {
1155 SDep D = Succ;
1156 D.setSUnit(CopyToSU);
1157 AddPred(SuccSU, D);
1158 DelDeps.push_back(std::make_pair(SuccSU, Succ));
1159 }
1160 else {
1161 // Avoid scheduling the def-side copy before other successors. Otherwise
1162 // we could introduce another physreg interference on the copy and
1163 // continue inserting copies indefinitely.
1164 AddPred(SuccSU, SDep(CopyFromSU, SDep::Artificial));
1165 }
1166 }
1167 for (auto &DelDep : DelDeps)
1168 RemovePred(DelDep.first, DelDep.second);
1169
1170 SDep FromDep(SU, SDep::Data, Reg);
1171 FromDep.setLatency(SU->Latency);
1172 AddPred(CopyFromSU, FromDep);
1173 SDep ToDep(CopyFromSU, SDep::Data, 0);
1174 ToDep.setLatency(CopyFromSU->Latency);
1175 AddPred(CopyToSU, ToDep);
1176
1177 AvailableQueue->updateNode(SU);
1178 AvailableQueue->addNode(CopyFromSU);
1179 AvailableQueue->addNode(CopyToSU);
1180 Copies.push_back(CopyFromSU);
1181 Copies.push_back(CopyToSU);
1182
1183 ++NumPRCopies;
1184}
1185
1186/// getPhysicalRegisterVT - Returns the ValueType of the physical register
1187/// definition of the specified node.
1188/// FIXME: Move to SelectionDAG?
1189static MVT getPhysicalRegisterVT(SDNode *N, unsigned Reg,
1190 const TargetInstrInfo *TII) {
1191 unsigned NumRes;
1192 if (N->getOpcode() == ISD::CopyFromReg) {
1193 // CopyFromReg has: "chain, Val, glue" so operand 1 gives the type.
1194 NumRes = 1;
1195 } else {
1196 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
1197 assert(MCID.ImplicitDefs && "Physical reg def must be in implicit def list!")((MCID.ImplicitDefs && "Physical reg def must be in implicit def list!"
) ? static_cast<void> (0) : __assert_fail ("MCID.ImplicitDefs && \"Physical reg def must be in implicit def list!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp"
, 1197, __PRETTY_FUNCTION__))
;
1198 NumRes = MCID.getNumDefs();
1199 for (const MCPhysReg *ImpDef = MCID.getImplicitDefs(); *ImpDef; ++ImpDef) {
1200 if (Reg == *ImpDef)
1201 break;
1202 ++NumRes;
1203 }
1204 }
1205 return N->getSimpleValueType(NumRes);
1206}
1207
1208/// CheckForLiveRegDef - Return true and update live register vector if the
1209/// specified register def of the specified SUnit clobbers any "live" registers.
1210static void CheckForLiveRegDef(SUnit *SU, unsigned Reg,
1211 SUnit **LiveRegDefs,
1212 SmallSet<unsigned, 4> &RegAdded,
1213 SmallVectorImpl<unsigned> &LRegs,
1214 const TargetRegisterInfo *TRI) {
1215 for (MCRegAliasIterator AliasI(Reg, TRI, true); AliasI.isValid(); ++AliasI) {
1216
1217 // Check if Ref is live.
1218 if (!LiveRegDefs[*AliasI]) continue;
1219
1220 // Allow multiple uses of the same def.
1221 if (LiveRegDefs[*AliasI] == SU) continue;
1222
1223 // Add Reg to the set of interfering live regs.
1224 if (RegAdded.insert(*AliasI).second) {
1225 LRegs.push_back(*AliasI);
1226 }
1227 }
1228}
1229
1230/// CheckForLiveRegDefMasked - Check for any live physregs that are clobbered
1231/// by RegMask, and add them to LRegs.
1232static void CheckForLiveRegDefMasked(SUnit *SU, const uint32_t *RegMask,
1233 ArrayRef<SUnit*> LiveRegDefs,
1234 SmallSet<unsigned, 4> &RegAdded,
1235 SmallVectorImpl<unsigned> &LRegs) {
1236 // Look at all live registers. Skip Reg0 and the special CallResource.
1237 for (unsigned i = 1, e = LiveRegDefs.size()-1; i != e; ++i) {
1238 if (!LiveRegDefs[i]) continue;
1239 if (LiveRegDefs[i] == SU) continue;
1240 if (!MachineOperand::clobbersPhysReg(RegMask, i)) continue;
1241 if (RegAdded.insert(i).second)
1242 LRegs.push_back(i);
1243 }
1244}
1245
1246/// getNodeRegMask - Returns the register mask attached to an SDNode, if any.
1247static const uint32_t *getNodeRegMask(const SDNode *N) {
1248 for (const SDValue &Op : N->op_values())
1249 if (const auto *RegOp = dyn_cast<RegisterMaskSDNode>(Op.getNode()))
1250 return RegOp->getRegMask();
1251 return nullptr;
1252}
1253
1254/// DelayForLiveRegsBottomUp - Returns true if it is necessary to delay
1255/// scheduling of the given node to satisfy live physical register dependencies.
1256/// If the specific node is the last one that's available to schedule, do
1257/// whatever is necessary (i.e. backtracking or cloning) to make it possible.
1258bool ScheduleDAGRRList::
1259DelayForLiveRegsBottomUp(SUnit *SU, SmallVectorImpl<unsigned> &LRegs) {
1260 if (NumLiveRegs == 0)
1261 return false;
1262
1263 SmallSet<unsigned, 4> RegAdded;
1264 // If this node would clobber any "live" register, then it's not ready.
1265 //
1266 // If SU is the currently live definition of the same register that it uses,
1267 // then we are free to schedule it.
1268 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
1269 I != E; ++I) {
1270 if (I->isAssignedRegDep() && LiveRegDefs[I->getReg()] != SU)
1271 CheckForLiveRegDef(I->getSUnit(), I->getReg(), LiveRegDefs.get(),
1272 RegAdded, LRegs, TRI);
1273 }
1274
1275 for (SDNode *Node = SU->getNode(); Node; Node = Node->getGluedNode()) {
1276 if (Node->getOpcode() == ISD::INLINEASM) {
1277 // Inline asm can clobber physical defs.
1278 unsigned NumOps = Node->getNumOperands();
1279 if (Node->getOperand(NumOps-1).getValueType() == MVT::Glue)
1280 --NumOps; // Ignore the glue operand.
1281
1282 for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
1283 unsigned Flags =
1284 cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue();
1285 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
1286
1287 ++i; // Skip the ID value.
1288 if (InlineAsm::isRegDefKind(Flags) ||
1289 InlineAsm::isRegDefEarlyClobberKind(Flags) ||
1290 InlineAsm::isClobberKind(Flags)) {
1291 // Check for def of register or earlyclobber register.
1292 for (; NumVals; --NumVals, ++i) {
1293 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
1294 if (TargetRegisterInfo::isPhysicalRegister(Reg))
1295 CheckForLiveRegDef(SU, Reg, LiveRegDefs.get(), RegAdded, LRegs, TRI);
1296 }
1297 } else
1298 i += NumVals;
1299 }
1300 continue;
1301 }
1302
1303 if (!Node->isMachineOpcode())
1304 continue;
1305 // If we're in the middle of scheduling a call, don't begin scheduling
1306 // another call. Also, don't allow any physical registers to be live across
1307 // the call.
1308 if (Node->getMachineOpcode() == (unsigned)TII->getCallFrameDestroyOpcode()) {
1309 // Check the special calling-sequence resource.
1310 unsigned CallResource = TRI->getNumRegs();
1311 if (LiveRegDefs[CallResource]) {
1312 SDNode *Gen = LiveRegGens[CallResource]->getNode();
1313 while (SDNode *Glued = Gen->getGluedNode())
1314 Gen = Glued;
1315 if (!IsChainDependent(Gen, Node, 0, TII) &&
1316 RegAdded.insert(CallResource).second)
1317 LRegs.push_back(CallResource);
1318 }
1319 }
1320 if (const uint32_t *RegMask = getNodeRegMask(Node))
1321 CheckForLiveRegDefMasked(SU, RegMask,
1322 makeArrayRef(LiveRegDefs.get(), TRI->getNumRegs()),
1323 RegAdded, LRegs);
1324
1325 const MCInstrDesc &MCID = TII->get(Node->getMachineOpcode());
1326 if (!MCID.ImplicitDefs)
1327 continue;
1328 for (const MCPhysReg *Reg = MCID.getImplicitDefs(); *Reg; ++Reg)
1329 CheckForLiveRegDef(SU, *Reg, LiveRegDefs.get(), RegAdded, LRegs, TRI);
1330 }
1331
1332 return !LRegs.empty();
1333}
1334
1335void ScheduleDAGRRList::releaseInterferences(unsigned Reg) {
1336 // Add the nodes that aren't ready back onto the available list.
1337 for (unsigned i = Interferences.size(); i > 0; --i) {
1338 SUnit *SU = Interferences[i-1];
1339 LRegsMapT::iterator LRegsPos = LRegsMap.find(SU);
1340 if (Reg) {
1341 SmallVectorImpl<unsigned> &LRegs = LRegsPos->second;
1342 if (!is_contained(LRegs, Reg))
1343 continue;
1344 }
1345 SU->isPending = false;
1346 // The interfering node may no longer be available due to backtracking.
1347 // Furthermore, it may have been made available again, in which case it is
1348 // now already in the AvailableQueue.
1349 if (SU->isAvailable && !SU->NodeQueueId) {
1350 DEBUG(dbgs() << " Repushing SU #" << SU->NodeNum << '\n')do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("pre-RA-sched")) { dbgs() << " Repushing SU #" <<
SU->NodeNum << '\n'; } } while (false)
;
1351 AvailableQueue->push(SU);
1352 }
1353 if (i < Interferences.size())
1354 Interferences[i-1] = Interferences.back();
1355 Interferences.pop_back();
1356 LRegsMap.erase(LRegsPos);
1357 }
1358}
1359
1360/// Return a node that can be scheduled in this cycle. Requirements:
1361/// (1) Ready: latency has been satisfied
1362/// (2) No Hazards: resources are available
1363/// (3) No Interferences: may unschedule to break register interferences.
1364SUnit *ScheduleDAGRRList::PickNodeToScheduleBottomUp() {
1365 SUnit *CurSU = AvailableQueue->empty() ? nullptr : AvailableQueue->pop();
1
Assuming the condition is false
2
'?' condition is false
1366 while (CurSU) {
3
Loop condition is false. Execution continues on line 1387
1367 SmallVector<unsigned, 4> LRegs;
1368 if (!DelayForLiveRegsBottomUp(CurSU, LRegs))
1369 break;
1370 DEBUG(dbgs() << " Interfering reg " <<do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("pre-RA-sched")) { dbgs() << " Interfering reg " <<
(LRegs[0] == TRI->getNumRegs() ? "CallResource" : TRI->
getName(LRegs[0])) << " SU #" << CurSU->NodeNum
<< '\n'; } } while (false)
1371 (LRegs[0] == TRI->getNumRegs() ? "CallResource"do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("pre-RA-sched")) { dbgs() << " Interfering reg " <<
(LRegs[0] == TRI->getNumRegs() ? "CallResource" : TRI->
getName(LRegs[0])) << " SU #" << CurSU->NodeNum
<< '\n'; } } while (false)
1372 : TRI->getName(LRegs[0]))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("pre-RA-sched")) { dbgs() << " Interfering reg " <<
(LRegs[0] == TRI->getNumRegs() ? "CallResource" : TRI->
getName(LRegs[0])) << " SU #" << CurSU->NodeNum
<< '\n'; } } while (false)
1373 << " SU #" << CurSU->NodeNum << '\n')do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("pre-RA-sched")) { dbgs() << " Interfering reg " <<
(LRegs[0] == TRI->getNumRegs() ? "CallResource" : TRI->
getName(LRegs[0])) << " SU #" << CurSU->NodeNum
<< '\n'; } } while (false)
;
1374 std::pair<LRegsMapT::iterator, bool> LRegsPair =
1375 LRegsMap.insert(std::make_pair(CurSU, LRegs));
1376 if (LRegsPair.second) {
1377 CurSU->isPending = true; // This SU is not in AvailableQueue right now.
1378 Interferences.push_back(CurSU);
1379 }
1380 else {
1381 assert(CurSU->isPending && "Interferences are pending")((CurSU->isPending && "Interferences are pending")
? static_cast<void> (0) : __assert_fail ("CurSU->isPending && \"Interferences are pending\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp"
, 1381, __PRETTY_FUNCTION__))
;
1382 // Update the interference with current live regs.
1383 LRegsPair.first->second = LRegs;
1384 }
1385 CurSU = AvailableQueue->pop();
1386 }
1387 if (CurSU)
4
Taking false branch
1388 return CurSU;
1389
1390 // All candidates are delayed due to live physical reg dependencies.
1391 // Try backtracking, code duplication, or inserting cross class copies
1392 // to resolve it.
1393 for (SUnit *TrySU : Interferences) {
5
Assuming '__begin' is not equal to '__end'
1394 SmallVectorImpl<unsigned> &LRegs = LRegsMap[TrySU];
1395
1396 // Try unscheduling up to the point where it's safe to schedule
1397 // this node.
1398 SUnit *BtSU = nullptr;
9
'BtSU' initialized to a null pointer value
1399 unsigned LiveCycle = UINT_MAX(2147483647 *2U +1U);
1400 for (unsigned Reg : LRegs) {
6
Assuming '__begin' is equal to '__end'
10
Assuming '__begin' is equal to '__end'
1401 if (LiveRegGens[Reg]->getHeight() < LiveCycle) {
1402 BtSU = LiveRegGens[Reg];
1403 LiveCycle = BtSU->getHeight();
1404 }
1405 }
1406 if (!WillCreateCycle(TrySU, BtSU)) {
7
Assuming the condition is false
8
Taking false branch
11
Assuming the condition is true
12
Taking true branch
1407 // BacktrackBottomUp mutates Interferences!
1408 BacktrackBottomUp(TrySU, BtSU);
1409
1410 // Force the current node to be scheduled before the node that
1411 // requires the physical reg dep.
1412 if (BtSU->isAvailable) {
13
Access to field 'isAvailable' results in a dereference of a null pointer (loaded from variable 'BtSU')
1413 BtSU->isAvailable = false;
1414 if (!BtSU->isPending)
1415 AvailableQueue->remove(BtSU);
1416 }
1417 DEBUG(dbgs() << "ARTIFICIAL edge from SU(" << BtSU->NodeNum << ") to SU("do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("pre-RA-sched")) { dbgs() << "ARTIFICIAL edge from SU("
<< BtSU->NodeNum << ") to SU(" << TrySU
->NodeNum << ")\n"; } } while (false)
1418 << TrySU->NodeNum << ")\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("pre-RA-sched")) { dbgs() << "ARTIFICIAL edge from SU("
<< BtSU->NodeNum << ") to SU(" << TrySU
->NodeNum << ")\n"; } } while (false)
;
1419 AddPred(TrySU, SDep(BtSU, SDep::Artificial));
1420
1421 // If one or more successors has been unscheduled, then the current
1422 // node is no longer available.
1423 if (!TrySU->isAvailable || !TrySU->NodeQueueId)
1424 CurSU = AvailableQueue->pop();
1425 else {
1426 // Available and in AvailableQueue
1427 AvailableQueue->remove(TrySU);
1428 CurSU = TrySU;
1429 }
1430 // Interferences has been mutated. We must break.
1431 break;
1432 }
1433 }
1434
1435 if (!CurSU) {
1436 // Can't backtrack. If it's too expensive to copy the value, then try
1437 // duplicate the nodes that produces these "too expensive to copy"
1438 // values to break the dependency. In case even that doesn't work,
1439 // insert cross class copies.
1440 // If it's not too expensive, i.e. cost != -1, issue copies.
1441 SUnit *TrySU = Interferences[0];
1442 SmallVectorImpl<unsigned> &LRegs = LRegsMap[TrySU];
1443 assert(LRegs.size() == 1 && "Can't handle this yet!")((LRegs.size() == 1 && "Can't handle this yet!") ? static_cast
<void> (0) : __assert_fail ("LRegs.size() == 1 && \"Can't handle this yet!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp"
, 1443, __PRETTY_FUNCTION__))
;
1444 unsigned Reg = LRegs[0];
1445 SUnit *LRDef = LiveRegDefs[Reg];
1446 MVT VT = getPhysicalRegisterVT(LRDef->getNode(), Reg, TII);
1447 const TargetRegisterClass *RC =
1448 TRI->getMinimalPhysRegClass(Reg, VT);
1449 const TargetRegisterClass *DestRC = TRI->getCrossCopyRegClass(RC);
1450
1451 // If cross copy register class is the same as RC, then it must be possible
1452 // copy the value directly. Do not try duplicate the def.
1453 // If cross copy register class is not the same as RC, then it's possible to
1454 // copy the value but it require cross register class copies and it is
1455 // expensive.
1456 // If cross copy register class is null, then it's not possible to copy
1457 // the value at all.
1458 SUnit *NewDef = nullptr;
1459 if (DestRC != RC) {
1460 NewDef = CopyAndMoveSuccessors(LRDef);
1461 if (!DestRC && !NewDef)
1462 report_fatal_error("Can't handle live physical register dependency!");
1463 }
1464 if (!NewDef) {
1465 // Issue copies, these can be expensive cross register class copies.
1466 SmallVector<SUnit*, 2> Copies;
1467 InsertCopiesAndMoveSuccs(LRDef, Reg, DestRC, RC, Copies);
1468 DEBUG(dbgs() << " Adding an edge from SU #" << TrySU->NodeNumdo { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("pre-RA-sched")) { dbgs() << " Adding an edge from SU #"
<< TrySU->NodeNum << " to SU #" << Copies
.front()->NodeNum << "\n"; } } while (false)
1469 << " to SU #" << Copies.front()->NodeNum << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("pre-RA-sched")) { dbgs() << " Adding an edge from SU #"
<< TrySU->NodeNum << " to SU #" << Copies
.front()->NodeNum << "\n"; } } while (false)
;
1470 AddPred(TrySU, SDep(Copies.front(), SDep::Artificial));
1471 NewDef = Copies.back();
1472 }
1473
1474 DEBUG(dbgs() << " Adding an edge from SU #" << NewDef->NodeNumdo { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("pre-RA-sched")) { dbgs() << " Adding an edge from SU #"
<< NewDef->NodeNum << " to SU #" << TrySU
->NodeNum << "\n"; } } while (false)
1475 << " to SU #" << TrySU->NodeNum << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("pre-RA-sched")) { dbgs() << " Adding an edge from SU #"
<< NewDef->NodeNum << " to SU #" << TrySU
->NodeNum << "\n"; } } while (false)
;
1476 LiveRegDefs[Reg] = NewDef;
1477 AddPred(NewDef, SDep(TrySU, SDep::Artificial));
1478 TrySU->isAvailable = false;
1479 CurSU = NewDef;
1480 }
1481 assert(CurSU && "Unable to resolve live physical register dependencies!")((CurSU && "Unable to resolve live physical register dependencies!"
) ? static_cast<void> (0) : __assert_fail ("CurSU && \"Unable to resolve live physical register dependencies!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp"
, 1481, __PRETTY_FUNCTION__))
;
1482 return CurSU;
1483}
1484
1485/// ListScheduleBottomUp - The main loop of list scheduling for bottom-up
1486/// schedulers.
1487void ScheduleDAGRRList::ListScheduleBottomUp() {
1488 // Release any predecessors of the special Exit node.
1489 ReleasePredecessors(&ExitSU);
1490
1491 // Add root to Available queue.
1492 if (!SUnits.empty()) {
1493 SUnit *RootSU = &SUnits[DAG->getRoot().getNode()->getNodeId()];
1494 assert(RootSU->Succs.empty() && "Graph root shouldn't have successors!")((RootSU->Succs.empty() && "Graph root shouldn't have successors!"
) ? static_cast<void> (0) : __assert_fail ("RootSU->Succs.empty() && \"Graph root shouldn't have successors!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp"
, 1494, __PRETTY_FUNCTION__))
;
1495 RootSU->isAvailable = true;
1496 AvailableQueue->push(RootSU);
1497 }
1498
1499 // While Available queue is not empty, grab the node with the highest
1500 // priority. If it is not ready put it back. Schedule the node.
1501 Sequence.reserve(SUnits.size());
1502 while (!AvailableQueue->empty() || !Interferences.empty()) {
1503 DEBUG(dbgs() << "\nExamining Available:\n";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("pre-RA-sched")) { dbgs() << "\nExamining Available:\n"
; AvailableQueue->dump(this); } } while (false)
1504 AvailableQueue->dump(this))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("pre-RA-sched")) { dbgs() << "\nExamining Available:\n"
; AvailableQueue->dump(this); } } while (false)
;
1505
1506 // Pick the best node to schedule taking all constraints into
1507 // consideration.
1508 SUnit *SU = PickNodeToScheduleBottomUp();
1509
1510 AdvancePastStalls(SU);
1511
1512 ScheduleNodeBottomUp(SU);
1513
1514 while (AvailableQueue->empty() && !PendingQueue.empty()) {
1515 // Advance the cycle to free resources. Skip ahead to the next ready SU.
1516 assert(MinAvailableCycle < UINT_MAX && "MinAvailableCycle uninitialized")((MinAvailableCycle < (2147483647 *2U +1U) && "MinAvailableCycle uninitialized"
) ? static_cast<void> (0) : __assert_fail ("MinAvailableCycle < UINT_MAX && \"MinAvailableCycle uninitialized\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp"
, 1516, __PRETTY_FUNCTION__))
;
1517 AdvanceToCycle(std::max(CurCycle + 1, MinAvailableCycle));
1518 }
1519 }
1520
1521 // Reverse the order if it is bottom up.
1522 std::reverse(Sequence.begin(), Sequence.end());
1523
1524#ifndef NDEBUG
1525 VerifyScheduledSequence(/*isBottomUp=*/true);
1526#endif
1527}
1528
1529//===----------------------------------------------------------------------===//
1530// RegReductionPriorityQueue Definition
1531//===----------------------------------------------------------------------===//
1532//
1533// This is a SchedulingPriorityQueue that schedules using Sethi Ullman numbers
1534// to reduce register pressure.
1535//
1536namespace {
1537class RegReductionPQBase;
1538
1539struct queue_sort : public std::binary_function<SUnit*, SUnit*, bool> {
1540 bool isReady(SUnit* SU, unsigned CurCycle) const { return true; }
1541};
1542
1543#ifndef NDEBUG
1544template<class SF>
1545struct reverse_sort : public queue_sort {
1546 SF &SortFunc;
1547 reverse_sort(SF &sf) : SortFunc(sf) {}
1548
1549 bool operator()(SUnit* left, SUnit* right) const {
1550 // reverse left/right rather than simply !SortFunc(left, right)
1551 // to expose different paths in the comparison logic.
1552 return SortFunc(right, left);
1553 }
1554};
1555#endif // NDEBUG
1556
1557/// bu_ls_rr_sort - Priority function for bottom up register pressure
1558// reduction scheduler.
1559struct bu_ls_rr_sort : public queue_sort {
1560 enum {
1561 IsBottomUp = true,
1562 HasReadyFilter = false
1563 };
1564
1565 RegReductionPQBase *SPQ;
1566 bu_ls_rr_sort(RegReductionPQBase *spq) : SPQ(spq) {}
1567
1568 bool operator()(SUnit* left, SUnit* right) const;
1569};
1570
1571// src_ls_rr_sort - Priority function for source order scheduler.
1572struct src_ls_rr_sort : public queue_sort {
1573 enum {
1574 IsBottomUp = true,
1575 HasReadyFilter = false
1576 };
1577
1578 RegReductionPQBase *SPQ;
1579 src_ls_rr_sort(RegReductionPQBase *spq)
1580 : SPQ(spq) {}
1581
1582 bool operator()(SUnit* left, SUnit* right) const;
1583};
1584
1585// hybrid_ls_rr_sort - Priority function for hybrid scheduler.
1586struct hybrid_ls_rr_sort : public queue_sort {
1587 enum {
1588 IsBottomUp = true,
1589 HasReadyFilter = false
1590 };
1591
1592 RegReductionPQBase *SPQ;
1593 hybrid_ls_rr_sort(RegReductionPQBase *spq)
1594 : SPQ(spq) {}
1595
1596 bool isReady(SUnit *SU, unsigned CurCycle) const;
1597
1598 bool operator()(SUnit* left, SUnit* right) const;
1599};
1600
1601// ilp_ls_rr_sort - Priority function for ILP (instruction level parallelism)
1602// scheduler.
1603struct ilp_ls_rr_sort : public queue_sort {
1604 enum {
1605 IsBottomUp = true,
1606 HasReadyFilter = false
1607 };
1608
1609 RegReductionPQBase *SPQ;
1610 ilp_ls_rr_sort(RegReductionPQBase *spq)
1611 : SPQ(spq) {}
1612
1613 bool isReady(SUnit *SU, unsigned CurCycle) const;
1614
1615 bool operator()(SUnit* left, SUnit* right) const;
1616};
1617
1618class RegReductionPQBase : public SchedulingPriorityQueue {
1619protected:
1620 std::vector<SUnit*> Queue;
1621 unsigned CurQueueId;
1622 bool TracksRegPressure;
1623 bool SrcOrder;
1624
1625 // SUnits - The SUnits for the current graph.
1626 std::vector<SUnit> *SUnits;
1627
1628 MachineFunction &MF;
1629 const TargetInstrInfo *TII;
1630 const TargetRegisterInfo *TRI;
1631 const TargetLowering *TLI;
1632 ScheduleDAGRRList *scheduleDAG;
1633
1634 // SethiUllmanNumbers - The SethiUllman number for each node.
1635 std::vector<unsigned> SethiUllmanNumbers;
1636
1637 /// RegPressure - Tracking current reg pressure per register class.
1638 ///
1639 std::vector<unsigned> RegPressure;
1640
1641 /// RegLimit - Tracking the number of allocatable registers per register
1642 /// class.
1643 std::vector<unsigned> RegLimit;
1644
1645public:
1646 RegReductionPQBase(MachineFunction &mf,
1647 bool hasReadyFilter,
1648 bool tracksrp,
1649 bool srcorder,
1650 const TargetInstrInfo *tii,
1651 const TargetRegisterInfo *tri,
1652 const TargetLowering *tli)
1653 : SchedulingPriorityQueue(hasReadyFilter),
1654 CurQueueId(0), TracksRegPressure(tracksrp), SrcOrder(srcorder),
1655 MF(mf), TII(tii), TRI(tri), TLI(tli), scheduleDAG(nullptr) {
1656 if (TracksRegPressure) {
1657 unsigned NumRC = TRI->getNumRegClasses();
1658 RegLimit.resize(NumRC);
1659 RegPressure.resize(NumRC);
1660 std::fill(RegLimit.begin(), RegLimit.end(), 0);
1661 std::fill(RegPressure.begin(), RegPressure.end(), 0);
1662 for (const TargetRegisterClass *RC : TRI->regclasses())
1663 RegLimit[RC->getID()] = tri->getRegPressureLimit(RC, MF);
1664 }
1665 }
1666
1667 void setScheduleDAG(ScheduleDAGRRList *scheduleDag) {
1668 scheduleDAG = scheduleDag;
1669 }
1670
1671 ScheduleHazardRecognizer* getHazardRec() {
1672 return scheduleDAG->getHazardRec();
1673 }
1674
1675 void initNodes(std::vector<SUnit> &sunits) override;
1676
1677 void addNode(const SUnit *SU) override;
1678
1679 void updateNode(const SUnit *SU) override;
1680
1681 void releaseState() override {
1682 SUnits = nullptr;
1683 SethiUllmanNumbers.clear();
1684 std::fill(RegPressure.begin(), RegPressure.end(), 0);
1685 }
1686
1687 unsigned getNodePriority(const SUnit *SU) const;
1688
1689 unsigned getNodeOrdering(const SUnit *SU) const {
1690 if (!SU->getNode()) return 0;
1691
1692 return SU->getNode()->getIROrder();
1693 }
1694
1695 bool empty() const override { return Queue.empty(); }
1696
1697 void push(SUnit *U) override {
1698 assert(!U->NodeQueueId && "Node in the queue already")((!U->NodeQueueId && "Node in the queue already") ?
static_cast<void> (0) : __assert_fail ("!U->NodeQueueId && \"Node in the queue already\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp"
, 1698, __PRETTY_FUNCTION__))
;
1699 U->NodeQueueId = ++CurQueueId;
1700 Queue.push_back(U);
1701 }
1702
1703 void remove(SUnit *SU) override {
1704 assert(!Queue.empty() && "Queue is empty!")((!Queue.empty() && "Queue is empty!") ? static_cast<
void> (0) : __assert_fail ("!Queue.empty() && \"Queue is empty!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp"
, 1704, __PRETTY_FUNCTION__))
;
1705 assert(SU->NodeQueueId != 0 && "Not in queue!")((SU->NodeQueueId != 0 && "Not in queue!") ? static_cast
<void> (0) : __assert_fail ("SU->NodeQueueId != 0 && \"Not in queue!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp"
, 1705, __PRETTY_FUNCTION__))
;
1706 std::vector<SUnit *>::iterator I = find(Queue, SU);
1707 if (I != std::prev(Queue.end()))
1708 std::swap(*I, Queue.back());
1709 Queue.pop_back();
1710 SU->NodeQueueId = 0;
1711 }
1712
1713 bool tracksRegPressure() const override { return TracksRegPressure; }
1714
1715 void dumpRegPressure() const;
1716
1717 bool HighRegPressure(const SUnit *SU) const;
1718
1719 bool MayReduceRegPressure(SUnit *SU) const;
1720
1721 int RegPressureDiff(SUnit *SU, unsigned &LiveUses) const;
1722
1723 void scheduledNode(SUnit *SU) override;
1724
1725 void unscheduledNode(SUnit *SU) override;
1726
1727protected:
1728 bool canClobber(const SUnit *SU, const SUnit *Op);
1729 void AddPseudoTwoAddrDeps();
1730 void PrescheduleNodesWithMultipleUses();
1731 void CalculateSethiUllmanNumbers();
1732};
1733
1734template<class SF>
1735static SUnit *popFromQueueImpl(std::vector<SUnit*> &Q, SF &Picker) {
1736 std::vector<SUnit *>::iterator Best = Q.begin();
1737 for (std::vector<SUnit *>::iterator I = std::next(Q.begin()),
1738 E = Q.end(); I != E; ++I)
1739 if (Picker(*Best, *I))
1740 Best = I;
1741 SUnit *V = *Best;
1742 if (Best != std::prev(Q.end()))
1743 std::swap(*Best, Q.back());
1744 Q.pop_back();
1745 return V;
1746}
1747
1748template<class SF>
1749SUnit *popFromQueue(std::vector<SUnit*> &Q, SF &Picker, ScheduleDAG *DAG) {
1750#ifndef NDEBUG
1751 if (DAG->StressSched) {
1752 reverse_sort<SF> RPicker(Picker);
1753 return popFromQueueImpl(Q, RPicker);
1754 }
1755#endif
1756 (void)DAG;
1757 return popFromQueueImpl(Q, Picker);
1758}
1759
1760template<class SF>
1761class RegReductionPriorityQueue : public RegReductionPQBase {
1762 SF Picker;
1763
1764public:
1765 RegReductionPriorityQueue(MachineFunction &mf,
1766 bool tracksrp,
1767 bool srcorder,
1768 const TargetInstrInfo *tii,
1769 const TargetRegisterInfo *tri,
1770 const TargetLowering *tli)
1771 : RegReductionPQBase(mf, SF::HasReadyFilter, tracksrp, srcorder,
1772 tii, tri, tli),
1773 Picker(this) {}
1774
1775 bool isBottomUp() const override { return SF::IsBottomUp; }
1776
1777 bool isReady(SUnit *U) const override {
1778 return Picker.HasReadyFilter && Picker.isReady(U, getCurCycle());
1779 }
1780
1781 SUnit *pop() override {
1782 if (Queue.empty()) return nullptr;
1783
1784 SUnit *V = popFromQueue(Queue, Picker, scheduleDAG);
1785 V->NodeQueueId = 0;
1786 return V;
1787 }
1788
1789#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
1790 LLVM_DUMP_METHOD__attribute__((noinline)) __attribute__((__used__)) void dump(ScheduleDAG *DAG) const override {
1791 // Emulate pop() without clobbering NodeQueueIds.
1792 std::vector<SUnit*> DumpQueue = Queue;
1793 SF DumpPicker = Picker;
1794 while (!DumpQueue.empty()) {
1795 SUnit *SU = popFromQueue(DumpQueue, DumpPicker, scheduleDAG);
1796 dbgs() << "Height " << SU->getHeight() << ": ";
1797 SU->dump(DAG);
1798 }
1799 }
1800#endif
1801};
1802
1803typedef RegReductionPriorityQueue<bu_ls_rr_sort>
1804BURegReductionPriorityQueue;
1805
1806typedef RegReductionPriorityQueue<src_ls_rr_sort>
1807SrcRegReductionPriorityQueue;
1808
1809typedef RegReductionPriorityQueue<hybrid_ls_rr_sort>
1810HybridBURRPriorityQueue;
1811
1812typedef RegReductionPriorityQueue<ilp_ls_rr_sort>
1813ILPBURRPriorityQueue;
1814} // end anonymous namespace
1815
1816//===----------------------------------------------------------------------===//
1817// Static Node Priority for Register Pressure Reduction
1818//===----------------------------------------------------------------------===//
1819
1820// Check for special nodes that bypass scheduling heuristics.
1821// Currently this pushes TokenFactor nodes down, but may be used for other
1822// pseudo-ops as well.
1823//
1824// Return -1 to schedule right above left, 1 for left above right.
1825// Return 0 if no bias exists.
1826static int checkSpecialNodes(const SUnit *left, const SUnit *right) {
1827 bool LSchedLow = left->isScheduleLow;
1828 bool RSchedLow = right->isScheduleLow;
1829 if (LSchedLow != RSchedLow)
1830 return LSchedLow < RSchedLow ? 1 : -1;
1831 return 0;
1832}
1833
1834/// CalcNodeSethiUllmanNumber - Compute Sethi Ullman number.
1835/// Smaller number is the higher priority.
1836static unsigned
1837CalcNodeSethiUllmanNumber(const SUnit *SU, std::vector<unsigned> &SUNumbers) {
1838 unsigned &SethiUllmanNumber = SUNumbers[SU->NodeNum];
1839 if (SethiUllmanNumber != 0)
1840 return SethiUllmanNumber;
1841
1842 unsigned Extra = 0;
1843 for (const SDep &Pred : SU->Preds) {
1844 if (Pred.isCtrl()) continue; // ignore chain preds
1845 SUnit *PredSU = Pred.getSUnit();
1846 unsigned PredSethiUllman = CalcNodeSethiUllmanNumber(PredSU, SUNumbers);
1847 if (PredSethiUllman > SethiUllmanNumber) {
1848 SethiUllmanNumber = PredSethiUllman;
1849 Extra = 0;
1850 } else if (PredSethiUllman == SethiUllmanNumber)
1851 ++Extra;
1852 }
1853
1854 SethiUllmanNumber += Extra;
1855
1856 if (SethiUllmanNumber == 0)
1857 SethiUllmanNumber = 1;
1858
1859 return SethiUllmanNumber;
1860}
1861
1862/// CalculateSethiUllmanNumbers - Calculate Sethi-Ullman numbers of all
1863/// scheduling units.
1864void RegReductionPQBase::CalculateSethiUllmanNumbers() {
1865 SethiUllmanNumbers.assign(SUnits->size(), 0);
1866
1867 for (const SUnit &SU : *SUnits)
1868 CalcNodeSethiUllmanNumber(&SU, SethiUllmanNumbers);
1869}
1870
1871void RegReductionPQBase::addNode(const SUnit *SU) {
1872 unsigned SUSize = SethiUllmanNumbers.size();
1873 if (SUnits->size() > SUSize)
1874 SethiUllmanNumbers.resize(SUSize*2, 0);
1875 CalcNodeSethiUllmanNumber(SU, SethiUllmanNumbers);
1876}
1877
1878void RegReductionPQBase::updateNode(const SUnit *SU) {
1879 SethiUllmanNumbers[SU->NodeNum] = 0;
1880 CalcNodeSethiUllmanNumber(SU, SethiUllmanNumbers);
1881}
1882
1883// Lower priority means schedule further down. For bottom-up scheduling, lower
1884// priority SUs are scheduled before higher priority SUs.
1885unsigned RegReductionPQBase::getNodePriority(const SUnit *SU) const {
1886 assert(SU->NodeNum < SethiUllmanNumbers.size())((SU->NodeNum < SethiUllmanNumbers.size()) ? static_cast
<void> (0) : __assert_fail ("SU->NodeNum < SethiUllmanNumbers.size()"
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp"
, 1886, __PRETTY_FUNCTION__))
;
1887 unsigned Opc = SU->getNode() ? SU->getNode()->getOpcode() : 0;
1888 if (Opc == ISD::TokenFactor || Opc == ISD::CopyToReg)
1889 // CopyToReg should be close to its uses to facilitate coalescing and
1890 // avoid spilling.
1891 return 0;
1892 if (Opc == TargetOpcode::EXTRACT_SUBREG ||
1893 Opc == TargetOpcode::SUBREG_TO_REG ||
1894 Opc == TargetOpcode::INSERT_SUBREG)
1895 // EXTRACT_SUBREG, INSERT_SUBREG, and SUBREG_TO_REG nodes should be
1896 // close to their uses to facilitate coalescing.
1897 return 0;
1898 if (SU->NumSuccs == 0 && SU->NumPreds != 0)
1899 // If SU does not have a register use, i.e. it doesn't produce a value
1900 // that would be consumed (e.g. store), then it terminates a chain of
1901 // computation. Give it a large SethiUllman number so it will be
1902 // scheduled right before its predecessors that it doesn't lengthen
1903 // their live ranges.
1904 return 0xffff;
1905 if (SU->NumPreds == 0 && SU->NumSuccs != 0)
1906 // If SU does not have a register def, schedule it close to its uses
1907 // because it does not lengthen any live ranges.
1908 return 0;
1909#if 1
1910 return SethiUllmanNumbers[SU->NodeNum];
1911#else
1912 unsigned Priority = SethiUllmanNumbers[SU->NodeNum];
1913 if (SU->isCallOp) {
1914 // FIXME: This assumes all of the defs are used as call operands.
1915 int NP = (int)Priority - SU->getNode()->getNumValues();
1916 return (NP > 0) ? NP : 0;
1917 }
1918 return Priority;
1919#endif
1920}
1921
1922//===----------------------------------------------------------------------===//
1923// Register Pressure Tracking
1924//===----------------------------------------------------------------------===//
1925
1926#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
1927LLVM_DUMP_METHOD__attribute__((noinline)) __attribute__((__used__)) void RegReductionPQBase::dumpRegPressure() const {
1928 for (const TargetRegisterClass *RC : TRI->regclasses()) {
1929 unsigned Id = RC->getID();
1930 unsigned RP = RegPressure[Id];
1931 if (!RP) continue;
1932 DEBUG(dbgs() << TRI->getRegClassName(RC) << ": " << RP << " / "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("pre-RA-sched")) { dbgs() << TRI->getRegClassName(RC
) << ": " << RP << " / " << RegLimit[
Id] << '\n'; } } while (false)
1933 << RegLimit[Id] << '\n')do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("pre-RA-sched")) { dbgs() << TRI->getRegClassName(RC
) << ": " << RP << " / " << RegLimit[
Id] << '\n'; } } while (false)
;
1934 }
1935}
1936#endif
1937
1938bool RegReductionPQBase::HighRegPressure(const SUnit *SU) const {
1939 if (!TLI)
1940 return false;
1941
1942 for (const SDep &Pred : SU->Preds) {
1943 if (Pred.isCtrl())
1944 continue;
1945 SUnit *PredSU = Pred.getSUnit();
1946 // NumRegDefsLeft is zero when enough uses of this node have been scheduled
1947 // to cover the number of registers defined (they are all live).
1948 if (PredSU->NumRegDefsLeft == 0) {
1949 continue;
1950 }
1951 for (ScheduleDAGSDNodes::RegDefIter RegDefPos(PredSU, scheduleDAG);
1952 RegDefPos.IsValid(); RegDefPos.Advance()) {
1953 unsigned RCId, Cost;
1954 GetCostForDef(RegDefPos, TLI, TII, TRI, RCId, Cost, MF);
1955
1956 if ((RegPressure[RCId] + Cost) >= RegLimit[RCId])
1957 return true;
1958 }
1959 }
1960 return false;
1961}
1962
1963bool RegReductionPQBase::MayReduceRegPressure(SUnit *SU) const {
1964 const SDNode *N = SU->getNode();
1965
1966 if (!N->isMachineOpcode() || !SU->NumSuccs)
1967 return false;
1968
1969 unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs();
1970 for (unsigned i = 0; i != NumDefs; ++i) {
1971 MVT VT = N->getSimpleValueType(i);
1972 if (!N->hasAnyUseOfValue(i))
1973 continue;
1974 unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
1975 if (RegPressure[RCId] >= RegLimit[RCId])
1976 return true;
1977 }
1978 return false;
1979}
1980
1981// Compute the register pressure contribution by this instruction by count up
1982// for uses that are not live and down for defs. Only count register classes
1983// that are already under high pressure. As a side effect, compute the number of
1984// uses of registers that are already live.
1985//
1986// FIXME: This encompasses the logic in HighRegPressure and MayReduceRegPressure
1987// so could probably be factored.
1988int RegReductionPQBase::RegPressureDiff(SUnit *SU, unsigned &LiveUses) const {
1989 LiveUses = 0;
1990 int PDiff = 0;
1991 for (const SDep &Pred : SU->Preds) {
1992 if (Pred.isCtrl())
1993 continue;
1994 SUnit *PredSU = Pred.getSUnit();
1995 // NumRegDefsLeft is zero when enough uses of this node have been scheduled
1996 // to cover the number of registers defined (they are all live).
1997 if (PredSU->NumRegDefsLeft == 0) {
1998 if (PredSU->getNode()->isMachineOpcode())
1999 ++LiveUses;
2000 continue;
2001 }
2002 for (ScheduleDAGSDNodes::RegDefIter RegDefPos(PredSU, scheduleDAG);
2003 RegDefPos.IsValid(); RegDefPos.Advance()) {
2004 MVT VT = RegDefPos.GetValue();
2005 unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
2006 if (RegPressure[RCId] >= RegLimit[RCId])
2007 ++PDiff;
2008 }
2009 }
2010 const SDNode *N = SU->getNode();
2011
2012 if (!N || !N->isMachineOpcode() || !SU->NumSuccs)
2013 return PDiff;
2014
2015 unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs();
2016 for (unsigned i = 0; i != NumDefs; ++i) {
2017 MVT VT = N->getSimpleValueType(i);
2018 if (!N->hasAnyUseOfValue(i))
2019 continue;
2020 unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
2021 if (RegPressure[RCId] >= RegLimit[RCId])
2022 --PDiff;
2023 }
2024 return PDiff;
2025}
2026
2027void RegReductionPQBase::scheduledNode(SUnit *SU) {
2028 if (!TracksRegPressure)
2029 return;
2030
2031 if (!SU->getNode())
2032 return;
2033
2034 for (const SDep &Pred : SU->Preds) {
2035 if (Pred.isCtrl())
2036 continue;
2037 SUnit *PredSU = Pred.getSUnit();
2038 // NumRegDefsLeft is zero when enough uses of this node have been scheduled
2039 // to cover the number of registers defined (they are all live).
2040 if (PredSU->NumRegDefsLeft == 0) {
2041 continue;
2042 }
2043 // FIXME: The ScheduleDAG currently loses information about which of a
2044 // node's values is consumed by each dependence. Consequently, if the node
2045 // defines multiple register classes, we don't know which to pressurize
2046 // here. Instead the following loop consumes the register defs in an
2047 // arbitrary order. At least it handles the common case of clustered loads
2048 // to the same class. For precise liveness, each SDep needs to indicate the
2049 // result number. But that tightly couples the ScheduleDAG with the
2050 // SelectionDAG making updates tricky. A simpler hack would be to attach a
2051 // value type or register class to SDep.
2052 //
2053 // The most important aspect of register tracking is balancing the increase
2054 // here with the reduction further below. Note that this SU may use multiple
2055 // defs in PredSU. The can't be determined here, but we've already
2056 // compensated by reducing NumRegDefsLeft in PredSU during
2057 // ScheduleDAGSDNodes::AddSchedEdges.
2058 --PredSU->NumRegDefsLeft;
2059 unsigned SkipRegDefs = PredSU->NumRegDefsLeft;
2060 for (ScheduleDAGSDNodes::RegDefIter RegDefPos(PredSU, scheduleDAG);
2061 RegDefPos.IsValid(); RegDefPos.Advance(), --SkipRegDefs) {
2062 if (SkipRegDefs)
2063 continue;
2064
2065 unsigned RCId, Cost;
2066 GetCostForDef(RegDefPos, TLI, TII, TRI, RCId, Cost, MF);
2067 RegPressure[RCId] += Cost;
2068 break;
2069 }
2070 }
2071
2072 // We should have this assert, but there may be dead SDNodes that never
2073 // materialize as SUnits, so they don't appear to generate liveness.
2074 //assert(SU->NumRegDefsLeft == 0 && "not all regdefs have scheduled uses");
2075 int SkipRegDefs = (int)SU->NumRegDefsLeft;
2076 for (ScheduleDAGSDNodes::RegDefIter RegDefPos(SU, scheduleDAG);
2077 RegDefPos.IsValid(); RegDefPos.Advance(), --SkipRegDefs) {
2078 if (SkipRegDefs > 0)
2079 continue;
2080 unsigned RCId, Cost;
2081 GetCostForDef(RegDefPos, TLI, TII, TRI, RCId, Cost, MF);
2082 if (RegPressure[RCId] < Cost) {
2083 // Register pressure tracking is imprecise. This can happen. But we try
2084 // hard not to let it happen because it likely results in poor scheduling.
2085 DEBUG(dbgs() << " SU(" << SU->NodeNum << ") has too many regdefs\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("pre-RA-sched")) { dbgs() << " SU(" << SU->NodeNum
<< ") has too many regdefs\n"; } } while (false)
;
2086 RegPressure[RCId] = 0;
2087 }
2088 else {
2089 RegPressure[RCId] -= Cost;
2090 }
2091 }
2092 DEBUG(dumpRegPressure())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("pre-RA-sched")) { dumpRegPressure(); } } while (false)
;
2093}
2094
2095void RegReductionPQBase::unscheduledNode(SUnit *SU) {
2096 if (!TracksRegPressure)
2097 return;
2098
2099 const SDNode *N = SU->getNode();
2100 if (!N) return;
2101
2102 if (!N->isMachineOpcode()) {
2103 if (N->getOpcode() != ISD::CopyToReg)
2104 return;
2105 } else {
2106 unsigned Opc = N->getMachineOpcode();
2107 if (Opc == TargetOpcode::EXTRACT_SUBREG ||
2108 Opc == TargetOpcode::INSERT_SUBREG ||
2109 Opc == TargetOpcode::SUBREG_TO_REG ||
2110 Opc == TargetOpcode::REG_SEQUENCE ||
2111 Opc == TargetOpcode::IMPLICIT_DEF)
2112 return;
2113 }
2114
2115 for (const SDep &Pred : SU->Preds) {
2116 if (Pred.isCtrl())
2117 continue;
2118 SUnit *PredSU = Pred.getSUnit();
2119 // NumSuccsLeft counts all deps. Don't compare it with NumSuccs which only
2120 // counts data deps.
2121 if (PredSU->NumSuccsLeft != PredSU->Succs.size())
2122 continue;
2123 const SDNode *PN = PredSU->getNode();
2124 if (!PN->isMachineOpcode()) {
2125 if (PN->getOpcode() == ISD::CopyFromReg) {
2126 MVT VT = PN->getSimpleValueType(0);
2127 unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
2128 RegPressure[RCId] += TLI->getRepRegClassCostFor(VT);
2129 }
2130 continue;
2131 }
2132 unsigned POpc = PN->getMachineOpcode();
2133 if (POpc == TargetOpcode::IMPLICIT_DEF)
2134 continue;
2135 if (POpc == TargetOpcode::EXTRACT_SUBREG ||
2136 POpc == TargetOpcode::INSERT_SUBREG ||
2137 POpc == TargetOpcode::SUBREG_TO_REG) {
2138 MVT VT = PN->getSimpleValueType(0);
2139 unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
2140 RegPressure[RCId] += TLI->getRepRegClassCostFor(VT);
2141 continue;
2142 }
2143 unsigned NumDefs = TII->get(PN->getMachineOpcode()).getNumDefs();
2144 for (unsigned i = 0; i != NumDefs; ++i) {
2145 MVT VT = PN->getSimpleValueType(i);
2146 if (!PN->hasAnyUseOfValue(i))
2147 continue;
2148 unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
2149 if (RegPressure[RCId] < TLI->getRepRegClassCostFor(VT))
2150 // Register pressure tracking is imprecise. This can happen.
2151 RegPressure[RCId] = 0;
2152 else
2153 RegPressure[RCId] -= TLI->getRepRegClassCostFor(VT);
2154 }
2155 }
2156
2157 // Check for isMachineOpcode() as PrescheduleNodesWithMultipleUses()
2158 // may transfer data dependencies to CopyToReg.
2159 if (SU->NumSuccs && N->isMachineOpcode()) {
2160 unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs();
2161 for (unsigned i = NumDefs, e = N->getNumValues(); i != e; ++i) {
2162 MVT VT = N->getSimpleValueType(i);
2163 if (VT == MVT::Glue || VT == MVT::Other)
2164 continue;
2165 if (!N->hasAnyUseOfValue(i))
2166 continue;
2167 unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
2168 RegPressure[RCId] += TLI->getRepRegClassCostFor(VT);
2169 }
2170 }
2171
2172 DEBUG(dumpRegPressure())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("pre-RA-sched")) { dumpRegPressure(); } } while (false)
;
2173}
2174
2175//===----------------------------------------------------------------------===//
2176// Dynamic Node Priority for Register Pressure Reduction
2177//===----------------------------------------------------------------------===//
2178
2179/// closestSucc - Returns the scheduled cycle of the successor which is
2180/// closest to the current cycle.
2181static unsigned closestSucc(const SUnit *SU) {
2182 unsigned MaxHeight = 0;
2183 for (const SDep &Succ : SU->Succs) {
2184 if (Succ.isCtrl()) continue; // ignore chain succs
2185 unsigned Height = Succ.getSUnit()->getHeight();
2186 // If there are bunch of CopyToRegs stacked up, they should be considered
2187 // to be at the same position.
2188 if (Succ.getSUnit()->getNode() &&
2189 Succ.getSUnit()->getNode()->getOpcode() == ISD::CopyToReg)
2190 Height = closestSucc(Succ.getSUnit())+1;
2191 if (Height > MaxHeight)
2192 MaxHeight = Height;
2193 }
2194 return MaxHeight;
2195}
2196
2197/// calcMaxScratches - Returns an cost estimate of the worse case requirement
2198/// for scratch registers, i.e. number of data dependencies.
2199static unsigned calcMaxScratches(const SUnit *SU) {
2200 unsigned Scratches = 0;
2201 for (const SDep &Pred : SU->Preds) {
2202 if (Pred.isCtrl()) continue; // ignore chain preds
2203 Scratches++;
2204 }
2205 return Scratches;
2206}
2207
2208/// hasOnlyLiveInOpers - Return true if SU has only value predecessors that are
2209/// CopyFromReg from a virtual register.
2210static bool hasOnlyLiveInOpers(const SUnit *SU) {
2211 bool RetVal = false;
2212 for (const SDep &Pred : SU->Preds) {
2213 if (Pred.isCtrl()) continue;
2214 const SUnit *PredSU = Pred.getSUnit();
2215 if (PredSU->getNode() &&
2216 PredSU->getNode()->getOpcode() == ISD::CopyFromReg) {
2217 unsigned Reg =
2218 cast<RegisterSDNode>(PredSU->getNode()->getOperand(1))->getReg();
2219 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
2220 RetVal = true;
2221 continue;
2222 }
2223 }
2224 return false;
2225 }
2226 return RetVal;
2227}
2228
2229/// hasOnlyLiveOutUses - Return true if SU has only value successors that are
2230/// CopyToReg to a virtual register. This SU def is probably a liveout and
2231/// it has no other use. It should be scheduled closer to the terminator.
2232static bool hasOnlyLiveOutUses(const SUnit *SU) {
2233 bool RetVal = false;
2234 for (const SDep &Succ : SU->Succs) {
2235 if (Succ.isCtrl()) continue;
2236 const SUnit *SuccSU = Succ.getSUnit();
2237 if (SuccSU->getNode() && SuccSU->getNode()->getOpcode() == ISD::CopyToReg) {
2238 unsigned Reg =
2239 cast<RegisterSDNode>(SuccSU->getNode()->getOperand(1))->getReg();
2240 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
2241 RetVal = true;
2242 continue;
2243 }
2244 }
2245 return false;
2246 }
2247 return RetVal;
2248}
2249
2250// Set isVRegCycle for a node with only live in opers and live out uses. Also
2251// set isVRegCycle for its CopyFromReg operands.
2252//
2253// This is only relevant for single-block loops, in which case the VRegCycle
2254// node is likely an induction variable in which the operand and target virtual
2255// registers should be coalesced (e.g. pre/post increment values). Setting the
2256// isVRegCycle flag helps the scheduler prioritize other uses of the same
2257// CopyFromReg so that this node becomes the virtual register "kill". This
2258// avoids interference between the values live in and out of the block and
2259// eliminates a copy inside the loop.
2260static void initVRegCycle(SUnit *SU) {
2261 if (DisableSchedVRegCycle)
2262 return;
2263
2264 if (!hasOnlyLiveInOpers(SU) || !hasOnlyLiveOutUses(SU))
2265 return;
2266
2267 DEBUG(dbgs() << "VRegCycle: SU(" << SU->NodeNum << ")\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("pre-RA-sched")) { dbgs() << "VRegCycle: SU(" <<
SU->NodeNum << ")\n"; } } while (false)
;
2268
2269 SU->isVRegCycle = true;
2270
2271 for (const SDep &Pred : SU->Preds) {
2272 if (Pred.isCtrl()) continue;
2273 Pred.getSUnit()->isVRegCycle = true;
2274 }
2275}
2276
2277// After scheduling the definition of a VRegCycle, clear the isVRegCycle flag of
2278// CopyFromReg operands. We should no longer penalize other uses of this VReg.
2279static void resetVRegCycle(SUnit *SU) {
2280 if (!SU->isVRegCycle)
2281 return;
2282
2283 for (const SDep &Pred : SU->Preds) {
2284 if (Pred.isCtrl()) continue; // ignore chain preds
2285 SUnit *PredSU = Pred.getSUnit();
2286 if (PredSU->isVRegCycle) {
2287 assert(PredSU->getNode()->getOpcode() == ISD::CopyFromReg &&((PredSU->getNode()->getOpcode() == ISD::CopyFromReg &&
"VRegCycle def must be CopyFromReg") ? static_cast<void>
(0) : __assert_fail ("PredSU->getNode()->getOpcode() == ISD::CopyFromReg && \"VRegCycle def must be CopyFromReg\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp"
, 2288, __PRETTY_FUNCTION__))
2288 "VRegCycle def must be CopyFromReg")((PredSU->getNode()->getOpcode() == ISD::CopyFromReg &&
"VRegCycle def must be CopyFromReg") ? static_cast<void>
(0) : __assert_fail ("PredSU->getNode()->getOpcode() == ISD::CopyFromReg && \"VRegCycle def must be CopyFromReg\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp"
, 2288, __PRETTY_FUNCTION__))
;
2289 Pred.getSUnit()->isVRegCycle = false;
2290 }
2291 }
2292}
2293
2294// Return true if this SUnit uses a CopyFromReg node marked as a VRegCycle. This
2295// means a node that defines the VRegCycle has not been scheduled yet.
2296static bool hasVRegCycleUse(const SUnit *SU) {
2297 // If this SU also defines the VReg, don't hoist it as a "use".
2298 if (SU->isVRegCycle)
2299 return false;
2300
2301 for (const SDep &Pred : SU->Preds) {
2302 if (Pred.isCtrl()) continue; // ignore chain preds
2303 if (Pred.getSUnit()->isVRegCycle &&
2304 Pred.getSUnit()->getNode()->getOpcode() == ISD::CopyFromReg) {
2305 DEBUG(dbgs() << " VReg cycle use: SU (" << SU->NodeNum << ")\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("pre-RA-sched")) { dbgs() << " VReg cycle use: SU (" <<
SU->NodeNum << ")\n"; } } while (false)
;
2306 return true;
2307 }
2308 }
2309 return false;
2310}
2311
2312// Check for either a dependence (latency) or resource (hazard) stall.
2313//
2314// Note: The ScheduleHazardRecognizer interface requires a non-const SU.
2315static bool BUHasStall(SUnit *SU, int Height, RegReductionPQBase *SPQ) {
2316 if ((int)SPQ->getCurCycle() < Height) return true;
2317 if (SPQ->getHazardRec()->getHazardType(SU, 0)
2318 != ScheduleHazardRecognizer::NoHazard)
2319 return true;
2320 return false;
2321}
2322
2323// Return -1 if left has higher priority, 1 if right has higher priority.
2324// Return 0 if latency-based priority is equivalent.
2325static int BUCompareLatency(SUnit *left, SUnit *right, bool checkPref,
2326 RegReductionPQBase *SPQ) {
2327 // Scheduling an instruction that uses a VReg whose postincrement has not yet
2328 // been scheduled will induce a copy. Model this as an extra cycle of latency.
2329 int LPenalty = hasVRegCycleUse(left) ? 1 : 0;
2330 int RPenalty = hasVRegCycleUse(right) ? 1 : 0;
2331 int LHeight = (int)left->getHeight() + LPenalty;
2332 int RHeight = (int)right->getHeight() + RPenalty;
2333
2334 bool LStall = (!checkPref || left->SchedulingPref == Sched::ILP) &&
2335 BUHasStall(left, LHeight, SPQ);
2336 bool RStall = (!checkPref || right->SchedulingPref == Sched::ILP) &&
2337 BUHasStall(right, RHeight, SPQ);
2338
2339 // If scheduling one of the node will cause a pipeline stall, delay it.
2340 // If scheduling either one of the node will cause a pipeline stall, sort
2341 // them according to their height.
2342 if (LStall) {
2343 if (!RStall)
2344 return 1;
2345 if (LHeight != RHeight)
2346 return LHeight > RHeight ? 1 : -1;
2347 } else if (RStall)
2348 return -1;
2349
2350 // If either node is scheduling for latency, sort them by height/depth
2351 // and latency.
2352 if (!checkPref || (left->SchedulingPref == Sched::ILP ||
2353 right->SchedulingPref == Sched::ILP)) {
2354 // If neither instruction stalls (!LStall && !RStall) and HazardRecognizer
2355 // is enabled, grouping instructions by cycle, then its height is already
2356 // covered so only its depth matters. We also reach this point if both stall
2357 // but have the same height.
2358 if (!SPQ->getHazardRec()->isEnabled()) {
2359 if (LHeight != RHeight)
2360 return LHeight > RHeight ? 1 : -1;
2361 }
2362 int LDepth = left->getDepth() - LPenalty;
2363 int RDepth = right->getDepth() - RPenalty;
2364 if (LDepth != RDepth) {
2365 DEBUG(dbgs() << " Comparing latency of SU (" << left->NodeNumdo { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("pre-RA-sched")) { dbgs() << " Comparing latency of SU ("
<< left->NodeNum << ") depth " << LDepth
<< " vs SU (" << right->NodeNum << ") depth "
<< RDepth << "\n"; } } while (false)
2366 << ") depth " << LDepth << " vs SU (" << right->NodeNumdo { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("pre-RA-sched")) { dbgs() << " Comparing latency of SU ("
<< left->NodeNum << ") depth " << LDepth
<< " vs SU (" << right->NodeNum << ") depth "
<< RDepth << "\n"; } } while (false)
2367 << ") depth " << RDepth << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("pre-RA-sched")) { dbgs() << " Comparing latency of SU ("
<< left->NodeNum << ") depth " << LDepth
<< " vs SU (" << right->NodeNum << ") depth "
<< RDepth << "\n"; } } while (false)
;
2368 return LDepth < RDepth ? 1 : -1;
2369 }
2370 if (left->Latency != right->Latency)
2371 return left->Latency > right->Latency ? 1 : -1;
2372 }
2373 return 0;
2374}
2375
2376static bool BURRSort(SUnit *left, SUnit *right, RegReductionPQBase *SPQ) {
2377 // Schedule physical register definitions close to their use. This is
2378 // motivated by microarchitectures that can fuse cmp+jump macro-ops. But as
2379 // long as shortening physreg live ranges is generally good, we can defer
2380 // creating a subtarget hook.
2381 if (!DisableSchedPhysRegJoin) {
2382 bool LHasPhysReg = left->hasPhysRegDefs;
2383 bool RHasPhysReg = right->hasPhysRegDefs;
2384 if (LHasPhysReg != RHasPhysReg) {
2385 #ifndef NDEBUG
2386 static const char *const PhysRegMsg[] = { " has no physreg",
2387 " defines a physreg" };
2388 #endif
2389 DEBUG(dbgs() << " SU (" << left->NodeNum << ") "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("pre-RA-sched")) { dbgs() << " SU (" << left->
NodeNum << ") " << PhysRegMsg[LHasPhysReg] <<
" SU(" << right->NodeNum << ") " << PhysRegMsg
[RHasPhysReg] << "\n"; } } while (false)
2390 << PhysRegMsg[LHasPhysReg] << " SU(" << right->NodeNum << ") "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("pre-RA-sched")) { dbgs() << " SU (" << left->
NodeNum << ") " << PhysRegMsg[LHasPhysReg] <<
" SU(" << right->NodeNum << ") " << PhysRegMsg
[RHasPhysReg] << "\n"; } } while (false)
2391 << PhysRegMsg[RHasPhysReg] << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("pre-RA-sched")) { dbgs() << " SU (" << left->
NodeNum << ") " << PhysRegMsg[LHasPhysReg] <<
" SU(" << right->NodeNum << ") " << PhysRegMsg
[RHasPhysReg] << "\n"; } } while (false)
;
2392 return LHasPhysReg < RHasPhysReg;
2393 }
2394 }
2395
2396 // Prioritize by Sethi-Ulmann number and push CopyToReg nodes down.
2397 unsigned LPriority = SPQ->getNodePriority(left);
2398 unsigned RPriority = SPQ->getNodePriority(right);
2399
2400 // Be really careful about hoisting call operands above previous calls.
2401 // Only allows it if it would reduce register pressure.
2402 if (left->isCall && right->isCallOp) {
2403 unsigned RNumVals = right->getNode()->getNumValues();
2404 RPriority = (RPriority > RNumVals) ? (RPriority - RNumVals) : 0;
2405 }
2406 if (right->isCall && left->isCallOp) {
2407 unsigned LNumVals = left->getNode()->getNumValues();
2408 LPriority = (LPriority > LNumVals) ? (LPriority - LNumVals) : 0;
2409 }
2410
2411 if (LPriority != RPriority)
2412 return LPriority > RPriority;
2413
2414 // One or both of the nodes are calls and their sethi-ullman numbers are the
2415 // same, then keep source order.
2416 if (left->isCall || right->isCall) {
2417 unsigned LOrder = SPQ->getNodeOrdering(left);
2418 unsigned ROrder = SPQ->getNodeOrdering(right);
2419
2420 // Prefer an ordering where the lower the non-zero order number, the higher
2421 // the preference.
2422 if ((LOrder || ROrder) && LOrder != ROrder)
2423 return LOrder != 0 && (LOrder < ROrder || ROrder == 0);
2424 }
2425
2426 // Try schedule def + use closer when Sethi-Ullman numbers are the same.
2427 // e.g.
2428 // t1 = op t2, c1
2429 // t3 = op t4, c2
2430 //
2431 // and the following instructions are both ready.
2432 // t2 = op c3
2433 // t4 = op c4
2434 //
2435 // Then schedule t2 = op first.
2436 // i.e.
2437 // t4 = op c4
2438 // t2 = op c3
2439 // t1 = op t2, c1
2440 // t3 = op t4, c2
2441 //
2442 // This creates more short live intervals.
2443 unsigned LDist = closestSucc(left);
2444 unsigned RDist = closestSucc(right);
2445 if (LDist != RDist)
2446 return LDist < RDist;
2447
2448 // How many registers becomes live when the node is scheduled.
2449 unsigned LScratch = calcMaxScratches(left);
2450 unsigned RScratch = calcMaxScratches(right);
2451 if (LScratch != RScratch)
2452 return LScratch > RScratch;
2453
2454 // Comparing latency against a call makes little sense unless the node
2455 // is register pressure-neutral.
2456 if ((left->isCall && RPriority > 0) || (right->isCall && LPriority > 0))
2457 return (left->NodeQueueId > right->NodeQueueId);
2458
2459 // Do not compare latencies when one or both of the nodes are calls.
2460 if (!DisableSchedCycles &&
2461 !(left->isCall || right->isCall)) {
2462 int result = BUCompareLatency(left, right, false /*checkPref*/, SPQ);
2463 if (result != 0)
2464 return result > 0;
2465 }
2466 else {
2467 if (left->getHeight() != right->getHeight())
2468 return left->getHeight() > right->getHeight();
2469
2470 if (left->getDepth() != right->getDepth())
2471 return left->getDepth() < right->getDepth();
2472 }
2473
2474 assert(left->NodeQueueId && right->NodeQueueId &&((left->NodeQueueId && right->NodeQueueId &&
"NodeQueueId cannot be zero") ? static_cast<void> (0) :
__assert_fail ("left->NodeQueueId && right->NodeQueueId && \"NodeQueueId cannot be zero\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp"
, 2475, __PRETTY_FUNCTION__))
2475 "NodeQueueId cannot be zero")((left->NodeQueueId && right->NodeQueueId &&
"NodeQueueId cannot be zero") ? static_cast<void> (0) :
__assert_fail ("left->NodeQueueId && right->NodeQueueId && \"NodeQueueId cannot be zero\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp"
, 2475, __PRETTY_FUNCTION__))
;
2476 return (left->NodeQueueId > right->NodeQueueId);
2477}
2478
2479// Bottom up
2480bool bu_ls_rr_sort::operator()(SUnit *left, SUnit *right) const {
2481 if (int res = checkSpecialNodes(left, right))
2482 return res > 0;
2483
2484 return BURRSort(left, right, SPQ);
2485}
2486
2487// Source order, otherwise bottom up.
2488bool src_ls_rr_sort::operator()(SUnit *left, SUnit *right) const {
2489 if (int res = checkSpecialNodes(left, right))
2490 return res > 0;
2491
2492 unsigned LOrder = SPQ->getNodeOrdering(left);
2493 unsigned ROrder = SPQ->getNodeOrdering(right);
2494
2495 // Prefer an ordering where the lower the non-zero order number, the higher
2496 // the preference.
2497 if ((LOrder || ROrder) && LOrder != ROrder)
2498 return LOrder != 0 && (LOrder < ROrder || ROrder == 0);
2499
2500 return BURRSort(left, right, SPQ);
2501}
2502
2503// If the time between now and when the instruction will be ready can cover
2504// the spill code, then avoid adding it to the ready queue. This gives long
2505// stalls highest priority and allows hoisting across calls. It should also
2506// speed up processing the available queue.
2507bool hybrid_ls_rr_sort::isReady(SUnit *SU, unsigned CurCycle) const {
2508 static const unsigned ReadyDelay = 3;
2509
2510 if (SPQ->MayReduceRegPressure(SU)) return true;
2511
2512 if (SU->getHeight() > (CurCycle + ReadyDelay)) return false;
2513
2514 if (SPQ->getHazardRec()->getHazardType(SU, -ReadyDelay)
2515 != ScheduleHazardRecognizer::NoHazard)
2516 return false;
2517
2518 return true;
2519}
2520
2521// Return true if right should be scheduled with higher priority than left.
2522bool hybrid_ls_rr_sort::operator()(SUnit *left, SUnit *right) const {
2523 if (int res = checkSpecialNodes(left, right))
2524 return res > 0;
2525
2526 if (left->isCall || right->isCall)
2527 // No way to compute latency of calls.
2528 return BURRSort(left, right, SPQ);
2529
2530 bool LHigh = SPQ->HighRegPressure(left);
2531 bool RHigh = SPQ->HighRegPressure(right);
2532 // Avoid causing spills. If register pressure is high, schedule for
2533 // register pressure reduction.
2534 if (LHigh && !RHigh) {
2535 DEBUG(dbgs() << " pressure SU(" << left->NodeNum << ") > SU("do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("pre-RA-sched")) { dbgs() << " pressure SU(" <<
left->NodeNum << ") > SU(" << right->NodeNum
<< ")\n"; } } while (false)
2536 << right->NodeNum << ")\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("pre-RA-sched")) { dbgs() << " pressure SU(" <<
left->NodeNum << ") > SU(" << right->NodeNum
<< ")\n"; } } while (false)
;
2537 return true;
2538 }
2539 else if (!LHigh && RHigh) {
2540 DEBUG(dbgs() << " pressure SU(" << right->NodeNum << ") > SU("do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("pre-RA-sched")) { dbgs() << " pressure SU(" <<
right->NodeNum << ") > SU(" << left->NodeNum
<< ")\n"; } } while (false)
2541 << left->NodeNum << ")\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("pre-RA-sched")) { dbgs() << " pressure SU(" <<
right->NodeNum << ") > SU(" << left->NodeNum
<< ")\n"; } } while (false)
;
2542 return false;
2543 }
2544 if (!LHigh && !RHigh) {
2545 int result = BUCompareLatency(left, right, true /*checkPref*/, SPQ);
2546 if (result != 0)
2547 return result > 0;
2548 }
2549 return BURRSort(left, right, SPQ);
2550}
2551
2552// Schedule as many instructions in each cycle as possible. So don't make an
2553// instruction available unless it is ready in the current cycle.
2554bool ilp_ls_rr_sort::isReady(SUnit *SU, unsigned CurCycle) const {
2555 if (SU->getHeight() > CurCycle) return false;
2556
2557 if (SPQ->getHazardRec()->getHazardType(SU, 0)
2558 != ScheduleHazardRecognizer::NoHazard)
2559 return false;
2560
2561 return true;
2562}
2563
2564static bool canEnableCoalescing(SUnit *SU) {
2565 unsigned Opc = SU->getNode() ? SU->getNode()->getOpcode() : 0;
2566 if (Opc == ISD::TokenFactor || Opc == ISD::CopyToReg)
2567 // CopyToReg should be close to its uses to facilitate coalescing and
2568 // avoid spilling.
2569 return true;
2570
2571 if (Opc == TargetOpcode::EXTRACT_SUBREG ||
2572 Opc == TargetOpcode::SUBREG_TO_REG ||
2573 Opc == TargetOpcode::INSERT_SUBREG)
2574 // EXTRACT_SUBREG, INSERT_SUBREG, and SUBREG_TO_REG nodes should be
2575 // close to their uses to facilitate coalescing.
2576 return true;
2577
2578 if (SU->NumPreds == 0 && SU->NumSuccs != 0)
2579 // If SU does not have a register def, schedule it close to its uses
2580 // because it does not lengthen any live ranges.
2581 return true;
2582
2583 return false;
2584}
2585
2586// list-ilp is currently an experimental scheduler that allows various
2587// heuristics to be enabled prior to the normal register reduction logic.
2588bool ilp_ls_rr_sort::operator()(SUnit *left, SUnit *right) const {
2589 if (int res = checkSpecialNodes(left, right))
2590 return res > 0;
2591
2592 if (left->isCall || right->isCall)
2593 // No way to compute latency of calls.
2594 return BURRSort(left, right, SPQ);
2595
2596 unsigned LLiveUses = 0, RLiveUses = 0;
2597 int LPDiff = 0, RPDiff = 0;
2598 if (!DisableSchedRegPressure || !DisableSchedLiveUses) {
2599 LPDiff = SPQ->RegPressureDiff(left, LLiveUses);
2600 RPDiff = SPQ->RegPressureDiff(right, RLiveUses);
2601 }
2602 if (!DisableSchedRegPressure && LPDiff != RPDiff) {
2603 DEBUG(dbgs() << "RegPressureDiff SU(" << left->NodeNum << "): " << LPDiffdo { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("pre-RA-sched")) { dbgs() << "RegPressureDiff SU(" <<
left->NodeNum << "): " << LPDiff << " != SU("
<< right->NodeNum << "): " << RPDiff <<
"\n"; } } while (false)
2604 << " != SU(" << right->NodeNum << "): " << RPDiff << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("pre-RA-sched")) { dbgs() << "RegPressureDiff SU(" <<
left->NodeNum << "): " << LPDiff << " != SU("
<< right->NodeNum << "): " << RPDiff <<
"\n"; } } while (false)
;
2605 return LPDiff > RPDiff;
2606 }
2607
2608 if (!DisableSchedRegPressure && (LPDiff > 0 || RPDiff > 0)) {
2609 bool LReduce = canEnableCoalescing(left);
2610 bool RReduce = canEnableCoalescing(right);
2611 if (LReduce && !RReduce) return false;
2612 if (RReduce && !LReduce) return true;
2613 }
2614
2615 if (!DisableSchedLiveUses && (LLiveUses != RLiveUses)) {
2616 DEBUG(dbgs() << "Live uses SU(" << left->NodeNum << "): " << LLiveUsesdo { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("pre-RA-sched")) { dbgs() << "Live uses SU(" << left
->NodeNum << "): " << LLiveUses << " != SU("
<< right->NodeNum << "): " << RLiveUses
<< "\n"; } } while (false)
2617 << " != SU(" << right->NodeNum << "): " << RLiveUses << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("pre-RA-sched")) { dbgs() << "Live uses SU(" << left
->NodeNum << "): " << LLiveUses << " != SU("
<< right->NodeNum << "): " << RLiveUses
<< "\n"; } } while (false)
;
2618 return LLiveUses < RLiveUses;
2619 }
2620
2621 if (!DisableSchedStalls) {
2622 bool LStall = BUHasStall(left, left->getHeight(), SPQ);
2623 bool RStall = BUHasStall(right, right->getHeight(), SPQ);
2624 if (LStall != RStall)
2625 return left->getHeight() > right->getHeight();
2626 }
2627
2628 if (!DisableSchedCriticalPath) {
2629 int spread = (int)left->getDepth() - (int)right->getDepth();
2630 if (std::abs(spread) > MaxReorderWindow) {
2631 DEBUG(dbgs() << "Depth of SU(" << left->NodeNum << "): "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("pre-RA-sched")) { dbgs() << "Depth of SU(" << left
->NodeNum << "): " << left->getDepth() <<
" != SU(" << right->NodeNum << "): " <<
right->getDepth() << "\n"; } } while (false)
2632 << left->getDepth() << " != SU(" << right->NodeNum << "): "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("pre-RA-sched")) { dbgs() << "Depth of SU(" << left
->NodeNum << "): " << left->getDepth() <<
" != SU(" << right->NodeNum << "): " <<
right->getDepth() << "\n"; } } while (false)
2633 << right->getDepth() << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("pre-RA-sched")) { dbgs() << "Depth of SU(" << left
->NodeNum << "): " << left->getDepth() <<
" != SU(" << right->NodeNum << "): " <<
right->getDepth() << "\n"; } } while (false)
;
2634 return left->getDepth() < right->getDepth();
2635 }
2636 }
2637
2638 if (!DisableSchedHeight && left->getHeight() != right->getHeight()) {
2639 int spread = (int)left->getHeight() - (int)right->getHeight();
2640 if (std::abs(spread) > MaxReorderWindow)
2641 return left->getHeight() > right->getHeight();
2642 }
2643
2644 return BURRSort(left, right, SPQ);
2645}
2646
2647void RegReductionPQBase::initNodes(std::vector<SUnit> &sunits) {
2648 SUnits = &sunits;
2649 // Add pseudo dependency edges for two-address nodes.
2650 if (!Disable2AddrHack)
2651 AddPseudoTwoAddrDeps();
2652 // Reroute edges to nodes with multiple uses.
2653 if (!TracksRegPressure && !SrcOrder)
2654 PrescheduleNodesWithMultipleUses();
2655 // Calculate node priorities.
2656 CalculateSethiUllmanNumbers();
2657
2658 // For single block loops, mark nodes that look like canonical IV increments.
2659 if (scheduleDAG->BB->isSuccessor(scheduleDAG->BB))
2660 for (SUnit &SU : sunits)
2661 initVRegCycle(&SU);
2662}
2663
2664//===----------------------------------------------------------------------===//
2665// Preschedule for Register Pressure
2666//===----------------------------------------------------------------------===//
2667
2668bool RegReductionPQBase::canClobber(const SUnit *SU, const SUnit *Op) {
2669 if (SU->isTwoAddress) {
2670 unsigned Opc = SU->getNode()->getMachineOpcode();
2671 const MCInstrDesc &MCID = TII->get(Opc);
2672 unsigned NumRes = MCID.getNumDefs();
2673 unsigned NumOps = MCID.getNumOperands() - NumRes;
2674 for (unsigned i = 0; i != NumOps; ++i) {
2675 if (MCID.getOperandConstraint(i+NumRes, MCOI::TIED_TO) != -1) {
2676 SDNode *DU = SU->getNode()->getOperand(i).getNode();
2677 if (DU->getNodeId() != -1 &&
2678 Op->OrigNode == &(*SUnits)[DU->getNodeId()])
2679 return true;
2680 }
2681 }
2682 }
2683 return false;
2684}
2685
2686/// canClobberReachingPhysRegUse - True if SU would clobber one of it's
2687/// successor's explicit physregs whose definition can reach DepSU.
2688/// i.e. DepSU should not be scheduled above SU.
2689static bool canClobberReachingPhysRegUse(const SUnit *DepSU, const SUnit *SU,
2690 ScheduleDAGRRList *scheduleDAG,
2691 const TargetInstrInfo *TII,
2692 const TargetRegisterInfo *TRI) {
2693 const MCPhysReg *ImpDefs
2694 = TII->get(SU->getNode()->getMachineOpcode()).getImplicitDefs();
2695 const uint32_t *RegMask = getNodeRegMask(SU->getNode());
2696 if(!ImpDefs && !RegMask)
2697 return false;
2698
2699 for (const SDep &Succ : SU->Succs) {
2700 SUnit *SuccSU = Succ.getSUnit();
2701 for (const SDep &SuccPred : SuccSU->Preds) {
2702 if (!SuccPred.isAssignedRegDep())
2703 continue;
2704
2705 if (RegMask &&
2706 MachineOperand::clobbersPhysReg(RegMask, SuccPred.getReg()) &&
2707 scheduleDAG->IsReachable(DepSU, SuccPred.getSUnit()))
2708 return true;
2709
2710 if (ImpDefs)
2711 for (const MCPhysReg *ImpDef = ImpDefs; *ImpDef; ++ImpDef)
2712 // Return true if SU clobbers this physical register use and the
2713 // definition of the register reaches from DepSU. IsReachable queries
2714 // a topological forward sort of the DAG (following the successors).
2715 if (TRI->regsOverlap(*ImpDef, SuccPred.getReg()) &&
2716 scheduleDAG->IsReachable(DepSU, SuccPred.getSUnit()))
2717 return true;
2718 }
2719 }
2720 return false;
2721}
2722
2723/// canClobberPhysRegDefs - True if SU would clobber one of SuccSU's
2724/// physical register defs.
2725static bool canClobberPhysRegDefs(const SUnit *SuccSU, const SUnit *SU,
2726 const TargetInstrInfo *TII,
2727 const TargetRegisterInfo *TRI) {
2728 SDNode *N = SuccSU->getNode();
2729 unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs();
2730 const MCPhysReg *ImpDefs = TII->get(N->getMachineOpcode()).getImplicitDefs();
2731 assert(ImpDefs && "Caller should check hasPhysRegDefs")((ImpDefs && "Caller should check hasPhysRegDefs") ? static_cast
<void> (0) : __assert_fail ("ImpDefs && \"Caller should check hasPhysRegDefs\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp"
, 2731, __PRETTY_FUNCTION__))
;
2732 for (const SDNode *SUNode = SU->getNode(); SUNode;
2733 SUNode = SUNode->getGluedNode()) {
2734 if (!SUNode->isMachineOpcode())
2735 continue;
2736 const MCPhysReg *SUImpDefs =
2737 TII->get(SUNode->getMachineOpcode()).getImplicitDefs();
2738 const uint32_t *SURegMask = getNodeRegMask(SUNode);
2739 if (!SUImpDefs && !SURegMask)
2740 continue;
2741 for (unsigned i = NumDefs, e = N->getNumValues(); i != e; ++i) {
2742 MVT VT = N->getSimpleValueType(i);
2743 if (VT == MVT::Glue || VT == MVT::Other)
2744 continue;
2745 if (!N->hasAnyUseOfValue(i))
2746 continue;
2747 unsigned Reg = ImpDefs[i - NumDefs];
2748 if (SURegMask && MachineOperand::clobbersPhysReg(SURegMask, Reg))
2749 return true;
2750 if (!SUImpDefs)
2751 continue;
2752 for (;*SUImpDefs; ++SUImpDefs) {
2753 unsigned SUReg = *SUImpDefs;
2754 if (TRI->regsOverlap(Reg, SUReg))
2755 return true;
2756 }
2757 }
2758 }
2759 return false;
2760}
2761
2762/// PrescheduleNodesWithMultipleUses - Nodes with multiple uses
2763/// are not handled well by the general register pressure reduction
2764/// heuristics. When presented with code like this:
2765///
2766/// N
2767/// / |
2768/// / |
2769/// U store
2770/// |
2771/// ...
2772///
2773/// the heuristics tend to push the store up, but since the
2774/// operand of the store has another use (U), this would increase
2775/// the length of that other use (the U->N edge).
2776///
2777/// This function transforms code like the above to route U's
2778/// dependence through the store when possible, like this:
2779///
2780/// N
2781/// ||
2782/// ||
2783/// store
2784/// |
2785/// U
2786/// |
2787/// ...
2788///
2789/// This results in the store being scheduled immediately
2790/// after N, which shortens the U->N live range, reducing
2791/// register pressure.
2792///
2793void RegReductionPQBase::PrescheduleNodesWithMultipleUses() {
2794 // Visit all the nodes in topological order, working top-down.
2795 for (SUnit &SU : *SUnits) {
2796 // For now, only look at nodes with no data successors, such as stores.
2797 // These are especially important, due to the heuristics in
2798 // getNodePriority for nodes with no data successors.
2799 if (SU.NumSuccs != 0)
2800 continue;
2801 // For now, only look at nodes with exactly one data predecessor.
2802 if (SU.NumPreds != 1)
2803 continue;
2804 // Avoid prescheduling copies to virtual registers, which don't behave
2805 // like other nodes from the perspective of scheduling heuristics.
2806 if (SDNode *N = SU.getNode())
2807 if (N->getOpcode() == ISD::CopyToReg &&
2808 TargetRegisterInfo::isVirtualRegister
2809 (cast<RegisterSDNode>(N->getOperand(1))->getReg()))
2810 continue;
2811
2812 // Locate the single data predecessor.
2813 SUnit *PredSU = nullptr;
2814 for (const SDep &Pred : SU.Preds)
2815 if (!Pred.isCtrl()) {
2816 PredSU = Pred.getSUnit();
2817 break;
2818 }
2819 assert(PredSU)((PredSU) ? static_cast<void> (0) : __assert_fail ("PredSU"
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp"
, 2819, __PRETTY_FUNCTION__))
;
2820
2821 // Don't rewrite edges that carry physregs, because that requires additional
2822 // support infrastructure.
2823 if (PredSU->hasPhysRegDefs)
2824 continue;
2825 // Short-circuit the case where SU is PredSU's only data successor.
2826 if (PredSU->NumSuccs == 1)
2827 continue;
2828 // Avoid prescheduling to copies from virtual registers, which don't behave
2829 // like other nodes from the perspective of scheduling heuristics.
2830 if (SDNode *N = SU.getNode())
2831 if (N->getOpcode() == ISD::CopyFromReg &&
2832 TargetRegisterInfo::isVirtualRegister
2833 (cast<RegisterSDNode>(N->getOperand(1))->getReg()))
2834 continue;
2835
2836 // Perform checks on the successors of PredSU.
2837 for (const SDep &PredSucc : PredSU->Succs) {
2838 SUnit *PredSuccSU = PredSucc.getSUnit();
2839 if (PredSuccSU == &SU) continue;
2840 // If PredSU has another successor with no data successors, for
2841 // now don't attempt to choose either over the other.
2842 if (PredSuccSU->NumSuccs == 0)
2843 goto outer_loop_continue;
2844 // Don't break physical register dependencies.
2845 if (SU.hasPhysRegClobbers && PredSuccSU->hasPhysRegDefs)
2846 if (canClobberPhysRegDefs(PredSuccSU, &SU, TII, TRI))
2847 goto outer_loop_continue;
2848 // Don't introduce graph cycles.
2849 if (scheduleDAG->IsReachable(&SU, PredSuccSU))
2850 goto outer_loop_continue;
2851 }
2852
2853 // Ok, the transformation is safe and the heuristics suggest it is
2854 // profitable. Update the graph.
2855 DEBUG(dbgs() << " Prescheduling SU #" << SU.NodeNumdo { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("pre-RA-sched")) { dbgs() << " Prescheduling SU #" <<
SU.NodeNum << " next to PredSU #" << PredSU->
NodeNum << " to guide scheduling in the presence of multiple uses\n"
; } } while (false)
2856 << " next to PredSU #" << PredSU->NodeNumdo { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("pre-RA-sched")) { dbgs() << " Prescheduling SU #" <<
SU.NodeNum << " next to PredSU #" << PredSU->
NodeNum << " to guide scheduling in the presence of multiple uses\n"
; } } while (false)
2857 << " to guide scheduling in the presence of multiple uses\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("pre-RA-sched")) { dbgs() << " Prescheduling SU #" <<
SU.NodeNum << " next to PredSU #" << PredSU->
NodeNum << " to guide scheduling in the presence of multiple uses\n"
; } } while (false)
;
2858 for (unsigned i = 0; i != PredSU->Succs.size(); ++i) {
2859 SDep Edge = PredSU->Succs[i];
2860 assert(!Edge.isAssignedRegDep())((!Edge.isAssignedRegDep()) ? static_cast<void> (0) : __assert_fail
("!Edge.isAssignedRegDep()", "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp"
, 2860, __PRETTY_FUNCTION__))
;
2861 SUnit *SuccSU = Edge.getSUnit();
2862 if (SuccSU != &SU) {
2863 Edge.setSUnit(PredSU);
2864 scheduleDAG->RemovePred(SuccSU, Edge);
2865 scheduleDAG->AddPred(&SU, Edge);
2866 Edge.setSUnit(&SU);
2867 scheduleDAG->AddPred(SuccSU, Edge);
2868 --i;
2869 }
2870 }
2871 outer_loop_continue:;
2872 }
2873}
2874
2875/// AddPseudoTwoAddrDeps - If two nodes share an operand and one of them uses
2876/// it as a def&use operand. Add a pseudo control edge from it to the other
2877/// node (if it won't create a cycle) so the two-address one will be scheduled
2878/// first (lower in the schedule). If both nodes are two-address, favor the
2879/// one that has a CopyToReg use (more likely to be a loop induction update).
2880/// If both are two-address, but one is commutable while the other is not
2881/// commutable, favor the one that's not commutable.
2882void RegReductionPQBase::AddPseudoTwoAddrDeps() {
2883 for (SUnit &SU : *SUnits) {
2884 if (!SU.isTwoAddress)
2885 continue;
2886
2887 SDNode *Node = SU.getNode();
2888 if (!Node || !Node->isMachineOpcode() || SU.getNode()->getGluedNode())
2889 continue;
2890
2891 bool isLiveOut = hasOnlyLiveOutUses(&SU);
2892 unsigned Opc = Node->getMachineOpcode();
2893 const MCInstrDesc &MCID = TII->get(Opc);
2894 unsigned NumRes = MCID.getNumDefs();
2895 unsigned NumOps = MCID.getNumOperands() - NumRes;
2896 for (unsigned j = 0; j != NumOps; ++j) {
2897 if (MCID.getOperandConstraint(j+NumRes, MCOI::TIED_TO) == -1)
2898 continue;
2899 SDNode *DU = SU.getNode()->getOperand(j).getNode();
2900 if (DU->getNodeId() == -1)
2901 continue;
2902 const SUnit *DUSU = &(*SUnits)[DU->getNodeId()];
2903 if (!DUSU)
2904 continue;
2905 for (const SDep &Succ : DUSU->Succs) {
2906 if (Succ.isCtrl())
2907 continue;
2908 SUnit *SuccSU = Succ.getSUnit();
2909 if (SuccSU == &SU)
2910 continue;
2911 // Be conservative. Ignore if nodes aren't at roughly the same
2912 // depth and height.
2913 if (SuccSU->getHeight() < SU.getHeight() &&
2914 (SU.getHeight() - SuccSU->getHeight()) > 1)
2915 continue;
2916 // Skip past COPY_TO_REGCLASS nodes, so that the pseudo edge
2917 // constrains whatever is using the copy, instead of the copy
2918 // itself. In the case that the copy is coalesced, this
2919 // preserves the intent of the pseudo two-address heurietics.
2920 while (SuccSU->Succs.size() == 1 &&
2921 SuccSU->getNode()->isMachineOpcode() &&
2922 SuccSU->getNode()->getMachineOpcode() ==
2923 TargetOpcode::COPY_TO_REGCLASS)
2924 SuccSU = SuccSU->Succs.front().getSUnit();
2925 // Don't constrain non-instruction nodes.
2926 if (!SuccSU->getNode() || !SuccSU->getNode()->isMachineOpcode())
2927 continue;
2928 // Don't constrain nodes with physical register defs if the
2929 // predecessor can clobber them.
2930 if (SuccSU->hasPhysRegDefs && SU.hasPhysRegClobbers) {
2931 if (canClobberPhysRegDefs(SuccSU, &SU, TII, TRI))
2932 continue;
2933 }
2934 // Don't constrain EXTRACT_SUBREG, INSERT_SUBREG, and SUBREG_TO_REG;
2935 // these may be coalesced away. We want them close to their uses.
2936 unsigned SuccOpc = SuccSU->getNode()->getMachineOpcode();
2937 if (SuccOpc == TargetOpcode::EXTRACT_SUBREG ||
2938 SuccOpc == TargetOpcode::INSERT_SUBREG ||
2939 SuccOpc == TargetOpcode::SUBREG_TO_REG)
2940 continue;
2941 if (!canClobberReachingPhysRegUse(SuccSU, &SU, scheduleDAG, TII, TRI) &&
2942 (!canClobber(SuccSU, DUSU) ||
2943 (isLiveOut && !hasOnlyLiveOutUses(SuccSU)) ||
2944 (!SU.isCommutable && SuccSU->isCommutable)) &&
2945 !scheduleDAG->IsReachable(SuccSU, &SU)) {
2946 DEBUG(dbgs() << " Adding a pseudo-two-addr edge from SU #"do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("pre-RA-sched")) { dbgs() << " Adding a pseudo-two-addr edge from SU #"
<< SU.NodeNum << " to SU #" << SuccSU->
NodeNum << "\n"; } } while (false)
2947 << SU.NodeNum << " to SU #" << SuccSU->NodeNum << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("pre-RA-sched")) { dbgs() << " Adding a pseudo-two-addr edge from SU #"
<< SU.NodeNum << " to SU #" << SuccSU->
NodeNum << "\n"; } } while (false)
;
2948 scheduleDAG->AddPred(&SU, SDep(SuccSU, SDep::Artificial));
2949 }
2950 }
2951 }
2952 }
2953}
2954
2955//===----------------------------------------------------------------------===//
2956// Public Constructor Functions
2957//===----------------------------------------------------------------------===//
2958
2959llvm::ScheduleDAGSDNodes *
2960llvm::createBURRListDAGScheduler(SelectionDAGISel *IS,
2961 CodeGenOpt::Level OptLevel) {
2962 const TargetSubtargetInfo &STI = IS->MF->getSubtarget();
2963 const TargetInstrInfo *TII = STI.getInstrInfo();
2964 const TargetRegisterInfo *TRI = STI.getRegisterInfo();
2965
2966 BURegReductionPriorityQueue *PQ =
2967 new BURegReductionPriorityQueue(*IS->MF, false, false, TII, TRI, nullptr);
2968 ScheduleDAGRRList *SD = new ScheduleDAGRRList(*IS->MF, false, PQ, OptLevel);
2969 PQ->setScheduleDAG(SD);
2970 return SD;
2971}
2972
2973llvm::ScheduleDAGSDNodes *
2974llvm::createSourceListDAGScheduler(SelectionDAGISel *IS,
2975 CodeGenOpt::Level OptLevel) {
2976 const TargetSubtargetInfo &STI = IS->MF->getSubtarget();
2977 const TargetInstrInfo *TII = STI.getInstrInfo();
2978 const TargetRegisterInfo *TRI = STI.getRegisterInfo();
2979
2980 SrcRegReductionPriorityQueue *PQ =
2981 new SrcRegReductionPriorityQueue(*IS->MF, false, true, TII, TRI, nullptr);
2982 ScheduleDAGRRList *SD = new ScheduleDAGRRList(*IS->MF, false, PQ, OptLevel);
2983 PQ->setScheduleDAG(SD);
2984 return SD;
2985}
2986
2987llvm::ScheduleDAGSDNodes *
2988llvm::createHybridListDAGScheduler(SelectionDAGISel *IS,
2989 CodeGenOpt::Level OptLevel) {
2990 const TargetSubtargetInfo &STI = IS->MF->getSubtarget();
2991 const TargetInstrInfo *TII = STI.getInstrInfo();
2992 const TargetRegisterInfo *TRI = STI.getRegisterInfo();
2993 const TargetLowering *TLI = IS->TLI;
2994
2995 HybridBURRPriorityQueue *PQ =
2996 new HybridBURRPriorityQueue(*IS->MF, true, false, TII, TRI, TLI);
2997
2998 ScheduleDAGRRList *SD = new ScheduleDAGRRList(*IS->MF, true, PQ, OptLevel);
2999 PQ->setScheduleDAG(SD);
3000 return SD;
3001}
3002
3003llvm::ScheduleDAGSDNodes *
3004llvm::createILPListDAGScheduler(SelectionDAGISel *IS,
3005 CodeGenOpt::Level OptLevel) {
3006 const TargetSubtargetInfo &STI = IS->MF->getSubtarget();
3007 const TargetInstrInfo *TII = STI.getInstrInfo();
3008 const TargetRegisterInfo *TRI = STI.getRegisterInfo();
3009 const TargetLowering *TLI = IS->TLI;
3010
3011 ILPBURRPriorityQueue *PQ =
3012 new ILPBURRPriorityQueue(*IS->MF, true, false, TII, TRI, TLI);
3013 ScheduleDAGRRList *SD = new ScheduleDAGRRList(*IS->MF, true, PQ, OptLevel);
3014 PQ->setScheduleDAG(SD);
3015 return SD;
3016}