Bug Summary

File:lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
Location:line 6453, column 14
Description:Called C++ object pointer is null

Annotated Source Code

1//===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This implements routines for translating from LLVM IR into SelectionDAG IR.
11//
12//===----------------------------------------------------------------------===//
13
14#include "SelectionDAGBuilder.h"
15#include "SDNodeDbgValue.h"
16#include "llvm/ADT/BitVector.h"
17#include "llvm/ADT/Optional.h"
18#include "llvm/ADT/SmallSet.h"
19#include "llvm/ADT/Statistic.h"
20#include "llvm/Analysis/AliasAnalysis.h"
21#include "llvm/Analysis/BranchProbabilityInfo.h"
22#include "llvm/Analysis/ConstantFolding.h"
23#include "llvm/Analysis/TargetLibraryInfo.h"
24#include "llvm/Analysis/ValueTracking.h"
25#include "llvm/CodeGen/Analysis.h"
26#include "llvm/CodeGen/FastISel.h"
27#include "llvm/CodeGen/FunctionLoweringInfo.h"
28#include "llvm/CodeGen/GCMetadata.h"
29#include "llvm/CodeGen/GCStrategy.h"
30#include "llvm/CodeGen/MachineFrameInfo.h"
31#include "llvm/CodeGen/MachineFunction.h"
32#include "llvm/CodeGen/MachineInstrBuilder.h"
33#include "llvm/CodeGen/MachineJumpTableInfo.h"
34#include "llvm/CodeGen/MachineModuleInfo.h"
35#include "llvm/CodeGen/MachineRegisterInfo.h"
36#include "llvm/CodeGen/SelectionDAG.h"
37#include "llvm/CodeGen/StackMaps.h"
38#include "llvm/IR/CallingConv.h"
39#include "llvm/IR/Constants.h"
40#include "llvm/IR/DataLayout.h"
41#include "llvm/IR/DebugInfo.h"
42#include "llvm/IR/DerivedTypes.h"
43#include "llvm/IR/Function.h"
44#include "llvm/IR/GlobalVariable.h"
45#include "llvm/IR/InlineAsm.h"
46#include "llvm/IR/Instructions.h"
47#include "llvm/IR/IntrinsicInst.h"
48#include "llvm/IR/Intrinsics.h"
49#include "llvm/IR/LLVMContext.h"
50#include "llvm/IR/Module.h"
51#include "llvm/IR/Statepoint.h"
52#include "llvm/MC/MCSymbol.h"
53#include "llvm/Support/CommandLine.h"
54#include "llvm/Support/Debug.h"
55#include "llvm/Support/ErrorHandling.h"
56#include "llvm/Support/MathExtras.h"
57#include "llvm/Support/raw_ostream.h"
58#include "llvm/Target/TargetFrameLowering.h"
59#include "llvm/Target/TargetInstrInfo.h"
60#include "llvm/Target/TargetIntrinsicInfo.h"
61#include "llvm/Target/TargetLowering.h"
62#include "llvm/Target/TargetOptions.h"
63#include "llvm/Target/TargetSelectionDAGInfo.h"
64#include "llvm/Target/TargetSubtargetInfo.h"
65#include <algorithm>
66using namespace llvm;
67
68#define DEBUG_TYPE"isel" "isel"
69
70/// LimitFloatPrecision - Generate low-precision inline sequences for
71/// some float libcalls (6, 8 or 12 bits).
72static unsigned LimitFloatPrecision;
73
74static cl::opt<unsigned, true>
75LimitFPPrecision("limit-float-precision",
76 cl::desc("Generate low-precision inline sequences "
77 "for some float libcalls"),
78 cl::location(LimitFloatPrecision),
79 cl::init(0));
80
81// Limit the width of DAG chains. This is important in general to prevent
82// prevent DAG-based analysis from blowing up. For example, alias analysis and
83// load clustering may not complete in reasonable time. It is difficult to
84// recognize and avoid this situation within each individual analysis, and
85// future analyses are likely to have the same behavior. Limiting DAG width is
86// the safe approach, and will be especially important with global DAGs.
87//
88// MaxParallelChains default is arbitrarily high to avoid affecting
89// optimization, but could be lowered to improve compile time. Any ld-ld-st-st
90// sequence over this should have been converted to llvm.memcpy by the
91// frontend. It easy to induce this behavior with .ll code such as:
92// %buffer = alloca [4096 x i8]
93// %data = load [4096 x i8]* %argPtr
94// store [4096 x i8] %data, [4096 x i8]* %buffer
95static const unsigned MaxParallelChains = 64;
96
97static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
98 const SDValue *Parts, unsigned NumParts,
99 MVT PartVT, EVT ValueVT, const Value *V);
100
101/// getCopyFromParts - Create a value that contains the specified legal parts
102/// combined into the value they represent. If the parts combine to a type
103/// larger then ValueVT then AssertOp can be used to specify whether the extra
104/// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
105/// (ISD::AssertSext).
106static SDValue getCopyFromParts(SelectionDAG &DAG, SDLoc DL,
107 const SDValue *Parts,
108 unsigned NumParts, MVT PartVT, EVT ValueVT,
109 const Value *V,
110 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
111 if (ValueVT.isVector())
112 return getCopyFromPartsVector(DAG, DL, Parts, NumParts,
113 PartVT, ValueVT, V);
114
115 assert(NumParts > 0 && "No parts to assemble!")((NumParts > 0 && "No parts to assemble!") ? static_cast
<void> (0) : __assert_fail ("NumParts > 0 && \"No parts to assemble!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 115, __PRETTY_FUNCTION__));
116 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
117 SDValue Val = Parts[0];
118
119 if (NumParts > 1) {
120 // Assemble the value from multiple parts.
121 if (ValueVT.isInteger()) {
122 unsigned PartBits = PartVT.getSizeInBits();
123 unsigned ValueBits = ValueVT.getSizeInBits();
124
125 // Assemble the power of 2 part.
126 unsigned RoundParts = NumParts & (NumParts - 1) ?
127 1 << Log2_32(NumParts) : NumParts;
128 unsigned RoundBits = PartBits * RoundParts;
129 EVT RoundVT = RoundBits == ValueBits ?
130 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
131 SDValue Lo, Hi;
132
133 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
134
135 if (RoundParts > 2) {
136 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2,
137 PartVT, HalfVT, V);
138 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2,
139 RoundParts / 2, PartVT, HalfVT, V);
140 } else {
141 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]);
142 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]);
143 }
144
145 if (TLI.isBigEndian())
146 std::swap(Lo, Hi);
147
148 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
149
150 if (RoundParts < NumParts) {
151 // Assemble the trailing non-power-of-2 part.
152 unsigned OddParts = NumParts - RoundParts;
153 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
154 Hi = getCopyFromParts(DAG, DL,
155 Parts + RoundParts, OddParts, PartVT, OddVT, V);
156
157 // Combine the round and odd parts.
158 Lo = Val;
159 if (TLI.isBigEndian())
160 std::swap(Lo, Hi);
161 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
162 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi);
163 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi,
164 DAG.getConstant(Lo.getValueType().getSizeInBits(),
165 TLI.getPointerTy()));
166 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo);
167 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi);
168 }
169 } else if (PartVT.isFloatingPoint()) {
170 // FP split into multiple FP parts (for ppcf128)
171 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 &&((ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 &&
"Unexpected split") ? static_cast<void> (0) : __assert_fail
("ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 && \"Unexpected split\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 172, __PRETTY_FUNCTION__))
172 "Unexpected split")((ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 &&
"Unexpected split") ? static_cast<void> (0) : __assert_fail
("ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 && \"Unexpected split\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 172, __PRETTY_FUNCTION__));
173 SDValue Lo, Hi;
174 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]);
175 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]);
176 if (TLI.hasBigEndianPartOrdering(ValueVT))
177 std::swap(Lo, Hi);
178 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi);
179 } else {
180 // FP split into integer parts (soft fp)
181 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&((ValueVT.isFloatingPoint() && PartVT.isInteger() &&
!PartVT.isVector() && "Unexpected split") ? static_cast
<void> (0) : __assert_fail ("ValueVT.isFloatingPoint() && PartVT.isInteger() && !PartVT.isVector() && \"Unexpected split\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 182, __PRETTY_FUNCTION__))
182 !PartVT.isVector() && "Unexpected split")((ValueVT.isFloatingPoint() && PartVT.isInteger() &&
!PartVT.isVector() && "Unexpected split") ? static_cast
<void> (0) : __assert_fail ("ValueVT.isFloatingPoint() && PartVT.isInteger() && !PartVT.isVector() && \"Unexpected split\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 182, __PRETTY_FUNCTION__));
183 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
184 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT, V);
185 }
186 }
187
188 // There is now one part, held in Val. Correct it to match ValueVT.
189 EVT PartEVT = Val.getValueType();
190
191 if (PartEVT == ValueVT)
192 return Val;
193
194 if (PartEVT.isInteger() && ValueVT.isInteger()) {
195 if (ValueVT.bitsLT(PartEVT)) {
196 // For a truncate, see if we have any information to
197 // indicate whether the truncated bits will always be
198 // zero or sign-extension.
199 if (AssertOp != ISD::DELETED_NODE)
200 Val = DAG.getNode(AssertOp, DL, PartEVT, Val,
201 DAG.getValueType(ValueVT));
202 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
203 }
204 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val);
205 }
206
207 if (PartEVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
208 // FP_ROUND's are always exact here.
209 if (ValueVT.bitsLT(Val.getValueType()))
210 return DAG.getNode(ISD::FP_ROUND, DL, ValueVT, Val,
211 DAG.getTargetConstant(1, TLI.getPointerTy()));
212
213 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);
214 }
215
216 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits())
217 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
218
219 llvm_unreachable("Unknown mismatch!")::llvm::llvm_unreachable_internal("Unknown mismatch!", "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 219);
220}
221
222static void diagnosePossiblyInvalidConstraint(LLVMContext &Ctx, const Value *V,
223 const Twine &ErrMsg) {
224 const Instruction *I = dyn_cast_or_null<Instruction>(V);
225 if (!V)
226 return Ctx.emitError(ErrMsg);
227
228 const char *AsmError = ", possible invalid constraint for vector type";
229 if (const CallInst *CI = dyn_cast<CallInst>(I))
230 if (isa<InlineAsm>(CI->getCalledValue()))
231 return Ctx.emitError(I, ErrMsg + AsmError);
232
233 return Ctx.emitError(I, ErrMsg);
234}
235
236/// getCopyFromPartsVector - Create a value that contains the specified legal
237/// parts combined into the value they represent. If the parts combine to a
238/// type larger then ValueVT then AssertOp can be used to specify whether the
239/// extra bits are known to be zero (ISD::AssertZext) or sign extended from
240/// ValueVT (ISD::AssertSext).
241static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
242 const SDValue *Parts, unsigned NumParts,
243 MVT PartVT, EVT ValueVT, const Value *V) {
244 assert(ValueVT.isVector() && "Not a vector value")((ValueVT.isVector() && "Not a vector value") ? static_cast
<void> (0) : __assert_fail ("ValueVT.isVector() && \"Not a vector value\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 244, __PRETTY_FUNCTION__));
245 assert(NumParts > 0 && "No parts to assemble!")((NumParts > 0 && "No parts to assemble!") ? static_cast
<void> (0) : __assert_fail ("NumParts > 0 && \"No parts to assemble!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 245, __PRETTY_FUNCTION__));
246 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
247 SDValue Val = Parts[0];
248
249 // Handle a multi-element vector.
250 if (NumParts > 1) {
251 EVT IntermediateVT;
252 MVT RegisterVT;
253 unsigned NumIntermediates;
254 unsigned NumRegs =
255 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
256 NumIntermediates, RegisterVT);
257 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!")((NumRegs == NumParts && "Part count doesn't match vector breakdown!"
) ? static_cast<void> (0) : __assert_fail ("NumRegs == NumParts && \"Part count doesn't match vector breakdown!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 257, __PRETTY_FUNCTION__));
258 NumParts = NumRegs; // Silence a compiler warning.
259 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!")((RegisterVT == PartVT && "Part type doesn't match vector breakdown!"
) ? static_cast<void> (0) : __assert_fail ("RegisterVT == PartVT && \"Part type doesn't match vector breakdown!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 259, __PRETTY_FUNCTION__));
260 assert(RegisterVT == Parts[0].getSimpleValueType() &&((RegisterVT == Parts[0].getSimpleValueType() && "Part type doesn't match part!"
) ? static_cast<void> (0) : __assert_fail ("RegisterVT == Parts[0].getSimpleValueType() && \"Part type doesn't match part!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 261, __PRETTY_FUNCTION__))
261 "Part type doesn't match part!")((RegisterVT == Parts[0].getSimpleValueType() && "Part type doesn't match part!"
) ? static_cast<void> (0) : __assert_fail ("RegisterVT == Parts[0].getSimpleValueType() && \"Part type doesn't match part!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 261, __PRETTY_FUNCTION__));
262
263 // Assemble the parts into intermediate operands.
264 SmallVector<SDValue, 8> Ops(NumIntermediates);
265 if (NumIntermediates == NumParts) {
266 // If the register was not expanded, truncate or copy the value,
267 // as appropriate.
268 for (unsigned i = 0; i != NumParts; ++i)
269 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1,
270 PartVT, IntermediateVT, V);
271 } else if (NumParts > 0) {
272 // If the intermediate type was expanded, build the intermediate
273 // operands from the parts.
274 assert(NumParts % NumIntermediates == 0 &&((NumParts % NumIntermediates == 0 && "Must expand into a divisible number of parts!"
) ? static_cast<void> (0) : __assert_fail ("NumParts % NumIntermediates == 0 && \"Must expand into a divisible number of parts!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 275, __PRETTY_FUNCTION__))
275 "Must expand into a divisible number of parts!")((NumParts % NumIntermediates == 0 && "Must expand into a divisible number of parts!"
) ? static_cast<void> (0) : __assert_fail ("NumParts % NumIntermediates == 0 && \"Must expand into a divisible number of parts!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 275, __PRETTY_FUNCTION__));
276 unsigned Factor = NumParts / NumIntermediates;
277 for (unsigned i = 0; i != NumIntermediates; ++i)
278 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor,
279 PartVT, IntermediateVT, V);
280 }
281
282 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
283 // intermediate operands.
284 Val = DAG.getNode(IntermediateVT.isVector() ? ISD::CONCAT_VECTORS
285 : ISD::BUILD_VECTOR,
286 DL, ValueVT, Ops);
287 }
288
289 // There is now one part, held in Val. Correct it to match ValueVT.
290 EVT PartEVT = Val.getValueType();
291
292 if (PartEVT == ValueVT)
293 return Val;
294
295 if (PartEVT.isVector()) {
296 // If the element type of the source/dest vectors are the same, but the
297 // parts vector has more elements than the value vector, then we have a
298 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the
299 // elements we want.
300 if (PartEVT.getVectorElementType() == ValueVT.getVectorElementType()) {
301 assert(PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements() &&((PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements
() && "Cannot narrow, it would be a lossy transformation"
) ? static_cast<void> (0) : __assert_fail ("PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements() && \"Cannot narrow, it would be a lossy transformation\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 302, __PRETTY_FUNCTION__))
302 "Cannot narrow, it would be a lossy transformation")((PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements
() && "Cannot narrow, it would be a lossy transformation"
) ? static_cast<void> (0) : __assert_fail ("PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements() && \"Cannot narrow, it would be a lossy transformation\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 302, __PRETTY_FUNCTION__));
303 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
304 DAG.getConstant(0, TLI.getVectorIdxTy()));
305 }
306
307 // Vector/Vector bitcast.
308 if (ValueVT.getSizeInBits() == PartEVT.getSizeInBits())
309 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
310
311 assert(PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements() &&((PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements
() && "Cannot handle this kind of promotion") ? static_cast
<void> (0) : __assert_fail ("PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements() && \"Cannot handle this kind of promotion\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 312, __PRETTY_FUNCTION__))
312 "Cannot handle this kind of promotion")((PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements
() && "Cannot handle this kind of promotion") ? static_cast
<void> (0) : __assert_fail ("PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements() && \"Cannot handle this kind of promotion\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 312, __PRETTY_FUNCTION__));
313 // Promoted vector extract
314 bool Smaller = ValueVT.bitsLE(PartEVT);
315 return DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
316 DL, ValueVT, Val);
317
318 }
319
320 // Trivial bitcast if the types are the same size and the destination
321 // vector type is legal.
322 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits() &&
323 TLI.isTypeLegal(ValueVT))
324 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
325
326 // Handle cases such as i8 -> <1 x i1>
327 if (ValueVT.getVectorNumElements() != 1) {
328 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
329 "non-trivial scalar-to-vector conversion");
330 return DAG.getUNDEF(ValueVT);
331 }
332
333 if (ValueVT.getVectorNumElements() == 1 &&
334 ValueVT.getVectorElementType() != PartEVT) {
335 bool Smaller = ValueVT.bitsLE(PartEVT);
336 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
337 DL, ValueVT.getScalarType(), Val);
338 }
339
340 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val);
341}
342
343static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc dl,
344 SDValue Val, SDValue *Parts, unsigned NumParts,
345 MVT PartVT, const Value *V);
346
347/// getCopyToParts - Create a series of nodes that contain the specified value
348/// split into legal parts. If the parts contain more bits than Val, then, for
349/// integers, ExtendKind can be used to specify how to generate the extra bits.
350static void getCopyToParts(SelectionDAG &DAG, SDLoc DL,
351 SDValue Val, SDValue *Parts, unsigned NumParts,
352 MVT PartVT, const Value *V,
353 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
354 EVT ValueVT = Val.getValueType();
355
356 // Handle the vector case separately.
357 if (ValueVT.isVector())
358 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT, V);
359
360 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
361 unsigned PartBits = PartVT.getSizeInBits();
362 unsigned OrigNumParts = NumParts;
363 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!")((TLI.isTypeLegal(PartVT) && "Copying to an illegal type!"
) ? static_cast<void> (0) : __assert_fail ("TLI.isTypeLegal(PartVT) && \"Copying to an illegal type!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 363, __PRETTY_FUNCTION__));
364
365 if (NumParts == 0)
366 return;
367
368 assert(!ValueVT.isVector() && "Vector case handled elsewhere")((!ValueVT.isVector() && "Vector case handled elsewhere"
) ? static_cast<void> (0) : __assert_fail ("!ValueVT.isVector() && \"Vector case handled elsewhere\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 368, __PRETTY_FUNCTION__));
369 EVT PartEVT = PartVT;
370 if (PartEVT == ValueVT) {
371 assert(NumParts == 1 && "No-op copy with multiple parts!")((NumParts == 1 && "No-op copy with multiple parts!")
? static_cast<void> (0) : __assert_fail ("NumParts == 1 && \"No-op copy with multiple parts!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 371, __PRETTY_FUNCTION__));
372 Parts[0] = Val;
373 return;
374 }
375
376 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
377 // If the parts cover more bits than the value has, promote the value.
378 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
379 assert(NumParts == 1 && "Do not know what to promote to!")((NumParts == 1 && "Do not know what to promote to!")
? static_cast<void> (0) : __assert_fail ("NumParts == 1 && \"Do not know what to promote to!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 379, __PRETTY_FUNCTION__));
380 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val);
381 } else {
382 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&(((PartVT.isInteger() || PartVT == MVT::x86mmx) && ValueVT
.isInteger() && "Unknown mismatch!") ? static_cast<
void> (0) : __assert_fail ("(PartVT.isInteger() || PartVT == MVT::x86mmx) && ValueVT.isInteger() && \"Unknown mismatch!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 384, __PRETTY_FUNCTION__))
383 ValueVT.isInteger() &&(((PartVT.isInteger() || PartVT == MVT::x86mmx) && ValueVT
.isInteger() && "Unknown mismatch!") ? static_cast<
void> (0) : __assert_fail ("(PartVT.isInteger() || PartVT == MVT::x86mmx) && ValueVT.isInteger() && \"Unknown mismatch!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 384, __PRETTY_FUNCTION__))
384 "Unknown mismatch!")(((PartVT.isInteger() || PartVT == MVT::x86mmx) && ValueVT
.isInteger() && "Unknown mismatch!") ? static_cast<
void> (0) : __assert_fail ("(PartVT.isInteger() || PartVT == MVT::x86mmx) && ValueVT.isInteger() && \"Unknown mismatch!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 384, __PRETTY_FUNCTION__));
385 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
386 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val);
387 if (PartVT == MVT::x86mmx)
388 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
389 }
390 } else if (PartBits == ValueVT.getSizeInBits()) {
391 // Different types of the same size.
392 assert(NumParts == 1 && PartEVT != ValueVT)((NumParts == 1 && PartEVT != ValueVT) ? static_cast<
void> (0) : __assert_fail ("NumParts == 1 && PartEVT != ValueVT"
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 392, __PRETTY_FUNCTION__));
393 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
394 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
395 // If the parts cover less bits than value has, truncate the value.
396 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&(((PartVT.isInteger() || PartVT == MVT::x86mmx) && ValueVT
.isInteger() && "Unknown mismatch!") ? static_cast<
void> (0) : __assert_fail ("(PartVT.isInteger() || PartVT == MVT::x86mmx) && ValueVT.isInteger() && \"Unknown mismatch!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 398, __PRETTY_FUNCTION__))
397 ValueVT.isInteger() &&(((PartVT.isInteger() || PartVT == MVT::x86mmx) && ValueVT
.isInteger() && "Unknown mismatch!") ? static_cast<
void> (0) : __assert_fail ("(PartVT.isInteger() || PartVT == MVT::x86mmx) && ValueVT.isInteger() && \"Unknown mismatch!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 398, __PRETTY_FUNCTION__))
398 "Unknown mismatch!")(((PartVT.isInteger() || PartVT == MVT::x86mmx) && ValueVT
.isInteger() && "Unknown mismatch!") ? static_cast<
void> (0) : __assert_fail ("(PartVT.isInteger() || PartVT == MVT::x86mmx) && ValueVT.isInteger() && \"Unknown mismatch!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 398, __PRETTY_FUNCTION__));
399 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
400 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
401 if (PartVT == MVT::x86mmx)
402 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
403 }
404
405 // The value may have changed - recompute ValueVT.
406 ValueVT = Val.getValueType();
407 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&((NumParts * PartBits == ValueVT.getSizeInBits() && "Failed to tile the value with PartVT!"
) ? static_cast<void> (0) : __assert_fail ("NumParts * PartBits == ValueVT.getSizeInBits() && \"Failed to tile the value with PartVT!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 408, __PRETTY_FUNCTION__))
408 "Failed to tile the value with PartVT!")((NumParts * PartBits == ValueVT.getSizeInBits() && "Failed to tile the value with PartVT!"
) ? static_cast<void> (0) : __assert_fail ("NumParts * PartBits == ValueVT.getSizeInBits() && \"Failed to tile the value with PartVT!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 408, __PRETTY_FUNCTION__));
409
410 if (NumParts == 1) {
411 if (PartEVT != ValueVT)
412 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
413 "scalar-to-vector conversion failed");
414
415 Parts[0] = Val;
416 return;
417 }
418
419 // Expand the value into multiple parts.
420 if (NumParts & (NumParts - 1)) {
421 // The number of parts is not a power of 2. Split off and copy the tail.
422 assert(PartVT.isInteger() && ValueVT.isInteger() &&((PartVT.isInteger() && ValueVT.isInteger() &&
"Do not know what to expand to!") ? static_cast<void> (
0) : __assert_fail ("PartVT.isInteger() && ValueVT.isInteger() && \"Do not know what to expand to!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 423, __PRETTY_FUNCTION__))
423 "Do not know what to expand to!")((PartVT.isInteger() && ValueVT.isInteger() &&
"Do not know what to expand to!") ? static_cast<void> (
0) : __assert_fail ("PartVT.isInteger() && ValueVT.isInteger() && \"Do not know what to expand to!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 423, __PRETTY_FUNCTION__));
424 unsigned RoundParts = 1 << Log2_32(NumParts);
425 unsigned RoundBits = RoundParts * PartBits;
426 unsigned OddParts = NumParts - RoundParts;
427 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val,
428 DAG.getIntPtrConstant(RoundBits));
429 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT, V);
430
431 if (TLI.isBigEndian())
432 // The odd parts were reversed by getCopyToParts - unreverse them.
433 std::reverse(Parts + RoundParts, Parts + NumParts);
434
435 NumParts = RoundParts;
436 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
437 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
438 }
439
440 // The number of parts is a power of 2. Repeatedly bisect the value using
441 // EXTRACT_ELEMENT.
442 Parts[0] = DAG.getNode(ISD::BITCAST, DL,
443 EVT::getIntegerVT(*DAG.getContext(),
444 ValueVT.getSizeInBits()),
445 Val);
446
447 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
448 for (unsigned i = 0; i < NumParts; i += StepSize) {
449 unsigned ThisBits = StepSize * PartBits / 2;
450 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
451 SDValue &Part0 = Parts[i];
452 SDValue &Part1 = Parts[i+StepSize/2];
453
454 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
455 ThisVT, Part0, DAG.getIntPtrConstant(1));
456 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
457 ThisVT, Part0, DAG.getIntPtrConstant(0));
458
459 if (ThisBits == PartBits && ThisVT != PartVT) {
460 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0);
461 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1);
462 }
463 }
464 }
465
466 if (TLI.isBigEndian())
467 std::reverse(Parts, Parts + OrigNumParts);
468}
469
470
471/// getCopyToPartsVector - Create a series of nodes that contain the specified
472/// value split into legal parts.
473static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc DL,
474 SDValue Val, SDValue *Parts, unsigned NumParts,
475 MVT PartVT, const Value *V) {
476 EVT ValueVT = Val.getValueType();
477 assert(ValueVT.isVector() && "Not a vector")((ValueVT.isVector() && "Not a vector") ? static_cast
<void> (0) : __assert_fail ("ValueVT.isVector() && \"Not a vector\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 477, __PRETTY_FUNCTION__));
478 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
479
480 if (NumParts == 1) {
481 EVT PartEVT = PartVT;
482 if (PartEVT == ValueVT) {
483 // Nothing to do.
484 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
485 // Bitconvert vector->vector case.
486 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
487 } else if (PartVT.isVector() &&
488 PartEVT.getVectorElementType() == ValueVT.getVectorElementType() &&
489 PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements()) {
490 EVT ElementVT = PartVT.getVectorElementType();
491 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in
492 // undef elements.
493 SmallVector<SDValue, 16> Ops;
494 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i)
495 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
496 ElementVT, Val, DAG.getConstant(i,
497 TLI.getVectorIdxTy())));
498
499 for (unsigned i = ValueVT.getVectorNumElements(),
500 e = PartVT.getVectorNumElements(); i != e; ++i)
501 Ops.push_back(DAG.getUNDEF(ElementVT));
502
503 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, Ops);
504
505 // FIXME: Use CONCAT for 2x -> 4x.
506
507 //SDValue UndefElts = DAG.getUNDEF(VectorTy);
508 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts);
509 } else if (PartVT.isVector() &&
510 PartEVT.getVectorElementType().bitsGE(
511 ValueVT.getVectorElementType()) &&
512 PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements()) {
513
514 // Promoted vector extract
515 bool Smaller = PartEVT.bitsLE(ValueVT);
516 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
517 DL, PartVT, Val);
518 } else{
519 // Vector -> scalar conversion.
520 assert(ValueVT.getVectorNumElements() == 1 &&((ValueVT.getVectorNumElements() == 1 && "Only trivial vector-to-scalar conversions should get here!"
) ? static_cast<void> (0) : __assert_fail ("ValueVT.getVectorNumElements() == 1 && \"Only trivial vector-to-scalar conversions should get here!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 521, __PRETTY_FUNCTION__))
521 "Only trivial vector-to-scalar conversions should get here!")((ValueVT.getVectorNumElements() == 1 && "Only trivial vector-to-scalar conversions should get here!"
) ? static_cast<void> (0) : __assert_fail ("ValueVT.getVectorNumElements() == 1 && \"Only trivial vector-to-scalar conversions should get here!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 521, __PRETTY_FUNCTION__));
522 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
523 PartVT, Val, DAG.getConstant(0, TLI.getVectorIdxTy()));
524
525 bool Smaller = ValueVT.bitsLE(PartVT);
526 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
527 DL, PartVT, Val);
528 }
529
530 Parts[0] = Val;
531 return;
532 }
533
534 // Handle a multi-element vector.
535 EVT IntermediateVT;
536 MVT RegisterVT;
537 unsigned NumIntermediates;
538 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
539 IntermediateVT,
540 NumIntermediates, RegisterVT);
541 unsigned NumElements = ValueVT.getVectorNumElements();
542
543 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!")((NumRegs == NumParts && "Part count doesn't match vector breakdown!"
) ? static_cast<void> (0) : __assert_fail ("NumRegs == NumParts && \"Part count doesn't match vector breakdown!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 543, __PRETTY_FUNCTION__));
544 NumParts = NumRegs; // Silence a compiler warning.
545 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!")((RegisterVT == PartVT && "Part type doesn't match vector breakdown!"
) ? static_cast<void> (0) : __assert_fail ("RegisterVT == PartVT && \"Part type doesn't match vector breakdown!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 545, __PRETTY_FUNCTION__));
546
547 // Split the vector into intermediate operands.
548 SmallVector<SDValue, 8> Ops(NumIntermediates);
549 for (unsigned i = 0; i != NumIntermediates; ++i) {
550 if (IntermediateVT.isVector())
551 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL,
552 IntermediateVT, Val,
553 DAG.getConstant(i * (NumElements / NumIntermediates),
554 TLI.getVectorIdxTy()));
555 else
556 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
557 IntermediateVT, Val,
558 DAG.getConstant(i, TLI.getVectorIdxTy()));
559 }
560
561 // Split the intermediate operands into legal parts.
562 if (NumParts == NumIntermediates) {
563 // If the register was not expanded, promote or copy the value,
564 // as appropriate.
565 for (unsigned i = 0; i != NumParts; ++i)
566 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT, V);
567 } else if (NumParts > 0) {
568 // If the intermediate type was expanded, split each the value into
569 // legal parts.
570 assert(NumIntermediates != 0 && "division by zero")((NumIntermediates != 0 && "division by zero") ? static_cast
<void> (0) : __assert_fail ("NumIntermediates != 0 && \"division by zero\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 570, __PRETTY_FUNCTION__));
571 assert(NumParts % NumIntermediates == 0 &&((NumParts % NumIntermediates == 0 && "Must expand into a divisible number of parts!"
) ? static_cast<void> (0) : __assert_fail ("NumParts % NumIntermediates == 0 && \"Must expand into a divisible number of parts!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 572, __PRETTY_FUNCTION__))
572 "Must expand into a divisible number of parts!")((NumParts % NumIntermediates == 0 && "Must expand into a divisible number of parts!"
) ? static_cast<void> (0) : __assert_fail ("NumParts % NumIntermediates == 0 && \"Must expand into a divisible number of parts!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 572, __PRETTY_FUNCTION__));
573 unsigned Factor = NumParts / NumIntermediates;
574 for (unsigned i = 0; i != NumIntermediates; ++i)
575 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT, V);
576 }
577}
578
579namespace {
580 /// RegsForValue - This struct represents the registers (physical or virtual)
581 /// that a particular set of values is assigned, and the type information
582 /// about the value. The most common situation is to represent one value at a
583 /// time, but struct or array values are handled element-wise as multiple
584 /// values. The splitting of aggregates is performed recursively, so that we
585 /// never have aggregate-typed registers. The values at this point do not
586 /// necessarily have legal types, so each value may require one or more
587 /// registers of some legal type.
588 ///
589 struct RegsForValue {
590 /// ValueVTs - The value types of the values, which may not be legal, and
591 /// may need be promoted or synthesized from one or more registers.
592 ///
593 SmallVector<EVT, 4> ValueVTs;
594
595 /// RegVTs - The value types of the registers. This is the same size as
596 /// ValueVTs and it records, for each value, what the type of the assigned
597 /// register or registers are. (Individual values are never synthesized
598 /// from more than one type of register.)
599 ///
600 /// With virtual registers, the contents of RegVTs is redundant with TLI's
601 /// getRegisterType member function, however when with physical registers
602 /// it is necessary to have a separate record of the types.
603 ///
604 SmallVector<MVT, 4> RegVTs;
605
606 /// Regs - This list holds the registers assigned to the values.
607 /// Each legal or promoted value requires one register, and each
608 /// expanded value requires multiple registers.
609 ///
610 SmallVector<unsigned, 4> Regs;
611
612 RegsForValue() {}
613
614 RegsForValue(const SmallVector<unsigned, 4> &regs,
615 MVT regvt, EVT valuevt)
616 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
617
618 RegsForValue(LLVMContext &Context, const TargetLowering &tli,
619 unsigned Reg, Type *Ty) {
620 ComputeValueVTs(tli, Ty, ValueVTs);
621
622 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
623 EVT ValueVT = ValueVTs[Value];
624 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT);
625 MVT RegisterVT = tli.getRegisterType(Context, ValueVT);
626 for (unsigned i = 0; i != NumRegs; ++i)
627 Regs.push_back(Reg + i);
628 RegVTs.push_back(RegisterVT);
629 Reg += NumRegs;
630 }
631 }
632
633 /// append - Add the specified values to this one.
634 void append(const RegsForValue &RHS) {
635 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
636 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
637 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
638 }
639
640 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
641 /// this value and returns the result as a ValueVTs value. This uses
642 /// Chain/Flag as the input and updates them for the output Chain/Flag.
643 /// If the Flag pointer is NULL, no flag is used.
644 SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo,
645 SDLoc dl,
646 SDValue &Chain, SDValue *Flag,
647 const Value *V = nullptr) const;
648
649 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
650 /// specified value into the registers specified by this object. This uses
651 /// Chain/Flag as the input and updates them for the output Chain/Flag.
652 /// If the Flag pointer is NULL, no flag is used.
653 void
654 getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl, SDValue &Chain,
655 SDValue *Flag, const Value *V,
656 ISD::NodeType PreferredExtendType = ISD::ANY_EXTEND) const;
657
658 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
659 /// operand list. This adds the code marker, matching input operand index
660 /// (if applicable), and includes the number of values added into it.
661 void AddInlineAsmOperands(unsigned Kind,
662 bool HasMatching, unsigned MatchingIdx,
663 SelectionDAG &DAG,
664 std::vector<SDValue> &Ops) const;
665 };
666}
667
668/// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
669/// this value and returns the result as a ValueVT value. This uses
670/// Chain/Flag as the input and updates them for the output Chain/Flag.
671/// If the Flag pointer is NULL, no flag is used.
672SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
673 FunctionLoweringInfo &FuncInfo,
674 SDLoc dl,
675 SDValue &Chain, SDValue *Flag,
676 const Value *V) const {
677 // A Value with type {} or [0 x %t] needs no registers.
678 if (ValueVTs.empty())
679 return SDValue();
680
681 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
682
683 // Assemble the legal parts into the final values.
684 SmallVector<SDValue, 4> Values(ValueVTs.size());
685 SmallVector<SDValue, 8> Parts;
686 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
687 // Copy the legal parts from the registers.
688 EVT ValueVT = ValueVTs[Value];
689 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
690 MVT RegisterVT = RegVTs[Value];
691
692 Parts.resize(NumRegs);
693 for (unsigned i = 0; i != NumRegs; ++i) {
694 SDValue P;
695 if (!Flag) {
696 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
697 } else {
698 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
699 *Flag = P.getValue(2);
700 }
701
702 Chain = P.getValue(1);
703 Parts[i] = P;
704
705 // If the source register was virtual and if we know something about it,
706 // add an assert node.
707 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) ||
708 !RegisterVT.isInteger() || RegisterVT.isVector())
709 continue;
710
711 const FunctionLoweringInfo::LiveOutInfo *LOI =
712 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]);
713 if (!LOI)
714 continue;
715
716 unsigned RegSize = RegisterVT.getSizeInBits();
717 unsigned NumSignBits = LOI->NumSignBits;
718 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes();
719
720 if (NumZeroBits == RegSize) {
721 // The current value is a zero.
722 // Explicitly express that as it would be easier for
723 // optimizations to kick in.
724 Parts[i] = DAG.getConstant(0, RegisterVT);
725 continue;
726 }
727
728 // FIXME: We capture more information than the dag can represent. For
729 // now, just use the tightest assertzext/assertsext possible.
730 bool isSExt = true;
731 EVT FromVT(MVT::Other);
732 if (NumSignBits == RegSize)
733 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
734 else if (NumZeroBits >= RegSize-1)
735 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
736 else if (NumSignBits > RegSize-8)
737 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
738 else if (NumZeroBits >= RegSize-8)
739 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
740 else if (NumSignBits > RegSize-16)
741 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
742 else if (NumZeroBits >= RegSize-16)
743 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
744 else if (NumSignBits > RegSize-32)
745 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
746 else if (NumZeroBits >= RegSize-32)
747 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
748 else
749 continue;
750
751 // Add an assertion node.
752 assert(FromVT != MVT::Other)((FromVT != MVT::Other) ? static_cast<void> (0) : __assert_fail
("FromVT != MVT::Other", "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 752, __PRETTY_FUNCTION__));
753 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
754 RegisterVT, P, DAG.getValueType(FromVT));
755 }
756
757 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
758 NumRegs, RegisterVT, ValueVT, V);
759 Part += NumRegs;
760 Parts.clear();
761 }
762
763 return DAG.getNode(ISD::MERGE_VALUES, dl, DAG.getVTList(ValueVTs), Values);
764}
765
766/// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
767/// specified value into the registers specified by this object. This uses
768/// Chain/Flag as the input and updates them for the output Chain/Flag.
769/// If the Flag pointer is NULL, no flag is used.
770void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl,
771 SDValue &Chain, SDValue *Flag, const Value *V,
772 ISD::NodeType PreferredExtendType) const {
773 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
774 ISD::NodeType ExtendKind = PreferredExtendType;
775
776 // Get the list of the values's legal parts.
777 unsigned NumRegs = Regs.size();
778 SmallVector<SDValue, 8> Parts(NumRegs);
779 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
780 EVT ValueVT = ValueVTs[Value];
781 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
782 MVT RegisterVT = RegVTs[Value];
783
784 if (ExtendKind == ISD::ANY_EXTEND && TLI.isZExtFree(Val, RegisterVT))
785 ExtendKind = ISD::ZERO_EXTEND;
786
787 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
788 &Parts[Part], NumParts, RegisterVT, V, ExtendKind);
789 Part += NumParts;
790 }
791
792 // Copy the parts into the registers.
793 SmallVector<SDValue, 8> Chains(NumRegs);
794 for (unsigned i = 0; i != NumRegs; ++i) {
795 SDValue Part;
796 if (!Flag) {
797 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
798 } else {
799 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
800 *Flag = Part.getValue(1);
801 }
802
803 Chains[i] = Part.getValue(0);
804 }
805
806 if (NumRegs == 1 || Flag)
807 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
808 // flagged to it. That is the CopyToReg nodes and the user are considered
809 // a single scheduling unit. If we create a TokenFactor and return it as
810 // chain, then the TokenFactor is both a predecessor (operand) of the
811 // user as well as a successor (the TF operands are flagged to the user).
812 // c1, f1 = CopyToReg
813 // c2, f2 = CopyToReg
814 // c3 = TokenFactor c1, c2
815 // ...
816 // = op c3, ..., f2
817 Chain = Chains[NumRegs-1];
818 else
819 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
820}
821
822/// AddInlineAsmOperands - Add this value to the specified inlineasm node
823/// operand list. This adds the code marker and includes the number of
824/// values added into it.
825void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
826 unsigned MatchingIdx,
827 SelectionDAG &DAG,
828 std::vector<SDValue> &Ops) const {
829 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
830
831 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size());
832 if (HasMatching)
833 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx);
834 else if (!Regs.empty() &&
835 TargetRegisterInfo::isVirtualRegister(Regs.front())) {
836 // Put the register class of the virtual registers in the flag word. That
837 // way, later passes can recompute register class constraints for inline
838 // assembly as well as normal instructions.
839 // Don't do this for tied operands that can use the regclass information
840 // from the def.
841 const MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
842 const TargetRegisterClass *RC = MRI.getRegClass(Regs.front());
843 Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID());
844 }
845
846 SDValue Res = DAG.getTargetConstant(Flag, MVT::i32);
847 Ops.push_back(Res);
848
849 unsigned SP = TLI.getStackPointerRegisterToSaveRestore();
850 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
851 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
852 MVT RegisterVT = RegVTs[Value];
853 for (unsigned i = 0; i != NumRegs; ++i) {
854 assert(Reg < Regs.size() && "Mismatch in # registers expected")((Reg < Regs.size() && "Mismatch in # registers expected"
) ? static_cast<void> (0) : __assert_fail ("Reg < Regs.size() && \"Mismatch in # registers expected\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 854, __PRETTY_FUNCTION__));
855 unsigned TheReg = Regs[Reg++];
856 Ops.push_back(DAG.getRegister(TheReg, RegisterVT));
857
858 if (TheReg == SP && Code == InlineAsm::Kind_Clobber) {
859 // If we clobbered the stack pointer, MFI should know about it.
860 assert(DAG.getMachineFunction().getFrameInfo()->((DAG.getMachineFunction().getFrameInfo()-> hasInlineAsmWithSPAdjust
()) ? static_cast<void> (0) : __assert_fail ("DAG.getMachineFunction().getFrameInfo()-> hasInlineAsmWithSPAdjust()"
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 861, __PRETTY_FUNCTION__))
861 hasInlineAsmWithSPAdjust())((DAG.getMachineFunction().getFrameInfo()-> hasInlineAsmWithSPAdjust
()) ? static_cast<void> (0) : __assert_fail ("DAG.getMachineFunction().getFrameInfo()-> hasInlineAsmWithSPAdjust()"
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 861, __PRETTY_FUNCTION__));
862 }
863 }
864 }
865}
866
867void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa,
868 const TargetLibraryInfo *li) {
869 AA = &aa;
870 GFI = gfi;
871 LibInfo = li;
872 DL = DAG.getTarget().getDataLayout();
873 Context = DAG.getContext();
874 LPadToCallSiteMap.clear();
875}
876
877/// clear - Clear out the current SelectionDAG and the associated
878/// state and prepare this SelectionDAGBuilder object to be used
879/// for a new block. This doesn't clear out information about
880/// additional blocks that are needed to complete switch lowering
881/// or PHI node updating; that information is cleared out as it is
882/// consumed.
883void SelectionDAGBuilder::clear() {
884 NodeMap.clear();
885 UnusedArgNodeMap.clear();
886 PendingLoads.clear();
887 PendingExports.clear();
888 CurInst = nullptr;
889 HasTailCall = false;
890 SDNodeOrder = LowestSDNodeOrder;
891 StatepointLowering.clear();
892}
893
894/// clearDanglingDebugInfo - Clear the dangling debug information
895/// map. This function is separated from the clear so that debug
896/// information that is dangling in a basic block can be properly
897/// resolved in a different basic block. This allows the
898/// SelectionDAG to resolve dangling debug information attached
899/// to PHI nodes.
900void SelectionDAGBuilder::clearDanglingDebugInfo() {
901 DanglingDebugInfoMap.clear();
902}
903
904/// getRoot - Return the current virtual root of the Selection DAG,
905/// flushing any PendingLoad items. This must be done before emitting
906/// a store or any other node that may need to be ordered after any
907/// prior load instructions.
908///
909SDValue SelectionDAGBuilder::getRoot() {
910 if (PendingLoads.empty())
911 return DAG.getRoot();
912
913 if (PendingLoads.size() == 1) {
914 SDValue Root = PendingLoads[0];
915 DAG.setRoot(Root);
916 PendingLoads.clear();
917 return Root;
918 }
919
920 // Otherwise, we have to make a token factor node.
921 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
922 PendingLoads);
923 PendingLoads.clear();
924 DAG.setRoot(Root);
925 return Root;
926}
927
928/// getControlRoot - Similar to getRoot, but instead of flushing all the
929/// PendingLoad items, flush all the PendingExports items. It is necessary
930/// to do this before emitting a terminator instruction.
931///
932SDValue SelectionDAGBuilder::getControlRoot() {
933 SDValue Root = DAG.getRoot();
934
935 if (PendingExports.empty())
936 return Root;
937
938 // Turn all of the CopyToReg chains into one factored node.
939 if (Root.getOpcode() != ISD::EntryToken) {
940 unsigned i = 0, e = PendingExports.size();
941 for (; i != e; ++i) {
942 assert(PendingExports[i].getNode()->getNumOperands() > 1)((PendingExports[i].getNode()->getNumOperands() > 1) ? static_cast
<void> (0) : __assert_fail ("PendingExports[i].getNode()->getNumOperands() > 1"
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 942, __PRETTY_FUNCTION__));
943 if (PendingExports[i].getNode()->getOperand(0) == Root)
944 break; // Don't add the root if we already indirectly depend on it.
945 }
946
947 if (i == e)
948 PendingExports.push_back(Root);
949 }
950
951 Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
952 PendingExports);
953 PendingExports.clear();
954 DAG.setRoot(Root);
955 return Root;
956}
957
958void SelectionDAGBuilder::visit(const Instruction &I) {
959 // Set up outgoing PHI node register values before emitting the terminator.
960 if (isa<TerminatorInst>(&I))
961 HandlePHINodesInSuccessorBlocks(I.getParent());
962
963 ++SDNodeOrder;
964
965 CurInst = &I;
966
967 visit(I.getOpcode(), I);
968
969 if (!isa<TerminatorInst>(&I) && !HasTailCall)
970 CopyToExportRegsIfNeeded(&I);
971
972 CurInst = nullptr;
973}
974
975void SelectionDAGBuilder::visitPHI(const PHINode &) {
976 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!")::llvm::llvm_unreachable_internal("SelectionDAGBuilder shouldn't visit PHI nodes!"
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 976);
977}
978
979void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
980 // Note: this doesn't use InstVisitor, because it has to work with
981 // ConstantExpr's in addition to instructions.
982 switch (Opcode) {
983 default: llvm_unreachable("Unknown instruction type encountered!")::llvm::llvm_unreachable_internal("Unknown instruction type encountered!"
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 983);
984 // Build the switch statement using the Instruction.def file.
985#define HANDLE_INST(NUM, OPCODE, CLASS) \
986 case Instruction::OPCODE: visit##OPCODE((const CLASS&)I); break;
987#include "llvm/IR/Instruction.def"
988 }
989}
990
991// resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
992// generate the debug data structures now that we've seen its definition.
993void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V,
994 SDValue Val) {
995 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V];
996 if (DDI.getDI()) {
997 const DbgValueInst *DI = DDI.getDI();
998 DebugLoc dl = DDI.getdl();
999 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder();
1000 MDNode *Variable = DI->getVariable();
1001 MDNode *Expr = DI->getExpression();
1002 uint64_t Offset = DI->getOffset();
1003 // A dbg.value for an alloca is always indirect.
1004 bool IsIndirect = isa<AllocaInst>(V) || Offset != 0;
1005 SDDbgValue *SDV;
1006 if (Val.getNode()) {
1007 if (!EmitFuncArgumentDbgValue(V, Variable, Expr, Offset, IsIndirect,
1008 Val)) {
1009 SDV = DAG.getDbgValue(Variable, Expr, Val.getNode(), Val.getResNo(),
1010 IsIndirect, Offset, dl, DbgSDNodeOrder);
1011 DAG.AddDbgValue(SDV, Val.getNode(), false);
1012 }
1013 } else
1014 DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << "Dropping debug info for " <<
*DI << "\n"; } } while (0);
1015 DanglingDebugInfoMap[V] = DanglingDebugInfo();
1016 }
1017}
1018
1019/// getValue - Return an SDValue for the given Value.
1020SDValue SelectionDAGBuilder::getValue(const Value *V) {
1021 // If we already have an SDValue for this value, use it. It's important
1022 // to do this first, so that we don't create a CopyFromReg if we already
1023 // have a regular SDValue.
1024 SDValue &N = NodeMap[V];
1025 if (N.getNode()) return N;
1026
1027 // If there's a virtual register allocated and initialized for this
1028 // value, use it.
1029 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V);
1030 if (It != FuncInfo.ValueMap.end()) {
1031 unsigned InReg = It->second;
1032 RegsForValue RFV(*DAG.getContext(), DAG.getTargetLoweringInfo(), InReg,
1033 V->getType());
1034 SDValue Chain = DAG.getEntryNode();
1035 N = RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
1036 resolveDanglingDebugInfo(V, N);
1037 return N;
1038 }
1039
1040 // Otherwise create a new SDValue and remember it.
1041 SDValue Val = getValueImpl(V);
1042 NodeMap[V] = Val;
1043 resolveDanglingDebugInfo(V, Val);
1044 return Val;
1045}
1046
1047/// getNonRegisterValue - Return an SDValue for the given Value, but
1048/// don't look in FuncInfo.ValueMap for a virtual register.
1049SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) {
1050 // If we already have an SDValue for this value, use it.
1051 SDValue &N = NodeMap[V];
1052 if (N.getNode()) return N;
1053
1054 // Otherwise create a new SDValue and remember it.
1055 SDValue Val = getValueImpl(V);
1056 NodeMap[V] = Val;
1057 resolveDanglingDebugInfo(V, Val);
1058 return Val;
1059}
1060
1061/// getValueImpl - Helper function for getValue and getNonRegisterValue.
1062/// Create an SDValue for the given value.
1063SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
1064 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1065
1066 if (const Constant *C = dyn_cast<Constant>(V)) {
1067 EVT VT = TLI.getValueType(V->getType(), true);
1068
1069 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
1070 return DAG.getConstant(*CI, VT);
1071
1072 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
1073 return DAG.getGlobalAddress(GV, getCurSDLoc(), VT);
1074
1075 if (isa<ConstantPointerNull>(C)) {
1076 unsigned AS = V->getType()->getPointerAddressSpace();
1077 return DAG.getConstant(0, TLI.getPointerTy(AS));
1078 }
1079
1080 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
1081 return DAG.getConstantFP(*CFP, VT);
1082
1083 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
1084 return DAG.getUNDEF(VT);
1085
1086 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
1087 visit(CE->getOpcode(), *CE);
1088 SDValue N1 = NodeMap[V];
1089 assert(N1.getNode() && "visit didn't populate the NodeMap!")((N1.getNode() && "visit didn't populate the NodeMap!"
) ? static_cast<void> (0) : __assert_fail ("N1.getNode() && \"visit didn't populate the NodeMap!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 1089, __PRETTY_FUNCTION__));
1090 return N1;
1091 }
1092
1093 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
1094 SmallVector<SDValue, 4> Constants;
1095 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
1096 OI != OE; ++OI) {
1097 SDNode *Val = getValue(*OI).getNode();
1098 // If the operand is an empty aggregate, there are no values.
1099 if (!Val) continue;
1100 // Add each leaf value from the operand to the Constants list
1101 // to form a flattened list of all the values.
1102 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1103 Constants.push_back(SDValue(Val, i));
1104 }
1105
1106 return DAG.getMergeValues(Constants, getCurSDLoc());
1107 }
1108
1109 if (const ConstantDataSequential *CDS =
1110 dyn_cast<ConstantDataSequential>(C)) {
1111 SmallVector<SDValue, 4> Ops;
1112 for (unsigned i = 0, e = CDS->getNumElements(); i != e; ++i) {
1113 SDNode *Val = getValue(CDS->getElementAsConstant(i)).getNode();
1114 // Add each leaf value from the operand to the Constants list
1115 // to form a flattened list of all the values.
1116 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1117 Ops.push_back(SDValue(Val, i));
1118 }
1119
1120 if (isa<ArrayType>(CDS->getType()))
1121 return DAG.getMergeValues(Ops, getCurSDLoc());
1122 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(),
1123 VT, Ops);
1124 }
1125
1126 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
1127 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&(((isa<ConstantAggregateZero>(C) || isa<UndefValue>
(C)) && "Unknown struct or array constant!") ? static_cast
<void> (0) : __assert_fail ("(isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) && \"Unknown struct or array constant!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 1128, __PRETTY_FUNCTION__))
1128 "Unknown struct or array constant!")(((isa<ConstantAggregateZero>(C) || isa<UndefValue>
(C)) && "Unknown struct or array constant!") ? static_cast
<void> (0) : __assert_fail ("(isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) && \"Unknown struct or array constant!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 1128, __PRETTY_FUNCTION__));
1129
1130 SmallVector<EVT, 4> ValueVTs;
1131 ComputeValueVTs(TLI, C->getType(), ValueVTs);
1132 unsigned NumElts = ValueVTs.size();
1133 if (NumElts == 0)
1134 return SDValue(); // empty struct
1135 SmallVector<SDValue, 4> Constants(NumElts);
1136 for (unsigned i = 0; i != NumElts; ++i) {
1137 EVT EltVT = ValueVTs[i];
1138 if (isa<UndefValue>(C))
1139 Constants[i] = DAG.getUNDEF(EltVT);
1140 else if (EltVT.isFloatingPoint())
1141 Constants[i] = DAG.getConstantFP(0, EltVT);
1142 else
1143 Constants[i] = DAG.getConstant(0, EltVT);
1144 }
1145
1146 return DAG.getMergeValues(Constants, getCurSDLoc());
1147 }
1148
1149 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C))
1150 return DAG.getBlockAddress(BA, VT);
1151
1152 VectorType *VecTy = cast<VectorType>(V->getType());
1153 unsigned NumElements = VecTy->getNumElements();
1154
1155 // Now that we know the number and type of the elements, get that number of
1156 // elements into the Ops array based on what kind of constant it is.
1157 SmallVector<SDValue, 16> Ops;
1158 if (const ConstantVector *CV = dyn_cast<ConstantVector>(C)) {
1159 for (unsigned i = 0; i != NumElements; ++i)
1160 Ops.push_back(getValue(CV->getOperand(i)));
1161 } else {
1162 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!")((isa<ConstantAggregateZero>(C) && "Unknown vector constant!"
) ? static_cast<void> (0) : __assert_fail ("isa<ConstantAggregateZero>(C) && \"Unknown vector constant!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 1162, __PRETTY_FUNCTION__));
1163 EVT EltVT = TLI.getValueType(VecTy->getElementType());
1164
1165 SDValue Op;
1166 if (EltVT.isFloatingPoint())
1167 Op = DAG.getConstantFP(0, EltVT);
1168 else
1169 Op = DAG.getConstant(0, EltVT);
1170 Ops.assign(NumElements, Op);
1171 }
1172
1173 // Create a BUILD_VECTOR node.
1174 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(), VT, Ops);
1175 }
1176
1177 // If this is a static alloca, generate it as the frameindex instead of
1178 // computation.
1179 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1180 DenseMap<const AllocaInst*, int>::iterator SI =
1181 FuncInfo.StaticAllocaMap.find(AI);
1182 if (SI != FuncInfo.StaticAllocaMap.end())
1183 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
1184 }
1185
1186 // If this is an instruction which fast-isel has deferred, select it now.
1187 if (const Instruction *Inst = dyn_cast<Instruction>(V)) {
1188 unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
1189 RegsForValue RFV(*DAG.getContext(), TLI, InReg, Inst->getType());
1190 SDValue Chain = DAG.getEntryNode();
1191 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
1192 }
1193
1194 llvm_unreachable("Can't get register for value!")::llvm::llvm_unreachable_internal("Can't get register for value!"
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 1194);
1195}
1196
1197void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
1198 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1199 SDValue Chain = getControlRoot();
1200 SmallVector<ISD::OutputArg, 8> Outs;
1201 SmallVector<SDValue, 8> OutVals;
1202
1203 if (!FuncInfo.CanLowerReturn) {
1204 unsigned DemoteReg = FuncInfo.DemoteRegister;
1205 const Function *F = I.getParent()->getParent();
1206
1207 // Emit a store of the return value through the virtual register.
1208 // Leave Outs empty so that LowerReturn won't try to load return
1209 // registers the usual way.
1210 SmallVector<EVT, 1> PtrValueVTs;
1211 ComputeValueVTs(TLI, PointerType::getUnqual(F->getReturnType()),
1212 PtrValueVTs);
1213
1214 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]);
1215 SDValue RetOp = getValue(I.getOperand(0));
1216
1217 SmallVector<EVT, 4> ValueVTs;
1218 SmallVector<uint64_t, 4> Offsets;
1219 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets);
1220 unsigned NumValues = ValueVTs.size();
1221
1222 SmallVector<SDValue, 4> Chains(NumValues);
1223 for (unsigned i = 0; i != NumValues; ++i) {
1224 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(),
1225 RetPtr.getValueType(), RetPtr,
1226 DAG.getIntPtrConstant(Offsets[i]));
1227 Chains[i] =
1228 DAG.getStore(Chain, getCurSDLoc(),
1229 SDValue(RetOp.getNode(), RetOp.getResNo() + i),
1230 // FIXME: better loc info would be nice.
1231 Add, MachinePointerInfo(), false, false, 0);
1232 }
1233
1234 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
1235 MVT::Other, Chains);
1236 } else if (I.getNumOperands() != 0) {
1237 SmallVector<EVT, 4> ValueVTs;
1238 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs);
1239 unsigned NumValues = ValueVTs.size();
1240 if (NumValues) {
1241 SDValue RetOp = getValue(I.getOperand(0));
1242
1243 const Function *F = I.getParent()->getParent();
1244
1245 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1246 if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1247 Attribute::SExt))
1248 ExtendKind = ISD::SIGN_EXTEND;
1249 else if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1250 Attribute::ZExt))
1251 ExtendKind = ISD::ZERO_EXTEND;
1252
1253 LLVMContext &Context = F->getContext();
1254 bool RetInReg = F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1255 Attribute::InReg);
1256
1257 for (unsigned j = 0; j != NumValues; ++j) {
1258 EVT VT = ValueVTs[j];
1259
1260 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger())
1261 VT = TLI.getTypeForExtArgOrReturn(Context, VT, ExtendKind);
1262
1263 unsigned NumParts = TLI.getNumRegisters(Context, VT);
1264 MVT PartVT = TLI.getRegisterType(Context, VT);
1265 SmallVector<SDValue, 4> Parts(NumParts);
1266 getCopyToParts(DAG, getCurSDLoc(),
1267 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
1268 &Parts[0], NumParts, PartVT, &I, ExtendKind);
1269
1270 // 'inreg' on function refers to return value
1271 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1272 if (RetInReg)
1273 Flags.setInReg();
1274
1275 // Propagate extension type if any
1276 if (ExtendKind == ISD::SIGN_EXTEND)
1277 Flags.setSExt();
1278 else if (ExtendKind == ISD::ZERO_EXTEND)
1279 Flags.setZExt();
1280
1281 for (unsigned i = 0; i < NumParts; ++i) {
1282 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(),
1283 VT, /*isfixed=*/true, 0, 0));
1284 OutVals.push_back(Parts[i]);
1285 }
1286 }
1287 }
1288 }
1289
1290 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1291 CallingConv::ID CallConv =
1292 DAG.getMachineFunction().getFunction()->getCallingConv();
1293 Chain = DAG.getTargetLoweringInfo().LowerReturn(
1294 Chain, CallConv, isVarArg, Outs, OutVals, getCurSDLoc(), DAG);
1295
1296 // Verify that the target's LowerReturn behaved as expected.
1297 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&((Chain.getNode() && Chain.getValueType() == MVT::Other
&& "LowerReturn didn't return a valid chain!") ? static_cast
<void> (0) : __assert_fail ("Chain.getNode() && Chain.getValueType() == MVT::Other && \"LowerReturn didn't return a valid chain!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 1298, __PRETTY_FUNCTION__))
1298 "LowerReturn didn't return a valid chain!")((Chain.getNode() && Chain.getValueType() == MVT::Other
&& "LowerReturn didn't return a valid chain!") ? static_cast
<void> (0) : __assert_fail ("Chain.getNode() && Chain.getValueType() == MVT::Other && \"LowerReturn didn't return a valid chain!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 1298, __PRETTY_FUNCTION__));
1299
1300 // Update the DAG with the new chain value resulting from return lowering.
1301 DAG.setRoot(Chain);
1302}
1303
1304/// CopyToExportRegsIfNeeded - If the given value has virtual registers
1305/// created for it, emit nodes to copy the value into the virtual
1306/// registers.
1307void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) {
1308 // Skip empty types
1309 if (V->getType()->isEmptyTy())
1310 return;
1311
1312 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1313 if (VMI != FuncInfo.ValueMap.end()) {
1314 assert(!V->use_empty() && "Unused value assigned virtual registers!")((!V->use_empty() && "Unused value assigned virtual registers!"
) ? static_cast<void> (0) : __assert_fail ("!V->use_empty() && \"Unused value assigned virtual registers!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 1314, __PRETTY_FUNCTION__));
1315 CopyValueToVirtualRegister(V, VMI->second);
1316 }
1317}
1318
1319/// ExportFromCurrentBlock - If this condition isn't known to be exported from
1320/// the current basic block, add it to ValueMap now so that we'll get a
1321/// CopyTo/FromReg.
1322void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) {
1323 // No need to export constants.
1324 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1325
1326 // Already exported?
1327 if (FuncInfo.isExportedInst(V)) return;
1328
1329 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1330 CopyValueToVirtualRegister(V, Reg);
1331}
1332
1333bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V,
1334 const BasicBlock *FromBB) {
1335 // The operands of the setcc have to be in this block. We don't know
1336 // how to export them from some other block.
1337 if (const Instruction *VI = dyn_cast<Instruction>(V)) {
1338 // Can export from current BB.
1339 if (VI->getParent() == FromBB)
1340 return true;
1341
1342 // Is already exported, noop.
1343 return FuncInfo.isExportedInst(V);
1344 }
1345
1346 // If this is an argument, we can export it if the BB is the entry block or
1347 // if it is already exported.
1348 if (isa<Argument>(V)) {
1349 if (FromBB == &FromBB->getParent()->getEntryBlock())
1350 return true;
1351
1352 // Otherwise, can only export this if it is already exported.
1353 return FuncInfo.isExportedInst(V);
1354 }
1355
1356 // Otherwise, constants can always be exported.
1357 return true;
1358}
1359
1360/// Return branch probability calculated by BranchProbabilityInfo for IR blocks.
1361uint32_t SelectionDAGBuilder::getEdgeWeight(const MachineBasicBlock *Src,
1362 const MachineBasicBlock *Dst) const {
1363 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1364 if (!BPI)
1365 return 0;
1366 const BasicBlock *SrcBB = Src->getBasicBlock();
1367 const BasicBlock *DstBB = Dst->getBasicBlock();
1368 return BPI->getEdgeWeight(SrcBB, DstBB);
1369}
1370
1371void SelectionDAGBuilder::
1372addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst,
1373 uint32_t Weight /* = 0 */) {
1374 if (!Weight)
1375 Weight = getEdgeWeight(Src, Dst);
1376 Src->addSuccessor(Dst, Weight);
1377}
1378
1379
1380static bool InBlock(const Value *V, const BasicBlock *BB) {
1381 if (const Instruction *I = dyn_cast<Instruction>(V))
1382 return I->getParent() == BB;
1383 return true;
1384}
1385
1386/// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1387/// This function emits a branch and is used at the leaves of an OR or an
1388/// AND operator tree.
1389///
1390void
1391SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond,
1392 MachineBasicBlock *TBB,
1393 MachineBasicBlock *FBB,
1394 MachineBasicBlock *CurBB,
1395 MachineBasicBlock *SwitchBB,
1396 uint32_t TWeight,
1397 uint32_t FWeight) {
1398 const BasicBlock *BB = CurBB->getBasicBlock();
1399
1400 // If the leaf of the tree is a comparison, merge the condition into
1401 // the caseblock.
1402 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1403 // The operands of the cmp have to be in this block. We don't know
1404 // how to export them from some other block. If this is the first block
1405 // of the sequence, no exporting is needed.
1406 if (CurBB == SwitchBB ||
1407 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1408 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1409 ISD::CondCode Condition;
1410 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1411 Condition = getICmpCondCode(IC->getPredicate());
1412 } else if (const FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1413 Condition = getFCmpCondCode(FC->getPredicate());
1414 if (TM.Options.NoNaNsFPMath)
1415 Condition = getFCmpCodeWithoutNaN(Condition);
1416 } else {
1417 (void)Condition; // silence warning.
1418 llvm_unreachable("Unknown compare instruction")::llvm::llvm_unreachable_internal("Unknown compare instruction"
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 1418);
1419 }
1420
1421 CaseBlock CB(Condition, BOp->getOperand(0), BOp->getOperand(1), nullptr,
1422 TBB, FBB, CurBB, TWeight, FWeight);
1423 SwitchCases.push_back(CB);
1424 return;
1425 }
1426 }
1427
1428 // Create a CaseBlock record representing this branch.
1429 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()),
1430 nullptr, TBB, FBB, CurBB, TWeight, FWeight);
1431 SwitchCases.push_back(CB);
1432}
1433
1434/// Scale down both weights to fit into uint32_t.
1435static void ScaleWeights(uint64_t &NewTrue, uint64_t &NewFalse) {
1436 uint64_t NewMax = (NewTrue > NewFalse) ? NewTrue : NewFalse;
1437 uint32_t Scale = (NewMax / UINT32_MAX(4294967295U)) + 1;
1438 NewTrue = NewTrue / Scale;
1439 NewFalse = NewFalse / Scale;
1440}
1441
1442/// FindMergedConditions - If Cond is an expression like
1443void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
1444 MachineBasicBlock *TBB,
1445 MachineBasicBlock *FBB,
1446 MachineBasicBlock *CurBB,
1447 MachineBasicBlock *SwitchBB,
1448 unsigned Opc, uint32_t TWeight,
1449 uint32_t FWeight) {
1450 // If this node is not part of the or/and tree, emit it as a branch.
1451 const Instruction *BOp = dyn_cast<Instruction>(Cond);
1452 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1453 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1454 BOp->getParent() != CurBB->getBasicBlock() ||
1455 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1456 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1457 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB,
1458 TWeight, FWeight);
1459 return;
1460 }
1461
1462 // Create TmpBB after CurBB.
1463 MachineFunction::iterator BBI = CurBB;
1464 MachineFunction &MF = DAG.getMachineFunction();
1465 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1466 CurBB->getParent()->insert(++BBI, TmpBB);
1467
1468 if (Opc == Instruction::Or) {
1469 // Codegen X | Y as:
1470 // BB1:
1471 // jmp_if_X TBB
1472 // jmp TmpBB
1473 // TmpBB:
1474 // jmp_if_Y TBB
1475 // jmp FBB
1476 //
1477
1478 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1479 // The requirement is that
1480 // TrueProb for BB1 + (FalseProb for BB1 * TrueProb for TmpBB)
1481 // = TrueProb for orignal BB.
1482 // Assuming the orignal weights are A and B, one choice is to set BB1's
1483 // weights to A and A+2B, and set TmpBB's weights to A and 2B. This choice
1484 // assumes that
1485 // TrueProb for BB1 == FalseProb for BB1 * TrueProb for TmpBB.
1486 // Another choice is to assume TrueProb for BB1 equals to TrueProb for
1487 // TmpBB, but the math is more complicated.
1488
1489 uint64_t NewTrueWeight = TWeight;
1490 uint64_t NewFalseWeight = (uint64_t)TWeight + 2 * (uint64_t)FWeight;
1491 ScaleWeights(NewTrueWeight, NewFalseWeight);
1492 // Emit the LHS condition.
1493 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc,
1494 NewTrueWeight, NewFalseWeight);
1495
1496 NewTrueWeight = TWeight;
1497 NewFalseWeight = 2 * (uint64_t)FWeight;
1498 ScaleWeights(NewTrueWeight, NewFalseWeight);
1499 // Emit the RHS condition into TmpBB.
1500 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1501 NewTrueWeight, NewFalseWeight);
1502 } else {
1503 assert(Opc == Instruction::And && "Unknown merge op!")((Opc == Instruction::And && "Unknown merge op!") ? static_cast
<void> (0) : __assert_fail ("Opc == Instruction::And && \"Unknown merge op!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 1503, __PRETTY_FUNCTION__));
1504 // Codegen X & Y as:
1505 // BB1:
1506 // jmp_if_X TmpBB
1507 // jmp FBB
1508 // TmpBB:
1509 // jmp_if_Y TBB
1510 // jmp FBB
1511 //
1512 // This requires creation of TmpBB after CurBB.
1513
1514 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1515 // The requirement is that
1516 // FalseProb for BB1 + (TrueProb for BB1 * FalseProb for TmpBB)
1517 // = FalseProb for orignal BB.
1518 // Assuming the orignal weights are A and B, one choice is to set BB1's
1519 // weights to 2A+B and B, and set TmpBB's weights to 2A and B. This choice
1520 // assumes that
1521 // FalseProb for BB1 == TrueProb for BB1 * FalseProb for TmpBB.
1522
1523 uint64_t NewTrueWeight = 2 * (uint64_t)TWeight + (uint64_t)FWeight;
1524 uint64_t NewFalseWeight = FWeight;
1525 ScaleWeights(NewTrueWeight, NewFalseWeight);
1526 // Emit the LHS condition.
1527 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc,
1528 NewTrueWeight, NewFalseWeight);
1529
1530 NewTrueWeight = 2 * (uint64_t)TWeight;
1531 NewFalseWeight = FWeight;
1532 ScaleWeights(NewTrueWeight, NewFalseWeight);
1533 // Emit the RHS condition into TmpBB.
1534 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1535 NewTrueWeight, NewFalseWeight);
1536 }
1537}
1538
1539/// If the set of cases should be emitted as a series of branches, return true.
1540/// If we should emit this as a bunch of and/or'd together conditions, return
1541/// false.
1542bool
1543SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases) {
1544 if (Cases.size() != 2) return true;
1545
1546 // If this is two comparisons of the same values or'd or and'd together, they
1547 // will get folded into a single comparison, so don't emit two blocks.
1548 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1549 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1550 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1551 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1552 return false;
1553 }
1554
1555 // Handle: (X != null) | (Y != null) --> (X|Y) != 0
1556 // Handle: (X == null) & (Y == null) --> (X|Y) == 0
1557 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
1558 Cases[0].CC == Cases[1].CC &&
1559 isa<Constant>(Cases[0].CmpRHS) &&
1560 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
1561 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
1562 return false;
1563 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
1564 return false;
1565 }
1566
1567 return true;
1568}
1569
1570void SelectionDAGBuilder::visitBr(const BranchInst &I) {
1571 MachineBasicBlock *BrMBB = FuncInfo.MBB;
1572
1573 // Update machine-CFG edges.
1574 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1575
1576 // Figure out which block is immediately after the current one.
1577 MachineBasicBlock *NextBlock = nullptr;
1578 MachineFunction::iterator BBI = BrMBB;
1579 if (++BBI != FuncInfo.MF->end())
1580 NextBlock = BBI;
1581
1582 if (I.isUnconditional()) {
1583 // Update machine-CFG edges.
1584 BrMBB->addSuccessor(Succ0MBB);
1585
1586 // If this is not a fall-through branch or optimizations are switched off,
1587 // emit the branch.
1588 if (Succ0MBB != NextBlock || TM.getOptLevel() == CodeGenOpt::None)
1589 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
1590 MVT::Other, getControlRoot(),
1591 DAG.getBasicBlock(Succ0MBB)));
1592
1593 return;
1594 }
1595
1596 // If this condition is one of the special cases we handle, do special stuff
1597 // now.
1598 const Value *CondVal = I.getCondition();
1599 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1600
1601 // If this is a series of conditions that are or'd or and'd together, emit
1602 // this as a sequence of branches instead of setcc's with and/or operations.
1603 // As long as jumps are not expensive, this should improve performance.
1604 // For example, instead of something like:
1605 // cmp A, B
1606 // C = seteq
1607 // cmp D, E
1608 // F = setle
1609 // or C, F
1610 // jnz foo
1611 // Emit:
1612 // cmp A, B
1613 // je foo
1614 // cmp D, E
1615 // jle foo
1616 //
1617 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1618 if (!DAG.getTargetLoweringInfo().isJumpExpensive() &&
1619 BOp->hasOneUse() && (BOp->getOpcode() == Instruction::And ||
1620 BOp->getOpcode() == Instruction::Or)) {
1621 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB,
1622 BOp->getOpcode(), getEdgeWeight(BrMBB, Succ0MBB),
1623 getEdgeWeight(BrMBB, Succ1MBB));
1624 // If the compares in later blocks need to use values not currently
1625 // exported from this block, export them now. This block should always
1626 // be the first entry.
1627 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!")((SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!"
) ? static_cast<void> (0) : __assert_fail ("SwitchCases[0].ThisBB == BrMBB && \"Unexpected lowering!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 1627, __PRETTY_FUNCTION__));
1628
1629 // Allow some cases to be rejected.
1630 if (ShouldEmitAsBranches(SwitchCases)) {
1631 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1632 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1633 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1634 }
1635
1636 // Emit the branch for this block.
1637 visitSwitchCase(SwitchCases[0], BrMBB);
1638 SwitchCases.erase(SwitchCases.begin());
1639 return;
1640 }
1641
1642 // Okay, we decided not to do this, remove any inserted MBB's and clear
1643 // SwitchCases.
1644 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1645 FuncInfo.MF->erase(SwitchCases[i].ThisBB);
1646
1647 SwitchCases.clear();
1648 }
1649 }
1650
1651 // Create a CaseBlock record representing this branch.
1652 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
1653 nullptr, Succ0MBB, Succ1MBB, BrMBB);
1654
1655 // Use visitSwitchCase to actually insert the fast branch sequence for this
1656 // cond branch.
1657 visitSwitchCase(CB, BrMBB);
1658}
1659
1660/// visitSwitchCase - Emits the necessary code to represent a single node in
1661/// the binary search tree resulting from lowering a switch instruction.
1662void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB,
1663 MachineBasicBlock *SwitchBB) {
1664 SDValue Cond;
1665 SDValue CondLHS = getValue(CB.CmpLHS);
1666 SDLoc dl = getCurSDLoc();
1667
1668 // Build the setcc now.
1669 if (!CB.CmpMHS) {
1670 // Fold "(X == true)" to X and "(X == false)" to !X to
1671 // handle common cases produced by branch lowering.
1672 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
1673 CB.CC == ISD::SETEQ)
1674 Cond = CondLHS;
1675 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
1676 CB.CC == ISD::SETEQ) {
1677 SDValue True = DAG.getConstant(1, CondLHS.getValueType());
1678 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1679 } else
1680 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1681 } else {
1682 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now")((CB.CC == ISD::SETLE && "Can handle only LE ranges now"
) ? static_cast<void> (0) : __assert_fail ("CB.CC == ISD::SETLE && \"Can handle only LE ranges now\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 1682, __PRETTY_FUNCTION__));
1683
1684 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1685 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1686
1687 SDValue CmpOp = getValue(CB.CmpMHS);
1688 EVT VT = CmpOp.getValueType();
1689
1690 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1691 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT),
1692 ISD::SETLE);
1693 } else {
1694 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1695 VT, CmpOp, DAG.getConstant(Low, VT));
1696 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1697 DAG.getConstant(High-Low, VT), ISD::SETULE);
1698 }
1699 }
1700
1701 // Update successor info
1702 addSuccessorWithWeight(SwitchBB, CB.TrueBB, CB.TrueWeight);
1703 // TrueBB and FalseBB are always different unless the incoming IR is
1704 // degenerate. This only happens when running llc on weird IR.
1705 if (CB.TrueBB != CB.FalseBB)
1706 addSuccessorWithWeight(SwitchBB, CB.FalseBB, CB.FalseWeight);
1707
1708 // Set NextBlock to be the MBB immediately after the current one, if any.
1709 // This is used to avoid emitting unnecessary branches to the next block.
1710 MachineBasicBlock *NextBlock = nullptr;
1711 MachineFunction::iterator BBI = SwitchBB;
1712 if (++BBI != FuncInfo.MF->end())
1713 NextBlock = BBI;
1714
1715 // If the lhs block is the next block, invert the condition so that we can
1716 // fall through to the lhs instead of the rhs block.
1717 if (CB.TrueBB == NextBlock) {
1718 std::swap(CB.TrueBB, CB.FalseBB);
1719 SDValue True = DAG.getConstant(1, Cond.getValueType());
1720 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1721 }
1722
1723 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1724 MVT::Other, getControlRoot(), Cond,
1725 DAG.getBasicBlock(CB.TrueBB));
1726
1727 // Insert the false branch. Do this even if it's a fall through branch,
1728 // this makes it easier to do DAG optimizations which require inverting
1729 // the branch condition.
1730 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1731 DAG.getBasicBlock(CB.FalseBB));
1732
1733 DAG.setRoot(BrCond);
1734}
1735
1736/// visitJumpTable - Emit JumpTable node in the current MBB
1737void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
1738 // Emit the code for the jump table
1739 assert(JT.Reg != -1U && "Should lower JT Header first!")((JT.Reg != -1U && "Should lower JT Header first!") ?
static_cast<void> (0) : __assert_fail ("JT.Reg != -1U && \"Should lower JT Header first!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 1739, __PRETTY_FUNCTION__));
1740 EVT PTy = DAG.getTargetLoweringInfo().getPointerTy();
1741 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(),
1742 JT.Reg, PTy);
1743 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1744 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurSDLoc(),
1745 MVT::Other, Index.getValue(1),
1746 Table, Index);
1747 DAG.setRoot(BrJumpTable);
1748}
1749
1750/// visitJumpTableHeader - This function emits necessary code to produce index
1751/// in the JumpTable from switch case.
1752void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
1753 JumpTableHeader &JTH,
1754 MachineBasicBlock *SwitchBB) {
1755 // Subtract the lowest switch case value from the value being switched on and
1756 // conditional branch to default mbb if the result is greater than the
1757 // difference between smallest and largest cases.
1758 SDValue SwitchOp = getValue(JTH.SValue);
1759 EVT VT = SwitchOp.getValueType();
1760 SDValue Sub = DAG.getNode(ISD::SUB, getCurSDLoc(), VT, SwitchOp,
1761 DAG.getConstant(JTH.First, VT));
1762
1763 // The SDNode we just created, which holds the value being switched on minus
1764 // the smallest case value, needs to be copied to a virtual register so it
1765 // can be used as an index into the jump table in a subsequent basic block.
1766 // This value may be smaller or larger than the target's pointer type, and
1767 // therefore require extension or truncating.
1768 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1769 SwitchOp = DAG.getZExtOrTrunc(Sub, getCurSDLoc(), TLI.getPointerTy());
1770
1771 unsigned JumpTableReg = FuncInfo.CreateReg(TLI.getPointerTy());
1772 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurSDLoc(),
1773 JumpTableReg, SwitchOp);
1774 JT.Reg = JumpTableReg;
1775
1776 // Emit the range check for the jump table, and branch to the default block
1777 // for the switch statement if the value being switched on exceeds the largest
1778 // case in the switch.
1779 SDValue CMP =
1780 DAG.getSetCC(getCurSDLoc(), TLI.getSetCCResultType(*DAG.getContext(),
1781 Sub.getValueType()),
1782 Sub, DAG.getConstant(JTH.Last - JTH.First, VT), ISD::SETUGT);
1783
1784 // Set NextBlock to be the MBB immediately after the current one, if any.
1785 // This is used to avoid emitting unnecessary branches to the next block.
1786 MachineBasicBlock *NextBlock = nullptr;
1787 MachineFunction::iterator BBI = SwitchBB;
1788
1789 if (++BBI != FuncInfo.MF->end())
1790 NextBlock = BBI;
1791
1792 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1793 MVT::Other, CopyTo, CMP,
1794 DAG.getBasicBlock(JT.Default));
1795
1796 if (JT.MBB != NextBlock)
1797 BrCond = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, BrCond,
1798 DAG.getBasicBlock(JT.MBB));
1799
1800 DAG.setRoot(BrCond);
1801}
1802
1803/// Codegen a new tail for a stack protector check ParentMBB which has had its
1804/// tail spliced into a stack protector check success bb.
1805///
1806/// For a high level explanation of how this fits into the stack protector
1807/// generation see the comment on the declaration of class
1808/// StackProtectorDescriptor.
1809void SelectionDAGBuilder::visitSPDescriptorParent(StackProtectorDescriptor &SPD,
1810 MachineBasicBlock *ParentBB) {
1811
1812 // First create the loads to the guard/stack slot for the comparison.
1813 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1814 EVT PtrTy = TLI.getPointerTy();
1815
1816 MachineFrameInfo *MFI = ParentBB->getParent()->getFrameInfo();
1817 int FI = MFI->getStackProtectorIndex();
1818
1819 const Value *IRGuard = SPD.getGuard();
1820 SDValue GuardPtr = getValue(IRGuard);
1821 SDValue StackSlotPtr = DAG.getFrameIndex(FI, PtrTy);
1822
1823 unsigned Align =
1824 TLI.getDataLayout()->getPrefTypeAlignment(IRGuard->getType());
1825
1826 SDValue Guard;
1827
1828 // If GuardReg is set and useLoadStackGuardNode returns true, retrieve the
1829 // guard value from the virtual register holding the value. Otherwise, emit a
1830 // volatile load to retrieve the stack guard value.
1831 unsigned GuardReg = SPD.getGuardReg();
1832
1833 if (GuardReg && TLI.useLoadStackGuardNode())
1834 Guard = DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(), GuardReg,
1835 PtrTy);
1836 else
1837 Guard = DAG.getLoad(PtrTy, getCurSDLoc(), DAG.getEntryNode(),
1838 GuardPtr, MachinePointerInfo(IRGuard, 0),
1839 true, false, false, Align);
1840
1841 SDValue StackSlot = DAG.getLoad(PtrTy, getCurSDLoc(), DAG.getEntryNode(),
1842 StackSlotPtr,
1843 MachinePointerInfo::getFixedStack(FI),
1844 true, false, false, Align);
1845
1846 // Perform the comparison via a subtract/getsetcc.
1847 EVT VT = Guard.getValueType();
1848 SDValue Sub = DAG.getNode(ISD::SUB, getCurSDLoc(), VT, Guard, StackSlot);
1849
1850 SDValue Cmp =
1851 DAG.getSetCC(getCurSDLoc(), TLI.getSetCCResultType(*DAG.getContext(),
1852 Sub.getValueType()),
1853 Sub, DAG.getConstant(0, VT), ISD::SETNE);
1854
1855 // If the sub is not 0, then we know the guard/stackslot do not equal, so
1856 // branch to failure MBB.
1857 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1858 MVT::Other, StackSlot.getOperand(0),
1859 Cmp, DAG.getBasicBlock(SPD.getFailureMBB()));
1860 // Otherwise branch to success MBB.
1861 SDValue Br = DAG.getNode(ISD::BR, getCurSDLoc(),
1862 MVT::Other, BrCond,
1863 DAG.getBasicBlock(SPD.getSuccessMBB()));
1864
1865 DAG.setRoot(Br);
1866}
1867
1868/// Codegen the failure basic block for a stack protector check.
1869///
1870/// A failure stack protector machine basic block consists simply of a call to
1871/// __stack_chk_fail().
1872///
1873/// For a high level explanation of how this fits into the stack protector
1874/// generation see the comment on the declaration of class
1875/// StackProtectorDescriptor.
1876void
1877SelectionDAGBuilder::visitSPDescriptorFailure(StackProtectorDescriptor &SPD) {
1878 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1879 SDValue Chain =
1880 TLI.makeLibCall(DAG, RTLIB::STACKPROTECTOR_CHECK_FAIL, MVT::isVoid,
1881 nullptr, 0, false, getCurSDLoc(), false, false).second;
1882 DAG.setRoot(Chain);
1883}
1884
1885/// visitBitTestHeader - This function emits necessary code to produce value
1886/// suitable for "bit tests"
1887void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
1888 MachineBasicBlock *SwitchBB) {
1889 // Subtract the minimum value
1890 SDValue SwitchOp = getValue(B.SValue);
1891 EVT VT = SwitchOp.getValueType();
1892 SDValue Sub = DAG.getNode(ISD::SUB, getCurSDLoc(), VT, SwitchOp,
1893 DAG.getConstant(B.First, VT));
1894
1895 // Check range
1896 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1897 SDValue RangeCmp =
1898 DAG.getSetCC(getCurSDLoc(), TLI.getSetCCResultType(*DAG.getContext(),
1899 Sub.getValueType()),
1900 Sub, DAG.getConstant(B.Range, VT), ISD::SETUGT);
1901
1902 // Determine the type of the test operands.
1903 bool UsePtrType = false;
1904 if (!TLI.isTypeLegal(VT))
1905 UsePtrType = true;
1906 else {
1907 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i)
1908 if (!isUIntN(VT.getSizeInBits(), B.Cases[i].Mask)) {
1909 // Switch table case range are encoded into series of masks.
1910 // Just use pointer type, it's guaranteed to fit.
1911 UsePtrType = true;
1912 break;
1913 }
1914 }
1915 if (UsePtrType) {
1916 VT = TLI.getPointerTy();
1917 Sub = DAG.getZExtOrTrunc(Sub, getCurSDLoc(), VT);
1918 }
1919
1920 B.RegVT = VT.getSimpleVT();
1921 B.Reg = FuncInfo.CreateReg(B.RegVT);
1922 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurSDLoc(),
1923 B.Reg, Sub);
1924
1925 // Set NextBlock to be the MBB immediately after the current one, if any.
1926 // This is used to avoid emitting unnecessary branches to the next block.
1927 MachineBasicBlock *NextBlock = nullptr;
1928 MachineFunction::iterator BBI = SwitchBB;
1929 if (++BBI != FuncInfo.MF->end())
1930 NextBlock = BBI;
1931
1932 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1933
1934 addSuccessorWithWeight(SwitchBB, B.Default);
1935 addSuccessorWithWeight(SwitchBB, MBB);
1936
1937 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1938 MVT::Other, CopyTo, RangeCmp,
1939 DAG.getBasicBlock(B.Default));
1940
1941 if (MBB != NextBlock)
1942 BrRange = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, CopyTo,
1943 DAG.getBasicBlock(MBB));
1944
1945 DAG.setRoot(BrRange);
1946}
1947
1948/// visitBitTestCase - this function produces one "bit test"
1949void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB,
1950 MachineBasicBlock* NextMBB,
1951 uint32_t BranchWeightToNext,
1952 unsigned Reg,
1953 BitTestCase &B,
1954 MachineBasicBlock *SwitchBB) {
1955 MVT VT = BB.RegVT;
1956 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(),
1957 Reg, VT);
1958 SDValue Cmp;
1959 unsigned PopCount = countPopulation(B.Mask);
1960 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1961 if (PopCount == 1) {
1962 // Testing for a single bit; just compare the shift count with what it
1963 // would need to be to shift a 1 bit in that position.
1964 Cmp = DAG.getSetCC(
1965 getCurSDLoc(), TLI.getSetCCResultType(*DAG.getContext(), VT), ShiftOp,
1966 DAG.getConstant(countTrailingZeros(B.Mask), VT), ISD::SETEQ);
1967 } else if (PopCount == BB.Range) {
1968 // There is only one zero bit in the range, test for it directly.
1969 Cmp = DAG.getSetCC(
1970 getCurSDLoc(), TLI.getSetCCResultType(*DAG.getContext(), VT), ShiftOp,
1971 DAG.getConstant(countTrailingOnes(B.Mask), VT), ISD::SETNE);
1972 } else {
1973 // Make desired shift
1974 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurSDLoc(), VT,
1975 DAG.getConstant(1, VT), ShiftOp);
1976
1977 // Emit bit tests and jumps
1978 SDValue AndOp = DAG.getNode(ISD::AND, getCurSDLoc(),
1979 VT, SwitchVal, DAG.getConstant(B.Mask, VT));
1980 Cmp = DAG.getSetCC(getCurSDLoc(),
1981 TLI.getSetCCResultType(*DAG.getContext(), VT), AndOp,
1982 DAG.getConstant(0, VT), ISD::SETNE);
1983 }
1984
1985 // The branch weight from SwitchBB to B.TargetBB is B.ExtraWeight.
1986 addSuccessorWithWeight(SwitchBB, B.TargetBB, B.ExtraWeight);
1987 // The branch weight from SwitchBB to NextMBB is BranchWeightToNext.
1988 addSuccessorWithWeight(SwitchBB, NextMBB, BranchWeightToNext);
1989
1990 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1991 MVT::Other, getControlRoot(),
1992 Cmp, DAG.getBasicBlock(B.TargetBB));
1993
1994 // Set NextBlock to be the MBB immediately after the current one, if any.
1995 // This is used to avoid emitting unnecessary branches to the next block.
1996 MachineBasicBlock *NextBlock = nullptr;
1997 MachineFunction::iterator BBI = SwitchBB;
1998 if (++BBI != FuncInfo.MF->end())
1999 NextBlock = BBI;
2000
2001 if (NextMBB != NextBlock)
2002 BrAnd = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, BrAnd,
2003 DAG.getBasicBlock(NextMBB));
2004
2005 DAG.setRoot(BrAnd);
2006}
2007
2008void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
2009 MachineBasicBlock *InvokeMBB = FuncInfo.MBB;
2010
2011 // Retrieve successors.
2012 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
2013 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
2014
2015 const Value *Callee(I.getCalledValue());
2016 const Function *Fn = dyn_cast<Function>(Callee);
2017 if (isa<InlineAsm>(Callee))
2018 visitInlineAsm(&I);
2019 else if (Fn && Fn->isIntrinsic()) {
2020 switch (Fn->getIntrinsicID()) {
2021 default:
2022 llvm_unreachable("Cannot invoke this intrinsic")::llvm::llvm_unreachable_internal("Cannot invoke this intrinsic"
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 2022);
2023 case Intrinsic::donothing:
2024 // Ignore invokes to @llvm.donothing: jump directly to the next BB.
2025 break;
2026 case Intrinsic::experimental_patchpoint_void:
2027 case Intrinsic::experimental_patchpoint_i64:
2028 visitPatchpoint(&I, LandingPad);
2029 break;
2030 }
2031 } else
2032 LowerCallTo(&I, getValue(Callee), false, LandingPad);
2033
2034 // If the value of the invoke is used outside of its defining block, make it
2035 // available as a virtual register.
2036 CopyToExportRegsIfNeeded(&I);
2037
2038 // Update successor info
2039 addSuccessorWithWeight(InvokeMBB, Return);
2040 addSuccessorWithWeight(InvokeMBB, LandingPad);
2041
2042 // Drop into normal successor.
2043 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
2044 MVT::Other, getControlRoot(),
2045 DAG.getBasicBlock(Return)));
2046}
2047
2048void SelectionDAGBuilder::visitResume(const ResumeInst &RI) {
2049 llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!")::llvm::llvm_unreachable_internal("SelectionDAGBuilder shouldn't visit resume instructions!"
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 2049);
2050}
2051
2052void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) {
2053 assert(FuncInfo.MBB->isLandingPad() &&((FuncInfo.MBB->isLandingPad() && "Call to landingpad not in landing pad!"
) ? static_cast<void> (0) : __assert_fail ("FuncInfo.MBB->isLandingPad() && \"Call to landingpad not in landing pad!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 2054, __PRETTY_FUNCTION__))
2054 "Call to landingpad not in landing pad!")((FuncInfo.MBB->isLandingPad() && "Call to landingpad not in landing pad!"
) ? static_cast<void> (0) : __assert_fail ("FuncInfo.MBB->isLandingPad() && \"Call to landingpad not in landing pad!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 2054, __PRETTY_FUNCTION__));
2055
2056 MachineBasicBlock *MBB = FuncInfo.MBB;
2057 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
2058 AddLandingPadInfo(LP, MMI, MBB);
2059
2060 // If there aren't registers to copy the values into (e.g., during SjLj
2061 // exceptions), then don't bother to create these DAG nodes.
2062 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2063 if (TLI.getExceptionPointerRegister() == 0 &&
2064 TLI.getExceptionSelectorRegister() == 0)
2065 return;
2066
2067 SmallVector<EVT, 2> ValueVTs;
2068 ComputeValueVTs(TLI, LP.getType(), ValueVTs);
2069 assert(ValueVTs.size() == 2 && "Only two-valued landingpads are supported")((ValueVTs.size() == 2 && "Only two-valued landingpads are supported"
) ? static_cast<void> (0) : __assert_fail ("ValueVTs.size() == 2 && \"Only two-valued landingpads are supported\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 2069, __PRETTY_FUNCTION__));
2070
2071 // Get the two live-in registers as SDValues. The physregs have already been
2072 // copied into virtual registers.
2073 SDValue Ops[2];
2074 if (FuncInfo.ExceptionPointerVirtReg) {
2075 Ops[0] = DAG.getZExtOrTrunc(
2076 DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(),
2077 FuncInfo.ExceptionPointerVirtReg, TLI.getPointerTy()),
2078 getCurSDLoc(), ValueVTs[0]);
2079 } else {
2080 Ops[0] = DAG.getConstant(0, TLI.getPointerTy());
2081 }
2082 Ops[1] = DAG.getZExtOrTrunc(
2083 DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(),
2084 FuncInfo.ExceptionSelectorVirtReg, TLI.getPointerTy()),
2085 getCurSDLoc(), ValueVTs[1]);
2086
2087 // Merge into one.
2088 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2089 DAG.getVTList(ValueVTs), Ops);
2090 setValue(&LP, Res);
2091}
2092
2093unsigned
2094SelectionDAGBuilder::visitLandingPadClauseBB(GlobalValue *ClauseGV,
2095 MachineBasicBlock *LPadBB) {
2096 SDValue Chain = getControlRoot();
2097
2098 // Get the typeid that we will dispatch on later.
2099 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2100 const TargetRegisterClass *RC = TLI.getRegClassFor(TLI.getPointerTy());
2101 unsigned VReg = FuncInfo.MF->getRegInfo().createVirtualRegister(RC);
2102 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(ClauseGV);
2103 SDValue Sel = DAG.getConstant(TypeID, TLI.getPointerTy());
2104 Chain = DAG.getCopyToReg(Chain, getCurSDLoc(), VReg, Sel);
2105
2106 // Branch to the main landing pad block.
2107 MachineBasicBlock *ClauseMBB = FuncInfo.MBB;
2108 ClauseMBB->addSuccessor(LPadBB);
2109 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, Chain,
2110 DAG.getBasicBlock(LPadBB)));
2111 return VReg;
2112}
2113
2114/// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
2115/// small case ranges).
2116bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR,
2117 CaseRecVector& WorkList,
2118 const Value* SV,
2119 MachineBasicBlock *Default,
2120 MachineBasicBlock *SwitchBB) {
2121 // Size is the number of Cases represented by this range.
2122 size_t Size = CR.Range.second - CR.Range.first;
2123 if (Size > 3)
2124 return false;
2125
2126 // Get the MachineFunction which holds the current MBB. This is used when
2127 // inserting any additional MBBs necessary to represent the switch.
2128 MachineFunction *CurMF = FuncInfo.MF;
2129
2130 // Figure out which block is immediately after the current one.
2131 MachineBasicBlock *NextBlock = nullptr;
2132 MachineFunction::iterator BBI = CR.CaseBB;
2133
2134 if (++BBI != FuncInfo.MF->end())
2135 NextBlock = BBI;
2136
2137 BranchProbabilityInfo *BPI = FuncInfo.BPI;
2138 // If any two of the cases has the same destination, and if one value
2139 // is the same as the other, but has one bit unset that the other has set,
2140 // use bit manipulation to do two compares at once. For example:
2141 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
2142 // TODO: This could be extended to merge any 2 cases in switches with 3 cases.
2143 // TODO: Handle cases where CR.CaseBB != SwitchBB.
2144 if (Size == 2 && CR.CaseBB == SwitchBB) {
2145 Case &Small = *CR.Range.first;
2146 Case &Big = *(CR.Range.second-1);
2147
2148 if (Small.Low == Small.High && Big.Low == Big.High && Small.BB == Big.BB) {
2149 const APInt& SmallValue = cast<ConstantInt>(Small.Low)->getValue();
2150 const APInt& BigValue = cast<ConstantInt>(Big.Low)->getValue();
2151
2152 // Check that there is only one bit different.
2153 if (BigValue.countPopulation() == SmallValue.countPopulation() + 1 &&
2154 (SmallValue | BigValue) == BigValue) {
2155 // Isolate the common bit.
2156 APInt CommonBit = BigValue & ~SmallValue;
2157 assert((SmallValue | CommonBit) == BigValue &&(((SmallValue | CommonBit) == BigValue && CommonBit.countPopulation
() == 1 && "Not a common bit?") ? static_cast<void
> (0) : __assert_fail ("(SmallValue | CommonBit) == BigValue && CommonBit.countPopulation() == 1 && \"Not a common bit?\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 2158, __PRETTY_FUNCTION__))
2158 CommonBit.countPopulation() == 1 && "Not a common bit?")(((SmallValue | CommonBit) == BigValue && CommonBit.countPopulation
() == 1 && "Not a common bit?") ? static_cast<void
> (0) : __assert_fail ("(SmallValue | CommonBit) == BigValue && CommonBit.countPopulation() == 1 && \"Not a common bit?\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 2158, __PRETTY_FUNCTION__));
2159
2160 SDValue CondLHS = getValue(SV);
2161 EVT VT = CondLHS.getValueType();
2162 SDLoc DL = getCurSDLoc();
2163
2164 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS,
2165 DAG.getConstant(CommonBit, VT));
2166 SDValue Cond = DAG.getSetCC(DL, MVT::i1,
2167 Or, DAG.getConstant(BigValue, VT),
2168 ISD::SETEQ);
2169
2170 // Update successor info.
2171 // Both Small and Big will jump to Small.BB, so we sum up the weights.
2172 addSuccessorWithWeight(SwitchBB, Small.BB,
2173 Small.ExtraWeight + Big.ExtraWeight);
2174 addSuccessorWithWeight(SwitchBB, Default,
2175 // The default destination is the first successor in IR.
2176 BPI ? BPI->getEdgeWeight(SwitchBB->getBasicBlock(), (unsigned)0) : 0);
2177
2178 // Insert the true branch.
2179 SDValue BrCond = DAG.getNode(ISD::BRCOND, DL, MVT::Other,
2180 getControlRoot(), Cond,
2181 DAG.getBasicBlock(Small.BB));
2182
2183 // Insert the false branch.
2184 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond,
2185 DAG.getBasicBlock(Default));
2186
2187 DAG.setRoot(BrCond);
2188 return true;
2189 }
2190 }
2191 }
2192
2193 // Order cases by weight so the most likely case will be checked first.
2194 uint32_t UnhandledWeights = 0;
2195 if (BPI) {
2196 for (CaseItr I = CR.Range.first, IE = CR.Range.second; I != IE; ++I) {
2197 uint32_t IWeight = I->ExtraWeight;
2198 UnhandledWeights += IWeight;
2199 for (CaseItr J = CR.Range.first; J < I; ++J) {
2200 uint32_t JWeight = J->ExtraWeight;
2201 if (IWeight > JWeight)
2202 std::swap(*I, *J);
2203 }
2204 }
2205 }
2206 // Rearrange the case blocks so that the last one falls through if possible.
2207 Case &BackCase = *(CR.Range.second-1);
2208 if (Size > 1 &&
2209 NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
2210 // The last case block won't fall through into 'NextBlock' if we emit the
2211 // branches in this order. See if rearranging a case value would help.
2212 // We start at the bottom as it's the case with the least weight.
2213 for (Case *I = &*(CR.Range.second-2), *E = &*CR.Range.first-1; I != E; --I)
2214 if (I->BB == NextBlock) {
2215 std::swap(*I, BackCase);
2216 break;
2217 }
2218 }
2219
2220 // Create a CaseBlock record representing a conditional branch to
2221 // the Case's target mbb if the value being switched on SV is equal
2222 // to C.
2223 MachineBasicBlock *CurBlock = CR.CaseBB;
2224 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
2225 MachineBasicBlock *FallThrough;
2226 if (I != E-1) {
2227 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock());
2228 CurMF->insert(BBI, FallThrough);
2229
2230 // Put SV in a virtual register to make it available from the new blocks.
2231 ExportFromCurrentBlock(SV);
2232 } else {
2233 // If the last case doesn't match, go to the default block.
2234 FallThrough = Default;
2235 }
2236
2237 const Value *RHS, *LHS, *MHS;
2238 ISD::CondCode CC;
2239 if (I->High == I->Low) {
2240 // This is just small small case range :) containing exactly 1 case
2241 CC = ISD::SETEQ;
2242 LHS = SV; RHS = I->High; MHS = nullptr;
2243 } else {
2244 CC = ISD::SETLE;
2245 LHS = I->Low; MHS = SV; RHS = I->High;
2246 }
2247
2248 // The false weight should be sum of all un-handled cases.
2249 UnhandledWeights -= I->ExtraWeight;
2250 CaseBlock CB(CC, LHS, RHS, MHS, /* truebb */ I->BB, /* falsebb */ FallThrough,
2251 /* me */ CurBlock,
2252 /* trueweight */ I->ExtraWeight,
2253 /* falseweight */ UnhandledWeights);
2254
2255 // If emitting the first comparison, just call visitSwitchCase to emit the
2256 // code into the current block. Otherwise, push the CaseBlock onto the
2257 // vector to be later processed by SDISel, and insert the node's MBB
2258 // before the next MBB.
2259 if (CurBlock == SwitchBB)
2260 visitSwitchCase(CB, SwitchBB);
2261 else
2262 SwitchCases.push_back(CB);
2263
2264 CurBlock = FallThrough;
2265 }
2266
2267 return true;
2268}
2269
2270static inline bool areJTsAllowed(const TargetLowering &TLI) {
2271 return TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
2272 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other);
2273}
2274
2275static APInt ComputeRange(const APInt &First, const APInt &Last) {
2276 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1;
2277 APInt LastExt = Last.sext(BitWidth), FirstExt = First.sext(BitWidth);
2278 return (LastExt - FirstExt + 1ULL);
2279}
2280
2281/// handleJTSwitchCase - Emit jumptable for current switch case range
2282bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec &CR,
2283 CaseRecVector &WorkList,
2284 const Value *SV,
2285 MachineBasicBlock *Default,
2286 MachineBasicBlock *SwitchBB) {
2287 Case& FrontCase = *CR.Range.first;
2288 Case& BackCase = *(CR.Range.second-1);
2289
2290 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
2291 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
2292
2293 APInt TSize(First.getBitWidth(), 0);
2294 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I)
2295 TSize += I->size();
2296
2297 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2298 if (!areJTsAllowed(TLI) || TSize.ult(TLI.getMinimumJumpTableEntries()))
2299 return false;
2300
2301 APInt Range = ComputeRange(First, Last);
2302 // The density is TSize / Range. Require at least 40%.
2303 // It should not be possible for IntTSize to saturate for sane code, but make
2304 // sure we handle Range saturation correctly.
2305 uint64_t IntRange = Range.getLimitedValue(UINT64_MAX(18446744073709551615UL)/10);
2306 uint64_t IntTSize = TSize.getLimitedValue(UINT64_MAX(18446744073709551615UL)/10);
2307 if (IntTSize * 10 < IntRange * 4)
2308 return false;
2309
2310 DEBUG(dbgs() << "Lowering jump table\n"do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << "Lowering jump table\n" << "First entry: "
<< First << ". Last entry: " << Last <<
'\n' << "Range: " << Range << ". Size: " <<
TSize << ".\n\n"; } } while (0)
2311 << "First entry: " << First << ". Last entry: " << Last << '\n'do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << "Lowering jump table\n" << "First entry: "
<< First << ". Last entry: " << Last <<
'\n' << "Range: " << Range << ". Size: " <<
TSize << ".\n\n"; } } while (0)
2312 << "Range: " << Range << ". Size: " << TSize << ".\n\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << "Lowering jump table\n" << "First entry: "
<< First << ". Last entry: " << Last <<
'\n' << "Range: " << Range << ". Size: " <<
TSize << ".\n\n"; } } while (0);
2313
2314 // Get the MachineFunction which holds the current MBB. This is used when
2315 // inserting any additional MBBs necessary to represent the switch.
2316 MachineFunction *CurMF = FuncInfo.MF;
2317
2318 // Figure out which block is immediately after the current one.
2319 MachineFunction::iterator BBI = CR.CaseBB;
2320 ++BBI;
2321
2322 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2323
2324 // Create a new basic block to hold the code for loading the address
2325 // of the jump table, and jumping to it. Update successor information;
2326 // we will either branch to the default case for the switch, or the jump
2327 // table.
2328 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2329 CurMF->insert(BBI, JumpTableBB);
2330
2331 addSuccessorWithWeight(CR.CaseBB, Default);
2332 addSuccessorWithWeight(CR.CaseBB, JumpTableBB);
2333
2334 // Build a vector of destination BBs, corresponding to each target
2335 // of the jump table. If the value of the jump table slot corresponds to
2336 // a case statement, push the case's BB onto the vector, otherwise, push
2337 // the default BB.
2338 std::vector<MachineBasicBlock*> DestBBs;
2339 APInt TEI = First;
2340 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
2341 const APInt &Low = cast<ConstantInt>(I->Low)->getValue();
2342 const APInt &High = cast<ConstantInt>(I->High)->getValue();
2343
2344 if (Low.sle(TEI) && TEI.sle(High)) {
2345 DestBBs.push_back(I->BB);
2346 if (TEI==High)
2347 ++I;
2348 } else {
2349 DestBBs.push_back(Default);
2350 }
2351 }
2352
2353 // Calculate weight for each unique destination in CR.
2354 DenseMap<MachineBasicBlock*, uint32_t> DestWeights;
2355 if (FuncInfo.BPI)
2356 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
2357 DenseMap<MachineBasicBlock*, uint32_t>::iterator Itr =
2358 DestWeights.find(I->BB);
2359 if (Itr != DestWeights.end())
2360 Itr->second += I->ExtraWeight;
2361 else
2362 DestWeights[I->BB] = I->ExtraWeight;
2363 }
2364
2365 // Update successor info. Add one edge to each unique successor.
2366 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
2367 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
2368 E = DestBBs.end(); I != E; ++I) {
2369 if (!SuccsHandled[(*I)->getNumber()]) {
2370 SuccsHandled[(*I)->getNumber()] = true;
2371 DenseMap<MachineBasicBlock*, uint32_t>::iterator Itr =
2372 DestWeights.find(*I);
2373 addSuccessorWithWeight(JumpTableBB, *I,
2374 Itr != DestWeights.end() ? Itr->second : 0);
2375 }
2376 }
2377
2378 // Create a jump table index for this jump table.
2379 unsigned JTEncoding = TLI.getJumpTableEncoding();
2380 unsigned JTI = CurMF->getOrCreateJumpTableInfo(JTEncoding)
2381 ->createJumpTableIndex(DestBBs);
2382
2383 // Set the jump table information so that we can codegen it as a second
2384 // MachineBasicBlock
2385 JumpTable JT(-1U, JTI, JumpTableBB, Default);
2386 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == SwitchBB));
2387 if (CR.CaseBB == SwitchBB)
2388 visitJumpTableHeader(JT, JTH, SwitchBB);
2389
2390 JTCases.push_back(JumpTableBlock(JTH, JT));
2391 return true;
2392}
2393
2394/// handleBTSplitSwitchCase - emit comparison and split binary search tree into
2395/// 2 subtrees.
2396bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR,
2397 CaseRecVector& WorkList,
2398 const Value* SV,
2399 MachineBasicBlock* SwitchBB) {
2400 Case& FrontCase = *CR.Range.first;
2401 Case& BackCase = *(CR.Range.second-1);
2402
2403 // Size is the number of Cases represented by this range.
2404 unsigned Size = CR.Range.second - CR.Range.first;
2405
2406 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
2407 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
2408 double FMetric = 0;
2409 CaseItr Pivot = CR.Range.first + Size/2;
2410
2411 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
2412 // (heuristically) allow us to emit JumpTable's later.
2413 APInt TSize(First.getBitWidth(), 0);
2414 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2415 I!=E; ++I)
2416 TSize += I->size();
2417
2418 APInt LSize = FrontCase.size();
2419 APInt RSize = TSize-LSize;
2420 DEBUG(dbgs() << "Selecting best pivot: \n"do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << "Selecting best pivot: \n" <<
"First: " << First << ", Last: " << Last <<
'\n' << "LSize: " << LSize << ", RSize: " <<
RSize << '\n'; } } while (0)
2421 << "First: " << First << ", Last: " << Last <<'\n'do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << "Selecting best pivot: \n" <<
"First: " << First << ", Last: " << Last <<
'\n' << "LSize: " << LSize << ", RSize: " <<
RSize << '\n'; } } while (0)
2422 << "LSize: " << LSize << ", RSize: " << RSize << '\n')do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << "Selecting best pivot: \n" <<
"First: " << First << ", Last: " << Last <<
'\n' << "LSize: " << LSize << ", RSize: " <<
RSize << '\n'; } } while (0);
2423 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2424 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
2425 J!=E; ++I, ++J) {
2426 const APInt &LEnd = cast<ConstantInt>(I->High)->getValue();
2427 const APInt &RBegin = cast<ConstantInt>(J->Low)->getValue();
2428 APInt Range = ComputeRange(LEnd, RBegin);
2429 assert((Range - 2ULL).isNonNegative() &&(((Range - 2ULL).isNonNegative() && "Invalid case distance"
) ? static_cast<void> (0) : __assert_fail ("(Range - 2ULL).isNonNegative() && \"Invalid case distance\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 2430, __PRETTY_FUNCTION__))
2430 "Invalid case distance")(((Range - 2ULL).isNonNegative() && "Invalid case distance"
) ? static_cast<void> (0) : __assert_fail ("(Range - 2ULL).isNonNegative() && \"Invalid case distance\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 2430, __PRETTY_FUNCTION__));
2431 // Use volatile double here to avoid excess precision issues on some hosts,
2432 // e.g. that use 80-bit X87 registers.
2433 // Only consider the density of sub-ranges that actually have sufficient
2434 // entries to be lowered as a jump table.
2435 volatile double LDensity =
2436 LSize.ult(TLI.getMinimumJumpTableEntries())
2437 ? 0.0
2438 : LSize.roundToDouble() / (LEnd - First + 1ULL).roundToDouble();
2439 volatile double RDensity =
2440 RSize.ult(TLI.getMinimumJumpTableEntries())
2441 ? 0.0
2442 : RSize.roundToDouble() / (Last - RBegin + 1ULL).roundToDouble();
2443 volatile double Metric = Range.logBase2() * (LDensity + RDensity);
2444 // Should always split in some non-trivial place
2445 DEBUG(dbgs() <<"=>Step\n"do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() <<"=>Step\n" << "LEnd: " <<
LEnd << ", RBegin: " << RBegin << '\n' <<
"LDensity: " << LDensity << ", RDensity: " <<
RDensity << '\n' << "Metric: " << Metric <<
'\n'; } } while (0)
2446 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n'do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() <<"=>Step\n" << "LEnd: " <<
LEnd << ", RBegin: " << RBegin << '\n' <<
"LDensity: " << LDensity << ", RDensity: " <<
RDensity << '\n' << "Metric: " << Metric <<
'\n'; } } while (0)
2447 << "LDensity: " << LDensitydo { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() <<"=>Step\n" << "LEnd: " <<
LEnd << ", RBegin: " << RBegin << '\n' <<
"LDensity: " << LDensity << ", RDensity: " <<
RDensity << '\n' << "Metric: " << Metric <<
'\n'; } } while (0)
2448 << ", RDensity: " << RDensity << '\n'do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() <<"=>Step\n" << "LEnd: " <<
LEnd << ", RBegin: " << RBegin << '\n' <<
"LDensity: " << LDensity << ", RDensity: " <<
RDensity << '\n' << "Metric: " << Metric <<
'\n'; } } while (0)
2449 << "Metric: " << Metric << '\n')do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() <<"=>Step\n" << "LEnd: " <<
LEnd << ", RBegin: " << RBegin << '\n' <<
"LDensity: " << LDensity << ", RDensity: " <<
RDensity << '\n' << "Metric: " << Metric <<
'\n'; } } while (0);
2450 if (FMetric < Metric) {
2451 Pivot = J;
2452 FMetric = Metric;
2453 DEBUG(dbgs() << "Current metric set to: " << FMetric << '\n')do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << "Current metric set to: " <<
FMetric << '\n'; } } while (0);
2454 }
2455
2456 LSize += J->size();
2457 RSize -= J->size();
2458 }
2459
2460 if (FMetric == 0 || !areJTsAllowed(TLI))
2461 Pivot = CR.Range.first + Size/2;
2462 splitSwitchCase(CR, Pivot, WorkList, SV, SwitchBB);
2463 return true;
2464}
2465
2466void SelectionDAGBuilder::splitSwitchCase(CaseRec &CR, CaseItr Pivot,
2467 CaseRecVector &WorkList,
2468 const Value *SV,
2469 MachineBasicBlock *SwitchBB) {
2470 // Get the MachineFunction which holds the current MBB. This is used when
2471 // inserting any additional MBBs necessary to represent the switch.
2472 MachineFunction *CurMF = FuncInfo.MF;
2473
2474 // Figure out which block is immediately after the current one.
2475 MachineFunction::iterator BBI = CR.CaseBB;
2476 ++BBI;
2477
2478 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2479
2480 CaseRange LHSR(CR.Range.first, Pivot);
2481 CaseRange RHSR(Pivot, CR.Range.second);
2482 const Constant *C = Pivot->Low;
2483 MachineBasicBlock *FalseBB = nullptr, *TrueBB = nullptr;
2484
2485 // We know that we branch to the LHS if the Value being switched on is
2486 // less than the Pivot value, C. We use this to optimize our binary
2487 // tree a bit, by recognizing that if SV is greater than or equal to the
2488 // LHS's Case Value, and that Case Value is exactly one less than the
2489 // Pivot's Value, then we can branch directly to the LHS's Target,
2490 // rather than creating a leaf node for it.
2491 if ((LHSR.second - LHSR.first) == 1 && LHSR.first->High == CR.GE &&
2492 cast<ConstantInt>(C)->getValue() ==
2493 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) {
2494 TrueBB = LHSR.first->BB;
2495 } else {
2496 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2497 CurMF->insert(BBI, TrueBB);
2498 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
2499
2500 // Put SV in a virtual register to make it available from the new blocks.
2501 ExportFromCurrentBlock(SV);
2502 }
2503
2504 // Similar to the optimization above, if the Value being switched on is
2505 // known to be less than the Constant CR.LT, and the current Case Value
2506 // is CR.LT - 1, then we can branch directly to the target block for
2507 // the current Case Value, rather than emitting a RHS leaf node for it.
2508 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
2509 cast<ConstantInt>(RHSR.first->Low)->getValue() ==
2510 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) {
2511 FalseBB = RHSR.first->BB;
2512 } else {
2513 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2514 CurMF->insert(BBI, FalseBB);
2515 WorkList.push_back(CaseRec(FalseBB, CR.LT, C, RHSR));
2516
2517 // Put SV in a virtual register to make it available from the new blocks.
2518 ExportFromCurrentBlock(SV);
2519 }
2520
2521 // Create a CaseBlock record representing a conditional branch to
2522 // the LHS node if the value being switched on SV is less than C.
2523 // Otherwise, branch to LHS.
2524 CaseBlock CB(ISD::SETLT, SV, C, nullptr, TrueBB, FalseBB, CR.CaseBB);
2525
2526 if (CR.CaseBB == SwitchBB)
2527 visitSwitchCase(CB, SwitchBB);
2528 else
2529 SwitchCases.push_back(CB);
2530}
2531
2532/// handleBitTestsSwitchCase - if current case range has few destination and
2533/// range span less, than machine word bitwidth, encode case range into series
2534/// of masks and emit bit tests with these masks.
2535bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR,
2536 CaseRecVector& WorkList,
2537 const Value* SV,
2538 MachineBasicBlock* Default,
2539 MachineBasicBlock* SwitchBB) {
2540 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2541 EVT PTy = TLI.getPointerTy();
2542 unsigned IntPtrBits = PTy.getSizeInBits();
2543
2544 Case& FrontCase = *CR.Range.first;
2545 Case& BackCase = *(CR.Range.second-1);
2546
2547 // Get the MachineFunction which holds the current MBB. This is used when
2548 // inserting any additional MBBs necessary to represent the switch.
2549 MachineFunction *CurMF = FuncInfo.MF;
2550
2551 // If target does not have legal shift left, do not emit bit tests at all.
2552 if (!TLI.isOperationLegal(ISD::SHL, PTy))
2553 return false;
2554
2555 size_t numCmps = 0;
2556 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
2557 // Single case counts one, case range - two.
2558 numCmps += (I->Low == I->High ? 1 : 2);
2559 }
2560
2561 // Count unique destinations
2562 SmallSet<MachineBasicBlock*, 4> Dests;
2563 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
2564 Dests.insert(I->BB);
2565 if (Dests.size() > 3)
2566 // Don't bother the code below, if there are too much unique destinations
2567 return false;
2568 }
2569 DEBUG(dbgs() << "Total number of unique destinations: "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << "Total number of unique destinations: "
<< Dests.size() << '\n' << "Total number of comparisons: "
<< numCmps << '\n'; } } while (0)
2570 << Dests.size() << '\n'do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << "Total number of unique destinations: "
<< Dests.size() << '\n' << "Total number of comparisons: "
<< numCmps << '\n'; } } while (0)
2571 << "Total number of comparisons: " << numCmps << '\n')do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << "Total number of unique destinations: "
<< Dests.size() << '\n' << "Total number of comparisons: "
<< numCmps << '\n'; } } while (0);
2572
2573 // Compute span of values.
2574 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue();
2575 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue();
2576 APInt cmpRange = maxValue - minValue;
2577
2578 DEBUG(dbgs() << "Compare range: " << cmpRange << '\n'do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << "Compare range: " << cmpRange
<< '\n' << "Low bound: " << minValue <<
'\n' << "High bound: " << maxValue << '\n'
; } } while (0)
2579 << "Low bound: " << minValue << '\n'do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << "Compare range: " << cmpRange
<< '\n' << "Low bound: " << minValue <<
'\n' << "High bound: " << maxValue << '\n'
; } } while (0)
2580 << "High bound: " << maxValue << '\n')do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << "Compare range: " << cmpRange
<< '\n' << "Low bound: " << minValue <<
'\n' << "High bound: " << maxValue << '\n'
; } } while (0);
2581
2582 if (cmpRange.uge(IntPtrBits) ||
2583 (!(Dests.size() == 1 && numCmps >= 3) &&
2584 !(Dests.size() == 2 && numCmps >= 5) &&
2585 !(Dests.size() >= 3 && numCmps >= 6)))
2586 return false;
2587
2588 DEBUG(dbgs() << "Emitting bit tests\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << "Emitting bit tests\n"; } } while
(0);
2589 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth());
2590
2591 // Optimize the case where all the case values fit in a
2592 // word without having to subtract minValue. In this case,
2593 // we can optimize away the subtraction.
2594 if (minValue.isNonNegative() && maxValue.slt(IntPtrBits)) {
2595 cmpRange = maxValue;
2596 } else {
2597 lowBound = minValue;
2598 }
2599
2600 CaseBitsVector CasesBits;
2601 unsigned i, count = 0;
2602
2603 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2604 MachineBasicBlock* Dest = I->BB;
2605 for (i = 0; i < count; ++i)
2606 if (Dest == CasesBits[i].BB)
2607 break;
2608
2609 if (i == count) {
2610 assert((count < 3) && "Too much destinations to test!")(((count < 3) && "Too much destinations to test!")
? static_cast<void> (0) : __assert_fail ("(count < 3) && \"Too much destinations to test!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 2610, __PRETTY_FUNCTION__));
2611 CasesBits.push_back(CaseBits(0, Dest, 0, 0/*Weight*/));
2612 count++;
2613 }
2614
2615 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue();
2616 const APInt& highValue = cast<ConstantInt>(I->High)->getValue();
2617
2618 uint64_t lo = (lowValue - lowBound).getZExtValue();
2619 uint64_t hi = (highValue - lowBound).getZExtValue();
2620 CasesBits[i].ExtraWeight += I->ExtraWeight;
2621
2622 for (uint64_t j = lo; j <= hi; j++) {
2623 CasesBits[i].Mask |= 1ULL << j;
2624 CasesBits[i].Bits++;
2625 }
2626
2627 }
2628 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
2629
2630 BitTestInfo BTC;
2631
2632 // Figure out which block is immediately after the current one.
2633 MachineFunction::iterator BBI = CR.CaseBB;
2634 ++BBI;
2635
2636 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2637
2638 DEBUG(dbgs() << "Cases:\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << "Cases:\n"; } } while (0);
2639 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
2640 DEBUG(dbgs() << "Mask: " << CasesBits[i].Maskdo { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << "Mask: " << CasesBits[i].Mask
<< ", Bits: " << CasesBits[i].Bits << ", BB: "
<< CasesBits[i].BB << '\n'; } } while (0)
2641 << ", Bits: " << CasesBits[i].Bitsdo { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << "Mask: " << CasesBits[i].Mask
<< ", Bits: " << CasesBits[i].Bits << ", BB: "
<< CasesBits[i].BB << '\n'; } } while (0)
2642 << ", BB: " << CasesBits[i].BB << '\n')do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << "Mask: " << CasesBits[i].Mask
<< ", Bits: " << CasesBits[i].Bits << ", BB: "
<< CasesBits[i].BB << '\n'; } } while (0);
2643
2644 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2645 CurMF->insert(BBI, CaseBB);
2646 BTC.push_back(BitTestCase(CasesBits[i].Mask,
2647 CaseBB,
2648 CasesBits[i].BB, CasesBits[i].ExtraWeight));
2649
2650 // Put SV in a virtual register to make it available from the new blocks.
2651 ExportFromCurrentBlock(SV);
2652 }
2653
2654 BitTestBlock BTB(lowBound, cmpRange, SV,
2655 -1U, MVT::Other, (CR.CaseBB == SwitchBB),
2656 CR.CaseBB, Default, std::move(BTC));
2657
2658 if (CR.CaseBB == SwitchBB)
2659 visitBitTestHeader(BTB, SwitchBB);
2660
2661 BitTestCases.push_back(std::move(BTB));
2662
2663 return true;
2664}
2665
2666/// Clusterify - Transform simple list of Cases into list of CaseRange's
2667void SelectionDAGBuilder::Clusterify(CaseVector& Cases,
2668 const SwitchInst& SI) {
2669 BranchProbabilityInfo *BPI = FuncInfo.BPI;
2670 // Start with "simple" cases.
2671 for (SwitchInst::ConstCaseIt i : SI.cases()) {
2672 const BasicBlock *SuccBB = i.getCaseSuccessor();
2673 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SuccBB];
2674
2675 uint32_t ExtraWeight =
2676 BPI ? BPI->getEdgeWeight(SI.getParent(), i.getSuccessorIndex()) : 0;
2677
2678 Cases.push_back(Case(i.getCaseValue(), i.getCaseValue(),
2679 SMBB, ExtraWeight));
2680 }
2681 std::sort(Cases.begin(), Cases.end(), CaseCmp());
2682
2683 // Merge case into clusters
2684 if (Cases.size() >= 2)
2685 // Must recompute end() each iteration because it may be
2686 // invalidated by erase if we hold on to it
2687 for (CaseItr I = Cases.begin(), J = std::next(Cases.begin());
2688 J != Cases.end(); ) {
2689 const APInt& nextValue = cast<ConstantInt>(J->Low)->getValue();
2690 const APInt& currentValue = cast<ConstantInt>(I->High)->getValue();
2691 MachineBasicBlock* nextBB = J->BB;
2692 MachineBasicBlock* currentBB = I->BB;
2693
2694 // If the two neighboring cases go to the same destination, merge them
2695 // into a single case.
2696 if ((nextValue - currentValue == 1) && (currentBB == nextBB)) {
2697 I->High = J->High;
2698 I->ExtraWeight += J->ExtraWeight;
2699 J = Cases.erase(J);
2700 } else {
2701 I = J++;
2702 }
2703 }
2704
2705 DEBUG({do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { { size_t numCmps = 0; for (auto &I : Cases) numCmps
+= I.Low != I.High ? 2 : 1; dbgs() << "Clusterify finished. Total clusters: "
<< Cases.size() << ". Total compares: " <<
numCmps << '\n'; }; } } while (0)
2706 size_t numCmps = 0;do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { { size_t numCmps = 0; for (auto &I : Cases) numCmps
+= I.Low != I.High ? 2 : 1; dbgs() << "Clusterify finished. Total clusters: "
<< Cases.size() << ". Total compares: " <<
numCmps << '\n'; }; } } while (0)
2707 for (auto &I : Cases)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { { size_t numCmps = 0; for (auto &I : Cases) numCmps
+= I.Low != I.High ? 2 : 1; dbgs() << "Clusterify finished. Total clusters: "
<< Cases.size() << ". Total compares: " <<
numCmps << '\n'; }; } } while (0)
2708 // A range counts double, since it requires two compares.do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { { size_t numCmps = 0; for (auto &I : Cases) numCmps
+= I.Low != I.High ? 2 : 1; dbgs() << "Clusterify finished. Total clusters: "
<< Cases.size() << ". Total compares: " <<
numCmps << '\n'; }; } } while (0)
2709 numCmps += I.Low != I.High ? 2 : 1;do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { { size_t numCmps = 0; for (auto &I : Cases) numCmps
+= I.Low != I.High ? 2 : 1; dbgs() << "Clusterify finished. Total clusters: "
<< Cases.size() << ". Total compares: " <<
numCmps << '\n'; }; } } while (0)
2710
2711 dbgs() << "Clusterify finished. Total clusters: " << Cases.size()do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { { size_t numCmps = 0; for (auto &I : Cases) numCmps
+= I.Low != I.High ? 2 : 1; dbgs() << "Clusterify finished. Total clusters: "
<< Cases.size() << ". Total compares: " <<
numCmps << '\n'; }; } } while (0)
2712 << ". Total compares: " << numCmps << '\n';do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { { size_t numCmps = 0; for (auto &I : Cases) numCmps
+= I.Low != I.High ? 2 : 1; dbgs() << "Clusterify finished. Total clusters: "
<< Cases.size() << ". Total compares: " <<
numCmps << '\n'; }; } } while (0)
2713 })do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { { size_t numCmps = 0; for (auto &I : Cases) numCmps
+= I.Low != I.High ? 2 : 1; dbgs() << "Clusterify finished. Total clusters: "
<< Cases.size() << ". Total compares: " <<
numCmps << '\n'; }; } } while (0);
2714}
2715
2716void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First,
2717 MachineBasicBlock *Last) {
2718 // Update JTCases.
2719 for (unsigned i = 0, e = JTCases.size(); i != e; ++i)
2720 if (JTCases[i].first.HeaderBB == First)
2721 JTCases[i].first.HeaderBB = Last;
2722
2723 // Update BitTestCases.
2724 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i)
2725 if (BitTestCases[i].Parent == First)
2726 BitTestCases[i].Parent = Last;
2727}
2728
2729void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
2730 MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
2731
2732 // Figure out which block is immediately after the current one.
2733 MachineBasicBlock *NextBlock = nullptr;
2734 if (SwitchMBB + 1 != FuncInfo.MF->end())
2735 NextBlock = SwitchMBB + 1;
2736
2737
2738 // Create a vector of Cases, sorted so that we can efficiently create a binary
2739 // search tree from them.
2740 CaseVector Cases;
2741 Clusterify(Cases, SI);
2742
2743 // Get the default destination MBB.
2744 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
2745
2746 if (isa<UnreachableInst>(SI.getDefaultDest()->getFirstNonPHIOrDbg()) &&
2747 !Cases.empty()) {
2748 // Replace an unreachable default destination with the most popular case
2749 // destination.
2750 DenseMap<const BasicBlock *, unsigned> Popularity;
2751 unsigned MaxPop = 0;
2752 const BasicBlock *MaxBB = nullptr;
2753 for (auto I : SI.cases()) {
2754 const BasicBlock *BB = I.getCaseSuccessor();
2755 if (++Popularity[BB] > MaxPop) {
2756 MaxPop = Popularity[BB];
2757 MaxBB = BB;
2758 }
2759 }
2760
2761 // Set new default.
2762 assert(MaxPop > 0)((MaxPop > 0) ? static_cast<void> (0) : __assert_fail
("MaxPop > 0", "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 2762, __PRETTY_FUNCTION__));
2763 assert(MaxBB)((MaxBB) ? static_cast<void> (0) : __assert_fail ("MaxBB"
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 2763, __PRETTY_FUNCTION__));
2764 Default = FuncInfo.MBBMap[MaxBB];
2765
2766 // Remove cases that were pointing to the destination that is now the default.
2767 Cases.erase(std::remove_if(Cases.begin(), Cases.end(),
2768 [&](const Case &C) { return C.BB == Default; }),
2769 Cases.end());
2770 }
2771
2772 // If there is only the default destination, go there directly.
2773 if (Cases.empty()) {
2774 // Update machine-CFG edges.
2775 SwitchMBB->addSuccessor(Default);
2776
2777 // If this is not a fall-through branch, emit the branch.
2778 if (Default != NextBlock) {
2779 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other,
2780 getControlRoot(), DAG.getBasicBlock(Default)));
2781 }
2782 return;
2783 }
2784
2785 // Get the Value to be switched on.
2786 const Value *SV = SI.getCondition();
2787
2788 // Push the initial CaseRec onto the worklist
2789 CaseRecVector WorkList;
2790 WorkList.push_back(CaseRec(SwitchMBB,nullptr,nullptr,
2791 CaseRange(Cases.begin(),Cases.end())));
2792
2793 while (!WorkList.empty()) {
2794 // Grab a record representing a case range to process off the worklist
2795 CaseRec CR = WorkList.back();
2796 WorkList.pop_back();
2797
2798 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2799 continue;
2800
2801 // If the range has few cases (two or less) emit a series of specific
2802 // tests.
2803 if (handleSmallSwitchRange(CR, WorkList, SV, Default, SwitchMBB))
2804 continue;
2805
2806 // If the switch has more than N blocks, and is at least 40% dense, and the
2807 // target supports indirect branches, then emit a jump table rather than
2808 // lowering the switch to a binary tree of conditional branches.
2809 // N defaults to 4 and is controlled via TLS.getMinimumJumpTableEntries().
2810 if (handleJTSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2811 continue;
2812
2813 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2814 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2815 handleBTSplitSwitchCase(CR, WorkList, SV, SwitchMBB);
2816 }
2817}
2818
2819void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
2820 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB;
2821
2822 // Update machine-CFG edges with unique successors.
2823 SmallSet<BasicBlock*, 32> Done;
2824 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) {
2825 BasicBlock *BB = I.getSuccessor(i);
2826 bool Inserted = Done.insert(BB).second;
2827 if (!Inserted)
2828 continue;
2829
2830 MachineBasicBlock *Succ = FuncInfo.MBBMap[BB];
2831 addSuccessorWithWeight(IndirectBrMBB, Succ);
2832 }
2833
2834 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurSDLoc(),
2835 MVT::Other, getControlRoot(),
2836 getValue(I.getAddress())));
2837}
2838
2839void SelectionDAGBuilder::visitUnreachable(const UnreachableInst &I) {
2840 if (DAG.getTarget().Options.TrapUnreachable)
2841 DAG.setRoot(DAG.getNode(ISD::TRAP, getCurSDLoc(), MVT::Other, DAG.getRoot()));
2842}
2843
2844void SelectionDAGBuilder::visitFSub(const User &I) {
2845 // -0.0 - X --> fneg
2846 Type *Ty = I.getType();
2847 if (isa<Constant>(I.getOperand(0)) &&
2848 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) {
2849 SDValue Op2 = getValue(I.getOperand(1));
2850 setValue(&I, DAG.getNode(ISD::FNEG, getCurSDLoc(),
2851 Op2.getValueType(), Op2));
2852 return;
2853 }
2854
2855 visitBinary(I, ISD::FSUB);
2856}
2857
2858void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
2859 SDValue Op1 = getValue(I.getOperand(0));
2860 SDValue Op2 = getValue(I.getOperand(1));
2861
2862 bool nuw = false;
2863 bool nsw = false;
2864 bool exact = false;
2865 if (const OverflowingBinaryOperator *OFBinOp =
2866 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2867 nuw = OFBinOp->hasNoUnsignedWrap();
2868 nsw = OFBinOp->hasNoSignedWrap();
2869 }
2870 if (const PossiblyExactOperator *ExactOp =
2871 dyn_cast<const PossiblyExactOperator>(&I))
2872 exact = ExactOp->isExact();
2873
2874 SDValue BinNodeValue = DAG.getNode(OpCode, getCurSDLoc(), Op1.getValueType(),
2875 Op1, Op2, nuw, nsw, exact);
2876 setValue(&I, BinNodeValue);
2877}
2878
2879void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
2880 SDValue Op1 = getValue(I.getOperand(0));
2881 SDValue Op2 = getValue(I.getOperand(1));
2882
2883 EVT ShiftTy =
2884 DAG.getTargetLoweringInfo().getShiftAmountTy(Op2.getValueType());
2885
2886 // Coerce the shift amount to the right type if we can.
2887 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) {
2888 unsigned ShiftSize = ShiftTy.getSizeInBits();
2889 unsigned Op2Size = Op2.getValueType().getSizeInBits();
2890 SDLoc DL = getCurSDLoc();
2891
2892 // If the operand is smaller than the shift count type, promote it.
2893 if (ShiftSize > Op2Size)
2894 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2);
2895
2896 // If the operand is larger than the shift count type but the shift
2897 // count type has enough bits to represent any shift value, truncate
2898 // it now. This is a common case and it exposes the truncate to
2899 // optimization early.
2900 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2901 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2);
2902 // Otherwise we'll need to temporarily settle for some other convenient
2903 // type. Type legalization will make adjustments once the shiftee is split.
2904 else
2905 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32);
2906 }
2907
2908 bool nuw = false;
2909 bool nsw = false;
2910 bool exact = false;
2911
2912 if (Opcode == ISD::SRL || Opcode == ISD::SRA || Opcode == ISD::SHL) {
2913
2914 if (const OverflowingBinaryOperator *OFBinOp =
2915 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2916 nuw = OFBinOp->hasNoUnsignedWrap();
2917 nsw = OFBinOp->hasNoSignedWrap();
2918 }
2919 if (const PossiblyExactOperator *ExactOp =
2920 dyn_cast<const PossiblyExactOperator>(&I))
2921 exact = ExactOp->isExact();
2922 }
2923
2924 SDValue Res = DAG.getNode(Opcode, getCurSDLoc(), Op1.getValueType(), Op1, Op2,
2925 nuw, nsw, exact);
2926 setValue(&I, Res);
2927}
2928
2929void SelectionDAGBuilder::visitSDiv(const User &I) {
2930 SDValue Op1 = getValue(I.getOperand(0));
2931 SDValue Op2 = getValue(I.getOperand(1));
2932
2933 // Turn exact SDivs into multiplications.
2934 // FIXME: This should be in DAGCombiner, but it doesn't have access to the
2935 // exact bit.
2936 if (isa<BinaryOperator>(&I) && cast<BinaryOperator>(&I)->isExact() &&
2937 !isa<ConstantSDNode>(Op1) &&
2938 isa<ConstantSDNode>(Op2) && !cast<ConstantSDNode>(Op2)->isNullValue())
2939 setValue(&I, DAG.getTargetLoweringInfo()
2940 .BuildExactSDIV(Op1, Op2, getCurSDLoc(), DAG));
2941 else
2942 setValue(&I, DAG.getNode(ISD::SDIV, getCurSDLoc(), Op1.getValueType(),
2943 Op1, Op2));
2944}
2945
2946void SelectionDAGBuilder::visitICmp(const User &I) {
2947 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2948 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2949 predicate = IC->getPredicate();
2950 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2951 predicate = ICmpInst::Predicate(IC->getPredicate());
2952 SDValue Op1 = getValue(I.getOperand(0));
2953 SDValue Op2 = getValue(I.getOperand(1));
2954 ISD::CondCode Opcode = getICmpCondCode(predicate);
2955
2956 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2957 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Opcode));
2958}
2959
2960void SelectionDAGBuilder::visitFCmp(const User &I) {
2961 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2962 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2963 predicate = FC->getPredicate();
2964 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2965 predicate = FCmpInst::Predicate(FC->getPredicate());
2966 SDValue Op1 = getValue(I.getOperand(0));
2967 SDValue Op2 = getValue(I.getOperand(1));
2968 ISD::CondCode Condition = getFCmpCondCode(predicate);
2969 if (TM.Options.NoNaNsFPMath)
2970 Condition = getFCmpCodeWithoutNaN(Condition);
2971 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2972 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Condition));
2973}
2974
2975void SelectionDAGBuilder::visitSelect(const User &I) {
2976 SmallVector<EVT, 4> ValueVTs;
2977 ComputeValueVTs(DAG.getTargetLoweringInfo(), I.getType(), ValueVTs);
2978 unsigned NumValues = ValueVTs.size();
2979 if (NumValues == 0) return;
2980
2981 SmallVector<SDValue, 4> Values(NumValues);
2982 SDValue Cond = getValue(I.getOperand(0));
2983 SDValue TrueVal = getValue(I.getOperand(1));
2984 SDValue FalseVal = getValue(I.getOperand(2));
2985 ISD::NodeType OpCode = Cond.getValueType().isVector() ?
2986 ISD::VSELECT : ISD::SELECT;
2987
2988 for (unsigned i = 0; i != NumValues; ++i)
2989 Values[i] = DAG.getNode(OpCode, getCurSDLoc(),
2990 TrueVal.getNode()->getValueType(TrueVal.getResNo()+i),
2991 Cond,
2992 SDValue(TrueVal.getNode(),
2993 TrueVal.getResNo() + i),
2994 SDValue(FalseVal.getNode(),
2995 FalseVal.getResNo() + i));
2996
2997 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2998 DAG.getVTList(ValueVTs), Values));
2999}
3000
3001void SelectionDAGBuilder::visitTrunc(const User &I) {
3002 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
3003 SDValue N = getValue(I.getOperand(0));
3004 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
3005 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), DestVT, N));
3006}
3007
3008void SelectionDAGBuilder::visitZExt(const User &I) {
3009 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
3010 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
3011 SDValue N = getValue(I.getOperand(0));
3012 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
3013 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurSDLoc(), DestVT, N));
3014}
3015
3016void SelectionDAGBuilder::visitSExt(const User &I) {
3017 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
3018 // SExt also can't be a cast to bool for same reason. So, nothing much to do
3019 SDValue N = getValue(I.getOperand(0));
3020 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
3021 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurSDLoc(), DestVT, N));
3022}
3023
3024void SelectionDAGBuilder::visitFPTrunc(const User &I) {
3025 // FPTrunc is never a no-op cast, no need to check
3026 SDValue N = getValue(I.getOperand(0));
3027 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3028 EVT DestVT = TLI.getValueType(I.getType());
3029 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurSDLoc(), DestVT, N,
3030 DAG.getTargetConstant(0, TLI.getPointerTy())));
3031}
3032
3033void SelectionDAGBuilder::visitFPExt(const User &I) {
3034 // FPExt is never a no-op cast, no need to check
3035 SDValue N = getValue(I.getOperand(0));
3036 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
3037 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurSDLoc(), DestVT, N));
3038}
3039
3040void SelectionDAGBuilder::visitFPToUI(const User &I) {
3041 // FPToUI is never a no-op cast, no need to check
3042 SDValue N = getValue(I.getOperand(0));
3043 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
3044 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurSDLoc(), DestVT, N));
3045}
3046
3047void SelectionDAGBuilder::visitFPToSI(const User &I) {
3048 // FPToSI is never a no-op cast, no need to check
3049 SDValue N = getValue(I.getOperand(0));
3050 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
3051 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurSDLoc(), DestVT, N));
3052}
3053
3054void SelectionDAGBuilder::visitUIToFP(const User &I) {
3055 // UIToFP is never a no-op cast, no need to check
3056 SDValue N = getValue(I.getOperand(0));
3057 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
3058 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurSDLoc(), DestVT, N));
3059}
3060
3061void SelectionDAGBuilder::visitSIToFP(const User &I) {
3062 // SIToFP is never a no-op cast, no need to check
3063 SDValue N = getValue(I.getOperand(0));
3064 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
3065 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurSDLoc(), DestVT, N));
3066}
3067
3068void SelectionDAGBuilder::visitPtrToInt(const User &I) {
3069 // What to do depends on the size of the integer and the size of the pointer.
3070 // We can either truncate, zero extend, or no-op, accordingly.
3071 SDValue N = getValue(I.getOperand(0));
3072 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
3073 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
3074}
3075
3076void SelectionDAGBuilder::visitIntToPtr(const User &I) {
3077 // What to do depends on the size of the integer and the size of the pointer.
3078 // We can either truncate, zero extend, or no-op, accordingly.
3079 SDValue N = getValue(I.getOperand(0));
3080 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
3081 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
3082}
3083
3084void SelectionDAGBuilder::visitBitCast(const User &I) {
3085 SDValue N = getValue(I.getOperand(0));
3086 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
3087
3088 // BitCast assures us that source and destination are the same size so this is
3089 // either a BITCAST or a no-op.
3090 if (DestVT != N.getValueType())
3091 setValue(&I, DAG.getNode(ISD::BITCAST, getCurSDLoc(),
3092 DestVT, N)); // convert types.
3093 // Check if the original LLVM IR Operand was a ConstantInt, because getValue()
3094 // might fold any kind of constant expression to an integer constant and that
3095 // is not what we are looking for. Only regcognize a bitcast of a genuine
3096 // constant integer as an opaque constant.
3097 else if(ConstantInt *C = dyn_cast<ConstantInt>(I.getOperand(0)))
3098 setValue(&I, DAG.getConstant(C->getValue(), DestVT, /*isTarget=*/false,
3099 /*isOpaque*/true));
3100 else
3101 setValue(&I, N); // noop cast.
3102}
3103
3104void SelectionDAGBuilder::visitAddrSpaceCast(const User &I) {
3105 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3106 const Value *SV = I.getOperand(0);
3107 SDValue N = getValue(SV);
3108 EVT DestVT = TLI.getValueType(I.getType());
3109
3110 unsigned SrcAS = SV->getType()->getPointerAddressSpace();
3111 unsigned DestAS = I.getType()->getPointerAddressSpace();
3112
3113 if (!TLI.isNoopAddrSpaceCast(SrcAS, DestAS))
3114 N = DAG.getAddrSpaceCast(getCurSDLoc(), DestVT, N, SrcAS, DestAS);
3115
3116 setValue(&I, N);
3117}
3118
3119void SelectionDAGBuilder::visitInsertElement(const User &I) {
3120 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3121 SDValue InVec = getValue(I.getOperand(0));
3122 SDValue InVal = getValue(I.getOperand(1));
3123 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(2)),
3124 getCurSDLoc(), TLI.getVectorIdxTy());
3125 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurSDLoc(),
3126 TLI.getValueType(I.getType()), InVec, InVal, InIdx));
3127}
3128
3129void SelectionDAGBuilder::visitExtractElement(const User &I) {
3130 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3131 SDValue InVec = getValue(I.getOperand(0));
3132 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(1)),
3133 getCurSDLoc(), TLI.getVectorIdxTy());
3134 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(),
3135 TLI.getValueType(I.getType()), InVec, InIdx));
3136}
3137
3138// Utility for visitShuffleVector - Return true if every element in Mask,
3139// beginning from position Pos and ending in Pos+Size, falls within the
3140// specified sequential range [L, L+Pos). or is undef.
3141static bool isSequentialInRange(const SmallVectorImpl<int> &Mask,
3142 unsigned Pos, unsigned Size, int Low) {
3143 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3144 if (Mask[i] >= 0 && Mask[i] != Low)
3145 return false;
3146 return true;
3147}
3148
3149void SelectionDAGBuilder::visitShuffleVector(const User &I) {
3150 SDValue Src1 = getValue(I.getOperand(0));
3151 SDValue Src2 = getValue(I.getOperand(1));
3152
3153 SmallVector<int, 8> Mask;
3154 ShuffleVectorInst::getShuffleMask(cast<Constant>(I.getOperand(2)), Mask);
3155 unsigned MaskNumElts = Mask.size();
3156
3157 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3158 EVT VT = TLI.getValueType(I.getType());
3159 EVT SrcVT = Src1.getValueType();
3160 unsigned SrcNumElts = SrcVT.getVectorNumElements();
3161
3162 if (SrcNumElts == MaskNumElts) {
3163 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
3164 &Mask[0]));
3165 return;
3166 }
3167
3168 // Normalize the shuffle vector since mask and vector length don't match.
3169 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
3170 // Mask is longer than the source vectors and is a multiple of the source
3171 // vectors. We can use concatenate vector to make the mask and vectors
3172 // lengths match.
3173 if (SrcNumElts*2 == MaskNumElts) {
3174 // First check for Src1 in low and Src2 in high
3175 if (isSequentialInRange(Mask, 0, SrcNumElts, 0) &&
3176 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, SrcNumElts)) {
3177 // The shuffle is concatenating two vectors together.
3178 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
3179 VT, Src1, Src2));
3180 return;
3181 }
3182 // Then check for Src2 in low and Src1 in high
3183 if (isSequentialInRange(Mask, 0, SrcNumElts, SrcNumElts) &&
3184 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, 0)) {
3185 // The shuffle is concatenating two vectors together.
3186 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
3187 VT, Src2, Src1));
3188 return;
3189 }
3190 }
3191
3192 // Pad both vectors with undefs to make them the same length as the mask.
3193 unsigned NumConcat = MaskNumElts / SrcNumElts;
3194 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
3195 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
3196 SDValue UndefVal = DAG.getUNDEF(SrcVT);
3197
3198 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
3199 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
3200 MOps1[0] = Src1;
3201 MOps2[0] = Src2;
3202
3203 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
3204 getCurSDLoc(), VT, MOps1);
3205 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
3206 getCurSDLoc(), VT, MOps2);
3207
3208 // Readjust mask for new input vector length.
3209 SmallVector<int, 8> MappedOps;
3210 for (unsigned i = 0; i != MaskNumElts; ++i) {
3211 int Idx = Mask[i];
3212 if (Idx >= (int)SrcNumElts)
3213 Idx -= SrcNumElts - MaskNumElts;
3214 MappedOps.push_back(Idx);
3215 }
3216
3217 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
3218 &MappedOps[0]));
3219 return;
3220 }
3221
3222 if (SrcNumElts > MaskNumElts) {
3223 // Analyze the access pattern of the vector to see if we can extract
3224 // two subvectors and do the shuffle. The analysis is done by calculating
3225 // the range of elements the mask access on both vectors.
3226 int MinRange[2] = { static_cast<int>(SrcNumElts),
3227 static_cast<int>(SrcNumElts)};
3228 int MaxRange[2] = {-1, -1};
3229
3230 for (unsigned i = 0; i != MaskNumElts; ++i) {
3231 int Idx = Mask[i];
3232 unsigned Input = 0;
3233 if (Idx < 0)
3234 continue;
3235
3236 if (Idx >= (int)SrcNumElts) {
3237 Input = 1;
3238 Idx -= SrcNumElts;
3239 }
3240 if (Idx > MaxRange[Input])
3241 MaxRange[Input] = Idx;
3242 if (Idx < MinRange[Input])
3243 MinRange[Input] = Idx;
3244 }
3245
3246 // Check if the access is smaller than the vector size and can we find
3247 // a reasonable extract index.
3248 int RangeUse[2] = { -1, -1 }; // 0 = Unused, 1 = Extract, -1 = Can not
3249 // Extract.
3250 int StartIdx[2]; // StartIdx to extract from
3251 for (unsigned Input = 0; Input < 2; ++Input) {
3252 if (MinRange[Input] >= (int)SrcNumElts && MaxRange[Input] < 0) {
3253 RangeUse[Input] = 0; // Unused
3254 StartIdx[Input] = 0;
3255 continue;
3256 }
3257
3258 // Find a good start index that is a multiple of the mask length. Then
3259 // see if the rest of the elements are in range.
3260 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
3261 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
3262 StartIdx[Input] + MaskNumElts <= SrcNumElts)
3263 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
3264 }
3265
3266 if (RangeUse[0] == 0 && RangeUse[1] == 0) {
3267 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
3268 return;
3269 }
3270 if (RangeUse[0] >= 0 && RangeUse[1] >= 0) {
3271 // Extract appropriate subvector and generate a vector shuffle
3272 for (unsigned Input = 0; Input < 2; ++Input) {
3273 SDValue &Src = Input == 0 ? Src1 : Src2;
3274 if (RangeUse[Input] == 0)
3275 Src = DAG.getUNDEF(VT);
3276 else
3277 Src = DAG.getNode(
3278 ISD::EXTRACT_SUBVECTOR, getCurSDLoc(), VT, Src,
3279 DAG.getConstant(StartIdx[Input], TLI.getVectorIdxTy()));
3280 }
3281
3282 // Calculate new mask.
3283 SmallVector<int, 8> MappedOps;
3284 for (unsigned i = 0; i != MaskNumElts; ++i) {
3285 int Idx = Mask[i];
3286 if (Idx >= 0) {
3287 if (Idx < (int)SrcNumElts)
3288 Idx -= StartIdx[0];
3289 else
3290 Idx -= SrcNumElts + StartIdx[1] - MaskNumElts;
3291 }
3292 MappedOps.push_back(Idx);
3293 }
3294
3295 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
3296 &MappedOps[0]));
3297 return;
3298 }
3299 }
3300
3301 // We can't use either concat vectors or extract subvectors so fall back to
3302 // replacing the shuffle with extract and build vector.
3303 // to insert and build vector.
3304 EVT EltVT = VT.getVectorElementType();
3305 EVT IdxVT = TLI.getVectorIdxTy();
3306 SmallVector<SDValue,8> Ops;
3307 for (unsigned i = 0; i != MaskNumElts; ++i) {
3308 int Idx = Mask[i];
3309 SDValue Res;
3310
3311 if (Idx < 0) {
3312 Res = DAG.getUNDEF(EltVT);
3313 } else {
3314 SDValue &Src = Idx < (int)SrcNumElts ? Src1 : Src2;
3315 if (Idx >= (int)SrcNumElts) Idx -= SrcNumElts;
3316
3317 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(),
3318 EltVT, Src, DAG.getConstant(Idx, IdxVT));
3319 }
3320
3321 Ops.push_back(Res);
3322 }
3323
3324 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(), VT, Ops));
3325}
3326
3327void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) {
3328 const Value *Op0 = I.getOperand(0);
3329 const Value *Op1 = I.getOperand(1);
3330 Type *AggTy = I.getType();
3331 Type *ValTy = Op1->getType();
3332 bool IntoUndef = isa<UndefValue>(Op0);
3333 bool FromUndef = isa<UndefValue>(Op1);
3334
3335 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
3336
3337 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3338 SmallVector<EVT, 4> AggValueVTs;
3339 ComputeValueVTs(TLI, AggTy, AggValueVTs);
3340 SmallVector<EVT, 4> ValValueVTs;
3341 ComputeValueVTs(TLI, ValTy, ValValueVTs);
3342
3343 unsigned NumAggValues = AggValueVTs.size();
3344 unsigned NumValValues = ValValueVTs.size();
3345 SmallVector<SDValue, 4> Values(NumAggValues);
3346
3347 // Ignore an insertvalue that produces an empty object
3348 if (!NumAggValues) {
3349 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
3350 return;
3351 }
3352
3353 SDValue Agg = getValue(Op0);
3354 unsigned i = 0;
3355 // Copy the beginning value(s) from the original aggregate.
3356 for (; i != LinearIndex; ++i)
3357 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3358 SDValue(Agg.getNode(), Agg.getResNo() + i);
3359 // Copy values from the inserted value(s).
3360 if (NumValValues) {
3361 SDValue Val = getValue(Op1);
3362 for (; i != LinearIndex + NumValValues; ++i)
3363 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3364 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
3365 }
3366 // Copy remaining value(s) from the original aggregate.
3367 for (; i != NumAggValues; ++i)
3368 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3369 SDValue(Agg.getNode(), Agg.getResNo() + i);
3370
3371 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
3372 DAG.getVTList(AggValueVTs), Values));
3373}
3374
3375void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) {
3376 const Value *Op0 = I.getOperand(0);
3377 Type *AggTy = Op0->getType();
3378 Type *ValTy = I.getType();
3379 bool OutOfUndef = isa<UndefValue>(Op0);
3380
3381 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
3382
3383 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3384 SmallVector<EVT, 4> ValValueVTs;
3385 ComputeValueVTs(TLI, ValTy, ValValueVTs);
3386
3387 unsigned NumValValues = ValValueVTs.size();
3388
3389 // Ignore a extractvalue that produces an empty object
3390 if (!NumValValues) {
3391 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
3392 return;
3393 }
3394
3395 SmallVector<SDValue, 4> Values(NumValValues);
3396
3397 SDValue Agg = getValue(Op0);
3398 // Copy out the selected value(s).
3399 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
3400 Values[i - LinearIndex] =
3401 OutOfUndef ?
3402 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
3403 SDValue(Agg.getNode(), Agg.getResNo() + i);
3404
3405 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
3406 DAG.getVTList(ValValueVTs), Values));
3407}
3408
3409void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
3410 Value *Op0 = I.getOperand(0);
3411 // Note that the pointer operand may be a vector of pointers. Take the scalar
3412 // element which holds a pointer.
3413 Type *Ty = Op0->getType()->getScalarType();
3414 unsigned AS = Ty->getPointerAddressSpace();
3415 SDValue N = getValue(Op0);
3416
3417 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end();
3418 OI != E; ++OI) {
3419 const Value *Idx = *OI;
3420 if (StructType *StTy = dyn_cast<StructType>(Ty)) {
3421 unsigned Field = cast<Constant>(Idx)->getUniqueInteger().getZExtValue();
3422 if (Field) {
3423 // N = N + Offset
3424 uint64_t Offset = DL->getStructLayout(StTy)->getElementOffset(Field);
3425 N = DAG.getNode(ISD::ADD, getCurSDLoc(), N.getValueType(), N,
3426 DAG.getConstant(Offset, N.getValueType()));
3427 }
3428
3429 Ty = StTy->getElementType(Field);
3430 } else {
3431 Ty = cast<SequentialType>(Ty)->getElementType();
3432
3433 // If this is a constant subscript, handle it quickly.
3434 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3435 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
3436 if (CI->isZero()) continue;
3437 uint64_t Offs =
3438 DL->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
3439 SDValue OffsVal;
3440 EVT PTy = TLI.getPointerTy(AS);
3441 unsigned PtrBits = PTy.getSizeInBits();
3442 if (PtrBits < 64)
3443 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), PTy,
3444 DAG.getConstant(Offs, MVT::i64));
3445 else
3446 OffsVal = DAG.getConstant(Offs, PTy);
3447
3448 N = DAG.getNode(ISD::ADD, getCurSDLoc(), N.getValueType(), N,
3449 OffsVal);
3450 continue;
3451 }
3452
3453 // N = N + Idx * ElementSize;
3454 APInt ElementSize =
3455 APInt(TLI.getPointerSizeInBits(AS), DL->getTypeAllocSize(Ty));
3456 SDValue IdxN = getValue(Idx);
3457
3458 // If the index is smaller or larger than intptr_t, truncate or extend
3459 // it.
3460 IdxN = DAG.getSExtOrTrunc(IdxN, getCurSDLoc(), N.getValueType());
3461
3462 // If this is a multiply by a power of two, turn it into a shl
3463 // immediately. This is a very common case.
3464 if (ElementSize != 1) {
3465 if (ElementSize.isPowerOf2()) {
3466 unsigned Amt = ElementSize.logBase2();
3467 IdxN = DAG.getNode(ISD::SHL, getCurSDLoc(),
3468 N.getValueType(), IdxN,
3469 DAG.getConstant(Amt, IdxN.getValueType()));
3470 } else {
3471 SDValue Scale = DAG.getConstant(ElementSize, IdxN.getValueType());
3472 IdxN = DAG.getNode(ISD::MUL, getCurSDLoc(),
3473 N.getValueType(), IdxN, Scale);
3474 }
3475 }
3476
3477 N = DAG.getNode(ISD::ADD, getCurSDLoc(),
3478 N.getValueType(), N, IdxN);
3479 }
3480 }
3481
3482 setValue(&I, N);
3483}
3484
3485void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
3486 // If this is a fixed sized alloca in the entry block of the function,
3487 // allocate it statically on the stack.
3488 if (FuncInfo.StaticAllocaMap.count(&I))
3489 return; // getValue will auto-populate this.
3490
3491 Type *Ty = I.getAllocatedType();
3492 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3493 uint64_t TySize = TLI.getDataLayout()->getTypeAllocSize(Ty);
3494 unsigned Align =
3495 std::max((unsigned)TLI.getDataLayout()->getPrefTypeAlignment(Ty),
3496 I.getAlignment());
3497
3498 SDValue AllocSize = getValue(I.getArraySize());
3499
3500 EVT IntPtr = TLI.getPointerTy();
3501 if (AllocSize.getValueType() != IntPtr)
3502 AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurSDLoc(), IntPtr);
3503
3504 AllocSize = DAG.getNode(ISD::MUL, getCurSDLoc(), IntPtr,
3505 AllocSize,
3506 DAG.getConstant(TySize, IntPtr));
3507
3508 // Handle alignment. If the requested alignment is less than or equal to
3509 // the stack alignment, ignore it. If the size is greater than or equal to
3510 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
3511 unsigned StackAlign =
3512 DAG.getSubtarget().getFrameLowering()->getStackAlignment();
3513 if (Align <= StackAlign)
3514 Align = 0;
3515
3516 // Round the size of the allocation up to the stack alignment size
3517 // by add SA-1 to the size.
3518 AllocSize = DAG.getNode(ISD::ADD, getCurSDLoc(),
3519 AllocSize.getValueType(), AllocSize,
3520 DAG.getIntPtrConstant(StackAlign-1));
3521
3522 // Mask out the low bits for alignment purposes.
3523 AllocSize = DAG.getNode(ISD::AND, getCurSDLoc(),
3524 AllocSize.getValueType(), AllocSize,
3525 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
3526
3527 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
3528 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
3529 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurSDLoc(), VTs, Ops);
3530 setValue(&I, DSA);
3531 DAG.setRoot(DSA.getValue(1));
3532
3533 assert(FuncInfo.MF->getFrameInfo()->hasVarSizedObjects())((FuncInfo.MF->getFrameInfo()->hasVarSizedObjects()) ? static_cast
<void> (0) : __assert_fail ("FuncInfo.MF->getFrameInfo()->hasVarSizedObjects()"
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 3533, __PRETTY_FUNCTION__));
3534}
3535
3536void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
3537 if (I.isAtomic())
3538 return visitAtomicLoad(I);
3539
3540 const Value *SV = I.getOperand(0);
3541 SDValue Ptr = getValue(SV);
3542
3543 Type *Ty = I.getType();
3544
3545 bool isVolatile = I.isVolatile();
3546 bool isNonTemporal = I.getMetadata(LLVMContext::MD_nontemporal) != nullptr;
3547 bool isInvariant = I.getMetadata(LLVMContext::MD_invariant_load) != nullptr;
3548 unsigned Alignment = I.getAlignment();
3549
3550 AAMDNodes AAInfo;
3551 I.getAAMetadata(AAInfo);
3552 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3553
3554 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3555 SmallVector<EVT, 4> ValueVTs;
3556 SmallVector<uint64_t, 4> Offsets;
3557 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets);
3558 unsigned NumValues = ValueVTs.size();
3559 if (NumValues == 0)
3560 return;
3561
3562 SDValue Root;
3563 bool ConstantMemory = false;
3564 if (isVolatile || NumValues > MaxParallelChains)
3565 // Serialize volatile loads with other side effects.
3566 Root = getRoot();
3567 else if (AA->pointsToConstantMemory(
3568 AliasAnalysis::Location(SV, AA->getTypeStoreSize(Ty), AAInfo))) {
3569 // Do not serialize (non-volatile) loads of constant memory with anything.
3570 Root = DAG.getEntryNode();
3571 ConstantMemory = true;
3572 } else {
3573 // Do not serialize non-volatile loads against each other.
3574 Root = DAG.getRoot();
3575 }
3576
3577 if (isVolatile)
3578 Root = TLI.prepareVolatileOrAtomicLoad(Root, getCurSDLoc(), DAG);
3579
3580 SmallVector<SDValue, 4> Values(NumValues);
3581 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
3582 NumValues));
3583 EVT PtrVT = Ptr.getValueType();
3584 unsigned ChainI = 0;
3585 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3586 // Serializing loads here may result in excessive register pressure, and
3587 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling
3588 // could recover a bit by hoisting nodes upward in the chain by recognizing
3589 // they are side-effect free or do not alias. The optimizer should really
3590 // avoid this case by converting large object/array copies to llvm.memcpy
3591 // (MaxParallelChains should always remain as failsafe).
3592 if (ChainI == MaxParallelChains) {
3593 assert(PendingLoads.empty() && "PendingLoads must be serialized first")((PendingLoads.empty() && "PendingLoads must be serialized first"
) ? static_cast<void> (0) : __assert_fail ("PendingLoads.empty() && \"PendingLoads must be serialized first\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 3593, __PRETTY_FUNCTION__));
3594 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
3595 makeArrayRef(Chains.data(), ChainI));
3596 Root = Chain;
3597 ChainI = 0;
3598 }
3599 SDValue A = DAG.getNode(ISD::ADD, getCurSDLoc(),
3600 PtrVT, Ptr,
3601 DAG.getConstant(Offsets[i], PtrVT));
3602 SDValue L = DAG.getLoad(ValueVTs[i], getCurSDLoc(), Root,
3603 A, MachinePointerInfo(SV, Offsets[i]), isVolatile,
3604 isNonTemporal, isInvariant, Alignment, AAInfo,
3605 Ranges);
3606
3607 Values[i] = L;
3608 Chains[ChainI] = L.getValue(1);
3609 }
3610
3611 if (!ConstantMemory) {
3612 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
3613 makeArrayRef(Chains.data(), ChainI));
3614 if (isVolatile)
3615 DAG.setRoot(Chain);
3616 else
3617 PendingLoads.push_back(Chain);
3618 }
3619
3620 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
3621 DAG.getVTList(ValueVTs), Values));
3622}
3623
3624void SelectionDAGBuilder::visitStore(const StoreInst &I) {
3625 if (I.isAtomic())
3626 return visitAtomicStore(I);
3627
3628 const Value *SrcV = I.getOperand(0);
3629 const Value *PtrV = I.getOperand(1);
3630
3631 SmallVector<EVT, 4> ValueVTs;
3632 SmallVector<uint64_t, 4> Offsets;
3633 ComputeValueVTs(DAG.getTargetLoweringInfo(), SrcV->getType(),
3634 ValueVTs, &Offsets);
3635 unsigned NumValues = ValueVTs.size();
3636 if (NumValues == 0)
3637 return;
3638
3639 // Get the lowered operands. Note that we do this after
3640 // checking if NumResults is zero, because with zero results
3641 // the operands won't have values in the map.
3642 SDValue Src = getValue(SrcV);
3643 SDValue Ptr = getValue(PtrV);
3644
3645 SDValue Root = getRoot();
3646 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
3647 NumValues));
3648 EVT PtrVT = Ptr.getValueType();
3649 bool isVolatile = I.isVolatile();
3650 bool isNonTemporal = I.getMetadata(LLVMContext::MD_nontemporal) != nullptr;
3651 unsigned Alignment = I.getAlignment();
3652
3653 AAMDNodes AAInfo;
3654 I.getAAMetadata(AAInfo);
3655
3656 unsigned ChainI = 0;
3657 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3658 // See visitLoad comments.
3659 if (ChainI == MaxParallelChains) {
3660 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
3661 makeArrayRef(Chains.data(), ChainI));
3662 Root = Chain;
3663 ChainI = 0;
3664 }
3665 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(), PtrVT, Ptr,
3666 DAG.getConstant(Offsets[i], PtrVT));
3667 SDValue St = DAG.getStore(Root, getCurSDLoc(),
3668 SDValue(Src.getNode(), Src.getResNo() + i),
3669 Add, MachinePointerInfo(PtrV, Offsets[i]),
3670 isVolatile, isNonTemporal, Alignment, AAInfo);
3671 Chains[ChainI] = St;
3672 }
3673
3674 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
3675 makeArrayRef(Chains.data(), ChainI));
3676 DAG.setRoot(StoreNode);
3677}
3678
3679void SelectionDAGBuilder::visitMaskedStore(const CallInst &I) {
3680 SDLoc sdl = getCurSDLoc();
3681
3682 // llvm.masked.store.*(Src0, Ptr, alignemt, Mask)
3683 Value *PtrOperand = I.getArgOperand(1);
3684 SDValue Ptr = getValue(PtrOperand);
3685 SDValue Src0 = getValue(I.getArgOperand(0));
3686 SDValue Mask = getValue(I.getArgOperand(3));
3687 EVT VT = Src0.getValueType();
3688 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(2)))->getZExtValue();
3689 if (!Alignment)
3690 Alignment = DAG.getEVTAlignment(VT);
3691
3692 AAMDNodes AAInfo;
3693 I.getAAMetadata(AAInfo);
3694
3695 MachineMemOperand *MMO =
3696 DAG.getMachineFunction().
3697 getMachineMemOperand(MachinePointerInfo(PtrOperand),
3698 MachineMemOperand::MOStore, VT.getStoreSize(),
3699 Alignment, AAInfo);
3700 SDValue StoreNode = DAG.getMaskedStore(getRoot(), sdl, Src0, Ptr, Mask, VT,
3701 MMO, false);
3702 DAG.setRoot(StoreNode);
3703 setValue(&I, StoreNode);
3704}
3705
3706void SelectionDAGBuilder::visitMaskedLoad(const CallInst &I) {
3707 SDLoc sdl = getCurSDLoc();
3708
3709 // @llvm.masked.load.*(Ptr, alignment, Mask, Src0)
3710 Value *PtrOperand = I.getArgOperand(0);
3711 SDValue Ptr = getValue(PtrOperand);
3712 SDValue Src0 = getValue(I.getArgOperand(3));
3713 SDValue Mask = getValue(I.getArgOperand(2));
3714
3715 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3716 EVT VT = TLI.getValueType(I.getType());
3717 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(1)))->getZExtValue();
3718 if (!Alignment)
3719 Alignment = DAG.getEVTAlignment(VT);
3720
3721 AAMDNodes AAInfo;
3722 I.getAAMetadata(AAInfo);
3723 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3724
3725 SDValue InChain = DAG.getRoot();
3726 if (AA->pointsToConstantMemory(
3727 AliasAnalysis::Location(PtrOperand,
3728 AA->getTypeStoreSize(I.getType()),
3729 AAInfo))) {
3730 // Do not serialize (non-volatile) loads of constant memory with anything.
3731 InChain = DAG.getEntryNode();
3732 }
3733
3734 MachineMemOperand *MMO =
3735 DAG.getMachineFunction().
3736 getMachineMemOperand(MachinePointerInfo(PtrOperand),
3737 MachineMemOperand::MOLoad, VT.getStoreSize(),
3738 Alignment, AAInfo, Ranges);
3739
3740 SDValue Load = DAG.getMaskedLoad(VT, sdl, InChain, Ptr, Mask, Src0, VT, MMO,
3741 ISD::NON_EXTLOAD);
3742 SDValue OutChain = Load.getValue(1);
3743 DAG.setRoot(OutChain);
3744 setValue(&I, Load);
3745}
3746
3747void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) {
3748 SDLoc dl = getCurSDLoc();
3749 AtomicOrdering SuccessOrder = I.getSuccessOrdering();
3750 AtomicOrdering FailureOrder = I.getFailureOrdering();
3751 SynchronizationScope Scope = I.getSynchScope();
3752
3753 SDValue InChain = getRoot();
3754
3755 MVT MemVT = getValue(I.getCompareOperand()).getSimpleValueType();
3756 SDVTList VTs = DAG.getVTList(MemVT, MVT::i1, MVT::Other);
3757 SDValue L = DAG.getAtomicCmpSwap(
3758 ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl, MemVT, VTs, InChain,
3759 getValue(I.getPointerOperand()), getValue(I.getCompareOperand()),
3760 getValue(I.getNewValOperand()), MachinePointerInfo(I.getPointerOperand()),
3761 /*Alignment=*/ 0, SuccessOrder, FailureOrder, Scope);
3762
3763 SDValue OutChain = L.getValue(2);
3764
3765 setValue(&I, L);
3766 DAG.setRoot(OutChain);
3767}
3768
3769void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) {
3770 SDLoc dl = getCurSDLoc();
3771 ISD::NodeType NT;
3772 switch (I.getOperation()) {
3773 default: llvm_unreachable("Unknown atomicrmw operation")::llvm::llvm_unreachable_internal("Unknown atomicrmw operation"
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 3773);
3774 case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break;
3775 case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break;
3776 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break;
3777 case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break;
3778 case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break;
3779 case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break;
3780 case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break;
3781 case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break;
3782 case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break;
3783 case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break;
3784 case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break;
3785 }
3786 AtomicOrdering Order = I.getOrdering();
3787 SynchronizationScope Scope = I.getSynchScope();
3788
3789 SDValue InChain = getRoot();
3790
3791 SDValue L =
3792 DAG.getAtomic(NT, dl,
3793 getValue(I.getValOperand()).getSimpleValueType(),
3794 InChain,
3795 getValue(I.getPointerOperand()),
3796 getValue(I.getValOperand()),
3797 I.getPointerOperand(),
3798 /* Alignment=*/ 0, Order, Scope);
3799
3800 SDValue OutChain = L.getValue(1);
3801
3802 setValue(&I, L);
3803 DAG.setRoot(OutChain);
3804}
3805
3806void SelectionDAGBuilder::visitFence(const FenceInst &I) {
3807 SDLoc dl = getCurSDLoc();
3808 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3809 SDValue Ops[3];
3810 Ops[0] = getRoot();
3811 Ops[1] = DAG.getConstant(I.getOrdering(), TLI.getPointerTy());
3812 Ops[2] = DAG.getConstant(I.getSynchScope(), TLI.getPointerTy());
3813 DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops));
3814}
3815
3816void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) {
3817 SDLoc dl = getCurSDLoc();
3818 AtomicOrdering Order = I.getOrdering();
3819 SynchronizationScope Scope = I.getSynchScope();
3820
3821 SDValue InChain = getRoot();
3822
3823 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3824 EVT VT = TLI.getValueType(I.getType());
3825
3826 if (I.getAlignment() < VT.getSizeInBits() / 8)
3827 report_fatal_error("Cannot generate unaligned atomic load");
3828
3829 MachineMemOperand *MMO =
3830 DAG.getMachineFunction().
3831 getMachineMemOperand(MachinePointerInfo(I.getPointerOperand()),
3832 MachineMemOperand::MOVolatile |
3833 MachineMemOperand::MOLoad,
3834 VT.getStoreSize(),
3835 I.getAlignment() ? I.getAlignment() :
3836 DAG.getEVTAlignment(VT));
3837
3838 InChain = TLI.prepareVolatileOrAtomicLoad(InChain, dl, DAG);
3839 SDValue L =
3840 DAG.getAtomic(ISD::ATOMIC_LOAD, dl, VT, VT, InChain,
3841 getValue(I.getPointerOperand()), MMO,
3842 Order, Scope);
3843
3844 SDValue OutChain = L.getValue(1);
3845
3846 setValue(&I, L);
3847 DAG.setRoot(OutChain);
3848}
3849
3850void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) {
3851 SDLoc dl = getCurSDLoc();
3852
3853 AtomicOrdering Order = I.getOrdering();
3854 SynchronizationScope Scope = I.getSynchScope();
3855
3856 SDValue InChain = getRoot();
3857
3858 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3859 EVT VT = TLI.getValueType(I.getValueOperand()->getType());
3860
3861 if (I.getAlignment() < VT.getSizeInBits() / 8)
3862 report_fatal_error("Cannot generate unaligned atomic store");
3863
3864 SDValue OutChain =
3865 DAG.getAtomic(ISD::ATOMIC_STORE, dl, VT,
3866 InChain,
3867 getValue(I.getPointerOperand()),
3868 getValue(I.getValueOperand()),
3869 I.getPointerOperand(), I.getAlignment(),
3870 Order, Scope);
3871
3872 DAG.setRoot(OutChain);
3873}
3874
3875/// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
3876/// node.
3877void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
3878 unsigned Intrinsic) {
3879 bool HasChain = !I.doesNotAccessMemory();
3880 bool OnlyLoad = HasChain && I.onlyReadsMemory();
3881
3882 // Build the operand list.
3883 SmallVector<SDValue, 8> Ops;
3884 if (HasChain) { // If this intrinsic has side-effects, chainify it.
3885 if (OnlyLoad) {
3886 // We don't need to serialize loads against other loads.
3887 Ops.push_back(DAG.getRoot());
3888 } else {
3889 Ops.push_back(getRoot());
3890 }
3891 }
3892
3893 // Info is set by getTgtMemInstrinsic
3894 TargetLowering::IntrinsicInfo Info;
3895 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3896 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
3897
3898 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
3899 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID ||
3900 Info.opc == ISD::INTRINSIC_W_CHAIN)
3901 Ops.push_back(DAG.getTargetConstant(Intrinsic, TLI.getPointerTy()));
3902
3903 // Add all operands of the call to the operand list.
3904 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
3905 SDValue Op = getValue(I.getArgOperand(i));
3906 Ops.push_back(Op);
3907 }
3908
3909 SmallVector<EVT, 4> ValueVTs;
3910 ComputeValueVTs(TLI, I.getType(), ValueVTs);
3911
3912 if (HasChain)
3913 ValueVTs.push_back(MVT::Other);
3914
3915 SDVTList VTs = DAG.getVTList(ValueVTs);
3916
3917 // Create the node.
3918 SDValue Result;
3919 if (IsTgtIntrinsic) {
3920 // This is target intrinsic that touches memory
3921 Result = DAG.getMemIntrinsicNode(Info.opc, getCurSDLoc(),
3922 VTs, Ops, Info.memVT,
3923 MachinePointerInfo(Info.ptrVal, Info.offset),
3924 Info.align, Info.vol,
3925 Info.readMem, Info.writeMem, Info.size);
3926 } else if (!HasChain) {
3927 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurSDLoc(), VTs, Ops);
3928 } else if (!I.getType()->isVoidTy()) {
3929 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurSDLoc(), VTs, Ops);
3930 } else {
3931 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurSDLoc(), VTs, Ops);
3932 }
3933
3934 if (HasChain) {
3935 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
3936 if (OnlyLoad)
3937 PendingLoads.push_back(Chain);
3938 else
3939 DAG.setRoot(Chain);
3940 }
3941
3942 if (!I.getType()->isVoidTy()) {
3943 if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3944 EVT VT = TLI.getValueType(PTy);
3945 Result = DAG.getNode(ISD::BITCAST, getCurSDLoc(), VT, Result);
3946 }
3947
3948 setValue(&I, Result);
3949 }
3950}
3951
3952/// GetSignificand - Get the significand and build it into a floating-point
3953/// number with exponent of 1:
3954///
3955/// Op = (Op & 0x007fffff) | 0x3f800000;
3956///
3957/// where Op is the hexadecimal representation of floating point value.
3958static SDValue
3959GetSignificand(SelectionDAG &DAG, SDValue Op, SDLoc dl) {
3960 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3961 DAG.getConstant(0x007fffff, MVT::i32));
3962 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3963 DAG.getConstant(0x3f800000, MVT::i32));
3964 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2);
3965}
3966
3967/// GetExponent - Get the exponent:
3968///
3969/// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3970///
3971/// where Op is the hexadecimal representation of floating point value.
3972static SDValue
3973GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3974 SDLoc dl) {
3975 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3976 DAG.getConstant(0x7f800000, MVT::i32));
3977 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0,
3978 DAG.getConstant(23, TLI.getPointerTy()));
3979 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3980 DAG.getConstant(127, MVT::i32));
3981 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3982}
3983
3984/// getF32Constant - Get 32-bit floating point constant.
3985static SDValue
3986getF32Constant(SelectionDAG &DAG, unsigned Flt) {
3987 return DAG.getConstantFP(APFloat(APFloat::IEEEsingle, APInt(32, Flt)),
3988 MVT::f32);
3989}
3990
3991/// expandExp - Lower an exp intrinsic. Handles the special sequences for
3992/// limited-precision mode.
3993static SDValue expandExp(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3994 const TargetLowering &TLI) {
3995 if (Op.getValueType() == MVT::f32 &&
3996 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3997
3998 // Put the exponent in the right bit position for later addition to the
3999 // final result:
4000 //
4001 // #define LOG2OFe 1.4426950f
4002 // IntegerPartOfX = ((int32_t)(X * LOG2OFe));
4003 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
4004 getF32Constant(DAG, 0x3fb8aa3b));
4005 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
4006
4007 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX;
4008 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
4009 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
4010
4011 // IntegerPartOfX <<= 23;
4012 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
4013 DAG.getConstant(23, TLI.getPointerTy()));
4014
4015 SDValue TwoToFracPartOfX;
4016 if (LimitFloatPrecision <= 6) {
4017 // For floating-point precision of 6:
4018 //
4019 // TwoToFractionalPartOfX =
4020 // 0.997535578f +
4021 // (0.735607626f + 0.252464424f * x) * x;
4022 //
4023 // error 0.0144103317, which is 6 bits
4024 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4025 getF32Constant(DAG, 0x3e814304));
4026 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4027 getF32Constant(DAG, 0x3f3c50c8));
4028 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4029 TwoToFracPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4030 getF32Constant(DAG, 0x3f7f5e7e));
4031 } else if (LimitFloatPrecision <= 12) {
4032 // For floating-point precision of 12:
4033 //
4034 // TwoToFractionalPartOfX =
4035 // 0.999892986f +
4036 // (0.696457318f +
4037 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
4038 //
4039 // 0.000107046256 error, which is 13 to 14 bits
4040 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4041 getF32Constant(DAG, 0x3da235e3));
4042 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4043 getF32Constant(DAG, 0x3e65b8f3));
4044 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4045 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4046 getF32Constant(DAG, 0x3f324b07));
4047 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4048 TwoToFracPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4049 getF32Constant(DAG, 0x3f7ff8fd));
4050 } else { // LimitFloatPrecision <= 18
4051 // For floating-point precision of 18:
4052 //
4053 // TwoToFractionalPartOfX =
4054 // 0.999999982f +
4055 // (0.693148872f +
4056 // (0.240227044f +
4057 // (0.554906021e-1f +
4058 // (0.961591928e-2f +
4059 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
4060 //
4061 // error 2.47208000*10^(-7), which is better than 18 bits
4062 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4063 getF32Constant(DAG, 0x3924b03e));
4064 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4065 getF32Constant(DAG, 0x3ab24b87));
4066 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4067 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4068 getF32Constant(DAG, 0x3c1d8c17));
4069 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4070 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4071 getF32Constant(DAG, 0x3d634a1d));
4072 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4073 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4074 getF32Constant(DAG, 0x3e75fe14));
4075 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4076 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
4077 getF32Constant(DAG, 0x3f317234));
4078 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
4079 TwoToFracPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
4080 getF32Constant(DAG, 0x3f800000));
4081 }
4082
4083 // Add the exponent into the result in integer domain.
4084 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, TwoToFracPartOfX);
4085 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
4086 DAG.getNode(ISD::ADD, dl, MVT::i32,
4087 t13, IntegerPartOfX));
4088 }
4089
4090 // No special expansion.
4091 return DAG.getNode(ISD::FEXP, dl, Op.getValueType(), Op);
4092}
4093
4094/// expandLog - Lower a log intrinsic. Handles the special sequences for
4095/// limited-precision mode.
4096static SDValue expandLog(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4097 const TargetLowering &TLI) {
4098 if (Op.getValueType() == MVT::f32 &&
4099 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4100 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
4101
4102 // Scale the exponent by log(2) [0.69314718f].
4103 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
4104 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
4105 getF32Constant(DAG, 0x3f317218));
4106
4107 // Get the significand and build it into a floating-point number with
4108 // exponent of 1.
4109 SDValue X = GetSignificand(DAG, Op1, dl);
4110
4111 SDValue LogOfMantissa;
4112 if (LimitFloatPrecision <= 6) {
4113 // For floating-point precision of 6:
4114 //
4115 // LogofMantissa =
4116 // -1.1609546f +
4117 // (1.4034025f - 0.23903021f * x) * x;
4118 //
4119 // error 0.0034276066, which is better than 8 bits
4120 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4121 getF32Constant(DAG, 0xbe74c456));
4122 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4123 getF32Constant(DAG, 0x3fb3a2b1));
4124 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4125 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4126 getF32Constant(DAG, 0x3f949a29));
4127 } else if (LimitFloatPrecision <= 12) {
4128 // For floating-point precision of 12:
4129 //
4130 // LogOfMantissa =
4131 // -1.7417939f +
4132 // (2.8212026f +
4133 // (-1.4699568f +
4134 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
4135 //
4136 // error 0.000061011436, which is 14 bits
4137 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4138 getF32Constant(DAG, 0xbd67b6d6));
4139 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4140 getF32Constant(DAG, 0x3ee4f4b8));
4141 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4142 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4143 getF32Constant(DAG, 0x3fbc278b));
4144 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4145 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4146 getF32Constant(DAG, 0x40348e95));
4147 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4148 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4149 getF32Constant(DAG, 0x3fdef31a));
4150 } else { // LimitFloatPrecision <= 18
4151 // For floating-point precision of 18:
4152 //
4153 // LogOfMantissa =
4154 // -2.1072184f +
4155 // (4.2372794f +
4156 // (-3.7029485f +
4157 // (2.2781945f +
4158 // (-0.87823314f +
4159 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
4160 //
4161 // error 0.0000023660568, which is better than 18 bits
4162 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4163 getF32Constant(DAG, 0xbc91e5ac));
4164 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4165 getF32Constant(DAG, 0x3e4350aa));
4166 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4167 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4168 getF32Constant(DAG, 0x3f60d3e3));
4169 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4170 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4171 getF32Constant(DAG, 0x4011cdf0));
4172 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4173 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4174 getF32Constant(DAG, 0x406cfd1c));
4175 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4176 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4177 getF32Constant(DAG, 0x408797cb));
4178 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4179 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
4180 getF32Constant(DAG, 0x4006dcab));
4181 }
4182
4183 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, LogOfMantissa);
4184 }
4185
4186 // No special expansion.
4187 return DAG.getNode(ISD::FLOG, dl, Op.getValueType(), Op);
4188}
4189
4190/// expandLog2 - Lower a log2 intrinsic. Handles the special sequences for
4191/// limited-precision mode.
4192static SDValue expandLog2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4193 const TargetLowering &TLI) {
4194 if (Op.getValueType() == MVT::f32 &&
4195 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4196 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
4197
4198 // Get the exponent.
4199 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
4200
4201 // Get the significand and build it into a floating-point number with
4202 // exponent of 1.
4203 SDValue X = GetSignificand(DAG, Op1, dl);
4204
4205 // Different possible minimax approximations of significand in
4206 // floating-point for various degrees of accuracy over [1,2].
4207 SDValue Log2ofMantissa;
4208 if (LimitFloatPrecision <= 6) {
4209 // For floating-point precision of 6:
4210 //
4211 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
4212 //
4213 // error 0.0049451742, which is more than 7 bits
4214 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4215 getF32Constant(DAG, 0xbeb08fe0));
4216 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4217 getF32Constant(DAG, 0x40019463));
4218 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4219 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4220 getF32Constant(DAG, 0x3fd6633d));
4221 } else if (LimitFloatPrecision <= 12) {
4222 // For floating-point precision of 12:
4223 //
4224 // Log2ofMantissa =
4225 // -2.51285454f +
4226 // (4.07009056f +
4227 // (-2.12067489f +
4228 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
4229 //
4230 // error 0.0000876136000, which is better than 13 bits
4231 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4232 getF32Constant(DAG, 0xbda7262e));
4233 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4234 getF32Constant(DAG, 0x3f25280b));
4235 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4236 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4237 getF32Constant(DAG, 0x4007b923));
4238 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4239 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4240 getF32Constant(DAG, 0x40823e2f));
4241 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4242 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4243 getF32Constant(DAG, 0x4020d29c));
4244 } else { // LimitFloatPrecision <= 18
4245 // For floating-point precision of 18:
4246 //
4247 // Log2ofMantissa =
4248 // -3.0400495f +
4249 // (6.1129976f +
4250 // (-5.3420409f +
4251 // (3.2865683f +
4252 // (-1.2669343f +
4253 // (0.27515199f -
4254 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
4255 //
4256 // error 0.0000018516, which is better than 18 bits
4257 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4258 getF32Constant(DAG, 0xbcd2769e));
4259 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4260 getF32Constant(DAG, 0x3e8ce0b9));
4261 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4262 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4263 getF32Constant(DAG, 0x3fa22ae7));
4264 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4265 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4266 getF32Constant(DAG, 0x40525723));
4267 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4268 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4269 getF32Constant(DAG, 0x40aaf200));
4270 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4271 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4272 getF32Constant(DAG, 0x40c39dad));
4273 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4274 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
4275 getF32Constant(DAG, 0x4042902c));
4276 }
4277
4278 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log2ofMantissa);
4279 }
4280
4281 // No special expansion.
4282 return DAG.getNode(ISD::FLOG2, dl, Op.getValueType(), Op);
4283}
4284
4285/// expandLog10 - Lower a log10 intrinsic. Handles the special sequences for
4286/// limited-precision mode.
4287static SDValue expandLog10(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4288 const TargetLowering &TLI) {
4289 if (Op.getValueType() == MVT::f32 &&
4290 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4291 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
4292
4293 // Scale the exponent by log10(2) [0.30102999f].
4294 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
4295 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
4296 getF32Constant(DAG, 0x3e9a209a));
4297
4298 // Get the significand and build it into a floating-point number with
4299 // exponent of 1.
4300 SDValue X = GetSignificand(DAG, Op1, dl);
4301
4302 SDValue Log10ofMantissa;
4303 if (LimitFloatPrecision <= 6) {
4304 // For floating-point precision of 6:
4305 //
4306 // Log10ofMantissa =
4307 // -0.50419619f +
4308 // (0.60948995f - 0.10380950f * x) * x;
4309 //
4310 // error 0.0014886165, which is 6 bits
4311 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4312 getF32Constant(DAG, 0xbdd49a13));
4313 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4314 getF32Constant(DAG, 0x3f1c0789));
4315 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4316 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4317 getF32Constant(DAG, 0x3f011300));
4318 } else if (LimitFloatPrecision <= 12) {
4319 // For floating-point precision of 12:
4320 //
4321 // Log10ofMantissa =
4322 // -0.64831180f +
4323 // (0.91751397f +
4324 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
4325 //
4326 // error 0.00019228036, which is better than 12 bits
4327 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4328 getF32Constant(DAG, 0x3d431f31));
4329 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4330 getF32Constant(DAG, 0x3ea21fb2));
4331 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4332 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4333 getF32Constant(DAG, 0x3f6ae232));
4334 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4335 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4336 getF32Constant(DAG, 0x3f25f7c3));
4337 } else { // LimitFloatPrecision <= 18
4338 // For floating-point precision of 18:
4339 //
4340 // Log10ofMantissa =
4341 // -0.84299375f +
4342 // (1.5327582f +
4343 // (-1.0688956f +
4344 // (0.49102474f +
4345 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
4346 //
4347 // error 0.0000037995730, which is better than 18 bits
4348 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4349 getF32Constant(DAG, 0x3c5d51ce));
4350 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4351 getF32Constant(DAG, 0x3e00685a));
4352 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4353 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4354 getF32Constant(DAG, 0x3efb6798));
4355 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4356 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4357 getF32Constant(DAG, 0x3f88d192));
4358 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4359 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4360 getF32Constant(DAG, 0x3fc4316c));
4361 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4362 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
4363 getF32Constant(DAG, 0x3f57ce70));
4364 }
4365
4366 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log10ofMantissa);
4367 }
4368
4369 // No special expansion.
4370 return DAG.getNode(ISD::FLOG10, dl, Op.getValueType(), Op);
4371}
4372
4373/// expandExp2 - Lower an exp2 intrinsic. Handles the special sequences for
4374/// limited-precision mode.
4375static SDValue expandExp2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4376 const TargetLowering &TLI) {
4377 if (Op.getValueType() == MVT::f32 &&
4378 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4379 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op);
4380
4381 // FractionalPartOfX = x - (float)IntegerPartOfX;
4382 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
4383 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1);
4384
4385 // IntegerPartOfX <<= 23;
4386 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
4387 DAG.getConstant(23, TLI.getPointerTy()));
4388
4389 SDValue TwoToFractionalPartOfX;
4390 if (LimitFloatPrecision <= 6) {
4391 // For floating-point precision of 6:
4392 //
4393 // TwoToFractionalPartOfX =
4394 // 0.997535578f +
4395 // (0.735607626f + 0.252464424f * x) * x;
4396 //
4397 // error 0.0144103317, which is 6 bits
4398 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4399 getF32Constant(DAG, 0x3e814304));
4400 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4401 getF32Constant(DAG, 0x3f3c50c8));
4402 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4403 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4404 getF32Constant(DAG, 0x3f7f5e7e));
4405 } else if (LimitFloatPrecision <= 12) {
4406 // For floating-point precision of 12:
4407 //
4408 // TwoToFractionalPartOfX =
4409 // 0.999892986f +
4410 // (0.696457318f +
4411 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
4412 //
4413 // error 0.000107046256, which is 13 to 14 bits
4414 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4415 getF32Constant(DAG, 0x3da235e3));
4416 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4417 getF32Constant(DAG, 0x3e65b8f3));
4418 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4419 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4420 getF32Constant(DAG, 0x3f324b07));
4421 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4422 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4423 getF32Constant(DAG, 0x3f7ff8fd));
4424 } else { // LimitFloatPrecision <= 18
4425 // For floating-point precision of 18:
4426 //
4427 // TwoToFractionalPartOfX =
4428 // 0.999999982f +
4429 // (0.693148872f +
4430 // (0.240227044f +
4431 // (0.554906021e-1f +
4432 // (0.961591928e-2f +
4433 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
4434 // error 2.47208000*10^(-7), which is better than 18 bits
4435 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4436 getF32Constant(DAG, 0x3924b03e));
4437 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4438 getF32Constant(DAG, 0x3ab24b87));
4439 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4440 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4441 getF32Constant(DAG, 0x3c1d8c17));
4442 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4443 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4444 getF32Constant(DAG, 0x3d634a1d));
4445 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4446 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4447 getF32Constant(DAG, 0x3e75fe14));
4448 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4449 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
4450 getF32Constant(DAG, 0x3f317234));
4451 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
4452 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
4453 getF32Constant(DAG, 0x3f800000));
4454 }
4455
4456 // Add the exponent into the result in integer domain.
4457 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32,
4458 TwoToFractionalPartOfX);
4459 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
4460 DAG.getNode(ISD::ADD, dl, MVT::i32,
4461 t13, IntegerPartOfX));
4462 }
4463
4464 // No special expansion.
4465 return DAG.getNode(ISD::FEXP2, dl, Op.getValueType(), Op);
4466}
4467
4468/// visitPow - Lower a pow intrinsic. Handles the special sequences for
4469/// limited-precision mode with x == 10.0f.
4470static SDValue expandPow(SDLoc dl, SDValue LHS, SDValue RHS,
4471 SelectionDAG &DAG, const TargetLowering &TLI) {
4472 bool IsExp10 = false;
4473 if (LHS.getValueType() == MVT::f32 && RHS.getValueType() == MVT::f32 &&
4474 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4475 if (ConstantFPSDNode *LHSC = dyn_cast<ConstantFPSDNode>(LHS)) {
4476 APFloat Ten(10.0f);
4477 IsExp10 = LHSC->isExactlyValue(Ten);
4478 }
4479 }
4480
4481 if (IsExp10) {
4482 // Put the exponent in the right bit position for later addition to the
4483 // final result:
4484 //
4485 // #define LOG2OF10 3.3219281f
4486 // IntegerPartOfX = (int32_t)(x * LOG2OF10);
4487 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, RHS,
4488 getF32Constant(DAG, 0x40549a78));
4489 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
4490
4491 // FractionalPartOfX = x - (float)IntegerPartOfX;
4492 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
4493 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
4494
4495 // IntegerPartOfX <<= 23;
4496 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
4497 DAG.getConstant(23, TLI.getPointerTy()));
4498
4499 SDValue TwoToFractionalPartOfX;
4500 if (LimitFloatPrecision <= 6) {
4501 // For floating-point precision of 6:
4502 //
4503 // twoToFractionalPartOfX =
4504 // 0.997535578f +
4505 // (0.735607626f + 0.252464424f * x) * x;
4506 //
4507 // error 0.0144103317, which is 6 bits
4508 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4509 getF32Constant(DAG, 0x3e814304));
4510 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4511 getF32Constant(DAG, 0x3f3c50c8));
4512 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4513 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4514 getF32Constant(DAG, 0x3f7f5e7e));
4515 } else if (LimitFloatPrecision <= 12) {
4516 // For floating-point precision of 12:
4517 //
4518 // TwoToFractionalPartOfX =
4519 // 0.999892986f +
4520 // (0.696457318f +
4521 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
4522 //
4523 // error 0.000107046256, which is 13 to 14 bits
4524 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4525 getF32Constant(DAG, 0x3da235e3));
4526 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4527 getF32Constant(DAG, 0x3e65b8f3));
4528 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4529 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4530 getF32Constant(DAG, 0x3f324b07));
4531 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4532 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4533 getF32Constant(DAG, 0x3f7ff8fd));
4534 } else { // LimitFloatPrecision <= 18
4535 // For floating-point precision of 18:
4536 //
4537 // TwoToFractionalPartOfX =
4538 // 0.999999982f +
4539 // (0.693148872f +
4540 // (0.240227044f +
4541 // (0.554906021e-1f +
4542 // (0.961591928e-2f +
4543 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
4544 // error 2.47208000*10^(-7), which is better than 18 bits
4545 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4546 getF32Constant(DAG, 0x3924b03e));
4547 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4548 getF32Constant(DAG, 0x3ab24b87));
4549 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4550 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4551 getF32Constant(DAG, 0x3c1d8c17));
4552 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4553 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4554 getF32Constant(DAG, 0x3d634a1d));
4555 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4556 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4557 getF32Constant(DAG, 0x3e75fe14));
4558 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4559 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
4560 getF32Constant(DAG, 0x3f317234));
4561 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
4562 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
4563 getF32Constant(DAG, 0x3f800000));
4564 }
4565
4566 SDValue t13 = DAG.getNode(ISD::BITCAST, dl,MVT::i32,TwoToFractionalPartOfX);
4567 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
4568 DAG.getNode(ISD::ADD, dl, MVT::i32,
4569 t13, IntegerPartOfX));
4570 }
4571
4572 // No special expansion.
4573 return DAG.getNode(ISD::FPOW, dl, LHS.getValueType(), LHS, RHS);
4574}
4575
4576
4577/// ExpandPowI - Expand a llvm.powi intrinsic.
4578static SDValue ExpandPowI(SDLoc DL, SDValue LHS, SDValue RHS,
4579 SelectionDAG &DAG) {
4580 // If RHS is a constant, we can expand this out to a multiplication tree,
4581 // otherwise we end up lowering to a call to __powidf2 (for example). When
4582 // optimizing for size, we only want to do this if the expansion would produce
4583 // a small number of multiplies, otherwise we do the full expansion.
4584 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
4585 // Get the exponent as a positive value.
4586 unsigned Val = RHSC->getSExtValue();
4587 if ((int)Val < 0) Val = -Val;
4588
4589 // powi(x, 0) -> 1.0
4590 if (Val == 0)
4591 return DAG.getConstantFP(1.0, LHS.getValueType());
4592
4593 const Function *F = DAG.getMachineFunction().getFunction();
4594 if (!F->hasFnAttribute(Attribute::OptimizeForSize) ||
4595 // If optimizing for size, don't insert too many multiplies. This
4596 // inserts up to 5 multiplies.
4597 countPopulation(Val) + Log2_32(Val) < 7) {
4598 // We use the simple binary decomposition method to generate the multiply
4599 // sequence. There are more optimal ways to do this (for example,
4600 // powi(x,15) generates one more multiply than it should), but this has
4601 // the benefit of being both really simple and much better than a libcall.
4602 SDValue Res; // Logically starts equal to 1.0
4603 SDValue CurSquare = LHS;
4604 while (Val) {
4605 if (Val & 1) {
4606 if (Res.getNode())
4607 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare);
4608 else
4609 Res = CurSquare; // 1.0*CurSquare.
4610 }
4611
4612 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(),
4613 CurSquare, CurSquare);
4614 Val >>= 1;
4615 }
4616
4617 // If the original was negative, invert the result, producing 1/(x*x*x).
4618 if (RHSC->getSExtValue() < 0)
4619 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(),
4620 DAG.getConstantFP(1.0, LHS.getValueType()), Res);
4621 return Res;
4622 }
4623 }
4624
4625 // Otherwise, expand to a libcall.
4626 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS);
4627}
4628
4629// getTruncatedArgReg - Find underlying register used for an truncated
4630// argument.
4631static unsigned getTruncatedArgReg(const SDValue &N) {
4632 if (N.getOpcode() != ISD::TRUNCATE)
4633 return 0;
4634
4635 const SDValue &Ext = N.getOperand(0);
4636 if (Ext.getOpcode() == ISD::AssertZext ||
4637 Ext.getOpcode() == ISD::AssertSext) {
4638 const SDValue &CFR = Ext.getOperand(0);
4639 if (CFR.getOpcode() == ISD::CopyFromReg)
4640 return cast<RegisterSDNode>(CFR.getOperand(1))->getReg();
4641 if (CFR.getOpcode() == ISD::TRUNCATE)
4642 return getTruncatedArgReg(CFR);
4643 }
4644 return 0;
4645}
4646
4647/// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function
4648/// argument, create the corresponding DBG_VALUE machine instruction for it now.
4649/// At the end of instruction selection, they will be inserted to the entry BB.
4650bool SelectionDAGBuilder::EmitFuncArgumentDbgValue(const Value *V,
4651 MDNode *Variable,
4652 MDNode *Expr, int64_t Offset,
4653 bool IsIndirect,
4654 const SDValue &N) {
4655 const Argument *Arg = dyn_cast<Argument>(V);
4656 if (!Arg)
4657 return false;
4658
4659 MachineFunction &MF = DAG.getMachineFunction();
4660 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
4661
4662 // Ignore inlined function arguments here.
4663 DIVariable DV(Variable);
4664 if (DV.isInlinedFnArgument(MF.getFunction()))
4665 return false;
4666
4667 Optional<MachineOperand> Op;
4668 // Some arguments' frame index is recorded during argument lowering.
4669 if (int FI = FuncInfo.getArgumentFrameIndex(Arg))
4670 Op = MachineOperand::CreateFI(FI);
4671
4672 if (!Op && N.getNode()) {
4673 unsigned Reg;
4674 if (N.getOpcode() == ISD::CopyFromReg)
4675 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg();
4676 else
4677 Reg = getTruncatedArgReg(N);
4678 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) {
4679 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4680 unsigned PR = RegInfo.getLiveInPhysReg(Reg);
4681 if (PR)
4682 Reg = PR;
4683 }
4684 if (Reg)
4685 Op = MachineOperand::CreateReg(Reg, false);
4686 }
4687
4688 if (!Op) {
4689 // Check if ValueMap has reg number.
4690 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
4691 if (VMI != FuncInfo.ValueMap.end())
4692 Op = MachineOperand::CreateReg(VMI->second, false);
4693 }
4694
4695 if (!Op && N.getNode())
4696 // Check if frame index is available.
4697 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode()))
4698 if (FrameIndexSDNode *FINode =
4699 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
4700 Op = MachineOperand::CreateFI(FINode->getIndex());
4701
4702 if (!Op)
4703 return false;
4704
4705 if (Op->isReg())
4706 FuncInfo.ArgDbgValues.push_back(
4707 BuildMI(MF, getCurDebugLoc(), TII->get(TargetOpcode::DBG_VALUE),
4708 IsIndirect, Op->getReg(), Offset, Variable, Expr));
4709 else
4710 FuncInfo.ArgDbgValues.push_back(
4711 BuildMI(MF, getCurDebugLoc(), TII->get(TargetOpcode::DBG_VALUE))
4712 .addOperand(*Op)
4713 .addImm(Offset)
4714 .addMetadata(Variable)
4715 .addMetadata(Expr));
4716
4717 return true;
4718}
4719
4720// VisualStudio defines setjmp as _setjmp
4721#if defined(_MSC_VER) && defined(setjmp) && \
4722 !defined(setjmp_undefined_for_msvc)
4723# pragma push_macro("setjmp")
4724# undef setjmp
4725# define setjmp_undefined_for_msvc
4726#endif
4727
4728/// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
4729/// we want to emit this as a call to a named external function, return the name
4730/// otherwise lower it and return null.
4731const char *
4732SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
4733 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4734 SDLoc sdl = getCurSDLoc();
4735 DebugLoc dl = getCurDebugLoc();
4736 SDValue Res;
4737
4738 switch (Intrinsic) {
4739 default:
4740 // By default, turn this into a target intrinsic node.
4741 visitTargetIntrinsic(I, Intrinsic);
4742 return nullptr;
4743 case Intrinsic::vastart: visitVAStart(I); return nullptr;
4744 case Intrinsic::vaend: visitVAEnd(I); return nullptr;
4745 case Intrinsic::vacopy: visitVACopy(I); return nullptr;
4746 case Intrinsic::returnaddress:
4747 setValue(&I, DAG.getNode(ISD::RETURNADDR, sdl, TLI.getPointerTy(),
4748 getValue(I.getArgOperand(0))));
4749 return nullptr;
4750 case Intrinsic::frameaddress:
4751 setValue(&I, DAG.getNode(ISD::FRAMEADDR, sdl, TLI.getPointerTy(),
4752 getValue(I.getArgOperand(0))));
4753 return nullptr;
4754 case Intrinsic::read_register: {
4755 Value *Reg = I.getArgOperand(0);
4756 SDValue RegName =
4757 DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
4758 EVT VT = TLI.getValueType(I.getType());
4759 setValue(&I, DAG.getNode(ISD::READ_REGISTER, sdl, VT, RegName));
4760 return nullptr;
4761 }
4762 case Intrinsic::write_register: {
4763 Value *Reg = I.getArgOperand(0);
4764 Value *RegValue = I.getArgOperand(1);
4765 SDValue Chain = getValue(RegValue).getOperand(0);
4766 SDValue RegName =
4767 DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
4768 DAG.setRoot(DAG.getNode(ISD::WRITE_REGISTER, sdl, MVT::Other, Chain,
4769 RegName, getValue(RegValue)));
4770 return nullptr;
4771 }
4772 case Intrinsic::setjmp:
4773 return &"_setjmp"[!TLI.usesUnderscoreSetJmp()];
4774 case Intrinsic::longjmp:
4775 return &"_longjmp"[!TLI.usesUnderscoreLongJmp()];
4776 case Intrinsic::memcpy: {
4777 // FIXME: this definition of "user defined address space" is x86-specific
4778 // Assert for address < 256 since we support only user defined address
4779 // spaces.
4780 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()((cast<PointerType>(I.getArgOperand(0)->getType())->
getAddressSpace() < 256 && cast<PointerType>
(I.getArgOperand(1)->getType())->getAddressSpace() <
256 && "Unknown address space") ? static_cast<void
> (0) : __assert_fail ("cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() < 256 && cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace() < 256 && \"Unknown address space\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 4784, __PRETTY_FUNCTION__))
4781 < 256 &&((cast<PointerType>(I.getArgOperand(0)->getType())->
getAddressSpace() < 256 && cast<PointerType>
(I.getArgOperand(1)->getType())->getAddressSpace() <
256 && "Unknown address space") ? static_cast<void
> (0) : __assert_fail ("cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() < 256 && cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace() < 256 && \"Unknown address space\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 4784, __PRETTY_FUNCTION__))
4782 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()((cast<PointerType>(I.getArgOperand(0)->getType())->
getAddressSpace() < 256 && cast<PointerType>
(I.getArgOperand(1)->getType())->getAddressSpace() <
256 && "Unknown address space") ? static_cast<void
> (0) : __assert_fail ("cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() < 256 && cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace() < 256 && \"Unknown address space\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 4784, __PRETTY_FUNCTION__))
4783 < 256 &&((cast<PointerType>(I.getArgOperand(0)->getType())->
getAddressSpace() < 256 && cast<PointerType>
(I.getArgOperand(1)->getType())->getAddressSpace() <
256 && "Unknown address space") ? static_cast<void
> (0) : __assert_fail ("cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() < 256 && cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace() < 256 && \"Unknown address space\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 4784, __PRETTY_FUNCTION__))
4784 "Unknown address space")((cast<PointerType>(I.getArgOperand(0)->getType())->
getAddressSpace() < 256 && cast<PointerType>
(I.getArgOperand(1)->getType())->getAddressSpace() <
256 && "Unknown address space") ? static_cast<void
> (0) : __assert_fail ("cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() < 256 && cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace() < 256 && \"Unknown address space\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 4784, __PRETTY_FUNCTION__));
4785 SDValue Op1 = getValue(I.getArgOperand(0));
4786 SDValue Op2 = getValue(I.getArgOperand(1));
4787 SDValue Op3 = getValue(I.getArgOperand(2));
4788 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4789 if (!Align)
4790 Align = 1; // @llvm.memcpy defines 0 and 1 to both mean no alignment.
4791 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4792 DAG.setRoot(DAG.getMemcpy(getRoot(), sdl, Op1, Op2, Op3, Align, isVol, false,
4793 MachinePointerInfo(I.getArgOperand(0)),
4794 MachinePointerInfo(I.getArgOperand(1))));
4795 return nullptr;
4796 }
4797 case Intrinsic::memset: {
4798 // FIXME: this definition of "user defined address space" is x86-specific
4799 // Assert for address < 256 since we support only user defined address
4800 // spaces.
4801 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()((cast<PointerType>(I.getArgOperand(0)->getType())->
getAddressSpace() < 256 && "Unknown address space"
) ? static_cast<void> (0) : __assert_fail ("cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() < 256 && \"Unknown address space\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 4803, __PRETTY_FUNCTION__))
4802 < 256 &&((cast<PointerType>(I.getArgOperand(0)->getType())->
getAddressSpace() < 256 && "Unknown address space"
) ? static_cast<void> (0) : __assert_fail ("cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() < 256 && \"Unknown address space\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 4803, __PRETTY_FUNCTION__))
4803 "Unknown address space")((cast<PointerType>(I.getArgOperand(0)->getType())->
getAddressSpace() < 256 && "Unknown address space"
) ? static_cast<void> (0) : __assert_fail ("cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() < 256 && \"Unknown address space\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 4803, __PRETTY_FUNCTION__));
4804 SDValue Op1 = getValue(I.getArgOperand(0));
4805 SDValue Op2 = getValue(I.getArgOperand(1));
4806 SDValue Op3 = getValue(I.getArgOperand(2));
4807 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4808 if (!Align)
4809 Align = 1; // @llvm.memset defines 0 and 1 to both mean no alignment.
4810 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4811 DAG.setRoot(DAG.getMemset(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4812 MachinePointerInfo(I.getArgOperand(0))));
4813 return nullptr;
4814 }
4815 case Intrinsic::memmove: {
4816 // FIXME: this definition of "user defined address space" is x86-specific
4817 // Assert for address < 256 since we support only user defined address
4818 // spaces.
4819 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()((cast<PointerType>(I.getArgOperand(0)->getType())->
getAddressSpace() < 256 && cast<PointerType>
(I.getArgOperand(1)->getType())->getAddressSpace() <
256 && "Unknown address space") ? static_cast<void
> (0) : __assert_fail ("cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() < 256 && cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace() < 256 && \"Unknown address space\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 4823, __PRETTY_FUNCTION__))
4820 < 256 &&((cast<PointerType>(I.getArgOperand(0)->getType())->
getAddressSpace() < 256 && cast<PointerType>
(I.getArgOperand(1)->getType())->getAddressSpace() <
256 && "Unknown address space") ? static_cast<void
> (0) : __assert_fail ("cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() < 256 && cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace() < 256 && \"Unknown address space\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 4823, __PRETTY_FUNCTION__))
4821 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()((cast<PointerType>(I.getArgOperand(0)->getType())->
getAddressSpace() < 256 && cast<PointerType>
(I.getArgOperand(1)->getType())->getAddressSpace() <
256 && "Unknown address space") ? static_cast<void
> (0) : __assert_fail ("cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() < 256 && cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace() < 256 && \"Unknown address space\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 4823, __PRETTY_FUNCTION__))
4822 < 256 &&((cast<PointerType>(I.getArgOperand(0)->getType())->
getAddressSpace() < 256 && cast<PointerType>
(I.getArgOperand(1)->getType())->getAddressSpace() <
256 && "Unknown address space") ? static_cast<void
> (0) : __assert_fail ("cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() < 256 && cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace() < 256 && \"Unknown address space\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 4823, __PRETTY_FUNCTION__))
4823 "Unknown address space")((cast<PointerType>(I.getArgOperand(0)->getType())->
getAddressSpace() < 256 && cast<PointerType>
(I.getArgOperand(1)->getType())->getAddressSpace() <
256 && "Unknown address space") ? static_cast<void
> (0) : __assert_fail ("cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() < 256 && cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace() < 256 && \"Unknown address space\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 4823, __PRETTY_FUNCTION__));
4824 SDValue Op1 = getValue(I.getArgOperand(0));
4825 SDValue Op2 = getValue(I.getArgOperand(1));
4826 SDValue Op3 = getValue(I.getArgOperand(2));
4827 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4828 if (!Align)
4829 Align = 1; // @llvm.memmove defines 0 and 1 to both mean no alignment.
4830 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4831 DAG.setRoot(DAG.getMemmove(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4832 MachinePointerInfo(I.getArgOperand(0)),
4833 MachinePointerInfo(I.getArgOperand(1))));
4834 return nullptr;
4835 }
4836 case Intrinsic::dbg_declare: {
4837 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
4838 MDNode *Variable = DI.getVariable();
4839 MDNode *Expression = DI.getExpression();
4840 const Value *Address = DI.getAddress();
4841 DIVariable DIVar(Variable);
4842 assert((!DIVar || DIVar.isVariable()) &&(((!DIVar || DIVar.isVariable()) && "Variable in DbgDeclareInst should be either null or a DIVariable."
) ? static_cast<void> (0) : __assert_fail ("(!DIVar || DIVar.isVariable()) && \"Variable in DbgDeclareInst should be either null or a DIVariable.\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 4843, __PRETTY_FUNCTION__))
4843 "Variable in DbgDeclareInst should be either null or a DIVariable.")(((!DIVar || DIVar.isVariable()) && "Variable in DbgDeclareInst should be either null or a DIVariable."
) ? static_cast<void> (0) : __assert_fail ("(!DIVar || DIVar.isVariable()) && \"Variable in DbgDeclareInst should be either null or a DIVariable.\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 4843, __PRETTY_FUNCTION__));
4844 if (!Address || !DIVar) {
4845 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << "Dropping debug info for " <<
DI << "\n"; } } while (0);
4846 return nullptr;
4847 }
4848
4849 // Check if address has undef value.
4850 if (isa<UndefValue>(Address) ||
4851 (Address->use_empty() && !isa<Argument>(Address))) {
4852 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << "Dropping debug info for " <<
DI << "\n"; } } while (0);
4853 return nullptr;
4854 }
4855
4856 SDValue &N = NodeMap[Address];
4857 if (!N.getNode() && isa<Argument>(Address))
4858 // Check unused arguments map.
4859 N = UnusedArgNodeMap[Address];
4860 SDDbgValue *SDV;
4861 if (N.getNode()) {
4862 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
4863 Address = BCI->getOperand(0);
4864 // Parameters are handled specially.
4865 bool isParameter =
4866 (DIVariable(Variable).getTag() == dwarf::DW_TAG_arg_variable ||
4867 isa<Argument>(Address));
4868
4869 const AllocaInst *AI = dyn_cast<AllocaInst>(Address);
4870
4871 if (isParameter && !AI) {
4872 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode());
4873 if (FINode)
4874 // Byval parameter. We have a frame index at this point.
4875 SDV = DAG.getFrameIndexDbgValue(
4876 Variable, Expression, FINode->getIndex(), 0, dl, SDNodeOrder);
4877 else {
4878 // Address is an argument, so try to emit its dbg value using
4879 // virtual register info from the FuncInfo.ValueMap.
4880 EmitFuncArgumentDbgValue(Address, Variable, Expression, 0, false, N);
4881 return nullptr;
4882 }
4883 } else if (AI)
4884 SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(),
4885 true, 0, dl, SDNodeOrder);
4886 else {
4887 // Can't do anything with other non-AI cases yet.
4888 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << "Dropping debug info for " <<
DI << "\n"; } } while (0);
4889 DEBUG(dbgs() << "non-AllocaInst issue for Address: \n\t")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << "non-AllocaInst issue for Address: \n\t"
; } } while (0);
4890 DEBUG(Address->dump())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { Address->dump(); } } while (0);
4891 return nullptr;
4892 }
4893 DAG.AddDbgValue(SDV, N.getNode(), isParameter);
4894 } else {
4895 // If Address is an argument then try to emit its dbg value using
4896 // virtual register info from the FuncInfo.ValueMap.
4897 if (!EmitFuncArgumentDbgValue(Address, Variable, Expression, 0, false,
4898 N)) {
4899 // If variable is pinned by a alloca in dominating bb then
4900 // use StaticAllocaMap.
4901 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
4902 if (AI->getParent() != DI.getParent()) {
4903 DenseMap<const AllocaInst*, int>::iterator SI =
4904 FuncInfo.StaticAllocaMap.find(AI);
4905 if (SI != FuncInfo.StaticAllocaMap.end()) {
4906 SDV = DAG.getFrameIndexDbgValue(Variable, Expression, SI->second,
4907 0, dl, SDNodeOrder);
4908 DAG.AddDbgValue(SDV, nullptr, false);
4909 return nullptr;
4910 }
4911 }
4912 }
4913 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << "Dropping debug info for " <<
DI << "\n"; } } while (0);
4914 }
4915 }
4916 return nullptr;
4917 }
4918 case Intrinsic::dbg_value: {
4919 const DbgValueInst &DI = cast<DbgValueInst>(I);
4920 DIVariable DIVar(DI.getVariable());
4921 assert((!DIVar || DIVar.isVariable()) &&(((!DIVar || DIVar.isVariable()) && "Variable in DbgValueInst should be either null or a DIVariable."
) ? static_cast<void> (0) : __assert_fail ("(!DIVar || DIVar.isVariable()) && \"Variable in DbgValueInst should be either null or a DIVariable.\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 4922, __PRETTY_FUNCTION__))
4922 "Variable in DbgValueInst should be either null or a DIVariable.")(((!DIVar || DIVar.isVariable()) && "Variable in DbgValueInst should be either null or a DIVariable."
) ? static_cast<void> (0) : __assert_fail ("(!DIVar || DIVar.isVariable()) && \"Variable in DbgValueInst should be either null or a DIVariable.\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 4922, __PRETTY_FUNCTION__));
4923 if (!DIVar)
4924 return nullptr;
4925
4926 MDNode *Variable = DI.getVariable();
4927 MDNode *Expression = DI.getExpression();
4928 uint64_t Offset = DI.getOffset();
4929 const Value *V = DI.getValue();
4930 if (!V)
4931 return nullptr;
4932
4933 SDDbgValue *SDV;
4934 if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V)) {
4935 SDV = DAG.getConstantDbgValue(Variable, Expression, V, Offset, dl,
4936 SDNodeOrder);
4937 DAG.AddDbgValue(SDV, nullptr, false);
4938 } else {
4939 // Do not use getValue() in here; we don't want to generate code at
4940 // this point if it hasn't been done yet.
4941 SDValue N = NodeMap[V];
4942 if (!N.getNode() && isa<Argument>(V))
4943 // Check unused arguments map.
4944 N = UnusedArgNodeMap[V];
4945 if (N.getNode()) {
4946 // A dbg.value for an alloca is always indirect.
4947 bool IsIndirect = isa<AllocaInst>(V) || Offset != 0;
4948 if (!EmitFuncArgumentDbgValue(V, Variable, Expression, Offset,
4949 IsIndirect, N)) {
4950 SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(),
4951 IsIndirect, Offset, dl, SDNodeOrder);
4952 DAG.AddDbgValue(SDV, N.getNode(), false);
4953 }
4954 } else if (!V->use_empty() ) {
4955 // Do not call getValue(V) yet, as we don't want to generate code.
4956 // Remember it for later.
4957 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder);
4958 DanglingDebugInfoMap[V] = DDI;
4959 } else {
4960 // We may expand this to cover more cases. One case where we have no
4961 // data available is an unreferenced parameter.
4962 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << "Dropping debug info for " <<
DI << "\n"; } } while (0);
4963 }
4964 }
4965
4966 // Build a debug info table entry.
4967 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V))
4968 V = BCI->getOperand(0);
4969 const AllocaInst *AI = dyn_cast<AllocaInst>(V);
4970 // Don't handle byval struct arguments or VLAs, for example.
4971 if (!AI) {
4972 DEBUG(dbgs() << "Dropping debug location info for:\n " << DI << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << "Dropping debug location info for:\n "
<< DI << "\n"; } } while (0);
4973 DEBUG(dbgs() << " Last seen at:\n " << *V << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << " Last seen at:\n " << *
V << "\n"; } } while (0);
4974 return nullptr;
4975 }
4976 DenseMap<const AllocaInst*, int>::iterator SI =
4977 FuncInfo.StaticAllocaMap.find(AI);
4978 if (SI == FuncInfo.StaticAllocaMap.end())
4979 return nullptr; // VLAs.
4980 return nullptr;
4981 }
4982
4983 case Intrinsic::eh_typeid_for: {
4984 // Find the type id for the given typeinfo.
4985 GlobalValue *GV = ExtractTypeInfo(I.getArgOperand(0));
4986 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV);
4987 Res = DAG.getConstant(TypeID, MVT::i32);
4988 setValue(&I, Res);
4989 return nullptr;
4990 }
4991
4992 case Intrinsic::eh_return_i32:
4993 case Intrinsic::eh_return_i64:
4994 DAG.getMachineFunction().getMMI().setCallsEHReturn(true);
4995 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, sdl,
4996 MVT::Other,
4997 getControlRoot(),
4998 getValue(I.getArgOperand(0)),
4999 getValue(I.getArgOperand(1))));
5000 return nullptr;
5001 case Intrinsic::eh_unwind_init:
5002 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true);
5003 return nullptr;
5004 case Intrinsic::eh_dwarf_cfa: {
5005 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), sdl,
5006 TLI.getPointerTy());
5007 SDValue Offset = DAG.getNode(ISD::ADD, sdl,
5008 CfaArg.getValueType(),
5009 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, sdl,
5010 CfaArg.getValueType()),
5011 CfaArg);
5012 SDValue FA = DAG.getNode(ISD::FRAMEADDR, sdl, TLI.getPointerTy(),
5013 DAG.getConstant(0, TLI.getPointerTy()));
5014 setValue(&I, DAG.getNode(ISD::ADD, sdl, FA.getValueType(),
5015 FA, Offset));
5016 return nullptr;
5017 }
5018 case Intrinsic::eh_sjlj_callsite: {
5019 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5020 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0));
5021 assert(CI && "Non-constant call site value in eh.sjlj.callsite!")((CI && "Non-constant call site value in eh.sjlj.callsite!"
) ? static_cast<void> (0) : __assert_fail ("CI && \"Non-constant call site value in eh.sjlj.callsite!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 5021, __PRETTY_FUNCTION__));
5022 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!")((MMI.getCurrentCallSite() == 0 && "Overlapping call sites!"
) ? static_cast<void> (0) : __assert_fail ("MMI.getCurrentCallSite() == 0 && \"Overlapping call sites!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 5022, __PRETTY_FUNCTION__));
5023
5024 MMI.setCurrentCallSite(CI->getZExtValue());
5025 return nullptr;
5026 }
5027 case Intrinsic::eh_sjlj_functioncontext: {
5028 // Get and store the index of the function context.
5029 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5030 AllocaInst *FnCtx =
5031 cast<AllocaInst>(I.getArgOperand(0)->stripPointerCasts());
5032 int FI = FuncInfo.StaticAllocaMap[FnCtx];
5033 MFI->setFunctionContextIndex(FI);
5034 return nullptr;
5035 }
5036 case Intrinsic::eh_sjlj_setjmp: {
5037 SDValue Ops[2];
5038 Ops[0] = getRoot();
5039 Ops[1] = getValue(I.getArgOperand(0));
5040 SDValue Op = DAG.getNode(ISD::EH_SJLJ_SETJMP, sdl,
5041 DAG.getVTList(MVT::i32, MVT::Other), Ops);
5042 setValue(&I, Op.getValue(0));
5043 DAG.setRoot(Op.getValue(1));
5044 return nullptr;
5045 }
5046 case Intrinsic::eh_sjlj_longjmp: {
5047 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, sdl, MVT::Other,
5048 getRoot(), getValue(I.getArgOperand(0))));
5049 return nullptr;
5050 }
5051
5052 case Intrinsic::masked_load:
5053 visitMaskedLoad(I);
5054 return nullptr;
5055 case Intrinsic::masked_store:
5056 visitMaskedStore(I);
5057 return nullptr;
5058 case Intrinsic::x86_mmx_pslli_w:
5059 case Intrinsic::x86_mmx_pslli_d:
5060 case Intrinsic::x86_mmx_pslli_q:
5061 case Intrinsic::x86_mmx_psrli_w:
5062 case Intrinsic::x86_mmx_psrli_d:
5063 case Intrinsic::x86_mmx_psrli_q:
5064 case Intrinsic::x86_mmx_psrai_w:
5065 case Intrinsic::x86_mmx_psrai_d: {
5066 SDValue ShAmt = getValue(I.getArgOperand(1));
5067 if (isa<ConstantSDNode>(ShAmt)) {
5068 visitTargetIntrinsic(I, Intrinsic);
5069 return nullptr;
5070 }
5071 unsigned NewIntrinsic = 0;
5072 EVT ShAmtVT = MVT::v2i32;
5073 switch (Intrinsic) {
5074 case Intrinsic::x86_mmx_pslli_w:
5075 NewIntrinsic = Intrinsic::x86_mmx_psll_w;
5076 break;
5077 case Intrinsic::x86_mmx_pslli_d:
5078 NewIntrinsic = Intrinsic::x86_mmx_psll_d;
5079 break;
5080 case Intrinsic::x86_mmx_pslli_q:
5081 NewIntrinsic = Intrinsic::x86_mmx_psll_q;
5082 break;
5083 case Intrinsic::x86_mmx_psrli_w:
5084 NewIntrinsic = Intrinsic::x86_mmx_psrl_w;
5085 break;
5086 case Intrinsic::x86_mmx_psrli_d:
5087 NewIntrinsic = Intrinsic::x86_mmx_psrl_d;
5088 break;
5089 case Intrinsic::x86_mmx_psrli_q:
5090 NewIntrinsic = Intrinsic::x86_mmx_psrl_q;
5091 break;
5092 case Intrinsic::x86_mmx_psrai_w:
5093 NewIntrinsic = Intrinsic::x86_mmx_psra_w;
5094 break;
5095 case Intrinsic::x86_mmx_psrai_d:
5096 NewIntrinsic = Intrinsic::x86_mmx_psra_d;
5097 break;
5098 default: llvm_unreachable("Impossible intrinsic")::llvm::llvm_unreachable_internal("Impossible intrinsic", "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 5098); // Can't reach here.
5099 }
5100
5101 // The vector shift intrinsics with scalars uses 32b shift amounts but
5102 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
5103 // to be zero.
5104 // We must do this early because v2i32 is not a legal type.
5105 SDValue ShOps[2];
5106 ShOps[0] = ShAmt;
5107 ShOps[1] = DAG.getConstant(0, MVT::i32);
5108 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, sdl, ShAmtVT, ShOps);
5109 EVT DestVT = TLI.getValueType(I.getType());
5110 ShAmt = DAG.getNode(ISD::BITCAST, sdl, DestVT, ShAmt);
5111 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, sdl, DestVT,
5112 DAG.getConstant(NewIntrinsic, MVT::i32),
5113 getValue(I.getArgOperand(0)), ShAmt);
5114 setValue(&I, Res);
5115 return nullptr;
5116 }
5117 case Intrinsic::x86_avx_vinsertf128_pd_256:
5118 case Intrinsic::x86_avx_vinsertf128_ps_256:
5119 case Intrinsic::x86_avx_vinsertf128_si_256:
5120 case Intrinsic::x86_avx2_vinserti128: {
5121 EVT DestVT = TLI.getValueType(I.getType());
5122 EVT ElVT = TLI.getValueType(I.getArgOperand(1)->getType());
5123 uint64_t Idx = (cast<ConstantInt>(I.getArgOperand(2))->getZExtValue() & 1) *
5124 ElVT.getVectorNumElements();
5125 Res =
5126 DAG.getNode(ISD::INSERT_SUBVECTOR, sdl, DestVT,
5127 getValue(I.getArgOperand(0)), getValue(I.getArgOperand(1)),
5128 DAG.getConstant(Idx, TLI.getVectorIdxTy()));
5129 setValue(&I, Res);
5130 return nullptr;
5131 }
5132 case Intrinsic::x86_avx_vextractf128_pd_256:
5133 case Intrinsic::x86_avx_vextractf128_ps_256:
5134 case Intrinsic::x86_avx_vextractf128_si_256:
5135 case Intrinsic::x86_avx2_vextracti128: {
5136 EVT DestVT = TLI.getValueType(I.getType());
5137 uint64_t Idx = (cast<ConstantInt>(I.getArgOperand(1))->getZExtValue() & 1) *
5138 DestVT.getVectorNumElements();
5139 Res = DAG.getNode(ISD::EXTRACT_SUBVECTOR, sdl, DestVT,
5140 getValue(I.getArgOperand(0)),
5141 DAG.getConstant(Idx, TLI.getVectorIdxTy()));
5142 setValue(&I, Res);
5143 return nullptr;
5144 }
5145 case Intrinsic::convertff:
5146 case Intrinsic::convertfsi:
5147 case Intrinsic::convertfui:
5148 case Intrinsic::convertsif:
5149 case Intrinsic::convertuif:
5150 case Intrinsic::convertss:
5151 case Intrinsic::convertsu:
5152 case Intrinsic::convertus:
5153 case Intrinsic::convertuu: {
5154 ISD::CvtCode Code = ISD::CVT_INVALID;
5155 switch (Intrinsic) {
5156 default: llvm_unreachable("Impossible intrinsic")::llvm::llvm_unreachable_internal("Impossible intrinsic", "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 5156); // Can't reach here.
5157 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
5158 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
5159 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
5160 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
5161 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
5162 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
5163 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
5164 case Intrinsic::convertus: Code = ISD::CVT_US; break;
5165 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
5166 }
5167 EVT DestVT = TLI.getValueType(I.getType());
5168 const Value *Op1 = I.getArgOperand(0);
5169 Res = DAG.getConvertRndSat(DestVT, sdl, getValue(Op1),
5170 DAG.getValueType(DestVT),
5171 DAG.getValueType(getValue(Op1).getValueType()),
5172 getValue(I.getArgOperand(1)),
5173 getValue(I.getArgOperand(2)),
5174 Code);
5175 setValue(&I, Res);
5176 return nullptr;
5177 }
5178 case Intrinsic::powi:
5179 setValue(&I, ExpandPowI(sdl, getValue(I.getArgOperand(0)),
5180 getValue(I.getArgOperand(1)), DAG));
5181 return nullptr;
5182 case Intrinsic::log:
5183 setValue(&I, expandLog(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
5184 return nullptr;
5185 case Intrinsic::log2:
5186 setValue(&I, expandLog2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
5187 return nullptr;
5188 case Intrinsic::log10:
5189 setValue(&I, expandLog10(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
5190 return nullptr;
5191 case Intrinsic::exp:
5192 setValue(&I, expandExp(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
5193 return nullptr;
5194 case Intrinsic::exp2:
5195 setValue(&I, expandExp2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
5196 return nullptr;
5197 case Intrinsic::pow:
5198 setValue(&I, expandPow(sdl, getValue(I.getArgOperand(0)),
5199 getValue(I.getArgOperand(1)), DAG, TLI));
5200 return nullptr;
5201 case Intrinsic::sqrt:
5202 case Intrinsic::fabs:
5203 case Intrinsic::sin:
5204 case Intrinsic::cos:
5205 case Intrinsic::floor:
5206 case Intrinsic::ceil:
5207 case Intrinsic::trunc:
5208 case Intrinsic::rint:
5209 case Intrinsic::nearbyint:
5210 case Intrinsic::round: {
5211 unsigned Opcode;
5212 switch (Intrinsic) {
5213 default: llvm_unreachable("Impossible intrinsic")::llvm::llvm_unreachable_internal("Impossible intrinsic", "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 5213); // Can't reach here.
5214 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break;
5215 case Intrinsic::fabs: Opcode = ISD::FABS; break;
5216 case Intrinsic::sin: Opcode = ISD::FSIN; break;
5217 case Intrinsic::cos: Opcode = ISD::FCOS; break;
5218 case Intrinsic::floor: Opcode = ISD::FFLOOR; break;
5219 case Intrinsic::ceil: Opcode = ISD::FCEIL; break;
5220 case Intrinsic::trunc: Opcode = ISD::FTRUNC; break;
5221 case Intrinsic::rint: Opcode = ISD::FRINT; break;
5222 case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break;
5223 case Intrinsic::round: Opcode = ISD::FROUND; break;
5224 }
5225
5226 setValue(&I, DAG.getNode(Opcode, sdl,
5227 getValue(I.getArgOperand(0)).getValueType(),
5228 getValue(I.getArgOperand(0))));
5229 return nullptr;
5230 }
5231 case Intrinsic::minnum:
5232 setValue(&I, DAG.getNode(ISD::FMINNUM, sdl,
5233 getValue(I.getArgOperand(0)).getValueType(),
5234 getValue(I.getArgOperand(0)),
5235 getValue(I.getArgOperand(1))));
5236 return nullptr;
5237 case Intrinsic::maxnum:
5238 setValue(&I, DAG.getNode(ISD::FMAXNUM, sdl,
5239 getValue(I.getArgOperand(0)).getValueType(),
5240 getValue(I.getArgOperand(0)),
5241 getValue(I.getArgOperand(1))));
5242 return nullptr;
5243 case Intrinsic::copysign:
5244 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, sdl,
5245 getValue(I.getArgOperand(0)).getValueType(),
5246 getValue(I.getArgOperand(0)),
5247 getValue(I.getArgOperand(1))));
5248 return nullptr;
5249 case Intrinsic::fma:
5250 setValue(&I, DAG.getNode(ISD::FMA, sdl,
5251 getValue(I.getArgOperand(0)).getValueType(),
5252 getValue(I.getArgOperand(0)),
5253 getValue(I.getArgOperand(1)),
5254 getValue(I.getArgOperand(2))));
5255 return nullptr;
5256 case Intrinsic::fmuladd: {
5257 EVT VT = TLI.getValueType(I.getType());
5258 if (TM.Options.AllowFPOpFusion != FPOpFusion::Strict &&
5259 TLI.isFMAFasterThanFMulAndFAdd(VT)) {
5260 setValue(&I, DAG.getNode(ISD::FMA, sdl,
5261 getValue(I.getArgOperand(0)).getValueType(),
5262 getValue(I.getArgOperand(0)),
5263 getValue(I.getArgOperand(1)),
5264 getValue(I.getArgOperand(2))));
5265 } else {
5266 SDValue Mul = DAG.getNode(ISD::FMUL, sdl,
5267 getValue(I.getArgOperand(0)).getValueType(),
5268 getValue(I.getArgOperand(0)),
5269 getValue(I.getArgOperand(1)));
5270 SDValue Add = DAG.getNode(ISD::FADD, sdl,
5271 getValue(I.getArgOperand(0)).getValueType(),
5272 Mul,
5273 getValue(I.getArgOperand(2)));
5274 setValue(&I, Add);
5275 }
5276 return nullptr;
5277 }
5278 case Intrinsic::convert_to_fp16:
5279 setValue(&I, DAG.getNode(ISD::BITCAST, sdl, MVT::i16,
5280 DAG.getNode(ISD::FP_ROUND, sdl, MVT::f16,
5281 getValue(I.getArgOperand(0)),
5282 DAG.getTargetConstant(0, MVT::i32))));
5283 return nullptr;
5284 case Intrinsic::convert_from_fp16:
5285 setValue(&I,
5286 DAG.getNode(ISD::FP_EXTEND, sdl, TLI.getValueType(I.getType()),
5287 DAG.getNode(ISD::BITCAST, sdl, MVT::f16,
5288 getValue(I.getArgOperand(0)))));
5289 return nullptr;
5290 case Intrinsic::pcmarker: {
5291 SDValue Tmp = getValue(I.getArgOperand(0));
5292 DAG.setRoot(DAG.getNode(ISD::PCMARKER, sdl, MVT::Other, getRoot(), Tmp));
5293 return nullptr;
5294 }
5295 case Intrinsic::readcyclecounter: {
5296 SDValue Op = getRoot();
5297 Res = DAG.getNode(ISD::READCYCLECOUNTER, sdl,
5298 DAG.getVTList(MVT::i64, MVT::Other), Op);
5299 setValue(&I, Res);
5300 DAG.setRoot(Res.getValue(1));
5301 return nullptr;
5302 }
5303 case Intrinsic::bswap:
5304 setValue(&I, DAG.getNode(ISD::BSWAP, sdl,
5305 getValue(I.getArgOperand(0)).getValueType(),
5306 getValue(I.getArgOperand(0))));
5307 return nullptr;
5308 case Intrinsic::cttz: {
5309 SDValue Arg = getValue(I.getArgOperand(0));
5310 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
5311 EVT Ty = Arg.getValueType();
5312 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTTZ : ISD::CTTZ_ZERO_UNDEF,
5313 sdl, Ty, Arg));
5314 return nullptr;
5315 }
5316 case Intrinsic::ctlz: {
5317 SDValue Arg = getValue(I.getArgOperand(0));
5318 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
5319 EVT Ty = Arg.getValueType();
5320 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTLZ : ISD::CTLZ_ZERO_UNDEF,
5321 sdl, Ty, Arg));
5322 return nullptr;
5323 }
5324 case Intrinsic::ctpop: {
5325 SDValue Arg = getValue(I.getArgOperand(0));
5326 EVT Ty = Arg.getValueType();
5327 setValue(&I, DAG.getNode(ISD::CTPOP, sdl, Ty, Arg));
5328 return nullptr;
5329 }
5330 case Intrinsic::stacksave: {
5331 SDValue Op = getRoot();
5332 Res = DAG.getNode(ISD::STACKSAVE, sdl,
5333 DAG.getVTList(TLI.getPointerTy(), MVT::Other), Op);
5334 setValue(&I, Res);
5335 DAG.setRoot(Res.getValue(1));
5336 return nullptr;
5337 }
5338 case Intrinsic::stackrestore: {
5339 Res = getValue(I.getArgOperand(0));
5340 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, sdl, MVT::Other, getRoot(), Res));
5341 return nullptr;
5342 }
5343 case Intrinsic::stackprotector: {
5344 // Emit code into the DAG to store the stack guard onto the stack.
5345 MachineFunction &MF = DAG.getMachineFunction();
5346 MachineFrameInfo *MFI = MF.getFrameInfo();
5347 EVT PtrTy = TLI.getPointerTy();
5348 SDValue Src, Chain = getRoot();
5349 const Value *Ptr = cast<LoadInst>(I.getArgOperand(0))->getPointerOperand();
5350 const GlobalVariable *GV = dyn_cast<GlobalVariable>(Ptr);
5351
5352 // See if Ptr is a bitcast. If it is, look through it and see if we can get
5353 // global variable __stack_chk_guard.
5354 if (!GV)
5355 if (const Operator *BC = dyn_cast<Operator>(Ptr))
5356 if (BC->getOpcode() == Instruction::BitCast)
5357 GV = dyn_cast<GlobalVariable>(BC->getOperand(0));
5358
5359 if (GV && TLI.useLoadStackGuardNode()) {
5360 // Emit a LOAD_STACK_GUARD node.
5361 MachineSDNode *Node = DAG.getMachineNode(TargetOpcode::LOAD_STACK_GUARD,
5362 sdl, PtrTy, Chain);
5363 MachinePointerInfo MPInfo(GV);
5364 MachineInstr::mmo_iterator MemRefs = MF.allocateMemRefsArray(1);
5365 unsigned Flags = MachineMemOperand::MOLoad |
5366 MachineMemOperand::MOInvariant;
5367 *MemRefs = MF.getMachineMemOperand(MPInfo, Flags,
5368 PtrTy.getSizeInBits() / 8,
5369 DAG.getEVTAlignment(PtrTy));
5370 Node->setMemRefs(MemRefs, MemRefs + 1);
5371
5372 // Copy the guard value to a virtual register so that it can be
5373 // retrieved in the epilogue.
5374 Src = SDValue(Node, 0);
5375 const TargetRegisterClass *RC =
5376 TLI.getRegClassFor(Src.getSimpleValueType());
5377 unsigned Reg = MF.getRegInfo().createVirtualRegister(RC);
5378
5379 SPDescriptor.setGuardReg(Reg);
5380 Chain = DAG.getCopyToReg(Chain, sdl, Reg, Src);
5381 } else {
5382 Src = getValue(I.getArgOperand(0)); // The guard's value.
5383 }
5384
5385 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1));
5386
5387 int FI = FuncInfo.StaticAllocaMap[Slot];
5388 MFI->setStackProtectorIndex(FI);
5389
5390 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
5391
5392 // Store the stack protector onto the stack.
5393 Res = DAG.getStore(Chain, sdl, Src, FIN,
5394 MachinePointerInfo::getFixedStack(FI),
5395 true, false, 0);
5396 setValue(&I, Res);
5397 DAG.setRoot(Res);
5398 return nullptr;
5399 }
5400 case Intrinsic::objectsize: {
5401 // If we don't know by now, we're never going to know.
5402 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1));
5403
5404 assert(CI && "Non-constant type in __builtin_object_size?")((CI && "Non-constant type in __builtin_object_size?"
) ? static_cast<void> (0) : __assert_fail ("CI && \"Non-constant type in __builtin_object_size?\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 5404, __PRETTY_FUNCTION__));
5405
5406 SDValue Arg = getValue(I.getCalledValue());
5407 EVT Ty = Arg.getValueType();
5408
5409 if (CI->isZero())
5410 Res = DAG.getConstant(-1ULL, Ty);
5411 else
5412 Res = DAG.getConstant(0, Ty);
5413
5414 setValue(&I, Res);
5415 return nullptr;
5416 }
5417 case Intrinsic::annotation:
5418 case Intrinsic::ptr_annotation:
5419 // Drop the intrinsic, but forward the value
5420 setValue(&I, getValue(I.getOperand(0)));
5421 return nullptr;
5422 case Intrinsic::assume:
5423 case Intrinsic::var_annotation:
5424 // Discard annotate attributes and assumptions
5425 return nullptr;
5426
5427 case Intrinsic::init_trampoline: {
5428 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts());
5429
5430 SDValue Ops[6];
5431 Ops[0] = getRoot();
5432 Ops[1] = getValue(I.getArgOperand(0));
5433 Ops[2] = getValue(I.getArgOperand(1));
5434 Ops[3] = getValue(I.getArgOperand(2));
5435 Ops[4] = DAG.getSrcValue(I.getArgOperand(0));
5436 Ops[5] = DAG.getSrcValue(F);
5437
5438 Res = DAG.getNode(ISD::INIT_TRAMPOLINE, sdl, MVT::Other, Ops);
5439
5440 DAG.setRoot(Res);
5441 return nullptr;
5442 }
5443 case Intrinsic::adjust_trampoline: {
5444 setValue(&I, DAG.getNode(ISD::ADJUST_TRAMPOLINE, sdl,
5445 TLI.getPointerTy(),
5446 getValue(I.getArgOperand(0))));
5447 return nullptr;
5448 }
5449 case Intrinsic::gcroot:
5450 if (GFI) {
5451 const Value *Alloca = I.getArgOperand(0)->stripPointerCasts();
5452 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1));
5453
5454 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
5455 GFI->addStackRoot(FI->getIndex(), TypeMap);
5456 }
5457 return nullptr;
5458 case Intrinsic::gcread:
5459 case Intrinsic::gcwrite:
5460 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!")::llvm::llvm_unreachable_internal("GC failed to lower gcread/gcwrite intrinsics!"
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 5460);
5461 case Intrinsic::flt_rounds:
5462 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, sdl, MVT::i32));
5463 return nullptr;
5464
5465 case Intrinsic::expect: {
5466 // Just replace __builtin_expect(exp, c) with EXP.
5467 setValue(&I, getValue(I.getArgOperand(0)));
5468 return nullptr;
5469 }
5470
5471 case Intrinsic::debugtrap:
5472 case Intrinsic::trap: {
5473 StringRef TrapFuncName = TM.Options.getTrapFunctionName();
5474 if (TrapFuncName.empty()) {
5475 ISD::NodeType Op = (Intrinsic == Intrinsic::trap) ?
5476 ISD::TRAP : ISD::DEBUGTRAP;
5477 DAG.setRoot(DAG.getNode(Op, sdl,MVT::Other, getRoot()));
5478 return nullptr;
5479 }
5480 TargetLowering::ArgListTy Args;
5481
5482 TargetLowering::CallLoweringInfo CLI(DAG);
5483 CLI.setDebugLoc(sdl).setChain(getRoot())
5484 .setCallee(CallingConv::C, I.getType(),
5485 DAG.getExternalSymbol(TrapFuncName.data(), TLI.getPointerTy()),
5486 std::move(Args), 0);
5487
5488 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
5489 DAG.setRoot(Result.second);
5490 return nullptr;
5491 }
5492
5493 case Intrinsic::uadd_with_overflow:
5494 case Intrinsic::sadd_with_overflow:
5495 case Intrinsic::usub_with_overflow:
5496 case Intrinsic::ssub_with_overflow:
5497 case Intrinsic::umul_with_overflow:
5498 case Intrinsic::smul_with_overflow: {
5499 ISD::NodeType Op;
5500 switch (Intrinsic) {
5501 default: llvm_unreachable("Impossible intrinsic")::llvm::llvm_unreachable_internal("Impossible intrinsic", "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 5501); // Can't reach here.
5502 case Intrinsic::uadd_with_overflow: Op = ISD::UADDO; break;
5503 case Intrinsic::sadd_with_overflow: Op = ISD::SADDO; break;
5504 case Intrinsic::usub_with_overflow: Op = ISD::USUBO; break;
5505 case Intrinsic::ssub_with_overflow: Op = ISD::SSUBO; break;
5506 case Intrinsic::umul_with_overflow: Op = ISD::UMULO; break;
5507 case Intrinsic::smul_with_overflow: Op = ISD::SMULO; break;
5508 }
5509 SDValue Op1 = getValue(I.getArgOperand(0));
5510 SDValue Op2 = getValue(I.getArgOperand(1));
5511
5512 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
5513 setValue(&I, DAG.getNode(Op, sdl, VTs, Op1, Op2));
5514 return nullptr;
5515 }
5516 case Intrinsic::prefetch: {
5517 SDValue Ops[5];
5518 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
5519 Ops[0] = getRoot();
5520 Ops[1] = getValue(I.getArgOperand(0));
5521 Ops[2] = getValue(I.getArgOperand(1));
5522 Ops[3] = getValue(I.getArgOperand(2));
5523 Ops[4] = getValue(I.getArgOperand(3));
5524 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, sdl,
5525 DAG.getVTList(MVT::Other), Ops,
5526 EVT::getIntegerVT(*Context, 8),
5527 MachinePointerInfo(I.getArgOperand(0)),
5528 0, /* align */
5529 false, /* volatile */
5530 rw==0, /* read */
5531 rw==1)); /* write */
5532 return nullptr;
5533 }
5534 case Intrinsic::lifetime_start:
5535 case Intrinsic::lifetime_end: {
5536 bool IsStart = (Intrinsic == Intrinsic::lifetime_start);
5537 // Stack coloring is not enabled in O0, discard region information.
5538 if (TM.getOptLevel() == CodeGenOpt::None)
5539 return nullptr;
5540
5541 SmallVector<Value *, 4> Allocas;
5542 GetUnderlyingObjects(I.getArgOperand(1), Allocas, DL);
5543
5544 for (SmallVectorImpl<Value*>::iterator Object = Allocas.begin(),
5545 E = Allocas.end(); Object != E; ++Object) {
5546 AllocaInst *LifetimeObject = dyn_cast_or_null<AllocaInst>(*Object);
5547
5548 // Could not find an Alloca.
5549 if (!LifetimeObject)
5550 continue;
5551
5552 // First check that the Alloca is static, otherwise it won't have a
5553 // valid frame index.
5554 auto SI = FuncInfo.StaticAllocaMap.find(LifetimeObject);
5555 if (SI == FuncInfo.StaticAllocaMap.end())
5556 return nullptr;
5557
5558 int FI = SI->second;
5559
5560 SDValue Ops[2];
5561 Ops[0] = getRoot();
5562 Ops[1] = DAG.getFrameIndex(FI, TLI.getPointerTy(), true);
5563 unsigned Opcode = (IsStart ? ISD::LIFETIME_START : ISD::LIFETIME_END);
5564
5565 Res = DAG.getNode(Opcode, sdl, MVT::Other, Ops);
5566 DAG.setRoot(Res);
5567 }
5568 return nullptr;
5569 }
5570 case Intrinsic::invariant_start:
5571 // Discard region information.
5572 setValue(&I, DAG.getUNDEF(TLI.getPointerTy()));
5573 return nullptr;
5574 case Intrinsic::invariant_end:
5575 // Discard region information.
5576 return nullptr;
5577 case Intrinsic::stackprotectorcheck: {
5578 // Do not actually emit anything for this basic block. Instead we initialize
5579 // the stack protector descriptor and export the guard variable so we can
5580 // access it in FinishBasicBlock.
5581 const BasicBlock *BB = I.getParent();
5582 SPDescriptor.initialize(BB, FuncInfo.MBBMap[BB], I);
5583 ExportFromCurrentBlock(SPDescriptor.getGuard());
5584
5585 // Flush our exports since we are going to process a terminator.
5586 (void)getControlRoot();
5587 return nullptr;
5588 }
5589 case Intrinsic::clear_cache:
5590 return TLI.getClearCacheBuiltinName();
5591 case Intrinsic::donothing:
5592 // ignore
5593 return nullptr;
5594 case Intrinsic::experimental_stackmap: {
5595 visitStackmap(I);
5596 return nullptr;
5597 }
5598 case Intrinsic::experimental_patchpoint_void:
5599 case Intrinsic::experimental_patchpoint_i64: {
5600 visitPatchpoint(&I);
5601 return nullptr;
5602 }
5603 case Intrinsic::experimental_gc_statepoint: {
5604 visitStatepoint(I);
5605 return nullptr;
5606 }
5607 case Intrinsic::experimental_gc_result_int:
5608 case Intrinsic::experimental_gc_result_float:
5609 case Intrinsic::experimental_gc_result_ptr:
5610 case Intrinsic::experimental_gc_result: {
5611 visitGCResult(I);
5612 return nullptr;
5613 }
5614 case Intrinsic::experimental_gc_relocate: {
5615 visitGCRelocate(I);
5616 return nullptr;
5617 }
5618 case Intrinsic::instrprof_increment:
5619 llvm_unreachable("instrprof failed to lower an increment")::llvm::llvm_unreachable_internal("instrprof failed to lower an increment"
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 5619);
5620
5621 case Intrinsic::frameallocate: {
5622 MachineFunction &MF = DAG.getMachineFunction();
5623 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
5624
5625 // Do the allocation and map it as a normal value.
5626 // FIXME: Maybe we should add this to the alloca map so that we don't have
5627 // to register allocate it?
5628 uint64_t Size = cast<ConstantInt>(I.getArgOperand(0))->getZExtValue();
5629 int Alloc = MF.getFrameInfo()->CreateFrameAllocation(Size);
5630 MVT PtrVT = TLI.getPointerTy(0);
5631 SDValue FIVal = DAG.getFrameIndex(Alloc, PtrVT);
5632 setValue(&I, FIVal);
5633
5634 // Directly emit a FRAME_ALLOC machine instr. Label assignment emission is
5635 // the same on all targets.
5636 MCSymbol *FrameAllocSym =
5637 MF.getMMI().getContext().getOrCreateFrameAllocSymbol(MF.getName());
5638 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, dl,
5639 TII->get(TargetOpcode::FRAME_ALLOC))
5640 .addSym(FrameAllocSym)
5641 .addFrameIndex(Alloc);
5642
5643 return nullptr;
5644 }
5645
5646 case Intrinsic::framerecover: {
5647 // i8* @llvm.framerecover(i8* %fn, i8* %fp)
5648 MachineFunction &MF = DAG.getMachineFunction();
5649 MVT PtrVT = TLI.getPointerTy(0);
5650
5651 // Get the symbol that defines the frame offset.
5652 Function *Fn = cast<Function>(I.getArgOperand(0)->stripPointerCasts());
5653 MCSymbol *FrameAllocSym =
5654 MF.getMMI().getContext().getOrCreateFrameAllocSymbol(Fn->getName());
5655
5656 // Create a TargetExternalSymbol for the label to avoid any target lowering
5657 // that would make this PC relative.
5658 StringRef Name = FrameAllocSym->getName();
5659 assert(Name.size() == strlen(Name.data()) && "not null terminated")((Name.size() == strlen(Name.data()) && "not null terminated"
) ? static_cast<void> (0) : __assert_fail ("Name.size() == strlen(Name.data()) && \"not null terminated\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 5659, __PRETTY_FUNCTION__));
5660 SDValue OffsetSym = DAG.getTargetExternalSymbol(Name.data(), PtrVT);
5661 SDValue OffsetVal =
5662 DAG.getNode(ISD::FRAME_ALLOC_RECOVER, sdl, PtrVT, OffsetSym);
5663
5664 // Add the offset to the FP.
5665 Value *FP = I.getArgOperand(1);
5666 SDValue FPVal = getValue(FP);
5667 SDValue Add = DAG.getNode(ISD::ADD, sdl, PtrVT, FPVal, OffsetVal);
5668 setValue(&I, Add);
5669
5670 return nullptr;
5671 }
5672 case Intrinsic::eh_begincatch:
5673 case Intrinsic::eh_endcatch:
5674 llvm_unreachable("begin/end catch intrinsics not lowered in codegen")::llvm::llvm_unreachable_internal("begin/end catch intrinsics not lowered in codegen"
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 5674);
5675 }
5676}
5677
5678std::pair<SDValue, SDValue>
5679SelectionDAGBuilder::lowerInvokable(TargetLowering::CallLoweringInfo &CLI,
5680 MachineBasicBlock *LandingPad) {
5681 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5682 MCSymbol *BeginLabel = nullptr;
5683
5684 if (LandingPad) {
5685 // Insert a label before the invoke call to mark the try range. This can be
5686 // used to detect deletion of the invoke via the MachineModuleInfo.
5687 BeginLabel = MMI.getContext().CreateTempSymbol();
5688
5689 // For SjLj, keep track of which landing pads go with which invokes
5690 // so as to maintain the ordering of pads in the LSDA.
5691 unsigned CallSiteIndex = MMI.getCurrentCallSite();
5692 if (CallSiteIndex) {
5693 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex);
5694 LPadToCallSiteMap[LandingPad].push_back(CallSiteIndex);
5695
5696 // Now that the call site is handled, stop tracking it.
5697 MMI.setCurrentCallSite(0);
5698 }
5699
5700 // Both PendingLoads and PendingExports must be flushed here;
5701 // this call might not return.
5702 (void)getRoot();
5703 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getControlRoot(), BeginLabel));
5704
5705 CLI.setChain(getRoot());
5706 }
5707 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5708 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
5709
5710 assert((CLI.IsTailCall || Result.second.getNode()) &&(((CLI.IsTailCall || Result.second.getNode()) && "Non-null chain expected with non-tail call!"
) ? static_cast<void> (0) : __assert_fail ("(CLI.IsTailCall || Result.second.getNode()) && \"Non-null chain expected with non-tail call!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 5711, __PRETTY_FUNCTION__))
5711 "Non-null chain expected with non-tail call!")(((CLI.IsTailCall || Result.second.getNode()) && "Non-null chain expected with non-tail call!"
) ? static_cast<void> (0) : __assert_fail ("(CLI.IsTailCall || Result.second.getNode()) && \"Non-null chain expected with non-tail call!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 5711, __PRETTY_FUNCTION__));
5712 assert((Result.second.getNode() || !Result.first.getNode()) &&(((Result.second.getNode() || !Result.first.getNode()) &&
"Null value expected with tail call!") ? static_cast<void
> (0) : __assert_fail ("(Result.second.getNode() || !Result.first.getNode()) && \"Null value expected with tail call!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 5713, __PRETTY_FUNCTION__))
5713 "Null value expected with tail call!")(((Result.second.getNode() || !Result.first.getNode()) &&
"Null value expected with tail call!") ? static_cast<void
> (0) : __assert_fail ("(Result.second.getNode() || !Result.first.getNode()) && \"Null value expected with tail call!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 5713, __PRETTY_FUNCTION__));
5714
5715 if (!Result.second.getNode()) {
5716 // As a special case, a null chain means that a tail call has been emitted
5717 // and the DAG root is already updated.
5718 HasTailCall = true;
5719
5720 // Since there's no actual continuation from this block, nothing can be
5721 // relying on us setting vregs for them.
5722 PendingExports.clear();
5723 } else {
5724 DAG.setRoot(Result.second);
5725 }
5726
5727 if (LandingPad) {
5728 // Insert a label at the end of the invoke call to mark the try range. This
5729 // can be used to detect deletion of the invoke via the MachineModuleInfo.
5730 MCSymbol *EndLabel = MMI.getContext().CreateTempSymbol();
5731 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getRoot(), EndLabel));
5732
5733 // Inform MachineModuleInfo of range.
5734 MMI.addInvoke(LandingPad, BeginLabel, EndLabel);
5735 }
5736
5737 return Result;
5738}
5739
5740void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee,
5741 bool isTailCall,
5742 MachineBasicBlock *LandingPad) {
5743 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
5744 FunctionType *FTy = cast<FunctionType>(PT->getElementType());
5745 Type *RetTy = FTy->getReturnType();
5746
5747 TargetLowering::ArgListTy Args;
5748 TargetLowering::ArgListEntry Entry;
5749 Args.reserve(CS.arg_size());
5750
5751 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
5752 i != e; ++i) {
5753 const Value *V = *i;
5754
5755 // Skip empty types
5756 if (V->getType()->isEmptyTy())
5757 continue;
5758
5759 SDValue ArgNode = getValue(V);
5760 Entry.Node = ArgNode; Entry.Ty = V->getType();
5761
5762 // Skip the first return-type Attribute to get to params.
5763 Entry.setAttributes(&CS, i - CS.arg_begin() + 1);
5764 Args.push_back(Entry);
5765 }
5766
5767 // Check if target-independent constraints permit a tail call here.
5768 // Target-dependent constraints are checked within TLI->LowerCallTo.
5769 if (isTailCall && !isInTailCallPosition(CS, DAG.getTarget()))
5770 isTailCall = false;
5771
5772 TargetLowering::CallLoweringInfo CLI(DAG);
5773 CLI.setDebugLoc(getCurSDLoc()).setChain(getRoot())
5774 .setCallee(RetTy, FTy, Callee, std::move(Args), CS)
5775 .setTailCall(isTailCall);
5776 std::pair<SDValue,SDValue> Result = lowerInvokable(CLI, LandingPad);
5777
5778 if (Result.first.getNode())
5779 setValue(CS.getInstruction(), Result.first);
5780}
5781
5782/// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the
5783/// value is equal or not-equal to zero.
5784static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) {
5785 for (const User *U : V->users()) {
5786 if (const ICmpInst *IC = dyn_cast<ICmpInst>(U))
5787 if (IC->isEquality())
5788 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1)))
5789 if (C->isNullValue())
5790 continue;
5791 // Unknown instruction.
5792 return false;
5793 }
5794 return true;
5795}
5796
5797static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT,
5798 Type *LoadTy,
5799 SelectionDAGBuilder &Builder) {
5800
5801 // Check to see if this load can be trivially constant folded, e.g. if the
5802 // input is from a string literal.
5803 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) {
5804 // Cast pointer to the type we really want to load.
5805 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput),
5806 PointerType::getUnqual(LoadTy));
5807
5808 if (const Constant *LoadCst =
5809 ConstantFoldLoadFromConstPtr(const_cast<Constant *>(LoadInput),
5810 Builder.DL))
5811 return Builder.getValue(LoadCst);
5812 }
5813
5814 // Otherwise, we have to emit the load. If the pointer is to unfoldable but
5815 // still constant memory, the input chain can be the entry node.
5816 SDValue Root;
5817 bool ConstantMemory = false;
5818
5819 // Do not serialize (non-volatile) loads of constant memory with anything.
5820 if (Builder.AA->pointsToConstantMemory(PtrVal)) {
5821 Root = Builder.DAG.getEntryNode();
5822 ConstantMemory = true;
5823 } else {
5824 // Do not serialize non-volatile loads against each other.
5825 Root = Builder.DAG.getRoot();
5826 }
5827
5828 SDValue Ptr = Builder.getValue(PtrVal);
5829 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurSDLoc(), Root,
5830 Ptr, MachinePointerInfo(PtrVal),
5831 false /*volatile*/,
5832 false /*nontemporal*/,
5833 false /*isinvariant*/, 1 /* align=1 */);
5834
5835 if (!ConstantMemory)
5836 Builder.PendingLoads.push_back(LoadVal.getValue(1));
5837 return LoadVal;
5838}
5839
5840/// processIntegerCallValue - Record the value for an instruction that
5841/// produces an integer result, converting the type where necessary.
5842void SelectionDAGBuilder::processIntegerCallValue(const Instruction &I,
5843 SDValue Value,
5844 bool IsSigned) {
5845 EVT VT = DAG.getTargetLoweringInfo().getValueType(I.getType(), true);
5846 if (IsSigned)
5847 Value = DAG.getSExtOrTrunc(Value, getCurSDLoc(), VT);
5848 else
5849 Value = DAG.getZExtOrTrunc(Value, getCurSDLoc(), VT);
5850 setValue(&I, Value);
5851}
5852
5853/// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form.
5854/// If so, return true and lower it, otherwise return false and it will be
5855/// lowered like a normal call.
5856bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) {
5857 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t)
5858 if (I.getNumArgOperands() != 3)
5859 return false;
5860
5861 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1);
5862 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() ||
5863 !I.getArgOperand(2)->getType()->isIntegerTy() ||
5864 !I.getType()->isIntegerTy())
5865 return false;
5866
5867 const Value *Size = I.getArgOperand(2);
5868 const ConstantInt *CSize = dyn_cast<ConstantInt>(Size);
5869 if (CSize && CSize->getZExtValue() == 0) {
5870 EVT CallVT = DAG.getTargetLoweringInfo().getValueType(I.getType(), true);
5871 setValue(&I, DAG.getConstant(0, CallVT));
5872 return true;
5873 }
5874
5875 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5876 std::pair<SDValue, SDValue> Res =
5877 TSI.EmitTargetCodeForMemcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5878 getValue(LHS), getValue(RHS), getValue(Size),
5879 MachinePointerInfo(LHS),
5880 MachinePointerInfo(RHS));
5881 if (Res.first.getNode()) {
5882 processIntegerCallValue(I, Res.first, true);
5883 PendingLoads.push_back(Res.second);
5884 return true;
5885 }
5886
5887 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0
5888 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0
5889 if (CSize && IsOnlyUsedInZeroEqualityComparison(&I)) {
5890 bool ActuallyDoIt = true;
5891 MVT LoadVT;
5892 Type *LoadTy;
5893 switch (CSize->getZExtValue()) {
5894 default:
5895 LoadVT = MVT::Other;
5896 LoadTy = nullptr;
5897 ActuallyDoIt = false;
5898 break;
5899 case 2:
5900 LoadVT = MVT::i16;
5901 LoadTy = Type::getInt16Ty(CSize->getContext());
5902 break;
5903 case 4:
5904 LoadVT = MVT::i32;
5905 LoadTy = Type::getInt32Ty(CSize->getContext());
5906 break;
5907 case 8:
5908 LoadVT = MVT::i64;
5909 LoadTy = Type::getInt64Ty(CSize->getContext());
5910 break;
5911 /*
5912 case 16:
5913 LoadVT = MVT::v4i32;
5914 LoadTy = Type::getInt32Ty(CSize->getContext());
5915 LoadTy = VectorType::get(LoadTy, 4);
5916 break;
5917 */
5918 }
5919
5920 // This turns into unaligned loads. We only do this if the target natively
5921 // supports the MVT we'll be loading or if it is small enough (<= 4) that
5922 // we'll only produce a small number of byte loads.
5923
5924 // Require that we can find a legal MVT, and only do this if the target
5925 // supports unaligned loads of that type. Expanding into byte loads would
5926 // bloat the code.
5927 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5928 if (ActuallyDoIt && CSize->getZExtValue() > 4) {
5929 unsigned DstAS = LHS->getType()->getPointerAddressSpace();
5930 unsigned SrcAS = RHS->getType()->getPointerAddressSpace();
5931 // TODO: Handle 5 byte compare as 4-byte + 1 byte.
5932 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads.
5933 // TODO: Check alignment of src and dest ptrs.
5934 if (!TLI.isTypeLegal(LoadVT) ||
5935 !TLI.allowsMisalignedMemoryAccesses(LoadVT, SrcAS) ||
5936 !TLI.allowsMisalignedMemoryAccesses(LoadVT, DstAS))
5937 ActuallyDoIt = false;
5938 }
5939
5940 if (ActuallyDoIt) {
5941 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this);
5942 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this);
5943
5944 SDValue Res = DAG.getSetCC(getCurSDLoc(), MVT::i1, LHSVal, RHSVal,
5945 ISD::SETNE);
5946 processIntegerCallValue(I, Res, false);
5947 return true;
5948 }
5949 }
5950
5951
5952 return false;
5953}
5954
5955/// visitMemChrCall -- See if we can lower a memchr call into an optimized
5956/// form. If so, return true and lower it, otherwise return false and it
5957/// will be lowered like a normal call.
5958bool SelectionDAGBuilder::visitMemChrCall(const CallInst &I) {
5959 // Verify that the prototype makes sense. void *memchr(void *, int, size_t)
5960 if (I.getNumArgOperands() != 3)
5961 return false;
5962
5963 const Value *Src = I.getArgOperand(0);
5964 const Value *Char = I.getArgOperand(1);
5965 const Value *Length = I.getArgOperand(2);
5966 if (!Src->getType()->isPointerTy() ||
5967 !Char->getType()->isIntegerTy() ||
5968 !Length->getType()->isIntegerTy() ||
5969 !I.getType()->isPointerTy())
5970 return false;
5971
5972 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5973 std::pair<SDValue, SDValue> Res =
5974 TSI.EmitTargetCodeForMemchr(DAG, getCurSDLoc(), DAG.getRoot(),
5975 getValue(Src), getValue(Char), getValue(Length),
5976 MachinePointerInfo(Src));
5977 if (Res.first.getNode()) {
5978 setValue(&I, Res.first);
5979 PendingLoads.push_back(Res.second);
5980 return true;
5981 }
5982
5983 return false;
5984}
5985
5986/// visitStrCpyCall -- See if we can lower a strcpy or stpcpy call into an
5987/// optimized form. If so, return true and lower it, otherwise return false
5988/// and it will be lowered like a normal call.
5989bool SelectionDAGBuilder::visitStrCpyCall(const CallInst &I, bool isStpcpy) {
5990 // Verify that the prototype makes sense. char *strcpy(char *, char *)
5991 if (I.getNumArgOperands() != 2)
5992 return false;
5993
5994 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5995 if (!Arg0->getType()->isPointerTy() ||
5996 !Arg1->getType()->isPointerTy() ||
5997 !I.getType()->isPointerTy())
5998 return false;
5999
6000 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
6001 std::pair<SDValue, SDValue> Res =
6002 TSI.EmitTargetCodeForStrcpy(DAG, getCurSDLoc(), getRoot(),
6003 getValue(Arg0), getValue(Arg1),
6004 MachinePointerInfo(Arg0),
6005 MachinePointerInfo(Arg1), isStpcpy);
6006 if (Res.first.getNode()) {
6007 setValue(&I, Res.first);
6008 DAG.setRoot(Res.second);
6009 return true;
6010 }
6011
6012 return false;
6013}
6014
6015/// visitStrCmpCall - See if we can lower a call to strcmp in an optimized form.
6016/// If so, return true and lower it, otherwise return false and it will be
6017/// lowered like a normal call.
6018bool SelectionDAGBuilder::visitStrCmpCall(const CallInst &I) {
6019 // Verify that the prototype makes sense. int strcmp(void*,void*)
6020 if (I.getNumArgOperands() != 2)
6021 return false;
6022
6023 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
6024 if (!Arg0->getType()->isPointerTy() ||
6025 !Arg1->getType()->isPointerTy() ||
6026 !I.getType()->isIntegerTy())
6027 return false;
6028
6029 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
6030 std::pair<SDValue, SDValue> Res =
6031 TSI.EmitTargetCodeForStrcmp(DAG, getCurSDLoc(), DAG.getRoot(),
6032 getValue(Arg0), getValue(Arg1),
6033 MachinePointerInfo(Arg0),
6034 MachinePointerInfo(Arg1));
6035 if (Res.first.getNode()) {
6036 processIntegerCallValue(I, Res.first, true);
6037 PendingLoads.push_back(Res.second);
6038 return true;
6039 }
6040
6041 return false;
6042}
6043
6044/// visitStrLenCall -- See if we can lower a strlen call into an optimized
6045/// form. If so, return true and lower it, otherwise return false and it
6046/// will be lowered like a normal call.
6047bool SelectionDAGBuilder::visitStrLenCall(const CallInst &I) {
6048 // Verify that the prototype makes sense. size_t strlen(char *)
6049 if (I.getNumArgOperands() != 1)
6050 return false;
6051
6052 const Value *Arg0 = I.getArgOperand(0);
6053 if (!Arg0->getType()->isPointerTy() || !I.getType()->isIntegerTy())
6054 return false;
6055
6056 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
6057 std::pair<SDValue, SDValue> Res =
6058 TSI.EmitTargetCodeForStrlen(DAG, getCurSDLoc(), DAG.getRoot(),
6059 getValue(Arg0), MachinePointerInfo(Arg0));
6060 if (Res.first.getNode()) {
6061 processIntegerCallValue(I, Res.first, false);
6062 PendingLoads.push_back(Res.second);
6063 return true;
6064 }
6065
6066 return false;
6067}
6068
6069/// visitStrNLenCall -- See if we can lower a strnlen call into an optimized
6070/// form. If so, return true and lower it, otherwise return false and it
6071/// will be lowered like a normal call.
6072bool SelectionDAGBuilder::visitStrNLenCall(const CallInst &I) {
6073 // Verify that the prototype makes sense. size_t strnlen(char *, size_t)
6074 if (I.getNumArgOperands() != 2)
6075 return false;
6076
6077 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
6078 if (!Arg0->getType()->isPointerTy() ||
6079 !Arg1->getType()->isIntegerTy() ||
6080 !I.getType()->isIntegerTy())
6081 return false;
6082
6083 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
6084 std::pair<SDValue, SDValue> Res =
6085 TSI.EmitTargetCodeForStrnlen(DAG, getCurSDLoc(), DAG.getRoot(),
6086 getValue(Arg0), getValue(Arg1),
6087 MachinePointerInfo(Arg0));
6088 if (Res.first.getNode()) {
6089 processIntegerCallValue(I, Res.first, false);
6090 PendingLoads.push_back(Res.second);
6091 return true;
6092 }
6093
6094 return false;
6095}
6096
6097/// visitUnaryFloatCall - If a call instruction is a unary floating-point
6098/// operation (as expected), translate it to an SDNode with the specified opcode
6099/// and return true.
6100bool SelectionDAGBuilder::visitUnaryFloatCall(const CallInst &I,
6101 unsigned Opcode) {
6102 // Sanity check that it really is a unary floating-point call.
6103 if (I.getNumArgOperands() != 1 ||
6104 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
6105 I.getType() != I.getArgOperand(0)->getType() ||
6106 !I.onlyReadsMemory())
6107 return false;
6108
6109 SDValue Tmp = getValue(I.getArgOperand(0));
6110 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), Tmp.getValueType(), Tmp));
6111 return true;
6112}
6113
6114/// visitBinaryFloatCall - If a call instruction is a binary floating-point
6115/// operation (as expected), translate it to an SDNode with the specified opcode
6116/// and return true.
6117bool SelectionDAGBuilder::visitBinaryFloatCall(const CallInst &I,
6118 unsigned Opcode) {
6119 // Sanity check that it really is a binary floating-point call.
6120 if (I.getNumArgOperands() != 2 ||
6121 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
6122 I.getType() != I.getArgOperand(0)->getType() ||
6123 I.getType() != I.getArgOperand(1)->getType() ||
6124 !I.onlyReadsMemory())
6125 return false;
6126
6127 SDValue Tmp0 = getValue(I.getArgOperand(0));
6128 SDValue Tmp1 = getValue(I.getArgOperand(1));
6129 EVT VT = Tmp0.getValueType();
6130 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), VT, Tmp0, Tmp1));
6131 return true;
6132}
6133
6134void SelectionDAGBuilder::visitCall(const CallInst &I) {
6135 // Handle inline assembly differently.
6136 if (isa<InlineAsm>(I.getCalledValue())) {
6137 visitInlineAsm(&I);
6138 return;
6139 }
6140
6141 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
6142 ComputeUsesVAFloatArgument(I, &MMI);
6143
6144 const char *RenameFn = nullptr;
6145 if (Function *F = I.getCalledFunction()) {
6146 if (F->isDeclaration()) {
6147 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) {
6148 if (unsigned IID = II->getIntrinsicID(F)) {
6149 RenameFn = visitIntrinsicCall(I, IID);
6150 if (!RenameFn)
6151 return;
6152 }
6153 }
6154 if (unsigned IID = F->getIntrinsicID()) {
6155 RenameFn = visitIntrinsicCall(I, IID);
6156 if (!RenameFn)
6157 return;
6158 }
6159 }
6160
6161 // Check for well-known libc/libm calls. If the function is internal, it
6162 // can't be a library call.
6163 LibFunc::Func Func;
6164 if (!F->hasLocalLinkage() && F->hasName() &&
6165 LibInfo->getLibFunc(F->getName(), Func) &&
6166 LibInfo->hasOptimizedCodeGen(Func)) {
6167 switch (Func) {
6168 default: break;
6169 case LibFunc::copysign:
6170 case LibFunc::copysignf:
6171 case LibFunc::copysignl:
6172 if (I.getNumArgOperands() == 2 && // Basic sanity checks.
6173 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
6174 I.getType() == I.getArgOperand(0)->getType() &&
6175 I.getType() == I.getArgOperand(1)->getType() &&
6176 I.onlyReadsMemory()) {
6177 SDValue LHS = getValue(I.getArgOperand(0));
6178 SDValue RHS = getValue(I.getArgOperand(1));
6179 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurSDLoc(),
6180 LHS.getValueType(), LHS, RHS));
6181 return;
6182 }
6183 break;
6184 case LibFunc::fabs:
6185 case LibFunc::fabsf:
6186 case LibFunc::fabsl:
6187 if (visitUnaryFloatCall(I, ISD::FABS))
6188 return;
6189 break;
6190 case LibFunc::fmin:
6191 case LibFunc::fminf:
6192 case LibFunc::fminl:
6193 if (visitBinaryFloatCall(I, ISD::FMINNUM))
6194 return;
6195 break;
6196 case LibFunc::fmax:
6197 case LibFunc::fmaxf:
6198 case LibFunc::fmaxl:
6199 if (visitBinaryFloatCall(I, ISD::FMAXNUM))
6200 return;
6201 break;
6202 case LibFunc::sin:
6203 case LibFunc::sinf:
6204 case LibFunc::sinl:
6205 if (visitUnaryFloatCall(I, ISD::FSIN))
6206 return;
6207 break;
6208 case LibFunc::cos:
6209 case LibFunc::cosf:
6210 case LibFunc::cosl:
6211 if (visitUnaryFloatCall(I, ISD::FCOS))
6212 return;
6213 break;
6214 case LibFunc::sqrt:
6215 case LibFunc::sqrtf:
6216 case LibFunc::sqrtl:
6217 case LibFunc::sqrt_finite:
6218 case LibFunc::sqrtf_finite:
6219 case LibFunc::sqrtl_finite:
6220 if (visitUnaryFloatCall(I, ISD::FSQRT))
6221 return;
6222 break;
6223 case LibFunc::floor:
6224 case LibFunc::floorf:
6225 case LibFunc::floorl:
6226 if (visitUnaryFloatCall(I, ISD::FFLOOR))
6227 return;
6228 break;
6229 case LibFunc::nearbyint:
6230 case LibFunc::nearbyintf:
6231 case LibFunc::nearbyintl:
6232 if (visitUnaryFloatCall(I, ISD::FNEARBYINT))
6233 return;
6234 break;
6235 case LibFunc::ceil:
6236 case LibFunc::ceilf:
6237 case LibFunc::ceill:
6238 if (visitUnaryFloatCall(I, ISD::FCEIL))
6239 return;
6240 break;
6241 case LibFunc::rint:
6242 case LibFunc::rintf:
6243 case LibFunc::rintl:
6244 if (visitUnaryFloatCall(I, ISD::FRINT))
6245 return;
6246 break;
6247 case LibFunc::round:
6248 case LibFunc::roundf:
6249 case LibFunc::roundl:
6250 if (visitUnaryFloatCall(I, ISD::FROUND))
6251 return;
6252 break;
6253 case LibFunc::trunc:
6254 case LibFunc::truncf:
6255 case LibFunc::truncl:
6256 if (visitUnaryFloatCall(I, ISD::FTRUNC))
6257 return;
6258 break;
6259 case LibFunc::log2:
6260 case LibFunc::log2f:
6261 case LibFunc::log2l:
6262 if (visitUnaryFloatCall(I, ISD::FLOG2))
6263 return;
6264 break;
6265 case LibFunc::exp2:
6266 case LibFunc::exp2f:
6267 case LibFunc::exp2l:
6268 if (visitUnaryFloatCall(I, ISD::FEXP2))
6269 return;
6270 break;
6271 case LibFunc::memcmp:
6272 if (visitMemCmpCall(I))
6273 return;
6274 break;
6275 case LibFunc::memchr:
6276 if (visitMemChrCall(I))
6277 return;
6278 break;
6279 case LibFunc::strcpy:
6280 if (visitStrCpyCall(I, false))
6281 return;
6282 break;
6283 case LibFunc::stpcpy:
6284 if (visitStrCpyCall(I, true))
6285 return;
6286 break;
6287 case LibFunc::strcmp:
6288 if (visitStrCmpCall(I))
6289 return;
6290 break;
6291 case LibFunc::strlen:
6292 if (visitStrLenCall(I))
6293 return;
6294 break;
6295 case LibFunc::strnlen:
6296 if (visitStrNLenCall(I))
6297 return;
6298 break;
6299 }
6300 }
6301 }
6302
6303 SDValue Callee;
6304 if (!RenameFn)
6305 Callee = getValue(I.getCalledValue());
6306 else
6307 Callee = DAG.getExternalSymbol(RenameFn,
6308 DAG.getTargetLoweringInfo().getPointerTy());
6309
6310 // Check if we can potentially perform a tail call. More detailed checking is
6311 // be done within LowerCallTo, after more information about the call is known.
6312 LowerCallTo(&I, Callee, I.isTailCall());
6313}
6314
6315namespace {
6316
6317/// AsmOperandInfo - This contains information for each constraint that we are
6318/// lowering.
6319class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
6320public:
6321 /// CallOperand - If this is the result output operand or a clobber
6322 /// this is null, otherwise it is the incoming operand to the CallInst.
6323 /// This gets modified as the asm is processed.
6324 SDValue CallOperand;
6325
6326 /// AssignedRegs - If this is a register or register class operand, this
6327 /// contains the set of register corresponding to the operand.
6328 RegsForValue AssignedRegs;
6329
6330 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info)
6331 : TargetLowering::AsmOperandInfo(info), CallOperand(nullptr,0) {
6332 }
6333
6334 /// getCallOperandValEVT - Return the EVT of the Value* that this operand
6335 /// corresponds to. If there is no Value* for this operand, it returns
6336 /// MVT::Other.
6337 EVT getCallOperandValEVT(LLVMContext &Context,
6338 const TargetLowering &TLI,
6339 const DataLayout *DL) const {
6340 if (!CallOperandVal) return MVT::Other;
6341
6342 if (isa<BasicBlock>(CallOperandVal))
6343 return TLI.getPointerTy();
6344
6345 llvm::Type *OpTy = CallOperandVal->getType();
6346
6347 // FIXME: code duplicated from TargetLowering::ParseConstraints().
6348 // If this is an indirect operand, the operand is a pointer to the
6349 // accessed type.
6350 if (isIndirect) {
6351 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
6352 if (!PtrTy)
6353 report_fatal_error("Indirect operand for inline asm not a pointer!");
6354 OpTy = PtrTy->getElementType();
6355 }
6356
6357 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
6358 if (StructType *STy = dyn_cast<StructType>(OpTy))
6359 if (STy->getNumElements() == 1)
6360 OpTy = STy->getElementType(0);
6361
6362 // If OpTy is not a single value, it may be a struct/union that we
6363 // can tile with integers.
6364 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
6365 unsigned BitSize = DL->getTypeSizeInBits(OpTy);
6366 switch (BitSize) {
6367 default: break;
6368 case 1:
6369 case 8:
6370 case 16:
6371 case 32:
6372 case 64:
6373 case 128:
6374 OpTy = IntegerType::get(Context, BitSize);
6375 break;
6376 }
6377 }
6378
6379 return TLI.getValueType(OpTy, true);
6380 }
6381};
6382
6383typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector;
6384
6385} // end anonymous namespace
6386
6387/// GetRegistersForValue - Assign registers (virtual or physical) for the
6388/// specified operand. We prefer to assign virtual registers, to allow the
6389/// register allocator to handle the assignment process. However, if the asm
6390/// uses features that we can't model on machineinstrs, we have SDISel do the
6391/// allocation. This produces generally horrible, but correct, code.
6392///
6393/// OpInfo describes the operand.
6394///
6395static void GetRegistersForValue(SelectionDAG &DAG,
6396 const TargetLowering &TLI,
6397 SDLoc DL,
6398 SDISelAsmOperandInfo &OpInfo) {
6399 LLVMContext &Context = *DAG.getContext();
6400
6401 MachineFunction &MF = DAG.getMachineFunction();
6402 SmallVector<unsigned, 4> Regs;
6403
6404 // If this is a constraint for a single physreg, or a constraint for a
6405 // register class, find it.
6406 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
6407 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
1
Value assigned to 'PhysReg.second'
→
6408 OpInfo.ConstraintVT);
6409
6410 unsigned NumRegs = 1;
6411 if (OpInfo.ConstraintVT != MVT::Other) {
2
←
Taking true branch
→
6412 // If this is a FP input in an integer register (or visa versa) insert a bit
6413 // cast of the input value. More generally, handle any case where the input
6414 // value disagrees with the register class we plan to stick this in.
6415 if (OpInfo.Type == InlineAsm::isInput &&
3
←
Assuming pointer value is null
→
6416 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
6417 // Try to convert to the first EVT that the reg class contains. If the
6418 // types are identical size, use a bitcast to convert (e.g. two differing
6419 // vector types).
6420 MVT RegVT = *PhysReg.second->vt_begin();
6421 if (RegVT.getSizeInBits() == OpInfo.CallOperand.getValueSizeInBits()) {
6422 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
6423 RegVT, OpInfo.CallOperand);
6424 OpInfo.ConstraintVT = RegVT;
6425 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
6426 // If the input is a FP value and we want it in FP registers, do a
6427 // bitcast to the corresponding integer type. This turns an f64 value
6428 // into i64, which can be passed with two i32 values on a 32-bit
6429 // machine.
6430 RegVT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits());
6431 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
6432 RegVT, OpInfo.CallOperand);
6433 OpInfo.ConstraintVT = RegVT;
6434 }
6435 }
6436
6437 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
6438 }
6439
6440 MVT RegVT;
6441 EVT ValueVT = OpInfo.ConstraintVT;
6442
6443 // If this is a constraint for a specific physical register, like {r17},
6444 // assign it now.
6445 if (unsigned AssignedReg = PhysReg.first) {
4
←
Assuming 'AssignedReg' is not equal to 0
→
5
←
Taking true branch
→
6446 const TargetRegisterClass *RC = PhysReg.second;
6
←
'RC' initialized to a null pointer value
→
6447 if (OpInfo.ConstraintVT == MVT::Other)
7
←
Taking false branch
→
6448 ValueVT = *RC->vt_begin();
6449
6450 // Get the actual register value type. This is important, because the user
6451 // may have asked for (e.g.) the AX register in i32 type. We need to
6452 // remember that AX is actually i16 to get the right extension.
6453 RegVT = *RC->vt_begin();
8
←
Called C++ object pointer is null
6454
6455 // This is a explicit reference to a physical register.
6456 Regs.push_back(AssignedReg);
6457
6458 // If this is an expanded reference, add the rest of the regs to Regs.
6459 if (NumRegs != 1) {
6460 TargetRegisterClass::iterator I = RC->begin();
6461 for (; *I != AssignedReg; ++I)
6462 assert(I != RC->end() && "Didn't find reg!")((I != RC->end() && "Didn't find reg!") ? static_cast
<void> (0) : __assert_fail ("I != RC->end() && \"Didn't find reg!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 6462, __PRETTY_FUNCTION__));
6463
6464 // Already added the first reg.
6465 --NumRegs; ++I;
6466 for (; NumRegs; --NumRegs, ++I) {
6467 assert(I != RC->end() && "Ran out of registers to allocate!")((I != RC->end() && "Ran out of registers to allocate!"
) ? static_cast<void> (0) : __assert_fail ("I != RC->end() && \"Ran out of registers to allocate!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 6467, __PRETTY_FUNCTION__));
6468 Regs.push_back(*I);
6469 }
6470 }
6471
6472 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
6473 return;
6474 }
6475
6476 // Otherwise, if this was a reference to an LLVM register class, create vregs
6477 // for this reference.
6478 if (const TargetRegisterClass *RC = PhysReg.second) {
6479 RegVT = *RC->vt_begin();
6480 if (OpInfo.ConstraintVT == MVT::Other)
6481 ValueVT = RegVT;
6482
6483 // Create the appropriate number of virtual registers.
6484 MachineRegisterInfo &RegInfo = MF.getRegInfo();
6485 for (; NumRegs; --NumRegs)
6486 Regs.push_back(RegInfo.createVirtualRegister(RC));
6487
6488 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
6489 return;
6490 }
6491
6492 // Otherwise, we couldn't allocate enough registers for this.
6493}
6494
6495/// visitInlineAsm - Handle a call to an InlineAsm object.
6496///
6497void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
6498 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
6499
6500 /// ConstraintOperands - Information about all of the constraints.
6501 SDISelAsmOperandInfoVector ConstraintOperands;
6502
6503 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6504 TargetLowering::AsmOperandInfoVector
6505 TargetConstraints = TLI.ParseConstraints(CS);
6506
6507 bool hasMemory = false;
6508
6509 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
6510 unsigned ResNo = 0; // ResNo - The result number of the next output.
6511 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
6512 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i]));
6513 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
6514
6515 MVT OpVT = MVT::Other;
6516
6517 // Compute the value type for each operand.
6518 switch (OpInfo.Type) {
6519 case InlineAsm::isOutput:
6520 // Indirect outputs just consume an argument.
6521 if (OpInfo.isIndirect) {
6522 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
6523 break;
6524 }
6525
6526 // The return value of the call is this value. As such, there is no
6527 // corresponding argument.
6528 assert(!CS.getType()->isVoidTy() && "Bad inline asm!")((!CS.getType()->isVoidTy() && "Bad inline asm!") ?
static_cast<void> (0) : __assert_fail ("!CS.getType()->isVoidTy() && \"Bad inline asm!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 6528, __PRETTY_FUNCTION__));
6529 if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
6530 OpVT = TLI.getSimpleValueType(STy->getElementType(ResNo));
6531 } else {
6532 assert(ResNo == 0 && "Asm only has one result!")((ResNo == 0 && "Asm only has one result!") ? static_cast
<void> (0) : __assert_fail ("ResNo == 0 && \"Asm only has one result!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 6532, __PRETTY_FUNCTION__));
6533 OpVT = TLI.getSimpleValueType(CS.getType());
6534 }
6535 ++ResNo;
6536 break;
6537 case InlineAsm::isInput:
6538 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
6539 break;
6540 case InlineAsm::isClobber:
6541 // Nothing to do.
6542 break;
6543 }
6544
6545 // If this is an input or an indirect output, process the call argument.
6546 // BasicBlocks are labels, currently appearing only in asm's.
6547 if (OpInfo.CallOperandVal) {
6548 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
6549 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
6550 } else {
6551 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
6552 }
6553
6554 OpVT =
6555 OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI, DL).getSimpleVT();
6556 }
6557
6558 OpInfo.ConstraintVT = OpVT;
6559
6560 // Indirect operand accesses access memory.
6561 if (OpInfo.isIndirect)
6562 hasMemory = true;
6563 else {
6564 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) {
6565 TargetLowering::ConstraintType
6566 CType = TLI.getConstraintType(OpInfo.Codes[j]);
6567 if (CType == TargetLowering::C_Memory) {
6568 hasMemory = true;
6569 break;
6570 }
6571 }
6572 }
6573 }
6574
6575 SDValue Chain, Flag;
6576
6577 // We won't need to flush pending loads if this asm doesn't touch
6578 // memory and is nonvolatile.
6579 if (hasMemory || IA->hasSideEffects())
6580 Chain = getRoot();
6581 else
6582 Chain = DAG.getRoot();
6583
6584 // Second pass over the constraints: compute which constraint option to use
6585 // and assign registers to constraints that want a specific physreg.
6586 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6587 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6588
6589 // If this is an output operand with a matching input operand, look up the
6590 // matching input. If their types mismatch, e.g. one is an integer, the
6591 // other is floating point, or their sizes are different, flag it as an
6592 // error.
6593 if (OpInfo.hasMatchingInput()) {
6594 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
6595
6596 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
6597 std::pair<unsigned, const TargetRegisterClass*> MatchRC =
6598 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
6599 OpInfo.ConstraintVT);
6600 std::pair<unsigned, const TargetRegisterClass*> InputRC =
6601 TLI.getRegForInlineAsmConstraint(Input.ConstraintCode,
6602 Input.ConstraintVT);
6603 if ((OpInfo.ConstraintVT.isInteger() !=
6604 Input.ConstraintVT.isInteger()) ||
6605 (MatchRC.second != InputRC.second)) {
6606 report_fatal_error("Unsupported asm: input constraint"
6607 " with a matching output constraint of"
6608 " incompatible type!");
6609 }
6610 Input.ConstraintVT = OpInfo.ConstraintVT;
6611 }
6612 }
6613
6614 // Compute the constraint code and ConstraintType to use.
6615 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
6616
6617 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
6618 OpInfo.Type == InlineAsm::isClobber)
6619 continue;
6620
6621 // If this is a memory input, and if the operand is not indirect, do what we
6622 // need to to provide an address for the memory input.
6623 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
6624 !OpInfo.isIndirect) {
6625 assert((OpInfo.isMultipleAlternative ||(((OpInfo.isMultipleAlternative || (OpInfo.Type == InlineAsm::
isInput)) && "Can only indirectify direct input operands!"
) ? static_cast<void> (0) : __assert_fail ("(OpInfo.isMultipleAlternative || (OpInfo.Type == InlineAsm::isInput)) && \"Can only indirectify direct input operands!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 6627, __PRETTY_FUNCTION__))
6626 (OpInfo.Type == InlineAsm::isInput)) &&(((OpInfo.isMultipleAlternative || (OpInfo.Type == InlineAsm::
isInput)) && "Can only indirectify direct input operands!"
) ? static_cast<void> (0) : __assert_fail ("(OpInfo.isMultipleAlternative || (OpInfo.Type == InlineAsm::isInput)) && \"Can only indirectify direct input operands!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 6627, __PRETTY_FUNCTION__))
6627 "Can only indirectify direct input operands!")(((OpInfo.isMultipleAlternative || (OpInfo.Type == InlineAsm::
isInput)) && "Can only indirectify direct input operands!"
) ? static_cast<void> (0) : __assert_fail ("(OpInfo.isMultipleAlternative || (OpInfo.Type == InlineAsm::isInput)) && \"Can only indirectify direct input operands!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 6627, __PRETTY_FUNCTION__));
6628
6629 // Memory operands really want the address of the value. If we don't have
6630 // an indirect input, put it in the constpool if we can, otherwise spill
6631 // it to a stack slot.
6632 // TODO: This isn't quite right. We need to handle these according to
6633 // the addressing mode that the constraint wants. Also, this may take
6634 // an additional register for the computation and we don't want that
6635 // either.
6636
6637 // If the operand is a float, integer, or vector constant, spill to a
6638 // constant pool entry to get its address.
6639 const Value *OpVal = OpInfo.CallOperandVal;
6640 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
6641 isa<ConstantVector>(OpVal) || isa<ConstantDataVector>(OpVal)) {
6642 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
6643 TLI.getPointerTy());
6644 } else {
6645 // Otherwise, create a stack slot and emit a store to it before the
6646 // asm.
6647 Type *Ty = OpVal->getType();
6648 uint64_t TySize = TLI.getDataLayout()->getTypeAllocSize(Ty);
6649 unsigned Align = TLI.getDataLayout()->getPrefTypeAlignment(Ty);
6650 MachineFunction &MF = DAG.getMachineFunction();
6651 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
6652 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
6653 Chain = DAG.getStore(Chain, getCurSDLoc(),
6654 OpInfo.CallOperand, StackSlot,
6655 MachinePointerInfo::getFixedStack(SSFI),
6656 false, false, 0);
6657 OpInfo.CallOperand = StackSlot;
6658 }
6659
6660 // There is no longer a Value* corresponding to this operand.
6661 OpInfo.CallOperandVal = nullptr;
6662
6663 // It is now an indirect operand.
6664 OpInfo.isIndirect = true;
6665 }
6666
6667 // If this constraint is for a specific register, allocate it before
6668 // anything else.
6669 if (OpInfo.ConstraintType == TargetLowering::C_Register)
6670 GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
6671 }
6672
6673 // Second pass - Loop over all of the operands, assigning virtual or physregs
6674 // to register class operands.
6675 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6676 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6677
6678 // C_Register operands have already been allocated, Other/Memory don't need
6679 // to be.
6680 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
6681 GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
6682 }
6683
6684 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
6685 std::vector<SDValue> AsmNodeOperands;
6686 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
6687 AsmNodeOperands.push_back(
6688 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(),
6689 TLI.getPointerTy()));
6690
6691 // If we have a !srcloc metadata node associated with it, we want to attach
6692 // this to the ultimately generated inline asm machineinstr. To do this, we
6693 // pass in the third operand as this (potentially null) inline asm MDNode.
6694 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc");
6695 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc));
6696
6697 // Remember the HasSideEffect, AlignStack, AsmDialect, MayLoad and MayStore
6698 // bits as operand 3.
6699 unsigned ExtraInfo = 0;
6700 if (IA->hasSideEffects())
6701 ExtraInfo |= InlineAsm::Extra_HasSideEffects;
6702 if (IA->isAlignStack())
6703 ExtraInfo |= InlineAsm::Extra_IsAlignStack;
6704 // Set the asm dialect.
6705 ExtraInfo |= IA->getDialect() * InlineAsm::Extra_AsmDialect;
6706
6707 // Determine if this InlineAsm MayLoad or MayStore based on the constraints.
6708 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
6709 TargetLowering::AsmOperandInfo &OpInfo = TargetConstraints[i];
6710
6711 // Compute the constraint code and ConstraintType to use.
6712 TLI.ComputeConstraintToUse(OpInfo, SDValue());
6713
6714 // Ideally, we would only check against memory constraints. However, the
6715 // meaning of an other constraint can be target-specific and we can't easily
6716 // reason about it. Therefore, be conservative and set MayLoad/MayStore
6717 // for other constriants as well.
6718 if (OpInfo.ConstraintType == TargetLowering::C_Memory ||
6719 OpInfo.ConstraintType == TargetLowering::C_Other) {
6720 if (OpInfo.Type == InlineAsm::isInput)
6721 ExtraInfo |= InlineAsm::Extra_MayLoad;
6722 else if (OpInfo.Type == InlineAsm::isOutput)
6723 ExtraInfo |= InlineAsm::Extra_MayStore;
6724 else if (OpInfo.Type == InlineAsm::isClobber)
6725 ExtraInfo |= (InlineAsm::Extra_MayLoad | InlineAsm::Extra_MayStore);
6726 }
6727 }
6728
6729 AsmNodeOperands.push_back(DAG.getTargetConstant(ExtraInfo,
6730 TLI.getPointerTy()));
6731
6732 // Loop over all of the inputs, copying the operand values into the
6733 // appropriate registers and processing the output regs.
6734 RegsForValue RetValRegs;
6735
6736 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
6737 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
6738
6739 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6740 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6741
6742 switch (OpInfo.Type) {
6743 case InlineAsm::isOutput: {
6744 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
6745 OpInfo.ConstraintType != TargetLowering::C_Register) {
6746 // Memory output, or 'other' output (e.g. 'X' constraint).
6747 assert(OpInfo.isIndirect && "Memory output must be indirect operand")((OpInfo.isIndirect && "Memory output must be indirect operand"
) ? static_cast<void> (0) : __assert_fail ("OpInfo.isIndirect && \"Memory output must be indirect operand\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 6747, __PRETTY_FUNCTION__));
6748
6749 // Add information to the INLINEASM node to know about this output.
6750 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6751 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags,
6752 TLI.getPointerTy()));
6753 AsmNodeOperands.push_back(OpInfo.CallOperand);
6754 break;
6755 }
6756
6757 // Otherwise, this is a register or register class output.
6758
6759 // Copy the output from the appropriate register. Find a register that
6760 // we can use.
6761 if (OpInfo.AssignedRegs.Regs.empty()) {
6762 LLVMContext &Ctx = *DAG.getContext();
6763 Ctx.emitError(CS.getInstruction(),
6764 "couldn't allocate output register for constraint '" +
6765 Twine(OpInfo.ConstraintCode) + "'");
6766 return;
6767 }
6768
6769 // If this is an indirect operand, store through the pointer after the
6770 // asm.
6771 if (OpInfo.isIndirect) {
6772 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
6773 OpInfo.CallOperandVal));
6774 } else {
6775 // This is the result value of the call.
6776 assert(!CS.getType()->isVoidTy() && "Bad inline asm!")((!CS.getType()->isVoidTy() && "Bad inline asm!") ?
static_cast<void> (0) : __assert_fail ("!CS.getType()->isVoidTy() && \"Bad inline asm!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 6776, __PRETTY_FUNCTION__));
6777 // Concatenate this output onto the outputs list.
6778 RetValRegs.append(OpInfo.AssignedRegs);
6779 }
6780
6781 // Add information to the INLINEASM node to know that this register is
6782 // set.
6783 OpInfo.AssignedRegs
6784 .AddInlineAsmOperands(OpInfo.isEarlyClobber
6785 ? InlineAsm::Kind_RegDefEarlyClobber
6786 : InlineAsm::Kind_RegDef,
6787 false, 0, DAG, AsmNodeOperands);
6788 break;
6789 }
6790 case InlineAsm::isInput: {
6791 SDValue InOperandVal = OpInfo.CallOperand;
6792
6793 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
6794 // If this is required to match an output register we have already set,
6795 // just use its register.
6796 unsigned OperandNo = OpInfo.getMatchedOperand();
6797
6798 // Scan until we find the definition we already emitted of this operand.
6799 // When we find it, create a RegsForValue operand.
6800 unsigned CurOp = InlineAsm::Op_FirstOperand;
6801 for (; OperandNo; --OperandNo) {
6802 // Advance to the next operand.
6803 unsigned OpFlag =
6804 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6805 assert((InlineAsm::isRegDefKind(OpFlag) ||(((InlineAsm::isRegDefKind(OpFlag) || InlineAsm::isRegDefEarlyClobberKind
(OpFlag) || InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?"
) ? static_cast<void> (0) : __assert_fail ("(InlineAsm::isRegDefKind(OpFlag) || InlineAsm::isRegDefEarlyClobberKind(OpFlag) || InlineAsm::isMemKind(OpFlag)) && \"Skipped past definitions?\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 6807, __PRETTY_FUNCTION__))
6806 InlineAsm::isRegDefEarlyClobberKind(OpFlag) ||(((InlineAsm::isRegDefKind(OpFlag) || InlineAsm::isRegDefEarlyClobberKind
(OpFlag) || InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?"
) ? static_cast<void> (0) : __assert_fail ("(InlineAsm::isRegDefKind(OpFlag) || InlineAsm::isRegDefEarlyClobberKind(OpFlag) || InlineAsm::isMemKind(OpFlag)) && \"Skipped past definitions?\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 6807, __PRETTY_FUNCTION__))
6807 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?")(((InlineAsm::isRegDefKind(OpFlag) || InlineAsm::isRegDefEarlyClobberKind
(OpFlag) || InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?"
) ? static_cast<void> (0) : __assert_fail ("(InlineAsm::isRegDefKind(OpFlag) || InlineAsm::isRegDefEarlyClobberKind(OpFlag) || InlineAsm::isMemKind(OpFlag)) && \"Skipped past definitions?\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 6807, __PRETTY_FUNCTION__));
6808 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
6809 }
6810
6811 unsigned OpFlag =
6812 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6813 if (InlineAsm::isRegDefKind(OpFlag) ||
6814 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) {
6815 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
6816 if (OpInfo.isIndirect) {
6817 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c
6818 LLVMContext &Ctx = *DAG.getContext();
6819 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:"
6820 " don't know how to handle tied "
6821 "indirect register inputs");
6822 return;
6823 }
6824
6825 RegsForValue MatchedRegs;
6826 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
6827 MVT RegVT = AsmNodeOperands[CurOp+1].getSimpleValueType();
6828 MatchedRegs.RegVTs.push_back(RegVT);
6829 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
6830 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
6831 i != e; ++i) {
6832 if (const TargetRegisterClass *RC = TLI.getRegClassFor(RegVT))
6833 MatchedRegs.Regs.push_back(RegInfo.createVirtualRegister(RC));
6834 else {
6835 LLVMContext &Ctx = *DAG.getContext();
6836 Ctx.emitError(CS.getInstruction(),
6837 "inline asm error: This value"
6838 " type register class is not natively supported!");
6839 return;
6840 }
6841 }
6842 // Use the produced MatchedRegs object to
6843 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurSDLoc(),
6844 Chain, &Flag, CS.getInstruction());
6845 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse,
6846 true, OpInfo.getMatchedOperand(),
6847 DAG, AsmNodeOperands);
6848 break;
6849 }
6850
6851 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!")((InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!"
) ? static_cast<void> (0) : __assert_fail ("InlineAsm::isMemKind(OpFlag) && \"Unknown matching constraint!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 6851, __PRETTY_FUNCTION__));
6852 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 &&((InlineAsm::getNumOperandRegisters(OpFlag) == 1 && "Unexpected number of operands"
) ? static_cast<void> (0) : __assert_fail ("InlineAsm::getNumOperandRegisters(OpFlag) == 1 && \"Unexpected number of operands\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 6853, __PRETTY_FUNCTION__))
6853 "Unexpected number of operands")((InlineAsm::getNumOperandRegisters(OpFlag) == 1 && "Unexpected number of operands"
) ? static_cast<void> (0) : __assert_fail ("InlineAsm::getNumOperandRegisters(OpFlag) == 1 && \"Unexpected number of operands\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 6853, __PRETTY_FUNCTION__));
6854 // Add information to the INLINEASM node to know about this input.
6855 // See InlineAsm.h isUseOperandTiedToDef.
6856 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag,
6857 OpInfo.getMatchedOperand());
6858 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag,
6859 TLI.getPointerTy()));
6860 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
6861 break;
6862 }
6863
6864 // Treat indirect 'X' constraint as memory.
6865 if (OpInfo.ConstraintType == TargetLowering::C_Other &&
6866 OpInfo.isIndirect)
6867 OpInfo.ConstraintType = TargetLowering::C_Memory;
6868
6869 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
6870 std::vector<SDValue> Ops;
6871 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode,
6872 Ops, DAG);
6873 if (Ops.empty()) {
6874 LLVMContext &Ctx = *DAG.getContext();
6875 Ctx.emitError(CS.getInstruction(),
6876 "invalid operand for inline asm constraint '" +
6877 Twine(OpInfo.ConstraintCode) + "'");
6878 return;
6879 }
6880
6881 // Add information to the INLINEASM node to know about this input.
6882 unsigned ResOpType =
6883 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
6884 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6885 TLI.getPointerTy()));
6886 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
6887 break;
6888 }
6889
6890 if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
6891 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!")((OpInfo.isIndirect && "Operand must be indirect to be a mem!"
) ? static_cast<void> (0) : __assert_fail ("OpInfo.isIndirect && \"Operand must be indirect to be a mem!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 6891, __PRETTY_FUNCTION__));
6892 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&((InOperandVal.getValueType() == TLI.getPointerTy() &&
"Memory operands expect pointer values") ? static_cast<void
> (0) : __assert_fail ("InOperandVal.getValueType() == TLI.getPointerTy() && \"Memory operands expect pointer values\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 6893, __PRETTY_FUNCTION__))
6893 "Memory operands expect pointer values")((InOperandVal.getValueType() == TLI.getPointerTy() &&
"Memory operands expect pointer values") ? static_cast<void
> (0) : __assert_fail ("InOperandVal.getValueType() == TLI.getPointerTy() && \"Memory operands expect pointer values\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 6893, __PRETTY_FUNCTION__));
6894
6895 // Add information to the INLINEASM node to know about this input.
6896 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6897 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6898 TLI.getPointerTy()));
6899 AsmNodeOperands.push_back(InOperandVal);
6900 break;
6901 }
6902
6903 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||(((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
OpInfo.ConstraintType == TargetLowering::C_Register) &&
"Unknown constraint type!") ? static_cast<void> (0) : __assert_fail
("(OpInfo.ConstraintType == TargetLowering::C_RegisterClass || OpInfo.ConstraintType == TargetLowering::C_Register) && \"Unknown constraint type!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 6905, __PRETTY_FUNCTION__))
6904 OpInfo.ConstraintType == TargetLowering::C_Register) &&(((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
OpInfo.ConstraintType == TargetLowering::C_Register) &&
"Unknown constraint type!") ? static_cast<void> (0) : __assert_fail
("(OpInfo.ConstraintType == TargetLowering::C_RegisterClass || OpInfo.ConstraintType == TargetLowering::C_Register) && \"Unknown constraint type!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 6905, __PRETTY_FUNCTION__))
6905 "Unknown constraint type!")(((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
OpInfo.ConstraintType == TargetLowering::C_Register) &&
"Unknown constraint type!") ? static_cast<void> (0) : __assert_fail
("(OpInfo.ConstraintType == TargetLowering::C_RegisterClass || OpInfo.ConstraintType == TargetLowering::C_Register) && \"Unknown constraint type!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 6905, __PRETTY_FUNCTION__));
6906
6907 // TODO: Support this.
6908 if (OpInfo.isIndirect) {
6909 LLVMContext &Ctx = *DAG.getContext();
6910 Ctx.emitError(CS.getInstruction(),
6911 "Don't know how to handle indirect register inputs yet "
6912 "for constraint '" +
6913 Twine(OpInfo.ConstraintCode) + "'");
6914 return;
6915 }
6916
6917 // Copy the input into the appropriate registers.
6918 if (OpInfo.AssignedRegs.Regs.empty()) {
6919 LLVMContext &Ctx = *DAG.getContext();
6920 Ctx.emitError(CS.getInstruction(),
6921 "couldn't allocate input reg for constraint '" +
6922 Twine(OpInfo.ConstraintCode) + "'");
6923 return;
6924 }
6925
6926 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurSDLoc(),
6927 Chain, &Flag, CS.getInstruction());
6928
6929 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0,
6930 DAG, AsmNodeOperands);
6931 break;
6932 }
6933 case InlineAsm::isClobber: {
6934 // Add the clobbered value to the operand list, so that the register
6935 // allocator is aware that the physreg got clobbered.
6936 if (!OpInfo.AssignedRegs.Regs.empty())
6937 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber,
6938 false, 0, DAG,
6939 AsmNodeOperands);
6940 break;
6941 }
6942 }
6943 }
6944
6945 // Finish up input operands. Set the input chain and add the flag last.
6946 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
6947 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
6948
6949 Chain = DAG.getNode(ISD::INLINEASM, getCurSDLoc(),
6950 DAG.getVTList(MVT::Other, MVT::Glue), AsmNodeOperands);
6951 Flag = Chain.getValue(1);
6952
6953 // If this asm returns a register value, copy the result from that register
6954 // and set it as the value of the call.
6955 if (!RetValRegs.Regs.empty()) {
6956 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6957 Chain, &Flag, CS.getInstruction());
6958
6959 // FIXME: Why don't we do this for inline asms with MRVs?
6960 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
6961 EVT ResultType = TLI.getValueType(CS.getType());
6962
6963 // If any of the results of the inline asm is a vector, it may have the
6964 // wrong width/num elts. This can happen for register classes that can
6965 // contain multiple different value types. The preg or vreg allocated may
6966 // not have the same VT as was expected. Convert it to the right type
6967 // with bit_convert.
6968 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
6969 Val = DAG.getNode(ISD::BITCAST, getCurSDLoc(),
6970 ResultType, Val);
6971
6972 } else if (ResultType != Val.getValueType() &&
6973 ResultType.isInteger() && Val.getValueType().isInteger()) {
6974 // If a result value was tied to an input value, the computed result may
6975 // have a wider width than the expected result. Extract the relevant
6976 // portion.
6977 Val = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), ResultType, Val);
6978 }
6979
6980 assert(ResultType == Val.getValueType() && "Asm result value mismatch!")((ResultType == Val.getValueType() && "Asm result value mismatch!"
) ? static_cast<void> (0) : __assert_fail ("ResultType == Val.getValueType() && \"Asm result value mismatch!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 6980, __PRETTY_FUNCTION__));
6981 }
6982
6983 setValue(CS.getInstruction(), Val);
6984 // Don't need to use this as a chain in this case.
6985 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
6986 return;
6987 }
6988
6989 std::vector<std::pair<SDValue, const Value *> > StoresToEmit;
6990
6991 // Process indirect outputs, first output all of the flagged copies out of
6992 // physregs.
6993 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
6994 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
6995 const Value *Ptr = IndirectStoresToEmit[i].second;
6996 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6997 Chain, &Flag, IA);
6998 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
6999 }
7000
7001 // Emit the non-flagged stores from the physregs.
7002 SmallVector<SDValue, 8> OutChains;
7003 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) {
7004 SDValue Val = DAG.getStore(Chain, getCurSDLoc(),
7005 StoresToEmit[i].first,
7006 getValue(StoresToEmit[i].second),
7007 MachinePointerInfo(StoresToEmit[i].second),
7008 false, false, 0);
7009 OutChains.push_back(Val);
7010 }
7011
7012 if (!OutChains.empty())
7013 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other, OutChains);
7014
7015 DAG.setRoot(Chain);
7016}
7017
7018void SelectionDAGBuilder::visitVAStart(const CallInst &I) {
7019 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurSDLoc(),
7020 MVT::Other, getRoot(),
7021 getValue(I.getArgOperand(0)),
7022 DAG.getSrcValue(I.getArgOperand(0))));
7023}
7024
7025void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) {
7026 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7027 const DataLayout &DL = *TLI.getDataLayout();
7028 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurSDLoc(),
7029 getRoot(), getValue(I.getOperand(0)),
7030 DAG.getSrcValue(I.getOperand(0)),
7031 DL.getABITypeAlignment(I.getType()));
7032 setValue(&I, V);
7033 DAG.setRoot(V.getValue(1));
7034}
7035
7036void SelectionDAGBuilder::visitVAEnd(const CallInst &I) {
7037 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurSDLoc(),
7038 MVT::Other, getRoot(),
7039 getValue(I.getArgOperand(0)),
7040 DAG.getSrcValue(I.getArgOperand(0))));
7041}
7042
7043void SelectionDAGBuilder::visitVACopy(const CallInst &I) {
7044 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurSDLoc(),
7045 MVT::Other, getRoot(),
7046 getValue(I.getArgOperand(0)),
7047 getValue(I.getArgOperand(1)),
7048 DAG.getSrcValue(I.getArgOperand(0)),
7049 DAG.getSrcValue(I.getArgOperand(1))));
7050}
7051
7052/// \brief Lower an argument list according to the target calling convention.
7053///
7054/// \return A tuple of <return-value, token-chain>
7055///
7056/// This is a helper for lowering intrinsics that follow a target calling
7057/// convention or require stack pointer adjustment. Only a subset of the
7058/// intrinsic's operands need to participate in the calling convention.
7059std::pair<SDValue, SDValue>
7060SelectionDAGBuilder::lowerCallOperands(ImmutableCallSite CS, unsigned ArgIdx,
7061 unsigned NumArgs, SDValue Callee,
7062 bool UseVoidTy,
7063 MachineBasicBlock *LandingPad,
7064 bool IsPatchPoint) {
7065 TargetLowering::ArgListTy Args;
7066 Args.reserve(NumArgs);
7067
7068 // Populate the argument list.
7069 // Attributes for args start at offset 1, after the return attribute.
7070 for (unsigned ArgI = ArgIdx, ArgE = ArgIdx + NumArgs, AttrI = ArgIdx + 1;
7071 ArgI != ArgE; ++ArgI) {
7072 const Value *V = CS->getOperand(ArgI);
7073
7074 assert(!V->getType()->isEmptyTy() && "Empty type passed to intrinsic.")((!V->getType()->isEmptyTy() && "Empty type passed to intrinsic."
) ? static_cast<void> (0) : __assert_fail ("!V->getType()->isEmptyTy() && \"Empty type passed to intrinsic.\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7074, __PRETTY_FUNCTION__));
7075
7076 TargetLowering::ArgListEntry Entry;
7077 Entry.Node = getValue(V);
7078 Entry.Ty = V->getType();
7079 Entry.setAttributes(&CS, AttrI);
7080 Args.push_back(Entry);
7081 }
7082
7083 Type *retTy = UseVoidTy ? Type::getVoidTy(*DAG.getContext()) : CS->getType();
7084 TargetLowering::CallLoweringInfo CLI(DAG);
7085 CLI.setDebugLoc(getCurSDLoc()).setChain(getRoot())
7086 .setCallee(CS.getCallingConv(), retTy, Callee, std::move(Args), NumArgs)
7087 .setDiscardResult(CS->use_empty()).setIsPatchPoint(IsPatchPoint);
7088
7089 return lowerInvokable(CLI, LandingPad);
7090}
7091
7092/// \brief Add a stack map intrinsic call's live variable operands to a stackmap
7093/// or patchpoint target node's operand list.
7094///
7095/// Constants are converted to TargetConstants purely as an optimization to
7096/// avoid constant materialization and register allocation.
7097///
7098/// FrameIndex operands are converted to TargetFrameIndex so that ISEL does not
7099/// generate addess computation nodes, and so ExpandISelPseudo can convert the
7100/// TargetFrameIndex into a DirectMemRefOp StackMap location. This avoids
7101/// address materialization and register allocation, but may also be required
7102/// for correctness. If a StackMap (or PatchPoint) intrinsic directly uses an
7103/// alloca in the entry block, then the runtime may assume that the alloca's
7104/// StackMap location can be read immediately after compilation and that the
7105/// location is valid at any point during execution (this is similar to the
7106/// assumption made by the llvm.gcroot intrinsic). If the alloca's location were
7107/// only available in a register, then the runtime would need to trap when
7108/// execution reaches the StackMap in order to read the alloca's location.
7109static void addStackMapLiveVars(ImmutableCallSite CS, unsigned StartIdx,
7110 SmallVectorImpl<SDValue> &Ops,
7111 SelectionDAGBuilder &Builder) {
7112 for (unsigned i = StartIdx, e = CS.arg_size(); i != e; ++i) {
7113 SDValue OpVal = Builder.getValue(CS.getArgument(i));
7114 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(OpVal)) {
7115 Ops.push_back(
7116 Builder.DAG.getTargetConstant(StackMaps::ConstantOp, MVT::i64));
7117 Ops.push_back(
7118 Builder.DAG.getTargetConstant(C->getSExtValue(), MVT::i64));
7119 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(OpVal)) {
7120 const TargetLowering &TLI = Builder.DAG.getTargetLoweringInfo();
7121 Ops.push_back(
7122 Builder.DAG.getTargetFrameIndex(FI->getIndex(), TLI.getPointerTy()));
7123 } else
7124 Ops.push_back(OpVal);
7125 }
7126}
7127
7128/// \brief Lower llvm.experimental.stackmap directly to its target opcode.
7129void SelectionDAGBuilder::visitStackmap(const CallInst &CI) {
7130 // void @llvm.experimental.stackmap(i32 <id>, i32 <numShadowBytes>,
7131 // [live variables...])
7132
7133 assert(CI.getType()->isVoidTy() && "Stackmap cannot return a value.")((CI.getType()->isVoidTy() && "Stackmap cannot return a value."
) ? static_cast<void> (0) : __assert_fail ("CI.getType()->isVoidTy() && \"Stackmap cannot return a value.\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7133, __PRETTY_FUNCTION__));
7134
7135 SDValue Chain, InFlag, Callee, NullPtr;
7136 SmallVector<SDValue, 32> Ops;
7137
7138 SDLoc DL = getCurSDLoc();
7139 Callee = getValue(CI.getCalledValue());
7140 NullPtr = DAG.getIntPtrConstant(0, true);
7141
7142 // The stackmap intrinsic only records the live variables (the arguemnts
7143 // passed to it) and emits NOPS (if requested). Unlike the patchpoint
7144 // intrinsic, this won't be lowered to a function call. This means we don't
7145 // have to worry about calling conventions and target specific lowering code.
7146 // Instead we perform the call lowering right here.
7147 //
7148 // chain, flag = CALLSEQ_START(chain, 0)
7149 // chain, flag = STACKMAP(id, nbytes, ..., chain, flag)
7150 // chain, flag = CALLSEQ_END(chain, 0, 0, flag)
7151 //
7152 Chain = DAG.getCALLSEQ_START(getRoot(), NullPtr, DL);
7153 InFlag = Chain.getValue(1);
7154
7155 // Add the <id> and <numBytes> constants.
7156 SDValue IDVal = getValue(CI.getOperand(PatchPointOpers::IDPos));
7157 Ops.push_back(DAG.getTargetConstant(
7158 cast<ConstantSDNode>(IDVal)->getZExtValue(), MVT::i64));
7159 SDValue NBytesVal = getValue(CI.getOperand(PatchPointOpers::NBytesPos));
7160 Ops.push_back(DAG.getTargetConstant(
7161 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), MVT::i32));
7162
7163 // Push live variables for the stack map.
7164 addStackMapLiveVars(&CI, 2, Ops, *this);
7165
7166 // We are not pushing any register mask info here on the operands list,
7167 // because the stackmap doesn't clobber anything.
7168
7169 // Push the chain and the glue flag.
7170 Ops.push_back(Chain);
7171 Ops.push_back(InFlag);
7172
7173 // Create the STACKMAP node.
7174 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7175 SDNode *SM = DAG.getMachineNode(TargetOpcode::STACKMAP, DL, NodeTys, Ops);
7176 Chain = SDValue(SM, 0);
7177 InFlag = Chain.getValue(1);
7178
7179 Chain = DAG.getCALLSEQ_END(Chain, NullPtr, NullPtr, InFlag, DL);
7180
7181 // Stackmaps don't generate values, so nothing goes into the NodeMap.
7182
7183 // Set the root to the target-lowered call chain.
7184 DAG.setRoot(Chain);
7185
7186 // Inform the Frame Information that we have a stackmap in this function.
7187 FuncInfo.MF->getFrameInfo()->setHasStackMap();
7188}
7189
7190/// \brief Lower llvm.experimental.patchpoint directly to its target opcode.
7191void SelectionDAGBuilder::visitPatchpoint(ImmutableCallSite CS,
7192 MachineBasicBlock *LandingPad) {
7193 // void|i64 @llvm.experimental.patchpoint.void|i64(i64 <id>,
7194 // i32 <numBytes>,
7195 // i8* <target>,
7196 // i32 <numArgs>,
7197 // [Args...],
7198 // [live variables...])
7199
7200 CallingConv::ID CC = CS.getCallingConv();
7201 bool IsAnyRegCC = CC == CallingConv::AnyReg;
7202 bool HasDef = !CS->getType()->isVoidTy();
7203 SDValue Callee = getValue(CS->getOperand(2)); // <target>
7204
7205 // Get the real number of arguments participating in the call <numArgs>
7206 SDValue NArgVal = getValue(CS.getArgument(PatchPointOpers::NArgPos));
7207 unsigned NumArgs = cast<ConstantSDNode>(NArgVal)->getZExtValue();
7208
7209 // Skip the four meta args: <id>, <numNopBytes>, <target>, <numArgs>
7210 // Intrinsics include all meta-operands up to but not including CC.
7211 unsigned NumMetaOpers = PatchPointOpers::CCPos;
7212 assert(CS.arg_size() >= NumMetaOpers + NumArgs &&((CS.arg_size() >= NumMetaOpers + NumArgs && "Not enough arguments provided to the patchpoint intrinsic"
) ? static_cast<void> (0) : __assert_fail ("CS.arg_size() >= NumMetaOpers + NumArgs && \"Not enough arguments provided to the patchpoint intrinsic\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7213, __PRETTY_FUNCTION__))
7213 "Not enough arguments provided to the patchpoint intrinsic")((CS.arg_size() >= NumMetaOpers + NumArgs && "Not enough arguments provided to the patchpoint intrinsic"
) ? static_cast<void> (0) : __assert_fail ("CS.arg_size() >= NumMetaOpers + NumArgs && \"Not enough arguments provided to the patchpoint intrinsic\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7213, __PRETTY_FUNCTION__));
7214
7215 // For AnyRegCC the arguments are lowered later on manually.
7216 unsigned NumCallArgs = IsAnyRegCC ? 0 : NumArgs;
7217 std::pair<SDValue, SDValue> Result =
7218 lowerCallOperands(CS, NumMetaOpers, NumCallArgs, Callee, IsAnyRegCC,
7219 LandingPad, true);
7220
7221 SDNode *CallEnd = Result.second.getNode();
7222 if (HasDef && (CallEnd->getOpcode() == ISD::CopyFromReg))
7223 CallEnd = CallEnd->getOperand(0).getNode();
7224
7225 /// Get a call instruction from the call sequence chain.
7226 /// Tail calls are not allowed.
7227 assert(CallEnd->getOpcode() == ISD::CALLSEQ_END &&((CallEnd->getOpcode() == ISD::CALLSEQ_END && "Expected a callseq node."
) ? static_cast<void> (0) : __assert_fail ("CallEnd->getOpcode() == ISD::CALLSEQ_END && \"Expected a callseq node.\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7228, __PRETTY_FUNCTION__))
7228 "Expected a callseq node.")((CallEnd->getOpcode() == ISD::CALLSEQ_END && "Expected a callseq node."
) ? static_cast<void> (0) : __assert_fail ("CallEnd->getOpcode() == ISD::CALLSEQ_END && \"Expected a callseq node.\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7228, __PRETTY_FUNCTION__));
7229 SDNode *Call = CallEnd->getOperand(0).getNode();
7230 bool HasGlue = Call->getGluedNode();
7231
7232 // Replace the target specific call node with the patchable intrinsic.
7233 SmallVector<SDValue, 8> Ops;
7234
7235 // Add the <id> and <numBytes> constants.
7236 SDValue IDVal = getValue(CS->getOperand(PatchPointOpers::IDPos));
7237 Ops.push_back(DAG.getTargetConstant(
7238 cast<ConstantSDNode>(IDVal)->getZExtValue(), MVT::i64));
7239 SDValue NBytesVal = getValue(CS->getOperand(PatchPointOpers::NBytesPos));
7240 Ops.push_back(DAG.getTargetConstant(
7241 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), MVT::i32));
7242
7243 // Assume that the Callee is a constant address.
7244 // FIXME: handle function symbols in the future.
7245 Ops.push_back(
7246 DAG.getIntPtrConstant(cast<ConstantSDNode>(Callee)->getZExtValue(),
7247 /*isTarget=*/true));
7248
7249 // Adjust <numArgs> to account for any arguments that have been passed on the
7250 // stack instead.
7251 // Call Node: Chain, Target, {Args}, RegMask, [Glue]
7252 unsigned NumCallRegArgs = Call->getNumOperands() - (HasGlue ? 4 : 3);
7253 NumCallRegArgs = IsAnyRegCC ? NumArgs : NumCallRegArgs;
7254 Ops.push_back(DAG.getTargetConstant(NumCallRegArgs, MVT::i32));
7255
7256 // Add the calling convention
7257 Ops.push_back(DAG.getTargetConstant((unsigned)CC, MVT::i32));
7258
7259 // Add the arguments we omitted previously. The register allocator should
7260 // place these in any free register.
7261 if (IsAnyRegCC)
7262 for (unsigned i = NumMetaOpers, e = NumMetaOpers + NumArgs; i != e; ++i)
7263 Ops.push_back(getValue(CS.getArgument(i)));
7264
7265 // Push the arguments from the call instruction up to the register mask.
7266 SDNode::op_iterator e = HasGlue ? Call->op_end()-2 : Call->op_end()-1;
7267 Ops.append(Call->op_begin() + 2, e);
7268
7269 // Push live variables for the stack map.
7270 addStackMapLiveVars(CS, NumMetaOpers + NumArgs, Ops, *this);
7271
7272 // Push the register mask info.
7273 if (HasGlue)
7274 Ops.push_back(*(Call->op_end()-2));
7275 else
7276 Ops.push_back(*(Call->op_end()-1));
7277
7278 // Push the chain (this is originally the first operand of the call, but
7279 // becomes now the last or second to last operand).
7280 Ops.push_back(*(Call->op_begin()));
7281
7282 // Push the glue flag (last operand).
7283 if (HasGlue)
7284 Ops.push_back(*(Call->op_end()-1));
7285
7286 SDVTList NodeTys;
7287 if (IsAnyRegCC && HasDef) {
7288 // Create the return types based on the intrinsic definition
7289 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7290 SmallVector<EVT, 3> ValueVTs;
7291 ComputeValueVTs(TLI, CS->getType(), ValueVTs);
7292 assert(ValueVTs.size() == 1 && "Expected only one return value type.")((ValueVTs.size() == 1 && "Expected only one return value type."
) ? static_cast<void> (0) : __assert_fail ("ValueVTs.size() == 1 && \"Expected only one return value type.\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7292, __PRETTY_FUNCTION__));
7293
7294 // There is always a chain and a glue type at the end
7295 ValueVTs.push_back(MVT::Other);
7296 ValueVTs.push_back(MVT::Glue);
7297 NodeTys = DAG.getVTList(ValueVTs);
7298 } else
7299 NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7300
7301 // Replace the target specific call node with a PATCHPOINT node.
7302 MachineSDNode *MN = DAG.getMachineNode(TargetOpcode::PATCHPOINT,
7303 getCurSDLoc(), NodeTys, Ops);
7304
7305 // Update the NodeMap.
7306 if (HasDef) {
7307 if (IsAnyRegCC)
7308 setValue(CS.getInstruction(), SDValue(MN, 0));
7309 else
7310 setValue(CS.getInstruction(), Result.first);
7311 }
7312
7313 // Fixup the consumers of the intrinsic. The chain and glue may be used in the
7314 // call sequence. Furthermore the location of the chain and glue can change
7315 // when the AnyReg calling convention is used and the intrinsic returns a
7316 // value.
7317 if (IsAnyRegCC && HasDef) {
7318 SDValue From[] = {SDValue(Call, 0), SDValue(Call, 1)};
7319 SDValue To[] = {SDValue(MN, 1), SDValue(MN, 2)};
7320 DAG.ReplaceAllUsesOfValuesWith(From, To, 2);
7321 } else
7322 DAG.ReplaceAllUsesWith(Call, MN);
7323 DAG.DeleteNode(Call);
7324
7325 // Inform the Frame Information that we have a patchpoint in this function.
7326 FuncInfo.MF->getFrameInfo()->setHasPatchPoint();
7327}
7328
7329/// Returns an AttributeSet representing the attributes applied to the return
7330/// value of the given call.
7331static AttributeSet getReturnAttrs(TargetLowering::CallLoweringInfo &CLI) {
7332 SmallVector<Attribute::AttrKind, 2> Attrs;
7333 if (CLI.RetSExt)
7334 Attrs.push_back(Attribute::SExt);
7335 if (CLI.RetZExt)
7336 Attrs.push_back(Attribute::ZExt);
7337 if (CLI.IsInReg)
7338 Attrs.push_back(Attribute::InReg);
7339
7340 return AttributeSet::get(CLI.RetTy->getContext(), AttributeSet::ReturnIndex,
7341 Attrs);
7342}
7343
7344/// TargetLowering::LowerCallTo - This is the default LowerCallTo
7345/// implementation, which just calls LowerCall.
7346/// FIXME: When all targets are
7347/// migrated to using LowerCall, this hook should be integrated into SDISel.
7348std::pair<SDValue, SDValue>
7349TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const {
7350 // Handle the incoming return values from the call.
7351 CLI.Ins.clear();
7352 Type *OrigRetTy = CLI.RetTy;
7353 SmallVector<EVT, 4> RetTys;
7354 SmallVector<uint64_t, 4> Offsets;
7355 ComputeValueVTs(*this, CLI.RetTy, RetTys, &Offsets);
7356
7357 SmallVector<ISD::OutputArg, 4> Outs;
7358 GetReturnInfo(CLI.RetTy, getReturnAttrs(CLI), Outs, *this);
7359
7360 bool CanLowerReturn =
7361 this->CanLowerReturn(CLI.CallConv, CLI.DAG.getMachineFunction(),
7362 CLI.IsVarArg, Outs, CLI.RetTy->getContext());
7363
7364 SDValue DemoteStackSlot;
7365 int DemoteStackIdx = -100;
7366 if (!CanLowerReturn) {
7367 // FIXME: equivalent assert?
7368 // assert(!CS.hasInAllocaArgument() &&
7369 // "sret demotion is incompatible with inalloca");
7370 uint64_t TySize = getDataLayout()->getTypeAllocSize(CLI.RetTy);
7371 unsigned Align = getDataLayout()->getPrefTypeAlignment(CLI.RetTy);
7372 MachineFunction &MF = CLI.DAG.getMachineFunction();
7373 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
7374 Type *StackSlotPtrType = PointerType::getUnqual(CLI.RetTy);
7375
7376 DemoteStackSlot = CLI.DAG.getFrameIndex(DemoteStackIdx, getPointerTy());
7377 ArgListEntry Entry;
7378 Entry.Node = DemoteStackSlot;
7379 Entry.Ty = StackSlotPtrType;
7380 Entry.isSExt = false;
7381 Entry.isZExt = false;
7382 Entry.isInReg = false;
7383 Entry.isSRet = true;
7384 Entry.isNest = false;
7385 Entry.isByVal = false;
7386 Entry.isReturned = false;
7387 Entry.Alignment = Align;
7388 CLI.getArgs().insert(CLI.getArgs().begin(), Entry);
7389 CLI.RetTy = Type::getVoidTy(CLI.RetTy->getContext());
7390 } else {
7391 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
7392 EVT VT = RetTys[I];
7393 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
7394 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
7395 for (unsigned i = 0; i != NumRegs; ++i) {
7396 ISD::InputArg MyFlags;
7397 MyFlags.VT = RegisterVT;
7398 MyFlags.ArgVT = VT;
7399 MyFlags.Used = CLI.IsReturnValueUsed;
7400 if (CLI.RetSExt)
7401 MyFlags.Flags.setSExt();
7402 if (CLI.RetZExt)
7403 MyFlags.Flags.setZExt();
7404 if (CLI.IsInReg)
7405 MyFlags.Flags.setInReg();
7406 CLI.Ins.push_back(MyFlags);
7407 }
7408 }
7409 }
7410
7411 // Handle all of the outgoing arguments.
7412 CLI.Outs.clear();
7413 CLI.OutVals.clear();
7414 ArgListTy &Args = CLI.getArgs();
7415 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
7416 SmallVector<EVT, 4> ValueVTs;
7417 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
7418 Type *FinalType = Args[i].Ty;
7419 if (Args[i].isByVal)
7420 FinalType = cast<PointerType>(Args[i].Ty)->getElementType();
7421 bool NeedsRegBlock = functionArgumentNeedsConsecutiveRegisters(
7422 FinalType, CLI.CallConv, CLI.IsVarArg);
7423 for (unsigned Value = 0, NumValues = ValueVTs.size(); Value != NumValues;
7424 ++Value) {
7425 EVT VT = ValueVTs[Value];
7426 Type *ArgTy = VT.getTypeForEVT(CLI.RetTy->getContext());
7427 SDValue Op = SDValue(Args[i].Node.getNode(),
7428 Args[i].Node.getResNo() + Value);
7429 ISD::ArgFlagsTy Flags;
7430 unsigned OriginalAlignment = getDataLayout()->getABITypeAlignment(ArgTy);
7431
7432 if (Args[i].isZExt)
7433 Flags.setZExt();
7434 if (Args[i].isSExt)
7435 Flags.setSExt();
7436 if (Args[i].isInReg)
7437 Flags.setInReg();
7438 if (Args[i].isSRet)
7439 Flags.setSRet();
7440 if (Args[i].isByVal)
7441 Flags.setByVal();
7442 if (Args[i].isInAlloca) {
7443 Flags.setInAlloca();
7444 // Set the byval flag for CCAssignFn callbacks that don't know about
7445 // inalloca. This way we can know how many bytes we should've allocated
7446 // and how many bytes a callee cleanup function will pop. If we port
7447 // inalloca to more targets, we'll have to add custom inalloca handling
7448 // in the various CC lowering callbacks.
7449 Flags.setByVal();
7450 }
7451 if (Args[i].isByVal || Args[i].isInAlloca) {
7452 PointerType *Ty = cast<PointerType>(Args[i].Ty);
7453 Type *ElementTy = Ty->getElementType();
7454 Flags.setByValSize(getDataLayout()->getTypeAllocSize(ElementTy));
7455 // For ByVal, alignment should come from FE. BE will guess if this
7456 // info is not there but there are cases it cannot get right.
7457 unsigned FrameAlign;
7458 if (Args[i].Alignment)
7459 FrameAlign = Args[i].Alignment;
7460 else
7461 FrameAlign = getByValTypeAlignment(ElementTy);
7462 Flags.setByValAlign(FrameAlign);
7463 }
7464 if (Args[i].isNest)
7465 Flags.setNest();
7466 if (NeedsRegBlock)
7467 Flags.setInConsecutiveRegs();
7468 Flags.setOrigAlign(OriginalAlignment);
7469
7470 MVT PartVT = getRegisterType(CLI.RetTy->getContext(), VT);
7471 unsigned NumParts = getNumRegisters(CLI.RetTy->getContext(), VT);
7472 SmallVector<SDValue, 4> Parts(NumParts);
7473 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
7474
7475 if (Args[i].isSExt)
7476 ExtendKind = ISD::SIGN_EXTEND;
7477 else if (Args[i].isZExt)
7478 ExtendKind = ISD::ZERO_EXTEND;
7479
7480 // Conservatively only handle 'returned' on non-vectors for now
7481 if (Args[i].isReturned && !Op.getValueType().isVector()) {
7482 assert(CLI.RetTy == Args[i].Ty && RetTys.size() == NumValues &&((CLI.RetTy == Args[i].Ty && RetTys.size() == NumValues
&& "unexpected use of 'returned'") ? static_cast<
void> (0) : __assert_fail ("CLI.RetTy == Args[i].Ty && RetTys.size() == NumValues && \"unexpected use of 'returned'\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7483, __PRETTY_FUNCTION__))
7483 "unexpected use of 'returned'")((CLI.RetTy == Args[i].Ty && RetTys.size() == NumValues
&& "unexpected use of 'returned'") ? static_cast<
void> (0) : __assert_fail ("CLI.RetTy == Args[i].Ty && RetTys.size() == NumValues && \"unexpected use of 'returned'\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7483, __PRETTY_FUNCTION__));
7484 // Before passing 'returned' to the target lowering code, ensure that
7485 // either the register MVT and the actual EVT are the same size or that
7486 // the return value and argument are extended in the same way; in these
7487 // cases it's safe to pass the argument register value unchanged as the
7488 // return register value (although it's at the target's option whether
7489 // to do so)
7490 // TODO: allow code generation to take advantage of partially preserved
7491 // registers rather than clobbering the entire register when the
7492 // parameter extension method is not compatible with the return
7493 // extension method
7494 if ((NumParts * PartVT.getSizeInBits() == VT.getSizeInBits()) ||
7495 (ExtendKind != ISD::ANY_EXTEND &&
7496 CLI.RetSExt == Args[i].isSExt && CLI.RetZExt == Args[i].isZExt))
7497 Flags.setReturned();
7498 }
7499
7500 getCopyToParts(CLI.DAG, CLI.DL, Op, &Parts[0], NumParts, PartVT,
7501 CLI.CS ? CLI.CS->getInstruction() : nullptr, ExtendKind);
7502
7503 for (unsigned j = 0; j != NumParts; ++j) {
7504 // if it isn't first piece, alignment must be 1
7505 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(), VT,
7506 i < CLI.NumFixedArgs,
7507 i, j*Parts[j].getValueType().getStoreSize());
7508 if (NumParts > 1 && j == 0)
7509 MyFlags.Flags.setSplit();
7510 else if (j != 0)
7511 MyFlags.Flags.setOrigAlign(1);
7512
7513 CLI.Outs.push_back(MyFlags);
7514 CLI.OutVals.push_back(Parts[j]);
7515 }
7516
7517 if (NeedsRegBlock && Value == NumValues - 1)
7518 CLI.Outs[CLI.Outs.size() - 1].Flags.setInConsecutiveRegsLast();
7519 }
7520 }
7521
7522 SmallVector<SDValue, 4> InVals;
7523 CLI.Chain = LowerCall(CLI, InVals);
7524
7525 // Verify that the target's LowerCall behaved as expected.
7526 assert(CLI.Chain.getNode() && CLI.Chain.getValueType() == MVT::Other &&((CLI.Chain.getNode() && CLI.Chain.getValueType() == MVT
::Other && "LowerCall didn't return a valid chain!") ?
static_cast<void> (0) : __assert_fail ("CLI.Chain.getNode() && CLI.Chain.getValueType() == MVT::Other && \"LowerCall didn't return a valid chain!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7527, __PRETTY_FUNCTION__))
7527 "LowerCall didn't return a valid chain!")((CLI.Chain.getNode() && CLI.Chain.getValueType() == MVT
::Other && "LowerCall didn't return a valid chain!") ?
static_cast<void> (0) : __assert_fail ("CLI.Chain.getNode() && CLI.Chain.getValueType() == MVT::Other && \"LowerCall didn't return a valid chain!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7527, __PRETTY_FUNCTION__));
7528 assert((!CLI.IsTailCall || InVals.empty()) &&(((!CLI.IsTailCall || InVals.empty()) && "LowerCall emitted a return value for a tail call!"
) ? static_cast<void> (0) : __assert_fail ("(!CLI.IsTailCall || InVals.empty()) && \"LowerCall emitted a return value for a tail call!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7529, __PRETTY_FUNCTION__))
7529 "LowerCall emitted a return value for a tail call!")(((!CLI.IsTailCall || InVals.empty()) && "LowerCall emitted a return value for a tail call!"
) ? static_cast<void> (0) : __assert_fail ("(!CLI.IsTailCall || InVals.empty()) && \"LowerCall emitted a return value for a tail call!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7529, __PRETTY_FUNCTION__));
7530 assert((CLI.IsTailCall || InVals.size() == CLI.Ins.size()) &&(((CLI.IsTailCall || InVals.size() == CLI.Ins.size()) &&
"LowerCall didn't emit the correct number of values!") ? static_cast
<void> (0) : __assert_fail ("(CLI.IsTailCall || InVals.size() == CLI.Ins.size()) && \"LowerCall didn't emit the correct number of values!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7531, __PRETTY_FUNCTION__))
7531 "LowerCall didn't emit the correct number of values!")(((CLI.IsTailCall || InVals.size() == CLI.Ins.size()) &&
"LowerCall didn't emit the correct number of values!") ? static_cast
<void> (0) : __assert_fail ("(CLI.IsTailCall || InVals.size() == CLI.Ins.size()) && \"LowerCall didn't emit the correct number of values!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7531, __PRETTY_FUNCTION__));
7532
7533 // For a tail call, the return value is merely live-out and there aren't
7534 // any nodes in the DAG representing it. Return a special value to
7535 // indicate that a tail call has been emitted and no more Instructions
7536 // should be processed in the current block.
7537 if (CLI.IsTailCall) {
7538 CLI.DAG.setRoot(CLI.Chain);
7539 return std::make_pair(SDValue(), SDValue());
7540 }
7541
7542 DEBUG(for (unsigned i = 0, e = CLI.Ins.size(); i != e; ++i) {do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { for (unsigned i = 0, e = CLI.Ins.size(); i != e; ++
i) { ((InVals[i].getNode() && "LowerCall emitted a null value!"
) ? static_cast<void> (0) : __assert_fail ("InVals[i].getNode() && \"LowerCall emitted a null value!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7544, __PRETTY_FUNCTION__)); ((EVT(CLI.Ins[i].VT) == InVals
[i].getValueType() && "LowerCall emitted a value with the wrong type!"
) ? static_cast<void> (0) : __assert_fail ("EVT(CLI.Ins[i].VT) == InVals[i].getValueType() && \"LowerCall emitted a value with the wrong type!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7546, __PRETTY_FUNCTION__)); }; } } while (0)
7543 assert(InVals[i].getNode() &&do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { for (unsigned i = 0, e = CLI.Ins.size(); i != e; ++
i) { ((InVals[i].getNode() && "LowerCall emitted a null value!"
) ? static_cast<void> (0) : __assert_fail ("InVals[i].getNode() && \"LowerCall emitted a null value!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7544, __PRETTY_FUNCTION__)); ((EVT(CLI.Ins[i].VT) == InVals
[i].getValueType() && "LowerCall emitted a value with the wrong type!"
) ? static_cast<void> (0) : __assert_fail ("EVT(CLI.Ins[i].VT) == InVals[i].getValueType() && \"LowerCall emitted a value with the wrong type!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7546, __PRETTY_FUNCTION__)); }; } } while (0)
7544 "LowerCall emitted a null value!");do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { for (unsigned i = 0, e = CLI.Ins.size(); i != e; ++
i) { ((InVals[i].getNode() && "LowerCall emitted a null value!"
) ? static_cast<void> (0) : __assert_fail ("InVals[i].getNode() && \"LowerCall emitted a null value!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7544, __PRETTY_FUNCTION__)); ((EVT(CLI.Ins[i].VT) == InVals
[i].getValueType() && "LowerCall emitted a value with the wrong type!"
) ? static_cast<void> (0) : __assert_fail ("EVT(CLI.Ins[i].VT) == InVals[i].getValueType() && \"LowerCall emitted a value with the wrong type!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7546, __PRETTY_FUNCTION__)); }; } } while (0)
7545 assert(EVT(CLI.Ins[i].VT) == InVals[i].getValueType() &&do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { for (unsigned i = 0, e = CLI.Ins.size(); i != e; ++
i) { ((InVals[i].getNode() && "LowerCall emitted a null value!"
) ? static_cast<void> (0) : __assert_fail ("InVals[i].getNode() && \"LowerCall emitted a null value!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7544, __PRETTY_FUNCTION__)); ((EVT(CLI.Ins[i].VT) == InVals
[i].getValueType() && "LowerCall emitted a value with the wrong type!"
) ? static_cast<void> (0) : __assert_fail ("EVT(CLI.Ins[i].VT) == InVals[i].getValueType() && \"LowerCall emitted a value with the wrong type!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7546, __PRETTY_FUNCTION__)); }; } } while (0)
7546 "LowerCall emitted a value with the wrong type!");do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { for (unsigned i = 0, e = CLI.Ins.size(); i != e; ++
i) { ((InVals[i].getNode() && "LowerCall emitted a null value!"
) ? static_cast<void> (0) : __assert_fail ("InVals[i].getNode() && \"LowerCall emitted a null value!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7544, __PRETTY_FUNCTION__)); ((EVT(CLI.Ins[i].VT) == InVals
[i].getValueType() && "LowerCall emitted a value with the wrong type!"
) ? static_cast<void> (0) : __assert_fail ("EVT(CLI.Ins[i].VT) == InVals[i].getValueType() && \"LowerCall emitted a value with the wrong type!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7546, __PRETTY_FUNCTION__)); }; } } while (0)
7547 })do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { for (unsigned i = 0, e = CLI.Ins.size(); i != e; ++
i) { ((InVals[i].getNode() && "LowerCall emitted a null value!"
) ? static_cast<void> (0) : __assert_fail ("InVals[i].getNode() && \"LowerCall emitted a null value!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7544, __PRETTY_FUNCTION__)); ((EVT(CLI.Ins[i].VT) == InVals
[i].getValueType() && "LowerCall emitted a value with the wrong type!"
) ? static_cast<void> (0) : __assert_fail ("EVT(CLI.Ins[i].VT) == InVals[i].getValueType() && \"LowerCall emitted a value with the wrong type!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7546, __PRETTY_FUNCTION__)); }; } } while (0);
7548
7549 SmallVector<SDValue, 4> ReturnValues;
7550 if (!CanLowerReturn) {
7551 // The instruction result is the result of loading from the
7552 // hidden sret parameter.
7553 SmallVector<EVT, 1> PVTs;
7554 Type *PtrRetTy = PointerType::getUnqual(OrigRetTy);
7555
7556 ComputeValueVTs(*this, PtrRetTy, PVTs);
7557 assert(PVTs.size() == 1 && "Pointers should fit in one register")((PVTs.size() == 1 && "Pointers should fit in one register"
) ? static_cast<void> (0) : __assert_fail ("PVTs.size() == 1 && \"Pointers should fit in one register\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7557, __PRETTY_FUNCTION__));
7558 EVT PtrVT = PVTs[0];
7559
7560 unsigned NumValues = RetTys.size();
7561 ReturnValues.resize(NumValues);
7562 SmallVector<SDValue, 4> Chains(NumValues);
7563
7564 for (unsigned i = 0; i < NumValues; ++i) {
7565 SDValue Add = CLI.DAG.getNode(ISD::ADD, CLI.DL, PtrVT, DemoteStackSlot,
7566 CLI.DAG.getConstant(Offsets[i], PtrVT));
7567 SDValue L = CLI.DAG.getLoad(
7568 RetTys[i], CLI.DL, CLI.Chain, Add,
7569 MachinePointerInfo::getFixedStack(DemoteStackIdx, Offsets[i]), false,
7570 false, false, 1);
7571 ReturnValues[i] = L;
7572 Chains[i] = L.getValue(1);
7573 }
7574
7575 CLI.Chain = CLI.DAG.getNode(ISD::TokenFactor, CLI.DL, MVT::Other, Chains);
7576 } else {
7577 // Collect the legal value parts into potentially illegal values
7578 // that correspond to the original function's return values.
7579 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7580 if (CLI.RetSExt)
7581 AssertOp = ISD::AssertSext;
7582 else if (CLI.RetZExt)
7583 AssertOp = ISD::AssertZext;
7584 unsigned CurReg = 0;
7585 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
7586 EVT VT = RetTys[I];
7587 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
7588 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
7589
7590 ReturnValues.push_back(getCopyFromParts(CLI.DAG, CLI.DL, &InVals[CurReg],
7591 NumRegs, RegisterVT, VT, nullptr,
7592 AssertOp));
7593 CurReg += NumRegs;
7594 }
7595
7596 // For a function returning void, there is no return value. We can't create
7597 // such a node, so we just return a null return value in that case. In
7598 // that case, nothing will actually look at the value.
7599 if (ReturnValues.empty())
7600 return std::make_pair(SDValue(), CLI.Chain);
7601 }
7602
7603 SDValue Res = CLI.DAG.getNode(ISD::MERGE_VALUES, CLI.DL,
7604 CLI.DAG.getVTList(RetTys), ReturnValues);
7605 return std::make_pair(Res, CLI.Chain);
7606}
7607
7608void TargetLowering::LowerOperationWrapper(SDNode *N,
7609 SmallVectorImpl<SDValue> &Results,
7610 SelectionDAG &DAG) const {
7611 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
7612 if (Res.getNode())
7613 Results.push_back(Res);
7614}
7615
7616SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
7617 llvm_unreachable("LowerOperation not implemented for this target!")::llvm::llvm_unreachable_internal("LowerOperation not implemented for this target!"
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7617);
7618}
7619
7620void
7621SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) {
7622 SDValue Op = getNonRegisterValue(V);
7623 assert((Op.getOpcode() != ISD::CopyFromReg ||(((Op.getOpcode() != ISD::CopyFromReg || cast<RegisterSDNode
>(Op.getOperand(1))->getReg() != Reg) && "Copy from a reg to the same reg!"
) ? static_cast<void> (0) : __assert_fail ("(Op.getOpcode() != ISD::CopyFromReg || cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) && \"Copy from a reg to the same reg!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7625, __PRETTY_FUNCTION__))
7624 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&(((Op.getOpcode() != ISD::CopyFromReg || cast<RegisterSDNode
>(Op.getOperand(1))->getReg() != Reg) && "Copy from a reg to the same reg!"
) ? static_cast<void> (0) : __assert_fail ("(Op.getOpcode() != ISD::CopyFromReg || cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) && \"Copy from a reg to the same reg!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7625, __PRETTY_FUNCTION__))
7625 "Copy from a reg to the same reg!")(((Op.getOpcode() != ISD::CopyFromReg || cast<RegisterSDNode
>(Op.getOperand(1))->getReg() != Reg) && "Copy from a reg to the same reg!"
) ? static_cast<void> (0) : __assert_fail ("(Op.getOpcode() != ISD::CopyFromReg || cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) && \"Copy from a reg to the same reg!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7625, __PRETTY_FUNCTION__));
7626 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg")((!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg"
) ? static_cast<void> (0) : __assert_fail ("!TargetRegisterInfo::isPhysicalRegister(Reg) && \"Is a physreg\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7626, __PRETTY_FUNCTION__));
7627
7628 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7629 RegsForValue RFV(V->getContext(), TLI, Reg, V->getType());
7630 SDValue Chain = DAG.getEntryNode();
7631
7632 ISD::NodeType ExtendType = (FuncInfo.PreferredExtendType.find(V) ==
7633 FuncInfo.PreferredExtendType.end())
7634 ? ISD::ANY_EXTEND
7635 : FuncInfo.PreferredExtendType[V];
7636 RFV.getCopyToRegs(Op, DAG, getCurSDLoc(), Chain, nullptr, V, ExtendType);
7637 PendingExports.push_back(Chain);
7638}
7639
7640#include "llvm/CodeGen/SelectionDAGISel.h"
7641
7642/// isOnlyUsedInEntryBlock - If the specified argument is only used in the
7643/// entry block, return true. This includes arguments used by switches, since
7644/// the switch may expand into multiple basic blocks.
7645static bool isOnlyUsedInEntryBlock(const Argument *A, bool FastISel) {
7646 // With FastISel active, we may be splitting blocks, so force creation
7647 // of virtual registers for all non-dead arguments.
7648 if (FastISel)
7649 return A->use_empty();
7650
7651 const BasicBlock *Entry = A->getParent()->begin();
7652 for (const User *U : A->users())
7653 if (cast<Instruction>(U)->getParent() != Entry || isa<SwitchInst>(U))
7654 return false; // Use not in entry block.
7655
7656 return true;
7657}
7658
7659void SelectionDAGISel::LowerArguments(const Function &F) {
7660 SelectionDAG &DAG = SDB->DAG;
7661 SDLoc dl = SDB->getCurSDLoc();
7662 const DataLayout *DL = TLI->getDataLayout();
7663 SmallVector<ISD::InputArg, 16> Ins;
7664
7665 if (!FuncInfo->CanLowerReturn) {
7666 // Put in an sret pointer parameter before all the other parameters.
7667 SmallVector<EVT, 1> ValueVTs;
7668 ComputeValueVTs(*TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
7669
7670 // NOTE: Assuming that a pointer will never break down to more than one VT
7671 // or one register.
7672 ISD::ArgFlagsTy Flags;
7673 Flags.setSRet();
7674 MVT RegisterVT = TLI->getRegisterType(*DAG.getContext(), ValueVTs[0]);
7675 ISD::InputArg RetArg(Flags, RegisterVT, ValueVTs[0], true,
7676 ISD::InputArg::NoArgIndex, 0);
7677 Ins.push_back(RetArg);
7678 }
7679
7680 // Set up the incoming argument description vector.
7681 unsigned Idx = 1;
7682 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
7683 I != E; ++I, ++Idx) {
7684 SmallVector<EVT, 4> ValueVTs;
7685 ComputeValueVTs(*TLI, I->getType(), ValueVTs);
7686 bool isArgValueUsed = !I->use_empty();
7687 unsigned PartBase = 0;
7688 Type *FinalType = I->getType();
7689 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
7690 FinalType = cast<PointerType>(FinalType)->getElementType();
7691 bool NeedsRegBlock = TLI->functionArgumentNeedsConsecutiveRegisters(
7692 FinalType, F.getCallingConv(), F.isVarArg());
7693 for (unsigned Value = 0, NumValues = ValueVTs.size();
7694 Value != NumValues; ++Value) {
7695 EVT VT = ValueVTs[Value];
7696 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
7697 ISD::ArgFlagsTy Flags;
7698 unsigned OriginalAlignment = DL->getABITypeAlignment(ArgTy);
7699
7700 if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7701 Flags.setZExt();
7702 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7703 Flags.setSExt();
7704 if (F.getAttributes().hasAttribute(Idx, Attribute::InReg))
7705 Flags.setInReg();
7706 if (F.getAttributes().hasAttribute(Idx, Attribute::StructRet))
7707 Flags.setSRet();
7708 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
7709 Flags.setByVal();
7710 if (F.getAttributes().hasAttribute(Idx, Attribute::InAlloca)) {
7711 Flags.setInAlloca();
7712 // Set the byval flag for CCAssignFn callbacks that don't know about
7713 // inalloca. This way we can know how many bytes we should've allocated
7714 // and how many bytes a callee cleanup function will pop. If we port
7715 // inalloca to more targets, we'll have to add custom inalloca handling
7716 // in the various CC lowering callbacks.
7717 Flags.setByVal();
7718 }
7719 if (Flags.isByVal() || Flags.isInAlloca()) {
7720 PointerType *Ty = cast<PointerType>(I->getType());
7721 Type *ElementTy = Ty->getElementType();
7722 Flags.setByValSize(DL->getTypeAllocSize(ElementTy));
7723 // For ByVal, alignment should be passed from FE. BE will guess if
7724 // this info is not there but there are cases it cannot get right.
7725 unsigned FrameAlign;
7726 if (F.getParamAlignment(Idx))
7727 FrameAlign = F.getParamAlignment(Idx);
7728 else
7729 FrameAlign = TLI->getByValTypeAlignment(ElementTy);
7730 Flags.setByValAlign(FrameAlign);
7731 }
7732 if (F.getAttributes().hasAttribute(Idx, Attribute::Nest))
7733 Flags.setNest();
7734 if (NeedsRegBlock)
7735 Flags.setInConsecutiveRegs();
7736 Flags.setOrigAlign(OriginalAlignment);
7737
7738 MVT RegisterVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7739 unsigned NumRegs = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7740 for (unsigned i = 0; i != NumRegs; ++i) {
7741 ISD::InputArg MyFlags(Flags, RegisterVT, VT, isArgValueUsed,
7742 Idx-1, PartBase+i*RegisterVT.getStoreSize());
7743 if (NumRegs > 1 && i == 0)
7744 MyFlags.Flags.setSplit();
7745 // if it isn't first piece, alignment must be 1
7746 else if (i > 0)
7747 MyFlags.Flags.setOrigAlign(1);
7748 Ins.push_back(MyFlags);
7749 }
7750 if (NeedsRegBlock && Value == NumValues - 1)
7751 Ins[Ins.size() - 1].Flags.setInConsecutiveRegsLast();
7752 PartBase += VT.getStoreSize();
7753 }
7754 }
7755
7756 // Call the target to set up the argument values.
7757 SmallVector<SDValue, 8> InVals;
7758 SDValue NewRoot = TLI->LowerFormalArguments(
7759 DAG.getRoot(), F.getCallingConv(), F.isVarArg(), Ins, dl, DAG, InVals);
7760
7761 // Verify that the target's LowerFormalArguments behaved as expected.
7762 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&((NewRoot.getNode() && NewRoot.getValueType() == MVT::
Other && "LowerFormalArguments didn't return a valid chain!"
) ? static_cast<void> (0) : __assert_fail ("NewRoot.getNode() && NewRoot.getValueType() == MVT::Other && \"LowerFormalArguments didn't return a valid chain!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7763, __PRETTY_FUNCTION__))
7763 "LowerFormalArguments didn't return a valid chain!")((NewRoot.getNode() && NewRoot.getValueType() == MVT::
Other && "LowerFormalArguments didn't return a valid chain!"
) ? static_cast<void> (0) : __assert_fail ("NewRoot.getNode() && NewRoot.getValueType() == MVT::Other && \"LowerFormalArguments didn't return a valid chain!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7763, __PRETTY_FUNCTION__));
7764 assert(InVals.size() == Ins.size() &&((InVals.size() == Ins.size() && "LowerFormalArguments didn't emit the correct number of values!"
) ? static_cast<void> (0) : __assert_fail ("InVals.size() == Ins.size() && \"LowerFormalArguments didn't emit the correct number of values!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7765, __PRETTY_FUNCTION__))
7765 "LowerFormalArguments didn't emit the correct number of values!")((InVals.size() == Ins.size() && "LowerFormalArguments didn't emit the correct number of values!"
) ? static_cast<void> (0) : __assert_fail ("InVals.size() == Ins.size() && \"LowerFormalArguments didn't emit the correct number of values!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7765, __PRETTY_FUNCTION__));
7766 DEBUG({do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { { for (unsigned i = 0, e = Ins.size(); i != e; ++
i) { ((InVals[i].getNode() && "LowerFormalArguments emitted a null value!"
) ? static_cast<void> (0) : __assert_fail ("InVals[i].getNode() && \"LowerFormalArguments emitted a null value!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7769, __PRETTY_FUNCTION__)); ((EVT(Ins[i].VT) == InVals[i].
getValueType() && "LowerFormalArguments emitted a value with the wrong type!"
) ? static_cast<void> (0) : __assert_fail ("EVT(Ins[i].VT) == InVals[i].getValueType() && \"LowerFormalArguments emitted a value with the wrong type!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7771, __PRETTY_FUNCTION__)); } }; } } while (0)
7767 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { { for (unsigned i = 0, e = Ins.size(); i != e; ++
i) { ((InVals[i].getNode() && "LowerFormalArguments emitted a null value!"
) ? static_cast<void> (0) : __assert_fail ("InVals[i].getNode() && \"LowerFormalArguments emitted a null value!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7769, __PRETTY_FUNCTION__)); ((EVT(Ins[i].VT) == InVals[i].
getValueType() && "LowerFormalArguments emitted a value with the wrong type!"
) ? static_cast<void> (0) : __assert_fail ("EVT(Ins[i].VT) == InVals[i].getValueType() && \"LowerFormalArguments emitted a value with the wrong type!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7771, __PRETTY_FUNCTION__)); } }; } } while (0)
7768 assert(InVals[i].getNode() &&do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { { for (unsigned i = 0, e = Ins.size(); i != e; ++
i) { ((InVals[i].getNode() && "LowerFormalArguments emitted a null value!"
) ? static_cast<void> (0) : __assert_fail ("InVals[i].getNode() && \"LowerFormalArguments emitted a null value!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7769, __PRETTY_FUNCTION__)); ((EVT(Ins[i].VT) == InVals[i].
getValueType() && "LowerFormalArguments emitted a value with the wrong type!"
) ? static_cast<void> (0) : __assert_fail ("EVT(Ins[i].VT) == InVals[i].getValueType() && \"LowerFormalArguments emitted a value with the wrong type!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7771, __PRETTY_FUNCTION__)); } }; } } while (0)
7769 "LowerFormalArguments emitted a null value!");do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { { for (unsigned i = 0, e = Ins.size(); i != e; ++
i) { ((InVals[i].getNode() && "LowerFormalArguments emitted a null value!"
) ? static_cast<void> (0) : __assert_fail ("InVals[i].getNode() && \"LowerFormalArguments emitted a null value!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7769, __PRETTY_FUNCTION__)); ((EVT(Ins[i].VT) == InVals[i].
getValueType() && "LowerFormalArguments emitted a value with the wrong type!"
) ? static_cast<void> (0) : __assert_fail ("EVT(Ins[i].VT) == InVals[i].getValueType() && \"LowerFormalArguments emitted a value with the wrong type!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7771, __PRETTY_FUNCTION__)); } }; } } while (0)
7770 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { { for (unsigned i = 0, e = Ins.size(); i != e; ++
i) { ((InVals[i].getNode() && "LowerFormalArguments emitted a null value!"
) ? static_cast<void> (0) : __assert_fail ("InVals[i].getNode() && \"LowerFormalArguments emitted a null value!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7769, __PRETTY_FUNCTION__)); ((EVT(Ins[i].VT) == InVals[i].
getValueType() && "LowerFormalArguments emitted a value with the wrong type!"
) ? static_cast<void> (0) : __assert_fail ("EVT(Ins[i].VT) == InVals[i].getValueType() && \"LowerFormalArguments emitted a value with the wrong type!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7771, __PRETTY_FUNCTION__)); } }; } } while (0)
7771 "LowerFormalArguments emitted a value with the wrong type!");do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { { for (unsigned i = 0, e = Ins.size(); i != e; ++
i) { ((InVals[i].getNode() && "LowerFormalArguments emitted a null value!"
) ? static_cast<void> (0) : __assert_fail ("InVals[i].getNode() && \"LowerFormalArguments emitted a null value!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7769, __PRETTY_FUNCTION__)); ((EVT(Ins[i].VT) == InVals[i].
getValueType() && "LowerFormalArguments emitted a value with the wrong type!"
) ? static_cast<void> (0) : __assert_fail ("EVT(Ins[i].VT) == InVals[i].getValueType() && \"LowerFormalArguments emitted a value with the wrong type!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7771, __PRETTY_FUNCTION__)); } }; } } while (0)
7772 }do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { { for (unsigned i = 0, e = Ins.size(); i != e; ++
i) { ((InVals[i].getNode() && "LowerFormalArguments emitted a null value!"
) ? static_cast<void> (0) : __assert_fail ("InVals[i].getNode() && \"LowerFormalArguments emitted a null value!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7769, __PRETTY_FUNCTION__)); ((EVT(Ins[i].VT) == InVals[i].
getValueType() && "LowerFormalArguments emitted a value with the wrong type!"
) ? static_cast<void> (0) : __assert_fail ("EVT(Ins[i].VT) == InVals[i].getValueType() && \"LowerFormalArguments emitted a value with the wrong type!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7771, __PRETTY_FUNCTION__)); } }; } } while (0)
7773 })do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { { for (unsigned i = 0, e = Ins.size(); i != e; ++
i) { ((InVals[i].getNode() && "LowerFormalArguments emitted a null value!"
) ? static_cast<void> (0) : __assert_fail ("InVals[i].getNode() && \"LowerFormalArguments emitted a null value!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7769, __PRETTY_FUNCTION__)); ((EVT(Ins[i].VT) == InVals[i].
getValueType() && "LowerFormalArguments emitted a value with the wrong type!"
) ? static_cast<void> (0) : __assert_fail ("EVT(Ins[i].VT) == InVals[i].getValueType() && \"LowerFormalArguments emitted a value with the wrong type!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7771, __PRETTY_FUNCTION__)); } }; } } while (0);
7774
7775 // Update the DAG with the new chain value resulting from argument lowering.
7776 DAG.setRoot(NewRoot);
7777
7778 // Set up the argument values.
7779 unsigned i = 0;
7780 Idx = 1;
7781 if (!FuncInfo->CanLowerReturn) {
7782 // Create a virtual register for the sret pointer, and put in a copy
7783 // from the sret argument into it.
7784 SmallVector<EVT, 1> ValueVTs;
7785 ComputeValueVTs(*TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
7786 MVT VT = ValueVTs[0].getSimpleVT();
7787 MVT RegVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7788 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7789 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1,
7790 RegVT, VT, nullptr, AssertOp);
7791
7792 MachineFunction& MF = SDB->DAG.getMachineFunction();
7793 MachineRegisterInfo& RegInfo = MF.getRegInfo();
7794 unsigned SRetReg = RegInfo.createVirtualRegister(TLI->getRegClassFor(RegVT));
7795 FuncInfo->DemoteRegister = SRetReg;
7796 NewRoot =
7797 SDB->DAG.getCopyToReg(NewRoot, SDB->getCurSDLoc(), SRetReg, ArgValue);
7798 DAG.setRoot(NewRoot);
7799
7800 // i indexes lowered arguments. Bump it past the hidden sret argument.
7801 // Idx indexes LLVM arguments. Don't touch it.
7802 ++i;
7803 }
7804
7805 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
7806 ++I, ++Idx) {
7807 SmallVector<SDValue, 4> ArgValues;
7808 SmallVector<EVT, 4> ValueVTs;
7809 ComputeValueVTs(*TLI, I->getType(), ValueVTs);
7810 unsigned NumValues = ValueVTs.size();
7811
7812 // If this argument is unused then remember its value. It is used to generate
7813 // debugging information.
7814 if (I->use_empty() && NumValues) {
7815 SDB->setUnusedArgValue(I, InVals[i]);
7816
7817 // Also remember any frame index for use in FastISel.
7818 if (FrameIndexSDNode *FI =
7819 dyn_cast<FrameIndexSDNode>(InVals[i].getNode()))
7820 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7821 }
7822
7823 for (unsigned Val = 0; Val != NumValues; ++Val) {
7824 EVT VT = ValueVTs[Val];
7825 MVT PartVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7826 unsigned NumParts = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7827
7828 if (!I->use_empty()) {
7829 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7830 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7831 AssertOp = ISD::AssertSext;
7832 else if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7833 AssertOp = ISD::AssertZext;
7834
7835 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i],
7836 NumParts, PartVT, VT,
7837 nullptr, AssertOp));
7838 }
7839
7840 i += NumParts;
7841 }
7842
7843 // We don't need to do anything else for unused arguments.
7844 if (ArgValues.empty())
7845 continue;
7846
7847 // Note down frame index.
7848 if (FrameIndexSDNode *FI =
7849 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode()))
7850 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7851
7852 SDValue Res = DAG.getMergeValues(makeArrayRef(ArgValues.data(), NumValues),
7853 SDB->getCurSDLoc());
7854
7855 SDB->setValue(I, Res);
7856 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) {
7857 if (LoadSDNode *LNode =
7858 dyn_cast<LoadSDNode>(Res.getOperand(0).getNode()))
7859 if (FrameIndexSDNode *FI =
7860 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
7861 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7862 }
7863
7864 // If this argument is live outside of the entry block, insert a copy from
7865 // wherever we got it to the vreg that other BB's will reference it as.
7866 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) {
7867 // If we can, though, try to skip creating an unnecessary vreg.
7868 // FIXME: This isn't very clean... it would be nice to make this more
7869 // general. It's also subtly incompatible with the hacks FastISel
7870 // uses with vregs.
7871 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg();
7872 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
7873 FuncInfo->ValueMap[I] = Reg;
7874 continue;
7875 }
7876 }
7877 if (!isOnlyUsedInEntryBlock(I, TM.Options.EnableFastISel)) {
7878 FuncInfo->InitializeRegForValue(I);
7879 SDB->CopyToExportRegsIfNeeded(I);
7880 }
7881 }
7882
7883 assert(i == InVals.size() && "Argument register count mismatch!")((i == InVals.size() && "Argument register count mismatch!"
) ? static_cast<void> (0) : __assert_fail ("i == InVals.size() && \"Argument register count mismatch!\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7883, __PRETTY_FUNCTION__));
7884
7885 // Finally, if the target has anything special to do, allow it to do so.
7886 EmitFunctionEntryCode();
7887}
7888
7889/// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
7890/// ensure constants are generated when needed. Remember the virtual registers
7891/// that need to be added to the Machine PHI nodes as input. We cannot just
7892/// directly add them, because expansion might result in multiple MBB's for one
7893/// BB. As such, the start of the BB might correspond to a different MBB than
7894/// the end.
7895///
7896void
7897SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
7898 const TerminatorInst *TI = LLVMBB->getTerminator();
7899
7900 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
7901
7902 // Check successor nodes' PHI nodes that expect a constant to be available
7903 // from this block.
7904 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
7905 const BasicBlock *SuccBB = TI->getSuccessor(succ);
7906 if (!isa<PHINode>(SuccBB->begin())) continue;
7907 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
7908
7909 // If this terminator has multiple identical successors (common for
7910 // switches), only handle each succ once.
7911 if (!SuccsHandled.insert(SuccMBB).second)
7912 continue;
7913
7914 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
7915
7916 // At this point we know that there is a 1-1 correspondence between LLVM PHI
7917 // nodes and Machine PHI nodes, but the incoming operands have not been
7918 // emitted yet.
7919 for (BasicBlock::const_iterator I = SuccBB->begin();
7920 const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
7921 // Ignore dead phi's.
7922 if (PN->use_empty()) continue;
7923
7924 // Skip empty types
7925 if (PN->getType()->isEmptyTy())
7926 continue;
7927
7928 unsigned Reg;
7929 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
7930
7931 if (const Constant *C = dyn_cast<Constant>(PHIOp)) {
7932 unsigned &RegOut = ConstantsOut[C];
7933 if (RegOut == 0) {
7934 RegOut = FuncInfo.CreateRegs(C->getType());
7935 CopyValueToVirtualRegister(C, RegOut);
7936 }
7937 Reg = RegOut;
7938 } else {
7939 DenseMap<const Value *, unsigned>::iterator I =
7940 FuncInfo.ValueMap.find(PHIOp);
7941 if (I != FuncInfo.ValueMap.end())
7942 Reg = I->second;
7943 else {
7944 assert(isa<AllocaInst>(PHIOp) &&((isa<AllocaInst>(PHIOp) && FuncInfo.StaticAllocaMap
.count(cast<AllocaInst>(PHIOp)) && "Didn't codegen value into a register!??"
) ? static_cast<void> (0) : __assert_fail ("isa<AllocaInst>(PHIOp) && FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) && \"Didn't codegen value into a register!??\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7946, __PRETTY_FUNCTION__))
7945 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&((isa<AllocaInst>(PHIOp) && FuncInfo.StaticAllocaMap
.count(cast<AllocaInst>(PHIOp)) && "Didn't codegen value into a register!??"
) ? static_cast<void> (0) : __assert_fail ("isa<AllocaInst>(PHIOp) && FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) && \"Didn't codegen value into a register!??\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7946, __PRETTY_FUNCTION__))
7946 "Didn't codegen value into a register!??")((isa<AllocaInst>(PHIOp) && FuncInfo.StaticAllocaMap
.count(cast<AllocaInst>(PHIOp)) && "Didn't codegen value into a register!??"
) ? static_cast<void> (0) : __assert_fail ("isa<AllocaInst>(PHIOp) && FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) && \"Didn't codegen value into a register!??\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn230682/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7946, __PRETTY_FUNCTION__));
7947 Reg = FuncInfo.CreateRegs(PHIOp->getType());
7948 CopyValueToVirtualRegister(PHIOp, Reg);
7949 }
7950 }
7951
7952 // Remember that this register needs to added to the machine PHI node as
7953 // the input for this MBB.
7954 SmallVector<EVT, 4> ValueVTs;
7955 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7956 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
7957 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
7958 EVT VT = ValueVTs[vti];
7959 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT);
7960 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
7961 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
7962 Reg += NumRegisters;
7963 }
7964 }
7965 }
7966
7967 ConstantsOut.clear();
7968}
7969
7970/// Add a successor MBB to ParentMBB< creating a new MachineBB for BB if SuccMBB
7971/// is 0.
7972MachineBasicBlock *
7973SelectionDAGBuilder::StackProtectorDescriptor::
7974AddSuccessorMBB(const BasicBlock *BB,
7975 MachineBasicBlock *ParentMBB,
7976 bool IsLikely,
7977 MachineBasicBlock *SuccMBB) {
7978 // If SuccBB has not been created yet, create it.
7979 if (!SuccMBB) {
7980 MachineFunction *MF = ParentMBB->getParent();
7981 MachineFunction::iterator BBI = ParentMBB;
7982 SuccMBB = MF->CreateMachineBasicBlock(BB);
7983 MF->insert(++BBI, SuccMBB);
7984 }
7985 // Add it as a successor of ParentMBB.
7986 ParentMBB->addSuccessor(
7987 SuccMBB, BranchProbabilityInfo::getBranchWeightStackProtector(IsLikely));
7988 return SuccMBB;
7989}