Bug Summary

File:lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
Warning:line 6697, column 14
Called C++ object pointer is null

Annotated Source Code

1//===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This implements routines for translating from LLVM IR into SelectionDAG IR.
11//
12//===----------------------------------------------------------------------===//
13
14#include "SelectionDAGBuilder.h"
15#include "SDNodeDbgValue.h"
16#include "llvm/ADT/BitVector.h"
17#include "llvm/ADT/Optional.h"
18#include "llvm/ADT/SmallSet.h"
19#include "llvm/ADT/Statistic.h"
20#include "llvm/Analysis/AliasAnalysis.h"
21#include "llvm/Analysis/BranchProbabilityInfo.h"
22#include "llvm/Analysis/ConstantFolding.h"
23#include "llvm/Analysis/Loads.h"
24#include "llvm/Analysis/TargetLibraryInfo.h"
25#include "llvm/Analysis/ValueTracking.h"
26#include "llvm/Analysis/VectorUtils.h"
27#include "llvm/CodeGen/Analysis.h"
28#include "llvm/CodeGen/FastISel.h"
29#include "llvm/CodeGen/FunctionLoweringInfo.h"
30#include "llvm/CodeGen/GCMetadata.h"
31#include "llvm/CodeGen/GCStrategy.h"
32#include "llvm/CodeGen/MachineFrameInfo.h"
33#include "llvm/CodeGen/MachineFunction.h"
34#include "llvm/CodeGen/MachineInstrBuilder.h"
35#include "llvm/CodeGen/MachineJumpTableInfo.h"
36#include "llvm/CodeGen/MachineModuleInfo.h"
37#include "llvm/CodeGen/MachineRegisterInfo.h"
38#include "llvm/CodeGen/SelectionDAG.h"
39#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
40#include "llvm/CodeGen/StackMaps.h"
41#include "llvm/CodeGen/WinEHFuncInfo.h"
42#include "llvm/IR/CallingConv.h"
43#include "llvm/IR/ConstantRange.h"
44#include "llvm/IR/Constants.h"
45#include "llvm/IR/DataLayout.h"
46#include "llvm/IR/DebugInfo.h"
47#include "llvm/IR/DerivedTypes.h"
48#include "llvm/IR/Function.h"
49#include "llvm/IR/GetElementPtrTypeIterator.h"
50#include "llvm/IR/GlobalVariable.h"
51#include "llvm/IR/InlineAsm.h"
52#include "llvm/IR/Instructions.h"
53#include "llvm/IR/IntrinsicInst.h"
54#include "llvm/IR/Intrinsics.h"
55#include "llvm/IR/LLVMContext.h"
56#include "llvm/IR/Module.h"
57#include "llvm/IR/Statepoint.h"
58#include "llvm/MC/MCSymbol.h"
59#include "llvm/Support/CommandLine.h"
60#include "llvm/Support/Debug.h"
61#include "llvm/Support/ErrorHandling.h"
62#include "llvm/Support/MathExtras.h"
63#include "llvm/Support/raw_ostream.h"
64#include "llvm/Target/TargetFrameLowering.h"
65#include "llvm/Target/TargetInstrInfo.h"
66#include "llvm/Target/TargetIntrinsicInfo.h"
67#include "llvm/Target/TargetLowering.h"
68#include "llvm/Target/TargetOptions.h"
69#include "llvm/Target/TargetSubtargetInfo.h"
70#include <algorithm>
71#include <utility>
72using namespace llvm;
73
74#define DEBUG_TYPE"isel" "isel"
75
76/// LimitFloatPrecision - Generate low-precision inline sequences for
77/// some float libcalls (6, 8 or 12 bits).
78static unsigned LimitFloatPrecision;
79
80static cl::opt<unsigned, true>
81LimitFPPrecision("limit-float-precision",
82 cl::desc("Generate low-precision inline sequences "
83 "for some float libcalls"),
84 cl::location(LimitFloatPrecision),
85 cl::init(0));
86
87static cl::opt<bool>
88EnableFMFInDAG("enable-fmf-dag", cl::init(true), cl::Hidden,
89 cl::desc("Enable fast-math-flags for DAG nodes"));
90
91/// Minimum jump table density for normal functions.
92static cl::opt<unsigned>
93JumpTableDensity("jump-table-density", cl::init(10), cl::Hidden,
94 cl::desc("Minimum density for building a jump table in "
95 "a normal function"));
96
97/// Minimum jump table density for -Os or -Oz functions.
98static cl::opt<unsigned>
99OptsizeJumpTableDensity("optsize-jump-table-density", cl::init(40), cl::Hidden,
100 cl::desc("Minimum density for building a jump table in "
101 "an optsize function"));
102
103
104// Limit the width of DAG chains. This is important in general to prevent
105// DAG-based analysis from blowing up. For example, alias analysis and
106// load clustering may not complete in reasonable time. It is difficult to
107// recognize and avoid this situation within each individual analysis, and
108// future analyses are likely to have the same behavior. Limiting DAG width is
109// the safe approach and will be especially important with global DAGs.
110//
111// MaxParallelChains default is arbitrarily high to avoid affecting
112// optimization, but could be lowered to improve compile time. Any ld-ld-st-st
113// sequence over this should have been converted to llvm.memcpy by the
114// frontend. It is easy to induce this behavior with .ll code such as:
115// %buffer = alloca [4096 x i8]
116// %data = load [4096 x i8]* %argPtr
117// store [4096 x i8] %data, [4096 x i8]* %buffer
118static const unsigned MaxParallelChains = 64;
119
120static SDValue getCopyFromPartsVector(SelectionDAG &DAG, const SDLoc &DL,
121 const SDValue *Parts, unsigned NumParts,
122 MVT PartVT, EVT ValueVT, const Value *V);
123
124/// getCopyFromParts - Create a value that contains the specified legal parts
125/// combined into the value they represent. If the parts combine to a type
126/// larger than ValueVT then AssertOp can be used to specify whether the extra
127/// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
128/// (ISD::AssertSext).
129static SDValue getCopyFromParts(SelectionDAG &DAG, const SDLoc &DL,
130 const SDValue *Parts, unsigned NumParts,
131 MVT PartVT, EVT ValueVT, const Value *V,
132 Optional<ISD::NodeType> AssertOp = None) {
133 if (ValueVT.isVector())
134 return getCopyFromPartsVector(DAG, DL, Parts, NumParts,
135 PartVT, ValueVT, V);
136
137 assert(NumParts > 0 && "No parts to assemble!")((NumParts > 0 && "No parts to assemble!") ? static_cast
<void> (0) : __assert_fail ("NumParts > 0 && \"No parts to assemble!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 137, __PRETTY_FUNCTION__))
;
138 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
139 SDValue Val = Parts[0];
140
141 if (NumParts > 1) {
142 // Assemble the value from multiple parts.
143 if (ValueVT.isInteger()) {
144 unsigned PartBits = PartVT.getSizeInBits();
145 unsigned ValueBits = ValueVT.getSizeInBits();
146
147 // Assemble the power of 2 part.
148 unsigned RoundParts = NumParts & (NumParts - 1) ?
149 1 << Log2_32(NumParts) : NumParts;
150 unsigned RoundBits = PartBits * RoundParts;
151 EVT RoundVT = RoundBits == ValueBits ?
152 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
153 SDValue Lo, Hi;
154
155 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
156
157 if (RoundParts > 2) {
158 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2,
159 PartVT, HalfVT, V);
160 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2,
161 RoundParts / 2, PartVT, HalfVT, V);
162 } else {
163 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]);
164 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]);
165 }
166
167 if (DAG.getDataLayout().isBigEndian())
168 std::swap(Lo, Hi);
169
170 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
171
172 if (RoundParts < NumParts) {
173 // Assemble the trailing non-power-of-2 part.
174 unsigned OddParts = NumParts - RoundParts;
175 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
176 Hi = getCopyFromParts(DAG, DL,
177 Parts + RoundParts, OddParts, PartVT, OddVT, V);
178
179 // Combine the round and odd parts.
180 Lo = Val;
181 if (DAG.getDataLayout().isBigEndian())
182 std::swap(Lo, Hi);
183 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
184 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi);
185 Hi =
186 DAG.getNode(ISD::SHL, DL, TotalVT, Hi,
187 DAG.getConstant(Lo.getValueSizeInBits(), DL,
188 TLI.getPointerTy(DAG.getDataLayout())));
189 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo);
190 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi);
191 }
192 } else if (PartVT.isFloatingPoint()) {
193 // FP split into multiple FP parts (for ppcf128)
194 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 &&((ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 &&
"Unexpected split") ? static_cast<void> (0) : __assert_fail
("ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 && \"Unexpected split\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 195, __PRETTY_FUNCTION__))
195 "Unexpected split")((ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 &&
"Unexpected split") ? static_cast<void> (0) : __assert_fail
("ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 && \"Unexpected split\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 195, __PRETTY_FUNCTION__))
;
196 SDValue Lo, Hi;
197 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]);
198 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]);
199 if (TLI.hasBigEndianPartOrdering(ValueVT, DAG.getDataLayout()))
200 std::swap(Lo, Hi);
201 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi);
202 } else {
203 // FP split into integer parts (soft fp)
204 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&((ValueVT.isFloatingPoint() && PartVT.isInteger() &&
!PartVT.isVector() && "Unexpected split") ? static_cast
<void> (0) : __assert_fail ("ValueVT.isFloatingPoint() && PartVT.isInteger() && !PartVT.isVector() && \"Unexpected split\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 205, __PRETTY_FUNCTION__))
205 !PartVT.isVector() && "Unexpected split")((ValueVT.isFloatingPoint() && PartVT.isInteger() &&
!PartVT.isVector() && "Unexpected split") ? static_cast
<void> (0) : __assert_fail ("ValueVT.isFloatingPoint() && PartVT.isInteger() && !PartVT.isVector() && \"Unexpected split\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 205, __PRETTY_FUNCTION__))
;
206 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
207 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT, V);
208 }
209 }
210
211 // There is now one part, held in Val. Correct it to match ValueVT.
212 // PartEVT is the type of the register class that holds the value.
213 // ValueVT is the type of the inline asm operation.
214 EVT PartEVT = Val.getValueType();
215
216 if (PartEVT == ValueVT)
217 return Val;
218
219 if (PartEVT.isInteger() && ValueVT.isFloatingPoint() &&
220 ValueVT.bitsLT(PartEVT)) {
221 // For an FP value in an integer part, we need to truncate to the right
222 // width first.
223 PartEVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
224 Val = DAG.getNode(ISD::TRUNCATE, DL, PartEVT, Val);
225 }
226
227 // Handle types that have the same size.
228 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits())
229 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
230
231 // Handle types with different sizes.
232 if (PartEVT.isInteger() && ValueVT.isInteger()) {
233 if (ValueVT.bitsLT(PartEVT)) {
234 // For a truncate, see if we have any information to
235 // indicate whether the truncated bits will always be
236 // zero or sign-extension.
237 if (AssertOp.hasValue())
238 Val = DAG.getNode(*AssertOp, DL, PartEVT, Val,
239 DAG.getValueType(ValueVT));
240 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
241 }
242 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val);
243 }
244
245 if (PartEVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
246 // FP_ROUND's are always exact here.
247 if (ValueVT.bitsLT(Val.getValueType()))
248 return DAG.getNode(
249 ISD::FP_ROUND, DL, ValueVT, Val,
250 DAG.getTargetConstant(1, DL, TLI.getPointerTy(DAG.getDataLayout())));
251
252 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);
253 }
254
255 llvm_unreachable("Unknown mismatch!")::llvm::llvm_unreachable_internal("Unknown mismatch!", "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 255)
;
256}
257
258static void diagnosePossiblyInvalidConstraint(LLVMContext &Ctx, const Value *V,
259 const Twine &ErrMsg) {
260 const Instruction *I = dyn_cast_or_null<Instruction>(V);
261 if (!V)
262 return Ctx.emitError(ErrMsg);
263
264 const char *AsmError = ", possible invalid constraint for vector type";
265 if (const CallInst *CI = dyn_cast<CallInst>(I))
266 if (isa<InlineAsm>(CI->getCalledValue()))
267 return Ctx.emitError(I, ErrMsg + AsmError);
268
269 return Ctx.emitError(I, ErrMsg);
270}
271
272/// getCopyFromPartsVector - Create a value that contains the specified legal
273/// parts combined into the value they represent. If the parts combine to a
274/// type larger than ValueVT then AssertOp can be used to specify whether the
275/// extra bits are known to be zero (ISD::AssertZext) or sign extended from
276/// ValueVT (ISD::AssertSext).
277static SDValue getCopyFromPartsVector(SelectionDAG &DAG, const SDLoc &DL,
278 const SDValue *Parts, unsigned NumParts,
279 MVT PartVT, EVT ValueVT, const Value *V) {
280 assert(ValueVT.isVector() && "Not a vector value")((ValueVT.isVector() && "Not a vector value") ? static_cast
<void> (0) : __assert_fail ("ValueVT.isVector() && \"Not a vector value\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 280, __PRETTY_FUNCTION__))
;
281 assert(NumParts > 0 && "No parts to assemble!")((NumParts > 0 && "No parts to assemble!") ? static_cast
<void> (0) : __assert_fail ("NumParts > 0 && \"No parts to assemble!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 281, __PRETTY_FUNCTION__))
;
282 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
283 SDValue Val = Parts[0];
284
285 // Handle a multi-element vector.
286 if (NumParts > 1) {
287 EVT IntermediateVT;
288 MVT RegisterVT;
289 unsigned NumIntermediates;
290 unsigned NumRegs =
291 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
292 NumIntermediates, RegisterVT);
293 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!")((NumRegs == NumParts && "Part count doesn't match vector breakdown!"
) ? static_cast<void> (0) : __assert_fail ("NumRegs == NumParts && \"Part count doesn't match vector breakdown!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 293, __PRETTY_FUNCTION__))
;
294 NumParts = NumRegs; // Silence a compiler warning.
295 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!")((RegisterVT == PartVT && "Part type doesn't match vector breakdown!"
) ? static_cast<void> (0) : __assert_fail ("RegisterVT == PartVT && \"Part type doesn't match vector breakdown!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 295, __PRETTY_FUNCTION__))
;
296 assert(RegisterVT.getSizeInBits() ==((RegisterVT.getSizeInBits() == Parts[0].getSimpleValueType()
.getSizeInBits() && "Part type sizes don't match!") ?
static_cast<void> (0) : __assert_fail ("RegisterVT.getSizeInBits() == Parts[0].getSimpleValueType().getSizeInBits() && \"Part type sizes don't match!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 298, __PRETTY_FUNCTION__))
297 Parts[0].getSimpleValueType().getSizeInBits() &&((RegisterVT.getSizeInBits() == Parts[0].getSimpleValueType()
.getSizeInBits() && "Part type sizes don't match!") ?
static_cast<void> (0) : __assert_fail ("RegisterVT.getSizeInBits() == Parts[0].getSimpleValueType().getSizeInBits() && \"Part type sizes don't match!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 298, __PRETTY_FUNCTION__))
298 "Part type sizes don't match!")((RegisterVT.getSizeInBits() == Parts[0].getSimpleValueType()
.getSizeInBits() && "Part type sizes don't match!") ?
static_cast<void> (0) : __assert_fail ("RegisterVT.getSizeInBits() == Parts[0].getSimpleValueType().getSizeInBits() && \"Part type sizes don't match!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 298, __PRETTY_FUNCTION__))
;
299
300 // Assemble the parts into intermediate operands.
301 SmallVector<SDValue, 8> Ops(NumIntermediates);
302 if (NumIntermediates == NumParts) {
303 // If the register was not expanded, truncate or copy the value,
304 // as appropriate.
305 for (unsigned i = 0; i != NumParts; ++i)
306 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1,
307 PartVT, IntermediateVT, V);
308 } else if (NumParts > 0) {
309 // If the intermediate type was expanded, build the intermediate
310 // operands from the parts.
311 assert(NumParts % NumIntermediates == 0 &&((NumParts % NumIntermediates == 0 && "Must expand into a divisible number of parts!"
) ? static_cast<void> (0) : __assert_fail ("NumParts % NumIntermediates == 0 && \"Must expand into a divisible number of parts!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 312, __PRETTY_FUNCTION__))
312 "Must expand into a divisible number of parts!")((NumParts % NumIntermediates == 0 && "Must expand into a divisible number of parts!"
) ? static_cast<void> (0) : __assert_fail ("NumParts % NumIntermediates == 0 && \"Must expand into a divisible number of parts!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 312, __PRETTY_FUNCTION__))
;
313 unsigned Factor = NumParts / NumIntermediates;
314 for (unsigned i = 0; i != NumIntermediates; ++i)
315 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor,
316 PartVT, IntermediateVT, V);
317 }
318
319 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
320 // intermediate operands.
321 Val = DAG.getNode(IntermediateVT.isVector() ? ISD::CONCAT_VECTORS
322 : ISD::BUILD_VECTOR,
323 DL, ValueVT, Ops);
324 }
325
326 // There is now one part, held in Val. Correct it to match ValueVT.
327 EVT PartEVT = Val.getValueType();
328
329 if (PartEVT == ValueVT)
330 return Val;
331
332 if (PartEVT.isVector()) {
333 // If the element type of the source/dest vectors are the same, but the
334 // parts vector has more elements than the value vector, then we have a
335 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the
336 // elements we want.
337 if (PartEVT.getVectorElementType() == ValueVT.getVectorElementType()) {
338 assert(PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements() &&((PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements
() && "Cannot narrow, it would be a lossy transformation"
) ? static_cast<void> (0) : __assert_fail ("PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements() && \"Cannot narrow, it would be a lossy transformation\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 339, __PRETTY_FUNCTION__))
339 "Cannot narrow, it would be a lossy transformation")((PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements
() && "Cannot narrow, it would be a lossy transformation"
) ? static_cast<void> (0) : __assert_fail ("PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements() && \"Cannot narrow, it would be a lossy transformation\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 339, __PRETTY_FUNCTION__))
;
340 return DAG.getNode(
341 ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
342 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
343 }
344
345 // Vector/Vector bitcast.
346 if (ValueVT.getSizeInBits() == PartEVT.getSizeInBits())
347 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
348
349 assert(PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements() &&((PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements
() && "Cannot handle this kind of promotion") ? static_cast
<void> (0) : __assert_fail ("PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements() && \"Cannot handle this kind of promotion\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 350, __PRETTY_FUNCTION__))
350 "Cannot handle this kind of promotion")((PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements
() && "Cannot handle this kind of promotion") ? static_cast
<void> (0) : __assert_fail ("PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements() && \"Cannot handle this kind of promotion\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 350, __PRETTY_FUNCTION__))
;
351 // Promoted vector extract
352 return DAG.getAnyExtOrTrunc(Val, DL, ValueVT);
353
354 }
355
356 // Trivial bitcast if the types are the same size and the destination
357 // vector type is legal.
358 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits() &&
359 TLI.isTypeLegal(ValueVT))
360 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
361
362 // Handle cases such as i8 -> <1 x i1>
363 if (ValueVT.getVectorNumElements() != 1) {
364 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
365 "non-trivial scalar-to-vector conversion");
366 return DAG.getUNDEF(ValueVT);
367 }
368
369 if (ValueVT.getVectorNumElements() == 1 &&
370 ValueVT.getVectorElementType() != PartEVT)
371 Val = DAG.getAnyExtOrTrunc(Val, DL, ValueVT.getScalarType());
372
373 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val);
374}
375
376static void getCopyToPartsVector(SelectionDAG &DAG, const SDLoc &dl,
377 SDValue Val, SDValue *Parts, unsigned NumParts,
378 MVT PartVT, const Value *V);
379
380/// getCopyToParts - Create a series of nodes that contain the specified value
381/// split into legal parts. If the parts contain more bits than Val, then, for
382/// integers, ExtendKind can be used to specify how to generate the extra bits.
383static void getCopyToParts(SelectionDAG &DAG, const SDLoc &DL, SDValue Val,
384 SDValue *Parts, unsigned NumParts, MVT PartVT,
385 const Value *V,
386 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
387 EVT ValueVT = Val.getValueType();
388
389 // Handle the vector case separately.
390 if (ValueVT.isVector())
391 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT, V);
392
393 unsigned PartBits = PartVT.getSizeInBits();
394 unsigned OrigNumParts = NumParts;
395 assert(DAG.getTargetLoweringInfo().isTypeLegal(PartVT) &&((DAG.getTargetLoweringInfo().isTypeLegal(PartVT) && "Copying to an illegal type!"
) ? static_cast<void> (0) : __assert_fail ("DAG.getTargetLoweringInfo().isTypeLegal(PartVT) && \"Copying to an illegal type!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 396, __PRETTY_FUNCTION__))
396 "Copying to an illegal type!")((DAG.getTargetLoweringInfo().isTypeLegal(PartVT) && "Copying to an illegal type!"
) ? static_cast<void> (0) : __assert_fail ("DAG.getTargetLoweringInfo().isTypeLegal(PartVT) && \"Copying to an illegal type!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 396, __PRETTY_FUNCTION__))
;
397
398 if (NumParts == 0)
399 return;
400
401 assert(!ValueVT.isVector() && "Vector case handled elsewhere")((!ValueVT.isVector() && "Vector case handled elsewhere"
) ? static_cast<void> (0) : __assert_fail ("!ValueVT.isVector() && \"Vector case handled elsewhere\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 401, __PRETTY_FUNCTION__))
;
402 EVT PartEVT = PartVT;
403 if (PartEVT == ValueVT) {
404 assert(NumParts == 1 && "No-op copy with multiple parts!")((NumParts == 1 && "No-op copy with multiple parts!")
? static_cast<void> (0) : __assert_fail ("NumParts == 1 && \"No-op copy with multiple parts!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 404, __PRETTY_FUNCTION__))
;
405 Parts[0] = Val;
406 return;
407 }
408
409 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
410 // If the parts cover more bits than the value has, promote the value.
411 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
412 assert(NumParts == 1 && "Do not know what to promote to!")((NumParts == 1 && "Do not know what to promote to!")
? static_cast<void> (0) : __assert_fail ("NumParts == 1 && \"Do not know what to promote to!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 412, __PRETTY_FUNCTION__))
;
413 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val);
414 } else {
415 if (ValueVT.isFloatingPoint()) {
416 // FP values need to be bitcast, then extended if they are being put
417 // into a larger container.
418 ValueVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
419 Val = DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
420 }
421 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&(((PartVT.isInteger() || PartVT == MVT::x86mmx) && ValueVT
.isInteger() && "Unknown mismatch!") ? static_cast<
void> (0) : __assert_fail ("(PartVT.isInteger() || PartVT == MVT::x86mmx) && ValueVT.isInteger() && \"Unknown mismatch!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 423, __PRETTY_FUNCTION__))
422 ValueVT.isInteger() &&(((PartVT.isInteger() || PartVT == MVT::x86mmx) && ValueVT
.isInteger() && "Unknown mismatch!") ? static_cast<
void> (0) : __assert_fail ("(PartVT.isInteger() || PartVT == MVT::x86mmx) && ValueVT.isInteger() && \"Unknown mismatch!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 423, __PRETTY_FUNCTION__))
423 "Unknown mismatch!")(((PartVT.isInteger() || PartVT == MVT::x86mmx) && ValueVT
.isInteger() && "Unknown mismatch!") ? static_cast<
void> (0) : __assert_fail ("(PartVT.isInteger() || PartVT == MVT::x86mmx) && ValueVT.isInteger() && \"Unknown mismatch!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 423, __PRETTY_FUNCTION__))
;
424 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
425 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val);
426 if (PartVT == MVT::x86mmx)
427 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
428 }
429 } else if (PartBits == ValueVT.getSizeInBits()) {
430 // Different types of the same size.
431 assert(NumParts == 1 && PartEVT != ValueVT)((NumParts == 1 && PartEVT != ValueVT) ? static_cast<
void> (0) : __assert_fail ("NumParts == 1 && PartEVT != ValueVT"
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 431, __PRETTY_FUNCTION__))
;
432 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
433 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
434 // If the parts cover less bits than value has, truncate the value.
435 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&(((PartVT.isInteger() || PartVT == MVT::x86mmx) && ValueVT
.isInteger() && "Unknown mismatch!") ? static_cast<
void> (0) : __assert_fail ("(PartVT.isInteger() || PartVT == MVT::x86mmx) && ValueVT.isInteger() && \"Unknown mismatch!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 437, __PRETTY_FUNCTION__))
436 ValueVT.isInteger() &&(((PartVT.isInteger() || PartVT == MVT::x86mmx) && ValueVT
.isInteger() && "Unknown mismatch!") ? static_cast<
void> (0) : __assert_fail ("(PartVT.isInteger() || PartVT == MVT::x86mmx) && ValueVT.isInteger() && \"Unknown mismatch!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 437, __PRETTY_FUNCTION__))
437 "Unknown mismatch!")(((PartVT.isInteger() || PartVT == MVT::x86mmx) && ValueVT
.isInteger() && "Unknown mismatch!") ? static_cast<
void> (0) : __assert_fail ("(PartVT.isInteger() || PartVT == MVT::x86mmx) && ValueVT.isInteger() && \"Unknown mismatch!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 437, __PRETTY_FUNCTION__))
;
438 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
439 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
440 if (PartVT == MVT::x86mmx)
441 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
442 }
443
444 // The value may have changed - recompute ValueVT.
445 ValueVT = Val.getValueType();
446 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&((NumParts * PartBits == ValueVT.getSizeInBits() && "Failed to tile the value with PartVT!"
) ? static_cast<void> (0) : __assert_fail ("NumParts * PartBits == ValueVT.getSizeInBits() && \"Failed to tile the value with PartVT!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 447, __PRETTY_FUNCTION__))
447 "Failed to tile the value with PartVT!")((NumParts * PartBits == ValueVT.getSizeInBits() && "Failed to tile the value with PartVT!"
) ? static_cast<void> (0) : __assert_fail ("NumParts * PartBits == ValueVT.getSizeInBits() && \"Failed to tile the value with PartVT!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 447, __PRETTY_FUNCTION__))
;
448
449 if (NumParts == 1) {
450 if (PartEVT != ValueVT) {
451 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
452 "scalar-to-vector conversion failed");
453 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
454 }
455
456 Parts[0] = Val;
457 return;
458 }
459
460 // Expand the value into multiple parts.
461 if (NumParts & (NumParts - 1)) {
462 // The number of parts is not a power of 2. Split off and copy the tail.
463 assert(PartVT.isInteger() && ValueVT.isInteger() &&((PartVT.isInteger() && ValueVT.isInteger() &&
"Do not know what to expand to!") ? static_cast<void> (
0) : __assert_fail ("PartVT.isInteger() && ValueVT.isInteger() && \"Do not know what to expand to!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 464, __PRETTY_FUNCTION__))
464 "Do not know what to expand to!")((PartVT.isInteger() && ValueVT.isInteger() &&
"Do not know what to expand to!") ? static_cast<void> (
0) : __assert_fail ("PartVT.isInteger() && ValueVT.isInteger() && \"Do not know what to expand to!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 464, __PRETTY_FUNCTION__))
;
465 unsigned RoundParts = 1 << Log2_32(NumParts);
466 unsigned RoundBits = RoundParts * PartBits;
467 unsigned OddParts = NumParts - RoundParts;
468 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val,
469 DAG.getIntPtrConstant(RoundBits, DL));
470 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT, V);
471
472 if (DAG.getDataLayout().isBigEndian())
473 // The odd parts were reversed by getCopyToParts - unreverse them.
474 std::reverse(Parts + RoundParts, Parts + NumParts);
475
476 NumParts = RoundParts;
477 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
478 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
479 }
480
481 // The number of parts is a power of 2. Repeatedly bisect the value using
482 // EXTRACT_ELEMENT.
483 Parts[0] = DAG.getNode(ISD::BITCAST, DL,
484 EVT::getIntegerVT(*DAG.getContext(),
485 ValueVT.getSizeInBits()),
486 Val);
487
488 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
489 for (unsigned i = 0; i < NumParts; i += StepSize) {
490 unsigned ThisBits = StepSize * PartBits / 2;
491 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
492 SDValue &Part0 = Parts[i];
493 SDValue &Part1 = Parts[i+StepSize/2];
494
495 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
496 ThisVT, Part0, DAG.getIntPtrConstant(1, DL));
497 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
498 ThisVT, Part0, DAG.getIntPtrConstant(0, DL));
499
500 if (ThisBits == PartBits && ThisVT != PartVT) {
501 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0);
502 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1);
503 }
504 }
505 }
506
507 if (DAG.getDataLayout().isBigEndian())
508 std::reverse(Parts, Parts + OrigNumParts);
509}
510
511
512/// getCopyToPartsVector - Create a series of nodes that contain the specified
513/// value split into legal parts.
514static void getCopyToPartsVector(SelectionDAG &DAG, const SDLoc &DL,
515 SDValue Val, SDValue *Parts, unsigned NumParts,
516 MVT PartVT, const Value *V) {
517 EVT ValueVT = Val.getValueType();
518 assert(ValueVT.isVector() && "Not a vector")((ValueVT.isVector() && "Not a vector") ? static_cast
<void> (0) : __assert_fail ("ValueVT.isVector() && \"Not a vector\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 518, __PRETTY_FUNCTION__))
;
519 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
520
521 if (NumParts == 1) {
522 EVT PartEVT = PartVT;
523 if (PartEVT == ValueVT) {
524 // Nothing to do.
525 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
526 // Bitconvert vector->vector case.
527 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
528 } else if (PartVT.isVector() &&
529 PartEVT.getVectorElementType() == ValueVT.getVectorElementType() &&
530 PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements()) {
531 EVT ElementVT = PartVT.getVectorElementType();
532 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in
533 // undef elements.
534 SmallVector<SDValue, 16> Ops;
535 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i)
536 Ops.push_back(DAG.getNode(
537 ISD::EXTRACT_VECTOR_ELT, DL, ElementVT, Val,
538 DAG.getConstant(i, DL, TLI.getVectorIdxTy(DAG.getDataLayout()))));
539
540 for (unsigned i = ValueVT.getVectorNumElements(),
541 e = PartVT.getVectorNumElements(); i != e; ++i)
542 Ops.push_back(DAG.getUNDEF(ElementVT));
543
544 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, Ops);
545
546 // FIXME: Use CONCAT for 2x -> 4x.
547
548 //SDValue UndefElts = DAG.getUNDEF(VectorTy);
549 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts);
550 } else if (PartVT.isVector() &&
551 PartEVT.getVectorElementType().bitsGE(
552 ValueVT.getVectorElementType()) &&
553 PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements()) {
554
555 // Promoted vector extract
556 Val = DAG.getAnyExtOrTrunc(Val, DL, PartVT);
557 } else{
558 // Vector -> scalar conversion.
559 assert(ValueVT.getVectorNumElements() == 1 &&((ValueVT.getVectorNumElements() == 1 && "Only trivial vector-to-scalar conversions should get here!"
) ? static_cast<void> (0) : __assert_fail ("ValueVT.getVectorNumElements() == 1 && \"Only trivial vector-to-scalar conversions should get here!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 560, __PRETTY_FUNCTION__))
560 "Only trivial vector-to-scalar conversions should get here!")((ValueVT.getVectorNumElements() == 1 && "Only trivial vector-to-scalar conversions should get here!"
) ? static_cast<void> (0) : __assert_fail ("ValueVT.getVectorNumElements() == 1 && \"Only trivial vector-to-scalar conversions should get here!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 560, __PRETTY_FUNCTION__))
;
561 Val = DAG.getNode(
562 ISD::EXTRACT_VECTOR_ELT, DL, PartVT, Val,
563 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
564
565 Val = DAG.getAnyExtOrTrunc(Val, DL, PartVT);
566 }
567
568 Parts[0] = Val;
569 return;
570 }
571
572 // Handle a multi-element vector.
573 EVT IntermediateVT;
574 MVT RegisterVT;
575 unsigned NumIntermediates;
576 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
577 IntermediateVT,
578 NumIntermediates, RegisterVT);
579 unsigned NumElements = ValueVT.getVectorNumElements();
580
581 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!")((NumRegs == NumParts && "Part count doesn't match vector breakdown!"
) ? static_cast<void> (0) : __assert_fail ("NumRegs == NumParts && \"Part count doesn't match vector breakdown!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 581, __PRETTY_FUNCTION__))
;
582 NumParts = NumRegs; // Silence a compiler warning.
583 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!")((RegisterVT == PartVT && "Part type doesn't match vector breakdown!"
) ? static_cast<void> (0) : __assert_fail ("RegisterVT == PartVT && \"Part type doesn't match vector breakdown!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 583, __PRETTY_FUNCTION__))
;
584
585 // Split the vector into intermediate operands.
586 SmallVector<SDValue, 8> Ops(NumIntermediates);
587 for (unsigned i = 0; i != NumIntermediates; ++i) {
588 if (IntermediateVT.isVector())
589 Ops[i] =
590 DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, IntermediateVT, Val,
591 DAG.getConstant(i * (NumElements / NumIntermediates), DL,
592 TLI.getVectorIdxTy(DAG.getDataLayout())));
593 else
594 Ops[i] = DAG.getNode(
595 ISD::EXTRACT_VECTOR_ELT, DL, IntermediateVT, Val,
596 DAG.getConstant(i, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
597 }
598
599 // Split the intermediate operands into legal parts.
600 if (NumParts == NumIntermediates) {
601 // If the register was not expanded, promote or copy the value,
602 // as appropriate.
603 for (unsigned i = 0; i != NumParts; ++i)
604 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT, V);
605 } else if (NumParts > 0) {
606 // If the intermediate type was expanded, split each the value into
607 // legal parts.
608 assert(NumIntermediates != 0 && "division by zero")((NumIntermediates != 0 && "division by zero") ? static_cast
<void> (0) : __assert_fail ("NumIntermediates != 0 && \"division by zero\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 608, __PRETTY_FUNCTION__))
;
609 assert(NumParts % NumIntermediates == 0 &&((NumParts % NumIntermediates == 0 && "Must expand into a divisible number of parts!"
) ? static_cast<void> (0) : __assert_fail ("NumParts % NumIntermediates == 0 && \"Must expand into a divisible number of parts!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 610, __PRETTY_FUNCTION__))
610 "Must expand into a divisible number of parts!")((NumParts % NumIntermediates == 0 && "Must expand into a divisible number of parts!"
) ? static_cast<void> (0) : __assert_fail ("NumParts % NumIntermediates == 0 && \"Must expand into a divisible number of parts!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 610, __PRETTY_FUNCTION__))
;
611 unsigned Factor = NumParts / NumIntermediates;
612 for (unsigned i = 0; i != NumIntermediates; ++i)
613 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT, V);
614 }
615}
616
617RegsForValue::RegsForValue() {}
618
619RegsForValue::RegsForValue(const SmallVector<unsigned, 4> &regs, MVT regvt,
620 EVT valuevt)
621 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
622
623RegsForValue::RegsForValue(LLVMContext &Context, const TargetLowering &TLI,
624 const DataLayout &DL, unsigned Reg, Type *Ty) {
625 ComputeValueVTs(TLI, DL, Ty, ValueVTs);
626
627 for (EVT ValueVT : ValueVTs) {
628 unsigned NumRegs = TLI.getNumRegisters(Context, ValueVT);
629 MVT RegisterVT = TLI.getRegisterType(Context, ValueVT);
630 for (unsigned i = 0; i != NumRegs; ++i)
631 Regs.push_back(Reg + i);
632 RegVTs.push_back(RegisterVT);
633 Reg += NumRegs;
634 }
635}
636
637SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
638 FunctionLoweringInfo &FuncInfo,
639 const SDLoc &dl, SDValue &Chain,
640 SDValue *Flag, const Value *V) const {
641 // A Value with type {} or [0 x %t] needs no registers.
642 if (ValueVTs.empty())
643 return SDValue();
644
645 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
646
647 // Assemble the legal parts into the final values.
648 SmallVector<SDValue, 4> Values(ValueVTs.size());
649 SmallVector<SDValue, 8> Parts;
650 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
651 // Copy the legal parts from the registers.
652 EVT ValueVT = ValueVTs[Value];
653 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
654 MVT RegisterVT = RegVTs[Value];
655
656 Parts.resize(NumRegs);
657 for (unsigned i = 0; i != NumRegs; ++i) {
658 SDValue P;
659 if (!Flag) {
660 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
661 } else {
662 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
663 *Flag = P.getValue(2);
664 }
665
666 Chain = P.getValue(1);
667 Parts[i] = P;
668
669 // If the source register was virtual and if we know something about it,
670 // add an assert node.
671 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) ||
672 !RegisterVT.isInteger() || RegisterVT.isVector())
673 continue;
674
675 const FunctionLoweringInfo::LiveOutInfo *LOI =
676 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]);
677 if (!LOI)
678 continue;
679
680 unsigned RegSize = RegisterVT.getSizeInBits();
681 unsigned NumSignBits = LOI->NumSignBits;
682 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes();
683
684 if (NumZeroBits == RegSize) {
685 // The current value is a zero.
686 // Explicitly express that as it would be easier for
687 // optimizations to kick in.
688 Parts[i] = DAG.getConstant(0, dl, RegisterVT);
689 continue;
690 }
691
692 // FIXME: We capture more information than the dag can represent. For
693 // now, just use the tightest assertzext/assertsext possible.
694 bool isSExt = true;
695 EVT FromVT(MVT::Other);
696 if (NumSignBits == RegSize) {
697 isSExt = true; // ASSERT SEXT 1
698 FromVT = MVT::i1;
699 } else if (NumZeroBits >= RegSize - 1) {
700 isSExt = false; // ASSERT ZEXT 1
701 FromVT = MVT::i1;
702 } else if (NumSignBits > RegSize - 8) {
703 isSExt = true; // ASSERT SEXT 8
704 FromVT = MVT::i8;
705 } else if (NumZeroBits >= RegSize - 8) {
706 isSExt = false; // ASSERT ZEXT 8
707 FromVT = MVT::i8;
708 } else if (NumSignBits > RegSize - 16) {
709 isSExt = true; // ASSERT SEXT 16
710 FromVT = MVT::i16;
711 } else if (NumZeroBits >= RegSize - 16) {
712 isSExt = false; // ASSERT ZEXT 16
713 FromVT = MVT::i16;
714 } else if (NumSignBits > RegSize - 32) {
715 isSExt = true; // ASSERT SEXT 32
716 FromVT = MVT::i32;
717 } else if (NumZeroBits >= RegSize - 32) {
718 isSExt = false; // ASSERT ZEXT 32
719 FromVT = MVT::i32;
720 } else {
721 continue;
722 }
723 // Add an assertion node.
724 assert(FromVT != MVT::Other)((FromVT != MVT::Other) ? static_cast<void> (0) : __assert_fail
("FromVT != MVT::Other", "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 724, __PRETTY_FUNCTION__))
;
725 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
726 RegisterVT, P, DAG.getValueType(FromVT));
727 }
728
729 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
730 NumRegs, RegisterVT, ValueVT, V);
731 Part += NumRegs;
732 Parts.clear();
733 }
734
735 return DAG.getNode(ISD::MERGE_VALUES, dl, DAG.getVTList(ValueVTs), Values);
736}
737
738void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG,
739 const SDLoc &dl, SDValue &Chain, SDValue *Flag,
740 const Value *V,
741 ISD::NodeType PreferredExtendType) const {
742 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
743 ISD::NodeType ExtendKind = PreferredExtendType;
744
745 // Get the list of the values's legal parts.
746 unsigned NumRegs = Regs.size();
747 SmallVector<SDValue, 8> Parts(NumRegs);
748 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
749 EVT ValueVT = ValueVTs[Value];
750 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
751 MVT RegisterVT = RegVTs[Value];
752
753 if (ExtendKind == ISD::ANY_EXTEND && TLI.isZExtFree(Val, RegisterVT))
754 ExtendKind = ISD::ZERO_EXTEND;
755
756 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
757 &Parts[Part], NumParts, RegisterVT, V, ExtendKind);
758 Part += NumParts;
759 }
760
761 // Copy the parts into the registers.
762 SmallVector<SDValue, 8> Chains(NumRegs);
763 for (unsigned i = 0; i != NumRegs; ++i) {
764 SDValue Part;
765 if (!Flag) {
766 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
767 } else {
768 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
769 *Flag = Part.getValue(1);
770 }
771
772 Chains[i] = Part.getValue(0);
773 }
774
775 if (NumRegs == 1 || Flag)
776 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
777 // flagged to it. That is the CopyToReg nodes and the user are considered
778 // a single scheduling unit. If we create a TokenFactor and return it as
779 // chain, then the TokenFactor is both a predecessor (operand) of the
780 // user as well as a successor (the TF operands are flagged to the user).
781 // c1, f1 = CopyToReg
782 // c2, f2 = CopyToReg
783 // c3 = TokenFactor c1, c2
784 // ...
785 // = op c3, ..., f2
786 Chain = Chains[NumRegs-1];
787 else
788 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
789}
790
791void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
792 unsigned MatchingIdx, const SDLoc &dl,
793 SelectionDAG &DAG,
794 std::vector<SDValue> &Ops) const {
795 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
796
797 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size());
798 if (HasMatching)
799 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx);
800 else if (!Regs.empty() &&
801 TargetRegisterInfo::isVirtualRegister(Regs.front())) {
802 // Put the register class of the virtual registers in the flag word. That
803 // way, later passes can recompute register class constraints for inline
804 // assembly as well as normal instructions.
805 // Don't do this for tied operands that can use the regclass information
806 // from the def.
807 const MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
808 const TargetRegisterClass *RC = MRI.getRegClass(Regs.front());
809 Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID());
810 }
811
812 SDValue Res = DAG.getTargetConstant(Flag, dl, MVT::i32);
813 Ops.push_back(Res);
814
815 unsigned SP = TLI.getStackPointerRegisterToSaveRestore();
816 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
817 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
818 MVT RegisterVT = RegVTs[Value];
819 for (unsigned i = 0; i != NumRegs; ++i) {
820 assert(Reg < Regs.size() && "Mismatch in # registers expected")((Reg < Regs.size() && "Mismatch in # registers expected"
) ? static_cast<void> (0) : __assert_fail ("Reg < Regs.size() && \"Mismatch in # registers expected\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 820, __PRETTY_FUNCTION__))
;
821 unsigned TheReg = Regs[Reg++];
822 Ops.push_back(DAG.getRegister(TheReg, RegisterVT));
823
824 if (TheReg == SP && Code == InlineAsm::Kind_Clobber) {
825 // If we clobbered the stack pointer, MFI should know about it.
826 assert(DAG.getMachineFunction().getFrameInfo().hasOpaqueSPAdjustment())((DAG.getMachineFunction().getFrameInfo().hasOpaqueSPAdjustment
()) ? static_cast<void> (0) : __assert_fail ("DAG.getMachineFunction().getFrameInfo().hasOpaqueSPAdjustment()"
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 826, __PRETTY_FUNCTION__))
;
827 }
828 }
829 }
830}
831
832void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa,
833 const TargetLibraryInfo *li) {
834 AA = &aa;
835 GFI = gfi;
836 LibInfo = li;
837 DL = &DAG.getDataLayout();
838 Context = DAG.getContext();
839 LPadToCallSiteMap.clear();
840}
841
842void SelectionDAGBuilder::clear() {
843 NodeMap.clear();
844 UnusedArgNodeMap.clear();
845 PendingLoads.clear();
846 PendingExports.clear();
847 CurInst = nullptr;
848 HasTailCall = false;
849 SDNodeOrder = LowestSDNodeOrder;
850 StatepointLowering.clear();
851}
852
853void SelectionDAGBuilder::clearDanglingDebugInfo() {
854 DanglingDebugInfoMap.clear();
855}
856
857SDValue SelectionDAGBuilder::getRoot() {
858 if (PendingLoads.empty())
859 return DAG.getRoot();
860
861 if (PendingLoads.size() == 1) {
862 SDValue Root = PendingLoads[0];
863 DAG.setRoot(Root);
864 PendingLoads.clear();
865 return Root;
866 }
867
868 // Otherwise, we have to make a token factor node.
869 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
870 PendingLoads);
871 PendingLoads.clear();
872 DAG.setRoot(Root);
873 return Root;
874}
875
876SDValue SelectionDAGBuilder::getControlRoot() {
877 SDValue Root = DAG.getRoot();
878
879 if (PendingExports.empty())
880 return Root;
881
882 // Turn all of the CopyToReg chains into one factored node.
883 if (Root.getOpcode() != ISD::EntryToken) {
884 unsigned i = 0, e = PendingExports.size();
885 for (; i != e; ++i) {
886 assert(PendingExports[i].getNode()->getNumOperands() > 1)((PendingExports[i].getNode()->getNumOperands() > 1) ? static_cast
<void> (0) : __assert_fail ("PendingExports[i].getNode()->getNumOperands() > 1"
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 886, __PRETTY_FUNCTION__))
;
887 if (PendingExports[i].getNode()->getOperand(0) == Root)
888 break; // Don't add the root if we already indirectly depend on it.
889 }
890
891 if (i == e)
892 PendingExports.push_back(Root);
893 }
894
895 Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
896 PendingExports);
897 PendingExports.clear();
898 DAG.setRoot(Root);
899 return Root;
900}
901
902void SelectionDAGBuilder::visit(const Instruction &I) {
903 // Set up outgoing PHI node register values before emitting the terminator.
904 if (isa<TerminatorInst>(&I)) {
905 HandlePHINodesInSuccessorBlocks(I.getParent());
906 }
907
908 // Increase the SDNodeOrder if dealing with a non-debug instruction.
909 if (!isa<DbgInfoIntrinsic>(I))
910 ++SDNodeOrder;
911
912 CurInst = &I;
913
914 visit(I.getOpcode(), I);
915
916 if (!isa<TerminatorInst>(&I) && !HasTailCall &&
917 !isStatepoint(&I)) // statepoints handle their exports internally
918 CopyToExportRegsIfNeeded(&I);
919
920 CurInst = nullptr;
921}
922
923void SelectionDAGBuilder::visitPHI(const PHINode &) {
924 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!")::llvm::llvm_unreachable_internal("SelectionDAGBuilder shouldn't visit PHI nodes!"
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 924)
;
925}
926
927void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
928 // Note: this doesn't use InstVisitor, because it has to work with
929 // ConstantExpr's in addition to instructions.
930 switch (Opcode) {
931 default: llvm_unreachable("Unknown instruction type encountered!")::llvm::llvm_unreachable_internal("Unknown instruction type encountered!"
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 931)
;
932 // Build the switch statement using the Instruction.def file.
933#define HANDLE_INST(NUM, OPCODE, CLASS) \
934 case Instruction::OPCODE: visit##OPCODE((const CLASS&)I); break;
935#include "llvm/IR/Instruction.def"
936 }
937}
938
939// resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
940// generate the debug data structures now that we've seen its definition.
941void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V,
942 SDValue Val) {
943 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V];
944 if (DDI.getDI()) {
945 const DbgValueInst *DI = DDI.getDI();
946 DebugLoc dl = DDI.getdl();
947 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder();
948 DILocalVariable *Variable = DI->getVariable();
949 DIExpression *Expr = DI->getExpression();
950 assert(Variable->isValidLocationForIntrinsic(dl) &&((Variable->isValidLocationForIntrinsic(dl) && "Expected inlined-at fields to agree"
) ? static_cast<void> (0) : __assert_fail ("Variable->isValidLocationForIntrinsic(dl) && \"Expected inlined-at fields to agree\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 951, __PRETTY_FUNCTION__))
951 "Expected inlined-at fields to agree")((Variable->isValidLocationForIntrinsic(dl) && "Expected inlined-at fields to agree"
) ? static_cast<void> (0) : __assert_fail ("Variable->isValidLocationForIntrinsic(dl) && \"Expected inlined-at fields to agree\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 951, __PRETTY_FUNCTION__))
;
952 uint64_t Offset = DI->getOffset();
953 SDDbgValue *SDV;
954 if (Val.getNode()) {
955 if (!EmitFuncArgumentDbgValue(V, Variable, Expr, dl, Offset, false,
956 Val)) {
957 SDV = getDbgValue(Val, Variable, Expr, Offset, dl, DbgSDNodeOrder);
958 DAG.AddDbgValue(SDV, Val.getNode(), false);
959 }
960 } else
961 DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << "Dropping debug info for " <<
*DI << "\n"; } } while (false)
;
962 DanglingDebugInfoMap[V] = DanglingDebugInfo();
963 }
964}
965
966/// getCopyFromRegs - If there was virtual register allocated for the value V
967/// emit CopyFromReg of the specified type Ty. Return empty SDValue() otherwise.
968SDValue SelectionDAGBuilder::getCopyFromRegs(const Value *V, Type *Ty) {
969 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V);
970 SDValue Result;
971
972 if (It != FuncInfo.ValueMap.end()) {
973 unsigned InReg = It->second;
974 RegsForValue RFV(*DAG.getContext(), DAG.getTargetLoweringInfo(),
975 DAG.getDataLayout(), InReg, Ty);
976 SDValue Chain = DAG.getEntryNode();
977 Result = RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
978 resolveDanglingDebugInfo(V, Result);
979 }
980
981 return Result;
982}
983
984/// getValue - Return an SDValue for the given Value.
985SDValue SelectionDAGBuilder::getValue(const Value *V) {
986 // If we already have an SDValue for this value, use it. It's important
987 // to do this first, so that we don't create a CopyFromReg if we already
988 // have a regular SDValue.
989 SDValue &N = NodeMap[V];
990 if (N.getNode()) return N;
991
992 // If there's a virtual register allocated and initialized for this
993 // value, use it.
994 if (SDValue copyFromReg = getCopyFromRegs(V, V->getType()))
995 return copyFromReg;
996
997 // Otherwise create a new SDValue and remember it.
998 SDValue Val = getValueImpl(V);
999 NodeMap[V] = Val;
1000 resolveDanglingDebugInfo(V, Val);
1001 return Val;
1002}
1003
1004// Return true if SDValue exists for the given Value
1005bool SelectionDAGBuilder::findValue(const Value *V) const {
1006 return (NodeMap.find(V) != NodeMap.end()) ||
1007 (FuncInfo.ValueMap.find(V) != FuncInfo.ValueMap.end());
1008}
1009
1010/// getNonRegisterValue - Return an SDValue for the given Value, but
1011/// don't look in FuncInfo.ValueMap for a virtual register.
1012SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) {
1013 // If we already have an SDValue for this value, use it.
1014 SDValue &N = NodeMap[V];
1015 if (N.getNode()) {
1016 if (isa<ConstantSDNode>(N) || isa<ConstantFPSDNode>(N)) {
1017 // Remove the debug location from the node as the node is about to be used
1018 // in a location which may differ from the original debug location. This
1019 // is relevant to Constant and ConstantFP nodes because they can appear
1020 // as constant expressions inside PHI nodes.
1021 N->setDebugLoc(DebugLoc());
1022 }
1023 return N;
1024 }
1025
1026 // Otherwise create a new SDValue and remember it.
1027 SDValue Val = getValueImpl(V);
1028 NodeMap[V] = Val;
1029 resolveDanglingDebugInfo(V, Val);
1030 return Val;
1031}
1032
1033/// getValueImpl - Helper function for getValue and getNonRegisterValue.
1034/// Create an SDValue for the given value.
1035SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
1036 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1037
1038 if (const Constant *C = dyn_cast<Constant>(V)) {
1039 EVT VT = TLI.getValueType(DAG.getDataLayout(), V->getType(), true);
1040
1041 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
1042 return DAG.getConstant(*CI, getCurSDLoc(), VT);
1043
1044 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
1045 return DAG.getGlobalAddress(GV, getCurSDLoc(), VT);
1046
1047 if (isa<ConstantPointerNull>(C)) {
1048 unsigned AS = V->getType()->getPointerAddressSpace();
1049 return DAG.getConstant(0, getCurSDLoc(),
1050 TLI.getPointerTy(DAG.getDataLayout(), AS));
1051 }
1052
1053 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
1054 return DAG.getConstantFP(*CFP, getCurSDLoc(), VT);
1055
1056 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
1057 return DAG.getUNDEF(VT);
1058
1059 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
1060 visit(CE->getOpcode(), *CE);
1061 SDValue N1 = NodeMap[V];
1062 assert(N1.getNode() && "visit didn't populate the NodeMap!")((N1.getNode() && "visit didn't populate the NodeMap!"
) ? static_cast<void> (0) : __assert_fail ("N1.getNode() && \"visit didn't populate the NodeMap!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 1062, __PRETTY_FUNCTION__))
;
1063 return N1;
1064 }
1065
1066 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
1067 SmallVector<SDValue, 4> Constants;
1068 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
1069 OI != OE; ++OI) {
1070 SDNode *Val = getValue(*OI).getNode();
1071 // If the operand is an empty aggregate, there are no values.
1072 if (!Val) continue;
1073 // Add each leaf value from the operand to the Constants list
1074 // to form a flattened list of all the values.
1075 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1076 Constants.push_back(SDValue(Val, i));
1077 }
1078
1079 return DAG.getMergeValues(Constants, getCurSDLoc());
1080 }
1081
1082 if (const ConstantDataSequential *CDS =
1083 dyn_cast<ConstantDataSequential>(C)) {
1084 SmallVector<SDValue, 4> Ops;
1085 for (unsigned i = 0, e = CDS->getNumElements(); i != e; ++i) {
1086 SDNode *Val = getValue(CDS->getElementAsConstant(i)).getNode();
1087 // Add each leaf value from the operand to the Constants list
1088 // to form a flattened list of all the values.
1089 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1090 Ops.push_back(SDValue(Val, i));
1091 }
1092
1093 if (isa<ArrayType>(CDS->getType()))
1094 return DAG.getMergeValues(Ops, getCurSDLoc());
1095 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(),
1096 VT, Ops);
1097 }
1098
1099 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
1100 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&(((isa<ConstantAggregateZero>(C) || isa<UndefValue>
(C)) && "Unknown struct or array constant!") ? static_cast
<void> (0) : __assert_fail ("(isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) && \"Unknown struct or array constant!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 1101, __PRETTY_FUNCTION__))
1101 "Unknown struct or array constant!")(((isa<ConstantAggregateZero>(C) || isa<UndefValue>
(C)) && "Unknown struct or array constant!") ? static_cast
<void> (0) : __assert_fail ("(isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) && \"Unknown struct or array constant!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 1101, __PRETTY_FUNCTION__))
;
1102
1103 SmallVector<EVT, 4> ValueVTs;
1104 ComputeValueVTs(TLI, DAG.getDataLayout(), C->getType(), ValueVTs);
1105 unsigned NumElts = ValueVTs.size();
1106 if (NumElts == 0)
1107 return SDValue(); // empty struct
1108 SmallVector<SDValue, 4> Constants(NumElts);
1109 for (unsigned i = 0; i != NumElts; ++i) {
1110 EVT EltVT = ValueVTs[i];
1111 if (isa<UndefValue>(C))
1112 Constants[i] = DAG.getUNDEF(EltVT);
1113 else if (EltVT.isFloatingPoint())
1114 Constants[i] = DAG.getConstantFP(0, getCurSDLoc(), EltVT);
1115 else
1116 Constants[i] = DAG.getConstant(0, getCurSDLoc(), EltVT);
1117 }
1118
1119 return DAG.getMergeValues(Constants, getCurSDLoc());
1120 }
1121
1122 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C))
1123 return DAG.getBlockAddress(BA, VT);
1124
1125 VectorType *VecTy = cast<VectorType>(V->getType());
1126 unsigned NumElements = VecTy->getNumElements();
1127
1128 // Now that we know the number and type of the elements, get that number of
1129 // elements into the Ops array based on what kind of constant it is.
1130 SmallVector<SDValue, 16> Ops;
1131 if (const ConstantVector *CV = dyn_cast<ConstantVector>(C)) {
1132 for (unsigned i = 0; i != NumElements; ++i)
1133 Ops.push_back(getValue(CV->getOperand(i)));
1134 } else {
1135 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!")((isa<ConstantAggregateZero>(C) && "Unknown vector constant!"
) ? static_cast<void> (0) : __assert_fail ("isa<ConstantAggregateZero>(C) && \"Unknown vector constant!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 1135, __PRETTY_FUNCTION__))
;
1136 EVT EltVT =
1137 TLI.getValueType(DAG.getDataLayout(), VecTy->getElementType());
1138
1139 SDValue Op;
1140 if (EltVT.isFloatingPoint())
1141 Op = DAG.getConstantFP(0, getCurSDLoc(), EltVT);
1142 else
1143 Op = DAG.getConstant(0, getCurSDLoc(), EltVT);
1144 Ops.assign(NumElements, Op);
1145 }
1146
1147 // Create a BUILD_VECTOR node.
1148 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(), VT, Ops);
1149 }
1150
1151 // If this is a static alloca, generate it as the frameindex instead of
1152 // computation.
1153 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1154 DenseMap<const AllocaInst*, int>::iterator SI =
1155 FuncInfo.StaticAllocaMap.find(AI);
1156 if (SI != FuncInfo.StaticAllocaMap.end())
1157 return DAG.getFrameIndex(SI->second,
1158 TLI.getPointerTy(DAG.getDataLayout()));
1159 }
1160
1161 // If this is an instruction which fast-isel has deferred, select it now.
1162 if (const Instruction *Inst = dyn_cast<Instruction>(V)) {
1163 unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
1164 RegsForValue RFV(*DAG.getContext(), TLI, DAG.getDataLayout(), InReg,
1165 Inst->getType());
1166 SDValue Chain = DAG.getEntryNode();
1167 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
1168 }
1169
1170 llvm_unreachable("Can't get register for value!")::llvm::llvm_unreachable_internal("Can't get register for value!"
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 1170)
;
1171}
1172
1173void SelectionDAGBuilder::visitCatchPad(const CatchPadInst &I) {
1174 auto Pers = classifyEHPersonality(FuncInfo.Fn->getPersonalityFn());
1175 bool IsMSVCCXX = Pers == EHPersonality::MSVC_CXX;
1176 bool IsCoreCLR = Pers == EHPersonality::CoreCLR;
1177 MachineBasicBlock *CatchPadMBB = FuncInfo.MBB;
1178 // In MSVC C++ and CoreCLR, catchblocks are funclets and need prologues.
1179 if (IsMSVCCXX || IsCoreCLR)
1180 CatchPadMBB->setIsEHFuncletEntry();
1181
1182 DAG.setRoot(DAG.getNode(ISD::CATCHPAD, getCurSDLoc(), MVT::Other, getControlRoot()));
1183}
1184
1185void SelectionDAGBuilder::visitCatchRet(const CatchReturnInst &I) {
1186 // Update machine-CFG edge.
1187 MachineBasicBlock *TargetMBB = FuncInfo.MBBMap[I.getSuccessor()];
1188 FuncInfo.MBB->addSuccessor(TargetMBB);
1189
1190 auto Pers = classifyEHPersonality(FuncInfo.Fn->getPersonalityFn());
1191 bool IsSEH = isAsynchronousEHPersonality(Pers);
1192 if (IsSEH) {
1193 // If this is not a fall-through branch or optimizations are switched off,
1194 // emit the branch.
1195 if (TargetMBB != NextBlock(FuncInfo.MBB) ||
1196 TM.getOptLevel() == CodeGenOpt::None)
1197 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other,
1198 getControlRoot(), DAG.getBasicBlock(TargetMBB)));
1199 return;
1200 }
1201
1202 // Figure out the funclet membership for the catchret's successor.
1203 // This will be used by the FuncletLayout pass to determine how to order the
1204 // BB's.
1205 // A 'catchret' returns to the outer scope's color.
1206 Value *ParentPad = I.getCatchSwitchParentPad();
1207 const BasicBlock *SuccessorColor;
1208 if (isa<ConstantTokenNone>(ParentPad))
1209 SuccessorColor = &FuncInfo.Fn->getEntryBlock();
1210 else
1211 SuccessorColor = cast<Instruction>(ParentPad)->getParent();
1212 assert(SuccessorColor && "No parent funclet for catchret!")((SuccessorColor && "No parent funclet for catchret!"
) ? static_cast<void> (0) : __assert_fail ("SuccessorColor && \"No parent funclet for catchret!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 1212, __PRETTY_FUNCTION__))
;
1213 MachineBasicBlock *SuccessorColorMBB = FuncInfo.MBBMap[SuccessorColor];
1214 assert(SuccessorColorMBB && "No MBB for SuccessorColor!")((SuccessorColorMBB && "No MBB for SuccessorColor!") ?
static_cast<void> (0) : __assert_fail ("SuccessorColorMBB && \"No MBB for SuccessorColor!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 1214, __PRETTY_FUNCTION__))
;
1215
1216 // Create the terminator node.
1217 SDValue Ret = DAG.getNode(ISD::CATCHRET, getCurSDLoc(), MVT::Other,
1218 getControlRoot(), DAG.getBasicBlock(TargetMBB),
1219 DAG.getBasicBlock(SuccessorColorMBB));
1220 DAG.setRoot(Ret);
1221}
1222
1223void SelectionDAGBuilder::visitCleanupPad(const CleanupPadInst &CPI) {
1224 // Don't emit any special code for the cleanuppad instruction. It just marks
1225 // the start of a funclet.
1226 FuncInfo.MBB->setIsEHFuncletEntry();
1227 FuncInfo.MBB->setIsCleanupFuncletEntry();
1228}
1229
1230/// When an invoke or a cleanupret unwinds to the next EH pad, there are
1231/// many places it could ultimately go. In the IR, we have a single unwind
1232/// destination, but in the machine CFG, we enumerate all the possible blocks.
1233/// This function skips over imaginary basic blocks that hold catchswitch
1234/// instructions, and finds all the "real" machine
1235/// basic block destinations. As those destinations may not be successors of
1236/// EHPadBB, here we also calculate the edge probability to those destinations.
1237/// The passed-in Prob is the edge probability to EHPadBB.
1238static void findUnwindDestinations(
1239 FunctionLoweringInfo &FuncInfo, const BasicBlock *EHPadBB,
1240 BranchProbability Prob,
1241 SmallVectorImpl<std::pair<MachineBasicBlock *, BranchProbability>>
1242 &UnwindDests) {
1243 EHPersonality Personality =
1244 classifyEHPersonality(FuncInfo.Fn->getPersonalityFn());
1245 bool IsMSVCCXX = Personality == EHPersonality::MSVC_CXX;
1246 bool IsCoreCLR = Personality == EHPersonality::CoreCLR;
1247
1248 while (EHPadBB) {
1249 const Instruction *Pad = EHPadBB->getFirstNonPHI();
1250 BasicBlock *NewEHPadBB = nullptr;
1251 if (isa<LandingPadInst>(Pad)) {
1252 // Stop on landingpads. They are not funclets.
1253 UnwindDests.emplace_back(FuncInfo.MBBMap[EHPadBB], Prob);
1254 break;
1255 } else if (isa<CleanupPadInst>(Pad)) {
1256 // Stop on cleanup pads. Cleanups are always funclet entries for all known
1257 // personalities.
1258 UnwindDests.emplace_back(FuncInfo.MBBMap[EHPadBB], Prob);
1259 UnwindDests.back().first->setIsEHFuncletEntry();
1260 break;
1261 } else if (auto *CatchSwitch = dyn_cast<CatchSwitchInst>(Pad)) {
1262 // Add the catchpad handlers to the possible destinations.
1263 for (const BasicBlock *CatchPadBB : CatchSwitch->handlers()) {
1264 UnwindDests.emplace_back(FuncInfo.MBBMap[CatchPadBB], Prob);
1265 // For MSVC++ and the CLR, catchblocks are funclets and need prologues.
1266 if (IsMSVCCXX || IsCoreCLR)
1267 UnwindDests.back().first->setIsEHFuncletEntry();
1268 }
1269 NewEHPadBB = CatchSwitch->getUnwindDest();
1270 } else {
1271 continue;
1272 }
1273
1274 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1275 if (BPI && NewEHPadBB)
1276 Prob *= BPI->getEdgeProbability(EHPadBB, NewEHPadBB);
1277 EHPadBB = NewEHPadBB;
1278 }
1279}
1280
1281void SelectionDAGBuilder::visitCleanupRet(const CleanupReturnInst &I) {
1282 // Update successor info.
1283 SmallVector<std::pair<MachineBasicBlock *, BranchProbability>, 1> UnwindDests;
1284 auto UnwindDest = I.getUnwindDest();
1285 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1286 BranchProbability UnwindDestProb =
1287 (BPI && UnwindDest)
1288 ? BPI->getEdgeProbability(FuncInfo.MBB->getBasicBlock(), UnwindDest)
1289 : BranchProbability::getZero();
1290 findUnwindDestinations(FuncInfo, UnwindDest, UnwindDestProb, UnwindDests);
1291 for (auto &UnwindDest : UnwindDests) {
1292 UnwindDest.first->setIsEHPad();
1293 addSuccessorWithProb(FuncInfo.MBB, UnwindDest.first, UnwindDest.second);
1294 }
1295 FuncInfo.MBB->normalizeSuccProbs();
1296
1297 // Create the terminator node.
1298 SDValue Ret =
1299 DAG.getNode(ISD::CLEANUPRET, getCurSDLoc(), MVT::Other, getControlRoot());
1300 DAG.setRoot(Ret);
1301}
1302
1303void SelectionDAGBuilder::visitCatchSwitch(const CatchSwitchInst &CSI) {
1304 report_fatal_error("visitCatchSwitch not yet implemented!");
1305}
1306
1307void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
1308 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1309 auto &DL = DAG.getDataLayout();
1310 SDValue Chain = getControlRoot();
1311 SmallVector<ISD::OutputArg, 8> Outs;
1312 SmallVector<SDValue, 8> OutVals;
1313
1314 // Calls to @llvm.experimental.deoptimize don't generate a return value, so
1315 // lower
1316 //
1317 // %val = call <ty> @llvm.experimental.deoptimize()
1318 // ret <ty> %val
1319 //
1320 // differently.
1321 if (I.getParent()->getTerminatingDeoptimizeCall()) {
1322 LowerDeoptimizingReturn();
1323 return;
1324 }
1325
1326 if (!FuncInfo.CanLowerReturn) {
1327 unsigned DemoteReg = FuncInfo.DemoteRegister;
1328 const Function *F = I.getParent()->getParent();
1329
1330 // Emit a store of the return value through the virtual register.
1331 // Leave Outs empty so that LowerReturn won't try to load return
1332 // registers the usual way.
1333 SmallVector<EVT, 1> PtrValueVTs;
1334 ComputeValueVTs(TLI, DL, PointerType::getUnqual(F->getReturnType()),
1335 PtrValueVTs);
1336
1337 SDValue RetPtr = DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(),
1338 DemoteReg, PtrValueVTs[0]);
1339 SDValue RetOp = getValue(I.getOperand(0));
1340
1341 SmallVector<EVT, 4> ValueVTs;
1342 SmallVector<uint64_t, 4> Offsets;
1343 ComputeValueVTs(TLI, DL, I.getOperand(0)->getType(), ValueVTs, &Offsets);
1344 unsigned NumValues = ValueVTs.size();
1345
1346 // An aggregate return value cannot wrap around the address space, so
1347 // offsets to its parts don't wrap either.
1348 SDNodeFlags Flags;
1349 Flags.setNoUnsignedWrap(true);
1350
1351 SmallVector<SDValue, 4> Chains(NumValues);
1352 for (unsigned i = 0; i != NumValues; ++i) {
1353 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(),
1354 RetPtr.getValueType(), RetPtr,
1355 DAG.getIntPtrConstant(Offsets[i],
1356 getCurSDLoc()),
1357 &Flags);
1358 Chains[i] = DAG.getStore(Chain, getCurSDLoc(),
1359 SDValue(RetOp.getNode(), RetOp.getResNo() + i),
1360 // FIXME: better loc info would be nice.
1361 Add, MachinePointerInfo());
1362 }
1363
1364 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
1365 MVT::Other, Chains);
1366 } else if (I.getNumOperands() != 0) {
1367 SmallVector<EVT, 4> ValueVTs;
1368 ComputeValueVTs(TLI, DL, I.getOperand(0)->getType(), ValueVTs);
1369 unsigned NumValues = ValueVTs.size();
1370 if (NumValues) {
1371 SDValue RetOp = getValue(I.getOperand(0));
1372
1373 const Function *F = I.getParent()->getParent();
1374
1375 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1376 if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1377 Attribute::SExt))
1378 ExtendKind = ISD::SIGN_EXTEND;
1379 else if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1380 Attribute::ZExt))
1381 ExtendKind = ISD::ZERO_EXTEND;
1382
1383 LLVMContext &Context = F->getContext();
1384 bool RetInReg = F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1385 Attribute::InReg);
1386
1387 for (unsigned j = 0; j != NumValues; ++j) {
1388 EVT VT = ValueVTs[j];
1389
1390 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger())
1391 VT = TLI.getTypeForExtReturn(Context, VT, ExtendKind);
1392
1393 unsigned NumParts = TLI.getNumRegisters(Context, VT);
1394 MVT PartVT = TLI.getRegisterType(Context, VT);
1395 SmallVector<SDValue, 4> Parts(NumParts);
1396 getCopyToParts(DAG, getCurSDLoc(),
1397 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
1398 &Parts[0], NumParts, PartVT, &I, ExtendKind);
1399
1400 // 'inreg' on function refers to return value
1401 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1402 if (RetInReg)
1403 Flags.setInReg();
1404
1405 // Propagate extension type if any
1406 if (ExtendKind == ISD::SIGN_EXTEND)
1407 Flags.setSExt();
1408 else if (ExtendKind == ISD::ZERO_EXTEND)
1409 Flags.setZExt();
1410
1411 for (unsigned i = 0; i < NumParts; ++i) {
1412 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(),
1413 VT, /*isfixed=*/true, 0, 0));
1414 OutVals.push_back(Parts[i]);
1415 }
1416 }
1417 }
1418 }
1419
1420 // Push in swifterror virtual register as the last element of Outs. This makes
1421 // sure swifterror virtual register will be returned in the swifterror
1422 // physical register.
1423 const Function *F = I.getParent()->getParent();
1424 if (TLI.supportSwiftError() &&
1425 F->getAttributes().hasAttrSomewhere(Attribute::SwiftError)) {
1426 assert(FuncInfo.SwiftErrorArg && "Need a swift error argument")((FuncInfo.SwiftErrorArg && "Need a swift error argument"
) ? static_cast<void> (0) : __assert_fail ("FuncInfo.SwiftErrorArg && \"Need a swift error argument\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 1426, __PRETTY_FUNCTION__))
;
1427 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1428 Flags.setSwiftError();
1429 Outs.push_back(ISD::OutputArg(Flags, EVT(TLI.getPointerTy(DL)) /*vt*/,
1430 EVT(TLI.getPointerTy(DL)) /*argvt*/,
1431 true /*isfixed*/, 1 /*origidx*/,
1432 0 /*partOffs*/));
1433 // Create SDNode for the swifterror virtual register.
1434 OutVals.push_back(DAG.getRegister(FuncInfo.getOrCreateSwiftErrorVReg(
1435 FuncInfo.MBB, FuncInfo.SwiftErrorArg),
1436 EVT(TLI.getPointerTy(DL))));
1437 }
1438
1439 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1440 CallingConv::ID CallConv =
1441 DAG.getMachineFunction().getFunction()->getCallingConv();
1442 Chain = DAG.getTargetLoweringInfo().LowerReturn(
1443 Chain, CallConv, isVarArg, Outs, OutVals, getCurSDLoc(), DAG);
1444
1445 // Verify that the target's LowerReturn behaved as expected.
1446 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&((Chain.getNode() && Chain.getValueType() == MVT::Other
&& "LowerReturn didn't return a valid chain!") ? static_cast
<void> (0) : __assert_fail ("Chain.getNode() && Chain.getValueType() == MVT::Other && \"LowerReturn didn't return a valid chain!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 1447, __PRETTY_FUNCTION__))
1447 "LowerReturn didn't return a valid chain!")((Chain.getNode() && Chain.getValueType() == MVT::Other
&& "LowerReturn didn't return a valid chain!") ? static_cast
<void> (0) : __assert_fail ("Chain.getNode() && Chain.getValueType() == MVT::Other && \"LowerReturn didn't return a valid chain!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 1447, __PRETTY_FUNCTION__))
;
1448
1449 // Update the DAG with the new chain value resulting from return lowering.
1450 DAG.setRoot(Chain);
1451}
1452
1453/// CopyToExportRegsIfNeeded - If the given value has virtual registers
1454/// created for it, emit nodes to copy the value into the virtual
1455/// registers.
1456void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) {
1457 // Skip empty types
1458 if (V->getType()->isEmptyTy())
1459 return;
1460
1461 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1462 if (VMI != FuncInfo.ValueMap.end()) {
1463 assert(!V->use_empty() && "Unused value assigned virtual registers!")((!V->use_empty() && "Unused value assigned virtual registers!"
) ? static_cast<void> (0) : __assert_fail ("!V->use_empty() && \"Unused value assigned virtual registers!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 1463, __PRETTY_FUNCTION__))
;
1464 CopyValueToVirtualRegister(V, VMI->second);
1465 }
1466}
1467
1468/// ExportFromCurrentBlock - If this condition isn't known to be exported from
1469/// the current basic block, add it to ValueMap now so that we'll get a
1470/// CopyTo/FromReg.
1471void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) {
1472 // No need to export constants.
1473 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1474
1475 // Already exported?
1476 if (FuncInfo.isExportedInst(V)) return;
1477
1478 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1479 CopyValueToVirtualRegister(V, Reg);
1480}
1481
1482bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V,
1483 const BasicBlock *FromBB) {
1484 // The operands of the setcc have to be in this block. We don't know
1485 // how to export them from some other block.
1486 if (const Instruction *VI = dyn_cast<Instruction>(V)) {
1487 // Can export from current BB.
1488 if (VI->getParent() == FromBB)
1489 return true;
1490
1491 // Is already exported, noop.
1492 return FuncInfo.isExportedInst(V);
1493 }
1494
1495 // If this is an argument, we can export it if the BB is the entry block or
1496 // if it is already exported.
1497 if (isa<Argument>(V)) {
1498 if (FromBB == &FromBB->getParent()->getEntryBlock())
1499 return true;
1500
1501 // Otherwise, can only export this if it is already exported.
1502 return FuncInfo.isExportedInst(V);
1503 }
1504
1505 // Otherwise, constants can always be exported.
1506 return true;
1507}
1508
1509/// Return branch probability calculated by BranchProbabilityInfo for IR blocks.
1510BranchProbability
1511SelectionDAGBuilder::getEdgeProbability(const MachineBasicBlock *Src,
1512 const MachineBasicBlock *Dst) const {
1513 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1514 const BasicBlock *SrcBB = Src->getBasicBlock();
1515 const BasicBlock *DstBB = Dst->getBasicBlock();
1516 if (!BPI) {
1517 // If BPI is not available, set the default probability as 1 / N, where N is
1518 // the number of successors.
1519 auto SuccSize = std::max<uint32_t>(
1520 std::distance(succ_begin(SrcBB), succ_end(SrcBB)), 1);
1521 return BranchProbability(1, SuccSize);
1522 }
1523 return BPI->getEdgeProbability(SrcBB, DstBB);
1524}
1525
1526void SelectionDAGBuilder::addSuccessorWithProb(MachineBasicBlock *Src,
1527 MachineBasicBlock *Dst,
1528 BranchProbability Prob) {
1529 if (!FuncInfo.BPI)
1530 Src->addSuccessorWithoutProb(Dst);
1531 else {
1532 if (Prob.isUnknown())
1533 Prob = getEdgeProbability(Src, Dst);
1534 Src->addSuccessor(Dst, Prob);
1535 }
1536}
1537
1538static bool InBlock(const Value *V, const BasicBlock *BB) {
1539 if (const Instruction *I = dyn_cast<Instruction>(V))
1540 return I->getParent() == BB;
1541 return true;
1542}
1543
1544/// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1545/// This function emits a branch and is used at the leaves of an OR or an
1546/// AND operator tree.
1547///
1548void
1549SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond,
1550 MachineBasicBlock *TBB,
1551 MachineBasicBlock *FBB,
1552 MachineBasicBlock *CurBB,
1553 MachineBasicBlock *SwitchBB,
1554 BranchProbability TProb,
1555 BranchProbability FProb,
1556 bool InvertCond) {
1557 const BasicBlock *BB = CurBB->getBasicBlock();
1558
1559 // If the leaf of the tree is a comparison, merge the condition into
1560 // the caseblock.
1561 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1562 // The operands of the cmp have to be in this block. We don't know
1563 // how to export them from some other block. If this is the first block
1564 // of the sequence, no exporting is needed.
1565 if (CurBB == SwitchBB ||
1566 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1567 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1568 ISD::CondCode Condition;
1569 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1570 ICmpInst::Predicate Pred =
1571 InvertCond ? IC->getInversePredicate() : IC->getPredicate();
1572 Condition = getICmpCondCode(Pred);
1573 } else {
1574 const FCmpInst *FC = cast<FCmpInst>(Cond);
1575 FCmpInst::Predicate Pred =
1576 InvertCond ? FC->getInversePredicate() : FC->getPredicate();
1577 Condition = getFCmpCondCode(Pred);
1578 if (TM.Options.NoNaNsFPMath)
1579 Condition = getFCmpCodeWithoutNaN(Condition);
1580 }
1581
1582 CaseBlock CB(Condition, BOp->getOperand(0), BOp->getOperand(1), nullptr,
1583 TBB, FBB, CurBB, TProb, FProb);
1584 SwitchCases.push_back(CB);
1585 return;
1586 }
1587 }
1588
1589 // Create a CaseBlock record representing this branch.
1590 ISD::CondCode Opc = InvertCond ? ISD::SETNE : ISD::SETEQ;
1591 CaseBlock CB(Opc, Cond, ConstantInt::getTrue(*DAG.getContext()),
1592 nullptr, TBB, FBB, CurBB, TProb, FProb);
1593 SwitchCases.push_back(CB);
1594}
1595
1596/// FindMergedConditions - If Cond is an expression like
1597void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
1598 MachineBasicBlock *TBB,
1599 MachineBasicBlock *FBB,
1600 MachineBasicBlock *CurBB,
1601 MachineBasicBlock *SwitchBB,
1602 Instruction::BinaryOps Opc,
1603 BranchProbability TProb,
1604 BranchProbability FProb,
1605 bool InvertCond) {
1606 // Skip over not part of the tree and remember to invert op and operands at
1607 // next level.
1608 if (BinaryOperator::isNot(Cond) && Cond->hasOneUse()) {
1609 const Value *CondOp = BinaryOperator::getNotArgument(Cond);
1610 if (InBlock(CondOp, CurBB->getBasicBlock())) {
1611 FindMergedConditions(CondOp, TBB, FBB, CurBB, SwitchBB, Opc, TProb, FProb,
1612 !InvertCond);
1613 return;
1614 }
1615 }
1616
1617 const Instruction *BOp = dyn_cast<Instruction>(Cond);
1618 // Compute the effective opcode for Cond, taking into account whether it needs
1619 // to be inverted, e.g.
1620 // and (not (or A, B)), C
1621 // gets lowered as
1622 // and (and (not A, not B), C)
1623 unsigned BOpc = 0;
1624 if (BOp) {
1625 BOpc = BOp->getOpcode();
1626 if (InvertCond) {
1627 if (BOpc == Instruction::And)
1628 BOpc = Instruction::Or;
1629 else if (BOpc == Instruction::Or)
1630 BOpc = Instruction::And;
1631 }
1632 }
1633
1634 // If this node is not part of the or/and tree, emit it as a branch.
1635 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1636 BOpc != Opc || !BOp->hasOneUse() ||
1637 BOp->getParent() != CurBB->getBasicBlock() ||
1638 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1639 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1640 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB,
1641 TProb, FProb, InvertCond);
1642 return;
1643 }
1644
1645 // Create TmpBB after CurBB.
1646 MachineFunction::iterator BBI(CurBB);
1647 MachineFunction &MF = DAG.getMachineFunction();
1648 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1649 CurBB->getParent()->insert(++BBI, TmpBB);
1650
1651 if (Opc == Instruction::Or) {
1652 // Codegen X | Y as:
1653 // BB1:
1654 // jmp_if_X TBB
1655 // jmp TmpBB
1656 // TmpBB:
1657 // jmp_if_Y TBB
1658 // jmp FBB
1659 //
1660
1661 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1662 // The requirement is that
1663 // TrueProb for BB1 + (FalseProb for BB1 * TrueProb for TmpBB)
1664 // = TrueProb for original BB.
1665 // Assuming the original probabilities are A and B, one choice is to set
1666 // BB1's probabilities to A/2 and A/2+B, and set TmpBB's probabilities to
1667 // A/(1+B) and 2B/(1+B). This choice assumes that
1668 // TrueProb for BB1 == FalseProb for BB1 * TrueProb for TmpBB.
1669 // Another choice is to assume TrueProb for BB1 equals to TrueProb for
1670 // TmpBB, but the math is more complicated.
1671
1672 auto NewTrueProb = TProb / 2;
1673 auto NewFalseProb = TProb / 2 + FProb;
1674 // Emit the LHS condition.
1675 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc,
1676 NewTrueProb, NewFalseProb, InvertCond);
1677
1678 // Normalize A/2 and B to get A/(1+B) and 2B/(1+B).
1679 SmallVector<BranchProbability, 2> Probs{TProb / 2, FProb};
1680 BranchProbability::normalizeProbabilities(Probs.begin(), Probs.end());
1681 // Emit the RHS condition into TmpBB.
1682 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1683 Probs[0], Probs[1], InvertCond);
1684 } else {
1685 assert(Opc == Instruction::And && "Unknown merge op!")((Opc == Instruction::And && "Unknown merge op!") ? static_cast
<void> (0) : __assert_fail ("Opc == Instruction::And && \"Unknown merge op!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 1685, __PRETTY_FUNCTION__))
;
1686 // Codegen X & Y as:
1687 // BB1:
1688 // jmp_if_X TmpBB
1689 // jmp FBB
1690 // TmpBB:
1691 // jmp_if_Y TBB
1692 // jmp FBB
1693 //
1694 // This requires creation of TmpBB after CurBB.
1695
1696 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1697 // The requirement is that
1698 // FalseProb for BB1 + (TrueProb for BB1 * FalseProb for TmpBB)
1699 // = FalseProb for original BB.
1700 // Assuming the original probabilities are A and B, one choice is to set
1701 // BB1's probabilities to A+B/2 and B/2, and set TmpBB's probabilities to
1702 // 2A/(1+A) and B/(1+A). This choice assumes that FalseProb for BB1 ==
1703 // TrueProb for BB1 * FalseProb for TmpBB.
1704
1705 auto NewTrueProb = TProb + FProb / 2;
1706 auto NewFalseProb = FProb / 2;
1707 // Emit the LHS condition.
1708 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc,
1709 NewTrueProb, NewFalseProb, InvertCond);
1710
1711 // Normalize A and B/2 to get 2A/(1+A) and B/(1+A).
1712 SmallVector<BranchProbability, 2> Probs{TProb, FProb / 2};
1713 BranchProbability::normalizeProbabilities(Probs.begin(), Probs.end());
1714 // Emit the RHS condition into TmpBB.
1715 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1716 Probs[0], Probs[1], InvertCond);
1717 }
1718}
1719
1720/// If the set of cases should be emitted as a series of branches, return true.
1721/// If we should emit this as a bunch of and/or'd together conditions, return
1722/// false.
1723bool
1724SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases) {
1725 if (Cases.size() != 2) return true;
1726
1727 // If this is two comparisons of the same values or'd or and'd together, they
1728 // will get folded into a single comparison, so don't emit two blocks.
1729 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1730 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1731 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1732 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1733 return false;
1734 }
1735
1736 // Handle: (X != null) | (Y != null) --> (X|Y) != 0
1737 // Handle: (X == null) & (Y == null) --> (X|Y) == 0
1738 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
1739 Cases[0].CC == Cases[1].CC &&
1740 isa<Constant>(Cases[0].CmpRHS) &&
1741 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
1742 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
1743 return false;
1744 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
1745 return false;
1746 }
1747
1748 return true;
1749}
1750
1751void SelectionDAGBuilder::visitBr(const BranchInst &I) {
1752 MachineBasicBlock *BrMBB = FuncInfo.MBB;
1753
1754 // Update machine-CFG edges.
1755 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1756
1757 if (I.isUnconditional()) {
1758 // Update machine-CFG edges.
1759 BrMBB->addSuccessor(Succ0MBB);
1760
1761 // If this is not a fall-through branch or optimizations are switched off,
1762 // emit the branch.
1763 if (Succ0MBB != NextBlock(BrMBB) || TM.getOptLevel() == CodeGenOpt::None)
1764 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
1765 MVT::Other, getControlRoot(),
1766 DAG.getBasicBlock(Succ0MBB)));
1767
1768 return;
1769 }
1770
1771 // If this condition is one of the special cases we handle, do special stuff
1772 // now.
1773 const Value *CondVal = I.getCondition();
1774 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1775
1776 // If this is a series of conditions that are or'd or and'd together, emit
1777 // this as a sequence of branches instead of setcc's with and/or operations.
1778 // As long as jumps are not expensive, this should improve performance.
1779 // For example, instead of something like:
1780 // cmp A, B
1781 // C = seteq
1782 // cmp D, E
1783 // F = setle
1784 // or C, F
1785 // jnz foo
1786 // Emit:
1787 // cmp A, B
1788 // je foo
1789 // cmp D, E
1790 // jle foo
1791 //
1792 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1793 Instruction::BinaryOps Opcode = BOp->getOpcode();
1794 if (!DAG.getTargetLoweringInfo().isJumpExpensive() && BOp->hasOneUse() &&
1795 !I.getMetadata(LLVMContext::MD_unpredictable) &&
1796 (Opcode == Instruction::And || Opcode == Instruction::Or)) {
1797 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB,
1798 Opcode,
1799 getEdgeProbability(BrMBB, Succ0MBB),
1800 getEdgeProbability(BrMBB, Succ1MBB),
1801 /*InvertCond=*/false);
1802 // If the compares in later blocks need to use values not currently
1803 // exported from this block, export them now. This block should always
1804 // be the first entry.
1805 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!")((SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!"
) ? static_cast<void> (0) : __assert_fail ("SwitchCases[0].ThisBB == BrMBB && \"Unexpected lowering!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 1805, __PRETTY_FUNCTION__))
;
1806
1807 // Allow some cases to be rejected.
1808 if (ShouldEmitAsBranches(SwitchCases)) {
1809 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1810 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1811 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1812 }
1813
1814 // Emit the branch for this block.
1815 visitSwitchCase(SwitchCases[0], BrMBB);
1816 SwitchCases.erase(SwitchCases.begin());
1817 return;
1818 }
1819
1820 // Okay, we decided not to do this, remove any inserted MBB's and clear
1821 // SwitchCases.
1822 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1823 FuncInfo.MF->erase(SwitchCases[i].ThisBB);
1824
1825 SwitchCases.clear();
1826 }
1827 }
1828
1829 // Create a CaseBlock record representing this branch.
1830 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
1831 nullptr, Succ0MBB, Succ1MBB, BrMBB);
1832
1833 // Use visitSwitchCase to actually insert the fast branch sequence for this
1834 // cond branch.
1835 visitSwitchCase(CB, BrMBB);
1836}
1837
1838/// visitSwitchCase - Emits the necessary code to represent a single node in
1839/// the binary search tree resulting from lowering a switch instruction.
1840void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB,
1841 MachineBasicBlock *SwitchBB) {
1842 SDValue Cond;
1843 SDValue CondLHS = getValue(CB.CmpLHS);
1844 SDLoc dl = getCurSDLoc();
1845
1846 // Build the setcc now.
1847 if (!CB.CmpMHS) {
1848 // Fold "(X == true)" to X and "(X == false)" to !X to
1849 // handle common cases produced by branch lowering.
1850 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
1851 CB.CC == ISD::SETEQ)
1852 Cond = CondLHS;
1853 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
1854 CB.CC == ISD::SETEQ) {
1855 SDValue True = DAG.getConstant(1, dl, CondLHS.getValueType());
1856 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1857 } else
1858 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1859 } else {
1860 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now")((CB.CC == ISD::SETLE && "Can handle only LE ranges now"
) ? static_cast<void> (0) : __assert_fail ("CB.CC == ISD::SETLE && \"Can handle only LE ranges now\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 1860, __PRETTY_FUNCTION__))
;
1861
1862 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1863 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1864
1865 SDValue CmpOp = getValue(CB.CmpMHS);
1866 EVT VT = CmpOp.getValueType();
1867
1868 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1869 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, dl, VT),
1870 ISD::SETLE);
1871 } else {
1872 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1873 VT, CmpOp, DAG.getConstant(Low, dl, VT));
1874 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1875 DAG.getConstant(High-Low, dl, VT), ISD::SETULE);
1876 }
1877 }
1878
1879 // Update successor info
1880 addSuccessorWithProb(SwitchBB, CB.TrueBB, CB.TrueProb);
1881 // TrueBB and FalseBB are always different unless the incoming IR is
1882 // degenerate. This only happens when running llc on weird IR.
1883 if (CB.TrueBB != CB.FalseBB)
1884 addSuccessorWithProb(SwitchBB, CB.FalseBB, CB.FalseProb);
1885 SwitchBB->normalizeSuccProbs();
1886
1887 // If the lhs block is the next block, invert the condition so that we can
1888 // fall through to the lhs instead of the rhs block.
1889 if (CB.TrueBB == NextBlock(SwitchBB)) {
1890 std::swap(CB.TrueBB, CB.FalseBB);
1891 SDValue True = DAG.getConstant(1, dl, Cond.getValueType());
1892 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1893 }
1894
1895 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1896 MVT::Other, getControlRoot(), Cond,
1897 DAG.getBasicBlock(CB.TrueBB));
1898
1899 // Insert the false branch. Do this even if it's a fall through branch,
1900 // this makes it easier to do DAG optimizations which require inverting
1901 // the branch condition.
1902 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1903 DAG.getBasicBlock(CB.FalseBB));
1904
1905 DAG.setRoot(BrCond);
1906}
1907
1908/// visitJumpTable - Emit JumpTable node in the current MBB
1909void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
1910 // Emit the code for the jump table
1911 assert(JT.Reg != -1U && "Should lower JT Header first!")((JT.Reg != -1U && "Should lower JT Header first!") ?
static_cast<void> (0) : __assert_fail ("JT.Reg != -1U && \"Should lower JT Header first!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 1911, __PRETTY_FUNCTION__))
;
1912 EVT PTy = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
1913 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(),
1914 JT.Reg, PTy);
1915 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1916 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurSDLoc(),
1917 MVT::Other, Index.getValue(1),
1918 Table, Index);
1919 DAG.setRoot(BrJumpTable);
1920}
1921
1922/// visitJumpTableHeader - This function emits necessary code to produce index
1923/// in the JumpTable from switch case.
1924void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
1925 JumpTableHeader &JTH,
1926 MachineBasicBlock *SwitchBB) {
1927 SDLoc dl = getCurSDLoc();
1928
1929 // Subtract the lowest switch case value from the value being switched on and
1930 // conditional branch to default mbb if the result is greater than the
1931 // difference between smallest and largest cases.
1932 SDValue SwitchOp = getValue(JTH.SValue);
1933 EVT VT = SwitchOp.getValueType();
1934 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, SwitchOp,
1935 DAG.getConstant(JTH.First, dl, VT));
1936
1937 // The SDNode we just created, which holds the value being switched on minus
1938 // the smallest case value, needs to be copied to a virtual register so it
1939 // can be used as an index into the jump table in a subsequent basic block.
1940 // This value may be smaller or larger than the target's pointer type, and
1941 // therefore require extension or truncating.
1942 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1943 SwitchOp = DAG.getZExtOrTrunc(Sub, dl, TLI.getPointerTy(DAG.getDataLayout()));
1944
1945 unsigned JumpTableReg =
1946 FuncInfo.CreateReg(TLI.getPointerTy(DAG.getDataLayout()));
1947 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), dl,
1948 JumpTableReg, SwitchOp);
1949 JT.Reg = JumpTableReg;
1950
1951 // Emit the range check for the jump table, and branch to the default block
1952 // for the switch statement if the value being switched on exceeds the largest
1953 // case in the switch.
1954 SDValue CMP = DAG.getSetCC(
1955 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
1956 Sub.getValueType()),
1957 Sub, DAG.getConstant(JTH.Last - JTH.First, dl, VT), ISD::SETUGT);
1958
1959 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1960 MVT::Other, CopyTo, CMP,
1961 DAG.getBasicBlock(JT.Default));
1962
1963 // Avoid emitting unnecessary branches to the next block.
1964 if (JT.MBB != NextBlock(SwitchBB))
1965 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1966 DAG.getBasicBlock(JT.MBB));
1967
1968 DAG.setRoot(BrCond);
1969}
1970
1971/// Create a LOAD_STACK_GUARD node, and let it carry the target specific global
1972/// variable if there exists one.
1973static SDValue getLoadStackGuard(SelectionDAG &DAG, const SDLoc &DL,
1974 SDValue &Chain) {
1975 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1976 EVT PtrTy = TLI.getPointerTy(DAG.getDataLayout());
1977 MachineFunction &MF = DAG.getMachineFunction();
1978 Value *Global = TLI.getSDagStackGuard(*MF.getFunction()->getParent());
1979 MachineSDNode *Node =
1980 DAG.getMachineNode(TargetOpcode::LOAD_STACK_GUARD, DL, PtrTy, Chain);
1981 if (Global) {
1982 MachinePointerInfo MPInfo(Global);
1983 MachineInstr::mmo_iterator MemRefs = MF.allocateMemRefsArray(1);
1984 auto Flags = MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant |
1985 MachineMemOperand::MODereferenceable;
1986 *MemRefs = MF.getMachineMemOperand(MPInfo, Flags, PtrTy.getSizeInBits() / 8,
1987 DAG.getEVTAlignment(PtrTy));
1988 Node->setMemRefs(MemRefs, MemRefs + 1);
1989 }
1990 return SDValue(Node, 0);
1991}
1992
1993/// Codegen a new tail for a stack protector check ParentMBB which has had its
1994/// tail spliced into a stack protector check success bb.
1995///
1996/// For a high level explanation of how this fits into the stack protector
1997/// generation see the comment on the declaration of class
1998/// StackProtectorDescriptor.
1999void SelectionDAGBuilder::visitSPDescriptorParent(StackProtectorDescriptor &SPD,
2000 MachineBasicBlock *ParentBB) {
2001
2002 // First create the loads to the guard/stack slot for the comparison.
2003 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2004 EVT PtrTy = TLI.getPointerTy(DAG.getDataLayout());
2005
2006 MachineFrameInfo &MFI = ParentBB->getParent()->getFrameInfo();
2007 int FI = MFI.getStackProtectorIndex();
2008
2009 SDValue Guard;
2010 SDLoc dl = getCurSDLoc();
2011 SDValue StackSlotPtr = DAG.getFrameIndex(FI, PtrTy);
2012 const Module &M = *ParentBB->getParent()->getFunction()->getParent();
2013 unsigned Align = DL->getPrefTypeAlignment(Type::getInt8PtrTy(M.getContext()));
2014
2015 // Generate code to load the content of the guard slot.
2016 SDValue StackSlot = DAG.getLoad(
2017 PtrTy, dl, DAG.getEntryNode(), StackSlotPtr,
2018 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI), Align,
2019 MachineMemOperand::MOVolatile);
2020
2021 // Retrieve guard check function, nullptr if instrumentation is inlined.
2022 if (const Value *GuardCheck = TLI.getSSPStackGuardCheck(M)) {
2023 // The target provides a guard check function to validate the guard value.
2024 // Generate a call to that function with the content of the guard slot as
2025 // argument.
2026 auto *Fn = cast<Function>(GuardCheck);
2027 FunctionType *FnTy = Fn->getFunctionType();
2028 assert(FnTy->getNumParams() == 1 && "Invalid function signature")((FnTy->getNumParams() == 1 && "Invalid function signature"
) ? static_cast<void> (0) : __assert_fail ("FnTy->getNumParams() == 1 && \"Invalid function signature\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 2028, __PRETTY_FUNCTION__))
;
2029
2030 TargetLowering::ArgListTy Args;
2031 TargetLowering::ArgListEntry Entry;
2032 Entry.Node = StackSlot;
2033 Entry.Ty = FnTy->getParamType(0);
2034 if (Fn->hasAttribute(1, Attribute::AttrKind::InReg))
2035 Entry.IsInReg = true;
2036 Args.push_back(Entry);
2037
2038 TargetLowering::CallLoweringInfo CLI(DAG);
2039 CLI.setDebugLoc(getCurSDLoc())
2040 .setChain(DAG.getEntryNode())
2041 .setCallee(Fn->getCallingConv(), FnTy->getReturnType(),
2042 getValue(GuardCheck), std::move(Args));
2043
2044 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
2045 DAG.setRoot(Result.second);
2046 return;
2047 }
2048
2049 // If useLoadStackGuardNode returns true, generate LOAD_STACK_GUARD.
2050 // Otherwise, emit a volatile load to retrieve the stack guard value.
2051 SDValue Chain = DAG.getEntryNode();
2052 if (TLI.useLoadStackGuardNode()) {
2053 Guard = getLoadStackGuard(DAG, dl, Chain);
2054 } else {
2055 const Value *IRGuard = TLI.getSDagStackGuard(M);
2056 SDValue GuardPtr = getValue(IRGuard);
2057
2058 Guard =
2059 DAG.getLoad(PtrTy, dl, Chain, GuardPtr, MachinePointerInfo(IRGuard, 0),
2060 Align, MachineMemOperand::MOVolatile);
2061 }
2062
2063 // Perform the comparison via a subtract/getsetcc.
2064 EVT VT = Guard.getValueType();
2065 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, Guard, StackSlot);
2066
2067 SDValue Cmp = DAG.getSetCC(dl, TLI.getSetCCResultType(DAG.getDataLayout(),
2068 *DAG.getContext(),
2069 Sub.getValueType()),
2070 Sub, DAG.getConstant(0, dl, VT), ISD::SETNE);
2071
2072 // If the sub is not 0, then we know the guard/stackslot do not equal, so
2073 // branch to failure MBB.
2074 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
2075 MVT::Other, StackSlot.getOperand(0),
2076 Cmp, DAG.getBasicBlock(SPD.getFailureMBB()));
2077 // Otherwise branch to success MBB.
2078 SDValue Br = DAG.getNode(ISD::BR, dl,
2079 MVT::Other, BrCond,
2080 DAG.getBasicBlock(SPD.getSuccessMBB()));
2081
2082 DAG.setRoot(Br);
2083}
2084
2085/// Codegen the failure basic block for a stack protector check.
2086///
2087/// A failure stack protector machine basic block consists simply of a call to
2088/// __stack_chk_fail().
2089///
2090/// For a high level explanation of how this fits into the stack protector
2091/// generation see the comment on the declaration of class
2092/// StackProtectorDescriptor.
2093void
2094SelectionDAGBuilder::visitSPDescriptorFailure(StackProtectorDescriptor &SPD) {
2095 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2096 SDValue Chain =
2097 TLI.makeLibCall(DAG, RTLIB::STACKPROTECTOR_CHECK_FAIL, MVT::isVoid,
2098 None, false, getCurSDLoc(), false, false).second;
2099 DAG.setRoot(Chain);
2100}
2101
2102/// visitBitTestHeader - This function emits necessary code to produce value
2103/// suitable for "bit tests"
2104void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
2105 MachineBasicBlock *SwitchBB) {
2106 SDLoc dl = getCurSDLoc();
2107
2108 // Subtract the minimum value
2109 SDValue SwitchOp = getValue(B.SValue);
2110 EVT VT = SwitchOp.getValueType();
2111 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, SwitchOp,
2112 DAG.getConstant(B.First, dl, VT));
2113
2114 // Check range
2115 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2116 SDValue RangeCmp = DAG.getSetCC(
2117 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
2118 Sub.getValueType()),
2119 Sub, DAG.getConstant(B.Range, dl, VT), ISD::SETUGT);
2120
2121 // Determine the type of the test operands.
2122 bool UsePtrType = false;
2123 if (!TLI.isTypeLegal(VT))
2124 UsePtrType = true;
2125 else {
2126 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i)
2127 if (!isUIntN(VT.getSizeInBits(), B.Cases[i].Mask)) {
2128 // Switch table case range are encoded into series of masks.
2129 // Just use pointer type, it's guaranteed to fit.
2130 UsePtrType = true;
2131 break;
2132 }
2133 }
2134 if (UsePtrType) {
2135 VT = TLI.getPointerTy(DAG.getDataLayout());
2136 Sub = DAG.getZExtOrTrunc(Sub, dl, VT);
2137 }
2138
2139 B.RegVT = VT.getSimpleVT();
2140 B.Reg = FuncInfo.CreateReg(B.RegVT);
2141 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), dl, B.Reg, Sub);
2142
2143 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
2144
2145 addSuccessorWithProb(SwitchBB, B.Default, B.DefaultProb);
2146 addSuccessorWithProb(SwitchBB, MBB, B.Prob);
2147 SwitchBB->normalizeSuccProbs();
2148
2149 SDValue BrRange = DAG.getNode(ISD::BRCOND, dl,
2150 MVT::Other, CopyTo, RangeCmp,
2151 DAG.getBasicBlock(B.Default));
2152
2153 // Avoid emitting unnecessary branches to the next block.
2154 if (MBB != NextBlock(SwitchBB))
2155 BrRange = DAG.getNode(ISD::BR, dl, MVT::Other, BrRange,
2156 DAG.getBasicBlock(MBB));
2157
2158 DAG.setRoot(BrRange);
2159}
2160
2161/// visitBitTestCase - this function produces one "bit test"
2162void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB,
2163 MachineBasicBlock* NextMBB,
2164 BranchProbability BranchProbToNext,
2165 unsigned Reg,
2166 BitTestCase &B,
2167 MachineBasicBlock *SwitchBB) {
2168 SDLoc dl = getCurSDLoc();
2169 MVT VT = BB.RegVT;
2170 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), dl, Reg, VT);
2171 SDValue Cmp;
2172 unsigned PopCount = countPopulation(B.Mask);
2173 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2174 if (PopCount == 1) {
2175 // Testing for a single bit; just compare the shift count with what it
2176 // would need to be to shift a 1 bit in that position.
2177 Cmp = DAG.getSetCC(
2178 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT),
2179 ShiftOp, DAG.getConstant(countTrailingZeros(B.Mask), dl, VT),
2180 ISD::SETEQ);
2181 } else if (PopCount == BB.Range) {
2182 // There is only one zero bit in the range, test for it directly.
2183 Cmp = DAG.getSetCC(
2184 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT),
2185 ShiftOp, DAG.getConstant(countTrailingOnes(B.Mask), dl, VT),
2186 ISD::SETNE);
2187 } else {
2188 // Make desired shift
2189 SDValue SwitchVal = DAG.getNode(ISD::SHL, dl, VT,
2190 DAG.getConstant(1, dl, VT), ShiftOp);
2191
2192 // Emit bit tests and jumps
2193 SDValue AndOp = DAG.getNode(ISD::AND, dl,
2194 VT, SwitchVal, DAG.getConstant(B.Mask, dl, VT));
2195 Cmp = DAG.getSetCC(
2196 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT),
2197 AndOp, DAG.getConstant(0, dl, VT), ISD::SETNE);
2198 }
2199
2200 // The branch probability from SwitchBB to B.TargetBB is B.ExtraProb.
2201 addSuccessorWithProb(SwitchBB, B.TargetBB, B.ExtraProb);
2202 // The branch probability from SwitchBB to NextMBB is BranchProbToNext.
2203 addSuccessorWithProb(SwitchBB, NextMBB, BranchProbToNext);
2204 // It is not guaranteed that the sum of B.ExtraProb and BranchProbToNext is
2205 // one as they are relative probabilities (and thus work more like weights),
2206 // and hence we need to normalize them to let the sum of them become one.
2207 SwitchBB->normalizeSuccProbs();
2208
2209 SDValue BrAnd = DAG.getNode(ISD::BRCOND, dl,
2210 MVT::Other, getControlRoot(),
2211 Cmp, DAG.getBasicBlock(B.TargetBB));
2212
2213 // Avoid emitting unnecessary branches to the next block.
2214 if (NextMBB != NextBlock(SwitchBB))
2215 BrAnd = DAG.getNode(ISD::BR, dl, MVT::Other, BrAnd,
2216 DAG.getBasicBlock(NextMBB));
2217
2218 DAG.setRoot(BrAnd);
2219}
2220
2221void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
2222 MachineBasicBlock *InvokeMBB = FuncInfo.MBB;
2223
2224 // Retrieve successors. Look through artificial IR level blocks like
2225 // catchswitch for successors.
2226 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
2227 const BasicBlock *EHPadBB = I.getSuccessor(1);
2228
2229 // Deopt bundles are lowered in LowerCallSiteWithDeoptBundle, and we don't
2230 // have to do anything here to lower funclet bundles.
2231 assert(!I.hasOperandBundlesOtherThan(((!I.hasOperandBundlesOtherThan( {LLVMContext::OB_deopt, LLVMContext
::OB_funclet}) && "Cannot lower invokes with arbitrary operand bundles yet!"
) ? static_cast<void> (0) : __assert_fail ("!I.hasOperandBundlesOtherThan( {LLVMContext::OB_deopt, LLVMContext::OB_funclet}) && \"Cannot lower invokes with arbitrary operand bundles yet!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 2233, __PRETTY_FUNCTION__))
2232 {LLVMContext::OB_deopt, LLVMContext::OB_funclet}) &&((!I.hasOperandBundlesOtherThan( {LLVMContext::OB_deopt, LLVMContext
::OB_funclet}) && "Cannot lower invokes with arbitrary operand bundles yet!"
) ? static_cast<void> (0) : __assert_fail ("!I.hasOperandBundlesOtherThan( {LLVMContext::OB_deopt, LLVMContext::OB_funclet}) && \"Cannot lower invokes with arbitrary operand bundles yet!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 2233, __PRETTY_FUNCTION__))
2233 "Cannot lower invokes with arbitrary operand bundles yet!")((!I.hasOperandBundlesOtherThan( {LLVMContext::OB_deopt, LLVMContext
::OB_funclet}) && "Cannot lower invokes with arbitrary operand bundles yet!"
) ? static_cast<void> (0) : __assert_fail ("!I.hasOperandBundlesOtherThan( {LLVMContext::OB_deopt, LLVMContext::OB_funclet}) && \"Cannot lower invokes with arbitrary operand bundles yet!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 2233, __PRETTY_FUNCTION__))
;
2234
2235 const Value *Callee(I.getCalledValue());
2236 const Function *Fn = dyn_cast<Function>(Callee);
2237 if (isa<InlineAsm>(Callee))
2238 visitInlineAsm(&I);
2239 else if (Fn && Fn->isIntrinsic()) {
2240 switch (Fn->getIntrinsicID()) {
2241 default:
2242 llvm_unreachable("Cannot invoke this intrinsic")::llvm::llvm_unreachable_internal("Cannot invoke this intrinsic"
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 2242)
;
2243 case Intrinsic::donothing:
2244 // Ignore invokes to @llvm.donothing: jump directly to the next BB.
2245 break;
2246 case Intrinsic::experimental_patchpoint_void:
2247 case Intrinsic::experimental_patchpoint_i64:
2248 visitPatchpoint(&I, EHPadBB);
2249 break;
2250 case Intrinsic::experimental_gc_statepoint:
2251 LowerStatepoint(ImmutableStatepoint(&I), EHPadBB);
2252 break;
2253 }
2254 } else if (I.countOperandBundlesOfType(LLVMContext::OB_deopt)) {
2255 // Currently we do not lower any intrinsic calls with deopt operand bundles.
2256 // Eventually we will support lowering the @llvm.experimental.deoptimize
2257 // intrinsic, and right now there are no plans to support other intrinsics
2258 // with deopt state.
2259 LowerCallSiteWithDeoptBundle(&I, getValue(Callee), EHPadBB);
2260 } else {
2261 LowerCallTo(&I, getValue(Callee), false, EHPadBB);
2262 }
2263
2264 // If the value of the invoke is used outside of its defining block, make it
2265 // available as a virtual register.
2266 // We already took care of the exported value for the statepoint instruction
2267 // during call to the LowerStatepoint.
2268 if (!isStatepoint(I)) {
2269 CopyToExportRegsIfNeeded(&I);
2270 }
2271
2272 SmallVector<std::pair<MachineBasicBlock *, BranchProbability>, 1> UnwindDests;
2273 BranchProbabilityInfo *BPI = FuncInfo.BPI;
2274 BranchProbability EHPadBBProb =
2275 BPI ? BPI->getEdgeProbability(InvokeMBB->getBasicBlock(), EHPadBB)
2276 : BranchProbability::getZero();
2277 findUnwindDestinations(FuncInfo, EHPadBB, EHPadBBProb, UnwindDests);
2278
2279 // Update successor info.
2280 addSuccessorWithProb(InvokeMBB, Return);
2281 for (auto &UnwindDest : UnwindDests) {
2282 UnwindDest.first->setIsEHPad();
2283 addSuccessorWithProb(InvokeMBB, UnwindDest.first, UnwindDest.second);
2284 }
2285 InvokeMBB->normalizeSuccProbs();
2286
2287 // Drop into normal successor.
2288 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
2289 MVT::Other, getControlRoot(),
2290 DAG.getBasicBlock(Return)));
2291}
2292
2293void SelectionDAGBuilder::visitResume(const ResumeInst &RI) {
2294 llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!")::llvm::llvm_unreachable_internal("SelectionDAGBuilder shouldn't visit resume instructions!"
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 2294)
;
2295}
2296
2297void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) {
2298 assert(FuncInfo.MBB->isEHPad() &&((FuncInfo.MBB->isEHPad() && "Call to landingpad not in landing pad!"
) ? static_cast<void> (0) : __assert_fail ("FuncInfo.MBB->isEHPad() && \"Call to landingpad not in landing pad!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 2299, __PRETTY_FUNCTION__))
2299 "Call to landingpad not in landing pad!")((FuncInfo.MBB->isEHPad() && "Call to landingpad not in landing pad!"
) ? static_cast<void> (0) : __assert_fail ("FuncInfo.MBB->isEHPad() && \"Call to landingpad not in landing pad!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 2299, __PRETTY_FUNCTION__))
;
2300
2301 MachineBasicBlock *MBB = FuncInfo.MBB;
2302 addLandingPadInfo(LP, *MBB);
2303
2304 // If there aren't registers to copy the values into (e.g., during SjLj
2305 // exceptions), then don't bother to create these DAG nodes.
2306 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2307 const Constant *PersonalityFn = FuncInfo.Fn->getPersonalityFn();
2308 if (TLI.getExceptionPointerRegister(PersonalityFn) == 0 &&
2309 TLI.getExceptionSelectorRegister(PersonalityFn) == 0)
2310 return;
2311
2312 // If landingpad's return type is token type, we don't create DAG nodes
2313 // for its exception pointer and selector value. The extraction of exception
2314 // pointer or selector value from token type landingpads is not currently
2315 // supported.
2316 if (LP.getType()->isTokenTy())
2317 return;
2318
2319 SmallVector<EVT, 2> ValueVTs;
2320 SDLoc dl = getCurSDLoc();
2321 ComputeValueVTs(TLI, DAG.getDataLayout(), LP.getType(), ValueVTs);
2322 assert(ValueVTs.size() == 2 && "Only two-valued landingpads are supported")((ValueVTs.size() == 2 && "Only two-valued landingpads are supported"
) ? static_cast<void> (0) : __assert_fail ("ValueVTs.size() == 2 && \"Only two-valued landingpads are supported\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 2322, __PRETTY_FUNCTION__))
;
2323
2324 // Get the two live-in registers as SDValues. The physregs have already been
2325 // copied into virtual registers.
2326 SDValue Ops[2];
2327 if (FuncInfo.ExceptionPointerVirtReg) {
2328 Ops[0] = DAG.getZExtOrTrunc(
2329 DAG.getCopyFromReg(DAG.getEntryNode(), dl,
2330 FuncInfo.ExceptionPointerVirtReg,
2331 TLI.getPointerTy(DAG.getDataLayout())),
2332 dl, ValueVTs[0]);
2333 } else {
2334 Ops[0] = DAG.getConstant(0, dl, TLI.getPointerTy(DAG.getDataLayout()));
2335 }
2336 Ops[1] = DAG.getZExtOrTrunc(
2337 DAG.getCopyFromReg(DAG.getEntryNode(), dl,
2338 FuncInfo.ExceptionSelectorVirtReg,
2339 TLI.getPointerTy(DAG.getDataLayout())),
2340 dl, ValueVTs[1]);
2341
2342 // Merge into one.
2343 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl,
2344 DAG.getVTList(ValueVTs), Ops);
2345 setValue(&LP, Res);
2346}
2347
2348void SelectionDAGBuilder::sortAndRangeify(CaseClusterVector &Clusters) {
2349#ifndef NDEBUG
2350 for (const CaseCluster &CC : Clusters)
2351 assert(CC.Low == CC.High && "Input clusters must be single-case")((CC.Low == CC.High && "Input clusters must be single-case"
) ? static_cast<void> (0) : __assert_fail ("CC.Low == CC.High && \"Input clusters must be single-case\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 2351, __PRETTY_FUNCTION__))
;
2352#endif
2353
2354 std::sort(Clusters.begin(), Clusters.end(),
2355 [](const CaseCluster &a, const CaseCluster &b) {
2356 return a.Low->getValue().slt(b.Low->getValue());
2357 });
2358
2359 // Merge adjacent clusters with the same destination.
2360 const unsigned N = Clusters.size();
2361 unsigned DstIndex = 0;
2362 for (unsigned SrcIndex = 0; SrcIndex < N; ++SrcIndex) {
2363 CaseCluster &CC = Clusters[SrcIndex];
2364 const ConstantInt *CaseVal = CC.Low;
2365 MachineBasicBlock *Succ = CC.MBB;
2366
2367 if (DstIndex != 0 && Clusters[DstIndex - 1].MBB == Succ &&
2368 (CaseVal->getValue() - Clusters[DstIndex - 1].High->getValue()) == 1) {
2369 // If this case has the same successor and is a neighbour, merge it into
2370 // the previous cluster.
2371 Clusters[DstIndex - 1].High = CaseVal;
2372 Clusters[DstIndex - 1].Prob += CC.Prob;
2373 } else {
2374 std::memmove(&Clusters[DstIndex++], &Clusters[SrcIndex],
2375 sizeof(Clusters[SrcIndex]));
2376 }
2377 }
2378 Clusters.resize(DstIndex);
2379}
2380
2381void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First,
2382 MachineBasicBlock *Last) {
2383 // Update JTCases.
2384 for (unsigned i = 0, e = JTCases.size(); i != e; ++i)
2385 if (JTCases[i].first.HeaderBB == First)
2386 JTCases[i].first.HeaderBB = Last;
2387
2388 // Update BitTestCases.
2389 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i)
2390 if (BitTestCases[i].Parent == First)
2391 BitTestCases[i].Parent = Last;
2392}
2393
2394void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
2395 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB;
2396
2397 // Update machine-CFG edges with unique successors.
2398 SmallSet<BasicBlock*, 32> Done;
2399 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) {
2400 BasicBlock *BB = I.getSuccessor(i);
2401 bool Inserted = Done.insert(BB).second;
2402 if (!Inserted)
2403 continue;
2404
2405 MachineBasicBlock *Succ = FuncInfo.MBBMap[BB];
2406 addSuccessorWithProb(IndirectBrMBB, Succ);
2407 }
2408 IndirectBrMBB->normalizeSuccProbs();
2409
2410 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurSDLoc(),
2411 MVT::Other, getControlRoot(),
2412 getValue(I.getAddress())));
2413}
2414
2415void SelectionDAGBuilder::visitUnreachable(const UnreachableInst &I) {
2416 if (DAG.getTarget().Options.TrapUnreachable)
2417 DAG.setRoot(
2418 DAG.getNode(ISD::TRAP, getCurSDLoc(), MVT::Other, DAG.getRoot()));
2419}
2420
2421void SelectionDAGBuilder::visitFSub(const User &I) {
2422 // -0.0 - X --> fneg
2423 Type *Ty = I.getType();
2424 if (isa<Constant>(I.getOperand(0)) &&
2425 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) {
2426 SDValue Op2 = getValue(I.getOperand(1));
2427 setValue(&I, DAG.getNode(ISD::FNEG, getCurSDLoc(),
2428 Op2.getValueType(), Op2));
2429 return;
2430 }
2431
2432 visitBinary(I, ISD::FSUB);
2433}
2434
2435/// Checks if the given instruction performs a vector reduction, in which case
2436/// we have the freedom to alter the elements in the result as long as the
2437/// reduction of them stays unchanged.
2438static bool isVectorReductionOp(const User *I) {
2439 const Instruction *Inst = dyn_cast<Instruction>(I);
2440 if (!Inst || !Inst->getType()->isVectorTy())
2441 return false;
2442
2443 auto OpCode = Inst->getOpcode();
2444 switch (OpCode) {
2445 case Instruction::Add:
2446 case Instruction::Mul:
2447 case Instruction::And:
2448 case Instruction::Or:
2449 case Instruction::Xor:
2450 break;
2451 case Instruction::FAdd:
2452 case Instruction::FMul:
2453 if (const FPMathOperator *FPOp = dyn_cast<const FPMathOperator>(Inst))
2454 if (FPOp->getFastMathFlags().unsafeAlgebra())
2455 break;
2456 LLVM_FALLTHROUGH[[clang::fallthrough]];
2457 default:
2458 return false;
2459 }
2460
2461 unsigned ElemNum = Inst->getType()->getVectorNumElements();
2462 unsigned ElemNumToReduce = ElemNum;
2463
2464 // Do DFS search on the def-use chain from the given instruction. We only
2465 // allow four kinds of operations during the search until we reach the
2466 // instruction that extracts the first element from the vector:
2467 //
2468 // 1. The reduction operation of the same opcode as the given instruction.
2469 //
2470 // 2. PHI node.
2471 //
2472 // 3. ShuffleVector instruction together with a reduction operation that
2473 // does a partial reduction.
2474 //
2475 // 4. ExtractElement that extracts the first element from the vector, and we
2476 // stop searching the def-use chain here.
2477 //
2478 // 3 & 4 above perform a reduction on all elements of the vector. We push defs
2479 // from 1-3 to the stack to continue the DFS. The given instruction is not
2480 // a reduction operation if we meet any other instructions other than those
2481 // listed above.
2482
2483 SmallVector<const User *, 16> UsersToVisit{Inst};
2484 SmallPtrSet<const User *, 16> Visited;
2485 bool ReduxExtracted = false;
2486
2487 while (!UsersToVisit.empty()) {
2488 auto User = UsersToVisit.back();
2489 UsersToVisit.pop_back();
2490 if (!Visited.insert(User).second)
2491 continue;
2492
2493 for (const auto &U : User->users()) {
2494 auto Inst = dyn_cast<Instruction>(U);
2495 if (!Inst)
2496 return false;
2497
2498 if (Inst->getOpcode() == OpCode || isa<PHINode>(U)) {
2499 if (const FPMathOperator *FPOp = dyn_cast<const FPMathOperator>(Inst))
2500 if (!isa<PHINode>(FPOp) && !FPOp->getFastMathFlags().unsafeAlgebra())
2501 return false;
2502 UsersToVisit.push_back(U);
2503 } else if (const ShuffleVectorInst *ShufInst =
2504 dyn_cast<ShuffleVectorInst>(U)) {
2505 // Detect the following pattern: A ShuffleVector instruction together
2506 // with a reduction that do partial reduction on the first and second
2507 // ElemNumToReduce / 2 elements, and store the result in
2508 // ElemNumToReduce / 2 elements in another vector.
2509
2510 unsigned ResultElements = ShufInst->getType()->getVectorNumElements();
2511 if (ResultElements < ElemNum)
2512 return false;
2513
2514 if (ElemNumToReduce == 1)
2515 return false;
2516 if (!isa<UndefValue>(U->getOperand(1)))
2517 return false;
2518 for (unsigned i = 0; i < ElemNumToReduce / 2; ++i)
2519 if (ShufInst->getMaskValue(i) != int(i + ElemNumToReduce / 2))
2520 return false;
2521 for (unsigned i = ElemNumToReduce / 2; i < ElemNum; ++i)
2522 if (ShufInst->getMaskValue(i) != -1)
2523 return false;
2524
2525 // There is only one user of this ShuffleVector instruction, which
2526 // must be a reduction operation.
2527 if (!U->hasOneUse())
2528 return false;
2529
2530 auto U2 = dyn_cast<Instruction>(*U->user_begin());
2531 if (!U2 || U2->getOpcode() != OpCode)
2532 return false;
2533
2534 // Check operands of the reduction operation.
2535 if ((U2->getOperand(0) == U->getOperand(0) && U2->getOperand(1) == U) ||
2536 (U2->getOperand(1) == U->getOperand(0) && U2->getOperand(0) == U)) {
2537 UsersToVisit.push_back(U2);
2538 ElemNumToReduce /= 2;
2539 } else
2540 return false;
2541 } else if (isa<ExtractElementInst>(U)) {
2542 // At this moment we should have reduced all elements in the vector.
2543 if (ElemNumToReduce != 1)
2544 return false;
2545
2546 const ConstantInt *Val = dyn_cast<ConstantInt>(U->getOperand(1));
2547 if (!Val || Val->getZExtValue() != 0)
2548 return false;
2549
2550 ReduxExtracted = true;
2551 } else
2552 return false;
2553 }
2554 }
2555 return ReduxExtracted;
2556}
2557
2558void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
2559 SDValue Op1 = getValue(I.getOperand(0));
2560 SDValue Op2 = getValue(I.getOperand(1));
2561
2562 bool nuw = false;
2563 bool nsw = false;
2564 bool exact = false;
2565 bool vec_redux = false;
2566 FastMathFlags FMF;
2567
2568 if (const OverflowingBinaryOperator *OFBinOp =
2569 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2570 nuw = OFBinOp->hasNoUnsignedWrap();
2571 nsw = OFBinOp->hasNoSignedWrap();
2572 }
2573 if (const PossiblyExactOperator *ExactOp =
2574 dyn_cast<const PossiblyExactOperator>(&I))
2575 exact = ExactOp->isExact();
2576 if (const FPMathOperator *FPOp = dyn_cast<const FPMathOperator>(&I))
2577 FMF = FPOp->getFastMathFlags();
2578
2579 if (isVectorReductionOp(&I)) {
2580 vec_redux = true;
2581 DEBUG(dbgs() << "Detected a reduction operation:" << I << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << "Detected a reduction operation:"
<< I << "\n"; } } while (false)
;
2582 }
2583
2584 SDNodeFlags Flags;
2585 Flags.setExact(exact);
2586 Flags.setNoSignedWrap(nsw);
2587 Flags.setNoUnsignedWrap(nuw);
2588 Flags.setVectorReduction(vec_redux);
2589 if (EnableFMFInDAG) {
2590 Flags.setAllowReciprocal(FMF.allowReciprocal());
2591 Flags.setNoInfs(FMF.noInfs());
2592 Flags.setNoNaNs(FMF.noNaNs());
2593 Flags.setNoSignedZeros(FMF.noSignedZeros());
2594 Flags.setUnsafeAlgebra(FMF.unsafeAlgebra());
2595 }
2596 SDValue BinNodeValue = DAG.getNode(OpCode, getCurSDLoc(), Op1.getValueType(),
2597 Op1, Op2, &Flags);
2598 setValue(&I, BinNodeValue);
2599}
2600
2601void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
2602 SDValue Op1 = getValue(I.getOperand(0));
2603 SDValue Op2 = getValue(I.getOperand(1));
2604
2605 EVT ShiftTy = DAG.getTargetLoweringInfo().getShiftAmountTy(
2606 Op2.getValueType(), DAG.getDataLayout());
2607
2608 // Coerce the shift amount to the right type if we can.
2609 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) {
2610 unsigned ShiftSize = ShiftTy.getSizeInBits();
2611 unsigned Op2Size = Op2.getValueSizeInBits();
2612 SDLoc DL = getCurSDLoc();
2613
2614 // If the operand is smaller than the shift count type, promote it.
2615 if (ShiftSize > Op2Size)
2616 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2);
2617
2618 // If the operand is larger than the shift count type but the shift
2619 // count type has enough bits to represent any shift value, truncate
2620 // it now. This is a common case and it exposes the truncate to
2621 // optimization early.
2622 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueSizeInBits()))
2623 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2);
2624 // Otherwise we'll need to temporarily settle for some other convenient
2625 // type. Type legalization will make adjustments once the shiftee is split.
2626 else
2627 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32);
2628 }
2629
2630 bool nuw = false;
2631 bool nsw = false;
2632 bool exact = false;
2633
2634 if (Opcode == ISD::SRL || Opcode == ISD::SRA || Opcode == ISD::SHL) {
2635
2636 if (const OverflowingBinaryOperator *OFBinOp =
2637 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2638 nuw = OFBinOp->hasNoUnsignedWrap();
2639 nsw = OFBinOp->hasNoSignedWrap();
2640 }
2641 if (const PossiblyExactOperator *ExactOp =
2642 dyn_cast<const PossiblyExactOperator>(&I))
2643 exact = ExactOp->isExact();
2644 }
2645 SDNodeFlags Flags;
2646 Flags.setExact(exact);
2647 Flags.setNoSignedWrap(nsw);
2648 Flags.setNoUnsignedWrap(nuw);
2649 SDValue Res = DAG.getNode(Opcode, getCurSDLoc(), Op1.getValueType(), Op1, Op2,
2650 &Flags);
2651 setValue(&I, Res);
2652}
2653
2654void SelectionDAGBuilder::visitSDiv(const User &I) {
2655 SDValue Op1 = getValue(I.getOperand(0));
2656 SDValue Op2 = getValue(I.getOperand(1));
2657
2658 SDNodeFlags Flags;
2659 Flags.setExact(isa<PossiblyExactOperator>(&I) &&
2660 cast<PossiblyExactOperator>(&I)->isExact());
2661 setValue(&I, DAG.getNode(ISD::SDIV, getCurSDLoc(), Op1.getValueType(), Op1,
2662 Op2, &Flags));
2663}
2664
2665void SelectionDAGBuilder::visitICmp(const User &I) {
2666 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2667 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2668 predicate = IC->getPredicate();
2669 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2670 predicate = ICmpInst::Predicate(IC->getPredicate());
2671 SDValue Op1 = getValue(I.getOperand(0));
2672 SDValue Op2 = getValue(I.getOperand(1));
2673 ISD::CondCode Opcode = getICmpCondCode(predicate);
2674
2675 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2676 I.getType());
2677 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Opcode));
2678}
2679
2680void SelectionDAGBuilder::visitFCmp(const User &I) {
2681 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2682 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2683 predicate = FC->getPredicate();
2684 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2685 predicate = FCmpInst::Predicate(FC->getPredicate());
2686 SDValue Op1 = getValue(I.getOperand(0));
2687 SDValue Op2 = getValue(I.getOperand(1));
2688 ISD::CondCode Condition = getFCmpCondCode(predicate);
2689
2690 // FIXME: Fcmp instructions have fast-math-flags in IR, so we should use them.
2691 // FIXME: We should propagate the fast-math-flags to the DAG node itself for
2692 // further optimization, but currently FMF is only applicable to binary nodes.
2693 if (TM.Options.NoNaNsFPMath)
2694 Condition = getFCmpCodeWithoutNaN(Condition);
2695 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2696 I.getType());
2697 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Condition));
2698}
2699
2700// Check if the condition of the select has one use or two users that are both
2701// selects with the same condition.
2702static bool hasOnlySelectUsers(const Value *Cond) {
2703 return all_of(Cond->users(), [](const Value *V) {
2704 return isa<SelectInst>(V);
2705 });
2706}
2707
2708void SelectionDAGBuilder::visitSelect(const User &I) {
2709 SmallVector<EVT, 4> ValueVTs;
2710 ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(), I.getType(),
2711 ValueVTs);
2712 unsigned NumValues = ValueVTs.size();
2713 if (NumValues == 0) return;
2714
2715 SmallVector<SDValue, 4> Values(NumValues);
2716 SDValue Cond = getValue(I.getOperand(0));
2717 SDValue LHSVal = getValue(I.getOperand(1));
2718 SDValue RHSVal = getValue(I.getOperand(2));
2719 auto BaseOps = {Cond};
2720 ISD::NodeType OpCode = Cond.getValueType().isVector() ?
2721 ISD::VSELECT : ISD::SELECT;
2722
2723 // Min/max matching is only viable if all output VTs are the same.
2724 if (std::equal(ValueVTs.begin(), ValueVTs.end(), ValueVTs.begin())) {
2725 EVT VT = ValueVTs[0];
2726 LLVMContext &Ctx = *DAG.getContext();
2727 auto &TLI = DAG.getTargetLoweringInfo();
2728
2729 // We care about the legality of the operation after it has been type
2730 // legalized.
2731 while (TLI.getTypeAction(Ctx, VT) != TargetLoweringBase::TypeLegal &&
2732 VT != TLI.getTypeToTransformTo(Ctx, VT))
2733 VT = TLI.getTypeToTransformTo(Ctx, VT);
2734
2735 // If the vselect is legal, assume we want to leave this as a vector setcc +
2736 // vselect. Otherwise, if this is going to be scalarized, we want to see if
2737 // min/max is legal on the scalar type.
2738 bool UseScalarMinMax = VT.isVector() &&
2739 !TLI.isOperationLegalOrCustom(ISD::VSELECT, VT);
2740
2741 Value *LHS, *RHS;
2742 auto SPR = matchSelectPattern(const_cast<User*>(&I), LHS, RHS);
2743 ISD::NodeType Opc = ISD::DELETED_NODE;
2744 switch (SPR.Flavor) {
2745 case SPF_UMAX: Opc = ISD::UMAX; break;
2746 case SPF_UMIN: Opc = ISD::UMIN; break;
2747 case SPF_SMAX: Opc = ISD::SMAX; break;
2748 case SPF_SMIN: Opc = ISD::SMIN; break;
2749 case SPF_FMINNUM:
2750 switch (SPR.NaNBehavior) {
2751 case SPNB_NA: llvm_unreachable("No NaN behavior for FP op?")::llvm::llvm_unreachable_internal("No NaN behavior for FP op?"
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 2751)
;
2752 case SPNB_RETURNS_NAN: Opc = ISD::FMINNAN; break;
2753 case SPNB_RETURNS_OTHER: Opc = ISD::FMINNUM; break;
2754 case SPNB_RETURNS_ANY: {
2755 if (TLI.isOperationLegalOrCustom(ISD::FMINNUM, VT))
2756 Opc = ISD::FMINNUM;
2757 else if (TLI.isOperationLegalOrCustom(ISD::FMINNAN, VT))
2758 Opc = ISD::FMINNAN;
2759 else if (UseScalarMinMax)
2760 Opc = TLI.isOperationLegalOrCustom(ISD::FMINNUM, VT.getScalarType()) ?
2761 ISD::FMINNUM : ISD::FMINNAN;
2762 break;
2763 }
2764 }
2765 break;
2766 case SPF_FMAXNUM:
2767 switch (SPR.NaNBehavior) {
2768 case SPNB_NA: llvm_unreachable("No NaN behavior for FP op?")::llvm::llvm_unreachable_internal("No NaN behavior for FP op?"
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 2768)
;
2769 case SPNB_RETURNS_NAN: Opc = ISD::FMAXNAN; break;
2770 case SPNB_RETURNS_OTHER: Opc = ISD::FMAXNUM; break;
2771 case SPNB_RETURNS_ANY:
2772
2773 if (TLI.isOperationLegalOrCustom(ISD::FMAXNUM, VT))
2774 Opc = ISD::FMAXNUM;
2775 else if (TLI.isOperationLegalOrCustom(ISD::FMAXNAN, VT))
2776 Opc = ISD::FMAXNAN;
2777 else if (UseScalarMinMax)
2778 Opc = TLI.isOperationLegalOrCustom(ISD::FMAXNUM, VT.getScalarType()) ?
2779 ISD::FMAXNUM : ISD::FMAXNAN;
2780 break;
2781 }
2782 break;
2783 default: break;
2784 }
2785
2786 if (Opc != ISD::DELETED_NODE &&
2787 (TLI.isOperationLegalOrCustom(Opc, VT) ||
2788 (UseScalarMinMax &&
2789 TLI.isOperationLegalOrCustom(Opc, VT.getScalarType()))) &&
2790 // If the underlying comparison instruction is used by any other
2791 // instruction, the consumed instructions won't be destroyed, so it is
2792 // not profitable to convert to a min/max.
2793 hasOnlySelectUsers(cast<SelectInst>(I).getCondition())) {
2794 OpCode = Opc;
2795 LHSVal = getValue(LHS);
2796 RHSVal = getValue(RHS);
2797 BaseOps = {};
2798 }
2799 }
2800
2801 for (unsigned i = 0; i != NumValues; ++i) {
2802 SmallVector<SDValue, 3> Ops(BaseOps.begin(), BaseOps.end());
2803 Ops.push_back(SDValue(LHSVal.getNode(), LHSVal.getResNo() + i));
2804 Ops.push_back(SDValue(RHSVal.getNode(), RHSVal.getResNo() + i));
2805 Values[i] = DAG.getNode(OpCode, getCurSDLoc(),
2806 LHSVal.getNode()->getValueType(LHSVal.getResNo()+i),
2807 Ops);
2808 }
2809
2810 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2811 DAG.getVTList(ValueVTs), Values));
2812}
2813
2814void SelectionDAGBuilder::visitTrunc(const User &I) {
2815 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2816 SDValue N = getValue(I.getOperand(0));
2817 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2818 I.getType());
2819 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), DestVT, N));
2820}
2821
2822void SelectionDAGBuilder::visitZExt(const User &I) {
2823 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2824 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2825 SDValue N = getValue(I.getOperand(0));
2826 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2827 I.getType());
2828 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurSDLoc(), DestVT, N));
2829}
2830
2831void SelectionDAGBuilder::visitSExt(const User &I) {
2832 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2833 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2834 SDValue N = getValue(I.getOperand(0));
2835 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2836 I.getType());
2837 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurSDLoc(), DestVT, N));
2838}
2839
2840void SelectionDAGBuilder::visitFPTrunc(const User &I) {
2841 // FPTrunc is never a no-op cast, no need to check
2842 SDValue N = getValue(I.getOperand(0));
2843 SDLoc dl = getCurSDLoc();
2844 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2845 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
2846 setValue(&I, DAG.getNode(ISD::FP_ROUND, dl, DestVT, N,
2847 DAG.getTargetConstant(
2848 0, dl, TLI.getPointerTy(DAG.getDataLayout()))));
2849}
2850
2851void SelectionDAGBuilder::visitFPExt(const User &I) {
2852 // FPExt is never a no-op cast, no need to check
2853 SDValue N = getValue(I.getOperand(0));
2854 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2855 I.getType());
2856 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurSDLoc(), DestVT, N));
2857}
2858
2859void SelectionDAGBuilder::visitFPToUI(const User &I) {
2860 // FPToUI is never a no-op cast, no need to check
2861 SDValue N = getValue(I.getOperand(0));
2862 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2863 I.getType());
2864 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurSDLoc(), DestVT, N));
2865}
2866
2867void SelectionDAGBuilder::visitFPToSI(const User &I) {
2868 // FPToSI is never a no-op cast, no need to check
2869 SDValue N = getValue(I.getOperand(0));
2870 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2871 I.getType());
2872 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurSDLoc(), DestVT, N));
2873}
2874
2875void SelectionDAGBuilder::visitUIToFP(const User &I) {
2876 // UIToFP is never a no-op cast, no need to check
2877 SDValue N = getValue(I.getOperand(0));
2878 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2879 I.getType());
2880 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurSDLoc(), DestVT, N));
2881}
2882
2883void SelectionDAGBuilder::visitSIToFP(const User &I) {
2884 // SIToFP is never a no-op cast, no need to check
2885 SDValue N = getValue(I.getOperand(0));
2886 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2887 I.getType());
2888 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurSDLoc(), DestVT, N));
2889}
2890
2891void SelectionDAGBuilder::visitPtrToInt(const User &I) {
2892 // What to do depends on the size of the integer and the size of the pointer.
2893 // We can either truncate, zero extend, or no-op, accordingly.
2894 SDValue N = getValue(I.getOperand(0));
2895 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2896 I.getType());
2897 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
2898}
2899
2900void SelectionDAGBuilder::visitIntToPtr(const User &I) {
2901 // What to do depends on the size of the integer and the size of the pointer.
2902 // We can either truncate, zero extend, or no-op, accordingly.
2903 SDValue N = getValue(I.getOperand(0));
2904 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2905 I.getType());
2906 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
2907}
2908
2909void SelectionDAGBuilder::visitBitCast(const User &I) {
2910 SDValue N = getValue(I.getOperand(0));
2911 SDLoc dl = getCurSDLoc();
2912 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2913 I.getType());
2914
2915 // BitCast assures us that source and destination are the same size so this is
2916 // either a BITCAST or a no-op.
2917 if (DestVT != N.getValueType())
2918 setValue(&I, DAG.getNode(ISD::BITCAST, dl,
2919 DestVT, N)); // convert types.
2920 // Check if the original LLVM IR Operand was a ConstantInt, because getValue()
2921 // might fold any kind of constant expression to an integer constant and that
2922 // is not what we are looking for. Only recognize a bitcast of a genuine
2923 // constant integer as an opaque constant.
2924 else if(ConstantInt *C = dyn_cast<ConstantInt>(I.getOperand(0)))
2925 setValue(&I, DAG.getConstant(C->getValue(), dl, DestVT, /*isTarget=*/false,
2926 /*isOpaque*/true));
2927 else
2928 setValue(&I, N); // noop cast.
2929}
2930
2931void SelectionDAGBuilder::visitAddrSpaceCast(const User &I) {
2932 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2933 const Value *SV = I.getOperand(0);
2934 SDValue N = getValue(SV);
2935 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
2936
2937 unsigned SrcAS = SV->getType()->getPointerAddressSpace();
2938 unsigned DestAS = I.getType()->getPointerAddressSpace();
2939
2940 if (!TLI.isNoopAddrSpaceCast(SrcAS, DestAS))
2941 N = DAG.getAddrSpaceCast(getCurSDLoc(), DestVT, N, SrcAS, DestAS);
2942
2943 setValue(&I, N);
2944}
2945
2946void SelectionDAGBuilder::visitInsertElement(const User &I) {
2947 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2948 SDValue InVec = getValue(I.getOperand(0));
2949 SDValue InVal = getValue(I.getOperand(1));
2950 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(2)), getCurSDLoc(),
2951 TLI.getVectorIdxTy(DAG.getDataLayout()));
2952 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurSDLoc(),
2953 TLI.getValueType(DAG.getDataLayout(), I.getType()),
2954 InVec, InVal, InIdx));
2955}
2956
2957void SelectionDAGBuilder::visitExtractElement(const User &I) {
2958 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2959 SDValue InVec = getValue(I.getOperand(0));
2960 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(1)), getCurSDLoc(),
2961 TLI.getVectorIdxTy(DAG.getDataLayout()));
2962 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(),
2963 TLI.getValueType(DAG.getDataLayout(), I.getType()),
2964 InVec, InIdx));
2965}
2966
2967void SelectionDAGBuilder::visitShuffleVector(const User &I) {
2968 SDValue Src1 = getValue(I.getOperand(0));
2969 SDValue Src2 = getValue(I.getOperand(1));
2970 SDLoc DL = getCurSDLoc();
2971
2972 SmallVector<int, 8> Mask;
2973 ShuffleVectorInst::getShuffleMask(cast<Constant>(I.getOperand(2)), Mask);
2974 unsigned MaskNumElts = Mask.size();
2975
2976 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2977 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
2978 EVT SrcVT = Src1.getValueType();
2979 unsigned SrcNumElts = SrcVT.getVectorNumElements();
2980
2981 if (SrcNumElts == MaskNumElts) {
2982 setValue(&I, DAG.getVectorShuffle(VT, DL, Src1, Src2, Mask));
2983 return;
2984 }
2985
2986 // Normalize the shuffle vector since mask and vector length don't match.
2987 if (SrcNumElts < MaskNumElts) {
2988 // Mask is longer than the source vectors. We can use concatenate vector to
2989 // make the mask and vectors lengths match.
2990
2991 if (MaskNumElts % SrcNumElts == 0) {
2992 // Mask length is a multiple of the source vector length.
2993 // Check if the shuffle is some kind of concatenation of the input
2994 // vectors.
2995 unsigned NumConcat = MaskNumElts / SrcNumElts;
2996 bool IsConcat = true;
2997 SmallVector<int, 8> ConcatSrcs(NumConcat, -1);
2998 for (unsigned i = 0; i != MaskNumElts; ++i) {
2999 int Idx = Mask[i];
3000 if (Idx < 0)
3001 continue;
3002 // Ensure the indices in each SrcVT sized piece are sequential and that
3003 // the same source is used for the whole piece.
3004 if ((Idx % SrcNumElts != (i % SrcNumElts)) ||
3005 (ConcatSrcs[i / SrcNumElts] >= 0 &&
3006 ConcatSrcs[i / SrcNumElts] != (int)(Idx / SrcNumElts))) {
3007 IsConcat = false;
3008 break;
3009 }
3010 // Remember which source this index came from.
3011 ConcatSrcs[i / SrcNumElts] = Idx / SrcNumElts;
3012 }
3013
3014 // The shuffle is concatenating multiple vectors together. Just emit
3015 // a CONCAT_VECTORS operation.
3016 if (IsConcat) {
3017 SmallVector<SDValue, 8> ConcatOps;
3018 for (auto Src : ConcatSrcs) {
3019 if (Src < 0)
3020 ConcatOps.push_back(DAG.getUNDEF(SrcVT));
3021 else if (Src == 0)
3022 ConcatOps.push_back(Src1);
3023 else
3024 ConcatOps.push_back(Src2);
3025 }
3026 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, ConcatOps));
3027 return;
3028 }
3029 }
3030
3031 unsigned PaddedMaskNumElts = alignTo(MaskNumElts, SrcNumElts);
3032 unsigned NumConcat = PaddedMaskNumElts / SrcNumElts;
3033 EVT PaddedVT = EVT::getVectorVT(*DAG.getContext(), VT.getScalarType(),
3034 PaddedMaskNumElts);
3035
3036 // Pad both vectors with undefs to make them the same length as the mask.
3037 SDValue UndefVal = DAG.getUNDEF(SrcVT);
3038
3039 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
3040 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
3041 MOps1[0] = Src1;
3042 MOps2[0] = Src2;
3043
3044 Src1 = Src1.isUndef()
3045 ? DAG.getUNDEF(PaddedVT)
3046 : DAG.getNode(ISD::CONCAT_VECTORS, DL, PaddedVT, MOps1);
3047 Src2 = Src2.isUndef()
3048 ? DAG.getUNDEF(PaddedVT)
3049 : DAG.getNode(ISD::CONCAT_VECTORS, DL, PaddedVT, MOps2);
3050
3051 // Readjust mask for new input vector length.
3052 SmallVector<int, 8> MappedOps(PaddedMaskNumElts, -1);
3053 for (unsigned i = 0; i != MaskNumElts; ++i) {
3054 int Idx = Mask[i];
3055 if (Idx >= (int)SrcNumElts)
3056 Idx -= SrcNumElts - PaddedMaskNumElts;
3057 MappedOps[i] = Idx;
3058 }
3059
3060 SDValue Result = DAG.getVectorShuffle(PaddedVT, DL, Src1, Src2, MappedOps);
3061
3062 // If the concatenated vector was padded, extract a subvector with the
3063 // correct number of elements.
3064 if (MaskNumElts != PaddedMaskNumElts)
3065 Result = DAG.getNode(
3066 ISD::EXTRACT_SUBVECTOR, DL, VT, Result,
3067 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
3068
3069 setValue(&I, Result);
3070 return;
3071 }
3072
3073 if (SrcNumElts > MaskNumElts) {
3074 // Analyze the access pattern of the vector to see if we can extract
3075 // two subvectors and do the shuffle.
3076 int StartIdx[2] = { -1, -1 }; // StartIdx to extract from
3077 bool CanExtract = true;
3078 for (int Idx : Mask) {
3079 unsigned Input = 0;
3080 if (Idx < 0)
3081 continue;
3082
3083 if (Idx >= (int)SrcNumElts) {
3084 Input = 1;
3085 Idx -= SrcNumElts;
3086 }
3087
3088 // If all the indices come from the same MaskNumElts sized portion of
3089 // the sources we can use extract. Also make sure the extract wouldn't
3090 // extract past the end of the source.
3091 int NewStartIdx = alignDown(Idx, MaskNumElts);
3092 if (NewStartIdx + MaskNumElts > SrcNumElts ||
3093 (StartIdx[Input] >= 0 && StartIdx[Input] != NewStartIdx))
3094 CanExtract = false;
3095 // Make sure we always update StartIdx as we use it to track if all
3096 // elements are undef.
3097 StartIdx[Input] = NewStartIdx;
3098 }
3099
3100 if (StartIdx[0] < 0 && StartIdx[1] < 0) {
3101 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
3102 return;
3103 }
3104 if (CanExtract) {
3105 // Extract appropriate subvector and generate a vector shuffle
3106 for (unsigned Input = 0; Input < 2; ++Input) {
3107 SDValue &Src = Input == 0 ? Src1 : Src2;
3108 if (StartIdx[Input] < 0)
3109 Src = DAG.getUNDEF(VT);
3110 else {
3111 Src = DAG.getNode(
3112 ISD::EXTRACT_SUBVECTOR, DL, VT, Src,
3113 DAG.getConstant(StartIdx[Input], DL,
3114 TLI.getVectorIdxTy(DAG.getDataLayout())));
3115 }
3116 }
3117
3118 // Calculate new mask.
3119 SmallVector<int, 8> MappedOps(Mask.begin(), Mask.end());
3120 for (int &Idx : MappedOps) {
3121 if (Idx >= (int)SrcNumElts)
3122 Idx -= SrcNumElts + StartIdx[1] - MaskNumElts;
3123 else if (Idx >= 0)
3124 Idx -= StartIdx[0];
3125 }
3126
3127 setValue(&I, DAG.getVectorShuffle(VT, DL, Src1, Src2, MappedOps));
3128 return;
3129 }
3130 }
3131
3132 // We can't use either concat vectors or extract subvectors so fall back to
3133 // replacing the shuffle with extract and build vector.
3134 // to insert and build vector.
3135 EVT EltVT = VT.getVectorElementType();
3136 EVT IdxVT = TLI.getVectorIdxTy(DAG.getDataLayout());
3137 SmallVector<SDValue,8> Ops;
3138 for (int Idx : Mask) {
3139 SDValue Res;
3140
3141 if (Idx < 0) {
3142 Res = DAG.getUNDEF(EltVT);
3143 } else {
3144 SDValue &Src = Idx < (int)SrcNumElts ? Src1 : Src2;
3145 if (Idx >= (int)SrcNumElts) Idx -= SrcNumElts;
3146
3147 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
3148 EltVT, Src, DAG.getConstant(Idx, DL, IdxVT));
3149 }
3150
3151 Ops.push_back(Res);
3152 }
3153
3154 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Ops));
3155}
3156
3157void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) {
3158 const Value *Op0 = I.getOperand(0);
3159 const Value *Op1 = I.getOperand(1);
3160 Type *AggTy = I.getType();
3161 Type *ValTy = Op1->getType();
3162 bool IntoUndef = isa<UndefValue>(Op0);
3163 bool FromUndef = isa<UndefValue>(Op1);
3164
3165 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
3166
3167 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3168 SmallVector<EVT, 4> AggValueVTs;
3169 ComputeValueVTs(TLI, DAG.getDataLayout(), AggTy, AggValueVTs);
3170 SmallVector<EVT, 4> ValValueVTs;
3171 ComputeValueVTs(TLI, DAG.getDataLayout(), ValTy, ValValueVTs);
3172
3173 unsigned NumAggValues = AggValueVTs.size();
3174 unsigned NumValValues = ValValueVTs.size();
3175 SmallVector<SDValue, 4> Values(NumAggValues);
3176
3177 // Ignore an insertvalue that produces an empty object
3178 if (!NumAggValues) {
3179 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
3180 return;
3181 }
3182
3183 SDValue Agg = getValue(Op0);
3184 unsigned i = 0;
3185 // Copy the beginning value(s) from the original aggregate.
3186 for (; i != LinearIndex; ++i)
3187 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3188 SDValue(Agg.getNode(), Agg.getResNo() + i);
3189 // Copy values from the inserted value(s).
3190 if (NumValValues) {
3191 SDValue Val = getValue(Op1);
3192 for (; i != LinearIndex + NumValValues; ++i)
3193 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3194 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
3195 }
3196 // Copy remaining value(s) from the original aggregate.
3197 for (; i != NumAggValues; ++i)
3198 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3199 SDValue(Agg.getNode(), Agg.getResNo() + i);
3200
3201 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
3202 DAG.getVTList(AggValueVTs), Values));
3203}
3204
3205void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) {
3206 const Value *Op0 = I.getOperand(0);
3207 Type *AggTy = Op0->getType();
3208 Type *ValTy = I.getType();
3209 bool OutOfUndef = isa<UndefValue>(Op0);
3210
3211 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
3212
3213 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3214 SmallVector<EVT, 4> ValValueVTs;
3215 ComputeValueVTs(TLI, DAG.getDataLayout(), ValTy, ValValueVTs);
3216
3217 unsigned NumValValues = ValValueVTs.size();
3218
3219 // Ignore a extractvalue that produces an empty object
3220 if (!NumValValues) {
3221 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
3222 return;
3223 }
3224
3225 SmallVector<SDValue, 4> Values(NumValValues);
3226
3227 SDValue Agg = getValue(Op0);
3228 // Copy out the selected value(s).
3229 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
3230 Values[i - LinearIndex] =
3231 OutOfUndef ?
3232 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
3233 SDValue(Agg.getNode(), Agg.getResNo() + i);
3234
3235 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
3236 DAG.getVTList(ValValueVTs), Values));
3237}
3238
3239void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
3240 Value *Op0 = I.getOperand(0);
3241 // Note that the pointer operand may be a vector of pointers. Take the scalar
3242 // element which holds a pointer.
3243 unsigned AS = Op0->getType()->getScalarType()->getPointerAddressSpace();
3244 SDValue N = getValue(Op0);
3245 SDLoc dl = getCurSDLoc();
3246
3247 // Normalize Vector GEP - all scalar operands should be converted to the
3248 // splat vector.
3249 unsigned VectorWidth = I.getType()->isVectorTy() ?
3250 cast<VectorType>(I.getType())->getVectorNumElements() : 0;
3251
3252 if (VectorWidth && !N.getValueType().isVector()) {
3253 LLVMContext &Context = *DAG.getContext();
3254 EVT VT = EVT::getVectorVT(Context, N.getValueType(), VectorWidth);
3255 N = DAG.getSplatBuildVector(VT, dl, N);
3256 }
3257
3258 for (gep_type_iterator GTI = gep_type_begin(&I), E = gep_type_end(&I);
3259 GTI != E; ++GTI) {
3260 const Value *Idx = GTI.getOperand();
3261 if (StructType *StTy = GTI.getStructTypeOrNull()) {
3262 unsigned Field = cast<Constant>(Idx)->getUniqueInteger().getZExtValue();
3263 if (Field) {
3264 // N = N + Offset
3265 uint64_t Offset = DL->getStructLayout(StTy)->getElementOffset(Field);
3266
3267 // In an inbounds GEP with an offset that is nonnegative even when
3268 // interpreted as signed, assume there is no unsigned overflow.
3269 SDNodeFlags Flags;
3270 if (int64_t(Offset) >= 0 && cast<GEPOperator>(I).isInBounds())
3271 Flags.setNoUnsignedWrap(true);
3272
3273 N = DAG.getNode(ISD::ADD, dl, N.getValueType(), N,
3274 DAG.getConstant(Offset, dl, N.getValueType()), &Flags);
3275 }
3276 } else {
3277 MVT PtrTy =
3278 DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout(), AS);
3279 unsigned PtrSize = PtrTy.getSizeInBits();
3280 APInt ElementSize(PtrSize, DL->getTypeAllocSize(GTI.getIndexedType()));
3281
3282 // If this is a scalar constant or a splat vector of constants,
3283 // handle it quickly.
3284 const auto *CI = dyn_cast<ConstantInt>(Idx);
3285 if (!CI && isa<ConstantDataVector>(Idx) &&
3286 cast<ConstantDataVector>(Idx)->getSplatValue())
3287 CI = cast<ConstantInt>(cast<ConstantDataVector>(Idx)->getSplatValue());
3288
3289 if (CI) {
3290 if (CI->isZero())
3291 continue;
3292 APInt Offs = ElementSize * CI->getValue().sextOrTrunc(PtrSize);
3293 LLVMContext &Context = *DAG.getContext();
3294 SDValue OffsVal = VectorWidth ?
3295 DAG.getConstant(Offs, dl, EVT::getVectorVT(Context, PtrTy, VectorWidth)) :
3296 DAG.getConstant(Offs, dl, PtrTy);
3297
3298 // In an inbouds GEP with an offset that is nonnegative even when
3299 // interpreted as signed, assume there is no unsigned overflow.
3300 SDNodeFlags Flags;
3301 if (Offs.isNonNegative() && cast<GEPOperator>(I).isInBounds())
3302 Flags.setNoUnsignedWrap(true);
3303
3304 N = DAG.getNode(ISD::ADD, dl, N.getValueType(), N, OffsVal, &Flags);
3305 continue;
3306 }
3307
3308 // N = N + Idx * ElementSize;
3309 SDValue IdxN = getValue(Idx);
3310
3311 if (!IdxN.getValueType().isVector() && VectorWidth) {
3312 MVT VT = MVT::getVectorVT(IdxN.getValueType().getSimpleVT(), VectorWidth);
3313 IdxN = DAG.getSplatBuildVector(VT, dl, IdxN);
3314 }
3315
3316 // If the index is smaller or larger than intptr_t, truncate or extend
3317 // it.
3318 IdxN = DAG.getSExtOrTrunc(IdxN, dl, N.getValueType());
3319
3320 // If this is a multiply by a power of two, turn it into a shl
3321 // immediately. This is a very common case.
3322 if (ElementSize != 1) {
3323 if (ElementSize.isPowerOf2()) {
3324 unsigned Amt = ElementSize.logBase2();
3325 IdxN = DAG.getNode(ISD::SHL, dl,
3326 N.getValueType(), IdxN,
3327 DAG.getConstant(Amt, dl, IdxN.getValueType()));
3328 } else {
3329 SDValue Scale = DAG.getConstant(ElementSize, dl, IdxN.getValueType());
3330 IdxN = DAG.getNode(ISD::MUL, dl,
3331 N.getValueType(), IdxN, Scale);
3332 }
3333 }
3334
3335 N = DAG.getNode(ISD::ADD, dl,
3336 N.getValueType(), N, IdxN);
3337 }
3338 }
3339
3340 setValue(&I, N);
3341}
3342
3343void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
3344 // If this is a fixed sized alloca in the entry block of the function,
3345 // allocate it statically on the stack.
3346 if (FuncInfo.StaticAllocaMap.count(&I))
3347 return; // getValue will auto-populate this.
3348
3349 SDLoc dl = getCurSDLoc();
3350 Type *Ty = I.getAllocatedType();
3351 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3352 auto &DL = DAG.getDataLayout();
3353 uint64_t TySize = DL.getTypeAllocSize(Ty);
3354 unsigned Align =
3355 std::max((unsigned)DL.getPrefTypeAlignment(Ty), I.getAlignment());
3356
3357 SDValue AllocSize = getValue(I.getArraySize());
3358
3359 EVT IntPtr = TLI.getPointerTy(DAG.getDataLayout());
3360 if (AllocSize.getValueType() != IntPtr)
3361 AllocSize = DAG.getZExtOrTrunc(AllocSize, dl, IntPtr);
3362
3363 AllocSize = DAG.getNode(ISD::MUL, dl, IntPtr,
3364 AllocSize,
3365 DAG.getConstant(TySize, dl, IntPtr));
3366
3367 // Handle alignment. If the requested alignment is less than or equal to
3368 // the stack alignment, ignore it. If the size is greater than or equal to
3369 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
3370 unsigned StackAlign =
3371 DAG.getSubtarget().getFrameLowering()->getStackAlignment();
3372 if (Align <= StackAlign)
3373 Align = 0;
3374
3375 // Round the size of the allocation up to the stack alignment size
3376 // by add SA-1 to the size. This doesn't overflow because we're computing
3377 // an address inside an alloca.
3378 SDNodeFlags Flags;
3379 Flags.setNoUnsignedWrap(true);
3380 AllocSize = DAG.getNode(ISD::ADD, dl,
3381 AllocSize.getValueType(), AllocSize,
3382 DAG.getIntPtrConstant(StackAlign - 1, dl), &Flags);
3383
3384 // Mask out the low bits for alignment purposes.
3385 AllocSize = DAG.getNode(ISD::AND, dl,
3386 AllocSize.getValueType(), AllocSize,
3387 DAG.getIntPtrConstant(~(uint64_t)(StackAlign - 1),
3388 dl));
3389
3390 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align, dl) };
3391 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
3392 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, dl, VTs, Ops);
3393 setValue(&I, DSA);
3394 DAG.setRoot(DSA.getValue(1));
3395
3396 assert(FuncInfo.MF->getFrameInfo().hasVarSizedObjects())((FuncInfo.MF->getFrameInfo().hasVarSizedObjects()) ? static_cast
<void> (0) : __assert_fail ("FuncInfo.MF->getFrameInfo().hasVarSizedObjects()"
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 3396, __PRETTY_FUNCTION__))
;
3397}
3398
3399void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
3400 if (I.isAtomic())
3401 return visitAtomicLoad(I);
3402
3403 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3404 const Value *SV = I.getOperand(0);
3405 if (TLI.supportSwiftError()) {
3406 // Swifterror values can come from either a function parameter with
3407 // swifterror attribute or an alloca with swifterror attribute.
3408 if (const Argument *Arg = dyn_cast<Argument>(SV)) {
3409 if (Arg->hasSwiftErrorAttr())
3410 return visitLoadFromSwiftError(I);
3411 }
3412
3413 if (const AllocaInst *Alloca = dyn_cast<AllocaInst>(SV)) {
3414 if (Alloca->isSwiftError())
3415 return visitLoadFromSwiftError(I);
3416 }
3417 }
3418
3419 SDValue Ptr = getValue(SV);
3420
3421 Type *Ty = I.getType();
3422
3423 bool isVolatile = I.isVolatile();
3424 bool isNonTemporal = I.getMetadata(LLVMContext::MD_nontemporal) != nullptr;
3425 bool isInvariant = I.getMetadata(LLVMContext::MD_invariant_load) != nullptr;
3426 bool isDereferenceable = isDereferenceablePointer(SV, DAG.getDataLayout());
3427 unsigned Alignment = I.getAlignment();
3428
3429 AAMDNodes AAInfo;
3430 I.getAAMetadata(AAInfo);
3431 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3432
3433 SmallVector<EVT, 4> ValueVTs;
3434 SmallVector<uint64_t, 4> Offsets;
3435 ComputeValueVTs(TLI, DAG.getDataLayout(), Ty, ValueVTs, &Offsets);
3436 unsigned NumValues = ValueVTs.size();
3437 if (NumValues == 0)
3438 return;
3439
3440 SDValue Root;
3441 bool ConstantMemory = false;
3442 if (isVolatile || NumValues > MaxParallelChains)
3443 // Serialize volatile loads with other side effects.
3444 Root = getRoot();
3445 else if (AA->pointsToConstantMemory(MemoryLocation(
3446 SV, DAG.getDataLayout().getTypeStoreSize(Ty), AAInfo))) {
3447 // Do not serialize (non-volatile) loads of constant memory with anything.
3448 Root = DAG.getEntryNode();
3449 ConstantMemory = true;
3450 } else {
3451 // Do not serialize non-volatile loads against each other.
3452 Root = DAG.getRoot();
3453 }
3454
3455 SDLoc dl = getCurSDLoc();
3456
3457 if (isVolatile)
3458 Root = TLI.prepareVolatileOrAtomicLoad(Root, dl, DAG);
3459
3460 // An aggregate load cannot wrap around the address space, so offsets to its
3461 // parts don't wrap either.
3462 SDNodeFlags Flags;
3463 Flags.setNoUnsignedWrap(true);
3464
3465 SmallVector<SDValue, 4> Values(NumValues);
3466 SmallVector<SDValue, 4> Chains(std::min(MaxParallelChains, NumValues));
3467 EVT PtrVT = Ptr.getValueType();
3468 unsigned ChainI = 0;
3469 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3470 // Serializing loads here may result in excessive register pressure, and
3471 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling
3472 // could recover a bit by hoisting nodes upward in the chain by recognizing
3473 // they are side-effect free or do not alias. The optimizer should really
3474 // avoid this case by converting large object/array copies to llvm.memcpy
3475 // (MaxParallelChains should always remain as failsafe).
3476 if (ChainI == MaxParallelChains) {
3477 assert(PendingLoads.empty() && "PendingLoads must be serialized first")((PendingLoads.empty() && "PendingLoads must be serialized first"
) ? static_cast<void> (0) : __assert_fail ("PendingLoads.empty() && \"PendingLoads must be serialized first\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 3477, __PRETTY_FUNCTION__))
;
3478 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3479 makeArrayRef(Chains.data(), ChainI));
3480 Root = Chain;
3481 ChainI = 0;
3482 }
3483 SDValue A = DAG.getNode(ISD::ADD, dl,
3484 PtrVT, Ptr,
3485 DAG.getConstant(Offsets[i], dl, PtrVT),
3486 &Flags);
3487 auto MMOFlags = MachineMemOperand::MONone;
3488 if (isVolatile)
3489 MMOFlags |= MachineMemOperand::MOVolatile;
3490 if (isNonTemporal)
3491 MMOFlags |= MachineMemOperand::MONonTemporal;
3492 if (isInvariant)
3493 MMOFlags |= MachineMemOperand::MOInvariant;
3494 if (isDereferenceable)
3495 MMOFlags |= MachineMemOperand::MODereferenceable;
3496
3497 SDValue L = DAG.getLoad(ValueVTs[i], dl, Root, A,
3498 MachinePointerInfo(SV, Offsets[i]), Alignment,
3499 MMOFlags, AAInfo, Ranges);
3500
3501 Values[i] = L;
3502 Chains[ChainI] = L.getValue(1);
3503 }
3504
3505 if (!ConstantMemory) {
3506 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3507 makeArrayRef(Chains.data(), ChainI));
3508 if (isVolatile)
3509 DAG.setRoot(Chain);
3510 else
3511 PendingLoads.push_back(Chain);
3512 }
3513
3514 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, dl,
3515 DAG.getVTList(ValueVTs), Values));
3516}
3517
3518void SelectionDAGBuilder::visitStoreToSwiftError(const StoreInst &I) {
3519 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3520 assert(TLI.supportSwiftError() &&((TLI.supportSwiftError() && "call visitStoreToSwiftError when backend supports swifterror"
) ? static_cast<void> (0) : __assert_fail ("TLI.supportSwiftError() && \"call visitStoreToSwiftError when backend supports swifterror\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 3521, __PRETTY_FUNCTION__))
3521 "call visitStoreToSwiftError when backend supports swifterror")((TLI.supportSwiftError() && "call visitStoreToSwiftError when backend supports swifterror"
) ? static_cast<void> (0) : __assert_fail ("TLI.supportSwiftError() && \"call visitStoreToSwiftError when backend supports swifterror\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 3521, __PRETTY_FUNCTION__))
;
3522
3523 SmallVector<EVT, 4> ValueVTs;
3524 SmallVector<uint64_t, 4> Offsets;
3525 const Value *SrcV = I.getOperand(0);
3526 ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(),
3527 SrcV->getType(), ValueVTs, &Offsets);
3528 assert(ValueVTs.size() == 1 && Offsets[0] == 0 &&((ValueVTs.size() == 1 && Offsets[0] == 0 && "expect a single EVT for swifterror"
) ? static_cast<void> (0) : __assert_fail ("ValueVTs.size() == 1 && Offsets[0] == 0 && \"expect a single EVT for swifterror\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 3529, __PRETTY_FUNCTION__))
3529 "expect a single EVT for swifterror")((ValueVTs.size() == 1 && Offsets[0] == 0 && "expect a single EVT for swifterror"
) ? static_cast<void> (0) : __assert_fail ("ValueVTs.size() == 1 && Offsets[0] == 0 && \"expect a single EVT for swifterror\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 3529, __PRETTY_FUNCTION__))
;
3530
3531 SDValue Src = getValue(SrcV);
3532 // Create a virtual register, then update the virtual register.
3533 auto &DL = DAG.getDataLayout();
3534 const TargetRegisterClass *RC = TLI.getRegClassFor(TLI.getPointerTy(DL));
3535 unsigned VReg = FuncInfo.MF->getRegInfo().createVirtualRegister(RC);
3536 // Chain, DL, Reg, N or Chain, DL, Reg, N, Glue
3537 // Chain can be getRoot or getControlRoot.
3538 SDValue CopyNode = DAG.getCopyToReg(getRoot(), getCurSDLoc(), VReg,
3539 SDValue(Src.getNode(), Src.getResNo()));
3540 DAG.setRoot(CopyNode);
3541 FuncInfo.setCurrentSwiftErrorVReg(FuncInfo.MBB, I.getOperand(1), VReg);
3542}
3543
3544void SelectionDAGBuilder::visitLoadFromSwiftError(const LoadInst &I) {
3545 assert(DAG.getTargetLoweringInfo().supportSwiftError() &&((DAG.getTargetLoweringInfo().supportSwiftError() && "call visitLoadFromSwiftError when backend supports swifterror"
) ? static_cast<void> (0) : __assert_fail ("DAG.getTargetLoweringInfo().supportSwiftError() && \"call visitLoadFromSwiftError when backend supports swifterror\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 3546, __PRETTY_FUNCTION__))
3546 "call visitLoadFromSwiftError when backend supports swifterror")((DAG.getTargetLoweringInfo().supportSwiftError() && "call visitLoadFromSwiftError when backend supports swifterror"
) ? static_cast<void> (0) : __assert_fail ("DAG.getTargetLoweringInfo().supportSwiftError() && \"call visitLoadFromSwiftError when backend supports swifterror\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 3546, __PRETTY_FUNCTION__))
;
3547
3548 assert(!I.isVolatile() &&((!I.isVolatile() && I.getMetadata(LLVMContext::MD_nontemporal
) == nullptr && I.getMetadata(LLVMContext::MD_invariant_load
) == nullptr && "Support volatile, non temporal, invariant for load_from_swift_error"
) ? static_cast<void> (0) : __assert_fail ("!I.isVolatile() && I.getMetadata(LLVMContext::MD_nontemporal) == nullptr && I.getMetadata(LLVMContext::MD_invariant_load) == nullptr && \"Support volatile, non temporal, invariant for load_from_swift_error\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 3551, __PRETTY_FUNCTION__))
3549 I.getMetadata(LLVMContext::MD_nontemporal) == nullptr &&((!I.isVolatile() && I.getMetadata(LLVMContext::MD_nontemporal
) == nullptr && I.getMetadata(LLVMContext::MD_invariant_load
) == nullptr && "Support volatile, non temporal, invariant for load_from_swift_error"
) ? static_cast<void> (0) : __assert_fail ("!I.isVolatile() && I.getMetadata(LLVMContext::MD_nontemporal) == nullptr && I.getMetadata(LLVMContext::MD_invariant_load) == nullptr && \"Support volatile, non temporal, invariant for load_from_swift_error\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 3551, __PRETTY_FUNCTION__))
3550 I.getMetadata(LLVMContext::MD_invariant_load) == nullptr &&((!I.isVolatile() && I.getMetadata(LLVMContext::MD_nontemporal
) == nullptr && I.getMetadata(LLVMContext::MD_invariant_load
) == nullptr && "Support volatile, non temporal, invariant for load_from_swift_error"
) ? static_cast<void> (0) : __assert_fail ("!I.isVolatile() && I.getMetadata(LLVMContext::MD_nontemporal) == nullptr && I.getMetadata(LLVMContext::MD_invariant_load) == nullptr && \"Support volatile, non temporal, invariant for load_from_swift_error\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 3551, __PRETTY_FUNCTION__))
3551 "Support volatile, non temporal, invariant for load_from_swift_error")((!I.isVolatile() && I.getMetadata(LLVMContext::MD_nontemporal
) == nullptr && I.getMetadata(LLVMContext::MD_invariant_load
) == nullptr && "Support volatile, non temporal, invariant for load_from_swift_error"
) ? static_cast<void> (0) : __assert_fail ("!I.isVolatile() && I.getMetadata(LLVMContext::MD_nontemporal) == nullptr && I.getMetadata(LLVMContext::MD_invariant_load) == nullptr && \"Support volatile, non temporal, invariant for load_from_swift_error\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 3551, __PRETTY_FUNCTION__))
;
3552
3553 const Value *SV = I.getOperand(0);
3554 Type *Ty = I.getType();
3555 AAMDNodes AAInfo;
3556 I.getAAMetadata(AAInfo);
3557 assert(!AA->pointsToConstantMemory(MemoryLocation(((!AA->pointsToConstantMemory(MemoryLocation( SV, DAG.getDataLayout
().getTypeStoreSize(Ty), AAInfo)) && "load_from_swift_error should not be constant memory"
) ? static_cast<void> (0) : __assert_fail ("!AA->pointsToConstantMemory(MemoryLocation( SV, DAG.getDataLayout().getTypeStoreSize(Ty), AAInfo)) && \"load_from_swift_error should not be constant memory\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 3559, __PRETTY_FUNCTION__))
3558 SV, DAG.getDataLayout().getTypeStoreSize(Ty), AAInfo)) &&((!AA->pointsToConstantMemory(MemoryLocation( SV, DAG.getDataLayout
().getTypeStoreSize(Ty), AAInfo)) && "load_from_swift_error should not be constant memory"
) ? static_cast<void> (0) : __assert_fail ("!AA->pointsToConstantMemory(MemoryLocation( SV, DAG.getDataLayout().getTypeStoreSize(Ty), AAInfo)) && \"load_from_swift_error should not be constant memory\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 3559, __PRETTY_FUNCTION__))
3559 "load_from_swift_error should not be constant memory")((!AA->pointsToConstantMemory(MemoryLocation( SV, DAG.getDataLayout
().getTypeStoreSize(Ty), AAInfo)) && "load_from_swift_error should not be constant memory"
) ? static_cast<void> (0) : __assert_fail ("!AA->pointsToConstantMemory(MemoryLocation( SV, DAG.getDataLayout().getTypeStoreSize(Ty), AAInfo)) && \"load_from_swift_error should not be constant memory\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 3559, __PRETTY_FUNCTION__))
;
3560
3561 SmallVector<EVT, 4> ValueVTs;
3562 SmallVector<uint64_t, 4> Offsets;
3563 ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(), Ty,
3564 ValueVTs, &Offsets);
3565 assert(ValueVTs.size() == 1 && Offsets[0] == 0 &&((ValueVTs.size() == 1 && Offsets[0] == 0 && "expect a single EVT for swifterror"
) ? static_cast<void> (0) : __assert_fail ("ValueVTs.size() == 1 && Offsets[0] == 0 && \"expect a single EVT for swifterror\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 3566, __PRETTY_FUNCTION__))
3566 "expect a single EVT for swifterror")((ValueVTs.size() == 1 && Offsets[0] == 0 && "expect a single EVT for swifterror"
) ? static_cast<void> (0) : __assert_fail ("ValueVTs.size() == 1 && Offsets[0] == 0 && \"expect a single EVT for swifterror\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 3566, __PRETTY_FUNCTION__))
;
3567
3568 // Chain, DL, Reg, VT, Glue or Chain, DL, Reg, VT
3569 SDValue L = DAG.getCopyFromReg(
3570 getRoot(), getCurSDLoc(),
3571 FuncInfo.getOrCreateSwiftErrorVReg(FuncInfo.MBB, SV), ValueVTs[0]);
3572
3573 setValue(&I, L);
3574}
3575
3576void SelectionDAGBuilder::visitStore(const StoreInst &I) {
3577 if (I.isAtomic())
3578 return visitAtomicStore(I);
3579
3580 const Value *SrcV = I.getOperand(0);
3581 const Value *PtrV = I.getOperand(1);
3582
3583 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3584 if (TLI.supportSwiftError()) {
3585 // Swifterror values can come from either a function parameter with
3586 // swifterror attribute or an alloca with swifterror attribute.
3587 if (const Argument *Arg = dyn_cast<Argument>(PtrV)) {
3588 if (Arg->hasSwiftErrorAttr())
3589 return visitStoreToSwiftError(I);
3590 }
3591
3592 if (const AllocaInst *Alloca = dyn_cast<AllocaInst>(PtrV)) {
3593 if (Alloca->isSwiftError())
3594 return visitStoreToSwiftError(I);
3595 }
3596 }
3597
3598 SmallVector<EVT, 4> ValueVTs;
3599 SmallVector<uint64_t, 4> Offsets;
3600 ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(),
3601 SrcV->getType(), ValueVTs, &Offsets);
3602 unsigned NumValues = ValueVTs.size();
3603 if (NumValues == 0)
3604 return;
3605
3606 // Get the lowered operands. Note that we do this after
3607 // checking if NumResults is zero, because with zero results
3608 // the operands won't have values in the map.
3609 SDValue Src = getValue(SrcV);
3610 SDValue Ptr = getValue(PtrV);
3611
3612 SDValue Root = getRoot();
3613 SmallVector<SDValue, 4> Chains(std::min(MaxParallelChains, NumValues));
3614 SDLoc dl = getCurSDLoc();
3615 EVT PtrVT = Ptr.getValueType();
3616 unsigned Alignment = I.getAlignment();
3617 AAMDNodes AAInfo;
3618 I.getAAMetadata(AAInfo);
3619
3620 auto MMOFlags = MachineMemOperand::MONone;
3621 if (I.isVolatile())
3622 MMOFlags |= MachineMemOperand::MOVolatile;
3623 if (I.getMetadata(LLVMContext::MD_nontemporal) != nullptr)
3624 MMOFlags |= MachineMemOperand::MONonTemporal;
3625
3626 // An aggregate load cannot wrap around the address space, so offsets to its
3627 // parts don't wrap either.
3628 SDNodeFlags Flags;
3629 Flags.setNoUnsignedWrap(true);
3630
3631 unsigned ChainI = 0;
3632 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3633 // See visitLoad comments.
3634 if (ChainI == MaxParallelChains) {
3635 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3636 makeArrayRef(Chains.data(), ChainI));
3637 Root = Chain;
3638 ChainI = 0;
3639 }
3640 SDValue Add = DAG.getNode(ISD::ADD, dl, PtrVT, Ptr,
3641 DAG.getConstant(Offsets[i], dl, PtrVT), &Flags);
3642 SDValue St = DAG.getStore(
3643 Root, dl, SDValue(Src.getNode(), Src.getResNo() + i), Add,
3644 MachinePointerInfo(PtrV, Offsets[i]), Alignment, MMOFlags, AAInfo);
3645 Chains[ChainI] = St;
3646 }
3647
3648 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3649 makeArrayRef(Chains.data(), ChainI));
3650 DAG.setRoot(StoreNode);
3651}
3652
3653void SelectionDAGBuilder::visitMaskedStore(const CallInst &I,
3654 bool IsCompressing) {
3655 SDLoc sdl = getCurSDLoc();
3656
3657 auto getMaskedStoreOps = [&](Value* &Ptr, Value* &Mask, Value* &Src0,
3658 unsigned& Alignment) {
3659 // llvm.masked.store.*(Src0, Ptr, alignment, Mask)
3660 Src0 = I.getArgOperand(0);
3661 Ptr = I.getArgOperand(1);
3662 Alignment = cast<ConstantInt>(I.getArgOperand(2))->getZExtValue();
3663 Mask = I.getArgOperand(3);
3664 };
3665 auto getCompressingStoreOps = [&](Value* &Ptr, Value* &Mask, Value* &Src0,
3666 unsigned& Alignment) {
3667 // llvm.masked.compressstore.*(Src0, Ptr, Mask)
3668 Src0 = I.getArgOperand(0);
3669 Ptr = I.getArgOperand(1);
3670 Mask = I.getArgOperand(2);
3671 Alignment = 0;
3672 };
3673
3674 Value *PtrOperand, *MaskOperand, *Src0Operand;
3675 unsigned Alignment;
3676 if (IsCompressing)
3677 getCompressingStoreOps(PtrOperand, MaskOperand, Src0Operand, Alignment);
3678 else
3679 getMaskedStoreOps(PtrOperand, MaskOperand, Src0Operand, Alignment);
3680
3681 SDValue Ptr = getValue(PtrOperand);
3682 SDValue Src0 = getValue(Src0Operand);
3683 SDValue Mask = getValue(MaskOperand);
3684
3685 EVT VT = Src0.getValueType();
3686 if (!Alignment)
3687 Alignment = DAG.getEVTAlignment(VT);
3688
3689 AAMDNodes AAInfo;
3690 I.getAAMetadata(AAInfo);
3691
3692 MachineMemOperand *MMO =
3693 DAG.getMachineFunction().
3694 getMachineMemOperand(MachinePointerInfo(PtrOperand),
3695 MachineMemOperand::MOStore, VT.getStoreSize(),
3696 Alignment, AAInfo);
3697 SDValue StoreNode = DAG.getMaskedStore(getRoot(), sdl, Src0, Ptr, Mask, VT,
3698 MMO, false /* Truncating */,
3699 IsCompressing);
3700 DAG.setRoot(StoreNode);
3701 setValue(&I, StoreNode);
3702}
3703
3704// Get a uniform base for the Gather/Scatter intrinsic.
3705// The first argument of the Gather/Scatter intrinsic is a vector of pointers.
3706// We try to represent it as a base pointer + vector of indices.
3707// Usually, the vector of pointers comes from a 'getelementptr' instruction.
3708// The first operand of the GEP may be a single pointer or a vector of pointers
3709// Example:
3710// %gep.ptr = getelementptr i32, <8 x i32*> %vptr, <8 x i32> %ind
3711// or
3712// %gep.ptr = getelementptr i32, i32* %ptr, <8 x i32> %ind
3713// %res = call <8 x i32> @llvm.masked.gather.v8i32(<8 x i32*> %gep.ptr, ..
3714//
3715// When the first GEP operand is a single pointer - it is the uniform base we
3716// are looking for. If first operand of the GEP is a splat vector - we
3717// extract the spalt value and use it as a uniform base.
3718// In all other cases the function returns 'false'.
3719//
3720static bool getUniformBase(const Value* &Ptr, SDValue& Base, SDValue& Index,
3721 SelectionDAGBuilder* SDB) {
3722
3723 SelectionDAG& DAG = SDB->DAG;
3724 LLVMContext &Context = *DAG.getContext();
3725
3726 assert(Ptr->getType()->isVectorTy() && "Uexpected pointer type")((Ptr->getType()->isVectorTy() && "Uexpected pointer type"
) ? static_cast<void> (0) : __assert_fail ("Ptr->getType()->isVectorTy() && \"Uexpected pointer type\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 3726, __PRETTY_FUNCTION__))
;
3727 const GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(Ptr);
3728 if (!GEP || GEP->getNumOperands() > 2)
3729 return false;
3730
3731 const Value *GEPPtr = GEP->getPointerOperand();
3732 if (!GEPPtr->getType()->isVectorTy())
3733 Ptr = GEPPtr;
3734 else if (!(Ptr = getSplatValue(GEPPtr)))
3735 return false;
3736
3737 Value *IndexVal = GEP->getOperand(1);
3738
3739 // The operands of the GEP may be defined in another basic block.
3740 // In this case we'll not find nodes for the operands.
3741 if (!SDB->findValue(Ptr) || !SDB->findValue(IndexVal))
3742 return false;
3743
3744 Base = SDB->getValue(Ptr);
3745 Index = SDB->getValue(IndexVal);
3746
3747 // Suppress sign extension.
3748 if (SExtInst* Sext = dyn_cast<SExtInst>(IndexVal)) {
3749 if (SDB->findValue(Sext->getOperand(0))) {
3750 IndexVal = Sext->getOperand(0);
3751 Index = SDB->getValue(IndexVal);
3752 }
3753 }
3754 if (!Index.getValueType().isVector()) {
3755 unsigned GEPWidth = GEP->getType()->getVectorNumElements();
3756 EVT VT = EVT::getVectorVT(Context, Index.getValueType(), GEPWidth);
3757 Index = DAG.getSplatBuildVector(VT, SDLoc(Index), Index);
3758 }
3759 return true;
3760}
3761
3762void SelectionDAGBuilder::visitMaskedScatter(const CallInst &I) {
3763 SDLoc sdl = getCurSDLoc();
3764
3765 // llvm.masked.scatter.*(Src0, Ptrs, alignemt, Mask)
3766 const Value *Ptr = I.getArgOperand(1);
3767 SDValue Src0 = getValue(I.getArgOperand(0));
3768 SDValue Mask = getValue(I.getArgOperand(3));
3769 EVT VT = Src0.getValueType();
3770 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(2)))->getZExtValue();
3771 if (!Alignment)
3772 Alignment = DAG.getEVTAlignment(VT);
3773 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3774
3775 AAMDNodes AAInfo;
3776 I.getAAMetadata(AAInfo);
3777
3778 SDValue Base;
3779 SDValue Index;
3780 const Value *BasePtr = Ptr;
3781 bool UniformBase = getUniformBase(BasePtr, Base, Index, this);
3782
3783 const Value *MemOpBasePtr = UniformBase ? BasePtr : nullptr;
3784 MachineMemOperand *MMO = DAG.getMachineFunction().
3785 getMachineMemOperand(MachinePointerInfo(MemOpBasePtr),
3786 MachineMemOperand::MOStore, VT.getStoreSize(),
3787 Alignment, AAInfo);
3788 if (!UniformBase) {
3789 Base = DAG.getTargetConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout()));
3790 Index = getValue(Ptr);
3791 }
3792 SDValue Ops[] = { getRoot(), Src0, Mask, Base, Index };
3793 SDValue Scatter = DAG.getMaskedScatter(DAG.getVTList(MVT::Other), VT, sdl,
3794 Ops, MMO);
3795 DAG.setRoot(Scatter);
3796 setValue(&I, Scatter);
3797}
3798
3799void SelectionDAGBuilder::visitMaskedLoad(const CallInst &I, bool IsExpanding) {
3800 SDLoc sdl = getCurSDLoc();
3801
3802 auto getMaskedLoadOps = [&](Value* &Ptr, Value* &Mask, Value* &Src0,
3803 unsigned& Alignment) {
3804 // @llvm.masked.load.*(Ptr, alignment, Mask, Src0)
3805 Ptr = I.getArgOperand(0);
3806 Alignment = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
3807 Mask = I.getArgOperand(2);
3808 Src0 = I.getArgOperand(3);
3809 };
3810 auto getExpandingLoadOps = [&](Value* &Ptr, Value* &Mask, Value* &Src0,
3811 unsigned& Alignment) {
3812 // @llvm.masked.expandload.*(Ptr, Mask, Src0)
3813 Ptr = I.getArgOperand(0);
3814 Alignment = 0;
3815 Mask = I.getArgOperand(1);
3816 Src0 = I.getArgOperand(2);
3817 };
3818
3819 Value *PtrOperand, *MaskOperand, *Src0Operand;
3820 unsigned Alignment;
3821 if (IsExpanding)
3822 getExpandingLoadOps(PtrOperand, MaskOperand, Src0Operand, Alignment);
3823 else
3824 getMaskedLoadOps(PtrOperand, MaskOperand, Src0Operand, Alignment);
3825
3826 SDValue Ptr = getValue(PtrOperand);
3827 SDValue Src0 = getValue(Src0Operand);
3828 SDValue Mask = getValue(MaskOperand);
3829
3830 EVT VT = Src0.getValueType();
3831 if (!Alignment)
3832 Alignment = DAG.getEVTAlignment(VT);
3833
3834 AAMDNodes AAInfo;
3835 I.getAAMetadata(AAInfo);
3836 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3837
3838 // Do not serialize masked loads of constant memory with anything.
3839 bool AddToChain = !AA->pointsToConstantMemory(MemoryLocation(
3840 PtrOperand, DAG.getDataLayout().getTypeStoreSize(I.getType()), AAInfo));
3841 SDValue InChain = AddToChain ? DAG.getRoot() : DAG.getEntryNode();
3842
3843 MachineMemOperand *MMO =
3844 DAG.getMachineFunction().
3845 getMachineMemOperand(MachinePointerInfo(PtrOperand),
3846 MachineMemOperand::MOLoad, VT.getStoreSize(),
3847 Alignment, AAInfo, Ranges);
3848
3849 SDValue Load = DAG.getMaskedLoad(VT, sdl, InChain, Ptr, Mask, Src0, VT, MMO,
3850 ISD::NON_EXTLOAD, IsExpanding);
3851 if (AddToChain) {
3852 SDValue OutChain = Load.getValue(1);
3853 DAG.setRoot(OutChain);
3854 }
3855 setValue(&I, Load);
3856}
3857
3858void SelectionDAGBuilder::visitMaskedGather(const CallInst &I) {
3859 SDLoc sdl = getCurSDLoc();
3860
3861 // @llvm.masked.gather.*(Ptrs, alignment, Mask, Src0)
3862 const Value *Ptr = I.getArgOperand(0);
3863 SDValue Src0 = getValue(I.getArgOperand(3));
3864 SDValue Mask = getValue(I.getArgOperand(2));
3865
3866 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3867 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
3868 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(1)))->getZExtValue();
3869 if (!Alignment)
3870 Alignment = DAG.getEVTAlignment(VT);
3871
3872 AAMDNodes AAInfo;
3873 I.getAAMetadata(AAInfo);
3874 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3875
3876 SDValue Root = DAG.getRoot();
3877 SDValue Base;
3878 SDValue Index;
3879 const Value *BasePtr = Ptr;
3880 bool UniformBase = getUniformBase(BasePtr, Base, Index, this);
3881 bool ConstantMemory = false;
3882 if (UniformBase &&
3883 AA->pointsToConstantMemory(MemoryLocation(
3884 BasePtr, DAG.getDataLayout().getTypeStoreSize(I.getType()),
3885 AAInfo))) {
3886 // Do not serialize (non-volatile) loads of constant memory with anything.
3887 Root = DAG.getEntryNode();
3888 ConstantMemory = true;
3889 }
3890
3891 MachineMemOperand *MMO =
3892 DAG.getMachineFunction().
3893 getMachineMemOperand(MachinePointerInfo(UniformBase ? BasePtr : nullptr),
3894 MachineMemOperand::MOLoad, VT.getStoreSize(),
3895 Alignment, AAInfo, Ranges);
3896
3897 if (!UniformBase) {
3898 Base = DAG.getTargetConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout()));
3899 Index = getValue(Ptr);
3900 }
3901 SDValue Ops[] = { Root, Src0, Mask, Base, Index };
3902 SDValue Gather = DAG.getMaskedGather(DAG.getVTList(VT, MVT::Other), VT, sdl,
3903 Ops, MMO);
3904
3905 SDValue OutChain = Gather.getValue(1);
3906 if (!ConstantMemory)
3907 PendingLoads.push_back(OutChain);
3908 setValue(&I, Gather);
3909}
3910
3911void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) {
3912 SDLoc dl = getCurSDLoc();
3913 AtomicOrdering SuccessOrder = I.getSuccessOrdering();
3914 AtomicOrdering FailureOrder = I.getFailureOrdering();
3915 SynchronizationScope Scope = I.getSynchScope();
3916
3917 SDValue InChain = getRoot();
3918
3919 MVT MemVT = getValue(I.getCompareOperand()).getSimpleValueType();
3920 SDVTList VTs = DAG.getVTList(MemVT, MVT::i1, MVT::Other);
3921 SDValue L = DAG.getAtomicCmpSwap(
3922 ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl, MemVT, VTs, InChain,
3923 getValue(I.getPointerOperand()), getValue(I.getCompareOperand()),
3924 getValue(I.getNewValOperand()), MachinePointerInfo(I.getPointerOperand()),
3925 /*Alignment=*/ 0, SuccessOrder, FailureOrder, Scope);
3926
3927 SDValue OutChain = L.getValue(2);
3928
3929 setValue(&I, L);
3930 DAG.setRoot(OutChain);
3931}
3932
3933void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) {
3934 SDLoc dl = getCurSDLoc();
3935 ISD::NodeType NT;
3936 switch (I.getOperation()) {
3937 default: llvm_unreachable("Unknown atomicrmw operation")::llvm::llvm_unreachable_internal("Unknown atomicrmw operation"
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 3937)
;
3938 case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break;
3939 case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break;
3940 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break;
3941 case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break;
3942 case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break;
3943 case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break;
3944 case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break;
3945 case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break;
3946 case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break;
3947 case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break;
3948 case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break;
3949 }
3950 AtomicOrdering Order = I.getOrdering();
3951 SynchronizationScope Scope = I.getSynchScope();
3952
3953 SDValue InChain = getRoot();
3954
3955 SDValue L =
3956 DAG.getAtomic(NT, dl,
3957 getValue(I.getValOperand()).getSimpleValueType(),
3958 InChain,
3959 getValue(I.getPointerOperand()),
3960 getValue(I.getValOperand()),
3961 I.getPointerOperand(),
3962 /* Alignment=*/ 0, Order, Scope);
3963
3964 SDValue OutChain = L.getValue(1);
3965
3966 setValue(&I, L);
3967 DAG.setRoot(OutChain);
3968}
3969
3970void SelectionDAGBuilder::visitFence(const FenceInst &I) {
3971 SDLoc dl = getCurSDLoc();
3972 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3973 SDValue Ops[3];
3974 Ops[0] = getRoot();
3975 Ops[1] = DAG.getConstant((unsigned)I.getOrdering(), dl,
3976 TLI.getPointerTy(DAG.getDataLayout()));
3977 Ops[2] = DAG.getConstant(I.getSynchScope(), dl,
3978 TLI.getPointerTy(DAG.getDataLayout()));
3979 DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops));
3980}
3981
3982void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) {
3983 SDLoc dl = getCurSDLoc();
3984 AtomicOrdering Order = I.getOrdering();
3985 SynchronizationScope Scope = I.getSynchScope();
3986
3987 SDValue InChain = getRoot();
3988
3989 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3990 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
3991
3992 if (I.getAlignment() < VT.getSizeInBits() / 8)
3993 report_fatal_error("Cannot generate unaligned atomic load");
3994
3995 MachineMemOperand *MMO =
3996 DAG.getMachineFunction().
3997 getMachineMemOperand(MachinePointerInfo(I.getPointerOperand()),
3998 MachineMemOperand::MOVolatile |
3999 MachineMemOperand::MOLoad,
4000 VT.getStoreSize(),
4001 I.getAlignment() ? I.getAlignment() :
4002 DAG.getEVTAlignment(VT),
4003 AAMDNodes(), nullptr, Scope, Order);
4004
4005 InChain = TLI.prepareVolatileOrAtomicLoad(InChain, dl, DAG);
4006 SDValue L =
4007 DAG.getAtomic(ISD::ATOMIC_LOAD, dl, VT, VT, InChain,
4008 getValue(I.getPointerOperand()), MMO);
4009
4010 SDValue OutChain = L.getValue(1);
4011
4012 setValue(&I, L);
4013 DAG.setRoot(OutChain);
4014}
4015
4016void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) {
4017 SDLoc dl = getCurSDLoc();
4018
4019 AtomicOrdering Order = I.getOrdering();
4020 SynchronizationScope Scope = I.getSynchScope();
4021
4022 SDValue InChain = getRoot();
4023
4024 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4025 EVT VT =
4026 TLI.getValueType(DAG.getDataLayout(), I.getValueOperand()->getType());
4027
4028 if (I.getAlignment() < VT.getSizeInBits() / 8)
4029 report_fatal_error("Cannot generate unaligned atomic store");
4030
4031 SDValue OutChain =
4032 DAG.getAtomic(ISD::ATOMIC_STORE, dl, VT,
4033 InChain,
4034 getValue(I.getPointerOperand()),
4035 getValue(I.getValueOperand()),
4036 I.getPointerOperand(), I.getAlignment(),
4037 Order, Scope);
4038
4039 DAG.setRoot(OutChain);
4040}
4041
4042/// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
4043/// node.
4044void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
4045 unsigned Intrinsic) {
4046 // Ignore the callsite's attributes. A specific call site may be marked with
4047 // readnone, but the lowering code will expect the chain based on the
4048 // definition.
4049 const Function *F = I.getCalledFunction();
4050 bool HasChain = !F->doesNotAccessMemory();
4051 bool OnlyLoad = HasChain && F->onlyReadsMemory();
4052
4053 // Build the operand list.
4054 SmallVector<SDValue, 8> Ops;
4055 if (HasChain) { // If this intrinsic has side-effects, chainify it.
4056 if (OnlyLoad) {
4057 // We don't need to serialize loads against other loads.
4058 Ops.push_back(DAG.getRoot());
4059 } else {
4060 Ops.push_back(getRoot());
4061 }
4062 }
4063
4064 // Info is set by getTgtMemInstrinsic
4065 TargetLowering::IntrinsicInfo Info;
4066 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4067 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
4068
4069 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
4070 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID ||
4071 Info.opc == ISD::INTRINSIC_W_CHAIN)
4072 Ops.push_back(DAG.getTargetConstant(Intrinsic, getCurSDLoc(),
4073 TLI.getPointerTy(DAG.getDataLayout())));
4074
4075 // Add all operands of the call to the operand list.
4076 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
4077 SDValue Op = getValue(I.getArgOperand(i));
4078 Ops.push_back(Op);
4079 }
4080
4081 SmallVector<EVT, 4> ValueVTs;
4082 ComputeValueVTs(TLI, DAG.getDataLayout(), I.getType(), ValueVTs);
4083
4084 if (HasChain)
4085 ValueVTs.push_back(MVT::Other);
4086
4087 SDVTList VTs = DAG.getVTList(ValueVTs);
4088
4089 // Create the node.
4090 SDValue Result;
4091 if (IsTgtIntrinsic) {
4092 // This is target intrinsic that touches memory
4093 Result = DAG.getMemIntrinsicNode(Info.opc, getCurSDLoc(),
4094 VTs, Ops, Info.memVT,
4095 MachinePointerInfo(Info.ptrVal, Info.offset),
4096 Info.align, Info.vol,
4097 Info.readMem, Info.writeMem, Info.size);
4098 } else if (!HasChain) {
4099 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurSDLoc(), VTs, Ops);
4100 } else if (!I.getType()->isVoidTy()) {
4101 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurSDLoc(), VTs, Ops);
4102 } else {
4103 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurSDLoc(), VTs, Ops);
4104 }
4105
4106 if (HasChain) {
4107 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
4108 if (OnlyLoad)
4109 PendingLoads.push_back(Chain);
4110 else
4111 DAG.setRoot(Chain);
4112 }
4113
4114 if (!I.getType()->isVoidTy()) {
4115 if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
4116 EVT VT = TLI.getValueType(DAG.getDataLayout(), PTy);
4117 Result = DAG.getNode(ISD::BITCAST, getCurSDLoc(), VT, Result);
4118 } else
4119 Result = lowerRangeToAssertZExt(DAG, I, Result);
4120
4121 setValue(&I, Result);
4122 }
4123}
4124
4125/// GetSignificand - Get the significand and build it into a floating-point
4126/// number with exponent of 1:
4127///
4128/// Op = (Op & 0x007fffff) | 0x3f800000;
4129///
4130/// where Op is the hexadecimal representation of floating point value.
4131static SDValue GetSignificand(SelectionDAG &DAG, SDValue Op, const SDLoc &dl) {
4132 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
4133 DAG.getConstant(0x007fffff, dl, MVT::i32));
4134 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
4135 DAG.getConstant(0x3f800000, dl, MVT::i32));
4136 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2);
4137}
4138
4139/// GetExponent - Get the exponent:
4140///
4141/// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
4142///
4143/// where Op is the hexadecimal representation of floating point value.
4144static SDValue GetExponent(SelectionDAG &DAG, SDValue Op,
4145 const TargetLowering &TLI, const SDLoc &dl) {
4146 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
4147 DAG.getConstant(0x7f800000, dl, MVT::i32));
4148 SDValue t1 = DAG.getNode(
4149 ISD::SRL, dl, MVT::i32, t0,
4150 DAG.getConstant(23, dl, TLI.getPointerTy(DAG.getDataLayout())));
4151 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
4152 DAG.getConstant(127, dl, MVT::i32));
4153 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
4154}
4155
4156/// getF32Constant - Get 32-bit floating point constant.
4157static SDValue getF32Constant(SelectionDAG &DAG, unsigned Flt,
4158 const SDLoc &dl) {
4159 return DAG.getConstantFP(APFloat(APFloat::IEEEsingle(), APInt(32, Flt)), dl,
4160 MVT::f32);
4161}
4162
4163static SDValue getLimitedPrecisionExp2(SDValue t0, const SDLoc &dl,
4164 SelectionDAG &DAG) {
4165 // TODO: What fast-math-flags should be set on the floating-point nodes?
4166
4167 // IntegerPartOfX = ((int32_t)(t0);
4168 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
4169
4170 // FractionalPartOfX = t0 - (float)IntegerPartOfX;
4171 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
4172 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
4173
4174 // IntegerPartOfX <<= 23;
4175 IntegerPartOfX = DAG.getNode(
4176 ISD::SHL, dl, MVT::i32, IntegerPartOfX,
4177 DAG.getConstant(23, dl, DAG.getTargetLoweringInfo().getPointerTy(
4178 DAG.getDataLayout())));
4179
4180 SDValue TwoToFractionalPartOfX;
4181 if (LimitFloatPrecision <= 6) {
4182 // For floating-point precision of 6:
4183 //
4184 // TwoToFractionalPartOfX =
4185 // 0.997535578f +
4186 // (0.735607626f + 0.252464424f * x) * x;
4187 //
4188 // error 0.0144103317, which is 6 bits
4189 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4190 getF32Constant(DAG, 0x3e814304, dl));
4191 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4192 getF32Constant(DAG, 0x3f3c50c8, dl));
4193 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4194 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4195 getF32Constant(DAG, 0x3f7f5e7e, dl));
4196 } else if (LimitFloatPrecision <= 12) {
4197 // For floating-point precision of 12:
4198 //
4199 // TwoToFractionalPartOfX =
4200 // 0.999892986f +
4201 // (0.696457318f +
4202 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
4203 //
4204 // error 0.000107046256, which is 13 to 14 bits
4205 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4206 getF32Constant(DAG, 0x3da235e3, dl));
4207 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4208 getF32Constant(DAG, 0x3e65b8f3, dl));
4209 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4210 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4211 getF32Constant(DAG, 0x3f324b07, dl));
4212 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4213 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4214 getF32Constant(DAG, 0x3f7ff8fd, dl));
4215 } else { // LimitFloatPrecision <= 18
4216 // For floating-point precision of 18:
4217 //
4218 // TwoToFractionalPartOfX =
4219 // 0.999999982f +
4220 // (0.693148872f +
4221 // (0.240227044f +
4222 // (0.554906021e-1f +
4223 // (0.961591928e-2f +
4224 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
4225 // error 2.47208000*10^(-7), which is better than 18 bits
4226 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4227 getF32Constant(DAG, 0x3924b03e, dl));
4228 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4229 getF32Constant(DAG, 0x3ab24b87, dl));
4230 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4231 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4232 getF32Constant(DAG, 0x3c1d8c17, dl));
4233 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4234 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4235 getF32Constant(DAG, 0x3d634a1d, dl));
4236 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4237 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4238 getF32Constant(DAG, 0x3e75fe14, dl));
4239 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4240 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
4241 getF32Constant(DAG, 0x3f317234, dl));
4242 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
4243 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
4244 getF32Constant(DAG, 0x3f800000, dl));
4245 }
4246
4247 // Add the exponent into the result in integer domain.
4248 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, TwoToFractionalPartOfX);
4249 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
4250 DAG.getNode(ISD::ADD, dl, MVT::i32, t13, IntegerPartOfX));
4251}
4252
4253/// expandExp - Lower an exp intrinsic. Handles the special sequences for
4254/// limited-precision mode.
4255static SDValue expandExp(const SDLoc &dl, SDValue Op, SelectionDAG &DAG,
4256 const TargetLowering &TLI) {
4257 if (Op.getValueType() == MVT::f32 &&
4258 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4259
4260 // Put the exponent in the right bit position for later addition to the
4261 // final result:
4262 //
4263 // #define LOG2OFe 1.4426950f
4264 // t0 = Op * LOG2OFe
4265
4266 // TODO: What fast-math-flags should be set here?
4267 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
4268 getF32Constant(DAG, 0x3fb8aa3b, dl));
4269 return getLimitedPrecisionExp2(t0, dl, DAG);
4270 }
4271
4272 // No special expansion.
4273 return DAG.getNode(ISD::FEXP, dl, Op.getValueType(), Op);
4274}
4275
4276/// expandLog - Lower a log intrinsic. Handles the special sequences for
4277/// limited-precision mode.
4278static SDValue expandLog(const SDLoc &dl, SDValue Op, SelectionDAG &DAG,
4279 const TargetLowering &TLI) {
4280
4281 // TODO: What fast-math-flags should be set on the floating-point nodes?
4282
4283 if (Op.getValueType() == MVT::f32 &&
4284 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4285 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
4286
4287 // Scale the exponent by log(2) [0.69314718f].
4288 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
4289 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
4290 getF32Constant(DAG, 0x3f317218, dl));
4291
4292 // Get the significand and build it into a floating-point number with
4293 // exponent of 1.
4294 SDValue X = GetSignificand(DAG, Op1, dl);
4295
4296 SDValue LogOfMantissa;
4297 if (LimitFloatPrecision <= 6) {
4298 // For floating-point precision of 6:
4299 //
4300 // LogofMantissa =
4301 // -1.1609546f +
4302 // (1.4034025f - 0.23903021f * x) * x;
4303 //
4304 // error 0.0034276066, which is better than 8 bits
4305 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4306 getF32Constant(DAG, 0xbe74c456, dl));
4307 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4308 getF32Constant(DAG, 0x3fb3a2b1, dl));
4309 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4310 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4311 getF32Constant(DAG, 0x3f949a29, dl));
4312 } else if (LimitFloatPrecision <= 12) {
4313 // For floating-point precision of 12:
4314 //
4315 // LogOfMantissa =
4316 // -1.7417939f +
4317 // (2.8212026f +
4318 // (-1.4699568f +
4319 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
4320 //
4321 // error 0.000061011436, which is 14 bits
4322 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4323 getF32Constant(DAG, 0xbd67b6d6, dl));
4324 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4325 getF32Constant(DAG, 0x3ee4f4b8, dl));
4326 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4327 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4328 getF32Constant(DAG, 0x3fbc278b, dl));
4329 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4330 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4331 getF32Constant(DAG, 0x40348e95, dl));
4332 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4333 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4334 getF32Constant(DAG, 0x3fdef31a, dl));
4335 } else { // LimitFloatPrecision <= 18
4336 // For floating-point precision of 18:
4337 //
4338 // LogOfMantissa =
4339 // -2.1072184f +
4340 // (4.2372794f +
4341 // (-3.7029485f +
4342 // (2.2781945f +
4343 // (-0.87823314f +
4344 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
4345 //
4346 // error 0.0000023660568, which is better than 18 bits
4347 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4348 getF32Constant(DAG, 0xbc91e5ac, dl));
4349 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4350 getF32Constant(DAG, 0x3e4350aa, dl));
4351 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4352 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4353 getF32Constant(DAG, 0x3f60d3e3, dl));
4354 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4355 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4356 getF32Constant(DAG, 0x4011cdf0, dl));
4357 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4358 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4359 getF32Constant(DAG, 0x406cfd1c, dl));
4360 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4361 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4362 getF32Constant(DAG, 0x408797cb, dl));
4363 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4364 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
4365 getF32Constant(DAG, 0x4006dcab, dl));
4366 }
4367
4368 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, LogOfMantissa);
4369 }
4370
4371 // No special expansion.
4372 return DAG.getNode(ISD::FLOG, dl, Op.getValueType(), Op);
4373}
4374
4375/// expandLog2 - Lower a log2 intrinsic. Handles the special sequences for
4376/// limited-precision mode.
4377static SDValue expandLog2(const SDLoc &dl, SDValue Op, SelectionDAG &DAG,
4378 const TargetLowering &TLI) {
4379
4380 // TODO: What fast-math-flags should be set on the floating-point nodes?
4381
4382 if (Op.getValueType() == MVT::f32 &&
4383 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4384 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
4385
4386 // Get the exponent.
4387 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
4388
4389 // Get the significand and build it into a floating-point number with
4390 // exponent of 1.
4391 SDValue X = GetSignificand(DAG, Op1, dl);
4392
4393 // Different possible minimax approximations of significand in
4394 // floating-point for various degrees of accuracy over [1,2].
4395 SDValue Log2ofMantissa;
4396 if (LimitFloatPrecision <= 6) {
4397 // For floating-point precision of 6:
4398 //
4399 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
4400 //
4401 // error 0.0049451742, which is more than 7 bits
4402 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4403 getF32Constant(DAG, 0xbeb08fe0, dl));
4404 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4405 getF32Constant(DAG, 0x40019463, dl));
4406 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4407 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4408 getF32Constant(DAG, 0x3fd6633d, dl));
4409 } else if (LimitFloatPrecision <= 12) {
4410 // For floating-point precision of 12:
4411 //
4412 // Log2ofMantissa =
4413 // -2.51285454f +
4414 // (4.07009056f +
4415 // (-2.12067489f +
4416 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
4417 //
4418 // error 0.0000876136000, which is better than 13 bits
4419 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4420 getF32Constant(DAG, 0xbda7262e, dl));
4421 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4422 getF32Constant(DAG, 0x3f25280b, dl));
4423 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4424 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4425 getF32Constant(DAG, 0x4007b923, dl));
4426 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4427 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4428 getF32Constant(DAG, 0x40823e2f, dl));
4429 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4430 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4431 getF32Constant(DAG, 0x4020d29c, dl));
4432 } else { // LimitFloatPrecision <= 18
4433 // For floating-point precision of 18:
4434 //
4435 // Log2ofMantissa =
4436 // -3.0400495f +
4437 // (6.1129976f +
4438 // (-5.3420409f +
4439 // (3.2865683f +
4440 // (-1.2669343f +
4441 // (0.27515199f -
4442 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
4443 //
4444 // error 0.0000018516, which is better than 18 bits
4445 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4446 getF32Constant(DAG, 0xbcd2769e, dl));
4447 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4448 getF32Constant(DAG, 0x3e8ce0b9, dl));
4449 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4450 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4451 getF32Constant(DAG, 0x3fa22ae7, dl));
4452 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4453 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4454 getF32Constant(DAG, 0x40525723, dl));
4455 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4456 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4457 getF32Constant(DAG, 0x40aaf200, dl));
4458 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4459 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4460 getF32Constant(DAG, 0x40c39dad, dl));
4461 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4462 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
4463 getF32Constant(DAG, 0x4042902c, dl));
4464 }
4465
4466 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log2ofMantissa);
4467 }
4468
4469 // No special expansion.
4470 return DAG.getNode(ISD::FLOG2, dl, Op.getValueType(), Op);
4471}
4472
4473/// expandLog10 - Lower a log10 intrinsic. Handles the special sequences for
4474/// limited-precision mode.
4475static SDValue expandLog10(const SDLoc &dl, SDValue Op, SelectionDAG &DAG,
4476 const TargetLowering &TLI) {
4477
4478 // TODO: What fast-math-flags should be set on the floating-point nodes?
4479
4480 if (Op.getValueType() == MVT::f32 &&
4481 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4482 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
4483
4484 // Scale the exponent by log10(2) [0.30102999f].
4485 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
4486 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
4487 getF32Constant(DAG, 0x3e9a209a, dl));
4488
4489 // Get the significand and build it into a floating-point number with
4490 // exponent of 1.
4491 SDValue X = GetSignificand(DAG, Op1, dl);
4492
4493 SDValue Log10ofMantissa;
4494 if (LimitFloatPrecision <= 6) {
4495 // For floating-point precision of 6:
4496 //
4497 // Log10ofMantissa =
4498 // -0.50419619f +
4499 // (0.60948995f - 0.10380950f * x) * x;
4500 //
4501 // error 0.0014886165, which is 6 bits
4502 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4503 getF32Constant(DAG, 0xbdd49a13, dl));
4504 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4505 getF32Constant(DAG, 0x3f1c0789, dl));
4506 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4507 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4508 getF32Constant(DAG, 0x3f011300, dl));
4509 } else if (LimitFloatPrecision <= 12) {
4510 // For floating-point precision of 12:
4511 //
4512 // Log10ofMantissa =
4513 // -0.64831180f +
4514 // (0.91751397f +
4515 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
4516 //
4517 // error 0.00019228036, which is better than 12 bits
4518 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4519 getF32Constant(DAG, 0x3d431f31, dl));
4520 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4521 getF32Constant(DAG, 0x3ea21fb2, dl));
4522 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4523 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4524 getF32Constant(DAG, 0x3f6ae232, dl));
4525 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4526 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4527 getF32Constant(DAG, 0x3f25f7c3, dl));
4528 } else { // LimitFloatPrecision <= 18
4529 // For floating-point precision of 18:
4530 //
4531 // Log10ofMantissa =
4532 // -0.84299375f +
4533 // (1.5327582f +
4534 // (-1.0688956f +
4535 // (0.49102474f +
4536 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
4537 //
4538 // error 0.0000037995730, which is better than 18 bits
4539 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4540 getF32Constant(DAG, 0x3c5d51ce, dl));
4541 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4542 getF32Constant(DAG, 0x3e00685a, dl));
4543 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4544 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4545 getF32Constant(DAG, 0x3efb6798, dl));
4546 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4547 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4548 getF32Constant(DAG, 0x3f88d192, dl));
4549 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4550 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4551 getF32Constant(DAG, 0x3fc4316c, dl));
4552 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4553 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
4554 getF32Constant(DAG, 0x3f57ce70, dl));
4555 }
4556
4557 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log10ofMantissa);
4558 }
4559
4560 // No special expansion.
4561 return DAG.getNode(ISD::FLOG10, dl, Op.getValueType(), Op);
4562}
4563
4564/// expandExp2 - Lower an exp2 intrinsic. Handles the special sequences for
4565/// limited-precision mode.
4566static SDValue expandExp2(const SDLoc &dl, SDValue Op, SelectionDAG &DAG,
4567 const TargetLowering &TLI) {
4568 if (Op.getValueType() == MVT::f32 &&
4569 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18)
4570 return getLimitedPrecisionExp2(Op, dl, DAG);
4571
4572 // No special expansion.
4573 return DAG.getNode(ISD::FEXP2, dl, Op.getValueType(), Op);
4574}
4575
4576/// visitPow - Lower a pow intrinsic. Handles the special sequences for
4577/// limited-precision mode with x == 10.0f.
4578static SDValue expandPow(const SDLoc &dl, SDValue LHS, SDValue RHS,
4579 SelectionDAG &DAG, const TargetLowering &TLI) {
4580 bool IsExp10 = false;
4581 if (LHS.getValueType() == MVT::f32 && RHS.getValueType() == MVT::f32 &&
4582 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4583 if (ConstantFPSDNode *LHSC = dyn_cast<ConstantFPSDNode>(LHS)) {
4584 APFloat Ten(10.0f);
4585 IsExp10 = LHSC->isExactlyValue(Ten);
4586 }
4587 }
4588
4589 // TODO: What fast-math-flags should be set on the FMUL node?
4590 if (IsExp10) {
4591 // Put the exponent in the right bit position for later addition to the
4592 // final result:
4593 //
4594 // #define LOG2OF10 3.3219281f
4595 // t0 = Op * LOG2OF10;
4596 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, RHS,
4597 getF32Constant(DAG, 0x40549a78, dl));
4598 return getLimitedPrecisionExp2(t0, dl, DAG);
4599 }
4600
4601 // No special expansion.
4602 return DAG.getNode(ISD::FPOW, dl, LHS.getValueType(), LHS, RHS);
4603}
4604
4605
4606/// ExpandPowI - Expand a llvm.powi intrinsic.
4607static SDValue ExpandPowI(const SDLoc &DL, SDValue LHS, SDValue RHS,
4608 SelectionDAG &DAG) {
4609 // If RHS is a constant, we can expand this out to a multiplication tree,
4610 // otherwise we end up lowering to a call to __powidf2 (for example). When
4611 // optimizing for size, we only want to do this if the expansion would produce
4612 // a small number of multiplies, otherwise we do the full expansion.
4613 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
4614 // Get the exponent as a positive value.
4615 unsigned Val = RHSC->getSExtValue();
4616 if ((int)Val < 0) Val = -Val;
4617
4618 // powi(x, 0) -> 1.0
4619 if (Val == 0)
4620 return DAG.getConstantFP(1.0, DL, LHS.getValueType());
4621
4622 const Function *F = DAG.getMachineFunction().getFunction();
4623 if (!F->optForSize() ||
4624 // If optimizing for size, don't insert too many multiplies.
4625 // This inserts up to 5 multiplies.
4626 countPopulation(Val) + Log2_32(Val) < 7) {
4627 // We use the simple binary decomposition method to generate the multiply
4628 // sequence. There are more optimal ways to do this (for example,
4629 // powi(x,15) generates one more multiply than it should), but this has
4630 // the benefit of being both really simple and much better than a libcall.
4631 SDValue Res; // Logically starts equal to 1.0
4632 SDValue CurSquare = LHS;
4633 // TODO: Intrinsics should have fast-math-flags that propagate to these
4634 // nodes.
4635 while (Val) {
4636 if (Val & 1) {
4637 if (Res.getNode())
4638 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare);
4639 else
4640 Res = CurSquare; // 1.0*CurSquare.
4641 }
4642
4643 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(),
4644 CurSquare, CurSquare);
4645 Val >>= 1;
4646 }
4647
4648 // If the original was negative, invert the result, producing 1/(x*x*x).
4649 if (RHSC->getSExtValue() < 0)
4650 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(),
4651 DAG.getConstantFP(1.0, DL, LHS.getValueType()), Res);
4652 return Res;
4653 }
4654 }
4655
4656 // Otherwise, expand to a libcall.
4657 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS);
4658}
4659
4660// getUnderlyingArgReg - Find underlying register used for a truncated or
4661// bitcasted argument.
4662static unsigned getUnderlyingArgReg(const SDValue &N) {
4663 switch (N.getOpcode()) {
4664 case ISD::CopyFromReg:
4665 return cast<RegisterSDNode>(N.getOperand(1))->getReg();
4666 case ISD::BITCAST:
4667 case ISD::AssertZext:
4668 case ISD::AssertSext:
4669 case ISD::TRUNCATE:
4670 return getUnderlyingArgReg(N.getOperand(0));
4671 default:
4672 return 0;
4673 }
4674}
4675
4676/// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function
4677/// argument, create the corresponding DBG_VALUE machine instruction for it now.
4678/// At the end of instruction selection, they will be inserted to the entry BB.
4679bool SelectionDAGBuilder::EmitFuncArgumentDbgValue(
4680 const Value *V, DILocalVariable *Variable, DIExpression *Expr,
4681 DILocation *DL, int64_t Offset, bool IsIndirect, const SDValue &N) {
4682 const Argument *Arg = dyn_cast<Argument>(V);
4683 if (!Arg)
4684 return false;
4685
4686 MachineFunction &MF = DAG.getMachineFunction();
4687 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
4688
4689 // Ignore inlined function arguments here.
4690 //
4691 // FIXME: Should we be checking DL->inlinedAt() to determine this?
4692 if (!Variable->getScope()->getSubprogram()->describes(MF.getFunction()))
4693 return false;
4694
4695 Optional<MachineOperand> Op;
4696 // Some arguments' frame index is recorded during argument lowering.
4697 if (int FI = FuncInfo.getArgumentFrameIndex(Arg))
4698 Op = MachineOperand::CreateFI(FI);
4699
4700 if (!Op && N.getNode()) {
4701 unsigned Reg = getUnderlyingArgReg(N);
4702 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) {
4703 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4704 unsigned PR = RegInfo.getLiveInPhysReg(Reg);
4705 if (PR)
4706 Reg = PR;
4707 }
4708 if (Reg)
4709 Op = MachineOperand::CreateReg(Reg, false);
4710 }
4711
4712 if (!Op) {
4713 // Check if ValueMap has reg number.
4714 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
4715 if (VMI != FuncInfo.ValueMap.end())
4716 Op = MachineOperand::CreateReg(VMI->second, false);
4717 }
4718
4719 if (!Op && N.getNode())
4720 // Check if frame index is available.
4721 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode()))
4722 if (FrameIndexSDNode *FINode =
4723 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
4724 Op = MachineOperand::CreateFI(FINode->getIndex());
4725
4726 if (!Op)
4727 return false;
4728
4729 assert(Variable->isValidLocationForIntrinsic(DL) &&((Variable->isValidLocationForIntrinsic(DL) && "Expected inlined-at fields to agree"
) ? static_cast<void> (0) : __assert_fail ("Variable->isValidLocationForIntrinsic(DL) && \"Expected inlined-at fields to agree\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 4730, __PRETTY_FUNCTION__))
4730 "Expected inlined-at fields to agree")((Variable->isValidLocationForIntrinsic(DL) && "Expected inlined-at fields to agree"
) ? static_cast<void> (0) : __assert_fail ("Variable->isValidLocationForIntrinsic(DL) && \"Expected inlined-at fields to agree\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 4730, __PRETTY_FUNCTION__))
;
4731 if (Op->isReg())
4732 FuncInfo.ArgDbgValues.push_back(
4733 BuildMI(MF, DL, TII->get(TargetOpcode::DBG_VALUE), IsIndirect,
4734 Op->getReg(), Offset, Variable, Expr));
4735 else
4736 FuncInfo.ArgDbgValues.push_back(
4737 BuildMI(MF, DL, TII->get(TargetOpcode::DBG_VALUE))
4738 .add(*Op)
4739 .addImm(Offset)
4740 .addMetadata(Variable)
4741 .addMetadata(Expr));
4742
4743 return true;
4744}
4745
4746/// Return the appropriate SDDbgValue based on N.
4747SDDbgValue *SelectionDAGBuilder::getDbgValue(SDValue N,
4748 DILocalVariable *Variable,
4749 DIExpression *Expr, int64_t Offset,
4750 const DebugLoc &dl,
4751 unsigned DbgSDNodeOrder) {
4752 SDDbgValue *SDV;
4753 auto *FISDN = dyn_cast<FrameIndexSDNode>(N.getNode());
4754 if (FISDN && Expr->startsWithDeref()) {
4755 // Construct a FrameIndexDbgValue for FrameIndexSDNodes so we can describe
4756 // stack slot locations as such instead of as indirectly addressed
4757 // locations.
4758 ArrayRef<uint64_t> TrailingElements(Expr->elements_begin() + 1,
4759 Expr->elements_end());
4760 DIExpression *DerefedDIExpr =
4761 DIExpression::get(*DAG.getContext(), TrailingElements);
4762 int FI = FISDN->getIndex();
4763 SDV = DAG.getFrameIndexDbgValue(Variable, DerefedDIExpr, FI, 0, dl,
4764 DbgSDNodeOrder);
4765 } else {
4766 SDV = DAG.getDbgValue(Variable, Expr, N.getNode(), N.getResNo(), false,
4767 Offset, dl, DbgSDNodeOrder);
4768 }
4769 return SDV;
4770}
4771
4772// VisualStudio defines setjmp as _setjmp
4773#if defined(_MSC_VER) && defined(setjmp) && \
4774 !defined(setjmp_undefined_for_msvc)
4775# pragma push_macro("setjmp")
4776# undef setjmp
4777# define setjmp_undefined_for_msvc
4778#endif
4779
4780/// Lower the call to the specified intrinsic function. If we want to emit this
4781/// as a call to a named external function, return the name. Otherwise, lower it
4782/// and return null.
4783const char *
4784SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
4785 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4786 SDLoc sdl = getCurSDLoc();
4787 DebugLoc dl = getCurDebugLoc();
4788 SDValue Res;
4789
4790 switch (Intrinsic) {
4791 default:
4792 // By default, turn this into a target intrinsic node.
4793 visitTargetIntrinsic(I, Intrinsic);
4794 return nullptr;
4795 case Intrinsic::vastart: visitVAStart(I); return nullptr;
4796 case Intrinsic::vaend: visitVAEnd(I); return nullptr;
4797 case Intrinsic::vacopy: visitVACopy(I); return nullptr;
4798 case Intrinsic::returnaddress:
4799 setValue(&I, DAG.getNode(ISD::RETURNADDR, sdl,
4800 TLI.getPointerTy(DAG.getDataLayout()),
4801 getValue(I.getArgOperand(0))));
4802 return nullptr;
4803 case Intrinsic::addressofreturnaddress:
4804 setValue(&I, DAG.getNode(ISD::ADDROFRETURNADDR, sdl,
4805 TLI.getPointerTy(DAG.getDataLayout())));
4806 return nullptr;
4807 case Intrinsic::frameaddress:
4808 setValue(&I, DAG.getNode(ISD::FRAMEADDR, sdl,
4809 TLI.getPointerTy(DAG.getDataLayout()),
4810 getValue(I.getArgOperand(0))));
4811 return nullptr;
4812 case Intrinsic::read_register: {
4813 Value *Reg = I.getArgOperand(0);
4814 SDValue Chain = getRoot();
4815 SDValue RegName =
4816 DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
4817 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4818 Res = DAG.getNode(ISD::READ_REGISTER, sdl,
4819 DAG.getVTList(VT, MVT::Other), Chain, RegName);
4820 setValue(&I, Res);
4821 DAG.setRoot(Res.getValue(1));
4822 return nullptr;
4823 }
4824 case Intrinsic::write_register: {
4825 Value *Reg = I.getArgOperand(0);
4826 Value *RegValue = I.getArgOperand(1);
4827 SDValue Chain = getRoot();
4828 SDValue RegName =
4829 DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
4830 DAG.setRoot(DAG.getNode(ISD::WRITE_REGISTER, sdl, MVT::Other, Chain,
4831 RegName, getValue(RegValue)));
4832 return nullptr;
4833 }
4834 case Intrinsic::setjmp:
4835 return &"_setjmp"[!TLI.usesUnderscoreSetJmp()];
4836 case Intrinsic::longjmp:
4837 return &"_longjmp"[!TLI.usesUnderscoreLongJmp()];
4838 case Intrinsic::memcpy: {
4839 SDValue Op1 = getValue(I.getArgOperand(0));
4840 SDValue Op2 = getValue(I.getArgOperand(1));
4841 SDValue Op3 = getValue(I.getArgOperand(2));
4842 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4843 if (!Align)
4844 Align = 1; // @llvm.memcpy defines 0 and 1 to both mean no alignment.
4845 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4846 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4847 SDValue MC = DAG.getMemcpy(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4848 false, isTC,
4849 MachinePointerInfo(I.getArgOperand(0)),
4850 MachinePointerInfo(I.getArgOperand(1)));
4851 updateDAGForMaybeTailCall(MC);
4852 return nullptr;
4853 }
4854 case Intrinsic::memset: {
4855 SDValue Op1 = getValue(I.getArgOperand(0));
4856 SDValue Op2 = getValue(I.getArgOperand(1));
4857 SDValue Op3 = getValue(I.getArgOperand(2));
4858 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4859 if (!Align)
4860 Align = 1; // @llvm.memset defines 0 and 1 to both mean no alignment.
4861 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4862 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4863 SDValue MS = DAG.getMemset(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4864 isTC, MachinePointerInfo(I.getArgOperand(0)));
4865 updateDAGForMaybeTailCall(MS);
4866 return nullptr;
4867 }
4868 case Intrinsic::memmove: {
4869 SDValue Op1 = getValue(I.getArgOperand(0));
4870 SDValue Op2 = getValue(I.getArgOperand(1));
4871 SDValue Op3 = getValue(I.getArgOperand(2));
4872 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4873 if (!Align)
4874 Align = 1; // @llvm.memmove defines 0 and 1 to both mean no alignment.
4875 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4876 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4877 SDValue MM = DAG.getMemmove(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4878 isTC, MachinePointerInfo(I.getArgOperand(0)),
4879 MachinePointerInfo(I.getArgOperand(1)));
4880 updateDAGForMaybeTailCall(MM);
4881 return nullptr;
4882 }
4883 case Intrinsic::memcpy_element_atomic: {
4884 SDValue Dst = getValue(I.getArgOperand(0));
4885 SDValue Src = getValue(I.getArgOperand(1));
4886 SDValue NumElements = getValue(I.getArgOperand(2));
4887 SDValue ElementSize = getValue(I.getArgOperand(3));
4888
4889 // Emit a library call.
4890 TargetLowering::ArgListTy Args;
4891 TargetLowering::ArgListEntry Entry;
4892 Entry.Ty = DAG.getDataLayout().getIntPtrType(*DAG.getContext());
4893 Entry.Node = Dst;
4894 Args.push_back(Entry);
4895
4896 Entry.Node = Src;
4897 Args.push_back(Entry);
4898
4899 Entry.Ty = I.getArgOperand(2)->getType();
4900 Entry.Node = NumElements;
4901 Args.push_back(Entry);
4902
4903 Entry.Ty = Type::getInt32Ty(*DAG.getContext());
4904 Entry.Node = ElementSize;
4905 Args.push_back(Entry);
4906
4907 uint64_t ElementSizeConstant =
4908 cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4909 RTLIB::Libcall LibraryCall =
4910 RTLIB::getMEMCPY_ELEMENT_ATOMIC(ElementSizeConstant);
4911 if (LibraryCall == RTLIB::UNKNOWN_LIBCALL)
4912 report_fatal_error("Unsupported element size");
4913
4914 TargetLowering::CallLoweringInfo CLI(DAG);
4915 CLI.setDebugLoc(sdl).setChain(getRoot()).setLibCallee(
4916 TLI.getLibcallCallingConv(LibraryCall),
4917 Type::getVoidTy(*DAG.getContext()),
4918 DAG.getExternalSymbol(TLI.getLibcallName(LibraryCall),
4919 TLI.getPointerTy(DAG.getDataLayout())),
4920 std::move(Args));
4921
4922 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
4923 DAG.setRoot(CallResult.second);
4924 return nullptr;
4925 }
4926 case Intrinsic::dbg_declare: {
4927 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
4928 DILocalVariable *Variable = DI.getVariable();
4929 DIExpression *Expression = DI.getExpression();
4930 const Value *Address = DI.getAddress();
4931 assert(Variable && "Missing variable")((Variable && "Missing variable") ? static_cast<void
> (0) : __assert_fail ("Variable && \"Missing variable\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 4931, __PRETTY_FUNCTION__))
;
4932 if (!Address) {
4933 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << "Dropping debug info for " <<
DI << "\n"; } } while (false)
;
4934 return nullptr;
4935 }
4936
4937 // Check if address has undef value.
4938 if (isa<UndefValue>(Address) ||
4939 (Address->use_empty() && !isa<Argument>(Address))) {
4940 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << "Dropping debug info for " <<
DI << "\n"; } } while (false)
;
4941 return nullptr;
4942 }
4943
4944 SDValue &N = NodeMap[Address];
4945 if (!N.getNode() && isa<Argument>(Address))
4946 // Check unused arguments map.
4947 N = UnusedArgNodeMap[Address];
4948 SDDbgValue *SDV;
4949 if (N.getNode()) {
4950 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
4951 Address = BCI->getOperand(0);
4952 // Parameters are handled specially.
4953 bool isParameter = Variable->isParameter() || isa<Argument>(Address);
4954 auto FINode = dyn_cast<FrameIndexSDNode>(N.getNode());
4955 if (isParameter && FINode) {
4956 // Byval parameter. We have a frame index at this point.
4957 SDV = DAG.getFrameIndexDbgValue(Variable, Expression,
4958 FINode->getIndex(), 0, dl, SDNodeOrder);
4959 } else if (isa<Argument>(Address)) {
4960 // Address is an argument, so try to emit its dbg value using
4961 // virtual register info from the FuncInfo.ValueMap.
4962 EmitFuncArgumentDbgValue(Address, Variable, Expression, dl, 0, false,
4963 N);
4964 return nullptr;
4965 } else {
4966 SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(),
4967 true, 0, dl, SDNodeOrder);
4968 }
4969 DAG.AddDbgValue(SDV, N.getNode(), isParameter);
4970 } else {
4971 // If Address is an argument then try to emit its dbg value using
4972 // virtual register info from the FuncInfo.ValueMap.
4973 if (!EmitFuncArgumentDbgValue(Address, Variable, Expression, dl, 0, false,
4974 N)) {
4975 // If variable is pinned by a alloca in dominating bb then
4976 // use StaticAllocaMap.
4977 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
4978 if (AI->getParent() != DI.getParent()) {
4979 DenseMap<const AllocaInst*, int>::iterator SI =
4980 FuncInfo.StaticAllocaMap.find(AI);
4981 if (SI != FuncInfo.StaticAllocaMap.end()) {
4982 SDV = DAG.getFrameIndexDbgValue(Variable, Expression, SI->second,
4983 0, dl, SDNodeOrder);
4984 DAG.AddDbgValue(SDV, nullptr, false);
4985 return nullptr;
4986 }
4987 }
4988 }
4989 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << "Dropping debug info for " <<
DI << "\n"; } } while (false)
;
4990 }
4991 }
4992 return nullptr;
4993 }
4994 case Intrinsic::dbg_value: {
4995 const DbgValueInst &DI = cast<DbgValueInst>(I);
4996 assert(DI.getVariable() && "Missing variable")((DI.getVariable() && "Missing variable") ? static_cast
<void> (0) : __assert_fail ("DI.getVariable() && \"Missing variable\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 4996, __PRETTY_FUNCTION__))
;
4997
4998 DILocalVariable *Variable = DI.getVariable();
4999 DIExpression *Expression = DI.getExpression();
5000 uint64_t Offset = DI.getOffset();
5001 const Value *V = DI.getValue();
5002 if (!V)
5003 return nullptr;
5004
5005 SDDbgValue *SDV;
5006 if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V)) {
5007 SDV = DAG.getConstantDbgValue(Variable, Expression, V, Offset, dl,
5008 SDNodeOrder);
5009 DAG.AddDbgValue(SDV, nullptr, false);
5010 } else {
5011 // Do not use getValue() in here; we don't want to generate code at
5012 // this point if it hasn't been done yet.
5013 SDValue N = NodeMap[V];
5014 if (!N.getNode() && isa<Argument>(V))
5015 // Check unused arguments map.
5016 N = UnusedArgNodeMap[V];
5017 if (N.getNode()) {
5018 if (!EmitFuncArgumentDbgValue(V, Variable, Expression, dl, Offset,
5019 false, N)) {
5020 SDV = getDbgValue(N, Variable, Expression, Offset, dl, SDNodeOrder);
5021 DAG.AddDbgValue(SDV, N.getNode(), false);
5022 }
5023 } else if (!V->use_empty() ) {
5024 // Do not call getValue(V) yet, as we don't want to generate code.
5025 // Remember it for later.
5026 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder);
5027 DanglingDebugInfoMap[V] = DDI;
5028 } else {
5029 // We may expand this to cover more cases. One case where we have no
5030 // data available is an unreferenced parameter.
5031 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << "Dropping debug info for " <<
DI << "\n"; } } while (false)
;
5032 }
5033 }
5034
5035 // Build a debug info table entry.
5036 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V))
5037 V = BCI->getOperand(0);
5038 const AllocaInst *AI = dyn_cast<AllocaInst>(V);
5039 // Don't handle byval struct arguments or VLAs, for example.
5040 if (!AI) {
5041 DEBUG(dbgs() << "Dropping debug location info for:\n " << DI << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << "Dropping debug location info for:\n "
<< DI << "\n"; } } while (false)
;
5042 DEBUG(dbgs() << " Last seen at:\n " << *V << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << " Last seen at:\n " << *
V << "\n"; } } while (false)
;
5043 return nullptr;
5044 }
5045 DenseMap<const AllocaInst*, int>::iterator SI =
5046 FuncInfo.StaticAllocaMap.find(AI);
5047 if (SI == FuncInfo.StaticAllocaMap.end())
5048 return nullptr; // VLAs.
5049 return nullptr;
5050 }
5051
5052 case Intrinsic::eh_typeid_for: {
5053 // Find the type id for the given typeinfo.
5054 GlobalValue *GV = ExtractTypeInfo(I.getArgOperand(0));
5055 unsigned TypeID = DAG.getMachineFunction().getTypeIDFor(GV);
5056 Res = DAG.getConstant(TypeID, sdl, MVT::i32);
5057 setValue(&I, Res);
5058 return nullptr;
5059 }
5060
5061 case Intrinsic::eh_return_i32:
5062 case Intrinsic::eh_return_i64:
5063 DAG.getMachineFunction().setCallsEHReturn(true);
5064 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, sdl,
5065 MVT::Other,
5066 getControlRoot(),
5067 getValue(I.getArgOperand(0)),
5068 getValue(I.getArgOperand(1))));
5069 return nullptr;
5070 case Intrinsic::eh_unwind_init:
5071 DAG.getMachineFunction().setCallsUnwindInit(true);
5072 return nullptr;
5073 case Intrinsic::eh_dwarf_cfa: {
5074 setValue(&I, DAG.getNode(ISD::EH_DWARF_CFA, sdl,
5075 TLI.getPointerTy(DAG.getDataLayout()),
5076 getValue(I.getArgOperand(0))));
5077 return nullptr;
5078 }
5079 case Intrinsic::eh_sjlj_callsite: {
5080 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5081 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0));
5082 assert(CI && "Non-constant call site value in eh.sjlj.callsite!")((CI && "Non-constant call site value in eh.sjlj.callsite!"
) ? static_cast<void> (0) : __assert_fail ("CI && \"Non-constant call site value in eh.sjlj.callsite!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 5082, __PRETTY_FUNCTION__))
;
5083 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!")((MMI.getCurrentCallSite() == 0 && "Overlapping call sites!"
) ? static_cast<void> (0) : __assert_fail ("MMI.getCurrentCallSite() == 0 && \"Overlapping call sites!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 5083, __PRETTY_FUNCTION__))
;
5084
5085 MMI.setCurrentCallSite(CI->getZExtValue());
5086 return nullptr;
5087 }
5088 case Intrinsic::eh_sjlj_functioncontext: {
5089 // Get and store the index of the function context.
5090 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
5091 AllocaInst *FnCtx =
5092 cast<AllocaInst>(I.getArgOperand(0)->stripPointerCasts());
5093 int FI = FuncInfo.StaticAllocaMap[FnCtx];
5094 MFI.setFunctionContextIndex(FI);
5095 return nullptr;
5096 }
5097 case Intrinsic::eh_sjlj_setjmp: {
5098 SDValue Ops[2];
5099 Ops[0] = getRoot();
5100 Ops[1] = getValue(I.getArgOperand(0));
5101 SDValue Op = DAG.getNode(ISD::EH_SJLJ_SETJMP, sdl,
5102 DAG.getVTList(MVT::i32, MVT::Other), Ops);
5103 setValue(&I, Op.getValue(0));
5104 DAG.setRoot(Op.getValue(1));
5105 return nullptr;
5106 }
5107 case Intrinsic::eh_sjlj_longjmp: {
5108 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, sdl, MVT::Other,
5109 getRoot(), getValue(I.getArgOperand(0))));
5110 return nullptr;
5111 }
5112 case Intrinsic::eh_sjlj_setup_dispatch: {
5113 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_SETUP_DISPATCH, sdl, MVT::Other,
5114 getRoot()));
5115 return nullptr;
5116 }
5117
5118 case Intrinsic::masked_gather:
5119 visitMaskedGather(I);
5120 return nullptr;
5121 case Intrinsic::masked_load:
5122 visitMaskedLoad(I);
5123 return nullptr;
5124 case Intrinsic::masked_scatter:
5125 visitMaskedScatter(I);
5126 return nullptr;
5127 case Intrinsic::masked_store:
5128 visitMaskedStore(I);
5129 return nullptr;
5130 case Intrinsic::masked_expandload:
5131 visitMaskedLoad(I, true /* IsExpanding */);
5132 return nullptr;
5133 case Intrinsic::masked_compressstore:
5134 visitMaskedStore(I, true /* IsCompressing */);
5135 return nullptr;
5136 case Intrinsic::x86_mmx_pslli_w:
5137 case Intrinsic::x86_mmx_pslli_d:
5138 case Intrinsic::x86_mmx_pslli_q:
5139 case Intrinsic::x86_mmx_psrli_w:
5140 case Intrinsic::x86_mmx_psrli_d:
5141 case Intrinsic::x86_mmx_psrli_q:
5142 case Intrinsic::x86_mmx_psrai_w:
5143 case Intrinsic::x86_mmx_psrai_d: {
5144 SDValue ShAmt = getValue(I.getArgOperand(1));
5145 if (isa<ConstantSDNode>(ShAmt)) {
5146 visitTargetIntrinsic(I, Intrinsic);
5147 return nullptr;
5148 }
5149 unsigned NewIntrinsic = 0;
5150 EVT ShAmtVT = MVT::v2i32;
5151 switch (Intrinsic) {
5152 case Intrinsic::x86_mmx_pslli_w:
5153 NewIntrinsic = Intrinsic::x86_mmx_psll_w;
5154 break;
5155 case Intrinsic::x86_mmx_pslli_d:
5156 NewIntrinsic = Intrinsic::x86_mmx_psll_d;
5157 break;
5158 case Intrinsic::x86_mmx_pslli_q:
5159 NewIntrinsic = Intrinsic::x86_mmx_psll_q;
5160 break;
5161 case Intrinsic::x86_mmx_psrli_w:
5162 NewIntrinsic = Intrinsic::x86_mmx_psrl_w;
5163 break;
5164 case Intrinsic::x86_mmx_psrli_d:
5165 NewIntrinsic = Intrinsic::x86_mmx_psrl_d;
5166 break;
5167 case Intrinsic::x86_mmx_psrli_q:
5168 NewIntrinsic = Intrinsic::x86_mmx_psrl_q;
5169 break;
5170 case Intrinsic::x86_mmx_psrai_w:
5171 NewIntrinsic = Intrinsic::x86_mmx_psra_w;
5172 break;
5173 case Intrinsic::x86_mmx_psrai_d:
5174 NewIntrinsic = Intrinsic::x86_mmx_psra_d;
5175 break;
5176 default: llvm_unreachable("Impossible intrinsic")::llvm::llvm_unreachable_internal("Impossible intrinsic", "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 5176)
; // Can't reach here.
5177 }
5178
5179 // The vector shift intrinsics with scalars uses 32b shift amounts but
5180 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
5181 // to be zero.
5182 // We must do this early because v2i32 is not a legal type.
5183 SDValue ShOps[2];
5184 ShOps[0] = ShAmt;
5185 ShOps[1] = DAG.getConstant(0, sdl, MVT::i32);
5186 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, sdl, ShAmtVT, ShOps);
5187 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
5188 ShAmt = DAG.getNode(ISD::BITCAST, sdl, DestVT, ShAmt);
5189 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, sdl, DestVT,
5190 DAG.getConstant(NewIntrinsic, sdl, MVT::i32),
5191 getValue(I.getArgOperand(0)), ShAmt);
5192 setValue(&I, Res);
5193 return nullptr;
5194 }
5195 case Intrinsic::powi:
5196 setValue(&I, ExpandPowI(sdl, getValue(I.getArgOperand(0)),
5197 getValue(I.getArgOperand(1)), DAG));
5198 return nullptr;
5199 case Intrinsic::log:
5200 setValue(&I, expandLog(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
5201 return nullptr;
5202 case Intrinsic::log2:
5203 setValue(&I, expandLog2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
5204 return nullptr;
5205 case Intrinsic::log10:
5206 setValue(&I, expandLog10(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
5207 return nullptr;
5208 case Intrinsic::exp:
5209 setValue(&I, expandExp(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
5210 return nullptr;
5211 case Intrinsic::exp2:
5212 setValue(&I, expandExp2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
5213 return nullptr;
5214 case Intrinsic::pow:
5215 setValue(&I, expandPow(sdl, getValue(I.getArgOperand(0)),
5216 getValue(I.getArgOperand(1)), DAG, TLI));
5217 return nullptr;
5218 case Intrinsic::sqrt:
5219 case Intrinsic::fabs:
5220 case Intrinsic::sin:
5221 case Intrinsic::cos:
5222 case Intrinsic::floor:
5223 case Intrinsic::ceil:
5224 case Intrinsic::trunc:
5225 case Intrinsic::rint:
5226 case Intrinsic::nearbyint:
5227 case Intrinsic::round:
5228 case Intrinsic::canonicalize: {
5229 unsigned Opcode;
5230 switch (Intrinsic) {
5231 default: llvm_unreachable("Impossible intrinsic")::llvm::llvm_unreachable_internal("Impossible intrinsic", "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 5231)
; // Can't reach here.
5232 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break;
5233 case Intrinsic::fabs: Opcode = ISD::FABS; break;
5234 case Intrinsic::sin: Opcode = ISD::FSIN; break;
5235 case Intrinsic::cos: Opcode = ISD::FCOS; break;
5236 case Intrinsic::floor: Opcode = ISD::FFLOOR; break;
5237 case Intrinsic::ceil: Opcode = ISD::FCEIL; break;
5238 case Intrinsic::trunc: Opcode = ISD::FTRUNC; break;
5239 case Intrinsic::rint: Opcode = ISD::FRINT; break;
5240 case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break;
5241 case Intrinsic::round: Opcode = ISD::FROUND; break;
5242 case Intrinsic::canonicalize: Opcode = ISD::FCANONICALIZE; break;
5243 }
5244
5245 setValue(&I, DAG.getNode(Opcode, sdl,
5246 getValue(I.getArgOperand(0)).getValueType(),
5247 getValue(I.getArgOperand(0))));
5248 return nullptr;
5249 }
5250 case Intrinsic::minnum: {
5251 auto VT = getValue(I.getArgOperand(0)).getValueType();
5252 unsigned Opc =
5253 I.hasNoNaNs() && TLI.isOperationLegalOrCustom(ISD::FMINNAN, VT)
5254 ? ISD::FMINNAN
5255 : ISD::FMINNUM;
5256 setValue(&I, DAG.getNode(Opc, sdl, VT,
5257 getValue(I.getArgOperand(0)),
5258 getValue(I.getArgOperand(1))));
5259 return nullptr;
5260 }
5261 case Intrinsic::maxnum: {
5262 auto VT = getValue(I.getArgOperand(0)).getValueType();
5263 unsigned Opc =
5264 I.hasNoNaNs() && TLI.isOperationLegalOrCustom(ISD::FMAXNAN, VT)
5265 ? ISD::FMAXNAN
5266 : ISD::FMAXNUM;
5267 setValue(&I, DAG.getNode(Opc, sdl, VT,
5268 getValue(I.getArgOperand(0)),
5269 getValue(I.getArgOperand(1))));
5270 return nullptr;
5271 }
5272 case Intrinsic::copysign:
5273 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, sdl,
5274 getValue(I.getArgOperand(0)).getValueType(),
5275 getValue(I.getArgOperand(0)),
5276 getValue(I.getArgOperand(1))));
5277 return nullptr;
5278 case Intrinsic::fma:
5279 setValue(&I, DAG.getNode(ISD::FMA, sdl,
5280 getValue(I.getArgOperand(0)).getValueType(),
5281 getValue(I.getArgOperand(0)),
5282 getValue(I.getArgOperand(1)),
5283 getValue(I.getArgOperand(2))));
5284 return nullptr;
5285 case Intrinsic::experimental_constrained_fadd:
5286 case Intrinsic::experimental_constrained_fsub:
5287 case Intrinsic::experimental_constrained_fmul:
5288 case Intrinsic::experimental_constrained_fdiv:
5289 case Intrinsic::experimental_constrained_frem:
5290 visitConstrainedFPIntrinsic(I, Intrinsic);
5291 return nullptr;
5292 case Intrinsic::fmuladd: {
5293 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
5294 if (TM.Options.AllowFPOpFusion != FPOpFusion::Strict &&
5295 TLI.isFMAFasterThanFMulAndFAdd(VT)) {
5296 setValue(&I, DAG.getNode(ISD::FMA, sdl,
5297 getValue(I.getArgOperand(0)).getValueType(),
5298 getValue(I.getArgOperand(0)),
5299 getValue(I.getArgOperand(1)),
5300 getValue(I.getArgOperand(2))));
5301 } else {
5302 // TODO: Intrinsic calls should have fast-math-flags.
5303 SDValue Mul = DAG.getNode(ISD::FMUL, sdl,
5304 getValue(I.getArgOperand(0)).getValueType(),
5305 getValue(I.getArgOperand(0)),
5306 getValue(I.getArgOperand(1)));
5307 SDValue Add = DAG.getNode(ISD::FADD, sdl,
5308 getValue(I.getArgOperand(0)).getValueType(),
5309 Mul,
5310 getValue(I.getArgOperand(2)));
5311 setValue(&I, Add);
5312 }
5313 return nullptr;
5314 }
5315 case Intrinsic::convert_to_fp16:
5316 setValue(&I, DAG.getNode(ISD::BITCAST, sdl, MVT::i16,
5317 DAG.getNode(ISD::FP_ROUND, sdl, MVT::f16,
5318 getValue(I.getArgOperand(0)),
5319 DAG.getTargetConstant(0, sdl,
5320 MVT::i32))));
5321 return nullptr;
5322 case Intrinsic::convert_from_fp16:
5323 setValue(&I, DAG.getNode(ISD::FP_EXTEND, sdl,
5324 TLI.getValueType(DAG.getDataLayout(), I.getType()),
5325 DAG.getNode(ISD::BITCAST, sdl, MVT::f16,
5326 getValue(I.getArgOperand(0)))));
5327 return nullptr;
5328 case Intrinsic::pcmarker: {
5329 SDValue Tmp = getValue(I.getArgOperand(0));
5330 DAG.setRoot(DAG.getNode(ISD::PCMARKER, sdl, MVT::Other, getRoot(), Tmp));
5331 return nullptr;
5332 }
5333 case Intrinsic::readcyclecounter: {
5334 SDValue Op = getRoot();
5335 Res = DAG.getNode(ISD::READCYCLECOUNTER, sdl,
5336 DAG.getVTList(MVT::i64, MVT::Other), Op);
5337 setValue(&I, Res);
5338 DAG.setRoot(Res.getValue(1));
5339 return nullptr;
5340 }
5341 case Intrinsic::bitreverse:
5342 setValue(&I, DAG.getNode(ISD::BITREVERSE, sdl,
5343 getValue(I.getArgOperand(0)).getValueType(),
5344 getValue(I.getArgOperand(0))));
5345 return nullptr;
5346 case Intrinsic::bswap:
5347 setValue(&I, DAG.getNode(ISD::BSWAP, sdl,
5348 getValue(I.getArgOperand(0)).getValueType(),
5349 getValue(I.getArgOperand(0))));
5350 return nullptr;
5351 case Intrinsic::cttz: {
5352 SDValue Arg = getValue(I.getArgOperand(0));
5353 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
5354 EVT Ty = Arg.getValueType();
5355 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTTZ : ISD::CTTZ_ZERO_UNDEF,
5356 sdl, Ty, Arg));
5357 return nullptr;
5358 }
5359 case Intrinsic::ctlz: {
5360 SDValue Arg = getValue(I.getArgOperand(0));
5361 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
5362 EVT Ty = Arg.getValueType();
5363 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTLZ : ISD::CTLZ_ZERO_UNDEF,
5364 sdl, Ty, Arg));
5365 return nullptr;
5366 }
5367 case Intrinsic::ctpop: {
5368 SDValue Arg = getValue(I.getArgOperand(0));
5369 EVT Ty = Arg.getValueType();
5370 setValue(&I, DAG.getNode(ISD::CTPOP, sdl, Ty, Arg));
5371 return nullptr;
5372 }
5373 case Intrinsic::stacksave: {
5374 SDValue Op = getRoot();
5375 Res = DAG.getNode(
5376 ISD::STACKSAVE, sdl,
5377 DAG.getVTList(TLI.getPointerTy(DAG.getDataLayout()), MVT::Other), Op);
5378 setValue(&I, Res);
5379 DAG.setRoot(Res.getValue(1));
5380 return nullptr;
5381 }
5382 case Intrinsic::stackrestore: {
5383 Res = getValue(I.getArgOperand(0));
5384 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, sdl, MVT::Other, getRoot(), Res));
5385 return nullptr;
5386 }
5387 case Intrinsic::get_dynamic_area_offset: {
5388 SDValue Op = getRoot();
5389 EVT PtrTy = TLI.getPointerTy(DAG.getDataLayout());
5390 EVT ResTy = TLI.getValueType(DAG.getDataLayout(), I.getType());
5391 // Result type for @llvm.get.dynamic.area.offset should match PtrTy for
5392 // target.
5393 if (PtrTy != ResTy)
5394 report_fatal_error("Wrong result type for @llvm.get.dynamic.area.offset"
5395 " intrinsic!");
5396 Res = DAG.getNode(ISD::GET_DYNAMIC_AREA_OFFSET, sdl, DAG.getVTList(ResTy),
5397 Op);
5398 DAG.setRoot(Op);
5399 setValue(&I, Res);
5400 return nullptr;
5401 }
5402 case Intrinsic::stackguard: {
5403 EVT PtrTy = TLI.getPointerTy(DAG.getDataLayout());
5404 MachineFunction &MF = DAG.getMachineFunction();
5405 const Module &M = *MF.getFunction()->getParent();
5406 SDValue Chain = getRoot();
5407 if (TLI.useLoadStackGuardNode()) {
5408 Res = getLoadStackGuard(DAG, sdl, Chain);
5409 } else {
5410 const Value *Global = TLI.getSDagStackGuard(M);
5411 unsigned Align = DL->getPrefTypeAlignment(Global->getType());
5412 Res = DAG.getLoad(PtrTy, sdl, Chain, getValue(Global),
5413 MachinePointerInfo(Global, 0), Align,
5414 MachineMemOperand::MOVolatile);
5415 }
5416 DAG.setRoot(Chain);
5417 setValue(&I, Res);
5418 return nullptr;
5419 }
5420 case Intrinsic::stackprotector: {
5421 // Emit code into the DAG to store the stack guard onto the stack.
5422 MachineFunction &MF = DAG.getMachineFunction();
5423 MachineFrameInfo &MFI = MF.getFrameInfo();
5424 EVT PtrTy = TLI.getPointerTy(DAG.getDataLayout());
5425 SDValue Src, Chain = getRoot();
5426
5427 if (TLI.useLoadStackGuardNode())
5428 Src = getLoadStackGuard(DAG, sdl, Chain);
5429 else
5430 Src = getValue(I.getArgOperand(0)); // The guard's value.
5431
5432 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1));
5433
5434 int FI = FuncInfo.StaticAllocaMap[Slot];
5435 MFI.setStackProtectorIndex(FI);
5436
5437 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
5438
5439 // Store the stack protector onto the stack.
5440 Res = DAG.getStore(Chain, sdl, Src, FIN, MachinePointerInfo::getFixedStack(
5441 DAG.getMachineFunction(), FI),
5442 /* Alignment = */ 0, MachineMemOperand::MOVolatile);
5443 setValue(&I, Res);
5444 DAG.setRoot(Res);
5445 return nullptr;
5446 }
5447 case Intrinsic::objectsize: {
5448 // If we don't know by now, we're never going to know.
5449 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1));
5450
5451 assert(CI && "Non-constant type in __builtin_object_size?")((CI && "Non-constant type in __builtin_object_size?"
) ? static_cast<void> (0) : __assert_fail ("CI && \"Non-constant type in __builtin_object_size?\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 5451, __PRETTY_FUNCTION__))
;
5452
5453 SDValue Arg = getValue(I.getCalledValue());
5454 EVT Ty = Arg.getValueType();
5455
5456 if (CI->isZero())
5457 Res = DAG.getConstant(-1ULL, sdl, Ty);
5458 else
5459 Res = DAG.getConstant(0, sdl, Ty);
5460
5461 setValue(&I, Res);
5462 return nullptr;
5463 }
5464 case Intrinsic::annotation:
5465 case Intrinsic::ptr_annotation:
5466 case Intrinsic::invariant_group_barrier:
5467 // Drop the intrinsic, but forward the value
5468 setValue(&I, getValue(I.getOperand(0)));
5469 return nullptr;
5470 case Intrinsic::assume:
5471 case Intrinsic::var_annotation:
5472 // Discard annotate attributes and assumptions
5473 return nullptr;
5474
5475 case Intrinsic::init_trampoline: {
5476 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts());
5477
5478 SDValue Ops[6];
5479 Ops[0] = getRoot();
5480 Ops[1] = getValue(I.getArgOperand(0));
5481 Ops[2] = getValue(I.getArgOperand(1));
5482 Ops[3] = getValue(I.getArgOperand(2));
5483 Ops[4] = DAG.getSrcValue(I.getArgOperand(0));
5484 Ops[5] = DAG.getSrcValue(F);
5485
5486 Res = DAG.getNode(ISD::INIT_TRAMPOLINE, sdl, MVT::Other, Ops);
5487
5488 DAG.setRoot(Res);
5489 return nullptr;
5490 }
5491 case Intrinsic::adjust_trampoline: {
5492 setValue(&I, DAG.getNode(ISD::ADJUST_TRAMPOLINE, sdl,
5493 TLI.getPointerTy(DAG.getDataLayout()),
5494 getValue(I.getArgOperand(0))));
5495 return nullptr;
5496 }
5497 case Intrinsic::gcroot: {
5498 MachineFunction &MF = DAG.getMachineFunction();
5499 const Function *F = MF.getFunction();
5500 (void)F;
5501 assert(F->hasGC() &&((F->hasGC() && "only valid in functions with gc specified, enforced by Verifier"
) ? static_cast<void> (0) : __assert_fail ("F->hasGC() && \"only valid in functions with gc specified, enforced by Verifier\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 5502, __PRETTY_FUNCTION__))
5502 "only valid in functions with gc specified, enforced by Verifier")((F->hasGC() && "only valid in functions with gc specified, enforced by Verifier"
) ? static_cast<void> (0) : __assert_fail ("F->hasGC() && \"only valid in functions with gc specified, enforced by Verifier\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 5502, __PRETTY_FUNCTION__))
;
5503 assert(GFI && "implied by previous")((GFI && "implied by previous") ? static_cast<void
> (0) : __assert_fail ("GFI && \"implied by previous\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 5503, __PRETTY_FUNCTION__))
;
5504 const Value *Alloca = I.getArgOperand(0)->stripPointerCasts();
5505 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1));
5506
5507 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
5508 GFI->addStackRoot(FI->getIndex(), TypeMap);
5509 return nullptr;
5510 }
5511 case Intrinsic::gcread:
5512 case Intrinsic::gcwrite:
5513 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!")::llvm::llvm_unreachable_internal("GC failed to lower gcread/gcwrite intrinsics!"
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 5513)
;
5514 case Intrinsic::flt_rounds:
5515 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, sdl, MVT::i32));
5516 return nullptr;
5517
5518 case Intrinsic::expect: {
5519 // Just replace __builtin_expect(exp, c) with EXP.
5520 setValue(&I, getValue(I.getArgOperand(0)));
5521 return nullptr;
5522 }
5523
5524 case Intrinsic::debugtrap:
5525 case Intrinsic::trap: {
5526 StringRef TrapFuncName =
5527 I.getAttributes()
5528 .getAttribute(AttributeSet::FunctionIndex, "trap-func-name")
5529 .getValueAsString();
5530 if (TrapFuncName.empty()) {
5531 ISD::NodeType Op = (Intrinsic == Intrinsic::trap) ?
5532 ISD::TRAP : ISD::DEBUGTRAP;
5533 DAG.setRoot(DAG.getNode(Op, sdl,MVT::Other, getRoot()));
5534 return nullptr;
5535 }
5536 TargetLowering::ArgListTy Args;
5537
5538 TargetLowering::CallLoweringInfo CLI(DAG);
5539 CLI.setDebugLoc(sdl).setChain(getRoot()).setLibCallee(
5540 CallingConv::C, I.getType(),
5541 DAG.getExternalSymbol(TrapFuncName.data(),
5542 TLI.getPointerTy(DAG.getDataLayout())),
5543 std::move(Args));
5544
5545 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
5546 DAG.setRoot(Result.second);
5547 return nullptr;
5548 }
5549
5550 case Intrinsic::uadd_with_overflow:
5551 case Intrinsic::sadd_with_overflow:
5552 case Intrinsic::usub_with_overflow:
5553 case Intrinsic::ssub_with_overflow:
5554 case Intrinsic::umul_with_overflow:
5555 case Intrinsic::smul_with_overflow: {
5556 ISD::NodeType Op;
5557 switch (Intrinsic) {
5558 default: llvm_unreachable("Impossible intrinsic")::llvm::llvm_unreachable_internal("Impossible intrinsic", "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 5558)
; // Can't reach here.
5559 case Intrinsic::uadd_with_overflow: Op = ISD::UADDO; break;
5560 case Intrinsic::sadd_with_overflow: Op = ISD::SADDO; break;
5561 case Intrinsic::usub_with_overflow: Op = ISD::USUBO; break;
5562 case Intrinsic::ssub_with_overflow: Op = ISD::SSUBO; break;
5563 case Intrinsic::umul_with_overflow: Op = ISD::UMULO; break;
5564 case Intrinsic::smul_with_overflow: Op = ISD::SMULO; break;
5565 }
5566 SDValue Op1 = getValue(I.getArgOperand(0));
5567 SDValue Op2 = getValue(I.getArgOperand(1));
5568
5569 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
5570 setValue(&I, DAG.getNode(Op, sdl, VTs, Op1, Op2));
5571 return nullptr;
5572 }
5573 case Intrinsic::prefetch: {
5574 SDValue Ops[5];
5575 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
5576 Ops[0] = getRoot();
5577 Ops[1] = getValue(I.getArgOperand(0));
5578 Ops[2] = getValue(I.getArgOperand(1));
5579 Ops[3] = getValue(I.getArgOperand(2));
5580 Ops[4] = getValue(I.getArgOperand(3));
5581 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, sdl,
5582 DAG.getVTList(MVT::Other), Ops,
5583 EVT::getIntegerVT(*Context, 8),
5584 MachinePointerInfo(I.getArgOperand(0)),
5585 0, /* align */
5586 false, /* volatile */
5587 rw==0, /* read */
5588 rw==1)); /* write */
5589 return nullptr;
5590 }
5591 case Intrinsic::lifetime_start:
5592 case Intrinsic::lifetime_end: {
5593 bool IsStart = (Intrinsic == Intrinsic::lifetime_start);
5594 // Stack coloring is not enabled in O0, discard region information.
5595 if (TM.getOptLevel() == CodeGenOpt::None)
5596 return nullptr;
5597
5598 SmallVector<Value *, 4> Allocas;
5599 GetUnderlyingObjects(I.getArgOperand(1), Allocas, *DL);
5600
5601 for (SmallVectorImpl<Value*>::iterator Object = Allocas.begin(),
5602 E = Allocas.end(); Object != E; ++Object) {
5603 AllocaInst *LifetimeObject = dyn_cast_or_null<AllocaInst>(*Object);
5604
5605 // Could not find an Alloca.
5606 if (!LifetimeObject)
5607 continue;
5608
5609 // First check that the Alloca is static, otherwise it won't have a
5610 // valid frame index.
5611 auto SI = FuncInfo.StaticAllocaMap.find(LifetimeObject);
5612 if (SI == FuncInfo.StaticAllocaMap.end())
5613 return nullptr;
5614
5615 int FI = SI->second;
5616
5617 SDValue Ops[2];
5618 Ops[0] = getRoot();
5619 Ops[1] =
5620 DAG.getFrameIndex(FI, TLI.getPointerTy(DAG.getDataLayout()), true);
5621 unsigned Opcode = (IsStart ? ISD::LIFETIME_START : ISD::LIFETIME_END);
5622
5623 Res = DAG.getNode(Opcode, sdl, MVT::Other, Ops);
5624 DAG.setRoot(Res);
5625 }
5626 return nullptr;
5627 }
5628 case Intrinsic::invariant_start:
5629 // Discard region information.
5630 setValue(&I, DAG.getUNDEF(TLI.getPointerTy(DAG.getDataLayout())));
5631 return nullptr;
5632 case Intrinsic::invariant_end:
5633 // Discard region information.
5634 return nullptr;
5635 case Intrinsic::clear_cache:
5636 return TLI.getClearCacheBuiltinName();
5637 case Intrinsic::donothing:
5638 // ignore
5639 return nullptr;
5640 case Intrinsic::experimental_stackmap: {
5641 visitStackmap(I);
5642 return nullptr;
5643 }
5644 case Intrinsic::experimental_patchpoint_void:
5645 case Intrinsic::experimental_patchpoint_i64: {
5646 visitPatchpoint(&I);
5647 return nullptr;
5648 }
5649 case Intrinsic::experimental_gc_statepoint: {
5650 LowerStatepoint(ImmutableStatepoint(&I));
5651 return nullptr;
5652 }
5653 case Intrinsic::experimental_gc_result: {
5654 visitGCResult(cast<GCResultInst>(I));
5655 return nullptr;
5656 }
5657 case Intrinsic::experimental_gc_relocate: {
5658 visitGCRelocate(cast<GCRelocateInst>(I));
5659 return nullptr;
5660 }
5661 case Intrinsic::instrprof_increment:
5662 llvm_unreachable("instrprof failed to lower an increment")::llvm::llvm_unreachable_internal("instrprof failed to lower an increment"
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 5662)
;
5663 case Intrinsic::instrprof_value_profile:
5664 llvm_unreachable("instrprof failed to lower a value profiling call")::llvm::llvm_unreachable_internal("instrprof failed to lower a value profiling call"
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 5664)
;
5665 case Intrinsic::localescape: {
5666 MachineFunction &MF = DAG.getMachineFunction();
5667 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
5668
5669 // Directly emit some LOCAL_ESCAPE machine instrs. Label assignment emission
5670 // is the same on all targets.
5671 for (unsigned Idx = 0, E = I.getNumArgOperands(); Idx < E; ++Idx) {
5672 Value *Arg = I.getArgOperand(Idx)->stripPointerCasts();
5673 if (isa<ConstantPointerNull>(Arg))
5674 continue; // Skip null pointers. They represent a hole in index space.
5675 AllocaInst *Slot = cast<AllocaInst>(Arg);
5676 assert(FuncInfo.StaticAllocaMap.count(Slot) &&((FuncInfo.StaticAllocaMap.count(Slot) && "can only escape static allocas"
) ? static_cast<void> (0) : __assert_fail ("FuncInfo.StaticAllocaMap.count(Slot) && \"can only escape static allocas\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 5677, __PRETTY_FUNCTION__))
5677 "can only escape static allocas")((FuncInfo.StaticAllocaMap.count(Slot) && "can only escape static allocas"
) ? static_cast<void> (0) : __assert_fail ("FuncInfo.StaticAllocaMap.count(Slot) && \"can only escape static allocas\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 5677, __PRETTY_FUNCTION__))
;
5678 int FI = FuncInfo.StaticAllocaMap[Slot];
5679 MCSymbol *FrameAllocSym =
5680 MF.getMMI().getContext().getOrCreateFrameAllocSymbol(
5681 GlobalValue::getRealLinkageName(MF.getName()), Idx);
5682 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, dl,
5683 TII->get(TargetOpcode::LOCAL_ESCAPE))
5684 .addSym(FrameAllocSym)
5685 .addFrameIndex(FI);
5686 }
5687
5688 return nullptr;
5689 }
5690
5691 case Intrinsic::localrecover: {
5692 // i8* @llvm.localrecover(i8* %fn, i8* %fp, i32 %idx)
5693 MachineFunction &MF = DAG.getMachineFunction();
5694 MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout(), 0);
5695
5696 // Get the symbol that defines the frame offset.
5697 auto *Fn = cast<Function>(I.getArgOperand(0)->stripPointerCasts());
5698 auto *Idx = cast<ConstantInt>(I.getArgOperand(2));
5699 unsigned IdxVal = unsigned(Idx->getLimitedValue(INT_MAX2147483647));
5700 MCSymbol *FrameAllocSym =
5701 MF.getMMI().getContext().getOrCreateFrameAllocSymbol(
5702 GlobalValue::getRealLinkageName(Fn->getName()), IdxVal);
5703
5704 // Create a MCSymbol for the label to avoid any target lowering
5705 // that would make this PC relative.
5706 SDValue OffsetSym = DAG.getMCSymbol(FrameAllocSym, PtrVT);
5707 SDValue OffsetVal =
5708 DAG.getNode(ISD::LOCAL_RECOVER, sdl, PtrVT, OffsetSym);
5709
5710 // Add the offset to the FP.
5711 Value *FP = I.getArgOperand(1);
5712 SDValue FPVal = getValue(FP);
5713 SDValue Add = DAG.getNode(ISD::ADD, sdl, PtrVT, FPVal, OffsetVal);
5714 setValue(&I, Add);
5715
5716 return nullptr;
5717 }
5718
5719 case Intrinsic::eh_exceptionpointer:
5720 case Intrinsic::eh_exceptioncode: {
5721 // Get the exception pointer vreg, copy from it, and resize it to fit.
5722 const auto *CPI = cast<CatchPadInst>(I.getArgOperand(0));
5723 MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout());
5724 const TargetRegisterClass *PtrRC = TLI.getRegClassFor(PtrVT);
5725 unsigned VReg = FuncInfo.getCatchPadExceptionPointerVReg(CPI, PtrRC);
5726 SDValue N =
5727 DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(), VReg, PtrVT);
5728 if (Intrinsic == Intrinsic::eh_exceptioncode)
5729 N = DAG.getZExtOrTrunc(N, getCurSDLoc(), MVT::i32);
5730 setValue(&I, N);
5731 return nullptr;
5732 }
5733
5734 case Intrinsic::experimental_deoptimize:
5735 LowerDeoptimizeCall(&I);
5736 return nullptr;
5737 }
5738}
5739
5740void SelectionDAGBuilder::visitConstrainedFPIntrinsic(const CallInst &I,
5741 unsigned Intrinsic) {
5742 SDLoc sdl = getCurSDLoc();
5743 unsigned Opcode;
5744 switch (Intrinsic) {
5745 default: llvm_unreachable("Impossible intrinsic")::llvm::llvm_unreachable_internal("Impossible intrinsic", "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 5745)
; // Can't reach here.
5746 case Intrinsic::experimental_constrained_fadd:
5747 Opcode = ISD::STRICT_FADD;
5748 break;
5749 case Intrinsic::experimental_constrained_fsub:
5750 Opcode = ISD::STRICT_FSUB;
5751 break;
5752 case Intrinsic::experimental_constrained_fmul:
5753 Opcode = ISD::STRICT_FMUL;
5754 break;
5755 case Intrinsic::experimental_constrained_fdiv:
5756 Opcode = ISD::STRICT_FDIV;
5757 break;
5758 case Intrinsic::experimental_constrained_frem:
5759 Opcode = ISD::STRICT_FREM;
5760 break;
5761 }
5762 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5763 SDValue Chain = getRoot();
5764 SDValue Ops[3] = { Chain, getValue(I.getArgOperand(0)),
5765 getValue(I.getArgOperand(1)) };
5766 SmallVector<EVT, 4> ValueVTs;
5767 ComputeValueVTs(TLI, DAG.getDataLayout(), I.getType(), ValueVTs);
5768 ValueVTs.push_back(MVT::Other); // Out chain
5769
5770 SDVTList VTs = DAG.getVTList(ValueVTs);
5771 SDValue Result = DAG.getNode(Opcode, sdl, VTs, Ops);
5772
5773 assert(Result.getNode()->getNumValues() == 2)((Result.getNode()->getNumValues() == 2) ? static_cast<
void> (0) : __assert_fail ("Result.getNode()->getNumValues() == 2"
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 5773, __PRETTY_FUNCTION__))
;
5774 SDValue OutChain = Result.getValue(1);
5775 DAG.setRoot(OutChain);
5776 SDValue FPResult = Result.getValue(0);
5777 setValue(&I, FPResult);
5778}
5779
5780std::pair<SDValue, SDValue>
5781SelectionDAGBuilder::lowerInvokable(TargetLowering::CallLoweringInfo &CLI,
5782 const BasicBlock *EHPadBB) {
5783 MachineFunction &MF = DAG.getMachineFunction();
5784 MachineModuleInfo &MMI = MF.getMMI();
5785 MCSymbol *BeginLabel = nullptr;
5786
5787 if (EHPadBB) {
5788 // Insert a label before the invoke call to mark the try range. This can be
5789 // used to detect deletion of the invoke via the MachineModuleInfo.
5790 BeginLabel = MMI.getContext().createTempSymbol();
5791
5792 // For SjLj, keep track of which landing pads go with which invokes
5793 // so as to maintain the ordering of pads in the LSDA.
5794 unsigned CallSiteIndex = MMI.getCurrentCallSite();
5795 if (CallSiteIndex) {
5796 MF.setCallSiteBeginLabel(BeginLabel, CallSiteIndex);
5797 LPadToCallSiteMap[FuncInfo.MBBMap[EHPadBB]].push_back(CallSiteIndex);
5798
5799 // Now that the call site is handled, stop tracking it.
5800 MMI.setCurrentCallSite(0);
5801 }
5802
5803 // Both PendingLoads and PendingExports must be flushed here;
5804 // this call might not return.
5805 (void)getRoot();
5806 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getControlRoot(), BeginLabel));
5807
5808 CLI.setChain(getRoot());
5809 }
5810 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5811 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
5812
5813 assert((CLI.IsTailCall || Result.second.getNode()) &&(((CLI.IsTailCall || Result.second.getNode()) && "Non-null chain expected with non-tail call!"
) ? static_cast<void> (0) : __assert_fail ("(CLI.IsTailCall || Result.second.getNode()) && \"Non-null chain expected with non-tail call!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 5814, __PRETTY_FUNCTION__))
5814 "Non-null chain expected with non-tail call!")(((CLI.IsTailCall || Result.second.getNode()) && "Non-null chain expected with non-tail call!"
) ? static_cast<void> (0) : __assert_fail ("(CLI.IsTailCall || Result.second.getNode()) && \"Non-null chain expected with non-tail call!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 5814, __PRETTY_FUNCTION__))
;
5815 assert((Result.second.getNode() || !Result.first.getNode()) &&(((Result.second.getNode() || !Result.first.getNode()) &&
"Null value expected with tail call!") ? static_cast<void
> (0) : __assert_fail ("(Result.second.getNode() || !Result.first.getNode()) && \"Null value expected with tail call!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 5816, __PRETTY_FUNCTION__))
5816 "Null value expected with tail call!")(((Result.second.getNode() || !Result.first.getNode()) &&
"Null value expected with tail call!") ? static_cast<void
> (0) : __assert_fail ("(Result.second.getNode() || !Result.first.getNode()) && \"Null value expected with tail call!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 5816, __PRETTY_FUNCTION__))
;
5817
5818 if (!Result.second.getNode()) {
5819 // As a special case, a null chain means that a tail call has been emitted
5820 // and the DAG root is already updated.
5821 HasTailCall = true;
5822
5823 // Since there's no actual continuation from this block, nothing can be
5824 // relying on us setting vregs for them.
5825 PendingExports.clear();
5826 } else {
5827 DAG.setRoot(Result.second);
5828 }
5829
5830 if (EHPadBB) {
5831 // Insert a label at the end of the invoke call to mark the try range. This
5832 // can be used to detect deletion of the invoke via the MachineModuleInfo.
5833 MCSymbol *EndLabel = MMI.getContext().createTempSymbol();
5834 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getRoot(), EndLabel));
5835
5836 // Inform MachineModuleInfo of range.
5837 if (MF.hasEHFunclets()) {
5838 assert(CLI.CS)((CLI.CS) ? static_cast<void> (0) : __assert_fail ("CLI.CS"
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 5838, __PRETTY_FUNCTION__))
;
5839 WinEHFuncInfo *EHInfo = DAG.getMachineFunction().getWinEHFuncInfo();
5840 EHInfo->addIPToStateRange(cast<InvokeInst>(CLI.CS->getInstruction()),
5841 BeginLabel, EndLabel);
5842 } else {
5843 MF.addInvoke(FuncInfo.MBBMap[EHPadBB], BeginLabel, EndLabel);
5844 }
5845 }
5846
5847 return Result;
5848}
5849
5850void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee,
5851 bool isTailCall,
5852 const BasicBlock *EHPadBB) {
5853 auto &DL = DAG.getDataLayout();
5854 FunctionType *FTy = CS.getFunctionType();
5855 Type *RetTy = CS.getType();
5856
5857 TargetLowering::ArgListTy Args;
5858 Args.reserve(CS.arg_size());
5859
5860 const Value *SwiftErrorVal = nullptr;
5861 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5862
5863 // We can't tail call inside a function with a swifterror argument. Lowering
5864 // does not support this yet. It would have to move into the swifterror
5865 // register before the call.
5866 auto *Caller = CS.getInstruction()->getParent()->getParent();
5867 if (TLI.supportSwiftError() &&
5868 Caller->getAttributes().hasAttrSomewhere(Attribute::SwiftError))
5869 isTailCall = false;
5870
5871 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
5872 i != e; ++i) {
5873 TargetLowering::ArgListEntry Entry;
5874 const Value *V = *i;
5875
5876 // Skip empty types
5877 if (V->getType()->isEmptyTy())
5878 continue;
5879
5880 SDValue ArgNode = getValue(V);
5881 Entry.Node = ArgNode; Entry.Ty = V->getType();
5882
5883 // Skip the first return-type Attribute to get to params.
5884 Entry.setAttributes(&CS, i - CS.arg_begin() + 1);
5885
5886 // Use swifterror virtual register as input to the call.
5887 if (Entry.IsSwiftError && TLI.supportSwiftError()) {
5888 SwiftErrorVal = V;
5889 // We find the virtual register for the actual swifterror argument.
5890 // Instead of using the Value, we use the virtual register instead.
5891 Entry.Node =
5892 DAG.getRegister(FuncInfo.getOrCreateSwiftErrorVReg(FuncInfo.MBB, V),
5893 EVT(TLI.getPointerTy(DL)));
5894 }
5895
5896 Args.push_back(Entry);
5897
5898 // If we have an explicit sret argument that is an Instruction, (i.e., it
5899 // might point to function-local memory), we can't meaningfully tail-call.
5900 if (Entry.IsSRet && isa<Instruction>(V))
5901 isTailCall = false;
5902 }
5903
5904 // Check if target-independent constraints permit a tail call here.
5905 // Target-dependent constraints are checked within TLI->LowerCallTo.
5906 if (isTailCall && !isInTailCallPosition(CS, DAG.getTarget()))
5907 isTailCall = false;
5908
5909 // Disable tail calls if there is an swifterror argument. Targets have not
5910 // been updated to support tail calls.
5911 if (TLI.supportSwiftError() && SwiftErrorVal)
5912 isTailCall = false;
5913
5914 TargetLowering::CallLoweringInfo CLI(DAG);
5915 CLI.setDebugLoc(getCurSDLoc())
5916 .setChain(getRoot())
5917 .setCallee(RetTy, FTy, Callee, std::move(Args), CS)
5918 .setTailCall(isTailCall)
5919 .setConvergent(CS.isConvergent());
5920 std::pair<SDValue, SDValue> Result = lowerInvokable(CLI, EHPadBB);
5921
5922 if (Result.first.getNode()) {
5923 const Instruction *Inst = CS.getInstruction();
5924 Result.first = lowerRangeToAssertZExt(DAG, *Inst, Result.first);
5925 setValue(Inst, Result.first);
5926 }
5927
5928 // The last element of CLI.InVals has the SDValue for swifterror return.
5929 // Here we copy it to a virtual register and update SwiftErrorMap for
5930 // book-keeping.
5931 if (SwiftErrorVal && TLI.supportSwiftError()) {
5932 // Get the last element of InVals.
5933 SDValue Src = CLI.InVals.back();
5934 const TargetRegisterClass *RC = TLI.getRegClassFor(TLI.getPointerTy(DL));
5935 unsigned VReg = FuncInfo.MF->getRegInfo().createVirtualRegister(RC);
5936 SDValue CopyNode = CLI.DAG.getCopyToReg(Result.second, CLI.DL, VReg, Src);
5937 // We update the virtual register for the actual swifterror argument.
5938 FuncInfo.setCurrentSwiftErrorVReg(FuncInfo.MBB, SwiftErrorVal, VReg);
5939 DAG.setRoot(CopyNode);
5940 }
5941}
5942
5943/// Return true if it only matters that the value is equal or not-equal to zero.
5944static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) {
5945 for (const User *U : V->users()) {
5946 if (const ICmpInst *IC = dyn_cast<ICmpInst>(U))
5947 if (IC->isEquality())
5948 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1)))
5949 if (C->isNullValue())
5950 continue;
5951 // Unknown instruction.
5952 return false;
5953 }
5954 return true;
5955}
5956
5957static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT,
5958 Type *LoadTy,
5959 SelectionDAGBuilder &Builder) {
5960
5961 // Check to see if this load can be trivially constant folded, e.g. if the
5962 // input is from a string literal.
5963 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) {
5964 // Cast pointer to the type we really want to load.
5965 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput),
5966 PointerType::getUnqual(LoadTy));
5967
5968 if (const Constant *LoadCst = ConstantFoldLoadFromConstPtr(
5969 const_cast<Constant *>(LoadInput), LoadTy, *Builder.DL))
5970 return Builder.getValue(LoadCst);
5971 }
5972
5973 // Otherwise, we have to emit the load. If the pointer is to unfoldable but
5974 // still constant memory, the input chain can be the entry node.
5975 SDValue Root;
5976 bool ConstantMemory = false;
5977
5978 // Do not serialize (non-volatile) loads of constant memory with anything.
5979 if (Builder.AA->pointsToConstantMemory(PtrVal)) {
5980 Root = Builder.DAG.getEntryNode();
5981 ConstantMemory = true;
5982 } else {
5983 // Do not serialize non-volatile loads against each other.
5984 Root = Builder.DAG.getRoot();
5985 }
5986
5987 SDValue Ptr = Builder.getValue(PtrVal);
5988 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurSDLoc(), Root,
5989 Ptr, MachinePointerInfo(PtrVal),
5990 /* Alignment = */ 1);
5991
5992 if (!ConstantMemory)
5993 Builder.PendingLoads.push_back(LoadVal.getValue(1));
5994 return LoadVal;
5995}
5996
5997/// Record the value for an instruction that produces an integer result,
5998/// converting the type where necessary.
5999void SelectionDAGBuilder::processIntegerCallValue(const Instruction &I,
6000 SDValue Value,
6001 bool IsSigned) {
6002 EVT VT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
6003 I.getType(), true);
6004 if (IsSigned)
6005 Value = DAG.getSExtOrTrunc(Value, getCurSDLoc(), VT);
6006 else
6007 Value = DAG.getZExtOrTrunc(Value, getCurSDLoc(), VT);
6008 setValue(&I, Value);
6009}
6010
6011/// See if we can lower a memcmp call into an optimized form. If so, return
6012/// true and lower it. Otherwise return false, and it will be lowered like a
6013/// normal call.
6014/// The caller already checked that \p I calls the appropriate LibFunc with a
6015/// correct prototype.
6016bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) {
6017 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1);
6018 const Value *Size = I.getArgOperand(2);
6019 const ConstantInt *CSize = dyn_cast<ConstantInt>(Size);
6020 if (CSize && CSize->getZExtValue() == 0) {
6021 EVT CallVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
6022 I.getType(), true);
6023 setValue(&I, DAG.getConstant(0, getCurSDLoc(), CallVT));
6024 return true;
6025 }
6026
6027 const SelectionDAGTargetInfo &TSI = DAG.getSelectionDAGInfo();
6028 std::pair<SDValue, SDValue> Res = TSI.EmitTargetCodeForMemcmp(
6029 DAG, getCurSDLoc(), DAG.getRoot(), getValue(LHS), getValue(RHS),
6030 getValue(Size), MachinePointerInfo(LHS), MachinePointerInfo(RHS));
6031 if (Res.first.getNode()) {
6032 processIntegerCallValue(I, Res.first, true);
6033 PendingLoads.push_back(Res.second);
6034 return true;
6035 }
6036
6037 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0
6038 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0
6039 if (!CSize || !IsOnlyUsedInZeroEqualityComparison(&I))
6040 return false;
6041
6042 MVT LoadVT;
6043 Type *LoadTy;
6044 switch (CSize->getZExtValue()) {
6045 default:
6046 return false;
6047 case 2:
6048 LoadVT = MVT::i16;
6049 LoadTy = Type::getInt16Ty(CSize->getContext());
6050 break;
6051 case 4:
6052 LoadVT = MVT::i32;
6053 LoadTy = Type::getInt32Ty(CSize->getContext());
6054 break;
6055 case 8:
6056 LoadVT = MVT::i64;
6057 LoadTy = Type::getInt64Ty(CSize->getContext());
6058 break;
6059 /*
6060 case 16:
6061 LoadVT = MVT::v4i32;
6062 LoadTy = Type::getInt32Ty(CSize->getContext());
6063 LoadTy = VectorType::get(LoadTy, 4);
6064 break;
6065 */
6066 }
6067
6068 // This turns into unaligned loads. We only do this if the target natively
6069 // supports the MVT we'll be loading or if it is small enough (<= 4) that
6070 // we'll only produce a small number of byte loads.
6071
6072 // Require that we can find a legal MVT, and only do this if the target
6073 // supports unaligned loads of that type. Expanding into byte loads would
6074 // bloat the code.
6075 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6076 if (CSize->getZExtValue() > 4) {
6077 unsigned DstAS = LHS->getType()->getPointerAddressSpace();
6078 unsigned SrcAS = RHS->getType()->getPointerAddressSpace();
6079 // TODO: Handle 5 byte compare as 4-byte + 1 byte.
6080 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads.
6081 // TODO: Check alignment of src and dest ptrs.
6082 if (!TLI.isTypeLegal(LoadVT) ||
6083 !TLI.allowsMisalignedMemoryAccesses(LoadVT, SrcAS) ||
6084 !TLI.allowsMisalignedMemoryAccesses(LoadVT, DstAS))
6085 return false;
6086 }
6087
6088 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this);
6089 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this);
6090 SDValue SetCC =
6091 DAG.getSetCC(getCurSDLoc(), MVT::i1, LHSVal, RHSVal, ISD::SETNE);
6092 processIntegerCallValue(I, SetCC, false);
6093 return true;
6094}
6095
6096/// See if we can lower a memchr call into an optimized form. If so, return
6097/// true and lower it. Otherwise return false, and it will be lowered like a
6098/// normal call.
6099/// The caller already checked that \p I calls the appropriate LibFunc with a
6100/// correct prototype.
6101bool SelectionDAGBuilder::visitMemChrCall(const CallInst &I) {
6102 const Value *Src = I.getArgOperand(0);
6103 const Value *Char = I.getArgOperand(1);
6104 const Value *Length = I.getArgOperand(2);
6105
6106 const SelectionDAGTargetInfo &TSI = DAG.getSelectionDAGInfo();
6107 std::pair<SDValue, SDValue> Res =
6108 TSI.EmitTargetCodeForMemchr(DAG, getCurSDLoc(), DAG.getRoot(),
6109 getValue(Src), getValue(Char), getValue(Length),
6110 MachinePointerInfo(Src));
6111 if (Res.first.getNode()) {
6112 setValue(&I, Res.first);
6113 PendingLoads.push_back(Res.second);
6114 return true;
6115 }
6116
6117 return false;
6118}
6119
6120/// See if we can lower a mempcpy call into an optimized form. If so, return
6121/// true and lower it. Otherwise return false, and it will be lowered like a
6122/// normal call.
6123/// The caller already checked that \p I calls the appropriate LibFunc with a
6124/// correct prototype.
6125bool SelectionDAGBuilder::visitMemPCpyCall(const CallInst &I) {
6126 SDValue Dst = getValue(I.getArgOperand(0));
6127 SDValue Src = getValue(I.getArgOperand(1));
6128 SDValue Size = getValue(I.getArgOperand(2));
6129
6130 unsigned DstAlign = DAG.InferPtrAlignment(Dst);
6131 unsigned SrcAlign = DAG.InferPtrAlignment(Src);
6132 unsigned Align = std::min(DstAlign, SrcAlign);
6133 if (Align == 0) // Alignment of one or both could not be inferred.
6134 Align = 1; // 0 and 1 both specify no alignment, but 0 is reserved.
6135
6136 bool isVol = false;
6137 SDLoc sdl = getCurSDLoc();
6138
6139 // In the mempcpy context we need to pass in a false value for isTailCall
6140 // because the return pointer needs to be adjusted by the size of
6141 // the copied memory.
6142 SDValue MC = DAG.getMemcpy(getRoot(), sdl, Dst, Src, Size, Align, isVol,
6143 false, /*isTailCall=*/false,
6144 MachinePointerInfo(I.getArgOperand(0)),
6145 MachinePointerInfo(I.getArgOperand(1)));
6146 assert(MC.getNode() != nullptr &&((MC.getNode() != nullptr && "** memcpy should not be lowered as TailCall in mempcpy context **"
) ? static_cast<void> (0) : __assert_fail ("MC.getNode() != nullptr && \"** memcpy should not be lowered as TailCall in mempcpy context **\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 6147, __PRETTY_FUNCTION__))
6147 "** memcpy should not be lowered as TailCall in mempcpy context **")((MC.getNode() != nullptr && "** memcpy should not be lowered as TailCall in mempcpy context **"
) ? static_cast<void> (0) : __assert_fail ("MC.getNode() != nullptr && \"** memcpy should not be lowered as TailCall in mempcpy context **\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 6147, __PRETTY_FUNCTION__))
;
6148 DAG.setRoot(MC);
6149
6150 // Check if Size needs to be truncated or extended.
6151 Size = DAG.getSExtOrTrunc(Size, sdl, Dst.getValueType());
6152
6153 // Adjust return pointer to point just past the last dst byte.
6154 SDValue DstPlusSize = DAG.getNode(ISD::ADD, sdl, Dst.getValueType(),
6155 Dst, Size);
6156 setValue(&I, DstPlusSize);
6157 return true;
6158}
6159
6160/// See if we can lower a strcpy call into an optimized form. If so, return
6161/// true and lower it, otherwise return false and it will be lowered like a
6162/// normal call.
6163/// The caller already checked that \p I calls the appropriate LibFunc with a
6164/// correct prototype.
6165bool SelectionDAGBuilder::visitStrCpyCall(const CallInst &I, bool isStpcpy) {
6166 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
6167
6168 const SelectionDAGTargetInfo &TSI = DAG.getSelectionDAGInfo();
6169 std::pair<SDValue, SDValue> Res =
6170 TSI.EmitTargetCodeForStrcpy(DAG, getCurSDLoc(), getRoot(),
6171 getValue(Arg0), getValue(Arg1),
6172 MachinePointerInfo(Arg0),
6173 MachinePointerInfo(Arg1), isStpcpy);
6174 if (Res.first.getNode()) {
6175 setValue(&I, Res.first);
6176 DAG.setRoot(Res.second);
6177 return true;
6178 }
6179
6180 return false;
6181}
6182
6183/// See if we can lower a strcmp call into an optimized form. If so, return
6184/// true and lower it, otherwise return false and it will be lowered like a
6185/// normal call.
6186/// The caller already checked that \p I calls the appropriate LibFunc with a
6187/// correct prototype.
6188bool SelectionDAGBuilder::visitStrCmpCall(const CallInst &I) {
6189 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
6190
6191 const SelectionDAGTargetInfo &TSI = DAG.getSelectionDAGInfo();
6192 std::pair<SDValue, SDValue> Res =
6193 TSI.EmitTargetCodeForStrcmp(DAG, getCurSDLoc(), DAG.getRoot(),
6194 getValue(Arg0), getValue(Arg1),
6195 MachinePointerInfo(Arg0),
6196 MachinePointerInfo(Arg1));
6197 if (Res.first.getNode()) {
6198 processIntegerCallValue(I, Res.first, true);
6199 PendingLoads.push_back(Res.second);
6200 return true;
6201 }
6202
6203 return false;
6204}
6205
6206/// See if we can lower a strlen call into an optimized form. If so, return
6207/// true and lower it, otherwise return false and it will be lowered like a
6208/// normal call.
6209/// The caller already checked that \p I calls the appropriate LibFunc with a
6210/// correct prototype.
6211bool SelectionDAGBuilder::visitStrLenCall(const CallInst &I) {
6212 const Value *Arg0 = I.getArgOperand(0);
6213
6214 const SelectionDAGTargetInfo &TSI = DAG.getSelectionDAGInfo();
6215 std::pair<SDValue, SDValue> Res =
6216 TSI.EmitTargetCodeForStrlen(DAG, getCurSDLoc(), DAG.getRoot(),
6217 getValue(Arg0), MachinePointerInfo(Arg0));
6218 if (Res.first.getNode()) {
6219 processIntegerCallValue(I, Res.first, false);
6220 PendingLoads.push_back(Res.second);
6221 return true;
6222 }
6223
6224 return false;
6225}
6226
6227/// See if we can lower a strnlen call into an optimized form. If so, return
6228/// true and lower it, otherwise return false and it will be lowered like a
6229/// normal call.
6230/// The caller already checked that \p I calls the appropriate LibFunc with a
6231/// correct prototype.
6232bool SelectionDAGBuilder::visitStrNLenCall(const CallInst &I) {
6233 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
6234
6235 const SelectionDAGTargetInfo &TSI = DAG.getSelectionDAGInfo();
6236 std::pair<SDValue, SDValue> Res =
6237 TSI.EmitTargetCodeForStrnlen(DAG, getCurSDLoc(), DAG.getRoot(),
6238 getValue(Arg0), getValue(Arg1),
6239 MachinePointerInfo(Arg0));
6240 if (Res.first.getNode()) {
6241 processIntegerCallValue(I, Res.first, false);
6242 PendingLoads.push_back(Res.second);
6243 return true;
6244 }
6245
6246 return false;
6247}
6248
6249/// See if we can lower a unary floating-point operation into an SDNode with
6250/// the specified Opcode. If so, return true and lower it, otherwise return
6251/// false and it will be lowered like a normal call.
6252/// The caller already checked that \p I calls the appropriate LibFunc with a
6253/// correct prototype.
6254bool SelectionDAGBuilder::visitUnaryFloatCall(const CallInst &I,
6255 unsigned Opcode) {
6256 // We already checked this call's prototype; verify it doesn't modify errno.
6257 if (!I.onlyReadsMemory())
6258 return false;
6259
6260 SDValue Tmp = getValue(I.getArgOperand(0));
6261 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), Tmp.getValueType(), Tmp));
6262 return true;
6263}
6264
6265/// See if we can lower a binary floating-point operation into an SDNode with
6266/// the specified Opcode. If so, return true and lower it. Otherwise return
6267/// false, and it will be lowered like a normal call.
6268/// The caller already checked that \p I calls the appropriate LibFunc with a
6269/// correct prototype.
6270bool SelectionDAGBuilder::visitBinaryFloatCall(const CallInst &I,
6271 unsigned Opcode) {
6272 // We already checked this call's prototype; verify it doesn't modify errno.
6273 if (!I.onlyReadsMemory())
6274 return false;
6275
6276 SDValue Tmp0 = getValue(I.getArgOperand(0));
6277 SDValue Tmp1 = getValue(I.getArgOperand(1));
6278 EVT VT = Tmp0.getValueType();
6279 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), VT, Tmp0, Tmp1));
6280 return true;
6281}
6282
6283void SelectionDAGBuilder::visitCall(const CallInst &I) {
6284 // Handle inline assembly differently.
6285 if (isa<InlineAsm>(I.getCalledValue())) {
6286 visitInlineAsm(&I);
6287 return;
6288 }
6289
6290 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
6291 computeUsesVAFloatArgument(I, MMI);
6292
6293 const char *RenameFn = nullptr;
6294 if (Function *F = I.getCalledFunction()) {
6295 if (F->isDeclaration()) {
6296 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) {
6297 if (unsigned IID = II->getIntrinsicID(F)) {
6298 RenameFn = visitIntrinsicCall(I, IID);
6299 if (!RenameFn)
6300 return;
6301 }
6302 }
6303 if (Intrinsic::ID IID = F->getIntrinsicID()) {
6304 RenameFn = visitIntrinsicCall(I, IID);
6305 if (!RenameFn)
6306 return;
6307 }
6308 }
6309
6310 // Check for well-known libc/libm calls. If the function is internal, it
6311 // can't be a library call. Don't do the check if marked as nobuiltin for
6312 // some reason.
6313 LibFunc Func;
6314 if (!I.isNoBuiltin() && !F->hasLocalLinkage() && F->hasName() &&
6315 LibInfo->getLibFunc(*F, Func) &&
6316 LibInfo->hasOptimizedCodeGen(Func)) {
6317 switch (Func) {
6318 default: break;
6319 case LibFunc_copysign:
6320 case LibFunc_copysignf:
6321 case LibFunc_copysignl:
6322 // We already checked this call's prototype; verify it doesn't modify
6323 // errno.
6324 if (I.onlyReadsMemory()) {
6325 SDValue LHS = getValue(I.getArgOperand(0));
6326 SDValue RHS = getValue(I.getArgOperand(1));
6327 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurSDLoc(),
6328 LHS.getValueType(), LHS, RHS));
6329 return;
6330 }
6331 break;
6332 case LibFunc_fabs:
6333 case LibFunc_fabsf:
6334 case LibFunc_fabsl:
6335 if (visitUnaryFloatCall(I, ISD::FABS))
6336 return;
6337 break;
6338 case LibFunc_fmin:
6339 case LibFunc_fminf:
6340 case LibFunc_fminl:
6341 if (visitBinaryFloatCall(I, ISD::FMINNUM))
6342 return;
6343 break;
6344 case LibFunc_fmax:
6345 case LibFunc_fmaxf:
6346 case LibFunc_fmaxl:
6347 if (visitBinaryFloatCall(I, ISD::FMAXNUM))
6348 return;
6349 break;
6350 case LibFunc_sin:
6351 case LibFunc_sinf:
6352 case LibFunc_sinl:
6353 if (visitUnaryFloatCall(I, ISD::FSIN))
6354 return;
6355 break;
6356 case LibFunc_cos:
6357 case LibFunc_cosf:
6358 case LibFunc_cosl:
6359 if (visitUnaryFloatCall(I, ISD::FCOS))
6360 return;
6361 break;
6362 case LibFunc_sqrt:
6363 case LibFunc_sqrtf:
6364 case LibFunc_sqrtl:
6365 case LibFunc_sqrt_finite:
6366 case LibFunc_sqrtf_finite:
6367 case LibFunc_sqrtl_finite:
6368 if (visitUnaryFloatCall(I, ISD::FSQRT))
6369 return;
6370 break;
6371 case LibFunc_floor:
6372 case LibFunc_floorf:
6373 case LibFunc_floorl:
6374 if (visitUnaryFloatCall(I, ISD::FFLOOR))
6375 return;
6376 break;
6377 case LibFunc_nearbyint:
6378 case LibFunc_nearbyintf:
6379 case LibFunc_nearbyintl:
6380 if (visitUnaryFloatCall(I, ISD::FNEARBYINT))
6381 return;
6382 break;
6383 case LibFunc_ceil:
6384 case LibFunc_ceilf:
6385 case LibFunc_ceill:
6386 if (visitUnaryFloatCall(I, ISD::FCEIL))
6387 return;
6388 break;
6389 case LibFunc_rint:
6390 case LibFunc_rintf:
6391 case LibFunc_rintl:
6392 if (visitUnaryFloatCall(I, ISD::FRINT))
6393 return;
6394 break;
6395 case LibFunc_round:
6396 case LibFunc_roundf:
6397 case LibFunc_roundl:
6398 if (visitUnaryFloatCall(I, ISD::FROUND))
6399 return;
6400 break;
6401 case LibFunc_trunc:
6402 case LibFunc_truncf:
6403 case LibFunc_truncl:
6404 if (visitUnaryFloatCall(I, ISD::FTRUNC))
6405 return;
6406 break;
6407 case LibFunc_log2:
6408 case LibFunc_log2f:
6409 case LibFunc_log2l:
6410 if (visitUnaryFloatCall(I, ISD::FLOG2))
6411 return;
6412 break;
6413 case LibFunc_exp2:
6414 case LibFunc_exp2f:
6415 case LibFunc_exp2l:
6416 if (visitUnaryFloatCall(I, ISD::FEXP2))
6417 return;
6418 break;
6419 case LibFunc_memcmp:
6420 if (visitMemCmpCall(I))
6421 return;
6422 break;
6423 case LibFunc_mempcpy:
6424 if (visitMemPCpyCall(I))
6425 return;
6426 break;
6427 case LibFunc_memchr:
6428 if (visitMemChrCall(I))
6429 return;
6430 break;
6431 case LibFunc_strcpy:
6432 if (visitStrCpyCall(I, false))
6433 return;
6434 break;
6435 case LibFunc_stpcpy:
6436 if (visitStrCpyCall(I, true))
6437 return;
6438 break;
6439 case LibFunc_strcmp:
6440 if (visitStrCmpCall(I))
6441 return;
6442 break;
6443 case LibFunc_strlen:
6444 if (visitStrLenCall(I))
6445 return;
6446 break;
6447 case LibFunc_strnlen:
6448 if (visitStrNLenCall(I))
6449 return;
6450 break;
6451 }
6452 }
6453 }
6454
6455 SDValue Callee;
6456 if (!RenameFn)
6457 Callee = getValue(I.getCalledValue());
6458 else
6459 Callee = DAG.getExternalSymbol(
6460 RenameFn,
6461 DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout()));
6462
6463 // Deopt bundles are lowered in LowerCallSiteWithDeoptBundle, and we don't
6464 // have to do anything here to lower funclet bundles.
6465 assert(!I.hasOperandBundlesOtherThan(((!I.hasOperandBundlesOtherThan( {LLVMContext::OB_deopt, LLVMContext
::OB_funclet}) && "Cannot lower calls with arbitrary operand bundles!"
) ? static_cast<void> (0) : __assert_fail ("!I.hasOperandBundlesOtherThan( {LLVMContext::OB_deopt, LLVMContext::OB_funclet}) && \"Cannot lower calls with arbitrary operand bundles!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 6467, __PRETTY_FUNCTION__))
6466 {LLVMContext::OB_deopt, LLVMContext::OB_funclet}) &&((!I.hasOperandBundlesOtherThan( {LLVMContext::OB_deopt, LLVMContext
::OB_funclet}) && "Cannot lower calls with arbitrary operand bundles!"
) ? static_cast<void> (0) : __assert_fail ("!I.hasOperandBundlesOtherThan( {LLVMContext::OB_deopt, LLVMContext::OB_funclet}) && \"Cannot lower calls with arbitrary operand bundles!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 6467, __PRETTY_FUNCTION__))
6467 "Cannot lower calls with arbitrary operand bundles!")((!I.hasOperandBundlesOtherThan( {LLVMContext::OB_deopt, LLVMContext
::OB_funclet}) && "Cannot lower calls with arbitrary operand bundles!"
) ? static_cast<void> (0) : __assert_fail ("!I.hasOperandBundlesOtherThan( {LLVMContext::OB_deopt, LLVMContext::OB_funclet}) && \"Cannot lower calls with arbitrary operand bundles!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 6467, __PRETTY_FUNCTION__))
;
6468
6469 if (I.countOperandBundlesOfType(LLVMContext::OB_deopt))
6470 LowerCallSiteWithDeoptBundle(&I, Callee, nullptr);
6471 else
6472 // Check if we can potentially perform a tail call. More detailed checking
6473 // is be done within LowerCallTo, after more information about the call is
6474 // known.
6475 LowerCallTo(&I, Callee, I.isTailCall());
6476}
6477
6478namespace {
6479
6480/// AsmOperandInfo - This contains information for each constraint that we are
6481/// lowering.
6482class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
6483public:
6484 /// CallOperand - If this is the result output operand or a clobber
6485 /// this is null, otherwise it is the incoming operand to the CallInst.
6486 /// This gets modified as the asm is processed.
6487 SDValue CallOperand;
6488
6489 /// AssignedRegs - If this is a register or register class operand, this
6490 /// contains the set of register corresponding to the operand.
6491 RegsForValue AssignedRegs;
6492
6493 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info)
6494 : TargetLowering::AsmOperandInfo(info), CallOperand(nullptr,0) {
6495 }
6496
6497 /// Whether or not this operand accesses memory
6498 bool hasMemory(const TargetLowering &TLI) const {
6499 // Indirect operand accesses access memory.
6500 if (isIndirect)
6501 return true;
6502
6503 for (const auto &Code : Codes)
6504 if (TLI.getConstraintType(Code) == TargetLowering::C_Memory)
6505 return true;
6506
6507 return false;
6508 }
6509
6510 /// getCallOperandValEVT - Return the EVT of the Value* that this operand
6511 /// corresponds to. If there is no Value* for this operand, it returns
6512 /// MVT::Other.
6513 EVT getCallOperandValEVT(LLVMContext &Context, const TargetLowering &TLI,
6514 const DataLayout &DL) const {
6515 if (!CallOperandVal) return MVT::Other;
6516
6517 if (isa<BasicBlock>(CallOperandVal))
6518 return TLI.getPointerTy(DL);
6519
6520 llvm::Type *OpTy = CallOperandVal->getType();
6521
6522 // FIXME: code duplicated from TargetLowering::ParseConstraints().
6523 // If this is an indirect operand, the operand is a pointer to the
6524 // accessed type.
6525 if (isIndirect) {
6526 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
6527 if (!PtrTy)
6528 report_fatal_error("Indirect operand for inline asm not a pointer!");
6529 OpTy = PtrTy->getElementType();
6530 }
6531
6532 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
6533 if (StructType *STy = dyn_cast<StructType>(OpTy))
6534 if (STy->getNumElements() == 1)
6535 OpTy = STy->getElementType(0);
6536
6537 // If OpTy is not a single value, it may be a struct/union that we
6538 // can tile with integers.
6539 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
6540 unsigned BitSize = DL.getTypeSizeInBits(OpTy);
6541 switch (BitSize) {
6542 default: break;
6543 case 1:
6544 case 8:
6545 case 16:
6546 case 32:
6547 case 64:
6548 case 128:
6549 OpTy = IntegerType::get(Context, BitSize);
6550 break;
6551 }
6552 }
6553
6554 return TLI.getValueType(DL, OpTy, true);
6555 }
6556};
6557
6558typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector;
6559
6560} // end anonymous namespace
6561
6562/// Make sure that the output operand \p OpInfo and its corresponding input
6563/// operand \p MatchingOpInfo have compatible constraint types (otherwise error
6564/// out).
6565static void patchMatchingInput(const SDISelAsmOperandInfo &OpInfo,
6566 SDISelAsmOperandInfo &MatchingOpInfo,
6567 SelectionDAG &DAG) {
6568 if (OpInfo.ConstraintVT == MatchingOpInfo.ConstraintVT)
6569 return;
6570
6571 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
6572 const auto &TLI = DAG.getTargetLoweringInfo();
6573
6574 std::pair<unsigned, const TargetRegisterClass *> MatchRC =
6575 TLI.getRegForInlineAsmConstraint(TRI, OpInfo.ConstraintCode,
6576 OpInfo.ConstraintVT);
6577 std::pair<unsigned, const TargetRegisterClass *> InputRC =
6578 TLI.getRegForInlineAsmConstraint(TRI, MatchingOpInfo.ConstraintCode,
6579 MatchingOpInfo.ConstraintVT);
6580 if ((OpInfo.ConstraintVT.isInteger() !=
6581 MatchingOpInfo.ConstraintVT.isInteger()) ||
6582 (MatchRC.second != InputRC.second)) {
6583 // FIXME: error out in a more elegant fashion
6584 report_fatal_error("Unsupported asm: input constraint"
6585 " with a matching output constraint of"
6586 " incompatible type!");
6587 }
6588 MatchingOpInfo.ConstraintVT = OpInfo.ConstraintVT;
6589}
6590
6591/// Get a direct memory input to behave well as an indirect operand.
6592/// This may introduce stores, hence the need for a \p Chain.
6593/// \return The (possibly updated) chain.
6594static SDValue getAddressForMemoryInput(SDValue Chain, const SDLoc &Location,
6595 SDISelAsmOperandInfo &OpInfo,
6596 SelectionDAG &DAG) {
6597 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6598
6599 // If we don't have an indirect input, put it in the constpool if we can,
6600 // otherwise spill it to a stack slot.
6601 // TODO: This isn't quite right. We need to handle these according to
6602 // the addressing mode that the constraint wants. Also, this may take
6603 // an additional register for the computation and we don't want that
6604 // either.
6605
6606 // If the operand is a float, integer, or vector constant, spill to a
6607 // constant pool entry to get its address.
6608 const Value *OpVal = OpInfo.CallOperandVal;
6609 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
6610 isa<ConstantVector>(OpVal) || isa<ConstantDataVector>(OpVal)) {
6611 OpInfo.CallOperand = DAG.getConstantPool(
6612 cast<Constant>(OpVal), TLI.getPointerTy(DAG.getDataLayout()));
6613 return Chain;
6614 }
6615
6616 // Otherwise, create a stack slot and emit a store to it before the asm.
6617 Type *Ty = OpVal->getType();
6618 auto &DL = DAG.getDataLayout();
6619 uint64_t TySize = DL.getTypeAllocSize(Ty);
6620 unsigned Align = DL.getPrefTypeAlignment(Ty);
6621 MachineFunction &MF = DAG.getMachineFunction();
6622 int SSFI = MF.getFrameInfo().CreateStackObject(TySize, Align, false);
6623 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy(DL));
6624 Chain = DAG.getStore(Chain, Location, OpInfo.CallOperand, StackSlot,
6625 MachinePointerInfo::getFixedStack(MF, SSFI));
6626 OpInfo.CallOperand = StackSlot;
6627
6628 return Chain;
6629}
6630
6631/// GetRegistersForValue - Assign registers (virtual or physical) for the
6632/// specified operand. We prefer to assign virtual registers, to allow the
6633/// register allocator to handle the assignment process. However, if the asm
6634/// uses features that we can't model on machineinstrs, we have SDISel do the
6635/// allocation. This produces generally horrible, but correct, code.
6636///
6637/// OpInfo describes the operand.
6638///
6639static void GetRegistersForValue(SelectionDAG &DAG, const TargetLowering &TLI,
6640 const SDLoc &DL,
6641 SDISelAsmOperandInfo &OpInfo) {
6642 LLVMContext &Context = *DAG.getContext();
6643
6644 MachineFunction &MF = DAG.getMachineFunction();
6645 SmallVector<unsigned, 4> Regs;
6646
6647 // If this is a constraint for a single physreg, or a constraint for a
6648 // register class, find it.
6649 std::pair<unsigned, const TargetRegisterClass *> PhysReg =
6650 TLI.getRegForInlineAsmConstraint(MF.getSubtarget().getRegisterInfo(),
1
Value assigned to 'PhysReg.second'
6651 OpInfo.ConstraintCode,
6652 OpInfo.ConstraintVT);
6653
6654 unsigned NumRegs = 1;
6655 if (OpInfo.ConstraintVT != MVT::Other) {
2
Taking true branch
6656 // If this is a FP input in an integer register (or visa versa) insert a bit
6657 // cast of the input value. More generally, handle any case where the input
6658 // value disagrees with the register class we plan to stick this in.
6659 if (OpInfo.Type == InlineAsm::isInput &&
3
Assuming the condition is true
4
Assuming pointer value is null
6660 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
5
Assuming the condition is false
6661 // Try to convert to the first EVT that the reg class contains. If the
6662 // types are identical size, use a bitcast to convert (e.g. two differing
6663 // vector types).
6664 MVT RegVT = *PhysReg.second->vt_begin();
6665 if (RegVT.getSizeInBits() == OpInfo.CallOperand.getValueSizeInBits()) {
6666 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
6667 RegVT, OpInfo.CallOperand);
6668 OpInfo.ConstraintVT = RegVT;
6669 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
6670 // If the input is a FP value and we want it in FP registers, do a
6671 // bitcast to the corresponding integer type. This turns an f64 value
6672 // into i64, which can be passed with two i32 values on a 32-bit
6673 // machine.
6674 RegVT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits());
6675 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
6676 RegVT, OpInfo.CallOperand);
6677 OpInfo.ConstraintVT = RegVT;
6678 }
6679 }
6680
6681 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
6682 }
6683
6684 MVT RegVT;
6685 EVT ValueVT = OpInfo.ConstraintVT;
6686
6687 // If this is a constraint for a specific physical register, like {r17},
6688 // assign it now.
6689 if (unsigned AssignedReg = PhysReg.first) {
6
Assuming 'AssignedReg' is not equal to 0
7
Taking true branch
6690 const TargetRegisterClass *RC = PhysReg.second;
8
'RC' initialized to a null pointer value
6691 if (OpInfo.ConstraintVT == MVT::Other)
9
Taking false branch
6692 ValueVT = *RC->vt_begin();
6693
6694 // Get the actual register value type. This is important, because the user
6695 // may have asked for (e.g.) the AX register in i32 type. We need to
6696 // remember that AX is actually i16 to get the right extension.
6697 RegVT = *RC->vt_begin();
10
Called C++ object pointer is null
6698
6699 // This is a explicit reference to a physical register.
6700 Regs.push_back(AssignedReg);
6701
6702 // If this is an expanded reference, add the rest of the regs to Regs.
6703 if (NumRegs != 1) {
6704 TargetRegisterClass::iterator I = RC->begin();
6705 for (; *I != AssignedReg; ++I)
6706 assert(I != RC->end() && "Didn't find reg!")((I != RC->end() && "Didn't find reg!") ? static_cast
<void> (0) : __assert_fail ("I != RC->end() && \"Didn't find reg!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 6706, __PRETTY_FUNCTION__))
;
6707
6708 // Already added the first reg.
6709 --NumRegs; ++I;
6710 for (; NumRegs; --NumRegs, ++I) {
6711 assert(I != RC->end() && "Ran out of registers to allocate!")((I != RC->end() && "Ran out of registers to allocate!"
) ? static_cast<void> (0) : __assert_fail ("I != RC->end() && \"Ran out of registers to allocate!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 6711, __PRETTY_FUNCTION__))
;
6712 Regs.push_back(*I);
6713 }
6714 }
6715
6716 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
6717 return;
6718 }
6719
6720 // Otherwise, if this was a reference to an LLVM register class, create vregs
6721 // for this reference.
6722 if (const TargetRegisterClass *RC = PhysReg.second) {
6723 RegVT = *RC->vt_begin();
6724 if (OpInfo.ConstraintVT == MVT::Other)
6725 ValueVT = RegVT;
6726
6727 // Create the appropriate number of virtual registers.
6728 MachineRegisterInfo &RegInfo = MF.getRegInfo();
6729 for (; NumRegs; --NumRegs)
6730 Regs.push_back(RegInfo.createVirtualRegister(RC));
6731
6732 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
6733 return;
6734 }
6735
6736 // Otherwise, we couldn't allocate enough registers for this.
6737}
6738
6739static unsigned
6740findMatchingInlineAsmOperand(unsigned OperandNo,
6741 const std::vector<SDValue> &AsmNodeOperands) {
6742 // Scan until we find the definition we already emitted of this operand.
6743 unsigned CurOp = InlineAsm::Op_FirstOperand;
6744 for (; OperandNo; --OperandNo) {
6745 // Advance to the next operand.
6746 unsigned OpFlag =
6747 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6748 assert((InlineAsm::isRegDefKind(OpFlag) ||(((InlineAsm::isRegDefKind(OpFlag) || InlineAsm::isRegDefEarlyClobberKind
(OpFlag) || InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?"
) ? static_cast<void> (0) : __assert_fail ("(InlineAsm::isRegDefKind(OpFlag) || InlineAsm::isRegDefEarlyClobberKind(OpFlag) || InlineAsm::isMemKind(OpFlag)) && \"Skipped past definitions?\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 6751, __PRETTY_FUNCTION__))
6749 InlineAsm::isRegDefEarlyClobberKind(OpFlag) ||(((InlineAsm::isRegDefKind(OpFlag) || InlineAsm::isRegDefEarlyClobberKind
(OpFlag) || InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?"
) ? static_cast<void> (0) : __assert_fail ("(InlineAsm::isRegDefKind(OpFlag) || InlineAsm::isRegDefEarlyClobberKind(OpFlag) || InlineAsm::isMemKind(OpFlag)) && \"Skipped past definitions?\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 6751, __PRETTY_FUNCTION__))
6750 InlineAsm::isMemKind(OpFlag)) &&(((InlineAsm::isRegDefKind(OpFlag) || InlineAsm::isRegDefEarlyClobberKind
(OpFlag) || InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?"
) ? static_cast<void> (0) : __assert_fail ("(InlineAsm::isRegDefKind(OpFlag) || InlineAsm::isRegDefEarlyClobberKind(OpFlag) || InlineAsm::isMemKind(OpFlag)) && \"Skipped past definitions?\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 6751, __PRETTY_FUNCTION__))
6751 "Skipped past definitions?")(((InlineAsm::isRegDefKind(OpFlag) || InlineAsm::isRegDefEarlyClobberKind
(OpFlag) || InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?"
) ? static_cast<void> (0) : __assert_fail ("(InlineAsm::isRegDefKind(OpFlag) || InlineAsm::isRegDefEarlyClobberKind(OpFlag) || InlineAsm::isMemKind(OpFlag)) && \"Skipped past definitions?\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 6751, __PRETTY_FUNCTION__))
;
6752 CurOp += InlineAsm::getNumOperandRegisters(OpFlag) + 1;
6753 }
6754 return CurOp;
6755}
6756
6757/// Fill \p Regs with \p NumRegs new virtual registers of type \p RegVT
6758/// \return true if it has succeeded, false otherwise
6759static bool createVirtualRegs(SmallVector<unsigned, 4> &Regs, unsigned NumRegs,
6760 MVT RegVT, SelectionDAG &DAG) {
6761 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6762 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
6763 for (unsigned i = 0, e = NumRegs; i != e; ++i) {
6764 if (const TargetRegisterClass *RC = TLI.getRegClassFor(RegVT))
6765 Regs.push_back(RegInfo.createVirtualRegister(RC));
6766 else
6767 return false;
6768 }
6769 return true;
6770}
6771
6772class ExtraFlags {
6773 unsigned Flags = 0;
6774
6775public:
6776 explicit ExtraFlags(ImmutableCallSite CS) {
6777 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
6778 if (IA->hasSideEffects())
6779 Flags |= InlineAsm::Extra_HasSideEffects;
6780 if (IA->isAlignStack())
6781 Flags |= InlineAsm::Extra_IsAlignStack;
6782 if (CS.isConvergent())
6783 Flags |= InlineAsm::Extra_IsConvergent;
6784 Flags |= IA->getDialect() * InlineAsm::Extra_AsmDialect;
6785 }
6786
6787 void update(const llvm::TargetLowering::AsmOperandInfo &OpInfo) {
6788 // Ideally, we would only check against memory constraints. However, the
6789 // meaning of an Other constraint can be target-specific and we can't easily
6790 // reason about it. Therefore, be conservative and set MayLoad/MayStore
6791 // for Other constraints as well.
6792 if (OpInfo.ConstraintType == TargetLowering::C_Memory ||
6793 OpInfo.ConstraintType == TargetLowering::C_Other) {
6794 if (OpInfo.Type == InlineAsm::isInput)
6795 Flags |= InlineAsm::Extra_MayLoad;
6796 else if (OpInfo.Type == InlineAsm::isOutput)
6797 Flags |= InlineAsm::Extra_MayStore;
6798 else if (OpInfo.Type == InlineAsm::isClobber)
6799 Flags |= (InlineAsm::Extra_MayLoad | InlineAsm::Extra_MayStore);
6800 }
6801 }
6802
6803 unsigned get() const { return Flags; }
6804};
6805
6806/// visitInlineAsm - Handle a call to an InlineAsm object.
6807///
6808void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
6809 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
6810
6811 /// ConstraintOperands - Information about all of the constraints.
6812 SDISelAsmOperandInfoVector ConstraintOperands;
6813
6814 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6815 TargetLowering::AsmOperandInfoVector TargetConstraints = TLI.ParseConstraints(
6816 DAG.getDataLayout(), DAG.getSubtarget().getRegisterInfo(), CS);
6817
6818 bool hasMemory = false;
6819
6820 // Remember the HasSideEffect, AlignStack, AsmDialect, MayLoad and MayStore
6821 ExtraFlags ExtraInfo(CS);
6822
6823 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
6824 unsigned ResNo = 0; // ResNo - The result number of the next output.
6825 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
6826 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i]));
6827 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
6828
6829 MVT OpVT = MVT::Other;
6830
6831 // Compute the value type for each operand.
6832 if (OpInfo.Type == InlineAsm::isInput ||
6833 (OpInfo.Type == InlineAsm::isOutput && OpInfo.isIndirect)) {
6834 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
6835
6836 // Process the call argument. BasicBlocks are labels, currently appearing
6837 // only in asm's.
6838 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
6839 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
6840 } else {
6841 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
6842 }
6843
6844 OpVT =
6845 OpInfo
6846 .getCallOperandValEVT(*DAG.getContext(), TLI, DAG.getDataLayout())
6847 .getSimpleVT();
6848 }
6849
6850 if (OpInfo.Type == InlineAsm::isOutput && !OpInfo.isIndirect) {
6851 // The return value of the call is this value. As such, there is no
6852 // corresponding argument.
6853 assert(!CS.getType()->isVoidTy() && "Bad inline asm!")((!CS.getType()->isVoidTy() && "Bad inline asm!") ?
static_cast<void> (0) : __assert_fail ("!CS.getType()->isVoidTy() && \"Bad inline asm!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 6853, __PRETTY_FUNCTION__))
;
6854 if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
6855 OpVT = TLI.getSimpleValueType(DAG.getDataLayout(),
6856 STy->getElementType(ResNo));
6857 } else {
6858 assert(ResNo == 0 && "Asm only has one result!")((ResNo == 0 && "Asm only has one result!") ? static_cast
<void> (0) : __assert_fail ("ResNo == 0 && \"Asm only has one result!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 6858, __PRETTY_FUNCTION__))
;
6859 OpVT = TLI.getSimpleValueType(DAG.getDataLayout(), CS.getType());
6860 }
6861 ++ResNo;
6862 }
6863
6864 OpInfo.ConstraintVT = OpVT;
6865
6866 if (!hasMemory)
6867 hasMemory = OpInfo.hasMemory(TLI);
6868
6869 // Determine if this InlineAsm MayLoad or MayStore based on the constraints.
6870 // FIXME: Could we compute this on OpInfo rather than TargetConstraints[i]?
6871 auto TargetConstraint = TargetConstraints[i];
6872
6873 // Compute the constraint code and ConstraintType to use.
6874 TLI.ComputeConstraintToUse(TargetConstraint, SDValue());
6875
6876 ExtraInfo.update(TargetConstraint);
6877 }
6878
6879 SDValue Chain, Flag;
6880
6881 // We won't need to flush pending loads if this asm doesn't touch
6882 // memory and is nonvolatile.
6883 if (hasMemory || IA->hasSideEffects())
6884 Chain = getRoot();
6885 else
6886 Chain = DAG.getRoot();
6887
6888 // Second pass over the constraints: compute which constraint option to use
6889 // and assign registers to constraints that want a specific physreg.
6890 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6891 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6892
6893 // If this is an output operand with a matching input operand, look up the
6894 // matching input. If their types mismatch, e.g. one is an integer, the
6895 // other is floating point, or their sizes are different, flag it as an
6896 // error.
6897 if (OpInfo.hasMatchingInput()) {
6898 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
6899 patchMatchingInput(OpInfo, Input, DAG);
6900 }
6901
6902 // Compute the constraint code and ConstraintType to use.
6903 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
6904
6905 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
6906 OpInfo.Type == InlineAsm::isClobber)
6907 continue;
6908
6909 // If this is a memory input, and if the operand is not indirect, do what we
6910 // need to to provide an address for the memory input.
6911 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
6912 !OpInfo.isIndirect) {
6913 assert((OpInfo.isMultipleAlternative ||(((OpInfo.isMultipleAlternative || (OpInfo.Type == InlineAsm::
isInput)) && "Can only indirectify direct input operands!"
) ? static_cast<void> (0) : __assert_fail ("(OpInfo.isMultipleAlternative || (OpInfo.Type == InlineAsm::isInput)) && \"Can only indirectify direct input operands!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 6915, __PRETTY_FUNCTION__))
6914 (OpInfo.Type == InlineAsm::isInput)) &&(((OpInfo.isMultipleAlternative || (OpInfo.Type == InlineAsm::
isInput)) && "Can only indirectify direct input operands!"
) ? static_cast<void> (0) : __assert_fail ("(OpInfo.isMultipleAlternative || (OpInfo.Type == InlineAsm::isInput)) && \"Can only indirectify direct input operands!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 6915, __PRETTY_FUNCTION__))
6915 "Can only indirectify direct input operands!")(((OpInfo.isMultipleAlternative || (OpInfo.Type == InlineAsm::
isInput)) && "Can only indirectify direct input operands!"
) ? static_cast<void> (0) : __assert_fail ("(OpInfo.isMultipleAlternative || (OpInfo.Type == InlineAsm::isInput)) && \"Can only indirectify direct input operands!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 6915, __PRETTY_FUNCTION__))
;
6916
6917 // Memory operands really want the address of the value.
6918 Chain = getAddressForMemoryInput(Chain, getCurSDLoc(), OpInfo, DAG);
6919
6920 // There is no longer a Value* corresponding to this operand.
6921 OpInfo.CallOperandVal = nullptr;
6922
6923 // It is now an indirect operand.
6924 OpInfo.isIndirect = true;
6925 }
6926
6927 // If this constraint is for a specific register, allocate it before
6928 // anything else.
6929 if (OpInfo.ConstraintType == TargetLowering::C_Register)
6930 GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
6931 }
6932
6933 // Third pass - Loop over all of the operands, assigning virtual or physregs
6934 // to register class operands.
6935 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6936 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6937
6938 // C_Register operands have already been allocated, Other/Memory don't need
6939 // to be.
6940 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
6941 GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
6942 }
6943
6944 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
6945 std::vector<SDValue> AsmNodeOperands;
6946 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
6947 AsmNodeOperands.push_back(DAG.getTargetExternalSymbol(
6948 IA->getAsmString().c_str(), TLI.getPointerTy(DAG.getDataLayout())));
6949
6950 // If we have a !srcloc metadata node associated with it, we want to attach
6951 // this to the ultimately generated inline asm machineinstr. To do this, we
6952 // pass in the third operand as this (potentially null) inline asm MDNode.
6953 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc");
6954 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc));
6955
6956 // Remember the HasSideEffect, AlignStack, AsmDialect, MayLoad and MayStore
6957 // bits as operand 3.
6958 AsmNodeOperands.push_back(DAG.getTargetConstant(
6959 ExtraInfo.get(), getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout())));
6960
6961 // Loop over all of the inputs, copying the operand values into the
6962 // appropriate registers and processing the output regs.
6963 RegsForValue RetValRegs;
6964
6965 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
6966 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
6967
6968 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6969 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6970
6971 switch (OpInfo.Type) {
6972 case InlineAsm::isOutput: {
6973 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
6974 OpInfo.ConstraintType != TargetLowering::C_Register) {
6975 // Memory output, or 'other' output (e.g. 'X' constraint).
6976 assert(OpInfo.isIndirect && "Memory output must be indirect operand")((OpInfo.isIndirect && "Memory output must be indirect operand"
) ? static_cast<void> (0) : __assert_fail ("OpInfo.isIndirect && \"Memory output must be indirect operand\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 6976, __PRETTY_FUNCTION__))
;
6977
6978 unsigned ConstraintID =
6979 TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
6980 assert(ConstraintID != InlineAsm::Constraint_Unknown &&((ConstraintID != InlineAsm::Constraint_Unknown && "Failed to convert memory constraint code to constraint id."
) ? static_cast<void> (0) : __assert_fail ("ConstraintID != InlineAsm::Constraint_Unknown && \"Failed to convert memory constraint code to constraint id.\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 6981, __PRETTY_FUNCTION__))
6981 "Failed to convert memory constraint code to constraint id.")((ConstraintID != InlineAsm::Constraint_Unknown && "Failed to convert memory constraint code to constraint id."
) ? static_cast<void> (0) : __assert_fail ("ConstraintID != InlineAsm::Constraint_Unknown && \"Failed to convert memory constraint code to constraint id.\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 6981, __PRETTY_FUNCTION__))
;
6982
6983 // Add information to the INLINEASM node to know about this output.
6984 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6985 OpFlags = InlineAsm::getFlagWordForMem(OpFlags, ConstraintID);
6986 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags, getCurSDLoc(),
6987 MVT::i32));
6988 AsmNodeOperands.push_back(OpInfo.CallOperand);
6989 break;
6990 }
6991
6992 // Otherwise, this is a register or register class output.
6993
6994 // Copy the output from the appropriate register. Find a register that
6995 // we can use.
6996 if (OpInfo.AssignedRegs.Regs.empty()) {
6997 emitInlineAsmError(
6998 CS, "couldn't allocate output register for constraint '" +
6999 Twine(OpInfo.ConstraintCode) + "'");
7000 return;
7001 }
7002
7003 // If this is an indirect operand, store through the pointer after the
7004 // asm.
7005 if (OpInfo.isIndirect) {
7006 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
7007 OpInfo.CallOperandVal));
7008 } else {
7009 // This is the result value of the call.
7010 assert(!CS.getType()->isVoidTy() && "Bad inline asm!")((!CS.getType()->isVoidTy() && "Bad inline asm!") ?
static_cast<void> (0) : __assert_fail ("!CS.getType()->isVoidTy() && \"Bad inline asm!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7010, __PRETTY_FUNCTION__))
;
7011 // Concatenate this output onto the outputs list.
7012 RetValRegs.append(OpInfo.AssignedRegs);
7013 }
7014
7015 // Add information to the INLINEASM node to know that this register is
7016 // set.
7017 OpInfo.AssignedRegs
7018 .AddInlineAsmOperands(OpInfo.isEarlyClobber
7019 ? InlineAsm::Kind_RegDefEarlyClobber
7020 : InlineAsm::Kind_RegDef,
7021 false, 0, getCurSDLoc(), DAG, AsmNodeOperands);
7022 break;
7023 }
7024 case InlineAsm::isInput: {
7025 SDValue InOperandVal = OpInfo.CallOperand;
7026
7027 if (OpInfo.isMatchingInputConstraint()) {
7028 // If this is required to match an output register we have already set,
7029 // just use its register.
7030 auto CurOp = findMatchingInlineAsmOperand(OpInfo.getMatchedOperand(),
7031 AsmNodeOperands);
7032 unsigned OpFlag =
7033 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
7034 if (InlineAsm::isRegDefKind(OpFlag) ||
7035 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) {
7036 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
7037 if (OpInfo.isIndirect) {
7038 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c
7039 emitInlineAsmError(CS, "inline asm not supported yet:"
7040 " don't know how to handle tied "
7041 "indirect register inputs");
7042 return;
7043 }
7044
7045 MVT RegVT = AsmNodeOperands[CurOp+1].getSimpleValueType();
7046 SmallVector<unsigned, 4> Regs;
7047
7048 if (!createVirtualRegs(Regs,
7049 InlineAsm::getNumOperandRegisters(OpFlag),
7050 RegVT, DAG)) {
7051 emitInlineAsmError(CS, "inline asm error: This value type register "
7052 "class is not natively supported!");
7053 return;
7054 }
7055
7056 RegsForValue MatchedRegs(Regs, RegVT, InOperandVal.getValueType());
7057
7058 SDLoc dl = getCurSDLoc();
7059 // Use the produced MatchedRegs object to
7060 MatchedRegs.getCopyToRegs(InOperandVal, DAG, dl,
7061 Chain, &Flag, CS.getInstruction());
7062 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse,
7063 true, OpInfo.getMatchedOperand(), dl,
7064 DAG, AsmNodeOperands);
7065 break;
7066 }
7067
7068 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!")((InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!"
) ? static_cast<void> (0) : __assert_fail ("InlineAsm::isMemKind(OpFlag) && \"Unknown matching constraint!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7068, __PRETTY_FUNCTION__))
;
7069 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 &&((InlineAsm::getNumOperandRegisters(OpFlag) == 1 && "Unexpected number of operands"
) ? static_cast<void> (0) : __assert_fail ("InlineAsm::getNumOperandRegisters(OpFlag) == 1 && \"Unexpected number of operands\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7070, __PRETTY_FUNCTION__))
7070 "Unexpected number of operands")((InlineAsm::getNumOperandRegisters(OpFlag) == 1 && "Unexpected number of operands"
) ? static_cast<void> (0) : __assert_fail ("InlineAsm::getNumOperandRegisters(OpFlag) == 1 && \"Unexpected number of operands\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7070, __PRETTY_FUNCTION__))
;
7071 // Add information to the INLINEASM node to know about this input.
7072 // See InlineAsm.h isUseOperandTiedToDef.
7073 OpFlag = InlineAsm::convertMemFlagWordToMatchingFlagWord(OpFlag);
7074 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag,
7075 OpInfo.getMatchedOperand());
7076 AsmNodeOperands.push_back(DAG.getTargetConstant(
7077 OpFlag, getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout())));
7078 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
7079 break;
7080 }
7081
7082 // Treat indirect 'X' constraint as memory.
7083 if (OpInfo.ConstraintType == TargetLowering::C_Other &&
7084 OpInfo.isIndirect)
7085 OpInfo.ConstraintType = TargetLowering::C_Memory;
7086
7087 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
7088 std::vector<SDValue> Ops;
7089 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode,
7090 Ops, DAG);
7091 if (Ops.empty()) {
7092 emitInlineAsmError(CS, "invalid operand for inline asm constraint '" +
7093 Twine(OpInfo.ConstraintCode) + "'");
7094 return;
7095 }
7096
7097 // Add information to the INLINEASM node to know about this input.
7098 unsigned ResOpType =
7099 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
7100 AsmNodeOperands.push_back(DAG.getTargetConstant(
7101 ResOpType, getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout())));
7102 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
7103 break;
7104 }
7105
7106 if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
7107 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!")((OpInfo.isIndirect && "Operand must be indirect to be a mem!"
) ? static_cast<void> (0) : __assert_fail ("OpInfo.isIndirect && \"Operand must be indirect to be a mem!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7107, __PRETTY_FUNCTION__))
;
7108 assert(InOperandVal.getValueType() ==((InOperandVal.getValueType() == TLI.getPointerTy(DAG.getDataLayout
()) && "Memory operands expect pointer values") ? static_cast
<void> (0) : __assert_fail ("InOperandVal.getValueType() == TLI.getPointerTy(DAG.getDataLayout()) && \"Memory operands expect pointer values\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7110, __PRETTY_FUNCTION__))
7109 TLI.getPointerTy(DAG.getDataLayout()) &&((InOperandVal.getValueType() == TLI.getPointerTy(DAG.getDataLayout
()) && "Memory operands expect pointer values") ? static_cast
<void> (0) : __assert_fail ("InOperandVal.getValueType() == TLI.getPointerTy(DAG.getDataLayout()) && \"Memory operands expect pointer values\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7110, __PRETTY_FUNCTION__))
7110 "Memory operands expect pointer values")((InOperandVal.getValueType() == TLI.getPointerTy(DAG.getDataLayout
()) && "Memory operands expect pointer values") ? static_cast
<void> (0) : __assert_fail ("InOperandVal.getValueType() == TLI.getPointerTy(DAG.getDataLayout()) && \"Memory operands expect pointer values\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7110, __PRETTY_FUNCTION__))
;
7111
7112 unsigned ConstraintID =
7113 TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
7114 assert(ConstraintID != InlineAsm::Constraint_Unknown &&((ConstraintID != InlineAsm::Constraint_Unknown && "Failed to convert memory constraint code to constraint id."
) ? static_cast<void> (0) : __assert_fail ("ConstraintID != InlineAsm::Constraint_Unknown && \"Failed to convert memory constraint code to constraint id.\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7115, __PRETTY_FUNCTION__))
7115 "Failed to convert memory constraint code to constraint id.")((ConstraintID != InlineAsm::Constraint_Unknown && "Failed to convert memory constraint code to constraint id."
) ? static_cast<void> (0) : __assert_fail ("ConstraintID != InlineAsm::Constraint_Unknown && \"Failed to convert memory constraint code to constraint id.\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7115, __PRETTY_FUNCTION__))
;
7116
7117 // Add information to the INLINEASM node to know about this input.
7118 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
7119 ResOpType = InlineAsm::getFlagWordForMem(ResOpType, ConstraintID);
7120 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
7121 getCurSDLoc(),
7122 MVT::i32));
7123 AsmNodeOperands.push_back(InOperandVal);
7124 break;
7125 }
7126
7127 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||(((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
OpInfo.ConstraintType == TargetLowering::C_Register) &&
"Unknown constraint type!") ? static_cast<void> (0) : __assert_fail
("(OpInfo.ConstraintType == TargetLowering::C_RegisterClass || OpInfo.ConstraintType == TargetLowering::C_Register) && \"Unknown constraint type!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7129, __PRETTY_FUNCTION__))
7128 OpInfo.ConstraintType == TargetLowering::C_Register) &&(((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
OpInfo.ConstraintType == TargetLowering::C_Register) &&
"Unknown constraint type!") ? static_cast<void> (0) : __assert_fail
("(OpInfo.ConstraintType == TargetLowering::C_RegisterClass || OpInfo.ConstraintType == TargetLowering::C_Register) && \"Unknown constraint type!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7129, __PRETTY_FUNCTION__))
7129 "Unknown constraint type!")(((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
OpInfo.ConstraintType == TargetLowering::C_Register) &&
"Unknown constraint type!") ? static_cast<void> (0) : __assert_fail
("(OpInfo.ConstraintType == TargetLowering::C_RegisterClass || OpInfo.ConstraintType == TargetLowering::C_Register) && \"Unknown constraint type!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7129, __PRETTY_FUNCTION__))
;
7130
7131 // TODO: Support this.
7132 if (OpInfo.isIndirect) {
7133 emitInlineAsmError(
7134 CS, "Don't know how to handle indirect register inputs yet "
7135 "for constraint '" +
7136 Twine(OpInfo.ConstraintCode) + "'");
7137 return;
7138 }
7139
7140 // Copy the input into the appropriate registers.
7141 if (OpInfo.AssignedRegs.Regs.empty()) {
7142 emitInlineAsmError(CS, "couldn't allocate input reg for constraint '" +
7143 Twine(OpInfo.ConstraintCode) + "'");
7144 return;
7145 }
7146
7147 SDLoc dl = getCurSDLoc();
7148
7149 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, dl,
7150 Chain, &Flag, CS.getInstruction());
7151
7152 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0,
7153 dl, DAG, AsmNodeOperands);
7154 break;
7155 }
7156 case InlineAsm::isClobber: {
7157 // Add the clobbered value to the operand list, so that the register
7158 // allocator is aware that the physreg got clobbered.
7159 if (!OpInfo.AssignedRegs.Regs.empty())
7160 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber,
7161 false, 0, getCurSDLoc(), DAG,
7162 AsmNodeOperands);
7163 break;
7164 }
7165 }
7166 }
7167
7168 // Finish up input operands. Set the input chain and add the flag last.
7169 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
7170 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
7171
7172 Chain = DAG.getNode(ISD::INLINEASM, getCurSDLoc(),
7173 DAG.getVTList(MVT::Other, MVT::Glue), AsmNodeOperands);
7174 Flag = Chain.getValue(1);
7175
7176 // If this asm returns a register value, copy the result from that register
7177 // and set it as the value of the call.
7178 if (!RetValRegs.Regs.empty()) {
7179 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
7180 Chain, &Flag, CS.getInstruction());
7181
7182 // FIXME: Why don't we do this for inline asms with MRVs?
7183 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
7184 EVT ResultType = TLI.getValueType(DAG.getDataLayout(), CS.getType());
7185
7186 // If any of the results of the inline asm is a vector, it may have the
7187 // wrong width/num elts. This can happen for register classes that can
7188 // contain multiple different value types. The preg or vreg allocated may
7189 // not have the same VT as was expected. Convert it to the right type
7190 // with bit_convert.
7191 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
7192 Val = DAG.getNode(ISD::BITCAST, getCurSDLoc(),
7193 ResultType, Val);
7194
7195 } else if (ResultType != Val.getValueType() &&
7196 ResultType.isInteger() && Val.getValueType().isInteger()) {
7197 // If a result value was tied to an input value, the computed result may
7198 // have a wider width than the expected result. Extract the relevant
7199 // portion.
7200 Val = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), ResultType, Val);
7201 }
7202
7203 assert(ResultType == Val.getValueType() && "Asm result value mismatch!")((ResultType == Val.getValueType() && "Asm result value mismatch!"
) ? static_cast<void> (0) : __assert_fail ("ResultType == Val.getValueType() && \"Asm result value mismatch!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7203, __PRETTY_FUNCTION__))
;
7204 }
7205
7206 setValue(CS.getInstruction(), Val);
7207 // Don't need to use this as a chain in this case.
7208 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
7209 return;
7210 }
7211
7212 std::vector<std::pair<SDValue, const Value *> > StoresToEmit;
7213
7214 // Process indirect outputs, first output all of the flagged copies out of
7215 // physregs.
7216 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
7217 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
7218 const Value *Ptr = IndirectStoresToEmit[i].second;
7219 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
7220 Chain, &Flag, IA);
7221 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
7222 }
7223
7224 // Emit the non-flagged stores from the physregs.
7225 SmallVector<SDValue, 8> OutChains;
7226 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) {
7227 SDValue Val = DAG.getStore(Chain, getCurSDLoc(), StoresToEmit[i].first,
7228 getValue(StoresToEmit[i].second),
7229 MachinePointerInfo(StoresToEmit[i].second));
7230 OutChains.push_back(Val);
7231 }
7232
7233 if (!OutChains.empty())
7234 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other, OutChains);
7235
7236 DAG.setRoot(Chain);
7237}
7238
7239void SelectionDAGBuilder::emitInlineAsmError(ImmutableCallSite CS,
7240 const Twine &Message) {
7241 LLVMContext &Ctx = *DAG.getContext();
7242 Ctx.emitError(CS.getInstruction(), Message);
7243
7244 // Make sure we leave the DAG in a valid state
7245 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7246 auto VT = TLI.getValueType(DAG.getDataLayout(), CS.getType());
7247 setValue(CS.getInstruction(), DAG.getUNDEF(VT));
7248}
7249
7250void SelectionDAGBuilder::visitVAStart(const CallInst &I) {
7251 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurSDLoc(),
7252 MVT::Other, getRoot(),
7253 getValue(I.getArgOperand(0)),
7254 DAG.getSrcValue(I.getArgOperand(0))));
7255}
7256
7257void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) {
7258 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7259 const DataLayout &DL = DAG.getDataLayout();
7260 SDValue V = DAG.getVAArg(TLI.getValueType(DAG.getDataLayout(), I.getType()),
7261 getCurSDLoc(), getRoot(), getValue(I.getOperand(0)),
7262 DAG.getSrcValue(I.getOperand(0)),
7263 DL.getABITypeAlignment(I.getType()));
7264 setValue(&I, V);
7265 DAG.setRoot(V.getValue(1));
7266}
7267
7268void SelectionDAGBuilder::visitVAEnd(const CallInst &I) {
7269 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurSDLoc(),
7270 MVT::Other, getRoot(),
7271 getValue(I.getArgOperand(0)),
7272 DAG.getSrcValue(I.getArgOperand(0))));
7273}
7274
7275void SelectionDAGBuilder::visitVACopy(const CallInst &I) {
7276 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurSDLoc(),
7277 MVT::Other, getRoot(),
7278 getValue(I.getArgOperand(0)),
7279 getValue(I.getArgOperand(1)),
7280 DAG.getSrcValue(I.getArgOperand(0)),
7281 DAG.getSrcValue(I.getArgOperand(1))));
7282}
7283
7284SDValue SelectionDAGBuilder::lowerRangeToAssertZExt(SelectionDAG &DAG,
7285 const Instruction &I,
7286 SDValue Op) {
7287 const MDNode *Range = I.getMetadata(LLVMContext::MD_range);
7288 if (!Range)
7289 return Op;
7290
7291 ConstantRange CR = getConstantRangeFromMetadata(*Range);
7292 if (CR.isFullSet() || CR.isEmptySet() || CR.isWrappedSet())
7293 return Op;
7294
7295 APInt Lo = CR.getUnsignedMin();
7296 if (!Lo.isMinValue())
7297 return Op;
7298
7299 APInt Hi = CR.getUnsignedMax();
7300 unsigned Bits = Hi.getActiveBits();
7301
7302 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), Bits);
7303
7304 SDLoc SL = getCurSDLoc();
7305
7306 SDValue ZExt = DAG.getNode(ISD::AssertZext, SL, Op.getValueType(), Op,
7307 DAG.getValueType(SmallVT));
7308 unsigned NumVals = Op.getNode()->getNumValues();
7309 if (NumVals == 1)
7310 return ZExt;
7311
7312 SmallVector<SDValue, 4> Ops;
7313
7314 Ops.push_back(ZExt);
7315 for (unsigned I = 1; I != NumVals; ++I)
7316 Ops.push_back(Op.getValue(I));
7317
7318 return DAG.getMergeValues(Ops, SL);
7319}
7320
7321/// \brief Populate a CallLowerinInfo (into \p CLI) based on the properties of
7322/// the call being lowered.
7323///
7324/// This is a helper for lowering intrinsics that follow a target calling
7325/// convention or require stack pointer adjustment. Only a subset of the
7326/// intrinsic's operands need to participate in the calling convention.
7327void SelectionDAGBuilder::populateCallLoweringInfo(
7328 TargetLowering::CallLoweringInfo &CLI, ImmutableCallSite CS,
7329 unsigned ArgIdx, unsigned NumArgs, SDValue Callee, Type *ReturnTy,
7330 bool IsPatchPoint) {
7331 TargetLowering::ArgListTy Args;
7332 Args.reserve(NumArgs);
7333
7334 // Populate the argument list.
7335 // Attributes for args start at offset 1, after the return attribute.
7336 for (unsigned ArgI = ArgIdx, ArgE = ArgIdx + NumArgs, AttrI = ArgIdx + 1;
7337 ArgI != ArgE; ++ArgI) {
7338 const Value *V = CS->getOperand(ArgI);
7339
7340 assert(!V->getType()->isEmptyTy() && "Empty type passed to intrinsic.")((!V->getType()->isEmptyTy() && "Empty type passed to intrinsic."
) ? static_cast<void> (0) : __assert_fail ("!V->getType()->isEmptyTy() && \"Empty type passed to intrinsic.\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7340, __PRETTY_FUNCTION__))
;
7341
7342 TargetLowering::ArgListEntry Entry;
7343 Entry.Node = getValue(V);
7344 Entry.Ty = V->getType();
7345 Entry.setAttributes(&CS, AttrI);
7346 Args.push_back(Entry);
7347 }
7348
7349 CLI.setDebugLoc(getCurSDLoc())
7350 .setChain(getRoot())
7351 .setCallee(CS.getCallingConv(), ReturnTy, Callee, std::move(Args))
7352 .setDiscardResult(CS->use_empty())
7353 .setIsPatchPoint(IsPatchPoint);
7354}
7355
7356/// \brief Add a stack map intrinsic call's live variable operands to a stackmap
7357/// or patchpoint target node's operand list.
7358///
7359/// Constants are converted to TargetConstants purely as an optimization to
7360/// avoid constant materialization and register allocation.
7361///
7362/// FrameIndex operands are converted to TargetFrameIndex so that ISEL does not
7363/// generate addess computation nodes, and so ExpandISelPseudo can convert the
7364/// TargetFrameIndex into a DirectMemRefOp StackMap location. This avoids
7365/// address materialization and register allocation, but may also be required
7366/// for correctness. If a StackMap (or PatchPoint) intrinsic directly uses an
7367/// alloca in the entry block, then the runtime may assume that the alloca's
7368/// StackMap location can be read immediately after compilation and that the
7369/// location is valid at any point during execution (this is similar to the
7370/// assumption made by the llvm.gcroot intrinsic). If the alloca's location were
7371/// only available in a register, then the runtime would need to trap when
7372/// execution reaches the StackMap in order to read the alloca's location.
7373static void addStackMapLiveVars(ImmutableCallSite CS, unsigned StartIdx,
7374 const SDLoc &DL, SmallVectorImpl<SDValue> &Ops,
7375 SelectionDAGBuilder &Builder) {
7376 for (unsigned i = StartIdx, e = CS.arg_size(); i != e; ++i) {
7377 SDValue OpVal = Builder.getValue(CS.getArgument(i));
7378 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(OpVal)) {
7379 Ops.push_back(
7380 Builder.DAG.getTargetConstant(StackMaps::ConstantOp, DL, MVT::i64));
7381 Ops.push_back(
7382 Builder.DAG.getTargetConstant(C->getSExtValue(), DL, MVT::i64));
7383 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(OpVal)) {
7384 const TargetLowering &TLI = Builder.DAG.getTargetLoweringInfo();
7385 Ops.push_back(Builder.DAG.getTargetFrameIndex(
7386 FI->getIndex(), TLI.getPointerTy(Builder.DAG.getDataLayout())));
7387 } else
7388 Ops.push_back(OpVal);
7389 }
7390}
7391
7392/// \brief Lower llvm.experimental.stackmap directly to its target opcode.
7393void SelectionDAGBuilder::visitStackmap(const CallInst &CI) {
7394 // void @llvm.experimental.stackmap(i32 <id>, i32 <numShadowBytes>,
7395 // [live variables...])
7396
7397 assert(CI.getType()->isVoidTy() && "Stackmap cannot return a value.")((CI.getType()->isVoidTy() && "Stackmap cannot return a value."
) ? static_cast<void> (0) : __assert_fail ("CI.getType()->isVoidTy() && \"Stackmap cannot return a value.\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7397, __PRETTY_FUNCTION__))
;
7398
7399 SDValue Chain, InFlag, Callee, NullPtr;
7400 SmallVector<SDValue, 32> Ops;
7401
7402 SDLoc DL = getCurSDLoc();
7403 Callee = getValue(CI.getCalledValue());
7404 NullPtr = DAG.getIntPtrConstant(0, DL, true);
7405
7406 // The stackmap intrinsic only records the live variables (the arguemnts
7407 // passed to it) and emits NOPS (if requested). Unlike the patchpoint
7408 // intrinsic, this won't be lowered to a function call. This means we don't
7409 // have to worry about calling conventions and target specific lowering code.
7410 // Instead we perform the call lowering right here.
7411 //
7412 // chain, flag = CALLSEQ_START(chain, 0)
7413 // chain, flag = STACKMAP(id, nbytes, ..., chain, flag)
7414 // chain, flag = CALLSEQ_END(chain, 0, 0, flag)
7415 //
7416 Chain = DAG.getCALLSEQ_START(getRoot(), NullPtr, DL);
7417 InFlag = Chain.getValue(1);
7418
7419 // Add the <id> and <numBytes> constants.
7420 SDValue IDVal = getValue(CI.getOperand(PatchPointOpers::IDPos));
7421 Ops.push_back(DAG.getTargetConstant(
7422 cast<ConstantSDNode>(IDVal)->getZExtValue(), DL, MVT::i64));
7423 SDValue NBytesVal = getValue(CI.getOperand(PatchPointOpers::NBytesPos));
7424 Ops.push_back(DAG.getTargetConstant(
7425 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), DL,
7426 MVT::i32));
7427
7428 // Push live variables for the stack map.
7429 addStackMapLiveVars(&CI, 2, DL, Ops, *this);
7430
7431 // We are not pushing any register mask info here on the operands list,
7432 // because the stackmap doesn't clobber anything.
7433
7434 // Push the chain and the glue flag.
7435 Ops.push_back(Chain);
7436 Ops.push_back(InFlag);
7437
7438 // Create the STACKMAP node.
7439 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7440 SDNode *SM = DAG.getMachineNode(TargetOpcode::STACKMAP, DL, NodeTys, Ops);
7441 Chain = SDValue(SM, 0);
7442 InFlag = Chain.getValue(1);
7443
7444 Chain = DAG.getCALLSEQ_END(Chain, NullPtr, NullPtr, InFlag, DL);
7445
7446 // Stackmaps don't generate values, so nothing goes into the NodeMap.
7447
7448 // Set the root to the target-lowered call chain.
7449 DAG.setRoot(Chain);
7450
7451 // Inform the Frame Information that we have a stackmap in this function.
7452 FuncInfo.MF->getFrameInfo().setHasStackMap();
7453}
7454
7455/// \brief Lower llvm.experimental.patchpoint directly to its target opcode.
7456void SelectionDAGBuilder::visitPatchpoint(ImmutableCallSite CS,
7457 const BasicBlock *EHPadBB) {
7458 // void|i64 @llvm.experimental.patchpoint.void|i64(i64 <id>,
7459 // i32 <numBytes>,
7460 // i8* <target>,
7461 // i32 <numArgs>,
7462 // [Args...],
7463 // [live variables...])
7464
7465 CallingConv::ID CC = CS.getCallingConv();
7466 bool IsAnyRegCC = CC == CallingConv::AnyReg;
7467 bool HasDef = !CS->getType()->isVoidTy();
7468 SDLoc dl = getCurSDLoc();
7469 SDValue Callee = getValue(CS->getOperand(PatchPointOpers::TargetPos));
7470
7471 // Handle immediate and symbolic callees.
7472 if (auto* ConstCallee = dyn_cast<ConstantSDNode>(Callee))
7473 Callee = DAG.getIntPtrConstant(ConstCallee->getZExtValue(), dl,
7474 /*isTarget=*/true);
7475 else if (auto* SymbolicCallee = dyn_cast<GlobalAddressSDNode>(Callee))
7476 Callee = DAG.getTargetGlobalAddress(SymbolicCallee->getGlobal(),
7477 SDLoc(SymbolicCallee),
7478 SymbolicCallee->getValueType(0));
7479
7480 // Get the real number of arguments participating in the call <numArgs>
7481 SDValue NArgVal = getValue(CS.getArgument(PatchPointOpers::NArgPos));
7482 unsigned NumArgs = cast<ConstantSDNode>(NArgVal)->getZExtValue();
7483
7484 // Skip the four meta args: <id>, <numNopBytes>, <target>, <numArgs>
7485 // Intrinsics include all meta-operands up to but not including CC.
7486 unsigned NumMetaOpers = PatchPointOpers::CCPos;
7487 assert(CS.arg_size() >= NumMetaOpers + NumArgs &&((CS.arg_size() >= NumMetaOpers + NumArgs && "Not enough arguments provided to the patchpoint intrinsic"
) ? static_cast<void> (0) : __assert_fail ("CS.arg_size() >= NumMetaOpers + NumArgs && \"Not enough arguments provided to the patchpoint intrinsic\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7488, __PRETTY_FUNCTION__))
7488 "Not enough arguments provided to the patchpoint intrinsic")((CS.arg_size() >= NumMetaOpers + NumArgs && "Not enough arguments provided to the patchpoint intrinsic"
) ? static_cast<void> (0) : __assert_fail ("CS.arg_size() >= NumMetaOpers + NumArgs && \"Not enough arguments provided to the patchpoint intrinsic\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7488, __PRETTY_FUNCTION__))
;
7489
7490 // For AnyRegCC the arguments are lowered later on manually.
7491 unsigned NumCallArgs = IsAnyRegCC ? 0 : NumArgs;
7492 Type *ReturnTy =
7493 IsAnyRegCC ? Type::getVoidTy(*DAG.getContext()) : CS->getType();
7494
7495 TargetLowering::CallLoweringInfo CLI(DAG);
7496 populateCallLoweringInfo(CLI, CS, NumMetaOpers, NumCallArgs, Callee, ReturnTy,
7497 true);
7498 std::pair<SDValue, SDValue> Result = lowerInvokable(CLI, EHPadBB);
7499
7500 SDNode *CallEnd = Result.second.getNode();
7501 if (HasDef && (CallEnd->getOpcode() == ISD::CopyFromReg))
7502 CallEnd = CallEnd->getOperand(0).getNode();
7503
7504 /// Get a call instruction from the call sequence chain.
7505 /// Tail calls are not allowed.
7506 assert(CallEnd->getOpcode() == ISD::CALLSEQ_END &&((CallEnd->getOpcode() == ISD::CALLSEQ_END && "Expected a callseq node."
) ? static_cast<void> (0) : __assert_fail ("CallEnd->getOpcode() == ISD::CALLSEQ_END && \"Expected a callseq node.\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7507, __PRETTY_FUNCTION__))
7507 "Expected a callseq node.")((CallEnd->getOpcode() == ISD::CALLSEQ_END && "Expected a callseq node."
) ? static_cast<void> (0) : __assert_fail ("CallEnd->getOpcode() == ISD::CALLSEQ_END && \"Expected a callseq node.\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7507, __PRETTY_FUNCTION__))
;
7508 SDNode *Call = CallEnd->getOperand(0).getNode();
7509 bool HasGlue = Call->getGluedNode();
7510
7511 // Replace the target specific call node with the patchable intrinsic.
7512 SmallVector<SDValue, 8> Ops;
7513
7514 // Add the <id> and <numBytes> constants.
7515 SDValue IDVal = getValue(CS->getOperand(PatchPointOpers::IDPos));
7516 Ops.push_back(DAG.getTargetConstant(
7517 cast<ConstantSDNode>(IDVal)->getZExtValue(), dl, MVT::i64));
7518 SDValue NBytesVal = getValue(CS->getOperand(PatchPointOpers::NBytesPos));
7519 Ops.push_back(DAG.getTargetConstant(
7520 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), dl,
7521 MVT::i32));
7522
7523 // Add the callee.
7524 Ops.push_back(Callee);
7525
7526 // Adjust <numArgs> to account for any arguments that have been passed on the
7527 // stack instead.
7528 // Call Node: Chain, Target, {Args}, RegMask, [Glue]
7529 unsigned NumCallRegArgs = Call->getNumOperands() - (HasGlue ? 4 : 3);
7530 NumCallRegArgs = IsAnyRegCC ? NumArgs : NumCallRegArgs;
7531 Ops.push_back(DAG.getTargetConstant(NumCallRegArgs, dl, MVT::i32));
7532
7533 // Add the calling convention
7534 Ops.push_back(DAG.getTargetConstant((unsigned)CC, dl, MVT::i32));
7535
7536 // Add the arguments we omitted previously. The register allocator should
7537 // place these in any free register.
7538 if (IsAnyRegCC)
7539 for (unsigned i = NumMetaOpers, e = NumMetaOpers + NumArgs; i != e; ++i)
7540 Ops.push_back(getValue(CS.getArgument(i)));
7541
7542 // Push the arguments from the call instruction up to the register mask.
7543 SDNode::op_iterator e = HasGlue ? Call->op_end()-2 : Call->op_end()-1;
7544 Ops.append(Call->op_begin() + 2, e);
7545
7546 // Push live variables for the stack map.
7547 addStackMapLiveVars(CS, NumMetaOpers + NumArgs, dl, Ops, *this);
7548
7549 // Push the register mask info.
7550 if (HasGlue)
7551 Ops.push_back(*(Call->op_end()-2));
7552 else
7553 Ops.push_back(*(Call->op_end()-1));
7554
7555 // Push the chain (this is originally the first operand of the call, but
7556 // becomes now the last or second to last operand).
7557 Ops.push_back(*(Call->op_begin()));
7558
7559 // Push the glue flag (last operand).
7560 if (HasGlue)
7561 Ops.push_back(*(Call->op_end()-1));
7562
7563 SDVTList NodeTys;
7564 if (IsAnyRegCC && HasDef) {
7565 // Create the return types based on the intrinsic definition
7566 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7567 SmallVector<EVT, 3> ValueVTs;
7568 ComputeValueVTs(TLI, DAG.getDataLayout(), CS->getType(), ValueVTs);
7569 assert(ValueVTs.size() == 1 && "Expected only one return value type.")((ValueVTs.size() == 1 && "Expected only one return value type."
) ? static_cast<void> (0) : __assert_fail ("ValueVTs.size() == 1 && \"Expected only one return value type.\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7569, __PRETTY_FUNCTION__))
;
7570
7571 // There is always a chain and a glue type at the end
7572 ValueVTs.push_back(MVT::Other);
7573 ValueVTs.push_back(MVT::Glue);
7574 NodeTys = DAG.getVTList(ValueVTs);
7575 } else
7576 NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7577
7578 // Replace the target specific call node with a PATCHPOINT node.
7579 MachineSDNode *MN = DAG.getMachineNode(TargetOpcode::PATCHPOINT,
7580 dl, NodeTys, Ops);
7581
7582 // Update the NodeMap.
7583 if (HasDef) {
7584 if (IsAnyRegCC)
7585 setValue(CS.getInstruction(), SDValue(MN, 0));
7586 else
7587 setValue(CS.getInstruction(), Result.first);
7588 }
7589
7590 // Fixup the consumers of the intrinsic. The chain and glue may be used in the
7591 // call sequence. Furthermore the location of the chain and glue can change
7592 // when the AnyReg calling convention is used and the intrinsic returns a
7593 // value.
7594 if (IsAnyRegCC && HasDef) {
7595 SDValue From[] = {SDValue(Call, 0), SDValue(Call, 1)};
7596 SDValue To[] = {SDValue(MN, 1), SDValue(MN, 2)};
7597 DAG.ReplaceAllUsesOfValuesWith(From, To, 2);
7598 } else
7599 DAG.ReplaceAllUsesWith(Call, MN);
7600 DAG.DeleteNode(Call);
7601
7602 // Inform the Frame Information that we have a patchpoint in this function.
7603 FuncInfo.MF->getFrameInfo().setHasPatchPoint();
7604}
7605
7606/// Returns an AttributeSet representing the attributes applied to the return
7607/// value of the given call.
7608static AttributeSet getReturnAttrs(TargetLowering::CallLoweringInfo &CLI) {
7609 SmallVector<Attribute::AttrKind, 2> Attrs;
7610 if (CLI.RetSExt)
7611 Attrs.push_back(Attribute::SExt);
7612 if (CLI.RetZExt)
7613 Attrs.push_back(Attribute::ZExt);
7614 if (CLI.IsInReg)
7615 Attrs.push_back(Attribute::InReg);
7616
7617 return AttributeSet::get(CLI.RetTy->getContext(), AttributeSet::ReturnIndex,
7618 Attrs);
7619}
7620
7621/// TargetLowering::LowerCallTo - This is the default LowerCallTo
7622/// implementation, which just calls LowerCall.
7623/// FIXME: When all targets are
7624/// migrated to using LowerCall, this hook should be integrated into SDISel.
7625std::pair<SDValue, SDValue>
7626TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const {
7627 // Handle the incoming return values from the call.
7628 CLI.Ins.clear();
7629 Type *OrigRetTy = CLI.RetTy;
7630 SmallVector<EVT, 4> RetTys;
7631 SmallVector<uint64_t, 4> Offsets;
7632 auto &DL = CLI.DAG.getDataLayout();
7633 ComputeValueVTs(*this, DL, CLI.RetTy, RetTys, &Offsets);
7634
7635 SmallVector<ISD::OutputArg, 4> Outs;
7636 GetReturnInfo(CLI.RetTy, getReturnAttrs(CLI), Outs, *this, DL);
7637
7638 bool CanLowerReturn =
7639 this->CanLowerReturn(CLI.CallConv, CLI.DAG.getMachineFunction(),
7640 CLI.IsVarArg, Outs, CLI.RetTy->getContext());
7641
7642 SDValue DemoteStackSlot;
7643 int DemoteStackIdx = -100;
7644 if (!CanLowerReturn) {
7645 // FIXME: equivalent assert?
7646 // assert(!CS.hasInAllocaArgument() &&
7647 // "sret demotion is incompatible with inalloca");
7648 uint64_t TySize = DL.getTypeAllocSize(CLI.RetTy);
7649 unsigned Align = DL.getPrefTypeAlignment(CLI.RetTy);
7650 MachineFunction &MF = CLI.DAG.getMachineFunction();
7651 DemoteStackIdx = MF.getFrameInfo().CreateStackObject(TySize, Align, false);
7652 Type *StackSlotPtrType = PointerType::getUnqual(CLI.RetTy);
7653
7654 DemoteStackSlot = CLI.DAG.getFrameIndex(DemoteStackIdx, getPointerTy(DL));
7655 ArgListEntry Entry;
7656 Entry.Node = DemoteStackSlot;
7657 Entry.Ty = StackSlotPtrType;
7658 Entry.IsSExt = false;
7659 Entry.IsZExt = false;
7660 Entry.IsInReg = false;
7661 Entry.IsSRet = true;
7662 Entry.IsNest = false;
7663 Entry.IsByVal = false;
7664 Entry.IsReturned = false;
7665 Entry.IsSwiftSelf = false;
7666 Entry.IsSwiftError = false;
7667 Entry.Alignment = Align;
7668 CLI.getArgs().insert(CLI.getArgs().begin(), Entry);
7669 CLI.RetTy = Type::getVoidTy(CLI.RetTy->getContext());
7670
7671 // sret demotion isn't compatible with tail-calls, since the sret argument
7672 // points into the callers stack frame.
7673 CLI.IsTailCall = false;
7674 } else {
7675 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
7676 EVT VT = RetTys[I];
7677 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
7678 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
7679 for (unsigned i = 0; i != NumRegs; ++i) {
7680 ISD::InputArg MyFlags;
7681 MyFlags.VT = RegisterVT;
7682 MyFlags.ArgVT = VT;
7683 MyFlags.Used = CLI.IsReturnValueUsed;
7684 if (CLI.RetSExt)
7685 MyFlags.Flags.setSExt();
7686 if (CLI.RetZExt)
7687 MyFlags.Flags.setZExt();
7688 if (CLI.IsInReg)
7689 MyFlags.Flags.setInReg();
7690 CLI.Ins.push_back(MyFlags);
7691 }
7692 }
7693 }
7694
7695 // We push in swifterror return as the last element of CLI.Ins.
7696 ArgListTy &Args = CLI.getArgs();
7697 if (supportSwiftError()) {
7698 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
7699 if (Args[i].IsSwiftError) {
7700 ISD::InputArg MyFlags;
7701 MyFlags.VT = getPointerTy(DL);
7702 MyFlags.ArgVT = EVT(getPointerTy(DL));
7703 MyFlags.Flags.setSwiftError();
7704 CLI.Ins.push_back(MyFlags);
7705 }
7706 }
7707 }
7708
7709 // Handle all of the outgoing arguments.
7710 CLI.Outs.clear();
7711 CLI.OutVals.clear();
7712 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
7713 SmallVector<EVT, 4> ValueVTs;
7714 ComputeValueVTs(*this, DL, Args[i].Ty, ValueVTs);
7715 Type *FinalType = Args[i].Ty;
7716 if (Args[i].IsByVal)
7717 FinalType = cast<PointerType>(Args[i].Ty)->getElementType();
7718 bool NeedsRegBlock = functionArgumentNeedsConsecutiveRegisters(
7719 FinalType, CLI.CallConv, CLI.IsVarArg);
7720 for (unsigned Value = 0, NumValues = ValueVTs.size(); Value != NumValues;
7721 ++Value) {
7722 EVT VT = ValueVTs[Value];
7723 Type *ArgTy = VT.getTypeForEVT(CLI.RetTy->getContext());
7724 SDValue Op = SDValue(Args[i].Node.getNode(),
7725 Args[i].Node.getResNo() + Value);
7726 ISD::ArgFlagsTy Flags;
7727 unsigned OriginalAlignment = DL.getABITypeAlignment(ArgTy);
7728
7729 if (Args[i].IsZExt)
7730 Flags.setZExt();
7731 if (Args[i].IsSExt)
7732 Flags.setSExt();
7733 if (Args[i].IsInReg) {
7734 // If we are using vectorcall calling convention, a structure that is
7735 // passed InReg - is surely an HVA
7736 if (CLI.CallConv == CallingConv::X86_VectorCall &&
7737 isa<StructType>(FinalType)) {
7738 // The first value of a structure is marked
7739 if (0 == Value)
7740 Flags.setHvaStart();
7741 Flags.setHva();
7742 }
7743 // Set InReg Flag
7744 Flags.setInReg();
7745 }
7746 if (Args[i].IsSRet)
7747 Flags.setSRet();
7748 if (Args[i].IsSwiftSelf)
7749 Flags.setSwiftSelf();
7750 if (Args[i].IsSwiftError)
7751 Flags.setSwiftError();
7752 if (Args[i].IsByVal)
7753 Flags.setByVal();
7754 if (Args[i].IsInAlloca) {
7755 Flags.setInAlloca();
7756 // Set the byval flag for CCAssignFn callbacks that don't know about
7757 // inalloca. This way we can know how many bytes we should've allocated
7758 // and how many bytes a callee cleanup function will pop. If we port
7759 // inalloca to more targets, we'll have to add custom inalloca handling
7760 // in the va