Bug Summary

File:lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
Warning:line 7419, column 14
Forming reference to null pointer

Annotated Source Code

Press '?' to see keyboard shortcuts

clang -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name SelectionDAGBuilder.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mthread-model posix -fmath-errno -masm-verbose -mconstructor-aliases -munwind-tables -fuse-init-array -target-cpu x86-64 -dwarf-column-info -debugger-tuning=gdb -momit-leaf-frame-pointer -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-8/lib/clang/8.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-8~svn350071/build-llvm/lib/CodeGen/SelectionDAG -I /build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG -I /build/llvm-toolchain-snapshot-8~svn350071/build-llvm/include -I /build/llvm-toolchain-snapshot-8~svn350071/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0/backward -internal-isystem /usr/include/clang/8.0.0/include/ -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-8/lib/clang/8.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++11 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-8~svn350071/build-llvm/lib/CodeGen/SelectionDAG -fdebug-prefix-map=/build/llvm-toolchain-snapshot-8~svn350071=. -ferror-limit 19 -fmessage-length 0 -fvisibility-inlines-hidden -stack-protector 2 -fobjc-runtime=gcc -fdiagnostics-show-option -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -o /tmp/scan-build-2018-12-27-042839-1215-1 -x c++ /build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp -faddrsig
1//===- SelectionDAGBuilder.cpp - Selection-DAG building -------------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This implements routines for translating from LLVM IR into SelectionDAG IR.
11//
12//===----------------------------------------------------------------------===//
13
14#include "SelectionDAGBuilder.h"
15#include "SDNodeDbgValue.h"
16#include "llvm/ADT/APFloat.h"
17#include "llvm/ADT/APInt.h"
18#include "llvm/ADT/ArrayRef.h"
19#include "llvm/ADT/BitVector.h"
20#include "llvm/ADT/DenseMap.h"
21#include "llvm/ADT/None.h"
22#include "llvm/ADT/Optional.h"
23#include "llvm/ADT/STLExtras.h"
24#include "llvm/ADT/SmallPtrSet.h"
25#include "llvm/ADT/SmallSet.h"
26#include "llvm/ADT/SmallVector.h"
27#include "llvm/ADT/StringRef.h"
28#include "llvm/ADT/Triple.h"
29#include "llvm/ADT/Twine.h"
30#include "llvm/Analysis/AliasAnalysis.h"
31#include "llvm/Analysis/BranchProbabilityInfo.h"
32#include "llvm/Analysis/ConstantFolding.h"
33#include "llvm/Analysis/EHPersonalities.h"
34#include "llvm/Analysis/Loads.h"
35#include "llvm/Analysis/MemoryLocation.h"
36#include "llvm/Analysis/TargetLibraryInfo.h"
37#include "llvm/Analysis/ValueTracking.h"
38#include "llvm/Analysis/VectorUtils.h"
39#include "llvm/CodeGen/Analysis.h"
40#include "llvm/CodeGen/FunctionLoweringInfo.h"
41#include "llvm/CodeGen/GCMetadata.h"
42#include "llvm/CodeGen/ISDOpcodes.h"
43#include "llvm/CodeGen/MachineBasicBlock.h"
44#include "llvm/CodeGen/MachineFrameInfo.h"
45#include "llvm/CodeGen/MachineFunction.h"
46#include "llvm/CodeGen/MachineInstr.h"
47#include "llvm/CodeGen/MachineInstrBuilder.h"
48#include "llvm/CodeGen/MachineJumpTableInfo.h"
49#include "llvm/CodeGen/MachineMemOperand.h"
50#include "llvm/CodeGen/MachineModuleInfo.h"
51#include "llvm/CodeGen/MachineOperand.h"
52#include "llvm/CodeGen/MachineRegisterInfo.h"
53#include "llvm/CodeGen/RuntimeLibcalls.h"
54#include "llvm/CodeGen/SelectionDAG.h"
55#include "llvm/CodeGen/SelectionDAGNodes.h"
56#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
57#include "llvm/CodeGen/StackMaps.h"
58#include "llvm/CodeGen/TargetFrameLowering.h"
59#include "llvm/CodeGen/TargetInstrInfo.h"
60#include "llvm/CodeGen/TargetLowering.h"
61#include "llvm/CodeGen/TargetOpcodes.h"
62#include "llvm/CodeGen/TargetRegisterInfo.h"
63#include "llvm/CodeGen/TargetSubtargetInfo.h"
64#include "llvm/CodeGen/ValueTypes.h"
65#include "llvm/CodeGen/WinEHFuncInfo.h"
66#include "llvm/IR/Argument.h"
67#include "llvm/IR/Attributes.h"
68#include "llvm/IR/BasicBlock.h"
69#include "llvm/IR/CFG.h"
70#include "llvm/IR/CallSite.h"
71#include "llvm/IR/CallingConv.h"
72#include "llvm/IR/Constant.h"
73#include "llvm/IR/ConstantRange.h"
74#include "llvm/IR/Constants.h"
75#include "llvm/IR/DataLayout.h"
76#include "llvm/IR/DebugInfoMetadata.h"
77#include "llvm/IR/DebugLoc.h"
78#include "llvm/IR/DerivedTypes.h"
79#include "llvm/IR/Function.h"
80#include "llvm/IR/GetElementPtrTypeIterator.h"
81#include "llvm/IR/InlineAsm.h"
82#include "llvm/IR/InstrTypes.h"
83#include "llvm/IR/Instruction.h"
84#include "llvm/IR/Instructions.h"
85#include "llvm/IR/IntrinsicInst.h"
86#include "llvm/IR/Intrinsics.h"
87#include "llvm/IR/LLVMContext.h"
88#include "llvm/IR/Metadata.h"
89#include "llvm/IR/Module.h"
90#include "llvm/IR/Operator.h"
91#include "llvm/IR/PatternMatch.h"
92#include "llvm/IR/Statepoint.h"
93#include "llvm/IR/Type.h"
94#include "llvm/IR/User.h"
95#include "llvm/IR/Value.h"
96#include "llvm/MC/MCContext.h"
97#include "llvm/MC/MCSymbol.h"
98#include "llvm/Support/AtomicOrdering.h"
99#include "llvm/Support/BranchProbability.h"
100#include "llvm/Support/Casting.h"
101#include "llvm/Support/CodeGen.h"
102#include "llvm/Support/CommandLine.h"
103#include "llvm/Support/Compiler.h"
104#include "llvm/Support/Debug.h"
105#include "llvm/Support/ErrorHandling.h"
106#include "llvm/Support/MachineValueType.h"
107#include "llvm/Support/MathExtras.h"
108#include "llvm/Support/raw_ostream.h"
109#include "llvm/Target/TargetIntrinsicInfo.h"
110#include "llvm/Target/TargetMachine.h"
111#include "llvm/Target/TargetOptions.h"
112#include <algorithm>
113#include <cassert>
114#include <cstddef>
115#include <cstdint>
116#include <cstring>
117#include <iterator>
118#include <limits>
119#include <numeric>
120#include <tuple>
121#include <utility>
122#include <vector>
123
124using namespace llvm;
125using namespace PatternMatch;
126
127#define DEBUG_TYPE"isel" "isel"
128
129/// LimitFloatPrecision - Generate low-precision inline sequences for
130/// some float libcalls (6, 8 or 12 bits).
131static unsigned LimitFloatPrecision;
132
133static cl::opt<unsigned, true>
134 LimitFPPrecision("limit-float-precision",
135 cl::desc("Generate low-precision inline sequences "
136 "for some float libcalls"),
137 cl::location(LimitFloatPrecision), cl::Hidden,
138 cl::init(0));
139
140static cl::opt<unsigned> SwitchPeelThreshold(
141 "switch-peel-threshold", cl::Hidden, cl::init(66),
142 cl::desc("Set the case probability threshold for peeling the case from a "
143 "switch statement. A value greater than 100 will void this "
144 "optimization"));
145
146// Limit the width of DAG chains. This is important in general to prevent
147// DAG-based analysis from blowing up. For example, alias analysis and
148// load clustering may not complete in reasonable time. It is difficult to
149// recognize and avoid this situation within each individual analysis, and
150// future analyses are likely to have the same behavior. Limiting DAG width is
151// the safe approach and will be especially important with global DAGs.
152//
153// MaxParallelChains default is arbitrarily high to avoid affecting
154// optimization, but could be lowered to improve compile time. Any ld-ld-st-st
155// sequence over this should have been converted to llvm.memcpy by the
156// frontend. It is easy to induce this behavior with .ll code such as:
157// %buffer = alloca [4096 x i8]
158// %data = load [4096 x i8]* %argPtr
159// store [4096 x i8] %data, [4096 x i8]* %buffer
160static const unsigned MaxParallelChains = 64;
161
162// Return the calling convention if the Value passed requires ABI mangling as it
163// is a parameter to a function or a return value from a function which is not
164// an intrinsic.
165static Optional<CallingConv::ID> getABIRegCopyCC(const Value *V) {
166 if (auto *R = dyn_cast<ReturnInst>(V))
167 return R->getParent()->getParent()->getCallingConv();
168
169 if (auto *CI = dyn_cast<CallInst>(V)) {
170 const bool IsInlineAsm = CI->isInlineAsm();
171 const bool IsIndirectFunctionCall =
172 !IsInlineAsm && !CI->getCalledFunction();
173
174 // It is possible that the call instruction is an inline asm statement or an
175 // indirect function call in which case the return value of
176 // getCalledFunction() would be nullptr.
177 const bool IsInstrinsicCall =
178 !IsInlineAsm && !IsIndirectFunctionCall &&
179 CI->getCalledFunction()->getIntrinsicID() != Intrinsic::not_intrinsic;
180
181 if (!IsInlineAsm && !IsInstrinsicCall)
182 return CI->getCallingConv();
183 }
184
185 return None;
186}
187
188static SDValue getCopyFromPartsVector(SelectionDAG &DAG, const SDLoc &DL,
189 const SDValue *Parts, unsigned NumParts,
190 MVT PartVT, EVT ValueVT, const Value *V,
191 Optional<CallingConv::ID> CC);
192
193/// getCopyFromParts - Create a value that contains the specified legal parts
194/// combined into the value they represent. If the parts combine to a type
195/// larger than ValueVT then AssertOp can be used to specify whether the extra
196/// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
197/// (ISD::AssertSext).
198static SDValue getCopyFromParts(SelectionDAG &DAG, const SDLoc &DL,
199 const SDValue *Parts, unsigned NumParts,
200 MVT PartVT, EVT ValueVT, const Value *V,
201 Optional<CallingConv::ID> CC = None,
202 Optional<ISD::NodeType> AssertOp = None) {
203 if (ValueVT.isVector())
204 return getCopyFromPartsVector(DAG, DL, Parts, NumParts, PartVT, ValueVT, V,
205 CC);
206
207 assert(NumParts > 0 && "No parts to assemble!")((NumParts > 0 && "No parts to assemble!") ? static_cast
<void> (0) : __assert_fail ("NumParts > 0 && \"No parts to assemble!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 207, __PRETTY_FUNCTION__))
;
208 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
209 SDValue Val = Parts[0];
210
211 if (NumParts > 1) {
212 // Assemble the value from multiple parts.
213 if (ValueVT.isInteger()) {
214 unsigned PartBits = PartVT.getSizeInBits();
215 unsigned ValueBits = ValueVT.getSizeInBits();
216
217 // Assemble the power of 2 part.
218 unsigned RoundParts = NumParts & (NumParts - 1) ?
219 1 << Log2_32(NumParts) : NumParts;
220 unsigned RoundBits = PartBits * RoundParts;
221 EVT RoundVT = RoundBits == ValueBits ?
222 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
223 SDValue Lo, Hi;
224
225 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
226
227 if (RoundParts > 2) {
228 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2,
229 PartVT, HalfVT, V);
230 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2,
231 RoundParts / 2, PartVT, HalfVT, V);
232 } else {
233 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]);
234 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]);
235 }
236
237 if (DAG.getDataLayout().isBigEndian())
238 std::swap(Lo, Hi);
239
240 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
241
242 if (RoundParts < NumParts) {
243 // Assemble the trailing non-power-of-2 part.
244 unsigned OddParts = NumParts - RoundParts;
245 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
246 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts, OddParts, PartVT,
247 OddVT, V, CC);
248
249 // Combine the round and odd parts.
250 Lo = Val;
251 if (DAG.getDataLayout().isBigEndian())
252 std::swap(Lo, Hi);
253 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
254 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi);
255 Hi =
256 DAG.getNode(ISD::SHL, DL, TotalVT, Hi,
257 DAG.getConstant(Lo.getValueSizeInBits(), DL,
258 TLI.getPointerTy(DAG.getDataLayout())));
259 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo);
260 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi);
261 }
262 } else if (PartVT.isFloatingPoint()) {
263 // FP split into multiple FP parts (for ppcf128)
264 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 &&((ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 &&
"Unexpected split") ? static_cast<void> (0) : __assert_fail
("ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 && \"Unexpected split\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 265, __PRETTY_FUNCTION__))
265 "Unexpected split")((ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 &&
"Unexpected split") ? static_cast<void> (0) : __assert_fail
("ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 && \"Unexpected split\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 265, __PRETTY_FUNCTION__))
;
266 SDValue Lo, Hi;
267 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]);
268 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]);
269 if (TLI.hasBigEndianPartOrdering(ValueVT, DAG.getDataLayout()))
270 std::swap(Lo, Hi);
271 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi);
272 } else {
273 // FP split into integer parts (soft fp)
274 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&((ValueVT.isFloatingPoint() && PartVT.isInteger() &&
!PartVT.isVector() && "Unexpected split") ? static_cast
<void> (0) : __assert_fail ("ValueVT.isFloatingPoint() && PartVT.isInteger() && !PartVT.isVector() && \"Unexpected split\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 275, __PRETTY_FUNCTION__))
275 !PartVT.isVector() && "Unexpected split")((ValueVT.isFloatingPoint() && PartVT.isInteger() &&
!PartVT.isVector() && "Unexpected split") ? static_cast
<void> (0) : __assert_fail ("ValueVT.isFloatingPoint() && PartVT.isInteger() && !PartVT.isVector() && \"Unexpected split\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 275, __PRETTY_FUNCTION__))
;
276 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
277 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT, V, CC);
278 }
279 }
280
281 // There is now one part, held in Val. Correct it to match ValueVT.
282 // PartEVT is the type of the register class that holds the value.
283 // ValueVT is the type of the inline asm operation.
284 EVT PartEVT = Val.getValueType();
285
286 if (PartEVT == ValueVT)
287 return Val;
288
289 if (PartEVT.isInteger() && ValueVT.isFloatingPoint() &&
290 ValueVT.bitsLT(PartEVT)) {
291 // For an FP value in an integer part, we need to truncate to the right
292 // width first.
293 PartEVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
294 Val = DAG.getNode(ISD::TRUNCATE, DL, PartEVT, Val);
295 }
296
297 // Handle types that have the same size.
298 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits())
299 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
300
301 // Handle types with different sizes.
302 if (PartEVT.isInteger() && ValueVT.isInteger()) {
303 if (ValueVT.bitsLT(PartEVT)) {
304 // For a truncate, see if we have any information to
305 // indicate whether the truncated bits will always be
306 // zero or sign-extension.
307 if (AssertOp.hasValue())
308 Val = DAG.getNode(*AssertOp, DL, PartEVT, Val,
309 DAG.getValueType(ValueVT));
310 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
311 }
312 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val);
313 }
314
315 if (PartEVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
316 // FP_ROUND's are always exact here.
317 if (ValueVT.bitsLT(Val.getValueType()))
318 return DAG.getNode(
319 ISD::FP_ROUND, DL, ValueVT, Val,
320 DAG.getTargetConstant(1, DL, TLI.getPointerTy(DAG.getDataLayout())));
321
322 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);
323 }
324
325 llvm_unreachable("Unknown mismatch!")::llvm::llvm_unreachable_internal("Unknown mismatch!", "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 325)
;
326}
327
328static void diagnosePossiblyInvalidConstraint(LLVMContext &Ctx, const Value *V,
329 const Twine &ErrMsg) {
330 const Instruction *I = dyn_cast_or_null<Instruction>(V);
331 if (!V)
332 return Ctx.emitError(ErrMsg);
333
334 const char *AsmError = ", possible invalid constraint for vector type";
335 if (const CallInst *CI = dyn_cast<CallInst>(I))
336 if (isa<InlineAsm>(CI->getCalledValue()))
337 return Ctx.emitError(I, ErrMsg + AsmError);
338
339 return Ctx.emitError(I, ErrMsg);
340}
341
342/// getCopyFromPartsVector - Create a value that contains the specified legal
343/// parts combined into the value they represent. If the parts combine to a
344/// type larger than ValueVT then AssertOp can be used to specify whether the
345/// extra bits are known to be zero (ISD::AssertZext) or sign extended from
346/// ValueVT (ISD::AssertSext).
347static SDValue getCopyFromPartsVector(SelectionDAG &DAG, const SDLoc &DL,
348 const SDValue *Parts, unsigned NumParts,
349 MVT PartVT, EVT ValueVT, const Value *V,
350 Optional<CallingConv::ID> CallConv) {
351 assert(ValueVT.isVector() && "Not a vector value")((ValueVT.isVector() && "Not a vector value") ? static_cast
<void> (0) : __assert_fail ("ValueVT.isVector() && \"Not a vector value\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 351, __PRETTY_FUNCTION__))
;
352 assert(NumParts > 0 && "No parts to assemble!")((NumParts > 0 && "No parts to assemble!") ? static_cast
<void> (0) : __assert_fail ("NumParts > 0 && \"No parts to assemble!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 352, __PRETTY_FUNCTION__))
;
353 const bool IsABIRegCopy = CallConv.hasValue();
354
355 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
356 SDValue Val = Parts[0];
357
358 // Handle a multi-element vector.
359 if (NumParts > 1) {
360 EVT IntermediateVT;
361 MVT RegisterVT;
362 unsigned NumIntermediates;
363 unsigned NumRegs;
364
365 if (IsABIRegCopy) {
366 NumRegs = TLI.getVectorTypeBreakdownForCallingConv(
367 *DAG.getContext(), CallConv.getValue(), ValueVT, IntermediateVT,
368 NumIntermediates, RegisterVT);
369 } else {
370 NumRegs =
371 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
372 NumIntermediates, RegisterVT);
373 }
374
375 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!")((NumRegs == NumParts && "Part count doesn't match vector breakdown!"
) ? static_cast<void> (0) : __assert_fail ("NumRegs == NumParts && \"Part count doesn't match vector breakdown!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 375, __PRETTY_FUNCTION__))
;
376 NumParts = NumRegs; // Silence a compiler warning.
377 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!")((RegisterVT == PartVT && "Part type doesn't match vector breakdown!"
) ? static_cast<void> (0) : __assert_fail ("RegisterVT == PartVT && \"Part type doesn't match vector breakdown!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 377, __PRETTY_FUNCTION__))
;
378 assert(RegisterVT.getSizeInBits() ==((RegisterVT.getSizeInBits() == Parts[0].getSimpleValueType()
.getSizeInBits() && "Part type sizes don't match!") ?
static_cast<void> (0) : __assert_fail ("RegisterVT.getSizeInBits() == Parts[0].getSimpleValueType().getSizeInBits() && \"Part type sizes don't match!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 380, __PRETTY_FUNCTION__))
379 Parts[0].getSimpleValueType().getSizeInBits() &&((RegisterVT.getSizeInBits() == Parts[0].getSimpleValueType()
.getSizeInBits() && "Part type sizes don't match!") ?
static_cast<void> (0) : __assert_fail ("RegisterVT.getSizeInBits() == Parts[0].getSimpleValueType().getSizeInBits() && \"Part type sizes don't match!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 380, __PRETTY_FUNCTION__))
380 "Part type sizes don't match!")((RegisterVT.getSizeInBits() == Parts[0].getSimpleValueType()
.getSizeInBits() && "Part type sizes don't match!") ?
static_cast<void> (0) : __assert_fail ("RegisterVT.getSizeInBits() == Parts[0].getSimpleValueType().getSizeInBits() && \"Part type sizes don't match!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 380, __PRETTY_FUNCTION__))
;
381
382 // Assemble the parts into intermediate operands.
383 SmallVector<SDValue, 8> Ops(NumIntermediates);
384 if (NumIntermediates == NumParts) {
385 // If the register was not expanded, truncate or copy the value,
386 // as appropriate.
387 for (unsigned i = 0; i != NumParts; ++i)
388 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1,
389 PartVT, IntermediateVT, V);
390 } else if (NumParts > 0) {
391 // If the intermediate type was expanded, build the intermediate
392 // operands from the parts.
393 assert(NumParts % NumIntermediates == 0 &&((NumParts % NumIntermediates == 0 && "Must expand into a divisible number of parts!"
) ? static_cast<void> (0) : __assert_fail ("NumParts % NumIntermediates == 0 && \"Must expand into a divisible number of parts!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 394, __PRETTY_FUNCTION__))
394 "Must expand into a divisible number of parts!")((NumParts % NumIntermediates == 0 && "Must expand into a divisible number of parts!"
) ? static_cast<void> (0) : __assert_fail ("NumParts % NumIntermediates == 0 && \"Must expand into a divisible number of parts!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 394, __PRETTY_FUNCTION__))
;
395 unsigned Factor = NumParts / NumIntermediates;
396 for (unsigned i = 0; i != NumIntermediates; ++i)
397 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor,
398 PartVT, IntermediateVT, V);
399 }
400
401 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
402 // intermediate operands.
403 EVT BuiltVectorTy =
404 EVT::getVectorVT(*DAG.getContext(), IntermediateVT.getScalarType(),
405 (IntermediateVT.isVector()
406 ? IntermediateVT.getVectorNumElements() * NumParts
407 : NumIntermediates));
408 Val = DAG.getNode(IntermediateVT.isVector() ? ISD::CONCAT_VECTORS
409 : ISD::BUILD_VECTOR,
410 DL, BuiltVectorTy, Ops);
411 }
412
413 // There is now one part, held in Val. Correct it to match ValueVT.
414 EVT PartEVT = Val.getValueType();
415
416 if (PartEVT == ValueVT)
417 return Val;
418
419 if (PartEVT.isVector()) {
420 // If the element type of the source/dest vectors are the same, but the
421 // parts vector has more elements than the value vector, then we have a
422 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the
423 // elements we want.
424 if (PartEVT.getVectorElementType() == ValueVT.getVectorElementType()) {
425 assert(PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements() &&((PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements
() && "Cannot narrow, it would be a lossy transformation"
) ? static_cast<void> (0) : __assert_fail ("PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements() && \"Cannot narrow, it would be a lossy transformation\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 426, __PRETTY_FUNCTION__))
426 "Cannot narrow, it would be a lossy transformation")((PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements
() && "Cannot narrow, it would be a lossy transformation"
) ? static_cast<void> (0) : __assert_fail ("PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements() && \"Cannot narrow, it would be a lossy transformation\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 426, __PRETTY_FUNCTION__))
;
427 return DAG.getNode(
428 ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
429 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
430 }
431
432 // Vector/Vector bitcast.
433 if (ValueVT.getSizeInBits() == PartEVT.getSizeInBits())
434 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
435
436 assert(PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements() &&((PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements
() && "Cannot handle this kind of promotion") ? static_cast
<void> (0) : __assert_fail ("PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements() && \"Cannot handle this kind of promotion\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 437, __PRETTY_FUNCTION__))
437 "Cannot handle this kind of promotion")((PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements
() && "Cannot handle this kind of promotion") ? static_cast
<void> (0) : __assert_fail ("PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements() && \"Cannot handle this kind of promotion\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 437, __PRETTY_FUNCTION__))
;
438 // Promoted vector extract
439 return DAG.getAnyExtOrTrunc(Val, DL, ValueVT);
440
441 }
442
443 // Trivial bitcast if the types are the same size and the destination
444 // vector type is legal.
445 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits() &&
446 TLI.isTypeLegal(ValueVT))
447 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
448
449 if (ValueVT.getVectorNumElements() != 1) {
450 // Certain ABIs require that vectors are passed as integers. For vectors
451 // are the same size, this is an obvious bitcast.
452 if (ValueVT.getSizeInBits() == PartEVT.getSizeInBits()) {
453 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
454 } else if (ValueVT.getSizeInBits() < PartEVT.getSizeInBits()) {
455 // Bitcast Val back the original type and extract the corresponding
456 // vector we want.
457 unsigned Elts = PartEVT.getSizeInBits() / ValueVT.getScalarSizeInBits();
458 EVT WiderVecType = EVT::getVectorVT(*DAG.getContext(),
459 ValueVT.getVectorElementType(), Elts);
460 Val = DAG.getBitcast(WiderVecType, Val);
461 return DAG.getNode(
462 ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
463 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
464 }
465
466 diagnosePossiblyInvalidConstraint(
467 *DAG.getContext(), V, "non-trivial scalar-to-vector conversion");
468 return DAG.getUNDEF(ValueVT);
469 }
470
471 // Handle cases such as i8 -> <1 x i1>
472 EVT ValueSVT = ValueVT.getVectorElementType();
473 if (ValueVT.getVectorNumElements() == 1 && ValueSVT != PartEVT)
474 Val = ValueVT.isFloatingPoint() ? DAG.getFPExtendOrRound(Val, DL, ValueSVT)
475 : DAG.getAnyExtOrTrunc(Val, DL, ValueSVT);
476
477 return DAG.getBuildVector(ValueVT, DL, Val);
478}
479
480static void getCopyToPartsVector(SelectionDAG &DAG, const SDLoc &dl,
481 SDValue Val, SDValue *Parts, unsigned NumParts,
482 MVT PartVT, const Value *V,
483 Optional<CallingConv::ID> CallConv);
484
485/// getCopyToParts - Create a series of nodes that contain the specified value
486/// split into legal parts. If the parts contain more bits than Val, then, for
487/// integers, ExtendKind can be used to specify how to generate the extra bits.
488static void getCopyToParts(SelectionDAG &DAG, const SDLoc &DL, SDValue Val,
489 SDValue *Parts, unsigned NumParts, MVT PartVT,
490 const Value *V,
491 Optional<CallingConv::ID> CallConv = None,
492 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
493 EVT ValueVT = Val.getValueType();
494
495 // Handle the vector case separately.
496 if (ValueVT.isVector())
497 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT, V,
498 CallConv);
499
500 unsigned PartBits = PartVT.getSizeInBits();
501 unsigned OrigNumParts = NumParts;
502 assert(DAG.getTargetLoweringInfo().isTypeLegal(PartVT) &&((DAG.getTargetLoweringInfo().isTypeLegal(PartVT) && "Copying to an illegal type!"
) ? static_cast<void> (0) : __assert_fail ("DAG.getTargetLoweringInfo().isTypeLegal(PartVT) && \"Copying to an illegal type!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 503, __PRETTY_FUNCTION__))
503 "Copying to an illegal type!")((DAG.getTargetLoweringInfo().isTypeLegal(PartVT) && "Copying to an illegal type!"
) ? static_cast<void> (0) : __assert_fail ("DAG.getTargetLoweringInfo().isTypeLegal(PartVT) && \"Copying to an illegal type!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 503, __PRETTY_FUNCTION__))
;
504
505 if (NumParts == 0)
506 return;
507
508 assert(!ValueVT.isVector() && "Vector case handled elsewhere")((!ValueVT.isVector() && "Vector case handled elsewhere"
) ? static_cast<void> (0) : __assert_fail ("!ValueVT.isVector() && \"Vector case handled elsewhere\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 508, __PRETTY_FUNCTION__))
;
509 EVT PartEVT = PartVT;
510 if (PartEVT == ValueVT) {
511 assert(NumParts == 1 && "No-op copy with multiple parts!")((NumParts == 1 && "No-op copy with multiple parts!")
? static_cast<void> (0) : __assert_fail ("NumParts == 1 && \"No-op copy with multiple parts!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 511, __PRETTY_FUNCTION__))
;
512 Parts[0] = Val;
513 return;
514 }
515
516 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
517 // If the parts cover more bits than the value has, promote the value.
518 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
519 assert(NumParts == 1 && "Do not know what to promote to!")((NumParts == 1 && "Do not know what to promote to!")
? static_cast<void> (0) : __assert_fail ("NumParts == 1 && \"Do not know what to promote to!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 519, __PRETTY_FUNCTION__))
;
520 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val);
521 } else {
522 if (ValueVT.isFloatingPoint()) {
523 // FP values need to be bitcast, then extended if they are being put
524 // into a larger container.
525 ValueVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
526 Val = DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
527 }
528 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&(((PartVT.isInteger() || PartVT == MVT::x86mmx) && ValueVT
.isInteger() && "Unknown mismatch!") ? static_cast<
void> (0) : __assert_fail ("(PartVT.isInteger() || PartVT == MVT::x86mmx) && ValueVT.isInteger() && \"Unknown mismatch!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 530, __PRETTY_FUNCTION__))
529 ValueVT.isInteger() &&(((PartVT.isInteger() || PartVT == MVT::x86mmx) && ValueVT
.isInteger() && "Unknown mismatch!") ? static_cast<
void> (0) : __assert_fail ("(PartVT.isInteger() || PartVT == MVT::x86mmx) && ValueVT.isInteger() && \"Unknown mismatch!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 530, __PRETTY_FUNCTION__))
530 "Unknown mismatch!")(((PartVT.isInteger() || PartVT == MVT::x86mmx) && ValueVT
.isInteger() && "Unknown mismatch!") ? static_cast<
void> (0) : __assert_fail ("(PartVT.isInteger() || PartVT == MVT::x86mmx) && ValueVT.isInteger() && \"Unknown mismatch!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 530, __PRETTY_FUNCTION__))
;
531 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
532 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val);
533 if (PartVT == MVT::x86mmx)
534 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
535 }
536 } else if (PartBits == ValueVT.getSizeInBits()) {
537 // Different types of the same size.
538 assert(NumParts == 1 && PartEVT != ValueVT)((NumParts == 1 && PartEVT != ValueVT) ? static_cast<
void> (0) : __assert_fail ("NumParts == 1 && PartEVT != ValueVT"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 538, __PRETTY_FUNCTION__))
;
539 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
540 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
541 // If the parts cover less bits than value has, truncate the value.
542 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&(((PartVT.isInteger() || PartVT == MVT::x86mmx) && ValueVT
.isInteger() && "Unknown mismatch!") ? static_cast<
void> (0) : __assert_fail ("(PartVT.isInteger() || PartVT == MVT::x86mmx) && ValueVT.isInteger() && \"Unknown mismatch!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 544, __PRETTY_FUNCTION__))
543 ValueVT.isInteger() &&(((PartVT.isInteger() || PartVT == MVT::x86mmx) && ValueVT
.isInteger() && "Unknown mismatch!") ? static_cast<
void> (0) : __assert_fail ("(PartVT.isInteger() || PartVT == MVT::x86mmx) && ValueVT.isInteger() && \"Unknown mismatch!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 544, __PRETTY_FUNCTION__))
544 "Unknown mismatch!")(((PartVT.isInteger() || PartVT == MVT::x86mmx) && ValueVT
.isInteger() && "Unknown mismatch!") ? static_cast<
void> (0) : __assert_fail ("(PartVT.isInteger() || PartVT == MVT::x86mmx) && ValueVT.isInteger() && \"Unknown mismatch!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 544, __PRETTY_FUNCTION__))
;
545 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
546 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
547 if (PartVT == MVT::x86mmx)
548 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
549 }
550
551 // The value may have changed - recompute ValueVT.
552 ValueVT = Val.getValueType();
553 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&((NumParts * PartBits == ValueVT.getSizeInBits() && "Failed to tile the value with PartVT!"
) ? static_cast<void> (0) : __assert_fail ("NumParts * PartBits == ValueVT.getSizeInBits() && \"Failed to tile the value with PartVT!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 554, __PRETTY_FUNCTION__))
554 "Failed to tile the value with PartVT!")((NumParts * PartBits == ValueVT.getSizeInBits() && "Failed to tile the value with PartVT!"
) ? static_cast<void> (0) : __assert_fail ("NumParts * PartBits == ValueVT.getSizeInBits() && \"Failed to tile the value with PartVT!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 554, __PRETTY_FUNCTION__))
;
555
556 if (NumParts == 1) {
557 if (PartEVT != ValueVT) {
558 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
559 "scalar-to-vector conversion failed");
560 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
561 }
562
563 Parts[0] = Val;
564 return;
565 }
566
567 // Expand the value into multiple parts.
568 if (NumParts & (NumParts - 1)) {
569 // The number of parts is not a power of 2. Split off and copy the tail.
570 assert(PartVT.isInteger() && ValueVT.isInteger() &&((PartVT.isInteger() && ValueVT.isInteger() &&
"Do not know what to expand to!") ? static_cast<void> (
0) : __assert_fail ("PartVT.isInteger() && ValueVT.isInteger() && \"Do not know what to expand to!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 571, __PRETTY_FUNCTION__))
571 "Do not know what to expand to!")((PartVT.isInteger() && ValueVT.isInteger() &&
"Do not know what to expand to!") ? static_cast<void> (
0) : __assert_fail ("PartVT.isInteger() && ValueVT.isInteger() && \"Do not know what to expand to!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 571, __PRETTY_FUNCTION__))
;
572 unsigned RoundParts = 1 << Log2_32(NumParts);
573 unsigned RoundBits = RoundParts * PartBits;
574 unsigned OddParts = NumParts - RoundParts;
575 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val,
576 DAG.getIntPtrConstant(RoundBits, DL));
577 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT, V,
578 CallConv);
579
580 if (DAG.getDataLayout().isBigEndian())
581 // The odd parts were reversed by getCopyToParts - unreverse them.
582 std::reverse(Parts + RoundParts, Parts + NumParts);
583
584 NumParts = RoundParts;
585 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
586 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
587 }
588
589 // The number of parts is a power of 2. Repeatedly bisect the value using
590 // EXTRACT_ELEMENT.
591 Parts[0] = DAG.getNode(ISD::BITCAST, DL,
592 EVT::getIntegerVT(*DAG.getContext(),
593 ValueVT.getSizeInBits()),
594 Val);
595
596 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
597 for (unsigned i = 0; i < NumParts; i += StepSize) {
598 unsigned ThisBits = StepSize * PartBits / 2;
599 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
600 SDValue &Part0 = Parts[i];
601 SDValue &Part1 = Parts[i+StepSize/2];
602
603 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
604 ThisVT, Part0, DAG.getIntPtrConstant(1, DL));
605 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
606 ThisVT, Part0, DAG.getIntPtrConstant(0, DL));
607
608 if (ThisBits == PartBits && ThisVT != PartVT) {
609 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0);
610 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1);
611 }
612 }
613 }
614
615 if (DAG.getDataLayout().isBigEndian())
616 std::reverse(Parts, Parts + OrigNumParts);
617}
618
619static SDValue widenVectorToPartType(SelectionDAG &DAG,
620 SDValue Val, const SDLoc &DL, EVT PartVT) {
621 if (!PartVT.isVector())
622 return SDValue();
623
624 EVT ValueVT = Val.getValueType();
625 unsigned PartNumElts = PartVT.getVectorNumElements();
626 unsigned ValueNumElts = ValueVT.getVectorNumElements();
627 if (PartNumElts > ValueNumElts &&
628 PartVT.getVectorElementType() == ValueVT.getVectorElementType()) {
629 EVT ElementVT = PartVT.getVectorElementType();
630 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in
631 // undef elements.
632 SmallVector<SDValue, 16> Ops;
633 DAG.ExtractVectorElements(Val, Ops);
634 SDValue EltUndef = DAG.getUNDEF(ElementVT);
635 for (unsigned i = ValueNumElts, e = PartNumElts; i != e; ++i)
636 Ops.push_back(EltUndef);
637
638 // FIXME: Use CONCAT for 2x -> 4x.
639 return DAG.getBuildVector(PartVT, DL, Ops);
640 }
641
642 return SDValue();
643}
644
645/// getCopyToPartsVector - Create a series of nodes that contain the specified
646/// value split into legal parts.
647static void getCopyToPartsVector(SelectionDAG &DAG, const SDLoc &DL,
648 SDValue Val, SDValue *Parts, unsigned NumParts,
649 MVT PartVT, const Value *V,
650 Optional<CallingConv::ID> CallConv) {
651 EVT ValueVT = Val.getValueType();
652 assert(ValueVT.isVector() && "Not a vector")((ValueVT.isVector() && "Not a vector") ? static_cast
<void> (0) : __assert_fail ("ValueVT.isVector() && \"Not a vector\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 652, __PRETTY_FUNCTION__))
;
653 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
654 const bool IsABIRegCopy = CallConv.hasValue();
655
656 if (NumParts == 1) {
657 EVT PartEVT = PartVT;
658 if (PartEVT == ValueVT) {
659 // Nothing to do.
660 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
661 // Bitconvert vector->vector case.
662 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
663 } else if (SDValue Widened = widenVectorToPartType(DAG, Val, DL, PartVT)) {
664 Val = Widened;
665 } else if (PartVT.isVector() &&
666 PartEVT.getVectorElementType().bitsGE(
667 ValueVT.getVectorElementType()) &&
668 PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements()) {
669
670 // Promoted vector extract
671 Val = DAG.getAnyExtOrTrunc(Val, DL, PartVT);
672 } else {
673 if (ValueVT.getVectorNumElements() == 1) {
674 Val = DAG.getNode(
675 ISD::EXTRACT_VECTOR_ELT, DL, PartVT, Val,
676 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
677 } else {
678 assert(PartVT.getSizeInBits() > ValueVT.getSizeInBits() &&((PartVT.getSizeInBits() > ValueVT.getSizeInBits() &&
"lossy conversion of vector to scalar type") ? static_cast<
void> (0) : __assert_fail ("PartVT.getSizeInBits() > ValueVT.getSizeInBits() && \"lossy conversion of vector to scalar type\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 679, __PRETTY_FUNCTION__))
679 "lossy conversion of vector to scalar type")((PartVT.getSizeInBits() > ValueVT.getSizeInBits() &&
"lossy conversion of vector to scalar type") ? static_cast<
void> (0) : __assert_fail ("PartVT.getSizeInBits() > ValueVT.getSizeInBits() && \"lossy conversion of vector to scalar type\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 679, __PRETTY_FUNCTION__))
;
680 EVT IntermediateType =
681 EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
682 Val = DAG.getBitcast(IntermediateType, Val);
683 Val = DAG.getAnyExtOrTrunc(Val, DL, PartVT);
684 }
685 }
686
687 assert(Val.getValueType() == PartVT && "Unexpected vector part value type")((Val.getValueType() == PartVT && "Unexpected vector part value type"
) ? static_cast<void> (0) : __assert_fail ("Val.getValueType() == PartVT && \"Unexpected vector part value type\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 687, __PRETTY_FUNCTION__))
;
688 Parts[0] = Val;
689 return;
690 }
691
692 // Handle a multi-element vector.
693 EVT IntermediateVT;
694 MVT RegisterVT;
695 unsigned NumIntermediates;
696 unsigned NumRegs;
697 if (IsABIRegCopy) {
698 NumRegs = TLI.getVectorTypeBreakdownForCallingConv(
699 *DAG.getContext(), CallConv.getValue(), ValueVT, IntermediateVT,
700 NumIntermediates, RegisterVT);
701 } else {
702 NumRegs =
703 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
704 NumIntermediates, RegisterVT);
705 }
706
707 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!")((NumRegs == NumParts && "Part count doesn't match vector breakdown!"
) ? static_cast<void> (0) : __assert_fail ("NumRegs == NumParts && \"Part count doesn't match vector breakdown!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 707, __PRETTY_FUNCTION__))
;
708 NumParts = NumRegs; // Silence a compiler warning.
709 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!")((RegisterVT == PartVT && "Part type doesn't match vector breakdown!"
) ? static_cast<void> (0) : __assert_fail ("RegisterVT == PartVT && \"Part type doesn't match vector breakdown!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 709, __PRETTY_FUNCTION__))
;
710
711 unsigned IntermediateNumElts = IntermediateVT.isVector() ?
712 IntermediateVT.getVectorNumElements() : 1;
713
714 // Convert the vector to the appropiate type if necessary.
715 unsigned DestVectorNoElts = NumIntermediates * IntermediateNumElts;
716
717 EVT BuiltVectorTy = EVT::getVectorVT(
718 *DAG.getContext(), IntermediateVT.getScalarType(), DestVectorNoElts);
719 MVT IdxVT = TLI.getVectorIdxTy(DAG.getDataLayout());
720 if (ValueVT != BuiltVectorTy) {
721 if (SDValue Widened = widenVectorToPartType(DAG, Val, DL, BuiltVectorTy))
722 Val = Widened;
723
724 Val = DAG.getNode(ISD::BITCAST, DL, BuiltVectorTy, Val);
725 }
726
727 // Split the vector into intermediate operands.
728 SmallVector<SDValue, 8> Ops(NumIntermediates);
729 for (unsigned i = 0; i != NumIntermediates; ++i) {
730 if (IntermediateVT.isVector()) {
731 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, IntermediateVT, Val,
732 DAG.getConstant(i * IntermediateNumElts, DL, IdxVT));
733 } else {
734 Ops[i] = DAG.getNode(
735 ISD::EXTRACT_VECTOR_ELT, DL, IntermediateVT, Val,
736 DAG.getConstant(i, DL, IdxVT));
737 }
738 }
739
740 // Split the intermediate operands into legal parts.
741 if (NumParts == NumIntermediates) {
742 // If the register was not expanded, promote or copy the value,
743 // as appropriate.
744 for (unsigned i = 0; i != NumParts; ++i)
745 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT, V, CallConv);
746 } else if (NumParts > 0) {
747 // If the intermediate type was expanded, split each the value into
748 // legal parts.
749 assert(NumIntermediates != 0 && "division by zero")((NumIntermediates != 0 && "division by zero") ? static_cast
<void> (0) : __assert_fail ("NumIntermediates != 0 && \"division by zero\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 749, __PRETTY_FUNCTION__))
;
750 assert(NumParts % NumIntermediates == 0 &&((NumParts % NumIntermediates == 0 && "Must expand into a divisible number of parts!"
) ? static_cast<void> (0) : __assert_fail ("NumParts % NumIntermediates == 0 && \"Must expand into a divisible number of parts!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 751, __PRETTY_FUNCTION__))
751 "Must expand into a divisible number of parts!")((NumParts % NumIntermediates == 0 && "Must expand into a divisible number of parts!"
) ? static_cast<void> (0) : __assert_fail ("NumParts % NumIntermediates == 0 && \"Must expand into a divisible number of parts!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 751, __PRETTY_FUNCTION__))
;
752 unsigned Factor = NumParts / NumIntermediates;
753 for (unsigned i = 0; i != NumIntermediates; ++i)
754 getCopyToParts(DAG, DL, Ops[i], &Parts[i * Factor], Factor, PartVT, V,
755 CallConv);
756 }
757}
758
759RegsForValue::RegsForValue(const SmallVector<unsigned, 4> &regs, MVT regvt,
760 EVT valuevt, Optional<CallingConv::ID> CC)
761 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs),
762 RegCount(1, regs.size()), CallConv(CC) {}
763
764RegsForValue::RegsForValue(LLVMContext &Context, const TargetLowering &TLI,
765 const DataLayout &DL, unsigned Reg, Type *Ty,
766 Optional<CallingConv::ID> CC) {
767 ComputeValueVTs(TLI, DL, Ty, ValueVTs);
768
769 CallConv = CC;
770
771 for (EVT ValueVT : ValueVTs) {
772 unsigned NumRegs =
773 isABIMangled()
774 ? TLI.getNumRegistersForCallingConv(Context, CC.getValue(), ValueVT)
775 : TLI.getNumRegisters(Context, ValueVT);
776 MVT RegisterVT =
777 isABIMangled()
778 ? TLI.getRegisterTypeForCallingConv(Context, CC.getValue(), ValueVT)
779 : TLI.getRegisterType(Context, ValueVT);
780 for (unsigned i = 0; i != NumRegs; ++i)
781 Regs.push_back(Reg + i);
782 RegVTs.push_back(RegisterVT);
783 RegCount.push_back(NumRegs);
784 Reg += NumRegs;
785 }
786}
787
788SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
789 FunctionLoweringInfo &FuncInfo,
790 const SDLoc &dl, SDValue &Chain,
791 SDValue *Flag, const Value *V) const {
792 // A Value with type {} or [0 x %t] needs no registers.
793 if (ValueVTs.empty())
794 return SDValue();
795
796 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
797
798 // Assemble the legal parts into the final values.
799 SmallVector<SDValue, 4> Values(ValueVTs.size());
800 SmallVector<SDValue, 8> Parts;
801 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
802 // Copy the legal parts from the registers.
803 EVT ValueVT = ValueVTs[Value];
804 unsigned NumRegs = RegCount[Value];
805 MVT RegisterVT = isABIMangled() ? TLI.getRegisterTypeForCallingConv(
806 *DAG.getContext(),
807 CallConv.getValue(), RegVTs[Value])
808 : RegVTs[Value];
809
810 Parts.resize(NumRegs);
811 for (unsigned i = 0; i != NumRegs; ++i) {
812 SDValue P;
813 if (!Flag) {
814 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
815 } else {
816 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
817 *Flag = P.getValue(2);
818 }
819
820 Chain = P.getValue(1);
821 Parts[i] = P;
822
823 // If the source register was virtual and if we know something about it,
824 // add an assert node.
825 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) ||
826 !RegisterVT.isInteger())
827 continue;
828
829 const FunctionLoweringInfo::LiveOutInfo *LOI =
830 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]);
831 if (!LOI)
832 continue;
833
834 unsigned RegSize = RegisterVT.getScalarSizeInBits();
835 unsigned NumSignBits = LOI->NumSignBits;
836 unsigned NumZeroBits = LOI->Known.countMinLeadingZeros();
837
838 if (NumZeroBits == RegSize) {
839 // The current value is a zero.
840 // Explicitly express that as it would be easier for
841 // optimizations to kick in.
842 Parts[i] = DAG.getConstant(0, dl, RegisterVT);
843 continue;
844 }
845
846 // FIXME: We capture more information than the dag can represent. For
847 // now, just use the tightest assertzext/assertsext possible.
848 bool isSExt;
849 EVT FromVT(MVT::Other);
850 if (NumZeroBits) {
851 FromVT = EVT::getIntegerVT(*DAG.getContext(), RegSize - NumZeroBits);
852 isSExt = false;
853 } else if (NumSignBits > 1) {
854 FromVT =
855 EVT::getIntegerVT(*DAG.getContext(), RegSize - NumSignBits + 1);
856 isSExt = true;
857 } else {
858 continue;
859 }
860 // Add an assertion node.
861 assert(FromVT != MVT::Other)((FromVT != MVT::Other) ? static_cast<void> (0) : __assert_fail
("FromVT != MVT::Other", "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 861, __PRETTY_FUNCTION__))
;
862 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
863 RegisterVT, P, DAG.getValueType(FromVT));
864 }
865
866 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(), NumRegs,
867 RegisterVT, ValueVT, V, CallConv);
868 Part += NumRegs;
869 Parts.clear();
870 }
871
872 return DAG.getNode(ISD::MERGE_VALUES, dl, DAG.getVTList(ValueVTs), Values);
873}
874
875void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG,
876 const SDLoc &dl, SDValue &Chain, SDValue *Flag,
877 const Value *V,
878 ISD::NodeType PreferredExtendType) const {
879 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
880 ISD::NodeType ExtendKind = PreferredExtendType;
881
882 // Get the list of the values's legal parts.
883 unsigned NumRegs = Regs.size();
884 SmallVector<SDValue, 8> Parts(NumRegs);
885 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
886 unsigned NumParts = RegCount[Value];
887
888 MVT RegisterVT = isABIMangled() ? TLI.getRegisterTypeForCallingConv(
889 *DAG.getContext(),
890 CallConv.getValue(), RegVTs[Value])
891 : RegVTs[Value];
892
893 if (ExtendKind == ISD::ANY_EXTEND && TLI.isZExtFree(Val, RegisterVT))
894 ExtendKind = ISD::ZERO_EXTEND;
895
896 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value), &Parts[Part],
897 NumParts, RegisterVT, V, CallConv, ExtendKind);
898 Part += NumParts;
899 }
900
901 // Copy the parts into the registers.
902 SmallVector<SDValue, 8> Chains(NumRegs);
903 for (unsigned i = 0; i != NumRegs; ++i) {
904 SDValue Part;
905 if (!Flag) {
906 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
907 } else {
908 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
909 *Flag = Part.getValue(1);
910 }
911
912 Chains[i] = Part.getValue(0);
913 }
914
915 if (NumRegs == 1 || Flag)
916 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
917 // flagged to it. That is the CopyToReg nodes and the user are considered
918 // a single scheduling unit. If we create a TokenFactor and return it as
919 // chain, then the TokenFactor is both a predecessor (operand) of the
920 // user as well as a successor (the TF operands are flagged to the user).
921 // c1, f1 = CopyToReg
922 // c2, f2 = CopyToReg
923 // c3 = TokenFactor c1, c2
924 // ...
925 // = op c3, ..., f2
926 Chain = Chains[NumRegs-1];
927 else
928 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
929}
930
931void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
932 unsigned MatchingIdx, const SDLoc &dl,
933 SelectionDAG &DAG,
934 std::vector<SDValue> &Ops) const {
935 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
936
937 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size());
938 if (HasMatching)
939 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx);
940 else if (!Regs.empty() &&
941 TargetRegisterInfo::isVirtualRegister(Regs.front())) {
942 // Put the register class of the virtual registers in the flag word. That
943 // way, later passes can recompute register class constraints for inline
944 // assembly as well as normal instructions.
945 // Don't do this for tied operands that can use the regclass information
946 // from the def.
947 const MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
948 const TargetRegisterClass *RC = MRI.getRegClass(Regs.front());
949 Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID());
950 }
951
952 SDValue Res = DAG.getTargetConstant(Flag, dl, MVT::i32);
953 Ops.push_back(Res);
954
955 if (Code == InlineAsm::Kind_Clobber) {
956 // Clobbers should always have a 1:1 mapping with registers, and may
957 // reference registers that have illegal (e.g. vector) types. Hence, we
958 // shouldn't try to apply any sort of splitting logic to them.
959 assert(Regs.size() == RegVTs.size() && Regs.size() == ValueVTs.size() &&((Regs.size() == RegVTs.size() && Regs.size() == ValueVTs
.size() && "No 1:1 mapping from clobbers to regs?") ?
static_cast<void> (0) : __assert_fail ("Regs.size() == RegVTs.size() && Regs.size() == ValueVTs.size() && \"No 1:1 mapping from clobbers to regs?\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 960, __PRETTY_FUNCTION__))
960 "No 1:1 mapping from clobbers to regs?")((Regs.size() == RegVTs.size() && Regs.size() == ValueVTs
.size() && "No 1:1 mapping from clobbers to regs?") ?
static_cast<void> (0) : __assert_fail ("Regs.size() == RegVTs.size() && Regs.size() == ValueVTs.size() && \"No 1:1 mapping from clobbers to regs?\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 960, __PRETTY_FUNCTION__))
;
961 unsigned SP = TLI.getStackPointerRegisterToSaveRestore();
962 (void)SP;
963 for (unsigned I = 0, E = ValueVTs.size(); I != E; ++I) {
964 Ops.push_back(DAG.getRegister(Regs[I], RegVTs[I]));
965 assert((((Regs[I] != SP || DAG.getMachineFunction().getFrameInfo().hasOpaqueSPAdjustment
()) && "If we clobbered the stack pointer, MFI should know about it."
) ? static_cast<void> (0) : __assert_fail ("(Regs[I] != SP || DAG.getMachineFunction().getFrameInfo().hasOpaqueSPAdjustment()) && \"If we clobbered the stack pointer, MFI should know about it.\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 968, __PRETTY_FUNCTION__))
966 (Regs[I] != SP ||(((Regs[I] != SP || DAG.getMachineFunction().getFrameInfo().hasOpaqueSPAdjustment
()) && "If we clobbered the stack pointer, MFI should know about it."
) ? static_cast<void> (0) : __assert_fail ("(Regs[I] != SP || DAG.getMachineFunction().getFrameInfo().hasOpaqueSPAdjustment()) && \"If we clobbered the stack pointer, MFI should know about it.\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 968, __PRETTY_FUNCTION__))
967 DAG.getMachineFunction().getFrameInfo().hasOpaqueSPAdjustment()) &&(((Regs[I] != SP || DAG.getMachineFunction().getFrameInfo().hasOpaqueSPAdjustment
()) && "If we clobbered the stack pointer, MFI should know about it."
) ? static_cast<void> (0) : __assert_fail ("(Regs[I] != SP || DAG.getMachineFunction().getFrameInfo().hasOpaqueSPAdjustment()) && \"If we clobbered the stack pointer, MFI should know about it.\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 968, __PRETTY_FUNCTION__))
968 "If we clobbered the stack pointer, MFI should know about it.")(((Regs[I] != SP || DAG.getMachineFunction().getFrameInfo().hasOpaqueSPAdjustment
()) && "If we clobbered the stack pointer, MFI should know about it."
) ? static_cast<void> (0) : __assert_fail ("(Regs[I] != SP || DAG.getMachineFunction().getFrameInfo().hasOpaqueSPAdjustment()) && \"If we clobbered the stack pointer, MFI should know about it.\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 968, __PRETTY_FUNCTION__))
;
969 }
970 return;
971 }
972
973 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
974 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
975 MVT RegisterVT = RegVTs[Value];
976 for (unsigned i = 0; i != NumRegs; ++i) {
977 assert(Reg < Regs.size() && "Mismatch in # registers expected")((Reg < Regs.size() && "Mismatch in # registers expected"
) ? static_cast<void> (0) : __assert_fail ("Reg < Regs.size() && \"Mismatch in # registers expected\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 977, __PRETTY_FUNCTION__))
;
978 unsigned TheReg = Regs[Reg++];
979 Ops.push_back(DAG.getRegister(TheReg, RegisterVT));
980 }
981 }
982}
983
984SmallVector<std::pair<unsigned, unsigned>, 4>
985RegsForValue::getRegsAndSizes() const {
986 SmallVector<std::pair<unsigned, unsigned>, 4> OutVec;
987 unsigned I = 0;
988 for (auto CountAndVT : zip_first(RegCount, RegVTs)) {
989 unsigned RegCount = std::get<0>(CountAndVT);
990 MVT RegisterVT = std::get<1>(CountAndVT);
991 unsigned RegisterSize = RegisterVT.getSizeInBits();
992 for (unsigned E = I + RegCount; I != E; ++I)
993 OutVec.push_back(std::make_pair(Regs[I], RegisterSize));
994 }
995 return OutVec;
996}
997
998void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis *aa,
999 const TargetLibraryInfo *li) {
1000 AA = aa;
1001 GFI = gfi;
1002 LibInfo = li;
1003 DL = &DAG.getDataLayout();
1004 Context = DAG.getContext();
1005 LPadToCallSiteMap.clear();
1006}
1007
1008void SelectionDAGBuilder::clear() {
1009 NodeMap.clear();
1010 UnusedArgNodeMap.clear();
1011 PendingLoads.clear();
1012 PendingExports.clear();
1013 CurInst = nullptr;
1014 HasTailCall = false;
1015 SDNodeOrder = LowestSDNodeOrder;
1016 StatepointLowering.clear();
1017}
1018
1019void SelectionDAGBuilder::clearDanglingDebugInfo() {
1020 DanglingDebugInfoMap.clear();
1021}
1022
1023SDValue SelectionDAGBuilder::getRoot() {
1024 if (PendingLoads.empty())
1025 return DAG.getRoot();
1026
1027 if (PendingLoads.size() == 1) {
1028 SDValue Root = PendingLoads[0];
1029 DAG.setRoot(Root);
1030 PendingLoads.clear();
1031 return Root;
1032 }
1033
1034 // Otherwise, we have to make a token factor node.
1035 // If we have >= 2^16 loads then split across multiple token factors as
1036 // there's a 64k limit on the number of SDNode operands.
1037 SDValue Root;
1038 size_t Limit = (1 << 16) - 1;
1039 while (PendingLoads.size() > Limit) {
1040 unsigned SliceIdx = PendingLoads.size() - Limit;
1041 auto ExtractedTFs = ArrayRef<SDValue>(PendingLoads).slice(SliceIdx, Limit);
1042 SDValue NewTF =
1043 DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other, ExtractedTFs);
1044 PendingLoads.erase(PendingLoads.begin() + SliceIdx, PendingLoads.end());
1045 PendingLoads.emplace_back(NewTF);
1046 }
1047 Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other, PendingLoads);
1048 PendingLoads.clear();
1049 DAG.setRoot(Root);
1050 return Root;
1051}
1052
1053SDValue SelectionDAGBuilder::getControlRoot() {
1054 SDValue Root = DAG.getRoot();
1055
1056 if (PendingExports.empty())
1057 return Root;
1058
1059 // Turn all of the CopyToReg chains into one factored node.
1060 if (Root.getOpcode() != ISD::EntryToken) {
1061 unsigned i = 0, e = PendingExports.size();
1062 for (; i != e; ++i) {
1063 assert(PendingExports[i].getNode()->getNumOperands() > 1)((PendingExports[i].getNode()->getNumOperands() > 1) ? static_cast
<void> (0) : __assert_fail ("PendingExports[i].getNode()->getNumOperands() > 1"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 1063, __PRETTY_FUNCTION__))
;
1064 if (PendingExports[i].getNode()->getOperand(0) == Root)
1065 break; // Don't add the root if we already indirectly depend on it.
1066 }
1067
1068 if (i == e)
1069 PendingExports.push_back(Root);
1070 }
1071
1072 Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
1073 PendingExports);
1074 PendingExports.clear();
1075 DAG.setRoot(Root);
1076 return Root;
1077}
1078
1079void SelectionDAGBuilder::visit(const Instruction &I) {
1080 // Set up outgoing PHI node register values before emitting the terminator.
1081 if (I.isTerminator()) {
1082 HandlePHINodesInSuccessorBlocks(I.getParent());
1083 }
1084
1085 // Increase the SDNodeOrder if dealing with a non-debug instruction.
1086 if (!isa<DbgInfoIntrinsic>(I))
1087 ++SDNodeOrder;
1088
1089 CurInst = &I;
1090
1091 visit(I.getOpcode(), I);
1092
1093 if (auto *FPMO = dyn_cast<FPMathOperator>(&I)) {
1094 // Propagate the fast-math-flags of this IR instruction to the DAG node that
1095 // maps to this instruction.
1096 // TODO: We could handle all flags (nsw, etc) here.
1097 // TODO: If an IR instruction maps to >1 node, only the final node will have
1098 // flags set.
1099 if (SDNode *Node = getNodeForIRValue(&I)) {
1100 SDNodeFlags IncomingFlags;
1101 IncomingFlags.copyFMF(*FPMO);
1102 if (!Node->getFlags().isDefined())
1103 Node->setFlags(IncomingFlags);
1104 else
1105 Node->intersectFlagsWith(IncomingFlags);
1106 }
1107 }
1108
1109 if (!I.isTerminator() && !HasTailCall &&
1110 !isStatepoint(&I)) // statepoints handle their exports internally
1111 CopyToExportRegsIfNeeded(&I);
1112
1113 CurInst = nullptr;
1114}
1115
1116void SelectionDAGBuilder::visitPHI(const PHINode &) {
1117 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!")::llvm::llvm_unreachable_internal("SelectionDAGBuilder shouldn't visit PHI nodes!"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 1117)
;
1118}
1119
1120void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
1121 // Note: this doesn't use InstVisitor, because it has to work with
1122 // ConstantExpr's in addition to instructions.
1123 switch (Opcode) {
1124 default: llvm_unreachable("Unknown instruction type encountered!")::llvm::llvm_unreachable_internal("Unknown instruction type encountered!"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 1124)
;
1125 // Build the switch statement using the Instruction.def file.
1126#define HANDLE_INST(NUM, OPCODE, CLASS) \
1127 case Instruction::OPCODE: visit##OPCODE((const CLASS&)I); break;
1128#include "llvm/IR/Instruction.def"
1129 }
1130}
1131
1132void SelectionDAGBuilder::dropDanglingDebugInfo(const DILocalVariable *Variable,
1133 const DIExpression *Expr) {
1134 auto isMatchingDbgValue = [&](DanglingDebugInfo &DDI) {
1135 const DbgValueInst *DI = DDI.getDI();
1136 DIVariable *DanglingVariable = DI->getVariable();
1137 DIExpression *DanglingExpr = DI->getExpression();
1138 if (DanglingVariable == Variable && Expr->fragmentsOverlap(DanglingExpr)) {
1139 LLVM_DEBUG(dbgs() << "Dropping dangling debug info for " << *DI << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << "Dropping dangling debug info for "
<< *DI << "\n"; } } while (false)
;
1140 return true;
1141 }
1142 return false;
1143 };
1144
1145 for (auto &DDIMI : DanglingDebugInfoMap) {
1146 DanglingDebugInfoVector &DDIV = DDIMI.second;
1147 DDIV.erase(remove_if(DDIV, isMatchingDbgValue), DDIV.end());
1148 }
1149}
1150
1151// resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
1152// generate the debug data structures now that we've seen its definition.
1153void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V,
1154 SDValue Val) {
1155 auto DanglingDbgInfoIt = DanglingDebugInfoMap.find(V);
1156 if (DanglingDbgInfoIt == DanglingDebugInfoMap.end())
1157 return;
1158
1159 DanglingDebugInfoVector &DDIV = DanglingDbgInfoIt->second;
1160 for (auto &DDI : DDIV) {
1161 const DbgValueInst *DI = DDI.getDI();
1162 assert(DI && "Ill-formed DanglingDebugInfo")((DI && "Ill-formed DanglingDebugInfo") ? static_cast
<void> (0) : __assert_fail ("DI && \"Ill-formed DanglingDebugInfo\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 1162, __PRETTY_FUNCTION__))
;
1163 DebugLoc dl = DDI.getdl();
1164 unsigned ValSDNodeOrder = Val.getNode()->getIROrder();
1165 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder();
1166 DILocalVariable *Variable = DI->getVariable();
1167 DIExpression *Expr = DI->getExpression();
1168 assert(Variable->isValidLocationForIntrinsic(dl) &&((Variable->isValidLocationForIntrinsic(dl) && "Expected inlined-at fields to agree"
) ? static_cast<void> (0) : __assert_fail ("Variable->isValidLocationForIntrinsic(dl) && \"Expected inlined-at fields to agree\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 1169, __PRETTY_FUNCTION__))
1169 "Expected inlined-at fields to agree")((Variable->isValidLocationForIntrinsic(dl) && "Expected inlined-at fields to agree"
) ? static_cast<void> (0) : __assert_fail ("Variable->isValidLocationForIntrinsic(dl) && \"Expected inlined-at fields to agree\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 1169, __PRETTY_FUNCTION__))
;
1170 SDDbgValue *SDV;
1171 if (Val.getNode()) {
1172 if (!EmitFuncArgumentDbgValue(V, Variable, Expr, dl, false, Val)) {
1173 LLVM_DEBUG(dbgs() << "Resolve dangling debug info [order="do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << "Resolve dangling debug info [order="
<< DbgSDNodeOrder << "] for:\n " << *DI <<
"\n"; } } while (false)
1174 << DbgSDNodeOrder << "] for:\n " << *DI << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << "Resolve dangling debug info [order="
<< DbgSDNodeOrder << "] for:\n " << *DI <<
"\n"; } } while (false)
;
1175 LLVM_DEBUG(dbgs() << " By mapping to:\n "; Val.dump())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << " By mapping to:\n "; Val.dump
(); } } while (false)
;
1176 // Increase the SDNodeOrder for the DbgValue here to make sure it is
1177 // inserted after the definition of Val when emitting the instructions
1178 // after ISel. An alternative could be to teach
1179 // ScheduleDAGSDNodes::EmitSchedule to delay the insertion properly.
1180 LLVM_DEBUG(if (ValSDNodeOrder > DbgSDNodeOrder) dbgs()do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { if (ValSDNodeOrder > DbgSDNodeOrder) dbgs() <<
"changing SDNodeOrder from " << DbgSDNodeOrder <<
" to " << ValSDNodeOrder << "\n"; } } while (false
)
1181 << "changing SDNodeOrder from " << DbgSDNodeOrder << " to "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { if (ValSDNodeOrder > DbgSDNodeOrder) dbgs() <<
"changing SDNodeOrder from " << DbgSDNodeOrder <<
" to " << ValSDNodeOrder << "\n"; } } while (false
)
1182 << ValSDNodeOrder << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { if (ValSDNodeOrder > DbgSDNodeOrder) dbgs() <<
"changing SDNodeOrder from " << DbgSDNodeOrder <<
" to " << ValSDNodeOrder << "\n"; } } while (false
)
;
1183 SDV = getDbgValue(Val, Variable, Expr, dl,
1184 std::max(DbgSDNodeOrder, ValSDNodeOrder));
1185 DAG.AddDbgValue(SDV, Val.getNode(), false);
1186 } else
1187 LLVM_DEBUG(dbgs() << "Resolved dangling debug info for " << *DIdo { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << "Resolved dangling debug info for "
<< *DI << "in EmitFuncArgumentDbgValue\n"; } } while
(false)
1188 << "in EmitFuncArgumentDbgValue\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << "Resolved dangling debug info for "
<< *DI << "in EmitFuncArgumentDbgValue\n"; } } while
(false)
;
1189 } else
1190 LLVM_DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << "Dropping debug info for " <<
*DI << "\n"; } } while (false)
;
1191 }
1192 DDIV.clear();
1193}
1194
1195/// getCopyFromRegs - If there was virtual register allocated for the value V
1196/// emit CopyFromReg of the specified type Ty. Return empty SDValue() otherwise.
1197SDValue SelectionDAGBuilder::getCopyFromRegs(const Value *V, Type *Ty) {
1198 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V);
1199 SDValue Result;
1200
1201 if (It != FuncInfo.ValueMap.end()) {
1202 unsigned InReg = It->second;
1203
1204 RegsForValue RFV(*DAG.getContext(), DAG.getTargetLoweringInfo(),
1205 DAG.getDataLayout(), InReg, Ty,
1206 None); // This is not an ABI copy.
1207 SDValue Chain = DAG.getEntryNode();
1208 Result = RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr,
1209 V);
1210 resolveDanglingDebugInfo(V, Result);
1211 }
1212
1213 return Result;
1214}
1215
1216/// getValue - Return an SDValue for the given Value.
1217SDValue SelectionDAGBuilder::getValue(const Value *V) {
1218 // If we already have an SDValue for this value, use it. It's important
1219 // to do this first, so that we don't create a CopyFromReg if we already
1220 // have a regular SDValue.
1221 SDValue &N = NodeMap[V];
1222 if (N.getNode()) return N;
1223
1224 // If there's a virtual register allocated and initialized for this
1225 // value, use it.
1226 if (SDValue copyFromReg = getCopyFromRegs(V, V->getType()))
1227 return copyFromReg;
1228
1229 // Otherwise create a new SDValue and remember it.
1230 SDValue Val = getValueImpl(V);
1231 NodeMap[V] = Val;
1232 resolveDanglingDebugInfo(V, Val);
1233 return Val;
1234}
1235
1236// Return true if SDValue exists for the given Value
1237bool SelectionDAGBuilder::findValue(const Value *V) const {
1238 return (NodeMap.find(V) != NodeMap.end()) ||
1239 (FuncInfo.ValueMap.find(V) != FuncInfo.ValueMap.end());
1240}
1241
1242/// getNonRegisterValue - Return an SDValue for the given Value, but
1243/// don't look in FuncInfo.ValueMap for a virtual register.
1244SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) {
1245 // If we already have an SDValue for this value, use it.
1246 SDValue &N = NodeMap[V];
1247 if (N.getNode()) {
1248 if (isa<ConstantSDNode>(N) || isa<ConstantFPSDNode>(N)) {
1249 // Remove the debug location from the node as the node is about to be used
1250 // in a location which may differ from the original debug location. This
1251 // is relevant to Constant and ConstantFP nodes because they can appear
1252 // as constant expressions inside PHI nodes.
1253 N->setDebugLoc(DebugLoc());
1254 }
1255 return N;
1256 }
1257
1258 // Otherwise create a new SDValue and remember it.
1259 SDValue Val = getValueImpl(V);
1260 NodeMap[V] = Val;
1261 resolveDanglingDebugInfo(V, Val);
1262 return Val;
1263}
1264
1265/// getValueImpl - Helper function for getValue and getNonRegisterValue.
1266/// Create an SDValue for the given value.
1267SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
1268 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1269
1270 if (const Constant *C = dyn_cast<Constant>(V)) {
1271 EVT VT = TLI.getValueType(DAG.getDataLayout(), V->getType(), true);
1272
1273 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
1274 return DAG.getConstant(*CI, getCurSDLoc(), VT);
1275
1276 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
1277 return DAG.getGlobalAddress(GV, getCurSDLoc(), VT);
1278
1279 if (isa<ConstantPointerNull>(C)) {
1280 unsigned AS = V->getType()->getPointerAddressSpace();
1281 return DAG.getConstant(0, getCurSDLoc(),
1282 TLI.getPointerTy(DAG.getDataLayout(), AS));
1283 }
1284
1285 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
1286 return DAG.getConstantFP(*CFP, getCurSDLoc(), VT);
1287
1288 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
1289 return DAG.getUNDEF(VT);
1290
1291 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
1292 visit(CE->getOpcode(), *CE);
1293 SDValue N1 = NodeMap[V];
1294 assert(N1.getNode() && "visit didn't populate the NodeMap!")((N1.getNode() && "visit didn't populate the NodeMap!"
) ? static_cast<void> (0) : __assert_fail ("N1.getNode() && \"visit didn't populate the NodeMap!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 1294, __PRETTY_FUNCTION__))
;
1295 return N1;
1296 }
1297
1298 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
1299 SmallVector<SDValue, 4> Constants;
1300 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
1301 OI != OE; ++OI) {
1302 SDNode *Val = getValue(*OI).getNode();
1303 // If the operand is an empty aggregate, there are no values.
1304 if (!Val) continue;
1305 // Add each leaf value from the operand to the Constants list
1306 // to form a flattened list of all the values.
1307 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1308 Constants.push_back(SDValue(Val, i));
1309 }
1310
1311 return DAG.getMergeValues(Constants, getCurSDLoc());
1312 }
1313
1314 if (const ConstantDataSequential *CDS =
1315 dyn_cast<ConstantDataSequential>(C)) {
1316 SmallVector<SDValue, 4> Ops;
1317 for (unsigned i = 0, e = CDS->getNumElements(); i != e; ++i) {
1318 SDNode *Val = getValue(CDS->getElementAsConstant(i)).getNode();
1319 // Add each leaf value from the operand to the Constants list
1320 // to form a flattened list of all the values.
1321 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1322 Ops.push_back(SDValue(Val, i));
1323 }
1324
1325 if (isa<ArrayType>(CDS->getType()))
1326 return DAG.getMergeValues(Ops, getCurSDLoc());
1327 return NodeMap[V] = DAG.getBuildVector(VT, getCurSDLoc(), Ops);
1328 }
1329
1330 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
1331 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&(((isa<ConstantAggregateZero>(C) || isa<UndefValue>
(C)) && "Unknown struct or array constant!") ? static_cast
<void> (0) : __assert_fail ("(isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) && \"Unknown struct or array constant!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 1332, __PRETTY_FUNCTION__))
1332 "Unknown struct or array constant!")(((isa<ConstantAggregateZero>(C) || isa<UndefValue>
(C)) && "Unknown struct or array constant!") ? static_cast
<void> (0) : __assert_fail ("(isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) && \"Unknown struct or array constant!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 1332, __PRETTY_FUNCTION__))
;
1333
1334 SmallVector<EVT, 4> ValueVTs;
1335 ComputeValueVTs(TLI, DAG.getDataLayout(), C->getType(), ValueVTs);
1336 unsigned NumElts = ValueVTs.size();
1337 if (NumElts == 0)
1338 return SDValue(); // empty struct
1339 SmallVector<SDValue, 4> Constants(NumElts);
1340 for (unsigned i = 0; i != NumElts; ++i) {
1341 EVT EltVT = ValueVTs[i];
1342 if (isa<UndefValue>(C))
1343 Constants[i] = DAG.getUNDEF(EltVT);
1344 else if (EltVT.isFloatingPoint())
1345 Constants[i] = DAG.getConstantFP(0, getCurSDLoc(), EltVT);
1346 else
1347 Constants[i] = DAG.getConstant(0, getCurSDLoc(), EltVT);
1348 }
1349
1350 return DAG.getMergeValues(Constants, getCurSDLoc());
1351 }
1352
1353 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C))
1354 return DAG.getBlockAddress(BA, VT);
1355
1356 VectorType *VecTy = cast<VectorType>(V->getType());
1357 unsigned NumElements = VecTy->getNumElements();
1358
1359 // Now that we know the number and type of the elements, get that number of
1360 // elements into the Ops array based on what kind of constant it is.
1361 SmallVector<SDValue, 16> Ops;
1362 if (const ConstantVector *CV = dyn_cast<ConstantVector>(C)) {
1363 for (unsigned i = 0; i != NumElements; ++i)
1364 Ops.push_back(getValue(CV->getOperand(i)));
1365 } else {
1366 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!")((isa<ConstantAggregateZero>(C) && "Unknown vector constant!"
) ? static_cast<void> (0) : __assert_fail ("isa<ConstantAggregateZero>(C) && \"Unknown vector constant!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 1366, __PRETTY_FUNCTION__))
;
1367 EVT EltVT =
1368 TLI.getValueType(DAG.getDataLayout(), VecTy->getElementType());
1369
1370 SDValue Op;
1371 if (EltVT.isFloatingPoint())
1372 Op = DAG.getConstantFP(0, getCurSDLoc(), EltVT);
1373 else
1374 Op = DAG.getConstant(0, getCurSDLoc(), EltVT);
1375 Ops.assign(NumElements, Op);
1376 }
1377
1378 // Create a BUILD_VECTOR node.
1379 return NodeMap[V] = DAG.getBuildVector(VT, getCurSDLoc(), Ops);
1380 }
1381
1382 // If this is a static alloca, generate it as the frameindex instead of
1383 // computation.
1384 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1385 DenseMap<const AllocaInst*, int>::iterator SI =
1386 FuncInfo.StaticAllocaMap.find(AI);
1387 if (SI != FuncInfo.StaticAllocaMap.end())
1388 return DAG.getFrameIndex(SI->second,
1389 TLI.getFrameIndexTy(DAG.getDataLayout()));
1390 }
1391
1392 // If this is an instruction which fast-isel has deferred, select it now.
1393 if (const Instruction *Inst = dyn_cast<Instruction>(V)) {
1394 unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
1395
1396 RegsForValue RFV(*DAG.getContext(), TLI, DAG.getDataLayout(), InReg,
1397 Inst->getType(), getABIRegCopyCC(V));
1398 SDValue Chain = DAG.getEntryNode();
1399 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
1400 }
1401
1402 llvm_unreachable("Can't get register for value!")::llvm::llvm_unreachable_internal("Can't get register for value!"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 1402)
;
1403}
1404
1405void SelectionDAGBuilder::visitCatchPad(const CatchPadInst &I) {
1406 auto Pers = classifyEHPersonality(FuncInfo.Fn->getPersonalityFn());
1407 bool IsMSVCCXX = Pers == EHPersonality::MSVC_CXX;
1408 bool IsCoreCLR = Pers == EHPersonality::CoreCLR;
1409 bool IsSEH = isAsynchronousEHPersonality(Pers);
1410 bool IsWasmCXX = Pers == EHPersonality::Wasm_CXX;
1411 MachineBasicBlock *CatchPadMBB = FuncInfo.MBB;
1412 if (!IsSEH)
1413 CatchPadMBB->setIsEHScopeEntry();
1414 // In MSVC C++ and CoreCLR, catchblocks are funclets and need prologues.
1415 if (IsMSVCCXX || IsCoreCLR)
1416 CatchPadMBB->setIsEHFuncletEntry();
1417 // Wasm does not need catchpads anymore
1418 if (!IsWasmCXX)
1419 DAG.setRoot(DAG.getNode(ISD::CATCHPAD, getCurSDLoc(), MVT::Other,
1420 getControlRoot()));
1421}
1422
1423void SelectionDAGBuilder::visitCatchRet(const CatchReturnInst &I) {
1424 // Update machine-CFG edge.
1425 MachineBasicBlock *TargetMBB = FuncInfo.MBBMap[I.getSuccessor()];
1426 FuncInfo.MBB->addSuccessor(TargetMBB);
1427
1428 auto Pers = classifyEHPersonality(FuncInfo.Fn->getPersonalityFn());
1429 bool IsSEH = isAsynchronousEHPersonality(Pers);
1430 if (IsSEH) {
1431 // If this is not a fall-through branch or optimizations are switched off,
1432 // emit the branch.
1433 if (TargetMBB != NextBlock(FuncInfo.MBB) ||
1434 TM.getOptLevel() == CodeGenOpt::None)
1435 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other,
1436 getControlRoot(), DAG.getBasicBlock(TargetMBB)));
1437 return;
1438 }
1439
1440 // Figure out the funclet membership for the catchret's successor.
1441 // This will be used by the FuncletLayout pass to determine how to order the
1442 // BB's.
1443 // A 'catchret' returns to the outer scope's color.
1444 Value *ParentPad = I.getCatchSwitchParentPad();
1445 const BasicBlock *SuccessorColor;
1446 if (isa<ConstantTokenNone>(ParentPad))
1447 SuccessorColor = &FuncInfo.Fn->getEntryBlock();
1448 else
1449 SuccessorColor = cast<Instruction>(ParentPad)->getParent();
1450 assert(SuccessorColor && "No parent funclet for catchret!")((SuccessorColor && "No parent funclet for catchret!"
) ? static_cast<void> (0) : __assert_fail ("SuccessorColor && \"No parent funclet for catchret!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 1450, __PRETTY_FUNCTION__))
;
1451 MachineBasicBlock *SuccessorColorMBB = FuncInfo.MBBMap[SuccessorColor];
1452 assert(SuccessorColorMBB && "No MBB for SuccessorColor!")((SuccessorColorMBB && "No MBB for SuccessorColor!") ?
static_cast<void> (0) : __assert_fail ("SuccessorColorMBB && \"No MBB for SuccessorColor!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 1452, __PRETTY_FUNCTION__))
;
1453
1454 // Create the terminator node.
1455 SDValue Ret = DAG.getNode(ISD::CATCHRET, getCurSDLoc(), MVT::Other,
1456 getControlRoot(), DAG.getBasicBlock(TargetMBB),
1457 DAG.getBasicBlock(SuccessorColorMBB));
1458 DAG.setRoot(Ret);
1459}
1460
1461void SelectionDAGBuilder::visitCleanupPad(const CleanupPadInst &CPI) {
1462 // Don't emit any special code for the cleanuppad instruction. It just marks
1463 // the start of an EH scope/funclet.
1464 FuncInfo.MBB->setIsEHScopeEntry();
1465 auto Pers = classifyEHPersonality(FuncInfo.Fn->getPersonalityFn());
1466 if (Pers != EHPersonality::Wasm_CXX) {
1467 FuncInfo.MBB->setIsEHFuncletEntry();
1468 FuncInfo.MBB->setIsCleanupFuncletEntry();
1469 }
1470}
1471
1472/// When an invoke or a cleanupret unwinds to the next EH pad, there are
1473/// many places it could ultimately go. In the IR, we have a single unwind
1474/// destination, but in the machine CFG, we enumerate all the possible blocks.
1475/// This function skips over imaginary basic blocks that hold catchswitch
1476/// instructions, and finds all the "real" machine
1477/// basic block destinations. As those destinations may not be successors of
1478/// EHPadBB, here we also calculate the edge probability to those destinations.
1479/// The passed-in Prob is the edge probability to EHPadBB.
1480static void findUnwindDestinations(
1481 FunctionLoweringInfo &FuncInfo, const BasicBlock *EHPadBB,
1482 BranchProbability Prob,
1483 SmallVectorImpl<std::pair<MachineBasicBlock *, BranchProbability>>
1484 &UnwindDests) {
1485 EHPersonality Personality =
1486 classifyEHPersonality(FuncInfo.Fn->getPersonalityFn());
1487 bool IsMSVCCXX = Personality == EHPersonality::MSVC_CXX;
1488 bool IsCoreCLR = Personality == EHPersonality::CoreCLR;
1489 bool IsWasmCXX = Personality == EHPersonality::Wasm_CXX;
1490 bool IsSEH = isAsynchronousEHPersonality(Personality);
1491
1492 while (EHPadBB) {
1493 const Instruction *Pad = EHPadBB->getFirstNonPHI();
1494 BasicBlock *NewEHPadBB = nullptr;
1495 if (isa<LandingPadInst>(Pad)) {
1496 // Stop on landingpads. They are not funclets.
1497 UnwindDests.emplace_back(FuncInfo.MBBMap[EHPadBB], Prob);
1498 break;
1499 } else if (isa<CleanupPadInst>(Pad)) {
1500 // Stop on cleanup pads. Cleanups are always funclet entries for all known
1501 // personalities.
1502 UnwindDests.emplace_back(FuncInfo.MBBMap[EHPadBB], Prob);
1503 UnwindDests.back().first->setIsEHScopeEntry();
1504 if (!IsWasmCXX)
1505 UnwindDests.back().first->setIsEHFuncletEntry();
1506 break;
1507 } else if (auto *CatchSwitch = dyn_cast<CatchSwitchInst>(Pad)) {
1508 // Add the catchpad handlers to the possible destinations.
1509 for (const BasicBlock *CatchPadBB : CatchSwitch->handlers()) {
1510 UnwindDests.emplace_back(FuncInfo.MBBMap[CatchPadBB], Prob);
1511 // For MSVC++ and the CLR, catchblocks are funclets and need prologues.
1512 if (IsMSVCCXX || IsCoreCLR)
1513 UnwindDests.back().first->setIsEHFuncletEntry();
1514 if (!IsSEH)
1515 UnwindDests.back().first->setIsEHScopeEntry();
1516 }
1517 NewEHPadBB = CatchSwitch->getUnwindDest();
1518 } else {
1519 continue;
1520 }
1521
1522 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1523 if (BPI && NewEHPadBB)
1524 Prob *= BPI->getEdgeProbability(EHPadBB, NewEHPadBB);
1525 EHPadBB = NewEHPadBB;
1526 }
1527}
1528
1529void SelectionDAGBuilder::visitCleanupRet(const CleanupReturnInst &I) {
1530 // Update successor info.
1531 SmallVector<std::pair<MachineBasicBlock *, BranchProbability>, 1> UnwindDests;
1532 auto UnwindDest = I.getUnwindDest();
1533 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1534 BranchProbability UnwindDestProb =
1535 (BPI && UnwindDest)
1536 ? BPI->getEdgeProbability(FuncInfo.MBB->getBasicBlock(), UnwindDest)
1537 : BranchProbability::getZero();
1538 findUnwindDestinations(FuncInfo, UnwindDest, UnwindDestProb, UnwindDests);
1539 for (auto &UnwindDest : UnwindDests) {
1540 UnwindDest.first->setIsEHPad();
1541 addSuccessorWithProb(FuncInfo.MBB, UnwindDest.first, UnwindDest.second);
1542 }
1543 FuncInfo.MBB->normalizeSuccProbs();
1544
1545 // Create the terminator node.
1546 SDValue Ret =
1547 DAG.getNode(ISD::CLEANUPRET, getCurSDLoc(), MVT::Other, getControlRoot());
1548 DAG.setRoot(Ret);
1549}
1550
1551void SelectionDAGBuilder::visitCatchSwitch(const CatchSwitchInst &CSI) {
1552 report_fatal_error("visitCatchSwitch not yet implemented!");
1553}
1554
1555void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
1556 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1557 auto &DL = DAG.getDataLayout();
1558 SDValue Chain = getControlRoot();
1559 SmallVector<ISD::OutputArg, 8> Outs;
1560 SmallVector<SDValue, 8> OutVals;
1561
1562 // Calls to @llvm.experimental.deoptimize don't generate a return value, so
1563 // lower
1564 //
1565 // %val = call <ty> @llvm.experimental.deoptimize()
1566 // ret <ty> %val
1567 //
1568 // differently.
1569 if (I.getParent()->getTerminatingDeoptimizeCall()) {
1570 LowerDeoptimizingReturn();
1571 return;
1572 }
1573
1574 if (!FuncInfo.CanLowerReturn) {
1575 unsigned DemoteReg = FuncInfo.DemoteRegister;
1576 const Function *F = I.getParent()->getParent();
1577
1578 // Emit a store of the return value through the virtual register.
1579 // Leave Outs empty so that LowerReturn won't try to load return
1580 // registers the usual way.
1581 SmallVector<EVT, 1> PtrValueVTs;
1582 ComputeValueVTs(TLI, DL,
1583 F->getReturnType()->getPointerTo(
1584 DAG.getDataLayout().getAllocaAddrSpace()),
1585 PtrValueVTs);
1586
1587 SDValue RetPtr = DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(),
1588 DemoteReg, PtrValueVTs[0]);
1589 SDValue RetOp = getValue(I.getOperand(0));
1590
1591 SmallVector<EVT, 4> ValueVTs;
1592 SmallVector<uint64_t, 4> Offsets;
1593 ComputeValueVTs(TLI, DL, I.getOperand(0)->getType(), ValueVTs, &Offsets);
1594 unsigned NumValues = ValueVTs.size();
1595
1596 SmallVector<SDValue, 4> Chains(NumValues);
1597 for (unsigned i = 0; i != NumValues; ++i) {
1598 // An aggregate return value cannot wrap around the address space, so
1599 // offsets to its parts don't wrap either.
1600 SDValue Ptr = DAG.getObjectPtrOffset(getCurSDLoc(), RetPtr, Offsets[i]);
1601 Chains[i] = DAG.getStore(
1602 Chain, getCurSDLoc(), SDValue(RetOp.getNode(), RetOp.getResNo() + i),
1603 // FIXME: better loc info would be nice.
1604 Ptr, MachinePointerInfo::getUnknownStack(DAG.getMachineFunction()));
1605 }
1606
1607 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
1608 MVT::Other, Chains);
1609 } else if (I.getNumOperands() != 0) {
1610 SmallVector<EVT, 4> ValueVTs;
1611 ComputeValueVTs(TLI, DL, I.getOperand(0)->getType(), ValueVTs);
1612 unsigned NumValues = ValueVTs.size();
1613 if (NumValues) {
1614 SDValue RetOp = getValue(I.getOperand(0));
1615
1616 const Function *F = I.getParent()->getParent();
1617
1618 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1619 if (F->getAttributes().hasAttribute(AttributeList::ReturnIndex,
1620 Attribute::SExt))
1621 ExtendKind = ISD::SIGN_EXTEND;
1622 else if (F->getAttributes().hasAttribute(AttributeList::ReturnIndex,
1623 Attribute::ZExt))
1624 ExtendKind = ISD::ZERO_EXTEND;
1625
1626 LLVMContext &Context = F->getContext();
1627 bool RetInReg = F->getAttributes().hasAttribute(
1628 AttributeList::ReturnIndex, Attribute::InReg);
1629
1630 for (unsigned j = 0; j != NumValues; ++j) {
1631 EVT VT = ValueVTs[j];
1632
1633 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger())
1634 VT = TLI.getTypeForExtReturn(Context, VT, ExtendKind);
1635
1636 CallingConv::ID CC = F->getCallingConv();
1637
1638 unsigned NumParts = TLI.getNumRegistersForCallingConv(Context, CC, VT);
1639 MVT PartVT = TLI.getRegisterTypeForCallingConv(Context, CC, VT);
1640 SmallVector<SDValue, 4> Parts(NumParts);
1641 getCopyToParts(DAG, getCurSDLoc(),
1642 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
1643 &Parts[0], NumParts, PartVT, &I, CC, ExtendKind);
1644
1645 // 'inreg' on function refers to return value
1646 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1647 if (RetInReg)
1648 Flags.setInReg();
1649
1650 // Propagate extension type if any
1651 if (ExtendKind == ISD::SIGN_EXTEND)
1652 Flags.setSExt();
1653 else if (ExtendKind == ISD::ZERO_EXTEND)
1654 Flags.setZExt();
1655
1656 for (unsigned i = 0; i < NumParts; ++i) {
1657 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(),
1658 VT, /*isfixed=*/true, 0, 0));
1659 OutVals.push_back(Parts[i]);
1660 }
1661 }
1662 }
1663 }
1664
1665 // Push in swifterror virtual register as the last element of Outs. This makes
1666 // sure swifterror virtual register will be returned in the swifterror
1667 // physical register.
1668 const Function *F = I.getParent()->getParent();
1669 if (TLI.supportSwiftError() &&
1670 F->getAttributes().hasAttrSomewhere(Attribute::SwiftError)) {
1671 assert(FuncInfo.SwiftErrorArg && "Need a swift error argument")((FuncInfo.SwiftErrorArg && "Need a swift error argument"
) ? static_cast<void> (0) : __assert_fail ("FuncInfo.SwiftErrorArg && \"Need a swift error argument\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 1671, __PRETTY_FUNCTION__))
;
1672 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1673 Flags.setSwiftError();
1674 Outs.push_back(ISD::OutputArg(Flags, EVT(TLI.getPointerTy(DL)) /*vt*/,
1675 EVT(TLI.getPointerTy(DL)) /*argvt*/,
1676 true /*isfixed*/, 1 /*origidx*/,
1677 0 /*partOffs*/));
1678 // Create SDNode for the swifterror virtual register.
1679 OutVals.push_back(
1680 DAG.getRegister(FuncInfo.getOrCreateSwiftErrorVRegUseAt(
1681 &I, FuncInfo.MBB, FuncInfo.SwiftErrorArg).first,
1682 EVT(TLI.getPointerTy(DL))));
1683 }
1684
1685 bool isVarArg = DAG.getMachineFunction().getFunction().isVarArg();
1686 CallingConv::ID CallConv =
1687 DAG.getMachineFunction().getFunction().getCallingConv();
1688 Chain = DAG.getTargetLoweringInfo().LowerReturn(
1689 Chain, CallConv, isVarArg, Outs, OutVals, getCurSDLoc(), DAG);
1690
1691 // Verify that the target's LowerReturn behaved as expected.
1692 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&((Chain.getNode() && Chain.getValueType() == MVT::Other
&& "LowerReturn didn't return a valid chain!") ? static_cast
<void> (0) : __assert_fail ("Chain.getNode() && Chain.getValueType() == MVT::Other && \"LowerReturn didn't return a valid chain!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 1693, __PRETTY_FUNCTION__))
1693 "LowerReturn didn't return a valid chain!")((Chain.getNode() && Chain.getValueType() == MVT::Other
&& "LowerReturn didn't return a valid chain!") ? static_cast
<void> (0) : __assert_fail ("Chain.getNode() && Chain.getValueType() == MVT::Other && \"LowerReturn didn't return a valid chain!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 1693, __PRETTY_FUNCTION__))
;
1694
1695 // Update the DAG with the new chain value resulting from return lowering.
1696 DAG.setRoot(Chain);
1697}
1698
1699/// CopyToExportRegsIfNeeded - If the given value has virtual registers
1700/// created for it, emit nodes to copy the value into the virtual
1701/// registers.
1702void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) {
1703 // Skip empty types
1704 if (V->getType()->isEmptyTy())
1705 return;
1706
1707 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1708 if (VMI != FuncInfo.ValueMap.end()) {
1709 assert(!V->use_empty() && "Unused value assigned virtual registers!")((!V->use_empty() && "Unused value assigned virtual registers!"
) ? static_cast<void> (0) : __assert_fail ("!V->use_empty() && \"Unused value assigned virtual registers!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 1709, __PRETTY_FUNCTION__))
;
1710 CopyValueToVirtualRegister(V, VMI->second);
1711 }
1712}
1713
1714/// ExportFromCurrentBlock - If this condition isn't known to be exported from
1715/// the current basic block, add it to ValueMap now so that we'll get a
1716/// CopyTo/FromReg.
1717void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) {
1718 // No need to export constants.
1719 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1720
1721 // Already exported?
1722 if (FuncInfo.isExportedInst(V)) return;
1723
1724 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1725 CopyValueToVirtualRegister(V, Reg);
1726}
1727
1728bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V,
1729 const BasicBlock *FromBB) {
1730 // The operands of the setcc have to be in this block. We don't know
1731 // how to export them from some other block.
1732 if (const Instruction *VI = dyn_cast<Instruction>(V)) {
1733 // Can export from current BB.
1734 if (VI->getParent() == FromBB)
1735 return true;
1736
1737 // Is already exported, noop.
1738 return FuncInfo.isExportedInst(V);
1739 }
1740
1741 // If this is an argument, we can export it if the BB is the entry block or
1742 // if it is already exported.
1743 if (isa<Argument>(V)) {
1744 if (FromBB == &FromBB->getParent()->getEntryBlock())
1745 return true;
1746
1747 // Otherwise, can only export this if it is already exported.
1748 return FuncInfo.isExportedInst(V);
1749 }
1750
1751 // Otherwise, constants can always be exported.
1752 return true;
1753}
1754
1755/// Return branch probability calculated by BranchProbabilityInfo for IR blocks.
1756BranchProbability
1757SelectionDAGBuilder::getEdgeProbability(const MachineBasicBlock *Src,
1758 const MachineBasicBlock *Dst) const {
1759 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1760 const BasicBlock *SrcBB = Src->getBasicBlock();
1761 const BasicBlock *DstBB = Dst->getBasicBlock();
1762 if (!BPI) {
1763 // If BPI is not available, set the default probability as 1 / N, where N is
1764 // the number of successors.
1765 auto SuccSize = std::max<uint32_t>(succ_size(SrcBB), 1);
1766 return BranchProbability(1, SuccSize);
1767 }
1768 return BPI->getEdgeProbability(SrcBB, DstBB);
1769}
1770
1771void SelectionDAGBuilder::addSuccessorWithProb(MachineBasicBlock *Src,
1772 MachineBasicBlock *Dst,
1773 BranchProbability Prob) {
1774 if (!FuncInfo.BPI)
1775 Src->addSuccessorWithoutProb(Dst);
1776 else {
1777 if (Prob.isUnknown())
1778 Prob = getEdgeProbability(Src, Dst);
1779 Src->addSuccessor(Dst, Prob);
1780 }
1781}
1782
1783static bool InBlock(const Value *V, const BasicBlock *BB) {
1784 if (const Instruction *I = dyn_cast<Instruction>(V))
1785 return I->getParent() == BB;
1786 return true;
1787}
1788
1789/// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1790/// This function emits a branch and is used at the leaves of an OR or an
1791/// AND operator tree.
1792void
1793SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond,
1794 MachineBasicBlock *TBB,
1795 MachineBasicBlock *FBB,
1796 MachineBasicBlock *CurBB,
1797 MachineBasicBlock *SwitchBB,
1798 BranchProbability TProb,
1799 BranchProbability FProb,
1800 bool InvertCond) {
1801 const BasicBlock *BB = CurBB->getBasicBlock();
1802
1803 // If the leaf of the tree is a comparison, merge the condition into
1804 // the caseblock.
1805 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1806 // The operands of the cmp have to be in this block. We don't know
1807 // how to export them from some other block. If this is the first block
1808 // of the sequence, no exporting is needed.
1809 if (CurBB == SwitchBB ||
1810 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1811 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1812 ISD::CondCode Condition;
1813 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1814 ICmpInst::Predicate Pred =
1815 InvertCond ? IC->getInversePredicate() : IC->getPredicate();
1816 Condition = getICmpCondCode(Pred);
1817 } else {
1818 const FCmpInst *FC = cast<FCmpInst>(Cond);
1819 FCmpInst::Predicate Pred =
1820 InvertCond ? FC->getInversePredicate() : FC->getPredicate();
1821 Condition = getFCmpCondCode(Pred);
1822 if (TM.Options.NoNaNsFPMath)
1823 Condition = getFCmpCodeWithoutNaN(Condition);
1824 }
1825
1826 CaseBlock CB(Condition, BOp->getOperand(0), BOp->getOperand(1), nullptr,
1827 TBB, FBB, CurBB, getCurSDLoc(), TProb, FProb);
1828 SwitchCases.push_back(CB);
1829 return;
1830 }
1831 }
1832
1833 // Create a CaseBlock record representing this branch.
1834 ISD::CondCode Opc = InvertCond ? ISD::SETNE : ISD::SETEQ;
1835 CaseBlock CB(Opc, Cond, ConstantInt::getTrue(*DAG.getContext()),
1836 nullptr, TBB, FBB, CurBB, getCurSDLoc(), TProb, FProb);
1837 SwitchCases.push_back(CB);
1838}
1839
1840void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
1841 MachineBasicBlock *TBB,
1842 MachineBasicBlock *FBB,
1843 MachineBasicBlock *CurBB,
1844 MachineBasicBlock *SwitchBB,
1845 Instruction::BinaryOps Opc,
1846 BranchProbability TProb,
1847 BranchProbability FProb,
1848 bool InvertCond) {
1849 // Skip over not part of the tree and remember to invert op and operands at
1850 // next level.
1851 Value *NotCond;
1852 if (match(Cond, m_OneUse(m_Not(m_Value(NotCond)))) &&
1853 InBlock(NotCond, CurBB->getBasicBlock())) {
1854 FindMergedConditions(NotCond, TBB, FBB, CurBB, SwitchBB, Opc, TProb, FProb,
1855 !InvertCond);
1856 return;
1857 }
1858
1859 const Instruction *BOp = dyn_cast<Instruction>(Cond);
1860 // Compute the effective opcode for Cond, taking into account whether it needs
1861 // to be inverted, e.g.
1862 // and (not (or A, B)), C
1863 // gets lowered as
1864 // and (and (not A, not B), C)
1865 unsigned BOpc = 0;
1866 if (BOp) {
1867 BOpc = BOp->getOpcode();
1868 if (InvertCond) {
1869 if (BOpc == Instruction::And)
1870 BOpc = Instruction::Or;
1871 else if (BOpc == Instruction::Or)
1872 BOpc = Instruction::And;
1873 }
1874 }
1875
1876 // If this node is not part of the or/and tree, emit it as a branch.
1877 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1878 BOpc != unsigned(Opc) || !BOp->hasOneUse() ||
1879 BOp->getParent() != CurBB->getBasicBlock() ||
1880 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1881 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1882 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB,
1883 TProb, FProb, InvertCond);
1884 return;
1885 }
1886
1887 // Create TmpBB after CurBB.
1888 MachineFunction::iterator BBI(CurBB);
1889 MachineFunction &MF = DAG.getMachineFunction();
1890 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1891 CurBB->getParent()->insert(++BBI, TmpBB);
1892
1893 if (Opc == Instruction::Or) {
1894 // Codegen X | Y as:
1895 // BB1:
1896 // jmp_if_X TBB
1897 // jmp TmpBB
1898 // TmpBB:
1899 // jmp_if_Y TBB
1900 // jmp FBB
1901 //
1902
1903 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1904 // The requirement is that
1905 // TrueProb for BB1 + (FalseProb for BB1 * TrueProb for TmpBB)
1906 // = TrueProb for original BB.
1907 // Assuming the original probabilities are A and B, one choice is to set
1908 // BB1's probabilities to A/2 and A/2+B, and set TmpBB's probabilities to
1909 // A/(1+B) and 2B/(1+B). This choice assumes that
1910 // TrueProb for BB1 == FalseProb for BB1 * TrueProb for TmpBB.
1911 // Another choice is to assume TrueProb for BB1 equals to TrueProb for
1912 // TmpBB, but the math is more complicated.
1913
1914 auto NewTrueProb = TProb / 2;
1915 auto NewFalseProb = TProb / 2 + FProb;
1916 // Emit the LHS condition.
1917 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc,
1918 NewTrueProb, NewFalseProb, InvertCond);
1919
1920 // Normalize A/2 and B to get A/(1+B) and 2B/(1+B).
1921 SmallVector<BranchProbability, 2> Probs{TProb / 2, FProb};
1922 BranchProbability::normalizeProbabilities(Probs.begin(), Probs.end());
1923 // Emit the RHS condition into TmpBB.
1924 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1925 Probs[0], Probs[1], InvertCond);
1926 } else {
1927 assert(Opc == Instruction::And && "Unknown merge op!")((Opc == Instruction::And && "Unknown merge op!") ? static_cast
<void> (0) : __assert_fail ("Opc == Instruction::And && \"Unknown merge op!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 1927, __PRETTY_FUNCTION__))
;
1928 // Codegen X & Y as:
1929 // BB1:
1930 // jmp_if_X TmpBB
1931 // jmp FBB
1932 // TmpBB:
1933 // jmp_if_Y TBB
1934 // jmp FBB
1935 //
1936 // This requires creation of TmpBB after CurBB.
1937
1938 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1939 // The requirement is that
1940 // FalseProb for BB1 + (TrueProb for BB1 * FalseProb for TmpBB)
1941 // = FalseProb for original BB.
1942 // Assuming the original probabilities are A and B, one choice is to set
1943 // BB1's probabilities to A+B/2 and B/2, and set TmpBB's probabilities to
1944 // 2A/(1+A) and B/(1+A). This choice assumes that FalseProb for BB1 ==
1945 // TrueProb for BB1 * FalseProb for TmpBB.
1946
1947 auto NewTrueProb = TProb + FProb / 2;
1948 auto NewFalseProb = FProb / 2;
1949 // Emit the LHS condition.
1950 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc,
1951 NewTrueProb, NewFalseProb, InvertCond);
1952
1953 // Normalize A and B/2 to get 2A/(1+A) and B/(1+A).
1954 SmallVector<BranchProbability, 2> Probs{TProb, FProb / 2};
1955 BranchProbability::normalizeProbabilities(Probs.begin(), Probs.end());
1956 // Emit the RHS condition into TmpBB.
1957 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1958 Probs[0], Probs[1], InvertCond);
1959 }
1960}
1961
1962/// If the set of cases should be emitted as a series of branches, return true.
1963/// If we should emit this as a bunch of and/or'd together conditions, return
1964/// false.
1965bool
1966SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases) {
1967 if (Cases.size() != 2) return true;
1968
1969 // If this is two comparisons of the same values or'd or and'd together, they
1970 // will get folded into a single comparison, so don't emit two blocks.
1971 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1972 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1973 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1974 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1975 return false;
1976 }
1977
1978 // Handle: (X != null) | (Y != null) --> (X|Y) != 0
1979 // Handle: (X == null) & (Y == null) --> (X|Y) == 0
1980 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
1981 Cases[0].CC == Cases[1].CC &&
1982 isa<Constant>(Cases[0].CmpRHS) &&
1983 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
1984 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
1985 return false;
1986 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
1987 return false;
1988 }
1989
1990 return true;
1991}
1992
1993void SelectionDAGBuilder::visitBr(const BranchInst &I) {
1994 MachineBasicBlock *BrMBB = FuncInfo.MBB;
1995
1996 // Update machine-CFG edges.
1997 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1998
1999 if (I.isUnconditional()) {
2000 // Update machine-CFG edges.
2001 BrMBB->addSuccessor(Succ0MBB);
2002
2003 // If this is not a fall-through branch or optimizations are switched off,
2004 // emit the branch.
2005 if (Succ0MBB != NextBlock(BrMBB) || TM.getOptLevel() == CodeGenOpt::None)
2006 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
2007 MVT::Other, getControlRoot(),
2008 DAG.getBasicBlock(Succ0MBB)));
2009
2010 return;
2011 }
2012
2013 // If this condition is one of the special cases we handle, do special stuff
2014 // now.
2015 const Value *CondVal = I.getCondition();
2016 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
2017
2018 // If this is a series of conditions that are or'd or and'd together, emit
2019 // this as a sequence of branches instead of setcc's with and/or operations.
2020 // As long as jumps are not expensive, this should improve performance.
2021 // For example, instead of something like:
2022 // cmp A, B
2023 // C = seteq
2024 // cmp D, E
2025 // F = setle
2026 // or C, F
2027 // jnz foo
2028 // Emit:
2029 // cmp A, B
2030 // je foo
2031 // cmp D, E
2032 // jle foo
2033 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
2034 Instruction::BinaryOps Opcode = BOp->getOpcode();
2035 if (!DAG.getTargetLoweringInfo().isJumpExpensive() && BOp->hasOneUse() &&
2036 !I.getMetadata(LLVMContext::MD_unpredictable) &&
2037 (Opcode == Instruction::And || Opcode == Instruction::Or)) {
2038 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB,
2039 Opcode,
2040 getEdgeProbability(BrMBB, Succ0MBB),
2041 getEdgeProbability(BrMBB, Succ1MBB),
2042 /*InvertCond=*/false);
2043 // If the compares in later blocks need to use values not currently
2044 // exported from this block, export them now. This block should always
2045 // be the first entry.
2046 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!")((SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!"
) ? static_cast<void> (0) : __assert_fail ("SwitchCases[0].ThisBB == BrMBB && \"Unexpected lowering!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 2046, __PRETTY_FUNCTION__))
;
2047
2048 // Allow some cases to be rejected.
2049 if (ShouldEmitAsBranches(SwitchCases)) {
2050 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
2051 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
2052 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
2053 }
2054
2055 // Emit the branch for this block.
2056 visitSwitchCase(SwitchCases[0], BrMBB);
2057 SwitchCases.erase(SwitchCases.begin());
2058 return;
2059 }
2060
2061 // Okay, we decided not to do this, remove any inserted MBB's and clear
2062 // SwitchCases.
2063 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
2064 FuncInfo.MF->erase(SwitchCases[i].ThisBB);
2065
2066 SwitchCases.clear();
2067 }
2068 }
2069
2070 // Create a CaseBlock record representing this branch.
2071 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
2072 nullptr, Succ0MBB, Succ1MBB, BrMBB, getCurSDLoc());
2073
2074 // Use visitSwitchCase to actually insert the fast branch sequence for this
2075 // cond branch.
2076 visitSwitchCase(CB, BrMBB);
2077}
2078
2079/// visitSwitchCase - Emits the necessary code to represent a single node in
2080/// the binary search tree resulting from lowering a switch instruction.
2081void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB,
2082 MachineBasicBlock *SwitchBB) {
2083 SDValue Cond;
2084 SDValue CondLHS = getValue(CB.CmpLHS);
2085 SDLoc dl = CB.DL;
2086
2087 // Build the setcc now.
2088 if (!CB.CmpMHS) {
2089 // Fold "(X == true)" to X and "(X == false)" to !X to
2090 // handle common cases produced by branch lowering.
2091 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
2092 CB.CC == ISD::SETEQ)
2093 Cond = CondLHS;
2094 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
2095 CB.CC == ISD::SETEQ) {
2096 SDValue True = DAG.getConstant(1, dl, CondLHS.getValueType());
2097 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
2098 } else
2099 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
2100 } else {
2101 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now")((CB.CC == ISD::SETLE && "Can handle only LE ranges now"
) ? static_cast<void> (0) : __assert_fail ("CB.CC == ISD::SETLE && \"Can handle only LE ranges now\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 2101, __PRETTY_FUNCTION__))
;
2102
2103 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
2104 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
2105
2106 SDValue CmpOp = getValue(CB.CmpMHS);
2107 EVT VT = CmpOp.getValueType();
2108
2109 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
2110 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, dl, VT),
2111 ISD::SETLE);
2112 } else {
2113 SDValue SUB = DAG.getNode(ISD::SUB, dl,
2114 VT, CmpOp, DAG.getConstant(Low, dl, VT));
2115 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
2116 DAG.getConstant(High-Low, dl, VT), ISD::SETULE);
2117 }
2118 }
2119
2120 // Update successor info
2121 addSuccessorWithProb(SwitchBB, CB.TrueBB, CB.TrueProb);
2122 // TrueBB and FalseBB are always different unless the incoming IR is
2123 // degenerate. This only happens when running llc on weird IR.
2124 if (CB.TrueBB != CB.FalseBB)
2125 addSuccessorWithProb(SwitchBB, CB.FalseBB, CB.FalseProb);
2126 SwitchBB->normalizeSuccProbs();
2127
2128 // If the lhs block is the next block, invert the condition so that we can
2129 // fall through to the lhs instead of the rhs block.
2130 if (CB.TrueBB == NextBlock(SwitchBB)) {
2131 std::swap(CB.TrueBB, CB.FalseBB);
2132 SDValue True = DAG.getConstant(1, dl, Cond.getValueType());
2133 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
2134 }
2135
2136 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
2137 MVT::Other, getControlRoot(), Cond,
2138 DAG.getBasicBlock(CB.TrueBB));
2139
2140 // Insert the false branch. Do this even if it's a fall through branch,
2141 // this makes it easier to do DAG optimizations which require inverting
2142 // the branch condition.
2143 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
2144 DAG.getBasicBlock(CB.FalseBB));
2145
2146 DAG.setRoot(BrCond);
2147}
2148
2149/// visitJumpTable - Emit JumpTable node in the current MBB
2150void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
2151 // Emit the code for the jump table
2152 assert(JT.Reg != -1U && "Should lower JT Header first!")((JT.Reg != -1U && "Should lower JT Header first!") ?
static_cast<void> (0) : __assert_fail ("JT.Reg != -1U && \"Should lower JT Header first!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 2152, __PRETTY_FUNCTION__))
;
2153 EVT PTy = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
2154 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(),
2155 JT.Reg, PTy);
2156 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
2157 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurSDLoc(),
2158 MVT::Other, Index.getValue(1),
2159 Table, Index);
2160 DAG.setRoot(BrJumpTable);
2161}
2162
2163/// visitJumpTableHeader - This function emits necessary code to produce index
2164/// in the JumpTable from switch case.
2165void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
2166 JumpTableHeader &JTH,
2167 MachineBasicBlock *SwitchBB) {
2168 SDLoc dl = getCurSDLoc();
2169
2170 // Subtract the lowest switch case value from the value being switched on and
2171 // conditional branch to default mbb if the result is greater than the
2172 // difference between smallest and largest cases.
2173 SDValue SwitchOp = getValue(JTH.SValue);
2174 EVT VT = SwitchOp.getValueType();
2175 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, SwitchOp,
2176 DAG.getConstant(JTH.First, dl, VT));
2177
2178 // The SDNode we just created, which holds the value being switched on minus
2179 // the smallest case value, needs to be copied to a virtual register so it
2180 // can be used as an index into the jump table in a subsequent basic block.
2181 // This value may be smaller or larger than the target's pointer type, and
2182 // therefore require extension or truncating.
2183 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2184 SwitchOp = DAG.getZExtOrTrunc(Sub, dl, TLI.getPointerTy(DAG.getDataLayout()));
2185
2186 unsigned JumpTableReg =
2187 FuncInfo.CreateReg(TLI.getPointerTy(DAG.getDataLayout()));
2188 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), dl,
2189 JumpTableReg, SwitchOp);
2190 JT.Reg = JumpTableReg;
2191
2192 // Emit the range check for the jump table, and branch to the default block
2193 // for the switch statement if the value being switched on exceeds the largest
2194 // case in the switch.
2195 SDValue CMP = DAG.getSetCC(
2196 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
2197 Sub.getValueType()),
2198 Sub, DAG.getConstant(JTH.Last - JTH.First, dl, VT), ISD::SETUGT);
2199
2200 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
2201 MVT::Other, CopyTo, CMP,
2202 DAG.getBasicBlock(JT.Default));
2203
2204 // Avoid emitting unnecessary branches to the next block.
2205 if (JT.MBB != NextBlock(SwitchBB))
2206 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
2207 DAG.getBasicBlock(JT.MBB));
2208
2209 DAG.setRoot(BrCond);
2210}
2211
2212/// Create a LOAD_STACK_GUARD node, and let it carry the target specific global
2213/// variable if there exists one.
2214static SDValue getLoadStackGuard(SelectionDAG &DAG, const SDLoc &DL,
2215 SDValue &Chain) {
2216 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2217 EVT PtrTy = TLI.getPointerTy(DAG.getDataLayout());
2218 MachineFunction &MF = DAG.getMachineFunction();
2219 Value *Global = TLI.getSDagStackGuard(*MF.getFunction().getParent());
2220 MachineSDNode *Node =
2221 DAG.getMachineNode(TargetOpcode::LOAD_STACK_GUARD, DL, PtrTy, Chain);
2222 if (Global) {
2223 MachinePointerInfo MPInfo(Global);
2224 auto Flags = MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant |
2225 MachineMemOperand::MODereferenceable;
2226 MachineMemOperand *MemRef = MF.getMachineMemOperand(
2227 MPInfo, Flags, PtrTy.getSizeInBits() / 8, DAG.getEVTAlignment(PtrTy));
2228 DAG.setNodeMemRefs(Node, {MemRef});
2229 }
2230 return SDValue(Node, 0);
2231}
2232
2233/// Codegen a new tail for a stack protector check ParentMBB which has had its
2234/// tail spliced into a stack protector check success bb.
2235///
2236/// For a high level explanation of how this fits into the stack protector
2237/// generation see the comment on the declaration of class
2238/// StackProtectorDescriptor.
2239void SelectionDAGBuilder::visitSPDescriptorParent(StackProtectorDescriptor &SPD,
2240 MachineBasicBlock *ParentBB) {
2241
2242 // First create the loads to the guard/stack slot for the comparison.
2243 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2244 EVT PtrTy = TLI.getPointerTy(DAG.getDataLayout());
2245
2246 MachineFrameInfo &MFI = ParentBB->getParent()->getFrameInfo();
2247 int FI = MFI.getStackProtectorIndex();
2248
2249 SDValue Guard;
2250 SDLoc dl = getCurSDLoc();
2251 SDValue StackSlotPtr = DAG.getFrameIndex(FI, PtrTy);
2252 const Module &M = *ParentBB->getParent()->getFunction().getParent();
2253 unsigned Align = DL->getPrefTypeAlignment(Type::getInt8PtrTy(M.getContext()));
2254
2255 // Generate code to load the content of the guard slot.
2256 SDValue GuardVal = DAG.getLoad(
2257 PtrTy, dl, DAG.getEntryNode(), StackSlotPtr,
2258 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI), Align,
2259 MachineMemOperand::MOVolatile);
2260
2261 if (TLI.useStackGuardXorFP())
2262 GuardVal = TLI.emitStackGuardXorFP(DAG, GuardVal, dl);
2263
2264 // Retrieve guard check function, nullptr if instrumentation is inlined.
2265 if (const Value *GuardCheck = TLI.getSSPStackGuardCheck(M)) {
2266 // The target provides a guard check function to validate the guard value.
2267 // Generate a call to that function with the content of the guard slot as
2268 // argument.
2269 auto *Fn = cast<Function>(GuardCheck);
2270 FunctionType *FnTy = Fn->getFunctionType();
2271 assert(FnTy->getNumParams() == 1 && "Invalid function signature")((FnTy->getNumParams() == 1 && "Invalid function signature"
) ? static_cast<void> (0) : __assert_fail ("FnTy->getNumParams() == 1 && \"Invalid function signature\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 2271, __PRETTY_FUNCTION__))
;
2272
2273 TargetLowering::ArgListTy Args;
2274 TargetLowering::ArgListEntry Entry;
2275 Entry.Node = GuardVal;
2276 Entry.Ty = FnTy->getParamType(0);
2277 if (Fn->hasAttribute(1, Attribute::AttrKind::InReg))
2278 Entry.IsInReg = true;
2279 Args.push_back(Entry);
2280
2281 TargetLowering::CallLoweringInfo CLI(DAG);
2282 CLI.setDebugLoc(getCurSDLoc())
2283 .setChain(DAG.getEntryNode())
2284 .setCallee(Fn->getCallingConv(), FnTy->getReturnType(),
2285 getValue(GuardCheck), std::move(Args));
2286
2287 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
2288 DAG.setRoot(Result.second);
2289 return;
2290 }
2291
2292 // If useLoadStackGuardNode returns true, generate LOAD_STACK_GUARD.
2293 // Otherwise, emit a volatile load to retrieve the stack guard value.
2294 SDValue Chain = DAG.getEntryNode();
2295 if (TLI.useLoadStackGuardNode()) {
2296 Guard = getLoadStackGuard(DAG, dl, Chain);
2297 } else {
2298 const Value *IRGuard = TLI.getSDagStackGuard(M);
2299 SDValue GuardPtr = getValue(IRGuard);
2300
2301 Guard =
2302 DAG.getLoad(PtrTy, dl, Chain, GuardPtr, MachinePointerInfo(IRGuard, 0),
2303 Align, MachineMemOperand::MOVolatile);
2304 }
2305
2306 // Perform the comparison via a subtract/getsetcc.
2307 EVT VT = Guard.getValueType();
2308 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, Guard, GuardVal);
2309
2310 SDValue Cmp = DAG.getSetCC(dl, TLI.getSetCCResultType(DAG.getDataLayout(),
2311 *DAG.getContext(),
2312 Sub.getValueType()),
2313 Sub, DAG.getConstant(0, dl, VT), ISD::SETNE);
2314
2315 // If the sub is not 0, then we know the guard/stackslot do not equal, so
2316 // branch to failure MBB.
2317 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
2318 MVT::Other, GuardVal.getOperand(0),
2319 Cmp, DAG.getBasicBlock(SPD.getFailureMBB()));
2320 // Otherwise branch to success MBB.
2321 SDValue Br = DAG.getNode(ISD::BR, dl,
2322 MVT::Other, BrCond,
2323 DAG.getBasicBlock(SPD.getSuccessMBB()));
2324
2325 DAG.setRoot(Br);
2326}
2327
2328/// Codegen the failure basic block for a stack protector check.
2329///
2330/// A failure stack protector machine basic block consists simply of a call to
2331/// __stack_chk_fail().
2332///
2333/// For a high level explanation of how this fits into the stack protector
2334/// generation see the comment on the declaration of class
2335/// StackProtectorDescriptor.
2336void
2337SelectionDAGBuilder::visitSPDescriptorFailure(StackProtectorDescriptor &SPD) {
2338 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2339 SDValue Chain =
2340 TLI.makeLibCall(DAG, RTLIB::STACKPROTECTOR_CHECK_FAIL, MVT::isVoid,
2341 None, false, getCurSDLoc(), false, false).second;
2342 DAG.setRoot(Chain);
2343}
2344
2345/// visitBitTestHeader - This function emits necessary code to produce value
2346/// suitable for "bit tests"
2347void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
2348 MachineBasicBlock *SwitchBB) {
2349 SDLoc dl = getCurSDLoc();
2350
2351 // Subtract the minimum value
2352 SDValue SwitchOp = getValue(B.SValue);
2353 EVT VT = SwitchOp.getValueType();
2354 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, SwitchOp,
2355 DAG.getConstant(B.First, dl, VT));
2356
2357 // Check range
2358 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2359 SDValue RangeCmp = DAG.getSetCC(
2360 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
2361 Sub.getValueType()),
2362 Sub, DAG.getConstant(B.Range, dl, VT), ISD::SETUGT);
2363
2364 // Determine the type of the test operands.
2365 bool UsePtrType = false;
2366 if (!TLI.isTypeLegal(VT))
2367 UsePtrType = true;
2368 else {
2369 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i)
2370 if (!isUIntN(VT.getSizeInBits(), B.Cases[i].Mask)) {
2371 // Switch table case range are encoded into series of masks.
2372 // Just use pointer type, it's guaranteed to fit.
2373 UsePtrType = true;
2374 break;
2375 }
2376 }
2377 if (UsePtrType) {
2378 VT = TLI.getPointerTy(DAG.getDataLayout());
2379 Sub = DAG.getZExtOrTrunc(Sub, dl, VT);
2380 }
2381
2382 B.RegVT = VT.getSimpleVT();
2383 B.Reg = FuncInfo.CreateReg(B.RegVT);
2384 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), dl, B.Reg, Sub);
2385
2386 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
2387
2388 addSuccessorWithProb(SwitchBB, B.Default, B.DefaultProb);
2389 addSuccessorWithProb(SwitchBB, MBB, B.Prob);
2390 SwitchBB->normalizeSuccProbs();
2391
2392 SDValue BrRange = DAG.getNode(ISD::BRCOND, dl,
2393 MVT::Other, CopyTo, RangeCmp,
2394 DAG.getBasicBlock(B.Default));
2395
2396 // Avoid emitting unnecessary branches to the next block.
2397 if (MBB != NextBlock(SwitchBB))
2398 BrRange = DAG.getNode(ISD::BR, dl, MVT::Other, BrRange,
2399 DAG.getBasicBlock(MBB));
2400
2401 DAG.setRoot(BrRange);
2402}
2403
2404/// visitBitTestCase - this function produces one "bit test"
2405void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB,
2406 MachineBasicBlock* NextMBB,
2407 BranchProbability BranchProbToNext,
2408 unsigned Reg,
2409 BitTestCase &B,
2410 MachineBasicBlock *SwitchBB) {
2411 SDLoc dl = getCurSDLoc();
2412 MVT VT = BB.RegVT;
2413 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), dl, Reg, VT);
2414 SDValue Cmp;
2415 unsigned PopCount = countPopulation(B.Mask);
2416 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2417 if (PopCount == 1) {
2418 // Testing for a single bit; just compare the shift count with what it
2419 // would need to be to shift a 1 bit in that position.
2420 Cmp = DAG.getSetCC(
2421 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT),
2422 ShiftOp, DAG.getConstant(countTrailingZeros(B.Mask), dl, VT),
2423 ISD::SETEQ);
2424 } else if (PopCount == BB.Range) {
2425 // There is only one zero bit in the range, test for it directly.
2426 Cmp = DAG.getSetCC(
2427 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT),
2428 ShiftOp, DAG.getConstant(countTrailingOnes(B.Mask), dl, VT),
2429 ISD::SETNE);
2430 } else {
2431 // Make desired shift
2432 SDValue SwitchVal = DAG.getNode(ISD::SHL, dl, VT,
2433 DAG.getConstant(1, dl, VT), ShiftOp);
2434
2435 // Emit bit tests and jumps
2436 SDValue AndOp = DAG.getNode(ISD::AND, dl,
2437 VT, SwitchVal, DAG.getConstant(B.Mask, dl, VT));
2438 Cmp = DAG.getSetCC(
2439 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT),
2440 AndOp, DAG.getConstant(0, dl, VT), ISD::SETNE);
2441 }
2442
2443 // The branch probability from SwitchBB to B.TargetBB is B.ExtraProb.
2444 addSuccessorWithProb(SwitchBB, B.TargetBB, B.ExtraProb);
2445 // The branch probability from SwitchBB to NextMBB is BranchProbToNext.
2446 addSuccessorWithProb(SwitchBB, NextMBB, BranchProbToNext);
2447 // It is not guaranteed that the sum of B.ExtraProb and BranchProbToNext is
2448 // one as they are relative probabilities (and thus work more like weights),
2449 // and hence we need to normalize them to let the sum of them become one.
2450 SwitchBB->normalizeSuccProbs();
2451
2452 SDValue BrAnd = DAG.getNode(ISD::BRCOND, dl,
2453 MVT::Other, getControlRoot(),
2454 Cmp, DAG.getBasicBlock(B.TargetBB));
2455
2456 // Avoid emitting unnecessary branches to the next block.
2457 if (NextMBB != NextBlock(SwitchBB))
2458 BrAnd = DAG.getNode(ISD::BR, dl, MVT::Other, BrAnd,
2459 DAG.getBasicBlock(NextMBB));
2460
2461 DAG.setRoot(BrAnd);
2462}
2463
2464void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
2465 MachineBasicBlock *InvokeMBB = FuncInfo.MBB;
2466
2467 // Retrieve successors. Look through artificial IR level blocks like
2468 // catchswitch for successors.
2469 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
2470 const BasicBlock *EHPadBB = I.getSuccessor(1);
2471
2472 // Deopt bundles are lowered in LowerCallSiteWithDeoptBundle, and we don't
2473 // have to do anything here to lower funclet bundles.
2474 assert(!I.hasOperandBundlesOtherThan(((!I.hasOperandBundlesOtherThan( {LLVMContext::OB_deopt, LLVMContext
::OB_funclet}) && "Cannot lower invokes with arbitrary operand bundles yet!"
) ? static_cast<void> (0) : __assert_fail ("!I.hasOperandBundlesOtherThan( {LLVMContext::OB_deopt, LLVMContext::OB_funclet}) && \"Cannot lower invokes with arbitrary operand bundles yet!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 2476, __PRETTY_FUNCTION__))
2475 {LLVMContext::OB_deopt, LLVMContext::OB_funclet}) &&((!I.hasOperandBundlesOtherThan( {LLVMContext::OB_deopt, LLVMContext
::OB_funclet}) && "Cannot lower invokes with arbitrary operand bundles yet!"
) ? static_cast<void> (0) : __assert_fail ("!I.hasOperandBundlesOtherThan( {LLVMContext::OB_deopt, LLVMContext::OB_funclet}) && \"Cannot lower invokes with arbitrary operand bundles yet!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 2476, __PRETTY_FUNCTION__))
2476 "Cannot lower invokes with arbitrary operand bundles yet!")((!I.hasOperandBundlesOtherThan( {LLVMContext::OB_deopt, LLVMContext
::OB_funclet}) && "Cannot lower invokes with arbitrary operand bundles yet!"
) ? static_cast<void> (0) : __assert_fail ("!I.hasOperandBundlesOtherThan( {LLVMContext::OB_deopt, LLVMContext::OB_funclet}) && \"Cannot lower invokes with arbitrary operand bundles yet!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 2476, __PRETTY_FUNCTION__))
;
2477
2478 const Value *Callee(I.getCalledValue());
2479 const Function *Fn = dyn_cast<Function>(Callee);
2480 if (isa<InlineAsm>(Callee))
2481 visitInlineAsm(&I);
2482 else if (Fn && Fn->isIntrinsic()) {
2483 switch (Fn->getIntrinsicID()) {
2484 default:
2485 llvm_unreachable("Cannot invoke this intrinsic")::llvm::llvm_unreachable_internal("Cannot invoke this intrinsic"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 2485)
;
2486 case Intrinsic::donothing:
2487 // Ignore invokes to @llvm.donothing: jump directly to the next BB.
2488 break;
2489 case Intrinsic::experimental_patchpoint_void:
2490 case Intrinsic::experimental_patchpoint_i64:
2491 visitPatchpoint(&I, EHPadBB);
2492 break;
2493 case Intrinsic::experimental_gc_statepoint:
2494 LowerStatepoint(ImmutableStatepoint(&I), EHPadBB);
2495 break;
2496 }
2497 } else if (I.countOperandBundlesOfType(LLVMContext::OB_deopt)) {
2498 // Currently we do not lower any intrinsic calls with deopt operand bundles.
2499 // Eventually we will support lowering the @llvm.experimental.deoptimize
2500 // intrinsic, and right now there are no plans to support other intrinsics
2501 // with deopt state.
2502 LowerCallSiteWithDeoptBundle(&I, getValue(Callee), EHPadBB);
2503 } else {
2504 LowerCallTo(&I, getValue(Callee), false, EHPadBB);
2505 }
2506
2507 // If the value of the invoke is used outside of its defining block, make it
2508 // available as a virtual register.
2509 // We already took care of the exported value for the statepoint instruction
2510 // during call to the LowerStatepoint.
2511 if (!isStatepoint(I)) {
2512 CopyToExportRegsIfNeeded(&I);
2513 }
2514
2515 SmallVector<std::pair<MachineBasicBlock *, BranchProbability>, 1> UnwindDests;
2516 BranchProbabilityInfo *BPI = FuncInfo.BPI;
2517 BranchProbability EHPadBBProb =
2518 BPI ? BPI->getEdgeProbability(InvokeMBB->getBasicBlock(), EHPadBB)
2519 : BranchProbability::getZero();
2520 findUnwindDestinations(FuncInfo, EHPadBB, EHPadBBProb, UnwindDests);
2521
2522 // Update successor info.
2523 addSuccessorWithProb(InvokeMBB, Return);
2524 for (auto &UnwindDest : UnwindDests) {
2525 UnwindDest.first->setIsEHPad();
2526 addSuccessorWithProb(InvokeMBB, UnwindDest.first, UnwindDest.second);
2527 }
2528 InvokeMBB->normalizeSuccProbs();
2529
2530 // Drop into normal successor.
2531 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
2532 MVT::Other, getControlRoot(),
2533 DAG.getBasicBlock(Return)));
2534}
2535
2536void SelectionDAGBuilder::visitResume(const ResumeInst &RI) {
2537 llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!")::llvm::llvm_unreachable_internal("SelectionDAGBuilder shouldn't visit resume instructions!"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 2537)
;
2538}
2539
2540void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) {
2541 assert(FuncInfo.MBB->isEHPad() &&((FuncInfo.MBB->isEHPad() && "Call to landingpad not in landing pad!"
) ? static_cast<void> (0) : __assert_fail ("FuncInfo.MBB->isEHPad() && \"Call to landingpad not in landing pad!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 2542, __PRETTY_FUNCTION__))
2542 "Call to landingpad not in landing pad!")((FuncInfo.MBB->isEHPad() && "Call to landingpad not in landing pad!"
) ? static_cast<void> (0) : __assert_fail ("FuncInfo.MBB->isEHPad() && \"Call to landingpad not in landing pad!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 2542, __PRETTY_FUNCTION__))
;
2543
2544 // If there aren't registers to copy the values into (e.g., during SjLj
2545 // exceptions), then don't bother to create these DAG nodes.
2546 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2547 const Constant *PersonalityFn = FuncInfo.Fn->getPersonalityFn();
2548 if (TLI.getExceptionPointerRegister(PersonalityFn) == 0 &&
2549 TLI.getExceptionSelectorRegister(PersonalityFn) == 0)
2550 return;
2551
2552 // If landingpad's return type is token type, we don't create DAG nodes
2553 // for its exception pointer and selector value. The extraction of exception
2554 // pointer or selector value from token type landingpads is not currently
2555 // supported.
2556 if (LP.getType()->isTokenTy())
2557 return;
2558
2559 SmallVector<EVT, 2> ValueVTs;
2560 SDLoc dl = getCurSDLoc();
2561 ComputeValueVTs(TLI, DAG.getDataLayout(), LP.getType(), ValueVTs);
2562 assert(ValueVTs.size() == 2 && "Only two-valued landingpads are supported")((ValueVTs.size() == 2 && "Only two-valued landingpads are supported"
) ? static_cast<void> (0) : __assert_fail ("ValueVTs.size() == 2 && \"Only two-valued landingpads are supported\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 2562, __PRETTY_FUNCTION__))
;
2563
2564 // Get the two live-in registers as SDValues. The physregs have already been
2565 // copied into virtual registers.
2566 SDValue Ops[2];
2567 if (FuncInfo.ExceptionPointerVirtReg) {
2568 Ops[0] = DAG.getZExtOrTrunc(
2569 DAG.getCopyFromReg(DAG.getEntryNode(), dl,
2570 FuncInfo.ExceptionPointerVirtReg,
2571 TLI.getPointerTy(DAG.getDataLayout())),
2572 dl, ValueVTs[0]);
2573 } else {
2574 Ops[0] = DAG.getConstant(0, dl, TLI.getPointerTy(DAG.getDataLayout()));
2575 }
2576 Ops[1] = DAG.getZExtOrTrunc(
2577 DAG.getCopyFromReg(DAG.getEntryNode(), dl,
2578 FuncInfo.ExceptionSelectorVirtReg,
2579 TLI.getPointerTy(DAG.getDataLayout())),
2580 dl, ValueVTs[1]);
2581
2582 // Merge into one.
2583 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl,
2584 DAG.getVTList(ValueVTs), Ops);
2585 setValue(&LP, Res);
2586}
2587
2588void SelectionDAGBuilder::sortAndRangeify(CaseClusterVector &Clusters) {
2589#ifndef NDEBUG
2590 for (const CaseCluster &CC : Clusters)
2591 assert(CC.Low == CC.High && "Input clusters must be single-case")((CC.Low == CC.High && "Input clusters must be single-case"
) ? static_cast<void> (0) : __assert_fail ("CC.Low == CC.High && \"Input clusters must be single-case\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 2591, __PRETTY_FUNCTION__))
;
2592#endif
2593
2594 llvm::sort(Clusters, [](const CaseCluster &a, const CaseCluster &b) {
2595 return a.Low->getValue().slt(b.Low->getValue());
2596 });
2597
2598 // Merge adjacent clusters with the same destination.
2599 const unsigned N = Clusters.size();
2600 unsigned DstIndex = 0;
2601 for (unsigned SrcIndex = 0; SrcIndex < N; ++SrcIndex) {
2602 CaseCluster &CC = Clusters[SrcIndex];
2603 const ConstantInt *CaseVal = CC.Low;
2604 MachineBasicBlock *Succ = CC.MBB;
2605
2606 if (DstIndex != 0 && Clusters[DstIndex - 1].MBB == Succ &&
2607 (CaseVal->getValue() - Clusters[DstIndex - 1].High->getValue()) == 1) {
2608 // If this case has the same successor and is a neighbour, merge it into
2609 // the previous cluster.
2610 Clusters[DstIndex - 1].High = CaseVal;
2611 Clusters[DstIndex - 1].Prob += CC.Prob;
2612 } else {
2613 std::memmove(&Clusters[DstIndex++], &Clusters[SrcIndex],
2614 sizeof(Clusters[SrcIndex]));
2615 }
2616 }
2617 Clusters.resize(DstIndex);
2618}
2619
2620void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First,
2621 MachineBasicBlock *Last) {
2622 // Update JTCases.
2623 for (unsigned i = 0, e = JTCases.size(); i != e; ++i)
2624 if (JTCases[i].first.HeaderBB == First)
2625 JTCases[i].first.HeaderBB = Last;
2626
2627 // Update BitTestCases.
2628 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i)
2629 if (BitTestCases[i].Parent == First)
2630 BitTestCases[i].Parent = Last;
2631}
2632
2633void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
2634 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB;
2635
2636 // Update machine-CFG edges with unique successors.
2637 SmallSet<BasicBlock*, 32> Done;
2638 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) {
2639 BasicBlock *BB = I.getSuccessor(i);
2640 bool Inserted = Done.insert(BB).second;
2641 if (!Inserted)
2642 continue;
2643
2644 MachineBasicBlock *Succ = FuncInfo.MBBMap[BB];
2645 addSuccessorWithProb(IndirectBrMBB, Succ);
2646 }
2647 IndirectBrMBB->normalizeSuccProbs();
2648
2649 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurSDLoc(),
2650 MVT::Other, getControlRoot(),
2651 getValue(I.getAddress())));
2652}
2653
2654void SelectionDAGBuilder::visitUnreachable(const UnreachableInst &I) {
2655 if (!DAG.getTarget().Options.TrapUnreachable)
2656 return;
2657
2658 // We may be able to ignore unreachable behind a noreturn call.
2659 if (DAG.getTarget().Options.NoTrapAfterNoreturn) {
2660 const BasicBlock &BB = *I.getParent();
2661 if (&I != &BB.front()) {
2662 BasicBlock::const_iterator PredI =
2663 std::prev(BasicBlock::const_iterator(&I));
2664 if (const CallInst *Call = dyn_cast<CallInst>(&*PredI)) {
2665 if (Call->doesNotReturn())
2666 return;
2667 }
2668 }
2669 }
2670
2671 DAG.setRoot(DAG.getNode(ISD::TRAP, getCurSDLoc(), MVT::Other, DAG.getRoot()));
2672}
2673
2674void SelectionDAGBuilder::visitFSub(const User &I) {
2675 // -0.0 - X --> fneg
2676 Type *Ty = I.getType();
2677 if (isa<Constant>(I.getOperand(0)) &&
2678 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) {
2679 SDValue Op2 = getValue(I.getOperand(1));
2680 setValue(&I, DAG.getNode(ISD::FNEG, getCurSDLoc(),
2681 Op2.getValueType(), Op2));
2682 return;
2683 }
2684
2685 visitBinary(I, ISD::FSUB);
2686}
2687
2688/// Checks if the given instruction performs a vector reduction, in which case
2689/// we have the freedom to alter the elements in the result as long as the
2690/// reduction of them stays unchanged.
2691static bool isVectorReductionOp(const User *I) {
2692 const Instruction *Inst = dyn_cast<Instruction>(I);
2693 if (!Inst || !Inst->getType()->isVectorTy())
2694 return false;
2695
2696 auto OpCode = Inst->getOpcode();
2697 switch (OpCode) {
2698 case Instruction::Add:
2699 case Instruction::Mul:
2700 case Instruction::And:
2701 case Instruction::Or:
2702 case Instruction::Xor:
2703 break;
2704 case Instruction::FAdd:
2705 case Instruction::FMul:
2706 if (const FPMathOperator *FPOp = dyn_cast<const FPMathOperator>(Inst))
2707 if (FPOp->getFastMathFlags().isFast())
2708 break;
2709 LLVM_FALLTHROUGH[[clang::fallthrough]];
2710 default:
2711 return false;
2712 }
2713
2714 unsigned ElemNum = Inst->getType()->getVectorNumElements();
2715 // Ensure the reduction size is a power of 2.
2716 if (!isPowerOf2_32(ElemNum))
2717 return false;
2718
2719 unsigned ElemNumToReduce = ElemNum;
2720
2721 // Do DFS search on the def-use chain from the given instruction. We only
2722 // allow four kinds of operations during the search until we reach the
2723 // instruction that extracts the first element from the vector:
2724 //
2725 // 1. The reduction operation of the same opcode as the given instruction.
2726 //
2727 // 2. PHI node.
2728 //
2729 // 3. ShuffleVector instruction together with a reduction operation that
2730 // does a partial reduction.
2731 //
2732 // 4. ExtractElement that extracts the first element from the vector, and we
2733 // stop searching the def-use chain here.
2734 //
2735 // 3 & 4 above perform a reduction on all elements of the vector. We push defs
2736 // from 1-3 to the stack to continue the DFS. The given instruction is not
2737 // a reduction operation if we meet any other instructions other than those
2738 // listed above.
2739
2740 SmallVector<const User *, 16> UsersToVisit{Inst};
2741 SmallPtrSet<const User *, 16> Visited;
2742 bool ReduxExtracted = false;
2743
2744 while (!UsersToVisit.empty()) {
2745 auto User = UsersToVisit.back();
2746 UsersToVisit.pop_back();
2747 if (!Visited.insert(User).second)
2748 continue;
2749
2750 for (const auto &U : User->users()) {
2751 auto Inst = dyn_cast<Instruction>(U);
2752 if (!Inst)
2753 return false;
2754
2755 if (Inst->getOpcode() == OpCode || isa<PHINode>(U)) {
2756 if (const FPMathOperator *FPOp = dyn_cast<const FPMathOperator>(Inst))
2757 if (!isa<PHINode>(FPOp) && !FPOp->getFastMathFlags().isFast())
2758 return false;
2759 UsersToVisit.push_back(U);
2760 } else if (const ShuffleVectorInst *ShufInst =
2761 dyn_cast<ShuffleVectorInst>(U)) {
2762 // Detect the following pattern: A ShuffleVector instruction together
2763 // with a reduction that do partial reduction on the first and second
2764 // ElemNumToReduce / 2 elements, and store the result in
2765 // ElemNumToReduce / 2 elements in another vector.
2766
2767 unsigned ResultElements = ShufInst->getType()->getVectorNumElements();
2768 if (ResultElements < ElemNum)
2769 return false;
2770
2771 if (ElemNumToReduce == 1)
2772 return false;
2773 if (!isa<UndefValue>(U->getOperand(1)))
2774 return false;
2775 for (unsigned i = 0; i < ElemNumToReduce / 2; ++i)
2776 if (ShufInst->getMaskValue(i) != int(i + ElemNumToReduce / 2))
2777 return false;
2778 for (unsigned i = ElemNumToReduce / 2; i < ElemNum; ++i)
2779 if (ShufInst->getMaskValue(i) != -1)
2780 return false;
2781
2782 // There is only one user of this ShuffleVector instruction, which
2783 // must be a reduction operation.
2784 if (!U->hasOneUse())
2785 return false;
2786
2787 auto U2 = dyn_cast<Instruction>(*U->user_begin());
2788 if (!U2 || U2->getOpcode() != OpCode)
2789 return false;
2790
2791 // Check operands of the reduction operation.
2792 if ((U2->getOperand(0) == U->getOperand(0) && U2->getOperand(1) == U) ||
2793 (U2->getOperand(1) == U->getOperand(0) && U2->getOperand(0) == U)) {
2794 UsersToVisit.push_back(U2);
2795 ElemNumToReduce /= 2;
2796 } else
2797 return false;
2798 } else if (isa<ExtractElementInst>(U)) {
2799 // At this moment we should have reduced all elements in the vector.
2800 if (ElemNumToReduce != 1)
2801 return false;
2802
2803 const ConstantInt *Val = dyn_cast<ConstantInt>(U->getOperand(1));
2804 if (!Val || !Val->isZero())
2805 return false;
2806
2807 ReduxExtracted = true;
2808 } else
2809 return false;
2810 }
2811 }
2812 return ReduxExtracted;
2813}
2814
2815void SelectionDAGBuilder::visitUnary(const User &I, unsigned Opcode) {
2816 SDNodeFlags Flags;
2817
2818 SDValue Op = getValue(I.getOperand(0));
2819 SDValue UnNodeValue = DAG.getNode(Opcode, getCurSDLoc(), Op.getValueType(),
2820 Op, Flags);
2821 setValue(&I, UnNodeValue);
2822}
2823
2824void SelectionDAGBuilder::visitBinary(const User &I, unsigned Opcode) {
2825 SDNodeFlags Flags;
2826 if (auto *OFBinOp = dyn_cast<OverflowingBinaryOperator>(&I)) {
2827 Flags.setNoSignedWrap(OFBinOp->hasNoSignedWrap());
2828 Flags.setNoUnsignedWrap(OFBinOp->hasNoUnsignedWrap());
2829 }
2830 if (auto *ExactOp = dyn_cast<PossiblyExactOperator>(&I)) {
2831 Flags.setExact(ExactOp->isExact());
2832 }
2833 if (isVectorReductionOp(&I)) {
2834 Flags.setVectorReduction(true);
2835 LLVM_DEBUG(dbgs() << "Detected a reduction operation:" << I << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << "Detected a reduction operation:"
<< I << "\n"; } } while (false)
;
2836 }
2837
2838 SDValue Op1 = getValue(I.getOperand(0));
2839 SDValue Op2 = getValue(I.getOperand(1));
2840 SDValue BinNodeValue = DAG.getNode(Opcode, getCurSDLoc(), Op1.getValueType(),
2841 Op1, Op2, Flags);
2842 setValue(&I, BinNodeValue);
2843}
2844
2845void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
2846 SDValue Op1 = getValue(I.getOperand(0));
2847 SDValue Op2 = getValue(I.getOperand(1));
2848
2849 EVT ShiftTy = DAG.getTargetLoweringInfo().getShiftAmountTy(
2850 Op1.getValueType(), DAG.getDataLayout());
2851
2852 // Coerce the shift amount to the right type if we can.
2853 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) {
2854 unsigned ShiftSize = ShiftTy.getSizeInBits();
2855 unsigned Op2Size = Op2.getValueSizeInBits();
2856 SDLoc DL = getCurSDLoc();
2857
2858 // If the operand is smaller than the shift count type, promote it.
2859 if (ShiftSize > Op2Size)
2860 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2);
2861
2862 // If the operand is larger than the shift count type but the shift
2863 // count type has enough bits to represent any shift value, truncate
2864 // it now. This is a common case and it exposes the truncate to
2865 // optimization early.
2866 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueSizeInBits()))
2867 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2);
2868 // Otherwise we'll need to temporarily settle for some other convenient
2869 // type. Type legalization will make adjustments once the shiftee is split.
2870 else
2871 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32);
2872 }
2873
2874 bool nuw = false;
2875 bool nsw = false;
2876 bool exact = false;
2877
2878 if (Opcode == ISD::SRL || Opcode == ISD::SRA || Opcode == ISD::SHL) {
2879
2880 if (const OverflowingBinaryOperator *OFBinOp =
2881 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2882 nuw = OFBinOp->hasNoUnsignedWrap();
2883 nsw = OFBinOp->hasNoSignedWrap();
2884 }
2885 if (const PossiblyExactOperator *ExactOp =
2886 dyn_cast<const PossiblyExactOperator>(&I))
2887 exact = ExactOp->isExact();
2888 }
2889 SDNodeFlags Flags;
2890 Flags.setExact(exact);
2891 Flags.setNoSignedWrap(nsw);
2892 Flags.setNoUnsignedWrap(nuw);
2893 SDValue Res = DAG.getNode(Opcode, getCurSDLoc(), Op1.getValueType(), Op1, Op2,
2894 Flags);
2895 setValue(&I, Res);
2896}
2897
2898void SelectionDAGBuilder::visitSDiv(const User &I) {
2899 SDValue Op1 = getValue(I.getOperand(0));
2900 SDValue Op2 = getValue(I.getOperand(1));
2901
2902 SDNodeFlags Flags;
2903 Flags.setExact(isa<PossiblyExactOperator>(&I) &&
2904 cast<PossiblyExactOperator>(&I)->isExact());
2905 setValue(&I, DAG.getNode(ISD::SDIV, getCurSDLoc(), Op1.getValueType(), Op1,
2906 Op2, Flags));
2907}
2908
2909void SelectionDAGBuilder::visitICmp(const User &I) {
2910 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2911 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2912 predicate = IC->getPredicate();
2913 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2914 predicate = ICmpInst::Predicate(IC->getPredicate());
2915 SDValue Op1 = getValue(I.getOperand(0));
2916 SDValue Op2 = getValue(I.getOperand(1));
2917 ISD::CondCode Opcode = getICmpCondCode(predicate);
2918
2919 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2920 I.getType());
2921 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Opcode));
2922}
2923
2924void SelectionDAGBuilder::visitFCmp(const User &I) {
2925 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2926 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2927 predicate = FC->getPredicate();
2928 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2929 predicate = FCmpInst::Predicate(FC->getPredicate());
2930 SDValue Op1 = getValue(I.getOperand(0));
2931 SDValue Op2 = getValue(I.getOperand(1));
2932
2933 ISD::CondCode Condition = getFCmpCondCode(predicate);
2934 auto *FPMO = dyn_cast<FPMathOperator>(&I);
2935 if ((FPMO && FPMO->hasNoNaNs()) || TM.Options.NoNaNsFPMath)
2936 Condition = getFCmpCodeWithoutNaN(Condition);
2937
2938 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2939 I.getType());
2940 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Condition));
2941}
2942
2943// Check if the condition of the select has one use or two users that are both
2944// selects with the same condition.
2945static bool hasOnlySelectUsers(const Value *Cond) {
2946 return llvm::all_of(Cond->users(), [](const Value *V) {
2947 return isa<SelectInst>(V);
2948 });
2949}
2950
2951void SelectionDAGBuilder::visitSelect(const User &I) {
2952 SmallVector<EVT, 4> ValueVTs;
2953 ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(), I.getType(),
2954 ValueVTs);
2955 unsigned NumValues = ValueVTs.size();
2956 if (NumValues == 0) return;
2957
2958 SmallVector<SDValue, 4> Values(NumValues);
2959 SDValue Cond = getValue(I.getOperand(0));
2960 SDValue LHSVal = getValue(I.getOperand(1));
2961 SDValue RHSVal = getValue(I.getOperand(2));
2962 auto BaseOps = {Cond};
2963 ISD::NodeType OpCode = Cond.getValueType().isVector() ?
2964 ISD::VSELECT : ISD::SELECT;
2965
2966 // Min/max matching is only viable if all output VTs are the same.
2967 if (is_splat(ValueVTs)) {
2968 EVT VT = ValueVTs[0];
2969 LLVMContext &Ctx = *DAG.getContext();
2970 auto &TLI = DAG.getTargetLoweringInfo();
2971
2972 // We care about the legality of the operation after it has been type
2973 // legalized.
2974 while (TLI.getTypeAction(Ctx, VT) != TargetLoweringBase::TypeLegal &&
2975 VT != TLI.getTypeToTransformTo(Ctx, VT))
2976 VT = TLI.getTypeToTransformTo(Ctx, VT);
2977
2978 // If the vselect is legal, assume we want to leave this as a vector setcc +
2979 // vselect. Otherwise, if this is going to be scalarized, we want to see if
2980 // min/max is legal on the scalar type.
2981 bool UseScalarMinMax = VT.isVector() &&
2982 !TLI.isOperationLegalOrCustom(ISD::VSELECT, VT);
2983
2984 Value *LHS, *RHS;
2985 auto SPR = matchSelectPattern(const_cast<User*>(&I), LHS, RHS);
2986 ISD::NodeType Opc = ISD::DELETED_NODE;
2987 switch (SPR.Flavor) {
2988 case SPF_UMAX: Opc = ISD::UMAX; break;
2989 case SPF_UMIN: Opc = ISD::UMIN; break;
2990 case SPF_SMAX: Opc = ISD::SMAX; break;
2991 case SPF_SMIN: Opc = ISD::SMIN; break;
2992 case SPF_FMINNUM:
2993 switch (SPR.NaNBehavior) {
2994 case SPNB_NA: llvm_unreachable("No NaN behavior for FP op?")::llvm::llvm_unreachable_internal("No NaN behavior for FP op?"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 2994)
;
2995 case SPNB_RETURNS_NAN: Opc = ISD::FMINIMUM; break;
2996 case SPNB_RETURNS_OTHER: Opc = ISD::FMINNUM; break;
2997 case SPNB_RETURNS_ANY: {
2998 if (TLI.isOperationLegalOrCustom(ISD::FMINNUM, VT))
2999 Opc = ISD::FMINNUM;
3000 else if (TLI.isOperationLegalOrCustom(ISD::FMINIMUM, VT))
3001 Opc = ISD::FMINIMUM;
3002 else if (UseScalarMinMax)
3003 Opc = TLI.isOperationLegalOrCustom(ISD::FMINNUM, VT.getScalarType()) ?
3004 ISD::FMINNUM : ISD::FMINIMUM;
3005 break;
3006 }
3007 }
3008 break;
3009 case SPF_FMAXNUM:
3010 switch (SPR.NaNBehavior) {
3011 case SPNB_NA: llvm_unreachable("No NaN behavior for FP op?")::llvm::llvm_unreachable_internal("No NaN behavior for FP op?"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 3011)
;
3012 case SPNB_RETURNS_NAN: Opc = ISD::FMAXIMUM; break;
3013 case SPNB_RETURNS_OTHER: Opc = ISD::FMAXNUM; break;
3014 case SPNB_RETURNS_ANY:
3015
3016 if (TLI.isOperationLegalOrCustom(ISD::FMAXNUM, VT))
3017 Opc = ISD::FMAXNUM;
3018 else if (TLI.isOperationLegalOrCustom(ISD::FMAXIMUM, VT))
3019 Opc = ISD::FMAXIMUM;
3020 else if (UseScalarMinMax)
3021 Opc = TLI.isOperationLegalOrCustom(ISD::FMAXNUM, VT.getScalarType()) ?
3022 ISD::FMAXNUM : ISD::FMAXIMUM;
3023 break;
3024 }
3025 break;
3026 default: break;
3027 }
3028
3029 if (Opc != ISD::DELETED_NODE &&
3030 (TLI.isOperationLegalOrCustom(Opc, VT) ||
3031 (UseScalarMinMax &&
3032 TLI.isOperationLegalOrCustom(Opc, VT.getScalarType()))) &&
3033 // If the underlying comparison instruction is used by any other
3034 // instruction, the consumed instructions won't be destroyed, so it is
3035 // not profitable to convert to a min/max.
3036 hasOnlySelectUsers(cast<SelectInst>(I).getCondition())) {
3037 OpCode = Opc;
3038 LHSVal = getValue(LHS);
3039 RHSVal = getValue(RHS);
3040 BaseOps = {};
3041 }
3042 }
3043
3044 for (unsigned i = 0; i != NumValues; ++i) {
3045 SmallVector<SDValue, 3> Ops(BaseOps.begin(), BaseOps.end());
3046 Ops.push_back(SDValue(LHSVal.getNode(), LHSVal.getResNo() + i));
3047 Ops.push_back(SDValue(RHSVal.getNode(), RHSVal.getResNo() + i));
3048 Values[i] = DAG.getNode(OpCode, getCurSDLoc(),
3049 LHSVal.getNode()->getValueType(LHSVal.getResNo()+i),
3050 Ops);
3051 }
3052
3053 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
3054 DAG.getVTList(ValueVTs), Values));
3055}
3056
3057void SelectionDAGBuilder::visitTrunc(const User &I) {
3058 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
3059 SDValue N = getValue(I.getOperand(0));
3060 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
3061 I.getType());
3062 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), DestVT, N));
3063}
3064
3065void SelectionDAGBuilder::visitZExt(const User &I) {
3066 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
3067 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
3068 SDValue N = getValue(I.getOperand(0));
3069 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
3070 I.getType());
3071 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurSDLoc(), DestVT, N));
3072}
3073
3074void SelectionDAGBuilder::visitSExt(const User &I) {
3075 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
3076 // SExt also can't be a cast to bool for same reason. So, nothing much to do
3077 SDValue N = getValue(I.getOperand(0));
3078 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
3079 I.getType());
3080 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurSDLoc(), DestVT, N));
3081}
3082
3083void SelectionDAGBuilder::visitFPTrunc(const User &I) {
3084 // FPTrunc is never a no-op cast, no need to check
3085 SDValue N = getValue(I.getOperand(0));
3086 SDLoc dl = getCurSDLoc();
3087 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3088 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
3089 setValue(&I, DAG.getNode(ISD::FP_ROUND, dl, DestVT, N,
3090 DAG.getTargetConstant(
3091 0, dl, TLI.getPointerTy(DAG.getDataLayout()))));
3092}
3093
3094void SelectionDAGBuilder::visitFPExt(const User &I) {
3095 // FPExt is never a no-op cast, no need to check
3096 SDValue N = getValue(I.getOperand(0));
3097 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
3098 I.getType());
3099 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurSDLoc(), DestVT, N));
3100}
3101
3102void SelectionDAGBuilder::visitFPToUI(const User &I) {
3103 // FPToUI is never a no-op cast, no need to check
3104 SDValue N = getValue(I.getOperand(0));
3105 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
3106 I.getType());
3107 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurSDLoc(), DestVT, N));
3108}
3109
3110void SelectionDAGBuilder::visitFPToSI(const User &I) {
3111 // FPToSI is never a no-op cast, no need to check
3112 SDValue N = getValue(I.getOperand(0));
3113 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
3114 I.getType());
3115 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurSDLoc(), DestVT, N));
3116}
3117
3118void SelectionDAGBuilder::visitUIToFP(const User &I) {
3119 // UIToFP is never a no-op cast, no need to check
3120 SDValue N = getValue(I.getOperand(0));
3121 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
3122 I.getType());
3123 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurSDLoc(), DestVT, N));
3124}
3125
3126void SelectionDAGBuilder::visitSIToFP(const User &I) {
3127 // SIToFP is never a no-op cast, no need to check
3128 SDValue N = getValue(I.getOperand(0));
3129 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
3130 I.getType());
3131 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurSDLoc(), DestVT, N));
3132}
3133
3134void SelectionDAGBuilder::visitPtrToInt(const User &I) {
3135 // What to do depends on the size of the integer and the size of the pointer.
3136 // We can either truncate, zero extend, or no-op, accordingly.
3137 SDValue N = getValue(I.getOperand(0));
3138 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
3139 I.getType());
3140 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
3141}
3142
3143void SelectionDAGBuilder::visitIntToPtr(const User &I) {
3144 // What to do depends on the size of the integer and the size of the pointer.
3145 // We can either truncate, zero extend, or no-op, accordingly.
3146 SDValue N = getValue(I.getOperand(0));
3147 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
3148 I.getType());
3149 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
3150}
3151
3152void SelectionDAGBuilder::visitBitCast(const User &I) {
3153 SDValue N = getValue(I.getOperand(0));
3154 SDLoc dl = getCurSDLoc();
3155 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
3156 I.getType());
3157
3158 // BitCast assures us that source and destination are the same size so this is
3159 // either a BITCAST or a no-op.
3160 if (DestVT != N.getValueType())
3161 setValue(&I, DAG.getNode(ISD::BITCAST, dl,
3162 DestVT, N)); // convert types.
3163 // Check if the original LLVM IR Operand was a ConstantInt, because getValue()
3164 // might fold any kind of constant expression to an integer constant and that
3165 // is not what we are looking for. Only recognize a bitcast of a genuine
3166 // constant integer as an opaque constant.
3167 else if(ConstantInt *C = dyn_cast<ConstantInt>(I.getOperand(0)))
3168 setValue(&I, DAG.getConstant(C->getValue(), dl, DestVT, /*isTarget=*/false,
3169 /*isOpaque*/true));
3170 else
3171 setValue(&I, N); // noop cast.
3172}
3173
3174void SelectionDAGBuilder::visitAddrSpaceCast(const User &I) {
3175 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3176 const Value *SV = I.getOperand(0);
3177 SDValue N = getValue(SV);
3178 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
3179
3180 unsigned SrcAS = SV->getType()->getPointerAddressSpace();
3181 unsigned DestAS = I.getType()->getPointerAddressSpace();
3182
3183 if (!TLI.isNoopAddrSpaceCast(SrcAS, DestAS))
3184 N = DAG.getAddrSpaceCast(getCurSDLoc(), DestVT, N, SrcAS, DestAS);
3185
3186 setValue(&I, N);
3187}
3188
3189void SelectionDAGBuilder::visitInsertElement(const User &I) {
3190 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3191 SDValue InVec = getValue(I.getOperand(0));
3192 SDValue InVal = getValue(I.getOperand(1));
3193 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(2)), getCurSDLoc(),
3194 TLI.getVectorIdxTy(DAG.getDataLayout()));
3195 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurSDLoc(),
3196 TLI.getValueType(DAG.getDataLayout(), I.getType()),
3197 InVec, InVal, InIdx));
3198}
3199
3200void SelectionDAGBuilder::visitExtractElement(const User &I) {
3201 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3202 SDValue InVec = getValue(I.getOperand(0));
3203 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(1)), getCurSDLoc(),
3204 TLI.getVectorIdxTy(DAG.getDataLayout()));
3205 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(),
3206 TLI.getValueType(DAG.getDataLayout(), I.getType()),
3207 InVec, InIdx));
3208}
3209
3210void SelectionDAGBuilder::visitShuffleVector(const User &I) {
3211 SDValue Src1 = getValue(I.getOperand(0));
3212 SDValue Src2 = getValue(I.getOperand(1));
3213 SDLoc DL = getCurSDLoc();
3214
3215 SmallVector<int, 8> Mask;
3216 ShuffleVectorInst::getShuffleMask(cast<Constant>(I.getOperand(2)), Mask);
3217 unsigned MaskNumElts = Mask.size();
3218
3219 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3220 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
3221 EVT SrcVT = Src1.getValueType();
3222 unsigned SrcNumElts = SrcVT.getVectorNumElements();
3223
3224 if (SrcNumElts == MaskNumElts) {
3225 setValue(&I, DAG.getVectorShuffle(VT, DL, Src1, Src2, Mask));
3226 return;
3227 }
3228
3229 // Normalize the shuffle vector since mask and vector length don't match.
3230 if (SrcNumElts < MaskNumElts) {
3231 // Mask is longer than the source vectors. We can use concatenate vector to
3232 // make the mask and vectors lengths match.
3233
3234 if (MaskNumElts % SrcNumElts == 0) {
3235 // Mask length is a multiple of the source vector length.
3236 // Check if the shuffle is some kind of concatenation of the input
3237 // vectors.
3238 unsigned NumConcat = MaskNumElts / SrcNumElts;
3239 bool IsConcat = true;
3240 SmallVector<int, 8> ConcatSrcs(NumConcat, -1);
3241 for (unsigned i = 0; i != MaskNumElts; ++i) {
3242 int Idx = Mask[i];
3243 if (Idx < 0)
3244 continue;
3245 // Ensure the indices in each SrcVT sized piece are sequential and that
3246 // the same source is used for the whole piece.
3247 if ((Idx % SrcNumElts != (i % SrcNumElts)) ||
3248 (ConcatSrcs[i / SrcNumElts] >= 0 &&
3249 ConcatSrcs[i / SrcNumElts] != (int)(Idx / SrcNumElts))) {
3250 IsConcat = false;
3251 break;
3252 }
3253 // Remember which source this index came from.
3254 ConcatSrcs[i / SrcNumElts] = Idx / SrcNumElts;
3255 }
3256
3257 // The shuffle is concatenating multiple vectors together. Just emit
3258 // a CONCAT_VECTORS operation.
3259 if (IsConcat) {
3260 SmallVector<SDValue, 8> ConcatOps;
3261 for (auto Src : ConcatSrcs) {
3262 if (Src < 0)
3263 ConcatOps.push_back(DAG.getUNDEF(SrcVT));
3264 else if (Src == 0)
3265 ConcatOps.push_back(Src1);
3266 else
3267 ConcatOps.push_back(Src2);
3268 }
3269 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, ConcatOps));
3270 return;
3271 }
3272 }
3273
3274 unsigned PaddedMaskNumElts = alignTo(MaskNumElts, SrcNumElts);
3275 unsigned NumConcat = PaddedMaskNumElts / SrcNumElts;
3276 EVT PaddedVT = EVT::getVectorVT(*DAG.getContext(), VT.getScalarType(),
3277 PaddedMaskNumElts);
3278
3279 // Pad both vectors with undefs to make them the same length as the mask.
3280 SDValue UndefVal = DAG.getUNDEF(SrcVT);
3281
3282 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
3283 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
3284 MOps1[0] = Src1;
3285 MOps2[0] = Src2;
3286
3287 Src1 = Src1.isUndef()
3288 ? DAG.getUNDEF(PaddedVT)
3289 : DAG.getNode(ISD::CONCAT_VECTORS, DL, PaddedVT, MOps1);
3290 Src2 = Src2.isUndef()
3291 ? DAG.getUNDEF(PaddedVT)
3292 : DAG.getNode(ISD::CONCAT_VECTORS, DL, PaddedVT, MOps2);
3293
3294 // Readjust mask for new input vector length.
3295 SmallVector<int, 8> MappedOps(PaddedMaskNumElts, -1);
3296 for (unsigned i = 0; i != MaskNumElts; ++i) {
3297 int Idx = Mask[i];
3298 if (Idx >= (int)SrcNumElts)
3299 Idx -= SrcNumElts - PaddedMaskNumElts;
3300 MappedOps[i] = Idx;
3301 }
3302
3303 SDValue Result = DAG.getVectorShuffle(PaddedVT, DL, Src1, Src2, MappedOps);
3304
3305 // If the concatenated vector was padded, extract a subvector with the
3306 // correct number of elements.
3307 if (MaskNumElts != PaddedMaskNumElts)
3308 Result = DAG.getNode(
3309 ISD::EXTRACT_SUBVECTOR, DL, VT, Result,
3310 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
3311
3312 setValue(&I, Result);
3313 return;
3314 }
3315
3316 if (SrcNumElts > MaskNumElts) {
3317 // Analyze the access pattern of the vector to see if we can extract
3318 // two subvectors and do the shuffle.
3319 int StartIdx[2] = { -1, -1 }; // StartIdx to extract from
3320 bool CanExtract = true;
3321 for (int Idx : Mask) {
3322 unsigned Input = 0;
3323 if (Idx < 0)
3324 continue;
3325
3326 if (Idx >= (int)SrcNumElts) {
3327 Input = 1;
3328 Idx -= SrcNumElts;
3329 }
3330
3331 // If all the indices come from the same MaskNumElts sized portion of
3332 // the sources we can use extract. Also make sure the extract wouldn't
3333 // extract past the end of the source.
3334 int NewStartIdx = alignDown(Idx, MaskNumElts);
3335 if (NewStartIdx + MaskNumElts > SrcNumElts ||
3336 (StartIdx[Input] >= 0 && StartIdx[Input] != NewStartIdx))
3337 CanExtract = false;
3338 // Make sure we always update StartIdx as we use it to track if all
3339 // elements are undef.
3340 StartIdx[Input] = NewStartIdx;
3341 }
3342
3343 if (StartIdx[0] < 0 && StartIdx[1] < 0) {
3344 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
3345 return;
3346 }
3347 if (CanExtract) {
3348 // Extract appropriate subvector and generate a vector shuffle
3349 for (unsigned Input = 0; Input < 2; ++Input) {
3350 SDValue &Src = Input == 0 ? Src1 : Src2;
3351 if (StartIdx[Input] < 0)
3352 Src = DAG.getUNDEF(VT);
3353 else {
3354 Src = DAG.getNode(
3355 ISD::EXTRACT_SUBVECTOR, DL, VT, Src,
3356 DAG.getConstant(StartIdx[Input], DL,
3357 TLI.getVectorIdxTy(DAG.getDataLayout())));
3358 }
3359 }
3360
3361 // Calculate new mask.
3362 SmallVector<int, 8> MappedOps(Mask.begin(), Mask.end());
3363 for (int &Idx : MappedOps) {
3364 if (Idx >= (int)SrcNumElts)
3365 Idx -= SrcNumElts + StartIdx[1] - MaskNumElts;
3366 else if (Idx >= 0)
3367 Idx -= StartIdx[0];
3368 }
3369
3370 setValue(&I, DAG.getVectorShuffle(VT, DL, Src1, Src2, MappedOps));
3371 return;
3372 }
3373 }
3374
3375 // We can't use either concat vectors or extract subvectors so fall back to
3376 // replacing the shuffle with extract and build vector.
3377 // to insert and build vector.
3378 EVT EltVT = VT.getVectorElementType();
3379 EVT IdxVT = TLI.getVectorIdxTy(DAG.getDataLayout());
3380 SmallVector<SDValue,8> Ops;
3381 for (int Idx : Mask) {
3382 SDValue Res;
3383
3384 if (Idx < 0) {
3385 Res = DAG.getUNDEF(EltVT);
3386 } else {
3387 SDValue &Src = Idx < (int)SrcNumElts ? Src1 : Src2;
3388 if (Idx >= (int)SrcNumElts) Idx -= SrcNumElts;
3389
3390 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
3391 EltVT, Src, DAG.getConstant(Idx, DL, IdxVT));
3392 }
3393
3394 Ops.push_back(Res);
3395 }
3396
3397 setValue(&I, DAG.getBuildVector(VT, DL, Ops));
3398}
3399
3400void SelectionDAGBuilder::visitInsertValue(const User &I) {
3401 ArrayRef<unsigned> Indices;
3402 if (const InsertValueInst *IV = dyn_cast<InsertValueInst>(&I))
3403 Indices = IV->getIndices();
3404 else
3405 Indices = cast<ConstantExpr>(&I)->getIndices();
3406
3407 const Value *Op0 = I.getOperand(0);
3408 const Value *Op1 = I.getOperand(1);
3409 Type *AggTy = I.getType();
3410 Type *ValTy = Op1->getType();
3411 bool IntoUndef = isa<UndefValue>(Op0);
3412 bool FromUndef = isa<UndefValue>(Op1);
3413
3414 unsigned LinearIndex = ComputeLinearIndex(AggTy, Indices);
3415
3416 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3417 SmallVector<EVT, 4> AggValueVTs;
3418 ComputeValueVTs(TLI, DAG.getDataLayout(), AggTy, AggValueVTs);
3419 SmallVector<EVT, 4> ValValueVTs;
3420 ComputeValueVTs(TLI, DAG.getDataLayout(), ValTy, ValValueVTs);
3421
3422 unsigned NumAggValues = AggValueVTs.size();
3423 unsigned NumValValues = ValValueVTs.size();
3424 SmallVector<SDValue, 4> Values(NumAggValues);
3425
3426 // Ignore an insertvalue that produces an empty object
3427 if (!NumAggValues) {
3428 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
3429 return;
3430 }
3431
3432 SDValue Agg = getValue(Op0);
3433 unsigned i = 0;
3434 // Copy the beginning value(s) from the original aggregate.
3435 for (; i != LinearIndex; ++i)
3436 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3437 SDValue(Agg.getNode(), Agg.getResNo() + i);
3438 // Copy values from the inserted value(s).
3439 if (NumValValues) {
3440 SDValue Val = getValue(Op1);
3441 for (; i != LinearIndex + NumValValues; ++i)
3442 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3443 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
3444 }
3445 // Copy remaining value(s) from the original aggregate.
3446 for (; i != NumAggValues; ++i)
3447 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3448 SDValue(Agg.getNode(), Agg.getResNo() + i);
3449
3450 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
3451 DAG.getVTList(AggValueVTs), Values));
3452}
3453
3454void SelectionDAGBuilder::visitExtractValue(const User &I) {
3455 ArrayRef<unsigned> Indices;
3456 if (const ExtractValueInst *EV = dyn_cast<ExtractValueInst>(&I))
3457 Indices = EV->getIndices();
3458 else
3459 Indices = cast<ConstantExpr>(&I)->getIndices();
3460
3461 const Value *Op0 = I.getOperand(0);
3462 Type *AggTy = Op0->getType();
3463 Type *ValTy = I.getType();
3464 bool OutOfUndef = isa<UndefValue>(Op0);
3465
3466 unsigned LinearIndex = ComputeLinearIndex(AggTy, Indices);
3467
3468 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3469 SmallVector<EVT, 4> ValValueVTs;
3470 ComputeValueVTs(TLI, DAG.getDataLayout(), ValTy, ValValueVTs);
3471
3472 unsigned NumValValues = ValValueVTs.size();
3473
3474 // Ignore a extractvalue that produces an empty object
3475 if (!NumValValues) {
3476 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
3477 return;
3478 }
3479
3480 SmallVector<SDValue, 4> Values(NumValValues);
3481
3482 SDValue Agg = getValue(Op0);
3483 // Copy out the selected value(s).
3484 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
3485 Values[i - LinearIndex] =
3486 OutOfUndef ?
3487 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
3488 SDValue(Agg.getNode(), Agg.getResNo() + i);
3489
3490 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
3491 DAG.getVTList(ValValueVTs), Values));
3492}
3493
3494void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
3495 Value *Op0 = I.getOperand(0);
3496 // Note that the pointer operand may be a vector of pointers. Take the scalar
3497 // element which holds a pointer.
3498 unsigned AS = Op0->getType()->getScalarType()->getPointerAddressSpace();
3499 SDValue N = getValue(Op0);
3500 SDLoc dl = getCurSDLoc();
3501
3502 // Normalize Vector GEP - all scalar operands should be converted to the
3503 // splat vector.
3504 unsigned VectorWidth = I.getType()->isVectorTy() ?
3505 cast<VectorType>(I.getType())->getVectorNumElements() : 0;
3506
3507 if (VectorWidth && !N.getValueType().isVector()) {
3508 LLVMContext &Context = *DAG.getContext();
3509 EVT VT = EVT::getVectorVT(Context, N.getValueType(), VectorWidth);
3510 N = DAG.getSplatBuildVector(VT, dl, N);
3511 }
3512
3513 for (gep_type_iterator GTI = gep_type_begin(&I), E = gep_type_end(&I);
3514 GTI != E; ++GTI) {
3515 const Value *Idx = GTI.getOperand();
3516 if (StructType *StTy = GTI.getStructTypeOrNull()) {
3517 unsigned Field = cast<Constant>(Idx)->getUniqueInteger().getZExtValue();
3518 if (Field) {
3519 // N = N + Offset
3520 uint64_t Offset = DL->getStructLayout(StTy)->getElementOffset(Field);
3521
3522 // In an inbounds GEP with an offset that is nonnegative even when
3523 // interpreted as signed, assume there is no unsigned overflow.
3524 SDNodeFlags Flags;
3525 if (int64_t(Offset) >= 0 && cast<GEPOperator>(I).isInBounds())
3526 Flags.setNoUnsignedWrap(true);
3527
3528 N = DAG.getNode(ISD::ADD, dl, N.getValueType(), N,
3529 DAG.getConstant(Offset, dl, N.getValueType()), Flags);
3530 }
3531 } else {
3532 unsigned IdxSize = DAG.getDataLayout().getIndexSizeInBits(AS);
3533 MVT IdxTy = MVT::getIntegerVT(IdxSize);
3534 APInt ElementSize(IdxSize, DL->getTypeAllocSize(GTI.getIndexedType()));
3535
3536 // If this is a scalar constant or a splat vector of constants,
3537 // handle it quickly.
3538 const auto *CI = dyn_cast<ConstantInt>(Idx);
3539 if (!CI && isa<ConstantDataVector>(Idx) &&
3540 cast<ConstantDataVector>(Idx)->getSplatValue())
3541 CI = cast<ConstantInt>(cast<ConstantDataVector>(Idx)->getSplatValue());
3542
3543 if (CI) {
3544 if (CI->isZero())
3545 continue;
3546 APInt Offs = ElementSize * CI->getValue().sextOrTrunc(IdxSize);
3547 LLVMContext &Context = *DAG.getContext();
3548 SDValue OffsVal = VectorWidth ?
3549 DAG.getConstant(Offs, dl, EVT::getVectorVT(Context, IdxTy, VectorWidth)) :
3550 DAG.getConstant(Offs, dl, IdxTy);
3551
3552 // In an inbouds GEP with an offset that is nonnegative even when
3553 // interpreted as signed, assume there is no unsigned overflow.
3554 SDNodeFlags Flags;
3555 if (Offs.isNonNegative() && cast<GEPOperator>(I).isInBounds())
3556 Flags.setNoUnsignedWrap(true);
3557
3558 N = DAG.getNode(ISD::ADD, dl, N.getValueType(), N, OffsVal, Flags);
3559 continue;
3560 }
3561
3562 // N = N + Idx * ElementSize;
3563 SDValue IdxN = getValue(Idx);
3564
3565 if (!IdxN.getValueType().isVector() && VectorWidth) {
3566 EVT VT = EVT::getVectorVT(*Context, IdxN.getValueType(), VectorWidth);
3567 IdxN = DAG.getSplatBuildVector(VT, dl, IdxN);
3568 }
3569
3570 // If the index is smaller or larger than intptr_t, truncate or extend
3571 // it.
3572 IdxN = DAG.getSExtOrTrunc(IdxN, dl, N.getValueType());
3573
3574 // If this is a multiply by a power of two, turn it into a shl
3575 // immediately. This is a very common case.
3576 if (ElementSize != 1) {
3577 if (ElementSize.isPowerOf2()) {
3578 unsigned Amt = ElementSize.logBase2();
3579 IdxN = DAG.getNode(ISD::SHL, dl,
3580 N.getValueType(), IdxN,
3581 DAG.getConstant(Amt, dl, IdxN.getValueType()));
3582 } else {
3583 SDValue Scale = DAG.getConstant(ElementSize, dl, IdxN.getValueType());
3584 IdxN = DAG.getNode(ISD::MUL, dl,
3585 N.getValueType(), IdxN, Scale);
3586 }
3587 }
3588
3589 N = DAG.getNode(ISD::ADD, dl,
3590 N.getValueType(), N, IdxN);
3591 }
3592 }
3593
3594 setValue(&I, N);
3595}
3596
3597void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
3598 // If this is a fixed sized alloca in the entry block of the function,
3599 // allocate it statically on the stack.
3600 if (FuncInfo.StaticAllocaMap.count(&I))
3601 return; // getValue will auto-populate this.
3602
3603 SDLoc dl = getCurSDLoc();
3604 Type *Ty = I.getAllocatedType();
3605 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3606 auto &DL = DAG.getDataLayout();
3607 uint64_t TySize = DL.getTypeAllocSize(Ty);
3608 unsigned Align =
3609 std::max((unsigned)DL.getPrefTypeAlignment(Ty), I.getAlignment());
3610
3611 SDValue AllocSize = getValue(I.getArraySize());
3612
3613 EVT IntPtr = TLI.getPointerTy(DAG.getDataLayout(), DL.getAllocaAddrSpace());
3614 if (AllocSize.getValueType() != IntPtr)
3615 AllocSize = DAG.getZExtOrTrunc(AllocSize, dl, IntPtr);
3616
3617 AllocSize = DAG.getNode(ISD::MUL, dl, IntPtr,
3618 AllocSize,
3619 DAG.getConstant(TySize, dl, IntPtr));
3620
3621 // Handle alignment. If the requested alignment is less than or equal to
3622 // the stack alignment, ignore it. If the size is greater than or equal to
3623 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
3624 unsigned StackAlign =
3625 DAG.getSubtarget().getFrameLowering()->getStackAlignment();
3626 if (Align <= StackAlign)
3627 Align = 0;
3628
3629 // Round the size of the allocation up to the stack alignment size
3630 // by add SA-1 to the size. This doesn't overflow because we're computing
3631 // an address inside an alloca.
3632 SDNodeFlags Flags;
3633 Flags.setNoUnsignedWrap(true);
3634 AllocSize = DAG.getNode(ISD::ADD, dl, AllocSize.getValueType(), AllocSize,
3635 DAG.getConstant(StackAlign - 1, dl, IntPtr), Flags);
3636
3637 // Mask out the low bits for alignment purposes.
3638 AllocSize =
3639 DAG.getNode(ISD::AND, dl, AllocSize.getValueType(), AllocSize,
3640 DAG.getConstant(~(uint64_t)(StackAlign - 1), dl, IntPtr));
3641
3642 SDValue Ops[] = {getRoot(), AllocSize, DAG.getConstant(Align, dl, IntPtr)};
3643 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
3644 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, dl, VTs, Ops);
3645 setValue(&I, DSA);
3646 DAG.setRoot(DSA.getValue(1));
3647
3648 assert(FuncInfo.MF->getFrameInfo().hasVarSizedObjects())((FuncInfo.MF->getFrameInfo().hasVarSizedObjects()) ? static_cast
<void> (0) : __assert_fail ("FuncInfo.MF->getFrameInfo().hasVarSizedObjects()"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 3648, __PRETTY_FUNCTION__))
;
3649}
3650
3651void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
3652 if (I.isAtomic())
3653 return visitAtomicLoad(I);
3654
3655 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3656 const Value *SV = I.getOperand(0);
3657 if (TLI.supportSwiftError()) {
3658 // Swifterror values can come from either a function parameter with
3659 // swifterror attribute or an alloca with swifterror attribute.
3660 if (const Argument *Arg = dyn_cast<Argument>(SV)) {
3661 if (Arg->hasSwiftErrorAttr())
3662 return visitLoadFromSwiftError(I);
3663 }
3664
3665 if (const AllocaInst *Alloca = dyn_cast<AllocaInst>(SV)) {
3666 if (Alloca->isSwiftError())
3667 return visitLoadFromSwiftError(I);
3668 }
3669 }
3670
3671 SDValue Ptr = getValue(SV);
3672
3673 Type *Ty = I.getType();
3674
3675 bool isVolatile = I.isVolatile();
3676 bool isNonTemporal = I.getMetadata(LLVMContext::MD_nontemporal) != nullptr;
3677 bool isInvariant = I.getMetadata(LLVMContext::MD_invariant_load) != nullptr;
3678 bool isDereferenceable = isDereferenceablePointer(SV, DAG.getDataLayout());
3679 unsigned Alignment = I.getAlignment();
3680
3681 AAMDNodes AAInfo;
3682 I.getAAMetadata(AAInfo);
3683 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3684
3685 SmallVector<EVT, 4> ValueVTs;
3686 SmallVector<uint64_t, 4> Offsets;
3687 ComputeValueVTs(TLI, DAG.getDataLayout(), Ty, ValueVTs, &Offsets);
3688 unsigned NumValues = ValueVTs.size();
3689 if (NumValues == 0)
3690 return;
3691
3692 SDValue Root;
3693 bool ConstantMemory = false;
3694 if (isVolatile || NumValues > MaxParallelChains)
3695 // Serialize volatile loads with other side effects.
3696 Root = getRoot();
3697 else if (AA &&
3698 AA->pointsToConstantMemory(MemoryLocation(
3699 SV,
3700 LocationSize::precise(DAG.getDataLayout().getTypeStoreSize(Ty)),
3701 AAInfo))) {
3702 // Do not serialize (non-volatile) loads of constant memory with anything.
3703 Root = DAG.getEntryNode();
3704 ConstantMemory = true;
3705 } else {
3706 // Do not serialize non-volatile loads against each other.
3707 Root = DAG.getRoot();
3708 }
3709
3710 SDLoc dl = getCurSDLoc();
3711
3712 if (isVolatile)
3713 Root = TLI.prepareVolatileOrAtomicLoad(Root, dl, DAG);
3714
3715 // An aggregate load cannot wrap around the address space, so offsets to its
3716 // parts don't wrap either.
3717 SDNodeFlags Flags;
3718 Flags.setNoUnsignedWrap(true);
3719
3720 SmallVector<SDValue, 4> Values(NumValues);
3721 SmallVector<SDValue, 4> Chains(std::min(MaxParallelChains, NumValues));
3722 EVT PtrVT = Ptr.getValueType();
3723 unsigned ChainI = 0;
3724 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3725 // Serializing loads here may result in excessive register pressure, and
3726 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling
3727 // could recover a bit by hoisting nodes upward in the chain by recognizing
3728 // they are side-effect free or do not alias. The optimizer should really
3729 // avoid this case by converting large object/array copies to llvm.memcpy
3730 // (MaxParallelChains should always remain as failsafe).
3731 if (ChainI == MaxParallelChains) {
3732 assert(PendingLoads.empty() && "PendingLoads must be serialized first")((PendingLoads.empty() && "PendingLoads must be serialized first"
) ? static_cast<void> (0) : __assert_fail ("PendingLoads.empty() && \"PendingLoads must be serialized first\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 3732, __PRETTY_FUNCTION__))
;
3733 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3734 makeArrayRef(Chains.data(), ChainI));
3735 Root = Chain;
3736 ChainI = 0;
3737 }
3738 SDValue A = DAG.getNode(ISD::ADD, dl,
3739 PtrVT, Ptr,
3740 DAG.getConstant(Offsets[i], dl, PtrVT),
3741 Flags);
3742 auto MMOFlags = MachineMemOperand::MONone;
3743 if (isVolatile)
3744 MMOFlags |= MachineMemOperand::MOVolatile;
3745 if (isNonTemporal)
3746 MMOFlags |= MachineMemOperand::MONonTemporal;
3747 if (isInvariant)
3748 MMOFlags |= MachineMemOperand::MOInvariant;
3749 if (isDereferenceable)
3750 MMOFlags |= MachineMemOperand::MODereferenceable;
3751 MMOFlags |= TLI.getMMOFlags(I);
3752
3753 SDValue L = DAG.getLoad(ValueVTs[i], dl, Root, A,
3754 MachinePointerInfo(SV, Offsets[i]), Alignment,
3755 MMOFlags, AAInfo, Ranges);
3756
3757 Values[i] = L;
3758 Chains[ChainI] = L.getValue(1);
3759 }
3760
3761 if (!ConstantMemory) {
3762 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3763 makeArrayRef(Chains.data(), ChainI));
3764 if (isVolatile)
3765 DAG.setRoot(Chain);
3766 else
3767 PendingLoads.push_back(Chain);
3768 }
3769
3770 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, dl,
3771 DAG.getVTList(ValueVTs), Values));
3772}
3773
3774void SelectionDAGBuilder::visitStoreToSwiftError(const StoreInst &I) {
3775 assert(DAG.getTargetLoweringInfo().supportSwiftError() &&((DAG.getTargetLoweringInfo().supportSwiftError() && "call visitStoreToSwiftError when backend supports swifterror"
) ? static_cast<void> (0) : __assert_fail ("DAG.getTargetLoweringInfo().supportSwiftError() && \"call visitStoreToSwiftError when backend supports swifterror\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 3776, __PRETTY_FUNCTION__))
3776 "call visitStoreToSwiftError when backend supports swifterror")((DAG.getTargetLoweringInfo().supportSwiftError() && "call visitStoreToSwiftError when backend supports swifterror"
) ? static_cast<void> (0) : __assert_fail ("DAG.getTargetLoweringInfo().supportSwiftError() && \"call visitStoreToSwiftError when backend supports swifterror\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 3776, __PRETTY_FUNCTION__))
;
3777
3778 SmallVector<EVT, 4> ValueVTs;
3779 SmallVector<uint64_t, 4> Offsets;
3780 const Value *SrcV = I.getOperand(0);
3781 ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(),
3782 SrcV->getType(), ValueVTs, &Offsets);
3783 assert(ValueVTs.size() == 1 && Offsets[0] == 0 &&((ValueVTs.size() == 1 && Offsets[0] == 0 && "expect a single EVT for swifterror"
) ? static_cast<void> (0) : __assert_fail ("ValueVTs.size() == 1 && Offsets[0] == 0 && \"expect a single EVT for swifterror\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 3784, __PRETTY_FUNCTION__))
3784 "expect a single EVT for swifterror")((ValueVTs.size() == 1 && Offsets[0] == 0 && "expect a single EVT for swifterror"
) ? static_cast<void> (0) : __assert_fail ("ValueVTs.size() == 1 && Offsets[0] == 0 && \"expect a single EVT for swifterror\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 3784, __PRETTY_FUNCTION__))
;
3785
3786 SDValue Src = getValue(SrcV);
3787 // Create a virtual register, then update the virtual register.
3788 unsigned VReg; bool CreatedVReg;
3789 std::tie(VReg, CreatedVReg) = FuncInfo.getOrCreateSwiftErrorVRegDefAt(&I);
3790 // Chain, DL, Reg, N or Chain, DL, Reg, N, Glue
3791 // Chain can be getRoot or getControlRoot.
3792 SDValue CopyNode = DAG.getCopyToReg(getRoot(), getCurSDLoc(), VReg,
3793 SDValue(Src.getNode(), Src.getResNo()));
3794 DAG.setRoot(CopyNode);
3795 if (CreatedVReg)
3796 FuncInfo.setCurrentSwiftErrorVReg(FuncInfo.MBB, I.getOperand(1), VReg);
3797}
3798
3799void SelectionDAGBuilder::visitLoadFromSwiftError(const LoadInst &I) {
3800 assert(DAG.getTargetLoweringInfo().supportSwiftError() &&((DAG.getTargetLoweringInfo().supportSwiftError() && "call visitLoadFromSwiftError when backend supports swifterror"
) ? static_cast<void> (0) : __assert_fail ("DAG.getTargetLoweringInfo().supportSwiftError() && \"call visitLoadFromSwiftError when backend supports swifterror\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 3801, __PRETTY_FUNCTION__))
3801 "call visitLoadFromSwiftError when backend supports swifterror")((DAG.getTargetLoweringInfo().supportSwiftError() && "call visitLoadFromSwiftError when backend supports swifterror"
) ? static_cast<void> (0) : __assert_fail ("DAG.getTargetLoweringInfo().supportSwiftError() && \"call visitLoadFromSwiftError when backend supports swifterror\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 3801, __PRETTY_FUNCTION__))
;
3802
3803 assert(!I.isVolatile() &&((!I.isVolatile() && I.getMetadata(LLVMContext::MD_nontemporal
) == nullptr && I.getMetadata(LLVMContext::MD_invariant_load
) == nullptr && "Support volatile, non temporal, invariant for load_from_swift_error"
) ? static_cast<void> (0) : __assert_fail ("!I.isVolatile() && I.getMetadata(LLVMContext::MD_nontemporal) == nullptr && I.getMetadata(LLVMContext::MD_invariant_load) == nullptr && \"Support volatile, non temporal, invariant for load_from_swift_error\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 3806, __PRETTY_FUNCTION__))
3804 I.getMetadata(LLVMContext::MD_nontemporal) == nullptr &&((!I.isVolatile() && I.getMetadata(LLVMContext::MD_nontemporal
) == nullptr && I.getMetadata(LLVMContext::MD_invariant_load
) == nullptr && "Support volatile, non temporal, invariant for load_from_swift_error"
) ? static_cast<void> (0) : __assert_fail ("!I.isVolatile() && I.getMetadata(LLVMContext::MD_nontemporal) == nullptr && I.getMetadata(LLVMContext::MD_invariant_load) == nullptr && \"Support volatile, non temporal, invariant for load_from_swift_error\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 3806, __PRETTY_FUNCTION__))
3805 I.getMetadata(LLVMContext::MD_invariant_load) == nullptr &&((!I.isVolatile() && I.getMetadata(LLVMContext::MD_nontemporal
) == nullptr && I.getMetadata(LLVMContext::MD_invariant_load
) == nullptr && "Support volatile, non temporal, invariant for load_from_swift_error"
) ? static_cast<void> (0) : __assert_fail ("!I.isVolatile() && I.getMetadata(LLVMContext::MD_nontemporal) == nullptr && I.getMetadata(LLVMContext::MD_invariant_load) == nullptr && \"Support volatile, non temporal, invariant for load_from_swift_error\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 3806, __PRETTY_FUNCTION__))
3806 "Support volatile, non temporal, invariant for load_from_swift_error")((!I.isVolatile() && I.getMetadata(LLVMContext::MD_nontemporal
) == nullptr && I.getMetadata(LLVMContext::MD_invariant_load
) == nullptr && "Support volatile, non temporal, invariant for load_from_swift_error"
) ? static_cast<void> (0) : __assert_fail ("!I.isVolatile() && I.getMetadata(LLVMContext::MD_nontemporal) == nullptr && I.getMetadata(LLVMContext::MD_invariant_load) == nullptr && \"Support volatile, non temporal, invariant for load_from_swift_error\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 3806, __PRETTY_FUNCTION__))
;
3807
3808 const Value *SV = I.getOperand(0);
3809 Type *Ty = I.getType();
3810 AAMDNodes AAInfo;
3811 I.getAAMetadata(AAInfo);
3812 assert((((!AA || !AA->pointsToConstantMemory(MemoryLocation( SV, LocationSize
::precise(DAG.getDataLayout().getTypeStoreSize(Ty)), AAInfo))
) && "load_from_swift_error should not be constant memory"
) ? static_cast<void> (0) : __assert_fail ("(!AA || !AA->pointsToConstantMemory(MemoryLocation( SV, LocationSize::precise(DAG.getDataLayout().getTypeStoreSize(Ty)), AAInfo))) && \"load_from_swift_error should not be constant memory\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 3817, __PRETTY_FUNCTION__))
3813 (!AA ||(((!AA || !AA->pointsToConstantMemory(MemoryLocation( SV, LocationSize
::precise(DAG.getDataLayout().getTypeStoreSize(Ty)), AAInfo))
) && "load_from_swift_error should not be constant memory"
) ? static_cast<void> (0) : __assert_fail ("(!AA || !AA->pointsToConstantMemory(MemoryLocation( SV, LocationSize::precise(DAG.getDataLayout().getTypeStoreSize(Ty)), AAInfo))) && \"load_from_swift_error should not be constant memory\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 3817, __PRETTY_FUNCTION__))
3814 !AA->pointsToConstantMemory(MemoryLocation((((!AA || !AA->pointsToConstantMemory(MemoryLocation( SV, LocationSize
::precise(DAG.getDataLayout().getTypeStoreSize(Ty)), AAInfo))
) && "load_from_swift_error should not be constant memory"
) ? static_cast<void> (0) : __assert_fail ("(!AA || !AA->pointsToConstantMemory(MemoryLocation( SV, LocationSize::precise(DAG.getDataLayout().getTypeStoreSize(Ty)), AAInfo))) && \"load_from_swift_error should not be constant memory\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 3817, __PRETTY_FUNCTION__))
3815 SV, LocationSize::precise(DAG.getDataLayout().getTypeStoreSize(Ty)),(((!AA || !AA->pointsToConstantMemory(MemoryLocation( SV, LocationSize
::precise(DAG.getDataLayout().getTypeStoreSize(Ty)), AAInfo))
) && "load_from_swift_error should not be constant memory"
) ? static_cast<void> (0) : __assert_fail ("(!AA || !AA->pointsToConstantMemory(MemoryLocation( SV, LocationSize::precise(DAG.getDataLayout().getTypeStoreSize(Ty)), AAInfo))) && \"load_from_swift_error should not be constant memory\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 3817, __PRETTY_FUNCTION__))
3816 AAInfo))) &&(((!AA || !AA->pointsToConstantMemory(MemoryLocation( SV, LocationSize
::precise(DAG.getDataLayout().getTypeStoreSize(Ty)), AAInfo))
) && "load_from_swift_error should not be constant memory"
) ? static_cast<void> (0) : __assert_fail ("(!AA || !AA->pointsToConstantMemory(MemoryLocation( SV, LocationSize::precise(DAG.getDataLayout().getTypeStoreSize(Ty)), AAInfo))) && \"load_from_swift_error should not be constant memory\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 3817, __PRETTY_FUNCTION__))
3817 "load_from_swift_error should not be constant memory")(((!AA || !AA->pointsToConstantMemory(MemoryLocation( SV, LocationSize
::precise(DAG.getDataLayout().getTypeStoreSize(Ty)), AAInfo))
) && "load_from_swift_error should not be constant memory"
) ? static_cast<void> (0) : __assert_fail ("(!AA || !AA->pointsToConstantMemory(MemoryLocation( SV, LocationSize::precise(DAG.getDataLayout().getTypeStoreSize(Ty)), AAInfo))) && \"load_from_swift_error should not be constant memory\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 3817, __PRETTY_FUNCTION__))
;
3818
3819 SmallVector<EVT, 4> ValueVTs;
3820 SmallVector<uint64_t, 4> Offsets;
3821 ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(), Ty,
3822 ValueVTs, &Offsets);
3823 assert(ValueVTs.size() == 1 && Offsets[0] == 0 &&((ValueVTs.size() == 1 && Offsets[0] == 0 && "expect a single EVT for swifterror"
) ? static_cast<void> (0) : __assert_fail ("ValueVTs.size() == 1 && Offsets[0] == 0 && \"expect a single EVT for swifterror\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 3824, __PRETTY_FUNCTION__))
3824 "expect a single EVT for swifterror")((ValueVTs.size() == 1 && Offsets[0] == 0 && "expect a single EVT for swifterror"
) ? static_cast<void> (0) : __assert_fail ("ValueVTs.size() == 1 && Offsets[0] == 0 && \"expect a single EVT for swifterror\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 3824, __PRETTY_FUNCTION__))
;
3825
3826 // Chain, DL, Reg, VT, Glue or Chain, DL, Reg, VT
3827 SDValue L = DAG.getCopyFromReg(
3828 getRoot(), getCurSDLoc(),
3829 FuncInfo.getOrCreateSwiftErrorVRegUseAt(&I, FuncInfo.MBB, SV).first,
3830 ValueVTs[0]);
3831
3832 setValue(&I, L);
3833}
3834
3835void SelectionDAGBuilder::visitStore(const StoreInst &I) {
3836 if (I.isAtomic())
3837 return visitAtomicStore(I);
3838
3839 const Value *SrcV = I.getOperand(0);
3840 const Value *PtrV = I.getOperand(1);
3841
3842 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3843 if (TLI.supportSwiftError()) {
3844 // Swifterror values can come from either a function parameter with
3845 // swifterror attribute or an alloca with swifterror attribute.
3846 if (const Argument *Arg = dyn_cast<Argument>(PtrV)) {
3847 if (Arg->hasSwiftErrorAttr())
3848 return visitStoreToSwiftError(I);
3849 }
3850
3851 if (const AllocaInst *Alloca = dyn_cast<AllocaInst>(PtrV)) {
3852 if (Alloca->isSwiftError())
3853 return visitStoreToSwiftError(I);
3854 }
3855 }
3856
3857 SmallVector<EVT, 4> ValueVTs;
3858 SmallVector<uint64_t, 4> Offsets;
3859 ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(),
3860 SrcV->getType(), ValueVTs, &Offsets);
3861 unsigned NumValues = ValueVTs.size();
3862 if (NumValues == 0)
3863 return;
3864
3865 // Get the lowered operands. Note that we do this after
3866 // checking if NumResults is zero, because with zero results
3867 // the operands won't have values in the map.
3868 SDValue Src = getValue(SrcV);
3869 SDValue Ptr = getValue(PtrV);
3870
3871 SDValue Root = getRoot();
3872 SmallVector<SDValue, 4> Chains(std::min(MaxParallelChains, NumValues));
3873 SDLoc dl = getCurSDLoc();
3874 EVT PtrVT = Ptr.getValueType();
3875 unsigned Alignment = I.getAlignment();
3876 AAMDNodes AAInfo;
3877 I.getAAMetadata(AAInfo);
3878
3879 auto MMOFlags = MachineMemOperand::MONone;
3880 if (I.isVolatile())
3881 MMOFlags |= MachineMemOperand::MOVolatile;
3882 if (I.getMetadata(LLVMContext::MD_nontemporal) != nullptr)
3883 MMOFlags |= MachineMemOperand::MONonTemporal;
3884 MMOFlags |= TLI.getMMOFlags(I);
3885
3886 // An aggregate load cannot wrap around the address space, so offsets to its
3887 // parts don't wrap either.
3888 SDNodeFlags Flags;
3889 Flags.setNoUnsignedWrap(true);
3890
3891 unsigned ChainI = 0;
3892 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3893 // See visitLoad comments.
3894 if (ChainI == MaxParallelChains) {
3895 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3896 makeArrayRef(Chains.data(), ChainI));
3897 Root = Chain;
3898 ChainI = 0;
3899 }
3900 SDValue Add = DAG.getNode(ISD::ADD, dl, PtrVT, Ptr,
3901 DAG.getConstant(Offsets[i], dl, PtrVT), Flags);
3902 SDValue St = DAG.getStore(
3903 Root, dl, SDValue(Src.getNode(), Src.getResNo() + i), Add,
3904 MachinePointerInfo(PtrV, Offsets[i]), Alignment, MMOFlags, AAInfo);
3905 Chains[ChainI] = St;
3906 }
3907
3908 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3909 makeArrayRef(Chains.data(), ChainI));
3910 DAG.setRoot(StoreNode);
3911}
3912
3913void SelectionDAGBuilder::visitMaskedStore(const CallInst &I,
3914 bool IsCompressing) {
3915 SDLoc sdl = getCurSDLoc();
3916
3917 auto getMaskedStoreOps = [&](Value* &Ptr, Value* &Mask, Value* &Src0,
3918 unsigned& Alignment) {
3919 // llvm.masked.store.*(Src0, Ptr, alignment, Mask)
3920 Src0 = I.getArgOperand(0);
3921 Ptr = I.getArgOperand(1);
3922 Alignment = cast<ConstantInt>(I.getArgOperand(2))->getZExtValue();
3923 Mask = I.getArgOperand(3);
3924 };
3925 auto getCompressingStoreOps = [&](Value* &Ptr, Value* &Mask, Value* &Src0,
3926 unsigned& Alignment) {
3927 // llvm.masked.compressstore.*(Src0, Ptr, Mask)
3928 Src0 = I.getArgOperand(0);
3929 Ptr = I.getArgOperand(1);
3930 Mask = I.getArgOperand(2);
3931 Alignment = 0;
3932 };
3933
3934 Value *PtrOperand, *MaskOperand, *Src0Operand;
3935 unsigned Alignment;
3936 if (IsCompressing)
3937 getCompressingStoreOps(PtrOperand, MaskOperand, Src0Operand, Alignment);
3938 else
3939 getMaskedStoreOps(PtrOperand, MaskOperand, Src0Operand, Alignment);
3940
3941 SDValue Ptr = getValue(PtrOperand);
3942 SDValue Src0 = getValue(Src0Operand);
3943 SDValue Mask = getValue(MaskOperand);
3944
3945 EVT VT = Src0.getValueType();
3946 if (!Alignment)
3947 Alignment = DAG.getEVTAlignment(VT);
3948
3949 AAMDNodes AAInfo;
3950 I.getAAMetadata(AAInfo);
3951
3952 MachineMemOperand *MMO =
3953 DAG.getMachineFunction().
3954 getMachineMemOperand(MachinePointerInfo(PtrOperand),
3955 MachineMemOperand::MOStore, VT.getStoreSize(),
3956 Alignment, AAInfo);
3957 SDValue StoreNode = DAG.getMaskedStore(getRoot(), sdl, Src0, Ptr, Mask, VT,
3958 MMO, false /* Truncating */,
3959 IsCompressing);
3960 DAG.setRoot(StoreNode);
3961 setValue(&I, StoreNode);
3962}
3963
3964// Get a uniform base for the Gather/Scatter intrinsic.
3965// The first argument of the Gather/Scatter intrinsic is a vector of pointers.
3966// We try to represent it as a base pointer + vector of indices.
3967// Usually, the vector of pointers comes from a 'getelementptr' instruction.
3968// The first operand of the GEP may be a single pointer or a vector of pointers
3969// Example:
3970// %gep.ptr = getelementptr i32, <8 x i32*> %vptr, <8 x i32> %ind
3971// or
3972// %gep.ptr = getelementptr i32, i32* %ptr, <8 x i32> %ind
3973// %res = call <8 x i32> @llvm.masked.gather.v8i32(<8 x i32*> %gep.ptr, ..
3974//
3975// When the first GEP operand is a single pointer - it is the uniform base we
3976// are looking for. If first operand of the GEP is a splat vector - we
3977// extract the splat value and use it as a uniform base.
3978// In all other cases the function returns 'false'.
3979static bool getUniformBase(const Value* &Ptr, SDValue& Base, SDValue& Index,
3980 SDValue &Scale, SelectionDAGBuilder* SDB) {
3981 SelectionDAG& DAG = SDB->DAG;
3982 LLVMContext &Context = *DAG.getContext();
3983
3984 assert(Ptr->getType()->isVectorTy() && "Uexpected pointer type")((Ptr->getType()->isVectorTy() && "Uexpected pointer type"
) ? static_cast<void> (0) : __assert_fail ("Ptr->getType()->isVectorTy() && \"Uexpected pointer type\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 3984, __PRETTY_FUNCTION__))
;
3985 const GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(Ptr);
3986 if (!GEP)
3987 return false;
3988
3989 const Value *GEPPtr = GEP->getPointerOperand();
3990 if (!GEPPtr->getType()->isVectorTy())
3991 Ptr = GEPPtr;
3992 else if (!(Ptr = getSplatValue(GEPPtr)))
3993 return false;
3994
3995 unsigned FinalIndex = GEP->getNumOperands() - 1;
3996 Value *IndexVal = GEP->getOperand(FinalIndex);
3997
3998 // Ensure all the other indices are 0.
3999 for (unsigned i = 1; i < FinalIndex; ++i) {
4000 auto *C = dyn_cast<ConstantInt>(GEP->getOperand(i));
4001 if (!C || !C->isZero())
4002 return false;
4003 }
4004
4005 // The operands of the GEP may be defined in another basic block.
4006 // In this case we'll not find nodes for the operands.
4007 if (!SDB->findValue(Ptr) || !SDB->findValue(IndexVal))
4008 return false;
4009
4010 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4011 const DataLayout &DL = DAG.getDataLayout();
4012 Scale = DAG.getTargetConstant(DL.getTypeAllocSize(GEP->getResultElementType()),
4013 SDB->getCurSDLoc(), TLI.getPointerTy(DL));
4014 Base = SDB->getValue(Ptr);
4015 Index = SDB->getValue(IndexVal);
4016
4017 if (!Index.getValueType().isVector()) {
4018 unsigned GEPWidth = GEP->getType()->getVectorNumElements();
4019 EVT VT = EVT::getVectorVT(Context, Index.getValueType(), GEPWidth);
4020 Index = DAG.getSplatBuildVector(VT, SDLoc(Index), Index);
4021 }
4022 return true;
4023}
4024
4025void SelectionDAGBuilder::visitMaskedScatter(const CallInst &I) {
4026 SDLoc sdl = getCurSDLoc();
4027
4028 // llvm.masked.scatter.*(Src0, Ptrs, alignemt, Mask)
4029 const Value *Ptr = I.getArgOperand(1);
4030 SDValue Src0 = getValue(I.getArgOperand(0));
4031 SDValue Mask = getValue(I.getArgOperand(3));
4032 EVT VT = Src0.getValueType();
4033 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(2)))->getZExtValue();
4034 if (!Alignment)
4035 Alignment = DAG.getEVTAlignment(VT);
4036 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4037
4038 AAMDNodes AAInfo;
4039 I.getAAMetadata(AAInfo);
4040
4041 SDValue Base;
4042 SDValue Index;
4043 SDValue Scale;
4044 const Value *BasePtr = Ptr;
4045 bool UniformBase = getUniformBase(BasePtr, Base, Index, Scale, this);
4046
4047 const Value *MemOpBasePtr = UniformBase ? BasePtr : nullptr;
4048 MachineMemOperand *MMO = DAG.getMachineFunction().
4049 getMachineMemOperand(MachinePointerInfo(MemOpBasePtr),
4050 MachineMemOperand::MOStore, VT.getStoreSize(),
4051 Alignment, AAInfo);
4052 if (!UniformBase) {
4053 Base = DAG.getConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout()));
4054 Index = getValue(Ptr);
4055 Scale = DAG.getTargetConstant(1, sdl, TLI.getPointerTy(DAG.getDataLayout()));
4056 }
4057 SDValue Ops[] = { getRoot(), Src0, Mask, Base, Index, Scale };
4058 SDValue Scatter = DAG.getMaskedScatter(DAG.getVTList(MVT::Other), VT, sdl,
4059 Ops, MMO);
4060 DAG.setRoot(Scatter);
4061 setValue(&I, Scatter);
4062}
4063
4064void SelectionDAGBuilder::visitMaskedLoad(const CallInst &I, bool IsExpanding) {
4065 SDLoc sdl = getCurSDLoc();
4066
4067 auto getMaskedLoadOps = [&](Value* &Ptr, Value* &Mask, Value* &Src0,
4068 unsigned& Alignment) {
4069 // @llvm.masked.load.*(Ptr, alignment, Mask, Src0)
4070 Ptr = I.getArgOperand(0);
4071 Alignment = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
4072 Mask = I.getArgOperand(2);
4073 Src0 = I.getArgOperand(3);
4074 };
4075 auto getExpandingLoadOps = [&](Value* &Ptr, Value* &Mask, Value* &Src0,
4076 unsigned& Alignment) {
4077 // @llvm.masked.expandload.*(Ptr, Mask, Src0)
4078 Ptr = I.getArgOperand(0);
4079 Alignment = 0;
4080 Mask = I.getArgOperand(1);
4081 Src0 = I.getArgOperand(2);
4082 };
4083
4084 Value *PtrOperand, *MaskOperand, *Src0Operand;
4085 unsigned Alignment;
4086 if (IsExpanding)
4087 getExpandingLoadOps(PtrOperand, MaskOperand, Src0Operand, Alignment);
4088 else
4089 getMaskedLoadOps(PtrOperand, MaskOperand, Src0Operand, Alignment);
4090
4091 SDValue Ptr = getValue(PtrOperand);
4092 SDValue Src0 = getValue(Src0Operand);
4093 SDValue Mask = getValue(MaskOperand);
4094
4095 EVT VT = Src0.getValueType();
4096 if (!Alignment)
4097 Alignment = DAG.getEVTAlignment(VT);
4098
4099 AAMDNodes AAInfo;
4100 I.getAAMetadata(AAInfo);
4101 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
4102
4103 // Do not serialize masked loads of constant memory with anything.
4104 bool AddToChain =
4105 !AA || !AA->pointsToConstantMemory(MemoryLocation(
4106 PtrOperand,
4107 LocationSize::precise(
4108 DAG.getDataLayout().getTypeStoreSize(I.getType())),
4109 AAInfo));
4110 SDValue InChain = AddToChain ? DAG.getRoot() : DAG.getEntryNode();
4111
4112 MachineMemOperand *MMO =
4113 DAG.getMachineFunction().
4114 getMachineMemOperand(MachinePointerInfo(PtrOperand),
4115 MachineMemOperand::MOLoad, VT.getStoreSize(),
4116 Alignment, AAInfo, Ranges);
4117
4118 SDValue Load = DAG.getMaskedLoad(VT, sdl, InChain, Ptr, Mask, Src0, VT, MMO,
4119 ISD::NON_EXTLOAD, IsExpanding);
4120 if (AddToChain)
4121 PendingLoads.push_back(Load.getValue(1));
4122 setValue(&I, Load);
4123}
4124
4125void SelectionDAGBuilder::visitMaskedGather(const CallInst &I) {
4126 SDLoc sdl = getCurSDLoc();
4127
4128 // @llvm.masked.gather.*(Ptrs, alignment, Mask, Src0)
4129 const Value *Ptr = I.getArgOperand(0);
4130 SDValue Src0 = getValue(I.getArgOperand(3));
4131 SDValue Mask = getValue(I.getArgOperand(2));
4132
4133 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4134 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4135 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(1)))->getZExtValue();
4136 if (!Alignment)
4137 Alignment = DAG.getEVTAlignment(VT);
4138
4139 AAMDNodes AAInfo;
4140 I.getAAMetadata(AAInfo);
4141 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
4142
4143 SDValue Root = DAG.getRoot();
4144 SDValue Base;
4145 SDValue Index;
4146 SDValue Scale;
4147 const Value *BasePtr = Ptr;
4148 bool UniformBase = getUniformBase(BasePtr, Base, Index, Scale, this);
4149 bool ConstantMemory = false;
4150 if (UniformBase && AA &&
4151 AA->pointsToConstantMemory(
4152 MemoryLocation(BasePtr,
4153 LocationSize::precise(
4154 DAG.getDataLayout().getTypeStoreSize(I.getType())),
4155 AAInfo))) {
4156 // Do not serialize (non-volatile) loads of constant memory with anything.
4157 Root = DAG.getEntryNode();
4158 ConstantMemory = true;
4159 }
4160
4161 MachineMemOperand *MMO =
4162 DAG.getMachineFunction().
4163 getMachineMemOperand(MachinePointerInfo(UniformBase ? BasePtr : nullptr),
4164 MachineMemOperand::MOLoad, VT.getStoreSize(),
4165 Alignment, AAInfo, Ranges);
4166
4167 if (!UniformBase) {
4168 Base = DAG.getConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout()));
4169 Index = getValue(Ptr);
4170 Scale = DAG.getTargetConstant(1, sdl, TLI.getPointerTy(DAG.getDataLayout()));
4171 }
4172 SDValue Ops[] = { Root, Src0, Mask, Base, Index, Scale };
4173 SDValue Gather = DAG.getMaskedGather(DAG.getVTList(VT, MVT::Other), VT, sdl,
4174 Ops, MMO);
4175
4176 SDValue OutChain = Gather.getValue(1);
4177 if (!ConstantMemory)
4178 PendingLoads.push_back(OutChain);
4179 setValue(&I, Gather);
4180}
4181
4182void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) {
4183 SDLoc dl = getCurSDLoc();
4184 AtomicOrdering SuccessOrder = I.getSuccessOrdering();
4185 AtomicOrdering FailureOrder = I.getFailureOrdering();
4186 SyncScope::ID SSID = I.getSyncScopeID();
4187
4188 SDValue InChain = getRoot();
4189
4190 MVT MemVT = getValue(I.getCompareOperand()).getSimpleValueType();
4191 SDVTList VTs = DAG.getVTList(MemVT, MVT::i1, MVT::Other);
4192 SDValue L = DAG.getAtomicCmpSwap(
4193 ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl, MemVT, VTs, InChain,
4194 getValue(I.getPointerOperand()), getValue(I.getCompareOperand()),
4195 getValue(I.getNewValOperand()), MachinePointerInfo(I.getPointerOperand()),
4196 /*Alignment=*/ 0, SuccessOrder, FailureOrder, SSID);
4197
4198 SDValue OutChain = L.getValue(2);
4199
4200 setValue(&I, L);
4201 DAG.setRoot(OutChain);
4202}
4203
4204void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) {
4205 SDLoc dl = getCurSDLoc();
4206 ISD::NodeType NT;
4207 switch (I.getOperation()) {
4208 default: llvm_unreachable("Unknown atomicrmw operation")::llvm::llvm_unreachable_internal("Unknown atomicrmw operation"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 4208)
;
4209 case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break;
4210 case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break;
4211 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break;
4212 case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break;
4213 case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break;
4214 case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break;
4215 case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break;
4216 case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break;
4217 case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break;
4218 case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break;
4219 case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break;
4220 }
4221 AtomicOrdering Order = I.getOrdering();
4222 SyncScope::ID SSID = I.getSyncScopeID();
4223
4224 SDValue InChain = getRoot();
4225
4226 SDValue L =
4227 DAG.getAtomic(NT, dl,
4228 getValue(I.getValOperand()).getSimpleValueType(),
4229 InChain,
4230 getValue(I.getPointerOperand()),
4231 getValue(I.getValOperand()),
4232 I.getPointerOperand(),
4233 /* Alignment=*/ 0, Order, SSID);
4234
4235 SDValue OutChain = L.getValue(1);
4236
4237 setValue(&I, L);
4238 DAG.setRoot(OutChain);
4239}
4240
4241void SelectionDAGBuilder::visitFence(const FenceInst &I) {
4242 SDLoc dl = getCurSDLoc();
4243 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4244 SDValue Ops[3];
4245 Ops[0] = getRoot();
4246 Ops[1] = DAG.getConstant((unsigned)I.getOrdering(), dl,
4247 TLI.getFenceOperandTy(DAG.getDataLayout()));
4248 Ops[2] = DAG.getConstant(I.getSyncScopeID(), dl,
4249 TLI.getFenceOperandTy(DAG.getDataLayout()));
4250 DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops));
4251}
4252
4253void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) {
4254 SDLoc dl = getCurSDLoc();
4255 AtomicOrdering Order = I.getOrdering();
4256 SyncScope::ID SSID = I.getSyncScopeID();
4257
4258 SDValue InChain = getRoot();
4259
4260 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4261 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4262
4263 if (!TLI.supportsUnalignedAtomics() &&
4264 I.getAlignment() < VT.getStoreSize())
4265 report_fatal_error("Cannot generate unaligned atomic load");
4266
4267 MachineMemOperand *MMO =
4268 DAG.getMachineFunction().
4269 getMachineMemOperand(MachinePointerInfo(I.getPointerOperand()),
4270 MachineMemOperand::MOVolatile |
4271 MachineMemOperand::MOLoad,
4272 VT.getStoreSize(),
4273 I.getAlignment() ? I.getAlignment() :
4274 DAG.getEVTAlignment(VT),
4275 AAMDNodes(), nullptr, SSID, Order);
4276
4277 InChain = TLI.prepareVolatileOrAtomicLoad(InChain, dl, DAG);
4278 SDValue L =
4279 DAG.getAtomic(ISD::ATOMIC_LOAD, dl, VT, VT, InChain,
4280 getValue(I.getPointerOperand()), MMO);
4281
4282 SDValue OutChain = L.getValue(1);
4283
4284 setValue(&I, L);
4285 DAG.setRoot(OutChain);
4286}
4287
4288void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) {
4289 SDLoc dl = getCurSDLoc();
4290
4291 AtomicOrdering Order = I.getOrdering();
4292 SyncScope::ID SSID = I.getSyncScopeID();
4293
4294 SDValue InChain = getRoot();
4295
4296 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4297 EVT VT =
4298 TLI.getValueType(DAG.getDataLayout(), I.getValueOperand()->getType());
4299
4300 if (I.getAlignment() < VT.getStoreSize())
4301 report_fatal_error("Cannot generate unaligned atomic store");
4302
4303 SDValue OutChain =
4304 DAG.getAtomic(ISD::ATOMIC_STORE, dl, VT,
4305 InChain,
4306 getValue(I.getPointerOperand()),
4307 getValue(I.getValueOperand()),
4308 I.getPointerOperand(), I.getAlignment(),
4309 Order, SSID);
4310
4311 DAG.setRoot(OutChain);
4312}
4313
4314/// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
4315/// node.
4316void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
4317 unsigned Intrinsic) {
4318 // Ignore the callsite's attributes. A specific call site may be marked with
4319 // readnone, but the lowering code will expect the chain based on the
4320 // definition.
4321 const Function *F = I.getCalledFunction();
4322 bool HasChain = !F->doesNotAccessMemory();
4323 bool OnlyLoad = HasChain && F->onlyReadsMemory();
4324
4325 // Build the operand list.
4326 SmallVector<SDValue, 8> Ops;
4327 if (HasChain) { // If this intrinsic has side-effects, chainify it.
4328 if (OnlyLoad) {
4329 // We don't need to serialize loads against other loads.
4330 Ops.push_back(DAG.getRoot());
4331 } else {
4332 Ops.push_back(getRoot());
4333 }
4334 }
4335
4336 // Info is set by getTgtMemInstrinsic
4337 TargetLowering::IntrinsicInfo Info;
4338 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4339 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I,
4340 DAG.getMachineFunction(),
4341 Intrinsic);
4342
4343 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
4344 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID ||
4345 Info.opc == ISD::INTRINSIC_W_CHAIN)
4346 Ops.push_back(DAG.getTargetConstant(Intrinsic, getCurSDLoc(),
4347 TLI.getPointerTy(DAG.getDataLayout())));
4348
4349 // Add all operands of the call to the operand list.
4350 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
4351 SDValue Op = getValue(I.getArgOperand(i));
4352 Ops.push_back(Op);
4353 }
4354
4355 SmallVector<EVT, 4> ValueVTs;
4356 ComputeValueVTs(TLI, DAG.getDataLayout(), I.getType(), ValueVTs);
4357
4358 if (HasChain)
4359 ValueVTs.push_back(MVT::Other);
4360
4361 SDVTList VTs = DAG.getVTList(ValueVTs);
4362
4363 // Create the node.
4364 SDValue Result;
4365 if (IsTgtIntrinsic) {
4366 // This is target intrinsic that touches memory
4367 Result = DAG.getMemIntrinsicNode(Info.opc, getCurSDLoc(), VTs,
4368 Ops, Info.memVT,
4369 MachinePointerInfo(Info.ptrVal, Info.offset), Info.align,
4370 Info.flags, Info.size);
4371 } else if (!HasChain) {
4372 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurSDLoc(), VTs, Ops);
4373 } else if (!I.getType()->isVoidTy()) {
4374 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurSDLoc(), VTs, Ops);
4375 } else {
4376 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurSDLoc(), VTs, Ops);
4377 }
4378
4379 if (HasChain) {
4380 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
4381 if (OnlyLoad)
4382 PendingLoads.push_back(Chain);
4383 else
4384 DAG.setRoot(Chain);
4385 }
4386
4387 if (!I.getType()->isVoidTy()) {
4388 if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
4389 EVT VT = TLI.getValueType(DAG.getDataLayout(), PTy);
4390 Result = DAG.getNode(ISD::BITCAST, getCurSDLoc(), VT, Result);
4391 } else
4392 Result = lowerRangeToAssertZExt(DAG, I, Result);
4393
4394 setValue(&I, Result);
4395 }
4396}
4397
4398/// GetSignificand - Get the significand and build it into a floating-point
4399/// number with exponent of 1:
4400///
4401/// Op = (Op & 0x007fffff) | 0x3f800000;
4402///
4403/// where Op is the hexadecimal representation of floating point value.
4404static SDValue GetSignificand(SelectionDAG &DAG, SDValue Op, const SDLoc &dl) {
4405 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
4406 DAG.getConstant(0x007fffff, dl, MVT::i32));
4407 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
4408 DAG.getConstant(0x3f800000, dl, MVT::i32));
4409 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2);
4410}
4411
4412/// GetExponent - Get the exponent:
4413///
4414/// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
4415///
4416/// where Op is the hexadecimal representation of floating point value.
4417static SDValue GetExponent(SelectionDAG &DAG, SDValue Op,
4418 const TargetLowering &TLI, const SDLoc &dl) {
4419 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
4420 DAG.getConstant(0x7f800000, dl, MVT::i32));
4421 SDValue t1 = DAG.getNode(
4422 ISD::SRL, dl, MVT::i32, t0,
4423 DAG.getConstant(23, dl, TLI.getPointerTy(DAG.getDataLayout())));
4424 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
4425 DAG.getConstant(127, dl, MVT::i32));
4426 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
4427}
4428
4429/// getF32Constant - Get 32-bit floating point constant.
4430static SDValue getF32Constant(SelectionDAG &DAG, unsigned Flt,
4431 const SDLoc &dl) {
4432 return DAG.getConstantFP(APFloat(APFloat::IEEEsingle(), APInt(32, Flt)), dl,
4433 MVT::f32);
4434}
4435
4436static SDValue getLimitedPrecisionExp2(SDValue t0, const SDLoc &dl,
4437 SelectionDAG &DAG) {
4438 // TODO: What fast-math-flags should be set on the floating-point nodes?
4439
4440 // IntegerPartOfX = ((int32_t)(t0);
4441 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
4442
4443 // FractionalPartOfX = t0 - (float)IntegerPartOfX;
4444 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
4445 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
4446
4447 // IntegerPartOfX <<= 23;
4448 IntegerPartOfX = DAG.getNode(
4449 ISD::SHL, dl, MVT::i32, IntegerPartOfX,
4450 DAG.getConstant(23, dl, DAG.getTargetLoweringInfo().getPointerTy(
4451 DAG.getDataLayout())));
4452
4453 SDValue TwoToFractionalPartOfX;
4454 if (LimitFloatPrecision <= 6) {
4455 // For floating-point precision of 6:
4456 //
4457 // TwoToFractionalPartOfX =
4458 // 0.997535578f +
4459 // (0.735607626f + 0.252464424f * x) * x;
4460 //
4461 // error 0.0144103317, which is 6 bits
4462 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4463 getF32Constant(DAG, 0x3e814304, dl));
4464 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4465 getF32Constant(DAG, 0x3f3c50c8, dl));
4466 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4467 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4468 getF32Constant(DAG, 0x3f7f5e7e, dl));
4469 } else if (LimitFloatPrecision <= 12) {
4470 // For floating-point precision of 12:
4471 //
4472 // TwoToFractionalPartOfX =
4473 // 0.999892986f +
4474 // (0.696457318f +
4475 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
4476 //
4477 // error 0.000107046256, which is 13 to 14 bits
4478 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4479 getF32Constant(DAG, 0x3da235e3, dl));
4480 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4481 getF32Constant(DAG, 0x3e65b8f3, dl));
4482 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4483 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4484 getF32Constant(DAG, 0x3f324b07, dl));
4485 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4486 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4487 getF32Constant(DAG, 0x3f7ff8fd, dl));
4488 } else { // LimitFloatPrecision <= 18
4489 // For floating-point precision of 18:
4490 //
4491 // TwoToFractionalPartOfX =
4492 // 0.999999982f +
4493 // (0.693148872f +
4494 // (0.240227044f +
4495 // (0.554906021e-1f +
4496 // (0.961591928e-2f +
4497 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
4498 // error 2.47208000*10^(-7), which is better than 18 bits
4499 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4500 getF32Constant(DAG, 0x3924b03e, dl));
4501 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4502 getF32Constant(DAG, 0x3ab24b87, dl));
4503 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4504 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4505 getF32Constant(DAG, 0x3c1d8c17, dl));
4506 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4507 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4508 getF32Constant(DAG, 0x3d634a1d, dl));
4509 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4510 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4511 getF32Constant(DAG, 0x3e75fe14, dl));
4512 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4513 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
4514 getF32Constant(DAG, 0x3f317234, dl));
4515 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
4516 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
4517 getF32Constant(DAG, 0x3f800000, dl));
4518 }
4519
4520 // Add the exponent into the result in integer domain.
4521 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, TwoToFractionalPartOfX);
4522 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
4523 DAG.getNode(ISD::ADD, dl, MVT::i32, t13, IntegerPartOfX));
4524}
4525
4526/// expandExp - Lower an exp intrinsic. Handles the special sequences for
4527/// limited-precision mode.
4528static SDValue expandExp(const SDLoc &dl, SDValue Op, SelectionDAG &DAG,
4529 const TargetLowering &TLI) {
4530 if (Op.getValueType() == MVT::f32 &&
4531 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4532
4533 // Put the exponent in the right bit position for later addition to the
4534 // final result:
4535 //
4536 // #define LOG2OFe 1.4426950f
4537 // t0 = Op * LOG2OFe
4538
4539 // TODO: What fast-math-flags should be set here?
4540 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
4541 getF32Constant(DAG, 0x3fb8aa3b, dl));
4542 return getLimitedPrecisionExp2(t0, dl, DAG);
4543 }
4544
4545 // No special expansion.
4546 return DAG.getNode(ISD::FEXP, dl, Op.getValueType(), Op);
4547}
4548
4549/// expandLog - Lower a log intrinsic. Handles the special sequences for
4550/// limited-precision mode.
4551static SDValue expandLog(const SDLoc &dl, SDValue Op, SelectionDAG &DAG,
4552 const TargetLowering &TLI) {
4553 // TODO: What fast-math-flags should be set on the floating-point nodes?
4554
4555 if (Op.getValueType() == MVT::f32 &&
4556 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4557 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
4558
4559 // Scale the exponent by log(2) [0.69314718f].
4560 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
4561 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
4562 getF32Constant(DAG, 0x3f317218, dl));
4563
4564 // Get the significand and build it into a floating-point number with
4565 // exponent of 1.
4566 SDValue X = GetSignificand(DAG, Op1, dl);
4567
4568 SDValue LogOfMantissa;
4569 if (LimitFloatPrecision <= 6) {
4570 // For floating-point precision of 6:
4571 //
4572 // LogofMantissa =
4573 // -1.1609546f +
4574 // (1.4034025f - 0.23903021f * x) * x;
4575 //
4576 // error 0.0034276066, which is better than 8 bits
4577 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4578 getF32Constant(DAG, 0xbe74c456, dl));
4579 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4580 getF32Constant(DAG, 0x3fb3a2b1, dl));
4581 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4582 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4583 getF32Constant(DAG, 0x3f949a29, dl));
4584 } else if (LimitFloatPrecision <= 12) {
4585 // For floating-point precision of 12:
4586 //
4587 // LogOfMantissa =
4588 // -1.7417939f +
4589 // (2.8212026f +
4590 // (-1.4699568f +
4591 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
4592 //
4593 // error 0.000061011436, which is 14 bits
4594 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4595 getF32Constant(DAG, 0xbd67b6d6, dl));
4596 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4597 getF32Constant(DAG, 0x3ee4f4b8, dl));
4598 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4599 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4600 getF32Constant(DAG, 0x3fbc278b, dl));
4601 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4602 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4603 getF32Constant(DAG, 0x40348e95, dl));
4604 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4605 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4606 getF32Constant(DAG, 0x3fdef31a, dl));
4607 } else { // LimitFloatPrecision <= 18
4608 // For floating-point precision of 18:
4609 //
4610 // LogOfMantissa =
4611 // -2.1072184f +
4612 // (4.2372794f +
4613 // (-3.7029485f +
4614 // (2.2781945f +
4615 // (-0.87823314f +
4616 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
4617 //
4618 // error 0.0000023660568, which is better than 18 bits
4619 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4620 getF32Constant(DAG, 0xbc91e5ac, dl));
4621 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4622 getF32Constant(DAG, 0x3e4350aa, dl));
4623 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4624 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4625 getF32Constant(DAG, 0x3f60d3e3, dl));
4626 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4627 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4628 getF32Constant(DAG, 0x4011cdf0, dl));
4629 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4630 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4631 getF32Constant(DAG, 0x406cfd1c, dl));
4632 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4633 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4634 getF32Constant(DAG, 0x408797cb, dl));
4635 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4636 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
4637 getF32Constant(DAG, 0x4006dcab, dl));
4638 }
4639
4640 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, LogOfMantissa);
4641 }
4642
4643 // No special expansion.
4644 return DAG.getNode(ISD::FLOG, dl, Op.getValueType(), Op);
4645}
4646
4647/// expandLog2 - Lower a log2 intrinsic. Handles the special sequences for
4648/// limited-precision mode.
4649static SDValue expandLog2(const SDLoc &dl, SDValue Op, SelectionDAG &DAG,
4650 const TargetLowering &TLI) {
4651 // TODO: What fast-math-flags should be set on the floating-point nodes?
4652
4653 if (Op.getValueType() == MVT::f32 &&
4654 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4655 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
4656
4657 // Get the exponent.
4658 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
4659
4660 // Get the significand and build it into a floating-point number with
4661 // exponent of 1.
4662 SDValue X = GetSignificand(DAG, Op1, dl);
4663
4664 // Different possible minimax approximations of significand in
4665 // floating-point for various degrees of accuracy over [1,2].
4666 SDValue Log2ofMantissa;
4667 if (LimitFloatPrecision <= 6) {
4668 // For floating-point precision of 6:
4669 //
4670 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
4671 //
4672 // error 0.0049451742, which is more than 7 bits
4673 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4674 getF32Constant(DAG, 0xbeb08fe0, dl));
4675 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4676 getF32Constant(DAG, 0x40019463, dl));
4677 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4678 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4679 getF32Constant(DAG, 0x3fd6633d, dl));
4680 } else if (LimitFloatPrecision <= 12) {
4681 // For floating-point precision of 12:
4682 //
4683 // Log2ofMantissa =
4684 // -2.51285454f +
4685 // (4.07009056f +
4686 // (-2.12067489f +
4687 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
4688 //
4689 // error 0.0000876136000, which is better than 13 bits
4690 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4691 getF32Constant(DAG, 0xbda7262e, dl));
4692 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4693 getF32Constant(DAG, 0x3f25280b, dl));
4694 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4695 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4696 getF32Constant(DAG, 0x4007b923, dl));
4697 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4698 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4699 getF32Constant(DAG, 0x40823e2f, dl));
4700 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4701 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4702 getF32Constant(DAG, 0x4020d29c, dl));
4703 } else { // LimitFloatPrecision <= 18
4704 // For floating-point precision of 18:
4705 //
4706 // Log2ofMantissa =
4707 // -3.0400495f +
4708 // (6.1129976f +
4709 // (-5.3420409f +
4710 // (3.2865683f +
4711 // (-1.2669343f +
4712 // (0.27515199f -
4713 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
4714 //
4715 // error 0.0000018516, which is better than 18 bits
4716 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4717 getF32Constant(DAG, 0xbcd2769e, dl));
4718 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4719 getF32Constant(DAG, 0x3e8ce0b9, dl));
4720 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4721 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4722 getF32Constant(DAG, 0x3fa22ae7, dl));
4723 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4724 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4725 getF32Constant(DAG, 0x40525723, dl));
4726 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4727 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4728 getF32Constant(DAG, 0x40aaf200, dl));
4729 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4730 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4731 getF32Constant(DAG, 0x40c39dad, dl));
4732 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4733 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
4734 getF32Constant(DAG, 0x4042902c, dl));
4735 }
4736
4737 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log2ofMantissa);
4738 }
4739
4740 // No special expansion.
4741 return DAG.getNode(ISD::FLOG2, dl, Op.getValueType(), Op);
4742}
4743
4744/// expandLog10 - Lower a log10 intrinsic. Handles the special sequences for
4745/// limited-precision mode.
4746static SDValue expandLog10(const SDLoc &dl, SDValue Op, SelectionDAG &DAG,
4747 const TargetLowering &TLI) {
4748 // TODO: What fast-math-flags should be set on the floating-point nodes?
4749
4750 if (Op.getValueType() == MVT::f32 &&
4751 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4752 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
4753
4754 // Scale the exponent by log10(2) [0.30102999f].
4755 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
4756 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
4757 getF32Constant(DAG, 0x3e9a209a, dl));
4758
4759 // Get the significand and build it into a floating-point number with
4760 // exponent of 1.
4761 SDValue X = GetSignificand(DAG, Op1, dl);
4762
4763 SDValue Log10ofMantissa;
4764 if (LimitFloatPrecision <= 6) {
4765 // For floating-point precision of 6:
4766 //
4767 // Log10ofMantissa =
4768 // -0.50419619f +
4769 // (0.60948995f - 0.10380950f * x) * x;
4770 //
4771 // error 0.0014886165, which is 6 bits
4772 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4773 getF32Constant(DAG, 0xbdd49a13, dl));
4774 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4775 getF32Constant(DAG, 0x3f1c0789, dl));
4776 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4777 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4778 getF32Constant(DAG, 0x3f011300, dl));
4779 } else if (LimitFloatPrecision <= 12) {
4780 // For floating-point precision of 12:
4781 //
4782 // Log10ofMantissa =
4783 // -0.64831180f +
4784 // (0.91751397f +
4785 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
4786 //
4787 // error 0.00019228036, which is better than 12 bits
4788 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4789 getF32Constant(DAG, 0x3d431f31, dl));
4790 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4791 getF32Constant(DAG, 0x3ea21fb2, dl));
4792 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4793 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4794 getF32Constant(DAG, 0x3f6ae232, dl));
4795 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4796 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4797 getF32Constant(DAG, 0x3f25f7c3, dl));
4798 } else { // LimitFloatPrecision <= 18
4799 // For floating-point precision of 18:
4800 //
4801 // Log10ofMantissa =
4802 // -0.84299375f +
4803 // (1.5327582f +
4804 // (-1.0688956f +
4805 // (0.49102474f +
4806 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
4807 //
4808 // error 0.0000037995730, which is better than 18 bits
4809 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4810 getF32Constant(DAG, 0x3c5d51ce, dl));
4811 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4812 getF32Constant(DAG, 0x3e00685a, dl));
4813 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4814 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4815 getF32Constant(DAG, 0x3efb6798, dl));
4816 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4817 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4818 getF32Constant(DAG, 0x3f88d192, dl));
4819 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4820 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4821 getF32Constant(DAG, 0x3fc4316c, dl));
4822 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4823 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
4824 getF32Constant(DAG, 0x3f57ce70, dl));
4825 }
4826
4827 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log10ofMantissa);
4828 }
4829
4830 // No special expansion.
4831 return DAG.getNode(ISD::FLOG10, dl, Op.getValueType(), Op);
4832}
4833
4834/// expandExp2 - Lower an exp2 intrinsic. Handles the special sequences for
4835/// limited-precision mode.
4836static SDValue expandExp2(const SDLoc &dl, SDValue Op, SelectionDAG &DAG,
4837 const TargetLowering &TLI) {
4838 if (Op.getValueType() == MVT::f32 &&
4839 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18)
4840 return getLimitedPrecisionExp2(Op, dl, DAG);
4841
4842 // No special expansion.
4843 return DAG.getNode(ISD::FEXP2, dl, Op.getValueType(), Op);
4844}
4845
4846/// visitPow - Lower a pow intrinsic. Handles the special sequences for
4847/// limited-precision mode with x == 10.0f.
4848static SDValue expandPow(const SDLoc &dl, SDValue LHS, SDValue RHS,
4849 SelectionDAG &DAG, const TargetLowering &TLI) {
4850 bool IsExp10 = false;
4851 if (LHS.getValueType() == MVT::f32 && RHS.getValueType() == MVT::f32 &&
4852 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4853 if (ConstantFPSDNode *LHSC = dyn_cast<ConstantFPSDNode>(LHS)) {
4854 APFloat Ten(10.0f);
4855 IsExp10 = LHSC->isExactlyValue(Ten);
4856 }
4857 }
4858
4859 // TODO: What fast-math-flags should be set on the FMUL node?
4860 if (IsExp10) {
4861 // Put the exponent in the right bit position for later addition to the
4862 // final result:
4863 //
4864 // #define LOG2OF10 3.3219281f
4865 // t0 = Op * LOG2OF10;
4866 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, RHS,
4867 getF32Constant(DAG, 0x40549a78, dl));
4868 return getLimitedPrecisionExp2(t0, dl, DAG);
4869 }
4870
4871 // No special expansion.
4872 return DAG.getNode(ISD::FPOW, dl, LHS.getValueType(), LHS, RHS);
4873}
4874
4875/// ExpandPowI - Expand a llvm.powi intrinsic.
4876static SDValue ExpandPowI(const SDLoc &DL, SDValue LHS, SDValue RHS,
4877 SelectionDAG &DAG) {
4878 // If RHS is a constant, we can expand this out to a multiplication tree,
4879 // otherwise we end up lowering to a call to __powidf2 (for example). When
4880 // optimizing for size, we only want to do this if the expansion would produce
4881 // a small number of multiplies, otherwise we do the full expansion.
4882 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
4883 // Get the exponent as a positive value.
4884 unsigned Val = RHSC->getSExtValue();
4885 if ((int)Val < 0) Val = -Val;
4886
4887 // powi(x, 0) -> 1.0
4888 if (Val == 0)
4889 return DAG.getConstantFP(1.0, DL, LHS.getValueType());
4890
4891 const Function &F = DAG.getMachineFunction().getFunction();
4892 if (!F.optForSize() ||
4893 // If optimizing for size, don't insert too many multiplies.
4894 // This inserts up to 5 multiplies.
4895 countPopulation(Val) + Log2_32(Val) < 7) {
4896 // We use the simple binary decomposition method to generate the multiply
4897 // sequence. There are more optimal ways to do this (for example,
4898 // powi(x,15) generates one more multiply than it should), but this has
4899 // the benefit of being both really simple and much better than a libcall.
4900 SDValue Res; // Logically starts equal to 1.0
4901 SDValue CurSquare = LHS;
4902 // TODO: Intrinsics should have fast-math-flags that propagate to these
4903 // nodes.
4904 while (Val) {
4905 if (Val & 1) {
4906 if (Res.getNode())
4907 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare);
4908 else
4909 Res = CurSquare; // 1.0*CurSquare.
4910 }
4911
4912 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(),
4913 CurSquare, CurSquare);
4914 Val >>= 1;
4915 }
4916
4917 // If the original was negative, invert the result, producing 1/(x*x*x).
4918 if (RHSC->getSExtValue() < 0)
4919 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(),
4920 DAG.getConstantFP(1.0, DL, LHS.getValueType()), Res);
4921 return Res;
4922 }
4923 }
4924
4925 // Otherwise, expand to a libcall.
4926 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS);
4927}
4928
4929// getUnderlyingArgReg - Find underlying register used for a truncated or
4930// bitcasted argument.
4931static unsigned getUnderlyingArgReg(const SDValue &N) {
4932 switch (N.getOpcode()) {
4933 case ISD::CopyFromReg:
4934 return cast<RegisterSDNode>(N.getOperand(1))->getReg();
4935 case ISD::BITCAST:
4936 case ISD::AssertZext:
4937 case ISD::AssertSext:
4938 case ISD::TRUNCATE:
4939 return getUnderlyingArgReg(N.getOperand(0));
4940 default:
4941 return 0;
4942 }
4943}
4944
4945/// If the DbgValueInst is a dbg_value of a function argument, create the
4946/// corresponding DBG_VALUE machine instruction for it now. At the end of
4947/// instruction selection, they will be inserted to the entry BB.
4948bool SelectionDAGBuilder::EmitFuncArgumentDbgValue(
4949 const Value *V, DILocalVariable *Variable, DIExpression *Expr,
4950 DILocation *DL, bool IsDbgDeclare, const SDValue &N) {
4951 const Argument *Arg = dyn_cast<Argument>(V);
4952 if (!Arg)
4953 return false;
4954
4955 MachineFunction &MF = DAG.getMachineFunction();
4956 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
4957
4958 bool IsIndirect = false;
4959 Optional<MachineOperand> Op;
4960 // Some arguments' frame index is recorded during argument lowering.
4961 int FI = FuncInfo.getArgumentFrameIndex(Arg);
4962 if (FI != std::numeric_limits<int>::max())
4963 Op = MachineOperand::CreateFI(FI);
4964
4965 if (!Op && N.getNode()) {
4966 unsigned Reg = getUnderlyingArgReg(N);
4967 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) {
4968 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4969 unsigned PR = RegInfo.getLiveInPhysReg(Reg);
4970 if (PR)
4971 Reg = PR;
4972 }
4973 if (Reg) {
4974 Op = MachineOperand::CreateReg(Reg, false);
4975 IsIndirect = IsDbgDeclare;
4976 }
4977 }
4978
4979 if (!Op && N.getNode())
4980 // Check if frame index is available.
4981 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode()))
4982 if (FrameIndexSDNode *FINode =
4983 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
4984 Op = MachineOperand::CreateFI(FINode->getIndex());
4985
4986 if (!Op) {
4987 // Check if ValueMap has reg number.
4988 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
4989 if (VMI != FuncInfo.ValueMap.end()) {
4990 const auto &TLI = DAG.getTargetLoweringInfo();
4991 RegsForValue RFV(V->getContext(), TLI, DAG.getDataLayout(), VMI->second,
4992 V->getType(), getABIRegCopyCC(V));
4993 if (RFV.occupiesMultipleRegs()) {
4994 unsigned Offset = 0;
4995 for (auto RegAndSize : RFV.getRegsAndSizes()) {
4996 Op = MachineOperand::CreateReg(RegAndSize.first, false);
4997 auto FragmentExpr = DIExpression::createFragmentExpression(
4998 Expr, Offset, RegAndSize.second);
4999 if (!FragmentExpr)
5000 continue;
5001 FuncInfo.ArgDbgValues.push_back(
5002 BuildMI(MF, DL, TII->get(TargetOpcode::DBG_VALUE), IsDbgDeclare,
5003 Op->getReg(), Variable, *FragmentExpr));
5004 Offset += RegAndSize.second;
5005 }
5006 return true;
5007 }
5008 Op = MachineOperand::CreateReg(VMI->second, false);
5009 IsIndirect = IsDbgDeclare;
5010 }
5011 }
5012
5013 if (!Op)
5014 return false;
5015
5016 assert(Variable->isValidLocationForIntrinsic(DL) &&((Variable->isValidLocationForIntrinsic(DL) && "Expected inlined-at fields to agree"
) ? static_cast<void> (0) : __assert_fail ("Variable->isValidLocationForIntrinsic(DL) && \"Expected inlined-at fields to agree\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 5017, __PRETTY_FUNCTION__))
5017 "Expected inlined-at fields to agree")((Variable->isValidLocationForIntrinsic(DL) && "Expected inlined-at fields to agree"
) ? static_cast<void> (0) : __assert_fail ("Variable->isValidLocationForIntrinsic(DL) && \"Expected inlined-at fields to agree\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 5017, __PRETTY_FUNCTION__))
;
5018 IsIndirect = (Op->isReg()) ? IsIndirect : true;
5019 FuncInfo.ArgDbgValues.push_back(
5020 BuildMI(MF, DL, TII->get(TargetOpcode::DBG_VALUE), IsIndirect,
5021 *Op, Variable, Expr));
5022
5023 return true;
5024}
5025
5026/// Return the appropriate SDDbgValue based on N.
5027SDDbgValue *SelectionDAGBuilder::getDbgValue(SDValue N,
5028 DILocalVariable *Variable,
5029 DIExpression *Expr,
5030 const DebugLoc &dl,
5031 unsigned DbgSDNodeOrder) {
5032 if (auto *FISDN = dyn_cast<FrameIndexSDNode>(N.getNode())) {
5033 // Construct a FrameIndexDbgValue for FrameIndexSDNodes so we can describe
5034 // stack slot locations.
5035 //
5036 // Consider "int x = 0; int *px = &x;". There are two kinds of interesting
5037 // debug values here after optimization:
5038 //
5039 // dbg.value(i32* %px, !"int *px", !DIExpression()), and
5040 // dbg.value(i32* %px, !"int x", !DIExpression(DW_OP_deref))
5041 //
5042 // Both describe the direct values of their associated variables.
5043 return DAG.getFrameIndexDbgValue(Variable, Expr, FISDN->getIndex(),
5044 /*IsIndirect*/ false, dl, DbgSDNodeOrder);
5045 }
5046 return DAG.getDbgValue(Variable, Expr, N.getNode(), N.getResNo(),
5047 /*IsIndirect*/ false, dl, DbgSDNodeOrder);
5048}
5049
5050// VisualStudio defines setjmp as _setjmp
5051#if defined(_MSC_VER) && defined(setjmp) && \
5052 !defined(setjmp_undefined_for_msvc)
5053# pragma push_macro("setjmp")
5054# undef setjmp
5055# define setjmp_undefined_for_msvc
5056#endif
5057
5058/// Lower the call to the specified intrinsic function. If we want to emit this
5059/// as a call to a named external function, return the name. Otherwise, lower it
5060/// and return null.
5061const char *
5062SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
5063 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5064 SDLoc sdl = getCurSDLoc();
5065 DebugLoc dl = getCurDebugLoc();
5066 SDValue Res;
5067
5068 switch (Intrinsic) {
5069 default:
5070 // By default, turn this into a target intrinsic node.
5071 visitTargetIntrinsic(I, Intrinsic);
5072 return nullptr;
5073 case Intrinsic::vastart: visitVAStart(I); return nullptr;
5074 case Intrinsic::vaend: visitVAEnd(I); return nullptr;
5075 case Intrinsic::vacopy: visitVACopy(I); return nullptr;
5076 case Intrinsic::returnaddress:
5077 setValue(&I, DAG.getNode(ISD::RETURNADDR, sdl,
5078 TLI.getPointerTy(DAG.getDataLayout()),
5079 getValue(I.getArgOperand(0))));
5080 return nullptr;
5081 case Intrinsic::addressofreturnaddress:
5082 setValue(&I, DAG.getNode(ISD::ADDROFRETURNADDR, sdl,
5083 TLI.getPointerTy(DAG.getDataLayout())));
5084 return nullptr;
5085 case Intrinsic::sponentry:
5086 setValue(&I, DAG.getNode(ISD::SPONENTRY, sdl,
5087 TLI.getPointerTy(DAG.getDataLayout())));
5088 return nullptr;
5089 case Intrinsic::frameaddress:
5090 setValue(&I, DAG.getNode(ISD::FRAMEADDR, sdl,
5091 TLI.getPointerTy(DAG.getDataLayout()),
5092 getValue(I.getArgOperand(0))));
5093 return nullptr;
5094 case Intrinsic::read_register: {
5095 Value *Reg = I.getArgOperand(0);
5096 SDValue Chain = getRoot();
5097 SDValue RegName =
5098 DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
5099 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
5100 Res = DAG.getNode(ISD::READ_REGISTER, sdl,
5101 DAG.getVTList(VT, MVT::Other), Chain, RegName);
5102 setValue(&I, Res);
5103 DAG.setRoot(Res.getValue(1));
5104 return nullptr;
5105 }
5106 case Intrinsic::write_register: {
5107 Value *Reg = I.getArgOperand(0);
5108 Value *RegValue = I.getArgOperand(1);
5109 SDValue Chain = getRoot();
5110 SDValue RegName =
5111 DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
5112 DAG.setRoot(DAG.getNode(ISD::WRITE_REGISTER, sdl, MVT::Other, Chain,
5113 RegName, getValue(RegValue)));
5114 return nullptr;
5115 }
5116 case Intrinsic::setjmp:
5117 return &"_setjmp"[!TLI.usesUnderscoreSetJmp()];
5118 case Intrinsic::longjmp:
5119 return &"_longjmp"[!TLI.usesUnderscoreLongJmp()];
5120 case Intrinsic::memcpy: {
5121 const auto &MCI = cast<MemCpyInst>(I);
5122 SDValue Op1 = getValue(I.getArgOperand(0));
5123 SDValue Op2 = getValue(I.getArgOperand(1));
5124 SDValue Op3 = getValue(I.getArgOperand(2));
5125 // @llvm.memcpy defines 0 and 1 to both mean no alignment.
5126 unsigned DstAlign = std::max<unsigned>(MCI.getDestAlignment(), 1);
5127 unsigned SrcAlign = std::max<unsigned>(MCI.getSourceAlignment(), 1);
5128 unsigned Align = MinAlign(DstAlign, SrcAlign);
5129 bool isVol = MCI.isVolatile();
5130 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
5131 // FIXME: Support passing different dest/src alignments to the memcpy DAG
5132 // node.
5133 SDValue MC = DAG.getMemcpy(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
5134 false, isTC,
5135 MachinePointerInfo(I.getArgOperand(0)),
5136 MachinePointerInfo(I.getArgOperand(1)));
5137 updateDAGForMaybeTailCall(MC);
5138 return nullptr;
5139 }
5140 case Intrinsic::memset: {
5141 const auto &MSI = cast<MemSetInst>(I);
5142 SDValue Op1 = getValue(I.getArgOperand(0));
5143 SDValue Op2 = getValue(I.getArgOperand(1));
5144 SDValue Op3 = getValue(I.getArgOperand(2));
5145 // @llvm.memset defines 0 and 1 to both mean no alignment.
5146 unsigned Align = std::max<unsigned>(MSI.getDestAlignment(), 1);
5147 bool isVol = MSI.isVolatile();
5148 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
5149 SDValue MS = DAG.getMemset(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
5150 isTC, MachinePointerInfo(I.getArgOperand(0)));
5151 updateDAGForMaybeTailCall(MS);
5152 return nullptr;
5153 }
5154 case Intrinsic::memmove: {
5155 const auto &MMI = cast<MemMoveInst>(I);
5156 SDValue Op1 = getValue(I.getArgOperand(0));
5157 SDValue Op2 = getValue(I.getArgOperand(1));
5158 SDValue Op3 = getValue(I.getArgOperand(2));
5159 // @llvm.memmove defines 0 and 1 to both mean no alignment.
5160 unsigned DstAlign = std::max<unsigned>(MMI.getDestAlignment(), 1);
5161 unsigned SrcAlign = std::max<unsigned>(MMI.getSourceAlignment(), 1);
5162 unsigned Align = MinAlign(DstAlign, SrcAlign);
5163 bool isVol = MMI.isVolatile();
5164 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
5165 // FIXME: Support passing different dest/src alignments to the memmove DAG
5166 // node.
5167 SDValue MM = DAG.getMemmove(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
5168 isTC, MachinePointerInfo(I.getArgOperand(0)),
5169 MachinePointerInfo(I.getArgOperand(1)));
5170 updateDAGForMaybeTailCall(MM);
5171 return nullptr;
5172 }
5173 case Intrinsic::memcpy_element_unordered_atomic: {
5174 const AtomicMemCpyInst &MI = cast<AtomicMemCpyInst>(I);
5175 SDValue Dst = getValue(MI.getRawDest());
5176 SDValue Src = getValue(MI.getRawSource());
5177 SDValue Length = getValue(MI.getLength());
5178
5179 unsigned DstAlign = MI.getDestAlignment();
5180 unsigned SrcAlign = MI.getSourceAlignment();
5181 Type *LengthTy = MI.getLength()->getType();
5182 unsigned ElemSz = MI.getElementSizeInBytes();
5183 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
5184 SDValue MC = DAG.getAtomicMemcpy(getRoot(), sdl, Dst, DstAlign, Src,
5185 SrcAlign, Length, LengthTy, ElemSz, isTC,
5186 MachinePointerInfo(MI.getRawDest()),
5187 MachinePointerInfo(MI.getRawSource()));
5188 updateDAGForMaybeTailCall(MC);
5189 return nullptr;
5190 }
5191 case Intrinsic::memmove_element_unordered_atomic: {
5192 auto &MI = cast<AtomicMemMoveInst>(I);
5193 SDValue Dst = getValue(MI.getRawDest());
5194 SDValue Src = getValue(MI.getRawSource());
5195 SDValue Length = getValue(MI.getLength());
5196
5197 unsigned DstAlign = MI.getDestAlignment();
5198 unsigned SrcAlign = MI.getSourceAlignment();
5199 Type *LengthTy = MI.getLength()->getType();
5200 unsigned ElemSz = MI.getElementSizeInBytes();
5201 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
5202 SDValue MC = DAG.getAtomicMemmove(getRoot(), sdl, Dst, DstAlign, Src,
5203 SrcAlign, Length, LengthTy, ElemSz, isTC,
5204 MachinePointerInfo(MI.getRawDest()),
5205 MachinePointerInfo(MI.getRawSource()));
5206 updateDAGForMaybeTailCall(MC);
5207 return nullptr;
5208 }
5209 case Intrinsic::memset_element_unordered_atomic: {
5210 auto &MI = cast<AtomicMemSetInst>(I);
5211 SDValue Dst = getValue(MI.getRawDest());
5212 SDValue Val = getValue(MI.getValue());
5213 SDValue Length = getValue(MI.getLength());
5214
5215 unsigned DstAlign = MI.getDestAlignment();
5216 Type *LengthTy = MI.getLength()->getType();
5217 unsigned ElemSz = MI.getElementSizeInBytes();
5218 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
5219 SDValue MC = DAG.getAtomicMemset(getRoot(), sdl, Dst, DstAlign, Val, Length,
5220 LengthTy, ElemSz, isTC,
5221 MachinePointerInfo(MI.getRawDest()));
5222 updateDAGForMaybeTailCall(MC);
5223 return nullptr;
5224 }
5225 case Intrinsic::dbg_addr:
5226 case Intrinsic::dbg_declare: {
5227 const auto &DI = cast<DbgVariableIntrinsic>(I);
5228 DILocalVariable *Variable = DI.getVariable();
5229 DIExpression *Expression = DI.getExpression();
5230 dropDanglingDebugInfo(Variable, Expression);
5231 assert(Variable && "Missing variable")((Variable && "Missing variable") ? static_cast<void
> (0) : __assert_fail ("Variable && \"Missing variable\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 5231, __PRETTY_FUNCTION__))
;
5232
5233 // Check if address has undef value.
5234 const Value *Address = DI.getVariableLocation();
5235 if (!Address || isa<UndefValue>(Address) ||
5236 (Address->use_empty() && !isa<Argument>(Address))) {
5237 LLVM_DEBUG(dbgs() << "Dropping debug info for " << DI << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << "Dropping debug info for " <<
DI << "\n"; } } while (false)
;
5238 return nullptr;
5239 }
5240
5241 bool isParameter = Variable->isParameter() || isa<Argument>(Address);
5242
5243 // Check if this variable can be described by a frame index, typically
5244 // either as a static alloca or a byval parameter.
5245 int FI = std::numeric_limits<int>::max();
5246 if (const auto *AI =
5247 dyn_cast<AllocaInst>(Address->stripInBoundsConstantOffsets())) {
5248 if (AI->isStaticAlloca()) {
5249 auto I = FuncInfo.StaticAllocaMap.find(AI);
5250 if (I != FuncInfo.StaticAllocaMap.end())
5251 FI = I->second;
5252 }
5253 } else if (const auto *Arg = dyn_cast<Argument>(
5254 Address->stripInBoundsConstantOffsets())) {
5255 FI = FuncInfo.getArgumentFrameIndex(Arg);
5256 }
5257
5258 // llvm.dbg.addr is control dependent and always generates indirect
5259 // DBG_VALUE instructions. llvm.dbg.declare is handled as a frame index in
5260 // the MachineFunction variable table.
5261 if (FI != std::numeric_limits<int>::max()) {
5262 if (Intrinsic == Intrinsic::dbg_addr) {
5263 SDDbgValue *SDV = DAG.getFrameIndexDbgValue(
5264 Variable, Expression, FI, /*IsIndirect*/ true, dl, SDNodeOrder);
5265 DAG.AddDbgValue(SDV, getRoot().getNode(), isParameter);
5266 }
5267 return nullptr;
5268 }
5269
5270 SDValue &N = NodeMap[Address];
5271 if (!N.getNode() && isa<Argument>(Address))
5272 // Check unused arguments map.
5273 N = UnusedArgNodeMap[Address];
5274 SDDbgValue *SDV;
5275 if (N.getNode()) {
5276 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
5277 Address = BCI->getOperand(0);
5278 // Parameters are handled specially.
5279 auto FINode = dyn_cast<FrameIndexSDNode>(N.getNode());
5280 if (isParameter && FINode) {
5281 // Byval parameter. We have a frame index at this point.
5282 SDV =
5283 DAG.getFrameIndexDbgValue(Variable, Expression, FINode->getIndex(),
5284 /*IsIndirect*/ true, dl, SDNodeOrder);
5285 } else if (isa<Argument>(Address)) {
5286 // Address is an argument, so try to emit its dbg value using
5287 // virtual register info from the FuncInfo.ValueMap.
5288 EmitFuncArgumentDbgValue(Address, Variable, Expression, dl, true, N);
5289 return nullptr;
5290 } else {
5291 SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(),
5292 true, dl, SDNodeOrder);
5293 }
5294 DAG.AddDbgValue(SDV, N.getNode(), isParameter);
5295 } else {
5296 // If Address is an argument then try to emit its dbg value using
5297 // virtual register info from the FuncInfo.ValueMap.
5298 if (!EmitFuncArgumentDbgValue(Address, Variable, Expression, dl, true,
5299 N)) {
5300 LLVM_DEBUG(dbgs() << "Dropping debug info for " << DI << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << "Dropping debug info for " <<
DI << "\n"; } } while (false)
;
5301 }
5302 }
5303 return nullptr;
5304 }
5305 case Intrinsic::dbg_label: {
5306 const DbgLabelInst &DI = cast<DbgLabelInst>(I);
5307 DILabel *Label = DI.getLabel();
5308 assert(Label && "Missing label")((Label && "Missing label") ? static_cast<void>
(0) : __assert_fail ("Label && \"Missing label\"", "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 5308, __PRETTY_FUNCTION__))
;
5309
5310 SDDbgLabel *SDV;
5311 SDV = DAG.getDbgLabel(Label, dl, SDNodeOrder);
5312 DAG.AddDbgLabel(SDV);
5313 return nullptr;
5314 }
5315 case Intrinsic::dbg_value: {
5316 const DbgValueInst &DI = cast<DbgValueInst>(I);
5317 assert(DI.getVariable() && "Missing variable")((DI.getVariable() && "Missing variable") ? static_cast
<void> (0) : __assert_fail ("DI.getVariable() && \"Missing variable\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 5317, __PRETTY_FUNCTION__))
;
5318
5319 DILocalVariable *Variable = DI.getVariable();
5320 DIExpression *Expression = DI.getExpression();
5321 dropDanglingDebugInfo(Variable, Expression);
5322 const Value *V = DI.getValue();
5323 if (!V)
5324 return nullptr;
5325
5326 SDDbgValue *SDV;
5327 if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V) ||
5328 isa<ConstantPointerNull>(V)) {
5329 SDV = DAG.getConstantDbgValue(Variable, Expression, V, dl, SDNodeOrder);
5330 DAG.AddDbgValue(SDV, nullptr, false);
5331 return nullptr;
5332 }
5333
5334 // Do not use getValue() in here; we don't want to generate code at
5335 // this point if it hasn't been done yet.
5336 SDValue N = NodeMap[V];
5337 if (!N.getNode() && isa<Argument>(V)) // Check unused arguments map.
5338 N = UnusedArgNodeMap[V];
5339 if (N.getNode()) {
5340 if (EmitFuncArgumentDbgValue(V, Variable, Expression, dl, false, N))
5341 return nullptr;
5342 SDV = getDbgValue(N, Variable, Expression, dl, SDNodeOrder);
5343 DAG.AddDbgValue(SDV, N.getNode(), false);
5344 return nullptr;
5345 }
5346
5347 // PHI nodes have already been selected, so we should know which VReg that
5348 // is assigns to already.
5349 if (isa<PHINode>(V)) {
5350 auto VMI = FuncInfo.ValueMap.find(V);
5351 if (VMI != FuncInfo.ValueMap.end()) {
5352 unsigned Reg = VMI->second;
5353 // The PHI node may be split up into several MI PHI nodes (in
5354 // FunctionLoweringInfo::set).
5355 RegsForValue RFV(V->getContext(), TLI, DAG.getDataLayout(), Reg,
5356 V->getType(), None);
5357 if (RFV.occupiesMultipleRegs()) {
5358 unsigned Offset = 0;
5359 unsigned BitsToDescribe = 0;
5360 if (auto VarSize = Variable->getSizeInBits())
5361 BitsToDescribe = *VarSize;
5362 if (auto Fragment = Expression->getFragmentInfo())
5363 BitsToDescribe = Fragment->SizeInBits;
5364 for (auto RegAndSize : RFV.getRegsAndSizes()) {
5365 unsigned RegisterSize = RegAndSize.second;
5366 // Bail out if all bits are described already.
5367 if (Offset >= BitsToDescribe)
5368 break;
5369 unsigned FragmentSize = (Offset + RegisterSize > BitsToDescribe)
5370 ? BitsToDescribe - Offset
5371 : RegisterSize;
5372 auto FragmentExpr = DIExpression::createFragmentExpression(
5373 Expression, Offset, FragmentSize);
5374 if (!FragmentExpr)
5375 continue;
5376 SDV = DAG.getVRegDbgValue(Variable, *FragmentExpr, RegAndSize.first,
5377 false, dl, SDNodeOrder);
5378 DAG.AddDbgValue(SDV, nullptr, false);
5379 Offset += RegisterSize;
5380 }
5381 } else {
5382 SDV = DAG.getVRegDbgValue(Variable, Expression, Reg, false, dl,
5383 SDNodeOrder);
5384 DAG.AddDbgValue(SDV, nullptr, false);
5385 }
5386 return nullptr;
5387 }
5388 }
5389
5390 // TODO: When we get here we will either drop the dbg.value completely, or
5391 // we try to move it forward by letting it dangle for awhile. So we should
5392 // probably add an extra DbgValue to the DAG here, with a reference to
5393 // "noreg", to indicate that we have lost the debug location for the
5394 // variable.
5395
5396 if (!V->use_empty() ) {
5397 // Do not call getValue(V) yet, as we don't want to generate code.
5398 // Remember it for later.
5399 DanglingDebugInfoMap[V].emplace_back(&DI, dl, SDNodeOrder);
5400 return nullptr;
5401 }
5402
5403 LLVM_DEBUG(dbgs() << "Dropping debug location info for:\n " << DI << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << "Dropping debug location info for:\n "
<< DI << "\n"; } } while (false)
;
5404 LLVM_DEBUG(dbgs() << " Last seen at:\n " << *V << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << " Last seen at:\n " << *
V << "\n"; } } while (false)
;
5405 return nullptr;
5406 }
5407
5408 case Intrinsic::eh_typeid_for: {
5409 // Find the type id for the given typeinfo.
5410 GlobalValue *GV = ExtractTypeInfo(I.getArgOperand(0));
5411 unsigned TypeID = DAG.getMachineFunction().getTypeIDFor(GV);
5412 Res = DAG.getConstant(TypeID, sdl, MVT::i32);
5413 setValue(&I, Res);
5414 return nullptr;
5415 }
5416
5417 case Intrinsic::eh_return_i32:
5418 case Intrinsic::eh_return_i64:
5419 DAG.getMachineFunction().setCallsEHReturn(true);
5420 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, sdl,
5421 MVT::Other,
5422 getControlRoot(),
5423 getValue(I.getArgOperand(0)),
5424 getValue(I.getArgOperand(1))));
5425 return nullptr;
5426 case Intrinsic::eh_unwind_init:
5427 DAG.getMachineFunction().setCallsUnwindInit(true);
5428 return nullptr;
5429 case Intrinsic::eh_dwarf_cfa:
5430 setValue(&I, DAG.getNode(ISD::EH_DWARF_CFA, sdl,
5431 TLI.getPointerTy(DAG.getDataLayout()),
5432 getValue(I.getArgOperand(0))));
5433 return nullptr;
5434 case Intrinsic::eh_sjlj_callsite: {
5435 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5436 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0));
5437 assert(CI && "Non-constant call site value in eh.sjlj.callsite!")((CI && "Non-constant call site value in eh.sjlj.callsite!"
) ? static_cast<void> (0) : __assert_fail ("CI && \"Non-constant call site value in eh.sjlj.callsite!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 5437, __PRETTY_FUNCTION__))
;
5438 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!")((MMI.getCurrentCallSite() == 0 && "Overlapping call sites!"
) ? static_cast<void> (0) : __assert_fail ("MMI.getCurrentCallSite() == 0 && \"Overlapping call sites!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 5438, __PRETTY_FUNCTION__))
;
5439
5440 MMI.setCurrentCallSite(CI->getZExtValue());
5441 return nullptr;
5442 }
5443 case Intrinsic::eh_sjlj_functioncontext: {
5444 // Get and store the index of the function context.
5445 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
5446 AllocaInst *FnCtx =
5447 cast<AllocaInst>(I.getArgOperand(0)->stripPointerCasts());
5448 int FI = FuncInfo.StaticAllocaMap[FnCtx];
5449 MFI.setFunctionContextIndex(FI);
5450 return nullptr;
5451 }
5452 case Intrinsic::eh_sjlj_setjmp: {
5453 SDValue Ops[2];
5454 Ops[0] = getRoot();
5455 Ops[1] = getValue(I.getArgOperand(0));
5456 SDValue Op = DAG.getNode(ISD::EH_SJLJ_SETJMP, sdl,
5457 DAG.getVTList(MVT::i32, MVT::Other), Ops);
5458 setValue(&I, Op.getValue(0));
5459 DAG.setRoot(Op.getValue(1));
5460 return nullptr;
5461 }
5462 case Intrinsic::eh_sjlj_longjmp:
5463 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, sdl, MVT::Other,
5464 getRoot(), getValue(I.getArgOperand(0))));
5465 return nullptr;
5466 case Intrinsic::eh_sjlj_setup_dispatch:
5467 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_SETUP_DISPATCH, sdl, MVT::Other,
5468 getRoot()));
5469 return nullptr;
5470 case Intrinsic::masked_gather:
5471 visitMaskedGather(I);
5472 return nullptr;
5473 case Intrinsic::masked_load:
5474 visitMaskedLoad(I);
5475 return nullptr;
5476 case Intrinsic::masked_scatter:
5477 visitMaskedScatter(I);
5478 return nullptr;
5479 case Intrinsic::masked_store:
5480 visitMaskedStore(I);
5481 return nullptr;
5482 case Intrinsic::masked_expandload:
5483 visitMaskedLoad(I, true /* IsExpanding */);
5484 return nullptr;
5485 case Intrinsic::masked_compressstore:
5486 visitMaskedStore(I, true /* IsCompressing */);
5487 return nullptr;
5488 case Intrinsic::x86_mmx_pslli_w:
5489 case Intrinsic::x86_mmx_pslli_d:
5490 case Intrinsic::x86_mmx_pslli_q:
5491 case Intrinsic::x86_mmx_psrli_w:
5492 case Intrinsic::x86_mmx_psrli_d:
5493 case Intrinsic::x86_mmx_psrli_q:
5494 case Intrinsic::x86_mmx_psrai_w:
5495 case Intrinsic::x86_mmx_psrai_d: {
5496 SDValue ShAmt = getValue(I.getArgOperand(1));
5497 if (isa<ConstantSDNode>(ShAmt)) {
5498 visitTargetIntrinsic(I, Intrinsic);
5499 return nullptr;
5500 }
5501 unsigned NewIntrinsic = 0;
5502 EVT ShAmtVT = MVT::v2i32;
5503 switch (Intrinsic) {
5504 case Intrinsic::x86_mmx_pslli_w:
5505 NewIntrinsic = Intrinsic::x86_mmx_psll_w;
5506 break;
5507 case Intrinsic::x86_mmx_pslli_d:
5508 NewIntrinsic = Intrinsic::x86_mmx_psll_d;
5509 break;
5510 case Intrinsic::x86_mmx_pslli_q:
5511 NewIntrinsic = Intrinsic::x86_mmx_psll_q;
5512 break;
5513 case Intrinsic::x86_mmx_psrli_w:
5514 NewIntrinsic = Intrinsic::x86_mmx_psrl_w;
5515 break;
5516 case Intrinsic::x86_mmx_psrli_d:
5517 NewIntrinsic = Intrinsic::x86_mmx_psrl_d;
5518 break;
5519 case Intrinsic::x86_mmx_psrli_q:
5520 NewIntrinsic = Intrinsic::x86_mmx_psrl_q;
5521 break;
5522 case Intrinsic::x86_mmx_psrai_w:
5523 NewIntrinsic = Intrinsic::x86_mmx_psra_w;
5524 break;
5525 case Intrinsic::x86_mmx_psrai_d:
5526 NewIntrinsic = Intrinsic::x86_mmx_psra_d;
5527 break;
5528 default: llvm_unreachable("Impossible intrinsic")::llvm::llvm_unreachable_internal("Impossible intrinsic", "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 5528)
; // Can't reach here.
5529 }
5530
5531 // The vector shift intrinsics with scalars uses 32b shift amounts but
5532 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
5533 // to be zero.
5534 // We must do this early because v2i32 is not a legal type.
5535 SDValue ShOps[2];
5536 ShOps[0] = ShAmt;
5537 ShOps[1] = DAG.getConstant(0, sdl, MVT::i32);
5538 ShAmt = DAG.getBuildVector(ShAmtVT, sdl, ShOps);
5539 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
5540 ShAmt = DAG.getNode(ISD::BITCAST, sdl, DestVT, ShAmt);
5541 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, sdl, DestVT,
5542 DAG.getConstant(NewIntrinsic, sdl, MVT::i32),
5543 getValue(I.getArgOperand(0)), ShAmt);
5544 setValue(&I, Res);
5545 return nullptr;
5546 }
5547 case Intrinsic::powi:
5548 setValue(&I, ExpandPowI(sdl, getValue(I.getArgOperand(0)),
5549 getValue(I.getArgOperand(1)), DAG));
5550 return nullptr;
5551 case Intrinsic::log:
5552 setValue(&I, expandLog(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
5553 return nullptr;
5554 case Intrinsic::log2:
5555 setValue(&I, expandLog2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
5556 return nullptr;
5557 case Intrinsic::log10:
5558 setValue(&I, expandLog10(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
5559 return nullptr;
5560 case Intrinsic::exp:
5561 setValue(&I, expandExp(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
5562 return nullptr;
5563 case Intrinsic::exp2:
5564 setValue(&I, expandExp2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
5565 return nullptr;
5566 case Intrinsic::pow:
5567 setValue(&I, expandPow(sdl, getValue(I.getArgOperand(0)),
5568 getValue(I.getArgOperand(1)), DAG, TLI));
5569 return nullptr;
5570 case Intrinsic::sqrt:
5571 case Intrinsic::fabs:
5572 case Intrinsic::sin:
5573 case Intrinsic::cos:
5574 case Intrinsic::floor:
5575 case Intrinsic::ceil:
5576 case Intrinsic::trunc:
5577 case Intrinsic::rint:
5578 case Intrinsic::nearbyint:
5579 case Intrinsic::round:
5580 case Intrinsic::canonicalize: {
5581 unsigned Opcode;
5582 switch (Intrinsic) {
5583 default: llvm_unreachable("Impossible intrinsic")::llvm::llvm_unreachable_internal("Impossible intrinsic", "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 5583)
; // Can't reach here.
5584 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break;
5585 case Intrinsic::fabs: Opcode = ISD::FABS; break;
5586 case Intrinsic::sin: Opcode = ISD::FSIN; break;
5587 case Intrinsic::cos: Opcode = ISD::FCOS; break;
5588 case Intrinsic::floor: Opcode = ISD::FFLOOR; break;
5589 case Intrinsic::ceil: Opcode = ISD::FCEIL; break;
5590 case Intrinsic::trunc: Opcode = ISD::FTRUNC; break;
5591 case Intrinsic::rint: Opcode = ISD::FRINT; break;
5592 case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break;
5593 case Intrinsic::round: Opcode = ISD::FROUND; break;
5594 case Intrinsic::canonicalize: Opcode = ISD::FCANONICALIZE; break;
5595 }
5596
5597 setValue(&I, DAG.getNode(Opcode, sdl,
5598 getValue(I.getArgOperand(0)).getValueType(),
5599 getValue(I.getArgOperand(0))));
5600 return nullptr;
5601 }
5602 case Intrinsic::minnum: {
5603 auto VT = getValue(I.getArgOperand(0)).getValueType();
5604 unsigned Opc =
5605 I.hasNoNaNs() && TLI.isOperationLegalOrCustom(ISD::FMINIMUM, VT)
5606 ? ISD::FMINIMUM
5607 : ISD::FMINNUM;
5608 setValue(&I, DAG.getNode(Opc, sdl, VT,
5609 getValue(I.getArgOperand(0)),
5610 getValue(I.getArgOperand(1))));
5611 return nullptr;
5612 }
5613 case Intrinsic::maxnum: {
5614 auto VT = getValue(I.getArgOperand(0)).getValueType();
5615 unsigned Opc =
5616 I.hasNoNaNs() && TLI.isOperationLegalOrCustom(ISD::FMAXIMUM, VT)
5617 ? ISD::FMAXIMUM
5618 : ISD::FMAXNUM;
5619 setValue(&I, DAG.getNode(Opc, sdl, VT,
5620 getValue(I.getArgOperand(0)),
5621 getValue(I.getArgOperand(1))));
5622 return nullptr;
5623 }
5624 case Intrinsic::minimum:
5625 setValue(&I, DAG.getNode(ISD::FMINIMUM, sdl,
5626 getValue(I.getArgOperand(0)).getValueType(),
5627 getValue(I.getArgOperand(0)),
5628 getValue(I.getArgOperand(1))));
5629 return nullptr;
5630 case Intrinsic::maximum:
5631 setValue(&I, DAG.getNode(ISD::FMAXIMUM, sdl,
5632 getValue(I.getArgOperand(0)).getValueType(),
5633 getValue(I.getArgOperand(0)),
5634 getValue(I.getArgOperand(1))));
5635 return nullptr;
5636 case Intrinsic::copysign:
5637 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, sdl,
5638 getValue(I.getArgOperand(0)).getValueType(),
5639 getValue(I.getArgOperand(0)),
5640 getValue(I.getArgOperand(1))));
5641 return nullptr;
5642 case Intrinsic::fma:
5643 setValue(&I, DAG.getNode(ISD::FMA, sdl,
5644 getValue(I.getArgOperand(0)).getValueType(),
5645 getValue(I.getArgOperand(0)),
5646 getValue(I.getArgOperand(1)),
5647 getValue(I.getArgOperand(2))));
5648 return nullptr;
5649 case Intrinsic::experimental_constrained_fadd:
5650 case Intrinsic::experimental_constrained_fsub:
5651 case Intrinsic::experimental_constrained_fmul:
5652 case Intrinsic::experimental_constrained_fdiv:
5653 case Intrinsic::experimental_constrained_frem:
5654 case Intrinsic::experimental_constrained_fma:
5655 case Intrinsic::experimental_constrained_sqrt:
5656 case Intrinsic::experimental_constrained_pow:
5657 case Intrinsic::experimental_constrained_powi:
5658 case Intrinsic::experimental_constrained_sin:
5659 case Intrinsic::experimental_constrained_cos:
5660 case Intrinsic::experimental_constrained_exp:
5661 case Intrinsic::experimental_constrained_exp2:
5662 case Intrinsic::experimental_constrained_log:
5663 case Intrinsic::experimental_constrained_log10:
5664 case Intrinsic::experimental_constrained_log2:
5665 case Intrinsic::experimental_constrained_rint:
5666 case Intrinsic::experimental_constrained_nearbyint:
5667 case Intrinsic::experimental_constrained_maxnum:
5668 case Intrinsic::experimental_constrained_minnum:
5669 case Intrinsic::experimental_constrained_ceil:
5670 case Intrinsic::experimental_constrained_floor:
5671 case Intrinsic::experimental_constrained_round:
5672 case Intrinsic::experimental_constrained_trunc:
5673 visitConstrainedFPIntrinsic(cast<ConstrainedFPIntrinsic>(I));
5674 return nullptr;
5675 case Intrinsic::fmuladd: {
5676 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
5677 if (TM.Options.AllowFPOpFusion != FPOpFusion::Strict &&
5678 TLI.isFMAFasterThanFMulAndFAdd(VT)) {
5679 setValue(&I, DAG.getNode(ISD::FMA, sdl,
5680 getValue(I.getArgOperand(0)).getValueType(),
5681 getValue(I.getArgOperand(0)),
5682 getValue(I.getArgOperand(1)),
5683 getValue(I.getArgOperand(2))));
5684 } else {
5685 // TODO: Intrinsic calls should have fast-math-flags.
5686 SDValue Mul = DAG.getNode(ISD::FMUL, sdl,
5687 getValue(I.getArgOperand(0)).getValueType(),
5688 getValue(I.getArgOperand(0)),
5689 getValue(I.getArgOperand(1)));
5690 SDValue Add = DAG.getNode(ISD::FADD, sdl,
5691 getValue(I.getArgOperand(0)).getValueType(),
5692 Mul,
5693 getValue(I.getArgOperand(2)));
5694 setValue(&I, Add);
5695 }
5696 return nullptr;
5697 }
5698 case Intrinsic::convert_to_fp16:
5699 setValue(&I, DAG.getNode(ISD::BITCAST, sdl, MVT::i16,
5700 DAG.getNode(ISD::FP_ROUND, sdl, MVT::f16,
5701 getValue(I.getArgOperand(0)),
5702 DAG.getTargetConstant(0, sdl,
5703 MVT::i32))));
5704 return nullptr;
5705 case Intrinsic::convert_from_fp16:
5706 setValue(&I, DAG.getNode(ISD::FP_EXTEND, sdl,
5707 TLI.getValueType(DAG.getDataLayout(), I.getType()),
5708 DAG.getNode(ISD::BITCAST, sdl, MVT::f16,
5709 getValue(I.getArgOperand(0)))));
5710 return nullptr;
5711 case Intrinsic::pcmarker: {
5712 SDValue Tmp = getValue(I.getArgOperand(0));
5713 DAG.setRoot(DAG.getNode(ISD::PCMARKER, sdl, MVT::Other, getRoot(), Tmp));
5714 return nullptr;
5715 }
5716 case Intrinsic::readcyclecounter: {
5717 SDValue Op = getRoot();
5718 Res = DAG.getNode(ISD::READCYCLECOUNTER, sdl,
5719 DAG.getVTList(MVT::i64, MVT::Other), Op);
5720 setValue(&I, Res);
5721 DAG.setRoot(Res.getValue(1));
5722 return nullptr;
5723 }
5724 case Intrinsic::bitreverse:
5725 setValue(&I, DAG.getNode(ISD::BITREVERSE, sdl,
5726 getValue(I.getArgOperand(0)).getValueType(),
5727 getValue(I.getArgOperand(0))));
5728 return nullptr;
5729 case Intrinsic::bswap:
5730 setValue(&I, DAG.getNode(ISD::BSWAP, sdl,
5731 getValue(I.getArgOperand(0)).getValueType(),
5732 getValue(I.getArgOperand(0))));
5733 return nullptr;
5734 case Intrinsic::cttz: {
5735 SDValue Arg = getValue(I.getArgOperand(0));
5736 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
5737 EVT Ty = Arg.getValueType();
5738 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTTZ : ISD::CTTZ_ZERO_UNDEF,
5739 sdl, Ty, Arg));
5740 return nullptr;
5741 }
5742 case Intrinsic::ctlz: {
5743 SDValue Arg = getValue(I.getArgOperand(0));
5744 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
5745 EVT Ty = Arg.getValueType();
5746 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTLZ : ISD::CTLZ_ZERO_UNDEF,
5747 sdl, Ty, Arg));
5748 return nullptr;
5749 }
5750 case Intrinsic::ctpop: {
5751 SDValue Arg = getValue(I.getArgOperand(0));
5752 EVT Ty = Arg.getValueType();
5753 setValue(&I, DAG.getNode(ISD::CTPOP, sdl, Ty, Arg));
5754 return nullptr;
5755 }
5756 case Intrinsic::fshl:
5757 case Intrinsic::fshr: {
5758 bool IsFSHL = Intrinsic == Intrinsic::fshl;
5759 SDValue X = getValue(I.getArgOperand(0));
5760 SDValue Y = getValue(I.getArgOperand(1));
5761 SDValue Z = getValue(I.getArgOperand(2));
5762 EVT VT = X.getValueType();
5763 SDValue BitWidthC = DAG.getConstant(VT.getScalarSizeInBits(), sdl, VT);
5764 SDValue Zero = DAG.getConstant(0, sdl, VT);
5765 SDValue ShAmt = DAG.getNode(ISD::UREM, sdl, VT, Z, BitWidthC);
5766
5767 auto FunnelOpcode = IsFSHL ? ISD::FSHL : ISD::FSHR;
5768 if (TLI.isOperationLegalOrCustom(FunnelOpcode, VT)) {
5769 setValue(&I, DAG.getNode(FunnelOpcode, sdl, VT, X, Y, Z));
5770 return nullptr;
5771 }
5772
5773 // When X == Y, this is rotate. If the data type has a power-of-2 size, we
5774 // avoid the select that is necessary in the general case to filter out
5775 // the 0-shift possibility that leads to UB.
5776 if (X == Y && isPowerOf2_32(VT.getScalarSizeInBits())) {
5777 auto RotateOpcode = IsFSHL ? ISD::ROTL : ISD::ROTR;
5778 if (TLI.isOperationLegalOrCustom(RotateOpcode, VT)) {
5779 setValue(&I, DAG.getNode(RotateOpcode, sdl, VT, X, Z));
5780 return nullptr;
5781 }
5782
5783 // Some targets only rotate one way. Try the opposite direction.
5784 RotateOpcode = IsFSHL ? ISD::ROTR : ISD::ROTL;
5785 if (TLI.isOperationLegalOrCustom(RotateOpcode, VT)) {
5786 // Negate the shift amount because it is safe to ignore the high bits.
5787 SDValue NegShAmt = DAG.getNode(ISD::SUB, sdl, VT, Zero, Z);
5788 setValue(&I, DAG.getNode(RotateOpcode, sdl, VT, X, NegShAmt));
5789 return nullptr;
5790 }
5791
5792 // fshl (rotl): (X << (Z % BW)) | (X >> ((0 - Z) % BW))
5793 // fshr (rotr): (X << ((0 - Z) % BW)) | (X >> (Z % BW))
5794 SDValue NegZ = DAG.getNode(ISD::SUB, sdl, VT, Zero, Z);
5795 SDValue NShAmt = DAG.getNode(ISD::UREM, sdl, VT, NegZ, BitWidthC);
5796 SDValue ShX = DAG.getNode(ISD::SHL, sdl, VT, X, IsFSHL ? ShAmt : NShAmt);
5797 SDValue ShY = DAG.getNode(ISD::SRL, sdl, VT, X, IsFSHL ? NShAmt : ShAmt);
5798 setValue(&I, DAG.getNode(ISD::OR, sdl, VT, ShX, ShY));
5799 return nullptr;
5800 }
5801
5802 // fshl: (X << (Z % BW)) | (Y >> (BW - (Z % BW)))
5803 // fshr: (X << (BW - (Z % BW))) | (Y >> (Z % BW))
5804 SDValue InvShAmt = DAG.getNode(ISD::SUB, sdl, VT, BitWidthC, ShAmt);
5805 SDValue ShX = DAG.getNode(ISD::SHL, sdl, VT, X, IsFSHL ? ShAmt : InvShAmt);
5806 SDValue ShY = DAG.getNode(ISD::SRL, sdl, VT, Y, IsFSHL ? InvShAmt : ShAmt);
5807 SDValue Or = DAG.getNode(ISD::OR, sdl, VT, ShX, ShY);
5808
5809 // If (Z % BW == 0), then the opposite direction shift is shift-by-bitwidth,
5810 // and that is undefined. We must compare and select to avoid UB.
5811 EVT CCVT = MVT::i1;
5812 if (VT.isVector())
5813 CCVT = EVT::getVectorVT(*Context, CCVT, VT.getVectorNumElements());
5814
5815 // For fshl, 0-shift returns the 1st arg (X).
5816 // For fshr, 0-shift returns the 2nd arg (Y).
5817 SDValue IsZeroShift = DAG.getSetCC(sdl, CCVT, ShAmt, Zero, ISD::SETEQ);
5818 setValue(&I, DAG.getSelect(sdl, VT, IsZeroShift, IsFSHL ? X : Y, Or));
5819 return nullptr;
5820 }
5821 case Intrinsic::sadd_sat: {
5822 SDValue Op1 = getValue(I.getArgOperand(0));
5823 SDValue Op2 = getValue(I.getArgOperand(1));
5824 setValue(&I, DAG.getNode(ISD::SADDSAT, sdl, Op1.getValueType(), Op1, Op2));
5825 return nullptr;
5826 }
5827 case Intrinsic::uadd_sat: {
5828 SDValue Op1 = getValue(I.getArgOperand(0));
5829 SDValue Op2 = getValue(I.getArgOperand(1));
5830 setValue(&I, DAG.getNode(ISD::UADDSAT, sdl, Op1.getValueType(), Op1, Op2));
5831 return nullptr;
5832 }
5833 case Intrinsic::ssub_sat: {
5834 SDValue Op1 = getValue(I.getArgOperand(0));
5835 SDValue Op2 = getValue(I.getArgOperand(1));
5836 setValue(&I, DAG.getNode(ISD::SSUBSAT, sdl, Op1.getValueType(), Op1, Op2));
5837 return nullptr;
5838 }
5839 case Intrinsic::usub_sat: {
5840 SDValue Op1 = getValue(I.getArgOperand(0));
5841 SDValue Op2 = getValue(I.getArgOperand(1));
5842 setValue(&I, DAG.getNode(ISD::USUBSAT, sdl, Op1.getValueType(), Op1, Op2));
5843 return nullptr;
5844 }
5845 case Intrinsic::smul_fix: {
5846 SDValue Op1 = getValue(I.getArgOperand(0));
5847 SDValue Op2 = getValue(I.getArgOperand(1));
5848 SDValue Op3 = getValue(I.getArgOperand(2));
5849 setValue(&I,
5850 DAG.getNode(ISD::SMULFIX, sdl, Op1.getValueType(), Op1, Op2, Op3));
5851 return nullptr;
5852 }
5853 case Intrinsic::stacksave: {
5854 SDValue Op = getRoot();
5855 Res = DAG.getNode(
5856 ISD::STACKSAVE, sdl,
5857 DAG.getVTList(TLI.getPointerTy(DAG.getDataLayout()), MVT::Other), Op);
5858 setValue(&I, Res);
5859 DAG.setRoot(Res.getValue(1));
5860 return nullptr;
5861 }
5862 case Intrinsic::stackrestore:
5863 Res = getValue(I.getArgOperand(0));
5864 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, sdl, MVT::Other, getRoot(), Res));
5865 return nullptr;
5866 case Intrinsic::get_dynamic_area_offset: {
5867 SDValue Op = getRoot();
5868 EVT PtrTy = TLI.getPointerTy(DAG.getDataLayout());
5869 EVT ResTy = TLI.getValueType(DAG.getDataLayout(), I.getType());
5870 // Result type for @llvm.get.dynamic.area.offset should match PtrTy for
5871 // target.
5872 if (PtrTy != ResTy)
5873 report_fatal_error("Wrong result type for @llvm.get.dynamic.area.offset"
5874 " intrinsic!");
5875 Res = DAG.getNode(ISD::GET_DYNAMIC_AREA_OFFSET, sdl, DAG.getVTList(ResTy),
5876 Op);
5877 DAG.setRoot(Op);
5878 setValue(&I, Res);
5879 return nullptr;
5880 }
5881 case Intrinsic::stackguard: {
5882 EVT PtrTy = TLI.getPointerTy(DAG.getDataLayout());
5883 MachineFunction &MF = DAG.getMachineFunction();
5884 const Module &M = *MF.getFunction().getParent();
5885 SDValue Chain = getRoot();
5886 if (TLI.useLoadStackGuardNode()) {
5887 Res = getLoadStackGuard(DAG, sdl, Chain);
5888 } else {
5889 const Value *Global = TLI.getSDagStackGuard(M);
5890 unsigned Align = DL->getPrefTypeAlignment(Global->getType());
5891 Res = DAG.getLoad(PtrTy, sdl, Chain, getValue(Global),
5892 MachinePointerInfo(Global, 0), Align,
5893 MachineMemOperand::MOVolatile);
5894 }
5895 if (TLI.useStackGuardXorFP())
5896 Res = TLI.emitStackGuardXorFP(DAG, Res, sdl);
5897 DAG.setRoot(Chain);
5898 setValue(&I, Res);
5899 return nullptr;
5900 }
5901 case Intrinsic::stackprotector: {
5902 // Emit code into the DAG to store the stack guard onto the stack.
5903 MachineFunction &MF = DAG.getMachineFunction();
5904 MachineFrameInfo &MFI = MF.getFrameInfo();
5905 EVT PtrTy = TLI.getPointerTy(DAG.getDataLayout());
5906 SDValue Src, Chain = getRoot();
5907
5908 if (TLI.useLoadStackGuardNode())
5909 Src = getLoadStackGuard(DAG, sdl, Chain);
5910 else
5911 Src = getValue(I.getArgOperand(0)); // The guard's value.
5912
5913 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1));
5914
5915 int FI = FuncInfo.StaticAllocaMap[Slot];
5916 MFI.setStackProtectorIndex(FI);
5917
5918 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
5919
5920 // Store the stack protector onto the stack.
5921 Res = DAG.getStore(Chain, sdl, Src, FIN, MachinePointerInfo::getFixedStack(
5922 DAG.getMachineFunction(), FI),
5923 /* Alignment = */ 0, MachineMemOperand::MOVolatile);
5924 setValue(&I, Res);
5925 DAG.setRoot(Res);
5926 return nullptr;
5927 }
5928 case Intrinsic::objectsize: {
5929 // If we don't know by now, we're never going to know.
5930 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1));
5931
5932 assert(CI && "Non-constant type in __builtin_object_size?")((CI && "Non-constant type in __builtin_object_size?"
) ? static_cast<void> (0) : __assert_fail ("CI && \"Non-constant type in __builtin_object_size?\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 5932, __PRETTY_FUNCTION__))
;
5933
5934 SDValue Arg = getValue(I.getCalledValue());
5935 EVT Ty = Arg.getValueType();
5936
5937 if (CI->isZero())
5938 Res = DAG.getConstant(-1ULL, sdl, Ty);
5939 else
5940 Res = DAG.getConstant(0, sdl, Ty);
5941
5942 setValue(&I, Res);
5943 return nullptr;
5944 }
5945
5946 case Intrinsic::is_constant:
5947 // If this wasn't constant-folded away by now, then it's not a
5948 // constant.
5949 setValue(&I, DAG.getConstant(0, sdl, MVT::i1));
5950 return nullptr;
5951
5952 case Intrinsic::annotation:
5953 case Intrinsic::ptr_annotation:
5954 case Intrinsic::launder_invariant_group:
5955 case Intrinsic::strip_invariant_group:
5956 // Drop the intrinsic, but forward the value
5957 setValue(&I, getValue(I.getOperand(0)));
5958 return nullptr;
5959 case Intrinsic::assume:
5960 case Intrinsic::var_annotation:
5961 case Intrinsic::sideeffect:
5962 // Discard annotate attributes, assumptions, and artificial side-effects.
5963 return nullptr;
5964
5965 case Intrinsic::codeview_annotation: {
5966 // Emit a label associated with this metadata.
5967 MachineFunction &MF = DAG.getMachineFunction();
5968 MCSymbol *Label =
5969 MF.getMMI().getContext().createTempSymbol("annotation", true);
5970 Metadata *MD = cast<MetadataAsValue>(I.getArgOperand(0))->getMetadata();
5971 MF.addCodeViewAnnotation(Label, cast<MDNode>(MD));
5972 Res = DAG.getLabelNode(ISD::ANNOTATION_LABEL, sdl, getRoot(), Label);
5973 DAG.setRoot(Res);
5974 return nullptr;
5975 }
5976
5977 case Intrinsic::init_trampoline: {
5978 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts());
5979
5980 SDValue Ops[6];
5981 Ops[0] = getRoot();
5982 Ops[1] = getValue(I.getArgOperand(0));
5983 Ops[2] = getValue(I.getArgOperand(1));
5984 Ops[3] = getValue(I.getArgOperand(2));
5985 Ops[4] = DAG.getSrcValue(I.getArgOperand(0));
5986 Ops[5] = DAG.getSrcValue(F);
5987
5988 Res = DAG.getNode(ISD::INIT_TRAMPOLINE, sdl, MVT::Other, Ops);
5989
5990 DAG.setRoot(Res);
5991 return nullptr;
5992 }
5993 case Intrinsic::adjust_trampoline:
5994 setValue(&I, DAG.getNode(ISD::ADJUST_TRAMPOLINE, sdl,
5995 TLI.getPointerTy(DAG.getDataLayout()),
5996 getValue(I.getArgOperand(0))));
5997 return nullptr;
5998 case Intrinsic::gcroot: {
5999 assert(DAG.getMachineFunction().getFunction().hasGC() &&((DAG.getMachineFunction().getFunction().hasGC() && "only valid in functions with gc specified, enforced by Verifier"
) ? static_cast<void> (0) : __assert_fail ("DAG.getMachineFunction().getFunction().hasGC() && \"only valid in functions with gc specified, enforced by Verifier\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 6000, __PRETTY_FUNCTION__))
6000 "only valid in functions with gc specified, enforced by Verifier")((DAG.getMachineFunction().getFunction().hasGC() && "only valid in functions with gc specified, enforced by Verifier"
) ? static_cast<void> (0) : __assert_fail ("DAG.getMachineFunction().getFunction().hasGC() && \"only valid in functions with gc specified, enforced by Verifier\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 6000, __PRETTY_FUNCTION__))
;
6001 assert(GFI && "implied by previous")((GFI && "implied by previous") ? static_cast<void
> (0) : __assert_fail ("GFI && \"implied by previous\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 6001, __PRETTY_FUNCTION__))
;
6002 const Value *Alloca = I.getArgOperand(0)->stripPointerCasts();
6003 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1));
6004
6005 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
6006 GFI->addStackRoot(FI->getIndex(), TypeMap);
6007 return nullptr;
6008 }
6009 case Intrinsic::gcread:
6010 case Intrinsic::gcwrite:
6011 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!")::llvm::llvm_unreachable_internal("GC failed to lower gcread/gcwrite intrinsics!"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 6011)
;
6012 case Intrinsic::flt_rounds:
6013 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, sdl, MVT::i32));
6014 return nullptr;
6015
6016 case Intrinsic::expect:
6017 // Just replace __builtin_expect(exp, c) with EXP.
6018 setValue(&I, getValue(I.getArgOperand(0)));
6019 return nullptr;
6020
6021 case Intrinsic::debugtrap:
6022 case Intrinsic::trap: {
6023 StringRef TrapFuncName =
6024 I.getAttributes()
6025 .getAttribute(AttributeList::FunctionIndex, "trap-func-name")
6026 .getValueAsString();
6027 if (TrapFuncName.empty()) {
6028 ISD::NodeType Op = (Intrinsic == Intrinsic::trap) ?
6029 ISD::TRAP : ISD::DEBUGTRAP;
6030 DAG.setRoot(DAG.getNode(Op, sdl,MVT::Other, getRoot()));
6031 return nullptr;
6032 }
6033 TargetLowering::ArgListTy Args;
6034
6035 TargetLowering::CallLoweringInfo CLI(DAG);
6036 CLI.setDebugLoc(sdl).setChain(getRoot()).setLibCallee(
6037 CallingConv::C, I.getType(),
6038 DAG.getExternalSymbol(TrapFuncName.data(),
6039 TLI.getPointerTy(DAG.getDataLayout())),
6040 std::move(Args));
6041
6042 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
6043 DAG.setRoot(Result.second);
6044 return nullptr;
6045 }
6046
6047 case Intrinsic::uadd_with_overflow:
6048 case Intrinsic::sadd_with_overflow:
6049 case Intrinsic::usub_with_overflow:
6050 case Intrinsic::ssub_with_overflow:
6051 case Intrinsic::umul_with_overflow:
6052 case Intrinsic::smul_with_overflow: {
6053 ISD::NodeType Op;
6054 switch (Intrinsic) {
6055 default: llvm_unreachable("Impossible intrinsic")::llvm::llvm_unreachable_internal("Impossible intrinsic", "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 6055)
; // Can't reach here.
6056 case Intrinsic::uadd_with_overflow: Op = ISD::UADDO; break;
6057 case Intrinsic::sadd_with_overflow: Op = ISD::SADDO; break;
6058 case Intrinsic::usub_with_overflow: Op = ISD::USUBO; break;
6059 case Intrinsic::ssub_with_overflow: Op = ISD::SSUBO; break;
6060 case Intrinsic::umul_with_overflow: Op = ISD::UMULO; break;
6061 case Intrinsic::smul_with_overflow: Op = ISD::SMULO; break;
6062 }
6063 SDValue Op1 = getValue(I.getArgOperand(0));
6064 SDValue Op2 = getValue(I.getArgOperand(1));
6065
6066 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
6067 setValue(&I, DAG.getNode(Op, sdl, VTs, Op1, Op2));
6068 return nullptr;
6069 }
6070 case Intrinsic::prefetch: {
6071 SDValue Ops[5];
6072 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
6073 auto Flags = rw == 0 ? MachineMemOperand::MOLoad :MachineMemOperand::MOStore;
6074 Ops[0] = DAG.getRoot();
6075 Ops[1] = getValue(I.getArgOperand(0));
6076 Ops[2] = getValue(I.getArgOperand(1));
6077 Ops[3] = getValue(I.getArgOperand(2));
6078 Ops[4] = getValue(I.getArgOperand(3));
6079 SDValue Result = DAG.getMemIntrinsicNode(ISD::PREFETCH, sdl,
6080 DAG.getVTList(MVT::Other), Ops,
6081 EVT::getIntegerVT(*Context, 8),
6082 MachinePointerInfo(I.getArgOperand(0)),
6083 0, /* align */
6084 Flags);
6085
6086 // Chain the prefetch in parallell with any pending loads, to stay out of
6087 // the way of later optimizations.
6088 PendingLoads.push_back(Result);
6089 Result = getRoot();
6090 DAG.setRoot(Result);
6091 return nullptr;
6092 }
6093 case Intrinsic::lifetime_start:
6094 case Intrinsic::lifetime_end: {
6095 bool IsStart = (Intrinsic == Intrinsic::lifetime_start);
6096 // Stack coloring is not enabled in O0, discard region information.
6097 if (TM.getOptLevel() == CodeGenOpt::None)
6098 return nullptr;
6099
6100 SmallVector<Value *, 4> Allocas;
6101 GetUnderlyingObjects(I.getArgOperand(1), Allocas, *DL);
6102
6103 for (SmallVectorImpl<Value*>::iterator Object = Allocas.begin(),
6104 E = Allocas.end(); Object != E; ++Object) {
6105 AllocaInst *LifetimeObject = dyn_cast_or_null<AllocaInst>(*Object);
6106
6107 // Could not find an Alloca.
6108 if (!LifetimeObject)
6109 continue;
6110
6111 // First check that the Alloca is static, otherwise it won't have a
6112 // valid frame index.
6113 auto SI = FuncInfo.StaticAllocaMap.find(LifetimeObject);
6114 if (SI == FuncInfo.StaticAllocaMap.end())
6115 return nullptr;
6116
6117 int FI = SI->second;
6118
6119 SDValue Ops[2];
6120 Ops[0] = getRoot();
6121 Ops[1] =
6122 DAG.getFrameIndex(FI, TLI.getFrameIndexTy(DAG.getDataLayout()), true);
6123 unsigned Opcode = (IsStart ? ISD::LIFETIME_START : ISD::LIFETIME_END);
6124
6125 Res = DAG.getNode(Opcode, sdl, MVT::Other, Ops);
6126 DAG.setRoot(Res);
6127 }
6128 return nullptr;
6129 }
6130 case Intrinsic::invariant_start:
6131 // Discard region information.
6132 setValue(&I, DAG.getUNDEF(TLI.getPointerTy(DAG.getDataLayout())));
6133 return nullptr;
6134 case Intrinsic::invariant_end:
6135 // Discard region information.
6136 return nullptr;
6137 case Intrinsic::clear_cache:
6138 return TLI.getClearCacheBuiltinName();
6139 case Intrinsic::donothing:
6140 // ignore
6141 return nullptr;
6142 case Intrinsic::experimental_stackmap:
6143 visitStackmap(I);
6144 return nullptr;
6145 case Intrinsic::experimental_patchpoint_void:
6146 case Intrinsic::experimental_patchpoint_i64:
6147 visitPatchpoint(&I);
6148 return nullptr;
6149 case Intrinsic::experimental_gc_statepoint:
6150 LowerStatepoint(ImmutableStatepoint(&I));
6151 return nullptr;
6152 case Intrinsic::experimental_gc_result:
6153 visitGCResult(cast<GCResultInst>(I));
6154 return nullptr;
6155 case Intrinsic::experimental_gc_relocate:
6156 visitGCRelocate(cast<GCRelocateInst>(I));
6157 return nullptr;
6158 case Intrinsic::instrprof_increment:
6159 llvm_unreachable("instrprof failed to lower an increment")::llvm::llvm_unreachable_internal("instrprof failed to lower an increment"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 6159)
;
6160 case Intrinsic::instrprof_value_profile:
6161 llvm_unreachable("instrprof failed to lower a value profiling call")::llvm::llvm_unreachable_internal("instrprof failed to lower a value profiling call"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 6161)
;
6162 case Intrinsic::localescape: {
6163 MachineFunction &MF = DAG.getMachineFunction();
6164 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
6165
6166 // Directly emit some LOCAL_ESCAPE machine instrs. Label assignment emission
6167 // is the same on all targets.
6168 for (unsigned Idx = 0, E = I.getNumArgOperands(); Idx < E; ++Idx) {
6169 Value *Arg = I.getArgOperand(Idx)->stripPointerCasts();
6170 if (isa<ConstantPointerNull>(Arg))
6171 continue; // Skip null pointers. They represent a hole in index space.
6172 AllocaInst *Slot = cast<AllocaInst>(Arg);
6173 assert(FuncInfo.StaticAllocaMap.count(Slot) &&((FuncInfo.StaticAllocaMap.count(Slot) && "can only escape static allocas"
) ? static_cast<void> (0) : __assert_fail ("FuncInfo.StaticAllocaMap.count(Slot) && \"can only escape static allocas\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 6174, __PRETTY_FUNCTION__))
6174 "can only escape static allocas")((FuncInfo.StaticAllocaMap.count(Slot) && "can only escape static allocas"
) ? static_cast<void> (0) : __assert_fail ("FuncInfo.StaticAllocaMap.count(Slot) && \"can only escape static allocas\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 6174, __PRETTY_FUNCTION__))
;
6175 int FI = FuncInfo.StaticAllocaMap[Slot];
6176 MCSymbol *FrameAllocSym =
6177 MF.getMMI().getContext().getOrCreateFrameAllocSymbol(
6178 GlobalValue::dropLLVMManglingEscape(MF.getName()), Idx);
6179 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, dl,
6180 TII->get(TargetOpcode::LOCAL_ESCAPE))
6181 .addSym(FrameAllocSym)
6182 .addFrameIndex(FI);
6183 }
6184
6185 return nullptr;
6186 }
6187
6188 case Intrinsic::localrecover: {
6189 // i8* @llvm.localrecover(i8* %fn, i8* %fp, i32 %idx)
6190 MachineFunction &MF = DAG.getMachineFunction();
6191 MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout(), 0);
6192
6193 // Get the symbol that defines the frame offset.
6194 auto *Fn = cast<Function>(I.getArgOperand(0)->stripPointerCasts());
6195 auto *Idx = cast<ConstantInt>(I.getArgOperand(2));
6196 unsigned IdxVal =
6197 unsigned(Idx->getLimitedValue(std::numeric_limits<int>::max()));
6198 MCSymbol *FrameAllocSym =
6199 MF.getMMI().getContext().getOrCreateFrameAllocSymbol(
6200 GlobalValue::dropLLVMManglingEscape(Fn->getName()), IdxVal);
6201
6202 // Create a MCSymbol for the label to avoid any target lowering
6203 // that would make this PC relative.
6204 SDValue OffsetSym = DAG.getMCSymbol(FrameAllocSym, PtrVT);
6205 SDValue OffsetVal =
6206 DAG.getNode(ISD::LOCAL_RECOVER, sdl, PtrVT, OffsetSym);
6207
6208 // Add the offset to the FP.
6209 Value *FP = I.getArgOperand(1);
6210 SDValue FPVal = getValue(FP);
6211 SDValue Add = DAG.getNode(ISD::ADD, sdl, PtrVT, FPVal, OffsetVal);
6212 setValue(&I, Add);
6213
6214 return nullptr;
6215 }
6216
6217 case Intrinsic::eh_exceptionpointer:
6218 case Intrinsic::eh_exceptioncode: {
6219 // Get the exception pointer vreg, copy from it, and resize it to fit.
6220 const auto *CPI = cast<CatchPadInst>(I.getArgOperand(0));
6221 MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout());
6222 const TargetRegisterClass *PtrRC = TLI.getRegClassFor(PtrVT);
6223 unsigned VReg = FuncInfo.getCatchPadExceptionPointerVReg(CPI, PtrRC);
6224 SDValue N =
6225 DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(), VReg, PtrVT);
6226 if (Intrinsic == Intrinsic::eh_exceptioncode)
6227 N = DAG.getZExtOrTrunc(N, getCurSDLoc(), MVT::i32);
6228 setValue(&I, N);
6229 return nullptr;
6230 }
6231 case Intrinsic::xray_customevent: {
6232 // Here we want to make sure that the intrinsic behaves as if it has a
6233 // specific calling convention, and only for x86_64.
6234 // FIXME: Support other platforms later.
6235 const auto &Triple = DAG.getTarget().getTargetTriple();
6236 if (Triple.getArch() != Triple::x86_64 || !Triple.isOSLinux())
6237 return nullptr;
6238
6239 SDLoc DL = getCurSDLoc();
6240 SmallVector<SDValue, 8> Ops;
6241
6242 // We want to say that we always want the arguments in registers.
6243 SDValue LogEntryVal = getValue(I.getArgOperand(0));
6244 SDValue StrSizeVal = getValue(I.getArgOperand(1));
6245 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
6246 SDValue Chain = getRoot();
6247 Ops.push_back(LogEntryVal);
6248 Ops.push_back(StrSizeVal);
6249 Ops.push_back(Chain);
6250
6251 // We need to enforce the calling convention for the callsite, so that
6252 // argument ordering is enforced correctly, and that register allocation can
6253 // see that some registers may be assumed clobbered and have to preserve
6254 // them across calls to the intrinsic.
6255 MachineSDNode *MN = DAG.getMachineNode(TargetOpcode::PATCHABLE_EVENT_CALL,
6256 DL, NodeTys, Ops);
6257 SDValue patchableNode = SDValue(MN, 0);
6258 DAG.setRoot(patchableNode);
6259 setValue(&I, patchableNode);
6260 return nullptr;
6261 }
6262 case Intrinsic::xray_typedevent: {
6263 // Here we want to make sure that the intrinsic behaves as if it has a
6264 // specific calling convention, and only for x86_64.
6265 // FIXME: Support other platforms later.
6266 const auto &Triple = DAG.getTarget().getTargetTriple();
6267 if (Triple.getArch() != Triple::x86_64 || !Triple.isOSLinux())
6268 return nullptr;
6269
6270 SDLoc DL = getCurSDLoc();
6271 SmallVector<SDValue, 8> Ops;
6272
6273 // We want to say that we always want the arguments in registers.
6274 // It's unclear to me how manipulating the selection DAG here forces callers
6275 // to provide arguments in registers instead of on the stack.
6276 SDValue LogTypeId = getValue(I.getArgOperand(0));
6277 SDValue LogEntryVal = getValue(I.getArgOperand(1));
6278 SDValue StrSizeVal = getValue(I.getArgOperand(2));
6279 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
6280 SDValue Chain = getRoot();
6281 Ops.push_back(LogTypeId);
6282 Ops.push_back(LogEntryVal);
6283 Ops.push_back(StrSizeVal);
6284 Ops.push_back(Chain);
6285
6286 // We need to enforce the calling convention for the callsite, so that
6287 // argument ordering is enforced correctly, and that register allocation can
6288 // see that some registers may be assumed clobbered and have to preserve
6289 // them across calls to the intrinsic.
6290 MachineSDNode *MN = DAG.getMachineNode(
6291 TargetOpcode::PATCHABLE_TYPED_EVENT_CALL, DL, NodeTys, Ops);
6292 SDValue patchableNode = SDValue(MN, 0);
6293 DAG.setRoot(patchableNode);
6294 setValue(&I, patchableNode);
6295 return nullptr;
6296 }
6297 case Intrinsic::experimental_deoptimize:
6298 LowerDeoptimizeCall(&I);
6299 return nullptr;
6300
6301 case Intrinsic::experimental_vector_reduce_fadd:
6302 case Intrinsic::experimental_vector_reduce_fmul:
6303 case Intrinsic::experimental_vector_reduce_add:
6304 case Intrinsic::experimental_vector_reduce_mul:
6305 case Intrinsic::experimental_vector_reduce_and:
6306 case Intrinsic::experimental_vector_reduce_or:
6307 case Intrinsic::experimental_vector_reduce_xor:
6308 case Intrinsic::experimental_vector_reduce_smax:
6309 case Intrinsic::experimental_vector_reduce_smin:
6310 case Intrinsic::experimental_vector_reduce_umax:
6311 case Intrinsic::experimental_vector_reduce_umin:
6312 case Intrinsic::experimental_vector_reduce_fmax:
6313 case Intrinsic::experimental_vector_reduce_fmin:
6314 visitVectorReduce(I, Intrinsic);
6315 return nullptr;
6316
6317 case Intrinsic::icall_branch_funnel: {
6318 SmallVector<SDValue, 16> Ops;
6319 Ops.push_back(DAG.getRoot());
6320 Ops.push_back(getValue(I.getArgOperand(0)));
6321
6322 int64_t Offset;
6323 auto *Base = dyn_cast<GlobalObject>(GetPointerBaseWithConstantOffset(
6324 I.getArgOperand(1), Offset, DAG.getDataLayout()));
6325 if (!Base)
6326 report_fatal_error(
6327 "llvm.icall.branch.funnel operand must be a GlobalValue");
6328 Ops.push_back(DAG.getTargetGlobalAddress(Base, getCurSDLoc(), MVT::i64, 0));
6329
6330 struct BranchFunnelTarget {
6331 int64_t Offset;
6332 SDValue Target;
6333 };
6334 SmallVector<BranchFunnelTarget, 8> Targets;
6335
6336 for (unsigned Op = 1, N = I.getNumArgOperands(); Op != N; Op += 2) {
6337 auto *ElemBase = dyn_cast<GlobalObject>(GetPointerBaseWithConstantOffset(
6338 I.getArgOperand(Op), Offset, DAG.getDataLayout()));
6339 if (ElemBase != Base)
6340 report_fatal_error("all llvm.icall.branch.funnel operands must refer "
6341 "to the same GlobalValue");
6342
6343 SDValue Val = getValue(I.getArgOperand(Op + 1));
6344 auto *GA = dyn_cast<GlobalAddressSDNode>(Val);
6345 if (!GA)
6346 report_fatal_error(
6347 "llvm.icall.branch.funnel operand must be a GlobalValue");
6348 Targets.push_back({Offset, DAG.getTargetGlobalAddress(
6349 GA->getGlobal(), getCurSDLoc(),
6350 Val.getValueType(), GA->getOffset())});
6351 }
6352 llvm::sort(Targets,
6353 [](const BranchFunnelTarget &T1, const BranchFunnelTarget &T2) {
6354 return T1.Offset < T2.Offset;
6355 });
6356
6357 for (auto &T : Targets) {
6358 Ops.push_back(DAG.getTargetConstant(T.Offset, getCurSDLoc(), MVT::i32));
6359 Ops.push_back(T.Target);
6360 }
6361
6362 SDValue N(DAG.getMachineNode(TargetOpcode::ICALL_BRANCH_FUNNEL,
6363 getCurSDLoc(), MVT::Other, Ops),
6364 0);
6365 DAG.setRoot(N);
6366 setValue(&I, N);
6367 HasTailCall = true;
6368 return nullptr;
6369 }
6370
6371 case Intrinsic::wasm_landingpad_index:
6372 // Information this intrinsic contained has been transferred to
6373 // MachineFunction in SelectionDAGISel::PrepareEHLandingPad. We can safely
6374 // delete it now.
6375 return nullptr;
6376 }
6377}
6378
6379void SelectionDAGBuilder::visitConstrainedFPIntrinsic(
6380 const ConstrainedFPIntrinsic &FPI) {
6381 SDLoc sdl = getCurSDLoc();
6382 unsigned Opcode;
6383 switch (FPI.getIntrinsicID()) {
6384 default: llvm_unreachable("Impossible intrinsic")::llvm::llvm_unreachable_internal("Impossible intrinsic", "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 6384)
; // Can't reach here.
6385 case Intrinsic::experimental_constrained_fadd:
6386 Opcode = ISD::STRICT_FADD;
6387 break;
6388 case Intrinsic::experimental_constrained_fsub:
6389 Opcode = ISD::STRICT_FSUB;
6390 break;
6391 case Intrinsic::experimental_constrained_fmul:
6392 Opcode = ISD::STRICT_FMUL;
6393 break;
6394 case Intrinsic::experimental_constrained_fdiv:
6395 Opcode = ISD::STRICT_FDIV;
6396 break;
6397 case Intrinsic::experimental_constrained_frem:
6398 Opcode = ISD::STRICT_FREM;
6399 break;
6400 case Intrinsic::experimental_constrained_fma:
6401 Opcode = ISD::STRICT_FMA;
6402 break;
6403 case Intrinsic::experimental_constrained_sqrt:
6404 Opcode = ISD::STRICT_FSQRT;
6405 break;
6406 case Intrinsic::experimental_constrained_pow:
6407 Opcode = ISD::STRICT_FPOW;
6408 break;
6409 case Intrinsic::experimental_constrained_powi:
6410 Opcode = ISD::STRICT_FPOWI;
6411 break;
6412 case Intrinsic::experimental_constrained_sin:
6413 Opcode = ISD::STRICT_FSIN;
6414 break;
6415 case Intrinsic::experimental_constrained_cos:
6416 Opcode = ISD::STRICT_FCOS;
6417 break;
6418 case Intrinsic::experimental_constrained_exp:
6419 Opcode = ISD::STRICT_FEXP;
6420 break;
6421 case Intrinsic::experimental_constrained_exp2:
6422 Opcode = ISD::STRICT_FEXP2;
6423 break;
6424 case Intrinsic::experimental_constrained_log:
6425 Opcode = ISD::STRICT_FLOG;
6426 break;
6427 case Intrinsic::experimental_constrained_log10:
6428 Opcode = ISD::STRICT_FLOG10;
6429 break;
6430 case Intrinsic::experimental_constrained_log2:
6431 Opcode = ISD::STRICT_FLOG2;
6432 break;
6433 case Intrinsic::experimental_constrained_rint:
6434 Opcode = ISD::STRICT_FRINT;
6435 break;
6436 case Intrinsic::experimental_constrained_nearbyint:
6437 Opcode = ISD::STRICT_FNEARBYINT;
6438 break;
6439 case Intrinsic::experimental_constrained_maxnum:
6440 Opcode = ISD::STRICT_FMAXNUM;
6441 break;
6442 case Intrinsic::experimental_constrained_minnum:
6443 Opcode = ISD::STRICT_FMINNUM;
6444 break;
6445 case Intrinsic::experimental_constrained_ceil:
6446 Opcode = ISD::STRICT_FCEIL;
6447 break;
6448 case Intrinsic::experimental_constrained_floor:
6449 Opcode = ISD::STRICT_FFLOOR;
6450 break;
6451 case Intrinsic::experimental_constrained_round:
6452 Opcode = ISD::STRICT_FROUND;
6453 break;
6454 case Intrinsic::experimental_constrained_trunc:
6455 Opcode = ISD::STRICT_FTRUNC;
6456 break;
6457 }
6458 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6459 SDValue Chain = getRoot();
6460 SmallVector<EVT, 4> ValueVTs;
6461 ComputeValueVTs(TLI, DAG.getDataLayout(), FPI.getType(), ValueVTs);
6462 ValueVTs.push_back(MVT::Other); // Out chain
6463
6464 SDVTList VTs = DAG.getVTList(ValueVTs);
6465 SDValue Result;
6466 if (FPI.isUnaryOp())
6467 Result = DAG.getNode(Opcode, sdl, VTs,
6468 { Chain, getValue(FPI.getArgOperand(0)) });
6469 else if (FPI.isTernaryOp())
6470 Result = DAG.getNode(Opcode, sdl, VTs,
6471 { Chain, getValue(FPI.getArgOperand(0)),
6472 getValue(FPI.getArgOperand(1)),
6473 getValue(FPI.getArgOperand(2)) });
6474 else
6475 Result = DAG.getNode(Opcode, sdl, VTs,
6476 { Chain, getValue(FPI.getArgOperand(0)),
6477 getValue(FPI.getArgOperand(1)) });
6478
6479 assert(Result.getNode()->getNumValues() == 2)((Result.getNode()->getNumValues() == 2) ? static_cast<
void> (0) : __assert_fail ("Result.getNode()->getNumValues() == 2"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 6479, __PRETTY_FUNCTION__))
;
6480 SDValue OutChain = Result.getValue(1);
6481 DAG.setRoot(OutChain);
6482 SDValue FPResult = Result.getValue(0);
6483 setValue(&FPI, FPResult);
6484}
6485
6486std::pair<SDValue, SDValue>
6487SelectionDAGBuilder::lowerInvokable(TargetLowering::CallLoweringInfo &CLI,
6488 const BasicBlock *EHPadBB) {
6489 MachineFunction &MF = DAG.getMachineFunction();
6490 MachineModuleInfo &MMI = MF.getMMI();
6491 MCSymbol *BeginLabel = nullptr;
6492
6493 if (EHPadBB) {
6494 // Insert a label before the invoke call to mark the try range. This can be
6495 // used to detect deletion of the invoke via the MachineModuleInfo.
6496 BeginLabel = MMI.getContext().createTempSymbol();
6497
6498 // For SjLj, keep track of which landing pads go with which invokes
6499 // so as to maintain the ordering of pads in the LSDA.
6500 unsigned CallSiteIndex = MMI.getCurrentCallSite();
6501 if (CallSiteIndex) {
6502 MF.setCallSiteBeginLabel(BeginLabel, CallSiteIndex);
6503 LPadToCallSiteMap[FuncInfo.MBBMap[EHPadBB]].push_back(CallSiteIndex);
6504
6505 // Now that the call site is handled, stop tracking it.
6506 MMI.setCurrentCallSite(0);
6507 }
6508
6509 // Both PendingLoads and PendingExports must be flushed here;
6510 // this call might not return.
6511 (void)getRoot();
6512 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getControlRoot(), BeginLabel));
6513
6514 CLI.setChain(getRoot());
6515 }
6516 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6517 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
6518
6519 assert((CLI.IsTailCall || Result.second.getNode()) &&(((CLI.IsTailCall || Result.second.getNode()) && "Non-null chain expected with non-tail call!"
) ? static_cast<void> (0) : __assert_fail ("(CLI.IsTailCall || Result.second.getNode()) && \"Non-null chain expected with non-tail call!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 6520, __PRETTY_FUNCTION__))
6520 "Non-null chain expected with non-tail call!")(((CLI.IsTailCall || Result.second.getNode()) && "Non-null chain expected with non-tail call!"
) ? static_cast<void> (0) : __assert_fail ("(CLI.IsTailCall || Result.second.getNode()) && \"Non-null chain expected with non-tail call!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 6520, __PRETTY_FUNCTION__))
;
6521 assert((Result.second.getNode() || !Result.first.getNode()) &&(((Result.second.getNode() || !Result.first.getNode()) &&
"Null value expected with tail call!") ? static_cast<void
> (0) : __assert_fail ("(Result.second.getNode() || !Result.first.getNode()) && \"Null value expected with tail call!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 6522, __PRETTY_FUNCTION__))
6522 "Null value expected with tail call!")(((Result.second.getNode() || !Result.first.getNode()) &&
"Null value expected with tail call!") ? static_cast<void
> (0) : __assert_fail ("(Result.second.getNode() || !Result.first.getNode()) && \"Null value expected with tail call!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 6522, __PRETTY_FUNCTION__))
;
6523
6524 if (!Result.second.getNode()) {
6525 // As a special case, a null chain means that a tail call has been emitted
6526 // and the DAG root is already updated.
6527 HasTailCall = true;
6528
6529 // Since there's no actual continuation from this block, nothing can be
6530 // relying on us setting vregs for them.
6531 PendingExports.clear();
6532 } else {
6533 DAG.setRoot(Result.second);
6534 }
6535
6536 if (EHPadBB) {
6537 // Insert a label at the end of the invoke call to mark the try range. This
6538 // can be used to detect deletion of the invoke via the MachineModuleInfo.
6539 MCSymbol *EndLabel = MMI.getContext().createTempSymbol();
6540 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getRoot(), EndLabel));
6541
6542 // Inform MachineModuleInfo of range.
6543 auto Pers = classifyEHPersonality(FuncInfo.Fn->getPersonalityFn());
6544 // There is a platform (e.g. wasm) that uses funclet style IR but does not
6545 // actually use outlined funclets and their LSDA info style.
6546 if (MF.hasEHFunclets() && isFuncletEHPersonality(Pers)) {
6547 assert(CLI.CS)((CLI.CS) ? static_cast<void> (0) : __assert_fail ("CLI.CS"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 6547, __PRETTY_FUNCTION__))
;
6548 WinEHFuncInfo *EHInfo = DAG.getMachineFunction().getWinEHFuncInfo();
6549 EHInfo->addIPToStateRange(cast<InvokeInst>(CLI.CS.getInstruction()),
6550 BeginLabel, EndLabel);
6551 } else if (!isScopedEHPersonality(Pers)) {
6552 MF.addInvoke(FuncInfo.MBBMap[EHPadBB], BeginLabel, EndLabel);
6553 }
6554 }
6555
6556 return Result;
6557}
6558
6559void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee,
6560 bool isTailCall,
6561 const BasicBlock *EHPadBB) {
6562 auto &DL = DAG.getDataLayout();
6563 FunctionType *FTy = CS.getFunctionType();
6564 Type *RetTy = CS.getType();
6565
6566 TargetLowering::ArgListTy Args;
6567 Args.reserve(CS.arg_size());
6568
6569 const Value *SwiftErrorVal = nullptr;
6570 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6571
6572 // We can't tail call inside a function with a swifterror argument. Lowering
6573 // does not support this yet. It would have to move into the swifterror
6574 // register before the call.
6575 auto *Caller = CS.getInstruction()->getParent()->getParent();
6576 if (TLI.supportSwiftError() &&
6577 Caller->getAttributes().hasAttrSomewhere(Attribute::SwiftError))
6578 isTailCall = false;
6579
6580 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
6581 i != e; ++i) {
6582 TargetLowering::ArgListEntry Entry;
6583 const Value *V = *i;
6584
6585 // Skip empty types
6586 if (V->getType()->isEmptyTy())
6587 continue;
6588
6589 SDValue ArgNode = getValue(V);
6590 Entry.Node = ArgNode; Entry.Ty = V->getType();
6591
6592 Entry.setAttributes(&CS, i - CS.arg_begin());
6593
6594 // Use swifterror virtual register as input to the call.
6595 if (Entry.IsSwiftError && TLI.supportSwiftError()) {
6596 SwiftErrorVal = V;
6597 // We find the virtual register for the actual swifterror argument.
6598 // Instead of using the Value, we use the virtual register instead.
6599 Entry.Node = DAG.getRegister(FuncInfo
6600 .getOrCreateSwiftErrorVRegUseAt(
6601 CS.getInstruction(), FuncInfo.MBB, V)
6602 .first,
6603 EVT(TLI.getPointerTy(DL)));
6604 }
6605
6606 Args.push_back(Entry);
6607
6608 // If we have an explicit sret argument that is an Instruction, (i.e., it
6609 // might point to function-local memory), we can't meaningfully tail-call.
6610 if (Entry.IsSRet && isa<Instruction>(V))
6611 isTailCall = false;
6612 }
6613
6614 // Check if target-independent constraints permit a tail call here.
6615 // Target-dependent constraints are checked within TLI->LowerCallTo.
6616 if (isTailCall && !isInTailCallPosition(CS, DAG.getTarget()))
6617 isTailCall = false;
6618
6619 // Disable tail calls if there is an swifterror argument. Targets have not
6620 // been updated to support tail calls.
6621 if (TLI.supportSwiftError() && SwiftErrorVal)
6622 isTailCall = false;
6623
6624 TargetLowering::CallLoweringInfo CLI(DAG);
6625 CLI.setDebugLoc(getCurSDLoc())
6626 .setChain(getRoot())
6627 .setCallee(RetTy, FTy, Callee, std::move(Args), CS)
6628 .setTailCall(isTailCall)
6629 .setConvergent(CS.isConvergent());
6630 std::pair<SDValue, SDValue> Result = lowerInvokable(CLI, EHPadBB);
6631
6632 if (Result.first.getNode()) {
6633 const Instruction *Inst = CS.getInstruction();
6634 Result.first = lowerRangeToAssertZExt(DAG, *Inst, Result.first);
6635 setValue(Inst, Result.first);
6636 }
6637
6638 // The last element of CLI.InVals has the SDValue for swifterror return.
6639 // Here we copy it to a virtual register and update SwiftErrorMap for
6640 // book-keeping.
6641 if (SwiftErrorVal && TLI.supportSwiftError()) {
6642 // Get the last element of InVals.
6643 SDValue Src = CLI.InVals.back();
6644 unsigned VReg; bool CreatedVReg;
6645 std::tie(VReg, CreatedVReg) =
6646 FuncInfo.getOrCreateSwiftErrorVRegDefAt(CS.getInstruction());
6647 SDValue CopyNode = CLI.DAG.getCopyToReg(Result.second, CLI.DL, VReg, Src);
6648 // We update the virtual register for the actual swifterror argument.
6649 if (CreatedVReg)
6650 FuncInfo.setCurrentSwiftErrorVReg(FuncInfo.MBB, SwiftErrorVal, VReg);
6651 DAG.setRoot(CopyNode);
6652 }
6653}
6654
6655static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT,
6656 SelectionDAGBuilder &Builder) {
6657 // Check to see if this load can be trivially constant folded, e.g. if the
6658 // input is from a string literal.
6659 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) {
6660 // Cast pointer to the type we really want to load.
6661 Type *LoadTy =
6662 Type::getIntNTy(PtrVal->getContext(), LoadVT.getScalarSizeInBits());
6663 if (LoadVT.isVector())
6664 LoadTy = VectorType::get(LoadTy, LoadVT.getVectorNumElements());
6665
6666 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput),
6667 PointerType::getUnqual(LoadTy));
6668
6669 if (const Constant *LoadCst = ConstantFoldLoadFromConstPtr(
6670 const_cast<Constant *>(LoadInput), LoadTy, *Builder.DL))
6671 return Builder.getValue(LoadCst);
6672 }
6673
6674 // Otherwise, we have to emit the load. If the pointer is to unfoldable but
6675 // still constant memory, the input chain can be the entry node.
6676 SDValue Root;
6677 bool ConstantMemory = false;
6678
6679 // Do not serialize (non-volatile) loads of constant memory with anything.
6680 if (Builder.AA && Builder.AA->pointsToConstantMemory(PtrVal)) {
6681 Root = Builder.DAG.getEntryNode();
6682 ConstantMemory = true;
6683 } else {
6684 // Do not serialize non-volatile loads against each other.
6685 Root = Builder.DAG.getRoot();
6686 }
6687
6688 SDValue Ptr = Builder.getValue(PtrVal);
6689 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurSDLoc(), Root,
6690 Ptr, MachinePointerInfo(PtrVal),
6691 /* Alignment = */ 1);
6692
6693 if (!ConstantMemory)
6694 Builder.PendingLoads.push_back(LoadVal.getValue(1));
6695 return LoadVal;
6696}
6697
6698/// Record the value for an instruction that produces an integer result,
6699/// converting the type where necessary.
6700void SelectionDAGBuilder::processIntegerCallValue(const Instruction &I,
6701 SDValue Value,
6702 bool IsSigned) {
6703 EVT VT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
6704 I.getType(), true);
6705 if (IsSigned)
6706 Value = DAG.getSExtOrTrunc(Value, getCurSDLoc(), VT);
6707 else
6708 Value = DAG.getZExtOrTrunc(Value, getCurSDLoc(), VT);
6709 setValue(&I, Value);
6710}
6711
6712/// See if we can lower a memcmp call into an optimized form. If so, return
6713/// true and lower it. Otherwise return false, and it will be lowered like a
6714/// normal call.
6715/// The caller already checked that \p I calls the appropriate LibFunc with a
6716/// correct prototype.
6717bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) {
6718 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1);
6719 const Value *Size = I.getArgOperand(2);
6720 const ConstantInt *CSize = dyn_cast<ConstantInt>(Size);
6721 if (CSize && CSize->getZExtValue() == 0) {
6722 EVT CallVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
6723 I.getType(), true);
6724 setValue(&I, DAG.getConstant(0, getCurSDLoc(), CallVT));
6725 return true;
6726 }
6727
6728 const SelectionDAGTargetInfo &TSI = DAG.getSelectionDAGInfo();
6729 std::pair<SDValue, SDValue> Res = TSI.EmitTargetCodeForMemcmp(
6730 DAG, getCurSDLoc(), DAG.getRoot(), getValue(LHS), getValue(RHS),
6731 getValue(Size), MachinePointerInfo(LHS), MachinePointerInfo(RHS));
6732 if (Res.first.getNode()) {
6733 processIntegerCallValue(I, Res.first, true);
6734 PendingLoads.push_back(Res.second);
6735 return true;
6736 }
6737
6738 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0
6739 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0
6740 if (!CSize || !isOnlyUsedInZeroEqualityComparison(&I))
6741 return false;
6742
6743 // If the target has a fast compare for the given size, it will return a
6744 // preferred load type for that size. Require that the load VT is legal and
6745 // that the target supports unaligned loads of that type. Otherwise, return
6746 // INVALID.
6747 auto hasFastLoadsAndCompare = [&](unsigned NumBits) {
6748 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6749 MVT LVT = TLI.hasFastEqualityCompare(NumBits);
6750 if (LVT != MVT::INVALID_SIMPLE_VALUE_TYPE) {
6751 // TODO: Handle 5 byte compare as 4-byte + 1 byte.
6752 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads.
6753 // TODO: Check alignment of src and dest ptrs.
6754 unsigned DstAS = LHS->getType()->getPointerAddressSpace();
6755 unsigned SrcAS = RHS->getType()->getPointerAddressSpace();
6756 if (!TLI.isTypeLegal(LVT) ||
6757 !TLI.allowsMisalignedMemoryAccesses(LVT, SrcAS) ||
6758 !TLI.allowsMisalignedMemoryAccesses(LVT, DstAS))
6759 LVT = MVT::INVALID_SIMPLE_VALUE_TYPE;
6760 }
6761
6762 return LVT;
6763 };
6764
6765 // This turns into unaligned loads. We only do this if the target natively
6766 // supports the MVT we'll be loading or if it is small enough (<= 4) that
6767 // we'll only produce a small number of byte loads.
6768 MVT LoadVT;
6769 unsigned NumBitsToCompare = CSize->getZExtValue() * 8;
6770 switch (NumBitsToCompare) {
6771 default:
6772 return false;
6773 case 16:
6774 LoadVT = MVT::i16;
6775 break;
6776 case 32:
6777 LoadVT = MVT::i32;
6778 break;
6779 case 64:
6780 case 128:
6781 case 256:
6782 LoadVT = hasFastLoadsAndCompare(NumBitsToCompare);
6783 break;
6784 }
6785
6786 if (LoadVT == MVT::INVALID_SIMPLE_VALUE_TYPE)
6787 return false;
6788
6789 SDValue LoadL = getMemCmpLoad(LHS, LoadVT, *this);
6790 SDValue LoadR = getMemCmpLoad(RHS, LoadVT, *this);
6791
6792 // Bitcast to a wide integer type if the loads are vectors.
6793 if (LoadVT.isVector()) {
6794 EVT CmpVT = EVT::getIntegerVT(LHS->getContext(), LoadVT.getSizeInBits());
6795 LoadL = DAG.getBitcast(CmpVT, LoadL);
6796 LoadR = DAG.getBitcast(CmpVT, LoadR);
6797 }
6798
6799 SDValue Cmp = DAG.getSetCC(getCurSDLoc(), MVT::i1, LoadL, LoadR, ISD::SETNE);
6800 processIntegerCallValue(I, Cmp, false);
6801 return true;
6802}
6803
6804/// See if we can lower a memchr call into an optimized form. If so, return
6805/// true and lower it. Otherwise return false, and it will be lowered like a
6806/// normal call.
6807/// The caller already checked that \p I calls the appropriate LibFunc with a
6808/// correct prototype.
6809bool SelectionDAGBuilder::visitMemChrCall(const CallInst &I) {
6810 const Value *Src = I.getArgOperand(0);
6811 const Value *Char = I.getArgOperand(1);
6812 const Value *Length = I.getArgOperand(2);
6813
6814 const SelectionDAGTargetInfo &TSI = DAG.getSelectionDAGInfo();
6815 std::pair<SDValue, SDValue> Res =
6816 TSI.EmitTargetCodeForMemchr(DAG, getCurSDLoc(), DAG.getRoot(),
6817 getValue(Src), getValue(Char), getValue(Length),
6818 MachinePointerInfo(Src));
6819 if (Res.first.getNode()) {
6820 setValue(&I, Res.first);
6821 PendingLoads.push_back(Res.second);
6822 return true;
6823 }
6824
6825 return false;
6826}
6827
6828/// See if we can lower a mempcpy call into an optimized form. If so, return
6829/// true and lower it. Otherwise return false, and it will be lowered like a
6830/// normal call.
6831/// The caller already checked that \p I calls the appropriate LibFunc with a
6832/// correct prototype.
6833bool SelectionDAGBuilder::visitMemPCpyCall(const CallInst &I) {
6834 SDValue Dst = getValue(I.getArgOperand(0));
6835 SDValue Src = getValue(I.getArgOperand(1));
6836 SDValue Size = getValue(I.getArgOperand(2));
6837
6838 unsigned DstAlign = DAG.InferPtrAlignment(Dst);
6839 unsigned SrcAlign = DAG.InferPtrAlignment(Src);
6840 unsigned Align = std::min(DstAlign, SrcAlign);
6841 if (Align == 0) // Alignment of one or both could not be inferred.
6842 Align = 1; // 0 and 1 both specify no alignment, but 0 is reserved.
6843
6844 bool isVol = false;
6845 SDLoc sdl = getCurSDLoc();
6846
6847 // In the mempcpy context we need to pass in a false value for isTailCall
6848 // because the return pointer needs to be adjusted by the size of
6849 // the copied memory.
6850 SDValue MC = DAG.getMemcpy(getRoot(), sdl, Dst, Src, Size, Align, isVol,
6851 false, /*isTailCall=*/false,
6852 MachinePointerInfo(I.getArgOperand(0)),
6853 MachinePointerInfo(I.getArgOperand(1)));
6854 assert(MC.getNode() != nullptr &&((MC.getNode() != nullptr && "** memcpy should not be lowered as TailCall in mempcpy context **"
) ? static_cast<void> (0) : __assert_fail ("MC.getNode() != nullptr && \"** memcpy should not be lowered as TailCall in mempcpy context **\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 6855, __PRETTY_FUNCTION__))
6855 "** memcpy should not be lowered as TailCall in mempcpy context **")((MC.getNode() != nullptr && "** memcpy should not be lowered as TailCall in mempcpy context **"
) ? static_cast<void> (0) : __assert_fail ("MC.getNode() != nullptr && \"** memcpy should not be lowered as TailCall in mempcpy context **\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 6855, __PRETTY_FUNCTION__))
;
6856 DAG.setRoot(MC);
6857
6858 // Check if Size needs to be truncated or extended.
6859 Size = DAG.getSExtOrTrunc(Size, sdl, Dst.getValueType());
6860
6861 // Adjust return pointer to point just past the last dst byte.
6862 SDValue DstPlusSize = DAG.getNode(ISD::ADD, sdl, Dst.getValueType(),
6863 Dst, Size);
6864 setValue(&I, DstPlusSize);
6865 return true;
6866}
6867
6868/// See if we can lower a strcpy call into an optimized form. If so, return
6869/// true and lower it, otherwise return false and it will be lowered like a
6870/// normal call.
6871/// The caller already checked that \p I calls the appropriate LibFunc with a
6872/// correct prototype.
6873bool SelectionDAGBuilder::visitStrCpyCall(const CallInst &I, bool isStpcpy) {
6874 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
6875
6876 const SelectionDAGTargetInfo &TSI = DAG.getSelectionDAGInfo();
6877 std::pair<SDValue, SDValue> Res =
6878 TSI.EmitTargetCodeForStrcpy(DAG, getCurSDLoc(), getRoot(),
6879 getValue(Arg0), getValue(Arg1),
6880 MachinePointerInfo(Arg0),
6881 MachinePointerInfo(Arg1), isStpcpy);
6882 if (Res.first.getNode()) {
6883 setValue(&I, Res.first);
6884 DAG.setRoot(Res.second);
6885 return true;
6886 }
6887
6888 return false;
6889}
6890
6891/// See if we can lower a strcmp call into an optimized form. If so, return
6892/// true and lower it, otherwise return false and it will be lowered like a
6893/// normal call.
6894/// The caller already checked that \p I calls the appropriate LibFunc with a
6895/// correct prototype.
6896bool SelectionDAGBuilder::visitStrCmpCall(const CallInst &I) {
6897 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
6898
6899 const SelectionDAGTargetInfo &TSI = DAG.getSelectionDAGInfo();
6900 std::pair<SDValue, SDValue> Res =
6901 TSI.EmitTargetCodeForStrcmp(DAG, getCurSDLoc(), DAG.getRoot(),
6902 getValue(Arg0), getValue(Arg1),
6903 MachinePointerInfo(Arg0),
6904 MachinePointerInfo(Arg1));
6905 if (Res.first.getNode()) {
6906 processIntegerCallValue(I, Res.first, true);
6907 PendingLoads.push_back(Res.second);
6908 return true;
6909 }
6910
6911 return false;
6912}
6913
6914/// See if we can lower a strlen call into an optimized form. If so, return
6915/// true and lower it, otherwise return false and it will be lowered like a
6916/// normal call.
6917/// The caller already checked that \p I calls the appropriate LibFunc with a
6918/// correct prototype.
6919bool SelectionDAGBuilder::visitStrLenCall(const CallInst &I) {
6920 const Value *Arg0 = I.getArgOperand(0);
6921
6922 const SelectionDAGTargetInfo &TSI = DAG.getSelectionDAGInfo();
6923 std::pair<SDValue, SDValue> Res =
6924 TSI.EmitTargetCodeForStrlen(DAG, getCurSDLoc(), DAG.getRoot(),
6925 getValue(Arg0), MachinePointerInfo(Arg0));
6926 if (Res.first.getNode()) {
6927 processIntegerCallValue(I, Res.first, false);
6928 PendingLoads.push_back(Res.second);
6929 return true;
6930 }
6931
6932 return false;
6933}
6934
6935/// See if we can lower a strnlen call into an optimized form. If so, return
6936/// true and lower it, otherwise return false and it will be lowered like a
6937/// normal call.
6938/// The caller already checked that \p I calls the appropriate LibFunc with a
6939/// correct prototype.
6940bool SelectionDAGBuilder::visitStrNLenCall(const CallInst &I) {
6941 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
6942
6943 const SelectionDAGTargetInfo &TSI = DAG.getSelectionDAGInfo();
6944 std::pair<SDValue, SDValue> Res =
6945 TSI.EmitTargetCodeForStrnlen(DAG, getCurSDLoc(), DAG.getRoot(),
6946 getValue(Arg0), getValue(Arg1),
6947 MachinePointerInfo(Arg0));
6948 if (Res.first.getNode()) {
6949 processIntegerCallValue(I, Res.first, false);
6950 PendingLoads.push_back(Res.second);
6951 return true;
6952 }
6953
6954 return false;
6955}
6956
6957/// See if we can lower a unary floating-point operation into an SDNode with
6958/// the specified Opcode. If so, return true and lower it, otherwise return
6959/// false and it will be lowered like a normal call.
6960/// The caller already checked that \p I calls the appropriate LibFunc with a
6961/// correct prototype.
6962bool SelectionDAGBuilder::visitUnaryFloatCall(const CallInst &I,
6963 unsigned Opcode) {
6964 // We already checked this call's prototype; verify it doesn't modify errno.
6965 if (!I.onlyReadsMemory())
6966 return false;
6967
6968 SDValue Tmp = getValue(I.getArgOperand(0));
6969 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), Tmp.getValueType(), Tmp));
6970 return true;
6971}
6972
6973/// See if we can lower a binary floating-point operation into an SDNode with
6974/// the specified Opcode. If so, return true and lower it. Otherwise return
6975/// false, and it will be lowered like a normal call.
6976/// The caller already checked that \p I calls the appropriate LibFunc with a
6977/// correct prototype.
6978bool SelectionDAGBuilder::visitBinaryFloatCall(const CallInst &I,
6979 unsigned Opcode) {
6980 // We already checked this call's prototype; verify it doesn't modify errno.
6981 if (!I.onlyReadsMemory())
6982 return false;
6983
6984 SDValue Tmp0 = getValue(I.getArgOperand(0));
6985 SDValue Tmp1 = getValue(I.getArgOperand(1));
6986 EVT VT = Tmp0.getValueType();
6987 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), VT, Tmp0, Tmp1));
6988 return true;
6989}
6990
6991void SelectionDAGBuilder::visitCall(const CallInst &I) {
6992 // Handle inline assembly differently.
6993 if (isa<InlineAsm>(I.getCalledValue())) {
6994 visitInlineAsm(&I);
6995 return;
6996 }
6997
6998 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
6999 computeUsesVAFloatArgument(I, MMI);
7000
7001 const char *RenameFn = nullptr;
7002 if (Function *F = I.getCalledFunction()) {
7003 if (F->isDeclaration()) {
7004 // Is this an LLVM intrinsic or a target-specific intrinsic?
7005 unsigned IID = F->getIntrinsicID();
7006 if (!IID)
7007 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo())
7008 IID = II->getIntrinsicID(F);
7009
7010 if (IID) {
7011 RenameFn = visitIntrinsicCall(I, IID);
7012 if (!RenameFn)
7013 return;
7014 }
7015 }
7016
7017 // Check for well-known libc/libm calls. If the function is internal, it
7018 // can't be a library call. Don't do the check if marked as nobuiltin for
7019 // some reason or the call site requires strict floating point semantics.
7020 LibFunc Func;
7021 if (!I.isNoBuiltin() && !I.isStrictFP() && !F->hasLocalLinkage() &&
7022 F->hasName() && LibInfo->getLibFunc(*F, Func) &&
7023 LibInfo->hasOptimizedCodeGen(Func)) {
7024 switch (Func) {
7025 default: break;
7026 case LibFunc_copysign:
7027 case LibFunc_copysignf:
7028 case LibFunc_copysignl:
7029 // We already checked this call's prototype; verify it doesn't modify
7030 // errno.
7031 if (I.onlyReadsMemory()) {
7032 SDValue LHS = getValue(I.getArgOperand(0));
7033 SDValue RHS = getValue(I.getArgOperand(1));
7034 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurSDLoc(),
7035 LHS.getValueType(), LHS, RHS));
7036 return;
7037 }
7038 break;
7039 case LibFunc_fabs:
7040 case LibFunc_fabsf:
7041 case LibFunc_fabsl:
7042 if (visitUnaryFloatCall(I, ISD::FABS))
7043 return;
7044 break;
7045 case LibFunc_fmin:
7046 case LibFunc_fminf:
7047 case LibFunc_fminl:
7048 if (visitBinaryFloatCall(I, ISD::FMINNUM))
7049 return;
7050 break;
7051 case LibFunc_fmax:
7052 case LibFunc_fmaxf:
7053 case LibFunc_fmaxl:
7054 if (visitBinaryFloatCall(I, ISD::FMAXNUM))
7055 return;
7056 break;
7057 case LibFunc_sin:
7058 case LibFunc_sinf:
7059 case LibFunc_sinl:
7060 if (visitUnaryFloatCall(I, ISD::FSIN))
7061 return;
7062 break;
7063 case LibFunc_cos:
7064 case LibFunc_cosf:
7065 case LibFunc_cosl:
7066 if (visitUnaryFloatCall(I, ISD::FCOS))
7067 return;
7068 break;
7069 case LibFunc_sqrt:
7070 case LibFunc_sqrtf:
7071 case LibFunc_sqrtl:
7072 case LibFunc_sqrt_finite:
7073 case LibFunc_sqrtf_finite:
7074 case LibFunc_sqrtl_finite:
7075 if (visitUnaryFloatCall(I, ISD::FSQRT))
7076 return;
7077 break;
7078 case LibFunc_floor:
7079 case LibFunc_floorf:
7080 case LibFunc_floorl:
7081 if (visitUnaryFloatCall(I, ISD::FFLOOR))
7082 return;
7083 break;
7084 case LibFunc_nearbyint:
7085 case LibFunc_nearbyintf:
7086 case LibFunc_nearbyintl:
7087 if (visitUnaryFloatCall(I, ISD::FNEARBYINT))
7088 return;
7089 break;
7090 case LibFunc_ceil:
7091 case LibFunc_ceilf:
7092 case LibFunc_ceill:
7093 if (visitUnaryFloatCall(I, ISD::FCEIL))
7094 return;
7095 break;
7096 case LibFunc_rint:
7097 case LibFunc_rintf:
7098 case LibFunc_rintl:
7099 if (visitUnaryFloatCall(I, ISD::FRINT))
7100 return;
7101 break;
7102 case LibFunc_round:
7103 case LibFunc_roundf:
7104 case LibFunc_roundl:
7105 if (visitUnaryFloatCall(I, ISD::FROUND))
7106 return;
7107 break;
7108 case LibFunc_trunc:
7109 case LibFunc_truncf:
7110 case LibFunc_truncl:
7111 if (visitUnaryFloatCall(I, ISD::FTRUNC))
7112 return;
7113 break;
7114 case LibFunc_log2:
7115 case LibFunc_log2f:
7116 case LibFunc_log2l:
7117 if (visitUnaryFloatCall(I, ISD::FLOG2))
7118 return;
7119 break;
7120 case LibFunc_exp2:
7121 case LibFunc_exp2f:
7122 case LibFunc_exp2l:
7123 if (visitUnaryFloatCall(I, ISD::FEXP2))
7124 return;
7125 break;
7126 case LibFunc_memcmp:
7127 if (visitMemCmpCall(I))
7128 return;
7129 break;
7130 case LibFunc_mempcpy:
7131 if (visitMemPCpyCall(I))
7132 return;
7133 break;
7134 case LibFunc_memchr:
7135 if (visitMemChrCall(I))
7136 return;
7137 break;
7138 case LibFunc_strcpy:
7139 if (visitStrCpyCall(I, false))
7140 return;
7141 break;
7142 case LibFunc_stpcpy:
7143 if (visitStrCpyCall(I, true))
7144 return;
7145 break;
7146 case LibFunc_strcmp:
7147 if (visitStrCmpCall(I))
7148 return;
7149 break;
7150 case LibFunc_strlen:
7151 if (visitStrLenCall(I))
7152 return;
7153 break;
7154 case LibFunc_strnlen:
7155 if (visitStrNLenCall(I))
7156 return;
7157 break;
7158 }
7159 }
7160 }
7161
7162 SDValue Callee;
7163 if (!RenameFn)
7164 Callee = getValue(I.getCalledValue());
7165 else
7166 Callee = DAG.getExternalSymbol(
7167 RenameFn,
7168 DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout()));
7169
7170 // Deopt bundles are lowered in LowerCallSiteWithDeoptBundle, and we don't
7171 // have to do anything here to lower funclet bundles.
7172 assert(!I.hasOperandBundlesOtherThan(((!I.hasOperandBundlesOtherThan( {LLVMContext::OB_deopt, LLVMContext
::OB_funclet}) && "Cannot lower calls with arbitrary operand bundles!"
) ? static_cast<void> (0) : __assert_fail ("!I.hasOperandBundlesOtherThan( {LLVMContext::OB_deopt, LLVMContext::OB_funclet}) && \"Cannot lower calls with arbitrary operand bundles!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7174, __PRETTY_FUNCTION__))
7173 {LLVMContext::OB_deopt, LLVMContext::OB_funclet}) &&((!I.hasOperandBundlesOtherThan( {LLVMContext::OB_deopt, LLVMContext
::OB_funclet}) && "Cannot lower calls with arbitrary operand bundles!"
) ? static_cast<void> (0) : __assert_fail ("!I.hasOperandBundlesOtherThan( {LLVMContext::OB_deopt, LLVMContext::OB_funclet}) && \"Cannot lower calls with arbitrary operand bundles!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7174, __PRETTY_FUNCTION__))
7174 "Cannot lower calls with arbitrary operand bundles!")((!I.hasOperandBundlesOtherThan( {LLVMContext::OB_deopt, LLVMContext
::OB_funclet}) && "Cannot lower calls with arbitrary operand bundles!"
) ? static_cast<void> (0) : __assert_fail ("!I.hasOperandBundlesOtherThan( {LLVMContext::OB_deopt, LLVMContext::OB_funclet}) && \"Cannot lower calls with arbitrary operand bundles!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7174, __PRETTY_FUNCTION__))
;
7175
7176 if (I.countOperandBundlesOfType(LLVMContext::OB_deopt))
7177 LowerCallSiteWithDeoptBundle(&I, Callee, nullptr);
7178 else
7179 // Check if we can potentially perform a tail call. More detailed checking
7180 // is be done within LowerCallTo, after more information about the call is
7181 // known.
7182 LowerCallTo(&I, Callee, I.isTailCall());
7183}
7184
7185namespace {
7186
7187/// AsmOperandInfo - This contains information for each constraint that we are
7188/// lowering.
7189class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
7190public:
7191 /// CallOperand - If this is the result output operand or a clobber
7192 /// this is null, otherwise it is the incoming operand to the CallInst.
7193 /// This gets modified as the asm is processed.
7194 SDValue CallOperand;
7195
7196 /// AssignedRegs - If this is a register or register class operand, this
7197 /// contains the set of register corresponding to the operand.
7198 RegsForValue AssignedRegs;
7199
7200 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info)
7201 : TargetLowering::AsmOperandInfo(info), CallOperand(nullptr, 0) {
7202 }
7203
7204 /// Whether or not this operand accesses memory
7205 bool hasMemory(const TargetLowering &TLI) const {
7206 // Indirect operand accesses access memory.
7207 if (isIndirect)
7208 return true;
7209
7210 for (const auto &Code : Codes)
7211 if (TLI.getConstraintType(Code) == TargetLowering::C_Memory)
7212 return true;
7213
7214 return false;
7215 }
7216
7217 /// getCallOperandValEVT - Return the EVT of the Value* that this operand
7218 /// corresponds to. If there is no Value* for this operand, it returns
7219 /// MVT::Other.
7220 EVT getCallOperandValEVT(LLVMContext &Context, const TargetLowering &TLI,
7221 const DataLayout &DL) const {
7222 if (!CallOperandVal) return MVT::Other;
7223
7224 if (isa<BasicBlock>(CallOperandVal))
7225 return TLI.getPointerTy(DL);
7226
7227 llvm::Type *OpTy = CallOperandVal->getType();
7228
7229 // FIXME: code duplicated from TargetLowering::ParseConstraints().
7230 // If this is an indirect operand, the operand is a pointer to the
7231 // accessed type.
7232 if (isIndirect) {
7233 PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
7234 if (!PtrTy)
7235 report_fatal_error("Indirect operand for inline asm not a pointer!");
7236 OpTy = PtrTy->getElementType();
7237 }
7238
7239 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
7240 if (StructType *STy = dyn_cast<StructType>(OpTy))
7241 if (STy->getNumElements() == 1)
7242 OpTy = STy->getElementType(0);
7243
7244 // If OpTy is not a single value, it may be a struct/union that we
7245 // can tile with integers.
7246 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
7247 unsigned BitSize = DL.getTypeSizeInBits(OpTy);
7248 switch (BitSize) {
7249 default: break;
7250 case 1:
7251 case 8:
7252 case 16:
7253 case 32:
7254 case 64:
7255 case 128:
7256 OpTy = IntegerType::get(Context, BitSize);
7257 break;
7258 }
7259 }
7260
7261 return TLI.getValueType(DL, OpTy, true);
7262 }
7263};
7264
7265using SDISelAsmOperandInfoVector = SmallVector<SDISelAsmOperandInfo, 16>;
7266
7267} // end anonymous namespace
7268
7269/// Make sure that the output operand \p OpInfo and its corresponding input
7270/// operand \p MatchingOpInfo have compatible constraint types (otherwise error
7271/// out).
7272static void patchMatchingInput(const SDISelAsmOperandInfo &OpInfo,
7273 SDISelAsmOperandInfo &MatchingOpInfo,
7274 SelectionDAG &DAG) {
7275 if (OpInfo.ConstraintVT == MatchingOpInfo.ConstraintVT)
7276 return;
7277
7278 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
7279 const auto &TLI = DAG.getTargetLoweringInfo();
7280
7281 std::pair<unsigned, const TargetRegisterClass *> MatchRC =
7282 TLI.getRegForInlineAsmConstraint(TRI, OpInfo.ConstraintCode,
7283 OpInfo.ConstraintVT);
7284 std::pair<unsigned, const TargetRegisterClass *> InputRC =
7285 TLI.getRegForInlineAsmConstraint(TRI, MatchingOpInfo.ConstraintCode,
7286 MatchingOpInfo.ConstraintVT);
7287 if ((OpInfo.ConstraintVT.isInteger() !=
7288 MatchingOpInfo.ConstraintVT.isInteger()) ||
7289 (MatchRC.second != InputRC.second)) {
7290 // FIXME: error out in a more elegant fashion
7291 report_fatal_error("Unsupported asm: input constraint"
7292 " with a matching output constraint of"
7293 " incompatible type!");
7294 }
7295 MatchingOpInfo.ConstraintVT = OpInfo.ConstraintVT;
7296}
7297
7298/// Get a direct memory input to behave well as an indirect operand.
7299/// This may introduce stores, hence the need for a \p Chain.
7300/// \return The (possibly updated) chain.
7301static SDValue getAddressForMemoryInput(SDValue Chain, const SDLoc &Location,
7302 SDISelAsmOperandInfo &OpInfo,
7303 SelectionDAG &DAG) {
7304 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7305
7306 // If we don't have an indirect input, put it in the constpool if we can,
7307 // otherwise spill it to a stack slot.
7308 // TODO: This isn't quite right. We need to handle these according to
7309 // the addressing mode that the constraint wants. Also, this may take
7310 // an additional register for the computation and we don't want that
7311 // either.
7312
7313 // If the operand is a float, integer, or vector constant, spill to a
7314 // constant pool entry to get its address.
7315 const Value *OpVal = OpInfo.CallOperandVal;
7316 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
7317 isa<ConstantVector>(OpVal) || isa<ConstantDataVector>(OpVal)) {
7318 OpInfo.CallOperand = DAG.getConstantPool(
7319 cast<Constant>(OpVal), TLI.getPointerTy(DAG.getDataLayout()));
7320 return Chain;
7321 }
7322
7323 // Otherwise, create a stack slot and emit a store to it before the asm.
7324 Type *Ty = OpVal->getType();
7325 auto &DL = DAG.getDataLayout();
7326 uint64_t TySize = DL.getTypeAllocSize(Ty);
7327 unsigned Align = DL.getPrefTypeAlignment(Ty);
7328 MachineFunction &MF = DAG.getMachineFunction();
7329 int SSFI = MF.getFrameInfo().CreateStackObject(TySize, Align, false);
7330 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getFrameIndexTy(DL));
7331 Chain = DAG.getStore(Chain, Location, OpInfo.CallOperand, StackSlot,
7332 MachinePointerInfo::getFixedStack(MF, SSFI));
7333 OpInfo.CallOperand = StackSlot;
7334
7335 return Chain;
7336}
7337
7338/// GetRegistersForValue - Assign registers (virtual or physical) for the
7339/// specified operand. We prefer to assign virtual registers, to allow the
7340/// register allocator to handle the assignment process. However, if the asm
7341/// uses features that we can't model on machineinstrs, we have SDISel do the
7342/// allocation. This produces generally horrible, but correct, code.
7343///
7344/// OpInfo describes the operand
7345/// RefOpInfo describes the matching operand if any, the operand otherwise
7346static void GetRegistersForValue(SelectionDAG &DAG, const TargetLowering &TLI,
7347 const SDLoc &DL, SDISelAsmOperandInfo &OpInfo,
7348 SDISelAsmOperandInfo &RefOpInfo) {
7349 LLVMContext &Context = *DAG.getContext();
7350
7351 MachineFunction &MF = DAG.getMachineFunction();
7352 SmallVector<unsigned, 4> Regs;
7353 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
7354
7355 // If this is a constraint for a single physreg, or a constraint for a
7356 // register class, find it.
7357 std::pair<unsigned, const TargetRegisterClass *> PhysReg =
7358 TLI.getRegForInlineAsmConstraint(&TRI, RefOpInfo.ConstraintCode,
14
Value assigned to 'PhysReg.second'
7359 RefOpInfo.ConstraintVT);
7360
7361 unsigned NumRegs = 1;
7362 if (OpInfo.ConstraintVT != MVT::Other) {
15
Taking true branch
7363 // If this is an FP operand in an integer register (or visa versa), or more
7364 // generally if the operand value disagrees with the register class we plan
7365 // to stick it in, fix the operand type.
7366 //
7367 // If this is an input value, the bitcast to the new type is done now.
7368 // Bitcast for output value is done at the end of visitInlineAsm().
7369 if ((OpInfo.Type == InlineAsm::isOutput ||
16
Assuming the condition is false
18
Assuming pointer value is null
7370 OpInfo.Type == InlineAsm::isInput) &&
17
Assuming the condition is true
7371 PhysReg.second &&
19
Assuming the condition is false
7372 !TRI.isTypeLegalForClass(*PhysReg.second, OpInfo.ConstraintVT)) {
7373 // Try to convert to the first EVT that the reg class contains. If the
7374 // types are identical size, use a bitcast to convert (e.g. two differing
7375 // vector types). Note: output bitcast is done at the end of
7376 // visitInlineAsm().
7377 MVT RegVT = *TRI.legalclasstypes_begin(*PhysReg.second);
7378 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) {
7379 // Exclude indirect inputs while they are unsupported because the code
7380 // to perform the load is missing and thus OpInfo.CallOperand still
7381 // refers to the input address rather than the pointed-to value.
7382 if (OpInfo.Type == InlineAsm::isInput && !OpInfo.isIndirect)
7383 OpInfo.CallOperand =
7384 DAG.getNode(ISD::BITCAST, DL, RegVT, OpInfo.CallOperand);
7385 OpInfo.ConstraintVT = RegVT;
7386 // If the operand is an FP value and we want it in integer registers,
7387 // use the corresponding integer type. This turns an f64 value into
7388 // i64, which can be passed with two i32 values on a 32-bit machine.
7389 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
7390 RegVT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits());
7391 if (OpInfo.Type == InlineAsm::isInput)
7392 OpInfo.CallOperand =
7393 DAG.getNode(ISD::BITCAST, DL, RegVT, OpInfo.CallOperand);
7394 OpInfo.ConstraintVT = RegVT;
7395 }
7396 }
7397
7398 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
7399 }
7400
7401 // No need to allocate a matching input constraint since the constraint it's
7402 // matching to has already been allocated.
7403 if (OpInfo.isMatchingInputConstraint())
20
Assuming the condition is false
21
Taking false branch
7404 return;
7405
7406 MVT RegVT;
7407 EVT ValueVT = OpInfo.ConstraintVT;
7408
7409 // If this is a constraint for a specific physical register, like {r17},
7410 // assign it now.
7411 if (unsigned AssignedReg = PhysReg.first) {
22
Assuming 'AssignedReg' is not equal to 0
23
Taking true branch
7412 const TargetRegisterClass *RC = PhysReg.second;
24
'RC' initialized to a null pointer value
7413 if (OpInfo.ConstraintVT == MVT::Other)
25
Taking false branch
7414 ValueVT = *TRI.legalclasstypes_begin(*RC);
7415
7416 // Get the actual register value type. This is important, because the user
7417 // may have asked for (e.g.) the AX register in i32 type. We need to
7418 // remember that AX is actually i16 to get the right extension.
7419 RegVT = *TRI.legalclasstypes_begin(*RC);
26
Forming reference to null pointer
7420
7421 // This is an explicit reference to a physical register.
7422 Regs.push_back(AssignedReg);
7423
7424 // If this is an expanded reference, add the rest of the regs to Regs.
7425 if (NumRegs != 1) {
7426 TargetRegisterClass::iterator I = RC->begin();
7427 for (; *I != AssignedReg; ++I)
7428 assert(I != RC->end() && "Didn't find reg!")((I != RC->end() && "Didn't find reg!") ? static_cast
<void> (0) : __assert_fail ("I != RC->end() && \"Didn't find reg!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7428, __PRETTY_FUNCTION__))
;
7429
7430 // Already added the first reg.
7431 --NumRegs; ++I;
7432 for (; NumRegs; --NumRegs, ++I) {
7433 assert(I != RC->end() && "Ran out of registers to allocate!")((I != RC->end() && "Ran out of registers to allocate!"
) ? static_cast<void> (0) : __assert_fail ("I != RC->end() && \"Ran out of registers to allocate!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7433, __PRETTY_FUNCTION__))
;
7434 Regs.push_back(*I);
7435 }
7436 }
7437
7438 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
7439 return;
7440 }
7441
7442 // Otherwise, if this was a reference to an LLVM register class, create vregs
7443 // for this reference.
7444 if (const TargetRegisterClass *RC = PhysReg.second) {
7445 RegVT = *TRI.legalclasstypes_begin(*RC);
7446 if (OpInfo.ConstraintVT == MVT::Other)
7447 ValueVT = RegVT;
7448
7449 // Create the appropriate number of virtual registers.
7450 MachineRegisterInfo &RegInfo = MF.getRegInfo();
7451 for (; NumRegs; --NumRegs)
7452 Regs.push_back(RegInfo.createVirtualRegister(RC));
7453
7454 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
7455 return;
7456 }
7457
7458 // Otherwise, we couldn't allocate enough registers for this.
7459}
7460
7461static unsigned
7462findMatchingInlineAsmOperand(unsigned OperandNo,
7463 const std::vector<SDValue> &AsmNodeOperands) {
7464 // Scan until we find the definition we already emitted of this operand.
7465 unsigned CurOp = InlineAsm::Op_FirstOperand;
7466 for (; OperandNo; --OperandNo) {
7467 // Advance to the next operand.
7468 unsigned OpFlag =
7469 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
7470 assert((InlineAsm::isRegDefKind(OpFlag) ||(((InlineAsm::isRegDefKind(OpFlag) || InlineAsm::isRegDefEarlyClobberKind
(OpFlag) || InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?"
) ? static_cast<void> (0) : __assert_fail ("(InlineAsm::isRegDefKind(OpFlag) || InlineAsm::isRegDefEarlyClobberKind(OpFlag) || InlineAsm::isMemKind(OpFlag)) && \"Skipped past definitions?\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7473, __PRETTY_FUNCTION__))
7471 InlineAsm::isRegDefEarlyClobberKind(OpFlag) ||(((InlineAsm::isRegDefKind(OpFlag) || InlineAsm::isRegDefEarlyClobberKind
(OpFlag) || InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?"
) ? static_cast<void> (0) : __assert_fail ("(InlineAsm::isRegDefKind(OpFlag) || InlineAsm::isRegDefEarlyClobberKind(OpFlag) || InlineAsm::isMemKind(OpFlag)) && \"Skipped past definitions?\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7473, __PRETTY_FUNCTION__))
7472 InlineAsm::isMemKind(OpFlag)) &&(((InlineAsm::isRegDefKind(OpFlag) || InlineAsm::isRegDefEarlyClobberKind
(OpFlag) || InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?"
) ? static_cast<void> (0) : __assert_fail ("(InlineAsm::isRegDefKind(OpFlag) || InlineAsm::isRegDefEarlyClobberKind(OpFlag) || InlineAsm::isMemKind(OpFlag)) && \"Skipped past definitions?\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7473, __PRETTY_FUNCTION__))
7473 "Skipped past definitions?")(((InlineAsm::isRegDefKind(OpFlag) || InlineAsm::isRegDefEarlyClobberKind
(OpFlag) || InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?"
) ? static_cast<void> (0) : __assert_fail ("(InlineAsm::isRegDefKind(OpFlag) || InlineAsm::isRegDefEarlyClobberKind(OpFlag) || InlineAsm::isMemKind(OpFlag)) && \"Skipped past definitions?\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7473, __PRETTY_FUNCTION__))
;
7474 CurOp += InlineAsm::getNumOperandRegisters(OpFlag) + 1;
7475 }
7476 return CurOp;
7477}
7478
7479/// Fill \p Regs with \p NumRegs new virtual registers of type \p RegVT
7480/// \return true if it has succeeded, false otherwise
7481static bool createVirtualRegs(SmallVector<unsigned, 4> &Regs, unsigned NumRegs,
7482 MVT RegVT, SelectionDAG &DAG) {
7483 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7484 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
7485 for (unsigned i = 0, e = NumRegs; i != e; ++i) {
7486 if (const TargetRegisterClass *RC = TLI.getRegClassFor(RegVT))
7487 Regs.push_back(RegInfo.createVirtualRegister(RC));
7488 else
7489 return false;
7490 }
7491 return true;
7492}
7493
7494namespace {
7495
7496class ExtraFlags {
7497 unsigned Flags = 0;
7498
7499public:
7500 explicit ExtraFlags(ImmutableCallSite CS) {
7501 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
7502 if (IA->hasSideEffects())
7503 Flags |= InlineAsm::Extra_HasSideEffects;
7504 if (IA->isAlignStack())
7505 Flags |= InlineAsm::Extra_IsAlignStack;
7506 if (CS.isConvergent())
7507 Flags |= InlineAsm::Extra_IsConvergent;
7508 Flags |= IA->getDialect() * InlineAsm::Extra_AsmDialect;
7509 }
7510
7511 void update(const TargetLowering::AsmOperandInfo &OpInfo) {
7512 // Ideally, we would only check against memory constraints. However, the
7513 // meaning of an Other constraint can be target-specific and we can't easily
7514 // reason about it. Therefore, be conservative and set MayLoad/MayStore
7515 // for Other constraints as well.
7516 if (OpInfo.ConstraintType == TargetLowering::C_Memory ||
7517 OpInfo.ConstraintType == TargetLowering::C_Other) {
7518 if (OpInfo.Type == InlineAsm::isInput)
7519 Flags |= InlineAsm::Extra_MayLoad;
7520 else if (OpInfo.Type == InlineAsm::isOutput)
7521 Flags |= InlineAsm::Extra_MayStore;
7522 else if (OpInfo.Type == InlineAsm::isClobber)
7523 Flags |= (InlineAsm::Extra_MayLoad | InlineAsm::Extra_MayStore);
7524 }
7525 }
7526
7527 unsigned get() const { return Flags; }
7528};
7529
7530} // end anonymous namespace
7531
7532/// visitInlineAsm - Handle a call to an InlineAsm object.
7533void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
7534 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
7535
7536 /// ConstraintOperands - Information about all of the constraints.
7537 SDISelAsmOperandInfoVector ConstraintOperands;
7538
7539 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7540 TargetLowering::AsmOperandInfoVector TargetConstraints = TLI.ParseConstraints(
7541 DAG.getDataLayout(), DAG.getSubtarget().getRegisterInfo(), CS);
7542
7543 bool hasMemory = false;
7544
7545 // Remember the HasSideEffect, AlignStack, AsmDialect, MayLoad and MayStore
7546 ExtraFlags ExtraInfo(CS);
7547
7548 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
7549 unsigned ResNo = 0; // ResNo - The result number of the next output.
7550 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
1
Assuming 'i' is equal to 'e'
2
Loop condition is false. Execution continues on line 7604
7551 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i]));
7552 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
7553
7554 MVT OpVT = MVT::Other;
7555
7556 // Compute the value type for each operand.
7557 if (OpInfo.Type == InlineAsm::isInput ||
7558 (OpInfo.Type == InlineAsm::isOutput && OpInfo.isIndirect)) {
7559 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
7560
7561 // Process the call argument. BasicBlocks are labels, currently appearing
7562 // only in asm's.
7563 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
7564 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
7565 } else {
7566 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
7567 }
7568
7569 OpVT =
7570 OpInfo
7571 .getCallOperandValEVT(*DAG.getContext(), TLI, DAG.getDataLayout())
7572 .getSimpleVT();
7573 }
7574
7575 if (OpInfo.Type == InlineAsm::isOutput && !OpInfo.isIndirect) {
7576 // The return value of the call is this value. As such, there is no
7577 // corresponding argument.
7578 assert(!CS.getType()->isVoidTy() && "Bad inline asm!")((!CS.getType()->isVoidTy() && "Bad inline asm!") ?
static_cast<void> (0) : __assert_fail ("!CS.getType()->isVoidTy() && \"Bad inline asm!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7578, __PRETTY_FUNCTION__))
;
7579 if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
7580 OpVT = TLI.getSimpleValueType(DAG.getDataLayout(),
7581 STy->getElementType(ResNo));
7582 } else {
7583 assert(ResNo == 0 && "Asm only has one result!")((ResNo == 0 && "Asm only has one result!") ? static_cast
<void> (0) : __assert_fail ("ResNo == 0 && \"Asm only has one result!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7583, __PRETTY_FUNCTION__))
;
7584 OpVT = TLI.getSimpleValueType(DAG.getDataLayout(), CS.getType());
7585 }
7586 ++ResNo;
7587 }
7588
7589 OpInfo.ConstraintVT = OpVT;
7590
7591 if (!hasMemory)
7592 hasMemory = OpInfo.hasMemory(TLI);
7593
7594 // Determine if this InlineAsm MayLoad or MayStore based on the constraints.
7595 // FIXME: Could we compute this on OpInfo rather than TargetConstraints[i]?
7596 auto TargetConstraint = TargetConstraints[i];
7597
7598 // Compute the constraint code and ConstraintType to use.
7599 TLI.ComputeConstraintToUse(TargetConstraint, SDValue());
7600
7601 ExtraInfo.update(TargetConstraint);
7602 }
7603
7604 SDValue Chain, Flag;
7605
7606 // We won't need to flush pending loads if this asm doesn't touch
7607 // memory and is nonvolatile.
7608 if (hasMemory || IA->hasSideEffects())
3
Assuming the condition is false
4
Taking false branch
7609 Chain = getRoot();
7610 else
7611 Chain = DAG.getRoot();
7612
7613 // Second pass over the constraints: compute which constraint option to use
7614 // and assign registers to constraints that want a specific physreg.
7615 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5
Assuming 'i' is not equal to 'e'
6
Loop condition is true. Entering loop body
7616 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
7617
7618 // If this is an output operand with a matching input operand, look up the
7619 // matching input. If their types mismatch, e.g. one is an integer, the
7620 // other is floating point, or their sizes are different, flag it as an
7621 // error.
7622 if (OpInfo.hasMatchingInput()) {
7
Taking false branch
7623 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
7624 patchMatchingInput(OpInfo, Input, DAG);
7625 }
7626
7627 // Compute the constraint code and ConstraintType to use.
7628 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
7629
7630 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
8
Assuming the condition is false
7631 OpInfo.Type == InlineAsm::isClobber)
7632 continue;
7633
7634 // If this is a memory input, and if the operand is not indirect, do what we
7635 // need to provide an address for the memory input.
7636 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
7637 !OpInfo.isIndirect) {
7638 assert((OpInfo.isMultipleAlternative ||(((OpInfo.isMultipleAlternative || (OpInfo.Type == InlineAsm::
isInput)) && "Can only indirectify direct input operands!"
) ? static_cast<void> (0) : __assert_fail ("(OpInfo.isMultipleAlternative || (OpInfo.Type == InlineAsm::isInput)) && \"Can only indirectify direct input operands!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7640, __PRETTY_FUNCTION__))
7639 (OpInfo.Type == InlineAsm::isInput)) &&(((OpInfo.isMultipleAlternative || (OpInfo.Type == InlineAsm::
isInput)) && "Can only indirectify direct input operands!"
) ? static_cast<void> (0) : __assert_fail ("(OpInfo.isMultipleAlternative || (OpInfo.Type == InlineAsm::isInput)) && \"Can only indirectify direct input operands!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7640, __PRETTY_FUNCTION__))
7640 "Can only indirectify direct input operands!")(((OpInfo.isMultipleAlternative || (OpInfo.Type == InlineAsm::
isInput)) && "Can only indirectify direct input operands!"
) ? static_cast<void> (0) : __assert_fail ("(OpInfo.isMultipleAlternative || (OpInfo.Type == InlineAsm::isInput)) && \"Can only indirectify direct input operands!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7640, __PRETTY_FUNCTION__))
;
7641
7642 // Memory operands really want the address of the value.
7643 Chain = getAddressForMemoryInput(Chain, getCurSDLoc(), OpInfo, DAG);
7644
7645 // There is no longer a Value* corresponding to this operand.
7646 OpInfo.CallOperandVal = nullptr;
7647
7648 // It is now an indirect operand.
7649 OpInfo.isIndirect = true;
7650 }
7651
7652 // If this constraint is for a specific register, allocate it before
7653 // anything else.
7654 SDISelAsmOperandInfo &RefOpInfo =
7655 OpInfo.isMatchingInputConstraint()
9
Assuming the condition is false
10
'?' condition is false
7656 ? ConstraintOperands[OpInfo.getMatchedOperand()]
7657 : ConstraintOperands[i];
7658 if (RefOpInfo.ConstraintType == TargetLowering::C_Register)
11
Assuming the condition is true
12
Taking true branch
7659 GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo, RefOpInfo);
13
Calling 'GetRegistersForValue'
7660 }
7661
7662 // Third pass - Loop over all of the operands, assigning virtual or physregs
7663 // to register class operands.
7664 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
7665 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
7666 SDISelAsmOperandInfo &RefOpInfo =
7667 OpInfo.isMatchingInputConstraint()
7668 ? ConstraintOperands[OpInfo.getMatchedOperand()]
7669 : ConstraintOperands[i];
7670
7671 // C_Register operands have already been allocated, Other/Memory don't need
7672 // to be.
7673 if (RefOpInfo.ConstraintType == TargetLowering::C_RegisterClass)
7674 GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo, RefOpInfo);
7675 }
7676
7677 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
7678 std::vector<SDValue> AsmNodeOperands;
7679 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
7680 AsmNodeOperands.push_back(DAG.getTargetExternalSymbol(
7681 IA->getAsmString().c_str(), TLI.getPointerTy(DAG.getDataLayout())));
7682
7683 // If we have a !srcloc metadata node associated with it, we want to attach
7684 // this to the ultimately generated inline asm machineinstr. To do this, we
7685 // pass in the third operand as this (potentially null) inline asm MDNode.
7686 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc");
7687 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc));
7688
7689 // Remember the HasSideEffect, AlignStack, AsmDialect, MayLoad and MayStore
7690 // bits as operand 3.
7691 AsmNodeOperands.push_back(DAG.getTargetConstant(
7692 ExtraInfo.get(), getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout())));
7693
7694 // Loop over all of the inputs, copying the operand values into the
7695 // appropriate registers and processing the output regs.
7696 RegsForValue RetValRegs;
7697
7698 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
7699 std::vector<std::pair<RegsForValue, Value *>> IndirectStoresToEmit;
7700
7701 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
7702 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
7703
7704 switch (OpInfo.Type) {
7705 case InlineAsm::isOutput:
7706 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
7707 OpInfo.ConstraintType != TargetLowering::C_Register) {
7708 // Memory output, or 'other' output (e.g. 'X' constraint).
7709 assert(OpInfo.isIndirect && "Memory output must be indirect operand")((OpInfo.isIndirect && "Memory output must be indirect operand"
) ? static_cast<void> (0) : __assert_fail ("OpInfo.isIndirect && \"Memory output must be indirect operand\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7709, __PRETTY_FUNCTION__))
;
7710
7711 unsigned ConstraintID =
7712 TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
7713 assert(ConstraintID != InlineAsm::Constraint_Unknown &&((ConstraintID != InlineAsm::Constraint_Unknown && "Failed to convert memory constraint code to constraint id."
) ? static_cast<void> (0) : __assert_fail ("ConstraintID != InlineAsm::Constraint_Unknown && \"Failed to convert memory constraint code to constraint id.\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7714, __PRETTY_FUNCTION__))
7714 "Failed to convert memory constraint code to constraint id.")((ConstraintID != InlineAsm::Constraint_Unknown && "Failed to convert memory constraint code to constraint id."
) ? static_cast<void> (0) : __assert_fail ("ConstraintID != InlineAsm::Constraint_Unknown && \"Failed to convert memory constraint code to constraint id.\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7714, __PRETTY_FUNCTION__))
;
7715
7716 // Add information to the INLINEASM node to know about this output.
7717 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
7718 OpFlags = InlineAsm::getFlagWordForMem(OpFlags, ConstraintID);
7719 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags, getCurSDLoc(),
7720 MVT::i32));
7721 AsmNodeOperands.push_back(OpInfo.CallOperand);
7722 break;
7723 }
7724
7725 // Otherwise, this is a register or register class output.
7726
7727 // Copy the output from the appropriate register. Find a register that
7728 // we can use.
7729 if (OpInfo.AssignedRegs.Regs.empty()) {
7730 emitInlineAsmError(
7731 CS, "couldn't allocate output register for constraint '" +
7732 Twine(OpInfo.ConstraintCode) + "'");
7733 return;
7734 }
7735
7736 // If this is an indirect operand, store through the pointer after the
7737 // asm.
7738 if (OpInfo.isIndirect) {
7739 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
7740 OpInfo.CallOperandVal));
7741 } else {
7742 // This is the result value of the call.
7743 assert(!CS.getType()->isVoidTy() && "Bad inline asm!")((!CS.getType()->isVoidTy() && "Bad inline asm!") ?
static_cast<void> (0) : __assert_fail ("!CS.getType()->isVoidTy() && \"Bad inline asm!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7743, __PRETTY_FUNCTION__))
;
7744 // Concatenate this output onto the outputs list.
7745 RetValRegs.append(OpInfo.AssignedRegs);
7746 }
7747
7748 // Add information to the INLINEASM node to know that this register is
7749 // set.
7750 OpInfo.AssignedRegs
7751 .AddInlineAsmOperands(OpInfo.isEarlyClobber
7752 ? InlineAsm::Kind_RegDefEarlyClobber
7753 : InlineAsm::Kind_RegDef,
7754 false, 0, getCurSDLoc(), DAG, AsmNodeOperands);
7755 break;
7756
7757 case InlineAsm::isInput: {
7758 SDValue InOperandVal = OpInfo.CallOperand;
7759
7760 if (OpInfo.isMatchingInputConstraint()) {
7761 // If this is required to match an output register we have already set,
7762 // just use its register.
7763 auto CurOp = findMatchingInlineAsmOperand(OpInfo.getMatchedOperand(),
7764 AsmNodeOperands);
7765 unsigned OpFlag =
7766 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
7767 if (InlineAsm::isRegDefKind(OpFlag) ||
7768 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) {
7769 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
7770 if (OpInfo.isIndirect) {
7771 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c
7772 emitInlineAsmError(CS, "inline asm not supported yet:"
7773 " don't know how to handle tied "
7774 "indirect register inputs");
7775 return;
7776 }
7777
7778 MVT RegVT = AsmNodeOperands[CurOp+1].getSimpleValueType();
7779 SmallVector<unsigned, 4> Regs;
7780
7781 if (!createVirtualRegs(Regs,
7782 InlineAsm::getNumOperandRegisters(OpFlag),
7783 RegVT, DAG)) {
7784 emitInlineAsmError(CS, "inline asm error: This value type register "
7785 "class is not natively supported!");
7786 return;
7787 }
7788
7789 RegsForValue MatchedRegs(Regs, RegVT, InOperandVal.getValueType());
7790
7791 SDLoc dl = getCurSDLoc();
7792 // Use the produced MatchedRegs object to
7793 MatchedRegs.getCopyToRegs(InOperandVal, DAG, dl, Chain, &Flag,
7794 CS.getInstruction());
7795 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse,
7796 true, OpInfo.getMatchedOperand(), dl,
7797 DAG, AsmNodeOperands);
7798 break;
7799 }
7800
7801 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!")((InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!"
) ? static_cast<void> (0) : __assert_fail ("InlineAsm::isMemKind(OpFlag) && \"Unknown matching constraint!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7801, __PRETTY_FUNCTION__))
;
7802 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 &&((InlineAsm::getNumOperandRegisters(OpFlag) == 1 && "Unexpected number of operands"
) ? static_cast<void> (0) : __assert_fail ("InlineAsm::getNumOperandRegisters(OpFlag) == 1 && \"Unexpected number of operands\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7803, __PRETTY_FUNCTION__))
7803 "Unexpected number of operands")((InlineAsm::getNumOperandRegisters(OpFlag) == 1 && "Unexpected number of operands"
) ? static_cast<void> (0) : __assert_fail ("InlineAsm::getNumOperandRegisters(OpFlag) == 1 && \"Unexpected number of operands\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7803, __PRETTY_FUNCTION__))
;
7804 // Add information to the INLINEASM node to know about this input.
7805 // See InlineAsm.h isUseOperandTiedToDef.
7806 OpFlag = InlineAsm::convertMemFlagWordToMatchingFlagWord(OpFlag);
7807 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag,
7808 OpInfo.getMatchedOperand());
7809 AsmNodeOperands.push_back(DAG.getTargetConstant(
7810 OpFlag, getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout())));
7811 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
7812 break;
7813 }
7814
7815 // Treat indirect 'X' constraint as memory.
7816 if (OpInfo.ConstraintType == TargetLowering::C_Other &&
7817 OpInfo.isIndirect)
7818 OpInfo.ConstraintType = TargetLowering::C_Memory;
7819
7820 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
7821 std::vector<SDValue> Ops;
7822 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode,
7823 Ops, DAG);
7824 if (Ops.empty()) {
7825 emitInlineAsmError(CS, "invalid operand for inline asm constraint '" +
7826 Twine(OpInfo.ConstraintCode) + "'");
7827 return;
7828 }
7829
7830 // Add information to the INLINEASM node to know about this input.
7831 unsigned ResOpType =
7832 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
7833 AsmNodeOperands.push_back(DAG.getTargetConstant(
7834 ResOpType, getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout())));
7835 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
7836 break;
7837 }
7838
7839 if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
7840 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!")((OpInfo.isIndirect && "Operand must be indirect to be a mem!"
) ? static_cast<void> (0) : __assert_fail ("OpInfo.isIndirect && \"Operand must be indirect to be a mem!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7840, __PRETTY_FUNCTION__))
;
7841 assert(InOperandVal.getValueType() ==((InOperandVal.getValueType() == TLI.getPointerTy(DAG.getDataLayout
()) && "Memory operands expect pointer values") ? static_cast
<void> (0) : __assert_fail ("InOperandVal.getValueType() == TLI.getPointerTy(DAG.getDataLayout()) && \"Memory operands expect pointer values\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7843, __PRETTY_FUNCTION__))
7842 TLI.getPointerTy(DAG.getDataLayout()) &&((InOperandVal.getValueType() == TLI.getPointerTy(DAG.getDataLayout
()) && "Memory operands expect pointer values") ? static_cast
<void> (0) : __assert_fail ("InOperandVal.getValueType() == TLI.getPointerTy(DAG.getDataLayout()) && \"Memory operands expect pointer values\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7843, __PRETTY_FUNCTION__))
7843 "Memory operands expect pointer values")((InOperandVal.getValueType() == TLI.getPointerTy(DAG.getDataLayout
()) && "Memory operands expect pointer values") ? static_cast
<void> (0) : __assert_fail ("InOperandVal.getValueType() == TLI.getPointerTy(DAG.getDataLayout()) && \"Memory operands expect pointer values\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7843, __PRETTY_FUNCTION__))
;
7844
7845 unsigned ConstraintID =
7846 TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
7847 assert(ConstraintID != InlineAsm::Constraint_Unknown &&((ConstraintID != InlineAsm::Constraint_Unknown && "Failed to convert memory constraint code to constraint id."
) ? static_cast<void> (0) : __assert_fail ("ConstraintID != InlineAsm::Constraint_Unknown && \"Failed to convert memory constraint code to constraint id.\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7848, __PRETTY_FUNCTION__))
7848 "Failed to convert memory constraint code to constraint id.")((ConstraintID != InlineAsm::Constraint_Unknown && "Failed to convert memory constraint code to constraint id."
) ? static_cast<void> (0) : __assert_fail ("ConstraintID != InlineAsm::Constraint_Unknown && \"Failed to convert memory constraint code to constraint id.\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7848, __PRETTY_FUNCTION__))
;
7849
7850 // Add information to the INLINEASM node to know about this input.
7851 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
7852 ResOpType = InlineAsm::getFlagWordForMem(ResOpType, ConstraintID);
7853 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
7854 getCurSDLoc(),
7855 MVT::i32));
7856 AsmNodeOperands.push_back(InOperandVal);
7857 break;
7858 }
7859
7860 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||(((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
OpInfo.ConstraintType == TargetLowering::C_Register) &&
"Unknown constraint type!") ? static_cast<void> (0) : __assert_fail
("(OpInfo.ConstraintType == TargetLowering::C_RegisterClass || OpInfo.ConstraintType == TargetLowering::C_Register) && \"Unknown constraint type!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7862, __PRETTY_FUNCTION__))
7861 OpInfo.ConstraintType == TargetLowering::C_Register) &&(((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
OpInfo.ConstraintType == TargetLowering::C_Register) &&
"Unknown constraint type!") ? static_cast<void> (0) : __assert_fail
("(OpInfo.ConstraintType == TargetLowering::C_RegisterClass || OpInfo.ConstraintType == TargetLowering::C_Register) && \"Unknown constraint type!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7862, __PRETTY_FUNCTION__))
7862 "Unknown constraint type!")(((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
OpInfo.ConstraintType == TargetLowering::C_Register) &&
"Unknown constraint type!") ? static_cast<void> (0) : __assert_fail
("(OpInfo.ConstraintType == TargetLowering::C_RegisterClass || OpInfo.ConstraintType == TargetLowering::C_Register) && \"Unknown constraint type!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7862, __PRETTY_FUNCTION__))
;
7863
7864 // TODO: Support this.
7865 if (OpInfo.isIndirect) {
7866 emitInlineAsmError(
7867 CS, "Don't know how to handle indirect register inputs yet "
7868 "for constraint '" +
7869 Twine(OpInfo.ConstraintCode) + "'");
7870 return;
7871 }
7872
7873 // Copy the input into the appropriate registers.
7874 if (OpInfo.AssignedRegs.Regs.empty()) {
7875 emitInlineAsmError(CS, "couldn't allocate input reg for constraint '" +
7876 Twine(OpInfo.ConstraintCode) + "'");
7877 return;
7878 }
7879
7880 SDLoc dl = getCurSDLoc();
7881
7882 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, dl,
7883 Chain, &Flag, CS.getInstruction());
7884
7885 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0,
7886 dl, DAG, AsmNodeOperands);
7887 break;
7888 }
7889 case InlineAsm::isClobber:
7890 // Add the clobbered value to the operand list, so that the register
7891 // allocator is aware that the physreg got clobbered.
7892 if (!OpInfo.AssignedRegs.Regs.empty())
7893 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber,
7894 false, 0, getCurSDLoc(), DAG,
7895 AsmNodeOperands);
7896 break;
7897 }
7898 }
7899
7900 // Finish up input operands. Set the input chain and add the flag last.
7901 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
7902 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
7903
7904 Chain = DAG.getNode(ISD::INLINEASM, getCurSDLoc(),
7905 DAG.getVTList(MVT::Other, MVT::Glue), AsmNodeOperands);
7906 Flag = Chain.getValue(1);
7907
7908 // If this asm returns a register value, copy the result from that register
7909 // and set it as the value of the call.
7910 if (!RetValRegs.Regs.empty()) {
7911 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
7912 Chain, &Flag, CS.getInstruction());
7913
7914 llvm::Type *CSResultType = CS.getType();
7915 unsigned numRet;
7916 ArrayRef<Type *> ResultTypes;
7917 SmallVector<SDValue, 1> ResultValues(1);
7918 if (CSResultType->isSingleValueType()) {
7919 numRet = 1;
7920 ResultValues[0] = Val;
7921 ResultTypes = makeArrayRef(CSResultType);
7922 } else {
7923 numRet = CSResultType->getNumContainedTypes();
7924 assert(Val->getNumOperands() == numRet &&((Val->getNumOperands() == numRet && "Mismatch in number of output operands in asm result"
) ? static_cast<void> (0) : __assert_fail ("Val->getNumOperands() == numRet && \"Mismatch in number of output operands in asm result\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7925, __PRETTY_FUNCTION__))
7925 "Mismatch in number of output operands in asm result")((Val->getNumOperands() == numRet && "Mismatch in number of output operands in asm result"
) ? static_cast<void> (0) : __assert_fail ("Val->getNumOperands() == numRet && \"Mismatch in number of output operands in asm result\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7925, __PRETTY_FUNCTION__))
;
7926 ResultTypes = CSResultType->subtypes();
7927 ArrayRef<SDUse> ValueUses = Val->ops();
7928 ResultValues.resize(numRet);
7929 std::transform(ValueUses.begin(), ValueUses.end(), ResultValues.begin(),
7930 [](const SDUse &u) -> SDValue { return u.get(); });
7931 }
7932 SmallVector<EVT, 1> ResultVTs(numRet);
7933 for (unsigned i = 0; i < numRet; i++) {
7934 EVT ResultVT = TLI.getValueType(DAG.getDataLayout(), ResultTypes[i]);
7935 SDValue Val = ResultValues[i];
7936 assert(ResultTypes[i]->isSized() && "Unexpected unsized type")((ResultTypes[i]->isSized() && "Unexpected unsized type"
) ? static_cast<void> (0) : __assert_fail ("ResultTypes[i]->isSized() && \"Unexpected unsized type\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7936, __PRETTY_FUNCTION__))
;
7937 // If the type of the inline asm call site return value is different but
7938 // has same size as the type of the asm output bitcast it. One example
7939 // of this is for vectors with different width / number of elements.
7940 // This can happen for register classes that can contain multiple
7941 // different value types. The preg or vreg allocated may not have the
7942 // same VT as was expected.
7943 //
7944 // This can also happen for a return value that disagrees with the
7945 // register class it is put in, eg. a double in a general-purpose
7946 // register on a 32-bit machine.
7947 if (ResultVT != Val.getValueType() &&
7948 ResultVT.getSizeInBits() == Val.getValueSizeInBits())
7949 Val = DAG.getNode(ISD::BITCAST, getCurSDLoc(), ResultVT, Val);
7950 else if (ResultVT != Val.getValueType() && ResultVT.isInteger() &&
7951 Val.getValueType().isInteger()) {
7952 // If a result value was tied to an input value, the computed result
7953 // may have a wider width than the expected result. Extract the
7954 // relevant portion.
7955 Val = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), ResultVT, Val);
7956 }
7957
7958 assert(ResultVT == Val.getValueType() && "Asm result value mismatch!")((ResultVT == Val.getValueType() && "Asm result value mismatch!"
) ? static_cast<void> (0) : __assert_fail ("ResultVT == Val.getValueType() && \"Asm result value mismatch!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7958, __PRETTY_FUNCTION__))
;
7959 ResultVTs[i] = ResultVT;
7960 ResultValues[i] = Val;
7961 }
7962
7963 Val = DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
7964 DAG.getVTList(ResultVTs), ResultValues);
7965 setValue(CS.getInstruction(), Val);
7966 // Don't need to use this as a chain in this case.
7967 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
7968 return;
7969 }
7970
7971 std::vector<std::pair<SDValue, const Value *>> StoresToEmit;
7972
7973 // Process indirect outputs, first output all of the flagged copies out of
7974 // physregs.
7975 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
7976 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
7977 const Value *Ptr = IndirectStoresToEmit[i].second;
7978 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
7979 Chain, &Flag, IA);
7980 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
7981 }
7982
7983 // Emit the non-flagged stores from the physregs.
7984 SmallVector<SDValue, 8> OutChains;
7985 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) {
7986 SDValue Val = DAG.getStore(Chain, getCurSDLoc(), StoresToEmit[i].first,
7987 getValue(StoresToEmit[i].second),
7988 MachinePointerInfo(StoresToEmit[i].second));
7989 OutChains.push_back(Val);
7990 }
7991
7992 if (!OutChains.empty())
7993 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other, OutChains);
7994
7995 DAG.setRoot(Chain);
7996}
7997
7998void SelectionDAGBuilder::emitInlineAsmError(ImmutableCallSite CS,
7999 const Twine &Message) {
8000 LLVMContext &Ctx = *DAG.getContext();
8001 Ctx.emitError(CS.getInstruction(), Message);
8002
8003 // Make sure we leave the DAG in a valid state
8004 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8005 SmallVector<EVT, 1> ValueVTs;
8006 ComputeValueVTs(TLI, DAG.getDataLayout(), CS->getType(), ValueVTs);
8007
8008 if (ValueVTs.empty())
8009 return;
8010
8011 SmallVector<SDValue, 1> Ops;
8012 for (unsigned i = 0, e = ValueVTs.size(); i != e; ++i)
8013 Ops.push_back(DAG.getUNDEF(ValueVTs[i]));
8014
8015 setValue(CS.getInstruction(), DAG.getMergeValues(Ops, getCurSDLoc()));
8016}
8017
8018void SelectionDAGBuilder::visitVAStart(const CallInst &I) {
8019 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurSDLoc(),
8020 MVT::Other, getRoot(),
8021 getValue(I.getArgOperand(0)),
8022 DAG.getSrcValue(I.getArgOperand(0))));
8023}
8024
8025void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) {
8026 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8027 const DataLayout &DL = DAG.getDataLayout();
8028 SDValue V = DAG.getVAArg(TLI.getValueType(DAG.getDataLayout(), I.getType()),
8029 getCurSDLoc(), getRoot(), getValue(I.getOperand(0)),
8030 DAG.getSrcValue(I.getOperand(0)),
8031 DL.getABITypeAlignment(I.getType()));
8032 setValue(&I, V);
8033 DAG.setRoot(V.getValue(1));
8034}
8035
8036void SelectionDAGBuilder::visitVAEnd(const CallInst &I) {
8037 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurSDLoc(),
8038 MVT::Other, getRoot(),
8039 getValue(I.getArgOperand(0)),
8040 DAG.getSrcValue(I.getArgOperand(0))));
8041}
8042
8043void SelectionDAGBuilder::visitVACopy(const CallInst &I) {
8044 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurSDLoc(),
8045 MVT::Other, getRoot(),
8046 getValue(I.getArgOperand(0)),
8047 getValue(I.getArgOperand(1)),
8048 DAG.getSrcValue(I.getArgOperand(0)),
8049 DAG.getSrcValue(I.getArgOperand(1))));
8050}
8051
8052SDValue SelectionDAGBuilder::lowerRangeToAssertZExt(SelectionDAG &DAG,
8053 const Instruction &I,
8054 SDValue Op) {
8055 const MDNode *Range = I.getMetadata(LLVMContext::MD_range);
8056 if (!Range)
8057 return Op;
8058
8059 ConstantRange CR = getConstantRangeFromMetadata(*Range);
8060 if (CR.isFullSet() || CR.isEmptySet() || CR.isWrappedSet())
8061 return Op;
8062
8063 APInt Lo = CR.getUnsignedMin();
8064 if (!Lo.isMinValue())
8065 return Op;
8066
8067 APInt Hi = CR.getUnsignedMax();
8068 unsigned Bits = std::max(Hi.getActiveBits(),
8069 static_cast<unsigned>(IntegerType::MIN_INT_BITS));
8070
8071 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), Bits);
8072
8073 SDLoc SL = getCurSDLoc();
8074
8075 SDValue ZExt = DAG.getNode(ISD::AssertZext, SL, Op.getValueType(), Op,
8076 DAG.getValueType(SmallVT));
8077 unsigned NumVals = Op.getNode()->getNumValues();
8078 if (NumVals == 1)
8079 return ZExt;
8080
8081 SmallVector<SDValue, 4> Ops;
8082
8083 Ops.push_back(ZExt);
8084 for (unsigned I = 1; I != NumVals; ++I)
8085 Ops.push_back(Op.getValue(I));
8086
8087 return DAG.getMergeValues(Ops, SL);
8088}
8089
8090/// Populate a CallLowerinInfo (into \p CLI) based on the properties of
8091/// the call being lowered.
8092///
8093/// This is a helper for lowering intrinsics that follow a target calling
8094/// convention or require stack pointer adjustment. Only a subset of the
8095/// intrinsic's operands need to participate in the calling convention.
8096void SelectionDAGBuilder::populateCallLoweringInfo(
8097 TargetLowering::CallLoweringInfo &CLI, ImmutableCallSite CS,
8098 unsigned ArgIdx, unsigned NumArgs, SDValue Callee, Type *ReturnTy,
8099 bool IsPatchPoint) {
8100 TargetLowering::ArgListTy Args;
8101 Args.reserve(NumArgs);
8102
8103 // Populate the argument list.
8104 // Attributes for args start at offset 1, after the return attribute.
8105 for (unsigned ArgI = ArgIdx, ArgE = ArgIdx + NumArgs;
8106 ArgI != ArgE; ++ArgI) {
8107 const Value *V = CS->getOperand(ArgI);
8108
8109 assert(!V->getType()->isEmptyTy() && "Empty type passed to intrinsic.")((!V->getType()->isEmptyTy() && "Empty type passed to intrinsic."
) ? static_cast<void> (0) : __assert_fail ("!V->getType()->isEmptyTy() && \"Empty type passed to intrinsic.\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 8109, __PRETTY_FUNCTION__))
;
8110
8111 TargetLowering::ArgListEntry Entry;
8112 Entry.Node = getValue(V);
8113 Entry.Ty = V->getType();
8114 Entry.setAttributes(&CS, ArgI);
8115 Args.push_back(Entry);
8116 }
8117
8118 CLI.setDebugLoc(getCurSDLoc())
8119 .setChain(getRoot())
8120 .setCallee(CS.getCallingConv(), ReturnTy, Callee, std::move(Args))
8121 .setDiscardResult(CS->use_empty())
8122 .setIsPatchPoint(IsPatchPoint);
8123}
8124
8125/// Add a stack map intrinsic call's live variable operands to a stackmap
8126/// or patchpoint target node's operand list.
8127///
8128/// Constants are converted to TargetConstants purely as an optimization to
8129/// avoid constant materialization and register allocation.
8130///
8131/// FrameIndex operands are converted to TargetFrameIndex so that ISEL does not
8132/// generate addess computation nodes, and so ExpandISelPseudo can convert the
8133/// TargetFrameIndex into a DirectMemRefOp StackMap location. This avoids
8134/// address materialization and register allocation, but may also be required
8135/// for correctness. If a StackMap (or PatchPoint) intrinsic directly uses an
8136/// alloca in the entry block, then the runtime may assume that the alloca's
8137/// StackMap location can be read immediately after compilation and that the
8138/// location is valid at any point during execution (this is similar to the
8139/// assumption made by the llvm.gcroot intrinsic). If the alloca's location were
8140/// only available in a register, then the runtime would need to trap when
8141/// execution reaches the StackMap in order to read the alloca's location.
8142static void addStackMapLiveVars(ImmutableCallSite CS, unsigned StartIdx,
8143 const SDLoc &DL, SmallVectorImpl<SDValue> &Ops,
8144 SelectionDAGBuilder &Builder) {
8145 for (unsigned i = StartIdx, e = CS.arg_size(); i != e; ++i) {
8146 SDValue OpVal = Builder.getValue(CS.getArgument(i));
8147 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(OpVal)) {
8148 Ops.push_back(
8149 Builder.DAG.getTargetConstant(StackMaps::ConstantOp, DL, MVT::i64));
8150 Ops.push_back(
8151 Builder.DAG.getTargetConstant(C->getSExtValue(), DL, MVT::i64));
8152 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(OpVal)) {
8153 const TargetLowering &TLI = Builder.DAG.getTargetLoweringInfo();
8154 Ops.push_back(Builder.DAG.getTargetFrameIndex(
8155 FI->getIndex(), TLI.getFrameIndexTy(Builder.DAG.getDataLayout())));
8156 } else
8157 Ops.push_back(OpVal);
8158 }
8159}
8160
8161/// Lower llvm.experimental.stackmap directly to its target opcode.
8162void SelectionDAGBuilder::visitStackmap(const CallInst &CI) {
8163 // void @llvm.experimental.stackmap(i32 <id>, i32 <numShadowBytes>,
8164 // [live variables...])
8165
8166 assert(CI.getType()->isVoidTy() && "Stackmap cannot return a value.")((CI.getType()->isVoidTy() && "Stackmap cannot return a value."
) ? static_cast<void> (0) : __assert_fail ("CI.getType()->isVoidTy() && \"Stackmap cannot return a value.\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 8166, __PRETTY_FUNCTION__))
;
8167
8168 SDValue Chain, InFlag, Callee, NullPtr;
8169 SmallVector<SDValue, 32> Ops;
8170
8171 SDLoc DL = getCurSDLoc();
8172 Callee = getValue(CI.getCalledValue());
8173 NullPtr = DAG.getIntPtrConstant(0, DL, true);
8174
8175 // The stackmap intrinsic only records the live variables (the arguemnts
8176 // passed to it) and emits NOPS (if requested). Unlike the patchpoint
8177 // intrinsic, this won't be lowered to a function call. This means we don't
8178 // have to worry about calling conventions and target specific lowering code.
8179 // Instead we perform the call lowering right here.
8180 //
8181 // chain, flag = CALLSEQ_START(chain, 0, 0)
8182 // chain, flag = STACKMAP(id, nbytes, ..., chain, flag)
8183 // chain, flag = CALLSEQ_END(chain, 0, 0, flag)
8184 //
8185 Chain = DAG.getCALLSEQ_START(getRoot(), 0, 0, DL);
8186 InFlag = Chain.getValue(1);
8187
8188 // Add the <id> and <numBytes> constants.
8189 SDValue IDVal = getValue(CI.getOperand(PatchPointOpers::IDPos));
8190 Ops.push_back(DAG.getTargetConstant(
8191 cast<ConstantSDNode>(IDVal)->getZExtValue(), DL, MVT::i64));
8192 SDValue NBytesVal = getValue(CI.getOperand(PatchPointOpers::NBytesPos));
8193 Ops.push_back(DAG.getTargetConstant(
8194 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), DL,
8195 MVT::i32));
8196
8197 // Push live variables for the stack map.
8198 addStackMapLiveVars(&CI, 2, DL, Ops, *this);
8199
8200 // We are not pushing any register mask info here on the operands list,
8201 // because the stackmap doesn't clobber anything.
8202
8203 // Push the chain and the glue flag.
8204 Ops.push_back(Chain);
8205 Ops.push_back(InFlag);
8206
8207 // Create the STACKMAP node.
8208 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
8209 SDNode *SM = DAG.getMachineNode(TargetOpcode::STACKMAP, DL, NodeTys, Ops);
8210 Chain = SDValue(SM, 0);
8211 InFlag = Chain.getValue(1);
8212
8213 Chain = DAG.getCALLSEQ_END(Chain, NullPtr, NullPtr, InFlag, DL);
8214
8215 // Stackmaps don't generate values, so nothing goes into the NodeMap.
8216
8217 // Set the root to the target-lowered call chain.
8218 DAG.setRoot(Chain);
8219
8220 // Inform the Frame Information that we have a stackmap in this function.
8221 FuncInfo.MF->getFrameInfo().setHasStackMap();
8222}
8223
8224/// Lower llvm.experimental.patchpoint directly to its target opcode.
8225void SelectionDAGBuilder::visitPatchpoint(ImmutableCallSite CS,
8226 const BasicBlock *EHPadBB) {
8227 // void|i64 @llvm.experimental.patchpoint.void|i64(i64 <id>,
8228 // i32 <numBytes>,
8229 // i8* <target>,
8230 // i32 <numArgs>,
8231 // [Args...],
8232 // [live variables...])
8233
8234 CallingConv::ID CC = CS.getCallingConv();
8235 bool IsAnyRegCC = CC == CallingConv::AnyReg;
8236 bool HasDef = !CS->getType()->isVoidTy();
8237 SDLoc dl = getCurSDLoc();
8238 SDValue Callee = getValue(CS->getOperand(PatchPointOpers::TargetPos));
8239
8240 // Handle immediate and symbolic callees.
8241 if (auto* ConstCallee = dyn_cast<ConstantSDNode>(Callee))
8242 Callee = DAG.getIntPtrConstant(ConstCallee->getZExtValue(), dl,
8243 /*isTarget=*/true);
8244 else if (auto* SymbolicCallee = dyn_cast<GlobalAddressSDNode>(Callee))
8245 Callee = DAG.getTargetGlobalAddress(SymbolicCallee->getGlobal(),
8246 SDLoc(SymbolicCallee),
8247 SymbolicCallee->getValueType(0));
8248
8249 // Get the real number of arguments participating in the call <numArgs>
8250 SDValue NArgVal = getValue(CS.getArgument(PatchPointOpers::NArgPos));
8251 unsigned NumArgs = cast<ConstantSDNode>(NArgVal)->getZExtValue();
8252
8253 // Skip the four meta args: <id>, <numNopBytes>, <target>, <numArgs>
8254 // Intrinsics include all meta-operands up to but not including CC.
8255 unsigned NumMetaOpers = PatchPointOpers::CCPos;
8256 assert(CS.arg_size() >= NumMetaOpers + NumArgs &&((CS.arg_size() >= NumMetaOpers + NumArgs && "Not enough arguments provided to the patchpoint intrinsic"
) ? static_cast<void> (0) : __assert_fail ("CS.arg_size() >= NumMetaOpers + NumArgs && \"Not enough arguments provided to the patchpoint intrinsic\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 8257, __PRETTY_FUNCTION__))
8257 "Not enough arguments provided to the patchpoint intrinsic")((CS.arg_size() >= NumMetaOpers + NumArgs && "Not enough arguments provided to the patchpoint intrinsic"
) ? static_cast<void> (0) : __assert_fail ("CS.arg_size() >= NumMetaOpers + NumArgs && \"Not enough arguments provided to the patchpoint intrinsic\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 8257, __PRETTY_FUNCTION__))
;
8258
8259 // For AnyRegCC the arguments are lowered later on manually.
8260 unsigned NumCallArgs = IsAnyRegCC ? 0 : NumArgs;
8261 Type *ReturnTy =
8262 IsAnyRegCC ? Type::getVoidTy(*DAG.getContext()) : CS->getType();
8263
8264 TargetLowering::CallLoweringInfo CLI(DAG);
8265 populateCallLoweringInfo(CLI, CS, NumMetaOpers, NumCallArgs, Callee, ReturnTy,
8266 true);
8267 std::pair<SDValue, SDValue> Result = lowerInvokable(CLI, EHPadBB);
8268
8269 SDNode *CallEnd = Result.second.getNode();
8270 if (HasDef && (CallEnd->getOpcode() == ISD::CopyFromReg))
8271 CallEnd = CallEnd->getOperand(0).getNode();
8272
8273 /// Get a call instruction from the call sequence chain.
8274 /// Tail calls are not allowed.
8275 assert(CallEnd->getOpcode() == ISD::CALLSEQ_END &&((CallEnd->getOpcode() == ISD::CALLSEQ_END && "Expected a callseq node."
) ? static_cast<void> (0) : __assert_fail ("CallEnd->getOpcode() == ISD::CALLSEQ_END && \"Expected a callseq node.\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 8276, __PRETTY_FUNCTION__))
8276 "Expected a callseq node.")((CallEnd->getOpcode() == ISD::CALLSEQ_END && "Expected a callseq node."
) ? static_cast<void> (0) : __assert_fail ("CallEnd->getOpcode() == ISD::CALLSEQ_END && \"Expected a callseq node.\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 8276, __PRETTY_FUNCTION__))
;
8277 SDNode *Call = CallEnd->getOperand(0).getNode();
8278 bool HasGlue = Call->getGluedNode();
8279
8280 // Replace the target specific call node with the patchable intrinsic.
8281 SmallVector<SDValue, 8> Ops;
8282
8283 // Add the <id> and <numBytes> constants.
8284 SDValue IDVal = getValue(CS->getOperand(PatchPointOpers::IDPos));
8285 Ops.push_back(DAG.getTargetConstant(
8286 cast<ConstantSDNode>(IDVal)->getZExtValue(), dl, MVT::i64));
8287 SDValue NBytesVal = getValue(CS->getOperand(PatchPointOpers::NBytesPos));
8288 Ops.push_back(DAG.getTargetConstant(
8289 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), dl,
8290 MVT::i32));
8291
8292 // Add the callee.
8293 Ops.push_back(Callee);
8294
8295 // Adjust <numArgs> to account for any arguments that have been passed on the
8296 // stack instead.
8297 // Call Node: Chain, Target, {Args}, RegMask, [Glue]
8298 unsigned NumCallRegArgs = Call->getNumOperands() - (HasGlue ? 4 : 3);
8299 NumCallRegArgs = IsAnyRegCC ? NumArgs : NumCallRegArgs;
8300 Ops.push_back(DAG.getTargetConstant(NumCallRegArgs, dl, MVT::i32));
8301
8302 // Add the calling convention
8303 Ops.push_back(DAG.getTargetConstant((unsigned)CC, dl, MVT::i32));
8304
8305 // Add the arguments we omitted previously. The register allocator should
8306 // place these in any free register.
8307 if (IsAnyRegCC)
8308 for (unsigned i = NumMetaOpers, e = NumMetaOpers + NumArgs; i != e; ++i)
8309 Ops.push_back(getValue(CS.getArgument(i)));
8310
8311 // Push the arguments from the call instruction up to the register mask.
8312 SDNode::op_iterator e = HasGlue ? Call->op_end()-2 : Call->op_end()-1;
8313 Ops.append(Call->op_begin() + 2, e);
8314
8315 // Push live variables for the stack map.
8316 addStackMapLiveVars(CS, NumMetaOpers + NumArgs, dl, Ops, *this);
8317
8318 // Push the register mask info.
8319 if (HasGlue)
8320 Ops.push_back(*(Call->op_end()-2));
8321 else
8322 Ops.push_back(*(Call->op_end()-1));
8323
8324 // Push the chain (this is originally the first operand of the call, but
8325 // becomes now the last or second to last operand).
8326 Ops.push_back(*(Call->op_begin()));
8327
8328 // Push the glue flag (last operand).
8329 if (HasGlue)
8330 Ops.push_back(*(Call->op_end()-1));
8331
8332 SDVTList NodeTys;
8333 if (IsAnyRegCC && HasDef) {
8334 // Create the return types based on the intrinsic definition
8335 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8336 SmallVector<EVT, 3> ValueVTs;
8337 ComputeValueVTs(TLI, DAG.getDataLayout(), CS->getType(), ValueVTs);
8338 assert(ValueVTs.size() == 1 && "Expected only one return value type.")((ValueVTs.size() == 1 && "Expected only one return value type."
) ? static_cast<void> (0) : __assert_fail ("ValueVTs.size() == 1 && \"Expected only one return value type.\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 8338, __PRETTY_FUNCTION__))
;
8339
8340 // There is always a chain and a glue type at the end
8341 ValueVTs.push_back(MVT::Other);
8342 ValueVTs.push_back(MVT::Glue);
8343 NodeTys = DAG.getVTList(ValueVTs);
8344 } else
8345 NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
8346
8347 // Replace the target specific call node with a PATCHPOINT node.
8348 MachineSDNode *MN = DAG.getMachineNode(TargetOpcode::PATCHPOINT,
8349 dl, NodeTys, Ops);
8350
8351 // Update the NodeMap.
8352 if (HasDef) {
8353 if (IsAnyRegCC)
8354 setValue(CS.getInstruction(), SDValue(MN, 0));
8355 else
8356 setValue(CS.getInstruction(), Result.first);
8357 }
8358
8359 // Fixup the consumers of the intrinsic. The chain and glue may be used in the
8360 // call sequence. Furthermore the location of the chain and glue can change
8361 // when the AnyReg calling convention is used and the intrinsic returns a
8362 // value.
8363 if (IsAnyRegCC && HasDef) {
8364 SDValue From[] = {SDValue(Call, 0), SDValue(Call, 1)};
8365 SDValue To[] = {SDValue(MN, 1), SDValue(MN, 2)};
8366 DAG.ReplaceAllUsesOfValuesWith(From, To, 2);
8367 } else
8368 DAG.ReplaceAllUsesWith(Call, MN);
8369 DAG.DeleteNode(Call);
8370
8371 // Inform the Frame Information that we have a patchpoint in this function.
8372 FuncInfo.MF->getFrameInfo().setHasPatchPoint();
8373}
8374
8375void SelectionDAGBuilder::visitVectorReduce(const CallInst &I,
8376 unsigned Intrinsic) {
8377 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8378 SDValue Op1 = getValue(I.getArgOperand(0));
8379 SDValue Op2;
8380 if (I.getNumArgOperands() > 1)
8381 Op2 = getValue(I.getArgOperand(1));
8382 SDLoc dl = getCurSDLoc();
8383 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
8384 SDValue Res;
8385 FastMathFlags FMF;
8386 if (isa<FPMathOperator>(I))
8387 FMF = I.getFastMathFlags();
8388
8389 switch (Intrinsic) {
8390 case Intrinsic::experimental_vector_reduce_fadd:
8391 if (FMF.isFast())
8392 Res = DAG.getNode(ISD::VECREDUCE_FADD, dl, VT, Op2);
8393 else
8394 Res = DAG.getNode(ISD::VECREDUCE_STRICT_FADD, dl, VT, Op1, Op2);
8395 break;
8396 case Intrinsic::experimental_vector_reduce_fmul:
8397 if (FMF.isFast())
8398 Res = DAG.getNode(ISD::VECREDUCE_FMUL, dl, VT, Op2);
8399 else
8400 Res = DAG.getNode(ISD::VECREDUCE_STRICT_FMUL, dl, VT, Op1, Op2);
8401 break;
8402 case Intrinsic::experimental_vector_reduce_add:
8403 Res = DAG.getNode(ISD::VECREDUCE_ADD, dl, VT, Op1);
8404 break;
8405 case Intrinsic::experimental_vector_reduce_mul:
8406 Res = DAG.getNode(ISD::VECREDUCE_MUL, dl, VT, Op1);
8407 break;
8408 case Intrinsic::experimental_vector_reduce_and:
8409 Res = DAG.getNode(ISD::VECREDUCE_AND, dl, VT, Op1);
8410 break;
8411 case Intrinsic::experimental_vector_reduce_or:
8412 Res = DAG.getNode(ISD::VECREDUCE_OR, dl, VT, Op1);
8413 break;
8414 case Intrinsic::experimental_vector_reduce_xor:
8415 Res = DAG.getNode(ISD::VECREDUCE_XOR, dl, VT, Op1);
8416 break;
8417 case Intrinsic::experimental_vector_reduce_smax:
8418 Res = DAG.getNode(ISD::VECREDUCE_SMAX, dl, VT, Op1);
8419 break;
8420 case Intrinsic::experimental_vector_reduce_smin:
8421 Res = DAG.getNode(ISD::VECREDUCE_SMIN, dl, VT, Op1);
8422 break;
8423 case Intrinsic::experimental_vector_reduce_umax:
8424 Res = DAG.getNode(ISD::VECREDUCE_UMAX, dl, VT, Op1);
8425 break;
8426 case Intrinsic::experimental_vector_reduce_umin:
8427 Res = DAG.getNode(ISD::VECREDUCE_UMIN, dl, VT, Op1);
8428 break;
8429 case Intrinsic::experimental_vector_reduce_fmax:
8430 Res = DAG.getNode(ISD::VECREDUCE_FMAX, dl, VT, Op1);
8431 break;
8432 case Intrinsic::experimental_vector_reduce_fmin:
8433 Res = DAG.getNode(ISD::VECREDUCE_FMIN, dl, VT, Op1);
8434 break;
8435 default:
8436 llvm_unreachable("Unhandled vector reduce intrinsic")::llvm::llvm_unreachable_internal("Unhandled vector reduce intrinsic"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 8436)
;
8437 }
8438 setValue(&I, Res);
8439}
8440
8441/// Returns an AttributeList representing the attributes applied to the return
8442/// value of the given call.
8443static AttributeList getReturnAttrs(TargetLowering::CallLoweringInfo &CLI) {
8444 SmallVector<Attribute::AttrKind, 2> Attrs;
8445 if (CLI.RetSExt)
8446 Attrs.push_back(Attribute::SExt);
8447 if (CLI.RetZExt)
8448 Attrs.push_back(Attribute::ZExt);
8449 if (CLI.IsInReg)
8450 Attrs.push_back(Attribute::InReg);
8451
8452 return AttributeList::get(CLI.RetTy->getContext(), AttributeList::ReturnIndex,
8453 Attrs);
8454}
8455
8456/// TargetLowering::LowerCallTo - This is the default LowerCallTo
8457/// implementation, which just calls LowerCall.
8458/// FIXME: When all targets are
8459/// migrated to using LowerCall, this hook should be integrated into SDISel.
8460std::pair<SDValue, SDValue>
8461TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const {
8462 // Handle the incoming return values from the call.
8463 CLI.Ins.clear();
8464 Type *OrigRetTy = CLI.RetTy;
8465 SmallVector<EVT, 4> RetTys;
8466 SmallVector<uint64_t, 4> Offsets;
8467 auto &DL = CLI.DAG.getDataLayout();
8468 ComputeValueVTs(*this, DL, CLI.RetTy, RetTys, &Offsets);
8469
8470 if (CLI.IsPostTypeLegalization) {
8471 // If we are lowering a libcall after legalization, split the return type.
8472 SmallVector<EVT, 4> OldRetTys = std::move(RetTys);
8473 SmallVector<uint64_t, 4> OldOffsets = std::move(Offsets);
8474 for (size_t i = 0, e = OldRetTys.size(); i != e; ++i) {
8475 EVT RetVT = OldRetTys[i];
8476 uint64_t Offset = OldOffsets[i];
8477 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), RetVT);
8478 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), RetVT);
8479 unsigned RegisterVTByteSZ = RegisterVT.getSizeInBits() / 8;
8480 RetTys.append(NumRegs, RegisterVT);
8481 for (unsigned j = 0; j != NumRegs; ++j)
8482 Offsets.push_back(Offset + j * RegisterVTByteSZ);
8483 }
8484 }
8485
8486 SmallVector<ISD::OutputArg, 4> Outs;
8487 GetReturnInfo(CLI.CallConv, CLI.RetTy, getReturnAttrs(CLI), Outs, *this, DL);
8488
8489 bool CanLowerReturn =
8490 this->CanLowerReturn(CLI.CallConv, CLI.DAG.getMachineFunction(),
8491 CLI.IsVarArg, Outs, CLI.RetTy->getContext());
8492
8493 SDValue DemoteStackSlot;
8494 int DemoteStackIdx = -100;
8495 if (!CanLowerReturn) {
8496 // FIXME: equivalent assert?
8497 // assert(!CS.hasInAllocaArgument() &&
8498 // "sret demotion is incompatible with inalloca");
8499 uint64_t TySize = DL.getTypeAllocSize(CLI.RetTy);
8500 unsigned Align = DL.getPrefTypeAlignment(CLI.RetTy);
8501 MachineFunction &MF = CLI.DAG.getMachineFunction();
8502 DemoteStackIdx = MF.getFrameInfo().CreateStackObject(TySize, Align, false);
8503 Type *StackSlotPtrType = PointerType::get(CLI.RetTy,
8504 DL.getAllocaAddrSpace());
8505
8506 DemoteStackSlot = CLI.DAG.getFrameIndex(DemoteStackIdx, getFrameIndexTy(DL));
8507 ArgListEntry Entry;
8508 Entry.Node = DemoteStackSlot;
8509 Entry.Ty = StackSlotPtrType;
8510 Entry.IsSExt = false;
8511 Entry.IsZExt = false;
8512 Entry.IsInReg = false;
8513 Entry.IsSRet = true;
8514 Entry.IsNest = false;
8515 Entry.IsByVal = false;
8516 Entry.IsReturned = false;
8517 Entry.IsSwiftSelf = false;
8518 Entry.IsSwiftError = false;
8519 Entry.Alignment = Align;
8520 CLI.getArgs().insert(CLI.getArgs().begin(), Entry);
8521 CLI.NumFixedArgs += 1;
8522 CLI.RetTy = Type::getVoidTy(CLI.RetTy->getContext());
8523
8524 // sret demotion isn't compatible with tail-calls, since the sret argument
8525 // points into the callers stack frame.
8526 CLI.IsTailCall = false;
8527 } else {
8528 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
8529 EVT VT = RetTys[I];
8530 MVT RegisterVT = getRegisterTypeForCallingConv(CLI.RetTy->getContext(),
8531 CLI.CallConv, VT);
8532 unsigned NumRegs = getNumRegistersForCallingConv(CLI.RetTy->getContext(),
8533 CLI.CallConv, VT);
8534 for (unsigned i = 0; i != NumRegs; ++i) {
8535 ISD::InputArg MyFlags;
8536 MyFlags.VT = RegisterVT;
8537 MyFlags.ArgVT = VT;
8538 MyFlags.Used = CLI.IsReturnValueUsed;
8539 if (CLI.RetSExt)
8540 MyFlags.Flags.setSExt();
8541 if (CLI.RetZExt)
8542 MyFlags.Flags.setZExt();
8543 if (CLI.IsInReg)
8544 MyFlags.Flags.setInReg();
8545 CLI.Ins.push_back(MyFlags);
8546 }
8547 }
8548 }
8549
8550 // We push in swifterror return as the last element of CLI.Ins.
8551 ArgListTy &Args = CLI.getArgs();
8552 if (supportSwiftError()) {
8553 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
8554 if (Args[i].IsSwiftError) {
8555 ISD::InputArg MyFlags;
8556 MyFlags.VT = getPointerTy(DL);
8557 MyFlags.ArgVT = EVT(getPointerTy(DL));
8558 MyFlags.Flags.setSwiftError();
8559 CLI.Ins.push_back(MyFlags);
8560 }
8561 }
8562 }
8563
8564 // Handle all of the outgoing arguments.
8565 CLI.Outs.clear();
8566 CLI.OutVals.clear();
8567 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
8568 SmallVector<EVT, 4> ValueVTs;
8569 ComputeValueVTs(*this, DL, Args[i].Ty, ValueVTs);
8570 // FIXME: Split arguments if CLI.IsPostTypeLegalization
8571 Type *FinalType = Args[i].Ty;
8572 if (Args[i].IsByVal)
8573 FinalType = cast<PointerType>(Args[i].Ty)->getElementType();
8574 bool NeedsRegBlock = functionArgumentNeedsConsecutiveRegisters(
8575 FinalType, CLI.CallConv, CLI.IsVarArg);
8576 for (unsigned Value = 0, NumValues = ValueVTs.size(); Value != NumValues;
8577 ++Value) {
8578 EVT VT = ValueVTs[Value];
8579 Type *ArgTy = VT.getTypeForEVT(CLI.RetTy->getContext());
8580 SDValue Op = SDValue(Args[i].Node.getNode(),
8581 Args[i].Node.getResNo() + Value);
8582 ISD::ArgFlagsTy Flags;
8583
8584 // Certain targets (such as MIPS), may have a different ABI alignment
8585 // for a type depending on the context. Give the target a chance to
8586 // specify the alignment it wants.
8587 unsigned OriginalAlignment = getABIAlignmentForCallingConv(ArgTy, DL);
8588
8589 if (Args[i].IsZExt)
8590 Flags.setZExt();
8591 if (Args[i].IsSExt)
8592 Flags.setSExt();
8593 if (Args[i].IsInReg) {
8594 // If we are using vectorcall calling convention, a structure that is
8595 // passed InReg - is surely an HVA
8596 if (CLI.CallConv == CallingConv::X86_VectorCall &&
8597 isa<StructType>(FinalType)) {
8598 // The first value of a structure is marked
8599 if (0 == Value)
8600 Flags.setHvaStart();
8601 Flags.setHva();
8602 }
8603 // Set InReg Flag
8604 Flags.setInReg();
8605 }
8606 if (Args[i].IsSRet)
8607 Flags.setSRet();
8608 if (Args[i].IsSwiftSelf)
8609 Flags.setSwiftSelf();
8610 if (Args[i].IsSwiftError)
8611 Flags.setSwiftError();
8612 if (Args[i].IsByVal)
8613 Flags.setByVal();
8614 if (Args[i].IsInAlloca) {
8615 Flags.setInAlloca();
8616 // Set the byval flag for CCAssignFn callbacks that don't know about
8617 // inalloca. This way we can know how many bytes we should've allocated
8618 // and how many bytes a callee cleanup function will pop. If we port
8619 // inalloca to more targets, we'll have to add custom inalloca handling
8620 // in the various CC lowering callbacks.
8621 Flags.setByVal();
8622 }
8623 if (Args[i].IsByVal || Args[i].IsInAlloca) {
8624 PointerType *Ty = cast<PointerType>(Args[i].Ty);
8625 Type *ElementTy = Ty->getElementType();
8626 Flags.setByValSize(DL.getTypeAllocSize(ElementTy));
8627 // For ByVal, alignment should come from FE. BE will guess if this
8628 // info is not there but there are cases it cannot get right.
8629 unsigned FrameAlign;
8630 if (Args[i].Alignment)
8631 FrameAlign = Args[i].Alignment;
8632 else
8633 FrameAlign = getByValTypeAlignment(ElementTy, DL);
8634 Flags.setByValAlign(FrameAlign);
8635 }
8636 if (Args[i].IsNest)
8637 Flags.setNest();
8638 if (NeedsRegBlock)
8639 Flags.setInConsecutiveRegs();
8640 Flags.setOrigAlign(OriginalAlignment);
8641
8642 MVT PartVT = getRegisterTypeForCallingConv(CLI.RetTy->getContext(),
8643 CLI.CallConv, VT);
8644 unsigned NumParts = getNumRegistersForCallingConv(CLI.RetTy->getContext(),
8645 CLI.CallConv, VT);
8646 SmallVector<SDValue, 4> Parts(NumParts);
8647 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
8648
8649 if (Args[i].IsSExt)
8650 ExtendKind = ISD::SIGN_EXTEND;
8651 else if (Args[i].IsZExt)
8652 ExtendKind = ISD::ZERO_EXTEND;
8653
8654 // Conservatively only handle 'returned' on non-vectors that can be lowered,
8655 // for now.
8656 if (Args[i].IsReturned && !Op.getValueType().isVector() &&
8657 CanLowerReturn) {
8658 assert(CLI.RetTy == Args[i].Ty && RetTys.size() == NumValues &&((CLI.RetTy == Args[i].Ty && RetTys.size() == NumValues
&& "unexpected use of 'returned'") ? static_cast<
void> (0) : __assert_fail ("CLI.RetTy == Args[i].Ty && RetTys.size() == NumValues && \"unexpected use of 'returned'\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 8659, __PRETTY_FUNCTION__))
8659 "unexpected use of 'returned'")((CLI.RetTy == Args[i].Ty && RetTys.size() == NumValues
&& "unexpected use of 'returned'") ? static_cast<
void> (0) : __assert_fail ("CLI.RetTy == Args[i].Ty && RetTys.size() == NumValues && \"unexpected use of 'returned'\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 8659, __PRETTY_FUNCTION__))
;
8660 // Before passing 'returned' to the target lowering code, ensure that
8661 // either the register MVT and the actual EVT are the same size or that
8662 // the return value and argument are extended in the same way; in these
8663 // cases it's safe to pass the argument register value unchanged as the
8664 // return register value (although it's at the target's option whether
8665 // to do so)
8666 // TODO: allow code generation to take advantage of partially preserved
8667 // registers rather than clobbering the entire register when the
8668 // parameter extension method is not compatible with the return
8669 // extension method
8670 if ((NumParts * PartVT.getSizeInBits() == VT.getSizeInBits()) ||
8671 (ExtendKind != ISD::ANY_EXTEND && CLI.RetSExt == Args[i].IsSExt &&
8672 CLI.RetZExt == Args[i].IsZExt))
8673 Flags.setReturned();
8674 }
8675
8676 getCopyToParts(CLI.DAG, CLI.DL, Op, &Parts[0], NumParts, PartVT,
8677 CLI.CS.getInstruction(), CLI.CallConv, ExtendKind);
8678
8679 for (unsigned j = 0; j != NumParts; ++j) {
8680 // if it isn't first piece, alignment must be 1
8681 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(), VT,
8682 i < CLI.NumFixedArgs,
8683 i, j*Parts[j].getValueType().getStoreSize());
8684 if (NumParts > 1 && j == 0)
8685 MyFlags.Flags.setSplit();
8686 else if (j != 0) {
8687 MyFlags.Flags.setOrigAlign(1);
8688 if (j == NumParts - 1)
8689 MyFlags.Flags.setSplitEnd();
8690 }
8691
8692 CLI.Outs.push_back(MyFlags);
8693 CLI.OutVals.push_back(Parts[j]);
8694 }
8695
8696 if (NeedsRegBlock && Value == NumValues - 1)
8697 CLI.Outs[CLI.Outs.size() - 1].Flags.setInConsecutiveRegsLast();
8698 }
8699 }
8700
8701 SmallVector<SDValue, 4> InVals;
8702 CLI.Chain = LowerCall(CLI, InVals);
8703
8704 // Update CLI.InVals to use outside of this function.
8705 CLI.InVals = InVals;
8706
8707 // Verify that the target's LowerCall behaved as expected.
8708 assert(CLI.Chain.getNode() && CLI.Chain.getValueType() == MVT::Other &&((CLI.Chain.getNode() && CLI.Chain.getValueType() == MVT
::Other && "LowerCall didn't return a valid chain!") ?
static_cast<void> (0) : __assert_fail ("CLI.Chain.getNode() && CLI.Chain.getValueType() == MVT::Other && \"LowerCall didn't return a valid chain!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 8709, __PRETTY_FUNCTION__))
8709 "LowerCall didn't return a valid chain!")((CLI.Chain.getNode() && CLI.Chain.getValueType() == MVT
::Other && "LowerCall didn't return a valid chain!") ?
static_cast<void> (0) : __assert_fail ("CLI.Chain.getNode() && CLI.Chain.getValueType() == MVT::Other && \"LowerCall didn't return a valid chain!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 8709, __PRETTY_FUNCTION__))
;
8710 assert((!CLI.IsTailCall || InVals.empty()) &&(((!CLI.IsTailCall || InVals.empty()) && "LowerCall emitted a return value for a tail call!"
) ? static_cast<void> (0) : __assert_fail ("(!CLI.IsTailCall || InVals.empty()) && \"LowerCall emitted a return value for a tail call!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 8711, __PRETTY_FUNCTION__))
8711 "LowerCall emitted a return value for a tail call!")(((!CLI.IsTailCall || InVals.empty()) && "LowerCall emitted a return value for a tail call!"
) ? static_cast<void> (0) : __assert_fail ("(!CLI.IsTailCall || InVals.empty()) && \"LowerCall emitted a return value for a tail call!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 8711, __PRETTY_FUNCTION__))
;
8712 assert((CLI.IsTailCall || InVals.size() == CLI.Ins.size()) &&(((CLI.IsTailCall || InVals.size() == CLI.Ins.size()) &&
"LowerCall didn't emit the correct number of values!") ? static_cast
<void> (0) : __assert_fail ("(CLI.IsTailCall || InVals.size() == CLI.Ins.size()) && \"LowerCall didn't emit the correct number of values!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 8713, __PRETTY_FUNCTION__))
8713 "LowerCall didn't emit the correct number of values!")(((CLI.IsTailCall || InVals.size() == CLI.Ins.size()) &&
"LowerCall didn't emit the correct number of values!") ? static_cast
<void> (0) : __assert_fail ("(CLI.IsTailCall || InVals.size() == CLI.Ins.size()) && \"LowerCall didn't emit the correct number of values!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 8713, __PRETTY_FUNCTION__))
;
8714
8715 // For a tail call, the return value is merely live-out and there aren't
8716 // any nodes in the DAG representing it. Return a special value to
8717 // indicate that a tail call has been emitted and no more Instructions
8718 // should be processed in the current block.
8719 if (CLI.IsTailCall) {
8720 CLI.DAG.setRoot(CLI.Chain);
8721 return std::make_pair(SDValue(), SDValue());
8722 }
8723
8724#ifndef NDEBUG
8725 for (unsigned i = 0, e = CLI.Ins.size(); i != e; ++i) {
8726 assert(InVals[i].getNode() && "LowerCall emitted a null value!")((InVals[i].getNode() && "LowerCall emitted a null value!"
) ? static_cast<void> (0) : __assert_fail ("InVals[i].getNode() && \"LowerCall emitted a null value!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 8726, __PRETTY_FUNCTION__))
;
8727 assert(EVT(CLI.Ins[i].VT) == InVals[i].getValueType() &&((EVT(CLI.Ins[i].VT) == InVals[i].getValueType() && "LowerCall emitted a value with the wrong type!"
) ? static_cast<void> (0) : __assert_fail ("EVT(CLI.Ins[i].VT) == InVals[i].getValueType() && \"LowerCall emitted a value with the wrong type!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 8728, __PRETTY_FUNCTION__))
8728 "LowerCall emitted a value with the wrong type!")((EVT(CLI.Ins[i].VT) == InVals[i].getValueType() && "LowerCall emitted a value with the wrong type!"
) ? static_cast<void> (0) : __assert_fail ("EVT(CLI.Ins[i].VT) == InVals[i].getValueType() && \"LowerCall emitted a value with the wrong type!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 8728, __PRETTY_FUNCTION__))
;
8729 }
8730#endif
8731
8732 SmallVector<SDValue, 4> ReturnValues;
8733 if (!CanLowerReturn) {
8734 // The instruction result is the result of loading from the
8735 // hidden sret parameter.
8736 SmallVector<EVT, 1> PVTs;
8737 Type *PtrRetTy = OrigRetTy->getPointerTo(DL.getAllocaAddrSpace());
8738
8739 ComputeValueVTs(*this, DL, PtrRetTy, PVTs);
8740 assert(PVTs.size() == 1 && "Pointers should fit in one register")((PVTs.size() == 1 && "Pointers should fit in one register"
) ? static_cast<void> (0) : __assert_fail ("PVTs.size() == 1 && \"Pointers should fit in one register\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 8740, __PRETTY_FUNCTION__))
;
8741 EVT PtrVT = PVTs[0];
8742
8743 unsigned NumValues = RetTys.size();
8744 ReturnValues.resize(NumValues);
8745 SmallVector<SDValue, 4> Chains(NumValues);
8746
8747 // An aggregate return value cannot wrap around the address space, so
8748 // offsets to its parts don't wrap either.
8749 SDNodeFlags Flags;
8750 Flags.setNoUnsignedWrap(true);
8751
8752 for (unsigned i = 0; i < NumValues; ++i) {
8753 SDValue Add = CLI.DAG.getNode(ISD::ADD, CLI.DL, PtrVT, DemoteStackSlot,
8754 CLI.DAG.getConstant(Offsets[i], CLI.DL,
8755 PtrVT), Flags);
8756 SDValue L = CLI.DAG.getLoad(
8757 RetTys[i], CLI.DL, CLI.Chain, Add,
8758 MachinePointerInfo::getFixedStack(CLI.DAG.getMachineFunction(),
8759 DemoteStackIdx, Offsets[i]),
8760 /* Alignment = */ 1);
8761 ReturnValues[i] = L;
8762 Chains[i] = L.getValue(1);
8763 }
8764
8765 CLI.Chain = CLI.DAG.getNode(ISD::TokenFactor, CLI.DL, MVT::Other, Chains);
8766 } else {
8767 // Collect the legal value parts into potentially illegal values
8768 // that correspond to the original function's return values.
8769 Optional<ISD::NodeType> AssertOp;
8770 if (CLI.RetSExt)
8771 AssertOp = ISD::AssertSext;
8772 else if (CLI.RetZExt)
8773 AssertOp = ISD::AssertZext;
8774 unsigned CurReg = 0;
8775 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
8776 EVT VT = RetTys[I];
8777 MVT RegisterVT = getRegisterTypeForCallingConv(CLI.RetTy->getContext(),
8778 CLI.CallConv, VT);
8779 unsigned NumRegs = getNumRegistersForCallingConv(CLI.RetTy->getContext(),
8780 CLI.CallConv, VT);
8781
8782 ReturnValues.push_back(getCopyFromParts(CLI.DAG, CLI.DL, &InVals[CurReg],
8783 NumRegs, RegisterVT, VT, nullptr,
8784 CLI.CallConv, AssertOp));
8785 CurReg += NumRegs;
8786 }
8787
8788 // For a function returning void, there is no return value. We can't create
8789 // such a node, so we just return a null return value in that case. In
8790 // that case, nothing will actually look at the value.
8791 if (ReturnValues.empty())
8792 return std::make_pair(SDValue(), CLI.Chain);
8793 }
8794
8795 SDValue Res = CLI.DAG.getNode(ISD::MERGE_VALUES, CLI.DL,
8796 CLI.DAG.getVTList(RetTys), ReturnValues);
8797 return std::make_pair(Res, CLI.Chain);
8798}
8799
8800void TargetLowering::LowerOperationWrapper(SDNode *N,
8801 SmallVectorImpl<SDValue> &Results,
8802 SelectionDAG &DAG) const {
8803 if (SDValue Res = LowerOperation(SDValue(N, 0), DAG))
8804 Results.push_back(Res);
8805}
8806
8807SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
8808 llvm_unreachable("LowerOperation not implemented for this target!")::llvm::llvm_unreachable_internal("LowerOperation not implemented for this target!"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 8808)
;
8809}
8810
8811void
8812SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) {
8813 SDValue Op = getNonRegisterValue(V);
8814 assert((Op.getOpcode() != ISD::CopyFromReg ||(((Op.getOpcode() != ISD::CopyFromReg || cast<RegisterSDNode
>(Op.getOperand(1))->getReg() != Reg) && "Copy from a reg to the same reg!"
) ? static_cast<void> (0) : __assert_fail ("(Op.getOpcode() != ISD::CopyFromReg || cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) && \"Copy from a reg to the same reg!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 8816, __PRETTY_FUNCTION__))
8815 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&(((Op.getOpcode() != ISD::CopyFromReg || cast<RegisterSDNode
>(Op.getOperand(1))->getReg() != Reg) && "Copy from a reg to the same reg!"
) ? static_cast<void> (0) : __assert_fail ("(Op.getOpcode() != ISD::CopyFromReg || cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) && \"Copy from a reg to the same reg!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 8816, __PRETTY_FUNCTION__))
8816 "Copy from a reg to the same reg!")(((Op.getOpcode() != ISD::CopyFromReg || cast<RegisterSDNode
>(Op.getOperand(1))->getReg() != Reg) && "Copy from a reg to the same reg!"
) ? static_cast<void> (0) : __assert_fail ("(Op.getOpcode() != ISD::CopyFromReg || cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) && \"Copy from a reg to the same reg!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 8816, __PRETTY_FUNCTION__))
;
8817 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg")((!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg"
) ? static_cast<void> (0) : __assert_fail ("!TargetRegisterInfo::isPhysicalRegister(Reg) && \"Is a physreg\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 8817, __PRETTY_FUNCTION__))
;
8818
8819 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8820 // If this is an InlineAsm we have to match the registers required, not the
8821 // notional registers required by the type.
8822
8823 RegsForValue RFV(V->getContext(), TLI, DAG.getDataLayout(), Reg, V->getType(),
8824 None); // This is not an ABI copy.
8825 SDValue Chain = DAG.getEntryNode();
8826
8827 ISD::NodeType ExtendType = (FuncInfo.PreferredExtendType.find(V) ==
8828 FuncInfo.PreferredExtendType.end())
8829 ? ISD::ANY_EXTEND
8830 : FuncInfo.PreferredExtendType[V];
8831 RFV.getCopyToRegs(Op, DAG, getCurSDLoc(), Chain, nullptr, V, ExtendType);
8832 PendingExports.push_back(Chain);
8833}
8834
8835#include "llvm/CodeGen/SelectionDAGISel.h"
8836
8837/// isOnlyUsedInEntryBlock - If the specified argument is only used in the
8838/// entry block, return true. This includes arguments used by switches, since
8839/// the switch may expand into multiple basic blocks.
8840static bool isOnlyUsedInEntryBlock(const Argument *A, bool FastISel) {
8841 // With FastISel active, we may be splitting blocks, so force creation
8842 // of virtual registers for all non-dead arguments.
8843 if (FastISel)
8844 return A->use_empty();
8845
8846 const BasicBlock &Entry = A->getParent()->front();
8847 for (const User *U : A->users())
8848 if (cast<Instruction>(U)->getParent() != &Entry || isa<SwitchInst>(U))
8849 return false; // Use not in entry block.
8850
8851 return true;
8852}
8853
8854using ArgCopyElisionMapTy =
8855 DenseMap<const Argument *,
8856 std::pair<const AllocaInst *, const StoreInst *>>;
8857
8858/// Scan the entry block of the function in FuncInfo for arguments that look
8859/// like copies into a local alloca. Record any copied arguments in
8860/// ArgCopyElisionCandidates.
8861static void
8862findArgumentCopyElisionCandidates(const DataLayout &DL,
8863 FunctionLoweringInfo *FuncInfo,
8864 ArgCopyElisionMapTy &ArgCopyElisionCandidates) {
8865 // Record the state of every static alloca used in the entry block. Argument
8866 // allocas are all used in the entry block, so we need approximately as many
8867 // entries as we have arguments.
8868 enum StaticAllocaInfo { Unknown, Clobbered, Elidable };
8869 SmallDenseMap<const AllocaInst *, StaticAllocaInfo, 8> StaticAllocas;
8870 unsigned NumArgs = FuncInfo->Fn->arg_size();
8871 StaticAllocas.reserve(NumArgs * 2);
8872
8873 auto GetInfoIfStaticAlloca = [&](const Value *V) -> StaticAllocaInfo * {
8874 if (!V)
8875 return nullptr;
8876 V = V->stripPointerCasts();
8877 const auto *AI = dyn_cast<AllocaInst>(V);
8878 if (!AI || !AI->isStaticAlloca() || !FuncInfo->StaticAllocaMap.count(AI))
8879 return nullptr;
8880 auto Iter = StaticAllocas.insert({AI, Unknown});
8881 return &Iter.first->second;
8882 };
8883
8884 // Look for stores of arguments to static allocas. Look through bitcasts and
8885 // GEPs to handle type coercions, as long as the alloca is fully initialized
8886 // by the store. Any non-store use of an alloca escapes it and any subsequent
8887 // unanalyzed store might write it.
8888 // FIXME: Handle structs initialized with multiple stores.
8889 for (const Instruction &I : FuncInfo->Fn->getEntryBlock()) {
8890 // Look for stores, and handle non-store uses conservatively.
8891 const auto *SI = dyn_cast<StoreInst>(&I);
8892 if (!SI) {
8893 // We will look through cast uses, so ignore them completely.
8894 if (I.isCast())
8895 continue;
8896 // Ignore debug info intrinsics, they don't escape or store to allocas.
8897 if (isa<DbgInfoIntrinsic>(I))
8898 continue;
8899 // This is an unknown instruction. Assume it escapes or writes to all
8900 // static alloca operands.
8901 for (const Use &U : I.operands()) {
8902 if (StaticAllocaInfo *Info = GetInfoIfStaticAlloca(U))
8903 *Info = StaticAllocaInfo::Clobbered;
8904 }
8905 continue;
8906 }
8907
8908 // If the stored value is a static alloca, mark it as escaped.
8909 if (StaticAllocaInfo *Info = GetInfoIfStaticAlloca(SI->getValueOperand()))
8910 *Info = StaticAllocaInfo::Clobbered;
8911
8912 // Check if the destination is a static alloca.
8913 const Value *Dst = SI->getPointerOperand()->stripPointerCasts();
8914 StaticAllocaInfo *Info = GetInfoIfStaticAlloca(Dst);
8915 if (!Info)
8916 continue;
8917 const AllocaInst *AI = cast<AllocaInst>(Dst);
8918
8919 // Skip allocas that have been initialized or clobbered.
8920 if (*Info != StaticAllocaInfo::Unknown)
8921 continue;
8922
8923 // Check if the stored value is an argument, and that this store fully
8924 // initializes the alloca. Don't elide copies from the same argument twice.
8925 const Value *Val = SI->getValueOperand()->stripPointerCasts();
8926 const auto *Arg = dyn_cast<Argument>(Val);
8927 if (!Arg || Arg->hasInAllocaAttr() || Arg->hasByValAttr() ||
8928 Arg->getType()->isEmptyTy() ||
8929 DL.getTypeStoreSize(Arg->getType()) !=
8930 DL.getTypeAllocSize(AI->getAllocatedType()) ||
8931 ArgCopyElisionCandidates.count(Arg)) {
8932 *Info = StaticAllocaInfo::Clobbered;
8933 continue;
8934 }
8935
8936 LLVM_DEBUG(dbgs() << "Found argument copy elision candidate: " << *AIdo { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << "Found argument copy elision candidate: "
<< *AI << '\n'; } } while (false)
8937 << '\n')do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << "Found argument copy elision candidate: "
<< *AI << '\n'; } } while (false)
;
8938
8939 // Mark this alloca and store for argument copy elision.
8940 *Info = StaticAllocaInfo::Elidable;
8941 ArgCopyElisionCandidates.insert({Arg, {AI, SI}});
8942
8943 // Stop scanning if we've seen all arguments. This will happen early in -O0
8944 // builds, which is useful, because -O0 builds have large entry blocks and
8945 // many allocas.
8946 if (ArgCopyElisionCandidates.size() == NumArgs)
8947 break;
8948 }
8949}
8950
8951/// Try to elide argument copies from memory into a local alloca. Succeeds if
8952/// ArgVal is a load from a suitable fixed stack object.
8953static void tryToElideArgumentCopy(
8954 FunctionLoweringInfo *FuncInfo, SmallVectorImpl<SDValue> &Chains,
8955 DenseMap<int, int> &ArgCopyElisionFrameIndexMap,
8956 SmallPtrSetImpl<const Instruction *> &ElidedArgCopyInstrs,
8957 ArgCopyElisionMapTy &ArgCopyElisionCandidates, const Argument &Arg,
8958 SDValue ArgVal, bool &ArgHasUses) {
8959 // Check if this is a load from a fixed stack object.
8960 auto *LNode = dyn_cast<LoadSDNode>(ArgVal);
8961 if (!LNode)
8962 return;
8963 auto *FINode = dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode());
8964 if (!FINode)
8965 return;
8966
8967 // Check that the fixed stack object is the right size and alignment.
8968 // Look at the alignment that the user wrote on the alloca instead of looking
8969 // at the stack object.
8970 auto ArgCopyIter = ArgCopyElisionCandidates.find(&Arg);
8971 assert(ArgCopyIter != ArgCopyElisionCandidates.end())((ArgCopyIter != ArgCopyElisionCandidates.end()) ? static_cast
<void> (0) : __assert_fail ("ArgCopyIter != ArgCopyElisionCandidates.end()"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 8971, __PRETTY_FUNCTION__))
;
8972 const AllocaInst *AI = ArgCopyIter->second.first;
8973 int FixedIndex = FINode->getIndex();
8974 int &AllocaIndex = FuncInfo->StaticAllocaMap[AI];
8975 int OldIndex = AllocaIndex;
8976 MachineFrameInfo &MFI = FuncInfo->MF->getFrameInfo();
8977 if (MFI.getObjectSize(FixedIndex) != MFI.getObjectSize(OldIndex)) {
8978 LLVM_DEBUG(do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << " argument copy elision failed due to bad fixed stack "
"object size\n"; } } while (false)
8979 dbgs() << " argument copy elision failed due to bad fixed stack "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << " argument copy elision failed due to bad fixed stack "
"object size\n"; } } while (false)
8980 "object size\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << " argument copy elision failed due to bad fixed stack "
"object size\n"; } } while (false)
;
8981 return;
8982 }
8983 unsigned RequiredAlignment = AI->getAlignment();
8984 if (!RequiredAlignment) {
8985 RequiredAlignment = FuncInfo->MF->getDataLayout().getABITypeAlignment(
8986 AI->getAllocatedType());
8987 }
8988 if (MFI.getObjectAlignment(FixedIndex) < RequiredAlignment) {
8989 LLVM_DEBUG(dbgs() << " argument copy elision failed: alignment of alloca "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << " argument copy elision failed: alignment of alloca "
"greater than stack argument alignment (" << RequiredAlignment
<< " vs " << MFI.getObjectAlignment(FixedIndex) <<
")\n"; } } while (false)
8990 "greater than stack argument alignment ("do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << " argument copy elision failed: alignment of alloca "
"greater than stack argument alignment (" << RequiredAlignment
<< " vs " << MFI.getObjectAlignment(FixedIndex) <<
")\n"; } } while (false)
8991 << RequiredAlignment << " vs "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << " argument copy elision failed: alignment of alloca "
"greater than stack argument alignment (" << RequiredAlignment
<< " vs " << MFI.getObjectAlignment(FixedIndex) <<
")\n"; } } while (false)
8992 << MFI.getObjectAlignment(FixedIndex) << ")\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << " argument copy elision failed: alignment of alloca "
"greater than stack argument alignment (" << RequiredAlignment
<< " vs " << MFI.getObjectAlignment(FixedIndex) <<
")\n"; } } while (false)
;
8993 return;
8994 }
8995
8996 // Perform the elision. Delete the old stack object and replace its only use
8997 // in the variable info map. Mark the stack object as mutable.
8998 LLVM_DEBUG({do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { { dbgs() << "Eliding argument copy from " <<
Arg << " to " << *AI << '\n' << " Replacing frame index "
<< OldIndex << " with " << FixedIndex <<
'\n'; }; } } while (false)
8999 dbgs() << "Eliding argument copy from " << Arg << " to " << *AI << '\n'do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { { dbgs() << "Eliding argument copy from " <<
Arg << " to " << *AI << '\n' << " Replacing frame index "
<< OldIndex << " with " << FixedIndex <<
'\n'; }; } } while (false)
9000 << " Replacing frame index " << OldIndex << " with " << FixedIndexdo { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { { dbgs() << "Eliding argument copy from " <<
Arg << " to " << *AI << '\n' << " Replacing frame index "
<< OldIndex << " with " << FixedIndex <<
'\n'; }; } } while (false)
9001 << '\n';do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { { dbgs() << "Eliding argument copy from " <<
Arg << " to " << *AI << '\n' << " Replacing frame index "
<< OldIndex << " with " << FixedIndex <<
'\n'; }; } } while (false)
9002 })do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { { dbgs() << "Eliding argument copy from " <<
Arg << " to " << *AI << '\n' << " Replacing frame index "
<< OldIndex << " with " << FixedIndex <<
'\n'; }; } } while (false)
;
9003 MFI.RemoveStackObject(OldIndex);
9004 MFI.setIsImmutableObjectIndex(FixedIndex, false);
9005 AllocaIndex = FixedIndex;
9006 ArgCopyElisionFrameIndexMap.insert({OldIndex, FixedIndex});
9007 Chains.push_back(ArgVal.getValue(1));
9008
9009 // Avoid emitting code for the store implementing the copy.
9010 const StoreInst *SI = ArgCopyIter->second.second;
9011 ElidedArgCopyInstrs.insert(SI);
9012
9013 // Check for uses of the argument again so that we can avoid exporting ArgVal
9014 // if it is't used by anything other than the store.
9015 for (const Value *U : Arg.users()) {
9016 if (U != SI) {
9017 ArgHasUses = true;
9018 break;
9019 }
9020 }
9021}
9022
9023void SelectionDAGISel::LowerArguments(const Function &F) {
9024 SelectionDAG &DAG = SDB->DAG;
9025 SDLoc dl = SDB->getCurSDLoc();
9026 const DataLayout &DL = DAG.getDataLayout();
9027 SmallVector<ISD::InputArg, 16> Ins;
9028
9029 if (!FuncInfo->CanLowerReturn) {
9030 // Put in an sret pointer parameter before all the other parameters.
9031 SmallVector<EVT, 1> ValueVTs;
9032 ComputeValueVTs(*TLI, DAG.getDataLayout(),
9033 F.getReturnType()->getPointerTo(
9034 DAG.getDataLayout().getAllocaAddrSpace()),
9035 ValueVTs);
9036
9037 // NOTE: Assuming that a pointer will never break down to more than one VT
9038 // or one register.
9039 ISD::ArgFlagsTy Flags;
9040 Flags.setSRet();
9041 MVT RegisterVT = TLI->getRegisterType(*DAG.getContext(), ValueVTs[0]);
9042 ISD::InputArg RetArg(Flags, RegisterVT, ValueVTs[0], true,
9043 ISD::InputArg::NoArgIndex, 0);
9044 Ins.push_back(RetArg);
9045 }
9046
9047 // Look for stores of arguments to static allocas. Mark such arguments with a
9048 // flag to ask the target to give us the memory location of that argument if
9049 // available.
9050 ArgCopyElisionMapTy ArgCopyElisionCandidates;
9051 findArgumentCopyElisionCandidates(DL, FuncInfo, ArgCopyElisionCandidates);
9052
9053 // Set up the incoming argument description vector.
9054 for (const Argument &Arg : F.args()) {
9055 unsigned ArgNo = Arg.getArgNo();
9056 SmallVector<EVT, 4> ValueVTs;
9057 ComputeValueVTs(*TLI, DAG.getDataLayout(), Arg.getType(), ValueVTs);
9058 bool isArgValueUsed = !Arg.use_empty();
9059 unsigned PartBase = 0;
9060 Type *FinalType = Arg.getType();
9061 if (Arg.hasAttribute(Attribute::ByVal))
9062 FinalType = cast<PointerType>(FinalType)->getElementType();
9063 bool NeedsRegBlock = TLI->functionArgumentNeedsConsecutiveRegisters(
9064 FinalType, F.getCallingConv(), F.isVarArg());
9065 for (unsigned Value = 0, NumValues = ValueVTs.size();
9066 Value != NumValues; ++Value) {
9067 EVT VT = ValueVTs[Value];
9068 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
9069 ISD::ArgFlagsTy Flags;
9070
9071 // Certain targets (such as MIPS), may have a different ABI alignment
9072 // for a type depending on the context. Give the target a chance to
9073 // specify the alignment it wants.
9074 unsigned OriginalAlignment =
9075 TLI->getABIAlignmentForCallingConv(ArgTy, DL);
9076
9077 if (Arg.hasAttribute(Attribute::ZExt))
9078 Flags.setZExt();
9079 if (Arg.hasAttribute(Attribute::SExt))
9080 Flags.setSExt();
9081 if (Arg.hasAttribute(Attribute::InReg)) {
9082 // If we are using vectorcall calling convention, a structure that is
9083 // passed InReg - is surely an HVA
9084 if (F.getCallingConv() == CallingConv::X86_VectorCall &&
9085 isa<StructType>(Arg.getType())) {
9086 // The first value of a structure is marked
9087 if (0 == Value)
9088 Flags.setHvaStart();
9089 Flags.setHva();
9090 }
9091 // Set InReg Flag
9092 Flags.setInReg();
9093 }
9094 if (Arg.hasAttribute(Attribute::StructRet))
9095 Flags.setSRet();
9096 if (Arg.hasAttribute(Attribute::SwiftSelf))
9097 Flags.setSwiftSelf();
9098 if (Arg.hasAttribute(Attribute::SwiftError))
9099 Flags.setSwiftError();
9100 if (Arg.hasAttribute(Attribute::ByVal))
9101 Flags.setByVal();
9102 if (Arg.hasAttribute(Attribute::InAlloca)) {
9103 Flags.setInAlloca();
9104 // Set the byval flag for CCAssignFn callbacks that don't know about
9105 // inalloca. This way we can know how many bytes we should've allocated
9106 // and how many bytes a callee cleanup function will pop. If we port
9107 // inalloca to more targets, we'll have to add custom inalloca handling
9108 // in the various CC lowering callbacks.
9109 Flags.setByVal();
9110 }
9111 if (F.getCallingConv() == CallingConv::X86_INTR) {
9112 // IA Interrupt passes frame (1st parameter) by value in the stack.
9113 if (ArgNo == 0)
9114 Flags.setByVal();
9115 }
9116 if (Flags.isByVal() || Flags.isInAlloca()) {
9117 PointerType *Ty = cast<PointerType>(Arg.getType());
9118 Type *ElementTy = Ty->getElementType();
9119 Flags.setByValSize(DL.getTypeAllocSize(ElementTy));
9120 // For ByVal, alignment should be passed from FE. BE will guess if
9121 // this info is not there but there are cases it cannot get right.
9122 unsigned FrameAlign;
9123 if (Arg.getParamAlignment())
9124 FrameAlign = Arg.getParamAlignment();
9125 else
9126 FrameAlign = TLI->getByValTypeAlignment(ElementTy, DL);
9127 Flags.setByValAlign(FrameAlign);
9128 }
9129 if (Arg.hasAttribute(Attribute::Nest))
9130 Flags.setNest();
9131 if (NeedsRegBlock)
9132 Flags.setInConsecutiveRegs();
9133 Flags.setOrigAlign(OriginalAlignment);
9134 if (ArgCopyElisionCandidates.count(&Arg))
9135 Flags.setCopyElisionCandidate();
9136
9137 MVT RegisterVT = TLI->getRegisterTypeForCallingConv(
9138 *CurDAG->getContext(), F.getCallingConv(), VT);
9139 unsigned NumRegs = TLI->getNumRegistersForCallingConv(
9140 *CurDAG->getContext(), F.getCallingConv(), VT);
9141 for (unsigned i = 0; i != NumRegs; ++i) {
9142 ISD::InputArg MyFlags(Flags, RegisterVT, VT, isArgValueUsed,
9143 ArgNo, PartBase+i*RegisterVT.getStoreSize());
9144 if (NumRegs > 1 && i == 0)
9145 MyFlags.Flags.setSplit();
9146 // if it isn't first piece, alignment must be 1
9147 else if (i > 0) {
9148 MyFlags.Flags.setOrigAlign(1);
9149 if (i == NumRegs - 1)
9150 MyFlags.Flags.setSplitEnd();
9151 }
9152 Ins.push_back(MyFlags);
9153 }
9154 if (NeedsRegBlock && Value == NumValues - 1)
9155 Ins[Ins.size() - 1].Flags.setInConsecutiveRegsLast();
9156 PartBase += VT.getStoreSize();
9157 }
9158 }
9159
9160 // Call the target to set up the argument values.
9161 SmallVector<SDValue, 8> InVals;
9162 SDValue NewRoot = TLI->LowerFormalArguments(
9163 DAG.getRoot(), F.getCallingConv(), F.isVarArg(), Ins, dl, DAG, InVals);
9164
9165 // Verify that the target's LowerFormalArguments behaved as expected.
9166 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&((NewRoot.getNode() && NewRoot.getValueType() == MVT::
Other && "LowerFormalArguments didn't return a valid chain!"
) ? static_cast<void> (0) : __assert_fail ("NewRoot.getNode() && NewRoot.getValueType() == MVT::Other && \"LowerFormalArguments didn't return a valid chain!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9167, __PRETTY_FUNCTION__))
9167 "LowerFormalArguments didn't return a valid chain!")((NewRoot.getNode() && NewRoot.getValueType() == MVT::
Other && "LowerFormalArguments didn't return a valid chain!"
) ? static_cast<void> (0) : __assert_fail ("NewRoot.getNode() && NewRoot.getValueType() == MVT::Other && \"LowerFormalArguments didn't return a valid chain!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9167, __PRETTY_FUNCTION__))
;
9168 assert(InVals.size() == Ins.size() &&((InVals.size() == Ins.size() && "LowerFormalArguments didn't emit the correct number of values!"
) ? static_cast<void> (0) : __assert_fail ("InVals.size() == Ins.size() && \"LowerFormalArguments didn't emit the correct number of values!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9169, __PRETTY_FUNCTION__))
9169 "LowerFormalArguments didn't emit the correct number of values!")((InVals.size() == Ins.size() && "LowerFormalArguments didn't emit the correct number of values!"
) ? static_cast<void> (0) : __assert_fail ("InVals.size() == Ins.size() && \"LowerFormalArguments didn't emit the correct number of values!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9169, __PRETTY_FUNCTION__))
;
9170 LLVM_DEBUG({do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { { for (unsigned i = 0, e = Ins.size(); i != e; ++
i) { ((InVals[i].getNode() && "LowerFormalArguments emitted a null value!"
) ? static_cast<void> (0) : __assert_fail ("InVals[i].getNode() && \"LowerFormalArguments emitted a null value!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9173, __PRETTY_FUNCTION__)); ((EVT(Ins[i].VT) == InVals[i].
getValueType() && "LowerFormalArguments emitted a value with the wrong type!"
) ? static_cast<void> (0) : __assert_fail ("EVT(Ins[i].VT) == InVals[i].getValueType() && \"LowerFormalArguments emitted a value with the wrong type!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9175, __PRETTY_FUNCTION__)); } }; } } while (false)
9171 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { { for (unsigned i = 0, e = Ins.size(); i != e; ++
i) { ((InVals[i].getNode() && "LowerFormalArguments emitted a null value!"
) ? static_cast<void> (0) : __assert_fail ("InVals[i].getNode() && \"LowerFormalArguments emitted a null value!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9173, __PRETTY_FUNCTION__)); ((EVT(Ins[i].VT) == InVals[i].
getValueType() && "LowerFormalArguments emitted a value with the wrong type!"
) ? static_cast<void> (0) : __assert_fail ("EVT(Ins[i].VT) == InVals[i].getValueType() && \"LowerFormalArguments emitted a value with the wrong type!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9175, __PRETTY_FUNCTION__)); } }; } } while (false)
9172 assert(InVals[i].getNode() &&do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { { for (unsigned i = 0, e = Ins.size(); i != e; ++
i) { ((InVals[i].getNode() && "LowerFormalArguments emitted a null value!"
) ? static_cast<void> (0) : __assert_fail ("InVals[i].getNode() && \"LowerFormalArguments emitted a null value!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9173, __PRETTY_FUNCTION__)); ((EVT(Ins[i].VT) == InVals[i].
getValueType() && "LowerFormalArguments emitted a value with the wrong type!"
) ? static_cast<void> (0) : __assert_fail ("EVT(Ins[i].VT) == InVals[i].getValueType() && \"LowerFormalArguments emitted a value with the wrong type!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9175, __PRETTY_FUNCTION__)); } }; } } while (false)
9173 "LowerFormalArguments emitted a null value!");do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { { for (unsigned i = 0, e = Ins.size(); i != e; ++
i) { ((InVals[i].getNode() && "LowerFormalArguments emitted a null value!"
) ? static_cast<void> (0) : __assert_fail ("InVals[i].getNode() && \"LowerFormalArguments emitted a null value!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9173, __PRETTY_FUNCTION__)); ((EVT(Ins[i].VT) == InVals[i].
getValueType() && "LowerFormalArguments emitted a value with the wrong type!"
) ? static_cast<void> (0) : __assert_fail ("EVT(Ins[i].VT) == InVals[i].getValueType() && \"LowerFormalArguments emitted a value with the wrong type!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9175, __PRETTY_FUNCTION__)); } }; } } while (false)
9174 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { { for (unsigned i = 0, e = Ins.size(); i != e; ++
i) { ((InVals[i].getNode() && "LowerFormalArguments emitted a null value!"
) ? static_cast<void> (0) : __assert_fail ("InVals[i].getNode() && \"LowerFormalArguments emitted a null value!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9173, __PRETTY_FUNCTION__)); ((EVT(Ins[i].VT) == InVals[i].
getValueType() && "LowerFormalArguments emitted a value with the wrong type!"
) ? static_cast<void> (0) : __assert_fail ("EVT(Ins[i].VT) == InVals[i].getValueType() && \"LowerFormalArguments emitted a value with the wrong type!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9175, __PRETTY_FUNCTION__)); } }; } } while (false)
9175 "LowerFormalArguments emitted a value with the wrong type!");do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { { for (unsigned i = 0, e = Ins.size(); i != e; ++
i) { ((InVals[i].getNode() && "LowerFormalArguments emitted a null value!"
) ? static_cast<void> (0) : __assert_fail ("InVals[i].getNode() && \"LowerFormalArguments emitted a null value!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9173, __PRETTY_FUNCTION__)); ((EVT(Ins[i].VT) == InVals[i].
getValueType() && "LowerFormalArguments emitted a value with the wrong type!"
) ? static_cast<void> (0) : __assert_fail ("EVT(Ins[i].VT) == InVals[i].getValueType() && \"LowerFormalArguments emitted a value with the wrong type!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9175, __PRETTY_FUNCTION__)); } }; } } while (false)
9176 }do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { { for (unsigned i = 0, e = Ins.size(); i != e; ++
i) { ((InVals[i].getNode() && "LowerFormalArguments emitted a null value!"
) ? static_cast<void> (0) : __assert_fail ("InVals[i].getNode() && \"LowerFormalArguments emitted a null value!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9173, __PRETTY_FUNCTION__)); ((EVT(Ins[i].VT) == InVals[i].
getValueType() && "LowerFormalArguments emitted a value with the wrong type!"
) ? static_cast<void> (0) : __assert_fail ("EVT(Ins[i].VT) == InVals[i].getValueType() && \"LowerFormalArguments emitted a value with the wrong type!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9175, __PRETTY_FUNCTION__)); } }; } } while (false)
9177 })do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { { for (unsigned i = 0, e = Ins.size(); i != e; ++
i) { ((InVals[i].getNode() && "LowerFormalArguments emitted a null value!"
) ? static_cast<void> (0) : __assert_fail ("InVals[i].getNode() && \"LowerFormalArguments emitted a null value!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9173, __PRETTY_FUNCTION__)); ((EVT(Ins[i].VT) == InVals[i].
getValueType() && "LowerFormalArguments emitted a value with the wrong type!"
) ? static_cast<void> (0) : __assert_fail ("EVT(Ins[i].VT) == InVals[i].getValueType() && \"LowerFormalArguments emitted a value with the wrong type!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9175, __PRETTY_FUNCTION__)); } }; } } while (false)
;
9178
9179 // Update the DAG with the new chain value resulting from argument lowering.
9180 DAG.setRoot(NewRoot);
9181
9182 // Set up the argument values.
9183 unsigned i = 0;
9184 if (!FuncInfo->CanLowerReturn) {
9185 // Create a virtual register for the sret pointer, and put in a copy
9186 // from the sret argument into it.
9187 SmallVector<EVT, 1> ValueVTs;
9188 ComputeValueVTs(*TLI, DAG.getDataLayout(),
9189 F.getReturnType()->getPointerTo(
9190 DAG.getDataLayout().getAllocaAddrSpace()),
9191 ValueVTs);
9192 MVT VT = ValueVTs[0].getSimpleVT();
9193 MVT RegVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
9194 Optional<ISD::NodeType> AssertOp = None;
9195 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1, RegVT, VT,
9196 nullptr, F.getCallingConv(), AssertOp);
9197
9198 MachineFunction& MF = SDB->DAG.getMachineFunction();
9199 MachineRegisterInfo& RegInfo = MF.getRegInfo();
9200 unsigned SRetReg = RegInfo.createVirtualRegister(TLI->getRegClassFor(RegVT));
9201 FuncInfo->DemoteRegister = SRetReg;
9202 NewRoot =
9203 SDB->DAG.getCopyToReg(NewRoot, SDB->getCurSDLoc(), SRetReg, ArgValue);
9204 DAG.setRoot(NewRoot);
9205
9206 // i indexes lowered arguments. Bump it past the hidden sret argument.
9207 ++i;
9208 }
9209
9210 SmallVector<SDValue, 4> Chains;
9211 DenseMap<int, int> ArgCopyElisionFrameIndexMap;
9212 for (const Argument &Arg : F.args()) {
9213 SmallVector<SDValue, 4> ArgValues;
9214 SmallVector<EVT, 4> ValueVTs;
9215 ComputeValueVTs(*TLI, DAG.getDataLayout(), Arg.getType(), ValueVTs);
9216 unsigned NumValues = ValueVTs.size();
9217 if (NumValues == 0)
9218 continue;
9219
9220 bool ArgHasUses = !Arg.use_empty();
9221
9222 // Elide the copying store if the target loaded this argument from a
9223 // suitable fixed stack object.
9224 if (Ins[i].Flags.isCopyElisionCandidate()) {
9225 tryToElideArgumentCopy(FuncInfo, Chains, ArgCopyElisionFrameIndexMap,
9226 ElidedArgCopyInstrs, ArgCopyElisionCandidates, Arg,
9227 InVals[i], ArgHasUses);
9228 }
9229
9230 // If this argument is unused then remember its value. It is used to generate
9231 // debugging information.
9232 bool isSwiftErrorArg =
9233 TLI->supportSwiftError() &&
9234 Arg.hasAttribute(Attribute::SwiftError);
9235 if (!ArgHasUses && !isSwiftErrorArg) {
9236 SDB->setUnusedArgValue(&Arg, InVals[i]);
9237
9238 // Also remember any frame index for use in FastISel.
9239 if (FrameIndexSDNode *FI =
9240 dyn_cast<FrameIndexSDNode>(InVals[i].getNode()))
9241 FuncInfo->setArgumentFrameIndex(&Arg, FI->getIndex());
9242 }
9243
9244 for (unsigned Val = 0; Val != NumValues; ++Val) {
9245 EVT VT = ValueVTs[Val];
9246 MVT PartVT = TLI->getRegisterTypeForCallingConv(*CurDAG->getContext(),
9247 F.getCallingConv(), VT);
9248 unsigned NumParts = TLI->getNumRegistersForCallingConv(
9249 *CurDAG->getContext(), F.getCallingConv(), VT);
9250
9251 // Even an apparant 'unused' swifterror argument needs to be returned. So
9252 // we do generate a copy for it that can be used on return from the
9253 // function.
9254 if (ArgHasUses || isSwiftErrorArg) {
9255 Optional<ISD::NodeType> AssertOp;
9256 if (Arg.hasAttribute(Attribute::SExt))
9257 AssertOp = ISD::AssertSext;
9258 else if (Arg.hasAttribute(Attribute::ZExt))
9259 AssertOp = ISD::AssertZext;
9260
9261 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i], NumParts,
9262 PartVT, VT, nullptr,
9263 F.getCallingConv(), AssertOp));
9264 }
9265
9266 i += NumParts;
9267 }
9268
9269 // We don't need to do anything else for unused arguments.
9270 if (ArgValues.empty())
9271 continue;
9272
9273 // Note down frame index.
9274 if (FrameIndexSDNode *FI =
9275 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode()))
9276 FuncInfo->setArgumentFrameIndex(&Arg, FI->getIndex());
9277
9278 SDValue Res = DAG.getMergeValues(makeArrayRef(ArgValues.data(), NumValues),
9279 SDB->getCurSDLoc());
9280
9281 SDB->setValue(&Arg, Res);
9282 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) {
9283 // We want to associate the argument with the frame index, among
9284 // involved operands, that correspond to the lowest address. The
9285 // getCopyFromParts function, called earlier, is swapping the order of
9286 // the operands to BUILD_PAIR depending on endianness. The result of
9287 // that swapping is that the least significant bits of the argument will
9288 // be in the first operand of the BUILD_PAIR node, and the most
9289 // significant bits will be in the second operand.
9290 unsigned LowAddressOp = DAG.getDataLayout().isBigEndian() ? 1 : 0;
9291 if (LoadSDNode *LNode =
9292 dyn_cast<LoadSDNode>(Res.getOperand(LowAddressOp).getNode()))
9293 if (FrameIndexSDNode *FI =
9294 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
9295 FuncInfo->setArgumentFrameIndex(&Arg, FI->getIndex());
9296 }
9297
9298 // Update the SwiftErrorVRegDefMap.
9299 if (Res.getOpcode() == ISD::CopyFromReg && isSwiftErrorArg) {
9300 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg();
9301 if (TargetRegisterInfo::isVirtualRegister(Reg))
9302 FuncInfo->setCurrentSwiftErrorVReg(FuncInfo->MBB,
9303 FuncInfo->SwiftErrorArg, Reg);
9304 }
9305
9306 // If this argument is live outside of the entry block, insert a copy from
9307 // wherever we got it to the vreg that other BB's will reference it as.
9308 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) {
9309 // If we can, though, try to skip creating an unnecessary vreg.
9310 // FIXME: This isn't very clean... it would be nice to make this more
9311 // general. It's also subtly incompatible with the hacks FastISel
9312 // uses with vregs.
9313 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg();
9314 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
9315 FuncInfo->ValueMap[&Arg] = Reg;
9316 continue;
9317 }
9318 }
9319 if (!isOnlyUsedInEntryBlock(&Arg, TM.Options.EnableFastISel)) {
9320 FuncInfo->InitializeRegForValue(&Arg);
9321 SDB->CopyToExportRegsIfNeeded(&Arg);
9322 }
9323 }
9324
9325 if (!Chains.empty()) {
9326 Chains.push_back(NewRoot);
9327 NewRoot = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
9328 }
9329
9330 DAG.setRoot(NewRoot);
9331
9332 assert(i == InVals.size() && "Argument register count mismatch!")((i == InVals.size() && "Argument register count mismatch!"
) ? static_cast<void> (0) : __assert_fail ("i == InVals.size() && \"Argument register count mismatch!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9332, __PRETTY_FUNCTION__))
;
9333
9334 // If any argument copy elisions occurred and we have debug info, update the
9335 // stale frame indices used in the dbg.declare variable info table.
9336 MachineFunction::VariableDbgInfoMapTy &DbgDeclareInfo = MF->getVariableDbgInfo();
9337 if (!DbgDeclareInfo.empty() && !ArgCopyElisionFrameIndexMap.empty()) {
9338 for (MachineFunction::VariableDbgInfo &VI : DbgDeclareInfo) {
9339 auto I = ArgCopyElisionFrameIndexMap.find(VI.Slot);
9340 if (I != ArgCopyElisionFrameIndexMap.end())
9341 VI.Slot = I->second;
9342 }
9343 }
9344
9345 // Finally, if the target has anything special to do, allow it to do so.
9346 EmitFunctionEntryCode();
9347}
9348
9349/// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
9350/// ensure constants are generated when needed. Remember the virtual registers
9351/// that need to be added to the Machine PHI nodes as input. We cannot just
9352/// directly add them, because expansion might result in multiple MBB's for one
9353/// BB. As such, the start of the BB might correspond to a different MBB than
9354/// the end.
9355void
9356SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
9357 const Instruction *TI = LLVMBB->getTerminator();
9358
9359 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
9360
9361 // Check PHI nodes in successors that expect a value to be available from this
9362 // block.
9363 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
9364 const BasicBlock *SuccBB = TI->getSuccessor(succ);
9365 if (!isa<PHINode>(SuccBB->begin())) continue;
9366 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
9367
9368 // If this terminator has multiple identical successors (common for
9369 // switches), only handle each succ once.
9370 if (!SuccsHandled.insert(SuccMBB).second)
9371 continue;
9372
9373 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
9374
9375 // At this point we know that there is a 1-1 correspondence between LLVM PHI
9376 // nodes and Machine PHI nodes, but the incoming operands have not been
9377 // emitted yet.
9378 for (const PHINode &PN : SuccBB->phis()) {
9379 // Ignore dead phi's.
9380 if (PN.use_empty())
9381 continue;
9382
9383 // Skip empty types
9384 if (PN.getType()->isEmptyTy())
9385 continue;
9386
9387 unsigned Reg;
9388 const Value *PHIOp = PN.getIncomingValueForBlock(LLVMBB);
9389
9390 if (const Constant *C = dyn_cast<Constant>(PHIOp)) {
9391 unsigned &RegOut = ConstantsOut[C];
9392 if (RegOut == 0) {
9393 RegOut = FuncInfo.CreateRegs(C->getType());
9394 CopyValueToVirtualRegister(C, RegOut);
9395 }
9396 Reg = RegOut;
9397 } else {
9398 DenseMap<const Value *, unsigned>::iterator I =
9399 FuncInfo.ValueMap.find(PHIOp);
9400 if (I != FuncInfo.ValueMap.end())
9401 Reg = I->second;
9402 else {
9403 assert(isa<AllocaInst>(PHIOp) &&((isa<AllocaInst>(PHIOp) && FuncInfo.StaticAllocaMap
.count(cast<AllocaInst>(PHIOp)) && "Didn't codegen value into a register!??"
) ? static_cast<void> (0) : __assert_fail ("isa<AllocaInst>(PHIOp) && FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) && \"Didn't codegen value into a register!??\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9405, __PRETTY_FUNCTION__))
9404 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&((isa<AllocaInst>(PHIOp) && FuncInfo.StaticAllocaMap
.count(cast<AllocaInst>(PHIOp)) && "Didn't codegen value into a register!??"
) ? static_cast<void> (0) : __assert_fail ("isa<AllocaInst>(PHIOp) && FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) && \"Didn't codegen value into a register!??\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9405, __PRETTY_FUNCTION__))
9405 "Didn't codegen value into a register!??")((isa<AllocaInst>(PHIOp) && FuncInfo.StaticAllocaMap
.count(cast<AllocaInst>(PHIOp)) && "Didn't codegen value into a register!??"
) ? static_cast<void> (0) : __assert_fail ("isa<AllocaInst>(PHIOp) && FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) && \"Didn't codegen value into a register!??\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9405, __PRETTY_FUNCTION__))
;
9406 Reg = FuncInfo.CreateRegs(PHIOp->getType());
9407 CopyValueToVirtualRegister(PHIOp, Reg);
9408 }
9409 }
9410
9411 // Remember that this register needs to added to the machine PHI node as
9412 // the input for this MBB.
9413 SmallVector<EVT, 4> ValueVTs;
9414 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9415 ComputeValueVTs(TLI, DAG.getDataLayout(), PN.getType(), ValueVTs);
9416 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
9417 EVT VT = ValueVTs[vti];
9418 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT);
9419 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
9420 FuncInfo.PHINodesToUpdate.push_back(
9421 std::make_pair(&*MBBI++, Reg + i));
9422 Reg += NumRegisters;
9423 }
9424 }
9425 }
9426
9427 ConstantsOut.clear();
9428}
9429
9430/// Add a successor MBB to ParentMBB< creating a new MachineBB for BB if SuccMBB
9431/// is 0.
9432MachineBasicBlock *
9433SelectionDAGBuilder::StackProtectorDescriptor::
9434AddSuccessorMBB(const BasicBlock *BB,
9435 MachineBasicBlock *ParentMBB,
9436 bool IsLikely,
9437 MachineBasicBlock *SuccMBB) {
9438 // If SuccBB has not been created yet, create it.
9439 if (!SuccMBB) {
9440 MachineFunction *MF = ParentMBB->getParent();
9441 MachineFunction::iterator BBI(ParentMBB);
9442 SuccMBB = MF->CreateMachineBasicBlock(BB);
9443 MF->insert(++BBI, SuccMBB);
9444 }
9445 // Add it as a successor of ParentMBB.
9446 ParentMBB->addSuccessor(
9447 SuccMBB, BranchProbabilityInfo::getBranchProbStackProtector(IsLikely));
9448 return SuccMBB;
9449}
9450
9451MachineBasicBlock *SelectionDAGBuilder::NextBlock(MachineBasicBlock *MBB) {
9452 MachineFunction::iterator I(MBB);
9453 if (++I == FuncInfo.MF->end())
9454 return nullptr;
9455 return &*I;
9456}
9457
9458/// During lowering new call nodes can be created (such as memset, etc.).
9459/// Those will become new roots of the current DAG, but complications arise
9460/// when they are tail calls. In such cases, the call lowering will update
9461/// the root, but the builder still needs to know that a tail call has been
9462/// lowered in order to avoid generating an additional return.
9463void SelectionDAGBuilder::updateDAGForMaybeTailCall(SDValue MaybeTC) {
9464 // If the node is null, we do have a tail call.
9465 if (MaybeTC.getNode() != nullptr)
9466 DAG.setRoot(MaybeTC);
9467 else
9468 HasTailCall = true;
9469}
9470
9471uint64_t
9472SelectionDAGBuilder::getJumpTableRange(const CaseClusterVector &Clusters,
9473 unsigned First, unsigned Last) const {
9474 assert(Last >= First)((Last >= First) ? static_cast<void> (0) : __assert_fail
("Last >= First", "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9474, __PRETTY_FUNCTION__))
;
9475 const APInt &LowCase = Clusters[First].Low->getValue();
9476 const APInt &HighCase = Clusters[Last].High->getValue();
9477 assert(LowCase.getBitWidth() == HighCase.getBitWidth())((LowCase.getBitWidth() == HighCase.getBitWidth()) ? static_cast
<void> (0) : __assert_fail ("LowCase.getBitWidth() == HighCase.getBitWidth()"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9477, __PRETTY_FUNCTION__))
;
9478
9479 // FIXME: A range of consecutive cases has 100% density, but only requires one
9480 // comparison to lower. We should discriminate against such consecutive ranges
9481 // in jump tables.
9482
9483 return (HighCase - LowCase).getLimitedValue((UINT64_MAX(18446744073709551615UL) - 1) / 100) + 1;
9484}
9485
9486uint64_t SelectionDAGBuilder::getJumpTableNumCases(
9487 const SmallVectorImpl<unsigned> &TotalCases, unsigned First,
9488 unsigned Last) const {
9489 assert(Last >= First)((Last >= First) ? static_cast<void> (0) : __assert_fail
("Last >= First", "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9489, __PRETTY_FUNCTION__))
;
9490 assert(TotalCases[Last] >= TotalCases[First])((TotalCases[Last] >= TotalCases[First]) ? static_cast<
void> (0) : __assert_fail ("TotalCases[Last] >= TotalCases[First]"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9490, __PRETTY_FUNCTION__))
;
9491 uint64_t NumCases =
9492 TotalCases[Last] - (First == 0 ? 0 : TotalCases[First - 1]);
9493 return NumCases;
9494}
9495
9496bool SelectionDAGBuilder::buildJumpTable(const CaseClusterVector &Clusters,
9497 unsigned First, unsigned Last,
9498 const SwitchInst *SI,
9499 MachineBasicBlock *DefaultMBB,
9500 CaseCluster &JTCluster) {
9501 assert(First <= Last)((First <= Last) ? static_cast<void> (0) : __assert_fail
("First <= Last", "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9501, __PRETTY_FUNCTION__))
;
9502
9503 auto Prob = BranchProbability::getZero();
9504 unsigned NumCmps = 0;
9505 std::vector<MachineBasicBlock*> Table;
9506 DenseMap<MachineBasicBlock*, BranchProbability> JTProbs;
9507
9508 // Initialize probabilities in JTProbs.
9509 for (unsigned I = First; I <= Last; ++I)
9510 JTProbs[Clusters[I].MBB] = BranchProbability::getZero();
9511
9512 for (unsigned I = First; I <= Last; ++I) {
9513 assert(Clusters[I].Kind == CC_Range)((Clusters[I].Kind == CC_Range) ? static_cast<void> (0)
: __assert_fail ("Clusters[I].Kind == CC_Range", "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9513, __PRETTY_FUNCTION__))
;
9514 Prob += Clusters[I].Prob;
9515 const APInt &Low = Clusters[I].Low->getValue();
9516 const APInt &High = Clusters[I].High->getValue();
9517 NumCmps += (Low == High) ? 1 : 2;
9518 if (I != First) {
9519 // Fill the gap between this and the previous cluster.
9520 const APInt &PreviousHigh = Clusters[I - 1].High->getValue();
9521 assert(PreviousHigh.slt(Low))((PreviousHigh.slt(Low)) ? static_cast<void> (0) : __assert_fail
("PreviousHigh.slt(Low)", "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9521, __PRETTY_FUNCTION__))
;
9522 uint64_t Gap = (Low - PreviousHigh).getLimitedValue() - 1;
9523 for (uint64_t J = 0; J < Gap; J++)
9524 Table.push_back(DefaultMBB);
9525 }
9526 uint64_t ClusterSize = (High - Low).getLimitedValue() + 1;
9527 for (uint64_t J = 0; J < ClusterSize; ++J)
9528 Table.push_back(Clusters[I].MBB);
9529 JTProbs[Clusters[I].MBB] += Clusters[I].Prob;
9530 }
9531
9532 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9533 unsigned NumDests = JTProbs.size();
9534 if (TLI.isSuitableForBitTests(
9535 NumDests, NumCmps, Clusters[First].Low->getValue(),
9536 Clusters[Last].High->getValue(), DAG.getDataLayout())) {
9537 // Clusters[First..Last] should be lowered as bit tests instead.
9538 return false;
9539 }
9540
9541 // Create the MBB that will load from and jump through the table.
9542 // Note: We create it here, but it's not inserted into the function yet.
9543 MachineFunction *CurMF = FuncInfo.MF;
9544 MachineBasicBlock *JumpTableMBB =
9545 CurMF->CreateMachineBasicBlock(SI->getParent());
9546
9547 // Add successors. Note: use table order for determinism.
9548 SmallPtrSet<MachineBasicBlock *, 8> Done;
9549 for (MachineBasicBlock *Succ : Table) {
9550 if (Done.count(Succ))
9551 continue;
9552 addSuccessorWithProb(JumpTableMBB, Succ, JTProbs[Succ]);
9553 Done.insert(Succ);
9554 }
9555 JumpTableMBB->normalizeSuccProbs();
9556
9557 unsigned JTI = CurMF->getOrCreateJumpTableInfo(TLI.getJumpTableEncoding())
9558 ->createJumpTableIndex(Table);
9559
9560 // Set up the jump table info.
9561 JumpTable JT(-1U, JTI, JumpTableMBB, nullptr);
9562 JumpTableHeader JTH(Clusters[First].Low->getValue(),
9563 Clusters[Last].High->getValue(), SI->getCondition(),
9564 nullptr, false);
9565 JTCases.emplace_back(std::move(JTH), std::move(JT));
9566
9567 JTCluster = CaseCluster::jumpTable(Clusters[First].Low, Clusters[Last].High,
9568 JTCases.size() - 1, Prob);
9569 return true;
9570}
9571
9572void SelectionDAGBuilder::findJumpTables(CaseClusterVector &Clusters,
9573 const SwitchInst *SI,
9574 MachineBasicBlock *DefaultMBB) {
9575#ifndef NDEBUG
9576 // Clusters must be non-empty, sorted, and only contain Range clusters.
9577 assert(!Clusters.empty())((!Clusters.empty()) ? static_cast<void> (0) : __assert_fail
("!Clusters.empty()", "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9577, __PRETTY_FUNCTION__))
;
9578 for (CaseCluster &C : Clusters)
9579 assert(C.Kind == CC_Range)((C.Kind == CC_Range) ? static_cast<void> (0) : __assert_fail
("C.Kind == CC_Range", "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9579, __PRETTY_FUNCTION__))
;
9580 for (unsigned i = 1, e = Clusters.size(); i < e; ++i)
9581 assert(Clusters[i - 1].High->getValue().slt(Clusters[i].Low->getValue()))((Clusters[i - 1].High->getValue().slt(Clusters[i].Low->
getValue())) ? static_cast<void> (0) : __assert_fail ("Clusters[i - 1].High->getValue().slt(Clusters[i].Low->getValue())"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9581, __PRETTY_FUNCTION__))
;
9582#endif
9583
9584 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9585 if (!TLI.areJTsAllowed(SI->getParent()->getParent()))
9586 return;
9587
9588 const int64_t N = Clusters.size();
9589 const unsigned MinJumpTableEntries = TLI.getMinimumJumpTableEntries();
9590 const unsigned SmallNumberOfEntries = MinJumpTableEntries / 2;
9591
9592 if (N < 2 || N < MinJumpTableEntries)
9593 return;
9594
9595 // TotalCases[i]: Total nbr of cases in Clusters[0..i].
9596 SmallVector<unsigned, 8> TotalCases(N);
9597 for (unsigned i = 0; i < N; ++i) {
9598 const APInt &Hi = Clusters[i].High->getValue();
9599 const APInt &Lo = Clusters[i].Low->getValue();
9600 TotalCases[i] = (Hi - Lo).getLimitedValue() + 1;
9601 if (i != 0)
9602 TotalCases[i] += TotalCases[i - 1];
9603 }
9604
9605 // Cheap case: the whole range may be suitable for jump table.
9606 uint64_t Range = getJumpTableRange(Clusters,0, N - 1);
9607 uint64_t NumCases = getJumpTableNumCases(TotalCases, 0, N - 1);
9608 assert(NumCases < UINT64_MAX / 100)((NumCases < (18446744073709551615UL) / 100) ? static_cast
<void> (0) : __assert_fail ("NumCases < UINT64_MAX / 100"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9608, __PRETTY_FUNCTION__))
;
9609 assert(Range >= NumCases)((Range >= NumCases) ? static_cast<void> (0) : __assert_fail
("Range >= NumCases", "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9609, __PRETTY_FUNCTION__))
;
9610 if (TLI.isSuitableForJumpTable(SI, NumCases, Range)) {
9611 CaseCluster JTCluster;
9612 if (buildJumpTable(Clusters, 0, N - 1, SI, DefaultMBB, JTCluster)) {
9613 Clusters[0] = JTCluster;
9614 Clusters.resize(1);
9615 return;
9616 }
9617 }
9618
9619 // The algorithm below is not suitable for -O0.
9620 if (TM.getOptLevel() == CodeGenOpt::None)
9621 return;
9622
9623 // Split Clusters into minimum number of dense partitions. The algorithm uses
9624 // the same idea as Kannan & Proebsting "Correction to 'Producing Good Code
9625 // for the Case Statement'" (1994), but builds the MinPartitions array in
9626 // reverse order to make it easier to reconstruct the partitions in ascending
9627 // order. In the choice between two optimal partitionings, it picks the one
9628 // which yields more jump tables.
9629
9630 // MinPartitions[i] is the minimum nbr of partitions of Clusters[i..N-1].
9631 SmallVector<unsigned, 8> MinPartitions(N);
9632 // LastElement[i] is the last element of the partition starting at i.
9633 SmallVector<unsigned, 8> LastElement(N);
9634 // PartitionsScore[i] is used to break ties when choosing between two
9635 // partitionings resulting in the same number of partitions.
9636 SmallVector<unsigned, 8> PartitionsScore(N);
9637 // For PartitionsScore, a small number of comparisons is considered as good as
9638 // a jump table and a single comparison is considered better than a jump
9639 // table.
9640 enum PartitionScores : unsigned {
9641 NoTable = 0,
9642 Table = 1,
9643 FewCases = 1,
9644 SingleCase = 2
9645 };
9646
9647 // Base case: There is only one way to partition Clusters[N-1].
9648 MinPartitions[N - 1] = 1;
9649 LastElement[N - 1] = N - 1;
9650 PartitionsScore[N - 1] = PartitionScores::SingleCase;
9651
9652 // Note: loop indexes are signed to avoid underflow.
9653 for (int64_t i = N - 2; i >= 0; i--) {
9654 // Find optimal partitioning of Clusters[i..N-1].
9655 // Baseline: Put Clusters[i] into a partition on its own.
9656 MinPartitions[i] = MinPartitions[i + 1] + 1;
9657 LastElement[i] = i;
9658 PartitionsScore[i] = PartitionsScore[i + 1] + PartitionScores::SingleCase;
9659
9660 // Search for a solution that results in fewer partitions.
9661 for (int64_t j = N - 1; j > i; j--) {
9662 // Try building a partition from Clusters[i..j].
9663 uint64_t Range = getJumpTableRange(Clusters, i, j);
9664 uint64_t NumCases = getJumpTableNumCases(TotalCases, i, j);
9665 assert(NumCases < UINT64_MAX / 100)((NumCases < (18446744073709551615UL) / 100) ? static_cast
<void> (0) : __assert_fail ("NumCases < UINT64_MAX / 100"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9665, __PRETTY_FUNCTION__))
;
9666 assert(Range >= NumCases)((Range >= NumCases) ? static_cast<void> (0) : __assert_fail
("Range >= NumCases", "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9666, __PRETTY_FUNCTION__))
;
9667 if (TLI.isSuitableForJumpTable(SI, NumCases, Range)) {
9668 unsigned NumPartitions = 1 + (j == N - 1 ? 0 : MinPartitions[j + 1]);
9669 unsigned Score = j == N - 1 ? 0 : PartitionsScore[j + 1];
9670 int64_t NumEntries = j - i + 1;
9671
9672 if (NumEntries == 1)
9673 Score += PartitionScores::SingleCase;
9674 else if (NumEntries <= SmallNumberOfEntries)
9675 Score += PartitionScores::FewCases;
9676 else if (NumEntries >= MinJumpTableEntries)
9677 Score += PartitionScores::Table;
9678
9679 // If this leads to fewer partitions, or to the same number of
9680 // partitions with better score, it is a better partitioning.
9681 if (NumPartitions < MinPartitions[i] ||
9682 (NumPartitions == MinPartitions[i] && Score > PartitionsScore[i])) {
9683 MinPartitions[i] = NumPartitions;
9684 LastElement[i] = j;
9685 PartitionsScore[i] = Score;
9686 }
9687 }
9688 }
9689 }
9690
9691 // Iterate over the partitions, replacing some with jump tables in-place.
9692 unsigned DstIndex = 0;
9693 for (unsigned First = 0, Last; First < N; First = Last + 1) {
9694 Last = LastElement[First];
9695 assert(Last >= First)((Last >= First) ? static_cast<void> (0) : __assert_fail
("Last >= First", "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9695, __PRETTY_FUNCTION__))
;
9696 assert(DstIndex <= First)((DstIndex <= First) ? static_cast<void> (0) : __assert_fail
("DstIndex <= First", "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9696, __PRETTY_FUNCTION__))
;
9697 unsigned NumClusters = Last - First + 1;
9698
9699 CaseCluster JTCluster;
9700 if (NumClusters >= MinJumpTableEntries &&
9701 buildJumpTable(Clusters, First, Last, SI, DefaultMBB, JTCluster)) {
9702 Clusters[DstIndex++] = JTCluster;
9703 } else {
9704 for (unsigned I = First; I <= Last; ++I)
9705 std::memmove(&Clusters[DstIndex++], &Clusters[I], sizeof(Clusters[I]));
9706 }
9707 }
9708 Clusters.resize(DstIndex);
9709}
9710
9711bool SelectionDAGBuilder::buildBitTests(CaseClusterVector &Clusters,
9712 unsigned First, unsigned Last,
9713 const SwitchInst *SI,
9714 CaseCluster &BTCluster) {
9715 assert(First <= Last)((First <= Last) ? static_cast<void> (0) : __assert_fail
("First <= Last", "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9715, __PRETTY_FUNCTION__))
;
9716 if (First == Last)
9717 return false;
9718
9719 BitVector Dests(FuncInfo.MF->getNumBlockIDs());
9720 unsigned NumCmps = 0;
9721 for (int64_t I = First; I <= Last; ++I) {
9722 assert(Clusters[I].Kind == CC_Range)((Clusters[I].Kind == CC_Range) ? static_cast<void> (0)
: __assert_fail ("Clusters[I].Kind == CC_Range", "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9722, __PRETTY_FUNCTION__))
;
9723 Dests.set(Clusters[I].MBB->getNumber());
9724 NumCmps += (Clusters[I].Low == Clusters[I].High) ? 1 : 2;
9725 }
9726 unsigned NumDests = Dests.count();
9727
9728 APInt Low = Clusters[First].Low->getValue();
9729 APInt High = Clusters[Last].High->getValue();
9730 assert(Low.slt(High))((Low.slt(High)) ? static_cast<void> (0) : __assert_fail
("Low.slt(High)", "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9730, __PRETTY_FUNCTION__))
;
9731
9732 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9733 const DataLayout &DL = DAG.getDataLayout();
9734 if (!TLI.isSuitableForBitTests(NumDests, NumCmps, Low, High, DL))
9735 return false;
9736
9737 APInt LowBound;
9738 APInt CmpRange;
9739
9740 const int BitWidth = TLI.getPointerTy(DL).getSizeInBits();
9741 assert(TLI.rangeFitsInWord(Low, High, DL) &&((TLI.rangeFitsInWord(Low, High, DL) && "Case range must fit in bit mask!"
) ? static_cast<void> (0) : __assert_fail ("TLI.rangeFitsInWord(Low, High, DL) && \"Case range must fit in bit mask!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9742, __PRETTY_FUNCTION__))
9742 "Case range must fit in bit mask!")((TLI.rangeFitsInWord(Low, High, DL) && "Case range must fit in bit mask!"
) ? static_cast<void> (0) : __assert_fail ("TLI.rangeFitsInWord(Low, High, DL) && \"Case range must fit in bit mask!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9742, __PRETTY_FUNCTION__))
;
9743
9744 // Check if the clusters cover a contiguous range such that no value in the
9745 // range will jump to the default statement.
9746 bool ContiguousRange = true;
9747 for (int64_t I = First + 1; I <= Last; ++I) {
9748 if (Clusters[I].Low->getValue() != Clusters[I - 1].High->getValue() + 1) {
9749 ContiguousRange = false;
9750 break;
9751 }
9752 }
9753
9754 if (Low.isStrictlyPositive() && High.slt(BitWidth)) {
9755 // Optimize the case where all the case values fit in a word without having
9756 // to subtract minValue. In this case, we can optimize away the subtraction.
9757 LowBound = APInt::getNullValue(Low.getBitWidth());
9758 CmpRange = High;
9759 ContiguousRange = false;
9760 } else {
9761 LowBound = Low;
9762 CmpRange = High - Low;
9763 }
9764
9765 CaseBitsVector CBV;
9766 auto TotalProb = BranchProbability::getZero();
9767 for (unsigned i = First; i <= Last; ++i) {
9768 // Find the CaseBits for this destination.
9769 unsigned j;
9770 for (j = 0; j < CBV.size(); ++j)
9771 if (CBV[j].BB == Clusters[i].MBB)
9772 break;
9773 if (j == CBV.size())
9774 CBV.push_back(
9775 CaseBits(0, Clusters[i].MBB, 0, BranchProbability::getZero()));
9776 CaseBits *CB = &CBV[j];
9777
9778 // Update Mask, Bits and ExtraProb.
9779 uint64_t Lo = (Clusters[i].Low->getValue() - LowBound).getZExtValue();
9780 uint64_t Hi = (Clusters[i].High->getValue() - LowBound).getZExtValue();
9781 assert(Hi >= Lo && Hi < 64 && "Invalid bit case!")((Hi >= Lo && Hi < 64 && "Invalid bit case!"
) ? static_cast<void> (0) : __assert_fail ("Hi >= Lo && Hi < 64 && \"Invalid bit case!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9781, __PRETTY_FUNCTION__))
;
9782 CB->Mask |= (-1ULL >> (63 - (Hi - Lo))) << Lo;
9783 CB->Bits += Hi - Lo + 1;
9784 CB->ExtraProb += Clusters[i].Prob;
9785 TotalProb += Clusters[i].Prob;
9786 }
9787
9788 BitTestInfo BTI;
9789 llvm::sort(CBV, [](const CaseBits &a, const CaseBits &b) {
9790 // Sort by probability first, number of bits second, bit mask third.
9791 if (a.ExtraProb != b.ExtraProb)
9792 return a.ExtraProb > b.ExtraProb;
9793 if (a.Bits != b.Bits)
9794 return a.Bits > b.Bits;
9795 return a.Mask < b.Mask;
9796 });
9797
9798 for (auto &CB : CBV) {
9799 MachineBasicBlock *BitTestBB =
9800 FuncInfo.MF->CreateMachineBasicBlock(SI->getParent());
9801 BTI.push_back(BitTestCase(CB.Mask, BitTestBB, CB.BB, CB.ExtraProb));
9802 }
9803 BitTestCases.emplace_back(std::move(LowBound), std::move(CmpRange),
9804 SI->getCondition(), -1U, MVT::Other, false,
9805 ContiguousRange, nullptr, nullptr, std::move(BTI),
9806 TotalProb);
9807
9808 BTCluster = CaseCluster::bitTests(Clusters[First].Low, Clusters[Last].High,
9809 BitTestCases.size() - 1, TotalProb);
9810 return true;
9811}
9812
9813void SelectionDAGBuilder::findBitTestClusters(CaseClusterVector &Clusters,
9814 const SwitchInst *SI) {
9815// Partition Clusters into as few subsets as possible, where each subset has a
9816// range that fits in a machine word and has <= 3 unique destinations.
9817
9818#ifndef NDEBUG
9819 // Clusters must be sorted and contain Range or JumpTable clusters.
9820 assert(!Clusters.empty())((!Clusters.empty()) ? static_cast<void> (0) : __assert_fail
("!Clusters.empty()", "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9820, __PRETTY_FUNCTION__))
;
9821 assert(Clusters[0].Kind == CC_Range || Clusters[0].Kind == CC_JumpTable)((Clusters[0].Kind == CC_Range || Clusters[0].Kind == CC_JumpTable
) ? static_cast<void> (0) : __assert_fail ("Clusters[0].Kind == CC_Range || Clusters[0].Kind == CC_JumpTable"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9821, __PRETTY_FUNCTION__))
;
9822 for (const CaseCluster &C : Clusters)
9823 assert(C.Kind == CC_Range || C.Kind == CC_JumpTable)((C.Kind == CC_Range || C.Kind == CC_JumpTable) ? static_cast
<void> (0) : __assert_fail ("C.Kind == CC_Range || C.Kind == CC_JumpTable"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9823, __PRETTY_FUNCTION__))
;
9824 for (unsigned i = 1; i < Clusters.size(); ++i)
9825 assert(Clusters[i-1].High->getValue().slt(Clusters[i].Low->getValue()))((Clusters[i-1].High->getValue().slt(Clusters[i].Low->getValue
())) ? static_cast<void> (0) : __assert_fail ("Clusters[i-1].High->getValue().slt(Clusters[i].Low->getValue())"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9825, __PRETTY_FUNCTION__))
;
9826#endif
9827
9828 // The algorithm below is not suitable for -O0.
9829 if (TM.getOptLevel() == CodeGenOpt::None)
9830 return;
9831
9832 // If target does not have legal shift left, do not emit bit tests at all.
9833 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9834 const DataLayout &DL = DAG.getDataLayout();
9835
9836 EVT PTy = TLI.getPointerTy(DL);
9837 if (!TLI.isOperationLegal(ISD::SHL, PTy))
9838 return;
9839
9840 int BitWidth = PTy.getSizeInBits();
9841 const int64_t N = Clusters.size();
9842
9843 // MinPartitions[i] is the minimum nbr of partitions of Clusters[i..N-1].
9844 SmallVector<unsigned, 8> MinPartitions(N);
9845 // LastElement[i] is the last element of the partition starting at i.
9846 SmallVector<unsigned, 8> LastElement(N);
9847
9848 // FIXME: This might not be the best algorithm for finding bit test clusters.
9849
9850 // Base case: There is only one way to partition Clusters[N-1].
9851 MinPartitions[N - 1] = 1;
9852 LastElement[N - 1] = N - 1;
9853
9854 // Note: loop indexes are signed to avoid underflow.
9855 for (int64_t i = N - 2; i >= 0; --i) {
9856 // Find optimal partitioning of Clusters[i..N-1].
9857 // Baseline: Put Clusters[i] into a partition on its own.
9858 MinPartitions[i] = MinPartitions[i + 1] + 1;
9859 LastElement[i] = i;
9860
9861 // Search for a solution that results in fewer partitions.
9862 // Note: the search is limited by BitWidth, reducing time complexity.
9863 for (int64_t j = std::min(N - 1, i + BitWidth - 1); j > i; --j) {
9864 // Try building a partition from Clusters[i..j].
9865
9866 // Check the range.
9867 if (!TLI.rangeFitsInWord(Clusters[i].Low->getValue(),
9868 Clusters[j].High->getValue(), DL))
9869 continue;
9870
9871 // Check nbr of destinations and cluster types.
9872 // FIXME: This works, but doesn't seem very efficient.
9873 bool RangesOnly = true;
9874 BitVector Dests(FuncInfo.MF->getNumBlockIDs());
9875 for (int64_t k = i; k <= j; k++) {
9876 if (Clusters[k].Kind != CC_Range) {
9877 RangesOnly = false;
9878 break;
9879 }
9880 Dests.set(Clusters[k].MBB->getNumber());
9881 }
9882 if (!RangesOnly || Dests.count() > 3)
9883 break;
9884
9885 // Check if it's a better partition.
9886 unsigned NumPartitions = 1 + (j == N - 1 ? 0 : MinPartitions[j + 1]);
9887 if (NumPartitions < MinPartitions[i]) {
9888 // Found a better partition.
9889 MinPartitions[i] = NumPartitions;
9890 LastElement[i] = j;
9891 }
9892 }
9893 }
9894
9895 // Iterate over the partitions, replacing with bit-test clusters in-place.
9896 unsigned DstIndex = 0;
9897 for (unsigned First = 0, Last; First < N; First = Last + 1) {
9898 Last = LastElement[First];
9899 assert(First <= Last)((First <= Last) ? static_cast<void> (0) : __assert_fail
("First <= Last", "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9899, __PRETTY_FUNCTION__))
;
9900 assert(DstIndex <= First)((DstIndex <= First) ? static_cast<void> (0) : __assert_fail
("DstIndex <= First", "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9900, __PRETTY_FUNCTION__))
;
9901
9902 CaseCluster BitTestCluster;
9903 if (buildBitTests(Clusters, First, Last, SI, BitTestCluster)) {
9904 Clusters[DstIndex++] = BitTestCluster;
9905 } else {
9906 size_t NumClusters = Last - First + 1;
9907 std::memmove(&Clusters[DstIndex], &Clusters[First],
9908 sizeof(Clusters[0]) * NumClusters);
9909 DstIndex += NumClusters;
9910 }
9911 }
9912 Clusters.resize(DstIndex);
9913}
9914
9915void SelectionDAGBuilder::lowerWorkItem(SwitchWorkListItem W, Value *Cond,
9916 MachineBasicBlock *SwitchMBB,
9917 MachineBasicBlock *DefaultMBB) {
9918 MachineFunction *CurMF = FuncInfo.MF;
9919 MachineBasicBlock *NextMBB = nullptr;
9920 MachineFunction::iterator BBI(W.MBB);
9921 if (++BBI != FuncInfo.MF->end())
9922 NextMBB = &*BBI;
9923
9924 unsigned Size = W.LastCluster - W.FirstCluster + 1;
9925
9926 BranchProbabilityInfo *BPI = FuncInfo.BPI;
9927
9928 if (Size == 2 && W.MBB == SwitchMBB) {
9929 // If any two of the cases has the same destination, and if one value
9930 // is the same as the other, but has one bit unset that the other has set,
9931 // use bit manipulation to do two compares at once. For example:
9932 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
9933 // TODO: This could be extended to merge any 2 cases in switches with 3
9934 // cases.
9935 // TODO: Handle cases where W.CaseBB != SwitchBB.
9936 CaseCluster &Small = *W.FirstCluster;
9937 CaseCluster &Big = *W.LastCluster;
9938
9939 if (Small.Low == Small.High && Big.Low == Big.High &&
9940 Small.MBB == Big.MBB) {
9941 const APInt &SmallValue = Small.Low->getValue();
9942 const APInt &BigValue = Big.Low->getValue();
9943
9944 // Check that there is only one bit different.
9945 APInt CommonBit = BigValue ^ SmallValue;
9946 if (CommonBit.isPowerOf2()) {
9947 SDValue CondLHS = getValue(Cond);
9948 EVT VT = CondLHS.getValueType();
9949 SDLoc DL = getCurSDLoc();
9950
9951 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS,
9952 DAG.getConstant(CommonBit, DL, VT));
9953 SDValue Cond = DAG.getSetCC(
9954 DL, MVT::i1, Or, DAG.getConstant(BigValue | SmallValue, DL, VT),
9955 ISD::SETEQ);
9956
9957 // Update successor info.
9958 // Both Small and Big will jump to Small.BB, so we sum up the
9959 // probabilities.
9960 addSuccessorWithProb(SwitchMBB, Small.MBB, Small.Prob + Big.Prob);
9961 if (BPI)
9962 addSuccessorWithProb(
9963 SwitchMBB, DefaultMBB,
9964 // The default destination is the first successor in IR.
9965 BPI->getEdgeProbability(SwitchMBB->getBasicBlock(), (unsigned)0));
9966 else
9967 addSuccessorWithProb(SwitchMBB, DefaultMBB);
9968
9969 // Insert the true branch.
9970 SDValue BrCond =
9971 DAG.getNode(ISD::BRCOND, DL, MVT::Other, getControlRoot(), Cond,
9972 DAG.getBasicBlock(Small.MBB));
9973 // Insert the false branch.
9974 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond,
9975 DAG.getBasicBlock(DefaultMBB));
9976
9977 DAG.setRoot(BrCond);
9978 return;
9979 }
9980 }
9981 }
9982
9983 if (TM.getOptLevel() != CodeGenOpt::None) {
9984 // Here, we order cases by probability so the most likely case will be
9985 // checked first. However, two clusters can have the same probability in
9986 // which case their relative ordering is non-deterministic. So we use Low
9987 // as a tie-breaker as clusters are guaranteed to never overlap.
9988 llvm::sort(W.FirstCluster, W.LastCluster + 1,
9989 [](const CaseCluster &a, const CaseCluster &b) {
9990 return a.Prob != b.Prob ?
9991 a.Prob > b.Prob :
9992 a.Low->getValue().slt(b.Low->getValue());
9993 });
9994
9995 // Rearrange the case blocks so that the last one falls through if possible
9996 // without changing the order of probabilities.
9997 for (CaseClusterIt I = W.LastCluster; I > W.FirstCluster; ) {
9998 --I;
9999 if (I->Prob > W.LastCluster->Prob)
10000 break;
10001 if (I->Kind == CC_Range && I->MBB == NextMBB) {
10002 std::swap(*I, *W.LastCluster);
10003 break;
10004 }
10005 }
10006 }
10007
10008 // Compute total probability.
10009 BranchProbability DefaultProb = W.DefaultProb;
10010 BranchProbability UnhandledProbs = DefaultProb;
10011 for (CaseClusterIt I = W.FirstCluster; I <= W.LastCluster; ++I)
10012 UnhandledProbs += I->Prob;
10013
10014 MachineBasicBlock *CurMBB = W.MBB;
10015 for (CaseClusterIt I = W.FirstCluster, E = W.LastCluster; I <= E; ++I) {
10016 MachineBasicBlock *Fallthrough;
10017 if (I == W.LastCluster) {
10018 // For the last cluster, fall through to the default destination.
10019 Fallthrough = DefaultMBB;
10020 } else {
10021 Fallthrough = CurMF->CreateMachineBasicBlock(CurMBB->getBasicBlock());
10022 CurMF->insert(BBI, Fallthrough);
10023 // Put Cond in a virtual register to make it available from the new blocks.
10024 ExportFromCurrentBlock(Cond);
10025 }
10026 UnhandledProbs -= I->Prob;
10027
10028 switch (I->Kind) {
10029 case CC_JumpTable: {
10030 // FIXME: Optimize away range check based on pivot comparisons.
10031 JumpTableHeader *JTH = &JTCases[I->JTCasesIndex].first;
10032 JumpTable *JT = &JTCases[I->JTCasesIndex].second;
10033
10034 // The jump block hasn't been inserted yet; insert it here.
10035 MachineBasicBlock *JumpMBB = JT->MBB;
10036 CurMF->insert(BBI, JumpMBB);
10037
10038 auto JumpProb = I->Prob;
10039 auto FallthroughProb = UnhandledProbs;
10040
10041 // If the default statement is a target of the jump table, we evenly
10042 // distribute the default probability to successors of CurMBB. Also
10043 // update the probability on the edge from JumpMBB to Fallthrough.
10044 for (MachineBasicBlock::succ_iterator SI = JumpMBB->succ_begin(),
10045 SE = JumpMBB->succ_end();
10046 SI != SE; ++SI) {
10047 if (*SI == DefaultMBB) {
10048 JumpProb += DefaultProb / 2;
10049 FallthroughProb -= DefaultProb / 2;
10050 JumpMBB->setSuccProbability(SI, DefaultProb / 2);
10051 JumpMBB->normalizeSuccProbs();
10052 break;
10053 }
10054 }
10055
10056 addSuccessorWithProb(CurMBB, Fallthrough, FallthroughProb);
10057 addSuccessorWithProb(CurMBB, JumpMBB, JumpProb);
10058 CurMBB->normalizeSuccProbs();
10059
10060 // The jump table header will be inserted in our current block, do the
10061 // range check, and fall through to our fallthrough block.
10062 JTH->HeaderBB = CurMBB;
10063 JT->Default = Fallthrough; // FIXME: Move Default to JumpTableHeader.
10064
10065 // If we're in the right place, emit the jump table header right now.
10066 if (CurMBB == SwitchMBB) {
10067 visitJumpTableHeader(*JT, *JTH, SwitchMBB);
10068 JTH->Emitted = true;
10069 }
10070 break;
10071 }
10072 case CC_BitTests: {
10073 // FIXME: Optimize away range check based on pivot comparisons.
10074 BitTestBlock *BTB = &BitTestCases[I->BTCasesIndex];
10075
10076 // The bit test blocks haven't been inserted yet; insert them here.
10077 for (BitTestCase &BTC : BTB->Cases)
10078 CurMF->insert(BBI, BTC.ThisBB);
10079
10080 // Fill in fields of the BitTestBlock.
10081 BTB->Parent = CurMBB;
10082 BTB->Default = Fallthrough;
10083
10084 BTB->DefaultProb = UnhandledProbs;
10085 // If the cases in bit test don't form a contiguous range, we evenly
10086 // distribute the probability on the edge to Fallthrough to two
10087 // successors of CurMBB.
10088 if (!BTB->ContiguousRange) {
10089 BTB->Prob += DefaultProb / 2;
10090 BTB->DefaultProb -= DefaultProb / 2;
10091 }
10092
10093 // If we're in the right place, emit the bit test header right now.
10094 if (CurMBB == SwitchMBB) {
10095 visitBitTestHeader(*BTB, SwitchMBB);
10096 BTB->Emitted = true;
10097 }
10098 break;
10099 }
10100 case CC_Range: {
10101 const Value *RHS, *LHS, *MHS;
10102 ISD::CondCode CC;
10103 if (I->Low == I->High) {
10104 // Check Cond == I->Low.
10105 CC = ISD::SETEQ;
10106 LHS = Cond;
10107 RHS=I->Low;
10108 MHS = nullptr;
10109 } else {
10110 // Check I->Low <= Cond <= I->High.
10111 CC = ISD::SETLE;
10112 LHS = I->Low;
10113 MHS = Cond;
10114 RHS = I->High;
10115 }
10116
10117 // The false probability is the sum of all unhandled cases.
10118 CaseBlock CB(CC, LHS, RHS, MHS, I->MBB, Fallthrough, CurMBB,
10119 getCurSDLoc(), I->Prob, UnhandledProbs);
10120
10121 if (CurMBB == SwitchMBB)
10122 visitSwitchCase(CB, SwitchMBB);
10123 else
10124 SwitchCases.push_back(CB);
10125
10126 break;
10127 }
10128 }
10129 CurMBB = Fallthrough;
10130 }
10131}
10132
10133unsigned SelectionDAGBuilder::caseClusterRank(const CaseCluster &CC,
10134 CaseClusterIt First,
10135 CaseClusterIt Last) {
10136 return std::count_if(First, Last + 1, [&](const CaseCluster &X) {
10137 if (X.Prob != CC.Prob)
10138 return X.Prob > CC.Prob;
10139
10140 // Ties are broken by comparing the case value.
10141 return X.Low->getValue().slt(CC.Low->getValue());
10142 });
10143}
10144
10145void SelectionDAGBuilder::splitWorkItem(SwitchWorkList &WorkList,
10146 const SwitchWorkListItem &W,
10147 Value *Cond,
10148 MachineBasicBlock *SwitchMBB) {
10149 assert(W.FirstCluster->Low->getValue().slt(W.LastCluster->Low->getValue()) &&((W.FirstCluster->Low->getValue().slt(W.LastCluster->
Low->getValue()) && "Clusters not sorted?") ? static_cast
<void> (0) : __assert_fail ("W.FirstCluster->Low->getValue().slt(W.LastCluster->Low->getValue()) && \"Clusters not sorted?\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 10150, __PRETTY_FUNCTION__))
10150 "Clusters not sorted?")((W.FirstCluster->Low->getValue().slt(W.LastCluster->
Low->getValue()) && "Clusters not sorted?") ? static_cast
<void> (0) : __assert_fail ("W.FirstCluster->Low->getValue().slt(W.LastCluster->Low->getValue()) && \"Clusters not sorted?\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 10150, __PRETTY_FUNCTION__))
;
10151
10152 assert(W.LastCluster - W.FirstCluster + 1 >= 2 && "Too small to split!")((W.LastCluster - W.FirstCluster + 1 >= 2 && "Too small to split!"
) ? static_cast<void> (0) : __assert_fail ("W.LastCluster - W.FirstCluster + 1 >= 2 && \"Too small to split!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 10152, __PRETTY_FUNCTION__))
;
10153
10154 // Balance the tree based on branch probabilities to create a near-optimal (in
10155 // terms of search time given key frequency) binary search tree. See e.g. Kurt
10156 // Mehlhorn "Nearly Optimal Binary Search Trees" (1975).
10157 CaseClusterIt LastLeft = W.FirstCluster;
10158 CaseClusterIt FirstRight = W.LastCluster;
10159 auto LeftProb = LastLeft->Prob + W.DefaultProb / 2;
10160 auto RightProb = FirstRight->Prob + W.DefaultProb / 2;
10161
10162 // Move LastLeft and FirstRight towards each other from opposite directions to
10163 // find a partitioning of the clusters which balances the probability on both
10164 // sides. If LeftProb and RightProb are equal, alternate which side is
10165 // taken to ensure 0-probability nodes are distributed evenly.
10166 unsigned I = 0;
10167 while (LastLeft + 1 < FirstRight) {
10168 if (LeftProb < RightProb || (LeftProb == RightProb && (I & 1)))
10169 LeftProb += (++LastLeft)->Prob;
10170 else
10171 RightProb += (--FirstRight)->Prob;
10172 I++;
10173 }
10174
10175 while (true) {
10176 // Our binary search tree differs from a typical BST in that ours can have up
10177 // to three values in each leaf. The pivot selection above doesn't take that
10178 // into account, which means the tree might require more nodes and be less
10179 // efficient. We compensate for this here.
10180
10181 unsigned NumLeft = LastLeft - W.FirstCluster + 1;
10182 unsigned NumRight = W.LastCluster - FirstRight + 1;
10183
10184 if (std::min(NumLeft, NumRight) < 3 && std::max(NumLeft, NumRight) > 3) {
10185 // If one side has less than 3 clusters, and the other has more than 3,
10186 // consider taking a cluster from the other side.
10187
10188 if (NumLeft < NumRight) {
10189 // Consider moving the first cluster on the right to the left side.
10190 CaseCluster &CC = *FirstRight;
10191 unsigned RightSideRank = caseClusterRank(CC, FirstRight, W.LastCluster);
10192 unsigned LeftSideRank = caseClusterRank(CC, W.FirstCluster, LastLeft);
10193 if (LeftSideRank <= RightSideRank) {
10194 // Moving the cluster to the left does not demote it.
10195 ++LastLeft;
10196 ++FirstRight;
10197 continue;
10198 }
10199 } else {
10200 assert(NumRight < NumLeft)((NumRight < NumLeft) ? static_cast<void> (0) : __assert_fail
("NumRight < NumLeft", "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 10200, __PRETTY_FUNCTION__))
;
10201 // Consider moving the last element on the left to the right side.
10202 CaseCluster &CC = *LastLeft;
10203 unsigned LeftSideRank = caseClusterRank(CC, W.FirstCluster, LastLeft);
10204 unsigned RightSideRank = caseClusterRank(CC, FirstRight, W.LastCluster);
10205 if (RightSideRank <= LeftSideRank) {
10206 // Moving the cluster to the right does not demot it.
10207 --LastLeft;
10208 --FirstRight;
10209 continue;
10210 }
10211 }
10212 }
10213 break;
10214 }
10215
10216 assert(LastLeft + 1 == FirstRight)((LastLeft + 1 == FirstRight) ? static_cast<void> (0) :
__assert_fail ("LastLeft + 1 == FirstRight", "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 10216, __PRETTY_FUNCTION__))
;
10217 assert(LastLeft >= W.FirstCluster)((LastLeft >= W.FirstCluster) ? static_cast<void> (0
) : __assert_fail ("LastLeft >= W.FirstCluster", "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 10217, __PRETTY_FUNCTION__))
;
10218 assert(FirstRight <= W.LastCluster)((FirstRight <= W.LastCluster) ? static_cast<void> (
0) : __assert_fail ("FirstRight <= W.LastCluster", "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 10218, __PRETTY_FUNCTION__))
;
10219
10220 // Use the first element on the right as pivot since we will make less-than
10221 // comparisons against it.
10222 CaseClusterIt PivotCluster = FirstRight;
10223 assert(PivotCluster > W.FirstCluster)((PivotCluster > W.FirstCluster) ? static_cast<void>
(0) : __assert_fail ("PivotCluster > W.FirstCluster", "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 10223, __PRETTY_FUNCTION__))
;
10224 assert(PivotCluster <= W.LastCluster)((PivotCluster <= W.LastCluster) ? static_cast<void>
(0) : __assert_fail ("PivotCluster <= W.LastCluster", "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 10224, __PRETTY_FUNCTION__))
;
10225
10226 CaseClusterIt FirstLeft = W.FirstCluster;
10227 CaseClusterIt LastRight = W.LastCluster;
10228
10229 const ConstantInt *Pivot = PivotCluster->Low;
10230
10231 // New blocks will be inserted immediately after the current one.
10232 MachineFunction::iterator BBI(W.MBB);
10233 ++BBI;
10234
10235 // We will branch to the LHS if Value < Pivot. If LHS is a single cluster,
10236 // we can branch to its destination directly if it's squeezed exactly in
10237 // between the known lower bound and Pivot - 1.
10238 MachineBasicBlock *LeftMBB;
10239 if (FirstLeft == LastLeft && FirstLeft->Kind == CC_Range &&
10240 FirstLeft->Low == W.GE &&
10241 (FirstLeft->High->getValue() + 1LL) == Pivot->getValue()) {
10242 LeftMBB = FirstLeft->MBB;
10243 } else {
10244 LeftMBB = FuncInfo.MF->CreateMachineBasicBlock(W.MBB->getBasicBlock());
10245 FuncInfo.MF->insert(BBI, LeftMBB);
10246 WorkList.push_back(
10247 {LeftMBB, FirstLeft, LastLeft, W.GE, Pivot, W.DefaultProb / 2});
10248 // Put Cond in a virtual register to make it available from the new blocks.
10249 ExportFromCurrentBlock(Cond);
10250 }
10251
10252 // Similarly, we will branch to the RHS if Value >= Pivot. If RHS is a
10253 // single cluster, RHS.Low == Pivot, and we can branch to its destination
10254 // directly if RHS.High equals the current upper bound.
10255 MachineBasicBlock *RightMBB;
10256 if (FirstRight == LastRight && FirstRight->Kind == CC_Range &&
10257 W.LT && (FirstRight->High->getValue() + 1ULL) == W.LT->getValue()) {
10258 RightMBB = FirstRight->MBB;
10259 } else {
10260 RightMBB = FuncInfo.MF->CreateMachineBasicBlock(W.MBB->getBasicBlock());
10261 FuncInfo.MF->insert(BBI, RightMBB);
10262 WorkList.push_back(
10263 {RightMBB, FirstRight, LastRight, Pivot, W.LT, W.DefaultProb / 2});
10264 // Put Cond in a virtual register to make it available from the new blocks.
10265 ExportFromCurrentBlock(Cond);
10266 }
10267
10268 // Create the CaseBlock record that will be used to lower the branch.
10269 CaseBlock CB(ISD::SETLT, Cond, Pivot, nullptr, LeftMBB, RightMBB, W.MBB,
10270 getCurSDLoc(), LeftProb, RightProb);
10271
10272 if (W.MBB == SwitchMBB)
10273 visitSwitchCase(CB, SwitchMBB);
10274 else
10275 SwitchCases.push_back(CB);
10276}
10277
10278// Scale CaseProb after peeling a case with the probablity of PeeledCaseProb
10279// from the swith statement.
10280static BranchProbability scaleCaseProbality(BranchProbability CaseProb,
10281 BranchProbability PeeledCaseProb) {
10282 if (PeeledCaseProb == BranchProbability::getOne())
10283 return BranchProbability::getZero();
10284 BranchProbability SwitchProb = PeeledCaseProb.getCompl();
10285
10286 uint32_t Numerator = CaseProb.getNumerator();
10287 uint32_t Denominator = SwitchProb.scale(CaseProb.getDenominator());
10288 return BranchProbability(Numerator, std::max(Numerator, Denominator));
10289}
10290
10291// Try to peel the top probability case if it exceeds the threshold.
10292// Return current MachineBasicBlock for the switch statement if the peeling
10293// does not occur.
10294// If the peeling is performed, return the newly created MachineBasicBlock
10295// for the peeled switch statement. Also update Clusters to remove the peeled
10296// case. PeeledCaseProb is the BranchProbability for the peeled case.
10297MachineBasicBlock *SelectionDAGBuilder::peelDominantCaseCluster(
10298 const SwitchInst &SI, CaseClusterVector &Clusters,
10299 BranchProbability &PeeledCaseProb) {
10300 MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
10301 // Don't perform if there is only one cluster or optimizing for size.
10302 if (SwitchPeelThreshold > 100 || !FuncInfo.BPI || Clusters.size() < 2 ||
10303 TM.getOptLevel() == CodeGenOpt::None ||
10304 SwitchMBB->getParent()->getFunction().optForMinSize())
10305 return SwitchMBB;
10306
10307 BranchProbability TopCaseProb = BranchProbability(SwitchPeelThreshold, 100);
10308 unsigned PeeledCaseIndex = 0;
10309 bool SwitchPeeled = false;
10310 for (unsigned Index = 0; Index < Clusters.size(); ++Index) {
10311 CaseCluster &CC = Clusters[Index];
10312 if (CC.Prob < TopCaseProb)
10313 continue;
10314 TopCaseProb = CC.Prob;
10315 PeeledCaseIndex = Index;
10316 SwitchPeeled = true;
10317 }
10318 if (!SwitchPeeled)
10319 return SwitchMBB;
10320
10321 LLVM_DEBUG(dbgs() << "Peeled one top case in switch stmt, prob: "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << "Peeled one top case in switch stmt, prob: "
<< TopCaseProb << "\n"; } } while (false)
10322 << TopCaseProb << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << "Peeled one top case in switch stmt, prob: "
<< TopCaseProb << "\n"; } } while (false)
;
10323
10324 // Record the MBB for the peeled switch statement.
10325 MachineFunction::iterator BBI(SwitchMBB);
10326 ++BBI;
10327 MachineBasicBlock *PeeledSwitchMBB =
10328 FuncInfo.MF->CreateMachineBasicBlock(SwitchMBB->getBasicBlock());
10329 FuncInfo.MF->insert(BBI, PeeledSwitchMBB);
10330
10331 ExportFromCurrentBlock(SI.getCondition());
10332 auto PeeledCaseIt = Clusters.begin() + PeeledCaseIndex;
10333 SwitchWorkListItem W = {SwitchMBB, PeeledCaseIt, PeeledCaseIt,
10334 nullptr, nullptr, TopCaseProb.getCompl()};
10335 lowerWorkItem(W, SI.getCondition(), SwitchMBB, PeeledSwitchMBB);
10336
10337 Clusters.erase(PeeledCaseIt);
10338 for (CaseCluster &CC : Clusters) {
10339 LLVM_DEBUG(do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << "Scale the probablity for one cluster, before scaling: "
<< CC.Prob << "\n"; } } while (false)
10340 dbgs() << "Scale the probablity for one cluster, before scaling: "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << "Scale the probablity for one cluster, before scaling: "
<< CC.Prob << "\n"; } } while (false)
10341 << CC.Prob << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << "Scale the probablity for one cluster, before scaling: "
<< CC.Prob << "\n"; } } while (false)
;
10342 CC.Prob = scaleCaseProbality(CC.Prob, TopCaseProb);
10343 LLVM_DEBUG(dbgs() << "After scaling: " << CC.Prob << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << "After scaling: " << CC.Prob
<< "\n"; } } while (false)
;
10344 }
10345 PeeledCaseProb = TopCaseProb;
10346 return PeeledSwitchMBB;
10347}
10348
10349void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
10350 // Extract cases from the switch.
10351 BranchProbabilityInfo *BPI = FuncInfo.BPI;
10352 CaseClusterVector Clusters;
10353 Clusters.reserve(SI.getNumCases());
10354 for (auto I : SI.cases()) {
10355 MachineBasicBlock *Succ = FuncInfo.MBBMap[I.getCaseSuccessor()];
10356 const ConstantInt *CaseVal = I.getCaseValue();
10357 BranchProbability Prob =
10358 BPI ? BPI->getEdgeProbability(SI.getParent(), I.getSuccessorIndex())
10359 : BranchProbability(1, SI.getNumCases() + 1);
10360 Clusters.push_back(CaseCluster::range(CaseVal, CaseVal, Succ, Prob));
10361 }
10362
10363 MachineBasicBlock *DefaultMBB = FuncInfo.MBBMap[SI.getDefaultDest()];
10364
10365 // Cluster adjacent cases with the same destination. We do this at all
10366 // optimization levels because it's cheap to do and will make codegen faster
10367 // if there are many clusters.
10368 sortAndRangeify(Clusters);
10369
10370 if (TM.getOptLevel() != CodeGenOpt::None) {
10371 // Replace an unreachable default with the most popular destination.
10372 // FIXME: Exploit unreachable default more aggressively.
10373 bool UnreachableDefault =
10374 isa<UnreachableInst>(SI.getDefaultDest()->getFirstNonPHIOrDbg());
10375 if (UnreachableDefault && !Clusters.empty()) {
10376 DenseMap<const BasicBlock *, unsigned> Popularity;
10377 unsigned MaxPop = 0;
10378 const BasicBlock *MaxBB = nullptr;
10379 for (auto I : SI.cases()) {
10380 const BasicBlock *BB = I.getCaseSuccessor();
10381 if (++Popularity[BB] > MaxPop) {
10382 MaxPop = Popularity[BB];
10383 MaxBB = BB;
10384 }
10385 }
10386 // Set new default.
10387 assert(MaxPop > 0 && MaxBB)((MaxPop > 0 && MaxBB) ? static_cast<void> (
0) : __assert_fail ("MaxPop > 0 && MaxBB", "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 10387, __PRETTY_FUNCTION__))
;
10388 DefaultMBB = FuncInfo.MBBMap[MaxBB];
10389
10390 // Remove cases that were pointing to the destination that is now the
10391 // default.
10392 CaseClusterVector New;
10393 New.reserve(Clusters.size());
10394 for (CaseCluster &CC : Clusters) {
10395 if (CC.MBB != DefaultMBB)
10396 New.push_back(CC);
10397 }
10398 Clusters = std::move(New);
10399 }
10400 }
10401
10402 // The branch probablity of the peeled case.
10403 BranchProbability PeeledCaseProb = BranchProbability::getZero();
10404 MachineBasicBlock *PeeledSwitchMBB =
10405 peelDominantCaseCluster(SI, Clusters, PeeledCaseProb);
10406
10407 // If there is only the default destination, jump there directly.
10408 MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
10409 if (Clusters.empty()) {
10410 assert(PeeledSwitchMBB == SwitchMBB)((PeeledSwitchMBB == SwitchMBB) ? static_cast<void> (0)
: __assert_fail ("PeeledSwitchMBB == SwitchMBB", "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 10410, __PRETTY_FUNCTION__))
;
10411 SwitchMBB->addSuccessor(DefaultMBB);
10412 if (DefaultMBB != NextBlock(SwitchMBB)) {
10413 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other,
10414 getControlRoot(), DAG.getBasicBlock(DefaultMBB)));
10415 }
10416 return;
10417 }
10418
10419 findJumpTables(Clusters, &SI, DefaultMBB);
10420 findBitTestClusters(Clusters, &SI);
10421
10422 LLVM_DEBUG({do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { { dbgs() << "Case clusters: "; for (const CaseCluster
&C : Clusters) { if (C.Kind == CC_JumpTable) dbgs() <<
"JT:"; if (C.Kind == CC_BitTests) dbgs() << "BT:"; C.Low
->getValue().print(dbgs(), true); if (C.Low != C.High) { dbgs
() << '-'; C.High->getValue().print(dbgs(), true); }
dbgs() << ' '; } dbgs() << '\n'; }; } } while (false
)
10423 dbgs() << "Case clusters: ";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { { dbgs() << "Case clusters: "; for (const CaseCluster
&C : Clusters) { if (C.Kind == CC_JumpTable) dbgs() <<
"JT:"; if (C.Kind == CC_BitTests) dbgs() << "BT:"; C.Low
->getValue().print(dbgs(), true); if (C.Low != C.High) { dbgs
() << '-'; C.High->getValue().print(dbgs(), true); }
dbgs() << ' '; } dbgs() << '\n'; }; } } while (false
)
10424 for (const CaseCluster &C : Clusters) {do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { { dbgs() << "Case clusters: "; for (const CaseCluster
&C : Clusters) { if (C.Kind == CC_JumpTable) dbgs() <<
"JT:"; if (C.Kind == CC_BitTests) dbgs() << "BT:"; C.Low
->getValue().print(dbgs(), true); if (C.Low != C.High) { dbgs
() << '-'; C.High->getValue().print(dbgs(), true); }
dbgs() << ' '; } dbgs() << '\n'; }; } } while (false
)
10425 if (C.Kind == CC_JumpTable)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { { dbgs() << "Case clusters: "; for (const CaseCluster
&C : Clusters) { if (C.Kind == CC_JumpTable) dbgs() <<
"JT:"; if (C.Kind == CC_BitTests) dbgs() << "BT:"; C.Low
->getValue().print(dbgs(), true); if (C.Low != C.High) { dbgs
() << '-'; C.High->getValue().print(dbgs(), true); }
dbgs() << ' '; } dbgs() << '\n'; }; } } while (false
)
10426 dbgs() << "JT:";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { { dbgs() << "Case clusters: "; for (const CaseCluster
&C : Clusters) { if (C.Kind == CC_JumpTable) dbgs() <<
"JT:"; if (C.Kind == CC_BitTests) dbgs() << "BT:"; C.Low
->getValue().print(dbgs(), true); if (C.Low != C.High) { dbgs
() << '-'; C.High->getValue().print(dbgs(), true); }
dbgs() << ' '; } dbgs() << '\n'; }; } } while (false
)
10427 if (C.Kind == CC_BitTests)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { { dbgs() << "Case clusters: "; for (const CaseCluster
&C : Clusters) { if (C.Kind == CC_JumpTable) dbgs() <<
"JT:"; if (C.Kind == CC_BitTests) dbgs() << "BT:"; C.Low
->getValue().print(dbgs(), true); if (C.Low != C.High) { dbgs
() << '-'; C.High->getValue().print(dbgs(), true); }
dbgs() << ' '; } dbgs() << '\n'; }; } } while (false
)
10428 dbgs() << "BT:";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { { dbgs() << "Case clusters: "; for (const CaseCluster
&C : Clusters) { if (C.Kind == CC_JumpTable) dbgs() <<
"JT:"; if (C.Kind == CC_BitTests) dbgs() << "BT:"; C.Low
->getValue().print(dbgs(), true); if (C.Low != C.High) { dbgs
() << '-'; C.High->getValue().print(dbgs(), true); }
dbgs() << ' '; } dbgs() << '\n'; }; } } while (false
)
10429
10430 C.Low->getValue().print(dbgs(), true);do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { { dbgs() << "Case clusters: "; for (const CaseCluster
&C : Clusters) { if (C.Kind == CC_JumpTable) dbgs() <<
"JT:"; if (C.Kind == CC_BitTests) dbgs() << "BT:"; C.Low
->getValue().print(dbgs(), true); if (C.Low != C.High) { dbgs
() << '-'; C.High->getValue().print(dbgs(), true); }
dbgs() << ' '; } dbgs() << '\n'; }; } } while (false
)
10431 if (C.Low != C.High) {do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { { dbgs() << "Case clusters: "; for (const CaseCluster
&C : Clusters) { if (C.Kind == CC_JumpTable) dbgs() <<
"JT:"; if (C.Kind == CC_BitTests) dbgs() << "BT:"; C.Low
->getValue().print(dbgs(), true); if (C.Low != C.High) { dbgs
() << '-'; C.High->getValue().print(dbgs(), true); }
dbgs() << ' '; } dbgs() << '\n'; }; } } while (false
)
10432 dbgs() << '-';do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { { dbgs() << "Case clusters: "; for (const CaseCluster
&C : Clusters) { if (C.Kind == CC_JumpTable) dbgs() <<
"JT:"; if (C.Kind == CC_BitTests) dbgs() << "BT:"; C.Low
->getValue().print(dbgs(), true); if (C.Low != C.High) { dbgs
() << '-'; C.High->getValue().print(dbgs(), true); }
dbgs() << ' '; } dbgs() << '\n'; }; } } while (false
)
10433 C.High->getValue().print(dbgs(), true);do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { { dbgs() << "Case clusters: "; for (const CaseCluster
&C : Clusters) { if (C.Kind == CC_JumpTable) dbgs() <<
"JT:"; if (C.Kind == CC_BitTests) dbgs() << "BT:"; C.Low
->getValue().print(dbgs(), true); if (C.Low != C.High) { dbgs
() << '-'; C.High->getValue().print(dbgs(), true); }
dbgs() << ' '; } dbgs() << '\n'; }; } } while (false
)
10434 }do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { { dbgs() << "Case clusters: "; for (const CaseCluster
&C : Clusters) { if (C.Kind == CC_JumpTable) dbgs() <<
"JT:"; if (C.Kind == CC_BitTests) dbgs() << "BT:"; C.Low
->getValue().print(dbgs(), true); if (C.Low != C.High) { dbgs
() << '-'; C.High->getValue().print(dbgs(), true); }
dbgs() << ' '; } dbgs() << '\n'; }; } } while (false
)
10435 dbgs() << ' ';do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { { dbgs() << "Case clusters: "; for (const CaseCluster
&C : Clusters) { if (C.Kind == CC_JumpTable) dbgs() <<
"JT:"; if (C.Kind == CC_BitTests) dbgs() << "BT:"; C.Low
->getValue().print(dbgs(), true); if (C.Low != C.High) { dbgs
() << '-'; C.High->getValue().print(dbgs(), true); }
dbgs() << ' '; } dbgs() << '\n'; }; } } while (false
)
10436 }do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { { dbgs() << "Case clusters: "; for (const CaseCluster
&C : Clusters) { if (C.Kind == CC_JumpTable) dbgs() <<
"JT:"; if (C.Kind == CC_BitTests) dbgs() << "BT:"; C.Low
->getValue().print(dbgs(), true); if (C.Low != C.High) { dbgs
() << '-'; C.High->getValue().print(dbgs(), true); }
dbgs() << ' '; } dbgs() << '\n'; }; } } while (false
)
10437 dbgs() << '\n';do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { { dbgs() << "Case clusters: "; for (const CaseCluster
&C : Clusters) { if (C.Kind == CC_JumpTable) dbgs() <<
"JT:"; if (C.Kind == CC_BitTests) dbgs() << "BT:"; C.Low
->getValue().print(dbgs(), true); if (C.Low != C.High) { dbgs
() << '-'; C.High->getValue().print(dbgs(), true); }
dbgs() << ' '; } dbgs() << '\n'; }; } } while (false
)
10438 })do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { { dbgs() << "Case clusters: "; for (const CaseCluster
&C : Clusters) { if (C.Kind == CC_JumpTable) dbgs() <<
"JT:"; if (C.Kind == CC_BitTests) dbgs() << "BT:"; C.Low
->getValue().print(dbgs(), true); if (C.Low != C.High) { dbgs
() << '-'; C.High->getValue().print(dbgs(), true); }
dbgs() << ' '; } dbgs() << '\n'; }; } } while (false
)
;
10439
10440 assert(!Clusters.empty())((!Clusters.empty()) ? static_cast<void> (0) : __assert_fail
("!Clusters.empty()", "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 10440, __PRETTY_FUNCTION__))
;
10441 SwitchWorkList WorkList;
10442 CaseClusterIt First = Clusters.begin();
10443 CaseClusterIt Last = Clusters.end() - 1;
10444 auto DefaultProb = getEdgeProbability(PeeledSwitchMBB, DefaultMBB);
10445 // Scale the branchprobability for DefaultMBB if the peel occurs and
10446 // DefaultMBB is not replaced.
10447 if (PeeledCaseProb != BranchProbability::getZero() &&
10448 DefaultMBB == FuncInfo.MBBMap[SI.getDefaultDest()])
10449 DefaultProb = scaleCaseProbality(DefaultProb, PeeledCaseProb);
10450 WorkList.push_back(
10451 {PeeledSwitchMBB, First, Last, nullptr, nullptr, DefaultProb});
10452
10453 while (!WorkList.empty()) {
10454 SwitchWorkListItem W = WorkList.back();
10455 WorkList.pop_back();
10456 unsigned NumClusters = W.LastCluster - W.FirstCluster + 1;
10457
10458 if (NumClusters > 3 && TM.getOptLevel() != CodeGenOpt::None &&
10459 !DefaultMBB->getParent()->getFunction().optForMinSize()) {
10460 // For optimized builds, lower large range as a balanced binary tree.
10461 splitWorkItem(WorkList, W, SI.getCondition(), SwitchMBB);
10462 continue;
10463 }
10464
10465 lowerWorkItem(W, SI.getCondition(), SwitchMBB, DefaultMBB);
10466 }
10467}