Bug Summary

File:lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
Warning:line 8863, column 9
Method called on moved-from object 'Offsets'

Annotated Source Code

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clang -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name SelectionDAGBuilder.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mthread-model posix -fmath-errno -masm-verbose -mconstructor-aliases -munwind-tables -fuse-init-array -target-cpu x86-64 -dwarf-column-info -debugger-tuning=gdb -momit-leaf-frame-pointer -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-9/lib/clang/9.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-9~svn359999/build-llvm/lib/CodeGen/SelectionDAG -I /build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG -I /build/llvm-toolchain-snapshot-9~svn359999/build-llvm/include -I /build/llvm-toolchain-snapshot-9~svn359999/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0/backward -internal-isystem /usr/include/clang/9.0.0/include/ -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-9/lib/clang/9.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++11 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-9~svn359999/build-llvm/lib/CodeGen/SelectionDAG -fdebug-prefix-map=/build/llvm-toolchain-snapshot-9~svn359999=. -ferror-limit 19 -fmessage-length 0 -fvisibility-inlines-hidden -stack-protector 2 -fobjc-runtime=gcc -fdiagnostics-show-option -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -o /tmp/scan-build-2019-05-06-051613-19774-1 -x c++ /build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp -faddrsig
1//===- SelectionDAGBuilder.cpp - Selection-DAG building -------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This implements routines for translating from LLVM IR into SelectionDAG IR.
10//
11//===----------------------------------------------------------------------===//
12
13#include "SelectionDAGBuilder.h"
14#include "SDNodeDbgValue.h"
15#include "llvm/ADT/APFloat.h"
16#include "llvm/ADT/APInt.h"
17#include "llvm/ADT/ArrayRef.h"
18#include "llvm/ADT/BitVector.h"
19#include "llvm/ADT/DenseMap.h"
20#include "llvm/ADT/None.h"
21#include "llvm/ADT/Optional.h"
22#include "llvm/ADT/STLExtras.h"
23#include "llvm/ADT/SmallPtrSet.h"
24#include "llvm/ADT/SmallSet.h"
25#include "llvm/ADT/SmallVector.h"
26#include "llvm/ADT/StringRef.h"
27#include "llvm/ADT/Triple.h"
28#include "llvm/ADT/Twine.h"
29#include "llvm/Analysis/AliasAnalysis.h"
30#include "llvm/Analysis/BranchProbabilityInfo.h"
31#include "llvm/Analysis/ConstantFolding.h"
32#include "llvm/Analysis/EHPersonalities.h"
33#include "llvm/Analysis/Loads.h"
34#include "llvm/Analysis/MemoryLocation.h"
35#include "llvm/Analysis/TargetLibraryInfo.h"
36#include "llvm/Analysis/ValueTracking.h"
37#include "llvm/Analysis/VectorUtils.h"
38#include "llvm/CodeGen/Analysis.h"
39#include "llvm/CodeGen/FunctionLoweringInfo.h"
40#include "llvm/CodeGen/GCMetadata.h"
41#include "llvm/CodeGen/ISDOpcodes.h"
42#include "llvm/CodeGen/MachineBasicBlock.h"
43#include "llvm/CodeGen/MachineFrameInfo.h"
44#include "llvm/CodeGen/MachineFunction.h"
45#include "llvm/CodeGen/MachineInstr.h"
46#include "llvm/CodeGen/MachineInstrBuilder.h"
47#include "llvm/CodeGen/MachineJumpTableInfo.h"
48#include "llvm/CodeGen/MachineMemOperand.h"
49#include "llvm/CodeGen/MachineModuleInfo.h"
50#include "llvm/CodeGen/MachineOperand.h"
51#include "llvm/CodeGen/MachineRegisterInfo.h"
52#include "llvm/CodeGen/RuntimeLibcalls.h"
53#include "llvm/CodeGen/SelectionDAG.h"
54#include "llvm/CodeGen/SelectionDAGNodes.h"
55#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
56#include "llvm/CodeGen/StackMaps.h"
57#include "llvm/CodeGen/TargetFrameLowering.h"
58#include "llvm/CodeGen/TargetInstrInfo.h"
59#include "llvm/CodeGen/TargetLowering.h"
60#include "llvm/CodeGen/TargetOpcodes.h"
61#include "llvm/CodeGen/TargetRegisterInfo.h"
62#include "llvm/CodeGen/TargetSubtargetInfo.h"
63#include "llvm/CodeGen/ValueTypes.h"
64#include "llvm/CodeGen/WinEHFuncInfo.h"
65#include "llvm/IR/Argument.h"
66#include "llvm/IR/Attributes.h"
67#include "llvm/IR/BasicBlock.h"
68#include "llvm/IR/CFG.h"
69#include "llvm/IR/CallSite.h"
70#include "llvm/IR/CallingConv.h"
71#include "llvm/IR/Constant.h"
72#include "llvm/IR/ConstantRange.h"
73#include "llvm/IR/Constants.h"
74#include "llvm/IR/DataLayout.h"
75#include "llvm/IR/DebugInfoMetadata.h"
76#include "llvm/IR/DebugLoc.h"
77#include "llvm/IR/DerivedTypes.h"
78#include "llvm/IR/Function.h"
79#include "llvm/IR/GetElementPtrTypeIterator.h"
80#include "llvm/IR/InlineAsm.h"
81#include "llvm/IR/InstrTypes.h"
82#include "llvm/IR/Instruction.h"
83#include "llvm/IR/Instructions.h"
84#include "llvm/IR/IntrinsicInst.h"
85#include "llvm/IR/Intrinsics.h"
86#include "llvm/IR/LLVMContext.h"
87#include "llvm/IR/Metadata.h"
88#include "llvm/IR/Module.h"
89#include "llvm/IR/Operator.h"
90#include "llvm/IR/PatternMatch.h"
91#include "llvm/IR/Statepoint.h"
92#include "llvm/IR/Type.h"
93#include "llvm/IR/User.h"
94#include "llvm/IR/Value.h"
95#include "llvm/MC/MCContext.h"
96#include "llvm/MC/MCSymbol.h"
97#include "llvm/Support/AtomicOrdering.h"
98#include "llvm/Support/BranchProbability.h"
99#include "llvm/Support/Casting.h"
100#include "llvm/Support/CodeGen.h"
101#include "llvm/Support/CommandLine.h"
102#include "llvm/Support/Compiler.h"
103#include "llvm/Support/Debug.h"
104#include "llvm/Support/ErrorHandling.h"
105#include "llvm/Support/MachineValueType.h"
106#include "llvm/Support/MathExtras.h"
107#include "llvm/Support/raw_ostream.h"
108#include "llvm/Target/TargetIntrinsicInfo.h"
109#include "llvm/Target/TargetMachine.h"
110#include "llvm/Target/TargetOptions.h"
111#include "llvm/Transforms/Utils/Local.h"
112#include <algorithm>
113#include <cassert>
114#include <cstddef>
115#include <cstdint>
116#include <cstring>
117#include <iterator>
118#include <limits>
119#include <numeric>
120#include <tuple>
121#include <utility>
122#include <vector>
123
124using namespace llvm;
125using namespace PatternMatch;
126
127#define DEBUG_TYPE"isel" "isel"
128
129/// LimitFloatPrecision - Generate low-precision inline sequences for
130/// some float libcalls (6, 8 or 12 bits).
131static unsigned LimitFloatPrecision;
132
133static cl::opt<unsigned, true>
134 LimitFPPrecision("limit-float-precision",
135 cl::desc("Generate low-precision inline sequences "
136 "for some float libcalls"),
137 cl::location(LimitFloatPrecision), cl::Hidden,
138 cl::init(0));
139
140static cl::opt<unsigned> SwitchPeelThreshold(
141 "switch-peel-threshold", cl::Hidden, cl::init(66),
142 cl::desc("Set the case probability threshold for peeling the case from a "
143 "switch statement. A value greater than 100 will void this "
144 "optimization"));
145
146// Limit the width of DAG chains. This is important in general to prevent
147// DAG-based analysis from blowing up. For example, alias analysis and
148// load clustering may not complete in reasonable time. It is difficult to
149// recognize and avoid this situation within each individual analysis, and
150// future analyses are likely to have the same behavior. Limiting DAG width is
151// the safe approach and will be especially important with global DAGs.
152//
153// MaxParallelChains default is arbitrarily high to avoid affecting
154// optimization, but could be lowered to improve compile time. Any ld-ld-st-st
155// sequence over this should have been converted to llvm.memcpy by the
156// frontend. It is easy to induce this behavior with .ll code such as:
157// %buffer = alloca [4096 x i8]
158// %data = load [4096 x i8]* %argPtr
159// store [4096 x i8] %data, [4096 x i8]* %buffer
160static const unsigned MaxParallelChains = 64;
161
162// Return the calling convention if the Value passed requires ABI mangling as it
163// is a parameter to a function or a return value from a function which is not
164// an intrinsic.
165static Optional<CallingConv::ID> getABIRegCopyCC(const Value *V) {
166 if (auto *R = dyn_cast<ReturnInst>(V))
167 return R->getParent()->getParent()->getCallingConv();
168
169 if (auto *CI = dyn_cast<CallInst>(V)) {
170 const bool IsInlineAsm = CI->isInlineAsm();
171 const bool IsIndirectFunctionCall =
172 !IsInlineAsm && !CI->getCalledFunction();
173
174 // It is possible that the call instruction is an inline asm statement or an
175 // indirect function call in which case the return value of
176 // getCalledFunction() would be nullptr.
177 const bool IsInstrinsicCall =
178 !IsInlineAsm && !IsIndirectFunctionCall &&
179 CI->getCalledFunction()->getIntrinsicID() != Intrinsic::not_intrinsic;
180
181 if (!IsInlineAsm && !IsInstrinsicCall)
182 return CI->getCallingConv();
183 }
184
185 return None;
186}
187
188static SDValue getCopyFromPartsVector(SelectionDAG &DAG, const SDLoc &DL,
189 const SDValue *Parts, unsigned NumParts,
190 MVT PartVT, EVT ValueVT, const Value *V,
191 Optional<CallingConv::ID> CC);
192
193/// getCopyFromParts - Create a value that contains the specified legal parts
194/// combined into the value they represent. If the parts combine to a type
195/// larger than ValueVT then AssertOp can be used to specify whether the extra
196/// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
197/// (ISD::AssertSext).
198static SDValue getCopyFromParts(SelectionDAG &DAG, const SDLoc &DL,
199 const SDValue *Parts, unsigned NumParts,
200 MVT PartVT, EVT ValueVT, const Value *V,
201 Optional<CallingConv::ID> CC = None,
202 Optional<ISD::NodeType> AssertOp = None) {
203 if (ValueVT.isVector())
204 return getCopyFromPartsVector(DAG, DL, Parts, NumParts, PartVT, ValueVT, V,
205 CC);
206
207 assert(NumParts > 0 && "No parts to assemble!")((NumParts > 0 && "No parts to assemble!") ? static_cast
<void> (0) : __assert_fail ("NumParts > 0 && \"No parts to assemble!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 207, __PRETTY_FUNCTION__))
;
208 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
209 SDValue Val = Parts[0];
210
211 if (NumParts > 1) {
212 // Assemble the value from multiple parts.
213 if (ValueVT.isInteger()) {
214 unsigned PartBits = PartVT.getSizeInBits();
215 unsigned ValueBits = ValueVT.getSizeInBits();
216
217 // Assemble the power of 2 part.
218 unsigned RoundParts = NumParts & (NumParts - 1) ?
219 1 << Log2_32(NumParts) : NumParts;
220 unsigned RoundBits = PartBits * RoundParts;
221 EVT RoundVT = RoundBits == ValueBits ?
222 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
223 SDValue Lo, Hi;
224
225 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
226
227 if (RoundParts > 2) {
228 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2,
229 PartVT, HalfVT, V);
230 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2,
231 RoundParts / 2, PartVT, HalfVT, V);
232 } else {
233 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]);
234 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]);
235 }
236
237 if (DAG.getDataLayout().isBigEndian())
238 std::swap(Lo, Hi);
239
240 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
241
242 if (RoundParts < NumParts) {
243 // Assemble the trailing non-power-of-2 part.
244 unsigned OddParts = NumParts - RoundParts;
245 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
246 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts, OddParts, PartVT,
247 OddVT, V, CC);
248
249 // Combine the round and odd parts.
250 Lo = Val;
251 if (DAG.getDataLayout().isBigEndian())
252 std::swap(Lo, Hi);
253 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
254 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi);
255 Hi =
256 DAG.getNode(ISD::SHL, DL, TotalVT, Hi,
257 DAG.getConstant(Lo.getValueSizeInBits(), DL,
258 TLI.getPointerTy(DAG.getDataLayout())));
259 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo);
260 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi);
261 }
262 } else if (PartVT.isFloatingPoint()) {
263 // FP split into multiple FP parts (for ppcf128)
264 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 &&((ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 &&
"Unexpected split") ? static_cast<void> (0) : __assert_fail
("ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 && \"Unexpected split\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 265, __PRETTY_FUNCTION__))
265 "Unexpected split")((ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 &&
"Unexpected split") ? static_cast<void> (0) : __assert_fail
("ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 && \"Unexpected split\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 265, __PRETTY_FUNCTION__))
;
266 SDValue Lo, Hi;
267 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]);
268 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]);
269 if (TLI.hasBigEndianPartOrdering(ValueVT, DAG.getDataLayout()))
270 std::swap(Lo, Hi);
271 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi);
272 } else {
273 // FP split into integer parts (soft fp)
274 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&((ValueVT.isFloatingPoint() && PartVT.isInteger() &&
!PartVT.isVector() && "Unexpected split") ? static_cast
<void> (0) : __assert_fail ("ValueVT.isFloatingPoint() && PartVT.isInteger() && !PartVT.isVector() && \"Unexpected split\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 275, __PRETTY_FUNCTION__))
275 !PartVT.isVector() && "Unexpected split")((ValueVT.isFloatingPoint() && PartVT.isInteger() &&
!PartVT.isVector() && "Unexpected split") ? static_cast
<void> (0) : __assert_fail ("ValueVT.isFloatingPoint() && PartVT.isInteger() && !PartVT.isVector() && \"Unexpected split\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 275, __PRETTY_FUNCTION__))
;
276 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
277 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT, V, CC);
278 }
279 }
280
281 // There is now one part, held in Val. Correct it to match ValueVT.
282 // PartEVT is the type of the register class that holds the value.
283 // ValueVT is the type of the inline asm operation.
284 EVT PartEVT = Val.getValueType();
285
286 if (PartEVT == ValueVT)
287 return Val;
288
289 if (PartEVT.isInteger() && ValueVT.isFloatingPoint() &&
290 ValueVT.bitsLT(PartEVT)) {
291 // For an FP value in an integer part, we need to truncate to the right
292 // width first.
293 PartEVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
294 Val = DAG.getNode(ISD::TRUNCATE, DL, PartEVT, Val);
295 }
296
297 // Handle types that have the same size.
298 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits())
299 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
300
301 // Handle types with different sizes.
302 if (PartEVT.isInteger() && ValueVT.isInteger()) {
303 if (ValueVT.bitsLT(PartEVT)) {
304 // For a truncate, see if we have any information to
305 // indicate whether the truncated bits will always be
306 // zero or sign-extension.
307 if (AssertOp.hasValue())
308 Val = DAG.getNode(*AssertOp, DL, PartEVT, Val,
309 DAG.getValueType(ValueVT));
310 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
311 }
312 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val);
313 }
314
315 if (PartEVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
316 // FP_ROUND's are always exact here.
317 if (ValueVT.bitsLT(Val.getValueType()))
318 return DAG.getNode(
319 ISD::FP_ROUND, DL, ValueVT, Val,
320 DAG.getTargetConstant(1, DL, TLI.getPointerTy(DAG.getDataLayout())));
321
322 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);
323 }
324
325 llvm_unreachable("Unknown mismatch!")::llvm::llvm_unreachable_internal("Unknown mismatch!", "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 325)
;
326}
327
328static void diagnosePossiblyInvalidConstraint(LLVMContext &Ctx, const Value *V,
329 const Twine &ErrMsg) {
330 const Instruction *I = dyn_cast_or_null<Instruction>(V);
331 if (!V)
332 return Ctx.emitError(ErrMsg);
333
334 const char *AsmError = ", possible invalid constraint for vector type";
335 if (const CallInst *CI = dyn_cast<CallInst>(I))
336 if (isa<InlineAsm>(CI->getCalledValue()))
337 return Ctx.emitError(I, ErrMsg + AsmError);
338
339 return Ctx.emitError(I, ErrMsg);
340}
341
342/// getCopyFromPartsVector - Create a value that contains the specified legal
343/// parts combined into the value they represent. If the parts combine to a
344/// type larger than ValueVT then AssertOp can be used to specify whether the
345/// extra bits are known to be zero (ISD::AssertZext) or sign extended from
346/// ValueVT (ISD::AssertSext).
347static SDValue getCopyFromPartsVector(SelectionDAG &DAG, const SDLoc &DL,
348 const SDValue *Parts, unsigned NumParts,
349 MVT PartVT, EVT ValueVT, const Value *V,
350 Optional<CallingConv::ID> CallConv) {
351 assert(ValueVT.isVector() && "Not a vector value")((ValueVT.isVector() && "Not a vector value") ? static_cast
<void> (0) : __assert_fail ("ValueVT.isVector() && \"Not a vector value\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 351, __PRETTY_FUNCTION__))
;
352 assert(NumParts > 0 && "No parts to assemble!")((NumParts > 0 && "No parts to assemble!") ? static_cast
<void> (0) : __assert_fail ("NumParts > 0 && \"No parts to assemble!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 352, __PRETTY_FUNCTION__))
;
353 const bool IsABIRegCopy = CallConv.hasValue();
354
355 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
356 SDValue Val = Parts[0];
357
358 // Handle a multi-element vector.
359 if (NumParts > 1) {
360 EVT IntermediateVT;
361 MVT RegisterVT;
362 unsigned NumIntermediates;
363 unsigned NumRegs;
364
365 if (IsABIRegCopy) {
366 NumRegs = TLI.getVectorTypeBreakdownForCallingConv(
367 *DAG.getContext(), CallConv.getValue(), ValueVT, IntermediateVT,
368 NumIntermediates, RegisterVT);
369 } else {
370 NumRegs =
371 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
372 NumIntermediates, RegisterVT);
373 }
374
375 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!")((NumRegs == NumParts && "Part count doesn't match vector breakdown!"
) ? static_cast<void> (0) : __assert_fail ("NumRegs == NumParts && \"Part count doesn't match vector breakdown!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 375, __PRETTY_FUNCTION__))
;
376 NumParts = NumRegs; // Silence a compiler warning.
377 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!")((RegisterVT == PartVT && "Part type doesn't match vector breakdown!"
) ? static_cast<void> (0) : __assert_fail ("RegisterVT == PartVT && \"Part type doesn't match vector breakdown!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 377, __PRETTY_FUNCTION__))
;
378 assert(RegisterVT.getSizeInBits() ==((RegisterVT.getSizeInBits() == Parts[0].getSimpleValueType()
.getSizeInBits() && "Part type sizes don't match!") ?
static_cast<void> (0) : __assert_fail ("RegisterVT.getSizeInBits() == Parts[0].getSimpleValueType().getSizeInBits() && \"Part type sizes don't match!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 380, __PRETTY_FUNCTION__))
379 Parts[0].getSimpleValueType().getSizeInBits() &&((RegisterVT.getSizeInBits() == Parts[0].getSimpleValueType()
.getSizeInBits() && "Part type sizes don't match!") ?
static_cast<void> (0) : __assert_fail ("RegisterVT.getSizeInBits() == Parts[0].getSimpleValueType().getSizeInBits() && \"Part type sizes don't match!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 380, __PRETTY_FUNCTION__))
380 "Part type sizes don't match!")((RegisterVT.getSizeInBits() == Parts[0].getSimpleValueType()
.getSizeInBits() && "Part type sizes don't match!") ?
static_cast<void> (0) : __assert_fail ("RegisterVT.getSizeInBits() == Parts[0].getSimpleValueType().getSizeInBits() && \"Part type sizes don't match!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 380, __PRETTY_FUNCTION__))
;
381
382 // Assemble the parts into intermediate operands.
383 SmallVector<SDValue, 8> Ops(NumIntermediates);
384 if (NumIntermediates == NumParts) {
385 // If the register was not expanded, truncate or copy the value,
386 // as appropriate.
387 for (unsigned i = 0; i != NumParts; ++i)
388 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1,
389 PartVT, IntermediateVT, V);
390 } else if (NumParts > 0) {
391 // If the intermediate type was expanded, build the intermediate
392 // operands from the parts.
393 assert(NumParts % NumIntermediates == 0 &&((NumParts % NumIntermediates == 0 && "Must expand into a divisible number of parts!"
) ? static_cast<void> (0) : __assert_fail ("NumParts % NumIntermediates == 0 && \"Must expand into a divisible number of parts!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 394, __PRETTY_FUNCTION__))
394 "Must expand into a divisible number of parts!")((NumParts % NumIntermediates == 0 && "Must expand into a divisible number of parts!"
) ? static_cast<void> (0) : __assert_fail ("NumParts % NumIntermediates == 0 && \"Must expand into a divisible number of parts!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 394, __PRETTY_FUNCTION__))
;
395 unsigned Factor = NumParts / NumIntermediates;
396 for (unsigned i = 0; i != NumIntermediates; ++i)
397 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor,
398 PartVT, IntermediateVT, V);
399 }
400
401 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
402 // intermediate operands.
403 EVT BuiltVectorTy =
404 EVT::getVectorVT(*DAG.getContext(), IntermediateVT.getScalarType(),
405 (IntermediateVT.isVector()
406 ? IntermediateVT.getVectorNumElements() * NumParts
407 : NumIntermediates));
408 Val = DAG.getNode(IntermediateVT.isVector() ? ISD::CONCAT_VECTORS
409 : ISD::BUILD_VECTOR,
410 DL, BuiltVectorTy, Ops);
411 }
412
413 // There is now one part, held in Val. Correct it to match ValueVT.
414 EVT PartEVT = Val.getValueType();
415
416 if (PartEVT == ValueVT)
417 return Val;
418
419 if (PartEVT.isVector()) {
420 // If the element type of the source/dest vectors are the same, but the
421 // parts vector has more elements than the value vector, then we have a
422 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the
423 // elements we want.
424 if (PartEVT.getVectorElementType() == ValueVT.getVectorElementType()) {
425 assert(PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements() &&((PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements
() && "Cannot narrow, it would be a lossy transformation"
) ? static_cast<void> (0) : __assert_fail ("PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements() && \"Cannot narrow, it would be a lossy transformation\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 426, __PRETTY_FUNCTION__))
426 "Cannot narrow, it would be a lossy transformation")((PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements
() && "Cannot narrow, it would be a lossy transformation"
) ? static_cast<void> (0) : __assert_fail ("PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements() && \"Cannot narrow, it would be a lossy transformation\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 426, __PRETTY_FUNCTION__))
;
427 return DAG.getNode(
428 ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
429 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
430 }
431
432 // Vector/Vector bitcast.
433 if (ValueVT.getSizeInBits() == PartEVT.getSizeInBits())
434 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
435
436 assert(PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements() &&((PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements
() && "Cannot handle this kind of promotion") ? static_cast
<void> (0) : __assert_fail ("PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements() && \"Cannot handle this kind of promotion\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 437, __PRETTY_FUNCTION__))
437 "Cannot handle this kind of promotion")((PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements
() && "Cannot handle this kind of promotion") ? static_cast
<void> (0) : __assert_fail ("PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements() && \"Cannot handle this kind of promotion\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 437, __PRETTY_FUNCTION__))
;
438 // Promoted vector extract
439 return DAG.getAnyExtOrTrunc(Val, DL, ValueVT);
440
441 }
442
443 // Trivial bitcast if the types are the same size and the destination
444 // vector type is legal.
445 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits() &&
446 TLI.isTypeLegal(ValueVT))
447 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
448
449 if (ValueVT.getVectorNumElements() != 1) {
450 // Certain ABIs require that vectors are passed as integers. For vectors
451 // are the same size, this is an obvious bitcast.
452 if (ValueVT.getSizeInBits() == PartEVT.getSizeInBits()) {
453 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
454 } else if (ValueVT.getSizeInBits() < PartEVT.getSizeInBits()) {
455 // Bitcast Val back the original type and extract the corresponding
456 // vector we want.
457 unsigned Elts = PartEVT.getSizeInBits() / ValueVT.getScalarSizeInBits();
458 EVT WiderVecType = EVT::getVectorVT(*DAG.getContext(),
459 ValueVT.getVectorElementType(), Elts);
460 Val = DAG.getBitcast(WiderVecType, Val);
461 return DAG.getNode(
462 ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
463 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
464 }
465
466 diagnosePossiblyInvalidConstraint(
467 *DAG.getContext(), V, "non-trivial scalar-to-vector conversion");
468 return DAG.getUNDEF(ValueVT);
469 }
470
471 // Handle cases such as i8 -> <1 x i1>
472 EVT ValueSVT = ValueVT.getVectorElementType();
473 if (ValueVT.getVectorNumElements() == 1 && ValueSVT != PartEVT)
474 Val = ValueVT.isFloatingPoint() ? DAG.getFPExtendOrRound(Val, DL, ValueSVT)
475 : DAG.getAnyExtOrTrunc(Val, DL, ValueSVT);
476
477 return DAG.getBuildVector(ValueVT, DL, Val);
478}
479
480static void getCopyToPartsVector(SelectionDAG &DAG, const SDLoc &dl,
481 SDValue Val, SDValue *Parts, unsigned NumParts,
482 MVT PartVT, const Value *V,
483 Optional<CallingConv::ID> CallConv);
484
485/// getCopyToParts - Create a series of nodes that contain the specified value
486/// split into legal parts. If the parts contain more bits than Val, then, for
487/// integers, ExtendKind can be used to specify how to generate the extra bits.
488static void getCopyToParts(SelectionDAG &DAG, const SDLoc &DL, SDValue Val,
489 SDValue *Parts, unsigned NumParts, MVT PartVT,
490 const Value *V,
491 Optional<CallingConv::ID> CallConv = None,
492 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
493 EVT ValueVT = Val.getValueType();
494
495 // Handle the vector case separately.
496 if (ValueVT.isVector())
497 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT, V,
498 CallConv);
499
500 unsigned PartBits = PartVT.getSizeInBits();
501 unsigned OrigNumParts = NumParts;
502 assert(DAG.getTargetLoweringInfo().isTypeLegal(PartVT) &&((DAG.getTargetLoweringInfo().isTypeLegal(PartVT) && "Copying to an illegal type!"
) ? static_cast<void> (0) : __assert_fail ("DAG.getTargetLoweringInfo().isTypeLegal(PartVT) && \"Copying to an illegal type!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 503, __PRETTY_FUNCTION__))
503 "Copying to an illegal type!")((DAG.getTargetLoweringInfo().isTypeLegal(PartVT) && "Copying to an illegal type!"
) ? static_cast<void> (0) : __assert_fail ("DAG.getTargetLoweringInfo().isTypeLegal(PartVT) && \"Copying to an illegal type!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 503, __PRETTY_FUNCTION__))
;
504
505 if (NumParts == 0)
506 return;
507
508 assert(!ValueVT.isVector() && "Vector case handled elsewhere")((!ValueVT.isVector() && "Vector case handled elsewhere"
) ? static_cast<void> (0) : __assert_fail ("!ValueVT.isVector() && \"Vector case handled elsewhere\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 508, __PRETTY_FUNCTION__))
;
509 EVT PartEVT = PartVT;
510 if (PartEVT == ValueVT) {
511 assert(NumParts == 1 && "No-op copy with multiple parts!")((NumParts == 1 && "No-op copy with multiple parts!")
? static_cast<void> (0) : __assert_fail ("NumParts == 1 && \"No-op copy with multiple parts!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 511, __PRETTY_FUNCTION__))
;
512 Parts[0] = Val;
513 return;
514 }
515
516 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
517 // If the parts cover more bits than the value has, promote the value.
518 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
519 assert(NumParts == 1 && "Do not know what to promote to!")((NumParts == 1 && "Do not know what to promote to!")
? static_cast<void> (0) : __assert_fail ("NumParts == 1 && \"Do not know what to promote to!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 519, __PRETTY_FUNCTION__))
;
520 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val);
521 } else {
522 if (ValueVT.isFloatingPoint()) {
523 // FP values need to be bitcast, then extended if they are being put
524 // into a larger container.
525 ValueVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
526 Val = DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
527 }
528 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&(((PartVT.isInteger() || PartVT == MVT::x86mmx) && ValueVT
.isInteger() && "Unknown mismatch!") ? static_cast<
void> (0) : __assert_fail ("(PartVT.isInteger() || PartVT == MVT::x86mmx) && ValueVT.isInteger() && \"Unknown mismatch!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 530, __PRETTY_FUNCTION__))
529 ValueVT.isInteger() &&(((PartVT.isInteger() || PartVT == MVT::x86mmx) && ValueVT
.isInteger() && "Unknown mismatch!") ? static_cast<
void> (0) : __assert_fail ("(PartVT.isInteger() || PartVT == MVT::x86mmx) && ValueVT.isInteger() && \"Unknown mismatch!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 530, __PRETTY_FUNCTION__))
530 "Unknown mismatch!")(((PartVT.isInteger() || PartVT == MVT::x86mmx) && ValueVT
.isInteger() && "Unknown mismatch!") ? static_cast<
void> (0) : __assert_fail ("(PartVT.isInteger() || PartVT == MVT::x86mmx) && ValueVT.isInteger() && \"Unknown mismatch!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 530, __PRETTY_FUNCTION__))
;
531 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
532 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val);
533 if (PartVT == MVT::x86mmx)
534 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
535 }
536 } else if (PartBits == ValueVT.getSizeInBits()) {
537 // Different types of the same size.
538 assert(NumParts == 1 && PartEVT != ValueVT)((NumParts == 1 && PartEVT != ValueVT) ? static_cast<
void> (0) : __assert_fail ("NumParts == 1 && PartEVT != ValueVT"
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 538, __PRETTY_FUNCTION__))
;
539 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
540 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
541 // If the parts cover less bits than value has, truncate the value.
542 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&(((PartVT.isInteger() || PartVT == MVT::x86mmx) && ValueVT
.isInteger() && "Unknown mismatch!") ? static_cast<
void> (0) : __assert_fail ("(PartVT.isInteger() || PartVT == MVT::x86mmx) && ValueVT.isInteger() && \"Unknown mismatch!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 544, __PRETTY_FUNCTION__))
543 ValueVT.isInteger() &&(((PartVT.isInteger() || PartVT == MVT::x86mmx) && ValueVT
.isInteger() && "Unknown mismatch!") ? static_cast<
void> (0) : __assert_fail ("(PartVT.isInteger() || PartVT == MVT::x86mmx) && ValueVT.isInteger() && \"Unknown mismatch!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 544, __PRETTY_FUNCTION__))
544 "Unknown mismatch!")(((PartVT.isInteger() || PartVT == MVT::x86mmx) && ValueVT
.isInteger() && "Unknown mismatch!") ? static_cast<
void> (0) : __assert_fail ("(PartVT.isInteger() || PartVT == MVT::x86mmx) && ValueVT.isInteger() && \"Unknown mismatch!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 544, __PRETTY_FUNCTION__))
;
545 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
546 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
547 if (PartVT == MVT::x86mmx)
548 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
549 }
550
551 // The value may have changed - recompute ValueVT.
552 ValueVT = Val.getValueType();
553 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&((NumParts * PartBits == ValueVT.getSizeInBits() && "Failed to tile the value with PartVT!"
) ? static_cast<void> (0) : __assert_fail ("NumParts * PartBits == ValueVT.getSizeInBits() && \"Failed to tile the value with PartVT!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 554, __PRETTY_FUNCTION__))
554 "Failed to tile the value with PartVT!")((NumParts * PartBits == ValueVT.getSizeInBits() && "Failed to tile the value with PartVT!"
) ? static_cast<void> (0) : __assert_fail ("NumParts * PartBits == ValueVT.getSizeInBits() && \"Failed to tile the value with PartVT!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 554, __PRETTY_FUNCTION__))
;
555
556 if (NumParts == 1) {
557 if (PartEVT != ValueVT) {
558 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
559 "scalar-to-vector conversion failed");
560 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
561 }
562
563 Parts[0] = Val;
564 return;
565 }
566
567 // Expand the value into multiple parts.
568 if (NumParts & (NumParts - 1)) {
569 // The number of parts is not a power of 2. Split off and copy the tail.
570 assert(PartVT.isInteger() && ValueVT.isInteger() &&((PartVT.isInteger() && ValueVT.isInteger() &&
"Do not know what to expand to!") ? static_cast<void> (
0) : __assert_fail ("PartVT.isInteger() && ValueVT.isInteger() && \"Do not know what to expand to!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 571, __PRETTY_FUNCTION__))
571 "Do not know what to expand to!")((PartVT.isInteger() && ValueVT.isInteger() &&
"Do not know what to expand to!") ? static_cast<void> (
0) : __assert_fail ("PartVT.isInteger() && ValueVT.isInteger() && \"Do not know what to expand to!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 571, __PRETTY_FUNCTION__))
;
572 unsigned RoundParts = 1 << Log2_32(NumParts);
573 unsigned RoundBits = RoundParts * PartBits;
574 unsigned OddParts = NumParts - RoundParts;
575 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val,
576 DAG.getShiftAmountConstant(RoundBits, ValueVT, DL, /*LegalTypes*/false));
577
578 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT, V,
579 CallConv);
580
581 if (DAG.getDataLayout().isBigEndian())
582 // The odd parts were reversed by getCopyToParts - unreverse them.
583 std::reverse(Parts + RoundParts, Parts + NumParts);
584
585 NumParts = RoundParts;
586 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
587 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
588 }
589
590 // The number of parts is a power of 2. Repeatedly bisect the value using
591 // EXTRACT_ELEMENT.
592 Parts[0] = DAG.getNode(ISD::BITCAST, DL,
593 EVT::getIntegerVT(*DAG.getContext(),
594 ValueVT.getSizeInBits()),
595 Val);
596
597 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
598 for (unsigned i = 0; i < NumParts; i += StepSize) {
599 unsigned ThisBits = StepSize * PartBits / 2;
600 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
601 SDValue &Part0 = Parts[i];
602 SDValue &Part1 = Parts[i+StepSize/2];
603
604 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
605 ThisVT, Part0, DAG.getIntPtrConstant(1, DL));
606 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
607 ThisVT, Part0, DAG.getIntPtrConstant(0, DL));
608
609 if (ThisBits == PartBits && ThisVT != PartVT) {
610 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0);
611 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1);
612 }
613 }
614 }
615
616 if (DAG.getDataLayout().isBigEndian())
617 std::reverse(Parts, Parts + OrigNumParts);
618}
619
620static SDValue widenVectorToPartType(SelectionDAG &DAG,
621 SDValue Val, const SDLoc &DL, EVT PartVT) {
622 if (!PartVT.isVector())
623 return SDValue();
624
625 EVT ValueVT = Val.getValueType();
626 unsigned PartNumElts = PartVT.getVectorNumElements();
627 unsigned ValueNumElts = ValueVT.getVectorNumElements();
628 if (PartNumElts > ValueNumElts &&
629 PartVT.getVectorElementType() == ValueVT.getVectorElementType()) {
630 EVT ElementVT = PartVT.getVectorElementType();
631 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in
632 // undef elements.
633 SmallVector<SDValue, 16> Ops;
634 DAG.ExtractVectorElements(Val, Ops);
635 SDValue EltUndef = DAG.getUNDEF(ElementVT);
636 for (unsigned i = ValueNumElts, e = PartNumElts; i != e; ++i)
637 Ops.push_back(EltUndef);
638
639 // FIXME: Use CONCAT for 2x -> 4x.
640 return DAG.getBuildVector(PartVT, DL, Ops);
641 }
642
643 return SDValue();
644}
645
646/// getCopyToPartsVector - Create a series of nodes that contain the specified
647/// value split into legal parts.
648static void getCopyToPartsVector(SelectionDAG &DAG, const SDLoc &DL,
649 SDValue Val, SDValue *Parts, unsigned NumParts,
650 MVT PartVT, const Value *V,
651 Optional<CallingConv::ID> CallConv) {
652 EVT ValueVT = Val.getValueType();
653 assert(ValueVT.isVector() && "Not a vector")((ValueVT.isVector() && "Not a vector") ? static_cast
<void> (0) : __assert_fail ("ValueVT.isVector() && \"Not a vector\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 653, __PRETTY_FUNCTION__))
;
654 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
655 const bool IsABIRegCopy = CallConv.hasValue();
656
657 if (NumParts == 1) {
658 EVT PartEVT = PartVT;
659 if (PartEVT == ValueVT) {
660 // Nothing to do.
661 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
662 // Bitconvert vector->vector case.
663 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
664 } else if (SDValue Widened = widenVectorToPartType(DAG, Val, DL, PartVT)) {
665 Val = Widened;
666 } else if (PartVT.isVector() &&
667 PartEVT.getVectorElementType().bitsGE(
668 ValueVT.getVectorElementType()) &&
669 PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements()) {
670
671 // Promoted vector extract
672 Val = DAG.getAnyExtOrTrunc(Val, DL, PartVT);
673 } else {
674 if (ValueVT.getVectorNumElements() == 1) {
675 Val = DAG.getNode(
676 ISD::EXTRACT_VECTOR_ELT, DL, PartVT, Val,
677 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
678 } else {
679 assert(PartVT.getSizeInBits() > ValueVT.getSizeInBits() &&((PartVT.getSizeInBits() > ValueVT.getSizeInBits() &&
"lossy conversion of vector to scalar type") ? static_cast<
void> (0) : __assert_fail ("PartVT.getSizeInBits() > ValueVT.getSizeInBits() && \"lossy conversion of vector to scalar type\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 680, __PRETTY_FUNCTION__))
680 "lossy conversion of vector to scalar type")((PartVT.getSizeInBits() > ValueVT.getSizeInBits() &&
"lossy conversion of vector to scalar type") ? static_cast<
void> (0) : __assert_fail ("PartVT.getSizeInBits() > ValueVT.getSizeInBits() && \"lossy conversion of vector to scalar type\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 680, __PRETTY_FUNCTION__))
;
681 EVT IntermediateType =
682 EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
683 Val = DAG.getBitcast(IntermediateType, Val);
684 Val = DAG.getAnyExtOrTrunc(Val, DL, PartVT);
685 }
686 }
687
688 assert(Val.getValueType() == PartVT && "Unexpected vector part value type")((Val.getValueType() == PartVT && "Unexpected vector part value type"
) ? static_cast<void> (0) : __assert_fail ("Val.getValueType() == PartVT && \"Unexpected vector part value type\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 688, __PRETTY_FUNCTION__))
;
689 Parts[0] = Val;
690 return;
691 }
692
693 // Handle a multi-element vector.
694 EVT IntermediateVT;
695 MVT RegisterVT;
696 unsigned NumIntermediates;
697 unsigned NumRegs;
698 if (IsABIRegCopy) {
699 NumRegs = TLI.getVectorTypeBreakdownForCallingConv(
700 *DAG.getContext(), CallConv.getValue(), ValueVT, IntermediateVT,
701 NumIntermediates, RegisterVT);
702 } else {
703 NumRegs =
704 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
705 NumIntermediates, RegisterVT);
706 }
707
708 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!")((NumRegs == NumParts && "Part count doesn't match vector breakdown!"
) ? static_cast<void> (0) : __assert_fail ("NumRegs == NumParts && \"Part count doesn't match vector breakdown!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 708, __PRETTY_FUNCTION__))
;
709 NumParts = NumRegs; // Silence a compiler warning.
710 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!")((RegisterVT == PartVT && "Part type doesn't match vector breakdown!"
) ? static_cast<void> (0) : __assert_fail ("RegisterVT == PartVT && \"Part type doesn't match vector breakdown!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 710, __PRETTY_FUNCTION__))
;
711
712 unsigned IntermediateNumElts = IntermediateVT.isVector() ?
713 IntermediateVT.getVectorNumElements() : 1;
714
715 // Convert the vector to the appropiate type if necessary.
716 unsigned DestVectorNoElts = NumIntermediates * IntermediateNumElts;
717
718 EVT BuiltVectorTy = EVT::getVectorVT(
719 *DAG.getContext(), IntermediateVT.getScalarType(), DestVectorNoElts);
720 MVT IdxVT = TLI.getVectorIdxTy(DAG.getDataLayout());
721 if (ValueVT != BuiltVectorTy) {
722 if (SDValue Widened = widenVectorToPartType(DAG, Val, DL, BuiltVectorTy))
723 Val = Widened;
724
725 Val = DAG.getNode(ISD::BITCAST, DL, BuiltVectorTy, Val);
726 }
727
728 // Split the vector into intermediate operands.
729 SmallVector<SDValue, 8> Ops(NumIntermediates);
730 for (unsigned i = 0; i != NumIntermediates; ++i) {
731 if (IntermediateVT.isVector()) {
732 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, IntermediateVT, Val,
733 DAG.getConstant(i * IntermediateNumElts, DL, IdxVT));
734 } else {
735 Ops[i] = DAG.getNode(
736 ISD::EXTRACT_VECTOR_ELT, DL, IntermediateVT, Val,
737 DAG.getConstant(i, DL, IdxVT));
738 }
739 }
740
741 // Split the intermediate operands into legal parts.
742 if (NumParts == NumIntermediates) {
743 // If the register was not expanded, promote or copy the value,
744 // as appropriate.
745 for (unsigned i = 0; i != NumParts; ++i)
746 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT, V, CallConv);
747 } else if (NumParts > 0) {
748 // If the intermediate type was expanded, split each the value into
749 // legal parts.
750 assert(NumIntermediates != 0 && "division by zero")((NumIntermediates != 0 && "division by zero") ? static_cast
<void> (0) : __assert_fail ("NumIntermediates != 0 && \"division by zero\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 750, __PRETTY_FUNCTION__))
;
751 assert(NumParts % NumIntermediates == 0 &&((NumParts % NumIntermediates == 0 && "Must expand into a divisible number of parts!"
) ? static_cast<void> (0) : __assert_fail ("NumParts % NumIntermediates == 0 && \"Must expand into a divisible number of parts!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 752, __PRETTY_FUNCTION__))
752 "Must expand into a divisible number of parts!")((NumParts % NumIntermediates == 0 && "Must expand into a divisible number of parts!"
) ? static_cast<void> (0) : __assert_fail ("NumParts % NumIntermediates == 0 && \"Must expand into a divisible number of parts!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 752, __PRETTY_FUNCTION__))
;
753 unsigned Factor = NumParts / NumIntermediates;
754 for (unsigned i = 0; i != NumIntermediates; ++i)
755 getCopyToParts(DAG, DL, Ops[i], &Parts[i * Factor], Factor, PartVT, V,
756 CallConv);
757 }
758}
759
760RegsForValue::RegsForValue(const SmallVector<unsigned, 4> &regs, MVT regvt,
761 EVT valuevt, Optional<CallingConv::ID> CC)
762 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs),
763 RegCount(1, regs.size()), CallConv(CC) {}
764
765RegsForValue::RegsForValue(LLVMContext &Context, const TargetLowering &TLI,
766 const DataLayout &DL, unsigned Reg, Type *Ty,
767 Optional<CallingConv::ID> CC) {
768 ComputeValueVTs(TLI, DL, Ty, ValueVTs);
769
770 CallConv = CC;
771
772 for (EVT ValueVT : ValueVTs) {
773 unsigned NumRegs =
774 isABIMangled()
775 ? TLI.getNumRegistersForCallingConv(Context, CC.getValue(), ValueVT)
776 : TLI.getNumRegisters(Context, ValueVT);
777 MVT RegisterVT =
778 isABIMangled()
779 ? TLI.getRegisterTypeForCallingConv(Context, CC.getValue(), ValueVT)
780 : TLI.getRegisterType(Context, ValueVT);
781 for (unsigned i = 0; i != NumRegs; ++i)
782 Regs.push_back(Reg + i);
783 RegVTs.push_back(RegisterVT);
784 RegCount.push_back(NumRegs);
785 Reg += NumRegs;
786 }
787}
788
789SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
790 FunctionLoweringInfo &FuncInfo,
791 const SDLoc &dl, SDValue &Chain,
792 SDValue *Flag, const Value *V) const {
793 // A Value with type {} or [0 x %t] needs no registers.
794 if (ValueVTs.empty())
795 return SDValue();
796
797 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
798
799 // Assemble the legal parts into the final values.
800 SmallVector<SDValue, 4> Values(ValueVTs.size());
801 SmallVector<SDValue, 8> Parts;
802 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
803 // Copy the legal parts from the registers.
804 EVT ValueVT = ValueVTs[Value];
805 unsigned NumRegs = RegCount[Value];
806 MVT RegisterVT = isABIMangled() ? TLI.getRegisterTypeForCallingConv(
807 *DAG.getContext(),
808 CallConv.getValue(), RegVTs[Value])
809 : RegVTs[Value];
810
811 Parts.resize(NumRegs);
812 for (unsigned i = 0; i != NumRegs; ++i) {
813 SDValue P;
814 if (!Flag) {
815 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
816 } else {
817 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
818 *Flag = P.getValue(2);
819 }
820
821 Chain = P.getValue(1);
822 Parts[i] = P;
823
824 // If the source register was virtual and if we know something about it,
825 // add an assert node.
826 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) ||
827 !RegisterVT.isInteger())
828 continue;
829
830 const FunctionLoweringInfo::LiveOutInfo *LOI =
831 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]);
832 if (!LOI)
833 continue;
834
835 unsigned RegSize = RegisterVT.getScalarSizeInBits();
836 unsigned NumSignBits = LOI->NumSignBits;
837 unsigned NumZeroBits = LOI->Known.countMinLeadingZeros();
838
839 if (NumZeroBits == RegSize) {
840 // The current value is a zero.
841 // Explicitly express that as it would be easier for
842 // optimizations to kick in.
843 Parts[i] = DAG.getConstant(0, dl, RegisterVT);
844 continue;
845 }
846
847 // FIXME: We capture more information than the dag can represent. For
848 // now, just use the tightest assertzext/assertsext possible.
849 bool isSExt;
850 EVT FromVT(MVT::Other);
851 if (NumZeroBits) {
852 FromVT = EVT::getIntegerVT(*DAG.getContext(), RegSize - NumZeroBits);
853 isSExt = false;
854 } else if (NumSignBits > 1) {
855 FromVT =
856 EVT::getIntegerVT(*DAG.getContext(), RegSize - NumSignBits + 1);
857 isSExt = true;
858 } else {
859 continue;
860 }
861 // Add an assertion node.
862 assert(FromVT != MVT::Other)((FromVT != MVT::Other) ? static_cast<void> (0) : __assert_fail
("FromVT != MVT::Other", "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 862, __PRETTY_FUNCTION__))
;
863 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
864 RegisterVT, P, DAG.getValueType(FromVT));
865 }
866
867 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(), NumRegs,
868 RegisterVT, ValueVT, V, CallConv);
869 Part += NumRegs;
870 Parts.clear();
871 }
872
873 return DAG.getNode(ISD::MERGE_VALUES, dl, DAG.getVTList(ValueVTs), Values);
874}
875
876void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG,
877 const SDLoc &dl, SDValue &Chain, SDValue *Flag,
878 const Value *V,
879 ISD::NodeType PreferredExtendType) const {
880 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
881 ISD::NodeType ExtendKind = PreferredExtendType;
882
883 // Get the list of the values's legal parts.
884 unsigned NumRegs = Regs.size();
885 SmallVector<SDValue, 8> Parts(NumRegs);
886 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
887 unsigned NumParts = RegCount[Value];
888
889 MVT RegisterVT = isABIMangled() ? TLI.getRegisterTypeForCallingConv(
890 *DAG.getContext(),
891 CallConv.getValue(), RegVTs[Value])
892 : RegVTs[Value];
893
894 if (ExtendKind == ISD::ANY_EXTEND && TLI.isZExtFree(Val, RegisterVT))
895 ExtendKind = ISD::ZERO_EXTEND;
896
897 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value), &Parts[Part],
898 NumParts, RegisterVT, V, CallConv, ExtendKind);
899 Part += NumParts;
900 }
901
902 // Copy the parts into the registers.
903 SmallVector<SDValue, 8> Chains(NumRegs);
904 for (unsigned i = 0; i != NumRegs; ++i) {
905 SDValue Part;
906 if (!Flag) {
907 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
908 } else {
909 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
910 *Flag = Part.getValue(1);
911 }
912
913 Chains[i] = Part.getValue(0);
914 }
915
916 if (NumRegs == 1 || Flag)
917 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
918 // flagged to it. That is the CopyToReg nodes and the user are considered
919 // a single scheduling unit. If we create a TokenFactor and return it as
920 // chain, then the TokenFactor is both a predecessor (operand) of the
921 // user as well as a successor (the TF operands are flagged to the user).
922 // c1, f1 = CopyToReg
923 // c2, f2 = CopyToReg
924 // c3 = TokenFactor c1, c2
925 // ...
926 // = op c3, ..., f2
927 Chain = Chains[NumRegs-1];
928 else
929 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
930}
931
932void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
933 unsigned MatchingIdx, const SDLoc &dl,
934 SelectionDAG &DAG,
935 std::vector<SDValue> &Ops) const {
936 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
937
938 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size());
939 if (HasMatching)
940 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx);
941 else if (!Regs.empty() &&
942 TargetRegisterInfo::isVirtualRegister(Regs.front())) {
943 // Put the register class of the virtual registers in the flag word. That
944 // way, later passes can recompute register class constraints for inline
945 // assembly as well as normal instructions.
946 // Don't do this for tied operands that can use the regclass information
947 // from the def.
948 const MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
949 const TargetRegisterClass *RC = MRI.getRegClass(Regs.front());
950 Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID());
951 }
952
953 SDValue Res = DAG.getTargetConstant(Flag, dl, MVT::i32);
954 Ops.push_back(Res);
955
956 if (Code == InlineAsm::Kind_Clobber) {
957 // Clobbers should always have a 1:1 mapping with registers, and may
958 // reference registers that have illegal (e.g. vector) types. Hence, we
959 // shouldn't try to apply any sort of splitting logic to them.
960 assert(Regs.size() == RegVTs.size() && Regs.size() == ValueVTs.size() &&((Regs.size() == RegVTs.size() && Regs.size() == ValueVTs
.size() && "No 1:1 mapping from clobbers to regs?") ?
static_cast<void> (0) : __assert_fail ("Regs.size() == RegVTs.size() && Regs.size() == ValueVTs.size() && \"No 1:1 mapping from clobbers to regs?\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 961, __PRETTY_FUNCTION__))
961 "No 1:1 mapping from clobbers to regs?")((Regs.size() == RegVTs.size() && Regs.size() == ValueVTs
.size() && "No 1:1 mapping from clobbers to regs?") ?
static_cast<void> (0) : __assert_fail ("Regs.size() == RegVTs.size() && Regs.size() == ValueVTs.size() && \"No 1:1 mapping from clobbers to regs?\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 961, __PRETTY_FUNCTION__))
;
962 unsigned SP = TLI.getStackPointerRegisterToSaveRestore();
963 (void)SP;
964 for (unsigned I = 0, E = ValueVTs.size(); I != E; ++I) {
965 Ops.push_back(DAG.getRegister(Regs[I], RegVTs[I]));
966 assert((((Regs[I] != SP || DAG.getMachineFunction().getFrameInfo().hasOpaqueSPAdjustment
()) && "If we clobbered the stack pointer, MFI should know about it."
) ? static_cast<void> (0) : __assert_fail ("(Regs[I] != SP || DAG.getMachineFunction().getFrameInfo().hasOpaqueSPAdjustment()) && \"If we clobbered the stack pointer, MFI should know about it.\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 969, __PRETTY_FUNCTION__))
967 (Regs[I] != SP ||(((Regs[I] != SP || DAG.getMachineFunction().getFrameInfo().hasOpaqueSPAdjustment
()) && "If we clobbered the stack pointer, MFI should know about it."
) ? static_cast<void> (0) : __assert_fail ("(Regs[I] != SP || DAG.getMachineFunction().getFrameInfo().hasOpaqueSPAdjustment()) && \"If we clobbered the stack pointer, MFI should know about it.\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 969, __PRETTY_FUNCTION__))
968 DAG.getMachineFunction().getFrameInfo().hasOpaqueSPAdjustment()) &&(((Regs[I] != SP || DAG.getMachineFunction().getFrameInfo().hasOpaqueSPAdjustment
()) && "If we clobbered the stack pointer, MFI should know about it."
) ? static_cast<void> (0) : __assert_fail ("(Regs[I] != SP || DAG.getMachineFunction().getFrameInfo().hasOpaqueSPAdjustment()) && \"If we clobbered the stack pointer, MFI should know about it.\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 969, __PRETTY_FUNCTION__))
969 "If we clobbered the stack pointer, MFI should know about it.")(((Regs[I] != SP || DAG.getMachineFunction().getFrameInfo().hasOpaqueSPAdjustment
()) && "If we clobbered the stack pointer, MFI should know about it."
) ? static_cast<void> (0) : __assert_fail ("(Regs[I] != SP || DAG.getMachineFunction().getFrameInfo().hasOpaqueSPAdjustment()) && \"If we clobbered the stack pointer, MFI should know about it.\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 969, __PRETTY_FUNCTION__))
;
970 }
971 return;
972 }
973
974 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
975 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
976 MVT RegisterVT = RegVTs[Value];
977 for (unsigned i = 0; i != NumRegs; ++i) {
978 assert(Reg < Regs.size() && "Mismatch in # registers expected")((Reg < Regs.size() && "Mismatch in # registers expected"
) ? static_cast<void> (0) : __assert_fail ("Reg < Regs.size() && \"Mismatch in # registers expected\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 978, __PRETTY_FUNCTION__))
;
979 unsigned TheReg = Regs[Reg++];
980 Ops.push_back(DAG.getRegister(TheReg, RegisterVT));
981 }
982 }
983}
984
985SmallVector<std::pair<unsigned, unsigned>, 4>
986RegsForValue::getRegsAndSizes() const {
987 SmallVector<std::pair<unsigned, unsigned>, 4> OutVec;
988 unsigned I = 0;
989 for (auto CountAndVT : zip_first(RegCount, RegVTs)) {
990 unsigned RegCount = std::get<0>(CountAndVT);
991 MVT RegisterVT = std::get<1>(CountAndVT);
992 unsigned RegisterSize = RegisterVT.getSizeInBits();
993 for (unsigned E = I + RegCount; I != E; ++I)
994 OutVec.push_back(std::make_pair(Regs[I], RegisterSize));
995 }
996 return OutVec;
997}
998
999void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis *aa,
1000 const TargetLibraryInfo *li) {
1001 AA = aa;
1002 GFI = gfi;
1003 LibInfo = li;
1004 DL = &DAG.getDataLayout();
1005 Context = DAG.getContext();
1006 LPadToCallSiteMap.clear();
1007}
1008
1009void SelectionDAGBuilder::clear() {
1010 NodeMap.clear();
1011 UnusedArgNodeMap.clear();
1012 PendingLoads.clear();
1013 PendingExports.clear();
1014 CurInst = nullptr;
1015 HasTailCall = false;
1016 SDNodeOrder = LowestSDNodeOrder;
1017 StatepointLowering.clear();
1018}
1019
1020void SelectionDAGBuilder::clearDanglingDebugInfo() {
1021 DanglingDebugInfoMap.clear();
1022}
1023
1024SDValue SelectionDAGBuilder::getRoot() {
1025 if (PendingLoads.empty())
1026 return DAG.getRoot();
1027
1028 if (PendingLoads.size() == 1) {
1029 SDValue Root = PendingLoads[0];
1030 DAG.setRoot(Root);
1031 PendingLoads.clear();
1032 return Root;
1033 }
1034
1035 // Otherwise, we have to make a token factor node.
1036 SDValue Root = DAG.getTokenFactor(getCurSDLoc(), PendingLoads);
1037 PendingLoads.clear();
1038 DAG.setRoot(Root);
1039 return Root;
1040}
1041
1042SDValue SelectionDAGBuilder::getControlRoot() {
1043 SDValue Root = DAG.getRoot();
1044
1045 if (PendingExports.empty())
1046 return Root;
1047
1048 // Turn all of the CopyToReg chains into one factored node.
1049 if (Root.getOpcode() != ISD::EntryToken) {
1050 unsigned i = 0, e = PendingExports.size();
1051 for (; i != e; ++i) {
1052 assert(PendingExports[i].getNode()->getNumOperands() > 1)((PendingExports[i].getNode()->getNumOperands() > 1) ? static_cast
<void> (0) : __assert_fail ("PendingExports[i].getNode()->getNumOperands() > 1"
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 1052, __PRETTY_FUNCTION__))
;
1053 if (PendingExports[i].getNode()->getOperand(0) == Root)
1054 break; // Don't add the root if we already indirectly depend on it.
1055 }
1056
1057 if (i == e)
1058 PendingExports.push_back(Root);
1059 }
1060
1061 Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
1062 PendingExports);
1063 PendingExports.clear();
1064 DAG.setRoot(Root);
1065 return Root;
1066}
1067
1068void SelectionDAGBuilder::visit(const Instruction &I) {
1069 // Set up outgoing PHI node register values before emitting the terminator.
1070 if (I.isTerminator()) {
1071 HandlePHINodesInSuccessorBlocks(I.getParent());
1072 }
1073
1074 // Increase the SDNodeOrder if dealing with a non-debug instruction.
1075 if (!isa<DbgInfoIntrinsic>(I))
1076 ++SDNodeOrder;
1077
1078 CurInst = &I;
1079
1080 visit(I.getOpcode(), I);
1081
1082 if (auto *FPMO = dyn_cast<FPMathOperator>(&I)) {
1083 // Propagate the fast-math-flags of this IR instruction to the DAG node that
1084 // maps to this instruction.
1085 // TODO: We could handle all flags (nsw, etc) here.
1086 // TODO: If an IR instruction maps to >1 node, only the final node will have
1087 // flags set.
1088 if (SDNode *Node = getNodeForIRValue(&I)) {
1089 SDNodeFlags IncomingFlags;
1090 IncomingFlags.copyFMF(*FPMO);
1091 if (!Node->getFlags().isDefined())
1092 Node->setFlags(IncomingFlags);
1093 else
1094 Node->intersectFlagsWith(IncomingFlags);
1095 }
1096 }
1097
1098 if (!I.isTerminator() && !HasTailCall &&
1099 !isStatepoint(&I)) // statepoints handle their exports internally
1100 CopyToExportRegsIfNeeded(&I);
1101
1102 CurInst = nullptr;
1103}
1104
1105void SelectionDAGBuilder::visitPHI(const PHINode &) {
1106 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!")::llvm::llvm_unreachable_internal("SelectionDAGBuilder shouldn't visit PHI nodes!"
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 1106)
;
1107}
1108
1109void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
1110 // Note: this doesn't use InstVisitor, because it has to work with
1111 // ConstantExpr's in addition to instructions.
1112 switch (Opcode) {
1113 default: llvm_unreachable("Unknown instruction type encountered!")::llvm::llvm_unreachable_internal("Unknown instruction type encountered!"
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 1113)
;
1114 // Build the switch statement using the Instruction.def file.
1115#define HANDLE_INST(NUM, OPCODE, CLASS) \
1116 case Instruction::OPCODE: visit##OPCODE((const CLASS&)I); break;
1117#include "llvm/IR/Instruction.def"
1118 }
1119}
1120
1121void SelectionDAGBuilder::dropDanglingDebugInfo(const DILocalVariable *Variable,
1122 const DIExpression *Expr) {
1123 auto isMatchingDbgValue = [&](DanglingDebugInfo &DDI) {
1124 const DbgValueInst *DI = DDI.getDI();
1125 DIVariable *DanglingVariable = DI->getVariable();
1126 DIExpression *DanglingExpr = DI->getExpression();
1127 if (DanglingVariable == Variable && Expr->fragmentsOverlap(DanglingExpr)) {
1128 LLVM_DEBUG(dbgs() << "Dropping dangling debug info for " << *DI << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << "Dropping dangling debug info for "
<< *DI << "\n"; } } while (false)
;
1129 return true;
1130 }
1131 return false;
1132 };
1133
1134 for (auto &DDIMI : DanglingDebugInfoMap) {
1135 DanglingDebugInfoVector &DDIV = DDIMI.second;
1136
1137 // If debug info is to be dropped, run it through final checks to see
1138 // whether it can be salvaged.
1139 for (auto &DDI : DDIV)
1140 if (isMatchingDbgValue(DDI))
1141 salvageUnresolvedDbgValue(DDI);
1142
1143 DDIV.erase(remove_if(DDIV, isMatchingDbgValue), DDIV.end());
1144 }
1145}
1146
1147// resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
1148// generate the debug data structures now that we've seen its definition.
1149void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V,
1150 SDValue Val) {
1151 auto DanglingDbgInfoIt = DanglingDebugInfoMap.find(V);
1152 if (DanglingDbgInfoIt == DanglingDebugInfoMap.end())
1153 return;
1154
1155 DanglingDebugInfoVector &DDIV = DanglingDbgInfoIt->second;
1156 for (auto &DDI : DDIV) {
1157 const DbgValueInst *DI = DDI.getDI();
1158 assert(DI && "Ill-formed DanglingDebugInfo")((DI && "Ill-formed DanglingDebugInfo") ? static_cast
<void> (0) : __assert_fail ("DI && \"Ill-formed DanglingDebugInfo\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 1158, __PRETTY_FUNCTION__))
;
1159 DebugLoc dl = DDI.getdl();
1160 unsigned ValSDNodeOrder = Val.getNode()->getIROrder();
1161 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder();
1162 DILocalVariable *Variable = DI->getVariable();
1163 DIExpression *Expr = DI->getExpression();
1164 assert(Variable->isValidLocationForIntrinsic(dl) &&((Variable->isValidLocationForIntrinsic(dl) && "Expected inlined-at fields to agree"
) ? static_cast<void> (0) : __assert_fail ("Variable->isValidLocationForIntrinsic(dl) && \"Expected inlined-at fields to agree\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 1165, __PRETTY_FUNCTION__))
1165 "Expected inlined-at fields to agree")((Variable->isValidLocationForIntrinsic(dl) && "Expected inlined-at fields to agree"
) ? static_cast<void> (0) : __assert_fail ("Variable->isValidLocationForIntrinsic(dl) && \"Expected inlined-at fields to agree\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 1165, __PRETTY_FUNCTION__))
;
1166 SDDbgValue *SDV;
1167 if (Val.getNode()) {
1168 // FIXME: I doubt that it is correct to resolve a dangling DbgValue as a
1169 // FuncArgumentDbgValue (it would be hoisted to the function entry, and if
1170 // we couldn't resolve it directly when examining the DbgValue intrinsic
1171 // in the first place we should not be more successful here). Unless we
1172 // have some test case that prove this to be correct we should avoid
1173 // calling EmitFuncArgumentDbgValue here.
1174 if (!EmitFuncArgumentDbgValue(V, Variable, Expr, dl, false, Val)) {
1175 LLVM_DEBUG(dbgs() << "Resolve dangling debug info [order="do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << "Resolve dangling debug info [order="
<< DbgSDNodeOrder << "] for:\n " << *DI <<
"\n"; } } while (false)
1176 << DbgSDNodeOrder << "] for:\n " << *DI << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << "Resolve dangling debug info [order="
<< DbgSDNodeOrder << "] for:\n " << *DI <<
"\n"; } } while (false)
;
1177 LLVM_DEBUG(dbgs() << " By mapping to:\n "; Val.dump())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << " By mapping to:\n "; Val.dump
(); } } while (false)
;
1178 // Increase the SDNodeOrder for the DbgValue here to make sure it is
1179 // inserted after the definition of Val when emitting the instructions
1180 // after ISel. An alternative could be to teach
1181 // ScheduleDAGSDNodes::EmitSchedule to delay the insertion properly.
1182 LLVM_DEBUG(if (ValSDNodeOrder > DbgSDNodeOrder) dbgs()do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { if (ValSDNodeOrder > DbgSDNodeOrder) dbgs() <<
"changing SDNodeOrder from " << DbgSDNodeOrder <<
" to " << ValSDNodeOrder << "\n"; } } while (false
)
1183 << "changing SDNodeOrder from " << DbgSDNodeOrder << " to "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { if (ValSDNodeOrder > DbgSDNodeOrder) dbgs() <<
"changing SDNodeOrder from " << DbgSDNodeOrder <<
" to " << ValSDNodeOrder << "\n"; } } while (false
)
1184 << ValSDNodeOrder << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { if (ValSDNodeOrder > DbgSDNodeOrder) dbgs() <<
"changing SDNodeOrder from " << DbgSDNodeOrder <<
" to " << ValSDNodeOrder << "\n"; } } while (false
)
;
1185 SDV = getDbgValue(Val, Variable, Expr, dl,
1186 std::max(DbgSDNodeOrder, ValSDNodeOrder));
1187 DAG.AddDbgValue(SDV, Val.getNode(), false);
1188 } else
1189 LLVM_DEBUG(dbgs() << "Resolved dangling debug info for " << *DIdo { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << "Resolved dangling debug info for "
<< *DI << "in EmitFuncArgumentDbgValue\n"; } } while
(false)
1190 << "in EmitFuncArgumentDbgValue\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << "Resolved dangling debug info for "
<< *DI << "in EmitFuncArgumentDbgValue\n"; } } while
(false)
;
1191 } else {
1192 LLVM_DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << "Dropping debug info for " <<
*DI << "\n"; } } while (false)
;
1193 auto Undef =
1194 UndefValue::get(DDI.getDI()->getVariableLocation()->getType());
1195 auto SDV =
1196 DAG.getConstantDbgValue(Variable, Expr, Undef, dl, DbgSDNodeOrder);
1197 DAG.AddDbgValue(SDV, nullptr, false);
1198 }
1199 }
1200 DDIV.clear();
1201}
1202
1203void SelectionDAGBuilder::salvageUnresolvedDbgValue(DanglingDebugInfo &DDI) {
1204 Value *V = DDI.getDI()->getValue();
1205 DILocalVariable *Var = DDI.getDI()->getVariable();
1206 DIExpression *Expr = DDI.getDI()->getExpression();
1207 DebugLoc DL = DDI.getdl();
1208 DebugLoc InstDL = DDI.getDI()->getDebugLoc();
1209 unsigned SDOrder = DDI.getSDNodeOrder();
1210
1211 // Currently we consider only dbg.value intrinsics -- we tell the salvager
1212 // that DW_OP_stack_value is desired.
1213 assert(isa<DbgValueInst>(DDI.getDI()))((isa<DbgValueInst>(DDI.getDI())) ? static_cast<void
> (0) : __assert_fail ("isa<DbgValueInst>(DDI.getDI())"
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 1213, __PRETTY_FUNCTION__))
;
1214 bool StackValue = true;
1215
1216 // Can this Value can be encoded without any further work?
1217 if (handleDebugValue(V, Var, Expr, DL, InstDL, SDOrder))
1218 return;
1219
1220 // Attempt to salvage back through as many instructions as possible. Bail if
1221 // a non-instruction is seen, such as a constant expression or global
1222 // variable. FIXME: Further work could recover those too.
1223 while (isa<Instruction>(V)) {
1224 Instruction &VAsInst = *cast<Instruction>(V);
1225 DIExpression *NewExpr = salvageDebugInfoImpl(VAsInst, Expr, StackValue);
1226
1227 // If we cannot salvage any further, and haven't yet found a suitable debug
1228 // expression, bail out.
1229 if (!NewExpr)
1230 break;
1231
1232 // New value and expr now represent this debuginfo.
1233 V = VAsInst.getOperand(0);
1234 Expr = NewExpr;
1235
1236 // Some kind of simplification occurred: check whether the operand of the
1237 // salvaged debug expression can be encoded in this DAG.
1238 if (handleDebugValue(V, Var, Expr, DL, InstDL, SDOrder)) {
1239 LLVM_DEBUG(dbgs() << "Salvaged debug location info for:\n "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << "Salvaged debug location info for:\n "
<< DDI.getDI() << "\nBy stripping back to:\n " <<
V; } } while (false)
1240 << DDI.getDI() << "\nBy stripping back to:\n " << V)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << "Salvaged debug location info for:\n "
<< DDI.getDI() << "\nBy stripping back to:\n " <<
V; } } while (false)
;
1241 return;
1242 }
1243 }
1244
1245 // This was the final opportunity to salvage this debug information, and it
1246 // couldn't be done. Place an undef DBG_VALUE at this location to terminate
1247 // any earlier variable location.
1248 auto Undef = UndefValue::get(DDI.getDI()->getVariableLocation()->getType());
1249 auto SDV = DAG.getConstantDbgValue(Var, Expr, Undef, DL, SDNodeOrder);
1250 DAG.AddDbgValue(SDV, nullptr, false);
1251
1252 LLVM_DEBUG(dbgs() << "Dropping debug value info for:\n " << DDI.getDI()do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << "Dropping debug value info for:\n "
<< DDI.getDI() << "\n"; } } while (false)
1253 << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << "Dropping debug value info for:\n "
<< DDI.getDI() << "\n"; } } while (false)
;
1254 LLVM_DEBUG(dbgs() << " Last seen at:\n " << *DDI.getDI()->getOperand(0)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << " Last seen at:\n " << *
DDI.getDI()->getOperand(0) << "\n"; } } while (false
)
1255 << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << " Last seen at:\n " << *
DDI.getDI()->getOperand(0) << "\n"; } } while (false
)
;
1256}
1257
1258bool SelectionDAGBuilder::handleDebugValue(const Value *V, DILocalVariable *Var,
1259 DIExpression *Expr, DebugLoc dl,
1260 DebugLoc InstDL, unsigned Order) {
1261 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1262 SDDbgValue *SDV;
1263 if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V) ||
1264 isa<ConstantPointerNull>(V)) {
1265 SDV = DAG.getConstantDbgValue(Var, Expr, V, dl, SDNodeOrder);
1266 DAG.AddDbgValue(SDV, nullptr, false);
1267 return true;
1268 }
1269
1270 // If the Value is a frame index, we can create a FrameIndex debug value
1271 // without relying on the DAG at all.
1272 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1273 auto SI = FuncInfo.StaticAllocaMap.find(AI);
1274 if (SI != FuncInfo.StaticAllocaMap.end()) {
1275 auto SDV =
1276 DAG.getFrameIndexDbgValue(Var, Expr, SI->second,
1277 /*IsIndirect*/ false, dl, SDNodeOrder);
1278 // Do not attach the SDNodeDbgValue to an SDNode: this variable location
1279 // is still available even if the SDNode gets optimized out.
1280 DAG.AddDbgValue(SDV, nullptr, false);
1281 return true;
1282 }
1283 }
1284
1285 // Do not use getValue() in here; we don't want to generate code at
1286 // this point if it hasn't been done yet.
1287 SDValue N = NodeMap[V];
1288 if (!N.getNode() && isa<Argument>(V)) // Check unused arguments map.
1289 N = UnusedArgNodeMap[V];
1290 if (N.getNode()) {
1291 if (EmitFuncArgumentDbgValue(V, Var, Expr, dl, false, N))
1292 return true;
1293 SDV = getDbgValue(N, Var, Expr, dl, SDNodeOrder);
1294 DAG.AddDbgValue(SDV, N.getNode(), false);
1295 return true;
1296 }
1297
1298 // Special rules apply for the first dbg.values of parameter variables in a
1299 // function. Identify them by the fact they reference Argument Values, that
1300 // they're parameters, and they are parameters of the current function. We
1301 // need to let them dangle until they get an SDNode.
1302 bool IsParamOfFunc = isa<Argument>(V) && Var->isParameter() &&
1303 !InstDL.getInlinedAt();
1304 if (!IsParamOfFunc) {
1305 // The value is not used in this block yet (or it would have an SDNode).
1306 // We still want the value to appear for the user if possible -- if it has
1307 // an associated VReg, we can refer to that instead.
1308 auto VMI = FuncInfo.ValueMap.find(V);
1309 if (VMI != FuncInfo.ValueMap.end()) {
1310 unsigned Reg = VMI->second;
1311 // If this is a PHI node, it may be split up into several MI PHI nodes
1312 // (in FunctionLoweringInfo::set).
1313 RegsForValue RFV(V->getContext(), TLI, DAG.getDataLayout(), Reg,
1314 V->getType(), None);
1315 if (RFV.occupiesMultipleRegs()) {
1316 unsigned Offset = 0;
1317 unsigned BitsToDescribe = 0;
1318 if (auto VarSize = Var->getSizeInBits())
1319 BitsToDescribe = *VarSize;
1320 if (auto Fragment = Expr->getFragmentInfo())
1321 BitsToDescribe = Fragment->SizeInBits;
1322 for (auto RegAndSize : RFV.getRegsAndSizes()) {
1323 unsigned RegisterSize = RegAndSize.second;
1324 // Bail out if all bits are described already.
1325 if (Offset >= BitsToDescribe)
1326 break;
1327 unsigned FragmentSize = (Offset + RegisterSize > BitsToDescribe)
1328 ? BitsToDescribe - Offset
1329 : RegisterSize;
1330 auto FragmentExpr = DIExpression::createFragmentExpression(
1331 Expr, Offset, FragmentSize);
1332 if (!FragmentExpr)
1333 continue;
1334 SDV = DAG.getVRegDbgValue(Var, *FragmentExpr, RegAndSize.first,
1335 false, dl, SDNodeOrder);
1336 DAG.AddDbgValue(SDV, nullptr, false);
1337 Offset += RegisterSize;
1338 }
1339 } else {
1340 SDV = DAG.getVRegDbgValue(Var, Expr, Reg, false, dl, SDNodeOrder);
1341 DAG.AddDbgValue(SDV, nullptr, false);
1342 }
1343 return true;
1344 }
1345 }
1346
1347 return false;
1348}
1349
1350void SelectionDAGBuilder::resolveOrClearDbgInfo() {
1351 // Try to fixup any remaining dangling debug info -- and drop it if we can't.
1352 for (auto &Pair : DanglingDebugInfoMap)
1353 for (auto &DDI : Pair.second)
1354 salvageUnresolvedDbgValue(DDI);
1355 clearDanglingDebugInfo();
1356}
1357
1358/// getCopyFromRegs - If there was virtual register allocated for the value V
1359/// emit CopyFromReg of the specified type Ty. Return empty SDValue() otherwise.
1360SDValue SelectionDAGBuilder::getCopyFromRegs(const Value *V, Type *Ty) {
1361 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V);
1362 SDValue Result;
1363
1364 if (It != FuncInfo.ValueMap.end()) {
1365 unsigned InReg = It->second;
1366
1367 RegsForValue RFV(*DAG.getContext(), DAG.getTargetLoweringInfo(),
1368 DAG.getDataLayout(), InReg, Ty,
1369 None); // This is not an ABI copy.
1370 SDValue Chain = DAG.getEntryNode();
1371 Result = RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr,
1372 V);
1373 resolveDanglingDebugInfo(V, Result);
1374 }
1375
1376 return Result;
1377}
1378
1379/// getValue - Return an SDValue for the given Value.
1380SDValue SelectionDAGBuilder::getValue(const Value *V) {
1381 // If we already have an SDValue for this value, use it. It's important
1382 // to do this first, so that we don't create a CopyFromReg if we already
1383 // have a regular SDValue.
1384 SDValue &N = NodeMap[V];
1385 if (N.getNode()) return N;
1386
1387 // If there's a virtual register allocated and initialized for this
1388 // value, use it.
1389 if (SDValue copyFromReg = getCopyFromRegs(V, V->getType()))
1390 return copyFromReg;
1391
1392 // Otherwise create a new SDValue and remember it.
1393 SDValue Val = getValueImpl(V);
1394 NodeMap[V] = Val;
1395 resolveDanglingDebugInfo(V, Val);
1396 return Val;
1397}
1398
1399// Return true if SDValue exists for the given Value
1400bool SelectionDAGBuilder::findValue(const Value *V) const {
1401 return (NodeMap.find(V) != NodeMap.end()) ||
1402 (FuncInfo.ValueMap.find(V) != FuncInfo.ValueMap.end());
1403}
1404
1405/// getNonRegisterValue - Return an SDValue for the given Value, but
1406/// don't look in FuncInfo.ValueMap for a virtual register.
1407SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) {
1408 // If we already have an SDValue for this value, use it.
1409 SDValue &N = NodeMap[V];
1410 if (N.getNode()) {
1411 if (isa<ConstantSDNode>(N) || isa<ConstantFPSDNode>(N)) {
1412 // Remove the debug location from the node as the node is about to be used
1413 // in a location which may differ from the original debug location. This
1414 // is relevant to Constant and ConstantFP nodes because they can appear
1415 // as constant expressions inside PHI nodes.
1416 N->setDebugLoc(DebugLoc());
1417 }
1418 return N;
1419 }
1420
1421 // Otherwise create a new SDValue and remember it.
1422 SDValue Val = getValueImpl(V);
1423 NodeMap[V] = Val;
1424 resolveDanglingDebugInfo(V, Val);
1425 return Val;
1426}
1427
1428/// getValueImpl - Helper function for getValue and getNonRegisterValue.
1429/// Create an SDValue for the given value.
1430SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
1431 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1432
1433 if (const Constant *C = dyn_cast<Constant>(V)) {
1434 EVT VT = TLI.getValueType(DAG.getDataLayout(), V->getType(), true);
1435
1436 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
1437 return DAG.getConstant(*CI, getCurSDLoc(), VT);
1438
1439 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
1440 return DAG.getGlobalAddress(GV, getCurSDLoc(), VT);
1441
1442 if (isa<ConstantPointerNull>(C)) {
1443 unsigned AS = V->getType()->getPointerAddressSpace();
1444 return DAG.getConstant(0, getCurSDLoc(),
1445 TLI.getPointerTy(DAG.getDataLayout(), AS));
1446 }
1447
1448 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
1449 return DAG.getConstantFP(*CFP, getCurSDLoc(), VT);
1450
1451 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
1452 return DAG.getUNDEF(VT);
1453
1454 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
1455 visit(CE->getOpcode(), *CE);
1456 SDValue N1 = NodeMap[V];
1457 assert(N1.getNode() && "visit didn't populate the NodeMap!")((N1.getNode() && "visit didn't populate the NodeMap!"
) ? static_cast<void> (0) : __assert_fail ("N1.getNode() && \"visit didn't populate the NodeMap!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 1457, __PRETTY_FUNCTION__))
;
1458 return N1;
1459 }
1460
1461 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
1462 SmallVector<SDValue, 4> Constants;
1463 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
1464 OI != OE; ++OI) {
1465 SDNode *Val = getValue(*OI).getNode();
1466 // If the operand is an empty aggregate, there are no values.
1467 if (!Val) continue;
1468 // Add each leaf value from the operand to the Constants list
1469 // to form a flattened list of all the values.
1470 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1471 Constants.push_back(SDValue(Val, i));
1472 }
1473
1474 return DAG.getMergeValues(Constants, getCurSDLoc());
1475 }
1476
1477 if (const ConstantDataSequential *CDS =
1478 dyn_cast<ConstantDataSequential>(C)) {
1479 SmallVector<SDValue, 4> Ops;
1480 for (unsigned i = 0, e = CDS->getNumElements(); i != e; ++i) {
1481 SDNode *Val = getValue(CDS->getElementAsConstant(i)).getNode();
1482 // Add each leaf value from the operand to the Constants list
1483 // to form a flattened list of all the values.
1484 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1485 Ops.push_back(SDValue(Val, i));
1486 }
1487
1488 if (isa<ArrayType>(CDS->getType()))
1489 return DAG.getMergeValues(Ops, getCurSDLoc());
1490 return NodeMap[V] = DAG.getBuildVector(VT, getCurSDLoc(), Ops);
1491 }
1492
1493 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
1494 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&(((isa<ConstantAggregateZero>(C) || isa<UndefValue>
(C)) && "Unknown struct or array constant!") ? static_cast
<void> (0) : __assert_fail ("(isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) && \"Unknown struct or array constant!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 1495, __PRETTY_FUNCTION__))
1495 "Unknown struct or array constant!")(((isa<ConstantAggregateZero>(C) || isa<UndefValue>
(C)) && "Unknown struct or array constant!") ? static_cast
<void> (0) : __assert_fail ("(isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) && \"Unknown struct or array constant!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 1495, __PRETTY_FUNCTION__))
;
1496
1497 SmallVector<EVT, 4> ValueVTs;
1498 ComputeValueVTs(TLI, DAG.getDataLayout(), C->getType(), ValueVTs);
1499 unsigned NumElts = ValueVTs.size();
1500 if (NumElts == 0)
1501 return SDValue(); // empty struct
1502 SmallVector<SDValue, 4> Constants(NumElts);
1503 for (unsigned i = 0; i != NumElts; ++i) {
1504 EVT EltVT = ValueVTs[i];
1505 if (isa<UndefValue>(C))
1506 Constants[i] = DAG.getUNDEF(EltVT);
1507 else if (EltVT.isFloatingPoint())
1508 Constants[i] = DAG.getConstantFP(0, getCurSDLoc(), EltVT);
1509 else
1510 Constants[i] = DAG.getConstant(0, getCurSDLoc(), EltVT);
1511 }
1512
1513 return DAG.getMergeValues(Constants, getCurSDLoc());
1514 }
1515
1516 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C))
1517 return DAG.getBlockAddress(BA, VT);
1518
1519 VectorType *VecTy = cast<VectorType>(V->getType());
1520 unsigned NumElements = VecTy->getNumElements();
1521
1522 // Now that we know the number and type of the elements, get that number of
1523 // elements into the Ops array based on what kind of constant it is.
1524 SmallVector<SDValue, 16> Ops;
1525 if (const ConstantVector *CV = dyn_cast<ConstantVector>(C)) {
1526 for (unsigned i = 0; i != NumElements; ++i)
1527 Ops.push_back(getValue(CV->getOperand(i)));
1528 } else {
1529 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!")((isa<ConstantAggregateZero>(C) && "Unknown vector constant!"
) ? static_cast<void> (0) : __assert_fail ("isa<ConstantAggregateZero>(C) && \"Unknown vector constant!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 1529, __PRETTY_FUNCTION__))
;
1530 EVT EltVT =
1531 TLI.getValueType(DAG.getDataLayout(), VecTy->getElementType());
1532
1533 SDValue Op;
1534 if (EltVT.isFloatingPoint())
1535 Op = DAG.getConstantFP(0, getCurSDLoc(), EltVT);
1536 else
1537 Op = DAG.getConstant(0, getCurSDLoc(), EltVT);
1538 Ops.assign(NumElements, Op);
1539 }
1540
1541 // Create a BUILD_VECTOR node.
1542 return NodeMap[V] = DAG.getBuildVector(VT, getCurSDLoc(), Ops);
1543 }
1544
1545 // If this is a static alloca, generate it as the frameindex instead of
1546 // computation.
1547 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1548 DenseMap<const AllocaInst*, int>::iterator SI =
1549 FuncInfo.StaticAllocaMap.find(AI);
1550 if (SI != FuncInfo.StaticAllocaMap.end())
1551 return DAG.getFrameIndex(SI->second,
1552 TLI.getFrameIndexTy(DAG.getDataLayout()));
1553 }
1554
1555 // If this is an instruction which fast-isel has deferred, select it now.
1556 if (const Instruction *Inst = dyn_cast<Instruction>(V)) {
1557 unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
1558
1559 RegsForValue RFV(*DAG.getContext(), TLI, DAG.getDataLayout(), InReg,
1560 Inst->getType(), getABIRegCopyCC(V));
1561 SDValue Chain = DAG.getEntryNode();
1562 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
1563 }
1564
1565 llvm_unreachable("Can't get register for value!")::llvm::llvm_unreachable_internal("Can't get register for value!"
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 1565)
;
1566}
1567
1568void SelectionDAGBuilder::visitCatchPad(const CatchPadInst &I) {
1569 auto Pers = classifyEHPersonality(FuncInfo.Fn->getPersonalityFn());
1570 bool IsMSVCCXX = Pers == EHPersonality::MSVC_CXX;
1571 bool IsCoreCLR = Pers == EHPersonality::CoreCLR;
1572 bool IsSEH = isAsynchronousEHPersonality(Pers);
1573 bool IsWasmCXX = Pers == EHPersonality::Wasm_CXX;
1574 MachineBasicBlock *CatchPadMBB = FuncInfo.MBB;
1575 if (!IsSEH)
1576 CatchPadMBB->setIsEHScopeEntry();
1577 // In MSVC C++ and CoreCLR, catchblocks are funclets and need prologues.
1578 if (IsMSVCCXX || IsCoreCLR)
1579 CatchPadMBB->setIsEHFuncletEntry();
1580 // Wasm does not need catchpads anymore
1581 if (!IsWasmCXX)
1582 DAG.setRoot(DAG.getNode(ISD::CATCHPAD, getCurSDLoc(), MVT::Other,
1583 getControlRoot()));
1584}
1585
1586void SelectionDAGBuilder::visitCatchRet(const CatchReturnInst &I) {
1587 // Update machine-CFG edge.
1588 MachineBasicBlock *TargetMBB = FuncInfo.MBBMap[I.getSuccessor()];
1589 FuncInfo.MBB->addSuccessor(TargetMBB);
1590
1591 auto Pers = classifyEHPersonality(FuncInfo.Fn->getPersonalityFn());
1592 bool IsSEH = isAsynchronousEHPersonality(Pers);
1593 if (IsSEH) {
1594 // If this is not a fall-through branch or optimizations are switched off,
1595 // emit the branch.
1596 if (TargetMBB != NextBlock(FuncInfo.MBB) ||
1597 TM.getOptLevel() == CodeGenOpt::None)
1598 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other,
1599 getControlRoot(), DAG.getBasicBlock(TargetMBB)));
1600 return;
1601 }
1602
1603 // Figure out the funclet membership for the catchret's successor.
1604 // This will be used by the FuncletLayout pass to determine how to order the
1605 // BB's.
1606 // A 'catchret' returns to the outer scope's color.
1607 Value *ParentPad = I.getCatchSwitchParentPad();
1608 const BasicBlock *SuccessorColor;
1609 if (isa<ConstantTokenNone>(ParentPad))
1610 SuccessorColor = &FuncInfo.Fn->getEntryBlock();
1611 else
1612 SuccessorColor = cast<Instruction>(ParentPad)->getParent();
1613 assert(SuccessorColor && "No parent funclet for catchret!")((SuccessorColor && "No parent funclet for catchret!"
) ? static_cast<void> (0) : __assert_fail ("SuccessorColor && \"No parent funclet for catchret!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 1613, __PRETTY_FUNCTION__))
;
1614 MachineBasicBlock *SuccessorColorMBB = FuncInfo.MBBMap[SuccessorColor];
1615 assert(SuccessorColorMBB && "No MBB for SuccessorColor!")((SuccessorColorMBB && "No MBB for SuccessorColor!") ?
static_cast<void> (0) : __assert_fail ("SuccessorColorMBB && \"No MBB for SuccessorColor!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 1615, __PRETTY_FUNCTION__))
;
1616
1617 // Create the terminator node.
1618 SDValue Ret = DAG.getNode(ISD::CATCHRET, getCurSDLoc(), MVT::Other,
1619 getControlRoot(), DAG.getBasicBlock(TargetMBB),
1620 DAG.getBasicBlock(SuccessorColorMBB));
1621 DAG.setRoot(Ret);
1622}
1623
1624void SelectionDAGBuilder::visitCleanupPad(const CleanupPadInst &CPI) {
1625 // Don't emit any special code for the cleanuppad instruction. It just marks
1626 // the start of an EH scope/funclet.
1627 FuncInfo.MBB->setIsEHScopeEntry();
1628 auto Pers = classifyEHPersonality(FuncInfo.Fn->getPersonalityFn());
1629 if (Pers != EHPersonality::Wasm_CXX) {
1630 FuncInfo.MBB->setIsEHFuncletEntry();
1631 FuncInfo.MBB->setIsCleanupFuncletEntry();
1632 }
1633}
1634
1635// For wasm, there's alwyas a single catch pad attached to a catchswitch, and
1636// the control flow always stops at the single catch pad, as it does for a
1637// cleanup pad. In case the exception caught is not of the types the catch pad
1638// catches, it will be rethrown by a rethrow.
1639static void findWasmUnwindDestinations(
1640 FunctionLoweringInfo &FuncInfo, const BasicBlock *EHPadBB,
1641 BranchProbability Prob,
1642 SmallVectorImpl<std::pair<MachineBasicBlock *, BranchProbability>>
1643 &UnwindDests) {
1644 while (EHPadBB) {
1645 const Instruction *Pad = EHPadBB->getFirstNonPHI();
1646 if (isa<CleanupPadInst>(Pad)) {
1647 // Stop on cleanup pads.
1648 UnwindDests.emplace_back(FuncInfo.MBBMap[EHPadBB], Prob);
1649 UnwindDests.back().first->setIsEHScopeEntry();
1650 break;
1651 } else if (auto *CatchSwitch = dyn_cast<CatchSwitchInst>(Pad)) {
1652 // Add the catchpad handlers to the possible destinations. We don't
1653 // continue to the unwind destination of the catchswitch for wasm.
1654 for (const BasicBlock *CatchPadBB : CatchSwitch->handlers()) {
1655 UnwindDests.emplace_back(FuncInfo.MBBMap[CatchPadBB], Prob);
1656 UnwindDests.back().first->setIsEHScopeEntry();
1657 }
1658 break;
1659 } else {
1660 continue;
1661 }
1662 }
1663}
1664
1665/// When an invoke or a cleanupret unwinds to the next EH pad, there are
1666/// many places it could ultimately go. In the IR, we have a single unwind
1667/// destination, but in the machine CFG, we enumerate all the possible blocks.
1668/// This function skips over imaginary basic blocks that hold catchswitch
1669/// instructions, and finds all the "real" machine
1670/// basic block destinations. As those destinations may not be successors of
1671/// EHPadBB, here we also calculate the edge probability to those destinations.
1672/// The passed-in Prob is the edge probability to EHPadBB.
1673static void findUnwindDestinations(
1674 FunctionLoweringInfo &FuncInfo, const BasicBlock *EHPadBB,
1675 BranchProbability Prob,
1676 SmallVectorImpl<std::pair<MachineBasicBlock *, BranchProbability>>
1677 &UnwindDests) {
1678 EHPersonality Personality =
1679 classifyEHPersonality(FuncInfo.Fn->getPersonalityFn());
1680 bool IsMSVCCXX = Personality == EHPersonality::MSVC_CXX;
1681 bool IsCoreCLR = Personality == EHPersonality::CoreCLR;
1682 bool IsWasmCXX = Personality == EHPersonality::Wasm_CXX;
1683 bool IsSEH = isAsynchronousEHPersonality(Personality);
1684
1685 if (IsWasmCXX) {
1686 findWasmUnwindDestinations(FuncInfo, EHPadBB, Prob, UnwindDests);
1687 assert(UnwindDests.size() <= 1 &&((UnwindDests.size() <= 1 && "There should be at most one unwind destination for wasm"
) ? static_cast<void> (0) : __assert_fail ("UnwindDests.size() <= 1 && \"There should be at most one unwind destination for wasm\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 1688, __PRETTY_FUNCTION__))
1688 "There should be at most one unwind destination for wasm")((UnwindDests.size() <= 1 && "There should be at most one unwind destination for wasm"
) ? static_cast<void> (0) : __assert_fail ("UnwindDests.size() <= 1 && \"There should be at most one unwind destination for wasm\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 1688, __PRETTY_FUNCTION__))
;
1689 return;
1690 }
1691
1692 while (EHPadBB) {
1693 const Instruction *Pad = EHPadBB->getFirstNonPHI();
1694 BasicBlock *NewEHPadBB = nullptr;
1695 if (isa<LandingPadInst>(Pad)) {
1696 // Stop on landingpads. They are not funclets.
1697 UnwindDests.emplace_back(FuncInfo.MBBMap[EHPadBB], Prob);
1698 break;
1699 } else if (isa<CleanupPadInst>(Pad)) {
1700 // Stop on cleanup pads. Cleanups are always funclet entries for all known
1701 // personalities.
1702 UnwindDests.emplace_back(FuncInfo.MBBMap[EHPadBB], Prob);
1703 UnwindDests.back().first->setIsEHScopeEntry();
1704 UnwindDests.back().first->setIsEHFuncletEntry();
1705 break;
1706 } else if (auto *CatchSwitch = dyn_cast<CatchSwitchInst>(Pad)) {
1707 // Add the catchpad handlers to the possible destinations.
1708 for (const BasicBlock *CatchPadBB : CatchSwitch->handlers()) {
1709 UnwindDests.emplace_back(FuncInfo.MBBMap[CatchPadBB], Prob);
1710 // For MSVC++ and the CLR, catchblocks are funclets and need prologues.
1711 if (IsMSVCCXX || IsCoreCLR)
1712 UnwindDests.back().first->setIsEHFuncletEntry();
1713 if (!IsSEH)
1714 UnwindDests.back().first->setIsEHScopeEntry();
1715 }
1716 NewEHPadBB = CatchSwitch->getUnwindDest();
1717 } else {
1718 continue;
1719 }
1720
1721 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1722 if (BPI && NewEHPadBB)
1723 Prob *= BPI->getEdgeProbability(EHPadBB, NewEHPadBB);
1724 EHPadBB = NewEHPadBB;
1725 }
1726}
1727
1728void SelectionDAGBuilder::visitCleanupRet(const CleanupReturnInst &I) {
1729 // Update successor info.
1730 SmallVector<std::pair<MachineBasicBlock *, BranchProbability>, 1> UnwindDests;
1731 auto UnwindDest = I.getUnwindDest();
1732 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1733 BranchProbability UnwindDestProb =
1734 (BPI && UnwindDest)
1735 ? BPI->getEdgeProbability(FuncInfo.MBB->getBasicBlock(), UnwindDest)
1736 : BranchProbability::getZero();
1737 findUnwindDestinations(FuncInfo, UnwindDest, UnwindDestProb, UnwindDests);
1738 for (auto &UnwindDest : UnwindDests) {
1739 UnwindDest.first->setIsEHPad();
1740 addSuccessorWithProb(FuncInfo.MBB, UnwindDest.first, UnwindDest.second);
1741 }
1742 FuncInfo.MBB->normalizeSuccProbs();
1743
1744 // Create the terminator node.
1745 SDValue Ret =
1746 DAG.getNode(ISD::CLEANUPRET, getCurSDLoc(), MVT::Other, getControlRoot());
1747 DAG.setRoot(Ret);
1748}
1749
1750void SelectionDAGBuilder::visitCatchSwitch(const CatchSwitchInst &CSI) {
1751 report_fatal_error("visitCatchSwitch not yet implemented!");
1752}
1753
1754void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
1755 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1756 auto &DL = DAG.getDataLayout();
1757 SDValue Chain = getControlRoot();
1758 SmallVector<ISD::OutputArg, 8> Outs;
1759 SmallVector<SDValue, 8> OutVals;
1760
1761 // Calls to @llvm.experimental.deoptimize don't generate a return value, so
1762 // lower
1763 //
1764 // %val = call <ty> @llvm.experimental.deoptimize()
1765 // ret <ty> %val
1766 //
1767 // differently.
1768 if (I.getParent()->getTerminatingDeoptimizeCall()) {
1769 LowerDeoptimizingReturn();
1770 return;
1771 }
1772
1773 if (!FuncInfo.CanLowerReturn) {
1774 unsigned DemoteReg = FuncInfo.DemoteRegister;
1775 const Function *F = I.getParent()->getParent();
1776
1777 // Emit a store of the return value through the virtual register.
1778 // Leave Outs empty so that LowerReturn won't try to load return
1779 // registers the usual way.
1780 SmallVector<EVT, 1> PtrValueVTs;
1781 ComputeValueVTs(TLI, DL,
1782 F->getReturnType()->getPointerTo(
1783 DAG.getDataLayout().getAllocaAddrSpace()),
1784 PtrValueVTs);
1785
1786 SDValue RetPtr = DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(),
1787 DemoteReg, PtrValueVTs[0]);
1788 SDValue RetOp = getValue(I.getOperand(0));
1789
1790 SmallVector<EVT, 4> ValueVTs, MemVTs;
1791 SmallVector<uint64_t, 4> Offsets;
1792 ComputeValueVTs(TLI, DL, I.getOperand(0)->getType(), ValueVTs, &MemVTs,
1793 &Offsets);
1794 unsigned NumValues = ValueVTs.size();
1795
1796 SmallVector<SDValue, 4> Chains(NumValues);
1797 for (unsigned i = 0; i != NumValues; ++i) {
1798 // An aggregate return value cannot wrap around the address space, so
1799 // offsets to its parts don't wrap either.
1800 SDValue Ptr = DAG.getObjectPtrOffset(getCurSDLoc(), RetPtr, Offsets[i]);
1801
1802 SDValue Val = RetOp.getValue(i);
1803 if (MemVTs[i] != ValueVTs[i])
1804 Val = DAG.getPtrExtOrTrunc(Val, getCurSDLoc(), MemVTs[i]);
1805 Chains[i] = DAG.getStore(Chain, getCurSDLoc(), Val,
1806 // FIXME: better loc info would be nice.
1807 Ptr, MachinePointerInfo::getUnknownStack(DAG.getMachineFunction()));
1808 }
1809
1810 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
1811 MVT::Other, Chains);
1812 } else if (I.getNumOperands() != 0) {
1813 SmallVector<EVT, 4> ValueVTs;
1814 ComputeValueVTs(TLI, DL, I.getOperand(0)->getType(), ValueVTs);
1815 unsigned NumValues = ValueVTs.size();
1816 if (NumValues) {
1817 SDValue RetOp = getValue(I.getOperand(0));
1818
1819 const Function *F = I.getParent()->getParent();
1820
1821 bool NeedsRegBlock = TLI.functionArgumentNeedsConsecutiveRegisters(
1822 I.getOperand(0)->getType(), F->getCallingConv(),
1823 /*IsVarArg*/ false);
1824
1825 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1826 if (F->getAttributes().hasAttribute(AttributeList::ReturnIndex,
1827 Attribute::SExt))
1828 ExtendKind = ISD::SIGN_EXTEND;
1829 else if (F->getAttributes().hasAttribute(AttributeList::ReturnIndex,
1830 Attribute::ZExt))
1831 ExtendKind = ISD::ZERO_EXTEND;
1832
1833 LLVMContext &Context = F->getContext();
1834 bool RetInReg = F->getAttributes().hasAttribute(
1835 AttributeList::ReturnIndex, Attribute::InReg);
1836
1837 for (unsigned j = 0; j != NumValues; ++j) {
1838 EVT VT = ValueVTs[j];
1839
1840 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger())
1841 VT = TLI.getTypeForExtReturn(Context, VT, ExtendKind);
1842
1843 CallingConv::ID CC = F->getCallingConv();
1844
1845 unsigned NumParts = TLI.getNumRegistersForCallingConv(Context, CC, VT);
1846 MVT PartVT = TLI.getRegisterTypeForCallingConv(Context, CC, VT);
1847 SmallVector<SDValue, 4> Parts(NumParts);
1848 getCopyToParts(DAG, getCurSDLoc(),
1849 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
1850 &Parts[0], NumParts, PartVT, &I, CC, ExtendKind);
1851
1852 // 'inreg' on function refers to return value
1853 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1854 if (RetInReg)
1855 Flags.setInReg();
1856
1857 if (I.getOperand(0)->getType()->isPointerTy()) {
1858 Flags.setPointer();
1859 Flags.setPointerAddrSpace(
1860 cast<PointerType>(I.getOperand(0)->getType())->getAddressSpace());
1861 }
1862
1863 if (NeedsRegBlock) {
1864 Flags.setInConsecutiveRegs();
1865 if (j == NumValues - 1)
1866 Flags.setInConsecutiveRegsLast();
1867 }
1868
1869 // Propagate extension type if any
1870 if (ExtendKind == ISD::SIGN_EXTEND)
1871 Flags.setSExt();
1872 else if (ExtendKind == ISD::ZERO_EXTEND)
1873 Flags.setZExt();
1874
1875 for (unsigned i = 0; i < NumParts; ++i) {
1876 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(),
1877 VT, /*isfixed=*/true, 0, 0));
1878 OutVals.push_back(Parts[i]);
1879 }
1880 }
1881 }
1882 }
1883
1884 // Push in swifterror virtual register as the last element of Outs. This makes
1885 // sure swifterror virtual register will be returned in the swifterror
1886 // physical register.
1887 const Function *F = I.getParent()->getParent();
1888 if (TLI.supportSwiftError() &&
1889 F->getAttributes().hasAttrSomewhere(Attribute::SwiftError)) {
1890 assert(FuncInfo.SwiftErrorArg && "Need a swift error argument")((FuncInfo.SwiftErrorArg && "Need a swift error argument"
) ? static_cast<void> (0) : __assert_fail ("FuncInfo.SwiftErrorArg && \"Need a swift error argument\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 1890, __PRETTY_FUNCTION__))
;
1891 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1892 Flags.setSwiftError();
1893 Outs.push_back(ISD::OutputArg(Flags, EVT(TLI.getPointerTy(DL)) /*vt*/,
1894 EVT(TLI.getPointerTy(DL)) /*argvt*/,
1895 true /*isfixed*/, 1 /*origidx*/,
1896 0 /*partOffs*/));
1897 // Create SDNode for the swifterror virtual register.
1898 OutVals.push_back(
1899 DAG.getRegister(FuncInfo.getOrCreateSwiftErrorVRegUseAt(
1900 &I, FuncInfo.MBB, FuncInfo.SwiftErrorArg).first,
1901 EVT(TLI.getPointerTy(DL))));
1902 }
1903
1904 bool isVarArg = DAG.getMachineFunction().getFunction().isVarArg();
1905 CallingConv::ID CallConv =
1906 DAG.getMachineFunction().getFunction().getCallingConv();
1907 Chain = DAG.getTargetLoweringInfo().LowerReturn(
1908 Chain, CallConv, isVarArg, Outs, OutVals, getCurSDLoc(), DAG);
1909
1910 // Verify that the target's LowerReturn behaved as expected.
1911 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&((Chain.getNode() && Chain.getValueType() == MVT::Other
&& "LowerReturn didn't return a valid chain!") ? static_cast
<void> (0) : __assert_fail ("Chain.getNode() && Chain.getValueType() == MVT::Other && \"LowerReturn didn't return a valid chain!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 1912, __PRETTY_FUNCTION__))
1912 "LowerReturn didn't return a valid chain!")((Chain.getNode() && Chain.getValueType() == MVT::Other
&& "LowerReturn didn't return a valid chain!") ? static_cast
<void> (0) : __assert_fail ("Chain.getNode() && Chain.getValueType() == MVT::Other && \"LowerReturn didn't return a valid chain!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 1912, __PRETTY_FUNCTION__))
;
1913
1914 // Update the DAG with the new chain value resulting from return lowering.
1915 DAG.setRoot(Chain);
1916}
1917
1918/// CopyToExportRegsIfNeeded - If the given value has virtual registers
1919/// created for it, emit nodes to copy the value into the virtual
1920/// registers.
1921void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) {
1922 // Skip empty types
1923 if (V->getType()->isEmptyTy())
1924 return;
1925
1926 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1927 if (VMI != FuncInfo.ValueMap.end()) {
1928 assert(!V->use_empty() && "Unused value assigned virtual registers!")((!V->use_empty() && "Unused value assigned virtual registers!"
) ? static_cast<void> (0) : __assert_fail ("!V->use_empty() && \"Unused value assigned virtual registers!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 1928, __PRETTY_FUNCTION__))
;
1929 CopyValueToVirtualRegister(V, VMI->second);
1930 }
1931}
1932
1933/// ExportFromCurrentBlock - If this condition isn't known to be exported from
1934/// the current basic block, add it to ValueMap now so that we'll get a
1935/// CopyTo/FromReg.
1936void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) {
1937 // No need to export constants.
1938 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1939
1940 // Already exported?
1941 if (FuncInfo.isExportedInst(V)) return;
1942
1943 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1944 CopyValueToVirtualRegister(V, Reg);
1945}
1946
1947bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V,
1948 const BasicBlock *FromBB) {
1949 // The operands of the setcc have to be in this block. We don't know
1950 // how to export them from some other block.
1951 if (const Instruction *VI = dyn_cast<Instruction>(V)) {
1952 // Can export from current BB.
1953 if (VI->getParent() == FromBB)
1954 return true;
1955
1956 // Is already exported, noop.
1957 return FuncInfo.isExportedInst(V);
1958 }
1959
1960 // If this is an argument, we can export it if the BB is the entry block or
1961 // if it is already exported.
1962 if (isa<Argument>(V)) {
1963 if (FromBB == &FromBB->getParent()->getEntryBlock())
1964 return true;
1965
1966 // Otherwise, can only export this if it is already exported.
1967 return FuncInfo.isExportedInst(V);
1968 }
1969
1970 // Otherwise, constants can always be exported.
1971 return true;
1972}
1973
1974/// Return branch probability calculated by BranchProbabilityInfo for IR blocks.
1975BranchProbability
1976SelectionDAGBuilder::getEdgeProbability(const MachineBasicBlock *Src,
1977 const MachineBasicBlock *Dst) const {
1978 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1979 const BasicBlock *SrcBB = Src->getBasicBlock();
1980 const BasicBlock *DstBB = Dst->getBasicBlock();
1981 if (!BPI) {
1982 // If BPI is not available, set the default probability as 1 / N, where N is
1983 // the number of successors.
1984 auto SuccSize = std::max<uint32_t>(succ_size(SrcBB), 1);
1985 return BranchProbability(1, SuccSize);
1986 }
1987 return BPI->getEdgeProbability(SrcBB, DstBB);
1988}
1989
1990void SelectionDAGBuilder::addSuccessorWithProb(MachineBasicBlock *Src,
1991 MachineBasicBlock *Dst,
1992 BranchProbability Prob) {
1993 if (!FuncInfo.BPI)
1994 Src->addSuccessorWithoutProb(Dst);
1995 else {
1996 if (Prob.isUnknown())
1997 Prob = getEdgeProbability(Src, Dst);
1998 Src->addSuccessor(Dst, Prob);
1999 }
2000}
2001
2002static bool InBlock(const Value *V, const BasicBlock *BB) {
2003 if (const Instruction *I = dyn_cast<Instruction>(V))
2004 return I->getParent() == BB;
2005 return true;
2006}
2007
2008/// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
2009/// This function emits a branch and is used at the leaves of an OR or an
2010/// AND operator tree.
2011void
2012SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond,
2013 MachineBasicBlock *TBB,
2014 MachineBasicBlock *FBB,
2015 MachineBasicBlock *CurBB,
2016 MachineBasicBlock *SwitchBB,
2017 BranchProbability TProb,
2018 BranchProbability FProb,
2019 bool InvertCond) {
2020 const BasicBlock *BB = CurBB->getBasicBlock();
2021
2022 // If the leaf of the tree is a comparison, merge the condition into
2023 // the caseblock.
2024 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
2025 // The operands of the cmp have to be in this block. We don't know
2026 // how to export them from some other block. If this is the first block
2027 // of the sequence, no exporting is needed.
2028 if (CurBB == SwitchBB ||
2029 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
2030 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
2031 ISD::CondCode Condition;
2032 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
2033 ICmpInst::Predicate Pred =
2034 InvertCond ? IC->getInversePredicate() : IC->getPredicate();
2035 Condition = getICmpCondCode(Pred);
2036 } else {
2037 const FCmpInst *FC = cast<FCmpInst>(Cond);
2038 FCmpInst::Predicate Pred =
2039 InvertCond ? FC->getInversePredicate() : FC->getPredicate();
2040 Condition = getFCmpCondCode(Pred);
2041 if (TM.Options.NoNaNsFPMath)
2042 Condition = getFCmpCodeWithoutNaN(Condition);
2043 }
2044
2045 CaseBlock CB(Condition, BOp->getOperand(0), BOp->getOperand(1), nullptr,
2046 TBB, FBB, CurBB, getCurSDLoc(), TProb, FProb);
2047 SwitchCases.push_back(CB);
2048 return;
2049 }
2050 }
2051
2052 // Create a CaseBlock record representing this branch.
2053 ISD::CondCode Opc = InvertCond ? ISD::SETNE : ISD::SETEQ;
2054 CaseBlock CB(Opc, Cond, ConstantInt::getTrue(*DAG.getContext()),
2055 nullptr, TBB, FBB, CurBB, getCurSDLoc(), TProb, FProb);
2056 SwitchCases.push_back(CB);
2057}
2058
2059void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
2060 MachineBasicBlock *TBB,
2061 MachineBasicBlock *FBB,
2062 MachineBasicBlock *CurBB,
2063 MachineBasicBlock *SwitchBB,
2064 Instruction::BinaryOps Opc,
2065 BranchProbability TProb,
2066 BranchProbability FProb,
2067 bool InvertCond) {
2068 // Skip over not part of the tree and remember to invert op and operands at
2069 // next level.
2070 Value *NotCond;
2071 if (match(Cond, m_OneUse(m_Not(m_Value(NotCond)))) &&
2072 InBlock(NotCond, CurBB->getBasicBlock())) {
2073 FindMergedConditions(NotCond, TBB, FBB, CurBB, SwitchBB, Opc, TProb, FProb,
2074 !InvertCond);
2075 return;
2076 }
2077
2078 const Instruction *BOp = dyn_cast<Instruction>(Cond);
2079 // Compute the effective opcode for Cond, taking into account whether it needs
2080 // to be inverted, e.g.
2081 // and (not (or A, B)), C
2082 // gets lowered as
2083 // and (and (not A, not B), C)
2084 unsigned BOpc = 0;
2085 if (BOp) {
2086 BOpc = BOp->getOpcode();
2087 if (InvertCond) {
2088 if (BOpc == Instruction::And)
2089 BOpc = Instruction::Or;
2090 else if (BOpc == Instruction::Or)
2091 BOpc = Instruction::And;
2092 }
2093 }
2094
2095 // If this node is not part of the or/and tree, emit it as a branch.
2096 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
2097 BOpc != unsigned(Opc) || !BOp->hasOneUse() ||
2098 BOp->getParent() != CurBB->getBasicBlock() ||
2099 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
2100 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
2101 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB,
2102 TProb, FProb, InvertCond);
2103 return;
2104 }
2105
2106 // Create TmpBB after CurBB.
2107 MachineFunction::iterator BBI(CurBB);
2108 MachineFunction &MF = DAG.getMachineFunction();
2109 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
2110 CurBB->getParent()->insert(++BBI, TmpBB);
2111
2112 if (Opc == Instruction::Or) {
2113 // Codegen X | Y as:
2114 // BB1:
2115 // jmp_if_X TBB
2116 // jmp TmpBB
2117 // TmpBB:
2118 // jmp_if_Y TBB
2119 // jmp FBB
2120 //
2121
2122 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
2123 // The requirement is that
2124 // TrueProb for BB1 + (FalseProb for BB1 * TrueProb for TmpBB)
2125 // = TrueProb for original BB.
2126 // Assuming the original probabilities are A and B, one choice is to set
2127 // BB1's probabilities to A/2 and A/2+B, and set TmpBB's probabilities to
2128 // A/(1+B) and 2B/(1+B). This choice assumes that
2129 // TrueProb for BB1 == FalseProb for BB1 * TrueProb for TmpBB.
2130 // Another choice is to assume TrueProb for BB1 equals to TrueProb for
2131 // TmpBB, but the math is more complicated.
2132
2133 auto NewTrueProb = TProb / 2;
2134 auto NewFalseProb = TProb / 2 + FProb;
2135 // Emit the LHS condition.
2136 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc,
2137 NewTrueProb, NewFalseProb, InvertCond);
2138
2139 // Normalize A/2 and B to get A/(1+B) and 2B/(1+B).
2140 SmallVector<BranchProbability, 2> Probs{TProb / 2, FProb};
2141 BranchProbability::normalizeProbabilities(Probs.begin(), Probs.end());
2142 // Emit the RHS condition into TmpBB.
2143 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
2144 Probs[0], Probs[1], InvertCond);
2145 } else {
2146 assert(Opc == Instruction::And && "Unknown merge op!")((Opc == Instruction::And && "Unknown merge op!") ? static_cast
<void> (0) : __assert_fail ("Opc == Instruction::And && \"Unknown merge op!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 2146, __PRETTY_FUNCTION__))
;
2147 // Codegen X & Y as:
2148 // BB1:
2149 // jmp_if_X TmpBB
2150 // jmp FBB
2151 // TmpBB:
2152 // jmp_if_Y TBB
2153 // jmp FBB
2154 //
2155 // This requires creation of TmpBB after CurBB.
2156
2157 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
2158 // The requirement is that
2159 // FalseProb for BB1 + (TrueProb for BB1 * FalseProb for TmpBB)
2160 // = FalseProb for original BB.
2161 // Assuming the original probabilities are A and B, one choice is to set
2162 // BB1's probabilities to A+B/2 and B/2, and set TmpBB's probabilities to
2163 // 2A/(1+A) and B/(1+A). This choice assumes that FalseProb for BB1 ==
2164 // TrueProb for BB1 * FalseProb for TmpBB.
2165
2166 auto NewTrueProb = TProb + FProb / 2;
2167 auto NewFalseProb = FProb / 2;
2168 // Emit the LHS condition.
2169 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc,
2170 NewTrueProb, NewFalseProb, InvertCond);
2171
2172 // Normalize A and B/2 to get 2A/(1+A) and B/(1+A).
2173 SmallVector<BranchProbability, 2> Probs{TProb, FProb / 2};
2174 BranchProbability::normalizeProbabilities(Probs.begin(), Probs.end());
2175 // Emit the RHS condition into TmpBB.
2176 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
2177 Probs[0], Probs[1], InvertCond);
2178 }
2179}
2180
2181/// If the set of cases should be emitted as a series of branches, return true.
2182/// If we should emit this as a bunch of and/or'd together conditions, return
2183/// false.
2184bool
2185SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases) {
2186 if (Cases.size() != 2) return true;
2187
2188 // If this is two comparisons of the same values or'd or and'd together, they
2189 // will get folded into a single comparison, so don't emit two blocks.
2190 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
2191 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
2192 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
2193 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
2194 return false;
2195 }
2196
2197 // Handle: (X != null) | (Y != null) --> (X|Y) != 0
2198 // Handle: (X == null) & (Y == null) --> (X|Y) == 0
2199 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
2200 Cases[0].CC == Cases[1].CC &&
2201 isa<Constant>(Cases[0].CmpRHS) &&
2202 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
2203 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
2204 return false;
2205 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
2206 return false;
2207 }
2208
2209 return true;
2210}
2211
2212void SelectionDAGBuilder::visitBr(const BranchInst &I) {
2213 MachineBasicBlock *BrMBB = FuncInfo.MBB;
2214
2215 // Update machine-CFG edges.
2216 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
2217
2218 if (I.isUnconditional()) {
2219 // Update machine-CFG edges.
2220 BrMBB->addSuccessor(Succ0MBB);
2221
2222 // If this is not a fall-through branch or optimizations are switched off,
2223 // emit the branch.
2224 if (Succ0MBB != NextBlock(BrMBB) || TM.getOptLevel() == CodeGenOpt::None)
2225 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
2226 MVT::Other, getControlRoot(),
2227 DAG.getBasicBlock(Succ0MBB)));
2228
2229 return;
2230 }
2231
2232 // If this condition is one of the special cases we handle, do special stuff
2233 // now.
2234 const Value *CondVal = I.getCondition();
2235 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
2236
2237 // If this is a series of conditions that are or'd or and'd together, emit
2238 // this as a sequence of branches instead of setcc's with and/or operations.
2239 // As long as jumps are not expensive, this should improve performance.
2240 // For example, instead of something like:
2241 // cmp A, B
2242 // C = seteq
2243 // cmp D, E
2244 // F = setle
2245 // or C, F
2246 // jnz foo
2247 // Emit:
2248 // cmp A, B
2249 // je foo
2250 // cmp D, E
2251 // jle foo
2252 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
2253 Instruction::BinaryOps Opcode = BOp->getOpcode();
2254 if (!DAG.getTargetLoweringInfo().isJumpExpensive() && BOp->hasOneUse() &&
2255 !I.getMetadata(LLVMContext::MD_unpredictable) &&
2256 (Opcode == Instruction::And || Opcode == Instruction::Or)) {
2257 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB,
2258 Opcode,
2259 getEdgeProbability(BrMBB, Succ0MBB),
2260 getEdgeProbability(BrMBB, Succ1MBB),
2261 /*InvertCond=*/false);
2262 // If the compares in later blocks need to use values not currently
2263 // exported from this block, export them now. This block should always
2264 // be the first entry.
2265 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!")((SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!"
) ? static_cast<void> (0) : __assert_fail ("SwitchCases[0].ThisBB == BrMBB && \"Unexpected lowering!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 2265, __PRETTY_FUNCTION__))
;
2266
2267 // Allow some cases to be rejected.
2268 if (ShouldEmitAsBranches(SwitchCases)) {
2269 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
2270 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
2271 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
2272 }
2273
2274 // Emit the branch for this block.
2275 visitSwitchCase(SwitchCases[0], BrMBB);
2276 SwitchCases.erase(SwitchCases.begin());
2277 return;
2278 }
2279
2280 // Okay, we decided not to do this, remove any inserted MBB's and clear
2281 // SwitchCases.
2282 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
2283 FuncInfo.MF->erase(SwitchCases[i].ThisBB);
2284
2285 SwitchCases.clear();
2286 }
2287 }
2288
2289 // Create a CaseBlock record representing this branch.
2290 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
2291 nullptr, Succ0MBB, Succ1MBB, BrMBB, getCurSDLoc());
2292
2293 // Use visitSwitchCase to actually insert the fast branch sequence for this
2294 // cond branch.
2295 visitSwitchCase(CB, BrMBB);
2296}
2297
2298/// visitSwitchCase - Emits the necessary code to represent a single node in
2299/// the binary search tree resulting from lowering a switch instruction.
2300void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB,
2301 MachineBasicBlock *SwitchBB) {
2302 SDValue Cond;
2303 SDValue CondLHS = getValue(CB.CmpLHS);
2304 SDLoc dl = CB.DL;
2305
2306 if (CB.CC == ISD::SETTRUE) {
2307 // Branch or fall through to TrueBB.
2308 addSuccessorWithProb(SwitchBB, CB.TrueBB, CB.TrueProb);
2309 SwitchBB->normalizeSuccProbs();
2310 if (CB.TrueBB != NextBlock(SwitchBB)) {
2311 DAG.setRoot(DAG.getNode(ISD::BR, dl, MVT::Other, getControlRoot(),
2312 DAG.getBasicBlock(CB.TrueBB)));
2313 }
2314 return;
2315 }
2316
2317 auto &TLI = DAG.getTargetLoweringInfo();
2318 EVT MemVT = TLI.getMemValueType(DAG.getDataLayout(), CB.CmpLHS->getType());
2319
2320 // Build the setcc now.
2321 if (!CB.CmpMHS) {
2322 // Fold "(X == true)" to X and "(X == false)" to !X to
2323 // handle common cases produced by branch lowering.
2324 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
2325 CB.CC == ISD::SETEQ)
2326 Cond = CondLHS;
2327 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
2328 CB.CC == ISD::SETEQ) {
2329 SDValue True = DAG.getConstant(1, dl, CondLHS.getValueType());
2330 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
2331 } else {
2332 SDValue CondRHS = getValue(CB.CmpRHS);
2333
2334 // If a pointer's DAG type is larger than its memory type then the DAG
2335 // values are zero-extended. This breaks signed comparisons so truncate
2336 // back to the underlying type before doing the compare.
2337 if (CondLHS.getValueType() != MemVT) {
2338 CondLHS = DAG.getPtrExtOrTrunc(CondLHS, getCurSDLoc(), MemVT);
2339 CondRHS = DAG.getPtrExtOrTrunc(CondRHS, getCurSDLoc(), MemVT);
2340 }
2341 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, CondRHS, CB.CC);
2342 }
2343 } else {
2344 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now")((CB.CC == ISD::SETLE && "Can handle only LE ranges now"
) ? static_cast<void> (0) : __assert_fail ("CB.CC == ISD::SETLE && \"Can handle only LE ranges now\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 2344, __PRETTY_FUNCTION__))
;
2345
2346 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
2347 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
2348
2349 SDValue CmpOp = getValue(CB.CmpMHS);
2350 EVT VT = CmpOp.getValueType();
2351
2352 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
2353 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, dl, VT),
2354 ISD::SETLE);
2355 } else {
2356 SDValue SUB = DAG.getNode(ISD::SUB, dl,
2357 VT, CmpOp, DAG.getConstant(Low, dl, VT));
2358 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
2359 DAG.getConstant(High-Low, dl, VT), ISD::SETULE);
2360 }
2361 }
2362
2363 // Update successor info
2364 addSuccessorWithProb(SwitchBB, CB.TrueBB, CB.TrueProb);
2365 // TrueBB and FalseBB are always different unless the incoming IR is
2366 // degenerate. This only happens when running llc on weird IR.
2367 if (CB.TrueBB != CB.FalseBB)
2368 addSuccessorWithProb(SwitchBB, CB.FalseBB, CB.FalseProb);
2369 SwitchBB->normalizeSuccProbs();
2370
2371 // If the lhs block is the next block, invert the condition so that we can
2372 // fall through to the lhs instead of the rhs block.
2373 if (CB.TrueBB == NextBlock(SwitchBB)) {
2374 std::swap(CB.TrueBB, CB.FalseBB);
2375 SDValue True = DAG.getConstant(1, dl, Cond.getValueType());
2376 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
2377 }
2378
2379 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
2380 MVT::Other, getControlRoot(), Cond,
2381 DAG.getBasicBlock(CB.TrueBB));
2382
2383 // Insert the false branch. Do this even if it's a fall through branch,
2384 // this makes it easier to do DAG optimizations which require inverting
2385 // the branch condition.
2386 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
2387 DAG.getBasicBlock(CB.FalseBB));
2388
2389 DAG.setRoot(BrCond);
2390}
2391
2392/// visitJumpTable - Emit JumpTable node in the current MBB
2393void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
2394 // Emit the code for the jump table
2395 assert(JT.Reg != -1U && "Should lower JT Header first!")((JT.Reg != -1U && "Should lower JT Header first!") ?
static_cast<void> (0) : __assert_fail ("JT.Reg != -1U && \"Should lower JT Header first!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 2395, __PRETTY_FUNCTION__))
;
2396 EVT PTy = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
2397 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(),
2398 JT.Reg, PTy);
2399 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
2400 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurSDLoc(),
2401 MVT::Other, Index.getValue(1),
2402 Table, Index);
2403 DAG.setRoot(BrJumpTable);
2404}
2405
2406/// visitJumpTableHeader - This function emits necessary code to produce index
2407/// in the JumpTable from switch case.
2408void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
2409 JumpTableHeader &JTH,
2410 MachineBasicBlock *SwitchBB) {
2411 SDLoc dl = getCurSDLoc();
2412
2413 // Subtract the lowest switch case value from the value being switched on.
2414 SDValue SwitchOp = getValue(JTH.SValue);
2415 EVT VT = SwitchOp.getValueType();
2416 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, SwitchOp,
2417 DAG.getConstant(JTH.First, dl, VT));
2418
2419 // The SDNode we just created, which holds the value being switched on minus
2420 // the smallest case value, needs to be copied to a virtual register so it
2421 // can be used as an index into the jump table in a subsequent basic block.
2422 // This value may be smaller or larger than the target's pointer type, and
2423 // therefore require extension or truncating.
2424 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2425 SwitchOp = DAG.getZExtOrTrunc(Sub, dl, TLI.getPointerTy(DAG.getDataLayout()));
2426
2427 unsigned JumpTableReg =
2428 FuncInfo.CreateReg(TLI.getPointerTy(DAG.getDataLayout()));
2429 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), dl,
2430 JumpTableReg, SwitchOp);
2431 JT.Reg = JumpTableReg;
2432
2433 if (!JTH.OmitRangeCheck) {
2434 // Emit the range check for the jump table, and branch to the default block
2435 // for the switch statement if the value being switched on exceeds the
2436 // largest case in the switch.
2437 SDValue CMP = DAG.getSetCC(
2438 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
2439 Sub.getValueType()),
2440 Sub, DAG.getConstant(JTH.Last - JTH.First, dl, VT), ISD::SETUGT);
2441
2442 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
2443 MVT::Other, CopyTo, CMP,
2444 DAG.getBasicBlock(JT.Default));
2445
2446 // Avoid emitting unnecessary branches to the next block.
2447 if (JT.MBB != NextBlock(SwitchBB))
2448 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
2449 DAG.getBasicBlock(JT.MBB));
2450
2451 DAG.setRoot(BrCond);
2452 } else {
2453 // Avoid emitting unnecessary branches to the next block.
2454 if (JT.MBB != NextBlock(SwitchBB))
2455 DAG.setRoot(DAG.getNode(ISD::BR, dl, MVT::Other, CopyTo,
2456 DAG.getBasicBlock(JT.MBB)));
2457 else
2458 DAG.setRoot(CopyTo);
2459 }
2460}
2461
2462/// Create a LOAD_STACK_GUARD node, and let it carry the target specific global
2463/// variable if there exists one.
2464static SDValue getLoadStackGuard(SelectionDAG &DAG, const SDLoc &DL,
2465 SDValue &Chain) {
2466 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2467 EVT PtrTy = TLI.getPointerTy(DAG.getDataLayout());
2468 EVT PtrMemTy = TLI.getPointerMemTy(DAG.getDataLayout());
2469 MachineFunction &MF = DAG.getMachineFunction();
2470 Value *Global = TLI.getSDagStackGuard(*MF.getFunction().getParent());
2471 MachineSDNode *Node =
2472 DAG.getMachineNode(TargetOpcode::LOAD_STACK_GUARD, DL, PtrTy, Chain);
2473 if (Global) {
2474 MachinePointerInfo MPInfo(Global);
2475 auto Flags = MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant |
2476 MachineMemOperand::MODereferenceable;
2477 MachineMemOperand *MemRef = MF.getMachineMemOperand(
2478 MPInfo, Flags, PtrTy.getSizeInBits() / 8, DAG.getEVTAlignment(PtrTy));
2479 DAG.setNodeMemRefs(Node, {MemRef});
2480 }
2481 if (PtrTy != PtrMemTy)
2482 return DAG.getPtrExtOrTrunc(SDValue(Node, 0), DL, PtrMemTy);
2483 return SDValue(Node, 0);
2484}
2485
2486/// Codegen a new tail for a stack protector check ParentMBB which has had its
2487/// tail spliced into a stack protector check success bb.
2488///
2489/// For a high level explanation of how this fits into the stack protector
2490/// generation see the comment on the declaration of class
2491/// StackProtectorDescriptor.
2492void SelectionDAGBuilder::visitSPDescriptorParent(StackProtectorDescriptor &SPD,
2493 MachineBasicBlock *ParentBB) {
2494
2495 // First create the loads to the guard/stack slot for the comparison.
2496 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2497 EVT PtrTy = TLI.getPointerTy(DAG.getDataLayout());
2498 EVT PtrMemTy = TLI.getPointerMemTy(DAG.getDataLayout());
2499
2500 MachineFrameInfo &MFI = ParentBB->getParent()->getFrameInfo();
2501 int FI = MFI.getStackProtectorIndex();
2502
2503 SDValue Guard;
2504 SDLoc dl = getCurSDLoc();
2505 SDValue StackSlotPtr = DAG.getFrameIndex(FI, PtrTy);
2506 const Module &M = *ParentBB->getParent()->getFunction().getParent();
2507 unsigned Align = DL->getPrefTypeAlignment(Type::getInt8PtrTy(M.getContext()));
2508
2509 // Generate code to load the content of the guard slot.
2510 SDValue GuardVal = DAG.getLoad(
2511 PtrMemTy, dl, DAG.getEntryNode(), StackSlotPtr,
2512 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI), Align,
2513 MachineMemOperand::MOVolatile);
2514
2515 if (TLI.useStackGuardXorFP())
2516 GuardVal = TLI.emitStackGuardXorFP(DAG, GuardVal, dl);
2517
2518 // Retrieve guard check function, nullptr if instrumentation is inlined.
2519 if (const Function *GuardCheckFn = TLI.getSSPStackGuardCheck(M)) {
2520 // The target provides a guard check function to validate the guard value.
2521 // Generate a call to that function with the content of the guard slot as
2522 // argument.
2523 FunctionType *FnTy = GuardCheckFn->getFunctionType();
2524 assert(FnTy->getNumParams() == 1 && "Invalid function signature")((FnTy->getNumParams() == 1 && "Invalid function signature"
) ? static_cast<void> (0) : __assert_fail ("FnTy->getNumParams() == 1 && \"Invalid function signature\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 2524, __PRETTY_FUNCTION__))
;
2525
2526 TargetLowering::ArgListTy Args;
2527 TargetLowering::ArgListEntry Entry;
2528 Entry.Node = GuardVal;
2529 Entry.Ty = FnTy->getParamType(0);
2530 if (GuardCheckFn->hasAttribute(1, Attribute::AttrKind::InReg))
2531 Entry.IsInReg = true;
2532 Args.push_back(Entry);
2533
2534 TargetLowering::CallLoweringInfo CLI(DAG);
2535 CLI.setDebugLoc(getCurSDLoc())
2536 .setChain(DAG.getEntryNode())
2537 .setCallee(GuardCheckFn->getCallingConv(), FnTy->getReturnType(),
2538 getValue(GuardCheckFn), std::move(Args));
2539
2540 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
2541 DAG.setRoot(Result.second);
2542 return;
2543 }
2544
2545 // If useLoadStackGuardNode returns true, generate LOAD_STACK_GUARD.
2546 // Otherwise, emit a volatile load to retrieve the stack guard value.
2547 SDValue Chain = DAG.getEntryNode();
2548 if (TLI.useLoadStackGuardNode()) {
2549 Guard = getLoadStackGuard(DAG, dl, Chain);
2550 } else {
2551 const Value *IRGuard = TLI.getSDagStackGuard(M);
2552 SDValue GuardPtr = getValue(IRGuard);
2553
2554 Guard = DAG.getLoad(PtrMemTy, dl, Chain, GuardPtr,
2555 MachinePointerInfo(IRGuard, 0), Align,
2556 MachineMemOperand::MOVolatile);
2557 }
2558
2559 // Perform the comparison via a subtract/getsetcc.
2560 EVT VT = Guard.getValueType();
2561 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, Guard, GuardVal);
2562
2563 SDValue Cmp = DAG.getSetCC(dl, TLI.getSetCCResultType(DAG.getDataLayout(),
2564 *DAG.getContext(),
2565 Sub.getValueType()),
2566 Sub, DAG.getConstant(0, dl, VT), ISD::SETNE);
2567
2568 // If the sub is not 0, then we know the guard/stackslot do not equal, so
2569 // branch to failure MBB.
2570 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
2571 MVT::Other, GuardVal.getOperand(0),
2572 Cmp, DAG.getBasicBlock(SPD.getFailureMBB()));
2573 // Otherwise branch to success MBB.
2574 SDValue Br = DAG.getNode(ISD::BR, dl,
2575 MVT::Other, BrCond,
2576 DAG.getBasicBlock(SPD.getSuccessMBB()));
2577
2578 DAG.setRoot(Br);
2579}
2580
2581/// Codegen the failure basic block for a stack protector check.
2582///
2583/// A failure stack protector machine basic block consists simply of a call to
2584/// __stack_chk_fail().
2585///
2586/// For a high level explanation of how this fits into the stack protector
2587/// generation see the comment on the declaration of class
2588/// StackProtectorDescriptor.
2589void
2590SelectionDAGBuilder::visitSPDescriptorFailure(StackProtectorDescriptor &SPD) {
2591 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2592 SDValue Chain =
2593 TLI.makeLibCall(DAG, RTLIB::STACKPROTECTOR_CHECK_FAIL, MVT::isVoid,
2594 None, false, getCurSDLoc(), false, false).second;
2595 // On PS4, the "return address" must still be within the calling function,
2596 // even if it's at the very end, so emit an explicit TRAP here.
2597 // Passing 'true' for doesNotReturn above won't generate the trap for us.
2598 if (TM.getTargetTriple().isPS4CPU())
2599 Chain = DAG.getNode(ISD::TRAP, getCurSDLoc(), MVT::Other, Chain);
2600
2601 DAG.setRoot(Chain);
2602}
2603
2604/// visitBitTestHeader - This function emits necessary code to produce value
2605/// suitable for "bit tests"
2606void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
2607 MachineBasicBlock *SwitchBB) {
2608 SDLoc dl = getCurSDLoc();
2609
2610 // Subtract the minimum value
2611 SDValue SwitchOp = getValue(B.SValue);
2612 EVT VT = SwitchOp.getValueType();
2613 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, SwitchOp,
2614 DAG.getConstant(B.First, dl, VT));
2615
2616 // Check range
2617 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2618 SDValue RangeCmp = DAG.getSetCC(
2619 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
2620 Sub.getValueType()),
2621 Sub, DAG.getConstant(B.Range, dl, VT), ISD::SETUGT);
2622
2623 // Determine the type of the test operands.
2624 bool UsePtrType = false;
2625 if (!TLI.isTypeLegal(VT))
2626 UsePtrType = true;
2627 else {
2628 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i)
2629 if (!isUIntN(VT.getSizeInBits(), B.Cases[i].Mask)) {
2630 // Switch table case range are encoded into series of masks.
2631 // Just use pointer type, it's guaranteed to fit.
2632 UsePtrType = true;
2633 break;
2634 }
2635 }
2636 if (UsePtrType) {
2637 VT = TLI.getPointerTy(DAG.getDataLayout());
2638 Sub = DAG.getZExtOrTrunc(Sub, dl, VT);
2639 }
2640
2641 B.RegVT = VT.getSimpleVT();
2642 B.Reg = FuncInfo.CreateReg(B.RegVT);
2643 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), dl, B.Reg, Sub);
2644
2645 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
2646
2647 addSuccessorWithProb(SwitchBB, B.Default, B.DefaultProb);
2648 addSuccessorWithProb(SwitchBB, MBB, B.Prob);
2649 SwitchBB->normalizeSuccProbs();
2650
2651 SDValue BrRange = DAG.getNode(ISD::BRCOND, dl,
2652 MVT::Other, CopyTo, RangeCmp,
2653 DAG.getBasicBlock(B.Default));
2654
2655 // Avoid emitting unnecessary branches to the next block.
2656 if (MBB != NextBlock(SwitchBB))
2657 BrRange = DAG.getNode(ISD::BR, dl, MVT::Other, BrRange,
2658 DAG.getBasicBlock(MBB));
2659
2660 DAG.setRoot(BrRange);
2661}
2662
2663/// visitBitTestCase - this function produces one "bit test"
2664void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB,
2665 MachineBasicBlock* NextMBB,
2666 BranchProbability BranchProbToNext,
2667 unsigned Reg,
2668 BitTestCase &B,
2669 MachineBasicBlock *SwitchBB) {
2670 SDLoc dl = getCurSDLoc();
2671 MVT VT = BB.RegVT;
2672 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), dl, Reg, VT);
2673 SDValue Cmp;
2674 unsigned PopCount = countPopulation(B.Mask);
2675 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2676 if (PopCount == 1) {
2677 // Testing for a single bit; just compare the shift count with what it
2678 // would need to be to shift a 1 bit in that position.
2679 Cmp = DAG.getSetCC(
2680 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT),
2681 ShiftOp, DAG.getConstant(countTrailingZeros(B.Mask), dl, VT),
2682 ISD::SETEQ);
2683 } else if (PopCount == BB.Range) {
2684 // There is only one zero bit in the range, test for it directly.
2685 Cmp = DAG.getSetCC(
2686 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT),
2687 ShiftOp, DAG.getConstant(countTrailingOnes(B.Mask), dl, VT),
2688 ISD::SETNE);
2689 } else {
2690 // Make desired shift
2691 SDValue SwitchVal = DAG.getNode(ISD::SHL, dl, VT,
2692 DAG.getConstant(1, dl, VT), ShiftOp);
2693
2694 // Emit bit tests and jumps
2695 SDValue AndOp = DAG.getNode(ISD::AND, dl,
2696 VT, SwitchVal, DAG.getConstant(B.Mask, dl, VT));
2697 Cmp = DAG.getSetCC(
2698 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT),
2699 AndOp, DAG.getConstant(0, dl, VT), ISD::SETNE);
2700 }
2701
2702 // The branch probability from SwitchBB to B.TargetBB is B.ExtraProb.
2703 addSuccessorWithProb(SwitchBB, B.TargetBB, B.ExtraProb);
2704 // The branch probability from SwitchBB to NextMBB is BranchProbToNext.
2705 addSuccessorWithProb(SwitchBB, NextMBB, BranchProbToNext);
2706 // It is not guaranteed that the sum of B.ExtraProb and BranchProbToNext is
2707 // one as they are relative probabilities (and thus work more like weights),
2708 // and hence we need to normalize them to let the sum of them become one.
2709 SwitchBB->normalizeSuccProbs();
2710
2711 SDValue BrAnd = DAG.getNode(ISD::BRCOND, dl,
2712 MVT::Other, getControlRoot(),
2713 Cmp, DAG.getBasicBlock(B.TargetBB));
2714
2715 // Avoid emitting unnecessary branches to the next block.
2716 if (NextMBB != NextBlock(SwitchBB))
2717 BrAnd = DAG.getNode(ISD::BR, dl, MVT::Other, BrAnd,
2718 DAG.getBasicBlock(NextMBB));
2719
2720 DAG.setRoot(BrAnd);
2721}
2722
2723void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
2724 MachineBasicBlock *InvokeMBB = FuncInfo.MBB;
2725
2726 // Retrieve successors. Look through artificial IR level blocks like
2727 // catchswitch for successors.
2728 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
2729 const BasicBlock *EHPadBB = I.getSuccessor(1);
2730
2731 // Deopt bundles are lowered in LowerCallSiteWithDeoptBundle, and we don't
2732 // have to do anything here to lower funclet bundles.
2733 assert(!I.hasOperandBundlesOtherThan(((!I.hasOperandBundlesOtherThan( {LLVMContext::OB_deopt, LLVMContext
::OB_funclet}) && "Cannot lower invokes with arbitrary operand bundles yet!"
) ? static_cast<void> (0) : __assert_fail ("!I.hasOperandBundlesOtherThan( {LLVMContext::OB_deopt, LLVMContext::OB_funclet}) && \"Cannot lower invokes with arbitrary operand bundles yet!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 2735, __PRETTY_FUNCTION__))
2734 {LLVMContext::OB_deopt, LLVMContext::OB_funclet}) &&((!I.hasOperandBundlesOtherThan( {LLVMContext::OB_deopt, LLVMContext
::OB_funclet}) && "Cannot lower invokes with arbitrary operand bundles yet!"
) ? static_cast<void> (0) : __assert_fail ("!I.hasOperandBundlesOtherThan( {LLVMContext::OB_deopt, LLVMContext::OB_funclet}) && \"Cannot lower invokes with arbitrary operand bundles yet!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 2735, __PRETTY_FUNCTION__))
2735 "Cannot lower invokes with arbitrary operand bundles yet!")((!I.hasOperandBundlesOtherThan( {LLVMContext::OB_deopt, LLVMContext
::OB_funclet}) && "Cannot lower invokes with arbitrary operand bundles yet!"
) ? static_cast<void> (0) : __assert_fail ("!I.hasOperandBundlesOtherThan( {LLVMContext::OB_deopt, LLVMContext::OB_funclet}) && \"Cannot lower invokes with arbitrary operand bundles yet!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 2735, __PRETTY_FUNCTION__))
;
2736
2737 const Value *Callee(I.getCalledValue());
2738 const Function *Fn = dyn_cast<Function>(Callee);
2739 if (isa<InlineAsm>(Callee))
2740 visitInlineAsm(&I);
2741 else if (Fn && Fn->isIntrinsic()) {
2742 switch (Fn->getIntrinsicID()) {
2743 default:
2744 llvm_unreachable("Cannot invoke this intrinsic")::llvm::llvm_unreachable_internal("Cannot invoke this intrinsic"
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 2744)
;
2745 case Intrinsic::donothing:
2746 // Ignore invokes to @llvm.donothing: jump directly to the next BB.
2747 break;
2748 case Intrinsic::experimental_patchpoint_void:
2749 case Intrinsic::experimental_patchpoint_i64:
2750 visitPatchpoint(&I, EHPadBB);
2751 break;
2752 case Intrinsic::experimental_gc_statepoint:
2753 LowerStatepoint(ImmutableStatepoint(&I), EHPadBB);
2754 break;
2755 case Intrinsic::wasm_rethrow_in_catch: {
2756 // This is usually done in visitTargetIntrinsic, but this intrinsic is
2757 // special because it can be invoked, so we manually lower it to a DAG
2758 // node here.
2759 SmallVector<SDValue, 8> Ops;
2760 Ops.push_back(getRoot()); // inchain
2761 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2762 Ops.push_back(
2763 DAG.getTargetConstant(Intrinsic::wasm_rethrow_in_catch, getCurSDLoc(),
2764 TLI.getPointerTy(DAG.getDataLayout())));
2765 SDVTList VTs = DAG.getVTList(ArrayRef<EVT>({MVT::Other})); // outchain
2766 DAG.setRoot(DAG.getNode(ISD::INTRINSIC_VOID, getCurSDLoc(), VTs, Ops));
2767 break;
2768 }
2769 }
2770 } else if (I.countOperandBundlesOfType(LLVMContext::OB_deopt)) {
2771 // Currently we do not lower any intrinsic calls with deopt operand bundles.
2772 // Eventually we will support lowering the @llvm.experimental.deoptimize
2773 // intrinsic, and right now there are no plans to support other intrinsics
2774 // with deopt state.
2775 LowerCallSiteWithDeoptBundle(&I, getValue(Callee), EHPadBB);
2776 } else {
2777 LowerCallTo(&I, getValue(Callee), false, EHPadBB);
2778 }
2779
2780 // If the value of the invoke is used outside of its defining block, make it
2781 // available as a virtual register.
2782 // We already took care of the exported value for the statepoint instruction
2783 // during call to the LowerStatepoint.
2784 if (!isStatepoint(I)) {
2785 CopyToExportRegsIfNeeded(&I);
2786 }
2787
2788 SmallVector<std::pair<MachineBasicBlock *, BranchProbability>, 1> UnwindDests;
2789 BranchProbabilityInfo *BPI = FuncInfo.BPI;
2790 BranchProbability EHPadBBProb =
2791 BPI ? BPI->getEdgeProbability(InvokeMBB->getBasicBlock(), EHPadBB)
2792 : BranchProbability::getZero();
2793 findUnwindDestinations(FuncInfo, EHPadBB, EHPadBBProb, UnwindDests);
2794
2795 // Update successor info.
2796 addSuccessorWithProb(InvokeMBB, Return);
2797 for (auto &UnwindDest : UnwindDests) {
2798 UnwindDest.first->setIsEHPad();
2799 addSuccessorWithProb(InvokeMBB, UnwindDest.first, UnwindDest.second);
2800 }
2801 InvokeMBB->normalizeSuccProbs();
2802
2803 // Drop into normal successor.
2804 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, getControlRoot(),
2805 DAG.getBasicBlock(Return)));
2806}
2807
2808void SelectionDAGBuilder::visitCallBr(const CallBrInst &I) {
2809 MachineBasicBlock *CallBrMBB = FuncInfo.MBB;
2810
2811 // Deopt bundles are lowered in LowerCallSiteWithDeoptBundle, and we don't
2812 // have to do anything here to lower funclet bundles.
2813 assert(!I.hasOperandBundlesOtherThan(((!I.hasOperandBundlesOtherThan( {LLVMContext::OB_deopt, LLVMContext
::OB_funclet}) && "Cannot lower callbrs with arbitrary operand bundles yet!"
) ? static_cast<void> (0) : __assert_fail ("!I.hasOperandBundlesOtherThan( {LLVMContext::OB_deopt, LLVMContext::OB_funclet}) && \"Cannot lower callbrs with arbitrary operand bundles yet!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 2815, __PRETTY_FUNCTION__))
2814 {LLVMContext::OB_deopt, LLVMContext::OB_funclet}) &&((!I.hasOperandBundlesOtherThan( {LLVMContext::OB_deopt, LLVMContext
::OB_funclet}) && "Cannot lower callbrs with arbitrary operand bundles yet!"
) ? static_cast<void> (0) : __assert_fail ("!I.hasOperandBundlesOtherThan( {LLVMContext::OB_deopt, LLVMContext::OB_funclet}) && \"Cannot lower callbrs with arbitrary operand bundles yet!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 2815, __PRETTY_FUNCTION__))
2815 "Cannot lower callbrs with arbitrary operand bundles yet!")((!I.hasOperandBundlesOtherThan( {LLVMContext::OB_deopt, LLVMContext
::OB_funclet}) && "Cannot lower callbrs with arbitrary operand bundles yet!"
) ? static_cast<void> (0) : __assert_fail ("!I.hasOperandBundlesOtherThan( {LLVMContext::OB_deopt, LLVMContext::OB_funclet}) && \"Cannot lower callbrs with arbitrary operand bundles yet!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 2815, __PRETTY_FUNCTION__))
;
2816
2817 assert(isa<InlineAsm>(I.getCalledValue()) &&((isa<InlineAsm>(I.getCalledValue()) && "Only know how to handle inlineasm callbr"
) ? static_cast<void> (0) : __assert_fail ("isa<InlineAsm>(I.getCalledValue()) && \"Only know how to handle inlineasm callbr\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 2818, __PRETTY_FUNCTION__))
2818 "Only know how to handle inlineasm callbr")((isa<InlineAsm>(I.getCalledValue()) && "Only know how to handle inlineasm callbr"
) ? static_cast<void> (0) : __assert_fail ("isa<InlineAsm>(I.getCalledValue()) && \"Only know how to handle inlineasm callbr\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 2818, __PRETTY_FUNCTION__))
;
2819 visitInlineAsm(&I);
2820
2821 // Retrieve successors.
2822 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getDefaultDest()];
2823
2824 // Update successor info.
2825 addSuccessorWithProb(CallBrMBB, Return);
2826 for (unsigned i = 0, e = I.getNumIndirectDests(); i < e; ++i) {
2827 MachineBasicBlock *Target = FuncInfo.MBBMap[I.getIndirectDest(i)];
2828 addSuccessorWithProb(CallBrMBB, Target);
2829 }
2830 CallBrMBB->normalizeSuccProbs();
2831
2832 // Drop into default successor.
2833 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
2834 MVT::Other, getControlRoot(),
2835 DAG.getBasicBlock(Return)));
2836}
2837
2838void SelectionDAGBuilder::visitResume(const ResumeInst &RI) {
2839 llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!")::llvm::llvm_unreachable_internal("SelectionDAGBuilder shouldn't visit resume instructions!"
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 2839)
;
2840}
2841
2842void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) {
2843 assert(FuncInfo.MBB->isEHPad() &&((FuncInfo.MBB->isEHPad() && "Call to landingpad not in landing pad!"
) ? static_cast<void> (0) : __assert_fail ("FuncInfo.MBB->isEHPad() && \"Call to landingpad not in landing pad!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 2844, __PRETTY_FUNCTION__))
2844 "Call to landingpad not in landing pad!")((FuncInfo.MBB->isEHPad() && "Call to landingpad not in landing pad!"
) ? static_cast<void> (0) : __assert_fail ("FuncInfo.MBB->isEHPad() && \"Call to landingpad not in landing pad!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 2844, __PRETTY_FUNCTION__))
;
2845
2846 // If there aren't registers to copy the values into (e.g., during SjLj
2847 // exceptions), then don't bother to create these DAG nodes.
2848 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2849 const Constant *PersonalityFn = FuncInfo.Fn->getPersonalityFn();
2850 if (TLI.getExceptionPointerRegister(PersonalityFn) == 0 &&
2851 TLI.getExceptionSelectorRegister(PersonalityFn) == 0)
2852 return;
2853
2854 // If landingpad's return type is token type, we don't create DAG nodes
2855 // for its exception pointer and selector value. The extraction of exception
2856 // pointer or selector value from token type landingpads is not currently
2857 // supported.
2858 if (LP.getType()->isTokenTy())
2859 return;
2860
2861 SmallVector<EVT, 2> ValueVTs;
2862 SDLoc dl = getCurSDLoc();
2863 ComputeValueVTs(TLI, DAG.getDataLayout(), LP.getType(), ValueVTs);
2864 assert(ValueVTs.size() == 2 && "Only two-valued landingpads are supported")((ValueVTs.size() == 2 && "Only two-valued landingpads are supported"
) ? static_cast<void> (0) : __assert_fail ("ValueVTs.size() == 2 && \"Only two-valued landingpads are supported\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 2864, __PRETTY_FUNCTION__))
;
2865
2866 // Get the two live-in registers as SDValues. The physregs have already been
2867 // copied into virtual registers.
2868 SDValue Ops[2];
2869 if (FuncInfo.ExceptionPointerVirtReg) {
2870 Ops[0] = DAG.getZExtOrTrunc(
2871 DAG.getCopyFromReg(DAG.getEntryNode(), dl,
2872 FuncInfo.ExceptionPointerVirtReg,
2873 TLI.getPointerTy(DAG.getDataLayout())),
2874 dl, ValueVTs[0]);
2875 } else {
2876 Ops[0] = DAG.getConstant(0, dl, TLI.getPointerTy(DAG.getDataLayout()));
2877 }
2878 Ops[1] = DAG.getZExtOrTrunc(
2879 DAG.getCopyFromReg(DAG.getEntryNode(), dl,
2880 FuncInfo.ExceptionSelectorVirtReg,
2881 TLI.getPointerTy(DAG.getDataLayout())),
2882 dl, ValueVTs[1]);
2883
2884 // Merge into one.
2885 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl,
2886 DAG.getVTList(ValueVTs), Ops);
2887 setValue(&LP, Res);
2888}
2889
2890void SelectionDAGBuilder::sortAndRangeify(CaseClusterVector &Clusters) {
2891#ifndef NDEBUG
2892 for (const CaseCluster &CC : Clusters)
2893 assert(CC.Low == CC.High && "Input clusters must be single-case")((CC.Low == CC.High && "Input clusters must be single-case"
) ? static_cast<void> (0) : __assert_fail ("CC.Low == CC.High && \"Input clusters must be single-case\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 2893, __PRETTY_FUNCTION__))
;
2894#endif
2895
2896 llvm::sort(Clusters, [](const CaseCluster &a, const CaseCluster &b) {
2897 return a.Low->getValue().slt(b.Low->getValue());
2898 });
2899
2900 // Merge adjacent clusters with the same destination.
2901 const unsigned N = Clusters.size();
2902 unsigned DstIndex = 0;
2903 for (unsigned SrcIndex = 0; SrcIndex < N; ++SrcIndex) {
2904 CaseCluster &CC = Clusters[SrcIndex];
2905 const ConstantInt *CaseVal = CC.Low;
2906 MachineBasicBlock *Succ = CC.MBB;
2907
2908 if (DstIndex != 0 && Clusters[DstIndex - 1].MBB == Succ &&
2909 (CaseVal->getValue() - Clusters[DstIndex - 1].High->getValue()) == 1) {
2910 // If this case has the same successor and is a neighbour, merge it into
2911 // the previous cluster.
2912 Clusters[DstIndex - 1].High = CaseVal;
2913 Clusters[DstIndex - 1].Prob += CC.Prob;
2914 } else {
2915 std::memmove(&Clusters[DstIndex++], &Clusters[SrcIndex],
2916 sizeof(Clusters[SrcIndex]));
2917 }
2918 }
2919 Clusters.resize(DstIndex);
2920}
2921
2922void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First,
2923 MachineBasicBlock *Last) {
2924 // Update JTCases.
2925 for (unsigned i = 0, e = JTCases.size(); i != e; ++i)
2926 if (JTCases[i].first.HeaderBB == First)
2927 JTCases[i].first.HeaderBB = Last;
2928
2929 // Update BitTestCases.
2930 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i)
2931 if (BitTestCases[i].Parent == First)
2932 BitTestCases[i].Parent = Last;
2933}
2934
2935void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
2936 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB;
2937
2938 // Update machine-CFG edges with unique successors.
2939 SmallSet<BasicBlock*, 32> Done;
2940 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) {
2941 BasicBlock *BB = I.getSuccessor(i);
2942 bool Inserted = Done.insert(BB).second;
2943 if (!Inserted)
2944 continue;
2945
2946 MachineBasicBlock *Succ = FuncInfo.MBBMap[BB];
2947 addSuccessorWithProb(IndirectBrMBB, Succ);
2948 }
2949 IndirectBrMBB->normalizeSuccProbs();
2950
2951 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurSDLoc(),
2952 MVT::Other, getControlRoot(),
2953 getValue(I.getAddress())));
2954}
2955
2956void SelectionDAGBuilder::visitUnreachable(const UnreachableInst &I) {
2957 if (!DAG.getTarget().Options.TrapUnreachable)
2958 return;
2959
2960 // We may be able to ignore unreachable behind a noreturn call.
2961 if (DAG.getTarget().Options.NoTrapAfterNoreturn) {
2962 const BasicBlock &BB = *I.getParent();
2963 if (&I != &BB.front()) {
2964 BasicBlock::const_iterator PredI =
2965 std::prev(BasicBlock::const_iterator(&I));
2966 if (const CallInst *Call = dyn_cast<CallInst>(&*PredI)) {
2967 if (Call->doesNotReturn())
2968 return;
2969 }
2970 }
2971 }
2972
2973 DAG.setRoot(DAG.getNode(ISD::TRAP, getCurSDLoc(), MVT::Other, DAG.getRoot()));
2974}
2975
2976void SelectionDAGBuilder::visitFSub(const User &I) {
2977 // -0.0 - X --> fneg
2978 Type *Ty = I.getType();
2979 if (isa<Constant>(I.getOperand(0)) &&
2980 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) {
2981 SDValue Op2 = getValue(I.getOperand(1));
2982 setValue(&I, DAG.getNode(ISD::FNEG, getCurSDLoc(),
2983 Op2.getValueType(), Op2));
2984 return;
2985 }
2986
2987 visitBinary(I, ISD::FSUB);
2988}
2989
2990/// Checks if the given instruction performs a vector reduction, in which case
2991/// we have the freedom to alter the elements in the result as long as the
2992/// reduction of them stays unchanged.
2993static bool isVectorReductionOp(const User *I) {
2994 const Instruction *Inst = dyn_cast<Instruction>(I);
2995 if (!Inst || !Inst->getType()->isVectorTy())
2996 return false;
2997
2998 auto OpCode = Inst->getOpcode();
2999 switch (OpCode) {
3000 case Instruction::Add:
3001 case Instruction::Mul:
3002 case Instruction::And:
3003 case Instruction::Or:
3004 case Instruction::Xor:
3005 break;
3006 case Instruction::FAdd:
3007 case Instruction::FMul:
3008 if (const FPMathOperator *FPOp = dyn_cast<const FPMathOperator>(Inst))
3009 if (FPOp->getFastMathFlags().isFast())
3010 break;
3011 LLVM_FALLTHROUGH[[clang::fallthrough]];
3012 default:
3013 return false;
3014 }
3015
3016 unsigned ElemNum = Inst->getType()->getVectorNumElements();
3017 // Ensure the reduction size is a power of 2.
3018 if (!isPowerOf2_32(ElemNum))
3019 return false;
3020
3021 unsigned ElemNumToReduce = ElemNum;
3022
3023 // Do DFS search on the def-use chain from the given instruction. We only
3024 // allow four kinds of operations during the search until we reach the
3025 // instruction that extracts the first element from the vector:
3026 //
3027 // 1. The reduction operation of the same opcode as the given instruction.
3028 //
3029 // 2. PHI node.
3030 //
3031 // 3. ShuffleVector instruction together with a reduction operation that
3032 // does a partial reduction.
3033 //
3034 // 4. ExtractElement that extracts the first element from the vector, and we
3035 // stop searching the def-use chain here.
3036 //
3037 // 3 & 4 above perform a reduction on all elements of the vector. We push defs
3038 // from 1-3 to the stack to continue the DFS. The given instruction is not
3039 // a reduction operation if we meet any other instructions other than those
3040 // listed above.
3041
3042 SmallVector<const User *, 16> UsersToVisit{Inst};
3043 SmallPtrSet<const User *, 16> Visited;
3044 bool ReduxExtracted = false;
3045
3046 while (!UsersToVisit.empty()) {
3047 auto User = UsersToVisit.back();
3048 UsersToVisit.pop_back();
3049 if (!Visited.insert(User).second)
3050 continue;
3051
3052 for (const auto &U : User->users()) {
3053 auto Inst = dyn_cast<Instruction>(U);
3054 if (!Inst)
3055 return false;
3056
3057 if (Inst->getOpcode() == OpCode || isa<PHINode>(U)) {
3058 if (const FPMathOperator *FPOp = dyn_cast<const FPMathOperator>(Inst))
3059 if (!isa<PHINode>(FPOp) && !FPOp->getFastMathFlags().isFast())
3060 return false;
3061 UsersToVisit.push_back(U);
3062 } else if (const ShuffleVectorInst *ShufInst =
3063 dyn_cast<ShuffleVectorInst>(U)) {
3064 // Detect the following pattern: A ShuffleVector instruction together
3065 // with a reduction that do partial reduction on the first and second
3066 // ElemNumToReduce / 2 elements, and store the result in
3067 // ElemNumToReduce / 2 elements in another vector.
3068
3069 unsigned ResultElements = ShufInst->getType()->getVectorNumElements();
3070 if (ResultElements < ElemNum)
3071 return false;
3072
3073 if (ElemNumToReduce == 1)
3074 return false;
3075 if (!isa<UndefValue>(U->getOperand(1)))
3076 return false;
3077 for (unsigned i = 0; i < ElemNumToReduce / 2; ++i)
3078 if (ShufInst->getMaskValue(i) != int(i + ElemNumToReduce / 2))
3079 return false;
3080 for (unsigned i = ElemNumToReduce / 2; i < ElemNum; ++i)
3081 if (ShufInst->getMaskValue(i) != -1)
3082 return false;
3083
3084 // There is only one user of this ShuffleVector instruction, which
3085 // must be a reduction operation.
3086 if (!U->hasOneUse())
3087 return false;
3088
3089 auto U2 = dyn_cast<Instruction>(*U->user_begin());
3090 if (!U2 || U2->getOpcode() != OpCode)
3091 return false;
3092
3093 // Check operands of the reduction operation.
3094 if ((U2->getOperand(0) == U->getOperand(0) && U2->getOperand(1) == U) ||
3095 (U2->getOperand(1) == U->getOperand(0) && U2->getOperand(0) == U)) {
3096 UsersToVisit.push_back(U2);
3097 ElemNumToReduce /= 2;
3098 } else
3099 return false;
3100 } else if (isa<ExtractElementInst>(U)) {
3101 // At this moment we should have reduced all elements in the vector.
3102 if (ElemNumToReduce != 1)
3103 return false;
3104
3105 const ConstantInt *Val = dyn_cast<ConstantInt>(U->getOperand(1));
3106 if (!Val || !Val->isZero())
3107 return false;
3108
3109 ReduxExtracted = true;
3110 } else
3111 return false;
3112 }
3113 }
3114 return ReduxExtracted;
3115}
3116
3117void SelectionDAGBuilder::visitUnary(const User &I, unsigned Opcode) {
3118 SDNodeFlags Flags;
3119
3120 SDValue Op = getValue(I.getOperand(0));
3121 SDValue UnNodeValue = DAG.getNode(Opcode, getCurSDLoc(), Op.getValueType(),
3122 Op, Flags);
3123 setValue(&I, UnNodeValue);
3124}
3125
3126void SelectionDAGBuilder::visitBinary(const User &I, unsigned Opcode) {
3127 SDNodeFlags Flags;
3128 if (auto *OFBinOp = dyn_cast<OverflowingBinaryOperator>(&I)) {
3129 Flags.setNoSignedWrap(OFBinOp->hasNoSignedWrap());
3130 Flags.setNoUnsignedWrap(OFBinOp->hasNoUnsignedWrap());
3131 }
3132 if (auto *ExactOp = dyn_cast<PossiblyExactOperator>(&I)) {
3133 Flags.setExact(ExactOp->isExact());
3134 }
3135 if (isVectorReductionOp(&I)) {
3136 Flags.setVectorReduction(true);
3137 LLVM_DEBUG(dbgs() << "Detected a reduction operation:" << I << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << "Detected a reduction operation:"
<< I << "\n"; } } while (false)
;
3138 }
3139
3140 SDValue Op1 = getValue(I.getOperand(0));
3141 SDValue Op2 = getValue(I.getOperand(1));
3142 SDValue BinNodeValue = DAG.getNode(Opcode, getCurSDLoc(), Op1.getValueType(),
3143 Op1, Op2, Flags);
3144 setValue(&I, BinNodeValue);
3145}
3146
3147void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
3148 SDValue Op1 = getValue(I.getOperand(0));
3149 SDValue Op2 = getValue(I.getOperand(1));
3150
3151 EVT ShiftTy = DAG.getTargetLoweringInfo().getShiftAmountTy(
3152 Op1.getValueType(), DAG.getDataLayout());
3153
3154 // Coerce the shift amount to the right type if we can.
3155 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) {
3156 unsigned ShiftSize = ShiftTy.getSizeInBits();
3157 unsigned Op2Size = Op2.getValueSizeInBits();
3158 SDLoc DL = getCurSDLoc();
3159
3160 // If the operand is smaller than the shift count type, promote it.
3161 if (ShiftSize > Op2Size)
3162 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2);
3163
3164 // If the operand is larger than the shift count type but the shift
3165 // count type has enough bits to represent any shift value, truncate
3166 // it now. This is a common case and it exposes the truncate to
3167 // optimization early.
3168 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueSizeInBits()))
3169 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2);
3170 // Otherwise we'll need to temporarily settle for some other convenient
3171 // type. Type legalization will make adjustments once the shiftee is split.
3172 else
3173 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32);
3174 }
3175
3176 bool nuw = false;
3177 bool nsw = false;
3178 bool exact = false;
3179
3180 if (Opcode == ISD::SRL || Opcode == ISD::SRA || Opcode == ISD::SHL) {
3181
3182 if (const OverflowingBinaryOperator *OFBinOp =
3183 dyn_cast<const OverflowingBinaryOperator>(&I)) {
3184 nuw = OFBinOp->hasNoUnsignedWrap();
3185 nsw = OFBinOp->hasNoSignedWrap();
3186 }
3187 if (const PossiblyExactOperator *ExactOp =
3188 dyn_cast<const PossiblyExactOperator>(&I))
3189 exact = ExactOp->isExact();
3190 }
3191 SDNodeFlags Flags;
3192 Flags.setExact(exact);
3193 Flags.setNoSignedWrap(nsw);
3194 Flags.setNoUnsignedWrap(nuw);
3195 SDValue Res = DAG.getNode(Opcode, getCurSDLoc(), Op1.getValueType(), Op1, Op2,
3196 Flags);
3197 setValue(&I, Res);
3198}
3199
3200void SelectionDAGBuilder::visitSDiv(const User &I) {
3201 SDValue Op1 = getValue(I.getOperand(0));
3202 SDValue Op2 = getValue(I.getOperand(1));
3203
3204 SDNodeFlags Flags;
3205 Flags.setExact(isa<PossiblyExactOperator>(&I) &&
3206 cast<PossiblyExactOperator>(&I)->isExact());
3207 setValue(&I, DAG.getNode(ISD::SDIV, getCurSDLoc(), Op1.getValueType(), Op1,
3208 Op2, Flags));
3209}
3210
3211void SelectionDAGBuilder::visitICmp(const User &I) {
3212 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
3213 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I))
3214 predicate = IC->getPredicate();
3215 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
3216 predicate = ICmpInst::Predicate(IC->getPredicate());
3217 SDValue Op1 = getValue(I.getOperand(0));
3218 SDValue Op2 = getValue(I.getOperand(1));
3219 ISD::CondCode Opcode = getICmpCondCode(predicate);
3220
3221 auto &TLI = DAG.getTargetLoweringInfo();
3222 EVT MemVT =
3223 TLI.getMemValueType(DAG.getDataLayout(), I.getOperand(0)->getType());
3224
3225 // If a pointer's DAG type is larger than its memory type then the DAG values
3226 // are zero-extended. This breaks signed comparisons so truncate back to the
3227 // underlying type before doing the compare.
3228 if (Op1.getValueType() != MemVT) {
3229 Op1 = DAG.getPtrExtOrTrunc(Op1, getCurSDLoc(), MemVT);
3230 Op2 = DAG.getPtrExtOrTrunc(Op2, getCurSDLoc(), MemVT);
3231 }
3232
3233 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
3234 I.getType());
3235 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Opcode));
3236}
3237
3238void SelectionDAGBuilder::visitFCmp(const User &I) {
3239 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
3240 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I))
3241 predicate = FC->getPredicate();
3242 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
3243 predicate = FCmpInst::Predicate(FC->getPredicate());
3244 SDValue Op1 = getValue(I.getOperand(0));
3245 SDValue Op2 = getValue(I.getOperand(1));
3246
3247 ISD::CondCode Condition = getFCmpCondCode(predicate);
3248 auto *FPMO = dyn_cast<FPMathOperator>(&I);
3249 if ((FPMO && FPMO->hasNoNaNs()) || TM.Options.NoNaNsFPMath)
3250 Condition = getFCmpCodeWithoutNaN(Condition);
3251
3252 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
3253 I.getType());
3254 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Condition));
3255}
3256
3257// Check if the condition of the select has one use or two users that are both
3258// selects with the same condition.
3259static bool hasOnlySelectUsers(const Value *Cond) {
3260 return llvm::all_of(Cond->users(), [](const Value *V) {
3261 return isa<SelectInst>(V);
3262 });
3263}
3264
3265void SelectionDAGBuilder::visitSelect(const User &I) {
3266 SmallVector<EVT, 4> ValueVTs;
3267 ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(), I.getType(),
3268 ValueVTs);
3269 unsigned NumValues = ValueVTs.size();
3270 if (NumValues == 0) return;
3271
3272 SmallVector<SDValue, 4> Values(NumValues);
3273 SDValue Cond = getValue(I.getOperand(0));
3274 SDValue LHSVal = getValue(I.getOperand(1));
3275 SDValue RHSVal = getValue(I.getOperand(2));
3276 auto BaseOps = {Cond};
3277 ISD::NodeType OpCode = Cond.getValueType().isVector() ?
3278 ISD::VSELECT : ISD::SELECT;
3279
3280 bool IsUnaryAbs = false;
3281
3282 // Min/max matching is only viable if all output VTs are the same.
3283 if (is_splat(ValueVTs)) {
3284 EVT VT = ValueVTs[0];
3285 LLVMContext &Ctx = *DAG.getContext();
3286 auto &TLI = DAG.getTargetLoweringInfo();
3287
3288 // We care about the legality of the operation after it has been type
3289 // legalized.
3290 while (TLI.getTypeAction(Ctx, VT) != TargetLoweringBase::TypeLegal &&
3291 VT != TLI.getTypeToTransformTo(Ctx, VT))
3292 VT = TLI.getTypeToTransformTo(Ctx, VT);
3293
3294 // If the vselect is legal, assume we want to leave this as a vector setcc +
3295 // vselect. Otherwise, if this is going to be scalarized, we want to see if
3296 // min/max is legal on the scalar type.
3297 bool UseScalarMinMax = VT.isVector() &&
3298 !TLI.isOperationLegalOrCustom(ISD::VSELECT, VT);
3299
3300 Value *LHS, *RHS;
3301 auto SPR = matchSelectPattern(const_cast<User*>(&I), LHS, RHS);
3302 ISD::NodeType Opc = ISD::DELETED_NODE;
3303 switch (SPR.Flavor) {
3304 case SPF_UMAX: Opc = ISD::UMAX; break;
3305 case SPF_UMIN: Opc = ISD::UMIN; break;
3306 case SPF_SMAX: Opc = ISD::SMAX; break;
3307 case SPF_SMIN: Opc = ISD::SMIN; break;
3308 case SPF_FMINNUM:
3309 switch (SPR.NaNBehavior) {
3310 case SPNB_NA: llvm_unreachable("No NaN behavior for FP op?")::llvm::llvm_unreachable_internal("No NaN behavior for FP op?"
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 3310)
;
3311 case SPNB_RETURNS_NAN: Opc = ISD::FMINIMUM; break;
3312 case SPNB_RETURNS_OTHER: Opc = ISD::FMINNUM; break;
3313 case SPNB_RETURNS_ANY: {
3314 if (TLI.isOperationLegalOrCustom(ISD::FMINNUM, VT))
3315 Opc = ISD::FMINNUM;
3316 else if (TLI.isOperationLegalOrCustom(ISD::FMINIMUM, VT))
3317 Opc = ISD::FMINIMUM;
3318 else if (UseScalarMinMax)
3319 Opc = TLI.isOperationLegalOrCustom(ISD::FMINNUM, VT.getScalarType()) ?
3320 ISD::FMINNUM : ISD::FMINIMUM;
3321 break;
3322 }
3323 }
3324 break;
3325 case SPF_FMAXNUM:
3326 switch (SPR.NaNBehavior) {
3327 case SPNB_NA: llvm_unreachable("No NaN behavior for FP op?")::llvm::llvm_unreachable_internal("No NaN behavior for FP op?"
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 3327)
;
3328 case SPNB_RETURNS_NAN: Opc = ISD::FMAXIMUM; break;
3329 case SPNB_RETURNS_OTHER: Opc = ISD::FMAXNUM; break;
3330 case SPNB_RETURNS_ANY:
3331
3332 if (TLI.isOperationLegalOrCustom(ISD::FMAXNUM, VT))
3333 Opc = ISD::FMAXNUM;
3334 else if (TLI.isOperationLegalOrCustom(ISD::FMAXIMUM, VT))
3335 Opc = ISD::FMAXIMUM;
3336 else if (UseScalarMinMax)
3337 Opc = TLI.isOperationLegalOrCustom(ISD::FMAXNUM, VT.getScalarType()) ?
3338 ISD::FMAXNUM : ISD::FMAXIMUM;
3339 break;
3340 }
3341 break;
3342 case SPF_ABS:
3343 IsUnaryAbs = true;
3344 Opc = ISD::ABS;
3345 break;
3346 case SPF_NABS:
3347 // TODO: we need to produce sub(0, abs(X)).
3348 default: break;
3349 }
3350
3351 if (!IsUnaryAbs && Opc != ISD::DELETED_NODE &&
3352 (TLI.isOperationLegalOrCustom(Opc, VT) ||
3353 (UseScalarMinMax &&
3354 TLI.isOperationLegalOrCustom(Opc, VT.getScalarType()))) &&
3355 // If the underlying comparison instruction is used by any other
3356 // instruction, the consumed instructions won't be destroyed, so it is
3357 // not profitable to convert to a min/max.
3358 hasOnlySelectUsers(cast<SelectInst>(I).getCondition())) {
3359 OpCode = Opc;
3360 LHSVal = getValue(LHS);
3361 RHSVal = getValue(RHS);
3362 BaseOps = {};
3363 }
3364
3365 if (IsUnaryAbs) {
3366 OpCode = Opc;
3367 LHSVal = getValue(LHS);
3368 BaseOps = {};
3369 }
3370 }
3371
3372 if (IsUnaryAbs) {
3373 for (unsigned i = 0; i != NumValues; ++i) {
3374 Values[i] =
3375 DAG.getNode(OpCode, getCurSDLoc(),
3376 LHSVal.getNode()->getValueType(LHSVal.getResNo() + i),
3377 SDValue(LHSVal.getNode(), LHSVal.getResNo() + i));
3378 }
3379 } else {
3380 for (unsigned i = 0; i != NumValues; ++i) {
3381 SmallVector<SDValue, 3> Ops(BaseOps.begin(), BaseOps.end());
3382 Ops.push_back(SDValue(LHSVal.getNode(), LHSVal.getResNo() + i));
3383 Ops.push_back(SDValue(RHSVal.getNode(), RHSVal.getResNo() + i));
3384 Values[i] = DAG.getNode(
3385 OpCode, getCurSDLoc(),
3386 LHSVal.getNode()->getValueType(LHSVal.getResNo() + i), Ops);
3387 }
3388 }
3389
3390 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
3391 DAG.getVTList(ValueVTs), Values));
3392}
3393
3394void SelectionDAGBuilder::visitTrunc(const User &I) {
3395 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
3396 SDValue N = getValue(I.getOperand(0));
3397 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
3398 I.getType());
3399 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), DestVT, N));
3400}
3401
3402void SelectionDAGBuilder::visitZExt(const User &I) {
3403 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
3404 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
3405 SDValue N = getValue(I.getOperand(0));
3406 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
3407 I.getType());
3408 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurSDLoc(), DestVT, N));
3409}
3410
3411void SelectionDAGBuilder::visitSExt(const User &I) {
3412 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
3413 // SExt also can't be a cast to bool for same reason. So, nothing much to do
3414 SDValue N = getValue(I.getOperand(0));
3415 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
3416 I.getType());
3417 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurSDLoc(), DestVT, N));
3418}
3419
3420void SelectionDAGBuilder::visitFPTrunc(const User &I) {
3421 // FPTrunc is never a no-op cast, no need to check
3422 SDValue N = getValue(I.getOperand(0));
3423 SDLoc dl = getCurSDLoc();
3424 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3425 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
3426 setValue(&I, DAG.getNode(ISD::FP_ROUND, dl, DestVT, N,
3427 DAG.getTargetConstant(
3428 0, dl, TLI.getPointerTy(DAG.getDataLayout()))));
3429}
3430
3431void SelectionDAGBuilder::visitFPExt(const User &I) {
3432 // FPExt is never a no-op cast, no need to check
3433 SDValue N = getValue(I.getOperand(0));
3434 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
3435 I.getType());
3436 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurSDLoc(), DestVT, N));
3437}
3438
3439void SelectionDAGBuilder::visitFPToUI(const User &I) {
3440 // FPToUI is never a no-op cast, no need to check
3441 SDValue N = getValue(I.getOperand(0));
3442 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
3443 I.getType());
3444 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurSDLoc(), DestVT, N));
3445}
3446
3447void SelectionDAGBuilder::visitFPToSI(const User &I) {
3448 // FPToSI is never a no-op cast, no need to check
3449 SDValue N = getValue(I.getOperand(0));
3450 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
3451 I.getType());
3452 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurSDLoc(), DestVT, N));
3453}
3454
3455void SelectionDAGBuilder::visitUIToFP(const User &I) {
3456 // UIToFP is never a no-op cast, no need to check
3457 SDValue N = getValue(I.getOperand(0));
3458 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
3459 I.getType());
3460 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurSDLoc(), DestVT, N));
3461}
3462
3463void SelectionDAGBuilder::visitSIToFP(const User &I) {
3464 // SIToFP is never a no-op cast, no need to check
3465 SDValue N = getValue(I.getOperand(0));
3466 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
3467 I.getType());
3468 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurSDLoc(), DestVT, N));
3469}
3470
3471void SelectionDAGBuilder::visitPtrToInt(const User &I) {
3472 // What to do depends on the size of the integer and the size of the pointer.
3473 // We can either truncate, zero extend, or no-op, accordingly.
3474 SDValue N = getValue(I.getOperand(0));
3475 auto &TLI = DAG.getTargetLoweringInfo();
3476 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
3477 I.getType());
3478 EVT PtrMemVT =
3479 TLI.getMemValueType(DAG.getDataLayout(), I.getOperand(0)->getType());
3480 N = DAG.getPtrExtOrTrunc(N, getCurSDLoc(), PtrMemVT);
3481 N = DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT);
3482 setValue(&I, N);
3483}
3484
3485void SelectionDAGBuilder::visitIntToPtr(const User &I) {
3486 // What to do depends on the size of the integer and the size of the pointer.
3487 // We can either truncate, zero extend, or no-op, accordingly.
3488 SDValue N = getValue(I.getOperand(0));
3489 auto &TLI = DAG.getTargetLoweringInfo();
3490 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
3491 EVT PtrMemVT = TLI.getMemValueType(DAG.getDataLayout(), I.getType());
3492 N = DAG.getZExtOrTrunc(N, getCurSDLoc(), PtrMemVT);
3493 N = DAG.getPtrExtOrTrunc(N, getCurSDLoc(), DestVT);
3494 setValue(&I, N);
3495}
3496
3497void SelectionDAGBuilder::visitBitCast(const User &I) {
3498 SDValue N = getValue(I.getOperand(0));
3499 SDLoc dl = getCurSDLoc();
3500 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
3501 I.getType());
3502
3503 // BitCast assures us that source and destination are the same size so this is
3504 // either a BITCAST or a no-op.
3505 if (DestVT != N.getValueType())
3506 setValue(&I, DAG.getNode(ISD::BITCAST, dl,
3507 DestVT, N)); // convert types.
3508 // Check if the original LLVM IR Operand was a ConstantInt, because getValue()
3509 // might fold any kind of constant expression to an integer constant and that
3510 // is not what we are looking for. Only recognize a bitcast of a genuine
3511 // constant integer as an opaque constant.
3512 else if(ConstantInt *C = dyn_cast<ConstantInt>(I.getOperand(0)))
3513 setValue(&I, DAG.getConstant(C->getValue(), dl, DestVT, /*isTarget=*/false,
3514 /*isOpaque*/true));
3515 else
3516 setValue(&I, N); // noop cast.
3517}
3518
3519void SelectionDAGBuilder::visitAddrSpaceCast(const User &I) {
3520 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3521 const Value *SV = I.getOperand(0);
3522 SDValue N = getValue(SV);
3523 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
3524
3525 unsigned SrcAS = SV->getType()->getPointerAddressSpace();
3526 unsigned DestAS = I.getType()->getPointerAddressSpace();
3527
3528 if (!TLI.isNoopAddrSpaceCast(SrcAS, DestAS))
3529 N = DAG.getAddrSpaceCast(getCurSDLoc(), DestVT, N, SrcAS, DestAS);
3530
3531 setValue(&I, N);
3532}
3533
3534void SelectionDAGBuilder::visitInsertElement(const User &I) {
3535 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3536 SDValue InVec = getValue(I.getOperand(0));
3537 SDValue InVal = getValue(I.getOperand(1));
3538 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(2)), getCurSDLoc(),
3539 TLI.getVectorIdxTy(DAG.getDataLayout()));
3540 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurSDLoc(),
3541 TLI.getValueType(DAG.getDataLayout(), I.getType()),
3542 InVec, InVal, InIdx));
3543}
3544
3545void SelectionDAGBuilder::visitExtractElement(const User &I) {
3546 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3547 SDValue InVec = getValue(I.getOperand(0));
3548 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(1)), getCurSDLoc(),
3549 TLI.getVectorIdxTy(DAG.getDataLayout()));
3550 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(),
3551 TLI.getValueType(DAG.getDataLayout(), I.getType()),
3552 InVec, InIdx));
3553}
3554
3555void SelectionDAGBuilder::visitShuffleVector(const User &I) {
3556 SDValue Src1 = getValue(I.getOperand(0));
3557 SDValue Src2 = getValue(I.getOperand(1));
3558 SDLoc DL = getCurSDLoc();
3559
3560 SmallVector<int, 8> Mask;
3561 ShuffleVectorInst::getShuffleMask(cast<Constant>(I.getOperand(2)), Mask);
3562 unsigned MaskNumElts = Mask.size();
3563
3564 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3565 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
3566 EVT SrcVT = Src1.getValueType();
3567 unsigned SrcNumElts = SrcVT.getVectorNumElements();
3568
3569 if (SrcNumElts == MaskNumElts) {
3570 setValue(&I, DAG.getVectorShuffle(VT, DL, Src1, Src2, Mask));
3571 return;
3572 }
3573
3574 // Normalize the shuffle vector since mask and vector length don't match.
3575 if (SrcNumElts < MaskNumElts) {
3576 // Mask is longer than the source vectors. We can use concatenate vector to
3577 // make the mask and vectors lengths match.
3578
3579 if (MaskNumElts % SrcNumElts == 0) {
3580 // Mask length is a multiple of the source vector length.
3581 // Check if the shuffle is some kind of concatenation of the input
3582 // vectors.
3583 unsigned NumConcat = MaskNumElts / SrcNumElts;
3584 bool IsConcat = true;
3585 SmallVector<int, 8> ConcatSrcs(NumConcat, -1);
3586 for (unsigned i = 0; i != MaskNumElts; ++i) {
3587 int Idx = Mask[i];
3588 if (Idx < 0)
3589 continue;
3590 // Ensure the indices in each SrcVT sized piece are sequential and that
3591 // the same source is used for the whole piece.
3592 if ((Idx % SrcNumElts != (i % SrcNumElts)) ||
3593 (ConcatSrcs[i / SrcNumElts] >= 0 &&
3594 ConcatSrcs[i / SrcNumElts] != (int)(Idx / SrcNumElts))) {
3595 IsConcat = false;
3596 break;
3597 }
3598 // Remember which source this index came from.
3599 ConcatSrcs[i / SrcNumElts] = Idx / SrcNumElts;
3600 }
3601
3602 // The shuffle is concatenating multiple vectors together. Just emit
3603 // a CONCAT_VECTORS operation.
3604 if (IsConcat) {
3605 SmallVector<SDValue, 8> ConcatOps;
3606 for (auto Src : ConcatSrcs) {
3607 if (Src < 0)
3608 ConcatOps.push_back(DAG.getUNDEF(SrcVT));
3609 else if (Src == 0)
3610 ConcatOps.push_back(Src1);
3611 else
3612 ConcatOps.push_back(Src2);
3613 }
3614 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, ConcatOps));
3615 return;
3616 }
3617 }
3618
3619 unsigned PaddedMaskNumElts = alignTo(MaskNumElts, SrcNumElts);
3620 unsigned NumConcat = PaddedMaskNumElts / SrcNumElts;
3621 EVT PaddedVT = EVT::getVectorVT(*DAG.getContext(), VT.getScalarType(),
3622 PaddedMaskNumElts);
3623
3624 // Pad both vectors with undefs to make them the same length as the mask.
3625 SDValue UndefVal = DAG.getUNDEF(SrcVT);
3626
3627 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
3628 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
3629 MOps1[0] = Src1;
3630 MOps2[0] = Src2;
3631
3632 Src1 = Src1.isUndef()
3633 ? DAG.getUNDEF(PaddedVT)
3634 : DAG.getNode(ISD::CONCAT_VECTORS, DL, PaddedVT, MOps1);
3635 Src2 = Src2.isUndef()
3636 ? DAG.getUNDEF(PaddedVT)
3637 : DAG.getNode(ISD::CONCAT_VECTORS, DL, PaddedVT, MOps2);
3638
3639 // Readjust mask for new input vector length.
3640 SmallVector<int, 8> MappedOps(PaddedMaskNumElts, -1);
3641 for (unsigned i = 0; i != MaskNumElts; ++i) {
3642 int Idx = Mask[i];
3643 if (Idx >= (int)SrcNumElts)
3644 Idx -= SrcNumElts - PaddedMaskNumElts;
3645 MappedOps[i] = Idx;
3646 }
3647
3648 SDValue Result = DAG.getVectorShuffle(PaddedVT, DL, Src1, Src2, MappedOps);
3649
3650 // If the concatenated vector was padded, extract a subvector with the
3651 // correct number of elements.
3652 if (MaskNumElts != PaddedMaskNumElts)
3653 Result = DAG.getNode(
3654 ISD::EXTRACT_SUBVECTOR, DL, VT, Result,
3655 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
3656
3657 setValue(&I, Result);
3658 return;
3659 }
3660
3661 if (SrcNumElts > MaskNumElts) {
3662 // Analyze the access pattern of the vector to see if we can extract
3663 // two subvectors and do the shuffle.
3664 int StartIdx[2] = { -1, -1 }; // StartIdx to extract from
3665 bool CanExtract = true;
3666 for (int Idx : Mask) {
3667 unsigned Input = 0;
3668 if (Idx < 0)
3669 continue;
3670
3671 if (Idx >= (int)SrcNumElts) {
3672 Input = 1;
3673 Idx -= SrcNumElts;
3674 }
3675
3676 // If all the indices come from the same MaskNumElts sized portion of
3677 // the sources we can use extract. Also make sure the extract wouldn't
3678 // extract past the end of the source.
3679 int NewStartIdx = alignDown(Idx, MaskNumElts);
3680 if (NewStartIdx + MaskNumElts > SrcNumElts ||
3681 (StartIdx[Input] >= 0 && StartIdx[Input] != NewStartIdx))
3682 CanExtract = false;
3683 // Make sure we always update StartIdx as we use it to track if all
3684 // elements are undef.
3685 StartIdx[Input] = NewStartIdx;
3686 }
3687
3688 if (StartIdx[0] < 0 && StartIdx[1] < 0) {
3689 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
3690 return;
3691 }
3692 if (CanExtract) {
3693 // Extract appropriate subvector and generate a vector shuffle
3694 for (unsigned Input = 0; Input < 2; ++Input) {
3695 SDValue &Src = Input == 0 ? Src1 : Src2;
3696 if (StartIdx[Input] < 0)
3697 Src = DAG.getUNDEF(VT);
3698 else {
3699 Src = DAG.getNode(
3700 ISD::EXTRACT_SUBVECTOR, DL, VT, Src,
3701 DAG.getConstant(StartIdx[Input], DL,
3702 TLI.getVectorIdxTy(DAG.getDataLayout())));
3703 }
3704 }
3705
3706 // Calculate new mask.
3707 SmallVector<int, 8> MappedOps(Mask.begin(), Mask.end());
3708 for (int &Idx : MappedOps) {
3709 if (Idx >= (int)SrcNumElts)
3710 Idx -= SrcNumElts + StartIdx[1] - MaskNumElts;
3711 else if (Idx >= 0)
3712 Idx -= StartIdx[0];
3713 }
3714
3715 setValue(&I, DAG.getVectorShuffle(VT, DL, Src1, Src2, MappedOps));
3716 return;
3717 }
3718 }
3719
3720 // We can't use either concat vectors or extract subvectors so fall back to
3721 // replacing the shuffle with extract and build vector.
3722 // to insert and build vector.
3723 EVT EltVT = VT.getVectorElementType();
3724 EVT IdxVT = TLI.getVectorIdxTy(DAG.getDataLayout());
3725 SmallVector<SDValue,8> Ops;
3726 for (int Idx : Mask) {
3727 SDValue Res;
3728
3729 if (Idx < 0) {
3730 Res = DAG.getUNDEF(EltVT);
3731 } else {
3732 SDValue &Src = Idx < (int)SrcNumElts ? Src1 : Src2;
3733 if (Idx >= (int)SrcNumElts) Idx -= SrcNumElts;
3734
3735 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
3736 EltVT, Src, DAG.getConstant(Idx, DL, IdxVT));
3737 }
3738
3739 Ops.push_back(Res);
3740 }
3741
3742 setValue(&I, DAG.getBuildVector(VT, DL, Ops));
3743}
3744
3745void SelectionDAGBuilder::visitInsertValue(const User &I) {
3746 ArrayRef<unsigned> Indices;
3747 if (const InsertValueInst *IV = dyn_cast<InsertValueInst>(&I))
3748 Indices = IV->getIndices();
3749 else
3750 Indices = cast<ConstantExpr>(&I)->getIndices();
3751
3752 const Value *Op0 = I.getOperand(0);
3753 const Value *Op1 = I.getOperand(1);
3754 Type *AggTy = I.getType();
3755 Type *ValTy = Op1->getType();
3756 bool IntoUndef = isa<UndefValue>(Op0);
3757 bool FromUndef = isa<UndefValue>(Op1);
3758
3759 unsigned LinearIndex = ComputeLinearIndex(AggTy, Indices);
3760
3761 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3762 SmallVector<EVT, 4> AggValueVTs;
3763 ComputeValueVTs(TLI, DAG.getDataLayout(), AggTy, AggValueVTs);
3764 SmallVector<EVT, 4> ValValueVTs;
3765 ComputeValueVTs(TLI, DAG.getDataLayout(), ValTy, ValValueVTs);
3766
3767 unsigned NumAggValues = AggValueVTs.size();
3768 unsigned NumValValues = ValValueVTs.size();
3769 SmallVector<SDValue, 4> Values(NumAggValues);
3770
3771 // Ignore an insertvalue that produces an empty object
3772 if (!NumAggValues) {
3773 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
3774 return;
3775 }
3776
3777 SDValue Agg = getValue(Op0);
3778 unsigned i = 0;
3779 // Copy the beginning value(s) from the original aggregate.
3780 for (; i != LinearIndex; ++i)
3781 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3782 SDValue(Agg.getNode(), Agg.getResNo() + i);
3783 // Copy values from the inserted value(s).
3784 if (NumValValues) {
3785 SDValue Val = getValue(Op1);
3786 for (; i != LinearIndex + NumValValues; ++i)
3787 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3788 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
3789 }
3790 // Copy remaining value(s) from the original aggregate.
3791 for (; i != NumAggValues; ++i)
3792 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3793 SDValue(Agg.getNode(), Agg.getResNo() + i);
3794
3795 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
3796 DAG.getVTList(AggValueVTs), Values));
3797}
3798
3799void SelectionDAGBuilder::visitExtractValue(const User &I) {
3800 ArrayRef<unsigned> Indices;
3801 if (const ExtractValueInst *EV = dyn_cast<ExtractValueInst>(&I))
3802 Indices = EV->getIndices();
3803 else
3804 Indices = cast<ConstantExpr>(&I)->getIndices();
3805
3806 const Value *Op0 = I.getOperand(0);
3807 Type *AggTy = Op0->getType();
3808 Type *ValTy = I.getType();
3809 bool OutOfUndef = isa<UndefValue>(Op0);
3810
3811 unsigned LinearIndex = ComputeLinearIndex(AggTy, Indices);
3812
3813 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3814 SmallVector<EVT, 4> ValValueVTs;
3815 ComputeValueVTs(TLI, DAG.getDataLayout(), ValTy, ValValueVTs);
3816
3817 unsigned NumValValues = ValValueVTs.size();
3818
3819 // Ignore a extractvalue that produces an empty object
3820 if (!NumValValues) {
3821 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
3822 return;
3823 }
3824
3825 SmallVector<SDValue, 4> Values(NumValValues);
3826
3827 SDValue Agg = getValue(Op0);
3828 // Copy out the selected value(s).
3829 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
3830 Values[i - LinearIndex] =
3831 OutOfUndef ?
3832 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
3833 SDValue(Agg.getNode(), Agg.getResNo() + i);
3834
3835 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
3836 DAG.getVTList(ValValueVTs), Values));
3837}
3838
3839void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
3840 Value *Op0 = I.getOperand(0);
3841 // Note that the pointer operand may be a vector of pointers. Take the scalar
3842 // element which holds a pointer.
3843 unsigned AS = Op0->getType()->getScalarType()->getPointerAddressSpace();
3844 SDValue N = getValue(Op0);
3845 SDLoc dl = getCurSDLoc();
3846 auto &TLI = DAG.getTargetLoweringInfo();
3847 MVT PtrTy = TLI.getPointerTy(DAG.getDataLayout(), AS);
3848 MVT PtrMemTy = TLI.getPointerMemTy(DAG.getDataLayout(), AS);
3849
3850 // Normalize Vector GEP - all scalar operands should be converted to the
3851 // splat vector.
3852 unsigned VectorWidth = I.getType()->isVectorTy() ?
3853 cast<VectorType>(I.getType())->getVectorNumElements() : 0;
3854
3855 if (VectorWidth && !N.getValueType().isVector()) {
3856 LLVMContext &Context = *DAG.getContext();
3857 EVT VT = EVT::getVectorVT(Context, N.getValueType(), VectorWidth);
3858 N = DAG.getSplatBuildVector(VT, dl, N);
3859 }
3860
3861 for (gep_type_iterator GTI = gep_type_begin(&I), E = gep_type_end(&I);
3862 GTI != E; ++GTI) {
3863 const Value *Idx = GTI.getOperand();
3864 if (StructType *StTy = GTI.getStructTypeOrNull()) {
3865 unsigned Field = cast<Constant>(Idx)->getUniqueInteger().getZExtValue();
3866 if (Field) {
3867 // N = N + Offset
3868 uint64_t Offset = DL->getStructLayout(StTy)->getElementOffset(Field);
3869
3870 // In an inbounds GEP with an offset that is nonnegative even when
3871 // interpreted as signed, assume there is no unsigned overflow.
3872 SDNodeFlags Flags;
3873 if (int64_t(Offset) >= 0 && cast<GEPOperator>(I).isInBounds())
3874 Flags.setNoUnsignedWrap(true);
3875
3876 N = DAG.getNode(ISD::ADD, dl, N.getValueType(), N,
3877 DAG.getConstant(Offset, dl, N.getValueType()), Flags);
3878 }
3879 } else {
3880 unsigned IdxSize = DAG.getDataLayout().getIndexSizeInBits(AS);
3881 MVT IdxTy = MVT::getIntegerVT(IdxSize);
3882 APInt ElementSize(IdxSize, DL->getTypeAllocSize(GTI.getIndexedType()));
3883
3884 // If this is a scalar constant or a splat vector of constants,
3885 // handle it quickly.
3886 const auto *CI = dyn_cast<ConstantInt>(Idx);
3887 if (!CI && isa<ConstantDataVector>(Idx) &&
3888 cast<ConstantDataVector>(Idx)->getSplatValue())
3889 CI = cast<ConstantInt>(cast<ConstantDataVector>(Idx)->getSplatValue());
3890
3891 if (CI) {
3892 if (CI->isZero())
3893 continue;
3894 APInt Offs = ElementSize * CI->getValue().sextOrTrunc(IdxSize);
3895 LLVMContext &Context = *DAG.getContext();
3896 SDValue OffsVal = VectorWidth ?
3897 DAG.getConstant(Offs, dl, EVT::getVectorVT(Context, IdxTy, VectorWidth)) :
3898 DAG.getConstant(Offs, dl, IdxTy);
3899
3900 // In an inbouds GEP with an offset that is nonnegative even when
3901 // interpreted as signed, assume there is no unsigned overflow.
3902 SDNodeFlags Flags;
3903 if (Offs.isNonNegative() && cast<GEPOperator>(I).isInBounds())
3904 Flags.setNoUnsignedWrap(true);
3905
3906 OffsVal = DAG.getSExtOrTrunc(OffsVal, dl, N.getValueType());
3907
3908 N = DAG.getNode(ISD::ADD, dl, N.getValueType(), N, OffsVal, Flags);
3909 continue;
3910 }
3911
3912 // N = N + Idx * ElementSize;
3913 SDValue IdxN = getValue(Idx);
3914
3915 if (!IdxN.getValueType().isVector() && VectorWidth) {
3916 EVT VT = EVT::getVectorVT(*Context, IdxN.getValueType(), VectorWidth);
3917 IdxN = DAG.getSplatBuildVector(VT, dl, IdxN);
3918 }
3919
3920 // If the index is smaller or larger than intptr_t, truncate or extend
3921 // it.
3922 IdxN = DAG.getSExtOrTrunc(IdxN, dl, N.getValueType());
3923
3924 // If this is a multiply by a power of two, turn it into a shl
3925 // immediately. This is a very common case.
3926 if (ElementSize != 1) {
3927 if (ElementSize.isPowerOf2()) {
3928 unsigned Amt = ElementSize.logBase2();
3929 IdxN = DAG.getNode(ISD::SHL, dl,
3930 N.getValueType(), IdxN,
3931 DAG.getConstant(Amt, dl, IdxN.getValueType()));
3932 } else {
3933 SDValue Scale = DAG.getConstant(ElementSize.getZExtValue(), dl,
3934 IdxN.getValueType());
3935 IdxN = DAG.getNode(ISD::MUL, dl,
3936 N.getValueType(), IdxN, Scale);
3937 }
3938 }
3939
3940 N = DAG.getNode(ISD::ADD, dl,
3941 N.getValueType(), N, IdxN);
3942 }
3943 }
3944
3945 if (PtrMemTy != PtrTy && !cast<GEPOperator>(I).isInBounds())
3946 N = DAG.getPtrExtendInReg(N, dl, PtrMemTy);
3947
3948 setValue(&I, N);
3949}
3950
3951void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
3952 // If this is a fixed sized alloca in the entry block of the function,
3953 // allocate it statically on the stack.
3954 if (FuncInfo.StaticAllocaMap.count(&I))
3955 return; // getValue will auto-populate this.
3956
3957 SDLoc dl = getCurSDLoc();
3958 Type *Ty = I.getAllocatedType();
3959 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3960 auto &DL = DAG.getDataLayout();
3961 uint64_t TySize = DL.getTypeAllocSize(Ty);
3962 unsigned Align =
3963 std::max((unsigned)DL.getPrefTypeAlignment(Ty), I.getAlignment());
3964
3965 SDValue AllocSize = getValue(I.getArraySize());
3966
3967 EVT IntPtr = TLI.getPointerTy(DAG.getDataLayout(), DL.getAllocaAddrSpace());
3968 if (AllocSize.getValueType() != IntPtr)
3969 AllocSize = DAG.getZExtOrTrunc(AllocSize, dl, IntPtr);
3970
3971 AllocSize = DAG.getNode(ISD::MUL, dl, IntPtr,
3972 AllocSize,
3973 DAG.getConstant(TySize, dl, IntPtr));
3974
3975 // Handle alignment. If the requested alignment is less than or equal to
3976 // the stack alignment, ignore it. If the size is greater than or equal to
3977 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
3978 unsigned StackAlign =
3979 DAG.getSubtarget().getFrameLowering()->getStackAlignment();
3980 if (Align <= StackAlign)
3981 Align = 0;
3982
3983 // Round the size of the allocation up to the stack alignment size
3984 // by add SA-1 to the size. This doesn't overflow because we're computing
3985 // an address inside an alloca.
3986 SDNodeFlags Flags;
3987 Flags.setNoUnsignedWrap(true);
3988 AllocSize = DAG.getNode(ISD::ADD, dl, AllocSize.getValueType(), AllocSize,
3989 DAG.getConstant(StackAlign - 1, dl, IntPtr), Flags);
3990
3991 // Mask out the low bits for alignment purposes.
3992 AllocSize =
3993 DAG.getNode(ISD::AND, dl, AllocSize.getValueType(), AllocSize,
3994 DAG.getConstant(~(uint64_t)(StackAlign - 1), dl, IntPtr));
3995
3996 SDValue Ops[] = {getRoot(), AllocSize, DAG.getConstant(Align, dl, IntPtr)};
3997 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
3998 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, dl, VTs, Ops);
3999 setValue(&I, DSA);
4000 DAG.setRoot(DSA.getValue(1));
4001
4002 assert(FuncInfo.MF->getFrameInfo().hasVarSizedObjects())((FuncInfo.MF->getFrameInfo().hasVarSizedObjects()) ? static_cast
<void> (0) : __assert_fail ("FuncInfo.MF->getFrameInfo().hasVarSizedObjects()"
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 4002, __PRETTY_FUNCTION__))
;
4003}
4004
4005void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
4006 if (I.isAtomic())
4007 return visitAtomicLoad(I);
4008
4009 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4010 const Value *SV = I.getOperand(0);
4011 if (TLI.supportSwiftError()) {
4012 // Swifterror values can come from either a function parameter with
4013 // swifterror attribute or an alloca with swifterror attribute.
4014 if (const Argument *Arg = dyn_cast<Argument>(SV)) {
4015 if (Arg->hasSwiftErrorAttr())
4016 return visitLoadFromSwiftError(I);
4017 }
4018
4019 if (const AllocaInst *Alloca = dyn_cast<AllocaInst>(SV)) {
4020 if (Alloca->isSwiftError())
4021 return visitLoadFromSwiftError(I);
4022 }
4023 }
4024
4025 SDValue Ptr = getValue(SV);
4026
4027 Type *Ty = I.getType();
4028
4029 bool isVolatile = I.isVolatile();
4030 bool isNonTemporal = I.getMetadata(LLVMContext::MD_nontemporal) != nullptr;
4031 bool isInvariant = I.getMetadata(LLVMContext::MD_invariant_load) != nullptr;
4032 bool isDereferenceable = isDereferenceablePointer(SV, DAG.getDataLayout());
4033 unsigned Alignment = I.getAlignment();
4034
4035 AAMDNodes AAInfo;
4036 I.getAAMetadata(AAInfo);
4037 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
4038
4039 SmallVector<EVT, 4> ValueVTs, MemVTs;
4040 SmallVector<uint64_t, 4> Offsets;
4041 ComputeValueVTs(TLI, DAG.getDataLayout(), Ty, ValueVTs, &MemVTs, &Offsets);
4042 unsigned NumValues = ValueVTs.size();
4043 if (NumValues == 0)
4044 return;
4045
4046 SDValue Root;
4047 bool ConstantMemory = false;
4048 if (isVolatile || NumValues > MaxParallelChains)
4049 // Serialize volatile loads with other side effects.
4050 Root = getRoot();
4051 else if (AA &&
4052 AA->pointsToConstantMemory(MemoryLocation(
4053 SV,
4054 LocationSize::precise(DAG.getDataLayout().getTypeStoreSize(Ty)),
4055 AAInfo))) {
4056 // Do not serialize (non-volatile) loads of constant memory with anything.
4057 Root = DAG.getEntryNode();
4058 ConstantMemory = true;
4059 } else {
4060 // Do not serialize non-volatile loads against each other.
4061 Root = DAG.getRoot();
4062 }
4063
4064 SDLoc dl = getCurSDLoc();
4065
4066 if (isVolatile)
4067 Root = TLI.prepareVolatileOrAtomicLoad(Root, dl, DAG);
4068
4069 // An aggregate load cannot wrap around the address space, so offsets to its
4070 // parts don't wrap either.
4071 SDNodeFlags Flags;
4072 Flags.setNoUnsignedWrap(true);
4073
4074 SmallVector<SDValue, 4> Values(NumValues);
4075 SmallVector<SDValue, 4> Chains(std::min(MaxParallelChains, NumValues));
4076 EVT PtrVT = Ptr.getValueType();
4077 unsigned ChainI = 0;
4078 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
4079 // Serializing loads here may result in excessive register pressure, and
4080 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling
4081 // could recover a bit by hoisting nodes upward in the chain by recognizing
4082 // they are side-effect free or do not alias. The optimizer should really
4083 // avoid this case by converting large object/array copies to llvm.memcpy
4084 // (MaxParallelChains should always remain as failsafe).
4085 if (ChainI == MaxParallelChains) {
4086 assert(PendingLoads.empty() && "PendingLoads must be serialized first")((PendingLoads.empty() && "PendingLoads must be serialized first"
) ? static_cast<void> (0) : __assert_fail ("PendingLoads.empty() && \"PendingLoads must be serialized first\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 4086, __PRETTY_FUNCTION__))
;
4087 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
4088 makeArrayRef(Chains.data(), ChainI));
4089 Root = Chain;
4090 ChainI = 0;
4091 }
4092 SDValue A = DAG.getNode(ISD::ADD, dl,
4093 PtrVT, Ptr,
4094 DAG.getConstant(Offsets[i], dl, PtrVT),
4095 Flags);
4096 auto MMOFlags = MachineMemOperand::MONone;
4097 if (isVolatile)
4098 MMOFlags |= MachineMemOperand::MOVolatile;
4099 if (isNonTemporal)
4100 MMOFlags |= MachineMemOperand::MONonTemporal;
4101 if (isInvariant)
4102 MMOFlags |= MachineMemOperand::MOInvariant;
4103 if (isDereferenceable)
4104 MMOFlags |= MachineMemOperand::MODereferenceable;
4105 MMOFlags |= TLI.getMMOFlags(I);
4106
4107 SDValue L = DAG.getLoad(MemVTs[i], dl, Root, A,
4108 MachinePointerInfo(SV, Offsets[i]), Alignment,
4109 MMOFlags, AAInfo, Ranges);
4110 Chains[ChainI] = L.getValue(1);
4111
4112 if (MemVTs[i] != ValueVTs[i])
4113 L = DAG.getZExtOrTrunc(L, dl, ValueVTs[i]);
4114
4115 Values[i] = L;
4116 }
4117
4118 if (!ConstantMemory) {
4119 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
4120 makeArrayRef(Chains.data(), ChainI));
4121 if (isVolatile)
4122 DAG.setRoot(Chain);
4123 else
4124 PendingLoads.push_back(Chain);
4125 }
4126
4127 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, dl,
4128 DAG.getVTList(ValueVTs), Values));
4129}
4130
4131void SelectionDAGBuilder::visitStoreToSwiftError(const StoreInst &I) {
4132 assert(DAG.getTargetLoweringInfo().supportSwiftError() &&((DAG.getTargetLoweringInfo().supportSwiftError() && "call visitStoreToSwiftError when backend supports swifterror"
) ? static_cast<void> (0) : __assert_fail ("DAG.getTargetLoweringInfo().supportSwiftError() && \"call visitStoreToSwiftError when backend supports swifterror\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 4133, __PRETTY_FUNCTION__))
4133 "call visitStoreToSwiftError when backend supports swifterror")((DAG.getTargetLoweringInfo().supportSwiftError() && "call visitStoreToSwiftError when backend supports swifterror"
) ? static_cast<void> (0) : __assert_fail ("DAG.getTargetLoweringInfo().supportSwiftError() && \"call visitStoreToSwiftError when backend supports swifterror\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 4133, __PRETTY_FUNCTION__))
;
4134
4135 SmallVector<EVT, 4> ValueVTs;
4136 SmallVector<uint64_t, 4> Offsets;
4137 const Value *SrcV = I.getOperand(0);
4138 ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(),
4139 SrcV->getType(), ValueVTs, &Offsets);
4140 assert(ValueVTs.size() == 1 && Offsets[0] == 0 &&((ValueVTs.size() == 1 && Offsets[0] == 0 && "expect a single EVT for swifterror"
) ? static_cast<void> (0) : __assert_fail ("ValueVTs.size() == 1 && Offsets[0] == 0 && \"expect a single EVT for swifterror\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 4141, __PRETTY_FUNCTION__))
4141 "expect a single EVT for swifterror")((ValueVTs.size() == 1 && Offsets[0] == 0 && "expect a single EVT for swifterror"
) ? static_cast<void> (0) : __assert_fail ("ValueVTs.size() == 1 && Offsets[0] == 0 && \"expect a single EVT for swifterror\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 4141, __PRETTY_FUNCTION__))
;
4142
4143 SDValue Src = getValue(SrcV);
4144 // Create a virtual register, then update the virtual register.
4145 unsigned VReg; bool CreatedVReg;
4146 std::tie(VReg, CreatedVReg) = FuncInfo.getOrCreateSwiftErrorVRegDefAt(&I);
4147 // Chain, DL, Reg, N or Chain, DL, Reg, N, Glue
4148 // Chain can be getRoot or getControlRoot.
4149 SDValue CopyNode = DAG.getCopyToReg(getRoot(), getCurSDLoc(), VReg,
4150 SDValue(Src.getNode(), Src.getResNo()));
4151 DAG.setRoot(CopyNode);
4152 if (CreatedVReg)
4153 FuncInfo.setCurrentSwiftErrorVReg(FuncInfo.MBB, I.getOperand(1), VReg);
4154}
4155
4156void SelectionDAGBuilder::visitLoadFromSwiftError(const LoadInst &I) {
4157 assert(DAG.getTargetLoweringInfo().supportSwiftError() &&((DAG.getTargetLoweringInfo().supportSwiftError() && "call visitLoadFromSwiftError when backend supports swifterror"
) ? static_cast<void> (0) : __assert_fail ("DAG.getTargetLoweringInfo().supportSwiftError() && \"call visitLoadFromSwiftError when backend supports swifterror\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 4158, __PRETTY_FUNCTION__))
4158 "call visitLoadFromSwiftError when backend supports swifterror")((DAG.getTargetLoweringInfo().supportSwiftError() && "call visitLoadFromSwiftError when backend supports swifterror"
) ? static_cast<void> (0) : __assert_fail ("DAG.getTargetLoweringInfo().supportSwiftError() && \"call visitLoadFromSwiftError when backend supports swifterror\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 4158, __PRETTY_FUNCTION__))
;
4159
4160 assert(!I.isVolatile() &&((!I.isVolatile() && I.getMetadata(LLVMContext::MD_nontemporal
) == nullptr && I.getMetadata(LLVMContext::MD_invariant_load
) == nullptr && "Support volatile, non temporal, invariant for load_from_swift_error"
) ? static_cast<void> (0) : __assert_fail ("!I.isVolatile() && I.getMetadata(LLVMContext::MD_nontemporal) == nullptr && I.getMetadata(LLVMContext::MD_invariant_load) == nullptr && \"Support volatile, non temporal, invariant for load_from_swift_error\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 4163, __PRETTY_FUNCTION__))
4161 I.getMetadata(LLVMContext::MD_nontemporal) == nullptr &&((!I.isVolatile() && I.getMetadata(LLVMContext::MD_nontemporal
) == nullptr && I.getMetadata(LLVMContext::MD_invariant_load
) == nullptr && "Support volatile, non temporal, invariant for load_from_swift_error"
) ? static_cast<void> (0) : __assert_fail ("!I.isVolatile() && I.getMetadata(LLVMContext::MD_nontemporal) == nullptr && I.getMetadata(LLVMContext::MD_invariant_load) == nullptr && \"Support volatile, non temporal, invariant for load_from_swift_error\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 4163, __PRETTY_FUNCTION__))
4162 I.getMetadata(LLVMContext::MD_invariant_load) == nullptr &&((!I.isVolatile() && I.getMetadata(LLVMContext::MD_nontemporal
) == nullptr && I.getMetadata(LLVMContext::MD_invariant_load
) == nullptr && "Support volatile, non temporal, invariant for load_from_swift_error"
) ? static_cast<void> (0) : __assert_fail ("!I.isVolatile() && I.getMetadata(LLVMContext::MD_nontemporal) == nullptr && I.getMetadata(LLVMContext::MD_invariant_load) == nullptr && \"Support volatile, non temporal, invariant for load_from_swift_error\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 4163, __PRETTY_FUNCTION__))
4163 "Support volatile, non temporal, invariant for load_from_swift_error")((!I.isVolatile() && I.getMetadata(LLVMContext::MD_nontemporal
) == nullptr && I.getMetadata(LLVMContext::MD_invariant_load
) == nullptr && "Support volatile, non temporal, invariant for load_from_swift_error"
) ? static_cast<void> (0) : __assert_fail ("!I.isVolatile() && I.getMetadata(LLVMContext::MD_nontemporal) == nullptr && I.getMetadata(LLVMContext::MD_invariant_load) == nullptr && \"Support volatile, non temporal, invariant for load_from_swift_error\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 4163, __PRETTY_FUNCTION__))
;
4164
4165 const Value *SV = I.getOperand(0);
4166 Type *Ty = I.getType();
4167 AAMDNodes AAInfo;
4168 I.getAAMetadata(AAInfo);
4169 assert((((!AA || !AA->pointsToConstantMemory(MemoryLocation( SV, LocationSize
::precise(DAG.getDataLayout().getTypeStoreSize(Ty)), AAInfo))
) && "load_from_swift_error should not be constant memory"
) ? static_cast<void> (0) : __assert_fail ("(!AA || !AA->pointsToConstantMemory(MemoryLocation( SV, LocationSize::precise(DAG.getDataLayout().getTypeStoreSize(Ty)), AAInfo))) && \"load_from_swift_error should not be constant memory\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 4174, __PRETTY_FUNCTION__))
4170 (!AA ||(((!AA || !AA->pointsToConstantMemory(MemoryLocation( SV, LocationSize
::precise(DAG.getDataLayout().getTypeStoreSize(Ty)), AAInfo))
) && "load_from_swift_error should not be constant memory"
) ? static_cast<void> (0) : __assert_fail ("(!AA || !AA->pointsToConstantMemory(MemoryLocation( SV, LocationSize::precise(DAG.getDataLayout().getTypeStoreSize(Ty)), AAInfo))) && \"load_from_swift_error should not be constant memory\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 4174, __PRETTY_FUNCTION__))
4171 !AA->pointsToConstantMemory(MemoryLocation((((!AA || !AA->pointsToConstantMemory(MemoryLocation( SV, LocationSize
::precise(DAG.getDataLayout().getTypeStoreSize(Ty)), AAInfo))
) && "load_from_swift_error should not be constant memory"
) ? static_cast<void> (0) : __assert_fail ("(!AA || !AA->pointsToConstantMemory(MemoryLocation( SV, LocationSize::precise(DAG.getDataLayout().getTypeStoreSize(Ty)), AAInfo))) && \"load_from_swift_error should not be constant memory\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 4174, __PRETTY_FUNCTION__))
4172 SV, LocationSize::precise(DAG.getDataLayout().getTypeStoreSize(Ty)),(((!AA || !AA->pointsToConstantMemory(MemoryLocation( SV, LocationSize
::precise(DAG.getDataLayout().getTypeStoreSize(Ty)), AAInfo))
) && "load_from_swift_error should not be constant memory"
) ? static_cast<void> (0) : __assert_fail ("(!AA || !AA->pointsToConstantMemory(MemoryLocation( SV, LocationSize::precise(DAG.getDataLayout().getTypeStoreSize(Ty)), AAInfo))) && \"load_from_swift_error should not be constant memory\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 4174, __PRETTY_FUNCTION__))
4173 AAInfo))) &&(((!AA || !AA->pointsToConstantMemory(MemoryLocation( SV, LocationSize
::precise(DAG.getDataLayout().getTypeStoreSize(Ty)), AAInfo))
) && "load_from_swift_error should not be constant memory"
) ? static_cast<void> (0) : __assert_fail ("(!AA || !AA->pointsToConstantMemory(MemoryLocation( SV, LocationSize::precise(DAG.getDataLayout().getTypeStoreSize(Ty)), AAInfo))) && \"load_from_swift_error should not be constant memory\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 4174, __PRETTY_FUNCTION__))
4174 "load_from_swift_error should not be constant memory")(((!AA || !AA->pointsToConstantMemory(MemoryLocation( SV, LocationSize
::precise(DAG.getDataLayout().getTypeStoreSize(Ty)), AAInfo))
) && "load_from_swift_error should not be constant memory"
) ? static_cast<void> (0) : __assert_fail ("(!AA || !AA->pointsToConstantMemory(MemoryLocation( SV, LocationSize::precise(DAG.getDataLayout().getTypeStoreSize(Ty)), AAInfo))) && \"load_from_swift_error should not be constant memory\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 4174, __PRETTY_FUNCTION__))
;
4175
4176 SmallVector<EVT, 4> ValueVTs;
4177 SmallVector<uint64_t, 4> Offsets;
4178 ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(), Ty,
4179 ValueVTs, &Offsets);
4180 assert(ValueVTs.size() == 1 && Offsets[0] == 0 &&((ValueVTs.size() == 1 && Offsets[0] == 0 && "expect a single EVT for swifterror"
) ? static_cast<void> (0) : __assert_fail ("ValueVTs.size() == 1 && Offsets[0] == 0 && \"expect a single EVT for swifterror\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 4181, __PRETTY_FUNCTION__))
4181 "expect a single EVT for swifterror")((ValueVTs.size() == 1 && Offsets[0] == 0 && "expect a single EVT for swifterror"
) ? static_cast<void> (0) : __assert_fail ("ValueVTs.size() == 1 && Offsets[0] == 0 && \"expect a single EVT for swifterror\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 4181, __PRETTY_FUNCTION__))
;
4182
4183 // Chain, DL, Reg, VT, Glue or Chain, DL, Reg, VT
4184 SDValue L = DAG.getCopyFromReg(
4185 getRoot(), getCurSDLoc(),
4186 FuncInfo.getOrCreateSwiftErrorVRegUseAt(&I, FuncInfo.MBB, SV).first,
4187 ValueVTs[0]);
4188
4189 setValue(&I, L);
4190}
4191
4192void SelectionDAGBuilder::visitStore(const StoreInst &I) {
4193 if (I.isAtomic())
4194 return visitAtomicStore(I);
4195
4196 const Value *SrcV = I.getOperand(0);
4197 const Value *PtrV = I.getOperand(1);
4198
4199 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4200 if (TLI.supportSwiftError()) {
4201 // Swifterror values can come from either a function parameter with
4202 // swifterror attribute or an alloca with swifterror attribute.
4203 if (const Argument *Arg = dyn_cast<Argument>(PtrV)) {
4204 if (Arg->hasSwiftErrorAttr())
4205 return visitStoreToSwiftError(I);
4206 }
4207
4208 if (const AllocaInst *Alloca = dyn_cast<AllocaInst>(PtrV)) {
4209 if (Alloca->isSwiftError())
4210 return visitStoreToSwiftError(I);
4211 }
4212 }
4213
4214 SmallVector<EVT, 4> ValueVTs, MemVTs;
4215 SmallVector<uint64_t, 4> Offsets;
4216 ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(),
4217 SrcV->getType(), ValueVTs, &MemVTs, &Offsets);
4218 unsigned NumValues = ValueVTs.size();
4219 if (NumValues == 0)
4220 return;
4221
4222 // Get the lowered operands. Note that we do this after
4223 // checking if NumResults is zero, because with zero results
4224 // the operands won't have values in the map.
4225 SDValue Src = getValue(SrcV);
4226 SDValue Ptr = getValue(PtrV);
4227
4228 SDValue Root = getRoot();
4229 SmallVector<SDValue, 4> Chains(std::min(MaxParallelChains, NumValues));
4230 SDLoc dl = getCurSDLoc();
4231 EVT PtrVT = Ptr.getValueType();
4232 unsigned Alignment = I.getAlignment();
4233 AAMDNodes AAInfo;
4234 I.getAAMetadata(AAInfo);
4235
4236 auto MMOFlags = MachineMemOperand::MONone;
4237 if (I.isVolatile())
4238 MMOFlags |= MachineMemOperand::MOVolatile;
4239 if (I.getMetadata(LLVMContext::MD_nontemporal) != nullptr)
4240 MMOFlags |= MachineMemOperand::MONonTemporal;
4241 MMOFlags |= TLI.getMMOFlags(I);
4242
4243 // An aggregate load cannot wrap around the address space, so offsets to its
4244 // parts don't wrap either.
4245 SDNodeFlags Flags;
4246 Flags.setNoUnsignedWrap(true);
4247
4248 unsigned ChainI = 0;
4249 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
4250 // See visitLoad comments.
4251 if (ChainI == MaxParallelChains) {
4252 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
4253 makeArrayRef(Chains.data(), ChainI));
4254 Root = Chain;
4255 ChainI = 0;
4256 }
4257 SDValue Add = DAG.getNode(ISD::ADD, dl, PtrVT, Ptr,
4258 DAG.getConstant(Offsets[i], dl, PtrVT), Flags);
4259 SDValue Val = SDValue(Src.getNode(), Src.getResNo() + i);
4260 if (MemVTs[i] != ValueVTs[i])
4261 Val = DAG.getPtrExtOrTrunc(Val, dl, MemVTs[i]);
4262 SDValue St =
4263 DAG.getStore(Root, dl, Val, Add, MachinePointerInfo(PtrV, Offsets[i]),
4264 Alignment, MMOFlags, AAInfo);
4265 Chains[ChainI] = St;
4266 }
4267
4268 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
4269 makeArrayRef(Chains.data(), ChainI));
4270 DAG.setRoot(StoreNode);
4271}
4272
4273void SelectionDAGBuilder::visitMaskedStore(const CallInst &I,
4274 bool IsCompressing) {
4275 SDLoc sdl = getCurSDLoc();
4276
4277 auto getMaskedStoreOps = [&](Value* &Ptr, Value* &Mask, Value* &Src0,
4278 unsigned& Alignment) {
4279 // llvm.masked.store.*(Src0, Ptr, alignment, Mask)
4280 Src0 = I.getArgOperand(0);
4281 Ptr = I.getArgOperand(1);
4282 Alignment = cast<ConstantInt>(I.getArgOperand(2))->getZExtValue();
4283 Mask = I.getArgOperand(3);
4284 };
4285 auto getCompressingStoreOps = [&](Value* &Ptr, Value* &Mask, Value* &Src0,
4286 unsigned& Alignment) {
4287 // llvm.masked.compressstore.*(Src0, Ptr, Mask)
4288 Src0 = I.getArgOperand(0);
4289 Ptr = I.getArgOperand(1);
4290 Mask = I.getArgOperand(2);
4291 Alignment = 0;
4292 };
4293
4294 Value *PtrOperand, *MaskOperand, *Src0Operand;
4295 unsigned Alignment;
4296 if (IsCompressing)
4297 getCompressingStoreOps(PtrOperand, MaskOperand, Src0Operand, Alignment);
4298 else
4299 getMaskedStoreOps(PtrOperand, MaskOperand, Src0Operand, Alignment);
4300
4301 SDValue Ptr = getValue(PtrOperand);
4302 SDValue Src0 = getValue(Src0Operand);
4303 SDValue Mask = getValue(MaskOperand);
4304
4305 EVT VT = Src0.getValueType();
4306 if (!Alignment)
4307 Alignment = DAG.getEVTAlignment(VT);
4308
4309 AAMDNodes AAInfo;
4310 I.getAAMetadata(AAInfo);
4311
4312 MachineMemOperand *MMO =
4313 DAG.getMachineFunction().
4314 getMachineMemOperand(MachinePointerInfo(PtrOperand),
4315 MachineMemOperand::MOStore, VT.getStoreSize(),
4316 Alignment, AAInfo);
4317 SDValue StoreNode = DAG.getMaskedStore(getRoot(), sdl, Src0, Ptr, Mask, VT,
4318 MMO, false /* Truncating */,
4319 IsCompressing);
4320 DAG.setRoot(StoreNode);
4321 setValue(&I, StoreNode);
4322}
4323
4324// Get a uniform base for the Gather/Scatter intrinsic.
4325// The first argument of the Gather/Scatter intrinsic is a vector of pointers.
4326// We try to represent it as a base pointer + vector of indices.
4327// Usually, the vector of pointers comes from a 'getelementptr' instruction.
4328// The first operand of the GEP may be a single pointer or a vector of pointers
4329// Example:
4330// %gep.ptr = getelementptr i32, <8 x i32*> %vptr, <8 x i32> %ind
4331// or
4332// %gep.ptr = getelementptr i32, i32* %ptr, <8 x i32> %ind
4333// %res = call <8 x i32> @llvm.masked.gather.v8i32(<8 x i32*> %gep.ptr, ..
4334//
4335// When the first GEP operand is a single pointer - it is the uniform base we
4336// are looking for. If first operand of the GEP is a splat vector - we
4337// extract the splat value and use it as a uniform base.
4338// In all other cases the function returns 'false'.
4339static bool getUniformBase(const Value* &Ptr, SDValue& Base, SDValue& Index,
4340 SDValue &Scale, SelectionDAGBuilder* SDB) {
4341 SelectionDAG& DAG = SDB->DAG;
4342 LLVMContext &Context = *DAG.getContext();
4343
4344 assert(Ptr->getType()->isVectorTy() && "Uexpected pointer type")((Ptr->getType()->isVectorTy() && "Uexpected pointer type"
) ? static_cast<void> (0) : __assert_fail ("Ptr->getType()->isVectorTy() && \"Uexpected pointer type\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 4344, __PRETTY_FUNCTION__))
;
4345 const GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(Ptr);
4346 if (!GEP)
4347 return false;
4348
4349 const Value *GEPPtr = GEP->getPointerOperand();
4350 if (!GEPPtr->getType()->isVectorTy())
4351 Ptr = GEPPtr;
4352 else if (!(Ptr = getSplatValue(GEPPtr)))
4353 return false;
4354
4355 unsigned FinalIndex = GEP->getNumOperands() - 1;
4356 Value *IndexVal = GEP->getOperand(FinalIndex);
4357
4358 // Ensure all the other indices are 0.
4359 for (unsigned i = 1; i < FinalIndex; ++i) {
4360 auto *C = dyn_cast<ConstantInt>(GEP->getOperand(i));
4361 if (!C || !C->isZero())
4362 return false;
4363 }
4364
4365 // The operands of the GEP may be defined in another basic block.
4366 // In this case we'll not find nodes for the operands.
4367 if (!SDB->findValue(Ptr) || !SDB->findValue(IndexVal))
4368 return false;
4369
4370 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4371 const DataLayout &DL = DAG.getDataLayout();
4372 Scale = DAG.getTargetConstant(DL.getTypeAllocSize(GEP->getResultElementType()),
4373 SDB->getCurSDLoc(), TLI.getPointerTy(DL));
4374 Base = SDB->getValue(Ptr);
4375 Index = SDB->getValue(IndexVal);
4376
4377 if (!Index.getValueType().isVector()) {
4378 unsigned GEPWidth = GEP->getType()->getVectorNumElements();
4379 EVT VT = EVT::getVectorVT(Context, Index.getValueType(), GEPWidth);
4380 Index = DAG.getSplatBuildVector(VT, SDLoc(Index), Index);
4381 }
4382 return true;
4383}
4384
4385void SelectionDAGBuilder::visitMaskedScatter(const CallInst &I) {
4386 SDLoc sdl = getCurSDLoc();
4387
4388 // llvm.masked.scatter.*(Src0, Ptrs, alignemt, Mask)
4389 const Value *Ptr = I.getArgOperand(1);
4390 SDValue Src0 = getValue(I.getArgOperand(0));
4391 SDValue Mask = getValue(I.getArgOperand(3));
4392 EVT VT = Src0.getValueType();
4393 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(2)))->getZExtValue();
4394 if (!Alignment)
4395 Alignment = DAG.getEVTAlignment(VT);
4396 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4397
4398 AAMDNodes AAInfo;
4399 I.getAAMetadata(AAInfo);
4400
4401 SDValue Base;
4402 SDValue Index;
4403 SDValue Scale;
4404 const Value *BasePtr = Ptr;
4405 bool UniformBase = getUniformBase(BasePtr, Base, Index, Scale, this);
4406
4407 const Value *MemOpBasePtr = UniformBase ? BasePtr : nullptr;
4408 MachineMemOperand *MMO = DAG.getMachineFunction().
4409 getMachineMemOperand(MachinePointerInfo(MemOpBasePtr),
4410 MachineMemOperand::MOStore, VT.getStoreSize(),
4411 Alignment, AAInfo);
4412 if (!UniformBase) {
4413 Base = DAG.getConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout()));
4414 Index = getValue(Ptr);
4415 Scale = DAG.getTargetConstant(1, sdl, TLI.getPointerTy(DAG.getDataLayout()));
4416 }
4417 SDValue Ops[] = { getRoot(), Src0, Mask, Base, Index, Scale };
4418 SDValue Scatter = DAG.getMaskedScatter(DAG.getVTList(MVT::Other), VT, sdl,
4419 Ops, MMO);
4420 DAG.setRoot(Scatter);
4421 setValue(&I, Scatter);
4422}
4423
4424void SelectionDAGBuilder::visitMaskedLoad(const CallInst &I, bool IsExpanding) {
4425 SDLoc sdl = getCurSDLoc();
4426
4427 auto getMaskedLoadOps = [&](Value* &Ptr, Value* &Mask, Value* &Src0,
4428 unsigned& Alignment) {
4429 // @llvm.masked.load.*(Ptr, alignment, Mask, Src0)
4430 Ptr = I.getArgOperand(0);
4431 Alignment = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
4432 Mask = I.getArgOperand(2);
4433 Src0 = I.getArgOperand(3);
4434 };
4435 auto getExpandingLoadOps = [&](Value* &Ptr, Value* &Mask, Value* &Src0,
4436 unsigned& Alignment) {
4437 // @llvm.masked.expandload.*(Ptr, Mask, Src0)
4438 Ptr = I.getArgOperand(0);
4439 Alignment = 0;
4440 Mask = I.getArgOperand(1);
4441 Src0 = I.getArgOperand(2);
4442 };
4443
4444 Value *PtrOperand, *MaskOperand, *Src0Operand;
4445 unsigned Alignment;
4446 if (IsExpanding)
4447 getExpandingLoadOps(PtrOperand, MaskOperand, Src0Operand, Alignment);
4448 else
4449 getMaskedLoadOps(PtrOperand, MaskOperand, Src0Operand, Alignment);
4450
4451 SDValue Ptr = getValue(PtrOperand);
4452 SDValue Src0 = getValue(Src0Operand);
4453 SDValue Mask = getValue(MaskOperand);
4454
4455 EVT VT = Src0.getValueType();
4456 if (!Alignment)
4457 Alignment = DAG.getEVTAlignment(VT);
4458
4459 AAMDNodes AAInfo;
4460 I.getAAMetadata(AAInfo);
4461 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
4462
4463 // Do not serialize masked loads of constant memory with anything.
4464 bool AddToChain =
4465 !AA || !AA->pointsToConstantMemory(MemoryLocation(
4466 PtrOperand,
4467 LocationSize::precise(
4468 DAG.getDataLayout().getTypeStoreSize(I.getType())),
4469 AAInfo));
4470 SDValue InChain = AddToChain ? DAG.getRoot() : DAG.getEntryNode();
4471
4472 MachineMemOperand *MMO =
4473 DAG.getMachineFunction().
4474 getMachineMemOperand(MachinePointerInfo(PtrOperand),
4475 MachineMemOperand::MOLoad, VT.getStoreSize(),
4476 Alignment, AAInfo, Ranges);
4477
4478 SDValue Load = DAG.getMaskedLoad(VT, sdl, InChain, Ptr, Mask, Src0, VT, MMO,
4479 ISD::NON_EXTLOAD, IsExpanding);
4480 if (AddToChain)
4481 PendingLoads.push_back(Load.getValue(1));
4482 setValue(&I, Load);
4483}
4484
4485void SelectionDAGBuilder::visitMaskedGather(const CallInst &I) {
4486 SDLoc sdl = getCurSDLoc();
4487
4488 // @llvm.masked.gather.*(Ptrs, alignment, Mask, Src0)
4489 const Value *Ptr = I.getArgOperand(0);
4490 SDValue Src0 = getValue(I.getArgOperand(3));
4491 SDValue Mask = getValue(I.getArgOperand(2));
4492
4493 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4494 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4495 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(1)))->getZExtValue();
4496 if (!Alignment)
4497 Alignment = DAG.getEVTAlignment(VT);
4498
4499 AAMDNodes AAInfo;
4500 I.getAAMetadata(AAInfo);
4501 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
4502
4503 SDValue Root = DAG.getRoot();
4504 SDValue Base;
4505 SDValue Index;
4506 SDValue Scale;
4507 const Value *BasePtr = Ptr;
4508 bool UniformBase = getUniformBase(BasePtr, Base, Index, Scale, this);
4509 bool ConstantMemory = false;
4510 if (UniformBase && AA &&
4511 AA->pointsToConstantMemory(
4512 MemoryLocation(BasePtr,
4513 LocationSize::precise(
4514 DAG.getDataLayout().getTypeStoreSize(I.getType())),
4515 AAInfo))) {
4516 // Do not serialize (non-volatile) loads of constant memory with anything.
4517 Root = DAG.getEntryNode();
4518 ConstantMemory = true;
4519 }
4520
4521 MachineMemOperand *MMO =
4522 DAG.getMachineFunction().
4523 getMachineMemOperand(MachinePointerInfo(UniformBase ? BasePtr : nullptr),
4524 MachineMemOperand::MOLoad, VT.getStoreSize(),
4525 Alignment, AAInfo, Ranges);
4526
4527 if (!UniformBase) {
4528 Base = DAG.getConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout()));
4529 Index = getValue(Ptr);
4530 Scale = DAG.getTargetConstant(1, sdl, TLI.getPointerTy(DAG.getDataLayout()));
4531 }
4532 SDValue Ops[] = { Root, Src0, Mask, Base, Index, Scale };
4533 SDValue Gather = DAG.getMaskedGather(DAG.getVTList(VT, MVT::Other), VT, sdl,
4534 Ops, MMO);
4535
4536 SDValue OutChain = Gather.getValue(1);
4537 if (!ConstantMemory)
4538 PendingLoads.push_back(OutChain);
4539 setValue(&I, Gather);
4540}
4541
4542void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) {
4543 SDLoc dl = getCurSDLoc();
4544 AtomicOrdering SuccessOrdering = I.getSuccessOrdering();
4545 AtomicOrdering FailureOrdering = I.getFailureOrdering();
4546 SyncScope::ID SSID = I.getSyncScopeID();
4547
4548 SDValue InChain = getRoot();
4549
4550 MVT MemVT = getValue(I.getCompareOperand()).getSimpleValueType();
4551 SDVTList VTs = DAG.getVTList(MemVT, MVT::i1, MVT::Other);
4552
4553 auto Alignment = DAG.getEVTAlignment(MemVT);
4554
4555 auto Flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore;
4556 if (I.isVolatile())
4557 Flags |= MachineMemOperand::MOVolatile;
4558 Flags |= DAG.getTargetLoweringInfo().getMMOFlags(I);
4559
4560 MachineFunction &MF = DAG.getMachineFunction();
4561 MachineMemOperand *MMO =
4562 MF.getMachineMemOperand(MachinePointerInfo(I.getPointerOperand()),
4563 Flags, MemVT.getStoreSize(), Alignment,
4564 AAMDNodes(), nullptr, SSID, SuccessOrdering,
4565 FailureOrdering);
4566
4567 SDValue L = DAG.getAtomicCmpSwap(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS,
4568 dl, MemVT, VTs, InChain,
4569 getValue(I.getPointerOperand()),
4570 getValue(I.getCompareOperand()),
4571 getValue(I.getNewValOperand()), MMO);
4572
4573 SDValue OutChain = L.getValue(2);
4574
4575 setValue(&I, L);
4576 DAG.setRoot(OutChain);
4577}
4578
4579void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) {
4580 SDLoc dl = getCurSDLoc();
4581 ISD::NodeType NT;
4582 switch (I.getOperation()) {
4583 default: llvm_unreachable("Unknown atomicrmw operation")::llvm::llvm_unreachable_internal("Unknown atomicrmw operation"
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 4583)
;
4584 case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break;
4585 case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break;
4586 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break;
4587 case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break;
4588 case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break;
4589 case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break;
4590 case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break;
4591 case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break;
4592 case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break;
4593 case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break;
4594 case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break;
4595 case AtomicRMWInst::FAdd: NT = ISD::ATOMIC_LOAD_FADD; break;
4596 case AtomicRMWInst::FSub: NT = ISD::ATOMIC_LOAD_FSUB; break;
4597 }
4598 AtomicOrdering Ordering = I.getOrdering();
4599 SyncScope::ID SSID = I.getSyncScopeID();
4600
4601 SDValue InChain = getRoot();
4602
4603 auto MemVT = getValue(I.getValOperand()).getSimpleValueType();
4604 auto Alignment = DAG.getEVTAlignment(MemVT);
4605
4606 auto Flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore;
4607 if (I.isVolatile())
4608 Flags |= MachineMemOperand::MOVolatile;
4609 Flags |= DAG.getTargetLoweringInfo().getMMOFlags(I);
4610
4611 MachineFunction &MF = DAG.getMachineFunction();
4612 MachineMemOperand *MMO =
4613 MF.getMachineMemOperand(MachinePointerInfo(I.getPointerOperand()), Flags,
4614 MemVT.getStoreSize(), Alignment, AAMDNodes(),
4615 nullptr, SSID, Ordering);
4616
4617 SDValue L =
4618 DAG.getAtomic(NT, dl, MemVT, InChain,
4619 getValue(I.getPointerOperand()), getValue(I.getValOperand()),
4620 MMO);
4621
4622 SDValue OutChain = L.getValue(1);
4623
4624 setValue(&I, L);
4625 DAG.setRoot(OutChain);
4626}
4627
4628void SelectionDAGBuilder::visitFence(const FenceInst &I) {
4629 SDLoc dl = getCurSDLoc();
4630 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4631 SDValue Ops[3];
4632 Ops[0] = getRoot();
4633 Ops[1] = DAG.getConstant((unsigned)I.getOrdering(), dl,
4634 TLI.getFenceOperandTy(DAG.getDataLayout()));
4635 Ops[2] = DAG.getConstant(I.getSyncScopeID(), dl,
4636 TLI.getFenceOperandTy(DAG.getDataLayout()));
4637 DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops));
4638}
4639
4640void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) {
4641 SDLoc dl = getCurSDLoc();
4642 AtomicOrdering Order = I.getOrdering();
4643 SyncScope::ID SSID = I.getSyncScopeID();
4644
4645 SDValue InChain = getRoot();
4646
4647 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4648 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4649 EVT MemVT = TLI.getMemValueType(DAG.getDataLayout(), I.getType());
4650
4651 if (!TLI.supportsUnalignedAtomics() &&
4652 I.getAlignment() < MemVT.getSizeInBits() / 8)
4653 report_fatal_error("Cannot generate unaligned atomic load");
4654
4655 auto Flags = MachineMemOperand::MOLoad;
4656 if (I.isVolatile())
4657 Flags |= MachineMemOperand::MOVolatile;
4658 if (I.getMetadata(LLVMContext::MD_invariant_load) != nullptr)
4659 Flags |= MachineMemOperand::MOInvariant;
4660 if (isDereferenceablePointer(I.getPointerOperand(), DAG.getDataLayout()))
4661 Flags |= MachineMemOperand::MODereferenceable;
4662
4663 Flags |= TLI.getMMOFlags(I);
4664
4665 MachineMemOperand *MMO =
4666 DAG.getMachineFunction().
4667 getMachineMemOperand(MachinePointerInfo(I.getPointerOperand()),
4668 Flags, MemVT.getStoreSize(),
4669 I.getAlignment() ? I.getAlignment() :
4670 DAG.getEVTAlignment(MemVT),
4671 AAMDNodes(), nullptr, SSID, Order);
4672
4673 InChain = TLI.prepareVolatileOrAtomicLoad(InChain, dl, DAG);
4674 SDValue L =
4675 DAG.getAtomic(ISD::ATOMIC_LOAD, dl, MemVT, MemVT, InChain,
4676 getValue(I.getPointerOperand()), MMO);
4677
4678 SDValue OutChain = L.getValue(1);
4679 if (MemVT != VT)
4680 L = DAG.getPtrExtOrTrunc(L, dl, VT);
4681
4682 setValue(&I, L);
4683 DAG.setRoot(OutChain);
4684}
4685
4686void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) {
4687 SDLoc dl = getCurSDLoc();
4688
4689 AtomicOrdering Ordering = I.getOrdering();
4690 SyncScope::ID SSID = I.getSyncScopeID();
4691
4692 SDValue InChain = getRoot();
4693
4694 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4695 EVT MemVT =
4696 TLI.getMemValueType(DAG.getDataLayout(), I.getValueOperand()->getType());
4697
4698 if (I.getAlignment() < MemVT.getSizeInBits() / 8)
4699 report_fatal_error("Cannot generate unaligned atomic store");
4700
4701 auto Flags = MachineMemOperand::MOStore;
4702 if (I.isVolatile())
4703 Flags |= MachineMemOperand::MOVolatile;
4704 Flags |= TLI.getMMOFlags(I);
4705
4706 MachineFunction &MF = DAG.getMachineFunction();
4707 MachineMemOperand *MMO =
4708 MF.getMachineMemOperand(MachinePointerInfo(I.getPointerOperand()), Flags,
4709 MemVT.getStoreSize(), I.getAlignment(), AAMDNodes(),
4710 nullptr, SSID, Ordering);
4711
4712 SDValue Val = DAG.getPtrExtOrTrunc(getValue(I.getValueOperand()), dl, MemVT);
4713 SDValue OutChain = DAG.getAtomic(ISD::ATOMIC_STORE, dl, MemVT, InChain,
4714 getValue(I.getPointerOperand()), Val, MMO);
4715
4716
4717 DAG.setRoot(OutChain);
4718}
4719
4720/// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
4721/// node.
4722void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
4723 unsigned Intrinsic) {
4724 // Ignore the callsite's attributes. A specific call site may be marked with
4725 // readnone, but the lowering code will expect the chain based on the
4726 // definition.
4727 const Function *F = I.getCalledFunction();
4728 bool HasChain = !F->doesNotAccessMemory();
4729 bool OnlyLoad = HasChain && F->onlyReadsMemory();
4730
4731 // Build the operand list.
4732 SmallVector<SDValue, 8> Ops;
4733 if (HasChain) { // If this intrinsic has side-effects, chainify it.
4734 if (OnlyLoad) {
4735 // We don't need to serialize loads against other loads.
4736 Ops.push_back(DAG.getRoot());
4737 } else {
4738 Ops.push_back(getRoot());
4739 }
4740 }
4741
4742 // Info is set by getTgtMemInstrinsic
4743 TargetLowering::IntrinsicInfo Info;
4744 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4745 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I,
4746 DAG.getMachineFunction(),
4747 Intrinsic);
4748
4749 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
4750 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID ||
4751 Info.opc == ISD::INTRINSIC_W_CHAIN)
4752 Ops.push_back(DAG.getTargetConstant(Intrinsic, getCurSDLoc(),
4753 TLI.getPointerTy(DAG.getDataLayout())));
4754
4755 // Add all operands of the call to the operand list.
4756 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
4757 SDValue Op = getValue(I.getArgOperand(i));
4758 Ops.push_back(Op);
4759 }
4760
4761 SmallVector<EVT, 4> ValueVTs;
4762 ComputeValueVTs(TLI, DAG.getDataLayout(), I.getType(), ValueVTs);
4763
4764 if (HasChain)
4765 ValueVTs.push_back(MVT::Other);
4766
4767 SDVTList VTs = DAG.getVTList(ValueVTs);
4768
4769 // Create the node.
4770 SDValue Result;
4771 if (IsTgtIntrinsic) {
4772 // This is target intrinsic that touches memory
4773 Result = DAG.getMemIntrinsicNode(Info.opc, getCurSDLoc(), VTs,
4774 Ops, Info.memVT,
4775 MachinePointerInfo(Info.ptrVal, Info.offset), Info.align,
4776 Info.flags, Info.size);
4777 } else if (!HasChain) {
4778 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurSDLoc(), VTs, Ops);
4779 } else if (!I.getType()->isVoidTy()) {
4780 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurSDLoc(), VTs, Ops);
4781 } else {
4782 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurSDLoc(), VTs, Ops);
4783 }
4784
4785 if (HasChain) {
4786 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
4787 if (OnlyLoad)
4788 PendingLoads.push_back(Chain);
4789 else
4790 DAG.setRoot(Chain);
4791 }
4792
4793 if (!I.getType()->isVoidTy()) {
4794 if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
4795 EVT VT = TLI.getValueType(DAG.getDataLayout(), PTy);
4796 Result = DAG.getNode(ISD::BITCAST, getCurSDLoc(), VT, Result);
4797 } else
4798 Result = lowerRangeToAssertZExt(DAG, I, Result);
4799
4800 setValue(&I, Result);
4801 }
4802}
4803
4804/// GetSignificand - Get the significand and build it into a floating-point
4805/// number with exponent of 1:
4806///
4807/// Op = (Op & 0x007fffff) | 0x3f800000;
4808///
4809/// where Op is the hexadecimal representation of floating point value.
4810static SDValue GetSignificand(SelectionDAG &DAG, SDValue Op, const SDLoc &dl) {
4811 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
4812 DAG.getConstant(0x007fffff, dl, MVT::i32));
4813 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
4814 DAG.getConstant(0x3f800000, dl, MVT::i32));
4815 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2);
4816}
4817
4818/// GetExponent - Get the exponent:
4819///
4820/// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
4821///
4822/// where Op is the hexadecimal representation of floating point value.
4823static SDValue GetExponent(SelectionDAG &DAG, SDValue Op,
4824 const TargetLowering &TLI, const SDLoc &dl) {
4825 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
4826 DAG.getConstant(0x7f800000, dl, MVT::i32));
4827 SDValue t1 = DAG.getNode(
4828 ISD::SRL, dl, MVT::i32, t0,
4829 DAG.getConstant(23, dl, TLI.getPointerTy(DAG.getDataLayout())));
4830 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
4831 DAG.getConstant(127, dl, MVT::i32));
4832 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
4833}
4834
4835/// getF32Constant - Get 32-bit floating point constant.
4836static SDValue getF32Constant(SelectionDAG &DAG, unsigned Flt,
4837 const SDLoc &dl) {
4838 return DAG.getConstantFP(APFloat(APFloat::IEEEsingle(), APInt(32, Flt)), dl,
4839 MVT::f32);
4840}
4841
4842static SDValue getLimitedPrecisionExp2(SDValue t0, const SDLoc &dl,
4843 SelectionDAG &DAG) {
4844 // TODO: What fast-math-flags should be set on the floating-point nodes?
4845
4846 // IntegerPartOfX = ((int32_t)(t0);
4847 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
4848
4849 // FractionalPartOfX = t0 - (float)IntegerPartOfX;
4850 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
4851 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
4852
4853 // IntegerPartOfX <<= 23;
4854 IntegerPartOfX = DAG.getNode(
4855 ISD::SHL, dl, MVT::i32, IntegerPartOfX,
4856 DAG.getConstant(23, dl, DAG.getTargetLoweringInfo().getPointerTy(
4857 DAG.getDataLayout())));
4858
4859 SDValue TwoToFractionalPartOfX;
4860 if (LimitFloatPrecision <= 6) {
4861 // For floating-point precision of 6:
4862 //
4863 // TwoToFractionalPartOfX =
4864 // 0.997535578f +
4865 // (0.735607626f + 0.252464424f * x) * x;
4866 //
4867 // error 0.0144103317, which is 6 bits
4868 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4869 getF32Constant(DAG, 0x3e814304, dl));
4870 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4871 getF32Constant(DAG, 0x3f3c50c8, dl));
4872 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4873 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4874 getF32Constant(DAG, 0x3f7f5e7e, dl));
4875 } else if (LimitFloatPrecision <= 12) {
4876 // For floating-point precision of 12:
4877 //
4878 // TwoToFractionalPartOfX =
4879 // 0.999892986f +
4880 // (0.696457318f +
4881 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
4882 //
4883 // error 0.000107046256, which is 13 to 14 bits
4884 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4885 getF32Constant(DAG, 0x3da235e3, dl));
4886 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4887 getF32Constant(DAG, 0x3e65b8f3, dl));
4888 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4889 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4890 getF32Constant(DAG, 0x3f324b07, dl));
4891 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4892 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4893 getF32Constant(DAG, 0x3f7ff8fd, dl));
4894 } else { // LimitFloatPrecision <= 18
4895 // For floating-point precision of 18:
4896 //
4897 // TwoToFractionalPartOfX =
4898 // 0.999999982f +
4899 // (0.693148872f +
4900 // (0.240227044f +
4901 // (0.554906021e-1f +
4902 // (0.961591928e-2f +
4903 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
4904 // error 2.47208000*10^(-7), which is better than 18 bits
4905 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4906 getF32Constant(DAG, 0x3924b03e, dl));
4907 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4908 getF32Constant(DAG, 0x3ab24b87, dl));
4909 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4910 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4911 getF32Constant(DAG, 0x3c1d8c17, dl));
4912 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4913 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4914 getF32Constant(DAG, 0x3d634a1d, dl));
4915 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4916 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4917 getF32Constant(DAG, 0x3e75fe14, dl));
4918 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4919 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
4920 getF32Constant(DAG, 0x3f317234, dl));
4921 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
4922 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
4923 getF32Constant(DAG, 0x3f800000, dl));
4924 }
4925
4926 // Add the exponent into the result in integer domain.
4927 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, TwoToFractionalPartOfX);
4928 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
4929 DAG.getNode(ISD::ADD, dl, MVT::i32, t13, IntegerPartOfX));
4930}
4931
4932/// expandExp - Lower an exp intrinsic. Handles the special sequences for
4933/// limited-precision mode.
4934static SDValue expandExp(const SDLoc &dl, SDValue Op, SelectionDAG &DAG,
4935 const TargetLowering &TLI) {
4936 if (Op.getValueType() == MVT::f32 &&
4937 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4938
4939 // Put the exponent in the right bit position for later addition to the
4940 // final result:
4941 //
4942 // #define LOG2OFe 1.4426950f
4943 // t0 = Op * LOG2OFe
4944
4945 // TODO: What fast-math-flags should be set here?
4946 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
4947 getF32Constant(DAG, 0x3fb8aa3b, dl));
4948 return getLimitedPrecisionExp2(t0, dl, DAG);
4949 }
4950
4951 // No special expansion.
4952 return DAG.getNode(ISD::FEXP, dl, Op.getValueType(), Op);
4953}
4954
4955/// expandLog - Lower a log intrinsic. Handles the special sequences for
4956/// limited-precision mode.
4957static SDValue expandLog(const SDLoc &dl, SDValue Op, SelectionDAG &DAG,
4958 const TargetLowering &TLI) {
4959 // TODO: What fast-math-flags should be set on the floating-point nodes?
4960
4961 if (Op.getValueType() == MVT::f32 &&
4962 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4963 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
4964
4965 // Scale the exponent by log(2) [0.69314718f].
4966 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
4967 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
4968 getF32Constant(DAG, 0x3f317218, dl));
4969
4970 // Get the significand and build it into a floating-point number with
4971 // exponent of 1.
4972 SDValue X = GetSignificand(DAG, Op1, dl);
4973
4974 SDValue LogOfMantissa;
4975 if (LimitFloatPrecision <= 6) {
4976 // For floating-point precision of 6:
4977 //
4978 // LogofMantissa =
4979 // -1.1609546f +
4980 // (1.4034025f - 0.23903021f * x) * x;
4981 //
4982 // error 0.0034276066, which is better than 8 bits
4983 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4984 getF32Constant(DAG, 0xbe74c456, dl));
4985 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4986 getF32Constant(DAG, 0x3fb3a2b1, dl));
4987 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4988 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4989 getF32Constant(DAG, 0x3f949a29, dl));
4990 } else if (LimitFloatPrecision <= 12) {
4991 // For floating-point precision of 12:
4992 //
4993 // LogOfMantissa =
4994 // -1.7417939f +
4995 // (2.8212026f +
4996 // (-1.4699568f +
4997 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
4998 //
4999 // error 0.000061011436, which is 14 bits
5000 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
5001 getF32Constant(DAG, 0xbd67b6d6, dl));
5002 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
5003 getF32Constant(DAG, 0x3ee4f4b8, dl));
5004 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
5005 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
5006 getF32Constant(DAG, 0x3fbc278b, dl));
5007 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
5008 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
5009 getF32Constant(DAG, 0x40348e95, dl));
5010 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
5011 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
5012 getF32Constant(DAG, 0x3fdef31a, dl));
5013 } else { // LimitFloatPrecision <= 18
5014 // For floating-point precision of 18:
5015 //
5016 // LogOfMantissa =
5017 // -2.1072184f +
5018 // (4.2372794f +
5019 // (-3.7029485f +
5020 // (2.2781945f +
5021 // (-0.87823314f +
5022 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
5023 //
5024 // error 0.0000023660568, which is better than 18 bits
5025 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
5026 getF32Constant(DAG, 0xbc91e5ac, dl));
5027 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
5028 getF32Constant(DAG, 0x3e4350aa, dl));
5029 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
5030 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
5031 getF32Constant(DAG, 0x3f60d3e3, dl));
5032 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
5033 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
5034 getF32Constant(DAG, 0x4011cdf0, dl));
5035 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
5036 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
5037 getF32Constant(DAG, 0x406cfd1c, dl));
5038 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
5039 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
5040 getF32Constant(DAG, 0x408797cb, dl));
5041 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
5042 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
5043 getF32Constant(DAG, 0x4006dcab, dl));
5044 }
5045
5046 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, LogOfMantissa);
5047 }
5048
5049 // No special expansion.
5050 return DAG.getNode(ISD::FLOG, dl, Op.getValueType(), Op);
5051}
5052
5053/// expandLog2 - Lower a log2 intrinsic. Handles the special sequences for
5054/// limited-precision mode.
5055static SDValue expandLog2(const SDLoc &dl, SDValue Op, SelectionDAG &DAG,
5056 const TargetLowering &TLI) {
5057 // TODO: What fast-math-flags should be set on the floating-point nodes?
5058
5059 if (Op.getValueType() == MVT::f32 &&
5060 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
5061 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
5062
5063 // Get the exponent.
5064 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
5065
5066 // Get the significand and build it into a floating-point number with
5067 // exponent of 1.
5068 SDValue X = GetSignificand(DAG, Op1, dl);
5069
5070 // Different possible minimax approximations of significand in
5071 // floating-point for various degrees of accuracy over [1,2].
5072 SDValue Log2ofMantissa;
5073 if (LimitFloatPrecision <= 6) {
5074 // For floating-point precision of 6:
5075 //
5076 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
5077 //
5078 // error 0.0049451742, which is more than 7 bits
5079 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
5080 getF32Constant(DAG, 0xbeb08fe0, dl));
5081 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
5082 getF32Constant(DAG, 0x40019463, dl));
5083 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
5084 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
5085 getF32Constant(DAG, 0x3fd6633d, dl));
5086 } else if (LimitFloatPrecision <= 12) {
5087 // For floating-point precision of 12:
5088 //
5089 // Log2ofMantissa =
5090 // -2.51285454f +
5091 // (4.07009056f +
5092 // (-2.12067489f +
5093 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
5094 //
5095 // error 0.0000876136000, which is better than 13 bits
5096 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
5097 getF32Constant(DAG, 0xbda7262e, dl));
5098 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
5099 getF32Constant(DAG, 0x3f25280b, dl));
5100 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
5101 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
5102 getF32Constant(DAG, 0x4007b923, dl));
5103 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
5104 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
5105 getF32Constant(DAG, 0x40823e2f, dl));
5106 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
5107 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
5108 getF32Constant(DAG, 0x4020d29c, dl));
5109 } else { // LimitFloatPrecision <= 18
5110 // For floating-point precision of 18:
5111 //
5112 // Log2ofMantissa =
5113 // -3.0400495f +
5114 // (6.1129976f +
5115 // (-5.3420409f +
5116 // (3.2865683f +
5117 // (-1.2669343f +
5118 // (0.27515199f -
5119 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
5120 //
5121 // error 0.0000018516, which is better than 18 bits
5122 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
5123 getF32Constant(DAG, 0xbcd2769e, dl));
5124 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
5125 getF32Constant(DAG, 0x3e8ce0b9, dl));
5126 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
5127 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
5128 getF32Constant(DAG, 0x3fa22ae7, dl));
5129 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
5130 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
5131 getF32Constant(DAG, 0x40525723, dl));
5132 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
5133 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
5134 getF32Constant(DAG, 0x40aaf200, dl));
5135 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
5136 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
5137 getF32Constant(DAG, 0x40c39dad, dl));
5138 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
5139 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
5140 getF32Constant(DAG, 0x4042902c, dl));
5141 }
5142
5143 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log2ofMantissa);
5144 }
5145
5146 // No special expansion.
5147 return DAG.getNode(ISD::FLOG2, dl, Op.getValueType(), Op);
5148}
5149
5150/// expandLog10 - Lower a log10 intrinsic. Handles the special sequences for
5151/// limited-precision mode.
5152static SDValue expandLog10(const SDLoc &dl, SDValue Op, SelectionDAG &DAG,
5153 const TargetLowering &TLI) {
5154 // TODO: What fast-math-flags should be set on the floating-point nodes?
5155
5156 if (Op.getValueType() == MVT::f32 &&
5157 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
5158 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
5159
5160 // Scale the exponent by log10(2) [0.30102999f].
5161 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
5162 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
5163 getF32Constant(DAG, 0x3e9a209a, dl));
5164
5165 // Get the significand and build it into a floating-point number with
5166 // exponent of 1.
5167 SDValue X = GetSignificand(DAG, Op1, dl);
5168
5169 SDValue Log10ofMantissa;
5170 if (LimitFloatPrecision <= 6) {
5171 // For floating-point precision of 6:
5172 //
5173 // Log10ofMantissa =
5174 // -0.50419619f +
5175 // (0.60948995f - 0.10380950f * x) * x;
5176 //
5177 // error 0.0014886165, which is 6 bits
5178 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
5179 getF32Constant(DAG, 0xbdd49a13, dl));
5180 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
5181 getF32Constant(DAG, 0x3f1c0789, dl));
5182 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
5183 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
5184 getF32Constant(DAG, 0x3f011300, dl));
5185 } else if (LimitFloatPrecision <= 12) {
5186 // For floating-point precision of 12:
5187 //
5188 // Log10ofMantissa =
5189 // -0.64831180f +
5190 // (0.91751397f +
5191 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
5192 //
5193 // error 0.00019228036, which is better than 12 bits
5194 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
5195 getF32Constant(DAG, 0x3d431f31, dl));
5196 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
5197 getF32Constant(DAG, 0x3ea21fb2, dl));
5198 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
5199 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
5200 getF32Constant(DAG, 0x3f6ae232, dl));
5201 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
5202 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
5203 getF32Constant(DAG, 0x3f25f7c3, dl));
5204 } else { // LimitFloatPrecision <= 18
5205 // For floating-point precision of 18:
5206 //
5207 // Log10ofMantissa =
5208 // -0.84299375f +
5209 // (1.5327582f +
5210 // (-1.0688956f +
5211 // (0.49102474f +
5212 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
5213 //
5214 // error 0.0000037995730, which is better than 18 bits
5215 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
5216 getF32Constant(DAG, 0x3c5d51ce, dl));
5217 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
5218 getF32Constant(DAG, 0x3e00685a, dl));
5219 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
5220 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
5221 getF32Constant(DAG, 0x3efb6798, dl));
5222 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
5223 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
5224 getF32Constant(DAG, 0x3f88d192, dl));
5225 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
5226 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
5227 getF32Constant(DAG, 0x3fc4316c, dl));
5228 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
5229 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
5230 getF32Constant(DAG, 0x3f57ce70, dl));
5231 }
5232
5233 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log10ofMantissa);
5234 }
5235
5236 // No special expansion.
5237 return DAG.getNode(ISD::FLOG10, dl, Op.getValueType(), Op);
5238}
5239
5240/// expandExp2 - Lower an exp2 intrinsic. Handles the special sequences for
5241/// limited-precision mode.
5242static SDValue expandExp2(const SDLoc &dl, SDValue Op, SelectionDAG &DAG,
5243 const TargetLowering &TLI) {
5244 if (Op.getValueType() == MVT::f32 &&
5245 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18)
5246 return getLimitedPrecisionExp2(Op, dl, DAG);
5247
5248 // No special expansion.
5249 return DAG.getNode(ISD::FEXP2, dl, Op.getValueType(), Op);
5250}
5251
5252/// visitPow - Lower a pow intrinsic. Handles the special sequences for
5253/// limited-precision mode with x == 10.0f.
5254static SDValue expandPow(const SDLoc &dl, SDValue LHS, SDValue RHS,
5255 SelectionDAG &DAG, const TargetLowering &TLI) {
5256 bool IsExp10 = false;
5257 if (LHS.getValueType() == MVT::f32 && RHS.getValueType() == MVT::f32 &&
5258 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
5259 if (ConstantFPSDNode *LHSC = dyn_cast<ConstantFPSDNode>(LHS)) {
5260 APFloat Ten(10.0f);
5261 IsExp10 = LHSC->isExactlyValue(Ten);
5262 }
5263 }
5264
5265 // TODO: What fast-math-flags should be set on the FMUL node?
5266 if (IsExp10) {
5267 // Put the exponent in the right bit position for later addition to the
5268 // final result:
5269 //
5270 // #define LOG2OF10 3.3219281f
5271 // t0 = Op * LOG2OF10;
5272 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, RHS,
5273 getF32Constant(DAG, 0x40549a78, dl));
5274 return getLimitedPrecisionExp2(t0, dl, DAG);
5275 }
5276
5277 // No special expansion.
5278 return DAG.getNode(ISD::FPOW, dl, LHS.getValueType(), LHS, RHS);
5279}
5280
5281/// ExpandPowI - Expand a llvm.powi intrinsic.
5282static SDValue ExpandPowI(const SDLoc &DL, SDValue LHS, SDValue RHS,
5283 SelectionDAG &DAG) {
5284 // If RHS is a constant, we can expand this out to a multiplication tree,
5285 // otherwise we end up lowering to a call to __powidf2 (for example). When
5286 // optimizing for size, we only want to do this if the expansion would produce
5287 // a small number of multiplies, otherwise we do the full expansion.
5288 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
5289 // Get the exponent as a positive value.
5290 unsigned Val = RHSC->getSExtValue();
5291 if ((int)Val < 0) Val = -Val;
5292
5293 // powi(x, 0) -> 1.0
5294 if (Val == 0)
5295 return DAG.getConstantFP(1.0, DL, LHS.getValueType());
5296
5297 const Function &F = DAG.getMachineFunction().getFunction();
5298 if (!F.hasOptSize() ||
5299 // If optimizing for size, don't insert too many multiplies.
5300 // This inserts up to 5 multiplies.
5301 countPopulation(Val) + Log2_32(Val) < 7) {
5302 // We use the simple binary decomposition method to generate the multiply
5303 // sequence. There are more optimal ways to do this (for example,
5304 // powi(x,15) generates one more multiply than it should), but this has
5305 // the benefit of being both really simple and much better than a libcall.
5306 SDValue Res; // Logically starts equal to 1.0
5307 SDValue CurSquare = LHS;
5308 // TODO: Intrinsics should have fast-math-flags that propagate to these
5309 // nodes.
5310 while (Val) {
5311 if (Val & 1) {
5312 if (Res.getNode())
5313 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare);
5314 else
5315 Res = CurSquare; // 1.0*CurSquare.
5316 }
5317
5318 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(),
5319 CurSquare, CurSquare);
5320 Val >>= 1;
5321 }
5322
5323 // If the original was negative, invert the result, producing 1/(x*x*x).
5324 if (RHSC->getSExtValue() < 0)
5325 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(),
5326 DAG.getConstantFP(1.0, DL, LHS.getValueType()), Res);
5327 return Res;
5328 }
5329 }
5330
5331 // Otherwise, expand to a libcall.
5332 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS);
5333}
5334
5335// getUnderlyingArgReg - Find underlying register used for a truncated or
5336// bitcasted argument.
5337static unsigned getUnderlyingArgReg(const SDValue &N) {
5338 switch (N.getOpcode()) {
5339 case ISD::CopyFromReg:
5340 return cast<RegisterSDNode>(N.getOperand(1))->getReg();
5341 case ISD::BITCAST:
5342 case ISD::AssertZext:
5343 case ISD::AssertSext:
5344 case ISD::TRUNCATE:
5345 return getUnderlyingArgReg(N.getOperand(0));
5346 default:
5347 return 0;
5348 }
5349}
5350
5351/// If the DbgValueInst is a dbg_value of a function argument, create the
5352/// corresponding DBG_VALUE machine instruction for it now. At the end of
5353/// instruction selection, they will be inserted to the entry BB.
5354bool SelectionDAGBuilder::EmitFuncArgumentDbgValue(
5355 const Value *V, DILocalVariable *Variable, DIExpression *Expr,
5356 DILocation *DL, bool IsDbgDeclare, const SDValue &N) {
5357 const Argument *Arg = dyn_cast<Argument>(V);
5358 if (!Arg)
5359 return false;
5360
5361 if (!IsDbgDeclare) {
5362 // ArgDbgValues are hoisted to the beginning of the entry block. So we
5363 // should only emit as ArgDbgValue if the dbg.value intrinsic is found in
5364 // the entry block.
5365 bool IsInEntryBlock = FuncInfo.MBB == &FuncInfo.MF->front();
5366 if (!IsInEntryBlock)
5367 return false;
5368
5369 // ArgDbgValues are hoisted to the beginning of the entry block. So we
5370 // should only emit as ArgDbgValue if the dbg.value intrinsic describes a
5371 // variable that also is a param.
5372 //
5373 // Although, if we are at the top of the entry block already, we can still
5374 // emit using ArgDbgValue. This might catch some situations when the
5375 // dbg.value refers to an argument that isn't used in the entry block, so
5376 // any CopyToReg node would be optimized out and the only way to express
5377 // this DBG_VALUE is by using the physical reg (or FI) as done in this
5378 // method. ArgDbgValues are hoisted to the beginning of the entry block. So
5379 // we should only emit as ArgDbgValue if the Variable is an argument to the
5380 // current function, and the dbg.value intrinsic is found in the entry
5381 // block.
5382 bool VariableIsFunctionInputArg = Variable->isParameter() &&
5383 !DL->getInlinedAt();
5384 bool IsInPrologue = SDNodeOrder == LowestSDNodeOrder;
5385 if (!IsInPrologue && !VariableIsFunctionInputArg)
5386 return false;
5387
5388 // Here we assume that a function argument on IR level only can be used to
5389 // describe one input parameter on source level. If we for example have
5390 // source code like this
5391 //
5392 // struct A { long x, y; };
5393 // void foo(struct A a, long b) {
5394 // ...
5395 // b = a.x;
5396 // ...
5397 // }
5398 //
5399 // and IR like this
5400 //
5401 // define void @foo(i32 %a1, i32 %a2, i32 %b) {
5402 // entry:
5403 // call void @llvm.dbg.value(metadata i32 %a1, "a", DW_OP_LLVM_fragment
5404 // call void @llvm.dbg.value(metadata i32 %a2, "a", DW_OP_LLVM_fragment
5405 // call void @llvm.dbg.value(metadata i32 %b, "b",
5406 // ...
5407 // call void @llvm.dbg.value(metadata i32 %a1, "b"
5408 // ...
5409 //
5410 // then the last dbg.value is describing a parameter "b" using a value that
5411 // is an argument. But since we already has used %a1 to describe a parameter
5412 // we should not handle that last dbg.value here (that would result in an
5413 // incorrect hoisting of the DBG_VALUE to the function entry).
5414 // Notice that we allow one dbg.value per IR level argument, to accomodate
5415 // for the situation with fragments above.
5416 if (VariableIsFunctionInputArg) {
5417 unsigned ArgNo = Arg->getArgNo();
5418 if (ArgNo >= FuncInfo.DescribedArgs.size())
5419 FuncInfo.DescribedArgs.resize(ArgNo + 1, false);
5420 else if (!IsInPrologue && FuncInfo.DescribedArgs.test(ArgNo))
5421 return false;
5422 FuncInfo.DescribedArgs.set(ArgNo);
5423 }
5424 }
5425
5426 MachineFunction &MF = DAG.getMachineFunction();
5427 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
5428
5429 bool IsIndirect = false;
5430 Optional<MachineOperand> Op;
5431 // Some arguments' frame index is recorded during argument lowering.
5432 int FI = FuncInfo.getArgumentFrameIndex(Arg);
5433 if (FI != std::numeric_limits<int>::max())
5434 Op = MachineOperand::CreateFI(FI);
5435
5436 if (!Op && N.getNode()) {
5437 unsigned Reg = getUnderlyingArgReg(N);
5438 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) {
5439 MachineRegisterInfo &RegInfo = MF.getRegInfo();
5440 unsigned PR = RegInfo.getLiveInPhysReg(Reg);
5441 if (PR)
5442 Reg = PR;
5443 }
5444 if (Reg) {
5445 Op = MachineOperand::CreateReg(Reg, false);
5446 IsIndirect = IsDbgDeclare;
5447 }
5448 }
5449
5450 if (!Op && N.getNode()) {
5451 // Check if frame index is available.
5452 SDValue LCandidate = peekThroughBitcasts(N);
5453 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(LCandidate.getNode()))
5454 if (FrameIndexSDNode *FINode =
5455 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
5456 Op = MachineOperand::CreateFI(FINode->getIndex());
5457 }
5458
5459 if (!Op) {
5460 // Check if ValueMap has reg number.
5461 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
5462 if (VMI != FuncInfo.ValueMap.end()) {
5463 const auto &TLI = DAG.getTargetLoweringInfo();
5464 RegsForValue RFV(V->getContext(), TLI, DAG.getDataLayout(), VMI->second,
5465 V->getType(), getABIRegCopyCC(V));
5466 if (RFV.occupiesMultipleRegs()) {
5467 unsigned Offset = 0;
5468 for (auto RegAndSize : RFV.getRegsAndSizes()) {
5469 Op = MachineOperand::CreateReg(RegAndSize.first, false);
5470 auto FragmentExpr = DIExpression::createFragmentExpression(
5471 Expr, Offset, RegAndSize.second);
5472 if (!FragmentExpr)
5473 continue;
5474 FuncInfo.ArgDbgValues.push_back(
5475 BuildMI(MF, DL, TII->get(TargetOpcode::DBG_VALUE), IsDbgDeclare,
5476 Op->getReg(), Variable, *FragmentExpr));
5477 Offset += RegAndSize.second;
5478 }
5479 return true;
5480 }
5481 Op = MachineOperand::CreateReg(VMI->second, false);
5482 IsIndirect = IsDbgDeclare;
5483 }
5484 }
5485
5486 if (!Op)
5487 return false;
5488
5489 assert(Variable->isValidLocationForIntrinsic(DL) &&((Variable->isValidLocationForIntrinsic(DL) && "Expected inlined-at fields to agree"
) ? static_cast<void> (0) : __assert_fail ("Variable->isValidLocationForIntrinsic(DL) && \"Expected inlined-at fields to agree\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 5490, __PRETTY_FUNCTION__))
5490 "Expected inlined-at fields to agree")((Variable->isValidLocationForIntrinsic(DL) && "Expected inlined-at fields to agree"
) ? static_cast<void> (0) : __assert_fail ("Variable->isValidLocationForIntrinsic(DL) && \"Expected inlined-at fields to agree\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 5490, __PRETTY_FUNCTION__))
;
5491 IsIndirect = (Op->isReg()) ? IsIndirect : true;
5492 FuncInfo.ArgDbgValues.push_back(
5493 BuildMI(MF, DL, TII->get(TargetOpcode::DBG_VALUE), IsIndirect,
5494 *Op, Variable, Expr));
5495
5496 return true;
5497}
5498
5499/// Return the appropriate SDDbgValue based on N.
5500SDDbgValue *SelectionDAGBuilder::getDbgValue(SDValue N,
5501 DILocalVariable *Variable,
5502 DIExpression *Expr,
5503 const DebugLoc &dl,
5504 unsigned DbgSDNodeOrder) {
5505 if (auto *FISDN = dyn_cast<FrameIndexSDNode>(N.getNode())) {
5506 // Construct a FrameIndexDbgValue for FrameIndexSDNodes so we can describe
5507 // stack slot locations.
5508 //
5509 // Consider "int x = 0; int *px = &x;". There are two kinds of interesting
5510 // debug values here after optimization:
5511 //
5512 // dbg.value(i32* %px, !"int *px", !DIExpression()), and
5513 // dbg.value(i32* %px, !"int x", !DIExpression(DW_OP_deref))
5514 //
5515 // Both describe the direct values of their associated variables.
5516 return DAG.getFrameIndexDbgValue(Variable, Expr, FISDN->getIndex(),
5517 /*IsIndirect*/ false, dl, DbgSDNodeOrder);
5518 }
5519 return DAG.getDbgValue(Variable, Expr, N.getNode(), N.getResNo(),
5520 /*IsIndirect*/ false, dl, DbgSDNodeOrder);
5521}
5522
5523// VisualStudio defines setjmp as _setjmp
5524#if defined(_MSC_VER) && defined(setjmp) && \
5525 !defined(setjmp_undefined_for_msvc)
5526# pragma push_macro("setjmp")
5527# undef setjmp
5528# define setjmp_undefined_for_msvc
5529#endif
5530
5531static unsigned FixedPointIntrinsicToOpcode(unsigned Intrinsic) {
5532 switch (Intrinsic) {
5533 case Intrinsic::smul_fix:
5534 return ISD::SMULFIX;
5535 case Intrinsic::umul_fix:
5536 return ISD::UMULFIX;
5537 default:
5538 llvm_unreachable("Unhandled fixed point intrinsic")::llvm::llvm_unreachable_internal("Unhandled fixed point intrinsic"
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 5538)
;
5539 }
5540}
5541
5542/// Lower the call to the specified intrinsic function. If we want to emit this
5543/// as a call to a named external function, return the name. Otherwise, lower it
5544/// and return null.
5545const char *
5546SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
5547 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5548 SDLoc sdl = getCurSDLoc();
5549 DebugLoc dl = getCurDebugLoc();
5550 SDValue Res;
5551
5552 switch (Intrinsic) {
5553 default:
5554 // By default, turn this into a target intrinsic node.
5555 visitTargetIntrinsic(I, Intrinsic);
5556 return nullptr;
5557 case Intrinsic::vastart: visitVAStart(I); return nullptr;
5558 case Intrinsic::vaend: visitVAEnd(I); return nullptr;
5559 case Intrinsic::vacopy: visitVACopy(I); return nullptr;
5560 case Intrinsic::returnaddress:
5561 setValue(&I, DAG.getNode(ISD::RETURNADDR, sdl,
5562 TLI.getPointerTy(DAG.getDataLayout()),
5563 getValue(I.getArgOperand(0))));
5564 return nullptr;
5565 case Intrinsic::addressofreturnaddress:
5566 setValue(&I, DAG.getNode(ISD::ADDROFRETURNADDR, sdl,
5567 TLI.getPointerTy(DAG.getDataLayout())));
5568 return nullptr;
5569 case Intrinsic::sponentry:
5570 setValue(&I, DAG.getNode(ISD::SPONENTRY, sdl,
5571 TLI.getPointerTy(DAG.getDataLayout())));
5572 return nullptr;
5573 case Intrinsic::frameaddress:
5574 setValue(&I, DAG.getNode(ISD::FRAMEADDR, sdl,
5575 TLI.getPointerTy(DAG.getDataLayout()),
5576 getValue(I.getArgOperand(0))));
5577 return nullptr;
5578 case Intrinsic::read_register: {
5579 Value *Reg = I.getArgOperand(0);
5580 SDValue Chain = getRoot();
5581 SDValue RegName =
5582 DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
5583 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
5584 Res = DAG.getNode(ISD::READ_REGISTER, sdl,
5585 DAG.getVTList(VT, MVT::Other), Chain, RegName);
5586 setValue(&I, Res);
5587 DAG.setRoot(Res.getValue(1));
5588 return nullptr;
5589 }
5590 case Intrinsic::write_register: {
5591 Value *Reg = I.getArgOperand(0);
5592 Value *RegValue = I.getArgOperand(1);
5593 SDValue Chain = getRoot();
5594 SDValue RegName =
5595 DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
5596 DAG.setRoot(DAG.getNode(ISD::WRITE_REGISTER, sdl, MVT::Other, Chain,
5597 RegName, getValue(RegValue)));
5598 return nullptr;
5599 }
5600 case Intrinsic::setjmp:
5601 return &"_setjmp"[!TLI.usesUnderscoreSetJmp()];
5602 case Intrinsic::longjmp:
5603 return &"_longjmp"[!TLI.usesUnderscoreLongJmp()];
5604 case Intrinsic::memcpy: {
5605 const auto &MCI = cast<MemCpyInst>(I);
5606 SDValue Op1 = getValue(I.getArgOperand(0));
5607 SDValue Op2 = getValue(I.getArgOperand(1));
5608 SDValue Op3 = getValue(I.getArgOperand(2));
5609 // @llvm.memcpy defines 0 and 1 to both mean no alignment.
5610 unsigned DstAlign = std::max<unsigned>(MCI.getDestAlignment(), 1);
5611 unsigned SrcAlign = std::max<unsigned>(MCI.getSourceAlignment(), 1);
5612 unsigned Align = MinAlign(DstAlign, SrcAlign);
5613 bool isVol = MCI.isVolatile();
5614 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
5615 // FIXME: Support passing different dest/src alignments to the memcpy DAG
5616 // node.
5617 SDValue MC = DAG.getMemcpy(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
5618 false, isTC,
5619 MachinePointerInfo(I.getArgOperand(0)),
5620 MachinePointerInfo(I.getArgOperand(1)));
5621 updateDAGForMaybeTailCall(MC);
5622 return nullptr;
5623 }
5624 case Intrinsic::memset: {
5625 const auto &MSI = cast<MemSetInst>(I);
5626 SDValue Op1 = getValue(I.getArgOperand(0));
5627 SDValue Op2 = getValue(I.getArgOperand(1));
5628 SDValue Op3 = getValue(I.getArgOperand(2));
5629 // @llvm.memset defines 0 and 1 to both mean no alignment.
5630 unsigned Align = std::max<unsigned>(MSI.getDestAlignment(), 1);
5631 bool isVol = MSI.isVolatile();
5632 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
5633 SDValue MS = DAG.getMemset(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
5634 isTC, MachinePointerInfo(I.getArgOperand(0)));
5635 updateDAGForMaybeTailCall(MS);
5636 return nullptr;
5637 }
5638 case Intrinsic::memmove: {
5639 const auto &MMI = cast<MemMoveInst>(I);
5640 SDValue Op1 = getValue(I.getArgOperand(0));
5641 SDValue Op2 = getValue(I.getArgOperand(1));
5642 SDValue Op3 = getValue(I.getArgOperand(2));
5643 // @llvm.memmove defines 0 and 1 to both mean no alignment.
5644 unsigned DstAlign = std::max<unsigned>(MMI.getDestAlignment(), 1);
5645 unsigned SrcAlign = std::max<unsigned>(MMI.getSourceAlignment(), 1);
5646 unsigned Align = MinAlign(DstAlign, SrcAlign);
5647 bool isVol = MMI.isVolatile();
5648 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
5649 // FIXME: Support passing different dest/src alignments to the memmove DAG
5650 // node.
5651 SDValue MM = DAG.getMemmove(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
5652 isTC, MachinePointerInfo(I.getArgOperand(0)),
5653 MachinePointerInfo(I.getArgOperand(1)));
5654 updateDAGForMaybeTailCall(MM);
5655 return nullptr;
5656 }
5657 case Intrinsic::memcpy_element_unordered_atomic: {
5658 const AtomicMemCpyInst &MI = cast<AtomicMemCpyInst>(I);
5659 SDValue Dst = getValue(MI.getRawDest());
5660 SDValue Src = getValue(MI.getRawSource());
5661 SDValue Length = getValue(MI.getLength());
5662
5663 unsigned DstAlign = MI.getDestAlignment();
5664 unsigned SrcAlign = MI.getSourceAlignment();
5665 Type *LengthTy = MI.getLength()->getType();
5666 unsigned ElemSz = MI.getElementSizeInBytes();
5667 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
5668 SDValue MC = DAG.getAtomicMemcpy(getRoot(), sdl, Dst, DstAlign, Src,
5669 SrcAlign, Length, LengthTy, ElemSz, isTC,
5670 MachinePointerInfo(MI.getRawDest()),
5671 MachinePointerInfo(MI.getRawSource()));
5672 updateDAGForMaybeTailCall(MC);
5673 return nullptr;
5674 }
5675 case Intrinsic::memmove_element_unordered_atomic: {
5676 auto &MI = cast<AtomicMemMoveInst>(I);
5677 SDValue Dst = getValue(MI.getRawDest());
5678 SDValue Src = getValue(MI.getRawSource());
5679 SDValue Length = getValue(MI.getLength());
5680
5681 unsigned DstAlign = MI.getDestAlignment();
5682 unsigned SrcAlign = MI.getSourceAlignment();
5683 Type *LengthTy = MI.getLength()->getType();
5684 unsigned ElemSz = MI.getElementSizeInBytes();
5685 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
5686 SDValue MC = DAG.getAtomicMemmove(getRoot(), sdl, Dst, DstAlign, Src,
5687 SrcAlign, Length, LengthTy, ElemSz, isTC,
5688 MachinePointerInfo(MI.getRawDest()),
5689 MachinePointerInfo(MI.getRawSource()));
5690 updateDAGForMaybeTailCall(MC);
5691 return nullptr;
5692 }
5693 case Intrinsic::memset_element_unordered_atomic: {
5694 auto &MI = cast<AtomicMemSetInst>(I);
5695 SDValue Dst = getValue(MI.getRawDest());
5696 SDValue Val = getValue(MI.getValue());
5697 SDValue Length = getValue(MI.getLength());
5698
5699 unsigned DstAlign = MI.getDestAlignment();
5700 Type *LengthTy = MI.getLength()->getType();
5701 unsigned ElemSz = MI.getElementSizeInBytes();
5702 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
5703 SDValue MC = DAG.getAtomicMemset(getRoot(), sdl, Dst, DstAlign, Val, Length,
5704 LengthTy, ElemSz, isTC,
5705 MachinePointerInfo(MI.getRawDest()));
5706 updateDAGForMaybeTailCall(MC);
5707 return nullptr;
5708 }
5709 case Intrinsic::dbg_addr:
5710 case Intrinsic::dbg_declare: {
5711 const auto &DI = cast<DbgVariableIntrinsic>(I);
5712 DILocalVariable *Variable = DI.getVariable();
5713 DIExpression *Expression = DI.getExpression();
5714 dropDanglingDebugInfo(Variable, Expression);
5715 assert(Variable && "Missing variable")((Variable && "Missing variable") ? static_cast<void
> (0) : __assert_fail ("Variable && \"Missing variable\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 5715, __PRETTY_FUNCTION__))
;
5716
5717 // Check if address has undef value.
5718 const Value *Address = DI.getVariableLocation();
5719 if (!Address || isa<UndefValue>(Address) ||
5720 (Address->use_empty() && !isa<Argument>(Address))) {
5721 LLVM_DEBUG(dbgs() << "Dropping debug info for " << DI << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << "Dropping debug info for " <<
DI << "\n"; } } while (false)
;
5722 return nullptr;
5723 }
5724
5725 bool isParameter = Variable->isParameter() || isa<Argument>(Address);
5726
5727 // Check if this variable can be described by a frame index, typically
5728 // either as a static alloca or a byval parameter.
5729 int FI = std::numeric_limits<int>::max();
5730 if (const auto *AI =
5731 dyn_cast<AllocaInst>(Address->stripInBoundsConstantOffsets())) {
5732 if (AI->isStaticAlloca()) {
5733 auto I = FuncInfo.StaticAllocaMap.find(AI);
5734 if (I != FuncInfo.StaticAllocaMap.end())
5735 FI = I->second;
5736 }
5737 } else if (const auto *Arg = dyn_cast<Argument>(
5738 Address->stripInBoundsConstantOffsets())) {
5739 FI = FuncInfo.getArgumentFrameIndex(Arg);
5740 }
5741
5742 // llvm.dbg.addr is control dependent and always generates indirect
5743 // DBG_VALUE instructions. llvm.dbg.declare is handled as a frame index in
5744 // the MachineFunction variable table.
5745 if (FI != std::numeric_limits<int>::max()) {
5746 if (Intrinsic == Intrinsic::dbg_addr) {
5747 SDDbgValue *SDV = DAG.getFrameIndexDbgValue(
5748 Variable, Expression, FI, /*IsIndirect*/ true, dl, SDNodeOrder);
5749 DAG.AddDbgValue(SDV, getRoot().getNode(), isParameter);
5750 }
5751 return nullptr;
5752 }
5753
5754 SDValue &N = NodeMap[Address];
5755 if (!N.getNode() && isa<Argument>(Address))
5756 // Check unused arguments map.
5757 N = UnusedArgNodeMap[Address];
5758 SDDbgValue *SDV;
5759 if (N.getNode()) {
5760 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
5761 Address = BCI->getOperand(0);
5762 // Parameters are handled specially.
5763 auto FINode = dyn_cast<FrameIndexSDNode>(N.getNode());
5764 if (isParameter && FINode) {
5765 // Byval parameter. We have a frame index at this point.
5766 SDV =
5767 DAG.getFrameIndexDbgValue(Variable, Expression, FINode->getIndex(),
5768 /*IsIndirect*/ true, dl, SDNodeOrder);
5769 } else if (isa<Argument>(Address)) {
5770 // Address is an argument, so try to emit its dbg value using
5771 // virtual register info from the FuncInfo.ValueMap.
5772 EmitFuncArgumentDbgValue(Address, Variable, Expression, dl, true, N);
5773 return nullptr;
5774 } else {
5775 SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(),
5776 true, dl, SDNodeOrder);
5777 }
5778 DAG.AddDbgValue(SDV, N.getNode(), isParameter);
5779 } else {
5780 // If Address is an argument then try to emit its dbg value using
5781 // virtual register info from the FuncInfo.ValueMap.
5782 if (!EmitFuncArgumentDbgValue(Address, Variable, Expression, dl, true,
5783 N)) {
5784 LLVM_DEBUG(dbgs() << "Dropping debug info for " << DI << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << "Dropping debug info for " <<
DI << "\n"; } } while (false)
;
5785 }
5786 }
5787 return nullptr;
5788 }
5789 case Intrinsic::dbg_label: {
5790 const DbgLabelInst &DI = cast<DbgLabelInst>(I);
5791 DILabel *Label = DI.getLabel();
5792 assert(Label && "Missing label")((Label && "Missing label") ? static_cast<void>
(0) : __assert_fail ("Label && \"Missing label\"", "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 5792, __PRETTY_FUNCTION__))
;
5793
5794 SDDbgLabel *SDV;
5795 SDV = DAG.getDbgLabel(Label, dl, SDNodeOrder);
5796 DAG.AddDbgLabel(SDV);
5797 return nullptr;
5798 }
5799 case Intrinsic::dbg_value: {
5800 const DbgValueInst &DI = cast<DbgValueInst>(I);
5801 assert(DI.getVariable() && "Missing variable")((DI.getVariable() && "Missing variable") ? static_cast
<void> (0) : __assert_fail ("DI.getVariable() && \"Missing variable\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 5801, __PRETTY_FUNCTION__))
;
5802
5803 DILocalVariable *Variable = DI.getVariable();
5804 DIExpression *Expression = DI.getExpression();
5805 dropDanglingDebugInfo(Variable, Expression);
5806 const Value *V = DI.getValue();
5807 if (!V)
5808 return nullptr;
5809
5810 if (handleDebugValue(V, Variable, Expression, dl, DI.getDebugLoc(),
5811 SDNodeOrder))
5812 return nullptr;
5813
5814 // TODO: Dangling debug info will eventually either be resolved or produce
5815 // an Undef DBG_VALUE. However in the resolution case, a gap may appear
5816 // between the original dbg.value location and its resolved DBG_VALUE, which
5817 // we should ideally fill with an extra Undef DBG_VALUE.
5818
5819 DanglingDebugInfoMap[V].emplace_back(&DI, dl, SDNodeOrder);
5820 return nullptr;
5821 }
5822
5823 case Intrinsic::eh_typeid_for: {
5824 // Find the type id for the given typeinfo.
5825 GlobalValue *GV = ExtractTypeInfo(I.getArgOperand(0));
5826 unsigned TypeID = DAG.getMachineFunction().getTypeIDFor(GV);
5827 Res = DAG.getConstant(TypeID, sdl, MVT::i32);
5828 setValue(&I, Res);
5829 return nullptr;
5830 }
5831
5832 case Intrinsic::eh_return_i32:
5833 case Intrinsic::eh_return_i64:
5834 DAG.getMachineFunction().setCallsEHReturn(true);
5835 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, sdl,
5836 MVT::Other,
5837 getControlRoot(),
5838 getValue(I.getArgOperand(0)),
5839 getValue(I.getArgOperand(1))));
5840 return nullptr;
5841 case Intrinsic::eh_unwind_init:
5842 DAG.getMachineFunction().setCallsUnwindInit(true);
5843 return nullptr;
5844 case Intrinsic::eh_dwarf_cfa:
5845 setValue(&I, DAG.getNode(ISD::EH_DWARF_CFA, sdl,
5846 TLI.getPointerTy(DAG.getDataLayout()),
5847 getValue(I.getArgOperand(0))));
5848 return nullptr;
5849 case Intrinsic::eh_sjlj_callsite: {
5850 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5851 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0));
5852 assert(CI && "Non-constant call site value in eh.sjlj.callsite!")((CI && "Non-constant call site value in eh.sjlj.callsite!"
) ? static_cast<void> (0) : __assert_fail ("CI && \"Non-constant call site value in eh.sjlj.callsite!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 5852, __PRETTY_FUNCTION__))
;
5853 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!")((MMI.getCurrentCallSite() == 0 && "Overlapping call sites!"
) ? static_cast<void> (0) : __assert_fail ("MMI.getCurrentCallSite() == 0 && \"Overlapping call sites!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 5853, __PRETTY_FUNCTION__))
;
5854
5855 MMI.setCurrentCallSite(CI->getZExtValue());
5856 return nullptr;
5857 }
5858 case Intrinsic::eh_sjlj_functioncontext: {
5859 // Get and store the index of the function context.
5860 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
5861 AllocaInst *FnCtx =
5862 cast<AllocaInst>(I.getArgOperand(0)->stripPointerCasts());
5863 int FI = FuncInfo.StaticAllocaMap[FnCtx];
5864 MFI.setFunctionContextIndex(FI);
5865 return nullptr;
5866 }
5867 case Intrinsic::eh_sjlj_setjmp: {
5868 SDValue Ops[2];
5869 Ops[0] = getRoot();
5870 Ops[1] = getValue(I.getArgOperand(0));
5871 SDValue Op = DAG.getNode(ISD::EH_SJLJ_SETJMP, sdl,
5872 DAG.getVTList(MVT::i32, MVT::Other), Ops);
5873 setValue(&I, Op.getValue(0));
5874 DAG.setRoot(Op.getValue(1));
5875 return nullptr;
5876 }
5877 case Intrinsic::eh_sjlj_longjmp:
5878 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, sdl, MVT::Other,
5879 getRoot(), getValue(I.getArgOperand(0))));
5880 return nullptr;
5881 case Intrinsic::eh_sjlj_setup_dispatch:
5882 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_SETUP_DISPATCH, sdl, MVT::Other,
5883 getRoot()));
5884 return nullptr;
5885 case Intrinsic::masked_gather:
5886 visitMaskedGather(I);
5887 return nullptr;
5888 case Intrinsic::masked_load:
5889 visitMaskedLoad(I);
5890 return nullptr;
5891 case Intrinsic::masked_scatter:
5892 visitMaskedScatter(I);
5893 return nullptr;
5894 case Intrinsic::masked_store:
5895 visitMaskedStore(I);
5896 return nullptr;
5897 case Intrinsic::masked_expandload:
5898 visitMaskedLoad(I, true /* IsExpanding */);
5899 return nullptr;
5900 case Intrinsic::masked_compressstore:
5901 visitMaskedStore(I, true /* IsCompressing */);
5902 return nullptr;
5903 case Intrinsic::x86_mmx_pslli_w:
5904 case Intrinsic::x86_mmx_pslli_d:
5905 case Intrinsic::x86_mmx_pslli_q:
5906 case Intrinsic::x86_mmx_psrli_w:
5907 case Intrinsic::x86_mmx_psrli_d:
5908 case Intrinsic::x86_mmx_psrli_q:
5909 case Intrinsic::x86_mmx_psrai_w:
5910 case Intrinsic::x86_mmx_psrai_d: {
5911 SDValue ShAmt = getValue(I.getArgOperand(1));
5912 if (isa<ConstantSDNode>(ShAmt)) {
5913 visitTargetIntrinsic(I, Intrinsic);
5914 return nullptr;
5915 }
5916 unsigned NewIntrinsic = 0;
5917 EVT ShAmtVT = MVT::v2i32;
5918 switch (Intrinsic) {
5919 case Intrinsic::x86_mmx_pslli_w:
5920 NewIntrinsic = Intrinsic::x86_mmx_psll_w;
5921 break;
5922 case Intrinsic::x86_mmx_pslli_d:
5923 NewIntrinsic = Intrinsic::x86_mmx_psll_d;
5924 break;
5925 case Intrinsic::x86_mmx_pslli_q:
5926 NewIntrinsic = Intrinsic::x86_mmx_psll_q;
5927 break;
5928 case Intrinsic::x86_mmx_psrli_w:
5929 NewIntrinsic = Intrinsic::x86_mmx_psrl_w;
5930 break;
5931 case Intrinsic::x86_mmx_psrli_d:
5932 NewIntrinsic = Intrinsic::x86_mmx_psrl_d;
5933 break;
5934 case Intrinsic::x86_mmx_psrli_q:
5935 NewIntrinsic = Intrinsic::x86_mmx_psrl_q;
5936 break;
5937 case Intrinsic::x86_mmx_psrai_w:
5938 NewIntrinsic = Intrinsic::x86_mmx_psra_w;
5939 break;
5940 case Intrinsic::x86_mmx_psrai_d:
5941 NewIntrinsic = Intrinsic::x86_mmx_psra_d;
5942 break;
5943 default: llvm_unreachable("Impossible intrinsic")::llvm::llvm_unreachable_internal("Impossible intrinsic", "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 5943)
; // Can't reach here.
5944 }
5945
5946 // The vector shift intrinsics with scalars uses 32b shift amounts but
5947 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
5948 // to be zero.
5949 // We must do this early because v2i32 is not a legal type.
5950 SDValue ShOps[2];
5951 ShOps[0] = ShAmt;
5952 ShOps[1] = DAG.getConstant(0, sdl, MVT::i32);
5953 ShAmt = DAG.getBuildVector(ShAmtVT, sdl, ShOps);
5954 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
5955 ShAmt = DAG.getNode(ISD::BITCAST, sdl, DestVT, ShAmt);
5956 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, sdl, DestVT,
5957 DAG.getConstant(NewIntrinsic, sdl, MVT::i32),
5958 getValue(I.getArgOperand(0)), ShAmt);
5959 setValue(&I, Res);
5960 return nullptr;
5961 }
5962 case Intrinsic::powi:
5963 setValue(&I, ExpandPowI(sdl, getValue(I.getArgOperand(0)),
5964 getValue(I.getArgOperand(1)), DAG));
5965 return nullptr;
5966 case Intrinsic::log:
5967 setValue(&I, expandLog(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
5968 return nullptr;
5969 case Intrinsic::log2:
5970 setValue(&I, expandLog2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
5971 return nullptr;
5972 case Intrinsic::log10:
5973 setValue(&I, expandLog10(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
5974 return nullptr;
5975 case Intrinsic::exp:
5976 setValue(&I, expandExp(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
5977 return nullptr;
5978 case Intrinsic::exp2:
5979 setValue(&I, expandExp2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
5980 return nullptr;
5981 case Intrinsic::pow:
5982 setValue(&I, expandPow(sdl, getValue(I.getArgOperand(0)),
5983 getValue(I.getArgOperand(1)), DAG, TLI));
5984 return nullptr;
5985 case Intrinsic::sqrt:
5986 case Intrinsic::fabs:
5987 case Intrinsic::sin:
5988 case Intrinsic::cos:
5989 case Intrinsic::floor:
5990 case Intrinsic::ceil:
5991 case Intrinsic::trunc:
5992 case Intrinsic::rint:
5993 case Intrinsic::nearbyint:
5994 case Intrinsic::round:
5995 case Intrinsic::canonicalize: {
5996 unsigned Opcode;
5997 switch (Intrinsic) {
5998 default: llvm_unreachable("Impossible intrinsic")::llvm::llvm_unreachable_internal("Impossible intrinsic", "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 5998)
; // Can't reach here.
5999 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break;
6000 case Intrinsic::fabs: Opcode = ISD::FABS; break;
6001 case Intrinsic::sin: Opcode = ISD::FSIN; break;
6002 case Intrinsic::cos: Opcode = ISD::FCOS; break;
6003 case Intrinsic::floor: Opcode = ISD::FFLOOR; break;
6004 case Intrinsic::ceil: Opcode = ISD::FCEIL; break;
6005 case Intrinsic::trunc: Opcode = ISD::FTRUNC; break;
6006 case Intrinsic::rint: Opcode = ISD::FRINT; break;
6007 case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break;
6008 case Intrinsic::round: Opcode = ISD::FROUND; break;
6009 case Intrinsic::canonicalize: Opcode = ISD::FCANONICALIZE; break;
6010 }
6011
6012 setValue(&I, DAG.getNode(Opcode, sdl,
6013 getValue(I.getArgOperand(0)).getValueType(),
6014 getValue(I.getArgOperand(0))));
6015 return nullptr;
6016 }
6017 case Intrinsic::minnum: {
6018 auto VT = getValue(I.getArgOperand(0)).getValueType();
6019 unsigned Opc =
6020 I.hasNoNaNs() && TLI.isOperationLegalOrCustom(ISD::FMINIMUM, VT)
6021 ? ISD::FMINIMUM
6022 : ISD::FMINNUM;
6023 setValue(&I, DAG.getNode(Opc, sdl, VT,
6024 getValue(I.getArgOperand(0)),
6025 getValue(I.getArgOperand(1))));
6026 return nullptr;
6027 }
6028 case Intrinsic::maxnum: {
6029 auto VT = getValue(I.getArgOperand(0)).getValueType();
6030 unsigned Opc =
6031 I.hasNoNaNs() && TLI.isOperationLegalOrCustom(ISD::FMAXIMUM, VT)
6032 ? ISD::FMAXIMUM
6033 : ISD::FMAXNUM;
6034 setValue(&I, DAG.getNode(Opc, sdl, VT,
6035 getValue(I.getArgOperand(0)),
6036 getValue(I.getArgOperand(1))));
6037 return nullptr;
6038 }
6039 case Intrinsic::minimum:
6040 setValue(&I, DAG.getNode(ISD::FMINIMUM, sdl,
6041 getValue(I.getArgOperand(0)).getValueType(),
6042 getValue(I.getArgOperand(0)),
6043 getValue(I.getArgOperand(1))));
6044 return nullptr;
6045 case Intrinsic::maximum:
6046 setValue(&I, DAG.getNode(ISD::FMAXIMUM, sdl,
6047 getValue(I.getArgOperand(0)).getValueType(),
6048 getValue(I.getArgOperand(0)),
6049 getValue(I.getArgOperand(1))));
6050 return nullptr;
6051 case Intrinsic::copysign:
6052 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, sdl,
6053 getValue(I.getArgOperand(0)).getValueType(),
6054 getValue(I.getArgOperand(0)),
6055 getValue(I.getArgOperand(1))));
6056 return nullptr;
6057 case Intrinsic::fma:
6058 setValue(&I, DAG.getNode(ISD::FMA, sdl,
6059 getValue(I.getArgOperand(0)).getValueType(),
6060 getValue(I.getArgOperand(0)),
6061 getValue(I.getArgOperand(1)),
6062 getValue(I.getArgOperand(2))));
6063 return nullptr;
6064 case Intrinsic::experimental_constrained_fadd:
6065 case Intrinsic::experimental_constrained_fsub:
6066 case Intrinsic::experimental_constrained_fmul:
6067 case Intrinsic::experimental_constrained_fdiv:
6068 case Intrinsic::experimental_constrained_frem:
6069 case Intrinsic::experimental_constrained_fma:
6070 case Intrinsic::experimental_constrained_sqrt:
6071 case Intrinsic::experimental_constrained_pow:
6072 case Intrinsic::experimental_constrained_powi:
6073 case Intrinsic::experimental_constrained_sin:
6074 case Intrinsic::experimental_constrained_cos:
6075 case Intrinsic::experimental_constrained_exp:
6076 case Intrinsic::experimental_constrained_exp2:
6077 case Intrinsic::experimental_constrained_log:
6078 case Intrinsic::experimental_constrained_log10:
6079 case Intrinsic::experimental_constrained_log2:
6080 case Intrinsic::experimental_constrained_rint:
6081 case Intrinsic::experimental_constrained_nearbyint:
6082 case Intrinsic::experimental_constrained_maxnum:
6083 case Intrinsic::experimental_constrained_minnum:
6084 case Intrinsic::experimental_constrained_ceil:
6085 case Intrinsic::experimental_constrained_floor:
6086 case Intrinsic::experimental_constrained_round:
6087 case Intrinsic::experimental_constrained_trunc:
6088 visitConstrainedFPIntrinsic(cast<ConstrainedFPIntrinsic>(I));
6089 return nullptr;
6090 case Intrinsic::fmuladd: {
6091 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
6092 if (TM.Options.AllowFPOpFusion != FPOpFusion::Strict &&
6093 TLI.isFMAFasterThanFMulAndFAdd(VT)) {
6094 setValue(&I, DAG.getNode(ISD::FMA, sdl,
6095 getValue(I.getArgOperand(0)).getValueType(),
6096 getValue(I.getArgOperand(0)),
6097 getValue(I.getArgOperand(1)),
6098 getValue(I.getArgOperand(2))));
6099 } else {
6100 // TODO: Intrinsic calls should have fast-math-flags.
6101 SDValue Mul = DAG.getNode(ISD::FMUL, sdl,
6102 getValue(I.getArgOperand(0)).getValueType(),
6103 getValue(I.getArgOperand(0)),
6104 getValue(I.getArgOperand(1)));
6105 SDValue Add = DAG.getNode(ISD::FADD, sdl,
6106 getValue(I.getArgOperand(0)).getValueType(),
6107 Mul,
6108 getValue(I.getArgOperand(2)));
6109 setValue(&I, Add);
6110 }
6111 return nullptr;
6112 }
6113 case Intrinsic::convert_to_fp16:
6114 setValue(&I, DAG.getNode(ISD::BITCAST, sdl, MVT::i16,
6115 DAG.getNode(ISD::FP_ROUND, sdl, MVT::f16,
6116 getValue(I.getArgOperand(0)),
6117 DAG.getTargetConstant(0, sdl,
6118 MVT::i32))));
6119 return nullptr;
6120 case Intrinsic::convert_from_fp16:
6121 setValue(&I, DAG.getNode(ISD::FP_EXTEND, sdl,
6122 TLI.getValueType(DAG.getDataLayout(), I.getType()),
6123 DAG.getNode(ISD::BITCAST, sdl, MVT::f16,
6124 getValue(I.getArgOperand(0)))));
6125 return nullptr;
6126 case Intrinsic::pcmarker: {
6127 SDValue Tmp = getValue(I.getArgOperand(0));
6128 DAG.setRoot(DAG.getNode(ISD::PCMARKER, sdl, MVT::Other, getRoot(), Tmp));
6129 return nullptr;
6130 }
6131 case Intrinsic::readcyclecounter: {
6132 SDValue Op = getRoot();
6133 Res = DAG.getNode(ISD::READCYCLECOUNTER, sdl,
6134 DAG.getVTList(MVT::i64, MVT::Other), Op);
6135 setValue(&I, Res);
6136 DAG.setRoot(Res.getValue(1));
6137 return nullptr;
6138 }
6139 case Intrinsic::bitreverse:
6140 setValue(&I, DAG.getNode(ISD::BITREVERSE, sdl,
6141 getValue(I.getArgOperand(0)).getValueType(),
6142 getValue(I.getArgOperand(0))));
6143 return nullptr;
6144 case Intrinsic::bswap:
6145 setValue(&I, DAG.getNode(ISD::BSWAP, sdl,
6146 getValue(I.getArgOperand(0)).getValueType(),
6147 getValue(I.getArgOperand(0))));
6148 return nullptr;
6149 case Intrinsic::cttz: {
6150 SDValue Arg = getValue(I.getArgOperand(0));
6151 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
6152 EVT Ty = Arg.getValueType();
6153 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTTZ : ISD::CTTZ_ZERO_UNDEF,
6154 sdl, Ty, Arg));
6155 return nullptr;
6156 }
6157 case Intrinsic::ctlz: {
6158 SDValue Arg = getValue(I.getArgOperand(0));
6159 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
6160 EVT Ty = Arg.getValueType();
6161 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTLZ : ISD::CTLZ_ZERO_UNDEF,
6162 sdl, Ty, Arg));
6163 return nullptr;
6164 }
6165 case Intrinsic::ctpop: {
6166 SDValue Arg = getValue(I.getArgOperand(0));
6167 EVT Ty = Arg.getValueType();
6168 setValue(&I, DAG.getNode(ISD::CTPOP, sdl, Ty, Arg));
6169 return nullptr;
6170 }
6171 case Intrinsic::fshl:
6172 case Intrinsic::fshr: {
6173 bool IsFSHL = Intrinsic == Intrinsic::fshl;
6174 SDValue X = getValue(I.getArgOperand(0));
6175 SDValue Y = getValue(I.getArgOperand(1));
6176 SDValue Z = getValue(I.getArgOperand(2));
6177 EVT VT = X.getValueType();
6178 SDValue BitWidthC = DAG.getConstant(VT.getScalarSizeInBits(), sdl, VT);
6179 SDValue Zero = DAG.getConstant(0, sdl, VT);
6180 SDValue ShAmt = DAG.getNode(ISD::UREM, sdl, VT, Z, BitWidthC);
6181
6182 auto FunnelOpcode = IsFSHL ? ISD::FSHL : ISD::FSHR;
6183 if (TLI.isOperationLegalOrCustom(FunnelOpcode, VT)) {
6184 setValue(&I, DAG.getNode(FunnelOpcode, sdl, VT, X, Y, Z));
6185 return nullptr;
6186 }
6187
6188 // When X == Y, this is rotate. If the data type has a power-of-2 size, we
6189 // avoid the select that is necessary in the general case to filter out
6190 // the 0-shift possibility that leads to UB.
6191 if (X == Y && isPowerOf2_32(VT.getScalarSizeInBits())) {
6192 auto RotateOpcode = IsFSHL ? ISD::ROTL : ISD::ROTR;
6193 if (TLI.isOperationLegalOrCustom(RotateOpcode, VT)) {
6194 setValue(&I, DAG.getNode(RotateOpcode, sdl, VT, X, Z));
6195 return nullptr;
6196 }
6197
6198 // Some targets only rotate one way. Try the opposite direction.
6199 RotateOpcode = IsFSHL ? ISD::ROTR : ISD::ROTL;
6200 if (TLI.isOperationLegalOrCustom(RotateOpcode, VT)) {
6201 // Negate the shift amount because it is safe to ignore the high bits.
6202 SDValue NegShAmt = DAG.getNode(ISD::SUB, sdl, VT, Zero, Z);
6203 setValue(&I, DAG.getNode(RotateOpcode, sdl, VT, X, NegShAmt));
6204 return nullptr;
6205 }
6206
6207 // fshl (rotl): (X << (Z % BW)) | (X >> ((0 - Z) % BW))
6208 // fshr (rotr): (X << ((0 - Z) % BW)) | (X >> (Z % BW))
6209 SDValue NegZ = DAG.getNode(ISD::SUB, sdl, VT, Zero, Z);
6210 SDValue NShAmt = DAG.getNode(ISD::UREM, sdl, VT, NegZ, BitWidthC);
6211 SDValue ShX = DAG.getNode(ISD::SHL, sdl, VT, X, IsFSHL ? ShAmt : NShAmt);
6212 SDValue ShY = DAG.getNode(ISD::SRL, sdl, VT, X, IsFSHL ? NShAmt : ShAmt);
6213 setValue(&I, DAG.getNode(ISD::OR, sdl, VT, ShX, ShY));
6214 return nullptr;
6215 }
6216
6217 // fshl: (X << (Z % BW)) | (Y >> (BW - (Z % BW)))
6218 // fshr: (X << (BW - (Z % BW))) | (Y >> (Z % BW))
6219 SDValue InvShAmt = DAG.getNode(ISD::SUB, sdl, VT, BitWidthC, ShAmt);
6220 SDValue ShX = DAG.getNode(ISD::SHL, sdl, VT, X, IsFSHL ? ShAmt : InvShAmt);
6221 SDValue ShY = DAG.getNode(ISD::SRL, sdl, VT, Y, IsFSHL ? InvShAmt : ShAmt);
6222 SDValue Or = DAG.getNode(ISD::OR, sdl, VT, ShX, ShY);
6223
6224 // If (Z % BW == 0), then the opposite direction shift is shift-by-bitwidth,
6225 // and that is undefined. We must compare and select to avoid UB.
6226 EVT CCVT = MVT::i1;
6227 if (VT.isVector())
6228 CCVT = EVT::getVectorVT(*Context, CCVT, VT.getVectorNumElements());
6229
6230 // For fshl, 0-shift returns the 1st arg (X).
6231 // For fshr, 0-shift returns the 2nd arg (Y).
6232 SDValue IsZeroShift = DAG.getSetCC(sdl, CCVT, ShAmt, Zero, ISD::SETEQ);
6233 setValue(&I, DAG.getSelect(sdl, VT, IsZeroShift, IsFSHL ? X : Y, Or));
6234 return nullptr;
6235 }
6236 case Intrinsic::sadd_sat: {
6237 SDValue Op1 = getValue(I.getArgOperand(0));
6238 SDValue Op2 = getValue(I.getArgOperand(1));
6239 setValue(&I, DAG.getNode(ISD::SADDSAT, sdl, Op1.getValueType(), Op1, Op2));
6240 return nullptr;
6241 }
6242 case Intrinsic::uadd_sat: {
6243 SDValue Op1 = getValue(I.getArgOperand(0));
6244 SDValue Op2 = getValue(I.getArgOperand(1));
6245 setValue(&I, DAG.getNode(ISD::UADDSAT, sdl, Op1.getValueType(), Op1, Op2));
6246 return nullptr;
6247 }
6248 case Intrinsic::ssub_sat: {
6249 SDValue Op1 = getValue(I.getArgOperand(0));
6250 SDValue Op2 = getValue(I.getArgOperand(1));
6251 setValue(&I, DAG.getNode(ISD::SSUBSAT, sdl, Op1.getValueType(), Op1, Op2));
6252 return nullptr;
6253 }
6254 case Intrinsic::usub_sat: {
6255 SDValue Op1 = getValue(I.getArgOperand(0));
6256 SDValue Op2 = getValue(I.getArgOperand(1));
6257 setValue(&I, DAG.getNode(ISD::USUBSAT, sdl, Op1.getValueType(), Op1, Op2));
6258 return nullptr;
6259 }
6260 case Intrinsic::smul_fix:
6261 case Intrinsic::umul_fix: {
6262 SDValue Op1 = getValue(I.getArgOperand(0));
6263 SDValue Op2 = getValue(I.getArgOperand(1));
6264 SDValue Op3 = getValue(I.getArgOperand(2));
6265 setValue(&I, DAG.getNode(FixedPointIntrinsicToOpcode(Intrinsic), sdl,
6266 Op1.getValueType(), Op1, Op2, Op3));
6267 return nullptr;
6268 }
6269 case Intrinsic::stacksave: {
6270 SDValue Op = getRoot();
6271 Res = DAG.getNode(
6272 ISD::STACKSAVE, sdl,
6273 DAG.getVTList(TLI.getPointerTy(DAG.getDataLayout()), MVT::Other), Op);
6274 setValue(&I, Res);
6275 DAG.setRoot(Res.getValue(1));
6276 return nullptr;
6277 }
6278 case Intrinsic::stackrestore:
6279 Res = getValue(I.getArgOperand(0));
6280 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, sdl, MVT::Other, getRoot(), Res));
6281 return nullptr;
6282 case Intrinsic::get_dynamic_area_offset: {
6283 SDValue Op = getRoot();
6284 EVT PtrTy = TLI.getPointerTy(DAG.getDataLayout());
6285 EVT ResTy = TLI.getValueType(DAG.getDataLayout(), I.getType());
6286 // Result type for @llvm.get.dynamic.area.offset should match PtrTy for
6287 // target.
6288 if (PtrTy.getSizeInBits() < ResTy.getSizeInBits())
6289 report_fatal_error("Wrong result type for @llvm.get.dynamic.area.offset"
6290 " intrinsic!");
6291 Res = DAG.getNode(ISD::GET_DYNAMIC_AREA_OFFSET, sdl, DAG.getVTList(ResTy),
6292 Op);
6293 DAG.setRoot(Op);
6294 setValue(&I, Res);
6295 return nullptr;
6296 }
6297 case Intrinsic::stackguard: {
6298 EVT PtrTy = TLI.getPointerTy(DAG.getDataLayout());
6299 MachineFunction &MF = DAG.getMachineFunction();
6300 const Module &M = *MF.getFunction().getParent();
6301 SDValue Chain = getRoot();
6302 if (TLI.useLoadStackGuardNode()) {
6303 Res = getLoadStackGuard(DAG, sdl, Chain);
6304 } else {
6305 const Value *Global = TLI.getSDagStackGuard(M);
6306 unsigned Align = DL->getPrefTypeAlignment(Global->getType());
6307 Res = DAG.getLoad(PtrTy, sdl, Chain, getValue(Global),
6308 MachinePointerInfo(Global, 0), Align,
6309 MachineMemOperand::MOVolatile);
6310 }
6311 if (TLI.useStackGuardXorFP())
6312 Res = TLI.emitStackGuardXorFP(DAG, Res, sdl);
6313 DAG.setRoot(Chain);
6314 setValue(&I, Res);
6315 return nullptr;
6316 }
6317 case Intrinsic::stackprotector: {
6318 // Emit code into the DAG to store the stack guard onto the stack.
6319 MachineFunction &MF = DAG.getMachineFunction();
6320 MachineFrameInfo &MFI = MF.getFrameInfo();
6321 EVT PtrTy = TLI.getPointerTy(DAG.getDataLayout());
6322 SDValue Src, Chain = getRoot();
6323
6324 if (TLI.useLoadStackGuardNode())
6325 Src = getLoadStackGuard(DAG, sdl, Chain);
6326 else
6327 Src = getValue(I.getArgOperand(0)); // The guard's value.
6328
6329 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1));
6330
6331 int FI = FuncInfo.StaticAllocaMap[Slot];
6332 MFI.setStackProtectorIndex(FI);
6333
6334 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
6335
6336 // Store the stack protector onto the stack.
6337 Res = DAG.getStore(Chain, sdl, Src, FIN, MachinePointerInfo::getFixedStack(
6338 DAG.getMachineFunction(), FI),
6339 /* Alignment = */ 0, MachineMemOperand::MOVolatile);
6340 setValue(&I, Res);
6341 DAG.setRoot(Res);
6342 return nullptr;
6343 }
6344 case Intrinsic::objectsize: {
6345 // If we don't know by now, we're never going to know.
6346 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1));
6347
6348 assert(CI && "Non-constant type in __builtin_object_size?")((CI && "Non-constant type in __builtin_object_size?"
) ? static_cast<void> (0) : __assert_fail ("CI && \"Non-constant type in __builtin_object_size?\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 6348, __PRETTY_FUNCTION__))
;
6349
6350 SDValue Arg = getValue(I.getCalledValue());
6351 EVT Ty = Arg.getValueType();
6352
6353 if (CI->isZero())
6354 Res = DAG.getConstant(-1ULL, sdl, Ty);
6355 else
6356 Res = DAG.getConstant(0, sdl, Ty);
6357
6358 setValue(&I, Res);
6359 return nullptr;
6360 }
6361
6362 case Intrinsic::is_constant:
6363 // If this wasn't constant-folded away by now, then it's not a
6364 // constant.
6365 setValue(&I, DAG.getConstant(0, sdl, MVT::i1));
6366 return nullptr;
6367
6368 case Intrinsic::annotation:
6369 case Intrinsic::ptr_annotation:
6370 case Intrinsic::launder_invariant_group:
6371 case Intrinsic::strip_invariant_group:
6372 // Drop the intrinsic, but forward the value
6373 setValue(&I, getValue(I.getOperand(0)));
6374 return nullptr;
6375 case Intrinsic::assume:
6376 case Intrinsic::var_annotation:
6377 case Intrinsic::sideeffect:
6378 // Discard annotate attributes, assumptions, and artificial side-effects.
6379 return nullptr;
6380
6381 case Intrinsic::codeview_annotation: {
6382 // Emit a label associated with this metadata.
6383 MachineFunction &MF = DAG.getMachineFunction();
6384 MCSymbol *Label =
6385 MF.getMMI().getContext().createTempSymbol("annotation", true);
6386 Metadata *MD = cast<MetadataAsValue>(I.getArgOperand(0))->getMetadata();
6387 MF.addCodeViewAnnotation(Label, cast<MDNode>(MD));
6388 Res = DAG.getLabelNode(ISD::ANNOTATION_LABEL, sdl, getRoot(), Label);
6389 DAG.setRoot(Res);
6390 return nullptr;
6391 }
6392
6393 case Intrinsic::init_trampoline: {
6394 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts());
6395
6396 SDValue Ops[6];
6397 Ops[0] = getRoot();
6398 Ops[1] = getValue(I.getArgOperand(0));
6399 Ops[2] = getValue(I.getArgOperand(1));
6400 Ops[3] = getValue(I.getArgOperand(2));
6401 Ops[4] = DAG.getSrcValue(I.getArgOperand(0));
6402 Ops[5] = DAG.getSrcValue(F);
6403
6404 Res = DAG.getNode(ISD::INIT_TRAMPOLINE, sdl, MVT::Other, Ops);
6405
6406 DAG.setRoot(Res);
6407 return nullptr;
6408 }
6409 case Intrinsic::adjust_trampoline:
6410 setValue(&I, DAG.getNode(ISD::ADJUST_TRAMPOLINE, sdl,
6411 TLI.getPointerTy(DAG.getDataLayout()),
6412 getValue(I.getArgOperand(0))));
6413 return nullptr;
6414 case Intrinsic::gcroot: {
6415 assert(DAG.getMachineFunction().getFunction().hasGC() &&((DAG.getMachineFunction().getFunction().hasGC() && "only valid in functions with gc specified, enforced by Verifier"
) ? static_cast<void> (0) : __assert_fail ("DAG.getMachineFunction().getFunction().hasGC() && \"only valid in functions with gc specified, enforced by Verifier\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 6416, __PRETTY_FUNCTION__))
6416 "only valid in functions with gc specified, enforced by Verifier")((DAG.getMachineFunction().getFunction().hasGC() && "only valid in functions with gc specified, enforced by Verifier"
) ? static_cast<void> (0) : __assert_fail ("DAG.getMachineFunction().getFunction().hasGC() && \"only valid in functions with gc specified, enforced by Verifier\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 6416, __PRETTY_FUNCTION__))
;
6417 assert(GFI && "implied by previous")((GFI && "implied by previous") ? static_cast<void
> (0) : __assert_fail ("GFI && \"implied by previous\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 6417, __PRETTY_FUNCTION__))
;
6418 const Value *Alloca = I.getArgOperand(0)->stripPointerCasts();
6419 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1));
6420
6421 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
6422 GFI->addStackRoot(FI->getIndex(), TypeMap);
6423 return nullptr;
6424 }
6425 case Intrinsic::gcread:
6426 case Intrinsic::gcwrite:
6427 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!")::llvm::llvm_unreachable_internal("GC failed to lower gcread/gcwrite intrinsics!"
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 6427)
;
6428 case Intrinsic::flt_rounds:
6429 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, sdl, MVT::i32));
6430 return nullptr;
6431
6432 case Intrinsic::expect:
6433 // Just replace __builtin_expect(exp, c) with EXP.
6434 setValue(&I, getValue(I.getArgOperand(0)));
6435 return nullptr;
6436
6437 case Intrinsic::debugtrap:
6438 case Intrinsic::trap: {
6439 StringRef TrapFuncName =
6440 I.getAttributes()
6441 .getAttribute(AttributeList::FunctionIndex, "trap-func-name")
6442 .getValueAsString();
6443 if (TrapFuncName.empty()) {
6444 ISD::NodeType Op = (Intrinsic == Intrinsic::trap) ?
6445 ISD::TRAP : ISD::DEBUGTRAP;
6446 DAG.setRoot(DAG.getNode(Op, sdl,MVT::Other, getRoot()));
6447 return nullptr;
6448 }
6449 TargetLowering::ArgListTy Args;
6450
6451 TargetLowering::CallLoweringInfo CLI(DAG);
6452 CLI.setDebugLoc(sdl).setChain(getRoot()).setLibCallee(
6453 CallingConv::C, I.getType(),
6454 DAG.getExternalSymbol(TrapFuncName.data(),
6455 TLI.getPointerTy(DAG.getDataLayout())),
6456 std::move(Args));
6457
6458 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
6459 DAG.setRoot(Result.second);
6460 return nullptr;
6461 }
6462
6463 case Intrinsic::uadd_with_overflow:
6464 case Intrinsic::sadd_with_overflow:
6465 case Intrinsic::usub_with_overflow:
6466 case Intrinsic::ssub_with_overflow:
6467 case Intrinsic::umul_with_overflow:
6468 case Intrinsic::smul_with_overflow: {
6469 ISD::NodeType Op;
6470 switch (Intrinsic) {
6471 default: llvm_unreachable("Impossible intrinsic")::llvm::llvm_unreachable_internal("Impossible intrinsic", "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 6471)
; // Can't reach here.
6472 case Intrinsic::uadd_with_overflow: Op = ISD::UADDO; break;
6473 case Intrinsic::sadd_with_overflow: Op = ISD::SADDO; break;
6474 case Intrinsic::usub_with_overflow: Op = ISD::USUBO; break;
6475 case Intrinsic::ssub_with_overflow: Op = ISD::SSUBO; break;
6476 case Intrinsic::umul_with_overflow: Op = ISD::UMULO; break;
6477 case Intrinsic::smul_with_overflow: Op = ISD::SMULO; break;
6478 }
6479 SDValue Op1 = getValue(I.getArgOperand(0));
6480 SDValue Op2 = getValue(I.getArgOperand(1));
6481
6482 EVT ResultVT = Op1.getValueType();
6483 EVT OverflowVT = MVT::i1;
6484 if (ResultVT.isVector())
6485 OverflowVT = EVT::getVectorVT(
6486 *Context, OverflowVT, ResultVT.getVectorNumElements());
6487
6488 SDVTList VTs = DAG.getVTList(ResultVT, OverflowVT);
6489 setValue(&I, DAG.getNode(Op, sdl, VTs, Op1, Op2));
6490 return nullptr;
6491 }
6492 case Intrinsic::prefetch: {
6493 SDValue Ops[5];
6494 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
6495 auto Flags = rw == 0 ? MachineMemOperand::MOLoad :MachineMemOperand::MOStore;
6496 Ops[0] = DAG.getRoot();
6497 Ops[1] = getValue(I.getArgOperand(0));
6498 Ops[2] = getValue(I.getArgOperand(1));
6499 Ops[3] = getValue(I.getArgOperand(2));
6500 Ops[4] = getValue(I.getArgOperand(3));
6501 SDValue Result = DAG.getMemIntrinsicNode(ISD::PREFETCH, sdl,
6502 DAG.getVTList(MVT::Other), Ops,
6503 EVT::getIntegerVT(*Context, 8),
6504 MachinePointerInfo(I.getArgOperand(0)),
6505 0, /* align */
6506 Flags);
6507
6508 // Chain the prefetch in parallell with any pending loads, to stay out of
6509 // the way of later optimizations.
6510 PendingLoads.push_back(Result);
6511 Result = getRoot();
6512 DAG.setRoot(Result);
6513 return nullptr;
6514 }
6515 case Intrinsic::lifetime_start:
6516 case Intrinsic::lifetime_end: {
6517 bool IsStart = (Intrinsic == Intrinsic::lifetime_start);
6518 // Stack coloring is not enabled in O0, discard region information.
6519 if (TM.getOptLevel() == CodeGenOpt::None)
6520 return nullptr;
6521
6522 const int64_t ObjectSize =
6523 cast<ConstantInt>(I.getArgOperand(0))->getSExtValue();
6524 Value *const ObjectPtr = I.getArgOperand(1);
6525 SmallVector<const Value *, 4> Allocas;
6526 GetUnderlyingObjects(ObjectPtr, Allocas, *DL);
6527
6528 for (SmallVectorImpl<const Value*>::iterator Object = Allocas.begin(),
6529 E = Allocas.end(); Object != E; ++Object) {
6530 const AllocaInst *LifetimeObject = dyn_cast_or_null<AllocaInst>(*Object);
6531
6532 // Could not find an Alloca.
6533 if (!LifetimeObject)
6534 continue;
6535
6536 // First check that the Alloca is static, otherwise it won't have a
6537 // valid frame index.
6538 auto SI = FuncInfo.StaticAllocaMap.find(LifetimeObject);
6539 if (SI == FuncInfo.StaticAllocaMap.end())
6540 return nullptr;
6541
6542 const int FrameIndex = SI->second;
6543 int64_t Offset;
6544 if (GetPointerBaseWithConstantOffset(
6545 ObjectPtr, Offset, DAG.getDataLayout()) != LifetimeObject)
6546 Offset = -1; // Cannot determine offset from alloca to lifetime object.
6547 Res = DAG.getLifetimeNode(IsStart, sdl, getRoot(), FrameIndex, ObjectSize,
6548 Offset);
6549 DAG.setRoot(Res);
6550 }
6551 return nullptr;
6552 }
6553 case Intrinsic::invariant_start:
6554 // Discard region information.
6555 setValue(&I, DAG.getUNDEF(TLI.getPointerTy(DAG.getDataLayout())));
6556 return nullptr;
6557 case Intrinsic::invariant_end:
6558 // Discard region information.
6559 return nullptr;
6560 case Intrinsic::clear_cache:
6561 return TLI.getClearCacheBuiltinName();
6562 case Intrinsic::donothing:
6563 // ignore
6564 return nullptr;
6565 case Intrinsic::experimental_stackmap:
6566 visitStackmap(I);
6567 return nullptr;
6568 case Intrinsic::experimental_patchpoint_void:
6569 case Intrinsic::experimental_patchpoint_i64:
6570 visitPatchpoint(&I);
6571 return nullptr;
6572 case Intrinsic::experimental_gc_statepoint:
6573 LowerStatepoint(ImmutableStatepoint(&I));
6574 return nullptr;
6575 case Intrinsic::experimental_gc_result:
6576 visitGCResult(cast<GCResultInst>(I));
6577 return nullptr;
6578 case Intrinsic::experimental_gc_relocate:
6579 visitGCRelocate(cast<GCRelocateInst>(I));
6580 return nullptr;
6581 case Intrinsic::instrprof_increment:
6582 llvm_unreachable("instrprof failed to lower an increment")::llvm::llvm_unreachable_internal("instrprof failed to lower an increment"
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 6582)
;
6583 case Intrinsic::instrprof_value_profile:
6584 llvm_unreachable("instrprof failed to lower a value profiling call")::llvm::llvm_unreachable_internal("instrprof failed to lower a value profiling call"
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 6584)
;
6585 case Intrinsic::localescape: {
6586 MachineFunction &MF = DAG.getMachineFunction();
6587 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
6588
6589 // Directly emit some LOCAL_ESCAPE machine instrs. Label assignment emission
6590 // is the same on all targets.
6591 for (unsigned Idx = 0, E = I.getNumArgOperands(); Idx < E; ++Idx) {
6592 Value *Arg = I.getArgOperand(Idx)->stripPointerCasts();
6593 if (isa<ConstantPointerNull>(Arg))
6594 continue; // Skip null pointers. They represent a hole in index space.
6595 AllocaInst *Slot = cast<AllocaInst>(Arg);
6596 assert(FuncInfo.StaticAllocaMap.count(Slot) &&((FuncInfo.StaticAllocaMap.count(Slot) && "can only escape static allocas"
) ? static_cast<void> (0) : __assert_fail ("FuncInfo.StaticAllocaMap.count(Slot) && \"can only escape static allocas\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 6597, __PRETTY_FUNCTION__))
6597 "can only escape static allocas")((FuncInfo.StaticAllocaMap.count(Slot) && "can only escape static allocas"
) ? static_cast<void> (0) : __assert_fail ("FuncInfo.StaticAllocaMap.count(Slot) && \"can only escape static allocas\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 6597, __PRETTY_FUNCTION__))
;
6598 int FI = FuncInfo.StaticAllocaMap[Slot];
6599 MCSymbol *FrameAllocSym =
6600 MF.getMMI().getContext().getOrCreateFrameAllocSymbol(
6601 GlobalValue::dropLLVMManglingEscape(MF.getName()), Idx);
6602 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, dl,
6603 TII->get(TargetOpcode::LOCAL_ESCAPE))
6604 .addSym(FrameAllocSym)
6605 .addFrameIndex(FI);
6606 }
6607
6608 return nullptr;
6609 }
6610
6611 case Intrinsic::localrecover: {
6612 // i8* @llvm.localrecover(i8* %fn, i8* %fp, i32 %idx)
6613 MachineFunction &MF = DAG.getMachineFunction();
6614 MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout(), 0);
6615
6616 // Get the symbol that defines the frame offset.
6617 auto *Fn = cast<Function>(I.getArgOperand(0)->stripPointerCasts());
6618 auto *Idx = cast<ConstantInt>(I.getArgOperand(2));
6619 unsigned IdxVal =
6620 unsigned(Idx->getLimitedValue(std::numeric_limits<int>::max()));
6621 MCSymbol *FrameAllocSym =
6622 MF.getMMI().getContext().getOrCreateFrameAllocSymbol(
6623 GlobalValue::dropLLVMManglingEscape(Fn->getName()), IdxVal);
6624
6625 // Create a MCSymbol for the label to avoid any target lowering
6626 // that would make this PC relative.
6627 SDValue OffsetSym = DAG.getMCSymbol(FrameAllocSym, PtrVT);
6628 SDValue OffsetVal =
6629 DAG.getNode(ISD::LOCAL_RECOVER, sdl, PtrVT, OffsetSym);
6630
6631 // Add the offset to the FP.
6632 Value *FP = I.getArgOperand(1);
6633 SDValue FPVal = getValue(FP);
6634 SDValue Add = DAG.getNode(ISD::ADD, sdl, PtrVT, FPVal, OffsetVal);
6635 setValue(&I, Add);
6636
6637 return nullptr;
6638 }
6639
6640 case Intrinsic::eh_exceptionpointer:
6641 case Intrinsic::eh_exceptioncode: {
6642 // Get the exception pointer vreg, copy from it, and resize it to fit.
6643 const auto *CPI = cast<CatchPadInst>(I.getArgOperand(0));
6644 MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout());
6645 const TargetRegisterClass *PtrRC = TLI.getRegClassFor(PtrVT);
6646 unsigned VReg = FuncInfo.getCatchPadExceptionPointerVReg(CPI, PtrRC);
6647 SDValue N =
6648 DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(), VReg, PtrVT);
6649 if (Intrinsic == Intrinsic::eh_exceptioncode)
6650 N = DAG.getZExtOrTrunc(N, getCurSDLoc(), MVT::i32);
6651 setValue(&I, N);
6652 return nullptr;
6653 }
6654 case Intrinsic::xray_customevent: {
6655 // Here we want to make sure that the intrinsic behaves as if it has a
6656 // specific calling convention, and only for x86_64.
6657 // FIXME: Support other platforms later.
6658 const auto &Triple = DAG.getTarget().getTargetTriple();
6659 if (Triple.getArch() != Triple::x86_64 || !Triple.isOSLinux())
6660 return nullptr;
6661
6662 SDLoc DL = getCurSDLoc();
6663 SmallVector<SDValue, 8> Ops;
6664
6665 // We want to say that we always want the arguments in registers.
6666 SDValue LogEntryVal = getValue(I.getArgOperand(0));
6667 SDValue StrSizeVal = getValue(I.getArgOperand(1));
6668 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
6669 SDValue Chain = getRoot();
6670 Ops.push_back(LogEntryVal);
6671 Ops.push_back(StrSizeVal);
6672 Ops.push_back(Chain);
6673
6674 // We need to enforce the calling convention for the callsite, so that
6675 // argument ordering is enforced correctly, and that register allocation can
6676 // see that some registers may be assumed clobbered and have to preserve
6677 // them across calls to the intrinsic.
6678 MachineSDNode *MN = DAG.getMachineNode(TargetOpcode::PATCHABLE_EVENT_CALL,
6679 DL, NodeTys, Ops);
6680 SDValue patchableNode = SDValue(MN, 0);
6681 DAG.setRoot(patchableNode);
6682 setValue(&I, patchableNode);
6683 return nullptr;
6684 }
6685 case Intrinsic::xray_typedevent: {
6686 // Here we want to make sure that the intrinsic behaves as if it has a
6687 // specific calling convention, and only for x86_64.
6688 // FIXME: Support other platforms later.
6689 const auto &Triple = DAG.getTarget().getTargetTriple();
6690 if (Triple.getArch() != Triple::x86_64 || !Triple.isOSLinux())
6691 return nullptr;
6692
6693 SDLoc DL = getCurSDLoc();
6694 SmallVector<SDValue, 8> Ops;
6695
6696 // We want to say that we always want the arguments in registers.
6697 // It's unclear to me how manipulating the selection DAG here forces callers
6698 // to provide arguments in registers instead of on the stack.
6699 SDValue LogTypeId = getValue(I.getArgOperand(0));
6700 SDValue LogEntryVal = getValue(I.getArgOperand(1));
6701 SDValue StrSizeVal = getValue(I.getArgOperand(2));
6702 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
6703 SDValue Chain = getRoot();
6704 Ops.push_back(LogTypeId);
6705 Ops.push_back(LogEntryVal);
6706 Ops.push_back(StrSizeVal);
6707 Ops.push_back(Chain);
6708
6709 // We need to enforce the calling convention for the callsite, so that
6710 // argument ordering is enforced correctly, and that register allocation can
6711 // see that some registers may be assumed clobbered and have to preserve
6712 // them across calls to the intrinsic.
6713 MachineSDNode *MN = DAG.getMachineNode(
6714 TargetOpcode::PATCHABLE_TYPED_EVENT_CALL, DL, NodeTys, Ops);
6715 SDValue patchableNode = SDValue(MN, 0);
6716 DAG.setRoot(patchableNode);
6717 setValue(&I, patchableNode);
6718 return nullptr;
6719 }
6720 case Intrinsic::experimental_deoptimize:
6721 LowerDeoptimizeCall(&I);
6722 return nullptr;
6723
6724 case Intrinsic::experimental_vector_reduce_fadd:
6725 case Intrinsic::experimental_vector_reduce_fmul:
6726 case Intrinsic::experimental_vector_reduce_add:
6727 case Intrinsic::experimental_vector_reduce_mul:
6728 case Intrinsic::experimental_vector_reduce_and:
6729 case Intrinsic::experimental_vector_reduce_or:
6730 case Intrinsic::experimental_vector_reduce_xor:
6731 case Intrinsic::experimental_vector_reduce_smax:
6732 case Intrinsic::experimental_vector_reduce_smin:
6733 case Intrinsic::experimental_vector_reduce_umax:
6734 case Intrinsic::experimental_vector_reduce_umin:
6735 case Intrinsic::experimental_vector_reduce_fmax:
6736 case Intrinsic::experimental_vector_reduce_fmin:
6737 visitVectorReduce(I, Intrinsic);
6738 return nullptr;
6739
6740 case Intrinsic::icall_branch_funnel: {
6741 SmallVector<SDValue, 16> Ops;
6742 Ops.push_back(DAG.getRoot());
6743 Ops.push_back(getValue(I.getArgOperand(0)));
6744
6745 int64_t Offset;
6746 auto *Base = dyn_cast<GlobalObject>(GetPointerBaseWithConstantOffset(
6747 I.getArgOperand(1), Offset, DAG.getDataLayout()));
6748 if (!Base)
6749 report_fatal_error(
6750 "llvm.icall.branch.funnel operand must be a GlobalValue");
6751 Ops.push_back(DAG.getTargetGlobalAddress(Base, getCurSDLoc(), MVT::i64, 0));
6752
6753 struct BranchFunnelTarget {
6754 int64_t Offset;
6755 SDValue Target;
6756 };
6757 SmallVector<BranchFunnelTarget, 8> Targets;
6758
6759 for (unsigned Op = 1, N = I.getNumArgOperands(); Op != N; Op += 2) {
6760 auto *ElemBase = dyn_cast<GlobalObject>(GetPointerBaseWithConstantOffset(
6761 I.getArgOperand(Op), Offset, DAG.getDataLayout()));
6762 if (ElemBase != Base)
6763 report_fatal_error("all llvm.icall.branch.funnel operands must refer "
6764 "to the same GlobalValue");
6765
6766 SDValue Val = getValue(I.getArgOperand(Op + 1));
6767 auto *GA = dyn_cast<GlobalAddressSDNode>(Val);
6768 if (!GA)
6769 report_fatal_error(
6770 "llvm.icall.branch.funnel operand must be a GlobalValue");
6771 Targets.push_back({Offset, DAG.getTargetGlobalAddress(
6772 GA->getGlobal(), getCurSDLoc(),
6773 Val.getValueType(), GA->getOffset())});
6774 }
6775 llvm::sort(Targets,
6776 [](const BranchFunnelTarget &T1, const BranchFunnelTarget &T2) {
6777 return T1.Offset < T2.Offset;
6778 });
6779
6780 for (auto &T : Targets) {
6781 Ops.push_back(DAG.getTargetConstant(T.Offset, getCurSDLoc(), MVT::i32));
6782 Ops.push_back(T.Target);
6783 }
6784
6785 SDValue N(DAG.getMachineNode(TargetOpcode::ICALL_BRANCH_FUNNEL,
6786 getCurSDLoc(), MVT::Other, Ops),
6787 0);
6788 DAG.setRoot(N);
6789 setValue(&I, N);
6790 HasTailCall = true;
6791 return nullptr;
6792 }
6793
6794 case Intrinsic::wasm_landingpad_index:
6795 // Information this intrinsic contained has been transferred to
6796 // MachineFunction in SelectionDAGISel::PrepareEHLandingPad. We can safely
6797 // delete it now.
6798 return nullptr;
6799 }
6800}
6801
6802void SelectionDAGBuilder::visitConstrainedFPIntrinsic(
6803 const ConstrainedFPIntrinsic &FPI) {
6804 SDLoc sdl = getCurSDLoc();
6805 unsigned Opcode;
6806 switch (FPI.getIntrinsicID()) {
6807 default: llvm_unreachable("Impossible intrinsic")::llvm::llvm_unreachable_internal("Impossible intrinsic", "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 6807)
; // Can't reach here.
6808 case Intrinsic::experimental_constrained_fadd:
6809 Opcode = ISD::STRICT_FADD;
6810 break;
6811 case Intrinsic::experimental_constrained_fsub:
6812 Opcode = ISD::STRICT_FSUB;
6813 break;
6814 case Intrinsic::experimental_constrained_fmul:
6815 Opcode = ISD::STRICT_FMUL;
6816 break;
6817 case Intrinsic::experimental_constrained_fdiv:
6818 Opcode = ISD::STRICT_FDIV;
6819 break;
6820 case Intrinsic::experimental_constrained_frem:
6821 Opcode = ISD::STRICT_FREM;
6822 break;
6823 case Intrinsic::experimental_constrained_fma:
6824 Opcode = ISD::STRICT_FMA;
6825 break;
6826 case Intrinsic::experimental_constrained_sqrt:
6827 Opcode = ISD::STRICT_FSQRT;
6828 break;
6829 case Intrinsic::experimental_constrained_pow:
6830 Opcode = ISD::STRICT_FPOW;
6831 break;
6832 case Intrinsic::experimental_constrained_powi:
6833 Opcode = ISD::STRICT_FPOWI;
6834 break;
6835 case Intrinsic::experimental_constrained_sin:
6836 Opcode = ISD::STRICT_FSIN;
6837 break;
6838 case Intrinsic::experimental_constrained_cos:
6839 Opcode = ISD::STRICT_FCOS;
6840 break;
6841 case Intrinsic::experimental_constrained_exp:
6842 Opcode = ISD::STRICT_FEXP;
6843 break;
6844 case Intrinsic::experimental_constrained_exp2:
6845 Opcode = ISD::STRICT_FEXP2;
6846 break;
6847 case Intrinsic::experimental_constrained_log:
6848 Opcode = ISD::STRICT_FLOG;
6849 break;
6850 case Intrinsic::experimental_constrained_log10:
6851 Opcode = ISD::STRICT_FLOG10;
6852 break;
6853 case Intrinsic::experimental_constrained_log2:
6854 Opcode = ISD::STRICT_FLOG2;
6855 break;
6856 case Intrinsic::experimental_constrained_rint:
6857 Opcode = ISD::STRICT_FRINT;
6858 break;
6859 case Intrinsic::experimental_constrained_nearbyint:
6860 Opcode = ISD::STRICT_FNEARBYINT;
6861 break;
6862 case Intrinsic::experimental_constrained_maxnum:
6863 Opcode = ISD::STRICT_FMAXNUM;
6864 break;
6865 case Intrinsic::experimental_constrained_minnum:
6866 Opcode = ISD::STRICT_FMINNUM;
6867 break;
6868 case Intrinsic::experimental_constrained_ceil:
6869 Opcode = ISD::STRICT_FCEIL;
6870 break;
6871 case Intrinsic::experimental_constrained_floor:
6872 Opcode = ISD::STRICT_FFLOOR;
6873 break;
6874 case Intrinsic::experimental_constrained_round:
6875 Opcode = ISD::STRICT_FROUND;
6876 break;
6877 case Intrinsic::experimental_constrained_trunc:
6878 Opcode = ISD::STRICT_FTRUNC;
6879 break;
6880 }
6881 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6882 SDValue Chain = getRoot();
6883 SmallVector<EVT, 4> ValueVTs;
6884 ComputeValueVTs(TLI, DAG.getDataLayout(), FPI.getType(), ValueVTs);
6885 ValueVTs.push_back(MVT::Other); // Out chain
6886
6887 SDVTList VTs = DAG.getVTList(ValueVTs);
6888 SDValue Result;
6889 if (FPI.isUnaryOp())
6890 Result = DAG.getNode(Opcode, sdl, VTs,
6891 { Chain, getValue(FPI.getArgOperand(0)) });
6892 else if (FPI.isTernaryOp())
6893 Result = DAG.getNode(Opcode, sdl, VTs,
6894 { Chain, getValue(FPI.getArgOperand(0)),
6895 getValue(FPI.getArgOperand(1)),
6896 getValue(FPI.getArgOperand(2)) });
6897 else
6898 Result = DAG.getNode(Opcode, sdl, VTs,
6899 { Chain, getValue(FPI.getArgOperand(0)),
6900 getValue(FPI.getArgOperand(1)) });
6901
6902 assert(Result.getNode()->getNumValues() == 2)((Result.getNode()->getNumValues() == 2) ? static_cast<
void> (0) : __assert_fail ("Result.getNode()->getNumValues() == 2"
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 6902, __PRETTY_FUNCTION__))
;
6903 SDValue OutChain = Result.getValue(1);
6904 DAG.setRoot(OutChain);
6905 SDValue FPResult = Result.getValue(0);
6906 setValue(&FPI, FPResult);
6907}
6908
6909std::pair<SDValue, SDValue>
6910SelectionDAGBuilder::lowerInvokable(TargetLowering::CallLoweringInfo &CLI,
6911 const BasicBlock *EHPadBB) {
6912 MachineFunction &MF = DAG.getMachineFunction();
6913 MachineModuleInfo &MMI = MF.getMMI();
6914 MCSymbol *BeginLabel = nullptr;
6915
6916 if (EHPadBB) {
6917 // Insert a label before the invoke call to mark the try range. This can be
6918 // used to detect deletion of the invoke via the MachineModuleInfo.
6919 BeginLabel = MMI.getContext().createTempSymbol();
6920
6921 // For SjLj, keep track of which landing pads go with which invokes
6922 // so as to maintain the ordering of pads in the LSDA.
6923 unsigned CallSiteIndex = MMI.getCurrentCallSite();
6924 if (CallSiteIndex) {
6925 MF.setCallSiteBeginLabel(BeginLabel, CallSiteIndex);
6926 LPadToCallSiteMap[FuncInfo.MBBMap[EHPadBB]].push_back(CallSiteIndex);
6927
6928 // Now that the call site is handled, stop tracking it.
6929 MMI.setCurrentCallSite(0);
6930 }
6931
6932 // Both PendingLoads and PendingExports must be flushed here;
6933 // this call might not return.
6934 (void)getRoot();
6935 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getControlRoot(), BeginLabel));
6936
6937 CLI.setChain(getRoot());
6938 }
6939 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6940 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
6941
6942 assert((CLI.IsTailCall || Result.second.getNode()) &&(((CLI.IsTailCall || Result.second.getNode()) && "Non-null chain expected with non-tail call!"
) ? static_cast<void> (0) : __assert_fail ("(CLI.IsTailCall || Result.second.getNode()) && \"Non-null chain expected with non-tail call!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 6943, __PRETTY_FUNCTION__))
6943 "Non-null chain expected with non-tail call!")(((CLI.IsTailCall || Result.second.getNode()) && "Non-null chain expected with non-tail call!"
) ? static_cast<void> (0) : __assert_fail ("(CLI.IsTailCall || Result.second.getNode()) && \"Non-null chain expected with non-tail call!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 6943, __PRETTY_FUNCTION__))
;
6944 assert((Result.second.getNode() || !Result.first.getNode()) &&(((Result.second.getNode() || !Result.first.getNode()) &&
"Null value expected with tail call!") ? static_cast<void
> (0) : __assert_fail ("(Result.second.getNode() || !Result.first.getNode()) && \"Null value expected with tail call!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 6945, __PRETTY_FUNCTION__))
6945 "Null value expected with tail call!")(((Result.second.getNode() || !Result.first.getNode()) &&
"Null value expected with tail call!") ? static_cast<void
> (0) : __assert_fail ("(Result.second.getNode() || !Result.first.getNode()) && \"Null value expected with tail call!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 6945, __PRETTY_FUNCTION__))
;
6946
6947 if (!Result.second.getNode()) {
6948 // As a special case, a null chain means that a tail call has been emitted
6949 // and the DAG root is already updated.
6950 HasTailCall = true;
6951
6952 // Since there's no actual continuation from this block, nothing can be
6953 // relying on us setting vregs for them.
6954 PendingExports.clear();
6955 } else {
6956 DAG.setRoot(Result.second);
6957 }
6958
6959 if (EHPadBB) {
6960 // Insert a label at the end of the invoke call to mark the try range. This
6961 // can be used to detect deletion of the invoke via the MachineModuleInfo.
6962 MCSymbol *EndLabel = MMI.getContext().createTempSymbol();
6963 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getRoot(), EndLabel));
6964
6965 // Inform MachineModuleInfo of range.
6966 auto Pers = classifyEHPersonality(FuncInfo.Fn->getPersonalityFn());
6967 // There is a platform (e.g. wasm) that uses funclet style IR but does not
6968 // actually use outlined funclets and their LSDA info style.
6969 if (MF.hasEHFunclets() && isFuncletEHPersonality(Pers)) {
6970 assert(CLI.CS)((CLI.CS) ? static_cast<void> (0) : __assert_fail ("CLI.CS"
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 6970, __PRETTY_FUNCTION__))
;
6971 WinEHFuncInfo *EHInfo = DAG.getMachineFunction().getWinEHFuncInfo();
6972 EHInfo->addIPToStateRange(cast<InvokeInst>(CLI.CS.getInstruction()),
6973 BeginLabel, EndLabel);
6974 } else if (!isScopedEHPersonality(Pers)) {
6975 MF.addInvoke(FuncInfo.MBBMap[EHPadBB], BeginLabel, EndLabel);
6976 }
6977 }
6978
6979 return Result;
6980}
6981
6982void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee,
6983 bool isTailCall,
6984 const BasicBlock *EHPadBB) {
6985 auto &DL = DAG.getDataLayout();
6986 FunctionType *FTy = CS.getFunctionType();
6987 Type *RetTy = CS.getType();
6988
6989 TargetLowering::ArgListTy Args;
6990 Args.reserve(CS.arg_size());
6991
6992 const Value *SwiftErrorVal = nullptr;
6993 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6994
6995 // We can't tail call inside a function with a swifterror argument. Lowering
6996 // does not support this yet. It would have to move into the swifterror
6997 // register before the call.
6998 auto *Caller = CS.getInstruction()->getParent()->getParent();
6999 if (TLI.supportSwiftError() &&
7000 Caller->getAttributes().hasAttrSomewhere(Attribute::SwiftError))
7001 isTailCall = false;
7002
7003 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
7004 i != e; ++i) {
7005 TargetLowering::ArgListEntry Entry;
7006 const Value *V = *i;
7007
7008 // Skip empty types
7009 if (V->getType()->isEmptyTy())
7010 continue;
7011
7012 SDValue ArgNode = getValue(V);
7013 Entry.Node = ArgNode; Entry.Ty = V->getType();
7014
7015 Entry.setAttributes(&CS, i - CS.arg_begin());
7016
7017 // Use swifterror virtual register as input to the call.
7018 if (Entry.IsSwiftError && TLI.supportSwiftError()) {
7019 SwiftErrorVal = V;
7020 // We find the virtual register for the actual swifterror argument.
7021 // Instead of using the Value, we use the virtual register instead.
7022 Entry.Node = DAG.getRegister(FuncInfo
7023 .getOrCreateSwiftErrorVRegUseAt(
7024 CS.getInstruction(), FuncInfo.MBB, V)
7025 .first,
7026 EVT(TLI.getPointerTy(DL)));
7027 }
7028
7029 Args.push_back(Entry);
7030
7031 // If we have an explicit sret argument that is an Instruction, (i.e., it
7032 // might point to function-local memory), we can't meaningfully tail-call.
7033 if (Entry.IsSRet && isa<Instruction>(V))
7034 isTailCall = false;
7035 }
7036
7037 // Check if target-independent constraints permit a tail call here.
7038 // Target-dependent constraints are checked within TLI->LowerCallTo.
7039 if (isTailCall && !isInTailCallPosition(CS, DAG.getTarget()))
7040 isTailCall = false;
7041
7042 // Disable tail calls if there is an swifterror argument. Targets have not
7043 // been updated to support tail calls.
7044 if (TLI.supportSwiftError() && SwiftErrorVal)
7045 isTailCall = false;
7046
7047 TargetLowering::CallLoweringInfo CLI(DAG);
7048 CLI.setDebugLoc(getCurSDLoc())
7049 .setChain(getRoot())
7050 .setCallee(RetTy, FTy, Callee, std::move(Args), CS)
7051 .setTailCall(isTailCall)
7052 .setConvergent(CS.isConvergent());
7053 std::pair<SDValue, SDValue> Result = lowerInvokable(CLI, EHPadBB);
7054
7055 if (Result.first.getNode()) {
7056 const Instruction *Inst = CS.getInstruction();
7057 Result.first = lowerRangeToAssertZExt(DAG, *Inst, Result.first);
7058 setValue(Inst, Result.first);
7059 }
7060
7061 // The last element of CLI.InVals has the SDValue for swifterror return.
7062 // Here we copy it to a virtual register and update SwiftErrorMap for
7063 // book-keeping.
7064 if (SwiftErrorVal && TLI.supportSwiftError()) {
7065 // Get the last element of InVals.
7066 SDValue Src = CLI.InVals.back();
7067 unsigned VReg; bool CreatedVReg;
7068 std::tie(VReg, CreatedVReg) =
7069 FuncInfo.getOrCreateSwiftErrorVRegDefAt(CS.getInstruction());
7070 SDValue CopyNode = CLI.DAG.getCopyToReg(Result.second, CLI.DL, VReg, Src);
7071 // We update the virtual register for the actual swifterror argument.
7072 if (CreatedVReg)
7073 FuncInfo.setCurrentSwiftErrorVReg(FuncInfo.MBB, SwiftErrorVal, VReg);
7074 DAG.setRoot(CopyNode);
7075 }
7076}
7077
7078static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT,
7079 SelectionDAGBuilder &Builder) {
7080 // Check to see if this load can be trivially constant folded, e.g. if the
7081 // input is from a string literal.
7082 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) {
7083 // Cast pointer to the type we really want to load.
7084 Type *LoadTy =
7085 Type::getIntNTy(PtrVal->getContext(), LoadVT.getScalarSizeInBits());
7086 if (LoadVT.isVector())
7087 LoadTy = VectorType::get(LoadTy, LoadVT.getVectorNumElements());
7088
7089 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput),
7090 PointerType::getUnqual(LoadTy));
7091
7092 if (const Constant *LoadCst = ConstantFoldLoadFromConstPtr(
7093 const_cast<Constant *>(LoadInput), LoadTy, *Builder.DL))
7094 return Builder.getValue(LoadCst);
7095 }
7096
7097 // Otherwise, we have to emit the load. If the pointer is to unfoldable but
7098 // still constant memory, the input chain can be the entry node.
7099 SDValue Root;
7100 bool ConstantMemory = false;
7101
7102 // Do not serialize (non-volatile) loads of constant memory with anything.
7103 if (Builder.AA && Builder.AA->pointsToConstantMemory(PtrVal)) {
7104 Root = Builder.DAG.getEntryNode();
7105 ConstantMemory = true;
7106 } else {
7107 // Do not serialize non-volatile loads against each other.
7108 Root = Builder.DAG.getRoot();
7109 }
7110
7111 SDValue Ptr = Builder.getValue(PtrVal);
7112 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurSDLoc(), Root,
7113 Ptr, MachinePointerInfo(PtrVal),
7114 /* Alignment = */ 1);
7115
7116 if (!ConstantMemory)
7117 Builder.PendingLoads.push_back(LoadVal.getValue(1));
7118 return LoadVal;
7119}
7120
7121/// Record the value for an instruction that produces an integer result,
7122/// converting the type where necessary.
7123void SelectionDAGBuilder::processIntegerCallValue(const Instruction &I,
7124 SDValue Value,
7125 bool IsSigned) {
7126 EVT VT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
7127 I.getType(), true);
7128 if (IsSigned)
7129 Value = DAG.getSExtOrTrunc(Value, getCurSDLoc(), VT);
7130 else
7131 Value = DAG.getZExtOrTrunc(Value, getCurSDLoc(), VT);
7132 setValue(&I, Value);
7133}
7134
7135/// See if we can lower a memcmp call into an optimized form. If so, return
7136/// true and lower it. Otherwise return false, and it will be lowered like a
7137/// normal call.
7138/// The caller already checked that \p I calls the appropriate LibFunc with a
7139/// correct prototype.
7140bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) {
7141 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1);
7142 const Value *Size = I.getArgOperand(2);
7143 const ConstantInt *CSize = dyn_cast<ConstantInt>(Size);
7144 if (CSize && CSize->getZExtValue() == 0) {
7145 EVT CallVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
7146 I.getType(), true);
7147 setValue(&I, DAG.getConstant(0, getCurSDLoc(), CallVT));
7148 return true;
7149 }
7150
7151 const SelectionDAGTargetInfo &TSI = DAG.getSelectionDAGInfo();
7152 std::pair<SDValue, SDValue> Res = TSI.EmitTargetCodeForMemcmp(
7153 DAG, getCurSDLoc(), DAG.getRoot(), getValue(LHS), getValue(RHS),
7154 getValue(Size), MachinePointerInfo(LHS), MachinePointerInfo(RHS));
7155 if (Res.first.getNode()) {
7156 processIntegerCallValue(I, Res.first, true);
7157 PendingLoads.push_back(Res.second);
7158 return true;
7159 }
7160
7161 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0
7162 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0
7163 if (!CSize || !isOnlyUsedInZeroEqualityComparison(&I))
7164 return false;
7165
7166 // If the target has a fast compare for the given size, it will return a
7167 // preferred load type for that size. Require that the load VT is legal and
7168 // that the target supports unaligned loads of that type. Otherwise, return
7169 // INVALID.
7170 auto hasFastLoadsAndCompare = [&](unsigned NumBits) {
7171 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7172 MVT LVT = TLI.hasFastEqualityCompare(NumBits);
7173 if (LVT != MVT::INVALID_SIMPLE_VALUE_TYPE) {
7174 // TODO: Handle 5 byte compare as 4-byte + 1 byte.
7175 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads.
7176 // TODO: Check alignment of src and dest ptrs.
7177 unsigned DstAS = LHS->getType()->getPointerAddressSpace();
7178 unsigned SrcAS = RHS->getType()->getPointerAddressSpace();
7179 if (!TLI.isTypeLegal(LVT) ||
7180 !TLI.allowsMisalignedMemoryAccesses(LVT, SrcAS) ||
7181 !TLI.allowsMisalignedMemoryAccesses(LVT, DstAS))
7182 LVT = MVT::INVALID_SIMPLE_VALUE_TYPE;
7183 }
7184
7185 return LVT;
7186 };
7187
7188 // This turns into unaligned loads. We only do this if the target natively
7189 // supports the MVT we'll be loading or if it is small enough (<= 4) that
7190 // we'll only produce a small number of byte loads.
7191 MVT LoadVT;
7192 unsigned NumBitsToCompare = CSize->getZExtValue() * 8;
7193 switch (NumBitsToCompare) {
7194 default:
7195 return false;
7196 case 16:
7197 LoadVT = MVT::i16;
7198 break;
7199 case 32:
7200 LoadVT = MVT::i32;
7201 break;
7202 case 64:
7203 case 128:
7204 case 256:
7205 LoadVT = hasFastLoadsAndCompare(NumBitsToCompare);
7206 break;
7207 }
7208
7209 if (LoadVT == MVT::INVALID_SIMPLE_VALUE_TYPE)
7210 return false;
7211
7212 SDValue LoadL = getMemCmpLoad(LHS, LoadVT, *this);
7213 SDValue LoadR = getMemCmpLoad(RHS, LoadVT, *this);
7214
7215 // Bitcast to a wide integer type if the loads are vectors.
7216 if (LoadVT.isVector()) {
7217 EVT CmpVT = EVT::getIntegerVT(LHS->getContext(), LoadVT.getSizeInBits());
7218 LoadL = DAG.getBitcast(CmpVT, LoadL);
7219 LoadR = DAG.getBitcast(CmpVT, LoadR);
7220 }
7221
7222 SDValue Cmp = DAG.getSetCC(getCurSDLoc(), MVT::i1, LoadL, LoadR, ISD::SETNE);
7223 processIntegerCallValue(I, Cmp, false);
7224 return true;
7225}
7226
7227/// See if we can lower a memchr call into an optimized form. If so, return
7228/// true and lower it. Otherwise return false, and it will be lowered like a
7229/// normal call.
7230/// The caller already checked that \p I calls the appropriate LibFunc with a
7231/// correct prototype.
7232bool SelectionDAGBuilder::visitMemChrCall(const CallInst &I) {
7233 const Value *Src = I.getArgOperand(0);
7234 const Value *Char = I.getArgOperand(1);
7235 const Value *Length = I.getArgOperand(2);
7236
7237 const SelectionDAGTargetInfo &TSI = DAG.getSelectionDAGInfo();
7238 std::pair<SDValue, SDValue> Res =
7239 TSI.EmitTargetCodeForMemchr(DAG, getCurSDLoc(), DAG.getRoot(),
7240 getValue(Src), getValue(Char), getValue(Length),
7241 MachinePointerInfo(Src));
7242 if (Res.first.getNode()) {
7243 setValue(&I, Res.first);
7244 PendingLoads.push_back(Res.second);
7245 return true;
7246 }
7247
7248 return false;
7249}
7250
7251/// See if we can lower a mempcpy call into an optimized form. If so, return
7252/// true and lower it. Otherwise return false, and it will be lowered like a
7253/// normal call.
7254/// The caller already checked that \p I calls the appropriate LibFunc with a
7255/// correct prototype.
7256bool SelectionDAGBuilder::visitMemPCpyCall(const CallInst &I) {
7257 SDValue Dst = getValue(I.getArgOperand(0));
7258 SDValue Src = getValue(I.getArgOperand(1));
7259 SDValue Size = getValue(I.getArgOperand(2));
7260
7261 unsigned DstAlign = DAG.InferPtrAlignment(Dst);
7262 unsigned SrcAlign = DAG.InferPtrAlignment(Src);
7263 unsigned Align = std::min(DstAlign, SrcAlign);
7264 if (Align == 0) // Alignment of one or both could not be inferred.
7265 Align = 1; // 0 and 1 both specify no alignment, but 0 is reserved.
7266
7267 bool isVol = false;
7268 SDLoc sdl = getCurSDLoc();
7269
7270 // In the mempcpy context we need to pass in a false value for isTailCall
7271 // because the return pointer needs to be adjusted by the size of
7272 // the copied memory.
7273 SDValue MC = DAG.getMemcpy(getRoot(), sdl, Dst, Src, Size, Align, isVol,
7274 false, /*isTailCall=*/false,
7275 MachinePointerInfo(I.getArgOperand(0)),
7276 MachinePointerInfo(I.getArgOperand(1)));
7277 assert(MC.getNode() != nullptr &&((MC.getNode() != nullptr && "** memcpy should not be lowered as TailCall in mempcpy context **"
) ? static_cast<void> (0) : __assert_fail ("MC.getNode() != nullptr && \"** memcpy should not be lowered as TailCall in mempcpy context **\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7278, __PRETTY_FUNCTION__))
7278 "** memcpy should not be lowered as TailCall in mempcpy context **")((MC.getNode() != nullptr && "** memcpy should not be lowered as TailCall in mempcpy context **"
) ? static_cast<void> (0) : __assert_fail ("MC.getNode() != nullptr && \"** memcpy should not be lowered as TailCall in mempcpy context **\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7278, __PRETTY_FUNCTION__))
;
7279 DAG.setRoot(MC);
7280
7281 // Check if Size needs to be truncated or extended.
7282 Size = DAG.getSExtOrTrunc(Size, sdl, Dst.getValueType());
7283
7284 // Adjust return pointer to point just past the last dst byte.
7285 SDValue DstPlusSize = DAG.getNode(ISD::ADD, sdl, Dst.getValueType(),
7286 Dst, Size);
7287 setValue(&I, DstPlusSize);
7288 return true;
7289}
7290
7291/// See if we can lower a strcpy call into an optimized form. If so, return
7292/// true and lower it, otherwise return false and it will be lowered like a
7293/// normal call.
7294/// The caller already checked that \p I calls the appropriate LibFunc with a
7295/// correct prototype.
7296bool SelectionDAGBuilder::visitStrCpyCall(const CallInst &I, bool isStpcpy) {
7297 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
7298
7299 const SelectionDAGTargetInfo &TSI = DAG.getSelectionDAGInfo();
7300 std::pair<SDValue, SDValue> Res =
7301 TSI.EmitTargetCodeForStrcpy(DAG, getCurSDLoc(), getRoot(),
7302 getValue(Arg0), getValue(Arg1),
7303 MachinePointerInfo(Arg0),
7304 MachinePointerInfo(Arg1), isStpcpy);
7305 if (Res.first.getNode()) {
7306 setValue(&I, Res.first);
7307 DAG.setRoot(Res.second);
7308 return true;
7309 }
7310
7311 return false;
7312}
7313
7314/// See if we can lower a strcmp call into an optimized form. If so, return
7315/// true and lower it, otherwise return false and it will be lowered like a
7316/// normal call.
7317/// The caller already checked that \p I calls the appropriate LibFunc with a
7318/// correct prototype.
7319bool SelectionDAGBuilder::visitStrCmpCall(const CallInst &I) {
7320 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
7321
7322 const SelectionDAGTargetInfo &TSI = DAG.getSelectionDAGInfo();
7323 std::pair<SDValue, SDValue> Res =
7324 TSI.EmitTargetCodeForStrcmp(DAG, getCurSDLoc(), DAG.getRoot(),
7325 getValue(Arg0), getValue(Arg1),
7326 MachinePointerInfo(Arg0),
7327 MachinePointerInfo(Arg1));
7328 if (Res.first.getNode()) {
7329 processIntegerCallValue(I, Res.first, true);
7330 PendingLoads.push_back(Res.second);
7331 return true;
7332 }
7333
7334 return false;
7335}
7336
7337/// See if we can lower a strlen call into an optimized form. If so, return
7338/// true and lower it, otherwise return false and it will be lowered like a
7339/// normal call.
7340/// The caller already checked that \p I calls the appropriate LibFunc with a
7341/// correct prototype.
7342bool SelectionDAGBuilder::visitStrLenCall(const CallInst &I) {
7343 const Value *Arg0 = I.getArgOperand(0);
7344
7345 const SelectionDAGTargetInfo &TSI = DAG.getSelectionDAGInfo();
7346 std::pair<SDValue, SDValue> Res =
7347 TSI.EmitTargetCodeForStrlen(DAG, getCurSDLoc(), DAG.getRoot(),
7348 getValue(Arg0), MachinePointerInfo(Arg0));
7349 if (Res.first.getNode()) {
7350 processIntegerCallValue(I, Res.first, false);
7351 PendingLoads.push_back(Res.second);
7352 return true;
7353 }
7354
7355 return false;
7356}
7357
7358/// See if we can lower a strnlen call into an optimized form. If so, return
7359/// true and lower it, otherwise return false and it will be lowered like a
7360/// normal call.
7361/// The caller already checked that \p I calls the appropriate LibFunc with a
7362/// correct prototype.
7363bool SelectionDAGBuilder::visitStrNLenCall(const CallInst &I) {
7364 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
7365
7366 const SelectionDAGTargetInfo &TSI = DAG.getSelectionDAGInfo();
7367 std::pair<SDValue, SDValue> Res =
7368 TSI.EmitTargetCodeForStrnlen(DAG, getCurSDLoc(), DAG.getRoot(),
7369 getValue(Arg0), getValue(Arg1),
7370 MachinePointerInfo(Arg0));
7371 if (Res.first.getNode()) {
7372 processIntegerCallValue(I, Res.first, false);
7373 PendingLoads.push_back(Res.second);
7374 return true;
7375 }
7376
7377 return false;
7378}
7379
7380/// See if we can lower a unary floating-point operation into an SDNode with
7381/// the specified Opcode. If so, return true and lower it, otherwise return
7382/// false and it will be lowered like a normal call.
7383/// The caller already checked that \p I calls the appropriate LibFunc with a
7384/// correct prototype.
7385bool SelectionDAGBuilder::visitUnaryFloatCall(const CallInst &I,
7386 unsigned Opcode) {
7387 // We already checked this call's prototype; verify it doesn't modify errno.
7388 if (!I.onlyReadsMemory())
7389 return false;
7390
7391 SDValue Tmp = getValue(I.getArgOperand(0));
7392 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), Tmp.getValueType(), Tmp));
7393 return true;
7394}
7395
7396/// See if we can lower a binary floating-point operation into an SDNode with
7397/// the specified Opcode. If so, return true and lower it. Otherwise return
7398/// false, and it will be lowered like a normal call.
7399/// The caller already checked that \p I calls the appropriate LibFunc with a
7400/// correct prototype.
7401bool SelectionDAGBuilder::visitBinaryFloatCall(const CallInst &I,
7402 unsigned Opcode) {
7403 // We already checked this call's prototype; verify it doesn't modify errno.
7404 if (!I.onlyReadsMemory())
7405 return false;
7406
7407 SDValue Tmp0 = getValue(I.getArgOperand(0));
7408 SDValue Tmp1 = getValue(I.getArgOperand(1));
7409 EVT VT = Tmp0.getValueType();
7410 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), VT, Tmp0, Tmp1));
7411 return true;
7412}
7413
7414void SelectionDAGBuilder::visitCall(const CallInst &I) {
7415 // Handle inline assembly differently.
7416 if (isa<InlineAsm>(I.getCalledValue())) {
7417 visitInlineAsm(&I);
7418 return;
7419 }
7420
7421 const char *RenameFn = nullptr;
7422 if (Function *F = I.getCalledFunction()) {
7423 if (F->isDeclaration()) {
7424 // Is this an LLVM intrinsic or a target-specific intrinsic?
7425 unsigned IID = F->getIntrinsicID();
7426 if (!IID)
7427 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo())
7428 IID = II->getIntrinsicID(F);
7429
7430 if (IID) {
7431 RenameFn = visitIntrinsicCall(I, IID);
7432 if (!RenameFn)
7433 return;
7434 }
7435 }
7436
7437 // Check for well-known libc/libm calls. If the function is internal, it
7438 // can't be a library call. Don't do the check if marked as nobuiltin for
7439 // some reason or the call site requires strict floating point semantics.
7440 LibFunc Func;
7441 if (!I.isNoBuiltin() && !I.isStrictFP() && !F->hasLocalLinkage() &&
7442 F->hasName() && LibInfo->getLibFunc(*F, Func) &&
7443 LibInfo->hasOptimizedCodeGen(Func)) {
7444 switch (Func) {
7445 default: break;
7446 case LibFunc_copysign:
7447 case LibFunc_copysignf:
7448 case LibFunc_copysignl:
7449 // We already checked this call's prototype; verify it doesn't modify
7450 // errno.
7451 if (I.onlyReadsMemory()) {
7452 SDValue LHS = getValue(I.getArgOperand(0));
7453 SDValue RHS = getValue(I.getArgOperand(1));
7454 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurSDLoc(),
7455 LHS.getValueType(), LHS, RHS));
7456 return;
7457 }
7458 break;
7459 case LibFunc_fabs:
7460 case LibFunc_fabsf:
7461 case LibFunc_fabsl:
7462 if (visitUnaryFloatCall(I, ISD::FABS))
7463 return;
7464 break;
7465 case LibFunc_fmin:
7466 case LibFunc_fminf:
7467 case LibFunc_fminl:
7468 if (visitBinaryFloatCall(I, ISD::FMINNUM))
7469 return;
7470 break;
7471 case LibFunc_fmax:
7472 case LibFunc_fmaxf:
7473 case LibFunc_fmaxl:
7474 if (visitBinaryFloatCall(I, ISD::FMAXNUM))
7475 return;
7476 break;
7477 case LibFunc_sin:
7478 case LibFunc_sinf:
7479 case LibFunc_sinl:
7480 if (visitUnaryFloatCall(I, ISD::FSIN))
7481 return;
7482 break;
7483 case LibFunc_cos:
7484 case LibFunc_cosf:
7485 case LibFunc_cosl:
7486 if (visitUnaryFloatCall(I, ISD::FCOS))
7487 return;
7488 break;
7489 case LibFunc_sqrt:
7490 case LibFunc_sqrtf:
7491 case LibFunc_sqrtl:
7492 case LibFunc_sqrt_finite:
7493 case LibFunc_sqrtf_finite:
7494 case LibFunc_sqrtl_finite:
7495 if (visitUnaryFloatCall(I, ISD::FSQRT))
7496 return;
7497 break;
7498 case LibFunc_floor:
7499 case LibFunc_floorf:
7500 case LibFunc_floorl:
7501 if (visitUnaryFloatCall(I, ISD::FFLOOR))
7502 return;
7503 break;
7504 case LibFunc_nearbyint:
7505 case LibFunc_nearbyintf:
7506 case LibFunc_nearbyintl:
7507 if (visitUnaryFloatCall(I, ISD::FNEARBYINT))
7508 return;
7509 break;
7510 case LibFunc_ceil:
7511 case LibFunc_ceilf:
7512 case LibFunc_ceill:
7513 if (visitUnaryFloatCall(I, ISD::FCEIL))
7514 return;
7515 break;
7516 case LibFunc_rint:
7517 case LibFunc_rintf:
7518 case LibFunc_rintl:
7519 if (visitUnaryFloatCall(I, ISD::FRINT))
7520 return;
7521 break;
7522 case LibFunc_round:
7523 case LibFunc_roundf:
7524 case LibFunc_roundl:
7525 if (visitUnaryFloatCall(I, ISD::FROUND))
7526 return;
7527 break;
7528 case LibFunc_trunc:
7529 case LibFunc_truncf:
7530 case LibFunc_truncl:
7531 if (visitUnaryFloatCall(I, ISD::FTRUNC))
7532 return;
7533 break;
7534 case LibFunc_log2:
7535 case LibFunc_log2f:
7536 case LibFunc_log2l:
7537 if (visitUnaryFloatCall(I, ISD::FLOG2))
7538 return;
7539 break;
7540 case LibFunc_exp2:
7541 case LibFunc_exp2f:
7542 case LibFunc_exp2l:
7543 if (visitUnaryFloatCall(I, ISD::FEXP2))
7544 return;
7545 break;
7546 case LibFunc_memcmp:
7547 if (visitMemCmpCall(I))
7548 return;
7549 break;
7550 case LibFunc_mempcpy:
7551 if (visitMemPCpyCall(I))
7552 return;
7553 break;
7554 case LibFunc_memchr:
7555 if (visitMemChrCall(I))
7556 return;
7557 break;
7558 case LibFunc_strcpy:
7559 if (visitStrCpyCall(I, false))
7560 return;
7561 break;
7562 case LibFunc_stpcpy:
7563 if (visitStrCpyCall(I, true))
7564 return;
7565 break;
7566 case LibFunc_strcmp:
7567 if (visitStrCmpCall(I))
7568 return;
7569 break;
7570 case LibFunc_strlen:
7571 if (visitStrLenCall(I))
7572 return;
7573 break;
7574 case LibFunc_strnlen:
7575 if (visitStrNLenCall(I))
7576 return;
7577 break;
7578 }
7579 }
7580 }
7581
7582 SDValue Callee;
7583 if (!RenameFn)
7584 Callee = getValue(I.getCalledValue());
7585 else
7586 Callee = DAG.getExternalSymbol(
7587 RenameFn,
7588 DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout()));
7589
7590 // Deopt bundles are lowered in LowerCallSiteWithDeoptBundle, and we don't
7591 // have to do anything here to lower funclet bundles.
7592 assert(!I.hasOperandBundlesOtherThan(((!I.hasOperandBundlesOtherThan( {LLVMContext::OB_deopt, LLVMContext
::OB_funclet}) && "Cannot lower calls with arbitrary operand bundles!"
) ? static_cast<void> (0) : __assert_fail ("!I.hasOperandBundlesOtherThan( {LLVMContext::OB_deopt, LLVMContext::OB_funclet}) && \"Cannot lower calls with arbitrary operand bundles!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7594, __PRETTY_FUNCTION__))
7593 {LLVMContext::OB_deopt, LLVMContext::OB_funclet}) &&((!I.hasOperandBundlesOtherThan( {LLVMContext::OB_deopt, LLVMContext
::OB_funclet}) && "Cannot lower calls with arbitrary operand bundles!"
) ? static_cast<void> (0) : __assert_fail ("!I.hasOperandBundlesOtherThan( {LLVMContext::OB_deopt, LLVMContext::OB_funclet}) && \"Cannot lower calls with arbitrary operand bundles!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7594, __PRETTY_FUNCTION__))
7594 "Cannot lower calls with arbitrary operand bundles!")((!I.hasOperandBundlesOtherThan( {LLVMContext::OB_deopt, LLVMContext
::OB_funclet}) && "Cannot lower calls with arbitrary operand bundles!"
) ? static_cast<void> (0) : __assert_fail ("!I.hasOperandBundlesOtherThan( {LLVMContext::OB_deopt, LLVMContext::OB_funclet}) && \"Cannot lower calls with arbitrary operand bundles!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7594, __PRETTY_FUNCTION__))
;
7595
7596 if (I.countOperandBundlesOfType(LLVMContext::OB_deopt))
7597 LowerCallSiteWithDeoptBundle(&I, Callee, nullptr);
7598 else
7599 // Check if we can potentially perform a tail call. More detailed checking
7600 // is be done within LowerCallTo, after more information about the call is
7601 // known.
7602 LowerCallTo(&I, Callee, I.isTailCall());
7603}
7604
7605namespace {
7606
7607/// AsmOperandInfo - This contains information for each constraint that we are
7608/// lowering.
7609class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
7610public:
7611 /// CallOperand - If this is the result output operand or a clobber
7612 /// this is null, otherwise it is the incoming operand to the CallInst.
7613 /// This gets modified as the asm is processed.
7614 SDValue CallOperand;
7615
7616 /// AssignedRegs - If this is a register or register class operand, this
7617 /// contains the set of register corresponding to the operand.
7618 RegsForValue AssignedRegs;
7619
7620 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info)
7621 : TargetLowering::AsmOperandInfo(info), CallOperand(nullptr, 0) {
7622 }
7623
7624 /// Whether or not this operand accesses memory
7625 bool hasMemory(const TargetLowering &TLI) const {
7626 // Indirect operand accesses access memory.
7627 if (isIndirect)
7628 return true;
7629
7630 for (const auto &Code : Codes)
7631 if (TLI.getConstraintType(Code) == TargetLowering::C_Memory)
7632 return true;
7633
7634 return false;
7635 }
7636
7637 /// getCallOperandValEVT - Return the EVT of the Value* that this operand
7638 /// corresponds to. If there is no Value* for this operand, it returns
7639 /// MVT::Other.
7640 EVT getCallOperandValEVT(LLVMContext &Context, const TargetLowering &TLI,
7641 const DataLayout &DL) const {
7642 if (!CallOperandVal) return MVT::Other;
7643
7644 if (isa<BasicBlock>(CallOperandVal))
7645 return TLI.getPointerTy(DL);
7646
7647 llvm::Type *OpTy = CallOperandVal->getType();
7648
7649 // FIXME: code duplicated from TargetLowering::ParseConstraints().
7650 // If this is an indirect operand, the operand is a pointer to the
7651 // accessed type.
7652 if (isIndirect) {
7653 PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
7654 if (!PtrTy)
7655 report_fatal_error("Indirect operand for inline asm not a pointer!");
7656 OpTy = PtrTy->getElementType();
7657 }
7658
7659 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
7660 if (StructType *STy = dyn_cast<StructType>(OpTy))
7661 if (STy->getNumElements() == 1)
7662 OpTy = STy->getElementType(0);
7663
7664 // If OpTy is not a single value, it may be a struct/union that we
7665 // can tile with integers.
7666 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
7667 unsigned BitSize = DL.getTypeSizeInBits(OpTy);
7668 switch (BitSize) {
7669 default: break;
7670 case 1:
7671 case 8:
7672 case 16:
7673 case 32:
7674 case 64:
7675 case 128:
7676 OpTy = IntegerType::get(Context, BitSize);
7677 break;
7678 }
7679 }
7680
7681 return TLI.getValueType(DL, OpTy, true);
7682 }
7683};
7684
7685using SDISelAsmOperandInfoVector = SmallVector<SDISelAsmOperandInfo, 16>;
7686
7687} // end anonymous namespace
7688
7689/// Make sure that the output operand \p OpInfo and its corresponding input
7690/// operand \p MatchingOpInfo have compatible constraint types (otherwise error
7691/// out).
7692static void patchMatchingInput(const SDISelAsmOperandInfo &OpInfo,
7693 SDISelAsmOperandInfo &MatchingOpInfo,
7694 SelectionDAG &DAG) {
7695 if (OpInfo.ConstraintVT == MatchingOpInfo.ConstraintVT)
7696 return;
7697
7698 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
7699 const auto &TLI = DAG.getTargetLoweringInfo();
7700
7701 std::pair<unsigned, const TargetRegisterClass *> MatchRC =
7702 TLI.getRegForInlineAsmConstraint(TRI, OpInfo.ConstraintCode,
7703 OpInfo.ConstraintVT);
7704 std::pair<unsigned, const TargetRegisterClass *> InputRC =
7705 TLI.getRegForInlineAsmConstraint(TRI, MatchingOpInfo.ConstraintCode,
7706 MatchingOpInfo.ConstraintVT);
7707 if ((OpInfo.ConstraintVT.isInteger() !=
7708 MatchingOpInfo.ConstraintVT.isInteger()) ||
7709 (MatchRC.second != InputRC.second)) {
7710 // FIXME: error out in a more elegant fashion
7711 report_fatal_error("Unsupported asm: input constraint"
7712 " with a matching output constraint of"
7713 " incompatible type!");
7714 }
7715 MatchingOpInfo.ConstraintVT = OpInfo.ConstraintVT;
7716}
7717
7718/// Get a direct memory input to behave well as an indirect operand.
7719/// This may introduce stores, hence the need for a \p Chain.
7720/// \return The (possibly updated) chain.
7721static SDValue getAddressForMemoryInput(SDValue Chain, const SDLoc &Location,
7722 SDISelAsmOperandInfo &OpInfo,
7723 SelectionDAG &DAG) {
7724 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7725
7726 // If we don't have an indirect input, put it in the constpool if we can,
7727 // otherwise spill it to a stack slot.
7728 // TODO: This isn't quite right. We need to handle these according to
7729 // the addressing mode that the constraint wants. Also, this may take
7730 // an additional register for the computation and we don't want that
7731 // either.
7732
7733 // If the operand is a float, integer, or vector constant, spill to a
7734 // constant pool entry to get its address.
7735 const Value *OpVal = OpInfo.CallOperandVal;
7736 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
7737 isa<ConstantVector>(OpVal) || isa<ConstantDataVector>(OpVal)) {
7738 OpInfo.CallOperand = DAG.getConstantPool(
7739 cast<Constant>(OpVal), TLI.getPointerTy(DAG.getDataLayout()));
7740 return Chain;
7741 }
7742
7743 // Otherwise, create a stack slot and emit a store to it before the asm.
7744 Type *Ty = OpVal->getType();
7745 auto &DL = DAG.getDataLayout();
7746 uint64_t TySize = DL.getTypeAllocSize(Ty);
7747 unsigned Align = DL.getPrefTypeAlignment(Ty);
7748 MachineFunction &MF = DAG.getMachineFunction();
7749 int SSFI = MF.getFrameInfo().CreateStackObject(TySize, Align, false);
7750 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getFrameIndexTy(DL));
7751 Chain = DAG.getTruncStore(Chain, Location, OpInfo.CallOperand, StackSlot,
7752 MachinePointerInfo::getFixedStack(MF, SSFI),
7753 TLI.getMemValueType(DL, Ty));
7754 OpInfo.CallOperand = StackSlot;
7755
7756 return Chain;
7757}
7758
7759/// GetRegistersForValue - Assign registers (virtual or physical) for the
7760/// specified operand. We prefer to assign virtual registers, to allow the
7761/// register allocator to handle the assignment process. However, if the asm
7762/// uses features that we can't model on machineinstrs, we have SDISel do the
7763/// allocation. This produces generally horrible, but correct, code.
7764///
7765/// OpInfo describes the operand
7766/// RefOpInfo describes the matching operand if any, the operand otherwise
7767static void GetRegistersForValue(SelectionDAG &DAG, const SDLoc &DL,
7768 SDISelAsmOperandInfo &OpInfo,
7769 SDISelAsmOperandInfo &RefOpInfo) {
7770 LLVMContext &Context = *DAG.getContext();
7771 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7772
7773 MachineFunction &MF = DAG.getMachineFunction();
7774 SmallVector<unsigned, 4> Regs;
7775 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
7776
7777 // No work to do for memory operations.
7778 if (OpInfo.ConstraintType == TargetLowering::C_Memory)
7779 return;
7780
7781 // If this is a constraint for a single physreg, or a constraint for a
7782 // register class, find it.
7783 unsigned AssignedReg;
7784 const TargetRegisterClass *RC;
7785 std::tie(AssignedReg, RC) = TLI.getRegForInlineAsmConstraint(
7786 &TRI, RefOpInfo.ConstraintCode, RefOpInfo.ConstraintVT);
7787 // RC is unset only on failure. Return immediately.
7788 if (!RC)
7789 return;
7790
7791 // Get the actual register value type. This is important, because the user
7792 // may have asked for (e.g.) the AX register in i32 type. We need to
7793 // remember that AX is actually i16 to get the right extension.
7794 const MVT RegVT = *TRI.legalclasstypes_begin(*RC);
7795
7796 if (OpInfo.ConstraintVT != MVT::Other) {
7797 // If this is an FP operand in an integer register (or visa versa), or more
7798 // generally if the operand value disagrees with the register class we plan
7799 // to stick it in, fix the operand type.
7800 //
7801 // If this is an input value, the bitcast to the new type is done now.
7802 // Bitcast for output value is done at the end of visitInlineAsm().
7803 if ((OpInfo.Type == InlineAsm::isOutput ||
7804 OpInfo.Type == InlineAsm::isInput) &&
7805 !TRI.isTypeLegalForClass(*RC, OpInfo.ConstraintVT)) {
7806 // Try to convert to the first EVT that the reg class contains. If the
7807 // types are identical size, use a bitcast to convert (e.g. two differing
7808 // vector types). Note: output bitcast is done at the end of
7809 // visitInlineAsm().
7810 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) {
7811 // Exclude indirect inputs while they are unsupported because the code
7812 // to perform the load is missing and thus OpInfo.CallOperand still
7813 // refers to the input address rather than the pointed-to value.
7814 if (OpInfo.Type == InlineAsm::isInput && !OpInfo.isIndirect)
7815 OpInfo.CallOperand =
7816 DAG.getNode(ISD::BITCAST, DL, RegVT, OpInfo.CallOperand);
7817 OpInfo.ConstraintVT = RegVT;
7818 // If the operand is an FP value and we want it in integer registers,
7819 // use the corresponding integer type. This turns an f64 value into
7820 // i64, which can be passed with two i32 values on a 32-bit machine.
7821 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
7822 MVT VT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits());
7823 if (OpInfo.Type == InlineAsm::isInput)
7824 OpInfo.CallOperand =
7825 DAG.getNode(ISD::BITCAST, DL, VT, OpInfo.CallOperand);
7826 OpInfo.ConstraintVT = VT;
7827 }
7828 }
7829 }
7830
7831 // No need to allocate a matching input constraint since the constraint it's
7832 // matching to has already been allocated.
7833 if (OpInfo.isMatchingInputConstraint())
7834 return;
7835
7836 EVT ValueVT = OpInfo.ConstraintVT;
7837 if (OpInfo.ConstraintVT == MVT::Other)
7838 ValueVT = RegVT;
7839
7840 // Initialize NumRegs.
7841 unsigned NumRegs = 1;
7842 if (OpInfo.ConstraintVT != MVT::Other)
7843 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
7844
7845 // If this is a constraint for a specific physical register, like {r17},
7846 // assign it now.
7847
7848 // If this associated to a specific register, initialize iterator to correct
7849 // place. If virtual, make sure we have enough registers
7850
7851 // Initialize iterator if necessary
7852 TargetRegisterClass::iterator I = RC->begin();
7853 MachineRegisterInfo &RegInfo = MF.getRegInfo();
7854
7855 // Do not check for single registers.
7856 if (AssignedReg) {
7857 for (; *I != AssignedReg; ++I)
7858 assert(I != RC->end() && "AssignedReg should be member of RC")((I != RC->end() && "AssignedReg should be member of RC"
) ? static_cast<void> (0) : __assert_fail ("I != RC->end() && \"AssignedReg should be member of RC\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7858, __PRETTY_FUNCTION__))
;
7859 }
7860
7861 for (; NumRegs; --NumRegs, ++I) {
7862 assert(I != RC->end() && "Ran out of registers to allocate!")((I != RC->end() && "Ran out of registers to allocate!"
) ? static_cast<void> (0) : __assert_fail ("I != RC->end() && \"Ran out of registers to allocate!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7862, __PRETTY_FUNCTION__))
;
7863 auto R = (AssignedReg) ? *I : RegInfo.createVirtualRegister(RC);
7864 Regs.push_back(R);
7865 }
7866
7867 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
7868}
7869
7870static unsigned
7871findMatchingInlineAsmOperand(unsigned OperandNo,
7872 const std::vector<SDValue> &AsmNodeOperands) {
7873 // Scan until we find the definition we already emitted of this operand.
7874 unsigned CurOp = InlineAsm::Op_FirstOperand;
7875 for (; OperandNo; --OperandNo) {
7876 // Advance to the next operand.
7877 unsigned OpFlag =
7878 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
7879 assert((InlineAsm::isRegDefKind(OpFlag) ||(((InlineAsm::isRegDefKind(OpFlag) || InlineAsm::isRegDefEarlyClobberKind
(OpFlag) || InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?"
) ? static_cast<void> (0) : __assert_fail ("(InlineAsm::isRegDefKind(OpFlag) || InlineAsm::isRegDefEarlyClobberKind(OpFlag) || InlineAsm::isMemKind(OpFlag)) && \"Skipped past definitions?\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7882, __PRETTY_FUNCTION__))
7880 InlineAsm::isRegDefEarlyClobberKind(OpFlag) ||(((InlineAsm::isRegDefKind(OpFlag) || InlineAsm::isRegDefEarlyClobberKind
(OpFlag) || InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?"
) ? static_cast<void> (0) : __assert_fail ("(InlineAsm::isRegDefKind(OpFlag) || InlineAsm::isRegDefEarlyClobberKind(OpFlag) || InlineAsm::isMemKind(OpFlag)) && \"Skipped past definitions?\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7882, __PRETTY_FUNCTION__))
7881 InlineAsm::isMemKind(OpFlag)) &&(((InlineAsm::isRegDefKind(OpFlag) || InlineAsm::isRegDefEarlyClobberKind
(OpFlag) || InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?"
) ? static_cast<void> (0) : __assert_fail ("(InlineAsm::isRegDefKind(OpFlag) || InlineAsm::isRegDefEarlyClobberKind(OpFlag) || InlineAsm::isMemKind(OpFlag)) && \"Skipped past definitions?\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7882, __PRETTY_FUNCTION__))
7882 "Skipped past definitions?")(((InlineAsm::isRegDefKind(OpFlag) || InlineAsm::isRegDefEarlyClobberKind
(OpFlag) || InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?"
) ? static_cast<void> (0) : __assert_fail ("(InlineAsm::isRegDefKind(OpFlag) || InlineAsm::isRegDefEarlyClobberKind(OpFlag) || InlineAsm::isMemKind(OpFlag)) && \"Skipped past definitions?\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7882, __PRETTY_FUNCTION__))
;
7883 CurOp += InlineAsm::getNumOperandRegisters(OpFlag) + 1;
7884 }
7885 return CurOp;
7886}
7887
7888namespace {
7889
7890class ExtraFlags {
7891 unsigned Flags = 0;
7892
7893public:
7894 explicit ExtraFlags(ImmutableCallSite CS) {
7895 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
7896 if (IA->hasSideEffects())
7897 Flags |= InlineAsm::Extra_HasSideEffects;
7898 if (IA->isAlignStack())
7899 Flags |= InlineAsm::Extra_IsAlignStack;
7900 if (CS.isConvergent())
7901 Flags |= InlineAsm::Extra_IsConvergent;
7902 Flags |= IA->getDialect() * InlineAsm::Extra_AsmDialect;
7903 }
7904
7905 void update(const TargetLowering::AsmOperandInfo &OpInfo) {
7906 // Ideally, we would only check against memory constraints. However, the
7907 // meaning of an Other constraint can be target-specific and we can't easily
7908 // reason about it. Therefore, be conservative and set MayLoad/MayStore
7909 // for Other constraints as well.
7910 if (OpInfo.ConstraintType == TargetLowering::C_Memory ||
7911 OpInfo.ConstraintType == TargetLowering::C_Other) {
7912 if (OpInfo.Type == InlineAsm::isInput)
7913 Flags |= InlineAsm::Extra_MayLoad;
7914 else if (OpInfo.Type == InlineAsm::isOutput)
7915 Flags |= InlineAsm::Extra_MayStore;
7916 else if (OpInfo.Type == InlineAsm::isClobber)
7917 Flags |= (InlineAsm::Extra_MayLoad | InlineAsm::Extra_MayStore);
7918 }
7919 }
7920
7921 unsigned get() const { return Flags; }
7922};
7923
7924} // end anonymous namespace
7925
7926/// visitInlineAsm - Handle a call to an InlineAsm object.
7927void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
7928 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
7929
7930 /// ConstraintOperands - Information about all of the constraints.
7931 SDISelAsmOperandInfoVector ConstraintOperands;
7932
7933 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7934 TargetLowering::AsmOperandInfoVector TargetConstraints = TLI.ParseConstraints(
7935 DAG.getDataLayout(), DAG.getSubtarget().getRegisterInfo(), CS);
7936
7937 // First Pass: Calculate HasSideEffects and ExtraFlags (AlignStack,
7938 // AsmDialect, MayLoad, MayStore).
7939 bool HasSideEffect = IA->hasSideEffects();
7940 ExtraFlags ExtraInfo(CS);
7941
7942 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
7943 unsigned ResNo = 0; // ResNo - The result number of the next output.
7944 for (auto &T : TargetConstraints) {
7945 ConstraintOperands.push_back(SDISelAsmOperandInfo(T));
7946 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
7947
7948 // Compute the value type for each operand.
7949 if (OpInfo.Type == InlineAsm::isInput ||
7950 (OpInfo.Type == InlineAsm::isOutput && OpInfo.isIndirect)) {
7951 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
7952
7953 // Process the call argument. BasicBlocks are labels, currently appearing
7954 // only in asm's.
7955 const Instruction *I = CS.getInstruction();
7956 if (isa<CallBrInst>(I) &&
7957 (ArgNo - 1) >= (cast<CallBrInst>(I)->getNumArgOperands() -
7958 cast<CallBrInst>(I)->getNumIndirectDests())) {
7959 const auto *BA = cast<BlockAddress>(OpInfo.CallOperandVal);
7960 EVT VT = TLI.getValueType(DAG.getDataLayout(), BA->getType(), true);
7961 OpInfo.CallOperand = DAG.getTargetBlockAddress(BA, VT);
7962 } else if (const auto *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
7963 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
7964 } else {
7965 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
7966 }
7967
7968 OpInfo.ConstraintVT =
7969 OpInfo
7970 .getCallOperandValEVT(*DAG.getContext(), TLI, DAG.getDataLayout())
7971 .getSimpleVT();
7972 } else if (OpInfo.Type == InlineAsm::isOutput && !OpInfo.isIndirect) {
7973 // The return value of the call is this value. As such, there is no
7974 // corresponding argument.
7975 assert(!CS.getType()->isVoidTy() && "Bad inline asm!")((!CS.getType()->isVoidTy() && "Bad inline asm!") ?
static_cast<void> (0) : __assert_fail ("!CS.getType()->isVoidTy() && \"Bad inline asm!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7975, __PRETTY_FUNCTION__))
;
7976 if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
7977 OpInfo.ConstraintVT = TLI.getSimpleValueType(
7978 DAG.getDataLayout(), STy->getElementType(ResNo));
7979 } else {
7980 assert(ResNo == 0 && "Asm only has one result!")((ResNo == 0 && "Asm only has one result!") ? static_cast
<void> (0) : __assert_fail ("ResNo == 0 && \"Asm only has one result!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 7980, __PRETTY_FUNCTION__))
;
7981 OpInfo.ConstraintVT =
7982 TLI.getSimpleValueType(DAG.getDataLayout(), CS.getType());
7983 }
7984 ++ResNo;
7985 } else {
7986 OpInfo.ConstraintVT = MVT::Other;
7987 }
7988
7989 if (!HasSideEffect)
7990 HasSideEffect = OpInfo.hasMemory(TLI);
7991
7992 // Determine if this InlineAsm MayLoad or MayStore based on the constraints.
7993 // FIXME: Could we compute this on OpInfo rather than T?
7994
7995 // Compute the constraint code and ConstraintType to use.
7996 TLI.ComputeConstraintToUse(T, SDValue());
7997
7998 ExtraInfo.update(T);
7999 }
8000
8001 // We won't need to flush pending loads if this asm doesn't touch
8002 // memory and is nonvolatile.
8003 SDValue Flag, Chain = (HasSideEffect) ? getRoot() : DAG.getRoot();
8004
8005 // Second pass over the constraints: compute which constraint option to use.
8006 for (SDISelAsmOperandInfo &OpInfo : ConstraintOperands) {
8007 // If this is an output operand with a matching input operand, look up the
8008 // matching input. If their types mismatch, e.g. one is an integer, the
8009 // other is floating point, or their sizes are different, flag it as an
8010 // error.
8011 if (OpInfo.hasMatchingInput()) {
8012 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
8013 patchMatchingInput(OpInfo, Input, DAG);
8014 }
8015
8016 // Compute the constraint code and ConstraintType to use.
8017 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
8018
8019 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
8020 OpInfo.Type == InlineAsm::isClobber)
8021 continue;
8022
8023 // If this is a memory input, and if the operand is not indirect, do what we
8024 // need to provide an address for the memory input.
8025 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
8026 !OpInfo.isIndirect) {
8027 assert((OpInfo.isMultipleAlternative ||(((OpInfo.isMultipleAlternative || (OpInfo.Type == InlineAsm::
isInput)) && "Can only indirectify direct input operands!"
) ? static_cast<void> (0) : __assert_fail ("(OpInfo.isMultipleAlternative || (OpInfo.Type == InlineAsm::isInput)) && \"Can only indirectify direct input operands!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 8029, __PRETTY_FUNCTION__))
8028 (OpInfo.Type == InlineAsm::isInput)) &&(((OpInfo.isMultipleAlternative || (OpInfo.Type == InlineAsm::
isInput)) && "Can only indirectify direct input operands!"
) ? static_cast<void> (0) : __assert_fail ("(OpInfo.isMultipleAlternative || (OpInfo.Type == InlineAsm::isInput)) && \"Can only indirectify direct input operands!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 8029, __PRETTY_FUNCTION__))
8029 "Can only indirectify direct input operands!")(((OpInfo.isMultipleAlternative || (OpInfo.Type == InlineAsm::
isInput)) && "Can only indirectify direct input operands!"
) ? static_cast<void> (0) : __assert_fail ("(OpInfo.isMultipleAlternative || (OpInfo.Type == InlineAsm::isInput)) && \"Can only indirectify direct input operands!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 8029, __PRETTY_FUNCTION__))
;
8030
8031 // Memory operands really want the address of the value.
8032 Chain = getAddressForMemoryInput(Chain, getCurSDLoc(), OpInfo, DAG);
8033
8034 // There is no longer a Value* corresponding to this operand.
8035 OpInfo.CallOperandVal = nullptr;
8036
8037 // It is now an indirect operand.
8038 OpInfo.isIndirect = true;
8039 }
8040
8041 }
8042
8043 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
8044 std::vector<SDValue> AsmNodeOperands;
8045 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
8046 AsmNodeOperands.push_back(DAG.getTargetExternalSymbol(
8047 IA->getAsmString().c_str(), TLI.getPointerTy(DAG.getDataLayout())));
8048
8049 // If we have a !srcloc metadata node associated with it, we want to attach
8050 // this to the ultimately generated inline asm machineinstr. To do this, we
8051 // pass in the third operand as this (potentially null) inline asm MDNode.
8052 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc");
8053 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc));
8054
8055 // Remember the HasSideEffect, AlignStack, AsmDialect, MayLoad and MayStore
8056 // bits as operand 3.
8057 AsmNodeOperands.push_back(DAG.getTargetConstant(
8058 ExtraInfo.get(), getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout())));
8059
8060 // Third pass: Loop over operands to prepare DAG-level operands.. As part of
8061 // this, assign virtual and physical registers for inputs and otput.
8062 for (SDISelAsmOperandInfo &OpInfo : ConstraintOperands) {
8063 // Assign Registers.
8064 SDISelAsmOperandInfo &RefOpInfo =
8065 OpInfo.isMatchingInputConstraint()
8066 ? ConstraintOperands[OpInfo.getMatchedOperand()]
8067 : OpInfo;
8068 GetRegistersForValue(DAG, getCurSDLoc(), OpInfo, RefOpInfo);
8069
8070 switch (OpInfo.Type) {
8071 case InlineAsm::isOutput:
8072 if (OpInfo.ConstraintType == TargetLowering::C_Memory ||
8073 (OpInfo.ConstraintType == TargetLowering::C_Other &&
8074 OpInfo.isIndirect)) {
8075 unsigned ConstraintID =
8076 TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
8077 assert(ConstraintID != InlineAsm::Constraint_Unknown &&((ConstraintID != InlineAsm::Constraint_Unknown && "Failed to convert memory constraint code to constraint id."
) ? static_cast<void> (0) : __assert_fail ("ConstraintID != InlineAsm::Constraint_Unknown && \"Failed to convert memory constraint code to constraint id.\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 8078, __PRETTY_FUNCTION__))
8078 "Failed to convert memory constraint code to constraint id.")((ConstraintID != InlineAsm::Constraint_Unknown && "Failed to convert memory constraint code to constraint id."
) ? static_cast<void> (0) : __assert_fail ("ConstraintID != InlineAsm::Constraint_Unknown && \"Failed to convert memory constraint code to constraint id.\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 8078, __PRETTY_FUNCTION__))
;
8079
8080 // Add information to the INLINEASM node to know about this output.
8081 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
8082 OpFlags = InlineAsm::getFlagWordForMem(OpFlags, ConstraintID);
8083 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags, getCurSDLoc(),
8084 MVT::i32));
8085 AsmNodeOperands.push_back(OpInfo.CallOperand);
8086 break;
8087 } else if ((OpInfo.ConstraintType == TargetLowering::C_Other &&
8088 !OpInfo.isIndirect) ||
8089 OpInfo.ConstraintType == TargetLowering::C_Register ||
8090 OpInfo.ConstraintType == TargetLowering::C_RegisterClass) {
8091 // Otherwise, this outputs to a register (directly for C_Register /
8092 // C_RegisterClass, and a target-defined fashion for C_Other). Find a
8093 // register that we can use.
8094 if (OpInfo.AssignedRegs.Regs.empty()) {
8095 emitInlineAsmError(
8096 CS, "couldn't allocate output register for constraint '" +
8097 Twine(OpInfo.ConstraintCode) + "'");
8098 return;
8099 }
8100
8101 // Add information to the INLINEASM node to know that this register is
8102 // set.
8103 OpInfo.AssignedRegs.AddInlineAsmOperands(
8104 OpInfo.isEarlyClobber ? InlineAsm::Kind_RegDefEarlyClobber
8105 : InlineAsm::Kind_RegDef,
8106 false, 0, getCurSDLoc(), DAG, AsmNodeOperands);
8107 }
8108 break;
8109
8110 case InlineAsm::isInput: {
8111 SDValue InOperandVal = OpInfo.CallOperand;
8112
8113 if (OpInfo.isMatchingInputConstraint()) {
8114 // If this is required to match an output register we have already set,
8115 // just use its register.
8116 auto CurOp = findMatchingInlineAsmOperand(OpInfo.getMatchedOperand(),
8117 AsmNodeOperands);
8118 unsigned OpFlag =
8119 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
8120 if (InlineAsm::isRegDefKind(OpFlag) ||
8121 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) {
8122 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
8123 if (OpInfo.isIndirect) {
8124 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c
8125 emitInlineAsmError(CS, "inline asm not supported yet:"
8126 " don't know how to handle tied "
8127 "indirect register inputs");
8128 return;
8129 }
8130
8131 MVT RegVT = AsmNodeOperands[CurOp+1].getSimpleValueType();
8132 SmallVector<unsigned, 4> Regs;
8133
8134 if (const TargetRegisterClass *RC = TLI.getRegClassFor(RegVT)) {
8135 unsigned NumRegs = InlineAsm::getNumOperandRegisters(OpFlag);
8136 MachineRegisterInfo &RegInfo =
8137 DAG.getMachineFunction().getRegInfo();
8138 for (unsigned i = 0; i != NumRegs; ++i)
8139 Regs.push_back(RegInfo.createVirtualRegister(RC));
8140 } else {
8141 emitInlineAsmError(CS, "inline asm error: This value type register "
8142 "class is not natively supported!");
8143 return;
8144 }
8145
8146 RegsForValue MatchedRegs(Regs, RegVT, InOperandVal.getValueType());
8147
8148 SDLoc dl = getCurSDLoc();
8149 // Use the produced MatchedRegs object to
8150 MatchedRegs.getCopyToRegs(InOperandVal, DAG, dl, Chain, &Flag,
8151 CS.getInstruction());
8152 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse,
8153 true, OpInfo.getMatchedOperand(), dl,
8154 DAG, AsmNodeOperands);
8155 break;
8156 }
8157
8158 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!")((InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!"
) ? static_cast<void> (0) : __assert_fail ("InlineAsm::isMemKind(OpFlag) && \"Unknown matching constraint!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 8158, __PRETTY_FUNCTION__))
;
8159 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 &&((InlineAsm::getNumOperandRegisters(OpFlag) == 1 && "Unexpected number of operands"
) ? static_cast<void> (0) : __assert_fail ("InlineAsm::getNumOperandRegisters(OpFlag) == 1 && \"Unexpected number of operands\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 8160, __PRETTY_FUNCTION__))
8160 "Unexpected number of operands")((InlineAsm::getNumOperandRegisters(OpFlag) == 1 && "Unexpected number of operands"
) ? static_cast<void> (0) : __assert_fail ("InlineAsm::getNumOperandRegisters(OpFlag) == 1 && \"Unexpected number of operands\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 8160, __PRETTY_FUNCTION__))
;
8161 // Add information to the INLINEASM node to know about this input.
8162 // See InlineAsm.h isUseOperandTiedToDef.
8163 OpFlag = InlineAsm::convertMemFlagWordToMatchingFlagWord(OpFlag);
8164 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag,
8165 OpInfo.getMatchedOperand());
8166 AsmNodeOperands.push_back(DAG.getTargetConstant(
8167 OpFlag, getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout())));
8168 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
8169 break;
8170 }
8171
8172 // Treat indirect 'X' constraint as memory.
8173 if (OpInfo.ConstraintType == TargetLowering::C_Other &&
8174 OpInfo.isIndirect)
8175 OpInfo.ConstraintType = TargetLowering::C_Memory;
8176
8177 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
8178 std::vector<SDValue> Ops;
8179 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode,
8180 Ops, DAG);
8181 if (Ops.empty()) {
8182 emitInlineAsmError(CS, "invalid operand for inline asm constraint '" +
8183 Twine(OpInfo.ConstraintCode) + "'");
8184 return;
8185 }
8186
8187 // Add information to the INLINEASM node to know about this input.
8188 unsigned ResOpType =
8189 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
8190 AsmNodeOperands.push_back(DAG.getTargetConstant(
8191 ResOpType, getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout())));
8192 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
8193 break;
8194 }
8195
8196 if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
8197 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!")((OpInfo.isIndirect && "Operand must be indirect to be a mem!"
) ? static_cast<void> (0) : __assert_fail ("OpInfo.isIndirect && \"Operand must be indirect to be a mem!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 8197, __PRETTY_FUNCTION__))
;
8198 assert(InOperandVal.getValueType() ==((InOperandVal.getValueType() == TLI.getPointerTy(DAG.getDataLayout
()) && "Memory operands expect pointer values") ? static_cast
<void> (0) : __assert_fail ("InOperandVal.getValueType() == TLI.getPointerTy(DAG.getDataLayout()) && \"Memory operands expect pointer values\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 8200, __PRETTY_FUNCTION__))
8199 TLI.getPointerTy(DAG.getDataLayout()) &&((InOperandVal.getValueType() == TLI.getPointerTy(DAG.getDataLayout
()) && "Memory operands expect pointer values") ? static_cast
<void> (0) : __assert_fail ("InOperandVal.getValueType() == TLI.getPointerTy(DAG.getDataLayout()) && \"Memory operands expect pointer values\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 8200, __PRETTY_FUNCTION__))
8200 "Memory operands expect pointer values")((InOperandVal.getValueType() == TLI.getPointerTy(DAG.getDataLayout
()) && "Memory operands expect pointer values") ? static_cast
<void> (0) : __assert_fail ("InOperandVal.getValueType() == TLI.getPointerTy(DAG.getDataLayout()) && \"Memory operands expect pointer values\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 8200, __PRETTY_FUNCTION__))
;
8201
8202 unsigned ConstraintID =
8203 TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
8204 assert(ConstraintID != InlineAsm::Constraint_Unknown &&((ConstraintID != InlineAsm::Constraint_Unknown && "Failed to convert memory constraint code to constraint id."
) ? static_cast<void> (0) : __assert_fail ("ConstraintID != InlineAsm::Constraint_Unknown && \"Failed to convert memory constraint code to constraint id.\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 8205, __PRETTY_FUNCTION__))
8205 "Failed to convert memory constraint code to constraint id.")((ConstraintID != InlineAsm::Constraint_Unknown && "Failed to convert memory constraint code to constraint id."
) ? static_cast<void> (0) : __assert_fail ("ConstraintID != InlineAsm::Constraint_Unknown && \"Failed to convert memory constraint code to constraint id.\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 8205, __PRETTY_FUNCTION__))
;
8206
8207 // Add information to the INLINEASM node to know about this input.
8208 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
8209 ResOpType = InlineAsm::getFlagWordForMem(ResOpType, ConstraintID);
8210 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
8211 getCurSDLoc(),
8212 MVT::i32));
8213 AsmNodeOperands.push_back(InOperandVal);
8214 break;
8215 }
8216
8217 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||(((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
OpInfo.ConstraintType == TargetLowering::C_Register) &&
"Unknown constraint type!") ? static_cast<void> (0) : __assert_fail
("(OpInfo.ConstraintType == TargetLowering::C_RegisterClass || OpInfo.ConstraintType == TargetLowering::C_Register) && \"Unknown constraint type!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 8219, __PRETTY_FUNCTION__))
8218 OpInfo.ConstraintType == TargetLowering::C_Register) &&(((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
OpInfo.ConstraintType == TargetLowering::C_Register) &&
"Unknown constraint type!") ? static_cast<void> (0) : __assert_fail
("(OpInfo.ConstraintType == TargetLowering::C_RegisterClass || OpInfo.ConstraintType == TargetLowering::C_Register) && \"Unknown constraint type!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 8219, __PRETTY_FUNCTION__))
8219 "Unknown constraint type!")(((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
OpInfo.ConstraintType == TargetLowering::C_Register) &&
"Unknown constraint type!") ? static_cast<void> (0) : __assert_fail
("(OpInfo.ConstraintType == TargetLowering::C_RegisterClass || OpInfo.ConstraintType == TargetLowering::C_Register) && \"Unknown constraint type!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 8219, __PRETTY_FUNCTION__))
;
8220
8221 // TODO: Support this.
8222 if (OpInfo.isIndirect) {
8223 emitInlineAsmError(
8224 CS, "Don't know how to handle indirect register inputs yet "
8225 "for constraint '" +
8226 Twine(OpInfo.ConstraintCode) + "'");
8227 return;
8228 }
8229
8230 // Copy the input into the appropriate registers.
8231 if (OpInfo.AssignedRegs.Regs.empty()) {
8232 emitInlineAsmError(CS, "couldn't allocate input reg for constraint '" +
8233 Twine(OpInfo.ConstraintCode) + "'");
8234 return;
8235 }
8236
8237 SDLoc dl = getCurSDLoc();
8238
8239 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, dl,
8240 Chain, &Flag, CS.getInstruction());
8241
8242 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0,
8243 dl, DAG, AsmNodeOperands);
8244 break;
8245 }
8246 case InlineAsm::isClobber:
8247 // Add the clobbered value to the operand list, so that the register
8248 // allocator is aware that the physreg got clobbered.
8249 if (!OpInfo.AssignedRegs.Regs.empty())
8250 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber,
8251 false, 0, getCurSDLoc(), DAG,
8252 AsmNodeOperands);
8253 break;
8254 }
8255 }
8256
8257 // Finish up input operands. Set the input chain and add the flag last.
8258 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
8259 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
8260
8261 unsigned ISDOpc = isa<CallBrInst>(CS.getInstruction()) ? ISD::INLINEASM_BR
8262 : ISD::INLINEASM;
8263 Chain = DAG.getNode(ISDOpc, getCurSDLoc(),
8264 DAG.getVTList(MVT::Other, MVT::Glue), AsmNodeOperands);
8265 Flag = Chain.getValue(1);
8266
8267 // Do additional work to generate outputs.
8268
8269 SmallVector<EVT, 1> ResultVTs;
8270 SmallVector<SDValue, 1> ResultValues;
8271 SmallVector<SDValue, 8> OutChains;
8272
8273 llvm::Type *CSResultType = CS.getType();
8274 ArrayRef<Type *> ResultTypes;
8275 if (StructType *StructResult = dyn_cast<StructType>(CSResultType))
8276 ResultTypes = StructResult->elements();
8277 else if (!CSResultType->isVoidTy())
8278 ResultTypes = makeArrayRef(CSResultType);
8279
8280 auto CurResultType = ResultTypes.begin();
8281 auto handleRegAssign = [&](SDValue V) {
8282 assert(CurResultType != ResultTypes.end() && "Unexpected value")((CurResultType != ResultTypes.end() && "Unexpected value"
) ? static_cast<void> (0) : __assert_fail ("CurResultType != ResultTypes.end() && \"Unexpected value\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 8282, __PRETTY_FUNCTION__))
;
8283 assert((*CurResultType)->isSized() && "Unexpected unsized type")(((*CurResultType)->isSized() && "Unexpected unsized type"
) ? static_cast<void> (0) : __assert_fail ("(*CurResultType)->isSized() && \"Unexpected unsized type\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 8283, __PRETTY_FUNCTION__))
;
8284 EVT ResultVT = TLI.getValueType(DAG.getDataLayout(), *CurResultType);
8285 ++CurResultType;
8286 // If the type of the inline asm call site return value is different but has
8287 // same size as the type of the asm output bitcast it. One example of this
8288 // is for vectors with different width / number of elements. This can
8289 // happen for register classes that can contain multiple different value
8290 // types. The preg or vreg allocated may not have the same VT as was
8291 // expected.
8292 //
8293 // This can also happen for a return value that disagrees with the register
8294 // class it is put in, eg. a double in a general-purpose register on a
8295 // 32-bit machine.
8296 if (ResultVT != V.getValueType() &&
8297 ResultVT.getSizeInBits() == V.getValueSizeInBits())
8298 V = DAG.getNode(ISD::BITCAST, getCurSDLoc(), ResultVT, V);
8299 else if (ResultVT != V.getValueType() && ResultVT.isInteger() &&
8300 V.getValueType().isInteger()) {
8301 // If a result value was tied to an input value, the computed result
8302 // may have a wider width than the expected result. Extract the
8303 // relevant portion.
8304 V = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), ResultVT, V);
8305 }
8306 assert(ResultVT == V.getValueType() && "Asm result value mismatch!")((ResultVT == V.getValueType() && "Asm result value mismatch!"
) ? static_cast<void> (0) : __assert_fail ("ResultVT == V.getValueType() && \"Asm result value mismatch!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 8306, __PRETTY_FUNCTION__))
;
8307 ResultVTs.push_back(ResultVT);
8308 ResultValues.push_back(V);
8309 };
8310
8311 // Deal with output operands.
8312 for (SDISelAsmOperandInfo &OpInfo : ConstraintOperands) {
8313 if (OpInfo.Type == InlineAsm::isOutput) {
8314 SDValue Val;
8315 // Skip trivial output operands.
8316 if (OpInfo.AssignedRegs.Regs.empty())
8317 continue;
8318
8319 switch (OpInfo.ConstraintType) {
8320 case TargetLowering::C_Register:
8321 case TargetLowering::C_RegisterClass:
8322 Val = OpInfo.AssignedRegs.getCopyFromRegs(
8323 DAG, FuncInfo, getCurSDLoc(), Chain, &Flag, CS.getInstruction());
8324 break;
8325 case TargetLowering::C_Other:
8326 Val = TLI.LowerAsmOutputForConstraint(Chain, Flag, getCurSDLoc(),
8327 OpInfo, DAG);
8328 break;
8329 case TargetLowering::C_Memory:
8330 break; // Already handled.
8331 case TargetLowering::C_Unknown:
8332 assert(false && "Unexpected unknown constraint")((false && "Unexpected unknown constraint") ? static_cast
<void> (0) : __assert_fail ("false && \"Unexpected unknown constraint\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 8332, __PRETTY_FUNCTION__))
;
8333 }
8334
8335 // Indirect output manifest as stores. Record output chains.
8336 if (OpInfo.isIndirect) {
8337 const Value *Ptr = OpInfo.CallOperandVal;
8338 assert(Ptr && "Expected value CallOperandVal for indirect asm operand")((Ptr && "Expected value CallOperandVal for indirect asm operand"
) ? static_cast<void> (0) : __assert_fail ("Ptr && \"Expected value CallOperandVal for indirect asm operand\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 8338, __PRETTY_FUNCTION__))
;
8339 SDValue Store = DAG.getStore(Chain, getCurSDLoc(), Val, getValue(Ptr),
8340 MachinePointerInfo(Ptr));
8341 OutChains.push_back(Store);
8342 } else {
8343 // generate CopyFromRegs to associated registers.
8344 assert(!CS.getType()->isVoidTy() && "Bad inline asm!")((!CS.getType()->isVoidTy() && "Bad inline asm!") ?
static_cast<void> (0) : __assert_fail ("!CS.getType()->isVoidTy() && \"Bad inline asm!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 8344, __PRETTY_FUNCTION__))
;
8345 if (Val.getOpcode() == ISD::MERGE_VALUES) {
8346 for (const SDValue &V : Val->op_values())
8347 handleRegAssign(V);
8348 } else
8349 handleRegAssign(Val);
8350 }
8351 }
8352 }
8353
8354 // Set results.
8355 if (!ResultValues.empty()) {
8356 assert(CurResultType == ResultTypes.end() &&((CurResultType == ResultTypes.end() && "Mismatch in number of ResultTypes"
) ? static_cast<void> (0) : __assert_fail ("CurResultType == ResultTypes.end() && \"Mismatch in number of ResultTypes\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 8357, __PRETTY_FUNCTION__))
8357 "Mismatch in number of ResultTypes")((CurResultType == ResultTypes.end() && "Mismatch in number of ResultTypes"
) ? static_cast<void> (0) : __assert_fail ("CurResultType == ResultTypes.end() && \"Mismatch in number of ResultTypes\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 8357, __PRETTY_FUNCTION__))
;
8358 assert(ResultValues.size() == ResultTypes.size() &&((ResultValues.size() == ResultTypes.size() && "Mismatch in number of output operands in asm result"
) ? static_cast<void> (0) : __assert_fail ("ResultValues.size() == ResultTypes.size() && \"Mismatch in number of output operands in asm result\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 8359, __PRETTY_FUNCTION__))
8359 "Mismatch in number of output operands in asm result")((ResultValues.size() == ResultTypes.size() && "Mismatch in number of output operands in asm result"
) ? static_cast<void> (0) : __assert_fail ("ResultValues.size() == ResultTypes.size() && \"Mismatch in number of output operands in asm result\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 8359, __PRETTY_FUNCTION__))
;
8360
8361 SDValue V = DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
8362 DAG.getVTList(ResultVTs), ResultValues);
8363 setValue(CS.getInstruction(), V);
8364 }
8365
8366 // Collect store chains.
8367 if (!OutChains.empty())
8368 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other, OutChains);
8369
8370 // Only Update Root if inline assembly has a memory effect.
8371 if (ResultValues.empty() || HasSideEffect || !OutChains.empty())
8372 DAG.setRoot(Chain);
8373}
8374
8375void SelectionDAGBuilder::emitInlineAsmError(ImmutableCallSite CS,
8376 const Twine &Message) {
8377 LLVMContext &Ctx = *DAG.getContext();
8378 Ctx.emitError(CS.getInstruction(), Message);
8379
8380 // Make sure we leave the DAG in a valid state
8381 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8382 SmallVector<EVT, 1> ValueVTs;
8383 ComputeValueVTs(TLI, DAG.getDataLayout(), CS->getType(), ValueVTs);
8384
8385 if (ValueVTs.empty())
8386 return;
8387
8388 SmallVector<SDValue, 1> Ops;
8389 for (unsigned i = 0, e = ValueVTs.size(); i != e; ++i)
8390 Ops.push_back(DAG.getUNDEF(ValueVTs[i]));
8391
8392 setValue(CS.getInstruction(), DAG.getMergeValues(Ops, getCurSDLoc()));
8393}
8394
8395void SelectionDAGBuilder::visitVAStart(const CallInst &I) {
8396 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurSDLoc(),
8397 MVT::Other, getRoot(),
8398 getValue(I.getArgOperand(0)),
8399 DAG.getSrcValue(I.getArgOperand(0))));
8400}
8401
8402void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) {
8403 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8404 const DataLayout &DL = DAG.getDataLayout();
8405 SDValue V = DAG.getVAArg(
8406 TLI.getMemValueType(DAG.getDataLayout(), I.getType()), getCurSDLoc(),
8407 getRoot(), getValue(I.getOperand(0)), DAG.getSrcValue(I.getOperand(0)),
8408 DL.getABITypeAlignment(I.getType()));
8409 DAG.setRoot(V.getValue(1));
8410
8411 if (I.getType()->isPointerTy())
8412 V = DAG.getPtrExtOrTrunc(
8413 V, getCurSDLoc(), TLI.getValueType(DAG.getDataLayout(), I.getType()));
8414 setValue(&I, V);
8415}
8416
8417void SelectionDAGBuilder::visitVAEnd(const CallInst &I) {
8418 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurSDLoc(),
8419 MVT::Other, getRoot(),
8420 getValue(I.getArgOperand(0)),
8421 DAG.getSrcValue(I.getArgOperand(0))));
8422}
8423
8424void SelectionDAGBuilder::visitVACopy(const CallInst &I) {
8425 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurSDLoc(),
8426 MVT::Other, getRoot(),
8427 getValue(I.getArgOperand(0)),
8428 getValue(I.getArgOperand(1)),
8429 DAG.getSrcValue(I.getArgOperand(0)),
8430 DAG.getSrcValue(I.getArgOperand(1))));
8431}
8432
8433SDValue SelectionDAGBuilder::lowerRangeToAssertZExt(SelectionDAG &DAG,
8434 const Instruction &I,
8435 SDValue Op) {
8436 const MDNode *Range = I.getMetadata(LLVMContext::MD_range);
8437 if (!Range)
8438 return Op;
8439
8440 ConstantRange CR = getConstantRangeFromMetadata(*Range);
8441 if (CR.isFullSet() || CR.isEmptySet() || CR.isUpperWrapped())
8442 return Op;
8443
8444 APInt Lo = CR.getUnsignedMin();
8445 if (!Lo.isMinValue())
8446 return Op;
8447
8448 APInt Hi = CR.getUnsignedMax();
8449 unsigned Bits = std::max(Hi.getActiveBits(),
8450 static_cast<unsigned>(IntegerType::MIN_INT_BITS));
8451
8452 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), Bits);
8453
8454 SDLoc SL = getCurSDLoc();
8455
8456 SDValue ZExt = DAG.getNode(ISD::AssertZext, SL, Op.getValueType(), Op,
8457 DAG.getValueType(SmallVT));
8458 unsigned NumVals = Op.getNode()->getNumValues();
8459 if (NumVals == 1)
8460 return ZExt;
8461
8462 SmallVector<SDValue, 4> Ops;
8463
8464 Ops.push_back(ZExt);
8465 for (unsigned I = 1; I != NumVals; ++I)
8466 Ops.push_back(Op.getValue(I));
8467
8468 return DAG.getMergeValues(Ops, SL);
8469}
8470
8471/// Populate a CallLowerinInfo (into \p CLI) based on the properties of
8472/// the call being lowered.
8473///
8474/// This is a helper for lowering intrinsics that follow a target calling
8475/// convention or require stack pointer adjustment. Only a subset of the
8476/// intrinsic's operands need to participate in the calling convention.
8477void SelectionDAGBuilder::populateCallLoweringInfo(
8478 TargetLowering::CallLoweringInfo &CLI, const CallBase *Call,
8479 unsigned ArgIdx, unsigned NumArgs, SDValue Callee, Type *ReturnTy,
8480 bool IsPatchPoint) {
8481 TargetLowering::ArgListTy Args;
8482 Args.reserve(NumArgs);
8483
8484 // Populate the argument list.
8485 // Attributes for args start at offset 1, after the return attribute.
8486 for (unsigned ArgI = ArgIdx, ArgE = ArgIdx + NumArgs;
8487 ArgI != ArgE; ++ArgI) {
8488 const Value *V = Call->getOperand(ArgI);
8489
8490 assert(!V->getType()->isEmptyTy() && "Empty type passed to intrinsic.")((!V->getType()->isEmptyTy() && "Empty type passed to intrinsic."
) ? static_cast<void> (0) : __assert_fail ("!V->getType()->isEmptyTy() && \"Empty type passed to intrinsic.\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 8490, __PRETTY_FUNCTION__))
;
8491
8492 TargetLowering::ArgListEntry Entry;
8493 Entry.Node = getValue(V);
8494 Entry.Ty = V->getType();
8495 Entry.setAttributes(Call, ArgI);
8496 Args.push_back(Entry);
8497 }
8498
8499 CLI.setDebugLoc(getCurSDLoc())
8500 .setChain(getRoot())
8501 .setCallee(Call->getCallingConv(), ReturnTy, Callee, std::move(Args))
8502 .setDiscardResult(Call->use_empty())
8503 .setIsPatchPoint(IsPatchPoint);
8504}
8505
8506/// Add a stack map intrinsic call's live variable operands to a stackmap
8507/// or patchpoint target node's operand list.
8508///
8509/// Constants are converted to TargetConstants purely as an optimization to
8510/// avoid constant materialization and register allocation.
8511///
8512/// FrameIndex operands are converted to TargetFrameIndex so that ISEL does not
8513/// generate addess computation nodes, and so ExpandISelPseudo can convert the
8514/// TargetFrameIndex into a DirectMemRefOp StackMap location. This avoids
8515/// address materialization and register allocation, but may also be required
8516/// for correctness. If a StackMap (or PatchPoint) intrinsic directly uses an
8517/// alloca in the entry block, then the runtime may assume that the alloca's
8518/// StackMap location can be read immediately after compilation and that the
8519/// location is valid at any point during execution (this is similar to the
8520/// assumption made by the llvm.gcroot intrinsic). If the alloca's location were
8521/// only available in a register, then the runtime would need to trap when
8522/// execution reaches the StackMap in order to read the alloca's location.
8523static void addStackMapLiveVars(ImmutableCallSite CS, unsigned StartIdx,
8524 const SDLoc &DL, SmallVectorImpl<SDValue> &Ops,
8525 SelectionDAGBuilder &Builder) {
8526 for (unsigned i = StartIdx, e = CS.arg_size(); i != e; ++i) {
8527 SDValue OpVal = Builder.getValue(CS.getArgument(i));
8528 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(OpVal)) {
8529 Ops.push_back(
8530 Builder.DAG.getTargetConstant(StackMaps::ConstantOp, DL, MVT::i64));
8531 Ops.push_back(
8532 Builder.DAG.getTargetConstant(C->getSExtValue(), DL, MVT::i64));
8533 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(OpVal)) {
8534 const TargetLowering &TLI = Builder.DAG.getTargetLoweringInfo();
8535 Ops.push_back(Builder.DAG.getTargetFrameIndex(
8536 FI->getIndex(), TLI.getFrameIndexTy(Builder.DAG.getDataLayout())));
8537 } else
8538 Ops.push_back(OpVal);
8539 }
8540}
8541
8542/// Lower llvm.experimental.stackmap directly to its target opcode.
8543void SelectionDAGBuilder::visitStackmap(const CallInst &CI) {
8544 // void @llvm.experimental.stackmap(i32 <id>, i32 <numShadowBytes>,
8545 // [live variables...])
8546
8547 assert(CI.getType()->isVoidTy() && "Stackmap cannot return a value.")((CI.getType()->isVoidTy() && "Stackmap cannot return a value."
) ? static_cast<void> (0) : __assert_fail ("CI.getType()->isVoidTy() && \"Stackmap cannot return a value.\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 8547, __PRETTY_FUNCTION__))
;
8548
8549 SDValue Chain, InFlag, Callee, NullPtr;
8550 SmallVector<SDValue, 32> Ops;
8551
8552 SDLoc DL = getCurSDLoc();
8553 Callee = getValue(CI.getCalledValue());
8554 NullPtr = DAG.getIntPtrConstant(0, DL, true);
8555
8556 // The stackmap intrinsic only records the live variables (the arguemnts
8557 // passed to it) and emits NOPS (if requested). Unlike the patchpoint
8558 // intrinsic, this won't be lowered to a function call. This means we don't
8559 // have to worry about calling conventions and target specific lowering code.
8560 // Instead we perform the call lowering right here.
8561 //
8562 // chain, flag = CALLSEQ_START(chain, 0, 0)
8563 // chain, flag = STACKMAP(id, nbytes, ..., chain, flag)
8564 // chain, flag = CALLSEQ_END(chain, 0, 0, flag)
8565 //
8566 Chain = DAG.getCALLSEQ_START(getRoot(), 0, 0, DL);
8567 InFlag = Chain.getValue(1);
8568
8569 // Add the <id> and <numBytes> constants.
8570 SDValue IDVal = getValue(CI.getOperand(PatchPointOpers::IDPos));
8571 Ops.push_back(DAG.getTargetConstant(
8572 cast<ConstantSDNode>(IDVal)->getZExtValue(), DL, MVT::i64));
8573 SDValue NBytesVal = getValue(CI.getOperand(PatchPointOpers::NBytesPos));
8574 Ops.push_back(DAG.getTargetConstant(
8575 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), DL,
8576 MVT::i32));
8577
8578 // Push live variables for the stack map.
8579 addStackMapLiveVars(&CI, 2, DL, Ops, *this);
8580
8581 // We are not pushing any register mask info here on the operands list,
8582 // because the stackmap doesn't clobber anything.
8583
8584 // Push the chain and the glue flag.
8585 Ops.push_back(Chain);
8586 Ops.push_back(InFlag);
8587
8588 // Create the STACKMAP node.
8589 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
8590 SDNode *SM = DAG.getMachineNode(TargetOpcode::STACKMAP, DL, NodeTys, Ops);
8591 Chain = SDValue(SM, 0);
8592 InFlag = Chain.getValue(1);
8593
8594 Chain = DAG.getCALLSEQ_END(Chain, NullPtr, NullPtr, InFlag, DL);
8595
8596 // Stackmaps don't generate values, so nothing goes into the NodeMap.
8597
8598 // Set the root to the target-lowered call chain.
8599 DAG.setRoot(Chain);
8600
8601 // Inform the Frame Information that we have a stackmap in this function.
8602 FuncInfo.MF->getFrameInfo().setHasStackMap();
8603}
8604
8605/// Lower llvm.experimental.patchpoint directly to its target opcode.
8606void SelectionDAGBuilder::visitPatchpoint(ImmutableCallSite CS,
8607 const BasicBlock *EHPadBB) {
8608 // void|i64 @llvm.experimental.patchpoint.void|i64(i64 <id>,
8609 // i32 <numBytes>,
8610 // i8* <target>,
8611 // i32 <numArgs>,
8612 // [Args...],
8613 // [live variables...])
8614
8615 CallingConv::ID CC = CS.getCallingConv();
8616 bool IsAnyRegCC = CC == CallingConv::AnyReg;
8617 bool HasDef = !CS->getType()->isVoidTy();
8618 SDLoc dl = getCurSDLoc();
8619 SDValue Callee = getValue(CS->getOperand(PatchPointOpers::TargetPos));
8620
8621 // Handle immediate and symbolic callees.
8622 if (auto* ConstCallee = dyn_cast<ConstantSDNode>(Callee))
8623 Callee = DAG.getIntPtrConstant(ConstCallee->getZExtValue(), dl,
8624 /*isTarget=*/true);
8625 else if (auto* SymbolicCallee = dyn_cast<GlobalAddressSDNode>(Callee))
8626 Callee = DAG.getTargetGlobalAddress(SymbolicCallee->getGlobal(),
8627 SDLoc(SymbolicCallee),
8628 SymbolicCallee->getValueType(0));
8629
8630 // Get the real number of arguments participating in the call <numArgs>
8631 SDValue NArgVal = getValue(CS.getArgument(PatchPointOpers::NArgPos));
8632 unsigned NumArgs = cast<ConstantSDNode>(NArgVal)->getZExtValue();
8633
8634 // Skip the four meta args: <id>, <numNopBytes>, <target>, <numArgs>
8635 // Intrinsics include all meta-operands up to but not including CC.
8636 unsigned NumMetaOpers = PatchPointOpers::CCPos;
8637 assert(CS.arg_size() >= NumMetaOpers + NumArgs &&((CS.arg_size() >= NumMetaOpers + NumArgs && "Not enough arguments provided to the patchpoint intrinsic"
) ? static_cast<void> (0) : __assert_fail ("CS.arg_size() >= NumMetaOpers + NumArgs && \"Not enough arguments provided to the patchpoint intrinsic\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 8638, __PRETTY_FUNCTION__))
8638 "Not enough arguments provided to the patchpoint intrinsic")((CS.arg_size() >= NumMetaOpers + NumArgs && "Not enough arguments provided to the patchpoint intrinsic"
) ? static_cast<void> (0) : __assert_fail ("CS.arg_size() >= NumMetaOpers + NumArgs && \"Not enough arguments provided to the patchpoint intrinsic\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 8638, __PRETTY_FUNCTION__))
;
8639
8640 // For AnyRegCC the arguments are lowered later on manually.
8641 unsigned NumCallArgs = IsAnyRegCC ? 0 : NumArgs;
8642 Type *ReturnTy =
8643 IsAnyRegCC ? Type::getVoidTy(*DAG.getContext()) : CS->getType();
8644
8645 TargetLowering::CallLoweringInfo CLI(DAG);
8646 populateCallLoweringInfo(CLI, cast<CallBase>(CS.getInstruction()),
8647 NumMetaOpers, NumCallArgs, Callee, ReturnTy, true);
8648 std::pair<SDValue, SDValue> Result = lowerInvokable(CLI, EHPadBB);
8649
8650 SDNode *CallEnd = Result.second.getNode();
8651 if (HasDef && (CallEnd->getOpcode() == ISD::CopyFromReg))
8652 CallEnd = CallEnd->getOperand(0).getNode();
8653
8654 /// Get a call instruction from the call sequence chain.
8655 /// Tail calls are not allowed.
8656 assert(CallEnd->getOpcode() == ISD::CALLSEQ_END &&((CallEnd->getOpcode() == ISD::CALLSEQ_END && "Expected a callseq node."
) ? static_cast<void> (0) : __assert_fail ("CallEnd->getOpcode() == ISD::CALLSEQ_END && \"Expected a callseq node.\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 8657, __PRETTY_FUNCTION__))
8657 "Expected a callseq node.")((CallEnd->getOpcode() == ISD::CALLSEQ_END && "Expected a callseq node."
) ? static_cast<void> (0) : __assert_fail ("CallEnd->getOpcode() == ISD::CALLSEQ_END && \"Expected a callseq node.\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 8657, __PRETTY_FUNCTION__))
;
8658 SDNode *Call = CallEnd->getOperand(0).getNode();
8659 bool HasGlue = Call->getGluedNode();
8660
8661 // Replace the target specific call node with the patchable intrinsic.
8662 SmallVector<SDValue, 8> Ops;
8663
8664 // Add the <id> and <numBytes> constants.
8665 SDValue IDVal = getValue(CS->getOperand(PatchPointOpers::IDPos));
8666 Ops.push_back(DAG.getTargetConstant(
8667 cast<ConstantSDNode>(IDVal)->getZExtValue(), dl, MVT::i64));
8668 SDValue NBytesVal = getValue(CS->getOperand(PatchPointOpers::NBytesPos));
8669 Ops.push_back(DAG.getTargetConstant(
8670 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), dl,
8671 MVT::i32));
8672
8673 // Add the callee.
8674 Ops.push_back(Callee);
8675
8676 // Adjust <numArgs> to account for any arguments that have been passed on the
8677 // stack instead.
8678 // Call Node: Chain, Target, {Args}, RegMask, [Glue]
8679 unsigned NumCallRegArgs = Call->getNumOperands() - (HasGlue ? 4 : 3);
8680 NumCallRegArgs = IsAnyRegCC ? NumArgs : NumCallRegArgs;
8681 Ops.push_back(DAG.getTargetConstant(NumCallRegArgs, dl, MVT::i32));
8682
8683 // Add the calling convention
8684 Ops.push_back(DAG.getTargetConstant((unsigned)CC, dl, MVT::i32));
8685
8686 // Add the arguments we omitted previously. The register allocator should
8687 // place these in any free register.
8688 if (IsAnyRegCC)
8689 for (unsigned i = NumMetaOpers, e = NumMetaOpers + NumArgs; i != e; ++i)
8690 Ops.push_back(getValue(CS.getArgument(i)));
8691
8692 // Push the arguments from the call instruction up to the register mask.
8693 SDNode::op_iterator e = HasGlue ? Call->op_end()-2 : Call->op_end()-1;
8694 Ops.append(Call->op_begin() + 2, e);
8695
8696 // Push live variables for the stack map.
8697 addStackMapLiveVars(CS, NumMetaOpers + NumArgs, dl, Ops, *this);
8698
8699 // Push the register mask info.
8700 if (HasGlue)
8701 Ops.push_back(*(Call->op_end()-2));
8702 else
8703 Ops.push_back(*(Call->op_end()-1));
8704
8705 // Push the chain (this is originally the first operand of the call, but
8706 // becomes now the last or second to last operand).
8707 Ops.push_back(*(Call->op_begin()));
8708
8709 // Push the glue flag (last operand).
8710 if (HasGlue)
8711 Ops.push_back(*(Call->op_end()-1));
8712
8713 SDVTList NodeTys;
8714 if (IsAnyRegCC && HasDef) {
8715 // Create the return types based on the intrinsic definition
8716 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8717 SmallVector<EVT, 3> ValueVTs;
8718 ComputeValueVTs(TLI, DAG.getDataLayout(), CS->getType(), ValueVTs);
8719 assert(ValueVTs.size() == 1 && "Expected only one return value type.")((ValueVTs.size() == 1 && "Expected only one return value type."
) ? static_cast<void> (0) : __assert_fail ("ValueVTs.size() == 1 && \"Expected only one return value type.\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 8719, __PRETTY_FUNCTION__))
;
8720
8721 // There is always a chain and a glue type at the end
8722 ValueVTs.push_back(MVT::Other);
8723 ValueVTs.push_back(MVT::Glue);
8724 NodeTys = DAG.getVTList(ValueVTs);
8725 } else
8726 NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
8727
8728 // Replace the target specific call node with a PATCHPOINT node.
8729 MachineSDNode *MN = DAG.getMachineNode(TargetOpcode::PATCHPOINT,
8730 dl, NodeTys, Ops);
8731
8732 // Update the NodeMap.
8733 if (HasDef) {
8734 if (IsAnyRegCC)
8735 setValue(CS.getInstruction(), SDValue(MN, 0));
8736 else
8737 setValue(CS.getInstruction(), Result.first);
8738 }
8739
8740 // Fixup the consumers of the intrinsic. The chain and glue may be used in the
8741 // call sequence. Furthermore the location of the chain and glue can change
8742 // when the AnyReg calling convention is used and the intrinsic returns a
8743 // value.
8744 if (IsAnyRegCC && HasDef) {
8745 SDValue From[] = {SDValue(Call, 0), SDValue(Call, 1)};
8746 SDValue To[] = {SDValue(MN, 1), SDValue(MN, 2)};
8747 DAG.ReplaceAllUsesOfValuesWith(From, To, 2);
8748 } else
8749 DAG.ReplaceAllUsesWith(Call, MN);
8750 DAG.DeleteNode(Call);
8751
8752 // Inform the Frame Information that we have a patchpoint in this function.
8753 FuncInfo.MF->getFrameInfo().setHasPatchPoint();
8754}
8755
8756void SelectionDAGBuilder::visitVectorReduce(const CallInst &I,
8757 unsigned Intrinsic) {
8758 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8759 SDValue Op1 = getValue(I.getArgOperand(0));
8760 SDValue Op2;
8761 if (I.getNumArgOperands() > 1)
8762 Op2 = getValue(I.getArgOperand(1));
8763 SDLoc dl = getCurSDLoc();
8764 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
8765 SDValue Res;
8766 FastMathFlags FMF;
8767 if (isa<FPMathOperator>(I))
8768 FMF = I.getFastMathFlags();
8769
8770 switch (Intrinsic) {
8771 case Intrinsic::experimental_vector_reduce_fadd:
8772 if (FMF.isFast())
8773 Res = DAG.getNode(ISD::VECREDUCE_FADD, dl, VT, Op2);
8774 else
8775 Res = DAG.getNode(ISD::VECREDUCE_STRICT_FADD, dl, VT, Op1, Op2);
8776 break;
8777 case Intrinsic::experimental_vector_reduce_fmul:
8778 if (FMF.isFast())
8779 Res = DAG.getNode(ISD::VECREDUCE_FMUL, dl, VT, Op2);
8780 else
8781 Res = DAG.getNode(ISD::VECREDUCE_STRICT_FMUL, dl, VT, Op1, Op2);
8782 break;
8783 case Intrinsic::experimental_vector_reduce_add:
8784 Res = DAG.getNode(ISD::VECREDUCE_ADD, dl, VT, Op1);
8785 break;
8786 case Intrinsic::experimental_vector_reduce_mul:
8787 Res = DAG.getNode(ISD::VECREDUCE_MUL, dl, VT, Op1);
8788 break;
8789 case Intrinsic::experimental_vector_reduce_and:
8790 Res = DAG.getNode(ISD::VECREDUCE_AND, dl, VT, Op1);
8791 break;
8792 case Intrinsic::experimental_vector_reduce_or:
8793 Res = DAG.getNode(ISD::VECREDUCE_OR, dl, VT, Op1);
8794 break;
8795 case Intrinsic::experimental_vector_reduce_xor:
8796 Res = DAG.getNode(ISD::VECREDUCE_XOR, dl, VT, Op1);
8797 break;
8798 case Intrinsic::experimental_vector_reduce_smax:
8799 Res = DAG.getNode(ISD::VECREDUCE_SMAX, dl, VT, Op1);
8800 break;
8801 case Intrinsic::experimental_vector_reduce_smin:
8802 Res = DAG.getNode(ISD::VECREDUCE_SMIN, dl, VT, Op1);
8803 break;
8804 case Intrinsic::experimental_vector_reduce_umax:
8805 Res = DAG.getNode(ISD::VECREDUCE_UMAX, dl, VT, Op1);
8806 break;
8807 case Intrinsic::experimental_vector_reduce_umin:
8808 Res = DAG.getNode(ISD::VECREDUCE_UMIN, dl, VT, Op1);
8809 break;
8810 case Intrinsic::experimental_vector_reduce_fmax:
8811 Res = DAG.getNode(ISD::VECREDUCE_FMAX, dl, VT, Op1);
8812 break;
8813 case Intrinsic::experimental_vector_reduce_fmin:
8814 Res = DAG.getNode(ISD::VECREDUCE_FMIN, dl, VT, Op1);
8815 break;
8816 default:
8817 llvm_unreachable("Unhandled vector reduce intrinsic")::llvm::llvm_unreachable_internal("Unhandled vector reduce intrinsic"
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 8817)
;
8818 }
8819 setValue(&I, Res);
8820}
8821
8822/// Returns an AttributeList representing the attributes applied to the return
8823/// value of the given call.
8824static AttributeList getReturnAttrs(TargetLowering::CallLoweringInfo &CLI) {
8825 SmallVector<Attribute::AttrKind, 2> Attrs;
8826 if (CLI.RetSExt)
8827 Attrs.push_back(Attribute::SExt);
8828 if (CLI.RetZExt)
8829 Attrs.push_back(Attribute::ZExt);
8830 if (CLI.IsInReg)
8831 Attrs.push_back(Attribute::InReg);
8832
8833 return AttributeList::get(CLI.RetTy->getContext(), AttributeList::ReturnIndex,
8834 Attrs);
8835}
8836
8837/// TargetLowering::LowerCallTo - This is the default LowerCallTo
8838/// implementation, which just calls LowerCall.
8839/// FIXME: When all targets are
8840/// migrated to using LowerCall, this hook should be integrated into SDISel.
8841std::pair<SDValue, SDValue>
8842TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const {
8843 // Handle the incoming return values from the call.
8844 CLI.Ins.clear();
8845 Type *OrigRetTy = CLI.RetTy;
8846 SmallVector<EVT, 4> RetTys;
8847 SmallVector<uint64_t, 4> Offsets;
8848 auto &DL = CLI.DAG.getDataLayout();
8849 ComputeValueVTs(*this, DL, CLI.RetTy, RetTys, &Offsets);
8850
8851 if (CLI.IsPostTypeLegalization) {
1
Assuming the condition is true
2
Taking true branch
8852 // If we are lowering a libcall after legalization, split the return type.
8853 SmallVector<EVT, 4> OldRetTys = std::move(RetTys);
8854 SmallVector<uint64_t, 4> OldOffsets = std::move(Offsets);
3
Object 'Offsets' is moved
8855 for (size_t i = 0, e = OldRetTys.size(); i != e; ++i) {
4
Assuming 'i' is not equal to 'e'
5
Loop condition is true. Entering loop body
8856 EVT RetVT = OldRetTys[i];
8857 uint64_t Offset = OldOffsets[i];
8858 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), RetVT);
8859 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), RetVT);
8860 unsigned RegisterVTByteSZ = RegisterVT.getSizeInBits() / 8;
8861 RetTys.append(NumRegs, RegisterVT);
8862 for (unsigned j = 0; j != NumRegs; ++j)
6
Assuming 'j' is not equal to 'NumRegs'
7
Loop condition is true. Entering loop body
8863 Offsets.push_back(Offset + j * RegisterVTByteSZ);
8
Method called on moved-from object 'Offsets'
8864 }
8865 }
8866
8867 SmallVector<ISD::OutputArg, 4> Outs;
8868 GetReturnInfo(CLI.CallConv, CLI.RetTy, getReturnAttrs(CLI), Outs, *this, DL);
8869
8870 bool CanLowerReturn =
8871 this->CanLowerReturn(CLI.CallConv, CLI.DAG.getMachineFunction(),
8872 CLI.IsVarArg, Outs, CLI.RetTy->getContext());
8873
8874 SDValue DemoteStackSlot;
8875 int DemoteStackIdx = -100;
8876 if (!CanLowerReturn) {
8877 // FIXME: equivalent assert?
8878 // assert(!CS.hasInAllocaArgument() &&
8879 // "sret demotion is incompatible with inalloca");
8880 uint64_t TySize = DL.getTypeAllocSize(CLI.RetTy);
8881 unsigned Align = DL.getPrefTypeAlignment(CLI.RetTy);
8882 MachineFunction &MF = CLI.DAG.getMachineFunction();
8883 DemoteStackIdx = MF.getFrameInfo().CreateStackObject(TySize, Align, false);
8884 Type *StackSlotPtrType = PointerType::get(CLI.RetTy,
8885 DL.getAllocaAddrSpace());
8886
8887 DemoteStackSlot = CLI.DAG.getFrameIndex(DemoteStackIdx, getFrameIndexTy(DL));
8888 ArgListEntry Entry;
8889 Entry.Node = DemoteStackSlot;
8890 Entry.Ty = StackSlotPtrType;
8891 Entry.IsSExt = false;
8892 Entry.IsZExt = false;
8893 Entry.IsInReg = false;
8894 Entry.IsSRet = true;
8895 Entry.IsNest = false;
8896 Entry.IsByVal = false;
8897 Entry.IsReturned = false;
8898 Entry.IsSwiftSelf = false;
8899 Entry.IsSwiftError = false;
8900 Entry.Alignment = Align;
8901 CLI.getArgs().insert(CLI.getArgs().begin(), Entry);
8902 CLI.NumFixedArgs += 1;
8903 CLI.RetTy = Type::getVoidTy(CLI.RetTy->getContext());
8904
8905 // sret demotion isn't compatible with tail-calls, since the sret argument
8906 // points into the callers stack frame.
8907 CLI.IsTailCall = false;
8908 } else {
8909 bool NeedsRegBlock = functionArgumentNeedsConsecutiveRegisters(
8910 CLI.RetTy, CLI.CallConv, CLI.IsVarArg);
8911 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
8912 ISD::ArgFlagsTy Flags;
8913 if (NeedsRegBlock) {
8914 Flags.setInConsecutiveRegs();
8915 if (I == RetTys.size() - 1)
8916 Flags.setInConsecutiveRegsLast();
8917 }
8918 EVT VT = RetTys[I];
8919 MVT RegisterVT = getRegisterTypeForCallingConv(CLI.RetTy->getContext(),
8920 CLI.CallConv, VT);
8921 unsigned NumRegs = getNumRegistersForCallingConv(CLI.RetTy->getContext(),
8922 CLI.CallConv, VT);
8923 for (unsigned i = 0; i != NumRegs; ++i) {
8924 ISD::InputArg MyFlags;
8925 MyFlags.Flags = Flags;
8926 MyFlags.VT = RegisterVT;
8927 MyFlags.ArgVT = VT;
8928 MyFlags.Used = CLI.IsReturnValueUsed;
8929 if (CLI.RetTy->isPointerTy()) {
8930 MyFlags.Flags.setPointer();
8931 MyFlags.Flags.setPointerAddrSpace(
8932 cast<PointerType>(CLI.RetTy)->getAddressSpace());
8933 }
8934 if (CLI.RetSExt)
8935 MyFlags.Flags.setSExt();
8936 if (CLI.RetZExt)
8937 MyFlags.Flags.setZExt();
8938 if (CLI.IsInReg)
8939 MyFlags.Flags.setInReg();
8940 CLI.Ins.push_back(MyFlags);
8941 }
8942 }
8943 }
8944
8945 // We push in swifterror return as the last element of CLI.Ins.
8946 ArgListTy &Args = CLI.getArgs();
8947 if (supportSwiftError()) {
8948 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
8949 if (Args[i].IsSwiftError) {
8950 ISD::InputArg MyFlags;
8951 MyFlags.VT = getPointerTy(DL);
8952 MyFlags.ArgVT = EVT(getPointerTy(DL));
8953 MyFlags.Flags.setSwiftError();
8954 CLI.Ins.push_back(MyFlags);
8955 }
8956 }
8957 }
8958
8959 // Handle all of the outgoing arguments.
8960 CLI.Outs.clear();
8961 CLI.OutVals.clear();
8962 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
8963 SmallVector<EVT, 4> ValueVTs;
8964 ComputeValueVTs(*this, DL, Args[i].Ty, ValueVTs);
8965 // FIXME: Split arguments if CLI.IsPostTypeLegalization
8966 Type *FinalType = Args[i].Ty;
8967 if (Args[i].IsByVal)
8968 FinalType = cast<PointerType>(Args[i].Ty)->getElementType();
8969 bool NeedsRegBlock = functionArgumentNeedsConsecutiveRegisters(
8970 FinalType, CLI.CallConv, CLI.IsVarArg);
8971 for (unsigned Value = 0, NumValues = ValueVTs.size(); Value != NumValues;
8972 ++Value) {
8973 EVT VT = ValueVTs[Value];
8974 Type *ArgTy = VT.getTypeForEVT(CLI.RetTy->getContext());
8975 SDValue Op = SDValue(Args[i].Node.getNode(),
8976 Args[i].Node.getResNo() + Value);
8977 ISD::ArgFlagsTy Flags;
8978
8979 // Certain targets (such as MIPS), may have a different ABI alignment
8980 // for a type depending on the context. Give the target a chance to
8981 // specify the alignment it wants.
8982 unsigned OriginalAlignment = getABIAlignmentForCallingConv(ArgTy, DL);
8983
8984 if (Args[i].Ty->isPointerTy()) {
8985 Flags.setPointer();
8986 Flags.setPointerAddrSpace(
8987 cast<PointerType>(Args[i].Ty)->getAddressSpace());
8988 }
8989 if (Args[i].IsZExt)
8990 Flags.setZExt();
8991 if (Args[i].IsSExt)
8992 Flags.setSExt();
8993 if (Args[i].IsInReg) {
8994 // If we are using vectorcall calling convention, a structure that is
8995 // passed InReg - is surely an HVA
8996 if (CLI.CallConv == CallingConv::X86_VectorCall &&
8997 isa<StructType>(FinalType)) {
8998 // The first value of a structure is marked
8999 if (0 == Value)
9000 Flags.setHvaStart();
9001 Flags.setHva();
9002 }
9003 // Set InReg Flag
9004 Flags.setInReg();
9005 }
9006 if (Args[i].IsSRet)
9007 Flags.setSRet();
9008 if (Args[i].IsSwiftSelf)
9009 Flags.setSwiftSelf();
9010 if (Args[i].IsSwiftError)
9011 Flags.setSwiftError();
9012 if (Args[i].IsByVal)
9013 Flags.setByVal();
9014 if (Args[i].IsInAlloca) {
9015 Flags.setInAlloca();
9016 // Set the byval flag for CCAssignFn callbacks that don't know about
9017 // inalloca. This way we can know how many bytes we should've allocated
9018 // and how many bytes a callee cleanup function will pop. If we port
9019 // inalloca to more targets, we'll have to add custom inalloca handling
9020 // in the various CC lowering callbacks.
9021 Flags.setByVal();
9022 }
9023 if (Args[i].IsByVal || Args[i].IsInAlloca) {
9024 PointerType *Ty = cast<PointerType>(Args[i].Ty);
9025 Type *ElementTy = Ty->getElementType();
9026 Flags.setByValSize(DL.getTypeAllocSize(ElementTy));
9027 // For ByVal, alignment should come from FE. BE will guess if this
9028 // info is not there but there are cases it cannot get right.
9029 unsigned FrameAlign;
9030 if (Args[i].Alignment)
9031 FrameAlign = Args[i].Alignment;
9032 else
9033 FrameAlign = getByValTypeAlignment(ElementTy, DL);
9034 Flags.setByValAlign(FrameAlign);
9035 }
9036 if (Args[i].IsNest)
9037 Flags.setNest();
9038 if (NeedsRegBlock)
9039 Flags.setInConsecutiveRegs();
9040 Flags.setOrigAlign(OriginalAlignment);
9041
9042 MVT PartVT = getRegisterTypeForCallingConv(CLI.RetTy->getContext(),
9043 CLI.CallConv, VT);
9044 unsigned NumParts = getNumRegistersForCallingConv(CLI.RetTy->getContext(),
9045 CLI.CallConv, VT);
9046 SmallVector<SDValue, 4> Parts(NumParts);
9047 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
9048
9049 if (Args[i].IsSExt)
9050 ExtendKind = ISD::SIGN_EXTEND;
9051 else if (Args[i].IsZExt)
9052 ExtendKind = ISD::ZERO_EXTEND;
9053
9054 // Conservatively only handle 'returned' on non-vectors that can be lowered,
9055 // for now.
9056 if (Args[i].IsReturned && !Op.getValueType().isVector() &&
9057 CanLowerReturn) {
9058 assert(CLI.RetTy == Args[i].Ty && RetTys.size() == NumValues &&((CLI.RetTy == Args[i].Ty && RetTys.size() == NumValues
&& "unexpected use of 'returned'") ? static_cast<
void> (0) : __assert_fail ("CLI.RetTy == Args[i].Ty && RetTys.size() == NumValues && \"unexpected use of 'returned'\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9059, __PRETTY_FUNCTION__))
9059 "unexpected use of 'returned'")((CLI.RetTy == Args[i].Ty && RetTys.size() == NumValues
&& "unexpected use of 'returned'") ? static_cast<
void> (0) : __assert_fail ("CLI.RetTy == Args[i].Ty && RetTys.size() == NumValues && \"unexpected use of 'returned'\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9059, __PRETTY_FUNCTION__))
;
9060 // Before passing 'returned' to the target lowering code, ensure that
9061 // either the register MVT and the actual EVT are the same size or that
9062 // the return value and argument are extended in the same way; in these
9063 // cases it's safe to pass the argument register value unchanged as the
9064 // return register value (although it's at the target's option whether
9065 // to do so)
9066 // TODO: allow code generation to take advantage of partially preserved
9067 // registers rather than clobbering the entire register when the
9068 // parameter extension method is not compatible with the return
9069 // extension method
9070 if ((NumParts * PartVT.getSizeInBits() == VT.getSizeInBits()) ||
9071 (ExtendKind != ISD::ANY_EXTEND && CLI.RetSExt == Args[i].IsSExt &&
9072 CLI.RetZExt == Args[i].IsZExt))
9073 Flags.setReturned();
9074 }
9075
9076 getCopyToParts(CLI.DAG, CLI.DL, Op, &Parts[0], NumParts, PartVT,
9077 CLI.CS.getInstruction(), CLI.CallConv, ExtendKind);
9078
9079 for (unsigned j = 0; j != NumParts; ++j) {
9080 // if it isn't first piece, alignment must be 1
9081 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(), VT,
9082 i < CLI.NumFixedArgs,
9083 i, j*Parts[j].getValueType().getStoreSize());
9084 if (NumParts > 1 && j == 0)
9085 MyFlags.Flags.setSplit();
9086 else if (j != 0) {
9087 MyFlags.Flags.setOrigAlign(1);
9088 if (j == NumParts - 1)
9089 MyFlags.Flags.setSplitEnd();
9090 }
9091
9092 CLI.Outs.push_back(MyFlags);
9093 CLI.OutVals.push_back(Parts[j]);
9094 }
9095
9096 if (NeedsRegBlock && Value == NumValues - 1)
9097 CLI.Outs[CLI.Outs.size() - 1].Flags.setInConsecutiveRegsLast();
9098 }
9099 }
9100
9101 SmallVector<SDValue, 4> InVals;
9102 CLI.Chain = LowerCall(CLI, InVals);
9103
9104 // Update CLI.InVals to use outside of this function.
9105 CLI.InVals = InVals;
9106
9107 // Verify that the target's LowerCall behaved as expected.
9108 assert(CLI.Chain.getNode() && CLI.Chain.getValueType() == MVT::Other &&((CLI.Chain.getNode() && CLI.Chain.getValueType() == MVT
::Other && "LowerCall didn't return a valid chain!") ?
static_cast<void> (0) : __assert_fail ("CLI.Chain.getNode() && CLI.Chain.getValueType() == MVT::Other && \"LowerCall didn't return a valid chain!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9109, __PRETTY_FUNCTION__))
9109 "LowerCall didn't return a valid chain!")((CLI.Chain.getNode() && CLI.Chain.getValueType() == MVT
::Other && "LowerCall didn't return a valid chain!") ?
static_cast<void> (0) : __assert_fail ("CLI.Chain.getNode() && CLI.Chain.getValueType() == MVT::Other && \"LowerCall didn't return a valid chain!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9109, __PRETTY_FUNCTION__))
;
9110 assert((!CLI.IsTailCall || InVals.empty()) &&(((!CLI.IsTailCall || InVals.empty()) && "LowerCall emitted a return value for a tail call!"
) ? static_cast<void> (0) : __assert_fail ("(!CLI.IsTailCall || InVals.empty()) && \"LowerCall emitted a return value for a tail call!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9111, __PRETTY_FUNCTION__))
9111 "LowerCall emitted a return value for a tail call!")(((!CLI.IsTailCall || InVals.empty()) && "LowerCall emitted a return value for a tail call!"
) ? static_cast<void> (0) : __assert_fail ("(!CLI.IsTailCall || InVals.empty()) && \"LowerCall emitted a return value for a tail call!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9111, __PRETTY_FUNCTION__))
;
9112 assert((CLI.IsTailCall || InVals.size() == CLI.Ins.size()) &&(((CLI.IsTailCall || InVals.size() == CLI.Ins.size()) &&
"LowerCall didn't emit the correct number of values!") ? static_cast
<void> (0) : __assert_fail ("(CLI.IsTailCall || InVals.size() == CLI.Ins.size()) && \"LowerCall didn't emit the correct number of values!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9113, __PRETTY_FUNCTION__))
9113 "LowerCall didn't emit the correct number of values!")(((CLI.IsTailCall || InVals.size() == CLI.Ins.size()) &&
"LowerCall didn't emit the correct number of values!") ? static_cast
<void> (0) : __assert_fail ("(CLI.IsTailCall || InVals.size() == CLI.Ins.size()) && \"LowerCall didn't emit the correct number of values!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9113, __PRETTY_FUNCTION__))
;
9114
9115 // For a tail call, the return value is merely live-out and there aren't
9116 // any nodes in the DAG representing it. Return a special value to
9117 // indicate that a tail call has been emitted and no more Instructions
9118 // should be processed in the current block.
9119 if (CLI.IsTailCall) {
9120 CLI.DAG.setRoot(CLI.Chain);
9121 return std::make_pair(SDValue(), SDValue());
9122 }
9123
9124#ifndef NDEBUG
9125 for (unsigned i = 0, e = CLI.Ins.size(); i != e; ++i) {
9126 assert(InVals[i].getNode() && "LowerCall emitted a null value!")((InVals[i].getNode() && "LowerCall emitted a null value!"
) ? static_cast<void> (0) : __assert_fail ("InVals[i].getNode() && \"LowerCall emitted a null value!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9126, __PRETTY_FUNCTION__))
;
9127 assert(EVT(CLI.Ins[i].VT) == InVals[i].getValueType() &&((EVT(CLI.Ins[i].VT) == InVals[i].getValueType() && "LowerCall emitted a value with the wrong type!"
) ? static_cast<void> (0) : __assert_fail ("EVT(CLI.Ins[i].VT) == InVals[i].getValueType() && \"LowerCall emitted a value with the wrong type!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9128, __PRETTY_FUNCTION__))
9128 "LowerCall emitted a value with the wrong type!")((EVT(CLI.Ins[i].VT) == InVals[i].getValueType() && "LowerCall emitted a value with the wrong type!"
) ? static_cast<void> (0) : __assert_fail ("EVT(CLI.Ins[i].VT) == InVals[i].getValueType() && \"LowerCall emitted a value with the wrong type!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9128, __PRETTY_FUNCTION__))
;
9129 }
9130#endif
9131
9132 SmallVector<SDValue, 4> ReturnValues;
9133 if (!CanLowerReturn) {
9134 // The instruction result is the result of loading from the
9135 // hidden sret parameter.
9136 SmallVector<EVT, 1> PVTs;
9137 Type *PtrRetTy = OrigRetTy->getPointerTo(DL.getAllocaAddrSpace());
9138
9139 ComputeValueVTs(*this, DL, PtrRetTy, PVTs);
9140 assert(PVTs.size() == 1 && "Pointers should fit in one register")((PVTs.size() == 1 && "Pointers should fit in one register"
) ? static_cast<void> (0) : __assert_fail ("PVTs.size() == 1 && \"Pointers should fit in one register\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9140, __PRETTY_FUNCTION__))
;
9141 EVT PtrVT = PVTs[0];
9142
9143 unsigned NumValues = RetTys.size();
9144 ReturnValues.resize(NumValues);
9145 SmallVector<SDValue, 4> Chains(NumValues);
9146
9147 // An aggregate return value cannot wrap around the address space, so
9148 // offsets to its parts don't wrap either.
9149 SDNodeFlags Flags;
9150 Flags.setNoUnsignedWrap(true);
9151
9152 for (unsigned i = 0; i < NumValues; ++i) {
9153 SDValue Add = CLI.DAG.getNode(ISD::ADD, CLI.DL, PtrVT, DemoteStackSlot,
9154 CLI.DAG.getConstant(Offsets[i], CLI.DL,
9155 PtrVT), Flags);
9156 SDValue L = CLI.DAG.getLoad(
9157 RetTys[i], CLI.DL, CLI.Chain, Add,
9158 MachinePointerInfo::getFixedStack(CLI.DAG.getMachineFunction(),
9159 DemoteStackIdx, Offsets[i]),
9160 /* Alignment = */ 1);
9161 ReturnValues[i] = L;
9162 Chains[i] = L.getValue(1);
9163 }
9164
9165 CLI.Chain = CLI.DAG.getNode(ISD::TokenFactor, CLI.DL, MVT::Other, Chains);
9166 } else {
9167 // Collect the legal value parts into potentially illegal values
9168 // that correspond to the original function's return values.
9169 Optional<ISD::NodeType> AssertOp;
9170 if (CLI.RetSExt)
9171 AssertOp = ISD::AssertSext;
9172 else if (CLI.RetZExt)
9173 AssertOp = ISD::AssertZext;
9174 unsigned CurReg = 0;
9175 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
9176 EVT VT = RetTys[I];
9177 MVT RegisterVT = getRegisterTypeForCallingConv(CLI.RetTy->getContext(),
9178 CLI.CallConv, VT);
9179 unsigned NumRegs = getNumRegistersForCallingConv(CLI.RetTy->getContext(),
9180 CLI.CallConv, VT);
9181
9182 ReturnValues.push_back(getCopyFromParts(CLI.DAG, CLI.DL, &InVals[CurReg],
9183 NumRegs, RegisterVT, VT, nullptr,
9184 CLI.CallConv, AssertOp));
9185 CurReg += NumRegs;
9186 }
9187
9188 // For a function returning void, there is no return value. We can't create
9189 // such a node, so we just return a null return value in that case. In
9190 // that case, nothing will actually look at the value.
9191 if (ReturnValues.empty())
9192 return std::make_pair(SDValue(), CLI.Chain);
9193 }
9194
9195 SDValue Res = CLI.DAG.getNode(ISD::MERGE_VALUES, CLI.DL,
9196 CLI.DAG.getVTList(RetTys), ReturnValues);
9197 return std::make_pair(Res, CLI.Chain);
9198}
9199
9200void TargetLowering::LowerOperationWrapper(SDNode *N,
9201 SmallVectorImpl<SDValue> &Results,
9202 SelectionDAG &DAG) const {
9203 if (SDValue Res = LowerOperation(SDValue(N, 0), DAG))
9204 Results.push_back(Res);
9205}
9206
9207SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
9208 llvm_unreachable("LowerOperation not implemented for this target!")::llvm::llvm_unreachable_internal("LowerOperation not implemented for this target!"
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9208)
;
9209}
9210
9211void
9212SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) {
9213 SDValue Op = getNonRegisterValue(V);
9214 assert((Op.getOpcode() != ISD::CopyFromReg ||(((Op.getOpcode() != ISD::CopyFromReg || cast<RegisterSDNode
>(Op.getOperand(1))->getReg() != Reg) && "Copy from a reg to the same reg!"
) ? static_cast<void> (0) : __assert_fail ("(Op.getOpcode() != ISD::CopyFromReg || cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) && \"Copy from a reg to the same reg!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9216, __PRETTY_FUNCTION__))
9215 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&(((Op.getOpcode() != ISD::CopyFromReg || cast<RegisterSDNode
>(Op.getOperand(1))->getReg() != Reg) && "Copy from a reg to the same reg!"
) ? static_cast<void> (0) : __assert_fail ("(Op.getOpcode() != ISD::CopyFromReg || cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) && \"Copy from a reg to the same reg!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9216, __PRETTY_FUNCTION__))
9216 "Copy from a reg to the same reg!")(((Op.getOpcode() != ISD::CopyFromReg || cast<RegisterSDNode
>(Op.getOperand(1))->getReg() != Reg) && "Copy from a reg to the same reg!"
) ? static_cast<void> (0) : __assert_fail ("(Op.getOpcode() != ISD::CopyFromReg || cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) && \"Copy from a reg to the same reg!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9216, __PRETTY_FUNCTION__))
;
9217 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg")((!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg"
) ? static_cast<void> (0) : __assert_fail ("!TargetRegisterInfo::isPhysicalRegister(Reg) && \"Is a physreg\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9217, __PRETTY_FUNCTION__))
;
9218
9219 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9220 // If this is an InlineAsm we have to match the registers required, not the
9221 // notional registers required by the type.
9222
9223 RegsForValue RFV(V->getContext(), TLI, DAG.getDataLayout(), Reg, V->getType(),
9224 None); // This is not an ABI copy.
9225 SDValue Chain = DAG.getEntryNode();
9226
9227 ISD::NodeType ExtendType = (FuncInfo.PreferredExtendType.find(V) ==
9228 FuncInfo.PreferredExtendType.end())
9229 ? ISD::ANY_EXTEND
9230 : FuncInfo.PreferredExtendType[V];
9231 RFV.getCopyToRegs(Op, DAG, getCurSDLoc(), Chain, nullptr, V, ExtendType);
9232 PendingExports.push_back(Chain);
9233}
9234
9235#include "llvm/CodeGen/SelectionDAGISel.h"
9236
9237/// isOnlyUsedInEntryBlock - If the specified argument is only used in the
9238/// entry block, return true. This includes arguments used by switches, since
9239/// the switch may expand into multiple basic blocks.
9240static bool isOnlyUsedInEntryBlock(const Argument *A, bool FastISel) {
9241 // With FastISel active, we may be splitting blocks, so force creation
9242 // of virtual registers for all non-dead arguments.
9243 if (FastISel)
9244 return A->use_empty();
9245
9246 const BasicBlock &Entry = A->getParent()->front();
9247 for (const User *U : A->users())
9248 if (cast<Instruction>(U)->getParent() != &Entry || isa<SwitchInst>(U))
9249 return false; // Use not in entry block.
9250
9251 return true;
9252}
9253
9254using ArgCopyElisionMapTy =
9255 DenseMap<const Argument *,
9256 std::pair<const AllocaInst *, const StoreInst *>>;
9257
9258/// Scan the entry block of the function in FuncInfo for arguments that look
9259/// like copies into a local alloca. Record any copied arguments in
9260/// ArgCopyElisionCandidates.
9261static void
9262findArgumentCopyElisionCandidates(const DataLayout &DL,
9263 FunctionLoweringInfo *FuncInfo,
9264 ArgCopyElisionMapTy &ArgCopyElisionCandidates) {
9265 // Record the state of every static alloca used in the entry block. Argument
9266 // allocas are all used in the entry block, so we need approximately as many
9267 // entries as we have arguments.
9268 enum StaticAllocaInfo { Unknown, Clobbered, Elidable };
9269 SmallDenseMap<const AllocaInst *, StaticAllocaInfo, 8> StaticAllocas;
9270 unsigned NumArgs = FuncInfo->Fn->arg_size();
9271 StaticAllocas.reserve(NumArgs * 2);
9272
9273 auto GetInfoIfStaticAlloca = [&](const Value *V) -> StaticAllocaInfo * {
9274 if (!V)
9275 return nullptr;
9276 V = V->stripPointerCasts();
9277 const auto *AI = dyn_cast<AllocaInst>(V);
9278 if (!AI || !AI->isStaticAlloca() || !FuncInfo->StaticAllocaMap.count(AI))
9279 return nullptr;
9280 auto Iter = StaticAllocas.insert({AI, Unknown});
9281 return &Iter.first->second;
9282 };
9283
9284 // Look for stores of arguments to static allocas. Look through bitcasts and
9285 // GEPs to handle type coercions, as long as the alloca is fully initialized
9286 // by the store. Any non-store use of an alloca escapes it and any subsequent
9287 // unanalyzed store might write it.
9288 // FIXME: Handle structs initialized with multiple stores.
9289 for (const Instruction &I : FuncInfo->Fn->getEntryBlock()) {
9290 // Look for stores, and handle non-store uses conservatively.
9291 const auto *SI = dyn_cast<StoreInst>(&I);
9292 if (!SI) {
9293 // We will look through cast uses, so ignore them completely.
9294 if (I.isCast())
9295 continue;
9296 // Ignore debug info intrinsics, they don't escape or store to allocas.
9297 if (isa<DbgInfoIntrinsic>(I))
9298 continue;
9299 // This is an unknown instruction. Assume it escapes or writes to all
9300 // static alloca operands.
9301 for (const Use &U : I.operands()) {
9302 if (StaticAllocaInfo *Info = GetInfoIfStaticAlloca(U))
9303 *Info = StaticAllocaInfo::Clobbered;
9304 }
9305 continue;
9306 }
9307
9308 // If the stored value is a static alloca, mark it as escaped.
9309 if (StaticAllocaInfo *Info = GetInfoIfStaticAlloca(SI->getValueOperand()))
9310 *Info = StaticAllocaInfo::Clobbered;
9311
9312 // Check if the destination is a static alloca.
9313 const Value *Dst = SI->getPointerOperand()->stripPointerCasts();
9314 StaticAllocaInfo *Info = GetInfoIfStaticAlloca(Dst);
9315 if (!Info)
9316 continue;
9317 const AllocaInst *AI = cast<AllocaInst>(Dst);
9318
9319 // Skip allocas that have been initialized or clobbered.
9320 if (*Info != StaticAllocaInfo::Unknown)
9321 continue;
9322
9323 // Check if the stored value is an argument, and that this store fully
9324 // initializes the alloca. Don't elide copies from the same argument twice.
9325 const Value *Val = SI->getValueOperand()->stripPointerCasts();
9326 const auto *Arg = dyn_cast<Argument>(Val);
9327 if (!Arg || Arg->hasInAllocaAttr() || Arg->hasByValAttr() ||
9328 Arg->getType()->isEmptyTy() ||
9329 DL.getTypeStoreSize(Arg->getType()) !=
9330 DL.getTypeAllocSize(AI->getAllocatedType()) ||
9331 ArgCopyElisionCandidates.count(Arg)) {
9332 *Info = StaticAllocaInfo::Clobbered;
9333 continue;
9334 }
9335
9336 LLVM_DEBUG(dbgs() << "Found argument copy elision candidate: " << *AIdo { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << "Found argument copy elision candidate: "
<< *AI << '\n'; } } while (false)
9337 << '\n')do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << "Found argument copy elision candidate: "
<< *AI << '\n'; } } while (false)
;
9338
9339 // Mark this alloca and store for argument copy elision.
9340 *Info = StaticAllocaInfo::Elidable;
9341 ArgCopyElisionCandidates.insert({Arg, {AI, SI}});
9342
9343 // Stop scanning if we've seen all arguments. This will happen early in -O0
9344 // builds, which is useful, because -O0 builds have large entry blocks and
9345 // many allocas.
9346 if (ArgCopyElisionCandidates.size() == NumArgs)
9347 break;
9348 }
9349}
9350
9351/// Try to elide argument copies from memory into a local alloca. Succeeds if
9352/// ArgVal is a load from a suitable fixed stack object.
9353static void tryToElideArgumentCopy(
9354 FunctionLoweringInfo *FuncInfo, SmallVectorImpl<SDValue> &Chains,
9355 DenseMap<int, int> &ArgCopyElisionFrameIndexMap,
9356 SmallPtrSetImpl<const Instruction *> &ElidedArgCopyInstrs,
9357 ArgCopyElisionMapTy &ArgCopyElisionCandidates, const Argument &Arg,
9358 SDValue ArgVal, bool &ArgHasUses) {
9359 // Check if this is a load from a fixed stack object.
9360 auto *LNode = dyn_cast<LoadSDNode>(ArgVal);
9361 if (!LNode)
9362 return;
9363 auto *FINode = dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode());
9364 if (!FINode)
9365 return;
9366
9367 // Check that the fixed stack object is the right size and alignment.
9368 // Look at the alignment that the user wrote on the alloca instead of looking
9369 // at the stack object.
9370 auto ArgCopyIter = ArgCopyElisionCandidates.find(&Arg);
9371 assert(ArgCopyIter != ArgCopyElisionCandidates.end())((ArgCopyIter != ArgCopyElisionCandidates.end()) ? static_cast
<void> (0) : __assert_fail ("ArgCopyIter != ArgCopyElisionCandidates.end()"
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9371, __PRETTY_FUNCTION__))
;
9372 const AllocaInst *AI = ArgCopyIter->second.first;
9373 int FixedIndex = FINode->getIndex();
9374 int &AllocaIndex = FuncInfo->StaticAllocaMap[AI];
9375 int OldIndex = AllocaIndex;
9376 MachineFrameInfo &MFI = FuncInfo->MF->getFrameInfo();
9377 if (MFI.getObjectSize(FixedIndex) != MFI.getObjectSize(OldIndex)) {
9378 LLVM_DEBUG(do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << " argument copy elision failed due to bad fixed stack "
"object size\n"; } } while (false)
9379 dbgs() << " argument copy elision failed due to bad fixed stack "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << " argument copy elision failed due to bad fixed stack "
"object size\n"; } } while (false)
9380 "object size\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << " argument copy elision failed due to bad fixed stack "
"object size\n"; } } while (false)
;
9381 return;
9382 }
9383 unsigned RequiredAlignment = AI->getAlignment();
9384 if (!RequiredAlignment) {
9385 RequiredAlignment = FuncInfo->MF->getDataLayout().getABITypeAlignment(
9386 AI->getAllocatedType());
9387 }
9388 if (MFI.getObjectAlignment(FixedIndex) < RequiredAlignment) {
9389 LLVM_DEBUG(dbgs() << " argument copy elision failed: alignment of alloca "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << " argument copy elision failed: alignment of alloca "
"greater than stack argument alignment (" << RequiredAlignment
<< " vs " << MFI.getObjectAlignment(FixedIndex) <<
")\n"; } } while (false)
9390 "greater than stack argument alignment ("do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << " argument copy elision failed: alignment of alloca "
"greater than stack argument alignment (" << RequiredAlignment
<< " vs " << MFI.getObjectAlignment(FixedIndex) <<
")\n"; } } while (false)
9391 << RequiredAlignment << " vs "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << " argument copy elision failed: alignment of alloca "
"greater than stack argument alignment (" << RequiredAlignment
<< " vs " << MFI.getObjectAlignment(FixedIndex) <<
")\n"; } } while (false)
9392 << MFI.getObjectAlignment(FixedIndex) << ")\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << " argument copy elision failed: alignment of alloca "
"greater than stack argument alignment (" << RequiredAlignment
<< " vs " << MFI.getObjectAlignment(FixedIndex) <<
")\n"; } } while (false)
;
9393 return;
9394 }
9395
9396 // Perform the elision. Delete the old stack object and replace its only use
9397 // in the variable info map. Mark the stack object as mutable.
9398 LLVM_DEBUG({do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { { dbgs() << "Eliding argument copy from " <<
Arg << " to " << *AI << '\n' << " Replacing frame index "
<< OldIndex << " with " << FixedIndex <<
'\n'; }; } } while (false)
9399 dbgs() << "Eliding argument copy from " << Arg << " to " << *AI << '\n'do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { { dbgs() << "Eliding argument copy from " <<
Arg << " to " << *AI << '\n' << " Replacing frame index "
<< OldIndex << " with " << FixedIndex <<
'\n'; }; } } while (false)
9400 << " Replacing frame index " << OldIndex << " with " << FixedIndexdo { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { { dbgs() << "Eliding argument copy from " <<
Arg << " to " << *AI << '\n' << " Replacing frame index "
<< OldIndex << " with " << FixedIndex <<
'\n'; }; } } while (false)
9401 << '\n';do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { { dbgs() << "Eliding argument copy from " <<
Arg << " to " << *AI << '\n' << " Replacing frame index "
<< OldIndex << " with " << FixedIndex <<
'\n'; }; } } while (false)
9402 })do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { { dbgs() << "Eliding argument copy from " <<
Arg << " to " << *AI << '\n' << " Replacing frame index "
<< OldIndex << " with " << FixedIndex <<
'\n'; }; } } while (false)
;
9403 MFI.RemoveStackObject(OldIndex);
9404 MFI.setIsImmutableObjectIndex(FixedIndex, false);
9405 AllocaIndex = FixedIndex;
9406 ArgCopyElisionFrameIndexMap.insert({OldIndex, FixedIndex});
9407 Chains.push_back(ArgVal.getValue(1));
9408
9409 // Avoid emitting code for the store implementing the copy.
9410 const StoreInst *SI = ArgCopyIter->second.second;
9411 ElidedArgCopyInstrs.insert(SI);
9412
9413 // Check for uses of the argument again so that we can avoid exporting ArgVal
9414 // if it is't used by anything other than the store.
9415 for (const Value *U : Arg.users()) {
9416 if (U != SI) {
9417 ArgHasUses = true;
9418 break;
9419 }
9420 }
9421}
9422
9423void SelectionDAGISel::LowerArguments(const Function &F) {
9424 SelectionDAG &DAG = SDB->DAG;
9425 SDLoc dl = SDB->getCurSDLoc();
9426 const DataLayout &DL = DAG.getDataLayout();
9427 SmallVector<ISD::InputArg, 16> Ins;
9428
9429 if (!FuncInfo->CanLowerReturn) {
9430 // Put in an sret pointer parameter before all the other parameters.
9431 SmallVector<EVT, 1> ValueVTs;
9432 ComputeValueVTs(*TLI, DAG.getDataLayout(),
9433 F.getReturnType()->getPointerTo(
9434 DAG.getDataLayout().getAllocaAddrSpace()),
9435 ValueVTs);
9436
9437 // NOTE: Assuming that a pointer will never break down to more than one VT
9438 // or one register.
9439 ISD::ArgFlagsTy Flags;
9440 Flags.setSRet();
9441 MVT RegisterVT = TLI->getRegisterType(*DAG.getContext(), ValueVTs[0]);
9442 ISD::InputArg RetArg(Flags, RegisterVT, ValueVTs[0], true,
9443 ISD::InputArg::NoArgIndex, 0);
9444 Ins.push_back(RetArg);
9445 }
9446
9447 // Look for stores of arguments to static allocas. Mark such arguments with a
9448 // flag to ask the target to give us the memory location of that argument if
9449 // available.
9450 ArgCopyElisionMapTy ArgCopyElisionCandidates;
9451 findArgumentCopyElisionCandidates(DL, FuncInfo, ArgCopyElisionCandidates);
9452
9453 // Set up the incoming argument description vector.
9454 for (const Argument &Arg : F.args()) {
9455 unsigned ArgNo = Arg.getArgNo();
9456 SmallVector<EVT, 4> ValueVTs;
9457 ComputeValueVTs(*TLI, DAG.getDataLayout(), Arg.getType(), ValueVTs);
9458 bool isArgValueUsed = !Arg.use_empty();
9459 unsigned PartBase = 0;
9460 Type *FinalType = Arg.getType();
9461 if (Arg.hasAttribute(Attribute::ByVal))
9462 FinalType = cast<PointerType>(FinalType)->getElementType();
9463 bool NeedsRegBlock = TLI->functionArgumentNeedsConsecutiveRegisters(
9464 FinalType, F.getCallingConv(), F.isVarArg());
9465 for (unsigned Value = 0, NumValues = ValueVTs.size();
9466 Value != NumValues; ++Value) {
9467 EVT VT = ValueVTs[Value];
9468 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
9469 ISD::ArgFlagsTy Flags;
9470
9471 // Certain targets (such as MIPS), may have a different ABI alignment
9472 // for a type depending on the context. Give the target a chance to
9473 // specify the alignment it wants.
9474 unsigned OriginalAlignment =
9475 TLI->getABIAlignmentForCallingConv(ArgTy, DL);
9476
9477 if (Arg.getType()->isPointerTy()) {
9478 Flags.setPointer();
9479 Flags.setPointerAddrSpace(
9480 cast<PointerType>(Arg.getType())->getAddressSpace());
9481 }
9482 if (Arg.hasAttribute(Attribute::ZExt))
9483 Flags.setZExt();
9484 if (Arg.hasAttribute(Attribute::SExt))
9485 Flags.setSExt();
9486 if (Arg.hasAttribute(Attribute::InReg)) {
9487 // If we are using vectorcall calling convention, a structure that is
9488 // passed InReg - is surely an HVA
9489 if (F.getCallingConv() == CallingConv::X86_VectorCall &&
9490 isa<StructType>(Arg.getType())) {
9491 // The first value of a structure is marked
9492 if (0 == Value)
9493 Flags.setHvaStart();
9494 Flags.setHva();
9495 }
9496 // Set InReg Flag
9497 Flags.setInReg();
9498 }
9499 if (Arg.hasAttribute(Attribute::StructRet))
9500 Flags.setSRet();
9501 if (Arg.hasAttribute(Attribute::SwiftSelf))
9502 Flags.setSwiftSelf();
9503 if (Arg.hasAttribute(Attribute::SwiftError))
9504 Flags.setSwiftError();
9505 if (Arg.hasAttribute(Attribute::ByVal))
9506 Flags.setByVal();
9507 if (Arg.hasAttribute(Attribute::InAlloca)) {
9508 Flags.setInAlloca();
9509 // Set the byval flag for CCAssignFn callbacks that don't know about
9510 // inalloca. This way we can know how many bytes we should've allocated
9511 // and how many bytes a callee cleanup function will pop. If we port
9512 // inalloca to more targets, we'll have to add custom inalloca handling
9513 // in the various CC lowering callbacks.
9514 Flags.setByVal();
9515 }
9516 if (F.getCallingConv() == CallingConv::X86_INTR) {
9517 // IA Interrupt passes frame (1st parameter) by value in the stack.
9518 if (ArgNo == 0)
9519 Flags.setByVal();
9520 }
9521 if (Flags.isByVal() || Flags.isInAlloca()) {
9522 PointerType *Ty = cast<PointerType>(Arg.getType());
9523 Type *ElementTy = Ty->getElementType();
9524 Flags.setByValSize(DL.getTypeAllocSize(ElementTy));
9525 // For ByVal, alignment should be passed from FE. BE will guess if
9526 // this info is not there but there are cases it cannot get right.
9527 unsigned FrameAlign;
9528 if (Arg.getParamAlignment())
9529 FrameAlign = Arg.getParamAlignment();
9530 else
9531 FrameAlign = TLI->getByValTypeAlignment(ElementTy, DL);
9532 Flags.setByValAlign(FrameAlign);
9533 }
9534 if (Arg.hasAttribute(Attribute::Nest))
9535 Flags.setNest();
9536 if (NeedsRegBlock)
9537 Flags.setInConsecutiveRegs();
9538 Flags.setOrigAlign(OriginalAlignment);
9539 if (ArgCopyElisionCandidates.count(&Arg))
9540 Flags.setCopyElisionCandidate();
9541
9542 MVT RegisterVT = TLI->getRegisterTypeForCallingConv(
9543 *CurDAG->getContext(), F.getCallingConv(), VT);
9544 unsigned NumRegs = TLI->getNumRegistersForCallingConv(
9545 *CurDAG->getContext(), F.getCallingConv(), VT);
9546 for (unsigned i = 0; i != NumRegs; ++i) {
9547 ISD::InputArg MyFlags(Flags, RegisterVT, VT, isArgValueUsed,
9548 ArgNo, PartBase+i*RegisterVT.getStoreSize());
9549 if (NumRegs > 1 && i == 0)
9550 MyFlags.Flags.setSplit();
9551 // if it isn't first piece, alignment must be 1
9552 else if (i > 0) {
9553 MyFlags.Flags.setOrigAlign(1);
9554 if (i == NumRegs - 1)
9555 MyFlags.Flags.setSplitEnd();
9556 }
9557 Ins.push_back(MyFlags);
9558 }
9559 if (NeedsRegBlock && Value == NumValues - 1)
9560 Ins[Ins.size() - 1].Flags.setInConsecutiveRegsLast();
9561 PartBase += VT.getStoreSize();
9562 }
9563 }
9564
9565 // Call the target to set up the argument values.
9566 SmallVector<SDValue, 8> InVals;
9567 SDValue NewRoot = TLI->LowerFormalArguments(
9568 DAG.getRoot(), F.getCallingConv(), F.isVarArg(), Ins, dl, DAG, InVals);
9569
9570 // Verify that the target's LowerFormalArguments behaved as expected.
9571 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&((NewRoot.getNode() && NewRoot.getValueType() == MVT::
Other && "LowerFormalArguments didn't return a valid chain!"
) ? static_cast<void> (0) : __assert_fail ("NewRoot.getNode() && NewRoot.getValueType() == MVT::Other && \"LowerFormalArguments didn't return a valid chain!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9572, __PRETTY_FUNCTION__))
9572 "LowerFormalArguments didn't return a valid chain!")((NewRoot.getNode() && NewRoot.getValueType() == MVT::
Other && "LowerFormalArguments didn't return a valid chain!"
) ? static_cast<void> (0) : __assert_fail ("NewRoot.getNode() && NewRoot.getValueType() == MVT::Other && \"LowerFormalArguments didn't return a valid chain!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9572, __PRETTY_FUNCTION__))
;
9573 assert(InVals.size() == Ins.size() &&((InVals.size() == Ins.size() && "LowerFormalArguments didn't emit the correct number of values!"
) ? static_cast<void> (0) : __assert_fail ("InVals.size() == Ins.size() && \"LowerFormalArguments didn't emit the correct number of values!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9574, __PRETTY_FUNCTION__))
9574 "LowerFormalArguments didn't emit the correct number of values!")((InVals.size() == Ins.size() && "LowerFormalArguments didn't emit the correct number of values!"
) ? static_cast<void> (0) : __assert_fail ("InVals.size() == Ins.size() && \"LowerFormalArguments didn't emit the correct number of values!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9574, __PRETTY_FUNCTION__))
;
9575 LLVM_DEBUG({do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { { for (unsigned i = 0, e = Ins.size(); i != e; ++
i) { ((InVals[i].getNode() && "LowerFormalArguments emitted a null value!"
) ? static_cast<void> (0) : __assert_fail ("InVals[i].getNode() && \"LowerFormalArguments emitted a null value!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9578, __PRETTY_FUNCTION__)); ((EVT(Ins[i].VT) == InVals[i].
getValueType() && "LowerFormalArguments emitted a value with the wrong type!"
) ? static_cast<void> (0) : __assert_fail ("EVT(Ins[i].VT) == InVals[i].getValueType() && \"LowerFormalArguments emitted a value with the wrong type!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9580, __PRETTY_FUNCTION__)); } }; } } while (false)
9576 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { { for (unsigned i = 0, e = Ins.size(); i != e; ++
i) { ((InVals[i].getNode() && "LowerFormalArguments emitted a null value!"
) ? static_cast<void> (0) : __assert_fail ("InVals[i].getNode() && \"LowerFormalArguments emitted a null value!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9578, __PRETTY_FUNCTION__)); ((EVT(Ins[i].VT) == InVals[i].
getValueType() && "LowerFormalArguments emitted a value with the wrong type!"
) ? static_cast<void> (0) : __assert_fail ("EVT(Ins[i].VT) == InVals[i].getValueType() && \"LowerFormalArguments emitted a value with the wrong type!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9580, __PRETTY_FUNCTION__)); } }; } } while (false)
9577 assert(InVals[i].getNode() &&do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { { for (unsigned i = 0, e = Ins.size(); i != e; ++
i) { ((InVals[i].getNode() && "LowerFormalArguments emitted a null value!"
) ? static_cast<void> (0) : __assert_fail ("InVals[i].getNode() && \"LowerFormalArguments emitted a null value!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9578, __PRETTY_FUNCTION__)); ((EVT(Ins[i].VT) == InVals[i].
getValueType() && "LowerFormalArguments emitted a value with the wrong type!"
) ? static_cast<void> (0) : __assert_fail ("EVT(Ins[i].VT) == InVals[i].getValueType() && \"LowerFormalArguments emitted a value with the wrong type!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9580, __PRETTY_FUNCTION__)); } }; } } while (false)
9578 "LowerFormalArguments emitted a null value!");do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { { for (unsigned i = 0, e = Ins.size(); i != e; ++
i) { ((InVals[i].getNode() && "LowerFormalArguments emitted a null value!"
) ? static_cast<void> (0) : __assert_fail ("InVals[i].getNode() && \"LowerFormalArguments emitted a null value!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9578, __PRETTY_FUNCTION__)); ((EVT(Ins[i].VT) == InVals[i].
getValueType() && "LowerFormalArguments emitted a value with the wrong type!"
) ? static_cast<void> (0) : __assert_fail ("EVT(Ins[i].VT) == InVals[i].getValueType() && \"LowerFormalArguments emitted a value with the wrong type!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9580, __PRETTY_FUNCTION__)); } }; } } while (false)
9579 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { { for (unsigned i = 0, e = Ins.size(); i != e; ++
i) { ((InVals[i].getNode() && "LowerFormalArguments emitted a null value!"
) ? static_cast<void> (0) : __assert_fail ("InVals[i].getNode() && \"LowerFormalArguments emitted a null value!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9578, __PRETTY_FUNCTION__)); ((EVT(Ins[i].VT) == InVals[i].
getValueType() && "LowerFormalArguments emitted a value with the wrong type!"
) ? static_cast<void> (0) : __assert_fail ("EVT(Ins[i].VT) == InVals[i].getValueType() && \"LowerFormalArguments emitted a value with the wrong type!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9580, __PRETTY_FUNCTION__)); } }; } } while (false)
9580 "LowerFormalArguments emitted a value with the wrong type!");do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { { for (unsigned i = 0, e = Ins.size(); i != e; ++
i) { ((InVals[i].getNode() && "LowerFormalArguments emitted a null value!"
) ? static_cast<void> (0) : __assert_fail ("InVals[i].getNode() && \"LowerFormalArguments emitted a null value!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9578, __PRETTY_FUNCTION__)); ((EVT(Ins[i].VT) == InVals[i].
getValueType() && "LowerFormalArguments emitted a value with the wrong type!"
) ? static_cast<void> (0) : __assert_fail ("EVT(Ins[i].VT) == InVals[i].getValueType() && \"LowerFormalArguments emitted a value with the wrong type!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9580, __PRETTY_FUNCTION__)); } }; } } while (false)
9581 }do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { { for (unsigned i = 0, e = Ins.size(); i != e; ++
i) { ((InVals[i].getNode() && "LowerFormalArguments emitted a null value!"
) ? static_cast<void> (0) : __assert_fail ("InVals[i].getNode() && \"LowerFormalArguments emitted a null value!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9578, __PRETTY_FUNCTION__)); ((EVT(Ins[i].VT) == InVals[i].
getValueType() && "LowerFormalArguments emitted a value with the wrong type!"
) ? static_cast<void> (0) : __assert_fail ("EVT(Ins[i].VT) == InVals[i].getValueType() && \"LowerFormalArguments emitted a value with the wrong type!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9580, __PRETTY_FUNCTION__)); } }; } } while (false)
9582 })do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { { for (unsigned i = 0, e = Ins.size(); i != e; ++
i) { ((InVals[i].getNode() && "LowerFormalArguments emitted a null value!"
) ? static_cast<void> (0) : __assert_fail ("InVals[i].getNode() && \"LowerFormalArguments emitted a null value!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9578, __PRETTY_FUNCTION__)); ((EVT(Ins[i].VT) == InVals[i].
getValueType() && "LowerFormalArguments emitted a value with the wrong type!"
) ? static_cast<void> (0) : __assert_fail ("EVT(Ins[i].VT) == InVals[i].getValueType() && \"LowerFormalArguments emitted a value with the wrong type!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9580, __PRETTY_FUNCTION__)); } }; } } while (false)
;
9583
9584 // Update the DAG with the new chain value resulting from argument lowering.
9585 DAG.setRoot(NewRoot);
9586
9587 // Set up the argument values.
9588 unsigned i = 0;
9589 if (!FuncInfo->CanLowerReturn) {
9590 // Create a virtual register for the sret pointer, and put in a copy
9591 // from the sret argument into it.
9592 SmallVector<EVT, 1> ValueVTs;
9593 ComputeValueVTs(*TLI, DAG.getDataLayout(),
9594 F.getReturnType()->getPointerTo(
9595 DAG.getDataLayout().getAllocaAddrSpace()),
9596 ValueVTs);
9597 MVT VT = ValueVTs[0].getSimpleVT();
9598 MVT RegVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
9599 Optional<ISD::NodeType> AssertOp = None;
9600 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1, RegVT, VT,
9601 nullptr, F.getCallingConv(), AssertOp);
9602
9603 MachineFunction& MF = SDB->DAG.getMachineFunction();
9604 MachineRegisterInfo& RegInfo = MF.getRegInfo();
9605 unsigned SRetReg = RegInfo.createVirtualRegister(TLI->getRegClassFor(RegVT));
9606 FuncInfo->DemoteRegister = SRetReg;
9607 NewRoot =
9608 SDB->DAG.getCopyToReg(NewRoot, SDB->getCurSDLoc(), SRetReg, ArgValue);
9609 DAG.setRoot(NewRoot);
9610
9611 // i indexes lowered arguments. Bump it past the hidden sret argument.
9612 ++i;
9613 }
9614
9615 SmallVector<SDValue, 4> Chains;
9616 DenseMap<int, int> ArgCopyElisionFrameIndexMap;
9617 for (const Argument &Arg : F.args()) {
9618 SmallVector<SDValue, 4> ArgValues;
9619 SmallVector<EVT, 4> ValueVTs;
9620 ComputeValueVTs(*TLI, DAG.getDataLayout(), Arg.getType(), ValueVTs);
9621 unsigned NumValues = ValueVTs.size();
9622 if (NumValues == 0)
9623 continue;
9624
9625 bool ArgHasUses = !Arg.use_empty();
9626
9627 // Elide the copying store if the target loaded this argument from a
9628 // suitable fixed stack object.
9629 if (Ins[i].Flags.isCopyElisionCandidate()) {
9630 tryToElideArgumentCopy(FuncInfo, Chains, ArgCopyElisionFrameIndexMap,
9631 ElidedArgCopyInstrs, ArgCopyElisionCandidates, Arg,
9632 InVals[i], ArgHasUses);
9633 }
9634
9635 // If this argument is unused then remember its value. It is used to generate
9636 // debugging information.
9637 bool isSwiftErrorArg =
9638 TLI->supportSwiftError() &&
9639 Arg.hasAttribute(Attribute::SwiftError);
9640 if (!ArgHasUses && !isSwiftErrorArg) {
9641 SDB->setUnusedArgValue(&Arg, InVals[i]);
9642
9643 // Also remember any frame index for use in FastISel.
9644 if (FrameIndexSDNode *FI =
9645 dyn_cast<FrameIndexSDNode>(InVals[i].getNode()))
9646 FuncInfo->setArgumentFrameIndex(&Arg, FI->getIndex());
9647 }
9648
9649 for (unsigned Val = 0; Val != NumValues; ++Val) {
9650 EVT VT = ValueVTs[Val];
9651 MVT PartVT = TLI->getRegisterTypeForCallingConv(*CurDAG->getContext(),
9652 F.getCallingConv(), VT);
9653 unsigned NumParts = TLI->getNumRegistersForCallingConv(
9654 *CurDAG->getContext(), F.getCallingConv(), VT);
9655
9656 // Even an apparant 'unused' swifterror argument needs to be returned. So
9657 // we do generate a copy for it that can be used on return from the
9658 // function.
9659 if (ArgHasUses || isSwiftErrorArg) {
9660 Optional<ISD::NodeType> AssertOp;
9661 if (Arg.hasAttribute(Attribute::SExt))
9662 AssertOp = ISD::AssertSext;
9663 else if (Arg.hasAttribute(Attribute::ZExt))
9664 AssertOp = ISD::AssertZext;
9665
9666 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i], NumParts,
9667 PartVT, VT, nullptr,
9668 F.getCallingConv(), AssertOp));
9669 }
9670
9671 i += NumParts;
9672 }
9673
9674 // We don't need to do anything else for unused arguments.
9675 if (ArgValues.empty())
9676 continue;
9677
9678 // Note down frame index.
9679 if (FrameIndexSDNode *FI =
9680 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode()))
9681 FuncInfo->setArgumentFrameIndex(&Arg, FI->getIndex());
9682
9683 SDValue Res = DAG.getMergeValues(makeArrayRef(ArgValues.data(), NumValues),
9684 SDB->getCurSDLoc());
9685
9686 SDB->setValue(&Arg, Res);
9687 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) {
9688 // We want to associate the argument with the frame index, among
9689 // involved operands, that correspond to the lowest address. The
9690 // getCopyFromParts function, called earlier, is swapping the order of
9691 // the operands to BUILD_PAIR depending on endianness. The result of
9692 // that swapping is that the least significant bits of the argument will
9693 // be in the first operand of the BUILD_PAIR node, and the most
9694 // significant bits will be in the second operand.
9695 unsigned LowAddressOp = DAG.getDataLayout().isBigEndian() ? 1 : 0;
9696 if (LoadSDNode *LNode =
9697 dyn_cast<LoadSDNode>(Res.getOperand(LowAddressOp).getNode()))
9698 if (FrameIndexSDNode *FI =
9699 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
9700 FuncInfo->setArgumentFrameIndex(&Arg, FI->getIndex());
9701 }
9702
9703 // Update the SwiftErrorVRegDefMap.
9704 if (Res.getOpcode() == ISD::CopyFromReg && isSwiftErrorArg) {
9705 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg();
9706 if (TargetRegisterInfo::isVirtualRegister(Reg))
9707 FuncInfo->setCurrentSwiftErrorVReg(FuncInfo->MBB,
9708 FuncInfo->SwiftErrorArg, Reg);
9709 }
9710
9711 // If this argument is live outside of the entry block, insert a copy from
9712 // wherever we got it to the vreg that other BB's will reference it as.
9713 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) {
9714 // If we can, though, try to skip creating an unnecessary vreg.
9715 // FIXME: This isn't very clean... it would be nice to make this more
9716 // general. It's also subtly incompatible with the hacks FastISel
9717 // uses with vregs.
9718 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg();
9719 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
9720 FuncInfo->ValueMap[&Arg] = Reg;
9721 continue;
9722 }
9723 }
9724 if (!isOnlyUsedInEntryBlock(&Arg, TM.Options.EnableFastISel)) {
9725 FuncInfo->InitializeRegForValue(&Arg);
9726 SDB->CopyToExportRegsIfNeeded(&Arg);
9727 }
9728 }
9729
9730 if (!Chains.empty()) {
9731 Chains.push_back(NewRoot);
9732 NewRoot = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
9733 }
9734
9735 DAG.setRoot(NewRoot);
9736
9737 assert(i == InVals.size() && "Argument register count mismatch!")((i == InVals.size() && "Argument register count mismatch!"
) ? static_cast<void> (0) : __assert_fail ("i == InVals.size() && \"Argument register count mismatch!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9737, __PRETTY_FUNCTION__))
;
9738
9739 // If any argument copy elisions occurred and we have debug info, update the
9740 // stale frame indices used in the dbg.declare variable info table.
9741 MachineFunction::VariableDbgInfoMapTy &DbgDeclareInfo = MF->getVariableDbgInfo();
9742 if (!DbgDeclareInfo.empty() && !ArgCopyElisionFrameIndexMap.empty()) {
9743 for (MachineFunction::VariableDbgInfo &VI : DbgDeclareInfo) {
9744 auto I = ArgCopyElisionFrameIndexMap.find(VI.Slot);
9745 if (I != ArgCopyElisionFrameIndexMap.end())
9746 VI.Slot = I->second;
9747 }
9748 }
9749
9750 // Finally, if the target has anything special to do, allow it to do so.
9751 EmitFunctionEntryCode();
9752}
9753
9754/// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
9755/// ensure constants are generated when needed. Remember the virtual registers
9756/// that need to be added to the Machine PHI nodes as input. We cannot just
9757/// directly add them, because expansion might result in multiple MBB's for one
9758/// BB. As such, the start of the BB might correspond to a different MBB than
9759/// the end.
9760void
9761SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
9762 const Instruction *TI = LLVMBB->getTerminator();
9763
9764 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
9765
9766 // Check PHI nodes in successors that expect a value to be available from this
9767 // block.
9768 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
9769 const BasicBlock *SuccBB = TI->getSuccessor(succ);
9770 if (!isa<PHINode>(SuccBB->begin())) continue;
9771 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
9772
9773 // If this terminator has multiple identical successors (common for
9774 // switches), only handle each succ once.
9775 if (!SuccsHandled.insert(SuccMBB).second)
9776 continue;
9777
9778 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
9779
9780 // At this point we know that there is a 1-1 correspondence between LLVM PHI
9781 // nodes and Machine PHI nodes, but the incoming operands have not been
9782 // emitted yet.
9783 for (const PHINode &PN : SuccBB->phis()) {
9784 // Ignore dead phi's.
9785 if (PN.use_empty())
9786 continue;
9787
9788 // Skip empty types
9789 if (PN.getType()->isEmptyTy())
9790 continue;
9791
9792 unsigned Reg;
9793 const Value *PHIOp = PN.getIncomingValueForBlock(LLVMBB);
9794
9795 if (const Constant *C = dyn_cast<Constant>(PHIOp)) {
9796 unsigned &RegOut = ConstantsOut[C];
9797 if (RegOut == 0) {
9798 RegOut = FuncInfo.CreateRegs(C->getType());
9799 CopyValueToVirtualRegister(C, RegOut);
9800 }
9801 Reg = RegOut;
9802 } else {
9803 DenseMap<const Value *, unsigned>::iterator I =
9804 FuncInfo.ValueMap.find(PHIOp);
9805 if (I != FuncInfo.ValueMap.end())
9806 Reg = I->second;
9807 else {
9808 assert(isa<AllocaInst>(PHIOp) &&((isa<AllocaInst>(PHIOp) && FuncInfo.StaticAllocaMap
.count(cast<AllocaInst>(PHIOp)) && "Didn't codegen value into a register!??"
) ? static_cast<void> (0) : __assert_fail ("isa<AllocaInst>(PHIOp) && FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) && \"Didn't codegen value into a register!??\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9810, __PRETTY_FUNCTION__))
9809 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&((isa<AllocaInst>(PHIOp) && FuncInfo.StaticAllocaMap
.count(cast<AllocaInst>(PHIOp)) && "Didn't codegen value into a register!??"
) ? static_cast<void> (0) : __assert_fail ("isa<AllocaInst>(PHIOp) && FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) && \"Didn't codegen value into a register!??\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9810, __PRETTY_FUNCTION__))
9810 "Didn't codegen value into a register!??")((isa<AllocaInst>(PHIOp) && FuncInfo.StaticAllocaMap
.count(cast<AllocaInst>(PHIOp)) && "Didn't codegen value into a register!??"
) ? static_cast<void> (0) : __assert_fail ("isa<AllocaInst>(PHIOp) && FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) && \"Didn't codegen value into a register!??\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9810, __PRETTY_FUNCTION__))
;
9811 Reg = FuncInfo.CreateRegs(PHIOp->getType());
9812 CopyValueToVirtualRegister(PHIOp, Reg);
9813 }
9814 }
9815
9816 // Remember that this register needs to added to the machine PHI node as
9817 // the input for this MBB.
9818 SmallVector<EVT, 4> ValueVTs;
9819 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9820 ComputeValueVTs(TLI, DAG.getDataLayout(), PN.getType(), ValueVTs);
9821 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
9822 EVT VT = ValueVTs[vti];
9823 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT);
9824 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
9825 FuncInfo.PHINodesToUpdate.push_back(
9826 std::make_pair(&*MBBI++, Reg + i));
9827 Reg += NumRegisters;
9828 }
9829 }
9830 }
9831
9832 ConstantsOut.clear();
9833}
9834
9835/// Add a successor MBB to ParentMBB< creating a new MachineBB for BB if SuccMBB
9836/// is 0.
9837MachineBasicBlock *
9838SelectionDAGBuilder::StackProtectorDescriptor::
9839AddSuccessorMBB(const BasicBlock *BB,
9840 MachineBasicBlock *ParentMBB,
9841 bool IsLikely,
9842 MachineBasicBlock *SuccMBB) {
9843 // If SuccBB has not been created yet, create it.
9844 if (!SuccMBB) {
9845 MachineFunction *MF = ParentMBB->getParent();
9846 MachineFunction::iterator BBI(ParentMBB);
9847 SuccMBB = MF->CreateMachineBasicBlock(BB);
9848 MF->insert(++BBI, SuccMBB);
9849 }
9850 // Add it as a successor of ParentMBB.
9851 ParentMBB->addSuccessor(
9852 SuccMBB, BranchProbabilityInfo::getBranchProbStackProtector(IsLikely));
9853 return SuccMBB;
9854}
9855
9856MachineBasicBlock *SelectionDAGBuilder::NextBlock(MachineBasicBlock *MBB) {
9857 MachineFunction::iterator I(MBB);
9858 if (++I == FuncInfo.MF->end())
9859 return nullptr;
9860 return &*I;
9861}
9862
9863/// During lowering new call nodes can be created (such as memset, etc.).
9864/// Those will become new roots of the current DAG, but complications arise
9865/// when they are tail calls. In such cases, the call lowering will update
9866/// the root, but the builder still needs to know that a tail call has been
9867/// lowered in order to avoid generating an additional return.
9868void SelectionDAGBuilder::updateDAGForMaybeTailCall(SDValue MaybeTC) {
9869 // If the node is null, we do have a tail call.
9870 if (MaybeTC.getNode() != nullptr)
9871 DAG.setRoot(MaybeTC);
9872 else
9873 HasTailCall = true;
9874}
9875
9876uint64_t
9877SelectionDAGBuilder::getJumpTableRange(const CaseClusterVector &Clusters,
9878 unsigned First, unsigned Last) const {
9879 assert(Last >= First)((Last >= First) ? static_cast<void> (0) : __assert_fail
("Last >= First", "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9879, __PRETTY_FUNCTION__))
;
9880 const APInt &LowCase = Clusters[First].Low->getValue();
9881 const APInt &HighCase = Clusters[Last].High->getValue();
9882 assert(LowCase.getBitWidth() == HighCase.getBitWidth())((LowCase.getBitWidth() == HighCase.getBitWidth()) ? static_cast
<void> (0) : __assert_fail ("LowCase.getBitWidth() == HighCase.getBitWidth()"
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9882, __PRETTY_FUNCTION__))
;
9883
9884 // FIXME: A range of consecutive cases has 100% density, but only requires one
9885 // comparison to lower. We should discriminate against such consecutive ranges
9886 // in jump tables.
9887
9888 return (HighCase - LowCase).getLimitedValue((UINT64_MAX(18446744073709551615UL) - 1) / 100) + 1;
9889}
9890
9891uint64_t SelectionDAGBuilder::getJumpTableNumCases(
9892 const SmallVectorImpl<unsigned> &TotalCases, unsigned First,
9893 unsigned Last) const {
9894 assert(Last >= First)((Last >= First) ? static_cast<void> (0) : __assert_fail
("Last >= First", "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9894, __PRETTY_FUNCTION__))
;
9895 assert(TotalCases[Last] >= TotalCases[First])((TotalCases[Last] >= TotalCases[First]) ? static_cast<
void> (0) : __assert_fail ("TotalCases[Last] >= TotalCases[First]"
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9895, __PRETTY_FUNCTION__))
;
9896 uint64_t NumCases =
9897 TotalCases[Last] - (First == 0 ? 0 : TotalCases[First - 1]);
9898 return NumCases;
9899}
9900
9901bool SelectionDAGBuilder::buildJumpTable(const CaseClusterVector &Clusters,
9902 unsigned First, unsigned Last,
9903 const SwitchInst *SI,
9904 MachineBasicBlock *DefaultMBB,
9905 CaseCluster &JTCluster) {
9906 assert(First <= Last)((First <= Last) ? static_cast<void> (0) : __assert_fail
("First <= Last", "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9906, __PRETTY_FUNCTION__))
;
9907
9908 auto Prob = BranchProbability::getZero();
9909 unsigned NumCmps = 0;
9910 std::vector<MachineBasicBlock*> Table;
9911 DenseMap<MachineBasicBlock*, BranchProbability> JTProbs;
9912
9913 // Initialize probabilities in JTProbs.
9914 for (unsigned I = First; I <= Last; ++I)
9915 JTProbs[Clusters[I].MBB] = BranchProbability::getZero();
9916
9917 for (unsigned I = First; I <= Last; ++I) {
9918 assert(Clusters[I].Kind == CC_Range)((Clusters[I].Kind == CC_Range) ? static_cast<void> (0)
: __assert_fail ("Clusters[I].Kind == CC_Range", "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9918, __PRETTY_FUNCTION__))
;
9919 Prob += Clusters[I].Prob;
9920 const APInt &Low = Clusters[I].Low->getValue();
9921 const APInt &High = Clusters[I].High->getValue();
9922 NumCmps += (Low == High) ? 1 : 2;
9923 if (I != First) {
9924 // Fill the gap between this and the previous cluster.
9925 const APInt &PreviousHigh = Clusters[I - 1].High->getValue();
9926 assert(PreviousHigh.slt(Low))((PreviousHigh.slt(Low)) ? static_cast<void> (0) : __assert_fail
("PreviousHigh.slt(Low)", "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9926, __PRETTY_FUNCTION__))
;
9927 uint64_t Gap = (Low - PreviousHigh).getLimitedValue() - 1;
9928 for (uint64_t J = 0; J < Gap; J++)
9929 Table.push_back(DefaultMBB);
9930 }
9931 uint64_t ClusterSize = (High - Low).getLimitedValue() + 1;
9932 for (uint64_t J = 0; J < ClusterSize; ++J)
9933 Table.push_back(Clusters[I].MBB);
9934 JTProbs[Clusters[I].MBB] += Clusters[I].Prob;
9935 }
9936
9937 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9938 unsigned NumDests = JTProbs.size();
9939 if (TLI.isSuitableForBitTests(
9940 NumDests, NumCmps, Clusters[First].Low->getValue(),
9941 Clusters[Last].High->getValue(), DAG.getDataLayout())) {
9942 // Clusters[First..Last] should be lowered as bit tests instead.
9943 return false;
9944 }
9945
9946 // Create the MBB that will load from and jump through the table.
9947 // Note: We create it here, but it's not inserted into the function yet.
9948 MachineFunction *CurMF = FuncInfo.MF;
9949 MachineBasicBlock *JumpTableMBB =
9950 CurMF->CreateMachineBasicBlock(SI->getParent());
9951
9952 // Add successors. Note: use table order for determinism.
9953 SmallPtrSet<MachineBasicBlock *, 8> Done;
9954 for (MachineBasicBlock *Succ : Table) {
9955 if (Done.count(Succ))
9956 continue;
9957 addSuccessorWithProb(JumpTableMBB, Succ, JTProbs[Succ]);
9958 Done.insert(Succ);
9959 }
9960 JumpTableMBB->normalizeSuccProbs();
9961
9962 unsigned JTI = CurMF->getOrCreateJumpTableInfo(TLI.getJumpTableEncoding())
9963 ->createJumpTableIndex(Table);
9964
9965 // Set up the jump table info.
9966 JumpTable JT(-1U, JTI, JumpTableMBB, nullptr);
9967 JumpTableHeader JTH(Clusters[First].Low->getValue(),
9968 Clusters[Last].High->getValue(), SI->getCondition(),
9969 nullptr, false);
9970 JTCases.emplace_back(std::move(JTH), std::move(JT));
9971
9972 JTCluster = CaseCluster::jumpTable(Clusters[First].Low, Clusters[Last].High,
9973 JTCases.size() - 1, Prob);
9974 return true;
9975}
9976
9977void SelectionDAGBuilder::findJumpTables(CaseClusterVector &Clusters,
9978 const SwitchInst *SI,
9979 MachineBasicBlock *DefaultMBB) {
9980#ifndef NDEBUG
9981 // Clusters must be non-empty, sorted, and only contain Range clusters.
9982 assert(!Clusters.empty())((!Clusters.empty()) ? static_cast<void> (0) : __assert_fail
("!Clusters.empty()", "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9982, __PRETTY_FUNCTION__))
;
9983 for (CaseCluster &C : Clusters)
9984 assert(C.Kind == CC_Range)((C.Kind == CC_Range) ? static_cast<void> (0) : __assert_fail
("C.Kind == CC_Range", "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9984, __PRETTY_FUNCTION__))
;
9985 for (unsigned i = 1, e = Clusters.size(); i < e; ++i)
9986 assert(Clusters[i - 1].High->getValue().slt(Clusters[i].Low->getValue()))((Clusters[i - 1].High->getValue().slt(Clusters[i].Low->
getValue())) ? static_cast<void> (0) : __assert_fail ("Clusters[i - 1].High->getValue().slt(Clusters[i].Low->getValue())"
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 9986, __PRETTY_FUNCTION__))
;
9987#endif
9988
9989 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9990 if (!TLI.areJTsAllowed(SI->getParent()->getParent()))
9991 return;
9992
9993 const int64_t N = Clusters.size();
9994 const unsigned MinJumpTableEntries = TLI.getMinimumJumpTableEntries();
9995 const unsigned SmallNumberOfEntries = MinJumpTableEntries / 2;
9996
9997 if (N < 2 || N < MinJumpTableEntries)
9998 return;
9999
10000 // TotalCases[i]: Total nbr of cases in Clusters[0..i].
10001 SmallVector<unsigned, 8> TotalCases(N);
10002 for (unsigned i = 0; i < N; ++i) {
10003 const APInt &Hi = Clusters[i].High->getValue();
10004 const APInt &Lo = Clusters[i].Low->getValue();
10005 TotalCases[i] = (Hi - Lo).getLimitedValue() + 1;
10006 if (i != 0)
10007 TotalCases[i] += TotalCases[i - 1];
10008 }
10009
10010 // Cheap case: the whole range may be suitable for jump table.
10011 uint64_t Range = getJumpTableRange(Clusters,0, N - 1);
10012 uint64_t NumCases = getJumpTableNumCases(TotalCases, 0, N - 1);
10013 assert(NumCases < UINT64_MAX / 100)((NumCases < (18446744073709551615UL) / 100) ? static_cast
<void> (0) : __assert_fail ("NumCases < UINT64_MAX / 100"
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 10013, __PRETTY_FUNCTION__))
;
10014 assert(Range >= NumCases)((Range >= NumCases) ? static_cast<void> (0) : __assert_fail
("Range >= NumCases", "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 10014, __PRETTY_FUNCTION__))
;
10015 if (TLI.isSuitableForJumpTable(SI, NumCases, Range)) {
10016 CaseCluster JTCluster;
10017 if (buildJumpTable(Clusters, 0, N - 1, SI, DefaultMBB, JTCluster)) {
10018 Clusters[0] = JTCluster;
10019 Clusters.resize(1);
10020 return;
10021 }
10022 }
10023
10024 // The algorithm below is not suitable for -O0.
10025 if (TM.getOptLevel() == CodeGenOpt::None)
10026 return;
10027
10028 // Split Clusters into minimum number of dense partitions. The algorithm uses
10029 // the same idea as Kannan & Proebsting "Correction to 'Producing Good Code
10030 // for the Case Statement'" (1994), but builds the MinPartitions array in
10031 // reverse order to make it easier to reconstruct the partitions in ascending
10032 // order. In the choice between two optimal partitionings, it picks the one
10033 // which yields more jump tables.
10034
10035 // MinPartitions[i] is the minimum nbr of partitions of Clusters[i..N-1].
10036 SmallVector<unsigned, 8> MinPartitions(N);
10037 // LastElement[i] is the last element of the partition starting at i.
10038 SmallVector<unsigned, 8> LastElement(N);
10039 // PartitionsScore[i] is used to break ties when choosing between two
10040 // partitionings resulting in the same number of partitions.
10041 SmallVector<unsigned, 8> PartitionsScore(N);
10042 // For PartitionsScore, a small number of comparisons is considered as good as
10043 // a jump table and a single comparison is considered better than a jump
10044 // table.
10045 enum PartitionScores : unsigned {
10046 NoTable = 0,
10047 Table = 1,
10048 FewCases = 1,
10049 SingleCase = 2
10050 };
10051
10052 // Base case: There is only one way to partition Clusters[N-1].
10053 MinPartitions[N - 1] = 1;
10054 LastElement[N - 1] = N - 1;
10055 PartitionsScore[N - 1] = PartitionScores::SingleCase;
10056
10057 // Note: loop indexes are signed to avoid underflow.
10058 for (int64_t i = N - 2; i >= 0; i--) {
10059 // Find optimal partitioning of Clusters[i..N-1].
10060 // Baseline: Put Clusters[i] into a partition on its own.
10061 MinPartitions[i] = MinPartitions[i + 1] + 1;
10062 LastElement[i] = i;
10063 PartitionsScore[i] = PartitionsScore[i + 1] + PartitionScores::SingleCase;
10064
10065 // Search for a solution that results in fewer partitions.
10066 for (int64_t j = N - 1; j > i; j--) {
10067 // Try building a partition from Clusters[i..j].
10068 uint64_t Range = getJumpTableRange(Clusters, i, j);
10069 uint64_t NumCases = getJumpTableNumCases(TotalCases, i, j);
10070 assert(NumCases < UINT64_MAX / 100)((NumCases < (18446744073709551615UL) / 100) ? static_cast
<void> (0) : __assert_fail ("NumCases < UINT64_MAX / 100"
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 10070, __PRETTY_FUNCTION__))
;
10071 assert(Range >= NumCases)((Range >= NumCases) ? static_cast<void> (0) : __assert_fail
("Range >= NumCases", "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 10071, __PRETTY_FUNCTION__))
;
10072 if (TLI.isSuitableForJumpTable(SI, NumCases, Range)) {
10073 unsigned NumPartitions = 1 + (j == N - 1 ? 0 : MinPartitions[j + 1]);
10074 unsigned Score = j == N - 1 ? 0 : PartitionsScore[j + 1];
10075 int64_t NumEntries = j - i + 1;
10076
10077 if (NumEntries == 1)
10078 Score += PartitionScores::SingleCase;
10079 else if (NumEntries <= SmallNumberOfEntries)
10080 Score += PartitionScores::FewCases;
10081 else if (NumEntries >= MinJumpTableEntries)
10082 Score += PartitionScores::Table;
10083
10084 // If this leads to fewer partitions, or to the same number of
10085 // partitions with better score, it is a better partitioning.
10086 if (NumPartitions < MinPartitions[i] ||
10087 (NumPartitions == MinPartitions[i] && Score > PartitionsScore[i])) {
10088 MinPartitions[i] = NumPartitions;
10089 LastElement[i] = j;
10090 PartitionsScore[i] = Score;
10091 }
10092 }
10093 }
10094 }
10095
10096 // Iterate over the partitions, replacing some with jump tables in-place.
10097 unsigned DstIndex = 0;
10098 for (unsigned First = 0, Last; First < N; First = Last + 1) {
10099 Last = LastElement[First];
10100 assert(Last >= First)((Last >= First) ? static_cast<void> (0) : __assert_fail
("Last >= First", "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 10100, __PRETTY_FUNCTION__))
;
10101 assert(DstIndex <= First)((DstIndex <= First) ? static_cast<void> (0) : __assert_fail
("DstIndex <= First", "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 10101, __PRETTY_FUNCTION__))
;
10102 unsigned NumClusters = Last - First + 1;
10103
10104 CaseCluster JTCluster;
10105 if (NumClusters >= MinJumpTableEntries &&
10106 buildJumpTable(Clusters, First, Last, SI, DefaultMBB, JTCluster)) {
10107 Clusters[DstIndex++] = JTCluster;
10108 } else {
10109 for (unsigned I = First; I <= Last; ++I)
10110 std::memmove(&Clusters[DstIndex++], &Clusters[I], sizeof(Clusters[I]));
10111 }
10112 }
10113 Clusters.resize(DstIndex);
10114}
10115
10116bool SelectionDAGBuilder::buildBitTests(CaseClusterVector &Clusters,
10117 unsigned First, unsigned Last,
10118 const SwitchInst *SI,
10119 CaseCluster &BTCluster) {
10120 assert(First <= Last)((First <= Last) ? static_cast<void> (0) : __assert_fail
("First <= Last", "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 10120, __PRETTY_FUNCTION__))
;
10121 if (First == Last)
10122 return false;
10123
10124 BitVector Dests(FuncInfo.MF->getNumBlockIDs());
10125 unsigned NumCmps = 0;
10126 for (int64_t I = First; I <= Last; ++I) {
10127 assert(Clusters[I].Kind == CC_Range)((Clusters[I].Kind == CC_Range) ? static_cast<void> (0)
: __assert_fail ("Clusters[I].Kind == CC_Range", "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 10127, __PRETTY_FUNCTION__))
;
10128 Dests.set(Clusters[I].MBB->getNumber());
10129 NumCmps += (Clusters[I].Low == Clusters[I].High) ? 1 : 2;
10130 }
10131 unsigned NumDests = Dests.count();
10132
10133 APInt Low = Clusters[First].Low->getValue();
10134 APInt High = Clusters[Last].High->getValue();
10135 assert(Low.slt(High))((Low.slt(High)) ? static_cast<void> (0) : __assert_fail
("Low.slt(High)", "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 10135, __PRETTY_FUNCTION__))
;
10136
10137 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
10138 const DataLayout &DL = DAG.getDataLayout();
10139 if (!TLI.isSuitableForBitTests(NumDests, NumCmps, Low, High, DL))
10140 return false;
10141
10142 APInt LowBound;
10143 APInt CmpRange;
10144
10145 const int BitWidth = TLI.getPointerTy(DL).getSizeInBits();
10146 assert(TLI.rangeFitsInWord(Low, High, DL) &&((TLI.rangeFitsInWord(Low, High, DL) && "Case range must fit in bit mask!"
) ? static_cast<void> (0) : __assert_fail ("TLI.rangeFitsInWord(Low, High, DL) && \"Case range must fit in bit mask!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 10147, __PRETTY_FUNCTION__))
10147 "Case range must fit in bit mask!")((TLI.rangeFitsInWord(Low, High, DL) && "Case range must fit in bit mask!"
) ? static_cast<void> (0) : __assert_fail ("TLI.rangeFitsInWord(Low, High, DL) && \"Case range must fit in bit mask!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 10147, __PRETTY_FUNCTION__))
;
10148
10149 // Check if the clusters cover a contiguous range such that no value in the
10150 // range will jump to the default statement.
10151 bool ContiguousRange = true;
10152 for (int64_t I = First + 1; I <= Last; ++I) {
10153 if (Clusters[I].Low->getValue() != Clusters[I - 1].High->getValue() + 1) {
10154 ContiguousRange = false;
10155 break;
10156 }
10157 }
10158
10159 if (Low.isStrictlyPositive() && High.slt(BitWidth)) {
10160 // Optimize the case where all the case values fit in a word without having
10161 // to subtract minValue. In this case, we can optimize away the subtraction.
10162 LowBound = APInt::getNullValue(Low.getBitWidth());
10163 CmpRange = High;
10164 ContiguousRange = false;
10165 } else {
10166 LowBound = Low;
10167 CmpRange = High - Low;
10168 }
10169
10170 CaseBitsVector CBV;
10171 auto TotalProb = BranchProbability::getZero();
10172 for (unsigned i = First; i <= Last; ++i) {
10173 // Find the CaseBits for this destination.
10174 unsigned j;
10175 for (j = 0; j < CBV.size(); ++j)
10176 if (CBV[j].BB == Clusters[i].MBB)
10177 break;
10178 if (j == CBV.size())
10179 CBV.push_back(
10180 CaseBits(0, Clusters[i].MBB, 0, BranchProbability::getZero()));
10181 CaseBits *CB = &CBV[j];
10182
10183 // Update Mask, Bits and ExtraProb.
10184 uint64_t Lo = (Clusters[i].Low->getValue() - LowBound).getZExtValue();
10185 uint64_t Hi = (Clusters[i].High->getValue() - LowBound).getZExtValue();
10186 assert(Hi >= Lo && Hi < 64 && "Invalid bit case!")((Hi >= Lo && Hi < 64 && "Invalid bit case!"
) ? static_cast<void> (0) : __assert_fail ("Hi >= Lo && Hi < 64 && \"Invalid bit case!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 10186, __PRETTY_FUNCTION__))
;
10187 CB->Mask |= (-1ULL >> (63 - (Hi - Lo))) << Lo;
10188 CB->Bits += Hi - Lo + 1;
10189 CB->ExtraProb += Clusters[i].Prob;
10190 TotalProb += Clusters[i].Prob;
10191 }
10192
10193 BitTestInfo BTI;
10194 llvm::sort(CBV, [](const CaseBits &a, const CaseBits &b) {
10195 // Sort by probability first, number of bits second, bit mask third.
10196 if (a.ExtraProb != b.ExtraProb)
10197 return a.ExtraProb > b.ExtraProb;
10198 if (a.Bits != b.Bits)
10199 return a.Bits > b.Bits;
10200 return a.Mask < b.Mask;
10201 });
10202
10203 for (auto &CB : CBV) {
10204 MachineBasicBlock *BitTestBB =
10205 FuncInfo.MF->CreateMachineBasicBlock(SI->getParent());
10206 BTI.push_back(BitTestCase(CB.Mask, BitTestBB, CB.BB, CB.ExtraProb));
10207 }
10208 BitTestCases.emplace_back(std::move(LowBound), std::move(CmpRange),
10209 SI->getCondition(), -1U, MVT::Other, false,
10210 ContiguousRange, nullptr, nullptr, std::move(BTI),
10211 TotalProb);
10212
10213 BTCluster = CaseCluster::bitTests(Clusters[First].Low, Clusters[Last].High,
10214 BitTestCases.size() - 1, TotalProb);
10215 return true;
10216}
10217
10218void SelectionDAGBuilder::findBitTestClusters(CaseClusterVector &Clusters,
10219 const SwitchInst *SI) {
10220// Partition Clusters into as few subsets as possible, where each subset has a
10221// range that fits in a machine word and has <= 3 unique destinations.
10222
10223#ifndef NDEBUG
10224 // Clusters must be sorted and contain Range or JumpTable clusters.
10225 assert(!Clusters.empty())((!Clusters.empty()) ? static_cast<void> (0) : __assert_fail
("!Clusters.empty()", "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 10225, __PRETTY_FUNCTION__))
;
10226 assert(Clusters[0].Kind == CC_Range || Clusters[0].Kind == CC_JumpTable)((Clusters[0].Kind == CC_Range || Clusters[0].Kind == CC_JumpTable
) ? static_cast<void> (0) : __assert_fail ("Clusters[0].Kind == CC_Range || Clusters[0].Kind == CC_JumpTable"
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 10226, __PRETTY_FUNCTION__))
;
10227 for (const CaseCluster &C : Clusters)
10228 assert(C.Kind == CC_Range || C.Kind == CC_JumpTable)((C.Kind == CC_Range || C.Kind == CC_JumpTable) ? static_cast
<void> (0) : __assert_fail ("C.Kind == CC_Range || C.Kind == CC_JumpTable"
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 10228, __PRETTY_FUNCTION__))
;
10229 for (unsigned i = 1; i < Clusters.size(); ++i)
10230 assert(Clusters[i-1].High->getValue().slt(Clusters[i].Low->getValue()))((Clusters[i-1].High->getValue().slt(Clusters[i].Low->getValue
())) ? static_cast<void> (0) : __assert_fail ("Clusters[i-1].High->getValue().slt(Clusters[i].Low->getValue())"
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 10230, __PRETTY_FUNCTION__))
;
10231#endif
10232
10233 // The algorithm below is not suitable for -O0.
10234 if (TM.getOptLevel() == CodeGenOpt::None)
10235 return;
10236
10237 // If target does not have legal shift left, do not emit bit tests at all.
10238 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
10239 const DataLayout &DL = DAG.getDataLayout();
10240
10241 EVT PTy = TLI.getPointerTy(DL);
10242 if (!TLI.isOperationLegal(ISD::SHL, PTy))
10243 return;
10244
10245 int BitWidth = PTy.getSizeInBits();
10246 const int64_t N = Clusters.size();
10247
10248 // MinPartitions[i] is the minimum nbr of partitions of Clusters[i..N-1].
10249 SmallVector<unsigned, 8> MinPartitions(N);
10250 // LastElement[i] is the last element of the partition starting at i.
10251 SmallVector<unsigned, 8> LastElement(N);
10252
10253 // FIXME: This might not be the best algorithm for finding bit test clusters.
10254
10255 // Base case: There is only one way to partition Clusters[N-1].
10256 MinPartitions[N - 1] = 1;
10257 LastElement[N - 1] = N - 1;
10258
10259 // Note: loop indexes are signed to avoid underflow.
10260 for (int64_t i = N - 2; i >= 0; --i) {
10261 // Find optimal partitioning of Clusters[i..N-1].
10262 // Baseline: Put Clusters[i] into a partition on its own.
10263 MinPartitions[i] = MinPartitions[i + 1] + 1;
10264 LastElement[i] = i;
10265
10266 // Search for a solution that results in fewer partitions.
10267 // Note: the search is limited by BitWidth, reducing time complexity.
10268 for (int64_t j = std::min(N - 1, i + BitWidth - 1); j > i; --j) {
10269 // Try building a partition from Clusters[i..j].
10270
10271 // Check the range.
10272 if (!TLI.rangeFitsInWord(Clusters[i].Low->getValue(),
10273 Clusters[j].High->getValue(), DL))
10274 continue;
10275
10276 // Check nbr of destinations and cluster types.
10277 // FIXME: This works, but doesn't seem very efficient.
10278 bool RangesOnly = true;
10279 BitVector Dests(FuncInfo.MF->getNumBlockIDs());
10280 for (int64_t k = i; k <= j; k++) {
10281 if (Clusters[k].Kind != CC_Range) {
10282 RangesOnly = false;
10283 break;
10284 }
10285 Dests.set(Clusters[k].MBB->getNumber());
10286 }
10287 if (!RangesOnly || Dests.count() > 3)
10288 break;
10289
10290 // Check if it's a better partition.
10291 unsigned NumPartitions = 1 + (j == N - 1 ? 0 : MinPartitions[j + 1]);
10292 if (NumPartitions < MinPartitions[i]) {
10293 // Found a better partition.
10294 MinPartitions[i] = NumPartitions;
10295 LastElement[i] = j;
10296 }
10297 }
10298 }
10299
10300 // Iterate over the partitions, replacing with bit-test clusters in-place.
10301 unsigned DstIndex = 0;
10302 for (unsigned First = 0, Last; First < N; First = Last + 1) {
10303 Last = LastElement[First];
10304 assert(First <= Last)((First <= Last) ? static_cast<void> (0) : __assert_fail
("First <= Last", "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 10304, __PRETTY_FUNCTION__))
;
10305 assert(DstIndex <= First)((DstIndex <= First) ? static_cast<void> (0) : __assert_fail
("DstIndex <= First", "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 10305, __PRETTY_FUNCTION__))
;
10306
10307 CaseCluster BitTestCluster;
10308 if (buildBitTests(Clusters, First, Last, SI, BitTestCluster)) {
10309 Clusters[DstIndex++] = BitTestCluster;
10310 } else {
10311 size_t NumClusters = Last - First + 1;
10312 std::memmove(&Clusters[DstIndex], &Clusters[First],
10313 sizeof(Clusters[0]) * NumClusters);
10314 DstIndex += NumClusters;
10315 }
10316 }
10317 Clusters.resize(DstIndex);
10318}
10319
10320void SelectionDAGBuilder::lowerWorkItem(SwitchWorkListItem W, Value *Cond,
10321 MachineBasicBlock *SwitchMBB,
10322 MachineBasicBlock *DefaultMBB) {
10323 MachineFunction *CurMF = FuncInfo.MF;
10324 MachineBasicBlock *NextMBB = nullptr;
10325 MachineFunction::iterator BBI(W.MBB);
10326 if (++BBI != FuncInfo.MF->end())
10327 NextMBB = &*BBI;
10328
10329 unsigned Size = W.LastCluster - W.FirstCluster + 1;
10330
10331 BranchProbabilityInfo *BPI = FuncInfo.BPI;
10332
10333 if (Size == 2 && W.MBB == SwitchMBB) {
10334 // If any two of the cases has the same destination, and if one value
10335 // is the same as the other, but has one bit unset that the other has set,
10336 // use bit manipulation to do two compares at once. For example:
10337 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
10338 // TODO: This could be extended to merge any 2 cases in switches with 3
10339 // cases.
10340 // TODO: Handle cases where W.CaseBB != SwitchBB.
10341 CaseCluster &Small = *W.FirstCluster;
10342 CaseCluster &Big = *W.LastCluster;
10343
10344 if (Small.Low == Small.High && Big.Low == Big.High &&
10345 Small.MBB == Big.MBB) {
10346 const APInt &SmallValue = Small.Low->getValue();
10347 const APInt &BigValue = Big.Low->getValue();
10348
10349 // Check that there is only one bit different.
10350 APInt CommonBit = BigValue ^ SmallValue;
10351 if (CommonBit.isPowerOf2()) {
10352 SDValue CondLHS = getValue(Cond);
10353 EVT VT = CondLHS.getValueType();
10354 SDLoc DL = getCurSDLoc();
10355
10356 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS,
10357 DAG.getConstant(CommonBit, DL, VT));
10358 SDValue Cond = DAG.getSetCC(
10359 DL, MVT::i1, Or, DAG.getConstant(BigValue | SmallValue, DL, VT),
10360 ISD::SETEQ);
10361
10362 // Update successor info.
10363 // Both Small and Big will jump to Small.BB, so we sum up the
10364 // probabilities.
10365 addSuccessorWithProb(SwitchMBB, Small.MBB, Small.Prob + Big.Prob);
10366 if (BPI)
10367 addSuccessorWithProb(
10368 SwitchMBB, DefaultMBB,
10369 // The default destination is the first successor in IR.
10370 BPI->getEdgeProbability(SwitchMBB->getBasicBlock(), (unsigned)0));
10371 else
10372 addSuccessorWithProb(SwitchMBB, DefaultMBB);
10373
10374 // Insert the true branch.
10375 SDValue BrCond =
10376 DAG.getNode(ISD::BRCOND, DL, MVT::Other, getControlRoot(), Cond,
10377 DAG.getBasicBlock(Small.MBB));
10378 // Insert the false branch.
10379 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond,
10380 DAG.getBasicBlock(DefaultMBB));
10381
10382 DAG.setRoot(BrCond);
10383 return;
10384 }
10385 }
10386 }
10387
10388 if (TM.getOptLevel() != CodeGenOpt::None) {
10389 // Here, we order cases by probability so the most likely case will be
10390 // checked first. However, two clusters can have the same probability in
10391 // which case their relative ordering is non-deterministic. So we use Low
10392 // as a tie-breaker as clusters are guaranteed to never overlap.
10393 llvm::sort(W.FirstCluster, W.LastCluster + 1,
10394 [](const CaseCluster &a, const CaseCluster &b) {
10395 return a.Prob != b.Prob ?
10396 a.Prob > b.Prob :
10397 a.Low->getValue().slt(b.Low->getValue());
10398 });
10399
10400 // Rearrange the case blocks so that the last one falls through if possible
10401 // without changing the order of probabilities.
10402 for (CaseClusterIt I = W.LastCluster; I > W.FirstCluster; ) {
10403 --I;
10404 if (I->Prob > W.LastCluster->Prob)
10405 break;
10406 if (I->Kind == CC_Range && I->MBB == NextMBB) {
10407 std::swap(*I, *W.LastCluster);
10408 break;
10409 }
10410 }
10411 }
10412
10413 // Compute total probability.
10414 BranchProbability DefaultProb = W.DefaultProb;
10415 BranchProbability UnhandledProbs = DefaultProb;
10416 for (CaseClusterIt I = W.FirstCluster; I <= W.LastCluster; ++I)
10417 UnhandledProbs += I->Prob;
10418
10419 MachineBasicBlock *CurMBB = W.MBB;
10420 for (CaseClusterIt I = W.FirstCluster, E = W.LastCluster; I <= E; ++I) {
10421 bool FallthroughUnreachable = false;
10422 MachineBasicBlock *Fallthrough;
10423 if (I == W.LastCluster) {
10424 // For the last cluster, fall through to the default destination.
10425 Fallthrough = DefaultMBB;
10426 FallthroughUnreachable = isa<UnreachableInst>(
10427 DefaultMBB->getBasicBlock()->getFirstNonPHIOrDbg());
10428 } else {
10429 Fallthrough = CurMF->CreateMachineBasicBlock(CurMBB->getBasicBlock());
10430 CurMF->insert(BBI, Fallthrough);
10431 // Put Cond in a virtual register to make it available from the new blocks.
10432 ExportFromCurrentBlock(Cond);
10433 }
10434 UnhandledProbs -= I->Prob;
10435
10436 switch (I->Kind) {
10437 case CC_JumpTable: {
10438 // FIXME: Optimize away range check based on pivot comparisons.
10439 JumpTableHeader *JTH = &JTCases[I->JTCasesIndex].first;
10440 JumpTable *JT = &JTCases[I->JTCasesIndex].second;
10441
10442 // The jump block hasn't been inserted yet; insert it here.
10443 MachineBasicBlock *JumpMBB = JT->MBB;
10444 CurMF->insert(BBI, JumpMBB);
10445
10446 auto JumpProb = I->Prob;
10447 auto FallthroughProb = UnhandledProbs;
10448
10449 // If the default statement is a target of the jump table, we evenly
10450 // distribute the default probability to successors of CurMBB. Also
10451 // update the probability on the edge from JumpMBB to Fallthrough.
10452 for (MachineBasicBlock::succ_iterator SI = JumpMBB->succ_begin(),
10453 SE = JumpMBB->succ_end();
10454 SI != SE; ++SI) {
10455 if (*SI == DefaultMBB) {
10456 JumpProb += DefaultProb / 2;
10457 FallthroughProb -= DefaultProb / 2;
10458 JumpMBB->setSuccProbability(SI, DefaultProb / 2);
10459 JumpMBB->normalizeSuccProbs();
10460 break;
10461 }
10462 }
10463
10464 if (FallthroughUnreachable) {
10465 // Skip the range check if the fallthrough block is unreachable.
10466 JTH->OmitRangeCheck = true;
10467 }
10468
10469 if (!JTH->OmitRangeCheck)
10470 addSuccessorWithProb(CurMBB, Fallthrough, FallthroughProb);
10471 addSuccessorWithProb(CurMBB, JumpMBB, JumpProb);
10472 CurMBB->normalizeSuccProbs();
10473
10474 // The jump table header will be inserted in our current block, do the
10475 // range check, and fall through to our fallthrough block.
10476 JTH->HeaderBB = CurMBB;
10477 JT->Default = Fallthrough; // FIXME: Move Default to JumpTableHeader.
10478
10479 // If we're in the right place, emit the jump table header right now.
10480 if (CurMBB == SwitchMBB) {
10481 visitJumpTableHeader(*JT, *JTH, SwitchMBB);
10482 JTH->Emitted = true;
10483 }
10484 break;
10485 }
10486 case CC_BitTests: {
10487 // FIXME: If Fallthrough is unreachable, skip the range check.
10488
10489 // FIXME: Optimize away range check based on pivot comparisons.
10490 BitTestBlock *BTB = &BitTestCases[I->BTCasesIndex];
10491
10492 // The bit test blocks haven't been inserted yet; insert them here.
10493 for (BitTestCase &BTC : BTB->Cases)
10494 CurMF->insert(BBI, BTC.ThisBB);
10495
10496 // Fill in fields of the BitTestBlock.
10497 BTB->Parent = CurMBB;
10498 BTB->Default = Fallthrough;
10499
10500 BTB->DefaultProb = UnhandledProbs;
10501 // If the cases in bit test don't form a contiguous range, we evenly
10502 // distribute the probability on the edge to Fallthrough to two
10503 // successors of CurMBB.
10504 if (!BTB->ContiguousRange) {
10505 BTB->Prob += DefaultProb / 2;
10506 BTB->DefaultProb -= DefaultProb / 2;
10507 }
10508
10509 // If we're in the right place, emit the bit test header right now.
10510 if (CurMBB == SwitchMBB) {
10511 visitBitTestHeader(*BTB, SwitchMBB);
10512 BTB->Emitted = true;
10513 }
10514 break;
10515 }
10516 case CC_Range: {
10517 const Value *RHS, *LHS, *MHS;
10518 ISD::CondCode CC;
10519 if (I->Low == I->High) {
10520 // Check Cond == I->Low.
10521 CC = ISD::SETEQ;
10522 LHS = Cond;
10523 RHS=I->Low;
10524 MHS = nullptr;
10525 } else {
10526 // Check I->Low <= Cond <= I->High.
10527 CC = ISD::SETLE;
10528 LHS = I->Low;
10529 MHS = Cond;
10530 RHS = I->High;
10531 }
10532
10533 // If Fallthrough is unreachable, fold away the comparison.
10534 if (FallthroughUnreachable)
10535 CC = ISD::SETTRUE;
10536
10537 // The false probability is the sum of all unhandled cases.
10538 CaseBlock CB(CC, LHS, RHS, MHS, I->MBB, Fallthrough, CurMBB,
10539 getCurSDLoc(), I->Prob, UnhandledProbs);
10540
10541 if (CurMBB == SwitchMBB)
10542 visitSwitchCase(CB, SwitchMBB);
10543 else
10544 SwitchCases.push_back(CB);
10545
10546 break;
10547 }
10548 }
10549 CurMBB = Fallthrough;
10550 }
10551}
10552
10553unsigned SelectionDAGBuilder::caseClusterRank(const CaseCluster &CC,
10554 CaseClusterIt First,
10555 CaseClusterIt Last) {
10556 return std::count_if(First, Last + 1, [&](const CaseCluster &X) {
10557 if (X.Prob != CC.Prob)
10558 return X.Prob > CC.Prob;
10559
10560 // Ties are broken by comparing the case value.
10561 return X.Low->getValue().slt(CC.Low->getValue());
10562 });
10563}
10564
10565void SelectionDAGBuilder::splitWorkItem(SwitchWorkList &WorkList,
10566 const SwitchWorkListItem &W,
10567 Value *Cond,
10568 MachineBasicBlock *SwitchMBB) {
10569 assert(W.FirstCluster->Low->getValue().slt(W.LastCluster->Low->getValue()) &&((W.FirstCluster->Low->getValue().slt(W.LastCluster->
Low->getValue()) && "Clusters not sorted?") ? static_cast
<void> (0) : __assert_fail ("W.FirstCluster->Low->getValue().slt(W.LastCluster->Low->getValue()) && \"Clusters not sorted?\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 10570, __PRETTY_FUNCTION__))
10570 "Clusters not sorted?")((W.FirstCluster->Low->getValue().slt(W.LastCluster->
Low->getValue()) && "Clusters not sorted?") ? static_cast
<void> (0) : __assert_fail ("W.FirstCluster->Low->getValue().slt(W.LastCluster->Low->getValue()) && \"Clusters not sorted?\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 10570, __PRETTY_FUNCTION__))
;
10571
10572 assert(W.LastCluster - W.FirstCluster + 1 >= 2 && "Too small to split!")((W.LastCluster - W.FirstCluster + 1 >= 2 && "Too small to split!"
) ? static_cast<void> (0) : __assert_fail ("W.LastCluster - W.FirstCluster + 1 >= 2 && \"Too small to split!\""
, "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 10572, __PRETTY_FUNCTION__))
;
10573
10574 // Balance the tree based on branch probabilities to create a near-optimal (in
10575 // terms of search time given key frequency) binary search tree. See e.g. Kurt
10576 // Mehlhorn "Nearly Optimal Binary Search Trees" (1975).
10577 CaseClusterIt LastLeft = W.FirstCluster;
10578 CaseClusterIt FirstRight = W.LastCluster;
10579 auto LeftProb = LastLeft->Prob + W.DefaultProb / 2;
10580 auto RightProb = FirstRight->Prob + W.DefaultProb / 2;
10581
10582 // Move LastLeft and FirstRight towards each other from opposite directions to
10583 // find a partitioning of the clusters which balances the probability on both
10584 // sides. If LeftProb and RightProb are equal, alternate which side is
10585 // taken to ensure 0-probability nodes are distributed evenly.
10586 unsigned I = 0;
10587 while (LastLeft + 1 < FirstRight) {
10588 if (LeftProb < RightProb || (LeftProb == RightProb && (I & 1)))
10589 LeftProb += (++LastLeft)->Prob;
10590 else
10591 RightProb += (--FirstRight)->Prob;
10592 I++;
10593 }
10594
10595 while (true) {
10596 // Our binary search tree differs from a typical BST in that ours can have up
10597 // to three values in each leaf. The pivot selection above doesn't take that
10598 // into account, which means the tree might require more nodes and be less
10599 // efficient. We compensate for this here.
10600
10601 unsigned NumLeft = LastLeft - W.FirstCluster + 1;
10602 unsigned NumRight = W.LastCluster - FirstRight + 1;
10603
10604 if (std::min(NumLeft, NumRight) < 3 && std::max(NumLeft, NumRight) > 3) {
10605 // If one side has less than 3 clusters, and the other has more than 3,
10606 // consider taking a cluster from the other side.
10607
10608 if (NumLeft < NumRight) {
10609 // Consider moving the first cluster on the right to the left side.
10610 CaseCluster &CC = *FirstRight;
10611 unsigned RightSideRank = caseClusterRank(CC, FirstRight, W.LastCluster);
10612 unsigned LeftSideRank = caseClusterRank(CC, W.FirstCluster, LastLeft);
10613 if (LeftSideRank <= RightSideRank) {
10614 // Moving the cluster to the left does not demote it.
10615 ++LastLeft;
10616 ++FirstRight;
10617 continue;
10618 }
10619 } else {
10620 assert(NumRight < NumLeft)((NumRight < NumLeft) ? static_cast<void> (0) : __assert_fail
("NumRight < NumLeft", "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 10620, __PRETTY_FUNCTION__))
;
10621 // Consider moving the last element on the left to the right side.
10622 CaseCluster &CC = *LastLeft;
10623 unsigned LeftSideRank = caseClusterRank(CC, W.FirstCluster, LastLeft);
10624 unsigned RightSideRank = caseClusterRank(CC, FirstRight, W.LastCluster);
10625 if (RightSideRank <= LeftSideRank) {
10626 // Moving the cluster to the right does not demot it.
10627 --LastLeft;
10628 --FirstRight;
10629 continue;
10630 }
10631 }
10632 }
10633 break;
10634 }
10635
10636 assert(LastLeft + 1 == FirstRight)((LastLeft + 1 == FirstRight) ? static_cast<void> (0) :
__assert_fail ("LastLeft + 1 == FirstRight", "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 10636, __PRETTY_FUNCTION__))
;
10637 assert(LastLeft >= W.FirstCluster)((LastLeft >= W.FirstCluster) ? static_cast<void> (0
) : __assert_fail ("LastLeft >= W.FirstCluster", "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 10637, __PRETTY_FUNCTION__))
;
10638 assert(FirstRight <= W.LastCluster)((FirstRight <= W.LastCluster) ? static_cast<void> (
0) : __assert_fail ("FirstRight <= W.LastCluster", "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 10638, __PRETTY_FUNCTION__))
;
10639
10640 // Use the first element on the right as pivot since we will make less-than
10641 // comparisons against it.
10642 CaseClusterIt PivotCluster = FirstRight;
10643 assert(PivotCluster > W.FirstCluster)((PivotCluster > W.FirstCluster) ? static_cast<void>
(0) : __assert_fail ("PivotCluster > W.FirstCluster", "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 10643, __PRETTY_FUNCTION__))
;
10644 assert(PivotCluster <= W.LastCluster)((PivotCluster <= W.LastCluster) ? static_cast<void>
(0) : __assert_fail ("PivotCluster <= W.LastCluster", "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 10644, __PRETTY_FUNCTION__))
;
10645
10646 CaseClusterIt FirstLeft = W.FirstCluster;
10647 CaseClusterIt LastRight = W.LastCluster;
10648
10649 const ConstantInt *Pivot = PivotCluster->Low;
10650
10651 // New blocks will be inserted immediately after the current one.
10652 MachineFunction::iterator BBI(W.MBB);
10653 ++BBI;
10654
10655 // We will branch to the LHS if Value < Pivot. If LHS is a single cluster,
10656 // we can branch to its destination directly if it's squeezed exactly in
10657 // between the known lower bound and Pivot - 1.
10658 MachineBasicBlock *LeftMBB;
10659 if (FirstLeft == LastLeft && FirstLeft->Kind == CC_Range &&
10660 FirstLeft->Low == W.GE &&
10661 (FirstLeft->High->getValue() + 1LL) == Pivot->getValue()) {
10662 LeftMBB = FirstLeft->MBB;
10663 } else {
10664 LeftMBB = FuncInfo.MF->CreateMachineBasicBlock(W.MBB->getBasicBlock());
10665 FuncInfo.MF->insert(BBI, LeftMBB);
10666 WorkList.push_back(
10667 {LeftMBB, FirstLeft, LastLeft, W.GE, Pivot, W.DefaultProb / 2});
10668 // Put Cond in a virtual register to make it available from the new blocks.
10669 ExportFromCurrentBlock(Cond);
10670 }
10671
10672 // Similarly, we will branch to the RHS if Value >= Pivot. If RHS is a
10673 // single cluster, RHS.Low == Pivot, and we can branch to its destination
10674 // directly if RHS.High equals the current upper bound.
10675 MachineBasicBlock *RightMBB;
10676 if (FirstRight == LastRight && FirstRight->Kind == CC_Range &&
10677 W.LT && (FirstRight->High->getValue() + 1ULL) == W.LT->getValue()) {
10678 RightMBB = FirstRight->MBB;
10679 } else {
10680 RightMBB = FuncInfo.MF->CreateMachineBasicBlock(W.MBB->getBasicBlock());
10681 FuncInfo.MF->insert(BBI, RightMBB);
10682 WorkList.push_back(
10683 {RightMBB, FirstRight, LastRight, Pivot, W.LT, W.DefaultProb / 2});
10684 // Put Cond in a virtual register to make it available from the new blocks.
10685 ExportFromCurrentBlock(Cond);
10686 }
10687
10688 // Create the CaseBlock record that will be used to lower the branch.
10689 CaseBlock CB(ISD::SETLT, Cond, Pivot, nullptr, LeftMBB, RightMBB, W.MBB,
10690 getCurSDLoc(), LeftProb, RightProb);
10691
10692 if (W.MBB == SwitchMBB)
10693 visitSwitchCase(CB, SwitchMBB);
10694 else
10695 SwitchCases.push_back(CB);
10696}
10697
10698// Scale CaseProb after peeling a case with the probablity of PeeledCaseProb
10699// from the swith statement.
10700static BranchProbability scaleCaseProbality(BranchProbability CaseProb,
10701 BranchProbability PeeledCaseProb) {
10702 if (PeeledCaseProb == BranchProbability::getOne())
10703 return BranchProbability::getZero();
10704 BranchProbability SwitchProb = PeeledCaseProb.getCompl();
10705
10706 uint32_t Numerator = CaseProb.getNumerator();
10707 uint32_t Denominator = SwitchProb.scale(CaseProb.getDenominator());
10708 return BranchProbability(Numerator, std::max(Numerator, Denominator));
10709}
10710
10711// Try to peel the top probability case if it exceeds the threshold.
10712// Return current MachineBasicBlock for the switch statement if the peeling
10713// does not occur.
10714// If the peeling is performed, return the newly created MachineBasicBlock
10715// for the peeled switch statement. Also update Clusters to remove the peeled
10716// case. PeeledCaseProb is the BranchProbability for the peeled case.
10717MachineBasicBlock *SelectionDAGBuilder::peelDominantCaseCluster(
10718 const SwitchInst &SI, CaseClusterVector &Clusters,
10719 BranchProbability &PeeledCaseProb) {
10720 MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
10721 // Don't perform if there is only one cluster or optimizing for size.
10722 if (SwitchPeelThreshold > 100 || !FuncInfo.BPI || Clusters.size() < 2 ||
10723 TM.getOptLevel() == CodeGenOpt::None ||
10724 SwitchMBB->getParent()->getFunction().hasMinSize())
10725 return SwitchMBB;
10726
10727 BranchProbability TopCaseProb = BranchProbability(SwitchPeelThreshold, 100);
10728 unsigned PeeledCaseIndex = 0;
10729 bool SwitchPeeled = false;
10730 for (unsigned Index = 0; Index < Clusters.size(); ++Index) {
10731 CaseCluster &CC = Clusters[Index];
10732 if (CC.Prob < TopCaseProb)
10733 continue;
10734 TopCaseProb = CC.Prob;
10735 PeeledCaseIndex = Index;
10736 SwitchPeeled = true;
10737 }
10738 if (!SwitchPeeled)
10739 return SwitchMBB;
10740
10741 LLVM_DEBUG(dbgs() << "Peeled one top case in switch stmt, prob: "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << "Peeled one top case in switch stmt, prob: "
<< TopCaseProb << "\n"; } } while (false)
10742 << TopCaseProb << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << "Peeled one top case in switch stmt, prob: "
<< TopCaseProb << "\n"; } } while (false)
;
10743
10744 // Record the MBB for the peeled switch statement.
10745 MachineFunction::iterator BBI(SwitchMBB);
10746 ++BBI;
10747 MachineBasicBlock *PeeledSwitchMBB =
10748 FuncInfo.MF->CreateMachineBasicBlock(SwitchMBB->getBasicBlock());
10749 FuncInfo.MF->insert(BBI, PeeledSwitchMBB);
10750
10751 ExportFromCurrentBlock(SI.getCondition());
10752 auto PeeledCaseIt = Clusters.begin() + PeeledCaseIndex;
10753 SwitchWorkListItem W = {SwitchMBB, PeeledCaseIt, PeeledCaseIt,
10754 nullptr, nullptr, TopCaseProb.getCompl()};
10755 lowerWorkItem(W, SI.getCondition(), SwitchMBB, PeeledSwitchMBB);
10756
10757 Clusters.erase(PeeledCaseIt);
10758 for (CaseCluster &CC : Clusters) {
10759 LLVM_DEBUG(do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << "Scale the probablity for one cluster, before scaling: "
<< CC.Prob << "\n"; } } while (false)
10760 dbgs() << "Scale the probablity for one cluster, before scaling: "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << "Scale the probablity for one cluster, before scaling: "
<< CC.Prob << "\n"; } } while (false)
10761 << CC.Prob << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << "Scale the probablity for one cluster, before scaling: "
<< CC.Prob << "\n"; } } while (false)
;
10762 CC.Prob = scaleCaseProbality(CC.Prob, TopCaseProb);
10763 LLVM_DEBUG(dbgs() << "After scaling: " << CC.Prob << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << "After scaling: " << CC.Prob
<< "\n"; } } while (false)
;
10764 }
10765 PeeledCaseProb = TopCaseProb;
10766 return PeeledSwitchMBB;
10767}
10768
10769void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
10770 // Extract cases from the switch.
10771 BranchProbabilityInfo *BPI = FuncInfo.BPI;
10772 CaseClusterVector Clusters;
10773 Clusters.reserve(SI.getNumCases());
10774 for (auto I : SI.cases()) {
10775 MachineBasicBlock *Succ = FuncInfo.MBBMap[I.getCaseSuccessor()];
10776 const ConstantInt *CaseVal = I.getCaseValue();
10777 BranchProbability Prob =
10778 BPI ? BPI->getEdgeProbability(SI.getParent(), I.getSuccessorIndex())
10779 : BranchProbability(1, SI.getNumCases() + 1);
10780 Clusters.push_back(CaseCluster::range(CaseVal, CaseVal, Succ, Prob));
10781 }
10782
10783 MachineBasicBlock *DefaultMBB = FuncInfo.MBBMap[SI.getDefaultDest()];
10784
10785 // Cluster adjacent cases with the same destination. We do this at all
10786 // optimization levels because it's cheap to do and will make codegen faster
10787 // if there are many clusters.
10788 sortAndRangeify(Clusters);
10789
10790 // The branch probablity of the peeled case.
10791 BranchProbability PeeledCaseProb = BranchProbability::getZero();
10792 MachineBasicBlock *PeeledSwitchMBB =
10793 peelDominantCaseCluster(SI, Clusters, PeeledCaseProb);
10794
10795 // If there is only the default destination, jump there directly.
10796 MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
10797 if (Clusters.empty()) {
10798 assert(PeeledSwitchMBB == SwitchMBB)((PeeledSwitchMBB == SwitchMBB) ? static_cast<void> (0)
: __assert_fail ("PeeledSwitchMBB == SwitchMBB", "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 10798, __PRETTY_FUNCTION__))
;
10799 SwitchMBB->addSuccessor(DefaultMBB);
10800 if (DefaultMBB != NextBlock(SwitchMBB)) {
10801 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other,
10802 getControlRoot(), DAG.getBasicBlock(DefaultMBB)));
10803 }
10804 return;
10805 }
10806
10807 findJumpTables(Clusters, &SI, DefaultMBB);
10808 findBitTestClusters(Clusters, &SI);
10809
10810 LLVM_DEBUG({do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { { dbgs() << "Case clusters: "; for (const CaseCluster
&C : Clusters) { if (C.Kind == CC_JumpTable) dbgs() <<
"JT:"; if (C.Kind == CC_BitTests) dbgs() << "BT:"; C.Low
->getValue().print(dbgs(), true); if (C.Low != C.High) { dbgs
() << '-'; C.High->getValue().print(dbgs(), true); }
dbgs() << ' '; } dbgs() << '\n'; }; } } while (false
)
10811 dbgs() << "Case clusters: ";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { { dbgs() << "Case clusters: "; for (const CaseCluster
&C : Clusters) { if (C.Kind == CC_JumpTable) dbgs() <<
"JT:"; if (C.Kind == CC_BitTests) dbgs() << "BT:"; C.Low
->getValue().print(dbgs(), true); if (C.Low != C.High) { dbgs
() << '-'; C.High->getValue().print(dbgs(), true); }
dbgs() << ' '; } dbgs() << '\n'; }; } } while (false
)
10812 for (const CaseCluster &C : Clusters) {do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { { dbgs() << "Case clusters: "; for (const CaseCluster
&C : Clusters) { if (C.Kind == CC_JumpTable) dbgs() <<
"JT:"; if (C.Kind == CC_BitTests) dbgs() << "BT:"; C.Low
->getValue().print(dbgs(), true); if (C.Low != C.High) { dbgs
() << '-'; C.High->getValue().print(dbgs(), true); }
dbgs() << ' '; } dbgs() << '\n'; }; } } while (false
)
10813 if (C.Kind == CC_JumpTable)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { { dbgs() << "Case clusters: "; for (const CaseCluster
&C : Clusters) { if (C.Kind == CC_JumpTable) dbgs() <<
"JT:"; if (C.Kind == CC_BitTests) dbgs() << "BT:"; C.Low
->getValue().print(dbgs(), true); if (C.Low != C.High) { dbgs
() << '-'; C.High->getValue().print(dbgs(), true); }
dbgs() << ' '; } dbgs() << '\n'; }; } } while (false
)
10814 dbgs() << "JT:";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { { dbgs() << "Case clusters: "; for (const CaseCluster
&C : Clusters) { if (C.Kind == CC_JumpTable) dbgs() <<
"JT:"; if (C.Kind == CC_BitTests) dbgs() << "BT:"; C.Low
->getValue().print(dbgs(), true); if (C.Low != C.High) { dbgs
() << '-'; C.High->getValue().print(dbgs(), true); }
dbgs() << ' '; } dbgs() << '\n'; }; } } while (false
)
10815 if (C.Kind == CC_BitTests)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { { dbgs() << "Case clusters: "; for (const CaseCluster
&C : Clusters) { if (C.Kind == CC_JumpTable) dbgs() <<
"JT:"; if (C.Kind == CC_BitTests) dbgs() << "BT:"; C.Low
->getValue().print(dbgs(), true); if (C.Low != C.High) { dbgs
() << '-'; C.High->getValue().print(dbgs(), true); }
dbgs() << ' '; } dbgs() << '\n'; }; } } while (false
)
10816 dbgs() << "BT:";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { { dbgs() << "Case clusters: "; for (const CaseCluster
&C : Clusters) { if (C.Kind == CC_JumpTable) dbgs() <<
"JT:"; if (C.Kind == CC_BitTests) dbgs() << "BT:"; C.Low
->getValue().print(dbgs(), true); if (C.Low != C.High) { dbgs
() << '-'; C.High->getValue().print(dbgs(), true); }
dbgs() << ' '; } dbgs() << '\n'; }; } } while (false
)
10817
10818 C.Low->getValue().print(dbgs(), true);do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { { dbgs() << "Case clusters: "; for (const CaseCluster
&C : Clusters) { if (C.Kind == CC_JumpTable) dbgs() <<
"JT:"; if (C.Kind == CC_BitTests) dbgs() << "BT:"; C.Low
->getValue().print(dbgs(), true); if (C.Low != C.High) { dbgs
() << '-'; C.High->getValue().print(dbgs(), true); }
dbgs() << ' '; } dbgs() << '\n'; }; } } while (false
)
10819 if (C.Low != C.High) {do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { { dbgs() << "Case clusters: "; for (const CaseCluster
&C : Clusters) { if (C.Kind == CC_JumpTable) dbgs() <<
"JT:"; if (C.Kind == CC_BitTests) dbgs() << "BT:"; C.Low
->getValue().print(dbgs(), true); if (C.Low != C.High) { dbgs
() << '-'; C.High->getValue().print(dbgs(), true); }
dbgs() << ' '; } dbgs() << '\n'; }; } } while (false
)
10820 dbgs() << '-';do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { { dbgs() << "Case clusters: "; for (const CaseCluster
&C : Clusters) { if (C.Kind == CC_JumpTable) dbgs() <<
"JT:"; if (C.Kind == CC_BitTests) dbgs() << "BT:"; C.Low
->getValue().print(dbgs(), true); if (C.Low != C.High) { dbgs
() << '-'; C.High->getValue().print(dbgs(), true); }
dbgs() << ' '; } dbgs() << '\n'; }; } } while (false
)
10821 C.High->getValue().print(dbgs(), true);do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { { dbgs() << "Case clusters: "; for (const CaseCluster
&C : Clusters) { if (C.Kind == CC_JumpTable) dbgs() <<
"JT:"; if (C.Kind == CC_BitTests) dbgs() << "BT:"; C.Low
->getValue().print(dbgs(), true); if (C.Low != C.High) { dbgs
() << '-'; C.High->getValue().print(dbgs(), true); }
dbgs() << ' '; } dbgs() << '\n'; }; } } while (false
)
10822 }do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { { dbgs() << "Case clusters: "; for (const CaseCluster
&C : Clusters) { if (C.Kind == CC_JumpTable) dbgs() <<
"JT:"; if (C.Kind == CC_BitTests) dbgs() << "BT:"; C.Low
->getValue().print(dbgs(), true); if (C.Low != C.High) { dbgs
() << '-'; C.High->getValue().print(dbgs(), true); }
dbgs() << ' '; } dbgs() << '\n'; }; } } while (false
)
10823 dbgs() << ' ';do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { { dbgs() << "Case clusters: "; for (const CaseCluster
&C : Clusters) { if (C.Kind == CC_JumpTable) dbgs() <<
"JT:"; if (C.Kind == CC_BitTests) dbgs() << "BT:"; C.Low
->getValue().print(dbgs(), true); if (C.Low != C.High) { dbgs
() << '-'; C.High->getValue().print(dbgs(), true); }
dbgs() << ' '; } dbgs() << '\n'; }; } } while (false
)
10824 }do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { { dbgs() << "Case clusters: "; for (const CaseCluster
&C : Clusters) { if (C.Kind == CC_JumpTable) dbgs() <<
"JT:"; if (C.Kind == CC_BitTests) dbgs() << "BT:"; C.Low
->getValue().print(dbgs(), true); if (C.Low != C.High) { dbgs
() << '-'; C.High->getValue().print(dbgs(), true); }
dbgs() << ' '; } dbgs() << '\n'; }; } } while (false
)
10825 dbgs() << '\n';do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { { dbgs() << "Case clusters: "; for (const CaseCluster
&C : Clusters) { if (C.Kind == CC_JumpTable) dbgs() <<
"JT:"; if (C.Kind == CC_BitTests) dbgs() << "BT:"; C.Low
->getValue().print(dbgs(), true); if (C.Low != C.High) { dbgs
() << '-'; C.High->getValue().print(dbgs(), true); }
dbgs() << ' '; } dbgs() << '\n'; }; } } while (false
)
10826 })do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { { dbgs() << "Case clusters: "; for (const CaseCluster
&C : Clusters) { if (C.Kind == CC_JumpTable) dbgs() <<
"JT:"; if (C.Kind == CC_BitTests) dbgs() << "BT:"; C.Low
->getValue().print(dbgs(), true); if (C.Low != C.High) { dbgs
() << '-'; C.High->getValue().print(dbgs(), true); }
dbgs() << ' '; } dbgs() << '\n'; }; } } while (false
)
;
10827
10828 assert(!Clusters.empty())((!Clusters.empty()) ? static_cast<void> (0) : __assert_fail
("!Clusters.empty()", "/build/llvm-toolchain-snapshot-9~svn359999/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 10828, __PRETTY_FUNCTION__))
;
10829 SwitchWorkList WorkList;
10830 CaseClusterIt First = Clusters.begin();
10831 CaseClusterIt Last = Clusters.end() - 1;
10832 auto DefaultProb = getEdgeProbability(PeeledSwitchMBB, DefaultMBB);
10833 // Scale the branchprobability for DefaultMBB if the peel occurs and
10834 // DefaultMBB is not replaced.
10835 if (PeeledCaseProb != BranchProbability::getZero() &&
10836 DefaultMBB == FuncInfo.MBBMap[SI.getDefaultDest()])
10837 DefaultProb = scaleCaseProbality(DefaultProb, PeeledCaseProb);
10838 WorkList.push_back(
10839 {PeeledSwitchMBB, First, Last, nullptr, nullptr, DefaultProb});
10840
10841 while (!WorkList.empty()) {
10842 SwitchWorkListItem W = WorkList.back();
10843 WorkList.pop_back();
10844 unsigned NumClusters = W.LastCluster - W.FirstCluster + 1;
10845
10846 if (NumClusters > 3 && TM.getOptLevel() != CodeGenOpt::None &&
10847 !DefaultMBB->getParent()->getFunction().hasMinSize()) {
10848 // For optimized builds, lower large range as a balanced binary tree.
10849 splitWorkItem(WorkList, W, SI.getCondition(), SwitchMBB);
10850 continue;
10851 }
10852
10853 lowerWorkItem(W, SI.getCondition(), SwitchMBB, DefaultMBB);
10854 }
10855}