Bug Summary

File:llvm/include/llvm/CodeGen/SelectionDAGNodes.h
Warning:line 1102, column 10
Called C++ object pointer is null

Annotated Source Code

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clang -cc1 -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name SelectionDAGBuilder.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mframe-pointer=none -fmath-errno -fno-rounding-math -mconstructor-aliases -munwind-tables -target-cpu x86-64 -tune-cpu generic -fno-split-dwarf-inlining -debugger-tuning=gdb -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-12/lib/clang/12.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/build-llvm/lib/CodeGen/SelectionDAG -I /build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG -I /build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/build-llvm/include -I /build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0/backward -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-12/lib/clang/12.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++14 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/build-llvm/lib/CodeGen/SelectionDAG -fdebug-prefix-map=/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d=. -ferror-limit 19 -fvisibility-inlines-hidden -stack-protector 2 -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -o /tmp/scan-build-2020-11-29-190409-37574-1 -x c++ /build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

1//===- SelectionDAGBuilder.cpp - Selection-DAG building -------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This implements routines for translating from LLVM IR into SelectionDAG IR.
10//
11//===----------------------------------------------------------------------===//
12
13#include "SelectionDAGBuilder.h"
14#include "SDNodeDbgValue.h"
15#include "llvm/ADT/APFloat.h"
16#include "llvm/ADT/APInt.h"
17#include "llvm/ADT/BitVector.h"
18#include "llvm/ADT/None.h"
19#include "llvm/ADT/Optional.h"
20#include "llvm/ADT/STLExtras.h"
21#include "llvm/ADT/SmallPtrSet.h"
22#include "llvm/ADT/SmallSet.h"
23#include "llvm/ADT/StringRef.h"
24#include "llvm/ADT/Triple.h"
25#include "llvm/ADT/Twine.h"
26#include "llvm/Analysis/AliasAnalysis.h"
27#include "llvm/Analysis/BlockFrequencyInfo.h"
28#include "llvm/Analysis/BranchProbabilityInfo.h"
29#include "llvm/Analysis/ConstantFolding.h"
30#include "llvm/Analysis/EHPersonalities.h"
31#include "llvm/Analysis/Loads.h"
32#include "llvm/Analysis/MemoryLocation.h"
33#include "llvm/Analysis/ProfileSummaryInfo.h"
34#include "llvm/Analysis/TargetLibraryInfo.h"
35#include "llvm/Analysis/ValueTracking.h"
36#include "llvm/Analysis/VectorUtils.h"
37#include "llvm/CodeGen/Analysis.h"
38#include "llvm/CodeGen/FunctionLoweringInfo.h"
39#include "llvm/CodeGen/GCMetadata.h"
40#include "llvm/CodeGen/MachineBasicBlock.h"
41#include "llvm/CodeGen/MachineFrameInfo.h"
42#include "llvm/CodeGen/MachineFunction.h"
43#include "llvm/CodeGen/MachineInstr.h"
44#include "llvm/CodeGen/MachineInstrBuilder.h"
45#include "llvm/CodeGen/MachineJumpTableInfo.h"
46#include "llvm/CodeGen/MachineMemOperand.h"
47#include "llvm/CodeGen/MachineModuleInfo.h"
48#include "llvm/CodeGen/MachineOperand.h"
49#include "llvm/CodeGen/MachineRegisterInfo.h"
50#include "llvm/CodeGen/RuntimeLibcalls.h"
51#include "llvm/CodeGen/SelectionDAG.h"
52#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
53#include "llvm/CodeGen/StackMaps.h"
54#include "llvm/CodeGen/SwiftErrorValueTracking.h"
55#include "llvm/CodeGen/TargetFrameLowering.h"
56#include "llvm/CodeGen/TargetInstrInfo.h"
57#include "llvm/CodeGen/TargetOpcodes.h"
58#include "llvm/CodeGen/TargetRegisterInfo.h"
59#include "llvm/CodeGen/TargetSubtargetInfo.h"
60#include "llvm/CodeGen/WinEHFuncInfo.h"
61#include "llvm/IR/Argument.h"
62#include "llvm/IR/Attributes.h"
63#include "llvm/IR/BasicBlock.h"
64#include "llvm/IR/CFG.h"
65#include "llvm/IR/CallingConv.h"
66#include "llvm/IR/Constant.h"
67#include "llvm/IR/ConstantRange.h"
68#include "llvm/IR/Constants.h"
69#include "llvm/IR/DataLayout.h"
70#include "llvm/IR/DebugInfoMetadata.h"
71#include "llvm/IR/DerivedTypes.h"
72#include "llvm/IR/Function.h"
73#include "llvm/IR/GetElementPtrTypeIterator.h"
74#include "llvm/IR/InlineAsm.h"
75#include "llvm/IR/InstrTypes.h"
76#include "llvm/IR/Instructions.h"
77#include "llvm/IR/IntrinsicInst.h"
78#include "llvm/IR/Intrinsics.h"
79#include "llvm/IR/IntrinsicsAArch64.h"
80#include "llvm/IR/IntrinsicsWebAssembly.h"
81#include "llvm/IR/LLVMContext.h"
82#include "llvm/IR/Metadata.h"
83#include "llvm/IR/Module.h"
84#include "llvm/IR/Operator.h"
85#include "llvm/IR/PatternMatch.h"
86#include "llvm/IR/Statepoint.h"
87#include "llvm/IR/Type.h"
88#include "llvm/IR/User.h"
89#include "llvm/IR/Value.h"
90#include "llvm/MC/MCContext.h"
91#include "llvm/MC/MCSymbol.h"
92#include "llvm/Support/AtomicOrdering.h"
93#include "llvm/Support/Casting.h"
94#include "llvm/Support/CommandLine.h"
95#include "llvm/Support/Compiler.h"
96#include "llvm/Support/Debug.h"
97#include "llvm/Support/MathExtras.h"
98#include "llvm/Support/raw_ostream.h"
99#include "llvm/Target/TargetIntrinsicInfo.h"
100#include "llvm/Target/TargetMachine.h"
101#include "llvm/Target/TargetOptions.h"
102#include "llvm/Transforms/Utils/Local.h"
103#include <cstddef>
104#include <cstring>
105#include <iterator>
106#include <limits>
107#include <numeric>
108#include <tuple>
109
110using namespace llvm;
111using namespace PatternMatch;
112using namespace SwitchCG;
113
114#define DEBUG_TYPE"isel" "isel"
115
116/// LimitFloatPrecision - Generate low-precision inline sequences for
117/// some float libcalls (6, 8 or 12 bits).
118static unsigned LimitFloatPrecision;
119
120static cl::opt<bool>
121 InsertAssertAlign("insert-assert-align", cl::init(true),
122 cl::desc("Insert the experimental `assertalign` node."),
123 cl::ReallyHidden);
124
125static cl::opt<unsigned, true>
126 LimitFPPrecision("limit-float-precision",
127 cl::desc("Generate low-precision inline sequences "
128 "for some float libcalls"),
129 cl::location(LimitFloatPrecision), cl::Hidden,
130 cl::init(0));
131
132static cl::opt<unsigned> SwitchPeelThreshold(
133 "switch-peel-threshold", cl::Hidden, cl::init(66),
134 cl::desc("Set the case probability threshold for peeling the case from a "
135 "switch statement. A value greater than 100 will void this "
136 "optimization"));
137
138// Limit the width of DAG chains. This is important in general to prevent
139// DAG-based analysis from blowing up. For example, alias analysis and
140// load clustering may not complete in reasonable time. It is difficult to
141// recognize and avoid this situation within each individual analysis, and
142// future analyses are likely to have the same behavior. Limiting DAG width is
143// the safe approach and will be especially important with global DAGs.
144//
145// MaxParallelChains default is arbitrarily high to avoid affecting
146// optimization, but could be lowered to improve compile time. Any ld-ld-st-st
147// sequence over this should have been converted to llvm.memcpy by the
148// frontend. It is easy to induce this behavior with .ll code such as:
149// %buffer = alloca [4096 x i8]
150// %data = load [4096 x i8]* %argPtr
151// store [4096 x i8] %data, [4096 x i8]* %buffer
152static const unsigned MaxParallelChains = 64;
153
154static SDValue getCopyFromPartsVector(SelectionDAG &DAG, const SDLoc &DL,
155 const SDValue *Parts, unsigned NumParts,
156 MVT PartVT, EVT ValueVT, const Value *V,
157 Optional<CallingConv::ID> CC);
158
159/// getCopyFromParts - Create a value that contains the specified legal parts
160/// combined into the value they represent. If the parts combine to a type
161/// larger than ValueVT then AssertOp can be used to specify whether the extra
162/// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
163/// (ISD::AssertSext).
164static SDValue getCopyFromParts(SelectionDAG &DAG, const SDLoc &DL,
165 const SDValue *Parts, unsigned NumParts,
166 MVT PartVT, EVT ValueVT, const Value *V,
167 Optional<CallingConv::ID> CC = None,
168 Optional<ISD::NodeType> AssertOp = None) {
169 // Let the target assemble the parts if it wants to
170 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
171 if (SDValue Val = TLI.joinRegisterPartsIntoValue(DAG, DL, Parts, NumParts,
172 PartVT, ValueVT, CC))
173 return Val;
174
175 if (ValueVT.isVector())
176 return getCopyFromPartsVector(DAG, DL, Parts, NumParts, PartVT, ValueVT, V,
177 CC);
178
179 assert(NumParts > 0 && "No parts to assemble!")((NumParts > 0 && "No parts to assemble!") ? static_cast
<void> (0) : __assert_fail ("NumParts > 0 && \"No parts to assemble!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 179, __PRETTY_FUNCTION__))
;
180 SDValue Val = Parts[0];
181
182 if (NumParts > 1) {
183 // Assemble the value from multiple parts.
184 if (ValueVT.isInteger()) {
185 unsigned PartBits = PartVT.getSizeInBits();
186 unsigned ValueBits = ValueVT.getSizeInBits();
187
188 // Assemble the power of 2 part.
189 unsigned RoundParts =
190 (NumParts & (NumParts - 1)) ? 1 << Log2_32(NumParts) : NumParts;
191 unsigned RoundBits = PartBits * RoundParts;
192 EVT RoundVT = RoundBits == ValueBits ?
193 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
194 SDValue Lo, Hi;
195
196 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
197
198 if (RoundParts > 2) {
199 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2,
200 PartVT, HalfVT, V);
201 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2,
202 RoundParts / 2, PartVT, HalfVT, V);
203 } else {
204 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]);
205 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]);
206 }
207
208 if (DAG.getDataLayout().isBigEndian())
209 std::swap(Lo, Hi);
210
211 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
212
213 if (RoundParts < NumParts) {
214 // Assemble the trailing non-power-of-2 part.
215 unsigned OddParts = NumParts - RoundParts;
216 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
217 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts, OddParts, PartVT,
218 OddVT, V, CC);
219
220 // Combine the round and odd parts.
221 Lo = Val;
222 if (DAG.getDataLayout().isBigEndian())
223 std::swap(Lo, Hi);
224 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
225 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi);
226 Hi =
227 DAG.getNode(ISD::SHL, DL, TotalVT, Hi,
228 DAG.getConstant(Lo.getValueSizeInBits(), DL,
229 TLI.getPointerTy(DAG.getDataLayout())));
230 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo);
231 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi);
232 }
233 } else if (PartVT.isFloatingPoint()) {
234 // FP split into multiple FP parts (for ppcf128)
235 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 &&((ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 &&
"Unexpected split") ? static_cast<void> (0) : __assert_fail
("ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 && \"Unexpected split\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 236, __PRETTY_FUNCTION__))
236 "Unexpected split")((ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 &&
"Unexpected split") ? static_cast<void> (0) : __assert_fail
("ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 && \"Unexpected split\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 236, __PRETTY_FUNCTION__))
;
237 SDValue Lo, Hi;
238 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]);
239 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]);
240 if (TLI.hasBigEndianPartOrdering(ValueVT, DAG.getDataLayout()))
241 std::swap(Lo, Hi);
242 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi);
243 } else {
244 // FP split into integer parts (soft fp)
245 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&((ValueVT.isFloatingPoint() && PartVT.isInteger() &&
!PartVT.isVector() && "Unexpected split") ? static_cast
<void> (0) : __assert_fail ("ValueVT.isFloatingPoint() && PartVT.isInteger() && !PartVT.isVector() && \"Unexpected split\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 246, __PRETTY_FUNCTION__))
246 !PartVT.isVector() && "Unexpected split")((ValueVT.isFloatingPoint() && PartVT.isInteger() &&
!PartVT.isVector() && "Unexpected split") ? static_cast
<void> (0) : __assert_fail ("ValueVT.isFloatingPoint() && PartVT.isInteger() && !PartVT.isVector() && \"Unexpected split\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 246, __PRETTY_FUNCTION__))
;
247 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
248 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT, V, CC);
249 }
250 }
251
252 // There is now one part, held in Val. Correct it to match ValueVT.
253 // PartEVT is the type of the register class that holds the value.
254 // ValueVT is the type of the inline asm operation.
255 EVT PartEVT = Val.getValueType();
256
257 if (PartEVT == ValueVT)
258 return Val;
259
260 if (PartEVT.isInteger() && ValueVT.isFloatingPoint() &&
261 ValueVT.bitsLT(PartEVT)) {
262 // For an FP value in an integer part, we need to truncate to the right
263 // width first.
264 PartEVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
265 Val = DAG.getNode(ISD::TRUNCATE, DL, PartEVT, Val);
266 }
267
268 // Handle types that have the same size.
269 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits())
270 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
271
272 // Handle types with different sizes.
273 if (PartEVT.isInteger() && ValueVT.isInteger()) {
274 if (ValueVT.bitsLT(PartEVT)) {
275 // For a truncate, see if we have any information to
276 // indicate whether the truncated bits will always be
277 // zero or sign-extension.
278 if (AssertOp.hasValue())
279 Val = DAG.getNode(*AssertOp, DL, PartEVT, Val,
280 DAG.getValueType(ValueVT));
281 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
282 }
283 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val);
284 }
285
286 if (PartEVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
287 // FP_ROUND's are always exact here.
288 if (ValueVT.bitsLT(Val.getValueType()))
289 return DAG.getNode(
290 ISD::FP_ROUND, DL, ValueVT, Val,
291 DAG.getTargetConstant(1, DL, TLI.getPointerTy(DAG.getDataLayout())));
292
293 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);
294 }
295
296 // Handle MMX to a narrower integer type by bitcasting MMX to integer and
297 // then truncating.
298 if (PartEVT == MVT::x86mmx && ValueVT.isInteger() &&
299 ValueVT.bitsLT(PartEVT)) {
300 Val = DAG.getNode(ISD::BITCAST, DL, MVT::i64, Val);
301 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
302 }
303
304 report_fatal_error("Unknown mismatch in getCopyFromParts!");
305}
306
307static void diagnosePossiblyInvalidConstraint(LLVMContext &Ctx, const Value *V,
308 const Twine &ErrMsg) {
309 const Instruction *I = dyn_cast_or_null<Instruction>(V);
310 if (!V)
311 return Ctx.emitError(ErrMsg);
312
313 const char *AsmError = ", possible invalid constraint for vector type";
314 if (const CallInst *CI = dyn_cast<CallInst>(I))
315 if (CI->isInlineAsm())
316 return Ctx.emitError(I, ErrMsg + AsmError);
317
318 return Ctx.emitError(I, ErrMsg);
319}
320
321/// getCopyFromPartsVector - Create a value that contains the specified legal
322/// parts combined into the value they represent. If the parts combine to a
323/// type larger than ValueVT then AssertOp can be used to specify whether the
324/// extra bits are known to be zero (ISD::AssertZext) or sign extended from
325/// ValueVT (ISD::AssertSext).
326static SDValue getCopyFromPartsVector(SelectionDAG &DAG, const SDLoc &DL,
327 const SDValue *Parts, unsigned NumParts,
328 MVT PartVT, EVT ValueVT, const Value *V,
329 Optional<CallingConv::ID> CallConv) {
330 assert(ValueVT.isVector() && "Not a vector value")((ValueVT.isVector() && "Not a vector value") ? static_cast
<void> (0) : __assert_fail ("ValueVT.isVector() && \"Not a vector value\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 330, __PRETTY_FUNCTION__))
;
331 assert(NumParts > 0 && "No parts to assemble!")((NumParts > 0 && "No parts to assemble!") ? static_cast
<void> (0) : __assert_fail ("NumParts > 0 && \"No parts to assemble!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 331, __PRETTY_FUNCTION__))
;
332 const bool IsABIRegCopy = CallConv.hasValue();
333
334 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
335 SDValue Val = Parts[0];
336
337 // Handle a multi-element vector.
338 if (NumParts > 1) {
339 EVT IntermediateVT;
340 MVT RegisterVT;
341 unsigned NumIntermediates;
342 unsigned NumRegs;
343
344 if (IsABIRegCopy) {
345 NumRegs = TLI.getVectorTypeBreakdownForCallingConv(
346 *DAG.getContext(), CallConv.getValue(), ValueVT, IntermediateVT,
347 NumIntermediates, RegisterVT);
348 } else {
349 NumRegs =
350 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
351 NumIntermediates, RegisterVT);
352 }
353
354 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!")((NumRegs == NumParts && "Part count doesn't match vector breakdown!"
) ? static_cast<void> (0) : __assert_fail ("NumRegs == NumParts && \"Part count doesn't match vector breakdown!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 354, __PRETTY_FUNCTION__))
;
355 NumParts = NumRegs; // Silence a compiler warning.
356 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!")((RegisterVT == PartVT && "Part type doesn't match vector breakdown!"
) ? static_cast<void> (0) : __assert_fail ("RegisterVT == PartVT && \"Part type doesn't match vector breakdown!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 356, __PRETTY_FUNCTION__))
;
357 assert(RegisterVT.getSizeInBits() ==((RegisterVT.getSizeInBits() == Parts[0].getSimpleValueType()
.getSizeInBits() && "Part type sizes don't match!") ?
static_cast<void> (0) : __assert_fail ("RegisterVT.getSizeInBits() == Parts[0].getSimpleValueType().getSizeInBits() && \"Part type sizes don't match!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 359, __PRETTY_FUNCTION__))
358 Parts[0].getSimpleValueType().getSizeInBits() &&((RegisterVT.getSizeInBits() == Parts[0].getSimpleValueType()
.getSizeInBits() && "Part type sizes don't match!") ?
static_cast<void> (0) : __assert_fail ("RegisterVT.getSizeInBits() == Parts[0].getSimpleValueType().getSizeInBits() && \"Part type sizes don't match!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 359, __PRETTY_FUNCTION__))
359 "Part type sizes don't match!")((RegisterVT.getSizeInBits() == Parts[0].getSimpleValueType()
.getSizeInBits() && "Part type sizes don't match!") ?
static_cast<void> (0) : __assert_fail ("RegisterVT.getSizeInBits() == Parts[0].getSimpleValueType().getSizeInBits() && \"Part type sizes don't match!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 359, __PRETTY_FUNCTION__))
;
360
361 // Assemble the parts into intermediate operands.
362 SmallVector<SDValue, 8> Ops(NumIntermediates);
363 if (NumIntermediates == NumParts) {
364 // If the register was not expanded, truncate or copy the value,
365 // as appropriate.
366 for (unsigned i = 0; i != NumParts; ++i)
367 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1,
368 PartVT, IntermediateVT, V, CallConv);
369 } else if (NumParts > 0) {
370 // If the intermediate type was expanded, build the intermediate
371 // operands from the parts.
372 assert(NumParts % NumIntermediates == 0 &&((NumParts % NumIntermediates == 0 && "Must expand into a divisible number of parts!"
) ? static_cast<void> (0) : __assert_fail ("NumParts % NumIntermediates == 0 && \"Must expand into a divisible number of parts!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 373, __PRETTY_FUNCTION__))
373 "Must expand into a divisible number of parts!")((NumParts % NumIntermediates == 0 && "Must expand into a divisible number of parts!"
) ? static_cast<void> (0) : __assert_fail ("NumParts % NumIntermediates == 0 && \"Must expand into a divisible number of parts!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 373, __PRETTY_FUNCTION__))
;
374 unsigned Factor = NumParts / NumIntermediates;
375 for (unsigned i = 0; i != NumIntermediates; ++i)
376 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor,
377 PartVT, IntermediateVT, V, CallConv);
378 }
379
380 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
381 // intermediate operands.
382 EVT BuiltVectorTy =
383 IntermediateVT.isVector()
384 ? EVT::getVectorVT(
385 *DAG.getContext(), IntermediateVT.getScalarType(),
386 IntermediateVT.getVectorElementCount() * NumParts)
387 : EVT::getVectorVT(*DAG.getContext(),
388 IntermediateVT.getScalarType(),
389 NumIntermediates);
390 Val = DAG.getNode(IntermediateVT.isVector() ? ISD::CONCAT_VECTORS
391 : ISD::BUILD_VECTOR,
392 DL, BuiltVectorTy, Ops);
393 }
394
395 // There is now one part, held in Val. Correct it to match ValueVT.
396 EVT PartEVT = Val.getValueType();
397
398 if (PartEVT == ValueVT)
399 return Val;
400
401 if (PartEVT.isVector()) {
402 // If the element type of the source/dest vectors are the same, but the
403 // parts vector has more elements than the value vector, then we have a
404 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the
405 // elements we want.
406 if (PartEVT.getVectorElementType() == ValueVT.getVectorElementType()) {
407 assert((PartEVT.getVectorElementCount().getKnownMinValue() >(((PartEVT.getVectorElementCount().getKnownMinValue() > ValueVT
.getVectorElementCount().getKnownMinValue()) && (PartEVT
.getVectorElementCount().isScalable() == ValueVT.getVectorElementCount
().isScalable()) && "Cannot narrow, it would be a lossy transformation"
) ? static_cast<void> (0) : __assert_fail ("(PartEVT.getVectorElementCount().getKnownMinValue() > ValueVT.getVectorElementCount().getKnownMinValue()) && (PartEVT.getVectorElementCount().isScalable() == ValueVT.getVectorElementCount().isScalable()) && \"Cannot narrow, it would be a lossy transformation\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 411, __PRETTY_FUNCTION__))
408 ValueVT.getVectorElementCount().getKnownMinValue()) &&(((PartEVT.getVectorElementCount().getKnownMinValue() > ValueVT
.getVectorElementCount().getKnownMinValue()) && (PartEVT
.getVectorElementCount().isScalable() == ValueVT.getVectorElementCount
().isScalable()) && "Cannot narrow, it would be a lossy transformation"
) ? static_cast<void> (0) : __assert_fail ("(PartEVT.getVectorElementCount().getKnownMinValue() > ValueVT.getVectorElementCount().getKnownMinValue()) && (PartEVT.getVectorElementCount().isScalable() == ValueVT.getVectorElementCount().isScalable()) && \"Cannot narrow, it would be a lossy transformation\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 411, __PRETTY_FUNCTION__))
409 (PartEVT.getVectorElementCount().isScalable() ==(((PartEVT.getVectorElementCount().getKnownMinValue() > ValueVT
.getVectorElementCount().getKnownMinValue()) && (PartEVT
.getVectorElementCount().isScalable() == ValueVT.getVectorElementCount
().isScalable()) && "Cannot narrow, it would be a lossy transformation"
) ? static_cast<void> (0) : __assert_fail ("(PartEVT.getVectorElementCount().getKnownMinValue() > ValueVT.getVectorElementCount().getKnownMinValue()) && (PartEVT.getVectorElementCount().isScalable() == ValueVT.getVectorElementCount().isScalable()) && \"Cannot narrow, it would be a lossy transformation\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 411, __PRETTY_FUNCTION__))
410 ValueVT.getVectorElementCount().isScalable()) &&(((PartEVT.getVectorElementCount().getKnownMinValue() > ValueVT
.getVectorElementCount().getKnownMinValue()) && (PartEVT
.getVectorElementCount().isScalable() == ValueVT.getVectorElementCount
().isScalable()) && "Cannot narrow, it would be a lossy transformation"
) ? static_cast<void> (0) : __assert_fail ("(PartEVT.getVectorElementCount().getKnownMinValue() > ValueVT.getVectorElementCount().getKnownMinValue()) && (PartEVT.getVectorElementCount().isScalable() == ValueVT.getVectorElementCount().isScalable()) && \"Cannot narrow, it would be a lossy transformation\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 411, __PRETTY_FUNCTION__))
411 "Cannot narrow, it would be a lossy transformation")(((PartEVT.getVectorElementCount().getKnownMinValue() > ValueVT
.getVectorElementCount().getKnownMinValue()) && (PartEVT
.getVectorElementCount().isScalable() == ValueVT.getVectorElementCount
().isScalable()) && "Cannot narrow, it would be a lossy transformation"
) ? static_cast<void> (0) : __assert_fail ("(PartEVT.getVectorElementCount().getKnownMinValue() > ValueVT.getVectorElementCount().getKnownMinValue()) && (PartEVT.getVectorElementCount().isScalable() == ValueVT.getVectorElementCount().isScalable()) && \"Cannot narrow, it would be a lossy transformation\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 411, __PRETTY_FUNCTION__))
;
412 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
413 DAG.getVectorIdxConstant(0, DL));
414 }
415
416 // Vector/Vector bitcast.
417 if (ValueVT.getSizeInBits() == PartEVT.getSizeInBits())
418 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
419
420 assert(PartEVT.getVectorElementCount() == ValueVT.getVectorElementCount() &&((PartEVT.getVectorElementCount() == ValueVT.getVectorElementCount
() && "Cannot handle this kind of promotion") ? static_cast
<void> (0) : __assert_fail ("PartEVT.getVectorElementCount() == ValueVT.getVectorElementCount() && \"Cannot handle this kind of promotion\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 421, __PRETTY_FUNCTION__))
421 "Cannot handle this kind of promotion")((PartEVT.getVectorElementCount() == ValueVT.getVectorElementCount
() && "Cannot handle this kind of promotion") ? static_cast
<void> (0) : __assert_fail ("PartEVT.getVectorElementCount() == ValueVT.getVectorElementCount() && \"Cannot handle this kind of promotion\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 421, __PRETTY_FUNCTION__))
;
422 // Promoted vector extract
423 return DAG.getAnyExtOrTrunc(Val, DL, ValueVT);
424
425 }
426
427 // Trivial bitcast if the types are the same size and the destination
428 // vector type is legal.
429 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits() &&
430 TLI.isTypeLegal(ValueVT))
431 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
432
433 if (ValueVT.getVectorNumElements() != 1) {
434 // Certain ABIs require that vectors are passed as integers. For vectors
435 // are the same size, this is an obvious bitcast.
436 if (ValueVT.getSizeInBits() == PartEVT.getSizeInBits()) {
437 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
438 } else if (ValueVT.bitsLT(PartEVT)) {
439 // Bitcast Val back the original type and extract the corresponding
440 // vector we want.
441 unsigned Elts = PartEVT.getSizeInBits() / ValueVT.getScalarSizeInBits();
442 EVT WiderVecType = EVT::getVectorVT(*DAG.getContext(),
443 ValueVT.getVectorElementType(), Elts);
444 Val = DAG.getBitcast(WiderVecType, Val);
445 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
446 DAG.getVectorIdxConstant(0, DL));
447 }
448
449 diagnosePossiblyInvalidConstraint(
450 *DAG.getContext(), V, "non-trivial scalar-to-vector conversion");
451 return DAG.getUNDEF(ValueVT);
452 }
453
454 // Handle cases such as i8 -> <1 x i1>
455 EVT ValueSVT = ValueVT.getVectorElementType();
456 if (ValueVT.getVectorNumElements() == 1 && ValueSVT != PartEVT) {
457 if (ValueSVT.getSizeInBits() == PartEVT.getSizeInBits())
458 Val = DAG.getNode(ISD::BITCAST, DL, ValueSVT, Val);
459 else
460 Val = ValueVT.isFloatingPoint()
461 ? DAG.getFPExtendOrRound(Val, DL, ValueSVT)
462 : DAG.getAnyExtOrTrunc(Val, DL, ValueSVT);
463 }
464
465 return DAG.getBuildVector(ValueVT, DL, Val);
466}
467
468static void getCopyToPartsVector(SelectionDAG &DAG, const SDLoc &dl,
469 SDValue Val, SDValue *Parts, unsigned NumParts,
470 MVT PartVT, const Value *V,
471 Optional<CallingConv::ID> CallConv);
472
473/// getCopyToParts - Create a series of nodes that contain the specified value
474/// split into legal parts. If the parts contain more bits than Val, then, for
475/// integers, ExtendKind can be used to specify how to generate the extra bits.
476static void getCopyToParts(SelectionDAG &DAG, const SDLoc &DL, SDValue Val,
477 SDValue *Parts, unsigned NumParts, MVT PartVT,
478 const Value *V,
479 Optional<CallingConv::ID> CallConv = None,
480 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
481 // Let the target split the parts if it wants to
482 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
483 if (TLI.splitValueIntoRegisterParts(DAG, DL, Val, Parts, NumParts, PartVT,
484 CallConv))
485 return;
486 EVT ValueVT = Val.getValueType();
487
488 // Handle the vector case separately.
489 if (ValueVT.isVector())
490 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT, V,
491 CallConv);
492
493 unsigned PartBits = PartVT.getSizeInBits();
494 unsigned OrigNumParts = NumParts;
495 assert(DAG.getTargetLoweringInfo().isTypeLegal(PartVT) &&((DAG.getTargetLoweringInfo().isTypeLegal(PartVT) && "Copying to an illegal type!"
) ? static_cast<void> (0) : __assert_fail ("DAG.getTargetLoweringInfo().isTypeLegal(PartVT) && \"Copying to an illegal type!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 496, __PRETTY_FUNCTION__))
496 "Copying to an illegal type!")((DAG.getTargetLoweringInfo().isTypeLegal(PartVT) && "Copying to an illegal type!"
) ? static_cast<void> (0) : __assert_fail ("DAG.getTargetLoweringInfo().isTypeLegal(PartVT) && \"Copying to an illegal type!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 496, __PRETTY_FUNCTION__))
;
497
498 if (NumParts == 0)
499 return;
500
501 assert(!ValueVT.isVector() && "Vector case handled elsewhere")((!ValueVT.isVector() && "Vector case handled elsewhere"
) ? static_cast<void> (0) : __assert_fail ("!ValueVT.isVector() && \"Vector case handled elsewhere\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 501, __PRETTY_FUNCTION__))
;
502 EVT PartEVT = PartVT;
503 if (PartEVT == ValueVT) {
504 assert(NumParts == 1 && "No-op copy with multiple parts!")((NumParts == 1 && "No-op copy with multiple parts!")
? static_cast<void> (0) : __assert_fail ("NumParts == 1 && \"No-op copy with multiple parts!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 504, __PRETTY_FUNCTION__))
;
505 Parts[0] = Val;
506 return;
507 }
508
509 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
510 // If the parts cover more bits than the value has, promote the value.
511 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
512 assert(NumParts == 1 && "Do not know what to promote to!")((NumParts == 1 && "Do not know what to promote to!")
? static_cast<void> (0) : __assert_fail ("NumParts == 1 && \"Do not know what to promote to!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 512, __PRETTY_FUNCTION__))
;
513 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val);
514 } else {
515 if (ValueVT.isFloatingPoint()) {
516 // FP values need to be bitcast, then extended if they are being put
517 // into a larger container.
518 ValueVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
519 Val = DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
520 }
521 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&(((PartVT.isInteger() || PartVT == MVT::x86mmx) && ValueVT
.isInteger() && "Unknown mismatch!") ? static_cast<
void> (0) : __assert_fail ("(PartVT.isInteger() || PartVT == MVT::x86mmx) && ValueVT.isInteger() && \"Unknown mismatch!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 523, __PRETTY_FUNCTION__))
522 ValueVT.isInteger() &&(((PartVT.isInteger() || PartVT == MVT::x86mmx) && ValueVT
.isInteger() && "Unknown mismatch!") ? static_cast<
void> (0) : __assert_fail ("(PartVT.isInteger() || PartVT == MVT::x86mmx) && ValueVT.isInteger() && \"Unknown mismatch!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 523, __PRETTY_FUNCTION__))
523 "Unknown mismatch!")(((PartVT.isInteger() || PartVT == MVT::x86mmx) && ValueVT
.isInteger() && "Unknown mismatch!") ? static_cast<
void> (0) : __assert_fail ("(PartVT.isInteger() || PartVT == MVT::x86mmx) && ValueVT.isInteger() && \"Unknown mismatch!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 523, __PRETTY_FUNCTION__))
;
524 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
525 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val);
526 if (PartVT == MVT::x86mmx)
527 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
528 }
529 } else if (PartBits == ValueVT.getSizeInBits()) {
530 // Different types of the same size.
531 assert(NumParts == 1 && PartEVT != ValueVT)((NumParts == 1 && PartEVT != ValueVT) ? static_cast<
void> (0) : __assert_fail ("NumParts == 1 && PartEVT != ValueVT"
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 531, __PRETTY_FUNCTION__))
;
532 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
533 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
534 // If the parts cover less bits than value has, truncate the value.
535 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&(((PartVT.isInteger() || PartVT == MVT::x86mmx) && ValueVT
.isInteger() && "Unknown mismatch!") ? static_cast<
void> (0) : __assert_fail ("(PartVT.isInteger() || PartVT == MVT::x86mmx) && ValueVT.isInteger() && \"Unknown mismatch!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 537, __PRETTY_FUNCTION__))
536 ValueVT.isInteger() &&(((PartVT.isInteger() || PartVT == MVT::x86mmx) && ValueVT
.isInteger() && "Unknown mismatch!") ? static_cast<
void> (0) : __assert_fail ("(PartVT.isInteger() || PartVT == MVT::x86mmx) && ValueVT.isInteger() && \"Unknown mismatch!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 537, __PRETTY_FUNCTION__))
537 "Unknown mismatch!")(((PartVT.isInteger() || PartVT == MVT::x86mmx) && ValueVT
.isInteger() && "Unknown mismatch!") ? static_cast<
void> (0) : __assert_fail ("(PartVT.isInteger() || PartVT == MVT::x86mmx) && ValueVT.isInteger() && \"Unknown mismatch!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 537, __PRETTY_FUNCTION__))
;
538 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
539 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
540 if (PartVT == MVT::x86mmx)
541 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
542 }
543
544 // The value may have changed - recompute ValueVT.
545 ValueVT = Val.getValueType();
546 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&((NumParts * PartBits == ValueVT.getSizeInBits() && "Failed to tile the value with PartVT!"
) ? static_cast<void> (0) : __assert_fail ("NumParts * PartBits == ValueVT.getSizeInBits() && \"Failed to tile the value with PartVT!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 547, __PRETTY_FUNCTION__))
547 "Failed to tile the value with PartVT!")((NumParts * PartBits == ValueVT.getSizeInBits() && "Failed to tile the value with PartVT!"
) ? static_cast<void> (0) : __assert_fail ("NumParts * PartBits == ValueVT.getSizeInBits() && \"Failed to tile the value with PartVT!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 547, __PRETTY_FUNCTION__))
;
548
549 if (NumParts == 1) {
550 if (PartEVT != ValueVT) {
551 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
552 "scalar-to-vector conversion failed");
553 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
554 }
555
556 Parts[0] = Val;
557 return;
558 }
559
560 // Expand the value into multiple parts.
561 if (NumParts & (NumParts - 1)) {
562 // The number of parts is not a power of 2. Split off and copy the tail.
563 assert(PartVT.isInteger() && ValueVT.isInteger() &&((PartVT.isInteger() && ValueVT.isInteger() &&
"Do not know what to expand to!") ? static_cast<void> (
0) : __assert_fail ("PartVT.isInteger() && ValueVT.isInteger() && \"Do not know what to expand to!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 564, __PRETTY_FUNCTION__))
564 "Do not know what to expand to!")((PartVT.isInteger() && ValueVT.isInteger() &&
"Do not know what to expand to!") ? static_cast<void> (
0) : __assert_fail ("PartVT.isInteger() && ValueVT.isInteger() && \"Do not know what to expand to!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 564, __PRETTY_FUNCTION__))
;
565 unsigned RoundParts = 1 << Log2_32(NumParts);
566 unsigned RoundBits = RoundParts * PartBits;
567 unsigned OddParts = NumParts - RoundParts;
568 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val,
569 DAG.getShiftAmountConstant(RoundBits, ValueVT, DL, /*LegalTypes*/false));
570
571 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT, V,
572 CallConv);
573
574 if (DAG.getDataLayout().isBigEndian())
575 // The odd parts were reversed by getCopyToParts - unreverse them.
576 std::reverse(Parts + RoundParts, Parts + NumParts);
577
578 NumParts = RoundParts;
579 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
580 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
581 }
582
583 // The number of parts is a power of 2. Repeatedly bisect the value using
584 // EXTRACT_ELEMENT.
585 Parts[0] = DAG.getNode(ISD::BITCAST, DL,
586 EVT::getIntegerVT(*DAG.getContext(),
587 ValueVT.getSizeInBits()),
588 Val);
589
590 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
591 for (unsigned i = 0; i < NumParts; i += StepSize) {
592 unsigned ThisBits = StepSize * PartBits / 2;
593 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
594 SDValue &Part0 = Parts[i];
595 SDValue &Part1 = Parts[i+StepSize/2];
596
597 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
598 ThisVT, Part0, DAG.getIntPtrConstant(1, DL));
599 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
600 ThisVT, Part0, DAG.getIntPtrConstant(0, DL));
601
602 if (ThisBits == PartBits && ThisVT != PartVT) {
603 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0);
604 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1);
605 }
606 }
607 }
608
609 if (DAG.getDataLayout().isBigEndian())
610 std::reverse(Parts, Parts + OrigNumParts);
611}
612
613static SDValue widenVectorToPartType(SelectionDAG &DAG,
614 SDValue Val, const SDLoc &DL, EVT PartVT) {
615 if (!PartVT.isFixedLengthVector())
616 return SDValue();
617
618 EVT ValueVT = Val.getValueType();
619 unsigned PartNumElts = PartVT.getVectorNumElements();
620 unsigned ValueNumElts = ValueVT.getVectorNumElements();
621 if (PartNumElts > ValueNumElts &&
622 PartVT.getVectorElementType() == ValueVT.getVectorElementType()) {
623 EVT ElementVT = PartVT.getVectorElementType();
624 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in
625 // undef elements.
626 SmallVector<SDValue, 16> Ops;
627 DAG.ExtractVectorElements(Val, Ops);
628 SDValue EltUndef = DAG.getUNDEF(ElementVT);
629 for (unsigned i = ValueNumElts, e = PartNumElts; i != e; ++i)
630 Ops.push_back(EltUndef);
631
632 // FIXME: Use CONCAT for 2x -> 4x.
633 return DAG.getBuildVector(PartVT, DL, Ops);
634 }
635
636 return SDValue();
637}
638
639/// getCopyToPartsVector - Create a series of nodes that contain the specified
640/// value split into legal parts.
641static void getCopyToPartsVector(SelectionDAG &DAG, const SDLoc &DL,
642 SDValue Val, SDValue *Parts, unsigned NumParts,
643 MVT PartVT, const Value *V,
644 Optional<CallingConv::ID> CallConv) {
645 EVT ValueVT = Val.getValueType();
646 assert(ValueVT.isVector() && "Not a vector")((ValueVT.isVector() && "Not a vector") ? static_cast
<void> (0) : __assert_fail ("ValueVT.isVector() && \"Not a vector\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 646, __PRETTY_FUNCTION__))
;
647 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
648 const bool IsABIRegCopy = CallConv.hasValue();
649
650 if (NumParts == 1) {
651 EVT PartEVT = PartVT;
652 if (PartEVT == ValueVT) {
653 // Nothing to do.
654 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
655 // Bitconvert vector->vector case.
656 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
657 } else if (SDValue Widened = widenVectorToPartType(DAG, Val, DL, PartVT)) {
658 Val = Widened;
659 } else if (PartVT.isVector() &&
660 PartEVT.getVectorElementType().bitsGE(
661 ValueVT.getVectorElementType()) &&
662 PartEVT.getVectorElementCount() ==
663 ValueVT.getVectorElementCount()) {
664
665 // Promoted vector extract
666 Val = DAG.getAnyExtOrTrunc(Val, DL, PartVT);
667 } else {
668 if (ValueVT.getVectorElementCount().isScalar()) {
669 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, PartVT, Val,
670 DAG.getVectorIdxConstant(0, DL));
671 } else {
672 uint64_t ValueSize = ValueVT.getFixedSizeInBits();
673 assert(PartVT.getFixedSizeInBits() > ValueSize &&((PartVT.getFixedSizeInBits() > ValueSize && "lossy conversion of vector to scalar type"
) ? static_cast<void> (0) : __assert_fail ("PartVT.getFixedSizeInBits() > ValueSize && \"lossy conversion of vector to scalar type\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 674, __PRETTY_FUNCTION__))
674 "lossy conversion of vector to scalar type")((PartVT.getFixedSizeInBits() > ValueSize && "lossy conversion of vector to scalar type"
) ? static_cast<void> (0) : __assert_fail ("PartVT.getFixedSizeInBits() > ValueSize && \"lossy conversion of vector to scalar type\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 674, __PRETTY_FUNCTION__))
;
675 EVT IntermediateType = EVT::getIntegerVT(*DAG.getContext(), ValueSize);
676 Val = DAG.getBitcast(IntermediateType, Val);
677 Val = DAG.getAnyExtOrTrunc(Val, DL, PartVT);
678 }
679 }
680
681 assert(Val.getValueType() == PartVT && "Unexpected vector part value type")((Val.getValueType() == PartVT && "Unexpected vector part value type"
) ? static_cast<void> (0) : __assert_fail ("Val.getValueType() == PartVT && \"Unexpected vector part value type\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 681, __PRETTY_FUNCTION__))
;
682 Parts[0] = Val;
683 return;
684 }
685
686 // Handle a multi-element vector.
687 EVT IntermediateVT;
688 MVT RegisterVT;
689 unsigned NumIntermediates;
690 unsigned NumRegs;
691 if (IsABIRegCopy) {
692 NumRegs = TLI.getVectorTypeBreakdownForCallingConv(
693 *DAG.getContext(), CallConv.getValue(), ValueVT, IntermediateVT,
694 NumIntermediates, RegisterVT);
695 } else {
696 NumRegs =
697 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
698 NumIntermediates, RegisterVT);
699 }
700
701 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!")((NumRegs == NumParts && "Part count doesn't match vector breakdown!"
) ? static_cast<void> (0) : __assert_fail ("NumRegs == NumParts && \"Part count doesn't match vector breakdown!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 701, __PRETTY_FUNCTION__))
;
702 NumParts = NumRegs; // Silence a compiler warning.
703 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!")((RegisterVT == PartVT && "Part type doesn't match vector breakdown!"
) ? static_cast<void> (0) : __assert_fail ("RegisterVT == PartVT && \"Part type doesn't match vector breakdown!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 703, __PRETTY_FUNCTION__))
;
704
705 assert(IntermediateVT.isScalableVector() == ValueVT.isScalableVector() &&((IntermediateVT.isScalableVector() == ValueVT.isScalableVector
() && "Mixing scalable and fixed vectors when copying in parts"
) ? static_cast<void> (0) : __assert_fail ("IntermediateVT.isScalableVector() == ValueVT.isScalableVector() && \"Mixing scalable and fixed vectors when copying in parts\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 706, __PRETTY_FUNCTION__))
706 "Mixing scalable and fixed vectors when copying in parts")((IntermediateVT.isScalableVector() == ValueVT.isScalableVector
() && "Mixing scalable and fixed vectors when copying in parts"
) ? static_cast<void> (0) : __assert_fail ("IntermediateVT.isScalableVector() == ValueVT.isScalableVector() && \"Mixing scalable and fixed vectors when copying in parts\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 706, __PRETTY_FUNCTION__))
;
707
708 Optional<ElementCount> DestEltCnt;
709
710 if (IntermediateVT.isVector())
711 DestEltCnt = IntermediateVT.getVectorElementCount() * NumIntermediates;
712 else
713 DestEltCnt = ElementCount::getFixed(NumIntermediates);
714
715 EVT BuiltVectorTy = EVT::getVectorVT(
716 *DAG.getContext(), IntermediateVT.getScalarType(), DestEltCnt.getValue());
717 if (ValueVT != BuiltVectorTy) {
718 if (SDValue Widened = widenVectorToPartType(DAG, Val, DL, BuiltVectorTy))
719 Val = Widened;
720
721 Val = DAG.getNode(ISD::BITCAST, DL, BuiltVectorTy, Val);
722 }
723
724 // Split the vector into intermediate operands.
725 SmallVector<SDValue, 8> Ops(NumIntermediates);
726 for (unsigned i = 0; i != NumIntermediates; ++i) {
727 if (IntermediateVT.isVector()) {
728 // This does something sensible for scalable vectors - see the
729 // definition of EXTRACT_SUBVECTOR for further details.
730 unsigned IntermediateNumElts = IntermediateVT.getVectorMinNumElements();
731 Ops[i] =
732 DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, IntermediateVT, Val,
733 DAG.getVectorIdxConstant(i * IntermediateNumElts, DL));
734 } else {
735 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, IntermediateVT, Val,
736 DAG.getVectorIdxConstant(i, DL));
737 }
738 }
739
740 // Split the intermediate operands into legal parts.
741 if (NumParts == NumIntermediates) {
742 // If the register was not expanded, promote or copy the value,
743 // as appropriate.
744 for (unsigned i = 0; i != NumParts; ++i)
745 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT, V, CallConv);
746 } else if (NumParts > 0) {
747 // If the intermediate type was expanded, split each the value into
748 // legal parts.
749 assert(NumIntermediates != 0 && "division by zero")((NumIntermediates != 0 && "division by zero") ? static_cast
<void> (0) : __assert_fail ("NumIntermediates != 0 && \"division by zero\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 749, __PRETTY_FUNCTION__))
;
750 assert(NumParts % NumIntermediates == 0 &&((NumParts % NumIntermediates == 0 && "Must expand into a divisible number of parts!"
) ? static_cast<void> (0) : __assert_fail ("NumParts % NumIntermediates == 0 && \"Must expand into a divisible number of parts!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 751, __PRETTY_FUNCTION__))
751 "Must expand into a divisible number of parts!")((NumParts % NumIntermediates == 0 && "Must expand into a divisible number of parts!"
) ? static_cast<void> (0) : __assert_fail ("NumParts % NumIntermediates == 0 && \"Must expand into a divisible number of parts!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 751, __PRETTY_FUNCTION__))
;
752 unsigned Factor = NumParts / NumIntermediates;
753 for (unsigned i = 0; i != NumIntermediates; ++i)
754 getCopyToParts(DAG, DL, Ops[i], &Parts[i * Factor], Factor, PartVT, V,
755 CallConv);
756 }
757}
758
759RegsForValue::RegsForValue(const SmallVector<unsigned, 4> &regs, MVT regvt,
760 EVT valuevt, Optional<CallingConv::ID> CC)
761 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs),
762 RegCount(1, regs.size()), CallConv(CC) {}
763
764RegsForValue::RegsForValue(LLVMContext &Context, const TargetLowering &TLI,
765 const DataLayout &DL, unsigned Reg, Type *Ty,
766 Optional<CallingConv::ID> CC) {
767 ComputeValueVTs(TLI, DL, Ty, ValueVTs);
768
769 CallConv = CC;
770
771 for (EVT ValueVT : ValueVTs) {
772 unsigned NumRegs =
773 isABIMangled()
774 ? TLI.getNumRegistersForCallingConv(Context, CC.getValue(), ValueVT)
775 : TLI.getNumRegisters(Context, ValueVT);
776 MVT RegisterVT =
777 isABIMangled()
778 ? TLI.getRegisterTypeForCallingConv(Context, CC.getValue(), ValueVT)
779 : TLI.getRegisterType(Context, ValueVT);
780 for (unsigned i = 0; i != NumRegs; ++i)
781 Regs.push_back(Reg + i);
782 RegVTs.push_back(RegisterVT);
783 RegCount.push_back(NumRegs);
784 Reg += NumRegs;
785 }
786}
787
788SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
789 FunctionLoweringInfo &FuncInfo,
790 const SDLoc &dl, SDValue &Chain,
791 SDValue *Flag, const Value *V) const {
792 // A Value with type {} or [0 x %t] needs no registers.
793 if (ValueVTs.empty())
794 return SDValue();
795
796 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
797
798 // Assemble the legal parts into the final values.
799 SmallVector<SDValue, 4> Values(ValueVTs.size());
800 SmallVector<SDValue, 8> Parts;
801 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
802 // Copy the legal parts from the registers.
803 EVT ValueVT = ValueVTs[Value];
804 unsigned NumRegs = RegCount[Value];
805 MVT RegisterVT = isABIMangled() ? TLI.getRegisterTypeForCallingConv(
806 *DAG.getContext(),
807 CallConv.getValue(), RegVTs[Value])
808 : RegVTs[Value];
809
810 Parts.resize(NumRegs);
811 for (unsigned i = 0; i != NumRegs; ++i) {
812 SDValue P;
813 if (!Flag) {
814 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
815 } else {
816 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
817 *Flag = P.getValue(2);
818 }
819
820 Chain = P.getValue(1);
821 Parts[i] = P;
822
823 // If the source register was virtual and if we know something about it,
824 // add an assert node.
825 if (!Register::isVirtualRegister(Regs[Part + i]) ||
826 !RegisterVT.isInteger())
827 continue;
828
829 const FunctionLoweringInfo::LiveOutInfo *LOI =
830 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]);
831 if (!LOI)
832 continue;
833
834 unsigned RegSize = RegisterVT.getScalarSizeInBits();
835 unsigned NumSignBits = LOI->NumSignBits;
836 unsigned NumZeroBits = LOI->Known.countMinLeadingZeros();
837
838 if (NumZeroBits == RegSize) {
839 // The current value is a zero.
840 // Explicitly express that as it would be easier for
841 // optimizations to kick in.
842 Parts[i] = DAG.getConstant(0, dl, RegisterVT);
843 continue;
844 }
845
846 // FIXME: We capture more information than the dag can represent. For
847 // now, just use the tightest assertzext/assertsext possible.
848 bool isSExt;
849 EVT FromVT(MVT::Other);
850 if (NumZeroBits) {
851 FromVT = EVT::getIntegerVT(*DAG.getContext(), RegSize - NumZeroBits);
852 isSExt = false;
853 } else if (NumSignBits > 1) {
854 FromVT =
855 EVT::getIntegerVT(*DAG.getContext(), RegSize - NumSignBits + 1);
856 isSExt = true;
857 } else {
858 continue;
859 }
860 // Add an assertion node.
861 assert(FromVT != MVT::Other)((FromVT != MVT::Other) ? static_cast<void> (0) : __assert_fail
("FromVT != MVT::Other", "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 861, __PRETTY_FUNCTION__))
;
862 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
863 RegisterVT, P, DAG.getValueType(FromVT));
864 }
865
866 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(), NumRegs,
867 RegisterVT, ValueVT, V, CallConv);
868 Part += NumRegs;
869 Parts.clear();
870 }
871
872 return DAG.getNode(ISD::MERGE_VALUES, dl, DAG.getVTList(ValueVTs), Values);
873}
874
875void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG,
876 const SDLoc &dl, SDValue &Chain, SDValue *Flag,
877 const Value *V,
878 ISD::NodeType PreferredExtendType) const {
879 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
880 ISD::NodeType ExtendKind = PreferredExtendType;
881
882 // Get the list of the values's legal parts.
883 unsigned NumRegs = Regs.size();
884 SmallVector<SDValue, 8> Parts(NumRegs);
885 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
886 unsigned NumParts = RegCount[Value];
887
888 MVT RegisterVT = isABIMangled() ? TLI.getRegisterTypeForCallingConv(
889 *DAG.getContext(),
890 CallConv.getValue(), RegVTs[Value])
891 : RegVTs[Value];
892
893 if (ExtendKind == ISD::ANY_EXTEND && TLI.isZExtFree(Val, RegisterVT))
894 ExtendKind = ISD::ZERO_EXTEND;
895
896 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value), &Parts[Part],
897 NumParts, RegisterVT, V, CallConv, ExtendKind);
898 Part += NumParts;
899 }
900
901 // Copy the parts into the registers.
902 SmallVector<SDValue, 8> Chains(NumRegs);
903 for (unsigned i = 0; i != NumRegs; ++i) {
904 SDValue Part;
905 if (!Flag) {
906 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
907 } else {
908 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
909 *Flag = Part.getValue(1);
910 }
911
912 Chains[i] = Part.getValue(0);
913 }
914
915 if (NumRegs == 1 || Flag)
916 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
917 // flagged to it. That is the CopyToReg nodes and the user are considered
918 // a single scheduling unit. If we create a TokenFactor and return it as
919 // chain, then the TokenFactor is both a predecessor (operand) of the
920 // user as well as a successor (the TF operands are flagged to the user).
921 // c1, f1 = CopyToReg
922 // c2, f2 = CopyToReg
923 // c3 = TokenFactor c1, c2
924 // ...
925 // = op c3, ..., f2
926 Chain = Chains[NumRegs-1];
927 else
928 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
929}
930
931void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
932 unsigned MatchingIdx, const SDLoc &dl,
933 SelectionDAG &DAG,
934 std::vector<SDValue> &Ops) const {
935 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
936
937 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size());
938 if (HasMatching)
939 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx);
940 else if (!Regs.empty() && Register::isVirtualRegister(Regs.front())) {
941 // Put the register class of the virtual registers in the flag word. That
942 // way, later passes can recompute register class constraints for inline
943 // assembly as well as normal instructions.
944 // Don't do this for tied operands that can use the regclass information
945 // from the def.
946 const MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
947 const TargetRegisterClass *RC = MRI.getRegClass(Regs.front());
948 Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID());
949 }
950
951 SDValue Res = DAG.getTargetConstant(Flag, dl, MVT::i32);
952 Ops.push_back(Res);
953
954 if (Code == InlineAsm::Kind_Clobber) {
955 // Clobbers should always have a 1:1 mapping with registers, and may
956 // reference registers that have illegal (e.g. vector) types. Hence, we
957 // shouldn't try to apply any sort of splitting logic to them.
958 assert(Regs.size() == RegVTs.size() && Regs.size() == ValueVTs.size() &&((Regs.size() == RegVTs.size() && Regs.size() == ValueVTs
.size() && "No 1:1 mapping from clobbers to regs?") ?
static_cast<void> (0) : __assert_fail ("Regs.size() == RegVTs.size() && Regs.size() == ValueVTs.size() && \"No 1:1 mapping from clobbers to regs?\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 959, __PRETTY_FUNCTION__))
959 "No 1:1 mapping from clobbers to regs?")((Regs.size() == RegVTs.size() && Regs.size() == ValueVTs
.size() && "No 1:1 mapping from clobbers to regs?") ?
static_cast<void> (0) : __assert_fail ("Regs.size() == RegVTs.size() && Regs.size() == ValueVTs.size() && \"No 1:1 mapping from clobbers to regs?\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 959, __PRETTY_FUNCTION__))
;
960 Register SP = TLI.getStackPointerRegisterToSaveRestore();
961 (void)SP;
962 for (unsigned I = 0, E = ValueVTs.size(); I != E; ++I) {
963 Ops.push_back(DAG.getRegister(Regs[I], RegVTs[I]));
964 assert((((Regs[I] != SP || DAG.getMachineFunction().getFrameInfo().hasOpaqueSPAdjustment
()) && "If we clobbered the stack pointer, MFI should know about it."
) ? static_cast<void> (0) : __assert_fail ("(Regs[I] != SP || DAG.getMachineFunction().getFrameInfo().hasOpaqueSPAdjustment()) && \"If we clobbered the stack pointer, MFI should know about it.\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 967, __PRETTY_FUNCTION__))
965 (Regs[I] != SP ||(((Regs[I] != SP || DAG.getMachineFunction().getFrameInfo().hasOpaqueSPAdjustment
()) && "If we clobbered the stack pointer, MFI should know about it."
) ? static_cast<void> (0) : __assert_fail ("(Regs[I] != SP || DAG.getMachineFunction().getFrameInfo().hasOpaqueSPAdjustment()) && \"If we clobbered the stack pointer, MFI should know about it.\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 967, __PRETTY_FUNCTION__))
966 DAG.getMachineFunction().getFrameInfo().hasOpaqueSPAdjustment()) &&(((Regs[I] != SP || DAG.getMachineFunction().getFrameInfo().hasOpaqueSPAdjustment
()) && "If we clobbered the stack pointer, MFI should know about it."
) ? static_cast<void> (0) : __assert_fail ("(Regs[I] != SP || DAG.getMachineFunction().getFrameInfo().hasOpaqueSPAdjustment()) && \"If we clobbered the stack pointer, MFI should know about it.\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 967, __PRETTY_FUNCTION__))
967 "If we clobbered the stack pointer, MFI should know about it.")(((Regs[I] != SP || DAG.getMachineFunction().getFrameInfo().hasOpaqueSPAdjustment
()) && "If we clobbered the stack pointer, MFI should know about it."
) ? static_cast<void> (0) : __assert_fail ("(Regs[I] != SP || DAG.getMachineFunction().getFrameInfo().hasOpaqueSPAdjustment()) && \"If we clobbered the stack pointer, MFI should know about it.\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 967, __PRETTY_FUNCTION__))
;
968 }
969 return;
970 }
971
972 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
973 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
974 MVT RegisterVT = RegVTs[Value];
975 for (unsigned i = 0; i != NumRegs; ++i) {
976 assert(Reg < Regs.size() && "Mismatch in # registers expected")((Reg < Regs.size() && "Mismatch in # registers expected"
) ? static_cast<void> (0) : __assert_fail ("Reg < Regs.size() && \"Mismatch in # registers expected\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 976, __PRETTY_FUNCTION__))
;
977 unsigned TheReg = Regs[Reg++];
978 Ops.push_back(DAG.getRegister(TheReg, RegisterVT));
979 }
980 }
981}
982
983SmallVector<std::pair<unsigned, unsigned>, 4>
984RegsForValue::getRegsAndSizes() const {
985 SmallVector<std::pair<unsigned, unsigned>, 4> OutVec;
986 unsigned I = 0;
987 for (auto CountAndVT : zip_first(RegCount, RegVTs)) {
988 unsigned RegCount = std::get<0>(CountAndVT);
989 MVT RegisterVT = std::get<1>(CountAndVT);
990 unsigned RegisterSize = RegisterVT.getSizeInBits();
991 for (unsigned E = I + RegCount; I != E; ++I)
992 OutVec.push_back(std::make_pair(Regs[I], RegisterSize));
993 }
994 return OutVec;
995}
996
997void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis *aa,
998 const TargetLibraryInfo *li) {
999 AA = aa;
1000 GFI = gfi;
1001 LibInfo = li;
1002 DL = &DAG.getDataLayout();
1003 Context = DAG.getContext();
1004 LPadToCallSiteMap.clear();
1005 SL->init(DAG.getTargetLoweringInfo(), TM, DAG.getDataLayout());
1006}
1007
1008void SelectionDAGBuilder::clear() {
1009 NodeMap.clear();
1010 UnusedArgNodeMap.clear();
1011 PendingLoads.clear();
1012 PendingExports.clear();
1013 PendingConstrainedFP.clear();
1014 PendingConstrainedFPStrict.clear();
1015 CurInst = nullptr;
1016 HasTailCall = false;
1017 SDNodeOrder = LowestSDNodeOrder;
1018 StatepointLowering.clear();
1019}
1020
1021void SelectionDAGBuilder::clearDanglingDebugInfo() {
1022 DanglingDebugInfoMap.clear();
1023}
1024
1025// Update DAG root to include dependencies on Pending chains.
1026SDValue SelectionDAGBuilder::updateRoot(SmallVectorImpl<SDValue> &Pending) {
1027 SDValue Root = DAG.getRoot();
1028
1029 if (Pending.empty())
1030 return Root;
1031
1032 // Add current root to PendingChains, unless we already indirectly
1033 // depend on it.
1034 if (Root.getOpcode() != ISD::EntryToken) {
1035 unsigned i = 0, e = Pending.size();
1036 for (; i != e; ++i) {
1037 assert(Pending[i].getNode()->getNumOperands() > 1)((Pending[i].getNode()->getNumOperands() > 1) ? static_cast
<void> (0) : __assert_fail ("Pending[i].getNode()->getNumOperands() > 1"
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 1037, __PRETTY_FUNCTION__))
;
1038 if (Pending[i].getNode()->getOperand(0) == Root)
1039 break; // Don't add the root if we already indirectly depend on it.
1040 }
1041
1042 if (i == e)
1043 Pending.push_back(Root);
1044 }
1045
1046 if (Pending.size() == 1)
1047 Root = Pending[0];
1048 else
1049 Root = DAG.getTokenFactor(getCurSDLoc(), Pending);
1050
1051 DAG.setRoot(Root);
1052 Pending.clear();
1053 return Root;
1054}
1055
1056SDValue SelectionDAGBuilder::getMemoryRoot() {
1057 return updateRoot(PendingLoads);
1058}
1059
1060SDValue SelectionDAGBuilder::getRoot() {
1061 // Chain up all pending constrained intrinsics together with all
1062 // pending loads, by simply appending them to PendingLoads and
1063 // then calling getMemoryRoot().
1064 PendingLoads.reserve(PendingLoads.size() +
1065 PendingConstrainedFP.size() +
1066 PendingConstrainedFPStrict.size());
1067 PendingLoads.append(PendingConstrainedFP.begin(),
1068 PendingConstrainedFP.end());
1069 PendingLoads.append(PendingConstrainedFPStrict.begin(),
1070 PendingConstrainedFPStrict.end());
1071 PendingConstrainedFP.clear();
1072 PendingConstrainedFPStrict.clear();
1073 return getMemoryRoot();
1074}
1075
1076SDValue SelectionDAGBuilder::getControlRoot() {
1077 // We need to emit pending fpexcept.strict constrained intrinsics,
1078 // so append them to the PendingExports list.
1079 PendingExports.append(PendingConstrainedFPStrict.begin(),
1080 PendingConstrainedFPStrict.end());
1081 PendingConstrainedFPStrict.clear();
1082 return updateRoot(PendingExports);
1083}
1084
1085void SelectionDAGBuilder::visit(const Instruction &I) {
1086 // Set up outgoing PHI node register values before emitting the terminator.
1087 if (I.isTerminator()) {
1088 HandlePHINodesInSuccessorBlocks(I.getParent());
1089 }
1090
1091 // Increase the SDNodeOrder if dealing with a non-debug instruction.
1092 if (!isa<DbgInfoIntrinsic>(I))
1093 ++SDNodeOrder;
1094
1095 CurInst = &I;
1096
1097 visit(I.getOpcode(), I);
1098
1099 if (!I.isTerminator() && !HasTailCall &&
1100 !isa<GCStatepointInst>(I)) // statepoints handle their exports internally
1101 CopyToExportRegsIfNeeded(&I);
1102
1103 CurInst = nullptr;
1104}
1105
1106void SelectionDAGBuilder::visitPHI(const PHINode &) {
1107 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!")::llvm::llvm_unreachable_internal("SelectionDAGBuilder shouldn't visit PHI nodes!"
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 1107)
;
1108}
1109
1110void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
1111 // Note: this doesn't use InstVisitor, because it has to work with
1112 // ConstantExpr's in addition to instructions.
1113 switch (Opcode) {
1114 default: llvm_unreachable("Unknown instruction type encountered!")::llvm::llvm_unreachable_internal("Unknown instruction type encountered!"
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 1114)
;
1115 // Build the switch statement using the Instruction.def file.
1116#define HANDLE_INST(NUM, OPCODE, CLASS) \
1117 case Instruction::OPCODE: visit##OPCODE((const CLASS&)I); break;
1118#include "llvm/IR/Instruction.def"
1119 }
1120}
1121
1122void SelectionDAGBuilder::dropDanglingDebugInfo(const DILocalVariable *Variable,
1123 const DIExpression *Expr) {
1124 auto isMatchingDbgValue = [&](DanglingDebugInfo &DDI) {
1125 const DbgValueInst *DI = DDI.getDI();
1126 DIVariable *DanglingVariable = DI->getVariable();
1127 DIExpression *DanglingExpr = DI->getExpression();
1128 if (DanglingVariable == Variable && Expr->fragmentsOverlap(DanglingExpr)) {
1129 LLVM_DEBUG(dbgs() << "Dropping dangling debug info for " << *DI << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << "Dropping dangling debug info for "
<< *DI << "\n"; } } while (false)
;
1130 return true;
1131 }
1132 return false;
1133 };
1134
1135 for (auto &DDIMI : DanglingDebugInfoMap) {
1136 DanglingDebugInfoVector &DDIV = DDIMI.second;
1137
1138 // If debug info is to be dropped, run it through final checks to see
1139 // whether it can be salvaged.
1140 for (auto &DDI : DDIV)
1141 if (isMatchingDbgValue(DDI))
1142 salvageUnresolvedDbgValue(DDI);
1143
1144 DDIV.erase(remove_if(DDIV, isMatchingDbgValue), DDIV.end());
1145 }
1146}
1147
1148// resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
1149// generate the debug data structures now that we've seen its definition.
1150void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V,
1151 SDValue Val) {
1152 auto DanglingDbgInfoIt = DanglingDebugInfoMap.find(V);
1153 if (DanglingDbgInfoIt == DanglingDebugInfoMap.end())
1154 return;
1155
1156 DanglingDebugInfoVector &DDIV = DanglingDbgInfoIt->second;
1157 for (auto &DDI : DDIV) {
1158 const DbgValueInst *DI = DDI.getDI();
1159 assert(DI && "Ill-formed DanglingDebugInfo")((DI && "Ill-formed DanglingDebugInfo") ? static_cast
<void> (0) : __assert_fail ("DI && \"Ill-formed DanglingDebugInfo\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 1159, __PRETTY_FUNCTION__))
;
1160 DebugLoc dl = DDI.getdl();
1161 unsigned ValSDNodeOrder = Val.getNode()->getIROrder();
1162 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder();
1163 DILocalVariable *Variable = DI->getVariable();
1164 DIExpression *Expr = DI->getExpression();
1165 assert(Variable->isValidLocationForIntrinsic(dl) &&((Variable->isValidLocationForIntrinsic(dl) && "Expected inlined-at fields to agree"
) ? static_cast<void> (0) : __assert_fail ("Variable->isValidLocationForIntrinsic(dl) && \"Expected inlined-at fields to agree\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 1166, __PRETTY_FUNCTION__))
1166 "Expected inlined-at fields to agree")((Variable->isValidLocationForIntrinsic(dl) && "Expected inlined-at fields to agree"
) ? static_cast<void> (0) : __assert_fail ("Variable->isValidLocationForIntrinsic(dl) && \"Expected inlined-at fields to agree\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 1166, __PRETTY_FUNCTION__))
;
1167 SDDbgValue *SDV;
1168 if (Val.getNode()) {
1169 // FIXME: I doubt that it is correct to resolve a dangling DbgValue as a
1170 // FuncArgumentDbgValue (it would be hoisted to the function entry, and if
1171 // we couldn't resolve it directly when examining the DbgValue intrinsic
1172 // in the first place we should not be more successful here). Unless we
1173 // have some test case that prove this to be correct we should avoid
1174 // calling EmitFuncArgumentDbgValue here.
1175 if (!EmitFuncArgumentDbgValue(V, Variable, Expr, dl, false, Val)) {
1176 LLVM_DEBUG(dbgs() << "Resolve dangling debug info [order="do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << "Resolve dangling debug info [order="
<< DbgSDNodeOrder << "] for:\n " << *DI <<
"\n"; } } while (false)
1177 << DbgSDNodeOrder << "] for:\n " << *DI << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << "Resolve dangling debug info [order="
<< DbgSDNodeOrder << "] for:\n " << *DI <<
"\n"; } } while (false)
;
1178 LLVM_DEBUG(dbgs() << " By mapping to:\n "; Val.dump())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << " By mapping to:\n "; Val.dump
(); } } while (false)
;
1179 // Increase the SDNodeOrder for the DbgValue here to make sure it is
1180 // inserted after the definition of Val when emitting the instructions
1181 // after ISel. An alternative could be to teach
1182 // ScheduleDAGSDNodes::EmitSchedule to delay the insertion properly.
1183 LLVM_DEBUG(if (ValSDNodeOrder > DbgSDNodeOrder) dbgs()do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { if (ValSDNodeOrder > DbgSDNodeOrder) dbgs() <<
"changing SDNodeOrder from " << DbgSDNodeOrder <<
" to " << ValSDNodeOrder << "\n"; } } while (false
)
1184 << "changing SDNodeOrder from " << DbgSDNodeOrder << " to "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { if (ValSDNodeOrder > DbgSDNodeOrder) dbgs() <<
"changing SDNodeOrder from " << DbgSDNodeOrder <<
" to " << ValSDNodeOrder << "\n"; } } while (false
)
1185 << ValSDNodeOrder << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { if (ValSDNodeOrder > DbgSDNodeOrder) dbgs() <<
"changing SDNodeOrder from " << DbgSDNodeOrder <<
" to " << ValSDNodeOrder << "\n"; } } while (false
)
;
1186 SDV = getDbgValue(Val, Variable, Expr, dl,
1187 std::max(DbgSDNodeOrder, ValSDNodeOrder));
1188 DAG.AddDbgValue(SDV, Val.getNode(), false);
1189 } else
1190 LLVM_DEBUG(dbgs() << "Resolved dangling debug info for " << *DIdo { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << "Resolved dangling debug info for "
<< *DI << "in EmitFuncArgumentDbgValue\n"; } } while
(false)
1191 << "in EmitFuncArgumentDbgValue\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << "Resolved dangling debug info for "
<< *DI << "in EmitFuncArgumentDbgValue\n"; } } while
(false)
;
1192 } else {
1193 LLVM_DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << "Dropping debug info for " <<
*DI << "\n"; } } while (false)
;
1194 auto Undef =
1195 UndefValue::get(DDI.getDI()->getVariableLocation()->getType());
1196 auto SDV =
1197 DAG.getConstantDbgValue(Variable, Expr, Undef, dl, DbgSDNodeOrder);
1198 DAG.AddDbgValue(SDV, nullptr, false);
1199 }
1200 }
1201 DDIV.clear();
1202}
1203
1204void SelectionDAGBuilder::salvageUnresolvedDbgValue(DanglingDebugInfo &DDI) {
1205 Value *V = DDI.getDI()->getValue();
1206 DILocalVariable *Var = DDI.getDI()->getVariable();
1207 DIExpression *Expr = DDI.getDI()->getExpression();
1208 DebugLoc DL = DDI.getdl();
1209 DebugLoc InstDL = DDI.getDI()->getDebugLoc();
1210 unsigned SDOrder = DDI.getSDNodeOrder();
1211
1212 // Currently we consider only dbg.value intrinsics -- we tell the salvager
1213 // that DW_OP_stack_value is desired.
1214 assert(isa<DbgValueInst>(DDI.getDI()))((isa<DbgValueInst>(DDI.getDI())) ? static_cast<void
> (0) : __assert_fail ("isa<DbgValueInst>(DDI.getDI())"
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 1214, __PRETTY_FUNCTION__))
;
1215 bool StackValue = true;
1216
1217 // Can this Value can be encoded without any further work?
1218 if (handleDebugValue(V, Var, Expr, DL, InstDL, SDOrder))
1219 return;
1220
1221 // Attempt to salvage back through as many instructions as possible. Bail if
1222 // a non-instruction is seen, such as a constant expression or global
1223 // variable. FIXME: Further work could recover those too.
1224 while (isa<Instruction>(V)) {
1225 Instruction &VAsInst = *cast<Instruction>(V);
1226 DIExpression *NewExpr = salvageDebugInfoImpl(VAsInst, Expr, StackValue);
1227
1228 // If we cannot salvage any further, and haven't yet found a suitable debug
1229 // expression, bail out.
1230 if (!NewExpr)
1231 break;
1232
1233 // New value and expr now represent this debuginfo.
1234 V = VAsInst.getOperand(0);
1235 Expr = NewExpr;
1236
1237 // Some kind of simplification occurred: check whether the operand of the
1238 // salvaged debug expression can be encoded in this DAG.
1239 if (handleDebugValue(V, Var, Expr, DL, InstDL, SDOrder)) {
1240 LLVM_DEBUG(dbgs() << "Salvaged debug location info for:\n "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << "Salvaged debug location info for:\n "
<< DDI.getDI() << "\nBy stripping back to:\n " <<
V; } } while (false)
1241 << DDI.getDI() << "\nBy stripping back to:\n " << V)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << "Salvaged debug location info for:\n "
<< DDI.getDI() << "\nBy stripping back to:\n " <<
V; } } while (false)
;
1242 return;
1243 }
1244 }
1245
1246 // This was the final opportunity to salvage this debug information, and it
1247 // couldn't be done. Place an undef DBG_VALUE at this location to terminate
1248 // any earlier variable location.
1249 auto Undef = UndefValue::get(DDI.getDI()->getVariableLocation()->getType());
1250 auto SDV = DAG.getConstantDbgValue(Var, Expr, Undef, DL, SDNodeOrder);
1251 DAG.AddDbgValue(SDV, nullptr, false);
1252
1253 LLVM_DEBUG(dbgs() << "Dropping debug value info for:\n " << DDI.getDI()do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << "Dropping debug value info for:\n "
<< DDI.getDI() << "\n"; } } while (false)
1254 << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << "Dropping debug value info for:\n "
<< DDI.getDI() << "\n"; } } while (false)
;
1255 LLVM_DEBUG(dbgs() << " Last seen at:\n " << *DDI.getDI()->getOperand(0)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << " Last seen at:\n " << *
DDI.getDI()->getOperand(0) << "\n"; } } while (false
)
1256 << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << " Last seen at:\n " << *
DDI.getDI()->getOperand(0) << "\n"; } } while (false
)
;
1257}
1258
1259bool SelectionDAGBuilder::handleDebugValue(const Value *V, DILocalVariable *Var,
1260 DIExpression *Expr, DebugLoc dl,
1261 DebugLoc InstDL, unsigned Order) {
1262 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1263 SDDbgValue *SDV;
1264 if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V) ||
1265 isa<ConstantPointerNull>(V)) {
1266 SDV = DAG.getConstantDbgValue(Var, Expr, V, dl, SDNodeOrder);
1267 DAG.AddDbgValue(SDV, nullptr, false);
1268 return true;
1269 }
1270
1271 // If the Value is a frame index, we can create a FrameIndex debug value
1272 // without relying on the DAG at all.
1273 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1274 auto SI = FuncInfo.StaticAllocaMap.find(AI);
1275 if (SI != FuncInfo.StaticAllocaMap.end()) {
1276 auto SDV =
1277 DAG.getFrameIndexDbgValue(Var, Expr, SI->second,
1278 /*IsIndirect*/ false, dl, SDNodeOrder);
1279 // Do not attach the SDNodeDbgValue to an SDNode: this variable location
1280 // is still available even if the SDNode gets optimized out.
1281 DAG.AddDbgValue(SDV, nullptr, false);
1282 return true;
1283 }
1284 }
1285
1286 // Do not use getValue() in here; we don't want to generate code at
1287 // this point if it hasn't been done yet.
1288 SDValue N = NodeMap[V];
1289 if (!N.getNode() && isa<Argument>(V)) // Check unused arguments map.
1290 N = UnusedArgNodeMap[V];
1291 if (N.getNode()) {
1292 if (EmitFuncArgumentDbgValue(V, Var, Expr, dl, false, N))
1293 return true;
1294 SDV = getDbgValue(N, Var, Expr, dl, SDNodeOrder);
1295 DAG.AddDbgValue(SDV, N.getNode(), false);
1296 return true;
1297 }
1298
1299 // Special rules apply for the first dbg.values of parameter variables in a
1300 // function. Identify them by the fact they reference Argument Values, that
1301 // they're parameters, and they are parameters of the current function. We
1302 // need to let them dangle until they get an SDNode.
1303 bool IsParamOfFunc = isa<Argument>(V) && Var->isParameter() &&
1304 !InstDL.getInlinedAt();
1305 if (!IsParamOfFunc) {
1306 // The value is not used in this block yet (or it would have an SDNode).
1307 // We still want the value to appear for the user if possible -- if it has
1308 // an associated VReg, we can refer to that instead.
1309 auto VMI = FuncInfo.ValueMap.find(V);
1310 if (VMI != FuncInfo.ValueMap.end()) {
1311 unsigned Reg = VMI->second;
1312 // If this is a PHI node, it may be split up into several MI PHI nodes
1313 // (in FunctionLoweringInfo::set).
1314 RegsForValue RFV(V->getContext(), TLI, DAG.getDataLayout(), Reg,
1315 V->getType(), None);
1316 if (RFV.occupiesMultipleRegs()) {
1317 unsigned Offset = 0;
1318 unsigned BitsToDescribe = 0;
1319 if (auto VarSize = Var->getSizeInBits())
1320 BitsToDescribe = *VarSize;
1321 if (auto Fragment = Expr->getFragmentInfo())
1322 BitsToDescribe = Fragment->SizeInBits;
1323 for (auto RegAndSize : RFV.getRegsAndSizes()) {
1324 unsigned RegisterSize = RegAndSize.second;
1325 // Bail out if all bits are described already.
1326 if (Offset >= BitsToDescribe)
1327 break;
1328 unsigned FragmentSize = (Offset + RegisterSize > BitsToDescribe)
1329 ? BitsToDescribe - Offset
1330 : RegisterSize;
1331 auto FragmentExpr = DIExpression::createFragmentExpression(
1332 Expr, Offset, FragmentSize);
1333 if (!FragmentExpr)
1334 continue;
1335 SDV = DAG.getVRegDbgValue(Var, *FragmentExpr, RegAndSize.first,
1336 false, dl, SDNodeOrder);
1337 DAG.AddDbgValue(SDV, nullptr, false);
1338 Offset += RegisterSize;
1339 }
1340 } else {
1341 SDV = DAG.getVRegDbgValue(Var, Expr, Reg, false, dl, SDNodeOrder);
1342 DAG.AddDbgValue(SDV, nullptr, false);
1343 }
1344 return true;
1345 }
1346 }
1347
1348 return false;
1349}
1350
1351void SelectionDAGBuilder::resolveOrClearDbgInfo() {
1352 // Try to fixup any remaining dangling debug info -- and drop it if we can't.
1353 for (auto &Pair : DanglingDebugInfoMap)
1354 for (auto &DDI : Pair.second)
1355 salvageUnresolvedDbgValue(DDI);
1356 clearDanglingDebugInfo();
1357}
1358
1359/// getCopyFromRegs - If there was virtual register allocated for the value V
1360/// emit CopyFromReg of the specified type Ty. Return empty SDValue() otherwise.
1361SDValue SelectionDAGBuilder::getCopyFromRegs(const Value *V, Type *Ty) {
1362 DenseMap<const Value *, Register>::iterator It = FuncInfo.ValueMap.find(V);
1363 SDValue Result;
1364
1365 if (It != FuncInfo.ValueMap.end()) {
1366 Register InReg = It->second;
1367
1368 RegsForValue RFV(*DAG.getContext(), DAG.getTargetLoweringInfo(),
1369 DAG.getDataLayout(), InReg, Ty,
1370 None); // This is not an ABI copy.
1371 SDValue Chain = DAG.getEntryNode();
1372 Result = RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr,
1373 V);
1374 resolveDanglingDebugInfo(V, Result);
1375 }
1376
1377 return Result;
1378}
1379
1380/// getValue - Return an SDValue for the given Value.
1381SDValue SelectionDAGBuilder::getValue(const Value *V) {
1382 // If we already have an SDValue for this value, use it. It's important
1383 // to do this first, so that we don't create a CopyFromReg if we already
1384 // have a regular SDValue.
1385 SDValue &N = NodeMap[V];
1386 if (N.getNode()) return N;
1387
1388 // If there's a virtual register allocated and initialized for this
1389 // value, use it.
1390 if (SDValue copyFromReg = getCopyFromRegs(V, V->getType()))
1391 return copyFromReg;
1392
1393 // Otherwise create a new SDValue and remember it.
1394 SDValue Val = getValueImpl(V);
1395 NodeMap[V] = Val;
1396 resolveDanglingDebugInfo(V, Val);
1397 return Val;
1398}
1399
1400/// getNonRegisterValue - Return an SDValue for the given Value, but
1401/// don't look in FuncInfo.ValueMap for a virtual register.
1402SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) {
1403 // If we already have an SDValue for this value, use it.
1404 SDValue &N = NodeMap[V];
1405 if (N.getNode()) {
1406 if (isa<ConstantSDNode>(N) || isa<ConstantFPSDNode>(N)) {
1407 // Remove the debug location from the node as the node is about to be used
1408 // in a location which may differ from the original debug location. This
1409 // is relevant to Constant and ConstantFP nodes because they can appear
1410 // as constant expressions inside PHI nodes.
1411 N->setDebugLoc(DebugLoc());
1412 }
1413 return N;
1414 }
1415
1416 // Otherwise create a new SDValue and remember it.
1417 SDValue Val = getValueImpl(V);
1418 NodeMap[V] = Val;
1419 resolveDanglingDebugInfo(V, Val);
1420 return Val;
1421}
1422
1423/// getValueImpl - Helper function for getValue and getNonRegisterValue.
1424/// Create an SDValue for the given value.
1425SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
1426 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1427
1428 if (const Constant *C = dyn_cast<Constant>(V)) {
1429 EVT VT = TLI.getValueType(DAG.getDataLayout(), V->getType(), true);
1430
1431 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
1432 return DAG.getConstant(*CI, getCurSDLoc(), VT);
1433
1434 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
1435 return DAG.getGlobalAddress(GV, getCurSDLoc(), VT);
1436
1437 if (isa<ConstantPointerNull>(C)) {
1438 unsigned AS = V->getType()->getPointerAddressSpace();
1439 return DAG.getConstant(0, getCurSDLoc(),
1440 TLI.getPointerTy(DAG.getDataLayout(), AS));
1441 }
1442
1443 if (match(C, m_VScale(DAG.getDataLayout())))
1444 return DAG.getVScale(getCurSDLoc(), VT, APInt(VT.getSizeInBits(), 1));
1445
1446 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
1447 return DAG.getConstantFP(*CFP, getCurSDLoc(), VT);
1448
1449 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
1450 return DAG.getUNDEF(VT);
1451
1452 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
1453 visit(CE->getOpcode(), *CE);
1454 SDValue N1 = NodeMap[V];
1455 assert(N1.getNode() && "visit didn't populate the NodeMap!")((N1.getNode() && "visit didn't populate the NodeMap!"
) ? static_cast<void> (0) : __assert_fail ("N1.getNode() && \"visit didn't populate the NodeMap!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 1455, __PRETTY_FUNCTION__))
;
1456 return N1;
1457 }
1458
1459 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
1460 SmallVector<SDValue, 4> Constants;
1461 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
1462 OI != OE; ++OI) {
1463 SDNode *Val = getValue(*OI).getNode();
1464 // If the operand is an empty aggregate, there are no values.
1465 if (!Val) continue;
1466 // Add each leaf value from the operand to the Constants list
1467 // to form a flattened list of all the values.
1468 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1469 Constants.push_back(SDValue(Val, i));
1470 }
1471
1472 return DAG.getMergeValues(Constants, getCurSDLoc());
1473 }
1474
1475 if (const ConstantDataSequential *CDS =
1476 dyn_cast<ConstantDataSequential>(C)) {
1477 SmallVector<SDValue, 4> Ops;
1478 for (unsigned i = 0, e = CDS->getNumElements(); i != e; ++i) {
1479 SDNode *Val = getValue(CDS->getElementAsConstant(i)).getNode();
1480 // Add each leaf value from the operand to the Constants list
1481 // to form a flattened list of all the values.
1482 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1483 Ops.push_back(SDValue(Val, i));
1484 }
1485
1486 if (isa<ArrayType>(CDS->getType()))
1487 return DAG.getMergeValues(Ops, getCurSDLoc());
1488 return NodeMap[V] = DAG.getBuildVector(VT, getCurSDLoc(), Ops);
1489 }
1490
1491 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
1492 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&(((isa<ConstantAggregateZero>(C) || isa<UndefValue>
(C)) && "Unknown struct or array constant!") ? static_cast
<void> (0) : __assert_fail ("(isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) && \"Unknown struct or array constant!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 1493, __PRETTY_FUNCTION__))
1493 "Unknown struct or array constant!")(((isa<ConstantAggregateZero>(C) || isa<UndefValue>
(C)) && "Unknown struct or array constant!") ? static_cast
<void> (0) : __assert_fail ("(isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) && \"Unknown struct or array constant!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 1493, __PRETTY_FUNCTION__))
;
1494
1495 SmallVector<EVT, 4> ValueVTs;
1496 ComputeValueVTs(TLI, DAG.getDataLayout(), C->getType(), ValueVTs);
1497 unsigned NumElts = ValueVTs.size();
1498 if (NumElts == 0)
1499 return SDValue(); // empty struct
1500 SmallVector<SDValue, 4> Constants(NumElts);
1501 for (unsigned i = 0; i != NumElts; ++i) {
1502 EVT EltVT = ValueVTs[i];
1503 if (isa<UndefValue>(C))
1504 Constants[i] = DAG.getUNDEF(EltVT);
1505 else if (EltVT.isFloatingPoint())
1506 Constants[i] = DAG.getConstantFP(0, getCurSDLoc(), EltVT);
1507 else
1508 Constants[i] = DAG.getConstant(0, getCurSDLoc(), EltVT);
1509 }
1510
1511 return DAG.getMergeValues(Constants, getCurSDLoc());
1512 }
1513
1514 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C))
1515 return DAG.getBlockAddress(BA, VT);
1516
1517 if (const auto *Equiv = dyn_cast<DSOLocalEquivalent>(C))
1518 return getValue(Equiv->getGlobalValue());
1519
1520 VectorType *VecTy = cast<VectorType>(V->getType());
1521
1522 // Now that we know the number and type of the elements, get that number of
1523 // elements into the Ops array based on what kind of constant it is.
1524 if (const ConstantVector *CV = dyn_cast<ConstantVector>(C)) {
1525 SmallVector<SDValue, 16> Ops;
1526 unsigned NumElements = cast<FixedVectorType>(VecTy)->getNumElements();
1527 for (unsigned i = 0; i != NumElements; ++i)
1528 Ops.push_back(getValue(CV->getOperand(i)));
1529
1530 return NodeMap[V] = DAG.getBuildVector(VT, getCurSDLoc(), Ops);
1531 } else if (isa<ConstantAggregateZero>(C)) {
1532 EVT EltVT =
1533 TLI.getValueType(DAG.getDataLayout(), VecTy->getElementType());
1534
1535 SDValue Op;
1536 if (EltVT.isFloatingPoint())
1537 Op = DAG.getConstantFP(0, getCurSDLoc(), EltVT);
1538 else
1539 Op = DAG.getConstant(0, getCurSDLoc(), EltVT);
1540
1541 if (isa<ScalableVectorType>(VecTy))
1542 return NodeMap[V] = DAG.getSplatVector(VT, getCurSDLoc(), Op);
1543 else {
1544 SmallVector<SDValue, 16> Ops;
1545 Ops.assign(cast<FixedVectorType>(VecTy)->getNumElements(), Op);
1546 return NodeMap[V] = DAG.getBuildVector(VT, getCurSDLoc(), Ops);
1547 }
1548 }
1549 llvm_unreachable("Unknown vector constant")::llvm::llvm_unreachable_internal("Unknown vector constant", "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 1549)
;
1550 }
1551
1552 // If this is a static alloca, generate it as the frameindex instead of
1553 // computation.
1554 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1555 DenseMap<const AllocaInst*, int>::iterator SI =
1556 FuncInfo.StaticAllocaMap.find(AI);
1557 if (SI != FuncInfo.StaticAllocaMap.end())
1558 return DAG.getFrameIndex(SI->second,
1559 TLI.getFrameIndexTy(DAG.getDataLayout()));
1560 }
1561
1562 // If this is an instruction which fast-isel has deferred, select it now.
1563 if (const Instruction *Inst = dyn_cast<Instruction>(V)) {
1564 unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
1565
1566 RegsForValue RFV(*DAG.getContext(), TLI, DAG.getDataLayout(), InReg,
1567 Inst->getType(), None);
1568 SDValue Chain = DAG.getEntryNode();
1569 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
1570 }
1571
1572 if (const MetadataAsValue *MD = dyn_cast<MetadataAsValue>(V)) {
1573 return DAG.getMDNode(cast<MDNode>(MD->getMetadata()));
1574 }
1575 llvm_unreachable("Can't get register for value!")::llvm::llvm_unreachable_internal("Can't get register for value!"
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 1575)
;
1576}
1577
1578void SelectionDAGBuilder::visitCatchPad(const CatchPadInst &I) {
1579 auto Pers = classifyEHPersonality(FuncInfo.Fn->getPersonalityFn());
1580 bool IsMSVCCXX = Pers == EHPersonality::MSVC_CXX;
1581 bool IsCoreCLR = Pers == EHPersonality::CoreCLR;
1582 bool IsSEH = isAsynchronousEHPersonality(Pers);
1583 MachineBasicBlock *CatchPadMBB = FuncInfo.MBB;
1584 if (!IsSEH)
1585 CatchPadMBB->setIsEHScopeEntry();
1586 // In MSVC C++ and CoreCLR, catchblocks are funclets and need prologues.
1587 if (IsMSVCCXX || IsCoreCLR)
1588 CatchPadMBB->setIsEHFuncletEntry();
1589}
1590
1591void SelectionDAGBuilder::visitCatchRet(const CatchReturnInst &I) {
1592 // Update machine-CFG edge.
1593 MachineBasicBlock *TargetMBB = FuncInfo.MBBMap[I.getSuccessor()];
1594 FuncInfo.MBB->addSuccessor(TargetMBB);
1595
1596 auto Pers = classifyEHPersonality(FuncInfo.Fn->getPersonalityFn());
1597 bool IsSEH = isAsynchronousEHPersonality(Pers);
1598 if (IsSEH) {
1599 // If this is not a fall-through branch or optimizations are switched off,
1600 // emit the branch.
1601 if (TargetMBB != NextBlock(FuncInfo.MBB) ||
1602 TM.getOptLevel() == CodeGenOpt::None)
1603 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other,
1604 getControlRoot(), DAG.getBasicBlock(TargetMBB)));
1605 return;
1606 }
1607
1608 // Figure out the funclet membership for the catchret's successor.
1609 // This will be used by the FuncletLayout pass to determine how to order the
1610 // BB's.
1611 // A 'catchret' returns to the outer scope's color.
1612 Value *ParentPad = I.getCatchSwitchParentPad();
1613 const BasicBlock *SuccessorColor;
1614 if (isa<ConstantTokenNone>(ParentPad))
1615 SuccessorColor = &FuncInfo.Fn->getEntryBlock();
1616 else
1617 SuccessorColor = cast<Instruction>(ParentPad)->getParent();
1618 assert(SuccessorColor && "No parent funclet for catchret!")((SuccessorColor && "No parent funclet for catchret!"
) ? static_cast<void> (0) : __assert_fail ("SuccessorColor && \"No parent funclet for catchret!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 1618, __PRETTY_FUNCTION__))
;
1619 MachineBasicBlock *SuccessorColorMBB = FuncInfo.MBBMap[SuccessorColor];
1620 assert(SuccessorColorMBB && "No MBB for SuccessorColor!")((SuccessorColorMBB && "No MBB for SuccessorColor!") ?
static_cast<void> (0) : __assert_fail ("SuccessorColorMBB && \"No MBB for SuccessorColor!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 1620, __PRETTY_FUNCTION__))
;
1621
1622 // Create the terminator node.
1623 SDValue Ret = DAG.getNode(ISD::CATCHRET, getCurSDLoc(), MVT::Other,
1624 getControlRoot(), DAG.getBasicBlock(TargetMBB),
1625 DAG.getBasicBlock(SuccessorColorMBB));
1626 DAG.setRoot(Ret);
1627}
1628
1629void SelectionDAGBuilder::visitCleanupPad(const CleanupPadInst &CPI) {
1630 // Don't emit any special code for the cleanuppad instruction. It just marks
1631 // the start of an EH scope/funclet.
1632 FuncInfo.MBB->setIsEHScopeEntry();
1633 auto Pers = classifyEHPersonality(FuncInfo.Fn->getPersonalityFn());
1634 if (Pers != EHPersonality::Wasm_CXX) {
1635 FuncInfo.MBB->setIsEHFuncletEntry();
1636 FuncInfo.MBB->setIsCleanupFuncletEntry();
1637 }
1638}
1639
1640// For wasm, there's alwyas a single catch pad attached to a catchswitch, and
1641// the control flow always stops at the single catch pad, as it does for a
1642// cleanup pad. In case the exception caught is not of the types the catch pad
1643// catches, it will be rethrown by a rethrow.
1644static void findWasmUnwindDestinations(
1645 FunctionLoweringInfo &FuncInfo, const BasicBlock *EHPadBB,
1646 BranchProbability Prob,
1647 SmallVectorImpl<std::pair<MachineBasicBlock *, BranchProbability>>
1648 &UnwindDests) {
1649 while (EHPadBB) {
1650 const Instruction *Pad = EHPadBB->getFirstNonPHI();
1651 if (isa<CleanupPadInst>(Pad)) {
1652 // Stop on cleanup pads.
1653 UnwindDests.emplace_back(FuncInfo.MBBMap[EHPadBB], Prob);
1654 UnwindDests.back().first->setIsEHScopeEntry();
1655 break;
1656 } else if (auto *CatchSwitch = dyn_cast<CatchSwitchInst>(Pad)) {
1657 // Add the catchpad handlers to the possible destinations. We don't
1658 // continue to the unwind destination of the catchswitch for wasm.
1659 for (const BasicBlock *CatchPadBB : CatchSwitch->handlers()) {
1660 UnwindDests.emplace_back(FuncInfo.MBBMap[CatchPadBB], Prob);
1661 UnwindDests.back().first->setIsEHScopeEntry();
1662 }
1663 break;
1664 } else {
1665 continue;
1666 }
1667 }
1668}
1669
1670/// When an invoke or a cleanupret unwinds to the next EH pad, there are
1671/// many places it could ultimately go. In the IR, we have a single unwind
1672/// destination, but in the machine CFG, we enumerate all the possible blocks.
1673/// This function skips over imaginary basic blocks that hold catchswitch
1674/// instructions, and finds all the "real" machine
1675/// basic block destinations. As those destinations may not be successors of
1676/// EHPadBB, here we also calculate the edge probability to those destinations.
1677/// The passed-in Prob is the edge probability to EHPadBB.
1678static void findUnwindDestinations(
1679 FunctionLoweringInfo &FuncInfo, const BasicBlock *EHPadBB,
1680 BranchProbability Prob,
1681 SmallVectorImpl<std::pair<MachineBasicBlock *, BranchProbability>>
1682 &UnwindDests) {
1683 EHPersonality Personality =
1684 classifyEHPersonality(FuncInfo.Fn->getPersonalityFn());
1685 bool IsMSVCCXX = Personality == EHPersonality::MSVC_CXX;
1686 bool IsCoreCLR = Personality == EHPersonality::CoreCLR;
1687 bool IsWasmCXX = Personality == EHPersonality::Wasm_CXX;
1688 bool IsSEH = isAsynchronousEHPersonality(Personality);
1689
1690 if (IsWasmCXX) {
1691 findWasmUnwindDestinations(FuncInfo, EHPadBB, Prob, UnwindDests);
1692 assert(UnwindDests.size() <= 1 &&((UnwindDests.size() <= 1 && "There should be at most one unwind destination for wasm"
) ? static_cast<void> (0) : __assert_fail ("UnwindDests.size() <= 1 && \"There should be at most one unwind destination for wasm\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 1693, __PRETTY_FUNCTION__))
1693 "There should be at most one unwind destination for wasm")((UnwindDests.size() <= 1 && "There should be at most one unwind destination for wasm"
) ? static_cast<void> (0) : __assert_fail ("UnwindDests.size() <= 1 && \"There should be at most one unwind destination for wasm\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 1693, __PRETTY_FUNCTION__))
;
1694 return;
1695 }
1696
1697 while (EHPadBB) {
1698 const Instruction *Pad = EHPadBB->getFirstNonPHI();
1699 BasicBlock *NewEHPadBB = nullptr;
1700 if (isa<LandingPadInst>(Pad)) {
1701 // Stop on landingpads. They are not funclets.
1702 UnwindDests.emplace_back(FuncInfo.MBBMap[EHPadBB], Prob);
1703 break;
1704 } else if (isa<CleanupPadInst>(Pad)) {
1705 // Stop on cleanup pads. Cleanups are always funclet entries for all known
1706 // personalities.
1707 UnwindDests.emplace_back(FuncInfo.MBBMap[EHPadBB], Prob);
1708 UnwindDests.back().first->setIsEHScopeEntry();
1709 UnwindDests.back().first->setIsEHFuncletEntry();
1710 break;
1711 } else if (auto *CatchSwitch = dyn_cast<CatchSwitchInst>(Pad)) {
1712 // Add the catchpad handlers to the possible destinations.
1713 for (const BasicBlock *CatchPadBB : CatchSwitch->handlers()) {
1714 UnwindDests.emplace_back(FuncInfo.MBBMap[CatchPadBB], Prob);
1715 // For MSVC++ and the CLR, catchblocks are funclets and need prologues.
1716 if (IsMSVCCXX || IsCoreCLR)
1717 UnwindDests.back().first->setIsEHFuncletEntry();
1718 if (!IsSEH)
1719 UnwindDests.back().first->setIsEHScopeEntry();
1720 }
1721 NewEHPadBB = CatchSwitch->getUnwindDest();
1722 } else {
1723 continue;
1724 }
1725
1726 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1727 if (BPI && NewEHPadBB)
1728 Prob *= BPI->getEdgeProbability(EHPadBB, NewEHPadBB);
1729 EHPadBB = NewEHPadBB;
1730 }
1731}
1732
1733void SelectionDAGBuilder::visitCleanupRet(const CleanupReturnInst &I) {
1734 // Update successor info.
1735 SmallVector<std::pair<MachineBasicBlock *, BranchProbability>, 1> UnwindDests;
1736 auto UnwindDest = I.getUnwindDest();
1737 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1738 BranchProbability UnwindDestProb =
1739 (BPI && UnwindDest)
1740 ? BPI->getEdgeProbability(FuncInfo.MBB->getBasicBlock(), UnwindDest)
1741 : BranchProbability::getZero();
1742 findUnwindDestinations(FuncInfo, UnwindDest, UnwindDestProb, UnwindDests);
1743 for (auto &UnwindDest : UnwindDests) {
1744 UnwindDest.first->setIsEHPad();
1745 addSuccessorWithProb(FuncInfo.MBB, UnwindDest.first, UnwindDest.second);
1746 }
1747 FuncInfo.MBB->normalizeSuccProbs();
1748
1749 // Create the terminator node.
1750 SDValue Ret =
1751 DAG.getNode(ISD::CLEANUPRET, getCurSDLoc(), MVT::Other, getControlRoot());
1752 DAG.setRoot(Ret);
1753}
1754
1755void SelectionDAGBuilder::visitCatchSwitch(const CatchSwitchInst &CSI) {
1756 report_fatal_error("visitCatchSwitch not yet implemented!");
1757}
1758
1759void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
1760 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1761 auto &DL = DAG.getDataLayout();
1762 SDValue Chain = getControlRoot();
1763 SmallVector<ISD::OutputArg, 8> Outs;
1764 SmallVector<SDValue, 8> OutVals;
1765
1766 // Calls to @llvm.experimental.deoptimize don't generate a return value, so
1767 // lower
1768 //
1769 // %val = call <ty> @llvm.experimental.deoptimize()
1770 // ret <ty> %val
1771 //
1772 // differently.
1773 if (I.getParent()->getTerminatingDeoptimizeCall()) {
1774 LowerDeoptimizingReturn();
1775 return;
1776 }
1777
1778 if (!FuncInfo.CanLowerReturn) {
1779 unsigned DemoteReg = FuncInfo.DemoteRegister;
1780 const Function *F = I.getParent()->getParent();
1781
1782 // Emit a store of the return value through the virtual register.
1783 // Leave Outs empty so that LowerReturn won't try to load return
1784 // registers the usual way.
1785 SmallVector<EVT, 1> PtrValueVTs;
1786 ComputeValueVTs(TLI, DL,
1787 F->getReturnType()->getPointerTo(
1788 DAG.getDataLayout().getAllocaAddrSpace()),
1789 PtrValueVTs);
1790
1791 SDValue RetPtr = DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(),
1792 DemoteReg, PtrValueVTs[0]);
1793 SDValue RetOp = getValue(I.getOperand(0));
1794
1795 SmallVector<EVT, 4> ValueVTs, MemVTs;
1796 SmallVector<uint64_t, 4> Offsets;
1797 ComputeValueVTs(TLI, DL, I.getOperand(0)->getType(), ValueVTs, &MemVTs,
1798 &Offsets);
1799 unsigned NumValues = ValueVTs.size();
1800
1801 SmallVector<SDValue, 4> Chains(NumValues);
1802 Align BaseAlign = DL.getPrefTypeAlign(I.getOperand(0)->getType());
1803 for (unsigned i = 0; i != NumValues; ++i) {
1804 // An aggregate return value cannot wrap around the address space, so
1805 // offsets to its parts don't wrap either.
1806 SDValue Ptr = DAG.getObjectPtrOffset(getCurSDLoc(), RetPtr,
1807 TypeSize::Fixed(Offsets[i]));
1808
1809 SDValue Val = RetOp.getValue(RetOp.getResNo() + i);
1810 if (MemVTs[i] != ValueVTs[i])
1811 Val = DAG.getPtrExtOrTrunc(Val, getCurSDLoc(), MemVTs[i]);
1812 Chains[i] = DAG.getStore(
1813 Chain, getCurSDLoc(), Val,
1814 // FIXME: better loc info would be nice.
1815 Ptr, MachinePointerInfo::getUnknownStack(DAG.getMachineFunction()),
1816 commonAlignment(BaseAlign, Offsets[i]));
1817 }
1818
1819 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
1820 MVT::Other, Chains);
1821 } else if (I.getNumOperands() != 0) {
1822 SmallVector<EVT, 4> ValueVTs;
1823 ComputeValueVTs(TLI, DL, I.getOperand(0)->getType(), ValueVTs);
1824 unsigned NumValues = ValueVTs.size();
1825 if (NumValues) {
1826 SDValue RetOp = getValue(I.getOperand(0));
1827
1828 const Function *F = I.getParent()->getParent();
1829
1830 bool NeedsRegBlock = TLI.functionArgumentNeedsConsecutiveRegisters(
1831 I.getOperand(0)->getType(), F->getCallingConv(),
1832 /*IsVarArg*/ false);
1833
1834 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1835 if (F->getAttributes().hasAttribute(AttributeList::ReturnIndex,
1836 Attribute::SExt))
1837 ExtendKind = ISD::SIGN_EXTEND;
1838 else if (F->getAttributes().hasAttribute(AttributeList::ReturnIndex,
1839 Attribute::ZExt))
1840 ExtendKind = ISD::ZERO_EXTEND;
1841
1842 LLVMContext &Context = F->getContext();
1843 bool RetInReg = F->getAttributes().hasAttribute(
1844 AttributeList::ReturnIndex, Attribute::InReg);
1845
1846 for (unsigned j = 0; j != NumValues; ++j) {
1847 EVT VT = ValueVTs[j];
1848
1849 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger())
1850 VT = TLI.getTypeForExtReturn(Context, VT, ExtendKind);
1851
1852 CallingConv::ID CC = F->getCallingConv();
1853
1854 unsigned NumParts = TLI.getNumRegistersForCallingConv(Context, CC, VT);
1855 MVT PartVT = TLI.getRegisterTypeForCallingConv(Context, CC, VT);
1856 SmallVector<SDValue, 4> Parts(NumParts);
1857 getCopyToParts(DAG, getCurSDLoc(),
1858 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
1859 &Parts[0], NumParts, PartVT, &I, CC, ExtendKind);
1860
1861 // 'inreg' on function refers to return value
1862 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1863 if (RetInReg)
1864 Flags.setInReg();
1865
1866 if (I.getOperand(0)->getType()->isPointerTy()) {
1867 Flags.setPointer();
1868 Flags.setPointerAddrSpace(
1869 cast<PointerType>(I.getOperand(0)->getType())->getAddressSpace());
1870 }
1871
1872 if (NeedsRegBlock) {
1873 Flags.setInConsecutiveRegs();
1874 if (j == NumValues - 1)
1875 Flags.setInConsecutiveRegsLast();
1876 }
1877
1878 // Propagate extension type if any
1879 if (ExtendKind == ISD::SIGN_EXTEND)
1880 Flags.setSExt();
1881 else if (ExtendKind == ISD::ZERO_EXTEND)
1882 Flags.setZExt();
1883
1884 for (unsigned i = 0; i < NumParts; ++i) {
1885 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(),
1886 VT, /*isfixed=*/true, 0, 0));
1887 OutVals.push_back(Parts[i]);
1888 }
1889 }
1890 }
1891 }
1892
1893 // Push in swifterror virtual register as the last element of Outs. This makes
1894 // sure swifterror virtual register will be returned in the swifterror
1895 // physical register.
1896 const Function *F = I.getParent()->getParent();
1897 if (TLI.supportSwiftError() &&
1898 F->getAttributes().hasAttrSomewhere(Attribute::SwiftError)) {
1899 assert(SwiftError.getFunctionArg() && "Need a swift error argument")((SwiftError.getFunctionArg() && "Need a swift error argument"
) ? static_cast<void> (0) : __assert_fail ("SwiftError.getFunctionArg() && \"Need a swift error argument\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 1899, __PRETTY_FUNCTION__))
;
1900 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1901 Flags.setSwiftError();
1902 Outs.push_back(ISD::OutputArg(Flags, EVT(TLI.getPointerTy(DL)) /*vt*/,
1903 EVT(TLI.getPointerTy(DL)) /*argvt*/,
1904 true /*isfixed*/, 1 /*origidx*/,
1905 0 /*partOffs*/));
1906 // Create SDNode for the swifterror virtual register.
1907 OutVals.push_back(
1908 DAG.getRegister(SwiftError.getOrCreateVRegUseAt(
1909 &I, FuncInfo.MBB, SwiftError.getFunctionArg()),
1910 EVT(TLI.getPointerTy(DL))));
1911 }
1912
1913 bool isVarArg = DAG.getMachineFunction().getFunction().isVarArg();
1914 CallingConv::ID CallConv =
1915 DAG.getMachineFunction().getFunction().getCallingConv();
1916 Chain = DAG.getTargetLoweringInfo().LowerReturn(
1917 Chain, CallConv, isVarArg, Outs, OutVals, getCurSDLoc(), DAG);
1918
1919 // Verify that the target's LowerReturn behaved as expected.
1920 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&((Chain.getNode() && Chain.getValueType() == MVT::Other
&& "LowerReturn didn't return a valid chain!") ? static_cast
<void> (0) : __assert_fail ("Chain.getNode() && Chain.getValueType() == MVT::Other && \"LowerReturn didn't return a valid chain!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 1921, __PRETTY_FUNCTION__))
1921 "LowerReturn didn't return a valid chain!")((Chain.getNode() && Chain.getValueType() == MVT::Other
&& "LowerReturn didn't return a valid chain!") ? static_cast
<void> (0) : __assert_fail ("Chain.getNode() && Chain.getValueType() == MVT::Other && \"LowerReturn didn't return a valid chain!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 1921, __PRETTY_FUNCTION__))
;
1922
1923 // Update the DAG with the new chain value resulting from return lowering.
1924 DAG.setRoot(Chain);
1925}
1926
1927/// CopyToExportRegsIfNeeded - If the given value has virtual registers
1928/// created for it, emit nodes to copy the value into the virtual
1929/// registers.
1930void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) {
1931 // Skip empty types
1932 if (V->getType()->isEmptyTy())
1933 return;
1934
1935 DenseMap<const Value *, Register>::iterator VMI = FuncInfo.ValueMap.find(V);
1936 if (VMI != FuncInfo.ValueMap.end()) {
1937 assert(!V->use_empty() && "Unused value assigned virtual registers!")((!V->use_empty() && "Unused value assigned virtual registers!"
) ? static_cast<void> (0) : __assert_fail ("!V->use_empty() && \"Unused value assigned virtual registers!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 1937, __PRETTY_FUNCTION__))
;
1938 CopyValueToVirtualRegister(V, VMI->second);
1939 }
1940}
1941
1942/// ExportFromCurrentBlock - If this condition isn't known to be exported from
1943/// the current basic block, add it to ValueMap now so that we'll get a
1944/// CopyTo/FromReg.
1945void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) {
1946 // No need to export constants.
1947 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1948
1949 // Already exported?
1950 if (FuncInfo.isExportedInst(V)) return;
1951
1952 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1953 CopyValueToVirtualRegister(V, Reg);
1954}
1955
1956bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V,
1957 const BasicBlock *FromBB) {
1958 // The operands of the setcc have to be in this block. We don't know
1959 // how to export them from some other block.
1960 if (const Instruction *VI = dyn_cast<Instruction>(V)) {
1961 // Can export from current BB.
1962 if (VI->getParent() == FromBB)
1963 return true;
1964
1965 // Is already exported, noop.
1966 return FuncInfo.isExportedInst(V);
1967 }
1968
1969 // If this is an argument, we can export it if the BB is the entry block or
1970 // if it is already exported.
1971 if (isa<Argument>(V)) {
1972 if (FromBB == &FromBB->getParent()->getEntryBlock())
1973 return true;
1974
1975 // Otherwise, can only export this if it is already exported.
1976 return FuncInfo.isExportedInst(V);
1977 }
1978
1979 // Otherwise, constants can always be exported.
1980 return true;
1981}
1982
1983/// Return branch probability calculated by BranchProbabilityInfo for IR blocks.
1984BranchProbability
1985SelectionDAGBuilder::getEdgeProbability(const MachineBasicBlock *Src,
1986 const MachineBasicBlock *Dst) const {
1987 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1988 const BasicBlock *SrcBB = Src->getBasicBlock();
1989 const BasicBlock *DstBB = Dst->getBasicBlock();
1990 if (!BPI) {
1991 // If BPI is not available, set the default probability as 1 / N, where N is
1992 // the number of successors.
1993 auto SuccSize = std::max<uint32_t>(succ_size(SrcBB), 1);
1994 return BranchProbability(1, SuccSize);
1995 }
1996 return BPI->getEdgeProbability(SrcBB, DstBB);
1997}
1998
1999void SelectionDAGBuilder::addSuccessorWithProb(MachineBasicBlock *Src,
2000 MachineBasicBlock *Dst,
2001 BranchProbability Prob) {
2002 if (!FuncInfo.BPI)
2003 Src->addSuccessorWithoutProb(Dst);
2004 else {
2005 if (Prob.isUnknown())
2006 Prob = getEdgeProbability(Src, Dst);
2007 Src->addSuccessor(Dst, Prob);
2008 }
2009}
2010
2011static bool InBlock(const Value *V, const BasicBlock *BB) {
2012 if (const Instruction *I = dyn_cast<Instruction>(V))
2013 return I->getParent() == BB;
2014 return true;
2015}
2016
2017/// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
2018/// This function emits a branch and is used at the leaves of an OR or an
2019/// AND operator tree.
2020void
2021SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond,
2022 MachineBasicBlock *TBB,
2023 MachineBasicBlock *FBB,
2024 MachineBasicBlock *CurBB,
2025 MachineBasicBlock *SwitchBB,
2026 BranchProbability TProb,
2027 BranchProbability FProb,
2028 bool InvertCond) {
2029 const BasicBlock *BB = CurBB->getBasicBlock();
2030
2031 // If the leaf of the tree is a comparison, merge the condition into
2032 // the caseblock.
2033 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
2034 // The operands of the cmp have to be in this block. We don't know
2035 // how to export them from some other block. If this is the first block
2036 // of the sequence, no exporting is needed.
2037 if (CurBB == SwitchBB ||
2038 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
2039 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
2040 ISD::CondCode Condition;
2041 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
2042 ICmpInst::Predicate Pred =
2043 InvertCond ? IC->getInversePredicate() : IC->getPredicate();
2044 Condition = getICmpCondCode(Pred);
2045 } else {
2046 const FCmpInst *FC = cast<FCmpInst>(Cond);
2047 FCmpInst::Predicate Pred =
2048 InvertCond ? FC->getInversePredicate() : FC->getPredicate();
2049 Condition = getFCmpCondCode(Pred);
2050 if (TM.Options.NoNaNsFPMath)
2051 Condition = getFCmpCodeWithoutNaN(Condition);
2052 }
2053
2054 CaseBlock CB(Condition, BOp->getOperand(0), BOp->getOperand(1), nullptr,
2055 TBB, FBB, CurBB, getCurSDLoc(), TProb, FProb);
2056 SL->SwitchCases.push_back(CB);
2057 return;
2058 }
2059 }
2060
2061 // Create a CaseBlock record representing this branch.
2062 ISD::CondCode Opc = InvertCond ? ISD::SETNE : ISD::SETEQ;
2063 CaseBlock CB(Opc, Cond, ConstantInt::getTrue(*DAG.getContext()),
2064 nullptr, TBB, FBB, CurBB, getCurSDLoc(), TProb, FProb);
2065 SL->SwitchCases.push_back(CB);
2066}
2067
2068void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
2069 MachineBasicBlock *TBB,
2070 MachineBasicBlock *FBB,
2071 MachineBasicBlock *CurBB,
2072 MachineBasicBlock *SwitchBB,
2073 Instruction::BinaryOps Opc,
2074 BranchProbability TProb,
2075 BranchProbability FProb,
2076 bool InvertCond) {
2077 // Skip over not part of the tree and remember to invert op and operands at
2078 // next level.
2079 Value *NotCond;
2080 if (match(Cond, m_OneUse(m_Not(m_Value(NotCond)))) &&
2081 InBlock(NotCond, CurBB->getBasicBlock())) {
2082 FindMergedConditions(NotCond, TBB, FBB, CurBB, SwitchBB, Opc, TProb, FProb,
2083 !InvertCond);
2084 return;
2085 }
2086
2087 const Instruction *BOp = dyn_cast<Instruction>(Cond);
2088 // Compute the effective opcode for Cond, taking into account whether it needs
2089 // to be inverted, e.g.
2090 // and (not (or A, B)), C
2091 // gets lowered as
2092 // and (and (not A, not B), C)
2093 unsigned BOpc = 0;
2094 if (BOp) {
2095 BOpc = BOp->getOpcode();
2096 if (InvertCond) {
2097 if (BOpc == Instruction::And)
2098 BOpc = Instruction::Or;
2099 else if (BOpc == Instruction::Or)
2100 BOpc = Instruction::And;
2101 }
2102 }
2103
2104 // If this node is not part of the or/and tree, emit it as a branch.
2105 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
2106 BOpc != unsigned(Opc) || !BOp->hasOneUse() ||
2107 BOp->getParent() != CurBB->getBasicBlock() ||
2108 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
2109 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
2110 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB,
2111 TProb, FProb, InvertCond);
2112 return;
2113 }
2114
2115 // Create TmpBB after CurBB.
2116 MachineFunction::iterator BBI(CurBB);
2117 MachineFunction &MF = DAG.getMachineFunction();
2118 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
2119 CurBB->getParent()->insert(++BBI, TmpBB);
2120
2121 if (Opc == Instruction::Or) {
2122 // Codegen X | Y as:
2123 // BB1:
2124 // jmp_if_X TBB
2125 // jmp TmpBB
2126 // TmpBB:
2127 // jmp_if_Y TBB
2128 // jmp FBB
2129 //
2130
2131 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
2132 // The requirement is that
2133 // TrueProb for BB1 + (FalseProb for BB1 * TrueProb for TmpBB)
2134 // = TrueProb for original BB.
2135 // Assuming the original probabilities are A and B, one choice is to set
2136 // BB1's probabilities to A/2 and A/2+B, and set TmpBB's probabilities to
2137 // A/(1+B) and 2B/(1+B). This choice assumes that
2138 // TrueProb for BB1 == FalseProb for BB1 * TrueProb for TmpBB.
2139 // Another choice is to assume TrueProb for BB1 equals to TrueProb for
2140 // TmpBB, but the math is more complicated.
2141
2142 auto NewTrueProb = TProb / 2;
2143 auto NewFalseProb = TProb / 2 + FProb;
2144 // Emit the LHS condition.
2145 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc,
2146 NewTrueProb, NewFalseProb, InvertCond);
2147
2148 // Normalize A/2 and B to get A/(1+B) and 2B/(1+B).
2149 SmallVector<BranchProbability, 2> Probs{TProb / 2, FProb};
2150 BranchProbability::normalizeProbabilities(Probs.begin(), Probs.end());
2151 // Emit the RHS condition into TmpBB.
2152 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
2153 Probs[0], Probs[1], InvertCond);
2154 } else {
2155 assert(Opc == Instruction::And && "Unknown merge op!")((Opc == Instruction::And && "Unknown merge op!") ? static_cast
<void> (0) : __assert_fail ("Opc == Instruction::And && \"Unknown merge op!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 2155, __PRETTY_FUNCTION__))
;
2156 // Codegen X & Y as:
2157 // BB1:
2158 // jmp_if_X TmpBB
2159 // jmp FBB
2160 // TmpBB:
2161 // jmp_if_Y TBB
2162 // jmp FBB
2163 //
2164 // This requires creation of TmpBB after CurBB.
2165
2166 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
2167 // The requirement is that
2168 // FalseProb for BB1 + (TrueProb for BB1 * FalseProb for TmpBB)
2169 // = FalseProb for original BB.
2170 // Assuming the original probabilities are A and B, one choice is to set
2171 // BB1's probabilities to A+B/2 and B/2, and set TmpBB's probabilities to
2172 // 2A/(1+A) and B/(1+A). This choice assumes that FalseProb for BB1 ==
2173 // TrueProb for BB1 * FalseProb for TmpBB.
2174
2175 auto NewTrueProb = TProb + FProb / 2;
2176 auto NewFalseProb = FProb / 2;
2177 // Emit the LHS condition.
2178 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc,
2179 NewTrueProb, NewFalseProb, InvertCond);
2180
2181 // Normalize A and B/2 to get 2A/(1+A) and B/(1+A).
2182 SmallVector<BranchProbability, 2> Probs{TProb, FProb / 2};
2183 BranchProbability::normalizeProbabilities(Probs.begin(), Probs.end());
2184 // Emit the RHS condition into TmpBB.
2185 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
2186 Probs[0], Probs[1], InvertCond);
2187 }
2188}
2189
2190/// If the set of cases should be emitted as a series of branches, return true.
2191/// If we should emit this as a bunch of and/or'd together conditions, return
2192/// false.
2193bool
2194SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases) {
2195 if (Cases.size() != 2) return true;
2196
2197 // If this is two comparisons of the same values or'd or and'd together, they
2198 // will get folded into a single comparison, so don't emit two blocks.
2199 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
2200 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
2201 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
2202 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
2203 return false;
2204 }
2205
2206 // Handle: (X != null) | (Y != null) --> (X|Y) != 0
2207 // Handle: (X == null) & (Y == null) --> (X|Y) == 0
2208 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
2209 Cases[0].CC == Cases[1].CC &&
2210 isa<Constant>(Cases[0].CmpRHS) &&
2211 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
2212 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
2213 return false;
2214 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
2215 return false;
2216 }
2217
2218 return true;
2219}
2220
2221void SelectionDAGBuilder::visitBr(const BranchInst &I) {
2222 MachineBasicBlock *BrMBB = FuncInfo.MBB;
2223
2224 // Update machine-CFG edges.
2225 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
2226
2227 if (I.isUnconditional()) {
2228 // Update machine-CFG edges.
2229 BrMBB->addSuccessor(Succ0MBB);
2230
2231 // If this is not a fall-through branch or optimizations are switched off,
2232 // emit the branch.
2233 if (Succ0MBB != NextBlock(BrMBB) || TM.getOptLevel() == CodeGenOpt::None)
2234 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
2235 MVT::Other, getControlRoot(),
2236 DAG.getBasicBlock(Succ0MBB)));
2237
2238 return;
2239 }
2240
2241 // If this condition is one of the special cases we handle, do special stuff
2242 // now.
2243 const Value *CondVal = I.getCondition();
2244 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
2245
2246 // If this is a series of conditions that are or'd or and'd together, emit
2247 // this as a sequence of branches instead of setcc's with and/or operations.
2248 // As long as jumps are not expensive (exceptions for multi-use logic ops,
2249 // unpredictable branches, and vector extracts because those jumps are likely
2250 // expensive for any target), this should improve performance.
2251 // For example, instead of something like:
2252 // cmp A, B
2253 // C = seteq
2254 // cmp D, E
2255 // F = setle
2256 // or C, F
2257 // jnz foo
2258 // Emit:
2259 // cmp A, B
2260 // je foo
2261 // cmp D, E
2262 // jle foo
2263 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
2264 Instruction::BinaryOps Opcode = BOp->getOpcode();
2265 Value *Vec, *BOp0 = BOp->getOperand(0), *BOp1 = BOp->getOperand(1);
2266 if (!DAG.getTargetLoweringInfo().isJumpExpensive() && BOp->hasOneUse() &&
2267 !I.hasMetadata(LLVMContext::MD_unpredictable) &&
2268 (Opcode == Instruction::And || Opcode == Instruction::Or) &&
2269 !(match(BOp0, m_ExtractElt(m_Value(Vec), m_Value())) &&
2270 match(BOp1, m_ExtractElt(m_Specific(Vec), m_Value())))) {
2271 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB,
2272 Opcode,
2273 getEdgeProbability(BrMBB, Succ0MBB),
2274 getEdgeProbability(BrMBB, Succ1MBB),
2275 /*InvertCond=*/false);
2276 // If the compares in later blocks need to use values not currently
2277 // exported from this block, export them now. This block should always
2278 // be the first entry.
2279 assert(SL->SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!")((SL->SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!"
) ? static_cast<void> (0) : __assert_fail ("SL->SwitchCases[0].ThisBB == BrMBB && \"Unexpected lowering!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 2279, __PRETTY_FUNCTION__))
;
2280
2281 // Allow some cases to be rejected.
2282 if (ShouldEmitAsBranches(SL->SwitchCases)) {
2283 for (unsigned i = 1, e = SL->SwitchCases.size(); i != e; ++i) {
2284 ExportFromCurrentBlock(SL->SwitchCases[i].CmpLHS);
2285 ExportFromCurrentBlock(SL->SwitchCases[i].CmpRHS);
2286 }
2287
2288 // Emit the branch for this block.
2289 visitSwitchCase(SL->SwitchCases[0], BrMBB);
2290 SL->SwitchCases.erase(SL->SwitchCases.begin());
2291 return;
2292 }
2293
2294 // Okay, we decided not to do this, remove any inserted MBB's and clear
2295 // SwitchCases.
2296 for (unsigned i = 1, e = SL->SwitchCases.size(); i != e; ++i)
2297 FuncInfo.MF->erase(SL->SwitchCases[i].ThisBB);
2298
2299 SL->SwitchCases.clear();
2300 }
2301 }
2302
2303 // Create a CaseBlock record representing this branch.
2304 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
2305 nullptr, Succ0MBB, Succ1MBB, BrMBB, getCurSDLoc());
2306
2307 // Use visitSwitchCase to actually insert the fast branch sequence for this
2308 // cond branch.
2309 visitSwitchCase(CB, BrMBB);
2310}
2311
2312/// visitSwitchCase - Emits the necessary code to represent a single node in
2313/// the binary search tree resulting from lowering a switch instruction.
2314void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB,
2315 MachineBasicBlock *SwitchBB) {
2316 SDValue Cond;
2317 SDValue CondLHS = getValue(CB.CmpLHS);
2318 SDLoc dl = CB.DL;
2319
2320 if (CB.CC == ISD::SETTRUE) {
2321 // Branch or fall through to TrueBB.
2322 addSuccessorWithProb(SwitchBB, CB.TrueBB, CB.TrueProb);
2323 SwitchBB->normalizeSuccProbs();
2324 if (CB.TrueBB != NextBlock(SwitchBB)) {
2325 DAG.setRoot(DAG.getNode(ISD::BR, dl, MVT::Other, getControlRoot(),
2326 DAG.getBasicBlock(CB.TrueBB)));
2327 }
2328 return;
2329 }
2330
2331 auto &TLI = DAG.getTargetLoweringInfo();
2332 EVT MemVT = TLI.getMemValueType(DAG.getDataLayout(), CB.CmpLHS->getType());
2333
2334 // Build the setcc now.
2335 if (!CB.CmpMHS) {
2336 // Fold "(X == true)" to X and "(X == false)" to !X to
2337 // handle common cases produced by branch lowering.
2338 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
2339 CB.CC == ISD::SETEQ)
2340 Cond = CondLHS;
2341 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
2342 CB.CC == ISD::SETEQ) {
2343 SDValue True = DAG.getConstant(1, dl, CondLHS.getValueType());
2344 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
2345 } else {
2346 SDValue CondRHS = getValue(CB.CmpRHS);
2347
2348 // If a pointer's DAG type is larger than its memory type then the DAG
2349 // values are zero-extended. This breaks signed comparisons so truncate
2350 // back to the underlying type before doing the compare.
2351 if (CondLHS.getValueType() != MemVT) {
2352 CondLHS = DAG.getPtrExtOrTrunc(CondLHS, getCurSDLoc(), MemVT);
2353 CondRHS = DAG.getPtrExtOrTrunc(CondRHS, getCurSDLoc(), MemVT);
2354 }
2355 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, CondRHS, CB.CC);
2356 }
2357 } else {
2358 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now")((CB.CC == ISD::SETLE && "Can handle only LE ranges now"
) ? static_cast<void> (0) : __assert_fail ("CB.CC == ISD::SETLE && \"Can handle only LE ranges now\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 2358, __PRETTY_FUNCTION__))
;
2359
2360 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
2361 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
2362
2363 SDValue CmpOp = getValue(CB.CmpMHS);
2364 EVT VT = CmpOp.getValueType();
2365
2366 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
2367 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, dl, VT),
2368 ISD::SETLE);
2369 } else {
2370 SDValue SUB = DAG.getNode(ISD::SUB, dl,
2371 VT, CmpOp, DAG.getConstant(Low, dl, VT));
2372 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
2373 DAG.getConstant(High-Low, dl, VT), ISD::SETULE);
2374 }
2375 }
2376
2377 // Update successor info
2378 addSuccessorWithProb(SwitchBB, CB.TrueBB, CB.TrueProb);
2379 // TrueBB and FalseBB are always different unless the incoming IR is
2380 // degenerate. This only happens when running llc on weird IR.
2381 if (CB.TrueBB != CB.FalseBB)
2382 addSuccessorWithProb(SwitchBB, CB.FalseBB, CB.FalseProb);
2383 SwitchBB->normalizeSuccProbs();
2384
2385 // If the lhs block is the next block, invert the condition so that we can
2386 // fall through to the lhs instead of the rhs block.
2387 if (CB.TrueBB == NextBlock(SwitchBB)) {
2388 std::swap(CB.TrueBB, CB.FalseBB);
2389 SDValue True = DAG.getConstant(1, dl, Cond.getValueType());
2390 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
2391 }
2392
2393 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
2394 MVT::Other, getControlRoot(), Cond,
2395 DAG.getBasicBlock(CB.TrueBB));
2396
2397 // Insert the false branch. Do this even if it's a fall through branch,
2398 // this makes it easier to do DAG optimizations which require inverting
2399 // the branch condition.
2400 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
2401 DAG.getBasicBlock(CB.FalseBB));
2402
2403 DAG.setRoot(BrCond);
2404}
2405
2406/// visitJumpTable - Emit JumpTable node in the current MBB
2407void SelectionDAGBuilder::visitJumpTable(SwitchCG::JumpTable &JT) {
2408 // Emit the code for the jump table
2409 assert(JT.Reg != -1U && "Should lower JT Header first!")((JT.Reg != -1U && "Should lower JT Header first!") ?
static_cast<void> (0) : __assert_fail ("JT.Reg != -1U && \"Should lower JT Header first!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 2409, __PRETTY_FUNCTION__))
;
2410 EVT PTy = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
2411 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(),
2412 JT.Reg, PTy);
2413 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
2414 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurSDLoc(),
2415 MVT::Other, Index.getValue(1),
2416 Table, Index);
2417 DAG.setRoot(BrJumpTable);
2418}
2419
2420/// visitJumpTableHeader - This function emits necessary code to produce index
2421/// in the JumpTable from switch case.
2422void SelectionDAGBuilder::visitJumpTableHeader(SwitchCG::JumpTable &JT,
2423 JumpTableHeader &JTH,
2424 MachineBasicBlock *SwitchBB) {
2425 SDLoc dl = getCurSDLoc();
2426
2427 // Subtract the lowest switch case value from the value being switched on.
2428 SDValue SwitchOp = getValue(JTH.SValue);
2429 EVT VT = SwitchOp.getValueType();
2430 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, SwitchOp,
2431 DAG.getConstant(JTH.First, dl, VT));
2432
2433 // The SDNode we just created, which holds the value being switched on minus
2434 // the smallest case value, needs to be copied to a virtual register so it
2435 // can be used as an index into the jump table in a subsequent basic block.
2436 // This value may be smaller or larger than the target's pointer type, and
2437 // therefore require extension or truncating.
2438 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2439 SwitchOp = DAG.getZExtOrTrunc(Sub, dl, TLI.getPointerTy(DAG.getDataLayout()));
2440
2441 unsigned JumpTableReg =
2442 FuncInfo.CreateReg(TLI.getPointerTy(DAG.getDataLayout()));
2443 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), dl,
2444 JumpTableReg, SwitchOp);
2445 JT.Reg = JumpTableReg;
2446
2447 if (!JTH.OmitRangeCheck) {
2448 // Emit the range check for the jump table, and branch to the default block
2449 // for the switch statement if the value being switched on exceeds the
2450 // largest case in the switch.
2451 SDValue CMP = DAG.getSetCC(
2452 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
2453 Sub.getValueType()),
2454 Sub, DAG.getConstant(JTH.Last - JTH.First, dl, VT), ISD::SETUGT);
2455
2456 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
2457 MVT::Other, CopyTo, CMP,
2458 DAG.getBasicBlock(JT.Default));
2459
2460 // Avoid emitting unnecessary branches to the next block.
2461 if (JT.MBB != NextBlock(SwitchBB))
2462 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
2463 DAG.getBasicBlock(JT.MBB));
2464
2465 DAG.setRoot(BrCond);
2466 } else {
2467 // Avoid emitting unnecessary branches to the next block.
2468 if (JT.MBB != NextBlock(SwitchBB))
2469 DAG.setRoot(DAG.getNode(ISD::BR, dl, MVT::Other, CopyTo,
2470 DAG.getBasicBlock(JT.MBB)));
2471 else
2472 DAG.setRoot(CopyTo);
2473 }
2474}
2475
2476/// Create a LOAD_STACK_GUARD node, and let it carry the target specific global
2477/// variable if there exists one.
2478static SDValue getLoadStackGuard(SelectionDAG &DAG, const SDLoc &DL,
2479 SDValue &Chain) {
2480 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2481 EVT PtrTy = TLI.getPointerTy(DAG.getDataLayout());
2482 EVT PtrMemTy = TLI.getPointerMemTy(DAG.getDataLayout());
2483 MachineFunction &MF = DAG.getMachineFunction();
2484 Value *Global = TLI.getSDagStackGuard(*MF.getFunction().getParent());
2485 MachineSDNode *Node =
2486 DAG.getMachineNode(TargetOpcode::LOAD_STACK_GUARD, DL, PtrTy, Chain);
2487 if (Global) {
2488 MachinePointerInfo MPInfo(Global);
2489 auto Flags = MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant |
2490 MachineMemOperand::MODereferenceable;
2491 MachineMemOperand *MemRef = MF.getMachineMemOperand(
2492 MPInfo, Flags, PtrTy.getSizeInBits() / 8, DAG.getEVTAlign(PtrTy));
2493 DAG.setNodeMemRefs(Node, {MemRef});
2494 }
2495 if (PtrTy != PtrMemTy)
2496 return DAG.getPtrExtOrTrunc(SDValue(Node, 0), DL, PtrMemTy);
2497 return SDValue(Node, 0);
2498}
2499
2500/// Codegen a new tail for a stack protector check ParentMBB which has had its
2501/// tail spliced into a stack protector check success bb.
2502///
2503/// For a high level explanation of how this fits into the stack protector
2504/// generation see the comment on the declaration of class
2505/// StackProtectorDescriptor.
2506void SelectionDAGBuilder::visitSPDescriptorParent(StackProtectorDescriptor &SPD,
2507 MachineBasicBlock *ParentBB) {
2508
2509 // First create the loads to the guard/stack slot for the comparison.
2510 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2511 EVT PtrTy = TLI.getPointerTy(DAG.getDataLayout());
2512 EVT PtrMemTy = TLI.getPointerMemTy(DAG.getDataLayout());
2513
2514 MachineFrameInfo &MFI = ParentBB->getParent()->getFrameInfo();
2515 int FI = MFI.getStackProtectorIndex();
2516
2517 SDValue Guard;
2518 SDLoc dl = getCurSDLoc();
2519 SDValue StackSlotPtr = DAG.getFrameIndex(FI, PtrTy);
2520 const Module &M = *ParentBB->getParent()->getFunction().getParent();
2521 Align Align = DL->getPrefTypeAlign(Type::getInt8PtrTy(M.getContext()));
2522
2523 // Generate code to load the content of the guard slot.
2524 SDValue GuardVal = DAG.getLoad(
2525 PtrMemTy, dl, DAG.getEntryNode(), StackSlotPtr,
2526 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI), Align,
2527 MachineMemOperand::MOVolatile);
2528
2529 if (TLI.useStackGuardXorFP())
2530 GuardVal = TLI.emitStackGuardXorFP(DAG, GuardVal, dl);
2531
2532 // Retrieve guard check function, nullptr if instrumentation is inlined.
2533 if (const Function *GuardCheckFn = TLI.getSSPStackGuardCheck(M)) {
2534 // The target provides a guard check function to validate the guard value.
2535 // Generate a call to that function with the content of the guard slot as
2536 // argument.
2537 FunctionType *FnTy = GuardCheckFn->getFunctionType();
2538 assert(FnTy->getNumParams() == 1 && "Invalid function signature")((FnTy->getNumParams() == 1 && "Invalid function signature"
) ? static_cast<void> (0) : __assert_fail ("FnTy->getNumParams() == 1 && \"Invalid function signature\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 2538, __PRETTY_FUNCTION__))
;
2539
2540 TargetLowering::ArgListTy Args;
2541 TargetLowering::ArgListEntry Entry;
2542 Entry.Node = GuardVal;
2543 Entry.Ty = FnTy->getParamType(0);
2544 if (GuardCheckFn->hasAttribute(1, Attribute::AttrKind::InReg))
2545 Entry.IsInReg = true;
2546 Args.push_back(Entry);
2547
2548 TargetLowering::CallLoweringInfo CLI(DAG);
2549 CLI.setDebugLoc(getCurSDLoc())
2550 .setChain(DAG.getEntryNode())
2551 .setCallee(GuardCheckFn->getCallingConv(), FnTy->getReturnType(),
2552 getValue(GuardCheckFn), std::move(Args));
2553
2554 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
2555 DAG.setRoot(Result.second);
2556 return;
2557 }
2558
2559 // If useLoadStackGuardNode returns true, generate LOAD_STACK_GUARD.
2560 // Otherwise, emit a volatile load to retrieve the stack guard value.
2561 SDValue Chain = DAG.getEntryNode();
2562 if (TLI.useLoadStackGuardNode()) {
2563 Guard = getLoadStackGuard(DAG, dl, Chain);
2564 } else {
2565 const Value *IRGuard = TLI.getSDagStackGuard(M);
2566 SDValue GuardPtr = getValue(IRGuard);
2567
2568 Guard = DAG.getLoad(PtrMemTy, dl, Chain, GuardPtr,
2569 MachinePointerInfo(IRGuard, 0), Align,
2570 MachineMemOperand::MOVolatile);
2571 }
2572
2573 // Perform the comparison via a getsetcc.
2574 SDValue Cmp = DAG.getSetCC(dl, TLI.getSetCCResultType(DAG.getDataLayout(),
2575 *DAG.getContext(),
2576 Guard.getValueType()),
2577 Guard, GuardVal, ISD::SETNE);
2578
2579 // If the guard/stackslot do not equal, branch to failure MBB.
2580 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
2581 MVT::Other, GuardVal.getOperand(0),
2582 Cmp, DAG.getBasicBlock(SPD.getFailureMBB()));
2583 // Otherwise branch to success MBB.
2584 SDValue Br = DAG.getNode(ISD::BR, dl,
2585 MVT::Other, BrCond,
2586 DAG.getBasicBlock(SPD.getSuccessMBB()));
2587
2588 DAG.setRoot(Br);
2589}
2590
2591/// Codegen the failure basic block for a stack protector check.
2592///
2593/// A failure stack protector machine basic block consists simply of a call to
2594/// __stack_chk_fail().
2595///
2596/// For a high level explanation of how this fits into the stack protector
2597/// generation see the comment on the declaration of class
2598/// StackProtectorDescriptor.
2599void
2600SelectionDAGBuilder::visitSPDescriptorFailure(StackProtectorDescriptor &SPD) {
2601 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2602 TargetLowering::MakeLibCallOptions CallOptions;
2603 CallOptions.setDiscardResult(true);
2604 SDValue Chain =
2605 TLI.makeLibCall(DAG, RTLIB::STACKPROTECTOR_CHECK_FAIL, MVT::isVoid,
2606 None, CallOptions, getCurSDLoc()).second;
2607 // On PS4, the "return address" must still be within the calling function,
2608 // even if it's at the very end, so emit an explicit TRAP here.
2609 // Passing 'true' for doesNotReturn above won't generate the trap for us.
2610 if (TM.getTargetTriple().isPS4CPU())
2611 Chain = DAG.getNode(ISD::TRAP, getCurSDLoc(), MVT::Other, Chain);
2612 // WebAssembly needs an unreachable instruction after a non-returning call,
2613 // because the function return type can be different from __stack_chk_fail's
2614 // return type (void).
2615 if (TM.getTargetTriple().isWasm())
2616 Chain = DAG.getNode(ISD::TRAP, getCurSDLoc(), MVT::Other, Chain);
2617
2618 DAG.setRoot(Chain);
2619}
2620
2621/// visitBitTestHeader - This function emits necessary code to produce value
2622/// suitable for "bit tests"
2623void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
2624 MachineBasicBlock *SwitchBB) {
2625 SDLoc dl = getCurSDLoc();
2626
2627 // Subtract the minimum value.
2628 SDValue SwitchOp = getValue(B.SValue);
2629 EVT VT = SwitchOp.getValueType();
2630 SDValue RangeSub =
2631 DAG.getNode(ISD::SUB, dl, VT, SwitchOp, DAG.getConstant(B.First, dl, VT));
2632
2633 // Determine the type of the test operands.
2634 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2635 bool UsePtrType = false;
2636 if (!TLI.isTypeLegal(VT)) {
2637 UsePtrType = true;
2638 } else {
2639 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i)
2640 if (!isUIntN(VT.getSizeInBits(), B.Cases[i].Mask)) {
2641 // Switch table case range are encoded into series of masks.
2642 // Just use pointer type, it's guaranteed to fit.
2643 UsePtrType = true;
2644 break;
2645 }
2646 }
2647 SDValue Sub = RangeSub;
2648 if (UsePtrType) {
2649 VT = TLI.getPointerTy(DAG.getDataLayout());
2650 Sub = DAG.getZExtOrTrunc(Sub, dl, VT);
2651 }
2652
2653 B.RegVT = VT.getSimpleVT();
2654 B.Reg = FuncInfo.CreateReg(B.RegVT);
2655 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), dl, B.Reg, Sub);
2656
2657 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
2658
2659 if (!B.OmitRangeCheck)
2660 addSuccessorWithProb(SwitchBB, B.Default, B.DefaultProb);
2661 addSuccessorWithProb(SwitchBB, MBB, B.Prob);
2662 SwitchBB->normalizeSuccProbs();
2663
2664 SDValue Root = CopyTo;
2665 if (!B.OmitRangeCheck) {
2666 // Conditional branch to the default block.
2667 SDValue RangeCmp = DAG.getSetCC(dl,
2668 TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
2669 RangeSub.getValueType()),
2670 RangeSub, DAG.getConstant(B.Range, dl, RangeSub.getValueType()),
2671 ISD::SETUGT);
2672
2673 Root = DAG.getNode(ISD::BRCOND, dl, MVT::Other, Root, RangeCmp,
2674 DAG.getBasicBlock(B.Default));
2675 }
2676
2677 // Avoid emitting unnecessary branches to the next block.
2678 if (MBB != NextBlock(SwitchBB))
2679 Root = DAG.getNode(ISD::BR, dl, MVT::Other, Root, DAG.getBasicBlock(MBB));
2680
2681 DAG.setRoot(Root);
2682}
2683
2684/// visitBitTestCase - this function produces one "bit test"
2685void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB,
2686 MachineBasicBlock* NextMBB,
2687 BranchProbability BranchProbToNext,
2688 unsigned Reg,
2689 BitTestCase &B,
2690 MachineBasicBlock *SwitchBB) {
2691 SDLoc dl = getCurSDLoc();
2692 MVT VT = BB.RegVT;
2693 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), dl, Reg, VT);
2694 SDValue Cmp;
2695 unsigned PopCount = countPopulation(B.Mask);
2696 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2697 if (PopCount == 1) {
2698 // Testing for a single bit; just compare the shift count with what it
2699 // would need to be to shift a 1 bit in that position.
2700 Cmp = DAG.getSetCC(
2701 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT),
2702 ShiftOp, DAG.getConstant(countTrailingZeros(B.Mask), dl, VT),
2703 ISD::SETEQ);
2704 } else if (PopCount == BB.Range) {
2705 // There is only one zero bit in the range, test for it directly.
2706 Cmp = DAG.getSetCC(
2707 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT),
2708 ShiftOp, DAG.getConstant(countTrailingOnes(B.Mask), dl, VT),
2709 ISD::SETNE);
2710 } else {
2711 // Make desired shift
2712 SDValue SwitchVal = DAG.getNode(ISD::SHL, dl, VT,
2713 DAG.getConstant(1, dl, VT), ShiftOp);
2714
2715 // Emit bit tests and jumps
2716 SDValue AndOp = DAG.getNode(ISD::AND, dl,
2717 VT, SwitchVal, DAG.getConstant(B.Mask, dl, VT));
2718 Cmp = DAG.getSetCC(
2719 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT),
2720 AndOp, DAG.getConstant(0, dl, VT), ISD::SETNE);
2721 }
2722
2723 // The branch probability from SwitchBB to B.TargetBB is B.ExtraProb.
2724 addSuccessorWithProb(SwitchBB, B.TargetBB, B.ExtraProb);
2725 // The branch probability from SwitchBB to NextMBB is BranchProbToNext.
2726 addSuccessorWithProb(SwitchBB, NextMBB, BranchProbToNext);
2727 // It is not guaranteed that the sum of B.ExtraProb and BranchProbToNext is
2728 // one as they are relative probabilities (and thus work more like weights),
2729 // and hence we need to normalize them to let the sum of them become one.
2730 SwitchBB->normalizeSuccProbs();
2731
2732 SDValue BrAnd = DAG.getNode(ISD::BRCOND, dl,
2733 MVT::Other, getControlRoot(),
2734 Cmp, DAG.getBasicBlock(B.TargetBB));
2735
2736 // Avoid emitting unnecessary branches to the next block.
2737 if (NextMBB != NextBlock(SwitchBB))
2738 BrAnd = DAG.getNode(ISD::BR, dl, MVT::Other, BrAnd,
2739 DAG.getBasicBlock(NextMBB));
2740
2741 DAG.setRoot(BrAnd);
2742}
2743
2744void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
2745 MachineBasicBlock *InvokeMBB = FuncInfo.MBB;
2746
2747 // Retrieve successors. Look through artificial IR level blocks like
2748 // catchswitch for successors.
2749 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
2750 const BasicBlock *EHPadBB = I.getSuccessor(1);
2751
2752 // Deopt bundles are lowered in LowerCallSiteWithDeoptBundle, and we don't
2753 // have to do anything here to lower funclet bundles.
2754 assert(!I.hasOperandBundlesOtherThan({LLVMContext::OB_deopt,((!I.hasOperandBundlesOtherThan({LLVMContext::OB_deopt, LLVMContext
::OB_gc_transition, LLVMContext::OB_gc_live, LLVMContext::OB_funclet
, LLVMContext::OB_cfguardtarget}) && "Cannot lower invokes with arbitrary operand bundles yet!"
) ? static_cast<void> (0) : __assert_fail ("!I.hasOperandBundlesOtherThan({LLVMContext::OB_deopt, LLVMContext::OB_gc_transition, LLVMContext::OB_gc_live, LLVMContext::OB_funclet, LLVMContext::OB_cfguardtarget}) && \"Cannot lower invokes with arbitrary operand bundles yet!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 2759, __PRETTY_FUNCTION__))
2755 LLVMContext::OB_gc_transition,((!I.hasOperandBundlesOtherThan({LLVMContext::OB_deopt, LLVMContext
::OB_gc_transition, LLVMContext::OB_gc_live, LLVMContext::OB_funclet
, LLVMContext::OB_cfguardtarget}) && "Cannot lower invokes with arbitrary operand bundles yet!"
) ? static_cast<void> (0) : __assert_fail ("!I.hasOperandBundlesOtherThan({LLVMContext::OB_deopt, LLVMContext::OB_gc_transition, LLVMContext::OB_gc_live, LLVMContext::OB_funclet, LLVMContext::OB_cfguardtarget}) && \"Cannot lower invokes with arbitrary operand bundles yet!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 2759, __PRETTY_FUNCTION__))
2756 LLVMContext::OB_gc_live,((!I.hasOperandBundlesOtherThan({LLVMContext::OB_deopt, LLVMContext
::OB_gc_transition, LLVMContext::OB_gc_live, LLVMContext::OB_funclet
, LLVMContext::OB_cfguardtarget}) && "Cannot lower invokes with arbitrary operand bundles yet!"
) ? static_cast<void> (0) : __assert_fail ("!I.hasOperandBundlesOtherThan({LLVMContext::OB_deopt, LLVMContext::OB_gc_transition, LLVMContext::OB_gc_live, LLVMContext::OB_funclet, LLVMContext::OB_cfguardtarget}) && \"Cannot lower invokes with arbitrary operand bundles yet!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 2759, __PRETTY_FUNCTION__))
2757 LLVMContext::OB_funclet,((!I.hasOperandBundlesOtherThan({LLVMContext::OB_deopt, LLVMContext
::OB_gc_transition, LLVMContext::OB_gc_live, LLVMContext::OB_funclet
, LLVMContext::OB_cfguardtarget}) && "Cannot lower invokes with arbitrary operand bundles yet!"
) ? static_cast<void> (0) : __assert_fail ("!I.hasOperandBundlesOtherThan({LLVMContext::OB_deopt, LLVMContext::OB_gc_transition, LLVMContext::OB_gc_live, LLVMContext::OB_funclet, LLVMContext::OB_cfguardtarget}) && \"Cannot lower invokes with arbitrary operand bundles yet!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 2759, __PRETTY_FUNCTION__))
2758 LLVMContext::OB_cfguardtarget}) &&((!I.hasOperandBundlesOtherThan({LLVMContext::OB_deopt, LLVMContext
::OB_gc_transition, LLVMContext::OB_gc_live, LLVMContext::OB_funclet
, LLVMContext::OB_cfguardtarget}) && "Cannot lower invokes with arbitrary operand bundles yet!"
) ? static_cast<void> (0) : __assert_fail ("!I.hasOperandBundlesOtherThan({LLVMContext::OB_deopt, LLVMContext::OB_gc_transition, LLVMContext::OB_gc_live, LLVMContext::OB_funclet, LLVMContext::OB_cfguardtarget}) && \"Cannot lower invokes with arbitrary operand bundles yet!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 2759, __PRETTY_FUNCTION__))
2759 "Cannot lower invokes with arbitrary operand bundles yet!")((!I.hasOperandBundlesOtherThan({LLVMContext::OB_deopt, LLVMContext
::OB_gc_transition, LLVMContext::OB_gc_live, LLVMContext::OB_funclet
, LLVMContext::OB_cfguardtarget}) && "Cannot lower invokes with arbitrary operand bundles yet!"
) ? static_cast<void> (0) : __assert_fail ("!I.hasOperandBundlesOtherThan({LLVMContext::OB_deopt, LLVMContext::OB_gc_transition, LLVMContext::OB_gc_live, LLVMContext::OB_funclet, LLVMContext::OB_cfguardtarget}) && \"Cannot lower invokes with arbitrary operand bundles yet!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 2759, __PRETTY_FUNCTION__))
;
2760
2761 const Value *Callee(I.getCalledOperand());
2762 const Function *Fn = dyn_cast<Function>(Callee);
2763 if (isa<InlineAsm>(Callee))
2764 visitInlineAsm(I);
2765 else if (Fn && Fn->isIntrinsic()) {
2766 switch (Fn->getIntrinsicID()) {
2767 default:
2768 llvm_unreachable("Cannot invoke this intrinsic")::llvm::llvm_unreachable_internal("Cannot invoke this intrinsic"
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 2768)
;
2769 case Intrinsic::donothing:
2770 // Ignore invokes to @llvm.donothing: jump directly to the next BB.
2771 break;
2772 case Intrinsic::experimental_patchpoint_void:
2773 case Intrinsic::experimental_patchpoint_i64:
2774 visitPatchpoint(I, EHPadBB);
2775 break;
2776 case Intrinsic::experimental_gc_statepoint:
2777 LowerStatepoint(cast<GCStatepointInst>(I), EHPadBB);
2778 break;
2779 case Intrinsic::wasm_rethrow_in_catch: {
2780 // This is usually done in visitTargetIntrinsic, but this intrinsic is
2781 // special because it can be invoked, so we manually lower it to a DAG
2782 // node here.
2783 SmallVector<SDValue, 8> Ops;
2784 Ops.push_back(getRoot()); // inchain
2785 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2786 Ops.push_back(
2787 DAG.getTargetConstant(Intrinsic::wasm_rethrow_in_catch, getCurSDLoc(),
2788 TLI.getPointerTy(DAG.getDataLayout())));
2789 SDVTList VTs = DAG.getVTList(ArrayRef<EVT>({MVT::Other})); // outchain
2790 DAG.setRoot(DAG.getNode(ISD::INTRINSIC_VOID, getCurSDLoc(), VTs, Ops));
2791 break;
2792 }
2793 }
2794 } else if (I.countOperandBundlesOfType(LLVMContext::OB_deopt)) {
2795 // Currently we do not lower any intrinsic calls with deopt operand bundles.
2796 // Eventually we will support lowering the @llvm.experimental.deoptimize
2797 // intrinsic, and right now there are no plans to support other intrinsics
2798 // with deopt state.
2799 LowerCallSiteWithDeoptBundle(&I, getValue(Callee), EHPadBB);
2800 } else {
2801 LowerCallTo(I, getValue(Callee), false, EHPadBB);
2802 }
2803
2804 // If the value of the invoke is used outside of its defining block, make it
2805 // available as a virtual register.
2806 // We already took care of the exported value for the statepoint instruction
2807 // during call to the LowerStatepoint.
2808 if (!isa<GCStatepointInst>(I)) {
2809 CopyToExportRegsIfNeeded(&I);
2810 }
2811
2812 SmallVector<std::pair<MachineBasicBlock *, BranchProbability>, 1> UnwindDests;
2813 BranchProbabilityInfo *BPI = FuncInfo.BPI;
2814 BranchProbability EHPadBBProb =
2815 BPI ? BPI->getEdgeProbability(InvokeMBB->getBasicBlock(), EHPadBB)
2816 : BranchProbability::getZero();
2817 findUnwindDestinations(FuncInfo, EHPadBB, EHPadBBProb, UnwindDests);
2818
2819 // Update successor info.
2820 addSuccessorWithProb(InvokeMBB, Return);
2821 for (auto &UnwindDest : UnwindDests) {
2822 UnwindDest.first->setIsEHPad();
2823 addSuccessorWithProb(InvokeMBB, UnwindDest.first, UnwindDest.second);
2824 }
2825 InvokeMBB->normalizeSuccProbs();
2826
2827 // Drop into normal successor.
2828 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, getControlRoot(),
2829 DAG.getBasicBlock(Return)));
2830}
2831
2832void SelectionDAGBuilder::visitCallBr(const CallBrInst &I) {
2833 MachineBasicBlock *CallBrMBB = FuncInfo.MBB;
2834
2835 // Deopt bundles are lowered in LowerCallSiteWithDeoptBundle, and we don't
2836 // have to do anything here to lower funclet bundles.
2837 assert(!I.hasOperandBundlesOtherThan(((!I.hasOperandBundlesOtherThan( {LLVMContext::OB_deopt, LLVMContext
::OB_funclet}) && "Cannot lower callbrs with arbitrary operand bundles yet!"
) ? static_cast<void> (0) : __assert_fail ("!I.hasOperandBundlesOtherThan( {LLVMContext::OB_deopt, LLVMContext::OB_funclet}) && \"Cannot lower callbrs with arbitrary operand bundles yet!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 2839, __PRETTY_FUNCTION__))
2838 {LLVMContext::OB_deopt, LLVMContext::OB_funclet}) &&((!I.hasOperandBundlesOtherThan( {LLVMContext::OB_deopt, LLVMContext
::OB_funclet}) && "Cannot lower callbrs with arbitrary operand bundles yet!"
) ? static_cast<void> (0) : __assert_fail ("!I.hasOperandBundlesOtherThan( {LLVMContext::OB_deopt, LLVMContext::OB_funclet}) && \"Cannot lower callbrs with arbitrary operand bundles yet!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 2839, __PRETTY_FUNCTION__))
2839 "Cannot lower callbrs with arbitrary operand bundles yet!")((!I.hasOperandBundlesOtherThan( {LLVMContext::OB_deopt, LLVMContext
::OB_funclet}) && "Cannot lower callbrs with arbitrary operand bundles yet!"
) ? static_cast<void> (0) : __assert_fail ("!I.hasOperandBundlesOtherThan( {LLVMContext::OB_deopt, LLVMContext::OB_funclet}) && \"Cannot lower callbrs with arbitrary operand bundles yet!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 2839, __PRETTY_FUNCTION__))
;
2840
2841 assert(I.isInlineAsm() && "Only know how to handle inlineasm callbr")((I.isInlineAsm() && "Only know how to handle inlineasm callbr"
) ? static_cast<void> (0) : __assert_fail ("I.isInlineAsm() && \"Only know how to handle inlineasm callbr\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 2841, __PRETTY_FUNCTION__))
;
2842 visitInlineAsm(I);
2843 CopyToExportRegsIfNeeded(&I);
2844
2845 // Retrieve successors.
2846 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getDefaultDest()];
2847
2848 // Update successor info.
2849 addSuccessorWithProb(CallBrMBB, Return, BranchProbability::getOne());
2850 for (unsigned i = 0, e = I.getNumIndirectDests(); i < e; ++i) {
2851 MachineBasicBlock *Target = FuncInfo.MBBMap[I.getIndirectDest(i)];
2852 addSuccessorWithProb(CallBrMBB, Target, BranchProbability::getZero());
2853 Target->setIsInlineAsmBrIndirectTarget();
2854 }
2855 CallBrMBB->normalizeSuccProbs();
2856
2857 // Drop into default successor.
2858 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
2859 MVT::Other, getControlRoot(),
2860 DAG.getBasicBlock(Return)));
2861}
2862
2863void SelectionDAGBuilder::visitResume(const ResumeInst &RI) {
2864 llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!")::llvm::llvm_unreachable_internal("SelectionDAGBuilder shouldn't visit resume instructions!"
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 2864)
;
2865}
2866
2867void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) {
2868 assert(FuncInfo.MBB->isEHPad() &&((FuncInfo.MBB->isEHPad() && "Call to landingpad not in landing pad!"
) ? static_cast<void> (0) : __assert_fail ("FuncInfo.MBB->isEHPad() && \"Call to landingpad not in landing pad!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 2869, __PRETTY_FUNCTION__))
2869 "Call to landingpad not in landing pad!")((FuncInfo.MBB->isEHPad() && "Call to landingpad not in landing pad!"
) ? static_cast<void> (0) : __assert_fail ("FuncInfo.MBB->isEHPad() && \"Call to landingpad not in landing pad!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 2869, __PRETTY_FUNCTION__))
;
2870
2871 // If there aren't registers to copy the values into (e.g., during SjLj
2872 // exceptions), then don't bother to create these DAG nodes.
2873 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2874 const Constant *PersonalityFn = FuncInfo.Fn->getPersonalityFn();
2875 if (TLI.getExceptionPointerRegister(PersonalityFn) == 0 &&
2876 TLI.getExceptionSelectorRegister(PersonalityFn) == 0)
2877 return;
2878
2879 // If landingpad's return type is token type, we don't create DAG nodes
2880 // for its exception pointer and selector value. The extraction of exception
2881 // pointer or selector value from token type landingpads is not currently
2882 // supported.
2883 if (LP.getType()->isTokenTy())
2884 return;
2885
2886 SmallVector<EVT, 2> ValueVTs;
2887 SDLoc dl = getCurSDLoc();
2888 ComputeValueVTs(TLI, DAG.getDataLayout(), LP.getType(), ValueVTs);
2889 assert(ValueVTs.size() == 2 && "Only two-valued landingpads are supported")((ValueVTs.size() == 2 && "Only two-valued landingpads are supported"
) ? static_cast<void> (0) : __assert_fail ("ValueVTs.size() == 2 && \"Only two-valued landingpads are supported\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 2889, __PRETTY_FUNCTION__))
;
2890
2891 // Get the two live-in registers as SDValues. The physregs have already been
2892 // copied into virtual registers.
2893 SDValue Ops[2];
2894 if (FuncInfo.ExceptionPointerVirtReg) {
2895 Ops[0] = DAG.getZExtOrTrunc(
2896 DAG.getCopyFromReg(DAG.getEntryNode(), dl,
2897 FuncInfo.ExceptionPointerVirtReg,
2898 TLI.getPointerTy(DAG.getDataLayout())),
2899 dl, ValueVTs[0]);
2900 } else {
2901 Ops[0] = DAG.getConstant(0, dl, TLI.getPointerTy(DAG.getDataLayout()));
2902 }
2903 Ops[1] = DAG.getZExtOrTrunc(
2904 DAG.getCopyFromReg(DAG.getEntryNode(), dl,
2905 FuncInfo.ExceptionSelectorVirtReg,
2906 TLI.getPointerTy(DAG.getDataLayout())),
2907 dl, ValueVTs[1]);
2908
2909 // Merge into one.
2910 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl,
2911 DAG.getVTList(ValueVTs), Ops);
2912 setValue(&LP, Res);
2913}
2914
2915void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First,
2916 MachineBasicBlock *Last) {
2917 // Update JTCases.
2918 for (unsigned i = 0, e = SL->JTCases.size(); i != e; ++i)
2919 if (SL->JTCases[i].first.HeaderBB == First)
2920 SL->JTCases[i].first.HeaderBB = Last;
2921
2922 // Update BitTestCases.
2923 for (unsigned i = 0, e = SL->BitTestCases.size(); i != e; ++i)
2924 if (SL->BitTestCases[i].Parent == First)
2925 SL->BitTestCases[i].Parent = Last;
2926}
2927
2928void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
2929 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB;
2930
2931 // Update machine-CFG edges with unique successors.
2932 SmallSet<BasicBlock*, 32> Done;
2933 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) {
2934 BasicBlock *BB = I.getSuccessor(i);
2935 bool Inserted = Done.insert(BB).second;
2936 if (!Inserted)
2937 continue;
2938
2939 MachineBasicBlock *Succ = FuncInfo.MBBMap[BB];
2940 addSuccessorWithProb(IndirectBrMBB, Succ);
2941 }
2942 IndirectBrMBB->normalizeSuccProbs();
2943
2944 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurSDLoc(),
2945 MVT::Other, getControlRoot(),
2946 getValue(I.getAddress())));
2947}
2948
2949void SelectionDAGBuilder::visitUnreachable(const UnreachableInst &I) {
2950 if (!DAG.getTarget().Options.TrapUnreachable)
2951 return;
2952
2953 // We may be able to ignore unreachable behind a noreturn call.
2954 if (DAG.getTarget().Options.NoTrapAfterNoreturn) {
2955 const BasicBlock &BB = *I.getParent();
2956 if (&I != &BB.front()) {
2957 BasicBlock::const_iterator PredI =
2958 std::prev(BasicBlock::const_iterator(&I));
2959 if (const CallInst *Call = dyn_cast<CallInst>(&*PredI)) {
2960 if (Call->doesNotReturn())
2961 return;
2962 }
2963 }
2964 }
2965
2966 DAG.setRoot(DAG.getNode(ISD::TRAP, getCurSDLoc(), MVT::Other, DAG.getRoot()));
2967}
2968
2969void SelectionDAGBuilder::visitUnary(const User &I, unsigned Opcode) {
2970 SDNodeFlags Flags;
2971
2972 SDValue Op = getValue(I.getOperand(0));
2973 SDValue UnNodeValue = DAG.getNode(Opcode, getCurSDLoc(), Op.getValueType(),
2974 Op, Flags);
2975 setValue(&I, UnNodeValue);
2976}
2977
2978void SelectionDAGBuilder::visitBinary(const User &I, unsigned Opcode) {
2979 SDNodeFlags Flags;
2980 if (auto *OFBinOp = dyn_cast<OverflowingBinaryOperator>(&I)) {
2981 Flags.setNoSignedWrap(OFBinOp->hasNoSignedWrap());
2982 Flags.setNoUnsignedWrap(OFBinOp->hasNoUnsignedWrap());
2983 }
2984 if (auto *ExactOp = dyn_cast<PossiblyExactOperator>(&I))
2985 Flags.setExact(ExactOp->isExact());
2986 if (auto *FPOp = dyn_cast<FPMathOperator>(&I))
2987 Flags.copyFMF(*FPOp);
2988
2989 SDValue Op1 = getValue(I.getOperand(0));
2990 SDValue Op2 = getValue(I.getOperand(1));
2991 SDValue BinNodeValue = DAG.getNode(Opcode, getCurSDLoc(), Op1.getValueType(),
2992 Op1, Op2, Flags);
2993 setValue(&I, BinNodeValue);
2994}
2995
2996void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
2997 SDValue Op1 = getValue(I.getOperand(0));
2998 SDValue Op2 = getValue(I.getOperand(1));
2999
3000 EVT ShiftTy = DAG.getTargetLoweringInfo().getShiftAmountTy(
3001 Op1.getValueType(), DAG.getDataLayout());
3002
3003 // Coerce the shift amount to the right type if we can.
3004 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) {
3005 unsigned ShiftSize = ShiftTy.getSizeInBits();
3006 unsigned Op2Size = Op2.getValueSizeInBits();
3007 SDLoc DL = getCurSDLoc();
3008
3009 // If the operand is smaller than the shift count type, promote it.
3010 if (ShiftSize > Op2Size)
3011 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2);
3012
3013 // If the operand is larger than the shift count type but the shift
3014 // count type has enough bits to represent any shift value, truncate
3015 // it now. This is a common case and it exposes the truncate to
3016 // optimization early.
3017 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueSizeInBits()))
3018 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2);
3019 // Otherwise we'll need to temporarily settle for some other convenient
3020 // type. Type legalization will make adjustments once the shiftee is split.
3021 else
3022 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32);
3023 }
3024
3025 bool nuw = false;
3026 bool nsw = false;
3027 bool exact = false;
3028
3029 if (Opcode == ISD::SRL || Opcode == ISD::SRA || Opcode == ISD::SHL) {
3030
3031 if (const OverflowingBinaryOperator *OFBinOp =
3032 dyn_cast<const OverflowingBinaryOperator>(&I)) {
3033 nuw = OFBinOp->hasNoUnsignedWrap();
3034 nsw = OFBinOp->hasNoSignedWrap();
3035 }
3036 if (const PossiblyExactOperator *ExactOp =
3037 dyn_cast<const PossiblyExactOperator>(&I))
3038 exact = ExactOp->isExact();
3039 }
3040 SDNodeFlags Flags;
3041 Flags.setExact(exact);
3042 Flags.setNoSignedWrap(nsw);
3043 Flags.setNoUnsignedWrap(nuw);
3044 SDValue Res = DAG.getNode(Opcode, getCurSDLoc(), Op1.getValueType(), Op1, Op2,
3045 Flags);
3046 setValue(&I, Res);
3047}
3048
3049void SelectionDAGBuilder::visitSDiv(const User &I) {
3050 SDValue Op1 = getValue(I.getOperand(0));
3051 SDValue Op2 = getValue(I.getOperand(1));
3052
3053 SDNodeFlags Flags;
3054 Flags.setExact(isa<PossiblyExactOperator>(&I) &&
3055 cast<PossiblyExactOperator>(&I)->isExact());
3056 setValue(&I, DAG.getNode(ISD::SDIV, getCurSDLoc(), Op1.getValueType(), Op1,
3057 Op2, Flags));
3058}
3059
3060void SelectionDAGBuilder::visitICmp(const User &I) {
3061 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
3062 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I))
3063 predicate = IC->getPredicate();
3064 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
3065 predicate = ICmpInst::Predicate(IC->getPredicate());
3066 SDValue Op1 = getValue(I.getOperand(0));
3067 SDValue Op2 = getValue(I.getOperand(1));
3068 ISD::CondCode Opcode = getICmpCondCode(predicate);
3069
3070 auto &TLI = DAG.getTargetLoweringInfo();
3071 EVT MemVT =
3072 TLI.getMemValueType(DAG.getDataLayout(), I.getOperand(0)->getType());
3073
3074 // If a pointer's DAG type is larger than its memory type then the DAG values
3075 // are zero-extended. This breaks signed comparisons so truncate back to the
3076 // underlying type before doing the compare.
3077 if (Op1.getValueType() != MemVT) {
3078 Op1 = DAG.getPtrExtOrTrunc(Op1, getCurSDLoc(), MemVT);
3079 Op2 = DAG.getPtrExtOrTrunc(Op2, getCurSDLoc(), MemVT);
3080 }
3081
3082 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
3083 I.getType());
3084 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Opcode));
3085}
3086
3087void SelectionDAGBuilder::visitFCmp(const User &I) {
3088 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
3089 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I))
3090 predicate = FC->getPredicate();
3091 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
3092 predicate = FCmpInst::Predicate(FC->getPredicate());
3093 SDValue Op1 = getValue(I.getOperand(0));
3094 SDValue Op2 = getValue(I.getOperand(1));
3095
3096 ISD::CondCode Condition = getFCmpCondCode(predicate);
3097 auto *FPMO = cast<FPMathOperator>(&I);
3098 if (FPMO->hasNoNaNs() || TM.Options.NoNaNsFPMath)
3099 Condition = getFCmpCodeWithoutNaN(Condition);
3100
3101 SDNodeFlags Flags;
3102 Flags.copyFMF(*FPMO);
3103 SelectionDAG::FlagInserter FlagsInserter(DAG, Flags);
3104
3105 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
3106 I.getType());
3107 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Condition));
3108}
3109
3110// Check if the condition of the select has one use or two users that are both
3111// selects with the same condition.
3112static bool hasOnlySelectUsers(const Value *Cond) {
3113 return llvm::all_of(Cond->users(), [](const Value *V) {
3114 return isa<SelectInst>(V);
3115 });
3116}
3117
3118void SelectionDAGBuilder::visitSelect(const User &I) {
3119 SmallVector<EVT, 4> ValueVTs;
3120 ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(), I.getType(),
3121 ValueVTs);
3122 unsigned NumValues = ValueVTs.size();
3123 if (NumValues == 0) return;
3124
3125 SmallVector<SDValue, 4> Values(NumValues);
3126 SDValue Cond = getValue(I.getOperand(0));
3127 SDValue LHSVal = getValue(I.getOperand(1));
3128 SDValue RHSVal = getValue(I.getOperand(2));
3129 SmallVector<SDValue, 1> BaseOps(1, Cond);
3130 ISD::NodeType OpCode =
3131 Cond.getValueType().isVector() ? ISD::VSELECT : ISD::SELECT;
3132
3133 bool IsUnaryAbs = false;
3134 bool Negate = false;
3135
3136 SDNodeFlags Flags;
3137 if (auto *FPOp = dyn_cast<FPMathOperator>(&I))
3138 Flags.copyFMF(*FPOp);
3139
3140 // Min/max matching is only viable if all output VTs are the same.
3141 if (is_splat(ValueVTs)) {
3142 EVT VT = ValueVTs[0];
3143 LLVMContext &Ctx = *DAG.getContext();
3144 auto &TLI = DAG.getTargetLoweringInfo();
3145
3146 // We care about the legality of the operation after it has been type
3147 // legalized.
3148 while (TLI.getTypeAction(Ctx, VT) != TargetLoweringBase::TypeLegal)
3149 VT = TLI.getTypeToTransformTo(Ctx, VT);
3150
3151 // If the vselect is legal, assume we want to leave this as a vector setcc +
3152 // vselect. Otherwise, if this is going to be scalarized, we want to see if
3153 // min/max is legal on the scalar type.
3154 bool UseScalarMinMax = VT.isVector() &&
3155 !TLI.isOperationLegalOrCustom(ISD::VSELECT, VT);
3156
3157 Value *LHS, *RHS;
3158 auto SPR = matchSelectPattern(const_cast<User*>(&I), LHS, RHS);
3159 ISD::NodeType Opc = ISD::DELETED_NODE;
3160 switch (SPR.Flavor) {
3161 case SPF_UMAX: Opc = ISD::UMAX; break;
3162 case SPF_UMIN: Opc = ISD::UMIN; break;
3163 case SPF_SMAX: Opc = ISD::SMAX; break;
3164 case SPF_SMIN: Opc = ISD::SMIN; break;
3165 case SPF_FMINNUM:
3166 switch (SPR.NaNBehavior) {
3167 case SPNB_NA: llvm_unreachable("No NaN behavior for FP op?")::llvm::llvm_unreachable_internal("No NaN behavior for FP op?"
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 3167)
;
3168 case SPNB_RETURNS_NAN: Opc = ISD::FMINIMUM; break;
3169 case SPNB_RETURNS_OTHER: Opc = ISD::FMINNUM; break;
3170 case SPNB_RETURNS_ANY: {
3171 if (TLI.isOperationLegalOrCustom(ISD::FMINNUM, VT))
3172 Opc = ISD::FMINNUM;
3173 else if (TLI.isOperationLegalOrCustom(ISD::FMINIMUM, VT))
3174 Opc = ISD::FMINIMUM;
3175 else if (UseScalarMinMax)
3176 Opc = TLI.isOperationLegalOrCustom(ISD::FMINNUM, VT.getScalarType()) ?
3177 ISD::FMINNUM : ISD::FMINIMUM;
3178 break;
3179 }
3180 }
3181 break;
3182 case SPF_FMAXNUM:
3183 switch (SPR.NaNBehavior) {
3184 case SPNB_NA: llvm_unreachable("No NaN behavior for FP op?")::llvm::llvm_unreachable_internal("No NaN behavior for FP op?"
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 3184)
;
3185 case SPNB_RETURNS_NAN: Opc = ISD::FMAXIMUM; break;
3186 case SPNB_RETURNS_OTHER: Opc = ISD::FMAXNUM; break;
3187 case SPNB_RETURNS_ANY:
3188
3189 if (TLI.isOperationLegalOrCustom(ISD::FMAXNUM, VT))
3190 Opc = ISD::FMAXNUM;
3191 else if (TLI.isOperationLegalOrCustom(ISD::FMAXIMUM, VT))
3192 Opc = ISD::FMAXIMUM;
3193 else if (UseScalarMinMax)
3194 Opc = TLI.isOperationLegalOrCustom(ISD::FMAXNUM, VT.getScalarType()) ?
3195 ISD::FMAXNUM : ISD::FMAXIMUM;
3196 break;
3197 }
3198 break;
3199 case SPF_NABS:
3200 Negate = true;
3201 LLVM_FALLTHROUGH[[gnu::fallthrough]];
3202 case SPF_ABS:
3203 IsUnaryAbs = true;
3204 Opc = ISD::ABS;
3205 break;
3206 default: break;
3207 }
3208
3209 if (!IsUnaryAbs && Opc != ISD::DELETED_NODE &&
3210 (TLI.isOperationLegalOrCustom(Opc, VT) ||
3211 (UseScalarMinMax &&
3212 TLI.isOperationLegalOrCustom(Opc, VT.getScalarType()))) &&
3213 // If the underlying comparison instruction is used by any other
3214 // instruction, the consumed instructions won't be destroyed, so it is
3215 // not profitable to convert to a min/max.
3216 hasOnlySelectUsers(cast<SelectInst>(I).getCondition())) {
3217 OpCode = Opc;
3218 LHSVal = getValue(LHS);
3219 RHSVal = getValue(RHS);
3220 BaseOps.clear();
3221 }
3222
3223 if (IsUnaryAbs) {
3224 OpCode = Opc;
3225 LHSVal = getValue(LHS);
3226 BaseOps.clear();
3227 }
3228 }
3229
3230 if (IsUnaryAbs) {
3231 for (unsigned i = 0; i != NumValues; ++i) {
3232 SDLoc dl = getCurSDLoc();
3233 EVT VT = LHSVal.getNode()->getValueType(LHSVal.getResNo() + i);
3234 Values[i] =
3235 DAG.getNode(OpCode, dl, VT, LHSVal.getValue(LHSVal.getResNo() + i));
3236 if (Negate)
3237 Values[i] = DAG.getNode(ISD::SUB, dl, VT, DAG.getConstant(0, dl, VT),
3238 Values[i]);
3239 }
3240 } else {
3241 for (unsigned i = 0; i != NumValues; ++i) {
3242 SmallVector<SDValue, 3> Ops(BaseOps.begin(), BaseOps.end());
3243 Ops.push_back(SDValue(LHSVal.getNode(), LHSVal.getResNo() + i));
3244 Ops.push_back(SDValue(RHSVal.getNode(), RHSVal.getResNo() + i));
3245 Values[i] = DAG.getNode(
3246 OpCode, getCurSDLoc(),
3247 LHSVal.getNode()->getValueType(LHSVal.getResNo() + i), Ops, Flags);
3248 }
3249 }
3250
3251 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
3252 DAG.getVTList(ValueVTs), Values));
3253}
3254
3255void SelectionDAGBuilder::visitTrunc(const User &I) {
3256 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
3257 SDValue N = getValue(I.getOperand(0));
3258 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
3259 I.getType());
3260 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), DestVT, N));
3261}
3262
3263void SelectionDAGBuilder::visitZExt(const User &I) {
3264 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
3265 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
3266 SDValue N = getValue(I.getOperand(0));
3267 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
3268 I.getType());
3269 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurSDLoc(), DestVT, N));
3270}
3271
3272void SelectionDAGBuilder::visitSExt(const User &I) {
3273 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
3274 // SExt also can't be a cast to bool for same reason. So, nothing much to do
3275 SDValue N = getValue(I.getOperand(0));
3276 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
3277 I.getType());
3278 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurSDLoc(), DestVT, N));
3279}
3280
3281void SelectionDAGBuilder::visitFPTrunc(const User &I) {
3282 // FPTrunc is never a no-op cast, no need to check
3283 SDValue N = getValue(I.getOperand(0));
3284 SDLoc dl = getCurSDLoc();
3285 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3286 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
3287 setValue(&I, DAG.getNode(ISD::FP_ROUND, dl, DestVT, N,
3288 DAG.getTargetConstant(
3289 0, dl, TLI.getPointerTy(DAG.getDataLayout()))));
3290}
3291
3292void SelectionDAGBuilder::visitFPExt(const User &I) {
3293 // FPExt is never a no-op cast, no need to check
3294 SDValue N = getValue(I.getOperand(0));
3295 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
3296 I.getType());
3297 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurSDLoc(), DestVT, N));
3298}
3299
3300void SelectionDAGBuilder::visitFPToUI(const User &I) {
3301 // FPToUI is never a no-op cast, no need to check
3302 SDValue N = getValue(I.getOperand(0));
3303 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
3304 I.getType());
3305 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurSDLoc(), DestVT, N));
3306}
3307
3308void SelectionDAGBuilder::visitFPToSI(const User &I) {
3309 // FPToSI is never a no-op cast, no need to check
3310 SDValue N = getValue(I.getOperand(0));
3311 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
3312 I.getType());
3313 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurSDLoc(), DestVT, N));
3314}
3315
3316void SelectionDAGBuilder::visitUIToFP(const User &I) {
3317 // UIToFP is never a no-op cast, no need to check
3318 SDValue N = getValue(I.getOperand(0));
3319 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
3320 I.getType());
3321 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurSDLoc(), DestVT, N));
3322}
3323
3324void SelectionDAGBuilder::visitSIToFP(const User &I) {
3325 // SIToFP is never a no-op cast, no need to check
3326 SDValue N = getValue(I.getOperand(0));
3327 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
3328 I.getType());
3329 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurSDLoc(), DestVT, N));
3330}
3331
3332void SelectionDAGBuilder::visitPtrToInt(const User &I) {
3333 // What to do depends on the size of the integer and the size of the pointer.
3334 // We can either truncate, zero extend, or no-op, accordingly.
3335 SDValue N = getValue(I.getOperand(0));
3336 auto &TLI = DAG.getTargetLoweringInfo();
3337 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
3338 I.getType());
3339 EVT PtrMemVT =
3340 TLI.getMemValueType(DAG.getDataLayout(), I.getOperand(0)->getType());
3341 N = DAG.getPtrExtOrTrunc(N, getCurSDLoc(), PtrMemVT);
3342 N = DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT);
3343 setValue(&I, N);
3344}
3345
3346void SelectionDAGBuilder::visitIntToPtr(const User &I) {
3347 // What to do depends on the size of the integer and the size of the pointer.
3348 // We can either truncate, zero extend, or no-op, accordingly.
3349 SDValue N = getValue(I.getOperand(0));
3350 auto &TLI = DAG.getTargetLoweringInfo();
3351 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
3352 EVT PtrMemVT = TLI.getMemValueType(DAG.getDataLayout(), I.getType());
3353 N = DAG.getZExtOrTrunc(N, getCurSDLoc(), PtrMemVT);
3354 N = DAG.getPtrExtOrTrunc(N, getCurSDLoc(), DestVT);
3355 setValue(&I, N);
3356}
3357
3358void SelectionDAGBuilder::visitBitCast(const User &I) {
3359 SDValue N = getValue(I.getOperand(0));
3360 SDLoc dl = getCurSDLoc();
3361 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
3362 I.getType());
3363
3364 // BitCast assures us that source and destination are the same size so this is
3365 // either a BITCAST or a no-op.
3366 if (DestVT != N.getValueType())
3367 setValue(&I, DAG.getNode(ISD::BITCAST, dl,
3368 DestVT, N)); // convert types.
3369 // Check if the original LLVM IR Operand was a ConstantInt, because getValue()
3370 // might fold any kind of constant expression to an integer constant and that
3371 // is not what we are looking for. Only recognize a bitcast of a genuine
3372 // constant integer as an opaque constant.
3373 else if(ConstantInt *C = dyn_cast<ConstantInt>(I.getOperand(0)))
3374 setValue(&I, DAG.getConstant(C->getValue(), dl, DestVT, /*isTarget=*/false,
3375 /*isOpaque*/true));
3376 else
3377 setValue(&I, N); // noop cast.
3378}
3379
3380void SelectionDAGBuilder::visitAddrSpaceCast(const User &I) {
3381 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3382 const Value *SV = I.getOperand(0);
3383 SDValue N = getValue(SV);
3384 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
3385
3386 unsigned SrcAS = SV->getType()->getPointerAddressSpace();
3387 unsigned DestAS = I.getType()->getPointerAddressSpace();
3388
3389 if (!TM.isNoopAddrSpaceCast(SrcAS, DestAS))
3390 N = DAG.getAddrSpaceCast(getCurSDLoc(), DestVT, N, SrcAS, DestAS);
3391
3392 setValue(&I, N);
3393}
3394
3395void SelectionDAGBuilder::visitInsertElement(const User &I) {
3396 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3397 SDValue InVec = getValue(I.getOperand(0));
3398 SDValue InVal = getValue(I.getOperand(1));
3399 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(2)), getCurSDLoc(),
3400 TLI.getVectorIdxTy(DAG.getDataLayout()));
3401 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurSDLoc(),
3402 TLI.getValueType(DAG.getDataLayout(), I.getType()),
3403 InVec, InVal, InIdx));
3404}
3405
3406void SelectionDAGBuilder::visitExtractElement(const User &I) {
3407 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3408 SDValue InVec = getValue(I.getOperand(0));
3409 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(1)), getCurSDLoc(),
3410 TLI.getVectorIdxTy(DAG.getDataLayout()));
3411 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(),
3412 TLI.getValueType(DAG.getDataLayout(), I.getType()),
3413 InVec, InIdx));
3414}
3415
3416void SelectionDAGBuilder::visitShuffleVector(const User &I) {
3417 SDValue Src1 = getValue(I.getOperand(0));
3418 SDValue Src2 = getValue(I.getOperand(1));
3419 ArrayRef<int> Mask;
3420 if (auto *SVI = dyn_cast<ShuffleVectorInst>(&I))
3421 Mask = SVI->getShuffleMask();
3422 else
3423 Mask = cast<ConstantExpr>(I).getShuffleMask();
3424 SDLoc DL = getCurSDLoc();
3425 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3426 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
3427 EVT SrcVT = Src1.getValueType();
3428
3429 if (all_of(Mask, [](int Elem) { return Elem == 0; }) &&
3430 VT.isScalableVector()) {
3431 // Canonical splat form of first element of first input vector.
3432 SDValue FirstElt =
3433 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, SrcVT.getScalarType(), Src1,
3434 DAG.getVectorIdxConstant(0, DL));
3435 setValue(&I, DAG.getNode(ISD::SPLAT_VECTOR, DL, VT, FirstElt));
3436 return;
3437 }
3438
3439 // For now, we only handle splats for scalable vectors.
3440 // The DAGCombiner will perform a BUILD_VECTOR -> SPLAT_VECTOR transformation
3441 // for targets that support a SPLAT_VECTOR for non-scalable vector types.
3442 assert(!VT.isScalableVector() && "Unsupported scalable vector shuffle")((!VT.isScalableVector() && "Unsupported scalable vector shuffle"
) ? static_cast<void> (0) : __assert_fail ("!VT.isScalableVector() && \"Unsupported scalable vector shuffle\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 3442, __PRETTY_FUNCTION__))
;
3443
3444 unsigned SrcNumElts = SrcVT.getVectorNumElements();
3445 unsigned MaskNumElts = Mask.size();
3446
3447 if (SrcNumElts == MaskNumElts) {
3448 setValue(&I, DAG.getVectorShuffle(VT, DL, Src1, Src2, Mask));
3449 return;
3450 }
3451
3452 // Normalize the shuffle vector since mask and vector length don't match.
3453 if (SrcNumElts < MaskNumElts) {
3454 // Mask is longer than the source vectors. We can use concatenate vector to
3455 // make the mask and vectors lengths match.
3456
3457 if (MaskNumElts % SrcNumElts == 0) {
3458 // Mask length is a multiple of the source vector length.
3459 // Check if the shuffle is some kind of concatenation of the input
3460 // vectors.
3461 unsigned NumConcat = MaskNumElts / SrcNumElts;
3462 bool IsConcat = true;
3463 SmallVector<int, 8> ConcatSrcs(NumConcat, -1);
3464 for (unsigned i = 0; i != MaskNumElts; ++i) {
3465 int Idx = Mask[i];
3466 if (Idx < 0)
3467 continue;
3468 // Ensure the indices in each SrcVT sized piece are sequential and that
3469 // the same source is used for the whole piece.
3470 if ((Idx % SrcNumElts != (i % SrcNumElts)) ||
3471 (ConcatSrcs[i / SrcNumElts] >= 0 &&
3472 ConcatSrcs[i / SrcNumElts] != (int)(Idx / SrcNumElts))) {
3473 IsConcat = false;
3474 break;
3475 }
3476 // Remember which source this index came from.
3477 ConcatSrcs[i / SrcNumElts] = Idx / SrcNumElts;
3478 }
3479
3480 // The shuffle is concatenating multiple vectors together. Just emit
3481 // a CONCAT_VECTORS operation.
3482 if (IsConcat) {
3483 SmallVector<SDValue, 8> ConcatOps;
3484 for (auto Src : ConcatSrcs) {
3485 if (Src < 0)
3486 ConcatOps.push_back(DAG.getUNDEF(SrcVT));
3487 else if (Src == 0)
3488 ConcatOps.push_back(Src1);
3489 else
3490 ConcatOps.push_back(Src2);
3491 }
3492 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, ConcatOps));
3493 return;
3494 }
3495 }
3496
3497 unsigned PaddedMaskNumElts = alignTo(MaskNumElts, SrcNumElts);
3498 unsigned NumConcat = PaddedMaskNumElts / SrcNumElts;
3499 EVT PaddedVT = EVT::getVectorVT(*DAG.getContext(), VT.getScalarType(),
3500 PaddedMaskNumElts);
3501
3502 // Pad both vectors with undefs to make them the same length as the mask.
3503 SDValue UndefVal = DAG.getUNDEF(SrcVT);
3504
3505 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
3506 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
3507 MOps1[0] = Src1;
3508 MOps2[0] = Src2;
3509
3510 Src1 = DAG.getNode(ISD::CONCAT_VECTORS, DL, PaddedVT, MOps1);
3511 Src2 = DAG.getNode(ISD::CONCAT_VECTORS, DL, PaddedVT, MOps2);
3512
3513 // Readjust mask for new input vector length.
3514 SmallVector<int, 8> MappedOps(PaddedMaskNumElts, -1);
3515 for (unsigned i = 0; i != MaskNumElts; ++i) {
3516 int Idx = Mask[i];
3517 if (Idx >= (int)SrcNumElts)
3518 Idx -= SrcNumElts - PaddedMaskNumElts;
3519 MappedOps[i] = Idx;
3520 }
3521
3522 SDValue Result = DAG.getVectorShuffle(PaddedVT, DL, Src1, Src2, MappedOps);
3523
3524 // If the concatenated vector was padded, extract a subvector with the
3525 // correct number of elements.
3526 if (MaskNumElts != PaddedMaskNumElts)
3527 Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, Result,
3528 DAG.getVectorIdxConstant(0, DL));
3529
3530 setValue(&I, Result);
3531 return;
3532 }
3533
3534 if (SrcNumElts > MaskNumElts) {
3535 // Analyze the access pattern of the vector to see if we can extract
3536 // two subvectors and do the shuffle.
3537 int StartIdx[2] = { -1, -1 }; // StartIdx to extract from
3538 bool CanExtract = true;
3539 for (int Idx : Mask) {
3540 unsigned Input = 0;
3541 if (Idx < 0)
3542 continue;
3543
3544 if (Idx >= (int)SrcNumElts) {
3545 Input = 1;
3546 Idx -= SrcNumElts;
3547 }
3548
3549 // If all the indices come from the same MaskNumElts sized portion of
3550 // the sources we can use extract. Also make sure the extract wouldn't
3551 // extract past the end of the source.
3552 int NewStartIdx = alignDown(Idx, MaskNumElts);
3553 if (NewStartIdx + MaskNumElts > SrcNumElts ||
3554 (StartIdx[Input] >= 0 && StartIdx[Input] != NewStartIdx))
3555 CanExtract = false;
3556 // Make sure we always update StartIdx as we use it to track if all
3557 // elements are undef.
3558 StartIdx[Input] = NewStartIdx;
3559 }
3560
3561 if (StartIdx[0] < 0 && StartIdx[1] < 0) {
3562 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
3563 return;
3564 }
3565 if (CanExtract) {
3566 // Extract appropriate subvector and generate a vector shuffle
3567 for (unsigned Input = 0; Input < 2; ++Input) {
3568 SDValue &Src = Input == 0 ? Src1 : Src2;
3569 if (StartIdx[Input] < 0)
3570 Src = DAG.getUNDEF(VT);
3571 else {
3572 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, Src,
3573 DAG.getVectorIdxConstant(StartIdx[Input], DL));
3574 }
3575 }
3576
3577 // Calculate new mask.
3578 SmallVector<int, 8> MappedOps(Mask.begin(), Mask.end());
3579 for (int &Idx : MappedOps) {
3580 if (Idx >= (int)SrcNumElts)
3581 Idx -= SrcNumElts + StartIdx[1] - MaskNumElts;
3582 else if (Idx >= 0)
3583 Idx -= StartIdx[0];
3584 }
3585
3586 setValue(&I, DAG.getVectorShuffle(VT, DL, Src1, Src2, MappedOps));
3587 return;
3588 }
3589 }
3590
3591 // We can't use either concat vectors or extract subvectors so fall back to
3592 // replacing the shuffle with extract and build vector.
3593 // to insert and build vector.
3594 EVT EltVT = VT.getVectorElementType();
3595 SmallVector<SDValue,8> Ops;
3596 for (int Idx : Mask) {
3597 SDValue Res;
3598
3599 if (Idx < 0) {
3600 Res = DAG.getUNDEF(EltVT);
3601 } else {
3602 SDValue &Src = Idx < (int)SrcNumElts ? Src1 : Src2;
3603 if (Idx >= (int)SrcNumElts) Idx -= SrcNumElts;
3604
3605 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, Src,
3606 DAG.getVectorIdxConstant(Idx, DL));
3607 }
3608
3609 Ops.push_back(Res);
3610 }
3611
3612 setValue(&I, DAG.getBuildVector(VT, DL, Ops));
3613}
3614
3615void SelectionDAGBuilder::visitInsertValue(const User &I) {
3616 ArrayRef<unsigned> Indices;
3617 if (const InsertValueInst *IV = dyn_cast<InsertValueInst>(&I))
3618 Indices = IV->getIndices();
3619 else
3620 Indices = cast<ConstantExpr>(&I)->getIndices();
3621
3622 const Value *Op0 = I.getOperand(0);
3623 const Value *Op1 = I.getOperand(1);
3624 Type *AggTy = I.getType();
3625 Type *ValTy = Op1->getType();
3626 bool IntoUndef = isa<UndefValue>(Op0);
3627 bool FromUndef = isa<UndefValue>(Op1);
3628
3629 unsigned LinearIndex = ComputeLinearIndex(AggTy, Indices);
3630
3631 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3632 SmallVector<EVT, 4> AggValueVTs;
3633 ComputeValueVTs(TLI, DAG.getDataLayout(), AggTy, AggValueVTs);
3634 SmallVector<EVT, 4> ValValueVTs;
3635 ComputeValueVTs(TLI, DAG.getDataLayout(), ValTy, ValValueVTs);
3636
3637 unsigned NumAggValues = AggValueVTs.size();
3638 unsigned NumValValues = ValValueVTs.size();
3639 SmallVector<SDValue, 4> Values(NumAggValues);
3640
3641 // Ignore an insertvalue that produces an empty object
3642 if (!NumAggValues) {
3643 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
3644 return;
3645 }
3646
3647 SDValue Agg = getValue(Op0);
3648 unsigned i = 0;
3649 // Copy the beginning value(s) from the original aggregate.
3650 for (; i != LinearIndex; ++i)
3651 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3652 SDValue(Agg.getNode(), Agg.getResNo() + i);
3653 // Copy values from the inserted value(s).
3654 if (NumValValues) {
3655 SDValue Val = getValue(Op1);
3656 for (; i != LinearIndex + NumValValues; ++i)
3657 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3658 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
3659 }
3660 // Copy remaining value(s) from the original aggregate.
3661 for (; i != NumAggValues; ++i)
3662 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3663 SDValue(Agg.getNode(), Agg.getResNo() + i);
3664
3665 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
3666 DAG.getVTList(AggValueVTs), Values));
3667}
3668
3669void SelectionDAGBuilder::visitExtractValue(const User &I) {
3670 ArrayRef<unsigned> Indices;
3671 if (const ExtractValueInst *EV = dyn_cast<ExtractValueInst>(&I))
3672 Indices = EV->getIndices();
3673 else
3674 Indices = cast<ConstantExpr>(&I)->getIndices();
3675
3676 const Value *Op0 = I.getOperand(0);
3677 Type *AggTy = Op0->getType();
3678 Type *ValTy = I.getType();
3679 bool OutOfUndef = isa<UndefValue>(Op0);
3680
3681 unsigned LinearIndex = ComputeLinearIndex(AggTy, Indices);
3682
3683 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3684 SmallVector<EVT, 4> ValValueVTs;
3685 ComputeValueVTs(TLI, DAG.getDataLayout(), ValTy, ValValueVTs);
3686
3687 unsigned NumValValues = ValValueVTs.size();
3688
3689 // Ignore a extractvalue that produces an empty object
3690 if (!NumValValues) {
3691 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
3692 return;
3693 }
3694
3695 SmallVector<SDValue, 4> Values(NumValValues);
3696
3697 SDValue Agg = getValue(Op0);
3698 // Copy out the selected value(s).
3699 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
3700 Values[i - LinearIndex] =
3701 OutOfUndef ?
3702 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
3703 SDValue(Agg.getNode(), Agg.getResNo() + i);
3704
3705 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
3706 DAG.getVTList(ValValueVTs), Values));
3707}
3708
3709void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
3710 Value *Op0 = I.getOperand(0);
3711 // Note that the pointer operand may be a vector of pointers. Take the scalar
3712 // element which holds a pointer.
3713 unsigned AS = Op0->getType()->getScalarType()->getPointerAddressSpace();
3714 SDValue N = getValue(Op0);
3715 SDLoc dl = getCurSDLoc();
3716 auto &TLI = DAG.getTargetLoweringInfo();
3717
3718 // Normalize Vector GEP - all scalar operands should be converted to the
3719 // splat vector.
3720 bool IsVectorGEP = I.getType()->isVectorTy();
3721 ElementCount VectorElementCount =
3722 IsVectorGEP ? cast<VectorType>(I.getType())->getElementCount()
3723 : ElementCount::getFixed(0);
3724
3725 if (IsVectorGEP && !N.getValueType().isVector()) {
3726 LLVMContext &Context = *DAG.getContext();
3727 EVT VT = EVT::getVectorVT(Context, N.getValueType(), VectorElementCount);
3728 if (VectorElementCount.isScalable())
3729 N = DAG.getSplatVector(VT, dl, N);
3730 else
3731 N = DAG.getSplatBuildVector(VT, dl, N);
3732 }
3733
3734 for (gep_type_iterator GTI = gep_type_begin(&I), E = gep_type_end(&I);
3735 GTI != E; ++GTI) {
3736 const Value *Idx = GTI.getOperand();
3737 if (StructType *StTy = GTI.getStructTypeOrNull()) {
3738 unsigned Field = cast<Constant>(Idx)->getUniqueInteger().getZExtValue();
3739 if (Field) {
3740 // N = N + Offset
3741 uint64_t Offset = DL->getStructLayout(StTy)->getElementOffset(Field);
3742
3743 // In an inbounds GEP with an offset that is nonnegative even when
3744 // interpreted as signed, assume there is no unsigned overflow.
3745 SDNodeFlags Flags;
3746 if (int64_t(Offset) >= 0 && cast<GEPOperator>(I).isInBounds())
3747 Flags.setNoUnsignedWrap(true);
3748
3749 N = DAG.getNode(ISD::ADD, dl, N.getValueType(), N,
3750 DAG.getConstant(Offset, dl, N.getValueType()), Flags);
3751 }
3752 } else {
3753 // IdxSize is the width of the arithmetic according to IR semantics.
3754 // In SelectionDAG, we may prefer to do arithmetic in a wider bitwidth
3755 // (and fix up the result later).
3756 unsigned IdxSize = DAG.getDataLayout().getIndexSizeInBits(AS);
3757 MVT IdxTy = MVT::getIntegerVT(IdxSize);
3758 TypeSize ElementSize = DL->getTypeAllocSize(GTI.getIndexedType());
3759 // We intentionally mask away the high bits here; ElementSize may not
3760 // fit in IdxTy.
3761 APInt ElementMul(IdxSize, ElementSize.getKnownMinSize());
3762 bool ElementScalable = ElementSize.isScalable();
3763
3764 // If this is a scalar constant or a splat vector of constants,
3765 // handle it quickly.
3766 const auto *C = dyn_cast<Constant>(Idx);
3767 if (C && isa<VectorType>(C->getType()))
3768 C = C->getSplatValue();
3769
3770 const auto *CI = dyn_cast_or_null<ConstantInt>(C);
3771 if (CI && CI->isZero())
3772 continue;
3773 if (CI && !ElementScalable) {
3774 APInt Offs = ElementMul * CI->getValue().sextOrTrunc(IdxSize);
3775 LLVMContext &Context = *DAG.getContext();
3776 SDValue OffsVal;
3777 if (IsVectorGEP)
3778 OffsVal = DAG.getConstant(
3779 Offs, dl, EVT::getVectorVT(Context, IdxTy, VectorElementCount));
3780 else
3781 OffsVal = DAG.getConstant(Offs, dl, IdxTy);
3782
3783 // In an inbounds GEP with an offset that is nonnegative even when
3784 // interpreted as signed, assume there is no unsigned overflow.
3785 SDNodeFlags Flags;
3786 if (Offs.isNonNegative() && cast<GEPOperator>(I).isInBounds())
3787 Flags.setNoUnsignedWrap(true);
3788
3789 OffsVal = DAG.getSExtOrTrunc(OffsVal, dl, N.getValueType());
3790
3791 N = DAG.getNode(ISD::ADD, dl, N.getValueType(), N, OffsVal, Flags);
3792 continue;
3793 }
3794
3795 // N = N + Idx * ElementMul;
3796 SDValue IdxN = getValue(Idx);
3797
3798 if (!IdxN.getValueType().isVector() && IsVectorGEP) {
3799 EVT VT = EVT::getVectorVT(*Context, IdxN.getValueType(),
3800 VectorElementCount);
3801 if (VectorElementCount.isScalable())
3802 IdxN = DAG.getSplatVector(VT, dl, IdxN);
3803 else
3804 IdxN = DAG.getSplatBuildVector(VT, dl, IdxN);
3805 }
3806
3807 // If the index is smaller or larger than intptr_t, truncate or extend
3808 // it.
3809 IdxN = DAG.getSExtOrTrunc(IdxN, dl, N.getValueType());
3810
3811 if (ElementScalable) {
3812 EVT VScaleTy = N.getValueType().getScalarType();
3813 SDValue VScale = DAG.getNode(
3814 ISD::VSCALE, dl, VScaleTy,
3815 DAG.getConstant(ElementMul.getZExtValue(), dl, VScaleTy));
3816 if (IsVectorGEP)
3817 VScale = DAG.getSplatVector(N.getValueType(), dl, VScale);
3818 IdxN = DAG.getNode(ISD::MUL, dl, N.getValueType(), IdxN, VScale);
3819 } else {
3820 // If this is a multiply by a power of two, turn it into a shl
3821 // immediately. This is a very common case.
3822 if (ElementMul != 1) {
3823 if (ElementMul.isPowerOf2()) {
3824 unsigned Amt = ElementMul.logBase2();
3825 IdxN = DAG.getNode(ISD::SHL, dl,
3826 N.getValueType(), IdxN,
3827 DAG.getConstant(Amt, dl, IdxN.getValueType()));
3828 } else {
3829 SDValue Scale = DAG.getConstant(ElementMul.getZExtValue(), dl,
3830 IdxN.getValueType());
3831 IdxN = DAG.getNode(ISD::MUL, dl,
3832 N.getValueType(), IdxN, Scale);
3833 }
3834 }
3835 }
3836
3837 N = DAG.getNode(ISD::ADD, dl,
3838 N.getValueType(), N, IdxN);
3839 }
3840 }
3841
3842 MVT PtrTy = TLI.getPointerTy(DAG.getDataLayout(), AS);
3843 MVT PtrMemTy = TLI.getPointerMemTy(DAG.getDataLayout(), AS);
3844 if (IsVectorGEP) {
3845 PtrTy = MVT::getVectorVT(PtrTy, VectorElementCount);
3846 PtrMemTy = MVT::getVectorVT(PtrMemTy, VectorElementCount);
3847 }
3848
3849 if (PtrMemTy != PtrTy && !cast<GEPOperator>(I).isInBounds())
3850 N = DAG.getPtrExtendInReg(N, dl, PtrMemTy);
3851
3852 setValue(&I, N);
3853}
3854
3855void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
3856 // If this is a fixed sized alloca in the entry block of the function,
3857 // allocate it statically on the stack.
3858 if (FuncInfo.StaticAllocaMap.count(&I))
3859 return; // getValue will auto-populate this.
3860
3861 SDLoc dl = getCurSDLoc();
3862 Type *Ty = I.getAllocatedType();
3863 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3864 auto &DL = DAG.getDataLayout();
3865 uint64_t TySize = DL.getTypeAllocSize(Ty);
3866 MaybeAlign Alignment = std::max(DL.getPrefTypeAlign(Ty), I.getAlign());
3867
3868 SDValue AllocSize = getValue(I.getArraySize());
3869
3870 EVT IntPtr = TLI.getPointerTy(DAG.getDataLayout(), DL.getAllocaAddrSpace());
3871 if (AllocSize.getValueType() != IntPtr)
3872 AllocSize = DAG.getZExtOrTrunc(AllocSize, dl, IntPtr);
3873
3874 AllocSize = DAG.getNode(ISD::MUL, dl, IntPtr,
3875 AllocSize,
3876 DAG.getConstant(TySize, dl, IntPtr));
3877
3878 // Handle alignment. If the requested alignment is less than or equal to
3879 // the stack alignment, ignore it. If the size is greater than or equal to
3880 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
3881 Align StackAlign = DAG.getSubtarget().getFrameLowering()->getStackAlign();
3882 if (*Alignment <= StackAlign)
3883 Alignment = None;
3884
3885 const uint64_t StackAlignMask = StackAlign.value() - 1U;
3886 // Round the size of the allocation up to the stack alignment size
3887 // by add SA-1 to the size. This doesn't overflow because we're computing
3888 // an address inside an alloca.
3889 SDNodeFlags Flags;
3890 Flags.setNoUnsignedWrap(true);
3891 AllocSize = DAG.getNode(ISD::ADD, dl, AllocSize.getValueType(), AllocSize,
3892 DAG.getConstant(StackAlignMask, dl, IntPtr), Flags);
3893
3894 // Mask out the low bits for alignment purposes.
3895 AllocSize = DAG.getNode(ISD::AND, dl, AllocSize.getValueType(), AllocSize,
3896 DAG.getConstant(~StackAlignMask, dl, IntPtr));
3897
3898 SDValue Ops[] = {
3899 getRoot(), AllocSize,
3900 DAG.getConstant(Alignment ? Alignment->value() : 0, dl, IntPtr)};
3901 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
3902 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, dl, VTs, Ops);
3903 setValue(&I, DSA);
3904 DAG.setRoot(DSA.getValue(1));
3905
3906 assert(FuncInfo.MF->getFrameInfo().hasVarSizedObjects())((FuncInfo.MF->getFrameInfo().hasVarSizedObjects()) ? static_cast
<void> (0) : __assert_fail ("FuncInfo.MF->getFrameInfo().hasVarSizedObjects()"
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 3906, __PRETTY_FUNCTION__))
;
3907}
3908
3909void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
3910 if (I.isAtomic())
3911 return visitAtomicLoad(I);
3912
3913 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3914 const Value *SV = I.getOperand(0);
3915 if (TLI.supportSwiftError()) {
3916 // Swifterror values can come from either a function parameter with
3917 // swifterror attribute or an alloca with swifterror attribute.
3918 if (const Argument *Arg = dyn_cast<Argument>(SV)) {
3919 if (Arg->hasSwiftErrorAttr())
3920 return visitLoadFromSwiftError(I);
3921 }
3922
3923 if (const AllocaInst *Alloca = dyn_cast<AllocaInst>(SV)) {
3924 if (Alloca->isSwiftError())
3925 return visitLoadFromSwiftError(I);
3926 }
3927 }
3928
3929 SDValue Ptr = getValue(SV);
3930
3931 Type *Ty = I.getType();
3932 Align Alignment = I.getAlign();
3933
3934 AAMDNodes AAInfo;
3935 I.getAAMetadata(AAInfo);
3936 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3937
3938 SmallVector<EVT, 4> ValueVTs, MemVTs;
3939 SmallVector<uint64_t, 4> Offsets;
3940 ComputeValueVTs(TLI, DAG.getDataLayout(), Ty, ValueVTs, &MemVTs, &Offsets);
3941 unsigned NumValues = ValueVTs.size();
3942 if (NumValues == 0)
3943 return;
3944
3945 bool isVolatile = I.isVolatile();
3946
3947 SDValue Root;
3948 bool ConstantMemory = false;
3949 if (isVolatile)
3950 // Serialize volatile loads with other side effects.
3951 Root = getRoot();
3952 else if (NumValues > MaxParallelChains)
3953 Root = getMemoryRoot();
3954 else if (AA &&
3955 AA->pointsToConstantMemory(MemoryLocation(
3956 SV,
3957 LocationSize::precise(DAG.getDataLayout().getTypeStoreSize(Ty)),
3958 AAInfo))) {
3959 // Do not serialize (non-volatile) loads of constant memory with anything.
3960 Root = DAG.getEntryNode();
3961 ConstantMemory = true;
3962 } else {
3963 // Do not serialize non-volatile loads against each other.
3964 Root = DAG.getRoot();
3965 }
3966
3967 SDLoc dl = getCurSDLoc();
3968
3969 if (isVolatile)
3970 Root = TLI.prepareVolatileOrAtomicLoad(Root, dl, DAG);
3971
3972 // An aggregate load cannot wrap around the address space, so offsets to its
3973 // parts don't wrap either.
3974 SDNodeFlags Flags;
3975 Flags.setNoUnsignedWrap(true);
3976
3977 SmallVector<SDValue, 4> Values(NumValues);
3978 SmallVector<SDValue, 4> Chains(std::min(MaxParallelChains, NumValues));
3979 EVT PtrVT = Ptr.getValueType();
3980
3981 MachineMemOperand::Flags MMOFlags
3982 = TLI.getLoadMemOperandFlags(I, DAG.getDataLayout());
3983
3984 unsigned ChainI = 0;
3985 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3986 // Serializing loads here may result in excessive register pressure, and
3987 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling
3988 // could recover a bit by hoisting nodes upward in the chain by recognizing
3989 // they are side-effect free or do not alias. The optimizer should really
3990 // avoid this case by converting large object/array copies to llvm.memcpy
3991 // (MaxParallelChains should always remain as failsafe).
3992 if (ChainI == MaxParallelChains) {
3993 assert(PendingLoads.empty() && "PendingLoads must be serialized first")((PendingLoads.empty() && "PendingLoads must be serialized first"
) ? static_cast<void> (0) : __assert_fail ("PendingLoads.empty() && \"PendingLoads must be serialized first\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 3993, __PRETTY_FUNCTION__))
;
3994 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3995 makeArrayRef(Chains.data(), ChainI));
3996 Root = Chain;
3997 ChainI = 0;
3998 }
3999 SDValue A = DAG.getNode(ISD::ADD, dl,
4000 PtrVT, Ptr,
4001 DAG.getConstant(Offsets[i], dl, PtrVT),
4002 Flags);
4003
4004 SDValue L = DAG.getLoad(MemVTs[i], dl, Root, A,
4005 MachinePointerInfo(SV, Offsets[i]), Alignment,
4006 MMOFlags, AAInfo, Ranges);
4007 Chains[ChainI] = L.getValue(1);
4008
4009 if (MemVTs[i] != ValueVTs[i])
4010 L = DAG.getZExtOrTrunc(L, dl, ValueVTs[i]);
4011
4012 Values[i] = L;
4013 }
4014
4015 if (!ConstantMemory) {
4016 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
4017 makeArrayRef(Chains.data(), ChainI));
4018 if (isVolatile)
4019 DAG.setRoot(Chain);
4020 else
4021 PendingLoads.push_back(Chain);
4022 }
4023
4024 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, dl,
4025 DAG.getVTList(ValueVTs), Values));
4026}
4027
4028void SelectionDAGBuilder::visitStoreToSwiftError(const StoreInst &I) {
4029 assert(DAG.getTargetLoweringInfo().supportSwiftError() &&((DAG.getTargetLoweringInfo().supportSwiftError() && "call visitStoreToSwiftError when backend supports swifterror"
) ? static_cast<void> (0) : __assert_fail ("DAG.getTargetLoweringInfo().supportSwiftError() && \"call visitStoreToSwiftError when backend supports swifterror\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 4030, __PRETTY_FUNCTION__))
4030 "call visitStoreToSwiftError when backend supports swifterror")((DAG.getTargetLoweringInfo().supportSwiftError() && "call visitStoreToSwiftError when backend supports swifterror"
) ? static_cast<void> (0) : __assert_fail ("DAG.getTargetLoweringInfo().supportSwiftError() && \"call visitStoreToSwiftError when backend supports swifterror\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 4030, __PRETTY_FUNCTION__))
;
4031
4032 SmallVector<EVT, 4> ValueVTs;
4033 SmallVector<uint64_t, 4> Offsets;
4034 const Value *SrcV = I.getOperand(0);
4035 ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(),
4036 SrcV->getType(), ValueVTs, &Offsets);
4037 assert(ValueVTs.size() == 1 && Offsets[0] == 0 &&((ValueVTs.size() == 1 && Offsets[0] == 0 && "expect a single EVT for swifterror"
) ? static_cast<void> (0) : __assert_fail ("ValueVTs.size() == 1 && Offsets[0] == 0 && \"expect a single EVT for swifterror\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 4038, __PRETTY_FUNCTION__))
4038 "expect a single EVT for swifterror")((ValueVTs.size() == 1 && Offsets[0] == 0 && "expect a single EVT for swifterror"
) ? static_cast<void> (0) : __assert_fail ("ValueVTs.size() == 1 && Offsets[0] == 0 && \"expect a single EVT for swifterror\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 4038, __PRETTY_FUNCTION__))
;
4039
4040 SDValue Src = getValue(SrcV);
4041 // Create a virtual register, then update the virtual register.
4042 Register VReg =
4043 SwiftError.getOrCreateVRegDefAt(&I, FuncInfo.MBB, I.getPointerOperand());
4044 // Chain, DL, Reg, N or Chain, DL, Reg, N, Glue
4045 // Chain can be getRoot or getControlRoot.
4046 SDValue CopyNode = DAG.getCopyToReg(getRoot(), getCurSDLoc(), VReg,
4047 SDValue(Src.getNode(), Src.getResNo()));
4048 DAG.setRoot(CopyNode);
4049}
4050
4051void SelectionDAGBuilder::visitLoadFromSwiftError(const LoadInst &I) {
4052 assert(DAG.getTargetLoweringInfo().supportSwiftError() &&((DAG.getTargetLoweringInfo().supportSwiftError() && "call visitLoadFromSwiftError when backend supports swifterror"
) ? static_cast<void> (0) : __assert_fail ("DAG.getTargetLoweringInfo().supportSwiftError() && \"call visitLoadFromSwiftError when backend supports swifterror\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 4053, __PRETTY_FUNCTION__))
4053 "call visitLoadFromSwiftError when backend supports swifterror")((DAG.getTargetLoweringInfo().supportSwiftError() && "call visitLoadFromSwiftError when backend supports swifterror"
) ? static_cast<void> (0) : __assert_fail ("DAG.getTargetLoweringInfo().supportSwiftError() && \"call visitLoadFromSwiftError when backend supports swifterror\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 4053, __PRETTY_FUNCTION__))
;
4054
4055 assert(!I.isVolatile() &&((!I.isVolatile() && !I.hasMetadata(LLVMContext::MD_nontemporal
) && !I.hasMetadata(LLVMContext::MD_invariant_load) &&
"Support volatile, non temporal, invariant for load_from_swift_error"
) ? static_cast<void> (0) : __assert_fail ("!I.isVolatile() && !I.hasMetadata(LLVMContext::MD_nontemporal) && !I.hasMetadata(LLVMContext::MD_invariant_load) && \"Support volatile, non temporal, invariant for load_from_swift_error\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 4058, __PRETTY_FUNCTION__))
4056 !I.hasMetadata(LLVMContext::MD_nontemporal) &&((!I.isVolatile() && !I.hasMetadata(LLVMContext::MD_nontemporal
) && !I.hasMetadata(LLVMContext::MD_invariant_load) &&
"Support volatile, non temporal, invariant for load_from_swift_error"
) ? static_cast<void> (0) : __assert_fail ("!I.isVolatile() && !I.hasMetadata(LLVMContext::MD_nontemporal) && !I.hasMetadata(LLVMContext::MD_invariant_load) && \"Support volatile, non temporal, invariant for load_from_swift_error\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 4058, __PRETTY_FUNCTION__))
4057 !I.hasMetadata(LLVMContext::MD_invariant_load) &&((!I.isVolatile() && !I.hasMetadata(LLVMContext::MD_nontemporal
) && !I.hasMetadata(LLVMContext::MD_invariant_load) &&
"Support volatile, non temporal, invariant for load_from_swift_error"
) ? static_cast<void> (0) : __assert_fail ("!I.isVolatile() && !I.hasMetadata(LLVMContext::MD_nontemporal) && !I.hasMetadata(LLVMContext::MD_invariant_load) && \"Support volatile, non temporal, invariant for load_from_swift_error\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 4058, __PRETTY_FUNCTION__))
4058 "Support volatile, non temporal, invariant for load_from_swift_error")((!I.isVolatile() && !I.hasMetadata(LLVMContext::MD_nontemporal
) && !I.hasMetadata(LLVMContext::MD_invariant_load) &&
"Support volatile, non temporal, invariant for load_from_swift_error"
) ? static_cast<void> (0) : __assert_fail ("!I.isVolatile() && !I.hasMetadata(LLVMContext::MD_nontemporal) && !I.hasMetadata(LLVMContext::MD_invariant_load) && \"Support volatile, non temporal, invariant for load_from_swift_error\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 4058, __PRETTY_FUNCTION__))
;
4059
4060 const Value *SV = I.getOperand(0);
4061 Type *Ty = I.getType();
4062 AAMDNodes AAInfo;
4063 I.getAAMetadata(AAInfo);
4064 assert((((!AA || !AA->pointsToConstantMemory(MemoryLocation( SV, LocationSize
::precise(DAG.getDataLayout().getTypeStoreSize(Ty)), AAInfo))
) && "load_from_swift_error should not be constant memory"
) ? static_cast<void> (0) : __assert_fail ("(!AA || !AA->pointsToConstantMemory(MemoryLocation( SV, LocationSize::precise(DAG.getDataLayout().getTypeStoreSize(Ty)), AAInfo))) && \"load_from_swift_error should not be constant memory\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 4069, __PRETTY_FUNCTION__))
4065 (!AA ||(((!AA || !AA->pointsToConstantMemory(MemoryLocation( SV, LocationSize
::precise(DAG.getDataLayout().getTypeStoreSize(Ty)), AAInfo))
) && "load_from_swift_error should not be constant memory"
) ? static_cast<void> (0) : __assert_fail ("(!AA || !AA->pointsToConstantMemory(MemoryLocation( SV, LocationSize::precise(DAG.getDataLayout().getTypeStoreSize(Ty)), AAInfo))) && \"load_from_swift_error should not be constant memory\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 4069, __PRETTY_FUNCTION__))
4066 !AA->pointsToConstantMemory(MemoryLocation((((!AA || !AA->pointsToConstantMemory(MemoryLocation( SV, LocationSize
::precise(DAG.getDataLayout().getTypeStoreSize(Ty)), AAInfo))
) && "load_from_swift_error should not be constant memory"
) ? static_cast<void> (0) : __assert_fail ("(!AA || !AA->pointsToConstantMemory(MemoryLocation( SV, LocationSize::precise(DAG.getDataLayout().getTypeStoreSize(Ty)), AAInfo))) && \"load_from_swift_error should not be constant memory\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 4069, __PRETTY_FUNCTION__))
4067 SV, LocationSize::precise(DAG.getDataLayout().getTypeStoreSize(Ty)),(((!AA || !AA->pointsToConstantMemory(MemoryLocation( SV, LocationSize
::precise(DAG.getDataLayout().getTypeStoreSize(Ty)), AAInfo))
) && "load_from_swift_error should not be constant memory"
) ? static_cast<void> (0) : __assert_fail ("(!AA || !AA->pointsToConstantMemory(MemoryLocation( SV, LocationSize::precise(DAG.getDataLayout().getTypeStoreSize(Ty)), AAInfo))) && \"load_from_swift_error should not be constant memory\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 4069, __PRETTY_FUNCTION__))
4068 AAInfo))) &&(((!AA || !AA->pointsToConstantMemory(MemoryLocation( SV, LocationSize
::precise(DAG.getDataLayout().getTypeStoreSize(Ty)), AAInfo))
) && "load_from_swift_error should not be constant memory"
) ? static_cast<void> (0) : __assert_fail ("(!AA || !AA->pointsToConstantMemory(MemoryLocation( SV, LocationSize::precise(DAG.getDataLayout().getTypeStoreSize(Ty)), AAInfo))) && \"load_from_swift_error should not be constant memory\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 4069, __PRETTY_FUNCTION__))
4069 "load_from_swift_error should not be constant memory")(((!AA || !AA->pointsToConstantMemory(MemoryLocation( SV, LocationSize
::precise(DAG.getDataLayout().getTypeStoreSize(Ty)), AAInfo))
) && "load_from_swift_error should not be constant memory"
) ? static_cast<void> (0) : __assert_fail ("(!AA || !AA->pointsToConstantMemory(MemoryLocation( SV, LocationSize::precise(DAG.getDataLayout().getTypeStoreSize(Ty)), AAInfo))) && \"load_from_swift_error should not be constant memory\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 4069, __PRETTY_FUNCTION__))
;
4070
4071 SmallVector<EVT, 4> ValueVTs;
4072 SmallVector<uint64_t, 4> Offsets;
4073 ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(), Ty,
4074 ValueVTs, &Offsets);
4075 assert(ValueVTs.size() == 1 && Offsets[0] == 0 &&((ValueVTs.size() == 1 && Offsets[0] == 0 && "expect a single EVT for swifterror"
) ? static_cast<void> (0) : __assert_fail ("ValueVTs.size() == 1 && Offsets[0] == 0 && \"expect a single EVT for swifterror\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 4076, __PRETTY_FUNCTION__))
4076 "expect a single EVT for swifterror")((ValueVTs.size() == 1 && Offsets[0] == 0 && "expect a single EVT for swifterror"
) ? static_cast<void> (0) : __assert_fail ("ValueVTs.size() == 1 && Offsets[0] == 0 && \"expect a single EVT for swifterror\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 4076, __PRETTY_FUNCTION__))
;
4077
4078 // Chain, DL, Reg, VT, Glue or Chain, DL, Reg, VT
4079 SDValue L = DAG.getCopyFromReg(
4080 getRoot(), getCurSDLoc(),
4081 SwiftError.getOrCreateVRegUseAt(&I, FuncInfo.MBB, SV), ValueVTs[0]);
4082
4083 setValue(&I, L);
4084}
4085
4086void SelectionDAGBuilder::visitStore(const StoreInst &I) {
4087 if (I.isAtomic())
4088 return visitAtomicStore(I);
4089
4090 const Value *SrcV = I.getOperand(0);
4091 const Value *PtrV = I.getOperand(1);
4092
4093 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4094 if (TLI.supportSwiftError()) {
4095 // Swifterror values can come from either a function parameter with
4096 // swifterror attribute or an alloca with swifterror attribute.
4097 if (const Argument *Arg = dyn_cast<Argument>(PtrV)) {
4098 if (Arg->hasSwiftErrorAttr())
4099 return visitStoreToSwiftError(I);
4100 }
4101
4102 if (const AllocaInst *Alloca = dyn_cast<AllocaInst>(PtrV)) {
4103 if (Alloca->isSwiftError())
4104 return visitStoreToSwiftError(I);
4105 }
4106 }
4107
4108 SmallVector<EVT, 4> ValueVTs, MemVTs;
4109 SmallVector<uint64_t, 4> Offsets;
4110 ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(),
4111 SrcV->getType(), ValueVTs, &MemVTs, &Offsets);
4112 unsigned NumValues = ValueVTs.size();
4113 if (NumValues == 0)
4114 return;
4115
4116 // Get the lowered operands. Note that we do this after
4117 // checking if NumResults is zero, because with zero results
4118 // the operands won't have values in the map.
4119 SDValue Src = getValue(SrcV);
4120 SDValue Ptr = getValue(PtrV);
4121
4122 SDValue Root = I.isVolatile() ? getRoot() : getMemoryRoot();
4123 SmallVector<SDValue, 4> Chains(std::min(MaxParallelChains, NumValues));
4124 SDLoc dl = getCurSDLoc();
4125 Align Alignment = I.getAlign();
4126 AAMDNodes AAInfo;
4127 I.getAAMetadata(AAInfo);
4128
4129 auto MMOFlags = TLI.getStoreMemOperandFlags(I, DAG.getDataLayout());
4130
4131 // An aggregate load cannot wrap around the address space, so offsets to its
4132 // parts don't wrap either.
4133 SDNodeFlags Flags;
4134 Flags.setNoUnsignedWrap(true);
4135
4136 unsigned ChainI = 0;
4137 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
4138 // See visitLoad comments.
4139 if (ChainI == MaxParallelChains) {
4140 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
4141 makeArrayRef(Chains.data(), ChainI));
4142 Root = Chain;
4143 ChainI = 0;
4144 }
4145 SDValue Add =
4146 DAG.getMemBasePlusOffset(Ptr, TypeSize::Fixed(Offsets[i]), dl, Flags);
4147 SDValue Val = SDValue(Src.getNode(), Src.getResNo() + i);
4148 if (MemVTs[i] != ValueVTs[i])
4149 Val = DAG.getPtrExtOrTrunc(Val, dl, MemVTs[i]);
4150 SDValue St =
4151 DAG.getStore(Root, dl, Val, Add, MachinePointerInfo(PtrV, Offsets[i]),
4152 Alignment, MMOFlags, AAInfo);
4153 Chains[ChainI] = St;
4154 }
4155
4156 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
4157 makeArrayRef(Chains.data(), ChainI));
4158 DAG.setRoot(StoreNode);
4159}
4160
4161void SelectionDAGBuilder::visitMaskedStore(const CallInst &I,
4162 bool IsCompressing) {
4163 SDLoc sdl = getCurSDLoc();
4164
4165 auto getMaskedStoreOps = [&](Value *&Ptr, Value *&Mask, Value *&Src0,
4166 MaybeAlign &Alignment) {
4167 // llvm.masked.store.*(Src0, Ptr, alignment, Mask)
4168 Src0 = I.getArgOperand(0);
4169 Ptr = I.getArgOperand(1);
4170 Alignment = cast<ConstantInt>(I.getArgOperand(2))->getMaybeAlignValue();
4171 Mask = I.getArgOperand(3);
4172 };
4173 auto getCompressingStoreOps = [&](Value *&Ptr, Value *&Mask, Value *&Src0,
4174 MaybeAlign &Alignment) {
4175 // llvm.masked.compressstore.*(Src0, Ptr, Mask)
4176 Src0 = I.getArgOperand(0);
4177 Ptr = I.getArgOperand(1);
4178 Mask = I.getArgOperand(2);
4179 Alignment = None;
4180 };
4181
4182 Value *PtrOperand, *MaskOperand, *Src0Operand;
4183 MaybeAlign Alignment;
4184 if (IsCompressing)
4185 getCompressingStoreOps(PtrOperand, MaskOperand, Src0Operand, Alignment);
4186 else
4187 getMaskedStoreOps(PtrOperand, MaskOperand, Src0Operand, Alignment);
4188
4189 SDValue Ptr = getValue(PtrOperand);
4190 SDValue Src0 = getValue(Src0Operand);
4191 SDValue Mask = getValue(MaskOperand);
4192 SDValue Offset = DAG.getUNDEF(Ptr.getValueType());
4193
4194 EVT VT = Src0.getValueType();
4195 if (!Alignment)
4196 Alignment = DAG.getEVTAlign(VT);
4197
4198 AAMDNodes AAInfo;
4199 I.getAAMetadata(AAInfo);
4200
4201 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
4202 MachinePointerInfo(PtrOperand), MachineMemOperand::MOStore,
4203 // TODO: Make MachineMemOperands aware of scalable
4204 // vectors.
4205 VT.getStoreSize().getKnownMinSize(), *Alignment, AAInfo);
4206 SDValue StoreNode =
4207 DAG.getMaskedStore(getMemoryRoot(), sdl, Src0, Ptr, Offset, Mask, VT, MMO,
4208 ISD::UNINDEXED, false /* Truncating */, IsCompressing);
4209 DAG.setRoot(StoreNode);
4210 setValue(&I, StoreNode);
4211}
4212
4213// Get a uniform base for the Gather/Scatter intrinsic.
4214// The first argument of the Gather/Scatter intrinsic is a vector of pointers.
4215// We try to represent it as a base pointer + vector of indices.
4216// Usually, the vector of pointers comes from a 'getelementptr' instruction.
4217// The first operand of the GEP may be a single pointer or a vector of pointers
4218// Example:
4219// %gep.ptr = getelementptr i32, <8 x i32*> %vptr, <8 x i32> %ind
4220// or
4221// %gep.ptr = getelementptr i32, i32* %ptr, <8 x i32> %ind
4222// %res = call <8 x i32> @llvm.masked.gather.v8i32(<8 x i32*> %gep.ptr, ..
4223//
4224// When the first GEP operand is a single pointer - it is the uniform base we
4225// are looking for. If first operand of the GEP is a splat vector - we
4226// extract the splat value and use it as a uniform base.
4227// In all other cases the function returns 'false'.
4228static bool getUniformBase(const Value *Ptr, SDValue &Base, SDValue &Index,
4229 ISD::MemIndexType &IndexType, SDValue &Scale,
4230 SelectionDAGBuilder *SDB, const BasicBlock *CurBB) {
4231 SelectionDAG& DAG = SDB->DAG;
4232 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4233 const DataLayout &DL = DAG.getDataLayout();
4234
4235 assert(Ptr->getType()->isVectorTy() && "Uexpected pointer type")((Ptr->getType()->isVectorTy() && "Uexpected pointer type"
) ? static_cast<void> (0) : __assert_fail ("Ptr->getType()->isVectorTy() && \"Uexpected pointer type\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 4235, __PRETTY_FUNCTION__))
;
4236
4237 // Handle splat constant pointer.
4238 if (auto *C = dyn_cast<Constant>(Ptr)) {
4239 C = C->getSplatValue();
4240 if (!C)
4241 return false;
4242
4243 Base = SDB->getValue(C);
4244
4245 unsigned NumElts = cast<FixedVectorType>(Ptr->getType())->getNumElements();
4246 EVT VT = EVT::getVectorVT(*DAG.getContext(), TLI.getPointerTy(DL), NumElts);
4247 Index = DAG.getConstant(0, SDB->getCurSDLoc(), VT);
4248 IndexType = ISD::SIGNED_SCALED;
4249 Scale = DAG.getTargetConstant(1, SDB->getCurSDLoc(), TLI.getPointerTy(DL));
4250 return true;
4251 }
4252
4253 const GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(Ptr);
4254 if (!GEP || GEP->getParent() != CurBB)
4255 return false;
4256
4257 if (GEP->getNumOperands() != 2)
4258 return false;
4259
4260 const Value *BasePtr = GEP->getPointerOperand();
4261 const Value *IndexVal = GEP->getOperand(GEP->getNumOperands() - 1);
4262
4263 // Make sure the base is scalar and the index is a vector.
4264 if (BasePtr->getType()->isVectorTy() || !IndexVal->getType()->isVectorTy())
4265 return false;
4266
4267 Base = SDB->getValue(BasePtr);
4268 Index = SDB->getValue(IndexVal);
4269 IndexType = ISD::SIGNED_SCALED;
4270 Scale = DAG.getTargetConstant(
4271 DL.getTypeAllocSize(GEP->getResultElementType()),
4272 SDB->getCurSDLoc(), TLI.getPointerTy(DL));
4273 return true;
4274}
4275
4276void SelectionDAGBuilder::visitMaskedScatter(const CallInst &I) {
4277 SDLoc sdl = getCurSDLoc();
4278
4279 // llvm.masked.scatter.*(Src0, Ptrs, alignment, Mask)
4280 const Value *Ptr = I.getArgOperand(1);
4281 SDValue Src0 = getValue(I.getArgOperand(0));
4282 SDValue Mask = getValue(I.getArgOperand(3));
4283 EVT VT = Src0.getValueType();
4284 Align Alignment = cast<ConstantInt>(I.getArgOperand(2))
4285 ->getMaybeAlignValue()
4286 .getValueOr(DAG.getEVTAlign(VT));
4287 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4288
4289 AAMDNodes AAInfo;
4290 I.getAAMetadata(AAInfo);
4291
4292 SDValue Base;
4293 SDValue Index;
4294 ISD::MemIndexType IndexType;
4295 SDValue Scale;
4296 bool UniformBase = getUniformBase(Ptr, Base, Index, IndexType, Scale, this,
4297 I.getParent());
4298
4299 unsigned AS = Ptr->getType()->getScalarType()->getPointerAddressSpace();
4300 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
4301 MachinePointerInfo(AS), MachineMemOperand::MOStore,
4302 // TODO: Make MachineMemOperands aware of scalable
4303 // vectors.
4304 MemoryLocation::UnknownSize, Alignment, AAInfo);
4305 if (!UniformBase) {
4306 Base = DAG.getConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout()));
4307 Index = getValue(Ptr);
4308 IndexType = ISD::SIGNED_UNSCALED;
4309 Scale = DAG.getTargetConstant(1, sdl, TLI.getPointerTy(DAG.getDataLayout()));
4310 }
4311 SDValue Ops[] = { getMemoryRoot(), Src0, Mask, Base, Index, Scale };
4312 SDValue Scatter = DAG.getMaskedScatter(DAG.getVTList(MVT::Other), VT, sdl,
4313 Ops, MMO, IndexType, false);
4314 DAG.setRoot(Scatter);
4315 setValue(&I, Scatter);
4316}
4317
4318void SelectionDAGBuilder::visitMaskedLoad(const CallInst &I, bool IsExpanding) {
4319 SDLoc sdl = getCurSDLoc();
4320
4321 auto getMaskedLoadOps = [&](Value *&Ptr, Value *&Mask, Value *&Src0,
4322 MaybeAlign &Alignment) {
4323 // @llvm.masked.load.*(Ptr, alignment, Mask, Src0)
4324 Ptr = I.getArgOperand(0);
4325 Alignment = cast<ConstantInt>(I.getArgOperand(1))->getMaybeAlignValue();
4326 Mask = I.getArgOperand(2);
4327 Src0 = I.getArgOperand(3);
4328 };
4329 auto getExpandingLoadOps = [&](Value *&Ptr, Value *&Mask, Value *&Src0,
4330 MaybeAlign &Alignment) {
4331 // @llvm.masked.expandload.*(Ptr, Mask, Src0)
4332 Ptr = I.getArgOperand(0);
4333 Alignment = None;
4334 Mask = I.getArgOperand(1);
4335 Src0 = I.getArgOperand(2);
4336 };
4337
4338 Value *PtrOperand, *MaskOperand, *Src0Operand;
4339 MaybeAlign Alignment;
4340 if (IsExpanding)
4341 getExpandingLoadOps(PtrOperand, MaskOperand, Src0Operand, Alignment);
4342 else
4343 getMaskedLoadOps(PtrOperand, MaskOperand, Src0Operand, Alignment);
4344
4345 SDValue Ptr = getValue(PtrOperand);
4346 SDValue Src0 = getValue(Src0Operand);
4347 SDValue Mask = getValue(MaskOperand);
4348 SDValue Offset = DAG.getUNDEF(Ptr.getValueType());
4349
4350 EVT VT = Src0.getValueType();
4351 if (!Alignment)
4352 Alignment = DAG.getEVTAlign(VT);
4353
4354 AAMDNodes AAInfo;
4355 I.getAAMetadata(AAInfo);
4356 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
4357
4358 // Do not serialize masked loads of constant memory with anything.
4359 MemoryLocation ML;
4360 if (VT.isScalableVector())
4361 ML = MemoryLocation::getAfter(PtrOperand);
4362 else
4363 ML = MemoryLocation(PtrOperand, LocationSize::precise(
4364 DAG.getDataLayout().getTypeStoreSize(I.getType())),
4365 AAInfo);
4366 bool AddToChain = !AA || !AA->pointsToConstantMemory(ML);
4367
4368 SDValue InChain = AddToChain ? DAG.getRoot() : DAG.getEntryNode();
4369
4370 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
4371 MachinePointerInfo(PtrOperand), MachineMemOperand::MOLoad,
4372 // TODO: Make MachineMemOperands aware of scalable
4373 // vectors.
4374 VT.getStoreSize().getKnownMinSize(), *Alignment, AAInfo, Ranges);
4375
4376 SDValue Load =
4377 DAG.getMaskedLoad(VT, sdl, InChain, Ptr, Offset, Mask, Src0, VT, MMO,
4378 ISD::UNINDEXED, ISD::NON_EXTLOAD, IsExpanding);
4379 if (AddToChain)
4380 PendingLoads.push_back(Load.getValue(1));
4381 setValue(&I, Load);
4382}
4383
4384void SelectionDAGBuilder::visitMaskedGather(const CallInst &I) {
4385 SDLoc sdl = getCurSDLoc();
4386
4387 // @llvm.masked.gather.*(Ptrs, alignment, Mask, Src0)
4388 const Value *Ptr = I.getArgOperand(0);
4389 SDValue Src0 = getValue(I.getArgOperand(3));
4390 SDValue Mask = getValue(I.getArgOperand(2));
4391
4392 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4393 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4394 Align Alignment = cast<ConstantInt>(I.getArgOperand(1))
4395 ->getMaybeAlignValue()
4396 .getValueOr(DAG.getEVTAlign(VT));
4397
4398 AAMDNodes AAInfo;
4399 I.getAAMetadata(AAInfo);
4400 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
4401
4402 SDValue Root = DAG.getRoot();
4403 SDValue Base;
4404 SDValue Index;
4405 ISD::MemIndexType IndexType;
4406 SDValue Scale;
4407 bool UniformBase = getUniformBase(Ptr, Base, Index, IndexType, Scale, this,
4408 I.getParent());
4409 unsigned AS = Ptr->getType()->getScalarType()->getPointerAddressSpace();
4410 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
4411 MachinePointerInfo(AS), MachineMemOperand::MOLoad,
4412 // TODO: Make MachineMemOperands aware of scalable
4413 // vectors.
4414 MemoryLocation::UnknownSize, Alignment, AAInfo, Ranges);
4415
4416 if (!UniformBase) {
4417 Base = DAG.getConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout()));
4418 Index = getValue(Ptr);
4419 IndexType = ISD::SIGNED_SCALED;
4420 Scale = DAG.getTargetConstant(1, sdl, TLI.getPointerTy(DAG.getDataLayout()));
4421 }
4422 SDValue Ops[] = { Root, Src0, Mask, Base, Index, Scale };
4423 SDValue Gather = DAG.getMaskedGather(DAG.getVTList(VT, MVT::Other), VT, sdl,
4424 Ops, MMO, IndexType);
4425
4426 PendingLoads.push_back(Gather.getValue(1));
4427 setValue(&I, Gather);
4428}
4429
4430void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) {
4431 SDLoc dl = getCurSDLoc();
4432 AtomicOrdering SuccessOrdering = I.getSuccessOrdering();
4433 AtomicOrdering FailureOrdering = I.getFailureOrdering();
4434 SyncScope::ID SSID = I.getSyncScopeID();
4435
4436 SDValue InChain = getRoot();
4437
4438 MVT MemVT = getValue(I.getCompareOperand()).getSimpleValueType();
4439 SDVTList VTs = DAG.getVTList(MemVT, MVT::i1, MVT::Other);
4440
4441 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4442 auto Flags = TLI.getAtomicMemOperandFlags(I, DAG.getDataLayout());
4443
4444 MachineFunction &MF = DAG.getMachineFunction();
4445 MachineMemOperand *MMO = MF.getMachineMemOperand(
4446 MachinePointerInfo(I.getPointerOperand()), Flags, MemVT.getStoreSize(),
4447 DAG.getEVTAlign(MemVT), AAMDNodes(), nullptr, SSID, SuccessOrdering,
4448 FailureOrdering);
4449
4450 SDValue L = DAG.getAtomicCmpSwap(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS,
4451 dl, MemVT, VTs, InChain,
4452 getValue(I.getPointerOperand()),
4453 getValue(I.getCompareOperand()),
4454 getValue(I.getNewValOperand()), MMO);
4455
4456 SDValue OutChain = L.getValue(2);
4457
4458 setValue(&I, L);
4459 DAG.setRoot(OutChain);
4460}
4461
4462void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) {
4463 SDLoc dl = getCurSDLoc();
4464 ISD::NodeType NT;
4465 switch (I.getOperation()) {
4466 default: llvm_unreachable("Unknown atomicrmw operation")::llvm::llvm_unreachable_internal("Unknown atomicrmw operation"
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 4466)
;
4467 case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break;
4468 case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break;
4469 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break;
4470 case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break;
4471 case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break;
4472 case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break;
4473 case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break;
4474 case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break;
4475 case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break;
4476 case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break;
4477 case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break;
4478 case AtomicRMWInst::FAdd: NT = ISD::ATOMIC_LOAD_FADD; break;
4479 case AtomicRMWInst::FSub: NT = ISD::ATOMIC_LOAD_FSUB; break;
4480 }
4481 AtomicOrdering Ordering = I.getOrdering();
4482 SyncScope::ID SSID = I.getSyncScopeID();
4483
4484 SDValue InChain = getRoot();
4485
4486 auto MemVT = getValue(I.getValOperand()).getSimpleValueType();
4487 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4488 auto Flags = TLI.getAtomicMemOperandFlags(I, DAG.getDataLayout());
4489
4490 MachineFunction &MF = DAG.getMachineFunction();
4491 MachineMemOperand *MMO = MF.getMachineMemOperand(
4492 MachinePointerInfo(I.getPointerOperand()), Flags, MemVT.getStoreSize(),
4493 DAG.getEVTAlign(MemVT), AAMDNodes(), nullptr, SSID, Ordering);
4494
4495 SDValue L =
4496 DAG.getAtomic(NT, dl, MemVT, InChain,
4497 getValue(I.getPointerOperand()), getValue(I.getValOperand()),
4498 MMO);
4499
4500 SDValue OutChain = L.getValue(1);
4501
4502 setValue(&I, L);
4503 DAG.setRoot(OutChain);
4504}
4505
4506void SelectionDAGBuilder::visitFence(const FenceInst &I) {
4507 SDLoc dl = getCurSDLoc();
4508 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4509 SDValue Ops[3];
4510 Ops[0] = getRoot();
4511 Ops[1] = DAG.getTargetConstant((unsigned)I.getOrdering(), dl,
4512 TLI.getFenceOperandTy(DAG.getDataLayout()));
4513 Ops[2] = DAG.getTargetConstant(I.getSyncScopeID(), dl,
4514 TLI.getFenceOperandTy(DAG.getDataLayout()));
4515 DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops));
4516}
4517
4518void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) {
4519 SDLoc dl = getCurSDLoc();
4520 AtomicOrdering Order = I.getOrdering();
4521 SyncScope::ID SSID = I.getSyncScopeID();
4522
4523 SDValue InChain = getRoot();
4524
4525 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4526 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4527 EVT MemVT = TLI.getMemValueType(DAG.getDataLayout(), I.getType());
4528
4529 if (!TLI.supportsUnalignedAtomics() &&
4530 I.getAlignment() < MemVT.getSizeInBits() / 8)
4531 report_fatal_error("Cannot generate unaligned atomic load");
4532
4533 auto Flags = TLI.getLoadMemOperandFlags(I, DAG.getDataLayout());
4534
4535 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
4536 MachinePointerInfo(I.getPointerOperand()), Flags, MemVT.getStoreSize(),
4537 I.getAlign(), AAMDNodes(), nullptr, SSID, Order);
4538
4539 InChain = TLI.prepareVolatileOrAtomicLoad(InChain, dl, DAG);
4540
4541 SDValue Ptr = getValue(I.getPointerOperand());
4542
4543 if (TLI.lowerAtomicLoadAsLoadSDNode(I)) {
4544 // TODO: Once this is better exercised by tests, it should be merged with
4545 // the normal path for loads to prevent future divergence.
4546 SDValue L = DAG.getLoad(MemVT, dl, InChain, Ptr, MMO);
4547 if (MemVT != VT)
4548 L = DAG.getPtrExtOrTrunc(L, dl, VT);
4549
4550 setValue(&I, L);
4551 SDValue OutChain = L.getValue(1);
4552 if (!I.isUnordered())
4553 DAG.setRoot(OutChain);
4554 else
4555 PendingLoads.push_back(OutChain);
4556 return;
4557 }
4558
4559 SDValue L = DAG.getAtomic(ISD::ATOMIC_LOAD, dl, MemVT, MemVT, InChain,
4560 Ptr, MMO);
4561
4562 SDValue OutChain = L.getValue(1);
4563 if (MemVT != VT)
4564 L = DAG.getPtrExtOrTrunc(L, dl, VT);
4565
4566 setValue(&I, L);
4567 DAG.setRoot(OutChain);
4568}
4569
4570void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) {
4571 SDLoc dl = getCurSDLoc();
4572
4573 AtomicOrdering Ordering = I.getOrdering();
4574 SyncScope::ID SSID = I.getSyncScopeID();
4575
4576 SDValue InChain = getRoot();
4577
4578 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4579 EVT MemVT =
4580 TLI.getMemValueType(DAG.getDataLayout(), I.getValueOperand()->getType());
4581
4582 if (I.getAlignment() < MemVT.getSizeInBits() / 8)
4583 report_fatal_error("Cannot generate unaligned atomic store");
4584
4585 auto Flags = TLI.getStoreMemOperandFlags(I, DAG.getDataLayout());
4586
4587 MachineFunction &MF = DAG.getMachineFunction();
4588 MachineMemOperand *MMO = MF.getMachineMemOperand(
4589 MachinePointerInfo(I.getPointerOperand()), Flags, MemVT.getStoreSize(),
4590 I.getAlign(), AAMDNodes(), nullptr, SSID, Ordering);
4591
4592 SDValue Val = getValue(I.getValueOperand());
4593 if (Val.getValueType() != MemVT)
4594 Val = DAG.getPtrExtOrTrunc(Val, dl, MemVT);
4595 SDValue Ptr = getValue(I.getPointerOperand());
4596
4597 if (TLI.lowerAtomicStoreAsStoreSDNode(I)) {
4598 // TODO: Once this is better exercised by tests, it should be merged with
4599 // the normal path for stores to prevent future divergence.
4600 SDValue S = DAG.getStore(InChain, dl, Val, Ptr, MMO);
4601 DAG.setRoot(S);
4602 return;
4603 }
4604 SDValue OutChain = DAG.getAtomic(ISD::ATOMIC_STORE, dl, MemVT, InChain,
4605 Ptr, Val, MMO);
4606
4607
4608 DAG.setRoot(OutChain);
4609}
4610
4611/// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
4612/// node.
4613void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
4614 unsigned Intrinsic) {
4615 // Ignore the callsite's attributes. A specific call site may be marked with
4616 // readnone, but the lowering code will expect the chain based on the
4617 // definition.
4618 const Function *F = I.getCalledFunction();
4619 bool HasChain = !F->doesNotAccessMemory();
4620 bool OnlyLoad = HasChain && F->onlyReadsMemory();
4621
4622 // Build the operand list.
4623 SmallVector<SDValue, 8> Ops;
4624 if (HasChain) { // If this intrinsic has side-effects, chainify it.
4625 if (OnlyLoad) {
4626 // We don't need to serialize loads against other loads.
4627 Ops.push_back(DAG.getRoot());
4628 } else {
4629 Ops.push_back(getRoot());
4630 }
4631 }
4632
4633 // Info is set by getTgtMemInstrinsic
4634 TargetLowering::IntrinsicInfo Info;
4635 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4636 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I,
4637 DAG.getMachineFunction(),
4638 Intrinsic);
4639
4640 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
4641 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID ||
4642 Info.opc == ISD::INTRINSIC_W_CHAIN)
4643 Ops.push_back(DAG.getTargetConstant(Intrinsic, getCurSDLoc(),
4644 TLI.getPointerTy(DAG.getDataLayout())));
4645
4646 // Add all operands of the call to the operand list.
4647 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
4648 const Value *Arg = I.getArgOperand(i);
4649 if (!I.paramHasAttr(i, Attribute::ImmArg)) {
4650 Ops.push_back(getValue(Arg));
4651 continue;
4652 }
4653
4654 // Use TargetConstant instead of a regular constant for immarg.
4655 EVT VT = TLI.getValueType(*DL, Arg->getType(), true);
4656 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Arg)) {
4657 assert(CI->getBitWidth() <= 64 &&((CI->getBitWidth() <= 64 && "large intrinsic immediates not handled"
) ? static_cast<void> (0) : __assert_fail ("CI->getBitWidth() <= 64 && \"large intrinsic immediates not handled\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 4658, __PRETTY_FUNCTION__))
4658 "large intrinsic immediates not handled")((CI->getBitWidth() <= 64 && "large intrinsic immediates not handled"
) ? static_cast<void> (0) : __assert_fail ("CI->getBitWidth() <= 64 && \"large intrinsic immediates not handled\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 4658, __PRETTY_FUNCTION__))
;
4659 Ops.push_back(DAG.getTargetConstant(*CI, SDLoc(), VT));
4660 } else {
4661 Ops.push_back(
4662 DAG.getTargetConstantFP(*cast<ConstantFP>(Arg), SDLoc(), VT));
4663 }
4664 }
4665
4666 SmallVector<EVT, 4> ValueVTs;
4667 ComputeValueVTs(TLI, DAG.getDataLayout(), I.getType(), ValueVTs);
4668
4669 if (HasChain)
4670 ValueVTs.push_back(MVT::Other);
4671
4672 SDVTList VTs = DAG.getVTList(ValueVTs);
4673
4674 // Create the node.
4675 SDValue Result;
4676 if (IsTgtIntrinsic) {
4677 // This is target intrinsic that touches memory
4678 AAMDNodes AAInfo;
4679 I.getAAMetadata(AAInfo);
4680 Result =
4681 DAG.getMemIntrinsicNode(Info.opc, getCurSDLoc(), VTs, Ops, Info.memVT,
4682 MachinePointerInfo(Info.ptrVal, Info.offset),
4683 Info.align, Info.flags, Info.size, AAInfo);
4684 } else if (!HasChain) {
4685 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurSDLoc(), VTs, Ops);
4686 } else if (!I.getType()->isVoidTy()) {
4687 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurSDLoc(), VTs, Ops);
4688 } else {
4689 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurSDLoc(), VTs, Ops);
4690 }
4691
4692 if (HasChain) {
4693 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
4694 if (OnlyLoad)
4695 PendingLoads.push_back(Chain);
4696 else
4697 DAG.setRoot(Chain);
4698 }
4699
4700 if (!I.getType()->isVoidTy()) {
4701 if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
4702 EVT VT = TLI.getValueType(DAG.getDataLayout(), PTy);
4703 Result = DAG.getNode(ISD::BITCAST, getCurSDLoc(), VT, Result);
4704 } else
4705 Result = lowerRangeToAssertZExt(DAG, I, Result);
4706
4707 MaybeAlign Alignment = I.getRetAlign();
4708 if (!Alignment)
4709 Alignment = F->getAttributes().getRetAlignment();
4710 // Insert `assertalign` node if there's an alignment.
4711 if (InsertAssertAlign && Alignment) {
4712 Result =
4713 DAG.getAssertAlign(getCurSDLoc(), Result, Alignment.valueOrOne());
4714 }
4715
4716 setValue(&I, Result);
4717 }
4718}
4719
4720/// GetSignificand - Get the significand and build it into a floating-point
4721/// number with exponent of 1:
4722///
4723/// Op = (Op & 0x007fffff) | 0x3f800000;
4724///
4725/// where Op is the hexadecimal representation of floating point value.
4726static SDValue GetSignificand(SelectionDAG &DAG, SDValue Op, const SDLoc &dl) {
4727 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
4728 DAG.getConstant(0x007fffff, dl, MVT::i32));
4729 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
4730 DAG.getConstant(0x3f800000, dl, MVT::i32));
4731 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2);
4732}
4733
4734/// GetExponent - Get the exponent:
4735///
4736/// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
4737///
4738/// where Op is the hexadecimal representation of floating point value.
4739static SDValue GetExponent(SelectionDAG &DAG, SDValue Op,
4740 const TargetLowering &TLI, const SDLoc &dl) {
4741 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
4742 DAG.getConstant(0x7f800000, dl, MVT::i32));
4743 SDValue t1 = DAG.getNode(
4744 ISD::SRL, dl, MVT::i32, t0,
4745 DAG.getConstant(23, dl, TLI.getPointerTy(DAG.getDataLayout())));
4746 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
4747 DAG.getConstant(127, dl, MVT::i32));
4748 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
4749}
4750
4751/// getF32Constant - Get 32-bit floating point constant.
4752static SDValue getF32Constant(SelectionDAG &DAG, unsigned Flt,
4753 const SDLoc &dl) {
4754 return DAG.getConstantFP(APFloat(APFloat::IEEEsingle(), APInt(32, Flt)), dl,
4755 MVT::f32);
4756}
4757
4758static SDValue getLimitedPrecisionExp2(SDValue t0, const SDLoc &dl,
4759 SelectionDAG &DAG) {
4760 // TODO: What fast-math-flags should be set on the floating-point nodes?
4761
4762 // IntegerPartOfX = ((int32_t)(t0);
4763 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
4764
4765 // FractionalPartOfX = t0 - (float)IntegerPartOfX;
4766 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
4767 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
4768
4769 // IntegerPartOfX <<= 23;
4770 IntegerPartOfX = DAG.getNode(
4771 ISD::SHL, dl, MVT::i32, IntegerPartOfX,
4772 DAG.getConstant(23, dl, DAG.getTargetLoweringInfo().getPointerTy(
4773 DAG.getDataLayout())));
4774
4775 SDValue TwoToFractionalPartOfX;
4776 if (LimitFloatPrecision <= 6) {
4777 // For floating-point precision of 6:
4778 //
4779 // TwoToFractionalPartOfX =
4780 // 0.997535578f +
4781 // (0.735607626f + 0.252464424f * x) * x;
4782 //
4783 // error 0.0144103317, which is 6 bits
4784 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4785 getF32Constant(DAG, 0x3e814304, dl));
4786 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4787 getF32Constant(DAG, 0x3f3c50c8, dl));
4788 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4789 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4790 getF32Constant(DAG, 0x3f7f5e7e, dl));
4791 } else if (LimitFloatPrecision <= 12) {
4792 // For floating-point precision of 12:
4793 //
4794 // TwoToFractionalPartOfX =
4795 // 0.999892986f +
4796 // (0.696457318f +
4797 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
4798 //
4799 // error 0.000107046256, which is 13 to 14 bits
4800 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4801 getF32Constant(DAG, 0x3da235e3, dl));
4802 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4803 getF32Constant(DAG, 0x3e65b8f3, dl));
4804 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4805 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4806 getF32Constant(DAG, 0x3f324b07, dl));
4807 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4808 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4809 getF32Constant(DAG, 0x3f7ff8fd, dl));
4810 } else { // LimitFloatPrecision <= 18
4811 // For floating-point precision of 18:
4812 //
4813 // TwoToFractionalPartOfX =
4814 // 0.999999982f +
4815 // (0.693148872f +
4816 // (0.240227044f +
4817 // (0.554906021e-1f +
4818 // (0.961591928e-2f +
4819 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
4820 // error 2.47208000*10^(-7), which is better than 18 bits
4821 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4822 getF32Constant(DAG, 0x3924b03e, dl));
4823 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4824 getF32Constant(DAG, 0x3ab24b87, dl));
4825 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4826 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4827 getF32Constant(DAG, 0x3c1d8c17, dl));
4828 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4829 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4830 getF32Constant(DAG, 0x3d634a1d, dl));
4831 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4832 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4833 getF32Constant(DAG, 0x3e75fe14, dl));
4834 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4835 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
4836 getF32Constant(DAG, 0x3f317234, dl));
4837 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
4838 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
4839 getF32Constant(DAG, 0x3f800000, dl));
4840 }
4841
4842 // Add the exponent into the result in integer domain.
4843 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, TwoToFractionalPartOfX);
4844 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
4845 DAG.getNode(ISD::ADD, dl, MVT::i32, t13, IntegerPartOfX));
4846}
4847
4848/// expandExp - Lower an exp intrinsic. Handles the special sequences for
4849/// limited-precision mode.
4850static SDValue expandExp(const SDLoc &dl, SDValue Op, SelectionDAG &DAG,
4851 const TargetLowering &TLI, SDNodeFlags Flags) {
4852 if (Op.getValueType() == MVT::f32 &&
4853 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4854
4855 // Put the exponent in the right bit position for later addition to the
4856 // final result:
4857 //
4858 // t0 = Op * log2(e)
4859
4860 // TODO: What fast-math-flags should be set here?
4861 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
4862 DAG.getConstantFP(numbers::log2ef, dl, MVT::f32));
4863 return getLimitedPrecisionExp2(t0, dl, DAG);
4864 }
4865
4866 // No special expansion.
4867 return DAG.getNode(ISD::FEXP, dl, Op.getValueType(), Op, Flags);
4868}
4869
4870/// expandLog - Lower a log intrinsic. Handles the special sequences for
4871/// limited-precision mode.
4872static SDValue expandLog(const SDLoc &dl, SDValue Op, SelectionDAG &DAG,
4873 const TargetLowering &TLI, SDNodeFlags Flags) {
4874 // TODO: What fast-math-flags should be set on the floating-point nodes?
4875
4876 if (Op.getValueType() == MVT::f32 &&
4877 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4878 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
4879
4880 // Scale the exponent by log(2).
4881 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
4882 SDValue LogOfExponent =
4883 DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
4884 DAG.getConstantFP(numbers::ln2f, dl, MVT::f32));
4885
4886 // Get the significand and build it into a floating-point number with
4887 // exponent of 1.
4888 SDValue X = GetSignificand(DAG, Op1, dl);
4889
4890 SDValue LogOfMantissa;
4891 if (LimitFloatPrecision <= 6) {
4892 // For floating-point precision of 6:
4893 //
4894 // LogofMantissa =
4895 // -1.1609546f +
4896 // (1.4034025f - 0.23903021f * x) * x;
4897 //
4898 // error 0.0034276066, which is better than 8 bits
4899 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4900 getF32Constant(DAG, 0xbe74c456, dl));
4901 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4902 getF32Constant(DAG, 0x3fb3a2b1, dl));
4903 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4904 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4905 getF32Constant(DAG, 0x3f949a29, dl));
4906 } else if (LimitFloatPrecision <= 12) {
4907 // For floating-point precision of 12:
4908 //
4909 // LogOfMantissa =
4910 // -1.7417939f +
4911 // (2.8212026f +
4912 // (-1.4699568f +
4913 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
4914 //
4915 // error 0.000061011436, which is 14 bits
4916 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4917 getF32Constant(DAG, 0xbd67b6d6, dl));
4918 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4919 getF32Constant(DAG, 0x3ee4f4b8, dl));
4920 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4921 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4922 getF32Constant(DAG, 0x3fbc278b, dl));
4923 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4924 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4925 getF32Constant(DAG, 0x40348e95, dl));
4926 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4927 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4928 getF32Constant(DAG, 0x3fdef31a, dl));
4929 } else { // LimitFloatPrecision <= 18
4930 // For floating-point precision of 18:
4931 //
4932 // LogOfMantissa =
4933 // -2.1072184f +
4934 // (4.2372794f +
4935 // (-3.7029485f +
4936 // (2.2781945f +
4937 // (-0.87823314f +
4938 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
4939 //
4940 // error 0.0000023660568, which is better than 18 bits
4941 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4942 getF32Constant(DAG, 0xbc91e5ac, dl));
4943 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4944 getF32Constant(DAG, 0x3e4350aa, dl));
4945 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4946 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4947 getF32Constant(DAG, 0x3f60d3e3, dl));
4948 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4949 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4950 getF32Constant(DAG, 0x4011cdf0, dl));
4951 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4952 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4953 getF32Constant(DAG, 0x406cfd1c, dl));
4954 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4955 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4956 getF32Constant(DAG, 0x408797cb, dl));
4957 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4958 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
4959 getF32Constant(DAG, 0x4006dcab, dl));
4960 }
4961
4962 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, LogOfMantissa);
4963 }
4964
4965 // No special expansion.
4966 return DAG.getNode(ISD::FLOG, dl, Op.getValueType(), Op, Flags);
4967}
4968
4969/// expandLog2 - Lower a log2 intrinsic. Handles the special sequences for
4970/// limited-precision mode.
4971static SDValue expandLog2(const SDLoc &dl, SDValue Op, SelectionDAG &DAG,
4972 const TargetLowering &TLI, SDNodeFlags Flags) {
4973 // TODO: What fast-math-flags should be set on the floating-point nodes?
4974
4975 if (Op.getValueType() == MVT::f32 &&
4976 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4977 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
4978
4979 // Get the exponent.
4980 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
4981
4982 // Get the significand and build it into a floating-point number with
4983 // exponent of 1.
4984 SDValue X = GetSignificand(DAG, Op1, dl);
4985
4986 // Different possible minimax approximations of significand in
4987 // floating-point for various degrees of accuracy over [1,2].
4988 SDValue Log2ofMantissa;
4989 if (LimitFloatPrecision <= 6) {
4990 // For floating-point precision of 6:
4991 //
4992 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
4993 //
4994 // error 0.0049451742, which is more than 7 bits
4995 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4996 getF32Constant(DAG, 0xbeb08fe0, dl));
4997 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4998 getF32Constant(DAG, 0x40019463, dl));
4999 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
5000 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
5001 getF32Constant(DAG, 0x3fd6633d, dl));
5002 } else if (LimitFloatPrecision <= 12) {
5003 // For floating-point precision of 12:
5004 //
5005 // Log2ofMantissa =
5006 // -2.51285454f +
5007 // (4.07009056f +
5008 // (-2.12067489f +
5009 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
5010 //
5011 // error 0.0000876136000, which is better than 13 bits
5012 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
5013 getF32Constant(DAG, 0xbda7262e, dl));
5014 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
5015 getF32Constant(DAG, 0x3f25280b, dl));
5016 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
5017 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
5018 getF32Constant(DAG, 0x4007b923, dl));
5019 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
5020 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
5021 getF32Constant(DAG, 0x40823e2f, dl));
5022 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
5023 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
5024 getF32Constant(DAG, 0x4020d29c, dl));
5025 } else { // LimitFloatPrecision <= 18
5026 // For floating-point precision of 18:
5027 //
5028 // Log2ofMantissa =
5029 // -3.0400495f +
5030 // (6.1129976f +
5031 // (-5.3420409f +
5032 // (3.2865683f +
5033 // (-1.2669343f +
5034 // (0.27515199f -
5035 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
5036 //
5037 // error 0.0000018516, which is better than 18 bits
5038 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
5039 getF32Constant(DAG, 0xbcd2769e, dl));
5040 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
5041 getF32Constant(DAG, 0x3e8ce0b9, dl));
5042 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
5043 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
5044 getF32Constant(DAG, 0x3fa22ae7, dl));
5045 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
5046 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
5047 getF32Constant(DAG, 0x40525723, dl));
5048 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
5049 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
5050 getF32Constant(DAG, 0x40aaf200, dl));
5051 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
5052 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
5053 getF32Constant(DAG, 0x40c39dad, dl));
5054 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
5055 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
5056 getF32Constant(DAG, 0x4042902c, dl));
5057 }
5058
5059 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log2ofMantissa);
5060 }
5061
5062 // No special expansion.
5063 return DAG.getNode(ISD::FLOG2, dl, Op.getValueType(), Op, Flags);
5064}
5065
5066/// expandLog10 - Lower a log10 intrinsic. Handles the special sequences for
5067/// limited-precision mode.
5068static SDValue expandLog10(const SDLoc &dl, SDValue Op, SelectionDAG &DAG,
5069 const TargetLowering &TLI, SDNodeFlags Flags) {
5070 // TODO: What fast-math-flags should be set on the floating-point nodes?
5071
5072 if (Op.getValueType() == MVT::f32 &&
5073 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
5074 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
5075
5076 // Scale the exponent by log10(2) [0.30102999f].
5077 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
5078 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
5079 getF32Constant(DAG, 0x3e9a209a, dl));
5080
5081 // Get the significand and build it into a floating-point number with
5082 // exponent of 1.
5083 SDValue X = GetSignificand(DAG, Op1, dl);
5084
5085 SDValue Log10ofMantissa;
5086 if (LimitFloatPrecision <= 6) {
5087 // For floating-point precision of 6:
5088 //
5089 // Log10ofMantissa =
5090 // -0.50419619f +
5091 // (0.60948995f - 0.10380950f * x) * x;
5092 //
5093 // error 0.0014886165, which is 6 bits
5094 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
5095 getF32Constant(DAG, 0xbdd49a13, dl));
5096 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
5097 getF32Constant(DAG, 0x3f1c0789, dl));
5098 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
5099 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
5100 getF32Constant(DAG, 0x3f011300, dl));
5101 } else if (LimitFloatPrecision <= 12) {
5102 // For floating-point precision of 12:
5103 //
5104 // Log10ofMantissa =
5105 // -0.64831180f +
5106 // (0.91751397f +
5107 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
5108 //
5109 // error 0.00019228036, which is better than 12 bits
5110 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
5111 getF32Constant(DAG, 0x3d431f31, dl));
5112 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
5113 getF32Constant(DAG, 0x3ea21fb2, dl));
5114 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
5115 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
5116 getF32Constant(DAG, 0x3f6ae232, dl));
5117 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
5118 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
5119 getF32Constant(DAG, 0x3f25f7c3, dl));
5120 } else { // LimitFloatPrecision <= 18
5121 // For floating-point precision of 18:
5122 //
5123 // Log10ofMantissa =
5124 // -0.84299375f +
5125 // (1.5327582f +
5126 // (-1.0688956f +
5127 // (0.49102474f +
5128 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
5129 //
5130 // error 0.0000037995730, which is better than 18 bits
5131 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
5132 getF32Constant(DAG, 0x3c5d51ce, dl));
5133 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
5134 getF32Constant(DAG, 0x3e00685a, dl));
5135 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
5136 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
5137 getF32Constant(DAG, 0x3efb6798, dl));
5138 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
5139 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
5140 getF32Constant(DAG, 0x3f88d192, dl));
5141 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
5142 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
5143 getF32Constant(DAG, 0x3fc4316c, dl));
5144 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
5145 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
5146 getF32Constant(DAG, 0x3f57ce70, dl));
5147 }
5148
5149 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log10ofMantissa);
5150 }
5151
5152 // No special expansion.
5153 return DAG.getNode(ISD::FLOG10, dl, Op.getValueType(), Op, Flags);
5154}
5155
5156/// expandExp2 - Lower an exp2 intrinsic. Handles the special sequences for
5157/// limited-precision mode.
5158static SDValue expandExp2(const SDLoc &dl, SDValue Op, SelectionDAG &DAG,
5159 const TargetLowering &TLI, SDNodeFlags Flags) {
5160 if (Op.getValueType() == MVT::f32 &&
5161 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18)
5162 return getLimitedPrecisionExp2(Op, dl, DAG);
5163
5164 // No special expansion.
5165 return DAG.getNode(ISD::FEXP2, dl, Op.getValueType(), Op, Flags);
5166}
5167
5168/// visitPow - Lower a pow intrinsic. Handles the special sequences for
5169/// limited-precision mode with x == 10.0f.
5170static SDValue expandPow(const SDLoc &dl, SDValue LHS, SDValue RHS,
5171 SelectionDAG &DAG, const TargetLowering &TLI,
5172 SDNodeFlags Flags) {
5173 bool IsExp10 = false;
5174 if (LHS.getValueType() == MVT::f32 && RHS.getValueType() == MVT::f32 &&
5175 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
5176 if (ConstantFPSDNode *LHSC = dyn_cast<ConstantFPSDNode>(LHS)) {
5177 APFloat Ten(10.0f);
5178 IsExp10 = LHSC->isExactlyValue(Ten);
5179 }
5180 }
5181
5182 // TODO: What fast-math-flags should be set on the FMUL node?
5183 if (IsExp10) {
5184 // Put the exponent in the right bit position for later addition to the
5185 // final result:
5186 //
5187 // #define LOG2OF10 3.3219281f
5188 // t0 = Op * LOG2OF10;
5189 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, RHS,
5190 getF32Constant(DAG, 0x40549a78, dl));
5191 return getLimitedPrecisionExp2(t0, dl, DAG);
5192 }
5193
5194 // No special expansion.
5195 return DAG.getNode(ISD::FPOW, dl, LHS.getValueType(), LHS, RHS, Flags);
5196}
5197
5198/// ExpandPowI - Expand a llvm.powi intrinsic.
5199static SDValue ExpandPowI(const SDLoc &DL, SDValue LHS, SDValue RHS,
5200 SelectionDAG &DAG) {
5201 // If RHS is a constant, we can expand this out to a multiplication tree,
5202 // otherwise we end up lowering to a call to __powidf2 (for example). When
5203 // optimizing for size, we only want to do this if the expansion would produce
5204 // a small number of multiplies, otherwise we do the full expansion.
5205 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
5206 // Get the exponent as a positive value.
5207 unsigned Val = RHSC->getSExtValue();
5208 if ((int)Val < 0) Val = -Val;
5209
5210 // powi(x, 0) -> 1.0
5211 if (Val == 0)
5212 return DAG.getConstantFP(1.0, DL, LHS.getValueType());
5213
5214 bool OptForSize = DAG.shouldOptForSize();
5215 if (!OptForSize ||
5216 // If optimizing for size, don't insert too many multiplies.
5217 // This inserts up to 5 multiplies.
5218 countPopulation(Val) + Log2_32(Val) < 7) {
5219 // We use the simple binary decomposition method to generate the multiply
5220 // sequence. There are more optimal ways to do this (for example,
5221 // powi(x,15) generates one more multiply than it should), but this has
5222 // the benefit of being both really simple and much better than a libcall.
5223 SDValue Res; // Logically starts equal to 1.0
5224 SDValue CurSquare = LHS;
5225 // TODO: Intrinsics should have fast-math-flags that propagate to these
5226 // nodes.
5227 while (Val) {
5228 if (Val & 1) {
5229 if (Res.getNode())
5230 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare);
5231 else
5232 Res = CurSquare; // 1.0*CurSquare.
5233 }
5234
5235 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(),
5236 CurSquare, CurSquare);
5237 Val >>= 1;
5238 }
5239
5240 // If the original was negative, invert the result, producing 1/(x*x*x).
5241 if (RHSC->getSExtValue() < 0)
5242 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(),
5243 DAG.getConstantFP(1.0, DL, LHS.getValueType()), Res);
5244 return Res;
5245 }
5246 }
5247
5248 // Otherwise, expand to a libcall.
5249 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS);
5250}
5251
5252static SDValue expandDivFix(unsigned Opcode, const SDLoc &DL,
5253 SDValue LHS, SDValue RHS, SDValue Scale,
5254 SelectionDAG &DAG, const TargetLowering &TLI) {
5255 EVT VT = LHS.getValueType();
5256 bool Signed = Opcode == ISD::SDIVFIX || Opcode == ISD::SDIVFIXSAT;
5257 bool Saturating = Opcode == ISD::SDIVFIXSAT || Opcode == ISD::UDIVFIXSAT;
5258 LLVMContext &Ctx = *DAG.getContext();
5259
5260 // If the type is legal but the operation isn't, this node might survive all
5261 // the way to operation legalization. If we end up there and we do not have
5262 // the ability to widen the type (if VT*2 is not legal), we cannot expand the
5263 // node.
5264
5265 // Coax the legalizer into expanding the node during type legalization instead
5266 // by bumping the size by one bit. This will force it to Promote, enabling the
5267 // early expansion and avoiding the need to expand later.
5268
5269 // We don't have to do this if Scale is 0; that can always be expanded, unless
5270 // it's a saturating signed operation. Those can experience true integer
5271 // division overflow, a case which we must avoid.
5272
5273 // FIXME: We wouldn't have to do this (or any of the early
5274 // expansion/promotion) if it was possible to expand a libcall of an
5275 // illegal type during operation legalization. But it's not, so things
5276 // get a bit hacky.
5277 unsigned ScaleInt = cast<ConstantSDNode>(Scale)->getZExtValue();
5278 if ((ScaleInt > 0 || (Saturating && Signed)) &&
5279 (TLI.isTypeLegal(VT) ||
5280 (VT.isVector() && TLI.isTypeLegal(VT.getVectorElementType())))) {
5281 TargetLowering::LegalizeAction Action = TLI.getFixedPointOperationAction(
5282 Opcode, VT, ScaleInt);
5283 if (Action != TargetLowering::Legal && Action != TargetLowering::Custom) {
5284 EVT PromVT;
5285 if (VT.isScalarInteger())
5286 PromVT = EVT::getIntegerVT(Ctx, VT.getSizeInBits() + 1);
5287 else if (VT.isVector()) {
5288 PromVT = VT.getVectorElementType();
5289 PromVT = EVT::getIntegerVT(Ctx, PromVT.getSizeInBits() + 1);
5290 PromVT = EVT::getVectorVT(Ctx, PromVT, VT.getVectorElementCount());
5291 } else
5292 llvm_unreachable("Wrong VT for DIVFIX?")::llvm::llvm_unreachable_internal("Wrong VT for DIVFIX?", "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 5292)
;
5293 if (Signed) {
5294 LHS = DAG.getSExtOrTrunc(LHS, DL, PromVT);
5295 RHS = DAG.getSExtOrTrunc(RHS, DL, PromVT);
5296 } else {
5297 LHS = DAG.getZExtOrTrunc(LHS, DL, PromVT);
5298 RHS = DAG.getZExtOrTrunc(RHS, DL, PromVT);
5299 }
5300 EVT ShiftTy = TLI.getShiftAmountTy(PromVT, DAG.getDataLayout());
5301 // For saturating operations, we need to shift up the LHS to get the
5302 // proper saturation width, and then shift down again afterwards.
5303 if (Saturating)
5304 LHS = DAG.getNode(ISD::SHL, DL, PromVT, LHS,
5305 DAG.getConstant(1, DL, ShiftTy));
5306 SDValue Res = DAG.getNode(Opcode, DL, PromVT, LHS, RHS, Scale);
5307 if (Saturating)
5308 Res = DAG.getNode(Signed ? ISD::SRA : ISD::SRL, DL, PromVT, Res,
5309 DAG.getConstant(1, DL, ShiftTy));
5310 return DAG.getZExtOrTrunc(Res, DL, VT);
5311 }
5312 }
5313
5314 return DAG.getNode(Opcode, DL, VT, LHS, RHS, Scale);
5315}
5316
5317// getUnderlyingArgRegs - Find underlying registers used for a truncated,
5318// bitcasted, or split argument. Returns a list of <Register, size in bits>
5319static void
5320getUnderlyingArgRegs(SmallVectorImpl<std::pair<unsigned, unsigned>> &Regs,
5321 const SDValue &N) {
5322 switch (N.getOpcode()) {
5323 case ISD::CopyFromReg: {
5324 SDValue Op = N.getOperand(1);
5325 Regs.emplace_back(cast<RegisterSDNode>(Op)->getReg(),
5326 Op.getValueType().getSizeInBits());
5327 return;
5328 }
5329 case ISD::BITCAST:
5330 case ISD::AssertZext:
5331 case ISD::AssertSext:
5332 case ISD::TRUNCATE:
5333 getUnderlyingArgRegs(Regs, N.getOperand(0));
5334 return;
5335 case ISD::BUILD_PAIR:
5336 case ISD::BUILD_VECTOR:
5337 case ISD::CONCAT_VECTORS:
5338 for (SDValue Op : N->op_values())
5339 getUnderlyingArgRegs(Regs, Op);
5340 return;
5341 default:
5342 return;
5343 }
5344}
5345
5346/// If the DbgValueInst is a dbg_value of a function argument, create the
5347/// corresponding DBG_VALUE machine instruction for it now. At the end of
5348/// instruction selection, they will be inserted to the entry BB.
5349bool SelectionDAGBuilder::EmitFuncArgumentDbgValue(
5350 const Value *V, DILocalVariable *Variable, DIExpression *Expr,
5351 DILocation *DL, bool IsDbgDeclare, const SDValue &N) {
5352 const Argument *Arg = dyn_cast<Argument>(V);
5353 if (!Arg)
5354 return false;
5355
5356 if (!IsDbgDeclare) {
5357 // ArgDbgValues are hoisted to the beginning of the entry block. So we
5358 // should only emit as ArgDbgValue if the dbg.value intrinsic is found in
5359 // the entry block.
5360 bool IsInEntryBlock = FuncInfo.MBB == &FuncInfo.MF->front();
5361 if (!IsInEntryBlock)
5362 return false;
5363
5364 // ArgDbgValues are hoisted to the beginning of the entry block. So we
5365 // should only emit as ArgDbgValue if the dbg.value intrinsic describes a
5366 // variable that also is a param.
5367 //
5368 // Although, if we are at the top of the entry block already, we can still
5369 // emit using ArgDbgValue. This might catch some situations when the
5370 // dbg.value refers to an argument that isn't used in the entry block, so
5371 // any CopyToReg node would be optimized out and the only way to express
5372 // this DBG_VALUE is by using the physical reg (or FI) as done in this
5373 // method. ArgDbgValues are hoisted to the beginning of the entry block. So
5374 // we should only emit as ArgDbgValue if the Variable is an argument to the
5375 // current function, and the dbg.value intrinsic is found in the entry
5376 // block.
5377 bool VariableIsFunctionInputArg = Variable->isParameter() &&
5378 !DL->getInlinedAt();
5379 bool IsInPrologue = SDNodeOrder == LowestSDNodeOrder;
5380 if (!IsInPrologue && !VariableIsFunctionInputArg)
5381 return false;
5382
5383 // Here we assume that a function argument on IR level only can be used to
5384 // describe one input parameter on source level. If we for example have
5385 // source code like this
5386 //
5387 // struct A { long x, y; };
5388 // void foo(struct A a, long b) {
5389 // ...
5390 // b = a.x;
5391 // ...
5392 // }
5393 //
5394 // and IR like this
5395 //
5396 // define void @foo(i32 %a1, i32 %a2, i32 %b) {
5397 // entry:
5398 // call void @llvm.dbg.value(metadata i32 %a1, "a", DW_OP_LLVM_fragment
5399 // call void @llvm.dbg.value(metadata i32 %a2, "a", DW_OP_LLVM_fragment
5400 // call void @llvm.dbg.value(metadata i32 %b, "b",
5401 // ...
5402 // call void @llvm.dbg.value(metadata i32 %a1, "b"
5403 // ...
5404 //
5405 // then the last dbg.value is describing a parameter "b" using a value that
5406 // is an argument. But since we already has used %a1 to describe a parameter
5407 // we should not handle that last dbg.value here (that would result in an
5408 // incorrect hoisting of the DBG_VALUE to the function entry).
5409 // Notice that we allow one dbg.value per IR level argument, to accommodate
5410 // for the situation with fragments above.
5411 if (VariableIsFunctionInputArg) {
5412 unsigned ArgNo = Arg->getArgNo();
5413 if (ArgNo >= FuncInfo.DescribedArgs.size())
5414 FuncInfo.DescribedArgs.resize(ArgNo + 1, false);
5415 else if (!IsInPrologue && FuncInfo.DescribedArgs.test(ArgNo))
5416 return false;
5417 FuncInfo.DescribedArgs.set(ArgNo);
5418 }
5419 }
5420
5421 MachineFunction &MF = DAG.getMachineFunction();
5422 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
5423
5424 bool IsIndirect = false;
5425 Optional<MachineOperand> Op;
5426 // Some arguments' frame index is recorded during argument lowering.
5427 int FI = FuncInfo.getArgumentFrameIndex(Arg);
5428 if (FI != std::numeric_limits<int>::max())
5429 Op = MachineOperand::CreateFI(FI);
5430
5431 SmallVector<std::pair<unsigned, unsigned>, 8> ArgRegsAndSizes;
5432 if (!Op && N.getNode()) {
5433 getUnderlyingArgRegs(ArgRegsAndSizes, N);
5434 Register Reg;
5435 if (ArgRegsAndSizes.size() == 1)
5436 Reg = ArgRegsAndSizes.front().first;
5437
5438 if (Reg && Reg.isVirtual()) {
5439 MachineRegisterInfo &RegInfo = MF.getRegInfo();
5440 Register PR = RegInfo.getLiveInPhysReg(Reg);
5441 if (PR)
5442 Reg = PR;
5443 }
5444 if (Reg) {
5445 Op = MachineOperand::CreateReg(Reg, false);
5446 IsIndirect = IsDbgDeclare;
5447 }
5448 }
5449
5450 if (!Op && N.getNode()) {
5451 // Check if frame index is available.
5452 SDValue LCandidate = peekThroughBitcasts(N);
5453 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(LCandidate.getNode()))
5454 if (FrameIndexSDNode *FINode =
5455 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
5456 Op = MachineOperand::CreateFI(FINode->getIndex());
5457 }
5458
5459 if (!Op) {
5460 // Create a DBG_VALUE for each decomposed value in ArgRegs to cover Reg
5461 auto splitMultiRegDbgValue
5462 = [&](ArrayRef<std::pair<unsigned, unsigned>> SplitRegs) {
5463 unsigned Offset = 0;
5464 for (auto RegAndSize : SplitRegs) {
5465 // If the expression is already a fragment, the current register
5466 // offset+size might extend beyond the fragment. In this case, only
5467 // the register bits that are inside the fragment are relevant.
5468 int RegFragmentSizeInBits = RegAndSize.second;
5469 if (auto ExprFragmentInfo = Expr->getFragmentInfo()) {
5470 uint64_t ExprFragmentSizeInBits = ExprFragmentInfo->SizeInBits;
5471 // The register is entirely outside the expression fragment,
5472 // so is irrelevant for debug info.
5473 if (Offset >= ExprFragmentSizeInBits)
5474 break;
5475 // The register is partially outside the expression fragment, only
5476 // the low bits within the fragment are relevant for debug info.
5477 if (Offset + RegFragmentSizeInBits > ExprFragmentSizeInBits) {
5478 RegFragmentSizeInBits = ExprFragmentSizeInBits - Offset;
5479 }
5480 }
5481
5482 auto FragmentExpr = DIExpression::createFragmentExpression(
5483 Expr, Offset, RegFragmentSizeInBits);
5484 Offset += RegAndSize.second;
5485 // If a valid fragment expression cannot be created, the variable's
5486 // correct value cannot be determined and so it is set as Undef.
5487 if (!FragmentExpr) {
5488 SDDbgValue *SDV = DAG.getConstantDbgValue(
5489 Variable, Expr, UndefValue::get(V->getType()), DL, SDNodeOrder);
5490 DAG.AddDbgValue(SDV, nullptr, false);
5491 continue;
5492 }
5493 assert(!IsDbgDeclare && "DbgDeclare operand is not in memory?")((!IsDbgDeclare && "DbgDeclare operand is not in memory?"
) ? static_cast<void> (0) : __assert_fail ("!IsDbgDeclare && \"DbgDeclare operand is not in memory?\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 5493, __PRETTY_FUNCTION__))
;
5494 FuncInfo.ArgDbgValues.push_back(
5495 BuildMI(MF, DL, TII->get(TargetOpcode::DBG_VALUE), IsDbgDeclare,
5496 RegAndSize.first, Variable, *FragmentExpr));
5497 }
5498 };
5499
5500 // Check if ValueMap has reg number.
5501 DenseMap<const Value *, Register>::const_iterator
5502 VMI = FuncInfo.ValueMap.find(V);
5503 if (VMI != FuncInfo.ValueMap.end()) {
5504 const auto &TLI = DAG.getTargetLoweringInfo();
5505 RegsForValue RFV(V->getContext(), TLI, DAG.getDataLayout(), VMI->second,
5506 V->getType(), None);
5507 if (RFV.occupiesMultipleRegs()) {
5508 splitMultiRegDbgValue(RFV.getRegsAndSizes());
5509 return true;
5510 }
5511
5512 Op = MachineOperand::CreateReg(VMI->second, false);
5513 IsIndirect = IsDbgDeclare;
5514 } else if (ArgRegsAndSizes.size() > 1) {
5515 // This was split due to the calling convention, and no virtual register
5516 // mapping exists for the value.
5517 splitMultiRegDbgValue(ArgRegsAndSizes);
5518 return true;
5519 }
5520 }
5521
5522 if (!Op)
5523 return false;
5524
5525 assert(Variable->isValidLocationForIntrinsic(DL) &&((Variable->isValidLocationForIntrinsic(DL) && "Expected inlined-at fields to agree"
) ? static_cast<void> (0) : __assert_fail ("Variable->isValidLocationForIntrinsic(DL) && \"Expected inlined-at fields to agree\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 5526, __PRETTY_FUNCTION__))
5526 "Expected inlined-at fields to agree")((Variable->isValidLocationForIntrinsic(DL) && "Expected inlined-at fields to agree"
) ? static_cast<void> (0) : __assert_fail ("Variable->isValidLocationForIntrinsic(DL) && \"Expected inlined-at fields to agree\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 5526, __PRETTY_FUNCTION__))
;
5527 IsIndirect = (Op->isReg()) ? IsIndirect : true;
5528 FuncInfo.ArgDbgValues.push_back(
5529 BuildMI(MF, DL, TII->get(TargetOpcode::DBG_VALUE), IsIndirect,
5530 *Op, Variable, Expr));
5531
5532 return true;
5533}
5534
5535/// Return the appropriate SDDbgValue based on N.
5536SDDbgValue *SelectionDAGBuilder::getDbgValue(SDValue N,
5537 DILocalVariable *Variable,
5538 DIExpression *Expr,
5539 const DebugLoc &dl,
5540 unsigned DbgSDNodeOrder) {
5541 if (auto *FISDN = dyn_cast<FrameIndexSDNode>(N.getNode())) {
5542 // Construct a FrameIndexDbgValue for FrameIndexSDNodes so we can describe
5543 // stack slot locations.
5544 //
5545 // Consider "int x = 0; int *px = &x;". There are two kinds of interesting
5546 // debug values here after optimization:
5547 //
5548 // dbg.value(i32* %px, !"int *px", !DIExpression()), and
5549 // dbg.value(i32* %px, !"int x", !DIExpression(DW_OP_deref))
5550 //
5551 // Both describe the direct values of their associated variables.
5552 return DAG.getFrameIndexDbgValue(Variable, Expr, FISDN->getIndex(),
5553 /*IsIndirect*/ false, dl, DbgSDNodeOrder);
5554 }
5555 return DAG.getDbgValue(Variable, Expr, N.getNode(), N.getResNo(),
5556 /*IsIndirect*/ false, dl, DbgSDNodeOrder);
5557}
5558
5559static unsigned FixedPointIntrinsicToOpcode(unsigned Intrinsic) {
5560 switch (Intrinsic) {
5561 case Intrinsic::smul_fix:
5562 return ISD::SMULFIX;
5563 case Intrinsic::umul_fix:
5564 return ISD::UMULFIX;
5565 case Intrinsic::smul_fix_sat:
5566 return ISD::SMULFIXSAT;
5567 case Intrinsic::umul_fix_sat:
5568 return ISD::UMULFIXSAT;
5569 case Intrinsic::sdiv_fix:
5570 return ISD::SDIVFIX;
5571 case Intrinsic::udiv_fix:
5572 return ISD::UDIVFIX;
5573 case Intrinsic::sdiv_fix_sat:
5574 return ISD::SDIVFIXSAT;
5575 case Intrinsic::udiv_fix_sat:
5576 return ISD::UDIVFIXSAT;
5577 default:
5578 llvm_unreachable("Unhandled fixed point intrinsic")::llvm::llvm_unreachable_internal("Unhandled fixed point intrinsic"
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 5578)
;
5579 }
5580}
5581
5582void SelectionDAGBuilder::lowerCallToExternalSymbol(const CallInst &I,
5583 const char *FunctionName) {
5584 assert(FunctionName && "FunctionName must not be nullptr")((FunctionName && "FunctionName must not be nullptr")
? static_cast<void> (0) : __assert_fail ("FunctionName && \"FunctionName must not be nullptr\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 5584, __PRETTY_FUNCTION__))
;
5585 SDValue Callee = DAG.getExternalSymbol(
5586 FunctionName,
5587 DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout()));
5588 LowerCallTo(I, Callee, I.isTailCall());
5589}
5590
5591/// Given a @llvm.call.preallocated.setup, return the corresponding
5592/// preallocated call.
5593static const CallBase *FindPreallocatedCall(const Value *PreallocatedSetup) {
5594 assert(cast<CallBase>(PreallocatedSetup)((cast<CallBase>(PreallocatedSetup) ->getCalledFunction
() ->getIntrinsicID() == Intrinsic::call_preallocated_setup
&& "expected call_preallocated_setup Value") ? static_cast
<void> (0) : __assert_fail ("cast<CallBase>(PreallocatedSetup) ->getCalledFunction() ->getIntrinsicID() == Intrinsic::call_preallocated_setup && \"expected call_preallocated_setup Value\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 5597, __PRETTY_FUNCTION__))
5595 ->getCalledFunction()((cast<CallBase>(PreallocatedSetup) ->getCalledFunction
() ->getIntrinsicID() == Intrinsic::call_preallocated_setup
&& "expected call_preallocated_setup Value") ? static_cast
<void> (0) : __assert_fail ("cast<CallBase>(PreallocatedSetup) ->getCalledFunction() ->getIntrinsicID() == Intrinsic::call_preallocated_setup && \"expected call_preallocated_setup Value\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 5597, __PRETTY_FUNCTION__))
5596 ->getIntrinsicID() == Intrinsic::call_preallocated_setup &&((cast<CallBase>(PreallocatedSetup) ->getCalledFunction
() ->getIntrinsicID() == Intrinsic::call_preallocated_setup
&& "expected call_preallocated_setup Value") ? static_cast
<void> (0) : __assert_fail ("cast<CallBase>(PreallocatedSetup) ->getCalledFunction() ->getIntrinsicID() == Intrinsic::call_preallocated_setup && \"expected call_preallocated_setup Value\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 5597, __PRETTY_FUNCTION__))
5597 "expected call_preallocated_setup Value")((cast<CallBase>(PreallocatedSetup) ->getCalledFunction
() ->getIntrinsicID() == Intrinsic::call_preallocated_setup
&& "expected call_preallocated_setup Value") ? static_cast
<void> (0) : __assert_fail ("cast<CallBase>(PreallocatedSetup) ->getCalledFunction() ->getIntrinsicID() == Intrinsic::call_preallocated_setup && \"expected call_preallocated_setup Value\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 5597, __PRETTY_FUNCTION__))
;
5598 for (auto *U : PreallocatedSetup->users()) {
5599 auto *UseCall = cast<CallBase>(U);
5600 const Function *Fn = UseCall->getCalledFunction();
5601 if (!Fn || Fn->getIntrinsicID() != Intrinsic::call_preallocated_arg) {
5602 return UseCall;
5603 }
5604 }
5605 llvm_unreachable("expected corresponding call to preallocated setup/arg")::llvm::llvm_unreachable_internal("expected corresponding call to preallocated setup/arg"
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 5605)
;
5606}
5607
5608/// Lower the call to the specified intrinsic function.
5609void SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I,
5610 unsigned Intrinsic) {
5611 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5612 SDLoc sdl = getCurSDLoc();
5613 DebugLoc dl = getCurDebugLoc();
5614 SDValue Res;
5615
5616 SDNodeFlags Flags;
5617 if (auto *FPOp = dyn_cast<FPMathOperator>(&I))
5618 Flags.copyFMF(*FPOp);
5619
5620 switch (Intrinsic) {
5621 default:
5622 // By default, turn this into a target intrinsic node.
5623 visitTargetIntrinsic(I, Intrinsic);
5624 return;
5625 case Intrinsic::vscale: {
5626 match(&I, m_VScale(DAG.getDataLayout()));
5627 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
5628 setValue(&I,
5629 DAG.getVScale(getCurSDLoc(), VT, APInt(VT.getSizeInBits(), 1)));
5630 return;
5631 }
5632 case Intrinsic::vastart: visitVAStart(I); return;
5633 case Intrinsic::vaend: visitVAEnd(I); return;
5634 case Intrinsic::vacopy: visitVACopy(I); return;
5635 case Intrinsic::returnaddress:
5636 setValue(&I, DAG.getNode(ISD::RETURNADDR, sdl,
5637 TLI.getPointerTy(DAG.getDataLayout()),
5638 getValue(I.getArgOperand(0))));
5639 return;
5640 case Intrinsic::addressofreturnaddress:
5641 setValue(&I, DAG.getNode(ISD::ADDROFRETURNADDR, sdl,
5642 TLI.getPointerTy(DAG.getDataLayout())));
5643 return;
5644 case Intrinsic::sponentry:
5645 setValue(&I, DAG.getNode(ISD::SPONENTRY, sdl,
5646 TLI.getFrameIndexTy(DAG.getDataLayout())));
5647 return;
5648 case Intrinsic::frameaddress:
5649 setValue(&I, DAG.getNode(ISD::FRAMEADDR, sdl,
5650 TLI.getFrameIndexTy(DAG.getDataLayout()),
5651 getValue(I.getArgOperand(0))));
5652 return;
5653 case Intrinsic::read_volatile_register:
5654 case Intrinsic::read_register: {
5655 Value *Reg = I.getArgOperand(0);
5656 SDValue Chain = getRoot();
5657 SDValue RegName =
5658 DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
5659 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
5660 Res = DAG.getNode(ISD::READ_REGISTER, sdl,
5661 DAG.getVTList(VT, MVT::Other), Chain, RegName);
5662 setValue(&I, Res);
5663 DAG.setRoot(Res.getValue(1));
5664 return;
5665 }
5666 case Intrinsic::write_register: {
5667 Value *Reg = I.getArgOperand(0);
5668 Value *RegValue = I.getArgOperand(1);
5669 SDValue Chain = getRoot();
5670 SDValue RegName =
5671 DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
5672 DAG.setRoot(DAG.getNode(ISD::WRITE_REGISTER, sdl, MVT::Other, Chain,
5673 RegName, getValue(RegValue)));
5674 return;
5675 }
5676 case Intrinsic::memcpy: {
5677 const auto &MCI = cast<MemCpyInst>(I);
5678 SDValue Op1 = getValue(I.getArgOperand(0));
5679 SDValue Op2 = getValue(I.getArgOperand(1));
5680 SDValue Op3 = getValue(I.getArgOperand(2));
5681 // @llvm.memcpy defines 0 and 1 to both mean no alignment.
5682 Align DstAlign = MCI.getDestAlign().valueOrOne();
5683 Align SrcAlign = MCI.getSourceAlign().valueOrOne();
5684 Align Alignment = commonAlignment(DstAlign, SrcAlign);
5685 bool isVol = MCI.isVolatile();
5686 bool isTC = I.isTailCall() && isInTailCallPosition(I, DAG.getTarget());
5687 // FIXME: Support passing different dest/src alignments to the memcpy DAG
5688 // node.
5689 SDValue Root = isVol ? getRoot() : getMemoryRoot();
5690 SDValue MC = DAG.getMemcpy(Root, sdl, Op1, Op2, Op3, Alignment, isVol,
5691 /* AlwaysInline */ false, isTC,
5692 MachinePointerInfo(I.getArgOperand(0)),
5693 MachinePointerInfo(I.getArgOperand(1)));
5694 updateDAGForMaybeTailCall(MC);
5695 return;
5696 }
5697 case Intrinsic::memcpy_inline: {
5698 const auto &MCI = cast<MemCpyInlineInst>(I);
5699 SDValue Dst = getValue(I.getArgOperand(0));
5700 SDValue Src = getValue(I.getArgOperand(1));
5701 SDValue Size = getValue(I.getArgOperand(2));
5702 assert(isa<ConstantSDNode>(Size) && "memcpy_inline needs constant size")((isa<ConstantSDNode>(Size) && "memcpy_inline needs constant size"
) ? static_cast<void> (0) : __assert_fail ("isa<ConstantSDNode>(Size) && \"memcpy_inline needs constant size\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 5702, __PRETTY_FUNCTION__))
;
5703 // @llvm.memcpy.inline defines 0 and 1 to both mean no alignment.
5704 Align DstAlign = MCI.getDestAlign().valueOrOne();
5705 Align SrcAlign = MCI.getSourceAlign().valueOrOne();
5706 Align Alignment = commonAlignment(DstAlign, SrcAlign);
5707 bool isVol = MCI.isVolatile();
5708 bool isTC = I.isTailCall() && isInTailCallPosition(I, DAG.getTarget());
5709 // FIXME: Support passing different dest/src alignments to the memcpy DAG
5710 // node.
5711 SDValue MC = DAG.getMemcpy(getRoot(), sdl, Dst, Src, Size, Alignment, isVol,
5712 /* AlwaysInline */ true, isTC,
5713 MachinePointerInfo(I.getArgOperand(0)),
5714 MachinePointerInfo(I.getArgOperand(1)));
5715 updateDAGForMaybeTailCall(MC);
5716 return;
5717 }
5718 case Intrinsic::memset: {
5719 const auto &MSI = cast<MemSetInst>(I);
5720 SDValue Op1 = getValue(I.getArgOperand(0));
5721 SDValue Op2 = getValue(I.getArgOperand(1));
5722 SDValue Op3 = getValue(I.getArgOperand(2));
5723 // @llvm.memset defines 0 and 1 to both mean no alignment.
5724 Align Alignment = MSI.getDestAlign().valueOrOne();
5725 bool isVol = MSI.isVolatile();
5726 bool isTC = I.isTailCall() && isInTailCallPosition(I, DAG.getTarget());
5727 SDValue Root = isVol ? getRoot() : getMemoryRoot();
5728 SDValue MS = DAG.getMemset(Root, sdl, Op1, Op2, Op3, Alignment, isVol, isTC,
5729 MachinePointerInfo(I.getArgOperand(0)));
5730 updateDAGForMaybeTailCall(MS);
5731 return;
5732 }
5733 case Intrinsic::memmove: {
5734 const auto &MMI = cast<MemMoveInst>(I);
5735 SDValue Op1 = getValue(I.getArgOperand(0));
5736 SDValue Op2 = getValue(I.getArgOperand(1));
5737 SDValue Op3 = getValue(I.getArgOperand(2));
5738 // @llvm.memmove defines 0 and 1 to both mean no alignment.
5739 Align DstAlign = MMI.getDestAlign().valueOrOne();
5740 Align SrcAlign = MMI.getSourceAlign().valueOrOne();
5741 Align Alignment = commonAlignment(DstAlign, SrcAlign);
5742 bool isVol = MMI.isVolatile();
5743 bool isTC = I.isTailCall() && isInTailCallPosition(I, DAG.getTarget());
5744 // FIXME: Support passing different dest/src alignments to the memmove DAG
5745 // node.
5746 SDValue Root = isVol ? getRoot() : getMemoryRoot();
5747 SDValue MM = DAG.getMemmove(Root, sdl, Op1, Op2, Op3, Alignment, isVol,
5748 isTC, MachinePointerInfo(I.getArgOperand(0)),
5749 MachinePointerInfo(I.getArgOperand(1)));
5750 updateDAGForMaybeTailCall(MM);
5751 return;
5752 }
5753 case Intrinsic::memcpy_element_unordered_atomic: {
5754 const AtomicMemCpyInst &MI = cast<AtomicMemCpyInst>(I);
5755 SDValue Dst = getValue(MI.getRawDest());
5756 SDValue Src = getValue(MI.getRawSource());
5757 SDValue Length = getValue(MI.getLength());
5758
5759 unsigned DstAlign = MI.getDestAlignment();
5760 unsigned SrcAlign = MI.getSourceAlignment();
5761 Type *LengthTy = MI.getLength()->getType();
5762 unsigned ElemSz = MI.getElementSizeInBytes();
5763 bool isTC = I.isTailCall() && isInTailCallPosition(I, DAG.getTarget());
5764 SDValue MC = DAG.getAtomicMemcpy(getRoot(), sdl, Dst, DstAlign, Src,
5765 SrcAlign, Length, LengthTy, ElemSz, isTC,
5766 MachinePointerInfo(MI.getRawDest()),
5767 MachinePointerInfo(MI.getRawSource()));
5768 updateDAGForMaybeTailCall(MC);
5769 return;
5770 }
5771 case Intrinsic::memmove_element_unordered_atomic: {
5772 auto &MI = cast<AtomicMemMoveInst>(I);
5773 SDValue Dst = getValue(MI.getRawDest());
5774 SDValue Src = getValue(MI.getRawSource());
5775 SDValue Length = getValue(MI.getLength());
5776
5777 unsigned DstAlign = MI.getDestAlignment();
5778 unsigned SrcAlign = MI.getSourceAlignment();
5779 Type *LengthTy = MI.getLength()->getType();
5780 unsigned ElemSz = MI.getElementSizeInBytes();
5781 bool isTC = I.isTailCall() && isInTailCallPosition(I, DAG.getTarget());
5782 SDValue MC = DAG.getAtomicMemmove(getRoot(), sdl, Dst, DstAlign, Src,
5783 SrcAlign, Length, LengthTy, ElemSz, isTC,
5784 MachinePointerInfo(MI.getRawDest()),
5785 MachinePointerInfo(MI.getRawSource()));
5786 updateDAGForMaybeTailCall(MC);
5787 return;
5788 }
5789 case Intrinsic::memset_element_unordered_atomic: {
5790 auto &MI = cast<AtomicMemSetInst>(I);
5791 SDValue Dst = getValue(MI.getRawDest());
5792 SDValue Val = getValue(MI.getValue());
5793 SDValue Length = getValue(MI.getLength());
5794
5795 unsigned DstAlign = MI.getDestAlignment();
5796 Type *LengthTy = MI.getLength()->getType();
5797 unsigned ElemSz = MI.getElementSizeInBytes();
5798 bool isTC = I.isTailCall() && isInTailCallPosition(I, DAG.getTarget());
5799 SDValue MC = DAG.getAtomicMemset(getRoot(), sdl, Dst, DstAlign, Val, Length,
5800 LengthTy, ElemSz, isTC,
5801 MachinePointerInfo(MI.getRawDest()));
5802 updateDAGForMaybeTailCall(MC);
5803 return;
5804 }
5805 case Intrinsic::call_preallocated_setup: {
5806 const CallBase *PreallocatedCall = FindPreallocatedCall(&I);
5807 SDValue SrcValue = DAG.getSrcValue(PreallocatedCall);
5808 SDValue Res = DAG.getNode(ISD::PREALLOCATED_SETUP, sdl, MVT::Other,
5809 getRoot(), SrcValue);
5810 setValue(&I, Res);
5811 DAG.setRoot(Res);
5812 return;
5813 }
5814 case Intrinsic::call_preallocated_arg: {
5815 const CallBase *PreallocatedCall = FindPreallocatedCall(I.getOperand(0));
5816 SDValue SrcValue = DAG.getSrcValue(PreallocatedCall);
5817 SDValue Ops[3];
5818 Ops[0] = getRoot();
5819 Ops[1] = SrcValue;
5820 Ops[2] = DAG.getTargetConstant(*cast<ConstantInt>(I.getArgOperand(1)), sdl,
5821 MVT::i32); // arg index
5822 SDValue Res = DAG.getNode(
5823 ISD::PREALLOCATED_ARG, sdl,
5824 DAG.getVTList(TLI.getPointerTy(DAG.getDataLayout()), MVT::Other), Ops);
5825 setValue(&I, Res);
5826 DAG.setRoot(Res.getValue(1));
5827 return;
5828 }
5829 case Intrinsic::dbg_addr:
5830 case Intrinsic::dbg_declare: {
5831 const auto &DI = cast<DbgVariableIntrinsic>(I);
5832 DILocalVariable *Variable = DI.getVariable();
5833 DIExpression *Expression = DI.getExpression();
5834 dropDanglingDebugInfo(Variable, Expression);
5835 assert(Variable && "Missing variable")((Variable && "Missing variable") ? static_cast<void
> (0) : __assert_fail ("Variable && \"Missing variable\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp"
, 5835, __PRETTY_FUNCTION__))
;
5836 LLVM_DEBUG(dbgs() << "SelectionDAG visiting debug intrinsic: " << DIdo { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << "SelectionDAG visiting debug intrinsic: "
<< DI << "\n"; } } while (false)
5837 << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("isel")) { dbgs() << "SelectionDAG visiting debug intrinsic: "
<< DI << "\n"; } } while (false)
;
5838 // Check if address has undef value.
5839 const Value *Address = DI.getVariableLocation();
5840 if (!Address || isa<Undef