File: | llvm/include/llvm/CodeGen/SelectionDAGNodes.h |
Warning: | line 1114, column 10 Called C++ object pointer is null |
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1 | //===-- TargetLowering.cpp - Implement the TargetLowering class -----------===// | ||||||
2 | // | ||||||
3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. | ||||||
4 | // See https://llvm.org/LICENSE.txt for license information. | ||||||
5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception | ||||||
6 | // | ||||||
7 | //===----------------------------------------------------------------------===// | ||||||
8 | // | ||||||
9 | // This implements the TargetLowering class. | ||||||
10 | // | ||||||
11 | //===----------------------------------------------------------------------===// | ||||||
12 | |||||||
13 | #include "llvm/CodeGen/TargetLowering.h" | ||||||
14 | #include "llvm/ADT/STLExtras.h" | ||||||
15 | #include "llvm/CodeGen/CallingConvLower.h" | ||||||
16 | #include "llvm/CodeGen/MachineFrameInfo.h" | ||||||
17 | #include "llvm/CodeGen/MachineFunction.h" | ||||||
18 | #include "llvm/CodeGen/MachineJumpTableInfo.h" | ||||||
19 | #include "llvm/CodeGen/MachineRegisterInfo.h" | ||||||
20 | #include "llvm/CodeGen/SelectionDAG.h" | ||||||
21 | #include "llvm/CodeGen/TargetRegisterInfo.h" | ||||||
22 | #include "llvm/CodeGen/TargetSubtargetInfo.h" | ||||||
23 | #include "llvm/IR/DataLayout.h" | ||||||
24 | #include "llvm/IR/DerivedTypes.h" | ||||||
25 | #include "llvm/IR/GlobalVariable.h" | ||||||
26 | #include "llvm/IR/LLVMContext.h" | ||||||
27 | #include "llvm/MC/MCAsmInfo.h" | ||||||
28 | #include "llvm/MC/MCExpr.h" | ||||||
29 | #include "llvm/Support/ErrorHandling.h" | ||||||
30 | #include "llvm/Support/KnownBits.h" | ||||||
31 | #include "llvm/Support/MathExtras.h" | ||||||
32 | #include "llvm/Target/TargetLoweringObjectFile.h" | ||||||
33 | #include "llvm/Target/TargetMachine.h" | ||||||
34 | #include <cctype> | ||||||
35 | using namespace llvm; | ||||||
36 | |||||||
37 | /// NOTE: The TargetMachine owns TLOF. | ||||||
38 | TargetLowering::TargetLowering(const TargetMachine &tm) | ||||||
39 | : TargetLoweringBase(tm) {} | ||||||
40 | |||||||
41 | const char *TargetLowering::getTargetNodeName(unsigned Opcode) const { | ||||||
42 | return nullptr; | ||||||
43 | } | ||||||
44 | |||||||
45 | bool TargetLowering::isPositionIndependent() const { | ||||||
46 | return getTargetMachine().isPositionIndependent(); | ||||||
47 | } | ||||||
48 | |||||||
49 | /// Check whether a given call node is in tail position within its function. If | ||||||
50 | /// so, it sets Chain to the input chain of the tail call. | ||||||
51 | bool TargetLowering::isInTailCallPosition(SelectionDAG &DAG, SDNode *Node, | ||||||
52 | SDValue &Chain) const { | ||||||
53 | const Function &F = DAG.getMachineFunction().getFunction(); | ||||||
54 | |||||||
55 | // First, check if tail calls have been disabled in this function. | ||||||
56 | if (F.getFnAttribute("disable-tail-calls").getValueAsString() == "true") | ||||||
57 | return false; | ||||||
58 | |||||||
59 | // Conservatively require the attributes of the call to match those of | ||||||
60 | // the return. Ignore NoAlias and NonNull because they don't affect the | ||||||
61 | // call sequence. | ||||||
62 | AttributeList CallerAttrs = F.getAttributes(); | ||||||
63 | if (AttrBuilder(CallerAttrs, AttributeList::ReturnIndex) | ||||||
64 | .removeAttribute(Attribute::NoAlias) | ||||||
65 | .removeAttribute(Attribute::NonNull) | ||||||
66 | .hasAttributes()) | ||||||
67 | return false; | ||||||
68 | |||||||
69 | // It's not safe to eliminate the sign / zero extension of the return value. | ||||||
70 | if (CallerAttrs.hasAttribute(AttributeList::ReturnIndex, Attribute::ZExt) || | ||||||
71 | CallerAttrs.hasAttribute(AttributeList::ReturnIndex, Attribute::SExt)) | ||||||
72 | return false; | ||||||
73 | |||||||
74 | // Check if the only use is a function return node. | ||||||
75 | return isUsedByReturnOnly(Node, Chain); | ||||||
76 | } | ||||||
77 | |||||||
78 | bool TargetLowering::parametersInCSRMatch(const MachineRegisterInfo &MRI, | ||||||
79 | const uint32_t *CallerPreservedMask, | ||||||
80 | const SmallVectorImpl<CCValAssign> &ArgLocs, | ||||||
81 | const SmallVectorImpl<SDValue> &OutVals) const { | ||||||
82 | for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) { | ||||||
83 | const CCValAssign &ArgLoc = ArgLocs[I]; | ||||||
84 | if (!ArgLoc.isRegLoc()) | ||||||
85 | continue; | ||||||
86 | MCRegister Reg = ArgLoc.getLocReg(); | ||||||
87 | // Only look at callee saved registers. | ||||||
88 | if (MachineOperand::clobbersPhysReg(CallerPreservedMask, Reg)) | ||||||
89 | continue; | ||||||
90 | // Check that we pass the value used for the caller. | ||||||
91 | // (We look for a CopyFromReg reading a virtual register that is used | ||||||
92 | // for the function live-in value of register Reg) | ||||||
93 | SDValue Value = OutVals[I]; | ||||||
94 | if (Value->getOpcode() != ISD::CopyFromReg) | ||||||
95 | return false; | ||||||
96 | Register ArgReg = cast<RegisterSDNode>(Value->getOperand(1))->getReg(); | ||||||
97 | if (MRI.getLiveInPhysReg(ArgReg) != Reg) | ||||||
98 | return false; | ||||||
99 | } | ||||||
100 | return true; | ||||||
101 | } | ||||||
102 | |||||||
103 | /// Set CallLoweringInfo attribute flags based on a call instruction | ||||||
104 | /// and called function attributes. | ||||||
105 | void TargetLoweringBase::ArgListEntry::setAttributes(const CallBase *Call, | ||||||
106 | unsigned ArgIdx) { | ||||||
107 | IsSExt = Call->paramHasAttr(ArgIdx, Attribute::SExt); | ||||||
108 | IsZExt = Call->paramHasAttr(ArgIdx, Attribute::ZExt); | ||||||
109 | IsInReg = Call->paramHasAttr(ArgIdx, Attribute::InReg); | ||||||
110 | IsSRet = Call->paramHasAttr(ArgIdx, Attribute::StructRet); | ||||||
111 | IsNest = Call->paramHasAttr(ArgIdx, Attribute::Nest); | ||||||
112 | IsByVal = Call->paramHasAttr(ArgIdx, Attribute::ByVal); | ||||||
113 | IsPreallocated = Call->paramHasAttr(ArgIdx, Attribute::Preallocated); | ||||||
114 | IsInAlloca = Call->paramHasAttr(ArgIdx, Attribute::InAlloca); | ||||||
115 | IsReturned = Call->paramHasAttr(ArgIdx, Attribute::Returned); | ||||||
116 | IsSwiftSelf = Call->paramHasAttr(ArgIdx, Attribute::SwiftSelf); | ||||||
117 | IsSwiftError = Call->paramHasAttr(ArgIdx, Attribute::SwiftError); | ||||||
118 | Alignment = Call->getParamAlign(ArgIdx); | ||||||
119 | ByValType = nullptr; | ||||||
120 | if (IsByVal) | ||||||
121 | ByValType = Call->getParamByValType(ArgIdx); | ||||||
122 | PreallocatedType = nullptr; | ||||||
123 | if (IsPreallocated) | ||||||
124 | PreallocatedType = Call->getParamPreallocatedType(ArgIdx); | ||||||
125 | } | ||||||
126 | |||||||
127 | /// Generate a libcall taking the given operands as arguments and returning a | ||||||
128 | /// result of type RetVT. | ||||||
129 | std::pair<SDValue, SDValue> | ||||||
130 | TargetLowering::makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT, | ||||||
131 | ArrayRef<SDValue> Ops, | ||||||
132 | MakeLibCallOptions CallOptions, | ||||||
133 | const SDLoc &dl, | ||||||
134 | SDValue InChain) const { | ||||||
135 | if (!InChain) | ||||||
136 | InChain = DAG.getEntryNode(); | ||||||
137 | |||||||
138 | TargetLowering::ArgListTy Args; | ||||||
139 | Args.reserve(Ops.size()); | ||||||
140 | |||||||
141 | TargetLowering::ArgListEntry Entry; | ||||||
142 | for (unsigned i = 0; i < Ops.size(); ++i) { | ||||||
143 | SDValue NewOp = Ops[i]; | ||||||
144 | Entry.Node = NewOp; | ||||||
145 | Entry.Ty = Entry.Node.getValueType().getTypeForEVT(*DAG.getContext()); | ||||||
146 | Entry.IsSExt = shouldSignExtendTypeInLibCall(NewOp.getValueType(), | ||||||
147 | CallOptions.IsSExt); | ||||||
148 | Entry.IsZExt = !Entry.IsSExt; | ||||||
149 | |||||||
150 | if (CallOptions.IsSoften && | ||||||
151 | !shouldExtendTypeInLibCall(CallOptions.OpsVTBeforeSoften[i])) { | ||||||
152 | Entry.IsSExt = Entry.IsZExt = false; | ||||||
153 | } | ||||||
154 | Args.push_back(Entry); | ||||||
155 | } | ||||||
156 | |||||||
157 | if (LC == RTLIB::UNKNOWN_LIBCALL) | ||||||
158 | report_fatal_error("Unsupported library call operation!"); | ||||||
159 | SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC), | ||||||
160 | getPointerTy(DAG.getDataLayout())); | ||||||
161 | |||||||
162 | Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext()); | ||||||
163 | TargetLowering::CallLoweringInfo CLI(DAG); | ||||||
164 | bool signExtend = shouldSignExtendTypeInLibCall(RetVT, CallOptions.IsSExt); | ||||||
165 | bool zeroExtend = !signExtend; | ||||||
166 | |||||||
167 | if (CallOptions.IsSoften && | ||||||
168 | !shouldExtendTypeInLibCall(CallOptions.RetVTBeforeSoften)) { | ||||||
169 | signExtend = zeroExtend = false; | ||||||
170 | } | ||||||
171 | |||||||
172 | CLI.setDebugLoc(dl) | ||||||
173 | .setChain(InChain) | ||||||
174 | .setLibCallee(getLibcallCallingConv(LC), RetTy, Callee, std::move(Args)) | ||||||
175 | .setNoReturn(CallOptions.DoesNotReturn) | ||||||
176 | .setDiscardResult(!CallOptions.IsReturnValueUsed) | ||||||
177 | .setIsPostTypeLegalization(CallOptions.IsPostTypeLegalization) | ||||||
178 | .setSExtResult(signExtend) | ||||||
179 | .setZExtResult(zeroExtend); | ||||||
180 | return LowerCallTo(CLI); | ||||||
181 | } | ||||||
182 | |||||||
183 | bool TargetLowering::findOptimalMemOpLowering( | ||||||
184 | std::vector<EVT> &MemOps, unsigned Limit, const MemOp &Op, unsigned DstAS, | ||||||
185 | unsigned SrcAS, const AttributeList &FuncAttributes) const { | ||||||
186 | if (Op.isMemcpyWithFixedDstAlign() && Op.getSrcAlign() < Op.getDstAlign()) | ||||||
187 | return false; | ||||||
188 | |||||||
189 | EVT VT = getOptimalMemOpType(Op, FuncAttributes); | ||||||
190 | |||||||
191 | if (VT == MVT::Other) { | ||||||
192 | // Use the largest integer type whose alignment constraints are satisfied. | ||||||
193 | // We only need to check DstAlign here as SrcAlign is always greater or | ||||||
194 | // equal to DstAlign (or zero). | ||||||
195 | VT = MVT::i64; | ||||||
196 | if (Op.isFixedDstAlign()) | ||||||
197 | while (Op.getDstAlign() < (VT.getSizeInBits() / 8) && | ||||||
198 | !allowsMisalignedMemoryAccesses(VT, DstAS, Op.getDstAlign())) | ||||||
199 | VT = (MVT::SimpleValueType)(VT.getSimpleVT().SimpleTy - 1); | ||||||
200 | assert(VT.isInteger())((VT.isInteger()) ? static_cast<void> (0) : __assert_fail ("VT.isInteger()", "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 200, __PRETTY_FUNCTION__)); | ||||||
201 | |||||||
202 | // Find the largest legal integer type. | ||||||
203 | MVT LVT = MVT::i64; | ||||||
204 | while (!isTypeLegal(LVT)) | ||||||
205 | LVT = (MVT::SimpleValueType)(LVT.SimpleTy - 1); | ||||||
206 | assert(LVT.isInteger())((LVT.isInteger()) ? static_cast<void> (0) : __assert_fail ("LVT.isInteger()", "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 206, __PRETTY_FUNCTION__)); | ||||||
207 | |||||||
208 | // If the type we've chosen is larger than the largest legal integer type | ||||||
209 | // then use that instead. | ||||||
210 | if (VT.bitsGT(LVT)) | ||||||
211 | VT = LVT; | ||||||
212 | } | ||||||
213 | |||||||
214 | unsigned NumMemOps = 0; | ||||||
215 | uint64_t Size = Op.size(); | ||||||
216 | while (Size) { | ||||||
217 | unsigned VTSize = VT.getSizeInBits() / 8; | ||||||
218 | while (VTSize > Size) { | ||||||
219 | // For now, only use non-vector load / store's for the left-over pieces. | ||||||
220 | EVT NewVT = VT; | ||||||
221 | unsigned NewVTSize; | ||||||
222 | |||||||
223 | bool Found = false; | ||||||
224 | if (VT.isVector() || VT.isFloatingPoint()) { | ||||||
225 | NewVT = (VT.getSizeInBits() > 64) ? MVT::i64 : MVT::i32; | ||||||
226 | if (isOperationLegalOrCustom(ISD::STORE, NewVT) && | ||||||
227 | isSafeMemOpType(NewVT.getSimpleVT())) | ||||||
228 | Found = true; | ||||||
229 | else if (NewVT == MVT::i64 && | ||||||
230 | isOperationLegalOrCustom(ISD::STORE, MVT::f64) && | ||||||
231 | isSafeMemOpType(MVT::f64)) { | ||||||
232 | // i64 is usually not legal on 32-bit targets, but f64 may be. | ||||||
233 | NewVT = MVT::f64; | ||||||
234 | Found = true; | ||||||
235 | } | ||||||
236 | } | ||||||
237 | |||||||
238 | if (!Found) { | ||||||
239 | do { | ||||||
240 | NewVT = (MVT::SimpleValueType)(NewVT.getSimpleVT().SimpleTy - 1); | ||||||
241 | if (NewVT == MVT::i8) | ||||||
242 | break; | ||||||
243 | } while (!isSafeMemOpType(NewVT.getSimpleVT())); | ||||||
244 | } | ||||||
245 | NewVTSize = NewVT.getSizeInBits() / 8; | ||||||
246 | |||||||
247 | // If the new VT cannot cover all of the remaining bits, then consider | ||||||
248 | // issuing a (or a pair of) unaligned and overlapping load / store. | ||||||
249 | bool Fast; | ||||||
250 | if (NumMemOps && Op.allowOverlap() && NewVTSize < Size && | ||||||
251 | allowsMisalignedMemoryAccesses( | ||||||
252 | VT, DstAS, Op.isFixedDstAlign() ? Op.getDstAlign() : Align(1), | ||||||
253 | MachineMemOperand::MONone, &Fast) && | ||||||
254 | Fast) | ||||||
255 | VTSize = Size; | ||||||
256 | else { | ||||||
257 | VT = NewVT; | ||||||
258 | VTSize = NewVTSize; | ||||||
259 | } | ||||||
260 | } | ||||||
261 | |||||||
262 | if (++NumMemOps > Limit) | ||||||
263 | return false; | ||||||
264 | |||||||
265 | MemOps.push_back(VT); | ||||||
266 | Size -= VTSize; | ||||||
267 | } | ||||||
268 | |||||||
269 | return true; | ||||||
270 | } | ||||||
271 | |||||||
272 | /// Soften the operands of a comparison. This code is shared among BR_CC, | ||||||
273 | /// SELECT_CC, and SETCC handlers. | ||||||
274 | void TargetLowering::softenSetCCOperands(SelectionDAG &DAG, EVT VT, | ||||||
275 | SDValue &NewLHS, SDValue &NewRHS, | ||||||
276 | ISD::CondCode &CCCode, | ||||||
277 | const SDLoc &dl, const SDValue OldLHS, | ||||||
278 | const SDValue OldRHS) const { | ||||||
279 | SDValue Chain; | ||||||
280 | return softenSetCCOperands(DAG, VT, NewLHS, NewRHS, CCCode, dl, OldLHS, | ||||||
281 | OldRHS, Chain); | ||||||
282 | } | ||||||
283 | |||||||
284 | void TargetLowering::softenSetCCOperands(SelectionDAG &DAG, EVT VT, | ||||||
285 | SDValue &NewLHS, SDValue &NewRHS, | ||||||
286 | ISD::CondCode &CCCode, | ||||||
287 | const SDLoc &dl, const SDValue OldLHS, | ||||||
288 | const SDValue OldRHS, | ||||||
289 | SDValue &Chain, | ||||||
290 | bool IsSignaling) const { | ||||||
291 | // FIXME: Currently we cannot really respect all IEEE predicates due to libgcc | ||||||
292 | // not supporting it. We can update this code when libgcc provides such | ||||||
293 | // functions. | ||||||
294 | |||||||
295 | assert((VT == MVT::f32 || VT == MVT::f64 || VT == MVT::f128 || VT == MVT::ppcf128)(((VT == MVT::f32 || VT == MVT::f64 || VT == MVT::f128 || VT == MVT::ppcf128) && "Unsupported setcc type!") ? static_cast <void> (0) : __assert_fail ("(VT == MVT::f32 || VT == MVT::f64 || VT == MVT::f128 || VT == MVT::ppcf128) && \"Unsupported setcc type!\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 296, __PRETTY_FUNCTION__)) | ||||||
296 | && "Unsupported setcc type!")(((VT == MVT::f32 || VT == MVT::f64 || VT == MVT::f128 || VT == MVT::ppcf128) && "Unsupported setcc type!") ? static_cast <void> (0) : __assert_fail ("(VT == MVT::f32 || VT == MVT::f64 || VT == MVT::f128 || VT == MVT::ppcf128) && \"Unsupported setcc type!\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 296, __PRETTY_FUNCTION__)); | ||||||
297 | |||||||
298 | // Expand into one or more soft-fp libcall(s). | ||||||
299 | RTLIB::Libcall LC1 = RTLIB::UNKNOWN_LIBCALL, LC2 = RTLIB::UNKNOWN_LIBCALL; | ||||||
300 | bool ShouldInvertCC = false; | ||||||
301 | switch (CCCode) { | ||||||
302 | case ISD::SETEQ: | ||||||
303 | case ISD::SETOEQ: | ||||||
304 | LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : | ||||||
305 | (VT == MVT::f64) ? RTLIB::OEQ_F64 : | ||||||
306 | (VT == MVT::f128) ? RTLIB::OEQ_F128 : RTLIB::OEQ_PPCF128; | ||||||
307 | break; | ||||||
308 | case ISD::SETNE: | ||||||
309 | case ISD::SETUNE: | ||||||
310 | LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : | ||||||
311 | (VT == MVT::f64) ? RTLIB::UNE_F64 : | ||||||
312 | (VT == MVT::f128) ? RTLIB::UNE_F128 : RTLIB::UNE_PPCF128; | ||||||
313 | break; | ||||||
314 | case ISD::SETGE: | ||||||
315 | case ISD::SETOGE: | ||||||
316 | LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : | ||||||
317 | (VT == MVT::f64) ? RTLIB::OGE_F64 : | ||||||
318 | (VT == MVT::f128) ? RTLIB::OGE_F128 : RTLIB::OGE_PPCF128; | ||||||
319 | break; | ||||||
320 | case ISD::SETLT: | ||||||
321 | case ISD::SETOLT: | ||||||
322 | LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : | ||||||
323 | (VT == MVT::f64) ? RTLIB::OLT_F64 : | ||||||
324 | (VT == MVT::f128) ? RTLIB::OLT_F128 : RTLIB::OLT_PPCF128; | ||||||
325 | break; | ||||||
326 | case ISD::SETLE: | ||||||
327 | case ISD::SETOLE: | ||||||
328 | LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : | ||||||
329 | (VT == MVT::f64) ? RTLIB::OLE_F64 : | ||||||
330 | (VT == MVT::f128) ? RTLIB::OLE_F128 : RTLIB::OLE_PPCF128; | ||||||
331 | break; | ||||||
332 | case ISD::SETGT: | ||||||
333 | case ISD::SETOGT: | ||||||
334 | LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : | ||||||
335 | (VT == MVT::f64) ? RTLIB::OGT_F64 : | ||||||
336 | (VT == MVT::f128) ? RTLIB::OGT_F128 : RTLIB::OGT_PPCF128; | ||||||
337 | break; | ||||||
338 | case ISD::SETO: | ||||||
339 | ShouldInvertCC = true; | ||||||
340 | LLVM_FALLTHROUGH[[gnu::fallthrough]]; | ||||||
341 | case ISD::SETUO: | ||||||
342 | LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : | ||||||
343 | (VT == MVT::f64) ? RTLIB::UO_F64 : | ||||||
344 | (VT == MVT::f128) ? RTLIB::UO_F128 : RTLIB::UO_PPCF128; | ||||||
345 | break; | ||||||
346 | case ISD::SETONE: | ||||||
347 | // SETONE = O && UNE | ||||||
348 | ShouldInvertCC = true; | ||||||
349 | LLVM_FALLTHROUGH[[gnu::fallthrough]]; | ||||||
350 | case ISD::SETUEQ: | ||||||
351 | LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : | ||||||
352 | (VT == MVT::f64) ? RTLIB::UO_F64 : | ||||||
353 | (VT == MVT::f128) ? RTLIB::UO_F128 : RTLIB::UO_PPCF128; | ||||||
354 | LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : | ||||||
355 | (VT == MVT::f64) ? RTLIB::OEQ_F64 : | ||||||
356 | (VT == MVT::f128) ? RTLIB::OEQ_F128 : RTLIB::OEQ_PPCF128; | ||||||
357 | break; | ||||||
358 | default: | ||||||
359 | // Invert CC for unordered comparisons | ||||||
360 | ShouldInvertCC = true; | ||||||
361 | switch (CCCode) { | ||||||
362 | case ISD::SETULT: | ||||||
363 | LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : | ||||||
364 | (VT == MVT::f64) ? RTLIB::OGE_F64 : | ||||||
365 | (VT == MVT::f128) ? RTLIB::OGE_F128 : RTLIB::OGE_PPCF128; | ||||||
366 | break; | ||||||
367 | case ISD::SETULE: | ||||||
368 | LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : | ||||||
369 | (VT == MVT::f64) ? RTLIB::OGT_F64 : | ||||||
370 | (VT == MVT::f128) ? RTLIB::OGT_F128 : RTLIB::OGT_PPCF128; | ||||||
371 | break; | ||||||
372 | case ISD::SETUGT: | ||||||
373 | LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : | ||||||
374 | (VT == MVT::f64) ? RTLIB::OLE_F64 : | ||||||
375 | (VT == MVT::f128) ? RTLIB::OLE_F128 : RTLIB::OLE_PPCF128; | ||||||
376 | break; | ||||||
377 | case ISD::SETUGE: | ||||||
378 | LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : | ||||||
379 | (VT == MVT::f64) ? RTLIB::OLT_F64 : | ||||||
380 | (VT == MVT::f128) ? RTLIB::OLT_F128 : RTLIB::OLT_PPCF128; | ||||||
381 | break; | ||||||
382 | default: llvm_unreachable("Do not know how to soften this setcc!")::llvm::llvm_unreachable_internal("Do not know how to soften this setcc!" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 382); | ||||||
383 | } | ||||||
384 | } | ||||||
385 | |||||||
386 | // Use the target specific return value for comparions lib calls. | ||||||
387 | EVT RetVT = getCmpLibcallReturnType(); | ||||||
388 | SDValue Ops[2] = {NewLHS, NewRHS}; | ||||||
389 | TargetLowering::MakeLibCallOptions CallOptions; | ||||||
390 | EVT OpsVT[2] = { OldLHS.getValueType(), | ||||||
391 | OldRHS.getValueType() }; | ||||||
392 | CallOptions.setTypeListBeforeSoften(OpsVT, RetVT, true); | ||||||
393 | auto Call = makeLibCall(DAG, LC1, RetVT, Ops, CallOptions, dl, Chain); | ||||||
394 | NewLHS = Call.first; | ||||||
395 | NewRHS = DAG.getConstant(0, dl, RetVT); | ||||||
396 | |||||||
397 | CCCode = getCmpLibcallCC(LC1); | ||||||
398 | if (ShouldInvertCC) { | ||||||
399 | assert(RetVT.isInteger())((RetVT.isInteger()) ? static_cast<void> (0) : __assert_fail ("RetVT.isInteger()", "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 399, __PRETTY_FUNCTION__)); | ||||||
400 | CCCode = getSetCCInverse(CCCode, RetVT); | ||||||
401 | } | ||||||
402 | |||||||
403 | if (LC2 == RTLIB::UNKNOWN_LIBCALL) { | ||||||
404 | // Update Chain. | ||||||
405 | Chain = Call.second; | ||||||
406 | } else { | ||||||
407 | EVT SetCCVT = | ||||||
408 | getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), RetVT); | ||||||
409 | SDValue Tmp = DAG.getSetCC(dl, SetCCVT, NewLHS, NewRHS, CCCode); | ||||||
410 | auto Call2 = makeLibCall(DAG, LC2, RetVT, Ops, CallOptions, dl, Chain); | ||||||
411 | CCCode = getCmpLibcallCC(LC2); | ||||||
412 | if (ShouldInvertCC) | ||||||
413 | CCCode = getSetCCInverse(CCCode, RetVT); | ||||||
414 | NewLHS = DAG.getSetCC(dl, SetCCVT, Call2.first, NewRHS, CCCode); | ||||||
415 | if (Chain) | ||||||
416 | Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Call.second, | ||||||
417 | Call2.second); | ||||||
418 | NewLHS = DAG.getNode(ShouldInvertCC ? ISD::AND : ISD::OR, dl, | ||||||
419 | Tmp.getValueType(), Tmp, NewLHS); | ||||||
420 | NewRHS = SDValue(); | ||||||
421 | } | ||||||
422 | } | ||||||
423 | |||||||
424 | /// Return the entry encoding for a jump table in the current function. The | ||||||
425 | /// returned value is a member of the MachineJumpTableInfo::JTEntryKind enum. | ||||||
426 | unsigned TargetLowering::getJumpTableEncoding() const { | ||||||
427 | // In non-pic modes, just use the address of a block. | ||||||
428 | if (!isPositionIndependent()) | ||||||
429 | return MachineJumpTableInfo::EK_BlockAddress; | ||||||
430 | |||||||
431 | // In PIC mode, if the target supports a GPRel32 directive, use it. | ||||||
432 | if (getTargetMachine().getMCAsmInfo()->getGPRel32Directive() != nullptr) | ||||||
433 | return MachineJumpTableInfo::EK_GPRel32BlockAddress; | ||||||
434 | |||||||
435 | // Otherwise, use a label difference. | ||||||
436 | return MachineJumpTableInfo::EK_LabelDifference32; | ||||||
437 | } | ||||||
438 | |||||||
439 | SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table, | ||||||
440 | SelectionDAG &DAG) const { | ||||||
441 | // If our PIC model is GP relative, use the global offset table as the base. | ||||||
442 | unsigned JTEncoding = getJumpTableEncoding(); | ||||||
443 | |||||||
444 | if ((JTEncoding == MachineJumpTableInfo::EK_GPRel64BlockAddress) || | ||||||
445 | (JTEncoding == MachineJumpTableInfo::EK_GPRel32BlockAddress)) | ||||||
446 | return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy(DAG.getDataLayout())); | ||||||
447 | |||||||
448 | return Table; | ||||||
449 | } | ||||||
450 | |||||||
451 | /// This returns the relocation base for the given PIC jumptable, the same as | ||||||
452 | /// getPICJumpTableRelocBase, but as an MCExpr. | ||||||
453 | const MCExpr * | ||||||
454 | TargetLowering::getPICJumpTableRelocBaseExpr(const MachineFunction *MF, | ||||||
455 | unsigned JTI,MCContext &Ctx) const{ | ||||||
456 | // The normal PIC reloc base is the label at the start of the jump table. | ||||||
457 | return MCSymbolRefExpr::create(MF->getJTISymbol(JTI, Ctx), Ctx); | ||||||
458 | } | ||||||
459 | |||||||
460 | bool | ||||||
461 | TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { | ||||||
462 | const TargetMachine &TM = getTargetMachine(); | ||||||
463 | const GlobalValue *GV = GA->getGlobal(); | ||||||
464 | |||||||
465 | // If the address is not even local to this DSO we will have to load it from | ||||||
466 | // a got and then add the offset. | ||||||
467 | if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV)) | ||||||
468 | return false; | ||||||
469 | |||||||
470 | // If the code is position independent we will have to add a base register. | ||||||
471 | if (isPositionIndependent()) | ||||||
472 | return false; | ||||||
473 | |||||||
474 | // Otherwise we can do it. | ||||||
475 | return true; | ||||||
476 | } | ||||||
477 | |||||||
478 | //===----------------------------------------------------------------------===// | ||||||
479 | // Optimization Methods | ||||||
480 | //===----------------------------------------------------------------------===// | ||||||
481 | |||||||
482 | /// If the specified instruction has a constant integer operand and there are | ||||||
483 | /// bits set in that constant that are not demanded, then clear those bits and | ||||||
484 | /// return true. | ||||||
485 | bool TargetLowering::ShrinkDemandedConstant(SDValue Op, | ||||||
486 | const APInt &DemandedBits, | ||||||
487 | const APInt &DemandedElts, | ||||||
488 | TargetLoweringOpt &TLO) const { | ||||||
489 | SDLoc DL(Op); | ||||||
490 | unsigned Opcode = Op.getOpcode(); | ||||||
491 | |||||||
492 | // Do target-specific constant optimization. | ||||||
493 | if (targetShrinkDemandedConstant(Op, DemandedBits, DemandedElts, TLO)) | ||||||
494 | return TLO.New.getNode(); | ||||||
495 | |||||||
496 | // FIXME: ISD::SELECT, ISD::SELECT_CC | ||||||
497 | switch (Opcode) { | ||||||
498 | default: | ||||||
499 | break; | ||||||
500 | case ISD::XOR: | ||||||
501 | case ISD::AND: | ||||||
502 | case ISD::OR: { | ||||||
503 | auto *Op1C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); | ||||||
504 | if (!Op1C) | ||||||
505 | return false; | ||||||
506 | |||||||
507 | // If this is a 'not' op, don't touch it because that's a canonical form. | ||||||
508 | const APInt &C = Op1C->getAPIntValue(); | ||||||
509 | if (Opcode == ISD::XOR && DemandedBits.isSubsetOf(C)) | ||||||
510 | return false; | ||||||
511 | |||||||
512 | if (!C.isSubsetOf(DemandedBits)) { | ||||||
513 | EVT VT = Op.getValueType(); | ||||||
514 | SDValue NewC = TLO.DAG.getConstant(DemandedBits & C, DL, VT); | ||||||
515 | SDValue NewOp = TLO.DAG.getNode(Opcode, DL, VT, Op.getOperand(0), NewC); | ||||||
516 | return TLO.CombineTo(Op, NewOp); | ||||||
517 | } | ||||||
518 | |||||||
519 | break; | ||||||
520 | } | ||||||
521 | } | ||||||
522 | |||||||
523 | return false; | ||||||
524 | } | ||||||
525 | |||||||
526 | bool TargetLowering::ShrinkDemandedConstant(SDValue Op, | ||||||
527 | const APInt &DemandedBits, | ||||||
528 | TargetLoweringOpt &TLO) const { | ||||||
529 | EVT VT = Op.getValueType(); | ||||||
530 | APInt DemandedElts = VT.isVector() | ||||||
531 | ? APInt::getAllOnesValue(VT.getVectorNumElements()) | ||||||
532 | : APInt(1, 1); | ||||||
533 | return ShrinkDemandedConstant(Op, DemandedBits, DemandedElts, TLO); | ||||||
534 | } | ||||||
535 | |||||||
536 | /// Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free. | ||||||
537 | /// This uses isZExtFree and ZERO_EXTEND for the widening cast, but it could be | ||||||
538 | /// generalized for targets with other types of implicit widening casts. | ||||||
539 | bool TargetLowering::ShrinkDemandedOp(SDValue Op, unsigned BitWidth, | ||||||
540 | const APInt &Demanded, | ||||||
541 | TargetLoweringOpt &TLO) const { | ||||||
542 | assert(Op.getNumOperands() == 2 &&((Op.getNumOperands() == 2 && "ShrinkDemandedOp only supports binary operators!" ) ? static_cast<void> (0) : __assert_fail ("Op.getNumOperands() == 2 && \"ShrinkDemandedOp only supports binary operators!\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 543, __PRETTY_FUNCTION__)) | ||||||
543 | "ShrinkDemandedOp only supports binary operators!")((Op.getNumOperands() == 2 && "ShrinkDemandedOp only supports binary operators!" ) ? static_cast<void> (0) : __assert_fail ("Op.getNumOperands() == 2 && \"ShrinkDemandedOp only supports binary operators!\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 543, __PRETTY_FUNCTION__)); | ||||||
544 | assert(Op.getNode()->getNumValues() == 1 &&((Op.getNode()->getNumValues() == 1 && "ShrinkDemandedOp only supports nodes with one result!" ) ? static_cast<void> (0) : __assert_fail ("Op.getNode()->getNumValues() == 1 && \"ShrinkDemandedOp only supports nodes with one result!\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 545, __PRETTY_FUNCTION__)) | ||||||
545 | "ShrinkDemandedOp only supports nodes with one result!")((Op.getNode()->getNumValues() == 1 && "ShrinkDemandedOp only supports nodes with one result!" ) ? static_cast<void> (0) : __assert_fail ("Op.getNode()->getNumValues() == 1 && \"ShrinkDemandedOp only supports nodes with one result!\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 545, __PRETTY_FUNCTION__)); | ||||||
546 | |||||||
547 | SelectionDAG &DAG = TLO.DAG; | ||||||
548 | SDLoc dl(Op); | ||||||
549 | |||||||
550 | // Early return, as this function cannot handle vector types. | ||||||
551 | if (Op.getValueType().isVector()) | ||||||
552 | return false; | ||||||
553 | |||||||
554 | // Don't do this if the node has another user, which may require the | ||||||
555 | // full value. | ||||||
556 | if (!Op.getNode()->hasOneUse()) | ||||||
557 | return false; | ||||||
558 | |||||||
559 | // Search for the smallest integer type with free casts to and from | ||||||
560 | // Op's type. For expedience, just check power-of-2 integer types. | ||||||
561 | const TargetLowering &TLI = DAG.getTargetLoweringInfo(); | ||||||
562 | unsigned DemandedSize = Demanded.getActiveBits(); | ||||||
563 | unsigned SmallVTBits = DemandedSize; | ||||||
564 | if (!isPowerOf2_32(SmallVTBits)) | ||||||
565 | SmallVTBits = NextPowerOf2(SmallVTBits); | ||||||
566 | for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) { | ||||||
567 | EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), SmallVTBits); | ||||||
568 | if (TLI.isTruncateFree(Op.getValueType(), SmallVT) && | ||||||
569 | TLI.isZExtFree(SmallVT, Op.getValueType())) { | ||||||
570 | // We found a type with free casts. | ||||||
571 | SDValue X = DAG.getNode( | ||||||
572 | Op.getOpcode(), dl, SmallVT, | ||||||
573 | DAG.getNode(ISD::TRUNCATE, dl, SmallVT, Op.getOperand(0)), | ||||||
574 | DAG.getNode(ISD::TRUNCATE, dl, SmallVT, Op.getOperand(1))); | ||||||
575 | assert(DemandedSize <= SmallVTBits && "Narrowed below demanded bits?")((DemandedSize <= SmallVTBits && "Narrowed below demanded bits?" ) ? static_cast<void> (0) : __assert_fail ("DemandedSize <= SmallVTBits && \"Narrowed below demanded bits?\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 575, __PRETTY_FUNCTION__)); | ||||||
576 | SDValue Z = DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(), X); | ||||||
577 | return TLO.CombineTo(Op, Z); | ||||||
578 | } | ||||||
579 | } | ||||||
580 | return false; | ||||||
581 | } | ||||||
582 | |||||||
583 | bool TargetLowering::SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits, | ||||||
584 | DAGCombinerInfo &DCI) const { | ||||||
585 | SelectionDAG &DAG = DCI.DAG; | ||||||
586 | TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), | ||||||
587 | !DCI.isBeforeLegalizeOps()); | ||||||
588 | KnownBits Known; | ||||||
589 | |||||||
590 | bool Simplified = SimplifyDemandedBits(Op, DemandedBits, Known, TLO); | ||||||
591 | if (Simplified) { | ||||||
592 | DCI.AddToWorklist(Op.getNode()); | ||||||
593 | DCI.CommitTargetLoweringOpt(TLO); | ||||||
594 | } | ||||||
595 | return Simplified; | ||||||
596 | } | ||||||
597 | |||||||
598 | bool TargetLowering::SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits, | ||||||
599 | KnownBits &Known, | ||||||
600 | TargetLoweringOpt &TLO, | ||||||
601 | unsigned Depth, | ||||||
602 | bool AssumeSingleUse) const { | ||||||
603 | EVT VT = Op.getValueType(); | ||||||
604 | |||||||
605 | // TODO: We can probably do more work on calculating the known bits and | ||||||
606 | // simplifying the operations for scalable vectors, but for now we just | ||||||
607 | // bail out. | ||||||
608 | if (VT.isScalableVector()) { | ||||||
609 | // Pretend we don't know anything for now. | ||||||
610 | Known = KnownBits(DemandedBits.getBitWidth()); | ||||||
611 | return false; | ||||||
612 | } | ||||||
613 | |||||||
614 | APInt DemandedElts = VT.isVector() | ||||||
615 | ? APInt::getAllOnesValue(VT.getVectorNumElements()) | ||||||
616 | : APInt(1, 1); | ||||||
617 | return SimplifyDemandedBits(Op, DemandedBits, DemandedElts, Known, TLO, Depth, | ||||||
618 | AssumeSingleUse); | ||||||
619 | } | ||||||
620 | |||||||
621 | // TODO: Can we merge SelectionDAG::GetDemandedBits into this? | ||||||
622 | // TODO: Under what circumstances can we create nodes? Constant folding? | ||||||
623 | SDValue TargetLowering::SimplifyMultipleUseDemandedBits( | ||||||
624 | SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, | ||||||
625 | SelectionDAG &DAG, unsigned Depth) const { | ||||||
626 | // Limit search depth. | ||||||
627 | if (Depth >= SelectionDAG::MaxRecursionDepth) | ||||||
628 | return SDValue(); | ||||||
629 | |||||||
630 | // Ignore UNDEFs. | ||||||
631 | if (Op.isUndef()) | ||||||
632 | return SDValue(); | ||||||
633 | |||||||
634 | // Not demanding any bits/elts from Op. | ||||||
635 | if (DemandedBits == 0 || DemandedElts == 0) | ||||||
636 | return DAG.getUNDEF(Op.getValueType()); | ||||||
637 | |||||||
638 | unsigned NumElts = DemandedElts.getBitWidth(); | ||||||
639 | unsigned BitWidth = DemandedBits.getBitWidth(); | ||||||
640 | KnownBits LHSKnown, RHSKnown; | ||||||
641 | switch (Op.getOpcode()) { | ||||||
642 | case ISD::BITCAST: { | ||||||
643 | SDValue Src = peekThroughBitcasts(Op.getOperand(0)); | ||||||
644 | EVT SrcVT = Src.getValueType(); | ||||||
645 | EVT DstVT = Op.getValueType(); | ||||||
646 | if (SrcVT == DstVT) | ||||||
647 | return Src; | ||||||
648 | |||||||
649 | unsigned NumSrcEltBits = SrcVT.getScalarSizeInBits(); | ||||||
650 | unsigned NumDstEltBits = DstVT.getScalarSizeInBits(); | ||||||
651 | if (NumSrcEltBits == NumDstEltBits) | ||||||
652 | if (SDValue V = SimplifyMultipleUseDemandedBits( | ||||||
653 | Src, DemandedBits, DemandedElts, DAG, Depth + 1)) | ||||||
654 | return DAG.getBitcast(DstVT, V); | ||||||
655 | |||||||
656 | // TODO - bigendian once we have test coverage. | ||||||
657 | if (SrcVT.isVector() && (NumDstEltBits % NumSrcEltBits) == 0 && | ||||||
658 | DAG.getDataLayout().isLittleEndian()) { | ||||||
659 | unsigned Scale = NumDstEltBits / NumSrcEltBits; | ||||||
660 | unsigned NumSrcElts = SrcVT.getVectorNumElements(); | ||||||
661 | APInt DemandedSrcBits = APInt::getNullValue(NumSrcEltBits); | ||||||
662 | APInt DemandedSrcElts = APInt::getNullValue(NumSrcElts); | ||||||
663 | for (unsigned i = 0; i != Scale; ++i) { | ||||||
664 | unsigned Offset = i * NumSrcEltBits; | ||||||
665 | APInt Sub = DemandedBits.extractBits(NumSrcEltBits, Offset); | ||||||
666 | if (!Sub.isNullValue()) { | ||||||
667 | DemandedSrcBits |= Sub; | ||||||
668 | for (unsigned j = 0; j != NumElts; ++j) | ||||||
669 | if (DemandedElts[j]) | ||||||
670 | DemandedSrcElts.setBit((j * Scale) + i); | ||||||
671 | } | ||||||
672 | } | ||||||
673 | |||||||
674 | if (SDValue V = SimplifyMultipleUseDemandedBits( | ||||||
675 | Src, DemandedSrcBits, DemandedSrcElts, DAG, Depth + 1)) | ||||||
676 | return DAG.getBitcast(DstVT, V); | ||||||
677 | } | ||||||
678 | |||||||
679 | // TODO - bigendian once we have test coverage. | ||||||
680 | if ((NumSrcEltBits % NumDstEltBits) == 0 && | ||||||
681 | DAG.getDataLayout().isLittleEndian()) { | ||||||
682 | unsigned Scale = NumSrcEltBits / NumDstEltBits; | ||||||
683 | unsigned NumSrcElts = SrcVT.isVector() ? SrcVT.getVectorNumElements() : 1; | ||||||
684 | APInt DemandedSrcBits = APInt::getNullValue(NumSrcEltBits); | ||||||
685 | APInt DemandedSrcElts = APInt::getNullValue(NumSrcElts); | ||||||
686 | for (unsigned i = 0; i != NumElts; ++i) | ||||||
687 | if (DemandedElts[i]) { | ||||||
688 | unsigned Offset = (i % Scale) * NumDstEltBits; | ||||||
689 | DemandedSrcBits.insertBits(DemandedBits, Offset); | ||||||
690 | DemandedSrcElts.setBit(i / Scale); | ||||||
691 | } | ||||||
692 | |||||||
693 | if (SDValue V = SimplifyMultipleUseDemandedBits( | ||||||
694 | Src, DemandedSrcBits, DemandedSrcElts, DAG, Depth + 1)) | ||||||
695 | return DAG.getBitcast(DstVT, V); | ||||||
696 | } | ||||||
697 | |||||||
698 | break; | ||||||
699 | } | ||||||
700 | case ISD::AND: { | ||||||
701 | LHSKnown = DAG.computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1); | ||||||
702 | RHSKnown = DAG.computeKnownBits(Op.getOperand(1), DemandedElts, Depth + 1); | ||||||
703 | |||||||
704 | // If all of the demanded bits are known 1 on one side, return the other. | ||||||
705 | // These bits cannot contribute to the result of the 'and' in this | ||||||
706 | // context. | ||||||
707 | if (DemandedBits.isSubsetOf(LHSKnown.Zero | RHSKnown.One)) | ||||||
708 | return Op.getOperand(0); | ||||||
709 | if (DemandedBits.isSubsetOf(RHSKnown.Zero | LHSKnown.One)) | ||||||
710 | return Op.getOperand(1); | ||||||
711 | break; | ||||||
712 | } | ||||||
713 | case ISD::OR: { | ||||||
714 | LHSKnown = DAG.computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1); | ||||||
715 | RHSKnown = DAG.computeKnownBits(Op.getOperand(1), DemandedElts, Depth + 1); | ||||||
716 | |||||||
717 | // If all of the demanded bits are known zero on one side, return the | ||||||
718 | // other. These bits cannot contribute to the result of the 'or' in this | ||||||
719 | // context. | ||||||
720 | if (DemandedBits.isSubsetOf(LHSKnown.One | RHSKnown.Zero)) | ||||||
721 | return Op.getOperand(0); | ||||||
722 | if (DemandedBits.isSubsetOf(RHSKnown.One | LHSKnown.Zero)) | ||||||
723 | return Op.getOperand(1); | ||||||
724 | break; | ||||||
725 | } | ||||||
726 | case ISD::XOR: { | ||||||
727 | LHSKnown = DAG.computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1); | ||||||
728 | RHSKnown = DAG.computeKnownBits(Op.getOperand(1), DemandedElts, Depth + 1); | ||||||
729 | |||||||
730 | // If all of the demanded bits are known zero on one side, return the | ||||||
731 | // other. | ||||||
732 | if (DemandedBits.isSubsetOf(RHSKnown.Zero)) | ||||||
733 | return Op.getOperand(0); | ||||||
734 | if (DemandedBits.isSubsetOf(LHSKnown.Zero)) | ||||||
735 | return Op.getOperand(1); | ||||||
736 | break; | ||||||
737 | } | ||||||
738 | case ISD::SHL: { | ||||||
739 | // If we are only demanding sign bits then we can use the shift source | ||||||
740 | // directly. | ||||||
741 | if (const APInt *MaxSA = | ||||||
742 | DAG.getValidMaximumShiftAmountConstant(Op, DemandedElts)) { | ||||||
743 | SDValue Op0 = Op.getOperand(0); | ||||||
744 | unsigned ShAmt = MaxSA->getZExtValue(); | ||||||
745 | unsigned NumSignBits = | ||||||
746 | DAG.ComputeNumSignBits(Op0, DemandedElts, Depth + 1); | ||||||
747 | unsigned UpperDemandedBits = BitWidth - DemandedBits.countTrailingZeros(); | ||||||
748 | if (NumSignBits > ShAmt && (NumSignBits - ShAmt) >= (UpperDemandedBits)) | ||||||
749 | return Op0; | ||||||
750 | } | ||||||
751 | break; | ||||||
752 | } | ||||||
753 | case ISD::SETCC: { | ||||||
754 | SDValue Op0 = Op.getOperand(0); | ||||||
755 | SDValue Op1 = Op.getOperand(1); | ||||||
756 | ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); | ||||||
757 | // If (1) we only need the sign-bit, (2) the setcc operands are the same | ||||||
758 | // width as the setcc result, and (3) the result of a setcc conforms to 0 or | ||||||
759 | // -1, we may be able to bypass the setcc. | ||||||
760 | if (DemandedBits.isSignMask() && | ||||||
761 | Op0.getScalarValueSizeInBits() == BitWidth && | ||||||
762 | getBooleanContents(Op0.getValueType()) == | ||||||
763 | BooleanContent::ZeroOrNegativeOneBooleanContent) { | ||||||
764 | // If we're testing X < 0, then this compare isn't needed - just use X! | ||||||
765 | // FIXME: We're limiting to integer types here, but this should also work | ||||||
766 | // if we don't care about FP signed-zero. The use of SETLT with FP means | ||||||
767 | // that we don't care about NaNs. | ||||||
768 | if (CC == ISD::SETLT && Op1.getValueType().isInteger() && | ||||||
769 | (isNullConstant(Op1) || ISD::isBuildVectorAllZeros(Op1.getNode()))) | ||||||
770 | return Op0; | ||||||
771 | } | ||||||
772 | break; | ||||||
773 | } | ||||||
774 | case ISD::SIGN_EXTEND_INREG: { | ||||||
775 | // If none of the extended bits are demanded, eliminate the sextinreg. | ||||||
776 | SDValue Op0 = Op.getOperand(0); | ||||||
777 | EVT ExVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); | ||||||
778 | unsigned ExBits = ExVT.getScalarSizeInBits(); | ||||||
779 | if (DemandedBits.getActiveBits() <= ExBits) | ||||||
780 | return Op0; | ||||||
781 | // If the input is already sign extended, just drop the extension. | ||||||
782 | unsigned NumSignBits = DAG.ComputeNumSignBits(Op0, DemandedElts, Depth + 1); | ||||||
783 | if (NumSignBits >= (BitWidth - ExBits + 1)) | ||||||
784 | return Op0; | ||||||
785 | break; | ||||||
786 | } | ||||||
787 | case ISD::ANY_EXTEND_VECTOR_INREG: | ||||||
788 | case ISD::SIGN_EXTEND_VECTOR_INREG: | ||||||
789 | case ISD::ZERO_EXTEND_VECTOR_INREG: { | ||||||
790 | // If we only want the lowest element and none of extended bits, then we can | ||||||
791 | // return the bitcasted source vector. | ||||||
792 | SDValue Src = Op.getOperand(0); | ||||||
793 | EVT SrcVT = Src.getValueType(); | ||||||
794 | EVT DstVT = Op.getValueType(); | ||||||
795 | if (DemandedElts == 1 && DstVT.getSizeInBits() == SrcVT.getSizeInBits() && | ||||||
796 | DAG.getDataLayout().isLittleEndian() && | ||||||
797 | DemandedBits.getActiveBits() <= SrcVT.getScalarSizeInBits()) { | ||||||
798 | return DAG.getBitcast(DstVT, Src); | ||||||
799 | } | ||||||
800 | break; | ||||||
801 | } | ||||||
802 | case ISD::INSERT_VECTOR_ELT: { | ||||||
803 | // If we don't demand the inserted element, return the base vector. | ||||||
804 | SDValue Vec = Op.getOperand(0); | ||||||
805 | auto *CIdx = dyn_cast<ConstantSDNode>(Op.getOperand(2)); | ||||||
806 | EVT VecVT = Vec.getValueType(); | ||||||
807 | if (CIdx && CIdx->getAPIntValue().ult(VecVT.getVectorNumElements()) && | ||||||
808 | !DemandedElts[CIdx->getZExtValue()]) | ||||||
809 | return Vec; | ||||||
810 | break; | ||||||
811 | } | ||||||
812 | case ISD::INSERT_SUBVECTOR: { | ||||||
813 | // If we don't demand the inserted subvector, return the base vector. | ||||||
814 | SDValue Vec = Op.getOperand(0); | ||||||
815 | SDValue Sub = Op.getOperand(1); | ||||||
816 | uint64_t Idx = Op.getConstantOperandVal(2); | ||||||
817 | unsigned NumSubElts = Sub.getValueType().getVectorNumElements(); | ||||||
818 | if (DemandedElts.extractBits(NumSubElts, Idx) == 0) | ||||||
819 | return Vec; | ||||||
820 | break; | ||||||
821 | } | ||||||
822 | case ISD::VECTOR_SHUFFLE: { | ||||||
823 | ArrayRef<int> ShuffleMask = cast<ShuffleVectorSDNode>(Op)->getMask(); | ||||||
824 | |||||||
825 | // If all the demanded elts are from one operand and are inline, | ||||||
826 | // then we can use the operand directly. | ||||||
827 | bool AllUndef = true, IdentityLHS = true, IdentityRHS = true; | ||||||
828 | for (unsigned i = 0; i != NumElts; ++i) { | ||||||
829 | int M = ShuffleMask[i]; | ||||||
830 | if (M < 0 || !DemandedElts[i]) | ||||||
831 | continue; | ||||||
832 | AllUndef = false; | ||||||
833 | IdentityLHS &= (M == (int)i); | ||||||
834 | IdentityRHS &= ((M - NumElts) == i); | ||||||
835 | } | ||||||
836 | |||||||
837 | if (AllUndef) | ||||||
838 | return DAG.getUNDEF(Op.getValueType()); | ||||||
839 | if (IdentityLHS) | ||||||
840 | return Op.getOperand(0); | ||||||
841 | if (IdentityRHS) | ||||||
842 | return Op.getOperand(1); | ||||||
843 | break; | ||||||
844 | } | ||||||
845 | default: | ||||||
846 | if (Op.getOpcode() >= ISD::BUILTIN_OP_END) | ||||||
847 | if (SDValue V = SimplifyMultipleUseDemandedBitsForTargetNode( | ||||||
848 | Op, DemandedBits, DemandedElts, DAG, Depth)) | ||||||
849 | return V; | ||||||
850 | break; | ||||||
851 | } | ||||||
852 | return SDValue(); | ||||||
853 | } | ||||||
854 | |||||||
855 | SDValue TargetLowering::SimplifyMultipleUseDemandedBits( | ||||||
856 | SDValue Op, const APInt &DemandedBits, SelectionDAG &DAG, | ||||||
857 | unsigned Depth) const { | ||||||
858 | EVT VT = Op.getValueType(); | ||||||
859 | APInt DemandedElts = VT.isVector() | ||||||
860 | ? APInt::getAllOnesValue(VT.getVectorNumElements()) | ||||||
861 | : APInt(1, 1); | ||||||
862 | return SimplifyMultipleUseDemandedBits(Op, DemandedBits, DemandedElts, DAG, | ||||||
863 | Depth); | ||||||
864 | } | ||||||
865 | |||||||
866 | SDValue TargetLowering::SimplifyMultipleUseDemandedVectorElts( | ||||||
867 | SDValue Op, const APInt &DemandedElts, SelectionDAG &DAG, | ||||||
868 | unsigned Depth) const { | ||||||
869 | APInt DemandedBits = APInt::getAllOnesValue(Op.getScalarValueSizeInBits()); | ||||||
870 | return SimplifyMultipleUseDemandedBits(Op, DemandedBits, DemandedElts, DAG, | ||||||
871 | Depth); | ||||||
872 | } | ||||||
873 | |||||||
874 | /// Look at Op. At this point, we know that only the OriginalDemandedBits of the | ||||||
875 | /// result of Op are ever used downstream. If we can use this information to | ||||||
876 | /// simplify Op, create a new simplified DAG node and return true, returning the | ||||||
877 | /// original and new nodes in Old and New. Otherwise, analyze the expression and | ||||||
878 | /// return a mask of Known bits for the expression (used to simplify the | ||||||
879 | /// caller). The Known bits may only be accurate for those bits in the | ||||||
880 | /// OriginalDemandedBits and OriginalDemandedElts. | ||||||
881 | bool TargetLowering::SimplifyDemandedBits( | ||||||
882 | SDValue Op, const APInt &OriginalDemandedBits, | ||||||
883 | const APInt &OriginalDemandedElts, KnownBits &Known, TargetLoweringOpt &TLO, | ||||||
884 | unsigned Depth, bool AssumeSingleUse) const { | ||||||
885 | unsigned BitWidth = OriginalDemandedBits.getBitWidth(); | ||||||
886 | assert(Op.getScalarValueSizeInBits() == BitWidth &&((Op.getScalarValueSizeInBits() == BitWidth && "Mask size mismatches value type size!" ) ? static_cast<void> (0) : __assert_fail ("Op.getScalarValueSizeInBits() == BitWidth && \"Mask size mismatches value type size!\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 887, __PRETTY_FUNCTION__)) | ||||||
887 | "Mask size mismatches value type size!")((Op.getScalarValueSizeInBits() == BitWidth && "Mask size mismatches value type size!" ) ? static_cast<void> (0) : __assert_fail ("Op.getScalarValueSizeInBits() == BitWidth && \"Mask size mismatches value type size!\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 887, __PRETTY_FUNCTION__)); | ||||||
888 | |||||||
889 | // Don't know anything. | ||||||
890 | Known = KnownBits(BitWidth); | ||||||
891 | |||||||
892 | // TODO: We can probably do more work on calculating the known bits and | ||||||
893 | // simplifying the operations for scalable vectors, but for now we just | ||||||
894 | // bail out. | ||||||
895 | if (Op.getValueType().isScalableVector()) | ||||||
896 | return false; | ||||||
897 | |||||||
898 | unsigned NumElts = OriginalDemandedElts.getBitWidth(); | ||||||
899 | assert((!Op.getValueType().isVector() ||(((!Op.getValueType().isVector() || NumElts == Op.getValueType ().getVectorNumElements()) && "Unexpected vector size" ) ? static_cast<void> (0) : __assert_fail ("(!Op.getValueType().isVector() || NumElts == Op.getValueType().getVectorNumElements()) && \"Unexpected vector size\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 901, __PRETTY_FUNCTION__)) | ||||||
900 | NumElts == Op.getValueType().getVectorNumElements()) &&(((!Op.getValueType().isVector() || NumElts == Op.getValueType ().getVectorNumElements()) && "Unexpected vector size" ) ? static_cast<void> (0) : __assert_fail ("(!Op.getValueType().isVector() || NumElts == Op.getValueType().getVectorNumElements()) && \"Unexpected vector size\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 901, __PRETTY_FUNCTION__)) | ||||||
901 | "Unexpected vector size")(((!Op.getValueType().isVector() || NumElts == Op.getValueType ().getVectorNumElements()) && "Unexpected vector size" ) ? static_cast<void> (0) : __assert_fail ("(!Op.getValueType().isVector() || NumElts == Op.getValueType().getVectorNumElements()) && \"Unexpected vector size\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 901, __PRETTY_FUNCTION__)); | ||||||
902 | |||||||
903 | APInt DemandedBits = OriginalDemandedBits; | ||||||
904 | APInt DemandedElts = OriginalDemandedElts; | ||||||
905 | SDLoc dl(Op); | ||||||
906 | auto &DL = TLO.DAG.getDataLayout(); | ||||||
907 | |||||||
908 | // Undef operand. | ||||||
909 | if (Op.isUndef()) | ||||||
910 | return false; | ||||||
911 | |||||||
912 | if (Op.getOpcode() == ISD::Constant) { | ||||||
913 | // We know all of the bits for a constant! | ||||||
914 | Known = KnownBits::makeConstant(cast<ConstantSDNode>(Op)->getAPIntValue()); | ||||||
915 | return false; | ||||||
916 | } | ||||||
917 | |||||||
918 | if (Op.getOpcode() == ISD::ConstantFP) { | ||||||
919 | // We know all of the bits for a floating point constant! | ||||||
920 | Known = KnownBits::makeConstant( | ||||||
921 | cast<ConstantFPSDNode>(Op)->getValueAPF().bitcastToAPInt()); | ||||||
922 | return false; | ||||||
923 | } | ||||||
924 | |||||||
925 | // Other users may use these bits. | ||||||
926 | EVT VT = Op.getValueType(); | ||||||
927 | if (!Op.getNode()->hasOneUse() && !AssumeSingleUse) { | ||||||
928 | if (Depth != 0) { | ||||||
929 | // If not at the root, Just compute the Known bits to | ||||||
930 | // simplify things downstream. | ||||||
931 | Known = TLO.DAG.computeKnownBits(Op, DemandedElts, Depth); | ||||||
932 | return false; | ||||||
933 | } | ||||||
934 | // If this is the root being simplified, allow it to have multiple uses, | ||||||
935 | // just set the DemandedBits/Elts to all bits. | ||||||
936 | DemandedBits = APInt::getAllOnesValue(BitWidth); | ||||||
937 | DemandedElts = APInt::getAllOnesValue(NumElts); | ||||||
938 | } else if (OriginalDemandedBits == 0 || OriginalDemandedElts == 0) { | ||||||
939 | // Not demanding any bits/elts from Op. | ||||||
940 | return TLO.CombineTo(Op, TLO.DAG.getUNDEF(VT)); | ||||||
941 | } else if (Depth >= SelectionDAG::MaxRecursionDepth) { | ||||||
942 | // Limit search depth. | ||||||
943 | return false; | ||||||
944 | } | ||||||
945 | |||||||
946 | KnownBits Known2; | ||||||
947 | switch (Op.getOpcode()) { | ||||||
948 | case ISD::TargetConstant: | ||||||
949 | llvm_unreachable("Can't simplify this node")::llvm::llvm_unreachable_internal("Can't simplify this node", "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 949); | ||||||
950 | case ISD::SCALAR_TO_VECTOR: { | ||||||
951 | if (!DemandedElts[0]) | ||||||
952 | return TLO.CombineTo(Op, TLO.DAG.getUNDEF(VT)); | ||||||
953 | |||||||
954 | KnownBits SrcKnown; | ||||||
955 | SDValue Src = Op.getOperand(0); | ||||||
956 | unsigned SrcBitWidth = Src.getScalarValueSizeInBits(); | ||||||
957 | APInt SrcDemandedBits = DemandedBits.zextOrSelf(SrcBitWidth); | ||||||
958 | if (SimplifyDemandedBits(Src, SrcDemandedBits, SrcKnown, TLO, Depth + 1)) | ||||||
959 | return true; | ||||||
960 | |||||||
961 | // Upper elements are undef, so only get the knownbits if we just demand | ||||||
962 | // the bottom element. | ||||||
963 | if (DemandedElts == 1) | ||||||
964 | Known = SrcKnown.anyextOrTrunc(BitWidth); | ||||||
965 | break; | ||||||
966 | } | ||||||
967 | case ISD::BUILD_VECTOR: | ||||||
968 | // Collect the known bits that are shared by every demanded element. | ||||||
969 | // TODO: Call SimplifyDemandedBits for non-constant demanded elements. | ||||||
970 | Known = TLO.DAG.computeKnownBits(Op, DemandedElts, Depth); | ||||||
971 | return false; // Don't fall through, will infinitely loop. | ||||||
972 | case ISD::LOAD: { | ||||||
973 | LoadSDNode *LD = cast<LoadSDNode>(Op); | ||||||
974 | if (getTargetConstantFromLoad(LD)) { | ||||||
975 | Known = TLO.DAG.computeKnownBits(Op, DemandedElts, Depth); | ||||||
976 | return false; // Don't fall through, will infinitely loop. | ||||||
977 | } else if (ISD::isZEXTLoad(Op.getNode()) && Op.getResNo() == 0) { | ||||||
978 | // If this is a ZEXTLoad and we are looking at the loaded value. | ||||||
979 | EVT MemVT = LD->getMemoryVT(); | ||||||
980 | unsigned MemBits = MemVT.getScalarSizeInBits(); | ||||||
981 | Known.Zero.setBitsFrom(MemBits); | ||||||
982 | return false; // Don't fall through, will infinitely loop. | ||||||
983 | } | ||||||
984 | break; | ||||||
985 | } | ||||||
986 | case ISD::INSERT_VECTOR_ELT: { | ||||||
987 | SDValue Vec = Op.getOperand(0); | ||||||
988 | SDValue Scl = Op.getOperand(1); | ||||||
989 | auto *CIdx = dyn_cast<ConstantSDNode>(Op.getOperand(2)); | ||||||
990 | EVT VecVT = Vec.getValueType(); | ||||||
991 | |||||||
992 | // If index isn't constant, assume we need all vector elements AND the | ||||||
993 | // inserted element. | ||||||
994 | APInt DemandedVecElts(DemandedElts); | ||||||
995 | if (CIdx && CIdx->getAPIntValue().ult(VecVT.getVectorNumElements())) { | ||||||
996 | unsigned Idx = CIdx->getZExtValue(); | ||||||
997 | DemandedVecElts.clearBit(Idx); | ||||||
998 | |||||||
999 | // Inserted element is not required. | ||||||
1000 | if (!DemandedElts[Idx]) | ||||||
1001 | return TLO.CombineTo(Op, Vec); | ||||||
1002 | } | ||||||
1003 | |||||||
1004 | KnownBits KnownScl; | ||||||
1005 | unsigned NumSclBits = Scl.getScalarValueSizeInBits(); | ||||||
1006 | APInt DemandedSclBits = DemandedBits.zextOrTrunc(NumSclBits); | ||||||
1007 | if (SimplifyDemandedBits(Scl, DemandedSclBits, KnownScl, TLO, Depth + 1)) | ||||||
1008 | return true; | ||||||
1009 | |||||||
1010 | Known = KnownScl.anyextOrTrunc(BitWidth); | ||||||
1011 | |||||||
1012 | KnownBits KnownVec; | ||||||
1013 | if (SimplifyDemandedBits(Vec, DemandedBits, DemandedVecElts, KnownVec, TLO, | ||||||
1014 | Depth + 1)) | ||||||
1015 | return true; | ||||||
1016 | |||||||
1017 | if (!!DemandedVecElts) | ||||||
1018 | Known = KnownBits::commonBits(Known, KnownVec); | ||||||
1019 | |||||||
1020 | return false; | ||||||
1021 | } | ||||||
1022 | case ISD::INSERT_SUBVECTOR: { | ||||||
1023 | // Demand any elements from the subvector and the remainder from the src its | ||||||
1024 | // inserted into. | ||||||
1025 | SDValue Src = Op.getOperand(0); | ||||||
1026 | SDValue Sub = Op.getOperand(1); | ||||||
1027 | uint64_t Idx = Op.getConstantOperandVal(2); | ||||||
1028 | unsigned NumSubElts = Sub.getValueType().getVectorNumElements(); | ||||||
1029 | APInt DemandedSubElts = DemandedElts.extractBits(NumSubElts, Idx); | ||||||
1030 | APInt DemandedSrcElts = DemandedElts; | ||||||
1031 | DemandedSrcElts.insertBits(APInt::getNullValue(NumSubElts), Idx); | ||||||
1032 | |||||||
1033 | KnownBits KnownSub, KnownSrc; | ||||||
1034 | if (SimplifyDemandedBits(Sub, DemandedBits, DemandedSubElts, KnownSub, TLO, | ||||||
1035 | Depth + 1)) | ||||||
1036 | return true; | ||||||
1037 | if (SimplifyDemandedBits(Src, DemandedBits, DemandedSrcElts, KnownSrc, TLO, | ||||||
1038 | Depth + 1)) | ||||||
1039 | return true; | ||||||
1040 | |||||||
1041 | Known.Zero.setAllBits(); | ||||||
1042 | Known.One.setAllBits(); | ||||||
1043 | if (!!DemandedSubElts) | ||||||
1044 | Known = KnownBits::commonBits(Known, KnownSub); | ||||||
1045 | if (!!DemandedSrcElts) | ||||||
1046 | Known = KnownBits::commonBits(Known, KnownSrc); | ||||||
1047 | |||||||
1048 | // Attempt to avoid multi-use src if we don't need anything from it. | ||||||
1049 | if (!DemandedBits.isAllOnesValue() || !DemandedSubElts.isAllOnesValue() || | ||||||
1050 | !DemandedSrcElts.isAllOnesValue()) { | ||||||
1051 | SDValue NewSub = SimplifyMultipleUseDemandedBits( | ||||||
1052 | Sub, DemandedBits, DemandedSubElts, TLO.DAG, Depth + 1); | ||||||
1053 | SDValue NewSrc = SimplifyMultipleUseDemandedBits( | ||||||
1054 | Src, DemandedBits, DemandedSrcElts, TLO.DAG, Depth + 1); | ||||||
1055 | if (NewSub || NewSrc) { | ||||||
1056 | NewSub = NewSub ? NewSub : Sub; | ||||||
1057 | NewSrc = NewSrc ? NewSrc : Src; | ||||||
1058 | SDValue NewOp = TLO.DAG.getNode(Op.getOpcode(), dl, VT, NewSrc, NewSub, | ||||||
1059 | Op.getOperand(2)); | ||||||
1060 | return TLO.CombineTo(Op, NewOp); | ||||||
1061 | } | ||||||
1062 | } | ||||||
1063 | break; | ||||||
1064 | } | ||||||
1065 | case ISD::EXTRACT_SUBVECTOR: { | ||||||
1066 | // Offset the demanded elts by the subvector index. | ||||||
1067 | SDValue Src = Op.getOperand(0); | ||||||
1068 | if (Src.getValueType().isScalableVector()) | ||||||
1069 | break; | ||||||
1070 | uint64_t Idx = Op.getConstantOperandVal(1); | ||||||
1071 | unsigned NumSrcElts = Src.getValueType().getVectorNumElements(); | ||||||
1072 | APInt DemandedSrcElts = DemandedElts.zextOrSelf(NumSrcElts).shl(Idx); | ||||||
1073 | |||||||
1074 | if (SimplifyDemandedBits(Src, DemandedBits, DemandedSrcElts, Known, TLO, | ||||||
1075 | Depth + 1)) | ||||||
1076 | return true; | ||||||
1077 | |||||||
1078 | // Attempt to avoid multi-use src if we don't need anything from it. | ||||||
1079 | if (!DemandedBits.isAllOnesValue() || !DemandedSrcElts.isAllOnesValue()) { | ||||||
1080 | SDValue DemandedSrc = SimplifyMultipleUseDemandedBits( | ||||||
1081 | Src, DemandedBits, DemandedSrcElts, TLO.DAG, Depth + 1); | ||||||
1082 | if (DemandedSrc) { | ||||||
1083 | SDValue NewOp = TLO.DAG.getNode(Op.getOpcode(), dl, VT, DemandedSrc, | ||||||
1084 | Op.getOperand(1)); | ||||||
1085 | return TLO.CombineTo(Op, NewOp); | ||||||
1086 | } | ||||||
1087 | } | ||||||
1088 | break; | ||||||
1089 | } | ||||||
1090 | case ISD::CONCAT_VECTORS: { | ||||||
1091 | Known.Zero.setAllBits(); | ||||||
1092 | Known.One.setAllBits(); | ||||||
1093 | EVT SubVT = Op.getOperand(0).getValueType(); | ||||||
1094 | unsigned NumSubVecs = Op.getNumOperands(); | ||||||
1095 | unsigned NumSubElts = SubVT.getVectorNumElements(); | ||||||
1096 | for (unsigned i = 0; i != NumSubVecs; ++i) { | ||||||
1097 | APInt DemandedSubElts = | ||||||
1098 | DemandedElts.extractBits(NumSubElts, i * NumSubElts); | ||||||
1099 | if (SimplifyDemandedBits(Op.getOperand(i), DemandedBits, DemandedSubElts, | ||||||
1100 | Known2, TLO, Depth + 1)) | ||||||
1101 | return true; | ||||||
1102 | // Known bits are shared by every demanded subvector element. | ||||||
1103 | if (!!DemandedSubElts) | ||||||
1104 | Known = KnownBits::commonBits(Known, Known2); | ||||||
1105 | } | ||||||
1106 | break; | ||||||
1107 | } | ||||||
1108 | case ISD::VECTOR_SHUFFLE: { | ||||||
1109 | ArrayRef<int> ShuffleMask = cast<ShuffleVectorSDNode>(Op)->getMask(); | ||||||
1110 | |||||||
1111 | // Collect demanded elements from shuffle operands.. | ||||||
1112 | APInt DemandedLHS(NumElts, 0); | ||||||
1113 | APInt DemandedRHS(NumElts, 0); | ||||||
1114 | for (unsigned i = 0; i != NumElts; ++i) { | ||||||
1115 | if (!DemandedElts[i]) | ||||||
1116 | continue; | ||||||
1117 | int M = ShuffleMask[i]; | ||||||
1118 | if (M < 0) { | ||||||
1119 | // For UNDEF elements, we don't know anything about the common state of | ||||||
1120 | // the shuffle result. | ||||||
1121 | DemandedLHS.clearAllBits(); | ||||||
1122 | DemandedRHS.clearAllBits(); | ||||||
1123 | break; | ||||||
1124 | } | ||||||
1125 | assert(0 <= M && M < (int)(2 * NumElts) && "Shuffle index out of range")((0 <= M && M < (int)(2 * NumElts) && "Shuffle index out of range" ) ? static_cast<void> (0) : __assert_fail ("0 <= M && M < (int)(2 * NumElts) && \"Shuffle index out of range\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 1125, __PRETTY_FUNCTION__)); | ||||||
1126 | if (M < (int)NumElts) | ||||||
1127 | DemandedLHS.setBit(M); | ||||||
1128 | else | ||||||
1129 | DemandedRHS.setBit(M - NumElts); | ||||||
1130 | } | ||||||
1131 | |||||||
1132 | if (!!DemandedLHS || !!DemandedRHS) { | ||||||
1133 | SDValue Op0 = Op.getOperand(0); | ||||||
1134 | SDValue Op1 = Op.getOperand(1); | ||||||
1135 | |||||||
1136 | Known.Zero.setAllBits(); | ||||||
1137 | Known.One.setAllBits(); | ||||||
1138 | if (!!DemandedLHS) { | ||||||
1139 | if (SimplifyDemandedBits(Op0, DemandedBits, DemandedLHS, Known2, TLO, | ||||||
1140 | Depth + 1)) | ||||||
1141 | return true; | ||||||
1142 | Known = KnownBits::commonBits(Known, Known2); | ||||||
1143 | } | ||||||
1144 | if (!!DemandedRHS) { | ||||||
1145 | if (SimplifyDemandedBits(Op1, DemandedBits, DemandedRHS, Known2, TLO, | ||||||
1146 | Depth + 1)) | ||||||
1147 | return true; | ||||||
1148 | Known = KnownBits::commonBits(Known, Known2); | ||||||
1149 | } | ||||||
1150 | |||||||
1151 | // Attempt to avoid multi-use ops if we don't need anything from them. | ||||||
1152 | SDValue DemandedOp0 = SimplifyMultipleUseDemandedBits( | ||||||
1153 | Op0, DemandedBits, DemandedLHS, TLO.DAG, Depth + 1); | ||||||
1154 | SDValue DemandedOp1 = SimplifyMultipleUseDemandedBits( | ||||||
1155 | Op1, DemandedBits, DemandedRHS, TLO.DAG, Depth + 1); | ||||||
1156 | if (DemandedOp0 || DemandedOp1) { | ||||||
1157 | Op0 = DemandedOp0 ? DemandedOp0 : Op0; | ||||||
1158 | Op1 = DemandedOp1 ? DemandedOp1 : Op1; | ||||||
1159 | SDValue NewOp = TLO.DAG.getVectorShuffle(VT, dl, Op0, Op1, ShuffleMask); | ||||||
1160 | return TLO.CombineTo(Op, NewOp); | ||||||
1161 | } | ||||||
1162 | } | ||||||
1163 | break; | ||||||
1164 | } | ||||||
1165 | case ISD::AND: { | ||||||
1166 | SDValue Op0 = Op.getOperand(0); | ||||||
1167 | SDValue Op1 = Op.getOperand(1); | ||||||
1168 | |||||||
1169 | // If the RHS is a constant, check to see if the LHS would be zero without | ||||||
1170 | // using the bits from the RHS. Below, we use knowledge about the RHS to | ||||||
1171 | // simplify the LHS, here we're using information from the LHS to simplify | ||||||
1172 | // the RHS. | ||||||
1173 | if (ConstantSDNode *RHSC = isConstOrConstSplat(Op1)) { | ||||||
1174 | // Do not increment Depth here; that can cause an infinite loop. | ||||||
1175 | KnownBits LHSKnown = TLO.DAG.computeKnownBits(Op0, DemandedElts, Depth); | ||||||
1176 | // If the LHS already has zeros where RHSC does, this 'and' is dead. | ||||||
1177 | if ((LHSKnown.Zero & DemandedBits) == | ||||||
1178 | (~RHSC->getAPIntValue() & DemandedBits)) | ||||||
1179 | return TLO.CombineTo(Op, Op0); | ||||||
1180 | |||||||
1181 | // If any of the set bits in the RHS are known zero on the LHS, shrink | ||||||
1182 | // the constant. | ||||||
1183 | if (ShrinkDemandedConstant(Op, ~LHSKnown.Zero & DemandedBits, | ||||||
1184 | DemandedElts, TLO)) | ||||||
1185 | return true; | ||||||
1186 | |||||||
1187 | // Bitwise-not (xor X, -1) is a special case: we don't usually shrink its | ||||||
1188 | // constant, but if this 'and' is only clearing bits that were just set by | ||||||
1189 | // the xor, then this 'and' can be eliminated by shrinking the mask of | ||||||
1190 | // the xor. For example, for a 32-bit X: | ||||||
1191 | // and (xor (srl X, 31), -1), 1 --> xor (srl X, 31), 1 | ||||||
1192 | if (isBitwiseNot(Op0) && Op0.hasOneUse() && | ||||||
1193 | LHSKnown.One == ~RHSC->getAPIntValue()) { | ||||||
1194 | SDValue Xor = TLO.DAG.getNode(ISD::XOR, dl, VT, Op0.getOperand(0), Op1); | ||||||
1195 | return TLO.CombineTo(Op, Xor); | ||||||
1196 | } | ||||||
1197 | } | ||||||
1198 | |||||||
1199 | if (SimplifyDemandedBits(Op1, DemandedBits, DemandedElts, Known, TLO, | ||||||
1200 | Depth + 1)) | ||||||
1201 | return true; | ||||||
1202 | assert(!Known.hasConflict() && "Bits known to be one AND zero?")((!Known.hasConflict() && "Bits known to be one AND zero?" ) ? static_cast<void> (0) : __assert_fail ("!Known.hasConflict() && \"Bits known to be one AND zero?\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 1202, __PRETTY_FUNCTION__)); | ||||||
1203 | if (SimplifyDemandedBits(Op0, ~Known.Zero & DemandedBits, DemandedElts, | ||||||
1204 | Known2, TLO, Depth + 1)) | ||||||
1205 | return true; | ||||||
1206 | assert(!Known2.hasConflict() && "Bits known to be one AND zero?")((!Known2.hasConflict() && "Bits known to be one AND zero?" ) ? static_cast<void> (0) : __assert_fail ("!Known2.hasConflict() && \"Bits known to be one AND zero?\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 1206, __PRETTY_FUNCTION__)); | ||||||
1207 | |||||||
1208 | // Attempt to avoid multi-use ops if we don't need anything from them. | ||||||
1209 | if (!DemandedBits.isAllOnesValue() || !DemandedElts.isAllOnesValue()) { | ||||||
1210 | SDValue DemandedOp0 = SimplifyMultipleUseDemandedBits( | ||||||
1211 | Op0, DemandedBits, DemandedElts, TLO.DAG, Depth + 1); | ||||||
1212 | SDValue DemandedOp1 = SimplifyMultipleUseDemandedBits( | ||||||
1213 | Op1, DemandedBits, DemandedElts, TLO.DAG, Depth + 1); | ||||||
1214 | if (DemandedOp0 || DemandedOp1) { | ||||||
1215 | Op0 = DemandedOp0 ? DemandedOp0 : Op0; | ||||||
1216 | Op1 = DemandedOp1 ? DemandedOp1 : Op1; | ||||||
1217 | SDValue NewOp = TLO.DAG.getNode(Op.getOpcode(), dl, VT, Op0, Op1); | ||||||
1218 | return TLO.CombineTo(Op, NewOp); | ||||||
1219 | } | ||||||
1220 | } | ||||||
1221 | |||||||
1222 | // If all of the demanded bits are known one on one side, return the other. | ||||||
1223 | // These bits cannot contribute to the result of the 'and'. | ||||||
1224 | if (DemandedBits.isSubsetOf(Known2.Zero | Known.One)) | ||||||
1225 | return TLO.CombineTo(Op, Op0); | ||||||
1226 | if (DemandedBits.isSubsetOf(Known.Zero | Known2.One)) | ||||||
1227 | return TLO.CombineTo(Op, Op1); | ||||||
1228 | // If all of the demanded bits in the inputs are known zeros, return zero. | ||||||
1229 | if (DemandedBits.isSubsetOf(Known.Zero | Known2.Zero)) | ||||||
1230 | return TLO.CombineTo(Op, TLO.DAG.getConstant(0, dl, VT)); | ||||||
1231 | // If the RHS is a constant, see if we can simplify it. | ||||||
1232 | if (ShrinkDemandedConstant(Op, ~Known2.Zero & DemandedBits, DemandedElts, | ||||||
1233 | TLO)) | ||||||
1234 | return true; | ||||||
1235 | // If the operation can be done in a smaller type, do so. | ||||||
1236 | if (ShrinkDemandedOp(Op, BitWidth, DemandedBits, TLO)) | ||||||
1237 | return true; | ||||||
1238 | |||||||
1239 | Known &= Known2; | ||||||
1240 | break; | ||||||
1241 | } | ||||||
1242 | case ISD::OR: { | ||||||
1243 | SDValue Op0 = Op.getOperand(0); | ||||||
1244 | SDValue Op1 = Op.getOperand(1); | ||||||
1245 | |||||||
1246 | if (SimplifyDemandedBits(Op1, DemandedBits, DemandedElts, Known, TLO, | ||||||
1247 | Depth + 1)) | ||||||
1248 | return true; | ||||||
1249 | assert(!Known.hasConflict() && "Bits known to be one AND zero?")((!Known.hasConflict() && "Bits known to be one AND zero?" ) ? static_cast<void> (0) : __assert_fail ("!Known.hasConflict() && \"Bits known to be one AND zero?\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 1249, __PRETTY_FUNCTION__)); | ||||||
1250 | if (SimplifyDemandedBits(Op0, ~Known.One & DemandedBits, DemandedElts, | ||||||
1251 | Known2, TLO, Depth + 1)) | ||||||
1252 | return true; | ||||||
1253 | assert(!Known2.hasConflict() && "Bits known to be one AND zero?")((!Known2.hasConflict() && "Bits known to be one AND zero?" ) ? static_cast<void> (0) : __assert_fail ("!Known2.hasConflict() && \"Bits known to be one AND zero?\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 1253, __PRETTY_FUNCTION__)); | ||||||
1254 | |||||||
1255 | // Attempt to avoid multi-use ops if we don't need anything from them. | ||||||
1256 | if (!DemandedBits.isAllOnesValue() || !DemandedElts.isAllOnesValue()) { | ||||||
1257 | SDValue DemandedOp0 = SimplifyMultipleUseDemandedBits( | ||||||
1258 | Op0, DemandedBits, DemandedElts, TLO.DAG, Depth + 1); | ||||||
1259 | SDValue DemandedOp1 = SimplifyMultipleUseDemandedBits( | ||||||
1260 | Op1, DemandedBits, DemandedElts, TLO.DAG, Depth + 1); | ||||||
1261 | if (DemandedOp0 || DemandedOp1) { | ||||||
1262 | Op0 = DemandedOp0 ? DemandedOp0 : Op0; | ||||||
1263 | Op1 = DemandedOp1 ? DemandedOp1 : Op1; | ||||||
1264 | SDValue NewOp = TLO.DAG.getNode(Op.getOpcode(), dl, VT, Op0, Op1); | ||||||
1265 | return TLO.CombineTo(Op, NewOp); | ||||||
1266 | } | ||||||
1267 | } | ||||||
1268 | |||||||
1269 | // If all of the demanded bits are known zero on one side, return the other. | ||||||
1270 | // These bits cannot contribute to the result of the 'or'. | ||||||
1271 | if (DemandedBits.isSubsetOf(Known2.One | Known.Zero)) | ||||||
1272 | return TLO.CombineTo(Op, Op0); | ||||||
1273 | if (DemandedBits.isSubsetOf(Known.One | Known2.Zero)) | ||||||
1274 | return TLO.CombineTo(Op, Op1); | ||||||
1275 | // If the RHS is a constant, see if we can simplify it. | ||||||
1276 | if (ShrinkDemandedConstant(Op, DemandedBits, DemandedElts, TLO)) | ||||||
1277 | return true; | ||||||
1278 | // If the operation can be done in a smaller type, do so. | ||||||
1279 | if (ShrinkDemandedOp(Op, BitWidth, DemandedBits, TLO)) | ||||||
1280 | return true; | ||||||
1281 | |||||||
1282 | Known |= Known2; | ||||||
1283 | break; | ||||||
1284 | } | ||||||
1285 | case ISD::XOR: { | ||||||
1286 | SDValue Op0 = Op.getOperand(0); | ||||||
1287 | SDValue Op1 = Op.getOperand(1); | ||||||
1288 | |||||||
1289 | if (SimplifyDemandedBits(Op1, DemandedBits, DemandedElts, Known, TLO, | ||||||
1290 | Depth + 1)) | ||||||
1291 | return true; | ||||||
1292 | assert(!Known.hasConflict() && "Bits known to be one AND zero?")((!Known.hasConflict() && "Bits known to be one AND zero?" ) ? static_cast<void> (0) : __assert_fail ("!Known.hasConflict() && \"Bits known to be one AND zero?\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 1292, __PRETTY_FUNCTION__)); | ||||||
1293 | if (SimplifyDemandedBits(Op0, DemandedBits, DemandedElts, Known2, TLO, | ||||||
1294 | Depth + 1)) | ||||||
1295 | return true; | ||||||
1296 | assert(!Known2.hasConflict() && "Bits known to be one AND zero?")((!Known2.hasConflict() && "Bits known to be one AND zero?" ) ? static_cast<void> (0) : __assert_fail ("!Known2.hasConflict() && \"Bits known to be one AND zero?\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 1296, __PRETTY_FUNCTION__)); | ||||||
1297 | |||||||
1298 | // Attempt to avoid multi-use ops if we don't need anything from them. | ||||||
1299 | if (!DemandedBits.isAllOnesValue() || !DemandedElts.isAllOnesValue()) { | ||||||
1300 | SDValue DemandedOp0 = SimplifyMultipleUseDemandedBits( | ||||||
1301 | Op0, DemandedBits, DemandedElts, TLO.DAG, Depth + 1); | ||||||
1302 | SDValue DemandedOp1 = SimplifyMultipleUseDemandedBits( | ||||||
1303 | Op1, DemandedBits, DemandedElts, TLO.DAG, Depth + 1); | ||||||
1304 | if (DemandedOp0 || DemandedOp1) { | ||||||
1305 | Op0 = DemandedOp0 ? DemandedOp0 : Op0; | ||||||
1306 | Op1 = DemandedOp1 ? DemandedOp1 : Op1; | ||||||
1307 | SDValue NewOp = TLO.DAG.getNode(Op.getOpcode(), dl, VT, Op0, Op1); | ||||||
1308 | return TLO.CombineTo(Op, NewOp); | ||||||
1309 | } | ||||||
1310 | } | ||||||
1311 | |||||||
1312 | // If all of the demanded bits are known zero on one side, return the other. | ||||||
1313 | // These bits cannot contribute to the result of the 'xor'. | ||||||
1314 | if (DemandedBits.isSubsetOf(Known.Zero)) | ||||||
1315 | return TLO.CombineTo(Op, Op0); | ||||||
1316 | if (DemandedBits.isSubsetOf(Known2.Zero)) | ||||||
1317 | return TLO.CombineTo(Op, Op1); | ||||||
1318 | // If the operation can be done in a smaller type, do so. | ||||||
1319 | if (ShrinkDemandedOp(Op, BitWidth, DemandedBits, TLO)) | ||||||
1320 | return true; | ||||||
1321 | |||||||
1322 | // If all of the unknown bits are known to be zero on one side or the other | ||||||
1323 | // turn this into an *inclusive* or. | ||||||
1324 | // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0 | ||||||
1325 | if (DemandedBits.isSubsetOf(Known.Zero | Known2.Zero)) | ||||||
1326 | return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, VT, Op0, Op1)); | ||||||
1327 | |||||||
1328 | ConstantSDNode* C = isConstOrConstSplat(Op1, DemandedElts); | ||||||
1329 | if (C) { | ||||||
1330 | // If one side is a constant, and all of the set bits in the constant are | ||||||
1331 | // also known set on the other side, turn this into an AND, as we know | ||||||
1332 | // the bits will be cleared. | ||||||
1333 | // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2 | ||||||
1334 | // NB: it is okay if more bits are known than are requested | ||||||
1335 | if (C->getAPIntValue() == Known2.One) { | ||||||
1336 | SDValue ANDC = | ||||||
1337 | TLO.DAG.getConstant(~C->getAPIntValue() & DemandedBits, dl, VT); | ||||||
1338 | return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT, Op0, ANDC)); | ||||||
1339 | } | ||||||
1340 | |||||||
1341 | // If the RHS is a constant, see if we can change it. Don't alter a -1 | ||||||
1342 | // constant because that's a 'not' op, and that is better for combining | ||||||
1343 | // and codegen. | ||||||
1344 | if (!C->isAllOnesValue() && | ||||||
1345 | DemandedBits.isSubsetOf(C->getAPIntValue())) { | ||||||
1346 | // We're flipping all demanded bits. Flip the undemanded bits too. | ||||||
1347 | SDValue New = TLO.DAG.getNOT(dl, Op0, VT); | ||||||
1348 | return TLO.CombineTo(Op, New); | ||||||
1349 | } | ||||||
1350 | } | ||||||
1351 | |||||||
1352 | // If we can't turn this into a 'not', try to shrink the constant. | ||||||
1353 | if (!C || !C->isAllOnesValue()) | ||||||
1354 | if (ShrinkDemandedConstant(Op, DemandedBits, DemandedElts, TLO)) | ||||||
1355 | return true; | ||||||
1356 | |||||||
1357 | Known ^= Known2; | ||||||
1358 | break; | ||||||
1359 | } | ||||||
1360 | case ISD::SELECT: | ||||||
1361 | if (SimplifyDemandedBits(Op.getOperand(2), DemandedBits, Known, TLO, | ||||||
1362 | Depth + 1)) | ||||||
1363 | return true; | ||||||
1364 | if (SimplifyDemandedBits(Op.getOperand(1), DemandedBits, Known2, TLO, | ||||||
1365 | Depth + 1)) | ||||||
1366 | return true; | ||||||
1367 | assert(!Known.hasConflict() && "Bits known to be one AND zero?")((!Known.hasConflict() && "Bits known to be one AND zero?" ) ? static_cast<void> (0) : __assert_fail ("!Known.hasConflict() && \"Bits known to be one AND zero?\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 1367, __PRETTY_FUNCTION__)); | ||||||
1368 | assert(!Known2.hasConflict() && "Bits known to be one AND zero?")((!Known2.hasConflict() && "Bits known to be one AND zero?" ) ? static_cast<void> (0) : __assert_fail ("!Known2.hasConflict() && \"Bits known to be one AND zero?\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 1368, __PRETTY_FUNCTION__)); | ||||||
1369 | |||||||
1370 | // If the operands are constants, see if we can simplify them. | ||||||
1371 | if (ShrinkDemandedConstant(Op, DemandedBits, DemandedElts, TLO)) | ||||||
1372 | return true; | ||||||
1373 | |||||||
1374 | // Only known if known in both the LHS and RHS. | ||||||
1375 | Known = KnownBits::commonBits(Known, Known2); | ||||||
1376 | break; | ||||||
1377 | case ISD::SELECT_CC: | ||||||
1378 | if (SimplifyDemandedBits(Op.getOperand(3), DemandedBits, Known, TLO, | ||||||
1379 | Depth + 1)) | ||||||
1380 | return true; | ||||||
1381 | if (SimplifyDemandedBits(Op.getOperand(2), DemandedBits, Known2, TLO, | ||||||
1382 | Depth + 1)) | ||||||
1383 | return true; | ||||||
1384 | assert(!Known.hasConflict() && "Bits known to be one AND zero?")((!Known.hasConflict() && "Bits known to be one AND zero?" ) ? static_cast<void> (0) : __assert_fail ("!Known.hasConflict() && \"Bits known to be one AND zero?\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 1384, __PRETTY_FUNCTION__)); | ||||||
1385 | assert(!Known2.hasConflict() && "Bits known to be one AND zero?")((!Known2.hasConflict() && "Bits known to be one AND zero?" ) ? static_cast<void> (0) : __assert_fail ("!Known2.hasConflict() && \"Bits known to be one AND zero?\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 1385, __PRETTY_FUNCTION__)); | ||||||
1386 | |||||||
1387 | // If the operands are constants, see if we can simplify them. | ||||||
1388 | if (ShrinkDemandedConstant(Op, DemandedBits, DemandedElts, TLO)) | ||||||
1389 | return true; | ||||||
1390 | |||||||
1391 | // Only known if known in both the LHS and RHS. | ||||||
1392 | Known = KnownBits::commonBits(Known, Known2); | ||||||
1393 | break; | ||||||
1394 | case ISD::SETCC: { | ||||||
1395 | SDValue Op0 = Op.getOperand(0); | ||||||
1396 | SDValue Op1 = Op.getOperand(1); | ||||||
1397 | ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); | ||||||
1398 | // If (1) we only need the sign-bit, (2) the setcc operands are the same | ||||||
1399 | // width as the setcc result, and (3) the result of a setcc conforms to 0 or | ||||||
1400 | // -1, we may be able to bypass the setcc. | ||||||
1401 | if (DemandedBits.isSignMask() && | ||||||
1402 | Op0.getScalarValueSizeInBits() == BitWidth && | ||||||
1403 | getBooleanContents(Op0.getValueType()) == | ||||||
1404 | BooleanContent::ZeroOrNegativeOneBooleanContent) { | ||||||
1405 | // If we're testing X < 0, then this compare isn't needed - just use X! | ||||||
1406 | // FIXME: We're limiting to integer types here, but this should also work | ||||||
1407 | // if we don't care about FP signed-zero. The use of SETLT with FP means | ||||||
1408 | // that we don't care about NaNs. | ||||||
1409 | if (CC == ISD::SETLT && Op1.getValueType().isInteger() && | ||||||
1410 | (isNullConstant(Op1) || ISD::isBuildVectorAllZeros(Op1.getNode()))) | ||||||
1411 | return TLO.CombineTo(Op, Op0); | ||||||
1412 | |||||||
1413 | // TODO: Should we check for other forms of sign-bit comparisons? | ||||||
1414 | // Examples: X <= -1, X >= 0 | ||||||
1415 | } | ||||||
1416 | if (getBooleanContents(Op0.getValueType()) == | ||||||
1417 | TargetLowering::ZeroOrOneBooleanContent && | ||||||
1418 | BitWidth > 1) | ||||||
1419 | Known.Zero.setBitsFrom(1); | ||||||
1420 | break; | ||||||
1421 | } | ||||||
1422 | case ISD::SHL: { | ||||||
1423 | SDValue Op0 = Op.getOperand(0); | ||||||
1424 | SDValue Op1 = Op.getOperand(1); | ||||||
1425 | EVT ShiftVT = Op1.getValueType(); | ||||||
1426 | |||||||
1427 | if (const APInt *SA = | ||||||
1428 | TLO.DAG.getValidShiftAmountConstant(Op, DemandedElts)) { | ||||||
1429 | unsigned ShAmt = SA->getZExtValue(); | ||||||
1430 | if (ShAmt == 0) | ||||||
1431 | return TLO.CombineTo(Op, Op0); | ||||||
1432 | |||||||
1433 | // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a | ||||||
1434 | // single shift. We can do this if the bottom bits (which are shifted | ||||||
1435 | // out) are never demanded. | ||||||
1436 | // TODO - support non-uniform vector amounts. | ||||||
1437 | if (Op0.getOpcode() == ISD::SRL) { | ||||||
1438 | if (!DemandedBits.intersects(APInt::getLowBitsSet(BitWidth, ShAmt))) { | ||||||
1439 | if (const APInt *SA2 = | ||||||
1440 | TLO.DAG.getValidShiftAmountConstant(Op0, DemandedElts)) { | ||||||
1441 | unsigned C1 = SA2->getZExtValue(); | ||||||
1442 | unsigned Opc = ISD::SHL; | ||||||
1443 | int Diff = ShAmt - C1; | ||||||
1444 | if (Diff < 0) { | ||||||
1445 | Diff = -Diff; | ||||||
1446 | Opc = ISD::SRL; | ||||||
1447 | } | ||||||
1448 | SDValue NewSA = TLO.DAG.getConstant(Diff, dl, ShiftVT); | ||||||
1449 | return TLO.CombineTo( | ||||||
1450 | Op, TLO.DAG.getNode(Opc, dl, VT, Op0.getOperand(0), NewSA)); | ||||||
1451 | } | ||||||
1452 | } | ||||||
1453 | } | ||||||
1454 | |||||||
1455 | // Convert (shl (anyext x, c)) to (anyext (shl x, c)) if the high bits | ||||||
1456 | // are not demanded. This will likely allow the anyext to be folded away. | ||||||
1457 | // TODO - support non-uniform vector amounts. | ||||||
1458 | if (Op0.getOpcode() == ISD::ANY_EXTEND) { | ||||||
1459 | SDValue InnerOp = Op0.getOperand(0); | ||||||
1460 | EVT InnerVT = InnerOp.getValueType(); | ||||||
1461 | unsigned InnerBits = InnerVT.getScalarSizeInBits(); | ||||||
1462 | if (ShAmt < InnerBits && DemandedBits.getActiveBits() <= InnerBits && | ||||||
1463 | isTypeDesirableForOp(ISD::SHL, InnerVT)) { | ||||||
1464 | EVT ShTy = getShiftAmountTy(InnerVT, DL); | ||||||
1465 | if (!APInt(BitWidth, ShAmt).isIntN(ShTy.getSizeInBits())) | ||||||
1466 | ShTy = InnerVT; | ||||||
1467 | SDValue NarrowShl = | ||||||
1468 | TLO.DAG.getNode(ISD::SHL, dl, InnerVT, InnerOp, | ||||||
1469 | TLO.DAG.getConstant(ShAmt, dl, ShTy)); | ||||||
1470 | return TLO.CombineTo( | ||||||
1471 | Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl, VT, NarrowShl)); | ||||||
1472 | } | ||||||
1473 | |||||||
1474 | // Repeat the SHL optimization above in cases where an extension | ||||||
1475 | // intervenes: (shl (anyext (shr x, c1)), c2) to | ||||||
1476 | // (shl (anyext x), c2-c1). This requires that the bottom c1 bits | ||||||
1477 | // aren't demanded (as above) and that the shifted upper c1 bits of | ||||||
1478 | // x aren't demanded. | ||||||
1479 | // TODO - support non-uniform vector amounts. | ||||||
1480 | if (Op0.hasOneUse() && InnerOp.getOpcode() == ISD::SRL && | ||||||
1481 | InnerOp.hasOneUse()) { | ||||||
1482 | if (const APInt *SA2 = | ||||||
1483 | TLO.DAG.getValidShiftAmountConstant(InnerOp, DemandedElts)) { | ||||||
1484 | unsigned InnerShAmt = SA2->getZExtValue(); | ||||||
1485 | if (InnerShAmt < ShAmt && InnerShAmt < InnerBits && | ||||||
1486 | DemandedBits.getActiveBits() <= | ||||||
1487 | (InnerBits - InnerShAmt + ShAmt) && | ||||||
1488 | DemandedBits.countTrailingZeros() >= ShAmt) { | ||||||
1489 | SDValue NewSA = | ||||||
1490 | TLO.DAG.getConstant(ShAmt - InnerShAmt, dl, ShiftVT); | ||||||
1491 | SDValue NewExt = TLO.DAG.getNode(ISD::ANY_EXTEND, dl, VT, | ||||||
1492 | InnerOp.getOperand(0)); | ||||||
1493 | return TLO.CombineTo( | ||||||
1494 | Op, TLO.DAG.getNode(ISD::SHL, dl, VT, NewExt, NewSA)); | ||||||
1495 | } | ||||||
1496 | } | ||||||
1497 | } | ||||||
1498 | } | ||||||
1499 | |||||||
1500 | APInt InDemandedMask = DemandedBits.lshr(ShAmt); | ||||||
1501 | if (SimplifyDemandedBits(Op0, InDemandedMask, DemandedElts, Known, TLO, | ||||||
1502 | Depth + 1)) | ||||||
1503 | return true; | ||||||
1504 | assert(!Known.hasConflict() && "Bits known to be one AND zero?")((!Known.hasConflict() && "Bits known to be one AND zero?" ) ? static_cast<void> (0) : __assert_fail ("!Known.hasConflict() && \"Bits known to be one AND zero?\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 1504, __PRETTY_FUNCTION__)); | ||||||
1505 | Known.Zero <<= ShAmt; | ||||||
1506 | Known.One <<= ShAmt; | ||||||
1507 | // low bits known zero. | ||||||
1508 | Known.Zero.setLowBits(ShAmt); | ||||||
1509 | |||||||
1510 | // Try shrinking the operation as long as the shift amount will still be | ||||||
1511 | // in range. | ||||||
1512 | if ((ShAmt < DemandedBits.getActiveBits()) && | ||||||
1513 | ShrinkDemandedOp(Op, BitWidth, DemandedBits, TLO)) | ||||||
1514 | return true; | ||||||
1515 | } | ||||||
1516 | |||||||
1517 | // If we are only demanding sign bits then we can use the shift source | ||||||
1518 | // directly. | ||||||
1519 | if (const APInt *MaxSA = | ||||||
1520 | TLO.DAG.getValidMaximumShiftAmountConstant(Op, DemandedElts)) { | ||||||
1521 | unsigned ShAmt = MaxSA->getZExtValue(); | ||||||
1522 | unsigned NumSignBits = | ||||||
1523 | TLO.DAG.ComputeNumSignBits(Op0, DemandedElts, Depth + 1); | ||||||
1524 | unsigned UpperDemandedBits = BitWidth - DemandedBits.countTrailingZeros(); | ||||||
1525 | if (NumSignBits > ShAmt && (NumSignBits - ShAmt) >= (UpperDemandedBits)) | ||||||
1526 | return TLO.CombineTo(Op, Op0); | ||||||
1527 | } | ||||||
1528 | break; | ||||||
1529 | } | ||||||
1530 | case ISD::SRL: { | ||||||
1531 | SDValue Op0 = Op.getOperand(0); | ||||||
1532 | SDValue Op1 = Op.getOperand(1); | ||||||
1533 | EVT ShiftVT = Op1.getValueType(); | ||||||
1534 | |||||||
1535 | if (const APInt *SA = | ||||||
1536 | TLO.DAG.getValidShiftAmountConstant(Op, DemandedElts)) { | ||||||
1537 | unsigned ShAmt = SA->getZExtValue(); | ||||||
1538 | if (ShAmt == 0) | ||||||
1539 | return TLO.CombineTo(Op, Op0); | ||||||
1540 | |||||||
1541 | // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a | ||||||
1542 | // single shift. We can do this if the top bits (which are shifted out) | ||||||
1543 | // are never demanded. | ||||||
1544 | // TODO - support non-uniform vector amounts. | ||||||
1545 | if (Op0.getOpcode() == ISD::SHL) { | ||||||
1546 | if (!DemandedBits.intersects(APInt::getHighBitsSet(BitWidth, ShAmt))) { | ||||||
1547 | if (const APInt *SA2 = | ||||||
1548 | TLO.DAG.getValidShiftAmountConstant(Op0, DemandedElts)) { | ||||||
1549 | unsigned C1 = SA2->getZExtValue(); | ||||||
1550 | unsigned Opc = ISD::SRL; | ||||||
1551 | int Diff = ShAmt - C1; | ||||||
1552 | if (Diff < 0) { | ||||||
1553 | Diff = -Diff; | ||||||
1554 | Opc = ISD::SHL; | ||||||
1555 | } | ||||||
1556 | SDValue NewSA = TLO.DAG.getConstant(Diff, dl, ShiftVT); | ||||||
1557 | return TLO.CombineTo( | ||||||
1558 | Op, TLO.DAG.getNode(Opc, dl, VT, Op0.getOperand(0), NewSA)); | ||||||
1559 | } | ||||||
1560 | } | ||||||
1561 | } | ||||||
1562 | |||||||
1563 | APInt InDemandedMask = (DemandedBits << ShAmt); | ||||||
1564 | |||||||
1565 | // If the shift is exact, then it does demand the low bits (and knows that | ||||||
1566 | // they are zero). | ||||||
1567 | if (Op->getFlags().hasExact()) | ||||||
1568 | InDemandedMask.setLowBits(ShAmt); | ||||||
1569 | |||||||
1570 | // Compute the new bits that are at the top now. | ||||||
1571 | if (SimplifyDemandedBits(Op0, InDemandedMask, DemandedElts, Known, TLO, | ||||||
1572 | Depth + 1)) | ||||||
1573 | return true; | ||||||
1574 | assert(!Known.hasConflict() && "Bits known to be one AND zero?")((!Known.hasConflict() && "Bits known to be one AND zero?" ) ? static_cast<void> (0) : __assert_fail ("!Known.hasConflict() && \"Bits known to be one AND zero?\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 1574, __PRETTY_FUNCTION__)); | ||||||
1575 | Known.Zero.lshrInPlace(ShAmt); | ||||||
1576 | Known.One.lshrInPlace(ShAmt); | ||||||
1577 | // High bits known zero. | ||||||
1578 | Known.Zero.setHighBits(ShAmt); | ||||||
1579 | } | ||||||
1580 | break; | ||||||
1581 | } | ||||||
1582 | case ISD::SRA: { | ||||||
1583 | SDValue Op0 = Op.getOperand(0); | ||||||
1584 | SDValue Op1 = Op.getOperand(1); | ||||||
1585 | EVT ShiftVT = Op1.getValueType(); | ||||||
1586 | |||||||
1587 | // If we only want bits that already match the signbit then we don't need | ||||||
1588 | // to shift. | ||||||
1589 | unsigned NumHiDemandedBits = BitWidth - DemandedBits.countTrailingZeros(); | ||||||
1590 | if (TLO.DAG.ComputeNumSignBits(Op0, DemandedElts, Depth + 1) >= | ||||||
1591 | NumHiDemandedBits) | ||||||
1592 | return TLO.CombineTo(Op, Op0); | ||||||
1593 | |||||||
1594 | // If this is an arithmetic shift right and only the low-bit is set, we can | ||||||
1595 | // always convert this into a logical shr, even if the shift amount is | ||||||
1596 | // variable. The low bit of the shift cannot be an input sign bit unless | ||||||
1597 | // the shift amount is >= the size of the datatype, which is undefined. | ||||||
1598 | if (DemandedBits.isOneValue()) | ||||||
1599 | return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT, Op0, Op1)); | ||||||
1600 | |||||||
1601 | if (const APInt *SA = | ||||||
1602 | TLO.DAG.getValidShiftAmountConstant(Op, DemandedElts)) { | ||||||
1603 | unsigned ShAmt = SA->getZExtValue(); | ||||||
1604 | if (ShAmt == 0) | ||||||
1605 | return TLO.CombineTo(Op, Op0); | ||||||
1606 | |||||||
1607 | APInt InDemandedMask = (DemandedBits << ShAmt); | ||||||
1608 | |||||||
1609 | // If the shift is exact, then it does demand the low bits (and knows that | ||||||
1610 | // they are zero). | ||||||
1611 | if (Op->getFlags().hasExact()) | ||||||
1612 | InDemandedMask.setLowBits(ShAmt); | ||||||
1613 | |||||||
1614 | // If any of the demanded bits are produced by the sign extension, we also | ||||||
1615 | // demand the input sign bit. | ||||||
1616 | if (DemandedBits.countLeadingZeros() < ShAmt) | ||||||
1617 | InDemandedMask.setSignBit(); | ||||||
1618 | |||||||
1619 | if (SimplifyDemandedBits(Op0, InDemandedMask, DemandedElts, Known, TLO, | ||||||
1620 | Depth + 1)) | ||||||
1621 | return true; | ||||||
1622 | assert(!Known.hasConflict() && "Bits known to be one AND zero?")((!Known.hasConflict() && "Bits known to be one AND zero?" ) ? static_cast<void> (0) : __assert_fail ("!Known.hasConflict() && \"Bits known to be one AND zero?\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 1622, __PRETTY_FUNCTION__)); | ||||||
1623 | Known.Zero.lshrInPlace(ShAmt); | ||||||
1624 | Known.One.lshrInPlace(ShAmt); | ||||||
1625 | |||||||
1626 | // If the input sign bit is known to be zero, or if none of the top bits | ||||||
1627 | // are demanded, turn this into an unsigned shift right. | ||||||
1628 | if (Known.Zero[BitWidth - ShAmt - 1] || | ||||||
1629 | DemandedBits.countLeadingZeros() >= ShAmt) { | ||||||
1630 | SDNodeFlags Flags; | ||||||
1631 | Flags.setExact(Op->getFlags().hasExact()); | ||||||
1632 | return TLO.CombineTo( | ||||||
1633 | Op, TLO.DAG.getNode(ISD::SRL, dl, VT, Op0, Op1, Flags)); | ||||||
1634 | } | ||||||
1635 | |||||||
1636 | int Log2 = DemandedBits.exactLogBase2(); | ||||||
1637 | if (Log2 >= 0) { | ||||||
1638 | // The bit must come from the sign. | ||||||
1639 | SDValue NewSA = TLO.DAG.getConstant(BitWidth - 1 - Log2, dl, ShiftVT); | ||||||
1640 | return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT, Op0, NewSA)); | ||||||
1641 | } | ||||||
1642 | |||||||
1643 | if (Known.One[BitWidth - ShAmt - 1]) | ||||||
1644 | // New bits are known one. | ||||||
1645 | Known.One.setHighBits(ShAmt); | ||||||
1646 | |||||||
1647 | // Attempt to avoid multi-use ops if we don't need anything from them. | ||||||
1648 | if (!InDemandedMask.isAllOnesValue() || !DemandedElts.isAllOnesValue()) { | ||||||
1649 | SDValue DemandedOp0 = SimplifyMultipleUseDemandedBits( | ||||||
1650 | Op0, InDemandedMask, DemandedElts, TLO.DAG, Depth + 1); | ||||||
1651 | if (DemandedOp0) { | ||||||
1652 | SDValue NewOp = TLO.DAG.getNode(ISD::SRA, dl, VT, DemandedOp0, Op1); | ||||||
1653 | return TLO.CombineTo(Op, NewOp); | ||||||
1654 | } | ||||||
1655 | } | ||||||
1656 | } | ||||||
1657 | break; | ||||||
1658 | } | ||||||
1659 | case ISD::FSHL: | ||||||
1660 | case ISD::FSHR: { | ||||||
1661 | SDValue Op0 = Op.getOperand(0); | ||||||
1662 | SDValue Op1 = Op.getOperand(1); | ||||||
1663 | SDValue Op2 = Op.getOperand(2); | ||||||
1664 | bool IsFSHL = (Op.getOpcode() == ISD::FSHL); | ||||||
1665 | |||||||
1666 | if (ConstantSDNode *SA = isConstOrConstSplat(Op2, DemandedElts)) { | ||||||
1667 | unsigned Amt = SA->getAPIntValue().urem(BitWidth); | ||||||
1668 | |||||||
1669 | // For fshl, 0-shift returns the 1st arg. | ||||||
1670 | // For fshr, 0-shift returns the 2nd arg. | ||||||
1671 | if (Amt == 0) { | ||||||
1672 | if (SimplifyDemandedBits(IsFSHL ? Op0 : Op1, DemandedBits, DemandedElts, | ||||||
1673 | Known, TLO, Depth + 1)) | ||||||
1674 | return true; | ||||||
1675 | break; | ||||||
1676 | } | ||||||
1677 | |||||||
1678 | // fshl: (Op0 << Amt) | (Op1 >> (BW - Amt)) | ||||||
1679 | // fshr: (Op0 << (BW - Amt)) | (Op1 >> Amt) | ||||||
1680 | APInt Demanded0 = DemandedBits.lshr(IsFSHL ? Amt : (BitWidth - Amt)); | ||||||
1681 | APInt Demanded1 = DemandedBits << (IsFSHL ? (BitWidth - Amt) : Amt); | ||||||
1682 | if (SimplifyDemandedBits(Op0, Demanded0, DemandedElts, Known2, TLO, | ||||||
1683 | Depth + 1)) | ||||||
1684 | return true; | ||||||
1685 | if (SimplifyDemandedBits(Op1, Demanded1, DemandedElts, Known, TLO, | ||||||
1686 | Depth + 1)) | ||||||
1687 | return true; | ||||||
1688 | |||||||
1689 | Known2.One <<= (IsFSHL ? Amt : (BitWidth - Amt)); | ||||||
1690 | Known2.Zero <<= (IsFSHL ? Amt : (BitWidth - Amt)); | ||||||
1691 | Known.One.lshrInPlace(IsFSHL ? (BitWidth - Amt) : Amt); | ||||||
1692 | Known.Zero.lshrInPlace(IsFSHL ? (BitWidth - Amt) : Amt); | ||||||
1693 | Known.One |= Known2.One; | ||||||
1694 | Known.Zero |= Known2.Zero; | ||||||
1695 | } | ||||||
1696 | |||||||
1697 | // For pow-2 bitwidths we only demand the bottom modulo amt bits. | ||||||
1698 | if (isPowerOf2_32(BitWidth)) { | ||||||
1699 | APInt DemandedAmtBits(Op2.getScalarValueSizeInBits(), BitWidth - 1); | ||||||
1700 | if (SimplifyDemandedBits(Op2, DemandedAmtBits, DemandedElts, | ||||||
1701 | Known2, TLO, Depth + 1)) | ||||||
1702 | return true; | ||||||
1703 | } | ||||||
1704 | break; | ||||||
1705 | } | ||||||
1706 | case ISD::ROTL: | ||||||
1707 | case ISD::ROTR: { | ||||||
1708 | SDValue Op0 = Op.getOperand(0); | ||||||
1709 | SDValue Op1 = Op.getOperand(1); | ||||||
1710 | |||||||
1711 | // If we're rotating an 0/-1 value, then it stays an 0/-1 value. | ||||||
1712 | if (BitWidth == TLO.DAG.ComputeNumSignBits(Op0, DemandedElts, Depth + 1)) | ||||||
1713 | return TLO.CombineTo(Op, Op0); | ||||||
1714 | |||||||
1715 | // For pow-2 bitwidths we only demand the bottom modulo amt bits. | ||||||
1716 | if (isPowerOf2_32(BitWidth)) { | ||||||
1717 | APInt DemandedAmtBits(Op1.getScalarValueSizeInBits(), BitWidth - 1); | ||||||
1718 | if (SimplifyDemandedBits(Op1, DemandedAmtBits, DemandedElts, Known2, TLO, | ||||||
1719 | Depth + 1)) | ||||||
1720 | return true; | ||||||
1721 | } | ||||||
1722 | break; | ||||||
1723 | } | ||||||
1724 | case ISD::UMIN: { | ||||||
1725 | // Check if one arg is always less than (or equal) to the other arg. | ||||||
1726 | SDValue Op0 = Op.getOperand(0); | ||||||
1727 | SDValue Op1 = Op.getOperand(1); | ||||||
1728 | KnownBits Known0 = TLO.DAG.computeKnownBits(Op0, DemandedElts, Depth + 1); | ||||||
1729 | KnownBits Known1 = TLO.DAG.computeKnownBits(Op1, DemandedElts, Depth + 1); | ||||||
1730 | Known = KnownBits::umin(Known0, Known1); | ||||||
1731 | if (Optional<bool> IsULE = KnownBits::ule(Known0, Known1)) | ||||||
1732 | return TLO.CombineTo(Op, IsULE.getValue() ? Op0 : Op1); | ||||||
1733 | if (Optional<bool> IsULT = KnownBits::ult(Known0, Known1)) | ||||||
1734 | return TLO.CombineTo(Op, IsULT.getValue() ? Op0 : Op1); | ||||||
1735 | break; | ||||||
1736 | } | ||||||
1737 | case ISD::UMAX: { | ||||||
1738 | // Check if one arg is always greater than (or equal) to the other arg. | ||||||
1739 | SDValue Op0 = Op.getOperand(0); | ||||||
1740 | SDValue Op1 = Op.getOperand(1); | ||||||
1741 | KnownBits Known0 = TLO.DAG.computeKnownBits(Op0, DemandedElts, Depth + 1); | ||||||
1742 | KnownBits Known1 = TLO.DAG.computeKnownBits(Op1, DemandedElts, Depth + 1); | ||||||
1743 | Known = KnownBits::umax(Known0, Known1); | ||||||
1744 | if (Optional<bool> IsUGE = KnownBits::uge(Known0, Known1)) | ||||||
1745 | return TLO.CombineTo(Op, IsUGE.getValue() ? Op0 : Op1); | ||||||
1746 | if (Optional<bool> IsUGT = KnownBits::ugt(Known0, Known1)) | ||||||
1747 | return TLO.CombineTo(Op, IsUGT.getValue() ? Op0 : Op1); | ||||||
1748 | break; | ||||||
1749 | } | ||||||
1750 | case ISD::BITREVERSE: { | ||||||
1751 | SDValue Src = Op.getOperand(0); | ||||||
1752 | APInt DemandedSrcBits = DemandedBits.reverseBits(); | ||||||
1753 | if (SimplifyDemandedBits(Src, DemandedSrcBits, DemandedElts, Known2, TLO, | ||||||
1754 | Depth + 1)) | ||||||
1755 | return true; | ||||||
1756 | Known.One = Known2.One.reverseBits(); | ||||||
1757 | Known.Zero = Known2.Zero.reverseBits(); | ||||||
1758 | break; | ||||||
1759 | } | ||||||
1760 | case ISD::BSWAP: { | ||||||
1761 | SDValue Src = Op.getOperand(0); | ||||||
1762 | APInt DemandedSrcBits = DemandedBits.byteSwap(); | ||||||
1763 | if (SimplifyDemandedBits(Src, DemandedSrcBits, DemandedElts, Known2, TLO, | ||||||
1764 | Depth + 1)) | ||||||
1765 | return true; | ||||||
1766 | Known.One = Known2.One.byteSwap(); | ||||||
1767 | Known.Zero = Known2.Zero.byteSwap(); | ||||||
1768 | break; | ||||||
1769 | } | ||||||
1770 | case ISD::CTPOP: { | ||||||
1771 | // If only 1 bit is demanded, replace with PARITY as long as we're before | ||||||
1772 | // op legalization. | ||||||
1773 | // FIXME: Limit to scalars for now. | ||||||
1774 | if (DemandedBits.isOneValue() && !TLO.LegalOps && !VT.isVector()) | ||||||
1775 | return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::PARITY, dl, VT, | ||||||
1776 | Op.getOperand(0))); | ||||||
1777 | |||||||
1778 | Known = TLO.DAG.computeKnownBits(Op, DemandedElts, Depth); | ||||||
1779 | break; | ||||||
1780 | } | ||||||
1781 | case ISD::SIGN_EXTEND_INREG: { | ||||||
1782 | SDValue Op0 = Op.getOperand(0); | ||||||
1783 | EVT ExVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); | ||||||
1784 | unsigned ExVTBits = ExVT.getScalarSizeInBits(); | ||||||
1785 | |||||||
1786 | // If we only care about the highest bit, don't bother shifting right. | ||||||
1787 | if (DemandedBits.isSignMask()) { | ||||||
1788 | unsigned NumSignBits = | ||||||
1789 | TLO.DAG.ComputeNumSignBits(Op0, DemandedElts, Depth + 1); | ||||||
1790 | bool AlreadySignExtended = NumSignBits >= BitWidth - ExVTBits + 1; | ||||||
1791 | // However if the input is already sign extended we expect the sign | ||||||
1792 | // extension to be dropped altogether later and do not simplify. | ||||||
1793 | if (!AlreadySignExtended) { | ||||||
1794 | // Compute the correct shift amount type, which must be getShiftAmountTy | ||||||
1795 | // for scalar types after legalization. | ||||||
1796 | EVT ShiftAmtTy = VT; | ||||||
1797 | if (TLO.LegalTypes() && !ShiftAmtTy.isVector()) | ||||||
1798 | ShiftAmtTy = getShiftAmountTy(ShiftAmtTy, DL); | ||||||
1799 | |||||||
1800 | SDValue ShiftAmt = | ||||||
1801 | TLO.DAG.getConstant(BitWidth - ExVTBits, dl, ShiftAmtTy); | ||||||
1802 | return TLO.CombineTo(Op, | ||||||
1803 | TLO.DAG.getNode(ISD::SHL, dl, VT, Op0, ShiftAmt)); | ||||||
1804 | } | ||||||
1805 | } | ||||||
1806 | |||||||
1807 | // If none of the extended bits are demanded, eliminate the sextinreg. | ||||||
1808 | if (DemandedBits.getActiveBits() <= ExVTBits) | ||||||
1809 | return TLO.CombineTo(Op, Op0); | ||||||
1810 | |||||||
1811 | APInt InputDemandedBits = DemandedBits.getLoBits(ExVTBits); | ||||||
1812 | |||||||
1813 | // Since the sign extended bits are demanded, we know that the sign | ||||||
1814 | // bit is demanded. | ||||||
1815 | InputDemandedBits.setBit(ExVTBits - 1); | ||||||
1816 | |||||||
1817 | if (SimplifyDemandedBits(Op0, InputDemandedBits, Known, TLO, Depth + 1)) | ||||||
1818 | return true; | ||||||
1819 | assert(!Known.hasConflict() && "Bits known to be one AND zero?")((!Known.hasConflict() && "Bits known to be one AND zero?" ) ? static_cast<void> (0) : __assert_fail ("!Known.hasConflict() && \"Bits known to be one AND zero?\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 1819, __PRETTY_FUNCTION__)); | ||||||
1820 | |||||||
1821 | // If the sign bit of the input is known set or clear, then we know the | ||||||
1822 | // top bits of the result. | ||||||
1823 | |||||||
1824 | // If the input sign bit is known zero, convert this into a zero extension. | ||||||
1825 | if (Known.Zero[ExVTBits - 1]) | ||||||
1826 | return TLO.CombineTo(Op, TLO.DAG.getZeroExtendInReg(Op0, dl, ExVT)); | ||||||
1827 | |||||||
1828 | APInt Mask = APInt::getLowBitsSet(BitWidth, ExVTBits); | ||||||
1829 | if (Known.One[ExVTBits - 1]) { // Input sign bit known set | ||||||
1830 | Known.One.setBitsFrom(ExVTBits); | ||||||
1831 | Known.Zero &= Mask; | ||||||
1832 | } else { // Input sign bit unknown | ||||||
1833 | Known.Zero &= Mask; | ||||||
1834 | Known.One &= Mask; | ||||||
1835 | } | ||||||
1836 | break; | ||||||
1837 | } | ||||||
1838 | case ISD::BUILD_PAIR: { | ||||||
1839 | EVT HalfVT = Op.getOperand(0).getValueType(); | ||||||
1840 | unsigned HalfBitWidth = HalfVT.getScalarSizeInBits(); | ||||||
1841 | |||||||
1842 | APInt MaskLo = DemandedBits.getLoBits(HalfBitWidth).trunc(HalfBitWidth); | ||||||
1843 | APInt MaskHi = DemandedBits.getHiBits(HalfBitWidth).trunc(HalfBitWidth); | ||||||
1844 | |||||||
1845 | KnownBits KnownLo, KnownHi; | ||||||
1846 | |||||||
1847 | if (SimplifyDemandedBits(Op.getOperand(0), MaskLo, KnownLo, TLO, Depth + 1)) | ||||||
1848 | return true; | ||||||
1849 | |||||||
1850 | if (SimplifyDemandedBits(Op.getOperand(1), MaskHi, KnownHi, TLO, Depth + 1)) | ||||||
1851 | return true; | ||||||
1852 | |||||||
1853 | Known.Zero = KnownLo.Zero.zext(BitWidth) | | ||||||
1854 | KnownHi.Zero.zext(BitWidth).shl(HalfBitWidth); | ||||||
1855 | |||||||
1856 | Known.One = KnownLo.One.zext(BitWidth) | | ||||||
1857 | KnownHi.One.zext(BitWidth).shl(HalfBitWidth); | ||||||
1858 | break; | ||||||
1859 | } | ||||||
1860 | case ISD::ZERO_EXTEND: | ||||||
1861 | case ISD::ZERO_EXTEND_VECTOR_INREG: { | ||||||
1862 | SDValue Src = Op.getOperand(0); | ||||||
1863 | EVT SrcVT = Src.getValueType(); | ||||||
1864 | unsigned InBits = SrcVT.getScalarSizeInBits(); | ||||||
1865 | unsigned InElts = SrcVT.isVector() ? SrcVT.getVectorNumElements() : 1; | ||||||
1866 | bool IsVecInReg = Op.getOpcode() == ISD::ZERO_EXTEND_VECTOR_INREG; | ||||||
1867 | |||||||
1868 | // If none of the top bits are demanded, convert this into an any_extend. | ||||||
1869 | if (DemandedBits.getActiveBits() <= InBits) { | ||||||
1870 | // If we only need the non-extended bits of the bottom element | ||||||
1871 | // then we can just bitcast to the result. | ||||||
1872 | if (IsVecInReg && DemandedElts == 1 && | ||||||
1873 | VT.getSizeInBits() == SrcVT.getSizeInBits() && | ||||||
1874 | TLO.DAG.getDataLayout().isLittleEndian()) | ||||||
1875 | return TLO.CombineTo(Op, TLO.DAG.getBitcast(VT, Src)); | ||||||
1876 | |||||||
1877 | unsigned Opc = | ||||||
1878 | IsVecInReg ? ISD::ANY_EXTEND_VECTOR_INREG : ISD::ANY_EXTEND; | ||||||
1879 | if (!TLO.LegalOperations() || isOperationLegal(Opc, VT)) | ||||||
1880 | return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, Src)); | ||||||
1881 | } | ||||||
1882 | |||||||
1883 | APInt InDemandedBits = DemandedBits.trunc(InBits); | ||||||
1884 | APInt InDemandedElts = DemandedElts.zextOrSelf(InElts); | ||||||
1885 | if (SimplifyDemandedBits(Src, InDemandedBits, InDemandedElts, Known, TLO, | ||||||
1886 | Depth + 1)) | ||||||
1887 | return true; | ||||||
1888 | assert(!Known.hasConflict() && "Bits known to be one AND zero?")((!Known.hasConflict() && "Bits known to be one AND zero?" ) ? static_cast<void> (0) : __assert_fail ("!Known.hasConflict() && \"Bits known to be one AND zero?\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 1888, __PRETTY_FUNCTION__)); | ||||||
1889 | assert(Known.getBitWidth() == InBits && "Src width has changed?")((Known.getBitWidth() == InBits && "Src width has changed?" ) ? static_cast<void> (0) : __assert_fail ("Known.getBitWidth() == InBits && \"Src width has changed?\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 1889, __PRETTY_FUNCTION__)); | ||||||
1890 | Known = Known.zext(BitWidth); | ||||||
1891 | |||||||
1892 | // Attempt to avoid multi-use ops if we don't need anything from them. | ||||||
1893 | if (SDValue NewSrc = SimplifyMultipleUseDemandedBits( | ||||||
1894 | Src, InDemandedBits, InDemandedElts, TLO.DAG, Depth + 1)) | ||||||
1895 | return TLO.CombineTo(Op, TLO.DAG.getNode(Op.getOpcode(), dl, VT, NewSrc)); | ||||||
1896 | break; | ||||||
1897 | } | ||||||
1898 | case ISD::SIGN_EXTEND: | ||||||
1899 | case ISD::SIGN_EXTEND_VECTOR_INREG: { | ||||||
1900 | SDValue Src = Op.getOperand(0); | ||||||
1901 | EVT SrcVT = Src.getValueType(); | ||||||
1902 | unsigned InBits = SrcVT.getScalarSizeInBits(); | ||||||
1903 | unsigned InElts = SrcVT.isVector() ? SrcVT.getVectorNumElements() : 1; | ||||||
1904 | bool IsVecInReg = Op.getOpcode() == ISD::SIGN_EXTEND_VECTOR_INREG; | ||||||
1905 | |||||||
1906 | // If none of the top bits are demanded, convert this into an any_extend. | ||||||
1907 | if (DemandedBits.getActiveBits() <= InBits) { | ||||||
1908 | // If we only need the non-extended bits of the bottom element | ||||||
1909 | // then we can just bitcast to the result. | ||||||
1910 | if (IsVecInReg && DemandedElts == 1 && | ||||||
1911 | VT.getSizeInBits() == SrcVT.getSizeInBits() && | ||||||
1912 | TLO.DAG.getDataLayout().isLittleEndian()) | ||||||
1913 | return TLO.CombineTo(Op, TLO.DAG.getBitcast(VT, Src)); | ||||||
1914 | |||||||
1915 | unsigned Opc = | ||||||
1916 | IsVecInReg ? ISD::ANY_EXTEND_VECTOR_INREG : ISD::ANY_EXTEND; | ||||||
1917 | if (!TLO.LegalOperations() || isOperationLegal(Opc, VT)) | ||||||
1918 | return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, Src)); | ||||||
1919 | } | ||||||
1920 | |||||||
1921 | APInt InDemandedBits = DemandedBits.trunc(InBits); | ||||||
1922 | APInt InDemandedElts = DemandedElts.zextOrSelf(InElts); | ||||||
1923 | |||||||
1924 | // Since some of the sign extended bits are demanded, we know that the sign | ||||||
1925 | // bit is demanded. | ||||||
1926 | InDemandedBits.setBit(InBits - 1); | ||||||
1927 | |||||||
1928 | if (SimplifyDemandedBits(Src, InDemandedBits, InDemandedElts, Known, TLO, | ||||||
1929 | Depth + 1)) | ||||||
1930 | return true; | ||||||
1931 | assert(!Known.hasConflict() && "Bits known to be one AND zero?")((!Known.hasConflict() && "Bits known to be one AND zero?" ) ? static_cast<void> (0) : __assert_fail ("!Known.hasConflict() && \"Bits known to be one AND zero?\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 1931, __PRETTY_FUNCTION__)); | ||||||
1932 | assert(Known.getBitWidth() == InBits && "Src width has changed?")((Known.getBitWidth() == InBits && "Src width has changed?" ) ? static_cast<void> (0) : __assert_fail ("Known.getBitWidth() == InBits && \"Src width has changed?\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 1932, __PRETTY_FUNCTION__)); | ||||||
1933 | |||||||
1934 | // If the sign bit is known one, the top bits match. | ||||||
1935 | Known = Known.sext(BitWidth); | ||||||
1936 | |||||||
1937 | // If the sign bit is known zero, convert this to a zero extend. | ||||||
1938 | if (Known.isNonNegative()) { | ||||||
1939 | unsigned Opc = | ||||||
1940 | IsVecInReg ? ISD::ZERO_EXTEND_VECTOR_INREG : ISD::ZERO_EXTEND; | ||||||
1941 | if (!TLO.LegalOperations() || isOperationLegal(Opc, VT)) | ||||||
1942 | return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, Src)); | ||||||
1943 | } | ||||||
1944 | |||||||
1945 | // Attempt to avoid multi-use ops if we don't need anything from them. | ||||||
1946 | if (SDValue NewSrc = SimplifyMultipleUseDemandedBits( | ||||||
1947 | Src, InDemandedBits, InDemandedElts, TLO.DAG, Depth + 1)) | ||||||
1948 | return TLO.CombineTo(Op, TLO.DAG.getNode(Op.getOpcode(), dl, VT, NewSrc)); | ||||||
1949 | break; | ||||||
1950 | } | ||||||
1951 | case ISD::ANY_EXTEND: | ||||||
1952 | case ISD::ANY_EXTEND_VECTOR_INREG: { | ||||||
1953 | SDValue Src = Op.getOperand(0); | ||||||
1954 | EVT SrcVT = Src.getValueType(); | ||||||
1955 | unsigned InBits = SrcVT.getScalarSizeInBits(); | ||||||
1956 | unsigned InElts = SrcVT.isVector() ? SrcVT.getVectorNumElements() : 1; | ||||||
1957 | bool IsVecInReg = Op.getOpcode() == ISD::ANY_EXTEND_VECTOR_INREG; | ||||||
1958 | |||||||
1959 | // If we only need the bottom element then we can just bitcast. | ||||||
1960 | // TODO: Handle ANY_EXTEND? | ||||||
1961 | if (IsVecInReg && DemandedElts == 1 && | ||||||
1962 | VT.getSizeInBits() == SrcVT.getSizeInBits() && | ||||||
1963 | TLO.DAG.getDataLayout().isLittleEndian()) | ||||||
1964 | return TLO.CombineTo(Op, TLO.DAG.getBitcast(VT, Src)); | ||||||
1965 | |||||||
1966 | APInt InDemandedBits = DemandedBits.trunc(InBits); | ||||||
1967 | APInt InDemandedElts = DemandedElts.zextOrSelf(InElts); | ||||||
1968 | if (SimplifyDemandedBits(Src, InDemandedBits, InDemandedElts, Known, TLO, | ||||||
1969 | Depth + 1)) | ||||||
1970 | return true; | ||||||
1971 | assert(!Known.hasConflict() && "Bits known to be one AND zero?")((!Known.hasConflict() && "Bits known to be one AND zero?" ) ? static_cast<void> (0) : __assert_fail ("!Known.hasConflict() && \"Bits known to be one AND zero?\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 1971, __PRETTY_FUNCTION__)); | ||||||
1972 | assert(Known.getBitWidth() == InBits && "Src width has changed?")((Known.getBitWidth() == InBits && "Src width has changed?" ) ? static_cast<void> (0) : __assert_fail ("Known.getBitWidth() == InBits && \"Src width has changed?\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 1972, __PRETTY_FUNCTION__)); | ||||||
1973 | Known = Known.anyext(BitWidth); | ||||||
1974 | |||||||
1975 | // Attempt to avoid multi-use ops if we don't need anything from them. | ||||||
1976 | if (SDValue NewSrc = SimplifyMultipleUseDemandedBits( | ||||||
1977 | Src, InDemandedBits, InDemandedElts, TLO.DAG, Depth + 1)) | ||||||
1978 | return TLO.CombineTo(Op, TLO.DAG.getNode(Op.getOpcode(), dl, VT, NewSrc)); | ||||||
1979 | break; | ||||||
1980 | } | ||||||
1981 | case ISD::TRUNCATE: { | ||||||
1982 | SDValue Src = Op.getOperand(0); | ||||||
1983 | |||||||
1984 | // Simplify the input, using demanded bit information, and compute the known | ||||||
1985 | // zero/one bits live out. | ||||||
1986 | unsigned OperandBitWidth = Src.getScalarValueSizeInBits(); | ||||||
1987 | APInt TruncMask = DemandedBits.zext(OperandBitWidth); | ||||||
1988 | if (SimplifyDemandedBits(Src, TruncMask, DemandedElts, Known, TLO, | ||||||
1989 | Depth + 1)) | ||||||
1990 | return true; | ||||||
1991 | Known = Known.trunc(BitWidth); | ||||||
1992 | |||||||
1993 | // Attempt to avoid multi-use ops if we don't need anything from them. | ||||||
1994 | if (SDValue NewSrc = SimplifyMultipleUseDemandedBits( | ||||||
1995 | Src, TruncMask, DemandedElts, TLO.DAG, Depth + 1)) | ||||||
1996 | return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::TRUNCATE, dl, VT, NewSrc)); | ||||||
1997 | |||||||
1998 | // If the input is only used by this truncate, see if we can shrink it based | ||||||
1999 | // on the known demanded bits. | ||||||
2000 | if (Src.getNode()->hasOneUse()) { | ||||||
2001 | switch (Src.getOpcode()) { | ||||||
2002 | default: | ||||||
2003 | break; | ||||||
2004 | case ISD::SRL: | ||||||
2005 | // Shrink SRL by a constant if none of the high bits shifted in are | ||||||
2006 | // demanded. | ||||||
2007 | if (TLO.LegalTypes() && !isTypeDesirableForOp(ISD::SRL, VT)) | ||||||
2008 | // Do not turn (vt1 truncate (vt2 srl)) into (vt1 srl) if vt1 is | ||||||
2009 | // undesirable. | ||||||
2010 | break; | ||||||
2011 | |||||||
2012 | const APInt *ShAmtC = | ||||||
2013 | TLO.DAG.getValidShiftAmountConstant(Src, DemandedElts); | ||||||
2014 | if (!ShAmtC || ShAmtC->uge(BitWidth)) | ||||||
2015 | break; | ||||||
2016 | uint64_t ShVal = ShAmtC->getZExtValue(); | ||||||
2017 | |||||||
2018 | APInt HighBits = | ||||||
2019 | APInt::getHighBitsSet(OperandBitWidth, OperandBitWidth - BitWidth); | ||||||
2020 | HighBits.lshrInPlace(ShVal); | ||||||
2021 | HighBits = HighBits.trunc(BitWidth); | ||||||
2022 | |||||||
2023 | if (!(HighBits & DemandedBits)) { | ||||||
2024 | // None of the shifted in bits are needed. Add a truncate of the | ||||||
2025 | // shift input, then shift it. | ||||||
2026 | SDValue NewShAmt = TLO.DAG.getConstant( | ||||||
2027 | ShVal, dl, getShiftAmountTy(VT, DL, TLO.LegalTypes())); | ||||||
2028 | SDValue NewTrunc = | ||||||
2029 | TLO.DAG.getNode(ISD::TRUNCATE, dl, VT, Src.getOperand(0)); | ||||||
2030 | return TLO.CombineTo( | ||||||
2031 | Op, TLO.DAG.getNode(ISD::SRL, dl, VT, NewTrunc, NewShAmt)); | ||||||
2032 | } | ||||||
2033 | break; | ||||||
2034 | } | ||||||
2035 | } | ||||||
2036 | |||||||
2037 | assert(!Known.hasConflict() && "Bits known to be one AND zero?")((!Known.hasConflict() && "Bits known to be one AND zero?" ) ? static_cast<void> (0) : __assert_fail ("!Known.hasConflict() && \"Bits known to be one AND zero?\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2037, __PRETTY_FUNCTION__)); | ||||||
2038 | break; | ||||||
2039 | } | ||||||
2040 | case ISD::AssertZext: { | ||||||
2041 | // AssertZext demands all of the high bits, plus any of the low bits | ||||||
2042 | // demanded by its users. | ||||||
2043 | EVT ZVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); | ||||||
2044 | APInt InMask = APInt::getLowBitsSet(BitWidth, ZVT.getSizeInBits()); | ||||||
2045 | if (SimplifyDemandedBits(Op.getOperand(0), ~InMask | DemandedBits, Known, | ||||||
2046 | TLO, Depth + 1)) | ||||||
2047 | return true; | ||||||
2048 | assert(!Known.hasConflict() && "Bits known to be one AND zero?")((!Known.hasConflict() && "Bits known to be one AND zero?" ) ? static_cast<void> (0) : __assert_fail ("!Known.hasConflict() && \"Bits known to be one AND zero?\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2048, __PRETTY_FUNCTION__)); | ||||||
2049 | |||||||
2050 | Known.Zero |= ~InMask; | ||||||
2051 | break; | ||||||
2052 | } | ||||||
2053 | case ISD::EXTRACT_VECTOR_ELT: { | ||||||
2054 | SDValue Src = Op.getOperand(0); | ||||||
2055 | SDValue Idx = Op.getOperand(1); | ||||||
2056 | ElementCount SrcEltCnt = Src.getValueType().getVectorElementCount(); | ||||||
2057 | unsigned EltBitWidth = Src.getScalarValueSizeInBits(); | ||||||
2058 | |||||||
2059 | if (SrcEltCnt.isScalable()) | ||||||
2060 | return false; | ||||||
2061 | |||||||
2062 | // Demand the bits from every vector element without a constant index. | ||||||
2063 | unsigned NumSrcElts = SrcEltCnt.getFixedValue(); | ||||||
2064 | APInt DemandedSrcElts = APInt::getAllOnesValue(NumSrcElts); | ||||||
2065 | if (auto *CIdx = dyn_cast<ConstantSDNode>(Idx)) | ||||||
2066 | if (CIdx->getAPIntValue().ult(NumSrcElts)) | ||||||
2067 | DemandedSrcElts = APInt::getOneBitSet(NumSrcElts, CIdx->getZExtValue()); | ||||||
2068 | |||||||
2069 | // If BitWidth > EltBitWidth the value is anyext:ed. So we do not know | ||||||
2070 | // anything about the extended bits. | ||||||
2071 | APInt DemandedSrcBits = DemandedBits; | ||||||
2072 | if (BitWidth > EltBitWidth) | ||||||
2073 | DemandedSrcBits = DemandedSrcBits.trunc(EltBitWidth); | ||||||
2074 | |||||||
2075 | if (SimplifyDemandedBits(Src, DemandedSrcBits, DemandedSrcElts, Known2, TLO, | ||||||
2076 | Depth + 1)) | ||||||
2077 | return true; | ||||||
2078 | |||||||
2079 | // Attempt to avoid multi-use ops if we don't need anything from them. | ||||||
2080 | if (!DemandedSrcBits.isAllOnesValue() || | ||||||
2081 | !DemandedSrcElts.isAllOnesValue()) { | ||||||
2082 | if (SDValue DemandedSrc = SimplifyMultipleUseDemandedBits( | ||||||
2083 | Src, DemandedSrcBits, DemandedSrcElts, TLO.DAG, Depth + 1)) { | ||||||
2084 | SDValue NewOp = | ||||||
2085 | TLO.DAG.getNode(Op.getOpcode(), dl, VT, DemandedSrc, Idx); | ||||||
2086 | return TLO.CombineTo(Op, NewOp); | ||||||
2087 | } | ||||||
2088 | } | ||||||
2089 | |||||||
2090 | Known = Known2; | ||||||
2091 | if (BitWidth > EltBitWidth) | ||||||
2092 | Known = Known.anyext(BitWidth); | ||||||
2093 | break; | ||||||
2094 | } | ||||||
2095 | case ISD::BITCAST: { | ||||||
2096 | SDValue Src = Op.getOperand(0); | ||||||
2097 | EVT SrcVT = Src.getValueType(); | ||||||
2098 | unsigned NumSrcEltBits = SrcVT.getScalarSizeInBits(); | ||||||
2099 | |||||||
2100 | // If this is an FP->Int bitcast and if the sign bit is the only | ||||||
2101 | // thing demanded, turn this into a FGETSIGN. | ||||||
2102 | if (!TLO.LegalOperations() && !VT.isVector() && !SrcVT.isVector() && | ||||||
2103 | DemandedBits == APInt::getSignMask(Op.getValueSizeInBits()) && | ||||||
2104 | SrcVT.isFloatingPoint()) { | ||||||
2105 | bool OpVTLegal = isOperationLegalOrCustom(ISD::FGETSIGN, VT); | ||||||
2106 | bool i32Legal = isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32); | ||||||
2107 | if ((OpVTLegal || i32Legal) && VT.isSimple() && SrcVT != MVT::f16 && | ||||||
2108 | SrcVT != MVT::f128) { | ||||||
2109 | // Cannot eliminate/lower SHL for f128 yet. | ||||||
2110 | EVT Ty = OpVTLegal ? VT : MVT::i32; | ||||||
2111 | // Make a FGETSIGN + SHL to move the sign bit into the appropriate | ||||||
2112 | // place. We expect the SHL to be eliminated by other optimizations. | ||||||
2113 | SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, dl, Ty, Src); | ||||||
2114 | unsigned OpVTSizeInBits = Op.getValueSizeInBits(); | ||||||
2115 | if (!OpVTLegal && OpVTSizeInBits > 32) | ||||||
2116 | Sign = TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Sign); | ||||||
2117 | unsigned ShVal = Op.getValueSizeInBits() - 1; | ||||||
2118 | SDValue ShAmt = TLO.DAG.getConstant(ShVal, dl, VT); | ||||||
2119 | return TLO.CombineTo(Op, | ||||||
2120 | TLO.DAG.getNode(ISD::SHL, dl, VT, Sign, ShAmt)); | ||||||
2121 | } | ||||||
2122 | } | ||||||
2123 | |||||||
2124 | // Bitcast from a vector using SimplifyDemanded Bits/VectorElts. | ||||||
2125 | // Demand the elt/bit if any of the original elts/bits are demanded. | ||||||
2126 | // TODO - bigendian once we have test coverage. | ||||||
2127 | if (SrcVT.isVector() && (BitWidth % NumSrcEltBits) == 0 && | ||||||
2128 | TLO.DAG.getDataLayout().isLittleEndian()) { | ||||||
2129 | unsigned Scale = BitWidth / NumSrcEltBits; | ||||||
2130 | unsigned NumSrcElts = SrcVT.getVectorNumElements(); | ||||||
2131 | APInt DemandedSrcBits = APInt::getNullValue(NumSrcEltBits); | ||||||
2132 | APInt DemandedSrcElts = APInt::getNullValue(NumSrcElts); | ||||||
2133 | for (unsigned i = 0; i != Scale; ++i) { | ||||||
2134 | unsigned Offset = i * NumSrcEltBits; | ||||||
2135 | APInt Sub = DemandedBits.extractBits(NumSrcEltBits, Offset); | ||||||
2136 | if (!Sub.isNullValue()) { | ||||||
2137 | DemandedSrcBits |= Sub; | ||||||
2138 | for (unsigned j = 0; j != NumElts; ++j) | ||||||
2139 | if (DemandedElts[j]) | ||||||
2140 | DemandedSrcElts.setBit((j * Scale) + i); | ||||||
2141 | } | ||||||
2142 | } | ||||||
2143 | |||||||
2144 | APInt KnownSrcUndef, KnownSrcZero; | ||||||
2145 | if (SimplifyDemandedVectorElts(Src, DemandedSrcElts, KnownSrcUndef, | ||||||
2146 | KnownSrcZero, TLO, Depth + 1)) | ||||||
2147 | return true; | ||||||
2148 | |||||||
2149 | KnownBits KnownSrcBits; | ||||||
2150 | if (SimplifyDemandedBits(Src, DemandedSrcBits, DemandedSrcElts, | ||||||
2151 | KnownSrcBits, TLO, Depth + 1)) | ||||||
2152 | return true; | ||||||
2153 | } else if ((NumSrcEltBits % BitWidth) == 0 && | ||||||
2154 | TLO.DAG.getDataLayout().isLittleEndian()) { | ||||||
2155 | unsigned Scale = NumSrcEltBits / BitWidth; | ||||||
2156 | unsigned NumSrcElts = SrcVT.isVector() ? SrcVT.getVectorNumElements() : 1; | ||||||
2157 | APInt DemandedSrcBits = APInt::getNullValue(NumSrcEltBits); | ||||||
2158 | APInt DemandedSrcElts = APInt::getNullValue(NumSrcElts); | ||||||
2159 | for (unsigned i = 0; i != NumElts; ++i) | ||||||
2160 | if (DemandedElts[i]) { | ||||||
2161 | unsigned Offset = (i % Scale) * BitWidth; | ||||||
2162 | DemandedSrcBits.insertBits(DemandedBits, Offset); | ||||||
2163 | DemandedSrcElts.setBit(i / Scale); | ||||||
2164 | } | ||||||
2165 | |||||||
2166 | if (SrcVT.isVector()) { | ||||||
2167 | APInt KnownSrcUndef, KnownSrcZero; | ||||||
2168 | if (SimplifyDemandedVectorElts(Src, DemandedSrcElts, KnownSrcUndef, | ||||||
2169 | KnownSrcZero, TLO, Depth + 1)) | ||||||
2170 | return true; | ||||||
2171 | } | ||||||
2172 | |||||||
2173 | KnownBits KnownSrcBits; | ||||||
2174 | if (SimplifyDemandedBits(Src, DemandedSrcBits, DemandedSrcElts, | ||||||
2175 | KnownSrcBits, TLO, Depth + 1)) | ||||||
2176 | return true; | ||||||
2177 | } | ||||||
2178 | |||||||
2179 | // If this is a bitcast, let computeKnownBits handle it. Only do this on a | ||||||
2180 | // recursive call where Known may be useful to the caller. | ||||||
2181 | if (Depth > 0) { | ||||||
2182 | Known = TLO.DAG.computeKnownBits(Op, DemandedElts, Depth); | ||||||
2183 | return false; | ||||||
2184 | } | ||||||
2185 | break; | ||||||
2186 | } | ||||||
2187 | case ISD::ADD: | ||||||
2188 | case ISD::MUL: | ||||||
2189 | case ISD::SUB: { | ||||||
2190 | // Add, Sub, and Mul don't demand any bits in positions beyond that | ||||||
2191 | // of the highest bit demanded of them. | ||||||
2192 | SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1); | ||||||
2193 | SDNodeFlags Flags = Op.getNode()->getFlags(); | ||||||
2194 | unsigned DemandedBitsLZ = DemandedBits.countLeadingZeros(); | ||||||
2195 | APInt LoMask = APInt::getLowBitsSet(BitWidth, BitWidth - DemandedBitsLZ); | ||||||
2196 | if (SimplifyDemandedBits(Op0, LoMask, DemandedElts, Known2, TLO, | ||||||
2197 | Depth + 1) || | ||||||
2198 | SimplifyDemandedBits(Op1, LoMask, DemandedElts, Known2, TLO, | ||||||
2199 | Depth + 1) || | ||||||
2200 | // See if the operation should be performed at a smaller bit width. | ||||||
2201 | ShrinkDemandedOp(Op, BitWidth, DemandedBits, TLO)) { | ||||||
2202 | if (Flags.hasNoSignedWrap() || Flags.hasNoUnsignedWrap()) { | ||||||
2203 | // Disable the nsw and nuw flags. We can no longer guarantee that we | ||||||
2204 | // won't wrap after simplification. | ||||||
2205 | Flags.setNoSignedWrap(false); | ||||||
2206 | Flags.setNoUnsignedWrap(false); | ||||||
2207 | SDValue NewOp = | ||||||
2208 | TLO.DAG.getNode(Op.getOpcode(), dl, VT, Op0, Op1, Flags); | ||||||
2209 | return TLO.CombineTo(Op, NewOp); | ||||||
2210 | } | ||||||
2211 | return true; | ||||||
2212 | } | ||||||
2213 | |||||||
2214 | // Attempt to avoid multi-use ops if we don't need anything from them. | ||||||
2215 | if (!LoMask.isAllOnesValue() || !DemandedElts.isAllOnesValue()) { | ||||||
2216 | SDValue DemandedOp0 = SimplifyMultipleUseDemandedBits( | ||||||
2217 | Op0, LoMask, DemandedElts, TLO.DAG, Depth + 1); | ||||||
2218 | SDValue DemandedOp1 = SimplifyMultipleUseDemandedBits( | ||||||
2219 | Op1, LoMask, DemandedElts, TLO.DAG, Depth + 1); | ||||||
2220 | if (DemandedOp0 || DemandedOp1) { | ||||||
2221 | Flags.setNoSignedWrap(false); | ||||||
2222 | Flags.setNoUnsignedWrap(false); | ||||||
2223 | Op0 = DemandedOp0 ? DemandedOp0 : Op0; | ||||||
2224 | Op1 = DemandedOp1 ? DemandedOp1 : Op1; | ||||||
2225 | SDValue NewOp = | ||||||
2226 | TLO.DAG.getNode(Op.getOpcode(), dl, VT, Op0, Op1, Flags); | ||||||
2227 | return TLO.CombineTo(Op, NewOp); | ||||||
2228 | } | ||||||
2229 | } | ||||||
2230 | |||||||
2231 | // If we have a constant operand, we may be able to turn it into -1 if we | ||||||
2232 | // do not demand the high bits. This can make the constant smaller to | ||||||
2233 | // encode, allow more general folding, or match specialized instruction | ||||||
2234 | // patterns (eg, 'blsr' on x86). Don't bother changing 1 to -1 because that | ||||||
2235 | // is probably not useful (and could be detrimental). | ||||||
2236 | ConstantSDNode *C = isConstOrConstSplat(Op1); | ||||||
2237 | APInt HighMask = APInt::getHighBitsSet(BitWidth, DemandedBitsLZ); | ||||||
2238 | if (C && !C->isAllOnesValue() && !C->isOne() && | ||||||
2239 | (C->getAPIntValue() | HighMask).isAllOnesValue()) { | ||||||
2240 | SDValue Neg1 = TLO.DAG.getAllOnesConstant(dl, VT); | ||||||
2241 | // Disable the nsw and nuw flags. We can no longer guarantee that we | ||||||
2242 | // won't wrap after simplification. | ||||||
2243 | Flags.setNoSignedWrap(false); | ||||||
2244 | Flags.setNoUnsignedWrap(false); | ||||||
2245 | SDValue NewOp = TLO.DAG.getNode(Op.getOpcode(), dl, VT, Op0, Neg1, Flags); | ||||||
2246 | return TLO.CombineTo(Op, NewOp); | ||||||
2247 | } | ||||||
2248 | |||||||
2249 | LLVM_FALLTHROUGH[[gnu::fallthrough]]; | ||||||
2250 | } | ||||||
2251 | default: | ||||||
2252 | if (Op.getOpcode() >= ISD::BUILTIN_OP_END) { | ||||||
2253 | if (SimplifyDemandedBitsForTargetNode(Op, DemandedBits, DemandedElts, | ||||||
2254 | Known, TLO, Depth)) | ||||||
2255 | return true; | ||||||
2256 | break; | ||||||
2257 | } | ||||||
2258 | |||||||
2259 | // Just use computeKnownBits to compute output bits. | ||||||
2260 | Known = TLO.DAG.computeKnownBits(Op, DemandedElts, Depth); | ||||||
2261 | break; | ||||||
2262 | } | ||||||
2263 | |||||||
2264 | // If we know the value of all of the demanded bits, return this as a | ||||||
2265 | // constant. | ||||||
2266 | if (DemandedBits.isSubsetOf(Known.Zero | Known.One)) { | ||||||
2267 | // Avoid folding to a constant if any OpaqueConstant is involved. | ||||||
2268 | const SDNode *N = Op.getNode(); | ||||||
2269 | for (SDNode *Op : | ||||||
2270 | llvm::make_range(SDNodeIterator::begin(N), SDNodeIterator::end(N))) { | ||||||
2271 | if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) | ||||||
2272 | if (C->isOpaque()) | ||||||
2273 | return false; | ||||||
2274 | } | ||||||
2275 | if (VT.isInteger()) | ||||||
2276 | return TLO.CombineTo(Op, TLO.DAG.getConstant(Known.One, dl, VT)); | ||||||
2277 | if (VT.isFloatingPoint()) | ||||||
2278 | return TLO.CombineTo( | ||||||
2279 | Op, | ||||||
2280 | TLO.DAG.getConstantFP( | ||||||
2281 | APFloat(TLO.DAG.EVTToAPFloatSemantics(VT), Known.One), dl, VT)); | ||||||
2282 | } | ||||||
2283 | |||||||
2284 | return false; | ||||||
2285 | } | ||||||
2286 | |||||||
2287 | bool TargetLowering::SimplifyDemandedVectorElts(SDValue Op, | ||||||
2288 | const APInt &DemandedElts, | ||||||
2289 | APInt &KnownUndef, | ||||||
2290 | APInt &KnownZero, | ||||||
2291 | DAGCombinerInfo &DCI) const { | ||||||
2292 | SelectionDAG &DAG = DCI.DAG; | ||||||
2293 | TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), | ||||||
2294 | !DCI.isBeforeLegalizeOps()); | ||||||
2295 | |||||||
2296 | bool Simplified = | ||||||
2297 | SimplifyDemandedVectorElts(Op, DemandedElts, KnownUndef, KnownZero, TLO); | ||||||
2298 | if (Simplified) { | ||||||
2299 | DCI.AddToWorklist(Op.getNode()); | ||||||
2300 | DCI.CommitTargetLoweringOpt(TLO); | ||||||
2301 | } | ||||||
2302 | |||||||
2303 | return Simplified; | ||||||
2304 | } | ||||||
2305 | |||||||
2306 | /// Given a vector binary operation and known undefined elements for each input | ||||||
2307 | /// operand, compute whether each element of the output is undefined. | ||||||
2308 | static APInt getKnownUndefForVectorBinop(SDValue BO, SelectionDAG &DAG, | ||||||
2309 | const APInt &UndefOp0, | ||||||
2310 | const APInt &UndefOp1) { | ||||||
2311 | EVT VT = BO.getValueType(); | ||||||
2312 | assert(DAG.getTargetLoweringInfo().isBinOp(BO.getOpcode()) && VT.isVector() &&((DAG.getTargetLoweringInfo().isBinOp(BO.getOpcode()) && VT.isVector() && "Vector binop only") ? static_cast< void> (0) : __assert_fail ("DAG.getTargetLoweringInfo().isBinOp(BO.getOpcode()) && VT.isVector() && \"Vector binop only\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2313, __PRETTY_FUNCTION__)) | ||||||
2313 | "Vector binop only")((DAG.getTargetLoweringInfo().isBinOp(BO.getOpcode()) && VT.isVector() && "Vector binop only") ? static_cast< void> (0) : __assert_fail ("DAG.getTargetLoweringInfo().isBinOp(BO.getOpcode()) && VT.isVector() && \"Vector binop only\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2313, __PRETTY_FUNCTION__)); | ||||||
2314 | |||||||
2315 | EVT EltVT = VT.getVectorElementType(); | ||||||
2316 | unsigned NumElts = VT.getVectorNumElements(); | ||||||
2317 | assert(UndefOp0.getBitWidth() == NumElts &&((UndefOp0.getBitWidth() == NumElts && UndefOp1.getBitWidth () == NumElts && "Bad type for undef analysis") ? static_cast <void> (0) : __assert_fail ("UndefOp0.getBitWidth() == NumElts && UndefOp1.getBitWidth() == NumElts && \"Bad type for undef analysis\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2318, __PRETTY_FUNCTION__)) | ||||||
2318 | UndefOp1.getBitWidth() == NumElts && "Bad type for undef analysis")((UndefOp0.getBitWidth() == NumElts && UndefOp1.getBitWidth () == NumElts && "Bad type for undef analysis") ? static_cast <void> (0) : __assert_fail ("UndefOp0.getBitWidth() == NumElts && UndefOp1.getBitWidth() == NumElts && \"Bad type for undef analysis\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2318, __PRETTY_FUNCTION__)); | ||||||
2319 | |||||||
2320 | auto getUndefOrConstantElt = [&](SDValue V, unsigned Index, | ||||||
2321 | const APInt &UndefVals) { | ||||||
2322 | if (UndefVals[Index]) | ||||||
2323 | return DAG.getUNDEF(EltVT); | ||||||
2324 | |||||||
2325 | if (auto *BV = dyn_cast<BuildVectorSDNode>(V)) { | ||||||
2326 | // Try hard to make sure that the getNode() call is not creating temporary | ||||||
2327 | // nodes. Ignore opaque integers because they do not constant fold. | ||||||
2328 | SDValue Elt = BV->getOperand(Index); | ||||||
2329 | auto *C = dyn_cast<ConstantSDNode>(Elt); | ||||||
2330 | if (isa<ConstantFPSDNode>(Elt) || Elt.isUndef() || (C && !C->isOpaque())) | ||||||
2331 | return Elt; | ||||||
2332 | } | ||||||
2333 | |||||||
2334 | return SDValue(); | ||||||
2335 | }; | ||||||
2336 | |||||||
2337 | APInt KnownUndef = APInt::getNullValue(NumElts); | ||||||
2338 | for (unsigned i = 0; i != NumElts; ++i) { | ||||||
2339 | // If both inputs for this element are either constant or undef and match | ||||||
2340 | // the element type, compute the constant/undef result for this element of | ||||||
2341 | // the vector. | ||||||
2342 | // TODO: Ideally we would use FoldConstantArithmetic() here, but that does | ||||||
2343 | // not handle FP constants. The code within getNode() should be refactored | ||||||
2344 | // to avoid the danger of creating a bogus temporary node here. | ||||||
2345 | SDValue C0 = getUndefOrConstantElt(BO.getOperand(0), i, UndefOp0); | ||||||
2346 | SDValue C1 = getUndefOrConstantElt(BO.getOperand(1), i, UndefOp1); | ||||||
2347 | if (C0 && C1 && C0.getValueType() == EltVT && C1.getValueType() == EltVT) | ||||||
2348 | if (DAG.getNode(BO.getOpcode(), SDLoc(BO), EltVT, C0, C1).isUndef()) | ||||||
2349 | KnownUndef.setBit(i); | ||||||
2350 | } | ||||||
2351 | return KnownUndef; | ||||||
2352 | } | ||||||
2353 | |||||||
2354 | bool TargetLowering::SimplifyDemandedVectorElts( | ||||||
2355 | SDValue Op, const APInt &OriginalDemandedElts, APInt &KnownUndef, | ||||||
2356 | APInt &KnownZero, TargetLoweringOpt &TLO, unsigned Depth, | ||||||
2357 | bool AssumeSingleUse) const { | ||||||
2358 | EVT VT = Op.getValueType(); | ||||||
2359 | unsigned Opcode = Op.getOpcode(); | ||||||
2360 | APInt DemandedElts = OriginalDemandedElts; | ||||||
2361 | unsigned NumElts = DemandedElts.getBitWidth(); | ||||||
2362 | assert(VT.isVector() && "Expected vector op")((VT.isVector() && "Expected vector op") ? static_cast <void> (0) : __assert_fail ("VT.isVector() && \"Expected vector op\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2362, __PRETTY_FUNCTION__)); | ||||||
2363 | |||||||
2364 | KnownUndef = KnownZero = APInt::getNullValue(NumElts); | ||||||
2365 | |||||||
2366 | // TODO: For now we assume we know nothing about scalable vectors. | ||||||
2367 | if (VT.isScalableVector()) | ||||||
2368 | return false; | ||||||
2369 | |||||||
2370 | assert(VT.getVectorNumElements() == NumElts &&((VT.getVectorNumElements() == NumElts && "Mask size mismatches value type element count!" ) ? static_cast<void> (0) : __assert_fail ("VT.getVectorNumElements() == NumElts && \"Mask size mismatches value type element count!\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2371, __PRETTY_FUNCTION__)) | ||||||
2371 | "Mask size mismatches value type element count!")((VT.getVectorNumElements() == NumElts && "Mask size mismatches value type element count!" ) ? static_cast<void> (0) : __assert_fail ("VT.getVectorNumElements() == NumElts && \"Mask size mismatches value type element count!\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2371, __PRETTY_FUNCTION__)); | ||||||
2372 | |||||||
2373 | // Undef operand. | ||||||
2374 | if (Op.isUndef()) { | ||||||
2375 | KnownUndef.setAllBits(); | ||||||
2376 | return false; | ||||||
2377 | } | ||||||
2378 | |||||||
2379 | // If Op has other users, assume that all elements are needed. | ||||||
2380 | if (!Op.getNode()->hasOneUse() && !AssumeSingleUse) | ||||||
2381 | DemandedElts.setAllBits(); | ||||||
2382 | |||||||
2383 | // Not demanding any elements from Op. | ||||||
2384 | if (DemandedElts == 0) { | ||||||
2385 | KnownUndef.setAllBits(); | ||||||
2386 | return TLO.CombineTo(Op, TLO.DAG.getUNDEF(VT)); | ||||||
2387 | } | ||||||
2388 | |||||||
2389 | // Limit search depth. | ||||||
2390 | if (Depth >= SelectionDAG::MaxRecursionDepth) | ||||||
2391 | return false; | ||||||
2392 | |||||||
2393 | SDLoc DL(Op); | ||||||
2394 | unsigned EltSizeInBits = VT.getScalarSizeInBits(); | ||||||
2395 | |||||||
2396 | // Helper for demanding the specified elements and all the bits of both binary | ||||||
2397 | // operands. | ||||||
2398 | auto SimplifyDemandedVectorEltsBinOp = [&](SDValue Op0, SDValue Op1) { | ||||||
2399 | SDValue NewOp0 = SimplifyMultipleUseDemandedVectorElts(Op0, DemandedElts, | ||||||
2400 | TLO.DAG, Depth + 1); | ||||||
2401 | SDValue NewOp1 = SimplifyMultipleUseDemandedVectorElts(Op1, DemandedElts, | ||||||
2402 | TLO.DAG, Depth + 1); | ||||||
2403 | if (NewOp0 || NewOp1) { | ||||||
2404 | SDValue NewOp = TLO.DAG.getNode( | ||||||
2405 | Opcode, SDLoc(Op), VT, NewOp0 ? NewOp0 : Op0, NewOp1 ? NewOp1 : Op1); | ||||||
2406 | return TLO.CombineTo(Op, NewOp); | ||||||
2407 | } | ||||||
2408 | return false; | ||||||
2409 | }; | ||||||
2410 | |||||||
2411 | switch (Opcode) { | ||||||
2412 | case ISD::SCALAR_TO_VECTOR: { | ||||||
2413 | if (!DemandedElts[0]) { | ||||||
2414 | KnownUndef.setAllBits(); | ||||||
2415 | return TLO.CombineTo(Op, TLO.DAG.getUNDEF(VT)); | ||||||
2416 | } | ||||||
2417 | KnownUndef.setHighBits(NumElts - 1); | ||||||
2418 | break; | ||||||
2419 | } | ||||||
2420 | case ISD::BITCAST: { | ||||||
2421 | SDValue Src = Op.getOperand(0); | ||||||
2422 | EVT SrcVT = Src.getValueType(); | ||||||
2423 | |||||||
2424 | // We only handle vectors here. | ||||||
2425 | // TODO - investigate calling SimplifyDemandedBits/ComputeKnownBits? | ||||||
2426 | if (!SrcVT.isVector()) | ||||||
2427 | break; | ||||||
2428 | |||||||
2429 | // Fast handling of 'identity' bitcasts. | ||||||
2430 | unsigned NumSrcElts = SrcVT.getVectorNumElements(); | ||||||
2431 | if (NumSrcElts == NumElts) | ||||||
2432 | return SimplifyDemandedVectorElts(Src, DemandedElts, KnownUndef, | ||||||
2433 | KnownZero, TLO, Depth + 1); | ||||||
2434 | |||||||
2435 | APInt SrcZero, SrcUndef; | ||||||
2436 | APInt SrcDemandedElts = APInt::getNullValue(NumSrcElts); | ||||||
2437 | |||||||
2438 | // Bitcast from 'large element' src vector to 'small element' vector, we | ||||||
2439 | // must demand a source element if any DemandedElt maps to it. | ||||||
2440 | if ((NumElts % NumSrcElts) == 0) { | ||||||
2441 | unsigned Scale = NumElts / NumSrcElts; | ||||||
2442 | for (unsigned i = 0; i != NumElts; ++i) | ||||||
2443 | if (DemandedElts[i]) | ||||||
2444 | SrcDemandedElts.setBit(i / Scale); | ||||||
2445 | |||||||
2446 | if (SimplifyDemandedVectorElts(Src, SrcDemandedElts, SrcUndef, SrcZero, | ||||||
2447 | TLO, Depth + 1)) | ||||||
2448 | return true; | ||||||
2449 | |||||||
2450 | // Try calling SimplifyDemandedBits, converting demanded elts to the bits | ||||||
2451 | // of the large element. | ||||||
2452 | // TODO - bigendian once we have test coverage. | ||||||
2453 | if (TLO.DAG.getDataLayout().isLittleEndian()) { | ||||||
2454 | unsigned SrcEltSizeInBits = SrcVT.getScalarSizeInBits(); | ||||||
2455 | APInt SrcDemandedBits = APInt::getNullValue(SrcEltSizeInBits); | ||||||
2456 | for (unsigned i = 0; i != NumElts; ++i) | ||||||
2457 | if (DemandedElts[i]) { | ||||||
2458 | unsigned Ofs = (i % Scale) * EltSizeInBits; | ||||||
2459 | SrcDemandedBits.setBits(Ofs, Ofs + EltSizeInBits); | ||||||
2460 | } | ||||||
2461 | |||||||
2462 | KnownBits Known; | ||||||
2463 | if (SimplifyDemandedBits(Src, SrcDemandedBits, SrcDemandedElts, Known, | ||||||
2464 | TLO, Depth + 1)) | ||||||
2465 | return true; | ||||||
2466 | } | ||||||
2467 | |||||||
2468 | // If the src element is zero/undef then all the output elements will be - | ||||||
2469 | // only demanded elements are guaranteed to be correct. | ||||||
2470 | for (unsigned i = 0; i != NumSrcElts; ++i) { | ||||||
2471 | if (SrcDemandedElts[i]) { | ||||||
2472 | if (SrcZero[i]) | ||||||
2473 | KnownZero.setBits(i * Scale, (i + 1) * Scale); | ||||||
2474 | if (SrcUndef[i]) | ||||||
2475 | KnownUndef.setBits(i * Scale, (i + 1) * Scale); | ||||||
2476 | } | ||||||
2477 | } | ||||||
2478 | } | ||||||
2479 | |||||||
2480 | // Bitcast from 'small element' src vector to 'large element' vector, we | ||||||
2481 | // demand all smaller source elements covered by the larger demanded element | ||||||
2482 | // of this vector. | ||||||
2483 | if ((NumSrcElts % NumElts) == 0) { | ||||||
2484 | unsigned Scale = NumSrcElts / NumElts; | ||||||
2485 | for (unsigned i = 0; i != NumElts; ++i) | ||||||
2486 | if (DemandedElts[i]) | ||||||
2487 | SrcDemandedElts.setBits(i * Scale, (i + 1) * Scale); | ||||||
2488 | |||||||
2489 | if (SimplifyDemandedVectorElts(Src, SrcDemandedElts, SrcUndef, SrcZero, | ||||||
2490 | TLO, Depth + 1)) | ||||||
2491 | return true; | ||||||
2492 | |||||||
2493 | // If all the src elements covering an output element are zero/undef, then | ||||||
2494 | // the output element will be as well, assuming it was demanded. | ||||||
2495 | for (unsigned i = 0; i != NumElts; ++i) { | ||||||
2496 | if (DemandedElts[i]) { | ||||||
2497 | if (SrcZero.extractBits(Scale, i * Scale).isAllOnesValue()) | ||||||
2498 | KnownZero.setBit(i); | ||||||
2499 | if (SrcUndef.extractBits(Scale, i * Scale).isAllOnesValue()) | ||||||
2500 | KnownUndef.setBit(i); | ||||||
2501 | } | ||||||
2502 | } | ||||||
2503 | } | ||||||
2504 | break; | ||||||
2505 | } | ||||||
2506 | case ISD::BUILD_VECTOR: { | ||||||
2507 | // Check all elements and simplify any unused elements with UNDEF. | ||||||
2508 | if (!DemandedElts.isAllOnesValue()) { | ||||||
2509 | // Don't simplify BROADCASTS. | ||||||
2510 | if (llvm::any_of(Op->op_values(), | ||||||
2511 | [&](SDValue Elt) { return Op.getOperand(0) != Elt; })) { | ||||||
2512 | SmallVector<SDValue, 32> Ops(Op->op_begin(), Op->op_end()); | ||||||
2513 | bool Updated = false; | ||||||
2514 | for (unsigned i = 0; i != NumElts; ++i) { | ||||||
2515 | if (!DemandedElts[i] && !Ops[i].isUndef()) { | ||||||
2516 | Ops[i] = TLO.DAG.getUNDEF(Ops[0].getValueType()); | ||||||
2517 | KnownUndef.setBit(i); | ||||||
2518 | Updated = true; | ||||||
2519 | } | ||||||
2520 | } | ||||||
2521 | if (Updated) | ||||||
2522 | return TLO.CombineTo(Op, TLO.DAG.getBuildVector(VT, DL, Ops)); | ||||||
2523 | } | ||||||
2524 | } | ||||||
2525 | for (unsigned i = 0; i != NumElts; ++i) { | ||||||
2526 | SDValue SrcOp = Op.getOperand(i); | ||||||
2527 | if (SrcOp.isUndef()) { | ||||||
2528 | KnownUndef.setBit(i); | ||||||
2529 | } else if (EltSizeInBits == SrcOp.getScalarValueSizeInBits() && | ||||||
2530 | (isNullConstant(SrcOp) || isNullFPConstant(SrcOp))) { | ||||||
2531 | KnownZero.setBit(i); | ||||||
2532 | } | ||||||
2533 | } | ||||||
2534 | break; | ||||||
2535 | } | ||||||
2536 | case ISD::CONCAT_VECTORS: { | ||||||
2537 | EVT SubVT = Op.getOperand(0).getValueType(); | ||||||
2538 | unsigned NumSubVecs = Op.getNumOperands(); | ||||||
2539 | unsigned NumSubElts = SubVT.getVectorNumElements(); | ||||||
2540 | for (unsigned i = 0; i != NumSubVecs; ++i) { | ||||||
2541 | SDValue SubOp = Op.getOperand(i); | ||||||
2542 | APInt SubElts = DemandedElts.extractBits(NumSubElts, i * NumSubElts); | ||||||
2543 | APInt SubUndef, SubZero; | ||||||
2544 | if (SimplifyDemandedVectorElts(SubOp, SubElts, SubUndef, SubZero, TLO, | ||||||
2545 | Depth + 1)) | ||||||
2546 | return true; | ||||||
2547 | KnownUndef.insertBits(SubUndef, i * NumSubElts); | ||||||
2548 | KnownZero.insertBits(SubZero, i * NumSubElts); | ||||||
2549 | } | ||||||
2550 | break; | ||||||
2551 | } | ||||||
2552 | case ISD::INSERT_SUBVECTOR: { | ||||||
2553 | // Demand any elements from the subvector and the remainder from the src its | ||||||
2554 | // inserted into. | ||||||
2555 | SDValue Src = Op.getOperand(0); | ||||||
2556 | SDValue Sub = Op.getOperand(1); | ||||||
2557 | uint64_t Idx = Op.getConstantOperandVal(2); | ||||||
2558 | unsigned NumSubElts = Sub.getValueType().getVectorNumElements(); | ||||||
2559 | APInt DemandedSubElts = DemandedElts.extractBits(NumSubElts, Idx); | ||||||
2560 | APInt DemandedSrcElts = DemandedElts; | ||||||
2561 | DemandedSrcElts.insertBits(APInt::getNullValue(NumSubElts), Idx); | ||||||
2562 | |||||||
2563 | APInt SubUndef, SubZero; | ||||||
2564 | if (SimplifyDemandedVectorElts(Sub, DemandedSubElts, SubUndef, SubZero, TLO, | ||||||
2565 | Depth + 1)) | ||||||
2566 | return true; | ||||||
2567 | |||||||
2568 | // If none of the src operand elements are demanded, replace it with undef. | ||||||
2569 | if (!DemandedSrcElts && !Src.isUndef()) | ||||||
2570 | return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, | ||||||
2571 | TLO.DAG.getUNDEF(VT), Sub, | ||||||
2572 | Op.getOperand(2))); | ||||||
2573 | |||||||
2574 | if (SimplifyDemandedVectorElts(Src, DemandedSrcElts, KnownUndef, KnownZero, | ||||||
2575 | TLO, Depth + 1)) | ||||||
2576 | return true; | ||||||
2577 | KnownUndef.insertBits(SubUndef, Idx); | ||||||
2578 | KnownZero.insertBits(SubZero, Idx); | ||||||
2579 | |||||||
2580 | // Attempt to avoid multi-use ops if we don't need anything from them. | ||||||
2581 | if (!DemandedSrcElts.isAllOnesValue() || | ||||||
2582 | !DemandedSubElts.isAllOnesValue()) { | ||||||
2583 | SDValue NewSrc = SimplifyMultipleUseDemandedVectorElts( | ||||||
2584 | Src, DemandedSrcElts, TLO.DAG, Depth + 1); | ||||||
2585 | SDValue NewSub = SimplifyMultipleUseDemandedVectorElts( | ||||||
2586 | Sub, DemandedSubElts, TLO.DAG, Depth + 1); | ||||||
2587 | if (NewSrc || NewSub) { | ||||||
2588 | NewSrc = NewSrc ? NewSrc : Src; | ||||||
2589 | NewSub = NewSub ? NewSub : Sub; | ||||||
2590 | SDValue NewOp = TLO.DAG.getNode(Op.getOpcode(), SDLoc(Op), VT, NewSrc, | ||||||
2591 | NewSub, Op.getOperand(2)); | ||||||
2592 | return TLO.CombineTo(Op, NewOp); | ||||||
2593 | } | ||||||
2594 | } | ||||||
2595 | break; | ||||||
2596 | } | ||||||
2597 | case ISD::EXTRACT_SUBVECTOR: { | ||||||
2598 | // Offset the demanded elts by the subvector index. | ||||||
2599 | SDValue Src = Op.getOperand(0); | ||||||
2600 | if (Src.getValueType().isScalableVector()) | ||||||
2601 | break; | ||||||
2602 | uint64_t Idx = Op.getConstantOperandVal(1); | ||||||
2603 | unsigned NumSrcElts = Src.getValueType().getVectorNumElements(); | ||||||
2604 | APInt DemandedSrcElts = DemandedElts.zextOrSelf(NumSrcElts).shl(Idx); | ||||||
2605 | |||||||
2606 | APInt SrcUndef, SrcZero; | ||||||
2607 | if (SimplifyDemandedVectorElts(Src, DemandedSrcElts, SrcUndef, SrcZero, TLO, | ||||||
2608 | Depth + 1)) | ||||||
2609 | return true; | ||||||
2610 | KnownUndef = SrcUndef.extractBits(NumElts, Idx); | ||||||
2611 | KnownZero = SrcZero.extractBits(NumElts, Idx); | ||||||
2612 | |||||||
2613 | // Attempt to avoid multi-use ops if we don't need anything from them. | ||||||
2614 | if (!DemandedElts.isAllOnesValue()) { | ||||||
2615 | SDValue NewSrc = SimplifyMultipleUseDemandedVectorElts( | ||||||
2616 | Src, DemandedSrcElts, TLO.DAG, Depth + 1); | ||||||
2617 | if (NewSrc) { | ||||||
2618 | SDValue NewOp = TLO.DAG.getNode(Op.getOpcode(), SDLoc(Op), VT, NewSrc, | ||||||
2619 | Op.getOperand(1)); | ||||||
2620 | return TLO.CombineTo(Op, NewOp); | ||||||
2621 | } | ||||||
2622 | } | ||||||
2623 | break; | ||||||
2624 | } | ||||||
2625 | case ISD::INSERT_VECTOR_ELT: { | ||||||
2626 | SDValue Vec = Op.getOperand(0); | ||||||
2627 | SDValue Scl = Op.getOperand(1); | ||||||
2628 | auto *CIdx = dyn_cast<ConstantSDNode>(Op.getOperand(2)); | ||||||
2629 | |||||||
2630 | // For a legal, constant insertion index, if we don't need this insertion | ||||||
2631 | // then strip it, else remove it from the demanded elts. | ||||||
2632 | if (CIdx && CIdx->getAPIntValue().ult(NumElts)) { | ||||||
2633 | unsigned Idx = CIdx->getZExtValue(); | ||||||
2634 | if (!DemandedElts[Idx]) | ||||||
2635 | return TLO.CombineTo(Op, Vec); | ||||||
2636 | |||||||
2637 | APInt DemandedVecElts(DemandedElts); | ||||||
2638 | DemandedVecElts.clearBit(Idx); | ||||||
2639 | if (SimplifyDemandedVectorElts(Vec, DemandedVecElts, KnownUndef, | ||||||
2640 | KnownZero, TLO, Depth + 1)) | ||||||
2641 | return true; | ||||||
2642 | |||||||
2643 | KnownUndef.setBitVal(Idx, Scl.isUndef()); | ||||||
2644 | |||||||
2645 | KnownZero.setBitVal(Idx, isNullConstant(Scl) || isNullFPConstant(Scl)); | ||||||
2646 | break; | ||||||
2647 | } | ||||||
2648 | |||||||
2649 | APInt VecUndef, VecZero; | ||||||
2650 | if (SimplifyDemandedVectorElts(Vec, DemandedElts, VecUndef, VecZero, TLO, | ||||||
2651 | Depth + 1)) | ||||||
2652 | return true; | ||||||
2653 | // Without knowing the insertion index we can't set KnownUndef/KnownZero. | ||||||
2654 | break; | ||||||
2655 | } | ||||||
2656 | case ISD::VSELECT: { | ||||||
2657 | // Try to transform the select condition based on the current demanded | ||||||
2658 | // elements. | ||||||
2659 | // TODO: If a condition element is undef, we can choose from one arm of the | ||||||
2660 | // select (and if one arm is undef, then we can propagate that to the | ||||||
2661 | // result). | ||||||
2662 | // TODO - add support for constant vselect masks (see IR version of this). | ||||||
2663 | APInt UnusedUndef, UnusedZero; | ||||||
2664 | if (SimplifyDemandedVectorElts(Op.getOperand(0), DemandedElts, UnusedUndef, | ||||||
2665 | UnusedZero, TLO, Depth + 1)) | ||||||
2666 | return true; | ||||||
2667 | |||||||
2668 | // See if we can simplify either vselect operand. | ||||||
2669 | APInt DemandedLHS(DemandedElts); | ||||||
2670 | APInt DemandedRHS(DemandedElts); | ||||||
2671 | APInt UndefLHS, ZeroLHS; | ||||||
2672 | APInt UndefRHS, ZeroRHS; | ||||||
2673 | if (SimplifyDemandedVectorElts(Op.getOperand(1), DemandedLHS, UndefLHS, | ||||||
2674 | ZeroLHS, TLO, Depth + 1)) | ||||||
2675 | return true; | ||||||
2676 | if (SimplifyDemandedVectorElts(Op.getOperand(2), DemandedRHS, UndefRHS, | ||||||
2677 | ZeroRHS, TLO, Depth + 1)) | ||||||
2678 | return true; | ||||||
2679 | |||||||
2680 | KnownUndef = UndefLHS & UndefRHS; | ||||||
2681 | KnownZero = ZeroLHS & ZeroRHS; | ||||||
2682 | break; | ||||||
2683 | } | ||||||
2684 | case ISD::VECTOR_SHUFFLE: { | ||||||
2685 | ArrayRef<int> ShuffleMask = cast<ShuffleVectorSDNode>(Op)->getMask(); | ||||||
2686 | |||||||
2687 | // Collect demanded elements from shuffle operands.. | ||||||
2688 | APInt DemandedLHS(NumElts, 0); | ||||||
2689 | APInt DemandedRHS(NumElts, 0); | ||||||
2690 | for (unsigned i = 0; i != NumElts; ++i) { | ||||||
2691 | int M = ShuffleMask[i]; | ||||||
2692 | if (M < 0 || !DemandedElts[i]) | ||||||
2693 | continue; | ||||||
2694 | assert(0 <= M && M < (int)(2 * NumElts) && "Shuffle index out of range")((0 <= M && M < (int)(2 * NumElts) && "Shuffle index out of range" ) ? static_cast<void> (0) : __assert_fail ("0 <= M && M < (int)(2 * NumElts) && \"Shuffle index out of range\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2694, __PRETTY_FUNCTION__)); | ||||||
2695 | if (M < (int)NumElts) | ||||||
2696 | DemandedLHS.setBit(M); | ||||||
2697 | else | ||||||
2698 | DemandedRHS.setBit(M - NumElts); | ||||||
2699 | } | ||||||
2700 | |||||||
2701 | // See if we can simplify either shuffle operand. | ||||||
2702 | APInt UndefLHS, ZeroLHS; | ||||||
2703 | APInt UndefRHS, ZeroRHS; | ||||||
2704 | if (SimplifyDemandedVectorElts(Op.getOperand(0), DemandedLHS, UndefLHS, | ||||||
2705 | ZeroLHS, TLO, Depth + 1)) | ||||||
2706 | return true; | ||||||
2707 | if (SimplifyDemandedVectorElts(Op.getOperand(1), DemandedRHS, UndefRHS, | ||||||
2708 | ZeroRHS, TLO, Depth + 1)) | ||||||
2709 | return true; | ||||||
2710 | |||||||
2711 | // Simplify mask using undef elements from LHS/RHS. | ||||||
2712 | bool Updated = false; | ||||||
2713 | bool IdentityLHS = true, IdentityRHS = true; | ||||||
2714 | SmallVector<int, 32> NewMask(ShuffleMask.begin(), ShuffleMask.end()); | ||||||
2715 | for (unsigned i = 0; i != NumElts; ++i) { | ||||||
2716 | int &M = NewMask[i]; | ||||||
2717 | if (M < 0) | ||||||
2718 | continue; | ||||||
2719 | if (!DemandedElts[i] || (M < (int)NumElts && UndefLHS[M]) || | ||||||
2720 | (M >= (int)NumElts && UndefRHS[M - NumElts])) { | ||||||
2721 | Updated = true; | ||||||
2722 | M = -1; | ||||||
2723 | } | ||||||
2724 | IdentityLHS &= (M < 0) || (M == (int)i); | ||||||
2725 | IdentityRHS &= (M < 0) || ((M - NumElts) == i); | ||||||
2726 | } | ||||||
2727 | |||||||
2728 | // Update legal shuffle masks based on demanded elements if it won't reduce | ||||||
2729 | // to Identity which can cause premature removal of the shuffle mask. | ||||||
2730 | if (Updated && !IdentityLHS && !IdentityRHS && !TLO.LegalOps) { | ||||||
2731 | SDValue LegalShuffle = | ||||||
2732 | buildLegalVectorShuffle(VT, DL, Op.getOperand(0), Op.getOperand(1), | ||||||
2733 | NewMask, TLO.DAG); | ||||||
2734 | if (LegalShuffle) | ||||||
2735 | return TLO.CombineTo(Op, LegalShuffle); | ||||||
2736 | } | ||||||
2737 | |||||||
2738 | // Propagate undef/zero elements from LHS/RHS. | ||||||
2739 | for (unsigned i = 0; i != NumElts; ++i) { | ||||||
2740 | int M = ShuffleMask[i]; | ||||||
2741 | if (M < 0) { | ||||||
2742 | KnownUndef.setBit(i); | ||||||
2743 | } else if (M < (int)NumElts) { | ||||||
2744 | if (UndefLHS[M]) | ||||||
2745 | KnownUndef.setBit(i); | ||||||
2746 | if (ZeroLHS[M]) | ||||||
2747 | KnownZero.setBit(i); | ||||||
2748 | } else { | ||||||
2749 | if (UndefRHS[M - NumElts]) | ||||||
2750 | KnownUndef.setBit(i); | ||||||
2751 | if (ZeroRHS[M - NumElts]) | ||||||
2752 | KnownZero.setBit(i); | ||||||
2753 | } | ||||||
2754 | } | ||||||
2755 | break; | ||||||
2756 | } | ||||||
2757 | case ISD::ANY_EXTEND_VECTOR_INREG: | ||||||
2758 | case ISD::SIGN_EXTEND_VECTOR_INREG: | ||||||
2759 | case ISD::ZERO_EXTEND_VECTOR_INREG: { | ||||||
2760 | APInt SrcUndef, SrcZero; | ||||||
2761 | SDValue Src = Op.getOperand(0); | ||||||
2762 | unsigned NumSrcElts = Src.getValueType().getVectorNumElements(); | ||||||
2763 | APInt DemandedSrcElts = DemandedElts.zextOrSelf(NumSrcElts); | ||||||
2764 | if (SimplifyDemandedVectorElts(Src, DemandedSrcElts, SrcUndef, SrcZero, TLO, | ||||||
2765 | Depth + 1)) | ||||||
2766 | return true; | ||||||
2767 | KnownZero = SrcZero.zextOrTrunc(NumElts); | ||||||
2768 | KnownUndef = SrcUndef.zextOrTrunc(NumElts); | ||||||
2769 | |||||||
2770 | if (Op.getOpcode() == ISD::ANY_EXTEND_VECTOR_INREG && | ||||||
2771 | Op.getValueSizeInBits() == Src.getValueSizeInBits() && | ||||||
2772 | DemandedSrcElts == 1 && TLO.DAG.getDataLayout().isLittleEndian()) { | ||||||
2773 | // aext - if we just need the bottom element then we can bitcast. | ||||||
2774 | return TLO.CombineTo(Op, TLO.DAG.getBitcast(VT, Src)); | ||||||
2775 | } | ||||||
2776 | |||||||
2777 | if (Op.getOpcode() == ISD::ZERO_EXTEND_VECTOR_INREG) { | ||||||
2778 | // zext(undef) upper bits are guaranteed to be zero. | ||||||
2779 | if (DemandedElts.isSubsetOf(KnownUndef)) | ||||||
2780 | return TLO.CombineTo(Op, TLO.DAG.getConstant(0, SDLoc(Op), VT)); | ||||||
2781 | KnownUndef.clearAllBits(); | ||||||
2782 | } | ||||||
2783 | break; | ||||||
2784 | } | ||||||
2785 | |||||||
2786 | // TODO: There are more binop opcodes that could be handled here - MIN, | ||||||
2787 | // MAX, saturated math, etc. | ||||||
2788 | case ISD::OR: | ||||||
2789 | case ISD::XOR: | ||||||
2790 | case ISD::ADD: | ||||||
2791 | case ISD::SUB: | ||||||
2792 | case ISD::FADD: | ||||||
2793 | case ISD::FSUB: | ||||||
2794 | case ISD::FMUL: | ||||||
2795 | case ISD::FDIV: | ||||||
2796 | case ISD::FREM: { | ||||||
2797 | SDValue Op0 = Op.getOperand(0); | ||||||
2798 | SDValue Op1 = Op.getOperand(1); | ||||||
2799 | |||||||
2800 | APInt UndefRHS, ZeroRHS; | ||||||
2801 | if (SimplifyDemandedVectorElts(Op1, DemandedElts, UndefRHS, ZeroRHS, TLO, | ||||||
2802 | Depth + 1)) | ||||||
2803 | return true; | ||||||
2804 | APInt UndefLHS, ZeroLHS; | ||||||
2805 | if (SimplifyDemandedVectorElts(Op0, DemandedElts, UndefLHS, ZeroLHS, TLO, | ||||||
2806 | Depth + 1)) | ||||||
2807 | return true; | ||||||
2808 | |||||||
2809 | KnownZero = ZeroLHS & ZeroRHS; | ||||||
2810 | KnownUndef = getKnownUndefForVectorBinop(Op, TLO.DAG, UndefLHS, UndefRHS); | ||||||
2811 | |||||||
2812 | // Attempt to avoid multi-use ops if we don't need anything from them. | ||||||
2813 | // TODO - use KnownUndef to relax the demandedelts? | ||||||
2814 | if (!DemandedElts.isAllOnesValue()) | ||||||
2815 | if (SimplifyDemandedVectorEltsBinOp(Op0, Op1)) | ||||||
2816 | return true; | ||||||
2817 | break; | ||||||
2818 | } | ||||||
2819 | case ISD::SHL: | ||||||
2820 | case ISD::SRL: | ||||||
2821 | case ISD::SRA: | ||||||
2822 | case ISD::ROTL: | ||||||
2823 | case ISD::ROTR: { | ||||||
2824 | SDValue Op0 = Op.getOperand(0); | ||||||
2825 | SDValue Op1 = Op.getOperand(1); | ||||||
2826 | |||||||
2827 | APInt UndefRHS, ZeroRHS; | ||||||
2828 | if (SimplifyDemandedVectorElts(Op1, DemandedElts, UndefRHS, ZeroRHS, TLO, | ||||||
2829 | Depth + 1)) | ||||||
2830 | return true; | ||||||
2831 | APInt UndefLHS, ZeroLHS; | ||||||
2832 | if (SimplifyDemandedVectorElts(Op0, DemandedElts, UndefLHS, ZeroLHS, TLO, | ||||||
2833 | Depth + 1)) | ||||||
2834 | return true; | ||||||
2835 | |||||||
2836 | KnownZero = ZeroLHS; | ||||||
2837 | KnownUndef = UndefLHS & UndefRHS; // TODO: use getKnownUndefForVectorBinop? | ||||||
2838 | |||||||
2839 | // Attempt to avoid multi-use ops if we don't need anything from them. | ||||||
2840 | // TODO - use KnownUndef to relax the demandedelts? | ||||||
2841 | if (!DemandedElts.isAllOnesValue()) | ||||||
2842 | if (SimplifyDemandedVectorEltsBinOp(Op0, Op1)) | ||||||
2843 | return true; | ||||||
2844 | break; | ||||||
2845 | } | ||||||
2846 | case ISD::MUL: | ||||||
2847 | case ISD::AND: { | ||||||
2848 | SDValue Op0 = Op.getOperand(0); | ||||||
2849 | SDValue Op1 = Op.getOperand(1); | ||||||
2850 | |||||||
2851 | APInt SrcUndef, SrcZero; | ||||||
2852 | if (SimplifyDemandedVectorElts(Op1, DemandedElts, SrcUndef, SrcZero, TLO, | ||||||
2853 | Depth + 1)) | ||||||
2854 | return true; | ||||||
2855 | if (SimplifyDemandedVectorElts(Op0, DemandedElts, KnownUndef, KnownZero, | ||||||
2856 | TLO, Depth + 1)) | ||||||
2857 | return true; | ||||||
2858 | |||||||
2859 | // If either side has a zero element, then the result element is zero, even | ||||||
2860 | // if the other is an UNDEF. | ||||||
2861 | // TODO: Extend getKnownUndefForVectorBinop to also deal with known zeros | ||||||
2862 | // and then handle 'and' nodes with the rest of the binop opcodes. | ||||||
2863 | KnownZero |= SrcZero; | ||||||
2864 | KnownUndef &= SrcUndef; | ||||||
2865 | KnownUndef &= ~KnownZero; | ||||||
2866 | |||||||
2867 | // Attempt to avoid multi-use ops if we don't need anything from them. | ||||||
2868 | // TODO - use KnownUndef to relax the demandedelts? | ||||||
2869 | if (!DemandedElts.isAllOnesValue()) | ||||||
2870 | if (SimplifyDemandedVectorEltsBinOp(Op0, Op1)) | ||||||
2871 | return true; | ||||||
2872 | break; | ||||||
2873 | } | ||||||
2874 | case ISD::TRUNCATE: | ||||||
2875 | case ISD::SIGN_EXTEND: | ||||||
2876 | case ISD::ZERO_EXTEND: | ||||||
2877 | if (SimplifyDemandedVectorElts(Op.getOperand(0), DemandedElts, KnownUndef, | ||||||
2878 | KnownZero, TLO, Depth + 1)) | ||||||
2879 | return true; | ||||||
2880 | |||||||
2881 | if (Op.getOpcode() == ISD::ZERO_EXTEND) { | ||||||
2882 | // zext(undef) upper bits are guaranteed to be zero. | ||||||
2883 | if (DemandedElts.isSubsetOf(KnownUndef)) | ||||||
2884 | return TLO.CombineTo(Op, TLO.DAG.getConstant(0, SDLoc(Op), VT)); | ||||||
2885 | KnownUndef.clearAllBits(); | ||||||
2886 | } | ||||||
2887 | break; | ||||||
2888 | default: { | ||||||
2889 | if (Op.getOpcode() >= ISD::BUILTIN_OP_END) { | ||||||
2890 | if (SimplifyDemandedVectorEltsForTargetNode(Op, DemandedElts, KnownUndef, | ||||||
2891 | KnownZero, TLO, Depth)) | ||||||
2892 | return true; | ||||||
2893 | } else { | ||||||
2894 | KnownBits Known; | ||||||
2895 | APInt DemandedBits = APInt::getAllOnesValue(EltSizeInBits); | ||||||
2896 | if (SimplifyDemandedBits(Op, DemandedBits, OriginalDemandedElts, Known, | ||||||
2897 | TLO, Depth, AssumeSingleUse)) | ||||||
2898 | return true; | ||||||
2899 | } | ||||||
2900 | break; | ||||||
2901 | } | ||||||
2902 | } | ||||||
2903 | assert((KnownUndef & KnownZero) == 0 && "Elements flagged as undef AND zero")(((KnownUndef & KnownZero) == 0 && "Elements flagged as undef AND zero" ) ? static_cast<void> (0) : __assert_fail ("(KnownUndef & KnownZero) == 0 && \"Elements flagged as undef AND zero\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2903, __PRETTY_FUNCTION__)); | ||||||
2904 | |||||||
2905 | // Constant fold all undef cases. | ||||||
2906 | // TODO: Handle zero cases as well. | ||||||
2907 | if (DemandedElts.isSubsetOf(KnownUndef)) | ||||||
2908 | return TLO.CombineTo(Op, TLO.DAG.getUNDEF(VT)); | ||||||
2909 | |||||||
2910 | return false; | ||||||
2911 | } | ||||||
2912 | |||||||
2913 | /// Determine which of the bits specified in Mask are known to be either zero or | ||||||
2914 | /// one and return them in the Known. | ||||||
2915 | void TargetLowering::computeKnownBitsForTargetNode(const SDValue Op, | ||||||
2916 | KnownBits &Known, | ||||||
2917 | const APInt &DemandedElts, | ||||||
2918 | const SelectionDAG &DAG, | ||||||
2919 | unsigned Depth) const { | ||||||
2920 | assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use MaskedValueIsZero if you don't know whether Op" " is a target node!") ? static_cast<void> (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use MaskedValueIsZero if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2925, __PRETTY_FUNCTION__)) | ||||||
2921 | Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use MaskedValueIsZero if you don't know whether Op" " is a target node!") ? static_cast<void> (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use MaskedValueIsZero if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2925, __PRETTY_FUNCTION__)) | ||||||
2922 | Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use MaskedValueIsZero if you don't know whether Op" " is a target node!") ? static_cast<void> (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use MaskedValueIsZero if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2925, __PRETTY_FUNCTION__)) | ||||||
2923 | Op.getOpcode() == ISD::INTRINSIC_VOID) &&(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use MaskedValueIsZero if you don't know whether Op" " is a target node!") ? static_cast<void> (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use MaskedValueIsZero if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2925, __PRETTY_FUNCTION__)) | ||||||
2924 | "Should use MaskedValueIsZero if you don't know whether Op"(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use MaskedValueIsZero if you don't know whether Op" " is a target node!") ? static_cast<void> (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use MaskedValueIsZero if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2925, __PRETTY_FUNCTION__)) | ||||||
2925 | " is a target node!")(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use MaskedValueIsZero if you don't know whether Op" " is a target node!") ? static_cast<void> (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use MaskedValueIsZero if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2925, __PRETTY_FUNCTION__)); | ||||||
2926 | Known.resetAll(); | ||||||
2927 | } | ||||||
2928 | |||||||
2929 | void TargetLowering::computeKnownBitsForTargetInstr( | ||||||
2930 | GISelKnownBits &Analysis, Register R, KnownBits &Known, | ||||||
2931 | const APInt &DemandedElts, const MachineRegisterInfo &MRI, | ||||||
2932 | unsigned Depth) const { | ||||||
2933 | Known.resetAll(); | ||||||
2934 | } | ||||||
2935 | |||||||
2936 | void TargetLowering::computeKnownBitsForFrameIndex( | ||||||
2937 | const int FrameIdx, KnownBits &Known, const MachineFunction &MF) const { | ||||||
2938 | // The low bits are known zero if the pointer is aligned. | ||||||
2939 | Known.Zero.setLowBits(Log2(MF.getFrameInfo().getObjectAlign(FrameIdx))); | ||||||
2940 | } | ||||||
2941 | |||||||
2942 | Align TargetLowering::computeKnownAlignForTargetInstr( | ||||||
2943 | GISelKnownBits &Analysis, Register R, const MachineRegisterInfo &MRI, | ||||||
2944 | unsigned Depth) const { | ||||||
2945 | return Align(1); | ||||||
2946 | } | ||||||
2947 | |||||||
2948 | /// This method can be implemented by targets that want to expose additional | ||||||
2949 | /// information about sign bits to the DAG Combiner. | ||||||
2950 | unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op, | ||||||
2951 | const APInt &, | ||||||
2952 | const SelectionDAG &, | ||||||
2953 | unsigned Depth) const { | ||||||
2954 | assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use ComputeNumSignBits if you don't know whether Op" " is a target node!") ? static_cast<void> (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use ComputeNumSignBits if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2959, __PRETTY_FUNCTION__)) | ||||||
2955 | Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use ComputeNumSignBits if you don't know whether Op" " is a target node!") ? static_cast<void> (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use ComputeNumSignBits if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2959, __PRETTY_FUNCTION__)) | ||||||
2956 | Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use ComputeNumSignBits if you don't know whether Op" " is a target node!") ? static_cast<void> (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use ComputeNumSignBits if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2959, __PRETTY_FUNCTION__)) | ||||||
2957 | Op.getOpcode() == ISD::INTRINSIC_VOID) &&(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use ComputeNumSignBits if you don't know whether Op" " is a target node!") ? static_cast<void> (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use ComputeNumSignBits if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2959, __PRETTY_FUNCTION__)) | ||||||
2958 | "Should use ComputeNumSignBits if you don't know whether Op"(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use ComputeNumSignBits if you don't know whether Op" " is a target node!") ? static_cast<void> (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use ComputeNumSignBits if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2959, __PRETTY_FUNCTION__)) | ||||||
2959 | " is a target node!")(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use ComputeNumSignBits if you don't know whether Op" " is a target node!") ? static_cast<void> (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use ComputeNumSignBits if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2959, __PRETTY_FUNCTION__)); | ||||||
2960 | return 1; | ||||||
2961 | } | ||||||
2962 | |||||||
2963 | unsigned TargetLowering::computeNumSignBitsForTargetInstr( | ||||||
2964 | GISelKnownBits &Analysis, Register R, const APInt &DemandedElts, | ||||||
2965 | const MachineRegisterInfo &MRI, unsigned Depth) const { | ||||||
2966 | return 1; | ||||||
2967 | } | ||||||
2968 | |||||||
2969 | bool TargetLowering::SimplifyDemandedVectorEltsForTargetNode( | ||||||
2970 | SDValue Op, const APInt &DemandedElts, APInt &KnownUndef, APInt &KnownZero, | ||||||
2971 | TargetLoweringOpt &TLO, unsigned Depth) const { | ||||||
2972 | assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use SimplifyDemandedVectorElts if you don't know whether Op" " is a target node!") ? static_cast<void> (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use SimplifyDemandedVectorElts if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2977, __PRETTY_FUNCTION__)) | ||||||
2973 | Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use SimplifyDemandedVectorElts if you don't know whether Op" " is a target node!") ? static_cast<void> (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use SimplifyDemandedVectorElts if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2977, __PRETTY_FUNCTION__)) | ||||||
2974 | Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use SimplifyDemandedVectorElts if you don't know whether Op" " is a target node!") ? static_cast<void> (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use SimplifyDemandedVectorElts if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2977, __PRETTY_FUNCTION__)) | ||||||
2975 | Op.getOpcode() == ISD::INTRINSIC_VOID) &&(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use SimplifyDemandedVectorElts if you don't know whether Op" " is a target node!") ? static_cast<void> (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use SimplifyDemandedVectorElts if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2977, __PRETTY_FUNCTION__)) | ||||||
2976 | "Should use SimplifyDemandedVectorElts if you don't know whether Op"(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use SimplifyDemandedVectorElts if you don't know whether Op" " is a target node!") ? static_cast<void> (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use SimplifyDemandedVectorElts if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2977, __PRETTY_FUNCTION__)) | ||||||
2977 | " is a target node!")(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use SimplifyDemandedVectorElts if you don't know whether Op" " is a target node!") ? static_cast<void> (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use SimplifyDemandedVectorElts if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2977, __PRETTY_FUNCTION__)); | ||||||
2978 | return false; | ||||||
2979 | } | ||||||
2980 | |||||||
2981 | bool TargetLowering::SimplifyDemandedBitsForTargetNode( | ||||||
2982 | SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, | ||||||
2983 | KnownBits &Known, TargetLoweringOpt &TLO, unsigned Depth) const { | ||||||
2984 | assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use SimplifyDemandedBits if you don't know whether Op" " is a target node!") ? static_cast<void> (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use SimplifyDemandedBits if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2989, __PRETTY_FUNCTION__)) | ||||||
2985 | Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use SimplifyDemandedBits if you don't know whether Op" " is a target node!") ? static_cast<void> (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use SimplifyDemandedBits if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2989, __PRETTY_FUNCTION__)) | ||||||
2986 | Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use SimplifyDemandedBits if you don't know whether Op" " is a target node!") ? static_cast<void> (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use SimplifyDemandedBits if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2989, __PRETTY_FUNCTION__)) | ||||||
2987 | Op.getOpcode() == ISD::INTRINSIC_VOID) &&(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use SimplifyDemandedBits if you don't know whether Op" " is a target node!") ? static_cast<void> (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use SimplifyDemandedBits if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2989, __PRETTY_FUNCTION__)) | ||||||
2988 | "Should use SimplifyDemandedBits if you don't know whether Op"(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use SimplifyDemandedBits if you don't know whether Op" " is a target node!") ? static_cast<void> (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use SimplifyDemandedBits if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2989, __PRETTY_FUNCTION__)) | ||||||
2989 | " is a target node!")(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use SimplifyDemandedBits if you don't know whether Op" " is a target node!") ? static_cast<void> (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use SimplifyDemandedBits if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2989, __PRETTY_FUNCTION__)); | ||||||
2990 | computeKnownBitsForTargetNode(Op, Known, DemandedElts, TLO.DAG, Depth); | ||||||
2991 | return false; | ||||||
2992 | } | ||||||
2993 | |||||||
2994 | SDValue TargetLowering::SimplifyMultipleUseDemandedBitsForTargetNode( | ||||||
2995 | SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, | ||||||
2996 | SelectionDAG &DAG, unsigned Depth) const { | ||||||
2997 | assert((((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use SimplifyMultipleUseDemandedBits if you don't know whether Op" " is a target node!") ? static_cast<void> (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use SimplifyMultipleUseDemandedBits if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 3003, __PRETTY_FUNCTION__)) | ||||||
2998 | (Op.getOpcode() >= ISD::BUILTIN_OP_END ||(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use SimplifyMultipleUseDemandedBits if you don't know whether Op" " is a target node!") ? static_cast<void> (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use SimplifyMultipleUseDemandedBits if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 3003, __PRETTY_FUNCTION__)) | ||||||
2999 | Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use SimplifyMultipleUseDemandedBits if you don't know whether Op" " is a target node!") ? static_cast<void> (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use SimplifyMultipleUseDemandedBits if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 3003, __PRETTY_FUNCTION__)) | ||||||
3000 | Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use SimplifyMultipleUseDemandedBits if you don't know whether Op" " is a target node!") ? static_cast<void> (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use SimplifyMultipleUseDemandedBits if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 3003, __PRETTY_FUNCTION__)) | ||||||
3001 | Op.getOpcode() == ISD::INTRINSIC_VOID) &&(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use SimplifyMultipleUseDemandedBits if you don't know whether Op" " is a target node!") ? static_cast<void> (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use SimplifyMultipleUseDemandedBits if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 3003, __PRETTY_FUNCTION__)) | ||||||
3002 | "Should use SimplifyMultipleUseDemandedBits if you don't know whether Op"(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use SimplifyMultipleUseDemandedBits if you don't know whether Op" " is a target node!") ? static_cast<void> (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use SimplifyMultipleUseDemandedBits if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 3003, __PRETTY_FUNCTION__)) | ||||||
3003 | " is a target node!")(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use SimplifyMultipleUseDemandedBits if you don't know whether Op" " is a target node!") ? static_cast<void> (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use SimplifyMultipleUseDemandedBits if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 3003, __PRETTY_FUNCTION__)); | ||||||
3004 | return SDValue(); | ||||||
3005 | } | ||||||
3006 | |||||||
3007 | SDValue | ||||||
3008 | TargetLowering::buildLegalVectorShuffle(EVT VT, const SDLoc &DL, SDValue N0, | ||||||
3009 | SDValue N1, MutableArrayRef<int> Mask, | ||||||
3010 | SelectionDAG &DAG) const { | ||||||
3011 | bool LegalMask = isShuffleMaskLegal(Mask, VT); | ||||||
3012 | if (!LegalMask) { | ||||||
3013 | std::swap(N0, N1); | ||||||
3014 | ShuffleVectorSDNode::commuteMask(Mask); | ||||||
3015 | LegalMask = isShuffleMaskLegal(Mask, VT); | ||||||
3016 | } | ||||||
3017 | |||||||
3018 | if (!LegalMask) | ||||||
3019 | return SDValue(); | ||||||
3020 | |||||||
3021 | return DAG.getVectorShuffle(VT, DL, N0, N1, Mask); | ||||||
3022 | } | ||||||
3023 | |||||||
3024 | const Constant *TargetLowering::getTargetConstantFromLoad(LoadSDNode*) const { | ||||||
3025 | return nullptr; | ||||||
3026 | } | ||||||
3027 | |||||||
3028 | bool TargetLowering::isKnownNeverNaNForTargetNode(SDValue Op, | ||||||
3029 | const SelectionDAG &DAG, | ||||||
3030 | bool SNaN, | ||||||
3031 | unsigned Depth) const { | ||||||
3032 | assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use isKnownNeverNaN if you don't know whether Op" " is a target node!") ? static_cast<void> (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use isKnownNeverNaN if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 3037, __PRETTY_FUNCTION__)) | ||||||
3033 | Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use isKnownNeverNaN if you don't know whether Op" " is a target node!") ? static_cast<void> (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use isKnownNeverNaN if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 3037, __PRETTY_FUNCTION__)) | ||||||
3034 | Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use isKnownNeverNaN if you don't know whether Op" " is a target node!") ? static_cast<void> (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use isKnownNeverNaN if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 3037, __PRETTY_FUNCTION__)) | ||||||
3035 | Op.getOpcode() == ISD::INTRINSIC_VOID) &&(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use isKnownNeverNaN if you don't know whether Op" " is a target node!") ? static_cast<void> (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use isKnownNeverNaN if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 3037, __PRETTY_FUNCTION__)) | ||||||
3036 | "Should use isKnownNeverNaN if you don't know whether Op"(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use isKnownNeverNaN if you don't know whether Op" " is a target node!") ? static_cast<void> (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use isKnownNeverNaN if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 3037, __PRETTY_FUNCTION__)) | ||||||
3037 | " is a target node!")(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use isKnownNeverNaN if you don't know whether Op" " is a target node!") ? static_cast<void> (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use isKnownNeverNaN if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 3037, __PRETTY_FUNCTION__)); | ||||||
3038 | return false; | ||||||
3039 | } | ||||||
3040 | |||||||
3041 | // FIXME: Ideally, this would use ISD::isConstantSplatVector(), but that must | ||||||
3042 | // work with truncating build vectors and vectors with elements of less than | ||||||
3043 | // 8 bits. | ||||||
3044 | bool TargetLowering::isConstTrueVal(const SDNode *N) const { | ||||||
3045 | if (!N) | ||||||
3046 | return false; | ||||||
3047 | |||||||
3048 | APInt CVal; | ||||||
3049 | if (auto *CN = dyn_cast<ConstantSDNode>(N)) { | ||||||
3050 | CVal = CN->getAPIntValue(); | ||||||
3051 | } else if (auto *BV = dyn_cast<BuildVectorSDNode>(N)) { | ||||||
3052 | auto *CN = BV->getConstantSplatNode(); | ||||||
3053 | if (!CN) | ||||||
3054 | return false; | ||||||
3055 | |||||||
3056 | // If this is a truncating build vector, truncate the splat value. | ||||||
3057 | // Otherwise, we may fail to match the expected values below. | ||||||
3058 | unsigned BVEltWidth = BV->getValueType(0).getScalarSizeInBits(); | ||||||
3059 | CVal = CN->getAPIntValue(); | ||||||
3060 | if (BVEltWidth < CVal.getBitWidth()) | ||||||
3061 | CVal = CVal.trunc(BVEltWidth); | ||||||
3062 | } else { | ||||||
3063 | return false; | ||||||
3064 | } | ||||||
3065 | |||||||
3066 | switch (getBooleanContents(N->getValueType(0))) { | ||||||
3067 | case UndefinedBooleanContent: | ||||||
3068 | return CVal[0]; | ||||||
3069 | case ZeroOrOneBooleanContent: | ||||||
3070 | return CVal.isOneValue(); | ||||||
3071 | case ZeroOrNegativeOneBooleanContent: | ||||||
3072 | return CVal.isAllOnesValue(); | ||||||
3073 | } | ||||||
3074 | |||||||
3075 | llvm_unreachable("Invalid boolean contents")::llvm::llvm_unreachable_internal("Invalid boolean contents", "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 3075); | ||||||
3076 | } | ||||||
3077 | |||||||
3078 | bool TargetLowering::isConstFalseVal(const SDNode *N) const { | ||||||
3079 | if (!N) | ||||||
3080 | return false; | ||||||
3081 | |||||||
3082 | const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N); | ||||||
3083 | if (!CN) { | ||||||
3084 | const BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N); | ||||||
3085 | if (!BV) | ||||||
3086 | return false; | ||||||
3087 | |||||||
3088 | // Only interested in constant splats, we don't care about undef | ||||||
3089 | // elements in identifying boolean constants and getConstantSplatNode | ||||||
3090 | // returns NULL if all ops are undef; | ||||||
3091 | CN = BV->getConstantSplatNode(); | ||||||
3092 | if (!CN) | ||||||
3093 | return false; | ||||||
3094 | } | ||||||
3095 | |||||||
3096 | if (getBooleanContents(N->getValueType(0)) == UndefinedBooleanContent) | ||||||
3097 | return !CN->getAPIntValue()[0]; | ||||||
3098 | |||||||
3099 | return CN->isNullValue(); | ||||||
3100 | } | ||||||
3101 | |||||||
3102 | bool TargetLowering::isExtendedTrueVal(const ConstantSDNode *N, EVT VT, | ||||||
3103 | bool SExt) const { | ||||||
3104 | if (VT == MVT::i1) | ||||||
3105 | return N->isOne(); | ||||||
3106 | |||||||
3107 | TargetLowering::BooleanContent Cnt = getBooleanContents(VT); | ||||||
3108 | switch (Cnt) { | ||||||
3109 | case TargetLowering::ZeroOrOneBooleanContent: | ||||||
3110 | // An extended value of 1 is always true, unless its original type is i1, | ||||||
3111 | // in which case it will be sign extended to -1. | ||||||
3112 | return (N->isOne() && !SExt) || (SExt && (N->getValueType(0) != MVT::i1)); | ||||||
3113 | case TargetLowering::UndefinedBooleanContent: | ||||||
3114 | case TargetLowering::ZeroOrNegativeOneBooleanContent: | ||||||
3115 | return N->isAllOnesValue() && SExt; | ||||||
3116 | } | ||||||
3117 | llvm_unreachable("Unexpected enumeration.")::llvm::llvm_unreachable_internal("Unexpected enumeration.", "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 3117); | ||||||
3118 | } | ||||||
3119 | |||||||
3120 | /// This helper function of SimplifySetCC tries to optimize the comparison when | ||||||
3121 | /// either operand of the SetCC node is a bitwise-and instruction. | ||||||
3122 | SDValue TargetLowering::foldSetCCWithAnd(EVT VT, SDValue N0, SDValue N1, | ||||||
3123 | ISD::CondCode Cond, const SDLoc &DL, | ||||||
3124 | DAGCombinerInfo &DCI) const { | ||||||
3125 | // Match these patterns in any of their permutations: | ||||||
3126 | // (X & Y) == Y | ||||||
3127 | // (X & Y) != Y | ||||||
3128 | if (N1.getOpcode() == ISD::AND && N0.getOpcode() != ISD::AND) | ||||||
3129 | std::swap(N0, N1); | ||||||
3130 | |||||||
3131 | EVT OpVT = N0.getValueType(); | ||||||
3132 | if (N0.getOpcode() != ISD::AND || !OpVT.isInteger() || | ||||||
3133 | (Cond != ISD::SETEQ && Cond != ISD::SETNE)) | ||||||
3134 | return SDValue(); | ||||||
3135 | |||||||
3136 | SDValue X, Y; | ||||||
3137 | if (N0.getOperand(0) == N1) { | ||||||
3138 | X = N0.getOperand(1); | ||||||
3139 | Y = N0.getOperand(0); | ||||||
3140 | } else if (N0.getOperand(1) == N1) { | ||||||
3141 | X = N0.getOperand(0); | ||||||
3142 | Y = N0.getOperand(1); | ||||||
3143 | } else { | ||||||
3144 | return SDValue(); | ||||||
3145 | } | ||||||
3146 | |||||||
3147 | SelectionDAG &DAG = DCI.DAG; | ||||||
3148 | SDValue Zero = DAG.getConstant(0, DL, OpVT); | ||||||
3149 | if (DAG.isKnownToBeAPowerOfTwo(Y)) { | ||||||
3150 | // Simplify X & Y == Y to X & Y != 0 if Y has exactly one bit set. | ||||||
3151 | // Note that where Y is variable and is known to have at most one bit set | ||||||
3152 | // (for example, if it is Z & 1) we cannot do this; the expressions are not | ||||||
3153 | // equivalent when Y == 0. | ||||||
3154 | assert(OpVT.isInteger())((OpVT.isInteger()) ? static_cast<void> (0) : __assert_fail ("OpVT.isInteger()", "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 3154, __PRETTY_FUNCTION__)); | ||||||
3155 | Cond = ISD::getSetCCInverse(Cond, OpVT); | ||||||
3156 | if (DCI.isBeforeLegalizeOps() || | ||||||
3157 | isCondCodeLegal(Cond, N0.getSimpleValueType())) | ||||||
3158 | return DAG.getSetCC(DL, VT, N0, Zero, Cond); | ||||||
3159 | } else if (N0.hasOneUse() && hasAndNotCompare(Y)) { | ||||||
3160 | // If the target supports an 'and-not' or 'and-complement' logic operation, | ||||||
3161 | // try to use that to make a comparison operation more efficient. | ||||||
3162 | // But don't do this transform if the mask is a single bit because there are | ||||||
3163 | // more efficient ways to deal with that case (for example, 'bt' on x86 or | ||||||
3164 | // 'rlwinm' on PPC). | ||||||
3165 | |||||||
3166 | // Bail out if the compare operand that we want to turn into a zero is | ||||||
3167 | // already a zero (otherwise, infinite loop). | ||||||
3168 | auto *YConst = dyn_cast<ConstantSDNode>(Y); | ||||||
3169 | if (YConst && YConst->isNullValue()) | ||||||
3170 | return SDValue(); | ||||||
3171 | |||||||
3172 | // Transform this into: ~X & Y == 0. | ||||||
3173 | SDValue NotX = DAG.getNOT(SDLoc(X), X, OpVT); | ||||||
3174 | SDValue NewAnd = DAG.getNode(ISD::AND, SDLoc(N0), OpVT, NotX, Y); | ||||||
3175 | return DAG.getSetCC(DL, VT, NewAnd, Zero, Cond); | ||||||
3176 | } | ||||||
3177 | |||||||
3178 | return SDValue(); | ||||||
3179 | } | ||||||
3180 | |||||||
3181 | /// There are multiple IR patterns that could be checking whether certain | ||||||
3182 | /// truncation of a signed number would be lossy or not. The pattern which is | ||||||
3183 | /// best at IR level, may not lower optimally. Thus, we want to unfold it. | ||||||
3184 | /// We are looking for the following pattern: (KeptBits is a constant) | ||||||
3185 | /// (add %x, (1 << (KeptBits-1))) srccond (1 << KeptBits) | ||||||
3186 | /// KeptBits won't be bitwidth(x), that will be constant-folded to true/false. | ||||||
3187 | /// KeptBits also can't be 1, that would have been folded to %x dstcond 0 | ||||||
3188 | /// We will unfold it into the natural trunc+sext pattern: | ||||||
3189 | /// ((%x << C) a>> C) dstcond %x | ||||||
3190 | /// Where C = bitwidth(x) - KeptBits and C u< bitwidth(x) | ||||||
3191 | SDValue TargetLowering::optimizeSetCCOfSignedTruncationCheck( | ||||||
3192 | EVT SCCVT, SDValue N0, SDValue N1, ISD::CondCode Cond, DAGCombinerInfo &DCI, | ||||||
3193 | const SDLoc &DL) const { | ||||||
3194 | // We must be comparing with a constant. | ||||||
3195 | ConstantSDNode *C1; | ||||||
3196 | if (!(C1 = dyn_cast<ConstantSDNode>(N1))) | ||||||
3197 | return SDValue(); | ||||||
3198 | |||||||
3199 | // N0 should be: add %x, (1 << (KeptBits-1)) | ||||||
3200 | if (N0->getOpcode() != ISD::ADD) | ||||||
3201 | return SDValue(); | ||||||
3202 | |||||||
3203 | // And we must be 'add'ing a constant. | ||||||
3204 | ConstantSDNode *C01; | ||||||
3205 | if (!(C01 = dyn_cast<ConstantSDNode>(N0->getOperand(1)))) | ||||||
3206 | return SDValue(); | ||||||
3207 | |||||||
3208 | SDValue X = N0->getOperand(0); | ||||||
3209 | EVT XVT = X.getValueType(); | ||||||
3210 | |||||||
3211 | // Validate constants ... | ||||||
3212 | |||||||
3213 | APInt I1 = C1->getAPIntValue(); | ||||||
3214 | |||||||
3215 | ISD::CondCode NewCond; | ||||||
3216 | if (Cond == ISD::CondCode::SETULT) { | ||||||
3217 | NewCond = ISD::CondCode::SETEQ; | ||||||
3218 | } else if (Cond == ISD::CondCode::SETULE) { | ||||||
3219 | NewCond = ISD::CondCode::SETEQ; | ||||||
3220 | // But need to 'canonicalize' the constant. | ||||||
3221 | I1 += 1; | ||||||
3222 | } else if (Cond == ISD::CondCode::SETUGT) { | ||||||
3223 | NewCond = ISD::CondCode::SETNE; | ||||||
3224 | // But need to 'canonicalize' the constant. | ||||||
3225 | I1 += 1; | ||||||
3226 | } else if (Cond == ISD::CondCode::SETUGE) { | ||||||
3227 | NewCond = ISD::CondCode::SETNE; | ||||||
3228 | } else | ||||||
3229 | return SDValue(); | ||||||
3230 | |||||||
3231 | APInt I01 = C01->getAPIntValue(); | ||||||
3232 | |||||||
3233 | auto checkConstants = [&I1, &I01]() -> bool { | ||||||
3234 | // Both of them must be power-of-two, and the constant from setcc is bigger. | ||||||
3235 | return I1.ugt(I01) && I1.isPowerOf2() && I01.isPowerOf2(); | ||||||
3236 | }; | ||||||
3237 | |||||||
3238 | if (checkConstants()) { | ||||||
3239 | // Great, e.g. got icmp ult i16 (add i16 %x, 128), 256 | ||||||
3240 | } else { | ||||||
3241 | // What if we invert constants? (and the target predicate) | ||||||
3242 | I1.negate(); | ||||||
3243 | I01.negate(); | ||||||
3244 | assert(XVT.isInteger())((XVT.isInteger()) ? static_cast<void> (0) : __assert_fail ("XVT.isInteger()", "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 3244, __PRETTY_FUNCTION__)); | ||||||
3245 | NewCond = getSetCCInverse(NewCond, XVT); | ||||||
3246 | if (!checkConstants()) | ||||||
3247 | return SDValue(); | ||||||
3248 | // Great, e.g. got icmp uge i16 (add i16 %x, -128), -256 | ||||||
3249 | } | ||||||
3250 | |||||||
3251 | // They are power-of-two, so which bit is set? | ||||||
3252 | const unsigned KeptBits = I1.logBase2(); | ||||||
3253 | const unsigned KeptBitsMinusOne = I01.logBase2(); | ||||||
3254 | |||||||
3255 | // Magic! | ||||||
3256 | if (KeptBits != (KeptBitsMinusOne + 1)) | ||||||
3257 | return SDValue(); | ||||||
3258 | assert(KeptBits > 0 && KeptBits < XVT.getSizeInBits() && "unreachable")((KeptBits > 0 && KeptBits < XVT.getSizeInBits( ) && "unreachable") ? static_cast<void> (0) : __assert_fail ("KeptBits > 0 && KeptBits < XVT.getSizeInBits() && \"unreachable\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 3258, __PRETTY_FUNCTION__)); | ||||||
3259 | |||||||
3260 | // We don't want to do this in every single case. | ||||||
3261 | SelectionDAG &DAG = DCI.DAG; | ||||||
3262 | if (!DAG.getTargetLoweringInfo().shouldTransformSignedTruncationCheck( | ||||||
3263 | XVT, KeptBits)) | ||||||
3264 | return SDValue(); | ||||||
3265 | |||||||
3266 | const unsigned MaskedBits = XVT.getSizeInBits() - KeptBits; | ||||||
3267 | assert(MaskedBits > 0 && MaskedBits < XVT.getSizeInBits() && "unreachable")((MaskedBits > 0 && MaskedBits < XVT.getSizeInBits () && "unreachable") ? static_cast<void> (0) : __assert_fail ("MaskedBits > 0 && MaskedBits < XVT.getSizeInBits() && \"unreachable\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 3267, __PRETTY_FUNCTION__)); | ||||||
3268 | |||||||
3269 | // Unfold into: ((%x << C) a>> C) cond %x | ||||||
3270 | // Where 'cond' will be either 'eq' or 'ne'. | ||||||
3271 | SDValue ShiftAmt = DAG.getConstant(MaskedBits, DL, XVT); | ||||||
3272 | SDValue T0 = DAG.getNode(ISD::SHL, DL, XVT, X, ShiftAmt); | ||||||
3273 | SDValue T1 = DAG.getNode(ISD::SRA, DL, XVT, T0, ShiftAmt); | ||||||
3274 | SDValue T2 = DAG.getSetCC(DL, SCCVT, T1, X, NewCond); | ||||||
3275 | |||||||
3276 | return T2; | ||||||
3277 | } | ||||||
3278 | |||||||
3279 | // (X & (C l>>/<< Y)) ==/!= 0 --> ((X <</l>> Y) & C) ==/!= 0 | ||||||
3280 | SDValue TargetLowering::optimizeSetCCByHoistingAndByConstFromLogicalShift( | ||||||
3281 | EVT SCCVT, SDValue N0, SDValue N1C, ISD::CondCode Cond, | ||||||
3282 | DAGCombinerInfo &DCI, const SDLoc &DL) const { | ||||||
3283 | assert(isConstOrConstSplat(N1C) &&((isConstOrConstSplat(N1C) && isConstOrConstSplat(N1C )->getAPIntValue().isNullValue() && "Should be a comparison with 0." ) ? static_cast<void> (0) : __assert_fail ("isConstOrConstSplat(N1C) && isConstOrConstSplat(N1C)->getAPIntValue().isNullValue() && \"Should be a comparison with 0.\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 3285, __PRETTY_FUNCTION__)) | ||||||
3284 | isConstOrConstSplat(N1C)->getAPIntValue().isNullValue() &&((isConstOrConstSplat(N1C) && isConstOrConstSplat(N1C )->getAPIntValue().isNullValue() && "Should be a comparison with 0." ) ? static_cast<void> (0) : __assert_fail ("isConstOrConstSplat(N1C) && isConstOrConstSplat(N1C)->getAPIntValue().isNullValue() && \"Should be a comparison with 0.\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 3285, __PRETTY_FUNCTION__)) | ||||||
3285 | "Should be a comparison with 0.")((isConstOrConstSplat(N1C) && isConstOrConstSplat(N1C )->getAPIntValue().isNullValue() && "Should be a comparison with 0." ) ? static_cast<void> (0) : __assert_fail ("isConstOrConstSplat(N1C) && isConstOrConstSplat(N1C)->getAPIntValue().isNullValue() && \"Should be a comparison with 0.\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 3285, __PRETTY_FUNCTION__)); | ||||||
3286 | assert((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&(((Cond == ISD::SETEQ || Cond == ISD::SETNE) && "Valid only for [in]equality comparisons." ) ? static_cast<void> (0) : __assert_fail ("(Cond == ISD::SETEQ || Cond == ISD::SETNE) && \"Valid only for [in]equality comparisons.\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 3287, __PRETTY_FUNCTION__)) | ||||||
3287 | "Valid only for [in]equality comparisons.")(((Cond == ISD::SETEQ || Cond == ISD::SETNE) && "Valid only for [in]equality comparisons." ) ? static_cast<void> (0) : __assert_fail ("(Cond == ISD::SETEQ || Cond == ISD::SETNE) && \"Valid only for [in]equality comparisons.\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 3287, __PRETTY_FUNCTION__)); | ||||||
3288 | |||||||
3289 | unsigned NewShiftOpcode; | ||||||
3290 | SDValue X, C, Y; | ||||||
3291 | |||||||
3292 | SelectionDAG &DAG = DCI.DAG; | ||||||
3293 | const TargetLowering &TLI = DAG.getTargetLoweringInfo(); | ||||||
3294 | |||||||
3295 | // Look for '(C l>>/<< Y)'. | ||||||
3296 | auto Match = [&NewShiftOpcode, &X, &C, &Y, &TLI, &DAG](SDValue V) { | ||||||
3297 | // The shift should be one-use. | ||||||
3298 | if (!V.hasOneUse()) | ||||||
3299 | return false; | ||||||
3300 | unsigned OldShiftOpcode = V.getOpcode(); | ||||||
3301 | switch (OldShiftOpcode) { | ||||||
3302 | case ISD::SHL: | ||||||
3303 | NewShiftOpcode = ISD::SRL; | ||||||
3304 | break; | ||||||
3305 | case ISD::SRL: | ||||||
3306 | NewShiftOpcode = ISD::SHL; | ||||||
3307 | break; | ||||||
3308 | default: | ||||||
3309 | return false; // must be a logical shift. | ||||||
3310 | } | ||||||
3311 | // We should be shifting a constant. | ||||||
3312 | // FIXME: best to use isConstantOrConstantVector(). | ||||||
3313 | C = V.getOperand(0); | ||||||
3314 | ConstantSDNode *CC = | ||||||
3315 | isConstOrConstSplat(C, /*AllowUndefs=*/true, /*AllowTruncation=*/true); | ||||||
3316 | if (!CC) | ||||||
3317 | return false; | ||||||
3318 | Y = V.getOperand(1); | ||||||
3319 | |||||||
3320 | ConstantSDNode *XC = | ||||||
3321 | isConstOrConstSplat(X, /*AllowUndefs=*/true, /*AllowTruncation=*/true); | ||||||
3322 | return TLI.shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd( | ||||||
3323 | X, XC, CC, Y, OldShiftOpcode, NewShiftOpcode, DAG); | ||||||
3324 | }; | ||||||
3325 | |||||||
3326 | // LHS of comparison should be an one-use 'and'. | ||||||
3327 | if (N0.getOpcode() != ISD::AND || !N0.hasOneUse()) | ||||||
3328 | return SDValue(); | ||||||
3329 | |||||||
3330 | X = N0.getOperand(0); | ||||||
3331 | SDValue Mask = N0.getOperand(1); | ||||||
3332 | |||||||
3333 | // 'and' is commutative! | ||||||
3334 | if (!Match(Mask)) { | ||||||
3335 | std::swap(X, Mask); | ||||||
3336 | if (!Match(Mask)) | ||||||
3337 | return SDValue(); | ||||||
3338 | } | ||||||
3339 | |||||||
3340 | EVT VT = X.getValueType(); | ||||||
3341 | |||||||
3342 | // Produce: | ||||||
3343 | // ((X 'OppositeShiftOpcode' Y) & C) Cond 0 | ||||||
3344 | SDValue T0 = DAG.getNode(NewShiftOpcode, DL, VT, X, Y); | ||||||
3345 | SDValue T1 = DAG.getNode(ISD::AND, DL, VT, T0, C); | ||||||
3346 | SDValue T2 = DAG.getSetCC(DL, SCCVT, T1, N1C, Cond); | ||||||
3347 | return T2; | ||||||
3348 | } | ||||||
3349 | |||||||
3350 | /// Try to fold an equality comparison with a {add/sub/xor} binary operation as | ||||||
3351 | /// the 1st operand (N0). Callers are expected to swap the N0/N1 parameters to | ||||||
3352 | /// handle the commuted versions of these patterns. | ||||||
3353 | SDValue TargetLowering::foldSetCCWithBinOp(EVT VT, SDValue N0, SDValue N1, | ||||||
3354 | ISD::CondCode Cond, const SDLoc &DL, | ||||||
3355 | DAGCombinerInfo &DCI) const { | ||||||
3356 | unsigned BOpcode = N0.getOpcode(); | ||||||
3357 | assert((BOpcode == ISD::ADD || BOpcode == ISD::SUB || BOpcode == ISD::XOR) &&(((BOpcode == ISD::ADD || BOpcode == ISD::SUB || BOpcode == ISD ::XOR) && "Unexpected binop") ? static_cast<void> (0) : __assert_fail ("(BOpcode == ISD::ADD || BOpcode == ISD::SUB || BOpcode == ISD::XOR) && \"Unexpected binop\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 3358, __PRETTY_FUNCTION__)) | ||||||
3358 | "Unexpected binop")(((BOpcode == ISD::ADD || BOpcode == ISD::SUB || BOpcode == ISD ::XOR) && "Unexpected binop") ? static_cast<void> (0) : __assert_fail ("(BOpcode == ISD::ADD || BOpcode == ISD::SUB || BOpcode == ISD::XOR) && \"Unexpected binop\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 3358, __PRETTY_FUNCTION__)); | ||||||
3359 | assert((Cond == ISD::SETEQ || Cond == ISD::SETNE) && "Unexpected condcode")(((Cond == ISD::SETEQ || Cond == ISD::SETNE) && "Unexpected condcode" ) ? static_cast<void> (0) : __assert_fail ("(Cond == ISD::SETEQ || Cond == ISD::SETNE) && \"Unexpected condcode\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 3359, __PRETTY_FUNCTION__)); | ||||||
3360 | |||||||
3361 | // (X + Y) == X --> Y == 0 | ||||||
3362 | // (X - Y) == X --> Y == 0 | ||||||
3363 | // (X ^ Y) == X --> Y == 0 | ||||||
3364 | SelectionDAG &DAG = DCI.DAG; | ||||||
3365 | EVT OpVT = N0.getValueType(); | ||||||
3366 | SDValue X = N0.getOperand(0); | ||||||
3367 | SDValue Y = N0.getOperand(1); | ||||||
3368 | if (X == N1) | ||||||
3369 | return DAG.getSetCC(DL, VT, Y, DAG.getConstant(0, DL, OpVT), Cond); | ||||||
3370 | |||||||
3371 | if (Y != N1) | ||||||
3372 | return SDValue(); | ||||||
3373 | |||||||
3374 | // (X + Y) == Y --> X == 0 | ||||||
3375 | // (X ^ Y) == Y --> X == 0 | ||||||
3376 | if (BOpcode == ISD::ADD || BOpcode == ISD::XOR) | ||||||
3377 | return DAG.getSetCC(DL, VT, X, DAG.getConstant(0, DL, OpVT), Cond); | ||||||
3378 | |||||||
3379 | // The shift would not be valid if the operands are boolean (i1). | ||||||
3380 | if (!N0.hasOneUse() || OpVT.getScalarSizeInBits() == 1) | ||||||
3381 | return SDValue(); | ||||||
3382 | |||||||
3383 | // (X - Y) == Y --> X == Y << 1 | ||||||
3384 | EVT ShiftVT = getShiftAmountTy(OpVT, DAG.getDataLayout(), | ||||||
3385 | !DCI.isBeforeLegalize()); | ||||||
3386 | SDValue One = DAG.getConstant(1, DL, ShiftVT); | ||||||
3387 | SDValue YShl1 = DAG.getNode(ISD::SHL, DL, N1.getValueType(), Y, One); | ||||||
3388 | if (!DCI.isCalledByLegalizer()) | ||||||
3389 | DCI.AddToWorklist(YShl1.getNode()); | ||||||
3390 | return DAG.getSetCC(DL, VT, X, YShl1, Cond); | ||||||
3391 | } | ||||||
3392 | |||||||
3393 | static SDValue simplifySetCCWithCTPOP(const TargetLowering &TLI, EVT VT, | ||||||
3394 | SDValue N0, const APInt &C1, | ||||||
3395 | ISD::CondCode Cond, const SDLoc &dl, | ||||||
3396 | SelectionDAG &DAG) { | ||||||
3397 | // Look through truncs that don't change the value of a ctpop. | ||||||
3398 | // FIXME: Add vector support? Need to be careful with setcc result type below. | ||||||
3399 | SDValue CTPOP = N0; | ||||||
3400 | if (N0.getOpcode() == ISD::TRUNCATE && N0.hasOneUse() && !VT.isVector() && | ||||||
3401 | N0.getScalarValueSizeInBits() > Log2_32(N0.getOperand(0).getScalarValueSizeInBits())) | ||||||
3402 | CTPOP = N0.getOperand(0); | ||||||
3403 | |||||||
3404 | if (CTPOP.getOpcode() != ISD::CTPOP || !CTPOP.hasOneUse()) | ||||||
3405 | return SDValue(); | ||||||
3406 | |||||||
3407 | EVT CTVT = CTPOP.getValueType(); | ||||||
3408 | SDValue CTOp = CTPOP.getOperand(0); | ||||||
3409 | |||||||
3410 | // If this is a vector CTPOP, keep the CTPOP if it is legal. | ||||||
3411 | // TODO: Should we check if CTPOP is legal(or custom) for scalars? | ||||||
3412 | if (VT.isVector() && TLI.isOperationLegal(ISD::CTPOP, CTVT)) | ||||||
3413 | return SDValue(); | ||||||
3414 | |||||||
3415 | // (ctpop x) u< 2 -> (x & x-1) == 0 | ||||||
3416 | // (ctpop x) u> 1 -> (x & x-1) != 0 | ||||||
3417 | if (Cond == ISD::SETULT || Cond == ISD::SETUGT) { | ||||||
3418 | unsigned CostLimit = TLI.getCustomCtpopCost(CTVT, Cond); | ||||||
3419 | if (C1.ugt(CostLimit + (Cond == ISD::SETULT))) | ||||||
3420 | return SDValue(); | ||||||
3421 | if (C1 == 0 && (Cond == ISD::SETULT)) | ||||||
3422 | return SDValue(); // This is handled elsewhere. | ||||||
3423 | |||||||
3424 | unsigned Passes = C1.getLimitedValue() - (Cond == ISD::SETULT); | ||||||
3425 | |||||||
3426 | SDValue NegOne = DAG.getAllOnesConstant(dl, CTVT); | ||||||
3427 | SDValue Result = CTOp; | ||||||
3428 | for (unsigned i = 0; i < Passes; i++) { | ||||||
3429 | SDValue Add = DAG.getNode(ISD::ADD, dl, CTVT, Result, NegOne); | ||||||
3430 | Result = DAG.getNode(ISD::AND, dl, CTVT, Result, Add); | ||||||
3431 | } | ||||||
3432 | ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE; | ||||||
3433 | return DAG.getSetCC(dl, VT, Result, DAG.getConstant(0, dl, CTVT), CC); | ||||||
3434 | } | ||||||
3435 | |||||||
3436 | // If ctpop is not supported, expand a power-of-2 comparison based on it. | ||||||
3437 | if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && C1 == 1) { | ||||||
3438 | // For scalars, keep CTPOP if it is legal or custom. | ||||||
3439 | if (!VT.isVector() && TLI.isOperationLegalOrCustom(ISD::CTPOP, CTVT)) | ||||||
3440 | return SDValue(); | ||||||
3441 | // This is based on X86's custom lowering for CTPOP which produces more | ||||||
3442 | // instructions than the expansion here. | ||||||
3443 | |||||||
3444 | // (ctpop x) == 1 --> (x != 0) && ((x & x-1) == 0) | ||||||
3445 | // (ctpop x) != 1 --> (x == 0) || ((x & x-1) != 0) | ||||||
3446 | SDValue Zero = DAG.getConstant(0, dl, CTVT); | ||||||
3447 | SDValue NegOne = DAG.getAllOnesConstant(dl, CTVT); | ||||||
3448 | assert(CTVT.isInteger())((CTVT.isInteger()) ? static_cast<void> (0) : __assert_fail ("CTVT.isInteger()", "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 3448, __PRETTY_FUNCTION__)); | ||||||
3449 | ISD::CondCode InvCond = ISD::getSetCCInverse(Cond, CTVT); | ||||||
3450 | SDValue Add = DAG.getNode(ISD::ADD, dl, CTVT, CTOp, NegOne); | ||||||
3451 | SDValue And = DAG.getNode(ISD::AND, dl, CTVT, CTOp, Add); | ||||||
3452 | SDValue LHS = DAG.getSetCC(dl, VT, CTOp, Zero, InvCond); | ||||||
3453 | SDValue RHS = DAG.getSetCC(dl, VT, And, Zero, Cond); | ||||||
3454 | unsigned LogicOpcode = Cond == ISD::SETEQ ? ISD::AND : ISD::OR; | ||||||
3455 | return DAG.getNode(LogicOpcode, dl, VT, LHS, RHS); | ||||||
3456 | } | ||||||
3457 | |||||||
3458 | return SDValue(); | ||||||
3459 | } | ||||||
3460 | |||||||
3461 | /// Try to simplify a setcc built with the specified operands and cc. If it is | ||||||
3462 | /// unable to simplify it, return a null SDValue. | ||||||
3463 | SDValue TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1, | ||||||
3464 | ISD::CondCode Cond, bool foldBooleans, | ||||||
3465 | DAGCombinerInfo &DCI, | ||||||
3466 | const SDLoc &dl) const { | ||||||
3467 | SelectionDAG &DAG = DCI.DAG; | ||||||
3468 | const DataLayout &Layout = DAG.getDataLayout(); | ||||||
3469 | EVT OpVT = N0.getValueType(); | ||||||
3470 | |||||||
3471 | // Constant fold or commute setcc. | ||||||
3472 | if (SDValue Fold = DAG.FoldSetCC(VT, N0, N1, Cond, dl)) | ||||||
3473 | return Fold; | ||||||
3474 | |||||||
3475 | // Ensure that the constant occurs on the RHS and fold constant comparisons. | ||||||
3476 | // TODO: Handle non-splat vector constants. All undef causes trouble. | ||||||
3477 | // FIXME: We can't yet fold constant scalable vector splats, so avoid an | ||||||
3478 | // infinite loop here when we encounter one. | ||||||
3479 | ISD::CondCode SwappedCC = ISD::getSetCCSwappedOperands(Cond); | ||||||
3480 | if (isConstOrConstSplat(N0) && | ||||||
3481 | (!OpVT.isScalableVector() || !isConstOrConstSplat(N1)) && | ||||||
3482 | (DCI.isBeforeLegalizeOps() || | ||||||
3483 | isCondCodeLegal(SwappedCC, N0.getSimpleValueType()))) | ||||||
3484 | return DAG.getSetCC(dl, VT, N1, N0, SwappedCC); | ||||||
3485 | |||||||
3486 | // If we have a subtract with the same 2 non-constant operands as this setcc | ||||||
3487 | // -- but in reverse order -- then try to commute the operands of this setcc | ||||||
3488 | // to match. A matching pair of setcc (cmp) and sub may be combined into 1 | ||||||
3489 | // instruction on some targets. | ||||||
3490 | if (!isConstOrConstSplat(N0) && !isConstOrConstSplat(N1) && | ||||||
3491 | (DCI.isBeforeLegalizeOps() || | ||||||
3492 | isCondCodeLegal(SwappedCC, N0.getSimpleValueType())) && | ||||||
3493 | DAG.doesNodeExist(ISD::SUB, DAG.getVTList(OpVT), {N1, N0}) && | ||||||
3494 | !DAG.doesNodeExist(ISD::SUB, DAG.getVTList(OpVT), {N0, N1})) | ||||||
3495 | return DAG.getSetCC(dl, VT, N1, N0, SwappedCC); | ||||||
3496 | |||||||
3497 | if (auto *N1C = isConstOrConstSplat(N1)) { | ||||||
3498 | const APInt &C1 = N1C->getAPIntValue(); | ||||||
3499 | |||||||
3500 | // Optimize some CTPOP cases. | ||||||
3501 | if (SDValue V = simplifySetCCWithCTPOP(*this, VT, N0, C1, Cond, dl, DAG)) | ||||||
3502 | return V; | ||||||
3503 | |||||||
3504 | // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an | ||||||
3505 | // equality comparison, then we're just comparing whether X itself is | ||||||
3506 | // zero. | ||||||
3507 | if (N0.getOpcode() == ISD::SRL && (C1.isNullValue() || C1.isOneValue()) && | ||||||
3508 | N0.getOperand(0).getOpcode() == ISD::CTLZ && | ||||||
3509 | isPowerOf2_32(N0.getScalarValueSizeInBits())) { | ||||||
3510 | if (ConstantSDNode *ShAmt = isConstOrConstSplat(N0.getOperand(1))) { | ||||||
3511 | if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && | ||||||
3512 | ShAmt->getAPIntValue() == Log2_32(N0.getScalarValueSizeInBits())) { | ||||||
3513 | if ((C1 == 0) == (Cond == ISD::SETEQ)) { | ||||||
3514 | // (srl (ctlz x), 5) == 0 -> X != 0 | ||||||
3515 | // (srl (ctlz x), 5) != 1 -> X != 0 | ||||||
3516 | Cond = ISD::SETNE; | ||||||
3517 | } else { | ||||||
3518 | // (srl (ctlz x), 5) != 0 -> X == 0 | ||||||
3519 | // (srl (ctlz x), 5) == 1 -> X == 0 | ||||||
3520 | Cond = ISD::SETEQ; | ||||||
3521 | } | ||||||
3522 | SDValue Zero = DAG.getConstant(0, dl, N0.getValueType()); | ||||||
3523 | return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0), Zero, | ||||||
3524 | Cond); | ||||||
3525 | } | ||||||
3526 | } | ||||||
3527 | } | ||||||
3528 | } | ||||||
3529 | |||||||
3530 | // FIXME: Support vectors. | ||||||
3531 | if (auto *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) { | ||||||
3532 | const APInt &C1 = N1C->getAPIntValue(); | ||||||
3533 | |||||||
3534 | // (zext x) == C --> x == (trunc C) | ||||||
3535 | // (sext x) == C --> x == (trunc C) | ||||||
3536 | if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && | ||||||
3537 | DCI.isBeforeLegalize() && N0->hasOneUse()) { | ||||||
3538 | unsigned MinBits = N0.getValueSizeInBits(); | ||||||
3539 | SDValue PreExt; | ||||||
3540 | bool Signed = false; | ||||||
3541 | if (N0->getOpcode() == ISD::ZERO_EXTEND) { | ||||||
3542 | // ZExt | ||||||
3543 | MinBits = N0->getOperand(0).getValueSizeInBits(); | ||||||
3544 | PreExt = N0->getOperand(0); | ||||||
3545 | } else if (N0->getOpcode() == ISD::AND) { | ||||||
3546 | // DAGCombine turns costly ZExts into ANDs | ||||||
3547 | if (auto *C = dyn_cast<ConstantSDNode>(N0->getOperand(1))) | ||||||
3548 | if ((C->getAPIntValue()+1).isPowerOf2()) { | ||||||
3549 | MinBits = C->getAPIntValue().countTrailingOnes(); | ||||||
3550 | PreExt = N0->getOperand(0); | ||||||
3551 | } | ||||||
3552 | } else if (N0->getOpcode() == ISD::SIGN_EXTEND) { | ||||||
3553 | // SExt | ||||||
3554 | MinBits = N0->getOperand(0).getValueSizeInBits(); | ||||||
3555 | PreExt = N0->getOperand(0); | ||||||
3556 | Signed = true; | ||||||
3557 | } else if (auto *LN0 = dyn_cast<LoadSDNode>(N0)) { | ||||||
3558 | // ZEXTLOAD / SEXTLOAD | ||||||
3559 | if (LN0->getExtensionType() == ISD::ZEXTLOAD) { | ||||||
3560 | MinBits = LN0->getMemoryVT().getSizeInBits(); | ||||||
3561 | PreExt = N0; | ||||||
3562 | } else if (LN0->getExtensionType() == ISD::SEXTLOAD) { | ||||||
3563 | Signed = true; | ||||||
3564 | MinBits = LN0->getMemoryVT().getSizeInBits(); | ||||||
3565 | PreExt = N0; | ||||||
3566 | } | ||||||
3567 | } | ||||||
3568 | |||||||
3569 | // Figure out how many bits we need to preserve this constant. | ||||||
3570 | unsigned ReqdBits = Signed ? | ||||||
3571 | C1.getBitWidth() - C1.getNumSignBits() + 1 : | ||||||
3572 | C1.getActiveBits(); | ||||||
3573 | |||||||
3574 | // Make sure we're not losing bits from the constant. | ||||||
3575 | if (MinBits > 0 && | ||||||
3576 | MinBits < C1.getBitWidth() && | ||||||
3577 | MinBits >= ReqdBits) { | ||||||
3578 | EVT MinVT = EVT::getIntegerVT(*DAG.getContext(), MinBits); | ||||||
3579 | if (isTypeDesirableForOp(ISD::SETCC, MinVT)) { | ||||||
3580 | // Will get folded away. | ||||||
3581 | SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MinVT, PreExt); | ||||||
3582 | if (MinBits == 1 && C1 == 1) | ||||||
3583 | // Invert the condition. | ||||||
3584 | return DAG.getSetCC(dl, VT, Trunc, DAG.getConstant(0, dl, MVT::i1), | ||||||
3585 | Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); | ||||||
3586 | SDValue C = DAG.getConstant(C1.trunc(MinBits), dl, MinVT); | ||||||
3587 | return DAG.getSetCC(dl, VT, Trunc, C, Cond); | ||||||
3588 | } | ||||||
3589 | |||||||
3590 | // If truncating the setcc operands is not desirable, we can still | ||||||
3591 | // simplify the expression in some cases: | ||||||
3592 | // setcc ([sz]ext (setcc x, y, cc)), 0, setne) -> setcc (x, y, cc) | ||||||
3593 | // setcc ([sz]ext (setcc x, y, cc)), 0, seteq) -> setcc (x, y, inv(cc)) | ||||||
3594 | // setcc (zext (setcc x, y, cc)), 1, setne) -> setcc (x, y, inv(cc)) | ||||||
3595 | // setcc (zext (setcc x, y, cc)), 1, seteq) -> setcc (x, y, cc) | ||||||
3596 | // setcc (sext (setcc x, y, cc)), -1, setne) -> setcc (x, y, inv(cc)) | ||||||
3597 | // setcc (sext (setcc x, y, cc)), -1, seteq) -> setcc (x, y, cc) | ||||||
3598 | SDValue TopSetCC = N0->getOperand(0); | ||||||
3599 | unsigned N0Opc = N0->getOpcode(); | ||||||
3600 | bool SExt = (N0Opc == ISD::SIGN_EXTEND); | ||||||
3601 | if (TopSetCC.getValueType() == MVT::i1 && VT == MVT::i1 && | ||||||
3602 | TopSetCC.getOpcode() == ISD::SETCC && | ||||||
3603 | (N0Opc == ISD::ZERO_EXTEND || N0Opc == ISD::SIGN_EXTEND) && | ||||||
3604 | (isConstFalseVal(N1C) || | ||||||
3605 | isExtendedTrueVal(N1C, N0->getValueType(0), SExt))) { | ||||||
3606 | |||||||
3607 | bool Inverse = (N1C->isNullValue() && Cond == ISD::SETEQ) || | ||||||
3608 | (!N1C->isNullValue() && Cond == ISD::SETNE); | ||||||
3609 | |||||||
3610 | if (!Inverse) | ||||||
3611 | return TopSetCC; | ||||||
3612 | |||||||
3613 | ISD::CondCode InvCond = ISD::getSetCCInverse( | ||||||
3614 | cast<CondCodeSDNode>(TopSetCC.getOperand(2))->get(), | ||||||
3615 | TopSetCC.getOperand(0).getValueType()); | ||||||
3616 | return DAG.getSetCC(dl, VT, TopSetCC.getOperand(0), | ||||||
3617 | TopSetCC.getOperand(1), | ||||||
3618 | InvCond); | ||||||
3619 | } | ||||||
3620 | } | ||||||
3621 | } | ||||||
3622 | |||||||
3623 | // If the LHS is '(and load, const)', the RHS is 0, the test is for | ||||||
3624 | // equality or unsigned, and all 1 bits of the const are in the same | ||||||
3625 | // partial word, see if we can shorten the load. | ||||||
3626 | if (DCI.isBeforeLegalize() && | ||||||
3627 | !ISD::isSignedIntSetCC(Cond) && | ||||||
3628 | N0.getOpcode() == ISD::AND && C1 == 0 && | ||||||
3629 | N0.getNode()->hasOneUse() && | ||||||
3630 | isa<LoadSDNode>(N0.getOperand(0)) && | ||||||
3631 | N0.getOperand(0).getNode()->hasOneUse() && | ||||||
3632 | isa<ConstantSDNode>(N0.getOperand(1))) { | ||||||
3633 | LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0)); | ||||||
3634 | APInt bestMask; | ||||||
3635 | unsigned bestWidth = 0, bestOffset = 0; | ||||||
3636 | if (Lod->isSimple() && Lod->isUnindexed()) { | ||||||
3637 | unsigned origWidth = N0.getValueSizeInBits(); | ||||||
3638 | unsigned maskWidth = origWidth; | ||||||
3639 | // We can narrow (e.g.) 16-bit extending loads on 32-bit target to | ||||||
3640 | // 8 bits, but have to be careful... | ||||||
3641 | if (Lod->getExtensionType() != ISD::NON_EXTLOAD) | ||||||
3642 | origWidth = Lod->getMemoryVT().getSizeInBits(); | ||||||
3643 | const APInt &Mask = N0.getConstantOperandAPInt(1); | ||||||
3644 | for (unsigned width = origWidth / 2; width>=8; width /= 2) { | ||||||
3645 | APInt newMask = APInt::getLowBitsSet(maskWidth, width); | ||||||
3646 | for (unsigned offset=0; offset<origWidth/width; offset++) { | ||||||
3647 | if (Mask.isSubsetOf(newMask)) { | ||||||
3648 | if (Layout.isLittleEndian()) | ||||||
3649 | bestOffset = (uint64_t)offset * (width/8); | ||||||
3650 | else | ||||||
3651 | bestOffset = (origWidth/width - offset - 1) * (width/8); | ||||||
3652 | bestMask = Mask.lshr(offset * (width/8) * 8); | ||||||
3653 | bestWidth = width; | ||||||
3654 | break; | ||||||
3655 | } | ||||||
3656 | newMask <<= width; | ||||||
3657 | } | ||||||
3658 | } | ||||||
3659 | } | ||||||
3660 | if (bestWidth) { | ||||||
3661 | EVT newVT = EVT::getIntegerVT(*DAG.getContext(), bestWidth); | ||||||
3662 | if (newVT.isRound() && | ||||||
3663 | shouldReduceLoadWidth(Lod, ISD::NON_EXTLOAD, newVT)) { | ||||||
3664 | SDValue Ptr = Lod->getBasePtr(); | ||||||
3665 | if (bestOffset != 0) | ||||||
3666 | Ptr = | ||||||
3667 | DAG.getMemBasePlusOffset(Ptr, TypeSize::Fixed(bestOffset), dl); | ||||||
3668 | SDValue NewLoad = | ||||||
3669 | DAG.getLoad(newVT, dl, Lod->getChain(), Ptr, | ||||||
3670 | Lod->getPointerInfo().getWithOffset(bestOffset), | ||||||
3671 | Lod->getOriginalAlign()); | ||||||
3672 | return DAG.getSetCC(dl, VT, | ||||||
3673 | DAG.getNode(ISD::AND, dl, newVT, NewLoad, | ||||||
3674 | DAG.getConstant(bestMask.trunc(bestWidth), | ||||||
3675 | dl, newVT)), | ||||||
3676 | DAG.getConstant(0LL, dl, newVT), Cond); | ||||||
3677 | } | ||||||
3678 | } | ||||||
3679 | } | ||||||
3680 | |||||||
3681 | // If the LHS is a ZERO_EXTEND, perform the comparison on the input. | ||||||
3682 | if (N0.getOpcode() == ISD::ZERO_EXTEND) { | ||||||
3683 | unsigned InSize = N0.getOperand(0).getValueSizeInBits(); | ||||||
3684 | |||||||
3685 | // If the comparison constant has bits in the upper part, the | ||||||
3686 | // zero-extended value could never match. | ||||||
3687 | if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(), | ||||||
3688 | C1.getBitWidth() - InSize))) { | ||||||
3689 | switch (Cond) { | ||||||
3690 | case ISD::SETUGT: | ||||||
3691 | case ISD::SETUGE: | ||||||
3692 | case ISD::SETEQ: | ||||||
3693 | return DAG.getConstant(0, dl, VT); | ||||||
3694 | case ISD::SETULT: | ||||||
3695 | case ISD::SETULE: | ||||||
3696 | case ISD::SETNE: | ||||||
3697 | return DAG.getConstant(1, dl, VT); | ||||||
3698 | case ISD::SETGT: | ||||||
3699 | case ISD::SETGE: | ||||||
3700 | // True if the sign bit of C1 is set. | ||||||
3701 | return DAG.getConstant(C1.isNegative(), dl, VT); | ||||||
3702 | case ISD::SETLT: | ||||||
3703 | case ISD::SETLE: | ||||||
3704 | // True if the sign bit of C1 isn't set. | ||||||
3705 | return DAG.getConstant(C1.isNonNegative(), dl, VT); | ||||||
3706 | default: | ||||||
3707 | break; | ||||||
3708 | } | ||||||
3709 | } | ||||||
3710 | |||||||
3711 | // Otherwise, we can perform the comparison with the low bits. | ||||||
3712 | switch (Cond) { | ||||||
3713 | case ISD::SETEQ: | ||||||
3714 | case ISD::SETNE: | ||||||
3715 | case ISD::SETUGT: | ||||||
3716 | case ISD::SETUGE: | ||||||
3717 | case ISD::SETULT: | ||||||
3718 | case ISD::SETULE: { | ||||||
3719 | EVT newVT = N0.getOperand(0).getValueType(); | ||||||
3720 | if (DCI.isBeforeLegalizeOps() || | ||||||
3721 | (isOperationLegal(ISD::SETCC, newVT) && | ||||||
3722 | isCondCodeLegal(Cond, newVT.getSimpleVT()))) { | ||||||
3723 | EVT NewSetCCVT = getSetCCResultType(Layout, *DAG.getContext(), newVT); | ||||||
3724 | SDValue NewConst = DAG.getConstant(C1.trunc(InSize), dl, newVT); | ||||||
3725 | |||||||
3726 | SDValue NewSetCC = DAG.getSetCC(dl, NewSetCCVT, N0.getOperand(0), | ||||||
3727 | NewConst, Cond); | ||||||
3728 | return DAG.getBoolExtOrTrunc(NewSetCC, dl, VT, N0.getValueType()); | ||||||
3729 | } | ||||||
3730 | break; | ||||||
3731 | } | ||||||
3732 | default: | ||||||
3733 | break; // todo, be more careful with signed comparisons | ||||||
3734 | } | ||||||
3735 | } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && | ||||||
3736 | (Cond == ISD::SETEQ || Cond == ISD::SETNE) && | ||||||
3737 | !isSExtCheaperThanZExt(cast<VTSDNode>(N0.getOperand(1))->getVT(), | ||||||
3738 | OpVT)) { | ||||||
3739 | EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT(); | ||||||
3740 | unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits(); | ||||||
3741 | EVT ExtDstTy = N0.getValueType(); | ||||||
3742 | unsigned ExtDstTyBits = ExtDstTy.getSizeInBits(); | ||||||
3743 | |||||||
3744 | // If the constant doesn't fit into the number of bits for the source of | ||||||
3745 | // the sign extension, it is impossible for both sides to be equal. | ||||||
3746 | if (C1.getMinSignedBits() > ExtSrcTyBits) | ||||||
3747 | return DAG.getBoolConstant(Cond == ISD::SETNE, dl, VT, OpVT); | ||||||
3748 | |||||||
3749 | assert(ExtDstTy == N0.getOperand(0).getValueType() &&((ExtDstTy == N0.getOperand(0).getValueType() && ExtDstTy != ExtSrcTy && "Unexpected types!") ? static_cast< void> (0) : __assert_fail ("ExtDstTy == N0.getOperand(0).getValueType() && ExtDstTy != ExtSrcTy && \"Unexpected types!\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 3750, __PRETTY_FUNCTION__)) | ||||||
3750 | ExtDstTy != ExtSrcTy && "Unexpected types!")((ExtDstTy == N0.getOperand(0).getValueType() && ExtDstTy != ExtSrcTy && "Unexpected types!") ? static_cast< void> (0) : __assert_fail ("ExtDstTy == N0.getOperand(0).getValueType() && ExtDstTy != ExtSrcTy && \"Unexpected types!\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 3750, __PRETTY_FUNCTION__)); | ||||||
3751 | APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits); | ||||||
3752 | SDValue ZextOp = DAG.getNode(ISD::AND, dl, ExtDstTy, N0.getOperand(0), | ||||||
3753 | DAG.getConstant(Imm, dl, ExtDstTy)); | ||||||
3754 | if (!DCI.isCalledByLegalizer()) | ||||||
3755 | DCI.AddToWorklist(ZextOp.getNode()); | ||||||
3756 | // Otherwise, make this a use of a zext. | ||||||
3757 | return DAG.getSetCC(dl, VT, ZextOp, | ||||||
3758 | DAG.getConstant(C1 & Imm, dl, ExtDstTy), Cond); | ||||||
3759 | } else if ((N1C->isNullValue() || N1C->isOne()) && | ||||||
3760 | (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { | ||||||
3761 | // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC | ||||||
3762 | if (N0.getOpcode() == ISD::SETCC && | ||||||
3763 | isTypeLegal(VT) && VT.bitsLE(N0.getValueType()) && | ||||||
3764 | (N0.getValueType() == MVT::i1 || | ||||||
3765 | getBooleanContents(N0.getOperand(0).getValueType()) == | ||||||
3766 | ZeroOrOneBooleanContent)) { | ||||||
3767 | bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (!N1C->isOne()); | ||||||
3768 | if (TrueWhenTrue) | ||||||
3769 | return DAG.getNode(ISD::TRUNCATE, dl, VT, N0); | ||||||
3770 | // Invert the condition. | ||||||
3771 | ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get(); | ||||||
3772 | CC = ISD::getSetCCInverse(CC, N0.getOperand(0).getValueType()); | ||||||
3773 | if (DCI.isBeforeLegalizeOps() || | ||||||
3774 | isCondCodeLegal(CC, N0.getOperand(0).getSimpleValueType())) | ||||||
3775 | return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC); | ||||||
3776 | } | ||||||
3777 | |||||||
3778 | if ((N0.getOpcode() == ISD::XOR || | ||||||
3779 | (N0.getOpcode() == ISD::AND && | ||||||
3780 | N0.getOperand(0).getOpcode() == ISD::XOR && | ||||||
3781 | N0.getOperand(1) == N0.getOperand(0).getOperand(1))) && | ||||||
3782 | isOneConstant(N0.getOperand(1))) { | ||||||
3783 | // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We | ||||||
3784 | // can only do this if the top bits are known zero. | ||||||
3785 | unsigned BitWidth = N0.getValueSizeInBits(); | ||||||
3786 | if (DAG.MaskedValueIsZero(N0, | ||||||
3787 | APInt::getHighBitsSet(BitWidth, | ||||||
3788 | BitWidth-1))) { | ||||||
3789 | // Okay, get the un-inverted input value. | ||||||
3790 | SDValue Val; | ||||||
3791 | if (N0.getOpcode() == ISD::XOR) { | ||||||
3792 | Val = N0.getOperand(0); | ||||||
3793 | } else { | ||||||
3794 | assert(N0.getOpcode() == ISD::AND &&((N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode () == ISD::XOR) ? static_cast<void> (0) : __assert_fail ("N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::XOR" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 3795, __PRETTY_FUNCTION__)) | ||||||
3795 | N0.getOperand(0).getOpcode() == ISD::XOR)((N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode () == ISD::XOR) ? static_cast<void> (0) : __assert_fail ("N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::XOR" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 3795, __PRETTY_FUNCTION__)); | ||||||
3796 | // ((X^1)&1)^1 -> X & 1 | ||||||
3797 | Val = DAG.getNode(ISD::AND, dl, N0.getValueType(), | ||||||
3798 | N0.getOperand(0).getOperand(0), | ||||||
3799 | N0.getOperand(1)); | ||||||
3800 | } | ||||||
3801 | |||||||
3802 | return DAG.getSetCC(dl, VT, Val, N1, | ||||||
3803 | Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); | ||||||
3804 | } | ||||||
3805 | } else if (N1C->isOne()) { | ||||||
3806 | SDValue Op0 = N0; | ||||||
3807 | if (Op0.getOpcode() == ISD::TRUNCATE) | ||||||
3808 | Op0 = Op0.getOperand(0); | ||||||
3809 | |||||||
3810 | if ((Op0.getOpcode() == ISD::XOR) && | ||||||
3811 | Op0.getOperand(0).getOpcode() == ISD::SETCC && | ||||||
3812 | Op0.getOperand(1).getOpcode() == ISD::SETCC) { | ||||||
3813 | SDValue XorLHS = Op0.getOperand(0); | ||||||
3814 | SDValue XorRHS = Op0.getOperand(1); | ||||||
3815 | // Ensure that the input setccs return an i1 type or 0/1 value. | ||||||
3816 | if (Op0.getValueType() == MVT::i1 || | ||||||
3817 | (getBooleanContents(XorLHS.getOperand(0).getValueType()) == | ||||||
3818 | ZeroOrOneBooleanContent && | ||||||
3819 | getBooleanContents(XorRHS.getOperand(0).getValueType()) == | ||||||
3820 | ZeroOrOneBooleanContent)) { | ||||||
3821 | // (xor (setcc), (setcc)) == / != 1 -> (setcc) != / == (setcc) | ||||||
3822 | Cond = (Cond == ISD::SETEQ) ? ISD::SETNE : ISD::SETEQ; | ||||||
3823 | return DAG.getSetCC(dl, VT, XorLHS, XorRHS, Cond); | ||||||
3824 | } | ||||||
3825 | } | ||||||
3826 | if (Op0.getOpcode() == ISD::AND && isOneConstant(Op0.getOperand(1))) { | ||||||
3827 | // If this is (X&1) == / != 1, normalize it to (X&1) != / == 0. | ||||||
3828 | if (Op0.getValueType().bitsGT(VT)) | ||||||
3829 | Op0 = DAG.getNode(ISD::AND, dl, VT, | ||||||
3830 | DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)), | ||||||
3831 | DAG.getConstant(1, dl, VT)); | ||||||
3832 | else if (Op0.getValueType().bitsLT(VT)) | ||||||
3833 | Op0 = DAG.getNode(ISD::AND, dl, VT, | ||||||
3834 | DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)), | ||||||
3835 | DAG.getConstant(1, dl, VT)); | ||||||
3836 | |||||||
3837 | return DAG.getSetCC(dl, VT, Op0, | ||||||
3838 | DAG.getConstant(0, dl, Op0.getValueType()), | ||||||
3839 | Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); | ||||||
3840 | } | ||||||
3841 | if (Op0.getOpcode() == ISD::AssertZext && | ||||||
3842 | cast<VTSDNode>(Op0.getOperand(1))->getVT() == MVT::i1) | ||||||
3843 | return DAG.getSetCC(dl, VT, Op0, | ||||||
3844 | DAG.getConstant(0, dl, Op0.getValueType()), | ||||||
3845 | Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); | ||||||
3846 | } | ||||||
3847 | } | ||||||
3848 | |||||||
3849 | // Given: | ||||||
3850 | // icmp eq/ne (urem %x, %y), 0 | ||||||
3851 | // Iff %x has 0 or 1 bits set, and %y has at least 2 bits set, omit 'urem': | ||||||
3852 | // icmp eq/ne %x, 0 | ||||||
3853 | if (N0.getOpcode() == ISD::UREM && N1C->isNullValue() && | ||||||
3854 | (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { | ||||||
3855 | KnownBits XKnown = DAG.computeKnownBits(N0.getOperand(0)); | ||||||
3856 | KnownBits YKnown = DAG.computeKnownBits(N0.getOperand(1)); | ||||||
3857 | if (XKnown.countMaxPopulation() == 1 && YKnown.countMinPopulation() >= 2) | ||||||
3858 | return DAG.getSetCC(dl, VT, N0.getOperand(0), N1, Cond); | ||||||
3859 | } | ||||||
3860 | |||||||
3861 | if (SDValue V = | ||||||
3862 | optimizeSetCCOfSignedTruncationCheck(VT, N0, N1, Cond, DCI, dl)) | ||||||
3863 | return V; | ||||||
3864 | } | ||||||
3865 | |||||||
3866 | // These simplifications apply to splat vectors as well. | ||||||
3867 | // TODO: Handle more splat vector cases. | ||||||
3868 | if (auto *N1C = isConstOrConstSplat(N1)) { | ||||||
3869 | const APInt &C1 = N1C->getAPIntValue(); | ||||||
3870 | |||||||
3871 | APInt MinVal, MaxVal; | ||||||
3872 | unsigned OperandBitSize = N1C->getValueType(0).getScalarSizeInBits(); | ||||||
3873 | if (ISD::isSignedIntSetCC(Cond)) { | ||||||
3874 | MinVal = APInt::getSignedMinValue(OperandBitSize); | ||||||
3875 | MaxVal = APInt::getSignedMaxValue(OperandBitSize); | ||||||
3876 | } else { | ||||||
3877 | MinVal = APInt::getMinValue(OperandBitSize); | ||||||
3878 | MaxVal = APInt::getMaxValue(OperandBitSize); | ||||||
3879 | } | ||||||
3880 | |||||||
3881 | // Canonicalize GE/LE comparisons to use GT/LT comparisons. | ||||||
3882 | if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { | ||||||
3883 | // X >= MIN --> true | ||||||
3884 | if (C1 == MinVal) | ||||||
3885 | return DAG.getBoolConstant(true, dl, VT, OpVT); | ||||||
3886 | |||||||
3887 | if (!VT.isVector()) { // TODO: Support this for vectors. | ||||||
3888 | // X >= C0 --> X > (C0 - 1) | ||||||
3889 | APInt C = C1 - 1; | ||||||
3890 | ISD::CondCode NewCC = (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT; | ||||||
3891 | if ((DCI.isBeforeLegalizeOps() || | ||||||
3892 | isCondCodeLegal(NewCC, VT.getSimpleVT())) && | ||||||
3893 | (!N1C->isOpaque() || (C.getBitWidth() <= 64 && | ||||||
3894 | isLegalICmpImmediate(C.getSExtValue())))) { | ||||||
3895 | return DAG.getSetCC(dl, VT, N0, | ||||||
3896 | DAG.getConstant(C, dl, N1.getValueType()), | ||||||
3897 | NewCC); | ||||||
3898 | } | ||||||
3899 | } | ||||||
3900 | } | ||||||
3901 | |||||||
3902 | if (Cond == ISD::SETLE || Cond == ISD::SETULE) { | ||||||
3903 | // X <= MAX --> true | ||||||
3904 | if (C1 == MaxVal) | ||||||
3905 | return DAG.getBoolConstant(true, dl, VT, OpVT); | ||||||
3906 | |||||||
3907 | // X <= C0 --> X < (C0 + 1) | ||||||
3908 | if (!VT.isVector()) { // TODO: Support this for vectors. | ||||||
3909 | APInt C = C1 + 1; | ||||||
3910 | ISD::CondCode NewCC = (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT; | ||||||
3911 | if ((DCI.isBeforeLegalizeOps() || | ||||||
3912 | isCondCodeLegal(NewCC, VT.getSimpleVT())) && | ||||||
3913 | (!N1C->isOpaque() || (C.getBitWidth() <= 64 && | ||||||
3914 | isLegalICmpImmediate(C.getSExtValue())))) { | ||||||
3915 | return DAG.getSetCC(dl, VT, N0, | ||||||
3916 | DAG.getConstant(C, dl, N1.getValueType()), | ||||||
3917 | NewCC); | ||||||
3918 | } | ||||||
3919 | } | ||||||
3920 | } | ||||||
3921 | |||||||
3922 | if (Cond == ISD::SETLT || Cond == ISD::SETULT) { | ||||||
3923 | if (C1 == MinVal) | ||||||
3924 | return DAG.getBoolConstant(false, dl, VT, OpVT); // X < MIN --> false | ||||||
3925 | |||||||
3926 | // TODO: Support this for vectors after legalize ops. | ||||||
3927 | if (!VT.isVector() || DCI.isBeforeLegalizeOps()) { | ||||||
3928 | // Canonicalize setlt X, Max --> setne X, Max | ||||||
3929 | if (C1 == MaxVal) | ||||||
3930 | return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE); | ||||||
3931 | |||||||
3932 | // If we have setult X, 1, turn it into seteq X, 0 | ||||||
3933 | if (C1 == MinVal+1) | ||||||
3934 | return DAG.getSetCC(dl, VT, N0, | ||||||
3935 | DAG.getConstant(MinVal, dl, N0.getValueType()), | ||||||
3936 | ISD::SETEQ); | ||||||
3937 | } | ||||||
3938 | } | ||||||
3939 | |||||||
3940 | if (Cond == ISD::SETGT || Cond == ISD::SETUGT) { | ||||||
3941 | if (C1 == MaxVal) | ||||||
3942 | return DAG.getBoolConstant(false, dl, VT, OpVT); // X > MAX --> false | ||||||
3943 | |||||||
3944 | // TODO: Support this for vectors after legalize ops. | ||||||
3945 | if (!VT.isVector() || DCI.isBeforeLegalizeOps()) { | ||||||
3946 | // Canonicalize setgt X, Min --> setne X, Min | ||||||
3947 | if (C1 == MinVal) | ||||||
3948 | return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE); | ||||||
3949 | |||||||
3950 | // If we have setugt X, Max-1, turn it into seteq X, Max | ||||||
3951 | if (C1 == MaxVal-1) | ||||||
3952 | return DAG.getSetCC(dl, VT, N0, | ||||||
3953 | DAG.getConstant(MaxVal, dl, N0.getValueType()), | ||||||
3954 | ISD::SETEQ); | ||||||
3955 | } | ||||||
3956 | } | ||||||
3957 | |||||||
3958 | if (Cond == ISD::SETEQ || Cond == ISD::SETNE) { | ||||||
3959 | // (X & (C l>>/<< Y)) ==/!= 0 --> ((X <</l>> Y) & C) ==/!= 0 | ||||||
3960 | if (C1.isNullValue()) | ||||||
3961 | if (SDValue CC = optimizeSetCCByHoistingAndByConstFromLogicalShift( | ||||||
3962 | VT, N0, N1, Cond, DCI, dl)) | ||||||
3963 | return CC; | ||||||
3964 | |||||||
3965 | // For all/any comparisons, replace or(x,shl(y,bw/2)) with and/or(x,y). | ||||||
3966 | // For example, when high 32-bits of i64 X are known clear: | ||||||
3967 | // all bits clear: (X | (Y<<32)) == 0 --> (X | Y) == 0 | ||||||
3968 | // all bits set: (X | (Y<<32)) == -1 --> (X & Y) == -1 | ||||||
3969 | bool CmpZero = N1C->getAPIntValue().isNullValue(); | ||||||
3970 | bool CmpNegOne = N1C->getAPIntValue().isAllOnesValue(); | ||||||
3971 | if ((CmpZero || CmpNegOne) && N0.hasOneUse()) { | ||||||
3972 | // Match or(lo,shl(hi,bw/2)) pattern. | ||||||
3973 | auto IsConcat = [&](SDValue V, SDValue &Lo, SDValue &Hi) { | ||||||
3974 | unsigned EltBits = V.getScalarValueSizeInBits(); | ||||||
3975 | if (V.getOpcode() != ISD::OR || (EltBits % 2) != 0) | ||||||
3976 | return false; | ||||||
3977 | SDValue LHS = V.getOperand(0); | ||||||
3978 | SDValue RHS = V.getOperand(1); | ||||||
3979 | APInt HiBits = APInt::getHighBitsSet(EltBits, EltBits / 2); | ||||||
3980 | // Unshifted element must have zero upperbits. | ||||||
3981 | if (RHS.getOpcode() == ISD::SHL && | ||||||
3982 | isa<ConstantSDNode>(RHS.getOperand(1)) && | ||||||
3983 | RHS.getConstantOperandAPInt(1) == (EltBits / 2) && | ||||||
3984 | DAG.MaskedValueIsZero(LHS, HiBits)) { | ||||||
3985 | Lo = LHS; | ||||||
3986 | Hi = RHS.getOperand(0); | ||||||
3987 | return true; | ||||||
3988 | } | ||||||
3989 | if (LHS.getOpcode() == ISD::SHL && | ||||||
3990 | isa<ConstantSDNode>(LHS.getOperand(1)) && | ||||||
3991 | LHS.getConstantOperandAPInt(1) == (EltBits / 2) && | ||||||
3992 | DAG.MaskedValueIsZero(RHS, HiBits)) { | ||||||
3993 | Lo = RHS; | ||||||
3994 | Hi = LHS.getOperand(0); | ||||||
3995 | return true; | ||||||
3996 | } | ||||||
3997 | return false; | ||||||
3998 | }; | ||||||
3999 | |||||||
4000 | auto MergeConcat = [&](SDValue Lo, SDValue Hi) { | ||||||
4001 | unsigned EltBits = N0.getScalarValueSizeInBits(); | ||||||
4002 | unsigned HalfBits = EltBits / 2; | ||||||
4003 | APInt HiBits = APInt::getHighBitsSet(EltBits, HalfBits); | ||||||
4004 | SDValue LoBits = DAG.getConstant(~HiBits, dl, OpVT); | ||||||
4005 | SDValue HiMask = DAG.getNode(ISD::AND, dl, OpVT, Hi, LoBits); | ||||||
4006 | SDValue NewN0 = | ||||||
4007 | DAG.getNode(CmpZero ? ISD::OR : ISD::AND, dl, OpVT, Lo, HiMask); | ||||||
4008 | SDValue NewN1 = CmpZero ? DAG.getConstant(0, dl, OpVT) : LoBits; | ||||||
4009 | return DAG.getSetCC(dl, VT, NewN0, NewN1, Cond); | ||||||
4010 | }; | ||||||
4011 | |||||||
4012 | SDValue Lo, Hi; | ||||||
4013 | if (IsConcat(N0, Lo, Hi)) | ||||||
4014 | return MergeConcat(Lo, Hi); | ||||||
4015 | |||||||
4016 | if (N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR) { | ||||||
4017 | SDValue Lo0, Lo1, Hi0, Hi1; | ||||||
4018 | if (IsConcat(N0.getOperand(0), Lo0, Hi0) && | ||||||
4019 | IsConcat(N0.getOperand(1), Lo1, Hi1)) { | ||||||
4020 | return MergeConcat(DAG.getNode(N0.getOpcode(), dl, OpVT, Lo0, Lo1), | ||||||
4021 | DAG.getNode(N0.getOpcode(), dl, OpVT, Hi0, Hi1)); | ||||||
4022 | } | ||||||
4023 | } | ||||||
4024 | } | ||||||
4025 | } | ||||||
4026 | |||||||
4027 | // If we have "setcc X, C0", check to see if we can shrink the immediate | ||||||
4028 | // by changing cc. | ||||||
4029 | // TODO: Support this for vectors after legalize ops. | ||||||
4030 | if (!VT.isVector() || DCI.isBeforeLegalizeOps()) { | ||||||
4031 | // SETUGT X, SINTMAX -> SETLT X, 0 | ||||||
4032 | // SETUGE X, SINTMIN -> SETLT X, 0 | ||||||
4033 | if ((Cond == ISD::SETUGT && C1.isMaxSignedValue()) || | ||||||
4034 | (Cond == ISD::SETUGE && C1.isMinSignedValue())) | ||||||
4035 | return DAG.getSetCC(dl, VT, N0, | ||||||
4036 | DAG.getConstant(0, dl, N1.getValueType()), | ||||||
4037 | ISD::SETLT); | ||||||
4038 | |||||||
4039 | // SETULT X, SINTMIN -> SETGT X, -1 | ||||||
4040 | // SETULE X, SINTMAX -> SETGT X, -1 | ||||||
4041 | if ((Cond == ISD::SETULT && C1.isMinSignedValue()) || | ||||||
4042 | (Cond == ISD::SETULE && C1.isMaxSignedValue())) | ||||||
4043 | return DAG.getSetCC(dl, VT, N0, | ||||||
4044 | DAG.getAllOnesConstant(dl, N1.getValueType()), | ||||||
4045 | ISD::SETGT); | ||||||
4046 | } | ||||||
4047 | } | ||||||
4048 | |||||||
4049 | // Back to non-vector simplifications. | ||||||
4050 | // TODO: Can we do these for vector splats? | ||||||
4051 | if (auto *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) { | ||||||
4052 | const TargetLowering &TLI = DAG.getTargetLoweringInfo(); | ||||||
4053 | const APInt &C1 = N1C->getAPIntValue(); | ||||||
4054 | EVT ShValTy = N0.getValueType(); | ||||||
4055 | |||||||
4056 | // Fold bit comparisons when we can. This will result in an | ||||||
4057 | // incorrect value when boolean false is negative one, unless | ||||||
4058 | // the bitsize is 1 in which case the false value is the same | ||||||
4059 | // in practice regardless of the representation. | ||||||
4060 | if ((VT.getSizeInBits() == 1 || | ||||||
4061 | getBooleanContents(N0.getValueType()) == ZeroOrOneBooleanContent) && | ||||||
4062 | (Cond == ISD::SETEQ || Cond == ISD::SETNE) && | ||||||
4063 | (VT == ShValTy || (isTypeLegal(VT) && VT.bitsLE(ShValTy))) && | ||||||
4064 | N0.getOpcode() == ISD::AND) { | ||||||
4065 | if (auto *AndRHS = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { | ||||||
4066 | EVT ShiftTy = | ||||||
4067 | getShiftAmountTy(ShValTy, Layout, !DCI.isBeforeLegalize()); | ||||||
4068 | if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3 | ||||||
4069 | // Perform the xform if the AND RHS is a single bit. | ||||||
4070 | unsigned ShCt = AndRHS->getAPIntValue().logBase2(); | ||||||
4071 | if (AndRHS->getAPIntValue().isPowerOf2() && | ||||||
4072 | !TLI.shouldAvoidTransformToShift(ShValTy, ShCt)) { | ||||||
4073 | return DAG.getNode(ISD::TRUNCATE, dl, VT, | ||||||
4074 | DAG.getNode(ISD::SRL, dl, ShValTy, N0, | ||||||
4075 | DAG.getConstant(ShCt, dl, ShiftTy))); | ||||||
4076 | } | ||||||
4077 | } else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) { | ||||||
4078 | // (X & 8) == 8 --> (X & 8) >> 3 | ||||||
4079 | // Perform the xform if C1 is a single bit. | ||||||
4080 | unsigned ShCt = C1.logBase2(); | ||||||
4081 | if (C1.isPowerOf2() && | ||||||
4082 | !TLI.shouldAvoidTransformToShift(ShValTy, ShCt)) { | ||||||
4083 | return DAG.getNode(ISD::TRUNCATE, dl, VT, | ||||||
4084 | DAG.getNode(ISD::SRL, dl, ShValTy, N0, | ||||||
4085 | DAG.getConstant(ShCt, dl, ShiftTy))); | ||||||
4086 | } | ||||||
4087 | } | ||||||
4088 | } | ||||||
4089 | } | ||||||
4090 | |||||||
4091 | if (C1.getMinSignedBits() <= 64 && | ||||||
4092 | !isLegalICmpImmediate(C1.getSExtValue())) { | ||||||
4093 | EVT ShiftTy = getShiftAmountTy(ShValTy, Layout, !DCI.isBeforeLegalize()); | ||||||
4094 | // (X & -256) == 256 -> (X >> 8) == 1 | ||||||
4095 | if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && | ||||||
4096 | N0.getOpcode() == ISD::AND && N0.hasOneUse()) { | ||||||
4097 | if (auto *AndRHS = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { | ||||||
4098 | const APInt &AndRHSC = AndRHS->getAPIntValue(); | ||||||
4099 | if ((-AndRHSC).isPowerOf2() && (AndRHSC & C1) == C1) { | ||||||
4100 | unsigned ShiftBits = AndRHSC.countTrailingZeros(); | ||||||
4101 | if (!TLI.shouldAvoidTransformToShift(ShValTy, ShiftBits)) { | ||||||
4102 | SDValue Shift = | ||||||
4103 | DAG.getNode(ISD::SRL, dl, ShValTy, N0.getOperand(0), | ||||||
4104 | DAG.getConstant(ShiftBits, dl, ShiftTy)); | ||||||
4105 | SDValue CmpRHS = DAG.getConstant(C1.lshr(ShiftBits), dl, ShValTy); | ||||||
4106 | return DAG.getSetCC(dl, VT, Shift, CmpRHS, Cond); | ||||||
4107 | } | ||||||
4108 | } | ||||||
4109 | } | ||||||
4110 | } else if (Cond == ISD::SETULT || Cond == ISD::SETUGE || | ||||||
4111 | Cond == ISD::SETULE || Cond == ISD::SETUGT) { | ||||||
4112 | bool AdjOne = (Cond == ISD::SETULE || Cond == ISD::SETUGT); | ||||||
4113 | // X < 0x100000000 -> (X >> 32) < 1 | ||||||
4114 | // X >= 0x100000000 -> (X >> 32) >= 1 | ||||||
4115 | // X <= 0x0ffffffff -> (X >> 32) < 1 | ||||||
4116 | // X > 0x0ffffffff -> (X >> 32) >= 1 | ||||||
4117 | unsigned ShiftBits; | ||||||
4118 | APInt NewC = C1; | ||||||
4119 | ISD::CondCode NewCond = Cond; | ||||||
4120 | if (AdjOne) { | ||||||
4121 | ShiftBits = C1.countTrailingOnes(); | ||||||
4122 | NewC = NewC + 1; | ||||||
4123 | NewCond = (Cond == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE; | ||||||
4124 | } else { | ||||||
4125 | ShiftBits = C1.countTrailingZeros(); | ||||||
4126 | } | ||||||
4127 | NewC.lshrInPlace(ShiftBits); | ||||||
4128 | if (ShiftBits && NewC.getMinSignedBits() <= 64 && | ||||||
4129 | isLegalICmpImmediate(NewC.getSExtValue()) && | ||||||
4130 | !TLI.shouldAvoidTransformToShift(ShValTy, ShiftBits)) { | ||||||
4131 | SDValue Shift = DAG.getNode(ISD::SRL, dl, ShValTy, N0, | ||||||
4132 | DAG.getConstant(ShiftBits, dl, ShiftTy)); | ||||||
4133 | SDValue CmpRHS = DAG.getConstant(NewC, dl, ShValTy); | ||||||
4134 | return DAG.getSetCC(dl, VT, Shift, CmpRHS, NewCond); | ||||||
4135 | } | ||||||
4136 | } | ||||||
4137 | } | ||||||
4138 | } | ||||||
4139 | |||||||
4140 | if (!isa<ConstantFPSDNode>(N0) && isa<ConstantFPSDNode>(N1)) { | ||||||
4141 | auto *CFP = cast<ConstantFPSDNode>(N1); | ||||||
4142 | assert(!CFP->getValueAPF().isNaN() && "Unexpected NaN value")((!CFP->getValueAPF().isNaN() && "Unexpected NaN value" ) ? static_cast<void> (0) : __assert_fail ("!CFP->getValueAPF().isNaN() && \"Unexpected NaN value\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 4142, __PRETTY_FUNCTION__)); | ||||||
4143 | |||||||
4144 | // Otherwise, we know the RHS is not a NaN. Simplify the node to drop the | ||||||
4145 | // constant if knowing that the operand is non-nan is enough. We prefer to | ||||||
4146 | // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to | ||||||
4147 | // materialize 0.0. | ||||||
4148 | if (Cond == ISD::SETO || Cond == ISD::SETUO) | ||||||
4149 | return DAG.getSetCC(dl, VT, N0, N0, Cond); | ||||||
4150 | |||||||
4151 | // setcc (fneg x), C -> setcc swap(pred) x, -C | ||||||
4152 | if (N0.getOpcode() == ISD::FNEG) { | ||||||
4153 | ISD::CondCode SwapCond = ISD::getSetCCSwappedOperands(Cond); | ||||||
4154 | if (DCI.isBeforeLegalizeOps() || | ||||||
4155 | isCondCodeLegal(SwapCond, N0.getSimpleValueType())) { | ||||||
4156 | SDValue NegN1 = DAG.getNode(ISD::FNEG, dl, N0.getValueType(), N1); | ||||||
4157 | return DAG.getSetCC(dl, VT, N0.getOperand(0), NegN1, SwapCond); | ||||||
4158 | } | ||||||
4159 | } | ||||||
4160 | |||||||
4161 | // If the condition is not legal, see if we can find an equivalent one | ||||||
4162 | // which is legal. | ||||||
4163 | if (!isCondCodeLegal(Cond, N0.getSimpleValueType())) { | ||||||
4164 | // If the comparison was an awkward floating-point == or != and one of | ||||||
4165 | // the comparison operands is infinity or negative infinity, convert the | ||||||
4166 | // condition to a less-awkward <= or >=. | ||||||
4167 | if (CFP->getValueAPF().isInfinity()) { | ||||||
4168 | bool IsNegInf = CFP->getValueAPF().isNegative(); | ||||||
4169 | ISD::CondCode NewCond = ISD::SETCC_INVALID; | ||||||
4170 | switch (Cond) { | ||||||
4171 | case ISD::SETOEQ: NewCond = IsNegInf ? ISD::SETOLE : ISD::SETOGE; break; | ||||||
4172 | case ISD::SETUEQ: NewCond = IsNegInf ? ISD::SETULE : ISD::SETUGE; break; | ||||||
4173 | case ISD::SETUNE: NewCond = IsNegInf ? ISD::SETUGT : ISD::SETULT; break; | ||||||
4174 | case ISD::SETONE: NewCond = IsNegInf ? ISD::SETOGT : ISD::SETOLT; break; | ||||||
4175 | default: break; | ||||||
4176 | } | ||||||
4177 | if (NewCond != ISD::SETCC_INVALID && | ||||||
4178 | isCondCodeLegal(NewCond, N0.getSimpleValueType())) | ||||||
4179 | return DAG.getSetCC(dl, VT, N0, N1, NewCond); | ||||||
4180 | } | ||||||
4181 | } | ||||||
4182 | } | ||||||
4183 | |||||||
4184 | if (N0 == N1) { | ||||||
4185 | // The sext(setcc()) => setcc() optimization relies on the appropriate | ||||||
4186 | // constant being emitted. | ||||||
4187 | assert(!N0.getValueType().isInteger() &&((!N0.getValueType().isInteger() && "Integer types should be handled by FoldSetCC" ) ? static_cast<void> (0) : __assert_fail ("!N0.getValueType().isInteger() && \"Integer types should be handled by FoldSetCC\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 4188, __PRETTY_FUNCTION__)) | ||||||
4188 | "Integer types should be handled by FoldSetCC")((!N0.getValueType().isInteger() && "Integer types should be handled by FoldSetCC" ) ? static_cast<void> (0) : __assert_fail ("!N0.getValueType().isInteger() && \"Integer types should be handled by FoldSetCC\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 4188, __PRETTY_FUNCTION__)); | ||||||
4189 | |||||||
4190 | bool EqTrue = ISD::isTrueWhenEqual(Cond); | ||||||
4191 | unsigned UOF = ISD::getUnorderedFlavor(Cond); | ||||||
4192 | if (UOF == 2) // FP operators that are undefined on NaNs. | ||||||
4193 | return DAG.getBoolConstant(EqTrue, dl, VT, OpVT); | ||||||
4194 | if (UOF == unsigned(EqTrue)) | ||||||
4195 | return DAG.getBoolConstant(EqTrue, dl, VT, OpVT); | ||||||
4196 | // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO | ||||||
4197 | // if it is not already. | ||||||
4198 | ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO; | ||||||
4199 | if (NewCond != Cond && | ||||||
4200 | (DCI.isBeforeLegalizeOps() || | ||||||
4201 | isCondCodeLegal(NewCond, N0.getSimpleValueType()))) | ||||||
4202 | return DAG.getSetCC(dl, VT, N0, N1, NewCond); | ||||||
4203 | } | ||||||
4204 | |||||||
4205 | if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && | ||||||
4206 | N0.getValueType().isInteger()) { | ||||||
4207 | if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB || | ||||||
4208 | N0.getOpcode() == ISD::XOR) { | ||||||
4209 | // Simplify (X+Y) == (X+Z) --> Y == Z | ||||||
4210 | if (N0.getOpcode() == N1.getOpcode()) { | ||||||
4211 | if (N0.getOperand(0) == N1.getOperand(0)) | ||||||
4212 | return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond); | ||||||
4213 | if (N0.getOperand(1) == N1.getOperand(1)) | ||||||
4214 | return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond); | ||||||
4215 | if (isCommutativeBinOp(N0.getOpcode())) { | ||||||
4216 | // If X op Y == Y op X, try other combinations. | ||||||
4217 | if (N0.getOperand(0) == N1.getOperand(1)) | ||||||
4218 | return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0), | ||||||
4219 | Cond); | ||||||
4220 | if (N0.getOperand(1) == N1.getOperand(0)) | ||||||
4221 | return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1), | ||||||
4222 | Cond); | ||||||
4223 | } | ||||||
4224 | } | ||||||
4225 | |||||||
4226 | // If RHS is a legal immediate value for a compare instruction, we need | ||||||
4227 | // to be careful about increasing register pressure needlessly. | ||||||
4228 | bool LegalRHSImm = false; | ||||||
4229 | |||||||
4230 | if (auto *RHSC = dyn_cast<ConstantSDNode>(N1)) { | ||||||
4231 | if (auto *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { | ||||||
4232 | // Turn (X+C1) == C2 --> X == C2-C1 | ||||||
4233 | if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) { | ||||||
4234 | return DAG.getSetCC(dl, VT, N0.getOperand(0), | ||||||
4235 | DAG.getConstant(RHSC->getAPIntValue()- | ||||||
4236 | LHSR->getAPIntValue(), | ||||||
4237 | dl, N0.getValueType()), Cond); | ||||||
4238 | } | ||||||
4239 | |||||||
4240 | // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0. | ||||||
4241 | if (N0.getOpcode() == ISD::XOR) | ||||||
4242 | // If we know that all of the inverted bits are zero, don't bother | ||||||
4243 | // performing the inversion. | ||||||
4244 | if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue())) | ||||||
4245 | return | ||||||
4246 | DAG.getSetCC(dl, VT, N0.getOperand(0), | ||||||
4247 | DAG.getConstant(LHSR->getAPIntValue() ^ | ||||||
4248 | RHSC->getAPIntValue(), | ||||||
4249 | dl, N0.getValueType()), | ||||||
4250 | Cond); | ||||||
4251 | } | ||||||
4252 | |||||||
4253 | // Turn (C1-X) == C2 --> X == C1-C2 | ||||||
4254 | if (auto *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) { | ||||||
4255 | if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) { | ||||||
4256 | return | ||||||
4257 | DAG.getSetCC(dl, VT, N0.getOperand(1), | ||||||
4258 | DAG.getConstant(SUBC->getAPIntValue() - | ||||||
4259 | RHSC->getAPIntValue(), | ||||||
4260 | dl, N0.getValueType()), | ||||||
4261 | Cond); | ||||||
4262 | } | ||||||
4263 | } | ||||||
4264 | |||||||
4265 | // Could RHSC fold directly into a compare? | ||||||
4266 | if (RHSC->getValueType(0).getSizeInBits() <= 64) | ||||||
4267 | LegalRHSImm = isLegalICmpImmediate(RHSC->getSExtValue()); | ||||||
4268 | } | ||||||
4269 | |||||||
4270 | // (X+Y) == X --> Y == 0 and similar folds. | ||||||
4271 | // Don't do this if X is an immediate that can fold into a cmp | ||||||
4272 | // instruction and X+Y has other uses. It could be an induction variable | ||||||
4273 | // chain, and the transform would increase register pressure. | ||||||
4274 | if (!LegalRHSImm || N0.hasOneUse()) | ||||||
4275 | if (SDValue V = foldSetCCWithBinOp(VT, N0, N1, Cond, dl, DCI)) | ||||||
4276 | return V; | ||||||
4277 | } | ||||||
4278 | |||||||
4279 | if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB || | ||||||
4280 | N1.getOpcode() == ISD::XOR) | ||||||
4281 | if (SDValue V = foldSetCCWithBinOp(VT, N1, N0, Cond, dl, DCI)) | ||||||
4282 | return V; | ||||||
4283 | |||||||
4284 | if (SDValue V = foldSetCCWithAnd(VT, N0, N1, Cond, dl, DCI)) | ||||||
4285 | return V; | ||||||
4286 | } | ||||||
4287 | |||||||
4288 | // Fold remainder of division by a constant. | ||||||
4289 | if ((N0.getOpcode() == ISD::UREM || N0.getOpcode() == ISD::SREM) && | ||||||
4290 | N0.hasOneUse() && (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { | ||||||
4291 | AttributeList Attr = DAG.getMachineFunction().getFunction().getAttributes(); | ||||||
4292 | |||||||
4293 | // When division is cheap or optimizing for minimum size, | ||||||
4294 | // fall through to DIVREM creation by skipping this fold. | ||||||
4295 | if (!isIntDivCheap(VT, Attr) && !Attr.hasFnAttribute(Attribute::MinSize)) { | ||||||
4296 | if (N0.getOpcode() == ISD::UREM) { | ||||||
4297 | if (SDValue Folded = buildUREMEqFold(VT, N0, N1, Cond, DCI, dl)) | ||||||
4298 | return Folded; | ||||||
4299 | } else if (N0.getOpcode() == ISD::SREM) { | ||||||
4300 | if (SDValue Folded = buildSREMEqFold(VT, N0, N1, Cond, DCI, dl)) | ||||||
4301 | return Folded; | ||||||
4302 | } | ||||||
4303 | } | ||||||
4304 | } | ||||||
4305 | |||||||
4306 | // Fold away ALL boolean setcc's. | ||||||
4307 | if (N0.getValueType().getScalarType() == MVT::i1 && foldBooleans) { | ||||||
4308 | SDValue Temp; | ||||||
4309 | switch (Cond) { | ||||||
4310 | default: llvm_unreachable("Unknown integer setcc!")::llvm::llvm_unreachable_internal("Unknown integer setcc!", "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 4310); | ||||||
4311 | case ISD::SETEQ: // X == Y -> ~(X^Y) | ||||||
4312 | Temp = DAG.getNode(ISD::XOR, dl, OpVT, N0, N1); | ||||||
4313 | N0 = DAG.getNOT(dl, Temp, OpVT); | ||||||
4314 | if (!DCI.isCalledByLegalizer()) | ||||||
4315 | DCI.AddToWorklist(Temp.getNode()); | ||||||
4316 | break; | ||||||
4317 | case ISD::SETNE: // X != Y --> (X^Y) | ||||||
4318 | N0 = DAG.getNode(ISD::XOR, dl, OpVT, N0, N1); | ||||||
4319 | break; | ||||||
4320 | case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y | ||||||
4321 | case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y | ||||||
4322 | Temp = DAG.getNOT(dl, N0, OpVT); | ||||||
4323 | N0 = DAG.getNode(ISD::AND, dl, OpVT, N1, Temp); | ||||||
4324 | if (!DCI.isCalledByLegalizer()) | ||||||
4325 | DCI.AddToWorklist(Temp.getNode()); | ||||||
4326 | break; | ||||||
4327 | case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X | ||||||
4328 | case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X | ||||||
4329 | Temp = DAG.getNOT(dl, N1, OpVT); | ||||||
4330 | N0 = DAG.getNode(ISD::AND, dl, OpVT, N0, Temp); | ||||||
4331 | if (!DCI.isCalledByLegalizer()) | ||||||
4332 | DCI.AddToWorklist(Temp.getNode()); | ||||||
4333 | break; | ||||||
4334 | case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y | ||||||
4335 | case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y | ||||||
4336 | Temp = DAG.getNOT(dl, N0, OpVT); | ||||||
4337 | N0 = DAG.getNode(ISD::OR, dl, OpVT, N1, Temp); | ||||||
4338 | if (!DCI.isCalledByLegalizer()) | ||||||
4339 | DCI.AddToWorklist(Temp.getNode()); | ||||||
4340 | break; | ||||||
4341 | case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X | ||||||
4342 | case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X | ||||||
4343 | Temp = DAG.getNOT(dl, N1, OpVT); | ||||||
4344 | N0 = DAG.getNode(ISD::OR, dl, OpVT, N0, Temp); | ||||||
4345 | break; | ||||||
4346 | } | ||||||
4347 | if (VT.getScalarType() != MVT::i1) { | ||||||
4348 | if (!DCI.isCalledByLegalizer()) | ||||||
4349 | DCI.AddToWorklist(N0.getNode()); | ||||||
4350 | // FIXME: If running after legalize, we probably can't do this. | ||||||
4351 | ISD::NodeType ExtendCode = getExtendForContent(getBooleanContents(OpVT)); | ||||||
4352 | N0 = DAG.getNode(ExtendCode, dl, VT, N0); | ||||||
4353 | } | ||||||
4354 | return N0; | ||||||
4355 | } | ||||||
4356 | |||||||
4357 | // Could not fold it. | ||||||
4358 | return SDValue(); | ||||||
4359 | } | ||||||
4360 | |||||||
4361 | /// Returns true (and the GlobalValue and the offset) if the node is a | ||||||
4362 | /// GlobalAddress + offset. | ||||||
4363 | bool TargetLowering::isGAPlusOffset(SDNode *WN, const GlobalValue *&GA, | ||||||
4364 | int64_t &Offset) const { | ||||||
4365 | |||||||
4366 | SDNode *N = unwrapAddress(SDValue(WN, 0)).getNode(); | ||||||
4367 | |||||||
4368 | if (auto *GASD = dyn_cast<GlobalAddressSDNode>(N)) { | ||||||
4369 | GA = GASD->getGlobal(); | ||||||
4370 | Offset += GASD->getOffset(); | ||||||
4371 | return true; | ||||||
4372 | } | ||||||
4373 | |||||||
4374 | if (N->getOpcode() == ISD::ADD) { | ||||||
4375 | SDValue N1 = N->getOperand(0); | ||||||
4376 | SDValue N2 = N->getOperand(1); | ||||||
4377 | if (isGAPlusOffset(N1.getNode(), GA, Offset)) { | ||||||
4378 | if (auto *V = dyn_cast<ConstantSDNode>(N2)) { | ||||||
4379 | Offset += V->getSExtValue(); | ||||||
4380 | return true; | ||||||
4381 | } | ||||||
4382 | } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) { | ||||||
4383 | if (auto *V = dyn_cast<ConstantSDNode>(N1)) { | ||||||
4384 | Offset += V->getSExtValue(); | ||||||
4385 | return true; | ||||||
4386 | } | ||||||
4387 | } | ||||||
4388 | } | ||||||
4389 | |||||||
4390 | return false; | ||||||
4391 | } | ||||||
4392 | |||||||
4393 | SDValue TargetLowering::PerformDAGCombine(SDNode *N, | ||||||
4394 | DAGCombinerInfo &DCI) const { | ||||||
4395 | // Default implementation: no optimization. | ||||||
4396 | return SDValue(); | ||||||
4397 | } | ||||||
4398 | |||||||
4399 | //===----------------------------------------------------------------------===// | ||||||
4400 | // Inline Assembler Implementation Methods | ||||||
4401 | //===----------------------------------------------------------------------===// | ||||||
4402 | |||||||
4403 | TargetLowering::ConstraintType | ||||||
4404 | TargetLowering::getConstraintType(StringRef Constraint) const { | ||||||
4405 | unsigned S = Constraint.size(); | ||||||
4406 | |||||||
4407 | if (S == 1) { | ||||||
4408 | switch (Constraint[0]) { | ||||||
4409 | default: break; | ||||||
4410 | case 'r': | ||||||
4411 | return C_RegisterClass; | ||||||
4412 | case 'm': // memory | ||||||
4413 | case 'o': // offsetable | ||||||
4414 | case 'V': // not offsetable | ||||||
4415 | return C_Memory; | ||||||
4416 | case 'n': // Simple Integer | ||||||
4417 | case 'E': // Floating Point Constant | ||||||
4418 | case 'F': // Floating Point Constant | ||||||
4419 | return C_Immediate; | ||||||
4420 | case 'i': // Simple Integer or Relocatable Constant | ||||||
4421 | case 's': // Relocatable Constant | ||||||
4422 | case 'p': // Address. | ||||||
4423 | case 'X': // Allow ANY value. | ||||||
4424 | case 'I': // Target registers. | ||||||
4425 | case 'J': | ||||||
4426 | case 'K': | ||||||
4427 | case 'L': | ||||||
4428 | case 'M': | ||||||
4429 | case 'N': | ||||||
4430 | case 'O': | ||||||
4431 | case 'P': | ||||||
4432 | case '<': | ||||||
4433 | case '>': | ||||||
4434 | return C_Other; | ||||||
4435 | } | ||||||
4436 | } | ||||||
4437 | |||||||
4438 | if (S > 1 && Constraint[0] == '{' && Constraint[S - 1] == '}') { | ||||||
4439 | if (S == 8 && Constraint.substr(1, 6) == "memory") // "{memory}" | ||||||
4440 | return C_Memory; | ||||||
4441 | return C_Register; | ||||||
4442 | } | ||||||
4443 | return C_Unknown; | ||||||
4444 | } | ||||||
4445 | |||||||
4446 | /// Try to replace an X constraint, which matches anything, with another that | ||||||
4447 | /// has more specific requirements based on the type of the corresponding | ||||||
4448 | /// operand. | ||||||
4449 | const char *TargetLowering::LowerXConstraint(EVT ConstraintVT) const { | ||||||
4450 | if (ConstraintVT.isInteger()) | ||||||
4451 | return "r"; | ||||||
4452 | if (ConstraintVT.isFloatingPoint()) | ||||||
4453 | return "f"; // works for many targets | ||||||
4454 | return nullptr; | ||||||
4455 | } | ||||||
4456 | |||||||
4457 | SDValue TargetLowering::LowerAsmOutputForConstraint( | ||||||
4458 | SDValue &Chain, SDValue &Flag, const SDLoc &DL, | ||||||
4459 | const AsmOperandInfo &OpInfo, SelectionDAG &DAG) const { | ||||||
4460 | return SDValue(); | ||||||
4461 | } | ||||||
4462 | |||||||
4463 | /// Lower the specified operand into the Ops vector. | ||||||
4464 | /// If it is invalid, don't add anything to Ops. | ||||||
4465 | void TargetLowering::LowerAsmOperandForConstraint(SDValue Op, | ||||||
4466 | std::string &Constraint, | ||||||
4467 | std::vector<SDValue> &Ops, | ||||||
4468 | SelectionDAG &DAG) const { | ||||||
4469 | |||||||
4470 | if (Constraint.length() > 1) return; | ||||||
4471 | |||||||
4472 | char ConstraintLetter = Constraint[0]; | ||||||
4473 | switch (ConstraintLetter) { | ||||||
4474 | default: break; | ||||||
4475 | case 'X': // Allows any operand; labels (basic block) use this. | ||||||
4476 | if (Op.getOpcode() == ISD::BasicBlock || | ||||||
4477 | Op.getOpcode() == ISD::TargetBlockAddress) { | ||||||
4478 | Ops.push_back(Op); | ||||||
4479 | return; | ||||||
4480 | } | ||||||
4481 | LLVM_FALLTHROUGH[[gnu::fallthrough]]; | ||||||
4482 | case 'i': // Simple Integer or Relocatable Constant | ||||||
4483 | case 'n': // Simple Integer | ||||||
4484 | case 's': { // Relocatable Constant | ||||||
4485 | |||||||
4486 | GlobalAddressSDNode *GA; | ||||||
4487 | ConstantSDNode *C; | ||||||
4488 | BlockAddressSDNode *BA; | ||||||
4489 | uint64_t Offset = 0; | ||||||
4490 | |||||||
4491 | // Match (GA) or (C) or (GA+C) or (GA-C) or ((GA+C)+C) or (((GA+C)+C)+C), | ||||||
4492 | // etc., since getelementpointer is variadic. We can't use | ||||||
4493 | // SelectionDAG::FoldSymbolOffset because it expects the GA to be accessible | ||||||
4494 | // while in this case the GA may be furthest from the root node which is | ||||||
4495 | // likely an ISD::ADD. | ||||||
4496 | while (1) { | ||||||
4497 | if ((GA = dyn_cast<GlobalAddressSDNode>(Op)) && ConstraintLetter != 'n') { | ||||||
4498 | Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(), SDLoc(Op), | ||||||
4499 | GA->getValueType(0), | ||||||
4500 | Offset + GA->getOffset())); | ||||||
4501 | return; | ||||||
4502 | } else if ((C = dyn_cast<ConstantSDNode>(Op)) && | ||||||
4503 | ConstraintLetter != 's') { | ||||||
4504 | // gcc prints these as sign extended. Sign extend value to 64 bits | ||||||
4505 | // now; without this it would get ZExt'd later in | ||||||
4506 | // ScheduleDAGSDNodes::EmitNode, which is very generic. | ||||||
4507 | bool IsBool = C->getConstantIntValue()->getBitWidth() == 1; | ||||||
4508 | BooleanContent BCont = getBooleanContents(MVT::i64); | ||||||
4509 | ISD::NodeType ExtOpc = IsBool ? getExtendForContent(BCont) | ||||||
4510 | : ISD::SIGN_EXTEND; | ||||||
4511 | int64_t ExtVal = ExtOpc == ISD::ZERO_EXTEND ? C->getZExtValue() | ||||||
4512 | : C->getSExtValue(); | ||||||
4513 | Ops.push_back(DAG.getTargetConstant(Offset + ExtVal, | ||||||
4514 | SDLoc(C), MVT::i64)); | ||||||
4515 | return; | ||||||
4516 | } else if ((BA = dyn_cast<BlockAddressSDNode>(Op)) && | ||||||
4517 | ConstraintLetter != 'n') { | ||||||
4518 | Ops.push_back(DAG.getTargetBlockAddress( | ||||||
4519 | BA->getBlockAddress(), BA->getValueType(0), | ||||||
4520 | Offset + BA->getOffset(), BA->getTargetFlags())); | ||||||
4521 | return; | ||||||
4522 | } else { | ||||||
4523 | const unsigned OpCode = Op.getOpcode(); | ||||||
4524 | if (OpCode == ISD::ADD || OpCode == ISD::SUB) { | ||||||
4525 | if ((C = dyn_cast<ConstantSDNode>(Op.getOperand(0)))) | ||||||
4526 | Op = Op.getOperand(1); | ||||||
4527 | // Subtraction is not commutative. | ||||||
4528 | else if (OpCode == ISD::ADD && | ||||||
4529 | (C = dyn_cast<ConstantSDNode>(Op.getOperand(1)))) | ||||||
4530 | Op = Op.getOperand(0); | ||||||
4531 | else | ||||||
4532 | return; | ||||||
4533 | Offset += (OpCode == ISD::ADD ? 1 : -1) * C->getSExtValue(); | ||||||
4534 | continue; | ||||||
4535 | } | ||||||
4536 | } | ||||||
4537 | return; | ||||||
4538 | } | ||||||
4539 | break; | ||||||
4540 | } | ||||||
4541 | } | ||||||
4542 | } | ||||||
4543 | |||||||
4544 | std::pair<unsigned, const TargetRegisterClass *> | ||||||
4545 | TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *RI, | ||||||
4546 | StringRef Constraint, | ||||||
4547 | MVT VT) const { | ||||||
4548 | if (Constraint.empty() || Constraint[0] != '{') | ||||||
4549 | return std::make_pair(0u, static_cast<TargetRegisterClass *>(nullptr)); | ||||||
4550 | assert(*(Constraint.end() - 1) == '}' && "Not a brace enclosed constraint?")((*(Constraint.end() - 1) == '}' && "Not a brace enclosed constraint?" ) ? static_cast<void> (0) : __assert_fail ("*(Constraint.end() - 1) == '}' && \"Not a brace enclosed constraint?\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 4550, __PRETTY_FUNCTION__)); | ||||||
4551 | |||||||
4552 | // Remove the braces from around the name. | ||||||
4553 | StringRef RegName(Constraint.data() + 1, Constraint.size() - 2); | ||||||
4554 | |||||||
4555 | std::pair<unsigned, const TargetRegisterClass *> R = | ||||||
4556 | std::make_pair(0u, static_cast<const TargetRegisterClass *>(nullptr)); | ||||||
4557 | |||||||
4558 | // Figure out which register class contains this reg. | ||||||
4559 | for (const TargetRegisterClass *RC : RI->regclasses()) { | ||||||
4560 | // If none of the value types for this register class are valid, we | ||||||
4561 | // can't use it. For example, 64-bit reg classes on 32-bit targets. | ||||||
4562 | if (!isLegalRC(*RI, *RC)) | ||||||
4563 | continue; | ||||||
4564 | |||||||
4565 | for (const MCPhysReg &PR : *RC) { | ||||||
4566 | if (RegName.equals_lower(RI->getRegAsmName(PR))) { | ||||||
4567 | std::pair<unsigned, const TargetRegisterClass *> S = | ||||||
4568 | std::make_pair(PR, RC); | ||||||
4569 | |||||||
4570 | // If this register class has the requested value type, return it, | ||||||
4571 | // otherwise keep searching and return the first class found | ||||||
4572 | // if no other is found which explicitly has the requested type. | ||||||
4573 | if (RI->isTypeLegalForClass(*RC, VT)) | ||||||
4574 | return S; | ||||||
4575 | if (!R.second) | ||||||
4576 | R = S; | ||||||
4577 | } | ||||||
4578 | } | ||||||
4579 | } | ||||||
4580 | |||||||
4581 | return R; | ||||||
4582 | } | ||||||
4583 | |||||||
4584 | //===----------------------------------------------------------------------===// | ||||||
4585 | // Constraint Selection. | ||||||
4586 | |||||||
4587 | /// Return true of this is an input operand that is a matching constraint like | ||||||
4588 | /// "4". | ||||||
4589 | bool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const { | ||||||
4590 | assert(!ConstraintCode.empty() && "No known constraint!")((!ConstraintCode.empty() && "No known constraint!") ? static_cast<void> (0) : __assert_fail ("!ConstraintCode.empty() && \"No known constraint!\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 4590, __PRETTY_FUNCTION__)); | ||||||
4591 | return isdigit(static_cast<unsigned char>(ConstraintCode[0])); | ||||||
4592 | } | ||||||
4593 | |||||||
4594 | /// If this is an input matching constraint, this method returns the output | ||||||
4595 | /// operand it matches. | ||||||
4596 | unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const { | ||||||
4597 | assert(!ConstraintCode.empty() && "No known constraint!")((!ConstraintCode.empty() && "No known constraint!") ? static_cast<void> (0) : __assert_fail ("!ConstraintCode.empty() && \"No known constraint!\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 4597, __PRETTY_FUNCTION__)); | ||||||
4598 | return atoi(ConstraintCode.c_str()); | ||||||
4599 | } | ||||||
4600 | |||||||
4601 | /// Split up the constraint string from the inline assembly value into the | ||||||
4602 | /// specific constraints and their prefixes, and also tie in the associated | ||||||
4603 | /// operand values. | ||||||
4604 | /// If this returns an empty vector, and if the constraint string itself | ||||||
4605 | /// isn't empty, there was an error parsing. | ||||||
4606 | TargetLowering::AsmOperandInfoVector | ||||||
4607 | TargetLowering::ParseConstraints(const DataLayout &DL, | ||||||
4608 | const TargetRegisterInfo *TRI, | ||||||
4609 | const CallBase &Call) const { | ||||||
4610 | /// Information about all of the constraints. | ||||||
4611 | AsmOperandInfoVector ConstraintOperands; | ||||||
4612 | const InlineAsm *IA = cast<InlineAsm>(Call.getCalledOperand()); | ||||||
4613 | unsigned maCount = 0; // Largest number of multiple alternative constraints. | ||||||
4614 | |||||||
4615 | // Do a prepass over the constraints, canonicalizing them, and building up the | ||||||
4616 | // ConstraintOperands list. | ||||||
4617 | unsigned ArgNo = 0; // ArgNo - The argument of the CallInst. | ||||||
4618 | unsigned ResNo = 0; // ResNo - The result number of the next output. | ||||||
4619 | |||||||
4620 | for (InlineAsm::ConstraintInfo &CI : IA->ParseConstraints()) { | ||||||
4621 | ConstraintOperands.emplace_back(std::move(CI)); | ||||||
4622 | AsmOperandInfo &OpInfo = ConstraintOperands.back(); | ||||||
4623 | |||||||
4624 | // Update multiple alternative constraint count. | ||||||
4625 | if (OpInfo.multipleAlternatives.size() > maCount) | ||||||
4626 | maCount = OpInfo.multipleAlternatives.size(); | ||||||
4627 | |||||||
4628 | OpInfo.ConstraintVT = MVT::Other; | ||||||
4629 | |||||||
4630 | // Compute the value type for each operand. | ||||||
4631 | switch (OpInfo.Type) { | ||||||
4632 | case InlineAsm::isOutput: | ||||||
4633 | // Indirect outputs just consume an argument. | ||||||
4634 | if (OpInfo.isIndirect) { | ||||||
4635 | OpInfo.CallOperandVal = Call.getArgOperand(ArgNo++); | ||||||
4636 | break; | ||||||
4637 | } | ||||||
4638 | |||||||
4639 | // The return value of the call is this value. As such, there is no | ||||||
4640 | // corresponding argument. | ||||||
4641 | assert(!Call.getType()->isVoidTy() && "Bad inline asm!")((!Call.getType()->isVoidTy() && "Bad inline asm!" ) ? static_cast<void> (0) : __assert_fail ("!Call.getType()->isVoidTy() && \"Bad inline asm!\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 4641, __PRETTY_FUNCTION__)); | ||||||
4642 | if (StructType *STy = dyn_cast<StructType>(Call.getType())) { | ||||||
4643 | OpInfo.ConstraintVT = | ||||||
4644 | getSimpleValueType(DL, STy->getElementType(ResNo)); | ||||||
4645 | } else { | ||||||
4646 | assert(ResNo == 0 && "Asm only has one result!")((ResNo == 0 && "Asm only has one result!") ? static_cast <void> (0) : __assert_fail ("ResNo == 0 && \"Asm only has one result!\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 4646, __PRETTY_FUNCTION__)); | ||||||
4647 | OpInfo.ConstraintVT = getSimpleValueType(DL, Call.getType()); | ||||||
4648 | } | ||||||
4649 | ++ResNo; | ||||||
4650 | break; | ||||||
4651 | case InlineAsm::isInput: | ||||||
4652 | OpInfo.CallOperandVal = Call.getArgOperand(ArgNo++); | ||||||
4653 | break; | ||||||
4654 | case InlineAsm::isClobber: | ||||||
4655 | // Nothing to do. | ||||||
4656 | break; | ||||||
4657 | } | ||||||
4658 | |||||||
4659 | if (OpInfo.CallOperandVal) { | ||||||
4660 | llvm::Type *OpTy = OpInfo.CallOperandVal->getType(); | ||||||
4661 | if (OpInfo.isIndirect) { | ||||||
4662 | llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy); | ||||||
4663 | if (!PtrTy) | ||||||
4664 | report_fatal_error("Indirect operand for inline asm not a pointer!"); | ||||||
4665 | OpTy = PtrTy->getElementType(); | ||||||
4666 | } | ||||||
4667 | |||||||
4668 | // Look for vector wrapped in a struct. e.g. { <16 x i8> }. | ||||||
4669 | if (StructType *STy = dyn_cast<StructType>(OpTy)) | ||||||
4670 | if (STy->getNumElements() == 1) | ||||||
4671 | OpTy = STy->getElementType(0); | ||||||
4672 | |||||||
4673 | // If OpTy is not a single value, it may be a struct/union that we | ||||||
4674 | // can tile with integers. | ||||||
4675 | if (!OpTy->isSingleValueType() && OpTy->isSized()) { | ||||||
4676 | unsigned BitSize = DL.getTypeSizeInBits(OpTy); | ||||||
4677 | switch (BitSize) { | ||||||
4678 | default: break; | ||||||
4679 | case 1: | ||||||
4680 | case 8: | ||||||
4681 | case 16: | ||||||
4682 | case 32: | ||||||
4683 | case 64: | ||||||
4684 | case 128: | ||||||
4685 | OpInfo.ConstraintVT = | ||||||
4686 | MVT::getVT(IntegerType::get(OpTy->getContext(), BitSize), true); | ||||||
4687 | break; | ||||||
4688 | } | ||||||
4689 | } else if (PointerType *PT = dyn_cast<PointerType>(OpTy)) { | ||||||
4690 | unsigned PtrSize = DL.getPointerSizeInBits(PT->getAddressSpace()); | ||||||
4691 | OpInfo.ConstraintVT = MVT::getIntegerVT(PtrSize); | ||||||
4692 | } else { | ||||||
4693 | OpInfo.ConstraintVT = MVT::getVT(OpTy, true); | ||||||
4694 | } | ||||||
4695 | } | ||||||
4696 | } | ||||||
4697 | |||||||
4698 | // If we have multiple alternative constraints, select the best alternative. | ||||||
4699 | if (!ConstraintOperands.empty()) { | ||||||
4700 | if (maCount) { | ||||||
4701 | unsigned bestMAIndex = 0; | ||||||
4702 | int bestWeight = -1; | ||||||
4703 | // weight: -1 = invalid match, and 0 = so-so match to 5 = good match. | ||||||
4704 | int weight = -1; | ||||||
4705 | unsigned maIndex; | ||||||
4706 | // Compute the sums of the weights for each alternative, keeping track | ||||||
4707 | // of the best (highest weight) one so far. | ||||||
4708 | for (maIndex = 0; maIndex < maCount; ++maIndex) { | ||||||
4709 | int weightSum = 0; | ||||||
4710 | for (unsigned cIndex = 0, eIndex = ConstraintOperands.size(); | ||||||
4711 | cIndex != eIndex; ++cIndex) { | ||||||
4712 | AsmOperandInfo &OpInfo = ConstraintOperands[cIndex]; | ||||||
4713 | if (OpInfo.Type == InlineAsm::isClobber) | ||||||
4714 | continue; | ||||||
4715 | |||||||
4716 | // If this is an output operand with a matching input operand, | ||||||
4717 | // look up the matching input. If their types mismatch, e.g. one | ||||||
4718 | // is an integer, the other is floating point, or their sizes are | ||||||
4719 | // different, flag it as an maCantMatch. | ||||||
4720 | if (OpInfo.hasMatchingInput()) { | ||||||
4721 | AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput]; | ||||||
4722 | if (OpInfo.ConstraintVT != Input.ConstraintVT) { | ||||||
4723 | if ((OpInfo.ConstraintVT.isInteger() != | ||||||
4724 | Input.ConstraintVT.isInteger()) || | ||||||
4725 | (OpInfo.ConstraintVT.getSizeInBits() != | ||||||
4726 | Input.ConstraintVT.getSizeInBits())) { | ||||||
4727 | weightSum = -1; // Can't match. | ||||||
4728 | break; | ||||||
4729 | } | ||||||
4730 | } | ||||||
4731 | } | ||||||
4732 | weight = getMultipleConstraintMatchWeight(OpInfo, maIndex); | ||||||
4733 | if (weight == -1) { | ||||||
4734 | weightSum = -1; | ||||||
4735 | break; | ||||||
4736 | } | ||||||
4737 | weightSum += weight; | ||||||
4738 | } | ||||||
4739 | // Update best. | ||||||
4740 | if (weightSum > bestWeight) { | ||||||
4741 | bestWeight = weightSum; | ||||||
4742 | bestMAIndex = maIndex; | ||||||
4743 | } | ||||||
4744 | } | ||||||
4745 | |||||||
4746 | // Now select chosen alternative in each constraint. | ||||||
4747 | for (unsigned cIndex = 0, eIndex = ConstraintOperands.size(); | ||||||
4748 | cIndex != eIndex; ++cIndex) { | ||||||
4749 | AsmOperandInfo &cInfo = ConstraintOperands[cIndex]; | ||||||
4750 | if (cInfo.Type == InlineAsm::isClobber) | ||||||
4751 | continue; | ||||||
4752 | cInfo.selectAlternative(bestMAIndex); | ||||||
4753 | } | ||||||
4754 | } | ||||||
4755 | } | ||||||
4756 | |||||||
4757 | // Check and hook up tied operands, choose constraint code to use. | ||||||
4758 | for (unsigned cIndex = 0, eIndex = ConstraintOperands.size(); | ||||||
4759 | cIndex != eIndex; ++cIndex) { | ||||||
4760 | AsmOperandInfo &OpInfo = ConstraintOperands[cIndex]; | ||||||
4761 | |||||||
4762 | // If this is an output operand with a matching input operand, look up the | ||||||
4763 | // matching input. If their types mismatch, e.g. one is an integer, the | ||||||
4764 | // other is floating point, or their sizes are different, flag it as an | ||||||
4765 | // error. | ||||||
4766 | if (OpInfo.hasMatchingInput()) { | ||||||
4767 | AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput]; | ||||||
4768 | |||||||
4769 | if (OpInfo.ConstraintVT != Input.ConstraintVT) { | ||||||
4770 | std::pair<unsigned, const TargetRegisterClass *> MatchRC = | ||||||
4771 | getRegForInlineAsmConstraint(TRI, OpInfo.ConstraintCode, | ||||||
4772 | OpInfo.ConstraintVT); | ||||||
4773 | std::pair<unsigned, const TargetRegisterClass *> InputRC = | ||||||
4774 | getRegForInlineAsmConstraint(TRI, Input.ConstraintCode, | ||||||
4775 | Input.ConstraintVT); | ||||||
4776 | if ((OpInfo.ConstraintVT.isInteger() != | ||||||
4777 | Input.ConstraintVT.isInteger()) || | ||||||
4778 | (MatchRC.second != InputRC.second)) { | ||||||
4779 | report_fatal_error("Unsupported asm: input constraint" | ||||||
4780 | " with a matching output constraint of" | ||||||
4781 | " incompatible type!"); | ||||||
4782 | } | ||||||
4783 | } | ||||||
4784 | } | ||||||
4785 | } | ||||||
4786 | |||||||
4787 | return ConstraintOperands; | ||||||
4788 | } | ||||||
4789 | |||||||
4790 | /// Return an integer indicating how general CT is. | ||||||
4791 | static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) { | ||||||
4792 | switch (CT) { | ||||||
4793 | case TargetLowering::C_Immediate: | ||||||
4794 | case TargetLowering::C_Other: | ||||||
4795 | case TargetLowering::C_Unknown: | ||||||
4796 | return 0; | ||||||
4797 | case TargetLowering::C_Register: | ||||||
4798 | return 1; | ||||||
4799 | case TargetLowering::C_RegisterClass: | ||||||
4800 | return 2; | ||||||
4801 | case TargetLowering::C_Memory: | ||||||
4802 | return 3; | ||||||
4803 | } | ||||||
4804 | llvm_unreachable("Invalid constraint type")::llvm::llvm_unreachable_internal("Invalid constraint type", "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 4804); | ||||||
4805 | } | ||||||
4806 | |||||||
4807 | /// Examine constraint type and operand type and determine a weight value. | ||||||
4808 | /// This object must already have been set up with the operand type | ||||||
4809 | /// and the current alternative constraint selected. | ||||||
4810 | TargetLowering::ConstraintWeight | ||||||
4811 | TargetLowering::getMultipleConstraintMatchWeight( | ||||||
4812 | AsmOperandInfo &info, int maIndex) const { | ||||||
4813 | InlineAsm::ConstraintCodeVector *rCodes; | ||||||
4814 | if (maIndex >= (int)info.multipleAlternatives.size()) | ||||||
4815 | rCodes = &info.Codes; | ||||||
4816 | else | ||||||
4817 | rCodes = &info.multipleAlternatives[maIndex].Codes; | ||||||
4818 | ConstraintWeight BestWeight = CW_Invalid; | ||||||
4819 | |||||||
4820 | // Loop over the options, keeping track of the most general one. | ||||||
4821 | for (unsigned i = 0, e = rCodes->size(); i != e; ++i) { | ||||||
4822 | ConstraintWeight weight = | ||||||
4823 | getSingleConstraintMatchWeight(info, (*rCodes)[i].c_str()); | ||||||
4824 | if (weight > BestWeight) | ||||||
4825 | BestWeight = weight; | ||||||
4826 | } | ||||||
4827 | |||||||
4828 | return BestWeight; | ||||||
4829 | } | ||||||
4830 | |||||||
4831 | /// Examine constraint type and operand type and determine a weight value. | ||||||
4832 | /// This object must already have been set up with the operand type | ||||||
4833 | /// and the current alternative constraint selected. | ||||||
4834 | TargetLowering::ConstraintWeight | ||||||
4835 | TargetLowering::getSingleConstraintMatchWeight( | ||||||
4836 | AsmOperandInfo &info, const char *constraint) const { | ||||||
4837 | ConstraintWeight weight = CW_Invalid; | ||||||
4838 | Value *CallOperandVal = info.CallOperandVal; | ||||||
4839 | // If we don't have a value, we can't do a match, | ||||||
4840 | // but allow it at the lowest weight. | ||||||
4841 | if (!CallOperandVal) | ||||||
4842 | return CW_Default; | ||||||
4843 | // Look at the constraint type. | ||||||
4844 | switch (*constraint) { | ||||||
4845 | case 'i': // immediate integer. | ||||||
4846 | case 'n': // immediate integer with a known value. | ||||||
4847 | if (isa<ConstantInt>(CallOperandVal)) | ||||||
4848 | weight = CW_Constant; | ||||||
4849 | break; | ||||||
4850 | case 's': // non-explicit intregal immediate. | ||||||
4851 | if (isa<GlobalValue>(CallOperandVal)) | ||||||
4852 | weight = CW_Constant; | ||||||
4853 | break; | ||||||
4854 | case 'E': // immediate float if host format. | ||||||
4855 | case 'F': // immediate float. | ||||||
4856 | if (isa<ConstantFP>(CallOperandVal)) | ||||||
4857 | weight = CW_Constant; | ||||||
4858 | break; | ||||||
4859 | case '<': // memory operand with autodecrement. | ||||||
4860 | case '>': // memory operand with autoincrement. | ||||||
4861 | case 'm': // memory operand. | ||||||
4862 | case 'o': // offsettable memory operand | ||||||
4863 | case 'V': // non-offsettable memory operand | ||||||
4864 | weight = CW_Memory; | ||||||
4865 | break; | ||||||
4866 | case 'r': // general register. | ||||||
4867 | case 'g': // general register, memory operand or immediate integer. | ||||||
4868 | // note: Clang converts "g" to "imr". | ||||||
4869 | if (CallOperandVal->getType()->isIntegerTy()) | ||||||
4870 | weight = CW_Register; | ||||||
4871 | break; | ||||||
4872 | case 'X': // any operand. | ||||||
4873 | default: | ||||||
4874 | weight = CW_Default; | ||||||
4875 | break; | ||||||
4876 | } | ||||||
4877 | return weight; | ||||||
4878 | } | ||||||
4879 | |||||||
4880 | /// If there are multiple different constraints that we could pick for this | ||||||
4881 | /// operand (e.g. "imr") try to pick the 'best' one. | ||||||
4882 | /// This is somewhat tricky: constraints fall into four classes: | ||||||
4883 | /// Other -> immediates and magic values | ||||||
4884 | /// Register -> one specific register | ||||||
4885 | /// RegisterClass -> a group of regs | ||||||
4886 | /// Memory -> memory | ||||||
4887 | /// Ideally, we would pick the most specific constraint possible: if we have | ||||||
4888 | /// something that fits into a register, we would pick it. The problem here | ||||||
4889 | /// is that if we have something that could either be in a register or in | ||||||
4890 | /// memory that use of the register could cause selection of *other* | ||||||
4891 | /// operands to fail: they might only succeed if we pick memory. Because of | ||||||
4892 | /// this the heuristic we use is: | ||||||
4893 | /// | ||||||
4894 | /// 1) If there is an 'other' constraint, and if the operand is valid for | ||||||
4895 | /// that constraint, use it. This makes us take advantage of 'i' | ||||||
4896 | /// constraints when available. | ||||||
4897 | /// 2) Otherwise, pick the most general constraint present. This prefers | ||||||
4898 | /// 'm' over 'r', for example. | ||||||
4899 | /// | ||||||
4900 | static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo, | ||||||
4901 | const TargetLowering &TLI, | ||||||
4902 | SDValue Op, SelectionDAG *DAG) { | ||||||
4903 | assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options")((OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options" ) ? static_cast<void> (0) : __assert_fail ("OpInfo.Codes.size() > 1 && \"Doesn't have multiple constraint options\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 4903, __PRETTY_FUNCTION__)); | ||||||
4904 | unsigned BestIdx = 0; | ||||||
4905 | TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown; | ||||||
4906 | int BestGenerality = -1; | ||||||
4907 | |||||||
4908 | // Loop over the options, keeping track of the most general one. | ||||||
4909 | for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) { | ||||||
4910 | TargetLowering::ConstraintType CType = | ||||||
4911 | TLI.getConstraintType(OpInfo.Codes[i]); | ||||||
4912 | |||||||
4913 | // Indirect 'other' or 'immediate' constraints are not allowed. | ||||||
4914 | if (OpInfo.isIndirect && !(CType == TargetLowering::C_Memory || | ||||||
4915 | CType == TargetLowering::C_Register || | ||||||
4916 | CType == TargetLowering::C_RegisterClass)) | ||||||
4917 | continue; | ||||||
4918 | |||||||
4919 | // If this is an 'other' or 'immediate' constraint, see if the operand is | ||||||
4920 | // valid for it. For example, on X86 we might have an 'rI' constraint. If | ||||||
4921 | // the operand is an integer in the range [0..31] we want to use I (saving a | ||||||
4922 | // load of a register), otherwise we must use 'r'. | ||||||
4923 | if ((CType == TargetLowering::C_Other || | ||||||
4924 | CType == TargetLowering::C_Immediate) && Op.getNode()) { | ||||||
4925 | assert(OpInfo.Codes[i].size() == 1 &&((OpInfo.Codes[i].size() == 1 && "Unhandled multi-letter 'other' constraint" ) ? static_cast<void> (0) : __assert_fail ("OpInfo.Codes[i].size() == 1 && \"Unhandled multi-letter 'other' constraint\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 4926, __PRETTY_FUNCTION__)) | ||||||
4926 | "Unhandled multi-letter 'other' constraint")((OpInfo.Codes[i].size() == 1 && "Unhandled multi-letter 'other' constraint" ) ? static_cast<void> (0) : __assert_fail ("OpInfo.Codes[i].size() == 1 && \"Unhandled multi-letter 'other' constraint\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 4926, __PRETTY_FUNCTION__)); | ||||||
4927 | std::vector<SDValue> ResultOps; | ||||||
4928 | TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i], | ||||||
4929 | ResultOps, *DAG); | ||||||
4930 | if (!ResultOps.empty()) { | ||||||
4931 | BestType = CType; | ||||||
4932 | BestIdx = i; | ||||||
4933 | break; | ||||||
4934 | } | ||||||
4935 | } | ||||||
4936 | |||||||
4937 | // Things with matching constraints can only be registers, per gcc | ||||||
4938 | // documentation. This mainly affects "g" constraints. | ||||||
4939 | if (CType == TargetLowering::C_Memory && OpInfo.hasMatchingInput()) | ||||||
4940 | continue; | ||||||
4941 | |||||||
4942 | // This constraint letter is more general than the previous one, use it. | ||||||
4943 | int Generality = getConstraintGenerality(CType); | ||||||
4944 | if (Generality > BestGenerality) { | ||||||
4945 | BestType = CType; | ||||||
4946 | BestIdx = i; | ||||||
4947 | BestGenerality = Generality; | ||||||
4948 | } | ||||||
4949 | } | ||||||
4950 | |||||||
4951 | OpInfo.ConstraintCode = OpInfo.Codes[BestIdx]; | ||||||
4952 | OpInfo.ConstraintType = BestType; | ||||||
4953 | } | ||||||
4954 | |||||||
4955 | /// Determines the constraint code and constraint type to use for the specific | ||||||
4956 | /// AsmOperandInfo, setting OpInfo.ConstraintCode and OpInfo.ConstraintType. | ||||||
4957 | void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo, | ||||||
4958 | SDValue Op, | ||||||
4959 | SelectionDAG *DAG) const { | ||||||
4960 | assert(!OpInfo.Codes.empty() && "Must have at least one constraint")((!OpInfo.Codes.empty() && "Must have at least one constraint" ) ? static_cast<void> (0) : __assert_fail ("!OpInfo.Codes.empty() && \"Must have at least one constraint\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 4960, __PRETTY_FUNCTION__)); | ||||||
4961 | |||||||
4962 | // Single-letter constraints ('r') are very common. | ||||||
4963 | if (OpInfo.Codes.size() == 1) { | ||||||
4964 | OpInfo.ConstraintCode = OpInfo.Codes[0]; | ||||||
4965 | OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode); | ||||||
4966 | } else { | ||||||
4967 | ChooseConstraint(OpInfo, *this, Op, DAG); | ||||||
4968 | } | ||||||
4969 | |||||||
4970 | // 'X' matches anything. | ||||||
4971 | if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) { | ||||||
4972 | // Labels and constants are handled elsewhere ('X' is the only thing | ||||||
4973 | // that matches labels). For Functions, the type here is the type of | ||||||
4974 | // the result, which is not what we want to look at; leave them alone. | ||||||
4975 | Value *v = OpInfo.CallOperandVal; | ||||||
4976 | if (isa<BasicBlock>(v) || isa<ConstantInt>(v) || isa<Function>(v)) { | ||||||
4977 | OpInfo.CallOperandVal = v; | ||||||
4978 | return; | ||||||
4979 | } | ||||||
4980 | |||||||
4981 | if (Op.getNode() && Op.getOpcode() == ISD::TargetBlockAddress) | ||||||
4982 | return; | ||||||
4983 | |||||||
4984 | // Otherwise, try to resolve it to something we know about by looking at | ||||||
4985 | // the actual operand type. | ||||||
4986 | if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) { | ||||||
4987 | OpInfo.ConstraintCode = Repl; | ||||||
4988 | OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode); | ||||||
4989 | } | ||||||
4990 | } | ||||||
4991 | } | ||||||
4992 | |||||||
4993 | /// Given an exact SDIV by a constant, create a multiplication | ||||||
4994 | /// with the multiplicative inverse of the constant. | ||||||
4995 | static SDValue BuildExactSDIV(const TargetLowering &TLI, SDNode *N, | ||||||
4996 | const SDLoc &dl, SelectionDAG &DAG, | ||||||
4997 | SmallVectorImpl<SDNode *> &Created) { | ||||||
4998 | SDValue Op0 = N->getOperand(0); | ||||||
4999 | SDValue Op1 = N->getOperand(1); | ||||||
5000 | EVT VT = N->getValueType(0); | ||||||
5001 | EVT SVT = VT.getScalarType(); | ||||||
5002 | EVT ShVT = TLI.getShiftAmountTy(VT, DAG.getDataLayout()); | ||||||
5003 | EVT ShSVT = ShVT.getScalarType(); | ||||||
5004 | |||||||
5005 | bool UseSRA = false; | ||||||
5006 | SmallVector<SDValue, 16> Shifts, Factors; | ||||||
5007 | |||||||
5008 | auto BuildSDIVPattern = [&](ConstantSDNode *C) { | ||||||
5009 | if (C->isNullValue()) | ||||||
5010 | return false; | ||||||
5011 | APInt Divisor = C->getAPIntValue(); | ||||||
5012 | unsigned Shift = Divisor.countTrailingZeros(); | ||||||
5013 | if (Shift) { | ||||||
5014 | Divisor.ashrInPlace(Shift); | ||||||
5015 | UseSRA = true; | ||||||
5016 | } | ||||||
5017 | // Calculate the multiplicative inverse, using Newton's method. | ||||||
5018 | APInt t; | ||||||
5019 | APInt Factor = Divisor; | ||||||
5020 | while ((t = Divisor * Factor) != 1) | ||||||
5021 | Factor *= APInt(Divisor.getBitWidth(), 2) - t; | ||||||
5022 | Shifts.push_back(DAG.getConstant(Shift, dl, ShSVT)); | ||||||
5023 | Factors.push_back(DAG.getConstant(Factor, dl, SVT)); | ||||||
5024 | return true; | ||||||
5025 | }; | ||||||
5026 | |||||||
5027 | // Collect all magic values from the build vector. | ||||||
5028 | if (!ISD::matchUnaryPredicate(Op1, BuildSDIVPattern)) | ||||||
5029 | return SDValue(); | ||||||
5030 | |||||||
5031 | SDValue Shift, Factor; | ||||||
5032 | if (Op1.getOpcode() == ISD::BUILD_VECTOR) { | ||||||
5033 | Shift = DAG.getBuildVector(ShVT, dl, Shifts); | ||||||
5034 | Factor = DAG.getBuildVector(VT, dl, Factors); | ||||||
5035 | } else if (Op1.getOpcode() == ISD::SPLAT_VECTOR) { | ||||||
5036 | assert(Shifts.size() == 1 && Factors.size() == 1 &&((Shifts.size() == 1 && Factors.size() == 1 && "Expected matchUnaryPredicate to return one element for scalable " "vectors") ? static_cast<void> (0) : __assert_fail ("Shifts.size() == 1 && Factors.size() == 1 && \"Expected matchUnaryPredicate to return one element for scalable \" \"vectors\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5038, __PRETTY_FUNCTION__)) | ||||||
5037 | "Expected matchUnaryPredicate to return one element for scalable "((Shifts.size() == 1 && Factors.size() == 1 && "Expected matchUnaryPredicate to return one element for scalable " "vectors") ? static_cast<void> (0) : __assert_fail ("Shifts.size() == 1 && Factors.size() == 1 && \"Expected matchUnaryPredicate to return one element for scalable \" \"vectors\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5038, __PRETTY_FUNCTION__)) | ||||||
5038 | "vectors")((Shifts.size() == 1 && Factors.size() == 1 && "Expected matchUnaryPredicate to return one element for scalable " "vectors") ? static_cast<void> (0) : __assert_fail ("Shifts.size() == 1 && Factors.size() == 1 && \"Expected matchUnaryPredicate to return one element for scalable \" \"vectors\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5038, __PRETTY_FUNCTION__)); | ||||||
5039 | Shift = DAG.getSplatVector(ShVT, dl, Shifts[0]); | ||||||
5040 | Factor = DAG.getSplatVector(VT, dl, Factors[0]); | ||||||
5041 | } else { | ||||||
5042 | assert(isa<ConstantSDNode>(Op1) && "Expected a constant")((isa<ConstantSDNode>(Op1) && "Expected a constant" ) ? static_cast<void> (0) : __assert_fail ("isa<ConstantSDNode>(Op1) && \"Expected a constant\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5042, __PRETTY_FUNCTION__)); | ||||||
5043 | Shift = Shifts[0]; | ||||||
5044 | Factor = Factors[0]; | ||||||
5045 | } | ||||||
5046 | |||||||
5047 | SDValue Res = Op0; | ||||||
5048 | |||||||
5049 | // Shift the value upfront if it is even, so the LSB is one. | ||||||
5050 | if (UseSRA) { | ||||||
5051 | // TODO: For UDIV use SRL instead of SRA. | ||||||
5052 | SDNodeFlags Flags; | ||||||
5053 | Flags.setExact(true); | ||||||
5054 | Res = DAG.getNode(ISD::SRA, dl, VT, Res, Shift, Flags); | ||||||
5055 | Created.push_back(Res.getNode()); | ||||||
5056 | } | ||||||
5057 | |||||||
5058 | return DAG.getNode(ISD::MUL, dl, VT, Res, Factor); | ||||||
5059 | } | ||||||
5060 | |||||||
5061 | SDValue TargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor, | ||||||
5062 | SelectionDAG &DAG, | ||||||
5063 | SmallVectorImpl<SDNode *> &Created) const { | ||||||
5064 | AttributeList Attr = DAG.getMachineFunction().getFunction().getAttributes(); | ||||||
5065 | const TargetLowering &TLI = DAG.getTargetLoweringInfo(); | ||||||
5066 | if (TLI.isIntDivCheap(N->getValueType(0), Attr)) | ||||||
5067 | return SDValue(N, 0); // Lower SDIV as SDIV | ||||||
5068 | return SDValue(); | ||||||
5069 | } | ||||||
5070 | |||||||
5071 | /// Given an ISD::SDIV node expressing a divide by constant, | ||||||
5072 | /// return a DAG expression to select that will generate the same value by | ||||||
5073 | /// multiplying by a magic number. | ||||||
5074 | /// Ref: "Hacker's Delight" or "The PowerPC Compiler Writer's Guide". | ||||||
5075 | SDValue TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG, | ||||||
5076 | bool IsAfterLegalization, | ||||||
5077 | SmallVectorImpl<SDNode *> &Created) const { | ||||||
5078 | SDLoc dl(N); | ||||||
5079 | EVT VT = N->getValueType(0); | ||||||
5080 | EVT SVT = VT.getScalarType(); | ||||||
5081 | EVT ShVT = getShiftAmountTy(VT, DAG.getDataLayout()); | ||||||
5082 | EVT ShSVT = ShVT.getScalarType(); | ||||||
5083 | unsigned EltBits = VT.getScalarSizeInBits(); | ||||||
5084 | EVT MulVT; | ||||||
5085 | |||||||
5086 | // Check to see if we can do this. | ||||||
5087 | // FIXME: We should be more aggressive here. | ||||||
5088 | if (!isTypeLegal(VT)) { | ||||||
5089 | // Limit this to simple scalars for now. | ||||||
5090 | if (VT.isVector() || !VT.isSimple()) | ||||||
5091 | return SDValue(); | ||||||
5092 | |||||||
5093 | // If this type will be promoted to a large enough type with a legal | ||||||
5094 | // multiply operation, we can go ahead and do this transform. | ||||||
5095 | if (getTypeAction(VT.getSimpleVT()) != TypePromoteInteger) | ||||||
5096 | return SDValue(); | ||||||
5097 | |||||||
5098 | MulVT = getTypeToTransformTo(*DAG.getContext(), VT); | ||||||
5099 | if (MulVT.getSizeInBits() < (2 * EltBits) || | ||||||
5100 | !isOperationLegal(ISD::MUL, MulVT)) | ||||||
5101 | return SDValue(); | ||||||
5102 | } | ||||||
5103 | |||||||
5104 | // If the sdiv has an 'exact' bit we can use a simpler lowering. | ||||||
5105 | if (N->getFlags().hasExact()) | ||||||
5106 | return BuildExactSDIV(*this, N, dl, DAG, Created); | ||||||
5107 | |||||||
5108 | SmallVector<SDValue, 16> MagicFactors, Factors, Shifts, ShiftMasks; | ||||||
5109 | |||||||
5110 | auto BuildSDIVPattern = [&](ConstantSDNode *C) { | ||||||
5111 | if (C->isNullValue()) | ||||||
5112 | return false; | ||||||
5113 | |||||||
5114 | const APInt &Divisor = C->getAPIntValue(); | ||||||
5115 | APInt::ms magics = Divisor.magic(); | ||||||
5116 | int NumeratorFactor = 0; | ||||||
5117 | int ShiftMask = -1; | ||||||
5118 | |||||||
5119 | if (Divisor.isOneValue() || Divisor.isAllOnesValue()) { | ||||||
5120 | // If d is +1/-1, we just multiply the numerator by +1/-1. | ||||||
5121 | NumeratorFactor = Divisor.getSExtValue(); | ||||||
5122 | magics.m = 0; | ||||||
5123 | magics.s = 0; | ||||||
5124 | ShiftMask = 0; | ||||||
5125 | } else if (Divisor.isStrictlyPositive() && magics.m.isNegative()) { | ||||||
5126 | // If d > 0 and m < 0, add the numerator. | ||||||
5127 | NumeratorFactor = 1; | ||||||
5128 | } else if (Divisor.isNegative() && magics.m.isStrictlyPositive()) { | ||||||
5129 | // If d < 0 and m > 0, subtract the numerator. | ||||||
5130 | NumeratorFactor = -1; | ||||||
5131 | } | ||||||
5132 | |||||||
5133 | MagicFactors.push_back(DAG.getConstant(magics.m, dl, SVT)); | ||||||
5134 | Factors.push_back(DAG.getConstant(NumeratorFactor, dl, SVT)); | ||||||
5135 | Shifts.push_back(DAG.getConstant(magics.s, dl, ShSVT)); | ||||||
5136 | ShiftMasks.push_back(DAG.getConstant(ShiftMask, dl, SVT)); | ||||||
5137 | return true; | ||||||
5138 | }; | ||||||
5139 | |||||||
5140 | SDValue N0 = N->getOperand(0); | ||||||
5141 | SDValue N1 = N->getOperand(1); | ||||||
5142 | |||||||
5143 | // Collect the shifts / magic values from each element. | ||||||
5144 | if (!ISD::matchUnaryPredicate(N1, BuildSDIVPattern)) | ||||||
5145 | return SDValue(); | ||||||
5146 | |||||||
5147 | SDValue MagicFactor, Factor, Shift, ShiftMask; | ||||||
5148 | if (N1.getOpcode() == ISD::BUILD_VECTOR) { | ||||||
5149 | MagicFactor = DAG.getBuildVector(VT, dl, MagicFactors); | ||||||
5150 | Factor = DAG.getBuildVector(VT, dl, Factors); | ||||||
5151 | Shift = DAG.getBuildVector(ShVT, dl, Shifts); | ||||||
5152 | ShiftMask = DAG.getBuildVector(VT, dl, ShiftMasks); | ||||||
5153 | } else if (N1.getOpcode() == ISD::SPLAT_VECTOR) { | ||||||
5154 | assert(MagicFactors.size() == 1 && Factors.size() == 1 &&((MagicFactors.size() == 1 && Factors.size() == 1 && Shifts.size() == 1 && ShiftMasks.size() == 1 && "Expected matchUnaryPredicate to return one element for scalable " "vectors") ? static_cast<void> (0) : __assert_fail ("MagicFactors.size() == 1 && Factors.size() == 1 && Shifts.size() == 1 && ShiftMasks.size() == 1 && \"Expected matchUnaryPredicate to return one element for scalable \" \"vectors\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5157, __PRETTY_FUNCTION__)) | ||||||
5155 | Shifts.size() == 1 && ShiftMasks.size() == 1 &&((MagicFactors.size() == 1 && Factors.size() == 1 && Shifts.size() == 1 && ShiftMasks.size() == 1 && "Expected matchUnaryPredicate to return one element for scalable " "vectors") ? static_cast<void> (0) : __assert_fail ("MagicFactors.size() == 1 && Factors.size() == 1 && Shifts.size() == 1 && ShiftMasks.size() == 1 && \"Expected matchUnaryPredicate to return one element for scalable \" \"vectors\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5157, __PRETTY_FUNCTION__)) | ||||||
5156 | "Expected matchUnaryPredicate to return one element for scalable "((MagicFactors.size() == 1 && Factors.size() == 1 && Shifts.size() == 1 && ShiftMasks.size() == 1 && "Expected matchUnaryPredicate to return one element for scalable " "vectors") ? static_cast<void> (0) : __assert_fail ("MagicFactors.size() == 1 && Factors.size() == 1 && Shifts.size() == 1 && ShiftMasks.size() == 1 && \"Expected matchUnaryPredicate to return one element for scalable \" \"vectors\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5157, __PRETTY_FUNCTION__)) | ||||||
5157 | "vectors")((MagicFactors.size() == 1 && Factors.size() == 1 && Shifts.size() == 1 && ShiftMasks.size() == 1 && "Expected matchUnaryPredicate to return one element for scalable " "vectors") ? static_cast<void> (0) : __assert_fail ("MagicFactors.size() == 1 && Factors.size() == 1 && Shifts.size() == 1 && ShiftMasks.size() == 1 && \"Expected matchUnaryPredicate to return one element for scalable \" \"vectors\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5157, __PRETTY_FUNCTION__)); | ||||||
5158 | MagicFactor = DAG.getSplatVector(VT, dl, MagicFactors[0]); | ||||||
5159 | Factor = DAG.getSplatVector(VT, dl, Factors[0]); | ||||||
5160 | Shift = DAG.getSplatVector(ShVT, dl, Shifts[0]); | ||||||
5161 | ShiftMask = DAG.getSplatVector(VT, dl, ShiftMasks[0]); | ||||||
5162 | } else { | ||||||
5163 | assert(isa<ConstantSDNode>(N1) && "Expected a constant")((isa<ConstantSDNode>(N1) && "Expected a constant" ) ? static_cast<void> (0) : __assert_fail ("isa<ConstantSDNode>(N1) && \"Expected a constant\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5163, __PRETTY_FUNCTION__)); | ||||||
5164 | MagicFactor = MagicFactors[0]; | ||||||
5165 | Factor = Factors[0]; | ||||||
5166 | Shift = Shifts[0]; | ||||||
5167 | ShiftMask = ShiftMasks[0]; | ||||||
5168 | } | ||||||
5169 | |||||||
5170 | // Multiply the numerator (operand 0) by the magic value. | ||||||
5171 | // FIXME: We should support doing a MUL in a wider type. | ||||||
5172 | auto GetMULHS = [&](SDValue X, SDValue Y) { | ||||||
5173 | // If the type isn't legal, use a wider mul of the the type calculated | ||||||
5174 | // earlier. | ||||||
5175 | if (!isTypeLegal(VT)) { | ||||||
5176 | X = DAG.getNode(ISD::SIGN_EXTEND, dl, MulVT, X); | ||||||
5177 | Y = DAG.getNode(ISD::SIGN_EXTEND, dl, MulVT, Y); | ||||||
5178 | Y = DAG.getNode(ISD::MUL, dl, MulVT, X, Y); | ||||||
5179 | Y = DAG.getNode(ISD::SRL, dl, MulVT, Y, | ||||||
5180 | DAG.getShiftAmountConstant(EltBits, MulVT, dl)); | ||||||
5181 | return DAG.getNode(ISD::TRUNCATE, dl, VT, Y); | ||||||
5182 | } | ||||||
5183 | |||||||
5184 | if (isOperationLegalOrCustom(ISD::MULHS, VT, IsAfterLegalization)) | ||||||
5185 | return DAG.getNode(ISD::MULHS, dl, VT, X, Y); | ||||||
5186 | if (isOperationLegalOrCustom(ISD::SMUL_LOHI, VT, IsAfterLegalization)) { | ||||||
5187 | SDValue LoHi = | ||||||
5188 | DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT), X, Y); | ||||||
5189 | return SDValue(LoHi.getNode(), 1); | ||||||
5190 | } | ||||||
5191 | return SDValue(); | ||||||
5192 | }; | ||||||
5193 | |||||||
5194 | SDValue Q = GetMULHS(N0, MagicFactor); | ||||||
5195 | if (!Q) | ||||||
5196 | return SDValue(); | ||||||
5197 | |||||||
5198 | Created.push_back(Q.getNode()); | ||||||
5199 | |||||||
5200 | // (Optionally) Add/subtract the numerator using Factor. | ||||||
5201 | Factor = DAG.getNode(ISD::MUL, dl, VT, N0, Factor); | ||||||
5202 | Created.push_back(Factor.getNode()); | ||||||
5203 | Q = DAG.getNode(ISD::ADD, dl, VT, Q, Factor); | ||||||
5204 | Created.push_back(Q.getNode()); | ||||||
5205 | |||||||
5206 | // Shift right algebraic by shift value. | ||||||
5207 | Q = DAG.getNode(ISD::SRA, dl, VT, Q, Shift); | ||||||
5208 | Created.push_back(Q.getNode()); | ||||||
5209 | |||||||
5210 | // Extract the sign bit, mask it and add it to the quotient. | ||||||
5211 | SDValue SignShift = DAG.getConstant(EltBits - 1, dl, ShVT); | ||||||
5212 | SDValue T = DAG.getNode(ISD::SRL, dl, VT, Q, SignShift); | ||||||
5213 | Created.push_back(T.getNode()); | ||||||
5214 | T = DAG.getNode(ISD::AND, dl, VT, T, ShiftMask); | ||||||
5215 | Created.push_back(T.getNode()); | ||||||
5216 | return DAG.getNode(ISD::ADD, dl, VT, Q, T); | ||||||
5217 | } | ||||||
5218 | |||||||
5219 | /// Given an ISD::UDIV node expressing a divide by constant, | ||||||
5220 | /// return a DAG expression to select that will generate the same value by | ||||||
5221 | /// multiplying by a magic number. | ||||||
5222 | /// Ref: "Hacker's Delight" or "The PowerPC Compiler Writer's Guide". | ||||||
5223 | SDValue TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG, | ||||||
5224 | bool IsAfterLegalization, | ||||||
5225 | SmallVectorImpl<SDNode *> &Created) const { | ||||||
5226 | SDLoc dl(N); | ||||||
5227 | EVT VT = N->getValueType(0); | ||||||
5228 | EVT SVT = VT.getScalarType(); | ||||||
5229 | EVT ShVT = getShiftAmountTy(VT, DAG.getDataLayout()); | ||||||
5230 | EVT ShSVT = ShVT.getScalarType(); | ||||||
5231 | unsigned EltBits = VT.getScalarSizeInBits(); | ||||||
5232 | EVT MulVT; | ||||||
5233 | |||||||
5234 | // Check to see if we can do this. | ||||||
5235 | // FIXME: We should be more aggressive here. | ||||||
5236 | if (!isTypeLegal(VT)) { | ||||||
5237 | // Limit this to simple scalars for now. | ||||||
5238 | if (VT.isVector() || !VT.isSimple()) | ||||||
5239 | return SDValue(); | ||||||
5240 | |||||||
5241 | // If this type will be promoted to a large enough type with a legal | ||||||
5242 | // multiply operation, we can go ahead and do this transform. | ||||||
5243 | if (getTypeAction(VT.getSimpleVT()) != TypePromoteInteger) | ||||||
5244 | return SDValue(); | ||||||
5245 | |||||||
5246 | MulVT = getTypeToTransformTo(*DAG.getContext(), VT); | ||||||
5247 | if (MulVT.getSizeInBits() < (2 * EltBits) || | ||||||
5248 | !isOperationLegal(ISD::MUL, MulVT)) | ||||||
5249 | return SDValue(); | ||||||
5250 | } | ||||||
5251 | |||||||
5252 | bool UseNPQ = false; | ||||||
5253 | SmallVector<SDValue, 16> PreShifts, PostShifts, MagicFactors, NPQFactors; | ||||||
5254 | |||||||
5255 | auto BuildUDIVPattern = [&](ConstantSDNode *C) { | ||||||
5256 | if (C->isNullValue()) | ||||||
5257 | return false; | ||||||
5258 | // FIXME: We should use a narrower constant when the upper | ||||||
5259 | // bits are known to be zero. | ||||||
5260 | const APInt& Divisor = C->getAPIntValue(); | ||||||
5261 | APInt::mu magics = Divisor.magicu(); | ||||||
5262 | unsigned PreShift = 0, PostShift = 0; | ||||||
5263 | |||||||
5264 | // If the divisor is even, we can avoid using the expensive fixup by | ||||||
5265 | // shifting the divided value upfront. | ||||||
5266 | if (magics.a != 0 && !Divisor[0]) { | ||||||
5267 | PreShift = Divisor.countTrailingZeros(); | ||||||
5268 | // Get magic number for the shifted divisor. | ||||||
5269 | magics = Divisor.lshr(PreShift).magicu(PreShift); | ||||||
5270 | assert(magics.a == 0 && "Should use cheap fixup now")((magics.a == 0 && "Should use cheap fixup now") ? static_cast <void> (0) : __assert_fail ("magics.a == 0 && \"Should use cheap fixup now\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5270, __PRETTY_FUNCTION__)); | ||||||
5271 | } | ||||||
5272 | |||||||
5273 | APInt Magic = magics.m; | ||||||
5274 | |||||||
5275 | unsigned SelNPQ; | ||||||
5276 | if (magics.a == 0 || Divisor.isOneValue()) { | ||||||
5277 | assert(magics.s < Divisor.getBitWidth() &&((magics.s < Divisor.getBitWidth() && "We shouldn't generate an undefined shift!" ) ? static_cast<void> (0) : __assert_fail ("magics.s < Divisor.getBitWidth() && \"We shouldn't generate an undefined shift!\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5278, __PRETTY_FUNCTION__)) | ||||||
5278 | "We shouldn't generate an undefined shift!")((magics.s < Divisor.getBitWidth() && "We shouldn't generate an undefined shift!" ) ? static_cast<void> (0) : __assert_fail ("magics.s < Divisor.getBitWidth() && \"We shouldn't generate an undefined shift!\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5278, __PRETTY_FUNCTION__)); | ||||||
5279 | PostShift = magics.s; | ||||||
5280 | SelNPQ = false; | ||||||
5281 | } else { | ||||||
5282 | PostShift = magics.s - 1; | ||||||
5283 | SelNPQ = true; | ||||||
5284 | } | ||||||
5285 | |||||||
5286 | PreShifts.push_back(DAG.getConstant(PreShift, dl, ShSVT)); | ||||||
5287 | MagicFactors.push_back(DAG.getConstant(Magic, dl, SVT)); | ||||||
5288 | NPQFactors.push_back( | ||||||
5289 | DAG.getConstant(SelNPQ ? APInt::getOneBitSet(EltBits, EltBits - 1) | ||||||
5290 | : APInt::getNullValue(EltBits), | ||||||
5291 | dl, SVT)); | ||||||
5292 | PostShifts.push_back(DAG.getConstant(PostShift, dl, ShSVT)); | ||||||
5293 | UseNPQ |= SelNPQ; | ||||||
5294 | return true; | ||||||
5295 | }; | ||||||
5296 | |||||||
5297 | SDValue N0 = N->getOperand(0); | ||||||
5298 | SDValue N1 = N->getOperand(1); | ||||||
5299 | |||||||
5300 | // Collect the shifts/magic values from each element. | ||||||
5301 | if (!ISD::matchUnaryPredicate(N1, BuildUDIVPattern)) | ||||||
5302 | return SDValue(); | ||||||
5303 | |||||||
5304 | SDValue PreShift, PostShift, MagicFactor, NPQFactor; | ||||||
5305 | if (N1.getOpcode() == ISD::BUILD_VECTOR) { | ||||||
5306 | PreShift = DAG.getBuildVector(ShVT, dl, PreShifts); | ||||||
5307 | MagicFactor = DAG.getBuildVector(VT, dl, MagicFactors); | ||||||
5308 | NPQFactor = DAG.getBuildVector(VT, dl, NPQFactors); | ||||||
5309 | PostShift = DAG.getBuildVector(ShVT, dl, PostShifts); | ||||||
5310 | } else if (N1.getOpcode() == ISD::SPLAT_VECTOR) { | ||||||
5311 | assert(PreShifts.size() == 1 && MagicFactors.size() == 1 &&((PreShifts.size() == 1 && MagicFactors.size() == 1 && NPQFactors.size() == 1 && PostShifts.size() == 1 && "Expected matchUnaryPredicate to return one for scalable vectors" ) ? static_cast<void> (0) : __assert_fail ("PreShifts.size() == 1 && MagicFactors.size() == 1 && NPQFactors.size() == 1 && PostShifts.size() == 1 && \"Expected matchUnaryPredicate to return one for scalable vectors\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5313, __PRETTY_FUNCTION__)) | ||||||
5312 | NPQFactors.size() == 1 && PostShifts.size() == 1 &&((PreShifts.size() == 1 && MagicFactors.size() == 1 && NPQFactors.size() == 1 && PostShifts.size() == 1 && "Expected matchUnaryPredicate to return one for scalable vectors" ) ? static_cast<void> (0) : __assert_fail ("PreShifts.size() == 1 && MagicFactors.size() == 1 && NPQFactors.size() == 1 && PostShifts.size() == 1 && \"Expected matchUnaryPredicate to return one for scalable vectors\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5313, __PRETTY_FUNCTION__)) | ||||||
5313 | "Expected matchUnaryPredicate to return one for scalable vectors")((PreShifts.size() == 1 && MagicFactors.size() == 1 && NPQFactors.size() == 1 && PostShifts.size() == 1 && "Expected matchUnaryPredicate to return one for scalable vectors" ) ? static_cast<void> (0) : __assert_fail ("PreShifts.size() == 1 && MagicFactors.size() == 1 && NPQFactors.size() == 1 && PostShifts.size() == 1 && \"Expected matchUnaryPredicate to return one for scalable vectors\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5313, __PRETTY_FUNCTION__)); | ||||||
5314 | PreShift = DAG.getSplatVector(ShVT, dl, PreShifts[0]); | ||||||
5315 | MagicFactor = DAG.getSplatVector(VT, dl, MagicFactors[0]); | ||||||
5316 | NPQFactor = DAG.getSplatVector(VT, dl, NPQFactors[0]); | ||||||
5317 | PostShift = DAG.getSplatVector(ShVT, dl, PostShifts[0]); | ||||||
5318 | } else { | ||||||
5319 | assert(isa<ConstantSDNode>(N1) && "Expected a constant")((isa<ConstantSDNode>(N1) && "Expected a constant" ) ? static_cast<void> (0) : __assert_fail ("isa<ConstantSDNode>(N1) && \"Expected a constant\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5319, __PRETTY_FUNCTION__)); | ||||||
5320 | PreShift = PreShifts[0]; | ||||||
5321 | MagicFactor = MagicFactors[0]; | ||||||
5322 | PostShift = PostShifts[0]; | ||||||
5323 | } | ||||||
5324 | |||||||
5325 | SDValue Q = N0; | ||||||
5326 | Q = DAG.getNode(ISD::SRL, dl, VT, Q, PreShift); | ||||||
5327 | Created.push_back(Q.getNode()); | ||||||
5328 | |||||||
5329 | // FIXME: We should support doing a MUL in a wider type. | ||||||
5330 | auto GetMULHU = [&](SDValue X, SDValue Y) { | ||||||
5331 | // If the type isn't legal, use a wider mul of the the type calculated | ||||||
5332 | // earlier. | ||||||
5333 | if (!isTypeLegal(VT)) { | ||||||
5334 | X = DAG.getNode(ISD::ZERO_EXTEND, dl, MulVT, X); | ||||||
5335 | Y = DAG.getNode(ISD::ZERO_EXTEND, dl, MulVT, Y); | ||||||
5336 | Y = DAG.getNode(ISD::MUL, dl, MulVT, X, Y); | ||||||
5337 | Y = DAG.getNode(ISD::SRL, dl, MulVT, Y, | ||||||
5338 | DAG.getShiftAmountConstant(EltBits, MulVT, dl)); | ||||||
5339 | return DAG.getNode(ISD::TRUNCATE, dl, VT, Y); | ||||||
5340 | } | ||||||
5341 | |||||||
5342 | if (isOperationLegalOrCustom(ISD::MULHU, VT, IsAfterLegalization)) | ||||||
5343 | return DAG.getNode(ISD::MULHU, dl, VT, X, Y); | ||||||
5344 | if (isOperationLegalOrCustom(ISD::UMUL_LOHI, VT, IsAfterLegalization)) { | ||||||
5345 | SDValue LoHi = | ||||||
5346 | DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT), X, Y); | ||||||
5347 | return SDValue(LoHi.getNode(), 1); | ||||||
5348 | } | ||||||
5349 | return SDValue(); // No mulhu or equivalent | ||||||
5350 | }; | ||||||
5351 | |||||||
5352 | // Multiply the numerator (operand 0) by the magic value. | ||||||
5353 | Q = GetMULHU(Q, MagicFactor); | ||||||
5354 | if (!Q) | ||||||
5355 | return SDValue(); | ||||||
5356 | |||||||
5357 | Created.push_back(Q.getNode()); | ||||||
5358 | |||||||
5359 | if (UseNPQ) { | ||||||
5360 | SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N0, Q); | ||||||
5361 | Created.push_back(NPQ.getNode()); | ||||||
5362 | |||||||
5363 | // For vectors we might have a mix of non-NPQ/NPQ paths, so use | ||||||
5364 | // MULHU to act as a SRL-by-1 for NPQ, else multiply by zero. | ||||||
5365 | if (VT.isVector()) | ||||||
5366 | NPQ = GetMULHU(NPQ, NPQFactor); | ||||||
5367 | else | ||||||
5368 | NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ, DAG.getConstant(1, dl, ShVT)); | ||||||
5369 | |||||||
5370 | Created.push_back(NPQ.getNode()); | ||||||
5371 | |||||||
5372 | Q = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q); | ||||||
5373 | Created.push_back(Q.getNode()); | ||||||
5374 | } | ||||||
5375 | |||||||
5376 | Q = DAG.getNode(ISD::SRL, dl, VT, Q, PostShift); | ||||||
5377 | Created.push_back(Q.getNode()); | ||||||
5378 | |||||||
5379 | EVT SetCCVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT); | ||||||
5380 | |||||||
5381 | SDValue One = DAG.getConstant(1, dl, VT); | ||||||
5382 | SDValue IsOne = DAG.getSetCC(dl, SetCCVT, N1, One, ISD::SETEQ); | ||||||
5383 | return DAG.getSelect(dl, VT, IsOne, N0, Q); | ||||||
5384 | } | ||||||
5385 | |||||||
5386 | /// If all values in Values that *don't* match the predicate are same 'splat' | ||||||
5387 | /// value, then replace all values with that splat value. | ||||||
5388 | /// Else, if AlternativeReplacement was provided, then replace all values that | ||||||
5389 | /// do match predicate with AlternativeReplacement value. | ||||||
5390 | static void | ||||||
5391 | turnVectorIntoSplatVector(MutableArrayRef<SDValue> Values, | ||||||
5392 | std::function<bool(SDValue)> Predicate, | ||||||
5393 | SDValue AlternativeReplacement = SDValue()) { | ||||||
5394 | SDValue Replacement; | ||||||
5395 | // Is there a value for which the Predicate does *NOT* match? What is it? | ||||||
5396 | auto SplatValue = llvm::find_if_not(Values, Predicate); | ||||||
5397 | if (SplatValue != Values.end()) { | ||||||
5398 | // Does Values consist only of SplatValue's and values matching Predicate? | ||||||
5399 | if (llvm::all_of(Values, [Predicate, SplatValue](SDValue Value) { | ||||||
5400 | return Value == *SplatValue || Predicate(Value); | ||||||
5401 | })) // Then we shall replace values matching predicate with SplatValue. | ||||||
5402 | Replacement = *SplatValue; | ||||||
5403 | } | ||||||
5404 | if (!Replacement) { | ||||||
5405 | // Oops, we did not find the "baseline" splat value. | ||||||
5406 | if (!AlternativeReplacement) | ||||||
5407 | return; // Nothing to do. | ||||||
5408 | // Let's replace with provided value then. | ||||||
5409 | Replacement = AlternativeReplacement; | ||||||
5410 | } | ||||||
5411 | std::replace_if(Values.begin(), Values.end(), Predicate, Replacement); | ||||||
5412 | } | ||||||
5413 | |||||||
5414 | /// Given an ISD::UREM used only by an ISD::SETEQ or ISD::SETNE | ||||||
5415 | /// where the divisor is constant and the comparison target is zero, | ||||||
5416 | /// return a DAG expression that will generate the same comparison result | ||||||
5417 | /// using only multiplications, additions and shifts/rotations. | ||||||
5418 | /// Ref: "Hacker's Delight" 10-17. | ||||||
5419 | SDValue TargetLowering::buildUREMEqFold(EVT SETCCVT, SDValue REMNode, | ||||||
5420 | SDValue CompTargetNode, | ||||||
5421 | ISD::CondCode Cond, | ||||||
5422 | DAGCombinerInfo &DCI, | ||||||
5423 | const SDLoc &DL) const { | ||||||
5424 | SmallVector<SDNode *, 5> Built; | ||||||
5425 | if (SDValue Folded = prepareUREMEqFold(SETCCVT, REMNode, CompTargetNode, Cond, | ||||||
5426 | DCI, DL, Built)) { | ||||||
5427 | for (SDNode *N : Built) | ||||||
5428 | DCI.AddToWorklist(N); | ||||||
5429 | return Folded; | ||||||
5430 | } | ||||||
5431 | |||||||
5432 | return SDValue(); | ||||||
5433 | } | ||||||
5434 | |||||||
5435 | SDValue | ||||||
5436 | TargetLowering::prepareUREMEqFold(EVT SETCCVT, SDValue REMNode, | ||||||
5437 | SDValue CompTargetNode, ISD::CondCode Cond, | ||||||
5438 | DAGCombinerInfo &DCI, const SDLoc &DL, | ||||||
5439 | SmallVectorImpl<SDNode *> &Created) const { | ||||||
5440 | // fold (seteq/ne (urem N, D), 0) -> (setule/ugt (rotr (mul N, P), K), Q) | ||||||
5441 | // - D must be constant, with D = D0 * 2^K where D0 is odd | ||||||
5442 | // - P is the multiplicative inverse of D0 modulo 2^W | ||||||
5443 | // - Q = floor(((2^W) - 1) / D) | ||||||
5444 | // where W is the width of the common type of N and D. | ||||||
5445 | assert((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&(((Cond == ISD::SETEQ || Cond == ISD::SETNE) && "Only applicable for (in)equality comparisons." ) ? static_cast<void> (0) : __assert_fail ("(Cond == ISD::SETEQ || Cond == ISD::SETNE) && \"Only applicable for (in)equality comparisons.\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5446, __PRETTY_FUNCTION__)) | ||||||
5446 | "Only applicable for (in)equality comparisons.")(((Cond == ISD::SETEQ || Cond == ISD::SETNE) && "Only applicable for (in)equality comparisons." ) ? static_cast<void> (0) : __assert_fail ("(Cond == ISD::SETEQ || Cond == ISD::SETNE) && \"Only applicable for (in)equality comparisons.\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5446, __PRETTY_FUNCTION__)); | ||||||
5447 | |||||||
5448 | SelectionDAG &DAG = DCI.DAG; | ||||||
5449 | |||||||
5450 | EVT VT = REMNode.getValueType(); | ||||||
5451 | EVT SVT = VT.getScalarType(); | ||||||
5452 | EVT ShVT = getShiftAmountTy(VT, DAG.getDataLayout()); | ||||||
5453 | EVT ShSVT = ShVT.getScalarType(); | ||||||
5454 | |||||||
5455 | // If MUL is unavailable, we cannot proceed in any case. | ||||||
5456 | if (!DCI.isBeforeLegalizeOps() && !isOperationLegalOrCustom(ISD::MUL, VT)) | ||||||
5457 | return SDValue(); | ||||||
5458 | |||||||
5459 | bool ComparingWithAllZeros = true; | ||||||
5460 | bool AllComparisonsWithNonZerosAreTautological = true; | ||||||
5461 | bool HadTautologicalLanes = false; | ||||||
5462 | bool AllLanesAreTautological = true; | ||||||
5463 | bool HadEvenDivisor = false; | ||||||
5464 | bool AllDivisorsArePowerOfTwo = true; | ||||||
5465 | bool HadTautologicalInvertedLanes = false; | ||||||
5466 | SmallVector<SDValue, 16> PAmts, KAmts, QAmts, IAmts; | ||||||
5467 | |||||||
5468 | auto BuildUREMPattern = [&](ConstantSDNode *CDiv, ConstantSDNode *CCmp) { | ||||||
5469 | // Division by 0 is UB. Leave it to be constant-folded elsewhere. | ||||||
5470 | if (CDiv->isNullValue()) | ||||||
5471 | return false; | ||||||
5472 | |||||||
5473 | const APInt &D = CDiv->getAPIntValue(); | ||||||
5474 | const APInt &Cmp = CCmp->getAPIntValue(); | ||||||
5475 | |||||||
5476 | ComparingWithAllZeros &= Cmp.isNullValue(); | ||||||
5477 | |||||||
5478 | // x u% C1` is *always* less than C1. So given `x u% C1 == C2`, | ||||||
5479 | // if C2 is not less than C1, the comparison is always false. | ||||||
5480 | // But we will only be able to produce the comparison that will give the | ||||||
5481 | // opposive tautological answer. So this lane would need to be fixed up. | ||||||
5482 | bool TautologicalInvertedLane = D.ule(Cmp); | ||||||
5483 | HadTautologicalInvertedLanes |= TautologicalInvertedLane; | ||||||
5484 | |||||||
5485 | // If all lanes are tautological (either all divisors are ones, or divisor | ||||||
5486 | // is not greater than the constant we are comparing with), | ||||||
5487 | // we will prefer to avoid the fold. | ||||||
5488 | bool TautologicalLane = D.isOneValue() || TautologicalInvertedLane; | ||||||
5489 | HadTautologicalLanes |= TautologicalLane; | ||||||
5490 | AllLanesAreTautological &= TautologicalLane; | ||||||
5491 | |||||||
5492 | // If we are comparing with non-zero, we need'll need to subtract said | ||||||
5493 | // comparison value from the LHS. But there is no point in doing that if | ||||||
5494 | // every lane where we are comparing with non-zero is tautological.. | ||||||
5495 | if (!Cmp.isNullValue()) | ||||||
5496 | AllComparisonsWithNonZerosAreTautological &= TautologicalLane; | ||||||
5497 | |||||||
5498 | // Decompose D into D0 * 2^K | ||||||
5499 | unsigned K = D.countTrailingZeros(); | ||||||
5500 | assert((!D.isOneValue() || (K == 0)) && "For divisor '1' we won't rotate.")(((!D.isOneValue() || (K == 0)) && "For divisor '1' we won't rotate." ) ? static_cast<void> (0) : __assert_fail ("(!D.isOneValue() || (K == 0)) && \"For divisor '1' we won't rotate.\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5500, __PRETTY_FUNCTION__)); | ||||||
5501 | APInt D0 = D.lshr(K); | ||||||
5502 | |||||||
5503 | // D is even if it has trailing zeros. | ||||||
5504 | HadEvenDivisor |= (K != 0); | ||||||
5505 | // D is a power-of-two if D0 is one. | ||||||
5506 | // If all divisors are power-of-two, we will prefer to avoid the fold. | ||||||
5507 | AllDivisorsArePowerOfTwo &= D0.isOneValue(); | ||||||
5508 | |||||||
5509 | // P = inv(D0, 2^W) | ||||||
5510 | // 2^W requires W + 1 bits, so we have to extend and then truncate. | ||||||
5511 | unsigned W = D.getBitWidth(); | ||||||
5512 | APInt P = D0.zext(W + 1) | ||||||
5513 | .multiplicativeInverse(APInt::getSignedMinValue(W + 1)) | ||||||
5514 | .trunc(W); | ||||||
5515 | assert(!P.isNullValue() && "No multiplicative inverse!")((!P.isNullValue() && "No multiplicative inverse!") ? static_cast<void> (0) : __assert_fail ("!P.isNullValue() && \"No multiplicative inverse!\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5515, __PRETTY_FUNCTION__)); // unreachable | ||||||
5516 | assert((D0 * P).isOneValue() && "Multiplicative inverse sanity check.")(((D0 * P).isOneValue() && "Multiplicative inverse sanity check." ) ? static_cast<void> (0) : __assert_fail ("(D0 * P).isOneValue() && \"Multiplicative inverse sanity check.\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5516, __PRETTY_FUNCTION__)); | ||||||
5517 | |||||||
5518 | // Q = floor((2^W - 1) u/ D) | ||||||
5519 | // R = ((2^W - 1) u% D) | ||||||
5520 | APInt Q, R; | ||||||
5521 | APInt::udivrem(APInt::getAllOnesValue(W), D, Q, R); | ||||||
5522 | |||||||
5523 | // If we are comparing with zero, then that comparison constant is okay, | ||||||
5524 | // else it may need to be one less than that. | ||||||
5525 | if (Cmp.ugt(R)) | ||||||
5526 | Q -= 1; | ||||||
5527 | |||||||
5528 | assert(APInt::getAllOnesValue(ShSVT.getSizeInBits()).ugt(K) &&((APInt::getAllOnesValue(ShSVT.getSizeInBits()).ugt(K) && "We are expecting that K is always less than all-ones for ShSVT" ) ? static_cast<void> (0) : __assert_fail ("APInt::getAllOnesValue(ShSVT.getSizeInBits()).ugt(K) && \"We are expecting that K is always less than all-ones for ShSVT\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5529, __PRETTY_FUNCTION__)) | ||||||
5529 | "We are expecting that K is always less than all-ones for ShSVT")((APInt::getAllOnesValue(ShSVT.getSizeInBits()).ugt(K) && "We are expecting that K is always less than all-ones for ShSVT" ) ? static_cast<void> (0) : __assert_fail ("APInt::getAllOnesValue(ShSVT.getSizeInBits()).ugt(K) && \"We are expecting that K is always less than all-ones for ShSVT\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5529, __PRETTY_FUNCTION__)); | ||||||
5530 | |||||||
5531 | // If the lane is tautological the result can be constant-folded. | ||||||
5532 | if (TautologicalLane) { | ||||||
5533 | // Set P and K amount to a bogus values so we can try to splat them. | ||||||
5534 | P = 0; | ||||||
5535 | K = -1; | ||||||
5536 | // And ensure that comparison constant is tautological, | ||||||
5537 | // it will always compare true/false. | ||||||
5538 | Q = -1; | ||||||
5539 | } | ||||||
5540 | |||||||
5541 | PAmts.push_back(DAG.getConstant(P, DL, SVT)); | ||||||
5542 | KAmts.push_back( | ||||||
5543 | DAG.getConstant(APInt(ShSVT.getSizeInBits(), K), DL, ShSVT)); | ||||||
5544 | QAmts.push_back(DAG.getConstant(Q, DL, SVT)); | ||||||
5545 | return true; | ||||||
5546 | }; | ||||||
5547 | |||||||
5548 | SDValue N = REMNode.getOperand(0); | ||||||
5549 | SDValue D = REMNode.getOperand(1); | ||||||
5550 | |||||||
5551 | // Collect the values from each element. | ||||||
5552 | if (!ISD::matchBinaryPredicate(D, CompTargetNode, BuildUREMPattern)) | ||||||
5553 | return SDValue(); | ||||||
5554 | |||||||
5555 | // If all lanes are tautological, the result can be constant-folded. | ||||||
5556 | if (AllLanesAreTautological) | ||||||
5557 | return SDValue(); | ||||||
5558 | |||||||
5559 | // If this is a urem by a powers-of-two, avoid the fold since it can be | ||||||
5560 | // best implemented as a bit test. | ||||||
5561 | if (AllDivisorsArePowerOfTwo) | ||||||
5562 | return SDValue(); | ||||||
5563 | |||||||
5564 | SDValue PVal, KVal, QVal; | ||||||
5565 | if (VT.isVector()) { | ||||||
5566 | if (HadTautologicalLanes) { | ||||||
5567 | // Try to turn PAmts into a splat, since we don't care about the values | ||||||
5568 | // that are currently '0'. If we can't, just keep '0'`s. | ||||||
5569 | turnVectorIntoSplatVector(PAmts, isNullConstant); | ||||||
5570 | // Try to turn KAmts into a splat, since we don't care about the values | ||||||
5571 | // that are currently '-1'. If we can't, change them to '0'`s. | ||||||
5572 | turnVectorIntoSplatVector(KAmts, isAllOnesConstant, | ||||||
5573 | DAG.getConstant(0, DL, ShSVT)); | ||||||
5574 | } | ||||||
5575 | |||||||
5576 | PVal = DAG.getBuildVector(VT, DL, PAmts); | ||||||
5577 | KVal = DAG.getBuildVector(ShVT, DL, KAmts); | ||||||
5578 | QVal = DAG.getBuildVector(VT, DL, QAmts); | ||||||
5579 | } else { | ||||||
5580 | PVal = PAmts[0]; | ||||||
5581 | KVal = KAmts[0]; | ||||||
5582 | QVal = QAmts[0]; | ||||||
5583 | } | ||||||
5584 | |||||||
5585 | if (!ComparingWithAllZeros && !AllComparisonsWithNonZerosAreTautological) { | ||||||
5586 | if (!DCI.isBeforeLegalizeOps() && !isOperationLegalOrCustom(ISD::SUB, VT)) | ||||||
5587 | return SDValue(); // FIXME: Could/should use `ISD::ADD`? | ||||||
5588 | assert(CompTargetNode.getValueType() == N.getValueType() &&((CompTargetNode.getValueType() == N.getValueType() && "Expecting that the types on LHS and RHS of comparisons match." ) ? static_cast<void> (0) : __assert_fail ("CompTargetNode.getValueType() == N.getValueType() && \"Expecting that the types on LHS and RHS of comparisons match.\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5589, __PRETTY_FUNCTION__)) | ||||||
5589 | "Expecting that the types on LHS and RHS of comparisons match.")((CompTargetNode.getValueType() == N.getValueType() && "Expecting that the types on LHS and RHS of comparisons match." ) ? static_cast<void> (0) : __assert_fail ("CompTargetNode.getValueType() == N.getValueType() && \"Expecting that the types on LHS and RHS of comparisons match.\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5589, __PRETTY_FUNCTION__)); | ||||||
5590 | N = DAG.getNode(ISD::SUB, DL, VT, N, CompTargetNode); | ||||||
5591 | } | ||||||
5592 | |||||||
5593 | // (mul N, P) | ||||||
5594 | SDValue Op0 = DAG.getNode(ISD::MUL, DL, VT, N, PVal); | ||||||
5595 | Created.push_back(Op0.getNode()); | ||||||
5596 | |||||||
5597 | // Rotate right only if any divisor was even. We avoid rotates for all-odd | ||||||
5598 | // divisors as a performance improvement, since rotating by 0 is a no-op. | ||||||
5599 | if (HadEvenDivisor) { | ||||||
5600 | // We need ROTR to do this. | ||||||
5601 | if (!DCI.isBeforeLegalizeOps() && !isOperationLegalOrCustom(ISD::ROTR, VT)) | ||||||
5602 | return SDValue(); | ||||||
5603 | SDNodeFlags Flags; | ||||||
5604 | Flags.setExact(true); | ||||||
5605 | // UREM: (rotr (mul N, P), K) | ||||||
5606 | Op0 = DAG.getNode(ISD::ROTR, DL, VT, Op0, KVal, Flags); | ||||||
5607 | Created.push_back(Op0.getNode()); | ||||||
5608 | } | ||||||
5609 | |||||||
5610 | // UREM: (setule/setugt (rotr (mul N, P), K), Q) | ||||||
5611 | SDValue NewCC = | ||||||
5612 | DAG.getSetCC(DL, SETCCVT, Op0, QVal, | ||||||
5613 | ((Cond == ISD::SETEQ) ? ISD::SETULE : ISD::SETUGT)); | ||||||
5614 | if (!HadTautologicalInvertedLanes) | ||||||
5615 | return NewCC; | ||||||
5616 | |||||||
5617 | // If any lanes previously compared always-false, the NewCC will give | ||||||
5618 | // always-true result for them, so we need to fixup those lanes. | ||||||
5619 | // Or the other way around for inequality predicate. | ||||||
5620 | assert(VT.isVector() && "Can/should only get here for vectors.")((VT.isVector() && "Can/should only get here for vectors." ) ? static_cast<void> (0) : __assert_fail ("VT.isVector() && \"Can/should only get here for vectors.\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5620, __PRETTY_FUNCTION__)); | ||||||
5621 | Created.push_back(NewCC.getNode()); | ||||||
5622 | |||||||
5623 | // x u% C1` is *always* less than C1. So given `x u% C1 == C2`, | ||||||
5624 | // if C2 is not less than C1, the comparison is always false. | ||||||
5625 | // But we have produced the comparison that will give the | ||||||
5626 | // opposive tautological answer. So these lanes would need to be fixed up. | ||||||
5627 | SDValue TautologicalInvertedChannels = | ||||||
5628 | DAG.getSetCC(DL, SETCCVT, D, CompTargetNode, ISD::SETULE); | ||||||
5629 | Created.push_back(TautologicalInvertedChannels.getNode()); | ||||||
5630 | |||||||
5631 | // NOTE: we avoid letting illegal types through even if we're before legalize | ||||||
5632 | // ops – legalization has a hard time producing good code for this. | ||||||
5633 | if (isOperationLegalOrCustom(ISD::VSELECT, SETCCVT)) { | ||||||
5634 | // If we have a vector select, let's replace the comparison results in the | ||||||
5635 | // affected lanes with the correct tautological result. | ||||||
5636 | SDValue Replacement = DAG.getBoolConstant(Cond == ISD::SETEQ ? false : true, | ||||||
5637 | DL, SETCCVT, SETCCVT); | ||||||
5638 | return DAG.getNode(ISD::VSELECT, DL, SETCCVT, TautologicalInvertedChannels, | ||||||
5639 | Replacement, NewCC); | ||||||
5640 | } | ||||||
5641 | |||||||
5642 | // Else, we can just invert the comparison result in the appropriate lanes. | ||||||
5643 | // | ||||||
5644 | // NOTE: see the note above VSELECT above. | ||||||
5645 | if (isOperationLegalOrCustom(ISD::XOR, SETCCVT)) | ||||||
5646 | return DAG.getNode(ISD::XOR, DL, SETCCVT, NewCC, | ||||||
5647 | TautologicalInvertedChannels); | ||||||
5648 | |||||||
5649 | return SDValue(); // Don't know how to lower. | ||||||
5650 | } | ||||||
5651 | |||||||
5652 | /// Given an ISD::SREM used only by an ISD::SETEQ or ISD::SETNE | ||||||
5653 | /// where the divisor is constant and the comparison target is zero, | ||||||
5654 | /// return a DAG expression that will generate the same comparison result | ||||||
5655 | /// using only multiplications, additions and shifts/rotations. | ||||||
5656 | /// Ref: "Hacker's Delight" 10-17. | ||||||
5657 | SDValue TargetLowering::buildSREMEqFold(EVT SETCCVT, SDValue REMNode, | ||||||
5658 | SDValue CompTargetNode, | ||||||
5659 | ISD::CondCode Cond, | ||||||
5660 | DAGCombinerInfo &DCI, | ||||||
5661 | const SDLoc &DL) const { | ||||||
5662 | SmallVector<SDNode *, 7> Built; | ||||||
5663 | if (SDValue Folded = prepareSREMEqFold(SETCCVT, REMNode, CompTargetNode, Cond, | ||||||
5664 | DCI, DL, Built)) { | ||||||
5665 | assert(Built.size() <= 7 && "Max size prediction failed.")((Built.size() <= 7 && "Max size prediction failed." ) ? static_cast<void> (0) : __assert_fail ("Built.size() <= 7 && \"Max size prediction failed.\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5665, __PRETTY_FUNCTION__)); | ||||||
5666 | for (SDNode *N : Built) | ||||||
5667 | DCI.AddToWorklist(N); | ||||||
5668 | return Folded; | ||||||
5669 | } | ||||||
5670 | |||||||
5671 | return SDValue(); | ||||||
5672 | } | ||||||
5673 | |||||||
5674 | SDValue | ||||||
5675 | TargetLowering::prepareSREMEqFold(EVT SETCCVT, SDValue REMNode, | ||||||
5676 | SDValue CompTargetNode, ISD::CondCode Cond, | ||||||
5677 | DAGCombinerInfo &DCI, const SDLoc &DL, | ||||||
5678 | SmallVectorImpl<SDNode *> &Created) const { | ||||||
5679 | // Fold: | ||||||
5680 | // (seteq/ne (srem N, D), 0) | ||||||
5681 | // To: | ||||||
5682 | // (setule/ugt (rotr (add (mul N, P), A), K), Q) | ||||||
5683 | // | ||||||
5684 | // - D must be constant, with D = D0 * 2^K where D0 is odd | ||||||
5685 | // - P is the multiplicative inverse of D0 modulo 2^W | ||||||
5686 | // - A = bitwiseand(floor((2^(W - 1) - 1) / D0), (-(2^k))) | ||||||
5687 | // - Q = floor((2 * A) / (2^K)) | ||||||
5688 | // where W is the width of the common type of N and D. | ||||||
5689 | assert((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&(((Cond == ISD::SETEQ || Cond == ISD::SETNE) && "Only applicable for (in)equality comparisons." ) ? static_cast<void> (0) : __assert_fail ("(Cond == ISD::SETEQ || Cond == ISD::SETNE) && \"Only applicable for (in)equality comparisons.\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5690, __PRETTY_FUNCTION__)) | ||||||
5690 | "Only applicable for (in)equality comparisons.")(((Cond == ISD::SETEQ || Cond == ISD::SETNE) && "Only applicable for (in)equality comparisons." ) ? static_cast<void> (0) : __assert_fail ("(Cond == ISD::SETEQ || Cond == ISD::SETNE) && \"Only applicable for (in)equality comparisons.\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5690, __PRETTY_FUNCTION__)); | ||||||
5691 | |||||||
5692 | SelectionDAG &DAG = DCI.DAG; | ||||||
5693 | |||||||
5694 | EVT VT = REMNode.getValueType(); | ||||||
5695 | EVT SVT = VT.getScalarType(); | ||||||
5696 | EVT ShVT = getShiftAmountTy(VT, DAG.getDataLayout()); | ||||||
5697 | EVT ShSVT = ShVT.getScalarType(); | ||||||
5698 | |||||||
5699 | // If we are after ops legalization, and MUL is unavailable, we can not | ||||||
5700 | // proceed. | ||||||
5701 | if (!DCI.isBeforeLegalizeOps() && !isOperationLegalOrCustom(ISD::MUL, VT)) | ||||||
5702 | return SDValue(); | ||||||
5703 | |||||||
5704 | // TODO: Could support comparing with non-zero too. | ||||||
5705 | ConstantSDNode *CompTarget = isConstOrConstSplat(CompTargetNode); | ||||||
5706 | if (!CompTarget || !CompTarget->isNullValue()) | ||||||
5707 | return SDValue(); | ||||||
5708 | |||||||
5709 | bool HadIntMinDivisor = false; | ||||||
5710 | bool HadOneDivisor = false; | ||||||
5711 | bool AllDivisorsAreOnes = true; | ||||||
5712 | bool HadEvenDivisor = false; | ||||||
5713 | bool NeedToApplyOffset = false; | ||||||
5714 | bool AllDivisorsArePowerOfTwo = true; | ||||||
5715 | SmallVector<SDValue, 16> PAmts, AAmts, KAmts, QAmts; | ||||||
5716 | |||||||
5717 | auto BuildSREMPattern = [&](ConstantSDNode *C) { | ||||||
5718 | // Division by 0 is UB. Leave it to be constant-folded elsewhere. | ||||||
5719 | if (C->isNullValue()) | ||||||
5720 | return false; | ||||||
5721 | |||||||
5722 | // FIXME: we don't fold `rem %X, -C` to `rem %X, C` in DAGCombine. | ||||||
5723 | |||||||
5724 | // WARNING: this fold is only valid for positive divisors! | ||||||
5725 | APInt D = C->getAPIntValue(); | ||||||
5726 | if (D.isNegative()) | ||||||
5727 | D.negate(); // `rem %X, -C` is equivalent to `rem %X, C` | ||||||
5728 | |||||||
5729 | HadIntMinDivisor |= D.isMinSignedValue(); | ||||||
5730 | |||||||
5731 | // If all divisors are ones, we will prefer to avoid the fold. | ||||||
5732 | HadOneDivisor |= D.isOneValue(); | ||||||
5733 | AllDivisorsAreOnes &= D.isOneValue(); | ||||||
5734 | |||||||
5735 | // Decompose D into D0 * 2^K | ||||||
5736 | unsigned K = D.countTrailingZeros(); | ||||||
5737 | assert((!D.isOneValue() || (K == 0)) && "For divisor '1' we won't rotate.")(((!D.isOneValue() || (K == 0)) && "For divisor '1' we won't rotate." ) ? static_cast<void> (0) : __assert_fail ("(!D.isOneValue() || (K == 0)) && \"For divisor '1' we won't rotate.\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5737, __PRETTY_FUNCTION__)); | ||||||
5738 | APInt D0 = D.lshr(K); | ||||||
5739 | |||||||
5740 | if (!D.isMinSignedValue()) { | ||||||
5741 | // D is even if it has trailing zeros; unless it's INT_MIN, in which case | ||||||
5742 | // we don't care about this lane in this fold, we'll special-handle it. | ||||||
5743 | HadEvenDivisor |= (K != 0); | ||||||
5744 | } | ||||||
5745 | |||||||
5746 | // D is a power-of-two if D0 is one. This includes INT_MIN. | ||||||
5747 | // If all divisors are power-of-two, we will prefer to avoid the fold. | ||||||
5748 | AllDivisorsArePowerOfTwo &= D0.isOneValue(); | ||||||
5749 | |||||||
5750 | // P = inv(D0, 2^W) | ||||||
5751 | // 2^W requires W + 1 bits, so we have to extend and then truncate. | ||||||
5752 | unsigned W = D.getBitWidth(); | ||||||
5753 | APInt P = D0.zext(W + 1) | ||||||
5754 | .multiplicativeInverse(APInt::getSignedMinValue(W + 1)) | ||||||
5755 | .trunc(W); | ||||||
5756 | assert(!P.isNullValue() && "No multiplicative inverse!")((!P.isNullValue() && "No multiplicative inverse!") ? static_cast<void> (0) : __assert_fail ("!P.isNullValue() && \"No multiplicative inverse!\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5756, __PRETTY_FUNCTION__)); // unreachable | ||||||
5757 | assert((D0 * P).isOneValue() && "Multiplicative inverse sanity check.")(((D0 * P).isOneValue() && "Multiplicative inverse sanity check." ) ? static_cast<void> (0) : __assert_fail ("(D0 * P).isOneValue() && \"Multiplicative inverse sanity check.\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5757, __PRETTY_FUNCTION__)); | ||||||
5758 | |||||||
5759 | // A = floor((2^(W - 1) - 1) / D0) & -2^K | ||||||
5760 | APInt A = APInt::getSignedMaxValue(W).udiv(D0); | ||||||
5761 | A.clearLowBits(K); | ||||||
5762 | |||||||
5763 | if (!D.isMinSignedValue()) { | ||||||
5764 | // If divisor INT_MIN, then we don't care about this lane in this fold, | ||||||
5765 | // we'll special-handle it. | ||||||
5766 | NeedToApplyOffset |= A != 0; | ||||||
5767 | } | ||||||
5768 | |||||||
5769 | // Q = floor((2 * A) / (2^K)) | ||||||
5770 | APInt Q = (2 * A).udiv(APInt::getOneBitSet(W, K)); | ||||||
5771 | |||||||
5772 | assert(APInt::getAllOnesValue(SVT.getSizeInBits()).ugt(A) &&((APInt::getAllOnesValue(SVT.getSizeInBits()).ugt(A) && "We are expecting that A is always less than all-ones for SVT" ) ? static_cast<void> (0) : __assert_fail ("APInt::getAllOnesValue(SVT.getSizeInBits()).ugt(A) && \"We are expecting that A is always less than all-ones for SVT\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5773, __PRETTY_FUNCTION__)) | ||||||
5773 | "We are expecting that A is always less than all-ones for SVT")((APInt::getAllOnesValue(SVT.getSizeInBits()).ugt(A) && "We are expecting that A is always less than all-ones for SVT" ) ? static_cast<void> (0) : __assert_fail ("APInt::getAllOnesValue(SVT.getSizeInBits()).ugt(A) && \"We are expecting that A is always less than all-ones for SVT\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5773, __PRETTY_FUNCTION__)); | ||||||
5774 | assert(APInt::getAllOnesValue(ShSVT.getSizeInBits()).ugt(K) &&((APInt::getAllOnesValue(ShSVT.getSizeInBits()).ugt(K) && "We are expecting that K is always less than all-ones for ShSVT" ) ? static_cast<void> (0) : __assert_fail ("APInt::getAllOnesValue(ShSVT.getSizeInBits()).ugt(K) && \"We are expecting that K is always less than all-ones for ShSVT\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5775, __PRETTY_FUNCTION__)) | ||||||
5775 | "We are expecting that K is always less than all-ones for ShSVT")((APInt::getAllOnesValue(ShSVT.getSizeInBits()).ugt(K) && "We are expecting that K is always less than all-ones for ShSVT" ) ? static_cast<void> (0) : __assert_fail ("APInt::getAllOnesValue(ShSVT.getSizeInBits()).ugt(K) && \"We are expecting that K is always less than all-ones for ShSVT\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5775, __PRETTY_FUNCTION__)); | ||||||
5776 | |||||||
5777 | // If the divisor is 1 the result can be constant-folded. Likewise, we | ||||||
5778 | // don't care about INT_MIN lanes, those can be set to undef if appropriate. | ||||||
5779 | if (D.isOneValue()) { | ||||||
5780 | // Set P, A and K to a bogus values so we can try to splat them. | ||||||
5781 | P = 0; | ||||||
5782 | A = -1; | ||||||
5783 | K = -1; | ||||||
5784 | |||||||
5785 | // x ?% 1 == 0 <--> true <--> x u<= -1 | ||||||
5786 | Q = -1; | ||||||
5787 | } | ||||||
5788 | |||||||
5789 | PAmts.push_back(DAG.getConstant(P, DL, SVT)); | ||||||
5790 | AAmts.push_back(DAG.getConstant(A, DL, SVT)); | ||||||
5791 | KAmts.push_back( | ||||||
5792 | DAG.getConstant(APInt(ShSVT.getSizeInBits(), K), DL, ShSVT)); | ||||||
5793 | QAmts.push_back(DAG.getConstant(Q, DL, SVT)); | ||||||
5794 | return true; | ||||||
5795 | }; | ||||||
5796 | |||||||
5797 | SDValue N = REMNode.getOperand(0); | ||||||
5798 | SDValue D = REMNode.getOperand(1); | ||||||
5799 | |||||||
5800 | // Collect the values from each element. | ||||||
5801 | if (!ISD::matchUnaryPredicate(D, BuildSREMPattern)) | ||||||
5802 | return SDValue(); | ||||||
5803 | |||||||
5804 | // If this is a srem by a one, avoid the fold since it can be constant-folded. | ||||||
5805 | if (AllDivisorsAreOnes) | ||||||
5806 | return SDValue(); | ||||||
5807 | |||||||
5808 | // If this is a srem by a powers-of-two (including INT_MIN), avoid the fold | ||||||
5809 | // since it can be best implemented as a bit test. | ||||||
5810 | if (AllDivisorsArePowerOfTwo) | ||||||
5811 | return SDValue(); | ||||||
5812 | |||||||
5813 | SDValue PVal, AVal, KVal, QVal; | ||||||
5814 | if (D.getOpcode() == ISD::BUILD_VECTOR) { | ||||||
5815 | if (HadOneDivisor) { | ||||||
5816 | // Try to turn PAmts into a splat, since we don't care about the values | ||||||
5817 | // that are currently '0'. If we can't, just keep '0'`s. | ||||||
5818 | turnVectorIntoSplatVector(PAmts, isNullConstant); | ||||||
5819 | // Try to turn AAmts into a splat, since we don't care about the | ||||||
5820 | // values that are currently '-1'. If we can't, change them to '0'`s. | ||||||
5821 | turnVectorIntoSplatVector(AAmts, isAllOnesConstant, | ||||||
5822 | DAG.getConstant(0, DL, SVT)); | ||||||
5823 | // Try to turn KAmts into a splat, since we don't care about the values | ||||||
5824 | // that are currently '-1'. If we can't, change them to '0'`s. | ||||||
5825 | turnVectorIntoSplatVector(KAmts, isAllOnesConstant, | ||||||
5826 | DAG.getConstant(0, DL, ShSVT)); | ||||||
5827 | } | ||||||
5828 | |||||||
5829 | PVal = DAG.getBuildVector(VT, DL, PAmts); | ||||||
5830 | AVal = DAG.getBuildVector(VT, DL, AAmts); | ||||||
5831 | KVal = DAG.getBuildVector(ShVT, DL, KAmts); | ||||||
5832 | QVal = DAG.getBuildVector(VT, DL, QAmts); | ||||||
5833 | } else if (D.getOpcode() == ISD::SPLAT_VECTOR) { | ||||||
5834 | assert(PAmts.size() == 1 && AAmts.size() == 1 && KAmts.size() == 1 &&((PAmts.size() == 1 && AAmts.size() == 1 && KAmts .size() == 1 && QAmts.size() == 1 && "Expected matchUnaryPredicate to return one element for scalable " "vectors") ? static_cast<void> (0) : __assert_fail ("PAmts.size() == 1 && AAmts.size() == 1 && KAmts.size() == 1 && QAmts.size() == 1 && \"Expected matchUnaryPredicate to return one element for scalable \" \"vectors\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5837, __PRETTY_FUNCTION__)) | ||||||
5835 | QAmts.size() == 1 &&((PAmts.size() == 1 && AAmts.size() == 1 && KAmts .size() == 1 && QAmts.size() == 1 && "Expected matchUnaryPredicate to return one element for scalable " "vectors") ? static_cast<void> (0) : __assert_fail ("PAmts.size() == 1 && AAmts.size() == 1 && KAmts.size() == 1 && QAmts.size() == 1 && \"Expected matchUnaryPredicate to return one element for scalable \" \"vectors\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5837, __PRETTY_FUNCTION__)) | ||||||
5836 | "Expected matchUnaryPredicate to return one element for scalable "((PAmts.size() == 1 && AAmts.size() == 1 && KAmts .size() == 1 && QAmts.size() == 1 && "Expected matchUnaryPredicate to return one element for scalable " "vectors") ? static_cast<void> (0) : __assert_fail ("PAmts.size() == 1 && AAmts.size() == 1 && KAmts.size() == 1 && QAmts.size() == 1 && \"Expected matchUnaryPredicate to return one element for scalable \" \"vectors\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5837, __PRETTY_FUNCTION__)) | ||||||
5837 | "vectors")((PAmts.size() == 1 && AAmts.size() == 1 && KAmts .size() == 1 && QAmts.size() == 1 && "Expected matchUnaryPredicate to return one element for scalable " "vectors") ? static_cast<void> (0) : __assert_fail ("PAmts.size() == 1 && AAmts.size() == 1 && KAmts.size() == 1 && QAmts.size() == 1 && \"Expected matchUnaryPredicate to return one element for scalable \" \"vectors\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5837, __PRETTY_FUNCTION__)); | ||||||
5838 | PVal = DAG.getSplatVector(VT, DL, PAmts[0]); | ||||||
5839 | AVal = DAG.getSplatVector(VT, DL, AAmts[0]); | ||||||
5840 | KVal = DAG.getSplatVector(ShVT, DL, KAmts[0]); | ||||||
5841 | QVal = DAG.getSplatVector(VT, DL, QAmts[0]); | ||||||
5842 | } else { | ||||||
5843 | assert(isa<ConstantSDNode>(D) && "Expected a constant")((isa<ConstantSDNode>(D) && "Expected a constant" ) ? static_cast<void> (0) : __assert_fail ("isa<ConstantSDNode>(D) && \"Expected a constant\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5843, __PRETTY_FUNCTION__)); | ||||||
5844 | PVal = PAmts[0]; | ||||||
5845 | AVal = AAmts[0]; | ||||||
5846 | KVal = KAmts[0]; | ||||||
5847 | QVal = QAmts[0]; | ||||||
5848 | } | ||||||
5849 | |||||||
5850 | // (mul N, P) | ||||||
5851 | SDValue Op0 = DAG.getNode(ISD::MUL, DL, VT, N, PVal); | ||||||
5852 | Created.push_back(Op0.getNode()); | ||||||
5853 | |||||||
5854 | if (NeedToApplyOffset) { | ||||||
5855 | // We need ADD to do this. | ||||||
5856 | if (!DCI.isBeforeLegalizeOps() && !isOperationLegalOrCustom(ISD::ADD, VT)) | ||||||
5857 | return SDValue(); | ||||||
5858 | |||||||
5859 | // (add (mul N, P), A) | ||||||
5860 | Op0 = DAG.getNode(ISD::ADD, DL, VT, Op0, AVal); | ||||||
5861 | Created.push_back(Op0.getNode()); | ||||||
5862 | } | ||||||
5863 | |||||||
5864 | // Rotate right only if any divisor was even. We avoid rotates for all-odd | ||||||
5865 | // divisors as a performance improvement, since rotating by 0 is a no-op. | ||||||
5866 | if (HadEvenDivisor) { | ||||||
5867 | // We need ROTR to do this. | ||||||
5868 | if (!DCI.isBeforeLegalizeOps() && !isOperationLegalOrCustom(ISD::ROTR, VT)) | ||||||
5869 | return SDValue(); | ||||||
5870 | SDNodeFlags Flags; | ||||||
5871 | Flags.setExact(true); | ||||||
5872 | // SREM: (rotr (add (mul N, P), A), K) | ||||||
5873 | Op0 = DAG.getNode(ISD::ROTR, DL, VT, Op0, KVal, Flags); | ||||||
5874 | Created.push_back(Op0.getNode()); | ||||||
5875 | } | ||||||
5876 | |||||||
5877 | // SREM: (setule/setugt (rotr (add (mul N, P), A), K), Q) | ||||||
5878 | SDValue Fold = | ||||||
5879 | DAG.getSetCC(DL, SETCCVT, Op0, QVal, | ||||||
5880 | ((Cond == ISD::SETEQ) ? ISD::SETULE : ISD::SETUGT)); | ||||||
5881 | |||||||
5882 | // If we didn't have lanes with INT_MIN divisor, then we're done. | ||||||
5883 | if (!HadIntMinDivisor) | ||||||
5884 | return Fold; | ||||||
5885 | |||||||
5886 | // That fold is only valid for positive divisors. Which effectively means, | ||||||
5887 | // it is invalid for INT_MIN divisors. So if we have such a lane, | ||||||
5888 | // we must fix-up results for said lanes. | ||||||
5889 | assert(VT.isVector() && "Can/should only get here for vectors.")((VT.isVector() && "Can/should only get here for vectors." ) ? static_cast<void> (0) : __assert_fail ("VT.isVector() && \"Can/should only get here for vectors.\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5889, __PRETTY_FUNCTION__)); | ||||||
5890 | |||||||
5891 | // NOTE: we avoid letting illegal types through even if we're before legalize | ||||||
5892 | // ops – legalization has a hard time producing good code for the code that | ||||||
5893 | // follows. | ||||||
5894 | if (!isOperationLegalOrCustom(ISD::SETEQ, VT) || | ||||||
5895 | !isOperationLegalOrCustom(ISD::AND, VT) || | ||||||
5896 | !isOperationLegalOrCustom(Cond, VT) || | ||||||
5897 | !isOperationLegalOrCustom(ISD::VSELECT, VT)) | ||||||
5898 | return SDValue(); | ||||||
5899 | |||||||
5900 | Created.push_back(Fold.getNode()); | ||||||
5901 | |||||||
5902 | SDValue IntMin = DAG.getConstant( | ||||||
5903 | APInt::getSignedMinValue(SVT.getScalarSizeInBits()), DL, VT); | ||||||
5904 | SDValue IntMax = DAG.getConstant( | ||||||
5905 | APInt::getSignedMaxValue(SVT.getScalarSizeInBits()), DL, VT); | ||||||
5906 | SDValue Zero = | ||||||
5907 | DAG.getConstant(APInt::getNullValue(SVT.getScalarSizeInBits()), DL, VT); | ||||||
5908 | |||||||
5909 | // Which lanes had INT_MIN divisors? Divisor is constant, so const-folded. | ||||||
5910 | SDValue DivisorIsIntMin = DAG.getSetCC(DL, SETCCVT, D, IntMin, ISD::SETEQ); | ||||||
5911 | Created.push_back(DivisorIsIntMin.getNode()); | ||||||
5912 | |||||||
5913 | // (N s% INT_MIN) ==/!= 0 <--> (N & INT_MAX) ==/!= 0 | ||||||
5914 | SDValue Masked = DAG.getNode(ISD::AND, DL, VT, N, IntMax); | ||||||
5915 | Created.push_back(Masked.getNode()); | ||||||
5916 | SDValue MaskedIsZero = DAG.getSetCC(DL, SETCCVT, Masked, Zero, Cond); | ||||||
5917 | Created.push_back(MaskedIsZero.getNode()); | ||||||
5918 | |||||||
5919 | // To produce final result we need to blend 2 vectors: 'SetCC' and | ||||||
5920 | // 'MaskedIsZero'. If the divisor for channel was *NOT* INT_MIN, we pick | ||||||
5921 | // from 'Fold', else pick from 'MaskedIsZero'. Since 'DivisorIsIntMin' is | ||||||
5922 | // constant-folded, select can get lowered to a shuffle with constant mask. | ||||||
5923 | SDValue Blended = | ||||||
5924 | DAG.getNode(ISD::VSELECT, DL, VT, DivisorIsIntMin, MaskedIsZero, Fold); | ||||||
5925 | |||||||
5926 | return Blended; | ||||||
5927 | } | ||||||
5928 | |||||||
5929 | bool TargetLowering:: | ||||||
5930 | verifyReturnAddressArgumentIsConstant(SDValue Op, SelectionDAG &DAG) const { | ||||||
5931 | if (!isa<ConstantSDNode>(Op.getOperand(0))) { | ||||||
5932 | DAG.getContext()->emitError("argument to '__builtin_return_address' must " | ||||||
5933 | "be a constant integer"); | ||||||
5934 | return true; | ||||||
5935 | } | ||||||
5936 | |||||||
5937 | return false; | ||||||
5938 | } | ||||||
5939 | |||||||
5940 | SDValue TargetLowering::getSqrtInputTest(SDValue Op, SelectionDAG &DAG, | ||||||
5941 | const DenormalMode &Mode) const { | ||||||
5942 | SDLoc DL(Op); | ||||||
5943 | EVT VT = Op.getValueType(); | ||||||
5944 | EVT CCVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT); | ||||||
5945 | SDValue FPZero = DAG.getConstantFP(0.0, DL, VT); | ||||||
5946 | // Testing it with denormal inputs to avoid wrong estimate. | ||||||
5947 | if (Mode.Input == DenormalMode::IEEE) { | ||||||
5948 | // This is specifically a check for the handling of denormal inputs, | ||||||
5949 | // not the result. | ||||||
5950 | |||||||
5951 | // Test = fabs(X) < SmallestNormal | ||||||
5952 | const fltSemantics &FltSem = DAG.EVTToAPFloatSemantics(VT); | ||||||
5953 | APFloat SmallestNorm = APFloat::getSmallestNormalized(FltSem); | ||||||
5954 | SDValue NormC = DAG.getConstantFP(SmallestNorm, DL, VT); | ||||||
5955 | SDValue Fabs = DAG.getNode(ISD::FABS, DL, VT, Op); | ||||||
5956 | return DAG.getSetCC(DL, CCVT, Fabs, NormC, ISD::SETLT); | ||||||
5957 | } | ||||||
5958 | // Test = X == 0.0 | ||||||
5959 | return DAG.getSetCC(DL, CCVT, Op, FPZero, ISD::SETEQ); | ||||||
5960 | } | ||||||
5961 | |||||||
5962 | SDValue TargetLowering::getNegatedExpression(SDValue Op, SelectionDAG &DAG, | ||||||
5963 | bool LegalOps, bool OptForSize, | ||||||
5964 | NegatibleCost &Cost, | ||||||
5965 | unsigned Depth) const { | ||||||
5966 | // fneg is removable even if it has multiple uses. | ||||||
5967 | if (Op.getOpcode() == ISD::FNEG) { | ||||||
5968 | Cost = NegatibleCost::Cheaper; | ||||||
5969 | return Op.getOperand(0); | ||||||
5970 | } | ||||||
5971 | |||||||
5972 | // Don't recurse exponentially. | ||||||
5973 | if (Depth > SelectionDAG::MaxRecursionDepth) | ||||||
5974 | return SDValue(); | ||||||
5975 | |||||||
5976 | // Pre-increment recursion depth for use in recursive calls. | ||||||
5977 | ++Depth; | ||||||
5978 | const SDNodeFlags Flags = Op->getFlags(); | ||||||
5979 | const TargetOptions &Options = DAG.getTarget().Options; | ||||||
5980 | EVT VT = Op.getValueType(); | ||||||
5981 | unsigned Opcode = Op.getOpcode(); | ||||||
5982 | |||||||
5983 | // Don't allow anything with multiple uses unless we know it is free. | ||||||
5984 | if (!Op.hasOneUse() && Opcode != ISD::ConstantFP) { | ||||||
5985 | bool IsFreeExtend = Opcode == ISD::FP_EXTEND && | ||||||
5986 | isFPExtFree(VT, Op.getOperand(0).getValueType()); | ||||||
5987 | if (!IsFreeExtend) | ||||||
5988 | return SDValue(); | ||||||
5989 | } | ||||||
5990 | |||||||
5991 | auto RemoveDeadNode = [&](SDValue N) { | ||||||
5992 | if (N && N.getNode()->use_empty()) | ||||||
5993 | DAG.RemoveDeadNode(N.getNode()); | ||||||
5994 | }; | ||||||
5995 | |||||||
5996 | SDLoc DL(Op); | ||||||
5997 | |||||||
5998 | // Because getNegatedExpression can delete nodes we need a handle to keep | ||||||
5999 | // temporary nodes alive in case the recursion manages to create an identical | ||||||
6000 | // node. | ||||||
6001 | std::list<HandleSDNode> Handles; | ||||||
6002 | |||||||
6003 | switch (Opcode) { | ||||||
6004 | case ISD::ConstantFP: { | ||||||
6005 | // Don't invert constant FP values after legalization unless the target says | ||||||
6006 | // the negated constant is legal. | ||||||
6007 | bool IsOpLegal = | ||||||
6008 | isOperationLegal(ISD::ConstantFP, VT) || | ||||||
6009 | isFPImmLegal(neg(cast<ConstantFPSDNode>(Op)->getValueAPF()), VT, | ||||||
6010 | OptForSize); | ||||||
6011 | |||||||
6012 | if (LegalOps && !IsOpLegal) | ||||||
6013 | break; | ||||||
6014 | |||||||
6015 | APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF(); | ||||||
6016 | V.changeSign(); | ||||||
6017 | SDValue CFP = DAG.getConstantFP(V, DL, VT); | ||||||
6018 | |||||||
6019 | // If we already have the use of the negated floating constant, it is free | ||||||
6020 | // to negate it even it has multiple uses. | ||||||
6021 | if (!Op.hasOneUse() && CFP.use_empty()) | ||||||
6022 | break; | ||||||
6023 | Cost = NegatibleCost::Neutral; | ||||||
6024 | return CFP; | ||||||
6025 | } | ||||||
6026 | case ISD::BUILD_VECTOR: { | ||||||
6027 | // Only permit BUILD_VECTOR of constants. | ||||||
6028 | if (llvm::any_of(Op->op_values(), [&](SDValue N) { | ||||||
6029 | return !N.isUndef() && !isa<ConstantFPSDNode>(N); | ||||||
6030 | })) | ||||||
6031 | break; | ||||||
6032 | |||||||
6033 | bool IsOpLegal = | ||||||
6034 | (isOperationLegal(ISD::ConstantFP, VT) && | ||||||
6035 | isOperationLegal(ISD::BUILD_VECTOR, VT)) || | ||||||
6036 | llvm::all_of(Op->op_values(), [&](SDValue N) { | ||||||
6037 | return N.isUndef() || | ||||||
6038 | isFPImmLegal(neg(cast<ConstantFPSDNode>(N)->getValueAPF()), VT, | ||||||
6039 | OptForSize); | ||||||
6040 | }); | ||||||
6041 | |||||||
6042 | if (LegalOps && !IsOpLegal) | ||||||
6043 | break; | ||||||
6044 | |||||||
6045 | SmallVector<SDValue, 4> Ops; | ||||||
6046 | for (SDValue C : Op->op_values()) { | ||||||
6047 | if (C.isUndef()) { | ||||||
6048 | Ops.push_back(C); | ||||||
6049 | continue; | ||||||
6050 | } | ||||||
6051 | APFloat V = cast<ConstantFPSDNode>(C)->getValueAPF(); | ||||||
6052 | V.changeSign(); | ||||||
6053 | Ops.push_back(DAG.getConstantFP(V, DL, C.getValueType())); | ||||||
6054 | } | ||||||
6055 | Cost = NegatibleCost::Neutral; | ||||||
6056 | return DAG.getBuildVector(VT, DL, Ops); | ||||||
6057 | } | ||||||
6058 | case ISD::FADD: { | ||||||
6059 | if (!Options.NoSignedZerosFPMath && !Flags.hasNoSignedZeros()) | ||||||
6060 | break; | ||||||
6061 | |||||||
6062 | // After operation legalization, it might not be legal to create new FSUBs. | ||||||
6063 | if (LegalOps && !isOperationLegalOrCustom(ISD::FSUB, VT)) | ||||||
6064 | break; | ||||||
6065 | SDValue X = Op.getOperand(0), Y = Op.getOperand(1); | ||||||
6066 | |||||||
6067 | // fold (fneg (fadd X, Y)) -> (fsub (fneg X), Y) | ||||||
6068 | NegatibleCost CostX = NegatibleCost::Expensive; | ||||||
6069 | SDValue NegX = | ||||||
6070 | getNegatedExpression(X, DAG, LegalOps, OptForSize, CostX, Depth); | ||||||
6071 | // Prevent this node from being deleted by the next call. | ||||||
6072 | if (NegX) | ||||||
6073 | Handles.emplace_back(NegX); | ||||||
6074 | |||||||
6075 | // fold (fneg (fadd X, Y)) -> (fsub (fneg Y), X) | ||||||
6076 | NegatibleCost CostY = NegatibleCost::Expensive; | ||||||
6077 | SDValue NegY = | ||||||
6078 | getNegatedExpression(Y, DAG, LegalOps, OptForSize, CostY, Depth); | ||||||
6079 | |||||||
6080 | // We're done with the handles. | ||||||
6081 | Handles.clear(); | ||||||
6082 | |||||||
6083 | // Negate the X if its cost is less or equal than Y. | ||||||
6084 | if (NegX && (CostX <= CostY)) { | ||||||
6085 | Cost = CostX; | ||||||
6086 | SDValue N = DAG.getNode(ISD::FSUB, DL, VT, NegX, Y, Flags); | ||||||
6087 | if (NegY != N) | ||||||
6088 | RemoveDeadNode(NegY); | ||||||
6089 | return N; | ||||||
6090 | } | ||||||
6091 | |||||||
6092 | // Negate the Y if it is not expensive. | ||||||
6093 | if (NegY) { | ||||||
6094 | Cost = CostY; | ||||||
6095 | SDValue N = DAG.getNode(ISD::FSUB, DL, VT, NegY, X, Flags); | ||||||
6096 | if (NegX != N) | ||||||
6097 | RemoveDeadNode(NegX); | ||||||
6098 | return N; | ||||||
6099 | } | ||||||
6100 | break; | ||||||
6101 | } | ||||||
6102 | case ISD::FSUB: { | ||||||
6103 | // We can't turn -(A-B) into B-A when we honor signed zeros. | ||||||
6104 | if (!Options.NoSignedZerosFPMath && !Flags.hasNoSignedZeros()) | ||||||
6105 | break; | ||||||
6106 | |||||||
6107 | SDValue X = Op.getOperand(0), Y = Op.getOperand(1); | ||||||
6108 | // fold (fneg (fsub 0, Y)) -> Y | ||||||
6109 | if (ConstantFPSDNode *C = isConstOrConstSplatFP(X, /*AllowUndefs*/ true)) | ||||||
6110 | if (C->isZero()) { | ||||||
6111 | Cost = NegatibleCost::Cheaper; | ||||||
6112 | return Y; | ||||||
6113 | } | ||||||
6114 | |||||||
6115 | // fold (fneg (fsub X, Y)) -> (fsub Y, X) | ||||||
6116 | Cost = NegatibleCost::Neutral; | ||||||
6117 | return DAG.getNode(ISD::FSUB, DL, VT, Y, X, Flags); | ||||||
6118 | } | ||||||
6119 | case ISD::FMUL: | ||||||
6120 | case ISD::FDIV: { | ||||||
6121 | SDValue X = Op.getOperand(0), Y = Op.getOperand(1); | ||||||
6122 | |||||||
6123 | // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) | ||||||
6124 | NegatibleCost CostX = NegatibleCost::Expensive; | ||||||
6125 | SDValue NegX = | ||||||
6126 | getNegatedExpression(X, DAG, LegalOps, OptForSize, CostX, Depth); | ||||||
6127 | // Prevent this node from being deleted by the next call. | ||||||
6128 | if (NegX) | ||||||
6129 | Handles.emplace_back(NegX); | ||||||
6130 | |||||||
6131 | // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y)) | ||||||
6132 | NegatibleCost CostY = NegatibleCost::Expensive; | ||||||
6133 | SDValue NegY = | ||||||
6134 | getNegatedExpression(Y, DAG, LegalOps, OptForSize, CostY, Depth); | ||||||
6135 | |||||||
6136 | // We're done with the handles. | ||||||
6137 | Handles.clear(); | ||||||
6138 | |||||||
6139 | // Negate the X if its cost is less or equal than Y. | ||||||
6140 | if (NegX && (CostX <= CostY)) { | ||||||
6141 | Cost = CostX; | ||||||
6142 | SDValue N = DAG.getNode(Opcode, DL, VT, NegX, Y, Flags); | ||||||
6143 | if (NegY != N) | ||||||
6144 | RemoveDeadNode(NegY); | ||||||
6145 | return N; | ||||||
6146 | } | ||||||
6147 | |||||||
6148 | // Ignore X * 2.0 because that is expected to be canonicalized to X + X. | ||||||
6149 | if (auto *C = isConstOrConstSplatFP(Op.getOperand(1))) | ||||||
6150 | if (C->isExactlyValue(2.0) && Op.getOpcode() == ISD::FMUL) | ||||||
6151 | break; | ||||||
6152 | |||||||
6153 | // Negate the Y if it is not expensive. | ||||||
6154 | if (NegY) { | ||||||
6155 | Cost = CostY; | ||||||
6156 | SDValue N = DAG.getNode(Opcode, DL, VT, X, NegY, Flags); | ||||||
6157 | if (NegX != N) | ||||||
6158 | RemoveDeadNode(NegX); | ||||||
6159 | return N; | ||||||
6160 | } | ||||||
6161 | break; | ||||||
6162 | } | ||||||
6163 | case ISD::FMA: | ||||||
6164 | case ISD::FMAD: { | ||||||
6165 | if (!Options.NoSignedZerosFPMath && !Flags.hasNoSignedZeros()) | ||||||
6166 | break; | ||||||
6167 | |||||||
6168 | SDValue X = Op.getOperand(0), Y = Op.getOperand(1), Z = Op.getOperand(2); | ||||||
6169 | NegatibleCost CostZ = NegatibleCost::Expensive; | ||||||
6170 | SDValue NegZ = | ||||||
6171 | getNegatedExpression(Z, DAG, LegalOps, OptForSize, CostZ, Depth); | ||||||
6172 | // Give up if fail to negate the Z. | ||||||
6173 | if (!NegZ) | ||||||
6174 | break; | ||||||
6175 | |||||||
6176 | // Prevent this node from being deleted by the next two calls. | ||||||
6177 | Handles.emplace_back(NegZ); | ||||||
6178 | |||||||
6179 | // fold (fneg (fma X, Y, Z)) -> (fma (fneg X), Y, (fneg Z)) | ||||||
6180 | NegatibleCost CostX = NegatibleCost::Expensive; | ||||||
6181 | SDValue NegX = | ||||||
6182 | getNegatedExpression(X, DAG, LegalOps, OptForSize, CostX, Depth); | ||||||
6183 | // Prevent this node from being deleted by the next call. | ||||||
6184 | if (NegX) | ||||||
6185 | Handles.emplace_back(NegX); | ||||||
6186 | |||||||
6187 | // fold (fneg (fma X, Y, Z)) -> (fma X, (fneg Y), (fneg Z)) | ||||||
6188 | NegatibleCost CostY = NegatibleCost::Expensive; | ||||||
6189 | SDValue NegY = | ||||||
6190 | getNegatedExpression(Y, DAG, LegalOps, OptForSize, CostY, Depth); | ||||||
6191 | |||||||
6192 | // We're done with the handles. | ||||||
6193 | Handles.clear(); | ||||||
6194 | |||||||
6195 | // Negate the X if its cost is less or equal than Y. | ||||||
6196 | if (NegX && (CostX <= CostY)) { | ||||||
6197 | Cost = std::min(CostX, CostZ); | ||||||
6198 | SDValue N = DAG.getNode(Opcode, DL, VT, NegX, Y, NegZ, Flags); | ||||||
6199 | if (NegY != N) | ||||||
6200 | RemoveDeadNode(NegY); | ||||||
6201 | return N; | ||||||
6202 | } | ||||||
6203 | |||||||
6204 | // Negate the Y if it is not expensive. | ||||||
6205 | if (NegY) { | ||||||
6206 | Cost = std::min(CostY, CostZ); | ||||||
6207 | SDValue N = DAG.getNode(Opcode, DL, VT, X, NegY, NegZ, Flags); | ||||||
6208 | if (NegX != N) | ||||||
6209 | RemoveDeadNode(NegX); | ||||||
6210 | return N; | ||||||
6211 | } | ||||||
6212 | break; | ||||||
6213 | } | ||||||
6214 | |||||||
6215 | case ISD::FP_EXTEND: | ||||||
6216 | case ISD::FSIN: | ||||||
6217 | if (SDValue NegV = getNegatedExpression(Op.getOperand(0), DAG, LegalOps, | ||||||
6218 | OptForSize, Cost, Depth)) | ||||||
6219 | return DAG.getNode(Opcode, DL, VT, NegV); | ||||||
6220 | break; | ||||||
6221 | case ISD::FP_ROUND: | ||||||
6222 | if (SDValue NegV = getNegatedExpression(Op.getOperand(0), DAG, LegalOps, | ||||||
6223 | OptForSize, Cost, Depth)) | ||||||
6224 | return DAG.getNode(ISD::FP_ROUND, DL, VT, NegV, Op.getOperand(1)); | ||||||
6225 | break; | ||||||
6226 | } | ||||||
6227 | |||||||
6228 | return SDValue(); | ||||||
6229 | } | ||||||
6230 | |||||||
6231 | //===----------------------------------------------------------------------===// | ||||||
6232 | // Legalization Utilities | ||||||
6233 | //===----------------------------------------------------------------------===// | ||||||
6234 | |||||||
6235 | bool TargetLowering::expandMUL_LOHI(unsigned Opcode, EVT VT, const SDLoc &dl, | ||||||
6236 | SDValue LHS, SDValue RHS, | ||||||
6237 | SmallVectorImpl<SDValue> &Result, | ||||||
6238 | EVT HiLoVT, SelectionDAG &DAG, | ||||||
6239 | MulExpansionKind Kind, SDValue LL, | ||||||
6240 | SDValue LH, SDValue RL, SDValue RH) const { | ||||||
6241 | assert(Opcode == ISD::MUL || Opcode == ISD::UMUL_LOHI ||((Opcode == ISD::MUL || Opcode == ISD::UMUL_LOHI || Opcode == ISD::SMUL_LOHI) ? static_cast<void> (0) : __assert_fail ("Opcode == ISD::MUL || Opcode == ISD::UMUL_LOHI || Opcode == ISD::SMUL_LOHI" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 6242, __PRETTY_FUNCTION__)) | ||||||
6242 | Opcode == ISD::SMUL_LOHI)((Opcode == ISD::MUL || Opcode == ISD::UMUL_LOHI || Opcode == ISD::SMUL_LOHI) ? static_cast<void> (0) : __assert_fail ("Opcode == ISD::MUL || Opcode == ISD::UMUL_LOHI || Opcode == ISD::SMUL_LOHI" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 6242, __PRETTY_FUNCTION__)); | ||||||
6243 | |||||||
6244 | bool HasMULHS = (Kind == MulExpansionKind::Always) || | ||||||
6245 | isOperationLegalOrCustom(ISD::MULHS, HiLoVT); | ||||||
6246 | bool HasMULHU = (Kind == MulExpansionKind::Always) || | ||||||
6247 | isOperationLegalOrCustom(ISD::MULHU, HiLoVT); | ||||||
6248 | bool HasSMUL_LOHI = (Kind == MulExpansionKind::Always) || | ||||||
6249 | isOperationLegalOrCustom(ISD::SMUL_LOHI, HiLoVT); | ||||||
6250 | bool HasUMUL_LOHI = (Kind == MulExpansionKind::Always) || | ||||||
6251 | isOperationLegalOrCustom(ISD::UMUL_LOHI, HiLoVT); | ||||||
6252 | |||||||
6253 | if (!HasMULHU && !HasMULHS && !HasUMUL_LOHI && !HasSMUL_LOHI) | ||||||
6254 | return false; | ||||||
6255 | |||||||
6256 | unsigned OuterBitSize = VT.getScalarSizeInBits(); | ||||||
6257 | unsigned InnerBitSize = HiLoVT.getScalarSizeInBits(); | ||||||
6258 | |||||||
6259 | // LL, LH, RL, and RH must be either all NULL or all set to a value. | ||||||
6260 | assert((LL.getNode() && LH.getNode() && RL.getNode() && RH.getNode()) ||(((LL.getNode() && LH.getNode() && RL.getNode () && RH.getNode()) || (!LL.getNode() && !LH. getNode() && !RL.getNode() && !RH.getNode())) ? static_cast<void> (0) : __assert_fail ("(LL.getNode() && LH.getNode() && RL.getNode() && RH.getNode()) || (!LL.getNode() && !LH.getNode() && !RL.getNode() && !RH.getNode())" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 6261, __PRETTY_FUNCTION__)) | ||||||
6261 | (!LL.getNode() && !LH.getNode() && !RL.getNode() && !RH.getNode()))(((LL.getNode() && LH.getNode() && RL.getNode () && RH.getNode()) || (!LL.getNode() && !LH. getNode() && !RL.getNode() && !RH.getNode())) ? static_cast<void> (0) : __assert_fail ("(LL.getNode() && LH.getNode() && RL.getNode() && RH.getNode()) || (!LL.getNode() && !LH.getNode() && !RL.getNode() && !RH.getNode())" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 6261, __PRETTY_FUNCTION__)); | ||||||
6262 | |||||||
6263 | SDVTList VTs = DAG.getVTList(HiLoVT, HiLoVT); | ||||||
6264 | auto MakeMUL_LOHI = [&](SDValue L, SDValue R, SDValue &Lo, SDValue &Hi, | ||||||
6265 | bool Signed) -> bool { | ||||||
6266 | if ((Signed && HasSMUL_LOHI) || (!Signed && HasUMUL_LOHI)) { | ||||||
6267 | Lo = DAG.getNode(Signed ? ISD::SMUL_LOHI : ISD::UMUL_LOHI, dl, VTs, L, R); | ||||||
6268 | Hi = SDValue(Lo.getNode(), 1); | ||||||
6269 | return true; | ||||||
6270 | } | ||||||
6271 | if ((Signed && HasMULHS) || (!Signed && HasMULHU)) { | ||||||
6272 | Lo = DAG.getNode(ISD::MUL, dl, HiLoVT, L, R); | ||||||
6273 | Hi = DAG.getNode(Signed ? ISD::MULHS : ISD::MULHU, dl, HiLoVT, L, R); | ||||||
6274 | return true; | ||||||
6275 | } | ||||||
6276 | return false; | ||||||
6277 | }; | ||||||
6278 | |||||||
6279 | SDValue Lo, Hi; | ||||||
6280 | |||||||
6281 | if (!LL.getNode() && !RL.getNode() && | ||||||
6282 | isOperationLegalOrCustom(ISD::TRUNCATE, HiLoVT)) { | ||||||
6283 | LL = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, LHS); | ||||||
6284 | RL = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, RHS); | ||||||
6285 | } | ||||||
6286 | |||||||
6287 | if (!LL.getNode()) | ||||||
6288 | return false; | ||||||
6289 | |||||||
6290 | APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize); | ||||||
6291 | if (DAG.MaskedValueIsZero(LHS, HighMask) && | ||||||
6292 | DAG.MaskedValueIsZero(RHS, HighMask)) { | ||||||
6293 | // The inputs are both zero-extended. | ||||||
6294 | if (MakeMUL_LOHI(LL, RL, Lo, Hi, false)) { | ||||||
6295 | Result.push_back(Lo); | ||||||
6296 | Result.push_back(Hi); | ||||||
6297 | if (Opcode != ISD::MUL) { | ||||||
6298 | SDValue Zero = DAG.getConstant(0, dl, HiLoVT); | ||||||
6299 | Result.push_back(Zero); | ||||||
6300 | Result.push_back(Zero); | ||||||
6301 | } | ||||||
6302 | return true; | ||||||
6303 | } | ||||||
6304 | } | ||||||
6305 | |||||||
6306 | if (!VT.isVector() && Opcode == ISD::MUL && | ||||||
6307 | DAG.ComputeNumSignBits(LHS) > InnerBitSize && | ||||||
6308 | DAG.ComputeNumSignBits(RHS) > InnerBitSize) { | ||||||
6309 | // The input values are both sign-extended. | ||||||
6310 | // TODO non-MUL case? | ||||||
6311 | if (MakeMUL_LOHI(LL, RL, Lo, Hi, true)) { | ||||||
6312 | Result.push_back(Lo); | ||||||
6313 | Result.push_back(Hi); | ||||||
6314 | return true; | ||||||
6315 | } | ||||||
6316 | } | ||||||
6317 | |||||||
6318 | unsigned ShiftAmount = OuterBitSize - InnerBitSize; | ||||||
6319 | EVT ShiftAmountTy = getShiftAmountTy(VT, DAG.getDataLayout()); | ||||||
6320 | if (APInt::getMaxValue(ShiftAmountTy.getSizeInBits()).ult(ShiftAmount)) { | ||||||
6321 | // FIXME getShiftAmountTy does not always return a sensible result when VT | ||||||
6322 | // is an illegal type, and so the type may be too small to fit the shift | ||||||
6323 | // amount. Override it with i32. The shift will have to be legalized. | ||||||
6324 | ShiftAmountTy = MVT::i32; | ||||||
6325 | } | ||||||
6326 | SDValue Shift = DAG.getConstant(ShiftAmount, dl, ShiftAmountTy); | ||||||
6327 | |||||||
6328 | if (!LH.getNode() && !RH.getNode() && | ||||||
6329 | isOperationLegalOrCustom(ISD::SRL, VT) && | ||||||
6330 | isOperationLegalOrCustom(ISD::TRUNCATE, HiLoVT)) { | ||||||
6331 | LH = DAG.getNode(ISD::SRL, dl, VT, LHS, Shift); | ||||||
6332 | LH = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, LH); | ||||||
6333 | RH = DAG.getNode(ISD::SRL, dl, VT, RHS, Shift); | ||||||
6334 | RH = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, RH); | ||||||
6335 | } | ||||||
6336 | |||||||
6337 | if (!LH.getNode()) | ||||||
6338 | return false; | ||||||
6339 | |||||||
6340 | if (!MakeMUL_LOHI(LL, RL, Lo, Hi, false)) | ||||||
6341 | return false; | ||||||
6342 | |||||||
6343 | Result.push_back(Lo); | ||||||
6344 | |||||||
6345 | if (Opcode == ISD::MUL) { | ||||||
6346 | RH = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RH); | ||||||
6347 | LH = DAG.getNode(ISD::MUL, dl, HiLoVT, LH, RL); | ||||||
6348 | Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, RH); | ||||||
6349 | Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, LH); | ||||||
6350 | Result.push_back(Hi); | ||||||
6351 | return true; | ||||||
6352 | } | ||||||
6353 | |||||||
6354 | // Compute the full width result. | ||||||
6355 | auto Merge = [&](SDValue Lo, SDValue Hi) -> SDValue { | ||||||
6356 | Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Lo); | ||||||
6357 | Hi = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Hi); | ||||||
6358 | Hi = DAG.getNode(ISD::SHL, dl, VT, Hi, Shift); | ||||||
6359 | return DAG.getNode(ISD::OR, dl, VT, Lo, Hi); | ||||||
6360 | }; | ||||||
6361 | |||||||
6362 | SDValue Next = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Hi); | ||||||
6363 | if (!MakeMUL_LOHI(LL, RH, Lo, Hi, false)) | ||||||
6364 | return false; | ||||||
6365 | |||||||
6366 | // This is effectively the add part of a multiply-add of half-sized operands, | ||||||
6367 | // so it cannot overflow. | ||||||
6368 | Next = DAG.getNode(ISD::ADD, dl, VT, Next, Merge(Lo, Hi)); | ||||||
6369 | |||||||
6370 | if (!MakeMUL_LOHI(LH, RL, Lo, Hi, false)) | ||||||
6371 | return false; | ||||||
6372 | |||||||
6373 | SDValue Zero = DAG.getConstant(0, dl, HiLoVT); | ||||||
6374 | EVT BoolType = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT); | ||||||
6375 | |||||||
6376 | bool UseGlue = (isOperationLegalOrCustom(ISD::ADDC, VT) && | ||||||
6377 | isOperationLegalOrCustom(ISD::ADDE, VT)); | ||||||
6378 | if (UseGlue) | ||||||
6379 | Next = DAG.getNode(ISD::ADDC, dl, DAG.getVTList(VT, MVT::Glue), Next, | ||||||
6380 | Merge(Lo, Hi)); | ||||||
6381 | else | ||||||
6382 | Next = DAG.getNode(ISD::ADDCARRY, dl, DAG.getVTList(VT, BoolType), Next, | ||||||
6383 | Merge(Lo, Hi), DAG.getConstant(0, dl, BoolType)); | ||||||
6384 | |||||||
6385 | SDValue Carry = Next.getValue(1); | ||||||
6386 | Result.push_back(DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, Next)); | ||||||
6387 | Next = DAG.getNode(ISD::SRL, dl, VT, Next, Shift); | ||||||
6388 | |||||||
6389 | if (!MakeMUL_LOHI(LH, RH, Lo, Hi, Opcode == ISD::SMUL_LOHI)) | ||||||
6390 | return false; | ||||||
6391 | |||||||
6392 | if (UseGlue) | ||||||
6393 | Hi = DAG.getNode(ISD::ADDE, dl, DAG.getVTList(HiLoVT, MVT::Glue), Hi, Zero, | ||||||
6394 | Carry); | ||||||
6395 | else | ||||||
6396 | Hi = DAG.getNode(ISD::ADDCARRY, dl, DAG.getVTList(HiLoVT, BoolType), Hi, | ||||||
6397 | Zero, Carry); | ||||||
6398 | |||||||
6399 | Next = DAG.getNode(ISD::ADD, dl, VT, Next, Merge(Lo, Hi)); | ||||||
6400 | |||||||
6401 | if (Opcode == ISD::SMUL_LOHI) { | ||||||
6402 | SDValue NextSub = DAG.getNode(ISD::SUB, dl, VT, Next, | ||||||
6403 | DAG.getNode(ISD::ZERO_EXTEND, dl, VT, RL)); | ||||||
6404 | Next = DAG.getSelectCC(dl, LH, Zero, NextSub, Next, ISD::SETLT); | ||||||
6405 | |||||||
6406 | NextSub = DAG.getNode(ISD::SUB, dl, VT, Next, | ||||||
6407 | DAG.getNode(ISD::ZERO_EXTEND, dl, VT, LL)); | ||||||
6408 | Next = DAG.getSelectCC(dl, RH, Zero, NextSub, Next, ISD::SETLT); | ||||||
6409 | } | ||||||
6410 | |||||||
6411 | Result.push_back(DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, Next)); | ||||||
6412 | Next = DAG.getNode(ISD::SRL, dl, VT, Next, Shift); | ||||||
6413 | Result.push_back(DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, Next)); | ||||||
6414 | return true; | ||||||
6415 | } | ||||||
6416 | |||||||
6417 | bool TargetLowering::expandMUL(SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT, | ||||||
6418 | SelectionDAG &DAG, MulExpansionKind Kind, | ||||||
6419 | SDValue LL, SDValue LH, SDValue RL, | ||||||
6420 | SDValue RH) const { | ||||||
6421 | SmallVector<SDValue, 2> Result; | ||||||
6422 | bool Ok = expandMUL_LOHI(N->getOpcode(), N->getValueType(0), SDLoc(N), | ||||||
6423 | N->getOperand(0), N->getOperand(1), Result, HiLoVT, | ||||||
6424 | DAG, Kind, LL, LH, RL, RH); | ||||||
6425 | if (Ok) { | ||||||
6426 | assert(Result.size() == 2)((Result.size() == 2) ? static_cast<void> (0) : __assert_fail ("Result.size() == 2", "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 6426, __PRETTY_FUNCTION__)); | ||||||
6427 | Lo = Result[0]; | ||||||
6428 | Hi = Result[1]; | ||||||
6429 | } | ||||||
6430 | return Ok; | ||||||
6431 | } | ||||||
6432 | |||||||
6433 | // Check that (every element of) Z is undef or not an exact multiple of BW. | ||||||
6434 | static bool isNonZeroModBitWidthOrUndef(SDValue Z, unsigned BW) { | ||||||
6435 | return ISD::matchUnaryPredicate( | ||||||
6436 | Z, | ||||||
6437 | [=](ConstantSDNode *C) { return !C || C->getAPIntValue().urem(BW) != 0; }, | ||||||
6438 | true); | ||||||
6439 | } | ||||||
6440 | |||||||
6441 | bool TargetLowering::expandFunnelShift(SDNode *Node, SDValue &Result, | ||||||
6442 | SelectionDAG &DAG) const { | ||||||
6443 | EVT VT = Node->getValueType(0); | ||||||
6444 | |||||||
6445 | if (VT.isVector() && (!isOperationLegalOrCustom(ISD::SHL, VT) || | ||||||
6446 | !isOperationLegalOrCustom(ISD::SRL, VT) || | ||||||
6447 | !isOperationLegalOrCustom(ISD::SUB, VT) || | ||||||
6448 | !isOperationLegalOrCustomOrPromote(ISD::OR, VT))) | ||||||
6449 | return false; | ||||||
6450 | |||||||
6451 | SDValue X = Node->getOperand(0); | ||||||
6452 | SDValue Y = Node->getOperand(1); | ||||||
6453 | SDValue Z = Node->getOperand(2); | ||||||
6454 | |||||||
6455 | unsigned BW = VT.getScalarSizeInBits(); | ||||||
6456 | bool IsFSHL = Node->getOpcode() == ISD::FSHL; | ||||||
6457 | SDLoc DL(SDValue(Node, 0)); | ||||||
6458 | |||||||
6459 | EVT ShVT = Z.getValueType(); | ||||||
6460 | |||||||
6461 | // If a funnel shift in the other direction is more supported, use it. | ||||||
6462 | unsigned RevOpcode = IsFSHL ? ISD::FSHR : ISD::FSHL; | ||||||
6463 | if (!isOperationLegalOrCustom(Node->getOpcode(), VT) && | ||||||
6464 | isOperationLegalOrCustom(RevOpcode, VT) && isPowerOf2_32(BW)) { | ||||||
6465 | if (isNonZeroModBitWidthOrUndef(Z, BW)) { | ||||||
6466 | // fshl X, Y, Z -> fshr X, Y, -Z | ||||||
6467 | // fshr X, Y, Z -> fshl X, Y, -Z | ||||||
6468 | SDValue Zero = DAG.getConstant(0, DL, ShVT); | ||||||
6469 | Z = DAG.getNode(ISD::SUB, DL, VT, Zero, Z); | ||||||
6470 | } else { | ||||||
6471 | // fshl X, Y, Z -> fshr (srl X, 1), (fshr X, Y, 1), ~Z | ||||||
6472 | // fshr X, Y, Z -> fshl (fshl X, Y, 1), (shl Y, 1), ~Z | ||||||
6473 | SDValue One = DAG.getConstant(1, DL, ShVT); | ||||||
6474 | if (IsFSHL) { | ||||||
6475 | Y = DAG.getNode(RevOpcode, DL, VT, X, Y, One); | ||||||
6476 | X = DAG.getNode(ISD::SRL, DL, VT, X, One); | ||||||
6477 | } else { | ||||||
6478 | X = DAG.getNode(RevOpcode, DL, VT, X, Y, One); | ||||||
6479 | Y = DAG.getNode(ISD::SHL, DL, VT, Y, One); | ||||||
6480 | } | ||||||
6481 | Z = DAG.getNOT(DL, Z, ShVT); | ||||||
6482 | } | ||||||
6483 | Result = DAG.getNode(RevOpcode, DL, VT, X, Y, Z); | ||||||
6484 | return true; | ||||||
6485 | } | ||||||
6486 | |||||||
6487 | SDValue ShX, ShY; | ||||||
6488 | SDValue ShAmt, InvShAmt; | ||||||
6489 | if (isNonZeroModBitWidthOrUndef(Z, BW)) { | ||||||
6490 | // fshl: X << C | Y >> (BW - C) | ||||||
6491 | // fshr: X << (BW - C) | Y >> C | ||||||
6492 | // where C = Z % BW is not zero | ||||||
6493 | SDValue BitWidthC = DAG.getConstant(BW, DL, ShVT); | ||||||
6494 | ShAmt = DAG.getNode(ISD::UREM, DL, ShVT, Z, BitWidthC); | ||||||
6495 | InvShAmt = DAG.getNode(ISD::SUB, DL, ShVT, BitWidthC, ShAmt); | ||||||
6496 | ShX = DAG.getNode(ISD::SHL, DL, VT, X, IsFSHL ? ShAmt : InvShAmt); | ||||||
6497 | ShY = DAG.getNode(ISD::SRL, DL, VT, Y, IsFSHL ? InvShAmt : ShAmt); | ||||||
6498 | } else { | ||||||
6499 | // fshl: X << (Z % BW) | Y >> 1 >> (BW - 1 - (Z % BW)) | ||||||
6500 | // fshr: X << 1 << (BW - 1 - (Z % BW)) | Y >> (Z % BW) | ||||||
6501 | SDValue Mask = DAG.getConstant(BW - 1, DL, ShVT); | ||||||
6502 | if (isPowerOf2_32(BW)) { | ||||||
6503 | // Z % BW -> Z & (BW - 1) | ||||||
6504 | ShAmt = DAG.getNode(ISD::AND, DL, ShVT, Z, Mask); | ||||||
6505 | // (BW - 1) - (Z % BW) -> ~Z & (BW - 1) | ||||||
6506 | InvShAmt = DAG.getNode(ISD::AND, DL, ShVT, DAG.getNOT(DL, Z, ShVT), Mask); | ||||||
6507 | } else { | ||||||
6508 | SDValue BitWidthC = DAG.getConstant(BW, DL, ShVT); | ||||||
6509 | ShAmt = DAG.getNode(ISD::UREM, DL, ShVT, Z, BitWidthC); | ||||||
6510 | InvShAmt = DAG.getNode(ISD::SUB, DL, ShVT, Mask, ShAmt); | ||||||
6511 | } | ||||||
6512 | |||||||
6513 | SDValue One = DAG.getConstant(1, DL, ShVT); | ||||||
6514 | if (IsFSHL) { | ||||||
6515 | ShX = DAG.getNode(ISD::SHL, DL, VT, X, ShAmt); | ||||||
6516 | SDValue ShY1 = DAG.getNode(ISD::SRL, DL, VT, Y, One); | ||||||
6517 | ShY = DAG.getNode(ISD::SRL, DL, VT, ShY1, InvShAmt); | ||||||
6518 | } else { | ||||||
6519 | SDValue ShX1 = DAG.getNode(ISD::SHL, DL, VT, X, One); | ||||||
6520 | ShX = DAG.getNode(ISD::SHL, DL, VT, ShX1, InvShAmt); | ||||||
6521 | ShY = DAG.getNode(ISD::SRL, DL, VT, Y, ShAmt); | ||||||
6522 | } | ||||||
6523 | } | ||||||
6524 | Result = DAG.getNode(ISD::OR, DL, VT, ShX, ShY); | ||||||
6525 | return true; | ||||||
6526 | } | ||||||
6527 | |||||||
6528 | // TODO: Merge with expandFunnelShift. | ||||||
6529 | bool TargetLowering::expandROT(SDNode *Node, bool AllowVectorOps, | ||||||
6530 | SDValue &Result, SelectionDAG &DAG) const { | ||||||
6531 | EVT VT = Node->getValueType(0); | ||||||
6532 | unsigned EltSizeInBits = VT.getScalarSizeInBits(); | ||||||
6533 | bool IsLeft = Node->getOpcode() == ISD::ROTL; | ||||||
6534 | SDValue Op0 = Node->getOperand(0); | ||||||
6535 | SDValue Op1 = Node->getOperand(1); | ||||||
6536 | SDLoc DL(SDValue(Node, 0)); | ||||||
6537 | |||||||
6538 | EVT ShVT = Op1.getValueType(); | ||||||
6539 | SDValue Zero = DAG.getConstant(0, DL, ShVT); | ||||||
6540 | |||||||
6541 | // If a rotate in the other direction is supported, use it. | ||||||
6542 | unsigned RevRot = IsLeft ? ISD::ROTR : ISD::ROTL; | ||||||
6543 | if (isOperationLegalOrCustom(RevRot, VT) && isPowerOf2_32(EltSizeInBits)) { | ||||||
6544 | SDValue Sub = DAG.getNode(ISD::SUB, DL, ShVT, Zero, Op1); | ||||||
6545 | Result = DAG.getNode(RevRot, DL, VT, Op0, Sub); | ||||||
6546 | return true; | ||||||
6547 | } | ||||||
6548 | |||||||
6549 | if (!AllowVectorOps && VT.isVector() && | ||||||
6550 | (!isOperationLegalOrCustom(ISD::SHL, VT) || | ||||||
6551 | !isOperationLegalOrCustom(ISD::SRL, VT) || | ||||||
6552 | !isOperationLegalOrCustom(ISD::SUB, VT) || | ||||||
6553 | !isOperationLegalOrCustomOrPromote(ISD::OR, VT) || | ||||||
6554 | !isOperationLegalOrCustomOrPromote(ISD::AND, VT))) | ||||||
6555 | return false; | ||||||
6556 | |||||||
6557 | unsigned ShOpc = IsLeft ? ISD::SHL : ISD::SRL; | ||||||
6558 | unsigned HsOpc = IsLeft ? ISD::SRL : ISD::SHL; | ||||||
6559 | SDValue BitWidthMinusOneC = DAG.getConstant(EltSizeInBits - 1, DL, ShVT); | ||||||
6560 | SDValue ShVal; | ||||||
6561 | SDValue HsVal; | ||||||
6562 | if (isPowerOf2_32(EltSizeInBits)) { | ||||||
6563 | // (rotl x, c) -> x << (c & (w - 1)) | x >> (-c & (w - 1)) | ||||||
6564 | // (rotr x, c) -> x >> (c & (w - 1)) | x << (-c & (w - 1)) | ||||||
6565 | SDValue NegOp1 = DAG.getNode(ISD::SUB, DL, ShVT, Zero, Op1); | ||||||
6566 | SDValue ShAmt = DAG.getNode(ISD::AND, DL, ShVT, Op1, BitWidthMinusOneC); | ||||||
6567 | ShVal = DAG.getNode(ShOpc, DL, VT, Op0, ShAmt); | ||||||
6568 | SDValue HsAmt = DAG.getNode(ISD::AND, DL, ShVT, NegOp1, BitWidthMinusOneC); | ||||||
6569 | HsVal = DAG.getNode(HsOpc, DL, VT, Op0, HsAmt); | ||||||
6570 | } else { | ||||||
6571 | // (rotl x, c) -> x << (c % w) | x >> 1 >> (w - 1 - (c % w)) | ||||||
6572 | // (rotr x, c) -> x >> (c % w) | x << 1 << (w - 1 - (c % w)) | ||||||
6573 | SDValue BitWidthC = DAG.getConstant(EltSizeInBits, DL, ShVT); | ||||||
6574 | SDValue ShAmt = DAG.getNode(ISD::UREM, DL, ShVT, Op1, BitWidthC); | ||||||
6575 | ShVal = DAG.getNode(ShOpc, DL, VT, Op0, ShAmt); | ||||||
6576 | SDValue HsAmt = DAG.getNode(ISD::SUB, DL, ShVT, BitWidthMinusOneC, ShAmt); | ||||||
6577 | SDValue One = DAG.getConstant(1, DL, ShVT); | ||||||
6578 | HsVal = | ||||||
6579 | DAG.getNode(HsOpc, DL, VT, DAG.getNode(HsOpc, DL, VT, Op0, One), HsAmt); | ||||||
6580 | } | ||||||
6581 | Result = DAG.getNode(ISD::OR, DL, VT, ShVal, HsVal); | ||||||
6582 | return true; | ||||||
6583 | } | ||||||
6584 | |||||||
6585 | bool TargetLowering::expandFP_TO_SINT(SDNode *Node, SDValue &Result, | ||||||
6586 | SelectionDAG &DAG) const { | ||||||
6587 | unsigned OpNo = Node->isStrictFPOpcode() ? 1 : 0; | ||||||
6588 | SDValue Src = Node->getOperand(OpNo); | ||||||
6589 | EVT SrcVT = Src.getValueType(); | ||||||
6590 | EVT DstVT = Node->getValueType(0); | ||||||
6591 | SDLoc dl(SDValue(Node, 0)); | ||||||
6592 | |||||||
6593 | // FIXME: Only f32 to i64 conversions are supported. | ||||||
6594 | if (SrcVT != MVT::f32 || DstVT != MVT::i64) | ||||||
6595 | return false; | ||||||
6596 | |||||||
6597 | if (Node->isStrictFPOpcode()) | ||||||
6598 | // When a NaN is converted to an integer a trap is allowed. We can't | ||||||
6599 | // use this expansion here because it would eliminate that trap. Other | ||||||
6600 | // traps are also allowed and cannot be eliminated. See | ||||||
6601 | // IEEE 754-2008 sec 5.8. | ||||||
6602 | return false; | ||||||
6603 | |||||||
6604 | // Expand f32 -> i64 conversion | ||||||
6605 | // This algorithm comes from compiler-rt's implementation of fixsfdi: | ||||||
6606 | // https://github.com/llvm/llvm-project/blob/main/compiler-rt/lib/builtins/fixsfdi.c | ||||||
6607 | unsigned SrcEltBits = SrcVT.getScalarSizeInBits(); | ||||||
6608 | EVT IntVT = SrcVT.changeTypeToInteger(); | ||||||
6609 | EVT IntShVT = getShiftAmountTy(IntVT, DAG.getDataLayout()); | ||||||
6610 | |||||||
6611 | SDValue ExponentMask = DAG.getConstant(0x7F800000, dl, IntVT); | ||||||
6612 | SDValue ExponentLoBit = DAG.getConstant(23, dl, IntVT); | ||||||
6613 | SDValue Bias = DAG.getConstant(127, dl, IntVT); | ||||||
6614 | SDValue SignMask = DAG.getConstant(APInt::getSignMask(SrcEltBits), dl, IntVT); | ||||||
6615 | SDValue SignLowBit = DAG.getConstant(SrcEltBits - 1, dl, IntVT); | ||||||
6616 | SDValue MantissaMask = DAG.getConstant(0x007FFFFF, dl, IntVT); | ||||||
6617 | |||||||
6618 | SDValue Bits = DAG.getNode(ISD::BITCAST, dl, IntVT, Src); | ||||||
6619 | |||||||
6620 | SDValue ExponentBits = DAG.getNode( | ||||||
6621 | ISD::SRL, dl, IntVT, DAG.getNode(ISD::AND, dl, IntVT, Bits, ExponentMask), | ||||||
6622 | DAG.getZExtOrTrunc(ExponentLoBit, dl, IntShVT)); | ||||||
6623 | SDValue Exponent = DAG.getNode(ISD::SUB, dl, IntVT, ExponentBits, Bias); | ||||||
6624 | |||||||
6625 | SDValue Sign = DAG.getNode(ISD::SRA, dl, IntVT, | ||||||
6626 | DAG.getNode(ISD::AND, dl, IntVT, Bits, SignMask), | ||||||
6627 | DAG.getZExtOrTrunc(SignLowBit, dl, IntShVT)); | ||||||
6628 | Sign = DAG.getSExtOrTrunc(Sign, dl, DstVT); | ||||||
6629 | |||||||
6630 | SDValue R = DAG.getNode(ISD::OR, dl, IntVT, | ||||||
6631 | DAG.getNode(ISD::AND, dl, IntVT, Bits, MantissaMask), | ||||||
6632 | DAG.getConstant(0x00800000, dl, IntVT)); | ||||||
6633 | |||||||
6634 | R = DAG.getZExtOrTrunc(R, dl, DstVT); | ||||||
6635 | |||||||
6636 | R = DAG.getSelectCC( | ||||||
6637 | dl, Exponent, ExponentLoBit, | ||||||
6638 | DAG.getNode(ISD::SHL, dl, DstVT, R, | ||||||
6639 | DAG.getZExtOrTrunc( | ||||||
6640 | DAG.getNode(ISD::SUB, dl, IntVT, Exponent, ExponentLoBit), | ||||||
6641 | dl, IntShVT)), | ||||||
6642 | DAG.getNode(ISD::SRL, dl, DstVT, R, | ||||||
6643 | DAG.getZExtOrTrunc( | ||||||
6644 | DAG.getNode(ISD::SUB, dl, IntVT, ExponentLoBit, Exponent), | ||||||
6645 | dl, IntShVT)), | ||||||
6646 | ISD::SETGT); | ||||||
6647 | |||||||
6648 | SDValue Ret = DAG.getNode(ISD::SUB, dl, DstVT, | ||||||
6649 | DAG.getNode(ISD::XOR, dl, DstVT, R, Sign), Sign); | ||||||
6650 | |||||||
6651 | Result = DAG.getSelectCC(dl, Exponent, DAG.getConstant(0, dl, IntVT), | ||||||
6652 | DAG.getConstant(0, dl, DstVT), Ret, ISD::SETLT); | ||||||
6653 | return true; | ||||||
6654 | } | ||||||
6655 | |||||||
6656 | bool TargetLowering::expandFP_TO_UINT(SDNode *Node, SDValue &Result, | ||||||
6657 | SDValue &Chain, | ||||||
6658 | SelectionDAG &DAG) const { | ||||||
6659 | SDLoc dl(SDValue(Node, 0)); | ||||||
6660 | unsigned OpNo = Node->isStrictFPOpcode() ? 1 : 0; | ||||||
6661 | SDValue Src = Node->getOperand(OpNo); | ||||||
6662 | |||||||
6663 | EVT SrcVT = Src.getValueType(); | ||||||
6664 | EVT DstVT = Node->getValueType(0); | ||||||
6665 | EVT SetCCVT = | ||||||
6666 | getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), SrcVT); | ||||||
6667 | EVT DstSetCCVT = | ||||||
6668 | getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), DstVT); | ||||||
6669 | |||||||
6670 | // Only expand vector types if we have the appropriate vector bit operations. | ||||||
6671 | unsigned SIntOpcode = Node->isStrictFPOpcode() ? ISD::STRICT_FP_TO_SINT : | ||||||
6672 | ISD::FP_TO_SINT; | ||||||
6673 | if (DstVT.isVector() && (!isOperationLegalOrCustom(SIntOpcode, DstVT) || | ||||||
6674 | !isOperationLegalOrCustomOrPromote(ISD::XOR, SrcVT))) | ||||||
6675 | return false; | ||||||
6676 | |||||||
6677 | // If the maximum float value is smaller then the signed integer range, | ||||||
6678 | // the destination signmask can't be represented by the float, so we can | ||||||
6679 | // just use FP_TO_SINT directly. | ||||||
6680 | const fltSemantics &APFSem = DAG.EVTToAPFloatSemantics(SrcVT); | ||||||
6681 | APFloat APF(APFSem, APInt::getNullValue(SrcVT.getScalarSizeInBits())); | ||||||
6682 | APInt SignMask = APInt::getSignMask(DstVT.getScalarSizeInBits()); | ||||||
6683 | if (APFloat::opOverflow & | ||||||
6684 | APF.convertFromAPInt(SignMask, false, APFloat::rmNearestTiesToEven)) { | ||||||
6685 | if (Node->isStrictFPOpcode()) { | ||||||
6686 | Result = DAG.getNode(ISD::STRICT_FP_TO_SINT, dl, { DstVT, MVT::Other }, | ||||||
6687 | { Node->getOperand(0), Src }); | ||||||
6688 | Chain = Result.getValue(1); | ||||||
6689 | } else | ||||||
6690 | Result = DAG.getNode(ISD::FP_TO_SINT, dl, DstVT, Src); | ||||||
6691 | return true; | ||||||
6692 | } | ||||||
6693 | |||||||
6694 | // Don't expand it if there isn't cheap fsub instruction. | ||||||
6695 | if (!isOperationLegalOrCustom( | ||||||
6696 | Node->isStrictFPOpcode() ? ISD::STRICT_FSUB : ISD::FSUB, SrcVT)) | ||||||
6697 | return false; | ||||||
6698 | |||||||
6699 | SDValue Cst = DAG.getConstantFP(APF, dl, SrcVT); | ||||||
6700 | SDValue Sel; | ||||||
6701 | |||||||
6702 | if (Node->isStrictFPOpcode()) { | ||||||
6703 | Sel = DAG.getSetCC(dl, SetCCVT, Src, Cst, ISD::SETLT, | ||||||
6704 | Node->getOperand(0), /*IsSignaling*/ true); | ||||||
6705 | Chain = Sel.getValue(1); | ||||||
6706 | } else { | ||||||
6707 | Sel = DAG.getSetCC(dl, SetCCVT, Src, Cst, ISD::SETLT); | ||||||
6708 | } | ||||||
6709 | |||||||
6710 | bool Strict = Node->isStrictFPOpcode() || | ||||||
6711 | shouldUseStrictFP_TO_INT(SrcVT, DstVT, /*IsSigned*/ false); | ||||||
6712 | |||||||
6713 | if (Strict) { | ||||||
6714 | // Expand based on maximum range of FP_TO_SINT, if the value exceeds the | ||||||
6715 | // signmask then offset (the result of which should be fully representable). | ||||||
6716 | // Sel = Src < 0x8000000000000000 | ||||||
6717 | // FltOfs = select Sel, 0, 0x8000000000000000 | ||||||
6718 | // IntOfs = select Sel, 0, 0x8000000000000000 | ||||||
6719 | // Result = fp_to_sint(Src - FltOfs) ^ IntOfs | ||||||
6720 | |||||||
6721 | // TODO: Should any fast-math-flags be set for the FSUB? | ||||||
6722 | SDValue FltOfs = DAG.getSelect(dl, SrcVT, Sel, | ||||||
6723 | DAG.getConstantFP(0.0, dl, SrcVT), Cst); | ||||||
6724 | Sel = DAG.getBoolExtOrTrunc(Sel, dl, DstSetCCVT, DstVT); | ||||||
6725 | SDValue IntOfs = DAG.getSelect(dl, DstVT, Sel, | ||||||
6726 | DAG.getConstant(0, dl, DstVT), | ||||||
6727 | DAG.getConstant(SignMask, dl, DstVT)); | ||||||
6728 | SDValue SInt; | ||||||
6729 | if (Node->isStrictFPOpcode()) { | ||||||
6730 | SDValue Val = DAG.getNode(ISD::STRICT_FSUB, dl, { SrcVT, MVT::Other }, | ||||||
6731 | { Chain, Src, FltOfs }); | ||||||
6732 | SInt = DAG.getNode(ISD::STRICT_FP_TO_SINT, dl, { DstVT, MVT::Other }, | ||||||
6733 | { Val.getValue(1), Val }); | ||||||
6734 | Chain = SInt.getValue(1); | ||||||
6735 | } else { | ||||||
6736 | SDValue Val = DAG.getNode(ISD::FSUB, dl, SrcVT, Src, FltOfs); | ||||||
6737 | SInt = DAG.getNode(ISD::FP_TO_SINT, dl, DstVT, Val); | ||||||
6738 | } | ||||||
6739 | Result = DAG.getNode(ISD::XOR, dl, DstVT, SInt, IntOfs); | ||||||
6740 | } else { | ||||||
6741 | // Expand based on maximum range of FP_TO_SINT: | ||||||
6742 | // True = fp_to_sint(Src) | ||||||
6743 | // False = 0x8000000000000000 + fp_to_sint(Src - 0x8000000000000000) | ||||||
6744 | // Result = select (Src < 0x8000000000000000), True, False | ||||||
6745 | |||||||
6746 | SDValue True = DAG.getNode(ISD::FP_TO_SINT, dl, DstVT, Src); | ||||||
6747 | // TODO: Should any fast-math-flags be set for the FSUB? | ||||||
6748 | SDValue False = DAG.getNode(ISD::FP_TO_SINT, dl, DstVT, | ||||||
6749 | DAG.getNode(ISD::FSUB, dl, SrcVT, Src, Cst)); | ||||||
6750 | False = DAG.getNode(ISD::XOR, dl, DstVT, False, | ||||||
6751 | DAG.getConstant(SignMask, dl, DstVT)); | ||||||
6752 | Sel = DAG.getBoolExtOrTrunc(Sel, dl, DstSetCCVT, DstVT); | ||||||
6753 | Result = DAG.getSelect(dl, DstVT, Sel, True, False); | ||||||
6754 | } | ||||||
6755 | return true; | ||||||
6756 | } | ||||||
6757 | |||||||
6758 | bool TargetLowering::expandUINT_TO_FP(SDNode *Node, SDValue &Result, | ||||||
6759 | SDValue &Chain, | ||||||
6760 | SelectionDAG &DAG) const { | ||||||
6761 | // This transform is not correct for converting 0 when rounding mode is set | ||||||
6762 | // to round toward negative infinity which will produce -0.0. So disable under | ||||||
6763 | // strictfp. | ||||||
6764 | if (Node->isStrictFPOpcode()) | ||||||
6765 | return false; | ||||||
6766 | |||||||
6767 | SDValue Src = Node->getOperand(0); | ||||||
6768 | EVT SrcVT = Src.getValueType(); | ||||||
6769 | EVT DstVT = Node->getValueType(0); | ||||||
6770 | |||||||
6771 | if (SrcVT.getScalarType() != MVT::i64 || DstVT.getScalarType() != MVT::f64) | ||||||
6772 | return false; | ||||||
6773 | |||||||
6774 | // Only expand vector types if we have the appropriate vector bit operations. | ||||||
6775 | if (SrcVT.isVector() && (!isOperationLegalOrCustom(ISD::SRL, SrcVT) || | ||||||
6776 | !isOperationLegalOrCustom(ISD::FADD, DstVT) || | ||||||
6777 | !isOperationLegalOrCustom(ISD::FSUB, DstVT) || | ||||||
6778 | !isOperationLegalOrCustomOrPromote(ISD::OR, SrcVT) || | ||||||
6779 | !isOperationLegalOrCustomOrPromote(ISD::AND, SrcVT))) | ||||||
6780 | return false; | ||||||
6781 | |||||||
6782 | SDLoc dl(SDValue(Node, 0)); | ||||||
6783 | EVT ShiftVT = getShiftAmountTy(SrcVT, DAG.getDataLayout()); | ||||||
6784 | |||||||
6785 | // Implementation of unsigned i64 to f64 following the algorithm in | ||||||
6786 | // __floatundidf in compiler_rt. This implementation performs rounding | ||||||
6787 | // correctly in all rounding modes with the exception of converting 0 | ||||||
6788 | // when rounding toward negative infinity. In that case the fsub will produce | ||||||
6789 | // -0.0. This will be added to +0.0 and produce -0.0 which is incorrect. | ||||||
6790 | SDValue TwoP52 = DAG.getConstant(UINT64_C(0x4330000000000000)0x4330000000000000UL, dl, SrcVT); | ||||||
6791 | SDValue TwoP84PlusTwoP52 = DAG.getConstantFP( | ||||||
6792 | BitsToDouble(UINT64_C(0x4530000000100000)0x4530000000100000UL), dl, DstVT); | ||||||
6793 | SDValue TwoP84 = DAG.getConstant(UINT64_C(0x4530000000000000)0x4530000000000000UL, dl, SrcVT); | ||||||
6794 | SDValue LoMask = DAG.getConstant(UINT64_C(0x00000000FFFFFFFF)0x00000000FFFFFFFFUL, dl, SrcVT); | ||||||
6795 | SDValue HiShift = DAG.getConstant(32, dl, ShiftVT); | ||||||
6796 | |||||||
6797 | SDValue Lo = DAG.getNode(ISD::AND, dl, SrcVT, Src, LoMask); | ||||||
6798 | SDValue Hi = DAG.getNode(ISD::SRL, dl, SrcVT, Src, HiShift); | ||||||
6799 | SDValue LoOr = DAG.getNode(ISD::OR, dl, SrcVT, Lo, TwoP52); | ||||||
6800 | SDValue HiOr = DAG.getNode(ISD::OR, dl, SrcVT, Hi, TwoP84); | ||||||
6801 | SDValue LoFlt = DAG.getBitcast(DstVT, LoOr); | ||||||
6802 | SDValue HiFlt = DAG.getBitcast(DstVT, HiOr); | ||||||
6803 | SDValue HiSub = | ||||||
6804 | DAG.getNode(ISD::FSUB, dl, DstVT, HiFlt, TwoP84PlusTwoP52); | ||||||
6805 | Result = DAG.getNode(ISD::FADD, dl, DstVT, LoFlt, HiSub); | ||||||
6806 | return true; | ||||||
6807 | } | ||||||
6808 | |||||||
6809 | SDValue TargetLowering::expandFMINNUM_FMAXNUM(SDNode *Node, | ||||||
6810 | SelectionDAG &DAG) const { | ||||||
6811 | SDLoc dl(Node); | ||||||
6812 | unsigned NewOp = Node->getOpcode() == ISD::FMINNUM ? | ||||||
6813 | ISD::FMINNUM_IEEE : ISD::FMAXNUM_IEEE; | ||||||
6814 | EVT VT = Node->getValueType(0); | ||||||
6815 | |||||||
6816 | if (VT.isScalableVector()) | ||||||
6817 | report_fatal_error( | ||||||
6818 | "Expanding fminnum/fmaxnum for scalable vectors is undefined."); | ||||||
6819 | |||||||
6820 | if (isOperationLegalOrCustom(NewOp, VT)) { | ||||||
6821 | SDValue Quiet0 = Node->getOperand(0); | ||||||
6822 | SDValue Quiet1 = Node->getOperand(1); | ||||||
6823 | |||||||
6824 | if (!Node->getFlags().hasNoNaNs()) { | ||||||
6825 | // Insert canonicalizes if it's possible we need to quiet to get correct | ||||||
6826 | // sNaN behavior. | ||||||
6827 | if (!DAG.isKnownNeverSNaN(Quiet0)) { | ||||||
6828 | Quiet0 = DAG.getNode(ISD::FCANONICALIZE, dl, VT, Quiet0, | ||||||
6829 | Node->getFlags()); | ||||||
6830 | } | ||||||
6831 | if (!DAG.isKnownNeverSNaN(Quiet1)) { | ||||||
6832 | Quiet1 = DAG.getNode(ISD::FCANONICALIZE, dl, VT, Quiet1, | ||||||
6833 | Node->getFlags()); | ||||||
6834 | } | ||||||
6835 | } | ||||||
6836 | |||||||
6837 | return DAG.getNode(NewOp, dl, VT, Quiet0, Quiet1, Node->getFlags()); | ||||||
6838 | } | ||||||
6839 | |||||||
6840 | // If the target has FMINIMUM/FMAXIMUM but not FMINNUM/FMAXNUM use that | ||||||
6841 | // instead if there are no NaNs. | ||||||
6842 | if (Node->getFlags().hasNoNaNs()) { | ||||||
6843 | unsigned IEEE2018Op = | ||||||
6844 | Node->getOpcode() == ISD::FMINNUM ? ISD::FMINIMUM : ISD::FMAXIMUM; | ||||||
6845 | if (isOperationLegalOrCustom(IEEE2018Op, VT)) { | ||||||
6846 | return DAG.getNode(IEEE2018Op, dl, VT, Node->getOperand(0), | ||||||
6847 | Node->getOperand(1), Node->getFlags()); | ||||||
6848 | } | ||||||
6849 | } | ||||||
6850 | |||||||
6851 | // If none of the above worked, but there are no NaNs, then expand to | ||||||
6852 | // a compare/select sequence. This is required for correctness since | ||||||
6853 | // InstCombine might have canonicalized a fcmp+select sequence to a | ||||||
6854 | // FMINNUM/FMAXNUM node. If we were to fall through to the default | ||||||
6855 | // expansion to libcall, we might introduce a link-time dependency | ||||||
6856 | // on libm into a file that originally did not have one. | ||||||
6857 | if (Node->getFlags().hasNoNaNs()) { | ||||||
6858 | ISD::CondCode Pred = | ||||||
6859 | Node->getOpcode() == ISD::FMINNUM ? ISD::SETLT : ISD::SETGT; | ||||||
6860 | SDValue Op1 = Node->getOperand(0); | ||||||
6861 | SDValue Op2 = Node->getOperand(1); | ||||||
6862 | SDValue SelCC = DAG.getSelectCC(dl, Op1, Op2, Op1, Op2, Pred); | ||||||
6863 | // Copy FMF flags, but always set the no-signed-zeros flag | ||||||
6864 | // as this is implied by the FMINNUM/FMAXNUM semantics. | ||||||
6865 | SDNodeFlags Flags = Node->getFlags(); | ||||||
6866 | Flags.setNoSignedZeros(true); | ||||||
6867 | SelCC->setFlags(Flags); | ||||||
6868 | return SelCC; | ||||||
6869 | } | ||||||
6870 | |||||||
6871 | return SDValue(); | ||||||
6872 | } | ||||||
6873 | |||||||
6874 | bool TargetLowering::expandCTPOP(SDNode *Node, SDValue &Result, | ||||||
6875 | SelectionDAG &DAG) const { | ||||||
6876 | SDLoc dl(Node); | ||||||
6877 | EVT VT = Node->getValueType(0); | ||||||
6878 | EVT ShVT = getShiftAmountTy(VT, DAG.getDataLayout()); | ||||||
6879 | SDValue Op = Node->getOperand(0); | ||||||
6880 | unsigned Len = VT.getScalarSizeInBits(); | ||||||
6881 | assert(VT.isInteger() && "CTPOP not implemented for this type.")((VT.isInteger() && "CTPOP not implemented for this type." ) ? static_cast<void> (0) : __assert_fail ("VT.isInteger() && \"CTPOP not implemented for this type.\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 6881, __PRETTY_FUNCTION__)); | ||||||
6882 | |||||||
6883 | // TODO: Add support for irregular type lengths. | ||||||
6884 | if (!(Len <= 128 && Len % 8 == 0)) | ||||||
6885 | return false; | ||||||
6886 | |||||||
6887 | // Only expand vector types if we have the appropriate vector bit operations. | ||||||
6888 | if (VT.isVector() && (!isOperationLegalOrCustom(ISD::ADD, VT) || | ||||||
6889 | !isOperationLegalOrCustom(ISD::SUB, VT) || | ||||||
6890 | !isOperationLegalOrCustom(ISD::SRL, VT) || | ||||||
6891 | (Len != 8 && !isOperationLegalOrCustom(ISD::MUL, VT)) || | ||||||
6892 | !isOperationLegalOrCustomOrPromote(ISD::AND, VT))) | ||||||
6893 | return false; | ||||||
6894 | |||||||
6895 | // This is the "best" algorithm from | ||||||
6896 | // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel | ||||||
6897 | SDValue Mask55 = | ||||||
6898 | DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x55)), dl, VT); | ||||||
6899 | SDValue Mask33 = | ||||||
6900 | DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x33)), dl, VT); | ||||||
6901 | SDValue Mask0F = | ||||||
6902 | DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x0F)), dl, VT); | ||||||
6903 | SDValue Mask01 = | ||||||
6904 | DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x01)), dl, VT); | ||||||
6905 | |||||||
6906 | // v = v - ((v >> 1) & 0x55555555...) | ||||||
6907 | Op = DAG.getNode(ISD::SUB, dl, VT, Op, | ||||||
6908 | DAG.getNode(ISD::AND, dl, VT, | ||||||
6909 | DAG.getNode(ISD::SRL, dl, VT, Op, | ||||||
6910 | DAG.getConstant(1, dl, ShVT)), | ||||||
6911 | Mask55)); | ||||||
6912 | // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...) | ||||||
6913 | Op = DAG.getNode(ISD::ADD, dl, VT, DAG.getNode(ISD::AND, dl, VT, Op, Mask33), | ||||||
6914 | DAG.getNode(ISD::AND, dl, VT, | ||||||
6915 | DAG.getNode(ISD::SRL, dl, VT, Op, | ||||||
6916 | DAG.getConstant(2, dl, ShVT)), | ||||||
6917 | Mask33)); | ||||||
6918 | // v = (v + (v >> 4)) & 0x0F0F0F0F... | ||||||
6919 | Op = DAG.getNode(ISD::AND, dl, VT, | ||||||
6920 | DAG.getNode(ISD::ADD, dl, VT, Op, | ||||||
6921 | DAG.getNode(ISD::SRL, dl, VT, Op, | ||||||
6922 | DAG.getConstant(4, dl, ShVT))), | ||||||
6923 | Mask0F); | ||||||
6924 | // v = (v * 0x01010101...) >> (Len - 8) | ||||||
6925 | if (Len > 8) | ||||||
6926 | Op = | ||||||
6927 | DAG.getNode(ISD::SRL, dl, VT, DAG.getNode(ISD::MUL, dl, VT, Op, Mask01), | ||||||
6928 | DAG.getConstant(Len - 8, dl, ShVT)); | ||||||
6929 | |||||||
6930 | Result = Op; | ||||||
6931 | return true; | ||||||
6932 | } | ||||||
6933 | |||||||
6934 | bool TargetLowering::expandCTLZ(SDNode *Node, SDValue &Result, | ||||||
6935 | SelectionDAG &DAG) const { | ||||||
6936 | SDLoc dl(Node); | ||||||
6937 | EVT VT = Node->getValueType(0); | ||||||
6938 | EVT ShVT = getShiftAmountTy(VT, DAG.getDataLayout()); | ||||||
6939 | SDValue Op = Node->getOperand(0); | ||||||
6940 | unsigned NumBitsPerElt = VT.getScalarSizeInBits(); | ||||||
6941 | |||||||
6942 | // If the non-ZERO_UNDEF version is supported we can use that instead. | ||||||
6943 | if (Node->getOpcode() == ISD::CTLZ_ZERO_UNDEF && | ||||||
6944 | isOperationLegalOrCustom(ISD::CTLZ, VT)) { | ||||||
6945 | Result = DAG.getNode(ISD::CTLZ, dl, VT, Op); | ||||||
6946 | return true; | ||||||
6947 | } | ||||||
6948 | |||||||
6949 | // If the ZERO_UNDEF version is supported use that and handle the zero case. | ||||||
6950 | if (isOperationLegalOrCustom(ISD::CTLZ_ZERO_UNDEF, VT)) { | ||||||
6951 | EVT SetCCVT = | ||||||
6952 | getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT); | ||||||
6953 | SDValue CTLZ = DAG.getNode(ISD::CTLZ_ZERO_UNDEF, dl, VT, Op); | ||||||
6954 | SDValue Zero = DAG.getConstant(0, dl, VT); | ||||||
6955 | SDValue SrcIsZero = DAG.getSetCC(dl, SetCCVT, Op, Zero, ISD::SETEQ); | ||||||
6956 | Result = DAG.getNode(ISD::SELECT, dl, VT, SrcIsZero, | ||||||
6957 | DAG.getConstant(NumBitsPerElt, dl, VT), CTLZ); | ||||||
6958 | return true; | ||||||
6959 | } | ||||||
6960 | |||||||
6961 | // Only expand vector types if we have the appropriate vector bit operations. | ||||||
6962 | if (VT.isVector() && (!isPowerOf2_32(NumBitsPerElt) || | ||||||
6963 | !isOperationLegalOrCustom(ISD::CTPOP, VT) || | ||||||
6964 | !isOperationLegalOrCustom(ISD::SRL, VT) || | ||||||
6965 | !isOperationLegalOrCustomOrPromote(ISD::OR, VT))) | ||||||
6966 | return false; | ||||||
6967 | |||||||
6968 | // for now, we do this: | ||||||
6969 | // x = x | (x >> 1); | ||||||
6970 | // x = x | (x >> 2); | ||||||
6971 | // ... | ||||||
6972 | // x = x | (x >>16); | ||||||
6973 | // x = x | (x >>32); // for 64-bit input | ||||||
6974 | // return popcount(~x); | ||||||
6975 | // | ||||||
6976 | // Ref: "Hacker's Delight" by Henry Warren | ||||||
6977 | for (unsigned i = 0; (1U << i) <= (NumBitsPerElt / 2); ++i) { | ||||||
6978 | SDValue Tmp = DAG.getConstant(1ULL << i, dl, ShVT); | ||||||
6979 | Op = DAG.getNode(ISD::OR, dl, VT, Op, | ||||||
6980 | DAG.getNode(ISD::SRL, dl, VT, Op, Tmp)); | ||||||
6981 | } | ||||||
6982 | Op = DAG.getNOT(dl, Op, VT); | ||||||
6983 | Result = DAG.getNode(ISD::CTPOP, dl, VT, Op); | ||||||
6984 | return true; | ||||||
6985 | } | ||||||
6986 | |||||||
6987 | bool TargetLowering::expandCTTZ(SDNode *Node, SDValue &Result, | ||||||
6988 | SelectionDAG &DAG) const { | ||||||
6989 | SDLoc dl(Node); | ||||||
6990 | EVT VT = Node->getValueType(0); | ||||||
6991 | SDValue Op = Node->getOperand(0); | ||||||
6992 | unsigned NumBitsPerElt = VT.getScalarSizeInBits(); | ||||||
6993 | |||||||
6994 | // If the non-ZERO_UNDEF version is supported we can use that instead. | ||||||
6995 | if (Node->getOpcode() == ISD::CTTZ_ZERO_UNDEF && | ||||||
6996 | isOperationLegalOrCustom(ISD::CTTZ, VT)) { | ||||||
6997 | Result = DAG.getNode(ISD::CTTZ, dl, VT, Op); | ||||||
6998 | return true; | ||||||
6999 | } | ||||||
7000 | |||||||
7001 | // If the ZERO_UNDEF version is supported use that and handle the zero case. | ||||||
7002 | if (isOperationLegalOrCustom(ISD::CTTZ_ZERO_UNDEF, VT)) { | ||||||
7003 | EVT SetCCVT = | ||||||
7004 | getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT); | ||||||
7005 | SDValue CTTZ = DAG.getNode(ISD::CTTZ_ZERO_UNDEF, dl, VT, Op); | ||||||
7006 | SDValue Zero = DAG.getConstant(0, dl, VT); | ||||||
7007 | SDValue SrcIsZero = DAG.getSetCC(dl, SetCCVT, Op, Zero, ISD::SETEQ); | ||||||
7008 | Result = DAG.getNode(ISD::SELECT, dl, VT, SrcIsZero, | ||||||
7009 | DAG.getConstant(NumBitsPerElt, dl, VT), CTTZ); | ||||||
7010 | return true; | ||||||
7011 | } | ||||||
7012 | |||||||
7013 | // Only expand vector types if we have the appropriate vector bit operations. | ||||||
7014 | if (VT.isVector() && (!isPowerOf2_32(NumBitsPerElt) || | ||||||
7015 | (!isOperationLegalOrCustom(ISD::CTPOP, VT) && | ||||||
7016 | !isOperationLegalOrCustom(ISD::CTLZ, VT)) || | ||||||
7017 | !isOperationLegalOrCustom(ISD::SUB, VT) || | ||||||
7018 | !isOperationLegalOrCustomOrPromote(ISD::AND, VT) || | ||||||
7019 | !isOperationLegalOrCustomOrPromote(ISD::XOR, VT))) | ||||||
7020 | return false; | ||||||
7021 | |||||||
7022 | // for now, we use: { return popcount(~x & (x - 1)); } | ||||||
7023 | // unless the target has ctlz but not ctpop, in which case we use: | ||||||
7024 | // { return 32 - nlz(~x & (x-1)); } | ||||||
7025 | // Ref: "Hacker's Delight" by Henry Warren | ||||||
7026 | SDValue Tmp = DAG.getNode( | ||||||
7027 | ISD::AND, dl, VT, DAG.getNOT(dl, Op, VT), | ||||||
7028 | DAG.getNode(ISD::SUB, dl, VT, Op, DAG.getConstant(1, dl, VT))); | ||||||
7029 | |||||||
7030 | // If ISD::CTLZ is legal and CTPOP isn't, then do that instead. | ||||||
7031 | if (isOperationLegal(ISD::CTLZ, VT) && !isOperationLegal(ISD::CTPOP, VT)) { | ||||||
7032 | Result = | ||||||
7033 | DAG.getNode(ISD::SUB, dl, VT, DAG.getConstant(NumBitsPerElt, dl, VT), | ||||||
7034 | DAG.getNode(ISD::CTLZ, dl, VT, Tmp)); | ||||||
7035 | return true; | ||||||
7036 | } | ||||||
7037 | |||||||
7038 | Result = DAG.getNode(ISD::CTPOP, dl, VT, Tmp); | ||||||
7039 | return true; | ||||||
7040 | } | ||||||
7041 | |||||||
7042 | bool TargetLowering::expandABS(SDNode *N, SDValue &Result, | ||||||
7043 | SelectionDAG &DAG, bool IsNegative) const { | ||||||
7044 | SDLoc dl(N); | ||||||
7045 | EVT VT = N->getValueType(0); | ||||||
7046 | EVT ShVT = getShiftAmountTy(VT, DAG.getDataLayout()); | ||||||
7047 | SDValue Op = N->getOperand(0); | ||||||
7048 | |||||||
7049 | // abs(x) -> smax(x,sub(0,x)) | ||||||
7050 | if (!IsNegative && isOperationLegal(ISD::SUB, VT) && | ||||||
7051 | isOperationLegal(ISD::SMAX, VT)) { | ||||||
7052 | SDValue Zero = DAG.getConstant(0, dl, VT); | ||||||
7053 | Result = DAG.getNode(ISD::SMAX, dl, VT, Op, | ||||||
7054 | DAG.getNode(ISD::SUB, dl, VT, Zero, Op)); | ||||||
7055 | return true; | ||||||
7056 | } | ||||||
7057 | |||||||
7058 | // abs(x) -> umin(x,sub(0,x)) | ||||||
7059 | if (!IsNegative && isOperationLegal(ISD::SUB, VT) && | ||||||
7060 | isOperationLegal(ISD::UMIN, VT)) { | ||||||
7061 | SDValue Zero = DAG.getConstant(0, dl, VT); | ||||||
7062 | Result = DAG.getNode(ISD::UMIN, dl, VT, Op, | ||||||
7063 | DAG.getNode(ISD::SUB, dl, VT, Zero, Op)); | ||||||
7064 | return true; | ||||||
7065 | } | ||||||
7066 | |||||||
7067 | // 0 - abs(x) -> smin(x, sub(0,x)) | ||||||
7068 | if (IsNegative && isOperationLegal(ISD::SUB, VT) && | ||||||
7069 | isOperationLegal(ISD::SMIN, VT)) { | ||||||
7070 | SDValue Zero = DAG.getConstant(0, dl, VT); | ||||||
7071 | Result = DAG.getNode(ISD::SMIN, dl, VT, Op, | ||||||
7072 | DAG.getNode(ISD::SUB, dl, VT, Zero, Op)); | ||||||
7073 | return true; | ||||||
7074 | } | ||||||
7075 | |||||||
7076 | // Only expand vector types if we have the appropriate vector operations. | ||||||
7077 | if (VT.isVector() && | ||||||
7078 | (!isOperationLegalOrCustom(ISD::SRA, VT) || | ||||||
7079 | (!IsNegative && !isOperationLegalOrCustom(ISD::ADD, VT)) || | ||||||
7080 | (IsNegative && !isOperationLegalOrCustom(ISD::SUB, VT)) || | ||||||
7081 | !isOperationLegalOrCustomOrPromote(ISD::XOR, VT))) | ||||||
7082 | return false; | ||||||
7083 | |||||||
7084 | SDValue Shift = | ||||||
7085 | DAG.getNode(ISD::SRA, dl, VT, Op, | ||||||
7086 | DAG.getConstant(VT.getScalarSizeInBits() - 1, dl, ShVT)); | ||||||
7087 | if (!IsNegative) { | ||||||
7088 | SDValue Add = DAG.getNode(ISD::ADD, dl, VT, Op, Shift); | ||||||
7089 | Result = DAG.getNode(ISD::XOR, dl, VT, Add, Shift); | ||||||
7090 | } else { | ||||||
7091 | // 0 - abs(x) -> Y = sra (X, size(X)-1); sub (Y, xor (X, Y)) | ||||||
7092 | SDValue Xor = DAG.getNode(ISD::XOR, dl, VT, Op, Shift); | ||||||
7093 | Result = DAG.getNode(ISD::SUB, dl, VT, Shift, Xor); | ||||||
7094 | } | ||||||
7095 | return true; | ||||||
7096 | } | ||||||
7097 | |||||||
7098 | SDValue TargetLowering::expandBSWAP(SDNode *N, SelectionDAG &DAG) const { | ||||||
7099 | SDLoc dl(N); | ||||||
7100 | EVT VT = N->getValueType(0); | ||||||
7101 | SDValue Op = N->getOperand(0); | ||||||
7102 | |||||||
7103 | if (!VT.isSimple()) | ||||||
7104 | return SDValue(); | ||||||
7105 | |||||||
7106 | EVT SHVT = getShiftAmountTy(VT, DAG.getDataLayout()); | ||||||
7107 | SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8; | ||||||
7108 | switch (VT.getSimpleVT().getScalarType().SimpleTy) { | ||||||
7109 | default: | ||||||
7110 | return SDValue(); | ||||||
7111 | case MVT::i16: | ||||||
7112 | // Use a rotate by 8. This can be further expanded if necessary. | ||||||
7113 | return DAG.getNode(ISD::ROTL, dl, VT, Op, DAG.getConstant(8, dl, SHVT)); | ||||||
7114 | case MVT::i32: | ||||||
7115 | Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, dl, SHVT)); | ||||||
7116 | Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, dl, SHVT)); | ||||||
7117 | Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, dl, SHVT)); | ||||||
7118 | Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, dl, SHVT)); | ||||||
7119 | Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, | ||||||
7120 | DAG.getConstant(0xFF0000, dl, VT)); | ||||||
7121 | Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, dl, VT)); | ||||||
7122 | Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3); | ||||||
7123 | Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1); | ||||||
7124 | return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2); | ||||||
7125 | case MVT::i64: | ||||||
7126 | Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, dl, SHVT)); | ||||||
7127 | Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, dl, SHVT)); | ||||||
7128 | Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, dl, SHVT)); | ||||||
7129 | Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, dl, SHVT)); | ||||||
7130 | Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, dl, SHVT)); | ||||||
7131 | Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, dl, SHVT)); | ||||||
7132 | Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, dl, SHVT)); | ||||||
7133 | Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, dl, SHVT)); | ||||||
7134 | Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7, | ||||||
7135 | DAG.getConstant(255ULL<<48, dl, VT)); | ||||||
7136 | Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6, | ||||||
7137 | DAG.getConstant(255ULL<<40, dl, VT)); | ||||||
7138 | Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5, | ||||||
7139 | DAG.getConstant(255ULL<<32, dl, VT)); | ||||||
7140 | Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4, | ||||||
7141 | DAG.getConstant(255ULL<<24, dl, VT)); | ||||||
7142 | Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, | ||||||
7143 | DAG.getConstant(255ULL<<16, dl, VT)); | ||||||
7144 | Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, | ||||||
7145 | DAG.getConstant(255ULL<<8 , dl, VT)); | ||||||
7146 | Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7); | ||||||
7147 | Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5); | ||||||
7148 | Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3); | ||||||
7149 | Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1); | ||||||
7150 | Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6); | ||||||
7151 | Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2); | ||||||
7152 | return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4); | ||||||
7153 | } | ||||||
7154 | } | ||||||
7155 | |||||||
7156 | SDValue TargetLowering::expandBITREVERSE(SDNode *N, SelectionDAG &DAG) const { | ||||||
7157 | SDLoc dl(N); | ||||||
7158 | EVT VT = N->getValueType(0); | ||||||
7159 | SDValue Op = N->getOperand(0); | ||||||
7160 | EVT SHVT = getShiftAmountTy(VT, DAG.getDataLayout()); | ||||||
7161 | unsigned Sz = VT.getScalarSizeInBits(); | ||||||
7162 | |||||||
7163 | SDValue Tmp, Tmp2, Tmp3; | ||||||
7164 | |||||||
7165 | // If we can, perform BSWAP first and then the mask+swap the i4, then i2 | ||||||
7166 | // and finally the i1 pairs. | ||||||
7167 | // TODO: We can easily support i4/i2 legal types if any target ever does. | ||||||
7168 | if (Sz >= 8 && isPowerOf2_32(Sz)) { | ||||||
7169 | // Create the masks - repeating the pattern every byte. | ||||||
7170 | APInt MaskHi4 = APInt::getSplat(Sz, APInt(8, 0xF0)); | ||||||
7171 | APInt MaskHi2 = APInt::getSplat(Sz, APInt(8, 0xCC)); | ||||||
7172 | APInt MaskHi1 = APInt::getSplat(Sz, APInt(8, 0xAA)); | ||||||
7173 | APInt MaskLo4 = APInt::getSplat(Sz, APInt(8, 0x0F)); | ||||||
7174 | APInt MaskLo2 = APInt::getSplat(Sz, APInt(8, 0x33)); | ||||||
7175 | APInt MaskLo1 = APInt::getSplat(Sz, APInt(8, 0x55)); | ||||||
7176 | |||||||
7177 | // BSWAP if the type is wider than a single byte. | ||||||
7178 | Tmp = (Sz > 8 ? DAG.getNode(ISD::BSWAP, dl, VT, Op) : Op); | ||||||
7179 | |||||||
7180 | // swap i4: ((V & 0xF0) >> 4) | ((V & 0x0F) << 4) | ||||||
7181 | Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp, DAG.getConstant(MaskHi4, dl, VT)); | ||||||
7182 | Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp, DAG.getConstant(MaskLo4, dl, VT)); | ||||||
7183 | Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Tmp2, DAG.getConstant(4, dl, SHVT)); | ||||||
7184 | Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Tmp3, DAG.getConstant(4, dl, SHVT)); | ||||||
7185 | Tmp = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3); | ||||||
7186 | |||||||
7187 | // swap i2: ((V & 0xCC) >> 2) | ((V & 0x33) << 2) | ||||||
7188 | Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp, DAG.getConstant(MaskHi2, dl, VT)); | ||||||
7189 | Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp, DAG.getConstant(MaskLo2, dl, VT)); | ||||||
7190 | Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Tmp2, DAG.getConstant(2, dl, SHVT)); | ||||||
7191 | Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Tmp3, DAG.getConstant(2, dl, SHVT)); | ||||||
7192 | Tmp = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3); | ||||||
7193 | |||||||
7194 | // swap i1: ((V & 0xAA) >> 1) | ((V & 0x55) << 1) | ||||||
7195 | Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp, DAG.getConstant(MaskHi1, dl, VT)); | ||||||
7196 | Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp, DAG.getConstant(MaskLo1, dl, VT)); | ||||||
7197 | Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Tmp2, DAG.getConstant(1, dl, SHVT)); | ||||||
7198 | Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Tmp3, DAG.getConstant(1, dl, SHVT)); | ||||||
7199 | Tmp = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3); | ||||||
7200 | return Tmp; | ||||||
7201 | } | ||||||
7202 | |||||||
7203 | Tmp = DAG.getConstant(0, dl, VT); | ||||||
7204 | for (unsigned I = 0, J = Sz-1; I < Sz; ++I, --J) { | ||||||
7205 | if (I < J) | ||||||
7206 | Tmp2 = | ||||||
7207 | DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(J - I, dl, SHVT)); | ||||||
7208 | else | ||||||
7209 | Tmp2 = | ||||||
7210 | DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(I - J, dl, SHVT)); | ||||||
7211 | |||||||
7212 | APInt Shift(Sz, 1); | ||||||
7213 | Shift <<= J; | ||||||
7214 | Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(Shift, dl, VT)); | ||||||
7215 | Tmp = DAG.getNode(ISD::OR, dl, VT, Tmp, Tmp2); | ||||||
7216 | } | ||||||
7217 | |||||||
7218 | return Tmp; | ||||||
7219 | } | ||||||
7220 | |||||||
7221 | std::pair<SDValue, SDValue> | ||||||
7222 | TargetLowering::scalarizeVectorLoad(LoadSDNode *LD, | ||||||
7223 | SelectionDAG &DAG) const { | ||||||
7224 | SDLoc SL(LD); | ||||||
7225 | SDValue Chain = LD->getChain(); | ||||||
7226 | SDValue BasePTR = LD->getBasePtr(); | ||||||
7227 | EVT SrcVT = LD->getMemoryVT(); | ||||||
7228 | EVT DstVT = LD->getValueType(0); | ||||||
7229 | ISD::LoadExtType ExtType = LD->getExtensionType(); | ||||||
7230 | |||||||
7231 | if (SrcVT.isScalableVector()) | ||||||
7232 | report_fatal_error("Cannot scalarize scalable vector loads"); | ||||||
7233 | |||||||
7234 | unsigned NumElem = SrcVT.getVectorNumElements(); | ||||||
7235 | |||||||
7236 | EVT SrcEltVT = SrcVT.getScalarType(); | ||||||
7237 | EVT DstEltVT = DstVT.getScalarType(); | ||||||
7238 | |||||||
7239 | // A vector must always be stored in memory as-is, i.e. without any padding | ||||||
7240 | // between the elements, since various code depend on it, e.g. in the | ||||||
7241 | // handling of a bitcast of a vector type to int, which may be done with a | ||||||
7242 | // vector store followed by an integer load. A vector that does not have | ||||||
7243 | // elements that are byte-sized must therefore be stored as an integer | ||||||
7244 | // built out of the extracted vector elements. | ||||||
7245 | if (!SrcEltVT.isByteSized()) { | ||||||
7246 | unsigned NumLoadBits = SrcVT.getStoreSizeInBits(); | ||||||
7247 | EVT LoadVT = EVT::getIntegerVT(*DAG.getContext(), NumLoadBits); | ||||||
7248 | |||||||
7249 | unsigned NumSrcBits = SrcVT.getSizeInBits(); | ||||||
7250 | EVT SrcIntVT = EVT::getIntegerVT(*DAG.getContext(), NumSrcBits); | ||||||
7251 | |||||||
7252 | unsigned SrcEltBits = SrcEltVT.getSizeInBits(); | ||||||
7253 | SDValue SrcEltBitMask = DAG.getConstant( | ||||||
7254 | APInt::getLowBitsSet(NumLoadBits, SrcEltBits), SL, LoadVT); | ||||||
7255 | |||||||
7256 | // Load the whole vector and avoid masking off the top bits as it makes | ||||||
7257 | // the codegen worse. | ||||||
7258 | SDValue Load = | ||||||
7259 | DAG.getExtLoad(ISD::EXTLOAD, SL, LoadVT, Chain, BasePTR, | ||||||
7260 | LD->getPointerInfo(), SrcIntVT, LD->getOriginalAlign(), | ||||||
7261 | LD->getMemOperand()->getFlags(), LD->getAAInfo()); | ||||||
7262 | |||||||
7263 | SmallVector<SDValue, 8> Vals; | ||||||
7264 | for (unsigned Idx = 0; Idx < NumElem; ++Idx) { | ||||||
7265 | unsigned ShiftIntoIdx = | ||||||
7266 | (DAG.getDataLayout().isBigEndian() ? (NumElem - 1) - Idx : Idx); | ||||||
7267 | SDValue ShiftAmount = | ||||||
7268 | DAG.getShiftAmountConstant(ShiftIntoIdx * SrcEltVT.getSizeInBits(), | ||||||
7269 | LoadVT, SL, /*LegalTypes=*/false); | ||||||
7270 | SDValue ShiftedElt = DAG.getNode(ISD::SRL, SL, LoadVT, Load, ShiftAmount); | ||||||
7271 | SDValue Elt = | ||||||
7272 | DAG.getNode(ISD::AND, SL, LoadVT, ShiftedElt, SrcEltBitMask); | ||||||
7273 | SDValue Scalar = DAG.getNode(ISD::TRUNCATE, SL, SrcEltVT, Elt); | ||||||
7274 | |||||||
7275 | if (ExtType != ISD::NON_EXTLOAD) { | ||||||
7276 | unsigned ExtendOp = ISD::getExtForLoadExtType(false, ExtType); | ||||||
7277 | Scalar = DAG.getNode(ExtendOp, SL, DstEltVT, Scalar); | ||||||
7278 | } | ||||||
7279 | |||||||
7280 | Vals.push_back(Scalar); | ||||||
7281 | } | ||||||
7282 | |||||||
7283 | SDValue Value = DAG.getBuildVector(DstVT, SL, Vals); | ||||||
7284 | return std::make_pair(Value, Load.getValue(1)); | ||||||
7285 | } | ||||||
7286 | |||||||
7287 | unsigned Stride = SrcEltVT.getSizeInBits() / 8; | ||||||
7288 | assert(SrcEltVT.isByteSized())((SrcEltVT.isByteSized()) ? static_cast<void> (0) : __assert_fail ("SrcEltVT.isByteSized()", "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 7288, __PRETTY_FUNCTION__)); | ||||||
7289 | |||||||
7290 | SmallVector<SDValue, 8> Vals; | ||||||
7291 | SmallVector<SDValue, 8> LoadChains; | ||||||
7292 | |||||||
7293 | for (unsigned Idx = 0; Idx < NumElem; ++Idx) { | ||||||
7294 | SDValue ScalarLoad = | ||||||
7295 | DAG.getExtLoad(ExtType, SL, DstEltVT, Chain, BasePTR, | ||||||
7296 | LD->getPointerInfo().getWithOffset(Idx * Stride), | ||||||
7297 | SrcEltVT, LD->getOriginalAlign(), | ||||||
7298 | LD->getMemOperand()->getFlags(), LD->getAAInfo()); | ||||||
7299 | |||||||
7300 | BasePTR = DAG.getObjectPtrOffset(SL, BasePTR, TypeSize::Fixed(Stride)); | ||||||
7301 | |||||||
7302 | Vals.push_back(ScalarLoad.getValue(0)); | ||||||
7303 | LoadChains.push_back(ScalarLoad.getValue(1)); | ||||||
7304 | } | ||||||
7305 | |||||||
7306 | SDValue NewChain = DAG.getNode(ISD::TokenFactor, SL, MVT::Other, LoadChains); | ||||||
7307 | SDValue Value = DAG.getBuildVector(DstVT, SL, Vals); | ||||||
7308 | |||||||
7309 | return std::make_pair(Value, NewChain); | ||||||
7310 | } | ||||||
7311 | |||||||
7312 | SDValue TargetLowering::scalarizeVectorStore(StoreSDNode *ST, | ||||||
7313 | SelectionDAG &DAG) const { | ||||||
7314 | SDLoc SL(ST); | ||||||
7315 | |||||||
7316 | SDValue Chain = ST->getChain(); | ||||||
7317 | SDValue BasePtr = ST->getBasePtr(); | ||||||
7318 | SDValue Value = ST->getValue(); | ||||||
7319 | EVT StVT = ST->getMemoryVT(); | ||||||
7320 | |||||||
7321 | if (StVT.isScalableVector()) | ||||||
7322 | report_fatal_error("Cannot scalarize scalable vector stores"); | ||||||
7323 | |||||||
7324 | // The type of the data we want to save | ||||||
7325 | EVT RegVT = Value.getValueType(); | ||||||
7326 | EVT RegSclVT = RegVT.getScalarType(); | ||||||
7327 | |||||||
7328 | // The type of data as saved in memory. | ||||||
7329 | EVT MemSclVT = StVT.getScalarType(); | ||||||
7330 | |||||||
7331 | unsigned NumElem = StVT.getVectorNumElements(); | ||||||
7332 | |||||||
7333 | // A vector must always be stored in memory as-is, i.e. without any padding | ||||||
7334 | // between the elements, since various code depend on it, e.g. in the | ||||||
7335 | // handling of a bitcast of a vector type to int, which may be done with a | ||||||
7336 | // vector store followed by an integer load. A vector that does not have | ||||||
7337 | // elements that are byte-sized must therefore be stored as an integer | ||||||
7338 | // built out of the extracted vector elements. | ||||||
7339 | if (!MemSclVT.isByteSized()) { | ||||||
7340 | unsigned NumBits = StVT.getSizeInBits(); | ||||||
7341 | EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), NumBits); | ||||||
7342 | |||||||
7343 | SDValue CurrVal = DAG.getConstant(0, SL, IntVT); | ||||||
7344 | |||||||
7345 | for (unsigned Idx = 0; Idx < NumElem; ++Idx) { | ||||||
7346 | SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, RegSclVT, Value, | ||||||
7347 | DAG.getVectorIdxConstant(Idx, SL)); | ||||||
7348 | SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SL, MemSclVT, Elt); | ||||||
7349 | SDValue ExtElt = DAG.getNode(ISD::ZERO_EXTEND, SL, IntVT, Trunc); | ||||||
7350 | unsigned ShiftIntoIdx = | ||||||
7351 | (DAG.getDataLayout().isBigEndian() ? (NumElem - 1) - Idx : Idx); | ||||||
7352 | SDValue ShiftAmount = | ||||||
7353 | DAG.getConstant(ShiftIntoIdx * MemSclVT.getSizeInBits(), SL, IntVT); | ||||||
7354 | SDValue ShiftedElt = | ||||||
7355 | DAG.getNode(ISD::SHL, SL, IntVT, ExtElt, ShiftAmount); | ||||||
7356 | CurrVal = DAG.getNode(ISD::OR, SL, IntVT, CurrVal, ShiftedElt); | ||||||
7357 | } | ||||||
7358 | |||||||
7359 | return DAG.getStore(Chain, SL, CurrVal, BasePtr, ST->getPointerInfo(), | ||||||
7360 | ST->getOriginalAlign(), ST->getMemOperand()->getFlags(), | ||||||
7361 | ST->getAAInfo()); | ||||||
7362 | } | ||||||
7363 | |||||||
7364 | // Store Stride in bytes | ||||||
7365 | unsigned Stride = MemSclVT.getSizeInBits() / 8; | ||||||
7366 | assert(Stride && "Zero stride!")((Stride && "Zero stride!") ? static_cast<void> (0) : __assert_fail ("Stride && \"Zero stride!\"", "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 7366, __PRETTY_FUNCTION__)); | ||||||
7367 | // Extract each of the elements from the original vector and save them into | ||||||
7368 | // memory individually. | ||||||
7369 | SmallVector<SDValue, 8> Stores; | ||||||
7370 | for (unsigned Idx = 0; Idx < NumElem; ++Idx) { | ||||||
7371 | SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, RegSclVT, Value, | ||||||
7372 | DAG.getVectorIdxConstant(Idx, SL)); | ||||||
7373 | |||||||
7374 | SDValue Ptr = | ||||||
7375 | DAG.getObjectPtrOffset(SL, BasePtr, TypeSize::Fixed(Idx * Stride)); | ||||||
7376 | |||||||
7377 | // This scalar TruncStore may be illegal, but we legalize it later. | ||||||
7378 | SDValue Store = DAG.getTruncStore( | ||||||
7379 | Chain, SL, Elt, Ptr, ST->getPointerInfo().getWithOffset(Idx * Stride), | ||||||
7380 | MemSclVT, ST->getOriginalAlign(), ST->getMemOperand()->getFlags(), | ||||||
7381 | ST->getAAInfo()); | ||||||
7382 | |||||||
7383 | Stores.push_back(Store); | ||||||
7384 | } | ||||||
7385 | |||||||
7386 | return DAG.getNode(ISD::TokenFactor, SL, MVT::Other, Stores); | ||||||
7387 | } | ||||||
7388 | |||||||
7389 | std::pair<SDValue, SDValue> | ||||||
7390 | TargetLowering::expandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG) const { | ||||||
7391 | assert(LD->getAddressingMode() == ISD::UNINDEXED &&((LD->getAddressingMode() == ISD::UNINDEXED && "unaligned indexed loads not implemented!" ) ? static_cast<void> (0) : __assert_fail ("LD->getAddressingMode() == ISD::UNINDEXED && \"unaligned indexed loads not implemented!\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 7392, __PRETTY_FUNCTION__)) | ||||||
7392 | "unaligned indexed loads not implemented!")((LD->getAddressingMode() == ISD::UNINDEXED && "unaligned indexed loads not implemented!" ) ? static_cast<void> (0) : __assert_fail ("LD->getAddressingMode() == ISD::UNINDEXED && \"unaligned indexed loads not implemented!\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 7392, __PRETTY_FUNCTION__)); | ||||||
7393 | SDValue Chain = LD->getChain(); | ||||||
7394 | SDValue Ptr = LD->getBasePtr(); | ||||||
7395 | EVT VT = LD->getValueType(0); | ||||||
7396 | EVT LoadedVT = LD->getMemoryVT(); | ||||||
7397 | SDLoc dl(LD); | ||||||
7398 | auto &MF = DAG.getMachineFunction(); | ||||||
7399 | |||||||
7400 | if (VT.isFloatingPoint() || VT.isVector()) { | ||||||
7401 | EVT intVT = EVT::getIntegerVT(*DAG.getContext(), LoadedVT.getSizeInBits()); | ||||||
7402 | if (isTypeLegal(intVT) && isTypeLegal(LoadedVT)) { | ||||||
7403 | if (!isOperationLegalOrCustom(ISD::LOAD, intVT) && | ||||||
7404 | LoadedVT.isVector()) { | ||||||
7405 | // Scalarize the load and let the individual components be handled. | ||||||
7406 | return scalarizeVectorLoad(LD, DAG); | ||||||
7407 | } | ||||||
7408 | |||||||
7409 | // Expand to a (misaligned) integer load of the same size, | ||||||
7410 | // then bitconvert to floating point or vector. | ||||||
7411 | SDValue newLoad = DAG.getLoad(intVT, dl, Chain, Ptr, | ||||||
7412 | LD->getMemOperand()); | ||||||
7413 | SDValue Result = DAG.getNode(ISD::BITCAST, dl, LoadedVT, newLoad); | ||||||
7414 | if (LoadedVT != VT) | ||||||
7415 | Result = DAG.getNode(VT.isFloatingPoint() ? ISD::FP_EXTEND : | ||||||
7416 | ISD::ANY_EXTEND, dl, VT, Result); | ||||||
7417 | |||||||
7418 | return std::make_pair(Result, newLoad.getValue(1)); | ||||||
7419 | } | ||||||
7420 | |||||||
7421 | // Copy the value to a (aligned) stack slot using (unaligned) integer | ||||||
7422 | // loads and stores, then do a (aligned) load from the stack slot. | ||||||
7423 | MVT RegVT = getRegisterType(*DAG.getContext(), intVT); | ||||||
7424 | unsigned LoadedBytes = LoadedVT.getStoreSize(); | ||||||
7425 | unsigned RegBytes = RegVT.getSizeInBits() / 8; | ||||||
7426 | unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes; | ||||||
7427 | |||||||
7428 | // Make sure the stack slot is also aligned for the register type. | ||||||
7429 | SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT); | ||||||
7430 | auto FrameIndex = cast<FrameIndexSDNode>(StackBase.getNode())->getIndex(); | ||||||
7431 | SmallVector<SDValue, 8> Stores; | ||||||
7432 | SDValue StackPtr = StackBase; | ||||||
7433 | unsigned Offset = 0; | ||||||
7434 | |||||||
7435 | EVT PtrVT = Ptr.getValueType(); | ||||||
7436 | EVT StackPtrVT = StackPtr.getValueType(); | ||||||
7437 | |||||||
7438 | SDValue PtrIncrement = DAG.getConstant(RegBytes, dl, PtrVT); | ||||||
7439 | SDValue StackPtrIncrement = DAG.getConstant(RegBytes, dl, StackPtrVT); | ||||||
7440 | |||||||
7441 | // Do all but one copies using the full register width. | ||||||
7442 | for (unsigned i = 1; i < NumRegs; i++) { | ||||||
7443 | // Load one integer register's worth from the original location. | ||||||
7444 | SDValue Load = DAG.getLoad( | ||||||
7445 | RegVT, dl, Chain, Ptr, LD->getPointerInfo().getWithOffset(Offset), | ||||||
7446 | LD->getOriginalAlign(), LD->getMemOperand()->getFlags(), | ||||||
7447 | LD->getAAInfo()); | ||||||
7448 | // Follow the load with a store to the stack slot. Remember the store. | ||||||
7449 | Stores.push_back(DAG.getStore( | ||||||
7450 | Load.getValue(1), dl, Load, StackPtr, | ||||||
7451 | MachinePointerInfo::getFixedStack(MF, FrameIndex, Offset))); | ||||||
7452 | // Increment the pointers. | ||||||
7453 | Offset += RegBytes; | ||||||
7454 | |||||||
7455 | Ptr = DAG.getObjectPtrOffset(dl, Ptr, PtrIncrement); | ||||||
7456 | StackPtr = DAG.getObjectPtrOffset(dl, StackPtr, StackPtrIncrement); | ||||||
7457 | } | ||||||
7458 | |||||||
7459 | // The last copy may be partial. Do an extending load. | ||||||
7460 | EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), | ||||||
7461 | 8 * (LoadedBytes - Offset)); | ||||||
7462 | SDValue Load = | ||||||
7463 | DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr, | ||||||
7464 | LD->getPointerInfo().getWithOffset(Offset), MemVT, | ||||||
7465 | LD->getOriginalAlign(), LD->getMemOperand()->getFlags(), | ||||||
7466 | LD->getAAInfo()); | ||||||
7467 | // Follow the load with a store to the stack slot. Remember the store. | ||||||
7468 | // On big-endian machines this requires a truncating store to ensure | ||||||
7469 | // that the bits end up in the right place. | ||||||
7470 | Stores.push_back(DAG.getTruncStore( | ||||||
7471 | Load.getValue(1), dl, Load, StackPtr, | ||||||
7472 | MachinePointerInfo::getFixedStack(MF, FrameIndex, Offset), MemVT)); | ||||||
7473 | |||||||
7474 | // The order of the stores doesn't matter - say it with a TokenFactor. | ||||||
7475 | SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores); | ||||||
7476 | |||||||
7477 | // Finally, perform the original load only redirected to the stack slot. | ||||||
7478 | Load = DAG.getExtLoad(LD->getExtensionType(), dl, VT, TF, StackBase, | ||||||
7479 | MachinePointerInfo::getFixedStack(MF, FrameIndex, 0), | ||||||
7480 | LoadedVT); | ||||||
7481 | |||||||
7482 | // Callers expect a MERGE_VALUES node. | ||||||
7483 | return std::make_pair(Load, TF); | ||||||
7484 | } | ||||||
7485 | |||||||
7486 | assert(LoadedVT.isInteger() && !LoadedVT.isVector() &&((LoadedVT.isInteger() && !LoadedVT.isVector() && "Unaligned load of unsupported type.") ? static_cast<void > (0) : __assert_fail ("LoadedVT.isInteger() && !LoadedVT.isVector() && \"Unaligned load of unsupported type.\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 7487, __PRETTY_FUNCTION__)) | ||||||
7487 | "Unaligned load of unsupported type.")((LoadedVT.isInteger() && !LoadedVT.isVector() && "Unaligned load of unsupported type.") ? static_cast<void > (0) : __assert_fail ("LoadedVT.isInteger() && !LoadedVT.isVector() && \"Unaligned load of unsupported type.\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 7487, __PRETTY_FUNCTION__)); | ||||||
7488 | |||||||
7489 | // Compute the new VT that is half the size of the old one. This is an | ||||||
7490 | // integer MVT. | ||||||
7491 | unsigned NumBits = LoadedVT.getSizeInBits(); | ||||||
7492 | EVT NewLoadedVT; | ||||||
7493 | NewLoadedVT = EVT::getIntegerVT(*DAG.getContext(), NumBits/2); | ||||||
7494 | NumBits >>= 1; | ||||||
7495 | |||||||
7496 | Align Alignment = LD->getOriginalAlign(); | ||||||
7497 | unsigned IncrementSize = NumBits / 8; | ||||||
7498 | ISD::LoadExtType HiExtType = LD->getExtensionType(); | ||||||
7499 | |||||||
7500 | // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD. | ||||||
7501 | if (HiExtType == ISD::NON_EXTLOAD) | ||||||
7502 | HiExtType = ISD::ZEXTLOAD; | ||||||
7503 | |||||||
7504 | // Load the value in two parts | ||||||
7505 | SDValue Lo, Hi; | ||||||
7506 | if (DAG.getDataLayout().isLittleEndian()) { | ||||||
7507 | Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getPointerInfo(), | ||||||
7508 | NewLoadedVT, Alignment, LD->getMemOperand()->getFlags(), | ||||||
7509 | LD->getAAInfo()); | ||||||
7510 | |||||||
7511 | Ptr = DAG.getObjectPtrOffset(dl, Ptr, TypeSize::Fixed(IncrementSize)); | ||||||
7512 | Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, | ||||||
7513 | LD->getPointerInfo().getWithOffset(IncrementSize), | ||||||
7514 | NewLoadedVT, Alignment, LD->getMemOperand()->getFlags(), | ||||||
7515 | LD->getAAInfo()); | ||||||
7516 | } else { | ||||||
7517 | Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getPointerInfo(), | ||||||
7518 | NewLoadedVT, Alignment, LD->getMemOperand()->getFlags(), | ||||||
7519 | LD->getAAInfo()); | ||||||
7520 | |||||||
7521 | Ptr = DAG.getObjectPtrOffset(dl, Ptr, TypeSize::Fixed(IncrementSize)); | ||||||
7522 | Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, | ||||||
7523 | LD->getPointerInfo().getWithOffset(IncrementSize), | ||||||
7524 | NewLoadedVT, Alignment, LD->getMemOperand()->getFlags(), | ||||||
7525 | LD->getAAInfo()); | ||||||
7526 | } | ||||||
7527 | |||||||
7528 | // aggregate the two parts | ||||||
7529 | SDValue ShiftAmount = | ||||||
7530 | DAG.getConstant(NumBits, dl, getShiftAmountTy(Hi.getValueType(), | ||||||
7531 | DAG.getDataLayout())); | ||||||
7532 | SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount); | ||||||
7533 | Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo); | ||||||
7534 | |||||||
7535 | SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), | ||||||
7536 | Hi.getValue(1)); | ||||||
7537 | |||||||
7538 | return std::make_pair(Result, TF); | ||||||
7539 | } | ||||||
7540 | |||||||
7541 | SDValue TargetLowering::expandUnalignedStore(StoreSDNode *ST, | ||||||
7542 | SelectionDAG &DAG) const { | ||||||
7543 | assert(ST->getAddressingMode() == ISD::UNINDEXED &&((ST->getAddressingMode() == ISD::UNINDEXED && "unaligned indexed stores not implemented!" ) ? static_cast<void> (0) : __assert_fail ("ST->getAddressingMode() == ISD::UNINDEXED && \"unaligned indexed stores not implemented!\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 7544, __PRETTY_FUNCTION__)) | ||||||
7544 | "unaligned indexed stores not implemented!")((ST->getAddressingMode() == ISD::UNINDEXED && "unaligned indexed stores not implemented!" ) ? static_cast<void> (0) : __assert_fail ("ST->getAddressingMode() == ISD::UNINDEXED && \"unaligned indexed stores not implemented!\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 7544, __PRETTY_FUNCTION__)); | ||||||
7545 | SDValue Chain = ST->getChain(); | ||||||
7546 | SDValue Ptr = ST->getBasePtr(); | ||||||
7547 | SDValue Val = ST->getValue(); | ||||||
7548 | EVT VT = Val.getValueType(); | ||||||
7549 | Align Alignment = ST->getOriginalAlign(); | ||||||
7550 | auto &MF = DAG.getMachineFunction(); | ||||||
7551 | EVT StoreMemVT = ST->getMemoryVT(); | ||||||
7552 | |||||||
7553 | SDLoc dl(ST); | ||||||
7554 | if (StoreMemVT.isFloatingPoint() || StoreMemVT.isVector()) { | ||||||
7555 | EVT intVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits()); | ||||||
7556 | if (isTypeLegal(intVT)) { | ||||||
7557 | if (!isOperationLegalOrCustom(ISD::STORE, intVT) && | ||||||
7558 | StoreMemVT.isVector()) { | ||||||
7559 | // Scalarize the store and let the individual components be handled. | ||||||
7560 | SDValue Result = scalarizeVectorStore(ST, DAG); | ||||||
7561 | return Result; | ||||||
7562 | } | ||||||
7563 | // Expand to a bitconvert of the value to the integer type of the | ||||||
7564 | // same size, then a (misaligned) int store. | ||||||
7565 | // FIXME: Does not handle truncating floating point stores! | ||||||
7566 | SDValue Result = DAG.getNode(ISD::BITCAST, dl, intVT, Val); | ||||||
7567 | Result = DAG.getStore(Chain, dl, Result, Ptr, ST->getPointerInfo(), | ||||||
7568 | Alignment, ST->getMemOperand()->getFlags()); | ||||||
7569 | return Result; | ||||||
7570 | } | ||||||
7571 | // Do a (aligned) store to a stack slot, then copy from the stack slot | ||||||
7572 | // to the final destination using (unaligned) integer loads and stores. | ||||||
7573 | MVT RegVT = getRegisterType( | ||||||
7574 | *DAG.getContext(), | ||||||
7575 | EVT::getIntegerVT(*DAG.getContext(), StoreMemVT.getSizeInBits())); | ||||||
7576 | EVT PtrVT = Ptr.getValueType(); | ||||||
7577 | unsigned StoredBytes = StoreMemVT.getStoreSize(); | ||||||
7578 | unsigned RegBytes = RegVT.getSizeInBits() / 8; | ||||||
7579 | unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes; | ||||||
7580 | |||||||
7581 | // Make sure the stack slot is also aligned for the register type. | ||||||
7582 | SDValue StackPtr = DAG.CreateStackTemporary(StoreMemVT, RegVT); | ||||||
7583 | auto FrameIndex = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex(); | ||||||
7584 | |||||||
7585 | // Perform the original store, only redirected to the stack slot. | ||||||
7586 | SDValue Store = DAG.getTruncStore( | ||||||
7587 | Chain, dl, Val, StackPtr, | ||||||
7588 | MachinePointerInfo::getFixedStack(MF, FrameIndex, 0), StoreMemVT); | ||||||
7589 | |||||||
7590 | EVT StackPtrVT = StackPtr.getValueType(); | ||||||
7591 | |||||||
7592 | SDValue PtrIncrement = DAG.getConstant(RegBytes, dl, PtrVT); | ||||||
7593 | SDValue StackPtrIncrement = DAG.getConstant(RegBytes, dl, StackPtrVT); | ||||||
7594 | SmallVector<SDValue, 8> Stores; | ||||||
7595 | unsigned Offset = 0; | ||||||
7596 | |||||||
7597 | // Do all but one copies using the full register width. | ||||||
7598 | for (unsigned i = 1; i < NumRegs; i++) { | ||||||
7599 | // Load one integer register's worth from the stack slot. | ||||||
7600 | SDValue Load = DAG.getLoad( | ||||||
7601 | RegVT, dl, Store, StackPtr, | ||||||
7602 | MachinePointerInfo::getFixedStack(MF, FrameIndex, Offset)); | ||||||
7603 | // Store it to the final location. Remember the store. | ||||||
7604 | Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr, | ||||||
7605 | ST->getPointerInfo().getWithOffset(Offset), | ||||||
7606 | ST->getOriginalAlign(), | ||||||
7607 | ST->getMemOperand()->getFlags())); | ||||||
7608 | // Increment the pointers. | ||||||
7609 | Offset += RegBytes; | ||||||
7610 | StackPtr = DAG.getObjectPtrOffset(dl, StackPtr, StackPtrIncrement); | ||||||
7611 | Ptr = DAG.getObjectPtrOffset(dl, Ptr, PtrIncrement); | ||||||
7612 | } | ||||||
7613 | |||||||
7614 | // The last store may be partial. Do a truncating store. On big-endian | ||||||
7615 | // machines this requires an extending load from the stack slot to ensure | ||||||
7616 | // that the bits are in the right place. | ||||||
7617 | EVT LoadMemVT = | ||||||
7618 | EVT::getIntegerVT(*DAG.getContext(), 8 * (StoredBytes - Offset)); | ||||||
7619 | |||||||
7620 | // Load from the stack slot. | ||||||
7621 | SDValue Load = DAG.getExtLoad( | ||||||
7622 | ISD::EXTLOAD, dl, RegVT, Store, StackPtr, | ||||||
7623 | MachinePointerInfo::getFixedStack(MF, FrameIndex, Offset), LoadMemVT); | ||||||
7624 | |||||||
7625 | Stores.push_back( | ||||||
7626 | DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr, | ||||||
7627 | ST->getPointerInfo().getWithOffset(Offset), LoadMemVT, | ||||||
7628 | ST->getOriginalAlign(), | ||||||
7629 | ST->getMemOperand()->getFlags(), ST->getAAInfo())); | ||||||
7630 | // The order of the stores doesn't matter - say it with a TokenFactor. | ||||||
7631 | SDValue Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores); | ||||||
7632 | return Result; | ||||||
7633 | } | ||||||
7634 | |||||||
7635 | assert(StoreMemVT.isInteger() && !StoreMemVT.isVector() &&((StoreMemVT.isInteger() && !StoreMemVT.isVector() && "Unaligned store of unknown type.") ? static_cast<void> (0) : __assert_fail ("StoreMemVT.isInteger() && !StoreMemVT.isVector() && \"Unaligned store of unknown type.\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 7636, __PRETTY_FUNCTION__)) | ||||||
7636 | "Unaligned store of unknown type.")((StoreMemVT.isInteger() && !StoreMemVT.isVector() && "Unaligned store of unknown type.") ? static_cast<void> (0) : __assert_fail ("StoreMemVT.isInteger() && !StoreMemVT.isVector() && \"Unaligned store of unknown type.\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 7636, __PRETTY_FUNCTION__)); | ||||||
7637 | // Get the half-size VT | ||||||
7638 | EVT NewStoredVT = StoreMemVT.getHalfSizedIntegerVT(*DAG.getContext()); | ||||||
7639 | unsigned NumBits = NewStoredVT.getFixedSizeInBits(); | ||||||
7640 | unsigned IncrementSize = NumBits / 8; | ||||||
7641 | |||||||
7642 | // Divide the stored value in two parts. | ||||||
7643 | SDValue ShiftAmount = DAG.getConstant( | ||||||
7644 | NumBits, dl, getShiftAmountTy(Val.getValueType(), DAG.getDataLayout())); | ||||||
7645 | SDValue Lo = Val; | ||||||
7646 | SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount); | ||||||
7647 | |||||||
7648 | // Store the two parts | ||||||
7649 | SDValue Store1, Store2; | ||||||
7650 | Store1 = DAG.getTruncStore(Chain, dl, | ||||||
7651 | DAG.getDataLayout().isLittleEndian() ? Lo : Hi, | ||||||
7652 | Ptr, ST->getPointerInfo(), NewStoredVT, Alignment, | ||||||
7653 | ST->getMemOperand()->getFlags()); | ||||||
7654 | |||||||
7655 | Ptr = DAG.getObjectPtrOffset(dl, Ptr, TypeSize::Fixed(IncrementSize)); | ||||||
7656 | Store2 = DAG.getTruncStore( | ||||||
7657 | Chain, dl, DAG.getDataLayout().isLittleEndian() ? Hi : Lo, Ptr, | ||||||
7658 | ST->getPointerInfo().getWithOffset(IncrementSize), NewStoredVT, Alignment, | ||||||
7659 | ST->getMemOperand()->getFlags(), ST->getAAInfo()); | ||||||
7660 | |||||||
7661 | SDValue Result = | ||||||
7662 | DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2); | ||||||
7663 | return Result; | ||||||
7664 | } | ||||||
7665 | |||||||
7666 | SDValue | ||||||
7667 | TargetLowering::IncrementMemoryAddress(SDValue Addr, SDValue Mask, | ||||||
7668 | const SDLoc &DL, EVT DataVT, | ||||||
7669 | SelectionDAG &DAG, | ||||||
7670 | bool IsCompressedMemory) const { | ||||||
7671 | SDValue Increment; | ||||||
7672 | EVT AddrVT = Addr.getValueType(); | ||||||
7673 | EVT MaskVT = Mask.getValueType(); | ||||||
7674 | assert(DataVT.getVectorElementCount() == MaskVT.getVectorElementCount() &&((DataVT.getVectorElementCount() == MaskVT.getVectorElementCount () && "Incompatible types of Data and Mask") ? static_cast <void> (0) : __assert_fail ("DataVT.getVectorElementCount() == MaskVT.getVectorElementCount() && \"Incompatible types of Data and Mask\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 7675, __PRETTY_FUNCTION__)) | ||||||
7675 | "Incompatible types of Data and Mask")((DataVT.getVectorElementCount() == MaskVT.getVectorElementCount () && "Incompatible types of Data and Mask") ? static_cast <void> (0) : __assert_fail ("DataVT.getVectorElementCount() == MaskVT.getVectorElementCount() && \"Incompatible types of Data and Mask\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 7675, __PRETTY_FUNCTION__)); | ||||||
7676 | if (IsCompressedMemory) { | ||||||
7677 | if (DataVT.isScalableVector()) | ||||||
7678 | report_fatal_error( | ||||||
7679 | "Cannot currently handle compressed memory with scalable vectors"); | ||||||
7680 | // Incrementing the pointer according to number of '1's in the mask. | ||||||
7681 | EVT MaskIntVT = EVT::getIntegerVT(*DAG.getContext(), MaskVT.getSizeInBits()); | ||||||
7682 | SDValue MaskInIntReg = DAG.getBitcast(MaskIntVT, Mask); | ||||||
7683 | if (MaskIntVT.getSizeInBits() < 32) { | ||||||
7684 | MaskInIntReg = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, MaskInIntReg); | ||||||
7685 | MaskIntVT = MVT::i32; | ||||||
7686 | } | ||||||
7687 | |||||||
7688 | // Count '1's with POPCNT. | ||||||
7689 | Increment = DAG.getNode(ISD::CTPOP, DL, MaskIntVT, MaskInIntReg); | ||||||
7690 | Increment = DAG.getZExtOrTrunc(Increment, DL, AddrVT); | ||||||
7691 | // Scale is an element size in bytes. | ||||||
7692 | SDValue Scale = DAG.getConstant(DataVT.getScalarSizeInBits() / 8, DL, | ||||||
7693 | AddrVT); | ||||||
7694 | Increment = DAG.getNode(ISD::MUL, DL, AddrVT, Increment, Scale); | ||||||
7695 | } else if (DataVT.isScalableVector()) { | ||||||
7696 | Increment = DAG.getVScale(DL, AddrVT, | ||||||
7697 | APInt(AddrVT.getFixedSizeInBits(), | ||||||
7698 | DataVT.getStoreSize().getKnownMinSize())); | ||||||
7699 | } else | ||||||
7700 | Increment = DAG.getConstant(DataVT.getStoreSize(), DL, AddrVT); | ||||||
7701 | |||||||
7702 | return DAG.getNode(ISD::ADD, DL, AddrVT, Addr, Increment); | ||||||
7703 | } | ||||||
7704 | |||||||
7705 | static SDValue clampDynamicVectorIndex(SelectionDAG &DAG, | ||||||
7706 | SDValue Idx, | ||||||
7707 | EVT VecVT, | ||||||
7708 | const SDLoc &dl) { | ||||||
7709 | if (!VecVT.isScalableVector() && isa<ConstantSDNode>(Idx)) | ||||||
7710 | return Idx; | ||||||
7711 | |||||||
7712 | EVT IdxVT = Idx.getValueType(); | ||||||
7713 | unsigned NElts = VecVT.getVectorMinNumElements(); | ||||||
7714 | if (VecVT.isScalableVector()) { | ||||||
7715 | SDValue VS = DAG.getVScale(dl, IdxVT, | ||||||
7716 | APInt(IdxVT.getFixedSizeInBits(), | ||||||
7717 | NElts)); | ||||||
7718 | SDValue Sub = DAG.getNode(ISD::SUB, dl, IdxVT, VS, | ||||||
7719 | DAG.getConstant(1, dl, IdxVT)); | ||||||
7720 | |||||||
7721 | return DAG.getNode(ISD::UMIN, dl, IdxVT, Idx, Sub); | ||||||
7722 | } else { | ||||||
7723 | if (isPowerOf2_32(NElts)) { | ||||||
7724 | APInt Imm = APInt::getLowBitsSet(IdxVT.getSizeInBits(), | ||||||
7725 | Log2_32(NElts)); | ||||||
7726 | return DAG.getNode(ISD::AND, dl, IdxVT, Idx, | ||||||
7727 | DAG.getConstant(Imm, dl, IdxVT)); | ||||||
7728 | } | ||||||
7729 | } | ||||||
7730 | |||||||
7731 | return DAG.getNode(ISD::UMIN, dl, IdxVT, Idx, | ||||||
7732 | DAG.getConstant(NElts - 1, dl, IdxVT)); | ||||||
7733 | } | ||||||
7734 | |||||||
7735 | SDValue TargetLowering::getVectorElementPointer(SelectionDAG &DAG, | ||||||
7736 | SDValue VecPtr, EVT VecVT, | ||||||
7737 | SDValue Index) const { | ||||||
7738 | SDLoc dl(Index); | ||||||
7739 | // Make sure the index type is big enough to compute in. | ||||||
7740 | Index = DAG.getZExtOrTrunc(Index, dl, VecPtr.getValueType()); | ||||||
7741 | |||||||
7742 | EVT EltVT = VecVT.getVectorElementType(); | ||||||
7743 | |||||||
7744 | // Calculate the element offset and add it to the pointer. | ||||||
7745 | unsigned EltSize = EltVT.getFixedSizeInBits() / 8; // FIXME: should be ABI size. | ||||||
7746 | assert(EltSize * 8 == EltVT.getFixedSizeInBits() &&((EltSize * 8 == EltVT.getFixedSizeInBits() && "Converting bits to bytes lost precision" ) ? static_cast<void> (0) : __assert_fail ("EltSize * 8 == EltVT.getFixedSizeInBits() && \"Converting bits to bytes lost precision\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 7747, __PRETTY_FUNCTION__)) | ||||||
7747 | "Converting bits to bytes lost precision")((EltSize * 8 == EltVT.getFixedSizeInBits() && "Converting bits to bytes lost precision" ) ? static_cast<void> (0) : __assert_fail ("EltSize * 8 == EltVT.getFixedSizeInBits() && \"Converting bits to bytes lost precision\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 7747, __PRETTY_FUNCTION__)); | ||||||
7748 | |||||||
7749 | Index = clampDynamicVectorIndex(DAG, Index, VecVT, dl); | ||||||
7750 | |||||||
7751 | EVT IdxVT = Index.getValueType(); | ||||||
7752 | |||||||
7753 | Index = DAG.getNode(ISD::MUL, dl, IdxVT, Index, | ||||||
7754 | DAG.getConstant(EltSize, dl, IdxVT)); | ||||||
7755 | return DAG.getMemBasePlusOffset(VecPtr, Index, dl); | ||||||
7756 | } | ||||||
7757 | |||||||
7758 | //===----------------------------------------------------------------------===// | ||||||
7759 | // Implementation of Emulated TLS Model | ||||||
7760 | //===----------------------------------------------------------------------===// | ||||||
7761 | |||||||
7762 | SDValue TargetLowering::LowerToTLSEmulatedModel(const GlobalAddressSDNode *GA, | ||||||
7763 | SelectionDAG &DAG) const { | ||||||
7764 | // Access to address of TLS varialbe xyz is lowered to a function call: | ||||||
7765 | // __emutls_get_address( address of global variable named "__emutls_v.xyz" ) | ||||||
7766 | EVT PtrVT = getPointerTy(DAG.getDataLayout()); | ||||||
7767 | PointerType *VoidPtrType = Type::getInt8PtrTy(*DAG.getContext()); | ||||||
7768 | SDLoc dl(GA); | ||||||
7769 | |||||||
7770 | ArgListTy Args; | ||||||
7771 | ArgListEntry Entry; | ||||||
7772 | std::string NameString = ("__emutls_v." + GA->getGlobal()->getName()).str(); | ||||||
7773 | Module *VariableModule = const_cast<Module*>(GA->getGlobal()->getParent()); | ||||||
7774 | StringRef EmuTlsVarName(NameString); | ||||||
7775 | GlobalVariable *EmuTlsVar = VariableModule->getNamedGlobal(EmuTlsVarName); | ||||||
7776 | assert(EmuTlsVar && "Cannot find EmuTlsVar ")((EmuTlsVar && "Cannot find EmuTlsVar ") ? static_cast <void> (0) : __assert_fail ("EmuTlsVar && \"Cannot find EmuTlsVar \"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 7776, __PRETTY_FUNCTION__)); | ||||||
7777 | Entry.Node = DAG.getGlobalAddress(EmuTlsVar, dl, PtrVT); | ||||||
7778 | Entry.Ty = VoidPtrType; | ||||||
7779 | Args.push_back(Entry); | ||||||
7780 | |||||||
7781 | SDValue EmuTlsGetAddr = DAG.getExternalSymbol("__emutls_get_address", PtrVT); | ||||||
7782 | |||||||
7783 | TargetLowering::CallLoweringInfo CLI(DAG); | ||||||
7784 | CLI.setDebugLoc(dl).setChain(DAG.getEntryNode()); | ||||||
7785 | CLI.setLibCallee(CallingConv::C, VoidPtrType, EmuTlsGetAddr, std::move(Args)); | ||||||
7786 | std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI); | ||||||
7787 | |||||||
7788 | // TLSADDR will be codegen'ed as call. Inform MFI that function has calls. | ||||||
7789 | // At last for X86 targets, maybe good for other targets too? | ||||||
7790 | MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo(); | ||||||
7791 | MFI.setAdjustsStack(true); // Is this only for X86 target? | ||||||
7792 | MFI.setHasCalls(true); | ||||||
7793 | |||||||
7794 | assert((GA->getOffset() == 0) &&(((GA->getOffset() == 0) && "Emulated TLS must have zero offset in GlobalAddressSDNode" ) ? static_cast<void> (0) : __assert_fail ("(GA->getOffset() == 0) && \"Emulated TLS must have zero offset in GlobalAddressSDNode\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 7795, __PRETTY_FUNCTION__)) | ||||||
7795 | "Emulated TLS must have zero offset in GlobalAddressSDNode")(((GA->getOffset() == 0) && "Emulated TLS must have zero offset in GlobalAddressSDNode" ) ? static_cast<void> (0) : __assert_fail ("(GA->getOffset() == 0) && \"Emulated TLS must have zero offset in GlobalAddressSDNode\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 7795, __PRETTY_FUNCTION__)); | ||||||
7796 | return CallResult.first; | ||||||
7797 | } | ||||||
7798 | |||||||
7799 | SDValue TargetLowering::lowerCmpEqZeroToCtlzSrl(SDValue Op, | ||||||
7800 | SelectionDAG &DAG) const { | ||||||
7801 | assert((Op->getOpcode() == ISD::SETCC) && "Input has to be a SETCC node.")(((Op->getOpcode() == ISD::SETCC) && "Input has to be a SETCC node." ) ? static_cast<void> (0) : __assert_fail ("(Op->getOpcode() == ISD::SETCC) && \"Input has to be a SETCC node.\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 7801, __PRETTY_FUNCTION__)); | ||||||
7802 | if (!isCtlzFast()) | ||||||
7803 | return SDValue(); | ||||||
7804 | ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); | ||||||
7805 | SDLoc dl(Op); | ||||||
7806 | if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { | ||||||
7807 | if (C->isNullValue() && CC == ISD::SETEQ) { | ||||||
7808 | EVT VT = Op.getOperand(0).getValueType(); | ||||||
7809 | SDValue Zext = Op.getOperand(0); | ||||||
7810 | if (VT.bitsLT(MVT::i32)) { | ||||||
7811 | VT = MVT::i32; | ||||||
7812 | Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0)); | ||||||
7813 | } | ||||||
7814 | unsigned Log2b = Log2_32(VT.getSizeInBits()); | ||||||
7815 | SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext); | ||||||
7816 | SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz, | ||||||
7817 | DAG.getConstant(Log2b, dl, MVT::i32)); | ||||||
7818 | return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc); | ||||||
7819 | } | ||||||
7820 | } | ||||||
7821 | return SDValue(); | ||||||
7822 | } | ||||||
7823 | |||||||
7824 | // Convert redundant addressing modes (e.g. scaling is redundant | ||||||
7825 | // when accessing bytes). | ||||||
7826 | ISD::MemIndexType | ||||||
7827 | TargetLowering::getCanonicalIndexType(ISD::MemIndexType IndexType, EVT MemVT, | ||||||
7828 | SDValue Offsets) const { | ||||||
7829 | bool IsScaledIndex = | ||||||
7830 | (IndexType == ISD::SIGNED_SCALED) || (IndexType == ISD::UNSIGNED_SCALED); | ||||||
7831 | bool IsSignedIndex = | ||||||
7832 | (IndexType == ISD::SIGNED_SCALED) || (IndexType == ISD::SIGNED_UNSCALED); | ||||||
7833 | |||||||
7834 | // Scaling is unimportant for bytes, canonicalize to unscaled. | ||||||
7835 | if (IsScaledIndex && MemVT.getScalarType() == MVT::i8) { | ||||||
7836 | IsScaledIndex = false; | ||||||
7837 | IndexType = IsSignedIndex ? ISD::SIGNED_UNSCALED : ISD::UNSIGNED_UNSCALED; | ||||||
7838 | } | ||||||
7839 | |||||||
7840 | return IndexType; | ||||||
7841 | } | ||||||
7842 | |||||||
7843 | SDValue TargetLowering::expandIntMINMAX(SDNode *Node, SelectionDAG &DAG) const { | ||||||
7844 | SDValue Op0 = Node->getOperand(0); | ||||||
7845 | SDValue Op1 = Node->getOperand(1); | ||||||
7846 | EVT VT = Op0.getValueType(); | ||||||
7847 | unsigned Opcode = Node->getOpcode(); | ||||||
7848 | SDLoc DL(Node); | ||||||
7849 | |||||||
7850 | // umin(x,y) -> sub(x,usubsat(x,y)) | ||||||
7851 | if (Opcode == ISD::UMIN && isOperationLegal(ISD::SUB, VT) && | ||||||
7852 | isOperationLegal(ISD::USUBSAT, VT)) { | ||||||
7853 | return DAG.getNode(ISD::SUB, DL, VT, Op0, | ||||||
7854 | DAG.getNode(ISD::USUBSAT, DL, VT, Op0, Op1)); | ||||||
7855 | } | ||||||
7856 | |||||||
7857 | // umax(x,y) -> add(x,usubsat(y,x)) | ||||||
7858 | if (Opcode == ISD::UMAX && isOperationLegal(ISD::ADD, VT) && | ||||||
7859 | isOperationLegal(ISD::USUBSAT, VT)) { | ||||||
7860 | return DAG.getNode(ISD::ADD, DL, VT, Op0, | ||||||
7861 | DAG.getNode(ISD::USUBSAT, DL, VT, Op1, Op0)); | ||||||
7862 | } | ||||||
7863 | |||||||
7864 | // Expand Y = MAX(A, B) -> Y = (A > B) ? A : B | ||||||
7865 | ISD::CondCode CC; | ||||||
7866 | switch (Opcode) { | ||||||
7867 | default: llvm_unreachable("How did we get here?")::llvm::llvm_unreachable_internal("How did we get here?", "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 7867); | ||||||
7868 | case ISD::SMAX: CC = ISD::SETGT; break; | ||||||
7869 | case ISD::SMIN: CC = ISD::SETLT; break; | ||||||
7870 | case ISD::UMAX: CC = ISD::SETUGT; break; | ||||||
7871 | case ISD::UMIN: CC = ISD::SETULT; break; | ||||||
7872 | } | ||||||
7873 | |||||||
7874 | // FIXME: Should really try to split the vector in case it's legal on a | ||||||
7875 | // subvector. | ||||||
7876 | if (VT.isVector() && !isOperationLegalOrCustom(ISD::VSELECT, VT)) | ||||||
7877 | return DAG.UnrollVectorOp(Node); | ||||||
7878 | |||||||
7879 | SDValue Cond = DAG.getSetCC(DL, VT, Op0, Op1, CC); | ||||||
7880 | return DAG.getSelect(DL, VT, Cond, Op0, Op1); | ||||||
7881 | } | ||||||
7882 | |||||||
7883 | SDValue TargetLowering::expandAddSubSat(SDNode *Node, SelectionDAG &DAG) const { | ||||||
7884 | unsigned Opcode = Node->getOpcode(); | ||||||
7885 | SDValue LHS = Node->getOperand(0); | ||||||
7886 | SDValue RHS = Node->getOperand(1); | ||||||
7887 | EVT VT = LHS.getValueType(); | ||||||
7888 | SDLoc dl(Node); | ||||||
7889 | |||||||
7890 | assert(VT == RHS.getValueType() && "Expected operands to be the same type")((VT == RHS.getValueType() && "Expected operands to be the same type" ) ? static_cast<void> (0) : __assert_fail ("VT == RHS.getValueType() && \"Expected operands to be the same type\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 7890, __PRETTY_FUNCTION__)); | ||||||
7891 | assert(VT.isInteger() && "Expected operands to be integers")((VT.isInteger() && "Expected operands to be integers" ) ? static_cast<void> (0) : __assert_fail ("VT.isInteger() && \"Expected operands to be integers\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 7891, __PRETTY_FUNCTION__)); | ||||||
7892 | |||||||
7893 | // usub.sat(a, b) -> umax(a, b) - b | ||||||
7894 | if (Opcode == ISD::USUBSAT && isOperationLegal(ISD::UMAX, VT)) { | ||||||
7895 | SDValue Max = DAG.getNode(ISD::UMAX, dl, VT, LHS, RHS); | ||||||
7896 | return DAG.getNode(ISD::SUB, dl, VT, Max, RHS); | ||||||
7897 | } | ||||||
7898 | |||||||
7899 | // uadd.sat(a, b) -> umin(a, ~b) + b | ||||||
7900 | if (Opcode == ISD::UADDSAT && isOperationLegal(ISD::UMIN, VT)) { | ||||||
7901 | SDValue InvRHS = DAG.getNOT(dl, RHS, VT); | ||||||
7902 | SDValue Min = DAG.getNode(ISD::UMIN, dl, VT, LHS, InvRHS); | ||||||
7903 | return DAG.getNode(ISD::ADD, dl, VT, Min, RHS); | ||||||
7904 | } | ||||||
7905 | |||||||
7906 | unsigned OverflowOp; | ||||||
7907 | switch (Opcode) { | ||||||
7908 | case ISD::SADDSAT: | ||||||
7909 | OverflowOp = ISD::SADDO; | ||||||
7910 | break; | ||||||
7911 | case ISD::UADDSAT: | ||||||
7912 | OverflowOp = ISD::UADDO; | ||||||
7913 | break; | ||||||
7914 | case ISD::SSUBSAT: | ||||||
7915 | OverflowOp = ISD::SSUBO; | ||||||
7916 | break; | ||||||
7917 | case ISD::USUBSAT: | ||||||
7918 | OverflowOp = ISD::USUBO; | ||||||
7919 | break; | ||||||
7920 | default: | ||||||
7921 | llvm_unreachable("Expected method to receive signed or unsigned saturation "::llvm::llvm_unreachable_internal("Expected method to receive signed or unsigned saturation " "addition or subtraction node.", "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 7922) | ||||||
7922 | "addition or subtraction node.")::llvm::llvm_unreachable_internal("Expected method to receive signed or unsigned saturation " "addition or subtraction node.", "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 7922); | ||||||
7923 | } | ||||||
7924 | |||||||
7925 | // FIXME: Should really try to split the vector in case it's legal on a | ||||||
7926 | // subvector. | ||||||
7927 | if (VT.isVector() && !isOperationLegalOrCustom(ISD::VSELECT, VT)) | ||||||
7928 | return DAG.UnrollVectorOp(Node); | ||||||
7929 | |||||||
7930 | unsigned BitWidth = LHS.getScalarValueSizeInBits(); | ||||||
7931 | EVT BoolVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT); | ||||||
7932 | SDValue Result = DAG.getNode(OverflowOp, dl, DAG.getVTList(VT, BoolVT), LHS, RHS); | ||||||
7933 | SDValue SumDiff = Result.getValue(0); | ||||||
7934 | SDValue Overflow = Result.getValue(1); | ||||||
7935 | SDValue Zero = DAG.getConstant(0, dl, VT); | ||||||
7936 | SDValue AllOnes = DAG.getAllOnesConstant(dl, VT); | ||||||
7937 | |||||||
7938 | if (Opcode == ISD::UADDSAT) { | ||||||
7939 | if (getBooleanContents(VT) == ZeroOrNegativeOneBooleanContent) { | ||||||
7940 | // (LHS + RHS) | OverflowMask | ||||||
7941 | SDValue OverflowMask = DAG.getSExtOrTrunc(Overflow, dl, VT); | ||||||
7942 | return DAG.getNode(ISD::OR, dl, VT, SumDiff, OverflowMask); | ||||||
7943 | } | ||||||
7944 | // Overflow ? 0xffff.... : (LHS + RHS) | ||||||
7945 | return DAG.getSelect(dl, VT, Overflow, AllOnes, SumDiff); | ||||||
7946 | } | ||||||
7947 | |||||||
7948 | if (Opcode == ISD::USUBSAT) { | ||||||
7949 | if (getBooleanContents(VT) == ZeroOrNegativeOneBooleanContent) { | ||||||
7950 | // (LHS - RHS) & ~OverflowMask | ||||||
7951 | SDValue OverflowMask = DAG.getSExtOrTrunc(Overflow, dl, VT); | ||||||
7952 | SDValue Not = DAG.getNOT(dl, OverflowMask, VT); | ||||||
7953 | return DAG.getNode(ISD::AND, dl, VT, SumDiff, Not); | ||||||
7954 | } | ||||||
7955 | // Overflow ? 0 : (LHS - RHS) | ||||||
7956 | return DAG.getSelect(dl, VT, Overflow, Zero, SumDiff); | ||||||
7957 | } | ||||||
7958 | |||||||
7959 | // SatMax -> Overflow && SumDiff < 0 | ||||||
7960 | // SatMin -> Overflow && SumDiff >= 0 | ||||||
7961 | APInt MinVal = APInt::getSignedMinValue(BitWidth); | ||||||
7962 | APInt MaxVal = APInt::getSignedMaxValue(BitWidth); | ||||||
7963 | SDValue SatMin = DAG.getConstant(MinVal, dl, VT); | ||||||
7964 | SDValue SatMax = DAG.getConstant(MaxVal, dl, VT); | ||||||
7965 | SDValue SumNeg = DAG.getSetCC(dl, BoolVT, SumDiff, Zero, ISD::SETLT); | ||||||
7966 | Result = DAG.getSelect(dl, VT, SumNeg, SatMax, SatMin); | ||||||
7967 | return DAG.getSelect(dl, VT, Overflow, Result, SumDiff); | ||||||
7968 | } | ||||||
7969 | |||||||
7970 | SDValue TargetLowering::expandShlSat(SDNode *Node, SelectionDAG &DAG) const { | ||||||
7971 | unsigned Opcode = Node->getOpcode(); | ||||||
7972 | bool IsSigned = Opcode == ISD::SSHLSAT; | ||||||
7973 | SDValue LHS = Node->getOperand(0); | ||||||
7974 | SDValue RHS = Node->getOperand(1); | ||||||
7975 | EVT VT = LHS.getValueType(); | ||||||
7976 | SDLoc dl(Node); | ||||||
7977 | |||||||
7978 | assert((Node->getOpcode() == ISD::SSHLSAT ||(((Node->getOpcode() == ISD::SSHLSAT || Node->getOpcode () == ISD::USHLSAT) && "Expected a SHLSAT opcode") ? static_cast <void> (0) : __assert_fail ("(Node->getOpcode() == ISD::SSHLSAT || Node->getOpcode() == ISD::USHLSAT) && \"Expected a SHLSAT opcode\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 7980, __PRETTY_FUNCTION__)) | ||||||
7979 | Node->getOpcode() == ISD::USHLSAT) &&(((Node->getOpcode() == ISD::SSHLSAT || Node->getOpcode () == ISD::USHLSAT) && "Expected a SHLSAT opcode") ? static_cast <void> (0) : __assert_fail ("(Node->getOpcode() == ISD::SSHLSAT || Node->getOpcode() == ISD::USHLSAT) && \"Expected a SHLSAT opcode\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 7980, __PRETTY_FUNCTION__)) | ||||||
7980 | "Expected a SHLSAT opcode")(((Node->getOpcode() == ISD::SSHLSAT || Node->getOpcode () == ISD::USHLSAT) && "Expected a SHLSAT opcode") ? static_cast <void> (0) : __assert_fail ("(Node->getOpcode() == ISD::SSHLSAT || Node->getOpcode() == ISD::USHLSAT) && \"Expected a SHLSAT opcode\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 7980, __PRETTY_FUNCTION__)); | ||||||
7981 | assert(VT == RHS.getValueType() && "Expected operands to be the same type")((VT == RHS.getValueType() && "Expected operands to be the same type" ) ? static_cast<void> (0) : __assert_fail ("VT == RHS.getValueType() && \"Expected operands to be the same type\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 7981, __PRETTY_FUNCTION__)); | ||||||
7982 | assert(VT.isInteger() && "Expected operands to be integers")((VT.isInteger() && "Expected operands to be integers" ) ? static_cast<void> (0) : __assert_fail ("VT.isInteger() && \"Expected operands to be integers\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 7982, __PRETTY_FUNCTION__)); | ||||||
7983 | |||||||
7984 | // If LHS != (LHS << RHS) >> RHS, we have overflow and must saturate. | ||||||
7985 | |||||||
7986 | unsigned BW = VT.getScalarSizeInBits(); | ||||||
7987 | SDValue Result = DAG.getNode(ISD::SHL, dl, VT, LHS, RHS); | ||||||
7988 | SDValue Orig = | ||||||
7989 | DAG.getNode(IsSigned ? ISD::SRA : ISD::SRL, dl, VT, Result, RHS); | ||||||
7990 | |||||||
7991 | SDValue SatVal; | ||||||
7992 | if (IsSigned) { | ||||||
7993 | SDValue SatMin = DAG.getConstant(APInt::getSignedMinValue(BW), dl, VT); | ||||||
7994 | SDValue SatMax = DAG.getConstant(APInt::getSignedMaxValue(BW), dl, VT); | ||||||
7995 | SatVal = DAG.getSelectCC(dl, LHS, DAG.getConstant(0, dl, VT), | ||||||
7996 | SatMin, SatMax, ISD::SETLT); | ||||||
7997 | } else { | ||||||
7998 | SatVal = DAG.getConstant(APInt::getMaxValue(BW), dl, VT); | ||||||
7999 | } | ||||||
8000 | Result = DAG.getSelectCC(dl, LHS, Orig, SatVal, Result, ISD::SETNE); | ||||||
8001 | |||||||
8002 | return Result; | ||||||
8003 | } | ||||||
8004 | |||||||
8005 | SDValue | ||||||
8006 | TargetLowering::expandFixedPointMul(SDNode *Node, SelectionDAG &DAG) const { | ||||||
8007 | assert((Node->getOpcode() == ISD::SMULFIX ||(((Node->getOpcode() == ISD::SMULFIX || Node->getOpcode () == ISD::UMULFIX || Node->getOpcode() == ISD::SMULFIXSAT || Node->getOpcode() == ISD::UMULFIXSAT) && "Expected a fixed point multiplication opcode" ) ? static_cast<void> (0) : __assert_fail ("(Node->getOpcode() == ISD::SMULFIX || Node->getOpcode() == ISD::UMULFIX || Node->getOpcode() == ISD::SMULFIXSAT || Node->getOpcode() == ISD::UMULFIXSAT) && \"Expected a fixed point multiplication opcode\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 8011, __PRETTY_FUNCTION__)) | ||||||
8008 | Node->getOpcode() == ISD::UMULFIX ||(((Node->getOpcode() == ISD::SMULFIX || Node->getOpcode () == ISD::UMULFIX || Node->getOpcode() == ISD::SMULFIXSAT || Node->getOpcode() == ISD::UMULFIXSAT) && "Expected a fixed point multiplication opcode" ) ? static_cast<void> (0) : __assert_fail ("(Node->getOpcode() == ISD::SMULFIX || Node->getOpcode() == ISD::UMULFIX || Node->getOpcode() == ISD::SMULFIXSAT || Node->getOpcode() == ISD::UMULFIXSAT) && \"Expected a fixed point multiplication opcode\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 8011, __PRETTY_FUNCTION__)) | ||||||
8009 | Node->getOpcode() == ISD::SMULFIXSAT ||(((Node->getOpcode() == ISD::SMULFIX || Node->getOpcode () == ISD::UMULFIX || Node->getOpcode() == ISD::SMULFIXSAT || Node->getOpcode() == ISD::UMULFIXSAT) && "Expected a fixed point multiplication opcode" ) ? static_cast<void> (0) : __assert_fail ("(Node->getOpcode() == ISD::SMULFIX || Node->getOpcode() == ISD::UMULFIX || Node->getOpcode() == ISD::SMULFIXSAT || Node->getOpcode() == ISD::UMULFIXSAT) && \"Expected a fixed point multiplication opcode\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 8011, __PRETTY_FUNCTION__)) | ||||||
8010 | Node->getOpcode() == ISD::UMULFIXSAT) &&(((Node->getOpcode() == ISD::SMULFIX || Node->getOpcode () == ISD::UMULFIX || Node->getOpcode() == ISD::SMULFIXSAT || Node->getOpcode() == ISD::UMULFIXSAT) && "Expected a fixed point multiplication opcode" ) ? static_cast<void> (0) : __assert_fail ("(Node->getOpcode() == ISD::SMULFIX || Node->getOpcode() == ISD::UMULFIX || Node->getOpcode() == ISD::SMULFIXSAT || Node->getOpcode() == ISD::UMULFIXSAT) && \"Expected a fixed point multiplication opcode\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 8011, __PRETTY_FUNCTION__)) | ||||||
8011 | "Expected a fixed point multiplication opcode")(((Node->getOpcode() == ISD::SMULFIX || Node->getOpcode () == ISD::UMULFIX || Node->getOpcode() == ISD::SMULFIXSAT || Node->getOpcode() == ISD::UMULFIXSAT) && "Expected a fixed point multiplication opcode" ) ? static_cast<void> (0) : __assert_fail ("(Node->getOpcode() == ISD::SMULFIX || Node->getOpcode() == ISD::UMULFIX || Node->getOpcode() == ISD::SMULFIXSAT || Node->getOpcode() == ISD::UMULFIXSAT) && \"Expected a fixed point multiplication opcode\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 8011, __PRETTY_FUNCTION__)); | ||||||
8012 | |||||||
8013 | SDLoc dl(Node); | ||||||
8014 | SDValue LHS = Node->getOperand(0); | ||||||
8015 | SDValue RHS = Node->getOperand(1); | ||||||
8016 | EVT VT = LHS.getValueType(); | ||||||
8017 | unsigned Scale = Node->getConstantOperandVal(2); | ||||||
8018 | bool Saturating = (Node->getOpcode() == ISD::SMULFIXSAT || | ||||||
8019 | Node->getOpcode() == ISD::UMULFIXSAT); | ||||||
8020 | bool Signed = (Node->getOpcode() == ISD::SMULFIX || | ||||||
8021 | Node->getOpcode() == ISD::SMULFIXSAT); | ||||||
8022 | EVT BoolVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT); | ||||||
8023 | unsigned VTSize = VT.getScalarSizeInBits(); | ||||||
8024 | |||||||
8025 | if (!Scale) { | ||||||
8026 | // [us]mul.fix(a, b, 0) -> mul(a, b) | ||||||
8027 | if (!Saturating) { | ||||||
8028 | if (isOperationLegalOrCustom(ISD::MUL, VT)) | ||||||
8029 | return DAG.getNode(ISD::MUL, dl, VT, LHS, RHS); | ||||||
8030 | } else if (Signed && isOperationLegalOrCustom(ISD::SMULO, VT)) { | ||||||
8031 | SDValue Result = | ||||||
8032 | DAG.getNode(ISD::SMULO, dl, DAG.getVTList(VT, BoolVT), LHS, RHS); | ||||||
8033 | SDValue Product = Result.getValue(0); | ||||||
8034 | SDValue Overflow = Result.getValue(1); | ||||||
8035 | SDValue Zero = DAG.getConstant(0, dl, VT); | ||||||
8036 | |||||||
8037 | APInt MinVal = APInt::getSignedMinValue(VTSize); | ||||||
8038 | APInt MaxVal = APInt::getSignedMaxValue(VTSize); | ||||||
8039 | SDValue SatMin = DAG.getConstant(MinVal, dl, VT); | ||||||
8040 | SDValue SatMax = DAG.getConstant(MaxVal, dl, VT); | ||||||
8041 | SDValue ProdNeg = DAG.getSetCC(dl, BoolVT, Product, Zero, ISD::SETLT); | ||||||
8042 | Result = DAG.getSelect(dl, VT, ProdNeg, SatMax, SatMin); | ||||||
8043 | return DAG.getSelect(dl, VT, Overflow, Result, Product); | ||||||
8044 | } else if (!Signed && isOperationLegalOrCustom(ISD::UMULO, VT)) { | ||||||
8045 | SDValue Result = | ||||||
8046 | DAG.getNode(ISD::UMULO, dl, DAG.getVTList(VT, BoolVT), LHS, RHS); | ||||||
8047 | SDValue Product = Result.getValue(0); | ||||||
8048 | SDValue Overflow = Result.getValue(1); | ||||||
8049 | |||||||
8050 | APInt MaxVal = APInt::getMaxValue(VTSize); | ||||||
8051 | SDValue SatMax = DAG.getConstant(MaxVal, dl, VT); | ||||||
8052 | return DAG.getSelect(dl, VT, Overflow, SatMax, Product); | ||||||
8053 | } | ||||||
8054 | } | ||||||
8055 | |||||||
8056 | assert(((Signed && Scale < VTSize) || (!Signed && Scale <= VTSize)) &&((((Signed && Scale < VTSize) || (!Signed && Scale <= VTSize)) && "Expected scale to be less than the number of bits if signed or at " "most the number of bits if unsigned.") ? static_cast<void > (0) : __assert_fail ("((Signed && Scale < VTSize) || (!Signed && Scale <= VTSize)) && \"Expected scale to be less than the number of bits if signed or at \" \"most the number of bits if unsigned.\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 8058, __PRETTY_FUNCTION__)) | ||||||
8057 | "Expected scale to be less than the number of bits if signed or at "((((Signed && Scale < VTSize) || (!Signed && Scale <= VTSize)) && "Expected scale to be less than the number of bits if signed or at " "most the number of bits if unsigned.") ? static_cast<void > (0) : __assert_fail ("((Signed && Scale < VTSize) || (!Signed && Scale <= VTSize)) && \"Expected scale to be less than the number of bits if signed or at \" \"most the number of bits if unsigned.\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 8058, __PRETTY_FUNCTION__)) | ||||||
8058 | "most the number of bits if unsigned.")((((Signed && Scale < VTSize) || (!Signed && Scale <= VTSize)) && "Expected scale to be less than the number of bits if signed or at " "most the number of bits if unsigned.") ? static_cast<void > (0) : __assert_fail ("((Signed && Scale < VTSize) || (!Signed && Scale <= VTSize)) && \"Expected scale to be less than the number of bits if signed or at \" \"most the number of bits if unsigned.\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 8058, __PRETTY_FUNCTION__)); | ||||||
8059 | assert(LHS.getValueType() == RHS.getValueType() &&((LHS.getValueType() == RHS.getValueType() && "Expected both operands to be the same type" ) ? static_cast<void> (0) : __assert_fail ("LHS.getValueType() == RHS.getValueType() && \"Expected both operands to be the same type\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 8060, __PRETTY_FUNCTION__)) | ||||||
8060 | "Expected both operands to be the same type")((LHS.getValueType() == RHS.getValueType() && "Expected both operands to be the same type" ) ? static_cast<void> (0) : __assert_fail ("LHS.getValueType() == RHS.getValueType() && \"Expected both operands to be the same type\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 8060, __PRETTY_FUNCTION__)); | ||||||
8061 | |||||||
8062 | // Get the upper and lower bits of the result. | ||||||
8063 | SDValue Lo, Hi; | ||||||
8064 | unsigned LoHiOp = Signed ? ISD::SMUL_LOHI : ISD::UMUL_LOHI; | ||||||
8065 | unsigned HiOp = Signed ? ISD::MULHS : ISD::MULHU; | ||||||
8066 | if (isOperationLegalOrCustom(LoHiOp, VT)) { | ||||||
8067 | SDValue Result = DAG.getNode(LoHiOp, dl, DAG.getVTList(VT, VT), LHS, RHS); | ||||||
8068 | Lo = Result.getValue(0); | ||||||
8069 | Hi = Result.getValue(1); | ||||||
8070 | } else if (isOperationLegalOrCustom(HiOp, VT)) { | ||||||
8071 | Lo = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS); | ||||||
8072 | Hi = DAG.getNode(HiOp, dl, VT, LHS, RHS); | ||||||
8073 | } else if (VT.isVector()) { | ||||||
8074 | return SDValue(); | ||||||
8075 | } else { | ||||||
8076 | report_fatal_error("Unable to expand fixed point multiplication."); | ||||||
8077 | } | ||||||
8078 | |||||||
8079 | if (Scale == VTSize) | ||||||
8080 | // Result is just the top half since we'd be shifting by the width of the | ||||||
8081 | // operand. Overflow impossible so this works for both UMULFIX and | ||||||
8082 | // UMULFIXSAT. | ||||||
8083 | return Hi; | ||||||
8084 | |||||||
8085 | // The result will need to be shifted right by the scale since both operands | ||||||
8086 | // are scaled. The result is given to us in 2 halves, so we only want part of | ||||||
8087 | // both in the result. | ||||||
8088 | EVT ShiftTy = getShiftAmountTy(VT, DAG.getDataLayout()); | ||||||
8089 | SDValue Result = DAG.getNode(ISD::FSHR, dl, VT, Hi, Lo, | ||||||
8090 | DAG.getConstant(Scale, dl, ShiftTy)); | ||||||
8091 | if (!Saturating) | ||||||
8092 | return Result; | ||||||
8093 | |||||||
8094 | if (!Signed) { | ||||||
8095 | // Unsigned overflow happened if the upper (VTSize - Scale) bits (of the | ||||||
8096 | // widened multiplication) aren't all zeroes. | ||||||
8097 | |||||||
8098 | // Saturate to max if ((Hi >> Scale) != 0), | ||||||
8099 | // which is the same as if (Hi > ((1 << Scale) - 1)) | ||||||
8100 | APInt MaxVal = APInt::getMaxValue(VTSize); | ||||||
8101 | SDValue LowMask = DAG.getConstant(APInt::getLowBitsSet(VTSize, Scale), | ||||||
8102 | dl, VT); | ||||||
8103 | Result = DAG.getSelectCC(dl, Hi, LowMask, | ||||||
8104 | DAG.getConstant(MaxVal, dl, VT), Result, | ||||||
8105 | ISD::SETUGT); | ||||||
8106 | |||||||
8107 | return Result; | ||||||
8108 | } | ||||||
8109 | |||||||
8110 | // Signed overflow happened if the upper (VTSize - Scale + 1) bits (of the | ||||||
8111 | // widened multiplication) aren't all ones or all zeroes. | ||||||
8112 | |||||||
8113 | SDValue SatMin = DAG.getConstant(APInt::getSignedMinValue(VTSize), dl, VT); | ||||||
8114 | SDValue SatMax = DAG.getConstant(APInt::getSignedMaxValue(VTSize), dl, VT); | ||||||
8115 | |||||||
8116 | if (Scale == 0) { | ||||||
8117 | SDValue Sign = DAG.getNode(ISD::SRA, dl, VT, Lo, | ||||||
8118 | DAG.getConstant(VTSize - 1, dl, ShiftTy)); | ||||||
8119 | SDValue Overflow = DAG.getSetCC(dl, BoolVT, Hi, Sign, ISD::SETNE); | ||||||
8120 | // Saturated to SatMin if wide product is negative, and SatMax if wide | ||||||
8121 | // product is positive ... | ||||||
8122 | SDValue Zero = DAG.getConstant(0, dl, VT); | ||||||
8123 | SDValue ResultIfOverflow = DAG.getSelectCC(dl, Hi, Zero, SatMin, SatMax, | ||||||
8124 | ISD::SETLT); | ||||||
8125 | // ... but only if we overflowed. | ||||||
8126 | return DAG.getSelect(dl, VT, Overflow, ResultIfOverflow, Result); | ||||||
8127 | } | ||||||
8128 | |||||||
8129 | // We handled Scale==0 above so all the bits to examine is in Hi. | ||||||
8130 | |||||||
8131 | // Saturate to max if ((Hi >> (Scale - 1)) > 0), | ||||||
8132 | // which is the same as if (Hi > (1 << (Scale - 1)) - 1) | ||||||
8133 | SDValue LowMask = DAG.getConstant(APInt::getLowBitsSet(VTSize, Scale - 1), | ||||||
8134 | dl, VT); | ||||||
8135 | Result = DAG.getSelectCC(dl, Hi, LowMask, SatMax, Result, ISD::SETGT); | ||||||
8136 | // Saturate to min if (Hi >> (Scale - 1)) < -1), | ||||||
8137 | // which is the same as if (HI < (-1 << (Scale - 1)) | ||||||
8138 | SDValue HighMask = | ||||||
8139 | DAG.getConstant(APInt::getHighBitsSet(VTSize, VTSize - Scale + 1), | ||||||
8140 | dl, VT); | ||||||
8141 | Result = DAG.getSelectCC(dl, Hi, HighMask, SatMin, Result, ISD::SETLT); | ||||||
8142 | return Result; | ||||||
8143 | } | ||||||
8144 | |||||||
8145 | SDValue | ||||||
8146 | TargetLowering::expandFixedPointDiv(unsigned Opcode, const SDLoc &dl, | ||||||
8147 | SDValue LHS, SDValue RHS, | ||||||
8148 | unsigned Scale, SelectionDAG &DAG) const { | ||||||
8149 | assert((Opcode == ISD::SDIVFIX || Opcode == ISD::SDIVFIXSAT ||(((Opcode == ISD::SDIVFIX || Opcode == ISD::SDIVFIXSAT || Opcode == ISD::UDIVFIX || Opcode == ISD::UDIVFIXSAT) && "Expected a fixed point division opcode" ) ? static_cast<void> (0) : __assert_fail ("(Opcode == ISD::SDIVFIX || Opcode == ISD::SDIVFIXSAT || Opcode == ISD::UDIVFIX || Opcode == ISD::UDIVFIXSAT) && \"Expected a fixed point division opcode\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 8151, __PRETTY_FUNCTION__)) | ||||||
| |||||||
8150 | Opcode == ISD::UDIVFIX || Opcode == ISD::UDIVFIXSAT) &&(((Opcode == ISD::SDIVFIX || Opcode == ISD::SDIVFIXSAT || Opcode == ISD::UDIVFIX || Opcode == ISD::UDIVFIXSAT) && "Expected a fixed point division opcode" ) ? static_cast<void> (0) : __assert_fail ("(Opcode == ISD::SDIVFIX || Opcode == ISD::SDIVFIXSAT || Opcode == ISD::UDIVFIX || Opcode == ISD::UDIVFIXSAT) && \"Expected a fixed point division opcode\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 8151, __PRETTY_FUNCTION__)) | ||||||
8151 | "Expected a fixed point division opcode")(((Opcode == ISD::SDIVFIX || Opcode == ISD::SDIVFIXSAT || Opcode == ISD::UDIVFIX || Opcode == ISD::UDIVFIXSAT) && "Expected a fixed point division opcode" ) ? static_cast<void> (0) : __assert_fail ("(Opcode == ISD::SDIVFIX || Opcode == ISD::SDIVFIXSAT || Opcode == ISD::UDIVFIX || Opcode == ISD::UDIVFIXSAT) && \"Expected a fixed point division opcode\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 8151, __PRETTY_FUNCTION__)); | ||||||
8152 | |||||||
8153 | EVT VT = LHS.getValueType(); | ||||||
8154 | bool Signed = Opcode
| ||||||
8155 | bool Saturating = Opcode
| ||||||
8156 | EVT BoolVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT); | ||||||
8157 | |||||||
8158 | // If there is enough room in the type to upscale the LHS or downscale the | ||||||
8159 | // RHS before the division, we can perform it in this type without having to | ||||||
8160 | // resize. For signed operations, the LHS headroom is the number of | ||||||
8161 | // redundant sign bits, and for unsigned ones it is the number of zeroes. | ||||||
8162 | // The headroom for the RHS is the number of trailing zeroes. | ||||||
8163 | unsigned LHSLead = Signed
| ||||||
8164 | : DAG.computeKnownBits(LHS).countMinLeadingZeros(); | ||||||
8165 | unsigned RHSTrail = DAG.computeKnownBits(RHS).countMinTrailingZeros(); | ||||||
8166 | |||||||
8167 | // For signed saturating operations, we need to be able to detect true integer | ||||||
8168 | // division overflow; that is, when you have MIN / -EPS. However, this | ||||||
8169 | // is undefined behavior and if we emit divisions that could take such | ||||||
8170 | // values it may cause undesired behavior (arithmetic exceptions on x86, for | ||||||
8171 | // example). | ||||||
8172 | // Avoid this by requiring an extra bit so that we never get this case. | ||||||
8173 | // FIXME: This is a bit unfortunate as it means that for an 8-bit 7-scale | ||||||
8174 | // signed saturating division, we need to emit a whopping 32-bit division. | ||||||
8175 | if (LHSLead + RHSTrail < Scale + (unsigned)(Saturating
| ||||||
8176 | return SDValue(); | ||||||
8177 | |||||||
8178 | unsigned LHSShift = std::min(LHSLead, Scale); | ||||||
8179 | unsigned RHSShift = Scale - LHSShift; | ||||||
8180 | |||||||
8181 | // At this point, we know that if we shift the LHS up by LHSShift and the | ||||||
8182 | // RHS down by RHSShift, we can emit a regular division with a final scaling | ||||||
8183 | // factor of Scale. | ||||||
8184 | |||||||
8185 | EVT ShiftTy = getShiftAmountTy(VT, DAG.getDataLayout()); | ||||||
8186 | if (LHSShift) | ||||||
8187 | LHS = DAG.getNode(ISD::SHL, dl, VT, LHS, | ||||||
8188 | DAG.getConstant(LHSShift, dl, ShiftTy)); | ||||||
8189 | if (RHSShift) | ||||||
8190 | RHS = DAG.getNode(Signed ? ISD::SRA : ISD::SRL, dl, VT, RHS, | ||||||
8191 | DAG.getConstant(RHSShift, dl, ShiftTy)); | ||||||
8192 | |||||||
8193 | SDValue Quot; | ||||||
8194 | if (Signed
| ||||||
8195 | // For signed operations, if the resulting quotient is negative and the | ||||||
8196 | // remainder is nonzero, subtract 1 from the quotient to round towards | ||||||
8197 | // negative infinity. | ||||||
8198 | SDValue Rem; | ||||||
8199 | // FIXME: Ideally we would always produce an SDIVREM here, but if the | ||||||
8200 | // type isn't legal, SDIVREM cannot be expanded. There is no reason why | ||||||
8201 | // we couldn't just form a libcall, but the type legalizer doesn't do it. | ||||||
8202 | if (isTypeLegal(VT) && | ||||||
8203 | isOperationLegalOrCustom(ISD::SDIVREM, VT)) { | ||||||
8204 | Quot = DAG.getNode(ISD::SDIVREM, dl, | ||||||
8205 | DAG.getVTList(VT, VT), | ||||||
8206 | LHS, RHS); | ||||||
8207 | Rem = Quot.getValue(1); | ||||||
8208 | Quot = Quot.getValue(0); | ||||||
8209 | } else { | ||||||
8210 | Quot = DAG.getNode(ISD::SDIV, dl, VT, | ||||||
8211 | LHS, RHS); | ||||||
8212 | Rem = DAG.getNode(ISD::SREM, dl, VT, | ||||||
8213 | LHS, RHS); | ||||||
8214 | } | ||||||
8215 | SDValue Zero = DAG.getConstant(0, dl, VT); | ||||||
8216 | SDValue RemNonZero = DAG.getSetCC(dl, BoolVT, Rem, Zero, ISD::SETNE); | ||||||
8217 | SDValue LHSNeg = DAG.getSetCC(dl, BoolVT, LHS, Zero, ISD::SETLT); | ||||||
8218 | SDValue RHSNeg = DAG.getSetCC(dl, BoolVT, RHS, Zero, ISD::SETLT); | ||||||
8219 | SDValue QuotNeg = DAG.getNode(ISD::XOR, dl, BoolVT, LHSNeg, RHSNeg); | ||||||
8220 | SDValue Sub1 = DAG.getNode(ISD::SUB, dl, VT, Quot, | ||||||
8221 | DAG.getConstant(1, dl, VT)); | ||||||
8222 | Quot = DAG.getSelect(dl, VT, | ||||||
8223 | DAG.getNode(ISD::AND, dl, BoolVT, RemNonZero, QuotNeg), | ||||||
8224 | Sub1, Quot); | ||||||
8225 | } else | ||||||
8226 | Quot = DAG.getNode(ISD::UDIV, dl, VT, | ||||||
8227 | LHS, RHS); | ||||||
8228 | |||||||
8229 | return Quot; | ||||||
8230 | } | ||||||
8231 | |||||||
8232 | void TargetLowering::expandUADDSUBO( | ||||||
8233 | SDNode *Node, SDValue &Result, SDValue &Overflow, SelectionDAG &DAG) const { | ||||||
8234 | SDLoc dl(Node); | ||||||
8235 | SDValue LHS = Node->getOperand(0); | ||||||
8236 | SDValue RHS = Node->getOperand(1); | ||||||
8237 | bool IsAdd = Node->getOpcode() == ISD::UADDO; | ||||||
8238 | |||||||
8239 | // If ADD/SUBCARRY is legal, use that instead. | ||||||
8240 | unsigned OpcCarry = IsAdd ? ISD::ADDCARRY : ISD::SUBCARRY; | ||||||
8241 | if (isOperationLegalOrCustom(OpcCarry, Node->getValueType(0))) { | ||||||
8242 | SDValue CarryIn = DAG.getConstant(0, dl, Node->getValueType(1)); | ||||||
8243 | SDValue NodeCarry = DAG.getNode(OpcCarry, dl, Node->getVTList(), | ||||||
8244 | { LHS, RHS, CarryIn }); | ||||||
8245 | Result = SDValue(NodeCarry.getNode(), 0); | ||||||
8246 | Overflow = SDValue(NodeCarry.getNode(), 1); | ||||||
8247 | return; | ||||||
8248 | } | ||||||
8249 | |||||||
8250 | Result = DAG.getNode(IsAdd ? ISD::ADD : ISD::SUB, dl, | ||||||
8251 | LHS.getValueType(), LHS, RHS); | ||||||
8252 | |||||||
8253 | EVT ResultType = Node->getValueType(1); | ||||||
8254 | EVT SetCCType = getSetCCResultType( | ||||||
8255 | DAG.getDataLayout(), *DAG.getContext(), Node->getValueType(0)); | ||||||
8256 | ISD::CondCode CC = IsAdd ? ISD::SETULT : ISD::SETUGT; | ||||||
8257 | SDValue SetCC = DAG.getSetCC(dl, SetCCType, Result, LHS, CC); | ||||||
8258 | Overflow = DAG.getBoolExtOrTrunc(SetCC, dl, ResultType, ResultType); | ||||||
8259 | } | ||||||
8260 | |||||||
8261 | void TargetLowering::expandSADDSUBO( | ||||||
8262 | SDNode *Node, SDValue &Result, SDValue &Overflow, SelectionDAG &DAG) const { | ||||||
8263 | SDLoc dl(Node); | ||||||
8264 | SDValue LHS = Node->getOperand(0); | ||||||
8265 | SDValue RHS = Node->getOperand(1); | ||||||
8266 | bool IsAdd = Node->getOpcode() == ISD::SADDO; | ||||||
8267 | |||||||
8268 | Result = DAG.getNode(IsAdd ? ISD::ADD : ISD::SUB, dl, | ||||||
8269 | LHS.getValueType(), LHS, RHS); | ||||||
8270 | |||||||
8271 | EVT ResultType = Node->getValueType(1); | ||||||
8272 | EVT OType = getSetCCResultType( | ||||||
8273 | DAG.getDataLayout(), *DAG.getContext(), Node->getValueType(0)); | ||||||
8274 | |||||||
8275 | // If SADDSAT/SSUBSAT is legal, compare results to detect overflow. | ||||||
8276 | unsigned OpcSat = IsAdd ? ISD::SADDSAT : ISD::SSUBSAT; | ||||||
8277 | if (isOperationLegalOrCustom(OpcSat, LHS.getValueType())) { | ||||||
8278 | SDValue Sat = DAG.getNode(OpcSat, dl, LHS.getValueType(), LHS, RHS); | ||||||
8279 | SDValue SetCC = DAG.getSetCC(dl, OType, Result, Sat, ISD::SETNE); | ||||||
8280 | Overflow = DAG.getBoolExtOrTrunc(SetCC, dl, ResultType, ResultType); | ||||||
8281 | return; | ||||||
8282 | } | ||||||
8283 | |||||||
8284 | SDValue Zero = DAG.getConstant(0, dl, LHS.getValueType()); | ||||||
8285 | |||||||
8286 | // For an addition, the result should be less than one of the operands (LHS) | ||||||
8287 | // if and only if the other operand (RHS) is negative, otherwise there will | ||||||
8288 | // be overflow. | ||||||
8289 | // For a subtraction, the result should be less than one of the operands | ||||||
8290 | // (LHS) if and only if the other operand (RHS) is (non-zero) positive, | ||||||
8291 | // otherwise there will be overflow. | ||||||
8292 | SDValue ResultLowerThanLHS = DAG.getSetCC(dl, OType, Result, LHS, ISD::SETLT); | ||||||
8293 | SDValue ConditionRHS = | ||||||
8294 | DAG.getSetCC(dl, OType, RHS, Zero, IsAdd ? ISD::SETLT : ISD::SETGT); | ||||||
8295 | |||||||
8296 | Overflow = DAG.getBoolExtOrTrunc( | ||||||
8297 | DAG.getNode(ISD::XOR, dl, OType, ConditionRHS, ResultLowerThanLHS), dl, | ||||||
8298 | ResultType, ResultType); | ||||||
8299 | } | ||||||
8300 | |||||||
8301 | bool TargetLowering::expandMULO(SDNode *Node, SDValue &Result, | ||||||
8302 | SDValue &Overflow, SelectionDAG &DAG) const { | ||||||
8303 | SDLoc dl(Node); | ||||||
8304 | EVT VT = Node->getValueType(0); | ||||||
8305 | EVT SetCCVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT); | ||||||
8306 | SDValue LHS = Node->getOperand(0); | ||||||
8307 | SDValue RHS = Node->getOperand(1); | ||||||
8308 | bool isSigned = Node->getOpcode() == ISD::SMULO; | ||||||
8309 | |||||||
8310 | // For power-of-two multiplications we can use a simpler shift expansion. | ||||||
8311 | if (ConstantSDNode *RHSC = isConstOrConstSplat(RHS)) { | ||||||
8312 | const APInt &C = RHSC->getAPIntValue(); | ||||||
8313 | // mulo(X, 1 << S) -> { X << S, (X << S) >> S != X } | ||||||
8314 | if (C.isPowerOf2()) { | ||||||
8315 | // smulo(x, signed_min) is same as umulo(x, signed_min). | ||||||
8316 | bool UseArithShift = isSigned && !C.isMinSignedValue(); | ||||||
8317 | EVT ShiftAmtTy = getShiftAmountTy(VT, DAG.getDataLayout()); | ||||||
8318 | SDValue ShiftAmt = DAG.getConstant(C.logBase2(), dl, ShiftAmtTy); | ||||||
8319 | Result = DAG.getNode(ISD::SHL, dl, VT, LHS, ShiftAmt); | ||||||
8320 | Overflow = DAG.getSetCC(dl, SetCCVT, | ||||||
8321 | DAG.getNode(UseArithShift ? ISD::SRA : ISD::SRL, | ||||||
8322 | dl, VT, Result, ShiftAmt), | ||||||
8323 | LHS, ISD::SETNE); | ||||||
8324 | return true; | ||||||
8325 | } | ||||||
8326 | } | ||||||
8327 | |||||||
8328 | EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), VT.getScalarSizeInBits() * 2); | ||||||
8329 | if (VT.isVector()) | ||||||
8330 | WideVT = EVT::getVectorVT(*DAG.getContext(), WideVT, | ||||||
8331 | VT.getVectorNumElements()); | ||||||
8332 | |||||||
8333 | SDValue BottomHalf; | ||||||
8334 | SDValue TopHalf; | ||||||
8335 | static const unsigned Ops[2][3] = | ||||||
8336 | { { ISD::MULHU, ISD::UMUL_LOHI, ISD::ZERO_EXTEND }, | ||||||
8337 | { ISD::MULHS, ISD::SMUL_LOHI, ISD::SIGN_EXTEND }}; | ||||||
8338 | if (isOperationLegalOrCustom(Ops[isSigned][0], VT)) { | ||||||
8339 | BottomHalf = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS); | ||||||
8340 | TopHalf = DAG.getNode(Ops[isSigned][0], dl, VT, LHS, RHS); | ||||||
8341 | } else if (isOperationLegalOrCustom(Ops[isSigned][1], VT)) { | ||||||
8342 | BottomHalf = DAG.getNode(Ops[isSigned][1], dl, DAG.getVTList(VT, VT), LHS, | ||||||
8343 | RHS); | ||||||
8344 | TopHalf = BottomHalf.getValue(1); | ||||||
8345 | } else if (isTypeLegal(WideVT)) { | ||||||
8346 | LHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, LHS); | ||||||
8347 | RHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, RHS); | ||||||
8348 | SDValue Mul = DAG.getNode(ISD::MUL, dl, WideVT, LHS, RHS); | ||||||
8349 | BottomHalf = DAG.getNode(ISD::TRUNCATE, dl, VT, Mul); | ||||||
8350 | SDValue ShiftAmt = DAG.getConstant(VT.getScalarSizeInBits(), dl, | ||||||
8351 | getShiftAmountTy(WideVT, DAG.getDataLayout())); | ||||||
8352 | TopHalf = DAG.getNode(ISD::TRUNCATE, dl, VT, | ||||||
8353 | DAG.getNode(ISD::SRL, dl, WideVT, Mul, ShiftAmt)); | ||||||
8354 | } else { | ||||||
8355 | if (VT.isVector()) | ||||||
8356 | return false; | ||||||
8357 | |||||||
8358 | // We can fall back to a libcall with an illegal type for the MUL if we | ||||||
8359 | // have a libcall big enough. | ||||||
8360 | // Also, we can fall back to a division in some cases, but that's a big | ||||||
8361 | // performance hit in the general case. | ||||||
8362 | RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; | ||||||
8363 | if (WideVT == MVT::i16) | ||||||
8364 | LC = RTLIB::MUL_I16; | ||||||
8365 | else if (WideVT == MVT::i32) | ||||||
8366 | LC = RTLIB::MUL_I32; | ||||||
8367 | else if (WideVT == MVT::i64) | ||||||
8368 | LC = RTLIB::MUL_I64; | ||||||
8369 | else if (WideVT == MVT::i128) | ||||||
8370 | LC = RTLIB::MUL_I128; | ||||||
8371 | assert(LC != RTLIB::UNKNOWN_LIBCALL && "Cannot expand this operation!")((LC != RTLIB::UNKNOWN_LIBCALL && "Cannot expand this operation!" ) ? static_cast<void> (0) : __assert_fail ("LC != RTLIB::UNKNOWN_LIBCALL && \"Cannot expand this operation!\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 8371, __PRETTY_FUNCTION__)); | ||||||
8372 | |||||||
8373 | SDValue HiLHS; | ||||||
8374 | SDValue HiRHS; | ||||||
8375 | if (isSigned) { | ||||||
8376 | // The high part is obtained by SRA'ing all but one of the bits of low | ||||||
8377 | // part. | ||||||
8378 | unsigned LoSize = VT.getFixedSizeInBits(); | ||||||
8379 | HiLHS = | ||||||
8380 | DAG.getNode(ISD::SRA, dl, VT, LHS, | ||||||
8381 | DAG.getConstant(LoSize - 1, dl, | ||||||
8382 | getPointerTy(DAG.getDataLayout()))); | ||||||
8383 | HiRHS = | ||||||
8384 | DAG.getNode(ISD::SRA, dl, VT, RHS, | ||||||
8385 | DAG.getConstant(LoSize - 1, dl, | ||||||
8386 | getPointerTy(DAG.getDataLayout()))); | ||||||
8387 | } else { | ||||||
8388 | HiLHS = DAG.getConstant(0, dl, VT); | ||||||
8389 | HiRHS = DAG.getConstant(0, dl, VT); | ||||||
8390 | } | ||||||
8391 | |||||||
8392 | // Here we're passing the 2 arguments explicitly as 4 arguments that are | ||||||
8393 | // pre-lowered to the correct types. This all depends upon WideVT not | ||||||
8394 | // being a legal type for the architecture and thus has to be split to | ||||||
8395 | // two arguments. | ||||||
8396 | SDValue Ret; | ||||||
8397 | TargetLowering::MakeLibCallOptions CallOptions; | ||||||
8398 | CallOptions.setSExt(isSigned); | ||||||
8399 | CallOptions.setIsPostTypeLegalization(true); | ||||||
8400 | if (shouldSplitFunctionArgumentsAsLittleEndian(DAG.getDataLayout())) { | ||||||
8401 | // Halves of WideVT are packed into registers in different order | ||||||
8402 | // depending on platform endianness. This is usually handled by | ||||||
8403 | // the C calling convention, but we can't defer to it in | ||||||
8404 | // the legalizer. | ||||||
8405 | SDValue Args[] = { LHS, HiLHS, RHS, HiRHS }; | ||||||
8406 | Ret = makeLibCall(DAG, LC, WideVT, Args, CallOptions, dl).first; | ||||||
8407 | } else { | ||||||
8408 | SDValue Args[] = { HiLHS, LHS, HiRHS, RHS }; | ||||||
8409 | Ret = makeLibCall(DAG, LC, WideVT, Args, CallOptions, dl).first; | ||||||
8410 | } | ||||||
8411 | assert(Ret.getOpcode() == ISD::MERGE_VALUES &&((Ret.getOpcode() == ISD::MERGE_VALUES && "Ret value is a collection of constituent nodes holding result." ) ? static_cast<void> (0) : __assert_fail ("Ret.getOpcode() == ISD::MERGE_VALUES && \"Ret value is a collection of constituent nodes holding result.\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 8412, __PRETTY_FUNCTION__)) | ||||||
8412 | "Ret value is a collection of constituent nodes holding result.")((Ret.getOpcode() == ISD::MERGE_VALUES && "Ret value is a collection of constituent nodes holding result." ) ? static_cast<void> (0) : __assert_fail ("Ret.getOpcode() == ISD::MERGE_VALUES && \"Ret value is a collection of constituent nodes holding result.\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 8412, __PRETTY_FUNCTION__)); | ||||||
8413 | if (DAG.getDataLayout().isLittleEndian()) { | ||||||
8414 | // Same as above. | ||||||
8415 | BottomHalf = Ret.getOperand(0); | ||||||
8416 | TopHalf = Ret.getOperand(1); | ||||||
8417 | } else { | ||||||
8418 | BottomHalf = Ret.getOperand(1); | ||||||
8419 | TopHalf = Ret.getOperand(0); | ||||||
8420 | } | ||||||
8421 | } | ||||||
8422 | |||||||
8423 | Result = BottomHalf; | ||||||
8424 | if (isSigned) { | ||||||
8425 | SDValue ShiftAmt = DAG.getConstant( | ||||||
8426 | VT.getScalarSizeInBits() - 1, dl, | ||||||
8427 | getShiftAmountTy(BottomHalf.getValueType(), DAG.getDataLayout())); | ||||||
8428 | SDValue Sign = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, ShiftAmt); | ||||||
8429 | Overflow = DAG.getSetCC(dl, SetCCVT, TopHalf, Sign, ISD::SETNE); | ||||||
8430 | } else { | ||||||
8431 | Overflow = DAG.getSetCC(dl, SetCCVT, TopHalf, | ||||||
8432 | DAG.getConstant(0, dl, VT), ISD::SETNE); | ||||||
8433 | } | ||||||
8434 | |||||||
8435 | // Truncate the result if SetCC returns a larger type than needed. | ||||||
8436 | EVT RType = Node->getValueType(1); | ||||||
8437 | if (RType.bitsLT(Overflow.getValueType())) | ||||||
8438 | Overflow = DAG.getNode(ISD::TRUNCATE, dl, RType, Overflow); | ||||||
8439 | |||||||
8440 | assert(RType.getSizeInBits() == Overflow.getValueSizeInBits() &&((RType.getSizeInBits() == Overflow.getValueSizeInBits() && "Unexpected result type for S/UMULO legalization") ? static_cast <void> (0) : __assert_fail ("RType.getSizeInBits() == Overflow.getValueSizeInBits() && \"Unexpected result type for S/UMULO legalization\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 8441, __PRETTY_FUNCTION__)) | ||||||
8441 | "Unexpected result type for S/UMULO legalization")((RType.getSizeInBits() == Overflow.getValueSizeInBits() && "Unexpected result type for S/UMULO legalization") ? static_cast <void> (0) : __assert_fail ("RType.getSizeInBits() == Overflow.getValueSizeInBits() && \"Unexpected result type for S/UMULO legalization\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 8441, __PRETTY_FUNCTION__)); | ||||||
8442 | return true; | ||||||
8443 | } | ||||||
8444 | |||||||
8445 | SDValue TargetLowering::expandVecReduce(SDNode *Node, SelectionDAG &DAG) const { | ||||||
8446 | SDLoc dl(Node); | ||||||
8447 | unsigned BaseOpcode = ISD::getVecReduceBaseOpcode(Node->getOpcode()); | ||||||
8448 | SDValue Op = Node->getOperand(0); | ||||||
8449 | EVT VT = Op.getValueType(); | ||||||
8450 | |||||||
8451 | if (VT.isScalableVector()) | ||||||
8452 | report_fatal_error( | ||||||
8453 | "Expanding reductions for scalable vectors is undefined."); | ||||||
8454 | |||||||
8455 | // Try to use a shuffle reduction for power of two vectors. | ||||||
8456 | if (VT.isPow2VectorType()) { | ||||||
8457 | while (VT.getVectorNumElements() > 1) { | ||||||
8458 | EVT HalfVT = VT.getHalfNumVectorElementsVT(*DAG.getContext()); | ||||||
8459 | if (!isOperationLegalOrCustom(BaseOpcode, HalfVT)) | ||||||
8460 | break; | ||||||
8461 | |||||||
8462 | SDValue Lo, Hi; | ||||||
8463 | std::tie(Lo, Hi) = DAG.SplitVector(Op, dl); | ||||||
8464 | Op = DAG.getNode(BaseOpcode, dl, HalfVT, Lo, Hi); | ||||||
8465 | VT = HalfVT; | ||||||
8466 | } | ||||||
8467 | } | ||||||
8468 | |||||||
8469 | EVT EltVT = VT.getVectorElementType(); | ||||||
8470 | unsigned NumElts = VT.getVectorNumElements(); | ||||||
8471 | |||||||
8472 | SmallVector<SDValue, 8> Ops; | ||||||
8473 | DAG.ExtractVectorElements(Op, Ops, 0, NumElts); | ||||||
8474 | |||||||
8475 | SDValue Res = Ops[0]; | ||||||
8476 | for (unsigned i = 1; i < NumElts; i++) | ||||||
8477 | Res = DAG.getNode(BaseOpcode, dl, EltVT, Res, Ops[i], Node->getFlags()); | ||||||
8478 | |||||||
8479 | // Result type may be wider than element type. | ||||||
8480 | if (EltVT != Node->getValueType(0)) | ||||||
8481 | Res = DAG.getNode(ISD::ANY_EXTEND, dl, Node->getValueType(0), Res); | ||||||
8482 | return Res; | ||||||
8483 | } | ||||||
8484 | |||||||
8485 | SDValue TargetLowering::expandVecReduceSeq(SDNode *Node, SelectionDAG &DAG) const { | ||||||
8486 | SDLoc dl(Node); | ||||||
8487 | SDValue AccOp = Node->getOperand(0); | ||||||
8488 | SDValue VecOp = Node->getOperand(1); | ||||||
8489 | SDNodeFlags Flags = Node->getFlags(); | ||||||
8490 | |||||||
8491 | EVT VT = VecOp.getValueType(); | ||||||
8492 | EVT EltVT = VT.getVectorElementType(); | ||||||
8493 | |||||||
8494 | if (VT.isScalableVector()) | ||||||
8495 | report_fatal_error( | ||||||
8496 | "Expanding reductions for scalable vectors is undefined."); | ||||||
8497 | |||||||
8498 | unsigned NumElts = VT.getVectorNumElements(); | ||||||
8499 | |||||||
8500 | SmallVector<SDValue, 8> Ops; | ||||||
8501 | DAG.ExtractVectorElements(VecOp, Ops, 0, NumElts); | ||||||
8502 | |||||||
8503 | unsigned BaseOpcode = ISD::getVecReduceBaseOpcode(Node->getOpcode()); | ||||||
8504 | |||||||
8505 | SDValue Res = AccOp; | ||||||
8506 | for (unsigned i = 0; i < NumElts; i++) | ||||||
8507 | Res = DAG.getNode(BaseOpcode, dl, EltVT, Res, Ops[i], Flags); | ||||||
8508 | |||||||
8509 | return Res; | ||||||
8510 | } | ||||||
8511 | |||||||
8512 | bool TargetLowering::expandREM(SDNode *Node, SDValue &Result, | ||||||
8513 | SelectionDAG &DAG) const { | ||||||
8514 | EVT VT = Node->getValueType(0); | ||||||
8515 | SDLoc dl(Node); | ||||||
8516 | bool isSigned = Node->getOpcode() == ISD::SREM; | ||||||
8517 | unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV; | ||||||
8518 | unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM; | ||||||
8519 | SDValue Dividend = Node->getOperand(0); | ||||||
8520 | SDValue Divisor = Node->getOperand(1); | ||||||
8521 | if (isOperationLegalOrCustom(DivRemOpc, VT)) { | ||||||
8522 | SDVTList VTs = DAG.getVTList(VT, VT); | ||||||
8523 | Result = DAG.getNode(DivRemOpc, dl, VTs, Dividend, Divisor).getValue(1); | ||||||
8524 | return true; | ||||||
8525 | } else if (isOperationLegalOrCustom(DivOpc, VT)) { | ||||||
8526 | // X % Y -> X-X/Y*Y | ||||||
8527 | SDValue Divide = DAG.getNode(DivOpc, dl, VT, Dividend, Divisor); | ||||||
8528 | SDValue Mul = DAG.getNode(ISD::MUL, dl, VT, Divide, Divisor); | ||||||
8529 | Result = DAG.getNode(ISD::SUB, dl, VT, Dividend, Mul); | ||||||
8530 | return true; | ||||||
8531 | } | ||||||
8532 | return false; | ||||||
8533 | } | ||||||
8534 | |||||||
8535 | SDValue TargetLowering::expandFP_TO_INT_SAT(SDNode *Node, | ||||||
8536 | SelectionDAG &DAG) const { | ||||||
8537 | bool IsSigned = Node->getOpcode() == ISD::FP_TO_SINT_SAT; | ||||||
8538 | SDLoc dl(SDValue(Node, 0)); | ||||||
8539 | SDValue Src = Node->getOperand(0); | ||||||
8540 | |||||||
8541 | // DstVT is the result type, while SatVT is the size to which we saturate | ||||||
8542 | EVT SrcVT = Src.getValueType(); | ||||||
8543 | EVT DstVT = Node->getValueType(0); | ||||||
8544 | |||||||
8545 | unsigned SatWidth = Node->getConstantOperandVal(1); | ||||||
8546 | unsigned DstWidth = DstVT.getScalarSizeInBits(); | ||||||
8547 | assert(SatWidth <= DstWidth &&((SatWidth <= DstWidth && "Expected saturation width smaller than result width" ) ? static_cast<void> (0) : __assert_fail ("SatWidth <= DstWidth && \"Expected saturation width smaller than result width\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 8548, __PRETTY_FUNCTION__)) | ||||||
8548 | "Expected saturation width smaller than result width")((SatWidth <= DstWidth && "Expected saturation width smaller than result width" ) ? static_cast<void> (0) : __assert_fail ("SatWidth <= DstWidth && \"Expected saturation width smaller than result width\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 8548, __PRETTY_FUNCTION__)); | ||||||
8549 | |||||||
8550 | // Determine minimum and maximum integer values and their corresponding | ||||||
8551 | // floating-point values. | ||||||
8552 | APInt MinInt, MaxInt; | ||||||
8553 | if (IsSigned) { | ||||||
8554 | MinInt = APInt::getSignedMinValue(SatWidth).sextOrSelf(DstWidth); | ||||||
8555 | MaxInt = APInt::getSignedMaxValue(SatWidth).sextOrSelf(DstWidth); | ||||||
8556 | } else { | ||||||
8557 | MinInt = APInt::getMinValue(SatWidth).zextOrSelf(DstWidth); | ||||||
8558 | MaxInt = APInt::getMaxValue(SatWidth).zextOrSelf(DstWidth); | ||||||
8559 | } | ||||||
8560 | |||||||
8561 | // We cannot risk emitting FP_TO_XINT nodes with a source VT of f16, as | ||||||
8562 | // libcall emission cannot handle this. Large result types will fail. | ||||||
8563 | if (SrcVT == MVT::f16) { | ||||||
8564 | Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f32, Src); | ||||||
8565 | SrcVT = Src.getValueType(); | ||||||
8566 | } | ||||||
8567 | |||||||
8568 | APFloat MinFloat(DAG.EVTToAPFloatSemantics(SrcVT)); | ||||||
8569 | APFloat MaxFloat(DAG.EVTToAPFloatSemantics(SrcVT)); | ||||||
8570 | |||||||
8571 | APFloat::opStatus MinStatus = | ||||||
8572 | MinFloat.convertFromAPInt(MinInt, IsSigned, APFloat::rmTowardZero); | ||||||
8573 | APFloat::opStatus MaxStatus = | ||||||
8574 | MaxFloat.convertFromAPInt(MaxInt, IsSigned, APFloat::rmTowardZero); | ||||||
8575 | bool AreExactFloatBounds = !(MinStatus & APFloat::opStatus::opInexact) && | ||||||
8576 | !(MaxStatus & APFloat::opStatus::opInexact); | ||||||
8577 | |||||||
8578 | SDValue MinFloatNode = DAG.getConstantFP(MinFloat, dl, SrcVT); | ||||||
8579 | SDValue MaxFloatNode = DAG.getConstantFP(MaxFloat, dl, SrcVT); | ||||||
8580 | |||||||
8581 | // If the integer bounds are exactly representable as floats and min/max are | ||||||
8582 | // legal, emit a min+max+fptoi sequence. Otherwise we have to use a sequence | ||||||
8583 | // of comparisons and selects. | ||||||
8584 | bool MinMaxLegal = isOperationLegal(ISD::FMINNUM, SrcVT) && | ||||||
8585 | isOperationLegal(ISD::FMAXNUM, SrcVT); | ||||||
8586 | if (AreExactFloatBounds && MinMaxLegal) { | ||||||
8587 | SDValue Clamped = Src; | ||||||
8588 | |||||||
8589 | // Clamp Src by MinFloat from below. If Src is NaN the result is MinFloat. | ||||||
8590 | Clamped = DAG.getNode(ISD::FMAXNUM, dl, SrcVT, Clamped, MinFloatNode); | ||||||
8591 | // Clamp by MaxFloat from above. NaN cannot occur. | ||||||
8592 | Clamped = DAG.getNode(ISD::FMINNUM, dl, SrcVT, Clamped, MaxFloatNode); | ||||||
8593 | // Convert clamped value to integer. | ||||||
8594 | SDValue FpToInt = DAG.getNode(IsSigned ? ISD::FP_TO_SINT : ISD::FP_TO_UINT, | ||||||
8595 | dl, DstVT, Clamped); | ||||||
8596 | |||||||
8597 | // In the unsigned case we're done, because we mapped NaN to MinFloat, | ||||||
8598 | // which will cast to zero. | ||||||
8599 | if (!IsSigned) | ||||||
8600 | return FpToInt; | ||||||
8601 | |||||||
8602 | // Otherwise, select 0 if Src is NaN. | ||||||
8603 | SDValue ZeroInt = DAG.getConstant(0, dl, DstVT); | ||||||
8604 | return DAG.getSelectCC(dl, Src, Src, ZeroInt, FpToInt, | ||||||
8605 | ISD::CondCode::SETUO); | ||||||
8606 | } | ||||||
8607 | |||||||
8608 | SDValue MinIntNode = DAG.getConstant(MinInt, dl, DstVT); | ||||||
8609 | SDValue MaxIntNode = DAG.getConstant(MaxInt, dl, DstVT); | ||||||
8610 | |||||||
8611 | // Result of direct conversion. The assumption here is that the operation is | ||||||
8612 | // non-trapping and it's fine to apply it to an out-of-range value if we | ||||||
8613 | // select it away later. | ||||||
8614 | SDValue FpToInt = | ||||||
8615 | DAG.getNode(IsSigned ? ISD::FP_TO_SINT : ISD::FP_TO_UINT, dl, DstVT, Src); | ||||||
8616 | |||||||
8617 | SDValue Select = FpToInt; | ||||||
8618 | |||||||
8619 | // If Src ULT MinFloat, select MinInt. In particular, this also selects | ||||||
8620 | // MinInt if Src is NaN. | ||||||
8621 | Select = DAG.getSelectCC(dl, Src, MinFloatNode, MinIntNode, Select, | ||||||
8622 | ISD::CondCode::SETULT); | ||||||
8623 | // If Src OGT MaxFloat, select MaxInt. | ||||||
8624 | Select = DAG.getSelectCC(dl, Src, MaxFloatNode, MaxIntNode, Select, | ||||||
8625 | ISD::CondCode::SETOGT); | ||||||
8626 | |||||||
8627 | // In the unsigned case we are done, because we mapped NaN to MinInt, which | ||||||
8628 | // is already zero. | ||||||
8629 | if (!IsSigned) | ||||||
8630 | return Select; | ||||||
8631 | |||||||
8632 | // Otherwise, select 0 if Src is NaN. | ||||||
8633 | SDValue ZeroInt = DAG.getConstant(0, dl, DstVT); | ||||||
8634 | return DAG.getSelectCC(dl, Src, Src, ZeroInt, Select, ISD::CondCode::SETUO); | ||||||
8635 | } | ||||||
8636 | |||||||
8637 | SDValue TargetLowering::expandVectorSplice(SDNode *Node, | ||||||
8638 | SelectionDAG &DAG) const { | ||||||
8639 | assert(Node->getOpcode() == ISD::VECTOR_SPLICE && "Unexpected opcode!")((Node->getOpcode() == ISD::VECTOR_SPLICE && "Unexpected opcode!" ) ? static_cast<void> (0) : __assert_fail ("Node->getOpcode() == ISD::VECTOR_SPLICE && \"Unexpected opcode!\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 8639, __PRETTY_FUNCTION__)); | ||||||
8640 | assert(Node->getValueType(0).isScalableVector() &&((Node->getValueType(0).isScalableVector() && "Fixed length vector types expected to use SHUFFLE_VECTOR!" ) ? static_cast<void> (0) : __assert_fail ("Node->getValueType(0).isScalableVector() && \"Fixed length vector types expected to use SHUFFLE_VECTOR!\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 8641, __PRETTY_FUNCTION__)) | ||||||
8641 | "Fixed length vector types expected to use SHUFFLE_VECTOR!")((Node->getValueType(0).isScalableVector() && "Fixed length vector types expected to use SHUFFLE_VECTOR!" ) ? static_cast<void> (0) : __assert_fail ("Node->getValueType(0).isScalableVector() && \"Fixed length vector types expected to use SHUFFLE_VECTOR!\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 8641, __PRETTY_FUNCTION__)); | ||||||
8642 | |||||||
8643 | EVT VT = Node->getValueType(0); | ||||||
8644 | SDValue V1 = Node->getOperand(0); | ||||||
8645 | SDValue V2 = Node->getOperand(1); | ||||||
8646 | int64_t Imm = cast<ConstantSDNode>(Node->getOperand(2))->getSExtValue(); | ||||||
8647 | SDLoc DL(Node); | ||||||
8648 | |||||||
8649 | // Expand through memory thusly: | ||||||
8650 | // Alloca CONCAT_VECTORS_TYPES(V1, V2) Ptr | ||||||
8651 | // Store V1, Ptr | ||||||
8652 | // Store V2, Ptr + sizeof(V1) | ||||||
8653 | // If (Imm < 0) | ||||||
8654 | // TrailingElts = -Imm | ||||||
8655 | // Ptr = Ptr + sizeof(V1) - (TrailingElts * sizeof(VT.Elt)) | ||||||
8656 | // else | ||||||
8657 | // Ptr = Ptr + (Imm * sizeof(VT.Elt)) | ||||||
8658 | // Res = Load Ptr | ||||||
8659 | |||||||
8660 | Align Alignment = DAG.getReducedAlign(VT, /*UseABI=*/false); | ||||||
8661 | |||||||
8662 | EVT MemVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(), | ||||||
8663 | VT.getVectorElementCount() * 2); | ||||||
8664 | SDValue StackPtr = DAG.CreateStackTemporary(MemVT.getStoreSize(), Alignment); | ||||||
8665 | EVT PtrVT = StackPtr.getValueType(); | ||||||
8666 | auto &MF = DAG.getMachineFunction(); | ||||||
8667 | auto FrameIndex = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex(); | ||||||
8668 | auto PtrInfo = MachinePointerInfo::getFixedStack(MF, FrameIndex); | ||||||
8669 | |||||||
8670 | // Store the lo part of CONCAT_VECTORS(V1, V2) | ||||||
8671 | SDValue StoreV1 = DAG.getStore(DAG.getEntryNode(), DL, V1, StackPtr, PtrInfo); | ||||||
8672 | // Store the hi part of CONCAT_VECTORS(V1, V2) | ||||||
8673 | SDValue OffsetToV2 = DAG.getVScale( | ||||||
8674 | DL, PtrVT, | ||||||
8675 | APInt(PtrVT.getFixedSizeInBits(), VT.getStoreSize().getKnownMinSize())); | ||||||
8676 | SDValue StackPtr2 = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr, OffsetToV2); | ||||||
8677 | SDValue StoreV2 = DAG.getStore(StoreV1, DL, V2, StackPtr2, PtrInfo); | ||||||
8678 | |||||||
8679 | if (Imm >= 0) { | ||||||
8680 | // Load back the required element. getVectorElementPointer takes care of | ||||||
8681 | // clamping the index if it's out-of-bounds. | ||||||
8682 | StackPtr = getVectorElementPointer(DAG, StackPtr, VT, Node->getOperand(2)); | ||||||
8683 | // Load the spliced result | ||||||
8684 | return DAG.getLoad(VT, DL, StoreV2, StackPtr, | ||||||
8685 | MachinePointerInfo::getUnknownStack(MF)); | ||||||
8686 | } | ||||||
8687 | |||||||
8688 | uint64_t TrailingElts = -Imm; | ||||||
8689 | |||||||
8690 | // NOTE: TrailingElts must be clamped so as not to read outside of V1:V2. | ||||||
8691 | TypeSize EltByteSize = VT.getVectorElementType().getStoreSize(); | ||||||
8692 | SDValue TrailingBytes = | ||||||
8693 | DAG.getConstant(TrailingElts * EltByteSize, DL, PtrVT); | ||||||
8694 | |||||||
8695 | if (TrailingElts > VT.getVectorMinNumElements()) { | ||||||
8696 | SDValue VLBytes = DAG.getVScale( | ||||||
8697 | DL, PtrVT, | ||||||
8698 | APInt(PtrVT.getFixedSizeInBits(), VT.getStoreSize().getKnownMinSize())); | ||||||
8699 | TrailingBytes = DAG.getNode(ISD::UMIN, DL, PtrVT, TrailingBytes, VLBytes); | ||||||
8700 | } | ||||||
8701 | |||||||
8702 | // Calculate the start address of the spliced result. | ||||||
8703 | StackPtr2 = DAG.getNode(ISD::SUB, DL, PtrVT, StackPtr2, TrailingBytes); | ||||||
8704 | |||||||
8705 | // Load the spliced result | ||||||
8706 | return DAG.getLoad(VT, DL, StoreV2, StackPtr2, | ||||||
8707 | MachinePointerInfo::getUnknownStack(MF)); | ||||||
8708 | } | ||||||
8709 | |||||||
8710 | bool TargetLowering::LegalizeSetCCCondCode(SelectionDAG &DAG, EVT VT, | ||||||
8711 | SDValue &LHS, SDValue &RHS, | ||||||
8712 | SDValue &CC, bool &NeedInvert, | ||||||
8713 | const SDLoc &dl, SDValue &Chain, | ||||||
8714 | bool IsSignaling) const { | ||||||
8715 | const TargetLowering &TLI = DAG.getTargetLoweringInfo(); | ||||||
8716 | MVT OpVT = LHS.getSimpleValueType(); | ||||||
8717 | ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get(); | ||||||
8718 | NeedInvert = false; | ||||||
8719 | switch (TLI.getCondCodeAction(CCCode, OpVT)) { | ||||||
8720 | default: | ||||||
8721 | llvm_unreachable("Unknown condition code action!")::llvm::llvm_unreachable_internal("Unknown condition code action!" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 8721); | ||||||
8722 | case TargetLowering::Legal: | ||||||
8723 | // Nothing to do. | ||||||
8724 | break; | ||||||
8725 | case TargetLowering::Expand: { | ||||||
8726 | ISD::CondCode InvCC = ISD::getSetCCSwappedOperands(CCCode); | ||||||
8727 | if (TLI.isCondCodeLegalOrCustom(InvCC, OpVT)) { | ||||||
8728 | std::swap(LHS, RHS); | ||||||
8729 | CC = DAG.getCondCode(InvCC); | ||||||
8730 | return true; | ||||||
8731 | } | ||||||
8732 | // Swapping operands didn't work. Try inverting the condition. | ||||||
8733 | bool NeedSwap = false; | ||||||
8734 | InvCC = getSetCCInverse(CCCode, OpVT); | ||||||
8735 | if (!TLI.isCondCodeLegalOrCustom(InvCC, OpVT)) { | ||||||
8736 | // If inverting the condition is not enough, try swapping operands | ||||||
8737 | // on top of it. | ||||||
8738 | InvCC = ISD::getSetCCSwappedOperands(InvCC); | ||||||
8739 | NeedSwap = true; | ||||||
8740 | } | ||||||
8741 | if (TLI.isCondCodeLegalOrCustom(InvCC, OpVT)) { | ||||||
8742 | CC = DAG.getCondCode(InvCC); | ||||||
8743 | NeedInvert = true; | ||||||
8744 | if (NeedSwap) | ||||||
8745 | std::swap(LHS, RHS); | ||||||
8746 | return true; | ||||||
8747 | } | ||||||
8748 | |||||||
8749 | ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID; | ||||||
8750 | unsigned Opc = 0; | ||||||
8751 | switch (CCCode) { | ||||||
8752 | default: | ||||||
8753 | llvm_unreachable("Don't know how to expand this condition!")::llvm::llvm_unreachable_internal("Don't know how to expand this condition!" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 8753); | ||||||
8754 | case ISD::SETUO: | ||||||
8755 | if (TLI.isCondCodeLegal(ISD::SETUNE, OpVT)) { | ||||||
8756 | CC1 = ISD::SETUNE; | ||||||
8757 | CC2 = ISD::SETUNE; | ||||||
8758 | Opc = ISD::OR; | ||||||
8759 | break; | ||||||
8760 | } | ||||||
8761 | assert(TLI.isCondCodeLegal(ISD::SETOEQ, OpVT) &&((TLI.isCondCodeLegal(ISD::SETOEQ, OpVT) && "If SETUE is expanded, SETOEQ or SETUNE must be legal!" ) ? static_cast<void> (0) : __assert_fail ("TLI.isCondCodeLegal(ISD::SETOEQ, OpVT) && \"If SETUE is expanded, SETOEQ or SETUNE must be legal!\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 8762, __PRETTY_FUNCTION__)) | ||||||
8762 | "If SETUE is expanded, SETOEQ or SETUNE must be legal!")((TLI.isCondCodeLegal(ISD::SETOEQ, OpVT) && "If SETUE is expanded, SETOEQ or SETUNE must be legal!" ) ? static_cast<void> (0) : __assert_fail ("TLI.isCondCodeLegal(ISD::SETOEQ, OpVT) && \"If SETUE is expanded, SETOEQ or SETUNE must be legal!\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 8762, __PRETTY_FUNCTION__)); | ||||||
8763 | NeedInvert = true; | ||||||
8764 | LLVM_FALLTHROUGH[[gnu::fallthrough]]; | ||||||
8765 | case ISD::SETO: | ||||||
8766 | assert(TLI.isCondCodeLegal(ISD::SETOEQ, OpVT) &&((TLI.isCondCodeLegal(ISD::SETOEQ, OpVT) && "If SETO is expanded, SETOEQ must be legal!" ) ? static_cast<void> (0) : __assert_fail ("TLI.isCondCodeLegal(ISD::SETOEQ, OpVT) && \"If SETO is expanded, SETOEQ must be legal!\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 8767, __PRETTY_FUNCTION__)) | ||||||
8767 | "If SETO is expanded, SETOEQ must be legal!")((TLI.isCondCodeLegal(ISD::SETOEQ, OpVT) && "If SETO is expanded, SETOEQ must be legal!" ) ? static_cast<void> (0) : __assert_fail ("TLI.isCondCodeLegal(ISD::SETOEQ, OpVT) && \"If SETO is expanded, SETOEQ must be legal!\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 8767, __PRETTY_FUNCTION__)); | ||||||
8768 | CC1 = ISD::SETOEQ; | ||||||
8769 | CC2 = ISD::SETOEQ; | ||||||
8770 | Opc = ISD::AND; | ||||||
8771 | break; | ||||||
8772 | case ISD::SETONE: | ||||||
8773 | case ISD::SETUEQ: | ||||||
8774 | // If the SETUO or SETO CC isn't legal, we might be able to use | ||||||
8775 | // SETOGT || SETOLT, inverting the result for SETUEQ. We only need one | ||||||
8776 | // of SETOGT/SETOLT to be legal, the other can be emulated by swapping | ||||||
8777 | // the operands. | ||||||
8778 | CC2 = ((unsigned)CCCode & 0x8U) ? ISD::SETUO : ISD::SETO; | ||||||
8779 | if (!TLI.isCondCodeLegal(CC2, OpVT) && | ||||||
8780 | (TLI.isCondCodeLegal(ISD::SETOGT, OpVT) || | ||||||
8781 | TLI.isCondCodeLegal(ISD::SETOLT, OpVT))) { | ||||||
8782 | CC1 = ISD::SETOGT; | ||||||
8783 | CC2 = ISD::SETOLT; | ||||||
8784 | Opc = ISD::OR; | ||||||
8785 | NeedInvert = ((unsigned)CCCode & 0x8U); | ||||||
8786 | break; | ||||||
8787 | } | ||||||
8788 | LLVM_FALLTHROUGH[[gnu::fallthrough]]; | ||||||
8789 | case ISD::SETOEQ: | ||||||
8790 | case ISD::SETOGT: | ||||||
8791 | case ISD::SETOGE: | ||||||
8792 | case ISD::SETOLT: | ||||||
8793 | case ISD::SETOLE: | ||||||
8794 | case ISD::SETUNE: | ||||||
8795 | case ISD::SETUGT: | ||||||
8796 | case ISD::SETUGE: | ||||||
8797 | case ISD::SETULT: | ||||||
8798 | case ISD::SETULE: | ||||||
8799 | // If we are floating point, assign and break, otherwise fall through. | ||||||
8800 | if (!OpVT.isInteger()) { | ||||||
8801 | // We can use the 4th bit to tell if we are the unordered | ||||||
8802 | // or ordered version of the opcode. | ||||||
8803 | CC2 = ((unsigned)CCCode & 0x8U) ? ISD::SETUO : ISD::SETO; | ||||||
8804 | Opc = ((unsigned)CCCode & 0x8U) ? ISD::OR : ISD::AND; | ||||||
8805 | CC1 = (ISD::CondCode)(((int)CCCode & 0x7) | 0x10); | ||||||
8806 | break; | ||||||
8807 | } | ||||||
8808 | // Fallthrough if we are unsigned integer. | ||||||
8809 | LLVM_FALLTHROUGH[[gnu::fallthrough]]; | ||||||
8810 | case ISD::SETLE: | ||||||
8811 | case ISD::SETGT: | ||||||
8812 | case ISD::SETGE: | ||||||
8813 | case ISD::SETLT: | ||||||
8814 | case ISD::SETNE: | ||||||
8815 | case ISD::SETEQ: | ||||||
8816 | // If all combinations of inverting the condition and swapping operands | ||||||
8817 | // didn't work then we have no means to expand the condition. | ||||||
8818 | llvm_unreachable("Don't know how to expand this condition!")::llvm::llvm_unreachable_internal("Don't know how to expand this condition!" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 8818); | ||||||
8819 | } | ||||||
8820 | |||||||
8821 | SDValue SetCC1, SetCC2; | ||||||
8822 | if (CCCode != ISD::SETO && CCCode != ISD::SETUO) { | ||||||
8823 | // If we aren't the ordered or unorder operation, | ||||||
8824 | // then the pattern is (LHS CC1 RHS) Opc (LHS CC2 RHS). | ||||||
8825 | SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1, Chain, IsSignaling); | ||||||
8826 | SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2, Chain, IsSignaling); | ||||||
8827 | } else { | ||||||
8828 | // Otherwise, the pattern is (LHS CC1 LHS) Opc (RHS CC2 RHS) | ||||||
8829 | SetCC1 = DAG.getSetCC(dl, VT, LHS, LHS, CC1, Chain, IsSignaling); | ||||||
8830 | SetCC2 = DAG.getSetCC(dl, VT, RHS, RHS, CC2, Chain, IsSignaling); | ||||||
8831 | } | ||||||
8832 | if (Chain) | ||||||
8833 | Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, SetCC1.getValue(1), | ||||||
8834 | SetCC2.getValue(1)); | ||||||
8835 | LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2); | ||||||
8836 | RHS = SDValue(); | ||||||
8837 | CC = SDValue(); | ||||||
8838 | return true; | ||||||
8839 | } | ||||||
8840 | } | ||||||
8841 | return false; | ||||||
8842 | } |
1 | //===- llvm/CodeGen/SelectionDAG.h - InstSelection DAG ----------*- C++ -*-===// |
2 | // |
3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
4 | // See https://llvm.org/LICENSE.txt for license information. |
5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
6 | // |
7 | //===----------------------------------------------------------------------===// |
8 | // |
9 | // This file declares the SelectionDAG class, and transitively defines the |
10 | // SDNode class and subclasses. |
11 | // |
12 | //===----------------------------------------------------------------------===// |
13 | |
14 | #ifndef LLVM_CODEGEN_SELECTIONDAG_H |
15 | #define LLVM_CODEGEN_SELECTIONDAG_H |
16 | |
17 | #include "llvm/ADT/APFloat.h" |
18 | #include "llvm/ADT/APInt.h" |
19 | #include "llvm/ADT/ArrayRef.h" |
20 | #include "llvm/ADT/DenseMap.h" |
21 | #include "llvm/ADT/DenseSet.h" |
22 | #include "llvm/ADT/FoldingSet.h" |
23 | #include "llvm/ADT/SetVector.h" |
24 | #include "llvm/ADT/SmallVector.h" |
25 | #include "llvm/ADT/StringMap.h" |
26 | #include "llvm/ADT/ilist.h" |
27 | #include "llvm/ADT/iterator.h" |
28 | #include "llvm/ADT/iterator_range.h" |
29 | #include "llvm/CodeGen/DAGCombine.h" |
30 | #include "llvm/CodeGen/ISDOpcodes.h" |
31 | #include "llvm/CodeGen/MachineFunction.h" |
32 | #include "llvm/CodeGen/MachineMemOperand.h" |
33 | #include "llvm/CodeGen/SelectionDAGNodes.h" |
34 | #include "llvm/CodeGen/ValueTypes.h" |
35 | #include "llvm/IR/DebugLoc.h" |
36 | #include "llvm/IR/Instructions.h" |
37 | #include "llvm/IR/Metadata.h" |
38 | #include "llvm/Support/Allocator.h" |
39 | #include "llvm/Support/ArrayRecycler.h" |
40 | #include "llvm/Support/AtomicOrdering.h" |
41 | #include "llvm/Support/Casting.h" |
42 | #include "llvm/Support/CodeGen.h" |
43 | #include "llvm/Support/ErrorHandling.h" |
44 | #include "llvm/Support/MachineValueType.h" |
45 | #include "llvm/Support/RecyclingAllocator.h" |
46 | #include <algorithm> |
47 | #include <cassert> |
48 | #include <cstdint> |
49 | #include <functional> |
50 | #include <map> |
51 | #include <string> |
52 | #include <tuple> |
53 | #include <utility> |
54 | #include <vector> |
55 | |
56 | namespace llvm { |
57 | |
58 | class AAResults; |
59 | class BlockAddress; |
60 | class BlockFrequencyInfo; |
61 | class Constant; |
62 | class ConstantFP; |
63 | class ConstantInt; |
64 | class DataLayout; |
65 | struct fltSemantics; |
66 | class FunctionLoweringInfo; |
67 | class GlobalValue; |
68 | struct KnownBits; |
69 | class LegacyDivergenceAnalysis; |
70 | class LLVMContext; |
71 | class MachineBasicBlock; |
72 | class MachineConstantPoolValue; |
73 | class MCSymbol; |
74 | class OptimizationRemarkEmitter; |
75 | class ProfileSummaryInfo; |
76 | class SDDbgValue; |
77 | class SDDbgOperand; |
78 | class SDDbgLabel; |
79 | class SelectionDAG; |
80 | class SelectionDAGTargetInfo; |
81 | class TargetLibraryInfo; |
82 | class TargetLowering; |
83 | class TargetMachine; |
84 | class TargetSubtargetInfo; |
85 | class Value; |
86 | |
87 | class SDVTListNode : public FoldingSetNode { |
88 | friend struct FoldingSetTrait<SDVTListNode>; |
89 | |
90 | /// A reference to an Interned FoldingSetNodeID for this node. |
91 | /// The Allocator in SelectionDAG holds the data. |
92 | /// SDVTList contains all types which are frequently accessed in SelectionDAG. |
93 | /// The size of this list is not expected to be big so it won't introduce |
94 | /// a memory penalty. |
95 | FoldingSetNodeIDRef FastID; |
96 | const EVT *VTs; |
97 | unsigned int NumVTs; |
98 | /// The hash value for SDVTList is fixed, so cache it to avoid |
99 | /// hash calculation. |
100 | unsigned HashValue; |
101 | |
102 | public: |
103 | SDVTListNode(const FoldingSetNodeIDRef ID, const EVT *VT, unsigned int Num) : |
104 | FastID(ID), VTs(VT), NumVTs(Num) { |
105 | HashValue = ID.ComputeHash(); |
106 | } |
107 | |
108 | SDVTList getSDVTList() { |
109 | SDVTList result = {VTs, NumVTs}; |
110 | return result; |
111 | } |
112 | }; |
113 | |
114 | /// Specialize FoldingSetTrait for SDVTListNode |
115 | /// to avoid computing temp FoldingSetNodeID and hash value. |
116 | template<> struct FoldingSetTrait<SDVTListNode> : DefaultFoldingSetTrait<SDVTListNode> { |
117 | static void Profile(const SDVTListNode &X, FoldingSetNodeID& ID) { |
118 | ID = X.FastID; |
119 | } |
120 | |
121 | static bool Equals(const SDVTListNode &X, const FoldingSetNodeID &ID, |
122 | unsigned IDHash, FoldingSetNodeID &TempID) { |
123 | if (X.HashValue != IDHash) |
124 | return false; |
125 | return ID == X.FastID; |
126 | } |
127 | |
128 | static unsigned ComputeHash(const SDVTListNode &X, FoldingSetNodeID &TempID) { |
129 | return X.HashValue; |
130 | } |
131 | }; |
132 | |
133 | template <> struct ilist_alloc_traits<SDNode> { |
134 | static void deleteNode(SDNode *) { |
135 | llvm_unreachable("ilist_traits<SDNode> shouldn't see a deleteNode call!")::llvm::llvm_unreachable_internal("ilist_traits<SDNode> shouldn't see a deleteNode call!" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/CodeGen/SelectionDAG.h" , 135); |
136 | } |
137 | }; |
138 | |
139 | /// Keeps track of dbg_value information through SDISel. We do |
140 | /// not build SDNodes for these so as not to perturb the generated code; |
141 | /// instead the info is kept off to the side in this structure. Each SDNode may |
142 | /// have one or more associated dbg_value entries. This information is kept in |
143 | /// DbgValMap. |
144 | /// Byval parameters are handled separately because they don't use alloca's, |
145 | /// which busts the normal mechanism. There is good reason for handling all |
146 | /// parameters separately: they may not have code generated for them, they |
147 | /// should always go at the beginning of the function regardless of other code |
148 | /// motion, and debug info for them is potentially useful even if the parameter |
149 | /// is unused. Right now only byval parameters are handled separately. |
150 | class SDDbgInfo { |
151 | BumpPtrAllocator Alloc; |
152 | SmallVector<SDDbgValue*, 32> DbgValues; |
153 | SmallVector<SDDbgValue*, 32> ByvalParmDbgValues; |
154 | SmallVector<SDDbgLabel*, 4> DbgLabels; |
155 | using DbgValMapType = DenseMap<const SDNode *, SmallVector<SDDbgValue *, 2>>; |
156 | DbgValMapType DbgValMap; |
157 | |
158 | public: |
159 | SDDbgInfo() = default; |
160 | SDDbgInfo(const SDDbgInfo &) = delete; |
161 | SDDbgInfo &operator=(const SDDbgInfo &) = delete; |
162 | |
163 | void add(SDDbgValue *V, bool isParameter); |
164 | |
165 | void add(SDDbgLabel *L) { DbgLabels.push_back(L); } |
166 | |
167 | /// Invalidate all DbgValues attached to the node and remove |
168 | /// it from the Node-to-DbgValues map. |
169 | void erase(const SDNode *Node); |
170 | |
171 | void clear() { |
172 | DbgValMap.clear(); |
173 | DbgValues.clear(); |
174 | ByvalParmDbgValues.clear(); |
175 | DbgLabels.clear(); |
176 | Alloc.Reset(); |
177 | } |
178 | |
179 | BumpPtrAllocator &getAlloc() { return Alloc; } |
180 | |
181 | bool empty() const { |
182 | return DbgValues.empty() && ByvalParmDbgValues.empty() && DbgLabels.empty(); |
183 | } |
184 | |
185 | ArrayRef<SDDbgValue*> getSDDbgValues(const SDNode *Node) const { |
186 | auto I = DbgValMap.find(Node); |
187 | if (I != DbgValMap.end()) |
188 | return I->second; |
189 | return ArrayRef<SDDbgValue*>(); |
190 | } |
191 | |
192 | using DbgIterator = SmallVectorImpl<SDDbgValue*>::iterator; |
193 | using DbgLabelIterator = SmallVectorImpl<SDDbgLabel*>::iterator; |
194 | |
195 | DbgIterator DbgBegin() { return DbgValues.begin(); } |
196 | DbgIterator DbgEnd() { return DbgValues.end(); } |
197 | DbgIterator ByvalParmDbgBegin() { return ByvalParmDbgValues.begin(); } |
198 | DbgIterator ByvalParmDbgEnd() { return ByvalParmDbgValues.end(); } |
199 | DbgLabelIterator DbgLabelBegin() { return DbgLabels.begin(); } |
200 | DbgLabelIterator DbgLabelEnd() { return DbgLabels.end(); } |
201 | }; |
202 | |
203 | void checkForCycles(const SelectionDAG *DAG, bool force = false); |
204 | |
205 | /// This is used to represent a portion of an LLVM function in a low-level |
206 | /// Data Dependence DAG representation suitable for instruction selection. |
207 | /// This DAG is constructed as the first step of instruction selection in order |
208 | /// to allow implementation of machine specific optimizations |
209 | /// and code simplifications. |
210 | /// |
211 | /// The representation used by the SelectionDAG is a target-independent |
212 | /// representation, which has some similarities to the GCC RTL representation, |
213 | /// but is significantly more simple, powerful, and is a graph form instead of a |
214 | /// linear form. |
215 | /// |
216 | class SelectionDAG { |
217 | const TargetMachine &TM; |
218 | const SelectionDAGTargetInfo *TSI = nullptr; |
219 | const TargetLowering *TLI = nullptr; |
220 | const TargetLibraryInfo *LibInfo = nullptr; |
221 | MachineFunction *MF; |
222 | Pass *SDAGISelPass = nullptr; |
223 | LLVMContext *Context; |
224 | CodeGenOpt::Level OptLevel; |
225 | |
226 | LegacyDivergenceAnalysis * DA = nullptr; |
227 | FunctionLoweringInfo * FLI = nullptr; |
228 | |
229 | /// The function-level optimization remark emitter. Used to emit remarks |
230 | /// whenever manipulating the DAG. |
231 | OptimizationRemarkEmitter *ORE; |
232 | |
233 | ProfileSummaryInfo *PSI = nullptr; |
234 | BlockFrequencyInfo *BFI = nullptr; |
235 | |
236 | /// The starting token. |
237 | SDNode EntryNode; |
238 | |
239 | /// The root of the entire DAG. |
240 | SDValue Root; |
241 | |
242 | /// A linked list of nodes in the current DAG. |
243 | ilist<SDNode> AllNodes; |
244 | |
245 | /// The AllocatorType for allocating SDNodes. We use |
246 | /// pool allocation with recycling. |
247 | using NodeAllocatorType = RecyclingAllocator<BumpPtrAllocator, SDNode, |
248 | sizeof(LargestSDNode), |
249 | alignof(MostAlignedSDNode)>; |
250 | |
251 | /// Pool allocation for nodes. |
252 | NodeAllocatorType NodeAllocator; |
253 | |
254 | /// This structure is used to memoize nodes, automatically performing |
255 | /// CSE with existing nodes when a duplicate is requested. |
256 | FoldingSet<SDNode> CSEMap; |
257 | |
258 | /// Pool allocation for machine-opcode SDNode operands. |
259 | BumpPtrAllocator OperandAllocator; |
260 | ArrayRecycler<SDUse> OperandRecycler; |
261 | |
262 | /// Pool allocation for misc. objects that are created once per SelectionDAG. |
263 | BumpPtrAllocator Allocator; |
264 | |
265 | /// Tracks dbg_value and dbg_label information through SDISel. |
266 | SDDbgInfo *DbgInfo; |
267 | |
268 | using CallSiteInfo = MachineFunction::CallSiteInfo; |
269 | using CallSiteInfoImpl = MachineFunction::CallSiteInfoImpl; |
270 | |
271 | struct CallSiteDbgInfo { |
272 | CallSiteInfo CSInfo; |
273 | MDNode *HeapAllocSite = nullptr; |
274 | bool NoMerge = false; |
275 | }; |
276 | |
277 | DenseMap<const SDNode *, CallSiteDbgInfo> SDCallSiteDbgInfo; |
278 | |
279 | uint16_t NextPersistentId = 0; |
280 | |
281 | public: |
282 | /// Clients of various APIs that cause global effects on |
283 | /// the DAG can optionally implement this interface. This allows the clients |
284 | /// to handle the various sorts of updates that happen. |
285 | /// |
286 | /// A DAGUpdateListener automatically registers itself with DAG when it is |
287 | /// constructed, and removes itself when destroyed in RAII fashion. |
288 | struct DAGUpdateListener { |
289 | DAGUpdateListener *const Next; |
290 | SelectionDAG &DAG; |
291 | |
292 | explicit DAGUpdateListener(SelectionDAG &D) |
293 | : Next(D.UpdateListeners), DAG(D) { |
294 | DAG.UpdateListeners = this; |
295 | } |
296 | |
297 | virtual ~DAGUpdateListener() { |
298 | assert(DAG.UpdateListeners == this &&((DAG.UpdateListeners == this && "DAGUpdateListeners must be destroyed in LIFO order" ) ? static_cast<void> (0) : __assert_fail ("DAG.UpdateListeners == this && \"DAGUpdateListeners must be destroyed in LIFO order\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/CodeGen/SelectionDAG.h" , 299, __PRETTY_FUNCTION__)) |
299 | "DAGUpdateListeners must be destroyed in LIFO order")((DAG.UpdateListeners == this && "DAGUpdateListeners must be destroyed in LIFO order" ) ? static_cast<void> (0) : __assert_fail ("DAG.UpdateListeners == this && \"DAGUpdateListeners must be destroyed in LIFO order\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/CodeGen/SelectionDAG.h" , 299, __PRETTY_FUNCTION__)); |
300 | DAG.UpdateListeners = Next; |
301 | } |
302 | |
303 | /// The node N that was deleted and, if E is not null, an |
304 | /// equivalent node E that replaced it. |
305 | virtual void NodeDeleted(SDNode *N, SDNode *E); |
306 | |
307 | /// The node N that was updated. |
308 | virtual void NodeUpdated(SDNode *N); |
309 | |
310 | /// The node N that was inserted. |
311 | virtual void NodeInserted(SDNode *N); |
312 | }; |
313 | |
314 | struct DAGNodeDeletedListener : public DAGUpdateListener { |
315 | std::function<void(SDNode *, SDNode *)> Callback; |
316 | |
317 | DAGNodeDeletedListener(SelectionDAG &DAG, |
318 | std::function<void(SDNode *, SDNode *)> Callback) |
319 | : DAGUpdateListener(DAG), Callback(std::move(Callback)) {} |
320 | |
321 | void NodeDeleted(SDNode *N, SDNode *E) override { Callback(N, E); } |
322 | |
323 | private: |
324 | virtual void anchor(); |
325 | }; |
326 | |
327 | /// Help to insert SDNodeFlags automatically in transforming. Use |
328 | /// RAII to save and resume flags in current scope. |
329 | class FlagInserter { |
330 | SelectionDAG &DAG; |
331 | SDNodeFlags Flags; |
332 | FlagInserter *LastInserter; |
333 | |
334 | public: |
335 | FlagInserter(SelectionDAG &SDAG, SDNodeFlags Flags) |
336 | : DAG(SDAG), Flags(Flags), |
337 | LastInserter(SDAG.getFlagInserter()) { |
338 | SDAG.setFlagInserter(this); |
339 | } |
340 | FlagInserter(SelectionDAG &SDAG, SDNode *N) |
341 | : FlagInserter(SDAG, N->getFlags()) {} |
342 | |
343 | FlagInserter(const FlagInserter &) = delete; |
344 | FlagInserter &operator=(const FlagInserter &) = delete; |
345 | ~FlagInserter() { DAG.setFlagInserter(LastInserter); } |
346 | |
347 | SDNodeFlags getFlags() const { return Flags; } |
348 | }; |
349 | |
350 | /// When true, additional steps are taken to |
351 | /// ensure that getConstant() and similar functions return DAG nodes that |
352 | /// have legal types. This is important after type legalization since |
353 | /// any illegally typed nodes generated after this point will not experience |
354 | /// type legalization. |
355 | bool NewNodesMustHaveLegalTypes = false; |
356 | |
357 | private: |
358 | /// DAGUpdateListener is a friend so it can manipulate the listener stack. |
359 | friend struct DAGUpdateListener; |
360 | |
361 | /// Linked list of registered DAGUpdateListener instances. |
362 | /// This stack is maintained by DAGUpdateListener RAII. |
363 | DAGUpdateListener *UpdateListeners = nullptr; |
364 | |
365 | /// Implementation of setSubgraphColor. |
366 | /// Return whether we had to truncate the search. |
367 | bool setSubgraphColorHelper(SDNode *N, const char *Color, |
368 | DenseSet<SDNode *> &visited, |
369 | int level, bool &printed); |
370 | |
371 | template <typename SDNodeT, typename... ArgTypes> |
372 | SDNodeT *newSDNode(ArgTypes &&... Args) { |
373 | return new (NodeAllocator.template Allocate<SDNodeT>()) |
374 | SDNodeT(std::forward<ArgTypes>(Args)...); |
375 | } |
376 | |
377 | /// Build a synthetic SDNodeT with the given args and extract its subclass |
378 | /// data as an integer (e.g. for use in a folding set). |
379 | /// |
380 | /// The args to this function are the same as the args to SDNodeT's |
381 | /// constructor, except the second arg (assumed to be a const DebugLoc&) is |
382 | /// omitted. |
383 | template <typename SDNodeT, typename... ArgTypes> |
384 | static uint16_t getSyntheticNodeSubclassData(unsigned IROrder, |
385 | ArgTypes &&... Args) { |
386 | // The compiler can reduce this expression to a constant iff we pass an |
387 | // empty DebugLoc. Thankfully, the debug location doesn't have any bearing |
388 | // on the subclass data. |
389 | return SDNodeT(IROrder, DebugLoc(), std::forward<ArgTypes>(Args)...) |
390 | .getRawSubclassData(); |
391 | } |
392 | |
393 | template <typename SDNodeTy> |
394 | static uint16_t getSyntheticNodeSubclassData(unsigned Opc, unsigned Order, |
395 | SDVTList VTs, EVT MemoryVT, |
396 | MachineMemOperand *MMO) { |
397 | return SDNodeTy(Opc, Order, DebugLoc(), VTs, MemoryVT, MMO) |
398 | .getRawSubclassData(); |
399 | } |
400 | |
401 | void createOperands(SDNode *Node, ArrayRef<SDValue> Vals); |
402 | |
403 | void removeOperands(SDNode *Node) { |
404 | if (!Node->OperandList) |
405 | return; |
406 | OperandRecycler.deallocate( |
407 | ArrayRecycler<SDUse>::Capacity::get(Node->NumOperands), |
408 | Node->OperandList); |
409 | Node->NumOperands = 0; |
410 | Node->OperandList = nullptr; |
411 | } |
412 | void CreateTopologicalOrder(std::vector<SDNode*>& Order); |
413 | |
414 | public: |
415 | // Maximum depth for recursive analysis such as computeKnownBits, etc. |
416 | static constexpr unsigned MaxRecursionDepth = 6; |
417 | |
418 | explicit SelectionDAG(const TargetMachine &TM, CodeGenOpt::Level); |
419 | SelectionDAG(const SelectionDAG &) = delete; |
420 | SelectionDAG &operator=(const SelectionDAG &) = delete; |
421 | ~SelectionDAG(); |
422 | |
423 | /// Prepare this SelectionDAG to process code in the given MachineFunction. |
424 | void init(MachineFunction &NewMF, OptimizationRemarkEmitter &NewORE, |
425 | Pass *PassPtr, const TargetLibraryInfo *LibraryInfo, |
426 | LegacyDivergenceAnalysis * Divergence, |
427 | ProfileSummaryInfo *PSIin, BlockFrequencyInfo *BFIin); |
428 | |
429 | void setFunctionLoweringInfo(FunctionLoweringInfo * FuncInfo) { |
430 | FLI = FuncInfo; |
431 | } |
432 | |
433 | /// Clear state and free memory necessary to make this |
434 | /// SelectionDAG ready to process a new block. |
435 | void clear(); |
436 | |
437 | MachineFunction &getMachineFunction() const { return *MF; } |
438 | const Pass *getPass() const { return SDAGISelPass; } |
439 | |
440 | const DataLayout &getDataLayout() const { return MF->getDataLayout(); } |
441 | const TargetMachine &getTarget() const { return TM; } |
442 | const TargetSubtargetInfo &getSubtarget() const { return MF->getSubtarget(); } |
443 | const TargetLowering &getTargetLoweringInfo() const { return *TLI; } |
444 | const TargetLibraryInfo &getLibInfo() const { return *LibInfo; } |
445 | const SelectionDAGTargetInfo &getSelectionDAGInfo() const { return *TSI; } |
446 | const LegacyDivergenceAnalysis *getDivergenceAnalysis() const { return DA; } |
447 | LLVMContext *getContext() const { return Context; } |
448 | OptimizationRemarkEmitter &getORE() const { return *ORE; } |
449 | ProfileSummaryInfo *getPSI() const { return PSI; } |
450 | BlockFrequencyInfo *getBFI() const { return BFI; } |
451 | |
452 | FlagInserter *getFlagInserter() { return Inserter; } |
453 | void setFlagInserter(FlagInserter *FI) { Inserter = FI; } |
454 | |
455 | /// Just dump dot graph to a user-provided path and title. |
456 | /// This doesn't open the dot viewer program and |
457 | /// helps visualization when outside debugging session. |
458 | /// FileName expects absolute path. If provided |
459 | /// without any path separators then the file |
460 | /// will be created in the current directory. |
461 | /// Error will be emitted if the path is insane. |
462 | #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) |
463 | LLVM_DUMP_METHOD__attribute__((noinline)) __attribute__((__used__)) void dumpDotGraph(const Twine &FileName, const Twine &Title); |
464 | #endif |
465 | |
466 | /// Pop up a GraphViz/gv window with the DAG rendered using 'dot'. |
467 | void viewGraph(const std::string &Title); |
468 | void viewGraph(); |
469 | |
470 | #ifndef NDEBUG |
471 | std::map<const SDNode *, std::string> NodeGraphAttrs; |
472 | #endif |
473 | |
474 | /// Clear all previously defined node graph attributes. |
475 | /// Intended to be used from a debugging tool (eg. gdb). |
476 | void clearGraphAttrs(); |
477 | |
478 | /// Set graph attributes for a node. (eg. "color=red".) |
479 | void setGraphAttrs(const SDNode *N, const char *Attrs); |
480 | |
481 | /// Get graph attributes for a node. (eg. "color=red".) |
482 | /// Used from getNodeAttributes. |
483 | std::string getGraphAttrs(const SDNode *N) const; |
484 | |
485 | /// Convenience for setting node color attribute. |
486 | void setGraphColor(const SDNode *N, const char *Color); |
487 | |
488 | /// Convenience for setting subgraph color attribute. |
489 | void setSubgraphColor(SDNode *N, const char *Color); |
490 | |
491 | using allnodes_const_iterator = ilist<SDNode>::const_iterator; |
492 | |
493 | allnodes_const_iterator allnodes_begin() const { return AllNodes.begin(); } |
494 | allnodes_const_iterator allnodes_end() const { return AllNodes.end(); } |
495 | |
496 | using allnodes_iterator = ilist<SDNode>::iterator; |
497 | |
498 | allnodes_iterator allnodes_begin() { return AllNodes.begin(); } |
499 | allnodes_iterator allnodes_end() { return AllNodes.end(); } |
500 | |
501 | ilist<SDNode>::size_type allnodes_size() const { |
502 | return AllNodes.size(); |
503 | } |
504 | |
505 | iterator_range<allnodes_iterator> allnodes() { |
506 | return make_range(allnodes_begin(), allnodes_end()); |
507 | } |
508 | iterator_range<allnodes_const_iterator> allnodes() const { |
509 | return make_range(allnodes_begin(), allnodes_end()); |
510 | } |
511 | |
512 | /// Return the root tag of the SelectionDAG. |
513 | const SDValue &getRoot() const { return Root; } |
514 | |
515 | /// Return the token chain corresponding to the entry of the function. |
516 | SDValue getEntryNode() const { |
517 | return SDValue(const_cast<SDNode *>(&EntryNode), 0); |
518 | } |
519 | |
520 | /// Set the current root tag of the SelectionDAG. |
521 | /// |
522 | const SDValue &setRoot(SDValue N) { |
523 | assert((!N.getNode() || N.getValueType() == MVT::Other) &&(((!N.getNode() || N.getValueType() == MVT::Other) && "DAG root value is not a chain!") ? static_cast<void> ( 0) : __assert_fail ("(!N.getNode() || N.getValueType() == MVT::Other) && \"DAG root value is not a chain!\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/CodeGen/SelectionDAG.h" , 524, __PRETTY_FUNCTION__)) |
524 | "DAG root value is not a chain!")(((!N.getNode() || N.getValueType() == MVT::Other) && "DAG root value is not a chain!") ? static_cast<void> ( 0) : __assert_fail ("(!N.getNode() || N.getValueType() == MVT::Other) && \"DAG root value is not a chain!\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/CodeGen/SelectionDAG.h" , 524, __PRETTY_FUNCTION__)); |
525 | if (N.getNode()) |
526 | checkForCycles(N.getNode(), this); |
527 | Root = N; |
528 | if (N.getNode()) |
529 | checkForCycles(this); |
530 | return Root; |
531 | } |
532 | |
533 | #ifndef NDEBUG |
534 | void VerifyDAGDiverence(); |
535 | #endif |
536 | |
537 | /// This iterates over the nodes in the SelectionDAG, folding |
538 | /// certain types of nodes together, or eliminating superfluous nodes. The |
539 | /// Level argument controls whether Combine is allowed to produce nodes and |
540 | /// types that are illegal on the target. |
541 | void Combine(CombineLevel Level, AAResults *AA, |
542 | CodeGenOpt::Level OptLevel); |
543 | |
544 | /// This transforms the SelectionDAG into a SelectionDAG that |
545 | /// only uses types natively supported by the target. |
546 | /// Returns "true" if it made any changes. |
547 | /// |
548 | /// Note that this is an involved process that may invalidate pointers into |
549 | /// the graph. |
550 | bool LegalizeTypes(); |
551 | |
552 | /// This transforms the SelectionDAG into a SelectionDAG that is |
553 | /// compatible with the target instruction selector, as indicated by the |
554 | /// TargetLowering object. |
555 | /// |
556 | /// Note that this is an involved process that may invalidate pointers into |
557 | /// the graph. |
558 | void Legalize(); |
559 | |
560 | /// Transforms a SelectionDAG node and any operands to it into a node |
561 | /// that is compatible with the target instruction selector, as indicated by |
562 | /// the TargetLowering object. |
563 | /// |
564 | /// \returns true if \c N is a valid, legal node after calling this. |
565 | /// |
566 | /// This essentially runs a single recursive walk of the \c Legalize process |
567 | /// over the given node (and its operands). This can be used to incrementally |
568 | /// legalize the DAG. All of the nodes which are directly replaced, |
569 | /// potentially including N, are added to the output parameter \c |
570 | /// UpdatedNodes so that the delta to the DAG can be understood by the |
571 | /// caller. |
572 | /// |
573 | /// When this returns false, N has been legalized in a way that make the |
574 | /// pointer passed in no longer valid. It may have even been deleted from the |
575 | /// DAG, and so it shouldn't be used further. When this returns true, the |
576 | /// N passed in is a legal node, and can be immediately processed as such. |
577 | /// This may still have done some work on the DAG, and will still populate |
578 | /// UpdatedNodes with any new nodes replacing those originally in the DAG. |
579 | bool LegalizeOp(SDNode *N, SmallSetVector<SDNode *, 16> &UpdatedNodes); |
580 | |
581 | /// This transforms the SelectionDAG into a SelectionDAG |
582 | /// that only uses vector math operations supported by the target. This is |
583 | /// necessary as a separate step from Legalize because unrolling a vector |
584 | /// operation can introduce illegal types, which requires running |
585 | /// LegalizeTypes again. |
586 | /// |
587 | /// This returns true if it made any changes; in that case, LegalizeTypes |
588 | /// is called again before Legalize. |
589 | /// |
590 | /// Note that this is an involved process that may invalidate pointers into |
591 | /// the graph. |
592 | bool LegalizeVectors(); |
593 | |
594 | /// This method deletes all unreachable nodes in the SelectionDAG. |
595 | void RemoveDeadNodes(); |
596 | |
597 | /// Remove the specified node from the system. This node must |
598 | /// have no referrers. |
599 | void DeleteNode(SDNode *N); |
600 | |
601 | /// Return an SDVTList that represents the list of values specified. |
602 | SDVTList getVTList(EVT VT); |
603 | SDVTList getVTList(EVT VT1, EVT VT2); |
604 | SDVTList getVTList(EVT VT1, EVT VT2, EVT VT3); |
605 | SDVTList getVTList(EVT VT1, EVT VT2, EVT VT3, EVT VT4); |
606 | SDVTList getVTList(ArrayRef<EVT> VTs); |
607 | |
608 | //===--------------------------------------------------------------------===// |
609 | // Node creation methods. |
610 | |
611 | /// Create a ConstantSDNode wrapping a constant value. |
612 | /// If VT is a vector type, the constant is splatted into a BUILD_VECTOR. |
613 | /// |
614 | /// If only legal types can be produced, this does the necessary |
615 | /// transformations (e.g., if the vector element type is illegal). |
616 | /// @{ |
617 | SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, |
618 | bool isTarget = false, bool isOpaque = false); |
619 | SDValue getConstant(const APInt &Val, const SDLoc &DL, EVT VT, |
620 | bool isTarget = false, bool isOpaque = false); |
621 | |
622 | SDValue getAllOnesConstant(const SDLoc &DL, EVT VT, bool IsTarget = false, |
623 | bool IsOpaque = false) { |
624 | return getConstant(APInt::getAllOnesValue(VT.getScalarSizeInBits()), DL, |
625 | VT, IsTarget, IsOpaque); |
626 | } |
627 | |
628 | SDValue getConstant(const ConstantInt &Val, const SDLoc &DL, EVT VT, |
629 | bool isTarget = false, bool isOpaque = false); |
630 | SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, |
631 | bool isTarget = false); |
632 | SDValue getShiftAmountConstant(uint64_t Val, EVT VT, const SDLoc &DL, |
633 | bool LegalTypes = true); |
634 | SDValue getVectorIdxConstant(uint64_t Val, const SDLoc &DL, |
635 | bool isTarget = false); |
636 | |
637 | SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT, |
638 | bool isOpaque = false) { |
639 | return getConstant(Val, DL, VT, true, isOpaque); |
640 | } |
641 | SDValue getTargetConstant(const APInt &Val, const SDLoc &DL, EVT VT, |
642 | bool isOpaque = false) { |
643 | return getConstant(Val, DL, VT, true, isOpaque); |
644 | } |
645 | SDValue getTargetConstant(const ConstantInt &Val, const SDLoc &DL, EVT VT, |
646 | bool isOpaque = false) { |
647 | return getConstant(Val, DL, VT, true, isOpaque); |
648 | } |
649 | |
650 | /// Create a true or false constant of type \p VT using the target's |
651 | /// BooleanContent for type \p OpVT. |
652 | SDValue getBoolConstant(bool V, const SDLoc &DL, EVT VT, EVT OpVT); |
653 | /// @} |
654 | |
655 | /// Create a ConstantFPSDNode wrapping a constant value. |
656 | /// If VT is a vector type, the constant is splatted into a BUILD_VECTOR. |
657 | /// |
658 | /// If only legal types can be produced, this does the necessary |
659 | /// transformations (e.g., if the vector element type is illegal). |
660 | /// The forms that take a double should only be used for simple constants |
661 | /// that can be exactly represented in VT. No checks are made. |
662 | /// @{ |
663 | SDValue getConstantFP(double Val, const SDLoc &DL, EVT VT, |
664 | bool isTarget = false); |
665 | SDValue getConstantFP(const APFloat &Val, const SDLoc &DL, EVT VT, |
666 | bool isTarget = false); |
667 | SDValue getConstantFP(const ConstantFP &V, const SDLoc &DL, EVT VT, |
668 | bool isTarget = false); |
669 | SDValue getTargetConstantFP(double Val, const SDLoc &DL, EVT VT) { |
670 | return getConstantFP(Val, DL, VT, true); |
671 | } |
672 | SDValue getTargetConstantFP(const APFloat &Val, const SDLoc &DL, EVT VT) { |
673 | return getConstantFP(Val, DL, VT, true); |
674 | } |
675 | SDValue getTargetConstantFP(const ConstantFP &Val, const SDLoc &DL, EVT VT) { |
676 | return getConstantFP(Val, DL, VT, true); |
677 | } |
678 | /// @} |
679 | |
680 | SDValue getGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, |
681 | int64_t offset = 0, bool isTargetGA = false, |
682 | unsigned TargetFlags = 0); |
683 | SDValue getTargetGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, |
684 | int64_t offset = 0, unsigned TargetFlags = 0) { |
685 | return getGlobalAddress(GV, DL, VT, offset, true, TargetFlags); |
686 | } |
687 | SDValue getFrameIndex(int FI, EVT VT, bool isTarget = false); |
688 | SDValue getTargetFrameIndex(int FI, EVT VT) { |
689 | return getFrameIndex(FI, VT, true); |
690 | } |
691 | SDValue getJumpTable(int JTI, EVT VT, bool isTarget = false, |
692 | unsigned TargetFlags = 0); |
693 | SDValue getTargetJumpTable(int JTI, EVT VT, unsigned TargetFlags = 0) { |
694 | return getJumpTable(JTI, VT, true, TargetFlags); |
695 | } |
696 | SDValue getConstantPool(const Constant *C, EVT VT, MaybeAlign Align = None, |
697 | int Offs = 0, bool isT = false, |
698 | unsigned TargetFlags = 0); |
699 | SDValue getTargetConstantPool(const Constant *C, EVT VT, |
700 | MaybeAlign Align = None, int Offset = 0, |
701 | unsigned TargetFlags = 0) { |
702 | return getConstantPool(C, VT, Align, Offset, true, TargetFlags); |
703 | } |
704 | SDValue getConstantPool(MachineConstantPoolValue *C, EVT VT, |
705 | MaybeAlign Align = None, int Offs = 0, |
706 | bool isT = false, unsigned TargetFlags = 0); |
707 | SDValue getTargetConstantPool(MachineConstantPoolValue *C, EVT VT, |
708 | MaybeAlign Align = None, int Offset = 0, |
709 | unsigned TargetFlags = 0) { |
710 | return getConstantPool(C, VT, Align, Offset, true, TargetFlags); |
711 | } |
712 | SDValue getTargetIndex(int Index, EVT VT, int64_t Offset = 0, |
713 | unsigned TargetFlags = 0); |
714 | // When generating a branch to a BB, we don't in general know enough |
715 | // to provide debug info for the BB at that time, so keep this one around. |
716 | SDValue getBasicBlock(MachineBasicBlock *MBB); |
717 | SDValue getExternalSymbol(const char *Sym, EVT VT); |
718 | SDValue getTargetExternalSymbol(const char *Sym, EVT VT, |
719 | unsigned TargetFlags = 0); |
720 | SDValue getMCSymbol(MCSymbol *Sym, EVT VT); |
721 | |
722 | SDValue getValueType(EVT); |
723 | SDValue getRegister(unsigned Reg, EVT VT); |
724 | SDValue getRegisterMask(const uint32_t *RegMask); |
725 | SDValue getEHLabel(const SDLoc &dl, SDValue Root, MCSymbol *Label); |
726 | SDValue getLabelNode(unsigned Opcode, const SDLoc &dl, SDValue Root, |
727 | MCSymbol *Label); |
728 | SDValue getBlockAddress(const BlockAddress *BA, EVT VT, int64_t Offset = 0, |
729 | bool isTarget = false, unsigned TargetFlags = 0); |
730 | SDValue getTargetBlockAddress(const BlockAddress *BA, EVT VT, |
731 | int64_t Offset = 0, unsigned TargetFlags = 0) { |
732 | return getBlockAddress(BA, VT, Offset, true, TargetFlags); |
733 | } |
734 | |
735 | SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg, |
736 | SDValue N) { |
737 | return getNode(ISD::CopyToReg, dl, MVT::Other, Chain, |
738 | getRegister(Reg, N.getValueType()), N); |
739 | } |
740 | |
741 | // This version of the getCopyToReg method takes an extra operand, which |
742 | // indicates that there is potentially an incoming glue value (if Glue is not |
743 | // null) and that there should be a glue result. |
744 | SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N, |
745 | SDValue Glue) { |
746 | SDVTList VTs = getVTList(MVT::Other, MVT::Glue); |
747 | SDValue Ops[] = { Chain, getRegister(Reg, N.getValueType()), N, Glue }; |
748 | return getNode(ISD::CopyToReg, dl, VTs, |
749 | makeArrayRef(Ops, Glue.getNode() ? 4 : 3)); |
750 | } |
751 | |
752 | // Similar to last getCopyToReg() except parameter Reg is a SDValue |
753 | SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, SDValue Reg, SDValue N, |
754 | SDValue Glue) { |
755 | SDVTList VTs = getVTList(MVT::Other, MVT::Glue); |
756 | SDValue Ops[] = { Chain, Reg, N, Glue }; |
757 | return getNode(ISD::CopyToReg, dl, VTs, |
758 | makeArrayRef(Ops, Glue.getNode() ? 4 : 3)); |
759 | } |
760 | |
761 | SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT) { |
762 | SDVTList VTs = getVTList(VT, MVT::Other); |
763 | SDValue Ops[] = { Chain, getRegister(Reg, VT) }; |
764 | return getNode(ISD::CopyFromReg, dl, VTs, Ops); |
765 | } |
766 | |
767 | // This version of the getCopyFromReg method takes an extra operand, which |
768 | // indicates that there is potentially an incoming glue value (if Glue is not |
769 | // null) and that there should be a glue result. |
770 | SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT, |
771 | SDValue Glue) { |
772 | SDVTList VTs = getVTList(VT, MVT::Other, MVT::Glue); |
773 | SDValue Ops[] = { Chain, getRegister(Reg, VT), Glue }; |
774 | return getNode(ISD::CopyFromReg, dl, VTs, |
775 | makeArrayRef(Ops, Glue.getNode() ? 3 : 2)); |
776 | } |
777 | |
778 | SDValue getCondCode(ISD::CondCode Cond); |
779 | |
780 | /// Return an ISD::VECTOR_SHUFFLE node. The number of elements in VT, |
781 | /// which must be a vector type, must match the number of mask elements |
782 | /// NumElts. An integer mask element equal to -1 is treated as undefined. |
783 | SDValue getVectorShuffle(EVT VT, const SDLoc &dl, SDValue N1, SDValue N2, |
784 | ArrayRef<int> Mask); |
785 | |
786 | /// Return an ISD::BUILD_VECTOR node. The number of elements in VT, |
787 | /// which must be a vector type, must match the number of operands in Ops. |
788 | /// The operands must have the same type as (or, for integers, a type wider |
789 | /// than) VT's element type. |
790 | SDValue getBuildVector(EVT VT, const SDLoc &DL, ArrayRef<SDValue> Ops) { |
791 | // VerifySDNode (via InsertNode) checks BUILD_VECTOR later. |
792 | return getNode(ISD::BUILD_VECTOR, DL, VT, Ops); |
793 | } |
794 | |
795 | /// Return an ISD::BUILD_VECTOR node. The number of elements in VT, |
796 | /// which must be a vector type, must match the number of operands in Ops. |
797 | /// The operands must have the same type as (or, for integers, a type wider |
798 | /// than) VT's element type. |
799 | SDValue getBuildVector(EVT VT, const SDLoc &DL, ArrayRef<SDUse> Ops) { |
800 | // VerifySDNode (via InsertNode) checks BUILD_VECTOR later. |
801 | return getNode(ISD::BUILD_VECTOR, DL, VT, Ops); |
802 | } |
803 | |
804 | /// Return a splat ISD::BUILD_VECTOR node, consisting of Op splatted to all |
805 | /// elements. VT must be a vector type. Op's type must be the same as (or, |
806 | /// for integers, a type wider than) VT's element type. |
807 | SDValue getSplatBuildVector(EVT VT, const SDLoc &DL, SDValue Op) { |
808 | // VerifySDNode (via InsertNode) checks BUILD_VECTOR later. |
809 | if (Op.getOpcode() == ISD::UNDEF) { |
810 | assert((VT.getVectorElementType() == Op.getValueType() ||(((VT.getVectorElementType() == Op.getValueType() || (VT.isInteger () && VT.getVectorElementType().bitsLE(Op.getValueType ()))) && "A splatted value must have a width equal or (for integers) " "greater than the vector element type!") ? static_cast<void > (0) : __assert_fail ("(VT.getVectorElementType() == Op.getValueType() || (VT.isInteger() && VT.getVectorElementType().bitsLE(Op.getValueType()))) && \"A splatted value must have a width equal or (for integers) \" \"greater than the vector element type!\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/CodeGen/SelectionDAG.h" , 814, __PRETTY_FUNCTION__)) |
811 | (VT.isInteger() &&(((VT.getVectorElementType() == Op.getValueType() || (VT.isInteger () && VT.getVectorElementType().bitsLE(Op.getValueType ()))) && "A splatted value must have a width equal or (for integers) " "greater than the vector element type!") ? static_cast<void > (0) : __assert_fail ("(VT.getVectorElementType() == Op.getValueType() || (VT.isInteger() && VT.getVectorElementType().bitsLE(Op.getValueType()))) && \"A splatted value must have a width equal or (for integers) \" \"greater than the vector element type!\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/CodeGen/SelectionDAG.h" , 814, __PRETTY_FUNCTION__)) |
812 | VT.getVectorElementType().bitsLE(Op.getValueType()))) &&(((VT.getVectorElementType() == Op.getValueType() || (VT.isInteger () && VT.getVectorElementType().bitsLE(Op.getValueType ()))) && "A splatted value must have a width equal or (for integers) " "greater than the vector element type!") ? static_cast<void > (0) : __assert_fail ("(VT.getVectorElementType() == Op.getValueType() || (VT.isInteger() && VT.getVectorElementType().bitsLE(Op.getValueType()))) && \"A splatted value must have a width equal or (for integers) \" \"greater than the vector element type!\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/CodeGen/SelectionDAG.h" , 814, __PRETTY_FUNCTION__)) |
813 | "A splatted value must have a width equal or (for integers) "(((VT.getVectorElementType() == Op.getValueType() || (VT.isInteger () && VT.getVectorElementType().bitsLE(Op.getValueType ()))) && "A splatted value must have a width equal or (for integers) " "greater than the vector element type!") ? static_cast<void > (0) : __assert_fail ("(VT.getVectorElementType() == Op.getValueType() || (VT.isInteger() && VT.getVectorElementType().bitsLE(Op.getValueType()))) && \"A splatted value must have a width equal or (for integers) \" \"greater than the vector element type!\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/CodeGen/SelectionDAG.h" , 814, __PRETTY_FUNCTION__)) |
814 | "greater than the vector element type!")(((VT.getVectorElementType() == Op.getValueType() || (VT.isInteger () && VT.getVectorElementType().bitsLE(Op.getValueType ()))) && "A splatted value must have a width equal or (for integers) " "greater than the vector element type!") ? static_cast<void > (0) : __assert_fail ("(VT.getVectorElementType() == Op.getValueType() || (VT.isInteger() && VT.getVectorElementType().bitsLE(Op.getValueType()))) && \"A splatted value must have a width equal or (for integers) \" \"greater than the vector element type!\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/CodeGen/SelectionDAG.h" , 814, __PRETTY_FUNCTION__)); |
815 | return getNode(ISD::UNDEF, SDLoc(), VT); |
816 | } |
817 | |
818 | SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Op); |
819 | return getNode(ISD::BUILD_VECTOR, DL, VT, Ops); |
820 | } |
821 | |
822 | // Return a splat ISD::SPLAT_VECTOR node, consisting of Op splatted to all |
823 | // elements. |
824 | SDValue getSplatVector(EVT VT, const SDLoc &DL, SDValue Op) { |
825 | if (Op.getOpcode() == ISD::UNDEF) { |
826 | assert((VT.getVectorElementType() == Op.getValueType() ||(((VT.getVectorElementType() == Op.getValueType() || (VT.isInteger () && VT.getVectorElementType().bitsLE(Op.getValueType ()))) && "A splatted value must have a width equal or (for integers) " "greater than the vector element type!") ? static_cast<void > (0) : __assert_fail ("(VT.getVectorElementType() == Op.getValueType() || (VT.isInteger() && VT.getVectorElementType().bitsLE(Op.getValueType()))) && \"A splatted value must have a width equal or (for integers) \" \"greater than the vector element type!\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/CodeGen/SelectionDAG.h" , 830, __PRETTY_FUNCTION__)) |
827 | (VT.isInteger() &&(((VT.getVectorElementType() == Op.getValueType() || (VT.isInteger () && VT.getVectorElementType().bitsLE(Op.getValueType ()))) && "A splatted value must have a width equal or (for integers) " "greater than the vector element type!") ? static_cast<void > (0) : __assert_fail ("(VT.getVectorElementType() == Op.getValueType() || (VT.isInteger() && VT.getVectorElementType().bitsLE(Op.getValueType()))) && \"A splatted value must have a width equal or (for integers) \" \"greater than the vector element type!\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/CodeGen/SelectionDAG.h" , 830, __PRETTY_FUNCTION__)) |
828 | VT.getVectorElementType().bitsLE(Op.getValueType()))) &&(((VT.getVectorElementType() == Op.getValueType() || (VT.isInteger () && VT.getVectorElementType().bitsLE(Op.getValueType ()))) && "A splatted value must have a width equal or (for integers) " "greater than the vector element type!") ? static_cast<void > (0) : __assert_fail ("(VT.getVectorElementType() == Op.getValueType() || (VT.isInteger() && VT.getVectorElementType().bitsLE(Op.getValueType()))) && \"A splatted value must have a width equal or (for integers) \" \"greater than the vector element type!\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/CodeGen/SelectionDAG.h" , 830, __PRETTY_FUNCTION__)) |
829 | "A splatted value must have a width equal or (for integers) "(((VT.getVectorElementType() == Op.getValueType() || (VT.isInteger () && VT.getVectorElementType().bitsLE(Op.getValueType ()))) && "A splatted value must have a width equal or (for integers) " "greater than the vector element type!") ? static_cast<void > (0) : __assert_fail ("(VT.getVectorElementType() == Op.getValueType() || (VT.isInteger() && VT.getVectorElementType().bitsLE(Op.getValueType()))) && \"A splatted value must have a width equal or (for integers) \" \"greater than the vector element type!\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/CodeGen/SelectionDAG.h" , 830, __PRETTY_FUNCTION__)) |
830 | "greater than the vector element type!")(((VT.getVectorElementType() == Op.getValueType() || (VT.isInteger () && VT.getVectorElementType().bitsLE(Op.getValueType ()))) && "A splatted value must have a width equal or (for integers) " "greater than the vector element type!") ? static_cast<void > (0) : __assert_fail ("(VT.getVectorElementType() == Op.getValueType() || (VT.isInteger() && VT.getVectorElementType().bitsLE(Op.getValueType()))) && \"A splatted value must have a width equal or (for integers) \" \"greater than the vector element type!\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/CodeGen/SelectionDAG.h" , 830, __PRETTY_FUNCTION__)); |
831 | return getNode(ISD::UNDEF, SDLoc(), VT); |
832 | } |
833 | return getNode(ISD::SPLAT_VECTOR, DL, VT, Op); |
834 | } |
835 | |
836 | /// Returns a vector of type ResVT whose elements contain the linear sequence |
837 | /// <0, Step, Step * 2, Step * 3, ...> |
838 | SDValue getStepVector(const SDLoc &DL, EVT ResVT, SDValue Step); |
839 | |
840 | /// Returns an ISD::VECTOR_SHUFFLE node semantically equivalent to |
841 | /// the shuffle node in input but with swapped operands. |
842 | /// |
843 | /// Example: shuffle A, B, <0,5,2,7> -> shuffle B, A, <4,1,6,3> |
844 | SDValue getCommutedVectorShuffle(const ShuffleVectorSDNode &SV); |
845 | |
846 | /// Convert Op, which must be of float type, to the |
847 | /// float type VT, by either extending or rounding (by truncation). |
848 | SDValue getFPExtendOrRound(SDValue Op, const SDLoc &DL, EVT VT); |
849 | |
850 | /// Convert Op, which must be a STRICT operation of float type, to the |
851 | /// float type VT, by either extending or rounding (by truncation). |
852 | std::pair<SDValue, SDValue> |
853 | getStrictFPExtendOrRound(SDValue Op, SDValue Chain, const SDLoc &DL, EVT VT); |
854 | |
855 | /// Convert Op, which must be of integer type, to the |
856 | /// integer type VT, by either any-extending or truncating it. |
857 | SDValue getAnyExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT); |
858 | |
859 | /// Convert Op, which must be of integer type, to the |
860 | /// integer type VT, by either sign-extending or truncating it. |
861 | SDValue getSExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT); |
862 | |
863 | /// Convert Op, which must be of integer type, to the |
864 | /// integer type VT, by either zero-extending or truncating it. |
865 | SDValue getZExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT); |
866 | |
867 | /// Return the expression required to zero extend the Op |
868 | /// value assuming it was the smaller SrcTy value. |
869 | SDValue getZeroExtendInReg(SDValue Op, const SDLoc &DL, EVT VT); |
870 | |
871 | /// Convert Op, which must be of integer type, to the integer type VT, by |
872 | /// either truncating it or performing either zero or sign extension as |
873 | /// appropriate extension for the pointer's semantics. |
874 | SDValue getPtrExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT); |
875 | |
876 | /// Return the expression required to extend the Op as a pointer value |
877 | /// assuming it was the smaller SrcTy value. This may be either a zero extend |
878 | /// or a sign extend. |
879 | SDValue getPtrExtendInReg(SDValue Op, const SDLoc &DL, EVT VT); |
880 | |
881 | /// Convert Op, which must be of integer type, to the integer type VT, |
882 | /// by using an extension appropriate for the target's |
883 | /// BooleanContent for type OpVT or truncating it. |
884 | SDValue getBoolExtOrTrunc(SDValue Op, const SDLoc &SL, EVT VT, EVT OpVT); |
885 | |
886 | /// Create a bitwise NOT operation as (XOR Val, -1). |
887 | SDValue getNOT(const SDLoc &DL, SDValue Val, EVT VT); |
888 | |
889 | /// Create a logical NOT operation as (XOR Val, BooleanOne). |
890 | SDValue getLogicalNOT(const SDLoc &DL, SDValue Val, EVT VT); |
891 | |
892 | /// Returns sum of the base pointer and offset. |
893 | /// Unlike getObjectPtrOffset this does not set NoUnsignedWrap by default. |
894 | SDValue getMemBasePlusOffset(SDValue Base, TypeSize Offset, const SDLoc &DL, |
895 | const SDNodeFlags Flags = SDNodeFlags()); |
896 | SDValue getMemBasePlusOffset(SDValue Base, SDValue Offset, const SDLoc &DL, |
897 | const SDNodeFlags Flags = SDNodeFlags()); |
898 | |
899 | /// Create an add instruction with appropriate flags when used for |
900 | /// addressing some offset of an object. i.e. if a load is split into multiple |
901 | /// components, create an add nuw from the base pointer to the offset. |
902 | SDValue getObjectPtrOffset(const SDLoc &SL, SDValue Ptr, TypeSize Offset) { |
903 | SDNodeFlags Flags; |
904 | Flags.setNoUnsignedWrap(true); |
905 | return getMemBasePlusOffset(Ptr, Offset, SL, Flags); |
906 | } |
907 | |
908 | SDValue getObjectPtrOffset(const SDLoc &SL, SDValue Ptr, SDValue Offset) { |
909 | // The object itself can't wrap around the address space, so it shouldn't be |
910 | // possible for the adds of the offsets to the split parts to overflow. |
911 | SDNodeFlags Flags; |
912 | Flags.setNoUnsignedWrap(true); |
913 | return getMemBasePlusOffset(Ptr, Offset, SL, Flags); |
914 | } |
915 | |
916 | /// Return a new CALLSEQ_START node, that starts new call frame, in which |
917 | /// InSize bytes are set up inside CALLSEQ_START..CALLSEQ_END sequence and |
918 | /// OutSize specifies part of the frame set up prior to the sequence. |
919 | SDValue getCALLSEQ_START(SDValue Chain, uint64_t InSize, uint64_t OutSize, |
920 | const SDLoc &DL) { |
921 | SDVTList VTs = getVTList(MVT::Other, MVT::Glue); |
922 | SDValue Ops[] = { Chain, |
923 | getIntPtrConstant(InSize, DL, true), |
924 | getIntPtrConstant(OutSize, DL, true) }; |
925 | return getNode(ISD::CALLSEQ_START, DL, VTs, Ops); |
926 | } |
927 | |
928 | /// Return a new CALLSEQ_END node, which always must have a |
929 | /// glue result (to ensure it's not CSE'd). |
930 | /// CALLSEQ_END does not have a useful SDLoc. |
931 | SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, |
932 | SDValue InGlue, const SDLoc &DL) { |
933 | SDVTList NodeTys = getVTList(MVT::Other, MVT::Glue); |
934 | SmallVector<SDValue, 4> Ops; |
935 | Ops.push_back(Chain); |
936 | Ops.push_back(Op1); |
937 | Ops.push_back(Op2); |
938 | if (InGlue.getNode()) |
939 | Ops.push_back(InGlue); |
940 | return getNode(ISD::CALLSEQ_END, DL, NodeTys, Ops); |
941 | } |
942 | |
943 | /// Return true if the result of this operation is always undefined. |
944 | bool isUndef(unsigned Opcode, ArrayRef<SDValue> Ops); |
945 | |
946 | /// Return an UNDEF node. UNDEF does not have a useful SDLoc. |
947 | SDValue getUNDEF(EVT VT) { |
948 | return getNode(ISD::UNDEF, SDLoc(), VT); |
949 | } |
950 | |
951 | /// Return a node that represents the runtime scaling 'MulImm * RuntimeVL'. |
952 | SDValue getVScale(const SDLoc &DL, EVT VT, APInt MulImm) { |
953 | assert(MulImm.getMinSignedBits() <= VT.getSizeInBits() &&((MulImm.getMinSignedBits() <= VT.getSizeInBits() && "Immediate does not fit VT") ? static_cast<void> (0) : __assert_fail ("MulImm.getMinSignedBits() <= VT.getSizeInBits() && \"Immediate does not fit VT\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/CodeGen/SelectionDAG.h" , 954, __PRETTY_FUNCTION__)) |
954 | "Immediate does not fit VT")((MulImm.getMinSignedBits() <= VT.getSizeInBits() && "Immediate does not fit VT") ? static_cast<void> (0) : __assert_fail ("MulImm.getMinSignedBits() <= VT.getSizeInBits() && \"Immediate does not fit VT\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/CodeGen/SelectionDAG.h" , 954, __PRETTY_FUNCTION__)); |
955 | return getNode(ISD::VSCALE, DL, VT, |
956 | getConstant(MulImm.sextOrTrunc(VT.getSizeInBits()), DL, VT)); |
957 | } |
958 | |
959 | /// Return a GLOBAL_OFFSET_TABLE node. This does not have a useful SDLoc. |
960 | SDValue getGLOBAL_OFFSET_TABLE(EVT VT) { |
961 | return getNode(ISD::GLOBAL_OFFSET_TABLE, SDLoc(), VT); |
962 | } |
963 | |
964 | /// Gets or creates the specified node. |
965 | /// |
966 | SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, |
967 | ArrayRef<SDUse> Ops); |
968 | SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, |
969 | ArrayRef<SDValue> Ops, const SDNodeFlags Flags); |
970 | SDValue getNode(unsigned Opcode, const SDLoc &DL, ArrayRef<EVT> ResultTys, |
971 | ArrayRef<SDValue> Ops); |
972 | SDValue getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList, |
973 | ArrayRef<SDValue> Ops, const SDNodeFlags Flags); |
974 | |
975 | // Use flags from current flag inserter. |
976 | SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, |
977 | ArrayRef<SDValue> Ops); |
978 | SDValue getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList, |
979 | ArrayRef<SDValue> Ops); |
980 | SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue Operand); |
981 | SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1, |
982 | SDValue N2); |
983 | SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1, |
984 | SDValue N2, SDValue N3); |
985 | |
986 | // Specialize based on number of operands. |
987 | SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT); |
988 | SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue Operand, |
989 | const SDNodeFlags Flags); |
990 | SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1, |
991 | SDValue N2, const SDNodeFlags Flags); |
992 | SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1, |
993 | SDValue N2, SDValue N3, const SDNodeFlags Flags); |
994 | SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1, |
995 | SDValue N2, SDValue N3, SDValue N4); |
996 | SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1, |
997 | SDValue N2, SDValue N3, SDValue N4, SDValue N5); |
998 | |
999 | // Specialize again based on number of operands for nodes with a VTList |
1000 | // rather than a single VT. |
1001 | SDValue getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList); |
1002 | SDValue getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList, SDValue N); |
1003 | SDValue getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList, SDValue N1, |
1004 | SDValue N2); |
1005 | SDValue getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList, SDValue N1, |
1006 | SDValue N2, SDValue N3); |
1007 | SDValue getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList, SDValue N1, |
1008 | SDValue N2, SDValue N3, SDValue N4); |
1009 | SDValue getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList, SDValue N1, |
1010 | SDValue N2, SDValue N3, SDValue N4, SDValue N5); |
1011 | |
1012 | /// Compute a TokenFactor to force all the incoming stack arguments to be |
1013 | /// loaded from the stack. This is used in tail call lowering to protect |
1014 | /// stack arguments from being clobbered. |
1015 | SDValue getStackArgumentTokenFactor(SDValue Chain); |
1016 | |
1017 | LLVM_ATTRIBUTE_DEPRECATED(SDValue getMemcpy(SDValue Chain, const SDLoc &dl,[[deprecated("Use the version that takes Align instead")]] SDValue getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVol, bool AlwaysInline , bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) |
1018 | SDValue Dst, SDValue Src,[[deprecated("Use the version that takes Align instead")]] SDValue getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVol, bool AlwaysInline , bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) |
1019 | SDValue Size, unsigned Align,[[deprecated("Use the version that takes Align instead")]] SDValue getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVol, bool AlwaysInline , bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) |
1020 | bool isVol, bool AlwaysInline,[[deprecated("Use the version that takes Align instead")]] SDValue getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVol, bool AlwaysInline , bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) |
1021 | bool isTailCall,[[deprecated("Use the version that takes Align instead")]] SDValue getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVol, bool AlwaysInline , bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) |
1022 | MachinePointerInfo DstPtrInfo,[[deprecated("Use the version that takes Align instead")]] SDValue getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVol, bool AlwaysInline , bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) |
1023 | MachinePointerInfo SrcPtrInfo),[[deprecated("Use the version that takes Align instead")]] SDValue getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVol, bool AlwaysInline , bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) |
1024 | "Use the version that takes Align instead")[[deprecated("Use the version that takes Align instead")]] SDValue getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVol, bool AlwaysInline , bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) { |
1025 | return getMemcpy(Chain, dl, Dst, Src, Size, llvm::Align(Align), isVol, |
1026 | AlwaysInline, isTailCall, DstPtrInfo, SrcPtrInfo); |
1027 | } |
1028 | |
1029 | SDValue getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, |
1030 | SDValue Size, Align Alignment, bool isVol, |
1031 | bool AlwaysInline, bool isTailCall, |
1032 | MachinePointerInfo DstPtrInfo, |
1033 | MachinePointerInfo SrcPtrInfo); |
1034 | |
1035 | LLVM_ATTRIBUTE_DEPRECATED(SDValue getMemmove(SDValue Chain, const SDLoc &dl,[[deprecated("Use the version that takes Align instead")]] SDValue getMemmove(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVol, bool isTailCall , MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo ) |
1036 | SDValue Dst, SDValue Src,[[deprecated("Use the version that takes Align instead")]] SDValue getMemmove(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVol, bool isTailCall , MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo ) |
1037 | SDValue Size, unsigned Align,[[deprecated("Use the version that takes Align instead")]] SDValue getMemmove(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVol, bool isTailCall , MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo ) |
1038 | bool isVol, bool isTailCall,[[deprecated("Use the version that takes Align instead")]] SDValue getMemmove(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVol, bool isTailCall , MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo ) |
1039 | MachinePointerInfo DstPtrInfo,[[deprecated("Use the version that takes Align instead")]] SDValue getMemmove(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVol, bool isTailCall , MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo ) |
1040 | MachinePointerInfo SrcPtrInfo),[[deprecated("Use the version that takes Align instead")]] SDValue getMemmove(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVol, bool isTailCall , MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo ) |
1041 | "Use the version that takes Align instead")[[deprecated("Use the version that takes Align instead")]] SDValue getMemmove(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVol, bool isTailCall , MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo ) { |
1042 | return getMemmove(Chain, dl, Dst, Src, Size, llvm::Align(Align), isVol, |
1043 | isTailCall, DstPtrInfo, SrcPtrInfo); |
1044 | } |
1045 | SDValue getMemmove(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, |
1046 | SDValue Size, Align Alignment, bool isVol, bool isTailCall, |
1047 | MachinePointerInfo DstPtrInfo, |
1048 | MachinePointerInfo SrcPtrInfo); |
1049 | |
1050 | LLVM_ATTRIBUTE_DEPRECATED(SDValue getMemset(SDValue Chain, const SDLoc &dl,[[deprecated("Use the version that takes Align instead")]] SDValue getMemset(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVol, bool isTailCall , MachinePointerInfo DstPtrInfo) |
1051 | SDValue Dst, SDValue Src,[[deprecated("Use the version that takes Align instead")]] SDValue getMemset(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVol, bool isTailCall , MachinePointerInfo DstPtrInfo) |
1052 | SDValue Size, unsigned Align,[[deprecated("Use the version that takes Align instead")]] SDValue getMemset(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVol, bool isTailCall , MachinePointerInfo DstPtrInfo) |
1053 | bool isVol, bool isTailCall,[[deprecated("Use the version that takes Align instead")]] SDValue getMemset(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVol, bool isTailCall , MachinePointerInfo DstPtrInfo) |
1054 | MachinePointerInfo DstPtrInfo),[[deprecated("Use the version that takes Align instead")]] SDValue getMemset(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVol, bool isTailCall , MachinePointerInfo DstPtrInfo) |
1055 | "Use the version that takes Align instead")[[deprecated("Use the version that takes Align instead")]] SDValue getMemset(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVol, bool isTailCall , MachinePointerInfo DstPtrInfo) { |
1056 | return getMemset(Chain, dl, Dst, Src, Size, llvm::Align(Align), isVol, |
1057 | isTailCall, DstPtrInfo); |
1058 | } |
1059 | SDValue getMemset(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, |
1060 | SDValue Size, Align Alignment, bool isVol, bool isTailCall, |
1061 | MachinePointerInfo DstPtrInfo); |
1062 | |
1063 | SDValue getAtomicMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, |
1064 | unsigned DstAlign, SDValue Src, unsigned SrcAlign, |
1065 | SDValue Size, Type *SizeTy, unsigned ElemSz, |
1066 | bool isTailCall, MachinePointerInfo DstPtrInfo, |
1067 | MachinePointerInfo SrcPtrInfo); |
1068 | |
1069 | SDValue getAtomicMemmove(SDValue Chain, const SDLoc &dl, SDValue Dst, |
1070 | unsigned DstAlign, SDValue Src, unsigned SrcAlign, |
1071 | SDValue Size, Type *SizeTy, unsigned ElemSz, |
1072 | bool isTailCall, MachinePointerInfo DstPtrInfo, |
1073 | MachinePointerInfo SrcPtrInfo); |
1074 | |
1075 | SDValue getAtomicMemset(SDValue Chain, const SDLoc &dl, SDValue Dst, |
1076 | unsigned DstAlign, SDValue Value, SDValue Size, |
1077 | Type *SizeTy, unsigned ElemSz, bool isTailCall, |
1078 | MachinePointerInfo DstPtrInfo); |
1079 | |
1080 | /// Helper function to make it easier to build SetCC's if you just have an |
1081 | /// ISD::CondCode instead of an SDValue. |
1082 | SDValue getSetCC(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, |
1083 | ISD::CondCode Cond, SDValue Chain = SDValue(), |
1084 | bool IsSignaling = false) { |
1085 | assert(LHS.getValueType().isVector() == RHS.getValueType().isVector() &&((LHS.getValueType().isVector() == RHS.getValueType().isVector () && "Cannot compare scalars to vectors") ? static_cast <void> (0) : __assert_fail ("LHS.getValueType().isVector() == RHS.getValueType().isVector() && \"Cannot compare scalars to vectors\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/CodeGen/SelectionDAG.h" , 1086, __PRETTY_FUNCTION__)) |
1086 | "Cannot compare scalars to vectors")((LHS.getValueType().isVector() == RHS.getValueType().isVector () && "Cannot compare scalars to vectors") ? static_cast <void> (0) : __assert_fail ("LHS.getValueType().isVector() == RHS.getValueType().isVector() && \"Cannot compare scalars to vectors\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/CodeGen/SelectionDAG.h" , 1086, __PRETTY_FUNCTION__)); |
1087 | assert(LHS.getValueType().isVector() == VT.isVector() &&((LHS.getValueType().isVector() == VT.isVector() && "Cannot compare scalars to vectors" ) ? static_cast<void> (0) : __assert_fail ("LHS.getValueType().isVector() == VT.isVector() && \"Cannot compare scalars to vectors\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/CodeGen/SelectionDAG.h" , 1088, __PRETTY_FUNCTION__)) |
1088 | "Cannot compare scalars to vectors")((LHS.getValueType().isVector() == VT.isVector() && "Cannot compare scalars to vectors" ) ? static_cast<void> (0) : __assert_fail ("LHS.getValueType().isVector() == VT.isVector() && \"Cannot compare scalars to vectors\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/CodeGen/SelectionDAG.h" , 1088, __PRETTY_FUNCTION__)); |
1089 | assert(Cond != ISD::SETCC_INVALID &&((Cond != ISD::SETCC_INVALID && "Cannot create a setCC of an invalid node." ) ? static_cast<void> (0) : __assert_fail ("Cond != ISD::SETCC_INVALID && \"Cannot create a setCC of an invalid node.\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/CodeGen/SelectionDAG.h" , 1090, __PRETTY_FUNCTION__)) |
1090 | "Cannot create a setCC of an invalid node.")((Cond != ISD::SETCC_INVALID && "Cannot create a setCC of an invalid node." ) ? static_cast<void> (0) : __assert_fail ("Cond != ISD::SETCC_INVALID && \"Cannot create a setCC of an invalid node.\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/CodeGen/SelectionDAG.h" , 1090, __PRETTY_FUNCTION__)); |
1091 | if (Chain) |
1092 | return getNode(IsSignaling ? ISD::STRICT_FSETCCS : ISD::STRICT_FSETCC, DL, |
1093 | {VT, MVT::Other}, {Chain, LHS, RHS, getCondCode(Cond)}); |
1094 | return getNode(ISD::SETCC, DL, VT, LHS, RHS, getCondCode(Cond)); |
1095 | } |
1096 | |
1097 | /// Helper function to make it easier to build Select's if you just have |
1098 | /// operands and don't want to check for vector. |
1099 | SDValue getSelect(const SDLoc &DL, EVT VT, SDValue Cond, SDValue LHS, |
1100 | SDValue RHS) { |
1101 | assert(LHS.getValueType() == RHS.getValueType() &&((LHS.getValueType() == RHS.getValueType() && "Cannot use select on differing types" ) ? static_cast<void> (0) : __assert_fail ("LHS.getValueType() == RHS.getValueType() && \"Cannot use select on differing types\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/CodeGen/SelectionDAG.h" , 1102, __PRETTY_FUNCTION__)) |
1102 | "Cannot use select on differing types")((LHS.getValueType() == RHS.getValueType() && "Cannot use select on differing types" ) ? static_cast<void> (0) : __assert_fail ("LHS.getValueType() == RHS.getValueType() && \"Cannot use select on differing types\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/CodeGen/SelectionDAG.h" , 1102, __PRETTY_FUNCTION__)); |
1103 | assert(VT.isVector() == LHS.getValueType().isVector() &&((VT.isVector() == LHS.getValueType().isVector() && "Cannot mix vectors and scalars" ) ? static_cast<void> (0) : __assert_fail ("VT.isVector() == LHS.getValueType().isVector() && \"Cannot mix vectors and scalars\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/CodeGen/SelectionDAG.h" , 1104, __PRETTY_FUNCTION__)) |
1104 | "Cannot mix vectors and scalars")((VT.isVector() == LHS.getValueType().isVector() && "Cannot mix vectors and scalars" ) ? static_cast<void> (0) : __assert_fail ("VT.isVector() == LHS.getValueType().isVector() && \"Cannot mix vectors and scalars\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/CodeGen/SelectionDAG.h" , 1104, __PRETTY_FUNCTION__)); |
1105 | auto Opcode = Cond.getValueType().isVector() ? ISD::VSELECT : ISD::SELECT; |
1106 | return getNode(Opcode, DL, VT, Cond, LHS, RHS); |
1107 | } |
1108 | |
1109 | /// Helper function to make it easier to build SelectCC's if you just have an |
1110 | /// ISD::CondCode instead of an SDValue. |
1111 | SDValue getSelectCC(const SDLoc &DL, SDValue LHS, SDValue RHS, SDValue True, |
1112 | SDValue False, ISD::CondCode Cond) { |
1113 | return getNode(ISD::SELECT_CC, DL, True.getValueType(), LHS, RHS, True, |
1114 | False, getCondCode(Cond)); |
1115 | } |
1116 | |
1117 | /// Try to simplify a select/vselect into 1 of its operands or a constant. |
1118 | SDValue simplifySelect(SDValue Cond, SDValue TVal, SDValue FVal); |
1119 | |
1120 | /// Try to simplify a shift into 1 of its operands or a constant. |
1121 | SDValue simplifyShift(SDValue X, SDValue Y); |
1122 | |
1123 | /// Try to simplify a floating-point binary operation into 1 of its operands |
1124 | /// or a constant. |
1125 | SDValue simplifyFPBinop(unsigned Opcode, SDValue X, SDValue Y, |
1126 | SDNodeFlags Flags); |
1127 | |
1128 | /// VAArg produces a result and token chain, and takes a pointer |
1129 | /// and a source value as input. |
1130 | SDValue getVAArg(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, |
1131 | SDValue SV, unsigned Align); |
1132 | |
1133 | /// Gets a node for an atomic cmpxchg op. There are two |
1134 | /// valid Opcodes. ISD::ATOMIC_CMO_SWAP produces the value loaded and a |
1135 | /// chain result. ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS produces the value loaded, |
1136 | /// a success flag (initially i1), and a chain. |
1137 | SDValue getAtomicCmpSwap(unsigned Opcode, const SDLoc &dl, EVT MemVT, |
1138 | SDVTList VTs, SDValue Chain, SDValue Ptr, |
1139 | SDValue Cmp, SDValue Swp, MachineMemOperand *MMO); |
1140 | |
1141 | /// Gets a node for an atomic op, produces result (if relevant) |
1142 | /// and chain and takes 2 operands. |
1143 | SDValue getAtomic(unsigned Opcode, const SDLoc &dl, EVT MemVT, SDValue Chain, |
1144 | SDValue Ptr, SDValue Val, MachineMemOperand *MMO); |
1145 | |
1146 | /// Gets a node for an atomic op, produces result and chain and |
1147 | /// takes 1 operand. |
1148 | SDValue getAtomic(unsigned Opcode, const SDLoc &dl, EVT MemVT, EVT VT, |
1149 | SDValue Chain, SDValue Ptr, MachineMemOperand *MMO); |
1150 | |
1151 | /// Gets a node for an atomic op, produces result and chain and takes N |
1152 | /// operands. |
1153 | SDValue getAtomic(unsigned Opcode, const SDLoc &dl, EVT MemVT, |
1154 | SDVTList VTList, ArrayRef<SDValue> Ops, |
1155 | MachineMemOperand *MMO); |
1156 | |
1157 | /// Creates a MemIntrinsicNode that may produce a |
1158 | /// result and takes a list of operands. Opcode may be INTRINSIC_VOID, |
1159 | /// INTRINSIC_W_CHAIN, or a target-specific opcode with a value not |
1160 | /// less than FIRST_TARGET_MEMORY_OPCODE. |
1161 | SDValue getMemIntrinsicNode( |
1162 | unsigned Opcode, const SDLoc &dl, SDVTList VTList, ArrayRef<SDValue> Ops, |
1163 | EVT MemVT, MachinePointerInfo PtrInfo, Align Alignment, |
1164 | MachineMemOperand::Flags Flags = MachineMemOperand::MOLoad | |
1165 | MachineMemOperand::MOStore, |
1166 | uint64_t Size = 0, const AAMDNodes &AAInfo = AAMDNodes()); |
1167 | |
1168 | inline SDValue getMemIntrinsicNode( |
1169 | unsigned Opcode, const SDLoc &dl, SDVTList VTList, ArrayRef<SDValue> Ops, |
1170 | EVT MemVT, MachinePointerInfo PtrInfo, MaybeAlign Alignment = None, |
1171 | MachineMemOperand::Flags Flags = MachineMemOperand::MOLoad | |
1172 | MachineMemOperand::MOStore, |
1173 | uint64_t Size = 0, const AAMDNodes &AAInfo = AAMDNodes()) { |
1174 | // Ensure that codegen never sees alignment 0 |
1175 | return getMemIntrinsicNode(Opcode, dl, VTList, Ops, MemVT, PtrInfo, |
1176 | Alignment.getValueOr(getEVTAlign(MemVT)), Flags, |
1177 | Size, AAInfo); |
1178 | } |
1179 | |
1180 | LLVM_ATTRIBUTE_DEPRECATED([[deprecated("")]] inline SDValue getMemIntrinsicNode( unsigned Opcode, const SDLoc &dl, SDVTList VTList, ArrayRef<SDValue > Ops, EVT MemVT, MachinePointerInfo PtrInfo, unsigned Alignment , MachineMemOperand::Flags Flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore, uint64_t Size = 0, const AAMDNodes &AAInfo = AAMDNodes()) |
1181 | inline SDValue getMemIntrinsicNode([[deprecated("")]] inline SDValue getMemIntrinsicNode( unsigned Opcode, const SDLoc &dl, SDVTList VTList, ArrayRef<SDValue > Ops, EVT MemVT, MachinePointerInfo PtrInfo, unsigned Alignment , MachineMemOperand::Flags Flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore, uint64_t Size = 0, const AAMDNodes &AAInfo = AAMDNodes()) |
1182 | unsigned Opcode, const SDLoc &dl, SDVTList VTList,[[deprecated("")]] inline SDValue getMemIntrinsicNode( unsigned Opcode, const SDLoc &dl, SDVTList VTList, ArrayRef<SDValue > Ops, EVT MemVT, MachinePointerInfo PtrInfo, unsigned Alignment , MachineMemOperand::Flags Flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore, uint64_t Size = 0, const AAMDNodes &AAInfo = AAMDNodes()) |
1183 | ArrayRef<SDValue> Ops, EVT MemVT, MachinePointerInfo PtrInfo,[[deprecated("")]] inline SDValue getMemIntrinsicNode( unsigned Opcode, const SDLoc &dl, SDVTList VTList, ArrayRef<SDValue > Ops, EVT MemVT, MachinePointerInfo PtrInfo, unsigned Alignment , MachineMemOperand::Flags Flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore, uint64_t Size = 0, const AAMDNodes &AAInfo = AAMDNodes()) |
1184 | unsigned Alignment,[[deprecated("")]] inline SDValue getMemIntrinsicNode( unsigned Opcode, const SDLoc &dl, SDVTList VTList, ArrayRef<SDValue > Ops, EVT MemVT, MachinePointerInfo PtrInfo, unsigned Alignment , MachineMemOperand::Flags Flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore, uint64_t Size = 0, const AAMDNodes &AAInfo = AAMDNodes()) |
1185 | MachineMemOperand::Flags Flags = MachineMemOperand::MOLoad |[[deprecated("")]] inline SDValue getMemIntrinsicNode( unsigned Opcode, const SDLoc &dl, SDVTList VTList, ArrayRef<SDValue > Ops, EVT MemVT, MachinePointerInfo PtrInfo, unsigned Alignment , MachineMemOperand::Flags Flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore, uint64_t Size = 0, const AAMDNodes &AAInfo = AAMDNodes()) |
1186 | MachineMemOperand::MOStore,[[deprecated("")]] inline SDValue getMemIntrinsicNode( unsigned Opcode, const SDLoc &dl, SDVTList VTList, ArrayRef<SDValue > Ops, EVT MemVT, MachinePointerInfo PtrInfo, unsigned Alignment , MachineMemOperand::Flags Flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore, uint64_t Size = 0, const AAMDNodes &AAInfo = AAMDNodes()) |
1187 | uint64_t Size = 0, const AAMDNodes &AAInfo = AAMDNodes()),[[deprecated("")]] inline SDValue getMemIntrinsicNode( unsigned Opcode, const SDLoc &dl, SDVTList VTList, ArrayRef<SDValue > Ops, EVT MemVT, MachinePointerInfo PtrInfo, unsigned Alignment , MachineMemOperand::Flags Flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore, uint64_t Size = 0, const AAMDNodes &AAInfo = AAMDNodes()) |
1188 | "")[[deprecated("")]] inline SDValue getMemIntrinsicNode( unsigned Opcode, const SDLoc &dl, SDVTList VTList, ArrayRef<SDValue > Ops, EVT MemVT, MachinePointerInfo PtrInfo, unsigned Alignment , MachineMemOperand::Flags Flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore, uint64_t Size = 0, const AAMDNodes &AAInfo = AAMDNodes()) { |
1189 | return getMemIntrinsicNode(Opcode, dl, VTList, Ops, MemVT, PtrInfo, |
1190 | MaybeAlign(Alignment), Flags, Size, AAInfo); |
1191 | } |
1192 | |
1193 | SDValue getMemIntrinsicNode(unsigned Opcode, const SDLoc &dl, SDVTList VTList, |
1194 | ArrayRef<SDValue> Ops, EVT MemVT, |
1195 | MachineMemOperand *MMO); |
1196 | |
1197 | /// Creates a LifetimeSDNode that starts (`IsStart==true`) or ends |
1198 | /// (`IsStart==false`) the lifetime of the portion of `FrameIndex` between |
1199 | /// offsets `Offset` and `Offset + Size`. |
1200 | SDValue getLifetimeNode(bool IsStart, const SDLoc &dl, SDValue Chain, |
1201 | int FrameIndex, int64_t Size, int64_t Offset = -1); |
1202 | |
1203 | /// Creates a PseudoProbeSDNode with function GUID `Guid` and |
1204 | /// the index of the block `Index` it is probing, as well as the attributes |
1205 | /// `attr` of the probe. |
1206 | SDValue getPseudoProbeNode(const SDLoc &Dl, SDValue Chain, uint64_t Guid, |
1207 | uint64_t Index, uint32_t Attr); |
1208 | |
1209 | /// Create a MERGE_VALUES node from the given operands. |
1210 | SDValue getMergeValues(ArrayRef<SDValue> Ops, const SDLoc &dl); |
1211 | |
1212 | /// Loads are not normal binary operators: their result type is not |
1213 | /// determined by their operands, and they produce a value AND a token chain. |
1214 | /// |
1215 | /// This function will set the MOLoad flag on MMOFlags, but you can set it if |
1216 | /// you want. The MOStore flag must not be set. |
1217 | SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, |
1218 | MachinePointerInfo PtrInfo, |
1219 | MaybeAlign Alignment = MaybeAlign(), |
1220 | MachineMemOperand::Flags MMOFlags = MachineMemOperand::MONone, |
1221 | const AAMDNodes &AAInfo = AAMDNodes(), |
1222 | const MDNode *Ranges = nullptr); |
1223 | /// FIXME: Remove once transition to Align is over. |
1224 | inline SDValue |
1225 | getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, |
1226 | MachinePointerInfo PtrInfo, unsigned Alignment, |
1227 | MachineMemOperand::Flags MMOFlags = MachineMemOperand::MONone, |
1228 | const AAMDNodes &AAInfo = AAMDNodes(), |
1229 | const MDNode *Ranges = nullptr) { |
1230 | return getLoad(VT, dl, Chain, Ptr, PtrInfo, MaybeAlign(Alignment), MMOFlags, |
1231 | AAInfo, Ranges); |
1232 | } |
1233 | SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, |
1234 | MachineMemOperand *MMO); |
1235 | SDValue |
1236 | getExtLoad(ISD::LoadExtType ExtType, const SDLoc &dl, EVT VT, SDValue Chain, |
1237 | SDValue Ptr, MachinePointerInfo PtrInfo, EVT MemVT, |
1238 | MaybeAlign Alignment = MaybeAlign(), |
1239 | MachineMemOperand::Flags MMOFlags = MachineMemOperand::MONone, |
1240 | const AAMDNodes &AAInfo = AAMDNodes()); |
1241 | /// FIXME: Remove once transition to Align is over. |
1242 | inline SDValue |
1243 | getExtLoad(ISD::LoadExtType ExtType, const SDLoc &dl, EVT VT, SDValue Chain, |
1244 | SDValue Ptr, MachinePointerInfo PtrInfo, EVT MemVT, |
1245 | unsigned Alignment, |
1246 | MachineMemOperand::Flags MMOFlags = MachineMemOperand::MONone, |
1247 | const AAMDNodes &AAInfo = AAMDNodes()) { |
1248 | return getExtLoad(ExtType, dl, VT, Chain, Ptr, PtrInfo, MemVT, |
1249 | MaybeAlign(Alignment), MMOFlags, AAInfo); |
1250 | } |
1251 | SDValue getExtLoad(ISD::LoadExtType ExtType, const SDLoc &dl, EVT VT, |
1252 | SDValue Chain, SDValue Ptr, EVT MemVT, |
1253 | MachineMemOperand *MMO); |
1254 | SDValue getIndexedLoad(SDValue OrigLoad, const SDLoc &dl, SDValue Base, |
1255 | SDValue Offset, ISD::MemIndexedMode AM); |
1256 | SDValue getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT, |
1257 | const SDLoc &dl, SDValue Chain, SDValue Ptr, SDValue Offset, |
1258 | MachinePointerInfo PtrInfo, EVT MemVT, Align Alignment, |
1259 | MachineMemOperand::Flags MMOFlags = MachineMemOperand::MONone, |
1260 | const AAMDNodes &AAInfo = AAMDNodes(), |
1261 | const MDNode *Ranges = nullptr); |
1262 | inline SDValue getLoad( |
1263 | ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT, const SDLoc &dl, |
1264 | SDValue Chain, SDValue Ptr, SDValue Offset, MachinePointerInfo PtrInfo, |
1265 | EVT MemVT, MaybeAlign Alignment = MaybeAlign(), |
1266 | MachineMemOperand::Flags MMOFlags = MachineMemOperand::MONone, |
1267 | const AAMDNodes &AAInfo = AAMDNodes(), const MDNode *Ranges = nullptr) { |
1268 | // Ensures that codegen never sees a None Alignment. |
1269 | return getLoad(AM, ExtType, VT, dl, Chain, Ptr, Offset, PtrInfo, MemVT, |
1270 | Alignment.getValueOr(getEVTAlign(MemVT)), MMOFlags, AAInfo, |
1271 | Ranges); |
1272 | } |
1273 | /// FIXME: Remove once transition to Align is over. |
1274 | inline SDValue |
1275 | getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT, |
1276 | const SDLoc &dl, SDValue Chain, SDValue Ptr, SDValue Offset, |
1277 | MachinePointerInfo PtrInfo, EVT MemVT, unsigned Alignment, |
1278 | MachineMemOperand::Flags MMOFlags = MachineMemOperand::MONone, |
1279 | const AAMDNodes &AAInfo = AAMDNodes(), |
1280 | const MDNode *Ranges = nullptr) { |
1281 | return getLoad(AM, ExtType, VT, dl, Chain, Ptr, Offset, PtrInfo, MemVT, |
1282 | MaybeAlign(Alignment), MMOFlags, AAInfo, Ranges); |
1283 | } |
1284 | SDValue getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT, |
1285 | const SDLoc &dl, SDValue Chain, SDValue Ptr, SDValue Offset, |
1286 | EVT MemVT, MachineMemOperand *MMO); |
1287 | |
1288 | /// Helper function to build ISD::STORE nodes. |
1289 | /// |
1290 | /// This function will set the MOStore flag on MMOFlags, but you can set it if |
1291 | /// you want. The MOLoad and MOInvariant flags must not be set. |
1292 | |
1293 | SDValue |
1294 | getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, |
1295 | MachinePointerInfo PtrInfo, Align Alignment, |
1296 | MachineMemOperand::Flags MMOFlags = MachineMemOperand::MONone, |
1297 | const AAMDNodes &AAInfo = AAMDNodes()); |
1298 | inline SDValue |
1299 | getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, |
1300 | MachinePointerInfo PtrInfo, MaybeAlign Alignment = MaybeAlign(), |
1301 | MachineMemOperand::Flags MMOFlags = MachineMemOperand::MONone, |
1302 | const AAMDNodes &AAInfo = AAMDNodes()) { |
1303 | return getStore(Chain, dl, Val, Ptr, PtrInfo, |
1304 | Alignment.getValueOr(getEVTAlign(Val.getValueType())), |
1305 | MMOFlags, AAInfo); |
1306 | } |
1307 | /// FIXME: Remove once transition to Align is over. |
1308 | inline SDValue |
1309 | getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, |
1310 | MachinePointerInfo PtrInfo, unsigned Alignment, |
1311 | MachineMemOperand::Flags MMOFlags = MachineMemOperand::MONone, |
1312 | const AAMDNodes &AAInfo = AAMDNodes()) { |
1313 | return getStore(Chain, dl, Val, Ptr, PtrInfo, MaybeAlign(Alignment), |
1314 | MMOFlags, AAInfo); |
1315 | } |
1316 | SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, |
1317 | MachineMemOperand *MMO); |
1318 | SDValue |
1319 | getTruncStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, |
1320 | MachinePointerInfo PtrInfo, EVT SVT, Align Alignment, |
1321 | MachineMemOperand::Flags MMOFlags = MachineMemOperand::MONone, |
1322 | const AAMDNodes &AAInfo = AAMDNodes()); |
1323 | inline SDValue |
1324 | getTruncStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, |
1325 | MachinePointerInfo PtrInfo, EVT SVT, |
1326 | MaybeAlign Alignment = MaybeAlign(), |
1327 | MachineMemOperand::Flags MMOFlags = MachineMemOperand::MONone, |
1328 | const AAMDNodes &AAInfo = AAMDNodes()) { |
1329 | return getTruncStore(Chain, dl, Val, Ptr, PtrInfo, SVT, |
1330 | Alignment.getValueOr(getEVTAlign(SVT)), MMOFlags, |
1331 | AAInfo); |
1332 | } |
1333 | /// FIXME: Remove once transition to Align is over. |
1334 | inline SDValue |
1335 | getTruncStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, |
1336 | MachinePointerInfo PtrInfo, EVT SVT, unsigned Alignment, |
1337 | MachineMemOperand::Flags MMOFlags = MachineMemOperand::MONone, |
1338 | const AAMDNodes &AAInfo = AAMDNodes()) { |
1339 | return getTruncStore(Chain, dl, Val, Ptr, PtrInfo, SVT, |
1340 | MaybeAlign(Alignment), MMOFlags, AAInfo); |
1341 | } |
1342 | SDValue getTruncStore(SDValue Chain, const SDLoc &dl, SDValue Val, |
1343 | SDValue Ptr, EVT SVT, MachineMemOperand *MMO); |
1344 | SDValue getIndexedStore(SDValue OrigStore, const SDLoc &dl, SDValue Base, |
1345 | SDValue Offset, ISD::MemIndexedMode AM); |
1346 | |
1347 | SDValue getMaskedLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Base, |
1348 | SDValue Offset, SDValue Mask, SDValue Src0, EVT MemVT, |
1349 | MachineMemOperand *MMO, ISD::MemIndexedMode AM, |
1350 | ISD::LoadExtType, bool IsExpanding = false); |
1351 | SDValue getIndexedMaskedLoad(SDValue OrigLoad, const SDLoc &dl, SDValue Base, |
1352 | SDValue Offset, ISD::MemIndexedMode AM); |
1353 | SDValue getMaskedStore(SDValue Chain, const SDLoc &dl, SDValue Val, |
1354 | SDValue Base, SDValue Offset, SDValue Mask, EVT MemVT, |
1355 | MachineMemOperand *MMO, ISD::MemIndexedMode AM, |
1356 | bool IsTruncating = false, bool IsCompressing = false); |
1357 | SDValue getIndexedMaskedStore(SDValue OrigStore, const SDLoc &dl, |
1358 | SDValue Base, SDValue Offset, |
1359 | ISD::MemIndexedMode AM); |
1360 | SDValue getMaskedGather(SDVTList VTs, EVT VT, const SDLoc &dl, |
1361 | ArrayRef<SDValue> Ops, MachineMemOperand *MMO, |
1362 | ISD::MemIndexType IndexType, ISD::LoadExtType ExtTy); |
1363 | SDValue getMaskedScatter(SDVTList VTs, EVT VT, const SDLoc &dl, |
1364 | ArrayRef<SDValue> Ops, MachineMemOperand *MMO, |
1365 | ISD::MemIndexType IndexType, |
1366 | bool IsTruncating = false); |
1367 | |
1368 | /// Construct a node to track a Value* through the backend. |
1369 | SDValue getSrcValue(const Value *v); |
1370 | |
1371 | /// Return an MDNodeSDNode which holds an MDNode. |
1372 | SDValue getMDNode(const MDNode *MD); |
1373 | |
1374 | /// Return a bitcast using the SDLoc of the value operand, and casting to the |
1375 | /// provided type. Use getNode to set a custom SDLoc. |
1376 | SDValue getBitcast(EVT VT, SDValue V); |
1377 | |
1378 | /// Return an AddrSpaceCastSDNode. |
1379 | SDValue getAddrSpaceCast(const SDLoc &dl, EVT VT, SDValue Ptr, unsigned SrcAS, |
1380 | unsigned DestAS); |
1381 | |
1382 | /// Return a freeze using the SDLoc of the value operand. |
1383 | SDValue getFreeze(SDValue V); |
1384 | |
1385 | /// Return an AssertAlignSDNode. |
1386 | SDValue getAssertAlign(const SDLoc &DL, SDValue V, Align A); |
1387 | |
1388 | /// Return the specified value casted to |
1389 | /// the target's desired shift amount type. |
1390 | SDValue getShiftAmountOperand(EVT LHSTy, SDValue Op); |
1391 | |
1392 | /// Expand the specified \c ISD::VAARG node as the Legalize pass would. |
1393 | SDValue expandVAArg(SDNode *Node); |
1394 | |
1395 | /// Expand the specified \c ISD::VACOPY node as the Legalize pass would. |
1396 | SDValue expandVACopy(SDNode *Node); |
1397 | |
1398 | /// Returs an GlobalAddress of the function from the current module with |
1399 | /// name matching the given ExternalSymbol. Additionally can provide the |
1400 | /// matched function. |
1401 | /// Panics the function doesn't exists. |
1402 | SDValue getSymbolFunctionGlobalAddress(SDValue Op, |
1403 | Function **TargetFunction = nullptr); |
1404 | |
1405 | /// *Mutate* the specified node in-place to have the |
1406 | /// specified operands. If the resultant node already exists in the DAG, |
1407 | /// this does not modify the specified node, instead it returns the node that |
1408 | /// already exists. If the resultant node does not exist in the DAG, the |
1409 | /// input node is returned. As a degenerate case, if you specify the same |
1410 | /// input operands as the node already has, the input node is returned. |
1411 | SDNode *UpdateNodeOperands(SDNode *N, SDValue Op); |
1412 | SDNode *UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2); |
1413 | SDNode *UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2, |
1414 | SDValue Op3); |
1415 | SDNode *UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2, |
1416 | SDValue Op3, SDValue Op4); |
1417 | SDNode *UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2, |
1418 | SDValue Op3, SDValue Op4, SDValue Op5); |
1419 | SDNode *UpdateNodeOperands(SDNode *N, ArrayRef<SDValue> Ops); |
1420 | |
1421 | /// Creates a new TokenFactor containing \p Vals. If \p Vals contains 64k |
1422 | /// values or more, move values into new TokenFactors in 64k-1 blocks, until |
1423 | /// the final TokenFactor has less than 64k operands. |
1424 | SDValue getTokenFactor(const SDLoc &DL, SmallVectorImpl<SDValue> &Vals); |
1425 | |
1426 | /// *Mutate* the specified machine node's memory references to the provided |
1427 | /// list. |
1428 | void setNodeMemRefs(MachineSDNode *N, |
1429 | ArrayRef<MachineMemOperand *> NewMemRefs); |
1430 | |
1431 | // Calculate divergence of node \p N based on its operands. |
1432 | bool calculateDivergence(SDNode *N); |
1433 | |
1434 | // Propagates the change in divergence to users |
1435 | void updateDivergence(SDNode * N); |
1436 | |
1437 | /// These are used for target selectors to *mutate* the |
1438 | /// specified node to have the specified return type, Target opcode, and |
1439 | /// operands. Note that target opcodes are stored as |
1440 | /// ~TargetOpcode in the node opcode field. The resultant node is returned. |
1441 | SDNode *SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT); |
1442 | SDNode *SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT, SDValue Op1); |
1443 | SDNode *SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT, |
1444 | SDValue Op1, SDValue Op2); |
1445 | SDNode *SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT, |
1446 | SDValue Op1, SDValue Op2, SDValue Op3); |
1447 | SDNode *SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT, |
1448 | ArrayRef<SDValue> Ops); |
1449 | SDNode *SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT1, EVT VT2); |
1450 | SDNode *SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT1, |
1451 | EVT VT2, ArrayRef<SDValue> Ops); |
1452 | SDNode *SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT1, |
1453 | EVT VT2, EVT VT3, ArrayRef<SDValue> Ops); |
1454 | SDNode *SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT1, |
1455 | EVT VT2, SDValue Op1, SDValue Op2); |
1456 | SDNode *SelectNodeTo(SDNode *N, unsigned MachineOpc, SDVTList VTs, |
1457 | ArrayRef<SDValue> Ops); |
1458 | |
1459 | /// This *mutates* the specified node to have the specified |
1460 | /// return type, opcode, and operands. |
1461 | SDNode *MorphNodeTo(SDNode *N, unsigned Opc, SDVTList VTs, |
1462 | ArrayRef<SDValue> Ops); |
1463 | |
1464 | /// Mutate the specified strict FP node to its non-strict equivalent, |
1465 | /// unlinking the node from its chain and dropping the metadata arguments. |
1466 | /// The node must be a strict FP node. |
1467 | SDNode *mutateStrictFPToFP(SDNode *Node); |
1468 | |
1469 | /// These are used for target selectors to create a new node |
1470 | /// with specified return type(s), MachineInstr opcode, and operands. |
1471 | /// |
1472 | /// Note that getMachineNode returns the resultant node. If there is already |
1473 | /// a node of the specified opcode and operands, it returns that node instead |
1474 | /// of the current one. |
1475 | MachineSDNode *getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT); |
1476 | MachineSDNode *getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT, |
1477 | SDValue Op1); |
1478 | MachineSDNode *getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT, |
1479 | SDValue Op1, SDValue Op2); |
1480 | MachineSDNode *getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT, |
1481 | SDValue Op1, SDValue Op2, SDValue Op3); |
1482 | MachineSDNode *getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT, |
1483 | ArrayRef<SDValue> Ops); |
1484 | MachineSDNode *getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT1, |
1485 | EVT VT2, SDValue Op1, SDValue Op2); |
1486 | MachineSDNode *getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT1, |
1487 | EVT VT2, SDValue Op1, SDValue Op2, SDValue Op3); |
1488 | MachineSDNode *getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT1, |
1489 | EVT VT2, ArrayRef<SDValue> Ops); |
1490 | MachineSDNode *getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT1, |
1491 | EVT VT2, EVT VT3, SDValue Op1, SDValue Op2); |
1492 | MachineSDNode *getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT1, |
1493 | EVT VT2, EVT VT3, SDValue Op1, SDValue Op2, |
1494 | SDValue Op3); |
1495 | MachineSDNode *getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT1, |
1496 | EVT VT2, EVT VT3, ArrayRef<SDValue> Ops); |
1497 | MachineSDNode *getMachineNode(unsigned Opcode, const SDLoc &dl, |
1498 | ArrayRef<EVT> ResultTys, ArrayRef<SDValue> Ops); |
1499 | MachineSDNode *getMachineNode(unsigned Opcode, const SDLoc &dl, SDVTList VTs, |
1500 | ArrayRef<SDValue> Ops); |
1501 | |
1502 | /// A convenience function for creating TargetInstrInfo::EXTRACT_SUBREG nodes. |
1503 | SDValue getTargetExtractSubreg(int SRIdx, const SDLoc &DL, EVT VT, |
1504 | SDValue Operand); |
1505 | |
1506 | /// A convenience function for creating TargetInstrInfo::INSERT_SUBREG nodes. |
1507 | SDValue getTargetInsertSubreg(int SRIdx, const SDLoc &DL, EVT VT, |
1508 | SDValue Operand, SDValue Subreg); |
1509 | |
1510 | /// Get the specified node if it's already available, or else return NULL. |
1511 | SDNode *getNodeIfExists(unsigned Opcode, SDVTList VTList, |
1512 | ArrayRef<SDValue> Ops, const SDNodeFlags Flags); |
1513 | SDNode *getNodeIfExists(unsigned Opcode, SDVTList VTList, |
1514 | ArrayRef<SDValue> Ops); |
1515 | |
1516 | /// Check if a node exists without modifying its flags. |
1517 | bool doesNodeExist(unsigned Opcode, SDVTList VTList, ArrayRef<SDValue> Ops); |
1518 | |
1519 | /// Creates a SDDbgValue node. |
1520 | SDDbgValue *getDbgValue(DIVariable *Var, DIExpression *Expr, SDNode *N, |
1521 | unsigned R, bool IsIndirect, const DebugLoc &DL, |
1522 | unsigned O); |
1523 | |
1524 | /// Creates a constant SDDbgValue node. |
1525 | SDDbgValue *getConstantDbgValue(DIVariable *Var, DIExpression *Expr, |
1526 | const Value *C, const DebugLoc &DL, |
1527 | unsigned O); |
1528 | |
1529 | /// Creates a FrameIndex SDDbgValue node. |
1530 | SDDbgValue *getFrameIndexDbgValue(DIVariable *Var, DIExpression *Expr, |
1531 | unsigned FI, bool IsIndirect, |
1532 | const DebugLoc &DL, unsigned O); |
1533 | |
1534 | /// Creates a FrameIndex SDDbgValue node. |
1535 | SDDbgValue *getFrameIndexDbgValue(DIVariable *Var, DIExpression *Expr, |
1536 | unsigned FI, |
1537 | ArrayRef<SDNode *> Dependencies, |
1538 | bool IsIndirect, const DebugLoc &DL, |
1539 | unsigned O); |
1540 | |
1541 | /// Creates a VReg SDDbgValue node. |
1542 | SDDbgValue *getVRegDbgValue(DIVariable *Var, DIExpression *Expr, |
1543 | unsigned VReg, bool IsIndirect, |
1544 | const DebugLoc &DL, unsigned O); |
1545 | |
1546 | /// Creates a SDDbgValue node from a list of locations. |
1547 | SDDbgValue *getDbgValueList(DIVariable *Var, DIExpression *Expr, |
1548 | ArrayRef<SDDbgOperand> Locs, |
1549 | ArrayRef<SDNode *> Dependencies, bool IsIndirect, |
1550 | const DebugLoc &DL, unsigned O, bool IsVariadic); |
1551 | |
1552 | /// Creates a SDDbgLabel node. |
1553 | SDDbgLabel *getDbgLabel(DILabel *Label, const DebugLoc &DL, unsigned O); |
1554 | |
1555 | /// Transfer debug values from one node to another, while optionally |
1556 | /// generating fragment expressions for split-up values. If \p InvalidateDbg |
1557 | /// is set, debug values are invalidated after they are transferred. |
1558 | void transferDbgValues(SDValue From, SDValue To, unsigned OffsetInBits = 0, |
1559 | unsigned SizeInBits = 0, bool InvalidateDbg = true); |
1560 | |
1561 | /// Remove the specified node from the system. If any of its |
1562 | /// operands then becomes dead, remove them as well. Inform UpdateListener |
1563 | /// for each node deleted. |
1564 | void RemoveDeadNode(SDNode *N); |
1565 | |
1566 | /// This method deletes the unreachable nodes in the |
1567 | /// given list, and any nodes that become unreachable as a result. |
1568 | void RemoveDeadNodes(SmallVectorImpl<SDNode *> &DeadNodes); |
1569 | |
1570 | /// Modify anything using 'From' to use 'To' instead. |
1571 | /// This can cause recursive merging of nodes in the DAG. Use the first |
1572 | /// version if 'From' is known to have a single result, use the second |
1573 | /// if you have two nodes with identical results (or if 'To' has a superset |
1574 | /// of the results of 'From'), use the third otherwise. |
1575 | /// |
1576 | /// These methods all take an optional UpdateListener, which (if not null) is |
1577 | /// informed about nodes that are deleted and modified due to recursive |
1578 | /// changes in the dag. |
1579 | /// |
1580 | /// These functions only replace all existing uses. It's possible that as |
1581 | /// these replacements are being performed, CSE may cause the From node |
1582 | /// to be given new uses. These new uses of From are left in place, and |
1583 | /// not automatically transferred to To. |
1584 | /// |
1585 | void ReplaceAllUsesWith(SDValue From, SDValue To); |
1586 | void ReplaceAllUsesWith(SDNode *From, SDNode *To); |
1587 | void ReplaceAllUsesWith(SDNode *From, const SDValue *To); |
1588 | |
1589 | /// Replace any uses of From with To, leaving |
1590 | /// uses of other values produced by From.getNode() alone. |
1591 | void ReplaceAllUsesOfValueWith(SDValue From, SDValue To); |
1592 | |
1593 | /// Like ReplaceAllUsesOfValueWith, but for multiple values at once. |
1594 | /// This correctly handles the case where |
1595 | /// there is an overlap between the From values and the To values. |
1596 | void ReplaceAllUsesOfValuesWith(const SDValue *From, const SDValue *To, |
1597 | unsigned Num); |
1598 | |
1599 | /// If an existing load has uses of its chain, create a token factor node with |
1600 | /// that chain and the new memory node's chain and update users of the old |
1601 | /// chain to the token factor. This ensures that the new memory node will have |
1602 | /// the same relative memory dependency position as the old load. Returns the |
1603 | /// new merged load chain. |
1604 | SDValue makeEquivalentMemoryOrdering(SDValue OldChain, SDValue NewMemOpChain); |
1605 | |
1606 | /// If an existing load has uses of its chain, create a token factor node with |
1607 | /// that chain and the new memory node's chain and update users of the old |
1608 | /// chain to the token factor. This ensures that the new memory node will have |
1609 | /// the same relative memory dependency position as the old load. Returns the |
1610 | /// new merged load chain. |
1611 | SDValue makeEquivalentMemoryOrdering(LoadSDNode *OldLoad, SDValue NewMemOp); |
1612 | |
1613 | /// Topological-sort the AllNodes list and a |
1614 | /// assign a unique node id for each node in the DAG based on their |
1615 | /// topological order. Returns the number of nodes. |
1616 | unsigned AssignTopologicalOrder(); |
1617 | |
1618 | /// Move node N in the AllNodes list to be immediately |
1619 | /// before the given iterator Position. This may be used to update the |
1620 | /// topological ordering when the list of nodes is modified. |
1621 | void RepositionNode(allnodes_iterator Position, SDNode *N) { |
1622 | AllNodes.insert(Position, AllNodes.remove(N)); |
1623 | } |
1624 | |
1625 | /// Returns an APFloat semantics tag appropriate for the given type. If VT is |
1626 | /// a vector type, the element semantics are returned. |
1627 | static const fltSemantics &EVTToAPFloatSemantics(EVT VT) { |
1628 | switch (VT.getScalarType().getSimpleVT().SimpleTy) { |
1629 | default: llvm_unreachable("Unknown FP format")::llvm::llvm_unreachable_internal("Unknown FP format", "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/CodeGen/SelectionDAG.h" , 1629); |
1630 | case MVT::f16: return APFloat::IEEEhalf(); |
1631 | case MVT::bf16: return APFloat::BFloat(); |
1632 | case MVT::f32: return APFloat::IEEEsingle(); |
1633 | case MVT::f64: return APFloat::IEEEdouble(); |
1634 | case MVT::f80: return APFloat::x87DoubleExtended(); |
1635 | case MVT::f128: return APFloat::IEEEquad(); |
1636 | case MVT::ppcf128: return APFloat::PPCDoubleDouble(); |
1637 | } |
1638 | } |
1639 | |
1640 | /// Add a dbg_value SDNode. If SD is non-null that means the |
1641 | /// value is produced by SD. |
1642 | void AddDbgValue(SDDbgValue *DB, bool isParameter); |
1643 | |
1644 | /// Add a dbg_label SDNode. |
1645 | void AddDbgLabel(SDDbgLabel *DB); |
1646 | |
1647 | /// Get the debug values which reference the given SDNode. |
1648 | ArrayRef<SDDbgValue*> GetDbgValues(const SDNode* SD) const { |
1649 | return DbgInfo->getSDDbgValues(SD); |
1650 | } |
1651 | |
1652 | public: |
1653 | /// Return true if there are any SDDbgValue nodes associated |
1654 | /// with this SelectionDAG. |
1655 | bool hasDebugValues() const { return !DbgInfo->empty(); } |
1656 | |
1657 | SDDbgInfo::DbgIterator DbgBegin() const { return DbgInfo->DbgBegin(); } |
1658 | SDDbgInfo::DbgIterator DbgEnd() const { return DbgInfo->DbgEnd(); } |
1659 | |
1660 | SDDbgInfo::DbgIterator ByvalParmDbgBegin() const { |
1661 | return DbgInfo->ByvalParmDbgBegin(); |
1662 | } |
1663 | SDDbgInfo::DbgIterator ByvalParmDbgEnd() const { |
1664 | return DbgInfo->ByvalParmDbgEnd(); |
1665 | } |
1666 | |
1667 | SDDbgInfo::DbgLabelIterator DbgLabelBegin() const { |
1668 | return DbgInfo->DbgLabelBegin(); |
1669 | } |
1670 | SDDbgInfo::DbgLabelIterator DbgLabelEnd() const { |
1671 | return DbgInfo->DbgLabelEnd(); |
1672 | } |
1673 | |
1674 | /// To be invoked on an SDNode that is slated to be erased. This |
1675 | /// function mirrors \c llvm::salvageDebugInfo. |
1676 | void salvageDebugInfo(SDNode &N); |
1677 | |
1678 | void dump() const; |
1679 | |
1680 | /// In most cases this function returns the ABI alignment for a given type, |
1681 | /// except for illegal vector types where the alignment exceeds that of the |
1682 | /// stack. In such cases we attempt to break the vector down to a legal type |
1683 | /// and return the ABI alignment for that instead. |
1684 | Align getReducedAlign(EVT VT, bool UseABI); |
1685 | |
1686 | /// Create a stack temporary based on the size in bytes and the alignment |
1687 | SDValue CreateStackTemporary(TypeSize Bytes, Align Alignment); |
1688 | |
1689 | /// Create a stack temporary, suitable for holding the specified value type. |
1690 | /// If minAlign is specified, the slot size will have at least that alignment. |
1691 | SDValue CreateStackTemporary(EVT VT, unsigned minAlign = 1); |
1692 | |
1693 | /// Create a stack temporary suitable for holding either of the specified |
1694 | /// value types. |
1695 | SDValue CreateStackTemporary(EVT VT1, EVT VT2); |
1696 | |
1697 | SDValue FoldSymbolOffset(unsigned Opcode, EVT VT, |
1698 | const GlobalAddressSDNode *GA, |
1699 | const SDNode *N2); |
1700 | |
1701 | SDValue FoldConstantArithmetic(unsigned Opcode, const SDLoc &DL, EVT VT, |
1702 | ArrayRef<SDValue> Ops); |
1703 | |
1704 | SDValue FoldConstantVectorArithmetic(unsigned Opcode, const SDLoc &DL, EVT VT, |
1705 | ArrayRef<SDValue> Ops, |
1706 | const SDNodeFlags Flags = SDNodeFlags()); |
1707 | |
1708 | /// Fold floating-point operations with 2 operands when both operands are |
1709 | /// constants and/or undefined. |
1710 | SDValue foldConstantFPMath(unsigned Opcode, const SDLoc &DL, EVT VT, |
1711 | SDValue N1, SDValue N2); |
1712 | |
1713 | /// Constant fold a setcc to true or false. |
1714 | SDValue FoldSetCC(EVT VT, SDValue N1, SDValue N2, ISD::CondCode Cond, |
1715 | const SDLoc &dl); |
1716 | |
1717 | /// See if the specified operand can be simplified with the knowledge that |
1718 | /// only the bits specified by DemandedBits are used. If so, return the |
1719 | /// simpler operand, otherwise return a null SDValue. |
1720 | /// |
1721 | /// (This exists alongside SimplifyDemandedBits because GetDemandedBits can |
1722 | /// simplify nodes with multiple uses more aggressively.) |
1723 | SDValue GetDemandedBits(SDValue V, const APInt &DemandedBits); |
1724 | |
1725 | /// See if the specified operand can be simplified with the knowledge that |
1726 | /// only the bits specified by DemandedBits are used in the elements specified |
1727 | /// by DemandedElts. If so, return the simpler operand, otherwise return a |
1728 | /// null SDValue. |
1729 | /// |
1730 | /// (This exists alongside SimplifyDemandedBits because GetDemandedBits can |
1731 | /// simplify nodes with multiple uses more aggressively.) |
1732 | SDValue GetDemandedBits(SDValue V, const APInt &DemandedBits, |
1733 | const APInt &DemandedElts); |
1734 | |
1735 | /// Return true if the sign bit of Op is known to be zero. |
1736 | /// We use this predicate to simplify operations downstream. |
1737 | bool SignBitIsZero(SDValue Op, unsigned Depth = 0) const; |
1738 | |
1739 | /// Return true if 'Op & Mask' is known to be zero. We |
1740 | /// use this predicate to simplify operations downstream. Op and Mask are |
1741 | /// known to be the same type. |
1742 | bool MaskedValueIsZero(SDValue Op, const APInt &Mask, |
1743 | unsigned Depth = 0) const; |
1744 | |
1745 | /// Return true if 'Op & Mask' is known to be zero in DemandedElts. We |
1746 | /// use this predicate to simplify operations downstream. Op and Mask are |
1747 | /// known to be the same type. |
1748 | bool MaskedValueIsZero(SDValue Op, const APInt &Mask, |
1749 | const APInt &DemandedElts, unsigned Depth = 0) const; |
1750 | |
1751 | /// Return true if '(Op & Mask) == Mask'. |
1752 | /// Op and Mask are known to be the same type. |
1753 | bool MaskedValueIsAllOnes(SDValue Op, const APInt &Mask, |
1754 | unsigned Depth = 0) const; |
1755 | |
1756 | /// Determine which bits of Op are known to be either zero or one and return |
1757 | /// them in Known. For vectors, the known bits are those that are shared by |
1758 | /// every vector element. |
1759 | /// Targets can implement the computeKnownBitsForTargetNode method in the |
1760 | /// TargetLowering class to allow target nodes to be understood. |
1761 | KnownBits computeKnownBits(SDValue Op, unsigned Depth = 0) const; |
1762 | |
1763 | /// Determine which bits of Op are known to be either zero or one and return |
1764 | /// them in Known. The DemandedElts argument allows us to only collect the |
1765 | /// known bits that are shared by the requested vector elements. |
1766 | /// Targets can implement the computeKnownBitsForTargetNode method in the |
1767 | /// TargetLowering class to allow target nodes to be understood. |
1768 | KnownBits computeKnownBits(SDValue Op, const APInt &DemandedElts, |
1769 | unsigned Depth = 0) const; |
1770 | |
1771 | /// Used to represent the possible overflow behavior of an operation. |
1772 | /// Never: the operation cannot overflow. |
1773 | /// Always: the operation will always overflow. |
1774 | /// Sometime: the operation may or may not overflow. |
1775 | enum OverflowKind { |
1776 | OFK_Never, |
1777 | OFK_Sometime, |
1778 | OFK_Always, |
1779 | }; |
1780 | |
1781 | /// Determine if the result of the addition of 2 node can overflow. |
1782 | OverflowKind computeOverflowKind(SDValue N0, SDValue N1) const; |
1783 | |
1784 | /// Test if the given value is known to have exactly one bit set. This differs |
1785 | /// from computeKnownBits in that it doesn't necessarily determine which bit |
1786 | /// is set. |
1787 | bool isKnownToBeAPowerOfTwo(SDValue Val) const; |
1788 | |
1789 | /// Return the number of times the sign bit of the register is replicated into |
1790 | /// the other bits. We know that at least 1 bit is always equal to the sign |
1791 | /// bit (itself), but other cases can give us information. For example, |
1792 | /// immediately after an "SRA X, 2", we know that the top 3 bits are all equal |
1793 | /// to each other, so we return 3. Targets can implement the |
1794 | /// ComputeNumSignBitsForTarget method in the TargetLowering class to allow |
1795 | /// target nodes to be understood. |
1796 | unsigned ComputeNumSignBits(SDValue Op, unsigned Depth = 0) const; |
1797 | |
1798 | /// Return the number of times the sign bit of the register is replicated into |
1799 | /// the other bits. We know that at least 1 bit is always equal to the sign |
1800 | /// bit (itself), but other cases can give us information. For example, |
1801 | /// immediately after an "SRA X, 2", we know that the top 3 bits are all equal |
1802 | /// to each other, so we return 3. The DemandedElts argument allows |
1803 | /// us to only collect the minimum sign bits of the requested vector elements. |
1804 | /// Targets can implement the ComputeNumSignBitsForTarget method in the |
1805 | /// TargetLowering class to allow target nodes to be understood. |
1806 | unsigned ComputeNumSignBits(SDValue Op, const APInt &DemandedElts, |
1807 | unsigned Depth = 0) const; |
1808 | |
1809 | /// Return true if the specified operand is an ISD::ADD with a ConstantSDNode |
1810 | /// on the right-hand side, or if it is an ISD::OR with a ConstantSDNode that |
1811 | /// is guaranteed to have the same semantics as an ADD. This handles the |
1812 | /// equivalence: |
1813 | /// X|Cst == X+Cst iff X&Cst = 0. |
1814 | bool isBaseWithConstantOffset(SDValue Op) const; |
1815 | |
1816 | /// Test whether the given SDValue is known to never be NaN. If \p SNaN is |
1817 | /// true, returns if \p Op is known to never be a signaling NaN (it may still |
1818 | /// be a qNaN). |
1819 | bool isKnownNeverNaN(SDValue Op, bool SNaN = false, unsigned Depth = 0) const; |
1820 | |
1821 | /// \returns true if \p Op is known to never be a signaling NaN. |
1822 | bool isKnownNeverSNaN(SDValue Op, unsigned Depth = 0) const { |
1823 | return isKnownNeverNaN(Op, true, Depth); |
1824 | } |
1825 | |
1826 | /// Test whether the given floating point SDValue is known to never be |
1827 | /// positive or negative zero. |
1828 | bool isKnownNeverZeroFloat(SDValue Op) const; |
1829 | |
1830 | /// Test whether the given SDValue is known to contain non-zero value(s). |
1831 | bool isKnownNeverZero(SDValue Op) const; |
1832 | |
1833 | /// Test whether two SDValues are known to compare equal. This |
1834 | /// is true if they are the same value, or if one is negative zero and the |
1835 | /// other positive zero. |
1836 | bool isEqualTo(SDValue A, SDValue B) const; |
1837 | |
1838 | /// Return true if A and B have no common bits set. As an example, this can |
1839 | /// allow an 'add' to be transformed into an 'or'. |
1840 | bool haveNoCommonBitsSet(SDValue A, SDValue B) const; |
1841 | |
1842 | /// Test whether \p V has a splatted value for all the demanded elements. |
1843 | /// |
1844 | /// On success \p UndefElts will indicate the elements that have UNDEF |
1845 | /// values instead of the splat value, this is only guaranteed to be correct |
1846 | /// for \p DemandedElts. |
1847 | /// |
1848 | /// NOTE: The function will return true for a demanded splat of UNDEF values. |
1849 | bool isSplatValue(SDValue V, const APInt &DemandedElts, APInt &UndefElts, |
1850 | unsigned Depth = 0); |
1851 | |
1852 | /// Test whether \p V has a splatted value. |
1853 | bool isSplatValue(SDValue V, bool AllowUndefs = false); |
1854 | |
1855 | /// If V is a splatted value, return the source vector and its splat index. |
1856 | SDValue getSplatSourceVector(SDValue V, int &SplatIndex); |
1857 | |
1858 | /// If V is a splat vector, return its scalar source operand by extracting |
1859 | /// that element from the source vector. |
1860 | SDValue getSplatValue(SDValue V); |
1861 | |
1862 | /// If a SHL/SRA/SRL node \p V has a constant or splat constant shift amount |
1863 | /// that is less than the element bit-width of the shift node, return it. |
1864 | const APInt *getValidShiftAmountConstant(SDValue V, |
1865 | const APInt &DemandedElts) const; |
1866 | |
1867 | /// If a SHL/SRA/SRL node \p V has constant shift amounts that are all less |
1868 | /// than the element bit-width of the shift node, return the minimum value. |
1869 | const APInt * |
1870 | getValidMinimumShiftAmountConstant(SDValue V, |
1871 | const APInt &DemandedElts) const; |
1872 | |
1873 | /// If a SHL/SRA/SRL node \p V has constant shift amounts that are all less |
1874 | /// than the element bit-width of the shift node, return the maximum value. |
1875 | const APInt * |
1876 | getValidMaximumShiftAmountConstant(SDValue V, |
1877 | const APInt &DemandedElts) const; |
1878 | |
1879 | /// Match a binop + shuffle pyramid that represents a horizontal reduction |
1880 | /// over the elements of a vector starting from the EXTRACT_VECTOR_ELT node /p |
1881 | /// Extract. The reduction must use one of the opcodes listed in /p |
1882 | /// CandidateBinOps and on success /p BinOp will contain the matching opcode. |
1883 | /// Returns the vector that is being reduced on, or SDValue() if a reduction |
1884 | /// was not matched. If \p AllowPartials is set then in the case of a |
1885 | /// reduction pattern that only matches the first few stages, the extracted |
1886 | /// subvector of the start of the reduction is returned. |
1887 | SDValue matchBinOpReduction(SDNode *Extract, ISD::NodeType &BinOp, |
1888 | ArrayRef<ISD::NodeType> CandidateBinOps, |
1889 | bool AllowPartials = false); |
1890 | |
1891 | /// Utility function used by legalize and lowering to |
1892 | /// "unroll" a vector operation by splitting out the scalars and operating |
1893 | /// on each element individually. If the ResNE is 0, fully unroll the vector |
1894 | /// op. If ResNE is less than the width of the vector op, unroll up to ResNE. |
1895 | /// If the ResNE is greater than the width of the vector op, unroll the |
1896 | /// vector op and fill the end of the resulting vector with UNDEFS. |
1897 | SDValue UnrollVectorOp(SDNode *N, unsigned ResNE = 0); |
1898 | |
1899 | /// Like UnrollVectorOp(), but for the [US](ADD|SUB|MUL)O family of opcodes. |
1900 | /// This is a separate function because those opcodes have two results. |
1901 | std::pair<SDValue, SDValue> UnrollVectorOverflowOp(SDNode *N, |
1902 | unsigned ResNE = 0); |
1903 | |
1904 | /// Return true if loads are next to each other and can be |
1905 | /// merged. Check that both are nonvolatile and if LD is loading |
1906 | /// 'Bytes' bytes from a location that is 'Dist' units away from the |
1907 | /// location that the 'Base' load is loading from. |
1908 | bool areNonVolatileConsecutiveLoads(LoadSDNode *LD, LoadSDNode *Base, |
1909 | unsigned Bytes, int Dist) const; |
1910 | |
1911 | /// Infer alignment of a load / store address. Return None if it cannot be |
1912 | /// inferred. |
1913 | MaybeAlign InferPtrAlign(SDValue Ptr) const; |
1914 | |
1915 | LLVM_ATTRIBUTE_DEPRECATED(inline unsigned InferPtrAlignment(SDValue Ptr)[[deprecated("Use InferPtrAlign instead")]] inline unsigned InferPtrAlignment (SDValue Ptr) const |
1916 | const,[[deprecated("Use InferPtrAlign instead")]] inline unsigned InferPtrAlignment (SDValue Ptr) const |
1917 | "Use InferPtrAlign instead")[[deprecated("Use InferPtrAlign instead")]] inline unsigned InferPtrAlignment (SDValue Ptr) const { |
1918 | if (auto A = InferPtrAlign(Ptr)) |
1919 | return A->value(); |
1920 | return 0; |
1921 | } |
1922 | |
1923 | /// Compute the VTs needed for the low/hi parts of a type |
1924 | /// which is split (or expanded) into two not necessarily identical pieces. |
1925 | std::pair<EVT, EVT> GetSplitDestVTs(const EVT &VT) const; |
1926 | |
1927 | /// Compute the VTs needed for the low/hi parts of a type, dependent on an |
1928 | /// enveloping VT that has been split into two identical pieces. Sets the |
1929 | /// HisIsEmpty flag when hi type has zero storage size. |
1930 | std::pair<EVT, EVT> GetDependentSplitDestVTs(const EVT &VT, const EVT &EnvVT, |
1931 | bool *HiIsEmpty) const; |
1932 | |
1933 | /// Split the vector with EXTRACT_SUBVECTOR using the provides |
1934 | /// VTs and return the low/high part. |
1935 | std::pair<SDValue, SDValue> SplitVector(const SDValue &N, const SDLoc &DL, |
1936 | const EVT &LoVT, const EVT &HiVT); |
1937 | |
1938 | /// Split the vector with EXTRACT_SUBVECTOR and return the low/high part. |
1939 | std::pair<SDValue, SDValue> SplitVector(const SDValue &N, const SDLoc &DL) { |
1940 | EVT LoVT, HiVT; |
1941 | std::tie(LoVT, HiVT) = GetSplitDestVTs(N.getValueType()); |
1942 | return SplitVector(N, DL, LoVT, HiVT); |
1943 | } |
1944 | |
1945 | /// Split the node's operand with EXTRACT_SUBVECTOR and |
1946 | /// return the low/high part. |
1947 | std::pair<SDValue, SDValue> SplitVectorOperand(const SDNode *N, unsigned OpNo) |
1948 | { |
1949 | return SplitVector(N->getOperand(OpNo), SDLoc(N)); |
1950 | } |
1951 | |
1952 | /// Widen the vector up to the next power of two using INSERT_SUBVECTOR. |
1953 | SDValue WidenVector(const SDValue &N, const SDLoc &DL); |
1954 | |
1955 | /// Append the extracted elements from Start to Count out of the vector Op in |
1956 | /// Args. If Count is 0, all of the elements will be extracted. The extracted |
1957 | /// elements will have type EVT if it is provided, and otherwise their type |
1958 | /// will be Op's element type. |
1959 | void ExtractVectorElements(SDValue Op, SmallVectorImpl<SDValue> &Args, |
1960 | unsigned Start = 0, unsigned Count = 0, |
1961 | EVT EltVT = EVT()); |
1962 | |
1963 | /// Compute the default alignment value for the given type. |
1964 | Align getEVTAlign(EVT MemoryVT) const; |
1965 | /// Compute the default alignment value for the given type. |
1966 | /// FIXME: Remove once transition to Align is over. |
1967 | inline unsigned getEVTAlignment(EVT MemoryVT) const { |
1968 | return getEVTAlign(MemoryVT).value(); |
1969 | } |
1970 | |
1971 | /// Test whether the given value is a constant int or similar node. |
1972 | SDNode *isConstantIntBuildVectorOrConstantInt(SDValue N) const; |
1973 | |
1974 | /// Test whether the given value is a constant FP or similar node. |
1975 | SDNode *isConstantFPBuildVectorOrConstantFP(SDValue N) const ; |
1976 | |
1977 | /// \returns true if \p N is any kind of constant or build_vector of |
1978 | /// constants, int or float. If a vector, it may not necessarily be a splat. |
1979 | inline bool isConstantValueOfAnyType(SDValue N) const { |
1980 | return isConstantIntBuildVectorOrConstantInt(N) || |
1981 | isConstantFPBuildVectorOrConstantFP(N); |
1982 | } |
1983 | |
1984 | void addCallSiteInfo(const SDNode *CallNode, CallSiteInfoImpl &&CallInfo) { |
1985 | SDCallSiteDbgInfo[CallNode].CSInfo = std::move(CallInfo); |
1986 | } |
1987 | |
1988 | CallSiteInfo getSDCallSiteInfo(const SDNode *CallNode) { |
1989 | auto I = SDCallSiteDbgInfo.find(CallNode); |
1990 | if (I != SDCallSiteDbgInfo.end()) |
1991 | return std::move(I->second).CSInfo; |
1992 | return CallSiteInfo(); |
1993 | } |
1994 | |
1995 | void addHeapAllocSite(const SDNode *Node, MDNode *MD) { |
1996 | SDCallSiteDbgInfo[Node].HeapAllocSite = MD; |
1997 | } |
1998 | |
1999 | /// Return the HeapAllocSite type associated with the SDNode, if it exists. |
2000 | MDNode *getHeapAllocSite(const SDNode *Node) { |
2001 | auto It = SDCallSiteDbgInfo.find(Node); |
2002 | if (It == SDCallSiteDbgInfo.end()) |
2003 | return nullptr; |
2004 | return It->second.HeapAllocSite; |
2005 | } |
2006 | |
2007 | void addNoMergeSiteInfo(const SDNode *Node, bool NoMerge) { |
2008 | if (NoMerge) |
2009 | SDCallSiteDbgInfo[Node].NoMerge = NoMerge; |
2010 | } |
2011 | |
2012 | bool getNoMergeSiteInfo(const SDNode *Node) { |
2013 | auto I = SDCallSiteDbgInfo.find(Node); |
2014 | if (I == SDCallSiteDbgInfo.end()) |
2015 | return false; |
2016 | return I->second.NoMerge; |
2017 | } |
2018 | |
2019 | /// Return the current function's default denormal handling kind for the given |
2020 | /// floating point type. |
2021 | DenormalMode getDenormalMode(EVT VT) const { |
2022 | return MF->getDenormalMode(EVTToAPFloatSemantics(VT)); |
2023 | } |
2024 | |
2025 | bool shouldOptForSize() const; |
2026 | |
2027 | /// Get the (commutative) neutral element for the given opcode, if it exists. |
2028 | SDValue getNeutralElement(unsigned Opcode, const SDLoc &DL, EVT VT, |
2029 | SDNodeFlags Flags); |
2030 | |
2031 | private: |
2032 | void InsertNode(SDNode *N); |
2033 | bool RemoveNodeFromCSEMaps(SDNode *N); |
2034 | void AddModifiedNodeToCSEMaps(SDNode *N); |
2035 | SDNode *FindModifiedNodeSlot(SDNode *N, SDValue Op, void *&InsertPos); |
2036 | SDNode *FindModifiedNodeSlot(SDNode *N, SDValue Op1, SDValue Op2, |
2037 | void *&InsertPos); |
2038 | SDNode *FindModifiedNodeSlot(SDNode *N, ArrayRef<SDValue> Ops, |
2039 | void *&InsertPos); |
2040 | SDNode *UpdateSDLocOnMergeSDNode(SDNode *N, const SDLoc &loc); |
2041 | |
2042 | void DeleteNodeNotInCSEMaps(SDNode *N); |
2043 | void DeallocateNode(SDNode *N); |
2044 | |
2045 | void allnodes_clear(); |
2046 | |
2047 | /// Look up the node specified by ID in CSEMap. If it exists, return it. If |
2048 | /// not, return the insertion token that will make insertion faster. This |
2049 | /// overload is for nodes other than Constant or ConstantFP, use the other one |
2050 | /// for those. |
2051 | SDNode *FindNodeOrInsertPos(const FoldingSetNodeID &ID, void *&InsertPos); |
2052 | |
2053 | /// Look up the node specified by ID in CSEMap. If it exists, return it. If |
2054 | /// not, return the insertion token that will make insertion faster. Performs |
2055 | /// additional processing for constant nodes. |
2056 | SDNode *FindNodeOrInsertPos(const FoldingSetNodeID &ID, const SDLoc &DL, |
2057 | void *&InsertPos); |
2058 | |
2059 | /// List of non-single value types. |
2060 | FoldingSet<SDVTListNode> VTListMap; |
2061 | |
2062 | /// Maps to auto-CSE operations. |
2063 | std::vector<CondCodeSDNode*> CondCodeNodes; |
2064 | |
2065 | std::vector<SDNode*> ValueTypeNodes; |
2066 | std::map<EVT, SDNode*, EVT::compareRawBits> ExtendedValueTypeNodes; |
2067 | StringMap<SDNode*> ExternalSymbols; |
2068 | |
2069 | std::map<std::pair<std::string, unsigned>, SDNode *> TargetExternalSymbols; |
2070 | DenseMap<MCSymbol *, SDNode *> MCSymbols; |
2071 | |
2072 | FlagInserter *Inserter = nullptr; |
2073 | }; |
2074 | |
2075 | template <> struct GraphTraits<SelectionDAG*> : public GraphTraits<SDNode*> { |
2076 | using nodes_iterator = pointer_iterator<SelectionDAG::allnodes_iterator>; |
2077 | |
2078 | static nodes_iterator nodes_begin(SelectionDAG *G) { |
2079 | return nodes_iterator(G->allnodes_begin()); |
2080 | } |
2081 | |
2082 | static nodes_iterator nodes_end(SelectionDAG *G) { |
2083 | return nodes_iterator(G->allnodes_end()); |
2084 | } |
2085 | }; |
2086 | |
2087 | } // end namespace llvm |
2088 | |
2089 | #endif // LLVM_CODEGEN_SELECTIONDAG_H |
1 | //===- llvm/CodeGen/SelectionDAGNodes.h - SelectionDAG Nodes ----*- C++ -*-===// | |||
2 | // | |||
3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. | |||
4 | // See https://llvm.org/LICENSE.txt for license information. | |||
5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception | |||
6 | // | |||
7 | //===----------------------------------------------------------------------===// | |||
8 | // | |||
9 | // This file declares the SDNode class and derived classes, which are used to | |||
10 | // represent the nodes and operations present in a SelectionDAG. These nodes | |||
11 | // and operations are machine code level operations, with some similarities to | |||
12 | // the GCC RTL representation. | |||
13 | // | |||
14 | // Clients should include the SelectionDAG.h file instead of this file directly. | |||
15 | // | |||
16 | //===----------------------------------------------------------------------===// | |||
17 | ||||
18 | #ifndef LLVM_CODEGEN_SELECTIONDAGNODES_H | |||
19 | #define LLVM_CODEGEN_SELECTIONDAGNODES_H | |||
20 | ||||
21 | #include "llvm/ADT/APFloat.h" | |||
22 | #include "llvm/ADT/ArrayRef.h" | |||
23 | #include "llvm/ADT/BitVector.h" | |||
24 | #include "llvm/ADT/FoldingSet.h" | |||
25 | #include "llvm/ADT/GraphTraits.h" | |||
26 | #include "llvm/ADT/SmallPtrSet.h" | |||
27 | #include "llvm/ADT/SmallVector.h" | |||
28 | #include "llvm/ADT/ilist_node.h" | |||
29 | #include "llvm/ADT/iterator.h" | |||
30 | #include "llvm/ADT/iterator_range.h" | |||
31 | #include "llvm/CodeGen/ISDOpcodes.h" | |||
32 | #include "llvm/CodeGen/MachineMemOperand.h" | |||
33 | #include "llvm/CodeGen/Register.h" | |||
34 | #include "llvm/CodeGen/ValueTypes.h" | |||
35 | #include "llvm/IR/Constants.h" | |||
36 | #include "llvm/IR/DebugLoc.h" | |||
37 | #include "llvm/IR/Instruction.h" | |||
38 | #include "llvm/IR/Instructions.h" | |||
39 | #include "llvm/IR/Metadata.h" | |||
40 | #include "llvm/IR/Operator.h" | |||
41 | #include "llvm/Support/AlignOf.h" | |||
42 | #include "llvm/Support/AtomicOrdering.h" | |||
43 | #include "llvm/Support/Casting.h" | |||
44 | #include "llvm/Support/ErrorHandling.h" | |||
45 | #include "llvm/Support/MachineValueType.h" | |||
46 | #include "llvm/Support/TypeSize.h" | |||
47 | #include <algorithm> | |||
48 | #include <cassert> | |||
49 | #include <climits> | |||
50 | #include <cstddef> | |||
51 | #include <cstdint> | |||
52 | #include <cstring> | |||
53 | #include <iterator> | |||
54 | #include <string> | |||
55 | #include <tuple> | |||
56 | ||||
57 | namespace llvm { | |||
58 | ||||
59 | class APInt; | |||
60 | class Constant; | |||
61 | template <typename T> struct DenseMapInfo; | |||
62 | class GlobalValue; | |||
63 | class MachineBasicBlock; | |||
64 | class MachineConstantPoolValue; | |||
65 | class MCSymbol; | |||
66 | class raw_ostream; | |||
67 | class SDNode; | |||
68 | class SelectionDAG; | |||
69 | class Type; | |||
70 | class Value; | |||
71 | ||||
72 | void checkForCycles(const SDNode *N, const SelectionDAG *DAG = nullptr, | |||
73 | bool force = false); | |||
74 | ||||
75 | /// This represents a list of ValueType's that has been intern'd by | |||
76 | /// a SelectionDAG. Instances of this simple value class are returned by | |||
77 | /// SelectionDAG::getVTList(...). | |||
78 | /// | |||
79 | struct SDVTList { | |||
80 | const EVT *VTs; | |||
81 | unsigned int NumVTs; | |||
82 | }; | |||
83 | ||||
84 | namespace ISD { | |||
85 | ||||
86 | /// Node predicates | |||
87 | ||||
88 | /// If N is a BUILD_VECTOR or SPLAT_VECTOR node whose elements are all the | |||
89 | /// same constant or undefined, return true and return the constant value in | |||
90 | /// \p SplatValue. | |||
91 | bool isConstantSplatVector(const SDNode *N, APInt &SplatValue); | |||
92 | ||||
93 | /// Return true if the specified node is a BUILD_VECTOR or SPLAT_VECTOR where | |||
94 | /// all of the elements are ~0 or undef. If \p BuildVectorOnly is set to | |||
95 | /// true, it only checks BUILD_VECTOR. | |||
96 | bool isConstantSplatVectorAllOnes(const SDNode *N, | |||
97 | bool BuildVectorOnly = false); | |||
98 | ||||
99 | /// Return true if the specified node is a BUILD_VECTOR or SPLAT_VECTOR where | |||
100 | /// all of the elements are 0 or undef. If \p BuildVectorOnly is set to true, it | |||
101 | /// only checks BUILD_VECTOR. | |||
102 | bool isConstantSplatVectorAllZeros(const SDNode *N, | |||
103 | bool BuildVectorOnly = false); | |||
104 | ||||
105 | /// Return true if the specified node is a BUILD_VECTOR where all of the | |||
106 | /// elements are ~0 or undef. | |||
107 | bool isBuildVectorAllOnes(const SDNode *N); | |||
108 | ||||
109 | /// Return true if the specified node is a BUILD_VECTOR where all of the | |||
110 | /// elements are 0 or undef. | |||
111 | bool isBuildVectorAllZeros(const SDNode *N); | |||
112 | ||||
113 | /// Return true if the specified node is a BUILD_VECTOR node of all | |||
114 | /// ConstantSDNode or undef. | |||
115 | bool isBuildVectorOfConstantSDNodes(const SDNode *N); | |||
116 | ||||
117 | /// Return true if the specified node is a BUILD_VECTOR node of all | |||
118 | /// ConstantFPSDNode or undef. | |||
119 | bool isBuildVectorOfConstantFPSDNodes(const SDNode *N); | |||
120 | ||||
121 | /// Return true if the node has at least one operand and all operands of the | |||
122 | /// specified node are ISD::UNDEF. | |||
123 | bool allOperandsUndef(const SDNode *N); | |||
124 | ||||
125 | } // end namespace ISD | |||
126 | ||||
127 | //===----------------------------------------------------------------------===// | |||
128 | /// Unlike LLVM values, Selection DAG nodes may return multiple | |||
129 | /// values as the result of a computation. Many nodes return multiple values, | |||
130 | /// from loads (which define a token and a return value) to ADDC (which returns | |||
131 | /// a result and a carry value), to calls (which may return an arbitrary number | |||
132 | /// of values). | |||
133 | /// | |||
134 | /// As such, each use of a SelectionDAG computation must indicate the node that | |||
135 | /// computes it as well as which return value to use from that node. This pair | |||
136 | /// of information is represented with the SDValue value type. | |||
137 | /// | |||
138 | class SDValue { | |||
139 | friend struct DenseMapInfo<SDValue>; | |||
140 | ||||
141 | SDNode *Node = nullptr; // The node defining the value we are using. | |||
142 | unsigned ResNo = 0; // Which return value of the node we are using. | |||
143 | ||||
144 | public: | |||
145 | SDValue() = default; | |||
146 | SDValue(SDNode *node, unsigned resno); | |||
147 | ||||
148 | /// get the index which selects a specific result in the SDNode | |||
149 | unsigned getResNo() const { return ResNo; } | |||
150 | ||||
151 | /// get the SDNode which holds the desired result | |||
152 | SDNode *getNode() const { return Node; } | |||
153 | ||||
154 | /// set the SDNode | |||
155 | void setNode(SDNode *N) { Node = N; } | |||
156 | ||||
157 | inline SDNode *operator->() const { return Node; } | |||
158 | ||||
159 | bool operator==(const SDValue &O) const { | |||
160 | return Node == O.Node && ResNo == O.ResNo; | |||
161 | } | |||
162 | bool operator!=(const SDValue &O) const { | |||
163 | return !operator==(O); | |||
164 | } | |||
165 | bool operator<(const SDValue &O) const { | |||
166 | return std::tie(Node, ResNo) < std::tie(O.Node, O.ResNo); | |||
167 | } | |||
168 | explicit operator bool() const { | |||
169 | return Node != nullptr; | |||
170 | } | |||
171 | ||||
172 | SDValue getValue(unsigned R) const { | |||
173 | return SDValue(Node, R); | |||
174 | } | |||
175 | ||||
176 | /// Return true if this node is an operand of N. | |||
177 | bool isOperandOf(const SDNode *N) const; | |||
178 | ||||
179 | /// Return the ValueType of the referenced return value. | |||
180 | inline EVT getValueType() const; | |||
181 | ||||
182 | /// Return the simple ValueType of the referenced return value. | |||
183 | MVT getSimpleValueType() const { | |||
184 | return getValueType().getSimpleVT(); | |||
185 | } | |||
186 | ||||
187 | /// Returns the size of the value in bits. | |||
188 | /// | |||
189 | /// If the value type is a scalable vector type, the scalable property will | |||
190 | /// be set and the runtime size will be a positive integer multiple of the | |||
191 | /// base size. | |||
192 | TypeSize getValueSizeInBits() const { | |||
193 | return getValueType().getSizeInBits(); | |||
194 | } | |||
195 | ||||
196 | uint64_t getScalarValueSizeInBits() const { | |||
197 | return getValueType().getScalarType().getFixedSizeInBits(); | |||
198 | } | |||
199 | ||||
200 | // Forwarding methods - These forward to the corresponding methods in SDNode. | |||
201 | inline unsigned getOpcode() const; | |||
202 | inline unsigned getNumOperands() const; | |||
203 | inline const SDValue &getOperand(unsigned i) const; | |||
204 | inline uint64_t getConstantOperandVal(unsigned i) const; | |||
205 | inline const APInt &getConstantOperandAPInt(unsigned i) const; | |||
206 | inline bool isTargetMemoryOpcode() const; | |||
207 | inline bool isTargetOpcode() const; | |||
208 | inline bool isMachineOpcode() const; | |||
209 | inline bool isUndef() const; | |||
210 | inline unsigned getMachineOpcode() const; | |||
211 | inline const DebugLoc &getDebugLoc() const; | |||
212 | inline void dump() const; | |||
213 | inline void dump(const SelectionDAG *G) const; | |||
214 | inline void dumpr() const; | |||
215 | inline void dumpr(const SelectionDAG *G) const; | |||
216 | ||||
217 | /// Return true if this operand (which must be a chain) reaches the | |||
218 | /// specified operand without crossing any side-effecting instructions. | |||
219 | /// In practice, this looks through token factors and non-volatile loads. | |||
220 | /// In order to remain efficient, this only | |||
221 | /// looks a couple of nodes in, it does not do an exhaustive search. | |||
222 | bool reachesChainWithoutSideEffects(SDValue Dest, | |||
223 | unsigned Depth = 2) const; | |||
224 | ||||
225 | /// Return true if there are no nodes using value ResNo of Node. | |||
226 | inline bool use_empty() const; | |||
227 | ||||
228 | /// Return true if there is exactly one node using value ResNo of Node. | |||
229 | inline bool hasOneUse() const; | |||
230 | }; | |||
231 | ||||
232 | template<> struct DenseMapInfo<SDValue> { | |||
233 | static inline SDValue getEmptyKey() { | |||
234 | SDValue V; | |||
235 | V.ResNo = -1U; | |||
236 | return V; | |||
237 | } | |||
238 | ||||
239 | static inline SDValue getTombstoneKey() { | |||
240 | SDValue V; | |||
241 | V.ResNo = -2U; | |||
242 | return V; | |||
243 | } | |||
244 | ||||
245 | static unsigned getHashValue(const SDValue &Val) { | |||
246 | return ((unsigned)((uintptr_t)Val.getNode() >> 4) ^ | |||
247 | (unsigned)((uintptr_t)Val.getNode() >> 9)) + Val.getResNo(); | |||
248 | } | |||
249 | ||||
250 | static bool isEqual(const SDValue &LHS, const SDValue &RHS) { | |||
251 | return LHS == RHS; | |||
252 | } | |||
253 | }; | |||
254 | ||||
255 | /// Allow casting operators to work directly on | |||
256 | /// SDValues as if they were SDNode*'s. | |||
257 | template<> struct simplify_type<SDValue> { | |||
258 | using SimpleType = SDNode *; | |||
259 | ||||
260 | static SimpleType getSimplifiedValue(SDValue &Val) { | |||
261 | return Val.getNode(); | |||
262 | } | |||
263 | }; | |||
264 | template<> struct simplify_type<const SDValue> { | |||
265 | using SimpleType = /*const*/ SDNode *; | |||
266 | ||||
267 | static SimpleType getSimplifiedValue(const SDValue &Val) { | |||
268 | return Val.getNode(); | |||
269 | } | |||
270 | }; | |||
271 | ||||
272 | /// Represents a use of a SDNode. This class holds an SDValue, | |||
273 | /// which records the SDNode being used and the result number, a | |||
274 | /// pointer to the SDNode using the value, and Next and Prev pointers, | |||
275 | /// which link together all the uses of an SDNode. | |||
276 | /// | |||
277 | class SDUse { | |||
278 | /// Val - The value being used. | |||
279 | SDValue Val; | |||
280 | /// User - The user of this value. | |||
281 | SDNode *User = nullptr; | |||
282 | /// Prev, Next - Pointers to the uses list of the SDNode referred by | |||
283 | /// this operand. | |||
284 | SDUse **Prev = nullptr; | |||
285 | SDUse *Next = nullptr; | |||
286 | ||||
287 | public: | |||
288 | SDUse() = default; | |||
289 | SDUse(const SDUse &U) = delete; | |||
290 | SDUse &operator=(const SDUse &) = delete; | |||
291 | ||||
292 | /// Normally SDUse will just implicitly convert to an SDValue that it holds. | |||
293 | operator const SDValue&() const { return Val; } | |||
294 | ||||
295 | /// If implicit conversion to SDValue doesn't work, the get() method returns | |||
296 | /// the SDValue. | |||
297 | const SDValue &get() const { return Val; } | |||
298 | ||||
299 | /// This returns the SDNode that contains this Use. | |||
300 | SDNode *getUser() { return User; } | |||
301 | ||||
302 | /// Get the next SDUse in the use list. | |||
303 | SDUse *getNext() const { return Next; } | |||
304 | ||||
305 | /// Convenience function for get().getNode(). | |||
306 | SDNode *getNode() const { return Val.getNode(); } | |||
307 | /// Convenience function for get().getResNo(). | |||
308 | unsigned getResNo() const { return Val.getResNo(); } | |||
309 | /// Convenience function for get().getValueType(). | |||
310 | EVT getValueType() const { return Val.getValueType(); } | |||
311 | ||||
312 | /// Convenience function for get().operator== | |||
313 | bool operator==(const SDValue &V) const { | |||
314 | return Val == V; | |||
315 | } | |||
316 | ||||
317 | /// Convenience function for get().operator!= | |||
318 | bool operator!=(const SDValue &V) const { | |||
319 | return Val != V; | |||
320 | } | |||
321 | ||||
322 | /// Convenience function for get().operator< | |||
323 | bool operator<(const SDValue &V) const { | |||
324 | return Val < V; | |||
325 | } | |||
326 | ||||
327 | private: | |||
328 | friend class SelectionDAG; | |||
329 | friend class SDNode; | |||
330 | // TODO: unfriend HandleSDNode once we fix its operand handling. | |||
331 | friend class HandleSDNode; | |||
332 | ||||
333 | void setUser(SDNode *p) { User = p; } | |||
334 | ||||
335 | /// Remove this use from its existing use list, assign it the | |||
336 | /// given value, and add it to the new value's node's use list. | |||
337 | inline void set(const SDValue &V); | |||
338 | /// Like set, but only supports initializing a newly-allocated | |||
339 | /// SDUse with a non-null value. | |||
340 | inline void setInitial(const SDValue &V); | |||
341 | /// Like set, but only sets the Node portion of the value, | |||
342 | /// leaving the ResNo portion unmodified. | |||
343 | inline void setNode(SDNode *N); | |||
344 | ||||
345 | void addToList(SDUse **List) { | |||
346 | Next = *List; | |||
347 | if (Next) Next->Prev = &Next; | |||
348 | Prev = List; | |||
349 | *List = this; | |||
350 | } | |||
351 | ||||
352 | void removeFromList() { | |||
353 | *Prev = Next; | |||
354 | if (Next) Next->Prev = Prev; | |||
355 | } | |||
356 | }; | |||
357 | ||||
358 | /// simplify_type specializations - Allow casting operators to work directly on | |||
359 | /// SDValues as if they were SDNode*'s. | |||
360 | template<> struct simplify_type<SDUse> { | |||
361 | using SimpleType = SDNode *; | |||
362 | ||||
363 | static SimpleType getSimplifiedValue(SDUse &Val) { | |||
364 | return Val.getNode(); | |||
365 | } | |||
366 | }; | |||
367 | ||||
368 | /// These are IR-level optimization flags that may be propagated to SDNodes. | |||
369 | /// TODO: This data structure should be shared by the IR optimizer and the | |||
370 | /// the backend. | |||
371 | struct SDNodeFlags { | |||
372 | private: | |||
373 | bool NoUnsignedWrap : 1; | |||
374 | bool NoSignedWrap : 1; | |||
375 | bool Exact : 1; | |||
376 | bool NoNaNs : 1; | |||
377 | bool NoInfs : 1; | |||
378 | bool NoSignedZeros : 1; | |||
379 | bool AllowReciprocal : 1; | |||
380 | bool AllowContract : 1; | |||
381 | bool ApproximateFuncs : 1; | |||
382 | bool AllowReassociation : 1; | |||
383 | ||||
384 | // We assume instructions do not raise floating-point exceptions by default, | |||
385 | // and only those marked explicitly may do so. We could choose to represent | |||
386 | // this via a positive "FPExcept" flags like on the MI level, but having a | |||
387 | // negative "NoFPExcept" flag here (that defaults to true) makes the flag | |||
388 | // intersection logic more straightforward. | |||
389 | bool NoFPExcept : 1; | |||
390 | ||||
391 | public: | |||
392 | /// Default constructor turns off all optimization flags. | |||
393 | SDNodeFlags() | |||
394 | : NoUnsignedWrap(false), NoSignedWrap(false), Exact(false), NoNaNs(false), | |||
395 | NoInfs(false), NoSignedZeros(false), AllowReciprocal(false), | |||
396 | AllowContract(false), ApproximateFuncs(false), | |||
397 | AllowReassociation(false), NoFPExcept(false) {} | |||
398 | ||||
399 | /// Propagate the fast-math-flags from an IR FPMathOperator. | |||
400 | void copyFMF(const FPMathOperator &FPMO) { | |||
401 | setNoNaNs(FPMO.hasNoNaNs()); | |||
402 | setNoInfs(FPMO.hasNoInfs()); | |||
403 | setNoSignedZeros(FPMO.hasNoSignedZeros()); | |||
404 | setAllowReciprocal(FPMO.hasAllowReciprocal()); | |||
405 | setAllowContract(FPMO.hasAllowContract()); | |||
406 | setApproximateFuncs(FPMO.hasApproxFunc()); | |||
407 | setAllowReassociation(FPMO.hasAllowReassoc()); | |||
408 | } | |||
409 | ||||
410 | // These are mutators for each flag. | |||
411 | void setNoUnsignedWrap(bool b) { NoUnsignedWrap = b; } | |||
412 | void setNoSignedWrap(bool b) { NoSignedWrap = b; } | |||
413 | void setExact(bool b) { Exact = b; } | |||
414 | void setNoNaNs(bool b) { NoNaNs = b; } | |||
415 | void setNoInfs(bool b) { NoInfs = b; } | |||
416 | void setNoSignedZeros(bool b) { NoSignedZeros = b; } | |||
417 | void setAllowReciprocal(bool b) { AllowReciprocal = b; } | |||
418 | void setAllowContract(bool b) { AllowContract = b; } | |||
419 | void setApproximateFuncs(bool b) { ApproximateFuncs = b; } | |||
420 | void setAllowReassociation(bool b) { AllowReassociation = b; } | |||
421 | void setNoFPExcept(bool b) { NoFPExcept = b; } | |||
422 | ||||
423 | // These are accessors for each flag. | |||
424 | bool hasNoUnsignedWrap() const { return NoUnsignedWrap; } | |||
425 | bool hasNoSignedWrap() const { return NoSignedWrap; } | |||
426 | bool hasExact() const { return Exact; } | |||
427 | bool hasNoNaNs() const { return NoNaNs; } | |||
428 | bool hasNoInfs() const { return NoInfs; } | |||
429 | bool hasNoSignedZeros() const { return NoSignedZeros; } | |||
430 | bool hasAllowReciprocal() const { return AllowReciprocal; } | |||
431 | bool hasAllowContract() const { return AllowContract; } | |||
432 | bool hasApproximateFuncs() const { return ApproximateFuncs; } | |||
433 | bool hasAllowReassociation() const { return AllowReassociation; } | |||
434 | bool hasNoFPExcept() const { return NoFPExcept; } | |||
435 | ||||
436 | /// Clear any flags in this flag set that aren't also set in Flags. All | |||
437 | /// flags will be cleared if Flags are undefined. | |||
438 | void intersectWith(const SDNodeFlags Flags) { | |||
439 | NoUnsignedWrap &= Flags.NoUnsignedWrap; | |||
440 | NoSignedWrap &= Flags.NoSignedWrap; | |||
441 | Exact &= Flags.Exact; | |||
442 | NoNaNs &= Flags.NoNaNs; | |||
443 | NoInfs &= Flags.NoInfs; | |||
444 | NoSignedZeros &= Flags.NoSignedZeros; | |||
445 | AllowReciprocal &= Flags.AllowReciprocal; | |||
446 | AllowContract &= Flags.AllowContract; | |||
447 | ApproximateFuncs &= Flags.ApproximateFuncs; | |||
448 | AllowReassociation &= Flags.AllowReassociation; | |||
449 | NoFPExcept &= Flags.NoFPExcept; | |||
450 | } | |||
451 | }; | |||
452 | ||||
453 | /// Represents one node in the SelectionDAG. | |||
454 | /// | |||
455 | class SDNode : public FoldingSetNode, public ilist_node<SDNode> { | |||
456 | private: | |||
457 | /// The operation that this node performs. | |||
458 | int16_t NodeType; | |||
459 | ||||
460 | protected: | |||
461 | // We define a set of mini-helper classes to help us interpret the bits in our | |||
462 | // SubclassData. These are designed to fit within a uint16_t so they pack | |||
463 | // with NodeType. | |||
464 | ||||
465 | #if defined(_AIX) && (!defined(__GNUC__4) || defined(__ibmxl__)) | |||
466 | // Except for GCC; by default, AIX compilers store bit-fields in 4-byte words | |||
467 | // and give the `pack` pragma push semantics. | |||
468 | #define BEGIN_TWO_BYTE_PACK() _Pragma("pack(2)")pack(2) | |||
469 | #define END_TWO_BYTE_PACK() _Pragma("pack(pop)")pack(pop) | |||
470 | #else | |||
471 | #define BEGIN_TWO_BYTE_PACK() | |||
472 | #define END_TWO_BYTE_PACK() | |||
473 | #endif | |||
474 | ||||
475 | BEGIN_TWO_BYTE_PACK() | |||
476 | class SDNodeBitfields { | |||
477 | friend class SDNode; | |||
478 | friend class MemIntrinsicSDNode; | |||
479 | friend class MemSDNode; | |||
480 | friend class SelectionDAG; | |||
481 | ||||
482 | uint16_t HasDebugValue : 1; | |||
483 | uint16_t IsMemIntrinsic : 1; | |||
484 | uint16_t IsDivergent : 1; | |||
485 | }; | |||
486 | enum { NumSDNodeBits = 3 }; | |||
487 | ||||
488 | class ConstantSDNodeBitfields { | |||
489 | friend class ConstantSDNode; | |||
490 | ||||
491 | uint16_t : NumSDNodeBits; | |||
492 | ||||
493 | uint16_t IsOpaque : 1; | |||
494 | }; | |||
495 | ||||
496 | class MemSDNodeBitfields { | |||
497 | friend class MemSDNode; | |||
498 | friend class MemIntrinsicSDNode; | |||
499 | friend class AtomicSDNode; | |||
500 | ||||
501 | uint16_t : NumSDNodeBits; | |||
502 | ||||
503 | uint16_t IsVolatile : 1; | |||
504 | uint16_t IsNonTemporal : 1; | |||
505 | uint16_t IsDereferenceable : 1; | |||
506 | uint16_t IsInvariant : 1; | |||
507 | }; | |||
508 | enum { NumMemSDNodeBits = NumSDNodeBits + 4 }; | |||
509 | ||||
510 | class LSBaseSDNodeBitfields { | |||
511 | friend class LSBaseSDNode; | |||
512 | friend class MaskedLoadStoreSDNode; | |||
513 | friend class MaskedGatherScatterSDNode; | |||
514 | ||||
515 | uint16_t : NumMemSDNodeBits; | |||
516 | ||||
517 | // This storage is shared between disparate class hierarchies to hold an | |||
518 | // enumeration specific to the class hierarchy in use. | |||
519 | // LSBaseSDNode => enum ISD::MemIndexedMode | |||
520 | // MaskedLoadStoreBaseSDNode => enum ISD::MemIndexedMode | |||
521 | // MaskedGatherScatterSDNode => enum ISD::MemIndexType | |||
522 | uint16_t AddressingMode : 3; | |||
523 | }; | |||
524 | enum { NumLSBaseSDNodeBits = NumMemSDNodeBits + 3 }; | |||
525 | ||||
526 | class LoadSDNodeBitfields { | |||
527 | friend class LoadSDNode; | |||
528 | friend class MaskedLoadSDNode; | |||
529 | friend class MaskedGatherSDNode; | |||
530 | ||||
531 | uint16_t : NumLSBaseSDNodeBits; | |||
532 | ||||
533 | uint16_t ExtTy : 2; // enum ISD::LoadExtType | |||
534 | uint16_t IsExpanding : 1; | |||
535 | }; | |||
536 | ||||
537 | class StoreSDNodeBitfields { | |||
538 | friend class StoreSDNode; | |||
539 | friend class MaskedStoreSDNode; | |||
540 | friend class MaskedScatterSDNode; | |||
541 | ||||
542 | uint16_t : NumLSBaseSDNodeBits; | |||
543 | ||||
544 | uint16_t IsTruncating : 1; | |||
545 | uint16_t IsCompressing : 1; | |||
546 | }; | |||
547 | ||||
548 | union { | |||
549 | char RawSDNodeBits[sizeof(uint16_t)]; | |||
550 | SDNodeBitfields SDNodeBits; | |||
551 | ConstantSDNodeBitfields ConstantSDNodeBits; | |||
552 | MemSDNodeBitfields MemSDNodeBits; | |||
553 | LSBaseSDNodeBitfields LSBaseSDNodeBits; | |||
554 | LoadSDNodeBitfields LoadSDNodeBits; | |||
555 | StoreSDNodeBitfields StoreSDNodeBits; | |||
556 | }; | |||
557 | END_TWO_BYTE_PACK() | |||
558 | #undef BEGIN_TWO_BYTE_PACK | |||
559 | #undef END_TWO_BYTE_PACK | |||
560 | ||||
561 | // RawSDNodeBits must cover the entirety of the union. This means that all of | |||
562 | // the union's members must have size <= RawSDNodeBits. We write the RHS as | |||
563 | // "2" instead of sizeof(RawSDNodeBits) because MSVC can't handle the latter. | |||
564 | static_assert(sizeof(SDNodeBitfields) <= 2, "field too wide"); | |||
565 | static_assert(sizeof(ConstantSDNodeBitfields) <= 2, "field too wide"); | |||
566 | static_assert(sizeof(MemSDNodeBitfields) <= 2, "field too wide"); | |||
567 | static_assert(sizeof(LSBaseSDNodeBitfields) <= 2, "field too wide"); | |||
568 | static_assert(sizeof(LoadSDNodeBitfields) <= 2, "field too wide"); | |||
569 | static_assert(sizeof(StoreSDNodeBitfields) <= 2, "field too wide"); | |||
570 | ||||
571 | private: | |||
572 | friend class SelectionDAG; | |||
573 | // TODO: unfriend HandleSDNode once we fix its operand handling. | |||
574 | friend class HandleSDNode; | |||
575 | ||||
576 | /// Unique id per SDNode in the DAG. | |||
577 | int NodeId = -1; | |||
578 | ||||
579 | /// The values that are used by this operation. | |||
580 | SDUse *OperandList = nullptr; | |||
581 | ||||
582 | /// The types of the values this node defines. SDNode's may | |||
583 | /// define multiple values simultaneously. | |||
584 | const EVT *ValueList; | |||
585 | ||||
586 | /// List of uses for this SDNode. | |||
587 | SDUse *UseList = nullptr; | |||
588 | ||||
589 | /// The number of entries in the Operand/Value list. | |||
590 | unsigned short NumOperands = 0; | |||
591 | unsigned short NumValues; | |||
592 | ||||
593 | // The ordering of the SDNodes. It roughly corresponds to the ordering of the | |||
594 | // original LLVM instructions. | |||
595 | // This is used for turning off scheduling, because we'll forgo | |||
596 | // the normal scheduling algorithms and output the instructions according to | |||
597 | // this ordering. | |||
598 | unsigned IROrder; | |||
599 | ||||
600 | /// Source line information. | |||
601 | DebugLoc debugLoc; | |||
602 | ||||
603 | /// Return a pointer to the specified value type. | |||
604 | static const EVT *getValueTypeList(EVT VT); | |||
605 | ||||
606 | SDNodeFlags Flags; | |||
607 | ||||
608 | public: | |||
609 | /// Unique and persistent id per SDNode in the DAG. | |||
610 | /// Used for debug printing. | |||
611 | uint16_t PersistentId; | |||
612 | ||||
613 | //===--------------------------------------------------------------------===// | |||
614 | // Accessors | |||
615 | // | |||
616 | ||||
617 | /// Return the SelectionDAG opcode value for this node. For | |||
618 | /// pre-isel nodes (those for which isMachineOpcode returns false), these | |||
619 | /// are the opcode values in the ISD and <target>ISD namespaces. For | |||
620 | /// post-isel opcodes, see getMachineOpcode. | |||
621 | unsigned getOpcode() const { return (unsigned short)NodeType; } | |||
622 | ||||
623 | /// Test if this node has a target-specific opcode (in the | |||
624 | /// \<target\>ISD namespace). | |||
625 | bool isTargetOpcode() const { return NodeType >= ISD::BUILTIN_OP_END; } | |||
626 | ||||
627 | /// Test if this node has a target-specific opcode that may raise | |||
628 | /// FP exceptions (in the \<target\>ISD namespace and greater than | |||
629 | /// FIRST_TARGET_STRICTFP_OPCODE). Note that all target memory | |||
630 | /// opcode are currently automatically considered to possibly raise | |||
631 | /// FP exceptions as well. | |||
632 | bool isTargetStrictFPOpcode() const { | |||
633 | return NodeType >= ISD::FIRST_TARGET_STRICTFP_OPCODE; | |||
634 | } | |||
635 | ||||
636 | /// Test if this node has a target-specific | |||
637 | /// memory-referencing opcode (in the \<target\>ISD namespace and | |||
638 | /// greater than FIRST_TARGET_MEMORY_OPCODE). | |||
639 | bool isTargetMemoryOpcode() const { | |||
640 | return NodeType >= ISD::FIRST_TARGET_MEMORY_OPCODE; | |||
641 | } | |||
642 | ||||
643 | /// Return true if the type of the node type undefined. | |||
644 | bool isUndef() const { return NodeType == ISD::UNDEF; } | |||
645 | ||||
646 | /// Test if this node is a memory intrinsic (with valid pointer information). | |||
647 | /// INTRINSIC_W_CHAIN and INTRINSIC_VOID nodes are sometimes created for | |||
648 | /// non-memory intrinsics (with chains) that are not really instances of | |||
649 | /// MemSDNode. For such nodes, we need some extra state to determine the | |||
650 | /// proper classof relationship. | |||
651 | bool isMemIntrinsic() const { | |||
652 | return (NodeType == ISD::INTRINSIC_W_CHAIN || | |||
653 | NodeType == ISD::INTRINSIC_VOID) && | |||
654 | SDNodeBits.IsMemIntrinsic; | |||
655 | } | |||
656 | ||||
657 | /// Test if this node is a strict floating point pseudo-op. | |||
658 | bool isStrictFPOpcode() { | |||
659 | switch (NodeType) { | |||
660 | default: | |||
661 | return false; | |||
662 | case ISD::STRICT_FP16_TO_FP: | |||
663 | case ISD::STRICT_FP_TO_FP16: | |||
664 | #define DAG_INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN) \ | |||
665 | case ISD::STRICT_##DAGN: | |||
666 | #include "llvm/IR/ConstrainedOps.def" | |||
667 | return true; | |||
668 | } | |||
669 | } | |||
670 | ||||
671 | /// Test if this node has a post-isel opcode, directly | |||
672 | /// corresponding to a MachineInstr opcode. | |||
673 | bool isMachineOpcode() const { return NodeType < 0; } | |||
674 | ||||
675 | /// This may only be called if isMachineOpcode returns | |||
676 | /// true. It returns the MachineInstr opcode value that the node's opcode | |||
677 | /// corresponds to. | |||
678 | unsigned getMachineOpcode() const { | |||
679 | assert(isMachineOpcode() && "Not a MachineInstr opcode!")((isMachineOpcode() && "Not a MachineInstr opcode!") ? static_cast<void> (0) : __assert_fail ("isMachineOpcode() && \"Not a MachineInstr opcode!\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/CodeGen/SelectionDAGNodes.h" , 679, __PRETTY_FUNCTION__)); | |||
680 | return ~NodeType; | |||
681 | } | |||
682 | ||||
683 | bool getHasDebugValue() const { return SDNodeBits.HasDebugValue; } | |||
684 | void setHasDebugValue(bool b) { SDNodeBits.HasDebugValue = b; } | |||
685 | ||||
686 | bool isDivergent() const { return SDNodeBits.IsDivergent; } | |||
687 | ||||
688 | /// Return true if there are no uses of this node. | |||
689 | bool use_empty() const { return UseList == nullptr; } | |||
690 | ||||
691 | /// Return true if there is exactly one use of this node. | |||
692 | bool hasOneUse() const { return hasSingleElement(uses()); } | |||
693 | ||||
694 | /// Return the number of uses of this node. This method takes | |||
695 | /// time proportional to the number of uses. | |||
696 | size_t use_size() const { return std::distance(use_begin(), use_end()); } | |||
697 | ||||
698 | /// Return the unique node id. | |||
699 | int getNodeId() const { return NodeId; } | |||
700 | ||||
701 | /// Set unique node id. | |||
702 | void setNodeId(int Id) { NodeId = Id; } | |||
703 | ||||
704 | /// Return the node ordering. | |||
705 | unsigned getIROrder() const { return IROrder; } | |||
706 | ||||
707 | /// Set the node ordering. | |||
708 | void setIROrder(unsigned Order) { IROrder = Order; } | |||
709 | ||||
710 | /// Return the source location info. | |||
711 | const DebugLoc &getDebugLoc() const { return debugLoc; } | |||
712 | ||||
713 | /// Set source location info. Try to avoid this, putting | |||
714 | /// it in the constructor is preferable. | |||
715 | void setDebugLoc(DebugLoc dl) { debugLoc = std::move(dl); } | |||
716 | ||||
717 | /// This class provides iterator support for SDUse | |||
718 | /// operands that use a specific SDNode. | |||
719 | class use_iterator { | |||
720 | friend class SDNode; | |||
721 | ||||
722 | SDUse *Op = nullptr; | |||
723 | ||||
724 | explicit use_iterator(SDUse *op) : Op(op) {} | |||
725 | ||||
726 | public: | |||
727 | using iterator_category = std::forward_iterator_tag; | |||
728 | using value_type = SDUse; | |||
729 | using difference_type = std::ptrdiff_t; | |||
730 | using pointer = value_type *; | |||
731 | using reference = value_type &; | |||
732 | ||||
733 | use_iterator() = default; | |||
734 | use_iterator(const use_iterator &I) : Op(I.Op) {} | |||
735 | ||||
736 | bool operator==(const use_iterator &x) const { | |||
737 | return Op == x.Op; | |||
738 | } | |||
739 | bool operator!=(const use_iterator &x) const { | |||
740 | return !operator==(x); | |||
741 | } | |||
742 | ||||
743 | /// Return true if this iterator is at the end of uses list. | |||
744 | bool atEnd() const { return Op == nullptr; } | |||
745 | ||||
746 | // Iterator traversal: forward iteration only. | |||
747 | use_iterator &operator++() { // Preincrement | |||
748 | assert(Op && "Cannot increment end iterator!")((Op && "Cannot increment end iterator!") ? static_cast <void> (0) : __assert_fail ("Op && \"Cannot increment end iterator!\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/CodeGen/SelectionDAGNodes.h" , 748, __PRETTY_FUNCTION__)); | |||
749 | Op = Op->getNext(); | |||
750 | return *this; | |||
751 | } | |||
752 | ||||
753 | use_iterator operator++(int) { // Postincrement | |||
754 | use_iterator tmp = *this; ++*this; return tmp; | |||
755 | } | |||
756 | ||||
757 | /// Retrieve a pointer to the current user node. | |||
758 | SDNode *operator*() const { | |||
759 | assert(Op && "Cannot dereference end iterator!")((Op && "Cannot dereference end iterator!") ? static_cast <void> (0) : __assert_fail ("Op && \"Cannot dereference end iterator!\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/CodeGen/SelectionDAGNodes.h" , 759, __PRETTY_FUNCTION__)); | |||
760 | return Op->getUser(); | |||
761 | } | |||
762 | ||||
763 | SDNode *operator->() const { return operator*(); } | |||
764 | ||||
765 | SDUse &getUse() const { return *Op; } | |||
766 | ||||
767 | /// Retrieve the operand # of this use in its user. | |||
768 | unsigned getOperandNo() const { | |||
769 | assert(Op && "Cannot dereference end iterator!")((Op && "Cannot dereference end iterator!") ? static_cast <void> (0) : __assert_fail ("Op && \"Cannot dereference end iterator!\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/CodeGen/SelectionDAGNodes.h" , 769, __PRETTY_FUNCTION__)); | |||
770 | return (unsigned)(Op - Op->getUser()->OperandList); | |||
771 | } | |||
772 | }; | |||
773 | ||||
774 | /// Provide iteration support to walk over all uses of an SDNode. | |||
775 | use_iterator use_begin() const { | |||
776 | return use_iterator(UseList); | |||
777 | } | |||
778 | ||||
779 | static use_iterator use_end() { return use_iterator(nullptr); } | |||
780 | ||||
781 | inline iterator_range<use_iterator> uses() { | |||
782 | return make_range(use_begin(), use_end()); | |||
783 | } | |||
784 | inline iterator_range<use_iterator> uses() const { | |||
785 | return make_range(use_begin(), use_end()); | |||
786 | } | |||
787 | ||||
788 | /// Return true if there are exactly NUSES uses of the indicated value. | |||
789 | /// This method ignores uses of other values defined by this operation. | |||
790 | bool hasNUsesOfValue(unsigned NUses, unsigned Value) const; | |||
791 | ||||
792 | /// Return true if there are any use of the indicated value. | |||
793 | /// This method ignores uses of other values defined by this operation. | |||
794 | bool hasAnyUseOfValue(unsigned Value) const; | |||
795 | ||||
796 | /// Return true if this node is the only use of N. | |||
797 | bool isOnlyUserOf(const SDNode *N) const; | |||
798 | ||||
799 | /// Return true if this node is an operand of N. | |||
800 | bool isOperandOf(const SDNode *N) const; | |||
801 | ||||
802 | /// Return true if this node is a predecessor of N. | |||
803 | /// NOTE: Implemented on top of hasPredecessor and every bit as | |||
804 | /// expensive. Use carefully. | |||
805 | bool isPredecessorOf(const SDNode *N) const { | |||
806 | return N->hasPredecessor(this); | |||
807 | } | |||
808 | ||||
809 | /// Return true if N is a predecessor of this node. | |||
810 | /// N is either an operand of this node, or can be reached by recursively | |||
811 | /// traversing up the operands. | |||
812 | /// NOTE: This is an expensive method. Use it carefully. | |||
813 | bool hasPredecessor(const SDNode *N) const; | |||
814 | ||||
815 | /// Returns true if N is a predecessor of any node in Worklist. This | |||
816 | /// helper keeps Visited and Worklist sets externally to allow unions | |||
817 | /// searches to be performed in parallel, caching of results across | |||
818 | /// queries and incremental addition to Worklist. Stops early if N is | |||
819 | /// found but will resume. Remember to clear Visited and Worklists | |||
820 | /// if DAG changes. MaxSteps gives a maximum number of nodes to visit before | |||
821 | /// giving up. The TopologicalPrune flag signals that positive NodeIds are | |||
822 | /// topologically ordered (Operands have strictly smaller node id) and search | |||
823 | /// can be pruned leveraging this. | |||
824 | static bool hasPredecessorHelper(const SDNode *N, | |||
825 | SmallPtrSetImpl<const SDNode *> &Visited, | |||
826 | SmallVectorImpl<const SDNode *> &Worklist, | |||
827 | unsigned int MaxSteps = 0, | |||
828 | bool TopologicalPrune = false) { | |||
829 | SmallVector<const SDNode *, 8> DeferredNodes; | |||
830 | if (Visited.count(N)) | |||
831 | return true; | |||
832 | ||||
833 | // Node Id's are assigned in three places: As a topological | |||
834 | // ordering (> 0), during legalization (results in values set to | |||
835 | // 0), new nodes (set to -1). If N has a topolgical id then we | |||
836 | // know that all nodes with ids smaller than it cannot be | |||
837 | // successors and we need not check them. Filter out all node | |||
838 | // that can't be matches. We add them to the worklist before exit | |||
839 | // in case of multiple calls. Note that during selection the topological id | |||
840 | // may be violated if a node's predecessor is selected before it. We mark | |||
841 | // this at selection negating the id of unselected successors and | |||
842 | // restricting topological pruning to positive ids. | |||
843 | ||||
844 | int NId = N->getNodeId(); | |||
845 | // If we Invalidated the Id, reconstruct original NId. | |||
846 | if (NId < -1) | |||
847 | NId = -(NId + 1); | |||
848 | ||||
849 | bool Found = false; | |||
850 | while (!Worklist.empty()) { | |||
851 | const SDNode *M = Worklist.pop_back_val(); | |||
852 | int MId = M->getNodeId(); | |||
853 | if (TopologicalPrune && M->getOpcode() != ISD::TokenFactor && (NId > 0) && | |||
854 | (MId > 0) && (MId < NId)) { | |||
855 | DeferredNodes.push_back(M); | |||
856 | continue; | |||
857 | } | |||
858 | for (const SDValue &OpV : M->op_values()) { | |||
859 | SDNode *Op = OpV.getNode(); | |||
860 | if (Visited.insert(Op).second) | |||
861 | Worklist.push_back(Op); | |||
862 | if (Op == N) | |||
863 | Found = true; | |||
864 | } | |||
865 | if (Found) | |||
866 | break; | |||
867 | if (MaxSteps != 0 && Visited.size() >= MaxSteps) | |||
868 | break; | |||
869 | } | |||
870 | // Push deferred nodes back on worklist. | |||
871 | Worklist.append(DeferredNodes.begin(), DeferredNodes.end()); | |||
872 | // If we bailed early, conservatively return found. | |||
873 | if (MaxSteps != 0 && Visited.size() >= MaxSteps) | |||
874 | return true; | |||
875 | return Found; | |||
876 | } | |||
877 | ||||
878 | /// Return true if all the users of N are contained in Nodes. | |||
879 | /// NOTE: Requires at least one match, but doesn't require them all. | |||
880 | static bool areOnlyUsersOf(ArrayRef<const SDNode *> Nodes, const SDNode *N); | |||
881 | ||||
882 | /// Return the number of values used by this operation. | |||
883 | unsigned getNumOperands() const { return NumOperands; } | |||
884 | ||||
885 | /// Return the maximum number of operands that a SDNode can hold. | |||
886 | static constexpr size_t getMaxNumOperands() { | |||
887 | return std::numeric_limits<decltype(SDNode::NumOperands)>::max(); | |||
888 | } | |||
889 | ||||
890 | /// Helper method returns the integer value of a ConstantSDNode operand. | |||
891 | inline uint64_t getConstantOperandVal(unsigned Num) const; | |||
892 | ||||
893 | /// Helper method returns the APInt of a ConstantSDNode operand. | |||
894 | inline const APInt &getConstantOperandAPInt(unsigned Num) const; | |||
895 | ||||
896 | const SDValue &getOperand(unsigned Num) const { | |||
897 | assert(Num < NumOperands && "Invalid child # of SDNode!")((Num < NumOperands && "Invalid child # of SDNode!" ) ? static_cast<void> (0) : __assert_fail ("Num < NumOperands && \"Invalid child # of SDNode!\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/CodeGen/SelectionDAGNodes.h" , 897, __PRETTY_FUNCTION__)); | |||
898 | return OperandList[Num]; | |||
899 | } | |||
900 | ||||
901 | using op_iterator = SDUse *; | |||
902 | ||||
903 | op_iterator op_begin() const { return OperandList; } | |||
904 | op_iterator op_end() const { return OperandList+NumOperands; } | |||
905 | ArrayRef<SDUse> ops() const { return makeArrayRef(op_begin(), op_end()); } | |||
906 | ||||
907 | /// Iterator for directly iterating over the operand SDValue's. | |||
908 | struct value_op_iterator | |||
909 | : iterator_adaptor_base<value_op_iterator, op_iterator, | |||
910 | std::random_access_iterator_tag, SDValue, | |||
911 | ptrdiff_t, value_op_iterator *, | |||
912 | value_op_iterator *> { | |||
913 | explicit value_op_iterator(SDUse *U = nullptr) | |||
914 | : iterator_adaptor_base(U) {} | |||
915 | ||||
916 | const SDValue &operator*() const { return I->get(); } | |||
917 | }; | |||
918 | ||||
919 | iterator_range<value_op_iterator> op_values() const { | |||
920 | return make_range(value_op_iterator(op_begin()), | |||
921 | value_op_iterator(op_end())); | |||
922 | } | |||
923 | ||||
924 | SDVTList getVTList() const { | |||
925 | SDVTList X = { ValueList, NumValues }; | |||
926 | return X; | |||
927 | } | |||
928 | ||||
929 | /// If this node has a glue operand, return the node | |||
930 | /// to which the glue operand points. Otherwise return NULL. | |||
931 | SDNode *getGluedNode() const { | |||
932 | if (getNumOperands() != 0 && | |||
933 | getOperand(getNumOperands()-1).getValueType() == MVT::Glue) | |||
934 | return getOperand(getNumOperands()-1).getNode(); | |||
935 | return nullptr; | |||
936 | } | |||
937 | ||||
938 | /// If this node has a glue value with a user, return | |||
939 | /// the user (there is at most one). Otherwise return NULL. | |||
940 | SDNode *getGluedUser() const { | |||
941 | for (use_iterator UI = use_begin(), UE = use_end(); UI != UE; ++UI) | |||
942 | if (UI.getUse().get().getValueType() == MVT::Glue) | |||
943 | return *UI; | |||
944 | return nullptr; | |||
945 | } | |||
946 | ||||
947 | SDNodeFlags getFlags() const { return Flags; } | |||
948 | void setFlags(SDNodeFlags NewFlags) { Flags = NewFlags; } | |||
949 | ||||
950 | /// Clear any flags in this node that aren't also set in Flags. | |||
951 | /// If Flags is not in a defined state then this has no effect. | |||
952 | void intersectFlagsWith(const SDNodeFlags Flags); | |||
953 | ||||
954 | /// Return the number of values defined/returned by this operator. | |||
955 | unsigned getNumValues() const { return NumValues; } | |||
956 | ||||
957 | /// Return the type of a specified result. | |||
958 | EVT getValueType(unsigned ResNo) const { | |||
959 | assert(ResNo < NumValues && "Illegal result number!")((ResNo < NumValues && "Illegal result number!") ? static_cast<void> (0) : __assert_fail ("ResNo < NumValues && \"Illegal result number!\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/CodeGen/SelectionDAGNodes.h" , 959, __PRETTY_FUNCTION__)); | |||
960 | return ValueList[ResNo]; | |||
961 | } | |||
962 | ||||
963 | /// Return the type of a specified result as a simple type. | |||
964 | MVT getSimpleValueType(unsigned ResNo) const { | |||
965 | return getValueType(ResNo).getSimpleVT(); | |||
966 | } | |||
967 | ||||
968 | /// Returns MVT::getSizeInBits(getValueType(ResNo)). | |||
969 | /// | |||
970 | /// If the value type is a scalable vector type, the scalable property will | |||
971 | /// be set and the runtime size will be a positive integer multiple of the | |||
972 | /// base size. | |||
973 | TypeSize getValueSizeInBits(unsigned ResNo) const { | |||
974 | return getValueType(ResNo).getSizeInBits(); | |||
975 | } | |||
976 | ||||
977 | using value_iterator = const EVT *; | |||
978 | ||||
979 | value_iterator value_begin() const { return ValueList; } | |||
980 | value_iterator value_end() const { return ValueList+NumValues; } | |||
981 | iterator_range<value_iterator> values() const { | |||
982 | return llvm::make_range(value_begin(), value_end()); | |||
983 | } | |||
984 | ||||
985 | /// Return the opcode of this operation for printing. | |||
986 | std::string getOperationName(const SelectionDAG *G = nullptr) const; | |||
987 | static const char* getIndexedModeName(ISD::MemIndexedMode AM); | |||
988 | void print_types(raw_ostream &OS, const SelectionDAG *G) const; | |||
989 | void print_details(raw_ostream &OS, const SelectionDAG *G) const; | |||
990 | void print(raw_ostream &OS, const SelectionDAG *G = nullptr) const; | |||
991 | void printr(raw_ostream &OS, const SelectionDAG *G = nullptr) const; | |||
992 | ||||
993 | /// Print a SelectionDAG node and all children down to | |||
994 | /// the leaves. The given SelectionDAG allows target-specific nodes | |||
995 | /// to be printed in human-readable form. Unlike printr, this will | |||
996 | /// print the whole DAG, including children that appear multiple | |||
997 | /// times. | |||
998 | /// | |||
999 | void printrFull(raw_ostream &O, const SelectionDAG *G = nullptr) const; | |||
1000 | ||||
1001 | /// Print a SelectionDAG node and children up to | |||
1002 | /// depth "depth." The given SelectionDAG allows target-specific | |||
1003 | /// nodes to be printed in human-readable form. Unlike printr, this | |||
1004 | /// will print children that appear multiple times wherever they are | |||
1005 | /// used. | |||
1006 | /// | |||
1007 | void printrWithDepth(raw_ostream &O, const SelectionDAG *G = nullptr, | |||
1008 | unsigned depth = 100) const; | |||
1009 | ||||
1010 | /// Dump this node, for debugging. | |||
1011 | void dump() const; | |||
1012 | ||||
1013 | /// Dump (recursively) this node and its use-def subgraph. | |||
1014 | void dumpr() const; | |||
1015 | ||||
1016 | /// Dump this node, for debugging. | |||
1017 | /// The given SelectionDAG allows target-specific nodes to be printed | |||
1018 | /// in human-readable form. | |||
1019 | void dump(const SelectionDAG *G) const; | |||
1020 | ||||
1021 | /// Dump (recursively) this node and its use-def subgraph. | |||
1022 | /// The given SelectionDAG allows target-specific nodes to be printed | |||
1023 | /// in human-readable form. | |||
1024 | void dumpr(const SelectionDAG *G) const; | |||
1025 | ||||
1026 | /// printrFull to dbgs(). The given SelectionDAG allows | |||
1027 | /// target-specific nodes to be printed in human-readable form. | |||
1028 | /// Unlike dumpr, this will print the whole DAG, including children | |||
1029 | /// that appear multiple times. | |||
1030 | void dumprFull(const SelectionDAG *G = nullptr) const; | |||
1031 | ||||
1032 | /// printrWithDepth to dbgs(). The given | |||
1033 | /// SelectionDAG allows target-specific nodes to be printed in | |||
1034 | /// human-readable form. Unlike dumpr, this will print children | |||
1035 | /// that appear multiple times wherever they are used. | |||
1036 | /// | |||
1037 | void dumprWithDepth(const SelectionDAG *G = nullptr, | |||
1038 | unsigned depth = 100) const; | |||
1039 | ||||
1040 | /// Gather unique data for the node. | |||
1041 | void Profile(FoldingSetNodeID &ID) const; | |||
1042 | ||||
1043 | /// This method should only be used by the SDUse class. | |||
1044 | void addUse(SDUse &U) { U.addToList(&UseList); } | |||
1045 | ||||
1046 | protected: | |||
1047 | static SDVTList getSDVTList(EVT VT) { | |||
1048 | SDVTList Ret = { getValueTypeList(VT), 1 }; | |||
1049 | return Ret; | |||
1050 | } | |||
1051 | ||||
1052 | /// Create an SDNode. | |||
1053 | /// | |||
1054 | /// SDNodes are created without any operands, and never own the operand | |||
1055 | /// storage. To add operands, see SelectionDAG::createOperands. | |||
1056 | SDNode(unsigned Opc, unsigned Order, DebugLoc dl, SDVTList VTs) | |||
1057 | : NodeType(Opc), ValueList(VTs.VTs), NumValues(VTs.NumVTs), | |||
1058 | IROrder(Order), debugLoc(std::move(dl)) { | |||
1059 | memset(&RawSDNodeBits, 0, sizeof(RawSDNodeBits)); | |||
1060 | assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor")((debugLoc.hasTrivialDestructor() && "Expected trivial destructor" ) ? static_cast<void> (0) : __assert_fail ("debugLoc.hasTrivialDestructor() && \"Expected trivial destructor\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/CodeGen/SelectionDAGNodes.h" , 1060, __PRETTY_FUNCTION__)); | |||
1061 | assert(NumValues == VTs.NumVTs &&((NumValues == VTs.NumVTs && "NumValues wasn't wide enough for its operands!" ) ? static_cast<void> (0) : __assert_fail ("NumValues == VTs.NumVTs && \"NumValues wasn't wide enough for its operands!\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/CodeGen/SelectionDAGNodes.h" , 1062, __PRETTY_FUNCTION__)) | |||
1062 | "NumValues wasn't wide enough for its operands!")((NumValues == VTs.NumVTs && "NumValues wasn't wide enough for its operands!" ) ? static_cast<void> (0) : __assert_fail ("NumValues == VTs.NumVTs && \"NumValues wasn't wide enough for its operands!\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/CodeGen/SelectionDAGNodes.h" , 1062, __PRETTY_FUNCTION__)); | |||
1063 | } | |||
1064 | ||||
1065 | /// Release the operands and set this node to have zero operands. | |||
1066 | void DropOperands(); | |||
1067 | }; | |||
1068 | ||||
1069 | /// Wrapper class for IR location info (IR ordering and DebugLoc) to be passed | |||
1070 | /// into SDNode creation functions. | |||
1071 | /// When an SDNode is created from the DAGBuilder, the DebugLoc is extracted | |||
1072 | /// from the original Instruction, and IROrder is the ordinal position of | |||
1073 | /// the instruction. | |||
1074 | /// When an SDNode is created after the DAG is being built, both DebugLoc and | |||
1075 | /// the IROrder are propagated from the original SDNode. | |||
1076 | /// So SDLoc class provides two constructors besides the default one, one to | |||
1077 | /// be used by the DAGBuilder, the other to be used by others. | |||
1078 | class SDLoc { | |||
1079 | private: | |||
1080 | DebugLoc DL; | |||
1081 | int IROrder = 0; | |||
1082 | ||||
1083 | public: | |||
1084 | SDLoc() = default; | |||
1085 | SDLoc(const SDNode *N) : DL(N->getDebugLoc()), IROrder(N->getIROrder()) {} | |||
1086 | SDLoc(const SDValue V) : SDLoc(V.getNode()) {} | |||
1087 | SDLoc(const Instruction *I, int Order) : IROrder(Order) { | |||
1088 | assert(Order >= 0 && "bad IROrder")((Order >= 0 && "bad IROrder") ? static_cast<void > (0) : __assert_fail ("Order >= 0 && \"bad IROrder\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/CodeGen/SelectionDAGNodes.h" , 1088, __PRETTY_FUNCTION__)); | |||
1089 | if (I) | |||
1090 | DL = I->getDebugLoc(); | |||
1091 | } | |||
1092 | ||||
1093 | unsigned getIROrder() const { return IROrder; } | |||
1094 | const DebugLoc &getDebugLoc() const { return DL; } | |||
1095 | }; | |||
1096 | ||||
1097 | // Define inline functions from the SDValue class. | |||
1098 | ||||
1099 | inline SDValue::SDValue(SDNode *node, unsigned resno) | |||
1100 | : Node(node), ResNo(resno) { | |||
1101 | // Explicitly check for !ResNo to avoid use-after-free, because there are | |||
1102 | // callers that use SDValue(N, 0) with a deleted N to indicate successful | |||
1103 | // combines. | |||
1104 | assert((!Node || !ResNo || ResNo < Node->getNumValues()) &&(((!Node || !ResNo || ResNo < Node->getNumValues()) && "Invalid result number for the given node!") ? static_cast< void> (0) : __assert_fail ("(!Node || !ResNo || ResNo < Node->getNumValues()) && \"Invalid result number for the given node!\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/CodeGen/SelectionDAGNodes.h" , 1105, __PRETTY_FUNCTION__)) | |||
1105 | "Invalid result number for the given node!")(((!Node || !ResNo || ResNo < Node->getNumValues()) && "Invalid result number for the given node!") ? static_cast< void> (0) : __assert_fail ("(!Node || !ResNo || ResNo < Node->getNumValues()) && \"Invalid result number for the given node!\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/CodeGen/SelectionDAGNodes.h" , 1105, __PRETTY_FUNCTION__)); | |||
1106 | assert(ResNo < -2U && "Cannot use result numbers reserved for DenseMaps.")((ResNo < -2U && "Cannot use result numbers reserved for DenseMaps." ) ? static_cast<void> (0) : __assert_fail ("ResNo < -2U && \"Cannot use result numbers reserved for DenseMaps.\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/CodeGen/SelectionDAGNodes.h" , 1106, __PRETTY_FUNCTION__)); | |||
1107 | } | |||
1108 | ||||
1109 | inline unsigned SDValue::getOpcode() const { | |||
1110 | return Node->getOpcode(); | |||
1111 | } | |||
1112 | ||||
1113 | inline EVT SDValue::getValueType() const { | |||
1114 | return Node->getValueType(ResNo); | |||
| ||||
1115 | } | |||
1116 | ||||
1117 | inline unsigned SDValue::getNumOperands() const { | |||
1118 | return Node->getNumOperands(); | |||
1119 | } | |||
1120 | ||||
1121 | inline const SDValue &SDValue::getOperand(unsigned i) const { | |||
1122 | return Node->getOperand(i); | |||
1123 | } | |||
1124 | ||||
1125 | inline uint64_t SDValue::getConstantOperandVal(unsigned i) const { | |||
1126 | return Node->getConstantOperandVal(i); | |||
1127 | } | |||
1128 | ||||
1129 | inline const APInt &SDValue::getConstantOperandAPInt(unsigned i) const { | |||
1130 | return Node->getConstantOperandAPInt(i); | |||
1131 | } | |||
1132 | ||||
1133 | inline bool SDValue::isTargetOpcode() const { | |||
1134 | return Node->isTargetOpcode(); | |||
1135 | } | |||
1136 | ||||
1137 | inline bool SDValue::isTargetMemoryOpcode() const { | |||
1138 | return Node->isTargetMemoryOpcode(); | |||
1139 | } | |||
1140 | ||||
1141 | inline bool SDValue::isMachineOpcode() const { | |||
1142 | return Node->isMachineOpcode(); | |||
1143 | } | |||
1144 | ||||
1145 | inline unsigned SDValue::getMachineOpcode() const { | |||
1146 | return Node->getMachineOpcode(); | |||
1147 | } | |||
1148 | ||||
1149 | inline bool SDValue::isUndef() const { | |||
1150 | return Node->isUndef(); | |||
1151 | } | |||
1152 | ||||
1153 | inline bool SDValue::use_empty() const { | |||
1154 | return !Node->hasAnyUseOfValue(ResNo); | |||
1155 | } | |||
1156 | ||||
1157 | inline bool SDValue::hasOneUse() const { | |||
1158 | return Node->hasNUsesOfValue(1, ResNo); | |||
1159 | } | |||
1160 | ||||
1161 | inline const DebugLoc &SDValue::getDebugLoc() const { | |||
1162 | return Node->getDebugLoc(); | |||
1163 | } | |||
1164 | ||||
1165 | inline void SDValue::dump() const { | |||
1166 | return Node->dump(); | |||
1167 | } | |||
1168 | ||||
1169 | inline void SDValue::dump(const SelectionDAG *G) const { | |||
1170 | return Node->dump(G); | |||
1171 | } | |||
1172 | ||||
1173 | inline void SDValue::dumpr() const { | |||
1174 | return Node->dumpr(); | |||
1175 | } | |||
1176 | ||||
1177 | inline void SDValue::dumpr(const SelectionDAG *G) const { | |||
1178 | return Node->dumpr(G); | |||
1179 | } | |||
1180 | ||||
1181 | // Define inline functions from the SDUse class. | |||
1182 | ||||
1183 | inline void SDUse::set(const SDValue &V) { | |||
1184 | if (Val.getNode()) removeFromList(); | |||
1185 | Val = V; | |||
1186 | if (V.getNode()) V.getNode()->addUse(*this); | |||
1187 | } | |||
1188 | ||||
1189 | inline void SDUse::setInitial(const SDValue &V) { | |||
1190 | Val = V; | |||
1191 | V.getNode()->addUse(*this); | |||
1192 | } | |||
1193 | ||||
1194 | inline void SDUse::setNode(SDNode *N) { | |||
1195 | if (Val.getNode()) removeFromList(); | |||
1196 | Val.setNode(N); | |||
1197 | if (N) N->addUse(*this); | |||
1198 | } | |||
1199 | ||||
1200 | /// This class is used to form a handle around another node that | |||
1201 | /// is persistent and is updated across invocations of replaceAllUsesWith on its | |||
1202 | /// operand. This node should be directly created by end-users and not added to | |||
1203 | /// the AllNodes list. | |||
1204 | class HandleSDNode : public SDNode { | |||
1205 | SDUse Op; | |||
1206 | ||||
1207 | public: | |||
1208 | explicit HandleSDNode(SDValue X) | |||
1209 | : SDNode(ISD::HANDLENODE, 0, DebugLoc(), getSDVTList(MVT::Other)) { | |||
1210 | // HandleSDNodes are never inserted into the DAG, so they won't be | |||
1211 | // auto-numbered. Use ID 65535 as a sentinel. | |||
1212 | PersistentId = 0xffff; | |||
1213 | ||||
1214 | // Manually set up the operand list. This node type is special in that it's | |||
1215 | // always stack allocated and SelectionDAG does not manage its operands. | |||
1216 | // TODO: This should either (a) not be in the SDNode hierarchy, or (b) not | |||
1217 | // be so special. | |||
1218 | Op.setUser(this); | |||
1219 | Op.setInitial(X); | |||
1220 | NumOperands = 1; | |||
1221 | OperandList = &Op; | |||
1222 | } | |||
1223 | ~HandleSDNode(); | |||
1224 | ||||
1225 | const SDValue &getValue() const { return Op; } | |||
1226 | }; | |||
1227 | ||||
1228 | class AddrSpaceCastSDNode : public SDNode { | |||
1229 | private: | |||
1230 | unsigned SrcAddrSpace; | |||
1231 | unsigned DestAddrSpace; | |||
1232 | ||||
1233 | public: | |||
1234 | AddrSpaceCastSDNode(unsigned Order, const DebugLoc &dl, EVT VT, | |||
1235 | unsigned SrcAS, unsigned DestAS); | |||
1236 | ||||
1237 | unsigned getSrcAddressSpace() const { return SrcAddrSpace; } | |||
1238 | unsigned getDestAddressSpace() const { return DestAddrSpace; } | |||
1239 | ||||
1240 | static bool classof(const SDNode *N) { | |||
1241 | return N->getOpcode() == ISD::ADDRSPACECAST; | |||
1242 | } | |||
1243 | }; | |||
1244 | ||||
1245 | /// This is an abstract virtual class for memory operations. | |||
1246 | class MemSDNode : public SDNode { | |||
1247 | private: | |||
1248 | // VT of in-memory value. | |||
1249 | EVT MemoryVT; | |||
1250 | ||||
1251 | protected: | |||
1252 | /// Memory reference information. | |||
1253 | MachineMemOperand *MMO; | |||
1254 | ||||
1255 | public: | |||
1256 | MemSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl, SDVTList VTs, | |||
1257 | EVT memvt, MachineMemOperand *MMO); | |||
1258 | ||||
1259 | bool readMem() const { return MMO->isLoad(); } | |||
1260 | bool writeMem() const { return MMO->isStore(); } | |||
1261 | ||||
1262 | /// Returns alignment and volatility of the memory access | |||
1263 | Align getOriginalAlign() const { return MMO->getBaseAlign(); } | |||
1264 | Align getAlign() const { return MMO->getAlign(); } | |||
1265 | LLVM_ATTRIBUTE_DEPRECATED(unsigned getOriginalAlignment() const,[[deprecated("Use getOriginalAlign() instead")]] unsigned getOriginalAlignment () const | |||
1266 | "Use getOriginalAlign() instead")[[deprecated("Use getOriginalAlign() instead")]] unsigned getOriginalAlignment () const { | |||
1267 | return MMO->getBaseAlign().value(); | |||
1268 | } | |||
1269 | // FIXME: Remove once transition to getAlign is over. | |||
1270 | unsigned getAlignment() const { return MMO->getAlign().value(); } | |||
1271 | ||||
1272 | /// Return the SubclassData value, without HasDebugValue. This contains an | |||
1273 | /// encoding of the volatile flag, as well as bits used by subclasses. This | |||
1274 | /// function should only be used to compute a FoldingSetNodeID value. | |||
1275 | /// The HasDebugValue bit is masked out because CSE map needs to match | |||
1276 | /// nodes with debug info with nodes without debug info. Same is about | |||
1277 | /// isDivergent bit. | |||
1278 | unsigned getRawSubclassData() const { | |||
1279 | uint16_t Data; | |||
1280 | union { | |||
1281 | char RawSDNodeBits[sizeof(uint16_t)]; | |||
1282 | SDNodeBitfields SDNodeBits; | |||
1283 | }; | |||
1284 | memcpy(&RawSDNodeBits, &this->RawSDNodeBits, sizeof(this->RawSDNodeBits)); | |||
1285 | SDNodeBits.HasDebugValue = 0; | |||
1286 | SDNodeBits.IsDivergent = false; | |||
1287 | memcpy(&Data, &RawSDNodeBits, sizeof(RawSDNodeBits)); | |||
1288 | return Data; | |||
1289 | } | |||
1290 | ||||
1291 | bool isVolatile() const { return MemSDNodeBits.IsVolatile; } | |||
1292 | bool isNonTemporal() const { return MemSDNodeBits.IsNonTemporal; } | |||
1293 | bool isDereferenceable() const { return MemSDNodeBits.IsDereferenceable; } | |||
1294 | bool isInvariant() const { return MemSDNodeBits.IsInvariant; } | |||
1295 | ||||
1296 | // Returns the offset from the location of the access. | |||
1297 | int64_t getSrcValueOffset() const { return MMO->getOffset(); } | |||
1298 | ||||
1299 | /// Returns the AA info that describes the dereference. | |||
1300 | AAMDNodes getAAInfo() const { return MMO->getAAInfo(); } | |||
1301 | ||||
1302 | /// Returns the Ranges that describes the dereference. | |||
1303 | const MDNode *getRanges() const { return MMO->getRanges(); } | |||
1304 | ||||
1305 | /// Returns the synchronization scope ID for this memory operation. | |||
1306 | SyncScope::ID getSyncScopeID() const { return MMO->getSyncScopeID(); } | |||
1307 | ||||
1308 | /// Return the atomic ordering requirements for this memory operation. For | |||
1309 | /// cmpxchg atomic operations, return the atomic ordering requirements when | |||
1310 | /// store occurs. | |||
1311 | AtomicOrdering getOrdering() const { return MMO->getOrdering(); } | |||
1312 | ||||
1313 | /// Return true if the memory operation ordering is Unordered or higher. | |||
1314 | bool isAtomic() const { return MMO->isAtomic(); } | |||
1315 | ||||
1316 | /// Returns true if the memory operation doesn't imply any ordering | |||
1317 | /// constraints on surrounding memory operations beyond the normal memory | |||
1318 | /// aliasing rules. | |||
1319 | bool isUnordered() const { return MMO->isUnordered(); } | |||
1320 | ||||
1321 | /// Returns true if the memory operation is neither atomic or volatile. | |||
1322 | bool isSimple() const { return !isAtomic() && !isVolatile(); } | |||
1323 | ||||
1324 | /// Return the type of the in-memory value. | |||
1325 | EVT getMemoryVT() const { return MemoryVT; } | |||
1326 | ||||
1327 | /// Return a MachineMemOperand object describing the memory | |||
1328 | /// reference performed by operation. | |||
1329 | MachineMemOperand *getMemOperand() const { return MMO; } | |||
1330 | ||||
1331 | const MachinePointerInfo &getPointerInfo() const { | |||
1332 | return MMO->getPointerInfo(); | |||
1333 | } | |||
1334 | ||||
1335 | /// Return the address space for the associated pointer | |||
1336 | unsigned getAddressSpace() const { | |||
1337 | return getPointerInfo().getAddrSpace(); | |||
1338 | } | |||
1339 | ||||
1340 | /// Update this MemSDNode's MachineMemOperand information | |||
1341 | /// to reflect the alignment of NewMMO, if it has a greater alignment. | |||
1342 | /// This must only be used when the new alignment applies to all users of | |||
1343 | /// this MachineMemOperand. | |||
1344 | void refineAlignment(const MachineMemOperand *NewMMO) { | |||
1345 | MMO->refineAlignment(NewMMO); | |||
1346 | } | |||
1347 | ||||
1348 | const SDValue &getChain() const { return getOperand(0); } | |||
1349 | ||||
1350 | const SDValue &getBasePtr() const { | |||
1351 | switch (getOpcode()) { | |||
1352 | case ISD::STORE: | |||
1353 | case ISD::MSTORE: | |||
1354 | return getOperand(2); | |||
1355 | case ISD::MGATHER: | |||
1356 | case ISD::MSCATTER: | |||
1357 | return getOperand(3); | |||
1358 | default: | |||
1359 | return getOperand(1); | |||
1360 | } | |||
1361 | } | |||
1362 | ||||
1363 | // Methods to support isa and dyn_cast | |||
1364 | static bool classof(const SDNode *N) { | |||
1365 | // For some targets, we lower some target intrinsics to a MemIntrinsicNode | |||
1366 | // with either an intrinsic or a target opcode. | |||
1367 | return N->getOpcode() == ISD::LOAD || | |||
1368 | N->getOpcode() == ISD::STORE || | |||
1369 | N->getOpcode() == ISD::PREFETCH || | |||
1370 | N->getOpcode() == ISD::ATOMIC_CMP_SWAP || | |||
1371 | N->getOpcode() == ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS || | |||
1372 | N->getOpcode() == ISD::ATOMIC_SWAP || | |||
1373 | N->getOpcode() == ISD::ATOMIC_LOAD_ADD || | |||
1374 | N->getOpcode() == ISD::ATOMIC_LOAD_SUB || | |||
1375 | N->getOpcode() == ISD::ATOMIC_LOAD_AND || | |||
1376 | N->getOpcode() == ISD::ATOMIC_LOAD_CLR || | |||
1377 | N->getOpcode() == ISD::ATOMIC_LOAD_OR || | |||
1378 | N->getOpcode() == ISD::ATOMIC_LOAD_XOR || | |||
1379 | N->getOpcode() == ISD::ATOMIC_LOAD_NAND || | |||
1380 | N->getOpcode() == ISD::ATOMIC_LOAD_MIN || | |||
1381 | N->getOpcode() == ISD::ATOMIC_LOAD_MAX || | |||
1382 | N->getOpcode() == ISD::ATOMIC_LOAD_UMIN || | |||
1383 | N->getOpcode() == ISD::ATOMIC_LOAD_UMAX || | |||
1384 | N->getOpcode() == ISD::ATOMIC_LOAD_FADD || | |||
1385 | N->getOpcode() == ISD::ATOMIC_LOAD_FSUB || | |||
1386 | N->getOpcode() == ISD::ATOMIC_LOAD || | |||
1387 | N->getOpcode() == ISD::ATOMIC_STORE || | |||
1388 | N->getOpcode() == ISD::MLOAD || | |||
1389 | N->getOpcode() == ISD::MSTORE || | |||
1390 | N->getOpcode() == ISD::MGATHER || | |||
1391 | N->getOpcode() == ISD::MSCATTER || | |||
1392 | N->isMemIntrinsic() || | |||
1393 | N->isTargetMemoryOpcode(); | |||
1394 | } | |||
1395 | }; | |||
1396 | ||||
1397 | /// This is an SDNode representing atomic operations. | |||
1398 | class AtomicSDNode : public MemSDNode { | |||
1399 | public: | |||
1400 | AtomicSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl, SDVTList VTL, | |||
1401 | EVT MemVT, MachineMemOperand *MMO) | |||
1402 | : MemSDNode(Opc, Order, dl, VTL, MemVT, MMO) { | |||
1403 | assert(((Opc != ISD::ATOMIC_LOAD && Opc != ISD::ATOMIC_STORE) ||((((Opc != ISD::ATOMIC_LOAD && Opc != ISD::ATOMIC_STORE ) || MMO->isAtomic()) && "then why are we using an AtomicSDNode?" ) ? static_cast<void> (0) : __assert_fail ("((Opc != ISD::ATOMIC_LOAD && Opc != ISD::ATOMIC_STORE) || MMO->isAtomic()) && \"then why are we using an AtomicSDNode?\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/CodeGen/SelectionDAGNodes.h" , 1404, __PRETTY_FUNCTION__)) | |||
1404 | MMO->isAtomic()) && "then why are we using an AtomicSDNode?")((((Opc != ISD::ATOMIC_LOAD && Opc != ISD::ATOMIC_STORE ) || MMO->isAtomic()) && "then why are we using an AtomicSDNode?" ) ? static_cast<void> (0) : __assert_fail ("((Opc != ISD::ATOMIC_LOAD && Opc != ISD::ATOMIC_STORE) || MMO->isAtomic()) && \"then why are we using an AtomicSDNode?\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/CodeGen/SelectionDAGNodes.h" , 1404, __PRETTY_FUNCTION__)); | |||
1405 | } | |||
1406 | ||||
1407 | const SDValue &getBasePtr() const { return getOperand(1); } | |||
1408 | const SDValue &getVal() const { return getOperand(2); } | |||
1409 | ||||
1410 | /// Returns true if this SDNode represents cmpxchg atomic operation, false | |||
1411 | /// otherwise. | |||
1412 | bool isCompareAndSwap() const { | |||
1413 | unsigned Op = getOpcode(); | |||
1414 | return Op == ISD::ATOMIC_CMP_SWAP || | |||
1415 | Op == ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS; | |||
1416 | } | |||
1417 | ||||
1418 | /// For cmpxchg atomic operations, return the atomic ordering requirements | |||
1419 | /// when store does not occur. | |||
1420 | AtomicOrdering getFailureOrdering() const { | |||
1421 | assert(isCompareAndSwap() && "Must be cmpxchg operation")((isCompareAndSwap() && "Must be cmpxchg operation") ? static_cast<void> (0) : __assert_fail ("isCompareAndSwap() && \"Must be cmpxchg operation\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/CodeGen/SelectionDAGNodes.h" , 1421, __PRETTY_FUNCTION__)); | |||
1422 | return MMO->getFailureOrdering(); | |||
1423 | } | |||
1424 | ||||
1425 | // Methods to support isa and dyn_cast | |||
1426 | static bool classof(const SDNode *N) { | |||
1427 | return N->getOpcode() == ISD::ATOMIC_CMP_SWAP || | |||
1428 | N->getOpcode() == ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS || | |||
1429 | N->getOpcode() == ISD::ATOMIC_SWAP || | |||
1430 | N->getOpcode() == ISD::ATOMIC_LOAD_ADD || | |||
1431 | N->getOpcode() == ISD::ATOMIC_LOAD_SUB || | |||
1432 | N->getOpcode() == ISD::ATOMIC_LOAD_AND || | |||
1433 | N->getOpcode() == ISD::ATOMIC_LOAD_CLR || | |||
1434 | N->getOpcode() == ISD::ATOMIC_LOAD_OR || | |||
1435 | N->getOpcode() == ISD::ATOMIC_LOAD_XOR || | |||
1436 | N->getOpcode() == ISD::ATOMIC_LOAD_NAND || | |||
1437 | N->getOpcode() == ISD::ATOMIC_LOAD_MIN || | |||
1438 | N->getOpcode() == ISD::ATOMIC_LOAD_MAX || | |||
1439 | N->getOpcode() == ISD::ATOMIC_LOAD_UMIN || | |||
1440 | N->getOpcode() == ISD::ATOMIC_LOAD_UMAX || | |||
1441 | N->getOpcode() == ISD::ATOMIC_LOAD_FADD || | |||
1442 | N->getOpcode() == ISD::ATOMIC_LOAD_FSUB || | |||
1443 | N->getOpcode() == ISD::ATOMIC_LOAD || | |||
1444 | N->getOpcode() == ISD::ATOMIC_STORE; | |||
1445 | } | |||
1446 | }; | |||
1447 | ||||
1448 | /// This SDNode is used for target intrinsics that touch | |||
1449 | /// memory and need an associated MachineMemOperand. Its opcode may be | |||
1450 | /// INTRINSIC_VOID, INTRINSIC_W_CHAIN, PREFETCH, or a target-specific opcode | |||
1451 | /// with a value not less than FIRST_TARGET_MEMORY_OPCODE. | |||
1452 | class MemIntrinsicSDNode : public MemSDNode { | |||
1453 | public: | |||
1454 | MemIntrinsicSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl, | |||
1455 | SDVTList VTs, EVT MemoryVT, MachineMemOperand *MMO) | |||
1456 | : MemSDNode(Opc, Order, dl, VTs, MemoryVT, MMO) { | |||
1457 | SDNodeBits.IsMemIntrinsic = true; | |||
1458 | } | |||
1459 | ||||
1460 | // Methods to support isa and dyn_cast | |||
1461 | static bool classof(const SDNode *N) { | |||
1462 | // We lower some target intrinsics to their target opcode | |||
1463 | // early a node with a target opcode can be of this class | |||
1464 | return N->isMemIntrinsic() || | |||
1465 | N->getOpcode() == ISD::PREFETCH || | |||
1466 | N->isTargetMemoryOpcode(); | |||
1467 | } | |||
1468 | }; | |||
1469 | ||||
1470 | /// This SDNode is used to implement the code generator | |||
1471 | /// support for the llvm IR shufflevector instruction. It combines elements | |||
1472 | /// from two input vectors into a new input vector, with the selection and | |||
1473 | /// ordering of elements determined by an array of integers, referred to as | |||
1474 | /// the shuffle mask. For input vectors of width N, mask indices of 0..N-1 | |||
1475 | /// refer to elements from the LHS input, and indices from N to 2N-1 the RHS. | |||
1476 | /// An index of -1 is treated as undef, such that the code generator may put | |||
1477 | /// any value in the corresponding element of the result. | |||
1478 | class ShuffleVectorSDNode : public SDNode { | |||
1479 | // The memory for Mask is owned by the SelectionDAG's OperandAllocator, and | |||
1480 | // is freed when the SelectionDAG object is destroyed. | |||
1481 | const int *Mask; | |||
1482 | ||||
1483 | protected: | |||
1484 | friend class SelectionDAG; | |||
1485 | ||||
1486 | ShuffleVectorSDNode(EVT VT, unsigned Order, const DebugLoc &dl, const int *M) | |||
1487 | : SDNode(ISD::VECTOR_SHUFFLE, Order, dl, getSDVTList(VT)), Mask(M) {} | |||
1488 | ||||
1489 | public: | |||
1490 | ArrayRef<int> getMask() const { | |||
1491 | EVT VT = getValueType(0); | |||
1492 | return makeArrayRef(Mask, VT.getVectorNumElements()); | |||
1493 | } | |||
1494 | ||||
1495 | int getMaskElt(unsigned Idx) const { | |||
1496 | assert(Idx < getValueType(0).getVectorNumElements() && "Idx out of range!")((Idx < getValueType(0).getVectorNumElements() && "Idx out of range!" ) ? static_cast<void> (0) : __assert_fail ("Idx < getValueType(0).getVectorNumElements() && \"Idx out of range!\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/CodeGen/SelectionDAGNodes.h" , 1496, __PRETTY_FUNCTION__)); | |||
1497 | return Mask[Idx]; | |||
1498 | } | |||
1499 | ||||
1500 | bool isSplat() const { return isSplatMask(Mask, getValueType(0)); } | |||
1501 | ||||
1502 | int getSplatIndex() const { | |||
1503 | assert(isSplat() && "Cannot get splat index for non-splat!")((isSplat() && "Cannot get splat index for non-splat!" ) ? static_cast<void> (0) : __assert_fail ("isSplat() && \"Cannot get splat index for non-splat!\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/CodeGen/SelectionDAGNodes.h" , 1503, __PRETTY_FUNCTION__)); | |||
1504 | EVT VT = getValueType(0); | |||
1505 | for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) | |||
1506 | if (Mask[i] >= 0) | |||
1507 | return Mask[i]; | |||
1508 | ||||
1509 | // We can choose any index value here and be correct because all elements | |||
1510 | // are undefined. Return 0 for better potential for callers to simplify. | |||
1511 | return 0; | |||
1512 | } | |||
1513 | ||||
1514 | static bool isSplatMask(const int *Mask, EVT VT); | |||
1515 | ||||
1516 | /// Change values in a shuffle permute mask assuming | |||
1517 | /// the two vector operands have swapped position. | |||
1518 | static void commuteMask(MutableArrayRef<int> Mask) { | |||
1519 | unsigned NumElems = Mask.size(); | |||
1520 | for (unsigned i = 0; i != NumElems; ++i) { | |||
1521 | int idx = Mask[i]; | |||
1522 | if (idx < 0) | |||
1523 | continue; | |||
1524 | else if (idx < (int)NumElems) | |||
1525 | Mask[i] = idx + NumElems; | |||
1526 | else | |||
1527 | Mask[i] = idx - NumElems; | |||
1528 | } | |||
1529 | } | |||
1530 | ||||
1531 | static bool classof(const SDNode *N) { | |||
1532 | return N->getOpcode() == ISD::VECTOR_SHUFFLE; | |||
1533 | } | |||
1534 | }; | |||
1535 | ||||
1536 | class ConstantSDNode : public SDNode { | |||
1537 | friend class SelectionDAG; | |||
1538 | ||||
1539 | const ConstantInt *Value; | |||
1540 | ||||
1541 | ConstantSDNode(bool isTarget, bool isOpaque, const ConstantInt *val, EVT VT) | |||
1542 | : SDNode(isTarget ? ISD::TargetConstant : ISD::Constant, 0, DebugLoc(), | |||
1543 | getSDVTList(VT)), | |||
1544 | Value(val) { | |||
1545 | ConstantSDNodeBits.IsOpaque = isOpaque; | |||
1546 | } | |||
1547 | ||||
1548 | public: | |||
1549 | const ConstantInt *getConstantIntValue() const { return Value; } | |||
1550 | const APInt &getAPIntValue() const { return Value->getValue(); } | |||
1551 | uint64_t getZExtValue() const { return Value->getZExtValue(); } | |||
1552 | int64_t getSExtValue() const { return Value->getSExtValue(); } | |||
1553 | uint64_t getLimitedValue(uint64_t Limit = UINT64_MAX(18446744073709551615UL)) { | |||
1554 | return Value->getLimitedValue(Limit); | |||
1555 | } | |||
1556 | MaybeAlign getMaybeAlignValue() const { return Value->getMaybeAlignValue(); } | |||
1557 | Align getAlignValue() const { return Value->getAlignValue(); } | |||
1558 | ||||
1559 | bool isOne() const { return Value->isOne(); } | |||
1560 | bool isNullValue() const { return Value->isZero(); } | |||
1561 | bool isAllOnesValue() const { return Value->isMinusOne(); } | |||
1562 | ||||
1563 | bool isOpaque() const { return ConstantSDNodeBits.IsOpaque; } | |||
1564 | ||||
1565 | static bool classof(const SDNode *N) { | |||
1566 | return N->getOpcode() == ISD::Constant || | |||
1567 | N->getOpcode() == ISD::TargetConstant; | |||
1568 | } | |||
1569 | }; | |||
1570 | ||||
1571 | uint64_t SDNode::getConstantOperandVal(unsigned Num) const { | |||
1572 | return cast<ConstantSDNode>(getOperand(Num))->getZExtValue(); | |||
1573 | } | |||
1574 | ||||
1575 | const APInt &SDNode::getConstantOperandAPInt(unsigned Num) const { | |||
1576 | return cast<ConstantSDNode>(getOperand(Num))->getAPIntValue(); | |||
1577 | } | |||
1578 | ||||
1579 | class ConstantFPSDNode : public SDNode { | |||
1580 | friend class SelectionDAG; | |||
1581 | ||||
1582 | const ConstantFP *Value; | |||
1583 | ||||
1584 | ConstantFPSDNode(bool isTarget, const ConstantFP *val, EVT VT) | |||
1585 | : SDNode(isTarget ? ISD::TargetConstantFP : ISD::ConstantFP, 0, | |||
1586 | DebugLoc(), getSDVTList(VT)), | |||
1587 | Value(val) {} | |||
1588 | ||||
1589 | public: | |||
1590 | const APFloat& getValueAPF() const { return Value->getValueAPF(); } | |||
1591 | const ConstantFP *getConstantFPValue() const { return Value; } | |||
1592 | ||||
1593 | /// Return true if the value is positive or negative zero. | |||
1594 | bool isZero() const { return Value->isZero(); } | |||
1595 | ||||
1596 | /// Return true if the value is a NaN. | |||
1597 | bool isNaN() const { return Value->isNaN(); } | |||
1598 | ||||
1599 | /// Return true if the value is an infinity | |||
1600 | bool isInfinity() const { return Value->isInfinity(); } | |||
1601 | ||||
1602 | /// Return true if the value is negative. | |||
1603 | bool isNegative() const { return Value->isNegative(); } | |||
1604 | ||||
1605 | /// We don't rely on operator== working on double values, as | |||
1606 | /// it returns true for things that are clearly not equal, like -0.0 and 0.0. | |||
1607 | /// As such, this method can be used to do an exact bit-for-bit comparison of | |||
1608 | /// two floating point values. | |||
1609 | ||||
1610 | /// We leave the version with the double argument here because it's just so | |||
1611 | /// convenient to write "2.0" and the like. Without this function we'd | |||
1612 | /// have to duplicate its logic everywhere it's called. | |||
1613 | bool isExactlyValue(double V) const { | |||
1614 | return Value->getValueAPF().isExactlyValue(V); | |||
1615 | } | |||
1616 | bool isExactlyValue(const APFloat& V) const; | |||
1617 | ||||
1618 | static bool isValueValidForType(EVT VT, const APFloat& Val); | |||
1619 | ||||
1620 | static bool classof(const SDNode *N) { | |||
1621 | return N->getOpcode() == ISD::ConstantFP || | |||
1622 | N->getOpcode() == ISD::TargetConstantFP; | |||
1623 | } | |||
1624 | }; | |||
1625 | ||||
1626 | /// Returns true if \p V is a constant integer zero. | |||
1627 | bool isNullConstant(SDValue V); | |||
1628 | ||||
1629 | /// Returns true if \p V is an FP constant with a value of positive zero. | |||
1630 | bool isNullFPConstant(SDValue V); | |||
1631 | ||||
1632 | /// Returns true if \p V is an integer constant with all bits set. | |||
1633 | bool isAllOnesConstant(SDValue V); | |||
1634 | ||||
1635 | /// Returns true if \p V is a constant integer one. | |||
1636 | bool isOneConstant(SDValue V); | |||
1637 | ||||
1638 | /// Return the non-bitcasted source operand of \p V if it exists. | |||
1639 | /// If \p V is not a bitcasted value, it is returned as-is. | |||
1640 | SDValue peekThroughBitcasts(SDValue V); | |||
1641 | ||||
1642 | /// Return the non-bitcasted and one-use source operand of \p V if it exists. | |||
1643 | /// If \p V is not a bitcasted one-use value, it is returned as-is. | |||
1644 | SDValue peekThroughOneUseBitcasts(SDValue V); | |||
1645 | ||||
1646 | /// Return the non-extracted vector source operand of \p V if it exists. | |||
1647 | /// If \p V is not an extracted subvector, it is returned as-is. | |||
1648 | SDValue peekThroughExtractSubvectors(SDValue V); | |||
1649 | ||||
1650 | /// Returns true if \p V is a bitwise not operation. Assumes that an all ones | |||
1651 | /// constant is canonicalized to be operand 1. | |||
1652 | bool isBitwiseNot(SDValue V, bool AllowUndefs = false); | |||
1653 | ||||
1654 | /// Returns the SDNode if it is a constant splat BuildVector or constant int. | |||
1655 | ConstantSDNode *isConstOrConstSplat(SDValue N, bool AllowUndefs = false, | |||
1656 | bool AllowTruncation = false); | |||
1657 | ||||
1658 | /// Returns the SDNode if it is a demanded constant splat BuildVector or | |||
1659 | /// constant int. | |||
1660 | ConstantSDNode *isConstOrConstSplat(SDValue N, const APInt &DemandedElts, | |||
1661 | bool AllowUndefs = false, | |||
1662 | bool AllowTruncation = false); | |||
1663 | ||||
1664 | /// Returns the SDNode if it is a constant splat BuildVector or constant float. | |||
1665 | ConstantFPSDNode *isConstOrConstSplatFP(SDValue N, bool AllowUndefs = false); | |||
1666 | ||||
1667 | /// Returns the SDNode if it is a demanded constant splat BuildVector or | |||
1668 | /// constant float. | |||
1669 | ConstantFPSDNode *isConstOrConstSplatFP(SDValue N, const APInt &DemandedElts, | |||
1670 | bool AllowUndefs = false); | |||
1671 | ||||
1672 | /// Return true if the value is a constant 0 integer or a splatted vector of | |||
1673 | /// a constant 0 integer (with no undefs by default). | |||
1674 | /// Build vector implicit truncation is not an issue for null values. | |||
1675 | bool isNullOrNullSplat(SDValue V, bool AllowUndefs = false); | |||
1676 | ||||
1677 | /// Return true if the value is a constant 1 integer or a splatted vector of a | |||
1678 | /// constant 1 integer (with no undefs). | |||
1679 | /// Does not permit build vector implicit truncation. | |||
1680 | bool isOneOrOneSplat(SDValue V, bool AllowUndefs = false); | |||
1681 | ||||
1682 | /// Return true if the value is a constant -1 integer or a splatted vector of a | |||
1683 | /// constant -1 integer (with no undefs). | |||
1684 | /// Does not permit build vector implicit truncation. | |||
1685 | bool isAllOnesOrAllOnesSplat(SDValue V, bool AllowUndefs = false); | |||
1686 | ||||
1687 | /// Return true if \p V is either a integer or FP constant. | |||
1688 | inline bool isIntOrFPConstant(SDValue V) { | |||
1689 | return isa<ConstantSDNode>(V) || isa<ConstantFPSDNode>(V); | |||
1690 | } | |||
1691 | ||||
1692 | class GlobalAddressSDNode : public SDNode { | |||
1693 | friend class SelectionDAG; | |||
1694 | ||||
1695 | const GlobalValue *TheGlobal; | |||
1696 | int64_t Offset; | |||
1697 | unsigned TargetFlags; | |||
1698 | ||||
1699 | GlobalAddressSDNode(unsigned Opc, unsigned Order, const DebugLoc &DL, | |||
1700 | const GlobalValue *GA, EVT VT, int64_t o, | |||
1701 | unsigned TF); | |||
1702 | ||||
1703 | public: | |||
1704 | const GlobalValue *getGlobal() const { return TheGlobal; } | |||
1705 | int64_t getOffset() const { return Offset; } | |||
1706 | unsigned getTargetFlags() const { return TargetFlags; } | |||
1707 | // Return the address space this GlobalAddress belongs to. | |||
1708 | unsigned getAddressSpace() const; | |||
1709 | ||||
1710 | static bool classof(const SDNode *N) { | |||
1711 | return N->getOpcode() == ISD::GlobalAddress || | |||
1712 | N->getOpcode() == ISD::TargetGlobalAddress || | |||
1713 | N->getOpcode() == ISD::GlobalTLSAddress || | |||
1714 | N->getOpcode() == ISD::TargetGlobalTLSAddress; | |||
1715 | } | |||
1716 | }; | |||
1717 | ||||
1718 | class FrameIndexSDNode : public SDNode { | |||
1719 | friend class SelectionDAG; | |||
1720 | ||||
1721 | int FI; | |||
1722 | ||||
1723 | FrameIndexSDNode(int fi, EVT VT, bool isTarg) | |||
1724 | : SDNode(isTarg ? ISD::TargetFrameIndex : ISD::FrameIndex, | |||
1725 | 0, DebugLoc(), getSDVTList(VT)), FI(fi) { | |||
1726 | } | |||
1727 | ||||
1728 | public: | |||
1729 | int getIndex() const { return FI; } | |||
1730 | ||||
1731 | static bool classof(const SDNode *N) { | |||
1732 | return N->getOpcode() == ISD::FrameIndex || | |||
1733 | N->getOpcode() == ISD::TargetFrameIndex; | |||
1734 | } | |||
1735 | }; | |||
1736 | ||||
1737 | /// This SDNode is used for LIFETIME_START/LIFETIME_END values, which indicate | |||
1738 | /// the offet and size that are started/ended in the underlying FrameIndex. | |||
1739 | class LifetimeSDNode : public SDNode { | |||
1740 | friend class SelectionDAG; | |||
1741 | int64_t Size; | |||
1742 | int64_t Offset; // -1 if offset is unknown. | |||
1743 | ||||
1744 | LifetimeSDNode(unsigned Opcode, unsigned Order, const DebugLoc &dl, | |||
1745 | SDVTList VTs, int64_t Size, int64_t Offset) | |||
1746 | : SDNode(Opcode, Order, dl, VTs), Size(Size), Offset(Offset) {} | |||
1747 | public: | |||
1748 | int64_t getFrameIndex() const { | |||
1749 | return cast<FrameIndexSDNode>(getOperand(1))->getIndex(); | |||
1750 | } | |||
1751 | ||||
1752 | bool hasOffset() const { return Offset >= 0; } | |||
1753 | int64_t getOffset() const { | |||
1754 | assert(hasOffset() && "offset is unknown")((hasOffset() && "offset is unknown") ? static_cast< void> (0) : __assert_fail ("hasOffset() && \"offset is unknown\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/CodeGen/SelectionDAGNodes.h" , 1754, __PRETTY_FUNCTION__)); | |||
1755 | return Offset; | |||
1756 | } | |||
1757 | int64_t getSize() const { | |||
1758 | assert(hasOffset() && "offset is unknown")((hasOffset() && "offset is unknown") ? static_cast< void> (0) : __assert_fail ("hasOffset() && \"offset is unknown\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/CodeGen/SelectionDAGNodes.h" , 1758, __PRETTY_FUNCTION__)); | |||
1759 | return Size; | |||
1760 | } | |||
1761 | ||||
1762 | // Methods to support isa and dyn_cast | |||
1763 | static bool classof(const SDNode *N) { | |||
1764 | return N->getOpcode() == ISD::LIFETIME_START || | |||
1765 | N->getOpcode() == ISD::LIFETIME_END; | |||
1766 | } | |||
1767 | }; | |||
1768 | ||||
1769 | /// This SDNode is used for PSEUDO_PROBE values, which are the function guid and | |||
1770 | /// the index of the basic block being probed. A pseudo probe serves as a place | |||
1771 | /// holder and will be removed at the end of compilation. It does not have any | |||
1772 | /// operand because we do not want the instruction selection to deal with any. | |||
1773 | class PseudoProbeSDNode : public SDNode { | |||
1774 | friend class SelectionDAG; | |||
1775 | uint64_t Guid; | |||
1776 | uint64_t Index; | |||
1777 | uint32_t Attributes; | |||
1778 | ||||
1779 | PseudoProbeSDNode(unsigned Opcode, unsigned Order, const DebugLoc &Dl, | |||
1780 | SDVTList VTs, uint64_t Guid, uint64_t Index, uint32_t Attr) | |||
1781 | : SDNode(Opcode, Order, Dl, VTs), Guid(Guid), Index(Index), | |||
1782 | Attributes(Attr) {} | |||
1783 | ||||
1784 | public: | |||
1785 | uint64_t getGuid() const { return Guid; } | |||
1786 | uint64_t getIndex() const { return Index; } | |||
1787 | uint32_t getAttributes() const { return Attributes; } | |||
1788 | ||||
1789 | // Methods to support isa and dyn_cast | |||
1790 | static bool classof(const SDNode *N) { | |||
1791 | return N->getOpcode() == ISD::PSEUDO_PROBE; | |||
1792 | } | |||
1793 | }; | |||
1794 | ||||
1795 | class JumpTableSDNode : public SDNode { | |||
1796 | friend class SelectionDAG; | |||
1797 | ||||
1798 | int JTI; | |||
1799 | unsigned TargetFlags; | |||
1800 | ||||
1801 | JumpTableSDNode(int jti, EVT VT, bool isTarg, unsigned TF) | |||
1802 | : SDNode(isTarg ? ISD::TargetJumpTable : ISD::JumpTable, | |||
1803 | 0, DebugLoc(), getSDVTList(VT)), JTI(jti), TargetFlags(TF) { | |||
1804 | } | |||
1805 | ||||
1806 | public: | |||
1807 | int getIndex() const { return JTI; } | |||
1808 | unsigned getTargetFlags() const { return TargetFlags; } | |||
1809 | ||||
1810 | static bool classof(const SDNode *N) { | |||
1811 | return N->getOpcode() == ISD::JumpTable || | |||
1812 | N->getOpcode() == ISD::TargetJumpTable; | |||
1813 | } | |||
1814 | }; | |||
1815 | ||||
1816 | class ConstantPoolSDNode : public SDNode { | |||
1817 | friend class SelectionDAG; | |||
1818 | ||||
1819 | union { | |||
1820 | const Constant *ConstVal; | |||
1821 | MachineConstantPoolValue *MachineCPVal; | |||
1822 | } Val; | |||
1823 | int Offset; // It's a MachineConstantPoolValue if top bit is set. | |||
1824 | Align Alignment; // Minimum alignment requirement of CP. | |||
1825 | unsigned TargetFlags; | |||
1826 | ||||
1827 | ConstantPoolSDNode(bool isTarget, const Constant *c, EVT VT, int o, | |||
1828 | Align Alignment, unsigned TF) | |||
1829 | : SDNode(isTarget ? ISD::TargetConstantPool : ISD::ConstantPool, 0, | |||
1830 | DebugLoc(), getSDVTList(VT)), | |||
1831 | Offset(o), Alignment(Alignment), TargetFlags(TF) { | |||
1832 | assert(Offset >= 0 && "Offset is too large")((Offset >= 0 && "Offset is too large") ? static_cast <void> (0) : __assert_fail ("Offset >= 0 && \"Offset is too large\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/CodeGen/SelectionDAGNodes.h" , 1832, __PRETTY_FUNCTION__)); | |||
1833 | Val.ConstVal = c; | |||
1834 | } | |||
1835 | ||||
1836 | ConstantPoolSDNode(bool isTarget, MachineConstantPoolValue *v, EVT VT, int o, | |||
1837 | Align Alignment, unsigned TF) | |||
1838 | : SDNode(isTarget ? ISD::TargetConstantPool : ISD::ConstantPool, 0, | |||
1839 | DebugLoc(), getSDVTList(VT)), | |||
1840 | Offset(o), Alignment(Alignment), TargetFlags(TF) { | |||
1841 | assert(Offset >= 0 && "Offset is too large")((Offset >= 0 && "Offset is too large") ? static_cast <void> (0) : __assert_fail ("Offset >= 0 && \"Offset is too large\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/CodeGen/SelectionDAGNodes.h" , 1841, __PRETTY_FUNCTION__)); | |||
1842 | Val.MachineCPVal = v; | |||
1843 | Offset |= 1 << (sizeof(unsigned)*CHAR_BIT8-1); | |||
1844 | } | |||
1845 | ||||
1846 | public: | |||
1847 | bool isMachineConstantPoolEntry() const { | |||
1848 | return Offset < 0; | |||
1849 | } | |||
1850 | ||||
1851 | const Constant *getConstVal() const { | |||
1852 | assert(!isMachineConstantPoolEntry() && "Wrong constantpool type")((!isMachineConstantPoolEntry() && "Wrong constantpool type" ) ? static_cast<void> (0) : __assert_fail ("!isMachineConstantPoolEntry() && \"Wrong constantpool type\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/CodeGen/SelectionDAGNodes.h" , 1852, __PRETTY_FUNCTION__)); | |||
1853 | return Val.ConstVal; | |||
1854 | } | |||
1855 | ||||
1856 | MachineConstantPoolValue *getMachineCPVal() const { | |||
1857 | assert(isMachineConstantPoolEntry() && "Wrong constantpool type")((isMachineConstantPoolEntry() && "Wrong constantpool type" ) ? static_cast<void> (0) : __assert_fail ("isMachineConstantPoolEntry() && \"Wrong constantpool type\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/CodeGen/SelectionDAGNodes.h" , 1857, __PRETTY_FUNCTION__)); | |||
1858 | return Val.MachineCPVal; | |||
1859 | } | |||
1860 | ||||
1861 | int getOffset() const { | |||
1862 | return Offset & ~(1 << (sizeof(unsigned)*CHAR_BIT8-1)); | |||
1863 | } | |||
1864 | ||||
1865 | // Return the alignment of this constant pool object, which is either 0 (for | |||
1866 | // default alignment) or the desired value. | |||
1867 | Align getAlign() const { return Alignment; } | |||
1868 | unsigned getTargetFlags() const { return TargetFlags; } | |||
1869 | ||||
1870 | Type *getType() const; | |||
1871 | ||||
1872 | static bool classof(const SDNode *N) { | |||
1873 | return N->getOpcode() == ISD::ConstantPool || | |||
1874 | N->getOpcode() == ISD::TargetConstantPool; | |||
1875 | } | |||
1876 | }; | |||
1877 | ||||
1878 | /// Completely target-dependent object reference. | |||
1879 | class TargetIndexSDNode : public SDNode { | |||
1880 | friend class SelectionDAG; | |||
1881 | ||||
1882 | unsigned TargetFlags; | |||
1883 | int Index; | |||
1884 | int64_t Offset; | |||
1885 | ||||
1886 | public: | |||
1887 | TargetIndexSDNode(int Idx, EVT VT, int64_t Ofs, unsigned TF) | |||
1888 | : SDNode(ISD::TargetIndex, 0, DebugLoc(), getSDVTList(VT)), | |||
1889 | TargetFlags(TF), Index(Idx), Offset(Ofs) {} | |||
1890 | ||||
1891 | unsigned getTargetFlags() const { return TargetFlags; } | |||
1892 | int getIndex() const { return Index; } | |||
1893 | int64_t getOffset() const { return Offset; } | |||
1894 | ||||
1895 | static bool classof(const SDNode *N) { | |||
1896 | return N->getOpcode() == ISD::TargetIndex; | |||
1897 | } | |||
1898 | }; | |||
1899 | ||||
1900 | class BasicBlockSDNode : public SDNode { | |||
1901 | friend class SelectionDAG; | |||
1902 | ||||
1903 | MachineBasicBlock *MBB; | |||
1904 | ||||
1905 | /// Debug info is meaningful and potentially useful here, but we create | |||
1906 | /// blocks out of order when they're jumped to, which makes it a bit | |||
1907 | /// harder. Let's see if we need it first. | |||
1908 | explicit BasicBlockSDNode(MachineBasicBlock *mbb) | |||
1909 | : SDNode(ISD::BasicBlock, 0, DebugLoc(), getSDVTList(MVT::Other)), MBB(mbb) | |||
1910 | {} | |||
1911 | ||||
1912 | public: | |||
1913 | MachineBasicBlock *getBasicBlock() const { return MBB; } | |||
1914 | ||||
1915 | static bool classof(const SDNode *N) { | |||
1916 | return N->getOpcode() == ISD::BasicBlock; | |||
1917 | } | |||
1918 | }; | |||
1919 | ||||
1920 | /// A "pseudo-class" with methods for operating on BUILD_VECTORs. | |||
1921 | class BuildVectorSDNode : public SDNode { | |||
1922 | public: | |||
1923 | // These are constructed as SDNodes and then cast to BuildVectorSDNodes. | |||
1924 | explicit BuildVectorSDNode() = delete; | |||
1925 | ||||
1926 | /// Check if this is a constant splat, and if so, find the | |||
1927 | /// smallest element size that splats the vector. If MinSplatBits is | |||
1928 | /// nonzero, the element size must be at least that large. Note that the | |||
1929 | /// splat element may be the entire vector (i.e., a one element vector). | |||
1930 | /// Returns the splat element value in SplatValue. Any undefined bits in | |||
1931 | /// that value are zero, and the corresponding bits in the SplatUndef mask | |||
1932 | /// are set. The SplatBitSize value is set to the splat element size in | |||
1933 | /// bits. HasAnyUndefs is set to true if any bits in the vector are | |||
1934 | /// undefined. isBigEndian describes the endianness of the target. | |||
1935 | bool isConstantSplat(APInt &SplatValue, APInt &SplatUndef, | |||
1936 | unsigned &SplatBitSize, bool &HasAnyUndefs, | |||
1937 | unsigned MinSplatBits = 0, | |||
1938 | bool isBigEndian = false) const; | |||
1939 | ||||
1940 | /// Returns the demanded splatted value or a null value if this is not a | |||
1941 | /// splat. | |||
1942 | /// | |||
1943 | /// The DemandedElts mask indicates the elements that must be in the splat. | |||
1944 | /// If passed a non-null UndefElements bitvector, it will resize it to match | |||
1945 | /// the vector width and set the bits where elements are undef. | |||
1946 | SDValue getSplatValue(const APInt &DemandedElts, | |||
1947 | BitVector *UndefElements = nullptr) const; | |||
1948 | ||||
1949 | /// Returns the splatted value or a null value if this is not a splat. | |||
1950 | /// | |||
1951 | /// If passed a non-null UndefElements bitvector, it will resize it to match | |||
1952 | /// the vector width and set the bits where elements are undef. | |||
1953 | SDValue getSplatValue(BitVector *UndefElements = nullptr) const; | |||
1954 | ||||
1955 | /// Find the shortest repeating sequence of values in the build vector. | |||
1956 | /// | |||
1957 | /// e.g. { u, X, u, X, u, u, X, u } -> { X } | |||
1958 | /// { X, Y, u, Y, u, u, X, u } -> { X, Y } | |||
1959 | /// | |||
1960 | /// Currently this must be a power-of-2 build vector. | |||
1961 | /// The DemandedElts mask indicates the elements that must be present, | |||
1962 | /// undemanded elements in Sequence may be null (SDValue()). If passed a | |||
1963 | /// non-null UndefElements bitvector, it will resize it to match the original | |||
1964 | /// vector width and set the bits where elements are undef. If result is | |||
1965 | /// false, Sequence will be empty. | |||
1966 | bool getRepeatedSequence(const APInt &DemandedElts, | |||
1967 | SmallVectorImpl<SDValue> &Sequence, | |||
1968 | BitVector *UndefElements = nullptr) const; | |||
1969 | ||||
1970 | /// Find the shortest repeating sequence of values in the build vector. | |||
1971 | /// | |||
1972 | /// e.g. { u, X, u, X, u, u, X, u } -> { X } | |||
1973 | /// { X, Y, u, Y, u, u, X, u } -> { X, Y } | |||
1974 | /// | |||
1975 | /// Currently this must be a power-of-2 build vector. | |||
1976 | /// If passed a non-null UndefElements bitvector, it will resize it to match | |||
1977 | /// the original vector width and set the bits where elements are undef. | |||
1978 | /// If result is false, Sequence will be empty. | |||
1979 | bool getRepeatedSequence(SmallVectorImpl<SDValue> &Sequence, | |||
1980 | BitVector *UndefElements = nullptr) const; | |||
1981 | ||||
1982 | /// Returns the demanded splatted constant or null if this is not a constant | |||
1983 | /// splat. | |||
1984 | /// | |||
1985 | /// The DemandedElts mask indicates the elements that must be in the splat. | |||
1986 | /// If passed a non-null UndefElements bitvector, it will resize it to match | |||
1987 | /// the vector width and set the bits where elements are undef. | |||
1988 | ConstantSDNode * | |||
1989 | getConstantSplatNode(const APInt &DemandedElts, | |||
1990 | BitVector *UndefElements = nullptr) const; | |||
1991 | ||||
1992 | /// Returns the splatted constant or null if this is not a constant | |||
1993 | /// splat. | |||
1994 | /// | |||
1995 | /// If passed a non-null UndefElements bitvector, it will resize it to match | |||
1996 | /// the vector width and set the bits where elements are undef. | |||
1997 | ConstantSDNode * | |||
1998 | getConstantSplatNode(BitVector *UndefElements = nullptr) const; | |||
1999 | ||||
2000 | /// Returns the demanded splatted constant FP or null if this is not a | |||
2001 | /// constant FP splat. | |||
2002 | /// | |||
2003 | /// The DemandedElts mask indicates the elements that must be in the splat. | |||
2004 | /// If passed a non-null UndefElements bitvector, it will resize it to match | |||
2005 | /// the vector width and set the bits where elements are undef. | |||
2006 | ConstantFPSDNode * | |||
2007 | getConstantFPSplatNode(const APInt &DemandedElts, | |||
2008 | BitVector *UndefElements = nullptr) const; | |||
2009 | ||||
2010 | /// Returns the splatted constant FP or null if this is not a constant | |||
2011 | /// FP splat. | |||
2012 | /// | |||
2013 | /// If passed a non-null UndefElements bitvector, it will resize it to match | |||
2014 | /// the vector width and set the bits where elements are undef. | |||
2015 | ConstantFPSDNode * | |||
2016 | getConstantFPSplatNode(BitVector *UndefElements = nullptr) const; | |||
2017 | ||||
2018 | /// If this is a constant FP splat and the splatted constant FP is an | |||
2019 | /// exact power or 2, return the log base 2 integer value. Otherwise, | |||
2020 | /// return -1. | |||
2021 | /// | |||
2022 | /// The BitWidth specifies the necessary bit precision. | |||
2023 | int32_t getConstantFPSplatPow2ToLog2Int(BitVector *UndefElements, | |||
2024 | uint32_t BitWidth) const; | |||
2025 | ||||
2026 | bool isConstant() const; | |||
2027 | ||||
2028 | static bool classof(const SDNode *N) { | |||
2029 | return N->getOpcode() == ISD::BUILD_VECTOR; | |||
2030 | } | |||
2031 | }; | |||
2032 | ||||
2033 | /// An SDNode that holds an arbitrary LLVM IR Value. This is | |||
2034 | /// used when the SelectionDAG needs to make a simple reference to something | |||
2035 | /// in the LLVM IR representation. | |||
2036 | /// | |||
2037 | class SrcValueSDNode : public SDNode { | |||
2038 | friend class SelectionDAG; | |||
2039 | ||||
2040 | const Value *V; | |||
2041 | ||||
2042 | /// Create a SrcValue for a general value. | |||
2043 | explicit SrcValueSDNode(const Value *v) | |||
2044 | : SDNode(ISD::SRCVALUE, 0, DebugLoc(), getSDVTList(MVT::Other)), V(v) {} | |||
2045 | ||||
2046 | public: | |||
2047 | /// Return the contained Value. | |||
2048 | const Value *getValue() const { return V; } | |||
2049 | ||||
2050 | static bool classof(const SDNode *N) { | |||
2051 | return N->getOpcode() == ISD::SRCVALUE; | |||
2052 | } | |||
2053 | }; | |||
2054 | ||||
2055 | class MDNodeSDNode : public SDNode { | |||
2056 | friend class SelectionDAG; | |||
2057 | ||||
2058 | const MDNode *MD; | |||
2059 | ||||
2060 | explicit MDNodeSDNode(const MDNode *md) | |||
2061 | : SDNode(ISD::MDNODE_SDNODE, 0, DebugLoc(), getSDVTList(MVT::Other)), MD(md) | |||
2062 | {} | |||
2063 | ||||
2064 | public: | |||
2065 | const MDNode *getMD() const { return MD; } | |||
2066 | ||||
2067 | static bool classof(const SDNode *N) { | |||
2068 | return N->getOpcode() == ISD::MDNODE_SDNODE; | |||
2069 | } | |||
2070 | }; | |||
2071 | ||||
2072 | class RegisterSDNode : public SDNode { | |||
2073 | friend class SelectionDAG; | |||
2074 | ||||
2075 | Register Reg; | |||
2076 | ||||
2077 | RegisterSDNode(Register reg, EVT VT) | |||
2078 | : SDNode(ISD::Register, 0, DebugLoc(), getSDVTList(VT)), Reg(reg) {} | |||
2079 | ||||
2080 | public: | |||
2081 | Register getReg() const { return Reg; } | |||
2082 | ||||
2083 | static bool classof(const SDNode *N) { | |||
2084 | return N->getOpcode() == ISD::Register; | |||
2085 | } | |||
2086 | }; | |||
2087 | ||||
2088 | class RegisterMaskSDNode : public SDNode { | |||
2089 | friend class SelectionDAG; | |||
2090 | ||||
2091 | // The memory for RegMask is not owned by the node. | |||
2092 | const uint32_t *RegMask; | |||
2093 | ||||
2094 | RegisterMaskSDNode(const uint32_t *mask) | |||
2095 | : SDNode(ISD::RegisterMask, 0, DebugLoc(), getSDVTList(MVT::Untyped)), | |||
2096 | RegMask(mask) {} | |||
2097 | ||||
2098 | public: | |||
2099 | const uint32_t *getRegMask() const { return RegMask; } | |||
2100 | ||||
2101 | static bool classof(const SDNode *N) { | |||
2102 | return N->getOpcode() == ISD::RegisterMask; | |||
2103 | } | |||
2104 | }; | |||
2105 | ||||
2106 | class BlockAddressSDNode : public SDNode { | |||
2107 | friend class SelectionDAG; | |||
2108 | ||||
2109 | const BlockAddress *BA; | |||
2110 | int64_t Offset; | |||
2111 | unsigned TargetFlags; | |||
2112 | ||||
2113 | BlockAddressSDNode(unsigned NodeTy, EVT VT, const BlockAddress *ba, | |||
2114 | int64_t o, unsigned Flags) | |||
2115 | : SDNode(NodeTy, 0, DebugLoc(), getSDVTList(VT)), | |||
2116 | BA(ba), Offset(o), TargetFlags(Flags) {} | |||
2117 | ||||
2118 | public: | |||
2119 | const BlockAddress *getBlockAddress() const { return BA; } | |||
2120 | int64_t getOffset() const { return Offset; } | |||
2121 | unsigned getTargetFlags() const { return TargetFlags; } | |||
2122 | ||||
2123 | static bool classof(const SDNode *N) { | |||
2124 | return N->getOpcode() == ISD::BlockAddress || | |||
2125 | N->getOpcode() == ISD::TargetBlockAddress; | |||
2126 | } | |||
2127 | }; | |||
2128 | ||||
2129 | class LabelSDNode : public SDNode { | |||
2130 | friend class SelectionDAG; | |||
2131 | ||||
2132 | MCSymbol *Label; | |||
2133 | ||||
2134 | LabelSDNode(unsigned Opcode, unsigned Order, const DebugLoc &dl, MCSymbol *L) | |||
2135 | : SDNode(Opcode, Order, dl, getSDVTList(MVT::Other)), Label(L) { | |||
2136 | assert(LabelSDNode::classof(this) && "not a label opcode")((LabelSDNode::classof(this) && "not a label opcode") ? static_cast<void> (0) : __assert_fail ("LabelSDNode::classof(this) && \"not a label opcode\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/CodeGen/SelectionDAGNodes.h" , 2136, __PRETTY_FUNCTION__)); | |||
2137 | } | |||
2138 | ||||
2139 | public: | |||
2140 | MCSymbol *getLabel() const { return Label; } | |||
2141 | ||||
2142 | static bool classof(const SDNode *N) { | |||
2143 | return N->getOpcode() == ISD::EH_LABEL || | |||
2144 | N->getOpcode() == ISD::ANNOTATION_LABEL; | |||
2145 | } | |||
2146 | }; | |||
2147 | ||||
2148 | class ExternalSymbolSDNode : public SDNode { | |||
2149 | friend class SelectionDAG; | |||
2150 | ||||
2151 | const char *Symbol; | |||
2152 | unsigned TargetFlags; | |||
2153 | ||||
2154 | ExternalSymbolSDNode(bool isTarget, const char *Sym, unsigned TF, EVT VT) | |||
2155 | : SDNode(isTarget ? ISD::TargetExternalSymbol : ISD::ExternalSymbol, 0, | |||
2156 | DebugLoc(), getSDVTList(VT)), | |||
2157 | Symbol(Sym), TargetFlags(TF) {} | |||
2158 | ||||
2159 | public: | |||
2160 | const char *getSymbol() const { return Symbol; } | |||
2161 | unsigned getTargetFlags() const { return TargetFlags; } | |||
2162 | ||||
2163 | static bool classof(const SDNode *N) { | |||
2164 | return N->getOpcode() == ISD::ExternalSymbol || | |||
2165 | N->getOpcode() == ISD::TargetExternalSymbol; | |||
2166 | } | |||
2167 | }; | |||
2168 | ||||
2169 | class MCSymbolSDNode : public SDNode { | |||
2170 | friend class SelectionDAG; | |||
2171 | ||||
2172 | MCSymbol *Symbol; | |||
2173 | ||||
2174 | MCSymbolSDNode(MCSymbol *Symbol, EVT VT) | |||
2175 | : SDNode(ISD::MCSymbol, 0, DebugLoc(), getSDVTList(VT)), Symbol(Symbol) {} | |||
2176 | ||||
2177 | public: | |||
2178 | MCSymbol *getMCSymbol() const { return Symbol; } | |||
2179 | ||||
2180 | static bool classof(const SDNode *N) { | |||
2181 | return N->getOpcode() == ISD::MCSymbol; | |||
2182 | } | |||
2183 | }; | |||
2184 | ||||
2185 | class CondCodeSDNode : public SDNode { | |||
2186 | friend class SelectionDAG; | |||
2187 | ||||
2188 | ISD::CondCode Condition; | |||
2189 | ||||
2190 | explicit CondCodeSDNode(ISD::CondCode Cond) | |||
2191 | : SDNode(ISD::CONDCODE, 0, DebugLoc(), getSDVTList(MVT::Other)), | |||
2192 | Condition(Cond) {} | |||
2193 | ||||
2194 | public: | |||
2195 | ISD::CondCode get() const { return Condition; } | |||
2196 | ||||
2197 | static bool classof(const SDNode *N) { | |||
2198 | return N->getOpcode() == ISD::CONDCODE; | |||
2199 | } | |||
2200 | }; | |||
2201 | ||||
2202 | /// This class is used to represent EVT's, which are used | |||
2203 | /// to parameterize some operations. | |||
2204 | class VTSDNode : public SDNode { | |||
2205 | friend class SelectionDAG; | |||
2206 | ||||
2207 | EVT ValueType; | |||
2208 | ||||
2209 | explicit VTSDNode(EVT VT) | |||
2210 | : SDNode(ISD::VALUETYPE, 0, DebugLoc(), getSDVTList(MVT::Other)), | |||
2211 | ValueType(VT) {} | |||
2212 | ||||
2213 | public: | |||
2214 | EVT getVT() const { return ValueType; } | |||
2215 | ||||
2216 | static bool classof(const SDNode *N) { | |||
2217 | return N->getOpcode() == ISD::VALUETYPE; | |||
2218 | } | |||
2219 | }; | |||
2220 | ||||
2221 | /// Base class for LoadSDNode and StoreSDNode | |||
2222 | class LSBaseSDNode : public MemSDNode { | |||
2223 | public: | |||
2224 | LSBaseSDNode(ISD::NodeType NodeTy, unsigned Order, const DebugLoc &dl, | |||
2225 | SDVTList VTs, ISD::MemIndexedMode AM, EVT MemVT, | |||
2226 | MachineMemOperand *MMO) | |||
2227 | : MemSDNode(NodeTy, Order, dl, VTs, MemVT, MMO) { | |||
2228 | LSBaseSDNodeBits.AddressingMode = AM; | |||
2229 | assert(getAddressingMode() == AM && "Value truncated")((getAddressingMode() == AM && "Value truncated") ? static_cast <void> (0) : __assert_fail ("getAddressingMode() == AM && \"Value truncated\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/CodeGen/SelectionDAGNodes.h" , 2229, __PRETTY_FUNCTION__)); | |||
2230 | } | |||
2231 | ||||
2232 | const SDValue &getOffset() const { | |||
2233 | return getOperand(getOpcode() == ISD::LOAD ? 2 : 3); | |||
2234 | } | |||
2235 | ||||
2236 | /// Return the addressing mode for this load or store: | |||
2237 | /// unindexed, pre-inc, pre-dec, post-inc, or post-dec. | |||
2238 | ISD::MemIndexedMode getAddressingMode() const { | |||
2239 | return static_cast<ISD::MemIndexedMode>(LSBaseSDNodeBits.AddressingMode); | |||
2240 | } | |||
2241 | ||||
2242 | /// Return true if this is a pre/post inc/dec load/store. | |||
2243 | bool isIndexed() const { return getAddressingMode() != ISD::UNINDEXED; } | |||
2244 | ||||
2245 | /// Return true if this is NOT a pre/post inc/dec load/store. | |||
2246 | bool isUnindexed() const { return getAddressingMode() == ISD::UNINDEXED; } | |||
2247 | ||||
2248 | static bool classof(const SDNode *N) { | |||
2249 | return N->getOpcode() == ISD::LOAD || | |||
2250 | N->getOpcode() == ISD::STORE; | |||
2251 | } | |||
2252 | }; | |||
2253 | ||||
2254 | /// This class is used to represent ISD::LOAD nodes. | |||
2255 | class LoadSDNode : public LSBaseSDNode { | |||
2256 | friend class SelectionDAG; | |||
2257 | ||||
2258 | LoadSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs, | |||
2259 | ISD::MemIndexedMode AM, ISD::LoadExtType ETy, EVT MemVT, | |||
2260 | MachineMemOperand *MMO) | |||
2261 | : LSBaseSDNode(ISD::LOAD, Order, dl, VTs, AM, MemVT, MMO) { | |||
2262 | LoadSDNodeBits.ExtTy = ETy; | |||
2263 | assert(readMem() && "Load MachineMemOperand is not a load!")((readMem() && "Load MachineMemOperand is not a load!" ) ? static_cast<void> (0) : __assert_fail ("readMem() && \"Load MachineMemOperand is not a load!\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/CodeGen/SelectionDAGNodes.h" , 2263, __PRETTY_FUNCTION__)); | |||
2264 | assert(!writeMem() && "Load MachineMemOperand is a store!")((!writeMem() && "Load MachineMemOperand is a store!" ) ? static_cast<void> (0) : __assert_fail ("!writeMem() && \"Load MachineMemOperand is a store!\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/CodeGen/SelectionDAGNodes.h" , 2264, __PRETTY_FUNCTION__)); | |||
2265 | } | |||
2266 | ||||
2267 | public: | |||
2268 | /// Return whether this is a plain node, | |||
2269 | /// or one of the varieties of value-extending loads. | |||
2270 | ISD::LoadExtType getExtensionType() const { | |||
2271 | return static_cast<ISD::LoadExtType>(LoadSDNodeBits.ExtTy); | |||
2272 | } | |||
2273 | ||||
2274 | const SDValue &getBasePtr() const { return getOperand(1); } | |||
2275 | const SDValue &getOffset() const { return getOperand(2); } | |||
2276 | ||||
2277 | static bool classof(const SDNode *N) { | |||
2278 | return N->getOpcode() == ISD::LOAD; | |||
2279 | } | |||
2280 | }; | |||
2281 | ||||
2282 | /// This class is used to represent ISD::STORE nodes. | |||
2283 | class StoreSDNode : public LSBaseSDNode { | |||
2284 | friend class SelectionDAG; | |||
2285 | ||||
2286 | StoreSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs, | |||
2287 | ISD::MemIndexedMode AM, bool isTrunc, EVT MemVT, | |||
2288 | MachineMemOperand *MMO) | |||
2289 | : LSBaseSDNode(ISD::STORE, Order, dl, VTs, AM, MemVT, MMO) { | |||
2290 | StoreSDNodeBits.IsTruncating = isTrunc; | |||
2291 | assert(!readMem() && "Store MachineMemOperand is a load!")((!readMem() && "Store MachineMemOperand is a load!") ? static_cast<void> (0) : __assert_fail ("!readMem() && \"Store MachineMemOperand is a load!\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/CodeGen/SelectionDAGNodes.h" , 2291, __PRETTY_FUNCTION__)); | |||
2292 | assert(writeMem() && "Store MachineMemOperand is not a store!")((writeMem() && "Store MachineMemOperand is not a store!" ) ? static_cast<void> (0) : __assert_fail ("writeMem() && \"Store MachineMemOperand is not a store!\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/CodeGen/SelectionDAGNodes.h" , 2292, __PRETTY_FUNCTION__)); | |||
2293 | } | |||
2294 | ||||
2295 | public: | |||
2296 | /// Return true if the op does a truncation before store. | |||
2297 | /// For integers this is the same as doing a TRUNCATE and storing the result. | |||
2298 | /// For floats, it is the same as doing an FP_ROUND and storing the result. | |||
2299 | bool isTruncatingStore() const { return StoreSDNodeBits.IsTruncating; } | |||
2300 | void setTruncatingStore(bool Truncating) { | |||
2301 | StoreSDNodeBits.IsTruncating = Truncating; | |||
2302 | } | |||
2303 | ||||
2304 | const SDValue &getValue() const { return getOperand(1); } | |||
2305 | const SDValue &getBasePtr() const { return getOperand(2); } | |||
2306 | const SDValue &getOffset() const { return getOperand(3); } | |||
2307 | ||||
2308 | static bool classof(const SDNode *N) { | |||
2309 | return N->getOpcode() == ISD::STORE; | |||
2310 | } | |||
2311 | }; | |||
2312 | ||||
2313 | /// This base class is used to represent MLOAD and MSTORE nodes | |||
2314 | class MaskedLoadStoreSDNode : public MemSDNode { | |||
2315 | public: | |||
2316 | friend class SelectionDAG; | |||
2317 | ||||
2318 | MaskedLoadStoreSDNode(ISD::NodeType NodeTy, unsigned Order, | |||
2319 | const DebugLoc &dl, SDVTList VTs, | |||
2320 | ISD::MemIndexedMode AM, EVT MemVT, | |||
2321 | MachineMemOperand *MMO) | |||
2322 | : MemSDNode(NodeTy, Order, dl, VTs, MemVT, MMO) { | |||
2323 | LSBaseSDNodeBits.AddressingMode = AM; | |||
2324 | assert(getAddressingMode() == AM && "Value truncated")((getAddressingMode() == AM && "Value truncated") ? static_cast <void> (0) : __assert_fail ("getAddressingMode() == AM && \"Value truncated\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/CodeGen/SelectionDAGNodes.h" , 2324, __PRETTY_FUNCTION__)); | |||
2325 | } | |||
2326 | ||||
2327 | // MaskedLoadSDNode (Chain, ptr, offset, mask, passthru) | |||
2328 | // MaskedStoreSDNode (Chain, data, ptr, offset, mask) | |||
2329 | // Mask is a vector of i1 elements | |||
2330 | const SDValue &getOffset() const { | |||
2331 | return getOperand(getOpcode() == ISD::MLOAD ? 2 : 3); | |||
2332 | } | |||
2333 | const SDValue &getMask() const { | |||
2334 | return getOperand(getOpcode() == ISD::MLOAD ? 3 : 4); | |||
2335 | } | |||
2336 | ||||
2337 | /// Return the addressing mode for this load or store: | |||
2338 | /// unindexed, pre-inc, pre-dec, post-inc, or post-dec. | |||
2339 | ISD::MemIndexedMode getAddressingMode() const { | |||
2340 | return static_cast<ISD::MemIndexedMode>(LSBaseSDNodeBits.AddressingMode); | |||
2341 | } | |||
2342 | ||||
2343 | /// Return true if this is a pre/post inc/dec load/store. | |||
2344 | bool isIndexed() const { return getAddressingMode() != ISD::UNINDEXED; } | |||
2345 | ||||
2346 | /// Return true if this is NOT a pre/post inc/dec load/store. | |||
2347 | bool isUnindexed() const { return getAddressingMode() == ISD::UNINDEXED; } | |||
2348 | ||||
2349 | static bool classof(const SDNode *N) { | |||
2350 | return N->getOpcode() == ISD::MLOAD || | |||
2351 | N->getOpcode() == ISD::MSTORE; | |||
2352 | } | |||
2353 | }; | |||
2354 | ||||
2355 | /// This class is used to represent an MLOAD node | |||
2356 | class MaskedLoadSDNode : public MaskedLoadStoreSDNode { | |||
2357 | public: | |||
2358 | friend class SelectionDAG; | |||
2359 | ||||
2360 | MaskedLoadSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs, | |||
2361 | ISD::MemIndexedMode AM, ISD::LoadExtType ETy, | |||
2362 | bool IsExpanding, EVT MemVT, MachineMemOperand *MMO) | |||
2363 | : MaskedLoadStoreSDNode(ISD::MLOAD, Order, dl, VTs, AM, MemVT, MMO) { | |||
2364 | LoadSDNodeBits.ExtTy = ETy; | |||
2365 | LoadSDNodeBits.IsExpanding = IsExpanding; | |||
2366 | } | |||
2367 | ||||
2368 | ISD::LoadExtType getExtensionType() const { | |||
2369 | return static_cast<ISD::LoadExtType>(LoadSDNodeBits.ExtTy); | |||
2370 | } | |||
2371 | ||||
2372 | const SDValue &getBasePtr() const { return getOperand(1); } | |||
2373 | const SDValue &getOffset() const { return getOperand(2); } | |||
2374 | const SDValue &getMask() const { return getOperand(3); } | |||
2375 | const SDValue &getPassThru() const { return getOperand(4); } | |||
2376 | ||||
2377 | static bool classof(const SDNode *N) { | |||
2378 | return N->getOpcode() == ISD::MLOAD; | |||
2379 | } | |||
2380 | ||||
2381 | bool isExpandingLoad() const { return LoadSDNodeBits.IsExpanding; } | |||
2382 | }; | |||
2383 | ||||
2384 | /// This class is used to represent an MSTORE node | |||
2385 | class MaskedStoreSDNode : public MaskedLoadStoreSDNode { | |||
2386 | public: | |||
2387 | friend class SelectionDAG; | |||
2388 | ||||
2389 | MaskedStoreSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs, | |||
2390 | ISD::MemIndexedMode AM, bool isTrunc, bool isCompressing, | |||
2391 | EVT MemVT, MachineMemOperand *MMO) | |||
2392 | : MaskedLoadStoreSDNode(ISD::MSTORE, Order, dl, VTs, AM, MemVT, MMO) { | |||
2393 | StoreSDNodeBits.IsTruncating = isTrunc; | |||
2394 | StoreSDNodeBits.IsCompressing = isCompressing; | |||
2395 | } | |||
2396 | ||||
2397 | /// Return true if the op does a truncation before store. | |||
2398 | /// For integers this is the same as doing a TRUNCATE and storing the result. | |||
2399 | /// For floats, it is the same as doing an FP_ROUND and storing the result. | |||
2400 | bool isTruncatingStore() const { return StoreSDNodeBits.IsTruncating; } | |||
2401 | ||||
2402 | /// Returns true if the op does a compression to the vector before storing. | |||
2403 | /// The node contiguously stores the active elements (integers or floats) | |||
2404 | /// in src (those with their respective bit set in writemask k) to unaligned | |||
2405 | /// memory at base_addr. | |||
2406 | bool isCompressingStore() const { return StoreSDNodeBits.IsCompressing; } | |||
2407 | ||||
2408 | const SDValue &getValue() const { return getOperand(1); } | |||
2409 | const SDValue &getBasePtr() const { return getOperand(2); } | |||
2410 | const SDValue &getOffset() const { return getOperand(3); } | |||
2411 | const SDValue &getMask() const { return getOperand(4); } | |||
2412 | ||||
2413 | static bool classof(const SDNode *N) { | |||
2414 | return N->getOpcode() == ISD::MSTORE; | |||
2415 | } | |||
2416 | }; | |||
2417 | ||||
2418 | /// This is a base class used to represent | |||
2419 | /// MGATHER and MSCATTER nodes | |||
2420 | /// | |||
2421 | class MaskedGatherScatterSDNode : public MemSDNode { | |||
2422 | public: | |||
2423 | friend class SelectionDAG; | |||
2424 | ||||
2425 | MaskedGatherScatterSDNode(ISD::NodeType NodeTy, unsigned Order, | |||
2426 | const DebugLoc &dl, SDVTList VTs, EVT MemVT, | |||
2427 | MachineMemOperand *MMO, ISD::MemIndexType IndexType) | |||
2428 | : MemSDNode(NodeTy, Order, dl, VTs, MemVT, MMO) { | |||
2429 | LSBaseSDNodeBits.AddressingMode = IndexType; | |||
2430 | assert(getIndexType() == IndexType && "Value truncated")((getIndexType() == IndexType && "Value truncated") ? static_cast<void> (0) : __assert_fail ("getIndexType() == IndexType && \"Value truncated\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/CodeGen/SelectionDAGNodes.h" , 2430, __PRETTY_FUNCTION__)); | |||
2431 | } | |||
2432 | ||||
2433 | /// How is Index applied to BasePtr when computing addresses. | |||
2434 | ISD::MemIndexType getIndexType() const { | |||
2435 | return static_cast<ISD::MemIndexType>(LSBaseSDNodeBits.AddressingMode); | |||
2436 | } | |||
2437 | void setIndexType(ISD::MemIndexType IndexType) { | |||
2438 | LSBaseSDNodeBits.AddressingMode = IndexType; | |||
2439 | } | |||
2440 | bool isIndexScaled() const { | |||
2441 | return (getIndexType() == ISD::SIGNED_SCALED) || | |||
2442 | (getIndexType() == ISD::UNSIGNED_SCALED); | |||
2443 | } | |||
2444 | bool isIndexSigned() const { | |||
2445 | return (getIndexType() == ISD::SIGNED_SCALED) || | |||
2446 | (getIndexType() == ISD::SIGNED_UNSCALED); | |||
2447 | } | |||
2448 | ||||
2449 | // In the both nodes address is Op1, mask is Op2: | |||
2450 | // MaskedGatherSDNode (Chain, passthru, mask, base, index, scale) | |||
2451 | // MaskedScatterSDNode (Chain, value, mask, base, index, scale) | |||
2452 | // Mask is a vector of i1 elements | |||
2453 | const SDValue &getBasePtr() const { return getOperand(3); } | |||
2454 | const SDValue &getIndex() const { return getOperand(4); } | |||
2455 | const SDValue &getMask() const { return getOperand(2); } | |||
2456 | const SDValue &getScale() const { return getOperand(5); } | |||
2457 | ||||
2458 | static bool classof(const SDNode *N) { | |||
2459 | return N->getOpcode() == ISD::MGATHER || | |||
2460 | N->getOpcode() == ISD::MSCATTER; | |||
2461 | } | |||
2462 | }; | |||
2463 | ||||
2464 | /// This class is used to represent an MGATHER node | |||
2465 | /// | |||
2466 | class MaskedGatherSDNode : public MaskedGatherScatterSDNode { | |||
2467 | public: | |||
2468 | friend class SelectionDAG; | |||
2469 | ||||
2470 | MaskedGatherSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs, | |||
2471 | EVT MemVT, MachineMemOperand *MMO, | |||
2472 | ISD::MemIndexType IndexType, ISD::LoadExtType ETy) | |||
2473 | : MaskedGatherScatterSDNode(ISD::MGATHER, Order, dl, VTs, MemVT, MMO, | |||
2474 | IndexType) { | |||
2475 | LoadSDNodeBits.ExtTy = ETy; | |||
2476 | } | |||
2477 | ||||
2478 | const SDValue &getPassThru() const { return getOperand(1); } | |||
2479 | ||||
2480 | ISD::LoadExtType getExtensionType() const { | |||
2481 | return ISD::LoadExtType(LoadSDNodeBits.ExtTy); | |||
2482 | } | |||
2483 | ||||
2484 | static bool classof(const SDNode *N) { | |||
2485 | return N->getOpcode() == ISD::MGATHER; | |||
2486 | } | |||
2487 | }; | |||
2488 | ||||
2489 | /// This class is used to represent an MSCATTER node | |||
2490 | /// | |||
2491 | class MaskedScatterSDNode : public MaskedGatherScatterSDNode { | |||
2492 | public: | |||
2493 | friend class SelectionDAG; | |||
2494 | ||||
2495 | MaskedScatterSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs, | |||
2496 | EVT MemVT, MachineMemOperand *MMO, | |||
2497 | ISD::MemIndexType IndexType, bool IsTrunc) | |||
2498 | : MaskedGatherScatterSDNode(ISD::MSCATTER, Order, dl, VTs, MemVT, MMO, | |||
2499 | IndexType) { | |||
2500 | StoreSDNodeBits.IsTruncating = IsTrunc; | |||
2501 | } | |||
2502 | ||||
2503 | /// Return true if the op does a truncation before store. | |||
2504 | /// For integers this is the same as doing a TRUNCATE and storing the result. | |||
2505 | /// For floats, it is the same as doing an FP_ROUND and storing the result. | |||
2506 | bool isTruncatingStore() const { return StoreSDNodeBits.IsTruncating; } | |||
2507 | ||||
2508 | const SDValue &getValue() const { return getOperand(1); } | |||
2509 | ||||
2510 | static bool classof(const SDNode *N) { | |||
2511 | return N->getOpcode() == ISD::MSCATTER; | |||
2512 | } | |||
2513 | }; | |||
2514 | ||||
2515 | /// An SDNode that represents everything that will be needed | |||
2516 | /// to construct a MachineInstr. These nodes are created during the | |||
2517 | /// instruction selection proper phase. | |||
2518 | /// | |||
2519 | /// Note that the only supported way to set the `memoperands` is by calling the | |||
2520 | /// `SelectionDAG::setNodeMemRefs` function as the memory management happens | |||
2521 | /// inside the DAG rather than in the node. | |||
2522 | class MachineSDNode : public SDNode { | |||
2523 | private: | |||
2524 | friend class SelectionDAG; | |||
2525 | ||||
2526 | MachineSDNode(unsigned Opc, unsigned Order, const DebugLoc &DL, SDVTList VTs) | |||
2527 | : SDNode(Opc, Order, DL, VTs) {} | |||
2528 | ||||
2529 | // We use a pointer union between a single `MachineMemOperand` pointer and | |||
2530 | // a pointer to an array of `MachineMemOperand` pointers. This is null when | |||
2531 | // the number of these is zero, the single pointer variant used when the | |||
2532 | // number is one, and the array is used for larger numbers. | |||
2533 | // | |||
2534 | // The array is allocated via the `SelectionDAG`'s allocator and so will | |||
2535 | // always live until the DAG is cleaned up and doesn't require ownership here. | |||
2536 | // | |||
2537 | // We can't use something simpler like `TinyPtrVector` here because `SDNode` | |||
2538 | // subclasses aren't managed in a conforming C++ manner. See the comments on | |||
2539 | // `SelectionDAG::MorphNodeTo` which details what all goes on, but the | |||
2540 | // constraint here is that these don't manage memory with their constructor or | |||
2541 | // destructor and can be initialized to a good state even if they start off | |||
2542 | // uninitialized. | |||
2543 | PointerUnion<MachineMemOperand *, MachineMemOperand **> MemRefs = {}; | |||
2544 | ||||
2545 | // Note that this could be folded into the above `MemRefs` member if doing so | |||
2546 | // is advantageous at some point. We don't need to store this in most cases. | |||
2547 | // However, at the moment this doesn't appear to make the allocation any | |||
2548 | // smaller and makes the code somewhat simpler to read. | |||
2549 | int NumMemRefs = 0; | |||
2550 | ||||
2551 | public: | |||
2552 | using mmo_iterator = ArrayRef<MachineMemOperand *>::const_iterator; | |||
2553 | ||||
2554 | ArrayRef<MachineMemOperand *> memoperands() const { | |||
2555 | // Special case the common cases. | |||
2556 | if (NumMemRefs == 0) | |||
2557 | return {}; | |||
2558 | if (NumMemRefs == 1) | |||
2559 | return makeArrayRef(MemRefs.getAddrOfPtr1(), 1); | |||
2560 | ||||
2561 | // Otherwise we have an actual array. | |||
2562 | return makeArrayRef(MemRefs.get<MachineMemOperand **>(), NumMemRefs); | |||
2563 | } | |||
2564 | mmo_iterator memoperands_begin() const { return memoperands().begin(); } | |||
2565 | mmo_iterator memoperands_end() const { return memoperands().end(); } | |||
2566 | bool memoperands_empty() const { return memoperands().empty(); } | |||
2567 | ||||
2568 | /// Clear out the memory reference descriptor list. | |||
2569 | void clearMemRefs() { | |||
2570 | MemRefs = nullptr; | |||
2571 | NumMemRefs = 0; | |||
2572 | } | |||
2573 | ||||
2574 | static bool classof(const SDNode *N) { | |||
2575 | return N->isMachineOpcode(); | |||
2576 | } | |||
2577 | }; | |||
2578 | ||||
2579 | /// An SDNode that records if a register contains a value that is guaranteed to | |||
2580 | /// be aligned accordingly. | |||
2581 | class AssertAlignSDNode : public SDNode { | |||
2582 | Align Alignment; | |||
2583 | ||||
2584 | public: | |||
2585 | AssertAlignSDNode(unsigned Order, const DebugLoc &DL, EVT VT, Align A) | |||
2586 | : SDNode(ISD::AssertAlign, Order, DL, getSDVTList(VT)), Alignment(A) {} | |||
2587 | ||||
2588 | Align getAlign() const { return Alignment; } | |||
2589 | ||||
2590 | static bool classof(const SDNode *N) { | |||
2591 | return N->getOpcode() == ISD::AssertAlign; | |||
2592 | } | |||
2593 | }; | |||
2594 | ||||
2595 | class SDNodeIterator { | |||
2596 | const SDNode *Node; | |||
2597 | unsigned Operand; | |||
2598 | ||||
2599 | SDNodeIterator(const SDNode *N, unsigned Op) : Node(N), Operand(Op) {} | |||
2600 | ||||
2601 | public: | |||
2602 | using iterator_category = std::forward_iterator_tag; | |||
2603 | using value_type = SDNode; | |||
2604 | using difference_type = std::ptrdiff_t; | |||
2605 | using pointer = value_type *; | |||
2606 | using reference = value_type &; | |||
2607 | ||||
2608 | bool operator==(const SDNodeIterator& x) const { | |||
2609 | return Operand == x.Operand; | |||
2610 | } | |||
2611 | bool operator!=(const SDNodeIterator& x) const { return !operator==(x); } | |||
2612 | ||||
2613 | pointer operator*() const { | |||
2614 | return Node->getOperand(Operand).getNode(); | |||
2615 | } | |||
2616 | pointer operator->() const { return operator*(); } | |||
2617 | ||||
2618 | SDNodeIterator& operator++() { // Preincrement | |||
2619 | ++Operand; | |||
2620 | return *this; | |||
2621 | } | |||
2622 | SDNodeIterator operator++(int) { // Postincrement | |||
2623 | SDNodeIterator tmp = *this; ++*this; return tmp; | |||
2624 | } | |||
2625 | size_t operator-(SDNodeIterator Other) const { | |||
2626 | assert(Node == Other.Node &&((Node == Other.Node && "Cannot compare iterators of two different nodes!" ) ? static_cast<void> (0) : __assert_fail ("Node == Other.Node && \"Cannot compare iterators of two different nodes!\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/CodeGen/SelectionDAGNodes.h" , 2627, __PRETTY_FUNCTION__)) | |||
2627 | "Cannot compare iterators of two different nodes!")((Node == Other.Node && "Cannot compare iterators of two different nodes!" ) ? static_cast<void> (0) : __assert_fail ("Node == Other.Node && \"Cannot compare iterators of two different nodes!\"" , "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include/llvm/CodeGen/SelectionDAGNodes.h" , 2627, __PRETTY_FUNCTION__)); | |||
2628 | return Operand - Other.Operand; | |||
2629 | } | |||
2630 | ||||
2631 | static SDNodeIterator begin(const SDNode *N) { return SDNodeIterator(N, 0); } | |||
2632 | static SDNodeIterator end (const SDNode *N) { | |||
2633 | return SDNodeIterator(N, N->getNumOperands()); | |||
2634 | } | |||
2635 | ||||
2636 | unsigned getOperand() const { return Operand; } | |||
2637 | const SDNode *getNode() const { return Node; } | |||
2638 | }; | |||
2639 | ||||
2640 | template <> struct GraphTraits<SDNode*> { | |||
2641 | using NodeRef = SDNode *; | |||
2642 | using ChildIteratorType = SDNodeIterator; | |||
2643 | ||||
2644 | static NodeRef getEntryNode(SDNode *N) { return N; } | |||
2645 | ||||
2646 | static ChildIteratorType child_begin(NodeRef N) { | |||
2647 | return SDNodeIterator::begin(N); | |||
2648 | } | |||
2649 | ||||
2650 | static ChildIteratorType child_end(NodeRef N) { | |||
2651 | return SDNodeIterator::end(N); | |||
2652 | } | |||
2653 | }; | |||
2654 | ||||
2655 | /// A representation of the largest SDNode, for use in sizeof(). | |||
2656 | /// | |||
2657 | /// This needs to be a union because the largest node differs on 32 bit systems | |||
2658 | /// with 4 and 8 byte pointer alignment, respectively. | |||
2659 | using LargestSDNode = AlignedCharArrayUnion<AtomicSDNode, TargetIndexSDNode, | |||
2660 | BlockAddressSDNode, | |||
2661 | GlobalAddressSDNode, | |||
2662 | PseudoProbeSDNode>; | |||
2663 | ||||
2664 | /// The SDNode class with the greatest alignment requirement. | |||
2665 | using MostAlignedSDNode = GlobalAddressSDNode; | |||
2666 | ||||
2667 | namespace ISD { | |||
2668 | ||||
2669 | /// Returns true if the specified node is a non-extending and unindexed load. | |||
2670 | inline bool isNormalLoad(const SDNode *N) { | |||
2671 | const LoadSDNode *Ld = dyn_cast<LoadSDNode>(N); | |||
2672 | return Ld && Ld->getExtensionType() == ISD::NON_EXTLOAD && | |||
2673 | Ld->getAddressingMode() == ISD::UNINDEXED; | |||
2674 | } | |||
2675 | ||||
2676 | /// Returns true if the specified node is a non-extending load. | |||
2677 | inline bool isNON_EXTLoad(const SDNode *N) { | |||
2678 | return isa<LoadSDNode>(N) && | |||
2679 | cast<LoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD; | |||
2680 | } | |||
2681 | ||||
2682 | /// Returns true if the specified node is a EXTLOAD. | |||
2683 | inline bool isEXTLoad(const SDNode *N) { | |||
2684 | return isa<LoadSDNode>(N) && | |||
2685 | cast<LoadSDNode>(N)->getExtensionType() == ISD::EXTLOAD; | |||
2686 | } | |||
2687 | ||||
2688 | /// Returns true if the specified node is a SEXTLOAD. | |||
2689 | inline bool isSEXTLoad(const SDNode *N) { | |||
2690 | return isa<LoadSDNode>(N) && | |||
2691 | cast<LoadSDNode>(N)->getExtensionType() == ISD::SEXTLOAD; | |||
2692 | } | |||
2693 | ||||
2694 | /// Returns true if the specified node is a ZEXTLOAD. | |||
2695 | inline bool isZEXTLoad(const SDNode *N) { | |||
2696 | return isa<LoadSDNode>(N) && | |||
2697 | cast<LoadSDNode>(N)->getExtensionType() == ISD::ZEXTLOAD; | |||
2698 | } | |||
2699 | ||||
2700 | /// Returns true if the specified node is an unindexed load. | |||
2701 | inline bool isUNINDEXEDLoad(const SDNode *N) { | |||
2702 | return isa<LoadSDNode>(N) && | |||
2703 | cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED; | |||
2704 | } | |||
2705 | ||||
2706 | /// Returns true if the specified node is a non-truncating | |||
2707 | /// and unindexed store. | |||
2708 | inline bool isNormalStore(const SDNode *N) { | |||
2709 | const StoreSDNode *St = dyn_cast<StoreSDNode>(N); | |||
2710 | return St && !St->isTruncatingStore() && | |||
2711 | St->getAddressingMode() == ISD::UNINDEXED; | |||
2712 | } | |||
2713 | ||||
2714 | /// Returns true if the specified node is a non-truncating store. | |||
2715 | inline bool isNON_TRUNCStore(const SDNode *N) { | |||
2716 | return isa<StoreSDNode>(N) && !cast<StoreSDNode>(N)->isTruncatingStore(); | |||
2717 | } | |||
2718 | ||||
2719 | /// Returns true if the specified node is a truncating store. | |||
2720 | inline bool isTRUNCStore(const SDNode *N) { | |||
2721 | return isa<StoreSDNode>(N) && cast<StoreSDNode>(N)->isTruncatingStore(); | |||
2722 | } | |||
2723 | ||||
2724 | /// Returns true if the specified node is an unindexed store. | |||
2725 | inline bool isUNINDEXEDStore(const SDNode *N) { | |||
2726 | return isa<StoreSDNode>(N) && | |||
2727 | cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED; | |||
2728 | } | |||
2729 | ||||
2730 | /// Attempt to match a unary predicate against a scalar/splat constant or | |||
2731 | /// every element of a constant BUILD_VECTOR. | |||
2732 | /// If AllowUndef is true, then UNDEF elements will pass nullptr to Match. | |||
2733 | bool matchUnaryPredicate(SDValue Op, | |||
2734 | std::function<bool(ConstantSDNode *)> Match, | |||
2735 | bool AllowUndefs = false); | |||
2736 | ||||
2737 | /// Attempt to match a binary predicate against a pair of scalar/splat | |||
2738 | /// constants or every element of a pair of constant BUILD_VECTORs. | |||
2739 | /// If AllowUndef is true, then UNDEF elements will pass nullptr to Match. | |||
2740 | /// If AllowTypeMismatch is true then RetType + ArgTypes don't need to match. | |||
2741 | bool matchBinaryPredicate( | |||
2742 | SDValue LHS, SDValue RHS, | |||
2743 | std::function<bool(ConstantSDNode *, ConstantSDNode *)> Match, | |||
2744 | bool AllowUndefs = false, bool AllowTypeMismatch = false); | |||
2745 | ||||
2746 | /// Returns true if the specified value is the overflow result from one | |||
2747 | /// of the overflow intrinsic nodes. | |||
2748 | inline bool isOverflowIntrOpRes(SDValue Op) { | |||
2749 | unsigned Opc = Op.getOpcode(); | |||
2750 | return (Op.getResNo() == 1 && | |||
2751 | (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO || | |||
2752 | Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO)); | |||
2753 | } | |||
2754 | ||||
2755 | } // end namespace ISD | |||
2756 | ||||
2757 | } // end namespace llvm | |||
2758 | ||||
2759 | #endif // LLVM_CODEGEN_SELECTIONDAGNODES_H |