Bug Summary

File:lib/CodeGen/TargetPassConfig.cpp
Warning:line 999, column 5
Value stored to 'Ctor' is never read

Annotated Source Code

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clang -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name TargetPassConfig.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-eagerly-assume -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -mrelocation-model pic -pic-level 2 -mthread-model posix -fmath-errno -masm-verbose -mconstructor-aliases -munwind-tables -fuse-init-array -target-cpu x86-64 -dwarf-column-info -debugger-tuning=gdb -momit-leaf-frame-pointer -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-7/lib/clang/7.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-7~svn338205/build-llvm/lib/CodeGen -I /build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen -I /build/llvm-toolchain-snapshot-7~svn338205/build-llvm/include -I /build/llvm-toolchain-snapshot-7~svn338205/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/8/../../../../include/c++/8 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/8/../../../../include/x86_64-linux-gnu/c++/8 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/8/../../../../include/x86_64-linux-gnu/c++/8 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/8/../../../../include/c++/8/backward -internal-isystem /usr/include/clang/7.0.0/include/ -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-7/lib/clang/7.0.0/include -internal-externc-isystem /usr/lib/gcc/x86_64-linux-gnu/8/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-class-memaccess -Wno-comment -std=c++11 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-7~svn338205/build-llvm/lib/CodeGen -ferror-limit 19 -fmessage-length 0 -fvisibility-inlines-hidden -fobjc-runtime=gcc -fdiagnostics-show-option -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -o /tmp/scan-build-2018-07-29-043837-17923-1 -x c++ /build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/TargetPassConfig.cpp -faddrsig
1//===- TargetPassConfig.cpp - Target independent code generation passes ---===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines interfaces to access the target independent code
11// generation passes provided by the LLVM backend.
12//
13//===---------------------------------------------------------------------===//
14
15#include "llvm/CodeGen/TargetPassConfig.h"
16#include "llvm/ADT/DenseMap.h"
17#include "llvm/ADT/SmallVector.h"
18#include "llvm/ADT/StringRef.h"
19#include "llvm/Analysis/BasicAliasAnalysis.h"
20#include "llvm/Analysis/CFLAndersAliasAnalysis.h"
21#include "llvm/Analysis/CFLSteensAliasAnalysis.h"
22#include "llvm/Analysis/CallGraphSCCPass.h"
23#include "llvm/Analysis/ScopedNoAliasAA.h"
24#include "llvm/Analysis/TargetTransformInfo.h"
25#include "llvm/Analysis/TypeBasedAliasAnalysis.h"
26#include "llvm/CodeGen/MachineFunctionPass.h"
27#include "llvm/CodeGen/MachinePassRegistry.h"
28#include "llvm/CodeGen/Passes.h"
29#include "llvm/CodeGen/RegAllocRegistry.h"
30#include "llvm/IR/IRPrintingPasses.h"
31#include "llvm/IR/LegacyPassManager.h"
32#include "llvm/IR/Verifier.h"
33#include "llvm/MC/MCAsmInfo.h"
34#include "llvm/MC/MCTargetOptions.h"
35#include "llvm/Pass.h"
36#include "llvm/Support/CodeGen.h"
37#include "llvm/Support/CommandLine.h"
38#include "llvm/Support/Compiler.h"
39#include "llvm/Support/Debug.h"
40#include "llvm/Support/ErrorHandling.h"
41#include "llvm/Support/Threading.h"
42#include "llvm/Target/TargetMachine.h"
43#include "llvm/Transforms/Scalar.h"
44#include "llvm/Transforms/Utils.h"
45#include "llvm/Transforms/Utils/SymbolRewriter.h"
46#include <cassert>
47#include <string>
48
49using namespace llvm;
50
51cl::opt<bool> EnableIPRA("enable-ipra", cl::init(false), cl::Hidden,
52 cl::desc("Enable interprocedural register allocation "
53 "to reduce load/store at procedure calls."));
54static cl::opt<bool> DisablePostRASched("disable-post-ra", cl::Hidden,
55 cl::desc("Disable Post Regalloc Scheduler"));
56static cl::opt<bool> DisableBranchFold("disable-branch-fold", cl::Hidden,
57 cl::desc("Disable branch folding"));
58static cl::opt<bool> DisableTailDuplicate("disable-tail-duplicate", cl::Hidden,
59 cl::desc("Disable tail duplication"));
60static cl::opt<bool> DisableEarlyTailDup("disable-early-taildup", cl::Hidden,
61 cl::desc("Disable pre-register allocation tail duplication"));
62static cl::opt<bool> DisableBlockPlacement("disable-block-placement",
63 cl::Hidden, cl::desc("Disable probability-driven block placement"));
64static cl::opt<bool> EnableBlockPlacementStats("enable-block-placement-stats",
65 cl::Hidden, cl::desc("Collect probability-driven block placement stats"));
66static cl::opt<bool> DisableSSC("disable-ssc", cl::Hidden,
67 cl::desc("Disable Stack Slot Coloring"));
68static cl::opt<bool> DisableMachineDCE("disable-machine-dce", cl::Hidden,
69 cl::desc("Disable Machine Dead Code Elimination"));
70static cl::opt<bool> DisableEarlyIfConversion("disable-early-ifcvt", cl::Hidden,
71 cl::desc("Disable Early If-conversion"));
72static cl::opt<bool> DisableMachineLICM("disable-machine-licm", cl::Hidden,
73 cl::desc("Disable Machine LICM"));
74static cl::opt<bool> DisableMachineCSE("disable-machine-cse", cl::Hidden,
75 cl::desc("Disable Machine Common Subexpression Elimination"));
76static cl::opt<cl::boolOrDefault> OptimizeRegAlloc(
77 "optimize-regalloc", cl::Hidden,
78 cl::desc("Enable optimized register allocation compilation path."));
79static cl::opt<bool> DisablePostRAMachineLICM("disable-postra-machine-licm",
80 cl::Hidden,
81 cl::desc("Disable Machine LICM"));
82static cl::opt<bool> DisableMachineSink("disable-machine-sink", cl::Hidden,
83 cl::desc("Disable Machine Sinking"));
84static cl::opt<bool> DisablePostRAMachineSink("disable-postra-machine-sink",
85 cl::Hidden,
86 cl::desc("Disable PostRA Machine Sinking"));
87static cl::opt<bool> DisableLSR("disable-lsr", cl::Hidden,
88 cl::desc("Disable Loop Strength Reduction Pass"));
89static cl::opt<bool> DisableConstantHoisting("disable-constant-hoisting",
90 cl::Hidden, cl::desc("Disable ConstantHoisting"));
91static cl::opt<bool> DisableCGP("disable-cgp", cl::Hidden,
92 cl::desc("Disable Codegen Prepare"));
93static cl::opt<bool> DisableCopyProp("disable-copyprop", cl::Hidden,
94 cl::desc("Disable Copy Propagation pass"));
95static cl::opt<bool> DisablePartialLibcallInlining("disable-partial-libcall-inlining",
96 cl::Hidden, cl::desc("Disable Partial Libcall Inlining"));
97static cl::opt<bool> EnableImplicitNullChecks(
98 "enable-implicit-null-checks",
99 cl::desc("Fold null checks into faulting memory operations"),
100 cl::init(false), cl::Hidden);
101static cl::opt<bool> DisableMergeICmps("disable-mergeicmps",
102 cl::desc("Disable MergeICmps Pass"),
103 cl::init(false), cl::Hidden);
104static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
105 cl::desc("Print LLVM IR produced by the loop-reduce pass"));
106static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
107 cl::desc("Print LLVM IR input to isel pass"));
108static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden,
109 cl::desc("Dump garbage collector data"));
110static cl::opt<bool> VerifyMachineCode("verify-machineinstrs", cl::Hidden,
111 cl::desc("Verify generated machine code"),
112 cl::init(false),
113 cl::ZeroOrMore);
114enum RunOutliner { AlwaysOutline, NeverOutline, TargetDefault };
115// Enable or disable the MachineOutliner.
116static cl::opt<RunOutliner> EnableMachineOutliner(
117 "enable-machine-outliner", cl::desc("Enable the machine outliner"),
118 cl::Hidden, cl::ValueOptional, cl::init(TargetDefault),
119 cl::values(clEnumValN(AlwaysOutline, "always",llvm::cl::OptionEnumValue { "always", int(AlwaysOutline), "Run on all functions guaranteed to be beneficial"
}
120 "Run on all functions guaranteed to be beneficial")llvm::cl::OptionEnumValue { "always", int(AlwaysOutline), "Run on all functions guaranteed to be beneficial"
}
,
121 clEnumValN(NeverOutline, "never", "Disable all outlining")llvm::cl::OptionEnumValue { "never", int(NeverOutline), "Disable all outlining"
}
,
122 // Sentinel value for unspecified option.
123 clEnumValN(AlwaysOutline, "", "")llvm::cl::OptionEnumValue { "", int(AlwaysOutline), "" }));
124// Enable or disable FastISel. Both options are needed, because
125// FastISel is enabled by default with -fast, and we wish to be
126// able to enable or disable fast-isel independently from -O0.
127static cl::opt<cl::boolOrDefault>
128EnableFastISelOption("fast-isel", cl::Hidden,
129 cl::desc("Enable the \"fast\" instruction selector"));
130
131static cl::opt<cl::boolOrDefault> EnableGlobalISelOption(
132 "global-isel", cl::Hidden,
133 cl::desc("Enable the \"global\" instruction selector"));
134
135static cl::opt<std::string> PrintMachineInstrs(
136 "print-machineinstrs", cl::ValueOptional, cl::desc("Print machine instrs"),
137 cl::value_desc("pass-name"), cl::init("option-unspecified"), cl::Hidden);
138
139static cl::opt<int> EnableGlobalISelAbort(
140 "global-isel-abort", cl::Hidden,
141 cl::desc("Enable abort calls when \"global\" instruction selection "
142 "fails to lower/select an instruction: 0 disable the abort, "
143 "1 enable the abort, and "
144 "2 disable the abort but emit a diagnostic on failure"),
145 cl::init(1));
146
147// Temporary option to allow experimenting with MachineScheduler as a post-RA
148// scheduler. Targets can "properly" enable this with
149// substitutePass(&PostRASchedulerID, &PostMachineSchedulerID).
150// Targets can return true in targetSchedulesPostRAScheduling() and
151// insert a PostRA scheduling pass wherever it wants.
152cl::opt<bool> MISchedPostRA("misched-postra", cl::Hidden,
153 cl::desc("Run MachineScheduler post regalloc (independent of preRA sched)"));
154
155// Experimental option to run live interval analysis early.
156static cl::opt<bool> EarlyLiveIntervals("early-live-intervals", cl::Hidden,
157 cl::desc("Run live interval analysis earlier in the pipeline"));
158
159// Experimental option to use CFL-AA in codegen
160enum class CFLAAType { None, Steensgaard, Andersen, Both };
161static cl::opt<CFLAAType> UseCFLAA(
162 "use-cfl-aa-in-codegen", cl::init(CFLAAType::None), cl::Hidden,
163 cl::desc("Enable the new, experimental CFL alias analysis in CodeGen"),
164 cl::values(clEnumValN(CFLAAType::None, "none", "Disable CFL-AA")llvm::cl::OptionEnumValue { "none", int(CFLAAType::None), "Disable CFL-AA"
}
,
165 clEnumValN(CFLAAType::Steensgaard, "steens",llvm::cl::OptionEnumValue { "steens", int(CFLAAType::Steensgaard
), "Enable unification-based CFL-AA" }
166 "Enable unification-based CFL-AA")llvm::cl::OptionEnumValue { "steens", int(CFLAAType::Steensgaard
), "Enable unification-based CFL-AA" }
,
167 clEnumValN(CFLAAType::Andersen, "anders",llvm::cl::OptionEnumValue { "anders", int(CFLAAType::Andersen
), "Enable inclusion-based CFL-AA" }
168 "Enable inclusion-based CFL-AA")llvm::cl::OptionEnumValue { "anders", int(CFLAAType::Andersen
), "Enable inclusion-based CFL-AA" }
,
169 clEnumValN(CFLAAType::Both, "both",llvm::cl::OptionEnumValue { "both", int(CFLAAType::Both), "Enable both variants of CFL-AA"
}
170 "Enable both variants of CFL-AA")llvm::cl::OptionEnumValue { "both", int(CFLAAType::Both), "Enable both variants of CFL-AA"
}
));
171
172/// Option names for limiting the codegen pipeline.
173/// Those are used in error reporting and we didn't want
174/// to duplicate their names all over the place.
175const char *StartAfterOptName = "start-after";
176const char *StartBeforeOptName = "start-before";
177const char *StopAfterOptName = "stop-after";
178const char *StopBeforeOptName = "stop-before";
179
180static cl::opt<std::string>
181 StartAfterOpt(StringRef(StartAfterOptName),
182 cl::desc("Resume compilation after a specific pass"),
183 cl::value_desc("pass-name"), cl::init(""), cl::Hidden);
184
185static cl::opt<std::string>
186 StartBeforeOpt(StringRef(StartBeforeOptName),
187 cl::desc("Resume compilation before a specific pass"),
188 cl::value_desc("pass-name"), cl::init(""), cl::Hidden);
189
190static cl::opt<std::string>
191 StopAfterOpt(StringRef(StopAfterOptName),
192 cl::desc("Stop compilation after a specific pass"),
193 cl::value_desc("pass-name"), cl::init(""), cl::Hidden);
194
195static cl::opt<std::string>
196 StopBeforeOpt(StringRef(StopBeforeOptName),
197 cl::desc("Stop compilation before a specific pass"),
198 cl::value_desc("pass-name"), cl::init(""), cl::Hidden);
199
200/// Allow standard passes to be disabled by command line options. This supports
201/// simple binary flags that either suppress the pass or do nothing.
202/// i.e. -disable-mypass=false has no effect.
203/// These should be converted to boolOrDefault in order to use applyOverride.
204static IdentifyingPassPtr applyDisable(IdentifyingPassPtr PassID,
205 bool Override) {
206 if (Override)
207 return IdentifyingPassPtr();
208 return PassID;
209}
210
211/// Allow standard passes to be disabled by the command line, regardless of who
212/// is adding the pass.
213///
214/// StandardID is the pass identified in the standard pass pipeline and provided
215/// to addPass(). It may be a target-specific ID in the case that the target
216/// directly adds its own pass, but in that case we harmlessly fall through.
217///
218/// TargetID is the pass that the target has configured to override StandardID.
219///
220/// StandardID may be a pseudo ID. In that case TargetID is the name of the real
221/// pass to run. This allows multiple options to control a single pass depending
222/// on where in the pipeline that pass is added.
223static IdentifyingPassPtr overridePass(AnalysisID StandardID,
224 IdentifyingPassPtr TargetID) {
225 if (StandardID == &PostRASchedulerID)
226 return applyDisable(TargetID, DisablePostRASched);
227
228 if (StandardID == &BranchFolderPassID)
229 return applyDisable(TargetID, DisableBranchFold);
230
231 if (StandardID == &TailDuplicateID)
232 return applyDisable(TargetID, DisableTailDuplicate);
233
234 if (StandardID == &EarlyTailDuplicateID)
235 return applyDisable(TargetID, DisableEarlyTailDup);
236
237 if (StandardID == &MachineBlockPlacementID)
238 return applyDisable(TargetID, DisableBlockPlacement);
239
240 if (StandardID == &StackSlotColoringID)
241 return applyDisable(TargetID, DisableSSC);
242
243 if (StandardID == &DeadMachineInstructionElimID)
244 return applyDisable(TargetID, DisableMachineDCE);
245
246 if (StandardID == &EarlyIfConverterID)
247 return applyDisable(TargetID, DisableEarlyIfConversion);
248
249 if (StandardID == &EarlyMachineLICMID)
250 return applyDisable(TargetID, DisableMachineLICM);
251
252 if (StandardID == &MachineCSEID)
253 return applyDisable(TargetID, DisableMachineCSE);
254
255 if (StandardID == &MachineLICMID)
256 return applyDisable(TargetID, DisablePostRAMachineLICM);
257
258 if (StandardID == &MachineSinkingID)
259 return applyDisable(TargetID, DisableMachineSink);
260
261 if (StandardID == &PostRAMachineSinkingID)
262 return applyDisable(TargetID, DisablePostRAMachineSink);
263
264 if (StandardID == &MachineCopyPropagationID)
265 return applyDisable(TargetID, DisableCopyProp);
266
267 return TargetID;
268}
269
270//===---------------------------------------------------------------------===//
271/// TargetPassConfig
272//===---------------------------------------------------------------------===//
273
274INITIALIZE_PASS(TargetPassConfig, "targetpassconfig",static void *initializeTargetPassConfigPassOnce(PassRegistry &
Registry) { PassInfo *PI = new PassInfo( "Target Pass Configuration"
, "targetpassconfig", &TargetPassConfig::ID, PassInfo::NormalCtor_t
(callDefaultCtor<TargetPassConfig>), false, false); Registry
.registerPass(*PI, true); return PI; } static llvm::once_flag
InitializeTargetPassConfigPassFlag; void llvm::initializeTargetPassConfigPass
(PassRegistry &Registry) { llvm::call_once(InitializeTargetPassConfigPassFlag
, initializeTargetPassConfigPassOnce, std::ref(Registry)); }
275 "Target Pass Configuration", false, false)static void *initializeTargetPassConfigPassOnce(PassRegistry &
Registry) { PassInfo *PI = new PassInfo( "Target Pass Configuration"
, "targetpassconfig", &TargetPassConfig::ID, PassInfo::NormalCtor_t
(callDefaultCtor<TargetPassConfig>), false, false); Registry
.registerPass(*PI, true); return PI; } static llvm::once_flag
InitializeTargetPassConfigPassFlag; void llvm::initializeTargetPassConfigPass
(PassRegistry &Registry) { llvm::call_once(InitializeTargetPassConfigPassFlag
, initializeTargetPassConfigPassOnce, std::ref(Registry)); }
276char TargetPassConfig::ID = 0;
277
278namespace {
279
280struct InsertedPass {
281 AnalysisID TargetPassID;
282 IdentifyingPassPtr InsertedPassID;
283 bool VerifyAfter;
284 bool PrintAfter;
285
286 InsertedPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID,
287 bool VerifyAfter, bool PrintAfter)
288 : TargetPassID(TargetPassID), InsertedPassID(InsertedPassID),
289 VerifyAfter(VerifyAfter), PrintAfter(PrintAfter) {}
290
291 Pass *getInsertedPass() const {
292 assert(InsertedPassID.isValid() && "Illegal Pass ID!")(static_cast <bool> (InsertedPassID.isValid() &&
"Illegal Pass ID!") ? void (0) : __assert_fail ("InsertedPassID.isValid() && \"Illegal Pass ID!\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/TargetPassConfig.cpp"
, 292, __extension__ __PRETTY_FUNCTION__))
;
293 if (InsertedPassID.isInstance())
294 return InsertedPassID.getInstance();
295 Pass *NP = Pass::createPass(InsertedPassID.getID());
296 assert(NP && "Pass ID not registered")(static_cast <bool> (NP && "Pass ID not registered"
) ? void (0) : __assert_fail ("NP && \"Pass ID not registered\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/TargetPassConfig.cpp"
, 296, __extension__ __PRETTY_FUNCTION__))
;
297 return NP;
298 }
299};
300
301} // end anonymous namespace
302
303namespace llvm {
304
305class PassConfigImpl {
306public:
307 // List of passes explicitly substituted by this target. Normally this is
308 // empty, but it is a convenient way to suppress or replace specific passes
309 // that are part of a standard pass pipeline without overridding the entire
310 // pipeline. This mechanism allows target options to inherit a standard pass's
311 // user interface. For example, a target may disable a standard pass by
312 // default by substituting a pass ID of zero, and the user may still enable
313 // that standard pass with an explicit command line option.
314 DenseMap<AnalysisID,IdentifyingPassPtr> TargetPasses;
315
316 /// Store the pairs of <AnalysisID, AnalysisID> of which the second pass
317 /// is inserted after each instance of the first one.
318 SmallVector<InsertedPass, 4> InsertedPasses;
319};
320
321} // end namespace llvm
322
323// Out of line virtual method.
324TargetPassConfig::~TargetPassConfig() {
325 delete Impl;
326}
327
328static const PassInfo *getPassInfo(StringRef PassName) {
329 if (PassName.empty())
330 return nullptr;
331
332 const PassRegistry &PR = *PassRegistry::getPassRegistry();
333 const PassInfo *PI = PR.getPassInfo(PassName);
334 if (!PI)
335 report_fatal_error(Twine('\"') + Twine(PassName) +
336 Twine("\" pass is not registered."));
337 return PI;
338}
339
340static AnalysisID getPassIDFromName(StringRef PassName) {
341 const PassInfo *PI = getPassInfo(PassName);
342 return PI ? PI->getTypeInfo() : nullptr;
343}
344
345void TargetPassConfig::setStartStopPasses() {
346 StartBefore = getPassIDFromName(StartBeforeOpt);
347 StartAfter = getPassIDFromName(StartAfterOpt);
348 StopBefore = getPassIDFromName(StopBeforeOpt);
349 StopAfter = getPassIDFromName(StopAfterOpt);
350 if (StartBefore && StartAfter)
351 report_fatal_error(Twine(StartBeforeOptName) + Twine(" and ") +
352 Twine(StartAfterOptName) + Twine(" specified!"));
353 if (StopBefore && StopAfter)
354 report_fatal_error(Twine(StopBeforeOptName) + Twine(" and ") +
355 Twine(StopAfterOptName) + Twine(" specified!"));
356 Started = (StartAfter == nullptr) && (StartBefore == nullptr);
357}
358
359// Out of line constructor provides default values for pass options and
360// registers all common codegen passes.
361TargetPassConfig::TargetPassConfig(LLVMTargetMachine &TM, PassManagerBase &pm)
362 : ImmutablePass(ID), PM(&pm), TM(&TM) {
363 Impl = new PassConfigImpl();
364
365 // Register all target independent codegen passes to activate their PassIDs,
366 // including this pass itself.
367 initializeCodeGen(*PassRegistry::getPassRegistry());
368
369 // Also register alias analysis passes required by codegen passes.
370 initializeBasicAAWrapperPassPass(*PassRegistry::getPassRegistry());
371 initializeAAResultsWrapperPassPass(*PassRegistry::getPassRegistry());
372
373 if (StringRef(PrintMachineInstrs.getValue()).equals(""))
374 TM.Options.PrintMachineCode = true;
375
376 if (EnableIPRA.getNumOccurrences())
377 TM.Options.EnableIPRA = EnableIPRA;
378 else {
379 // If not explicitly specified, use target default.
380 TM.Options.EnableIPRA = TM.useIPRA();
381 }
382
383 if (TM.Options.EnableIPRA)
384 setRequiresCodeGenSCCOrder();
385
386 setStartStopPasses();
387}
388
389CodeGenOpt::Level TargetPassConfig::getOptLevel() const {
390 return TM->getOptLevel();
391}
392
393/// Insert InsertedPassID pass after TargetPassID.
394void TargetPassConfig::insertPass(AnalysisID TargetPassID,
395 IdentifyingPassPtr InsertedPassID,
396 bool VerifyAfter, bool PrintAfter) {
397 assert(((!InsertedPassID.isInstance() &&(static_cast <bool> (((!InsertedPassID.isInstance() &&
TargetPassID != InsertedPassID.getID()) || (InsertedPassID.isInstance
() && TargetPassID != InsertedPassID.getInstance()->
getPassID())) && "Insert a pass after itself!") ? void
(0) : __assert_fail ("((!InsertedPassID.isInstance() && TargetPassID != InsertedPassID.getID()) || (InsertedPassID.isInstance() && TargetPassID != InsertedPassID.getInstance()->getPassID())) && \"Insert a pass after itself!\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/TargetPassConfig.cpp"
, 401, __extension__ __PRETTY_FUNCTION__))
398 TargetPassID != InsertedPassID.getID()) ||(static_cast <bool> (((!InsertedPassID.isInstance() &&
TargetPassID != InsertedPassID.getID()) || (InsertedPassID.isInstance
() && TargetPassID != InsertedPassID.getInstance()->
getPassID())) && "Insert a pass after itself!") ? void
(0) : __assert_fail ("((!InsertedPassID.isInstance() && TargetPassID != InsertedPassID.getID()) || (InsertedPassID.isInstance() && TargetPassID != InsertedPassID.getInstance()->getPassID())) && \"Insert a pass after itself!\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/TargetPassConfig.cpp"
, 401, __extension__ __PRETTY_FUNCTION__))
399 (InsertedPassID.isInstance() &&(static_cast <bool> (((!InsertedPassID.isInstance() &&
TargetPassID != InsertedPassID.getID()) || (InsertedPassID.isInstance
() && TargetPassID != InsertedPassID.getInstance()->
getPassID())) && "Insert a pass after itself!") ? void
(0) : __assert_fail ("((!InsertedPassID.isInstance() && TargetPassID != InsertedPassID.getID()) || (InsertedPassID.isInstance() && TargetPassID != InsertedPassID.getInstance()->getPassID())) && \"Insert a pass after itself!\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/TargetPassConfig.cpp"
, 401, __extension__ __PRETTY_FUNCTION__))
400 TargetPassID != InsertedPassID.getInstance()->getPassID())) &&(static_cast <bool> (((!InsertedPassID.isInstance() &&
TargetPassID != InsertedPassID.getID()) || (InsertedPassID.isInstance
() && TargetPassID != InsertedPassID.getInstance()->
getPassID())) && "Insert a pass after itself!") ? void
(0) : __assert_fail ("((!InsertedPassID.isInstance() && TargetPassID != InsertedPassID.getID()) || (InsertedPassID.isInstance() && TargetPassID != InsertedPassID.getInstance()->getPassID())) && \"Insert a pass after itself!\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/TargetPassConfig.cpp"
, 401, __extension__ __PRETTY_FUNCTION__))
401 "Insert a pass after itself!")(static_cast <bool> (((!InsertedPassID.isInstance() &&
TargetPassID != InsertedPassID.getID()) || (InsertedPassID.isInstance
() && TargetPassID != InsertedPassID.getInstance()->
getPassID())) && "Insert a pass after itself!") ? void
(0) : __assert_fail ("((!InsertedPassID.isInstance() && TargetPassID != InsertedPassID.getID()) || (InsertedPassID.isInstance() && TargetPassID != InsertedPassID.getInstance()->getPassID())) && \"Insert a pass after itself!\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/TargetPassConfig.cpp"
, 401, __extension__ __PRETTY_FUNCTION__))
;
402 Impl->InsertedPasses.emplace_back(TargetPassID, InsertedPassID, VerifyAfter,
403 PrintAfter);
404}
405
406/// createPassConfig - Create a pass configuration object to be used by
407/// addPassToEmitX methods for generating a pipeline of CodeGen passes.
408///
409/// Targets may override this to extend TargetPassConfig.
410TargetPassConfig *LLVMTargetMachine::createPassConfig(PassManagerBase &PM) {
411 return new TargetPassConfig(*this, PM);
412}
413
414TargetPassConfig::TargetPassConfig()
415 : ImmutablePass(ID) {
416 report_fatal_error("Trying to construct TargetPassConfig without a target "
417 "machine. Scheduling a CodeGen pass without a target "
418 "triple set?");
419}
420
421bool TargetPassConfig::hasLimitedCodeGenPipeline() const {
422 return StartBefore || StartAfter || StopBefore || StopAfter;
423}
424
425std::string
426TargetPassConfig::getLimitedCodeGenPipelineReason(const char *Separator) const {
427 if (!hasLimitedCodeGenPipeline())
428 return std::string();
429 std::string Res;
430 static cl::opt<std::string> *PassNames[] = {&StartAfterOpt, &StartBeforeOpt,
431 &StopAfterOpt, &StopBeforeOpt};
432 static const char *OptNames[] = {StartAfterOptName, StartBeforeOptName,
433 StopAfterOptName, StopBeforeOptName};
434 bool IsFirst = true;
435 for (int Idx = 0; Idx < 4; ++Idx)
436 if (!PassNames[Idx]->empty()) {
437 if (!IsFirst)
438 Res += Separator;
439 IsFirst = false;
440 Res += OptNames[Idx];
441 }
442 return Res;
443}
444
445// Helper to verify the analysis is really immutable.
446void TargetPassConfig::setOpt(bool &Opt, bool Val) {
447 assert(!Initialized && "PassConfig is immutable")(static_cast <bool> (!Initialized && "PassConfig is immutable"
) ? void (0) : __assert_fail ("!Initialized && \"PassConfig is immutable\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/TargetPassConfig.cpp"
, 447, __extension__ __PRETTY_FUNCTION__))
;
448 Opt = Val;
449}
450
451void TargetPassConfig::substitutePass(AnalysisID StandardID,
452 IdentifyingPassPtr TargetID) {
453 Impl->TargetPasses[StandardID] = TargetID;
454}
455
456IdentifyingPassPtr TargetPassConfig::getPassSubstitution(AnalysisID ID) const {
457 DenseMap<AnalysisID, IdentifyingPassPtr>::const_iterator
458 I = Impl->TargetPasses.find(ID);
459 if (I == Impl->TargetPasses.end())
460 return ID;
461 return I->second;
462}
463
464bool TargetPassConfig::isPassSubstitutedOrOverridden(AnalysisID ID) const {
465 IdentifyingPassPtr TargetID = getPassSubstitution(ID);
466 IdentifyingPassPtr FinalPtr = overridePass(ID, TargetID);
467 return !FinalPtr.isValid() || FinalPtr.isInstance() ||
468 FinalPtr.getID() != ID;
469}
470
471/// Add a pass to the PassManager if that pass is supposed to be run. If the
472/// Started/Stopped flags indicate either that the compilation should start at
473/// a later pass or that it should stop after an earlier pass, then do not add
474/// the pass. Finally, compare the current pass against the StartAfter
475/// and StopAfter options and change the Started/Stopped flags accordingly.
476void TargetPassConfig::addPass(Pass *P, bool verifyAfter, bool printAfter) {
477 assert(!Initialized && "PassConfig is immutable")(static_cast <bool> (!Initialized && "PassConfig is immutable"
) ? void (0) : __assert_fail ("!Initialized && \"PassConfig is immutable\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/TargetPassConfig.cpp"
, 477, __extension__ __PRETTY_FUNCTION__))
;
478
479 // Cache the Pass ID here in case the pass manager finds this pass is
480 // redundant with ones already scheduled / available, and deletes it.
481 // Fundamentally, once we add the pass to the manager, we no longer own it
482 // and shouldn't reference it.
483 AnalysisID PassID = P->getPassID();
484
485 if (StartBefore == PassID)
486 Started = true;
487 if (StopBefore == PassID)
488 Stopped = true;
489 if (Started && !Stopped) {
490 std::string Banner;
491 // Construct banner message before PM->add() as that may delete the pass.
492 if (AddingMachinePasses && (printAfter || verifyAfter))
493 Banner = std::string("After ") + std::string(P->getPassName());
494 PM->add(P);
495 if (AddingMachinePasses) {
496 if (printAfter)
497 addPrintPass(Banner);
498 if (verifyAfter)
499 addVerifyPass(Banner);
500 }
501
502 // Add the passes after the pass P if there is any.
503 for (auto IP : Impl->InsertedPasses) {
504 if (IP.TargetPassID == PassID)
505 addPass(IP.getInsertedPass(), IP.VerifyAfter, IP.PrintAfter);
506 }
507 } else {
508 delete P;
509 }
510 if (StopAfter == PassID)
511 Stopped = true;
512 if (StartAfter == PassID)
513 Started = true;
514 if (Stopped && !Started)
515 report_fatal_error("Cannot stop compilation after pass that is not run");
516}
517
518/// Add a CodeGen pass at this point in the pipeline after checking for target
519/// and command line overrides.
520///
521/// addPass cannot return a pointer to the pass instance because is internal the
522/// PassManager and the instance we create here may already be freed.
523AnalysisID TargetPassConfig::addPass(AnalysisID PassID, bool verifyAfter,
524 bool printAfter) {
525 IdentifyingPassPtr TargetID = getPassSubstitution(PassID);
526 IdentifyingPassPtr FinalPtr = overridePass(PassID, TargetID);
527 if (!FinalPtr.isValid())
528 return nullptr;
529
530 Pass *P;
531 if (FinalPtr.isInstance())
532 P = FinalPtr.getInstance();
533 else {
534 P = Pass::createPass(FinalPtr.getID());
535 if (!P)
536 llvm_unreachable("Pass ID not registered")::llvm::llvm_unreachable_internal("Pass ID not registered", "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/TargetPassConfig.cpp"
, 536)
;
537 }
538 AnalysisID FinalID = P->getPassID();
539 addPass(P, verifyAfter, printAfter); // Ends the lifetime of P.
540
541 return FinalID;
542}
543
544void TargetPassConfig::printAndVerify(const std::string &Banner) {
545 addPrintPass(Banner);
546 addVerifyPass(Banner);
547}
548
549void TargetPassConfig::addPrintPass(const std::string &Banner) {
550 if (TM->shouldPrintMachineCode())
551 PM->add(createMachineFunctionPrinterPass(dbgs(), Banner));
552}
553
554void TargetPassConfig::addVerifyPass(const std::string &Banner) {
555 bool Verify = VerifyMachineCode;
556#ifdef EXPENSIVE_CHECKS
557 if (VerifyMachineCode == cl::BOU_UNSET)
558 Verify = TM->isMachineVerifierClean();
559#endif
560 if (Verify)
561 PM->add(createMachineVerifierPass(Banner));
562}
563
564/// Add common target configurable passes that perform LLVM IR to IR transforms
565/// following machine independent optimization.
566void TargetPassConfig::addIRPasses() {
567 switch (UseCFLAA) {
568 case CFLAAType::Steensgaard:
569 addPass(createCFLSteensAAWrapperPass());
570 break;
571 case CFLAAType::Andersen:
572 addPass(createCFLAndersAAWrapperPass());
573 break;
574 case CFLAAType::Both:
575 addPass(createCFLAndersAAWrapperPass());
576 addPass(createCFLSteensAAWrapperPass());
577 break;
578 default:
579 break;
580 }
581
582 // Basic AliasAnalysis support.
583 // Add TypeBasedAliasAnalysis before BasicAliasAnalysis so that
584 // BasicAliasAnalysis wins if they disagree. This is intended to help
585 // support "obvious" type-punning idioms.
586 addPass(createTypeBasedAAWrapperPass());
587 addPass(createScopedNoAliasAAWrapperPass());
588 addPass(createBasicAAWrapperPass());
589
590 // Before running any passes, run the verifier to determine if the input
591 // coming from the front-end and/or optimizer is valid.
592 if (!DisableVerify)
593 addPass(createVerifierPass());
594
595 // Run loop strength reduction before anything else.
596 if (getOptLevel() != CodeGenOpt::None && !DisableLSR) {
597 addPass(createLoopStrengthReducePass());
598 if (PrintLSR)
599 addPass(createPrintFunctionPass(dbgs(), "\n\n*** Code after LSR ***\n"));
600 }
601
602 if (getOptLevel() != CodeGenOpt::None) {
603 // The MergeICmpsPass tries to create memcmp calls by grouping sequences of
604 // loads and compares. ExpandMemCmpPass then tries to expand those calls
605 // into optimally-sized loads and compares. The transforms are enabled by a
606 // target lowering hook.
607 if (!DisableMergeICmps)
608 addPass(createMergeICmpsPass());
609 addPass(createExpandMemCmpPass());
610 }
611
612 // Run GC lowering passes for builtin collectors
613 // TODO: add a pass insertion point here
614 addPass(createGCLoweringPass());
615 addPass(createShadowStackGCLoweringPass());
616
617 // Make sure that no unreachable blocks are instruction selected.
618 addPass(createUnreachableBlockEliminationPass());
619
620 // Prepare expensive constants for SelectionDAG.
621 if (getOptLevel() != CodeGenOpt::None && !DisableConstantHoisting)
622 addPass(createConstantHoistingPass());
623
624 if (getOptLevel() != CodeGenOpt::None && !DisablePartialLibcallInlining)
625 addPass(createPartiallyInlineLibCallsPass());
626
627 // Instrument function entry and exit, e.g. with calls to mcount().
628 addPass(createPostInlineEntryExitInstrumenterPass());
629
630 // Add scalarization of target's unsupported masked memory intrinsics pass.
631 // the unsupported intrinsic will be replaced with a chain of basic blocks,
632 // that stores/loads element one-by-one if the appropriate mask bit is set.
633 addPass(createScalarizeMaskedMemIntrinPass());
634
635 // Expand reduction intrinsics into shuffle sequences if the target wants to.
636 addPass(createExpandReductionsPass());
637}
638
639/// Turn exception handling constructs into something the code generators can
640/// handle.
641void TargetPassConfig::addPassesToHandleExceptions() {
642 const MCAsmInfo *MCAI = TM->getMCAsmInfo();
643 assert(MCAI && "No MCAsmInfo")(static_cast <bool> (MCAI && "No MCAsmInfo") ? void
(0) : __assert_fail ("MCAI && \"No MCAsmInfo\"", "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/TargetPassConfig.cpp"
, 643, __extension__ __PRETTY_FUNCTION__))
;
644 switch (MCAI->getExceptionHandlingType()) {
645 case ExceptionHandling::SjLj:
646 // SjLj piggy-backs on dwarf for this bit. The cleanups done apply to both
647 // Dwarf EH prepare needs to be run after SjLj prepare. Otherwise,
648 // catch info can get misplaced when a selector ends up more than one block
649 // removed from the parent invoke(s). This could happen when a landing
650 // pad is shared by multiple invokes and is also a target of a normal
651 // edge from elsewhere.
652 addPass(createSjLjEHPreparePass());
653 LLVM_FALLTHROUGH[[clang::fallthrough]];
654 case ExceptionHandling::DwarfCFI:
655 case ExceptionHandling::ARM:
656 addPass(createDwarfEHPass());
657 break;
658 case ExceptionHandling::WinEH:
659 // We support using both GCC-style and MSVC-style exceptions on Windows, so
660 // add both preparation passes. Each pass will only actually run if it
661 // recognizes the personality function.
662 addPass(createWinEHPass());
663 addPass(createDwarfEHPass());
664 break;
665 case ExceptionHandling::Wasm:
666 // Wasm EH uses Windows EH instructions, but it does not need to demote PHIs
667 // on catchpads and cleanuppads because it does not outline them into
668 // funclets. Catchswitch blocks are not lowered in SelectionDAG, so we
669 // should remove PHIs there.
670 addPass(createWinEHPass(/*DemoteCatchSwitchPHIOnly=*/false));
671 addPass(createWasmEHPass());
672 break;
673 case ExceptionHandling::None:
674 addPass(createLowerInvokePass());
675
676 // The lower invoke pass may create unreachable code. Remove it.
677 addPass(createUnreachableBlockEliminationPass());
678 break;
679 }
680}
681
682/// Add pass to prepare the LLVM IR for code generation. This should be done
683/// before exception handling preparation passes.
684void TargetPassConfig::addCodeGenPrepare() {
685 if (getOptLevel() != CodeGenOpt::None && !DisableCGP)
686 addPass(createCodeGenPreparePass());
687 addPass(createRewriteSymbolsPass());
688}
689
690/// Add common passes that perform LLVM IR to IR transforms in preparation for
691/// instruction selection.
692void TargetPassConfig::addISelPrepare() {
693 addPreISel();
694
695 // Force codegen to run according to the callgraph.
696 if (requiresCodeGenSCCOrder())
697 addPass(new DummyCGSCCPass);
698
699 // Add both the safe stack and the stack protection passes: each of them will
700 // only protect functions that have corresponding attributes.
701 addPass(createSafeStackPass());
702 addPass(createStackProtectorPass());
703
704 if (PrintISelInput)
705 addPass(createPrintFunctionPass(
706 dbgs(), "\n\n*** Final LLVM Code input to ISel ***\n"));
707
708 // All passes which modify the LLVM IR are now complete; run the verifier
709 // to ensure that the IR is valid.
710 if (!DisableVerify)
711 addPass(createVerifierPass());
712}
713
714bool TargetPassConfig::addCoreISelPasses() {
715 // Enable FastISel with -fast-isel, but allow that to be overridden.
716 TM->setO0WantsFastISel(EnableFastISelOption != cl::BOU_FALSE);
717 if (EnableFastISelOption == cl::BOU_TRUE ||
718 (TM->getOptLevel() == CodeGenOpt::None && TM->getO0WantsFastISel()))
719 TM->setFastISel(true);
720
721 // Ask the target for an instruction selector.
722 // Explicitly enabling fast-isel should override implicitly enabled
723 // global-isel.
724 if (EnableGlobalISelOption == cl::BOU_TRUE ||
725 (EnableGlobalISelOption == cl::BOU_UNSET &&
726 TM->Options.EnableGlobalISel && EnableFastISelOption != cl::BOU_TRUE)) {
727 TM->setFastISel(false);
728
729 if (addIRTranslator())
730 return true;
731
732 addPreLegalizeMachineIR();
733
734 if (addLegalizeMachineIR())
735 return true;
736
737 // Before running the register bank selector, ask the target if it
738 // wants to run some passes.
739 addPreRegBankSelect();
740
741 if (addRegBankSelect())
742 return true;
743
744 addPreGlobalInstructionSelect();
745
746 if (addGlobalInstructionSelect())
747 return true;
748
749 // Pass to reset the MachineFunction if the ISel failed.
750 addPass(createResetMachineFunctionPass(
751 reportDiagnosticWhenGlobalISelFallback(), isGlobalISelAbortEnabled()));
752
753 // Provide a fallback path when we do not want to abort on
754 // not-yet-supported input.
755 if (!isGlobalISelAbortEnabled() && addInstSelector())
756 return true;
757
758 } else if (addInstSelector())
759 return true;
760
761 return false;
762}
763
764bool TargetPassConfig::addISelPasses() {
765 if (TM->useEmulatedTLS())
766 addPass(createLowerEmuTLSPass());
767
768 addPass(createPreISelIntrinsicLoweringPass());
769 addPass(createTargetTransformInfoWrapperPass(TM->getTargetIRAnalysis()));
770 addIRPasses();
771 addCodeGenPrepare();
772 addPassesToHandleExceptions();
773 addISelPrepare();
774
775 return addCoreISelPasses();
776}
777
778/// -regalloc=... command line option.
779static FunctionPass *useDefaultRegisterAllocator() { return nullptr; }
780static cl::opt<RegisterRegAlloc::FunctionPassCtor, false,
781 RegisterPassParser<RegisterRegAlloc>>
782 RegAlloc("regalloc", cl::Hidden, cl::init(&useDefaultRegisterAllocator),
783 cl::desc("Register allocator to use"));
784
785/// Add the complete set of target-independent postISel code generator passes.
786///
787/// This can be read as the standard order of major LLVM CodeGen stages. Stages
788/// with nontrivial configuration or multiple passes are broken out below in
789/// add%Stage routines.
790///
791/// Any TargetPassConfig::addXX routine may be overriden by the Target. The
792/// addPre/Post methods with empty header implementations allow injecting
793/// target-specific fixups just before or after major stages. Additionally,
794/// targets have the flexibility to change pass order within a stage by
795/// overriding default implementation of add%Stage routines below. Each
796/// technique has maintainability tradeoffs because alternate pass orders are
797/// not well supported. addPre/Post works better if the target pass is easily
798/// tied to a common pass. But if it has subtle dependencies on multiple passes,
799/// the target should override the stage instead.
800///
801/// TODO: We could use a single addPre/Post(ID) hook to allow pass injection
802/// before/after any target-independent pass. But it's currently overkill.
803void TargetPassConfig::addMachinePasses() {
804 AddingMachinePasses = true;
805
806 // Insert a machine instr printer pass after the specified pass.
807 if (!StringRef(PrintMachineInstrs.getValue()).equals("") &&
808 !StringRef(PrintMachineInstrs.getValue()).equals("option-unspecified")) {
809 const PassRegistry *PR = PassRegistry::getPassRegistry();
810 const PassInfo *TPI = PR->getPassInfo(PrintMachineInstrs.getValue());
811 const PassInfo *IPI = PR->getPassInfo(StringRef("machineinstr-printer"));
812 assert (TPI && IPI && "Pass ID not registered!")(static_cast <bool> (TPI && IPI && "Pass ID not registered!"
) ? void (0) : __assert_fail ("TPI && IPI && \"Pass ID not registered!\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/TargetPassConfig.cpp"
, 812, __extension__ __PRETTY_FUNCTION__))
;
813 const char *TID = (const char *)(TPI->getTypeInfo());
814 const char *IID = (const char *)(IPI->getTypeInfo());
815 insertPass(TID, IID);
816 }
817
818 // Print the instruction selected machine code...
819 printAndVerify("After Instruction Selection");
820
821 // Expand pseudo-instructions emitted by ISel.
822 addPass(&ExpandISelPseudosID);
823
824 // Add passes that optimize machine instructions in SSA form.
825 if (getOptLevel() != CodeGenOpt::None) {
826 addMachineSSAOptimization();
827 } else {
828 // If the target requests it, assign local variables to stack slots relative
829 // to one another and simplify frame index references where possible.
830 addPass(&LocalStackSlotAllocationID, false);
831 }
832
833 if (TM->Options.EnableIPRA)
834 addPass(createRegUsageInfoPropPass());
835
836 // Run pre-ra passes.
837 addPreRegAlloc();
838
839 // Run register allocation and passes that are tightly coupled with it,
840 // including phi elimination and scheduling.
841 if (getOptimizeRegAlloc())
842 addOptimizedRegAlloc(createRegAllocPass(true));
843 else {
844 if (RegAlloc != &useDefaultRegisterAllocator &&
845 RegAlloc != &createFastRegisterAllocator)
846 report_fatal_error("Must use fast (default) register allocator for unoptimized regalloc.");
847 addFastRegAlloc(createRegAllocPass(false));
848 }
849
850 // Run post-ra passes.
851 addPostRegAlloc();
852
853 // Insert prolog/epilog code. Eliminate abstract frame index references...
854 if (getOptLevel() != CodeGenOpt::None) {
855 addPass(&PostRAMachineSinkingID);
856 addPass(&ShrinkWrapID);
857 }
858
859 // Prolog/Epilog inserter needs a TargetMachine to instantiate. But only
860 // do so if it hasn't been disabled, substituted, or overridden.
861 if (!isPassSubstitutedOrOverridden(&PrologEpilogCodeInserterID))
862 addPass(createPrologEpilogInserterPass());
863
864 /// Add passes that optimize machine instructions after register allocation.
865 if (getOptLevel() != CodeGenOpt::None)
866 addMachineLateOptimization();
867
868 // Expand pseudo instructions before second scheduling pass.
869 addPass(&ExpandPostRAPseudosID);
870
871 // Run pre-sched2 passes.
872 addPreSched2();
873
874 if (EnableImplicitNullChecks)
875 addPass(&ImplicitNullChecksID);
876
877 // Second pass scheduler.
878 // Let Target optionally insert this pass by itself at some other
879 // point.
880 if (getOptLevel() != CodeGenOpt::None &&
881 !TM->targetSchedulesPostRAScheduling()) {
882 if (MISchedPostRA)
883 addPass(&PostMachineSchedulerID);
884 else
885 addPass(&PostRASchedulerID);
886 }
887
888 // GC
889 if (addGCPasses()) {
890 if (PrintGCInfo)
891 addPass(createGCInfoPrinter(dbgs()), false, false);
892 }
893
894 // Basic block placement.
895 if (getOptLevel() != CodeGenOpt::None)
896 addBlockPlacement();
897
898 addPreEmitPass();
899
900 if (TM->Options.EnableIPRA)
901 // Collect register usage information and produce a register mask of
902 // clobbered registers, to be used to optimize call sites.
903 addPass(createRegUsageInfoCollector());
904
905 addPass(&FuncletLayoutID, false);
906
907 addPass(&StackMapLivenessID, false);
908 addPass(&LiveDebugValuesID, false);
909
910 // Insert before XRay Instrumentation.
911 addPass(&FEntryInserterID, false);
912
913 addPass(&XRayInstrumentationID, false);
914 addPass(&PatchableFunctionID, false);
915
916 if (TM->Options.EnableMachineOutliner && getOptLevel() != CodeGenOpt::None &&
917 EnableMachineOutliner != NeverOutline) {
918 bool RunOnAllFunctions = (EnableMachineOutliner == AlwaysOutline);
919 bool AddOutliner = RunOnAllFunctions ||
920 TM->Options.SupportsDefaultOutlining;
921 if (AddOutliner)
922 addPass(createMachineOutlinerPass(RunOnAllFunctions));
923 }
924
925 // Add passes that directly emit MI after all other MI passes.
926 addPreEmitPass2();
927
928 AddingMachinePasses = false;
929}
930
931/// Add passes that optimize machine instructions in SSA form.
932void TargetPassConfig::addMachineSSAOptimization() {
933 // Pre-ra tail duplication.
934 addPass(&EarlyTailDuplicateID);
935
936 // Optimize PHIs before DCE: removing dead PHI cycles may make more
937 // instructions dead.
938 addPass(&OptimizePHIsID, false);
939
940 // This pass merges large allocas. StackSlotColoring is a different pass
941 // which merges spill slots.
942 addPass(&StackColoringID, false);
943
944 // If the target requests it, assign local variables to stack slots relative
945 // to one another and simplify frame index references where possible.
946 addPass(&LocalStackSlotAllocationID, false);
947
948 // With optimization, dead code should already be eliminated. However
949 // there is one known exception: lowered code for arguments that are only
950 // used by tail calls, where the tail calls reuse the incoming stack
951 // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
952 addPass(&DeadMachineInstructionElimID);
953
954 // Allow targets to insert passes that improve instruction level parallelism,
955 // like if-conversion. Such passes will typically need dominator trees and
956 // loop info, just like LICM and CSE below.
957 addILPOpts();
958
959 addPass(&EarlyMachineLICMID, false);
960 addPass(&MachineCSEID, false);
961
962 addPass(&MachineSinkingID);
963
964 addPass(&PeepholeOptimizerID);
965 // Clean-up the dead code that may have been generated by peephole
966 // rewriting.
967 addPass(&DeadMachineInstructionElimID);
968}
969
970//===---------------------------------------------------------------------===//
971/// Register Allocation Pass Configuration
972//===---------------------------------------------------------------------===//
973
974bool TargetPassConfig::getOptimizeRegAlloc() const {
975 switch (OptimizeRegAlloc) {
976 case cl::BOU_UNSET: return getOptLevel() != CodeGenOpt::None;
977 case cl::BOU_TRUE: return true;
978 case cl::BOU_FALSE: return false;
979 }
980 llvm_unreachable("Invalid optimize-regalloc state")::llvm::llvm_unreachable_internal("Invalid optimize-regalloc state"
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/TargetPassConfig.cpp"
, 980)
;
981}
982
983/// RegisterRegAlloc's global Registry tracks allocator registration.
984MachinePassRegistry RegisterRegAlloc::Registry;
985
986/// A dummy default pass factory indicates whether the register allocator is
987/// overridden on the command line.
988static llvm::once_flag InitializeDefaultRegisterAllocatorFlag;
989
990static RegisterRegAlloc
991defaultRegAlloc("default",
992 "pick register allocator based on -O option",
993 useDefaultRegisterAllocator);
994
995static void initializeDefaultRegisterAllocatorOnce() {
996 RegisterRegAlloc::FunctionPassCtor Ctor = RegisterRegAlloc::getDefault();
997
998 if (!Ctor) {
999 Ctor = RegAlloc;
Value stored to 'Ctor' is never read
1000 RegisterRegAlloc::setDefault(RegAlloc);
1001 }
1002}
1003
1004/// Instantiate the default register allocator pass for this target for either
1005/// the optimized or unoptimized allocation path. This will be added to the pass
1006/// manager by addFastRegAlloc in the unoptimized case or addOptimizedRegAlloc
1007/// in the optimized case.
1008///
1009/// A target that uses the standard regalloc pass order for fast or optimized
1010/// allocation may still override this for per-target regalloc
1011/// selection. But -regalloc=... always takes precedence.
1012FunctionPass *TargetPassConfig::createTargetRegisterAllocator(bool Optimized) {
1013 if (Optimized)
1014 return createGreedyRegisterAllocator();
1015 else
1016 return createFastRegisterAllocator();
1017}
1018
1019/// Find and instantiate the register allocation pass requested by this target
1020/// at the current optimization level. Different register allocators are
1021/// defined as separate passes because they may require different analysis.
1022///
1023/// This helper ensures that the regalloc= option is always available,
1024/// even for targets that override the default allocator.
1025///
1026/// FIXME: When MachinePassRegistry register pass IDs instead of function ptrs,
1027/// this can be folded into addPass.
1028FunctionPass *TargetPassConfig::createRegAllocPass(bool Optimized) {
1029 // Initialize the global default.
1030 llvm::call_once(InitializeDefaultRegisterAllocatorFlag,
1031 initializeDefaultRegisterAllocatorOnce);
1032
1033 RegisterRegAlloc::FunctionPassCtor Ctor = RegisterRegAlloc::getDefault();
1034 if (Ctor != useDefaultRegisterAllocator)
1035 return Ctor();
1036
1037 // With no -regalloc= override, ask the target for a regalloc pass.
1038 return createTargetRegisterAllocator(Optimized);
1039}
1040
1041/// Return true if the default global register allocator is in use and
1042/// has not be overriden on the command line with '-regalloc=...'
1043bool TargetPassConfig::usingDefaultRegAlloc() const {
1044 return RegAlloc.getNumOccurrences() == 0;
1045}
1046
1047/// Add the minimum set of target-independent passes that are required for
1048/// register allocation. No coalescing or scheduling.
1049void TargetPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
1050 addPass(&PHIEliminationID, false);
1051 addPass(&TwoAddressInstructionPassID, false);
1052
1053 if (RegAllocPass)
1054 addPass(RegAllocPass);
1055}
1056
1057/// Add standard target-independent passes that are tightly coupled with
1058/// optimized register allocation, including coalescing, machine instruction
1059/// scheduling, and register allocation itself.
1060void TargetPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
1061 addPass(&DetectDeadLanesID, false);
1062
1063 addPass(&ProcessImplicitDefsID, false);
1064
1065 // LiveVariables currently requires pure SSA form.
1066 //
1067 // FIXME: Once TwoAddressInstruction pass no longer uses kill flags,
1068 // LiveVariables can be removed completely, and LiveIntervals can be directly
1069 // computed. (We still either need to regenerate kill flags after regalloc, or
1070 // preferably fix the scavenger to not depend on them).
1071 addPass(&LiveVariablesID, false);
1072
1073 // Edge splitting is smarter with machine loop info.
1074 addPass(&MachineLoopInfoID, false);
1075 addPass(&PHIEliminationID, false);
1076
1077 // Eventually, we want to run LiveIntervals before PHI elimination.
1078 if (EarlyLiveIntervals)
1079 addPass(&LiveIntervalsID, false);
1080
1081 addPass(&TwoAddressInstructionPassID, false);
1082 addPass(&RegisterCoalescerID);
1083
1084 // The machine scheduler may accidentally create disconnected components
1085 // when moving subregister definitions around, avoid this by splitting them to
1086 // separate vregs before. Splitting can also improve reg. allocation quality.
1087 addPass(&RenameIndependentSubregsID);
1088
1089 // PreRA instruction scheduling.
1090 addPass(&MachineSchedulerID);
1091
1092 if (RegAllocPass) {
1093 // Add the selected register allocation pass.
1094 addPass(RegAllocPass);
1095
1096 // Allow targets to change the register assignments before rewriting.
1097 addPreRewrite();
1098
1099 // Finally rewrite virtual registers.
1100 addPass(&VirtRegRewriterID);
1101
1102 // Perform stack slot coloring and post-ra machine LICM.
1103 //
1104 // FIXME: Re-enable coloring with register when it's capable of adding
1105 // kill markers.
1106 addPass(&StackSlotColoringID);
1107
1108 // Copy propagate to forward register uses and try to eliminate COPYs that
1109 // were not coalesced.
1110 addPass(&MachineCopyPropagationID);
1111
1112 // Run post-ra machine LICM to hoist reloads / remats.
1113 //
1114 // FIXME: can this move into MachineLateOptimization?
1115 addPass(&MachineLICMID);
1116 }
1117}
1118
1119//===---------------------------------------------------------------------===//
1120/// Post RegAlloc Pass Configuration
1121//===---------------------------------------------------------------------===//
1122
1123/// Add passes that optimize machine instructions after register allocation.
1124void TargetPassConfig::addMachineLateOptimization() {
1125 // Branch folding must be run after regalloc and prolog/epilog insertion.
1126 addPass(&BranchFolderPassID);
1127
1128 // Tail duplication.
1129 // Note that duplicating tail just increases code size and degrades
1130 // performance for targets that require Structured Control Flow.
1131 // In addition it can also make CFG irreducible. Thus we disable it.
1132 if (!TM->requiresStructuredCFG())
1133 addPass(&TailDuplicateID);
1134
1135 // Copy propagation.
1136 addPass(&MachineCopyPropagationID);
1137}
1138
1139/// Add standard GC passes.
1140bool TargetPassConfig::addGCPasses() {
1141 addPass(&GCMachineCodeAnalysisID, false);
1142 return true;
1143}
1144
1145/// Add standard basic block placement passes.
1146void TargetPassConfig::addBlockPlacement() {
1147 if (addPass(&MachineBlockPlacementID)) {
1148 // Run a separate pass to collect block placement statistics.
1149 if (EnableBlockPlacementStats)
1150 addPass(&MachineBlockPlacementStatsID);
1151 }
1152}
1153
1154//===---------------------------------------------------------------------===//
1155/// GlobalISel Configuration
1156//===---------------------------------------------------------------------===//
1157bool TargetPassConfig::isGlobalISelAbortEnabled() const {
1158 if (EnableGlobalISelAbort.getNumOccurrences() > 0)
1159 return EnableGlobalISelAbort == 1;
1160
1161 // When no abort behaviour is specified, we don't abort if the target says
1162 // that GISel is enabled.
1163 return !TM->Options.EnableGlobalISel;
1164}
1165
1166bool TargetPassConfig::reportDiagnosticWhenGlobalISelFallback() const {
1167 return EnableGlobalISelAbort == 2;
1168}