Bug Summary

File:lib/CodeGen/TargetPassConfig.cpp
Warning:line 976, column 5
Value stored to 'Ctor' is never read

Annotated Source Code

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1//===- TargetPassConfig.cpp - Target independent code generation passes ---===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines interfaces to access the target independent code
11// generation passes provided by the LLVM backend.
12//
13//===---------------------------------------------------------------------===//
14
15#include "llvm/CodeGen/TargetPassConfig.h"
16#include "llvm/ADT/DenseMap.h"
17#include "llvm/ADT/SmallVector.h"
18#include "llvm/ADT/StringRef.h"
19#include "llvm/Analysis/BasicAliasAnalysis.h"
20#include "llvm/Analysis/CFLAndersAliasAnalysis.h"
21#include "llvm/Analysis/CFLSteensAliasAnalysis.h"
22#include "llvm/Analysis/CallGraphSCCPass.h"
23#include "llvm/Analysis/ScopedNoAliasAA.h"
24#include "llvm/Analysis/TargetTransformInfo.h"
25#include "llvm/Analysis/TypeBasedAliasAnalysis.h"
26#include "llvm/CodeGen/MachineFunctionPass.h"
27#include "llvm/CodeGen/MachinePassRegistry.h"
28#include "llvm/CodeGen/Passes.h"
29#include "llvm/CodeGen/RegAllocRegistry.h"
30#include "llvm/IR/IRPrintingPasses.h"
31#include "llvm/IR/LegacyPassManager.h"
32#include "llvm/IR/Verifier.h"
33#include "llvm/MC/MCAsmInfo.h"
34#include "llvm/MC/MCTargetOptions.h"
35#include "llvm/Pass.h"
36#include "llvm/Support/CodeGen.h"
37#include "llvm/Support/CommandLine.h"
38#include "llvm/Support/Compiler.h"
39#include "llvm/Support/Debug.h"
40#include "llvm/Support/ErrorHandling.h"
41#include "llvm/Support/Threading.h"
42#include "llvm/Target/TargetMachine.h"
43#include "llvm/Transforms/Scalar.h"
44#include "llvm/Transforms/Utils/SymbolRewriter.h"
45#include <cassert>
46#include <string>
47
48using namespace llvm;
49
50cl::opt<bool> EnableIPRA("enable-ipra", cl::init(false), cl::Hidden,
51 cl::desc("Enable interprocedural register allocation "
52 "to reduce load/store at procedure calls."));
53static cl::opt<bool> DisablePostRASched("disable-post-ra", cl::Hidden,
54 cl::desc("Disable Post Regalloc Scheduler"));
55static cl::opt<bool> DisableBranchFold("disable-branch-fold", cl::Hidden,
56 cl::desc("Disable branch folding"));
57static cl::opt<bool> DisableTailDuplicate("disable-tail-duplicate", cl::Hidden,
58 cl::desc("Disable tail duplication"));
59static cl::opt<bool> DisableEarlyTailDup("disable-early-taildup", cl::Hidden,
60 cl::desc("Disable pre-register allocation tail duplication"));
61static cl::opt<bool> DisableBlockPlacement("disable-block-placement",
62 cl::Hidden, cl::desc("Disable probability-driven block placement"));
63static cl::opt<bool> EnableBlockPlacementStats("enable-block-placement-stats",
64 cl::Hidden, cl::desc("Collect probability-driven block placement stats"));
65static cl::opt<bool> DisableSSC("disable-ssc", cl::Hidden,
66 cl::desc("Disable Stack Slot Coloring"));
67static cl::opt<bool> DisableMachineDCE("disable-machine-dce", cl::Hidden,
68 cl::desc("Disable Machine Dead Code Elimination"));
69static cl::opt<bool> DisableEarlyIfConversion("disable-early-ifcvt", cl::Hidden,
70 cl::desc("Disable Early If-conversion"));
71static cl::opt<bool> DisableMachineLICM("disable-machine-licm", cl::Hidden,
72 cl::desc("Disable Machine LICM"));
73static cl::opt<bool> DisableMachineCSE("disable-machine-cse", cl::Hidden,
74 cl::desc("Disable Machine Common Subexpression Elimination"));
75static cl::opt<cl::boolOrDefault> OptimizeRegAlloc(
76 "optimize-regalloc", cl::Hidden,
77 cl::desc("Enable optimized register allocation compilation path."));
78static cl::opt<bool> DisablePostRAMachineLICM("disable-postra-machine-licm",
79 cl::Hidden,
80 cl::desc("Disable Machine LICM"));
81static cl::opt<bool> DisableMachineSink("disable-machine-sink", cl::Hidden,
82 cl::desc("Disable Machine Sinking"));
83static cl::opt<bool> DisableLSR("disable-lsr", cl::Hidden,
84 cl::desc("Disable Loop Strength Reduction Pass"));
85static cl::opt<bool> DisableConstantHoisting("disable-constant-hoisting",
86 cl::Hidden, cl::desc("Disable ConstantHoisting"));
87static cl::opt<bool> DisableCGP("disable-cgp", cl::Hidden,
88 cl::desc("Disable Codegen Prepare"));
89static cl::opt<bool> DisableCopyProp("disable-copyprop", cl::Hidden,
90 cl::desc("Disable Copy Propagation pass"));
91static cl::opt<bool> DisablePartialLibcallInlining("disable-partial-libcall-inlining",
92 cl::Hidden, cl::desc("Disable Partial Libcall Inlining"));
93static cl::opt<bool> EnableImplicitNullChecks(
94 "enable-implicit-null-checks",
95 cl::desc("Fold null checks into faulting memory operations"),
96 cl::init(false), cl::Hidden);
97static cl::opt<bool>
98 EnableMergeICmps("enable-mergeicmps",
99 cl::desc("Merge ICmp chains into a single memcmp"),
100 cl::init(false), cl::Hidden);
101static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
102 cl::desc("Print LLVM IR produced by the loop-reduce pass"));
103static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
104 cl::desc("Print LLVM IR input to isel pass"));
105static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden,
106 cl::desc("Dump garbage collector data"));
107static cl::opt<bool> VerifyMachineCode("verify-machineinstrs", cl::Hidden,
108 cl::desc("Verify generated machine code"),
109 cl::init(false),
110 cl::ZeroOrMore);
111static cl::opt<bool> EnableMachineOutliner("enable-machine-outliner",
112 cl::Hidden,
113 cl::desc("Enable machine outliner"));
114static cl::opt<bool> EnableLinkOnceODROutlining(
115 "enable-linkonceodr-outlining",
116 cl::Hidden,
117 cl::desc("Enable the machine outliner on linkonceodr functions"),
118 cl::init(false));
119// Enable or disable FastISel. Both options are needed, because
120// FastISel is enabled by default with -fast, and we wish to be
121// able to enable or disable fast-isel independently from -O0.
122static cl::opt<cl::boolOrDefault>
123EnableFastISelOption("fast-isel", cl::Hidden,
124 cl::desc("Enable the \"fast\" instruction selector"));
125
126static cl::opt<cl::boolOrDefault>
127 EnableGlobalISel("global-isel", cl::Hidden,
128 cl::desc("Enable the \"global\" instruction selector"));
129
130static cl::opt<std::string> PrintMachineInstrs(
131 "print-machineinstrs", cl::ValueOptional, cl::desc("Print machine instrs"),
132 cl::value_desc("pass-name"), cl::init("option-unspecified"), cl::Hidden);
133
134static cl::opt<int> EnableGlobalISelAbort(
135 "global-isel-abort", cl::Hidden,
136 cl::desc("Enable abort calls when \"global\" instruction selection "
137 "fails to lower/select an instruction: 0 disable the abort, "
138 "1 enable the abort, and "
139 "2 disable the abort but emit a diagnostic on failure"),
140 cl::init(1));
141
142// Temporary option to allow experimenting with MachineScheduler as a post-RA
143// scheduler. Targets can "properly" enable this with
144// substitutePass(&PostRASchedulerID, &PostMachineSchedulerID).
145// Targets can return true in targetSchedulesPostRAScheduling() and
146// insert a PostRA scheduling pass wherever it wants.
147cl::opt<bool> MISchedPostRA("misched-postra", cl::Hidden,
148 cl::desc("Run MachineScheduler post regalloc (independent of preRA sched)"));
149
150// Experimental option to run live interval analysis early.
151static cl::opt<bool> EarlyLiveIntervals("early-live-intervals", cl::Hidden,
152 cl::desc("Run live interval analysis earlier in the pipeline"));
153
154// Experimental option to use CFL-AA in codegen
155enum class CFLAAType { None, Steensgaard, Andersen, Both };
156static cl::opt<CFLAAType> UseCFLAA(
157 "use-cfl-aa-in-codegen", cl::init(CFLAAType::None), cl::Hidden,
158 cl::desc("Enable the new, experimental CFL alias analysis in CodeGen"),
159 cl::values(clEnumValN(CFLAAType::None, "none", "Disable CFL-AA")llvm::cl::OptionEnumValue { "none", int(CFLAAType::None), "Disable CFL-AA"
}
,
160 clEnumValN(CFLAAType::Steensgaard, "steens",llvm::cl::OptionEnumValue { "steens", int(CFLAAType::Steensgaard
), "Enable unification-based CFL-AA" }
161 "Enable unification-based CFL-AA")llvm::cl::OptionEnumValue { "steens", int(CFLAAType::Steensgaard
), "Enable unification-based CFL-AA" }
,
162 clEnumValN(CFLAAType::Andersen, "anders",llvm::cl::OptionEnumValue { "anders", int(CFLAAType::Andersen
), "Enable inclusion-based CFL-AA" }
163 "Enable inclusion-based CFL-AA")llvm::cl::OptionEnumValue { "anders", int(CFLAAType::Andersen
), "Enable inclusion-based CFL-AA" }
,
164 clEnumValN(CFLAAType::Both, "both",llvm::cl::OptionEnumValue { "both", int(CFLAAType::Both), "Enable both variants of CFL-AA"
}
165 "Enable both variants of CFL-AA")llvm::cl::OptionEnumValue { "both", int(CFLAAType::Both), "Enable both variants of CFL-AA"
}
));
166
167/// Option names for limiting the codegen pipeline.
168/// Those are used in error reporting and we didn't want
169/// to duplicate their names all over the place.
170const char *StartAfterOptName = "start-after";
171const char *StartBeforeOptName = "start-before";
172const char *StopAfterOptName = "stop-after";
173const char *StopBeforeOptName = "stop-before";
174
175static cl::opt<std::string>
176 StartAfterOpt(StringRef(StartAfterOptName),
177 cl::desc("Resume compilation after a specific pass"),
178 cl::value_desc("pass-name"), cl::init(""), cl::Hidden);
179
180static cl::opt<std::string>
181 StartBeforeOpt(StringRef(StartBeforeOptName),
182 cl::desc("Resume compilation before a specific pass"),
183 cl::value_desc("pass-name"), cl::init(""), cl::Hidden);
184
185static cl::opt<std::string>
186 StopAfterOpt(StringRef(StopAfterOptName),
187 cl::desc("Stop compilation after a specific pass"),
188 cl::value_desc("pass-name"), cl::init(""), cl::Hidden);
189
190static cl::opt<std::string>
191 StopBeforeOpt(StringRef(StopBeforeOptName),
192 cl::desc("Stop compilation before a specific pass"),
193 cl::value_desc("pass-name"), cl::init(""), cl::Hidden);
194
195/// Allow standard passes to be disabled by command line options. This supports
196/// simple binary flags that either suppress the pass or do nothing.
197/// i.e. -disable-mypass=false has no effect.
198/// These should be converted to boolOrDefault in order to use applyOverride.
199static IdentifyingPassPtr applyDisable(IdentifyingPassPtr PassID,
200 bool Override) {
201 if (Override)
202 return IdentifyingPassPtr();
203 return PassID;
204}
205
206/// Allow standard passes to be disabled by the command line, regardless of who
207/// is adding the pass.
208///
209/// StandardID is the pass identified in the standard pass pipeline and provided
210/// to addPass(). It may be a target-specific ID in the case that the target
211/// directly adds its own pass, but in that case we harmlessly fall through.
212///
213/// TargetID is the pass that the target has configured to override StandardID.
214///
215/// StandardID may be a pseudo ID. In that case TargetID is the name of the real
216/// pass to run. This allows multiple options to control a single pass depending
217/// on where in the pipeline that pass is added.
218static IdentifyingPassPtr overridePass(AnalysisID StandardID,
219 IdentifyingPassPtr TargetID) {
220 if (StandardID == &PostRASchedulerID)
221 return applyDisable(TargetID, DisablePostRASched);
222
223 if (StandardID == &BranchFolderPassID)
224 return applyDisable(TargetID, DisableBranchFold);
225
226 if (StandardID == &TailDuplicateID)
227 return applyDisable(TargetID, DisableTailDuplicate);
228
229 if (StandardID == &TargetPassConfig::EarlyTailDuplicateID)
230 return applyDisable(TargetID, DisableEarlyTailDup);
231
232 if (StandardID == &MachineBlockPlacementID)
233 return applyDisable(TargetID, DisableBlockPlacement);
234
235 if (StandardID == &StackSlotColoringID)
236 return applyDisable(TargetID, DisableSSC);
237
238 if (StandardID == &DeadMachineInstructionElimID)
239 return applyDisable(TargetID, DisableMachineDCE);
240
241 if (StandardID == &EarlyIfConverterID)
242 return applyDisable(TargetID, DisableEarlyIfConversion);
243
244 if (StandardID == &MachineLICMID)
245 return applyDisable(TargetID, DisableMachineLICM);
246
247 if (StandardID == &MachineCSEID)
248 return applyDisable(TargetID, DisableMachineCSE);
249
250 if (StandardID == &TargetPassConfig::PostRAMachineLICMID)
251 return applyDisable(TargetID, DisablePostRAMachineLICM);
252
253 if (StandardID == &MachineSinkingID)
254 return applyDisable(TargetID, DisableMachineSink);
255
256 if (StandardID == &MachineCopyPropagationID)
257 return applyDisable(TargetID, DisableCopyProp);
258
259 return TargetID;
260}
261
262//===---------------------------------------------------------------------===//
263/// TargetPassConfig
264//===---------------------------------------------------------------------===//
265
266INITIALIZE_PASS(TargetPassConfig, "targetpassconfig",static void *initializeTargetPassConfigPassOnce(PassRegistry &
Registry) { PassInfo *PI = new PassInfo( "Target Pass Configuration"
, "targetpassconfig", &TargetPassConfig::ID, PassInfo::NormalCtor_t
(callDefaultCtor<TargetPassConfig>), false, false); Registry
.registerPass(*PI, true); return PI; } static llvm::once_flag
InitializeTargetPassConfigPassFlag; void llvm::initializeTargetPassConfigPass
(PassRegistry &Registry) { llvm::call_once(InitializeTargetPassConfigPassFlag
, initializeTargetPassConfigPassOnce, std::ref(Registry)); }
267 "Target Pass Configuration", false, false)static void *initializeTargetPassConfigPassOnce(PassRegistry &
Registry) { PassInfo *PI = new PassInfo( "Target Pass Configuration"
, "targetpassconfig", &TargetPassConfig::ID, PassInfo::NormalCtor_t
(callDefaultCtor<TargetPassConfig>), false, false); Registry
.registerPass(*PI, true); return PI; } static llvm::once_flag
InitializeTargetPassConfigPassFlag; void llvm::initializeTargetPassConfigPass
(PassRegistry &Registry) { llvm::call_once(InitializeTargetPassConfigPassFlag
, initializeTargetPassConfigPassOnce, std::ref(Registry)); }
268char TargetPassConfig::ID = 0;
269
270// Pseudo Pass IDs.
271char TargetPassConfig::EarlyTailDuplicateID = 0;
272char TargetPassConfig::PostRAMachineLICMID = 0;
273
274namespace {
275
276struct InsertedPass {
277 AnalysisID TargetPassID;
278 IdentifyingPassPtr InsertedPassID;
279 bool VerifyAfter;
280 bool PrintAfter;
281
282 InsertedPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID,
283 bool VerifyAfter, bool PrintAfter)
284 : TargetPassID(TargetPassID), InsertedPassID(InsertedPassID),
285 VerifyAfter(VerifyAfter), PrintAfter(PrintAfter) {}
286
287 Pass *getInsertedPass() const {
288 assert(InsertedPassID.isValid() && "Illegal Pass ID!")(static_cast <bool> (InsertedPassID.isValid() &&
"Illegal Pass ID!") ? void (0) : __assert_fail ("InsertedPassID.isValid() && \"Illegal Pass ID!\""
, "/build/llvm-toolchain-snapshot-6.0~svn321639/lib/CodeGen/TargetPassConfig.cpp"
, 288, __extension__ __PRETTY_FUNCTION__))
;
289 if (InsertedPassID.isInstance())
290 return InsertedPassID.getInstance();
291 Pass *NP = Pass::createPass(InsertedPassID.getID());
292 assert(NP && "Pass ID not registered")(static_cast <bool> (NP && "Pass ID not registered"
) ? void (0) : __assert_fail ("NP && \"Pass ID not registered\""
, "/build/llvm-toolchain-snapshot-6.0~svn321639/lib/CodeGen/TargetPassConfig.cpp"
, 292, __extension__ __PRETTY_FUNCTION__))
;
293 return NP;
294 }
295};
296
297} // end anonymous namespace
298
299namespace llvm {
300
301class PassConfigImpl {
302public:
303 // List of passes explicitly substituted by this target. Normally this is
304 // empty, but it is a convenient way to suppress or replace specific passes
305 // that are part of a standard pass pipeline without overridding the entire
306 // pipeline. This mechanism allows target options to inherit a standard pass's
307 // user interface. For example, a target may disable a standard pass by
308 // default by substituting a pass ID of zero, and the user may still enable
309 // that standard pass with an explicit command line option.
310 DenseMap<AnalysisID,IdentifyingPassPtr> TargetPasses;
311
312 /// Store the pairs of <AnalysisID, AnalysisID> of which the second pass
313 /// is inserted after each instance of the first one.
314 SmallVector<InsertedPass, 4> InsertedPasses;
315};
316
317} // end namespace llvm
318
319// Out of line virtual method.
320TargetPassConfig::~TargetPassConfig() {
321 delete Impl;
322}
323
324static const PassInfo *getPassInfo(StringRef PassName) {
325 if (PassName.empty())
326 return nullptr;
327
328 const PassRegistry &PR = *PassRegistry::getPassRegistry();
329 const PassInfo *PI = PR.getPassInfo(PassName);
330 if (!PI)
331 report_fatal_error(Twine('\"') + Twine(PassName) +
332 Twine("\" pass is not registered."));
333 return PI;
334}
335
336static AnalysisID getPassIDFromName(StringRef PassName) {
337 const PassInfo *PI = getPassInfo(PassName);
338 return PI ? PI->getTypeInfo() : nullptr;
339}
340
341void TargetPassConfig::setStartStopPasses() {
342 StartBefore = getPassIDFromName(StartBeforeOpt);
343 StartAfter = getPassIDFromName(StartAfterOpt);
344 StopBefore = getPassIDFromName(StopBeforeOpt);
345 StopAfter = getPassIDFromName(StopAfterOpt);
346 if (StartBefore && StartAfter)
347 report_fatal_error(Twine(StartBeforeOptName) + Twine(" and ") +
348 Twine(StartAfterOptName) + Twine(" specified!"));
349 if (StopBefore && StopAfter)
350 report_fatal_error(Twine(StopBeforeOptName) + Twine(" and ") +
351 Twine(StopAfterOptName) + Twine(" specified!"));
352 Started = (StartAfter == nullptr) && (StartBefore == nullptr);
353}
354
355// Out of line constructor provides default values for pass options and
356// registers all common codegen passes.
357TargetPassConfig::TargetPassConfig(LLVMTargetMachine &TM, PassManagerBase &pm)
358 : ImmutablePass(ID), PM(&pm), TM(&TM) {
359 Impl = new PassConfigImpl();
360
361 // Register all target independent codegen passes to activate their PassIDs,
362 // including this pass itself.
363 initializeCodeGen(*PassRegistry::getPassRegistry());
364
365 // Also register alias analysis passes required by codegen passes.
366 initializeBasicAAWrapperPassPass(*PassRegistry::getPassRegistry());
367 initializeAAResultsWrapperPassPass(*PassRegistry::getPassRegistry());
368
369 // Substitute Pseudo Pass IDs for real ones.
370 substitutePass(&EarlyTailDuplicateID, &TailDuplicateID);
371 substitutePass(&PostRAMachineLICMID, &MachineLICMID);
372
373 if (StringRef(PrintMachineInstrs.getValue()).equals(""))
374 TM.Options.PrintMachineCode = true;
375
376 if (EnableIPRA.getNumOccurrences())
377 TM.Options.EnableIPRA = EnableIPRA;
378 else {
379 // If not explicitly specified, use target default.
380 TM.Options.EnableIPRA = TM.useIPRA();
381 }
382
383 if (TM.Options.EnableIPRA)
384 setRequiresCodeGenSCCOrder();
385
386 setStartStopPasses();
387}
388
389CodeGenOpt::Level TargetPassConfig::getOptLevel() const {
390 return TM->getOptLevel();
391}
392
393/// Insert InsertedPassID pass after TargetPassID.
394void TargetPassConfig::insertPass(AnalysisID TargetPassID,
395 IdentifyingPassPtr InsertedPassID,
396 bool VerifyAfter, bool PrintAfter) {
397 assert(((!InsertedPassID.isInstance() &&(static_cast <bool> (((!InsertedPassID.isInstance() &&
TargetPassID != InsertedPassID.getID()) || (InsertedPassID.isInstance
() && TargetPassID != InsertedPassID.getInstance()->
getPassID())) && "Insert a pass after itself!") ? void
(0) : __assert_fail ("((!InsertedPassID.isInstance() && TargetPassID != InsertedPassID.getID()) || (InsertedPassID.isInstance() && TargetPassID != InsertedPassID.getInstance()->getPassID())) && \"Insert a pass after itself!\""
, "/build/llvm-toolchain-snapshot-6.0~svn321639/lib/CodeGen/TargetPassConfig.cpp"
, 401, __extension__ __PRETTY_FUNCTION__))
398 TargetPassID != InsertedPassID.getID()) ||(static_cast <bool> (((!InsertedPassID.isInstance() &&
TargetPassID != InsertedPassID.getID()) || (InsertedPassID.isInstance
() && TargetPassID != InsertedPassID.getInstance()->
getPassID())) && "Insert a pass after itself!") ? void
(0) : __assert_fail ("((!InsertedPassID.isInstance() && TargetPassID != InsertedPassID.getID()) || (InsertedPassID.isInstance() && TargetPassID != InsertedPassID.getInstance()->getPassID())) && \"Insert a pass after itself!\""
, "/build/llvm-toolchain-snapshot-6.0~svn321639/lib/CodeGen/TargetPassConfig.cpp"
, 401, __extension__ __PRETTY_FUNCTION__))
399 (InsertedPassID.isInstance() &&(static_cast <bool> (((!InsertedPassID.isInstance() &&
TargetPassID != InsertedPassID.getID()) || (InsertedPassID.isInstance
() && TargetPassID != InsertedPassID.getInstance()->
getPassID())) && "Insert a pass after itself!") ? void
(0) : __assert_fail ("((!InsertedPassID.isInstance() && TargetPassID != InsertedPassID.getID()) || (InsertedPassID.isInstance() && TargetPassID != InsertedPassID.getInstance()->getPassID())) && \"Insert a pass after itself!\""
, "/build/llvm-toolchain-snapshot-6.0~svn321639/lib/CodeGen/TargetPassConfig.cpp"
, 401, __extension__ __PRETTY_FUNCTION__))
400 TargetPassID != InsertedPassID.getInstance()->getPassID())) &&(static_cast <bool> (((!InsertedPassID.isInstance() &&
TargetPassID != InsertedPassID.getID()) || (InsertedPassID.isInstance
() && TargetPassID != InsertedPassID.getInstance()->
getPassID())) && "Insert a pass after itself!") ? void
(0) : __assert_fail ("((!InsertedPassID.isInstance() && TargetPassID != InsertedPassID.getID()) || (InsertedPassID.isInstance() && TargetPassID != InsertedPassID.getInstance()->getPassID())) && \"Insert a pass after itself!\""
, "/build/llvm-toolchain-snapshot-6.0~svn321639/lib/CodeGen/TargetPassConfig.cpp"
, 401, __extension__ __PRETTY_FUNCTION__))
401 "Insert a pass after itself!")(static_cast <bool> (((!InsertedPassID.isInstance() &&
TargetPassID != InsertedPassID.getID()) || (InsertedPassID.isInstance
() && TargetPassID != InsertedPassID.getInstance()->
getPassID())) && "Insert a pass after itself!") ? void
(0) : __assert_fail ("((!InsertedPassID.isInstance() && TargetPassID != InsertedPassID.getID()) || (InsertedPassID.isInstance() && TargetPassID != InsertedPassID.getInstance()->getPassID())) && \"Insert a pass after itself!\""
, "/build/llvm-toolchain-snapshot-6.0~svn321639/lib/CodeGen/TargetPassConfig.cpp"
, 401, __extension__ __PRETTY_FUNCTION__))
;
402 Impl->InsertedPasses.emplace_back(TargetPassID, InsertedPassID, VerifyAfter,
403 PrintAfter);
404}
405
406/// createPassConfig - Create a pass configuration object to be used by
407/// addPassToEmitX methods for generating a pipeline of CodeGen passes.
408///
409/// Targets may override this to extend TargetPassConfig.
410TargetPassConfig *LLVMTargetMachine::createPassConfig(PassManagerBase &PM) {
411 return new TargetPassConfig(*this, PM);
412}
413
414TargetPassConfig::TargetPassConfig()
415 : ImmutablePass(ID) {
416 report_fatal_error("Trying to construct TargetPassConfig without a target "
417 "machine. Scheduling a CodeGen pass without a target "
418 "triple set?");
419}
420
421bool TargetPassConfig::hasLimitedCodeGenPipeline() const {
422 return StartBefore || StartAfter || StopBefore || StopAfter;
423}
424
425std::string
426TargetPassConfig::getLimitedCodeGenPipelineReason(const char *Separator) const {
427 if (!hasLimitedCodeGenPipeline())
428 return std::string();
429 std::string Res;
430 static cl::opt<std::string> *PassNames[] = {&StartAfterOpt, &StartBeforeOpt,
431 &StopAfterOpt, &StopBeforeOpt};
432 static const char *OptNames[] = {StartAfterOptName, StartBeforeOptName,
433 StopAfterOptName, StopBeforeOptName};
434 bool IsFirst = true;
435 for (int Idx = 0; Idx < 4; ++Idx)
436 if (!PassNames[Idx]->empty()) {
437 if (!IsFirst)
438 Res += Separator;
439 IsFirst = false;
440 Res += OptNames[Idx];
441 }
442 return Res;
443}
444
445// Helper to verify the analysis is really immutable.
446void TargetPassConfig::setOpt(bool &Opt, bool Val) {
447 assert(!Initialized && "PassConfig is immutable")(static_cast <bool> (!Initialized && "PassConfig is immutable"
) ? void (0) : __assert_fail ("!Initialized && \"PassConfig is immutable\""
, "/build/llvm-toolchain-snapshot-6.0~svn321639/lib/CodeGen/TargetPassConfig.cpp"
, 447, __extension__ __PRETTY_FUNCTION__))
;
448 Opt = Val;
449}
450
451void TargetPassConfig::substitutePass(AnalysisID StandardID,
452 IdentifyingPassPtr TargetID) {
453 Impl->TargetPasses[StandardID] = TargetID;
454}
455
456IdentifyingPassPtr TargetPassConfig::getPassSubstitution(AnalysisID ID) const {
457 DenseMap<AnalysisID, IdentifyingPassPtr>::const_iterator
458 I = Impl->TargetPasses.find(ID);
459 if (I == Impl->TargetPasses.end())
460 return ID;
461 return I->second;
462}
463
464bool TargetPassConfig::isPassSubstitutedOrOverridden(AnalysisID ID) const {
465 IdentifyingPassPtr TargetID = getPassSubstitution(ID);
466 IdentifyingPassPtr FinalPtr = overridePass(ID, TargetID);
467 return !FinalPtr.isValid() || FinalPtr.isInstance() ||
468 FinalPtr.getID() != ID;
469}
470
471/// Add a pass to the PassManager if that pass is supposed to be run. If the
472/// Started/Stopped flags indicate either that the compilation should start at
473/// a later pass or that it should stop after an earlier pass, then do not add
474/// the pass. Finally, compare the current pass against the StartAfter
475/// and StopAfter options and change the Started/Stopped flags accordingly.
476void TargetPassConfig::addPass(Pass *P, bool verifyAfter, bool printAfter) {
477 assert(!Initialized && "PassConfig is immutable")(static_cast <bool> (!Initialized && "PassConfig is immutable"
) ? void (0) : __assert_fail ("!Initialized && \"PassConfig is immutable\""
, "/build/llvm-toolchain-snapshot-6.0~svn321639/lib/CodeGen/TargetPassConfig.cpp"
, 477, __extension__ __PRETTY_FUNCTION__))
;
478
479 // Cache the Pass ID here in case the pass manager finds this pass is
480 // redundant with ones already scheduled / available, and deletes it.
481 // Fundamentally, once we add the pass to the manager, we no longer own it
482 // and shouldn't reference it.
483 AnalysisID PassID = P->getPassID();
484
485 if (StartBefore == PassID)
486 Started = true;
487 if (StopBefore == PassID)
488 Stopped = true;
489 if (Started && !Stopped) {
490 std::string Banner;
491 // Construct banner message before PM->add() as that may delete the pass.
492 if (AddingMachinePasses && (printAfter || verifyAfter))
493 Banner = std::string("After ") + std::string(P->getPassName());
494 PM->add(P);
495 if (AddingMachinePasses) {
496 if (printAfter)
497 addPrintPass(Banner);
498 if (verifyAfter)
499 addVerifyPass(Banner);
500 }
501
502 // Add the passes after the pass P if there is any.
503 for (auto IP : Impl->InsertedPasses) {
504 if (IP.TargetPassID == PassID)
505 addPass(IP.getInsertedPass(), IP.VerifyAfter, IP.PrintAfter);
506 }
507 } else {
508 delete P;
509 }
510 if (StopAfter == PassID)
511 Stopped = true;
512 if (StartAfter == PassID)
513 Started = true;
514 if (Stopped && !Started)
515 report_fatal_error("Cannot stop compilation after pass that is not run");
516}
517
518/// Add a CodeGen pass at this point in the pipeline after checking for target
519/// and command line overrides.
520///
521/// addPass cannot return a pointer to the pass instance because is internal the
522/// PassManager and the instance we create here may already be freed.
523AnalysisID TargetPassConfig::addPass(AnalysisID PassID, bool verifyAfter,
524 bool printAfter) {
525 IdentifyingPassPtr TargetID = getPassSubstitution(PassID);
526 IdentifyingPassPtr FinalPtr = overridePass(PassID, TargetID);
527 if (!FinalPtr.isValid())
528 return nullptr;
529
530 Pass *P;
531 if (FinalPtr.isInstance())
532 P = FinalPtr.getInstance();
533 else {
534 P = Pass::createPass(FinalPtr.getID());
535 if (!P)
536 llvm_unreachable("Pass ID not registered")::llvm::llvm_unreachable_internal("Pass ID not registered", "/build/llvm-toolchain-snapshot-6.0~svn321639/lib/CodeGen/TargetPassConfig.cpp"
, 536)
;
537 }
538 AnalysisID FinalID = P->getPassID();
539 addPass(P, verifyAfter, printAfter); // Ends the lifetime of P.
540
541 return FinalID;
542}
543
544void TargetPassConfig::printAndVerify(const std::string &Banner) {
545 addPrintPass(Banner);
546 addVerifyPass(Banner);
547}
548
549void TargetPassConfig::addPrintPass(const std::string &Banner) {
550 if (TM->shouldPrintMachineCode())
551 PM->add(createMachineFunctionPrinterPass(dbgs(), Banner));
552}
553
554void TargetPassConfig::addVerifyPass(const std::string &Banner) {
555 bool Verify = VerifyMachineCode;
556#ifdef EXPENSIVE_CHECKS
557 if (VerifyMachineCode == cl::BOU_UNSET)
558 Verify = TM->isMachineVerifierClean();
559#endif
560 if (Verify)
561 PM->add(createMachineVerifierPass(Banner));
562}
563
564/// Add common target configurable passes that perform LLVM IR to IR transforms
565/// following machine independent optimization.
566void TargetPassConfig::addIRPasses() {
567 switch (UseCFLAA) {
568 case CFLAAType::Steensgaard:
569 addPass(createCFLSteensAAWrapperPass());
570 break;
571 case CFLAAType::Andersen:
572 addPass(createCFLAndersAAWrapperPass());
573 break;
574 case CFLAAType::Both:
575 addPass(createCFLAndersAAWrapperPass());
576 addPass(createCFLSteensAAWrapperPass());
577 break;
578 default:
579 break;
580 }
581
582 // Basic AliasAnalysis support.
583 // Add TypeBasedAliasAnalysis before BasicAliasAnalysis so that
584 // BasicAliasAnalysis wins if they disagree. This is intended to help
585 // support "obvious" type-punning idioms.
586 addPass(createTypeBasedAAWrapperPass());
587 addPass(createScopedNoAliasAAWrapperPass());
588 addPass(createBasicAAWrapperPass());
589
590 // Before running any passes, run the verifier to determine if the input
591 // coming from the front-end and/or optimizer is valid.
592 if (!DisableVerify)
593 addPass(createVerifierPass());
594
595 // Run loop strength reduction before anything else.
596 if (getOptLevel() != CodeGenOpt::None && !DisableLSR) {
597 addPass(createLoopStrengthReducePass());
598 if (PrintLSR)
599 addPass(createPrintFunctionPass(dbgs(), "\n\n*** Code after LSR ***\n"));
600 }
601
602 if (getOptLevel() != CodeGenOpt::None) {
603 // The MergeICmpsPass tries to create memcmp calls by grouping sequences of
604 // loads and compares. ExpandMemCmpPass then tries to expand those calls
605 // into optimally-sized loads and compares. The transforms are enabled by a
606 // target lowering hook.
607 if (EnableMergeICmps)
608 addPass(createMergeICmpsPass());
609 addPass(createExpandMemCmpPass());
610 }
611
612 // Run GC lowering passes for builtin collectors
613 // TODO: add a pass insertion point here
614 addPass(createGCLoweringPass());
615 addPass(createShadowStackGCLoweringPass());
616
617 // Make sure that no unreachable blocks are instruction selected.
618 addPass(createUnreachableBlockEliminationPass());
619
620 // Prepare expensive constants for SelectionDAG.
621 if (getOptLevel() != CodeGenOpt::None && !DisableConstantHoisting)
622 addPass(createConstantHoistingPass());
623
624 if (getOptLevel() != CodeGenOpt::None && !DisablePartialLibcallInlining)
625 addPass(createPartiallyInlineLibCallsPass());
626
627 // Instrument function entry and exit, e.g. with calls to mcount().
628 addPass(createPostInlineEntryExitInstrumenterPass());
629
630 // Add scalarization of target's unsupported masked memory intrinsics pass.
631 // the unsupported intrinsic will be replaced with a chain of basic blocks,
632 // that stores/loads element one-by-one if the appropriate mask bit is set.
633 addPass(createScalarizeMaskedMemIntrinPass());
634
635 // Expand reduction intrinsics into shuffle sequences if the target wants to.
636 addPass(createExpandReductionsPass());
637}
638
639/// Turn exception handling constructs into something the code generators can
640/// handle.
641void TargetPassConfig::addPassesToHandleExceptions() {
642 const MCAsmInfo *MCAI = TM->getMCAsmInfo();
643 assert(MCAI && "No MCAsmInfo")(static_cast <bool> (MCAI && "No MCAsmInfo") ? void
(0) : __assert_fail ("MCAI && \"No MCAsmInfo\"", "/build/llvm-toolchain-snapshot-6.0~svn321639/lib/CodeGen/TargetPassConfig.cpp"
, 643, __extension__ __PRETTY_FUNCTION__))
;
644 switch (MCAI->getExceptionHandlingType()) {
645 case ExceptionHandling::SjLj:
646 // SjLj piggy-backs on dwarf for this bit. The cleanups done apply to both
647 // Dwarf EH prepare needs to be run after SjLj prepare. Otherwise,
648 // catch info can get misplaced when a selector ends up more than one block
649 // removed from the parent invoke(s). This could happen when a landing
650 // pad is shared by multiple invokes and is also a target of a normal
651 // edge from elsewhere.
652 addPass(createSjLjEHPreparePass());
653 LLVM_FALLTHROUGH[[clang::fallthrough]];
654 case ExceptionHandling::DwarfCFI:
655 case ExceptionHandling::ARM:
656 addPass(createDwarfEHPass());
657 break;
658 case ExceptionHandling::WinEH:
659 // We support using both GCC-style and MSVC-style exceptions on Windows, so
660 // add both preparation passes. Each pass will only actually run if it
661 // recognizes the personality function.
662 addPass(createWinEHPass());
663 addPass(createDwarfEHPass());
664 break;
665 case ExceptionHandling::None:
666 addPass(createLowerInvokePass());
667
668 // The lower invoke pass may create unreachable code. Remove it.
669 addPass(createUnreachableBlockEliminationPass());
670 break;
671 }
672}
673
674/// Add pass to prepare the LLVM IR for code generation. This should be done
675/// before exception handling preparation passes.
676void TargetPassConfig::addCodeGenPrepare() {
677 if (getOptLevel() != CodeGenOpt::None && !DisableCGP)
678 addPass(createCodeGenPreparePass());
679 addPass(createRewriteSymbolsPass());
680}
681
682/// Add common passes that perform LLVM IR to IR transforms in preparation for
683/// instruction selection.
684void TargetPassConfig::addISelPrepare() {
685 addPreISel();
686
687 // Force codegen to run according to the callgraph.
688 if (requiresCodeGenSCCOrder())
689 addPass(new DummyCGSCCPass);
690
691 // Add both the safe stack and the stack protection passes: each of them will
692 // only protect functions that have corresponding attributes.
693 addPass(createSafeStackPass());
694 addPass(createStackProtectorPass());
695
696 if (PrintISelInput)
697 addPass(createPrintFunctionPass(
698 dbgs(), "\n\n*** Final LLVM Code input to ISel ***\n"));
699
700 // All passes which modify the LLVM IR are now complete; run the verifier
701 // to ensure that the IR is valid.
702 if (!DisableVerify)
703 addPass(createVerifierPass());
704}
705
706bool TargetPassConfig::addCoreISelPasses() {
707 // Enable FastISel with -fast, but allow that to be overridden.
708 TM->setO0WantsFastISel(EnableFastISelOption != cl::BOU_FALSE);
709 if (EnableFastISelOption == cl::BOU_TRUE ||
710 (TM->getOptLevel() == CodeGenOpt::None && TM->getO0WantsFastISel()))
711 TM->setFastISel(true);
712
713 // Ask the target for an isel.
714 // Enable GlobalISel if the target wants to, but allow that to be overriden.
715 if (EnableGlobalISel == cl::BOU_TRUE ||
716 (EnableGlobalISel == cl::BOU_UNSET && isGlobalISelEnabled())) {
717 if (addIRTranslator())
718 return true;
719
720 addPreLegalizeMachineIR();
721
722 if (addLegalizeMachineIR())
723 return true;
724
725 // Before running the register bank selector, ask the target if it
726 // wants to run some passes.
727 addPreRegBankSelect();
728
729 if (addRegBankSelect())
730 return true;
731
732 addPreGlobalInstructionSelect();
733
734 if (addGlobalInstructionSelect())
735 return true;
736
737 // Pass to reset the MachineFunction if the ISel failed.
738 addPass(createResetMachineFunctionPass(
739 reportDiagnosticWhenGlobalISelFallback(), isGlobalISelAbortEnabled()));
740
741 // Provide a fallback path when we do not want to abort on
742 // not-yet-supported input.
743 if (!isGlobalISelAbortEnabled() && addInstSelector())
744 return true;
745
746 } else if (addInstSelector())
747 return true;
748
749 return false;
750}
751
752bool TargetPassConfig::addISelPasses() {
753 if (TM->Options.EmulatedTLS)
754 addPass(createLowerEmuTLSPass());
755
756 addPass(createPreISelIntrinsicLoweringPass());
757 addPass(createTargetTransformInfoWrapperPass(TM->getTargetIRAnalysis()));
758 addIRPasses();
759 addCodeGenPrepare();
760 addPassesToHandleExceptions();
761 addISelPrepare();
762
763 return addCoreISelPasses();
764}
765
766/// -regalloc=... command line option.
767static FunctionPass *useDefaultRegisterAllocator() { return nullptr; }
768static cl::opt<RegisterRegAlloc::FunctionPassCtor, false,
769 RegisterPassParser<RegisterRegAlloc>>
770 RegAlloc("regalloc", cl::Hidden, cl::init(&useDefaultRegisterAllocator),
771 cl::desc("Register allocator to use"));
772
773/// Add the complete set of target-independent postISel code generator passes.
774///
775/// This can be read as the standard order of major LLVM CodeGen stages. Stages
776/// with nontrivial configuration or multiple passes are broken out below in
777/// add%Stage routines.
778///
779/// Any TargetPassConfig::addXX routine may be overriden by the Target. The
780/// addPre/Post methods with empty header implementations allow injecting
781/// target-specific fixups just before or after major stages. Additionally,
782/// targets have the flexibility to change pass order within a stage by
783/// overriding default implementation of add%Stage routines below. Each
784/// technique has maintainability tradeoffs because alternate pass orders are
785/// not well supported. addPre/Post works better if the target pass is easily
786/// tied to a common pass. But if it has subtle dependencies on multiple passes,
787/// the target should override the stage instead.
788///
789/// TODO: We could use a single addPre/Post(ID) hook to allow pass injection
790/// before/after any target-independent pass. But it's currently overkill.
791void TargetPassConfig::addMachinePasses() {
792 AddingMachinePasses = true;
793
794 // Insert a machine instr printer pass after the specified pass.
795 if (!StringRef(PrintMachineInstrs.getValue()).equals("") &&
796 !StringRef(PrintMachineInstrs.getValue()).equals("option-unspecified")) {
797 const PassRegistry *PR = PassRegistry::getPassRegistry();
798 const PassInfo *TPI = PR->getPassInfo(PrintMachineInstrs.getValue());
799 const PassInfo *IPI = PR->getPassInfo(StringRef("machineinstr-printer"));
800 assert (TPI && IPI && "Pass ID not registered!")(static_cast <bool> (TPI && IPI && "Pass ID not registered!"
) ? void (0) : __assert_fail ("TPI && IPI && \"Pass ID not registered!\""
, "/build/llvm-toolchain-snapshot-6.0~svn321639/lib/CodeGen/TargetPassConfig.cpp"
, 800, __extension__ __PRETTY_FUNCTION__))
;
801 const char *TID = (const char *)(TPI->getTypeInfo());
802 const char *IID = (const char *)(IPI->getTypeInfo());
803 insertPass(TID, IID);
804 }
805
806 // Print the instruction selected machine code...
807 printAndVerify("After Instruction Selection");
808
809 // Expand pseudo-instructions emitted by ISel.
810 addPass(&ExpandISelPseudosID);
811
812 // Add passes that optimize machine instructions in SSA form.
813 if (getOptLevel() != CodeGenOpt::None) {
814 addMachineSSAOptimization();
815 } else {
816 // If the target requests it, assign local variables to stack slots relative
817 // to one another and simplify frame index references where possible.
818 addPass(&LocalStackSlotAllocationID, false);
819 }
820
821 if (TM->Options.EnableIPRA)
822 addPass(createRegUsageInfoPropPass());
823
824 // Run pre-ra passes.
825 addPreRegAlloc();
826
827 // Run register allocation and passes that are tightly coupled with it,
828 // including phi elimination and scheduling.
829 if (getOptimizeRegAlloc())
830 addOptimizedRegAlloc(createRegAllocPass(true));
831 else {
832 if (RegAlloc != &useDefaultRegisterAllocator &&
833 RegAlloc != &createFastRegisterAllocator)
834 report_fatal_error("Must use fast (default) register allocator for unoptimized regalloc.");
835 addFastRegAlloc(createRegAllocPass(false));
836 }
837
838 // Run post-ra passes.
839 addPostRegAlloc();
840
841 // Insert prolog/epilog code. Eliminate abstract frame index references...
842 if (getOptLevel() != CodeGenOpt::None)
843 addPass(&ShrinkWrapID);
844
845 // Prolog/Epilog inserter needs a TargetMachine to instantiate. But only
846 // do so if it hasn't been disabled, substituted, or overridden.
847 if (!isPassSubstitutedOrOverridden(&PrologEpilogCodeInserterID))
848 addPass(createPrologEpilogInserterPass());
849
850 /// Add passes that optimize machine instructions after register allocation.
851 if (getOptLevel() != CodeGenOpt::None)
852 addMachineLateOptimization();
853
854 // Expand pseudo instructions before second scheduling pass.
855 addPass(&ExpandPostRAPseudosID);
856
857 // Run pre-sched2 passes.
858 addPreSched2();
859
860 if (EnableImplicitNullChecks)
861 addPass(&ImplicitNullChecksID);
862
863 // Second pass scheduler.
864 // Let Target optionally insert this pass by itself at some other
865 // point.
866 if (getOptLevel() != CodeGenOpt::None &&
867 !TM->targetSchedulesPostRAScheduling()) {
868 if (MISchedPostRA)
869 addPass(&PostMachineSchedulerID);
870 else
871 addPass(&PostRASchedulerID);
872 }
873
874 // GC
875 if (addGCPasses()) {
876 if (PrintGCInfo)
877 addPass(createGCInfoPrinter(dbgs()), false, false);
878 }
879
880 // Basic block placement.
881 if (getOptLevel() != CodeGenOpt::None)
882 addBlockPlacement();
883
884 addPreEmitPass();
885
886 if (TM->Options.EnableIPRA)
887 // Collect register usage information and produce a register mask of
888 // clobbered registers, to be used to optimize call sites.
889 addPass(createRegUsageInfoCollector());
890
891 addPass(&FuncletLayoutID, false);
892
893 addPass(&StackMapLivenessID, false);
894 addPass(&LiveDebugValuesID, false);
895
896 // Insert before XRay Instrumentation.
897 addPass(&FEntryInserterID, false);
898
899 addPass(&XRayInstrumentationID, false);
900 addPass(&PatchableFunctionID, false);
901
902 if (EnableMachineOutliner)
903 PM->add(createMachineOutlinerPass(EnableLinkOnceODROutlining));
904
905 AddingMachinePasses = false;
906}
907
908/// Add passes that optimize machine instructions in SSA form.
909void TargetPassConfig::addMachineSSAOptimization() {
910 // Pre-ra tail duplication.
911 addPass(&EarlyTailDuplicateID);
912
913 // Optimize PHIs before DCE: removing dead PHI cycles may make more
914 // instructions dead.
915 addPass(&OptimizePHIsID, false);
916
917 // This pass merges large allocas. StackSlotColoring is a different pass
918 // which merges spill slots.
919 addPass(&StackColoringID, false);
920
921 // If the target requests it, assign local variables to stack slots relative
922 // to one another and simplify frame index references where possible.
923 addPass(&LocalStackSlotAllocationID, false);
924
925 // With optimization, dead code should already be eliminated. However
926 // there is one known exception: lowered code for arguments that are only
927 // used by tail calls, where the tail calls reuse the incoming stack
928 // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
929 addPass(&DeadMachineInstructionElimID);
930
931 // Allow targets to insert passes that improve instruction level parallelism,
932 // like if-conversion. Such passes will typically need dominator trees and
933 // loop info, just like LICM and CSE below.
934 addILPOpts();
935
936 addPass(&MachineLICMID, false);
937 addPass(&MachineCSEID, false);
938
939 addPass(&MachineSinkingID);
940
941 addPass(&PeepholeOptimizerID);
942 // Clean-up the dead code that may have been generated by peephole
943 // rewriting.
944 addPass(&DeadMachineInstructionElimID);
945}
946
947//===---------------------------------------------------------------------===//
948/// Register Allocation Pass Configuration
949//===---------------------------------------------------------------------===//
950
951bool TargetPassConfig::getOptimizeRegAlloc() const {
952 switch (OptimizeRegAlloc) {
953 case cl::BOU_UNSET: return getOptLevel() != CodeGenOpt::None;
954 case cl::BOU_TRUE: return true;
955 case cl::BOU_FALSE: return false;
956 }
957 llvm_unreachable("Invalid optimize-regalloc state")::llvm::llvm_unreachable_internal("Invalid optimize-regalloc state"
, "/build/llvm-toolchain-snapshot-6.0~svn321639/lib/CodeGen/TargetPassConfig.cpp"
, 957)
;
958}
959
960/// RegisterRegAlloc's global Registry tracks allocator registration.
961MachinePassRegistry RegisterRegAlloc::Registry;
962
963/// A dummy default pass factory indicates whether the register allocator is
964/// overridden on the command line.
965static llvm::once_flag InitializeDefaultRegisterAllocatorFlag;
966
967static RegisterRegAlloc
968defaultRegAlloc("default",
969 "pick register allocator based on -O option",
970 useDefaultRegisterAllocator);
971
972static void initializeDefaultRegisterAllocatorOnce() {
973 RegisterRegAlloc::FunctionPassCtor Ctor = RegisterRegAlloc::getDefault();
974
975 if (!Ctor) {
976 Ctor = RegAlloc;
Value stored to 'Ctor' is never read
977 RegisterRegAlloc::setDefault(RegAlloc);
978 }
979}
980
981/// Instantiate the default register allocator pass for this target for either
982/// the optimized or unoptimized allocation path. This will be added to the pass
983/// manager by addFastRegAlloc in the unoptimized case or addOptimizedRegAlloc
984/// in the optimized case.
985///
986/// A target that uses the standard regalloc pass order for fast or optimized
987/// allocation may still override this for per-target regalloc
988/// selection. But -regalloc=... always takes precedence.
989FunctionPass *TargetPassConfig::createTargetRegisterAllocator(bool Optimized) {
990 if (Optimized)
991 return createGreedyRegisterAllocator();
992 else
993 return createFastRegisterAllocator();
994}
995
996/// Find and instantiate the register allocation pass requested by this target
997/// at the current optimization level. Different register allocators are
998/// defined as separate passes because they may require different analysis.
999///
1000/// This helper ensures that the regalloc= option is always available,
1001/// even for targets that override the default allocator.
1002///
1003/// FIXME: When MachinePassRegistry register pass IDs instead of function ptrs,
1004/// this can be folded into addPass.
1005FunctionPass *TargetPassConfig::createRegAllocPass(bool Optimized) {
1006 // Initialize the global default.
1007 llvm::call_once(InitializeDefaultRegisterAllocatorFlag,
1008 initializeDefaultRegisterAllocatorOnce);
1009
1010 RegisterRegAlloc::FunctionPassCtor Ctor = RegisterRegAlloc::getDefault();
1011 if (Ctor != useDefaultRegisterAllocator)
1012 return Ctor();
1013
1014 // With no -regalloc= override, ask the target for a regalloc pass.
1015 return createTargetRegisterAllocator(Optimized);
1016}
1017
1018/// Return true if the default global register allocator is in use and
1019/// has not be overriden on the command line with '-regalloc=...'
1020bool TargetPassConfig::usingDefaultRegAlloc() const {
1021 return RegAlloc.getNumOccurrences() == 0;
1022}
1023
1024/// Add the minimum set of target-independent passes that are required for
1025/// register allocation. No coalescing or scheduling.
1026void TargetPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
1027 addPass(&PHIEliminationID, false);
1028 addPass(&TwoAddressInstructionPassID, false);
1029
1030 if (RegAllocPass)
1031 addPass(RegAllocPass);
1032}
1033
1034/// Add standard target-independent passes that are tightly coupled with
1035/// optimized register allocation, including coalescing, machine instruction
1036/// scheduling, and register allocation itself.
1037void TargetPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
1038 addPass(&DetectDeadLanesID, false);
1039
1040 addPass(&ProcessImplicitDefsID, false);
1041
1042 // LiveVariables currently requires pure SSA form.
1043 //
1044 // FIXME: Once TwoAddressInstruction pass no longer uses kill flags,
1045 // LiveVariables can be removed completely, and LiveIntervals can be directly
1046 // computed. (We still either need to regenerate kill flags after regalloc, or
1047 // preferably fix the scavenger to not depend on them).
1048 addPass(&LiveVariablesID, false);
1049
1050 // Edge splitting is smarter with machine loop info.
1051 addPass(&MachineLoopInfoID, false);
1052 addPass(&PHIEliminationID, false);
1053
1054 // Eventually, we want to run LiveIntervals before PHI elimination.
1055 if (EarlyLiveIntervals)
1056 addPass(&LiveIntervalsID, false);
1057
1058 addPass(&TwoAddressInstructionPassID, false);
1059 addPass(&RegisterCoalescerID);
1060
1061 // The machine scheduler may accidentally create disconnected components
1062 // when moving subregister definitions around, avoid this by splitting them to
1063 // separate vregs before. Splitting can also improve reg. allocation quality.
1064 addPass(&RenameIndependentSubregsID);
1065
1066 // PreRA instruction scheduling.
1067 addPass(&MachineSchedulerID);
1068
1069 if (RegAllocPass) {
1070 // Add the selected register allocation pass.
1071 addPass(RegAllocPass);
1072
1073 // Allow targets to change the register assignments before rewriting.
1074 addPreRewrite();
1075
1076 // Finally rewrite virtual registers.
1077 addPass(&VirtRegRewriterID);
1078
1079 // Perform stack slot coloring and post-ra machine LICM.
1080 //
1081 // FIXME: Re-enable coloring with register when it's capable of adding
1082 // kill markers.
1083 addPass(&StackSlotColoringID);
1084
1085 // Run post-ra machine LICM to hoist reloads / remats.
1086 //
1087 // FIXME: can this move into MachineLateOptimization?
1088 addPass(&PostRAMachineLICMID);
1089 }
1090}
1091
1092//===---------------------------------------------------------------------===//
1093/// Post RegAlloc Pass Configuration
1094//===---------------------------------------------------------------------===//
1095
1096/// Add passes that optimize machine instructions after register allocation.
1097void TargetPassConfig::addMachineLateOptimization() {
1098 // Branch folding must be run after regalloc and prolog/epilog insertion.
1099 addPass(&BranchFolderPassID);
1100
1101 // Tail duplication.
1102 // Note that duplicating tail just increases code size and degrades
1103 // performance for targets that require Structured Control Flow.
1104 // In addition it can also make CFG irreducible. Thus we disable it.
1105 if (!TM->requiresStructuredCFG())
1106 addPass(&TailDuplicateID);
1107
1108 // Copy propagation.
1109 addPass(&MachineCopyPropagationID);
1110}
1111
1112/// Add standard GC passes.
1113bool TargetPassConfig::addGCPasses() {
1114 addPass(&GCMachineCodeAnalysisID, false);
1115 return true;
1116}
1117
1118/// Add standard basic block placement passes.
1119void TargetPassConfig::addBlockPlacement() {
1120 if (addPass(&MachineBlockPlacementID)) {
1121 // Run a separate pass to collect block placement statistics.
1122 if (EnableBlockPlacementStats)
1123 addPass(&MachineBlockPlacementStatsID);
1124 }
1125}
1126
1127//===---------------------------------------------------------------------===//
1128/// GlobalISel Configuration
1129//===---------------------------------------------------------------------===//
1130
1131bool TargetPassConfig::isGlobalISelEnabled() const {
1132 return false;
1133}
1134
1135bool TargetPassConfig::isGlobalISelAbortEnabled() const {
1136 return EnableGlobalISelAbort == 1;
1137}
1138
1139bool TargetPassConfig::reportDiagnosticWhenGlobalISelFallback() const {
1140 return EnableGlobalISelAbort == 2;
1141}