Bug Summary

File:lib/CodeGen/TargetPassConfig.cpp
Warning:line 1001, column 5
Value stored to 'Ctor' is never read

Annotated Source Code

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clang -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name TargetPassConfig.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -mrelocation-model pic -pic-level 2 -mthread-model posix -fmath-errno -masm-verbose -mconstructor-aliases -munwind-tables -fuse-init-array -target-cpu x86-64 -dwarf-column-info -debugger-tuning=gdb -momit-leaf-frame-pointer -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-8/lib/clang/8.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-8~svn345461/build-llvm/lib/CodeGen -I /build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen -I /build/llvm-toolchain-snapshot-8~svn345461/build-llvm/include -I /build/llvm-toolchain-snapshot-8~svn345461/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0/backward -internal-isystem /usr/include/clang/8.0.0/include/ -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-8/lib/clang/8.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++11 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-8~svn345461/build-llvm/lib/CodeGen -ferror-limit 19 -fmessage-length 0 -fvisibility-inlines-hidden -fobjc-runtime=gcc -fdiagnostics-show-option -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -o /tmp/scan-build-2018-10-27-211344-32123-1 -x c++ /build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/TargetPassConfig.cpp -faddrsig
1//===- TargetPassConfig.cpp - Target independent code generation passes ---===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines interfaces to access the target independent code
11// generation passes provided by the LLVM backend.
12//
13//===---------------------------------------------------------------------===//
14
15#include "llvm/CodeGen/TargetPassConfig.h"
16#include "llvm/ADT/DenseMap.h"
17#include "llvm/ADT/SmallVector.h"
18#include "llvm/ADT/StringRef.h"
19#include "llvm/Analysis/BasicAliasAnalysis.h"
20#include "llvm/Analysis/CFLAndersAliasAnalysis.h"
21#include "llvm/Analysis/CFLSteensAliasAnalysis.h"
22#include "llvm/Analysis/CallGraphSCCPass.h"
23#include "llvm/Analysis/ScopedNoAliasAA.h"
24#include "llvm/Analysis/TargetTransformInfo.h"
25#include "llvm/Analysis/TypeBasedAliasAnalysis.h"
26#include "llvm/CodeGen/MachineFunctionPass.h"
27#include "llvm/CodeGen/MachinePassRegistry.h"
28#include "llvm/CodeGen/Passes.h"
29#include "llvm/CodeGen/RegAllocRegistry.h"
30#include "llvm/IR/IRPrintingPasses.h"
31#include "llvm/IR/LegacyPassManager.h"
32#include "llvm/IR/Verifier.h"
33#include "llvm/MC/MCAsmInfo.h"
34#include "llvm/MC/MCTargetOptions.h"
35#include "llvm/Pass.h"
36#include "llvm/Support/CodeGen.h"
37#include "llvm/Support/CommandLine.h"
38#include "llvm/Support/Compiler.h"
39#include "llvm/Support/Debug.h"
40#include "llvm/Support/ErrorHandling.h"
41#include "llvm/Support/Threading.h"
42#include "llvm/Support/SaveAndRestore.h"
43#include "llvm/Target/TargetMachine.h"
44#include "llvm/Transforms/Scalar.h"
45#include "llvm/Transforms/Utils.h"
46#include "llvm/Transforms/Utils/SymbolRewriter.h"
47#include <cassert>
48#include <string>
49
50using namespace llvm;
51
52cl::opt<bool> EnableIPRA("enable-ipra", cl::init(false), cl::Hidden,
53 cl::desc("Enable interprocedural register allocation "
54 "to reduce load/store at procedure calls."));
55static cl::opt<bool> DisablePostRASched("disable-post-ra", cl::Hidden,
56 cl::desc("Disable Post Regalloc Scheduler"));
57static cl::opt<bool> DisableBranchFold("disable-branch-fold", cl::Hidden,
58 cl::desc("Disable branch folding"));
59static cl::opt<bool> DisableTailDuplicate("disable-tail-duplicate", cl::Hidden,
60 cl::desc("Disable tail duplication"));
61static cl::opt<bool> DisableEarlyTailDup("disable-early-taildup", cl::Hidden,
62 cl::desc("Disable pre-register allocation tail duplication"));
63static cl::opt<bool> DisableBlockPlacement("disable-block-placement",
64 cl::Hidden, cl::desc("Disable probability-driven block placement"));
65static cl::opt<bool> EnableBlockPlacementStats("enable-block-placement-stats",
66 cl::Hidden, cl::desc("Collect probability-driven block placement stats"));
67static cl::opt<bool> DisableSSC("disable-ssc", cl::Hidden,
68 cl::desc("Disable Stack Slot Coloring"));
69static cl::opt<bool> DisableMachineDCE("disable-machine-dce", cl::Hidden,
70 cl::desc("Disable Machine Dead Code Elimination"));
71static cl::opt<bool> DisableEarlyIfConversion("disable-early-ifcvt", cl::Hidden,
72 cl::desc("Disable Early If-conversion"));
73static cl::opt<bool> DisableMachineLICM("disable-machine-licm", cl::Hidden,
74 cl::desc("Disable Machine LICM"));
75static cl::opt<bool> DisableMachineCSE("disable-machine-cse", cl::Hidden,
76 cl::desc("Disable Machine Common Subexpression Elimination"));
77static cl::opt<cl::boolOrDefault> OptimizeRegAlloc(
78 "optimize-regalloc", cl::Hidden,
79 cl::desc("Enable optimized register allocation compilation path."));
80static cl::opt<bool> DisablePostRAMachineLICM("disable-postra-machine-licm",
81 cl::Hidden,
82 cl::desc("Disable Machine LICM"));
83static cl::opt<bool> DisableMachineSink("disable-machine-sink", cl::Hidden,
84 cl::desc("Disable Machine Sinking"));
85static cl::opt<bool> DisablePostRAMachineSink("disable-postra-machine-sink",
86 cl::Hidden,
87 cl::desc("Disable PostRA Machine Sinking"));
88static cl::opt<bool> DisableLSR("disable-lsr", cl::Hidden,
89 cl::desc("Disable Loop Strength Reduction Pass"));
90static cl::opt<bool> DisableConstantHoisting("disable-constant-hoisting",
91 cl::Hidden, cl::desc("Disable ConstantHoisting"));
92static cl::opt<bool> DisableCGP("disable-cgp", cl::Hidden,
93 cl::desc("Disable Codegen Prepare"));
94static cl::opt<bool> DisableCopyProp("disable-copyprop", cl::Hidden,
95 cl::desc("Disable Copy Propagation pass"));
96static cl::opt<bool> DisablePartialLibcallInlining("disable-partial-libcall-inlining",
97 cl::Hidden, cl::desc("Disable Partial Libcall Inlining"));
98static cl::opt<bool> EnableImplicitNullChecks(
99 "enable-implicit-null-checks",
100 cl::desc("Fold null checks into faulting memory operations"),
101 cl::init(false), cl::Hidden);
102static cl::opt<bool> DisableMergeICmps("disable-mergeicmps",
103 cl::desc("Disable MergeICmps Pass"),
104 cl::init(false), cl::Hidden);
105static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
106 cl::desc("Print LLVM IR produced by the loop-reduce pass"));
107static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
108 cl::desc("Print LLVM IR input to isel pass"));
109static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden,
110 cl::desc("Dump garbage collector data"));
111static cl::opt<cl::boolOrDefault>
112 VerifyMachineCode("verify-machineinstrs", cl::Hidden,
113 cl::desc("Verify generated machine code"),
114 cl::ZeroOrMore);
115enum RunOutliner { AlwaysOutline, NeverOutline, TargetDefault };
116// Enable or disable the MachineOutliner.
117static cl::opt<RunOutliner> EnableMachineOutliner(
118 "enable-machine-outliner", cl::desc("Enable the machine outliner"),
119 cl::Hidden, cl::ValueOptional, cl::init(TargetDefault),
120 cl::values(clEnumValN(AlwaysOutline, "always",llvm::cl::OptionEnumValue { "always", int(AlwaysOutline), "Run on all functions guaranteed to be beneficial"
}
121 "Run on all functions guaranteed to be beneficial")llvm::cl::OptionEnumValue { "always", int(AlwaysOutline), "Run on all functions guaranteed to be beneficial"
}
,
122 clEnumValN(NeverOutline, "never", "Disable all outlining")llvm::cl::OptionEnumValue { "never", int(NeverOutline), "Disable all outlining"
}
,
123 // Sentinel value for unspecified option.
124 clEnumValN(AlwaysOutline, "", "")llvm::cl::OptionEnumValue { "", int(AlwaysOutline), "" }));
125// Enable or disable FastISel. Both options are needed, because
126// FastISel is enabled by default with -fast, and we wish to be
127// able to enable or disable fast-isel independently from -O0.
128static cl::opt<cl::boolOrDefault>
129EnableFastISelOption("fast-isel", cl::Hidden,
130 cl::desc("Enable the \"fast\" instruction selector"));
131
132static cl::opt<cl::boolOrDefault> EnableGlobalISelOption(
133 "global-isel", cl::Hidden,
134 cl::desc("Enable the \"global\" instruction selector"));
135
136static cl::opt<std::string> PrintMachineInstrs(
137 "print-machineinstrs", cl::ValueOptional, cl::desc("Print machine instrs"),
138 cl::value_desc("pass-name"), cl::init("option-unspecified"), cl::Hidden);
139
140static cl::opt<int> EnableGlobalISelAbort(
141 "global-isel-abort", cl::Hidden,
142 cl::desc("Enable abort calls when \"global\" instruction selection "
143 "fails to lower/select an instruction: 0 disable the abort, "
144 "1 enable the abort, and "
145 "2 disable the abort but emit a diagnostic on failure"),
146 cl::init(1));
147
148// Temporary option to allow experimenting with MachineScheduler as a post-RA
149// scheduler. Targets can "properly" enable this with
150// substitutePass(&PostRASchedulerID, &PostMachineSchedulerID).
151// Targets can return true in targetSchedulesPostRAScheduling() and
152// insert a PostRA scheduling pass wherever it wants.
153cl::opt<bool> MISchedPostRA("misched-postra", cl::Hidden,
154 cl::desc("Run MachineScheduler post regalloc (independent of preRA sched)"));
155
156// Experimental option to run live interval analysis early.
157static cl::opt<bool> EarlyLiveIntervals("early-live-intervals", cl::Hidden,
158 cl::desc("Run live interval analysis earlier in the pipeline"));
159
160// Experimental option to use CFL-AA in codegen
161enum class CFLAAType { None, Steensgaard, Andersen, Both };
162static cl::opt<CFLAAType> UseCFLAA(
163 "use-cfl-aa-in-codegen", cl::init(CFLAAType::None), cl::Hidden,
164 cl::desc("Enable the new, experimental CFL alias analysis in CodeGen"),
165 cl::values(clEnumValN(CFLAAType::None, "none", "Disable CFL-AA")llvm::cl::OptionEnumValue { "none", int(CFLAAType::None), "Disable CFL-AA"
}
,
166 clEnumValN(CFLAAType::Steensgaard, "steens",llvm::cl::OptionEnumValue { "steens", int(CFLAAType::Steensgaard
), "Enable unification-based CFL-AA" }
167 "Enable unification-based CFL-AA")llvm::cl::OptionEnumValue { "steens", int(CFLAAType::Steensgaard
), "Enable unification-based CFL-AA" }
,
168 clEnumValN(CFLAAType::Andersen, "anders",llvm::cl::OptionEnumValue { "anders", int(CFLAAType::Andersen
), "Enable inclusion-based CFL-AA" }
169 "Enable inclusion-based CFL-AA")llvm::cl::OptionEnumValue { "anders", int(CFLAAType::Andersen
), "Enable inclusion-based CFL-AA" }
,
170 clEnumValN(CFLAAType::Both, "both",llvm::cl::OptionEnumValue { "both", int(CFLAAType::Both), "Enable both variants of CFL-AA"
}
171 "Enable both variants of CFL-AA")llvm::cl::OptionEnumValue { "both", int(CFLAAType::Both), "Enable both variants of CFL-AA"
}
));
172
173/// Option names for limiting the codegen pipeline.
174/// Those are used in error reporting and we didn't want
175/// to duplicate their names all over the place.
176const char *StartAfterOptName = "start-after";
177const char *StartBeforeOptName = "start-before";
178const char *StopAfterOptName = "stop-after";
179const char *StopBeforeOptName = "stop-before";
180
181static cl::opt<std::string>
182 StartAfterOpt(StringRef(StartAfterOptName),
183 cl::desc("Resume compilation after a specific pass"),
184 cl::value_desc("pass-name"), cl::init(""), cl::Hidden);
185
186static cl::opt<std::string>
187 StartBeforeOpt(StringRef(StartBeforeOptName),
188 cl::desc("Resume compilation before a specific pass"),
189 cl::value_desc("pass-name"), cl::init(""), cl::Hidden);
190
191static cl::opt<std::string>
192 StopAfterOpt(StringRef(StopAfterOptName),
193 cl::desc("Stop compilation after a specific pass"),
194 cl::value_desc("pass-name"), cl::init(""), cl::Hidden);
195
196static cl::opt<std::string>
197 StopBeforeOpt(StringRef(StopBeforeOptName),
198 cl::desc("Stop compilation before a specific pass"),
199 cl::value_desc("pass-name"), cl::init(""), cl::Hidden);
200
201/// Allow standard passes to be disabled by command line options. This supports
202/// simple binary flags that either suppress the pass or do nothing.
203/// i.e. -disable-mypass=false has no effect.
204/// These should be converted to boolOrDefault in order to use applyOverride.
205static IdentifyingPassPtr applyDisable(IdentifyingPassPtr PassID,
206 bool Override) {
207 if (Override)
208 return IdentifyingPassPtr();
209 return PassID;
210}
211
212/// Allow standard passes to be disabled by the command line, regardless of who
213/// is adding the pass.
214///
215/// StandardID is the pass identified in the standard pass pipeline and provided
216/// to addPass(). It may be a target-specific ID in the case that the target
217/// directly adds its own pass, but in that case we harmlessly fall through.
218///
219/// TargetID is the pass that the target has configured to override StandardID.
220///
221/// StandardID may be a pseudo ID. In that case TargetID is the name of the real
222/// pass to run. This allows multiple options to control a single pass depending
223/// on where in the pipeline that pass is added.
224static IdentifyingPassPtr overridePass(AnalysisID StandardID,
225 IdentifyingPassPtr TargetID) {
226 if (StandardID == &PostRASchedulerID)
227 return applyDisable(TargetID, DisablePostRASched);
228
229 if (StandardID == &BranchFolderPassID)
230 return applyDisable(TargetID, DisableBranchFold);
231
232 if (StandardID == &TailDuplicateID)
233 return applyDisable(TargetID, DisableTailDuplicate);
234
235 if (StandardID == &EarlyTailDuplicateID)
236 return applyDisable(TargetID, DisableEarlyTailDup);
237
238 if (StandardID == &MachineBlockPlacementID)
239 return applyDisable(TargetID, DisableBlockPlacement);
240
241 if (StandardID == &StackSlotColoringID)
242 return applyDisable(TargetID, DisableSSC);
243
244 if (StandardID == &DeadMachineInstructionElimID)
245 return applyDisable(TargetID, DisableMachineDCE);
246
247 if (StandardID == &EarlyIfConverterID)
248 return applyDisable(TargetID, DisableEarlyIfConversion);
249
250 if (StandardID == &EarlyMachineLICMID)
251 return applyDisable(TargetID, DisableMachineLICM);
252
253 if (StandardID == &MachineCSEID)
254 return applyDisable(TargetID, DisableMachineCSE);
255
256 if (StandardID == &MachineLICMID)
257 return applyDisable(TargetID, DisablePostRAMachineLICM);
258
259 if (StandardID == &MachineSinkingID)
260 return applyDisable(TargetID, DisableMachineSink);
261
262 if (StandardID == &PostRAMachineSinkingID)
263 return applyDisable(TargetID, DisablePostRAMachineSink);
264
265 if (StandardID == &MachineCopyPropagationID)
266 return applyDisable(TargetID, DisableCopyProp);
267
268 return TargetID;
269}
270
271//===---------------------------------------------------------------------===//
272/// TargetPassConfig
273//===---------------------------------------------------------------------===//
274
275INITIALIZE_PASS(TargetPassConfig, "targetpassconfig",static void *initializeTargetPassConfigPassOnce(PassRegistry &
Registry) { PassInfo *PI = new PassInfo( "Target Pass Configuration"
, "targetpassconfig", &TargetPassConfig::ID, PassInfo::NormalCtor_t
(callDefaultCtor<TargetPassConfig>), false, false); Registry
.registerPass(*PI, true); return PI; } static llvm::once_flag
InitializeTargetPassConfigPassFlag; void llvm::initializeTargetPassConfigPass
(PassRegistry &Registry) { llvm::call_once(InitializeTargetPassConfigPassFlag
, initializeTargetPassConfigPassOnce, std::ref(Registry)); }
276 "Target Pass Configuration", false, false)static void *initializeTargetPassConfigPassOnce(PassRegistry &
Registry) { PassInfo *PI = new PassInfo( "Target Pass Configuration"
, "targetpassconfig", &TargetPassConfig::ID, PassInfo::NormalCtor_t
(callDefaultCtor<TargetPassConfig>), false, false); Registry
.registerPass(*PI, true); return PI; } static llvm::once_flag
InitializeTargetPassConfigPassFlag; void llvm::initializeTargetPassConfigPass
(PassRegistry &Registry) { llvm::call_once(InitializeTargetPassConfigPassFlag
, initializeTargetPassConfigPassOnce, std::ref(Registry)); }
277char TargetPassConfig::ID = 0;
278
279namespace {
280
281struct InsertedPass {
282 AnalysisID TargetPassID;
283 IdentifyingPassPtr InsertedPassID;
284 bool VerifyAfter;
285 bool PrintAfter;
286
287 InsertedPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID,
288 bool VerifyAfter, bool PrintAfter)
289 : TargetPassID(TargetPassID), InsertedPassID(InsertedPassID),
290 VerifyAfter(VerifyAfter), PrintAfter(PrintAfter) {}
291
292 Pass *getInsertedPass() const {
293 assert(InsertedPassID.isValid() && "Illegal Pass ID!")((InsertedPassID.isValid() && "Illegal Pass ID!") ? static_cast
<void> (0) : __assert_fail ("InsertedPassID.isValid() && \"Illegal Pass ID!\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/TargetPassConfig.cpp"
, 293, __PRETTY_FUNCTION__))
;
294 if (InsertedPassID.isInstance())
295 return InsertedPassID.getInstance();
296 Pass *NP = Pass::createPass(InsertedPassID.getID());
297 assert(NP && "Pass ID not registered")((NP && "Pass ID not registered") ? static_cast<void
> (0) : __assert_fail ("NP && \"Pass ID not registered\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/TargetPassConfig.cpp"
, 297, __PRETTY_FUNCTION__))
;
298 return NP;
299 }
300};
301
302} // end anonymous namespace
303
304namespace llvm {
305
306class PassConfigImpl {
307public:
308 // List of passes explicitly substituted by this target. Normally this is
309 // empty, but it is a convenient way to suppress or replace specific passes
310 // that are part of a standard pass pipeline without overridding the entire
311 // pipeline. This mechanism allows target options to inherit a standard pass's
312 // user interface. For example, a target may disable a standard pass by
313 // default by substituting a pass ID of zero, and the user may still enable
314 // that standard pass with an explicit command line option.
315 DenseMap<AnalysisID,IdentifyingPassPtr> TargetPasses;
316
317 /// Store the pairs of <AnalysisID, AnalysisID> of which the second pass
318 /// is inserted after each instance of the first one.
319 SmallVector<InsertedPass, 4> InsertedPasses;
320};
321
322} // end namespace llvm
323
324// Out of line virtual method.
325TargetPassConfig::~TargetPassConfig() {
326 delete Impl;
327}
328
329static const PassInfo *getPassInfo(StringRef PassName) {
330 if (PassName.empty())
331 return nullptr;
332
333 const PassRegistry &PR = *PassRegistry::getPassRegistry();
334 const PassInfo *PI = PR.getPassInfo(PassName);
335 if (!PI)
336 report_fatal_error(Twine('\"') + Twine(PassName) +
337 Twine("\" pass is not registered."));
338 return PI;
339}
340
341static AnalysisID getPassIDFromName(StringRef PassName) {
342 const PassInfo *PI = getPassInfo(PassName);
343 return PI ? PI->getTypeInfo() : nullptr;
344}
345
346void TargetPassConfig::setStartStopPasses() {
347 StartBefore = getPassIDFromName(StartBeforeOpt);
348 StartAfter = getPassIDFromName(StartAfterOpt);
349 StopBefore = getPassIDFromName(StopBeforeOpt);
350 StopAfter = getPassIDFromName(StopAfterOpt);
351 if (StartBefore && StartAfter)
352 report_fatal_error(Twine(StartBeforeOptName) + Twine(" and ") +
353 Twine(StartAfterOptName) + Twine(" specified!"));
354 if (StopBefore && StopAfter)
355 report_fatal_error(Twine(StopBeforeOptName) + Twine(" and ") +
356 Twine(StopAfterOptName) + Twine(" specified!"));
357 Started = (StartAfter == nullptr) && (StartBefore == nullptr);
358}
359
360// Out of line constructor provides default values for pass options and
361// registers all common codegen passes.
362TargetPassConfig::TargetPassConfig(LLVMTargetMachine &TM, PassManagerBase &pm)
363 : ImmutablePass(ID), PM(&pm), TM(&TM) {
364 Impl = new PassConfigImpl();
365
366 // Register all target independent codegen passes to activate their PassIDs,
367 // including this pass itself.
368 initializeCodeGen(*PassRegistry::getPassRegistry());
369
370 // Also register alias analysis passes required by codegen passes.
371 initializeBasicAAWrapperPassPass(*PassRegistry::getPassRegistry());
372 initializeAAResultsWrapperPassPass(*PassRegistry::getPassRegistry());
373
374 if (StringRef(PrintMachineInstrs.getValue()).equals(""))
375 TM.Options.PrintMachineCode = true;
376
377 if (EnableIPRA.getNumOccurrences())
378 TM.Options.EnableIPRA = EnableIPRA;
379 else {
380 // If not explicitly specified, use target default.
381 TM.Options.EnableIPRA = TM.useIPRA();
382 }
383
384 if (TM.Options.EnableIPRA)
385 setRequiresCodeGenSCCOrder();
386
387 setStartStopPasses();
388}
389
390CodeGenOpt::Level TargetPassConfig::getOptLevel() const {
391 return TM->getOptLevel();
392}
393
394/// Insert InsertedPassID pass after TargetPassID.
395void TargetPassConfig::insertPass(AnalysisID TargetPassID,
396 IdentifyingPassPtr InsertedPassID,
397 bool VerifyAfter, bool PrintAfter) {
398 assert(((!InsertedPassID.isInstance() &&((((!InsertedPassID.isInstance() && TargetPassID != InsertedPassID
.getID()) || (InsertedPassID.isInstance() && TargetPassID
!= InsertedPassID.getInstance()->getPassID())) &&
"Insert a pass after itself!") ? static_cast<void> (0)
: __assert_fail ("((!InsertedPassID.isInstance() && TargetPassID != InsertedPassID.getID()) || (InsertedPassID.isInstance() && TargetPassID != InsertedPassID.getInstance()->getPassID())) && \"Insert a pass after itself!\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/TargetPassConfig.cpp"
, 402, __PRETTY_FUNCTION__))
399 TargetPassID != InsertedPassID.getID()) ||((((!InsertedPassID.isInstance() && TargetPassID != InsertedPassID
.getID()) || (InsertedPassID.isInstance() && TargetPassID
!= InsertedPassID.getInstance()->getPassID())) &&
"Insert a pass after itself!") ? static_cast<void> (0)
: __assert_fail ("((!InsertedPassID.isInstance() && TargetPassID != InsertedPassID.getID()) || (InsertedPassID.isInstance() && TargetPassID != InsertedPassID.getInstance()->getPassID())) && \"Insert a pass after itself!\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/TargetPassConfig.cpp"
, 402, __PRETTY_FUNCTION__))
400 (InsertedPassID.isInstance() &&((((!InsertedPassID.isInstance() && TargetPassID != InsertedPassID
.getID()) || (InsertedPassID.isInstance() && TargetPassID
!= InsertedPassID.getInstance()->getPassID())) &&
"Insert a pass after itself!") ? static_cast<void> (0)
: __assert_fail ("((!InsertedPassID.isInstance() && TargetPassID != InsertedPassID.getID()) || (InsertedPassID.isInstance() && TargetPassID != InsertedPassID.getInstance()->getPassID())) && \"Insert a pass after itself!\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/TargetPassConfig.cpp"
, 402, __PRETTY_FUNCTION__))
401 TargetPassID != InsertedPassID.getInstance()->getPassID())) &&((((!InsertedPassID.isInstance() && TargetPassID != InsertedPassID
.getID()) || (InsertedPassID.isInstance() && TargetPassID
!= InsertedPassID.getInstance()->getPassID())) &&
"Insert a pass after itself!") ? static_cast<void> (0)
: __assert_fail ("((!InsertedPassID.isInstance() && TargetPassID != InsertedPassID.getID()) || (InsertedPassID.isInstance() && TargetPassID != InsertedPassID.getInstance()->getPassID())) && \"Insert a pass after itself!\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/TargetPassConfig.cpp"
, 402, __PRETTY_FUNCTION__))
402 "Insert a pass after itself!")((((!InsertedPassID.isInstance() && TargetPassID != InsertedPassID
.getID()) || (InsertedPassID.isInstance() && TargetPassID
!= InsertedPassID.getInstance()->getPassID())) &&
"Insert a pass after itself!") ? static_cast<void> (0)
: __assert_fail ("((!InsertedPassID.isInstance() && TargetPassID != InsertedPassID.getID()) || (InsertedPassID.isInstance() && TargetPassID != InsertedPassID.getInstance()->getPassID())) && \"Insert a pass after itself!\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/TargetPassConfig.cpp"
, 402, __PRETTY_FUNCTION__))
;
403 Impl->InsertedPasses.emplace_back(TargetPassID, InsertedPassID, VerifyAfter,
404 PrintAfter);
405}
406
407/// createPassConfig - Create a pass configuration object to be used by
408/// addPassToEmitX methods for generating a pipeline of CodeGen passes.
409///
410/// Targets may override this to extend TargetPassConfig.
411TargetPassConfig *LLVMTargetMachine::createPassConfig(PassManagerBase &PM) {
412 return new TargetPassConfig(*this, PM);
413}
414
415TargetPassConfig::TargetPassConfig()
416 : ImmutablePass(ID) {
417 report_fatal_error("Trying to construct TargetPassConfig without a target "
418 "machine. Scheduling a CodeGen pass without a target "
419 "triple set?");
420}
421
422bool TargetPassConfig::hasLimitedCodeGenPipeline() const {
423 return StartBefore || StartAfter || StopBefore || StopAfter;
424}
425
426std::string
427TargetPassConfig::getLimitedCodeGenPipelineReason(const char *Separator) const {
428 if (!hasLimitedCodeGenPipeline())
429 return std::string();
430 std::string Res;
431 static cl::opt<std::string> *PassNames[] = {&StartAfterOpt, &StartBeforeOpt,
432 &StopAfterOpt, &StopBeforeOpt};
433 static const char *OptNames[] = {StartAfterOptName, StartBeforeOptName,
434 StopAfterOptName, StopBeforeOptName};
435 bool IsFirst = true;
436 for (int Idx = 0; Idx < 4; ++Idx)
437 if (!PassNames[Idx]->empty()) {
438 if (!IsFirst)
439 Res += Separator;
440 IsFirst = false;
441 Res += OptNames[Idx];
442 }
443 return Res;
444}
445
446// Helper to verify the analysis is really immutable.
447void TargetPassConfig::setOpt(bool &Opt, bool Val) {
448 assert(!Initialized && "PassConfig is immutable")((!Initialized && "PassConfig is immutable") ? static_cast
<void> (0) : __assert_fail ("!Initialized && \"PassConfig is immutable\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/TargetPassConfig.cpp"
, 448, __PRETTY_FUNCTION__))
;
449 Opt = Val;
450}
451
452void TargetPassConfig::substitutePass(AnalysisID StandardID,
453 IdentifyingPassPtr TargetID) {
454 Impl->TargetPasses[StandardID] = TargetID;
455}
456
457IdentifyingPassPtr TargetPassConfig::getPassSubstitution(AnalysisID ID) const {
458 DenseMap<AnalysisID, IdentifyingPassPtr>::const_iterator
459 I = Impl->TargetPasses.find(ID);
460 if (I == Impl->TargetPasses.end())
461 return ID;
462 return I->second;
463}
464
465bool TargetPassConfig::isPassSubstitutedOrOverridden(AnalysisID ID) const {
466 IdentifyingPassPtr TargetID = getPassSubstitution(ID);
467 IdentifyingPassPtr FinalPtr = overridePass(ID, TargetID);
468 return !FinalPtr.isValid() || FinalPtr.isInstance() ||
469 FinalPtr.getID() != ID;
470}
471
472/// Add a pass to the PassManager if that pass is supposed to be run. If the
473/// Started/Stopped flags indicate either that the compilation should start at
474/// a later pass or that it should stop after an earlier pass, then do not add
475/// the pass. Finally, compare the current pass against the StartAfter
476/// and StopAfter options and change the Started/Stopped flags accordingly.
477void TargetPassConfig::addPass(Pass *P, bool verifyAfter, bool printAfter) {
478 assert(!Initialized && "PassConfig is immutable")((!Initialized && "PassConfig is immutable") ? static_cast
<void> (0) : __assert_fail ("!Initialized && \"PassConfig is immutable\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/TargetPassConfig.cpp"
, 478, __PRETTY_FUNCTION__))
;
479
480 // Cache the Pass ID here in case the pass manager finds this pass is
481 // redundant with ones already scheduled / available, and deletes it.
482 // Fundamentally, once we add the pass to the manager, we no longer own it
483 // and shouldn't reference it.
484 AnalysisID PassID = P->getPassID();
485
486 if (StartBefore == PassID)
487 Started = true;
488 if (StopBefore == PassID)
489 Stopped = true;
490 if (Started && !Stopped) {
491 std::string Banner;
492 // Construct banner message before PM->add() as that may delete the pass.
493 if (AddingMachinePasses && (printAfter || verifyAfter))
494 Banner = std::string("After ") + std::string(P->getPassName());
495 PM->add(P);
496 if (AddingMachinePasses) {
497 if (printAfter)
498 addPrintPass(Banner);
499 if (verifyAfter)
500 addVerifyPass(Banner);
501 }
502
503 // Add the passes after the pass P if there is any.
504 for (auto IP : Impl->InsertedPasses) {
505 if (IP.TargetPassID == PassID)
506 addPass(IP.getInsertedPass(), IP.VerifyAfter, IP.PrintAfter);
507 }
508 } else {
509 delete P;
510 }
511 if (StopAfter == PassID)
512 Stopped = true;
513 if (StartAfter == PassID)
514 Started = true;
515 if (Stopped && !Started)
516 report_fatal_error("Cannot stop compilation after pass that is not run");
517}
518
519/// Add a CodeGen pass at this point in the pipeline after checking for target
520/// and command line overrides.
521///
522/// addPass cannot return a pointer to the pass instance because is internal the
523/// PassManager and the instance we create here may already be freed.
524AnalysisID TargetPassConfig::addPass(AnalysisID PassID, bool verifyAfter,
525 bool printAfter) {
526 IdentifyingPassPtr TargetID = getPassSubstitution(PassID);
527 IdentifyingPassPtr FinalPtr = overridePass(PassID, TargetID);
528 if (!FinalPtr.isValid())
529 return nullptr;
530
531 Pass *P;
532 if (FinalPtr.isInstance())
533 P = FinalPtr.getInstance();
534 else {
535 P = Pass::createPass(FinalPtr.getID());
536 if (!P)
537 llvm_unreachable("Pass ID not registered")::llvm::llvm_unreachable_internal("Pass ID not registered", "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/TargetPassConfig.cpp"
, 537)
;
538 }
539 AnalysisID FinalID = P->getPassID();
540 addPass(P, verifyAfter, printAfter); // Ends the lifetime of P.
541
542 return FinalID;
543}
544
545void TargetPassConfig::printAndVerify(const std::string &Banner) {
546 addPrintPass(Banner);
547 addVerifyPass(Banner);
548}
549
550void TargetPassConfig::addPrintPass(const std::string &Banner) {
551 if (TM->shouldPrintMachineCode())
552 PM->add(createMachineFunctionPrinterPass(dbgs(), Banner));
553}
554
555void TargetPassConfig::addVerifyPass(const std::string &Banner) {
556 bool Verify = VerifyMachineCode == cl::BOU_TRUE;
557#ifdef EXPENSIVE_CHECKS
558 if (VerifyMachineCode == cl::BOU_UNSET)
559 Verify = TM->isMachineVerifierClean();
560#endif
561 if (Verify)
562 PM->add(createMachineVerifierPass(Banner));
563}
564
565/// Add common target configurable passes that perform LLVM IR to IR transforms
566/// following machine independent optimization.
567void TargetPassConfig::addIRPasses() {
568 switch (UseCFLAA) {
569 case CFLAAType::Steensgaard:
570 addPass(createCFLSteensAAWrapperPass());
571 break;
572 case CFLAAType::Andersen:
573 addPass(createCFLAndersAAWrapperPass());
574 break;
575 case CFLAAType::Both:
576 addPass(createCFLAndersAAWrapperPass());
577 addPass(createCFLSteensAAWrapperPass());
578 break;
579 default:
580 break;
581 }
582
583 // Basic AliasAnalysis support.
584 // Add TypeBasedAliasAnalysis before BasicAliasAnalysis so that
585 // BasicAliasAnalysis wins if they disagree. This is intended to help
586 // support "obvious" type-punning idioms.
587 addPass(createTypeBasedAAWrapperPass());
588 addPass(createScopedNoAliasAAWrapperPass());
589 addPass(createBasicAAWrapperPass());
590
591 // Before running any passes, run the verifier to determine if the input
592 // coming from the front-end and/or optimizer is valid.
593 if (!DisableVerify)
594 addPass(createVerifierPass());
595
596 // Run loop strength reduction before anything else.
597 if (getOptLevel() != CodeGenOpt::None && !DisableLSR) {
598 addPass(createLoopStrengthReducePass());
599 if (PrintLSR)
600 addPass(createPrintFunctionPass(dbgs(), "\n\n*** Code after LSR ***\n"));
601 }
602
603 if (getOptLevel() != CodeGenOpt::None) {
604 // The MergeICmpsPass tries to create memcmp calls by grouping sequences of
605 // loads and compares. ExpandMemCmpPass then tries to expand those calls
606 // into optimally-sized loads and compares. The transforms are enabled by a
607 // target lowering hook.
608 if (!DisableMergeICmps)
609 addPass(createMergeICmpsPass());
610 addPass(createExpandMemCmpPass());
611 }
612
613 // Run GC lowering passes for builtin collectors
614 // TODO: add a pass insertion point here
615 addPass(createGCLoweringPass());
616 addPass(createShadowStackGCLoweringPass());
617
618 // Make sure that no unreachable blocks are instruction selected.
619 addPass(createUnreachableBlockEliminationPass());
620
621 // Prepare expensive constants for SelectionDAG.
622 if (getOptLevel() != CodeGenOpt::None && !DisableConstantHoisting)
623 addPass(createConstantHoistingPass());
624
625 if (getOptLevel() != CodeGenOpt::None && !DisablePartialLibcallInlining)
626 addPass(createPartiallyInlineLibCallsPass());
627
628 // Instrument function entry and exit, e.g. with calls to mcount().
629 addPass(createPostInlineEntryExitInstrumenterPass());
630
631 // Add scalarization of target's unsupported masked memory intrinsics pass.
632 // the unsupported intrinsic will be replaced with a chain of basic blocks,
633 // that stores/loads element one-by-one if the appropriate mask bit is set.
634 addPass(createScalarizeMaskedMemIntrinPass());
635
636 // Expand reduction intrinsics into shuffle sequences if the target wants to.
637 addPass(createExpandReductionsPass());
638}
639
640/// Turn exception handling constructs into something the code generators can
641/// handle.
642void TargetPassConfig::addPassesToHandleExceptions() {
643 const MCAsmInfo *MCAI = TM->getMCAsmInfo();
644 assert(MCAI && "No MCAsmInfo")((MCAI && "No MCAsmInfo") ? static_cast<void> (
0) : __assert_fail ("MCAI && \"No MCAsmInfo\"", "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/TargetPassConfig.cpp"
, 644, __PRETTY_FUNCTION__))
;
645 switch (MCAI->getExceptionHandlingType()) {
646 case ExceptionHandling::SjLj:
647 // SjLj piggy-backs on dwarf for this bit. The cleanups done apply to both
648 // Dwarf EH prepare needs to be run after SjLj prepare. Otherwise,
649 // catch info can get misplaced when a selector ends up more than one block
650 // removed from the parent invoke(s). This could happen when a landing
651 // pad is shared by multiple invokes and is also a target of a normal
652 // edge from elsewhere.
653 addPass(createSjLjEHPreparePass());
654 LLVM_FALLTHROUGH[[clang::fallthrough]];
655 case ExceptionHandling::DwarfCFI:
656 case ExceptionHandling::ARM:
657 addPass(createDwarfEHPass());
658 break;
659 case ExceptionHandling::WinEH:
660 // We support using both GCC-style and MSVC-style exceptions on Windows, so
661 // add both preparation passes. Each pass will only actually run if it
662 // recognizes the personality function.
663 addPass(createWinEHPass());
664 addPass(createDwarfEHPass());
665 break;
666 case ExceptionHandling::Wasm:
667 // Wasm EH uses Windows EH instructions, but it does not need to demote PHIs
668 // on catchpads and cleanuppads because it does not outline them into
669 // funclets. Catchswitch blocks are not lowered in SelectionDAG, so we
670 // should remove PHIs there.
671 addPass(createWinEHPass(/*DemoteCatchSwitchPHIOnly=*/false));
672 addPass(createWasmEHPass());
673 break;
674 case ExceptionHandling::None:
675 addPass(createLowerInvokePass());
676
677 // The lower invoke pass may create unreachable code. Remove it.
678 addPass(createUnreachableBlockEliminationPass());
679 break;
680 }
681}
682
683/// Add pass to prepare the LLVM IR for code generation. This should be done
684/// before exception handling preparation passes.
685void TargetPassConfig::addCodeGenPrepare() {
686 if (getOptLevel() != CodeGenOpt::None && !DisableCGP)
687 addPass(createCodeGenPreparePass());
688 addPass(createRewriteSymbolsPass());
689}
690
691/// Add common passes that perform LLVM IR to IR transforms in preparation for
692/// instruction selection.
693void TargetPassConfig::addISelPrepare() {
694 addPreISel();
695
696 // Force codegen to run according to the callgraph.
697 if (requiresCodeGenSCCOrder())
698 addPass(new DummyCGSCCPass);
699
700 // Add both the safe stack and the stack protection passes: each of them will
701 // only protect functions that have corresponding attributes.
702 addPass(createSafeStackPass());
703 addPass(createStackProtectorPass());
704
705 if (PrintISelInput)
706 addPass(createPrintFunctionPass(
707 dbgs(), "\n\n*** Final LLVM Code input to ISel ***\n"));
708
709 // All passes which modify the LLVM IR are now complete; run the verifier
710 // to ensure that the IR is valid.
711 if (!DisableVerify)
712 addPass(createVerifierPass());
713}
714
715bool TargetPassConfig::addCoreISelPasses() {
716 // Enable FastISel with -fast-isel, but allow that to be overridden.
717 TM->setO0WantsFastISel(EnableFastISelOption != cl::BOU_FALSE);
718 if (EnableFastISelOption == cl::BOU_TRUE ||
719 (TM->getOptLevel() == CodeGenOpt::None && TM->getO0WantsFastISel()))
720 TM->setFastISel(true);
721
722 // Ask the target for an instruction selector.
723 // Explicitly enabling fast-isel should override implicitly enabled
724 // global-isel.
725 if (EnableGlobalISelOption == cl::BOU_TRUE ||
726 (EnableGlobalISelOption == cl::BOU_UNSET &&
727 TM->Options.EnableGlobalISel && EnableFastISelOption != cl::BOU_TRUE)) {
728 TM->setFastISel(false);
729
730 SaveAndRestore<bool> SavedAddingMachinePasses(AddingMachinePasses, true);
731 if (addIRTranslator())
732 return true;
733
734 addPreLegalizeMachineIR();
735
736 if (addLegalizeMachineIR())
737 return true;
738
739 // Before running the register bank selector, ask the target if it
740 // wants to run some passes.
741 addPreRegBankSelect();
742
743 if (addRegBankSelect())
744 return true;
745
746 addPreGlobalInstructionSelect();
747
748 if (addGlobalInstructionSelect())
749 return true;
750
751 // Pass to reset the MachineFunction if the ISel failed.
752 addPass(createResetMachineFunctionPass(
753 reportDiagnosticWhenGlobalISelFallback(), isGlobalISelAbortEnabled()));
754
755 // Provide a fallback path when we do not want to abort on
756 // not-yet-supported input.
757 if (!isGlobalISelAbortEnabled() && addInstSelector())
758 return true;
759
760 } else if (addInstSelector())
761 return true;
762
763 return false;
764}
765
766bool TargetPassConfig::addISelPasses() {
767 if (TM->useEmulatedTLS())
768 addPass(createLowerEmuTLSPass());
769
770 addPass(createPreISelIntrinsicLoweringPass());
771 addPass(createTargetTransformInfoWrapperPass(TM->getTargetIRAnalysis()));
772 addIRPasses();
773 addCodeGenPrepare();
774 addPassesToHandleExceptions();
775 addISelPrepare();
776
777 return addCoreISelPasses();
778}
779
780/// -regalloc=... command line option.
781static FunctionPass *useDefaultRegisterAllocator() { return nullptr; }
782static cl::opt<RegisterRegAlloc::FunctionPassCtor, false,
783 RegisterPassParser<RegisterRegAlloc>>
784 RegAlloc("regalloc", cl::Hidden, cl::init(&useDefaultRegisterAllocator),
785 cl::desc("Register allocator to use"));
786
787/// Add the complete set of target-independent postISel code generator passes.
788///
789/// This can be read as the standard order of major LLVM CodeGen stages. Stages
790/// with nontrivial configuration or multiple passes are broken out below in
791/// add%Stage routines.
792///
793/// Any TargetPassConfig::addXX routine may be overriden by the Target. The
794/// addPre/Post methods with empty header implementations allow injecting
795/// target-specific fixups just before or after major stages. Additionally,
796/// targets have the flexibility to change pass order within a stage by
797/// overriding default implementation of add%Stage routines below. Each
798/// technique has maintainability tradeoffs because alternate pass orders are
799/// not well supported. addPre/Post works better if the target pass is easily
800/// tied to a common pass. But if it has subtle dependencies on multiple passes,
801/// the target should override the stage instead.
802///
803/// TODO: We could use a single addPre/Post(ID) hook to allow pass injection
804/// before/after any target-independent pass. But it's currently overkill.
805void TargetPassConfig::addMachinePasses() {
806 AddingMachinePasses = true;
807
808 // Insert a machine instr printer pass after the specified pass.
809 if (!StringRef(PrintMachineInstrs.getValue()).equals("") &&
810 !StringRef(PrintMachineInstrs.getValue()).equals("option-unspecified")) {
811 const PassRegistry *PR = PassRegistry::getPassRegistry();
812 const PassInfo *TPI = PR->getPassInfo(PrintMachineInstrs.getValue());
813 const PassInfo *IPI = PR->getPassInfo(StringRef("machineinstr-printer"));
814 assert (TPI && IPI && "Pass ID not registered!")((TPI && IPI && "Pass ID not registered!") ? static_cast
<void> (0) : __assert_fail ("TPI && IPI && \"Pass ID not registered!\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/TargetPassConfig.cpp"
, 814, __PRETTY_FUNCTION__))
;
815 const char *TID = (const char *)(TPI->getTypeInfo());
816 const char *IID = (const char *)(IPI->getTypeInfo());
817 insertPass(TID, IID);
818 }
819
820 // Print the instruction selected machine code...
821 printAndVerify("After Instruction Selection");
822
823 // Expand pseudo-instructions emitted by ISel.
824 addPass(&ExpandISelPseudosID);
825
826 // Add passes that optimize machine instructions in SSA form.
827 if (getOptLevel() != CodeGenOpt::None) {
828 addMachineSSAOptimization();
829 } else {
830 // If the target requests it, assign local variables to stack slots relative
831 // to one another and simplify frame index references where possible.
832 addPass(&LocalStackSlotAllocationID, false);
833 }
834
835 if (TM->Options.EnableIPRA)
836 addPass(createRegUsageInfoPropPass());
837
838 // Run pre-ra passes.
839 addPreRegAlloc();
840
841 // Run register allocation and passes that are tightly coupled with it,
842 // including phi elimination and scheduling.
843 if (getOptimizeRegAlloc())
844 addOptimizedRegAlloc(createRegAllocPass(true));
845 else {
846 if (RegAlloc != &useDefaultRegisterAllocator &&
847 RegAlloc != &createFastRegisterAllocator)
848 report_fatal_error("Must use fast (default) register allocator for unoptimized regalloc.");
849 addFastRegAlloc(createRegAllocPass(false));
850 }
851
852 // Run post-ra passes.
853 addPostRegAlloc();
854
855 // Insert prolog/epilog code. Eliminate abstract frame index references...
856 if (getOptLevel() != CodeGenOpt::None) {
857 addPass(&PostRAMachineSinkingID);
858 addPass(&ShrinkWrapID);
859 }
860
861 // Prolog/Epilog inserter needs a TargetMachine to instantiate. But only
862 // do so if it hasn't been disabled, substituted, or overridden.
863 if (!isPassSubstitutedOrOverridden(&PrologEpilogCodeInserterID))
864 addPass(createPrologEpilogInserterPass());
865
866 /// Add passes that optimize machine instructions after register allocation.
867 if (getOptLevel() != CodeGenOpt::None)
868 addMachineLateOptimization();
869
870 // Expand pseudo instructions before second scheduling pass.
871 addPass(&ExpandPostRAPseudosID);
872
873 // Run pre-sched2 passes.
874 addPreSched2();
875
876 if (EnableImplicitNullChecks)
877 addPass(&ImplicitNullChecksID);
878
879 // Second pass scheduler.
880 // Let Target optionally insert this pass by itself at some other
881 // point.
882 if (getOptLevel() != CodeGenOpt::None &&
883 !TM->targetSchedulesPostRAScheduling()) {
884 if (MISchedPostRA)
885 addPass(&PostMachineSchedulerID);
886 else
887 addPass(&PostRASchedulerID);
888 }
889
890 // GC
891 if (addGCPasses()) {
892 if (PrintGCInfo)
893 addPass(createGCInfoPrinter(dbgs()), false, false);
894 }
895
896 // Basic block placement.
897 if (getOptLevel() != CodeGenOpt::None)
898 addBlockPlacement();
899
900 addPreEmitPass();
901
902 if (TM->Options.EnableIPRA)
903 // Collect register usage information and produce a register mask of
904 // clobbered registers, to be used to optimize call sites.
905 addPass(createRegUsageInfoCollector());
906
907 addPass(&FuncletLayoutID, false);
908
909 addPass(&StackMapLivenessID, false);
910 addPass(&LiveDebugValuesID, false);
911
912 // Insert before XRay Instrumentation.
913 addPass(&FEntryInserterID, false);
914
915 addPass(&XRayInstrumentationID, false);
916 addPass(&PatchableFunctionID, false);
917
918 if (TM->Options.EnableMachineOutliner && getOptLevel() != CodeGenOpt::None &&
919 EnableMachineOutliner != NeverOutline) {
920 bool RunOnAllFunctions = (EnableMachineOutliner == AlwaysOutline);
921 bool AddOutliner = RunOnAllFunctions ||
922 TM->Options.SupportsDefaultOutlining;
923 if (AddOutliner)
924 addPass(createMachineOutlinerPass(RunOnAllFunctions));
925 }
926
927 // Add passes that directly emit MI after all other MI passes.
928 addPreEmitPass2();
929
930 AddingMachinePasses = false;
931}
932
933/// Add passes that optimize machine instructions in SSA form.
934void TargetPassConfig::addMachineSSAOptimization() {
935 // Pre-ra tail duplication.
936 addPass(&EarlyTailDuplicateID);
937
938 // Optimize PHIs before DCE: removing dead PHI cycles may make more
939 // instructions dead.
940 addPass(&OptimizePHIsID, false);
941
942 // This pass merges large allocas. StackSlotColoring is a different pass
943 // which merges spill slots.
944 addPass(&StackColoringID, false);
945
946 // If the target requests it, assign local variables to stack slots relative
947 // to one another and simplify frame index references where possible.
948 addPass(&LocalStackSlotAllocationID, false);
949
950 // With optimization, dead code should already be eliminated. However
951 // there is one known exception: lowered code for arguments that are only
952 // used by tail calls, where the tail calls reuse the incoming stack
953 // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
954 addPass(&DeadMachineInstructionElimID);
955
956 // Allow targets to insert passes that improve instruction level parallelism,
957 // like if-conversion. Such passes will typically need dominator trees and
958 // loop info, just like LICM and CSE below.
959 addILPOpts();
960
961 addPass(&EarlyMachineLICMID, false);
962 addPass(&MachineCSEID, false);
963
964 addPass(&MachineSinkingID);
965
966 addPass(&PeepholeOptimizerID);
967 // Clean-up the dead code that may have been generated by peephole
968 // rewriting.
969 addPass(&DeadMachineInstructionElimID);
970}
971
972//===---------------------------------------------------------------------===//
973/// Register Allocation Pass Configuration
974//===---------------------------------------------------------------------===//
975
976bool TargetPassConfig::getOptimizeRegAlloc() const {
977 switch (OptimizeRegAlloc) {
978 case cl::BOU_UNSET: return getOptLevel() != CodeGenOpt::None;
979 case cl::BOU_TRUE: return true;
980 case cl::BOU_FALSE: return false;
981 }
982 llvm_unreachable("Invalid optimize-regalloc state")::llvm::llvm_unreachable_internal("Invalid optimize-regalloc state"
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/TargetPassConfig.cpp"
, 982)
;
983}
984
985/// RegisterRegAlloc's global Registry tracks allocator registration.
986MachinePassRegistry RegisterRegAlloc::Registry;
987
988/// A dummy default pass factory indicates whether the register allocator is
989/// overridden on the command line.
990static llvm::once_flag InitializeDefaultRegisterAllocatorFlag;
991
992static RegisterRegAlloc
993defaultRegAlloc("default",
994 "pick register allocator based on -O option",
995 useDefaultRegisterAllocator);
996
997static void initializeDefaultRegisterAllocatorOnce() {
998 RegisterRegAlloc::FunctionPassCtor Ctor = RegisterRegAlloc::getDefault();
999
1000 if (!Ctor) {
1001 Ctor = RegAlloc;
Value stored to 'Ctor' is never read
1002 RegisterRegAlloc::setDefault(RegAlloc);
1003 }
1004}
1005
1006/// Instantiate the default register allocator pass for this target for either
1007/// the optimized or unoptimized allocation path. This will be added to the pass
1008/// manager by addFastRegAlloc in the unoptimized case or addOptimizedRegAlloc
1009/// in the optimized case.
1010///
1011/// A target that uses the standard regalloc pass order for fast or optimized
1012/// allocation may still override this for per-target regalloc
1013/// selection. But -regalloc=... always takes precedence.
1014FunctionPass *TargetPassConfig::createTargetRegisterAllocator(bool Optimized) {
1015 if (Optimized)
1016 return createGreedyRegisterAllocator();
1017 else
1018 return createFastRegisterAllocator();
1019}
1020
1021/// Find and instantiate the register allocation pass requested by this target
1022/// at the current optimization level. Different register allocators are
1023/// defined as separate passes because they may require different analysis.
1024///
1025/// This helper ensures that the regalloc= option is always available,
1026/// even for targets that override the default allocator.
1027///
1028/// FIXME: When MachinePassRegistry register pass IDs instead of function ptrs,
1029/// this can be folded into addPass.
1030FunctionPass *TargetPassConfig::createRegAllocPass(bool Optimized) {
1031 // Initialize the global default.
1032 llvm::call_once(InitializeDefaultRegisterAllocatorFlag,
1033 initializeDefaultRegisterAllocatorOnce);
1034
1035 RegisterRegAlloc::FunctionPassCtor Ctor = RegisterRegAlloc::getDefault();
1036 if (Ctor != useDefaultRegisterAllocator)
1037 return Ctor();
1038
1039 // With no -regalloc= override, ask the target for a regalloc pass.
1040 return createTargetRegisterAllocator(Optimized);
1041}
1042
1043/// Return true if the default global register allocator is in use and
1044/// has not be overriden on the command line with '-regalloc=...'
1045bool TargetPassConfig::usingDefaultRegAlloc() const {
1046 return RegAlloc.getNumOccurrences() == 0;
1047}
1048
1049/// Add the minimum set of target-independent passes that are required for
1050/// register allocation. No coalescing or scheduling.
1051void TargetPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
1052 addPass(&PHIEliminationID, false);
1053 addPass(&TwoAddressInstructionPassID, false);
1054
1055 if (RegAllocPass)
1056 addPass(RegAllocPass);
1057}
1058
1059/// Add standard target-independent passes that are tightly coupled with
1060/// optimized register allocation, including coalescing, machine instruction
1061/// scheduling, and register allocation itself.
1062void TargetPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
1063 addPass(&DetectDeadLanesID, false);
1064
1065 addPass(&ProcessImplicitDefsID, false);
1066
1067 // LiveVariables currently requires pure SSA form.
1068 //
1069 // FIXME: Once TwoAddressInstruction pass no longer uses kill flags,
1070 // LiveVariables can be removed completely, and LiveIntervals can be directly
1071 // computed. (We still either need to regenerate kill flags after regalloc, or
1072 // preferably fix the scavenger to not depend on them).
1073 addPass(&LiveVariablesID, false);
1074
1075 // Edge splitting is smarter with machine loop info.
1076 addPass(&MachineLoopInfoID, false);
1077 addPass(&PHIEliminationID, false);
1078
1079 // Eventually, we want to run LiveIntervals before PHI elimination.
1080 if (EarlyLiveIntervals)
1081 addPass(&LiveIntervalsID, false);
1082
1083 addPass(&TwoAddressInstructionPassID, false);
1084 addPass(&RegisterCoalescerID);
1085
1086 // The machine scheduler may accidentally create disconnected components
1087 // when moving subregister definitions around, avoid this by splitting them to
1088 // separate vregs before. Splitting can also improve reg. allocation quality.
1089 addPass(&RenameIndependentSubregsID);
1090
1091 // PreRA instruction scheduling.
1092 addPass(&MachineSchedulerID);
1093
1094 if (RegAllocPass) {
1095 // Add the selected register allocation pass.
1096 addPass(RegAllocPass);
1097
1098 // Allow targets to change the register assignments before rewriting.
1099 addPreRewrite();
1100
1101 // Finally rewrite virtual registers.
1102 addPass(&VirtRegRewriterID);
1103
1104 // Perform stack slot coloring and post-ra machine LICM.
1105 //
1106 // FIXME: Re-enable coloring with register when it's capable of adding
1107 // kill markers.
1108 addPass(&StackSlotColoringID);
1109
1110 // Copy propagate to forward register uses and try to eliminate COPYs that
1111 // were not coalesced.
1112 addPass(&MachineCopyPropagationID);
1113
1114 // Run post-ra machine LICM to hoist reloads / remats.
1115 //
1116 // FIXME: can this move into MachineLateOptimization?
1117 addPass(&MachineLICMID);
1118 }
1119}
1120
1121//===---------------------------------------------------------------------===//
1122/// Post RegAlloc Pass Configuration
1123//===---------------------------------------------------------------------===//
1124
1125/// Add passes that optimize machine instructions after register allocation.
1126void TargetPassConfig::addMachineLateOptimization() {
1127 // Branch folding must be run after regalloc and prolog/epilog insertion.
1128 addPass(&BranchFolderPassID);
1129
1130 // Tail duplication.
1131 // Note that duplicating tail just increases code size and degrades
1132 // performance for targets that require Structured Control Flow.
1133 // In addition it can also make CFG irreducible. Thus we disable it.
1134 if (!TM->requiresStructuredCFG())
1135 addPass(&TailDuplicateID);
1136
1137 // Copy propagation.
1138 addPass(&MachineCopyPropagationID);
1139}
1140
1141/// Add standard GC passes.
1142bool TargetPassConfig::addGCPasses() {
1143 addPass(&GCMachineCodeAnalysisID, false);
1144 return true;
1145}
1146
1147/// Add standard basic block placement passes.
1148void TargetPassConfig::addBlockPlacement() {
1149 if (addPass(&MachineBlockPlacementID)) {
1150 // Run a separate pass to collect block placement statistics.
1151 if (EnableBlockPlacementStats)
1152 addPass(&MachineBlockPlacementStatsID);
1153 }
1154}
1155
1156//===---------------------------------------------------------------------===//
1157/// GlobalISel Configuration
1158//===---------------------------------------------------------------------===//
1159bool TargetPassConfig::isGlobalISelAbortEnabled() const {
1160 if (EnableGlobalISelAbort.getNumOccurrences() > 0)
1161 return EnableGlobalISelAbort == 1;
1162
1163 // When no abort behaviour is specified, we don't abort if the target says
1164 // that GISel is enabled.
1165 return !TM->Options.EnableGlobalISel;
1166}
1167
1168bool TargetPassConfig::reportDiagnosticWhenGlobalISelFallback() const {
1169 return EnableGlobalISelAbort == 2;
1170}