Bug Summary

File:lib/CodeGen/TargetPassConfig.cpp
Warning:line 783, column 5
Value stored to 'Ctor' is never read

Annotated Source Code

1//===-- TargetPassConfig.cpp - Target independent code generation passes --===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines interfaces to access the target independent code
11// generation passes provided by the LLVM backend.
12//
13//===---------------------------------------------------------------------===//
14
15#include "llvm/CodeGen/TargetPassConfig.h"
16
17#include "llvm/Analysis/BasicAliasAnalysis.h"
18#include "llvm/Analysis/CFLAndersAliasAnalysis.h"
19#include "llvm/Analysis/CFLSteensAliasAnalysis.h"
20#include "llvm/Analysis/CallGraphSCCPass.h"
21#include "llvm/Analysis/Passes.h"
22#include "llvm/Analysis/ScopedNoAliasAA.h"
23#include "llvm/Analysis/TypeBasedAliasAnalysis.h"
24#include "llvm/CodeGen/MachineFunctionPass.h"
25#include "llvm/CodeGen/RegAllocRegistry.h"
26#include "llvm/CodeGen/RegisterUsageInfo.h"
27#include "llvm/IR/IRPrintingPasses.h"
28#include "llvm/IR/LegacyPassManager.h"
29#include "llvm/IR/Verifier.h"
30#include "llvm/MC/MCAsmInfo.h"
31#include "llvm/Support/Debug.h"
32#include "llvm/Support/ErrorHandling.h"
33#include "llvm/Support/raw_ostream.h"
34#include "llvm/Target/TargetMachine.h"
35#include "llvm/Transforms/Instrumentation.h"
36#include "llvm/Transforms/Scalar.h"
37#include "llvm/Transforms/Utils/SymbolRewriter.h"
38
39using namespace llvm;
40
41static cl::opt<bool> DisablePostRASched("disable-post-ra", cl::Hidden,
42 cl::desc("Disable Post Regalloc Scheduler"));
43static cl::opt<bool> DisableBranchFold("disable-branch-fold", cl::Hidden,
44 cl::desc("Disable branch folding"));
45static cl::opt<bool> DisableTailDuplicate("disable-tail-duplicate", cl::Hidden,
46 cl::desc("Disable tail duplication"));
47static cl::opt<bool> DisableEarlyTailDup("disable-early-taildup", cl::Hidden,
48 cl::desc("Disable pre-register allocation tail duplication"));
49static cl::opt<bool> DisableBlockPlacement("disable-block-placement",
50 cl::Hidden, cl::desc("Disable probability-driven block placement"));
51static cl::opt<bool> EnableBlockPlacementStats("enable-block-placement-stats",
52 cl::Hidden, cl::desc("Collect probability-driven block placement stats"));
53static cl::opt<bool> DisableSSC("disable-ssc", cl::Hidden,
54 cl::desc("Disable Stack Slot Coloring"));
55static cl::opt<bool> DisableMachineDCE("disable-machine-dce", cl::Hidden,
56 cl::desc("Disable Machine Dead Code Elimination"));
57static cl::opt<bool> DisableEarlyIfConversion("disable-early-ifcvt", cl::Hidden,
58 cl::desc("Disable Early If-conversion"));
59static cl::opt<bool> DisableMachineLICM("disable-machine-licm", cl::Hidden,
60 cl::desc("Disable Machine LICM"));
61static cl::opt<bool> DisableMachineCSE("disable-machine-cse", cl::Hidden,
62 cl::desc("Disable Machine Common Subexpression Elimination"));
63static cl::opt<cl::boolOrDefault> OptimizeRegAlloc(
64 "optimize-regalloc", cl::Hidden,
65 cl::desc("Enable optimized register allocation compilation path."));
66static cl::opt<bool> DisablePostRAMachineLICM("disable-postra-machine-licm",
67 cl::Hidden,
68 cl::desc("Disable Machine LICM"));
69static cl::opt<bool> DisableMachineSink("disable-machine-sink", cl::Hidden,
70 cl::desc("Disable Machine Sinking"));
71static cl::opt<bool> DisableLSR("disable-lsr", cl::Hidden,
72 cl::desc("Disable Loop Strength Reduction Pass"));
73static cl::opt<bool> DisableConstantHoisting("disable-constant-hoisting",
74 cl::Hidden, cl::desc("Disable ConstantHoisting"));
75static cl::opt<bool> DisableCGP("disable-cgp", cl::Hidden,
76 cl::desc("Disable Codegen Prepare"));
77static cl::opt<bool> DisableCopyProp("disable-copyprop", cl::Hidden,
78 cl::desc("Disable Copy Propagation pass"));
79static cl::opt<bool> DisablePartialLibcallInlining("disable-partial-libcall-inlining",
80 cl::Hidden, cl::desc("Disable Partial Libcall Inlining"));
81static cl::opt<bool> EnableImplicitNullChecks(
82 "enable-implicit-null-checks",
83 cl::desc("Fold null checks into faulting memory operations"),
84 cl::init(false));
85static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
86 cl::desc("Print LLVM IR produced by the loop-reduce pass"));
87static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
88 cl::desc("Print LLVM IR input to isel pass"));
89static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden,
90 cl::desc("Dump garbage collector data"));
91static cl::opt<bool> VerifyMachineCode("verify-machineinstrs", cl::Hidden,
92 cl::desc("Verify generated machine code"),
93 cl::init(false),
94 cl::ZeroOrMore);
95static cl::opt<bool> EnableMachineOutliner("enable-machine-outliner",
96 cl::Hidden,
97 cl::desc("Enable machine outliner"));
98
99static cl::opt<std::string>
100PrintMachineInstrs("print-machineinstrs", cl::ValueOptional,
101 cl::desc("Print machine instrs"),
102 cl::value_desc("pass-name"), cl::init("option-unspecified"));
103
104static cl::opt<int> EnableGlobalISelAbort(
105 "global-isel-abort", cl::Hidden,
106 cl::desc("Enable abort calls when \"global\" instruction selection "
107 "fails to lower/select an instruction: 0 disable the abort, "
108 "1 enable the abort, and "
109 "2 disable the abort but emit a diagnostic on failure"),
110 cl::init(1));
111
112// Temporary option to allow experimenting with MachineScheduler as a post-RA
113// scheduler. Targets can "properly" enable this with
114// substitutePass(&PostRASchedulerID, &PostMachineSchedulerID).
115// Targets can return true in targetSchedulesPostRAScheduling() and
116// insert a PostRA scheduling pass wherever it wants.
117cl::opt<bool> MISchedPostRA("misched-postra", cl::Hidden,
118 cl::desc("Run MachineScheduler post regalloc (independent of preRA sched)"));
119
120// Experimental option to run live interval analysis early.
121static cl::opt<bool> EarlyLiveIntervals("early-live-intervals", cl::Hidden,
122 cl::desc("Run live interval analysis earlier in the pipeline"));
123
124// Experimental option to use CFL-AA in codegen
125enum class CFLAAType { None, Steensgaard, Andersen, Both };
126static cl::opt<CFLAAType> UseCFLAA(
127 "use-cfl-aa-in-codegen", cl::init(CFLAAType::None), cl::Hidden,
128 cl::desc("Enable the new, experimental CFL alias analysis in CodeGen"),
129 cl::values(clEnumValN(CFLAAType::None, "none", "Disable CFL-AA")llvm::cl::OptionEnumValue { "none", int(CFLAAType::None), "Disable CFL-AA"
}
,
130 clEnumValN(CFLAAType::Steensgaard, "steens",llvm::cl::OptionEnumValue { "steens", int(CFLAAType::Steensgaard
), "Enable unification-based CFL-AA" }
131 "Enable unification-based CFL-AA")llvm::cl::OptionEnumValue { "steens", int(CFLAAType::Steensgaard
), "Enable unification-based CFL-AA" }
,
132 clEnumValN(CFLAAType::Andersen, "anders",llvm::cl::OptionEnumValue { "anders", int(CFLAAType::Andersen
), "Enable inclusion-based CFL-AA" }
133 "Enable inclusion-based CFL-AA")llvm::cl::OptionEnumValue { "anders", int(CFLAAType::Andersen
), "Enable inclusion-based CFL-AA" }
,
134 clEnumValN(CFLAAType::Both, "both",llvm::cl::OptionEnumValue { "both", int(CFLAAType::Both), "Enable both variants of CFL-AA"
}
135 "Enable both variants of CFL-AA")llvm::cl::OptionEnumValue { "both", int(CFLAAType::Both), "Enable both variants of CFL-AA"
}
));
136
137/// Allow standard passes to be disabled by command line options. This supports
138/// simple binary flags that either suppress the pass or do nothing.
139/// i.e. -disable-mypass=false has no effect.
140/// These should be converted to boolOrDefault in order to use applyOverride.
141static IdentifyingPassPtr applyDisable(IdentifyingPassPtr PassID,
142 bool Override) {
143 if (Override)
144 return IdentifyingPassPtr();
145 return PassID;
146}
147
148/// Allow standard passes to be disabled by the command line, regardless of who
149/// is adding the pass.
150///
151/// StandardID is the pass identified in the standard pass pipeline and provided
152/// to addPass(). It may be a target-specific ID in the case that the target
153/// directly adds its own pass, but in that case we harmlessly fall through.
154///
155/// TargetID is the pass that the target has configured to override StandardID.
156///
157/// StandardID may be a pseudo ID. In that case TargetID is the name of the real
158/// pass to run. This allows multiple options to control a single pass depending
159/// on where in the pipeline that pass is added.
160static IdentifyingPassPtr overridePass(AnalysisID StandardID,
161 IdentifyingPassPtr TargetID) {
162 if (StandardID == &PostRASchedulerID)
163 return applyDisable(TargetID, DisablePostRASched);
164
165 if (StandardID == &BranchFolderPassID)
166 return applyDisable(TargetID, DisableBranchFold);
167
168 if (StandardID == &TailDuplicateID)
169 return applyDisable(TargetID, DisableTailDuplicate);
170
171 if (StandardID == &TargetPassConfig::EarlyTailDuplicateID)
172 return applyDisable(TargetID, DisableEarlyTailDup);
173
174 if (StandardID == &MachineBlockPlacementID)
175 return applyDisable(TargetID, DisableBlockPlacement);
176
177 if (StandardID == &StackSlotColoringID)
178 return applyDisable(TargetID, DisableSSC);
179
180 if (StandardID == &DeadMachineInstructionElimID)
181 return applyDisable(TargetID, DisableMachineDCE);
182
183 if (StandardID == &EarlyIfConverterID)
184 return applyDisable(TargetID, DisableEarlyIfConversion);
185
186 if (StandardID == &MachineLICMID)
187 return applyDisable(TargetID, DisableMachineLICM);
188
189 if (StandardID == &MachineCSEID)
190 return applyDisable(TargetID, DisableMachineCSE);
191
192 if (StandardID == &TargetPassConfig::PostRAMachineLICMID)
193 return applyDisable(TargetID, DisablePostRAMachineLICM);
194
195 if (StandardID == &MachineSinkingID)
196 return applyDisable(TargetID, DisableMachineSink);
197
198 if (StandardID == &MachineCopyPropagationID)
199 return applyDisable(TargetID, DisableCopyProp);
200
201 return TargetID;
202}
203
204//===---------------------------------------------------------------------===//
205/// TargetPassConfig
206//===---------------------------------------------------------------------===//
207
208INITIALIZE_PASS(TargetPassConfig, "targetpassconfig",static void *initializeTargetPassConfigPassOnce(PassRegistry &
Registry) { PassInfo *PI = new PassInfo( "Target Pass Configuration"
, "targetpassconfig", &TargetPassConfig::ID, PassInfo::NormalCtor_t
(callDefaultCtor<TargetPassConfig>), false, false); Registry
.registerPass(*PI, true); return PI; } static llvm::once_flag
InitializeTargetPassConfigPassFlag; void llvm::initializeTargetPassConfigPass
(PassRegistry &Registry) { llvm::call_once(InitializeTargetPassConfigPassFlag
, initializeTargetPassConfigPassOnce, std::ref(Registry)); }
209 "Target Pass Configuration", false, false)static void *initializeTargetPassConfigPassOnce(PassRegistry &
Registry) { PassInfo *PI = new PassInfo( "Target Pass Configuration"
, "targetpassconfig", &TargetPassConfig::ID, PassInfo::NormalCtor_t
(callDefaultCtor<TargetPassConfig>), false, false); Registry
.registerPass(*PI, true); return PI; } static llvm::once_flag
InitializeTargetPassConfigPassFlag; void llvm::initializeTargetPassConfigPass
(PassRegistry &Registry) { llvm::call_once(InitializeTargetPassConfigPassFlag
, initializeTargetPassConfigPassOnce, std::ref(Registry)); }
210char TargetPassConfig::ID = 0;
211
212// Pseudo Pass IDs.
213char TargetPassConfig::EarlyTailDuplicateID = 0;
214char TargetPassConfig::PostRAMachineLICMID = 0;
215
216namespace {
217struct InsertedPass {
218 AnalysisID TargetPassID;
219 IdentifyingPassPtr InsertedPassID;
220 bool VerifyAfter;
221 bool PrintAfter;
222
223 InsertedPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID,
224 bool VerifyAfter, bool PrintAfter)
225 : TargetPassID(TargetPassID), InsertedPassID(InsertedPassID),
226 VerifyAfter(VerifyAfter), PrintAfter(PrintAfter) {}
227
228 Pass *getInsertedPass() const {
229 assert(InsertedPassID.isValid() && "Illegal Pass ID!")((InsertedPassID.isValid() && "Illegal Pass ID!") ? static_cast
<void> (0) : __assert_fail ("InsertedPassID.isValid() && \"Illegal Pass ID!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/CodeGen/TargetPassConfig.cpp"
, 229, __PRETTY_FUNCTION__))
;
230 if (InsertedPassID.isInstance())
231 return InsertedPassID.getInstance();
232 Pass *NP = Pass::createPass(InsertedPassID.getID());
233 assert(NP && "Pass ID not registered")((NP && "Pass ID not registered") ? static_cast<void
> (0) : __assert_fail ("NP && \"Pass ID not registered\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/CodeGen/TargetPassConfig.cpp"
, 233, __PRETTY_FUNCTION__))
;
234 return NP;
235 }
236};
237}
238
239namespace llvm {
240class PassConfigImpl {
241public:
242 // List of passes explicitly substituted by this target. Normally this is
243 // empty, but it is a convenient way to suppress or replace specific passes
244 // that are part of a standard pass pipeline without overridding the entire
245 // pipeline. This mechanism allows target options to inherit a standard pass's
246 // user interface. For example, a target may disable a standard pass by
247 // default by substituting a pass ID of zero, and the user may still enable
248 // that standard pass with an explicit command line option.
249 DenseMap<AnalysisID,IdentifyingPassPtr> TargetPasses;
250
251 /// Store the pairs of <AnalysisID, AnalysisID> of which the second pass
252 /// is inserted after each instance of the first one.
253 SmallVector<InsertedPass, 4> InsertedPasses;
254};
255} // namespace llvm
256
257// Out of line virtual method.
258TargetPassConfig::~TargetPassConfig() {
259 delete Impl;
260}
261
262// Out of line constructor provides default values for pass options and
263// registers all common codegen passes.
264TargetPassConfig::TargetPassConfig(TargetMachine *tm, PassManagerBase &pm)
265 : ImmutablePass(ID), PM(&pm), Started(true), Stopped(false),
266 AddingMachinePasses(false), TM(tm), Impl(nullptr), Initialized(false),
267 DisableVerify(false), EnableTailMerge(true),
268 RequireCodeGenSCCOrder(false) {
269
270 Impl = new PassConfigImpl();
271
272 // Register all target independent codegen passes to activate their PassIDs,
273 // including this pass itself.
274 initializeCodeGen(*PassRegistry::getPassRegistry());
275
276 // Also register alias analysis passes required by codegen passes.
277 initializeBasicAAWrapperPassPass(*PassRegistry::getPassRegistry());
278 initializeAAResultsWrapperPassPass(*PassRegistry::getPassRegistry());
279
280 // Substitute Pseudo Pass IDs for real ones.
281 substitutePass(&EarlyTailDuplicateID, &TailDuplicateID);
282 substitutePass(&PostRAMachineLICMID, &MachineLICMID);
283
284 if (StringRef(PrintMachineInstrs.getValue()).equals(""))
285 TM->Options.PrintMachineCode = true;
286
287 if (TM->Options.EnableIPRA)
288 setRequiresCodeGenSCCOrder();
289}
290
291CodeGenOpt::Level TargetPassConfig::getOptLevel() const {
292 return TM->getOptLevel();
293}
294
295/// Insert InsertedPassID pass after TargetPassID.
296void TargetPassConfig::insertPass(AnalysisID TargetPassID,
297 IdentifyingPassPtr InsertedPassID,
298 bool VerifyAfter, bool PrintAfter) {
299 assert(((!InsertedPassID.isInstance() &&((((!InsertedPassID.isInstance() && TargetPassID != InsertedPassID
.getID()) || (InsertedPassID.isInstance() && TargetPassID
!= InsertedPassID.getInstance()->getPassID())) &&
"Insert a pass after itself!") ? static_cast<void> (0)
: __assert_fail ("((!InsertedPassID.isInstance() && TargetPassID != InsertedPassID.getID()) || (InsertedPassID.isInstance() && TargetPassID != InsertedPassID.getInstance()->getPassID())) && \"Insert a pass after itself!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/CodeGen/TargetPassConfig.cpp"
, 303, __PRETTY_FUNCTION__))
300 TargetPassID != InsertedPassID.getID()) ||((((!InsertedPassID.isInstance() && TargetPassID != InsertedPassID
.getID()) || (InsertedPassID.isInstance() && TargetPassID
!= InsertedPassID.getInstance()->getPassID())) &&
"Insert a pass after itself!") ? static_cast<void> (0)
: __assert_fail ("((!InsertedPassID.isInstance() && TargetPassID != InsertedPassID.getID()) || (InsertedPassID.isInstance() && TargetPassID != InsertedPassID.getInstance()->getPassID())) && \"Insert a pass after itself!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/CodeGen/TargetPassConfig.cpp"
, 303, __PRETTY_FUNCTION__))
301 (InsertedPassID.isInstance() &&((((!InsertedPassID.isInstance() && TargetPassID != InsertedPassID
.getID()) || (InsertedPassID.isInstance() && TargetPassID
!= InsertedPassID.getInstance()->getPassID())) &&
"Insert a pass after itself!") ? static_cast<void> (0)
: __assert_fail ("((!InsertedPassID.isInstance() && TargetPassID != InsertedPassID.getID()) || (InsertedPassID.isInstance() && TargetPassID != InsertedPassID.getInstance()->getPassID())) && \"Insert a pass after itself!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/CodeGen/TargetPassConfig.cpp"
, 303, __PRETTY_FUNCTION__))
302 TargetPassID != InsertedPassID.getInstance()->getPassID())) &&((((!InsertedPassID.isInstance() && TargetPassID != InsertedPassID
.getID()) || (InsertedPassID.isInstance() && TargetPassID
!= InsertedPassID.getInstance()->getPassID())) &&
"Insert a pass after itself!") ? static_cast<void> (0)
: __assert_fail ("((!InsertedPassID.isInstance() && TargetPassID != InsertedPassID.getID()) || (InsertedPassID.isInstance() && TargetPassID != InsertedPassID.getInstance()->getPassID())) && \"Insert a pass after itself!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/CodeGen/TargetPassConfig.cpp"
, 303, __PRETTY_FUNCTION__))
303 "Insert a pass after itself!")((((!InsertedPassID.isInstance() && TargetPassID != InsertedPassID
.getID()) || (InsertedPassID.isInstance() && TargetPassID
!= InsertedPassID.getInstance()->getPassID())) &&
"Insert a pass after itself!") ? static_cast<void> (0)
: __assert_fail ("((!InsertedPassID.isInstance() && TargetPassID != InsertedPassID.getID()) || (InsertedPassID.isInstance() && TargetPassID != InsertedPassID.getInstance()->getPassID())) && \"Insert a pass after itself!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/CodeGen/TargetPassConfig.cpp"
, 303, __PRETTY_FUNCTION__))
;
304 Impl->InsertedPasses.emplace_back(TargetPassID, InsertedPassID, VerifyAfter,
305 PrintAfter);
306}
307
308/// createPassConfig - Create a pass configuration object to be used by
309/// addPassToEmitX methods for generating a pipeline of CodeGen passes.
310///
311/// Targets may override this to extend TargetPassConfig.
312TargetPassConfig *LLVMTargetMachine::createPassConfig(PassManagerBase &PM) {
313 return new TargetPassConfig(this, PM);
314}
315
316TargetPassConfig::TargetPassConfig()
317 : ImmutablePass(ID), PM(nullptr) {
318 report_fatal_error("Trying to construct TargetPassConfig without a target "
319 "machine. Scheduling a CodeGen pass without a target "
320 "triple set?");
321}
322
323// Helper to verify the analysis is really immutable.
324void TargetPassConfig::setOpt(bool &Opt, bool Val) {
325 assert(!Initialized && "PassConfig is immutable")((!Initialized && "PassConfig is immutable") ? static_cast
<void> (0) : __assert_fail ("!Initialized && \"PassConfig is immutable\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/CodeGen/TargetPassConfig.cpp"
, 325, __PRETTY_FUNCTION__))
;
326 Opt = Val;
327}
328
329void TargetPassConfig::substitutePass(AnalysisID StandardID,
330 IdentifyingPassPtr TargetID) {
331 Impl->TargetPasses[StandardID] = TargetID;
332}
333
334IdentifyingPassPtr TargetPassConfig::getPassSubstitution(AnalysisID ID) const {
335 DenseMap<AnalysisID, IdentifyingPassPtr>::const_iterator
336 I = Impl->TargetPasses.find(ID);
337 if (I == Impl->TargetPasses.end())
338 return ID;
339 return I->second;
340}
341
342bool TargetPassConfig::isPassSubstitutedOrOverridden(AnalysisID ID) const {
343 IdentifyingPassPtr TargetID = getPassSubstitution(ID);
344 IdentifyingPassPtr FinalPtr = overridePass(ID, TargetID);
345 return !FinalPtr.isValid() || FinalPtr.isInstance() ||
346 FinalPtr.getID() != ID;
347}
348
349/// Add a pass to the PassManager if that pass is supposed to be run. If the
350/// Started/Stopped flags indicate either that the compilation should start at
351/// a later pass or that it should stop after an earlier pass, then do not add
352/// the pass. Finally, compare the current pass against the StartAfter
353/// and StopAfter options and change the Started/Stopped flags accordingly.
354void TargetPassConfig::addPass(Pass *P, bool verifyAfter, bool printAfter) {
355 assert(!Initialized && "PassConfig is immutable")((!Initialized && "PassConfig is immutable") ? static_cast
<void> (0) : __assert_fail ("!Initialized && \"PassConfig is immutable\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/CodeGen/TargetPassConfig.cpp"
, 355, __PRETTY_FUNCTION__))
;
356
357 // Cache the Pass ID here in case the pass manager finds this pass is
358 // redundant with ones already scheduled / available, and deletes it.
359 // Fundamentally, once we add the pass to the manager, we no longer own it
360 // and shouldn't reference it.
361 AnalysisID PassID = P->getPassID();
362
363 if (StartBefore == PassID)
364 Started = true;
365 if (StopBefore == PassID)
366 Stopped = true;
367 if (Started && !Stopped) {
368 std::string Banner;
369 // Construct banner message before PM->add() as that may delete the pass.
370 if (AddingMachinePasses && (printAfter || verifyAfter))
371 Banner = std::string("After ") + std::string(P->getPassName());
372 PM->add(P);
373 if (AddingMachinePasses) {
374 if (printAfter)
375 addPrintPass(Banner);
376 if (verifyAfter)
377 addVerifyPass(Banner);
378 }
379
380 // Add the passes after the pass P if there is any.
381 for (auto IP : Impl->InsertedPasses) {
382 if (IP.TargetPassID == PassID)
383 addPass(IP.getInsertedPass(), IP.VerifyAfter, IP.PrintAfter);
384 }
385 } else {
386 delete P;
387 }
388 if (StopAfter == PassID)
389 Stopped = true;
390 if (StartAfter == PassID)
391 Started = true;
392 if (Stopped && !Started)
393 report_fatal_error("Cannot stop compilation after pass that is not run");
394}
395
396/// Add a CodeGen pass at this point in the pipeline after checking for target
397/// and command line overrides.
398///
399/// addPass cannot return a pointer to the pass instance because is internal the
400/// PassManager and the instance we create here may already be freed.
401AnalysisID TargetPassConfig::addPass(AnalysisID PassID, bool verifyAfter,
402 bool printAfter) {
403 IdentifyingPassPtr TargetID = getPassSubstitution(PassID);
404 IdentifyingPassPtr FinalPtr = overridePass(PassID, TargetID);
405 if (!FinalPtr.isValid())
406 return nullptr;
407
408 Pass *P;
409 if (FinalPtr.isInstance())
410 P = FinalPtr.getInstance();
411 else {
412 P = Pass::createPass(FinalPtr.getID());
413 if (!P)
414 llvm_unreachable("Pass ID not registered")::llvm::llvm_unreachable_internal("Pass ID not registered", "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/CodeGen/TargetPassConfig.cpp"
, 414)
;
415 }
416 AnalysisID FinalID = P->getPassID();
417 addPass(P, verifyAfter, printAfter); // Ends the lifetime of P.
418
419 return FinalID;
420}
421
422void TargetPassConfig::printAndVerify(const std::string &Banner) {
423 addPrintPass(Banner);
424 addVerifyPass(Banner);
425}
426
427void TargetPassConfig::addPrintPass(const std::string &Banner) {
428 if (TM->shouldPrintMachineCode())
429 PM->add(createMachineFunctionPrinterPass(dbgs(), Banner));
430}
431
432void TargetPassConfig::addVerifyPass(const std::string &Banner) {
433 if (VerifyMachineCode)
434 PM->add(createMachineVerifierPass(Banner));
435}
436
437/// Add common target configurable passes that perform LLVM IR to IR transforms
438/// following machine independent optimization.
439void TargetPassConfig::addIRPasses() {
440 switch (UseCFLAA) {
441 case CFLAAType::Steensgaard:
442 addPass(createCFLSteensAAWrapperPass());
443 break;
444 case CFLAAType::Andersen:
445 addPass(createCFLAndersAAWrapperPass());
446 break;
447 case CFLAAType::Both:
448 addPass(createCFLAndersAAWrapperPass());
449 addPass(createCFLSteensAAWrapperPass());
450 break;
451 default:
452 break;
453 }
454
455 // Basic AliasAnalysis support.
456 // Add TypeBasedAliasAnalysis before BasicAliasAnalysis so that
457 // BasicAliasAnalysis wins if they disagree. This is intended to help
458 // support "obvious" type-punning idioms.
459 addPass(createTypeBasedAAWrapperPass());
460 addPass(createScopedNoAliasAAWrapperPass());
461 addPass(createBasicAAWrapperPass());
462
463 // Before running any passes, run the verifier to determine if the input
464 // coming from the front-end and/or optimizer is valid.
465 if (!DisableVerify)
466 addPass(createVerifierPass());
467
468 // Run loop strength reduction before anything else.
469 if (getOptLevel() != CodeGenOpt::None && !DisableLSR) {
470 addPass(createLoopStrengthReducePass());
471 if (PrintLSR)
472 addPass(createPrintFunctionPass(dbgs(), "\n\n*** Code after LSR ***\n"));
473 }
474
475 // Run GC lowering passes for builtin collectors
476 // TODO: add a pass insertion point here
477 addPass(createGCLoweringPass());
478 addPass(createShadowStackGCLoweringPass());
479
480 // Make sure that no unreachable blocks are instruction selected.
481 addPass(createUnreachableBlockEliminationPass());
482
483 // Prepare expensive constants for SelectionDAG.
484 if (getOptLevel() != CodeGenOpt::None && !DisableConstantHoisting)
485 addPass(createConstantHoistingPass());
486
487 if (getOptLevel() != CodeGenOpt::None && !DisablePartialLibcallInlining)
488 addPass(createPartiallyInlineLibCallsPass());
489
490 // Insert calls to mcount-like functions.
491 addPass(createCountingFunctionInserterPass());
492
493 // Add scalarization of target's unsupported masked memory intrinsics pass.
494 // the unsupported intrinsic will be replaced with a chain of basic blocks,
495 // that stores/loads element one-by-one if the appropriate mask bit is set.
496 addPass(createScalarizeMaskedMemIntrinPass());
497
498 // Expand reduction intrinsics into shuffle sequences if the target wants to.
499 addPass(createExpandReductionsPass());
500}
501
502/// Turn exception handling constructs into something the code generators can
503/// handle.
504void TargetPassConfig::addPassesToHandleExceptions() {
505 const MCAsmInfo *MCAI = TM->getMCAsmInfo();
506 assert(MCAI && "No MCAsmInfo")((MCAI && "No MCAsmInfo") ? static_cast<void> (
0) : __assert_fail ("MCAI && \"No MCAsmInfo\"", "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/CodeGen/TargetPassConfig.cpp"
, 506, __PRETTY_FUNCTION__))
;
507 switch (MCAI->getExceptionHandlingType()) {
508 case ExceptionHandling::SjLj:
509 // SjLj piggy-backs on dwarf for this bit. The cleanups done apply to both
510 // Dwarf EH prepare needs to be run after SjLj prepare. Otherwise,
511 // catch info can get misplaced when a selector ends up more than one block
512 // removed from the parent invoke(s). This could happen when a landing
513 // pad is shared by multiple invokes and is also a target of a normal
514 // edge from elsewhere.
515 addPass(createSjLjEHPreparePass());
516 LLVM_FALLTHROUGH[[clang::fallthrough]];
517 case ExceptionHandling::DwarfCFI:
518 case ExceptionHandling::ARM:
519 addPass(createDwarfEHPass());
520 break;
521 case ExceptionHandling::WinEH:
522 // We support using both GCC-style and MSVC-style exceptions on Windows, so
523 // add both preparation passes. Each pass will only actually run if it
524 // recognizes the personality function.
525 addPass(createWinEHPass());
526 addPass(createDwarfEHPass());
527 break;
528 case ExceptionHandling::None:
529 addPass(createLowerInvokePass());
530
531 // The lower invoke pass may create unreachable code. Remove it.
532 addPass(createUnreachableBlockEliminationPass());
533 break;
534 }
535}
536
537/// Add pass to prepare the LLVM IR for code generation. This should be done
538/// before exception handling preparation passes.
539void TargetPassConfig::addCodeGenPrepare() {
540 if (getOptLevel() != CodeGenOpt::None && !DisableCGP)
541 addPass(createCodeGenPreparePass());
542 addPass(createRewriteSymbolsPass());
543}
544
545/// Add common passes that perform LLVM IR to IR transforms in preparation for
546/// instruction selection.
547void TargetPassConfig::addISelPrepare() {
548 addPreISel();
549
550 // Force codegen to run according to the callgraph.
551 if (requiresCodeGenSCCOrder())
552 addPass(new DummyCGSCCPass);
553
554 // Add both the safe stack and the stack protection passes: each of them will
555 // only protect functions that have corresponding attributes.
556 addPass(createSafeStackPass());
557 addPass(createStackProtectorPass());
558
559 if (PrintISelInput)
560 addPass(createPrintFunctionPass(
561 dbgs(), "\n\n*** Final LLVM Code input to ISel ***\n"));
562
563 // All passes which modify the LLVM IR are now complete; run the verifier
564 // to ensure that the IR is valid.
565 if (!DisableVerify)
566 addPass(createVerifierPass());
567}
568
569/// -regalloc=... command line option.
570static FunctionPass *useDefaultRegisterAllocator() { return nullptr; }
571static cl::opt<RegisterRegAlloc::FunctionPassCtor, false,
572 RegisterPassParser<RegisterRegAlloc> >
573RegAlloc("regalloc",
574 cl::init(&useDefaultRegisterAllocator),
575 cl::desc("Register allocator to use"));
576
577/// Add the complete set of target-independent postISel code generator passes.
578///
579/// This can be read as the standard order of major LLVM CodeGen stages. Stages
580/// with nontrivial configuration or multiple passes are broken out below in
581/// add%Stage routines.
582///
583/// Any TargetPassConfig::addXX routine may be overriden by the Target. The
584/// addPre/Post methods with empty header implementations allow injecting
585/// target-specific fixups just before or after major stages. Additionally,
586/// targets have the flexibility to change pass order within a stage by
587/// overriding default implementation of add%Stage routines below. Each
588/// technique has maintainability tradeoffs because alternate pass orders are
589/// not well supported. addPre/Post works better if the target pass is easily
590/// tied to a common pass. But if it has subtle dependencies on multiple passes,
591/// the target should override the stage instead.
592///
593/// TODO: We could use a single addPre/Post(ID) hook to allow pass injection
594/// before/after any target-independent pass. But it's currently overkill.
595void TargetPassConfig::addMachinePasses() {
596 AddingMachinePasses = true;
597
598 // Insert a machine instr printer pass after the specified pass.
599 if (!StringRef(PrintMachineInstrs.getValue()).equals("") &&
600 !StringRef(PrintMachineInstrs.getValue()).equals("option-unspecified")) {
601 const PassRegistry *PR = PassRegistry::getPassRegistry();
602 const PassInfo *TPI = PR->getPassInfo(PrintMachineInstrs.getValue());
603 const PassInfo *IPI = PR->getPassInfo(StringRef("machineinstr-printer"));
604 assert (TPI && IPI && "Pass ID not registered!")((TPI && IPI && "Pass ID not registered!") ? static_cast
<void> (0) : __assert_fail ("TPI && IPI && \"Pass ID not registered!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/CodeGen/TargetPassConfig.cpp"
, 604, __PRETTY_FUNCTION__))
;
605 const char *TID = (const char *)(TPI->getTypeInfo());
606 const char *IID = (const char *)(IPI->getTypeInfo());
607 insertPass(TID, IID);
608 }
609
610 // Print the instruction selected machine code...
611 printAndVerify("After Instruction Selection");
612
613 if (TM->Options.EnableIPRA)
614 addPass(createRegUsageInfoPropPass());
615
616 // Expand pseudo-instructions emitted by ISel.
617 addPass(&ExpandISelPseudosID);
618
619 // Add passes that optimize machine instructions in SSA form.
620 if (getOptLevel() != CodeGenOpt::None) {
621 addMachineSSAOptimization();
622 } else {
623 // If the target requests it, assign local variables to stack slots relative
624 // to one another and simplify frame index references where possible.
625 addPass(&LocalStackSlotAllocationID, false);
626 }
627
628 // Run pre-ra passes.
629 addPreRegAlloc();
630
631 // Run register allocation and passes that are tightly coupled with it,
632 // including phi elimination and scheduling.
633 if (getOptimizeRegAlloc())
634 addOptimizedRegAlloc(createRegAllocPass(true));
635 else {
636 if (RegAlloc != &useDefaultRegisterAllocator &&
637 RegAlloc != &createFastRegisterAllocator)
638 report_fatal_error("Must use fast (default) register allocator for unoptimized regalloc.");
639 addFastRegAlloc(createRegAllocPass(false));
640 }
641
642 // Run post-ra passes.
643 addPostRegAlloc();
644
645 // Insert prolog/epilog code. Eliminate abstract frame index references...
646 if (getOptLevel() != CodeGenOpt::None)
647 addPass(&ShrinkWrapID);
648
649 // Prolog/Epilog inserter needs a TargetMachine to instantiate. But only
650 // do so if it hasn't been disabled, substituted, or overridden.
651 if (!isPassSubstitutedOrOverridden(&PrologEpilogCodeInserterID))
652 addPass(createPrologEpilogInserterPass());
653
654 /// Add passes that optimize machine instructions after register allocation.
655 if (getOptLevel() != CodeGenOpt::None)
656 addMachineLateOptimization();
657
658 // Expand pseudo instructions before second scheduling pass.
659 addPass(&ExpandPostRAPseudosID);
660
661 // Run pre-sched2 passes.
662 addPreSched2();
663
664 if (EnableImplicitNullChecks)
665 addPass(&ImplicitNullChecksID);
666
667 // Second pass scheduler.
668 // Let Target optionally insert this pass by itself at some other
669 // point.
670 if (getOptLevel() != CodeGenOpt::None &&
671 !TM->targetSchedulesPostRAScheduling()) {
672 if (MISchedPostRA)
673 addPass(&PostMachineSchedulerID);
674 else
675 addPass(&PostRASchedulerID);
676 }
677
678 // GC
679 if (addGCPasses()) {
680 if (PrintGCInfo)
681 addPass(createGCInfoPrinter(dbgs()), false, false);
682 }
683
684 // Basic block placement.
685 if (getOptLevel() != CodeGenOpt::None)
686 addBlockPlacement();
687
688 addPreEmitPass();
689
690 if (TM->Options.EnableIPRA)
691 // Collect register usage information and produce a register mask of
692 // clobbered registers, to be used to optimize call sites.
693 addPass(createRegUsageInfoCollector());
694
695 addPass(&FuncletLayoutID, false);
696
697 addPass(&StackMapLivenessID, false);
698 addPass(&LiveDebugValuesID, false);
699
700 // Insert before XRay Instrumentation.
701 addPass(&FEntryInserterID, false);
702
703 addPass(&XRayInstrumentationID, false);
704 addPass(&PatchableFunctionID, false);
705
706 if (EnableMachineOutliner)
707 PM->add(createMachineOutlinerPass());
708
709 AddingMachinePasses = false;
710}
711
712/// Add passes that optimize machine instructions in SSA form.
713void TargetPassConfig::addMachineSSAOptimization() {
714 // Pre-ra tail duplication.
715 addPass(&EarlyTailDuplicateID);
716
717 // Optimize PHIs before DCE: removing dead PHI cycles may make more
718 // instructions dead.
719 addPass(&OptimizePHIsID, false);
720
721 // This pass merges large allocas. StackSlotColoring is a different pass
722 // which merges spill slots.
723 addPass(&StackColoringID, false);
724
725 // If the target requests it, assign local variables to stack slots relative
726 // to one another and simplify frame index references where possible.
727 addPass(&LocalStackSlotAllocationID, false);
728
729 // With optimization, dead code should already be eliminated. However
730 // there is one known exception: lowered code for arguments that are only
731 // used by tail calls, where the tail calls reuse the incoming stack
732 // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
733 addPass(&DeadMachineInstructionElimID);
734
735 // Allow targets to insert passes that improve instruction level parallelism,
736 // like if-conversion. Such passes will typically need dominator trees and
737 // loop info, just like LICM and CSE below.
738 addILPOpts();
739
740 addPass(&MachineLICMID, false);
741 addPass(&MachineCSEID, false);
742
743 // Coalesce basic blocks with the same branch condition
744 addPass(&BranchCoalescingID);
745
746 addPass(&MachineSinkingID);
747
748 addPass(&PeepholeOptimizerID);
749 // Clean-up the dead code that may have been generated by peephole
750 // rewriting.
751 addPass(&DeadMachineInstructionElimID);
752}
753
754//===---------------------------------------------------------------------===//
755/// Register Allocation Pass Configuration
756//===---------------------------------------------------------------------===//
757
758bool TargetPassConfig::getOptimizeRegAlloc() const {
759 switch (OptimizeRegAlloc) {
760 case cl::BOU_UNSET: return getOptLevel() != CodeGenOpt::None;
761 case cl::BOU_TRUE: return true;
762 case cl::BOU_FALSE: return false;
763 }
764 llvm_unreachable("Invalid optimize-regalloc state")::llvm::llvm_unreachable_internal("Invalid optimize-regalloc state"
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/CodeGen/TargetPassConfig.cpp"
, 764)
;
765}
766
767/// RegisterRegAlloc's global Registry tracks allocator registration.
768MachinePassRegistry RegisterRegAlloc::Registry;
769
770/// A dummy default pass factory indicates whether the register allocator is
771/// overridden on the command line.
772static llvm::once_flag InitializeDefaultRegisterAllocatorFlag;
773
774static RegisterRegAlloc
775defaultRegAlloc("default",
776 "pick register allocator based on -O option",
777 useDefaultRegisterAllocator);
778
779static void initializeDefaultRegisterAllocatorOnce() {
780 RegisterRegAlloc::FunctionPassCtor Ctor = RegisterRegAlloc::getDefault();
781
782 if (!Ctor) {
783 Ctor = RegAlloc;
Value stored to 'Ctor' is never read
784 RegisterRegAlloc::setDefault(RegAlloc);
785 }
786}
787
788/// Instantiate the default register allocator pass for this target for either
789/// the optimized or unoptimized allocation path. This will be added to the pass
790/// manager by addFastRegAlloc in the unoptimized case or addOptimizedRegAlloc
791/// in the optimized case.
792///
793/// A target that uses the standard regalloc pass order for fast or optimized
794/// allocation may still override this for per-target regalloc
795/// selection. But -regalloc=... always takes precedence.
796FunctionPass *TargetPassConfig::createTargetRegisterAllocator(bool Optimized) {
797 if (Optimized)
798 return createGreedyRegisterAllocator();
799 else
800 return createFastRegisterAllocator();
801}
802
803/// Find and instantiate the register allocation pass requested by this target
804/// at the current optimization level. Different register allocators are
805/// defined as separate passes because they may require different analysis.
806///
807/// This helper ensures that the regalloc= option is always available,
808/// even for targets that override the default allocator.
809///
810/// FIXME: When MachinePassRegistry register pass IDs instead of function ptrs,
811/// this can be folded into addPass.
812FunctionPass *TargetPassConfig::createRegAllocPass(bool Optimized) {
813 // Initialize the global default.
814 llvm::call_once(InitializeDefaultRegisterAllocatorFlag,
815 initializeDefaultRegisterAllocatorOnce);
816
817 RegisterRegAlloc::FunctionPassCtor Ctor = RegisterRegAlloc::getDefault();
818 if (Ctor != useDefaultRegisterAllocator)
819 return Ctor();
820
821 // With no -regalloc= override, ask the target for a regalloc pass.
822 return createTargetRegisterAllocator(Optimized);
823}
824
825/// Return true if the default global register allocator is in use and
826/// has not be overriden on the command line with '-regalloc=...'
827bool TargetPassConfig::usingDefaultRegAlloc() const {
828 return RegAlloc.getNumOccurrences() == 0;
829}
830
831/// Add the minimum set of target-independent passes that are required for
832/// register allocation. No coalescing or scheduling.
833void TargetPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
834 addPass(&PHIEliminationID, false);
835 addPass(&TwoAddressInstructionPassID, false);
836
837 if (RegAllocPass)
838 addPass(RegAllocPass);
839}
840
841/// Add standard target-independent passes that are tightly coupled with
842/// optimized register allocation, including coalescing, machine instruction
843/// scheduling, and register allocation itself.
844void TargetPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
845 addPass(&DetectDeadLanesID, false);
846
847 addPass(&ProcessImplicitDefsID, false);
848
849 // LiveVariables currently requires pure SSA form.
850 //
851 // FIXME: Once TwoAddressInstruction pass no longer uses kill flags,
852 // LiveVariables can be removed completely, and LiveIntervals can be directly
853 // computed. (We still either need to regenerate kill flags after regalloc, or
854 // preferably fix the scavenger to not depend on them).
855 addPass(&LiveVariablesID, false);
856
857 // Edge splitting is smarter with machine loop info.
858 addPass(&MachineLoopInfoID, false);
859 addPass(&PHIEliminationID, false);
860
861 // Eventually, we want to run LiveIntervals before PHI elimination.
862 if (EarlyLiveIntervals)
863 addPass(&LiveIntervalsID, false);
864
865 addPass(&TwoAddressInstructionPassID, false);
866 addPass(&RegisterCoalescerID);
867
868 // The machine scheduler may accidentally create disconnected components
869 // when moving subregister definitions around, avoid this by splitting them to
870 // separate vregs before. Splitting can also improve reg. allocation quality.
871 addPass(&RenameIndependentSubregsID);
872
873 // PreRA instruction scheduling.
874 addPass(&MachineSchedulerID);
875
876 if (RegAllocPass) {
877 // Add the selected register allocation pass.
878 addPass(RegAllocPass);
879
880 // Allow targets to change the register assignments before rewriting.
881 addPreRewrite();
882
883 // Finally rewrite virtual registers.
884 addPass(&VirtRegRewriterID);
885
886 // Perform stack slot coloring and post-ra machine LICM.
887 //
888 // FIXME: Re-enable coloring with register when it's capable of adding
889 // kill markers.
890 addPass(&StackSlotColoringID);
891
892 // Run post-ra machine LICM to hoist reloads / remats.
893 //
894 // FIXME: can this move into MachineLateOptimization?
895 addPass(&PostRAMachineLICMID);
896 }
897}
898
899//===---------------------------------------------------------------------===//
900/// Post RegAlloc Pass Configuration
901//===---------------------------------------------------------------------===//
902
903/// Add passes that optimize machine instructions after register allocation.
904void TargetPassConfig::addMachineLateOptimization() {
905 // Branch folding must be run after regalloc and prolog/epilog insertion.
906 addPass(&BranchFolderPassID);
907
908 // Tail duplication.
909 // Note that duplicating tail just increases code size and degrades
910 // performance for targets that require Structured Control Flow.
911 // In addition it can also make CFG irreducible. Thus we disable it.
912 if (!TM->requiresStructuredCFG())
913 addPass(&TailDuplicateID);
914
915 // Copy propagation.
916 addPass(&MachineCopyPropagationID);
917}
918
919/// Add standard GC passes.
920bool TargetPassConfig::addGCPasses() {
921 addPass(&GCMachineCodeAnalysisID, false);
922 return true;
923}
924
925/// Add standard basic block placement passes.
926void TargetPassConfig::addBlockPlacement() {
927 if (addPass(&MachineBlockPlacementID)) {
928 // Run a separate pass to collect block placement statistics.
929 if (EnableBlockPlacementStats)
930 addPass(&MachineBlockPlacementStatsID);
931 }
932}
933
934//===---------------------------------------------------------------------===//
935/// GlobalISel Configuration
936//===---------------------------------------------------------------------===//
937
938bool TargetPassConfig::isGlobalISelEnabled() const {
939 return false;
940}
941
942bool TargetPassConfig::isGlobalISelAbortEnabled() const {
943 return EnableGlobalISelAbort == 1;
944}
945
946bool TargetPassConfig::reportDiagnosticWhenGlobalISelFallback() const {
947 return EnableGlobalISelAbort == 2;
948}