Bug Summary

File:lib/CodeGen/TargetPassConfig.cpp
Warning:line 986, column 5
Value stored to 'Ctor' is never read

Annotated Source Code

Press '?' to see keyboard shortcuts

clang -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name TargetPassConfig.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-eagerly-assume -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -mrelocation-model pic -pic-level 2 -mthread-model posix -fmath-errno -masm-verbose -mconstructor-aliases -munwind-tables -fuse-init-array -target-cpu x86-64 -dwarf-column-info -debugger-tuning=gdb -momit-leaf-frame-pointer -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-7/lib/clang/7.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-7~svn329677/build-llvm/lib/CodeGen -I /build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen -I /build/llvm-toolchain-snapshot-7~svn329677/build-llvm/include -I /build/llvm-toolchain-snapshot-7~svn329677/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/7.3.0/../../../../include/c++/7.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/7.3.0/../../../../include/x86_64-linux-gnu/c++/7.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/7.3.0/../../../../include/x86_64-linux-gnu/c++/7.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/7.3.0/../../../../include/c++/7.3.0/backward -internal-isystem /usr/include/clang/7.0.0/include/ -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-7/lib/clang/7.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++11 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-7~svn329677/build-llvm/lib/CodeGen -ferror-limit 19 -fmessage-length 0 -fvisibility-inlines-hidden -fobjc-runtime=gcc -fdiagnostics-show-option -vectorize-loops -vectorize-slp -analyzer-checker optin.performance.Padding -analyzer-output=html -analyzer-config stable-report-filename=true -o /tmp/scan-build-2018-04-11-031539-24776-1 -x c++ /build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/TargetPassConfig.cpp
1//===- TargetPassConfig.cpp - Target independent code generation passes ---===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines interfaces to access the target independent code
11// generation passes provided by the LLVM backend.
12//
13//===---------------------------------------------------------------------===//
14
15#include "llvm/CodeGen/TargetPassConfig.h"
16#include "llvm/ADT/DenseMap.h"
17#include "llvm/ADT/SmallVector.h"
18#include "llvm/ADT/StringRef.h"
19#include "llvm/Analysis/BasicAliasAnalysis.h"
20#include "llvm/Analysis/CFLAndersAliasAnalysis.h"
21#include "llvm/Analysis/CFLSteensAliasAnalysis.h"
22#include "llvm/Analysis/CallGraphSCCPass.h"
23#include "llvm/Analysis/ScopedNoAliasAA.h"
24#include "llvm/Analysis/TargetTransformInfo.h"
25#include "llvm/Analysis/TypeBasedAliasAnalysis.h"
26#include "llvm/CodeGen/MachineFunctionPass.h"
27#include "llvm/CodeGen/MachinePassRegistry.h"
28#include "llvm/CodeGen/Passes.h"
29#include "llvm/CodeGen/RegAllocRegistry.h"
30#include "llvm/IR/IRPrintingPasses.h"
31#include "llvm/IR/LegacyPassManager.h"
32#include "llvm/IR/Verifier.h"
33#include "llvm/MC/MCAsmInfo.h"
34#include "llvm/MC/MCTargetOptions.h"
35#include "llvm/Pass.h"
36#include "llvm/Support/CodeGen.h"
37#include "llvm/Support/CommandLine.h"
38#include "llvm/Support/Compiler.h"
39#include "llvm/Support/Debug.h"
40#include "llvm/Support/ErrorHandling.h"
41#include "llvm/Support/Threading.h"
42#include "llvm/Target/TargetMachine.h"
43#include "llvm/Transforms/Scalar.h"
44#include "llvm/Transforms/Utils.h"
45#include "llvm/Transforms/Utils/SymbolRewriter.h"
46#include <cassert>
47#include <string>
48
49using namespace llvm;
50
51cl::opt<bool> EnableIPRA("enable-ipra", cl::init(false), cl::Hidden,
52 cl::desc("Enable interprocedural register allocation "
53 "to reduce load/store at procedure calls."));
54static cl::opt<bool> DisablePostRASched("disable-post-ra", cl::Hidden,
55 cl::desc("Disable Post Regalloc Scheduler"));
56static cl::opt<bool> DisableBranchFold("disable-branch-fold", cl::Hidden,
57 cl::desc("Disable branch folding"));
58static cl::opt<bool> DisableTailDuplicate("disable-tail-duplicate", cl::Hidden,
59 cl::desc("Disable tail duplication"));
60static cl::opt<bool> DisableEarlyTailDup("disable-early-taildup", cl::Hidden,
61 cl::desc("Disable pre-register allocation tail duplication"));
62static cl::opt<bool> DisableBlockPlacement("disable-block-placement",
63 cl::Hidden, cl::desc("Disable probability-driven block placement"));
64static cl::opt<bool> EnableBlockPlacementStats("enable-block-placement-stats",
65 cl::Hidden, cl::desc("Collect probability-driven block placement stats"));
66static cl::opt<bool> DisableSSC("disable-ssc", cl::Hidden,
67 cl::desc("Disable Stack Slot Coloring"));
68static cl::opt<bool> DisableMachineDCE("disable-machine-dce", cl::Hidden,
69 cl::desc("Disable Machine Dead Code Elimination"));
70static cl::opt<bool> DisableEarlyIfConversion("disable-early-ifcvt", cl::Hidden,
71 cl::desc("Disable Early If-conversion"));
72static cl::opt<bool> DisableMachineLICM("disable-machine-licm", cl::Hidden,
73 cl::desc("Disable Machine LICM"));
74static cl::opt<bool> DisableMachineCSE("disable-machine-cse", cl::Hidden,
75 cl::desc("Disable Machine Common Subexpression Elimination"));
76static cl::opt<cl::boolOrDefault> OptimizeRegAlloc(
77 "optimize-regalloc", cl::Hidden,
78 cl::desc("Enable optimized register allocation compilation path."));
79static cl::opt<bool> DisablePostRAMachineLICM("disable-postra-machine-licm",
80 cl::Hidden,
81 cl::desc("Disable Machine LICM"));
82static cl::opt<bool> DisableMachineSink("disable-machine-sink", cl::Hidden,
83 cl::desc("Disable Machine Sinking"));
84static cl::opt<bool> DisablePostRAMachineSink("disable-postra-machine-sink",
85 cl::Hidden,
86 cl::desc("Disable PostRA Machine Sinking"));
87static cl::opt<bool> DisableLSR("disable-lsr", cl::Hidden,
88 cl::desc("Disable Loop Strength Reduction Pass"));
89static cl::opt<bool> DisableConstantHoisting("disable-constant-hoisting",
90 cl::Hidden, cl::desc("Disable ConstantHoisting"));
91static cl::opt<bool> DisableCGP("disable-cgp", cl::Hidden,
92 cl::desc("Disable Codegen Prepare"));
93static cl::opt<bool> DisableCopyProp("disable-copyprop", cl::Hidden,
94 cl::desc("Disable Copy Propagation pass"));
95static cl::opt<bool> DisablePartialLibcallInlining("disable-partial-libcall-inlining",
96 cl::Hidden, cl::desc("Disable Partial Libcall Inlining"));
97static cl::opt<bool> EnableImplicitNullChecks(
98 "enable-implicit-null-checks",
99 cl::desc("Fold null checks into faulting memory operations"),
100 cl::init(false), cl::Hidden);
101static cl::opt<bool> DisableMergeICmps("disable-mergeicmps",
102 cl::desc("Disable MergeICmps Pass"),
103 cl::init(false), cl::Hidden);
104static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
105 cl::desc("Print LLVM IR produced by the loop-reduce pass"));
106static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
107 cl::desc("Print LLVM IR input to isel pass"));
108static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden,
109 cl::desc("Dump garbage collector data"));
110static cl::opt<bool> VerifyMachineCode("verify-machineinstrs", cl::Hidden,
111 cl::desc("Verify generated machine code"),
112 cl::init(false),
113 cl::ZeroOrMore);
114static cl::opt<bool> EnableMachineOutliner("enable-machine-outliner",
115 cl::Hidden,
116 cl::desc("Enable machine outliner"));
117static cl::opt<bool> EnableLinkOnceODROutlining(
118 "enable-linkonceodr-outlining",
119 cl::Hidden,
120 cl::desc("Enable the machine outliner on linkonceodr functions"),
121 cl::init(false));
122// Enable or disable FastISel. Both options are needed, because
123// FastISel is enabled by default with -fast, and we wish to be
124// able to enable or disable fast-isel independently from -O0.
125static cl::opt<cl::boolOrDefault>
126EnableFastISelOption("fast-isel", cl::Hidden,
127 cl::desc("Enable the \"fast\" instruction selector"));
128
129static cl::opt<cl::boolOrDefault> EnableGlobalISelOption(
130 "global-isel", cl::Hidden,
131 cl::desc("Enable the \"global\" instruction selector"));
132
133static cl::opt<std::string> PrintMachineInstrs(
134 "print-machineinstrs", cl::ValueOptional, cl::desc("Print machine instrs"),
135 cl::value_desc("pass-name"), cl::init("option-unspecified"), cl::Hidden);
136
137static cl::opt<int> EnableGlobalISelAbort(
138 "global-isel-abort", cl::Hidden,
139 cl::desc("Enable abort calls when \"global\" instruction selection "
140 "fails to lower/select an instruction: 0 disable the abort, "
141 "1 enable the abort, and "
142 "2 disable the abort but emit a diagnostic on failure"),
143 cl::init(1));
144
145// Temporary option to allow experimenting with MachineScheduler as a post-RA
146// scheduler. Targets can "properly" enable this with
147// substitutePass(&PostRASchedulerID, &PostMachineSchedulerID).
148// Targets can return true in targetSchedulesPostRAScheduling() and
149// insert a PostRA scheduling pass wherever it wants.
150cl::opt<bool> MISchedPostRA("misched-postra", cl::Hidden,
151 cl::desc("Run MachineScheduler post regalloc (independent of preRA sched)"));
152
153// Experimental option to run live interval analysis early.
154static cl::opt<bool> EarlyLiveIntervals("early-live-intervals", cl::Hidden,
155 cl::desc("Run live interval analysis earlier in the pipeline"));
156
157// Experimental option to use CFL-AA in codegen
158enum class CFLAAType { None, Steensgaard, Andersen, Both };
159static cl::opt<CFLAAType> UseCFLAA(
160 "use-cfl-aa-in-codegen", cl::init(CFLAAType::None), cl::Hidden,
161 cl::desc("Enable the new, experimental CFL alias analysis in CodeGen"),
162 cl::values(clEnumValN(CFLAAType::None, "none", "Disable CFL-AA")llvm::cl::OptionEnumValue { "none", int(CFLAAType::None), "Disable CFL-AA"
}
,
163 clEnumValN(CFLAAType::Steensgaard, "steens",llvm::cl::OptionEnumValue { "steens", int(CFLAAType::Steensgaard
), "Enable unification-based CFL-AA" }
164 "Enable unification-based CFL-AA")llvm::cl::OptionEnumValue { "steens", int(CFLAAType::Steensgaard
), "Enable unification-based CFL-AA" }
,
165 clEnumValN(CFLAAType::Andersen, "anders",llvm::cl::OptionEnumValue { "anders", int(CFLAAType::Andersen
), "Enable inclusion-based CFL-AA" }
166 "Enable inclusion-based CFL-AA")llvm::cl::OptionEnumValue { "anders", int(CFLAAType::Andersen
), "Enable inclusion-based CFL-AA" }
,
167 clEnumValN(CFLAAType::Both, "both",llvm::cl::OptionEnumValue { "both", int(CFLAAType::Both), "Enable both variants of CFL-AA"
}
168 "Enable both variants of CFL-AA")llvm::cl::OptionEnumValue { "both", int(CFLAAType::Both), "Enable both variants of CFL-AA"
}
));
169
170/// Option names for limiting the codegen pipeline.
171/// Those are used in error reporting and we didn't want
172/// to duplicate their names all over the place.
173const char *StartAfterOptName = "start-after";
174const char *StartBeforeOptName = "start-before";
175const char *StopAfterOptName = "stop-after";
176const char *StopBeforeOptName = "stop-before";
177
178static cl::opt<std::string>
179 StartAfterOpt(StringRef(StartAfterOptName),
180 cl::desc("Resume compilation after a specific pass"),
181 cl::value_desc("pass-name"), cl::init(""), cl::Hidden);
182
183static cl::opt<std::string>
184 StartBeforeOpt(StringRef(StartBeforeOptName),
185 cl::desc("Resume compilation before a specific pass"),
186 cl::value_desc("pass-name"), cl::init(""), cl::Hidden);
187
188static cl::opt<std::string>
189 StopAfterOpt(StringRef(StopAfterOptName),
190 cl::desc("Stop compilation after a specific pass"),
191 cl::value_desc("pass-name"), cl::init(""), cl::Hidden);
192
193static cl::opt<std::string>
194 StopBeforeOpt(StringRef(StopBeforeOptName),
195 cl::desc("Stop compilation before a specific pass"),
196 cl::value_desc("pass-name"), cl::init(""), cl::Hidden);
197
198/// Allow standard passes to be disabled by command line options. This supports
199/// simple binary flags that either suppress the pass or do nothing.
200/// i.e. -disable-mypass=false has no effect.
201/// These should be converted to boolOrDefault in order to use applyOverride.
202static IdentifyingPassPtr applyDisable(IdentifyingPassPtr PassID,
203 bool Override) {
204 if (Override)
205 return IdentifyingPassPtr();
206 return PassID;
207}
208
209/// Allow standard passes to be disabled by the command line, regardless of who
210/// is adding the pass.
211///
212/// StandardID is the pass identified in the standard pass pipeline and provided
213/// to addPass(). It may be a target-specific ID in the case that the target
214/// directly adds its own pass, but in that case we harmlessly fall through.
215///
216/// TargetID is the pass that the target has configured to override StandardID.
217///
218/// StandardID may be a pseudo ID. In that case TargetID is the name of the real
219/// pass to run. This allows multiple options to control a single pass depending
220/// on where in the pipeline that pass is added.
221static IdentifyingPassPtr overridePass(AnalysisID StandardID,
222 IdentifyingPassPtr TargetID) {
223 if (StandardID == &PostRASchedulerID)
224 return applyDisable(TargetID, DisablePostRASched);
225
226 if (StandardID == &BranchFolderPassID)
227 return applyDisable(TargetID, DisableBranchFold);
228
229 if (StandardID == &TailDuplicateID)
230 return applyDisable(TargetID, DisableTailDuplicate);
231
232 if (StandardID == &EarlyTailDuplicateID)
233 return applyDisable(TargetID, DisableEarlyTailDup);
234
235 if (StandardID == &MachineBlockPlacementID)
236 return applyDisable(TargetID, DisableBlockPlacement);
237
238 if (StandardID == &StackSlotColoringID)
239 return applyDisable(TargetID, DisableSSC);
240
241 if (StandardID == &DeadMachineInstructionElimID)
242 return applyDisable(TargetID, DisableMachineDCE);
243
244 if (StandardID == &EarlyIfConverterID)
245 return applyDisable(TargetID, DisableEarlyIfConversion);
246
247 if (StandardID == &EarlyMachineLICMID)
248 return applyDisable(TargetID, DisableMachineLICM);
249
250 if (StandardID == &MachineCSEID)
251 return applyDisable(TargetID, DisableMachineCSE);
252
253 if (StandardID == &MachineLICMID)
254 return applyDisable(TargetID, DisablePostRAMachineLICM);
255
256 if (StandardID == &MachineSinkingID)
257 return applyDisable(TargetID, DisableMachineSink);
258
259 if (StandardID == &PostRAMachineSinkingID)
260 return applyDisable(TargetID, DisablePostRAMachineSink);
261
262 if (StandardID == &MachineCopyPropagationID)
263 return applyDisable(TargetID, DisableCopyProp);
264
265 return TargetID;
266}
267
268//===---------------------------------------------------------------------===//
269/// TargetPassConfig
270//===---------------------------------------------------------------------===//
271
272INITIALIZE_PASS(TargetPassConfig, "targetpassconfig",static void *initializeTargetPassConfigPassOnce(PassRegistry &
Registry) { PassInfo *PI = new PassInfo( "Target Pass Configuration"
, "targetpassconfig", &TargetPassConfig::ID, PassInfo::NormalCtor_t
(callDefaultCtor<TargetPassConfig>), false, false); Registry
.registerPass(*PI, true); return PI; } static llvm::once_flag
InitializeTargetPassConfigPassFlag; void llvm::initializeTargetPassConfigPass
(PassRegistry &Registry) { llvm::call_once(InitializeTargetPassConfigPassFlag
, initializeTargetPassConfigPassOnce, std::ref(Registry)); }
273 "Target Pass Configuration", false, false)static void *initializeTargetPassConfigPassOnce(PassRegistry &
Registry) { PassInfo *PI = new PassInfo( "Target Pass Configuration"
, "targetpassconfig", &TargetPassConfig::ID, PassInfo::NormalCtor_t
(callDefaultCtor<TargetPassConfig>), false, false); Registry
.registerPass(*PI, true); return PI; } static llvm::once_flag
InitializeTargetPassConfigPassFlag; void llvm::initializeTargetPassConfigPass
(PassRegistry &Registry) { llvm::call_once(InitializeTargetPassConfigPassFlag
, initializeTargetPassConfigPassOnce, std::ref(Registry)); }
274char TargetPassConfig::ID = 0;
275
276namespace {
277
278struct InsertedPass {
279 AnalysisID TargetPassID;
280 IdentifyingPassPtr InsertedPassID;
281 bool VerifyAfter;
282 bool PrintAfter;
283
284 InsertedPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID,
285 bool VerifyAfter, bool PrintAfter)
286 : TargetPassID(TargetPassID), InsertedPassID(InsertedPassID),
287 VerifyAfter(VerifyAfter), PrintAfter(PrintAfter) {}
288
289 Pass *getInsertedPass() const {
290 assert(InsertedPassID.isValid() && "Illegal Pass ID!")(static_cast <bool> (InsertedPassID.isValid() &&
"Illegal Pass ID!") ? void (0) : __assert_fail ("InsertedPassID.isValid() && \"Illegal Pass ID!\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/TargetPassConfig.cpp"
, 290, __extension__ __PRETTY_FUNCTION__))
;
291 if (InsertedPassID.isInstance())
292 return InsertedPassID.getInstance();
293 Pass *NP = Pass::createPass(InsertedPassID.getID());
294 assert(NP && "Pass ID not registered")(static_cast <bool> (NP && "Pass ID not registered"
) ? void (0) : __assert_fail ("NP && \"Pass ID not registered\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/TargetPassConfig.cpp"
, 294, __extension__ __PRETTY_FUNCTION__))
;
295 return NP;
296 }
297};
298
299} // end anonymous namespace
300
301namespace llvm {
302
303class PassConfigImpl {
304public:
305 // List of passes explicitly substituted by this target. Normally this is
306 // empty, but it is a convenient way to suppress or replace specific passes
307 // that are part of a standard pass pipeline without overridding the entire
308 // pipeline. This mechanism allows target options to inherit a standard pass's
309 // user interface. For example, a target may disable a standard pass by
310 // default by substituting a pass ID of zero, and the user may still enable
311 // that standard pass with an explicit command line option.
312 DenseMap<AnalysisID,IdentifyingPassPtr> TargetPasses;
313
314 /// Store the pairs of <AnalysisID, AnalysisID> of which the second pass
315 /// is inserted after each instance of the first one.
316 SmallVector<InsertedPass, 4> InsertedPasses;
317};
318
319} // end namespace llvm
320
321// Out of line virtual method.
322TargetPassConfig::~TargetPassConfig() {
323 delete Impl;
324}
325
326static const PassInfo *getPassInfo(StringRef PassName) {
327 if (PassName.empty())
328 return nullptr;
329
330 const PassRegistry &PR = *PassRegistry::getPassRegistry();
331 const PassInfo *PI = PR.getPassInfo(PassName);
332 if (!PI)
333 report_fatal_error(Twine('\"') + Twine(PassName) +
334 Twine("\" pass is not registered."));
335 return PI;
336}
337
338static AnalysisID getPassIDFromName(StringRef PassName) {
339 const PassInfo *PI = getPassInfo(PassName);
340 return PI ? PI->getTypeInfo() : nullptr;
341}
342
343void TargetPassConfig::setStartStopPasses() {
344 StartBefore = getPassIDFromName(StartBeforeOpt);
345 StartAfter = getPassIDFromName(StartAfterOpt);
346 StopBefore = getPassIDFromName(StopBeforeOpt);
347 StopAfter = getPassIDFromName(StopAfterOpt);
348 if (StartBefore && StartAfter)
349 report_fatal_error(Twine(StartBeforeOptName) + Twine(" and ") +
350 Twine(StartAfterOptName) + Twine(" specified!"));
351 if (StopBefore && StopAfter)
352 report_fatal_error(Twine(StopBeforeOptName) + Twine(" and ") +
353 Twine(StopAfterOptName) + Twine(" specified!"));
354 Started = (StartAfter == nullptr) && (StartBefore == nullptr);
355}
356
357// Out of line constructor provides default values for pass options and
358// registers all common codegen passes.
359TargetPassConfig::TargetPassConfig(LLVMTargetMachine &TM, PassManagerBase &pm)
360 : ImmutablePass(ID), PM(&pm), TM(&TM) {
361 Impl = new PassConfigImpl();
362
363 // Register all target independent codegen passes to activate their PassIDs,
364 // including this pass itself.
365 initializeCodeGen(*PassRegistry::getPassRegistry());
366
367 // Also register alias analysis passes required by codegen passes.
368 initializeBasicAAWrapperPassPass(*PassRegistry::getPassRegistry());
369 initializeAAResultsWrapperPassPass(*PassRegistry::getPassRegistry());
370
371 if (StringRef(PrintMachineInstrs.getValue()).equals(""))
372 TM.Options.PrintMachineCode = true;
373
374 if (EnableIPRA.getNumOccurrences())
375 TM.Options.EnableIPRA = EnableIPRA;
376 else {
377 // If not explicitly specified, use target default.
378 TM.Options.EnableIPRA = TM.useIPRA();
379 }
380
381 if (TM.Options.EnableIPRA)
382 setRequiresCodeGenSCCOrder();
383
384 setStartStopPasses();
385}
386
387CodeGenOpt::Level TargetPassConfig::getOptLevel() const {
388 return TM->getOptLevel();
389}
390
391/// Insert InsertedPassID pass after TargetPassID.
392void TargetPassConfig::insertPass(AnalysisID TargetPassID,
393 IdentifyingPassPtr InsertedPassID,
394 bool VerifyAfter, bool PrintAfter) {
395 assert(((!InsertedPassID.isInstance() &&(static_cast <bool> (((!InsertedPassID.isInstance() &&
TargetPassID != InsertedPassID.getID()) || (InsertedPassID.isInstance
() && TargetPassID != InsertedPassID.getInstance()->
getPassID())) && "Insert a pass after itself!") ? void
(0) : __assert_fail ("((!InsertedPassID.isInstance() && TargetPassID != InsertedPassID.getID()) || (InsertedPassID.isInstance() && TargetPassID != InsertedPassID.getInstance()->getPassID())) && \"Insert a pass after itself!\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/TargetPassConfig.cpp"
, 399, __extension__ __PRETTY_FUNCTION__))
396 TargetPassID != InsertedPassID.getID()) ||(static_cast <bool> (((!InsertedPassID.isInstance() &&
TargetPassID != InsertedPassID.getID()) || (InsertedPassID.isInstance
() && TargetPassID != InsertedPassID.getInstance()->
getPassID())) && "Insert a pass after itself!") ? void
(0) : __assert_fail ("((!InsertedPassID.isInstance() && TargetPassID != InsertedPassID.getID()) || (InsertedPassID.isInstance() && TargetPassID != InsertedPassID.getInstance()->getPassID())) && \"Insert a pass after itself!\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/TargetPassConfig.cpp"
, 399, __extension__ __PRETTY_FUNCTION__))
397 (InsertedPassID.isInstance() &&(static_cast <bool> (((!InsertedPassID.isInstance() &&
TargetPassID != InsertedPassID.getID()) || (InsertedPassID.isInstance
() && TargetPassID != InsertedPassID.getInstance()->
getPassID())) && "Insert a pass after itself!") ? void
(0) : __assert_fail ("((!InsertedPassID.isInstance() && TargetPassID != InsertedPassID.getID()) || (InsertedPassID.isInstance() && TargetPassID != InsertedPassID.getInstance()->getPassID())) && \"Insert a pass after itself!\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/TargetPassConfig.cpp"
, 399, __extension__ __PRETTY_FUNCTION__))
398 TargetPassID != InsertedPassID.getInstance()->getPassID())) &&(static_cast <bool> (((!InsertedPassID.isInstance() &&
TargetPassID != InsertedPassID.getID()) || (InsertedPassID.isInstance
() && TargetPassID != InsertedPassID.getInstance()->
getPassID())) && "Insert a pass after itself!") ? void
(0) : __assert_fail ("((!InsertedPassID.isInstance() && TargetPassID != InsertedPassID.getID()) || (InsertedPassID.isInstance() && TargetPassID != InsertedPassID.getInstance()->getPassID())) && \"Insert a pass after itself!\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/TargetPassConfig.cpp"
, 399, __extension__ __PRETTY_FUNCTION__))
399 "Insert a pass after itself!")(static_cast <bool> (((!InsertedPassID.isInstance() &&
TargetPassID != InsertedPassID.getID()) || (InsertedPassID.isInstance
() && TargetPassID != InsertedPassID.getInstance()->
getPassID())) && "Insert a pass after itself!") ? void
(0) : __assert_fail ("((!InsertedPassID.isInstance() && TargetPassID != InsertedPassID.getID()) || (InsertedPassID.isInstance() && TargetPassID != InsertedPassID.getInstance()->getPassID())) && \"Insert a pass after itself!\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/TargetPassConfig.cpp"
, 399, __extension__ __PRETTY_FUNCTION__))
;
400 Impl->InsertedPasses.emplace_back(TargetPassID, InsertedPassID, VerifyAfter,
401 PrintAfter);
402}
403
404/// createPassConfig - Create a pass configuration object to be used by
405/// addPassToEmitX methods for generating a pipeline of CodeGen passes.
406///
407/// Targets may override this to extend TargetPassConfig.
408TargetPassConfig *LLVMTargetMachine::createPassConfig(PassManagerBase &PM) {
409 return new TargetPassConfig(*this, PM);
410}
411
412TargetPassConfig::TargetPassConfig()
413 : ImmutablePass(ID) {
414 report_fatal_error("Trying to construct TargetPassConfig without a target "
415 "machine. Scheduling a CodeGen pass without a target "
416 "triple set?");
417}
418
419bool TargetPassConfig::hasLimitedCodeGenPipeline() const {
420 return StartBefore || StartAfter || StopBefore || StopAfter;
421}
422
423std::string
424TargetPassConfig::getLimitedCodeGenPipelineReason(const char *Separator) const {
425 if (!hasLimitedCodeGenPipeline())
426 return std::string();
427 std::string Res;
428 static cl::opt<std::string> *PassNames[] = {&StartAfterOpt, &StartBeforeOpt,
429 &StopAfterOpt, &StopBeforeOpt};
430 static const char *OptNames[] = {StartAfterOptName, StartBeforeOptName,
431 StopAfterOptName, StopBeforeOptName};
432 bool IsFirst = true;
433 for (int Idx = 0; Idx < 4; ++Idx)
434 if (!PassNames[Idx]->empty()) {
435 if (!IsFirst)
436 Res += Separator;
437 IsFirst = false;
438 Res += OptNames[Idx];
439 }
440 return Res;
441}
442
443// Helper to verify the analysis is really immutable.
444void TargetPassConfig::setOpt(bool &Opt, bool Val) {
445 assert(!Initialized && "PassConfig is immutable")(static_cast <bool> (!Initialized && "PassConfig is immutable"
) ? void (0) : __assert_fail ("!Initialized && \"PassConfig is immutable\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/TargetPassConfig.cpp"
, 445, __extension__ __PRETTY_FUNCTION__))
;
446 Opt = Val;
447}
448
449void TargetPassConfig::substitutePass(AnalysisID StandardID,
450 IdentifyingPassPtr TargetID) {
451 Impl->TargetPasses[StandardID] = TargetID;
452}
453
454IdentifyingPassPtr TargetPassConfig::getPassSubstitution(AnalysisID ID) const {
455 DenseMap<AnalysisID, IdentifyingPassPtr>::const_iterator
456 I = Impl->TargetPasses.find(ID);
457 if (I == Impl->TargetPasses.end())
458 return ID;
459 return I->second;
460}
461
462bool TargetPassConfig::isPassSubstitutedOrOverridden(AnalysisID ID) const {
463 IdentifyingPassPtr TargetID = getPassSubstitution(ID);
464 IdentifyingPassPtr FinalPtr = overridePass(ID, TargetID);
465 return !FinalPtr.isValid() || FinalPtr.isInstance() ||
466 FinalPtr.getID() != ID;
467}
468
469/// Add a pass to the PassManager if that pass is supposed to be run. If the
470/// Started/Stopped flags indicate either that the compilation should start at
471/// a later pass or that it should stop after an earlier pass, then do not add
472/// the pass. Finally, compare the current pass against the StartAfter
473/// and StopAfter options and change the Started/Stopped flags accordingly.
474void TargetPassConfig::addPass(Pass *P, bool verifyAfter, bool printAfter) {
475 assert(!Initialized && "PassConfig is immutable")(static_cast <bool> (!Initialized && "PassConfig is immutable"
) ? void (0) : __assert_fail ("!Initialized && \"PassConfig is immutable\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/TargetPassConfig.cpp"
, 475, __extension__ __PRETTY_FUNCTION__))
;
476
477 // Cache the Pass ID here in case the pass manager finds this pass is
478 // redundant with ones already scheduled / available, and deletes it.
479 // Fundamentally, once we add the pass to the manager, we no longer own it
480 // and shouldn't reference it.
481 AnalysisID PassID = P->getPassID();
482
483 if (StartBefore == PassID)
484 Started = true;
485 if (StopBefore == PassID)
486 Stopped = true;
487 if (Started && !Stopped) {
488 std::string Banner;
489 // Construct banner message before PM->add() as that may delete the pass.
490 if (AddingMachinePasses && (printAfter || verifyAfter))
491 Banner = std::string("After ") + std::string(P->getPassName());
492 PM->add(P);
493 if (AddingMachinePasses) {
494 if (printAfter)
495 addPrintPass(Banner);
496 if (verifyAfter)
497 addVerifyPass(Banner);
498 }
499
500 // Add the passes after the pass P if there is any.
501 for (auto IP : Impl->InsertedPasses) {
502 if (IP.TargetPassID == PassID)
503 addPass(IP.getInsertedPass(), IP.VerifyAfter, IP.PrintAfter);
504 }
505 } else {
506 delete P;
507 }
508 if (StopAfter == PassID)
509 Stopped = true;
510 if (StartAfter == PassID)
511 Started = true;
512 if (Stopped && !Started)
513 report_fatal_error("Cannot stop compilation after pass that is not run");
514}
515
516/// Add a CodeGen pass at this point in the pipeline after checking for target
517/// and command line overrides.
518///
519/// addPass cannot return a pointer to the pass instance because is internal the
520/// PassManager and the instance we create here may already be freed.
521AnalysisID TargetPassConfig::addPass(AnalysisID PassID, bool verifyAfter,
522 bool printAfter) {
523 IdentifyingPassPtr TargetID = getPassSubstitution(PassID);
524 IdentifyingPassPtr FinalPtr = overridePass(PassID, TargetID);
525 if (!FinalPtr.isValid())
526 return nullptr;
527
528 Pass *P;
529 if (FinalPtr.isInstance())
530 P = FinalPtr.getInstance();
531 else {
532 P = Pass::createPass(FinalPtr.getID());
533 if (!P)
534 llvm_unreachable("Pass ID not registered")::llvm::llvm_unreachable_internal("Pass ID not registered", "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/TargetPassConfig.cpp"
, 534)
;
535 }
536 AnalysisID FinalID = P->getPassID();
537 addPass(P, verifyAfter, printAfter); // Ends the lifetime of P.
538
539 return FinalID;
540}
541
542void TargetPassConfig::printAndVerify(const std::string &Banner) {
543 addPrintPass(Banner);
544 addVerifyPass(Banner);
545}
546
547void TargetPassConfig::addPrintPass(const std::string &Banner) {
548 if (TM->shouldPrintMachineCode())
549 PM->add(createMachineFunctionPrinterPass(dbgs(), Banner));
550}
551
552void TargetPassConfig::addVerifyPass(const std::string &Banner) {
553 bool Verify = VerifyMachineCode;
554#ifdef EXPENSIVE_CHECKS
555 if (VerifyMachineCode == cl::BOU_UNSET)
556 Verify = TM->isMachineVerifierClean();
557#endif
558 if (Verify)
559 PM->add(createMachineVerifierPass(Banner));
560}
561
562/// Add common target configurable passes that perform LLVM IR to IR transforms
563/// following machine independent optimization.
564void TargetPassConfig::addIRPasses() {
565 switch (UseCFLAA) {
566 case CFLAAType::Steensgaard:
567 addPass(createCFLSteensAAWrapperPass());
568 break;
569 case CFLAAType::Andersen:
570 addPass(createCFLAndersAAWrapperPass());
571 break;
572 case CFLAAType::Both:
573 addPass(createCFLAndersAAWrapperPass());
574 addPass(createCFLSteensAAWrapperPass());
575 break;
576 default:
577 break;
578 }
579
580 // Basic AliasAnalysis support.
581 // Add TypeBasedAliasAnalysis before BasicAliasAnalysis so that
582 // BasicAliasAnalysis wins if they disagree. This is intended to help
583 // support "obvious" type-punning idioms.
584 addPass(createTypeBasedAAWrapperPass());
585 addPass(createScopedNoAliasAAWrapperPass());
586 addPass(createBasicAAWrapperPass());
587
588 // Before running any passes, run the verifier to determine if the input
589 // coming from the front-end and/or optimizer is valid.
590 if (!DisableVerify)
591 addPass(createVerifierPass());
592
593 // Run loop strength reduction before anything else.
594 if (getOptLevel() != CodeGenOpt::None && !DisableLSR) {
595 addPass(createLoopStrengthReducePass());
596 if (PrintLSR)
597 addPass(createPrintFunctionPass(dbgs(), "\n\n*** Code after LSR ***\n"));
598 }
599
600 if (getOptLevel() != CodeGenOpt::None) {
601 // The MergeICmpsPass tries to create memcmp calls by grouping sequences of
602 // loads and compares. ExpandMemCmpPass then tries to expand those calls
603 // into optimally-sized loads and compares. The transforms are enabled by a
604 // target lowering hook.
605 if (!DisableMergeICmps)
606 addPass(createMergeICmpsPass());
607 addPass(createExpandMemCmpPass());
608 }
609
610 // Run GC lowering passes for builtin collectors
611 // TODO: add a pass insertion point here
612 addPass(createGCLoweringPass());
613 addPass(createShadowStackGCLoweringPass());
614
615 // Make sure that no unreachable blocks are instruction selected.
616 addPass(createUnreachableBlockEliminationPass());
617
618 // Prepare expensive constants for SelectionDAG.
619 if (getOptLevel() != CodeGenOpt::None && !DisableConstantHoisting)
620 addPass(createConstantHoistingPass());
621
622 if (getOptLevel() != CodeGenOpt::None && !DisablePartialLibcallInlining)
623 addPass(createPartiallyInlineLibCallsPass());
624
625 // Instrument function entry and exit, e.g. with calls to mcount().
626 addPass(createPostInlineEntryExitInstrumenterPass());
627
628 // Add scalarization of target's unsupported masked memory intrinsics pass.
629 // the unsupported intrinsic will be replaced with a chain of basic blocks,
630 // that stores/loads element one-by-one if the appropriate mask bit is set.
631 addPass(createScalarizeMaskedMemIntrinPass());
632
633 // Expand reduction intrinsics into shuffle sequences if the target wants to.
634 addPass(createExpandReductionsPass());
635}
636
637/// Turn exception handling constructs into something the code generators can
638/// handle.
639void TargetPassConfig::addPassesToHandleExceptions() {
640 const MCAsmInfo *MCAI = TM->getMCAsmInfo();
641 assert(MCAI && "No MCAsmInfo")(static_cast <bool> (MCAI && "No MCAsmInfo") ? void
(0) : __assert_fail ("MCAI && \"No MCAsmInfo\"", "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/TargetPassConfig.cpp"
, 641, __extension__ __PRETTY_FUNCTION__))
;
642 switch (MCAI->getExceptionHandlingType()) {
643 case ExceptionHandling::SjLj:
644 // SjLj piggy-backs on dwarf for this bit. The cleanups done apply to both
645 // Dwarf EH prepare needs to be run after SjLj prepare. Otherwise,
646 // catch info can get misplaced when a selector ends up more than one block
647 // removed from the parent invoke(s). This could happen when a landing
648 // pad is shared by multiple invokes and is also a target of a normal
649 // edge from elsewhere.
650 addPass(createSjLjEHPreparePass());
651 LLVM_FALLTHROUGH[[clang::fallthrough]];
652 case ExceptionHandling::DwarfCFI:
653 case ExceptionHandling::ARM:
654 addPass(createDwarfEHPass());
655 break;
656 case ExceptionHandling::WinEH:
657 // We support using both GCC-style and MSVC-style exceptions on Windows, so
658 // add both preparation passes. Each pass will only actually run if it
659 // recognizes the personality function.
660 addPass(createWinEHPass());
661 addPass(createDwarfEHPass());
662 break;
663 case ExceptionHandling::Wasm:
664 // TODO to prevent warning
665 break;
666 case ExceptionHandling::None:
667 addPass(createLowerInvokePass());
668
669 // The lower invoke pass may create unreachable code. Remove it.
670 addPass(createUnreachableBlockEliminationPass());
671 break;
672 }
673}
674
675/// Add pass to prepare the LLVM IR for code generation. This should be done
676/// before exception handling preparation passes.
677void TargetPassConfig::addCodeGenPrepare() {
678 if (getOptLevel() != CodeGenOpt::None && !DisableCGP)
679 addPass(createCodeGenPreparePass());
680 addPass(createRewriteSymbolsPass());
681}
682
683/// Add common passes that perform LLVM IR to IR transforms in preparation for
684/// instruction selection.
685void TargetPassConfig::addISelPrepare() {
686 addPreISel();
687
688 // Force codegen to run according to the callgraph.
689 if (requiresCodeGenSCCOrder())
690 addPass(new DummyCGSCCPass);
691
692 // Add both the safe stack and the stack protection passes: each of them will
693 // only protect functions that have corresponding attributes.
694 addPass(createSafeStackPass());
695 addPass(createStackProtectorPass());
696
697 if (PrintISelInput)
698 addPass(createPrintFunctionPass(
699 dbgs(), "\n\n*** Final LLVM Code input to ISel ***\n"));
700
701 // All passes which modify the LLVM IR are now complete; run the verifier
702 // to ensure that the IR is valid.
703 if (!DisableVerify)
704 addPass(createVerifierPass());
705}
706
707bool TargetPassConfig::addCoreISelPasses() {
708 // Enable FastISel with -fast-isel, but allow that to be overridden.
709 TM->setO0WantsFastISel(EnableFastISelOption != cl::BOU_FALSE);
710 if (EnableFastISelOption == cl::BOU_TRUE ||
711 (TM->getOptLevel() == CodeGenOpt::None && TM->getO0WantsFastISel()))
712 TM->setFastISel(true);
713
714 // Ask the target for an instruction selector.
715 // Explicitly enabling fast-isel should override implicitly enabled
716 // global-isel.
717 if (EnableGlobalISelOption == cl::BOU_TRUE ||
718 (EnableGlobalISelOption == cl::BOU_UNSET &&
719 TM->Options.EnableGlobalISel && EnableFastISelOption != cl::BOU_TRUE)) {
720 TM->setFastISel(false);
721
722 if (addIRTranslator())
723 return true;
724
725 addPreLegalizeMachineIR();
726
727 if (addLegalizeMachineIR())
728 return true;
729
730 // Before running the register bank selector, ask the target if it
731 // wants to run some passes.
732 addPreRegBankSelect();
733
734 if (addRegBankSelect())
735 return true;
736
737 addPreGlobalInstructionSelect();
738
739 if (addGlobalInstructionSelect())
740 return true;
741
742 // Pass to reset the MachineFunction if the ISel failed.
743 addPass(createResetMachineFunctionPass(
744 reportDiagnosticWhenGlobalISelFallback(), isGlobalISelAbortEnabled()));
745
746 // Provide a fallback path when we do not want to abort on
747 // not-yet-supported input.
748 if (!isGlobalISelAbortEnabled() && addInstSelector())
749 return true;
750
751 } else if (addInstSelector())
752 return true;
753
754 return false;
755}
756
757bool TargetPassConfig::addISelPasses() {
758 if (TM->useEmulatedTLS())
759 addPass(createLowerEmuTLSPass());
760
761 addPass(createPreISelIntrinsicLoweringPass());
762 addPass(createTargetTransformInfoWrapperPass(TM->getTargetIRAnalysis()));
763 addIRPasses();
764 addCodeGenPrepare();
765 addPassesToHandleExceptions();
766 addISelPrepare();
767
768 return addCoreISelPasses();
769}
770
771/// -regalloc=... command line option.
772static FunctionPass *useDefaultRegisterAllocator() { return nullptr; }
773static cl::opt<RegisterRegAlloc::FunctionPassCtor, false,
774 RegisterPassParser<RegisterRegAlloc>>
775 RegAlloc("regalloc", cl::Hidden, cl::init(&useDefaultRegisterAllocator),
776 cl::desc("Register allocator to use"));
777
778/// Add the complete set of target-independent postISel code generator passes.
779///
780/// This can be read as the standard order of major LLVM CodeGen stages. Stages
781/// with nontrivial configuration or multiple passes are broken out below in
782/// add%Stage routines.
783///
784/// Any TargetPassConfig::addXX routine may be overriden by the Target. The
785/// addPre/Post methods with empty header implementations allow injecting
786/// target-specific fixups just before or after major stages. Additionally,
787/// targets have the flexibility to change pass order within a stage by
788/// overriding default implementation of add%Stage routines below. Each
789/// technique has maintainability tradeoffs because alternate pass orders are
790/// not well supported. addPre/Post works better if the target pass is easily
791/// tied to a common pass. But if it has subtle dependencies on multiple passes,
792/// the target should override the stage instead.
793///
794/// TODO: We could use a single addPre/Post(ID) hook to allow pass injection
795/// before/after any target-independent pass. But it's currently overkill.
796void TargetPassConfig::addMachinePasses() {
797 AddingMachinePasses = true;
798
799 // Insert a machine instr printer pass after the specified pass.
800 if (!StringRef(PrintMachineInstrs.getValue()).equals("") &&
801 !StringRef(PrintMachineInstrs.getValue()).equals("option-unspecified")) {
802 const PassRegistry *PR = PassRegistry::getPassRegistry();
803 const PassInfo *TPI = PR->getPassInfo(PrintMachineInstrs.getValue());
804 const PassInfo *IPI = PR->getPassInfo(StringRef("machineinstr-printer"));
805 assert (TPI && IPI && "Pass ID not registered!")(static_cast <bool> (TPI && IPI && "Pass ID not registered!"
) ? void (0) : __assert_fail ("TPI && IPI && \"Pass ID not registered!\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/TargetPassConfig.cpp"
, 805, __extension__ __PRETTY_FUNCTION__))
;
806 const char *TID = (const char *)(TPI->getTypeInfo());
807 const char *IID = (const char *)(IPI->getTypeInfo());
808 insertPass(TID, IID);
809 }
810
811 // Print the instruction selected machine code...
812 printAndVerify("After Instruction Selection");
813
814 // Expand pseudo-instructions emitted by ISel.
815 addPass(&ExpandISelPseudosID);
816
817 // Add passes that optimize machine instructions in SSA form.
818 if (getOptLevel() != CodeGenOpt::None) {
819 addMachineSSAOptimization();
820 } else {
821 // If the target requests it, assign local variables to stack slots relative
822 // to one another and simplify frame index references where possible.
823 addPass(&LocalStackSlotAllocationID, false);
824 }
825
826 if (TM->Options.EnableIPRA)
827 addPass(createRegUsageInfoPropPass());
828
829 // Run pre-ra passes.
830 addPreRegAlloc();
831
832 // Run register allocation and passes that are tightly coupled with it,
833 // including phi elimination and scheduling.
834 if (getOptimizeRegAlloc())
835 addOptimizedRegAlloc(createRegAllocPass(true));
836 else {
837 if (RegAlloc != &useDefaultRegisterAllocator &&
838 RegAlloc != &createFastRegisterAllocator)
839 report_fatal_error("Must use fast (default) register allocator for unoptimized regalloc.");
840 addFastRegAlloc(createRegAllocPass(false));
841 }
842
843 // Run post-ra passes.
844 addPostRegAlloc();
845
846 // Insert prolog/epilog code. Eliminate abstract frame index references...
847 if (getOptLevel() != CodeGenOpt::None) {
848 addPass(&PostRAMachineSinkingID);
849 addPass(&ShrinkWrapID);
850 }
851
852 // Prolog/Epilog inserter needs a TargetMachine to instantiate. But only
853 // do so if it hasn't been disabled, substituted, or overridden.
854 if (!isPassSubstitutedOrOverridden(&PrologEpilogCodeInserterID))
855 addPass(createPrologEpilogInserterPass());
856
857 /// Add passes that optimize machine instructions after register allocation.
858 if (getOptLevel() != CodeGenOpt::None)
859 addMachineLateOptimization();
860
861 // Expand pseudo instructions before second scheduling pass.
862 addPass(&ExpandPostRAPseudosID);
863
864 // Run pre-sched2 passes.
865 addPreSched2();
866
867 if (EnableImplicitNullChecks)
868 addPass(&ImplicitNullChecksID);
869
870 // Second pass scheduler.
871 // Let Target optionally insert this pass by itself at some other
872 // point.
873 if (getOptLevel() != CodeGenOpt::None &&
874 !TM->targetSchedulesPostRAScheduling()) {
875 if (MISchedPostRA)
876 addPass(&PostMachineSchedulerID);
877 else
878 addPass(&PostRASchedulerID);
879 }
880
881 // GC
882 if (addGCPasses()) {
883 if (PrintGCInfo)
884 addPass(createGCInfoPrinter(dbgs()), false, false);
885 }
886
887 // Basic block placement.
888 if (getOptLevel() != CodeGenOpt::None)
889 addBlockPlacement();
890
891 addPreEmitPass();
892
893 if (TM->Options.EnableIPRA)
894 // Collect register usage information and produce a register mask of
895 // clobbered registers, to be used to optimize call sites.
896 addPass(createRegUsageInfoCollector());
897
898 addPass(&FuncletLayoutID, false);
899
900 addPass(&StackMapLivenessID, false);
901 addPass(&LiveDebugValuesID, false);
902
903 // Insert before XRay Instrumentation.
904 addPass(&FEntryInserterID, false);
905
906 addPass(&XRayInstrumentationID, false);
907 addPass(&PatchableFunctionID, false);
908
909 if (EnableMachineOutliner)
910 PM->add(createMachineOutlinerPass(EnableLinkOnceODROutlining));
911
912 // Add passes that directly emit MI after all other MI passes.
913 addPreEmitPass2();
914
915 AddingMachinePasses = false;
916}
917
918/// Add passes that optimize machine instructions in SSA form.
919void TargetPassConfig::addMachineSSAOptimization() {
920 // Pre-ra tail duplication.
921 addPass(&EarlyTailDuplicateID);
922
923 // Optimize PHIs before DCE: removing dead PHI cycles may make more
924 // instructions dead.
925 addPass(&OptimizePHIsID, false);
926
927 // This pass merges large allocas. StackSlotColoring is a different pass
928 // which merges spill slots.
929 addPass(&StackColoringID, false);
930
931 // If the target requests it, assign local variables to stack slots relative
932 // to one another and simplify frame index references where possible.
933 addPass(&LocalStackSlotAllocationID, false);
934
935 // With optimization, dead code should already be eliminated. However
936 // there is one known exception: lowered code for arguments that are only
937 // used by tail calls, where the tail calls reuse the incoming stack
938 // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
939 addPass(&DeadMachineInstructionElimID);
940
941 // Allow targets to insert passes that improve instruction level parallelism,
942 // like if-conversion. Such passes will typically need dominator trees and
943 // loop info, just like LICM and CSE below.
944 addILPOpts();
945
946 addPass(&EarlyMachineLICMID, false);
947 addPass(&MachineCSEID, false);
948
949 addPass(&MachineSinkingID);
950
951 addPass(&PeepholeOptimizerID);
952 // Clean-up the dead code that may have been generated by peephole
953 // rewriting.
954 addPass(&DeadMachineInstructionElimID);
955}
956
957//===---------------------------------------------------------------------===//
958/// Register Allocation Pass Configuration
959//===---------------------------------------------------------------------===//
960
961bool TargetPassConfig::getOptimizeRegAlloc() const {
962 switch (OptimizeRegAlloc) {
963 case cl::BOU_UNSET: return getOptLevel() != CodeGenOpt::None;
964 case cl::BOU_TRUE: return true;
965 case cl::BOU_FALSE: return false;
966 }
967 llvm_unreachable("Invalid optimize-regalloc state")::llvm::llvm_unreachable_internal("Invalid optimize-regalloc state"
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/TargetPassConfig.cpp"
, 967)
;
968}
969
970/// RegisterRegAlloc's global Registry tracks allocator registration.
971MachinePassRegistry RegisterRegAlloc::Registry;
972
973/// A dummy default pass factory indicates whether the register allocator is
974/// overridden on the command line.
975static llvm::once_flag InitializeDefaultRegisterAllocatorFlag;
976
977static RegisterRegAlloc
978defaultRegAlloc("default",
979 "pick register allocator based on -O option",
980 useDefaultRegisterAllocator);
981
982static void initializeDefaultRegisterAllocatorOnce() {
983 RegisterRegAlloc::FunctionPassCtor Ctor = RegisterRegAlloc::getDefault();
984
985 if (!Ctor) {
986 Ctor = RegAlloc;
Value stored to 'Ctor' is never read
987 RegisterRegAlloc::setDefault(RegAlloc);
988 }
989}
990
991/// Instantiate the default register allocator pass for this target for either
992/// the optimized or unoptimized allocation path. This will be added to the pass
993/// manager by addFastRegAlloc in the unoptimized case or addOptimizedRegAlloc
994/// in the optimized case.
995///
996/// A target that uses the standard regalloc pass order for fast or optimized
997/// allocation may still override this for per-target regalloc
998/// selection. But -regalloc=... always takes precedence.
999FunctionPass *TargetPassConfig::createTargetRegisterAllocator(bool Optimized) {
1000 if (Optimized)
1001 return createGreedyRegisterAllocator();
1002 else
1003 return createFastRegisterAllocator();
1004}
1005
1006/// Find and instantiate the register allocation pass requested by this target
1007/// at the current optimization level. Different register allocators are
1008/// defined as separate passes because they may require different analysis.
1009///
1010/// This helper ensures that the regalloc= option is always available,
1011/// even for targets that override the default allocator.
1012///
1013/// FIXME: When MachinePassRegistry register pass IDs instead of function ptrs,
1014/// this can be folded into addPass.
1015FunctionPass *TargetPassConfig::createRegAllocPass(bool Optimized) {
1016 // Initialize the global default.
1017 llvm::call_once(InitializeDefaultRegisterAllocatorFlag,
1018 initializeDefaultRegisterAllocatorOnce);
1019
1020 RegisterRegAlloc::FunctionPassCtor Ctor = RegisterRegAlloc::getDefault();
1021 if (Ctor != useDefaultRegisterAllocator)
1022 return Ctor();
1023
1024 // With no -regalloc= override, ask the target for a regalloc pass.
1025 return createTargetRegisterAllocator(Optimized);
1026}
1027
1028/// Return true if the default global register allocator is in use and
1029/// has not be overriden on the command line with '-regalloc=...'
1030bool TargetPassConfig::usingDefaultRegAlloc() const {
1031 return RegAlloc.getNumOccurrences() == 0;
1032}
1033
1034/// Add the minimum set of target-independent passes that are required for
1035/// register allocation. No coalescing or scheduling.
1036void TargetPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
1037 addPass(&PHIEliminationID, false);
1038 addPass(&TwoAddressInstructionPassID, false);
1039
1040 if (RegAllocPass)
1041 addPass(RegAllocPass);
1042}
1043
1044/// Add standard target-independent passes that are tightly coupled with
1045/// optimized register allocation, including coalescing, machine instruction
1046/// scheduling, and register allocation itself.
1047void TargetPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
1048 addPass(&DetectDeadLanesID, false);
1049
1050 addPass(&ProcessImplicitDefsID, false);
1051
1052 // LiveVariables currently requires pure SSA form.
1053 //
1054 // FIXME: Once TwoAddressInstruction pass no longer uses kill flags,
1055 // LiveVariables can be removed completely, and LiveIntervals can be directly
1056 // computed. (We still either need to regenerate kill flags after regalloc, or
1057 // preferably fix the scavenger to not depend on them).
1058 addPass(&LiveVariablesID, false);
1059
1060 // Edge splitting is smarter with machine loop info.
1061 addPass(&MachineLoopInfoID, false);
1062 addPass(&PHIEliminationID, false);
1063
1064 // Eventually, we want to run LiveIntervals before PHI elimination.
1065 if (EarlyLiveIntervals)
1066 addPass(&LiveIntervalsID, false);
1067
1068 addPass(&TwoAddressInstructionPassID, false);
1069 addPass(&RegisterCoalescerID);
1070
1071 // The machine scheduler may accidentally create disconnected components
1072 // when moving subregister definitions around, avoid this by splitting them to
1073 // separate vregs before. Splitting can also improve reg. allocation quality.
1074 addPass(&RenameIndependentSubregsID);
1075
1076 // PreRA instruction scheduling.
1077 addPass(&MachineSchedulerID);
1078
1079 if (RegAllocPass) {
1080 // Add the selected register allocation pass.
1081 addPass(RegAllocPass);
1082
1083 // Allow targets to change the register assignments before rewriting.
1084 addPreRewrite();
1085
1086 // Finally rewrite virtual registers.
1087 addPass(&VirtRegRewriterID);
1088
1089 // Perform stack slot coloring and post-ra machine LICM.
1090 //
1091 // FIXME: Re-enable coloring with register when it's capable of adding
1092 // kill markers.
1093 addPass(&StackSlotColoringID);
1094
1095 // Copy propagate to forward register uses and try to eliminate COPYs that
1096 // were not coalesced.
1097 addPass(&MachineCopyPropagationID);
1098
1099 // Run post-ra machine LICM to hoist reloads / remats.
1100 //
1101 // FIXME: can this move into MachineLateOptimization?
1102 addPass(&MachineLICMID);
1103 }
1104}
1105
1106//===---------------------------------------------------------------------===//
1107/// Post RegAlloc Pass Configuration
1108//===---------------------------------------------------------------------===//
1109
1110/// Add passes that optimize machine instructions after register allocation.
1111void TargetPassConfig::addMachineLateOptimization() {
1112 // Branch folding must be run after regalloc and prolog/epilog insertion.
1113 addPass(&BranchFolderPassID);
1114
1115 // Tail duplication.
1116 // Note that duplicating tail just increases code size and degrades
1117 // performance for targets that require Structured Control Flow.
1118 // In addition it can also make CFG irreducible. Thus we disable it.
1119 if (!TM->requiresStructuredCFG())
1120 addPass(&TailDuplicateID);
1121
1122 // Copy propagation.
1123 addPass(&MachineCopyPropagationID);
1124}
1125
1126/// Add standard GC passes.
1127bool TargetPassConfig::addGCPasses() {
1128 addPass(&GCMachineCodeAnalysisID, false);
1129 return true;
1130}
1131
1132/// Add standard basic block placement passes.
1133void TargetPassConfig::addBlockPlacement() {
1134 if (addPass(&MachineBlockPlacementID)) {
1135 // Run a separate pass to collect block placement statistics.
1136 if (EnableBlockPlacementStats)
1137 addPass(&MachineBlockPlacementStatsID);
1138 }
1139}
1140
1141//===---------------------------------------------------------------------===//
1142/// GlobalISel Configuration
1143//===---------------------------------------------------------------------===//
1144bool TargetPassConfig::isGlobalISelAbortEnabled() const {
1145 if (EnableGlobalISelAbort.getNumOccurrences() > 0)
1146 return EnableGlobalISelAbort == 1;
1147
1148 // When no abort behaviour is specified, we don't abort if the target says
1149 // that GISel is enabled.
1150 return !TM->Options.EnableGlobalISel;
1151}
1152
1153bool TargetPassConfig::reportDiagnosticWhenGlobalISelFallback() const {
1154 return EnableGlobalISelAbort == 2;
1155}