Bug Summary

File:lib/Target/X86/X86CmovConversion.cpp
Warning:line 309, column 37
The right operand of '!=' is a garbage value

Annotated Source Code

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clang -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name X86CmovConversion.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-config-compatibility-mode=true -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -mrelocation-model pic -pic-level 2 -mthread-model posix -fmath-errno -masm-verbose -mconstructor-aliases -munwind-tables -fuse-init-array -target-cpu x86-64 -dwarf-column-info -debugger-tuning=gdb -momit-leaf-frame-pointer -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-8/lib/clang/8.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-8~svn348900/build-llvm/lib/Target/X86 -I /build/llvm-toolchain-snapshot-8~svn348900/lib/Target/X86 -I /build/llvm-toolchain-snapshot-8~svn348900/build-llvm/include -I /build/llvm-toolchain-snapshot-8~svn348900/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0/backward -internal-isystem /usr/include/clang/8.0.0/include/ -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-8/lib/clang/8.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-command-line-argument -Wno-unknown-warning-option -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++11 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-8~svn348900/build-llvm/lib/Target/X86 -ferror-limit 19 -fmessage-length 0 -fvisibility-inlines-hidden -fobjc-runtime=gcc -fdiagnostics-show-option -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -o /tmp/scan-build-2018-12-12-042652-12204-1 -x c++ /build/llvm-toolchain-snapshot-8~svn348900/lib/Target/X86/X86CmovConversion.cpp -faddrsig
1//====- X86CmovConversion.cpp - Convert Cmov to Branch --------------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10/// \file
11/// This file implements a pass that converts X86 cmov instructions into
12/// branches when profitable. This pass is conservative. It transforms if and
13/// only if it can guarantee a gain with high confidence.
14///
15/// Thus, the optimization applies under the following conditions:
16/// 1. Consider as candidates only CMOVs in innermost loops (assume that
17/// most hotspots are represented by these loops).
18/// 2. Given a group of CMOV instructions that are using the same EFLAGS def
19/// instruction:
20/// a. Consider them as candidates only if all have the same code condition
21/// or the opposite one to prevent generating more than one conditional
22/// jump per EFLAGS def instruction.
23/// b. Consider them as candidates only if all are profitable to be
24/// converted (assume that one bad conversion may cause a degradation).
25/// 3. Apply conversion only for loops that are found profitable and only for
26/// CMOV candidates that were found profitable.
27/// a. A loop is considered profitable only if conversion will reduce its
28/// depth cost by some threshold.
29/// b. CMOV is considered profitable if the cost of its condition is higher
30/// than the average cost of its true-value and false-value by 25% of
31/// branch-misprediction-penalty. This assures no degradation even with
32/// 25% branch misprediction.
33///
34/// Note: This pass is assumed to run on SSA machine code.
35//
36//===----------------------------------------------------------------------===//
37//
38// External interfaces:
39// FunctionPass *llvm::createX86CmovConverterPass();
40// bool X86CmovConverterPass::runOnMachineFunction(MachineFunction &MF);
41//
42//===----------------------------------------------------------------------===//
43
44#include "X86.h"
45#include "X86InstrInfo.h"
46#include "llvm/ADT/ArrayRef.h"
47#include "llvm/ADT/DenseMap.h"
48#include "llvm/ADT/STLExtras.h"
49#include "llvm/ADT/SmallPtrSet.h"
50#include "llvm/ADT/SmallVector.h"
51#include "llvm/ADT/Statistic.h"
52#include "llvm/CodeGen/MachineBasicBlock.h"
53#include "llvm/CodeGen/MachineFunction.h"
54#include "llvm/CodeGen/MachineFunctionPass.h"
55#include "llvm/CodeGen/MachineInstr.h"
56#include "llvm/CodeGen/MachineInstrBuilder.h"
57#include "llvm/CodeGen/MachineLoopInfo.h"
58#include "llvm/CodeGen/MachineOperand.h"
59#include "llvm/CodeGen/MachineRegisterInfo.h"
60#include "llvm/CodeGen/TargetInstrInfo.h"
61#include "llvm/CodeGen/TargetRegisterInfo.h"
62#include "llvm/CodeGen/TargetSchedule.h"
63#include "llvm/CodeGen/TargetSubtargetInfo.h"
64#include "llvm/IR/DebugLoc.h"
65#include "llvm/MC/MCSchedule.h"
66#include "llvm/Pass.h"
67#include "llvm/Support/CommandLine.h"
68#include "llvm/Support/Debug.h"
69#include "llvm/Support/raw_ostream.h"
70#include <algorithm>
71#include <cassert>
72#include <iterator>
73#include <utility>
74
75using namespace llvm;
76
77#define DEBUG_TYPE"x86-cmov-conversion" "x86-cmov-conversion"
78
79STATISTIC(NumOfSkippedCmovGroups, "Number of unsupported CMOV-groups")static llvm::Statistic NumOfSkippedCmovGroups = {"x86-cmov-conversion"
, "NumOfSkippedCmovGroups", "Number of unsupported CMOV-groups"
, {0}, {false}}
;
80STATISTIC(NumOfCmovGroupCandidate, "Number of CMOV-group candidates")static llvm::Statistic NumOfCmovGroupCandidate = {"x86-cmov-conversion"
, "NumOfCmovGroupCandidate", "Number of CMOV-group candidates"
, {0}, {false}}
;
81STATISTIC(NumOfLoopCandidate, "Number of CMOV-conversion profitable loops")static llvm::Statistic NumOfLoopCandidate = {"x86-cmov-conversion"
, "NumOfLoopCandidate", "Number of CMOV-conversion profitable loops"
, {0}, {false}}
;
82STATISTIC(NumOfOptimizedCmovGroups, "Number of optimized CMOV-groups")static llvm::Statistic NumOfOptimizedCmovGroups = {"x86-cmov-conversion"
, "NumOfOptimizedCmovGroups", "Number of optimized CMOV-groups"
, {0}, {false}}
;
83
84// This internal switch can be used to turn off the cmov/branch optimization.
85static cl::opt<bool>
86 EnableCmovConverter("x86-cmov-converter",
87 cl::desc("Enable the X86 cmov-to-branch optimization."),
88 cl::init(true), cl::Hidden);
89
90static cl::opt<unsigned>
91 GainCycleThreshold("x86-cmov-converter-threshold",
92 cl::desc("Minimum gain per loop (in cycles) threshold."),
93 cl::init(4), cl::Hidden);
94
95static cl::opt<bool> ForceMemOperand(
96 "x86-cmov-converter-force-mem-operand",
97 cl::desc("Convert cmovs to branches whenever they have memory operands."),
98 cl::init(true), cl::Hidden);
99
100namespace {
101
102/// Converts X86 cmov instructions into branches when profitable.
103class X86CmovConverterPass : public MachineFunctionPass {
104public:
105 X86CmovConverterPass() : MachineFunctionPass(ID) {
106 initializeX86CmovConverterPassPass(*PassRegistry::getPassRegistry());
107 }
108
109 StringRef getPassName() const override { return "X86 cmov Conversion"; }
110 bool runOnMachineFunction(MachineFunction &MF) override;
111 void getAnalysisUsage(AnalysisUsage &AU) const override;
112
113 /// Pass identification, replacement for typeid.
114 static char ID;
115
116private:
117 MachineRegisterInfo *MRI;
118 const TargetInstrInfo *TII;
119 const TargetRegisterInfo *TRI;
120 TargetSchedModel TSchedModel;
121
122 /// List of consecutive CMOV instructions.
123 using CmovGroup = SmallVector<MachineInstr *, 2>;
124 using CmovGroups = SmallVector<CmovGroup, 2>;
125
126 /// Collect all CMOV-group-candidates in \p CurrLoop and update \p
127 /// CmovInstGroups accordingly.
128 ///
129 /// \param Blocks List of blocks to process.
130 /// \param CmovInstGroups List of consecutive CMOV instructions in CurrLoop.
131 /// \returns true iff it found any CMOV-group-candidate.
132 bool collectCmovCandidates(ArrayRef<MachineBasicBlock *> Blocks,
133 CmovGroups &CmovInstGroups,
134 bool IncludeLoads = false);
135
136 /// Check if it is profitable to transform each CMOV-group-candidates into
137 /// branch. Remove all groups that are not profitable from \p CmovInstGroups.
138 ///
139 /// \param Blocks List of blocks to process.
140 /// \param CmovInstGroups List of consecutive CMOV instructions in CurrLoop.
141 /// \returns true iff any CMOV-group-candidate remain.
142 bool checkForProfitableCmovCandidates(ArrayRef<MachineBasicBlock *> Blocks,
143 CmovGroups &CmovInstGroups);
144
145 /// Convert the given list of consecutive CMOV instructions into a branch.
146 ///
147 /// \param Group Consecutive CMOV instructions to be converted into branch.
148 void convertCmovInstsToBranches(SmallVectorImpl<MachineInstr *> &Group) const;
149};
150
151} // end anonymous namespace
152
153char X86CmovConverterPass::ID = 0;
154
155void X86CmovConverterPass::getAnalysisUsage(AnalysisUsage &AU) const {
156 MachineFunctionPass::getAnalysisUsage(AU);
157 AU.addRequired<MachineLoopInfo>();
158}
159
160bool X86CmovConverterPass::runOnMachineFunction(MachineFunction &MF) {
161 if (skipFunction(MF.getFunction()))
1
Assuming the condition is false
2
Taking false branch
162 return false;
163 if (!EnableCmovConverter)
3
Assuming the condition is false
4
Taking false branch
164 return false;
165
166 LLVM_DEBUG(dbgs() << "********** " << getPassName() << " : " << MF.getName()do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("x86-cmov-conversion")) { dbgs() << "********** " <<
getPassName() << " : " << MF.getName() << "**********\n"
; } } while (false)
5
Assuming 'DebugFlag' is 0
6
Loop condition is false. Exiting loop
167 << "**********\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("x86-cmov-conversion")) { dbgs() << "********** " <<
getPassName() << " : " << MF.getName() << "**********\n"
; } } while (false)
;
168
169 bool Changed = false;
170 MachineLoopInfo &MLI = getAnalysis<MachineLoopInfo>();
171 const TargetSubtargetInfo &STI = MF.getSubtarget();
172 MRI = &MF.getRegInfo();
173 TII = STI.getInstrInfo();
174 TRI = STI.getRegisterInfo();
175 TSchedModel.init(&STI);
176
177 // Before we handle the more subtle cases of register-register CMOVs inside
178 // of potentially hot loops, we want to quickly remove all CMOVs with
179 // a memory operand. The CMOV will risk a stall waiting for the load to
180 // complete that speculative execution behind a branch is better suited to
181 // handle on modern x86 chips.
182 if (ForceMemOperand) {
7
Assuming the condition is true
8
Taking true branch
183 CmovGroups AllCmovGroups;
184 SmallVector<MachineBasicBlock *, 4> Blocks;
185 for (auto &MBB : MF)
186 Blocks.push_back(&MBB);
187 if (collectCmovCandidates(Blocks, AllCmovGroups, /*IncludeLoads*/ true)) {
9
Calling 'X86CmovConverterPass::collectCmovCandidates'
188 for (auto &Group : AllCmovGroups) {
189 // Skip any group that doesn't do at least one memory operand cmov.
190 if (!llvm::any_of(Group, [&](MachineInstr *I) { return I->mayLoad(); }))
191 continue;
192
193 // For CMOV groups which we can rewrite and which contain a memory load,
194 // always rewrite them. On x86, a CMOV will dramatically amplify any
195 // memory latency by blocking speculative execution.
196 Changed = true;
197 convertCmovInstsToBranches(Group);
198 }
199 }
200 }
201
202 //===--------------------------------------------------------------------===//
203 // Register-operand Conversion Algorithm
204 // ---------
205 // For each inner most loop
206 // collectCmovCandidates() {
207 // Find all CMOV-group-candidates.
208 // }
209 //
210 // checkForProfitableCmovCandidates() {
211 // * Calculate both loop-depth and optimized-loop-depth.
212 // * Use these depth to check for loop transformation profitability.
213 // * Check for CMOV-group-candidate transformation profitability.
214 // }
215 //
216 // For each profitable CMOV-group-candidate
217 // convertCmovInstsToBranches() {
218 // * Create FalseBB, SinkBB, Conditional branch to SinkBB.
219 // * Replace each CMOV instruction with a PHI instruction in SinkBB.
220 // }
221 //
222 // Note: For more details, see each function description.
223 //===--------------------------------------------------------------------===//
224
225 // Build up the loops in pre-order.
226 SmallVector<MachineLoop *, 4> Loops(MLI.begin(), MLI.end());
227 // Note that we need to check size on each iteration as we accumulate child
228 // loops.
229 for (int i = 0; i < (int)Loops.size(); ++i)
230 for (MachineLoop *Child : Loops[i]->getSubLoops())
231 Loops.push_back(Child);
232
233 for (MachineLoop *CurrLoop : Loops) {
234 // Optimize only inner most loops.
235 if (!CurrLoop->getSubLoops().empty())
236 continue;
237
238 // List of consecutive CMOV instructions to be processed.
239 CmovGroups CmovInstGroups;
240
241 if (!collectCmovCandidates(CurrLoop->getBlocks(), CmovInstGroups))
242 continue;
243
244 if (!checkForProfitableCmovCandidates(CurrLoop->getBlocks(),
245 CmovInstGroups))
246 continue;
247
248 Changed = true;
249 for (auto &Group : CmovInstGroups)
250 convertCmovInstsToBranches(Group);
251 }
252
253 return Changed;
254}
255
256bool X86CmovConverterPass::collectCmovCandidates(
257 ArrayRef<MachineBasicBlock *> Blocks, CmovGroups &CmovInstGroups,
258 bool IncludeLoads) {
259 //===--------------------------------------------------------------------===//
260 // Collect all CMOV-group-candidates and add them into CmovInstGroups.
261 //
262 // CMOV-group:
263 // CMOV instructions, in same MBB, that uses same EFLAGS def instruction.
264 //
265 // CMOV-group-candidate:
266 // CMOV-group where all the CMOV instructions are
267 // 1. consecutive.
268 // 2. have same condition code or opposite one.
269 // 3. have only operand registers (X86::CMOVrr).
270 //===--------------------------------------------------------------------===//
271 // List of possible improvement (TODO's):
272 // --------------------------------------
273 // TODO: Add support for X86::CMOVrm instructions.
274 // TODO: Add support for X86::SETcc instructions.
275 // TODO: Add support for CMOV-groups with non consecutive CMOV instructions.
276 //===--------------------------------------------------------------------===//
277
278 // Current processed CMOV-Group.
279 CmovGroup Group;
280 for (auto *MBB : Blocks) {
10
Assuming '__begin1' is not equal to '__end1'
281 Group.clear();
282 // Condition code of first CMOV instruction current processed range and its
283 // opposite condition code.
284 X86::CondCode FirstCC, FirstOppCC, MemOpCC;
11
'FirstCC' declared without an initial value
285 // Indicator of a non CMOVrr instruction in the current processed range.
286 bool FoundNonCMOVInst = false;
287 // Indicator for current processed CMOV-group if it should be skipped.
288 bool SkipGroup = false;
289
290 for (auto &I : *MBB) {
291 // Skip debug instructions.
292 if (I.isDebugInstr())
12
Taking false branch
293 continue;
294 X86::CondCode CC = X86::getCondFromCMovOpc(I.getOpcode());
295 // Check if we found a X86::CMOVrr instruction.
296 if (CC != X86::COND_INVALID && (IncludeLoads || !I.mayLoad())) {
13
Assuming 'CC' is not equal to COND_INVALID
297 if (Group.empty()) {
14
Taking false branch
298 // We found first CMOV in the range, reset flags.
299 FirstCC = CC;
300 FirstOppCC = X86::GetOppositeBranchCondition(CC);
301 // Clear out the prior group's memory operand CC.
302 MemOpCC = X86::COND_INVALID;
303 FoundNonCMOVInst = false;
304 SkipGroup = false;
305 }
306 Group.push_back(&I);
307 // Check if it is a non-consecutive CMOV instruction or it has different
308 // condition code than FirstCC or FirstOppCC.
309 if (FoundNonCMOVInst || (CC != FirstCC && CC != FirstOppCC))
15
The right operand of '!=' is a garbage value
310 // Mark the SKipGroup indicator to skip current processed CMOV-Group.
311 SkipGroup = true;
312 if (I.mayLoad()) {
313 if (MemOpCC == X86::COND_INVALID)
314 // The first memory operand CMOV.
315 MemOpCC = CC;
316 else if (CC != MemOpCC)
317 // Can't handle mixed conditions with memory operands.
318 SkipGroup = true;
319 }
320 // Check if we were relying on zero-extending behavior of the CMOV.
321 if (!SkipGroup &&
322 llvm::any_of(
323 MRI->use_nodbg_instructions(I.defs().begin()->getReg()),
324 [&](MachineInstr &UseI) {
325 return UseI.getOpcode() == X86::SUBREG_TO_REG;
326 }))
327 // FIXME: We should model the cost of using an explicit MOV to handle
328 // the zero-extension rather than just refusing to handle this.
329 SkipGroup = true;
330 continue;
331 }
332 // If Group is empty, keep looking for first CMOV in the range.
333 if (Group.empty())
334 continue;
335
336 // We found a non X86::CMOVrr instruction.
337 FoundNonCMOVInst = true;
338 // Check if this instruction define EFLAGS, to determine end of processed
339 // range, as there would be no more instructions using current EFLAGS def.
340 if (I.definesRegister(X86::EFLAGS)) {
341 // Check if current processed CMOV-group should not be skipped and add
342 // it as a CMOV-group-candidate.
343 if (!SkipGroup)
344 CmovInstGroups.push_back(Group);
345 else
346 ++NumOfSkippedCmovGroups;
347 Group.clear();
348 }
349 }
350 // End of basic block is considered end of range, check if current processed
351 // CMOV-group should not be skipped and add it as a CMOV-group-candidate.
352 if (Group.empty())
353 continue;
354 if (!SkipGroup)
355 CmovInstGroups.push_back(Group);
356 else
357 ++NumOfSkippedCmovGroups;
358 }
359
360 NumOfCmovGroupCandidate += CmovInstGroups.size();
361 return !CmovInstGroups.empty();
362}
363
364/// \returns Depth of CMOV instruction as if it was converted into branch.
365/// \param TrueOpDepth depth cost of CMOV true value operand.
366/// \param FalseOpDepth depth cost of CMOV false value operand.
367static unsigned getDepthOfOptCmov(unsigned TrueOpDepth, unsigned FalseOpDepth) {
368 //===--------------------------------------------------------------------===//
369 // With no info about branch weight, we assume 50% for each value operand.
370 // Thus, depth of optimized CMOV instruction is the rounded up average of
371 // its True-Operand-Value-Depth and False-Operand-Value-Depth.
372 //===--------------------------------------------------------------------===//
373 return (TrueOpDepth + FalseOpDepth + 1) / 2;
374}
375
376bool X86CmovConverterPass::checkForProfitableCmovCandidates(
377 ArrayRef<MachineBasicBlock *> Blocks, CmovGroups &CmovInstGroups) {
378 struct DepthInfo {
379 /// Depth of original loop.
380 unsigned Depth;
381 /// Depth of optimized loop.
382 unsigned OptDepth;
383 };
384 /// Number of loop iterations to calculate depth for ?!
385 static const unsigned LoopIterations = 2;
386 DenseMap<MachineInstr *, DepthInfo> DepthMap;
387 DepthInfo LoopDepth[LoopIterations] = {{0, 0}, {0, 0}};
388 enum { PhyRegType = 0, VirRegType = 1, RegTypeNum = 2 };
389 /// For each register type maps the register to its last def instruction.
390 DenseMap<unsigned, MachineInstr *> RegDefMaps[RegTypeNum];
391 /// Maps register operand to its def instruction, which can be nullptr if it
392 /// is unknown (e.g., operand is defined outside the loop).
393 DenseMap<MachineOperand *, MachineInstr *> OperandToDefMap;
394
395 // Set depth of unknown instruction (i.e., nullptr) to zero.
396 DepthMap[nullptr] = {0, 0};
397
398 SmallPtrSet<MachineInstr *, 4> CmovInstructions;
399 for (auto &Group : CmovInstGroups)
400 CmovInstructions.insert(Group.begin(), Group.end());
401
402 //===--------------------------------------------------------------------===//
403 // Step 1: Calculate instruction depth and loop depth.
404 // Optimized-Loop:
405 // loop with CMOV-group-candidates converted into branches.
406 //
407 // Instruction-Depth:
408 // instruction latency + max operand depth.
409 // * For CMOV instruction in optimized loop the depth is calculated as:
410 // CMOV latency + getDepthOfOptCmov(True-Op-Depth, False-Op-depth)
411 // TODO: Find a better way to estimate the latency of the branch instruction
412 // rather than using the CMOV latency.
413 //
414 // Loop-Depth:
415 // max instruction depth of all instructions in the loop.
416 // Note: instruction with max depth represents the critical-path in the loop.
417 //
418 // Loop-Depth[i]:
419 // Loop-Depth calculated for first `i` iterations.
420 // Note: it is enough to calculate depth for up to two iterations.
421 //
422 // Depth-Diff[i]:
423 // Number of cycles saved in first 'i` iterations by optimizing the loop.
424 //===--------------------------------------------------------------------===//
425 for (unsigned I = 0; I < LoopIterations; ++I) {
426 DepthInfo &MaxDepth = LoopDepth[I];
427 for (auto *MBB : Blocks) {
428 // Clear physical registers Def map.
429 RegDefMaps[PhyRegType].clear();
430 for (MachineInstr &MI : *MBB) {
431 // Skip debug instructions.
432 if (MI.isDebugInstr())
433 continue;
434 unsigned MIDepth = 0;
435 unsigned MIDepthOpt = 0;
436 bool IsCMOV = CmovInstructions.count(&MI);
437 for (auto &MO : MI.uses()) {
438 // Checks for "isUse()" as "uses()" returns also implicit definitions.
439 if (!MO.isReg() || !MO.isUse())
440 continue;
441 unsigned Reg = MO.getReg();
442 auto &RDM = RegDefMaps[TargetRegisterInfo::isVirtualRegister(Reg)];
443 if (MachineInstr *DefMI = RDM.lookup(Reg)) {
444 OperandToDefMap[&MO] = DefMI;
445 DepthInfo Info = DepthMap.lookup(DefMI);
446 MIDepth = std::max(MIDepth, Info.Depth);
447 if (!IsCMOV)
448 MIDepthOpt = std::max(MIDepthOpt, Info.OptDepth);
449 }
450 }
451
452 if (IsCMOV)
453 MIDepthOpt = getDepthOfOptCmov(
454 DepthMap[OperandToDefMap.lookup(&MI.getOperand(1))].OptDepth,
455 DepthMap[OperandToDefMap.lookup(&MI.getOperand(2))].OptDepth);
456
457 // Iterates over all operands to handle implicit definitions as well.
458 for (auto &MO : MI.operands()) {
459 if (!MO.isReg() || !MO.isDef())
460 continue;
461 unsigned Reg = MO.getReg();
462 RegDefMaps[TargetRegisterInfo::isVirtualRegister(Reg)][Reg] = &MI;
463 }
464
465 unsigned Latency = TSchedModel.computeInstrLatency(&MI);
466 DepthMap[&MI] = {MIDepth += Latency, MIDepthOpt += Latency};
467 MaxDepth.Depth = std::max(MaxDepth.Depth, MIDepth);
468 MaxDepth.OptDepth = std::max(MaxDepth.OptDepth, MIDepthOpt);
469 }
470 }
471 }
472
473 unsigned Diff[LoopIterations] = {LoopDepth[0].Depth - LoopDepth[0].OptDepth,
474 LoopDepth[1].Depth - LoopDepth[1].OptDepth};
475
476 //===--------------------------------------------------------------------===//
477 // Step 2: Check if Loop worth to be optimized.
478 // Worth-Optimize-Loop:
479 // case 1: Diff[1] == Diff[0]
480 // Critical-path is iteration independent - there is no dependency
481 // of critical-path instructions on critical-path instructions of
482 // previous iteration.
483 // Thus, it is enough to check gain percent of 1st iteration -
484 // To be conservative, the optimized loop need to have a depth of
485 // 12.5% cycles less than original loop, per iteration.
486 //
487 // case 2: Diff[1] > Diff[0]
488 // Critical-path is iteration dependent - there is dependency of
489 // critical-path instructions on critical-path instructions of
490 // previous iteration.
491 // Thus, check the gain percent of the 2nd iteration (similar to the
492 // previous case), but it is also required to check the gradient of
493 // the gain - the change in Depth-Diff compared to the change in
494 // Loop-Depth between 1st and 2nd iterations.
495 // To be conservative, the gradient need to be at least 50%.
496 //
497 // In addition, In order not to optimize loops with very small gain, the
498 // gain (in cycles) after 2nd iteration should not be less than a given
499 // threshold. Thus, the check (Diff[1] >= GainCycleThreshold) must apply.
500 //
501 // If loop is not worth optimizing, remove all CMOV-group-candidates.
502 //===--------------------------------------------------------------------===//
503 if (Diff[1] < GainCycleThreshold)
504 return false;
505
506 bool WorthOptLoop = false;
507 if (Diff[1] == Diff[0])
508 WorthOptLoop = Diff[0] * 8 >= LoopDepth[0].Depth;
509 else if (Diff[1] > Diff[0])
510 WorthOptLoop =
511 (Diff[1] - Diff[0]) * 2 >= (LoopDepth[1].Depth - LoopDepth[0].Depth) &&
512 (Diff[1] * 8 >= LoopDepth[1].Depth);
513
514 if (!WorthOptLoop)
515 return false;
516
517 ++NumOfLoopCandidate;
518
519 //===--------------------------------------------------------------------===//
520 // Step 3: Check for each CMOV-group-candidate if it worth to be optimized.
521 // Worth-Optimize-Group:
522 // Iff it worths to optimize all CMOV instructions in the group.
523 //
524 // Worth-Optimize-CMOV:
525 // Predicted branch is faster than CMOV by the difference between depth of
526 // condition operand and depth of taken (predicted) value operand.
527 // To be conservative, the gain of such CMOV transformation should cover at
528 // at least 25% of branch-misprediction-penalty.
529 //===--------------------------------------------------------------------===//
530 unsigned MispredictPenalty = TSchedModel.getMCSchedModel()->MispredictPenalty;
531 CmovGroups TempGroups;
532 std::swap(TempGroups, CmovInstGroups);
533 for (auto &Group : TempGroups) {
534 bool WorthOpGroup = true;
535 for (auto *MI : Group) {
536 // Avoid CMOV instruction which value is used as a pointer to load from.
537 // This is another conservative check to avoid converting CMOV instruction
538 // used with tree-search like algorithm, where the branch is unpredicted.
539 auto UIs = MRI->use_instructions(MI->defs().begin()->getReg());
540 if (UIs.begin() != UIs.end() && ++UIs.begin() == UIs.end()) {
541 unsigned Op = UIs.begin()->getOpcode();
542 if (Op == X86::MOV64rm || Op == X86::MOV32rm) {
543 WorthOpGroup = false;
544 break;
545 }
546 }
547
548 unsigned CondCost =
549 DepthMap[OperandToDefMap.lookup(&MI->getOperand(3))].Depth;
550 unsigned ValCost = getDepthOfOptCmov(
551 DepthMap[OperandToDefMap.lookup(&MI->getOperand(1))].Depth,
552 DepthMap[OperandToDefMap.lookup(&MI->getOperand(2))].Depth);
553 if (ValCost > CondCost || (CondCost - ValCost) * 4 < MispredictPenalty) {
554 WorthOpGroup = false;
555 break;
556 }
557 }
558
559 if (WorthOpGroup)
560 CmovInstGroups.push_back(Group);
561 }
562
563 return !CmovInstGroups.empty();
564}
565
566static bool checkEFLAGSLive(MachineInstr *MI) {
567 if (MI->killsRegister(X86::EFLAGS))
568 return false;
569
570 // The EFLAGS operand of MI might be missing a kill marker.
571 // Figure out whether EFLAGS operand should LIVE after MI instruction.
572 MachineBasicBlock *BB = MI->getParent();
573 MachineBasicBlock::iterator ItrMI = MI;
574
575 // Scan forward through BB for a use/def of EFLAGS.
576 for (auto I = std::next(ItrMI), E = BB->end(); I != E; ++I) {
577 if (I->readsRegister(X86::EFLAGS))
578 return true;
579 if (I->definesRegister(X86::EFLAGS))
580 return false;
581 }
582
583 // We hit the end of the block, check whether EFLAGS is live into a successor.
584 for (auto I = BB->succ_begin(), E = BB->succ_end(); I != E; ++I) {
585 if ((*I)->isLiveIn(X86::EFLAGS))
586 return true;
587 }
588
589 return false;
590}
591
592/// Given /p First CMOV instruction and /p Last CMOV instruction representing a
593/// group of CMOV instructions, which may contain debug instructions in between,
594/// move all debug instructions to after the last CMOV instruction, making the
595/// CMOV group consecutive.
596static void packCmovGroup(MachineInstr *First, MachineInstr *Last) {
597 assert(X86::getCondFromCMovOpc(Last->getOpcode()) != X86::COND_INVALID &&((X86::getCondFromCMovOpc(Last->getOpcode()) != X86::COND_INVALID
&& "Last instruction in a CMOV group must be a CMOV instruction"
) ? static_cast<void> (0) : __assert_fail ("X86::getCondFromCMovOpc(Last->getOpcode()) != X86::COND_INVALID && \"Last instruction in a CMOV group must be a CMOV instruction\""
, "/build/llvm-toolchain-snapshot-8~svn348900/lib/Target/X86/X86CmovConversion.cpp"
, 598, __PRETTY_FUNCTION__))
598 "Last instruction in a CMOV group must be a CMOV instruction")((X86::getCondFromCMovOpc(Last->getOpcode()) != X86::COND_INVALID
&& "Last instruction in a CMOV group must be a CMOV instruction"
) ? static_cast<void> (0) : __assert_fail ("X86::getCondFromCMovOpc(Last->getOpcode()) != X86::COND_INVALID && \"Last instruction in a CMOV group must be a CMOV instruction\""
, "/build/llvm-toolchain-snapshot-8~svn348900/lib/Target/X86/X86CmovConversion.cpp"
, 598, __PRETTY_FUNCTION__))
;
599
600 SmallVector<MachineInstr *, 2> DBGInstructions;
601 for (auto I = First->getIterator(), E = Last->getIterator(); I != E; I++) {
602 if (I->isDebugInstr())
603 DBGInstructions.push_back(&*I);
604 }
605
606 // Splice the debug instruction after the cmov group.
607 MachineBasicBlock *MBB = First->getParent();
608 for (auto *MI : DBGInstructions)
609 MBB->insertAfter(Last, MI->removeFromParent());
610}
611
612void X86CmovConverterPass::convertCmovInstsToBranches(
613 SmallVectorImpl<MachineInstr *> &Group) const {
614 assert(!Group.empty() && "No CMOV instructions to convert")((!Group.empty() && "No CMOV instructions to convert"
) ? static_cast<void> (0) : __assert_fail ("!Group.empty() && \"No CMOV instructions to convert\""
, "/build/llvm-toolchain-snapshot-8~svn348900/lib/Target/X86/X86CmovConversion.cpp"
, 614, __PRETTY_FUNCTION__))
;
615 ++NumOfOptimizedCmovGroups;
616
617 // If the CMOV group is not packed, e.g., there are debug instructions between
618 // first CMOV and last CMOV, then pack the group and make the CMOV instruction
619 // consecutive by moving the debug instructions to after the last CMOV.
620 packCmovGroup(Group.front(), Group.back());
621
622 // To convert a CMOVcc instruction, we actually have to insert the diamond
623 // control-flow pattern. The incoming instruction knows the destination vreg
624 // to set, the condition code register to branch on, the true/false values to
625 // select between, and a branch opcode to use.
626
627 // Before
628 // -----
629 // MBB:
630 // cond = cmp ...
631 // v1 = CMOVge t1, f1, cond
632 // v2 = CMOVlt t2, f2, cond
633 // v3 = CMOVge v1, f3, cond
634 //
635 // After
636 // -----
637 // MBB:
638 // cond = cmp ...
639 // jge %SinkMBB
640 //
641 // FalseMBB:
642 // jmp %SinkMBB
643 //
644 // SinkMBB:
645 // %v1 = phi[%f1, %FalseMBB], [%t1, %MBB]
646 // %v2 = phi[%t2, %FalseMBB], [%f2, %MBB] ; For CMOV with OppCC switch
647 // ; true-value with false-value
648 // %v3 = phi[%f3, %FalseMBB], [%t1, %MBB] ; Phi instruction cannot use
649 // ; previous Phi instruction result
650
651 MachineInstr &MI = *Group.front();
652 MachineInstr *LastCMOV = Group.back();
653 DebugLoc DL = MI.getDebugLoc();
654
655 X86::CondCode CC = X86::CondCode(X86::getCondFromCMovOpc(MI.getOpcode()));
656 X86::CondCode OppCC = X86::GetOppositeBranchCondition(CC);
657 // Potentially swap the condition codes so that any memory operand to a CMOV
658 // is in the *false* position instead of the *true* position. We can invert
659 // any non-memory operand CMOV instructions to cope with this and we ensure
660 // memory operand CMOVs are only included with a single condition code.
661 if (llvm::any_of(Group, [&](MachineInstr *I) {
662 return I->mayLoad() && X86::getCondFromCMovOpc(I->getOpcode()) == CC;
663 }))
664 std::swap(CC, OppCC);
665
666 MachineBasicBlock *MBB = MI.getParent();
667 MachineFunction::iterator It = ++MBB->getIterator();
668 MachineFunction *F = MBB->getParent();
669 const BasicBlock *BB = MBB->getBasicBlock();
670
671 MachineBasicBlock *FalseMBB = F->CreateMachineBasicBlock(BB);
672 MachineBasicBlock *SinkMBB = F->CreateMachineBasicBlock(BB);
673 F->insert(It, FalseMBB);
674 F->insert(It, SinkMBB);
675
676 // If the EFLAGS register isn't dead in the terminator, then claim that it's
677 // live into the sink and copy blocks.
678 if (checkEFLAGSLive(LastCMOV)) {
679 FalseMBB->addLiveIn(X86::EFLAGS);
680 SinkMBB->addLiveIn(X86::EFLAGS);
681 }
682
683 // Transfer the remainder of BB and its successor edges to SinkMBB.
684 SinkMBB->splice(SinkMBB->begin(), MBB,
685 std::next(MachineBasicBlock::iterator(LastCMOV)), MBB->end());
686 SinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
687
688 // Add the false and sink blocks as its successors.
689 MBB->addSuccessor(FalseMBB);
690 MBB->addSuccessor(SinkMBB);
691
692 // Create the conditional branch instruction.
693 BuildMI(MBB, DL, TII->get(X86::GetCondBranchFromCond(CC))).addMBB(SinkMBB);
694
695 // Add the sink block to the false block successors.
696 FalseMBB->addSuccessor(SinkMBB);
697
698 MachineInstrBuilder MIB;
699 MachineBasicBlock::iterator MIItBegin = MachineBasicBlock::iterator(MI);
700 MachineBasicBlock::iterator MIItEnd =
701 std::next(MachineBasicBlock::iterator(LastCMOV));
702 MachineBasicBlock::iterator FalseInsertionPoint = FalseMBB->begin();
703 MachineBasicBlock::iterator SinkInsertionPoint = SinkMBB->begin();
704
705 // First we need to insert an explicit load on the false path for any memory
706 // operand. We also need to potentially do register rewriting here, but it is
707 // simpler as the memory operands are always on the false path so we can
708 // simply take that input, whatever it is.
709 DenseMap<unsigned, unsigned> FalseBBRegRewriteTable;
710 for (MachineBasicBlock::iterator MIIt = MIItBegin; MIIt != MIItEnd;) {
711 auto &MI = *MIIt++;
712 // Skip any CMOVs in this group which don't load from memory.
713 if (!MI.mayLoad()) {
714 // Remember the false-side register input.
715 unsigned FalseReg =
716 MI.getOperand(X86::getCondFromCMovOpc(MI.getOpcode()) == CC ? 1 : 2)
717 .getReg();
718 // Walk back through any intermediate cmovs referenced.
719 while (true) {
720 auto FRIt = FalseBBRegRewriteTable.find(FalseReg);
721 if (FRIt == FalseBBRegRewriteTable.end())
722 break;
723 FalseReg = FRIt->second;
724 }
725 FalseBBRegRewriteTable[MI.getOperand(0).getReg()] = FalseReg;
726 continue;
727 }
728
729 // The condition must be the *opposite* of the one we've decided to branch
730 // on as the branch will go *around* the load and the load should happen
731 // when the CMOV condition is false.
732 assert(X86::getCondFromCMovOpc(MI.getOpcode()) == OppCC &&((X86::getCondFromCMovOpc(MI.getOpcode()) == OppCC &&
"Can only handle memory-operand cmov instructions with a condition "
"opposite to the selected branch direction.") ? static_cast<
void> (0) : __assert_fail ("X86::getCondFromCMovOpc(MI.getOpcode()) == OppCC && \"Can only handle memory-operand cmov instructions with a condition \" \"opposite to the selected branch direction.\""
, "/build/llvm-toolchain-snapshot-8~svn348900/lib/Target/X86/X86CmovConversion.cpp"
, 734, __PRETTY_FUNCTION__))
733 "Can only handle memory-operand cmov instructions with a condition "((X86::getCondFromCMovOpc(MI.getOpcode()) == OppCC &&
"Can only handle memory-operand cmov instructions with a condition "
"opposite to the selected branch direction.") ? static_cast<
void> (0) : __assert_fail ("X86::getCondFromCMovOpc(MI.getOpcode()) == OppCC && \"Can only handle memory-operand cmov instructions with a condition \" \"opposite to the selected branch direction.\""
, "/build/llvm-toolchain-snapshot-8~svn348900/lib/Target/X86/X86CmovConversion.cpp"
, 734, __PRETTY_FUNCTION__))
734 "opposite to the selected branch direction.")((X86::getCondFromCMovOpc(MI.getOpcode()) == OppCC &&
"Can only handle memory-operand cmov instructions with a condition "
"opposite to the selected branch direction.") ? static_cast<
void> (0) : __assert_fail ("X86::getCondFromCMovOpc(MI.getOpcode()) == OppCC && \"Can only handle memory-operand cmov instructions with a condition \" \"opposite to the selected branch direction.\""
, "/build/llvm-toolchain-snapshot-8~svn348900/lib/Target/X86/X86CmovConversion.cpp"
, 734, __PRETTY_FUNCTION__))
;
735
736 // The goal is to rewrite the cmov from:
737 //
738 // MBB:
739 // %A = CMOVcc %B (tied), (mem)
740 //
741 // to
742 //
743 // MBB:
744 // %A = CMOVcc %B (tied), %C
745 // FalseMBB:
746 // %C = MOV (mem)
747 //
748 // Which will allow the next loop to rewrite the CMOV in terms of a PHI:
749 //
750 // MBB:
751 // JMP!cc SinkMBB
752 // FalseMBB:
753 // %C = MOV (mem)
754 // SinkMBB:
755 // %A = PHI [ %C, FalseMBB ], [ %B, MBB]
756
757 // Get a fresh register to use as the destination of the MOV.
758 const TargetRegisterClass *RC = MRI->getRegClass(MI.getOperand(0).getReg());
759 unsigned TmpReg = MRI->createVirtualRegister(RC);
760
761 SmallVector<MachineInstr *, 4> NewMIs;
762 bool Unfolded = TII->unfoldMemoryOperand(*MBB->getParent(), MI, TmpReg,
763 /*UnfoldLoad*/ true,
764 /*UnfoldStore*/ false, NewMIs);
765 (void)Unfolded;
766 assert(Unfolded && "Should never fail to unfold a loading cmov!")((Unfolded && "Should never fail to unfold a loading cmov!"
) ? static_cast<void> (0) : __assert_fail ("Unfolded && \"Should never fail to unfold a loading cmov!\""
, "/build/llvm-toolchain-snapshot-8~svn348900/lib/Target/X86/X86CmovConversion.cpp"
, 766, __PRETTY_FUNCTION__))
;
767
768 // Move the new CMOV to just before the old one and reset any impacted
769 // iterator.
770 auto *NewCMOV = NewMIs.pop_back_val();
771 assert(X86::getCondFromCMovOpc(NewCMOV->getOpcode()) == OppCC &&((X86::getCondFromCMovOpc(NewCMOV->getOpcode()) == OppCC &&
"Last new instruction isn't the expected CMOV!") ? static_cast
<void> (0) : __assert_fail ("X86::getCondFromCMovOpc(NewCMOV->getOpcode()) == OppCC && \"Last new instruction isn't the expected CMOV!\""
, "/build/llvm-toolchain-snapshot-8~svn348900/lib/Target/X86/X86CmovConversion.cpp"
, 772, __PRETTY_FUNCTION__))
772 "Last new instruction isn't the expected CMOV!")((X86::getCondFromCMovOpc(NewCMOV->getOpcode()) == OppCC &&
"Last new instruction isn't the expected CMOV!") ? static_cast
<void> (0) : __assert_fail ("X86::getCondFromCMovOpc(NewCMOV->getOpcode()) == OppCC && \"Last new instruction isn't the expected CMOV!\""
, "/build/llvm-toolchain-snapshot-8~svn348900/lib/Target/X86/X86CmovConversion.cpp"
, 772, __PRETTY_FUNCTION__))
;
773 LLVM_DEBUG(dbgs() << "\tRewritten cmov: "; NewCMOV->dump())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("x86-cmov-conversion")) { dbgs() << "\tRewritten cmov: "
; NewCMOV->dump(); } } while (false)
;
774 MBB->insert(MachineBasicBlock::iterator(MI), NewCMOV);
775 if (&*MIItBegin == &MI)
776 MIItBegin = MachineBasicBlock::iterator(NewCMOV);
777
778 // Sink whatever instructions were needed to produce the unfolded operand
779 // into the false block.
780 for (auto *NewMI : NewMIs) {
781 LLVM_DEBUG(dbgs() << "\tRewritten load instr: "; NewMI->dump())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("x86-cmov-conversion")) { dbgs() << "\tRewritten load instr: "
; NewMI->dump(); } } while (false)
;
782 FalseMBB->insert(FalseInsertionPoint, NewMI);
783 // Re-map any operands that are from other cmovs to the inputs for this block.
784 for (auto &MOp : NewMI->uses()) {
785 if (!MOp.isReg())
786 continue;
787 auto It = FalseBBRegRewriteTable.find(MOp.getReg());
788 if (It == FalseBBRegRewriteTable.end())
789 continue;
790
791 MOp.setReg(It->second);
792 // This might have been a kill when it referenced the cmov result, but
793 // it won't necessarily be once rewritten.
794 // FIXME: We could potentially improve this by tracking whether the
795 // operand to the cmov was also a kill, and then skipping the PHI node
796 // construction below.
797 MOp.setIsKill(false);
798 }
799 }
800 MBB->erase(MachineBasicBlock::iterator(MI),
801 std::next(MachineBasicBlock::iterator(MI)));
802
803 // Add this PHI to the rewrite table.
804 FalseBBRegRewriteTable[NewCMOV->getOperand(0).getReg()] = TmpReg;
805 }
806
807 // As we are creating the PHIs, we have to be careful if there is more than
808 // one. Later CMOVs may reference the results of earlier CMOVs, but later
809 // PHIs have to reference the individual true/false inputs from earlier PHIs.
810 // That also means that PHI construction must work forward from earlier to
811 // later, and that the code must maintain a mapping from earlier PHI's
812 // destination registers, and the registers that went into the PHI.
813 DenseMap<unsigned, std::pair<unsigned, unsigned>> RegRewriteTable;
814
815 for (MachineBasicBlock::iterator MIIt = MIItBegin; MIIt != MIItEnd; ++MIIt) {
816 unsigned DestReg = MIIt->getOperand(0).getReg();
817 unsigned Op1Reg = MIIt->getOperand(1).getReg();
818 unsigned Op2Reg = MIIt->getOperand(2).getReg();
819
820 // If this CMOV we are processing is the opposite condition from the jump we
821 // generated, then we have to swap the operands for the PHI that is going to
822 // be generated.
823 if (X86::getCondFromCMovOpc(MIIt->getOpcode()) == OppCC)
824 std::swap(Op1Reg, Op2Reg);
825
826 auto Op1Itr = RegRewriteTable.find(Op1Reg);
827 if (Op1Itr != RegRewriteTable.end())
828 Op1Reg = Op1Itr->second.first;
829
830 auto Op2Itr = RegRewriteTable.find(Op2Reg);
831 if (Op2Itr != RegRewriteTable.end())
832 Op2Reg = Op2Itr->second.second;
833
834 // SinkMBB:
835 // %Result = phi [ %FalseValue, FalseMBB ], [ %TrueValue, MBB ]
836 // ...
837 MIB = BuildMI(*SinkMBB, SinkInsertionPoint, DL, TII->get(X86::PHI), DestReg)
838 .addReg(Op1Reg)
839 .addMBB(FalseMBB)
840 .addReg(Op2Reg)
841 .addMBB(MBB);
842 (void)MIB;
843 LLVM_DEBUG(dbgs() << "\tFrom: "; MIIt->dump())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("x86-cmov-conversion")) { dbgs() << "\tFrom: "; MIIt->
dump(); } } while (false)
;
844 LLVM_DEBUG(dbgs() << "\tTo: "; MIB->dump())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("x86-cmov-conversion")) { dbgs() << "\tTo: "; MIB->
dump(); } } while (false)
;
845
846 // Add this PHI to the rewrite table.
847 RegRewriteTable[DestReg] = std::make_pair(Op1Reg, Op2Reg);
848 }
849
850 // Now remove the CMOV(s).
851 MBB->erase(MIItBegin, MIItEnd);
852}
853
854INITIALIZE_PASS_BEGIN(X86CmovConverterPass, DEBUG_TYPE, "X86 cmov Conversion",static void *initializeX86CmovConverterPassPassOnce(PassRegistry
&Registry) {
855 false, false)static void *initializeX86CmovConverterPassPassOnce(PassRegistry
&Registry) {
856INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo)initializeMachineLoopInfoPass(Registry);
857INITIALIZE_PASS_END(X86CmovConverterPass, DEBUG_TYPE, "X86 cmov Conversion",PassInfo *PI = new PassInfo( "X86 cmov Conversion", "x86-cmov-conversion"
, &X86CmovConverterPass::ID, PassInfo::NormalCtor_t(callDefaultCtor
<X86CmovConverterPass>), false, false); Registry.registerPass
(*PI, true); return PI; } static llvm::once_flag InitializeX86CmovConverterPassPassFlag
; void llvm::initializeX86CmovConverterPassPass(PassRegistry &
Registry) { llvm::call_once(InitializeX86CmovConverterPassPassFlag
, initializeX86CmovConverterPassPassOnce, std::ref(Registry))
; }
858 false, false)PassInfo *PI = new PassInfo( "X86 cmov Conversion", "x86-cmov-conversion"
, &X86CmovConverterPass::ID, PassInfo::NormalCtor_t(callDefaultCtor
<X86CmovConverterPass>), false, false); Registry.registerPass
(*PI, true); return PI; } static llvm::once_flag InitializeX86CmovConverterPassPassFlag
; void llvm::initializeX86CmovConverterPassPass(PassRegistry &
Registry) { llvm::call_once(InitializeX86CmovConverterPassPassFlag
, initializeX86CmovConverterPassPassOnce, std::ref(Registry))
; }
859
860FunctionPass *llvm::createX86CmovConverterPass() {
861 return new X86CmovConverterPass();
862}