Bug Summary

File:build-llvm/lib/Target/X86/X86GenAsmMatcher.inc
Warning:line 6911, column 10
Excessive padding in 'struct (anonymous namespace)::MatchEntry' (5 padding bytes, where 1 is optimal). Optimal fields order: RequiredFeatures, Mnemonic, Opcode, ConvertFn, Classes, consider reordering the fields or adding explicit padding members

Annotated Source Code

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1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Assembly Matcher Source Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9
10#ifdef GET_ASSEMBLER_HEADER
11#undef GET_ASSEMBLER_HEADER
12 // This should be included into the middle of the declaration of
13 // your subclasses implementation of MCTargetAsmParser.
14 uint64_t ComputeAvailableFeatures(const FeatureBitset& FB) const;
15 void convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
16 const OperandVector &Operands);
17 void convertToMapAndConstraints(unsigned Kind,
18 const OperandVector &Operands) override;
19 unsigned MatchInstructionImpl(const OperandVector &Operands,
20 MCInst &Inst,
21 uint64_t &ErrorInfo,
22 bool matchingInlineAsm,
23 unsigned VariantID = 0);
24#endif // GET_ASSEMBLER_HEADER_INFO
25
26
27#ifdef GET_OPERAND_DIAGNOSTIC_TYPES
28#undef GET_OPERAND_DIAGNOSTIC_TYPES
29
30#endif // GET_OPERAND_DIAGNOSTIC_TYPES
31
32
33#ifdef GET_REGISTER_MATCHER
34#undef GET_REGISTER_MATCHER
35
36// Flags for subtarget features that participate in instruction matching.
37enum SubtargetFeatureFlag : uint32_t {
38 Feature_HasAVX512 = (1ULL << 0),
39 Feature_HasCDI = (1ULL << 3),
40 Feature_HasVPOPCNTDQ = (1ULL << 12),
41 Feature_HasPFI = (1ULL << 7),
42 Feature_HasERI = (1ULL << 5),
43 Feature_HasDQI = (1ULL << 4),
44 Feature_HasBWI = (1ULL << 2),
45 Feature_HasVLX = (1ULL << 10),
46 Feature_HasVNNI = (1ULL << 11),
47 Feature_HasBITALG = (1ULL << 1),
48 Feature_HasVBMI = (1ULL << 8),
49 Feature_HasVBMI2 = (1ULL << 9),
50 Feature_HasIFMA = (1ULL << 6),
51 Feature_Not64BitMode = (1ULL << 17),
52 Feature_In64BitMode = (1ULL << 15),
53 Feature_In16BitMode = (1ULL << 13),
54 Feature_Not16BitMode = (1ULL << 16),
55 Feature_In32BitMode = (1ULL << 14),
56 Feature_None = 0
57};
58
59static unsigned MatchRegisterName(StringRef Name) {
60 switch (Name.size()) {
61 default: break;
62 case 2: // 33 strings to match.
63 switch (Name[0]) {
64 default: break;
65 case 'a': // 3 strings to match.
66 switch (Name[1]) {
67 default: break;
68 case 'h': // 1 string to match.
69 return 1; // "ah"
70 case 'l': // 1 string to match.
71 return 2; // "al"
72 case 'x': // 1 string to match.
73 return 3; // "ax"
74 }
75 break;
76 case 'b': // 4 strings to match.
77 switch (Name[1]) {
78 default: break;
79 case 'h': // 1 string to match.
80 return 4; // "bh"
81 case 'l': // 1 string to match.
82 return 5; // "bl"
83 case 'p': // 1 string to match.
84 return 6; // "bp"
85 case 'x': // 1 string to match.
86 return 8; // "bx"
87 }
88 break;
89 case 'c': // 4 strings to match.
90 switch (Name[1]) {
91 default: break;
92 case 'h': // 1 string to match.
93 return 9; // "ch"
94 case 'l': // 1 string to match.
95 return 10; // "cl"
96 case 's': // 1 string to match.
97 return 11; // "cs"
98 case 'x': // 1 string to match.
99 return 12; // "cx"
100 }
101 break;
102 case 'd': // 5 strings to match.
103 switch (Name[1]) {
104 default: break;
105 case 'h': // 1 string to match.
106 return 13; // "dh"
107 case 'i': // 1 string to match.
108 return 14; // "di"
109 case 'l': // 1 string to match.
110 return 16; // "dl"
111 case 's': // 1 string to match.
112 return 17; // "ds"
113 case 'x': // 1 string to match.
114 return 18; // "dx"
115 }
116 break;
117 case 'e': // 1 string to match.
118 if (Name[1] != 's')
119 break;
120 return 28; // "es"
121 case 'f': // 1 string to match.
122 if (Name[1] != 's')
123 break;
124 return 32; // "fs"
125 case 'g': // 1 string to match.
126 if (Name[1] != 's')
127 break;
128 return 33; // "gs"
129 case 'i': // 1 string to match.
130 if (Name[1] != 'p')
131 break;
132 return 34; // "ip"
133 case 'k': // 8 strings to match.
134 switch (Name[1]) {
135 default: break;
136 case '0': // 1 string to match.
137 return 95; // "k0"
138 case '1': // 1 string to match.
139 return 96; // "k1"
140 case '2': // 1 string to match.
141 return 97; // "k2"
142 case '3': // 1 string to match.
143 return 98; // "k3"
144 case '4': // 1 string to match.
145 return 99; // "k4"
146 case '5': // 1 string to match.
147 return 100; // "k5"
148 case '6': // 1 string to match.
149 return 101; // "k6"
150 case '7': // 1 string to match.
151 return 102; // "k7"
152 }
153 break;
154 case 'r': // 2 strings to match.
155 switch (Name[1]) {
156 default: break;
157 case '8': // 1 string to match.
158 return 111; // "r8"
159 case '9': // 1 string to match.
160 return 112; // "r9"
161 }
162 break;
163 case 's': // 3 strings to match.
164 switch (Name[1]) {
165 default: break;
166 case 'i': // 1 string to match.
167 return 45; // "si"
168 case 'p': // 1 string to match.
169 return 47; // "sp"
170 case 's': // 1 string to match.
171 return 49; // "ss"
172 }
173 break;
174 }
175 break;
176 case 3: // 73 strings to match.
177 switch (Name[0]) {
178 default: break;
179 case 'b': // 1 string to match.
180 if (memcmp(Name.data()+1, "pl", 2) != 0)
181 break;
182 return 7; // "bpl"
183 case 'c': // 10 strings to match.
184 if (Name[1] != 'r')
185 break;
186 switch (Name[2]) {
187 default: break;
188 case '0': // 1 string to match.
189 return 55; // "cr0"
190 case '1': // 1 string to match.
191 return 56; // "cr1"
192 case '2': // 1 string to match.
193 return 57; // "cr2"
194 case '3': // 1 string to match.
195 return 58; // "cr3"
196 case '4': // 1 string to match.
197 return 59; // "cr4"
198 case '5': // 1 string to match.
199 return 60; // "cr5"
200 case '6': // 1 string to match.
201 return 61; // "cr6"
202 case '7': // 1 string to match.
203 return 62; // "cr7"
204 case '8': // 1 string to match.
205 return 63; // "cr8"
206 case '9': // 1 string to match.
207 return 64; // "cr9"
208 }
209 break;
210 case 'd': // 11 strings to match.
211 switch (Name[1]) {
212 default: break;
213 case 'i': // 1 string to match.
214 if (Name[2] != 'l')
215 break;
216 return 15; // "dil"
217 case 'r': // 10 strings to match.
218 switch (Name[2]) {
219 default: break;
220 case '0': // 1 string to match.
221 return 71; // "dr0"
222 case '1': // 1 string to match.
223 return 72; // "dr1"
224 case '2': // 1 string to match.
225 return 73; // "dr2"
226 case '3': // 1 string to match.
227 return 74; // "dr3"
228 case '4': // 1 string to match.
229 return 75; // "dr4"
230 case '5': // 1 string to match.
231 return 76; // "dr5"
232 case '6': // 1 string to match.
233 return 77; // "dr6"
234 case '7': // 1 string to match.
235 return 78; // "dr7"
236 case '8': // 1 string to match.
237 return 79; // "dr8"
238 case '9': // 1 string to match.
239 return 80; // "dr9"
240 }
241 break;
242 }
243 break;
244 case 'e': // 10 strings to match.
245 switch (Name[1]) {
246 default: break;
247 case 'a': // 1 string to match.
248 if (Name[2] != 'x')
249 break;
250 return 19; // "eax"
251 case 'b': // 2 strings to match.
252 switch (Name[2]) {
253 default: break;
254 case 'p': // 1 string to match.
255 return 20; // "ebp"
256 case 'x': // 1 string to match.
257 return 21; // "ebx"
258 }
259 break;
260 case 'c': // 1 string to match.
261 if (Name[2] != 'x')
262 break;
263 return 22; // "ecx"
264 case 'd': // 2 strings to match.
265 switch (Name[2]) {
266 default: break;
267 case 'i': // 1 string to match.
268 return 23; // "edi"
269 case 'x': // 1 string to match.
270 return 24; // "edx"
271 }
272 break;
273 case 'i': // 2 strings to match.
274 switch (Name[2]) {
275 default: break;
276 case 'p': // 1 string to match.
277 return 26; // "eip"
278 case 'z': // 1 string to match.
279 return 27; // "eiz"
280 }
281 break;
282 case 's': // 2 strings to match.
283 switch (Name[2]) {
284 default: break;
285 case 'i': // 1 string to match.
286 return 29; // "esi"
287 case 'p': // 1 string to match.
288 return 30; // "esp"
289 }
290 break;
291 }
292 break;
293 case 'f': // 8 strings to match.
294 if (Name[1] != 'p')
295 break;
296 switch (Name[2]) {
297 default: break;
298 case '0': // 1 string to match.
299 return 87; // "fp0"
300 case '1': // 1 string to match.
301 return 88; // "fp1"
302 case '2': // 1 string to match.
303 return 89; // "fp2"
304 case '3': // 1 string to match.
305 return 90; // "fp3"
306 case '4': // 1 string to match.
307 return 91; // "fp4"
308 case '5': // 1 string to match.
309 return 92; // "fp5"
310 case '6': // 1 string to match.
311 return 93; // "fp6"
312 case '7': // 1 string to match.
313 return 94; // "fp7"
314 }
315 break;
316 case 'm': // 8 strings to match.
317 if (Name[1] != 'm')
318 break;
319 switch (Name[2]) {
320 default: break;
321 case '0': // 1 string to match.
322 return 103; // "mm0"
323 case '1': // 1 string to match.
324 return 104; // "mm1"
325 case '2': // 1 string to match.
326 return 105; // "mm2"
327 case '3': // 1 string to match.
328 return 106; // "mm3"
329 case '4': // 1 string to match.
330 return 107; // "mm4"
331 case '5': // 1 string to match.
332 return 108; // "mm5"
333 case '6': // 1 string to match.
334 return 109; // "mm6"
335 case '7': // 1 string to match.
336 return 110; // "mm7"
337 }
338 break;
339 case 'r': // 22 strings to match.
340 switch (Name[1]) {
341 default: break;
342 case '1': // 6 strings to match.
343 switch (Name[2]) {
344 default: break;
345 case '0': // 1 string to match.
346 return 113; // "r10"
347 case '1': // 1 string to match.
348 return 114; // "r11"
349 case '2': // 1 string to match.
350 return 115; // "r12"
351 case '3': // 1 string to match.
352 return 116; // "r13"
353 case '4': // 1 string to match.
354 return 117; // "r14"
355 case '5': // 1 string to match.
356 return 118; // "r15"
357 }
358 break;
359 case '8': // 3 strings to match.
360 switch (Name[2]) {
361 default: break;
362 case 'b': // 1 string to match.
363 return 223; // "r8b"
364 case 'd': // 1 string to match.
365 return 231; // "r8d"
366 case 'w': // 1 string to match.
367 return 239; // "r8w"
368 }
369 break;
370 case '9': // 3 strings to match.
371 switch (Name[2]) {
372 default: break;
373 case 'b': // 1 string to match.
374 return 224; // "r9b"
375 case 'd': // 1 string to match.
376 return 232; // "r9d"
377 case 'w': // 1 string to match.
378 return 240; // "r9w"
379 }
380 break;
381 case 'a': // 1 string to match.
382 if (Name[2] != 'x')
383 break;
384 return 35; // "rax"
385 case 'b': // 2 strings to match.
386 switch (Name[2]) {
387 default: break;
388 case 'p': // 1 string to match.
389 return 36; // "rbp"
390 case 'x': // 1 string to match.
391 return 37; // "rbx"
392 }
393 break;
394 case 'c': // 1 string to match.
395 if (Name[2] != 'x')
396 break;
397 return 38; // "rcx"
398 case 'd': // 2 strings to match.
399 switch (Name[2]) {
400 default: break;
401 case 'i': // 1 string to match.
402 return 39; // "rdi"
403 case 'x': // 1 string to match.
404 return 40; // "rdx"
405 }
406 break;
407 case 'i': // 2 strings to match.
408 switch (Name[2]) {
409 default: break;
410 case 'p': // 1 string to match.
411 return 41; // "rip"
412 case 'z': // 1 string to match.
413 return 42; // "riz"
414 }
415 break;
416 case 's': // 2 strings to match.
417 switch (Name[2]) {
418 default: break;
419 case 'i': // 1 string to match.
420 return 43; // "rsi"
421 case 'p': // 1 string to match.
422 return 44; // "rsp"
423 }
424 break;
425 }
426 break;
427 case 's': // 3 strings to match.
428 switch (Name[1]) {
429 default: break;
430 case 'i': // 1 string to match.
431 if (Name[2] != 'l')
432 break;
433 return 46; // "sil"
434 case 'p': // 1 string to match.
435 if (Name[2] != 'l')
436 break;
437 return 48; // "spl"
438 case 's': // 1 string to match.
439 if (Name[2] != 'p')
440 break;
441 return 50; // "ssp"
442 }
443 break;
444 }
445 break;
446 case 4: // 65 strings to match.
447 switch (Name[0]) {
448 default: break;
449 case 'b': // 4 strings to match.
450 if (memcmp(Name.data()+1, "nd", 2) != 0)
451 break;
452 switch (Name[3]) {
453 default: break;
454 case '0': // 1 string to match.
455 return 51; // "bnd0"
456 case '1': // 1 string to match.
457 return 52; // "bnd1"
458 case '2': // 1 string to match.
459 return 53; // "bnd2"
460 case '3': // 1 string to match.
461 return 54; // "bnd3"
462 }
463 break;
464 case 'c': // 6 strings to match.
465 if (memcmp(Name.data()+1, "r1", 2) != 0)
466 break;
467 switch (Name[3]) {
468 default: break;
469 case '0': // 1 string to match.
470 return 65; // "cr10"
471 case '1': // 1 string to match.
472 return 66; // "cr11"
473 case '2': // 1 string to match.
474 return 67; // "cr12"
475 case '3': // 1 string to match.
476 return 68; // "cr13"
477 case '4': // 1 string to match.
478 return 69; // "cr14"
479 case '5': // 1 string to match.
480 return 70; // "cr15"
481 }
482 break;
483 case 'd': // 6 strings to match.
484 if (memcmp(Name.data()+1, "r1", 2) != 0)
485 break;
486 switch (Name[3]) {
487 default: break;
488 case '0': // 1 string to match.
489 return 81; // "dr10"
490 case '1': // 1 string to match.
491 return 82; // "dr11"
492 case '2': // 1 string to match.
493 return 83; // "dr12"
494 case '3': // 1 string to match.
495 return 84; // "dr13"
496 case '4': // 1 string to match.
497 return 85; // "dr14"
498 case '5': // 1 string to match.
499 return 86; // "dr15"
500 }
501 break;
502 case 'f': // 1 string to match.
503 if (memcmp(Name.data()+1, "psw", 3) != 0)
504 break;
505 return 31; // "fpsw"
506 case 'r': // 18 strings to match.
507 if (Name[1] != '1')
508 break;
509 switch (Name[2]) {
510 default: break;
511 case '0': // 3 strings to match.
512 switch (Name[3]) {
513 default: break;
514 case 'b': // 1 string to match.
515 return 225; // "r10b"
516 case 'd': // 1 string to match.
517 return 233; // "r10d"
518 case 'w': // 1 string to match.
519 return 241; // "r10w"
520 }
521 break;
522 case '1': // 3 strings to match.
523 switch (Name[3]) {
524 default: break;
525 case 'b': // 1 string to match.
526 return 226; // "r11b"
527 case 'd': // 1 string to match.
528 return 234; // "r11d"
529 case 'w': // 1 string to match.
530 return 242; // "r11w"
531 }
532 break;
533 case '2': // 3 strings to match.
534 switch (Name[3]) {
535 default: break;
536 case 'b': // 1 string to match.
537 return 227; // "r12b"
538 case 'd': // 1 string to match.
539 return 235; // "r12d"
540 case 'w': // 1 string to match.
541 return 243; // "r12w"
542 }
543 break;
544 case '3': // 3 strings to match.
545 switch (Name[3]) {
546 default: break;
547 case 'b': // 1 string to match.
548 return 228; // "r13b"
549 case 'd': // 1 string to match.
550 return 236; // "r13d"
551 case 'w': // 1 string to match.
552 return 244; // "r13w"
553 }
554 break;
555 case '4': // 3 strings to match.
556 switch (Name[3]) {
557 default: break;
558 case 'b': // 1 string to match.
559 return 229; // "r14b"
560 case 'd': // 1 string to match.
561 return 237; // "r14d"
562 case 'w': // 1 string to match.
563 return 245; // "r14w"
564 }
565 break;
566 case '5': // 3 strings to match.
567 switch (Name[3]) {
568 default: break;
569 case 'b': // 1 string to match.
570 return 230; // "r15b"
571 case 'd': // 1 string to match.
572 return 238; // "r15d"
573 case 'w': // 1 string to match.
574 return 246; // "r15w"
575 }
576 break;
577 }
578 break;
579 case 'x': // 10 strings to match.
580 if (memcmp(Name.data()+1, "mm", 2) != 0)
581 break;
582 switch (Name[3]) {
583 default: break;
584 case '0': // 1 string to match.
585 return 127; // "xmm0"
586 case '1': // 1 string to match.
587 return 128; // "xmm1"
588 case '2': // 1 string to match.
589 return 129; // "xmm2"
590 case '3': // 1 string to match.
591 return 130; // "xmm3"
592 case '4': // 1 string to match.
593 return 131; // "xmm4"
594 case '5': // 1 string to match.
595 return 132; // "xmm5"
596 case '6': // 1 string to match.
597 return 133; // "xmm6"
598 case '7': // 1 string to match.
599 return 134; // "xmm7"
600 case '8': // 1 string to match.
601 return 135; // "xmm8"
602 case '9': // 1 string to match.
603 return 136; // "xmm9"
604 }
605 break;
606 case 'y': // 10 strings to match.
607 if (memcmp(Name.data()+1, "mm", 2) != 0)
608 break;
609 switch (Name[3]) {
610 default: break;
611 case '0': // 1 string to match.
612 return 159; // "ymm0"
613 case '1': // 1 string to match.
614 return 160; // "ymm1"
615 case '2': // 1 string to match.
616 return 161; // "ymm2"
617 case '3': // 1 string to match.
618 return 162; // "ymm3"
619 case '4': // 1 string to match.
620 return 163; // "ymm4"
621 case '5': // 1 string to match.
622 return 164; // "ymm5"
623 case '6': // 1 string to match.
624 return 165; // "ymm6"
625 case '7': // 1 string to match.
626 return 166; // "ymm7"
627 case '8': // 1 string to match.
628 return 167; // "ymm8"
629 case '9': // 1 string to match.
630 return 168; // "ymm9"
631 }
632 break;
633 case 'z': // 10 strings to match.
634 if (memcmp(Name.data()+1, "mm", 2) != 0)
635 break;
636 switch (Name[3]) {
637 default: break;
638 case '0': // 1 string to match.
639 return 191; // "zmm0"
640 case '1': // 1 string to match.
641 return 192; // "zmm1"
642 case '2': // 1 string to match.
643 return 193; // "zmm2"
644 case '3': // 1 string to match.
645 return 194; // "zmm3"
646 case '4': // 1 string to match.
647 return 195; // "zmm4"
648 case '5': // 1 string to match.
649 return 196; // "zmm5"
650 case '6': // 1 string to match.
651 return 197; // "zmm6"
652 case '7': // 1 string to match.
653 return 198; // "zmm7"
654 case '8': // 1 string to match.
655 return 199; // "zmm8"
656 case '9': // 1 string to match.
657 return 200; // "zmm9"
658 }
659 break;
660 }
661 break;
662 case 5: // 75 strings to match.
663 switch (Name[0]) {
664 default: break;
665 case 'f': // 1 string to match.
666 if (memcmp(Name.data()+1, "lags", 4) != 0)
667 break;
668 return 25; // "flags"
669 case 's': // 8 strings to match.
670 if (memcmp(Name.data()+1, "t(", 2) != 0)
671 break;
672 switch (Name[3]) {
673 default: break;
674 case '0': // 1 string to match.
675 if (Name[4] != ')')
676 break;
677 return 119; // "st(0)"
678 case '1': // 1 string to match.
679 if (Name[4] != ')')
680 break;
681 return 120; // "st(1)"
682 case '2': // 1 string to match.
683 if (Name[4] != ')')
684 break;
685 return 121; // "st(2)"
686 case '3': // 1 string to match.
687 if (Name[4] != ')')
688 break;
689 return 122; // "st(3)"
690 case '4': // 1 string to match.
691 if (Name[4] != ')')
692 break;
693 return 123; // "st(4)"
694 case '5': // 1 string to match.
695 if (Name[4] != ')')
696 break;
697 return 124; // "st(5)"
698 case '6': // 1 string to match.
699 if (Name[4] != ')')
700 break;
701 return 125; // "st(6)"
702 case '7': // 1 string to match.
703 if (Name[4] != ')')
704 break;
705 return 126; // "st(7)"
706 }
707 break;
708 case 'x': // 22 strings to match.
709 if (memcmp(Name.data()+1, "mm", 2) != 0)
710 break;
711 switch (Name[3]) {
712 default: break;
713 case '1': // 10 strings to match.
714 switch (Name[4]) {
715 default: break;
716 case '0': // 1 string to match.
717 return 137; // "xmm10"
718 case '1': // 1 string to match.
719 return 138; // "xmm11"
720 case '2': // 1 string to match.
721 return 139; // "xmm12"
722 case '3': // 1 string to match.
723 return 140; // "xmm13"
724 case '4': // 1 string to match.
725 return 141; // "xmm14"
726 case '5': // 1 string to match.
727 return 142; // "xmm15"
728 case '6': // 1 string to match.
729 return 143; // "xmm16"
730 case '7': // 1 string to match.
731 return 144; // "xmm17"
732 case '8': // 1 string to match.
733 return 145; // "xmm18"
734 case '9': // 1 string to match.
735 return 146; // "xmm19"
736 }
737 break;
738 case '2': // 10 strings to match.
739 switch (Name[4]) {
740 default: break;
741 case '0': // 1 string to match.
742 return 147; // "xmm20"
743 case '1': // 1 string to match.
744 return 148; // "xmm21"
745 case '2': // 1 string to match.
746 return 149; // "xmm22"
747 case '3': // 1 string to match.
748 return 150; // "xmm23"
749 case '4': // 1 string to match.
750 return 151; // "xmm24"
751 case '5': // 1 string to match.
752 return 152; // "xmm25"
753 case '6': // 1 string to match.
754 return 153; // "xmm26"
755 case '7': // 1 string to match.
756 return 154; // "xmm27"
757 case '8': // 1 string to match.
758 return 155; // "xmm28"
759 case '9': // 1 string to match.
760 return 156; // "xmm29"
761 }
762 break;
763 case '3': // 2 strings to match.
764 switch (Name[4]) {
765 default: break;
766 case '0': // 1 string to match.
767 return 157; // "xmm30"
768 case '1': // 1 string to match.
769 return 158; // "xmm31"
770 }
771 break;
772 }
773 break;
774 case 'y': // 22 strings to match.
775 if (memcmp(Name.data()+1, "mm", 2) != 0)
776 break;
777 switch (Name[3]) {
778 default: break;
779 case '1': // 10 strings to match.
780 switch (Name[4]) {
781 default: break;
782 case '0': // 1 string to match.
783 return 169; // "ymm10"
784 case '1': // 1 string to match.
785 return 170; // "ymm11"
786 case '2': // 1 string to match.
787 return 171; // "ymm12"
788 case '3': // 1 string to match.
789 return 172; // "ymm13"
790 case '4': // 1 string to match.
791 return 173; // "ymm14"
792 case '5': // 1 string to match.
793 return 174; // "ymm15"
794 case '6': // 1 string to match.
795 return 175; // "ymm16"
796 case '7': // 1 string to match.
797 return 176; // "ymm17"
798 case '8': // 1 string to match.
799 return 177; // "ymm18"
800 case '9': // 1 string to match.
801 return 178; // "ymm19"
802 }
803 break;
804 case '2': // 10 strings to match.
805 switch (Name[4]) {
806 default: break;
807 case '0': // 1 string to match.
808 return 179; // "ymm20"
809 case '1': // 1 string to match.
810 return 180; // "ymm21"
811 case '2': // 1 string to match.
812 return 181; // "ymm22"
813 case '3': // 1 string to match.
814 return 182; // "ymm23"
815 case '4': // 1 string to match.
816 return 183; // "ymm24"
817 case '5': // 1 string to match.
818 return 184; // "ymm25"
819 case '6': // 1 string to match.
820 return 185; // "ymm26"
821 case '7': // 1 string to match.
822 return 186; // "ymm27"
823 case '8': // 1 string to match.
824 return 187; // "ymm28"
825 case '9': // 1 string to match.
826 return 188; // "ymm29"
827 }
828 break;
829 case '3': // 2 strings to match.
830 switch (Name[4]) {
831 default: break;
832 case '0': // 1 string to match.
833 return 189; // "ymm30"
834 case '1': // 1 string to match.
835 return 190; // "ymm31"
836 }
837 break;
838 }
839 break;
840 case 'z': // 22 strings to match.
841 if (memcmp(Name.data()+1, "mm", 2) != 0)
842 break;
843 switch (Name[3]) {
844 default: break;
845 case '1': // 10 strings to match.
846 switch (Name[4]) {
847 default: break;
848 case '0': // 1 string to match.
849 return 201; // "zmm10"
850 case '1': // 1 string to match.
851 return 202; // "zmm11"
852 case '2': // 1 string to match.
853 return 203; // "zmm12"
854 case '3': // 1 string to match.
855 return 204; // "zmm13"
856 case '4': // 1 string to match.
857 return 205; // "zmm14"
858 case '5': // 1 string to match.
859 return 206; // "zmm15"
860 case '6': // 1 string to match.
861 return 207; // "zmm16"
862 case '7': // 1 string to match.
863 return 208; // "zmm17"
864 case '8': // 1 string to match.
865 return 209; // "zmm18"
866 case '9': // 1 string to match.
867 return 210; // "zmm19"
868 }
869 break;
870 case '2': // 10 strings to match.
871 switch (Name[4]) {
872 default: break;
873 case '0': // 1 string to match.
874 return 211; // "zmm20"
875 case '1': // 1 string to match.
876 return 212; // "zmm21"
877 case '2': // 1 string to match.
878 return 213; // "zmm22"
879 case '3': // 1 string to match.
880 return 214; // "zmm23"
881 case '4': // 1 string to match.
882 return 215; // "zmm24"
883 case '5': // 1 string to match.
884 return 216; // "zmm25"
885 case '6': // 1 string to match.
886 return 217; // "zmm26"
887 case '7': // 1 string to match.
888 return 218; // "zmm27"
889 case '8': // 1 string to match.
890 return 219; // "zmm28"
891 case '9': // 1 string to match.
892 return 220; // "zmm29"
893 }
894 break;
895 case '3': // 2 strings to match.
896 switch (Name[4]) {
897 default: break;
898 case '0': // 1 string to match.
899 return 221; // "zmm30"
900 case '1': // 1 string to match.
901 return 222; // "zmm31"
902 }
903 break;
904 }
905 break;
906 }
907 break;
908 }
909 return 0;
910}
911
912#endif // GET_REGISTER_MATCHER
913
914
915#ifdef GET_SUBTARGET_FEATURE_NAME
916#undef GET_SUBTARGET_FEATURE_NAME
917
918// User-level names for subtarget features that participate in
919// instruction matching.
920static const char *getSubtargetFeatureName(uint64_t Val) {
921 switch(Val) {
922 case Feature_HasAVX512: return "AVX-512 ISA";
923 case Feature_HasCDI: return "AVX-512 CD ISA";
924 case Feature_HasVPOPCNTDQ: return "AVX-512 VPOPCNTDQ ISA";
925 case Feature_HasPFI: return "AVX-512 PF ISA";
926 case Feature_HasERI: return "AVX-512 ER ISA";
927 case Feature_HasDQI: return "AVX-512 DQ ISA";
928 case Feature_HasBWI: return "AVX-512 BW ISA";
929 case Feature_HasVLX: return "AVX-512 VL ISA";
930 case Feature_HasVNNI: return "AVX-512 VNNI ISA";
931 case Feature_HasBITALG: return "AVX-512 BITALG ISA";
932 case Feature_HasVBMI: return "AVX-512 VBMI ISA";
933 case Feature_HasVBMI2: return "AVX-512 VBMI2 ISA";
934 case Feature_HasIFMA: return "AVX-512 IFMA ISA";
935 case Feature_Not64BitMode: return "Not 64-bit mode";
936 case Feature_In64BitMode: return "64-bit mode";
937 case Feature_In16BitMode: return "16-bit mode";
938 case Feature_Not16BitMode: return "Not 16-bit mode";
939 case Feature_In32BitMode: return "32-bit mode";
940 default: return "(unknown)";
941 }
942}
943
944#endif // GET_SUBTARGET_FEATURE_NAME
945
946
947#ifdef GET_MATCHER_IMPLEMENTATION
948#undef GET_MATCHER_IMPLEMENTATION
949
950static void applyMnemonicAliases(StringRef &Mnemonic, uint64_t Features, unsigned VariantID) {
951 switch (VariantID) {
952 case 0:
953 switch (Mnemonic.size()) {
954 default: break;
955 case 3: // 6 strings to match.
956 switch (Mnemonic[0]) {
957 default: break;
958 case 'c': // 4 strings to match.
959 switch (Mnemonic[1]) {
960 default: break;
961 case 'b': // 1 string to match.
962 if (Mnemonic[2] != 'w')
963 break;
964 Mnemonic = "cbtw"; // "cbw"
965 return;
966 case 'd': // 1 string to match.
967 if (Mnemonic[2] != 'q')
968 break;
969 Mnemonic = "cltd"; // "cdq"
970 return;
971 case 'q': // 1 string to match.
972 if (Mnemonic[2] != 'o')
973 break;
974 Mnemonic = "cqto"; // "cqo"
975 return;
976 case 'w': // 1 string to match.
977 if (Mnemonic[2] != 'd')
978 break;
979 Mnemonic = "cwtd"; // "cwd"
980 return;
981 }
982 break;
983 case 'p': // 1 string to match.
984 if (memcmp(Mnemonic.data()+1, "op", 2) != 0)
985 break;
986 if ((Features & Feature_In16BitMode) == Feature_In16BitMode) // "pop"
987 Mnemonic = "popw";
988 else if ((Features & Feature_In32BitMode) == Feature_In32BitMode)
989 Mnemonic = "popl";
990 else if ((Features & Feature_In64BitMode) == Feature_In64BitMode)
991 Mnemonic = "popq";
992 return;
993 case 'r': // 1 string to match.
994 if (memcmp(Mnemonic.data()+1, "et", 2) != 0)
995 break;
996 if ((Features & Feature_In16BitMode) == Feature_In16BitMode) // "ret"
997 Mnemonic = "retw";
998 else if ((Features & Feature_In32BitMode) == Feature_In32BitMode)
999 Mnemonic = "retl";
1000 else if ((Features & Feature_In64BitMode) == Feature_In64BitMode)
1001 Mnemonic = "retq";
1002 return;
1003 }
1004 break;
1005 case 4: // 18 strings to match.
1006 switch (Mnemonic[0]) {
1007 default: break;
1008 case 'c': // 3 strings to match.
1009 switch (Mnemonic[1]) {
1010 default: break;
1011 case 'a': // 1 string to match.
1012 if (memcmp(Mnemonic.data()+2, "ll", 2) != 0)
1013 break;
1014 if ((Features & Feature_In16BitMode) == Feature_In16BitMode) // "call"
1015 Mnemonic = "callw";
1016 else if ((Features & Feature_In32BitMode) == Feature_In32BitMode)
1017 Mnemonic = "calll";
1018 else if ((Features & Feature_In64BitMode) == Feature_In64BitMode)
1019 Mnemonic = "callq";
1020 return;
1021 case 'd': // 1 string to match.
1022 if (memcmp(Mnemonic.data()+2, "qe", 2) != 0)
1023 break;
1024 Mnemonic = "cltq"; // "cdqe"
1025 return;
1026 case 'w': // 1 string to match.
1027 if (memcmp(Mnemonic.data()+2, "de", 2) != 0)
1028 break;
1029 Mnemonic = "cwtl"; // "cwde"
1030 return;
1031 }
1032 break;
1033 case 'i': // 1 string to match.
1034 if (memcmp(Mnemonic.data()+1, "ret", 3) != 0)
1035 break;
1036 if ((Features & Feature_In16BitMode) == Feature_In16BitMode) // "iret"
1037 Mnemonic = "iretw";
1038 else if ((Features & Feature_Not16BitMode) == Feature_Not16BitMode)
1039 Mnemonic = "iretl";
1040 return;
1041 case 'l': // 3 strings to match.
1042 switch (Mnemonic[1]) {
1043 default: break;
1044 case 'g': // 1 string to match.
1045 if (memcmp(Mnemonic.data()+2, "dt", 2) != 0)
1046 break;
1047 if ((Features & Feature_In16BitMode) == Feature_In16BitMode) // "lgdt"
1048 Mnemonic = "lgdtw";
1049 else if ((Features & Feature_In32BitMode) == Feature_In32BitMode)
1050 Mnemonic = "lgdtl";
1051 else if ((Features & Feature_In64BitMode) == Feature_In64BitMode)
1052 Mnemonic = "lgdtq";
1053 return;
1054 case 'i': // 1 string to match.
1055 if (memcmp(Mnemonic.data()+2, "dt", 2) != 0)
1056 break;
1057 if ((Features & Feature_In16BitMode) == Feature_In16BitMode) // "lidt"
1058 Mnemonic = "lidtw";
1059 else if ((Features & Feature_In32BitMode) == Feature_In32BitMode)
1060 Mnemonic = "lidtl";
1061 else if ((Features & Feature_In64BitMode) == Feature_In64BitMode)
1062 Mnemonic = "lidtq";
1063 return;
1064 case 'r': // 1 string to match.
1065 if (memcmp(Mnemonic.data()+2, "et", 2) != 0)
1066 break;
1067 if ((Features & Feature_In16BitMode) == Feature_In16BitMode) // "lret"
1068 Mnemonic = "lretw";
1069 else if ((Features & Feature_Not16BitMode) == Feature_Not16BitMode)
1070 Mnemonic = "lretl";
1071 return;
1072 }
1073 break;
1074 case 'p': // 3 strings to match.
1075 switch (Mnemonic[1]) {
1076 default: break;
1077 case 'o': // 2 strings to match.
1078 if (Mnemonic[2] != 'p')
1079 break;
1080 switch (Mnemonic[3]) {
1081 default: break;
1082 case 'a': // 1 string to match.
1083 if ((Features & Feature_In16BitMode) == Feature_In16BitMode) // "popa"
1084 Mnemonic = "popaw";
1085 else if ((Features & Feature_In32BitMode) == Feature_In32BitMode)
1086 Mnemonic = "popal";
1087 return;
1088 case 'f': // 1 string to match.
1089 if ((Features & Feature_In16BitMode) == Feature_In16BitMode) // "popf"
1090 Mnemonic = "popfw";
1091 else if ((Features & Feature_In32BitMode) == Feature_In32BitMode)
1092 Mnemonic = "popfl";
1093 else if ((Features & Feature_In64BitMode) == Feature_In64BitMode)
1094 Mnemonic = "popfq";
1095 return;
1096 }
1097 break;
1098 case 'u': // 1 string to match.
1099 if (memcmp(Mnemonic.data()+2, "sh", 2) != 0)
1100 break;
1101 if ((Features & Feature_In16BitMode) == Feature_In16BitMode) // "push"
1102 Mnemonic = "pushw";
1103 else if ((Features & Feature_In32BitMode) == Feature_In32BitMode)
1104 Mnemonic = "pushl";
1105 else if ((Features & Feature_In64BitMode) == Feature_In64BitMode)
1106 Mnemonic = "pushq";
1107 return;
1108 }
1109 break;
1110 case 'r': // 1 string to match.
1111 if (memcmp(Mnemonic.data()+1, "etn", 3) != 0)
1112 break;
1113 if ((Features & Feature_In16BitMode) == Feature_In16BitMode) // "retn"
1114 Mnemonic = "retw";
1115 else if ((Features & Feature_In32BitMode) == Feature_In32BitMode)
1116 Mnemonic = "retl";
1117 else if ((Features & Feature_In64BitMode) == Feature_In64BitMode)
1118 Mnemonic = "retq";
1119 return;
1120 case 's': // 6 strings to match.
1121 switch (Mnemonic[1]) {
1122 default: break;
1123 case 'a': // 4 strings to match.
1124 if (Mnemonic[2] != 'l')
1125 break;
1126 switch (Mnemonic[3]) {
1127 default: break;
1128 case 'b': // 1 string to match.
1129 Mnemonic = "shlb"; // "salb"
1130 return;
1131 case 'l': // 1 string to match.
1132 Mnemonic = "shll"; // "sall"
1133 return;
1134 case 'q': // 1 string to match.
1135 Mnemonic = "shlq"; // "salq"
1136 return;
1137 case 'w': // 1 string to match.
1138 Mnemonic = "shlw"; // "salw"
1139 return;
1140 }
1141 break;
1142 case 'g': // 1 string to match.
1143 if (memcmp(Mnemonic.data()+2, "dt", 2) != 0)
1144 break;
1145 if ((Features & Feature_In16BitMode) == Feature_In16BitMode) // "sgdt"
1146 Mnemonic = "sgdtw";
1147 else if ((Features & Feature_In32BitMode) == Feature_In32BitMode)
1148 Mnemonic = "sgdtl";
1149 else if ((Features & Feature_In64BitMode) == Feature_In64BitMode)
1150 Mnemonic = "sgdtq";
1151 return;
1152 case 'i': // 1 string to match.
1153 if (memcmp(Mnemonic.data()+2, "dt", 2) != 0)
1154 break;
1155 if ((Features & Feature_In16BitMode) == Feature_In16BitMode) // "sidt"
1156 Mnemonic = "sidtw";
1157 else if ((Features & Feature_In32BitMode) == Feature_In32BitMode)
1158 Mnemonic = "sidtl";
1159 else if ((Features & Feature_In64BitMode) == Feature_In64BitMode)
1160 Mnemonic = "sidtq";
1161 return;
1162 }
1163 break;
1164 case 'u': // 1 string to match.
1165 if (memcmp(Mnemonic.data()+1, "d2a", 3) != 0)
1166 break;
1167 Mnemonic = "ud2"; // "ud2a"
1168 return;
1169 }
1170 break;
1171 case 5: // 9 strings to match.
1172 switch (Mnemonic[0]) {
1173 default: break;
1174 case 'f': // 1 string to match.
1175 if (memcmp(Mnemonic.data()+1, "ildq", 4) != 0)
1176 break;
1177 Mnemonic = "fildll"; // "fildq"
1178 return;
1179 case 'p': // 3 strings to match.
1180 switch (Mnemonic[1]) {
1181 default: break;
1182 case 'o': // 1 string to match.
1183 if (memcmp(Mnemonic.data()+2, "pfd", 3) != 0)
1184 break;
1185 Mnemonic = "popfl"; // "popfd"
1186 return;
1187 case 'u': // 2 strings to match.
1188 if (memcmp(Mnemonic.data()+2, "sh", 2) != 0)
1189 break;
1190 switch (Mnemonic[4]) {
1191 default: break;
1192 case 'a': // 1 string to match.
1193 if ((Features & Feature_In16BitMode) == Feature_In16BitMode) // "pusha"
1194 Mnemonic = "pushaw";
1195 else if ((Features & Feature_In32BitMode) == Feature_In32BitMode)
1196 Mnemonic = "pushal";
1197 return;
1198 case 'f': // 1 string to match.
1199 if ((Features & Feature_In16BitMode) == Feature_In16BitMode) // "pushf"
1200 Mnemonic = "pushfw";
1201 else if ((Features & Feature_In32BitMode) == Feature_In32BitMode)
1202 Mnemonic = "pushfl";
1203 else if ((Features & Feature_In64BitMode) == Feature_In64BitMode)
1204 Mnemonic = "pushfq";
1205 return;
1206 }
1207 break;
1208 }
1209 break;
1210 case 's': // 4 strings to match.
1211 if (memcmp(Mnemonic.data()+1, "mov", 3) != 0)
1212 break;
1213 switch (Mnemonic[4]) {
1214 default: break;
1215 case 'b': // 1 string to match.
1216 Mnemonic = "movsb"; // "smovb"
1217 return;
1218 case 'l': // 1 string to match.
1219 Mnemonic = "movsl"; // "smovl"
1220 return;
1221 case 'q': // 1 string to match.
1222 Mnemonic = "movsq"; // "smovq"
1223 return;
1224 case 'w': // 1 string to match.
1225 Mnemonic = "movsw"; // "smovw"
1226 return;
1227 }
1228 break;
1229 case 'v': // 1 string to match.
1230 if (memcmp(Mnemonic.data()+1, "errw", 4) != 0)
1231 break;
1232 Mnemonic = "verr"; // "verrw"
1233 return;
1234 }
1235 break;
1236 case 6: // 15 strings to match.
1237 switch (Mnemonic[0]) {
1238 default: break;
1239 case 'c': // 6 strings to match.
1240 if (memcmp(Mnemonic.data()+1, "mov", 3) != 0)
1241 break;
1242 switch (Mnemonic[4]) {
1243 default: break;
1244 case 'c': // 3 strings to match.
1245 switch (Mnemonic[5]) {
1246 default: break;
1247 case 'l': // 1 string to match.
1248 Mnemonic = "cmovbl"; // "cmovcl"
1249 return;
1250 case 'q': // 1 string to match.
1251 Mnemonic = "cmovbq"; // "cmovcq"
1252 return;
1253 case 'w': // 1 string to match.
1254 Mnemonic = "cmovbw"; // "cmovcw"
1255 return;
1256 }
1257 break;
1258 case 'z': // 3 strings to match.
1259 switch (Mnemonic[5]) {
1260 default: break;
1261 case 'l': // 1 string to match.
1262 Mnemonic = "cmovel"; // "cmovzl"
1263 return;
1264 case 'q': // 1 string to match.
1265 Mnemonic = "cmoveq"; // "cmovzq"
1266 return;
1267 case 'w': // 1 string to match.
1268 Mnemonic = "cmovew"; // "cmovzw"
1269 return;
1270 }
1271 break;
1272 }
1273 break;
1274 case 'f': // 4 strings to match.
1275 switch (Mnemonic[1]) {
1276 default: break;
1277 case 'c': // 2 strings to match.
1278 if (memcmp(Mnemonic.data()+2, "mov", 3) != 0)
1279 break;
1280 switch (Mnemonic[5]) {
1281 default: break;
1282 case 'a': // 1 string to match.
1283 Mnemonic = "fcmovnbe"; // "fcmova"
1284 return;
1285 case 'z': // 1 string to match.
1286 Mnemonic = "fcmove"; // "fcmovz"
1287 return;
1288 }
1289 break;
1290 case 'i': // 1 string to match.
1291 if (memcmp(Mnemonic.data()+2, "stpq", 4) != 0)
1292 break;
1293 Mnemonic = "fistpll"; // "fistpq"
1294 return;
1295 case 'l': // 1 string to match.
1296 if (memcmp(Mnemonic.data()+2, "dcww", 4) != 0)
1297 break;
1298 Mnemonic = "fldcw"; // "fldcww"
1299 return;
1300 }
1301 break;
1302 case 'l': // 2 strings to match.
1303 if (memcmp(Mnemonic.data()+1, "eave", 4) != 0)
1304 break;
1305 switch (Mnemonic[5]) {
1306 default: break;
1307 case 'l': // 1 string to match.
1308 if ((Features & Feature_Not64BitMode) == Feature_Not64BitMode) // "leavel"
1309 Mnemonic = "leave";
1310 return;
1311 case 'q': // 1 string to match.
1312 if ((Features & Feature_In64BitMode) == Feature_In64BitMode) // "leaveq"
1313 Mnemonic = "leave";
1314 return;
1315 }
1316 break;
1317 case 'p': // 1 string to match.
1318 if (memcmp(Mnemonic.data()+1, "ushfd", 5) != 0)
1319 break;
1320 Mnemonic = "pushfl"; // "pushfd"
1321 return;
1322 case 's': // 1 string to match.
1323 if (memcmp(Mnemonic.data()+1, "ysret", 5) != 0)
1324 break;
1325 Mnemonic = "sysretl"; // "sysret"
1326 return;
1327 case 'x': // 1 string to match.
1328 if (memcmp(Mnemonic.data()+1, "saveq", 5) != 0)
1329 break;
1330 Mnemonic = "xsave64"; // "xsaveq"
1331 return;
1332 }
1333 break;
1334 case 7: // 34 strings to match.
1335 switch (Mnemonic[0]) {
1336 default: break;
1337 case 'c': // 24 strings to match.
1338 if (memcmp(Mnemonic.data()+1, "mov", 3) != 0)
1339 break;
1340 switch (Mnemonic[4]) {
1341 default: break;
1342 case 'n': // 18 strings to match.
1343 switch (Mnemonic[5]) {
1344 default: break;
1345 case 'a': // 3 strings to match.
1346 switch (Mnemonic[6]) {
1347 default: break;
1348 case 'l': // 1 string to match.
1349 Mnemonic = "cmovbel"; // "cmovnal"
1350 return;
1351 case 'q': // 1 string to match.
1352 Mnemonic = "cmovbeq"; // "cmovnaq"
1353 return;
1354 case 'w': // 1 string to match.
1355 Mnemonic = "cmovbew"; // "cmovnaw"
1356 return;
1357 }
1358 break;
1359 case 'b': // 3 strings to match.
1360 switch (Mnemonic[6]) {
1361 default: break;
1362 case 'l': // 1 string to match.
1363 Mnemonic = "cmovael"; // "cmovnbl"
1364 return;
1365 case 'q': // 1 string to match.
1366 Mnemonic = "cmovaeq"; // "cmovnbq"
1367 return;
1368 case 'w': // 1 string to match.
1369 Mnemonic = "cmovaew"; // "cmovnbw"
1370 return;
1371 }
1372 break;
1373 case 'c': // 3 strings to match.
1374 switch (Mnemonic[6]) {
1375 default: break;
1376 case 'l': // 1 string to match.
1377 Mnemonic = "cmovael"; // "cmovncl"
1378 return;
1379 case 'q': // 1 string to match.
1380 Mnemonic = "cmovaeq"; // "cmovncq"
1381 return;
1382 case 'w': // 1 string to match.
1383 Mnemonic = "cmovaew"; // "cmovncw"
1384 return;
1385 }
1386 break;
1387 case 'g': // 3 strings to match.
1388 switch (Mnemonic[6]) {
1389 default: break;
1390 case 'l': // 1 string to match.
1391 Mnemonic = "cmovlel"; // "cmovngl"
1392 return;
1393 case 'q': // 1 string to match.
1394 Mnemonic = "cmovleq"; // "cmovngq"
1395 return;
1396 case 'w': // 1 string to match.
1397 Mnemonic = "cmovlew"; // "cmovngw"
1398 return;
1399 }
1400 break;
1401 case 'l': // 3 strings to match.
1402 switch (Mnemonic[6]) {
1403 default: break;
1404 case 'l': // 1 string to match.
1405 Mnemonic = "cmovgel"; // "cmovnll"
1406 return;
1407 case 'q': // 1 string to match.
1408 Mnemonic = "cmovgeq"; // "cmovnlq"
1409 return;
1410 case 'w': // 1 string to match.
1411 Mnemonic = "cmovgew"; // "cmovnlw"
1412 return;
1413 }
1414 break;
1415 case 'z': // 3 strings to match.
1416 switch (Mnemonic[6]) {
1417 default: break;
1418 case 'l': // 1 string to match.
1419 Mnemonic = "cmovnel"; // "cmovnzl"
1420 return;
1421 case 'q': // 1 string to match.
1422 Mnemonic = "cmovneq"; // "cmovnzq"
1423 return;
1424 case 'w': // 1 string to match.
1425 Mnemonic = "cmovnew"; // "cmovnzw"
1426 return;
1427 }
1428 break;
1429 }
1430 break;
1431 case 'p': // 6 strings to match.
1432 switch (Mnemonic[5]) {
1433 default: break;
1434 case 'e': // 3 strings to match.
1435 switch (Mnemonic[6]) {
1436 default: break;
1437 case 'l': // 1 string to match.
1438 Mnemonic = "cmovpl"; // "cmovpel"
1439 return;
1440 case 'q': // 1 string to match.
1441 Mnemonic = "cmovpq"; // "cmovpeq"
1442 return;
1443 case 'w': // 1 string to match.
1444 Mnemonic = "cmovpw"; // "cmovpew"
1445 return;
1446 }
1447 break;
1448 case 'o': // 3 strings to match.
1449 switch (Mnemonic[6]) {
1450 default: break;
1451 case 'l': // 1 string to match.
1452 Mnemonic = "cmovnpl"; // "cmovpol"
1453 return;
1454 case 'q': // 1 string to match.
1455 Mnemonic = "cmovnpq"; // "cmovpoq"
1456 return;
1457 case 'w': // 1 string to match.
1458 Mnemonic = "cmovnpw"; // "cmovpow"
1459 return;
1460 }
1461 break;
1462 }
1463 break;
1464 }
1465 break;
1466 case 'f': // 6 strings to match.
1467 switch (Mnemonic[1]) {
1468 default: break;
1469 case 'c': // 2 strings to match.
1470 if (memcmp(Mnemonic.data()+2, "mov", 3) != 0)
1471 break;
1472 switch (Mnemonic[5]) {
1473 default: break;
1474 case 'a': // 1 string to match.
1475 if (Mnemonic[6] != 'e')
1476 break;
1477 Mnemonic = "fcmovnb"; // "fcmovae"
1478 return;
1479 case 'n': // 1 string to match.
1480 if (Mnemonic[6] != 'a')
1481 break;
1482 Mnemonic = "fcmovbe"; // "fcmovna"
1483 return;
1484 }
1485 break;
1486 case 'i': // 1 string to match.
1487 if (memcmp(Mnemonic.data()+2, "sttpq", 5) != 0)
1488 break;
1489 Mnemonic = "fisttpll"; // "fisttpq"
1490 return;
1491 case 'n': // 2 strings to match.
1492 if (memcmp(Mnemonic.data()+2, "st", 2) != 0)
1493 break;
1494 switch (Mnemonic[4]) {
1495 default: break;
1496 case 'c': // 1 string to match.
1497 if (memcmp(Mnemonic.data()+5, "ww", 2) != 0)
1498 break;
1499 Mnemonic = "fnstcw"; // "fnstcww"
1500 return;
1501 case 's': // 1 string to match.
1502 if (memcmp(Mnemonic.data()+5, "ww", 2) != 0)
1503 break;
1504 Mnemonic = "fnstsw"; // "fnstsww"
1505 return;
1506 }
1507 break;
1508 case 'x': // 1 string to match.
1509 if (memcmp(Mnemonic.data()+2, "saveq", 5) != 0)
1510 break;
1511 Mnemonic = "fxsave64"; // "fxsaveq"
1512 return;
1513 }
1514 break;
1515 case 's': // 1 string to match.
1516 if (memcmp(Mnemonic.data()+1, "ysexit", 6) != 0)
1517 break;
1518 Mnemonic = "sysexitl"; // "sysexit"
1519 return;
1520 case 'x': // 3 strings to match.
1521 switch (Mnemonic[1]) {
1522 default: break;
1523 case 'r': // 1 string to match.
1524 if (memcmp(Mnemonic.data()+2, "storq", 5) != 0)
1525 break;
1526 Mnemonic = "xrstor64"; // "xrstorq"
1527 return;
1528 case 's': // 2 strings to match.
1529 if (memcmp(Mnemonic.data()+2, "ave", 3) != 0)
1530 break;
1531 switch (Mnemonic[5]) {
1532 default: break;
1533 case 'c': // 1 string to match.
1534 if (Mnemonic[6] != 'q')
1535 break;
1536 Mnemonic = "xsavec64"; // "xsavecq"
1537 return;
1538 case 's': // 1 string to match.
1539 if (Mnemonic[6] != 'q')
1540 break;
1541 Mnemonic = "xsaves64"; // "xsavesq"
1542 return;
1543 }
1544 break;
1545 }
1546 break;
1547 }
1548 break;
1549 case 8: // 15 strings to match.
1550 switch (Mnemonic[0]) {
1551 default: break;
1552 case 'c': // 12 strings to match.
1553 if (memcmp(Mnemonic.data()+1, "movn", 4) != 0)
1554 break;
1555 switch (Mnemonic[5]) {
1556 default: break;
1557 case 'a': // 3 strings to match.
1558 if (Mnemonic[6] != 'e')
1559 break;
1560 switch (Mnemonic[7]) {
1561 default: break;
1562 case 'l': // 1 string to match.
1563 Mnemonic = "cmovbl"; // "cmovnael"
1564 return;
1565 case 'q': // 1 string to match.
1566 Mnemonic = "cmovbq"; // "cmovnaeq"
1567 return;
1568 case 'w': // 1 string to match.
1569 Mnemonic = "cmovbw"; // "cmovnaew"
1570 return;
1571 }
1572 break;
1573 case 'b': // 3 strings to match.
1574 if (Mnemonic[6] != 'e')
1575 break;
1576 switch (Mnemonic[7]) {
1577 default: break;
1578 case 'l': // 1 string to match.
1579 Mnemonic = "cmoval"; // "cmovnbel"
1580 return;
1581 case 'q': // 1 string to match.
1582 Mnemonic = "cmovaq"; // "cmovnbeq"
1583 return;
1584 case 'w': // 1 string to match.
1585 Mnemonic = "cmovaw"; // "cmovnbew"
1586 return;
1587 }
1588 break;
1589 case 'g': // 3 strings to match.
1590 if (Mnemonic[6] != 'e')
1591 break;
1592 switch (Mnemonic[7]) {
1593 default: break;
1594 case 'l': // 1 string to match.
1595 Mnemonic = "cmovll"; // "cmovngel"
1596 return;
1597 case 'q': // 1 string to match.
1598 Mnemonic = "cmovlq"; // "cmovngeq"
1599 return;
1600 case 'w': // 1 string to match.
1601 Mnemonic = "cmovlw"; // "cmovngew"
1602 return;
1603 }
1604 break;
1605 case 'l': // 3 strings to match.
1606 if (Mnemonic[6] != 'e')
1607 break;
1608 switch (Mnemonic[7]) {
1609 default: break;
1610 case 'l': // 1 string to match.
1611 Mnemonic = "cmovgl"; // "cmovnlel"
1612 return;
1613 case 'q': // 1 string to match.
1614 Mnemonic = "cmovgq"; // "cmovnleq"
1615 return;
1616 case 'w': // 1 string to match.
1617 Mnemonic = "cmovgw"; // "cmovnlew"
1618 return;
1619 }
1620 break;
1621 }
1622 break;
1623 case 'f': // 2 strings to match.
1624 switch (Mnemonic[1]) {
1625 default: break;
1626 case 'c': // 1 string to match.
1627 if (memcmp(Mnemonic.data()+2, "movnae", 6) != 0)
1628 break;
1629 Mnemonic = "fcmovb"; // "fcmovnae"
1630 return;
1631 case 'x': // 1 string to match.
1632 if (memcmp(Mnemonic.data()+2, "rstorq", 6) != 0)
1633 break;
1634 Mnemonic = "fxrstor64"; // "fxrstorq"
1635 return;
1636 }
1637 break;
1638 case 'x': // 1 string to match.
1639 if (memcmp(Mnemonic.data()+1, "rstorsq", 7) != 0)
1640 break;
1641 Mnemonic = "xrstors64"; // "xrstorsq"
1642 return;
1643 }
1644 break;
1645 case 9: // 1 string to match.
1646 if (memcmp(Mnemonic.data()+0, "xsaveoptq", 9) != 0)
1647 break;
1648 Mnemonic = "xsaveopt64"; // "xsaveoptq"
1649 return;
1650 }
1651 break;
1652 case 1:
1653 switch (Mnemonic.size()) {
1654 default: break;
1655 case 3: // 1 string to match.
1656 if (memcmp(Mnemonic.data()+0, "sal", 3) != 0)
1657 break;
1658 Mnemonic = "shl"; // "sal"
1659 return;
1660 case 4: // 3 strings to match.
1661 switch (Mnemonic[0]) {
1662 default: break;
1663 case 'p': // 2 strings to match.
1664 if (memcmp(Mnemonic.data()+1, "op", 2) != 0)
1665 break;
1666 switch (Mnemonic[3]) {
1667 default: break;
1668 case 'a': // 1 string to match.
1669 if ((Features & Feature_In16BitMode) == Feature_In16BitMode) // "popa"
1670 Mnemonic = "popaw";
1671 else if ((Features & Feature_In32BitMode) == Feature_In32BitMode)
1672 Mnemonic = "popal";
1673 return;
1674 case 'f': // 1 string to match.
1675 if ((Features & Feature_In64BitMode) == Feature_In64BitMode) // "popf"
1676 Mnemonic = "popfq";
1677 return;
1678 }
1679 break;
1680 case 'r': // 1 string to match.
1681 if (memcmp(Mnemonic.data()+1, "etn", 3) != 0)
1682 break;
1683 Mnemonic = "ret"; // "retn"
1684 return;
1685 }
1686 break;
1687 case 5: // 5 strings to match.
1688 switch (Mnemonic[0]) {
1689 default: break;
1690 case 'c': // 2 strings to match.
1691 if (memcmp(Mnemonic.data()+1, "mov", 3) != 0)
1692 break;
1693 switch (Mnemonic[4]) {
1694 default: break;
1695 case 'c': // 1 string to match.
1696 Mnemonic = "cmovb"; // "cmovc"
1697 return;
1698 case 'z': // 1 string to match.
1699 Mnemonic = "cmove"; // "cmovz"
1700 return;
1701 }
1702 break;
1703 case 'p': // 3 strings to match.
1704 switch (Mnemonic[1]) {
1705 default: break;
1706 case 'o': // 1 string to match.
1707 if (memcmp(Mnemonic.data()+2, "pad", 3) != 0)
1708 break;
1709 if ((Features & Feature_Not64BitMode) == Feature_Not64BitMode) // "popad"
1710 Mnemonic = "popal";
1711 return;
1712 case 'u': // 2 strings to match.
1713 if (memcmp(Mnemonic.data()+2, "sh", 2) != 0)
1714 break;
1715 switch (Mnemonic[4]) {
1716 default: break;
1717 case 'a': // 1 string to match.
1718 if ((Features & Feature_In16BitMode) == Feature_In16BitMode) // "pusha"
1719 Mnemonic = "pushaw";
1720 else if ((Features & Feature_In32BitMode) == Feature_In32BitMode)
1721 Mnemonic = "pushal";
1722 return;
1723 case 'f': // 1 string to match.
1724 if ((Features & Feature_In64BitMode) == Feature_In64BitMode) // "pushf"
1725 Mnemonic = "pushfq";
1726 return;
1727 }
1728 break;
1729 }
1730 break;
1731 }
1732 break;
1733 case 6: // 9 strings to match.
1734 switch (Mnemonic[0]) {
1735 default: break;
1736 case 'c': // 8 strings to match.
1737 if (memcmp(Mnemonic.data()+1, "mov", 3) != 0)
1738 break;
1739 switch (Mnemonic[4]) {
1740 default: break;
1741 case 'n': // 6 strings to match.
1742 switch (Mnemonic[5]) {
1743 default: break;
1744 case 'a': // 1 string to match.
1745 Mnemonic = "cmovbe"; // "cmovna"
1746 return;
1747 case 'b': // 1 string to match.
1748 Mnemonic = "cmovae"; // "cmovnb"
1749 return;
1750 case 'c': // 1 string to match.
1751 Mnemonic = "cmovae"; // "cmovnc"
1752 return;
1753 case 'g': // 1 string to match.
1754 Mnemonic = "cmovle"; // "cmovng"
1755 return;
1756 case 'l': // 1 string to match.
1757 Mnemonic = "cmovge"; // "cmovnl"
1758 return;
1759 case 'z': // 1 string to match.
1760 Mnemonic = "cmovne"; // "cmovnz"
1761 return;
1762 }
1763 break;
1764 case 'p': // 2 strings to match.
1765 switch (Mnemonic[5]) {
1766 default: break;
1767 case 'e': // 1 string to match.
1768 Mnemonic = "cmovp"; // "cmovpe"
1769 return;
1770 case 'o': // 1 string to match.
1771 Mnemonic = "cmovnp"; // "cmovpo"
1772 return;
1773 }
1774 break;
1775 }
1776 break;
1777 case 'p': // 1 string to match.
1778 if (memcmp(Mnemonic.data()+1, "ushad", 5) != 0)
1779 break;
1780 if ((Features & Feature_Not64BitMode) == Feature_Not64BitMode) // "pushad"
1781 Mnemonic = "pushal";
1782 return;
1783 }
1784 break;
1785 case 7: // 6 strings to match.
1786 switch (Mnemonic[0]) {
1787 default: break;
1788 case 'a': // 1 string to match.
1789 if (memcmp(Mnemonic.data()+1, "cquire", 6) != 0)
1790 break;
1791 Mnemonic = "xacquire"; // "acquire"
1792 return;
1793 case 'c': // 4 strings to match.
1794 if (memcmp(Mnemonic.data()+1, "movn", 4) != 0)
1795 break;
1796 switch (Mnemonic[5]) {
1797 default: break;
1798 case 'a': // 1 string to match.
1799 if (Mnemonic[6] != 'e')
1800 break;
1801 Mnemonic = "cmovb"; // "cmovnae"
1802 return;
1803 case 'b': // 1 string to match.
1804 if (Mnemonic[6] != 'e')
1805 break;
1806 Mnemonic = "cmova"; // "cmovnbe"
1807 return;
1808 case 'g': // 1 string to match.
1809 if (Mnemonic[6] != 'e')
1810 break;
1811 Mnemonic = "cmovl"; // "cmovnge"
1812 return;
1813 case 'l': // 1 string to match.
1814 if (Mnemonic[6] != 'e')
1815 break;
1816 Mnemonic = "cmovg"; // "cmovnle"
1817 return;
1818 }
1819 break;
1820 case 'r': // 1 string to match.
1821 if (memcmp(Mnemonic.data()+1, "elease", 6) != 0)
1822 break;
1823 Mnemonic = "xrelease"; // "release"
1824 return;
1825 }
1826 break;
1827 }
1828 break;
1829 }
1830 switch (Mnemonic.size()) {
1831 default: break;
1832 case 2: // 2 strings to match.
1833 if (Mnemonic[0] != 'j')
1834 break;
1835 switch (Mnemonic[1]) {
1836 default: break;
1837 case 'c': // 1 string to match.
1838 Mnemonic = "jb"; // "jc"
1839 return;
1840 case 'z': // 1 string to match.
1841 Mnemonic = "je"; // "jz"
1842 return;
1843 }
1844 break;
1845 case 3: // 8 strings to match.
1846 if (Mnemonic[0] != 'j')
1847 break;
1848 switch (Mnemonic[1]) {
1849 default: break;
1850 case 'n': // 6 strings to match.
1851 switch (Mnemonic[2]) {
1852 default: break;
1853 case 'a': // 1 string to match.
1854 Mnemonic = "jbe"; // "jna"
1855 return;
1856 case 'b': // 1 string to match.
1857 Mnemonic = "jae"; // "jnb"
1858 return;
1859 case 'c': // 1 string to match.
1860 Mnemonic = "jae"; // "jnc"
1861 return;
1862 case 'g': // 1 string to match.
1863 Mnemonic = "jle"; // "jng"
1864 return;
1865 case 'l': // 1 string to match.
1866 Mnemonic = "jge"; // "jnl"
1867 return;
1868 case 'z': // 1 string to match.
1869 Mnemonic = "jne"; // "jnz"
1870 return;
1871 }
1872 break;
1873 case 'p': // 2 strings to match.
1874 switch (Mnemonic[2]) {
1875 default: break;
1876 case 'e': // 1 string to match.
1877 Mnemonic = "jp"; // "jpe"
1878 return;
1879 case 'o': // 1 string to match.
1880 Mnemonic = "jnp"; // "jpo"
1881 return;
1882 }
1883 break;
1884 }
1885 break;
1886 case 4: // 8 strings to match.
1887 switch (Mnemonic[0]) {
1888 default: break;
1889 case 'j': // 4 strings to match.
1890 if (Mnemonic[1] != 'n')
1891 break;
1892 switch (Mnemonic[2]) {
1893 default: break;
1894 case 'a': // 1 string to match.
1895 if (Mnemonic[3] != 'e')
1896 break;
1897 Mnemonic = "jb"; // "jnae"
1898 return;
1899 case 'b': // 1 string to match.
1900 if (Mnemonic[3] != 'e')
1901 break;
1902 Mnemonic = "ja"; // "jnbe"
1903 return;
1904 case 'g': // 1 string to match.
1905 if (Mnemonic[3] != 'e')
1906 break;
1907 Mnemonic = "jl"; // "jnge"
1908 return;
1909 case 'l': // 1 string to match.
1910 if (Mnemonic[3] != 'e')
1911 break;
1912 Mnemonic = "jg"; // "jnle"
1913 return;
1914 }
1915 break;
1916 case 'r': // 2 strings to match.
1917 if (memcmp(Mnemonic.data()+1, "ep", 2) != 0)
1918 break;
1919 switch (Mnemonic[3]) {
1920 default: break;
1921 case 'e': // 1 string to match.
1922 Mnemonic = "rep"; // "repe"
1923 return;
1924 case 'z': // 1 string to match.
1925 Mnemonic = "rep"; // "repz"
1926 return;
1927 }
1928 break;
1929 case 's': // 2 strings to match.
1930 if (memcmp(Mnemonic.data()+1, "et", 2) != 0)
1931 break;
1932 switch (Mnemonic[3]) {
1933 default: break;
1934 case 'c': // 1 string to match.
1935 Mnemonic = "setb"; // "setc"
1936 return;
1937 case 'z': // 1 string to match.
1938 Mnemonic = "sete"; // "setz"
1939 return;
1940 }
1941 break;
1942 }
1943 break;
1944 case 5: // 11 strings to match.
1945 switch (Mnemonic[0]) {
1946 default: break;
1947 case 'f': // 1 string to match.
1948 if (memcmp(Mnemonic.data()+1, "wait", 4) != 0)
1949 break;
1950 Mnemonic = "wait"; // "fwait"
1951 return;
1952 case 'l': // 1 string to match.
1953 if (memcmp(Mnemonic.data()+1, "oopz", 4) != 0)
1954 break;
1955 Mnemonic = "loope"; // "loopz"
1956 return;
1957 case 'r': // 1 string to match.
1958 if (memcmp(Mnemonic.data()+1, "epnz", 4) != 0)
1959 break;
1960 Mnemonic = "repne"; // "repnz"
1961 return;
1962 case 's': // 8 strings to match.
1963 if (memcmp(Mnemonic.data()+1, "et", 2) != 0)
1964 break;
1965 switch (Mnemonic[3]) {
1966 default: break;
1967 case 'n': // 6 strings to match.
1968 switch (Mnemonic[4]) {
1969 default: break;
1970 case 'a': // 1 string to match.
1971 Mnemonic = "setbe"; // "setna"
1972 return;
1973 case 'b': // 1 string to match.
1974 Mnemonic = "setae"; // "setnb"
1975 return;
1976 case 'c': // 1 string to match.
1977 Mnemonic = "setae"; // "setnc"
1978 return;
1979 case 'g': // 1 string to match.
1980 Mnemonic = "setle"; // "setng"
1981 return;
1982 case 'l': // 1 string to match.
1983 Mnemonic = "setge"; // "setnl"
1984 return;
1985 case 'z': // 1 string to match.
1986 Mnemonic = "setne"; // "setnz"
1987 return;
1988 }
1989 break;
1990 case 'p': // 2 strings to match.
1991 switch (Mnemonic[4]) {
1992 default: break;
1993 case 'e': // 1 string to match.
1994 Mnemonic = "setp"; // "setpe"
1995 return;
1996 case 'o': // 1 string to match.
1997 Mnemonic = "setnp"; // "setpo"
1998 return;
1999 }
2000 break;
2001 }
2002 break;
2003 }
2004 break;
2005 case 6: // 6 strings to match.
2006 switch (Mnemonic[0]) {
2007 default: break;
2008 case 'f': // 1 string to match.
2009 if (memcmp(Mnemonic.data()+1, "comip", 5) != 0)
2010 break;
2011 Mnemonic = "fcompi"; // "fcomip"
2012 return;
2013 case 'l': // 1 string to match.
2014 if (memcmp(Mnemonic.data()+1, "oopnz", 5) != 0)
2015 break;
2016 Mnemonic = "loopne"; // "loopnz"
2017 return;
2018 case 's': // 4 strings to match.
2019 if (memcmp(Mnemonic.data()+1, "etn", 3) != 0)
2020 break;
2021 switch (Mnemonic[4]) {
2022 default: break;
2023 case 'a': // 1 string to match.
2024 if (Mnemonic[5] != 'e')
2025 break;
2026 Mnemonic = "setb"; // "setnae"
2027 return;
2028 case 'b': // 1 string to match.
2029 if (Mnemonic[5] != 'e')
2030 break;
2031 Mnemonic = "seta"; // "setnbe"
2032 return;
2033 case 'g': // 1 string to match.
2034 if (Mnemonic[5] != 'e')
2035 break;
2036 Mnemonic = "setl"; // "setnge"
2037 return;
2038 case 'l': // 1 string to match.
2039 if (Mnemonic[5] != 'e')
2040 break;
2041 Mnemonic = "setg"; // "setnle"
2042 return;
2043 }
2044 break;
2045 }
2046 break;
2047 case 7: // 1 string to match.
2048 if (memcmp(Mnemonic.data()+0, "fucomip", 7) != 0)
2049 break;
2050 Mnemonic = "fucompi"; // "fucomip"
2051 return;
2052 }
2053}
2054
2055namespace {
2056enum OperatorConversionKind {
2057 CVT_Done,
2058 CVT_Reg,
2059 CVT_Tied,
2060 CVT_imm_95_10,
2061 CVT_95_addImmOperands,
2062 CVT_regAX,
2063 CVT_regEAX,
2064 CVT_regRAX,
2065 CVT_95_Reg,
2066 CVT_95_addMemOperands,
2067 CVT_95_addAbsMemOperands,
2068 CVT_95_addDstIdxOperands,
2069 CVT_95_addSrcIdxOperands,
2070 CVT_95_addGR32orGR64Operands,
2071 CVT_regST1,
2072 CVT_regST0,
2073 CVT_95_addMemOffsOperands,
2074 CVT_imm_95_17,
2075 CVT_imm_95_1,
2076 CVT_imm_95_16,
2077 CVT_imm_95_0,
2078 CVT_95_addAVX512RCOperands,
2079 CVT_NUM_CONVERTERS
2080};
2081
2082enum InstructionConversionKind {
2083 Convert_NoOperands,
2084 Convert__imm_95_10,
2085 Convert__Imm1_0,
2086 Convert__Imm1_1,
2087 Convert__regAX__Tie0__ImmSExti16i81_1,
2088 Convert__regEAX__Tie0__ImmSExti32i81_1,
2089 Convert__regRAX__Tie0__ImmSExti64i81_1,
2090 Convert__ImmSExti64i321_1,
2091 Convert__Reg1_0__Tie0__Reg1_1,
2092 Convert__Reg1_0__Tie0__ImmSExti16i81_1,
2093 Convert__Reg1_0__Tie0__Imm1_1,
2094 Convert__Reg1_0__Tie0__Mem165_1,
2095 Convert__Reg1_0__Tie0__ImmSExti32i81_1,
2096 Convert__Reg1_0__Tie0__Mem325_1,
2097 Convert__Reg1_0__Tie0__ImmSExti64i81_1,
2098 Convert__Reg1_0__Tie0__ImmSExti64i321_1,
2099 Convert__Reg1_0__Tie0__Mem645_1,
2100 Convert__Reg1_0__Tie0__Mem85_1,
2101 Convert__Mem165_0__Reg1_1,
2102 Convert__Mem165_0__ImmSExti16i81_1,
2103 Convert__Mem165_0__Imm1_1,
2104 Convert__Mem325_0__Reg1_1,
2105 Convert__Mem325_0__ImmSExti32i81_1,
2106 Convert__Mem325_0__Imm1_1,
2107 Convert__Mem645_0__Reg1_1,
2108 Convert__Mem645_0__ImmSExti64i81_1,
2109 Convert__Mem645_0__ImmSExti64i321_1,
2110 Convert__Mem85_0__Reg1_1,
2111 Convert__Mem85_0__Imm1_1,
2112 Convert__Reg1_1__Tie0__Reg1_0,
2113 Convert__Mem85_1__Reg1_0,
2114 Convert__Reg1_1__Tie0__Imm1_0,
2115 Convert__Mem85_1__Imm1_0,
2116 Convert__Reg1_1__Tie0__Mem85_0,
2117 Convert__Mem325_1__Reg1_0,
2118 Convert__regEAX__Tie0__ImmSExti32i81_0,
2119 Convert__Reg1_1__Tie0__ImmSExti32i81_0,
2120 Convert__Mem325_1__ImmSExti32i81_0,
2121 Convert__Mem325_1__Imm1_0,
2122 Convert__Reg1_1__Tie0__Mem325_0,
2123 Convert__Mem645_1__Reg1_0,
2124 Convert__regRAX__Tie0__ImmSExti64i81_0,
2125 Convert__Reg1_1__Tie0__ImmSExti64i81_0,
2126 Convert__Mem645_1__ImmSExti64i81_0,
2127 Convert__ImmSExti64i321_0,
2128 Convert__Reg1_1__Tie0__ImmSExti64i321_0,
2129 Convert__Mem645_1__ImmSExti64i321_0,
2130 Convert__Reg1_1__Tie0__Mem645_0,
2131 Convert__Mem165_1__Reg1_0,
2132 Convert__regAX__Tie0__ImmSExti16i81_0,
2133 Convert__Reg1_1__Tie0__ImmSExti16i81_0,
2134 Convert__Mem165_1__ImmSExti16i81_0,
2135 Convert__Mem165_1__Imm1_0,
2136 Convert__Reg1_1__Tie0__Mem165_0,
2137 Convert__Reg1_0__Tie0__Mem1285_1,
2138 Convert__Reg1_1__Tie0__Mem1285_0,
2139 Convert__Reg1_0__Reg1_1,
2140 Convert__Reg1_0__Mem325_1,
2141 Convert__Reg1_0__Mem645_1,
2142 Convert__Reg1_1__Reg1_0,
2143 Convert__Reg1_1__Mem325_0,
2144 Convert__Reg1_1__Mem645_0,
2145 Convert__Reg1_0__Mem1285_1,
2146 Convert__Reg1_1__Mem1285_0,
2147 Convert__Reg1_0__Reg1_1__ImmUnsignedi81_2,
2148 Convert__Reg1_0__Mem1285_1__ImmUnsignedi81_2,
2149 Convert__Reg1_2__Reg1_1__ImmUnsignedi81_0,
2150 Convert__Reg1_2__Mem1285_1__ImmUnsignedi81_0,
2151 Convert__Reg1_0__Reg1_1__Reg1_2,
2152 Convert__Reg1_0__Reg1_1__Mem325_2,
2153 Convert__Reg1_0__Reg1_1__Mem645_2,
2154 Convert__Reg1_2__Reg1_1__Reg1_0,
2155 Convert__Reg1_2__Reg1_1__Mem325_0,
2156 Convert__Reg1_2__Reg1_1__Mem645_0,
2157 Convert__Reg1_0__Reg1_1__Imm1_2,
2158 Convert__Reg1_0__Mem325_1__Reg1_2,
2159 Convert__Reg1_0__Mem325_1__Imm1_2,
2160 Convert__Reg1_0__Reg1_1__ImmSExti64i321_2,
2161 Convert__Reg1_0__Mem645_1__Reg1_2,
2162 Convert__Reg1_0__Mem645_1__ImmSExti64i321_2,
2163 Convert__Reg1_2__Reg1_1__ImmSExti64i321_0,
2164 Convert__Reg1_2__Mem645_1__ImmSExti64i321_0,
2165 Convert__Reg1_2__Reg1_1__Imm1_0,
2166 Convert__Reg1_2__Mem325_1__Imm1_0,
2167 Convert__Reg1_2__Mem325_1__Reg1_0,
2168 Convert__Reg1_2__Mem645_1__Reg1_0,
2169 Convert__Reg1_0__Tie0__Reg1_1__ImmUnsignedi81_2,
2170 Convert__Reg1_0__Tie0__Mem1285_1__ImmUnsignedi81_2,
2171 Convert__Reg1_2__Tie0__Reg1_1__ImmUnsignedi81_0,
2172 Convert__Reg1_2__Tie0__Mem1285_1__ImmUnsignedi81_0,
2173 Convert__Reg1_2__Tie0__Reg1_1,
2174 Convert__Reg1_2__Tie0__Mem1285_1,
2175 Convert__Reg1_0__Mem5_1,
2176 Convert__Reg1_1__Mem5_0,
2177 Convert__Mem1285_1__Reg1_0,
2178 Convert__Mem1285_0__Reg1_1,
2179 Convert__Reg1_0__Mem165_1,
2180 Convert__Reg1_1__Mem165_0,
2181 Convert__Reg1_0__Tie0,
2182 Convert__Reg1_0__ImmSExti16i81_1,
2183 Convert__Reg1_0__ImmSExti32i81_1,
2184 Convert__Reg1_0__ImmSExti64i81_1,
2185 Convert__Reg1_1__ImmSExti32i81_0,
2186 Convert__Reg1_1__ImmSExti64i81_0,
2187 Convert__Reg1_1__ImmSExti16i81_0,
2188 Convert__Reg1_0,
2189 Convert__AbsMem1_0,
2190 Convert__Mem165_0,
2191 Convert__Mem325_0,
2192 Convert__Mem645_0,
2193 Convert__Mem5_0,
2194 Convert__Mem165_1,
2195 Convert__Mem325_1,
2196 Convert__Mem645_1,
2197 Convert__Imm1_1__Imm1_0,
2198 Convert__Reg1_1,
2199 Convert__Mem85_0,
2200 Convert__Reg1_0__Tie0__Reg1_0,
2201 Convert__regAX__ImmSExti16i81_1,
2202 Convert__regEAX__ImmSExti32i81_1,
2203 Convert__regRAX__ImmSExti64i81_1,
2204 Convert__Reg1_0__Imm1_1,
2205 Convert__Reg1_0__ImmSExti64i321_1,
2206 Convert__Reg1_0__Mem85_1,
2207 Convert__Reg1_3__Tie0__Reg1_2__Imm1_0,
2208 Convert__Reg1_2__Tie0__Reg1_3__Imm1_0,
2209 Convert__Reg1_2__Tie0__Mem1285_3__Imm1_0,
2210 Convert__Reg1_3__Tie0__Mem1285_2__Imm1_0,
2211 Convert__Reg1_2__Tie0__Mem645_3__Imm1_0,
2212 Convert__Reg1_3__Tie0__Mem645_2__Imm1_0,
2213 Convert__Reg1_2__Tie0__Mem325_3__Imm1_0,
2214 Convert__Reg1_3__Tie0__Mem325_2__Imm1_0,
2215 Convert__Reg1_1__Imm1_0,
2216 Convert__Reg1_1__Mem85_0,
2217 Convert__regEAX__ImmSExti32i81_0,
2218 Convert__regRAX__ImmSExti64i81_0,
2219 Convert__Reg1_1__ImmSExti64i321_0,
2220 Convert__DstIdx161_0__SrcIdx162_1,
2221 Convert__DstIdx321_0__SrcIdx322_1,
2222 Convert__DstIdx641_0__SrcIdx642_1,
2223 Convert__DstIdx81_0__SrcIdx82_1,
2224 Convert__DstIdx161_1__SrcIdx162_0,
2225 Convert__DstIdx321_1__SrcIdx322_0,
2226 Convert__DstIdx641_1__SrcIdx642_0,
2227 Convert__DstIdx81_1__SrcIdx82_0,
2228 Convert__Reg1_0__Tie0__Mem645_1__ImmUnsignedi81_2,
2229 Convert__Reg1_2__Tie0__Mem645_1__ImmUnsignedi81_0,
2230 Convert__Reg1_0__Tie0__Mem325_1__ImmUnsignedi81_2,
2231 Convert__Reg1_2__Tie0__Mem325_1__ImmUnsignedi81_0,
2232 Convert__regAX__ImmSExti16i81_0,
2233 Convert__Mem1285_0,
2234 Convert__Mem85_1,
2235 Convert__Imm1_0__Imm1_1,
2236 Convert__GR32orGR641_2__Reg1_1__ImmUnsignedi81_0,
2237 Convert__Mem325_2__Reg1_1__ImmUnsignedi81_0,
2238 Convert__GR32orGR641_0__Reg1_1__ImmUnsignedi81_2,
2239 Convert__Mem325_0__Reg1_1__ImmUnsignedi81_2,
2240 Convert__Reg1_0__Tie0__ImmUnsignedi81_1__ImmUnsignedi81_2,
2241 Convert__Reg1_2__Tie0__ImmUnsignedi81_1__ImmUnsignedi81_0,
2242 Convert__regST1,
2243 Convert__regST0,
2244 Convert__Mem805_0,
2245 Convert__Reg1_0__Reg1_0__ImmSExti16i81_1,
2246 Convert__Reg1_0__Reg1_0__Imm1_1,
2247 Convert__Reg1_0__Reg1_0__ImmSExti32i81_1,
2248 Convert__Reg1_0__Reg1_0__ImmSExti64i81_1,
2249 Convert__Reg1_0__Reg1_0__ImmSExti64i321_1,
2250 Convert__Reg1_0__Reg1_1__ImmSExti16i81_2,
2251 Convert__Reg1_0__Mem165_1__ImmSExti16i81_2,
2252 Convert__Reg1_0__Mem165_1__Imm1_2,
2253 Convert__Reg1_0__Reg1_1__ImmSExti32i81_2,
2254 Convert__Reg1_0__Mem325_1__ImmSExti32i81_2,
2255 Convert__Reg1_0__Reg1_1__ImmSExti64i81_2,
2256 Convert__Reg1_0__Mem645_1__ImmSExti64i81_2,
2257 Convert__Reg1_1__Reg1_1__ImmSExti32i81_0,
2258 Convert__Reg1_1__Reg1_1__Imm1_0,
2259 Convert__Reg1_2__Reg1_1__ImmSExti32i81_0,
2260 Convert__Reg1_2__Mem325_1__ImmSExti32i81_0,
2261 Convert__Reg1_1__Reg1_1__ImmSExti64i81_0,
2262 Convert__Reg1_1__Reg1_1__ImmSExti64i321_0,
2263 Convert__Reg1_2__Reg1_1__ImmSExti64i81_0,
2264 Convert__Reg1_2__Mem645_1__ImmSExti64i81_0,
2265 Convert__Reg1_1__Reg1_1__ImmSExti16i81_0,
2266 Convert__Reg1_2__Reg1_1__ImmSExti16i81_0,
2267 Convert__Reg1_2__Mem165_1__ImmSExti16i81_0,
2268 Convert__Reg1_2__Mem165_1__Imm1_0,
2269 Convert__ImmUnsignedi81_1,
2270 Convert__ImmUnsignedi81_0,
2271 Convert__DstIdx161_1,
2272 Convert__DstIdx321_1,
2273 Convert__DstIdx81_1,
2274 Convert__DstIdx161_0,
2275 Convert__DstIdx321_0,
2276 Convert__DstIdx81_0,
2277 Convert__Reg1_0__Tie0__Reg1_1__ImmUnsignedi81_2__ImmUnsignedi81_3,
2278 Convert__Reg1_3__Tie0__Reg1_2__ImmUnsignedi81_1__ImmUnsignedi81_0,
2279 Convert__Mem5_1,
2280 Convert__SrcIdx162_0,
2281 Convert__SrcIdx322_0,
2282 Convert__SrcIdx642_0,
2283 Convert__SrcIdx82_0,
2284 Convert__SrcIdx82_1,
2285 Convert__SrcIdx162_1,
2286 Convert__SrcIdx322_1,
2287 Convert__SrcIdx642_1,
2288 Convert__MemOffs16_82_1,
2289 Convert__MemOffs32_82_1,
2290 Convert__MemOffs16_162_1,
2291 Convert__MemOffs32_162_1,
2292 Convert__MemOffs16_322_1,
2293 Convert__MemOffs32_322_1,
2294 Convert__MemOffs32_642_1,
2295 Convert__MemOffs16_162_0,
2296 Convert__MemOffs16_322_0,
2297 Convert__MemOffs16_82_0,
2298 Convert__MemOffs32_162_0,
2299 Convert__MemOffs32_322_0,
2300 Convert__MemOffs32_642_0,
2301 Convert__MemOffs32_82_0,
2302 Convert__MemOffs64_82_1,
2303 Convert__MemOffs64_162_1,
2304 Convert__MemOffs64_322_1,
2305 Convert__MemOffs64_642_1,
2306 Convert__MemOffs64_162_0,
2307 Convert__MemOffs64_322_0,
2308 Convert__MemOffs64_642_0,
2309 Convert__MemOffs64_82_0,
2310 Convert__GR32orGR641_1__Reg1_0,
2311 Convert__GR32orGR641_0__Reg1_1,
2312 Convert__Reg1_1__Tie0__Reg1_0__imm_95_17,
2313 Convert__Reg1_0__Tie0__Reg1_1__imm_95_17,
2314 Convert__Reg1_0__Tie0__Mem1285_1__imm_95_17,
2315 Convert__Reg1_1__Tie0__Mem1285_0__imm_95_17,
2316 Convert__Reg1_1__Tie0__Reg1_0__imm_95_1,
2317 Convert__Reg1_0__Tie0__Reg1_1__imm_95_1,
2318 Convert__Reg1_0__Tie0__Mem1285_1__imm_95_1,
2319 Convert__Reg1_1__Tie0__Mem1285_0__imm_95_1,
2320 Convert__Reg1_1__Tie0__Reg1_0__imm_95_16,
2321 Convert__Reg1_0__Tie0__Reg1_1__imm_95_16,
2322 Convert__Reg1_0__Tie0__Mem1285_1__imm_95_16,
2323 Convert__Reg1_1__Tie0__Mem1285_0__imm_95_16,
2324 Convert__Reg1_1__Tie0__Reg1_0__imm_95_0,
2325 Convert__Reg1_0__Tie0__Reg1_1__imm_95_0,
2326 Convert__Reg1_0__Tie0__Mem1285_1__imm_95_0,
2327 Convert__Reg1_1__Tie0__Mem1285_0__imm_95_0,
2328 Convert__Mem85_2__Reg1_1__ImmUnsignedi81_0,
2329 Convert__Mem85_0__Reg1_1__ImmUnsignedi81_2,
2330 Convert__Mem645_2__Reg1_1__ImmUnsignedi81_0,
2331 Convert__Mem645_0__Reg1_1__ImmUnsignedi81_2,
2332 Convert__Mem165_2__Reg1_1__ImmUnsignedi81_0,
2333 Convert__Mem165_0__Reg1_1__ImmUnsignedi81_2,
2334 Convert__Reg1_0__Tie0__GR32orGR641_1__ImmUnsignedi81_2,
2335 Convert__Reg1_0__Tie0__Mem85_1__ImmUnsignedi81_2,
2336 Convert__Reg1_2__Tie0__GR32orGR641_1__ImmUnsignedi81_0,
2337 Convert__Reg1_2__Tie0__Mem85_1__ImmUnsignedi81_0,
2338 Convert__Reg1_0__Tie0__Mem165_1__ImmUnsignedi81_2,
2339 Convert__Reg1_2__Tie0__Mem165_1__ImmUnsignedi81_0,
2340 Convert__Reg1_0__Mem645_1__ImmUnsignedi81_2,
2341 Convert__Reg1_2__Mem645_1__ImmUnsignedi81_0,
2342 Convert__Reg1_0__Tie0__ImmUnsignedi81_1,
2343 Convert__Reg1_1__Tie0__ImmUnsignedi81_0,
2344 Convert__ImmSExti64i81_0,
2345 Convert__ImmSExti16i81_0,
2346 Convert__ImmSExti32i81_0,
2347 Convert__Mem165_0__ImmUnsignedi81_1,
2348 Convert__Mem325_0__ImmUnsignedi81_1,
2349 Convert__Mem645_0__ImmUnsignedi81_1,
2350 Convert__Mem85_0__ImmUnsignedi81_1,
2351 Convert__Reg1_1__Tie0,
2352 Convert__Mem85_1__ImmUnsignedi81_0,
2353 Convert__Mem325_1__ImmUnsignedi81_0,
2354 Convert__Mem645_1__ImmUnsignedi81_0,
2355 Convert__Mem165_1__ImmUnsignedi81_0,
2356 Convert__Reg1_0__Mem325_1__ImmUnsignedi81_2,
2357 Convert__Reg1_2__Mem325_1__ImmUnsignedi81_0,
2358 Convert__DstIdx641_0,
2359 Convert__DstIdx641_1,
2360 Convert__Mem325_2__Reg1_1,
2361 Convert__Mem645_2__Reg1_1,
2362 Convert__Mem165_2__Reg1_1,
2363 Convert__Reg1_0__Reg1_1__Mem1285_2,
2364 Convert__Reg1_0__Reg1_1__Mem2565_2,
2365 Convert__Reg1_0__Reg1_1__Mem5125_2,
2366 Convert__Reg1_2__Reg1_1__Mem1285_0,
2367 Convert__Reg1_2__Reg1_1__Mem2565_0,
2368 Convert__Reg1_2__Reg1_1__Mem5125_0,
2369 Convert__Reg1_0__Reg1_1__Reg1_2__AVX512RC1_3,
2370 Convert__Reg1_3__Reg1_2__Reg1_1__AVX512RC1_0,
2371 Convert__Reg1_3__Reg1_2__Mem645_0,
2372 Convert__Reg1_0__Tie0__Reg1_2__Reg1_4__Reg1_5,
2373 Convert__Reg1_0__Tie0__Reg1_2__Reg1_4__Mem1285_5,
2374 Convert__Reg1_2__Tie0__Reg1_4__Reg1_1__Reg1_0,
2375 Convert__Reg1_0__Tie0__Reg1_2__Reg1_4__Mem2565_5,
2376 Convert__Reg1_0__Tie0__Reg1_2__Reg1_4__Mem5125_5,
2377 Convert__Reg1_2__Tie0__Reg1_4__Reg1_1__Mem1285_0,
2378 Convert__Reg1_2__Tie0__Reg1_4__Reg1_1__Mem2565_0,
2379 Convert__Reg1_2__Tie0__Reg1_4__Reg1_1__Mem5125_0,
2380 Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6,
2381 Convert__Reg1_0__Reg1_2__Reg1_5__Mem1285_6,
2382 Convert__Reg1_0__Tie0__Reg1_2__Reg1_4__Mem645_5,
2383 Convert__Reg1_2__Reg1_4__Reg1_1__Reg1_0,
2384 Convert__Reg1_0__Reg1_2__Reg1_5__Mem2565_6,
2385 Convert__Reg1_0__Reg1_2__Reg1_5__Mem5125_6,
2386 Convert__Reg1_0__Tie0__Reg1_2__Reg1_4__Reg1_5__AVX512RC1_6,
2387 Convert__Reg1_3__Tie0__Reg1_5__Reg1_2__Reg1_1__AVX512RC1_0,
2388 Convert__Reg1_2__Reg1_4__Reg1_1__Mem1285_0,
2389 Convert__Reg1_2__Reg1_4__Reg1_1__Mem2565_0,
2390 Convert__Reg1_2__Reg1_4__Reg1_1__Mem5125_0,
2391 Convert__Reg1_3__Tie0__Reg1_5__Reg1_2__Mem645_0,
2392 Convert__Reg1_0__Reg1_2__Reg1_5__Mem645_6,
2393 Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6__AVX512RC1_7,
2394 Convert__Reg1_3__Reg1_5__Reg1_2__Reg1_1__AVX512RC1_0,
2395 Convert__Reg1_3__Reg1_5__Reg1_2__Mem645_0,
2396 Convert__Reg1_3__Reg1_2__Mem325_0,
2397 Convert__Reg1_0__Tie0__Reg1_2__Reg1_4__Mem325_5,
2398 Convert__Reg1_3__Tie0__Reg1_5__Reg1_2__Mem325_0,
2399 Convert__Reg1_0__Reg1_2__Reg1_5__Mem325_6,
2400 Convert__Reg1_3__Reg1_5__Reg1_2__Mem325_0,
2401 Convert__Reg1_2__Tie0__Reg1_4__Reg1_1__Mem645_0,
2402 Convert__Reg1_2__Reg1_4__Reg1_1__Mem645_0,
2403 Convert__Reg1_2__Tie0__Reg1_4__Reg1_1__Mem325_0,
2404 Convert__Reg1_2__Reg1_4__Reg1_1__Mem325_0,
2405 Convert__Reg1_0__Reg1_1__Reg1_2__ImmUnsignedi81_3,
2406 Convert__Reg1_0__Reg1_1__Mem1285_2__ImmUnsignedi81_3,
2407 Convert__Reg1_0__Reg1_1__Mem2565_2__ImmUnsignedi81_3,
2408 Convert__Reg1_0__Reg1_1__Mem5125_2__ImmUnsignedi81_3,
2409 Convert__Reg1_3__Reg1_2__Reg1_1__ImmUnsignedi81_0,
2410 Convert__Reg1_3__Reg1_2__Mem1285_1__ImmUnsignedi81_0,
2411 Convert__Reg1_3__Reg1_2__Mem2565_1__ImmUnsignedi81_0,
2412 Convert__Reg1_3__Reg1_2__Mem5125_1__ImmUnsignedi81_0,
2413 Convert__Reg1_0__Reg1_1__Mem325_2__ImmUnsignedi81_4,
2414 Convert__Reg1_4__Reg1_3__Mem325_1__ImmUnsignedi81_0,
2415 Convert__Reg1_0__Tie0__Reg1_2__Reg1_4__Reg1_5__ImmUnsignedi81_6,
2416 Convert__Reg1_0__Tie0__Reg1_2__Reg1_4__Mem1285_5__ImmUnsignedi81_6,
2417 Convert__Reg1_0__Tie0__Reg1_2__Reg1_4__Mem2565_5__ImmUnsignedi81_6,
2418 Convert__Reg1_0__Tie0__Reg1_2__Reg1_4__Mem5125_5__ImmUnsignedi81_6,
2419 Convert__Reg1_3__Tie0__Reg1_5__Reg1_2__Reg1_1__ImmUnsignedi81_0,
2420 Convert__Reg1_3__Tie0__Reg1_5__Reg1_2__Mem1285_1__ImmUnsignedi81_0,
2421 Convert__Reg1_3__Tie0__Reg1_5__Reg1_2__Mem2565_1__ImmUnsignedi81_0,
2422 Convert__Reg1_3__Tie0__Reg1_5__Reg1_2__Mem5125_1__ImmUnsignedi81_0,
2423 Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6__ImmUnsignedi81_7,
2424 Convert__Reg1_0__Reg1_2__Reg1_5__Mem1285_6__ImmUnsignedi81_7,
2425 Convert__Reg1_0__Tie0__Reg1_2__Reg1_4__Mem325_5__ImmUnsignedi81_7,
2426 Convert__Reg1_0__Reg1_2__Reg1_5__Mem2565_6__ImmUnsignedi81_7,
2427 Convert__Reg1_0__Reg1_2__Reg1_5__Mem5125_6__ImmUnsignedi81_7,
2428 Convert__Reg1_3__Reg1_5__Reg1_2__Reg1_1__ImmUnsignedi81_0,
2429 Convert__Reg1_3__Reg1_5__Reg1_2__Mem1285_1__ImmUnsignedi81_0,
2430 Convert__Reg1_3__Reg1_5__Reg1_2__Mem2565_1__ImmUnsignedi81_0,
2431 Convert__Reg1_4__Tie0__Reg1_6__Reg1_3__Mem325_1__ImmUnsignedi81_0,
2432 Convert__Reg1_3__Reg1_5__Reg1_2__Mem5125_1__ImmUnsignedi81_0,
2433 Convert__Reg1_0__Reg1_2__Reg1_5__Mem325_6__ImmUnsignedi81_8,
2434 Convert__Reg1_4__Reg1_6__Reg1_3__Mem325_1__ImmUnsignedi81_0,
2435 Convert__Reg1_0__Reg1_1__Mem645_2__ImmUnsignedi81_4,
2436 Convert__Reg1_4__Reg1_3__Mem645_1__ImmUnsignedi81_0,
2437 Convert__Reg1_0__Tie0__Reg1_2__Reg1_4__Mem645_5__ImmUnsignedi81_7,
2438 Convert__Reg1_4__Tie0__Reg1_6__Reg1_3__Mem645_1__ImmUnsignedi81_0,
2439 Convert__Reg1_0__Reg1_2__Reg1_5__Mem645_6__ImmUnsignedi81_8,
2440 Convert__Reg1_4__Reg1_6__Reg1_3__Mem645_1__ImmUnsignedi81_0,
2441 Convert__Reg1_0__Reg1_2__Reg1_4__Reg1_5,
2442 Convert__Reg1_0__Reg1_2__Reg1_4__Mem1285_5,
2443 Convert__Reg1_0__Reg1_2__Reg1_4__Mem2565_5,
2444 Convert__Reg1_0__Reg1_2__Reg1_4__Mem5125_5,
2445 Convert__Reg1_0__Reg1_2__Reg1_4__Mem645_5,
2446 Convert__Reg1_0__Reg1_2__Reg1_4__Mem325_5,
2447 Convert__Reg1_3__Reg1_2__Reg1_1__Reg1_0,
2448 Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3,
2449 Convert__Reg1_0__Reg1_1__Mem1285_2__Reg1_3,
2450 Convert__Reg1_3__Reg1_2__Mem1285_1__Reg1_0,
2451 Convert__Reg1_0__Reg1_1__Mem2565_2__Reg1_3,
2452 Convert__Reg1_3__Reg1_2__Mem2565_1__Reg1_0,
2453 Convert__Reg1_1__Tie0__Reg1_3__Reg1_0,
2454 Convert__Reg1_0__Tie0__Reg1_2__Reg1_4,
2455 Convert__Reg1_0__Tie0__Reg1_2__Mem645_4,
2456 Convert__Reg1_1__Tie0__Reg1_3__Mem645_0,
2457 Convert__Reg1_1__Reg1_3__Reg1_0,
2458 Convert__Reg1_0__Reg1_2__Reg1_5,
2459 Convert__Reg1_0__Reg1_2__Mem645_5,
2460 Convert__Reg1_1__Reg1_3__Mem645_0,
2461 Convert__Reg1_0__Tie0__Reg1_2__Mem1285_4,
2462 Convert__Reg1_1__Tie0__Reg1_3__Mem1285_0,
2463 Convert__Reg1_0__Reg1_2__Mem1285_5,
2464 Convert__Reg1_1__Reg1_3__Mem1285_0,
2465 Convert__Reg1_0__Mem2565_1,
2466 Convert__Reg1_1__Mem2565_0,
2467 Convert__Reg1_0__Tie0__Reg1_2__Mem2565_4,
2468 Convert__Reg1_1__Tie0__Reg1_3__Mem2565_0,
2469 Convert__Reg1_0__Reg1_2__Mem2565_5,
2470 Convert__Reg1_1__Reg1_3__Mem2565_0,
2471 Convert__Reg1_0__Tie0__Reg1_2__Mem325_4,
2472 Convert__Reg1_1__Tie0__Reg1_3__Mem325_0,
2473 Convert__Reg1_0__Reg1_2__Mem325_5,
2474 Convert__Reg1_1__Reg1_3__Mem325_0,
2475 Convert__Reg1_2__Reg1_3__Reg1_4__Imm1_0,
2476 Convert__Reg1_2__Reg1_3__Mem1285_4__Imm1_0,
2477 Convert__Reg1_2__Reg1_3__Mem2565_4__Imm1_0,
2478 Convert__Reg1_2__Reg1_3__Mem5125_4__Imm1_0,
2479 Convert__Reg1_4__Reg1_3__Reg1_2__Imm1_0,
2480 Convert__Reg1_4__Reg1_3__Mem1285_2__Imm1_0,
2481 Convert__Reg1_4__Reg1_3__Mem2565_2__Imm1_0,
2482 Convert__Reg1_4__Reg1_3__Mem5125_2__Imm1_0,
2483 Convert__Reg1_2__Reg1_3__Mem645_4__Imm1_0,
2484 Convert__Reg1_4__Reg1_3__Mem645_2__Imm1_0,
2485 Convert__Reg1_2__Reg1_3__Mem325_4__Imm1_0,
2486 Convert__Reg1_4__Reg1_3__Mem325_2__Imm1_0,
2487 Convert__Reg1_5__Reg1_4__Reg1_3__Imm1_0,
2488 Convert__Reg1_5__Reg1_4__Mem645_2__Imm1_0,
2489 Convert__Reg1_5__Reg1_4__Mem325_2__Imm1_0,
2490 Convert__Reg1_2__Reg1_4__Reg1_6__Reg1_7__Imm1_0,
2491 Convert__Reg1_2__Reg1_4__Reg1_6__Mem1285_7__Imm1_0,
2492 Convert__Reg1_2__Reg1_4__Reg1_6__Mem2565_7__Imm1_0,
2493 Convert__Reg1_2__Reg1_4__Reg1_6__Mem5125_7__Imm1_0,
2494 Convert__Reg1_4__Reg1_6__Reg1_3__Reg1_2__Imm1_0,
2495 Convert__Reg1_4__Reg1_6__Reg1_3__Mem1285_2__Imm1_0,
2496 Convert__Reg1_4__Reg1_6__Reg1_3__Mem2565_2__Imm1_0,
2497 Convert__Reg1_4__Reg1_6__Reg1_3__Mem5125_2__Imm1_0,
2498 Convert__Reg1_2__Reg1_4__Reg1_6__Mem645_7__Imm1_0,
2499 Convert__Reg1_4__Reg1_6__Reg1_3__Mem645_2__Imm1_0,
2500 Convert__Reg1_2__Reg1_4__Reg1_6__Mem325_7__Imm1_0,
2501 Convert__Reg1_4__Reg1_6__Reg1_3__Mem325_2__Imm1_0,
2502 Convert__Reg1_5__Reg1_7__Reg1_4__Reg1_3__Imm1_0,
2503 Convert__Reg1_5__Reg1_7__Reg1_4__Mem645_2__Imm1_0,
2504 Convert__Reg1_5__Reg1_7__Reg1_4__Mem325_2__Imm1_0,
2505 Convert__Reg1_0__Reg1_1__Reg1_2__ImmUnsignedi81_4,
2506 Convert__Reg1_4__Reg1_3__Reg1_2__ImmUnsignedi81_0,
2507 Convert__Reg1_0__Reg1_2__Reg1_4__Reg1_5__ImmUnsignedi81_6,
2508 Convert__Reg1_0__Reg1_2__Reg1_4__Mem1285_5__ImmUnsignedi81_6,
2509 Convert__Reg1_0__Reg1_2__Reg1_4__Mem2565_5__ImmUnsignedi81_6,
2510 Convert__Reg1_0__Reg1_2__Reg1_4__Mem5125_5__ImmUnsignedi81_6,
2511 Convert__Reg1_0__Reg1_2__Reg1_4__Mem645_5__ImmUnsignedi81_7,
2512 Convert__Reg1_0__Reg1_2__Reg1_4__Reg1_5__ImmUnsignedi81_7,
2513 Convert__Reg1_4__Reg1_6__Reg1_3__Reg1_2__ImmUnsignedi81_0,
2514 Convert__Reg1_0__Reg1_2__Reg1_4__Mem325_5__ImmUnsignedi81_7,
2515 Convert__Reg1_0__Reg1_1__Mem645_2__ImmUnsignedi81_3,
2516 Convert__Reg1_3__Reg1_2__Mem645_1__ImmUnsignedi81_0,
2517 Convert__Reg1_0__Reg1_2__Reg1_4__Mem645_5__ImmUnsignedi81_6,
2518 Convert__Reg1_3__Reg1_5__Reg1_2__Mem645_1__ImmUnsignedi81_0,
2519 Convert__Reg1_0__Reg1_1__Mem325_2__ImmUnsignedi81_3,
2520 Convert__Reg1_3__Reg1_2__Mem325_1__ImmUnsignedi81_0,
2521 Convert__Reg1_0__Reg1_2__Reg1_4__Mem325_5__ImmUnsignedi81_6,
2522 Convert__Reg1_3__Reg1_5__Reg1_2__Mem325_1__ImmUnsignedi81_0,
2523 Convert__Reg1_2__Reg1_1,
2524 Convert__Mem2565_1__Reg1_0,
2525 Convert__Mem5125_1__Reg1_0,
2526 Convert__Mem2565_0__Reg1_1,
2527 Convert__Mem5125_0__Reg1_1,
2528 Convert__Mem1285_1__Reg1_3__Reg1_0,
2529 Convert__Mem2565_1__Reg1_3__Reg1_0,
2530 Convert__Mem5125_1__Reg1_3__Reg1_0,
2531 Convert__Mem1285_0__Reg1_2__Reg1_4,
2532 Convert__Mem2565_0__Reg1_2__Reg1_4,
2533 Convert__Mem5125_0__Reg1_2__Reg1_4,
2534 Convert__Reg1_2__Mem325_0,
2535 Convert__Reg1_2__Tie0__Reg1_4__Mem325_0,
2536 Convert__Reg1_2__Reg1_4__Mem325_0,
2537 Convert__Reg1_0__Mem5125_1,
2538 Convert__Reg1_1__Mem5125_0,
2539 Convert__Reg1_0__Reg1_1__AVX512RC1_2,
2540 Convert__Reg1_2__Reg1_1__AVX512RC1_0,
2541 Convert__Reg1_0__Tie0__Reg1_2__Mem5125_4,
2542 Convert__Reg1_1__Tie0__Reg1_3__Mem5125_0,
2543 Convert__Reg1_0__Reg1_2__Mem5125_5,
2544 Convert__Reg1_0__Tie0__Reg1_2__Reg1_4__AVX512RC1_5,
2545 Convert__Reg1_2__Tie0__Reg1_4__Reg1_1__AVX512RC1_0,
2546 Convert__Reg1_1__Reg1_3__Mem5125_0,
2547 Convert__Reg1_0__Reg1_2__Reg1_5__AVX512RC1_6,
2548 Convert__Reg1_2__Reg1_4__Reg1_1__AVX512RC1_0,
2549 Convert__Reg1_2__Mem645_0,
2550 Convert__Reg1_2__Tie0__Reg1_4__Mem645_0,
2551 Convert__Reg1_2__Reg1_4__Mem645_0,
2552 Convert__Reg1_2__Tie0__Reg1_4__Reg1_1,
2553 Convert__Reg1_2__Reg1_4__Reg1_1,
2554 Convert__Mem1285_2__Reg1_1__ImmUnsignedi81_0,
2555 Convert__Mem2565_2__Reg1_1__ImmUnsignedi81_0,
2556 Convert__Mem1285_0__Reg1_1__ImmUnsignedi81_2,
2557 Convert__Mem2565_0__Reg1_1__ImmUnsignedi81_2,
2558 Convert__Reg1_0__Reg1_1__ImmUnsignedi81_3,
2559 Convert__Reg1_3__Reg1_2__ImmUnsignedi81_0,
2560 Convert__Reg1_0__Tie0__Reg1_2__Reg1_4__ImmUnsignedi81_5,
2561 Convert__Reg1_2__Tie0__Reg1_4__Reg1_1__ImmUnsignedi81_0,
2562 Convert__Mem645_2__Reg1_4__Reg1_1__ImmUnsignedi81_0,
2563 Convert__Mem1285_2__Reg1_4__Reg1_1__ImmUnsignedi81_0,
2564 Convert__Mem2565_2__Reg1_4__Reg1_1__ImmUnsignedi81_0,
2565 Convert__Mem1285_0__Reg1_2__Reg1_4__ImmUnsignedi81_5,
2566 Convert__Mem2565_0__Reg1_2__Reg1_4__ImmUnsignedi81_5,
2567 Convert__Mem645_0__Reg1_2__Reg1_4__ImmUnsignedi81_5,
2568 Convert__Reg1_0__Reg1_2__Reg1_5__ImmUnsignedi81_6,
2569 Convert__Reg1_0__Tie0__Reg1_2__Reg1_4__ImmUnsignedi81_6,
2570 Convert__Reg1_3__Tie0__Reg1_5__Reg1_2__ImmUnsignedi81_0,
2571 Convert__Reg1_2__Reg1_4__Reg1_1__ImmUnsignedi81_0,
2572 Convert__Reg1_0__Reg1_2__Reg1_5__ImmUnsignedi81_7,
2573 Convert__Reg1_3__Reg1_5__Reg1_2__ImmUnsignedi81_0,
2574 Convert__Reg1_0__Reg1_1__Reg1_3__AVX512RC1_2,
2575 Convert__Reg1_3__Reg1_2__Reg1_0__AVX512RC1_1,
2576 Convert__Reg1_3__Reg1_2__Reg1_1,
2577 Convert__Reg1_3__Tie0__Reg1_5__Reg1_2__Reg1_1,
2578 Convert__Reg1_3__Reg1_5__Reg1_2__Reg1_1,
2579 Convert__Reg1_0__Tie0__Reg1_1__Reg1_2__ImmUnsignedi81_3,
2580 Convert__Reg1_0__Tie0__Reg1_1__Mem1285_2__ImmUnsignedi81_3,
2581 Convert__Reg1_0__Tie0__Reg1_1__Mem2565_2__ImmUnsignedi81_3,
2582 Convert__Reg1_0__Tie0__Reg1_1__Mem5125_2__ImmUnsignedi81_3,
2583 Convert__Reg1_3__Tie0__Reg1_2__Reg1_1__ImmUnsignedi81_0,
2584 Convert__Reg1_3__Tie0__Reg1_2__Mem1285_1__ImmUnsignedi81_0,
2585 Convert__Reg1_3__Tie0__Reg1_2__Mem2565_1__ImmUnsignedi81_0,
2586 Convert__Reg1_3__Tie0__Reg1_2__Mem5125_1__ImmUnsignedi81_0,
2587 Convert__Reg1_0__Tie0__Reg1_1__Mem645_2__ImmUnsignedi81_4,
2588 Convert__Reg1_0__Tie0__Reg1_1__Reg1_2__ImmUnsignedi81_4,
2589 Convert__Reg1_4__Tie0__Reg1_3__Reg1_2__ImmUnsignedi81_0,
2590 Convert__Reg1_4__Tie0__Reg1_3__Mem645_1__ImmUnsignedi81_0,
2591 Convert__Reg1_0__Tie0__Reg1_2__Reg1_5__Reg1_6__ImmUnsignedi81_7,
2592 Convert__Reg1_0__Tie0__Reg1_2__Reg1_5__Mem1285_6__ImmUnsignedi81_7,
2593 Convert__Reg1_0__Tie0__Reg1_2__Reg1_5__Mem2565_6__ImmUnsignedi81_7,
2594 Convert__Reg1_0__Tie0__Reg1_2__Reg1_5__Mem5125_6__ImmUnsignedi81_7,
2595 Convert__Reg1_0__Tie0__Reg1_2__Reg1_4__Reg1_5__ImmUnsignedi81_7,
2596 Convert__Reg1_4__Tie0__Reg1_6__Reg1_3__Reg1_2__ImmUnsignedi81_0,
2597 Convert__Reg1_0__Tie0__Reg1_2__Reg1_5__Mem645_6__ImmUnsignedi81_8,
2598 Convert__Reg1_0__Tie0__Reg1_2__Reg1_5__Reg1_6__ImmUnsignedi81_8,
2599 Convert__Reg1_0__Tie0__Reg1_1__Mem325_2__ImmUnsignedi81_4,
2600 Convert__Reg1_4__Tie0__Reg1_3__Mem325_1__ImmUnsignedi81_0,
2601 Convert__Reg1_0__Tie0__Reg1_2__Reg1_5__Mem325_6__ImmUnsignedi81_8,
2602 Convert__Reg1_0__Tie0__Reg1_1__Mem645_2__ImmUnsignedi81_3,
2603 Convert__Reg1_3__Tie0__Reg1_2__Mem645_1__ImmUnsignedi81_0,
2604 Convert__Reg1_0__Tie0__Reg1_2__Reg1_4__Mem645_5__ImmUnsignedi81_6,
2605 Convert__Reg1_3__Tie0__Reg1_5__Reg1_2__Mem645_1__ImmUnsignedi81_0,
2606 Convert__Reg1_0__Tie0__Reg1_2__Reg1_5__Mem645_6__ImmUnsignedi81_7,
2607 Convert__Reg1_0__Tie0__Reg1_1__Mem325_2__ImmUnsignedi81_3,
2608 Convert__Reg1_3__Tie0__Reg1_2__Mem325_1__ImmUnsignedi81_0,
2609 Convert__Reg1_0__Tie0__Reg1_2__Reg1_4__Mem325_5__ImmUnsignedi81_6,
2610 Convert__Reg1_3__Tie0__Reg1_5__Reg1_2__Mem325_1__ImmUnsignedi81_0,
2611 Convert__Reg1_0__Tie0__Reg1_2__Reg1_5__Mem325_6__ImmUnsignedi81_7,
2612 Convert__Reg1_2__Tie0__Reg1_1__Reg1_0,
2613 Convert__Reg1_0__Tie0__Reg1_1__Reg1_2,
2614 Convert__Reg1_0__Tie0__Reg1_1__Mem1285_2,
2615 Convert__Reg1_0__Tie0__Reg1_1__Mem2565_2,
2616 Convert__Reg1_0__Tie0__Reg1_1__Mem5125_2,
2617 Convert__Reg1_2__Tie0__Reg1_1__Mem1285_0,
2618 Convert__Reg1_2__Tie0__Reg1_1__Mem2565_0,
2619 Convert__Reg1_2__Tie0__Reg1_1__Mem5125_0,
2620 Convert__Reg1_0__Tie0__Reg1_1__Mem645_2,
2621 Convert__Reg1_0__Tie0__Reg1_1__Reg1_2__AVX512RC1_3,
2622 Convert__Reg1_3__Tie0__Reg1_2__Reg1_1__AVX512RC1_0,
2623 Convert__Reg1_3__Tie0__Reg1_2__Mem645_0,
2624 Convert__Reg1_0__Tie0__Reg1_2__Reg1_5__Reg1_6,
2625 Convert__Reg1_0__Tie0__Reg1_2__Reg1_5__Mem1285_6,
2626 Convert__Reg1_0__Tie0__Reg1_2__Reg1_5__Mem2565_6,
2627 Convert__Reg1_0__Tie0__Reg1_2__Reg1_5__Mem5125_6,
2628 Convert__Reg1_0__Tie0__Reg1_2__Reg1_5__Mem645_6,
2629 Convert__Reg1_0__Tie0__Reg1_2__Reg1_5__Reg1_6__AVX512RC1_7,
2630 Convert__Reg1_0__Tie0__Reg1_1__Mem325_2,
2631 Convert__Reg1_3__Tie0__Reg1_2__Mem325_0,
2632 Convert__Reg1_0__Tie0__Reg1_2__Reg1_5__Mem325_6,
2633 Convert__Reg1_2__Tie0__Reg1_1__Mem645_0,
2634 Convert__Reg1_2__Tie0__Reg1_1__Mem325_0,
2635 Convert__Reg1_0__Reg1_1__Reg1_2__Mem1285_3,
2636 Convert__Reg1_0__Reg1_1__Reg1_2__Mem2565_3,
2637 Convert__Reg1_3__Reg1_2__Reg1_1__Mem1285_0,
2638 Convert__Reg1_3__Reg1_2__Reg1_1__Mem2565_0,
2639 Convert__Reg1_0__Reg1_1__Reg1_2__Mem645_3,
2640 Convert__Reg1_0__Reg1_1__Mem645_2__Reg1_3,
2641 Convert__Reg1_3__Reg1_2__Mem645_1__Reg1_0,
2642 Convert__Reg1_3__Reg1_2__Reg1_1__Mem645_0,
2643 Convert__Reg1_0__Reg1_1__Reg1_2__Mem325_3,
2644 Convert__Reg1_0__Reg1_1__Mem325_2__Reg1_3,
2645 Convert__Reg1_3__Reg1_2__Mem325_1__Reg1_0,
2646 Convert__Reg1_3__Reg1_2__Reg1_1__Mem325_0,
2647 Convert__Reg1_0__Mem2565_1__ImmUnsignedi81_2,
2648 Convert__Reg1_0__Mem5125_1__ImmUnsignedi81_2,
2649 Convert__Reg1_0__Mem645_1__ImmUnsignedi81_3,
2650 Convert__Reg1_0__Reg1_2__Reg1_4__ImmUnsignedi81_5,
2651 Convert__Reg1_0__Reg1_2__Mem1285_4__ImmUnsignedi81_5,
2652 Convert__Reg1_0__Reg1_2__Mem2565_4__ImmUnsignedi81_5,
2653 Convert__Reg1_0__Reg1_2__Mem5125_4__ImmUnsignedi81_5,
2654 Convert__Reg1_0__Reg1_2__Mem645_4__ImmUnsignedi81_6,
2655 Convert__Reg1_3__Mem645_1__ImmUnsignedi81_0,
2656 Convert__Reg1_3__Reg1_5__Mem645_1__ImmUnsignedi81_0,
2657 Convert__Reg1_2__Reg1_4__Mem1285_1__ImmUnsignedi81_0,
2658 Convert__Reg1_2__Mem2565_1__ImmUnsignedi81_0,
2659 Convert__Reg1_2__Reg1_4__Mem2565_1__ImmUnsignedi81_0,
2660 Convert__Reg1_2__Mem5125_1__ImmUnsignedi81_0,
2661 Convert__Reg1_2__Reg1_4__Mem5125_1__ImmUnsignedi81_0,
2662 Convert__Reg1_0__Mem325_1__ImmUnsignedi81_3,
2663 Convert__Reg1_0__Reg1_2__Mem325_4__ImmUnsignedi81_6,
2664 Convert__Reg1_3__Mem325_1__ImmUnsignedi81_0,
2665 Convert__Reg1_3__Reg1_5__Mem325_1__ImmUnsignedi81_0,
2666 Convert__Reg1_0__Reg1_2__Mem645_4__ImmUnsignedi81_5,
2667 Convert__Reg1_2__Reg1_4__Mem645_1__ImmUnsignedi81_0,
2668 Convert__Reg1_0__Reg1_2__Mem325_4__ImmUnsignedi81_5,
2669 Convert__Reg1_2__Reg1_4__Mem325_1__ImmUnsignedi81_0,
2670 Convert__Reg1_2__Reg1_0__Tie0__Mem128_RC1285_1__Tie1,
2671 Convert__Reg1_0__Reg1_2__Tie0__Mem128_RC1285_1__Tie1,
2672 Convert__Reg1_2__Reg1_0__Tie0__Mem256_RC1285_1__Tie1,
2673 Convert__Reg1_0__Reg1_2__Tie0__Mem256_RC1285_1__Tie1,
2674 Convert__Reg1_0__Reg1_2__Tie0__Tie1__Mem128_RC128X5_4,
2675 Convert__Reg1_0__Reg1_2__Tie0__Tie1__Mem256_RC128X5_4,
2676 Convert__Reg1_0__Reg1_2__Tie0__Tie1__Mem512_RC256X5_4,
2677 Convert__Reg1_1__Reg1_3__Tie0__Tie1__Mem128_RC128X5_0,
2678 Convert__Reg1_1__Reg1_3__Tie0__Tie1__Mem256_RC128X5_0,
2679 Convert__Reg1_1__Reg1_3__Tie0__Tie1__Mem512_RC256X5_0,
2680 Convert__Reg1_2__Reg1_0__Tie0__Mem256_RC2565_1__Tie1,
2681 Convert__Reg1_0__Reg1_2__Tie0__Mem256_RC2565_1__Tie1,
2682 Convert__Reg1_0__Reg1_2__Tie0__Tie1__Mem256_RC256X5_4,
2683 Convert__Reg1_0__Reg1_2__Tie0__Tie1__Mem512_RC5125_4,
2684 Convert__Reg1_1__Reg1_3__Tie0__Tie1__Mem256_RC256X5_0,
2685 Convert__Reg1_1__Reg1_3__Tie0__Tie1__Mem512_RC5125_0,
2686 Convert__Reg1_1__Mem512_RC256X5_3,
2687 Convert__Reg1_2__Mem512_RC256X5_0,
2688 Convert__Reg1_1__Mem512_RC5125_3,
2689 Convert__Reg1_2__Mem512_RC5125_0,
2690 Convert__Reg1_1__Mem256_RC5125_3,
2691 Convert__Reg1_2__Mem256_RC5125_0,
2692 Convert__Reg1_2__Reg1_0__Tie0__Mem128_RC2565_1__Tie1,
2693 Convert__Reg1_0__Reg1_2__Tie0__Mem128_RC2565_1__Tie1,
2694 Convert__Reg1_2__Reg1_0__Tie0__Mem64_RC1285_1__Tie1,
2695 Convert__Reg1_0__Reg1_2__Tie0__Mem64_RC1285_1__Tie1,
2696 Convert__Reg1_0__Reg1_2__Tie0__Tie1__Mem128_RC256X5_4,
2697 Convert__Reg1_0__Reg1_2__Tie0__Tie1__Mem64_RC128X5_4,
2698 Convert__Reg1_0__Reg1_2__Tie0__Tie1__Mem256_RC5125_4,
2699 Convert__Reg1_1__Reg1_3__Tie0__Tie1__Mem128_RC256X5_0,
2700 Convert__Reg1_1__Reg1_3__Tie0__Tie1__Mem256_RC5125_0,
2701 Convert__Reg1_1__Reg1_3__Tie0__Tie1__Mem64_RC128X5_0,
2702 Convert__Reg1_0__Tie0__Reg1_2__Mem1285_4__ImmUnsignedi81_5,
2703 Convert__Reg1_0__Tie0__Reg1_2__Mem2565_4__ImmUnsignedi81_5,
2704 Convert__Reg1_0__Tie0__Reg1_2__Mem5125_4__ImmUnsignedi81_5,
2705 Convert__Reg1_2__Tie0__Reg1_4__Mem1285_1__ImmUnsignedi81_0,
2706 Convert__Reg1_2__Tie0__Reg1_4__Mem2565_1__ImmUnsignedi81_0,
2707 Convert__Reg1_2__Tie0__Reg1_4__Mem5125_1__ImmUnsignedi81_0,
2708 Convert__Reg1_0__Reg1_2__Mem1285_5__ImmUnsignedi81_6,
2709 Convert__Reg1_0__Tie0__Reg1_2__Mem645_4__ImmUnsignedi81_6,
2710 Convert__Reg1_0__Reg1_2__Mem2565_5__ImmUnsignedi81_6,
2711 Convert__Reg1_0__Reg1_2__Mem5125_5__ImmUnsignedi81_6,
2712 Convert__Reg1_3__Tie0__Reg1_5__Mem645_1__ImmUnsignedi81_0,
2713 Convert__Reg1_0__Reg1_2__Mem645_5__ImmUnsignedi81_7,
2714 Convert__Reg1_0__Tie0__Reg1_2__Mem325_4__ImmUnsignedi81_6,
2715 Convert__Reg1_3__Tie0__Reg1_5__Mem325_1__ImmUnsignedi81_0,
2716 Convert__Reg1_0__Reg1_2__Mem325_5__ImmUnsignedi81_7,
2717 Convert__Reg1_0__Reg1_2__Reg1_5__Mem645_6__ImmUnsignedi81_7,
2718 Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6__ImmUnsignedi81_8,
2719 Convert__Reg1_0__Reg1_2__Reg1_5__Mem325_6__ImmUnsignedi81_7,
2720 Convert__Reg1_0__Reg1_1__Mem85_2__ImmUnsignedi81_4,
2721 Convert__Reg1_4__Reg1_3__Mem85_1__ImmUnsignedi81_0,
2722 Convert__Reg1_0__Tie0__Reg1_2__Reg1_4__Mem85_5__ImmUnsignedi81_7,
2723 Convert__Reg1_4__Tie0__Reg1_6__Reg1_3__Mem85_1__ImmUnsignedi81_0,
2724 Convert__Reg1_0__Reg1_2__Reg1_5__Mem85_6__ImmUnsignedi81_8,
2725 Convert__Reg1_4__Reg1_6__Reg1_3__Mem85_1__ImmUnsignedi81_0,
2726 Convert__Mem1285_2__Reg1_1__Reg1_0,
2727 Convert__Mem2565_2__Reg1_1__Reg1_0,
2728 Convert__Mem1285_0__Reg1_1__Reg1_2,
2729 Convert__Mem2565_0__Reg1_1__Reg1_2,
2730 Convert__Reg1_0__Reg1_2__Reg1_4,
2731 Convert__Mem645_1__Reg1_3__Reg1_0,
2732 Convert__Mem645_0__Reg1_2__Reg1_4,
2733 Convert__Mem325_1__Reg1_3__Reg1_0,
2734 Convert__Mem325_0__Reg1_2__Reg1_4,
2735 Convert__Reg1_0__Tie0__Reg1_2__Mem85_4,
2736 Convert__Reg1_1__Tie0__Reg1_3__Mem85_0,
2737 Convert__Reg1_0__Reg1_2__Mem85_5,
2738 Convert__Reg1_1__Reg1_3__Mem85_0,
2739 Convert__Reg1_0__Tie0__Reg1_2__Mem165_4,
2740 Convert__Reg1_1__Tie0__Reg1_3__Mem165_0,
2741 Convert__Reg1_0__Reg1_2__Mem165_5,
2742 Convert__Reg1_1__Reg1_3__Mem165_0,
2743 Convert__Reg1_2__Reg1_1__Reg1_0__imm_95_17,
2744 Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_17,
2745 Convert__Reg1_0__Reg1_1__Mem1285_2__imm_95_17,
2746 Convert__Reg1_0__Reg1_1__Mem2565_2__imm_95_17,
2747 Convert__Reg1_0__Reg1_1__Mem5125_2__imm_95_17,
2748 Convert__Reg1_2__Reg1_1__Mem1285_0__imm_95_17,
2749 Convert__Reg1_2__Reg1_1__Mem2565_0__imm_95_17,
2750 Convert__Reg1_2__Reg1_1__Mem5125_0__imm_95_17,
2751 Convert__Reg1_2__Reg1_1__Reg1_0__imm_95_1,
2752 Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_1,
2753 Convert__Reg1_0__Reg1_1__Mem1285_2__imm_95_1,
2754 Convert__Reg1_0__Reg1_1__Mem2565_2__imm_95_1,
2755 Convert__Reg1_0__Reg1_1__Mem5125_2__imm_95_1,
2756 Convert__Reg1_2__Reg1_1__Mem1285_0__imm_95_1,
2757 Convert__Reg1_2__Reg1_1__Mem2565_0__imm_95_1,
2758 Convert__Reg1_2__Reg1_1__Mem5125_0__imm_95_1,
2759 Convert__Reg1_2__Reg1_1__Reg1_0__imm_95_16,
2760 Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_16,
2761 Convert__Reg1_0__Reg1_1__Mem1285_2__imm_95_16,
2762 Convert__Reg1_0__Reg1_1__Mem2565_2__imm_95_16,
2763 Convert__Reg1_0__Reg1_1__Mem5125_2__imm_95_16,
2764 Convert__Reg1_2__Reg1_1__Mem1285_0__imm_95_16,
2765 Convert__Reg1_2__Reg1_1__Mem2565_0__imm_95_16,
2766 Convert__Reg1_2__Reg1_1__Mem5125_0__imm_95_16,
2767 Convert__Reg1_2__Reg1_1__Reg1_0__imm_95_0,
2768 Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0,
2769 Convert__Reg1_0__Reg1_1__Mem1285_2__imm_95_0,
2770 Convert__Reg1_0__Reg1_1__Mem2565_2__imm_95_0,
2771 Convert__Reg1_0__Reg1_1__Mem5125_2__imm_95_0,
2772 Convert__Reg1_2__Reg1_1__Mem1285_0__imm_95_0,
2773 Convert__Reg1_2__Reg1_1__Mem2565_0__imm_95_0,
2774 Convert__Reg1_2__Reg1_1__Mem5125_0__imm_95_0,
2775 Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmUnsignedi81_4,
2776 Convert__Reg1_0__Reg1_1__Reg1_2__Mem1285_3__ImmUnsignedi81_4,
2777 Convert__Reg1_0__Reg1_1__Mem1285_2__Reg1_3__ImmUnsignedi81_4,
2778 Convert__Reg1_0__Reg1_1__Reg1_2__Mem2565_3__ImmUnsignedi81_4,
2779 Convert__Reg1_0__Reg1_1__Mem2565_2__Reg1_3__ImmUnsignedi81_4,
2780 Convert__Reg1_4__Reg1_3__Reg1_2__Reg1_1__ImmUnsignedi81_0,
2781 Convert__Reg1_4__Reg1_3__Mem1285_2__Reg1_1__ImmUnsignedi81_0,
2782 Convert__Reg1_4__Reg1_3__Mem2565_2__Reg1_1__ImmUnsignedi81_0,
2783 Convert__Reg1_4__Reg1_3__Reg1_2__Mem1285_1__ImmUnsignedi81_0,
2784 Convert__Reg1_4__Reg1_3__Reg1_2__Mem2565_1__ImmUnsignedi81_0,
2785 Convert__Reg1_0__Reg1_1__GR32orGR641_2__ImmUnsignedi81_3,
2786 Convert__Reg1_0__Reg1_1__Mem85_2__ImmUnsignedi81_3,
2787 Convert__Reg1_3__Reg1_2__GR32orGR641_1__ImmUnsignedi81_0,
2788 Convert__Reg1_3__Reg1_2__Mem85_1__ImmUnsignedi81_0,
2789 Convert__Reg1_0__Reg1_1__Mem165_2__ImmUnsignedi81_3,
2790 Convert__Reg1_3__Reg1_2__Mem165_1__ImmUnsignedi81_0,
2791 Convert__Mem165_1__Reg1_3__Reg1_0,
2792 Convert__Mem165_0__Reg1_2__Reg1_4,
2793 Convert__Reg1_2__Mem1285_1__Reg1_0,
2794 Convert__Reg1_0__Mem1285_1__Reg1_2,
2795 Convert__Reg1_3__Mem128_RC128X5_1__Tie0__Reg1_0,
2796 Convert__Reg1_3__Mem256_RC256X5_1__Tie0__Reg1_0,
2797 Convert__Reg1_3__Mem512_RC5125_1__Tie0__Reg1_0,
2798 Convert__Reg1_2__Mem128_RC128X5_0__Tie0__Reg1_4,
2799 Convert__Reg1_2__Mem256_RC256X5_0__Tie0__Reg1_4,
2800 Convert__Reg1_2__Mem512_RC5125_0__Tie0__Reg1_4,
2801 Convert__Reg1_3__Mem256_RC128X5_1__Tie0__Reg1_0,
2802 Convert__Reg1_3__Mem512_RC256X5_1__Tie0__Reg1_0,
2803 Convert__Reg1_2__Mem256_RC128X5_0__Tie0__Reg1_4,
2804 Convert__Reg1_2__Mem512_RC256X5_0__Tie0__Reg1_4,
2805 Convert__Reg1_3__Mem128_RC256X5_1__Tie0__Reg1_0,
2806 Convert__Reg1_3__Mem64_RC128X5_1__Tie0__Reg1_0,
2807 Convert__Reg1_3__Mem256_RC5125_1__Tie0__Reg1_0,
2808 Convert__Reg1_2__Mem128_RC256X5_0__Tie0__Reg1_4,
2809 Convert__Reg1_2__Mem256_RC5125_0__Tie0__Reg1_4,
2810 Convert__Reg1_2__Mem64_RC128X5_0__Tie0__Reg1_4,
2811 Convert__AbsMem161_0,
2812 CVT_NUM_SIGNATURES
2813};
2814
2815} // end anonymous namespace
2816
2817static const uint8_t ConversionTable[CVT_NUM_SIGNATURES][13] = {
2818 // Convert_NoOperands
2819 { CVT_Done },
2820 // Convert__imm_95_10
2821 { CVT_imm_95_10, 0, CVT_Done },
2822 // Convert__Imm1_0
2823 { CVT_95_addImmOperands, 1, CVT_Done },
2824 // Convert__Imm1_1
2825 { CVT_95_addImmOperands, 2, CVT_Done },
2826 // Convert__regAX__Tie0__ImmSExti16i81_1
2827 { CVT_regAX, 0, CVT_Tied, 0, CVT_95_addImmOperands, 2, CVT_Done },
2828 // Convert__regEAX__Tie0__ImmSExti32i81_1
2829 { CVT_regEAX, 0, CVT_Tied, 0, CVT_95_addImmOperands, 2, CVT_Done },
2830 // Convert__regRAX__Tie0__ImmSExti64i81_1
2831 { CVT_regRAX, 0, CVT_Tied, 0, CVT_95_addImmOperands, 2, CVT_Done },
2832 // Convert__ImmSExti64i321_1
2833 { CVT_95_addImmOperands, 2, CVT_Done },
2834 // Convert__Reg1_0__Tie0__Reg1_1
2835 { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_Reg, 2, CVT_Done },
2836 // Convert__Reg1_0__Tie0__ImmSExti16i81_1
2837 { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_addImmOperands, 2, CVT_Done },
2838 // Convert__Reg1_0__Tie0__Imm1_1
2839 { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_addImmOperands, 2, CVT_Done },
2840 // Convert__Reg1_0__Tie0__Mem165_1
2841 { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_addMemOperands, 2, CVT_Done },
2842 // Convert__Reg1_0__Tie0__ImmSExti32i81_1
2843 { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_addImmOperands, 2, CVT_Done },
2844 // Convert__Reg1_0__Tie0__Mem325_1
2845 { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_addMemOperands, 2, CVT_Done },
2846 // Convert__Reg1_0__Tie0__ImmSExti64i81_1
2847 { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_addImmOperands, 2, CVT_Done },
2848 // Convert__Reg1_0__Tie0__ImmSExti64i321_1
2849 { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_addImmOperands, 2, CVT_Done },
2850 // Convert__Reg1_0__Tie0__Mem645_1
2851 { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_addMemOperands, 2, CVT_Done },
2852 // Convert__Reg1_0__Tie0__Mem85_1
2853 { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_addMemOperands, 2, CVT_Done },
2854 // Convert__Mem165_0__Reg1_1
2855 { CVT_95_addMemOperands, 1, CVT_95_Reg, 2, CVT_Done },
2856 // Convert__Mem165_0__ImmSExti16i81_1
2857 { CVT_95_addMemOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
2858 // Convert__Mem165_0__Imm1_1
2859 { CVT_95_addMemOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
2860 // Convert__Mem325_0__Reg1_1
2861 { CVT_95_addMemOperands, 1, CVT_95_Reg, 2, CVT_Done },
2862 // Convert__Mem325_0__ImmSExti32i81_1
2863 { CVT_95_addMemOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
2864 // Convert__Mem325_0__Imm1_1
2865 { CVT_95_addMemOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
2866 // Convert__Mem645_0__Reg1_1
2867 { CVT_95_addMemOperands, 1, CVT_95_Reg, 2, CVT_Done },
2868 // Convert__Mem645_0__ImmSExti64i81_1
2869 { CVT_95_addMemOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
2870 // Convert__Mem645_0__ImmSExti64i321_1
2871 { CVT_95_addMemOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
2872 // Convert__Mem85_0__Reg1_1
2873 { CVT_95_addMemOperands, 1, CVT_95_Reg, 2, CVT_Done },
2874 // Convert__Mem85_0__Imm1_1
2875 { CVT_95_addMemOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
2876 // Convert__Reg1_1__Tie0__Reg1_0
2877 { CVT_95_Reg, 2, CVT_Tied, 0, CVT_95_Reg, 1, CVT_Done },
2878 // Convert__Mem85_1__Reg1_0
2879 { CVT_95_addMemOperands, 2, CVT_95_Reg, 1, CVT_Done },
2880 // Convert__Reg1_1__Tie0__Imm1_0
2881 { CVT_95_Reg, 2, CVT_Tied, 0, CVT_95_addImmOperands, 1, CVT_Done },
2882 // Convert__Mem85_1__Imm1_0
2883 { CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
2884 // Convert__Reg1_1__Tie0__Mem85_0
2885 { CVT_95_Reg, 2, CVT_Tied, 0, CVT_95_addMemOperands, 1, CVT_Done },
2886 // Convert__Mem325_1__Reg1_0
2887 { CVT_95_addMemOperands, 2, CVT_95_Reg, 1, CVT_Done },
2888 // Convert__regEAX__Tie0__ImmSExti32i81_0
2889 { CVT_regEAX, 0, CVT_Tied, 0, CVT_95_addImmOperands, 1, CVT_Done },
2890 // Convert__Reg1_1__Tie0__ImmSExti32i81_0
2891 { CVT_95_Reg, 2, CVT_Tied, 0, CVT_95_addImmOperands, 1, CVT_Done },
2892 // Convert__Mem325_1__ImmSExti32i81_0
2893 { CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
2894 // Convert__Mem325_1__Imm1_0
2895 { CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
2896 // Convert__Reg1_1__Tie0__Mem325_0
2897 { CVT_95_Reg, 2, CVT_Tied, 0, CVT_95_addMemOperands, 1, CVT_Done },
2898 // Convert__Mem645_1__Reg1_0
2899 { CVT_95_addMemOperands, 2, CVT_95_Reg, 1, CVT_Done },
2900 // Convert__regRAX__Tie0__ImmSExti64i81_0
2901 { CVT_regRAX, 0, CVT_Tied, 0, CVT_95_addImmOperands, 1, CVT_Done },
2902 // Convert__Reg1_1__Tie0__ImmSExti64i81_0
2903 { CVT_95_Reg, 2, CVT_Tied, 0, CVT_95_addImmOperands, 1, CVT_Done },
2904 // Convert__Mem645_1__ImmSExti64i81_0
2905 { CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
2906 // Convert__ImmSExti64i321_0
2907 { CVT_95_addImmOperands, 1, CVT_Done },
2908 // Convert__Reg1_1__Tie0__ImmSExti64i321_0
2909 { CVT_95_Reg, 2, CVT_Tied, 0, CVT_95_addImmOperands, 1, CVT_Done },
2910 // Convert__Mem645_1__ImmSExti64i321_0
2911 { CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
2912 // Convert__Reg1_1__Tie0__Mem645_0
2913 { CVT_95_Reg, 2, CVT_Tied, 0, CVT_95_addMemOperands, 1, CVT_Done },
2914 // Convert__Mem165_1__Reg1_0
2915 { CVT_95_addMemOperands, 2, CVT_95_Reg, 1, CVT_Done },
2916 // Convert__regAX__Tie0__ImmSExti16i81_0
2917 { CVT_regAX, 0, CVT_Tied, 0, CVT_95_addImmOperands, 1, CVT_Done },
2918 // Convert__Reg1_1__Tie0__ImmSExti16i81_0
2919 { CVT_95_Reg, 2, CVT_Tied, 0, CVT_95_addImmOperands, 1, CVT_Done },
2920 // Convert__Mem165_1__ImmSExti16i81_0
2921 { CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
2922 // Convert__Mem165_1__Imm1_0
2923 { CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
2924 // Convert__Reg1_1__Tie0__Mem165_0
2925 { CVT_95_Reg, 2, CVT_Tied, 0, CVT_95_addMemOperands, 1, CVT_Done },
2926 // Convert__Reg1_0__Tie0__Mem1285_1
2927 { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_addMemOperands, 2, CVT_Done },
2928 // Convert__Reg1_1__Tie0__Mem1285_0
2929 { CVT_95_Reg, 2, CVT_Tied, 0, CVT_95_addMemOperands, 1, CVT_Done },
2930 // Convert__Reg1_0__Reg1_1
2931 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Done },
2932 // Convert__Reg1_0__Mem325_1
2933 { CVT_95_Reg, 1, CVT_95_addMemOperands, 2, CVT_Done },
2934 // Convert__Reg1_0__Mem645_1
2935 { CVT_95_Reg, 1, CVT_95_addMemOperands, 2, CVT_Done },
2936 // Convert__Reg1_1__Reg1_0
2937 { CVT_95_Reg, 2, CVT_95_Reg, 1, CVT_Done },
2938 // Convert__Reg1_1__Mem325_0
2939 { CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_Done },
2940 // Convert__Reg1_1__Mem645_0
2941 { CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_Done },
2942 // Convert__Reg1_0__Mem1285_1
2943 { CVT_95_Reg, 1, CVT_95_addMemOperands, 2, CVT_Done },
2944 // Convert__Reg1_1__Mem1285_0
2945 { CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_Done },
2946 // Convert__Reg1_0__Reg1_1__ImmUnsignedi81_2
2947 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
2948 // Convert__Reg1_0__Mem1285_1__ImmUnsignedi81_2
2949 { CVT_95_Reg, 1, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
2950 // Convert__Reg1_2__Reg1_1__ImmUnsignedi81_0
2951 { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
2952 // Convert__Reg1_2__Mem1285_1__ImmUnsignedi81_0
2953 { CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
2954 // Convert__Reg1_0__Reg1_1__Reg1_2
2955 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
2956 // Convert__Reg1_0__Reg1_1__Mem325_2
2957 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_Done },
2958 // Convert__Reg1_0__Reg1_1__Mem645_2
2959 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_Done },
2960 // Convert__Reg1_2__Reg1_1__Reg1_0
2961 { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_Reg, 1, CVT_Done },
2962 // Convert__Reg1_2__Reg1_1__Mem325_0
2963 { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_Done },
2964 // Convert__Reg1_2__Reg1_1__Mem645_0
2965 { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_Done },
2966 // Convert__Reg1_0__Reg1_1__Imm1_2
2967 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
2968 // Convert__Reg1_0__Mem325_1__Reg1_2
2969 { CVT_95_Reg, 1, CVT_95_addMemOperands, 2, CVT_95_Reg, 3, CVT_Done },
2970 // Convert__Reg1_0__Mem325_1__Imm1_2
2971 { CVT_95_Reg, 1, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
2972 // Convert__Reg1_0__Reg1_1__ImmSExti64i321_2
2973 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
2974 // Convert__Reg1_0__Mem645_1__Reg1_2
2975 { CVT_95_Reg, 1, CVT_95_addMemOperands, 2, CVT_95_Reg, 3, CVT_Done },
2976 // Convert__Reg1_0__Mem645_1__ImmSExti64i321_2
2977 { CVT_95_Reg, 1, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
2978 // Convert__Reg1_2__Reg1_1__ImmSExti64i321_0
2979 { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
2980 // Convert__Reg1_2__Mem645_1__ImmSExti64i321_0
2981 { CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
2982 // Convert__Reg1_2__Reg1_1__Imm1_0
2983 { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
2984 // Convert__Reg1_2__Mem325_1__Imm1_0
2985 { CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
2986 // Convert__Reg1_2__Mem325_1__Reg1_0
2987 { CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_Reg, 1, CVT_Done },
2988 // Convert__Reg1_2__Mem645_1__Reg1_0
2989 { CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_Reg, 1, CVT_Done },
2990 // Convert__Reg1_0__Tie0__Reg1_1__ImmUnsignedi81_2
2991 { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
2992 // Convert__Reg1_0__Tie0__Mem1285_1__ImmUnsignedi81_2
2993 { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
2994 // Convert__Reg1_2__Tie0__Reg1_1__ImmUnsignedi81_0
2995 { CVT_95_Reg, 3, CVT_Tied, 0, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
2996 // Convert__Reg1_2__Tie0__Mem1285_1__ImmUnsignedi81_0
2997 { CVT_95_Reg, 3, CVT_Tied, 0, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
2998 // Convert__Reg1_2__Tie0__Reg1_1
2999 { CVT_95_Reg, 3, CVT_Tied, 0, CVT_95_Reg, 2, CVT_Done },
3000 // Convert__Reg1_2__Tie0__Mem1285_1
3001 { CVT_95_Reg, 3, CVT_Tied, 0, CVT_95_addMemOperands, 2, CVT_Done },
3002 // Convert__Reg1_0__Mem5_1
3003 { CVT_95_Reg, 1, CVT_95_addMemOperands, 2, CVT_Done },
3004 // Convert__Reg1_1__Mem5_0
3005 { CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_Done },
3006 // Convert__Mem1285_1__Reg1_0
3007 { CVT_95_addMemOperands, 2, CVT_95_Reg, 1, CVT_Done },
3008 // Convert__Mem1285_0__Reg1_1
3009 { CVT_95_addMemOperands, 1, CVT_95_Reg, 2, CVT_Done },
3010 // Convert__Reg1_0__Mem165_1
3011 { CVT_95_Reg, 1, CVT_95_addMemOperands, 2, CVT_Done },
3012 // Convert__Reg1_1__Mem165_0
3013 { CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_Done },
3014 // Convert__Reg1_0__Tie0
3015 { CVT_95_Reg, 1, CVT_Tied, 0, CVT_Done },
3016 // Convert__Reg1_0__ImmSExti16i81_1
3017 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
3018 // Convert__Reg1_0__ImmSExti32i81_1
3019 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
3020 // Convert__Reg1_0__ImmSExti64i81_1
3021 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
3022 // Convert__Reg1_1__ImmSExti32i81_0
3023 { CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
3024 // Convert__Reg1_1__ImmSExti64i81_0
3025 { CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
3026 // Convert__Reg1_1__ImmSExti16i81_0
3027 { CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
3028 // Convert__Reg1_0
3029 { CVT_95_Reg, 1, CVT_Done },
3030 // Convert__AbsMem1_0
3031 { CVT_95_addAbsMemOperands, 1, CVT_Done },
3032 // Convert__Mem165_0
3033 { CVT_95_addMemOperands, 1, CVT_Done },
3034 // Convert__Mem325_0
3035 { CVT_95_addMemOperands, 1, CVT_Done },
3036 // Convert__Mem645_0
3037 { CVT_95_addMemOperands, 1, CVT_Done },
3038 // Convert__Mem5_0
3039 { CVT_95_addMemOperands, 1, CVT_Done },
3040 // Convert__Mem165_1
3041 { CVT_95_addMemOperands, 2, CVT_Done },
3042 // Convert__Mem325_1
3043 { CVT_95_addMemOperands, 2, CVT_Done },
3044 // Convert__Mem645_1
3045 { CVT_95_addMemOperands, 2, CVT_Done },
3046 // Convert__Imm1_1__Imm1_0
3047 { CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3048 // Convert__Reg1_1
3049 { CVT_95_Reg, 2, CVT_Done },
3050 // Convert__Mem85_0
3051 { CVT_95_addMemOperands, 1, CVT_Done },
3052 // Convert__Reg1_0__Tie0__Reg1_0
3053 { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_Reg, 1, CVT_Done },
3054 // Convert__regAX__ImmSExti16i81_1
3055 { CVT_regAX, 0, CVT_95_addImmOperands, 2, CVT_Done },
3056 // Convert__regEAX__ImmSExti32i81_1
3057 { CVT_regEAX, 0, CVT_95_addImmOperands, 2, CVT_Done },
3058 // Convert__regRAX__ImmSExti64i81_1
3059 { CVT_regRAX, 0, CVT_95_addImmOperands, 2, CVT_Done },
3060 // Convert__Reg1_0__Imm1_1
3061 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
3062 // Convert__Reg1_0__ImmSExti64i321_1
3063 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
3064 // Convert__Reg1_0__Mem85_1
3065 { CVT_95_Reg, 1, CVT_95_addMemOperands, 2, CVT_Done },
3066 // Convert__Reg1_3__Tie0__Reg1_2__Imm1_0
3067 { CVT_95_Reg, 4, CVT_Tied, 0, CVT_95_Reg, 3, CVT_95_addImmOperands, 1, CVT_Done },
3068 // Convert__Reg1_2__Tie0__Reg1_3__Imm1_0
3069 { CVT_95_Reg, 3, CVT_Tied, 0, CVT_95_Reg, 4, CVT_95_addImmOperands, 1, CVT_Done },
3070 // Convert__Reg1_2__Tie0__Mem1285_3__Imm1_0
3071 { CVT_95_Reg, 3, CVT_Tied, 0, CVT_95_addMemOperands, 4, CVT_95_addImmOperands, 1, CVT_Done },
3072 // Convert__Reg1_3__Tie0__Mem1285_2__Imm1_0
3073 { CVT_95_Reg, 4, CVT_Tied, 0, CVT_95_addMemOperands, 3, CVT_95_addImmOperands, 1, CVT_Done },
3074 // Convert__Reg1_2__Tie0__Mem645_3__Imm1_0
3075 { CVT_95_Reg, 3, CVT_Tied, 0, CVT_95_addMemOperands, 4, CVT_95_addImmOperands, 1, CVT_Done },
3076 // Convert__Reg1_3__Tie0__Mem645_2__Imm1_0
3077 { CVT_95_Reg, 4, CVT_Tied, 0, CVT_95_addMemOperands, 3, CVT_95_addImmOperands, 1, CVT_Done },
3078 // Convert__Reg1_2__Tie0__Mem325_3__Imm1_0
3079 { CVT_95_Reg, 3, CVT_Tied, 0, CVT_95_addMemOperands, 4, CVT_95_addImmOperands, 1, CVT_Done },
3080 // Convert__Reg1_3__Tie0__Mem325_2__Imm1_0
3081 { CVT_95_Reg, 4, CVT_Tied, 0, CVT_95_addMemOperands, 3, CVT_95_addImmOperands, 1, CVT_Done },
3082 // Convert__Reg1_1__Imm1_0
3083 { CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
3084 // Convert__Reg1_1__Mem85_0
3085 { CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_Done },
3086 // Convert__regEAX__ImmSExti32i81_0
3087 { CVT_regEAX, 0, CVT_95_addImmOperands, 1, CVT_Done },
3088 // Convert__regRAX__ImmSExti64i81_0
3089 { CVT_regRAX, 0, CVT_95_addImmOperands, 1, CVT_Done },
3090 // Convert__Reg1_1__ImmSExti64i321_0
3091 { CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
3092 // Convert__DstIdx161_0__SrcIdx162_1
3093 { CVT_95_addDstIdxOperands, 1, CVT_95_addSrcIdxOperands, 2, CVT_Done },
3094 // Convert__DstIdx321_0__SrcIdx322_1
3095 { CVT_95_addDstIdxOperands, 1, CVT_95_addSrcIdxOperands, 2, CVT_Done },
3096 // Convert__DstIdx641_0__SrcIdx642_1
3097 { CVT_95_addDstIdxOperands, 1, CVT_95_addSrcIdxOperands, 2, CVT_Done },
3098 // Convert__DstIdx81_0__SrcIdx82_1
3099 { CVT_95_addDstIdxOperands, 1, CVT_95_addSrcIdxOperands, 2, CVT_Done },
3100 // Convert__DstIdx161_1__SrcIdx162_0
3101 { CVT_95_addDstIdxOperands, 2, CVT_95_addSrcIdxOperands, 1, CVT_Done },
3102 // Convert__DstIdx321_1__SrcIdx322_0
3103 { CVT_95_addDstIdxOperands, 2, CVT_95_addSrcIdxOperands, 1, CVT_Done },
3104 // Convert__DstIdx641_1__SrcIdx642_0
3105 { CVT_95_addDstIdxOperands, 2, CVT_95_addSrcIdxOperands, 1, CVT_Done },
3106 // Convert__DstIdx81_1__SrcIdx82_0
3107 { CVT_95_addDstIdxOperands, 2, CVT_95_addSrcIdxOperands, 1, CVT_Done },
3108 // Convert__Reg1_0__Tie0__Mem645_1__ImmUnsignedi81_2
3109 { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
3110 // Convert__Reg1_2__Tie0__Mem645_1__ImmUnsignedi81_0
3111 { CVT_95_Reg, 3, CVT_Tied, 0, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3112 // Convert__Reg1_0__Tie0__Mem325_1__ImmUnsignedi81_2
3113 { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
3114 // Convert__Reg1_2__Tie0__Mem325_1__ImmUnsignedi81_0
3115 { CVT_95_Reg, 3, CVT_Tied, 0, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3116 // Convert__regAX__ImmSExti16i81_0
3117 { CVT_regAX, 0, CVT_95_addImmOperands, 1, CVT_Done },
3118 // Convert__Mem1285_0
3119 { CVT_95_addMemOperands, 1, CVT_Done },
3120 // Convert__Mem85_1
3121 { CVT_95_addMemOperands, 2, CVT_Done },
3122 // Convert__Imm1_0__Imm1_1
3123 { CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
3124 // Convert__GR32orGR641_2__Reg1_1__ImmUnsignedi81_0
3125 { CVT_95_addGR32orGR64Operands, 3, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
3126 // Convert__Mem325_2__Reg1_1__ImmUnsignedi81_0
3127 { CVT_95_addMemOperands, 3, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
3128 // Convert__GR32orGR641_0__Reg1_1__ImmUnsignedi81_2
3129 { CVT_95_addGR32orGR64Operands, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
3130 // Convert__Mem325_0__Reg1_1__ImmUnsignedi81_2
3131 { CVT_95_addMemOperands, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
3132 // Convert__Reg1_0__Tie0__ImmUnsignedi81_1__ImmUnsignedi81_2
3133 { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
3134 // Convert__Reg1_2__Tie0__ImmUnsignedi81_1__ImmUnsignedi81_0
3135 { CVT_95_Reg, 3, CVT_Tied, 0, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3136 // Convert__regST1
3137 { CVT_regST1, 0, CVT_Done },
3138 // Convert__regST0
3139 { CVT_regST0, 0, CVT_Done },
3140 // Convert__Mem805_0
3141 { CVT_95_addMemOperands, 1, CVT_Done },
3142 // Convert__Reg1_0__Reg1_0__ImmSExti16i81_1
3143 { CVT_95_Reg, 1, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
3144 // Convert__Reg1_0__Reg1_0__Imm1_1
3145 { CVT_95_Reg, 1, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
3146 // Convert__Reg1_0__Reg1_0__ImmSExti32i81_1
3147 { CVT_95_Reg, 1, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
3148 // Convert__Reg1_0__Reg1_0__ImmSExti64i81_1
3149 { CVT_95_Reg, 1, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
3150 // Convert__Reg1_0__Reg1_0__ImmSExti64i321_1
3151 { CVT_95_Reg, 1, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
3152 // Convert__Reg1_0__Reg1_1__ImmSExti16i81_2
3153 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
3154 // Convert__Reg1_0__Mem165_1__ImmSExti16i81_2
3155 { CVT_95_Reg, 1, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
3156 // Convert__Reg1_0__Mem165_1__Imm1_2
3157 { CVT_95_Reg, 1, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
3158 // Convert__Reg1_0__Reg1_1__ImmSExti32i81_2
3159 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
3160 // Convert__Reg1_0__Mem325_1__ImmSExti32i81_2
3161 { CVT_95_Reg, 1, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
3162 // Convert__Reg1_0__Reg1_1__ImmSExti64i81_2
3163 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
3164 // Convert__Reg1_0__Mem645_1__ImmSExti64i81_2
3165 { CVT_95_Reg, 1, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
3166 // Convert__Reg1_1__Reg1_1__ImmSExti32i81_0
3167 { CVT_95_Reg, 2, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
3168 // Convert__Reg1_1__Reg1_1__Imm1_0
3169 { CVT_95_Reg, 2, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
3170 // Convert__Reg1_2__Reg1_1__ImmSExti32i81_0
3171 { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
3172 // Convert__Reg1_2__Mem325_1__ImmSExti32i81_0
3173 { CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3174 // Convert__Reg1_1__Reg1_1__ImmSExti64i81_0
3175 { CVT_95_Reg, 2, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
3176 // Convert__Reg1_1__Reg1_1__ImmSExti64i321_0
3177 { CVT_95_Reg, 2, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
3178 // Convert__Reg1_2__Reg1_1__ImmSExti64i81_0
3179 { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
3180 // Convert__Reg1_2__Mem645_1__ImmSExti64i81_0
3181 { CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3182 // Convert__Reg1_1__Reg1_1__ImmSExti16i81_0
3183 { CVT_95_Reg, 2, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
3184 // Convert__Reg1_2__Reg1_1__ImmSExti16i81_0
3185 { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
3186 // Convert__Reg1_2__Mem165_1__ImmSExti16i81_0
3187 { CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3188 // Convert__Reg1_2__Mem165_1__Imm1_0
3189 { CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3190 // Convert__ImmUnsignedi81_1
3191 { CVT_95_addImmOperands, 2, CVT_Done },
3192 // Convert__ImmUnsignedi81_0
3193 { CVT_95_addImmOperands, 1, CVT_Done },
3194 // Convert__DstIdx161_1
3195 { CVT_95_addDstIdxOperands, 2, CVT_Done },
3196 // Convert__DstIdx321_1
3197 { CVT_95_addDstIdxOperands, 2, CVT_Done },
3198 // Convert__DstIdx81_1
3199 { CVT_95_addDstIdxOperands, 2, CVT_Done },
3200 // Convert__DstIdx161_0
3201 { CVT_95_addDstIdxOperands, 1, CVT_Done },
3202 // Convert__DstIdx321_0
3203 { CVT_95_addDstIdxOperands, 1, CVT_Done },
3204 // Convert__DstIdx81_0
3205 { CVT_95_addDstIdxOperands, 1, CVT_Done },
3206 // Convert__Reg1_0__Tie0__Reg1_1__ImmUnsignedi81_2__ImmUnsignedi81_3
3207 { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
3208 // Convert__Reg1_3__Tie0__Reg1_2__ImmUnsignedi81_1__ImmUnsignedi81_0
3209 { CVT_95_Reg, 4, CVT_Tied, 0, CVT_95_Reg, 3, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3210 // Convert__Mem5_1
3211 { CVT_95_addMemOperands, 2, CVT_Done },
3212 // Convert__SrcIdx162_0
3213 { CVT_95_addSrcIdxOperands, 1, CVT_Done },
3214 // Convert__SrcIdx322_0
3215 { CVT_95_addSrcIdxOperands, 1, CVT_Done },
3216 // Convert__SrcIdx642_0
3217 { CVT_95_addSrcIdxOperands, 1, CVT_Done },
3218 // Convert__SrcIdx82_0
3219 { CVT_95_addSrcIdxOperands, 1, CVT_Done },
3220 // Convert__SrcIdx82_1
3221 { CVT_95_addSrcIdxOperands, 2, CVT_Done },
3222 // Convert__SrcIdx162_1
3223 { CVT_95_addSrcIdxOperands, 2, CVT_Done },
3224 // Convert__SrcIdx322_1
3225 { CVT_95_addSrcIdxOperands, 2, CVT_Done },
3226 // Convert__SrcIdx642_1
3227 { CVT_95_addSrcIdxOperands, 2, CVT_Done },
3228 // Convert__MemOffs16_82_1
3229 { CVT_95_addMemOffsOperands, 2, CVT_Done },
3230 // Convert__MemOffs32_82_1
3231 { CVT_95_addMemOffsOperands, 2, CVT_Done },
3232 // Convert__MemOffs16_162_1
3233 { CVT_95_addMemOffsOperands, 2, CVT_Done },
3234 // Convert__MemOffs32_162_1
3235 { CVT_95_addMemOffsOperands, 2, CVT_Done },
3236 // Convert__MemOffs16_322_1
3237 { CVT_95_addMemOffsOperands, 2, CVT_Done },
3238 // Convert__MemOffs32_322_1
3239 { CVT_95_addMemOffsOperands, 2, CVT_Done },
3240 // Convert__MemOffs32_642_1
3241 { CVT_95_addMemOffsOperands, 2, CVT_Done },
3242 // Convert__MemOffs16_162_0
3243 { CVT_95_addMemOffsOperands, 1, CVT_Done },
3244 // Convert__MemOffs16_322_0
3245 { CVT_95_addMemOffsOperands, 1, CVT_Done },
3246 // Convert__MemOffs16_82_0
3247 { CVT_95_addMemOffsOperands, 1, CVT_Done },
3248 // Convert__MemOffs32_162_0
3249 { CVT_95_addMemOffsOperands, 1, CVT_Done },
3250 // Convert__MemOffs32_322_0
3251 { CVT_95_addMemOffsOperands, 1, CVT_Done },
3252 // Convert__MemOffs32_642_0
3253 { CVT_95_addMemOffsOperands, 1, CVT_Done },
3254 // Convert__MemOffs32_82_0
3255 { CVT_95_addMemOffsOperands, 1, CVT_Done },
3256 // Convert__MemOffs64_82_1
3257 { CVT_95_addMemOffsOperands, 2, CVT_Done },
3258 // Convert__MemOffs64_162_1
3259 { CVT_95_addMemOffsOperands, 2, CVT_Done },
3260 // Convert__MemOffs64_322_1
3261 { CVT_95_addMemOffsOperands, 2, CVT_Done },
3262 // Convert__MemOffs64_642_1
3263 { CVT_95_addMemOffsOperands, 2, CVT_Done },
3264 // Convert__MemOffs64_162_0
3265 { CVT_95_addMemOffsOperands, 1, CVT_Done },
3266 // Convert__MemOffs64_322_0
3267 { CVT_95_addMemOffsOperands, 1, CVT_Done },
3268 // Convert__MemOffs64_642_0
3269 { CVT_95_addMemOffsOperands, 1, CVT_Done },
3270 // Convert__MemOffs64_82_0
3271 { CVT_95_addMemOffsOperands, 1, CVT_Done },
3272 // Convert__GR32orGR641_1__Reg1_0
3273 { CVT_95_addGR32orGR64Operands, 2, CVT_95_Reg, 1, CVT_Done },
3274 // Convert__GR32orGR641_0__Reg1_1
3275 { CVT_95_addGR32orGR64Operands, 1, CVT_95_Reg, 2, CVT_Done },
3276 // Convert__Reg1_1__Tie0__Reg1_0__imm_95_17
3277 { CVT_95_Reg, 2, CVT_Tied, 0, CVT_95_Reg, 1, CVT_imm_95_17, 0, CVT_Done },
3278 // Convert__Reg1_0__Tie0__Reg1_1__imm_95_17
3279 { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_Reg, 2, CVT_imm_95_17, 0, CVT_Done },
3280 // Convert__Reg1_0__Tie0__Mem1285_1__imm_95_17
3281 { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_addMemOperands, 2, CVT_imm_95_17, 0, CVT_Done },
3282 // Convert__Reg1_1__Tie0__Mem1285_0__imm_95_17
3283 { CVT_95_Reg, 2, CVT_Tied, 0, CVT_95_addMemOperands, 1, CVT_imm_95_17, 0, CVT_Done },
3284 // Convert__Reg1_1__Tie0__Reg1_0__imm_95_1
3285 { CVT_95_Reg, 2, CVT_Tied, 0, CVT_95_Reg, 1, CVT_imm_95_1, 0, CVT_Done },
3286 // Convert__Reg1_0__Tie0__Reg1_1__imm_95_1
3287 { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_Reg, 2, CVT_imm_95_1, 0, CVT_Done },
3288 // Convert__Reg1_0__Tie0__Mem1285_1__imm_95_1
3289 { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_addMemOperands, 2, CVT_imm_95_1, 0, CVT_Done },
3290 // Convert__Reg1_1__Tie0__Mem1285_0__imm_95_1
3291 { CVT_95_Reg, 2, CVT_Tied, 0, CVT_95_addMemOperands, 1, CVT_imm_95_1, 0, CVT_Done },
3292 // Convert__Reg1_1__Tie0__Reg1_0__imm_95_16
3293 { CVT_95_Reg, 2, CVT_Tied, 0, CVT_95_Reg, 1, CVT_imm_95_16, 0, CVT_Done },
3294 // Convert__Reg1_0__Tie0__Reg1_1__imm_95_16
3295 { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_Reg, 2, CVT_imm_95_16, 0, CVT_Done },
3296 // Convert__Reg1_0__Tie0__Mem1285_1__imm_95_16
3297 { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_addMemOperands, 2, CVT_imm_95_16, 0, CVT_Done },
3298 // Convert__Reg1_1__Tie0__Mem1285_0__imm_95_16
3299 { CVT_95_Reg, 2, CVT_Tied, 0, CVT_95_addMemOperands, 1, CVT_imm_95_16, 0, CVT_Done },
3300 // Convert__Reg1_1__Tie0__Reg1_0__imm_95_0
3301 { CVT_95_Reg, 2, CVT_Tied, 0, CVT_95_Reg, 1, CVT_imm_95_0, 0, CVT_Done },
3302 // Convert__Reg1_0__Tie0__Reg1_1__imm_95_0
3303 { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_Reg, 2, CVT_imm_95_0, 0, CVT_Done },
3304 // Convert__Reg1_0__Tie0__Mem1285_1__imm_95_0
3305 { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_addMemOperands, 2, CVT_imm_95_0, 0, CVT_Done },
3306 // Convert__Reg1_1__Tie0__Mem1285_0__imm_95_0
3307 { CVT_95_Reg, 2, CVT_Tied, 0, CVT_95_addMemOperands, 1, CVT_imm_95_0, 0, CVT_Done },
3308 // Convert__Mem85_2__Reg1_1__ImmUnsignedi81_0
3309 { CVT_95_addMemOperands, 3, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
3310 // Convert__Mem85_0__Reg1_1__ImmUnsignedi81_2
3311 { CVT_95_addMemOperands, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
3312 // Convert__Mem645_2__Reg1_1__ImmUnsignedi81_0
3313 { CVT_95_addMemOperands, 3, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
3314 // Convert__Mem645_0__Reg1_1__ImmUnsignedi81_2
3315 { CVT_95_addMemOperands, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
3316 // Convert__Mem165_2__Reg1_1__ImmUnsignedi81_0
3317 { CVT_95_addMemOperands, 3, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
3318 // Convert__Mem165_0__Reg1_1__ImmUnsignedi81_2
3319 { CVT_95_addMemOperands, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
3320 // Convert__Reg1_0__Tie0__GR32orGR641_1__ImmUnsignedi81_2
3321 { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_addGR32orGR64Operands, 2, CVT_95_addImmOperands, 3, CVT_Done },
3322 // Convert__Reg1_0__Tie0__Mem85_1__ImmUnsignedi81_2
3323 { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
3324 // Convert__Reg1_2__Tie0__GR32orGR641_1__ImmUnsignedi81_0
3325 { CVT_95_Reg, 3, CVT_Tied, 0, CVT_95_addGR32orGR64Operands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3326 // Convert__Reg1_2__Tie0__Mem85_1__ImmUnsignedi81_0
3327 { CVT_95_Reg, 3, CVT_Tied, 0, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3328 // Convert__Reg1_0__Tie0__Mem165_1__ImmUnsignedi81_2
3329 { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
3330 // Convert__Reg1_2__Tie0__Mem165_1__ImmUnsignedi81_0
3331 { CVT_95_Reg, 3, CVT_Tied, 0, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3332 // Convert__Reg1_0__Mem645_1__ImmUnsignedi81_2
3333 { CVT_95_Reg, 1, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
3334 // Convert__Reg1_2__Mem645_1__ImmUnsignedi81_0
3335 { CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3336 // Convert__Reg1_0__Tie0__ImmUnsignedi81_1
3337 { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_addImmOperands, 2, CVT_Done },
3338 // Convert__Reg1_1__Tie0__ImmUnsignedi81_0
3339 { CVT_95_Reg, 2, CVT_Tied, 0, CVT_95_addImmOperands, 1, CVT_Done },
3340 // Convert__ImmSExti64i81_0
3341 { CVT_95_addImmOperands, 1, CVT_Done },
3342 // Convert__ImmSExti16i81_0
3343 { CVT_95_addImmOperands, 1, CVT_Done },
3344 // Convert__ImmSExti32i81_0
3345 { CVT_95_addImmOperands, 1, CVT_Done },
3346 // Convert__Mem165_0__ImmUnsignedi81_1
3347 { CVT_95_addMemOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
3348 // Convert__Mem325_0__ImmUnsignedi81_1
3349 { CVT_95_addMemOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
3350 // Convert__Mem645_0__ImmUnsignedi81_1
3351 { CVT_95_addMemOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
3352 // Convert__Mem85_0__ImmUnsignedi81_1
3353 { CVT_95_addMemOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
3354 // Convert__Reg1_1__Tie0
3355 { CVT_95_Reg, 2, CVT_Tied, 0, CVT_Done },
3356 // Convert__Mem85_1__ImmUnsignedi81_0
3357 { CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3358 // Convert__Mem325_1__ImmUnsignedi81_0
3359 { CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3360 // Convert__Mem645_1__ImmUnsignedi81_0
3361 { CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3362 // Convert__Mem165_1__ImmUnsignedi81_0
3363 { CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3364 // Convert__Reg1_0__Mem325_1__ImmUnsignedi81_2
3365 { CVT_95_Reg, 1, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
3366 // Convert__Reg1_2__Mem325_1__ImmUnsignedi81_0
3367 { CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3368 // Convert__DstIdx641_0
3369 { CVT_95_addDstIdxOperands, 1, CVT_Done },
3370 // Convert__DstIdx641_1
3371 { CVT_95_addDstIdxOperands, 2, CVT_Done },
3372 // Convert__Mem325_2__Reg1_1
3373 { CVT_95_addMemOperands, 3, CVT_95_Reg, 2, CVT_Done },
3374 // Convert__Mem645_2__Reg1_1
3375 { CVT_95_addMemOperands, 3, CVT_95_Reg, 2, CVT_Done },
3376 // Convert__Mem165_2__Reg1_1
3377 { CVT_95_addMemOperands, 3, CVT_95_Reg, 2, CVT_Done },
3378 // Convert__Reg1_0__Reg1_1__Mem1285_2
3379 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_Done },
3380 // Convert__Reg1_0__Reg1_1__Mem2565_2
3381 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_Done },
3382 // Convert__Reg1_0__Reg1_1__Mem5125_2
3383 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_Done },
3384 // Convert__Reg1_2__Reg1_1__Mem1285_0
3385 { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_Done },
3386 // Convert__Reg1_2__Reg1_1__Mem2565_0
3387 { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_Done },
3388 // Convert__Reg1_2__Reg1_1__Mem5125_0
3389 { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_Done },
3390 // Convert__Reg1_0__Reg1_1__Reg1_2__AVX512RC1_3
3391 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addAVX512RCOperands, 4, CVT_Done },
3392 // Convert__Reg1_3__Reg1_2__Reg1_1__AVX512RC1_0
3393 { CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addAVX512RCOperands, 1, CVT_Done },
3394 // Convert__Reg1_3__Reg1_2__Mem645_0
3395 { CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_addMemOperands, 1, CVT_Done },
3396 // Convert__Reg1_0__Tie0__Reg1_2__Reg1_4__Reg1_5
3397 { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_Done },
3398 // Convert__Reg1_0__Tie0__Reg1_2__Reg1_4__Mem1285_5
3399 { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addMemOperands, 6, CVT_Done },
3400 // Convert__Reg1_2__Tie0__Reg1_4__Reg1_1__Reg1_0
3401 { CVT_95_Reg, 3, CVT_Tied, 0, CVT_95_Reg, 5, CVT_95_Reg, 2, CVT_95_Reg, 1, CVT_Done },
3402 // Convert__Reg1_0__Tie0__Reg1_2__Reg1_4__Mem2565_5
3403 { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addMemOperands, 6, CVT_Done },
3404 // Convert__Reg1_0__Tie0__Reg1_2__Reg1_4__Mem5125_5
3405 { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addMemOperands, 6, CVT_Done },
3406 // Convert__Reg1_2__Tie0__Reg1_4__Reg1_1__Mem1285_0
3407 { CVT_95_Reg, 3, CVT_Tied, 0, CVT_95_Reg, 5, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_Done },
3408 // Convert__Reg1_2__Tie0__Reg1_4__Reg1_1__Mem2565_0
3409 { CVT_95_Reg, 3, CVT_Tied, 0, CVT_95_Reg, 5, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_Done },
3410 // Convert__Reg1_2__Tie0__Reg1_4__Reg1_1__Mem5125_0
3411 { CVT_95_Reg, 3, CVT_Tied, 0, CVT_95_Reg, 5, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_Done },
3412 // Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6
3413 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_Reg, 7, CVT_Done },
3414 // Convert__Reg1_0__Reg1_2__Reg1_5__Mem1285_6
3415 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_addMemOperands, 7, CVT_Done },
3416 // Convert__Reg1_0__Tie0__Reg1_2__Reg1_4__Mem645_5
3417 { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addMemOperands, 6, CVT_Done },
3418 // Convert__Reg1_2__Reg1_4__Reg1_1__Reg1_0
3419 { CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_Reg, 2, CVT_95_Reg, 1, CVT_Done },
3420 // Convert__Reg1_0__Reg1_2__Reg1_5__Mem2565_6
3421 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_addMemOperands, 7, CVT_Done },
3422 // Convert__Reg1_0__Reg1_2__Reg1_5__Mem5125_6
3423 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_addMemOperands, 7, CVT_Done },
3424 // Convert__Reg1_0__Tie0__Reg1_2__Reg1_4__Reg1_5__AVX512RC1_6
3425 { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_addAVX512RCOperands, 7, CVT_Done },
3426 // Convert__Reg1_3__Tie0__Reg1_5__Reg1_2__Reg1_1__AVX512RC1_0
3427 { CVT_95_Reg, 4, CVT_Tied, 0, CVT_95_Reg, 6, CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addAVX512RCOperands, 1, CVT_Done },
3428 // Convert__Reg1_2__Reg1_4__Reg1_1__Mem1285_0
3429 { CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_Done },
3430 // Convert__Reg1_2__Reg1_4__Reg1_1__Mem2565_0
3431 { CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_Done },
3432 // Convert__Reg1_2__Reg1_4__Reg1_1__Mem5125_0
3433 { CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_Done },
3434 // Convert__Reg1_3__Tie0__Reg1_5__Reg1_2__Mem645_0
3435 { CVT_95_Reg, 4, CVT_Tied, 0, CVT_95_Reg, 6, CVT_95_Reg, 3, CVT_95_addMemOperands, 1, CVT_Done },
3436 // Convert__Reg1_0__Reg1_2__Reg1_5__Mem645_6
3437 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_addMemOperands, 7, CVT_Done },
3438 // Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6__AVX512RC1_7
3439 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_Reg, 7, CVT_95_addAVX512RCOperands, 8, CVT_Done },
3440 // Convert__Reg1_3__Reg1_5__Reg1_2__Reg1_1__AVX512RC1_0
3441 { CVT_95_Reg, 4, CVT_95_Reg, 6, CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addAVX512RCOperands, 1, CVT_Done },
3442 // Convert__Reg1_3__Reg1_5__Reg1_2__Mem645_0
3443 { CVT_95_Reg, 4, CVT_95_Reg, 6, CVT_95_Reg, 3, CVT_95_addMemOperands, 1, CVT_Done },
3444 // Convert__Reg1_3__Reg1_2__Mem325_0
3445 { CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_addMemOperands, 1, CVT_Done },
3446 // Convert__Reg1_0__Tie0__Reg1_2__Reg1_4__Mem325_5
3447 { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addMemOperands, 6, CVT_Done },
3448 // Convert__Reg1_3__Tie0__Reg1_5__Reg1_2__Mem325_0
3449 { CVT_95_Reg, 4, CVT_Tied, 0, CVT_95_Reg, 6, CVT_95_Reg, 3, CVT_95_addMemOperands, 1, CVT_Done },
3450 // Convert__Reg1_0__Reg1_2__Reg1_5__Mem325_6
3451 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_addMemOperands, 7, CVT_Done },
3452 // Convert__Reg1_3__Reg1_5__Reg1_2__Mem325_0
3453 { CVT_95_Reg, 4, CVT_95_Reg, 6, CVT_95_Reg, 3, CVT_95_addMemOperands, 1, CVT_Done },
3454 // Convert__Reg1_2__Tie0__Reg1_4__Reg1_1__Mem645_0
3455 { CVT_95_Reg, 3, CVT_Tied, 0, CVT_95_Reg, 5, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_Done },
3456 // Convert__Reg1_2__Reg1_4__Reg1_1__Mem645_0
3457 { CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_Done },
3458 // Convert__Reg1_2__Tie0__Reg1_4__Reg1_1__Mem325_0
3459 { CVT_95_Reg, 3, CVT_Tied, 0, CVT_95_Reg, 5, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_Done },
3460 // Convert__Reg1_2__Reg1_4__Reg1_1__Mem325_0
3461 { CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_Done },
3462 // Convert__Reg1_0__Reg1_1__Reg1_2__ImmUnsignedi81_3
3463 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
3464 // Convert__Reg1_0__Reg1_1__Mem1285_2__ImmUnsignedi81_3
3465 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
3466 // Convert__Reg1_0__Reg1_1__Mem2565_2__ImmUnsignedi81_3
3467 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
3468 // Convert__Reg1_0__Reg1_1__Mem5125_2__ImmUnsignedi81_3
3469 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
3470 // Convert__Reg1_3__Reg1_2__Reg1_1__ImmUnsignedi81_0
3471 { CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
3472 // Convert__Reg1_3__Reg1_2__Mem1285_1__ImmUnsignedi81_0
3473 { CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3474 // Convert__Reg1_3__Reg1_2__Mem2565_1__ImmUnsignedi81_0
3475 { CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3476 // Convert__Reg1_3__Reg1_2__Mem5125_1__ImmUnsignedi81_0
3477 { CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3478 // Convert__Reg1_0__Reg1_1__Mem325_2__ImmUnsignedi81_4
3479 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_95_addImmOperands, 5, CVT_Done },
3480 // Convert__Reg1_4__Reg1_3__Mem325_1__ImmUnsignedi81_0
3481 { CVT_95_Reg, 5, CVT_95_Reg, 4, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3482 // Convert__Reg1_0__Tie0__Reg1_2__Reg1_4__Reg1_5__ImmUnsignedi81_6
3483 { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_addImmOperands, 7, CVT_Done },
3484 // Convert__Reg1_0__Tie0__Reg1_2__Reg1_4__Mem1285_5__ImmUnsignedi81_6
3485 { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addMemOperands, 6, CVT_95_addImmOperands, 7, CVT_Done },
3486 // Convert__Reg1_0__Tie0__Reg1_2__Reg1_4__Mem2565_5__ImmUnsignedi81_6
3487 { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addMemOperands, 6, CVT_95_addImmOperands, 7, CVT_Done },
3488 // Convert__Reg1_0__Tie0__Reg1_2__Reg1_4__Mem5125_5__ImmUnsignedi81_6
3489 { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addMemOperands, 6, CVT_95_addImmOperands, 7, CVT_Done },
3490 // Convert__Reg1_3__Tie0__Reg1_5__Reg1_2__Reg1_1__ImmUnsignedi81_0
3491 { CVT_95_Reg, 4, CVT_Tied, 0, CVT_95_Reg, 6, CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
3492 // Convert__Reg1_3__Tie0__Reg1_5__Reg1_2__Mem1285_1__ImmUnsignedi81_0
3493 { CVT_95_Reg, 4, CVT_Tied, 0, CVT_95_Reg, 6, CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3494 // Convert__Reg1_3__Tie0__Reg1_5__Reg1_2__Mem2565_1__ImmUnsignedi81_0
3495 { CVT_95_Reg, 4, CVT_Tied, 0, CVT_95_Reg, 6, CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3496 // Convert__Reg1_3__Tie0__Reg1_5__Reg1_2__Mem5125_1__ImmUnsignedi81_0
3497 { CVT_95_Reg, 4, CVT_Tied, 0, CVT_95_Reg, 6, CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3498 // Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6__ImmUnsignedi81_7
3499 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_Reg, 7, CVT_95_addImmOperands, 8, CVT_Done },
3500 // Convert__Reg1_0__Reg1_2__Reg1_5__Mem1285_6__ImmUnsignedi81_7
3501 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_addMemOperands, 7, CVT_95_addImmOperands, 8, CVT_Done },
3502 // Convert__Reg1_0__Tie0__Reg1_2__Reg1_4__Mem325_5__ImmUnsignedi81_7
3503 { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addMemOperands, 6, CVT_95_addImmOperands, 8, CVT_Done },
3504 // Convert__Reg1_0__Reg1_2__Reg1_5__Mem2565_6__ImmUnsignedi81_7
3505 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_addMemOperands, 7, CVT_95_addImmOperands, 8, CVT_Done },
3506 // Convert__Reg1_0__Reg1_2__Reg1_5__Mem5125_6__ImmUnsignedi81_7
3507 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_addMemOperands, 7, CVT_95_addImmOperands, 8, CVT_Done },
3508 // Convert__Reg1_3__Reg1_5__Reg1_2__Reg1_1__ImmUnsignedi81_0
3509 { CVT_95_Reg, 4, CVT_95_Reg, 6, CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
3510 // Convert__Reg1_3__Reg1_5__Reg1_2__Mem1285_1__ImmUnsignedi81_0
3511 { CVT_95_Reg, 4, CVT_95_Reg, 6, CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3512 // Convert__Reg1_3__Reg1_5__Reg1_2__Mem2565_1__ImmUnsignedi81_0
3513 { CVT_95_Reg, 4, CVT_95_Reg, 6, CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3514 // Convert__Reg1_4__Tie0__Reg1_6__Reg1_3__Mem325_1__ImmUnsignedi81_0
3515 { CVT_95_Reg, 5, CVT_Tied, 0, CVT_95_Reg, 7, CVT_95_Reg, 4, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3516 // Convert__Reg1_3__Reg1_5__Reg1_2__Mem5125_1__ImmUnsignedi81_0
3517 { CVT_95_Reg, 4, CVT_95_Reg, 6, CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3518 // Convert__Reg1_0__Reg1_2__Reg1_5__Mem325_6__ImmUnsignedi81_8
3519 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_addMemOperands, 7, CVT_95_addImmOperands, 9, CVT_Done },
3520 // Convert__Reg1_4__Reg1_6__Reg1_3__Mem325_1__ImmUnsignedi81_0
3521 { CVT_95_Reg, 5, CVT_95_Reg, 7, CVT_95_Reg, 4, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3522 // Convert__Reg1_0__Reg1_1__Mem645_2__ImmUnsignedi81_4
3523 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_95_addImmOperands, 5, CVT_Done },
3524 // Convert__Reg1_4__Reg1_3__Mem645_1__ImmUnsignedi81_0
3525 { CVT_95_Reg, 5, CVT_95_Reg, 4, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3526 // Convert__Reg1_0__Tie0__Reg1_2__Reg1_4__Mem645_5__ImmUnsignedi81_7
3527 { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addMemOperands, 6, CVT_95_addImmOperands, 8, CVT_Done },
3528 // Convert__Reg1_4__Tie0__Reg1_6__Reg1_3__Mem645_1__ImmUnsignedi81_0
3529 { CVT_95_Reg, 5, CVT_Tied, 0, CVT_95_Reg, 7, CVT_95_Reg, 4, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3530 // Convert__Reg1_0__Reg1_2__Reg1_5__Mem645_6__ImmUnsignedi81_8
3531 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_addMemOperands, 7, CVT_95_addImmOperands, 9, CVT_Done },
3532 // Convert__Reg1_4__Reg1_6__Reg1_3__Mem645_1__ImmUnsignedi81_0
3533 { CVT_95_Reg, 5, CVT_95_Reg, 7, CVT_95_Reg, 4, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3534 // Convert__Reg1_0__Reg1_2__Reg1_4__Reg1_5
3535 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_Done },
3536 // Convert__Reg1_0__Reg1_2__Reg1_4__Mem1285_5
3537 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addMemOperands, 6, CVT_Done },
3538 // Convert__Reg1_0__Reg1_2__Reg1_4__Mem2565_5
3539 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addMemOperands, 6, CVT_Done },
3540 // Convert__Reg1_0__Reg1_2__Reg1_4__Mem5125_5
3541 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addMemOperands, 6, CVT_Done },
3542 // Convert__Reg1_0__Reg1_2__Reg1_4__Mem645_5
3543 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addMemOperands, 6, CVT_Done },
3544 // Convert__Reg1_0__Reg1_2__Reg1_4__Mem325_5
3545 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addMemOperands, 6, CVT_Done },
3546 // Convert__Reg1_3__Reg1_2__Reg1_1__Reg1_0
3547 { CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_Reg, 1, CVT_Done },
3548 // Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3
3549 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done },
3550 // Convert__Reg1_0__Reg1_1__Mem1285_2__Reg1_3
3551 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_95_Reg, 4, CVT_Done },
3552 // Convert__Reg1_3__Reg1_2__Mem1285_1__Reg1_0
3553 { CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_Reg, 1, CVT_Done },
3554 // Convert__Reg1_0__Reg1_1__Mem2565_2__Reg1_3
3555 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_95_Reg, 4, CVT_Done },
3556 // Convert__Reg1_3__Reg1_2__Mem2565_1__Reg1_0
3557 { CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_Reg, 1, CVT_Done },
3558 // Convert__Reg1_1__Tie0__Reg1_3__Reg1_0
3559 { CVT_95_Reg, 2, CVT_Tied, 0, CVT_95_Reg, 4, CVT_95_Reg, 1, CVT_Done },
3560 // Convert__Reg1_0__Tie0__Reg1_2__Reg1_4
3561 { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_Done },
3562 // Convert__Reg1_0__Tie0__Reg1_2__Mem645_4
3563 { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_Reg, 3, CVT_95_addMemOperands, 5, CVT_Done },
3564 // Convert__Reg1_1__Tie0__Reg1_3__Mem645_0
3565 { CVT_95_Reg, 2, CVT_Tied, 0, CVT_95_Reg, 4, CVT_95_addMemOperands, 1, CVT_Done },
3566 // Convert__Reg1_1__Reg1_3__Reg1_0
3567 { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_95_Reg, 1, CVT_Done },
3568 // Convert__Reg1_0__Reg1_2__Reg1_5
3569 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_Done },
3570 // Convert__Reg1_0__Reg1_2__Mem645_5
3571 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_addMemOperands, 6, CVT_Done },
3572 // Convert__Reg1_1__Reg1_3__Mem645_0
3573 { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_95_addMemOperands, 1, CVT_Done },
3574 // Convert__Reg1_0__Tie0__Reg1_2__Mem1285_4
3575 { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_Reg, 3, CVT_95_addMemOperands, 5, CVT_Done },
3576 // Convert__Reg1_1__Tie0__Reg1_3__Mem1285_0
3577 { CVT_95_Reg, 2, CVT_Tied, 0, CVT_95_Reg, 4, CVT_95_addMemOperands, 1, CVT_Done },
3578 // Convert__Reg1_0__Reg1_2__Mem1285_5
3579 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_addMemOperands, 6, CVT_Done },
3580 // Convert__Reg1_1__Reg1_3__Mem1285_0
3581 { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_95_addMemOperands, 1, CVT_Done },
3582 // Convert__Reg1_0__Mem2565_1
3583 { CVT_95_Reg, 1, CVT_95_addMemOperands, 2, CVT_Done },
3584 // Convert__Reg1_1__Mem2565_0
3585 { CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_Done },
3586 // Convert__Reg1_0__Tie0__Reg1_2__Mem2565_4
3587 { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_Reg, 3, CVT_95_addMemOperands, 5, CVT_Done },
3588 // Convert__Reg1_1__Tie0__Reg1_3__Mem2565_0
3589 { CVT_95_Reg, 2, CVT_Tied, 0, CVT_95_Reg, 4, CVT_95_addMemOperands, 1, CVT_Done },
3590 // Convert__Reg1_0__Reg1_2__Mem2565_5
3591 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_addMemOperands, 6, CVT_Done },
3592 // Convert__Reg1_1__Reg1_3__Mem2565_0
3593 { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_95_addMemOperands, 1, CVT_Done },
3594 // Convert__Reg1_0__Tie0__Reg1_2__Mem325_4
3595 { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_Reg, 3, CVT_95_addMemOperands, 5, CVT_Done },
3596 // Convert__Reg1_1__Tie0__Reg1_3__Mem325_0
3597 { CVT_95_Reg, 2, CVT_Tied, 0, CVT_95_Reg, 4, CVT_95_addMemOperands, 1, CVT_Done },
3598 // Convert__Reg1_0__Reg1_2__Mem325_5
3599 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_addMemOperands, 6, CVT_Done },
3600 // Convert__Reg1_1__Reg1_3__Mem325_0
3601 { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_95_addMemOperands, 1, CVT_Done },
3602 // Convert__Reg1_2__Reg1_3__Reg1_4__Imm1_0
3603 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 1, CVT_Done },
3604 // Convert__Reg1_2__Reg1_3__Mem1285_4__Imm1_0
3605 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addMemOperands, 5, CVT_95_addImmOperands, 1, CVT_Done },
3606 // Convert__Reg1_2__Reg1_3__Mem2565_4__Imm1_0
3607 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addMemOperands, 5, CVT_95_addImmOperands, 1, CVT_Done },
3608 // Convert__Reg1_2__Reg1_3__Mem5125_4__Imm1_0
3609 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addMemOperands, 5, CVT_95_addImmOperands, 1, CVT_Done },
3610 // Convert__Reg1_4__Reg1_3__Reg1_2__Imm1_0
3611 { CVT_95_Reg, 5, CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_addImmOperands, 1, CVT_Done },
3612 // Convert__Reg1_4__Reg1_3__Mem1285_2__Imm1_0
3613 { CVT_95_Reg, 5, CVT_95_Reg, 4, CVT_95_addMemOperands, 3, CVT_95_addImmOperands, 1, CVT_Done },
3614 // Convert__Reg1_4__Reg1_3__Mem2565_2__Imm1_0
3615 { CVT_95_Reg, 5, CVT_95_Reg, 4, CVT_95_addMemOperands, 3, CVT_95_addImmOperands, 1, CVT_Done },
3616 // Convert__Reg1_4__Reg1_3__Mem5125_2__Imm1_0
3617 { CVT_95_Reg, 5, CVT_95_Reg, 4, CVT_95_addMemOperands, 3, CVT_95_addImmOperands, 1, CVT_Done },
3618 // Convert__Reg1_2__Reg1_3__Mem645_4__Imm1_0
3619 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addMemOperands, 5, CVT_95_addImmOperands, 1, CVT_Done },
3620 // Convert__Reg1_4__Reg1_3__Mem645_2__Imm1_0
3621 { CVT_95_Reg, 5, CVT_95_Reg, 4, CVT_95_addMemOperands, 3, CVT_95_addImmOperands, 1, CVT_Done },
3622 // Convert__Reg1_2__Reg1_3__Mem325_4__Imm1_0
3623 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addMemOperands, 5, CVT_95_addImmOperands, 1, CVT_Done },
3624 // Convert__Reg1_4__Reg1_3__Mem325_2__Imm1_0
3625 { CVT_95_Reg, 5, CVT_95_Reg, 4, CVT_95_addMemOperands, 3, CVT_95_addImmOperands, 1, CVT_Done },
3626 // Convert__Reg1_5__Reg1_4__Reg1_3__Imm1_0
3627 { CVT_95_Reg, 6, CVT_95_Reg, 5, CVT_95_Reg, 4, CVT_95_addImmOperands, 1, CVT_Done },
3628 // Convert__Reg1_5__Reg1_4__Mem645_2__Imm1_0
3629 { CVT_95_Reg, 6, CVT_95_Reg, 5, CVT_95_addMemOperands, 3, CVT_95_addImmOperands, 1, CVT_Done },
3630 // Convert__Reg1_5__Reg1_4__Mem325_2__Imm1_0
3631 { CVT_95_Reg, 6, CVT_95_Reg, 5, CVT_95_addMemOperands, 3, CVT_95_addImmOperands, 1, CVT_Done },
3632 // Convert__Reg1_2__Reg1_4__Reg1_6__Reg1_7__Imm1_0
3633 { CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_Reg, 7, CVT_95_Reg, 8, CVT_95_addImmOperands, 1, CVT_Done },
3634 // Convert__Reg1_2__Reg1_4__Reg1_6__Mem1285_7__Imm1_0
3635 { CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_Reg, 7, CVT_95_addMemOperands, 8, CVT_95_addImmOperands, 1, CVT_Done },
3636 // Convert__Reg1_2__Reg1_4__Reg1_6__Mem2565_7__Imm1_0
3637 { CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_Reg, 7, CVT_95_addMemOperands, 8, CVT_95_addImmOperands, 1, CVT_Done },
3638 // Convert__Reg1_2__Reg1_4__Reg1_6__Mem5125_7__Imm1_0
3639 { CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_Reg, 7, CVT_95_addMemOperands, 8, CVT_95_addImmOperands, 1, CVT_Done },
3640 // Convert__Reg1_4__Reg1_6__Reg1_3__Reg1_2__Imm1_0
3641 { CVT_95_Reg, 5, CVT_95_Reg, 7, CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_addImmOperands, 1, CVT_Done },
3642 // Convert__Reg1_4__Reg1_6__Reg1_3__Mem1285_2__Imm1_0
3643 { CVT_95_Reg, 5, CVT_95_Reg, 7, CVT_95_Reg, 4, CVT_95_addMemOperands, 3, CVT_95_addImmOperands, 1, CVT_Done },
3644 // Convert__Reg1_4__Reg1_6__Reg1_3__Mem2565_2__Imm1_0
3645 { CVT_95_Reg, 5, CVT_95_Reg, 7, CVT_95_Reg, 4, CVT_95_addMemOperands, 3, CVT_95_addImmOperands, 1, CVT_Done },
3646 // Convert__Reg1_4__Reg1_6__Reg1_3__Mem5125_2__Imm1_0
3647 { CVT_95_Reg, 5, CVT_95_Reg, 7, CVT_95_Reg, 4, CVT_95_addMemOperands, 3, CVT_95_addImmOperands, 1, CVT_Done },
3648 // Convert__Reg1_2__Reg1_4__Reg1_6__Mem645_7__Imm1_0
3649 { CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_Reg, 7, CVT_95_addMemOperands, 8, CVT_95_addImmOperands, 1, CVT_Done },
3650 // Convert__Reg1_4__Reg1_6__Reg1_3__Mem645_2__Imm1_0
3651 { CVT_95_Reg, 5, CVT_95_Reg, 7, CVT_95_Reg, 4, CVT_95_addMemOperands, 3, CVT_95_addImmOperands, 1, CVT_Done },
3652 // Convert__Reg1_2__Reg1_4__Reg1_6__Mem325_7__Imm1_0
3653 { CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_Reg, 7, CVT_95_addMemOperands, 8, CVT_95_addImmOperands, 1, CVT_Done },
3654 // Convert__Reg1_4__Reg1_6__Reg1_3__Mem325_2__Imm1_0
3655 { CVT_95_Reg, 5, CVT_95_Reg, 7, CVT_95_Reg, 4, CVT_95_addMemOperands, 3, CVT_95_addImmOperands, 1, CVT_Done },
3656 // Convert__Reg1_5__Reg1_7__Reg1_4__Reg1_3__Imm1_0
3657 { CVT_95_Reg, 6, CVT_95_Reg, 8, CVT_95_Reg, 5, CVT_95_Reg, 4, CVT_95_addImmOperands, 1, CVT_Done },
3658 // Convert__Reg1_5__Reg1_7__Reg1_4__Mem645_2__Imm1_0
3659 { CVT_95_Reg, 6, CVT_95_Reg, 8, CVT_95_Reg, 5, CVT_95_addMemOperands, 3, CVT_95_addImmOperands, 1, CVT_Done },
3660 // Convert__Reg1_5__Reg1_7__Reg1_4__Mem325_2__Imm1_0
3661 { CVT_95_Reg, 6, CVT_95_Reg, 8, CVT_95_Reg, 5, CVT_95_addMemOperands, 3, CVT_95_addImmOperands, 1, CVT_Done },
3662 // Convert__Reg1_0__Reg1_1__Reg1_2__ImmUnsignedi81_4
3663 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 5, CVT_Done },
3664 // Convert__Reg1_4__Reg1_3__Reg1_2__ImmUnsignedi81_0
3665 { CVT_95_Reg, 5, CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_addImmOperands, 1, CVT_Done },
3666 // Convert__Reg1_0__Reg1_2__Reg1_4__Reg1_5__ImmUnsignedi81_6
3667 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_addImmOperands, 7, CVT_Done },
3668 // Convert__Reg1_0__Reg1_2__Reg1_4__Mem1285_5__ImmUnsignedi81_6
3669 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addMemOperands, 6, CVT_95_addImmOperands, 7, CVT_Done },
3670 // Convert__Reg1_0__Reg1_2__Reg1_4__Mem2565_5__ImmUnsignedi81_6
3671 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addMemOperands, 6, CVT_95_addImmOperands, 7, CVT_Done },
3672 // Convert__Reg1_0__Reg1_2__Reg1_4__Mem5125_5__ImmUnsignedi81_6
3673 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addMemOperands, 6, CVT_95_addImmOperands, 7, CVT_Done },
3674 // Convert__Reg1_0__Reg1_2__Reg1_4__Mem645_5__ImmUnsignedi81_7
3675 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addMemOperands, 6, CVT_95_addImmOperands, 8, CVT_Done },
3676 // Convert__Reg1_0__Reg1_2__Reg1_4__Reg1_5__ImmUnsignedi81_7
3677 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_addImmOperands, 8, CVT_Done },
3678 // Convert__Reg1_4__Reg1_6__Reg1_3__Reg1_2__ImmUnsignedi81_0
3679 { CVT_95_Reg, 5, CVT_95_Reg, 7, CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_addImmOperands, 1, CVT_Done },
3680 // Convert__Reg1_0__Reg1_2__Reg1_4__Mem325_5__ImmUnsignedi81_7
3681 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addMemOperands, 6, CVT_95_addImmOperands, 8, CVT_Done },
3682 // Convert__Reg1_0__Reg1_1__Mem645_2__ImmUnsignedi81_3
3683 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
3684 // Convert__Reg1_3__Reg1_2__Mem645_1__ImmUnsignedi81_0
3685 { CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3686 // Convert__Reg1_0__Reg1_2__Reg1_4__Mem645_5__ImmUnsignedi81_6
3687 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addMemOperands, 6, CVT_95_addImmOperands, 7, CVT_Done },
3688 // Convert__Reg1_3__Reg1_5__Reg1_2__Mem645_1__ImmUnsignedi81_0
3689 { CVT_95_Reg, 4, CVT_95_Reg, 6, CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3690 // Convert__Reg1_0__Reg1_1__Mem325_2__ImmUnsignedi81_3
3691 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
3692 // Convert__Reg1_3__Reg1_2__Mem325_1__ImmUnsignedi81_0
3693 { CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3694 // Convert__Reg1_0__Reg1_2__Reg1_4__Mem325_5__ImmUnsignedi81_6
3695 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addMemOperands, 6, CVT_95_addImmOperands, 7, CVT_Done },
3696 // Convert__Reg1_3__Reg1_5__Reg1_2__Mem325_1__ImmUnsignedi81_0
3697 { CVT_95_Reg, 4, CVT_95_Reg, 6, CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3698 // Convert__Reg1_2__Reg1_1
3699 { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_Done },
3700 // Convert__Mem2565_1__Reg1_0
3701 { CVT_95_addMemOperands, 2, CVT_95_Reg, 1, CVT_Done },
3702 // Convert__Mem5125_1__Reg1_0
3703 { CVT_95_addMemOperands, 2, CVT_95_Reg, 1, CVT_Done },
3704 // Convert__Mem2565_0__Reg1_1
3705 { CVT_95_addMemOperands, 1, CVT_95_Reg, 2, CVT_Done },
3706 // Convert__Mem5125_0__Reg1_1
3707 { CVT_95_addMemOperands, 1, CVT_95_Reg, 2, CVT_Done },
3708 // Convert__Mem1285_1__Reg1_3__Reg1_0
3709 { CVT_95_addMemOperands, 2, CVT_95_Reg, 4, CVT_95_Reg, 1, CVT_Done },
3710 // Convert__Mem2565_1__Reg1_3__Reg1_0
3711 { CVT_95_addMemOperands, 2, CVT_95_Reg, 4, CVT_95_Reg, 1, CVT_Done },
3712 // Convert__Mem5125_1__Reg1_3__Reg1_0
3713 { CVT_95_addMemOperands, 2, CVT_95_Reg, 4, CVT_95_Reg, 1, CVT_Done },
3714 // Convert__Mem1285_0__Reg1_2__Reg1_4
3715 { CVT_95_addMemOperands, 1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_Done },
3716 // Convert__Mem2565_0__Reg1_2__Reg1_4
3717 { CVT_95_addMemOperands, 1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_Done },
3718 // Convert__Mem5125_0__Reg1_2__Reg1_4
3719 { CVT_95_addMemOperands, 1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_Done },
3720 // Convert__Reg1_2__Mem325_0
3721 { CVT_95_Reg, 3, CVT_95_addMemOperands, 1, CVT_Done },
3722 // Convert__Reg1_2__Tie0__Reg1_4__Mem325_0
3723 { CVT_95_Reg, 3, CVT_Tied, 0, CVT_95_Reg, 5, CVT_95_addMemOperands, 1, CVT_Done },
3724 // Convert__Reg1_2__Reg1_4__Mem325_0
3725 { CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addMemOperands, 1, CVT_Done },
3726 // Convert__Reg1_0__Mem5125_1
3727 { CVT_95_Reg, 1, CVT_95_addMemOperands, 2, CVT_Done },
3728 // Convert__Reg1_1__Mem5125_0
3729 { CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_Done },
3730 // Convert__Reg1_0__Reg1_1__AVX512RC1_2
3731 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addAVX512RCOperands, 3, CVT_Done },
3732 // Convert__Reg1_2__Reg1_1__AVX512RC1_0
3733 { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addAVX512RCOperands, 1, CVT_Done },
3734 // Convert__Reg1_0__Tie0__Reg1_2__Mem5125_4
3735 { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_Reg, 3, CVT_95_addMemOperands, 5, CVT_Done },
3736 // Convert__Reg1_1__Tie0__Reg1_3__Mem5125_0
3737 { CVT_95_Reg, 2, CVT_Tied, 0, CVT_95_Reg, 4, CVT_95_addMemOperands, 1, CVT_Done },
3738 // Convert__Reg1_0__Reg1_2__Mem5125_5
3739 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_addMemOperands, 6, CVT_Done },
3740 // Convert__Reg1_0__Tie0__Reg1_2__Reg1_4__AVX512RC1_5
3741 { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addAVX512RCOperands, 6, CVT_Done },
3742 // Convert__Reg1_2__Tie0__Reg1_4__Reg1_1__AVX512RC1_0
3743 { CVT_95_Reg, 3, CVT_Tied, 0, CVT_95_Reg, 5, CVT_95_Reg, 2, CVT_95_addAVX512RCOperands, 1, CVT_Done },
3744 // Convert__Reg1_1__Reg1_3__Mem5125_0
3745 { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_95_addMemOperands, 1, CVT_Done },
3746 // Convert__Reg1_0__Reg1_2__Reg1_5__AVX512RC1_6
3747 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_addAVX512RCOperands, 7, CVT_Done },
3748 // Convert__Reg1_2__Reg1_4__Reg1_1__AVX512RC1_0
3749 { CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_Reg, 2, CVT_95_addAVX512RCOperands, 1, CVT_Done },
3750 // Convert__Reg1_2__Mem645_0
3751 { CVT_95_Reg, 3, CVT_95_addMemOperands, 1, CVT_Done },
3752 // Convert__Reg1_2__Tie0__Reg1_4__Mem645_0
3753 { CVT_95_Reg, 3, CVT_Tied, 0, CVT_95_Reg, 5, CVT_95_addMemOperands, 1, CVT_Done },
3754 // Convert__Reg1_2__Reg1_4__Mem645_0
3755 { CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addMemOperands, 1, CVT_Done },
3756 // Convert__Reg1_2__Tie0__Reg1_4__Reg1_1
3757 { CVT_95_Reg, 3, CVT_Tied, 0, CVT_95_Reg, 5, CVT_95_Reg, 2, CVT_Done },
3758 // Convert__Reg1_2__Reg1_4__Reg1_1
3759 { CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_Reg, 2, CVT_Done },
3760 // Convert__Mem1285_2__Reg1_1__ImmUnsignedi81_0
3761 { CVT_95_addMemOperands, 3, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
3762 // Convert__Mem2565_2__Reg1_1__ImmUnsignedi81_0
3763 { CVT_95_addMemOperands, 3, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
3764 // Convert__Mem1285_0__Reg1_1__ImmUnsignedi81_2
3765 { CVT_95_addMemOperands, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
3766 // Convert__Mem2565_0__Reg1_1__ImmUnsignedi81_2
3767 { CVT_95_addMemOperands, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
3768 // Convert__Reg1_0__Reg1_1__ImmUnsignedi81_3
3769 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 4, CVT_Done },
3770 // Convert__Reg1_3__Reg1_2__ImmUnsignedi81_0
3771 { CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_addImmOperands, 1, CVT_Done },
3772 // Convert__Reg1_0__Tie0__Reg1_2__Reg1_4__ImmUnsignedi81_5
3773 { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_Done },
3774 // Convert__Reg1_2__Tie0__Reg1_4__Reg1_1__ImmUnsignedi81_0
3775 { CVT_95_Reg, 3, CVT_Tied, 0, CVT_95_Reg, 5, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
3776 // Convert__Mem645_2__Reg1_4__Reg1_1__ImmUnsignedi81_0
3777 { CVT_95_addMemOperands, 3, CVT_95_Reg, 5, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
3778 // Convert__Mem1285_2__Reg1_4__Reg1_1__ImmUnsignedi81_0
3779 { CVT_95_addMemOperands, 3, CVT_95_Reg, 5, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
3780 // Convert__Mem2565_2__Reg1_4__Reg1_1__ImmUnsignedi81_0
3781 { CVT_95_addMemOperands, 3, CVT_95_Reg, 5, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
3782 // Convert__Mem1285_0__Reg1_2__Reg1_4__ImmUnsignedi81_5
3783 { CVT_95_addMemOperands, 1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_Done },
3784 // Convert__Mem2565_0__Reg1_2__Reg1_4__ImmUnsignedi81_5
3785 { CVT_95_addMemOperands, 1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_Done },
3786 // Convert__Mem645_0__Reg1_2__Reg1_4__ImmUnsignedi81_5
3787 { CVT_95_addMemOperands, 1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_Done },
3788 // Convert__Reg1_0__Reg1_2__Reg1_5__ImmUnsignedi81_6
3789 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_addImmOperands, 7, CVT_Done },
3790 // Convert__Reg1_0__Tie0__Reg1_2__Reg1_4__ImmUnsignedi81_6
3791 { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addImmOperands, 7, CVT_Done },
3792 // Convert__Reg1_3__Tie0__Reg1_5__Reg1_2__ImmUnsignedi81_0
3793 { CVT_95_Reg, 4, CVT_Tied, 0, CVT_95_Reg, 6, CVT_95_Reg, 3, CVT_95_addImmOperands, 1, CVT_Done },
3794 // Convert__Reg1_2__Reg1_4__Reg1_1__ImmUnsignedi81_0
3795 { CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
3796 // Convert__Reg1_0__Reg1_2__Reg1_5__ImmUnsignedi81_7
3797 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_addImmOperands, 8, CVT_Done },
3798 // Convert__Reg1_3__Reg1_5__Reg1_2__ImmUnsignedi81_0
3799 { CVT_95_Reg, 4, CVT_95_Reg, 6, CVT_95_Reg, 3, CVT_95_addImmOperands, 1, CVT_Done },
3800 // Convert__Reg1_0__Reg1_1__Reg1_3__AVX512RC1_2
3801 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_95_addAVX512RCOperands, 3, CVT_Done },
3802 // Convert__Reg1_3__Reg1_2__Reg1_0__AVX512RC1_1
3803 { CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_addAVX512RCOperands, 2, CVT_Done },
3804 // Convert__Reg1_3__Reg1_2__Reg1_1
3805 { CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_Done },
3806 // Convert__Reg1_3__Tie0__Reg1_5__Reg1_2__Reg1_1
3807 { CVT_95_Reg, 4, CVT_Tied, 0, CVT_95_Reg, 6, CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_Done },
3808 // Convert__Reg1_3__Reg1_5__Reg1_2__Reg1_1
3809 { CVT_95_Reg, 4, CVT_95_Reg, 6, CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_Done },
3810 // Convert__Reg1_0__Tie0__Reg1_1__Reg1_2__ImmUnsignedi81_3
3811 { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
3812 // Convert__Reg1_0__Tie0__Reg1_1__Mem1285_2__ImmUnsignedi81_3
3813 { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
3814 // Convert__Reg1_0__Tie0__Reg1_1__Mem2565_2__ImmUnsignedi81_3
3815 { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
3816 // Convert__Reg1_0__Tie0__Reg1_1__Mem5125_2__ImmUnsignedi81_3
3817 { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
3818 // Convert__Reg1_3__Tie0__Reg1_2__Reg1_1__ImmUnsignedi81_0
3819 { CVT_95_Reg, 4, CVT_Tied, 0, CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
3820 // Convert__Reg1_3__Tie0__Reg1_2__Mem1285_1__ImmUnsignedi81_0
3821 { CVT_95_Reg, 4, CVT_Tied, 0, CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3822 // Convert__Reg1_3__Tie0__Reg1_2__Mem2565_1__ImmUnsignedi81_0
3823 { CVT_95_Reg, 4, CVT_Tied, 0, CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3824 // Convert__Reg1_3__Tie0__Reg1_2__Mem5125_1__ImmUnsignedi81_0
3825 { CVT_95_Reg, 4, CVT_Tied, 0, CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3826 // Convert__Reg1_0__Tie0__Reg1_1__Mem645_2__ImmUnsignedi81_4
3827 { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_95_addImmOperands, 5, CVT_Done },
3828 // Convert__Reg1_0__Tie0__Reg1_1__Reg1_2__ImmUnsignedi81_4
3829 { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 5, CVT_Done },
3830 // Convert__Reg1_4__Tie0__Reg1_3__Reg1_2__ImmUnsignedi81_0
3831 { CVT_95_Reg, 5, CVT_Tied, 0, CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_addImmOperands, 1, CVT_Done },
3832 // Convert__Reg1_4__Tie0__Reg1_3__Mem645_1__ImmUnsignedi81_0
3833 { CVT_95_Reg, 5, CVT_Tied, 0, CVT_95_Reg, 4, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3834 // Convert__Reg1_0__Tie0__Reg1_2__Reg1_5__Reg1_6__ImmUnsignedi81_7
3835 { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_Reg, 7, CVT_95_addImmOperands, 8, CVT_Done },
3836 // Convert__Reg1_0__Tie0__Reg1_2__Reg1_5__Mem1285_6__ImmUnsignedi81_7
3837 { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_addMemOperands, 7, CVT_95_addImmOperands, 8, CVT_Done },
3838 // Convert__Reg1_0__Tie0__Reg1_2__Reg1_5__Mem2565_6__ImmUnsignedi81_7
3839 { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_addMemOperands, 7, CVT_95_addImmOperands, 8, CVT_Done },
3840 // Convert__Reg1_0__Tie0__Reg1_2__Reg1_5__Mem5125_6__ImmUnsignedi81_7
3841 { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_addMemOperands, 7, CVT_95_addImmOperands, 8, CVT_Done },
3842 // Convert__Reg1_0__Tie0__Reg1_2__Reg1_4__Reg1_5__ImmUnsignedi81_7
3843 { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_addImmOperands, 8, CVT_Done },
3844 // Convert__Reg1_4__Tie0__Reg1_6__Reg1_3__Reg1_2__ImmUnsignedi81_0
3845 { CVT_95_Reg, 5, CVT_Tied, 0, CVT_95_Reg, 7, CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_addImmOperands, 1, CVT_Done },
3846 // Convert__Reg1_0__Tie0__Reg1_2__Reg1_5__Mem645_6__ImmUnsignedi81_8
3847 { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_addMemOperands, 7, CVT_95_addImmOperands, 9, CVT_Done },
3848 // Convert__Reg1_0__Tie0__Reg1_2__Reg1_5__Reg1_6__ImmUnsignedi81_8
3849 { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_Reg, 7, CVT_95_addImmOperands, 9, CVT_Done },
3850 // Convert__Reg1_0__Tie0__Reg1_1__Mem325_2__ImmUnsignedi81_4
3851 { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_95_addImmOperands, 5, CVT_Done },
3852 // Convert__Reg1_4__Tie0__Reg1_3__Mem325_1__ImmUnsignedi81_0
3853 { CVT_95_Reg, 5, CVT_Tied, 0, CVT_95_Reg, 4, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3854 // Convert__Reg1_0__Tie0__Reg1_2__Reg1_5__Mem325_6__ImmUnsignedi81_8
3855 { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_addMemOperands, 7, CVT_95_addImmOperands, 9, CVT_Done },
3856 // Convert__Reg1_0__Tie0__Reg1_1__Mem645_2__ImmUnsignedi81_3
3857 { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
3858 // Convert__Reg1_3__Tie0__Reg1_2__Mem645_1__ImmUnsignedi81_0
3859 { CVT_95_Reg, 4, CVT_Tied, 0, CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3860 // Convert__Reg1_0__Tie0__Reg1_2__Reg1_4__Mem645_5__ImmUnsignedi81_6
3861 { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addMemOperands, 6, CVT_95_addImmOperands, 7, CVT_Done },
3862 // Convert__Reg1_3__Tie0__Reg1_5__Reg1_2__Mem645_1__ImmUnsignedi81_0
3863 { CVT_95_Reg, 4, CVT_Tied, 0, CVT_95_Reg, 6, CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3864 // Convert__Reg1_0__Tie0__Reg1_2__Reg1_5__Mem645_6__ImmUnsignedi81_7
3865 { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_addMemOperands, 7, CVT_95_addImmOperands, 8, CVT_Done },
3866 // Convert__Reg1_0__Tie0__Reg1_1__Mem325_2__ImmUnsignedi81_3
3867 { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
3868 // Convert__Reg1_3__Tie0__Reg1_2__Mem325_1__ImmUnsignedi81_0
3869 { CVT_95_Reg, 4, CVT_Tied, 0, CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3870 // Convert__Reg1_0__Tie0__Reg1_2__Reg1_4__Mem325_5__ImmUnsignedi81_6
3871 { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addMemOperands, 6, CVT_95_addImmOperands, 7, CVT_Done },
3872 // Convert__Reg1_3__Tie0__Reg1_5__Reg1_2__Mem325_1__ImmUnsignedi81_0
3873 { CVT_95_Reg, 4, CVT_Tied, 0, CVT_95_Reg, 6, CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3874 // Convert__Reg1_0__Tie0__Reg1_2__Reg1_5__Mem325_6__ImmUnsignedi81_7
3875 { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_addMemOperands, 7, CVT_95_addImmOperands, 8, CVT_Done },
3876 // Convert__Reg1_2__Tie0__Reg1_1__Reg1_0
3877 { CVT_95_Reg, 3, CVT_Tied, 0, CVT_95_Reg, 2, CVT_95_Reg, 1, CVT_Done },
3878 // Convert__Reg1_0__Tie0__Reg1_1__Reg1_2
3879 { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
3880 // Convert__Reg1_0__Tie0__Reg1_1__Mem1285_2
3881 { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_Done },
3882 // Convert__Reg1_0__Tie0__Reg1_1__Mem2565_2
3883 { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_Done },
3884 // Convert__Reg1_0__Tie0__Reg1_1__Mem5125_2
3885 { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_Done },
3886 // Convert__Reg1_2__Tie0__Reg1_1__Mem1285_0
3887 { CVT_95_Reg, 3, CVT_Tied, 0, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_Done },
3888 // Convert__Reg1_2__Tie0__Reg1_1__Mem2565_0
3889 { CVT_95_Reg, 3, CVT_Tied, 0, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_Done },
3890 // Convert__Reg1_2__Tie0__Reg1_1__Mem5125_0
3891 { CVT_95_Reg, 3, CVT_Tied, 0, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_Done },
3892 // Convert__Reg1_0__Tie0__Reg1_1__Mem645_2
3893 { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_Done },
3894 // Convert__Reg1_0__Tie0__Reg1_1__Reg1_2__AVX512RC1_3
3895 { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addAVX512RCOperands, 4, CVT_Done },
3896 // Convert__Reg1_3__Tie0__Reg1_2__Reg1_1__AVX512RC1_0
3897 { CVT_95_Reg, 4, CVT_Tied, 0, CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addAVX512RCOperands, 1, CVT_Done },
3898 // Convert__Reg1_3__Tie0__Reg1_2__Mem645_0
3899 { CVT_95_Reg, 4, CVT_Tied, 0, CVT_95_Reg, 3, CVT_95_addMemOperands, 1, CVT_Done },
3900 // Convert__Reg1_0__Tie0__Reg1_2__Reg1_5__Reg1_6
3901 { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_Reg, 7, CVT_Done },
3902 // Convert__Reg1_0__Tie0__Reg1_2__Reg1_5__Mem1285_6
3903 { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_addMemOperands, 7, CVT_Done },
3904 // Convert__Reg1_0__Tie0__Reg1_2__Reg1_5__Mem2565_6
3905 { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_addMemOperands, 7, CVT_Done },
3906 // Convert__Reg1_0__Tie0__Reg1_2__Reg1_5__Mem5125_6
3907 { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_addMemOperands, 7, CVT_Done },
3908 // Convert__Reg1_0__Tie0__Reg1_2__Reg1_5__Mem645_6
3909 { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_addMemOperands, 7, CVT_Done },
3910 // Convert__Reg1_0__Tie0__Reg1_2__Reg1_5__Reg1_6__AVX512RC1_7
3911 { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_Reg, 7, CVT_95_addAVX512RCOperands, 8, CVT_Done },
3912 // Convert__Reg1_0__Tie0__Reg1_1__Mem325_2
3913 { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_Done },
3914 // Convert__Reg1_3__Tie0__Reg1_2__Mem325_0
3915 { CVT_95_Reg, 4, CVT_Tied, 0, CVT_95_Reg, 3, CVT_95_addMemOperands, 1, CVT_Done },
3916 // Convert__Reg1_0__Tie0__Reg1_2__Reg1_5__Mem325_6
3917 { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_addMemOperands, 7, CVT_Done },
3918 // Convert__Reg1_2__Tie0__Reg1_1__Mem645_0
3919 { CVT_95_Reg, 3, CVT_Tied, 0, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_Done },
3920 // Convert__Reg1_2__Tie0__Reg1_1__Mem325_0
3921 { CVT_95_Reg, 3, CVT_Tied, 0, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_Done },
3922 // Convert__Reg1_0__Reg1_1__Reg1_2__Mem1285_3
3923 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addMemOperands, 4, CVT_Done },
3924 // Convert__Reg1_0__Reg1_1__Reg1_2__Mem2565_3
3925 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addMemOperands, 4, CVT_Done },
3926 // Convert__Reg1_3__Reg1_2__Reg1_1__Mem1285_0
3927 { CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_Done },
3928 // Convert__Reg1_3__Reg1_2__Reg1_1__Mem2565_0
3929 { CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_Done },
3930 // Convert__Reg1_0__Reg1_1__Reg1_2__Mem645_3
3931 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addMemOperands, 4, CVT_Done },
3932 // Convert__Reg1_0__Reg1_1__Mem645_2__Reg1_3
3933 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_95_Reg, 4, CVT_Done },
3934 // Convert__Reg1_3__Reg1_2__Mem645_1__Reg1_0
3935 { CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_Reg, 1, CVT_Done },
3936 // Convert__Reg1_3__Reg1_2__Reg1_1__Mem645_0
3937 { CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_Done },
3938 // Convert__Reg1_0__Reg1_1__Reg1_2__Mem325_3
3939 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addMemOperands, 4, CVT_Done },
3940 // Convert__Reg1_0__Reg1_1__Mem325_2__Reg1_3
3941 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_95_Reg, 4, CVT_Done },
3942 // Convert__Reg1_3__Reg1_2__Mem325_1__Reg1_0
3943 { CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_Reg, 1, CVT_Done },
3944 // Convert__Reg1_3__Reg1_2__Reg1_1__Mem325_0
3945 { CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_Done },
3946 // Convert__Reg1_0__Mem2565_1__ImmUnsignedi81_2
3947 { CVT_95_Reg, 1, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
3948 // Convert__Reg1_0__Mem5125_1__ImmUnsignedi81_2
3949 { CVT_95_Reg, 1, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
3950 // Convert__Reg1_0__Mem645_1__ImmUnsignedi81_3
3951 { CVT_95_Reg, 1, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 4, CVT_Done },
3952 // Convert__Reg1_0__Reg1_2__Reg1_4__ImmUnsignedi81_5
3953 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_Done },
3954 // Convert__Reg1_0__Reg1_2__Mem1285_4__ImmUnsignedi81_5
3955 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_addMemOperands, 5, CVT_95_addImmOperands, 6, CVT_Done },
3956 // Convert__Reg1_0__Reg1_2__Mem2565_4__ImmUnsignedi81_5
3957 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_addMemOperands, 5, CVT_95_addImmOperands, 6, CVT_Done },
3958 // Convert__Reg1_0__Reg1_2__Mem5125_4__ImmUnsignedi81_5
3959 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_addMemOperands, 5, CVT_95_addImmOperands, 6, CVT_Done },
3960 // Convert__Reg1_0__Reg1_2__Mem645_4__ImmUnsignedi81_6
3961 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_addMemOperands, 5, CVT_95_addImmOperands, 7, CVT_Done },
3962 // Convert__Reg1_3__Mem645_1__ImmUnsignedi81_0
3963 { CVT_95_Reg, 4, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3964 // Convert__Reg1_3__Reg1_5__Mem645_1__ImmUnsignedi81_0
3965 { CVT_95_Reg, 4, CVT_95_Reg, 6, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3966 // Convert__Reg1_2__Reg1_4__Mem1285_1__ImmUnsignedi81_0
3967 { CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3968 // Convert__Reg1_2__Mem2565_1__ImmUnsignedi81_0
3969 { CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3970 // Convert__Reg1_2__Reg1_4__Mem2565_1__ImmUnsignedi81_0
3971 { CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3972 // Convert__Reg1_2__Mem5125_1__ImmUnsignedi81_0
3973 { CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3974 // Convert__Reg1_2__Reg1_4__Mem5125_1__ImmUnsignedi81_0
3975 { CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3976 // Convert__Reg1_0__Mem325_1__ImmUnsignedi81_3
3977 { CVT_95_Reg, 1, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 4, CVT_Done },
3978 // Convert__Reg1_0__Reg1_2__Mem325_4__ImmUnsignedi81_6
3979 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_addMemOperands, 5, CVT_95_addImmOperands, 7, CVT_Done },
3980 // Convert__Reg1_3__Mem325_1__ImmUnsignedi81_0
3981 { CVT_95_Reg, 4, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3982 // Convert__Reg1_3__Reg1_5__Mem325_1__ImmUnsignedi81_0
3983 { CVT_95_Reg, 4, CVT_95_Reg, 6, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3984 // Convert__Reg1_0__Reg1_2__Mem645_4__ImmUnsignedi81_5
3985 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_addMemOperands, 5, CVT_95_addImmOperands, 6, CVT_Done },
3986 // Convert__Reg1_2__Reg1_4__Mem645_1__ImmUnsignedi81_0
3987 { CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3988 // Convert__Reg1_0__Reg1_2__Mem325_4__ImmUnsignedi81_5
3989 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_addMemOperands, 5, CVT_95_addImmOperands, 6, CVT_Done },
3990 // Convert__Reg1_2__Reg1_4__Mem325_1__ImmUnsignedi81_0
3991 { CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3992 // Convert__Reg1_2__Reg1_0__Tie0__Mem128_RC1285_1__Tie1
3993 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_addMemOperands, 2, CVT_Tied, 1, CVT_Done },
3994 // Convert__Reg1_0__Reg1_2__Tie0__Mem128_RC1285_1__Tie1
3995 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_Tied, 0, CVT_95_addMemOperands, 2, CVT_Tied, 1, CVT_Done },
3996 // Convert__Reg1_2__Reg1_0__Tie0__Mem256_RC1285_1__Tie1
3997 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_addMemOperands, 2, CVT_Tied, 1, CVT_Done },
3998 // Convert__Reg1_0__Reg1_2__Tie0__Mem256_RC1285_1__Tie1
3999 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_Tied, 0, CVT_95_addMemOperands, 2, CVT_Tied, 1, CVT_Done },
4000 // Convert__Reg1_0__Reg1_2__Tie0__Tie1__Mem128_RC128X5_4
4001 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_Tied, 0, CVT_Tied, 1, CVT_95_addMemOperands, 5, CVT_Done },
4002 // Convert__Reg1_0__Reg1_2__Tie0__Tie1__Mem256_RC128X5_4
4003 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_Tied, 0, CVT_Tied, 1, CVT_95_addMemOperands, 5, CVT_Done },
4004 // Convert__Reg1_0__Reg1_2__Tie0__Tie1__Mem512_RC256X5_4
4005 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_Tied, 0, CVT_Tied, 1, CVT_95_addMemOperands, 5, CVT_Done },
4006 // Convert__Reg1_1__Reg1_3__Tie0__Tie1__Mem128_RC128X5_0
4007 { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_Tied, 0, CVT_Tied, 1, CVT_95_addMemOperands, 1, CVT_Done },
4008 // Convert__Reg1_1__Reg1_3__Tie0__Tie1__Mem256_RC128X5_0
4009 { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_Tied, 0, CVT_Tied, 1, CVT_95_addMemOperands, 1, CVT_Done },
4010 // Convert__Reg1_1__Reg1_3__Tie0__Tie1__Mem512_RC256X5_0
4011 { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_Tied, 0, CVT_Tied, 1, CVT_95_addMemOperands, 1, CVT_Done },
4012 // Convert__Reg1_2__Reg1_0__Tie0__Mem256_RC2565_1__Tie1
4013 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_addMemOperands, 2, CVT_Tied, 1, CVT_Done },
4014 // Convert__Reg1_0__Reg1_2__Tie0__Mem256_RC2565_1__Tie1
4015 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_Tied, 0, CVT_95_addMemOperands, 2, CVT_Tied, 1, CVT_Done },
4016 // Convert__Reg1_0__Reg1_2__Tie0__Tie1__Mem256_RC256X5_4
4017 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_Tied, 0, CVT_Tied, 1, CVT_95_addMemOperands, 5, CVT_Done },
4018 // Convert__Reg1_0__Reg1_2__Tie0__Tie1__Mem512_RC5125_4
4019 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_Tied, 0, CVT_Tied, 1, CVT_95_addMemOperands, 5, CVT_Done },
4020 // Convert__Reg1_1__Reg1_3__Tie0__Tie1__Mem256_RC256X5_0
4021 { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_Tied, 0, CVT_Tied, 1, CVT_95_addMemOperands, 1, CVT_Done },
4022 // Convert__Reg1_1__Reg1_3__Tie0__Tie1__Mem512_RC5125_0
4023 { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_Tied, 0, CVT_Tied, 1, CVT_95_addMemOperands, 1, CVT_Done },
4024 // Convert__Reg1_1__Mem512_RC256X5_3
4025 { CVT_95_Reg, 2, CVT_95_addMemOperands, 4, CVT_Done },
4026 // Convert__Reg1_2__Mem512_RC256X5_0
4027 { CVT_95_Reg, 3, CVT_95_addMemOperands, 1, CVT_Done },
4028 // Convert__Reg1_1__Mem512_RC5125_3
4029 { CVT_95_Reg, 2, CVT_95_addMemOperands, 4, CVT_Done },
4030 // Convert__Reg1_2__Mem512_RC5125_0
4031 { CVT_95_Reg, 3, CVT_95_addMemOperands, 1, CVT_Done },
4032 // Convert__Reg1_1__Mem256_RC5125_3
4033 { CVT_95_Reg, 2, CVT_95_addMemOperands, 4, CVT_Done },
4034 // Convert__Reg1_2__Mem256_RC5125_0
4035 { CVT_95_Reg, 3, CVT_95_addMemOperands, 1, CVT_Done },
4036 // Convert__Reg1_2__Reg1_0__Tie0__Mem128_RC2565_1__Tie1
4037 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_addMemOperands, 2, CVT_Tied, 1, CVT_Done },
4038 // Convert__Reg1_0__Reg1_2__Tie0__Mem128_RC2565_1__Tie1
4039 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_Tied, 0, CVT_95_addMemOperands, 2, CVT_Tied, 1, CVT_Done },
4040 // Convert__Reg1_2__Reg1_0__Tie0__Mem64_RC1285_1__Tie1
4041 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_addMemOperands, 2, CVT_Tied, 1, CVT_Done },
4042 // Convert__Reg1_0__Reg1_2__Tie0__Mem64_RC1285_1__Tie1
4043 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_Tied, 0, CVT_95_addMemOperands, 2, CVT_Tied, 1, CVT_Done },
4044 // Convert__Reg1_0__Reg1_2__Tie0__Tie1__Mem128_RC256X5_4
4045 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_Tied, 0, CVT_Tied, 1, CVT_95_addMemOperands, 5, CVT_Done },
4046 // Convert__Reg1_0__Reg1_2__Tie0__Tie1__Mem64_RC128X5_4
4047 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_Tied, 0, CVT_Tied, 1, CVT_95_addMemOperands, 5, CVT_Done },
4048 // Convert__Reg1_0__Reg1_2__Tie0__Tie1__Mem256_RC5125_4
4049 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_Tied, 0, CVT_Tied, 1, CVT_95_addMemOperands, 5, CVT_Done },
4050 // Convert__Reg1_1__Reg1_3__Tie0__Tie1__Mem128_RC256X5_0
4051 { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_Tied, 0, CVT_Tied, 1, CVT_95_addMemOperands, 1, CVT_Done },
4052 // Convert__Reg1_1__Reg1_3__Tie0__Tie1__Mem256_RC5125_0
4053 { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_Tied, 0, CVT_Tied, 1, CVT_95_addMemOperands, 1, CVT_Done },
4054 // Convert__Reg1_1__Reg1_3__Tie0__Tie1__Mem64_RC128X5_0
4055 { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_Tied, 0, CVT_Tied, 1, CVT_95_addMemOperands, 1, CVT_Done },
4056 // Convert__Reg1_0__Tie0__Reg1_2__Mem1285_4__ImmUnsignedi81_5
4057 { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_Reg, 3, CVT_95_addMemOperands, 5, CVT_95_addImmOperands, 6, CVT_Done },
4058 // Convert__Reg1_0__Tie0__Reg1_2__Mem2565_4__ImmUnsignedi81_5
4059 { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_Reg, 3, CVT_95_addMemOperands, 5, CVT_95_addImmOperands, 6, CVT_Done },
4060 // Convert__Reg1_0__Tie0__Reg1_2__Mem5125_4__ImmUnsignedi81_5
4061 { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_Reg, 3, CVT_95_addMemOperands, 5, CVT_95_addImmOperands, 6, CVT_Done },
4062 // Convert__Reg1_2__Tie0__Reg1_4__Mem1285_1__ImmUnsignedi81_0
4063 { CVT_95_Reg, 3, CVT_Tied, 0, CVT_95_Reg, 5, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
4064 // Convert__Reg1_2__Tie0__Reg1_4__Mem2565_1__ImmUnsignedi81_0
4065 { CVT_95_Reg, 3, CVT_Tied, 0, CVT_95_Reg, 5, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
4066 // Convert__Reg1_2__Tie0__Reg1_4__Mem5125_1__ImmUnsignedi81_0
4067 { CVT_95_Reg, 3, CVT_Tied, 0, CVT_95_Reg, 5, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
4068 // Convert__Reg1_0__Reg1_2__Mem1285_5__ImmUnsignedi81_6
4069 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_addMemOperands, 6, CVT_95_addImmOperands, 7, CVT_Done },
4070 // Convert__Reg1_0__Tie0__Reg1_2__Mem645_4__ImmUnsignedi81_6
4071 { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_Reg, 3, CVT_95_addMemOperands, 5, CVT_95_addImmOperands, 7, CVT_Done },
4072 // Convert__Reg1_0__Reg1_2__Mem2565_5__ImmUnsignedi81_6
4073 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_addMemOperands, 6, CVT_95_addImmOperands, 7, CVT_Done },
4074 // Convert__Reg1_0__Reg1_2__Mem5125_5__ImmUnsignedi81_6
4075 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_addMemOperands, 6, CVT_95_addImmOperands, 7, CVT_Done },
4076 // Convert__Reg1_3__Tie0__Reg1_5__Mem645_1__ImmUnsignedi81_0
4077 { CVT_95_Reg, 4, CVT_Tied, 0, CVT_95_Reg, 6, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
4078 // Convert__Reg1_0__Reg1_2__Mem645_5__ImmUnsignedi81_7
4079 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_addMemOperands, 6, CVT_95_addImmOperands, 8, CVT_Done },
4080 // Convert__Reg1_0__Tie0__Reg1_2__Mem325_4__ImmUnsignedi81_6
4081 { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_Reg, 3, CVT_95_addMemOperands, 5, CVT_95_addImmOperands, 7, CVT_Done },
4082 // Convert__Reg1_3__Tie0__Reg1_5__Mem325_1__ImmUnsignedi81_0
4083 { CVT_95_Reg, 4, CVT_Tied, 0, CVT_95_Reg, 6, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
4084 // Convert__Reg1_0__Reg1_2__Mem325_5__ImmUnsignedi81_7
4085 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_addMemOperands, 6, CVT_95_addImmOperands, 8, CVT_Done },
4086 // Convert__Reg1_0__Reg1_2__Reg1_5__Mem645_6__ImmUnsignedi81_7
4087 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_addMemOperands, 7, CVT_95_addImmOperands, 8, CVT_Done },
4088 // Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6__ImmUnsignedi81_8
4089 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_Reg, 7, CVT_95_addImmOperands, 9, CVT_Done },
4090 // Convert__Reg1_0__Reg1_2__Reg1_5__Mem325_6__ImmUnsignedi81_7
4091 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_addMemOperands, 7, CVT_95_addImmOperands, 8, CVT_Done },
4092 // Convert__Reg1_0__Reg1_1__Mem85_2__ImmUnsignedi81_4
4093 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_95_addImmOperands, 5, CVT_Done },
4094 // Convert__Reg1_4__Reg1_3__Mem85_1__ImmUnsignedi81_0
4095 { CVT_95_Reg, 5, CVT_95_Reg, 4, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
4096 // Convert__Reg1_0__Tie0__Reg1_2__Reg1_4__Mem85_5__ImmUnsignedi81_7
4097 { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addMemOperands, 6, CVT_95_addImmOperands, 8, CVT_Done },
4098 // Convert__Reg1_4__Tie0__Reg1_6__Reg1_3__Mem85_1__ImmUnsignedi81_0
4099 { CVT_95_Reg, 5, CVT_Tied, 0, CVT_95_Reg, 7, CVT_95_Reg, 4, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
4100 // Convert__Reg1_0__Reg1_2__Reg1_5__Mem85_6__ImmUnsignedi81_8
4101 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_addMemOperands, 7, CVT_95_addImmOperands, 9, CVT_Done },
4102 // Convert__Reg1_4__Reg1_6__Reg1_3__Mem85_1__ImmUnsignedi81_0
4103 { CVT_95_Reg, 5, CVT_95_Reg, 7, CVT_95_Reg, 4, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
4104 // Convert__Mem1285_2__Reg1_1__Reg1_0
4105 { CVT_95_addMemOperands, 3, CVT_95_Reg, 2, CVT_95_Reg, 1, CVT_Done },
4106 // Convert__Mem2565_2__Reg1_1__Reg1_0
4107 { CVT_95_addMemOperands, 3, CVT_95_Reg, 2, CVT_95_Reg, 1, CVT_Done },
4108 // Convert__Mem1285_0__Reg1_1__Reg1_2
4109 { CVT_95_addMemOperands, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
4110 // Convert__Mem2565_0__Reg1_1__Reg1_2
4111 { CVT_95_addMemOperands, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
4112 // Convert__Reg1_0__Reg1_2__Reg1_4
4113 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_Done },
4114 // Convert__Mem645_1__Reg1_3__Reg1_0
4115 { CVT_95_addMemOperands, 2, CVT_95_Reg, 4, CVT_95_Reg, 1, CVT_Done },
4116 // Convert__Mem645_0__Reg1_2__Reg1_4
4117 { CVT_95_addMemOperands, 1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_Done },
4118 // Convert__Mem325_1__Reg1_3__Reg1_0
4119 { CVT_95_addMemOperands, 2, CVT_95_Reg, 4, CVT_95_Reg, 1, CVT_Done },
4120 // Convert__Mem325_0__Reg1_2__Reg1_4
4121 { CVT_95_addMemOperands, 1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_Done },
4122 // Convert__Reg1_0__Tie0__Reg1_2__Mem85_4
4123 { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_Reg, 3, CVT_95_addMemOperands, 5, CVT_Done },
4124 // Convert__Reg1_1__Tie0__Reg1_3__Mem85_0
4125 { CVT_95_Reg, 2, CVT_Tied, 0, CVT_95_Reg, 4, CVT_95_addMemOperands, 1, CVT_Done },
4126 // Convert__Reg1_0__Reg1_2__Mem85_5
4127 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_addMemOperands, 6, CVT_Done },
4128 // Convert__Reg1_1__Reg1_3__Mem85_0
4129 { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_95_addMemOperands, 1, CVT_Done },
4130 // Convert__Reg1_0__Tie0__Reg1_2__Mem165_4
4131 { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_Reg, 3, CVT_95_addMemOperands, 5, CVT_Done },
4132 // Convert__Reg1_1__Tie0__Reg1_3__Mem165_0
4133 { CVT_95_Reg, 2, CVT_Tied, 0, CVT_95_Reg, 4, CVT_95_addMemOperands, 1, CVT_Done },
4134 // Convert__Reg1_0__Reg1_2__Mem165_5
4135 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_addMemOperands, 6, CVT_Done },
4136 // Convert__Reg1_1__Reg1_3__Mem165_0
4137 { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_95_addMemOperands, 1, CVT_Done },
4138 // Convert__Reg1_2__Reg1_1__Reg1_0__imm_95_17
4139 { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_Reg, 1, CVT_imm_95_17, 0, CVT_Done },
4140 // Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_17
4141 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_imm_95_17, 0, CVT_Done },
4142 // Convert__Reg1_0__Reg1_1__Mem1285_2__imm_95_17
4143 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_imm_95_17, 0, CVT_Done },
4144 // Convert__Reg1_0__Reg1_1__Mem2565_2__imm_95_17
4145 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_imm_95_17, 0, CVT_Done },
4146 // Convert__Reg1_0__Reg1_1__Mem5125_2__imm_95_17
4147 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_imm_95_17, 0, CVT_Done },
4148 // Convert__Reg1_2__Reg1_1__Mem1285_0__imm_95_17
4149 { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_imm_95_17, 0, CVT_Done },
4150 // Convert__Reg1_2__Reg1_1__Mem2565_0__imm_95_17
4151 { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_imm_95_17, 0, CVT_Done },
4152 // Convert__Reg1_2__Reg1_1__Mem5125_0__imm_95_17
4153 { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_imm_95_17, 0, CVT_Done },
4154 // Convert__Reg1_2__Reg1_1__Reg1_0__imm_95_1
4155 { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_Reg, 1, CVT_imm_95_1, 0, CVT_Done },
4156 // Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_1
4157 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_imm_95_1, 0, CVT_Done },
4158 // Convert__Reg1_0__Reg1_1__Mem1285_2__imm_95_1
4159 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_imm_95_1, 0, CVT_Done },
4160 // Convert__Reg1_0__Reg1_1__Mem2565_2__imm_95_1
4161 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_imm_95_1, 0, CVT_Done },
4162 // Convert__Reg1_0__Reg1_1__Mem5125_2__imm_95_1
4163 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_imm_95_1, 0, CVT_Done },
4164 // Convert__Reg1_2__Reg1_1__Mem1285_0__imm_95_1
4165 { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_imm_95_1, 0, CVT_Done },
4166 // Convert__Reg1_2__Reg1_1__Mem2565_0__imm_95_1
4167 { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_imm_95_1, 0, CVT_Done },
4168 // Convert__Reg1_2__Reg1_1__Mem5125_0__imm_95_1
4169 { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_imm_95_1, 0, CVT_Done },
4170 // Convert__Reg1_2__Reg1_1__Reg1_0__imm_95_16
4171 { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_Reg, 1, CVT_imm_95_16, 0, CVT_Done },
4172 // Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_16
4173 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_imm_95_16, 0, CVT_Done },
4174 // Convert__Reg1_0__Reg1_1__Mem1285_2__imm_95_16
4175 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_imm_95_16, 0, CVT_Done },
4176 // Convert__Reg1_0__Reg1_1__Mem2565_2__imm_95_16
4177 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_imm_95_16, 0, CVT_Done },
4178 // Convert__Reg1_0__Reg1_1__Mem5125_2__imm_95_16
4179 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_imm_95_16, 0, CVT_Done },
4180 // Convert__Reg1_2__Reg1_1__Mem1285_0__imm_95_16
4181 { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_imm_95_16, 0, CVT_Done },
4182 // Convert__Reg1_2__Reg1_1__Mem2565_0__imm_95_16
4183 { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_imm_95_16, 0, CVT_Done },
4184 // Convert__Reg1_2__Reg1_1__Mem5125_0__imm_95_16
4185 { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_imm_95_16, 0, CVT_Done },
4186 // Convert__Reg1_2__Reg1_1__Reg1_0__imm_95_0
4187 { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_Reg, 1, CVT_imm_95_0, 0, CVT_Done },
4188 // Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0
4189 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_Done },
4190 // Convert__Reg1_0__Reg1_1__Mem1285_2__imm_95_0
4191 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_imm_95_0, 0, CVT_Done },
4192 // Convert__Reg1_0__Reg1_1__Mem2565_2__imm_95_0
4193 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_imm_95_0, 0, CVT_Done },
4194 // Convert__Reg1_0__Reg1_1__Mem5125_2__imm_95_0
4195 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_imm_95_0, 0, CVT_Done },
4196 // Convert__Reg1_2__Reg1_1__Mem1285_0__imm_95_0
4197 { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_imm_95_0, 0, CVT_Done },
4198 // Convert__Reg1_2__Reg1_1__Mem2565_0__imm_95_0
4199 { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_imm_95_0, 0, CVT_Done },
4200 // Convert__Reg1_2__Reg1_1__Mem5125_0__imm_95_0
4201 { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_imm_95_0, 0, CVT_Done },
4202 // Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmUnsignedi81_4
4203 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_Done },
4204 // Convert__Reg1_0__Reg1_1__Reg1_2__Mem1285_3__ImmUnsignedi81_4
4205 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addMemOperands, 4, CVT_95_addImmOperands, 5, CVT_Done },
4206 // Convert__Reg1_0__Reg1_1__Mem1285_2__Reg1_3__ImmUnsignedi81_4
4207 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_Done },
4208 // Convert__Reg1_0__Reg1_1__Reg1_2__Mem2565_3__ImmUnsignedi81_4
4209 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addMemOperands, 4, CVT_95_addImmOperands, 5, CVT_Done },
4210 // Convert__Reg1_0__Reg1_1__Mem2565_2__Reg1_3__ImmUnsignedi81_4
4211 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_Done },
4212 // Convert__Reg1_4__Reg1_3__Reg1_2__Reg1_1__ImmUnsignedi81_0
4213 { CVT_95_Reg, 5, CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
4214 // Convert__Reg1_4__Reg1_3__Mem1285_2__Reg1_1__ImmUnsignedi81_0
4215 { CVT_95_Reg, 5, CVT_95_Reg, 4, CVT_95_addMemOperands, 3, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
4216 // Convert__Reg1_4__Reg1_3__Mem2565_2__Reg1_1__ImmUnsignedi81_0
4217 { CVT_95_Reg, 5, CVT_95_Reg, 4, CVT_95_addMemOperands, 3, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
4218 // Convert__Reg1_4__Reg1_3__Reg1_2__Mem1285_1__ImmUnsignedi81_0
4219 { CVT_95_Reg, 5, CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
4220 // Convert__Reg1_4__Reg1_3__Reg1_2__Mem2565_1__ImmUnsignedi81_0
4221 { CVT_95_Reg, 5, CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
4222 // Convert__Reg1_0__Reg1_1__GR32orGR641_2__ImmUnsignedi81_3
4223 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addGR32orGR64Operands, 3, CVT_95_addImmOperands, 4, CVT_Done },
4224 // Convert__Reg1_0__Reg1_1__Mem85_2__ImmUnsignedi81_3
4225 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
4226 // Convert__Reg1_3__Reg1_2__GR32orGR641_1__ImmUnsignedi81_0
4227 { CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_addGR32orGR64Operands, 2, CVT_95_addImmOperands, 1, CVT_Done },
4228 // Convert__Reg1_3__Reg1_2__Mem85_1__ImmUnsignedi81_0
4229 { CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
4230 // Convert__Reg1_0__Reg1_1__Mem165_2__ImmUnsignedi81_3
4231 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
4232 // Convert__Reg1_3__Reg1_2__Mem165_1__ImmUnsignedi81_0
4233 { CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
4234 // Convert__Mem165_1__Reg1_3__Reg1_0
4235 { CVT_95_addMemOperands, 2, CVT_95_Reg, 4, CVT_95_Reg, 1, CVT_Done },
4236 // Convert__Mem165_0__Reg1_2__Reg1_4
4237 { CVT_95_addMemOperands, 1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_Done },
4238 // Convert__Reg1_2__Mem1285_1__Reg1_0
4239 { CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_Reg, 1, CVT_Done },
4240 // Convert__Reg1_0__Mem1285_1__Reg1_2
4241 { CVT_95_Reg, 1, CVT_95_addMemOperands, 2, CVT_95_Reg, 3, CVT_Done },
4242 // Convert__Reg1_3__Mem128_RC128X5_1__Tie0__Reg1_0
4243 { CVT_95_Reg, 4, CVT_95_addMemOperands, 2, CVT_Tied, 0, CVT_95_Reg, 1, CVT_Done },
4244 // Convert__Reg1_3__Mem256_RC256X5_1__Tie0__Reg1_0
4245 { CVT_95_Reg, 4, CVT_95_addMemOperands, 2, CVT_Tied, 0, CVT_95_Reg, 1, CVT_Done },
4246 // Convert__Reg1_3__Mem512_RC5125_1__Tie0__Reg1_0
4247 { CVT_95_Reg, 4, CVT_95_addMemOperands, 2, CVT_Tied, 0, CVT_95_Reg, 1, CVT_Done },
4248 // Convert__Reg1_2__Mem128_RC128X5_0__Tie0__Reg1_4
4249 { CVT_95_Reg, 3, CVT_95_addMemOperands, 1, CVT_Tied, 0, CVT_95_Reg, 5, CVT_Done },
4250 // Convert__Reg1_2__Mem256_RC256X5_0__Tie0__Reg1_4
4251 { CVT_95_Reg, 3, CVT_95_addMemOperands, 1, CVT_Tied, 0, CVT_95_Reg, 5, CVT_Done },
4252 // Convert__Reg1_2__Mem512_RC5125_0__Tie0__Reg1_4
4253 { CVT_95_Reg, 3, CVT_95_addMemOperands, 1, CVT_Tied, 0, CVT_95_Reg, 5, CVT_Done },
4254 // Convert__Reg1_3__Mem256_RC128X5_1__Tie0__Reg1_0
4255 { CVT_95_Reg, 4, CVT_95_addMemOperands, 2, CVT_Tied, 0, CVT_95_Reg, 1, CVT_Done },
4256 // Convert__Reg1_3__Mem512_RC256X5_1__Tie0__Reg1_0
4257 { CVT_95_Reg, 4, CVT_95_addMemOperands, 2, CVT_Tied, 0, CVT_95_Reg, 1, CVT_Done },
4258 // Convert__Reg1_2__Mem256_RC128X5_0__Tie0__Reg1_4
4259 { CVT_95_Reg, 3, CVT_95_addMemOperands, 1, CVT_Tied, 0, CVT_95_Reg, 5, CVT_Done },
4260 // Convert__Reg1_2__Mem512_RC256X5_0__Tie0__Reg1_4
4261 { CVT_95_Reg, 3, CVT_95_addMemOperands, 1, CVT_Tied, 0, CVT_95_Reg, 5, CVT_Done },
4262 // Convert__Reg1_3__Mem128_RC256X5_1__Tie0__Reg1_0
4263 { CVT_95_Reg, 4, CVT_95_addMemOperands, 2, CVT_Tied, 0, CVT_95_Reg, 1, CVT_Done },
4264 // Convert__Reg1_3__Mem64_RC128X5_1__Tie0__Reg1_0
4265 { CVT_95_Reg, 4, CVT_95_addMemOperands, 2, CVT_Tied, 0, CVT_95_Reg, 1, CVT_Done },
4266 // Convert__Reg1_3__Mem256_RC5125_1__Tie0__Reg1_0
4267 { CVT_95_Reg, 4, CVT_95_addMemOperands, 2, CVT_Tied, 0, CVT_95_Reg, 1, CVT_Done },
4268 // Convert__Reg1_2__Mem128_RC256X5_0__Tie0__Reg1_4
4269 { CVT_95_Reg, 3, CVT_95_addMemOperands, 1, CVT_Tied, 0, CVT_95_Reg, 5, CVT_Done },
4270 // Convert__Reg1_2__Mem256_RC5125_0__Tie0__Reg1_4
4271 { CVT_95_Reg, 3, CVT_95_addMemOperands, 1, CVT_Tied, 0, CVT_95_Reg, 5, CVT_Done },
4272 // Convert__Reg1_2__Mem64_RC128X5_0__Tie0__Reg1_4
4273 { CVT_95_Reg, 3, CVT_95_addMemOperands, 1, CVT_Tied, 0, CVT_95_Reg, 5, CVT_Done },
4274 // Convert__AbsMem161_0
4275 { CVT_95_addAbsMemOperands, 1, CVT_Done },
4276};
4277
4278void X86AsmParser::
4279convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
4280 const OperandVector &Operands) {
4281 assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!")(static_cast <bool> (Kind < CVT_NUM_SIGNATURES &&
"Invalid signature!") ? void (0) : __assert_fail ("Kind < CVT_NUM_SIGNATURES && \"Invalid signature!\""
, "/build/llvm-toolchain-snapshot-6.0~svn321639/build-llvm/lib/Target/X86/X86GenAsmMatcher.inc"
, 4281, __extension__ __PRETTY_FUNCTION__))
;
4282 const uint8_t *Converter = ConversionTable[Kind];
4283 unsigned OpIdx;
4284 Inst.setOpcode(Opcode);
4285 for (const uint8_t *p = Converter; *p; p+= 2) {
4286 OpIdx = *(p + 1);
4287 switch (*p) {
4288 default: llvm_unreachable("invalid conversion entry!")::llvm::llvm_unreachable_internal("invalid conversion entry!"
, "/build/llvm-toolchain-snapshot-6.0~svn321639/build-llvm/lib/Target/X86/X86GenAsmMatcher.inc"
, 4288)
;
4289 case CVT_Reg:
4290 static_cast<X86Operand&>(*Operands[OpIdx]).addRegOperands(Inst, 1);
4291 break;
4292 case CVT_Tied:
4293 Inst.addOperand(Inst.getOperand(OpIdx));
4294 break;
4295 case CVT_imm_95_10:
4296 Inst.addOperand(MCOperand::createImm(10));
4297 break;
4298 case CVT_95_addImmOperands:
4299 static_cast<X86Operand&>(*Operands[OpIdx]).addImmOperands(Inst, 1);
4300 break;
4301 case CVT_regAX:
4302 Inst.addOperand(MCOperand::createReg(X86::AX));
4303 break;
4304 case CVT_regEAX:
4305 Inst.addOperand(MCOperand::createReg(X86::EAX));
4306 break;
4307 case CVT_regRAX:
4308 Inst.addOperand(MCOperand::createReg(X86::RAX));
4309 break;
4310 case CVT_95_Reg:
4311 static_cast<X86Operand&>(*Operands[OpIdx]).addRegOperands(Inst, 1);
4312 break;
4313 case CVT_95_addMemOperands:
4314 static_cast<X86Operand&>(*Operands[OpIdx]).addMemOperands(Inst, 5);
4315 break;
4316 case CVT_95_addAbsMemOperands:
4317 static_cast<X86Operand&>(*Operands[OpIdx]).addAbsMemOperands(Inst, 1);
4318 break;
4319 case CVT_95_addDstIdxOperands:
4320 static_cast<X86Operand&>(*Operands[OpIdx]).addDstIdxOperands(Inst, 1);
4321 break;
4322 case CVT_95_addSrcIdxOperands:
4323 static_cast<X86Operand&>(*Operands[OpIdx]).addSrcIdxOperands(Inst, 2);
4324 break;
4325 case CVT_95_addGR32orGR64Operands:
4326 static_cast<X86Operand&>(*Operands[OpIdx]).addGR32orGR64Operands(Inst, 1);
4327 break;
4328 case CVT_regST1:
4329 Inst.addOperand(MCOperand::createReg(X86::ST1));
4330 break;
4331 case CVT_regST0:
4332 Inst.addOperand(MCOperand::createReg(X86::ST0));
4333 break;
4334 case CVT_95_addMemOffsOperands:
4335 static_cast<X86Operand&>(*Operands[OpIdx]).addMemOffsOperands(Inst, 2);
4336 break;
4337 case CVT_imm_95_17:
4338 Inst.addOperand(MCOperand::createImm(17));
4339 break;
4340 case CVT_imm_95_1:
4341 Inst.addOperand(MCOperand::createImm(1));
4342 break;
4343 case CVT_imm_95_16:
4344 Inst.addOperand(MCOperand::createImm(16));
4345 break;
4346 case CVT_imm_95_0:
4347 Inst.addOperand(MCOperand::createImm(0));
4348 break;
4349 case CVT_95_addAVX512RCOperands:
4350 static_cast<X86Operand&>(*Operands[OpIdx]).addAVX512RCOperands(Inst, 1);
4351 break;
4352 }
4353 }
4354}
4355
4356void X86AsmParser::
4357convertToMapAndConstraints(unsigned Kind,
4358 const OperandVector &Operands) {
4359 assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!")(static_cast <bool> (Kind < CVT_NUM_SIGNATURES &&
"Invalid signature!") ? void (0) : __assert_fail ("Kind < CVT_NUM_SIGNATURES && \"Invalid signature!\""
, "/build/llvm-toolchain-snapshot-6.0~svn321639/build-llvm/lib/Target/X86/X86GenAsmMatcher.inc"
, 4359, __extension__ __PRETTY_FUNCTION__))
;
4360 unsigned NumMCOperands = 0;
4361 const uint8_t *Converter = ConversionTable[Kind];
4362 for (const uint8_t *p = Converter; *p; p+= 2) {
4363 switch (*p) {
4364 default: llvm_unreachable("invalid conversion entry!")::llvm::llvm_unreachable_internal("invalid conversion entry!"
, "/build/llvm-toolchain-snapshot-6.0~svn321639/build-llvm/lib/Target/X86/X86GenAsmMatcher.inc"
, 4364)
;
4365 case CVT_Reg:
4366 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4367 Operands[*(p + 1)]->setConstraint("r");
4368 ++NumMCOperands;
4369 break;
4370 case CVT_Tied:
4371 ++NumMCOperands;
4372 break;
4373 case CVT_imm_95_10:
4374 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4375 Operands[*(p + 1)]->setConstraint("");
4376 ++NumMCOperands;
4377 break;
4378 case CVT_95_addImmOperands:
4379 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4380 Operands[*(p + 1)]->setConstraint("m");
4381 NumMCOperands += 1;
4382 break;
4383 case CVT_regAX:
4384 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4385 Operands[*(p + 1)]->setConstraint("m");
4386 ++NumMCOperands;
4387 break;
4388 case CVT_regEAX:
4389 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4390 Operands[*(p + 1)]->setConstraint("m");
4391 ++NumMCOperands;
4392 break;
4393 case CVT_regRAX:
4394 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4395 Operands[*(p + 1)]->setConstraint("m");
4396 ++NumMCOperands;
4397 break;
4398 case CVT_95_Reg:
4399 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4400 Operands[*(p + 1)]->setConstraint("r");
4401 NumMCOperands += 1;
4402 break;
4403 case CVT_95_addMemOperands:
4404 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4405 Operands[*(p + 1)]->setConstraint("m");
4406 NumMCOperands += 5;
4407 break;
4408 case CVT_95_addAbsMemOperands:
4409 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4410 Operands[*(p + 1)]->setConstraint("m");
4411 NumMCOperands += 1;
4412 break;
4413 case CVT_95_addDstIdxOperands:
4414 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4415 Operands[*(p + 1)]->setConstraint("m");
4416 NumMCOperands += 1;
4417 break;
4418 case CVT_95_addSrcIdxOperands:
4419 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4420 Operands[*(p + 1)]->setConstraint("m");
4421 NumMCOperands += 2;
4422 break;
4423 case CVT_95_addGR32orGR64Operands:
4424 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4425 Operands[*(p + 1)]->setConstraint("m");
4426 NumMCOperands += 1;
4427 break;
4428 case CVT_regST1:
4429 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4430 Operands[*(p + 1)]->setConstraint("m");
4431 ++NumMCOperands;
4432 break;
4433 case CVT_regST0:
4434 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4435 Operands[*(p + 1)]->setConstraint("m");
4436 ++NumMCOperands;
4437 break;
4438 case CVT_95_addMemOffsOperands:
4439 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4440 Operands[*(p + 1)]->setConstraint("m");
4441 NumMCOperands += 2;
4442 break;
4443 case CVT_imm_95_17:
4444 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4445 Operands[*(p + 1)]->setConstraint("");
4446 ++NumMCOperands;
4447 break;
4448 case CVT_imm_95_1:
4449 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4450 Operands[*(p + 1)]->setConstraint("");
4451 ++NumMCOperands;
4452 break;
4453 case CVT_imm_95_16:
4454 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4455 Operands[*(p + 1)]->setConstraint("");
4456 ++NumMCOperands;
4457 break;
4458 case CVT_imm_95_0:
4459 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4460 Operands[*(p + 1)]->setConstraint("");
4461 ++NumMCOperands;
4462 break;
4463 case CVT_95_addAVX512RCOperands:
4464 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4465 Operands[*(p + 1)]->setConstraint("m");
4466 NumMCOperands += 1;
4467 break;
4468 }
4469 }
4470}
4471
4472namespace {
4473
4474/// MatchClassKind - The kinds of classes which participate in
4475/// instruction matching.
4476enum MatchClassKind {
4477 InvalidMatchClass = 0,
4478 OptionalMatchClass = 1,
4479 MCK__STAR_, // '*'
4480 MCK_b, // 'b'
4481 MCK_d, // 'd'
4482 MCK_pd, // 'pd'
4483 MCK_ps, // 'ps'
4484 MCK_q, // 'q'
4485 MCK_sae, // 'sae'
4486 MCK_sd, // 'sd'
4487 MCK_ss, // 'ss'
4488 MCK_ub, // 'ub'
4489 MCK_ud, // 'ud'
4490 MCK_uq, // 'uq'
4491 MCK_uw, // 'uw'
4492 MCK_w, // 'w'
4493 MCK__123_, // '{'
4494 MCK__123_1to16_125_, // '{1to16}'
4495 MCK__123_1to2_125_, // '{1to2}'
4496 MCK__123_1to4_125_, // '{1to4}'
4497 MCK__123_1to8_125_, // '{1to8}'
4498 MCK__123_sae_125_, // '{sae}'
4499 MCK__123_z_125_, // '{z}'
4500 MCK__125_, // '}'
4501 MCK_LAST_TOKEN = MCK__125_,
4502 MCK_Reg64, // derived register class
4503 MCK_Reg66, // derived register class
4504 MCK_AL, // register class 'AL'
4505 MCK_AX, // register class 'AX'
4506 MCK_CCR, // register class 'CCR'
4507 MCK_CL, // register class 'CL'
4508 MCK_CS, // register class 'CS'
4509 MCK_DS, // register class 'DS'
4510 MCK_DX, // register class 'DX'
4511 MCK_EAX, // register class 'EAX'
4512 MCK_EBX, // register class 'EBX'
4513 MCK_ECX, // register class 'ECX'
4514 MCK_EDX, // register class 'EDX'
4515 MCK_ES, // register class 'ES'
4516 MCK_FPCCR, // register class 'FPCCR'
4517 MCK_FS, // register class 'FS'
4518 MCK_GS, // register class 'GS'
4519 MCK_RAX, // register class 'RAX'
4520 MCK_RBX, // register class 'RBX'
4521 MCK_RCX, // register class 'RCX'
4522 MCK_RDX, // register class 'RDX'
4523 MCK_SS, // register class 'SS'
4524 MCK_ST0, // register class 'ST0'
4525 MCK_XMM0, // register class 'XMM0'
4526 MCK_Reg24, // derived register class
4527 MCK_Reg52, // derived register class
4528 MCK_Reg65, // derived register class
4529 MCK_GR32_AD, // register class 'GR32_AD'
4530 MCK_GR64_AD, // register class 'GR64_AD'
4531 MCK_Reg25, // derived register class
4532 MCK_Reg34, // derived register class
4533 MCK_Reg53, // derived register class
4534 MCK_GR32_TC, // register class 'GR32_TC'
4535 MCK_Reg50, // derived register class
4536 MCK_Reg58, // derived register class
4537 MCK_BNDR, // register class 'BNDR'
4538 MCK_GR16_ABCD, // register class 'GR16_ABCD'
4539 MCK_GR32_ABCD, // register class 'GR32_ABCD'
4540 MCK_GR64_ABCD, // register class 'GR64_ABCD'
4541 MCK_GR8_ABCD_H, // register class 'GR8_ABCD_H'
4542 MCK_GR8_ABCD_L, // register class 'GR8_ABCD_L'
4543 MCK_Reg42, // derived register class
4544 MCK_Reg61, // derived register class
4545 MCK_Reg26, // derived register class
4546 MCK_Reg45, // derived register class
4547 MCK_Reg48, // derived register class
4548 MCK_Reg54, // derived register class
4549 MCK_Reg60, // derived register class
4550 MCK_SEGMENT_REG, // register class 'SEGMENT_REG'
4551 MCK_Reg27, // derived register class
4552 MCK_Reg46, // derived register class
4553 MCK_Reg49, // derived register class
4554 MCK_Reg55, // derived register class
4555 MCK_Reg59, // derived register class
4556 MCK_GR32_NOREX_NOSP, // register class 'GR32_NOREX_NOSP'
4557 MCK_GR64_NOREX_NOSP, // register class 'GR64_NOREX_NOSP'
4558 MCK_RFP32, // register class 'RFP32,RFP64,RFP80'
4559 MCK_VK16WM, // register class 'VK16WM,VK1WM,VK2WM,VK4WM,VK8WM,VK32WM,VK64WM'
4560 MCK_Reg37, // derived register class
4561 MCK_Reg43, // derived register class
4562 MCK_Reg78, // derived register class
4563 MCK_Reg81, // derived register class
4564 MCK_GR16_NOREX, // register class 'GR16_NOREX'
4565 MCK_GR32_NOREX, // register class 'GR32_NOREX'
4566 MCK_GR64_TCW64, // register class 'GR64_TCW64'
4567 MCK_GR8_NOREX, // register class 'GR8_NOREX'
4568 MCK_RST, // register class 'RST'
4569 MCK_VK1, // register class 'VK1,VK16,VK2,VK4,VK8,VK32,VK64'
4570 MCK_VR128H, // register class 'VR128H'
4571 MCK_VR128L, // register class 'VR128L'
4572 MCK_VR256H, // register class 'VR256H'
4573 MCK_VR256L, // register class 'VR256L'
4574 MCK_VR64, // register class 'VR64'
4575 MCK_Reg21, // derived register class
4576 MCK_GR64_NOREX, // register class 'GR64_NOREX'
4577 MCK_GR64_TC, // register class 'GR64_TC'
4578 MCK_Reg29, // derived register class
4579 MCK_Reg57, // derived register class
4580 MCK_Reg56, // derived register class
4581 MCK_GR32_NOAX, // register class 'GR32_NOAX'
4582 MCK_GR32_NOSP, // register class 'GR32_NOSP'
4583 MCK_GR64_NOSP, // register class 'GR64_NOSP'
4584 MCK_Reg38, // derived register class
4585 MCK_Reg79, // derived register class
4586 MCK_CONTROL_REG, // register class 'CONTROL_REG'
4587 MCK_DEBUG_REG, // register class 'DEBUG_REG'
4588 MCK_FR32, // register class 'FR32,FR64,FR128,VR128'
4589 MCK_GR16, // register class 'GR16'
4590 MCK_GR32, // register class 'GR32'
4591 MCK_VR256, // register class 'VR256'
4592 MCK_Reg18, // derived register class
4593 MCK_GR64, // register class 'GR64'
4594 MCK_LOW32_ADDR_ACCESS, // register class 'LOW32_ADDR_ACCESS'
4595 MCK_LOW32_ADDR_ACCESS_RBP, // register class 'LOW32_ADDR_ACCESS_RBP'
4596 MCK_GR8, // register class 'GR8'
4597 MCK_FR32X, // register class 'FR32X,FR64X,VR128X'
4598 MCK_VR256X, // register class 'VR256X'
4599 MCK_VR512, // register class 'VR512'
4600 MCK_LAST_REGISTER = MCK_VR512,
4601 MCK_AVX512RC, // user defined class 'AVX512RCOperand'
4602 MCK_ImmSExti64i8, // user defined class 'ImmSExti64i8AsmOperand'
4603 MCK_ImmSExti16i8, // user defined class 'ImmSExti16i8AsmOperand'
4604 MCK_ImmSExti32i8, // user defined class 'ImmSExti32i8AsmOperand'
4605 MCK_ImmSExti64i32, // user defined class 'ImmSExti64i32AsmOperand'
4606 MCK_Imm, // user defined class 'ImmAsmOperand'
4607 MCK_ImmUnsignedi8, // user defined class 'ImmUnsignedi8AsmOperand'
4608 MCK_GR32orGR64, // user defined class 'X86GR32orGR64AsmOperand'
4609 MCK_AbsMem16, // user defined class 'X86AbsMem16AsmOperand'
4610 MCK_DstIdx16, // user defined class 'X86DstIdx16Operand'
4611 MCK_DstIdx32, // user defined class 'X86DstIdx32Operand'
4612 MCK_DstIdx64, // user defined class 'X86DstIdx64Operand'
4613 MCK_DstIdx8, // user defined class 'X86DstIdx8Operand'
4614 MCK_MemOffs16_16, // user defined class 'X86MemOffs16_16AsmOperand'
4615 MCK_MemOffs16_32, // user defined class 'X86MemOffs16_32AsmOperand'
4616 MCK_MemOffs16_8, // user defined class 'X86MemOffs16_8AsmOperand'
4617 MCK_MemOffs32_16, // user defined class 'X86MemOffs32_16AsmOperand'
4618 MCK_MemOffs32_32, // user defined class 'X86MemOffs32_32AsmOperand'
4619 MCK_MemOffs32_64, // user defined class 'X86MemOffs32_64AsmOperand'
4620 MCK_MemOffs32_8, // user defined class 'X86MemOffs32_8AsmOperand'
4621 MCK_MemOffs64_16, // user defined class 'X86MemOffs64_16AsmOperand'
4622 MCK_MemOffs64_32, // user defined class 'X86MemOffs64_32AsmOperand'
4623 MCK_MemOffs64_64, // user defined class 'X86MemOffs64_64AsmOperand'
4624 MCK_MemOffs64_8, // user defined class 'X86MemOffs64_8AsmOperand'
4625 MCK_SrcIdx16, // user defined class 'X86SrcIdx16Operand'
4626 MCK_SrcIdx32, // user defined class 'X86SrcIdx32Operand'
4627 MCK_SrcIdx64, // user defined class 'X86SrcIdx64Operand'
4628 MCK_SrcIdx8, // user defined class 'X86SrcIdx8Operand'
4629 MCK_AbsMem, // user defined class 'X86AbsMemAsmOperand'
4630 MCK_Mem128, // user defined class 'X86Mem128AsmOperand'
4631 MCK_Mem128_RC128, // user defined class 'X86Mem128_RC128Operand'
4632 MCK_Mem128_RC128X, // user defined class 'X86Mem128_RC128XOperand'
4633 MCK_Mem128_RC256, // user defined class 'X86Mem128_RC256Operand'
4634 MCK_Mem128_RC256X, // user defined class 'X86Mem128_RC256XOperand'
4635 MCK_Mem16, // user defined class 'X86Mem16AsmOperand'
4636 MCK_Mem256, // user defined class 'X86Mem256AsmOperand'
4637 MCK_Mem256_RC128, // user defined class 'X86Mem256_RC128Operand'
4638 MCK_Mem256_RC128X, // user defined class 'X86Mem256_RC128XOperand'
4639 MCK_Mem256_RC256, // user defined class 'X86Mem256_RC256Operand'
4640 MCK_Mem256_RC256X, // user defined class 'X86Mem256_RC256XOperand'
4641 MCK_Mem256_RC512, // user defined class 'X86Mem256_RC512Operand'
4642 MCK_Mem32, // user defined class 'X86Mem32AsmOperand'
4643 MCK_Mem512, // user defined class 'X86Mem512AsmOperand'
4644 MCK_Mem512_RC256X, // user defined class 'X86Mem512_RC256XOperand'
4645 MCK_Mem512_RC512, // user defined class 'X86Mem512_RC512Operand'
4646 MCK_Mem64, // user defined class 'X86Mem64AsmOperand'
4647 MCK_Mem64_RC128, // user defined class 'X86Mem64_RC128Operand'
4648 MCK_Mem64_RC128X, // user defined class 'X86Mem64_RC128XOperand'
4649 MCK_Mem80, // user defined class 'X86Mem80AsmOperand'
4650 MCK_Mem8, // user defined class 'X86Mem8AsmOperand'
4651 MCK_Mem, // user defined class 'X86MemAsmOperand'
4652 NumMatchClassKinds
4653};
4654
4655}
4656
4657static unsigned getDiagKindFromRegisterClass(MatchClassKind RegisterClass) {
4658 return MCTargetAsmParser::Match_InvalidOperand;
4659}
4660
4661static MatchClassKind matchTokenString(StringRef Name) {
4662 switch (Name.size()) {
4663 default: break;
4664 case 1: // 7 strings to match.
4665 switch (Name[0]) {
4666 default: break;
4667 case '*': // 1 string to match.
4668 return MCK__STAR_; // "*"
4669 case 'b': // 1 string to match.
4670 return MCK_b; // "b"
4671 case 'd': // 1 string to match.
4672 return MCK_d; // "d"
4673 case 'q': // 1 string to match.
4674 return MCK_q; // "q"
4675 case 'w': // 1 string to match.
4676 return MCK_w; // "w"
4677 case '{': // 1 string to match.
4678 return MCK__123_; // "{"
4679 case '}': // 1 string to match.
4680 return MCK__125_; // "}"
4681 }
4682 break;
4683 case 2: // 8 strings to match.
4684 switch (Name[0]) {
4685 default: break;
4686 case 'p': // 2 strings to match.
4687 switch (Name[1]) {
4688 default: break;
4689 case 'd': // 1 string to match.
4690 return MCK_pd; // "pd"
4691 case 's': // 1 string to match.
4692 return MCK_ps; // "ps"
4693 }
4694 break;
4695 case 's': // 2 strings to match.
4696 switch (Name[1]) {
4697 default: break;
4698 case 'd': // 1 string to match.
4699 return MCK_sd; // "sd"
4700 case 's': // 1 string to match.
4701 return MCK_ss; // "ss"
4702 }
4703 break;
4704 case 'u': // 4 strings to match.
4705 switch (Name[1]) {
4706 default: break;
4707 case 'b': // 1 string to match.
4708 return MCK_ub; // "ub"
4709 case 'd': // 1 string to match.
4710 return MCK_ud; // "ud"
4711 case 'q': // 1 string to match.
4712 return MCK_uq; // "uq"
4713 case 'w': // 1 string to match.
4714 return MCK_uw; // "uw"
4715 }
4716 break;
4717 }
4718 break;
4719 case 3: // 2 strings to match.
4720 switch (Name[0]) {
4721 default: break;
4722 case 's': // 1 string to match.
4723 if (memcmp(Name.data()+1, "ae", 2) != 0)
4724 break;
4725 return MCK_sae; // "sae"
4726 case '{': // 1 string to match.
4727 if (memcmp(Name.data()+1, "z}", 2) != 0)
4728 break;
4729 return MCK__123_z_125_; // "{z}"
4730 }
4731 break;
4732 case 5: // 1 string to match.
4733 if (memcmp(Name.data()+0, "{sae}", 5) != 0)
4734 break;
4735 return MCK__123_sae_125_; // "{sae}"
4736 case 6: // 3 strings to match.
4737 if (memcmp(Name.data()+0, "{1to", 4) != 0)
4738 break;
4739 switch (Name[4]) {
4740 default: break;
4741 case '2': // 1 string to match.
4742 if (Name[5] != '}')
4743 break;
4744 return MCK__123_1to2_125_; // "{1to2}"
4745 case '4': // 1 string to match.
4746 if (Name[5] != '}')
4747 break;
4748 return MCK__123_1to4_125_; // "{1to4}"
4749 case '8': // 1 string to match.
4750 if (Name[5] != '}')
4751 break;
4752 return MCK__123_1to8_125_; // "{1to8}"
4753 }
4754 break;
4755 case 7: // 1 string to match.
4756 if (memcmp(Name.data()+0, "{1to16}", 7) != 0)
4757 break;
4758 return MCK__123_1to16_125_; // "{1to16}"
4759 }
4760 return InvalidMatchClass;
4761}
4762
4763/// isSubclass - Compute whether \p A is a subclass of \p B.
4764static bool isSubclass(MatchClassKind A, MatchClassKind B) {
4765 if (A == B)
4766 return true;
4767
4768 switch (A) {
4769 default:
4770 return false;
4771
4772 case MCK_Reg64:
4773 switch (B) {
4774 default: return false;
4775 case MCK_Reg65: return true;
4776 case MCK_Reg54: return true;
4777 case MCK_Reg55: return true;
4778 case MCK_GR64_NOREX_NOSP: return true;
4779 case MCK_Reg37: return true;
4780 case MCK_Reg21: return true;
4781 case MCK_GR64_NOREX: return true;
4782 case MCK_Reg57: return true;
4783 case MCK_Reg56: return true;
4784 case MCK_GR64_NOSP: return true;
4785 case MCK_Reg38: return true;
4786 case MCK_Reg18: return true;
4787 case MCK_GR64: return true;
4788 case MCK_LOW32_ADDR_ACCESS_RBP: return true;
4789 }
4790
4791 case MCK_Reg66:
4792 switch (B) {
4793 default: return false;
4794 case MCK_Reg65: return true;
4795 case MCK_Reg50: return true;
4796 case MCK_Reg45: return true;
4797 case MCK_Reg49: return true;
4798 case MCK_GR64_TCW64: return true;
4799 case MCK_GR64_NOREX: return true;
4800 case MCK_GR64_TC: return true;
4801 case MCK_GR64: return true;
4802 case MCK_LOW32_ADDR_ACCESS: return true;
4803 case MCK_LOW32_ADDR_ACCESS_RBP: return true;
4804 }
4805
4806 case MCK_AL:
4807 switch (B) {
4808 default: return false;
4809 case MCK_GR8_ABCD_L: return true;
4810 case MCK_GR8_NOREX: return true;
4811 case MCK_GR8: return true;
4812 }
4813
4814 case MCK_AX:
4815 switch (B) {
4816 default: return false;
4817 case MCK_GR16_ABCD: return true;
4818 case MCK_GR16_NOREX: return true;
4819 case MCK_GR16: return true;
4820 }
4821
4822 case MCK_CL:
4823 switch (B) {
4824 default: return false;
4825 case MCK_GR8_ABCD_L: return true;
4826 case MCK_GR8_NOREX: return true;
4827 case MCK_GR8: return true;
4828 }
4829
4830 case MCK_CS:
4831 return B == MCK_SEGMENT_REG;
4832
4833 case MCK_DS:
4834 return B == MCK_SEGMENT_REG;
4835
4836 case MCK_DX:
4837 switch (B) {
4838 default: return false;
4839 case MCK_GR16_ABCD: return true;
4840 case MCK_GR16_NOREX: return true;
4841 case MCK_GR16: return true;
4842 }
4843
4844 case MCK_EAX:
4845 switch (B) {
4846 default: return false;
4847 case MCK_GR32_AD: return true;
4848 case MCK_GR32_TC: return true;
4849 case MCK_GR32_ABCD: return true;
4850 case MCK_GR32_NOREX_NOSP: return true;
4851 case MCK_GR32_NOREX: return true;
4852 case MCK_Reg21: return true;
4853 case MCK_GR32_NOSP: return true;
4854 case MCK_GR32: return true;
4855 case MCK_Reg18: return true;
4856 case MCK_LOW32_ADDR_ACCESS: return true;
4857 case MCK_LOW32_ADDR_ACCESS_RBP: return true;
4858 }
4859
4860 case MCK_EBX:
4861 switch (B) {
4862 default: return false;
4863 case MCK_Reg25: return true;
4864 case MCK_GR32_ABCD: return true;
4865 case MCK_Reg26: return true;
4866 case MCK_Reg27: return true;
4867 case MCK_GR32_NOREX_NOSP: return true;
4868 case MCK_GR32_NOREX: return true;
4869 case MCK_Reg21: return true;
4870 case MCK_Reg29: return true;
4871 case MCK_GR32_NOAX: return true;
4872 case MCK_GR32_NOSP: return true;
4873 case MCK_GR32: return true;
4874 case MCK_Reg18: return true;
4875 case MCK_LOW32_ADDR_ACCESS: return true;
4876 case MCK_LOW32_ADDR_ACCESS_RBP: return true;
4877 }
4878
4879 case MCK_ECX:
4880 switch (B) {
4881 default: return false;
4882 case MCK_Reg24: return true;
4883 case MCK_Reg25: return true;
4884 case MCK_GR32_TC: return true;
4885 case MCK_GR32_ABCD: return true;
4886 case MCK_Reg26: return true;
4887 case MCK_Reg27: return true;
4888 case MCK_GR32_NOREX_NOSP: return true;
4889 case MCK_GR32_NOREX: return true;
4890 case MCK_Reg21: return true;
4891 case MCK_Reg29: return true;
4892 case MCK_GR32_NOAX: return true;
4893 case MCK_GR32_NOSP: return true;
4894 case MCK_GR32: return true;
4895 case MCK_Reg18: return true;
4896 case MCK_LOW32_ADDR_ACCESS: return true;
4897 case MCK_LOW32_ADDR_ACCESS_RBP: return true;
4898 }
4899
4900 case MCK_EDX:
4901 switch (B) {
4902 default: return false;
4903 case MCK_Reg24: return true;
4904 case MCK_GR32_AD: return true;
4905 case MCK_Reg25: return true;
4906 case MCK_GR32_TC: return true;
4907 case MCK_GR32_ABCD: return true;
4908 case MCK_Reg26: return true;
4909 case MCK_Reg27: return true;
4910 case MCK_GR32_NOREX_NOSP: return true;
4911 case MCK_GR32_NOREX: return true;
4912 case MCK_Reg21: return true;
4913 case MCK_Reg29: return true;
4914 case MCK_GR32_NOAX: return true;
4915 case MCK_GR32_NOSP: return true;
4916 case MCK_GR32: return true;
4917 case MCK_Reg18: return true;
4918 case MCK_LOW32_ADDR_ACCESS: return true;
4919 case MCK_LOW32_ADDR_ACCESS_RBP: return true;
4920 }
4921
4922 case MCK_ES:
4923 return B == MCK_SEGMENT_REG;
4924
4925 case MCK_FS:
4926 return B == MCK_SEGMENT_REG;
4927
4928 case MCK_GS:
4929 return B == MCK_SEGMENT_REG;
4930
4931 case MCK_RAX:
4932 switch (B) {
4933 default: return false;
4934 case MCK_GR64_AD: return true;
4935 case MCK_Reg34: return true;
4936 case MCK_Reg50: return true;
4937 case MCK_GR64_ABCD: return true;
4938 case MCK_Reg42: return true;
4939 case MCK_Reg45: return true;
4940 case MCK_Reg48: return true;
4941 case MCK_Reg46: return true;
4942 case MCK_Reg49: return true;
4943 case MCK_GR64_NOREX_NOSP: return true;
4944 case MCK_Reg37: return true;
4945 case MCK_Reg43: return true;
4946 case MCK_GR64_TCW64: return true;
4947 case MCK_GR64_NOREX: return true;
4948 case MCK_GR64_TC: return true;
4949 case MCK_GR64_NOSP: return true;
4950 case MCK_Reg38: return true;
4951 case MCK_GR64: return true;
4952 }
4953
4954 case MCK_RBX:
4955 switch (B) {
4956 default: return false;
4957 case MCK_Reg53: return true;
4958 case MCK_GR64_ABCD: return true;
4959 case MCK_Reg54: return true;
4960 case MCK_Reg55: return true;
4961 case MCK_GR64_NOREX_NOSP: return true;
4962 case MCK_Reg37: return true;
4963 case MCK_GR64_NOREX: return true;
4964 case MCK_Reg57: return true;
4965 case MCK_Reg56: return true;
4966 case MCK_GR64_NOSP: return true;
4967 case MCK_Reg38: return true;
4968 case MCK_GR64: return true;
4969 }
4970
4971 case MCK_RCX:
4972 switch (B) {
4973 default: return false;
4974 case MCK_Reg52: return true;
4975 case MCK_Reg34: return true;
4976 case MCK_Reg53: return true;
4977 case MCK_Reg50: return true;
4978 case MCK_Reg58: return true;
4979 case MCK_GR64_ABCD: return true;
4980 case MCK_Reg42: return true;
4981 case MCK_Reg61: return true;
4982 case MCK_Reg45: return true;
4983 case MCK_Reg48: return true;
4984 case MCK_Reg54: return true;
4985 case MCK_Reg60: return true;
4986 case MCK_Reg46: return true;
4987 case MCK_Reg49: return true;
4988 case MCK_Reg55: return true;
4989 case MCK_Reg59: return true;
4990 case MCK_GR64_NOREX_NOSP: return true;
4991 case MCK_Reg37: return true;
4992 case MCK_Reg43: return true;
4993 case MCK_GR64_TCW64: return true;
4994 case MCK_GR64_NOREX: return true;
4995 case MCK_GR64_TC: return true;
4996 case MCK_Reg57: return true;
4997 case MCK_Reg56: return true;
4998 case MCK_GR64_NOSP: return true;
4999 case MCK_Reg38: return true;
5000 case MCK_GR64: return true;
5001 }
5002
5003 case MCK_RDX:
5004 switch (B) {
5005 default: return false;
5006 case MCK_Reg52: return true;
5007 case MCK_GR64_AD: return true;
5008 case MCK_Reg34: return true;
5009 case MCK_Reg53: return true;
5010 case MCK_Reg50: return true;
5011 case MCK_Reg58: return true;
5012 case MCK_GR64_ABCD: return true;
5013 case MCK_Reg42: return true;
5014 case MCK_Reg61: return true;
5015 case MCK_Reg45: return true;
5016 case MCK_Reg48: return true;
5017 case MCK_Reg54: return true;
5018 case MCK_Reg60: return true;
5019 case MCK_Reg46: return true;
5020 case MCK_Reg49: return true;
5021 case MCK_Reg55: return true;
5022 case MCK_Reg59: return true;
5023 case MCK_GR64_NOREX_NOSP: return true;
5024 case MCK_Reg37: return true;
5025 case MCK_Reg43: return true;
5026 case MCK_GR64_TCW64: return true;
5027 case MCK_GR64_NOREX: return true;
5028 case MCK_GR64_TC: return true;
5029 case MCK_Reg57: return true;
5030 case MCK_Reg56: return true;
5031 case MCK_GR64_NOSP: return true;
5032 case MCK_Reg38: return true;
5033 case MCK_GR64: return true;
5034 }
5035
5036 case MCK_SS:
5037 return B == MCK_SEGMENT_REG;
5038
5039 case MCK_ST0:
5040 return B == MCK_RST;
5041
5042 case MCK_XMM0:
5043 switch (B) {
5044 default: return false;
5045 case MCK_VR128L: return true;
5046 case MCK_FR32: return true;
5047 case MCK_FR32X: return true;
5048 }
5049
5050 case MCK_Reg24:
5051 switch (B) {
5052 default: return false;
5053 case MCK_Reg25: return true;
5054 case MCK_GR32_TC: return true;
5055 case MCK_GR32_ABCD: return true;
5056 case MCK_Reg26: return true;
5057 case MCK_Reg27: return true;
5058 case MCK_GR32_NOREX_NOSP: return true;
5059 case MCK_GR32_NOREX: return true;
5060 case MCK_Reg21: return true;
5061 case MCK_Reg29: return true;
5062 case MCK_GR32_NOAX: return true;
5063 case MCK_GR32_NOSP: return true;
5064 case MCK_GR32: return true;
5065 case MCK_Reg18: return true;
5066 case MCK_LOW32_ADDR_ACCESS: return true;
5067 case MCK_LOW32_ADDR_ACCESS_RBP: return true;
5068 }
5069
5070 case MCK_Reg52:
5071 switch (B) {
5072 default: return false;
5073 case MCK_Reg34: return true;
5074 case MCK_Reg53: return true;
5075 case MCK_Reg50: return true;
5076 case MCK_Reg58: return true;
5077 case MCK_GR64_ABCD: return true;
5078 case MCK_Reg42: return true;
5079 case MCK_Reg61: return true;
5080 case MCK_Reg45: return true;
5081 case MCK_Reg48: return true;
5082 case MCK_Reg54: return true;
5083 case MCK_Reg60: return true;
5084 case MCK_Reg46: return true;
5085 case MCK_Reg49: return true;
5086 case MCK_Reg55: return true;
5087 case MCK_Reg59: return true;
5088 case MCK_GR64_NOREX_NOSP: return true;
5089 case MCK_Reg37: return true;
5090 case MCK_Reg43: return true;
5091 case MCK_GR64_TCW64: return true;
5092 case MCK_GR64_NOREX: return true;
5093 case MCK_GR64_TC: return true;
5094 case MCK_Reg57: return true;
5095 case MCK_Reg56: return true;
5096 case MCK_GR64_NOSP: return true;
5097 case MCK_Reg38: return true;
5098 case MCK_GR64: return true;
5099 }
5100
5101 case MCK_Reg65:
5102 switch (B) {
5103 default: return false;
5104 case MCK_GR64_NOREX: return true;
5105 case MCK_GR64: return true;
5106 case MCK_LOW32_ADDR_ACCESS_RBP: return true;
5107 }
5108
5109 case MCK_GR32_AD:
5110 switch (B) {
5111 default: return false;
5112 case MCK_GR32_TC: return true;
5113 case MCK_GR32_ABCD: return true;
5114 case MCK_GR32_NOREX_NOSP: return true;
5115 case MCK_GR32_NOREX: return true;
5116 case MCK_Reg21: return true;
5117 case MCK_GR32_NOSP: return true;
5118 case MCK_GR32: return true;
5119 case MCK_Reg18: return true;
5120 case MCK_LOW32_ADDR_ACCESS: return true;
5121 case MCK_LOW32_ADDR_ACCESS_RBP: return true;
5122 }
5123
5124 case MCK_GR64_AD:
5125 switch (B) {
5126 default: return false;
5127 case MCK_Reg34: return true;
5128 case MCK_Reg50: return true;
5129 case MCK_GR64_ABCD: return true;
5130 case MCK_Reg42: return true;
5131 case MCK_Reg45: return true;
5132 case MCK_Reg48: return true;
5133 case MCK_Reg46: return true;
5134 case MCK_Reg49: return true;
5135 case MCK_GR64_NOREX_NOSP: return true;
5136 case MCK_Reg37: return true;
5137 case MCK_Reg43: return true;
5138 case MCK_GR64_TCW64: return true;
5139 case MCK_GR64_NOREX: return true;
5140 case MCK_GR64_TC: return true;
5141 case MCK_GR64_NOSP: return true;
5142 case MCK_Reg38: return true;
5143 case MCK_GR64: return true;
5144 }
5145
5146 case MCK_Reg25:
5147 switch (B) {
5148 default: return false;
5149 case MCK_GR32_ABCD: return true;
5150 case MCK_Reg26: return true;
5151 case MCK_Reg27: return true;
5152 case MCK_GR32_NOREX_NOSP: return true;
5153 case MCK_GR32_NOREX: return true;
5154 case MCK_Reg21: return true;
5155 case MCK_Reg29: return true;
5156 case MCK_GR32_NOAX: return true;
5157 case MCK_GR32_NOSP: return true;
5158 case MCK_GR32: return true;
5159 case MCK_Reg18: return true;
5160 case MCK_LOW32_ADDR_ACCESS: return true;
5161 case MCK_LOW32_ADDR_ACCESS_RBP: return true;
5162 }
5163
5164 case MCK_Reg34:
5165 switch (B) {
5166 default: return false;
5167 case MCK_Reg50: return true;
5168 case MCK_GR64_ABCD: return true;
5169 case MCK_Reg42: return true;
5170 case MCK_Reg45: return true;
5171 case MCK_Reg48: return true;
5172 case MCK_Reg46: return true;
5173 case MCK_Reg49: return true;
5174 case MCK_GR64_NOREX_NOSP: return true;
5175 case MCK_Reg37: return true;
5176 case MCK_Reg43: return true;
5177 case MCK_GR64_TCW64: return true;
5178 case MCK_GR64_NOREX: return true;
5179 case MCK_GR64_TC: return true;
5180 case MCK_GR64_NOSP: return true;
5181 case MCK_Reg38: return true;
5182 case MCK_GR64: return true;
5183 }
5184
5185 case MCK_Reg53:
5186 switch (B) {
5187 default: return false;
5188 case MCK_GR64_ABCD: return true;
5189 case MCK_Reg54: return true;
5190 case MCK_Reg55: return true;
5191 case MCK_GR64_NOREX_NOSP: return true;
5192 case MCK_Reg37: return true;
5193 case MCK_GR64_NOREX: return true;
5194 case MCK_Reg57: return true;
5195 case MCK_Reg56: return true;
5196 case MCK_GR64_NOSP: return true;
5197 case MCK_Reg38: return true;
5198 case MCK_GR64: return true;
5199 }
5200
5201 case MCK_GR32_TC:
5202 switch (B) {
5203 default: return false;
5204 case MCK_GR32_ABCD: return true;
5205 case MCK_GR32_NOREX_NOSP: return true;
5206 case MCK_GR32_NOREX: return true;
5207 case MCK_Reg21: return true;
5208 case MCK_GR32_NOSP: return true;
5209 case MCK_GR32: return true;
5210 case MCK_Reg18: return true;
5211 case MCK_LOW32_ADDR_ACCESS: return true;
5212 case MCK_LOW32_ADDR_ACCESS_RBP: return true;
5213 }
5214
5215 case MCK_Reg50:
5216 switch (B) {
5217 default: return false;
5218 case MCK_Reg45: return true;
5219 case MCK_Reg49: return true;
5220 case MCK_GR64_TCW64: return true;
5221 case MCK_GR64_NOREX: return true;
5222 case MCK_GR64_TC: return true;
5223 case MCK_GR64: return true;
5224 }
5225
5226 case MCK_Reg58:
5227 switch (B) {
5228 default: return false;
5229 case MCK_Reg42: return true;
5230 case MCK_Reg45: return true;
5231 case MCK_Reg54: return true;
5232 case MCK_Reg55: return true;
5233 case MCK_Reg59: return true;
5234 case MCK_GR64_NOREX_NOSP: return true;
5235 case MCK_Reg37: return true;
5236 case MCK_Reg43: return true;
5237 case MCK_GR64_NOREX: return true;
5238 case MCK_GR64_TC: return true;
5239 case MCK_Reg57: return true;
5240 case MCK_Reg56: return true;
5241 case MCK_GR64_NOSP: return true;
5242 case MCK_Reg38: return true;
5243 case MCK_GR64: return true;
5244 }
5245
5246 case MCK_GR16_ABCD:
5247 switch (B) {
5248 default: return false;
5249 case MCK_GR16_NOREX: return true;
5250 case MCK_GR16: return true;
5251 }
5252
5253 case MCK_GR32_ABCD:
5254 switch (B) {
5255 default: return false;
5256 case MCK_GR32_NOREX_NOSP: return true;
5257 case MCK_GR32_NOREX: return true;
5258 case MCK_Reg21: return true;
5259 case MCK_GR32_NOSP: return true;
5260 case MCK_GR32: return true;
5261 case MCK_Reg18: return true;
5262 case MCK_LOW32_ADDR_ACCESS: return true;
5263 case MCK_LOW32_ADDR_ACCESS_RBP: return true;
5264 }
5265
5266 case MCK_GR64_ABCD:
5267 switch (B) {
5268 default: return false;
5269 case MCK_GR64_NOREX_NOSP: return true;
5270 case MCK_Reg37: return true;
5271 case MCK_GR64_NOREX: return true;
5272 case MCK_GR64_NOSP: return true;
5273 case MCK_Reg38: return true;
5274 case MCK_GR64: return true;
5275 }
5276
5277 case MCK_GR8_ABCD_H:
5278 switch (B) {
5279 default: return false;
5280 case MCK_GR8_NOREX: return true;
5281 case MCK_GR8: return true;
5282 }
5283
5284 case MCK_GR8_ABCD_L:
5285 switch (B) {
5286 default: return false;
5287 case MCK_GR8_NOREX: return true;
5288 case MCK_GR8: return true;
5289 }
5290
5291 case MCK_Reg42:
5292 switch (B) {
5293 default: return false;
5294 case MCK_Reg45: return true;
5295 case MCK_GR64_NOREX_NOSP: return true;
5296 case MCK_Reg37: return true;
5297 case MCK_Reg43: return true;
5298 case MCK_GR64_NOREX: return true;
5299 case MCK_GR64_TC: return true;
5300 case MCK_GR64_NOSP: return true;
5301 case MCK_Reg38: return true;
5302 case MCK_GR64: return true;
5303 }
5304
5305 case MCK_Reg61:
5306 switch (B) {
5307 default: return false;
5308 case MCK_Reg48: return true;
5309 case MCK_Reg60: return true;
5310 case MCK_Reg46: return true;
5311 case MCK_Reg49: return true;
5312 case MCK_Reg59: return true;
5313 case MCK_Reg43: return true;
5314 case MCK_GR64_TCW64: return true;
5315 case MCK_GR64_TC: return true;
5316 case MCK_Reg57: return true;
5317 case MCK_Reg56: return true;
5318 case MCK_GR64_NOSP: return true;
5319 case MCK_Reg38: return true;
5320 case MCK_GR64: return true;
5321 }
5322
5323 case MCK_Reg26:
5324 switch (B) {
5325 default: return false;
5326 case MCK_Reg27: return true;
5327 case MCK_GR32_NOREX_NOSP: return true;
5328 case MCK_GR32_NOREX: return true;
5329 case MCK_Reg21: return true;
5330 case MCK_Reg29: return true;
5331 case MCK_GR32_NOAX: return true;
5332 case MCK_GR32_NOSP: return true;
5333 case MCK_GR32: return true;
5334 case MCK_Reg18: return true;
5335 case MCK_LOW32_ADDR_ACCESS: return true;
5336 case MCK_LOW32_ADDR_ACCESS_RBP: return true;
5337 }
5338
5339 case MCK_Reg45:
5340 switch (B) {
5341 default: return false;
5342 case MCK_GR64_NOREX: return true;
5343 case MCK_GR64_TC: return true;
5344 case MCK_GR64: return true;
5345 }
5346
5347 case MCK_Reg48:
5348 switch (B) {
5349 default: return false;
5350 case MCK_Reg46: return true;
5351 case MCK_Reg49: return true;
5352 case MCK_Reg43: return true;
5353 case MCK_GR64_TCW64: return true;
5354 case MCK_GR64_TC: return true;
5355 case MCK_GR64_NOSP: return true;
5356 case MCK_Reg38: return true;
5357 case MCK_GR64: return true;
5358 }
5359
5360 case MCK_Reg54:
5361 switch (B) {
5362 default: return false;
5363 case MCK_Reg55: return true;
5364 case MCK_GR64_NOREX_NOSP: return true;
5365 case MCK_Reg37: return true;
5366 case MCK_GR64_NOREX: return true;
5367 case MCK_Reg57: return true;
5368 case MCK_Reg56: return true;
5369 case MCK_GR64_NOSP: return true;
5370 case MCK_Reg38: return true;
5371 case MCK_GR64: return true;
5372 }
5373
5374 case MCK_Reg60:
5375 switch (B) {
5376 default: return false;
5377 case MCK_Reg46: return true;
5378 case MCK_GR64_TCW64: return true;
5379 case MCK_Reg57: return true;
5380 case MCK_Reg56: return true;
5381 case MCK_GR64_NOSP: return true;
5382 case MCK_Reg38: return true;
5383 case MCK_GR64: return true;
5384 }
5385
5386 case MCK_Reg27:
5387 switch (B) {
5388 default: return false;
5389 case MCK_GR32_NOREX: return true;
5390 case MCK_Reg21: return true;
5391 case MCK_GR32_NOAX: return true;
5392 case MCK_GR32: return true;
5393 case MCK_Reg18: return true;
5394 case MCK_LOW32_ADDR_ACCESS: return true;
5395 case MCK_LOW32_ADDR_ACCESS_RBP: return true;
5396 }
5397
5398 case MCK_Reg46:
5399 switch (B) {
5400 default: return false;
5401 case MCK_GR64_TCW64: return true;
5402 case MCK_GR64_NOSP: return true;
5403 case MCK_Reg38: return true;
5404 case MCK_GR64: return true;
5405 }
5406
5407 case MCK_Reg49:
5408 switch (B) {
5409 default: return false;
5410 case MCK_GR64_TCW64: return true;
5411 case MCK_GR64_TC: return true;
5412 case MCK_GR64: return true;
5413 }
5414
5415 case MCK_Reg55:
5416 switch (B) {
5417 default: return false;
5418 case MCK_Reg37: return true;
5419 case MCK_GR64_NOREX: return true;
5420 case MCK_Reg56: return true;
5421 case MCK_Reg38: return true;
5422 case MCK_GR64: return true;
5423 }
5424
5425 case MCK_Reg59:
5426 switch (B) {
5427 default: return false;
5428 case MCK_Reg43: return true;
5429 case MCK_GR64_TC: return true;
5430 case MCK_Reg57: return true;
5431 case MCK_Reg56: return true;
5432 case MCK_GR64_NOSP: return true;
5433 case MCK_Reg38: return true;
5434 case MCK_GR64: return true;
5435 }
5436
5437 case MCK_GR32_NOREX_NOSP:
5438 switch (B) {
5439 default: return false;
5440 case MCK_GR32_NOREX: return true;
5441 case MCK_Reg21: return true;
5442 case MCK_GR32_NOSP: return true;
5443 case MCK_GR32: return true;
5444 case MCK_Reg18: return true;
5445 case MCK_LOW32_ADDR_ACCESS: return true;
5446 case MCK_LOW32_ADDR_ACCESS_RBP: return true;
5447 }
5448
5449 case MCK_GR64_NOREX_NOSP:
5450 switch (B) {
5451 default: return false;
5452 case MCK_Reg37: return true;
5453 case MCK_GR64_NOREX: return true;
5454 case MCK_GR64_NOSP: return true;
5455 case MCK_Reg38: return true;
5456 case MCK_GR64: return true;
5457 }
5458
5459 case MCK_VK16WM:
5460 return B == MCK_VK1;
5461
5462 case MCK_Reg37:
5463 switch (B) {
5464 default: return false;
5465 case MCK_GR64_NOREX: return true;
5466 case MCK_Reg38: return true;
5467 case MCK_GR64: return true;
5468 }
5469
5470 case MCK_Reg43:
5471 switch (B) {
5472 default: return false;
5473 case MCK_GR64_TC: return true;
5474 case MCK_GR64_NOSP: return true;
5475 case MCK_Reg38: return true;
5476 case MCK_GR64: return true;
5477 }
5478
5479 case MCK_Reg78:
5480 switch (B) {
5481 default: return false;
5482 case MCK_Reg79: return true;
5483 case MCK_VR512: return true;
5484 }
5485
5486 case MCK_Reg81:
5487 switch (B) {
5488 default: return false;
5489 case MCK_Reg79: return true;
5490 case MCK_VR512: return true;
5491 }
5492
5493 case MCK_GR16_NOREX:
5494 return B == MCK_GR16;
5495
5496 case MCK_GR32_NOREX:
5497 switch (B) {
5498 default: return false;
5499 case MCK_Reg21: return true;
5500 case MCK_GR32: return true;
5501 case MCK_Reg18: return true;
5502 case MCK_LOW32_ADDR_ACCESS: return true;
5503 case MCK_LOW32_ADDR_ACCESS_RBP: return true;
5504 }
5505
5506 case MCK_GR64_TCW64:
5507 return B == MCK_GR64;
5508
5509 case MCK_GR8_NOREX:
5510 return B == MCK_GR8;
5511
5512 case MCK_VR128H:
5513 switch (B) {
5514 default: return false;
5515 case MCK_FR32: return true;
5516 case MCK_FR32X: return true;
5517 }
5518
5519 case MCK_VR128L:
5520 switch (B) {
5521 default: return false;
5522 case MCK_FR32: return true;
5523 case MCK_FR32X: return true;
5524 }
5525
5526 case MCK_VR256H:
5527 switch (B) {
5528 default: return false;
5529 case MCK_VR256: return true;
5530 case MCK_VR256X: return true;
5531 }
5532
5533 case MCK_VR256L:
5534 switch (B) {
5535 default: return false;
5536 case MCK_VR256: return true;
5537 case MCK_VR256X: return true;
5538 }
5539
5540 case MCK_Reg21:
5541 switch (B) {
5542 default: return false;
5543 case MCK_Reg18: return true;
5544 case MCK_LOW32_ADDR_ACCESS_RBP: return true;
5545 }
5546
5547 case MCK_GR64_NOREX:
5548 return B == MCK_GR64;
5549
5550 case MCK_GR64_TC:
5551 return B == MCK_GR64;
5552
5553 case MCK_Reg29:
5554 switch (B) {
5555 default: return false;
5556 case MCK_GR32_NOAX: return true;
5557 case MCK_GR32_NOSP: return true;
5558 case MCK_GR32: return true;
5559 case MCK_Reg18: return true;
5560 case MCK_LOW32_ADDR_ACCESS: return true;
5561 case MCK_LOW32_ADDR_ACCESS_RBP: return true;
5562 }
5563
5564 case MCK_Reg57:
5565 switch (B) {
5566 default: return false;
5567 case MCK_Reg56: return true;
5568 case MCK_GR64_NOSP: return true;
5569 case MCK_Reg38: return true;
5570 case MCK_GR64: return true;
5571 }
5572
5573 case MCK_Reg56:
5574 switch (B) {
5575 default: return false;
5576 case MCK_Reg38: return true;
5577 case MCK_GR64: return true;
5578 }
5579
5580 case MCK_GR32_NOAX:
5581 switch (B) {
5582 default: return false;
5583 case MCK_GR32: return true;
5584 case MCK_Reg18: return true;
5585 case MCK_LOW32_ADDR_ACCESS: return true;
5586 case MCK_LOW32_ADDR_ACCESS_RBP: return true;
5587 }
5588
5589 case MCK_GR32_NOSP:
5590 switch (B) {
5591 default: return false;
5592 case MCK_GR32: return true;
5593 case MCK_Reg18: return true;
5594 case MCK_LOW32_ADDR_ACCESS: return true;
5595 case MCK_LOW32_ADDR_ACCESS_RBP: return true;
5596 }
5597
5598 case MCK_GR64_NOSP:
5599 switch (B) {
5600 default: return false;
5601 case MCK_Reg38: return true;
5602 case MCK_GR64: return true;
5603 }
5604
5605 case MCK_Reg38:
5606 return B == MCK_GR64;
5607
5608 case MCK_Reg79:
5609 return B == MCK_VR512;
5610
5611 case MCK_FR32:
5612 return B == MCK_FR32X;
5613
5614 case MCK_GR32:
5615 switch (B) {
5616 default: return false;
5617 case MCK_Reg18: return true;
5618 case MCK_LOW32_ADDR_ACCESS: return true;
5619 case MCK_LOW32_ADDR_ACCESS_RBP: return true;
5620 }
5621
5622 case MCK_VR256:
5623 return B == MCK_VR256X;
5624
5625 case MCK_Reg18:
5626 return B == MCK_LOW32_ADDR_ACCESS_RBP;
5627
5628 case MCK_LOW32_ADDR_ACCESS:
5629 return B == MCK_LOW32_ADDR_ACCESS_RBP;
5630
5631 case MCK_ImmSExti64i8:
5632 switch (B) {
5633 default: return false;
5634 case MCK_ImmSExti16i8: return true;
5635 case MCK_ImmSExti32i8: return true;
5636 case MCK_ImmSExti64i32: return true;
5637 case MCK_Imm: return true;
5638 }
5639
5640 case MCK_ImmSExti16i8:
5641 switch (B) {
5642 default: return false;
5643 case MCK_ImmSExti64i32: return true;
5644 case MCK_Imm: return true;
5645 }
5646
5647 case MCK_ImmSExti32i8:
5648 return B == MCK_Imm;
5649
5650 case MCK_ImmSExti64i32:
5651 return B == MCK_Imm;
5652
5653 case MCK_AbsMem16:
5654 switch (B) {
5655 default: return false;
5656 case MCK_AbsMem: return true;
5657 case MCK_Mem: return true;
5658 }
5659
5660 case MCK_DstIdx16:
5661 switch (B) {
5662 default: return false;
5663 case MCK_Mem16: return true;
5664 case MCK_Mem: return true;
5665 }
5666
5667 case MCK_DstIdx32:
5668 switch (B) {
5669 default: return false;
5670 case MCK_Mem32: return true;
5671 case MCK_Mem: return true;
5672 }
5673
5674 case MCK_DstIdx64:
5675 switch (B) {
5676 default: return false;
5677 case MCK_Mem64: return true;
5678 case MCK_Mem: return true;
5679 }
5680
5681 case MCK_DstIdx8:
5682 switch (B) {
5683 default: return false;
5684 case MCK_Mem8: return true;
5685 case MCK_Mem: return true;
5686 }
5687
5688 case MCK_MemOffs16_16:
5689 switch (B) {
5690 default: return false;
5691 case MCK_Mem16: return true;
5692 case MCK_Mem: return true;
5693 }
5694
5695 case MCK_MemOffs16_32:
5696 switch (B) {
5697 default: return false;
5698 case MCK_Mem32: return true;
5699 case MCK_Mem: return true;
5700 }
5701
5702 case MCK_MemOffs16_8:
5703 switch (B) {
5704 default: return false;
5705 case MCK_Mem8: return true;
5706 case MCK_Mem: return true;
5707 }
5708
5709 case MCK_MemOffs32_16:
5710 switch (B) {
5711 default: return false;
5712 case MCK_Mem16: return true;
5713 case MCK_Mem: return true;
5714 }
5715
5716 case MCK_MemOffs32_32:
5717 switch (B) {
5718 default: return false;
5719 case MCK_Mem32: return true;
5720 case MCK_Mem: return true;
5721 }
5722
5723 case MCK_MemOffs32_64:
5724 switch (B) {
5725 default: return false;
5726 case MCK_Mem64: return true;
5727 case MCK_Mem: return true;
5728 }
5729
5730 case MCK_MemOffs32_8:
5731 switch (B) {
5732 default: return false;
5733 case MCK_Mem8: return true;
5734 case MCK_Mem: return true;
5735 }
5736
5737 case MCK_MemOffs64_16:
5738 switch (B) {
5739 default: return false;
5740 case MCK_Mem16: return true;
5741 case MCK_Mem: return true;
5742 }
5743
5744 case MCK_MemOffs64_32:
5745 switch (B) {
5746 default: return false;
5747 case MCK_Mem32: return true;
5748 case MCK_Mem: return true;
5749 }
5750
5751 case MCK_MemOffs64_64:
5752 switch (B) {
5753 default: return false;
5754 case MCK_Mem64: return true;
5755 case MCK_Mem: return true;
5756 }
5757
5758 case MCK_MemOffs64_8:
5759 switch (B) {
5760 default: return false;
5761 case MCK_Mem8: return true;
5762 case MCK_Mem: return true;
5763 }
5764
5765 case MCK_SrcIdx16:
5766 switch (B) {
5767 default: return false;
5768 case MCK_Mem16: return true;
5769 case MCK_Mem: return true;
5770 }
5771
5772 case MCK_SrcIdx32:
5773 switch (B) {
5774 default: return false;
5775 case MCK_Mem32: return true;
5776 case MCK_Mem: return true;
5777 }
5778
5779 case MCK_SrcIdx64:
5780 switch (B) {
5781 default: return false;
5782 case MCK_Mem64: return true;
5783 case MCK_Mem: return true;
5784 }
5785
5786 case MCK_SrcIdx8:
5787 switch (B) {
5788 default: return false;
5789 case MCK_Mem8: return true;
5790 case MCK_Mem: return true;
5791 }
5792
5793 case MCK_AbsMem:
5794 return B == MCK_Mem;
5795
5796 case MCK_Mem128:
5797 return B == MCK_Mem;
5798
5799 case MCK_Mem128_RC128:
5800 return B == MCK_Mem;
5801
5802 case MCK_Mem128_RC128X:
5803 return B == MCK_Mem;
5804
5805 case MCK_Mem128_RC256:
5806 return B == MCK_Mem;
5807
5808 case MCK_Mem128_RC256X:
5809 return B == MCK_Mem;
5810
5811 case MCK_Mem16:
5812 return B == MCK_Mem;
5813
5814 case MCK_Mem256:
5815 return B == MCK_Mem;
5816
5817 case MCK_Mem256_RC128:
5818 return B == MCK_Mem;
5819
5820 case MCK_Mem256_RC128X:
5821 return B == MCK_Mem;
5822
5823 case MCK_Mem256_RC256:
5824 return B == MCK_Mem;
5825
5826 case MCK_Mem256_RC256X:
5827 return B == MCK_Mem;
5828
5829 case MCK_Mem256_RC512:
5830 return B == MCK_Mem;
5831
5832 case MCK_Mem32:
5833 return B == MCK_Mem;
5834
5835 case MCK_Mem512:
5836 return B == MCK_Mem;
5837
5838 case MCK_Mem512_RC256X:
5839 return B == MCK_Mem;
5840
5841 case MCK_Mem512_RC512:
5842 return B == MCK_Mem;
5843
5844 case MCK_Mem64:
5845 return B == MCK_Mem;
5846
5847 case MCK_Mem64_RC128:
5848 return B == MCK_Mem;
5849
5850 case MCK_Mem64_RC128X:
5851 return B == MCK_Mem;
5852
5853 case MCK_Mem80:
5854 return B == MCK_Mem;
5855
5856 case MCK_Mem8:
5857 return B == MCK_Mem;
5858 }
5859}
5860
5861static unsigned validateOperandClass(MCParsedAsmOperand &GOp, MatchClassKind Kind) {
5862 X86Operand &Operand = (X86Operand&)GOp;
5863 if (Kind == InvalidMatchClass)
5864 return MCTargetAsmParser::Match_InvalidOperand;
5865
5866 if (Operand.isToken() && Kind <= MCK_LAST_TOKEN)
5867 return isSubclass(matchTokenString(Operand.getToken()), Kind) ?
5868 MCTargetAsmParser::Match_Success :
5869 MCTargetAsmParser::Match_InvalidOperand;
5870
5871 switch (Kind) {
5872 default: break;
5873 // 'AVX512RC' class
5874 case MCK_AVX512RC:
5875 if (Operand.isAVX512RC())
5876 return MCTargetAsmParser::Match_Success;
5877 break;
5878 // 'ImmSExti64i8' class
5879 case MCK_ImmSExti64i8:
5880 if (Operand.isImmSExti64i8())
5881 return MCTargetAsmParser::Match_Success;
5882 break;
5883 // 'ImmSExti16i8' class
5884 case MCK_ImmSExti16i8:
5885 if (Operand.isImmSExti16i8())
5886 return MCTargetAsmParser::Match_Success;
5887 break;
5888 // 'ImmSExti32i8' class
5889 case MCK_ImmSExti32i8:
5890 if (Operand.isImmSExti32i8())
5891 return MCTargetAsmParser::Match_Success;
5892 break;
5893 // 'ImmSExti64i32' class
5894 case MCK_ImmSExti64i32:
5895 if (Operand.isImmSExti64i32())
5896 return MCTargetAsmParser::Match_Success;
5897 break;
5898 // 'Imm' class
5899 case MCK_Imm:
5900 if (Operand.isImm())
5901 return MCTargetAsmParser::Match_Success;
5902 break;
5903 // 'ImmUnsignedi8' class
5904 case MCK_ImmUnsignedi8:
5905 if (Operand.isImmUnsignedi8())
5906 return MCTargetAsmParser::Match_Success;
5907 break;
5908 // 'GR32orGR64' class
5909 case MCK_GR32orGR64:
5910 if (Operand.isGR32orGR64())
5911 return MCTargetAsmParser::Match_Success;
5912 break;
5913 // 'AbsMem16' class
5914 case MCK_AbsMem16:
5915 if (Operand.isAbsMem16())
5916 return MCTargetAsmParser::Match_Success;
5917 break;
5918 // 'DstIdx16' class
5919 case MCK_DstIdx16:
5920 if (Operand.isDstIdx16())
5921 return MCTargetAsmParser::Match_Success;
5922 break;
5923 // 'DstIdx32' class
5924 case MCK_DstIdx32:
5925 if (Operand.isDstIdx32())
5926 return MCTargetAsmParser::Match_Success;
5927 break;
5928 // 'DstIdx64' class
5929 case MCK_DstIdx64:
5930 if (Operand.isDstIdx64())
5931 return MCTargetAsmParser::Match_Success;
5932 break;
5933 // 'DstIdx8' class
5934 case MCK_DstIdx8:
5935 if (Operand.isDstIdx8())
5936 return MCTargetAsmParser::Match_Success;
5937 break;
5938 // 'MemOffs16_16' class
5939 case MCK_MemOffs16_16:
5940 if (Operand.isMemOffs16_16())
5941 return MCTargetAsmParser::Match_Success;
5942 break;
5943 // 'MemOffs16_32' class
5944 case MCK_MemOffs16_32:
5945 if (Operand.isMemOffs16_32())
5946 return MCTargetAsmParser::Match_Success;
5947 break;
5948 // 'MemOffs16_8' class
5949 case MCK_MemOffs16_8:
5950 if (Operand.isMemOffs16_8())
5951 return MCTargetAsmParser::Match_Success;
5952 break;
5953 // 'MemOffs32_16' class
5954 case MCK_MemOffs32_16:
5955 if (Operand.isMemOffs32_16())
5956 return MCTargetAsmParser::Match_Success;
5957 break;
5958 // 'MemOffs32_32' class
5959 case MCK_MemOffs32_32:
5960 if (Operand.isMemOffs32_32())
5961 return MCTargetAsmParser::Match_Success;
5962 break;
5963 // 'MemOffs32_64' class
5964 case MCK_MemOffs32_64:
5965 if (Operand.isMemOffs32_64())
5966 return MCTargetAsmParser::Match_Success;
5967 break;
5968 // 'MemOffs32_8' class
5969 case MCK_MemOffs32_8:
5970 if (Operand.isMemOffs32_8())
5971 return MCTargetAsmParser::Match_Success;
5972 break;
5973 // 'MemOffs64_16' class
5974 case MCK_MemOffs64_16:
5975 if (Operand.isMemOffs64_16())
5976 return MCTargetAsmParser::Match_Success;
5977 break;
5978 // 'MemOffs64_32' class
5979 case MCK_MemOffs64_32:
5980 if (Operand.isMemOffs64_32())
5981 return MCTargetAsmParser::Match_Success;
5982 break;
5983 // 'MemOffs64_64' class
5984 case MCK_MemOffs64_64:
5985 if (Operand.isMemOffs64_64())
5986 return MCTargetAsmParser::Match_Success;
5987 break;
5988 // 'MemOffs64_8' class
5989 case MCK_MemOffs64_8:
5990 if (Operand.isMemOffs64_8())
5991 return MCTargetAsmParser::Match_Success;
5992 break;
5993 // 'SrcIdx16' class
5994 case MCK_SrcIdx16:
5995 if (Operand.isSrcIdx16())
5996 return MCTargetAsmParser::Match_Success;
5997 break;
5998 // 'SrcIdx32' class
5999 case MCK_SrcIdx32:
6000 if (Operand.isSrcIdx32())
6001 return MCTargetAsmParser::Match_Success;
6002 break;
6003 // 'SrcIdx64' class
6004 case MCK_SrcIdx64:
6005 if (Operand.isSrcIdx64())
6006 return MCTargetAsmParser::Match_Success;
6007 break;
6008 // 'SrcIdx8' class
6009 case MCK_SrcIdx8:
6010 if (Operand.isSrcIdx8())
6011 return MCTargetAsmParser::Match_Success;
6012 break;
6013 // 'AbsMem' class
6014 case MCK_AbsMem:
6015 if (Operand.isAbsMem())
6016 return MCTargetAsmParser::Match_Success;
6017 break;
6018 // 'Mem128' class
6019 case MCK_Mem128:
6020 if (Operand.isMem128())
6021 return MCTargetAsmParser::Match_Success;
6022 break;
6023 // 'Mem128_RC128' class
6024 case MCK_Mem128_RC128:
6025 if (Operand.isMem128_RC128())
6026 return MCTargetAsmParser::Match_Success;
6027 break;
6028 // 'Mem128_RC128X' class
6029 case MCK_Mem128_RC128X:
6030 if (Operand.isMem128_RC128X())
6031 return MCTargetAsmParser::Match_Success;
6032 break;
6033 // 'Mem128_RC256' class
6034 case MCK_Mem128_RC256:
6035 if (Operand.isMem128_RC256())
6036 return MCTargetAsmParser::Match_Success;
6037 break;
6038 // 'Mem128_RC256X' class
6039 case MCK_Mem128_RC256X:
6040 if (Operand.isMem128_RC256X())
6041 return MCTargetAsmParser::Match_Success;
6042 break;
6043 // 'Mem16' class
6044 case MCK_Mem16:
6045 if (Operand.isMem16())
6046 return MCTargetAsmParser::Match_Success;
6047 break;
6048 // 'Mem256' class
6049 case MCK_Mem256:
6050 if (Operand.isMem256())
6051 return MCTargetAsmParser::Match_Success;
6052 break;
6053 // 'Mem256_RC128' class
6054 case MCK_Mem256_RC128:
6055 if (Operand.isMem256_RC128())
6056 return MCTargetAsmParser::Match_Success;
6057 break;
6058 // 'Mem256_RC128X' class
6059 case MCK_Mem256_RC128X:
6060 if (Operand.isMem256_RC128X())
6061 return MCTargetAsmParser::Match_Success;
6062 break;
6063 // 'Mem256_RC256' class
6064 case MCK_Mem256_RC256:
6065 if (Operand.isMem256_RC256())
6066 return MCTargetAsmParser::Match_Success;
6067 break;
6068 // 'Mem256_RC256X' class
6069 case MCK_Mem256_RC256X:
6070 if (Operand.isMem256_RC256X())
6071 return MCTargetAsmParser::Match_Success;
6072 break;
6073 // 'Mem256_RC512' class
6074 case MCK_Mem256_RC512:
6075 if (Operand.isMem256_RC512())
6076 return MCTargetAsmParser::Match_Success;
6077 break;
6078 // 'Mem32' class
6079 case MCK_Mem32:
6080 if (Operand.isMem32())
6081 return MCTargetAsmParser::Match_Success;
6082 break;
6083 // 'Mem512' class
6084 case MCK_Mem512:
6085 if (Operand.isMem512())
6086 return MCTargetAsmParser::Match_Success;
6087 break;
6088 // 'Mem512_RC256X' class
6089 case MCK_Mem512_RC256X:
6090 if (Operand.isMem512_RC256X())
6091 return MCTargetAsmParser::Match_Success;
6092 break;
6093 // 'Mem512_RC512' class
6094 case MCK_Mem512_RC512:
6095 if (Operand.isMem512_RC512())
6096 return MCTargetAsmParser::Match_Success;
6097 break;
6098 // 'Mem64' class
6099 case MCK_Mem64:
6100 if (Operand.isMem64())
6101 return MCTargetAsmParser::Match_Success;
6102 break;
6103 // 'Mem64_RC128' class
6104 case MCK_Mem64_RC128:
6105 if (Operand.isMem64_RC128())
6106 return MCTargetAsmParser::Match_Success;
6107 break;
6108 // 'Mem64_RC128X' class
6109 case MCK_Mem64_RC128X:
6110 if (Operand.isMem64_RC128X())
6111 return MCTargetAsmParser::Match_Success;
6112 break;
6113 // 'Mem80' class
6114 case MCK_Mem80:
6115 if (Operand.isMem80())
6116 return MCTargetAsmParser::Match_Success;
6117 break;
6118 // 'Mem8' class
6119 case MCK_Mem8:
6120 if (Operand.isMem8())
6121 return MCTargetAsmParser::Match_Success;
6122 break;
6123 // 'Mem' class
6124 case MCK_Mem:
6125 if (Operand.isMem())
6126 return MCTargetAsmParser::Match_Success;
6127 break;
6128 } // end switch (Kind)
6129
6130 if (Operand.isReg()) {
6131 MatchClassKind OpKind;
6132 switch (Operand.getReg()) {
6133 default: OpKind = InvalidMatchClass; break;
6134 case X86::AL: OpKind = MCK_AL; break;
6135 case X86::DL: OpKind = MCK_GR8_ABCD_L; break;
6136 case X86::CL: OpKind = MCK_CL; break;
6137 case X86::BL: OpKind = MCK_GR8_ABCD_L; break;
6138 case X86::AH: OpKind = MCK_GR8_ABCD_H; break;
6139 case X86::DH: OpKind = MCK_GR8_ABCD_H; break;
6140 case X86::CH: OpKind = MCK_GR8_ABCD_H; break;
6141 case X86::BH: OpKind = MCK_GR8_ABCD_H; break;
6142 case X86::SIL: OpKind = MCK_GR8; break;
6143 case X86::DIL: OpKind = MCK_GR8; break;
6144 case X86::BPL: OpKind = MCK_GR8; break;
6145 case X86::SPL: OpKind = MCK_GR8; break;
6146 case X86::R8B: OpKind = MCK_GR8; break;
6147 case X86::R9B: OpKind = MCK_GR8; break;
6148 case X86::R10B: OpKind = MCK_GR8; break;
6149 case X86::R11B: OpKind = MCK_GR8; break;
6150 case X86::R12B: OpKind = MCK_GR8; break;
6151 case X86::R13B: OpKind = MCK_GR8; break;
6152 case X86::R14B: OpKind = MCK_GR8; break;
6153 case X86::R15B: OpKind = MCK_GR8; break;
6154 case X86::AX: OpKind = MCK_AX; break;
6155 case X86::DX: OpKind = MCK_DX; break;
6156 case X86::CX: OpKind = MCK_GR16_ABCD; break;
6157 case X86::BX: OpKind = MCK_GR16_ABCD; break;
6158 case X86::SI: OpKind = MCK_GR16_NOREX; break;
6159 case X86::DI: OpKind = MCK_GR16_NOREX; break;
6160 case X86::BP: OpKind = MCK_GR16_NOREX; break;
6161 case X86::SP: OpKind = MCK_GR16_NOREX; break;
6162 case X86::R8W: OpKind = MCK_GR16; break;
6163 case X86::R9W: OpKind = MCK_GR16; break;
6164 case X86::R10W: OpKind = MCK_GR16; break;
6165 case X86::R11W: OpKind = MCK_GR16; break;
6166 case X86::R12W: OpKind = MCK_GR16; break;
6167 case X86::R13W: OpKind = MCK_GR16; break;
6168 case X86::R14W: OpKind = MCK_GR16; break;
6169 case X86::R15W: OpKind = MCK_GR16; break;
6170 case X86::EAX: OpKind = MCK_EAX; break;
6171 case X86::EDX: OpKind = MCK_EDX; break;
6172 case X86::ECX: OpKind = MCK_ECX; break;
6173 case X86::EBX: OpKind = MCK_EBX; break;
6174 case X86::ESI: OpKind = MCK_Reg26; break;
6175 case X86::EDI: OpKind = MCK_Reg26; break;
6176 case X86::EBP: OpKind = MCK_Reg26; break;
6177 case X86::ESP: OpKind = MCK_Reg27; break;
6178 case X86::R8D: OpKind = MCK_Reg29; break;
6179 case X86::R9D: OpKind = MCK_Reg29; break;
6180 case X86::R10D: OpKind = MCK_Reg29; break;
6181 case X86::R11D: OpKind = MCK_Reg29; break;
6182 case X86::R12D: OpKind = MCK_Reg29; break;
6183 case X86::R13D: OpKind = MCK_Reg29; break;
6184 case X86::R14D: OpKind = MCK_Reg29; break;
6185 case X86::R15D: OpKind = MCK_Reg29; break;
6186 case X86::RAX: OpKind = MCK_RAX; break;
6187 case X86::RDX: OpKind = MCK_RDX; break;
6188 case X86::RCX: OpKind = MCK_RCX; break;
6189 case X86::RBX: OpKind = MCK_RBX; break;
6190 case X86::RSI: OpKind = MCK_Reg58; break;
6191 case X86::RDI: OpKind = MCK_Reg58; break;
6192 case X86::RBP: OpKind = MCK_Reg64; break;
6193 case X86::RSP: OpKind = MCK_Reg55; break;
6194 case X86::R8: OpKind = MCK_Reg61; break;
6195 case X86::R9: OpKind = MCK_Reg61; break;
6196 case X86::R10: OpKind = MCK_Reg60; break;
6197 case X86::R11: OpKind = MCK_Reg61; break;
6198 case X86::R12: OpKind = MCK_Reg57; break;
6199 case X86::R13: OpKind = MCK_Reg57; break;
6200 case X86::R14: OpKind = MCK_Reg57; break;
6201 case X86::R15: OpKind = MCK_Reg57; break;
6202 case X86::RIP: OpKind = MCK_Reg66; break;
6203 case X86::MM0: OpKind = MCK_VR64; break;
6204 case X86::MM1: OpKind = MCK_VR64; break;
6205 case X86::MM2: OpKind = MCK_VR64; break;
6206 case X86::MM3: OpKind = MCK_VR64; break;
6207 case X86::MM4: OpKind = MCK_VR64; break;
6208 case X86::MM5: OpKind = MCK_VR64; break;
6209 case X86::MM6: OpKind = MCK_VR64; break;
6210 case X86::MM7: OpKind = MCK_VR64; break;
6211 case X86::FP0: OpKind = MCK_RFP32; break;
6212 case X86::FP1: OpKind = MCK_RFP32; break;
6213 case X86::FP2: OpKind = MCK_RFP32; break;
6214 case X86::FP3: OpKind = MCK_RFP32; break;
6215 case X86::FP4: OpKind = MCK_RFP32; break;
6216 case X86::FP5: OpKind = MCK_RFP32; break;
6217 case X86::FP6: OpKind = MCK_RFP32; break;
6218 case X86::XMM0: OpKind = MCK_XMM0; break;
6219 case X86::XMM1: OpKind = MCK_VR128L; break;
6220 case X86::XMM2: OpKind = MCK_VR128L; break;
6221 case X86::XMM3: OpKind = MCK_VR128L; break;
6222 case X86::XMM4: OpKind = MCK_VR128L; break;
6223 case X86::XMM5: OpKind = MCK_VR128L; break;
6224 case X86::XMM6: OpKind = MCK_VR128L; break;
6225 case X86::XMM7: OpKind = MCK_VR128L; break;
6226 case X86::XMM8: OpKind = MCK_VR128H; break;
6227 case X86::XMM9: OpKind = MCK_VR128H; break;
6228 case X86::XMM10: OpKind = MCK_VR128H; break;
6229 case X86::XMM11: OpKind = MCK_VR128H; break;
6230 case X86::XMM12: OpKind = MCK_VR128H; break;
6231 case X86::XMM13: OpKind = MCK_VR128H; break;
6232 case X86::XMM14: OpKind = MCK_VR128H; break;
6233 case X86::XMM15: OpKind = MCK_VR128H; break;
6234 case X86::XMM16: OpKind = MCK_FR32X; break;
6235 case X86::XMM17: OpKind = MCK_FR32X; break;
6236 case X86::XMM18: OpKind = MCK_FR32X; break;
6237 case X86::XMM19: OpKind = MCK_FR32X; break;
6238 case X86::XMM20: OpKind = MCK_FR32X; break;
6239 case X86::XMM21: OpKind = MCK_FR32X; break;
6240 case X86::XMM22: OpKind = MCK_FR32X; break;
6241 case X86::XMM23: OpKind = MCK_FR32X; break;
6242 case X86::XMM24: OpKind = MCK_FR32X; break;
6243 case X86::XMM25: OpKind = MCK_FR32X; break;
6244 case X86::XMM26: OpKind = MCK_FR32X; break;
6245 case X86::XMM27: OpKind = MCK_FR32X; break;
6246 case X86::XMM28: OpKind = MCK_FR32X; break;
6247 case X86::XMM29: OpKind = MCK_FR32X; break;
6248 case X86::XMM30: OpKind = MCK_FR32X; break;
6249 case X86::XMM31: OpKind = MCK_FR32X; break;
6250 case X86::YMM0: OpKind = MCK_VR256L; break;
6251 case X86::YMM1: OpKind = MCK_VR256L; break;
6252 case X86::YMM2: OpKind = MCK_VR256L; break;
6253 case X86::YMM3: OpKind = MCK_VR256L; break;
6254 case X86::YMM4: OpKind = MCK_VR256L; break;
6255 case X86::YMM5: OpKind = MCK_VR256L; break;
6256 case X86::YMM6: OpKind = MCK_VR256L; break;
6257 case X86::YMM7: OpKind = MCK_VR256L; break;
6258 case X86::YMM8: OpKind = MCK_VR256H; break;
6259 case X86::YMM9: OpKind = MCK_VR256H; break;
6260 case X86::YMM10: OpKind = MCK_VR256H; break;
6261 case X86::YMM11: OpKind = MCK_VR256H; break;
6262 case X86::YMM12: OpKind = MCK_VR256H; break;
6263 case X86::YMM13: OpKind = MCK_VR256H; break;
6264 case X86::YMM14: OpKind = MCK_VR256H; break;
6265 case X86::YMM15: OpKind = MCK_VR256H; break;
6266 case X86::YMM16: OpKind = MCK_VR256X; break;
6267 case X86::YMM17: OpKind = MCK_VR256X; break;
6268 case X86::YMM18: OpKind = MCK_VR256X; break;
6269 case X86::YMM19: OpKind = MCK_VR256X; break;
6270 case X86::YMM20: OpKind = MCK_VR256X; break;
6271 case X86::YMM21: OpKind = MCK_VR256X; break;
6272 case X86::YMM22: OpKind = MCK_VR256X; break;
6273 case X86::YMM23: OpKind = MCK_VR256X; break;
6274 case X86::YMM24: OpKind = MCK_VR256X; break;
6275 case X86::YMM25: OpKind = MCK_VR256X; break;
6276 case X86::YMM26: OpKind = MCK_VR256X; break;
6277 case X86::YMM27: OpKind = MCK_VR256X; break;
6278 case X86::YMM28: OpKind = MCK_VR256X; break;
6279 case X86::YMM29: OpKind = MCK_VR256X; break;
6280 case X86::YMM30: OpKind = MCK_VR256X; break;
6281 case X86::YMM31: OpKind = MCK_VR256X; break;
6282 case X86::ZMM0: OpKind = MCK_Reg78; break;
6283 case X86::ZMM1: OpKind = MCK_Reg78; break;
6284 case X86::ZMM2: OpKind = MCK_Reg78; break;
6285 case X86::ZMM3: OpKind = MCK_Reg78; break;
6286 case X86::ZMM4: OpKind = MCK_Reg78; break;
6287 case X86::ZMM5: OpKind = MCK_Reg78; break;
6288 case X86::ZMM6: OpKind = MCK_Reg78; break;
6289 case X86::ZMM7: OpKind = MCK_Reg78; break;
6290 case X86::ZMM8: OpKind = MCK_Reg81; break;
6291 case X86::ZMM9: OpKind = MCK_Reg81; break;
6292 case X86::ZMM10: OpKind = MCK_Reg81; break;
6293 case X86::ZMM11: OpKind = MCK_Reg81; break;
6294 case X86::ZMM12: OpKind = MCK_Reg81; break;
6295 case X86::ZMM13: OpKind = MCK_Reg81; break;
6296 case X86::ZMM14: OpKind = MCK_Reg81; break;
6297 case X86::ZMM15: OpKind = MCK_Reg81; break;
6298 case X86::ZMM16: OpKind = MCK_VR512; break;
6299 case X86::ZMM17: OpKind = MCK_VR512; break;
6300 case X86::ZMM18: OpKind = MCK_VR512; break;
6301 case X86::ZMM19: OpKind = MCK_VR512; break;
6302 case X86::ZMM20: OpKind = MCK_VR512; break;
6303 case X86::ZMM21: OpKind = MCK_VR512; break;
6304 case X86::ZMM22: OpKind = MCK_VR512; break;
6305 case X86::ZMM23: OpKind = MCK_VR512; break;
6306 case X86::ZMM24: OpKind = MCK_VR512; break;
6307 case X86::ZMM25: OpKind = MCK_VR512; break;
6308 case X86::ZMM26: OpKind = MCK_VR512; break;
6309 case X86::ZMM27: OpKind = MCK_VR512; break;
6310 case X86::ZMM28: OpKind = MCK_VR512; break;
6311 case X86::ZMM29: OpKind = MCK_VR512; break;
6312 case X86::ZMM30: OpKind = MCK_VR512; break;
6313 case X86::ZMM31: OpKind = MCK_VR512; break;
6314 case X86::K0: OpKind = MCK_VK1; break;
6315 case X86::K1: OpKind = MCK_VK16WM; break;
6316 case X86::K2: OpKind = MCK_VK16WM; break;
6317 case X86::K3: OpKind = MCK_VK16WM; break;
6318 case X86::K4: OpKind = MCK_VK16WM; break;
6319 case X86::K5: OpKind = MCK_VK16WM; break;
6320 case X86::K6: OpKind = MCK_VK16WM; break;
6321 case X86::K7: OpKind = MCK_VK16WM; break;
6322 case X86::ST0: OpKind = MCK_ST0; break;
6323 case X86::ST1: OpKind = MCK_RST; break;
6324 case X86::ST2: OpKind = MCK_RST; break;
6325 case X86::ST3: OpKind = MCK_RST; break;
6326 case X86::ST4: OpKind = MCK_RST; break;
6327 case X86::ST5: OpKind = MCK_RST; break;
6328 case X86::ST6: OpKind = MCK_RST; break;
6329 case X86::ST7: OpKind = MCK_RST; break;
6330 case X86::FPSW: OpKind = MCK_FPCCR; break;
6331 case X86::EFLAGS: OpKind = MCK_CCR; break;
6332 case X86::CS: OpKind = MCK_CS; break;
6333 case X86::DS: OpKind = MCK_DS; break;
6334 case X86::SS: OpKind = MCK_SS; break;
6335 case X86::ES: OpKind = MCK_ES; break;
6336 case X86::FS: OpKind = MCK_FS; break;
6337 case X86::GS: OpKind = MCK_GS; break;
6338 case X86::DR0: OpKind = MCK_DEBUG_REG; break;
6339 case X86::DR1: OpKind = MCK_DEBUG_REG; break;
6340 case X86::DR2: OpKind = MCK_DEBUG_REG; break;
6341 case X86::DR3: OpKind = MCK_DEBUG_REG; break;
6342 case X86::DR4: OpKind = MCK_DEBUG_REG; break;
6343 case X86::DR5: OpKind = MCK_DEBUG_REG; break;
6344 case X86::DR6: OpKind = MCK_DEBUG_REG; break;
6345 case X86::DR7: OpKind = MCK_DEBUG_REG; break;
6346 case X86::DR8: OpKind = MCK_DEBUG_REG; break;
6347 case X86::DR9: OpKind = MCK_DEBUG_REG; break;
6348 case X86::DR10: OpKind = MCK_DEBUG_REG; break;
6349 case X86::DR11: OpKind = MCK_DEBUG_REG; break;
6350 case X86::DR12: OpKind = MCK_DEBUG_REG; break;
6351 case X86::DR13: OpKind = MCK_DEBUG_REG; break;
6352 case X86::DR14: OpKind = MCK_DEBUG_REG; break;
6353 case X86::DR15: OpKind = MCK_DEBUG_REG; break;
6354 case X86::CR0: OpKind = MCK_CONTROL_REG; break;
6355 case X86::CR1: OpKind = MCK_CONTROL_REG; break;
6356 case X86::CR2: OpKind = MCK_CONTROL_REG; break;
6357 case X86::CR3: OpKind = MCK_CONTROL_REG; break;
6358 case X86::CR4: OpKind = MCK_CONTROL_REG; break;
6359 case X86::CR5: OpKind = MCK_CONTROL_REG; break;
6360 case X86::CR6: OpKind = MCK_CONTROL_REG; break;
6361 case X86::CR7: OpKind = MCK_CONTROL_REG; break;
6362 case X86::CR8: OpKind = MCK_CONTROL_REG; break;
6363 case X86::CR9: OpKind = MCK_CONTROL_REG; break;
6364 case X86::CR10: OpKind = MCK_CONTROL_REG; break;
6365 case X86::CR11: OpKind = MCK_CONTROL_REG; break;
6366 case X86::CR12: OpKind = MCK_CONTROL_REG; break;
6367 case X86::CR13: OpKind = MCK_CONTROL_REG; break;
6368 case X86::CR14: OpKind = MCK_CONTROL_REG; break;
6369 case X86::CR15: OpKind = MCK_CONTROL_REG; break;
6370 case X86::BND0: OpKind = MCK_BNDR; break;
6371 case X86::BND1: OpKind = MCK_BNDR; break;
6372 case X86::BND2: OpKind = MCK_BNDR; break;
6373 case X86::BND3: OpKind = MCK_BNDR; break;
6374 }
6375 return isSubclass(OpKind, Kind) ? (unsigned)MCTargetAsmParser::Match_Success :
6376 getDiagKindFromRegisterClass(Kind);
6377 }
6378
6379 if (Kind > MCK_LAST_TOKEN && Kind <= MCK_LAST_REGISTER)
6380 return getDiagKindFromRegisterClass(Kind);
6381
6382 return MCTargetAsmParser::Match_InvalidOperand;
6383}
6384
6385#ifndef NDEBUG
6386const char *getMatchClassName(MatchClassKind Kind) {
6387 switch (Kind) {
6388 case InvalidMatchClass: return "InvalidMatchClass";
6389 case OptionalMatchClass: return "OptionalMatchClass";
6390 case MCK__STAR_: return "MCK__STAR_";
6391 case MCK_b: return "MCK_b";
6392 case MCK_d: return "MCK_d";
6393 case MCK_pd: return "MCK_pd";
6394 case MCK_ps: return "MCK_ps";
6395 case MCK_q: return "MCK_q";
6396 case MCK_sae: return "MCK_sae";
6397 case MCK_sd: return "MCK_sd";
6398 case MCK_ss: return "MCK_ss";
6399 case MCK_ub: return "MCK_ub";
6400 case MCK_ud: return "MCK_ud";
6401 case MCK_uq: return "MCK_uq";
6402 case MCK_uw: return "MCK_uw";
6403 case MCK_w: return "MCK_w";
6404 case MCK__123_: return "MCK__123_";
6405 case MCK__123_1to16_125_: return "MCK__123_1to16_125_";
6406 case MCK__123_1to2_125_: return "MCK__123_1to2_125_";
6407 case MCK__123_1to4_125_: return "MCK__123_1to4_125_";
6408 case MCK__123_1to8_125_: return "MCK__123_1to8_125_";
6409 case MCK__123_sae_125_: return "MCK__123_sae_125_";
6410 case MCK__123_z_125_: return "MCK__123_z_125_";
6411 case MCK__125_: return "MCK__125_";
6412 case MCK_Reg64: return "MCK_Reg64";
6413 case MCK_Reg66: return "MCK_Reg66";
6414 case MCK_AL: return "MCK_AL";
6415 case MCK_AX: return "MCK_AX";
6416 case MCK_CCR: return "MCK_CCR";
6417 case MCK_CL: return "MCK_CL";
6418 case MCK_CS: return "MCK_CS";
6419 case MCK_DS: return "MCK_DS";
6420 case MCK_DX: return "MCK_DX";
6421 case MCK_EAX: return "MCK_EAX";
6422 case MCK_EBX: return "MCK_EBX";
6423 case MCK_ECX: return "MCK_ECX";
6424 case MCK_EDX: return "MCK_EDX";
6425 case MCK_ES: return "MCK_ES";
6426 case MCK_FPCCR: return "MCK_FPCCR";
6427 case MCK_FS: return "MCK_FS";
6428 case MCK_GS: return "MCK_GS";
6429 case MCK_RAX: return "MCK_RAX";
6430 case MCK_RBX: return "MCK_RBX";
6431 case MCK_RCX: return "MCK_RCX";
6432 case MCK_RDX: return "MCK_RDX";
6433 case MCK_SS: return "MCK_SS";
6434 case MCK_ST0: return "MCK_ST0";
6435 case MCK_XMM0: return "MCK_XMM0";
6436 case MCK_Reg24: return "MCK_Reg24";
6437 case MCK_Reg52: return "MCK_Reg52";
6438 case MCK_Reg65: return "MCK_Reg65";
6439 case MCK_GR32_AD: return "MCK_GR32_AD";
6440 case MCK_GR64_AD: return "MCK_GR64_AD";
6441 case MCK_Reg25: return "MCK_Reg25";
6442 case MCK_Reg34: return "MCK_Reg34";
6443 case MCK_Reg53: return "MCK_Reg53";
6444 case MCK_GR32_TC: return "MCK_GR32_TC";
6445 case MCK_Reg50: return "MCK_Reg50";
6446 case MCK_Reg58: return "MCK_Reg58";
6447 case MCK_BNDR: return "MCK_BNDR";
6448 case MCK_GR16_ABCD: return "MCK_GR16_ABCD";
6449 case MCK_GR32_ABCD: return "MCK_GR32_ABCD";
6450 case MCK_GR64_ABCD: return "MCK_GR64_ABCD";
6451 case MCK_GR8_ABCD_H: return "MCK_GR8_ABCD_H";
6452 case MCK_GR8_ABCD_L: return "MCK_GR8_ABCD_L";
6453 case MCK_Reg42: return "MCK_Reg42";
6454 case MCK_Reg61: return "MCK_Reg61";
6455 case MCK_Reg26: return "MCK_Reg26";
6456 case MCK_Reg45: return "MCK_Reg45";
6457 case MCK_Reg48: return "MCK_Reg48";
6458 case MCK_Reg54: return "MCK_Reg54";
6459 case MCK_Reg60: return "MCK_Reg60";
6460 case MCK_SEGMENT_REG: return "MCK_SEGMENT_REG";
6461 case MCK_Reg27: return "MCK_Reg27";
6462 case MCK_Reg46: return "MCK_Reg46";
6463 case MCK_Reg49: return "MCK_Reg49";
6464 case MCK_Reg55: return "MCK_Reg55";
6465 case MCK_Reg59: return "MCK_Reg59";
6466 case MCK_GR32_NOREX_NOSP: return "MCK_GR32_NOREX_NOSP";
6467 case MCK_GR64_NOREX_NOSP: return "MCK_GR64_NOREX_NOSP";
6468 case MCK_RFP32: return "MCK_RFP32";
6469 case MCK_VK16WM: return "MCK_VK16WM";
6470 case MCK_Reg37: return "MCK_Reg37";
6471 case MCK_Reg43: return "MCK_Reg43";
6472 case MCK_Reg78: return "MCK_Reg78";
6473 case MCK_Reg81: return "MCK_Reg81";
6474 case MCK_GR16_NOREX: return "MCK_GR16_NOREX";
6475 case MCK_GR32_NOREX: return "MCK_GR32_NOREX";
6476 case MCK_GR64_TCW64: return "MCK_GR64_TCW64";
6477 case MCK_GR8_NOREX: return "MCK_GR8_NOREX";
6478 case MCK_RST: return "MCK_RST";
6479 case MCK_VK1: return "MCK_VK1";
6480 case MCK_VR128H: return "MCK_VR128H";
6481 case MCK_VR128L: return "MCK_VR128L";
6482 case MCK_VR256H: return "MCK_VR256H";
6483 case MCK_VR256L: return "MCK_VR256L";
6484 case MCK_VR64: return "MCK_VR64";
6485 case MCK_Reg21: return "MCK_Reg21";
6486 case MCK_GR64_NOREX: return "MCK_GR64_NOREX";
6487 case MCK_GR64_TC: return "MCK_GR64_TC";
6488 case MCK_Reg29: return "MCK_Reg29";
6489 case MCK_Reg57: return "MCK_Reg57";
6490 case MCK_Reg56: return "MCK_Reg56";
6491 case MCK_GR32_NOAX: return "MCK_GR32_NOAX";
6492 case MCK_GR32_NOSP: return "MCK_GR32_NOSP";
6493 case MCK_GR64_NOSP: return "MCK_GR64_NOSP";
6494 case MCK_Reg38: return "MCK_Reg38";
6495 case MCK_Reg79: return "MCK_Reg79";
6496 case MCK_CONTROL_REG: return "MCK_CONTROL_REG";
6497 case MCK_DEBUG_REG: return "MCK_DEBUG_REG";
6498 case MCK_FR32: return "MCK_FR32";
6499 case MCK_GR16: return "MCK_GR16";
6500 case MCK_GR32: return "MCK_GR32";
6501 case MCK_VR256: return "MCK_VR256";
6502 case MCK_Reg18: return "MCK_Reg18";
6503 case MCK_GR64: return "MCK_GR64";
6504 case MCK_LOW32_ADDR_ACCESS: return "MCK_LOW32_ADDR_ACCESS";
6505 case MCK_LOW32_ADDR_ACCESS_RBP: return "MCK_LOW32_ADDR_ACCESS_RBP";
6506 case MCK_GR8: return "MCK_GR8";
6507 case MCK_FR32X: return "MCK_FR32X";
6508 case MCK_VR256X: return "MCK_VR256X";
6509 case MCK_VR512: return "MCK_VR512";
6510 case MCK_AVX512RC: return "MCK_AVX512RC";
6511 case MCK_ImmSExti64i8: return "MCK_ImmSExti64i8";
6512 case MCK_ImmSExti16i8: return "MCK_ImmSExti16i8";
6513 case MCK_ImmSExti32i8: return "MCK_ImmSExti32i8";
6514 case MCK_ImmSExti64i32: return "MCK_ImmSExti64i32";
6515 case MCK_Imm: return "MCK_Imm";
6516 case MCK_ImmUnsignedi8: return "MCK_ImmUnsignedi8";
6517 case MCK_GR32orGR64: return "MCK_GR32orGR64";
6518 case MCK_AbsMem16: return "MCK_AbsMem16";
6519 case MCK_DstIdx16: return "MCK_DstIdx16";
6520 case MCK_DstIdx32: return "MCK_DstIdx32";
6521 case MCK_DstIdx64: return "MCK_DstIdx64";
6522 case MCK_DstIdx8: return "MCK_DstIdx8";
6523 case MCK_MemOffs16_16: return "MCK_MemOffs16_16";
6524 case MCK_MemOffs16_32: return "MCK_MemOffs16_32";
6525 case MCK_MemOffs16_8: return "MCK_MemOffs16_8";
6526 case MCK_MemOffs32_16: return "MCK_MemOffs32_16";
6527 case MCK_MemOffs32_32: return "MCK_MemOffs32_32";
6528 case MCK_MemOffs32_64: return "MCK_MemOffs32_64";
6529 case MCK_MemOffs32_8: return "MCK_MemOffs32_8";
6530 case MCK_MemOffs64_16: return "MCK_MemOffs64_16";
6531 case MCK_MemOffs64_32: return "MCK_MemOffs64_32";
6532 case MCK_MemOffs64_64: return "MCK_MemOffs64_64";
6533 case MCK_MemOffs64_8: return "MCK_MemOffs64_8";
6534 case MCK_SrcIdx16: return "MCK_SrcIdx16";
6535 case MCK_SrcIdx32: return "MCK_SrcIdx32";
6536 case MCK_SrcIdx64: return "MCK_SrcIdx64";
6537 case MCK_SrcIdx8: return "MCK_SrcIdx8";
6538 case MCK_AbsMem: return "MCK_AbsMem";
6539 case MCK_Mem128: return "MCK_Mem128";
6540 case MCK_Mem128_RC128: return "MCK_Mem128_RC128";
6541 case MCK_Mem128_RC128X: return "MCK_Mem128_RC128X";
6542 case MCK_Mem128_RC256: return "MCK_Mem128_RC256";
6543 case MCK_Mem128_RC256X: return "MCK_Mem128_RC256X";
6544 case MCK_Mem16: return "MCK_Mem16";
6545 case MCK_Mem256: return "MCK_Mem256";
6546 case MCK_Mem256_RC128: return "MCK_Mem256_RC128";
6547 case MCK_Mem256_RC128X: return "MCK_Mem256_RC128X";
6548 case MCK_Mem256_RC256: return "MCK_Mem256_RC256";
6549 case MCK_Mem256_RC256X: return "MCK_Mem256_RC256X";
6550 case MCK_Mem256_RC512: return "MCK_Mem256_RC512";
6551 case MCK_Mem32: return "MCK_Mem32";
6552 case MCK_Mem512: return "MCK_Mem512";
6553 case MCK_Mem512_RC256X: return "MCK_Mem512_RC256X";
6554 case MCK_Mem512_RC512: return "MCK_Mem512_RC512";
6555 case MCK_Mem64: return "MCK_Mem64";
6556 case MCK_Mem64_RC128: return "MCK_Mem64_RC128";
6557 case MCK_Mem64_RC128X: return "MCK_Mem64_RC128X";
6558 case MCK_Mem80: return "MCK_Mem80";
6559 case MCK_Mem8: return "MCK_Mem8";
6560 case MCK_Mem: return "MCK_Mem";
6561 case NumMatchClassKinds: return "NumMatchClassKinds";
6562 }
6563 llvm_unreachable("unhandled MatchClassKind!")::llvm::llvm_unreachable_internal("unhandled MatchClassKind!"
, "/build/llvm-toolchain-snapshot-6.0~svn321639/build-llvm/lib/Target/X86/X86GenAsmMatcher.inc"
, 6563)
;
6564}
6565
6566#endif // NDEBUG
6567uint64_t X86AsmParser::
6568ComputeAvailableFeatures(const FeatureBitset& FB) const {
6569 uint64_t Features = 0;
6570 if ((FB[X86::FeatureAVX512]))
6571 Features |= Feature_HasAVX512;
6572 if ((FB[X86::FeatureCDI]))
6573 Features |= Feature_HasCDI;
6574 if ((FB[X86::FeatureVPOPCNTDQ]))
6575 Features |= Feature_HasVPOPCNTDQ;
6576 if ((FB[X86::FeaturePFI]))
6577 Features |= Feature_HasPFI;
6578 if ((FB[X86::FeatureERI]))
6579 Features |= Feature_HasERI;
6580 if ((FB[X86::FeatureDQI]))
6581 Features |= Feature_HasDQI;
6582 if ((FB[X86::FeatureBWI]))
6583 Features |= Feature_HasBWI;
6584 if ((FB[X86::FeatureVLX]))
6585 Features |= Feature_HasVLX;
6586 if ((FB[X86::FeatureVNNI]))
6587 Features |= Feature_HasVNNI;
6588 if ((FB[X86::FeatureBITALG]))
6589 Features |= Feature_HasBITALG;
6590 if ((FB[X86::FeatureVBMI]))
6591 Features |= Feature_HasVBMI;
6592 if ((FB[X86::FeatureVBMI2]))
6593 Features |= Feature_HasVBMI2;
6594 if ((FB[X86::FeatureIFMA]))
6595 Features |= Feature_HasIFMA;
6596 if ((!FB[X86::Mode64Bit]))
6597 Features |= Feature_Not64BitMode;
6598 if ((FB[X86::Mode64Bit]))
6599 Features |= Feature_In64BitMode;
6600 if ((FB[X86::Mode16Bit]))
6601 Features |= Feature_In16BitMode;
6602 if ((!FB[X86::Mode16Bit]))
6603 Features |= Feature_Not16BitMode;
6604 if ((FB[X86::Mode32Bit]))
6605 Features |= Feature_In32BitMode;
6606 return Features;
6607}
6608
6609static const char *const MnemonicTable =
6610 "\003aaa\003aad\003aam\003aas\003adc\004adcb\004adcl\004adcq\004adcw\004"
6611 "adcx\005adcxl\005adcxq\003add\004addb\004addl\005addpd\005addps\004addq"
6612 "\005addsd\005addss\010addsubpd\010addsubps\004addw\004adox\005adoxl\005"
6613 "adoxq\006aesdec\naesdeclast\006aesenc\naesenclast\006aesimc\017aeskeyge"
6614 "nassist\003and\004andb\004andl\004andn\005andnl\006andnpd\006andnps\005"
6615 "andnq\005andpd\005andps\004andq\004andw\004arpl\005bextr\006bextrl\006b"
6616 "extrq\007blcfill\004blci\005blcic\006blcmsk\004blcs\007blendpd\007blend"
6617 "ps\010blendvpd\010blendvps\007blsfill\004blsi\005blsic\005blsil\005blsi"
6618 "q\006blsmsk\007blsmskl\007blsmskq\004blsr\005blsrl\005blsrq\005bndcl\005"
6619 "bndcn\005bndcu\006bndldx\005bndmk\006bndmov\006bndstx\005bound\003bsf\004"
6620 "bsfl\004bsfq\004bsfw\003bsr\004bsrl\004bsrq\004bsrw\005bswap\006bswapl\006"
6621 "bswapq\002bt\003btc\004btcl\004btcq\004btcw\003btl\003btq\003btr\004btr"
6622 "l\004btrq\004btrw\003bts\004btsl\004btsq\004btsw\003btw\004bzhi\005bzhi"
6623 "l\005bzhiq\004call\005calll\005callq\005callw\004cbtw\003cbw\003cdq\004"
6624 "cdqe\004clac\003clc\003cld\007clflush\nclflushopt\004clgi\003cli\004clr"
6625 "b\004clrl\004clrq\010clrssbsy\004clrw\004cltd\004cltq\004clts\004clwb\006"
6626 "clzero\003cmc\005cmova\006cmovae\007cmovael\007cmovaeq\007cmovaew\006cm"
6627 "oval\006cmovaq\006cmovaw\005cmovb\006cmovbe\007cmovbel\007cmovbeq\007cm"
6628 "ovbew\006cmovbl\006cmovbq\006cmovbw\005cmove\006cmovel\006cmoveq\006cmo"
6629 "vew\005cmovg\006cmovge\007cmovgel\007cmovgeq\007cmovgew\006cmovgl\006cm"
6630 "ovgq\006cmovgw\005cmovl\006cmovle\007cmovlel\007cmovleq\007cmovlew\006c"
6631 "movll\006cmovlq\006cmovlw\006cmovne\007cmovnel\007cmovneq\007cmovnew\006"
6632 "cmovno\007cmovnol\007cmovnoq\007cmovnow\006cmovnp\007cmovnpl\007cmovnpq"
6633 "\007cmovnpw\006cmovns\007cmovnsl\007cmovnsq\007cmovnsw\005cmovo\006cmov"
6634 "ol\006cmovoq\006cmovow\005cmovp\006cmovpl\006cmovpq\006cmovpw\005cmovs\006"
6635 "cmovsl\006cmovsq\006cmovsw\003cmp\004cmpb\004cmpl\005cmppd\005cmpps\004"
6636 "cmpq\004cmps\005cmpsb\005cmpsd\005cmpsl\005cmpsq\005cmpss\005cmpsw\004c"
6637 "mpw\007cmpxchg\ncmpxchg16b\tcmpxchg8b\010cmpxchgb\010cmpxchgl\010cmpxch"
6638 "gq\010cmpxchgw\006comisd\006comiss\005cpuid\003cqo\004cqto\005crc32\006"
6639 "crc32b\006crc32l\006crc32q\006crc32w\002cs\010cvtdq2pd\010cvtdq2ps\010c"
6640 "vtpd2dq\010cvtpd2pi\010cvtpd2ps\010cvtpi2pd\010cvtpi2ps\010cvtps2dq\010"
6641 "cvtps2pd\010cvtps2pi\010cvtsd2si\tcvtsd2sil\tcvtsd2siq\010cvtsd2ss\010c"
6642 "vtsi2sd\tcvtsi2sdl\tcvtsi2sdq\010cvtsi2ss\tcvtsi2ssl\tcvtsi2ssq\010cvts"
6643 "s2sd\010cvtss2si\tcvtss2sil\tcvtss2siq\tcvttpd2dq\tcvttpd2pi\tcvttps2dq"
6644 "\tcvttps2pi\tcvttsd2si\ncvttsd2sil\ncvttsd2siq\tcvttss2si\ncvttss2sil\n"
6645 "cvttss2siq\003cwd\004cwde\004cwtd\004cwtl\003daa\003das\006data16\006da"
6646 "ta32\003dec\004decb\004decl\004decq\004decw\003div\004divb\004divl\005d"
6647 "ivpd\005divps\004divq\005divsd\005divss\004divw\004dppd\004dpps\002ds\004"
6648 "emms\005encls\005enclu\005enter\002es\textractps\005extrq\005f2xm1\004f"
6649 "abs\004fadd\005faddl\005faddp\005fadds\004fbld\005fbstp\004fchs\006fcmo"
6650 "vb\007fcmovbe\006fcmove\007fcmovnb\010fcmovnbe\007fcmovne\007fcmovnu\006"
6651 "fcmovu\004fcom\005fcomi\005fcoml\005fcomp\006fcompi\006fcompl\006fcompp"
6652 "\006fcomps\005fcoms\004fcos\007fdecstp\004fdiv\005fdivl\005fdivp\005fdi"
6653 "vr\006fdivrl\006fdivrp\006fdivrs\005fdivs\005femms\005ffree\006ffreep\005"
6654 "fiadd\006fiaddl\006fiadds\005ficom\006ficoml\006ficomp\007ficompl\007fi"
6655 "comps\006ficoms\005fidiv\006fidivl\006fidivr\007fidivrl\007fidivrs\006f"
6656 "idivs\004fild\005fildl\006fildll\005filds\005fimul\006fimull\006fimuls\007"
6657 "fincstp\004fist\005fistl\005fistp\006fistpl\007fistpll\006fistps\005fis"
6658 "ts\006fisttp\007fisttpl\010fisttpll\007fisttps\005fisub\006fisubl\006fi"
6659 "subr\007fisubrl\007fisubrs\006fisubs\003fld\004fld1\005fldcw\006fldenv\004"
6660 "fldl\006fldl2e\006fldl2t\006fldlg2\006fldln2\005fldpi\004flds\004fldt\004"
6661 "fldz\004fmul\005fmull\005fmulp\005fmuls\006fnclex\006fninit\004fnop\006"
6662 "fnsave\006fnstcw\007fnstenv\006fnstsw\006fpatan\005fprem\006fprem1\005f"
6663 "ptan\007frndint\006frstor\002fs\006fscale\004fsin\007fsincos\005fsqrt\003"
6664 "fst\004fstl\004fstp\005fstpl\005fstps\005fstpt\004fsts\004fsub\005fsubl"
6665 "\005fsubp\005fsubr\006fsubrl\006fsubrp\006fsubrs\005fsubs\004ftst\005fu"
6666 "com\006fucomi\006fucomp\007fucompi\007fucompp\004fxam\004fxch\007fxrsto"
6667 "r\tfxrstor64\006fxsave\010fxsave64\007fxtract\005fyl2x\007fyl2xp1\006ge"
6668 "tsec\020gf2p8affineinvqb\015gf2p8affineqb\tgf2p8mulb\002gs\006haddpd\006"
6669 "haddps\003hlt\006hsubpd\006hsubps\004idiv\005idivb\005idivl\005idivq\005"
6670 "idivw\004imul\005imulb\005imull\005imulq\005imulw\002in\003inb\003inc\004"
6671 "incb\004incl\004incq\007incsspd\007incsspq\004incw\003inl\003ins\004ins"
6672 "b\004insd\010insertps\007insertq\004insl\004insw\003int\004int3\004into"
6673 "\004invd\006invept\006invlpg\007invlpga\007invpcid\007invvpid\003inw\004"
6674 "iret\005iretd\005iretl\005iretq\005iretw\002ja\003jae\002jb\003jbe\004j"
6675 "cxz\002je\005jecxz\002jg\003jge\002jl\003jle\003jmp\004jmpl\004jmpq\004"
6676 "jmpw\003jne\003jno\003jnp\003jns\002jo\002jp\005jrcxz\002js\005kaddb\005"
6677 "kaddd\005kaddq\005kaddw\005kandb\005kandd\006kandnb\006kandnd\006kandnq"
6678 "\006kandnw\005kandq\005kandw\005kmovb\005kmovd\005kmovq\005kmovw\005kno"
6679 "tb\005knotd\005knotq\005knotw\004korb\004kord\004korq\010kortestb\010ko"
6680 "rtestd\010kortestq\010kortestw\004korw\010kshiftlb\010kshiftld\010kshif"
6681 "tlq\010kshiftlw\010kshiftrb\010kshiftrd\010kshiftrq\010kshiftrw\006ktes"
6682 "tb\006ktestd\006ktestq\006ktestw\010kunpckbw\010kunpckdq\010kunpckwd\006"
6683 "kxnorb\006kxnord\006kxnorq\006kxnorw\005kxorb\005kxord\005kxorq\005kxor"
6684 "w\004lahf\003lar\004larl\004larq\004larw\005lcall\006lcalll\006lcallq\006"
6685 "lcallw\005lddqu\007ldmxcsr\003lds\004ldsl\004ldsw\003lea\004leal\004lea"
6686 "q\005leave\004leaw\003les\004lesl\004lesw\006lfence\003lfs\004lfsl\004l"
6687 "fsq\004lfsw\004lgdt\005lgdtl\005lgdtq\005lgdtw\003lgs\004lgsl\004lgsq\004"
6688 "lgsw\004lidt\005lidtl\005lidtq\005lidtw\004ljmp\005ljmpl\005ljmpq\005lj"
6689 "mpw\004lldt\005lldtw\006llwpcb\004lmsw\005lmsww\004lock\004lods\005lods"
6690 "b\005lodsd\005lodsl\005lodsq\005lodsw\004loop\005loope\006loopne\005lre"
6691 "tl\005lretq\005lretw\003lsl\004lsll\004lslq\004lslw\003lss\004lssl\004l"
6692 "ssq\004lssw\003ltr\004ltrw\006lwpins\006lwpval\005lzcnt\006lzcntl\006lz"
6693 "cntq\006lzcntw\nmaskmovdqu\010maskmovq\005maxpd\005maxps\005maxsd\005ma"
6694 "xss\006mfence\005minpd\005minps\005minsd\005minss\007monitor\010monitor"
6695 "x\007montmul\003mov\006movabs\007movabsb\007movabsl\007movabsq\007movab"
6696 "sw\006movapd\006movaps\004movb\005movbe\006movbel\006movbeq\006movbew\004"
6697 "movd\007movddup\007movdq2q\006movdqa\006movdqu\007movhlps\006movhpd\006"
6698 "movhps\004movl\007movlhps\006movlpd\006movlps\010movmskpd\010movmskps\007"
6699 "movntdq\010movntdqa\006movnti\007movntil\007movntiq\007movntpd\007movnt"
6700 "ps\006movntq\007movntsd\007movntss\004movq\007movq2dq\004movs\005movsb\006"
6701 "movsbl\006movsbq\006movsbw\005movsd\010movshdup\005movsl\010movsldup\006"
6702 "movslq\005movsq\005movss\005movsw\006movswl\006movswq\005movsx\006movsx"
6703 "d\006movupd\006movups\004movw\006movzbl\006movzbq\006movzbw\006movzwl\006"
6704 "movzwq\005movzx\007mpsadbw\003mul\004mulb\004mull\005mulpd\005mulps\004"
6705 "mulq\005mulsd\005mulss\004mulw\004mulx\005mulxl\005mulxq\005mwait\006mw"
6706 "aitx\003neg\004negb\004negl\004negq\004negw\003nop\004nopl\004nopq\004n"
6707 "opw\003not\004notb\004notl\004notq\004notw\002or\003orb\003orl\004orpd\004"
6708 "orps\003orq\003orw\003out\004outb\004outl\004outs\005outsb\005outsd\005"
6709 "outsl\005outsw\004outw\005pabsb\005pabsd\005pabsw\010packssdw\010packss"
6710 "wb\010packusdw\010packuswb\005paddb\005paddd\005paddq\006paddsb\006padd"
6711 "sw\007paddusb\007paddusw\005paddw\007palignr\004pand\005pandn\005pause\005"
6712 "pavgb\007pavgusb\005pavgw\010pblendvb\007pblendw\014pclmulhqhqdq\014pcl"
6713 "mulhqlqdq\014pclmullqhqdq\014pclmullqlqdq\tpclmulqdq\007pcmpeqb\007pcmp"
6714 "eqd\007pcmpeqq\007pcmpeqw\tpcmpestri\tpcmpestrm\007pcmpgtb\007pcmpgtd\007"
6715 "pcmpgtq\007pcmpgtw\tpcmpistri\tpcmpistrm\004pdep\005pdepl\005pdepq\004p"
6716 "ext\005pextl\005pextq\006pextrb\006pextrd\006pextrq\006pextrw\005pf2id\005"
6717 "pf2iw\005pfacc\005pfadd\007pfcmpeq\007pfcmpge\007pfcmpgt\005pfmax\005pf"
6718 "min\005pfmul\006pfnacc\007pfpnacc\005pfrcp\010pfrcpit1\010pfrcpit2\010p"
6719 "frsqit1\007pfrsqrt\005pfsub\006pfsubr\006phaddd\007phaddsw\006phaddw\np"
6720 "hminposuw\006phsubd\007phsubsw\006phsubw\005pi2fd\005pi2fw\006pinsrb\006"
6721 "pinsrd\006pinsrq\006pinsrw\tpmaddubsw\007pmaddwd\006pmaxsb\006pmaxsd\006"
6722 "pmaxsw\006pmaxub\006pmaxud\006pmaxuw\006pminsb\006pminsd\006pminsw\006p"
6723 "minub\006pminud\006pminuw\010pmovmskb\010pmovsxbd\010pmovsxbq\010pmovsx"
6724 "bw\010pmovsxdq\010pmovsxwd\010pmovsxwq\010pmovzxbd\010pmovzxbq\010pmovz"
6725 "xbw\010pmovzxdq\010pmovzxwd\010pmovzxwq\006pmuldq\010pmulhrsw\007pmulhr"
6726 "w\007pmulhuw\006pmulhw\006pmulld\006pmullw\007pmuludq\003pop\005popal\005"
6727 "popaw\006popcnt\007popcntl\007popcntq\007popcntw\004popf\005popfd\005po"
6728 "pfl\005popfq\005popfw\004popl\004popq\004popw\003por\010prefetch\013pre"
6729 "fetchnta\nprefetcht0\nprefetcht1\nprefetcht2\tprefetchw\013prefetchwt1\006"
6730 "psadbw\006pshufb\006pshufd\007pshufhw\007pshuflw\006pshufw\006psignb\006"
6731 "psignd\006psignw\005pslld\006pslldq\005psllq\005psllw\005psrad\005psraw"
6732 "\005psrld\006psrldq\005psrlq\005psrlw\005psubb\005psubd\005psubq\006psu"
6733 "bsb\006psubsw\007psubusb\007psubusw\005psubw\006pswapd\005ptest\007ptwr"
6734 "ite\010ptwritel\010ptwriteq\tpunpckhbw\tpunpckhdq\npunpckhqdq\tpunpckhw"
6735 "d\tpunpcklbw\tpunpckldq\npunpcklqdq\tpunpcklwd\004push\006pushal\006pus"
6736 "haw\005pushf\006pushfd\006pushfl\006pushfq\006pushfw\005pushl\005pushq\005"
6737 "pushw\004pxor\003rcl\004rclb\004rcll\004rclq\004rclw\005rcpps\005rcpss\003"
6738 "rcr\004rcrb\004rcrl\004rcrq\004rcrw\010rdfsbase\trdfsbasel\trdfsbaseq\010"
6739 "rdgsbase\trdgsbasel\trdgsbaseq\005rdmsr\005rdpid\006rdpkru\005rdpmc\006"
6740 "rdrand\007rdrandl\007rdrandq\007rdrandw\006rdseed\007rdseedl\007rdseedq"
6741 "\007rdseedw\006rdsspd\006rdsspq\005rdtsc\006rdtscp\003rep\005repne\003r"
6742 "et\004retf\005retfq\004retl\004retq\004retw\005rex64\003rol\004rolb\004"
6743 "roll\004rolq\004rolw\003ror\004rorb\004rorl\004rorq\004rorw\004rorx\005"
6744 "rorxl\005rorxq\007roundpd\007roundps\007roundsd\007roundss\003rsm\007rs"
6745 "qrtps\007rsqrtss\010rstorssp\004sahf\004salc\003sar\004sarb\004sarl\004"
6746 "sarq\004sarw\004sarx\005sarxl\005sarxq\013saveprevssp\003sbb\004sbbb\004"
6747 "sbbl\004sbbq\004sbbw\004scas\005scasb\005scasd\005scasl\005scasq\005sca"
6748 "sw\004seta\005setae\004setb\005setbe\004sete\004setg\005setge\004setl\005"
6749 "setle\005setne\005setno\005setnp\005setns\004seto\004setp\004sets\010se"
6750 "tssbsy\006sfence\004sgdt\005sgdtl\005sgdtq\005sgdtw\010sha1msg1\010sha1"
6751 "msg2\tsha1nexte\tsha1rnds4\nsha256msg1\nsha256msg2\013sha256rnds2\003sh"
6752 "l\004shlb\004shld\005shldl\005shldq\005shldw\004shll\004shlq\004shlw\004"
6753 "shlx\005shlxl\005shlxq\003shr\004shrb\004shrd\005shrdl\005shrdq\005shrd"
6754 "w\004shrl\004shrq\004shrw\004shrx\005shrxl\005shrxq\006shufpd\006shufps"
6755 "\004sidt\005sidtl\005sidtq\005sidtw\006skinit\004sldt\005sldtl\005sldtq"
6756 "\005sldtw\006slwpcb\004smsw\005smswl\005smswq\005smsww\006sqrtpd\006sqr"
6757 "tps\006sqrtsd\006sqrtss\002ss\004stac\003stc\003std\004stgi\003sti\007s"
6758 "tmxcsr\004stos\005stosb\005stosd\005stosl\005stosq\005stosw\003str\004s"
6759 "trl\004strq\004strw\003sub\004subb\004subl\005subpd\005subps\004subq\005"
6760 "subsd\005subss\004subw\006swapgs\007syscall\010sysenter\007sysexit\010s"
6761 "ysexitl\010sysexitq\006sysret\007sysretl\007sysretq\006t1mskc\004test\005"
6762 "testb\005testl\005testq\005testw\005tzcnt\006tzcntl\006tzcntq\006tzcntw"
6763 "\005tzmsk\007ucomisd\007ucomiss\003ud2\004ud2b\010unpckhpd\010unpckhps\010"
6764 "unpcklpd\010unpcklps\006vaddpd\006vaddps\006vaddsd\006vaddss\tvaddsubpd"
6765 "\tvaddsubps\007vaesdec\013vaesdeclast\007vaesenc\013vaesenclast\007vaes"
6766 "imc\020vaeskeygenassist\007valignd\007valignq\007vandnpd\007vandnps\006"
6767 "vandpd\006vandps\tvblendmpd\tvblendmps\010vblendpd\010vblendps\tvblendv"
6768 "pd\tvblendvps\016vbroadcastf128\017vbroadcastf32x2\017vbroadcastf32x4\017"
6769 "vbroadcastf32x8\017vbroadcastf64x2\017vbroadcastf64x4\016vbroadcasti128"
6770 "\017vbroadcasti32x2\017vbroadcasti32x4\017vbroadcasti32x8\017vbroadcast"
6771 "i64x2\017vbroadcasti64x4\014vbroadcastsd\014vbroadcastss\004vcmp\006vcm"
6772 "ppd\006vcmpps\006vcmpsd\006vcmpss\007vcomisd\007vcomiss\013vcompresspd\013"
6773 "vcompressps\tvcvtdq2pd\tvcvtdq2ps\tvcvtpd2dq\nvcvtpd2dqx\nvcvtpd2dqy\tv"
6774 "cvtpd2ps\nvcvtpd2psx\nvcvtpd2psy\tvcvtpd2qq\nvcvtpd2udq\013vcvtpd2udqx\013"
6775 "vcvtpd2udqy\nvcvtpd2uqq\tvcvtph2ps\tvcvtps2dq\tvcvtps2pd\tvcvtps2ph\tvc"
6776 "vtps2qq\nvcvtps2udq\nvcvtps2uqq\tvcvtqq2pd\tvcvtqq2ps\nvcvtqq2psx\nvcvt"
6777 "qq2psy\tvcvtsd2si\nvcvtsd2sil\nvcvtsd2siq\tvcvtsd2ss\nvcvtsd2usi\tvcvts"
6778 "i2sd\nvcvtsi2sdl\nvcvtsi2sdq\tvcvtsi2ss\nvcvtsi2ssl\nvcvtsi2ssq\tvcvtss"
6779 "2sd\tvcvtss2si\nvcvtss2sil\nvcvtss2siq\nvcvtss2usi\nvcvttpd2dq\013vcvtt"
6780 "pd2dqx\013vcvttpd2dqy\nvcvttpd2qq\013vcvttpd2udq\014vcvttpd2udqx\014vcv"
6781 "ttpd2udqy\013vcvttpd2uqq\nvcvttps2dq\nvcvttps2qq\013vcvttps2udq\013vcvt"
6782 "tps2uqq\nvcvttsd2si\013vcvttsd2sil\013vcvttsd2siq\013vcvttsd2usi\014vcv"
6783 "ttsd2usil\014vcvttsd2usiq\nvcvttss2si\013vcvttss2sil\013vcvttss2siq\013"
6784 "vcvttss2usi\014vcvttss2usil\014vcvttss2usiq\nvcvtudq2pd\nvcvtudq2ps\nvc"
6785 "vtuqq2pd\nvcvtuqq2ps\013vcvtuqq2psx\013vcvtuqq2psy\nvcvtusi2sd\013vcvtu"
6786 "si2sdl\013vcvtusi2sdq\nvcvtusi2ss\013vcvtusi2ssl\013vcvtusi2ssq\tvdbpsa"
6787 "dbw\006vdivpd\006vdivps\006vdivsd\006vdivss\005vdppd\005vdpps\004verr\004"
6788 "verw\007vexp2pd\007vexp2ps\tvexpandpd\tvexpandps\014vextractf128\015vex"
6789 "tractf32x4\015vextractf32x8\015vextractf64x2\015vextractf64x4\014vextra"
6790 "cti128\015vextracti32x4\015vextracti32x8\015vextracti64x2\015vextracti6"
6791 "4x4\nvextractps\013vfixupimmpd\013vfixupimmps\013vfixupimmsd\013vfixupi"
6792 "mmss\013vfmadd132pd\013vfmadd132ps\013vfmadd132sd\013vfmadd132ss\013vfm"
6793 "add213pd\013vfmadd213ps\013vfmadd213sd\013vfmadd213ss\013vfmadd231pd\013"
6794 "vfmadd231ps\013vfmadd231sd\013vfmadd231ss\010vfmaddpd\010vfmaddps\010vf"
6795 "maddsd\010vfmaddss\016vfmaddsub132pd\016vfmaddsub132ps\016vfmaddsub213p"
6796 "d\016vfmaddsub213ps\016vfmaddsub231pd\016vfmaddsub231ps\013vfmaddsubpd\013"
6797 "vfmaddsubps\013vfmsub132pd\013vfmsub132ps\013vfmsub132sd\013vfmsub132ss"
6798 "\013vfmsub213pd\013vfmsub213ps\013vfmsub213sd\013vfmsub213ss\013vfmsub2"
6799 "31pd\013vfmsub231ps\013vfmsub231sd\013vfmsub231ss\016vfmsubadd132pd\016"
6800 "vfmsubadd132ps\016vfmsubadd213pd\016vfmsubadd213ps\016vfmsubadd231pd\016"
6801 "vfmsubadd231ps\013vfmsubaddpd\013vfmsubaddps\010vfmsubpd\010vfmsubps\010"
6802 "vfmsubsd\010vfmsubss\014vfnmadd132pd\014vfnmadd132ps\014vfnmadd132sd\014"
6803 "vfnmadd132ss\014vfnmadd213pd\014vfnmadd213ps\014vfnmadd213sd\014vfnmadd"
6804 "213ss\014vfnmadd231pd\014vfnmadd231ps\014vfnmadd231sd\014vfnmadd231ss\t"
6805 "vfnmaddpd\tvfnmaddps\tvfnmaddsd\tvfnmaddss\014vfnmsub132pd\014vfnmsub13"
6806 "2ps\014vfnmsub132sd\014vfnmsub132ss\014vfnmsub213pd\014vfnmsub213ps\014"
6807 "vfnmsub213sd\014vfnmsub213ss\014vfnmsub231pd\014vfnmsub231ps\014vfnmsub"
6808 "231sd\014vfnmsub231ss\tvfnmsubpd\tvfnmsubps\tvfnmsubsd\tvfnmsubss\nvfpc"
6809 "lasspd\013vfpclasspdq\013vfpclasspdx\013vfpclasspdy\013vfpclasspdz\nvfp"
6810 "classps\013vfpclasspsl\013vfpclasspsx\013vfpclasspsy\013vfpclasspsz\nvf"
6811 "pclasssd\nvfpclassss\007vfrczpd\007vfrczps\007vfrczsd\007vfrczss\nvgath"
6812 "erdpd\nvgatherdps\015vgatherpf0dpd\015vgatherpf0dps\015vgatherpf0qpd\015"
6813 "vgatherpf0qps\015vgatherpf1dpd\015vgatherpf1dps\015vgatherpf1qpd\015vga"
6814 "therpf1qps\nvgatherqpd\nvgatherqps\tvgetexppd\tvgetexpps\tvgetexpsd\tvg"
6815 "etexpss\nvgetmantpd\nvgetmantps\nvgetmantsd\nvgetmantss\021vgf2p8affine"
6816 "invqb\016vgf2p8affineqb\nvgf2p8mulb\007vhaddpd\007vhaddps\007vhsubpd\007"
6817 "vhsubps\013vinsertf128\014vinsertf32x4\014vinsertf32x8\014vinsertf64x2\014"
6818 "vinsertf64x4\013vinserti128\014vinserti32x4\014vinserti32x8\014vinserti"
6819 "64x2\014vinserti64x4\tvinsertps\006vlddqu\010vldmxcsr\013vmaskmovdqu\nv"
6820 "maskmovpd\nvmaskmovps\006vmaxpd\006vmaxps\006vmaxsd\006vmaxss\006vmcall"
6821 "\007vmclear\006vmfunc\006vminpd\006vminps\006vminsd\006vminss\010vmlaun"
6822 "ch\006vmload\007vmmcall\007vmovapd\tvmovapd.s\007vmovaps\tvmovaps.s\005"
6823 "vmovd\010vmovddup\007vmovdqa\tvmovdqa32\013vmovdqa32.s\tvmovdqa64\013vm"
6824 "ovdqa64.s\007vmovdqu\tvmovdqu16\013vmovdqu16.s\tvmovdqu32\013vmovdqu32."
6825 "s\tvmovdqu64\013vmovdqu64.s\010vmovdqu8\nvmovdqu8.s\010vmovhlps\007vmov"
6826 "hpd\007vmovhps\010vmovlhps\007vmovlpd\007vmovlps\tvmovmskpd\tvmovmskps\010"
6827 "vmovntdq\tvmovntdqa\010vmovntpd\010vmovntps\005vmovq\007vmovq.s\006vmov"
6828 "sd\010vmovsd.s\tvmovshdup\tvmovsldup\006vmovss\010vmovss.s\007vmovupd\t"
6829 "vmovupd.s\007vmovups\tvmovups.s\010vmpsadbw\007vmptrld\007vmptrst\006vm"
6830 "read\007vmreadl\007vmreadq\010vmresume\005vmrun\006vmsave\006vmulpd\006"
6831 "vmulps\006vmulsd\006vmulss\007vmwrite\010vmwritel\010vmwriteq\006vmxoff"
6832 "\005vmxon\005vorpd\005vorps\006vpabsb\006vpabsd\006vpabsq\006vpabsw\tvp"
6833 "ackssdw\tvpacksswb\tvpackusdw\tvpackuswb\006vpaddb\006vpaddd\006vpaddq\007"
6834 "vpaddsb\007vpaddsw\010vpaddusb\010vpaddusw\006vpaddw\010vpalignr\005vpa"
6835 "nd\006vpandd\006vpandn\007vpandnd\007vpandnq\006vpandq\006vpavgb\006vpa"
6836 "vgw\010vpblendd\tvpblendmb\tvpblendmd\tvpblendmq\tvpblendmw\tvpblendvb\010"
6837 "vpblendw\014vpbroadcastb\014vpbroadcastd\017vpbroadcastmb2q\017vpbroadc"
6838 "astmw2d\014vpbroadcastq\014vpbroadcastw\015vpclmulhqhqdq\015vpclmulhqlq"
6839 "dq\015vpclmullqhqdq\015vpclmullqlqdq\nvpclmulqdq\006vpcmov\005vpcmp\006"
6840 "vpcmpb\006vpcmpd\010vpcmpeqb\010vpcmpeqd\010vpcmpeqq\010vpcmpeqw\nvpcmp"
6841 "estri\nvpcmpestrm\010vpcmpgtb\010vpcmpgtd\010vpcmpgtq\010vpcmpgtw\nvpcm"
6842 "pistri\nvpcmpistrm\006vpcmpq\007vpcmpub\007vpcmpud\007vpcmpuq\007vpcmpu"
6843 "w\006vpcmpw\005vpcom\006vpcomb\006vpcomd\013vpcompressb\013vpcompressd\013"
6844 "vpcompressq\013vpcompressw\006vpcomq\007vpcomub\007vpcomud\007vpcomuq\007"
6845 "vpcomuw\006vpcomw\013vpconflictd\013vpconflictq\010vpdpbusd\tvpdpbusds\010"
6846 "vpdpwssd\tvpdpwssds\nvperm2f128\nvperm2i128\006vpermb\006vpermd\010vper"
6847 "mi2b\010vpermi2d\tvpermi2pd\tvpermi2ps\010vpermi2q\010vpermi2w\nvpermil"
6848 "2pd\nvpermil2ps\tvpermilpd\tvpermilps\007vpermpd\007vpermps\006vpermq\010"
6849 "vpermt2b\010vpermt2d\tvpermt2pd\tvpermt2ps\010vpermt2q\010vpermt2w\006v"
6850 "permw\tvpexpandb\tvpexpandd\tvpexpandq\tvpexpandw\007vpextrb\007vpextrd"
6851 "\007vpextrq\007vpextrw\tvpextrw.s\nvpgatherdd\nvpgatherdq\nvpgatherqd\n"
6852 "vpgatherqq\010vphaddbd\010vphaddbq\010vphaddbw\007vphaddd\010vphadddq\010"
6853 "vphaddsw\tvphaddubd\tvphaddubq\tvphaddubw\tvphaddudq\tvphadduwd\tvphadd"
6854 "uwq\007vphaddw\010vphaddwd\010vphaddwq\013vphminposuw\010vphsubbw\007vp"
6855 "hsubd\010vphsubdq\010vphsubsw\007vphsubw\010vphsubwd\007vpinsrb\007vpin"
6856 "srd\007vpinsrq\007vpinsrw\010vplzcntd\010vplzcntq\010vpmacsdd\tvpmacsdq"
6857 "h\tvpmacsdql\tvpmacssdd\nvpmacssdqh\nvpmacssdql\tvpmacsswd\tvpmacssww\010"
6858 "vpmacswd\010vpmacsww\nvpmadcsswd\tvpmadcswd\013vpmadd52huq\013vpmadd52l"
6859 "uq\nvpmaddubsw\010vpmaddwd\nvpmaskmovd\nvpmaskmovq\007vpmaxsb\007vpmaxs"
6860 "d\007vpmaxsq\007vpmaxsw\007vpmaxub\007vpmaxud\007vpmaxuq\007vpmaxuw\007"
6861 "vpminsb\007vpminsd\007vpminsq\007vpminsw\007vpminub\007vpminud\007vpmin"
6862 "uq\007vpminuw\010vpmovb2m\010vpmovd2m\007vpmovdb\007vpmovdw\010vpmovm2b"
6863 "\010vpmovm2d\010vpmovm2q\010vpmovm2w\tvpmovmskb\010vpmovq2m\007vpmovqb\007"
6864 "vpmovqd\007vpmovqw\010vpmovsdb\010vpmovsdw\010vpmovsqb\010vpmovsqd\010v"
6865 "pmovsqw\010vpmovswb\tvpmovsxbd\tvpmovsxbq\tvpmovsxbw\tvpmovsxdq\tvpmovs"
6866 "xwd\tvpmovsxwq\tvpmovusdb\tvpmovusdw\tvpmovusqb\tvpmovusqd\tvpmovusqw\t"
6867 "vpmovuswb\010vpmovw2m\007vpmovwb\tvpmovzxbd\tvpmovzxbq\tvpmovzxbw\tvpmo"
6868 "vzxdq\tvpmovzxwd\tvpmovzxwq\007vpmuldq\tvpmulhrsw\010vpmulhuw\007vpmulh"
6869 "w\007vpmulld\007vpmullq\007vpmullw\016vpmultishiftqb\010vpmuludq\010vpo"
6870 "pcntb\010vpopcntd\010vpopcntq\010vpopcntw\004vpor\005vpord\005vporq\006"
6871 "vpperm\006vprold\006vprolq\007vprolvd\007vprolvq\006vprord\006vprorq\007"
6872 "vprorvd\007vprorvq\006vprotb\006vprotd\006vprotq\006vprotw\007vpsadbw\013"
6873 "vpscatterdd\013vpscatterdq\013vpscatterqd\013vpscatterqq\006vpshab\006v"
6874 "pshad\006vpshaq\006vpshaw\006vpshlb\006vpshld\007vpshldd\007vpshldq\010"
6875 "vpshldvd\010vpshldvq\010vpshldvw\007vpshldw\006vpshlq\006vpshlw\007vpsh"
6876 "rdd\007vpshrdq\010vpshrdvd\010vpshrdvq\010vpshrdvw\007vpshrdw\007vpshuf"
6877 "b\014vpshufbitqmb\007vpshufd\010vpshufhw\010vpshuflw\007vpsignb\007vpsi"
6878 "gnd\007vpsignw\006vpslld\007vpslldq\006vpsllq\007vpsllvd\007vpsllvq\007"
6879 "vpsllvw\006vpsllw\006vpsrad\006vpsraq\007vpsravd\007vpsravq\007vpsravw\006"
6880 "vpsraw\006vpsrld\007vpsrldq\006vpsrlq\007vpsrlvd\007vpsrlvq\007vpsrlvw\006"
6881 "vpsrlw\006vpsubb\006vpsubd\006vpsubq\007vpsubsb\007vpsubsw\010vpsubusb\010"
6882 "vpsubusw\006vpsubw\nvpternlogd\nvpternlogq\006vptest\010vptestmb\010vpt"
6883 "estmd\010vptestmq\010vptestmw\tvptestnmb\tvptestnmd\tvptestnmq\tvptestn"
6884 "mw\nvpunpckhbw\nvpunpckhdq\013vpunpckhqdq\nvpunpckhwd\nvpunpcklbw\nvpun"
6885 "pckldq\013vpunpcklqdq\nvpunpcklwd\005vpxor\006vpxord\006vpxorq\010vrang"
6886 "epd\010vrangeps\010vrangesd\010vrangess\010vrcp14pd\010vrcp14ps\010vrcp"
6887 "14sd\010vrcp14ss\010vrcp28pd\010vrcp28ps\010vrcp28sd\010vrcp28ss\006vrc"
6888 "pps\006vrcpss\tvreducepd\tvreduceps\tvreducesd\tvreducess\013vrndscalep"
6889 "d\013vrndscaleps\013vrndscalesd\013vrndscaless\010vroundpd\010vroundps\010"
6890 "vroundsd\010vroundss\nvrsqrt14pd\nvrsqrt14ps\nvrsqrt14sd\nvrsqrt14ss\nv"
6891 "rsqrt28pd\nvrsqrt28ps\nvrsqrt28sd\nvrsqrt28ss\010vrsqrtps\010vrsqrtss\t"
6892 "vscalefpd\tvscalefps\tvscalefsd\tvscalefss\013vscatterdpd\013vscatterdp"
6893 "s\016vscatterpf0dpd\016vscatterpf0dps\016vscatterpf0qpd\016vscatterpf0q"
6894 "ps\016vscatterpf1dpd\016vscatterpf1dps\016vscatterpf1qpd\016vscatterpf1"
6895 "qps\013vscatterqpd\013vscatterqps\nvshuff32x4\nvshuff64x2\nvshufi32x4\n"
6896 "vshufi64x2\007vshufpd\007vshufps\007vsqrtpd\007vsqrtps\007vsqrtsd\007vs"
6897 "qrtss\010vstmxcsr\006vsubpd\006vsubps\006vsubsd\006vsubss\007vtestpd\007"
6898 "vtestps\010vucomisd\010vucomiss\tvunpckhpd\tvunpckhps\tvunpcklpd\tvunpc"
6899 "klps\006vxorpd\006vxorps\010vzeroall\nvzeroupper\004wait\006wbinvd\010w"
6900 "rfsbase\twrfsbasel\twrfsbaseq\010wrgsbase\twrgsbasel\twrgsbaseq\005wrms"
6901 "r\006wrpkru\005wrssd\005wrssq\006wrussd\006wrussq\006xabort\010xacquire"
6902 "\004xadd\005xaddb\005xaddl\005xaddq\005xaddw\006xbegin\004xchg\005xchgb"
6903 "\005xchgl\005xchgq\005xchgw\txcryptcbc\txcryptcfb\txcryptctr\txcryptecb"
6904 "\txcryptofb\004xend\006xgetbv\005xlatb\003xor\004xorb\004xorl\005xorpd\005"
6905 "xorps\004xorq\004xorw\010xrelease\006xrstor\010xrstor64\007xrstors\txrs"
6906 "tors64\005xsave\007xsave64\006xsavec\010xsavec64\010xsaveopt\nxsaveopt6"
6907 "4\006xsaves\010xsaves64\006xsetbv\005xsha1\007xsha256\006xstore\txstore"
6908 "rng\005xtest";
6909
6910namespace {
6911 struct MatchEntry {
Excessive padding in 'struct (anonymous namespace)::MatchEntry' (5 padding bytes, where 1 is optimal). Optimal fields order: RequiredFeatures, Mnemonic, Opcode, ConvertFn, Classes, consider reordering the fields or adding explicit padding members
6912 uint16_t Mnemonic;
6913 uint16_t Opcode;
6914 uint16_t ConvertFn;
6915 uint32_t RequiredFeatures;
6916 uint8_t Classes[9];
6917 StringRef getMnemonic() const {
6918 return StringRef(MnemonicTable + Mnemonic + 1,
6919 MnemonicTable[Mnemonic]);
6920 }
6921 };
6922
6923 // Predicate for searching for an opcode.
6924 struct LessOpcode {
6925 bool operator()(const MatchEntry &LHS, StringRef RHS) {
6926 return LHS.getMnemonic() < RHS;
6927 }
6928 bool operator()(StringRef LHS, const MatchEntry &RHS) {
6929 return LHS < RHS.getMnemonic();
6930 }
6931 bool operator()(const MatchEntry &LHS, const MatchEntry &RHS) {
6932 return LHS.getMnemonic() < RHS.getMnemonic();
6933 }
6934 };
6935} // end anonymous namespace.
6936
6937static const MatchEntry MatchTable0[] = {
6938 { 0 /* aaa */, X86::AAA, Convert_NoOperands, Feature_Not64BitMode, { }, },
6939 { 4 /* aad */, X86::AAD8i8, Convert__imm_95_10, Feature_Not64BitMode, { }, },
6940 { 4 /* aad */, X86::AAD8i8, Convert__Imm1_0, Feature_Not64BitMode, { MCK_Imm }, },
6941 { 8 /* aam */, X86::AAM8i8, Convert__imm_95_10, Feature_Not64BitMode, { }, },
6942 { 8 /* aam */, X86::AAM8i8, Convert__Imm1_0, Feature_Not64BitMode, { MCK_Imm }, },
6943 { 12 /* aas */, X86::AAS, Convert_NoOperands, Feature_Not64BitMode, { }, },
6944 { 20 /* adcb */, X86::ADC8rr, Convert__Reg1_1__Tie0__Reg1_0, 0, { MCK_GR8, MCK_GR8 }, },
6945 { 20 /* adcb */, X86::ADC8mr, Convert__Mem85_1__Reg1_0, 0, { MCK_GR8, MCK_Mem8 }, },
6946 { 20 /* adcb */, X86::ADC8i8, Convert__Imm1_0, 0, { MCK_Imm, MCK_AL }, },
6947 { 20 /* adcb */, X86::ADC8ri, Convert__Reg1_1__Tie0__Imm1_0, 0, { MCK_Imm, MCK_GR8 }, },
6948 { 20 /* adcb */, X86::ADC8mi, Convert__Mem85_1__Imm1_0, 0, { MCK_Imm, MCK_Mem8 }, },
6949 { 20 /* adcb */, X86::ADC8rm, Convert__Reg1_1__Tie0__Mem85_0, 0, { MCK_Mem8, MCK_GR8 }, },
6950 { 25 /* adcl */, X86::ADC32rr, Convert__Reg1_1__Tie0__Reg1_0, 0, { MCK_GR32, MCK_GR32 }, },
6951 { 25 /* adcl */, X86::ADC32mr, Convert__Mem325_1__Reg1_0, 0, { MCK_GR32, MCK_Mem32 }, },
6952 { 25 /* adcl */, X86::ADC32ri8, Convert__regEAX__Tie0__ImmSExti32i81_0, 0, { MCK_ImmSExti32i8, MCK_EAX }, },
6953 { 25 /* adcl */, X86::ADC32ri8, Convert__Reg1_1__Tie0__ImmSExti32i81_0, 0, { MCK_ImmSExti32i8, MCK_GR32 }, },
6954 { 25 /* adcl */, X86::ADC32mi8, Convert__Mem325_1__ImmSExti32i81_0, 0, { MCK_ImmSExti32i8, MCK_Mem32 }, },
6955 { 25 /* adcl */, X86::ADC32i32, Convert__Imm1_0, 0, { MCK_Imm, MCK_EAX }, },
6956 { 25 /* adcl */, X86::ADC32ri, Convert__Reg1_1__Tie0__Imm1_0, 0, { MCK_Imm, MCK_GR32 }, },
6957 { 25 /* adcl */, X86::ADC32mi, Convert__Mem325_1__Imm1_0, 0, { MCK_Imm, MCK_Mem32 }, },
6958 { 25 /* adcl */, X86::ADC32rm, Convert__Reg1_1__Tie0__Mem325_0, 0, { MCK_Mem32, MCK_GR32 }, },
6959 { 30 /* adcq */, X86::ADC64rr, Convert__Reg1_1__Tie0__Reg1_0, 0, { MCK_GR64, MCK_GR64 }, },
6960 { 30 /* adcq */, X86::ADC64mr, Convert__Mem645_1__Reg1_0, 0, { MCK_GR64, MCK_Mem64 }, },
6961 { 30 /* adcq */, X86::ADC64ri8, Convert__regRAX__Tie0__ImmSExti64i81_0, 0, { MCK_ImmSExti64i8, MCK_RAX }, },
6962 { 30 /* adcq */, X86::ADC64ri8, Convert__Reg1_1__Tie0__ImmSExti64i81_0, 0, { MCK_ImmSExti64i8, MCK_GR64 }, },
6963 { 30 /* adcq */, X86::ADC64mi8, Convert__Mem645_1__ImmSExti64i81_0, Feature_In64BitMode, { MCK_ImmSExti64i8, MCK_Mem64 }, },
6964 { 30 /* adcq */, X86::ADC64i32, Convert__ImmSExti64i321_0, 0, { MCK_ImmSExti64i32, MCK_RAX }, },
6965 { 30 /* adcq */, X86::ADC64ri32, Convert__Reg1_1__Tie0__ImmSExti64i321_0, 0, { MCK_ImmSExti64i32, MCK_GR64 }, },
6966 { 30 /* adcq */, X86::ADC64mi32, Convert__Mem645_1__ImmSExti64i321_0, Feature_In64BitMode, { MCK_ImmSExti64i32, MCK_Mem64 }, },
6967 { 30 /* adcq */, X86::ADC64rm, Convert__Reg1_1__Tie0__Mem645_0, 0, { MCK_Mem64, MCK_GR64 }, },
6968 { 35 /* adcw */, X86::ADC16rr, Convert__Reg1_1__Tie0__Reg1_0, 0, { MCK_GR16, MCK_GR16 }, },
6969 { 35 /* adcw */, X86::ADC16mr, Convert__Mem165_1__Reg1_0, 0, { MCK_GR16, MCK_Mem16 }, },
6970 { 35 /* adcw */, X86::ADC16ri8, Convert__regAX__Tie0__ImmSExti16i81_0, 0, { MCK_ImmSExti16i8, MCK_AX }, },
6971 { 35 /* adcw */, X86::ADC16ri8, Convert__Reg1_1__Tie0__ImmSExti16i81_0, 0, { MCK_ImmSExti16i8, MCK_GR16 }, },
6972 { 35 /* adcw */, X86::ADC16mi8, Convert__Mem165_1__ImmSExti16i81_0, 0, { MCK_ImmSExti16i8, MCK_Mem16 }, },
6973 { 35 /* adcw */, X86::ADC16i16, Convert__Imm1_0, 0, { MCK_Imm, MCK_AX }, },
6974 { 35 /* adcw */, X86::ADC16ri, Convert__Reg1_1__Tie0__Imm1_0, 0, { MCK_Imm, MCK_GR16 }, },
6975 { 35 /* adcw */, X86::ADC16mi, Convert__Mem165_1__Imm1_0, 0, { MCK_Imm, MCK_Mem16 }, },
6976 { 35 /* adcw */, X86::ADC16rm, Convert__Reg1_1__Tie0__Mem165_0, 0, { MCK_Mem16, MCK_GR16 }, },
6977 { 45 /* adcxl */, X86::ADCX32rr, Convert__Reg1_1__Tie0__Reg1_0, 0, { MCK_GR32, MCK_GR32 }, },
6978 { 45 /* adcxl */, X86::ADCX32rm, Convert__Reg1_1__Tie0__Mem325_0, 0, { MCK_Mem32, MCK_GR32 }, },
6979 { 51 /* adcxq */, X86::ADCX64rr, Convert__Reg1_1__Tie0__Reg1_0, 0, { MCK_GR64, MCK_GR64 }, },
6980 { 51 /* adcxq */, X86::ADCX64rm, Convert__Reg1_1__Tie0__Mem645_0, 0, { MCK_Mem64, MCK_GR64 }, },
6981 { 61 /* addb */, X86::ADD8rr, Convert__Reg1_1__Tie0__Reg1_0, 0, { MCK_GR8, MCK_GR8 }, },
6982 { 61 /* addb */, X86::ADD8mr, Convert__Mem85_1__Reg1_0, 0, { MCK_GR8, MCK_Mem8 }, },
6983 { 61 /* addb */, X86::ADD8i8, Convert__Imm1_0, 0, { MCK_Imm, MCK_AL }, },
6984 { 61 /* addb */, X86::ADD8ri, Convert__Reg1_1__Tie0__Imm1_0, 0, { MCK_Imm, MCK_GR8 }, },
6985 { 61 /* addb */, X86::ADD8mi, Convert__Mem85_1__Imm1_0, 0, { MCK_Imm, MCK_Mem8 }, },
6986 { 61 /* addb */, X86::ADD8rm, Convert__Reg1_1__Tie0__Mem85_0, 0, { MCK_Mem8, MCK_GR8 }, },
6987 { 66 /* addl */, X86::ADD32rr, Convert__Reg1_1__Tie0__Reg1_0, 0, { MCK_GR32, MCK_GR32 }, },
6988 { 66 /* addl */, X86::ADD32mr, Convert__Mem325_1__Reg1_0, 0, { MCK_GR32, MCK_Mem32 }, },
6989 { 66 /* addl */, X86::ADD32ri8, Convert__regEAX__Tie0__ImmSExti32i81_0, 0, { MCK_ImmSExti32i8, MCK_EAX }, },
6990 { 66 /* addl */, X86::ADD32ri8, Convert__Reg1_1__Tie0__ImmSExti32i81_0, 0, { MCK_ImmSExti32i8, MCK_GR32 }, },
6991 { 66 /* addl */, X86::ADD32mi8, Convert__Mem325_1__ImmSExti32i81_0, 0, { MCK_ImmSExti32i8, MCK_Mem32 }, },
6992 { 66 /* addl */, X86::ADD32i32, Convert__Imm1_0, 0, { MCK_Imm, MCK_EAX }, },
6993 { 66 /* addl */, X86::ADD32ri, Convert__Reg1_1__Tie0__Imm1_0, 0, { MCK_Imm, MCK_GR32 }, },
6994 { 66 /* addl */, X86::ADD32mi, Convert__Mem325_1__Imm1_0, 0, { MCK_Imm, MCK_Mem32 }, },
6995 { 66 /* addl */, X86::ADD32rm, Convert__Reg1_1__Tie0__Mem325_0, 0, { MCK_Mem32, MCK_GR32 }, },
6996 { 71 /* addpd */, X86::ADDPDrr, Convert__Reg1_1__Tie0__Reg1_0, 0, { MCK_FR32, MCK_FR32 }, },
6997 { 71 /* addpd */, X86::ADDPDrm, Convert__Reg1_1__Tie0__Mem1285_0, 0, { MCK_Mem128, MCK_FR32 }, },
6998 { 77 /* addps */, X86::ADDPSrr, Convert__Reg1_1__Tie0__Reg1_0, 0, { MCK_FR32, MCK_FR32 }, },
6999 { 77 /* addps */, X86::ADDPSrm, Convert__Reg1_1__Tie0__Mem1285_0, 0, { MCK_Mem128, MCK_FR32 }, },
7000 { 83 /* addq */, X86::ADD64rr, Convert__Reg1_1__Tie0__Reg1_0, 0, { MCK_GR64, MCK_GR64 }, },
7001 { 83 /* addq */, X86::ADD64mr, Convert__Mem645_1__Reg1_0, 0, { MCK_GR64, MCK_Mem64 }, },
7002 { 83 /* addq */, X86::ADD64ri8, Convert__regRAX__Tie0__ImmSExti64i81_0, 0, { MCK_ImmSExti64i8, MCK_RAX }, },
7003 { 83 /* addq */, X86::ADD64ri8, Convert__Reg1_1__Tie0__ImmSExti64i81_0, 0, { MCK_ImmSExti64i8, MCK_GR64 }, },
7004 { 83 /* addq */, X86::ADD64mi8, Convert__Mem645_1__ImmSExti64i81_0, Feature_In64BitMode, { MCK_ImmSExti64i8, MCK_Mem64 }, },
7005 { 83 /* addq */, X86::ADD64i32, Convert__ImmSExti64i321_0, 0, { MCK_ImmSExti64i32, MCK_RAX }, },
7006 { 83 /* addq */, X86::ADD64ri32, Convert__Reg1_1__Tie0__ImmSExti64i321_0, 0, { MCK_ImmSExti64i32, MCK_GR64 }, },
7007 { 83 /* addq */, X86::ADD64mi32, Convert__Mem645_1__ImmSExti64i321_0, Feature_In64BitMode, { MCK_ImmSExti64i32, MCK_Mem64 }, },
7008 { 83 /* addq */, X86::ADD64rm, Convert__Reg1_1__Tie0__Mem645_0, 0, { MCK_Mem64, MCK_GR64 }, },
7009 { 88 /* addsd */, X86::ADDSDrr, Convert__Reg1_1__Tie0__Reg1_0, 0, { MCK_FR32, MCK_FR32 }, },
7010 { 88 /* addsd */, X86::ADDSDrm, Convert__Reg1_1__Tie0__Mem645_0, 0, { MCK_Mem64, MCK_FR32 }, },
7011 { 94 /* addss */, X86::ADDSSrr, Convert__Reg1_1__Tie0__Reg1_0, 0, { MCK_FR32, MCK_FR32 }, },
7012 { 94 /* addss */, X86::ADDSSrm, Convert__Reg1_1__Tie0__Mem325_0, 0, { MCK_Mem32, MCK_FR32 }, },
7013 { 100 /* addsubpd */, X86::ADDSUBPDrr, Convert__Reg1_1__Tie0__Reg1_0, 0, { MCK_FR32, MCK_FR32 }, },
7014 { 100 /* addsubpd */, X86::ADDSUBPDrm, Convert__Reg1_1__Tie0__Mem1285_0, 0, { MCK_Mem128, MCK_FR32 }, },
7015 { 109 /* addsubps */, X86::ADDSUBPSrr, Convert__Reg1_1__Tie0__Reg1_0, 0, { MCK_FR32, MCK_FR32 }, },
7016 { 109 /* addsubps */, X86::ADDSUBPSrm, Convert__Reg1_1__Tie0__Mem1285_0, 0, { MCK_Mem128, MCK_FR32 }, },
7017 { 118 /* addw */, X86::ADD16rr, Convert__Reg1_1__Tie0__Reg1_0, 0, { MCK_GR16, MCK_GR16 }, },
7018 { 118 /* addw */, X86::ADD16mr, Convert__Mem165_1__Reg1_0, 0, { MCK_GR16, MCK_Mem16 }, },
7019 { 118 /* addw */, X86::ADD16ri8, Convert__regAX__Tie0__ImmSExti16i81_0, 0, { MCK_ImmSExti16i8, MCK_AX }, },
7020 { 118 /* addw */, X86::ADD16ri8, Convert__Reg1_1__Tie0__ImmSExti16i81_0, 0, { MCK_ImmSExti16i8, MCK_GR16 }, },
7021 { 118 /* addw */, X86::ADD16mi8, Convert__Mem165_1__ImmSExti16i81_0, 0, { MCK_ImmSExti16i8, MCK_Mem16 }, },
7022 { 118 /* addw */, X86::ADD16i16, Convert__Imm1_0, 0, { MCK_Imm, MCK_AX }, },
7023 { 118 /* addw */, X86::ADD16ri, Convert__Reg1_1__Tie0__Imm1_0, 0, { MCK_Imm, MCK_GR16 }, },
7024 { 118 /* addw */, X86::ADD16mi, Convert__Mem165_1__Imm1_0, 0, { MCK_Imm, MCK_Mem16 }, },
7025 { 118 /* addw */, X86::ADD16rm, Convert__Reg1_1__Tie0__Mem165_0, 0, { MCK_Mem16, MCK_GR16 }, },
7026 { 128 /* adoxl */, X86::ADOX32rr, Convert__Reg1_1__Reg1_0, 0, { MCK_GR32, MCK_GR32 }, },
7027 { 128 /* adoxl */, X86::ADOX32rm, Convert__Reg1_1__Mem325_0, 0, { MCK_Mem32, MCK_GR32 }, },
7028 { 134 /* adoxq */, X86::ADOX64rr, Convert__Reg1_1__Reg1_0, 0, { MCK_GR64, MCK_GR64 }, },
7029 { 134 /* adoxq */, X86::ADOX64rm, Convert__Reg1_1__Mem645_0, 0, { MCK_Mem64, MCK_GR64 }, },
7030 { 140 /* aesdec */, X86::AESDECrr, Convert__Reg1_1__Tie0__Reg1_0, 0, { MCK_FR32, MCK_FR32 }, },
7031 { 140 /* aesdec */, X86::AESDECrm, Convert__Reg1_1__Tie0__Mem1285_0, 0, { MCK_Mem128, MCK_FR32 }, },
7032 { 147 /* aesdeclast */, X86::AESDECLASTrr, Convert__Reg1_1__Tie0__Reg1_0, 0, { MCK_FR32, MCK_FR32 }, },
7033 { 147 /* aesdeclast */, X86::AESDECLASTrm, Convert__Reg1_1__Tie0__Mem1285_0, 0, { MCK_Mem128, MCK_FR32 }, },
7034 { 158 /* aesenc */, X86::AESENCrr, Convert__Reg1_1__Tie0__Reg1_0, 0, { MCK_FR32, MCK_FR32 }, },
7035 { 158 /* aesenc */, X86::AESENCrm, Convert__Reg1_1__Tie0__Mem1285_0, 0, { MCK_Mem128, MCK_FR32 }, },
7036 { 165 /* aesenclast */, X86::AESENCLASTrr, Convert__Reg1_1__Tie0__Reg1_0, 0, { MCK_FR32, MCK_FR32 }, },
7037 { 165 /* aesenclast */, X86::AESENCLASTrm, Convert__Reg1_1__Tie0__Mem1285_0, 0, { MCK_Mem128, MCK_FR32 }, },
7038 { 176 /* aesimc */, X86::AESIMCrr, Convert__Reg1_1__Reg1_0, 0, { MCK_FR32, MCK_FR32 }, },
7039 { 176 /* aesimc */, X86::AESIMCrm, Convert__Reg1_1__Mem1285_0, 0, { MCK_Mem128, MCK_FR32 }, },
7040 { 183 /* aeskeygenassist */, X86::AESKEYGENASSIST128rr, Convert__Reg1_2__Reg1_1__ImmUnsignedi81_0, 0, { MCK_ImmUnsignedi8, MCK_FR32, MCK_FR32 }, },
7041 { 183 /* aeskeygenassist */, X86::AESKEYGENASSIST128rm, Convert__Reg1_2__Mem1285_1__ImmUnsignedi81_0, 0, { MCK_ImmUnsignedi8, MCK_Mem128, MCK_FR32 }, },
7042 { 203 /* andb */, X86::AND8rr, Convert__Reg1_1__Tie0__Reg1_0, 0, { MCK_GR8, MCK_GR8 }, },
7043 { 203 /* andb */, X86::AND8mr, Convert__Mem85_1__Reg1_0, 0, { MCK_GR8, MCK_Mem8 }, },
7044 { 203 /* andb */, X86::AND8i8, Convert__Imm1_0, 0, { MCK_Imm, MCK_AL }, },
7045 { 203 /* andb */, X86::AND8ri, Convert__Reg1_1__Tie0__Imm1_0, 0, { MCK_Imm, MCK_GR8 }, },
7046 { 203 /* andb */, X86::AND8mi, Convert__Mem85_1__Imm1_0, 0, { MCK_Imm, MCK_Mem8 }, },
7047 { 203 /* andb */, X86::AND8rm, Convert__Reg1_1__Tie0__Mem85_0, 0, { MCK_Mem8, MCK_GR8 }, },
7048 { 208 /* andl */, X86::AND32rr, Convert__Reg1_1__Tie0__Reg1_0, 0, { MCK_GR32, MCK_GR32 }, },
7049 { 208 /* andl */, X86::AND32mr, Convert__Mem325_1__Reg1_0, 0, { MCK_GR32, MCK_Mem32 }, },
7050 { 208 /* andl */, X86::AND32ri8, Convert__regEAX__Tie0__ImmSExti32i81_0, 0, { MCK_ImmSExti32i8, MCK_EAX }, },
7051 { 208 /* andl */, X86::AND32ri8, Convert__Reg1_1__Tie0__ImmSExti32i81_0, 0, { MCK_ImmSExti32i8, MCK_GR32 }, },
7052 { 208 /* andl */, X86::AND32mi8, Convert__Mem325_1__ImmSExti32i81_0, 0, { MCK_ImmSExti32i8, MCK_Mem32 }, },
7053 { 208 /* andl */, X86::AND32i32, Convert__Imm1_0, 0, { MCK_Imm, MCK_EAX }, },
7054 { 208 /* andl */, X86::AND32ri, Convert__Reg1_1__Tie0__Imm1_0, 0, { MCK_Imm, MCK_GR32 }, },
7055 { 208 /* andl */, X86::AND32mi, Convert__Mem325_1__Imm1_0, 0, { MCK_Imm, MCK_Mem32 }, },
7056 { 208 /* andl */, X86::AND32rm, Convert__Reg1_1__Tie0__Mem325_0, 0, { MCK_Mem32, MCK_GR32 }, },
7057 { 218 /* andnl */, X86::ANDN32rr, Convert__Reg1_2__Reg1_1__Reg1_0, 0, { MCK_GR32, MCK_GR32, MCK_GR32 }, },
7058 { 218 /* andnl */, X86::ANDN32rm, Convert__Reg1_2__Reg1_1__Mem325_0, 0, { MCK_Mem32, MCK_GR32, MCK_GR32 }, },
7059 { 224 /* andnpd */, X86::ANDNPDrr, Convert__Reg1_1__Tie0__Reg1_0, 0, { MCK_FR32, MCK_FR32 }, },
7060 { 224 /* andnpd */, X86::ANDNPDrm, Convert__Reg1_1__Tie0__Mem1285_0, 0, { MCK_Mem128, MCK_FR32 }, },
7061 { 231 /* andnps */, X86::ANDNPSrr, Convert__Reg1_1__Tie0__Reg1_0, 0, { MCK_FR32, MCK_FR32 }, },
7062 { 231 /* andnps */, X86::ANDNPSrm, Convert__Reg1_1__Tie0__Mem1285_0, 0, { MCK_Mem128, MCK_FR32 }, },
7063 { 238 /* andnq */, X86::ANDN64rr, Convert__Reg1_2__Reg1_1__Reg1_0, 0, { MCK_GR64, MCK_GR64, MCK_GR64 }, },
7064 { 238 /* andnq */, X86::ANDN64rm, Convert__Reg1_2__Reg1_1__Mem645_0, 0, { MCK_Mem64, MCK_GR64, MCK_GR64 }, },
7065 { 244 /* andpd */, X86::ANDPDrr, Convert__Reg1_1__Tie0__Reg1_0, 0, { MCK_FR32, MCK_FR32 }, },
7066 { 244 /* andpd */, X86::ANDPDrm, Convert__Reg1_1__Tie0__Mem1285_0, 0, { MCK_Mem128, MCK_FR32 }, },
7067 { 250 /* andps */, X86::ANDPSrr, Convert__Reg1_1__Tie0__Reg1_0, 0, { MCK_FR32, MCK_FR32 }, },
7068 { 250 /* andps */, X86::ANDPSrm, Convert__Reg1_1__Tie0__Mem1285_0, 0, { MCK_Mem128, MCK_FR32 }, },
7069 { 256 /* andq */, X86::AND64rr, Convert__Reg1_1__Tie0__Reg1_0, 0, { MCK_GR64, MCK_GR64 }, },
7070 { 256 /* andq */, X86::AND64mr, Convert__Mem645_1__Reg1_0, 0, { MCK_GR64, MCK_Mem64 }, },
7071 { 256 /* andq */, X86::AND64ri8, Convert__regRAX__Tie0__ImmSExti64i81_0, 0, { MCK_ImmSExti64i8, MCK_RAX }, },
7072 { 256 /* andq */, X86::AND64ri8, Convert__Reg1_1__Tie0__ImmSExti64i81_0, 0, { MCK_ImmSExti64i8, MCK_GR64 }, },
7073 { 256 /* andq */, X86::AND64mi8, Convert__Mem645_1__ImmSExti64i81_0, Feature_In64BitMode, { MCK_ImmSExti64i8, MCK_Mem64 }, },
7074 { 256 /* andq */, X86::AND64i32, Convert__ImmSExti64i321_0, 0, { MCK_ImmSExti64i32, MCK_RAX }, },
7075 { 256 /* andq */, X86::AND64ri32, Convert__Reg1_1__Tie0__ImmSExti64i321_0, 0, { MCK_ImmSExti64i32, MCK_GR64 }, },
7076 { 256 /* andq */, X86::AND64mi32, Convert__Mem645_1__ImmSExti64i321_0, Feature_In64BitMode, { MCK_ImmSExti64i32, MCK_Mem64 }, },
7077 { 256 /* andq */, X86::AND64rm, Convert__Reg1_1__Tie0__Mem645_0, 0, { MCK_Mem64, MCK_GR64 }, },
7078 { 261 /* andw */, X86::AND16rr, Convert__Reg1_1__Tie0__Reg1_0, 0, { MCK_GR16, MCK_GR16 }, },
7079 { 261 /* andw */, X86::AND16mr, Convert__Mem165_1__Reg1_0, 0, { MCK_GR16, MCK_Mem16 }, },
7080 { 261 /* andw */, X86::AND16ri8, Convert__regAX__Tie0__ImmSExti16i81_0, 0, { MCK_ImmSExti16i8, MCK_AX }, },
7081 { 261 /* andw */, X86::AND16ri8, Convert__Reg1_1__Tie0__ImmSExti16i81_0, 0, { MCK_ImmSExti16i8, MCK_GR16 }, },
7082 { 261 /* andw */, X86::AND16mi8, Convert__Mem165_1__ImmSExti16i81_0, 0, { MCK_ImmSExti16i8, MCK_Mem16 }, },
7083 { 261 /* andw */, X86::AND16i16, Convert__Imm1_0, 0, { MCK_Imm, MCK_AX }, },
7084 { 261 /* andw */, X86::AND16ri, Convert__Reg1_1__Tie0__Imm1_0, 0, { MCK_Imm, MCK_GR16 }, },
7085 { 261 /* andw */, X86::AND16mi, Convert__Mem165_1__Imm1_0, 0, { MCK_Imm, MCK_Mem16 }, },
7086 { 261 /* andw */, X86::AND16rm, Convert__Reg1_1__Tie0__Mem165_0, 0, { MCK_Mem16, MCK_GR16 }, },
7087 { 266 /* arpl */, X86::ARPL16rr, Convert__Reg1_1__Reg1_0, Feature_Not64BitMode, { MCK_GR16, MCK_GR16 }, },
7088 { 266 /* arpl */, X86::ARPL16mr, Convert__Mem165_1__Reg1_0, Feature_Not64BitMode, { MCK_GR16, MCK_Mem16 }, },
7089 { 271 /* bextr */, X86::BEXTRI64ri, Convert__Reg1_2__Reg1_1__ImmSExti64i321_0, 0, { MCK_ImmSExti64i32, MCK_GR64, MCK_GR64 }, },
7090 { 271 /* bextr */, X86::BEXTRI64mi, Convert__Reg1_2__Mem645_1__ImmSExti64i321_0, 0, { MCK_ImmSExti64i32, MCK_Mem64, MCK_GR64 }, },
7091 { 271 /* bextr */, X86::BEXTRI32ri, Convert__Reg1_2__Reg1_1__Imm1_0, 0, { MCK_Imm, MCK_GR32, MCK_GR32 }, },
7092 { 271 /* bextr */, X86::BEXTRI32mi, Convert__Reg1_2__Mem325_1__Imm1_0, 0, { MCK_Imm, MCK_Mem32, MCK_GR32 }, },
7093 { 277 /* bextrl */, X86::BEXTR32rr, Convert__Reg1_2__Reg1_1__Reg1_0, 0, { MCK_GR32, MCK_GR32, MCK_GR32 }, },
7094 { 277 /* bextrl */, X86::BEXTR32rm, Convert__Reg1_2__Mem325_1__Reg1_0, 0, { MCK_GR32, MCK_Mem32, MCK_GR32 }, },
7095 { 284 /* bextrq */, X86::BEXTR64rr, Convert__Reg1_2__Reg1_1__Reg1_0, 0, { MCK_GR64, MCK_GR64, MCK_GR64 }, },
7096 { 284 /* bextrq */, X86::BEXTR64rm, Convert__Reg1_2__Mem645_1__Reg1_0, 0, { MCK_GR64, MCK_Mem64, MCK_GR64 }, },
7097 { 291 /* blcfill */, X86::BLCFILL32rr, Convert__Reg1_1__Reg1_0, 0, { MCK_GR32, MCK_GR32 }, },
7098 { 291 /* blcfill */, X86::BLCFILL64rr, Convert__Reg1_1__Reg1_0, 0, { MCK_GR64, MCK_GR64 }, },
7099 { 291 /* blcfill */, X86::BLCFILL32rm, Convert__Reg1_1__Mem325_0, 0, { MCK_Mem32, MCK_GR32 }, },
7100 { 291 /* blcfill */, X86::BLCFILL64rm, Convert__Reg1_1__Mem645_0, 0, { MCK_Mem64, MCK_GR64 }, },
7101 { 299 /* blci */, X86::BLCI32rr, Convert__Reg1_1__Reg1_0, 0, { MCK_GR32, MCK_GR32 }, },
7102 { 299 /* blci */, X86::BLCI64rr, Convert__Reg1_1__Reg1_0, 0, { MCK_GR64, MCK_GR64 }, },
7103 { 299 /* blci */, X86::BLCI32rm, Convert__Reg1_1__Mem325_0, 0, { MCK_Mem32, MCK_GR32 }, },
7104 { 299 /* blci */, X86::BLCI64rm, Convert__Reg1_1__Mem645_0, 0, { MCK_Mem64, MCK_GR64 }, },
7105 { 304 /* blcic */, X86::BLCIC32rr, Convert__Reg1_1__Reg1_0, 0, { MCK_GR32, MCK_GR32 }, },
7106 { 304 /* blcic */, X86::BLCIC64rr, Convert__Reg1_1__Reg1_0, 0, { MCK_GR64, MCK_GR64 }, },
7107 { 304 /* blcic */, X86::BLCIC32rm, Convert__Reg1_1__Mem325_0, 0, { MCK_Mem32, MCK_GR32 }, },
7108 { 304 /* blcic */, X86::BLCIC64rm, Convert__Reg1_1__Mem645_0, 0, { MCK_Mem64, MCK_GR64 }, },
7109 { 310 /* blcmsk */, X86::BLCMSK32rr, Convert__Reg1_1__Reg1_0, 0, { MCK_GR32, MCK_GR32 }, },
7110 { 310 /* blcmsk */, X86::BLCMSK64rr, Convert__Reg1_1__Reg1_0, 0, { MCK_GR64, MCK_GR64 }, },
7111 { 310 /* blcmsk */, X86::BLCMSK32rm, Convert__Reg1_1__Mem325_0, 0, { MCK_Mem32, MCK_GR32 }, },
7112 { 310 /* blcmsk */, X86::BLCMSK64rm, Convert__Reg1_1__Mem645_0, 0, { MCK_Mem64, MCK_GR64 }, },
7113 { 317 /* blcs */, X86::BLCS32rr, Convert__Reg1_1__Reg1_0, 0, { MCK_GR32, MCK_GR32 }, },
7114 { 317 /* blcs */, X86::BLCS64rr, Convert__Reg1_1__Reg1_0, 0, { MCK_GR64, MCK_GR64 }, },
7115 { 317 /* blcs */, X86::BLCS32rm, Convert__Reg1_1__Mem325_0, 0, { MCK_Mem32, MCK_GR32 }, },
7116 { 317 /* blcs */, X86::BLCS64rm, Convert__Reg1_1__Mem645_0, 0, { MCK_Mem64, MCK_GR64 }, },
7117 { 322 /* blendpd */, X86::BLENDPDrri, Convert__Reg1_2__Tie0__Reg1_1__ImmUnsignedi81_0, 0, { MCK_ImmUnsignedi8, MCK_FR32, MCK_FR32 }, },
7118 { 322 /* blendpd */, X86::BLENDPDrmi, Convert__Reg1_2__Tie0__Mem1285_1__ImmUnsignedi81_0, 0, { MCK_ImmUnsignedi8, MCK_Mem128, MCK_FR32 }, },
7119 { 330 /* blendps */, X86::BLENDPSrri, Convert__Reg1_2__Tie0__Reg1_1__ImmUnsignedi81_0, 0, { MCK_ImmUnsignedi8, MCK_FR32, MCK_FR32 }, },
7120 { 330 /* blendps */, X86::BLENDPSrmi, Convert__Reg1_2__Tie0__Mem1285_1__ImmUnsignedi81_0, 0, { MCK_ImmUnsignedi8, MCK_Mem128, MCK_FR32 }, },
7121 { 338 /* blendvpd */, X86::BLENDVPDrr0, Convert__Reg1_1__Tie0__Reg1_0, 0, { MCK_FR32, MCK_FR32 }, },
7122 { 338 /* blendvpd */, X86::BLENDVPDrm0, Convert__Reg1_1__Tie0__Mem1285_0, 0, { MCK_Mem128, MCK_FR32 }, },
7123 { 338 /* blendvpd */, X86::BLENDVPDrr0, Convert__Reg1_2__Tie0__Reg1_1, 0, { MCK_XMM0, MCK_FR32, MCK_FR32 }, },
7124 { 338 /* blendvpd */, X86::BLENDVPDrm0, Convert__Reg1_2__Tie0__Mem1285_1, 0, { MCK_XMM0, MCK_Mem128, MCK_FR32 }, },
7125 { 347 /* blendvps */, X86::BLENDVPSrr0, Convert__Reg1_1__Tie0__Reg1_0, 0, { MCK_FR32, MCK_FR32 }, },
7126 { 347 /* blendvps */, X86::BLENDVPSrm0, Convert__Reg1_1__Tie0__Mem1285_0, 0, { MCK_Mem128, MCK_FR32 }, },
7127 { 347 /* blendvps */, X86::BLENDVPSrr0, Convert__Reg1_2__Tie0__Reg1_1, 0, { MCK_XMM0, MCK_FR32, MCK_FR32 }, },
7128 { 347 /* blendvps */, X86::BLENDVPSrm0, Convert__Reg1_2__Tie0__Mem1285_1, 0, { MCK_XMM0, MCK_Mem128, MCK_FR32 }, },
7129 { 356 /* blsfill */, X86::BLSFILL32rr, Convert__Reg1_1__Reg1_0, 0, { MCK_GR32, MCK_GR32 }, },
7130 { 356 /* blsfill */, X86::BLSFILL64rr, Convert__Reg1_1__Reg1_0, 0, { MCK_GR64, MCK_G