Bug Summary

File:lib/Target/X86/X86ISelLowering.cpp
Warning:line 6661, column 1
Potential leak of memory pointed to by 'UndefMask.X'

Annotated Source Code

/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp

1//===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that X86 uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#include "X86ISelLowering.h"
16#include "Utils/X86ShuffleDecode.h"
17#include "X86CallingConv.h"
18#include "X86FrameLowering.h"
19#include "X86InstrBuilder.h"
20#include "X86IntrinsicsInfo.h"
21#include "X86MachineFunctionInfo.h"
22#include "X86ShuffleDecodeConstantPool.h"
23#include "X86TargetMachine.h"
24#include "X86TargetObjectFile.h"
25#include "llvm/ADT/SmallBitVector.h"
26#include "llvm/ADT/SmallSet.h"
27#include "llvm/ADT/Statistic.h"
28#include "llvm/ADT/StringExtras.h"
29#include "llvm/ADT/StringSwitch.h"
30#include "llvm/Analysis/EHPersonalities.h"
31#include "llvm/CodeGen/IntrinsicLowering.h"
32#include "llvm/CodeGen/MachineFrameInfo.h"
33#include "llvm/CodeGen/MachineFunction.h"
34#include "llvm/CodeGen/MachineInstrBuilder.h"
35#include "llvm/CodeGen/MachineJumpTableInfo.h"
36#include "llvm/CodeGen/MachineModuleInfo.h"
37#include "llvm/CodeGen/MachineRegisterInfo.h"
38#include "llvm/CodeGen/TargetLowering.h"
39#include "llvm/CodeGen/WinEHFuncInfo.h"
40#include "llvm/IR/CallSite.h"
41#include "llvm/IR/CallingConv.h"
42#include "llvm/IR/Constants.h"
43#include "llvm/IR/DerivedTypes.h"
44#include "llvm/IR/DiagnosticInfo.h"
45#include "llvm/IR/Function.h"
46#include "llvm/IR/GlobalAlias.h"
47#include "llvm/IR/GlobalVariable.h"
48#include "llvm/IR/Instructions.h"
49#include "llvm/IR/Intrinsics.h"
50#include "llvm/MC/MCAsmInfo.h"
51#include "llvm/MC/MCContext.h"
52#include "llvm/MC/MCExpr.h"
53#include "llvm/MC/MCSymbol.h"
54#include "llvm/Support/CommandLine.h"
55#include "llvm/Support/Debug.h"
56#include "llvm/Support/ErrorHandling.h"
57#include "llvm/Support/KnownBits.h"
58#include "llvm/Support/MathExtras.h"
59#include "llvm/Target/TargetOptions.h"
60#include <algorithm>
61#include <bitset>
62#include <cctype>
63#include <numeric>
64using namespace llvm;
65
66#define DEBUG_TYPE"x86-isel" "x86-isel"
67
68STATISTIC(NumTailCalls, "Number of tail calls")static llvm::Statistic NumTailCalls = {"x86-isel", "NumTailCalls"
, "Number of tail calls", {0}, false}
;
69
70static cl::opt<bool> ExperimentalVectorWideningLegalization(
71 "x86-experimental-vector-widening-legalization", cl::init(false),
72 cl::desc("Enable an experimental vector type legalization through widening "
73 "rather than promotion."),
74 cl::Hidden);
75
76static cl::opt<int> ExperimentalPrefLoopAlignment(
77 "x86-experimental-pref-loop-alignment", cl::init(4),
78 cl::desc("Sets the preferable loop alignment for experiments "
79 "(the last x86-experimental-pref-loop-alignment bits"
80 " of the loop header PC will be 0)."),
81 cl::Hidden);
82
83static cl::opt<bool> MulConstantOptimization(
84 "mul-constant-optimization", cl::init(true),
85 cl::desc("Replace 'mul x, Const' with more effective instructions like "
86 "SHIFT, LEA, etc."),
87 cl::Hidden);
88
89/// Call this when the user attempts to do something unsupported, like
90/// returning a double without SSE2 enabled on x86_64. This is not fatal, unlike
91/// report_fatal_error, so calling code should attempt to recover without
92/// crashing.
93static void errorUnsupported(SelectionDAG &DAG, const SDLoc &dl,
94 const char *Msg) {
95 MachineFunction &MF = DAG.getMachineFunction();
96 DAG.getContext()->diagnose(
97 DiagnosticInfoUnsupported(*MF.getFunction(), Msg, dl.getDebugLoc()));
98}
99
100X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
101 const X86Subtarget &STI)
102 : TargetLowering(TM), Subtarget(STI) {
103 bool UseX87 = !Subtarget.useSoftFloat() && Subtarget.hasX87();
104 X86ScalarSSEf64 = Subtarget.hasSSE2();
105 X86ScalarSSEf32 = Subtarget.hasSSE1();
106 MVT PtrVT = MVT::getIntegerVT(8 * TM.getPointerSize());
107
108 // Set up the TargetLowering object.
109
110 // X86 is weird. It always uses i8 for shift amounts and setcc results.
111 setBooleanContents(ZeroOrOneBooleanContent);
112 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
113 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
114
115 // For 64-bit, since we have so many registers, use the ILP scheduler.
116 // For 32-bit, use the register pressure specific scheduling.
117 // For Atom, always use ILP scheduling.
118 if (Subtarget.isAtom())
119 setSchedulingPreference(Sched::ILP);
120 else if (Subtarget.is64Bit())
121 setSchedulingPreference(Sched::ILP);
122 else
123 setSchedulingPreference(Sched::RegPressure);
124 const X86RegisterInfo *RegInfo = Subtarget.getRegisterInfo();
125 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
126
127 // Bypass expensive divides and use cheaper ones.
128 if (TM.getOptLevel() >= CodeGenOpt::Default) {
129 if (Subtarget.hasSlowDivide32())
130 addBypassSlowDiv(32, 8);
131 if (Subtarget.hasSlowDivide64() && Subtarget.is64Bit())
132 addBypassSlowDiv(64, 32);
133 }
134
135 if (Subtarget.isTargetKnownWindowsMSVC() ||
136 Subtarget.isTargetWindowsItanium()) {
137 // Setup Windows compiler runtime calls.
138 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
139 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
140 setLibcallName(RTLIB::SREM_I64, "_allrem");
141 setLibcallName(RTLIB::UREM_I64, "_aullrem");
142 setLibcallName(RTLIB::MUL_I64, "_allmul");
143 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
144 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
145 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
146 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
147 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
148 }
149
150 if (Subtarget.isTargetDarwin()) {
151 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
152 setUseUnderscoreSetJmp(false);
153 setUseUnderscoreLongJmp(false);
154 } else if (Subtarget.isTargetWindowsGNU()) {
155 // MS runtime is weird: it exports _setjmp, but longjmp!
156 setUseUnderscoreSetJmp(true);
157 setUseUnderscoreLongJmp(false);
158 } else {
159 setUseUnderscoreSetJmp(true);
160 setUseUnderscoreLongJmp(true);
161 }
162
163 // Set up the register classes.
164 addRegisterClass(MVT::i8, &X86::GR8RegClass);
165 addRegisterClass(MVT::i16, &X86::GR16RegClass);
166 addRegisterClass(MVT::i32, &X86::GR32RegClass);
167 if (Subtarget.is64Bit())
168 addRegisterClass(MVT::i64, &X86::GR64RegClass);
169
170 for (MVT VT : MVT::integer_valuetypes())
171 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
172
173 // We don't accept any truncstore of integer registers.
174 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
175 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
176 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
177 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
178 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
179 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
180
181 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
182
183 // SETOEQ and SETUNE require checking two conditions.
184 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
185 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
186 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
187 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
188 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
189 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
190
191 // Integer absolute.
192 if (Subtarget.hasCMov()) {
193 setOperationAction(ISD::ABS , MVT::i16 , Custom);
194 setOperationAction(ISD::ABS , MVT::i32 , Custom);
195 if (Subtarget.is64Bit())
196 setOperationAction(ISD::ABS , MVT::i64 , Custom);
197 }
198
199 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
200 // operation.
201 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
202 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
203 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
204
205 if (Subtarget.is64Bit()) {
206 if (!Subtarget.useSoftFloat() && Subtarget.hasAVX512())
207 // f32/f64 are legal, f80 is custom.
208 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
209 else
210 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
211 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
212 } else if (!Subtarget.useSoftFloat()) {
213 // We have an algorithm for SSE2->double, and we turn this into a
214 // 64-bit FILD followed by conditional FADD for other targets.
215 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
216 // We have an algorithm for SSE2, and we turn this into a 64-bit
217 // FILD or VCVTUSI2SS/SD for other targets.
218 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
219 }
220
221 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
222 // this operation.
223 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
224 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
225
226 if (!Subtarget.useSoftFloat()) {
227 // SSE has no i16 to fp conversion, only i32.
228 if (X86ScalarSSEf32) {
229 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
230 // f32 and f64 cases are Legal, f80 case is not
231 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
232 } else {
233 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
234 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
235 }
236 } else {
237 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
238 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
239 }
240
241 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
242 // this operation.
243 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
244 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
245
246 if (!Subtarget.useSoftFloat()) {
247 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
248 // are Legal, f80 is custom lowered.
249 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
250 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
251
252 if (X86ScalarSSEf32) {
253 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
254 // f32 and f64 cases are Legal, f80 case is not
255 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
256 } else {
257 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
258 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
259 }
260 } else {
261 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
262 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Expand);
263 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Expand);
264 }
265
266 // Handle FP_TO_UINT by promoting the destination to a larger signed
267 // conversion.
268 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
269 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
270 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
271
272 if (Subtarget.is64Bit()) {
273 if (!Subtarget.useSoftFloat() && Subtarget.hasAVX512()) {
274 // FP_TO_UINT-i32/i64 is legal for f32/f64, but custom for f80.
275 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
276 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
277 } else {
278 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
279 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
280 }
281 } else if (!Subtarget.useSoftFloat()) {
282 // Since AVX is a superset of SSE3, only check for SSE here.
283 if (Subtarget.hasSSE1() && !Subtarget.hasSSE3())
284 // Expand FP_TO_UINT into a select.
285 // FIXME: We would like to use a Custom expander here eventually to do
286 // the optimal thing for SSE vs. the default expansion in the legalizer.
287 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
288 else
289 // With AVX512 we can use vcvts[ds]2usi for f32/f64->i32, f80 is custom.
290 // With SSE3 we can use fisttpll to convert to a signed i64; without
291 // SSE, we're stuck with a fistpll.
292 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
293
294 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
295 }
296
297 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
298 if (!X86ScalarSSEf64) {
299 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
300 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
301 if (Subtarget.is64Bit()) {
302 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
303 // Without SSE, i64->f64 goes through memory.
304 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
305 }
306 } else if (!Subtarget.is64Bit())
307 setOperationAction(ISD::BITCAST , MVT::i64 , Custom);
308
309 // Scalar integer divide and remainder are lowered to use operations that
310 // produce two results, to match the available instructions. This exposes
311 // the two-result form to trivial CSE, which is able to combine x/y and x%y
312 // into a single instruction.
313 //
314 // Scalar integer multiply-high is also lowered to use two-result
315 // operations, to match the available instructions. However, plain multiply
316 // (low) operations are left as Legal, as there are single-result
317 // instructions for this in x86. Using the two-result multiply instructions
318 // when both high and low results are needed must be arranged by dagcombine.
319 for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
320 setOperationAction(ISD::MULHS, VT, Expand);
321 setOperationAction(ISD::MULHU, VT, Expand);
322 setOperationAction(ISD::SDIV, VT, Expand);
323 setOperationAction(ISD::UDIV, VT, Expand);
324 setOperationAction(ISD::SREM, VT, Expand);
325 setOperationAction(ISD::UREM, VT, Expand);
326 }
327
328 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
329 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
330 for (auto VT : { MVT::f32, MVT::f64, MVT::f80, MVT::f128,
331 MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
332 setOperationAction(ISD::BR_CC, VT, Expand);
333 setOperationAction(ISD::SELECT_CC, VT, Expand);
334 }
335 if (Subtarget.is64Bit())
336 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
337 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
338 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
339 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
340 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
341
342 setOperationAction(ISD::FREM , MVT::f32 , Expand);
343 setOperationAction(ISD::FREM , MVT::f64 , Expand);
344 setOperationAction(ISD::FREM , MVT::f80 , Expand);
345 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
346
347 // Promote the i8 variants and force them on up to i32 which has a shorter
348 // encoding.
349 setOperationPromotedToType(ISD::CTTZ , MVT::i8 , MVT::i32);
350 setOperationPromotedToType(ISD::CTTZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
351 if (!Subtarget.hasBMI()) {
352 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
353 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
354 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Legal);
355 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Legal);
356 if (Subtarget.is64Bit()) {
357 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
358 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Legal);
359 }
360 }
361
362 if (Subtarget.hasLZCNT()) {
363 // When promoting the i8 variants, force them to i32 for a shorter
364 // encoding.
365 setOperationPromotedToType(ISD::CTLZ , MVT::i8 , MVT::i32);
366 setOperationPromotedToType(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
367 } else {
368 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
369 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
370 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
371 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
372 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
373 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
374 if (Subtarget.is64Bit()) {
375 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
376 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
377 }
378 }
379
380 // Special handling for half-precision floating point conversions.
381 // If we don't have F16C support, then lower half float conversions
382 // into library calls.
383 if (Subtarget.useSoftFloat() || !Subtarget.hasF16C()) {
384 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
385 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
386 }
387
388 // There's never any support for operations beyond MVT::f32.
389 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
390 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
391 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
392 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
393
394 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
395 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
396 setLoadExtAction(ISD::EXTLOAD, MVT::f80, MVT::f16, Expand);
397 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
398 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
399 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
400
401 if (Subtarget.hasPOPCNT()) {
402 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
403 } else {
404 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
405 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
406 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
407 if (Subtarget.is64Bit())
408 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
409 }
410
411 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
412
413 if (!Subtarget.hasMOVBE())
414 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
415
416 // These should be promoted to a larger select which is supported.
417 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
418 // X86 wants to expand cmov itself.
419 for (auto VT : { MVT::f32, MVT::f64, MVT::f80, MVT::f128 }) {
420 setOperationAction(ISD::SELECT, VT, Custom);
421 setOperationAction(ISD::SETCC, VT, Custom);
422 }
423 for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
424 if (VT == MVT::i64 && !Subtarget.is64Bit())
425 continue;
426 setOperationAction(ISD::SELECT, VT, Custom);
427 setOperationAction(ISD::SETCC, VT, Custom);
428 }
429
430 // Custom action for SELECT MMX and expand action for SELECT_CC MMX
431 setOperationAction(ISD::SELECT, MVT::x86mmx, Custom);
432 setOperationAction(ISD::SELECT_CC, MVT::x86mmx, Expand);
433
434 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
435 // NOTE: EH_SJLJ_SETJMP/_LONGJMP are not recommended, since
436 // LLVM/Clang supports zero-cost DWARF and SEH exception handling.
437 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
438 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
439 setOperationAction(ISD::EH_SJLJ_SETUP_DISPATCH, MVT::Other, Custom);
440 if (TM.Options.ExceptionModel == ExceptionHandling::SjLj)
441 setLibcallName(RTLIB::UNWIND_RESUME, "_Unwind_SjLj_Resume");
442
443 // Darwin ABI issue.
444 for (auto VT : { MVT::i32, MVT::i64 }) {
445 if (VT == MVT::i64 && !Subtarget.is64Bit())
446 continue;
447 setOperationAction(ISD::ConstantPool , VT, Custom);
448 setOperationAction(ISD::JumpTable , VT, Custom);
449 setOperationAction(ISD::GlobalAddress , VT, Custom);
450 setOperationAction(ISD::GlobalTLSAddress, VT, Custom);
451 setOperationAction(ISD::ExternalSymbol , VT, Custom);
452 setOperationAction(ISD::BlockAddress , VT, Custom);
453 }
454
455 // 64-bit shl, sra, srl (iff 32-bit x86)
456 for (auto VT : { MVT::i32, MVT::i64 }) {
457 if (VT == MVT::i64 && !Subtarget.is64Bit())
458 continue;
459 setOperationAction(ISD::SHL_PARTS, VT, Custom);
460 setOperationAction(ISD::SRA_PARTS, VT, Custom);
461 setOperationAction(ISD::SRL_PARTS, VT, Custom);
462 }
463
464 if (Subtarget.hasSSE1())
465 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
466
467 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
468
469 // Expand certain atomics
470 for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
471 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
472 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
473 setOperationAction(ISD::ATOMIC_LOAD_ADD, VT, Custom);
474 setOperationAction(ISD::ATOMIC_LOAD_OR, VT, Custom);
475 setOperationAction(ISD::ATOMIC_LOAD_XOR, VT, Custom);
476 setOperationAction(ISD::ATOMIC_LOAD_AND, VT, Custom);
477 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
478 }
479
480 if (Subtarget.hasCmpxchg16b()) {
481 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
482 }
483
484 // FIXME - use subtarget debug flags
485 if (!Subtarget.isTargetDarwin() && !Subtarget.isTargetELF() &&
486 !Subtarget.isTargetCygMing() && !Subtarget.isTargetWin64() &&
487 TM.Options.ExceptionModel != ExceptionHandling::SjLj) {
488 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
489 }
490
491 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
492 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
493
494 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
495 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
496
497 setOperationAction(ISD::TRAP, MVT::Other, Legal);
498 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
499
500 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
501 setOperationAction(ISD::VASTART , MVT::Other, Custom);
502 setOperationAction(ISD::VAEND , MVT::Other, Expand);
503 bool Is64Bit = Subtarget.is64Bit();
504 setOperationAction(ISD::VAARG, MVT::Other, Is64Bit ? Custom : Expand);
505 setOperationAction(ISD::VACOPY, MVT::Other, Is64Bit ? Custom : Expand);
506
507 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
508 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
509
510 setOperationAction(ISD::DYNAMIC_STACKALLOC, PtrVT, Custom);
511
512 // GC_TRANSITION_START and GC_TRANSITION_END need custom lowering.
513 setOperationAction(ISD::GC_TRANSITION_START, MVT::Other, Custom);
514 setOperationAction(ISD::GC_TRANSITION_END, MVT::Other, Custom);
515
516 if (!Subtarget.useSoftFloat() && X86ScalarSSEf64) {
517 // f32 and f64 use SSE.
518 // Set up the FP register classes.
519 addRegisterClass(MVT::f32, Subtarget.hasAVX512() ? &X86::FR32XRegClass
520 : &X86::FR32RegClass);
521 addRegisterClass(MVT::f64, Subtarget.hasAVX512() ? &X86::FR64XRegClass
522 : &X86::FR64RegClass);
523
524 for (auto VT : { MVT::f32, MVT::f64 }) {
525 // Use ANDPD to simulate FABS.
526 setOperationAction(ISD::FABS, VT, Custom);
527
528 // Use XORP to simulate FNEG.
529 setOperationAction(ISD::FNEG, VT, Custom);
530
531 // Use ANDPD and ORPD to simulate FCOPYSIGN.
532 setOperationAction(ISD::FCOPYSIGN, VT, Custom);
533
534 // We don't support sin/cos/fmod
535 setOperationAction(ISD::FSIN , VT, Expand);
536 setOperationAction(ISD::FCOS , VT, Expand);
537 setOperationAction(ISD::FSINCOS, VT, Expand);
538 }
539
540 // Lower this to MOVMSK plus an AND.
541 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
542 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
543
544 // Expand FP immediates into loads from the stack, except for the special
545 // cases we handle.
546 addLegalFPImmediate(APFloat(+0.0)); // xorpd
547 addLegalFPImmediate(APFloat(+0.0f)); // xorps
548 } else if (UseX87 && X86ScalarSSEf32) {
549 // Use SSE for f32, x87 for f64.
550 // Set up the FP register classes.
551 addRegisterClass(MVT::f32, Subtarget.hasAVX512() ? &X86::FR32XRegClass
552 : &X86::FR32RegClass);
553 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
554
555 // Use ANDPS to simulate FABS.
556 setOperationAction(ISD::FABS , MVT::f32, Custom);
557
558 // Use XORP to simulate FNEG.
559 setOperationAction(ISD::FNEG , MVT::f32, Custom);
560
561 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
562
563 // Use ANDPS and ORPS to simulate FCOPYSIGN.
564 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
565 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
566
567 // We don't support sin/cos/fmod
568 setOperationAction(ISD::FSIN , MVT::f32, Expand);
569 setOperationAction(ISD::FCOS , MVT::f32, Expand);
570 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
571
572 // Special cases we handle for FP constants.
573 addLegalFPImmediate(APFloat(+0.0f)); // xorps
574 addLegalFPImmediate(APFloat(+0.0)); // FLD0
575 addLegalFPImmediate(APFloat(+1.0)); // FLD1
576 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
577 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
578
579 // Always expand sin/cos functions even though x87 has an instruction.
580 setOperationAction(ISD::FSIN , MVT::f64, Expand);
581 setOperationAction(ISD::FCOS , MVT::f64, Expand);
582 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
583 } else if (UseX87) {
584 // f32 and f64 in x87.
585 // Set up the FP register classes.
586 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
587 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
588
589 for (auto VT : { MVT::f32, MVT::f64 }) {
590 setOperationAction(ISD::UNDEF, VT, Expand);
591 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
592
593 // Always expand sin/cos functions even though x87 has an instruction.
594 setOperationAction(ISD::FSIN , VT, Expand);
595 setOperationAction(ISD::FCOS , VT, Expand);
596 setOperationAction(ISD::FSINCOS, VT, Expand);
597 }
598 addLegalFPImmediate(APFloat(+0.0)); // FLD0
599 addLegalFPImmediate(APFloat(+1.0)); // FLD1
600 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
601 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
602 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
603 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
604 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
605 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
606 }
607
608 // We don't support FMA.
609 setOperationAction(ISD::FMA, MVT::f64, Expand);
610 setOperationAction(ISD::FMA, MVT::f32, Expand);
611
612 // Long double always uses X87, except f128 in MMX.
613 if (UseX87) {
614 if (Subtarget.is64Bit() && Subtarget.hasMMX()) {
615 addRegisterClass(MVT::f128, &X86::FR128RegClass);
616 ValueTypeActions.setTypeAction(MVT::f128, TypeSoftenFloat);
617 setOperationAction(ISD::FABS , MVT::f128, Custom);
618 setOperationAction(ISD::FNEG , MVT::f128, Custom);
619 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Custom);
620 }
621
622 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
623 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
624 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
625 {
626 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended());
627 addLegalFPImmediate(TmpFlt); // FLD0
628 TmpFlt.changeSign();
629 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
630
631 bool ignored;
632 APFloat TmpFlt2(+1.0);
633 TmpFlt2.convert(APFloat::x87DoubleExtended(), APFloat::rmNearestTiesToEven,
634 &ignored);
635 addLegalFPImmediate(TmpFlt2); // FLD1
636 TmpFlt2.changeSign();
637 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
638 }
639
640 // Always expand sin/cos functions even though x87 has an instruction.
641 setOperationAction(ISD::FSIN , MVT::f80, Expand);
642 setOperationAction(ISD::FCOS , MVT::f80, Expand);
643 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
644
645 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
646 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
647 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
648 setOperationAction(ISD::FRINT, MVT::f80, Expand);
649 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
650 setOperationAction(ISD::FMA, MVT::f80, Expand);
651 }
652
653 // Always use a library call for pow.
654 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
655 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
656 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
657
658 setOperationAction(ISD::FLOG, MVT::f80, Expand);
659 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
660 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
661 setOperationAction(ISD::FEXP, MVT::f80, Expand);
662 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
663 setOperationAction(ISD::FMINNUM, MVT::f80, Expand);
664 setOperationAction(ISD::FMAXNUM, MVT::f80, Expand);
665
666 // Some FP actions are always expanded for vector types.
667 for (auto VT : { MVT::v4f32, MVT::v8f32, MVT::v16f32,
668 MVT::v2f64, MVT::v4f64, MVT::v8f64 }) {
669 setOperationAction(ISD::FSIN, VT, Expand);
670 setOperationAction(ISD::FSINCOS, VT, Expand);
671 setOperationAction(ISD::FCOS, VT, Expand);
672 setOperationAction(ISD::FREM, VT, Expand);
673 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
674 setOperationAction(ISD::FPOW, VT, Expand);
675 setOperationAction(ISD::FLOG, VT, Expand);
676 setOperationAction(ISD::FLOG2, VT, Expand);
677 setOperationAction(ISD::FLOG10, VT, Expand);
678 setOperationAction(ISD::FEXP, VT, Expand);
679 setOperationAction(ISD::FEXP2, VT, Expand);
680 }
681
682 // First set operation action for all vector types to either promote
683 // (for widening) or expand (for scalarization). Then we will selectively
684 // turn on ones that can be effectively codegen'd.
685 for (MVT VT : MVT::vector_valuetypes()) {
686 setOperationAction(ISD::SDIV, VT, Expand);
687 setOperationAction(ISD::UDIV, VT, Expand);
688 setOperationAction(ISD::SREM, VT, Expand);
689 setOperationAction(ISD::UREM, VT, Expand);
690 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
691 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
692 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
693 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
694 setOperationAction(ISD::FMA, VT, Expand);
695 setOperationAction(ISD::FFLOOR, VT, Expand);
696 setOperationAction(ISD::FCEIL, VT, Expand);
697 setOperationAction(ISD::FTRUNC, VT, Expand);
698 setOperationAction(ISD::FRINT, VT, Expand);
699 setOperationAction(ISD::FNEARBYINT, VT, Expand);
700 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
701 setOperationAction(ISD::MULHS, VT, Expand);
702 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
703 setOperationAction(ISD::MULHU, VT, Expand);
704 setOperationAction(ISD::SDIVREM, VT, Expand);
705 setOperationAction(ISD::UDIVREM, VT, Expand);
706 setOperationAction(ISD::CTPOP, VT, Expand);
707 setOperationAction(ISD::CTTZ, VT, Expand);
708 setOperationAction(ISD::CTLZ, VT, Expand);
709 setOperationAction(ISD::ROTL, VT, Expand);
710 setOperationAction(ISD::ROTR, VT, Expand);
711 setOperationAction(ISD::BSWAP, VT, Expand);
712 setOperationAction(ISD::SETCC, VT, Expand);
713 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
714 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
715 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
716 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
717 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
718 setOperationAction(ISD::TRUNCATE, VT, Expand);
719 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
720 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
721 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
722 setOperationAction(ISD::SELECT_CC, VT, Expand);
723 for (MVT InnerVT : MVT::vector_valuetypes()) {
724 setTruncStoreAction(InnerVT, VT, Expand);
725
726 setLoadExtAction(ISD::SEXTLOAD, InnerVT, VT, Expand);
727 setLoadExtAction(ISD::ZEXTLOAD, InnerVT, VT, Expand);
728
729 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like
730 // types, we have to deal with them whether we ask for Expansion or not.
731 // Setting Expand causes its own optimisation problems though, so leave
732 // them legal.
733 if (VT.getVectorElementType() == MVT::i1)
734 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
735
736 // EXTLOAD for MVT::f16 vectors is not legal because f16 vectors are
737 // split/scalarized right now.
738 if (VT.getVectorElementType() == MVT::f16)
739 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
740 }
741 }
742
743 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
744 // with -msoft-float, disable use of MMX as well.
745 if (!Subtarget.useSoftFloat() && Subtarget.hasMMX()) {
746 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
747 // No operations on x86mmx supported, everything uses intrinsics.
748 }
749
750 if (!Subtarget.useSoftFloat() && Subtarget.hasSSE1()) {
751 addRegisterClass(MVT::v4f32, Subtarget.hasVLX() ? &X86::VR128XRegClass
752 : &X86::VR128RegClass);
753
754 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
755 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
756 setOperationAction(ISD::FCOPYSIGN, MVT::v4f32, Custom);
757 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
758 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
759 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
760 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
761 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
762 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
763 }
764
765 if (!Subtarget.useSoftFloat() && Subtarget.hasSSE2()) {
766 addRegisterClass(MVT::v2f64, Subtarget.hasVLX() ? &X86::VR128XRegClass
767 : &X86::VR128RegClass);
768
769 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
770 // registers cannot be used even for integer operations.
771 addRegisterClass(MVT::v16i8, Subtarget.hasVLX() ? &X86::VR128XRegClass
772 : &X86::VR128RegClass);
773 addRegisterClass(MVT::v8i16, Subtarget.hasVLX() ? &X86::VR128XRegClass
774 : &X86::VR128RegClass);
775 addRegisterClass(MVT::v4i32, Subtarget.hasVLX() ? &X86::VR128XRegClass
776 : &X86::VR128RegClass);
777 addRegisterClass(MVT::v2i64, Subtarget.hasVLX() ? &X86::VR128XRegClass
778 : &X86::VR128RegClass);
779
780 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
781 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
782 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
783 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
784 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
785 setOperationAction(ISD::MULHU, MVT::v16i8, Custom);
786 setOperationAction(ISD::MULHS, MVT::v16i8, Custom);
787 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
788 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
789 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
790 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
791 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
792 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Custom);
793
794 setOperationAction(ISD::SMAX, MVT::v8i16, Legal);
795 setOperationAction(ISD::UMAX, MVT::v16i8, Legal);
796 setOperationAction(ISD::SMIN, MVT::v8i16, Legal);
797 setOperationAction(ISD::UMIN, MVT::v16i8, Legal);
798
799 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
800 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
801 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
802
803 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
804 setOperationAction(ISD::SETCC, VT, Custom);
805 setOperationAction(ISD::CTPOP, VT, Custom);
806 setOperationAction(ISD::CTTZ, VT, Custom);
807 }
808
809 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32 }) {
810 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
811 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
812 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
813 setOperationAction(ISD::VSELECT, VT, Custom);
814 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
815 }
816
817 // We support custom legalizing of sext and anyext loads for specific
818 // memory vector types which we can load as a scalar (or sequence of
819 // scalars) and extend in-register to a legal 128-bit vector type. For sext
820 // loads these must work with a single scalar load.
821 for (MVT VT : MVT::integer_vector_valuetypes()) {
822 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i8, Custom);
823 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i16, Custom);
824 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v8i8, Custom);
825 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Custom);
826 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Custom);
827 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i32, Custom);
828 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i8, Custom);
829 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Custom);
830 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8i8, Custom);
831 }
832
833 for (auto VT : { MVT::v2f64, MVT::v2i64 }) {
834 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
835 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
836 setOperationAction(ISD::VSELECT, VT, Custom);
837
838 if (VT == MVT::v2i64 && !Subtarget.is64Bit())
839 continue;
840
841 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
842 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
843 }
844
845 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
846 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32 }) {
847 setOperationPromotedToType(ISD::AND, VT, MVT::v2i64);
848 setOperationPromotedToType(ISD::OR, VT, MVT::v2i64);
849 setOperationPromotedToType(ISD::XOR, VT, MVT::v2i64);
850 setOperationPromotedToType(ISD::LOAD, VT, MVT::v2i64);
851 setOperationPromotedToType(ISD::SELECT, VT, MVT::v2i64);
852 }
853
854 // Custom lower v2i64 and v2f64 selects.
855 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
856 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
857
858 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
859 setOperationAction(ISD::FP_TO_SINT, MVT::v2i32, Custom);
860
861 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
862 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
863
864 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
865 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
866 setOperationAction(ISD::UINT_TO_FP, MVT::v2i32, Custom);
867
868 // Fast v2f32 UINT_TO_FP( v2i32 ) custom conversion.
869 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
870
871 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
872 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
873
874 for (MVT VT : MVT::fp_vector_valuetypes())
875 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2f32, Legal);
876
877 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
878 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
879 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
880
881 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v2i64, Custom);
882 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v4i32, Custom);
883 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v8i16, Custom);
884
885 // In the customized shift lowering, the legal v4i32/v2i64 cases
886 // in AVX2 will be recognized.
887 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
888 setOperationAction(ISD::SRL, VT, Custom);
889 setOperationAction(ISD::SHL, VT, Custom);
890 setOperationAction(ISD::SRA, VT, Custom);
891 }
892 }
893
894 if (!Subtarget.useSoftFloat() && Subtarget.hasSSSE3()) {
895 setOperationAction(ISD::ABS, MVT::v16i8, Legal);
896 setOperationAction(ISD::ABS, MVT::v8i16, Legal);
897 setOperationAction(ISD::ABS, MVT::v4i32, Legal);
898 setOperationAction(ISD::BITREVERSE, MVT::v16i8, Custom);
899 setOperationAction(ISD::CTLZ, MVT::v16i8, Custom);
900 setOperationAction(ISD::CTLZ, MVT::v8i16, Custom);
901 setOperationAction(ISD::CTLZ, MVT::v4i32, Custom);
902 setOperationAction(ISD::CTLZ, MVT::v2i64, Custom);
903 }
904
905 if (!Subtarget.useSoftFloat() && Subtarget.hasSSE41()) {
906 for (MVT RoundedTy : {MVT::f32, MVT::f64, MVT::v4f32, MVT::v2f64}) {
907 setOperationAction(ISD::FFLOOR, RoundedTy, Legal);
908 setOperationAction(ISD::FCEIL, RoundedTy, Legal);
909 setOperationAction(ISD::FTRUNC, RoundedTy, Legal);
910 setOperationAction(ISD::FRINT, RoundedTy, Legal);
911 setOperationAction(ISD::FNEARBYINT, RoundedTy, Legal);
912 }
913
914 setOperationAction(ISD::SMAX, MVT::v16i8, Legal);
915 setOperationAction(ISD::SMAX, MVT::v4i32, Legal);
916 setOperationAction(ISD::UMAX, MVT::v8i16, Legal);
917 setOperationAction(ISD::UMAX, MVT::v4i32, Legal);
918 setOperationAction(ISD::SMIN, MVT::v16i8, Legal);
919 setOperationAction(ISD::SMIN, MVT::v4i32, Legal);
920 setOperationAction(ISD::UMIN, MVT::v8i16, Legal);
921 setOperationAction(ISD::UMIN, MVT::v4i32, Legal);
922
923 // FIXME: Do we need to handle scalar-to-vector here?
924 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
925
926 // We directly match byte blends in the backend as they match the VSELECT
927 // condition form.
928 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
929
930 // SSE41 brings specific instructions for doing vector sign extend even in
931 // cases where we don't have SRA.
932 for (auto VT : { MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
933 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Legal);
934 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, VT, Legal);
935 }
936
937 for (MVT VT : MVT::integer_vector_valuetypes()) {
938 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i8, Custom);
939 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i16, Custom);
940 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i32, Custom);
941 }
942
943 // SSE41 also has vector sign/zero extending loads, PMOV[SZ]X
944 for (auto LoadExtOp : { ISD::SEXTLOAD, ISD::ZEXTLOAD }) {
945 setLoadExtAction(LoadExtOp, MVT::v8i16, MVT::v8i8, Legal);
946 setLoadExtAction(LoadExtOp, MVT::v4i32, MVT::v4i8, Legal);
947 setLoadExtAction(LoadExtOp, MVT::v2i32, MVT::v2i8, Legal);
948 setLoadExtAction(LoadExtOp, MVT::v2i64, MVT::v2i8, Legal);
949 setLoadExtAction(LoadExtOp, MVT::v4i32, MVT::v4i16, Legal);
950 setLoadExtAction(LoadExtOp, MVT::v2i64, MVT::v2i16, Legal);
951 setLoadExtAction(LoadExtOp, MVT::v2i64, MVT::v2i32, Legal);
952 }
953
954 // i8 vectors are custom because the source register and source
955 // source memory operand types are not the same width.
956 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
957 }
958
959 if (!Subtarget.useSoftFloat() && Subtarget.hasXOP()) {
960 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64,
961 MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 })
962 setOperationAction(ISD::ROTL, VT, Custom);
963
964 // XOP can efficiently perform BITREVERSE with VPPERM.
965 for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 })
966 setOperationAction(ISD::BITREVERSE, VT, Custom);
967
968 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64,
969 MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 })
970 setOperationAction(ISD::BITREVERSE, VT, Custom);
971 }
972
973 if (!Subtarget.useSoftFloat() && Subtarget.hasFp256()) {
974 bool HasInt256 = Subtarget.hasInt256();
975
976 addRegisterClass(MVT::v32i8, Subtarget.hasVLX() ? &X86::VR256XRegClass
977 : &X86::VR256RegClass);
978 addRegisterClass(MVT::v16i16, Subtarget.hasVLX() ? &X86::VR256XRegClass
979 : &X86::VR256RegClass);
980 addRegisterClass(MVT::v8i32, Subtarget.hasVLX() ? &X86::VR256XRegClass
981 : &X86::VR256RegClass);
982 addRegisterClass(MVT::v8f32, Subtarget.hasVLX() ? &X86::VR256XRegClass
983 : &X86::VR256RegClass);
984 addRegisterClass(MVT::v4i64, Subtarget.hasVLX() ? &X86::VR256XRegClass
985 : &X86::VR256RegClass);
986 addRegisterClass(MVT::v4f64, Subtarget.hasVLX() ? &X86::VR256XRegClass
987 : &X86::VR256RegClass);
988
989 for (auto VT : { MVT::v8f32, MVT::v4f64 }) {
990 setOperationAction(ISD::FFLOOR, VT, Legal);
991 setOperationAction(ISD::FCEIL, VT, Legal);
992 setOperationAction(ISD::FTRUNC, VT, Legal);
993 setOperationAction(ISD::FRINT, VT, Legal);
994 setOperationAction(ISD::FNEARBYINT, VT, Legal);
995 setOperationAction(ISD::FNEG, VT, Custom);
996 setOperationAction(ISD::FABS, VT, Custom);
997 setOperationAction(ISD::FCOPYSIGN, VT, Custom);
998 }
999
1000 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1001 // even though v8i16 is a legal type.
1002 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1003 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1004 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1005
1006 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1007 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1008 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1009
1010 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1011 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1012
1013 for (MVT VT : MVT::fp_vector_valuetypes())
1014 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4f32, Legal);
1015
1016 // In the customized shift lowering, the legal v8i32/v4i64 cases
1017 // in AVX2 will be recognized.
1018 for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 }) {
1019 setOperationAction(ISD::SRL, VT, Custom);
1020 setOperationAction(ISD::SHL, VT, Custom);
1021 setOperationAction(ISD::SRA, VT, Custom);
1022 }
1023
1024 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1025 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1026 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1027
1028 for (auto VT : { MVT::v16i16, MVT::v8i32, MVT::v4i64 }) {
1029 setOperationAction(ISD::SIGN_EXTEND, VT, Custom);
1030 setOperationAction(ISD::ZERO_EXTEND, VT, Custom);
1031 setOperationAction(ISD::ANY_EXTEND, VT, Custom);
1032 }
1033
1034 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1035 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1036 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1037 setOperationAction(ISD::BITREVERSE, MVT::v32i8, Custom);
1038
1039 for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 }) {
1040 setOperationAction(ISD::SETCC, VT, Custom);
1041 setOperationAction(ISD::CTPOP, VT, Custom);
1042 setOperationAction(ISD::CTTZ, VT, Custom);
1043 setOperationAction(ISD::CTLZ, VT, Custom);
1044 }
1045
1046 if (Subtarget.hasAnyFMA()) {
1047 for (auto VT : { MVT::f32, MVT::f64, MVT::v4f32, MVT::v8f32,
1048 MVT::v2f64, MVT::v4f64 })
1049 setOperationAction(ISD::FMA, VT, Legal);
1050 }
1051
1052 for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 }) {
1053 setOperationAction(ISD::ADD, VT, HasInt256 ? Legal : Custom);
1054 setOperationAction(ISD::SUB, VT, HasInt256 ? Legal : Custom);
1055 }
1056
1057 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1058 setOperationAction(ISD::MUL, MVT::v8i32, HasInt256 ? Legal : Custom);
1059 setOperationAction(ISD::MUL, MVT::v16i16, HasInt256 ? Legal : Custom);
1060 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1061
1062 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1063 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1064
1065 setOperationAction(ISD::MULHU, MVT::v16i16, HasInt256 ? Legal : Custom);
1066 setOperationAction(ISD::MULHS, MVT::v16i16, HasInt256 ? Legal : Custom);
1067 setOperationAction(ISD::MULHU, MVT::v32i8, Custom);
1068 setOperationAction(ISD::MULHS, MVT::v32i8, Custom);
1069
1070 for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32 }) {
1071 setOperationAction(ISD::ABS, VT, HasInt256 ? Legal : Custom);
1072 setOperationAction(ISD::SMAX, VT, HasInt256 ? Legal : Custom);
1073 setOperationAction(ISD::UMAX, VT, HasInt256 ? Legal : Custom);
1074 setOperationAction(ISD::SMIN, VT, HasInt256 ? Legal : Custom);
1075 setOperationAction(ISD::UMIN, VT, HasInt256 ? Legal : Custom);
1076 }
1077
1078 if (HasInt256) {
1079 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v4i64, Custom);
1080 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v8i32, Custom);
1081 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v16i16, Custom);
1082
1083 // The custom lowering for UINT_TO_FP for v8i32 becomes interesting
1084 // when we have a 256bit-wide blend with immediate.
1085 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Custom);
1086
1087 // AVX2 also has wider vector sign/zero extending loads, VPMOV[SZ]X
1088 for (auto LoadExtOp : { ISD::SEXTLOAD, ISD::ZEXTLOAD }) {
1089 setLoadExtAction(LoadExtOp, MVT::v16i16, MVT::v16i8, Legal);
1090 setLoadExtAction(LoadExtOp, MVT::v8i32, MVT::v8i8, Legal);
1091 setLoadExtAction(LoadExtOp, MVT::v4i64, MVT::v4i8, Legal);
1092 setLoadExtAction(LoadExtOp, MVT::v8i32, MVT::v8i16, Legal);
1093 setLoadExtAction(LoadExtOp, MVT::v4i64, MVT::v4i16, Legal);
1094 setLoadExtAction(LoadExtOp, MVT::v4i64, MVT::v4i32, Legal);
1095 }
1096 }
1097
1098 for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64,
1099 MVT::v4f32, MVT::v8f32, MVT::v2f64, MVT::v4f64 }) {
1100 setOperationAction(ISD::MLOAD, VT, Legal);
1101 setOperationAction(ISD::MSTORE, VT, Legal);
1102 }
1103
1104 // Extract subvector is special because the value type
1105 // (result) is 128-bit but the source is 256-bit wide.
1106 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64,
1107 MVT::v4f32, MVT::v2f64 }) {
1108 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1109 }
1110
1111 // Custom lower several nodes for 256-bit types.
1112 for (MVT VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64,
1113 MVT::v8f32, MVT::v4f64 }) {
1114 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1115 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1116 setOperationAction(ISD::VSELECT, VT, Custom);
1117 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1118 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1119 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1120 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Legal);
1121 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1122 }
1123
1124 if (HasInt256)
1125 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1126
1127 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1128 for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32 }) {
1129 setOperationPromotedToType(ISD::AND, VT, MVT::v4i64);
1130 setOperationPromotedToType(ISD::OR, VT, MVT::v4i64);
1131 setOperationPromotedToType(ISD::XOR, VT, MVT::v4i64);
1132 setOperationPromotedToType(ISD::LOAD, VT, MVT::v4i64);
1133 setOperationPromotedToType(ISD::SELECT, VT, MVT::v4i64);
1134 }
1135 }
1136
1137 if (!Subtarget.useSoftFloat() && Subtarget.hasAVX512()) {
1138 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1139 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1140 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1141 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1142
1143 addRegisterClass(MVT::v1i1, &X86::VK1RegClass);
1144 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1145 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1146
1147 for (MVT VT : MVT::fp_vector_valuetypes())
1148 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8f32, Legal);
1149
1150 for (auto ExtType : {ISD::ZEXTLOAD, ISD::SEXTLOAD}) {
1151 setLoadExtAction(ExtType, MVT::v16i32, MVT::v16i8, Legal);
1152 setLoadExtAction(ExtType, MVT::v16i32, MVT::v16i16, Legal);
1153 setLoadExtAction(ExtType, MVT::v8i64, MVT::v8i8, Legal);
1154 setLoadExtAction(ExtType, MVT::v8i64, MVT::v8i16, Legal);
1155 setLoadExtAction(ExtType, MVT::v8i64, MVT::v8i32, Legal);
1156 }
1157
1158 for (MVT VT : {MVT::v2i64, MVT::v4i32, MVT::v8i32, MVT::v4i64, MVT::v8i16,
1159 MVT::v16i8, MVT::v16i16, MVT::v32i8, MVT::v16i32,
1160 MVT::v8i64, MVT::v32i16, MVT::v64i8}) {
1161 MVT MaskVT = MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
1162 setLoadExtAction(ISD::SEXTLOAD, VT, MaskVT, Custom);
1163 setLoadExtAction(ISD::ZEXTLOAD, VT, MaskVT, Custom);
1164 setLoadExtAction(ISD::EXTLOAD, VT, MaskVT, Custom);
1165 setTruncStoreAction(VT, MaskVT, Custom);
1166 }
1167
1168 for (MVT VT : { MVT::v16f32, MVT::v8f64 }) {
1169 setOperationAction(ISD::FNEG, VT, Custom);
1170 setOperationAction(ISD::FABS, VT, Custom);
1171 setOperationAction(ISD::FMA, VT, Legal);
1172 setOperationAction(ISD::FCOPYSIGN, VT, Custom);
1173 }
1174
1175 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1176 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1177 setOperationAction(ISD::FP_TO_UINT, MVT::v16i8, Legal);
1178 setOperationAction(ISD::FP_TO_UINT, MVT::v16i16, Legal);
1179 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1180 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1181 setOperationAction(ISD::FP_TO_UINT, MVT::v2i32, Custom);
1182 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1183 setOperationAction(ISD::SINT_TO_FP, MVT::v8i1, Custom);
1184 setOperationAction(ISD::SINT_TO_FP, MVT::v16i1, Custom);
1185 setOperationAction(ISD::SINT_TO_FP, MVT::v16i8, Promote);
1186 setOperationAction(ISD::SINT_TO_FP, MVT::v16i16, Promote);
1187 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1188 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1189 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1190 setOperationAction(ISD::UINT_TO_FP, MVT::v16i8, Custom);
1191 setOperationAction(ISD::UINT_TO_FP, MVT::v16i16, Custom);
1192 setOperationAction(ISD::SINT_TO_FP, MVT::v16i1, Custom);
1193 setOperationAction(ISD::UINT_TO_FP, MVT::v16i1, Custom);
1194 setOperationAction(ISD::SINT_TO_FP, MVT::v8i1, Custom);
1195 setOperationAction(ISD::UINT_TO_FP, MVT::v8i1, Custom);
1196 setOperationAction(ISD::SINT_TO_FP, MVT::v4i1, Custom);
1197 setOperationAction(ISD::UINT_TO_FP, MVT::v4i1, Custom);
1198 setOperationAction(ISD::SINT_TO_FP, MVT::v2i1, Custom);
1199 setOperationAction(ISD::UINT_TO_FP, MVT::v2i1, Custom);
1200 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1201 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1202
1203 setTruncStoreAction(MVT::v8i64, MVT::v8i8, Legal);
1204 setTruncStoreAction(MVT::v8i64, MVT::v8i16, Legal);
1205 setTruncStoreAction(MVT::v8i64, MVT::v8i32, Legal);
1206 setTruncStoreAction(MVT::v16i32, MVT::v16i8, Legal);
1207 setTruncStoreAction(MVT::v16i32, MVT::v16i16, Legal);
1208 if (Subtarget.hasVLX()){
1209 setTruncStoreAction(MVT::v4i64, MVT::v4i8, Legal);
1210 setTruncStoreAction(MVT::v4i64, MVT::v4i16, Legal);
1211 setTruncStoreAction(MVT::v4i64, MVT::v4i32, Legal);
1212 setTruncStoreAction(MVT::v8i32, MVT::v8i8, Legal);
1213 setTruncStoreAction(MVT::v8i32, MVT::v8i16, Legal);
1214
1215 setTruncStoreAction(MVT::v2i64, MVT::v2i8, Legal);
1216 setTruncStoreAction(MVT::v2i64, MVT::v2i16, Legal);
1217 setTruncStoreAction(MVT::v2i64, MVT::v2i32, Legal);
1218 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Legal);
1219 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Legal);
1220 } else {
1221 for (auto VT : {MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64,
1222 MVT::v4f32, MVT::v8f32, MVT::v2f64, MVT::v4f64}) {
1223 setOperationAction(ISD::MLOAD, VT, Custom);
1224 setOperationAction(ISD::MSTORE, VT, Custom);
1225 }
1226 }
1227
1228 if (Subtarget.hasDQI()) {
1229 for (auto VT : { MVT::v2i64, MVT::v4i64, MVT::v8i64 }) {
1230 setOperationAction(ISD::SINT_TO_FP, VT, Legal);
1231 setOperationAction(ISD::UINT_TO_FP, VT, Legal);
1232 setOperationAction(ISD::FP_TO_SINT, VT, Legal);
1233 setOperationAction(ISD::FP_TO_UINT, VT, Legal);
1234 }
1235 if (Subtarget.hasVLX()) {
1236 // Fast v2f32 SINT_TO_FP( v2i32 ) custom conversion.
1237 setOperationAction(ISD::SINT_TO_FP, MVT::v2f32, Custom);
1238 setOperationAction(ISD::FP_TO_SINT, MVT::v2f32, Custom);
1239 setOperationAction(ISD::FP_TO_UINT, MVT::v2f32, Custom);
1240 }
1241 }
1242 if (Subtarget.hasVLX()) {
1243 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1244 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1245 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1246 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1247 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1248 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1249 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1250 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i32, Custom);
1251 setOperationAction(ISD::ZERO_EXTEND, MVT::v2i64, Custom);
1252 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i32, Custom);
1253 setOperationAction(ISD::SIGN_EXTEND, MVT::v2i64, Custom);
1254 }
1255
1256 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1257 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1258 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1259 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1260 setOperationAction(ISD::ANY_EXTEND, MVT::v16i32, Custom);
1261 setOperationAction(ISD::ANY_EXTEND, MVT::v8i64, Custom);
1262 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1263 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1264 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1265 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1266 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1267
1268 for (auto VT : { MVT::v16f32, MVT::v8f64 }) {
1269 setOperationAction(ISD::FFLOOR, VT, Legal);
1270 setOperationAction(ISD::FCEIL, VT, Legal);
1271 setOperationAction(ISD::FTRUNC, VT, Legal);
1272 setOperationAction(ISD::FRINT, VT, Legal);
1273 setOperationAction(ISD::FNEARBYINT, VT, Legal);
1274 }
1275
1276 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v8i64, Custom);
1277 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v16i32, Custom);
1278
1279 // Without BWI we need to use custom lowering to handle MVT::v64i8 input.
1280 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v64i8, Custom);
1281 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, MVT::v64i8, Custom);
1282
1283 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1284 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1285 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1286 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1287 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Custom);
1288
1289 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1290 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1291
1292 setOperationAction(ISD::UMUL_LOHI, MVT::v16i32, Custom);
1293 setOperationAction(ISD::SMUL_LOHI, MVT::v16i32, Custom);
1294
1295 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v1i1, Custom);
1296 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v16i1, Custom);
1297 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i1, Custom);
1298 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1299 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1300 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1301
1302
1303 // NonVLX sub-targets extend 128/256 vectors to use the 512 version.
1304 setOperationAction(ISD::ABS, MVT::v4i64, Legal);
1305 setOperationAction(ISD::ABS, MVT::v2i64, Legal);
1306
1307 for (auto VT : { MVT::v8i1, MVT::v16i1 }) {
1308 setOperationAction(ISD::ADD, VT, Custom);
1309 setOperationAction(ISD::SUB, VT, Custom);
1310 setOperationAction(ISD::MUL, VT, Custom);
1311 setOperationAction(ISD::SETCC, VT, Custom);
1312 setOperationAction(ISD::SELECT, VT, Custom);
1313 setOperationAction(ISD::TRUNCATE, VT, Custom);
1314
1315 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1316 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1317 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1318 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1319 setOperationAction(ISD::VSELECT, VT, Expand);
1320 }
1321
1322 for (auto VT : { MVT::v16i32, MVT::v8i64 }) {
1323 setOperationAction(ISD::SMAX, VT, Legal);
1324 setOperationAction(ISD::UMAX, VT, Legal);
1325 setOperationAction(ISD::SMIN, VT, Legal);
1326 setOperationAction(ISD::UMIN, VT, Legal);
1327 setOperationAction(ISD::ABS, VT, Legal);
1328 setOperationAction(ISD::SRL, VT, Custom);
1329 setOperationAction(ISD::SHL, VT, Custom);
1330 setOperationAction(ISD::SRA, VT, Custom);
1331 setOperationAction(ISD::CTPOP, VT, Custom);
1332 setOperationAction(ISD::CTTZ, VT, Custom);
1333 }
1334
1335 // NonVLX sub-targets extend 128/256 vectors to use the 512 version.
1336 for (auto VT : {MVT::v4i32, MVT::v8i32, MVT::v16i32, MVT::v2i64, MVT::v4i64,
1337 MVT::v8i64}) {
1338 setOperationAction(ISD::ROTL, VT, Custom);
1339 setOperationAction(ISD::ROTR, VT, Custom);
1340 }
1341
1342 // Need to promote to 64-bit even though we have 32-bit masked instructions
1343 // because the IR optimizers rearrange bitcasts around logic ops leaving
1344 // too many variations to handle if we don't promote them.
1345 setOperationPromotedToType(ISD::AND, MVT::v16i32, MVT::v8i64);
1346 setOperationPromotedToType(ISD::OR, MVT::v16i32, MVT::v8i64);
1347 setOperationPromotedToType(ISD::XOR, MVT::v16i32, MVT::v8i64);
1348
1349 if (Subtarget.hasCDI()) {
1350 // NonVLX sub-targets extend 128/256 vectors to use the 512 version.
1351 for (auto VT : {MVT::v4i32, MVT::v8i32, MVT::v16i32, MVT::v2i64,
1352 MVT::v4i64, MVT::v8i64}) {
1353 setOperationAction(ISD::CTLZ, VT, Legal);
1354 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Custom);
1355 }
1356 } // Subtarget.hasCDI()
1357
1358 if (Subtarget.hasDQI()) {
1359 // NonVLX sub-targets extend 128/256 vectors to use the 512 version.
1360 setOperationAction(ISD::MUL, MVT::v2i64, Legal);
1361 setOperationAction(ISD::MUL, MVT::v4i64, Legal);
1362 setOperationAction(ISD::MUL, MVT::v8i64, Legal);
1363 }
1364
1365 if (Subtarget.hasVPOPCNTDQ()) {
1366 // VPOPCNTDQ sub-targets extend 128/256 vectors to use the avx512
1367 // version of popcntd/q.
1368 for (auto VT : {MVT::v16i32, MVT::v8i64, MVT::v8i32, MVT::v4i64,
1369 MVT::v4i32, MVT::v2i64})
1370 setOperationAction(ISD::CTPOP, VT, Legal);
1371 }
1372
1373 // Custom legalize 2x32 to get a little better code.
1374 if (Subtarget.hasVLX()) {
1375 setOperationAction(ISD::MGATHER, MVT::v2f32, Custom);
1376 }
1377
1378 // Custom lower several nodes.
1379 for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64,
1380 MVT::v4f32, MVT::v8f32, MVT::v2f64, MVT::v4f64 }) {
1381 setOperationAction(ISD::MGATHER, VT, Custom);
1382 setOperationAction(ISD::MSCATTER, VT, Custom);
1383 }
1384
1385 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v1i1, Legal);
1386
1387 // Extract subvector is special because the value type
1388 // (result) is 256-bit but the source is 512-bit wide.
1389 // 128-bit was made Legal under AVX1.
1390 for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64,
1391 MVT::v8f32, MVT::v4f64 })
1392 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1393 for (auto VT : { MVT::v2i1, MVT::v4i1, MVT::v8i1,
1394 MVT::v16i1, MVT::v32i1, MVT::v64i1 })
1395 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1396
1397 for (auto VT : { MVT::v16i32, MVT::v8i64, MVT::v16f32, MVT::v8f64 }) {
1398 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1399 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1400 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1401 setOperationAction(ISD::VSELECT, VT, Custom);
1402 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1403 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1404 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Legal);
1405 setOperationAction(ISD::MLOAD, VT, Legal);
1406 setOperationAction(ISD::MSTORE, VT, Legal);
1407 setOperationAction(ISD::MGATHER, VT, Legal);
1408 setOperationAction(ISD::MSCATTER, VT, Custom);
1409 }
1410 for (auto VT : { MVT::v64i8, MVT::v32i16, MVT::v16i32 }) {
1411 setOperationPromotedToType(ISD::LOAD, VT, MVT::v8i64);
1412 setOperationPromotedToType(ISD::SELECT, VT, MVT::v8i64);
1413 }
1414 }// has AVX-512
1415
1416 if (!Subtarget.useSoftFloat() && Subtarget.hasBWI()) {
1417 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1418 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1419
1420 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1421 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1422
1423 setOperationAction(ISD::ADD, MVT::v32i1, Custom);
1424 setOperationAction(ISD::ADD, MVT::v64i1, Custom);
1425 setOperationAction(ISD::SUB, MVT::v32i1, Custom);
1426 setOperationAction(ISD::SUB, MVT::v64i1, Custom);
1427 setOperationAction(ISD::MUL, MVT::v32i1, Custom);
1428 setOperationAction(ISD::MUL, MVT::v64i1, Custom);
1429
1430 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1431 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1432 setOperationAction(ISD::MUL, MVT::v32i16, Legal);
1433 setOperationAction(ISD::MUL, MVT::v64i8, Custom);
1434 setOperationAction(ISD::MULHS, MVT::v32i16, Legal);
1435 setOperationAction(ISD::MULHU, MVT::v32i16, Legal);
1436 setOperationAction(ISD::MULHS, MVT::v64i8, Custom);
1437 setOperationAction(ISD::MULHU, MVT::v64i8, Custom);
1438 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i1, Custom);
1439 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i1, Custom);
1440 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i16, Custom);
1441 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i8, Custom);
1442 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i1, Custom);
1443 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i1, Custom);
1444 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i16, Legal);
1445 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i8, Legal);
1446 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v32i16, Custom);
1447 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v64i8, Custom);
1448 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v32i1, Custom);
1449 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v64i1, Custom);
1450 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v32i16, Custom);
1451 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v64i8, Custom);
1452 setOperationAction(ISD::SELECT, MVT::v32i1, Custom);
1453 setOperationAction(ISD::SELECT, MVT::v64i1, Custom);
1454 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i8, Custom);
1455 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i8, Custom);
1456 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i16, Custom);
1457 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i16, Custom);
1458 setOperationAction(ISD::ANY_EXTEND, MVT::v32i16, Custom);
1459 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v32i16, Custom);
1460 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v64i8, Custom);
1461 setOperationAction(ISD::SIGN_EXTEND, MVT::v64i8, Custom);
1462 setOperationAction(ISD::ZERO_EXTEND, MVT::v64i8, Custom);
1463 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v32i1, Custom);
1464 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v64i1, Custom);
1465 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v32i16, Custom);
1466 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v64i8, Custom);
1467 setOperationAction(ISD::TRUNCATE, MVT::v32i1, Custom);
1468 setOperationAction(ISD::TRUNCATE, MVT::v64i1, Custom);
1469 setOperationAction(ISD::TRUNCATE, MVT::v32i8, Custom);
1470 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v32i1, Custom);
1471 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v64i1, Custom);
1472 setOperationAction(ISD::BUILD_VECTOR, MVT::v32i1, Custom);
1473 setOperationAction(ISD::BUILD_VECTOR, MVT::v64i1, Custom);
1474 setOperationAction(ISD::VSELECT, MVT::v32i1, Expand);
1475 setOperationAction(ISD::VSELECT, MVT::v64i1, Expand);
1476 setOperationAction(ISD::BITREVERSE, MVT::v64i8, Custom);
1477
1478 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v32i16, Custom);
1479
1480 setTruncStoreAction(MVT::v32i16, MVT::v32i8, Legal);
1481 if (Subtarget.hasVLX()) {
1482 setTruncStoreAction(MVT::v16i16, MVT::v16i8, Legal);
1483 setTruncStoreAction(MVT::v8i16, MVT::v8i8, Legal);
1484 }
1485
1486 LegalizeAction Action = Subtarget.hasVLX() ? Legal : Custom;
1487 for (auto VT : { MVT::v32i8, MVT::v16i8, MVT::v16i16, MVT::v8i16 }) {
1488 setOperationAction(ISD::MLOAD, VT, Action);
1489 setOperationAction(ISD::MSTORE, VT, Action);
1490 }
1491
1492 if (Subtarget.hasCDI()) {
1493 setOperationAction(ISD::CTLZ, MVT::v32i16, Custom);
1494 setOperationAction(ISD::CTLZ, MVT::v64i8, Custom);
1495 }
1496
1497 for (auto VT : { MVT::v64i8, MVT::v32i16 }) {
1498 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1499 setOperationAction(ISD::VSELECT, VT, Custom);
1500 setOperationAction(ISD::ABS, VT, Legal);
1501 setOperationAction(ISD::SRL, VT, Custom);
1502 setOperationAction(ISD::SHL, VT, Custom);
1503 setOperationAction(ISD::SRA, VT, Custom);
1504 setOperationAction(ISD::MLOAD, VT, Legal);
1505 setOperationAction(ISD::MSTORE, VT, Legal);
1506 setOperationAction(ISD::CTPOP, VT, Custom);
1507 setOperationAction(ISD::CTTZ, VT, Custom);
1508 setOperationAction(ISD::SMAX, VT, Legal);
1509 setOperationAction(ISD::UMAX, VT, Legal);
1510 setOperationAction(ISD::SMIN, VT, Legal);
1511 setOperationAction(ISD::UMIN, VT, Legal);
1512
1513 setOperationPromotedToType(ISD::AND, VT, MVT::v8i64);
1514 setOperationPromotedToType(ISD::OR, VT, MVT::v8i64);
1515 setOperationPromotedToType(ISD::XOR, VT, MVT::v8i64);
1516 }
1517
1518 for (auto ExtType : {ISD::ZEXTLOAD, ISD::SEXTLOAD}) {
1519 setLoadExtAction(ExtType, MVT::v32i16, MVT::v32i8, Legal);
1520 }
1521 }
1522
1523 if (!Subtarget.useSoftFloat() && Subtarget.hasVLX()) {
1524 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1525 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1526
1527 for (auto VT : { MVT::v2i1, MVT::v4i1 }) {
1528 setOperationAction(ISD::ADD, VT, Custom);
1529 setOperationAction(ISD::SUB, VT, Custom);
1530 setOperationAction(ISD::MUL, VT, Custom);
1531 setOperationAction(ISD::VSELECT, VT, Expand);
1532
1533 setOperationAction(ISD::TRUNCATE, VT, Custom);
1534 setOperationAction(ISD::SETCC, VT, Custom);
1535 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1536 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1537 setOperationAction(ISD::SELECT, VT, Custom);
1538 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1539 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1540 }
1541
1542 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1543 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i1, Custom);
1544 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Custom);
1545 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v4i1, Custom);
1546
1547 for (auto VT : { MVT::v2i64, MVT::v4i64 }) {
1548 setOperationAction(ISD::SMAX, VT, Legal);
1549 setOperationAction(ISD::UMAX, VT, Legal);
1550 setOperationAction(ISD::SMIN, VT, Legal);
1551 setOperationAction(ISD::UMIN, VT, Legal);
1552 }
1553 }
1554
1555 // We want to custom lower some of our intrinsics.
1556 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1557 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1558 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1559 if (!Subtarget.is64Bit()) {
1560 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1561 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom);
1562 }
1563
1564 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1565 // handle type legalization for these operations here.
1566 //
1567 // FIXME: We really should do custom legalization for addition and
1568 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1569 // than generic legalization for 64-bit multiplication-with-overflow, though.
1570 for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
1571 if (VT == MVT::i64 && !Subtarget.is64Bit())
1572 continue;
1573 // Add/Sub/Mul with overflow operations are custom lowered.
1574 setOperationAction(ISD::SADDO, VT, Custom);
1575 setOperationAction(ISD::UADDO, VT, Custom);
1576 setOperationAction(ISD::SSUBO, VT, Custom);
1577 setOperationAction(ISD::USUBO, VT, Custom);
1578 setOperationAction(ISD::SMULO, VT, Custom);
1579 setOperationAction(ISD::UMULO, VT, Custom);
1580
1581 // Support carry in as value rather than glue.
1582 setOperationAction(ISD::ADDCARRY, VT, Custom);
1583 setOperationAction(ISD::SUBCARRY, VT, Custom);
1584 setOperationAction(ISD::SETCCCARRY, VT, Custom);
1585 }
1586
1587 if (!Subtarget.is64Bit()) {
1588 // These libcalls are not available in 32-bit.
1589 setLibcallName(RTLIB::SHL_I128, nullptr);
1590 setLibcallName(RTLIB::SRL_I128, nullptr);
1591 setLibcallName(RTLIB::SRA_I128, nullptr);
1592 setLibcallName(RTLIB::MUL_I128, nullptr);
1593 }
1594
1595 // Combine sin / cos into one node or libcall if possible.
1596 if (Subtarget.hasSinCos()) {
1597 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1598 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1599 if (Subtarget.isTargetDarwin()) {
1600 // For MacOSX, we don't want the normal expansion of a libcall to sincos.
1601 // We want to issue a libcall to __sincos_stret to avoid memory traffic.
1602 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1603 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1604 }
1605 }
1606
1607 if (Subtarget.isTargetWin64()) {
1608 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1609 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1610 setOperationAction(ISD::SREM, MVT::i128, Custom);
1611 setOperationAction(ISD::UREM, MVT::i128, Custom);
1612 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1613 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1614 }
1615
1616 // On 32 bit MSVC, `fmodf(f32)` is not defined - only `fmod(f64)`
1617 // is. We should promote the value to 64-bits to solve this.
1618 // This is what the CRT headers do - `fmodf` is an inline header
1619 // function casting to f64 and calling `fmod`.
1620 if (Subtarget.is32Bit() && (Subtarget.isTargetKnownWindowsMSVC() ||
1621 Subtarget.isTargetWindowsItanium()))
1622 for (ISD::NodeType Op :
1623 {ISD::FCEIL, ISD::FCOS, ISD::FEXP, ISD::FFLOOR, ISD::FREM, ISD::FLOG,
1624 ISD::FLOG10, ISD::FPOW, ISD::FSIN})
1625 if (isOperationExpand(Op, MVT::f32))
1626 setOperationAction(Op, MVT::f32, Promote);
1627
1628 // We have target-specific dag combine patterns for the following nodes:
1629 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1630 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1631 setTargetDAGCombine(ISD::INSERT_SUBVECTOR);
1632 setTargetDAGCombine(ISD::EXTRACT_SUBVECTOR);
1633 setTargetDAGCombine(ISD::BITCAST);
1634 setTargetDAGCombine(ISD::VSELECT);
1635 setTargetDAGCombine(ISD::SELECT);
1636 setTargetDAGCombine(ISD::SHL);
1637 setTargetDAGCombine(ISD::SRA);
1638 setTargetDAGCombine(ISD::SRL);
1639 setTargetDAGCombine(ISD::OR);
1640 setTargetDAGCombine(ISD::AND);
1641 setTargetDAGCombine(ISD::ADD);
1642 setTargetDAGCombine(ISD::FADD);
1643 setTargetDAGCombine(ISD::FSUB);
1644 setTargetDAGCombine(ISD::FNEG);
1645 setTargetDAGCombine(ISD::FMA);
1646 setTargetDAGCombine(ISD::FMINNUM);
1647 setTargetDAGCombine(ISD::FMAXNUM);
1648 setTargetDAGCombine(ISD::SUB);
1649 setTargetDAGCombine(ISD::LOAD);
1650 setTargetDAGCombine(ISD::MLOAD);
1651 setTargetDAGCombine(ISD::STORE);
1652 setTargetDAGCombine(ISD::MSTORE);
1653 setTargetDAGCombine(ISD::TRUNCATE);
1654 setTargetDAGCombine(ISD::ZERO_EXTEND);
1655 setTargetDAGCombine(ISD::ANY_EXTEND);
1656 setTargetDAGCombine(ISD::SIGN_EXTEND);
1657 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1658 setTargetDAGCombine(ISD::SIGN_EXTEND_VECTOR_INREG);
1659 setTargetDAGCombine(ISD::ZERO_EXTEND_VECTOR_INREG);
1660 setTargetDAGCombine(ISD::SINT_TO_FP);
1661 setTargetDAGCombine(ISD::UINT_TO_FP);
1662 setTargetDAGCombine(ISD::SETCC);
1663 setTargetDAGCombine(ISD::MUL);
1664 setTargetDAGCombine(ISD::XOR);
1665 setTargetDAGCombine(ISD::MSCATTER);
1666 setTargetDAGCombine(ISD::MGATHER);
1667
1668 computeRegisterProperties(Subtarget.getRegisterInfo());
1669
1670 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1671 MaxStoresPerMemsetOptSize = 8;
1672 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1673 MaxStoresPerMemcpyOptSize = 4;
1674 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1675 MaxStoresPerMemmoveOptSize = 4;
1676
1677 // TODO: These control memcmp expansion in CGP and could be raised higher, but
1678 // that needs to benchmarked and balanced with the potential use of vector
1679 // load/store types (PR33329, PR33914).
1680 MaxLoadsPerMemcmp = 2;
1681 MaxLoadsPerMemcmpOptSize = 2;
1682
1683 // Set loop alignment to 2^ExperimentalPrefLoopAlignment bytes (default: 2^4).
1684 setPrefLoopAlignment(ExperimentalPrefLoopAlignment);
1685
1686 // An out-of-order CPU can speculatively execute past a predictable branch,
1687 // but a conditional move could be stalled by an expensive earlier operation.
1688 PredictableSelectIsExpensive = Subtarget.getSchedModel().isOutOfOrder();
1689 EnableExtLdPromotion = true;
1690 setPrefFunctionAlignment(4); // 2^4 bytes.
1691
1692 verifyIntrinsicTables();
1693}
1694
1695// This has so far only been implemented for 64-bit MachO.
1696bool X86TargetLowering::useLoadStackGuardNode() const {
1697 return Subtarget.isTargetMachO() && Subtarget.is64Bit();
1698}
1699
1700TargetLoweringBase::LegalizeTypeAction
1701X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1702 if (ExperimentalVectorWideningLegalization &&
1703 VT.getVectorNumElements() != 1 &&
1704 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1705 return TypeWidenVector;
1706
1707 return TargetLoweringBase::getPreferredVectorAction(VT);
1708}
1709
1710EVT X86TargetLowering::getSetCCResultType(const DataLayout &DL,
1711 LLVMContext& Context,
1712 EVT VT) const {
1713 if (!VT.isVector())
1714 return MVT::i8;
1715
1716 if (VT.isSimple()) {
1717 MVT VVT = VT.getSimpleVT();
1718 const unsigned NumElts = VVT.getVectorNumElements();
1719 MVT EltVT = VVT.getVectorElementType();
1720 if (VVT.is512BitVector()) {
1721 if (Subtarget.hasAVX512())
1722 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1723 EltVT == MVT::f32 || EltVT == MVT::f64)
1724 switch(NumElts) {
1725 case 8: return MVT::v8i1;
1726 case 16: return MVT::v16i1;
1727 }
1728 if (Subtarget.hasBWI())
1729 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1730 switch(NumElts) {
1731 case 32: return MVT::v32i1;
1732 case 64: return MVT::v64i1;
1733 }
1734 }
1735
1736 if (Subtarget.hasBWI() && Subtarget.hasVLX())
1737 return MVT::getVectorVT(MVT::i1, NumElts);
1738
1739 if (!isTypeLegal(VT) && getTypeAction(Context, VT) == TypePromoteInteger) {
1740 EVT LegalVT = getTypeToTransformTo(Context, VT);
1741 EltVT = LegalVT.getVectorElementType().getSimpleVT();
1742 }
1743
1744 if (Subtarget.hasVLX() && EltVT.getSizeInBits() >= 32)
1745 switch(NumElts) {
1746 case 2: return MVT::v2i1;
1747 case 4: return MVT::v4i1;
1748 case 8: return MVT::v8i1;
1749 }
1750 }
1751
1752 return VT.changeVectorElementTypeToInteger();
1753}
1754
1755/// Helper for getByValTypeAlignment to determine
1756/// the desired ByVal argument alignment.
1757static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1758 if (MaxAlign == 16)
1759 return;
1760 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1761 if (VTy->getBitWidth() == 128)
1762 MaxAlign = 16;
1763 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1764 unsigned EltAlign = 0;
1765 getMaxByValAlign(ATy->getElementType(), EltAlign);
1766 if (EltAlign > MaxAlign)
1767 MaxAlign = EltAlign;
1768 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1769 for (auto *EltTy : STy->elements()) {
1770 unsigned EltAlign = 0;
1771 getMaxByValAlign(EltTy, EltAlign);
1772 if (EltAlign > MaxAlign)
1773 MaxAlign = EltAlign;
1774 if (MaxAlign == 16)
1775 break;
1776 }
1777 }
1778}
1779
1780/// Return the desired alignment for ByVal aggregate
1781/// function arguments in the caller parameter area. For X86, aggregates
1782/// that contain SSE vectors are placed at 16-byte boundaries while the rest
1783/// are at 4-byte boundaries.
1784unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty,
1785 const DataLayout &DL) const {
1786 if (Subtarget.is64Bit()) {
1787 // Max of 8 and alignment of type.
1788 unsigned TyAlign = DL.getABITypeAlignment(Ty);
1789 if (TyAlign > 8)
1790 return TyAlign;
1791 return 8;
1792 }
1793
1794 unsigned Align = 4;
1795 if (Subtarget.hasSSE1())
1796 getMaxByValAlign(Ty, Align);
1797 return Align;
1798}
1799
1800/// Returns the target specific optimal type for load
1801/// and store operations as a result of memset, memcpy, and memmove
1802/// lowering. If DstAlign is zero that means it's safe to destination
1803/// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1804/// means there isn't a need to check it against alignment requirement,
1805/// probably because the source does not need to be loaded. If 'IsMemset' is
1806/// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1807/// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1808/// source is constant so it does not need to be loaded.
1809/// It returns EVT::Other if the type should be determined using generic
1810/// target-independent logic.
1811EVT
1812X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1813 unsigned DstAlign, unsigned SrcAlign,
1814 bool IsMemset, bool ZeroMemset,
1815 bool MemcpyStrSrc,
1816 MachineFunction &MF) const {
1817 const Function *F = MF.getFunction();
1818 if (!F->hasFnAttribute(Attribute::NoImplicitFloat)) {
1819 if (Size >= 16 &&
1820 (!Subtarget.isUnalignedMem16Slow() ||
1821 ((DstAlign == 0 || DstAlign >= 16) &&
1822 (SrcAlign == 0 || SrcAlign >= 16)))) {
1823 // FIXME: Check if unaligned 32-byte accesses are slow.
1824 if (Size >= 32 && Subtarget.hasAVX()) {
1825 // Although this isn't a well-supported type for AVX1, we'll let
1826 // legalization and shuffle lowering produce the optimal codegen. If we
1827 // choose an optimal type with a vector element larger than a byte,
1828 // getMemsetStores() may create an intermediate splat (using an integer
1829 // multiply) before we splat as a vector.
1830 return MVT::v32i8;
1831 }
1832 if (Subtarget.hasSSE2())
1833 return MVT::v16i8;
1834 // TODO: Can SSE1 handle a byte vector?
1835 if (Subtarget.hasSSE1())
1836 return MVT::v4f32;
1837 } else if ((!IsMemset || ZeroMemset) && !MemcpyStrSrc && Size >= 8 &&
1838 !Subtarget.is64Bit() && Subtarget.hasSSE2()) {
1839 // Do not use f64 to lower memcpy if source is string constant. It's
1840 // better to use i32 to avoid the loads.
1841 // Also, do not use f64 to lower memset unless this is a memset of zeros.
1842 // The gymnastics of splatting a byte value into an XMM register and then
1843 // only using 8-byte stores (because this is a CPU with slow unaligned
1844 // 16-byte accesses) makes that a loser.
1845 return MVT::f64;
1846 }
1847 }
1848 // This is a compromise. If we reach here, unaligned accesses may be slow on
1849 // this target. However, creating smaller, aligned accesses could be even
1850 // slower and would certainly be a lot more code.
1851 if (Subtarget.is64Bit() && Size >= 8)
1852 return MVT::i64;
1853 return MVT::i32;
1854}
1855
1856bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1857 if (VT == MVT::f32)
1858 return X86ScalarSSEf32;
1859 else if (VT == MVT::f64)
1860 return X86ScalarSSEf64;
1861 return true;
1862}
1863
1864bool
1865X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1866 unsigned,
1867 unsigned,
1868 bool *Fast) const {
1869 if (Fast) {
1870 switch (VT.getSizeInBits()) {
1871 default:
1872 // 8-byte and under are always assumed to be fast.
1873 *Fast = true;
1874 break;
1875 case 128:
1876 *Fast = !Subtarget.isUnalignedMem16Slow();
1877 break;
1878 case 256:
1879 *Fast = !Subtarget.isUnalignedMem32Slow();
1880 break;
1881 // TODO: What about AVX-512 (512-bit) accesses?
1882 }
1883 }
1884 // Misaligned accesses of any size are always allowed.
1885 return true;
1886}
1887
1888/// Return the entry encoding for a jump table in the
1889/// current function. The returned value is a member of the
1890/// MachineJumpTableInfo::JTEntryKind enum.
1891unsigned X86TargetLowering::getJumpTableEncoding() const {
1892 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1893 // symbol.
1894 if (isPositionIndependent() && Subtarget.isPICStyleGOT())
1895 return MachineJumpTableInfo::EK_Custom32;
1896
1897 // Otherwise, use the normal jump table encoding heuristics.
1898 return TargetLowering::getJumpTableEncoding();
1899}
1900
1901bool X86TargetLowering::useSoftFloat() const {
1902 return Subtarget.useSoftFloat();
1903}
1904
1905void X86TargetLowering::markLibCallAttributes(MachineFunction *MF, unsigned CC,
1906 ArgListTy &Args) const {
1907
1908 // Only relabel X86-32 for C / Stdcall CCs.
1909 if (Subtarget.is64Bit())
1910 return;
1911 if (CC != CallingConv::C && CC != CallingConv::X86_StdCall)
1912 return;
1913 unsigned ParamRegs = 0;
1914 if (auto *M = MF->getFunction()->getParent())
1915 ParamRegs = M->getNumberRegisterParameters();
1916
1917 // Mark the first N int arguments as having reg
1918 for (unsigned Idx = 0; Idx < Args.size(); Idx++) {
1919 Type *T = Args[Idx].Ty;
1920 if (T->isPointerTy() || T->isIntegerTy())
1921 if (MF->getDataLayout().getTypeAllocSize(T) <= 8) {
1922 unsigned numRegs = 1;
1923 if (MF->getDataLayout().getTypeAllocSize(T) > 4)
1924 numRegs = 2;
1925 if (ParamRegs < numRegs)
1926 return;
1927 ParamRegs -= numRegs;
1928 Args[Idx].IsInReg = true;
1929 }
1930 }
1931}
1932
1933const MCExpr *
1934X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1935 const MachineBasicBlock *MBB,
1936 unsigned uid,MCContext &Ctx) const{
1937 assert(isPositionIndependent() && Subtarget.isPICStyleGOT())(static_cast <bool> (isPositionIndependent() &&
Subtarget.isPICStyleGOT()) ? void (0) : __assert_fail ("isPositionIndependent() && Subtarget.isPICStyleGOT()"
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 1937, __extension__ __PRETTY_FUNCTION__))
;
1938 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1939 // entries.
1940 return MCSymbolRefExpr::create(MBB->getSymbol(),
1941 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1942}
1943
1944/// Returns relocation base for the given PIC jumptable.
1945SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1946 SelectionDAG &DAG) const {
1947 if (!Subtarget.is64Bit())
1948 // This doesn't have SDLoc associated with it, but is not really the
1949 // same as a Register.
1950 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(),
1951 getPointerTy(DAG.getDataLayout()));
1952 return Table;
1953}
1954
1955/// This returns the relocation base for the given PIC jumptable,
1956/// the same as getPICJumpTableRelocBase, but as an MCExpr.
1957const MCExpr *X86TargetLowering::
1958getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1959 MCContext &Ctx) const {
1960 // X86-64 uses RIP relative addressing based on the jump table label.
1961 if (Subtarget.isPICStyleRIPRel())
1962 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1963
1964 // Otherwise, the reference is relative to the PIC base.
1965 return MCSymbolRefExpr::create(MF->getPICBaseSymbol(), Ctx);
1966}
1967
1968std::pair<const TargetRegisterClass *, uint8_t>
1969X86TargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
1970 MVT VT) const {
1971 const TargetRegisterClass *RRC = nullptr;
1972 uint8_t Cost = 1;
1973 switch (VT.SimpleTy) {
1974 default:
1975 return TargetLowering::findRepresentativeClass(TRI, VT);
1976 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1977 RRC = Subtarget.is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
1978 break;
1979 case MVT::x86mmx:
1980 RRC = &X86::VR64RegClass;
1981 break;
1982 case MVT::f32: case MVT::f64:
1983 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1984 case MVT::v4f32: case MVT::v2f64:
1985 case MVT::v32i8: case MVT::v16i16: case MVT::v8i32: case MVT::v4i64:
1986 case MVT::v8f32: case MVT::v4f64:
1987 case MVT::v64i8: case MVT::v32i16: case MVT::v16i32: case MVT::v8i64:
1988 case MVT::v16f32: case MVT::v8f64:
1989 RRC = &X86::VR128XRegClass;
1990 break;
1991 }
1992 return std::make_pair(RRC, Cost);
1993}
1994
1995unsigned X86TargetLowering::getAddressSpace() const {
1996 if (Subtarget.is64Bit())
1997 return (getTargetMachine().getCodeModel() == CodeModel::Kernel) ? 256 : 257;
1998 return 256;
1999}
2000
2001static bool hasStackGuardSlotTLS(const Triple &TargetTriple) {
2002 return TargetTriple.isOSGlibc() || TargetTriple.isOSFuchsia() ||
2003 (TargetTriple.isAndroid() && !TargetTriple.isAndroidVersionLT(17));
2004}
2005
2006static Constant* SegmentOffset(IRBuilder<> &IRB,
2007 unsigned Offset, unsigned AddressSpace) {
2008 return ConstantExpr::getIntToPtr(
2009 ConstantInt::get(Type::getInt32Ty(IRB.getContext()), Offset),
2010 Type::getInt8PtrTy(IRB.getContext())->getPointerTo(AddressSpace));
2011}
2012
2013Value *X86TargetLowering::getIRStackGuard(IRBuilder<> &IRB) const {
2014 // glibc, bionic, and Fuchsia have a special slot for the stack guard in
2015 // tcbhead_t; use it instead of the usual global variable (see
2016 // sysdeps/{i386,x86_64}/nptl/tls.h)
2017 if (hasStackGuardSlotTLS(Subtarget.getTargetTriple())) {
2018 if (Subtarget.isTargetFuchsia()) {
2019 // <zircon/tls.h> defines ZX_TLS_STACK_GUARD_OFFSET with this value.
2020 return SegmentOffset(IRB, 0x10, getAddressSpace());
2021 } else {
2022 // %fs:0x28, unless we're using a Kernel code model, in which case
2023 // it's %gs:0x28. gs:0x14 on i386.
2024 unsigned Offset = (Subtarget.is64Bit()) ? 0x28 : 0x14;
2025 return SegmentOffset(IRB, Offset, getAddressSpace());
2026 }
2027 }
2028
2029 return TargetLowering::getIRStackGuard(IRB);
2030}
2031
2032void X86TargetLowering::insertSSPDeclarations(Module &M) const {
2033 // MSVC CRT provides functionalities for stack protection.
2034 if (Subtarget.getTargetTriple().isOSMSVCRT()) {
2035 // MSVC CRT has a global variable holding security cookie.
2036 M.getOrInsertGlobal("__security_cookie",
2037 Type::getInt8PtrTy(M.getContext()));
2038
2039 // MSVC CRT has a function to validate security cookie.
2040 auto *SecurityCheckCookie = cast<Function>(
2041 M.getOrInsertFunction("__security_check_cookie",
2042 Type::getVoidTy(M.getContext()),
2043 Type::getInt8PtrTy(M.getContext())));
2044 SecurityCheckCookie->setCallingConv(CallingConv::X86_FastCall);
2045 SecurityCheckCookie->addAttribute(1, Attribute::AttrKind::InReg);
2046 return;
2047 }
2048 // glibc, bionic, and Fuchsia have a special slot for the stack guard.
2049 if (hasStackGuardSlotTLS(Subtarget.getTargetTriple()))
2050 return;
2051 TargetLowering::insertSSPDeclarations(M);
2052}
2053
2054Value *X86TargetLowering::getSDagStackGuard(const Module &M) const {
2055 // MSVC CRT has a global variable holding security cookie.
2056 if (Subtarget.getTargetTriple().isOSMSVCRT())
2057 return M.getGlobalVariable("__security_cookie");
2058 return TargetLowering::getSDagStackGuard(M);
2059}
2060
2061Value *X86TargetLowering::getSSPStackGuardCheck(const Module &M) const {
2062 // MSVC CRT has a function to validate security cookie.
2063 if (Subtarget.getTargetTriple().isOSMSVCRT())
2064 return M.getFunction("__security_check_cookie");
2065 return TargetLowering::getSSPStackGuardCheck(M);
2066}
2067
2068Value *X86TargetLowering::getSafeStackPointerLocation(IRBuilder<> &IRB) const {
2069 if (Subtarget.getTargetTriple().isOSContiki())
2070 return getDefaultSafeStackPointerLocation(IRB, false);
2071
2072 // Android provides a fixed TLS slot for the SafeStack pointer. See the
2073 // definition of TLS_SLOT_SAFESTACK in
2074 // https://android.googlesource.com/platform/bionic/+/master/libc/private/bionic_tls.h
2075 if (Subtarget.isTargetAndroid()) {
2076 // %fs:0x48, unless we're using a Kernel code model, in which case it's %gs:
2077 // %gs:0x24 on i386
2078 unsigned Offset = (Subtarget.is64Bit()) ? 0x48 : 0x24;
2079 return SegmentOffset(IRB, Offset, getAddressSpace());
2080 }
2081
2082 // Fuchsia is similar.
2083 if (Subtarget.isTargetFuchsia()) {
2084 // <zircon/tls.h> defines ZX_TLS_UNSAFE_SP_OFFSET with this value.
2085 return SegmentOffset(IRB, 0x18, getAddressSpace());
2086 }
2087
2088 return TargetLowering::getSafeStackPointerLocation(IRB);
2089}
2090
2091bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
2092 unsigned DestAS) const {
2093 assert(SrcAS != DestAS && "Expected different address spaces!")(static_cast <bool> (SrcAS != DestAS && "Expected different address spaces!"
) ? void (0) : __assert_fail ("SrcAS != DestAS && \"Expected different address spaces!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 2093, __extension__ __PRETTY_FUNCTION__))
;
2094
2095 return SrcAS < 256 && DestAS < 256;
2096}
2097
2098//===----------------------------------------------------------------------===//
2099// Return Value Calling Convention Implementation
2100//===----------------------------------------------------------------------===//
2101
2102#include "X86GenCallingConv.inc"
2103
2104bool X86TargetLowering::CanLowerReturn(
2105 CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
2106 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
2107 SmallVector<CCValAssign, 16> RVLocs;
2108 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
2109 return CCInfo.CheckReturn(Outs, RetCC_X86);
2110}
2111
2112const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
2113 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
2114 return ScratchRegs;
2115}
2116
2117/// Lowers masks values (v*i1) to the local register values
2118/// \returns DAG node after lowering to register type
2119static SDValue lowerMasksToReg(const SDValue &ValArg, const EVT &ValLoc,
2120 const SDLoc &Dl, SelectionDAG &DAG) {
2121 EVT ValVT = ValArg.getValueType();
2122
2123 if ((ValVT == MVT::v8i1 && (ValLoc == MVT::i8 || ValLoc == MVT::i32)) ||
2124 (ValVT == MVT::v16i1 && (ValLoc == MVT::i16 || ValLoc == MVT::i32))) {
2125 // Two stage lowering might be required
2126 // bitcast: v8i1 -> i8 / v16i1 -> i16
2127 // anyextend: i8 -> i32 / i16 -> i32
2128 EVT TempValLoc = ValVT == MVT::v8i1 ? MVT::i8 : MVT::i16;
2129 SDValue ValToCopy = DAG.getBitcast(TempValLoc, ValArg);
2130 if (ValLoc == MVT::i32)
2131 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, Dl, ValLoc, ValToCopy);
2132 return ValToCopy;
2133 } else if ((ValVT == MVT::v32i1 && ValLoc == MVT::i32) ||
2134 (ValVT == MVT::v64i1 && ValLoc == MVT::i64)) {
2135 // One stage lowering is required
2136 // bitcast: v32i1 -> i32 / v64i1 -> i64
2137 return DAG.getBitcast(ValLoc, ValArg);
2138 } else
2139 return DAG.getNode(ISD::SIGN_EXTEND, Dl, ValLoc, ValArg);
2140}
2141
2142/// Breaks v64i1 value into two registers and adds the new node to the DAG
2143static void Passv64i1ArgInRegs(
2144 const SDLoc &Dl, SelectionDAG &DAG, SDValue Chain, SDValue &Arg,
2145 SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass, CCValAssign &VA,
2146 CCValAssign &NextVA, const X86Subtarget &Subtarget) {
2147 assert((Subtarget.hasBWI() || Subtarget.hasBMI()) &&(static_cast <bool> ((Subtarget.hasBWI() || Subtarget.hasBMI
()) && "Expected AVX512BW or AVX512BMI target!") ? void
(0) : __assert_fail ("(Subtarget.hasBWI() || Subtarget.hasBMI()) && \"Expected AVX512BW or AVX512BMI target!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 2148, __extension__ __PRETTY_FUNCTION__))
2148 "Expected AVX512BW or AVX512BMI target!")(static_cast <bool> ((Subtarget.hasBWI() || Subtarget.hasBMI
()) && "Expected AVX512BW or AVX512BMI target!") ? void
(0) : __assert_fail ("(Subtarget.hasBWI() || Subtarget.hasBMI()) && \"Expected AVX512BW or AVX512BMI target!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 2148, __extension__ __PRETTY_FUNCTION__))
;
2149 assert(Subtarget.is32Bit() && "Expecting 32 bit target")(static_cast <bool> (Subtarget.is32Bit() && "Expecting 32 bit target"
) ? void (0) : __assert_fail ("Subtarget.is32Bit() && \"Expecting 32 bit target\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 2149, __extension__ __PRETTY_FUNCTION__))
;
2150 assert(Arg.getValueType() == MVT::i64 && "Expecting 64 bit value")(static_cast <bool> (Arg.getValueType() == MVT::i64 &&
"Expecting 64 bit value") ? void (0) : __assert_fail ("Arg.getValueType() == MVT::i64 && \"Expecting 64 bit value\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 2150, __extension__ __PRETTY_FUNCTION__))
;
2151 assert(VA.isRegLoc() && NextVA.isRegLoc() &&(static_cast <bool> (VA.isRegLoc() && NextVA.isRegLoc
() && "The value should reside in two registers") ? void
(0) : __assert_fail ("VA.isRegLoc() && NextVA.isRegLoc() && \"The value should reside in two registers\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 2152, __extension__ __PRETTY_FUNCTION__))
2152 "The value should reside in two registers")(static_cast <bool> (VA.isRegLoc() && NextVA.isRegLoc
() && "The value should reside in two registers") ? void
(0) : __assert_fail ("VA.isRegLoc() && NextVA.isRegLoc() && \"The value should reside in two registers\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 2152, __extension__ __PRETTY_FUNCTION__))
;
2153
2154 // Before splitting the value we cast it to i64
2155 Arg = DAG.getBitcast(MVT::i64, Arg);
2156
2157 // Splitting the value into two i32 types
2158 SDValue Lo, Hi;
2159 Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, Dl, MVT::i32, Arg,
2160 DAG.getConstant(0, Dl, MVT::i32));
2161 Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, Dl, MVT::i32, Arg,
2162 DAG.getConstant(1, Dl, MVT::i32));
2163
2164 // Attach the two i32 types into corresponding registers
2165 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Lo));
2166 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), Hi));
2167}
2168
2169SDValue
2170X86TargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
2171 bool isVarArg,
2172 const SmallVectorImpl<ISD::OutputArg> &Outs,
2173 const SmallVectorImpl<SDValue> &OutVals,
2174 const SDLoc &dl, SelectionDAG &DAG) const {
2175 MachineFunction &MF = DAG.getMachineFunction();
2176 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2177
2178 // In some cases we need to disable registers from the default CSR list.
2179 // For example, when they are used for argument passing.
2180 bool ShouldDisableCalleeSavedRegister =
2181 CallConv == CallingConv::X86_RegCall ||
2182 MF.getFunction()->hasFnAttribute("no_caller_saved_registers");
2183
2184 if (CallConv == CallingConv::X86_INTR && !Outs.empty())
2185 report_fatal_error("X86 interrupts may not return any value");
2186
2187 SmallVector<CCValAssign, 16> RVLocs;
2188 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
2189 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
2190
2191 SDValue Flag;
2192 SmallVector<SDValue, 6> RetOps;
2193 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
2194 // Operand #1 = Bytes To Pop
2195 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(), dl,
2196 MVT::i32));
2197
2198 // Copy the result values into the output registers.
2199 for (unsigned I = 0, OutsIndex = 0, E = RVLocs.size(); I != E;
2200 ++I, ++OutsIndex) {
2201 CCValAssign &VA = RVLocs[I];
2202 assert(VA.isRegLoc() && "Can only return in registers!")(static_cast <bool> (VA.isRegLoc() && "Can only return in registers!"
) ? void (0) : __assert_fail ("VA.isRegLoc() && \"Can only return in registers!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 2202, __extension__ __PRETTY_FUNCTION__))
;
2203
2204 // Add the register to the CalleeSaveDisableRegs list.
2205 if (ShouldDisableCalleeSavedRegister)
2206 MF.getRegInfo().disableCalleeSavedRegister(VA.getLocReg());
2207
2208 SDValue ValToCopy = OutVals[OutsIndex];
2209 EVT ValVT = ValToCopy.getValueType();
2210
2211 // Promote values to the appropriate types.
2212 if (VA.getLocInfo() == CCValAssign::SExt)
2213 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2214 else if (VA.getLocInfo() == CCValAssign::ZExt)
2215 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2216 else if (VA.getLocInfo() == CCValAssign::AExt) {
2217 if (ValVT.isVector() && ValVT.getVectorElementType() == MVT::i1)
2218 ValToCopy = lowerMasksToReg(ValToCopy, VA.getLocVT(), dl, DAG);
2219 else
2220 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2221 }
2222 else if (VA.getLocInfo() == CCValAssign::BCvt)
2223 ValToCopy = DAG.getBitcast(VA.getLocVT(), ValToCopy);
2224
2225 assert(VA.getLocInfo() != CCValAssign::FPExt &&(static_cast <bool> (VA.getLocInfo() != CCValAssign::FPExt
&& "Unexpected FP-extend for return value.") ? void (
0) : __assert_fail ("VA.getLocInfo() != CCValAssign::FPExt && \"Unexpected FP-extend for return value.\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 2226, __extension__ __PRETTY_FUNCTION__))
2226 "Unexpected FP-extend for return value.")(static_cast <bool> (VA.getLocInfo() != CCValAssign::FPExt
&& "Unexpected FP-extend for return value.") ? void (
0) : __assert_fail ("VA.getLocInfo() != CCValAssign::FPExt && \"Unexpected FP-extend for return value.\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 2226, __extension__ __PRETTY_FUNCTION__))
;
2227
2228 // If this is x86-64, and we disabled SSE, we can't return FP values,
2229 // or SSE or MMX vectors.
2230 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2231 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2232 (Subtarget.is64Bit() && !Subtarget.hasSSE1())) {
2233 errorUnsupported(DAG, dl, "SSE register return with SSE disabled");
2234 VA.convertToReg(X86::FP0); // Set reg to FP0, avoid hitting asserts.
2235 } else if (ValVT == MVT::f64 &&
2236 (Subtarget.is64Bit() && !Subtarget.hasSSE2())) {
2237 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
2238 // llvm-gcc has never done it right and no one has noticed, so this
2239 // should be OK for now.
2240 errorUnsupported(DAG, dl, "SSE2 register return with SSE2 disabled");
2241 VA.convertToReg(X86::FP0); // Set reg to FP0, avoid hitting asserts.
2242 }
2243
2244 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2245 // the RET instruction and handled by the FP Stackifier.
2246 if (VA.getLocReg() == X86::FP0 ||
2247 VA.getLocReg() == X86::FP1) {
2248 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2249 // change the value to the FP stack register class.
2250 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2251 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2252 RetOps.push_back(ValToCopy);
2253 // Don't emit a copytoreg.
2254 continue;
2255 }
2256
2257 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2258 // which is returned in RAX / RDX.
2259 if (Subtarget.is64Bit()) {
2260 if (ValVT == MVT::x86mmx) {
2261 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2262 ValToCopy = DAG.getBitcast(MVT::i64, ValToCopy);
2263 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2264 ValToCopy);
2265 // If we don't have SSE2 available, convert to v4f32 so the generated
2266 // register is legal.
2267 if (!Subtarget.hasSSE2())
2268 ValToCopy = DAG.getBitcast(MVT::v4f32, ValToCopy);
2269 }
2270 }
2271 }
2272
2273 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2274
2275 if (VA.needsCustom()) {
2276 assert(VA.getValVT() == MVT::v64i1 &&(static_cast <bool> (VA.getValVT() == MVT::v64i1 &&
"Currently the only custom case is when we split v64i1 to 2 regs"
) ? void (0) : __assert_fail ("VA.getValVT() == MVT::v64i1 && \"Currently the only custom case is when we split v64i1 to 2 regs\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 2277, __extension__ __PRETTY_FUNCTION__))
2277 "Currently the only custom case is when we split v64i1 to 2 regs")(static_cast <bool> (VA.getValVT() == MVT::v64i1 &&
"Currently the only custom case is when we split v64i1 to 2 regs"
) ? void (0) : __assert_fail ("VA.getValVT() == MVT::v64i1 && \"Currently the only custom case is when we split v64i1 to 2 regs\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 2277, __extension__ __PRETTY_FUNCTION__))
;
2278
2279 Passv64i1ArgInRegs(dl, DAG, Chain, ValToCopy, RegsToPass, VA, RVLocs[++I],
2280 Subtarget);
2281
2282 assert(2 == RegsToPass.size() &&(static_cast <bool> (2 == RegsToPass.size() && "Expecting two registers after Pass64BitArgInRegs"
) ? void (0) : __assert_fail ("2 == RegsToPass.size() && \"Expecting two registers after Pass64BitArgInRegs\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 2283, __extension__ __PRETTY_FUNCTION__))
2283 "Expecting two registers after Pass64BitArgInRegs")(static_cast <bool> (2 == RegsToPass.size() && "Expecting two registers after Pass64BitArgInRegs"
) ? void (0) : __assert_fail ("2 == RegsToPass.size() && \"Expecting two registers after Pass64BitArgInRegs\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 2283, __extension__ __PRETTY_FUNCTION__))
;
2284
2285 // Add the second register to the CalleeSaveDisableRegs list.
2286 if (ShouldDisableCalleeSavedRegister)
2287 MF.getRegInfo().disableCalleeSavedRegister(RVLocs[I].getLocReg());
2288 } else {
2289 RegsToPass.push_back(std::make_pair(VA.getLocReg(), ValToCopy));
2290 }
2291
2292 // Add nodes to the DAG and add the values into the RetOps list
2293 for (auto &Reg : RegsToPass) {
2294 Chain = DAG.getCopyToReg(Chain, dl, Reg.first, Reg.second, Flag);
2295 Flag = Chain.getValue(1);
2296 RetOps.push_back(DAG.getRegister(Reg.first, Reg.second.getValueType()));
2297 }
2298 }
2299
2300 // Swift calling convention does not require we copy the sret argument
2301 // into %rax/%eax for the return, and SRetReturnReg is not set for Swift.
2302
2303 // All x86 ABIs require that for returning structs by value we copy
2304 // the sret argument into %rax/%eax (depending on ABI) for the return.
2305 // We saved the argument into a virtual register in the entry block,
2306 // so now we copy the value out and into %rax/%eax.
2307 //
2308 // Checking Function.hasStructRetAttr() here is insufficient because the IR
2309 // may not have an explicit sret argument. If FuncInfo.CanLowerReturn is
2310 // false, then an sret argument may be implicitly inserted in the SelDAG. In
2311 // either case FuncInfo->setSRetReturnReg() will have been called.
2312 if (unsigned SRetReg = FuncInfo->getSRetReturnReg()) {
2313 // When we have both sret and another return value, we should use the
2314 // original Chain stored in RetOps[0], instead of the current Chain updated
2315 // in the above loop. If we only have sret, RetOps[0] equals to Chain.
2316
2317 // For the case of sret and another return value, we have
2318 // Chain_0 at the function entry
2319 // Chain_1 = getCopyToReg(Chain_0) in the above loop
2320 // If we use Chain_1 in getCopyFromReg, we will have
2321 // Val = getCopyFromReg(Chain_1)
2322 // Chain_2 = getCopyToReg(Chain_1, Val) from below
2323
2324 // getCopyToReg(Chain_0) will be glued together with
2325 // getCopyToReg(Chain_1, Val) into Unit A, getCopyFromReg(Chain_1) will be
2326 // in Unit B, and we will have cyclic dependency between Unit A and Unit B:
2327 // Data dependency from Unit B to Unit A due to usage of Val in
2328 // getCopyToReg(Chain_1, Val)
2329 // Chain dependency from Unit A to Unit B
2330
2331 // So here, we use RetOps[0] (i.e Chain_0) for getCopyFromReg.
2332 SDValue Val = DAG.getCopyFromReg(RetOps[0], dl, SRetReg,
2333 getPointerTy(MF.getDataLayout()));
2334
2335 unsigned RetValReg
2336 = (Subtarget.is64Bit() && !Subtarget.isTarget64BitILP32()) ?
2337 X86::RAX : X86::EAX;
2338 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2339 Flag = Chain.getValue(1);
2340
2341 // RAX/EAX now acts like a return value.
2342 RetOps.push_back(
2343 DAG.getRegister(RetValReg, getPointerTy(DAG.getDataLayout())));
2344
2345 // Add the returned register to the CalleeSaveDisableRegs list.
2346 if (ShouldDisableCalleeSavedRegister)
2347 MF.getRegInfo().disableCalleeSavedRegister(RetValReg);
2348 }
2349
2350 const X86RegisterInfo *TRI = Subtarget.getRegisterInfo();
2351 const MCPhysReg *I =
2352 TRI->getCalleeSavedRegsViaCopy(&DAG.getMachineFunction());
2353 if (I) {
2354 for (; *I; ++I) {
2355 if (X86::GR64RegClass.contains(*I))
2356 RetOps.push_back(DAG.getRegister(*I, MVT::i64));
2357 else
2358 llvm_unreachable("Unexpected register class in CSRsViaCopy!")::llvm::llvm_unreachable_internal("Unexpected register class in CSRsViaCopy!"
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 2358)
;
2359 }
2360 }
2361
2362 RetOps[0] = Chain; // Update chain.
2363
2364 // Add the flag if we have it.
2365 if (Flag.getNode())
2366 RetOps.push_back(Flag);
2367
2368 X86ISD::NodeType opcode = X86ISD::RET_FLAG;
2369 if (CallConv == CallingConv::X86_INTR)
2370 opcode = X86ISD::IRET;
2371 return DAG.getNode(opcode, dl, MVT::Other, RetOps);
2372}
2373
2374bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2375 if (N->getNumValues() != 1 || !N->hasNUsesOfValue(1, 0))
2376 return false;
2377
2378 SDValue TCChain = Chain;
2379 SDNode *Copy = *N->use_begin();
2380 if (Copy->getOpcode() == ISD::CopyToReg) {
2381 // If the copy has a glue operand, we conservatively assume it isn't safe to
2382 // perform a tail call.
2383 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2384 return false;
2385 TCChain = Copy->getOperand(0);
2386 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2387 return false;
2388
2389 bool HasRet = false;
2390 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2391 UI != UE; ++UI) {
2392 if (UI->getOpcode() != X86ISD::RET_FLAG)
2393 return false;
2394 // If we are returning more than one value, we can definitely
2395 // not make a tail call see PR19530
2396 if (UI->getNumOperands() > 4)
2397 return false;
2398 if (UI->getNumOperands() == 4 &&
2399 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2400 return false;
2401 HasRet = true;
2402 }
2403
2404 if (!HasRet)
2405 return false;
2406
2407 Chain = TCChain;
2408 return true;
2409}
2410
2411EVT X86TargetLowering::getTypeForExtReturn(LLVMContext &Context, EVT VT,
2412 ISD::NodeType ExtendKind) const {
2413 MVT ReturnMVT = MVT::i32;
2414
2415 bool Darwin = Subtarget.getTargetTriple().isOSDarwin();
2416 if (VT == MVT::i1 || (!Darwin && (VT == MVT::i8 || VT == MVT::i16))) {
2417 // The ABI does not require i1, i8 or i16 to be extended.
2418 //
2419 // On Darwin, there is code in the wild relying on Clang's old behaviour of
2420 // always extending i8/i16 return values, so keep doing that for now.
2421 // (PR26665).
2422 ReturnMVT = MVT::i8;
2423 }
2424
2425 EVT MinVT = getRegisterType(Context, ReturnMVT);
2426 return VT.bitsLT(MinVT) ? MinVT : VT;
2427}
2428
2429/// Reads two 32 bit registers and creates a 64 bit mask value.
2430/// \param VA The current 32 bit value that need to be assigned.
2431/// \param NextVA The next 32 bit value that need to be assigned.
2432/// \param Root The parent DAG node.
2433/// \param [in,out] InFlag Represents SDvalue in the parent DAG node for
2434/// glue purposes. In the case the DAG is already using
2435/// physical register instead of virtual, we should glue
2436/// our new SDValue to InFlag SDvalue.
2437/// \return a new SDvalue of size 64bit.
2438static SDValue getv64i1Argument(CCValAssign &VA, CCValAssign &NextVA,
2439 SDValue &Root, SelectionDAG &DAG,
2440 const SDLoc &Dl, const X86Subtarget &Subtarget,
2441 SDValue *InFlag = nullptr) {
2442 assert((Subtarget.hasBWI()) && "Expected AVX512BW target!")(static_cast <bool> ((Subtarget.hasBWI()) && "Expected AVX512BW target!"
) ? void (0) : __assert_fail ("(Subtarget.hasBWI()) && \"Expected AVX512BW target!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 2442, __extension__ __PRETTY_FUNCTION__))
;
2443 assert(Subtarget.is32Bit() && "Expecting 32 bit target")(static_cast <bool> (Subtarget.is32Bit() && "Expecting 32 bit target"
) ? void (0) : __assert_fail ("Subtarget.is32Bit() && \"Expecting 32 bit target\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 2443, __extension__ __PRETTY_FUNCTION__))
;
2444 assert(VA.getValVT() == MVT::v64i1 &&(static_cast <bool> (VA.getValVT() == MVT::v64i1 &&
"Expecting first location of 64 bit width type") ? void (0) :
__assert_fail ("VA.getValVT() == MVT::v64i1 && \"Expecting first location of 64 bit width type\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 2445, __extension__ __PRETTY_FUNCTION__))
2445 "Expecting first location of 64 bit width type")(static_cast <bool> (VA.getValVT() == MVT::v64i1 &&
"Expecting first location of 64 bit width type") ? void (0) :
__assert_fail ("VA.getValVT() == MVT::v64i1 && \"Expecting first location of 64 bit width type\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 2445, __extension__ __PRETTY_FUNCTION__))
;
2446 assert(NextVA.getValVT() == VA.getValVT() &&(static_cast <bool> (NextVA.getValVT() == VA.getValVT()
&& "The locations should have the same type") ? void
(0) : __assert_fail ("NextVA.getValVT() == VA.getValVT() && \"The locations should have the same type\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 2447, __extension__ __PRETTY_FUNCTION__))
2447 "The locations should have the same type")(static_cast <bool> (NextVA.getValVT() == VA.getValVT()
&& "The locations should have the same type") ? void
(0) : __assert_fail ("NextVA.getValVT() == VA.getValVT() && \"The locations should have the same type\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 2447, __extension__ __PRETTY_FUNCTION__))
;
2448 assert(VA.isRegLoc() && NextVA.isRegLoc() &&(static_cast <bool> (VA.isRegLoc() && NextVA.isRegLoc
() && "The values should reside in two registers") ? void
(0) : __assert_fail ("VA.isRegLoc() && NextVA.isRegLoc() && \"The values should reside in two registers\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 2449, __extension__ __PRETTY_FUNCTION__))
2449 "The values should reside in two registers")(static_cast <bool> (VA.isRegLoc() && NextVA.isRegLoc
() && "The values should reside in two registers") ? void
(0) : __assert_fail ("VA.isRegLoc() && NextVA.isRegLoc() && \"The values should reside in two registers\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 2449, __extension__ __PRETTY_FUNCTION__))
;
2450
2451 SDValue Lo, Hi;
2452 unsigned Reg;
2453 SDValue ArgValueLo, ArgValueHi;
2454
2455 MachineFunction &MF = DAG.getMachineFunction();
2456 const TargetRegisterClass *RC = &X86::GR32RegClass;
2457
2458 // Read a 32 bit value from the registers
2459 if (nullptr == InFlag) {
2460 // When no physical register is present,
2461 // create an intermediate virtual register
2462 Reg = MF.addLiveIn(VA.getLocReg(), RC);
2463 ArgValueLo = DAG.getCopyFromReg(Root, Dl, Reg, MVT::i32);
2464 Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
2465 ArgValueHi = DAG.getCopyFromReg(Root, Dl, Reg, MVT::i32);
2466 } else {
2467 // When a physical register is available read the value from it and glue
2468 // the reads together.
2469 ArgValueLo =
2470 DAG.getCopyFromReg(Root, Dl, VA.getLocReg(), MVT::i32, *InFlag);
2471 *InFlag = ArgValueLo.getValue(2);
2472 ArgValueHi =
2473 DAG.getCopyFromReg(Root, Dl, NextVA.getLocReg(), MVT::i32, *InFlag);
2474 *InFlag = ArgValueHi.getValue(2);
2475 }
2476
2477 // Convert the i32 type into v32i1 type
2478 Lo = DAG.getBitcast(MVT::v32i1, ArgValueLo);
2479
2480 // Convert the i32 type into v32i1 type
2481 Hi = DAG.getBitcast(MVT::v32i1, ArgValueHi);
2482
2483 // Concatenate the two values together
2484 return DAG.getNode(ISD::CONCAT_VECTORS, Dl, MVT::v64i1, Lo, Hi);
2485}
2486
2487/// The function will lower a register of various sizes (8/16/32/64)
2488/// to a mask value of the expected size (v8i1/v16i1/v32i1/v64i1)
2489/// \returns a DAG node contains the operand after lowering to mask type.
2490static SDValue lowerRegToMasks(const SDValue &ValArg, const EVT &ValVT,
2491 const EVT &ValLoc, const SDLoc &Dl,
2492 SelectionDAG &DAG) {
2493 SDValue ValReturned = ValArg;
2494
2495 if (ValVT == MVT::v1i1)
2496 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Dl, MVT::v1i1, ValReturned);
2497
2498 if (ValVT == MVT::v64i1) {
2499 // In 32 bit machine, this case is handled by getv64i1Argument
2500 assert(ValLoc == MVT::i64 && "Expecting only i64 locations")(static_cast <bool> (ValLoc == MVT::i64 && "Expecting only i64 locations"
) ? void (0) : __assert_fail ("ValLoc == MVT::i64 && \"Expecting only i64 locations\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 2500, __extension__ __PRETTY_FUNCTION__))
;
2501 // In 64 bit machine, There is no need to truncate the value only bitcast
2502 } else {
2503 MVT maskLen;
2504 switch (ValVT.getSimpleVT().SimpleTy) {
2505 case MVT::v8i1:
2506 maskLen = MVT::i8;
2507 break;
2508 case MVT::v16i1:
2509 maskLen = MVT::i16;
2510 break;
2511 case MVT::v32i1:
2512 maskLen = MVT::i32;
2513 break;
2514 default:
2515 llvm_unreachable("Expecting a vector of i1 types")::llvm::llvm_unreachable_internal("Expecting a vector of i1 types"
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 2515)
;
2516 }
2517
2518 ValReturned = DAG.getNode(ISD::TRUNCATE, Dl, maskLen, ValReturned);
2519 }
2520 return DAG.getBitcast(ValVT, ValReturned);
2521}
2522
2523/// Lower the result values of a call into the
2524/// appropriate copies out of appropriate physical registers.
2525///
2526SDValue X86TargetLowering::LowerCallResult(
2527 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
2528 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
2529 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals,
2530 uint32_t *RegMask) const {
2531
2532 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
2533 // Assign locations to each value returned by this call.
2534 SmallVector<CCValAssign, 16> RVLocs;
2535 bool Is64Bit = Subtarget.is64Bit();
2536 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2537 *DAG.getContext());
2538 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2539
2540 // Copy all of the result registers out of their specified physreg.
2541 for (unsigned I = 0, InsIndex = 0, E = RVLocs.size(); I != E;
2542 ++I, ++InsIndex) {
2543 CCValAssign &VA = RVLocs[I];
2544 EVT CopyVT = VA.getLocVT();
2545
2546 // In some calling conventions we need to remove the used registers
2547 // from the register mask.
2548 if (RegMask) {
2549 for (MCSubRegIterator SubRegs(VA.getLocReg(), TRI, /*IncludeSelf=*/true);
2550 SubRegs.isValid(); ++SubRegs)
2551 RegMask[*SubRegs / 32] &= ~(1u << (*SubRegs % 32));
2552 }
2553
2554 // If this is x86-64, and we disabled SSE, we can't return FP values
2555 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64 || CopyVT == MVT::f128) &&
2556 ((Is64Bit || Ins[InsIndex].Flags.isInReg()) && !Subtarget.hasSSE1())) {
2557 errorUnsupported(DAG, dl, "SSE register return with SSE disabled");
2558 VA.convertToReg(X86::FP0); // Set reg to FP0, avoid hitting asserts.
2559 }
2560
2561 // If we prefer to use the value in xmm registers, copy it out as f80 and
2562 // use a truncate to move it from fp stack reg to xmm reg.
2563 bool RoundAfterCopy = false;
2564 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2565 isScalarFPTypeInSSEReg(VA.getValVT())) {
2566 if (!Subtarget.hasX87())
2567 report_fatal_error("X87 register return with X87 disabled");
2568 CopyVT = MVT::f80;
2569 RoundAfterCopy = (CopyVT != VA.getLocVT());
2570 }
2571
2572 SDValue Val;
2573 if (VA.needsCustom()) {
2574 assert(VA.getValVT() == MVT::v64i1 &&(static_cast <bool> (VA.getValVT() == MVT::v64i1 &&
"Currently the only custom case is when we split v64i1 to 2 regs"
) ? void (0) : __assert_fail ("VA.getValVT() == MVT::v64i1 && \"Currently the only custom case is when we split v64i1 to 2 regs\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 2575, __extension__ __PRETTY_FUNCTION__))
2575 "Currently the only custom case is when we split v64i1 to 2 regs")(static_cast <bool> (VA.getValVT() == MVT::v64i1 &&
"Currently the only custom case is when we split v64i1 to 2 regs"
) ? void (0) : __assert_fail ("VA.getValVT() == MVT::v64i1 && \"Currently the only custom case is when we split v64i1 to 2 regs\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 2575, __extension__ __PRETTY_FUNCTION__))
;
2576 Val =
2577 getv64i1Argument(VA, RVLocs[++I], Chain, DAG, dl, Subtarget, &InFlag);
2578 } else {
2579 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), CopyVT, InFlag)
2580 .getValue(1);
2581 Val = Chain.getValue(0);
2582 InFlag = Chain.getValue(2);
2583 }
2584
2585 if (RoundAfterCopy)
2586 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2587 // This truncation won't change the value.
2588 DAG.getIntPtrConstant(1, dl));
2589
2590 if (VA.isExtInLoc() && (VA.getValVT().getScalarType() == MVT::i1)) {
2591 if (VA.getValVT().isVector() &&
2592 ((VA.getLocVT() == MVT::i64) || (VA.getLocVT() == MVT::i32) ||
2593 (VA.getLocVT() == MVT::i16) || (VA.getLocVT() == MVT::i8))) {
2594 // promoting a mask type (v*i1) into a register of type i64/i32/i16/i8
2595 Val = lowerRegToMasks(Val, VA.getValVT(), VA.getLocVT(), dl, DAG);
2596 } else
2597 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
2598 }
2599
2600 InVals.push_back(Val);
2601 }
2602
2603 return Chain;
2604}
2605
2606//===----------------------------------------------------------------------===//
2607// C & StdCall & Fast Calling Convention implementation
2608//===----------------------------------------------------------------------===//
2609// StdCall calling convention seems to be standard for many Windows' API
2610// routines and around. It differs from C calling convention just a little:
2611// callee should clean up the stack, not caller. Symbols should be also
2612// decorated in some fancy way :) It doesn't support any vector arguments.
2613// For info on fast calling convention see Fast Calling Convention (tail call)
2614// implementation LowerX86_32FastCCCallTo.
2615
2616/// CallIsStructReturn - Determines whether a call uses struct return
2617/// semantics.
2618enum StructReturnType {
2619 NotStructReturn,
2620 RegStructReturn,
2621 StackStructReturn
2622};
2623static StructReturnType
2624callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs, bool IsMCU) {
2625 if (Outs.empty())
2626 return NotStructReturn;
2627
2628 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2629 if (!Flags.isSRet())
2630 return NotStructReturn;
2631 if (Flags.isInReg() || IsMCU)
2632 return RegStructReturn;
2633 return StackStructReturn;
2634}
2635
2636/// Determines whether a function uses struct return semantics.
2637static StructReturnType
2638argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins, bool IsMCU) {
2639 if (Ins.empty())
2640 return NotStructReturn;
2641
2642 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2643 if (!Flags.isSRet())
2644 return NotStructReturn;
2645 if (Flags.isInReg() || IsMCU)
2646 return RegStructReturn;
2647 return StackStructReturn;
2648}
2649
2650/// Make a copy of an aggregate at address specified by "Src" to address
2651/// "Dst" with size and alignment information specified by the specific
2652/// parameter attribute. The copy will be passed as a byval function parameter.
2653static SDValue CreateCopyOfByValArgument(SDValue Src, SDValue Dst,
2654 SDValue Chain, ISD::ArgFlagsTy Flags,
2655 SelectionDAG &DAG, const SDLoc &dl) {
2656 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
2657
2658 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2659 /*isVolatile*/false, /*AlwaysInline=*/true,
2660 /*isTailCall*/false,
2661 MachinePointerInfo(), MachinePointerInfo());
2662}
2663
2664/// Return true if the calling convention is one that we can guarantee TCO for.
2665static bool canGuaranteeTCO(CallingConv::ID CC) {
2666 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2667 CC == CallingConv::X86_RegCall || CC == CallingConv::HiPE ||
2668 CC == CallingConv::HHVM);
2669}
2670
2671/// Return true if we might ever do TCO for calls with this calling convention.
2672static bool mayTailCallThisCC(CallingConv::ID CC) {
2673 switch (CC) {
2674 // C calling conventions:
2675 case CallingConv::C:
2676 case CallingConv::Win64:
2677 case CallingConv::X86_64_SysV:
2678 // Callee pop conventions:
2679 case CallingConv::X86_ThisCall:
2680 case CallingConv::X86_StdCall:
2681 case CallingConv::X86_VectorCall:
2682 case CallingConv::X86_FastCall:
2683 return true;
2684 default:
2685 return canGuaranteeTCO(CC);
2686 }
2687}
2688
2689/// Return true if the function is being made into a tailcall target by
2690/// changing its ABI.
2691static bool shouldGuaranteeTCO(CallingConv::ID CC, bool GuaranteedTailCallOpt) {
2692 return GuaranteedTailCallOpt && canGuaranteeTCO(CC);
2693}
2694
2695bool X86TargetLowering::mayBeEmittedAsTailCall(const CallInst *CI) const {
2696 auto Attr =
2697 CI->getParent()->getParent()->getFnAttribute("disable-tail-calls");
2698 if (!CI->isTailCall() || Attr.getValueAsString() == "true")
2699 return false;
2700
2701 ImmutableCallSite CS(CI);
2702 CallingConv::ID CalleeCC = CS.getCallingConv();
2703 if (!mayTailCallThisCC(CalleeCC))
2704 return false;
2705
2706 return true;
2707}
2708
2709SDValue
2710X86TargetLowering::LowerMemArgument(SDValue Chain, CallingConv::ID CallConv,
2711 const SmallVectorImpl<ISD::InputArg> &Ins,
2712 const SDLoc &dl, SelectionDAG &DAG,
2713 const CCValAssign &VA,
2714 MachineFrameInfo &MFI, unsigned i) const {
2715 // Create the nodes corresponding to a load from this parameter slot.
2716 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2717 bool AlwaysUseMutable = shouldGuaranteeTCO(
2718 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2719 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2720 EVT ValVT;
2721 MVT PtrVT = getPointerTy(DAG.getDataLayout());
2722
2723 // If value is passed by pointer we have address passed instead of the value
2724 // itself. No need to extend if the mask value and location share the same
2725 // absolute size.
2726 bool ExtendedInMem =
2727 VA.isExtInLoc() && VA.getValVT().getScalarType() == MVT::i1 &&
2728 VA.getValVT().getSizeInBits() != VA.getLocVT().getSizeInBits();
2729
2730 if (VA.getLocInfo() == CCValAssign::Indirect || ExtendedInMem)
2731 ValVT = VA.getLocVT();
2732 else
2733 ValVT = VA.getValVT();
2734
2735 // Calculate SP offset of interrupt parameter, re-arrange the slot normally
2736 // taken by a return address.
2737 int Offset = 0;
2738 if (CallConv == CallingConv::X86_INTR) {
2739 // X86 interrupts may take one or two arguments.
2740 // On the stack there will be no return address as in regular call.
2741 // Offset of last argument need to be set to -4/-8 bytes.
2742 // Where offset of the first argument out of two, should be set to 0 bytes.
2743 Offset = (Subtarget.is64Bit() ? 8 : 4) * ((i + 1) % Ins.size() - 1);
2744 if (Subtarget.is64Bit() && Ins.size() == 2) {
2745 // The stack pointer needs to be realigned for 64 bit handlers with error
2746 // code, so the argument offset changes by 8 bytes.
2747 Offset += 8;
2748 }
2749 }
2750
2751 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2752 // changed with more analysis.
2753 // In case of tail call optimization mark all arguments mutable. Since they
2754 // could be overwritten by lowering of arguments in case of a tail call.
2755 if (Flags.isByVal()) {
2756 unsigned Bytes = Flags.getByValSize();
2757 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2758 int FI = MFI.CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2759 // Adjust SP offset of interrupt parameter.
2760 if (CallConv == CallingConv::X86_INTR) {
2761 MFI.setObjectOffset(FI, Offset);
2762 }
2763 return DAG.getFrameIndex(FI, PtrVT);
2764 }
2765
2766 // This is an argument in memory. We might be able to perform copy elision.
2767 if (Flags.isCopyElisionCandidate()) {
2768 EVT ArgVT = Ins[i].ArgVT;
2769 SDValue PartAddr;
2770 if (Ins[i].PartOffset == 0) {
2771 // If this is a one-part value or the first part of a multi-part value,
2772 // create a stack object for the entire argument value type and return a
2773 // load from our portion of it. This assumes that if the first part of an
2774 // argument is in memory, the rest will also be in memory.
2775 int FI = MFI.CreateFixedObject(ArgVT.getStoreSize(), VA.getLocMemOffset(),
2776 /*Immutable=*/false);
2777 PartAddr = DAG.getFrameIndex(FI, PtrVT);
2778 return DAG.getLoad(
2779 ValVT, dl, Chain, PartAddr,
2780 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI));
2781 } else {
2782 // This is not the first piece of an argument in memory. See if there is
2783 // already a fixed stack object including this offset. If so, assume it
2784 // was created by the PartOffset == 0 branch above and create a load from
2785 // the appropriate offset into it.
2786 int64_t PartBegin = VA.getLocMemOffset();
2787 int64_t PartEnd = PartBegin + ValVT.getSizeInBits() / 8;
2788 int FI = MFI.getObjectIndexBegin();
2789 for (; MFI.isFixedObjectIndex(FI); ++FI) {
2790 int64_t ObjBegin = MFI.getObjectOffset(FI);
2791 int64_t ObjEnd = ObjBegin + MFI.getObjectSize(FI);
2792 if (ObjBegin <= PartBegin && PartEnd <= ObjEnd)
2793 break;
2794 }
2795 if (MFI.isFixedObjectIndex(FI)) {
2796 SDValue Addr =
2797 DAG.getNode(ISD::ADD, dl, PtrVT, DAG.getFrameIndex(FI, PtrVT),
2798 DAG.getIntPtrConstant(Ins[i].PartOffset, dl));
2799 return DAG.getLoad(
2800 ValVT, dl, Chain, Addr,
2801 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI,
2802 Ins[i].PartOffset));
2803 }
2804 }
2805 }
2806
2807 int FI = MFI.CreateFixedObject(ValVT.getSizeInBits() / 8,
2808 VA.getLocMemOffset(), isImmutable);
2809
2810 // Set SExt or ZExt flag.
2811 if (VA.getLocInfo() == CCValAssign::ZExt) {
2812 MFI.setObjectZExt(FI, true);
2813 } else if (VA.getLocInfo() == CCValAssign::SExt) {
2814 MFI.setObjectSExt(FI, true);
2815 }
2816
2817 // Adjust SP offset of interrupt parameter.
2818 if (CallConv == CallingConv::X86_INTR) {
2819 MFI.setObjectOffset(FI, Offset);
2820 }
2821
2822 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2823 SDValue Val = DAG.getLoad(
2824 ValVT, dl, Chain, FIN,
2825 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI));
2826 return ExtendedInMem
2827 ? (VA.getValVT().isVector()
2828 ? DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VA.getValVT(), Val)
2829 : DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val))
2830 : Val;
2831}
2832
2833// FIXME: Get this from tablegen.
2834static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2835 const X86Subtarget &Subtarget) {
2836 assert(Subtarget.is64Bit())(static_cast <bool> (Subtarget.is64Bit()) ? void (0) : __assert_fail
("Subtarget.is64Bit()", "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 2836, __extension__ __PRETTY_FUNCTION__))
;
2837
2838 if (Subtarget.isCallingConvWin64(CallConv)) {
2839 static const MCPhysReg GPR64ArgRegsWin64[] = {
2840 X86::RCX, X86::RDX, X86::R8, X86::R9
2841 };
2842 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2843 }
2844
2845 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2846 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2847 };
2848 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2849}
2850
2851// FIXME: Get this from tablegen.
2852static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2853 CallingConv::ID CallConv,
2854 const X86Subtarget &Subtarget) {
2855 assert(Subtarget.is64Bit())(static_cast <bool> (Subtarget.is64Bit()) ? void (0) : __assert_fail
("Subtarget.is64Bit()", "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 2855, __extension__ __PRETTY_FUNCTION__))
;
2856 if (Subtarget.isCallingConvWin64(CallConv)) {
2857 // The XMM registers which might contain var arg parameters are shadowed
2858 // in their paired GPR. So we only need to save the GPR to their home
2859 // slots.
2860 // TODO: __vectorcall will change this.
2861 return None;
2862 }
2863
2864 const Function *Fn = MF.getFunction();
2865 bool NoImplicitFloatOps = Fn->hasFnAttribute(Attribute::NoImplicitFloat);
2866 bool isSoftFloat = Subtarget.useSoftFloat();
2867 assert(!(isSoftFloat && NoImplicitFloatOps) &&(static_cast <bool> (!(isSoftFloat && NoImplicitFloatOps
) && "SSE register cannot be used when SSE is disabled!"
) ? void (0) : __assert_fail ("!(isSoftFloat && NoImplicitFloatOps) && \"SSE register cannot be used when SSE is disabled!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 2868, __extension__ __PRETTY_FUNCTION__))
2868 "SSE register cannot be used when SSE is disabled!")(static_cast <bool> (!(isSoftFloat && NoImplicitFloatOps
) && "SSE register cannot be used when SSE is disabled!"
) ? void (0) : __assert_fail ("!(isSoftFloat && NoImplicitFloatOps) && \"SSE register cannot be used when SSE is disabled!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 2868, __extension__ __PRETTY_FUNCTION__))
;
2869 if (isSoftFloat || NoImplicitFloatOps || !Subtarget.hasSSE1())
2870 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2871 // registers.
2872 return None;
2873
2874 static const MCPhysReg XMMArgRegs64Bit[] = {
2875 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2876 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2877 };
2878 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2879}
2880
2881#ifndef NDEBUG
2882static bool isSortedByValueNo(const SmallVectorImpl<CCValAssign> &ArgLocs) {
2883 return std::is_sorted(ArgLocs.begin(), ArgLocs.end(),
2884 [](const CCValAssign &A, const CCValAssign &B) -> bool {
2885 return A.getValNo() < B.getValNo();
2886 });
2887}
2888#endif
2889
2890SDValue X86TargetLowering::LowerFormalArguments(
2891 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
2892 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
2893 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
2894 MachineFunction &MF = DAG.getMachineFunction();
2895 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2896 const TargetFrameLowering &TFI = *Subtarget.getFrameLowering();
2897
2898 const Function *Fn = MF.getFunction();
2899 if (Fn->hasExternalLinkage() &&
2900 Subtarget.isTargetCygMing() &&
2901 Fn->getName() == "main")
2902 FuncInfo->setForceFramePointer(true);
2903
2904 MachineFrameInfo &MFI = MF.getFrameInfo();
2905 bool Is64Bit = Subtarget.is64Bit();
2906 bool IsWin64 = Subtarget.isCallingConvWin64(CallConv);
2907
2908 assert((static_cast <bool> (!(isVarArg && canGuaranteeTCO
(CallConv)) && "Var args not supported with calling conv' regcall, fastcc, ghc or hipe"
) ? void (0) : __assert_fail ("!(isVarArg && canGuaranteeTCO(CallConv)) && \"Var args not supported with calling conv' regcall, fastcc, ghc or hipe\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 2910, __extension__ __PRETTY_FUNCTION__))
2909 !(isVarArg && canGuaranteeTCO(CallConv)) &&(static_cast <bool> (!(isVarArg && canGuaranteeTCO
(CallConv)) && "Var args not supported with calling conv' regcall, fastcc, ghc or hipe"
) ? void (0) : __assert_fail ("!(isVarArg && canGuaranteeTCO(CallConv)) && \"Var args not supported with calling conv' regcall, fastcc, ghc or hipe\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 2910, __extension__ __PRETTY_FUNCTION__))
2910 "Var args not supported with calling conv' regcall, fastcc, ghc or hipe")(static_cast <bool> (!(isVarArg && canGuaranteeTCO
(CallConv)) && "Var args not supported with calling conv' regcall, fastcc, ghc or hipe"
) ? void (0) : __assert_fail ("!(isVarArg && canGuaranteeTCO(CallConv)) && \"Var args not supported with calling conv' regcall, fastcc, ghc or hipe\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 2910, __extension__ __PRETTY_FUNCTION__))
;
2911
2912 if (CallConv == CallingConv::X86_INTR) {
2913 bool isLegal = Ins.size() == 1 ||
2914 (Ins.size() == 2 && ((Is64Bit && Ins[1].VT == MVT::i64) ||
2915 (!Is64Bit && Ins[1].VT == MVT::i32)));
2916 if (!isLegal)
2917 report_fatal_error("X86 interrupts may take one or two arguments");
2918 }
2919
2920 // Assign locations to all of the incoming arguments.
2921 SmallVector<CCValAssign, 16> ArgLocs;
2922 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2923
2924 // Allocate shadow area for Win64.
2925 if (IsWin64)
2926 CCInfo.AllocateStack(32, 8);
2927
2928 CCInfo.AnalyzeArguments(Ins, CC_X86);
2929
2930 // In vectorcall calling convention a second pass is required for the HVA
2931 // types.
2932 if (CallingConv::X86_VectorCall == CallConv) {
2933 CCInfo.AnalyzeArgumentsSecondPass(Ins, CC_X86);
2934 }
2935
2936 // The next loop assumes that the locations are in the same order of the
2937 // input arguments.
2938 assert(isSortedByValueNo(ArgLocs) &&(static_cast <bool> (isSortedByValueNo(ArgLocs) &&
"Argument Location list must be sorted before lowering") ? void
(0) : __assert_fail ("isSortedByValueNo(ArgLocs) && \"Argument Location list must be sorted before lowering\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 2939, __extension__ __PRETTY_FUNCTION__))
2939 "Argument Location list must be sorted before lowering")(static_cast <bool> (isSortedByValueNo(ArgLocs) &&
"Argument Location list must be sorted before lowering") ? void
(0) : __assert_fail ("isSortedByValueNo(ArgLocs) && \"Argument Location list must be sorted before lowering\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 2939, __extension__ __PRETTY_FUNCTION__))
;
2940
2941 SDValue ArgValue;
2942 for (unsigned I = 0, InsIndex = 0, E = ArgLocs.size(); I != E;
2943 ++I, ++InsIndex) {
2944 assert(InsIndex < Ins.size() && "Invalid Ins index")(static_cast <bool> (InsIndex < Ins.size() &&
"Invalid Ins index") ? void (0) : __assert_fail ("InsIndex < Ins.size() && \"Invalid Ins index\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 2944, __extension__ __PRETTY_FUNCTION__))
;
2945 CCValAssign &VA = ArgLocs[I];
2946
2947 if (VA.isRegLoc()) {
2948 EVT RegVT = VA.getLocVT();
2949 if (VA.needsCustom()) {
2950 assert((static_cast <bool> (VA.getValVT() == MVT::v64i1 &&
"Currently the only custom case is when we split v64i1 to 2 regs"
) ? void (0) : __assert_fail ("VA.getValVT() == MVT::v64i1 && \"Currently the only custom case is when we split v64i1 to 2 regs\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 2952, __extension__ __PRETTY_FUNCTION__))
2951 VA.getValVT() == MVT::v64i1 &&(static_cast <bool> (VA.getValVT() == MVT::v64i1 &&
"Currently the only custom case is when we split v64i1 to 2 regs"
) ? void (0) : __assert_fail ("VA.getValVT() == MVT::v64i1 && \"Currently the only custom case is when we split v64i1 to 2 regs\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 2952, __extension__ __PRETTY_FUNCTION__))
2952 "Currently the only custom case is when we split v64i1 to 2 regs")(static_cast <bool> (VA.getValVT() == MVT::v64i1 &&
"Currently the only custom case is when we split v64i1 to 2 regs"
) ? void (0) : __assert_fail ("VA.getValVT() == MVT::v64i1 && \"Currently the only custom case is when we split v64i1 to 2 regs\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 2952, __extension__ __PRETTY_FUNCTION__))
;
2953
2954 // v64i1 values, in regcall calling convention, that are
2955 // compiled to 32 bit arch, are split up into two registers.
2956 ArgValue =
2957 getv64i1Argument(VA, ArgLocs[++I], Chain, DAG, dl, Subtarget);
2958 } else {
2959 const TargetRegisterClass *RC;
2960 if (RegVT == MVT::i32)
2961 RC = &X86::GR32RegClass;
2962 else if (Is64Bit && RegVT == MVT::i64)
2963 RC = &X86::GR64RegClass;
2964 else if (RegVT == MVT::f32)
2965 RC = Subtarget.hasAVX512() ? &X86::FR32XRegClass : &X86::FR32RegClass;
2966 else if (RegVT == MVT::f64)
2967 RC = Subtarget.hasAVX512() ? &X86::FR64XRegClass : &X86::FR64RegClass;
2968 else if (RegVT == MVT::f80)
2969 RC = &X86::RFP80RegClass;
2970 else if (RegVT == MVT::f128)
2971 RC = &X86::FR128RegClass;
2972 else if (RegVT.is512BitVector())
2973 RC = &X86::VR512RegClass;
2974 else if (RegVT.is256BitVector())
2975 RC = Subtarget.hasVLX() ? &X86::VR256XRegClass : &X86::VR256RegClass;
2976 else if (RegVT.is128BitVector())
2977 RC = Subtarget.hasVLX() ? &X86::VR128XRegClass : &X86::VR128RegClass;
2978 else if (RegVT == MVT::x86mmx)
2979 RC = &X86::VR64RegClass;
2980 else if (RegVT == MVT::v1i1)
2981 RC = &X86::VK1RegClass;
2982 else if (RegVT == MVT::v8i1)
2983 RC = &X86::VK8RegClass;
2984 else if (RegVT == MVT::v16i1)
2985 RC = &X86::VK16RegClass;
2986 else if (RegVT == MVT::v32i1)
2987 RC = &X86::VK32RegClass;
2988 else if (RegVT == MVT::v64i1)
2989 RC = &X86::VK64RegClass;
2990 else
2991 llvm_unreachable("Unknown argument type!")::llvm::llvm_unreachable_internal("Unknown argument type!", "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 2991)
;
2992
2993 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2994 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2995 }
2996
2997 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2998 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2999 // right size.
3000 if (VA.getLocInfo() == CCValAssign::SExt)
3001 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
3002 DAG.getValueType(VA.getValVT()));
3003 else if (VA.getLocInfo() == CCValAssign::ZExt)
3004 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
3005 DAG.getValueType(VA.getValVT()));
3006 else if (VA.getLocInfo() == CCValAssign::BCvt)
3007 ArgValue = DAG.getBitcast(VA.getValVT(), ArgValue);
3008
3009 if (VA.isExtInLoc()) {
3010 // Handle MMX values passed in XMM regs.
3011 if (RegVT.isVector() && VA.getValVT().getScalarType() != MVT::i1)
3012 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
3013 else if (VA.getValVT().isVector() &&
3014 VA.getValVT().getScalarType() == MVT::i1 &&
3015 ((VA.getLocVT() == MVT::i64) || (VA.getLocVT() == MVT::i32) ||
3016 (VA.getLocVT() == MVT::i16) || (VA.getLocVT() == MVT::i8))) {
3017 // Promoting a mask type (v*i1) into a register of type i64/i32/i16/i8
3018 ArgValue = lowerRegToMasks(ArgValue, VA.getValVT(), RegVT, dl, DAG);
3019 } else
3020 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
3021 }
3022 } else {
3023 assert(VA.isMemLoc())(static_cast <bool> (VA.isMemLoc()) ? void (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 3023, __extension__ __PRETTY_FUNCTION__))
;
3024 ArgValue =
3025 LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, InsIndex);
3026 }
3027
3028 // If value is passed via pointer - do a load.
3029 if (VA.getLocInfo() == CCValAssign::Indirect)
3030 ArgValue =
3031 DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue, MachinePointerInfo());
3032
3033 InVals.push_back(ArgValue);
3034 }
3035
3036 for (unsigned I = 0, E = Ins.size(); I != E; ++I) {
3037 // Swift calling convention does not require we copy the sret argument
3038 // into %rax/%eax for the return. We don't set SRetReturnReg for Swift.
3039 if (CallConv == CallingConv::Swift)
3040 continue;
3041
3042 // All x86 ABIs require that for returning structs by value we copy the
3043 // sret argument into %rax/%eax (depending on ABI) for the return. Save
3044 // the argument into a virtual register so that we can access it from the
3045 // return points.
3046 if (Ins[I].Flags.isSRet()) {
3047 unsigned Reg = FuncInfo->getSRetReturnReg();
3048 if (!Reg) {
3049 MVT PtrTy = getPointerTy(DAG.getDataLayout());
3050 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
3051 FuncInfo->setSRetReturnReg(Reg);
3052 }
3053 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[I]);
3054 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
3055 break;
3056 }
3057 }
3058
3059 unsigned StackSize = CCInfo.getNextStackOffset();
3060 // Align stack specially for tail calls.
3061 if (shouldGuaranteeTCO(CallConv,
3062 MF.getTarget().Options.GuaranteedTailCallOpt))
3063 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
3064
3065 // If the function takes variable number of arguments, make a frame index for
3066 // the start of the first vararg value... for expansion of llvm.va_start. We
3067 // can skip this if there are no va_start calls.
3068 if (MFI.hasVAStart() &&
3069 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
3070 CallConv != CallingConv::X86_ThisCall))) {
3071 FuncInfo->setVarArgsFrameIndex(MFI.CreateFixedObject(1, StackSize, true));
3072 }
3073
3074 // Figure out if XMM registers are in use.
3075 assert(!(Subtarget.useSoftFloat() &&(static_cast <bool> (!(Subtarget.useSoftFloat() &&
Fn->hasFnAttribute(Attribute::NoImplicitFloat)) &&
"SSE register cannot be used when SSE is disabled!") ? void (
0) : __assert_fail ("!(Subtarget.useSoftFloat() && Fn->hasFnAttribute(Attribute::NoImplicitFloat)) && \"SSE register cannot be used when SSE is disabled!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 3077, __extension__ __PRETTY_FUNCTION__))
3076 Fn->hasFnAttribute(Attribute::NoImplicitFloat)) &&(static_cast <bool> (!(Subtarget.useSoftFloat() &&
Fn->hasFnAttribute(Attribute::NoImplicitFloat)) &&
"SSE register cannot be used when SSE is disabled!") ? void (
0) : __assert_fail ("!(Subtarget.useSoftFloat() && Fn->hasFnAttribute(Attribute::NoImplicitFloat)) && \"SSE register cannot be used when SSE is disabled!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 3077, __extension__ __PRETTY_FUNCTION__))
3077 "SSE register cannot be used when SSE is disabled!")(static_cast <bool> (!(Subtarget.useSoftFloat() &&
Fn->hasFnAttribute(Attribute::NoImplicitFloat)) &&
"SSE register cannot be used when SSE is disabled!") ? void (
0) : __assert_fail ("!(Subtarget.useSoftFloat() && Fn->hasFnAttribute(Attribute::NoImplicitFloat)) && \"SSE register cannot be used when SSE is disabled!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 3077, __extension__ __PRETTY_FUNCTION__))
;
3078
3079 // 64-bit calling conventions support varargs and register parameters, so we
3080 // have to do extra work to spill them in the prologue.
3081 if (Is64Bit && isVarArg && MFI.hasVAStart()) {
3082 // Find the first unallocated argument registers.
3083 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
3084 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
3085 unsigned NumIntRegs = CCInfo.getFirstUnallocated(ArgGPRs);
3086 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(ArgXMMs);
3087 assert(!(NumXMMRegs && !Subtarget.hasSSE1()) &&(static_cast <bool> (!(NumXMMRegs && !Subtarget
.hasSSE1()) && "SSE register cannot be used when SSE is disabled!"
) ? void (0) : __assert_fail ("!(NumXMMRegs && !Subtarget.hasSSE1()) && \"SSE register cannot be used when SSE is disabled!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 3088, __extension__ __PRETTY_FUNCTION__))
3088 "SSE register cannot be used when SSE is disabled!")(static_cast <bool> (!(NumXMMRegs && !Subtarget
.hasSSE1()) && "SSE register cannot be used when SSE is disabled!"
) ? void (0) : __assert_fail ("!(NumXMMRegs && !Subtarget.hasSSE1()) && \"SSE register cannot be used when SSE is disabled!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 3088, __extension__ __PRETTY_FUNCTION__))
;
3089
3090 // Gather all the live in physical registers.
3091 SmallVector<SDValue, 6> LiveGPRs;
3092 SmallVector<SDValue, 8> LiveXMMRegs;
3093 SDValue ALVal;
3094 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
3095 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
3096 LiveGPRs.push_back(
3097 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
3098 }
3099 if (!ArgXMMs.empty()) {
3100 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
3101 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
3102 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
3103 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
3104 LiveXMMRegs.push_back(
3105 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
3106 }
3107 }
3108
3109 if (IsWin64) {
3110 // Get to the caller-allocated home save location. Add 8 to account
3111 // for the return address.
3112 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
3113 FuncInfo->setRegSaveFrameIndex(
3114 MFI.CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
3115 // Fixup to set vararg frame on shadow area (4 x i64).
3116 if (NumIntRegs < 4)
3117 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
3118 } else {
3119 // For X86-64, if there are vararg parameters that are passed via
3120 // registers, then we must store them to their spots on the stack so
3121 // they may be loaded by dereferencing the result of va_next.
3122 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
3123 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
3124 FuncInfo->setRegSaveFrameIndex(MFI.CreateStackObject(
3125 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
3126 }
3127
3128 // Store the integer parameter registers.
3129 SmallVector<SDValue, 8> MemOps;
3130 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
3131 getPointerTy(DAG.getDataLayout()));
3132 unsigned Offset = FuncInfo->getVarArgsGPOffset();
3133 for (SDValue Val : LiveGPRs) {
3134 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
3135 RSFIN, DAG.getIntPtrConstant(Offset, dl));
3136 SDValue Store =
3137 DAG.getStore(Val.getValue(1), dl, Val, FIN,
3138 MachinePointerInfo::getFixedStack(
3139 DAG.getMachineFunction(),
3140 FuncInfo->getRegSaveFrameIndex(), Offset));
3141 MemOps.push_back(Store);
3142 Offset += 8;
3143 }
3144
3145 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
3146 // Now store the XMM (fp + vector) parameter registers.
3147 SmallVector<SDValue, 12> SaveXMMOps;
3148 SaveXMMOps.push_back(Chain);
3149 SaveXMMOps.push_back(ALVal);
3150 SaveXMMOps.push_back(DAG.getIntPtrConstant(
3151 FuncInfo->getRegSaveFrameIndex(), dl));
3152 SaveXMMOps.push_back(DAG.getIntPtrConstant(
3153 FuncInfo->getVarArgsFPOffset(), dl));
3154 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
3155 LiveXMMRegs.end());
3156 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
3157 MVT::Other, SaveXMMOps));
3158 }
3159
3160 if (!MemOps.empty())
3161 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
3162 }
3163
3164 if (isVarArg && MFI.hasMustTailInVarArgFunc()) {
3165 // Find the largest legal vector type.
3166 MVT VecVT = MVT::Other;
3167 // FIXME: Only some x86_32 calling conventions support AVX512.
3168 if (Subtarget.hasAVX512() &&
3169 (Is64Bit || (CallConv == CallingConv::X86_VectorCall ||
3170 CallConv == CallingConv::Intel_OCL_BI)))
3171 VecVT = MVT::v16f32;
3172 else if (Subtarget.hasAVX())
3173 VecVT = MVT::v8f32;
3174 else if (Subtarget.hasSSE2())
3175 VecVT = MVT::v4f32;
3176
3177 // We forward some GPRs and some vector types.
3178 SmallVector<MVT, 2> RegParmTypes;
3179 MVT IntVT = Is64Bit ? MVT::i64 : MVT::i32;
3180 RegParmTypes.push_back(IntVT);
3181 if (VecVT != MVT::Other)
3182 RegParmTypes.push_back(VecVT);
3183
3184 // Compute the set of forwarded registers. The rest are scratch.
3185 SmallVectorImpl<ForwardedRegister> &Forwards =
3186 FuncInfo->getForwardedMustTailRegParms();
3187 CCInfo.analyzeMustTailForwardedRegisters(Forwards, RegParmTypes, CC_X86);
3188
3189 // Conservatively forward AL on x86_64, since it might be used for varargs.
3190 if (Is64Bit && !CCInfo.isAllocated(X86::AL)) {
3191 unsigned ALVReg = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
3192 Forwards.push_back(ForwardedRegister(ALVReg, X86::AL, MVT::i8));
3193 }
3194
3195 // Copy all forwards from physical to virtual registers.
3196 for (ForwardedRegister &F : Forwards) {
3197 // FIXME: Can we use a less constrained schedule?
3198 SDValue RegVal = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
3199 F.VReg = MF.getRegInfo().createVirtualRegister(getRegClassFor(F.VT));
3200 Chain = DAG.getCopyToReg(Chain, dl, F.VReg, RegVal);
3201 }
3202 }
3203
3204 // Some CCs need callee pop.
3205 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3206 MF.getTarget().Options.GuaranteedTailCallOpt)) {
3207 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
3208 } else if (CallConv == CallingConv::X86_INTR && Ins.size() == 2) {
3209 // X86 interrupts must pop the error code (and the alignment padding) if
3210 // present.
3211 FuncInfo->setBytesToPopOnReturn(Is64Bit ? 16 : 4);
3212 } else {
3213 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
3214 // If this is an sret function, the return should pop the hidden pointer.
3215 if (!Is64Bit && !canGuaranteeTCO(CallConv) &&
3216 !Subtarget.getTargetTriple().isOSMSVCRT() &&
3217 argsAreStructReturn(Ins, Subtarget.isTargetMCU()) == StackStructReturn)
3218 FuncInfo->setBytesToPopOnReturn(4);
3219 }
3220
3221 if (!Is64Bit) {
3222 // RegSaveFrameIndex is X86-64 only.
3223 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
3224 if (CallConv == CallingConv::X86_FastCall ||
3225 CallConv == CallingConv::X86_ThisCall)
3226 // fastcc functions can't have varargs.
3227 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
3228 }
3229
3230 FuncInfo->setArgumentStackSize(StackSize);
3231
3232 if (WinEHFuncInfo *EHInfo = MF.getWinEHFuncInfo()) {
3233 EHPersonality Personality = classifyEHPersonality(Fn->getPersonalityFn());
3234 if (Personality == EHPersonality::CoreCLR) {
3235 assert(Is64Bit)(static_cast <bool> (Is64Bit) ? void (0) : __assert_fail
("Is64Bit", "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 3235, __extension__ __PRETTY_FUNCTION__))
;
3236 // TODO: Add a mechanism to frame lowering that will allow us to indicate
3237 // that we'd prefer this slot be allocated towards the bottom of the frame
3238 // (i.e. near the stack pointer after allocating the frame). Every
3239 // funclet needs a copy of this slot in its (mostly empty) frame, and the
3240 // offset from the bottom of this and each funclet's frame must be the
3241 // same, so the size of funclets' (mostly empty) frames is dictated by
3242 // how far this slot is from the bottom (since they allocate just enough
3243 // space to accommodate holding this slot at the correct offset).
3244 int PSPSymFI = MFI.CreateStackObject(8, 8, /*isSS=*/false);
3245 EHInfo->PSPSymFrameIdx = PSPSymFI;
3246 }
3247 }
3248
3249 if (CallConv == CallingConv::X86_RegCall ||
3250 Fn->hasFnAttribute("no_caller_saved_registers")) {
3251 MachineRegisterInfo &MRI = MF.getRegInfo();
3252 for (std::pair<unsigned, unsigned> Pair : MRI.liveins())
3253 MRI.disableCalleeSavedRegister(Pair.first);
3254 }
3255
3256 return Chain;
3257}
3258
3259SDValue X86TargetLowering::LowerMemOpCallTo(SDValue Chain, SDValue StackPtr,
3260 SDValue Arg, const SDLoc &dl,
3261 SelectionDAG &DAG,
3262 const CCValAssign &VA,
3263 ISD::ArgFlagsTy Flags) const {
3264 unsigned LocMemOffset = VA.getLocMemOffset();
3265 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
3266 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
3267 StackPtr, PtrOff);
3268 if (Flags.isByVal())
3269 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
3270
3271 return DAG.getStore(
3272 Chain, dl, Arg, PtrOff,
3273 MachinePointerInfo::getStack(DAG.getMachineFunction(), LocMemOffset));
3274}
3275
3276/// Emit a load of return address if tail call
3277/// optimization is performed and it is required.
3278SDValue X86TargetLowering::EmitTailCallLoadRetAddr(
3279 SelectionDAG &DAG, SDValue &OutRetAddr, SDValue Chain, bool IsTailCall,
3280 bool Is64Bit, int FPDiff, const SDLoc &dl) const {
3281 // Adjust the Return address stack slot.
3282 EVT VT = getPointerTy(DAG.getDataLayout());
3283 OutRetAddr = getReturnAddressFrameIndex(DAG);
3284
3285 // Load the "old" Return address.
3286 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo());
3287 return SDValue(OutRetAddr.getNode(), 1);
3288}
3289
3290/// Emit a store of the return address if tail call
3291/// optimization is performed and it is required (FPDiff!=0).
3292static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
3293 SDValue Chain, SDValue RetAddrFrIdx,
3294 EVT PtrVT, unsigned SlotSize,
3295 int FPDiff, const SDLoc &dl) {
3296 // Store the return address to the appropriate stack slot.
3297 if (!FPDiff) return Chain;
3298 // Calculate the new stack slot for the return address.
3299 int NewReturnAddrFI =
3300 MF.getFrameInfo().CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
3301 false);
3302 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
3303 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
3304 MachinePointerInfo::getFixedStack(
3305 DAG.getMachineFunction(), NewReturnAddrFI));
3306 return Chain;
3307}
3308
3309/// Returns a vector_shuffle mask for an movs{s|d}, movd
3310/// operation of specified width.
3311static SDValue getMOVL(SelectionDAG &DAG, const SDLoc &dl, MVT VT, SDValue V1,
3312 SDValue V2) {
3313 unsigned NumElems = VT.getVectorNumElements();
3314 SmallVector<int, 8> Mask;
3315 Mask.push_back(NumElems);
3316 for (unsigned i = 1; i != NumElems; ++i)
3317 Mask.push_back(i);
3318 return DAG.getVectorShuffle(VT, dl, V1, V2, Mask);
3319}
3320
3321SDValue
3322X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
3323 SmallVectorImpl<SDValue> &InVals) const {
3324 SelectionDAG &DAG = CLI.DAG;
3325 SDLoc &dl = CLI.DL;
3326 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
3327 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
3328 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
3329 SDValue Chain = CLI.Chain;
3330 SDValue Callee = CLI.Callee;
3331 CallingConv::ID CallConv = CLI.CallConv;
3332 bool &isTailCall = CLI.IsTailCall;
3333 bool isVarArg = CLI.IsVarArg;
3334
3335 MachineFunction &MF = DAG.getMachineFunction();
3336 bool Is64Bit = Subtarget.is64Bit();
3337 bool IsWin64 = Subtarget.isCallingConvWin64(CallConv);
3338 StructReturnType SR = callIsStructReturn(Outs, Subtarget.isTargetMCU());
3339 bool IsSibcall = false;
3340 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
3341 auto Attr = MF.getFunction()->getFnAttribute("disable-tail-calls");
3342 const auto *CI = dyn_cast_or_null<CallInst>(CLI.CS.getInstruction());
3343 const Function *Fn = CI ? CI->getCalledFunction() : nullptr;
3344 bool HasNCSR = (CI && CI->hasFnAttr("no_caller_saved_registers")) ||
3345 (Fn && Fn->hasFnAttribute("no_caller_saved_registers"));
3346
3347 if (CallConv == CallingConv::X86_INTR)
3348 report_fatal_error("X86 interrupts may not be called directly");
3349
3350 if (Attr.getValueAsString() == "true")
3351 isTailCall = false;
3352
3353 if (Subtarget.isPICStyleGOT() &&
3354 !MF.getTarget().Options.GuaranteedTailCallOpt) {
3355 // If we are using a GOT, disable tail calls to external symbols with
3356 // default visibility. Tail calling such a symbol requires using a GOT
3357 // relocation, which forces early binding of the symbol. This breaks code
3358 // that require lazy function symbol resolution. Using musttail or
3359 // GuaranteedTailCallOpt will override this.
3360 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
3361 if (!G || (!G->getGlobal()->hasLocalLinkage() &&
3362 G->getGlobal()->hasDefaultVisibility()))
3363 isTailCall = false;
3364 }
3365
3366 bool IsMustTail = CLI.CS && CLI.CS.isMustTailCall();
3367 if (IsMustTail) {
3368 // Force this to be a tail call. The verifier rules are enough to ensure
3369 // that we can lower this successfully without moving the return address
3370 // around.
3371 isTailCall = true;
3372 } else if (isTailCall) {
3373 // Check if it's really possible to do a tail call.
3374 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
3375 isVarArg, SR != NotStructReturn,
3376 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
3377 Outs, OutVals, Ins, DAG);
3378
3379 // Sibcalls are automatically detected tailcalls which do not require
3380 // ABI changes.
3381 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
3382 IsSibcall = true;
3383
3384 if (isTailCall)
3385 ++NumTailCalls;
3386 }
3387
3388 assert(!(isVarArg && canGuaranteeTCO(CallConv)) &&(static_cast <bool> (!(isVarArg && canGuaranteeTCO
(CallConv)) && "Var args not supported with calling convention fastcc, ghc or hipe"
) ? void (0) : __assert_fail ("!(isVarArg && canGuaranteeTCO(CallConv)) && \"Var args not supported with calling convention fastcc, ghc or hipe\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 3389, __extension__ __PRETTY_FUNCTION__))
3389 "Var args not supported with calling convention fastcc, ghc or hipe")(static_cast <bool> (!(isVarArg && canGuaranteeTCO
(CallConv)) && "Var args not supported with calling convention fastcc, ghc or hipe"
) ? void (0) : __assert_fail ("!(isVarArg && canGuaranteeTCO(CallConv)) && \"Var args not supported with calling convention fastcc, ghc or hipe\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 3389, __extension__ __PRETTY_FUNCTION__))
;
3390
3391 // Analyze operands of the call, assigning locations to each operand.
3392 SmallVector<CCValAssign, 16> ArgLocs;
3393 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
3394
3395 // Allocate shadow area for Win64.
3396 if (IsWin64)
3397 CCInfo.AllocateStack(32, 8);
3398
3399 CCInfo.AnalyzeArguments(Outs, CC_X86);
3400
3401 // In vectorcall calling convention a second pass is required for the HVA
3402 // types.
3403 if (CallingConv::X86_VectorCall == CallConv) {
3404 CCInfo.AnalyzeArgumentsSecondPass(Outs, CC_X86);
3405 }
3406
3407 // Get a count of how many bytes are to be pushed on the stack.
3408 unsigned NumBytes = CCInfo.getAlignedCallFrameSize();
3409 if (IsSibcall)
3410 // This is a sibcall. The memory operands are available in caller's
3411 // own caller's stack.
3412 NumBytes = 0;
3413 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
3414 canGuaranteeTCO(CallConv))
3415 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
3416
3417 int FPDiff = 0;
3418 if (isTailCall && !IsSibcall && !IsMustTail) {
3419 // Lower arguments at fp - stackoffset + fpdiff.
3420 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
3421
3422 FPDiff = NumBytesCallerPushed - NumBytes;
3423
3424 // Set the delta of movement of the returnaddr stackslot.
3425 // But only set if delta is greater than previous delta.
3426 if (FPDiff < X86Info->getTCReturnAddrDelta())
3427 X86Info->setTCReturnAddrDelta(FPDiff);
3428 }
3429
3430 unsigned NumBytesToPush = NumBytes;
3431 unsigned NumBytesToPop = NumBytes;
3432
3433 // If we have an inalloca argument, all stack space has already been allocated
3434 // for us and be right at the top of the stack. We don't support multiple
3435 // arguments passed in memory when using inalloca.
3436 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
3437 NumBytesToPush = 0;
3438 if (!ArgLocs.back().isMemLoc())
3439 report_fatal_error("cannot use inalloca attribute on a register "
3440 "parameter");
3441 if (ArgLocs.back().getLocMemOffset() != 0)
3442 report_fatal_error("any parameter with the inalloca attribute must be "
3443 "the only memory argument");
3444 }
3445
3446 if (!IsSibcall)
3447 Chain = DAG.getCALLSEQ_START(Chain, NumBytesToPush,
3448 NumBytes - NumBytesToPush, dl);
3449
3450 SDValue RetAddrFrIdx;
3451 // Load return address for tail calls.
3452 if (isTailCall && FPDiff)
3453 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
3454 Is64Bit, FPDiff, dl);
3455
3456 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
3457 SmallVector<SDValue, 8> MemOpChains;
3458 SDValue StackPtr;
3459
3460 // The next loop assumes that the locations are in the same order of the
3461 // input arguments.
3462 assert(isSortedByValueNo(ArgLocs) &&(static_cast <bool> (isSortedByValueNo(ArgLocs) &&
"Argument Location list must be sorted before lowering") ? void
(0) : __assert_fail ("isSortedByValueNo(ArgLocs) && \"Argument Location list must be sorted before lowering\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 3463, __extension__ __PRETTY_FUNCTION__))
3463 "Argument Location list must be sorted before lowering")(static_cast <bool> (isSortedByValueNo(ArgLocs) &&
"Argument Location list must be sorted before lowering") ? void
(0) : __assert_fail ("isSortedByValueNo(ArgLocs) && \"Argument Location list must be sorted before lowering\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 3463, __extension__ __PRETTY_FUNCTION__))
;
3464
3465 // Walk the register/memloc assignments, inserting copies/loads. In the case
3466 // of tail call optimization arguments are handle later.
3467 const X86RegisterInfo *RegInfo = Subtarget.getRegisterInfo();
3468 for (unsigned I = 0, OutIndex = 0, E = ArgLocs.size(); I != E;
3469 ++I, ++OutIndex) {
3470 assert(OutIndex < Outs.size() && "Invalid Out index")(static_cast <bool> (OutIndex < Outs.size() &&
"Invalid Out index") ? void (0) : __assert_fail ("OutIndex < Outs.size() && \"Invalid Out index\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 3470, __extension__ __PRETTY_FUNCTION__))
;
3471 // Skip inalloca arguments, they have already been written.
3472 ISD::ArgFlagsTy Flags = Outs[OutIndex].Flags;
3473 if (Flags.isInAlloca())
3474 continue;
3475
3476 CCValAssign &VA = ArgLocs[I];
3477 EVT RegVT = VA.getLocVT();
3478 SDValue Arg = OutVals[OutIndex];
3479 bool isByVal = Flags.isByVal();
3480
3481 // Promote the value if needed.
3482 switch (VA.getLocInfo()) {
3483 default: llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 3483)
;
3484 case CCValAssign::Full: break;
3485 case CCValAssign::SExt:
3486 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
3487 break;
3488 case CCValAssign::ZExt:
3489 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
3490 break;
3491 case CCValAssign::AExt:
3492 if (Arg.getValueType().isVector() &&
3493 Arg.getValueType().getVectorElementType() == MVT::i1)
3494 Arg = lowerMasksToReg(Arg, RegVT, dl, DAG);
3495 else if (RegVT.is128BitVector()) {
3496 // Special case: passing MMX values in XMM registers.
3497 Arg = DAG.getBitcast(MVT::i64, Arg);
3498 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
3499 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
3500 } else
3501 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
3502 break;
3503 case CCValAssign::BCvt:
3504 Arg = DAG.getBitcast(RegVT, Arg);
3505 break;
3506 case CCValAssign::Indirect: {
3507 // Store the argument.
3508 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
3509 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
3510 Chain = DAG.getStore(
3511 Chain, dl, Arg, SpillSlot,
3512 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI));
3513 Arg = SpillSlot;
3514 break;
3515 }
3516 }
3517
3518 if (VA.needsCustom()) {
3519 assert(VA.getValVT() == MVT::v64i1 &&(static_cast <bool> (VA.getValVT() == MVT::v64i1 &&
"Currently the only custom case is when we split v64i1 to 2 regs"
) ? void (0) : __assert_fail ("VA.getValVT() == MVT::v64i1 && \"Currently the only custom case is when we split v64i1 to 2 regs\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 3520, __extension__ __PRETTY_FUNCTION__))
3520 "Currently the only custom case is when we split v64i1 to 2 regs")(static_cast <bool> (VA.getValVT() == MVT::v64i1 &&
"Currently the only custom case is when we split v64i1 to 2 regs"
) ? void (0) : __assert_fail ("VA.getValVT() == MVT::v64i1 && \"Currently the only custom case is when we split v64i1 to 2 regs\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 3520, __extension__ __PRETTY_FUNCTION__))
;
3521 // Split v64i1 value into two registers
3522 Passv64i1ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++I],
3523 Subtarget);
3524 } else if (VA.isRegLoc()) {
3525 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
3526 if (isVarArg && IsWin64) {
3527 // Win64 ABI requires argument XMM reg to be copied to the corresponding
3528 // shadow reg if callee is a varargs function.
3529 unsigned ShadowReg = 0;
3530 switch (VA.getLocReg()) {
3531 case X86::XMM0: ShadowReg = X86::RCX; break;
3532 case X86::XMM1: ShadowReg = X86::RDX; break;
3533 case X86::XMM2: ShadowReg = X86::R8; break;
3534 case X86::XMM3: ShadowReg = X86::R9; break;
3535 }
3536 if (ShadowReg)
3537 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
3538 }
3539 } else if (!IsSibcall && (!isTailCall || isByVal)) {
3540 assert(VA.isMemLoc())(static_cast <bool> (VA.isMemLoc()) ? void (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 3540, __extension__ __PRETTY_FUNCTION__))
;
3541 if (!StackPtr.getNode())
3542 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
3543 getPointerTy(DAG.getDataLayout()));
3544 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
3545 dl, DAG, VA, Flags));
3546 }
3547 }
3548
3549 if (!MemOpChains.empty())
3550 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
3551
3552 if (Subtarget.isPICStyleGOT()) {
3553 // ELF / PIC requires GOT in the EBX register before function calls via PLT
3554 // GOT pointer.
3555 if (!isTailCall) {
3556 RegsToPass.push_back(std::make_pair(
3557 unsigned(X86::EBX), DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(),
3558 getPointerTy(DAG.getDataLayout()))));
3559 } else {
3560 // If we are tail calling and generating PIC/GOT style code load the
3561 // address of the callee into ECX. The value in ecx is used as target of
3562 // the tail jump. This is done to circumvent the ebx/callee-saved problem
3563 // for tail calls on PIC/GOT architectures. Normally we would just put the
3564 // address of GOT into ebx and then call target@PLT. But for tail calls
3565 // ebx would be restored (since ebx is callee saved) before jumping to the
3566 // target@PLT.
3567
3568 // Note: The actual moving to ECX is done further down.
3569 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
3570 if (G && !G->getGlobal()->hasLocalLinkage() &&
3571 G->getGlobal()->hasDefaultVisibility())
3572 Callee = LowerGlobalAddress(Callee, DAG);
3573 else if (isa<ExternalSymbolSDNode>(Callee))
3574 Callee = LowerExternalSymbol(Callee, DAG);
3575 }
3576 }
3577
3578 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
3579 // From AMD64 ABI document:
3580 // For calls that may call functions that use varargs or stdargs
3581 // (prototype-less calls or calls to functions containing ellipsis (...) in
3582 // the declaration) %al is used as hidden argument to specify the number
3583 // of SSE registers used. The contents of %al do not need to match exactly
3584 // the number of registers, but must be an ubound on the number of SSE
3585 // registers used and is in the range 0 - 8 inclusive.
3586
3587 // Count the number of XMM registers allocated.
3588 static const MCPhysReg XMMArgRegs[] = {
3589 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
3590 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
3591 };
3592 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs);
3593 assert((Subtarget.hasSSE1() || !NumXMMRegs)(static_cast <bool> ((Subtarget.hasSSE1() || !NumXMMRegs
) && "SSE registers cannot be used when SSE is disabled"
) ? void (0) : __assert_fail ("(Subtarget.hasSSE1() || !NumXMMRegs) && \"SSE registers cannot be used when SSE is disabled\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 3594, __extension__ __PRETTY_FUNCTION__))
3594 && "SSE registers cannot be used when SSE is disabled")(static_cast <bool> ((Subtarget.hasSSE1() || !NumXMMRegs
) && "SSE registers cannot be used when SSE is disabled"
) ? void (0) : __assert_fail ("(Subtarget.hasSSE1() || !NumXMMRegs) && \"SSE registers cannot be used when SSE is disabled\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 3594, __extension__ __PRETTY_FUNCTION__))
;
3595
3596 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
3597 DAG.getConstant(NumXMMRegs, dl,
3598 MVT::i8)));
3599 }
3600
3601 if (isVarArg && IsMustTail) {
3602 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
3603 for (const auto &F : Forwards) {
3604 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
3605 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
3606 }
3607 }
3608
3609 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
3610 // don't need this because the eligibility check rejects calls that require
3611 // shuffling arguments passed in memory.
3612 if (!IsSibcall && isTailCall) {
3613 // Force all the incoming stack arguments to be loaded from the stack
3614 // before any new outgoing arguments are stored to the stack, because the
3615 // outgoing stack slots may alias the incoming argument stack slots, and
3616 // the alias isn't otherwise explicit. This is slightly more conservative
3617 // than necessary, because it means that each store effectively depends
3618 // on every argument instead of just those arguments it would clobber.
3619 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
3620
3621 SmallVector<SDValue, 8> MemOpChains2;
3622 SDValue FIN;
3623 int FI = 0;
3624 for (unsigned I = 0, OutsIndex = 0, E = ArgLocs.size(); I != E;
3625 ++I, ++OutsIndex) {
3626 CCValAssign &VA = ArgLocs[I];
3627
3628 if (VA.isRegLoc()) {
3629 if (VA.needsCustom()) {
3630 assert((CallConv == CallingConv::X86_RegCall) &&(static_cast <bool> ((CallConv == CallingConv::X86_RegCall
) && "Expecting custom case only in regcall calling convention"
) ? void (0) : __assert_fail ("(CallConv == CallingConv::X86_RegCall) && \"Expecting custom case only in regcall calling convention\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 3631, __extension__ __PRETTY_FUNCTION__))
3631 "Expecting custom case only in regcall calling convention")(static_cast <bool> ((CallConv == CallingConv::X86_RegCall
) && "Expecting custom case only in regcall calling convention"
) ? void (0) : __assert_fail ("(CallConv == CallingConv::X86_RegCall) && \"Expecting custom case only in regcall calling convention\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 3631, __extension__ __PRETTY_FUNCTION__))
;
3632 // This means that we are in special case where one argument was
3633 // passed through two register locations - Skip the next location
3634 ++I;
3635 }
3636
3637 continue;
3638 }
3639
3640 assert(VA.isMemLoc())(static_cast <bool> (VA.isMemLoc()) ? void (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 3640, __extension__ __PRETTY_FUNCTION__))
;
3641 SDValue Arg = OutVals[OutsIndex];
3642 ISD::ArgFlagsTy Flags = Outs[OutsIndex].Flags;
3643 // Skip inalloca arguments. They don't require any work.
3644 if (Flags.isInAlloca())
3645 continue;
3646 // Create frame index.
3647 int32_t Offset = VA.getLocMemOffset()+FPDiff;
3648 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
3649 FI = MF.getFrameInfo().CreateFixedObject(OpSize, Offset, true);
3650 FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
3651
3652 if (Flags.isByVal()) {
3653 // Copy relative to framepointer.
3654 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset(), dl);
3655 if (!StackPtr.getNode())
3656 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
3657 getPointerTy(DAG.getDataLayout()));
3658 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
3659 StackPtr, Source);
3660
3661 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3662 ArgChain,
3663 Flags, DAG, dl));
3664 } else {
3665 // Store relative to framepointer.
3666 MemOpChains2.push_back(DAG.getStore(
3667 ArgChain, dl, Arg, FIN,
3668 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI)));
3669 }
3670 }
3671
3672 if (!MemOpChains2.empty())
3673 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3674
3675 // Store the return address to the appropriate stack slot.
3676 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3677 getPointerTy(DAG.getDataLayout()),
3678 RegInfo->getSlotSize(), FPDiff, dl);
3679 }
3680
3681 // Build a sequence of copy-to-reg nodes chained together with token chain
3682 // and flag operands which copy the outgoing args into registers.
3683 SDValue InFlag;
3684 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3685 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3686 RegsToPass[i].second, InFlag);
3687 InFlag = Chain.getValue(1);
3688 }
3689
3690 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3691 assert(Is64Bit && "Large code model is only legal in 64-bit mode.")(static_cast <bool> (Is64Bit && "Large code model is only legal in 64-bit mode."
) ? void (0) : __assert_fail ("Is64Bit && \"Large code model is only legal in 64-bit mode.\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 3691, __extension__ __PRETTY_FUNCTION__))
;
3692 // In the 64-bit large code model, we have to make all calls
3693 // through a register, since the call instruction's 32-bit
3694 // pc-relative offset may not be large enough to hold the whole
3695 // address.
3696 } else if (Callee->getOpcode() == ISD::GlobalAddress) {
3697 // If the callee is a GlobalAddress node (quite common, every direct call
3698 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3699 // it.
3700 GlobalAddressSDNode* G = cast<GlobalAddressSDNode>(Callee);
3701
3702 // We should use extra load for direct calls to dllimported functions in
3703 // non-JIT mode.
3704 const GlobalValue *GV = G->getGlobal();
3705 if (!GV->hasDLLImportStorageClass()) {
3706 unsigned char OpFlags = Subtarget.classifyGlobalFunctionReference(GV);
3707
3708 Callee = DAG.getTargetGlobalAddress(
3709 GV, dl, getPointerTy(DAG.getDataLayout()), G->getOffset(), OpFlags);
3710
3711 if (OpFlags == X86II::MO_GOTPCREL) {
3712 // Add a wrapper.
3713 Callee = DAG.getNode(X86ISD::WrapperRIP, dl,
3714 getPointerTy(DAG.getDataLayout()), Callee);
3715 // Add extra indirection
3716 Callee = DAG.getLoad(
3717 getPointerTy(DAG.getDataLayout()), dl, DAG.getEntryNode(), Callee,
3718 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
3719 }
3720 }
3721 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3722 const Module *Mod = DAG.getMachineFunction().getFunction()->getParent();
3723 unsigned char OpFlags =
3724 Subtarget.classifyGlobalFunctionReference(nullptr, *Mod);
3725
3726 Callee = DAG.getTargetExternalSymbol(
3727 S->getSymbol(), getPointerTy(DAG.getDataLayout()), OpFlags);
3728 } else if (Subtarget.isTarget64BitILP32() &&
3729 Callee->getValueType(0) == MVT::i32) {
3730 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3731 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3732 }
3733
3734 // Returns a chain & a flag for retval copy to use.
3735 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3736 SmallVector<SDValue, 8> Ops;
3737
3738 if (!IsSibcall && isTailCall) {
3739 Chain = DAG.getCALLSEQ_END(Chain,
3740 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
3741 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
3742 InFlag = Chain.getValue(1);
3743 }
3744
3745 Ops.push_back(Chain);
3746 Ops.push_back(Callee);
3747
3748 if (isTailCall)
3749 Ops.push_back(DAG.getConstant(FPDiff, dl, MVT::i32));
3750
3751 // Add argument registers to the end of the list so that they are known live
3752 // into the call.
3753 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3754 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3755 RegsToPass[i].second.getValueType()));
3756
3757 // Add a register mask operand representing the call-preserved registers.
3758 // If HasNCSR is asserted (attribute NoCallerSavedRegisters exists) then we
3759 // set X86_INTR calling convention because it has the same CSR mask
3760 // (same preserved registers).
3761 const uint32_t *Mask = RegInfo->getCallPreservedMask(
3762 MF, HasNCSR ? (CallingConv::ID)CallingConv::X86_INTR : CallConv);
3763 assert(Mask && "Missing call preserved mask for calling convention")(static_cast <bool> (Mask && "Missing call preserved mask for calling convention"
) ? void (0) : __assert_fail ("Mask && \"Missing call preserved mask for calling convention\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 3763, __extension__ __PRETTY_FUNCTION__))
;
3764
3765 // If this is an invoke in a 32-bit function using a funclet-based
3766 // personality, assume the function clobbers all registers. If an exception
3767 // is thrown, the runtime will not restore CSRs.
3768 // FIXME: Model this more precisely so that we can register allocate across
3769 // the normal edge and spill and fill across the exceptional edge.
3770 if (!Is64Bit && CLI.CS && CLI.CS.isInvoke()) {
3771 const Function *CallerFn = MF.getFunction();
3772 EHPersonality Pers =
3773 CallerFn->hasPersonalityFn()
3774 ? classifyEHPersonality(CallerFn->getPersonalityFn())
3775 : EHPersonality::Unknown;
3776 if (isFuncletEHPersonality(Pers))
3777 Mask = RegInfo->getNoPreservedMask();
3778 }
3779
3780 // Define a new register mask from the existing mask.
3781 uint32_t *RegMask = nullptr;
3782
3783 // In some calling conventions we need to remove the used physical registers
3784 // from the reg mask.
3785 if (CallConv == CallingConv::X86_RegCall || HasNCSR) {
3786 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
3787
3788 // Allocate a new Reg Mask and copy Mask.
3789 RegMask = MF.allocateRegisterMask(TRI->getNumRegs());
3790 unsigned RegMaskSize = (TRI->getNumRegs() + 31) / 32;
3791 memcpy(RegMask, Mask, sizeof(uint32_t) * RegMaskSize);
3792
3793 // Make sure all sub registers of the argument registers are reset
3794 // in the RegMask.
3795 for (auto const &RegPair : RegsToPass)
3796 for (MCSubRegIterator SubRegs(RegPair.first, TRI, /*IncludeSelf=*/true);
3797 SubRegs.isValid(); ++SubRegs)
3798 RegMask[*SubRegs / 32] &= ~(1u << (*SubRegs % 32));
3799
3800 // Create the RegMask Operand according to our updated mask.
3801 Ops.push_back(DAG.getRegisterMask(RegMask));
3802 } else {
3803 // Create the RegMask Operand according to the static mask.
3804 Ops.push_back(DAG.getRegisterMask(Mask));
3805 }
3806
3807 if (InFlag.getNode())
3808 Ops.push_back(InFlag);
3809
3810 if (isTailCall) {
3811 // We used to do:
3812 //// If this is the first return lowered for this function, add the regs
3813 //// to the liveout set for the function.
3814 // This isn't right, although it's probably harmless on x86; liveouts
3815 // should be computed from returns not tail calls. Consider a void
3816 // function making a tail call to a function returning int.
3817 MF.getFrameInfo().setHasTailCall();
3818 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3819 }
3820
3821 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3822 InFlag = Chain.getValue(1);
3823
3824 // Create the CALLSEQ_END node.
3825 unsigned NumBytesForCalleeToPop;
3826 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3827 DAG.getTarget().Options.GuaranteedTailCallOpt))
3828 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3829 else if (!Is64Bit && !canGuaranteeTCO(CallConv) &&
3830 !Subtarget.getTargetTriple().isOSMSVCRT() &&
3831 SR == StackStructReturn)
3832 // If this is a call to a struct-return function, the callee
3833 // pops the hidden struct pointer, so we have to push it back.
3834 // This is common for Darwin/X86, Linux & Mingw32 targets.
3835 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3836 NumBytesForCalleeToPop = 4;
3837 else
3838 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3839
3840 if (CLI.DoesNotReturn && !getTargetMachine().Options.TrapUnreachable) {
3841 // No need to reset the stack after the call if the call doesn't return. To
3842 // make the MI verify, we'll pretend the callee does it for us.
3843 NumBytesForCalleeToPop = NumBytes;
3844 }
3845
3846 // Returns a flag for retval copy to use.
3847 if (!IsSibcall) {
3848 Chain = DAG.getCALLSEQ_END(Chain,
3849 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
3850 DAG.getIntPtrConstant(NumBytesForCalleeToPop, dl,
3851 true),
3852 InFlag, dl);
3853 InFlag = Chain.getValue(1);
3854 }
3855
3856 // Handle result values, copying them out of physregs into vregs that we
3857 // return.
3858 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl, DAG,
3859 InVals, RegMask);
3860}
3861
3862//===----------------------------------------------------------------------===//
3863// Fast Calling Convention (tail call) implementation
3864//===----------------------------------------------------------------------===//
3865
3866// Like std call, callee cleans arguments, convention except that ECX is
3867// reserved for storing the tail called function address. Only 2 registers are
3868// free for argument passing (inreg). Tail call optimization is performed
3869// provided:
3870// * tailcallopt is enabled
3871// * caller/callee are fastcc
3872// On X86_64 architecture with GOT-style position independent code only local
3873// (within module) calls are supported at the moment.
3874// To keep the stack aligned according to platform abi the function
3875// GetAlignedArgumentStackSize ensures that argument delta is always multiples
3876// of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3877// If a tail called function callee has more arguments than the caller the
3878// caller needs to make sure that there is room to move the RETADDR to. This is
3879// achieved by reserving an area the size of the argument delta right after the
3880// original RETADDR, but before the saved framepointer or the spilled registers
3881// e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3882// stack layout:
3883// arg1
3884// arg2
3885// RETADDR
3886// [ new RETADDR
3887// move area ]
3888// (possible EBP)
3889// ESI
3890// EDI
3891// local1 ..
3892
3893/// Make the stack size align e.g 16n + 12 aligned for a 16-byte align
3894/// requirement.
3895unsigned
3896X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3897 SelectionDAG& DAG) const {
3898 const X86RegisterInfo *RegInfo = Subtarget.getRegisterInfo();
3899 const TargetFrameLowering &TFI = *Subtarget.getFrameLowering();
3900 unsigned StackAlignment = TFI.getStackAlignment();
3901 uint64_t AlignMask = StackAlignment - 1;
3902 int64_t Offset = StackSize;
3903 unsigned SlotSize = RegInfo->getSlotSize();
3904 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3905 // Number smaller than 12 so just add the difference.
3906 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3907 } else {
3908 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3909 Offset = ((~AlignMask) & Offset) + StackAlignment +
3910 (StackAlignment-SlotSize);
3911 }
3912 return Offset;
3913}
3914
3915/// Return true if the given stack call argument is already available in the
3916/// same position (relatively) of the caller's incoming argument stack.
3917static
3918bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3919 MachineFrameInfo &MFI, const MachineRegisterInfo *MRI,
3920 const X86InstrInfo *TII, const CCValAssign &VA) {
3921 unsigned Bytes = Arg.getValueSizeInBits() / 8;
3922
3923 for (;;) {
3924 // Look through nodes that don't alter the bits of the incoming value.
3925 unsigned Op = Arg.getOpcode();
3926 if (Op == ISD::ZERO_EXTEND || Op == ISD::ANY_EXTEND || Op == ISD::BITCAST) {
3927 Arg = Arg.getOperand(0);
3928 continue;
3929 }
3930 if (Op == ISD::TRUNCATE) {
3931 const SDValue &TruncInput = Arg.getOperand(0);
3932 if (TruncInput.getOpcode() == ISD::AssertZext &&
3933 cast<VTSDNode>(TruncInput.getOperand(1))->getVT() ==
3934 Arg.getValueType()) {
3935 Arg = TruncInput.getOperand(0);
3936 continue;
3937 }
3938 }
3939 break;
3940 }
3941
3942 int FI = INT_MAX2147483647;
3943 if (Arg.getOpcode() == ISD::CopyFromReg) {
3944 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3945 if (!TargetRegisterInfo::isVirtualRegister(VR))
3946 return false;
3947 MachineInstr *Def = MRI->getVRegDef(VR);
3948 if (!Def)
3949 return false;
3950 if (!Flags.isByVal()) {
3951 if (!TII->isLoadFromStackSlot(*Def, FI))
3952 return false;
3953 } else {
3954 unsigned Opcode = Def->getOpcode();
3955 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r ||
3956 Opcode == X86::LEA64_32r) &&
3957 Def->getOperand(1).isFI()) {
3958 FI = Def->getOperand(1).getIndex();
3959 Bytes = Flags.getByValSize();
3960 } else
3961 return false;
3962 }
3963 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3964 if (Flags.isByVal())
3965 // ByVal argument is passed in as a pointer but it's now being
3966 // dereferenced. e.g.
3967 // define @foo(%struct.X* %A) {
3968 // tail call @bar(%struct.X* byval %A)
3969 // }
3970 return false;
3971 SDValue Ptr = Ld->getBasePtr();
3972 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3973 if (!FINode)
3974 return false;
3975 FI = FINode->getIndex();
3976 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3977 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3978 FI = FINode->getIndex();
3979 Bytes = Flags.getByValSize();
3980 } else
3981 return false;
3982
3983 assert(FI != INT_MAX)(static_cast <bool> (FI != 2147483647) ? void (0) : __assert_fail
("FI != INT_MAX", "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 3983, __extension__ __PRETTY_FUNCTION__))
;
3984 if (!MFI.isFixedObjectIndex(FI))
3985 return false;
3986
3987 if (Offset != MFI.getObjectOffset(FI))
3988 return false;
3989
3990 // If this is not byval, check that the argument stack object is immutable.
3991 // inalloca and argument copy elision can create mutable argument stack
3992 // objects. Byval objects can be mutated, but a byval call intends to pass the
3993 // mutated memory.
3994 if (!Flags.isByVal() && !MFI.isImmutableObjectIndex(FI))
3995 return false;
3996
3997 if (VA.getLocVT().getSizeInBits() > Arg.getValueSizeInBits()) {
3998 // If the argument location is wider than the argument type, check that any
3999 // extension flags match.
4000 if (Flags.isZExt() != MFI.isObjectZExt(FI) ||
4001 Flags.isSExt() != MFI.isObjectSExt(FI)) {
4002 return false;
4003 }
4004 }
4005
4006 return Bytes == MFI.getObjectSize(FI);
4007}
4008
4009/// Check whether the call is eligible for tail call optimization. Targets
4010/// that want to do tail call optimization should implement this function.
4011bool X86TargetLowering::IsEligibleForTailCallOptimization(
4012 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
4013 bool isCalleeStructRet, bool isCallerStructRet, Type *RetTy,
4014 const SmallVectorImpl<ISD::OutputArg> &Outs,
4015 const SmallVectorImpl<SDValue> &OutVals,
4016 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const {
4017 if (!mayTailCallThisCC(CalleeCC))
4018 return false;
4019
4020 // If -tailcallopt is specified, make fastcc functions tail-callable.
4021 MachineFunction &MF = DAG.getMachineFunction();
4022 const Function *CallerF = MF.getFunction();
4023
4024 // If the function return type is x86_fp80 and the callee return type is not,
4025 // then the FP_EXTEND of the call result is not a nop. It's not safe to
4026 // perform a tailcall optimization here.
4027 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
4028 return false;
4029
4030 CallingConv::ID CallerCC = CallerF->getCallingConv();
4031 bool CCMatch = CallerCC == CalleeCC;
4032 bool IsCalleeWin64 = Subtarget.isCallingConvWin64(CalleeCC);
4033 bool IsCallerWin64 = Subtarget.isCallingConvWin64(CallerCC);
4034
4035 // Win64 functions have extra shadow space for argument homing. Don't do the
4036 // sibcall if the caller and callee have mismatched expectations for this
4037 // space.
4038 if (IsCalleeWin64 != IsCallerWin64)
4039 return false;
4040
4041 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
4042 if (canGuaranteeTCO(CalleeCC) && CCMatch)
4043 return true;
4044 return false;
4045 }
4046
4047 // Look for obvious safe cases to perform tail call optimization that do not
4048 // require ABI changes. This is what gcc calls sibcall.
4049
4050 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
4051 // emit a special epilogue.
4052 const X86RegisterInfo *RegInfo = Subtarget.getRegisterInfo();
4053 if (RegInfo->needsStackRealignment(MF))
4054 return false;
4055
4056 // Also avoid sibcall optimization if either caller or callee uses struct
4057 // return semantics.
4058 if (isCalleeStructRet || isCallerStructRet)
4059 return false;
4060
4061 // Do not sibcall optimize vararg calls unless all arguments are passed via
4062 // registers.
4063 LLVMContext &C = *DAG.getContext();
4064 if (isVarArg && !Outs.empty()) {
4065 // Optimizing for varargs on Win64 is unlikely to be safe without
4066 // additional testing.
4067 if (IsCalleeWin64 || IsCallerWin64)
4068 return false;
4069
4070 SmallVector<CCValAssign, 16> ArgLocs;
4071 CCState CCInfo(CalleeCC, isVarArg, MF, ArgLocs, C);
4072
4073 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
4074 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
4075 if (!ArgLocs[i].isRegLoc())
4076 return false;
4077 }
4078
4079 // If the call result is in ST0 / ST1, it needs to be popped off the x87
4080 // stack. Therefore, if it's not used by the call it is not safe to optimize
4081 // this into a sibcall.
4082 bool Unused = false;
4083 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
4084 if (!Ins[i].Used) {
4085 Unused = true;
4086 break;
4087 }
4088 }
4089 if (Unused) {
4090 SmallVector<CCValAssign, 16> RVLocs;
4091 CCState CCInfo(CalleeCC, false, MF, RVLocs, C);
4092 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
4093 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
4094 CCValAssign &VA = RVLocs[i];
4095 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
4096 return false;
4097 }
4098 }
4099
4100 // Check that the call results are passed in the same way.
4101 if (!CCState::resultsCompatible(CalleeCC, CallerCC, MF, C, Ins,
4102 RetCC_X86, RetCC_X86))
4103 return false;
4104 // The callee has to preserve all registers the caller needs to preserve.
4105 const X86RegisterInfo *TRI = Subtarget.getRegisterInfo();
4106 const uint32_t *CallerPreserved = TRI->getCallPreservedMask(MF, CallerCC);
4107 if (!CCMatch) {
4108 const uint32_t *CalleePreserved = TRI->getCallPreservedMask(MF, CalleeCC);
4109 if (!TRI->regmaskSubsetEqual(CallerPreserved, CalleePreserved))
4110 return false;
4111 }
4112
4113 unsigned StackArgsSize = 0;
4114
4115 // If the callee takes no arguments then go on to check the results of the
4116 // call.
4117 if (!Outs.empty()) {
4118 // Check if stack adjustment is needed. For now, do not do this if any
4119 // argument is passed on the stack.
4120 SmallVector<CCValAssign, 16> ArgLocs;
4121 CCState CCInfo(CalleeCC, isVarArg, MF, ArgLocs, C);
4122
4123 // Allocate shadow area for Win64
4124 if (IsCalleeWin64)
4125 CCInfo.AllocateStack(32, 8);
4126
4127 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
4128 StackArgsSize = CCInfo.getNextStackOffset();
4129
4130 if (CCInfo.getNextStackOffset()) {
4131 // Check if the arguments are already laid out in the right way as
4132 // the caller's fixed stack objects.
4133 MachineFrameInfo &MFI = MF.getFrameInfo();
4134 const MachineRegisterInfo *MRI = &MF.getRegInfo();
4135 const X86InstrInfo *TII = Subtarget.getInstrInfo();
4136 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
4137 CCValAssign &VA = ArgLocs[i];
4138 SDValue Arg = OutVals[i];
4139 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4140 if (VA.getLocInfo() == CCValAssign::Indirect)
4141 return false;
4142 if (!VA.isRegLoc()) {
4143 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
4144 MFI, MRI, TII, VA))
4145 return false;
4146 }
4147 }
4148 }
4149
4150 bool PositionIndependent = isPositionIndependent();
4151 // If the tailcall address may be in a register, then make sure it's
4152 // possible to register allocate for it. In 32-bit, the call address can
4153 // only target EAX, EDX, or ECX since the tail call must be scheduled after
4154 // callee-saved registers are restored. These happen to be the same
4155 // registers used to pass 'inreg' arguments so watch out for those.
4156 if (!Subtarget.is64Bit() && ((!isa<GlobalAddressSDNode>(Callee) &&
4157 !isa<ExternalSymbolSDNode>(Callee)) ||
4158 PositionIndependent)) {
4159 unsigned NumInRegs = 0;
4160 // In PIC we need an extra register to formulate the address computation
4161 // for the callee.
4162 unsigned MaxInRegs = PositionIndependent ? 2 : 3;
4163
4164 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
4165 CCValAssign &VA = ArgLocs[i];
4166 if (!VA.isRegLoc())
4167 continue;
4168 unsigned Reg = VA.getLocReg();
4169 switch (Reg) {
4170 default: break;
4171 case X86::EAX: case X86::EDX: case X86::ECX:
4172 if (++NumInRegs == MaxInRegs)
4173 return false;
4174 break;
4175 }
4176 }
4177 }
4178
4179 const MachineRegisterInfo &MRI = MF.getRegInfo();
4180 if (!parametersInCSRMatch(MRI, CallerPreserved, ArgLocs, OutVals))
4181 return false;
4182 }
4183
4184 bool CalleeWillPop =
4185 X86::isCalleePop(CalleeCC, Subtarget.is64Bit(), isVarArg,
4186 MF.getTarget().Options.GuaranteedTailCallOpt);
4187
4188 if (unsigned BytesToPop =
4189 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn()) {
4190 // If we have bytes to pop, the callee must pop them.
4191 bool CalleePopMatches = CalleeWillPop && BytesToPop == StackArgsSize;
4192 if (!CalleePopMatches)
4193 return false;
4194 } else if (CalleeWillPop && StackArgsSize > 0) {
4195 // If we don't have bytes to pop, make sure the callee doesn't pop any.
4196 return false;
4197 }
4198
4199 return true;
4200}
4201
4202FastISel *
4203X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
4204 const TargetLibraryInfo *libInfo) const {
4205 return X86::createFastISel(funcInfo, libInfo);
4206}
4207
4208//===----------------------------------------------------------------------===//
4209// Other Lowering Hooks
4210//===----------------------------------------------------------------------===//
4211
4212static bool MayFoldLoad(SDValue Op) {
4213 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
4214}
4215
4216static bool MayFoldIntoStore(SDValue Op) {
4217 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
4218}
4219
4220static bool MayFoldIntoZeroExtend(SDValue Op) {
4221 if (Op.hasOneUse()) {
4222 unsigned Opcode = Op.getNode()->use_begin()->getOpcode();
4223 return (ISD::ZERO_EXTEND == Opcode);
4224 }
4225 return false;
4226}
4227
4228static bool isTargetShuffle(unsigned Opcode) {
4229 switch(Opcode) {
4230 default: return false;
4231 case X86ISD::BLENDI:
4232 case X86ISD::PSHUFB:
4233 case X86ISD::PSHUFD:
4234 case X86ISD::PSHUFHW:
4235 case X86ISD::PSHUFLW:
4236 case X86ISD::SHUFP:
4237 case X86ISD::INSERTPS:
4238 case X86ISD::EXTRQI:
4239 case X86ISD::INSERTQI:
4240 case X86ISD::PALIGNR:
4241 case X86ISD::VSHLDQ:
4242 case X86ISD::VSRLDQ:
4243 case X86ISD::MOVLHPS:
4244 case X86ISD::MOVHLPS:
4245 case X86ISD::MOVLPS:
4246 case X86ISD::MOVLPD:
4247 case X86ISD::MOVSHDUP:
4248 case X86ISD::MOVSLDUP:
4249 case X86ISD::MOVDDUP:
4250 case X86ISD::MOVSS:
4251 case X86ISD::MOVSD:
4252 case X86ISD::UNPCKL:
4253 case X86ISD::UNPCKH:
4254 case X86ISD::VBROADCAST:
4255 case X86ISD::VPERMILPI:
4256 case X86ISD::VPERMILPV:
4257 case X86ISD::VPERM2X128:
4258 case X86ISD::VPERMIL2:
4259 case X86ISD::VPERMI:
4260 case X86ISD::VPPERM:
4261 case X86ISD::VPERMV:
4262 case X86ISD::VPERMV3:
4263 case X86ISD::VPERMIV3:
4264 case X86ISD::VZEXT_MOVL:
4265 return true;
4266 }
4267}
4268
4269static bool isTargetShuffleVariableMask(unsigned Opcode) {
4270 switch (Opcode) {
4271 default: return false;
4272 // Target Shuffles.
4273 case X86ISD::PSHUFB:
4274 case X86ISD::VPERMILPV:
4275 case X86ISD::VPERMIL2:
4276 case X86ISD::VPPERM:
4277 case X86ISD::VPERMV:
4278 case X86ISD::VPERMV3:
4279 case X86ISD::VPERMIV3:
4280 return true;
4281 // 'Faux' Target Shuffles.
4282 case ISD::AND:
4283 case X86ISD::ANDNP:
4284 return true;
4285 }
4286}
4287
4288SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
4289 MachineFunction &MF = DAG.getMachineFunction();
4290 const X86RegisterInfo *RegInfo = Subtarget.getRegisterInfo();
4291 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
4292 int ReturnAddrIndex = FuncInfo->getRAIndex();
4293
4294 if (ReturnAddrIndex == 0) {
4295 // Set up a frame object for the return address.
4296 unsigned SlotSize = RegInfo->getSlotSize();
4297 ReturnAddrIndex = MF.getFrameInfo().CreateFixedObject(SlotSize,
4298 -(int64_t)SlotSize,
4299 false);
4300 FuncInfo->setRAIndex(ReturnAddrIndex);
4301 }
4302
4303 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy(DAG.getDataLayout()));
4304}
4305
4306bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
4307 bool hasSymbolicDisplacement) {
4308 // Offset should fit into 32 bit immediate field.
4309 if (!isInt<32>(Offset))
4310 return false;
4311
4312 // If we don't have a symbolic displacement - we don't have any extra
4313 // restrictions.
4314 if (!hasSymbolicDisplacement)
4315 return true;
4316
4317 // FIXME: Some tweaks might be needed for medium code model.
4318 if (M != CodeModel::Small && M != CodeModel::Kernel)
4319 return false;
4320
4321 // For small code model we assume that latest object is 16MB before end of 31
4322 // bits boundary. We may also accept pretty large negative constants knowing
4323 // that all objects are in the positive half of address space.
4324 if (M == CodeModel::Small && Offset < 16*1024*1024)
4325 return true;
4326
4327 // For kernel code model we know that all object resist in the negative half
4328 // of 32bits address space. We may not accept negative offsets, since they may
4329 // be just off and we may accept pretty large positive ones.
4330 if (M == CodeModel::Kernel && Offset >= 0)
4331 return true;
4332
4333 return false;
4334}
4335
4336/// Determines whether the callee is required to pop its own arguments.
4337/// Callee pop is necessary to support tail calls.
4338bool X86::isCalleePop(CallingConv::ID CallingConv,
4339 bool is64Bit, bool IsVarArg, bool GuaranteeTCO) {
4340 // If GuaranteeTCO is true, we force some calls to be callee pop so that we
4341 // can guarantee TCO.
4342 if (!IsVarArg && shouldGuaranteeTCO(CallingConv, GuaranteeTCO))
4343 return true;
4344
4345 switch (CallingConv) {
4346 default:
4347 return false;
4348 case CallingConv::X86_StdCall:
4349 case CallingConv::X86_FastCall:
4350 case CallingConv::X86_ThisCall:
4351 case CallingConv::X86_VectorCall:
4352 return !is64Bit;
4353 }
4354}
4355
4356/// \brief Return true if the condition is an unsigned comparison operation.
4357static bool isX86CCUnsigned(unsigned X86CC) {
4358 switch (X86CC) {
4359 default:
4360 llvm_unreachable("Invalid integer condition!")::llvm::llvm_unreachable_internal("Invalid integer condition!"
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 4360)
;
4361 case X86::COND_E:
4362 case X86::COND_NE:
4363 case X86::COND_B:
4364 case X86::COND_A:
4365 case X86::COND_BE:
4366 case X86::COND_AE:
4367 return true;
4368 case X86::COND_G:
4369 case X86::COND_GE:
4370 case X86::COND_L:
4371 case X86::COND_LE:
4372 return false;
4373 }
4374}
4375
4376static X86::CondCode TranslateIntegerX86CC(ISD::CondCode SetCCOpcode) {
4377 switch (SetCCOpcode) {
4378 default: llvm_unreachable("Invalid integer condition!")::llvm::llvm_unreachable_internal("Invalid integer condition!"
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 4378)
;
4379 case ISD::SETEQ: return X86::COND_E;
4380 case ISD::SETGT: return X86::COND_G;
4381 case ISD::SETGE: return X86::COND_GE;
4382 case ISD::SETLT: return X86::COND_L;
4383 case ISD::SETLE: return X86::COND_LE;
4384 case ISD::SETNE: return X86::COND_NE;
4385 case ISD::SETULT: return X86::COND_B;
4386 case ISD::SETUGT: return X86::COND_A;
4387 case ISD::SETULE: return X86::COND_BE;
4388 case ISD::SETUGE: return X86::COND_AE;
4389 }
4390}
4391
4392/// Do a one-to-one translation of a ISD::CondCode to the X86-specific
4393/// condition code, returning the condition code and the LHS/RHS of the
4394/// comparison to make.
4395static X86::CondCode TranslateX86CC(ISD::CondCode SetCCOpcode, const SDLoc &DL,
4396 bool isFP, SDValue &LHS, SDValue &RHS,
4397 SelectionDAG &DAG) {
4398 if (!isFP) {
4399 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
4400 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
4401 // X > -1 -> X == 0, jump !sign.
4402 RHS = DAG.getConstant(0, DL, RHS.getValueType());
4403 return X86::COND_NS;
4404 }
4405 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
4406 // X < 0 -> X == 0, jump on sign.
4407 return X86::COND_S;
4408 }
4409 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
4410 // X < 1 -> X <= 0
4411 RHS = DAG.getConstant(0, DL, RHS.getValueType());
4412 return X86::COND_LE;
4413 }
4414 }
4415
4416 return TranslateIntegerX86CC(SetCCOpcode);
4417 }
4418
4419 // First determine if it is required or is profitable to flip the operands.
4420
4421 // If LHS is a foldable load, but RHS is not, flip the condition.
4422 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
4423 !ISD::isNON_EXTLoad(RHS.getNode())) {
4424 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
4425 std::swap(LHS, RHS);
4426 }
4427
4428 switch (SetCCOpcode) {
4429 default: break;
4430 case ISD::SETOLT:
4431 case ISD::SETOLE:
4432 case ISD::SETUGT:
4433 case ISD::SETUGE:
4434 std::swap(LHS, RHS);
4435 break;
4436 }
4437
4438 // On a floating point condition, the flags are set as follows:
4439 // ZF PF CF op
4440 // 0 | 0 | 0 | X > Y
4441 // 0 | 0 | 1 | X < Y
4442 // 1 | 0 | 0 | X == Y
4443 // 1 | 1 | 1 | unordered
4444 switch (SetCCOpcode) {
4445 default: llvm_unreachable("Condcode should be pre-legalized away")::llvm::llvm_unreachable_internal("Condcode should be pre-legalized away"
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 4445)
;
4446 case ISD::SETUEQ:
4447 case ISD::SETEQ: return X86::COND_E;
4448 case ISD::SETOLT: // flipped
4449 case ISD::SETOGT:
4450 case ISD::SETGT: return X86::COND_A;
4451 case ISD::SETOLE: // flipped
4452 case ISD::SETOGE:
4453 case ISD::SETGE: return X86::COND_AE;
4454 case ISD::SETUGT: // flipped
4455 case ISD::SETULT:
4456 case ISD::SETLT: return X86::COND_B;
4457 case ISD::SETUGE: // flipped
4458 case ISD::SETULE:
4459 case ISD::SETLE: return X86::COND_BE;
4460 case ISD::SETONE:
4461 case ISD::SETNE: return X86::COND_NE;
4462 case ISD::SETUO: return X86::COND_P;
4463 case ISD::SETO: return X86::COND_NP;
4464 case ISD::SETOEQ:
4465 case ISD::SETUNE: return X86::COND_INVALID;
4466 }
4467}
4468
4469/// Is there a floating point cmov for the specific X86 condition code?
4470/// Current x86 isa includes the following FP cmov instructions:
4471/// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
4472static bool hasFPCMov(unsigned X86CC) {
4473 switch (X86CC) {
4474 default:
4475 return false;
4476 case X86::COND_B:
4477 case X86::COND_BE:
4478 case X86::COND_E:
4479 case X86::COND_P:
4480 case X86::COND_A:
4481 case X86::COND_AE:
4482 case X86::COND_NE:
4483 case X86::COND_NP:
4484 return true;
4485 }
4486}
4487
4488
4489bool X86TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
4490 const CallInst &I,
4491 unsigned Intrinsic) const {
4492
4493 const IntrinsicData* IntrData = getIntrinsicWithChain(Intrinsic);
4494 if (!IntrData)
4495 return false;
4496
4497 Info.opc = ISD::INTRINSIC_W_CHAIN;
4498 Info.readMem = false;
4499 Info.writeMem = false;
4500 Info.vol = false;
4501 Info.offset = 0;
4502
4503 switch (IntrData->Type) {
4504 case EXPAND_FROM_MEM: {
4505 Info.ptrVal = I.getArgOperand(0);
4506 Info.memVT = MVT::getVT(I.getType());
4507 Info.align = 1;
4508 Info.readMem = true;
4509 break;
4510 }
4511 case COMPRESS_TO_MEM: {
4512 Info.ptrVal = I.getArgOperand(0);
4513 Info.memVT = MVT::getVT(I.getArgOperand(1)->getType());
4514 Info.align = 1;
4515 Info.writeMem = true;
4516 break;
4517 }
4518 case TRUNCATE_TO_MEM_VI8:
4519 case TRUNCATE_TO_MEM_VI16:
4520 case TRUNCATE_TO_MEM_VI32: {
4521 Info.ptrVal = I.getArgOperand(0);
4522 MVT VT = MVT::getVT(I.getArgOperand(1)->getType());
4523 MVT ScalarVT = MVT::INVALID_SIMPLE_VALUE_TYPE;
4524 if (IntrData->Type == TRUNCATE_TO_MEM_VI8)
4525 ScalarVT = MVT::i8;
4526 else if (IntrData->Type == TRUNCATE_TO_MEM_VI16)
4527 ScalarVT = MVT::i16;
4528 else if (IntrData->Type == TRUNCATE_TO_MEM_VI32)
4529 ScalarVT = MVT::i32;
4530
4531 Info.memVT = MVT::getVectorVT(ScalarVT, VT.getVectorNumElements());
4532 Info.align = 1;
4533 Info.writeMem = true;
4534 break;
4535 }
4536 default:
4537 return false;
4538 }
4539
4540 return true;
4541}
4542
4543/// Returns true if the target can instruction select the
4544/// specified FP immediate natively. If false, the legalizer will
4545/// materialize the FP immediate as a load from a constant pool.
4546bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
4547 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
4548 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
4549 return true;
4550 }
4551 return false;
4552}
4553
4554bool X86TargetLowering::shouldReduceLoadWidth(SDNode *Load,
4555 ISD::LoadExtType ExtTy,
4556 EVT NewVT) const {
4557 // "ELF Handling for Thread-Local Storage" specifies that R_X86_64_GOTTPOFF
4558 // relocation target a movq or addq instruction: don't let the load shrink.
4559 SDValue BasePtr = cast<LoadSDNode>(Load)->getBasePtr();
4560 if (BasePtr.getOpcode() == X86ISD::WrapperRIP)
4561 if (const auto *GA = dyn_cast<GlobalAddressSDNode>(BasePtr.getOperand(0)))
4562 return GA->getTargetFlags() != X86II::MO_GOTTPOFF;
4563 return true;
4564}
4565
4566/// \brief Returns true if it is beneficial to convert a load of a constant
4567/// to just the constant itself.
4568bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
4569 Type *Ty) const {
4570 assert(Ty->isIntegerTy())(static_cast <bool> (Ty->isIntegerTy()) ? void (0) :
__assert_fail ("Ty->isIntegerTy()", "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 4570, __extension__ __PRETTY_FUNCTION__))
;
4571
4572 unsigned BitSize = Ty->getPrimitiveSizeInBits();
4573 if (BitSize == 0 || BitSize > 64)
4574 return false;
4575 return true;
4576}
4577
4578bool X86TargetLowering::convertSelectOfConstantsToMath(EVT VT) const {
4579 // TODO: It might be a win to ease or lift this restriction, but the generic
4580 // folds in DAGCombiner conflict with vector folds for an AVX512 target.
4581 if (VT.isVector() && Subtarget.hasAVX512())
4582 return false;
4583
4584 return true;
4585}
4586
4587bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
4588 unsigned Index) const {
4589 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))
4590 return false;
4591
4592 // Mask vectors support all subregister combinations and operations that
4593 // extract half of vector.
4594 if (ResVT.getVectorElementType() == MVT::i1)
4595 return Index == 0 || ((ResVT.getSizeInBits() == SrcVT.getSizeInBits()*2) &&
4596 (Index == ResVT.getVectorNumElements()));
4597
4598 return (Index % ResVT.getVectorNumElements()) == 0;
4599}
4600
4601bool X86TargetLowering::isCheapToSpeculateCttz() const {
4602 // Speculate cttz only if we can directly use TZCNT.
4603 return Subtarget.hasBMI();
4604}
4605
4606bool X86TargetLowering::isCheapToSpeculateCtlz() const {
4607 // Speculate ctlz only if we can directly use LZCNT.
4608 return Subtarget.hasLZCNT();
4609}
4610
4611bool X86TargetLowering::canMergeStoresTo(unsigned AddressSpace, EVT MemVT,
4612 const SelectionDAG &DAG) const {
4613 // Do not merge to float value size (128 bytes) if no implicit
4614 // float attribute is set.
4615 bool NoFloat = DAG.getMachineFunction().getFunction()->hasFnAttribute(
4616 Attribute::NoImplicitFloat);
4617
4618 if (NoFloat) {
4619 unsigned MaxIntSize = Subtarget.is64Bit() ? 64 : 32;
4620 return (MemVT.getSizeInBits() <= MaxIntSize);
4621 }
4622 return true;
4623}
4624
4625bool X86TargetLowering::isCtlzFast() const {
4626 return Subtarget.hasFastLZCNT();
4627}
4628
4629bool X86TargetLowering::isMaskAndCmp0FoldingBeneficial(
4630 const Instruction &AndI) const {
4631 return true;
4632}
4633
4634bool X86TargetLowering::hasAndNotCompare(SDValue Y) const {
4635 if (!Subtarget.hasBMI())
4636 return false;
4637
4638 // There are only 32-bit and 64-bit forms for 'andn'.
4639 EVT VT = Y.getValueType();
4640 if (VT != MVT::i32 && VT != MVT::i64)
4641 return false;
4642
4643 return true;
4644}
4645
4646MVT X86TargetLowering::hasFastEqualityCompare(unsigned NumBits) const {
4647 MVT VT = MVT::getIntegerVT(NumBits);
4648 if (isTypeLegal(VT))
4649 return VT;
4650
4651 // PMOVMSKB can handle this.
4652 if (NumBits == 128 && isTypeLegal(MVT::v16i8))
4653 return MVT::v16i8;
4654
4655 // VPMOVMSKB can handle this.
4656 if (NumBits == 256 && isTypeLegal(MVT::v32i8))
4657 return MVT::v32i8;
4658
4659 // TODO: Allow 64-bit type for 32-bit target.
4660 // TODO: 512-bit types should be allowed, but make sure that those
4661 // cases are handled in combineVectorSizedSetCCEquality().
4662
4663 return MVT::INVALID_SIMPLE_VALUE_TYPE;
4664}
4665
4666/// Val is the undef sentinel value or equal to the specified value.
4667static bool isUndefOrEqual(int Val, int CmpVal) {
4668 return ((Val == SM_SentinelUndef) || (Val == CmpVal));
4669}
4670
4671/// Val is either the undef or zero sentinel value.
4672static bool isUndefOrZero(int Val) {
4673 return ((Val == SM_SentinelUndef) || (Val == SM_SentinelZero));
4674}
4675
4676/// Return true if every element in Mask, beginning
4677/// from position Pos and ending in Pos+Size is the undef sentinel value.
4678static bool isUndefInRange(ArrayRef<int> Mask, unsigned Pos, unsigned Size) {
4679 for (unsigned i = Pos, e = Pos + Size; i != e; ++i)
4680 if (Mask[i] != SM_SentinelUndef)
4681 return false;
4682 return true;
4683}
4684
4685/// Return true if Val is undef or if its value falls within the
4686/// specified range (L, H].
4687static bool isUndefOrInRange(int Val, int Low, int Hi) {
4688 return (Val == SM_SentinelUndef) || (Val >= Low && Val < Hi);
4689}
4690
4691/// Return true if every element in Mask is undef or if its value
4692/// falls within the specified range (L, H].
4693static bool isUndefOrInRange(ArrayRef<int> Mask,
4694 int Low, int Hi) {
4695 for (int M : Mask)
4696 if (!isUndefOrInRange(M, Low, Hi))
4697 return false;
4698 return true;
4699}
4700
4701/// Return true if Val is undef, zero or if its value falls within the
4702/// specified range (L, H].
4703static bool isUndefOrZeroOrInRange(int Val, int Low, int Hi) {
4704 return isUndefOrZero(Val) || (Val >= Low && Val < Hi);
4705}
4706
4707/// Return true if every element in Mask is undef, zero or if its value
4708/// falls within the specified range (L, H].
4709static bool isUndefOrZeroOrInRange(ArrayRef<int> Mask, int Low, int Hi) {
4710 for (int M : Mask)
4711 if (!isUndefOrZeroOrInRange(M, Low, Hi))
4712 return false;
4713 return true;
4714}
4715
4716/// Return true if every element in Mask, beginning
4717/// from position Pos and ending in Pos+Size, falls within the specified
4718/// sequential range (Low, Low+Size]. or is undef.
4719static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
4720 unsigned Pos, unsigned Size, int Low) {
4721 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
4722 if (!isUndefOrEqual(Mask[i], Low))
4723 return false;
4724 return true;
4725}
4726
4727/// Return true if every element in Mask, beginning
4728/// from position Pos and ending in Pos+Size, falls within the specified
4729/// sequential range (Low, Low+Size], or is undef or is zero.
4730static bool isSequentialOrUndefOrZeroInRange(ArrayRef<int> Mask, unsigned Pos,
4731 unsigned Size, int Low) {
4732 for (unsigned i = Pos, e = Pos + Size; i != e; ++i, ++Low)
4733 if (!isUndefOrZero(Mask[i]) && Mask[i] != Low)
4734 return false;
4735 return true;
4736}
4737
4738/// Return true if every element in Mask, beginning
4739/// from position Pos and ending in Pos+Size is undef or is zero.
4740static bool isUndefOrZeroInRange(ArrayRef<int> Mask, unsigned Pos,
4741 unsigned Size) {
4742 for (unsigned i = Pos, e = Pos + Size; i != e; ++i)
4743 if (!isUndefOrZero(Mask[i]))
4744 return false;
4745 return true;
4746}
4747
4748/// \brief Helper function to test whether a shuffle mask could be
4749/// simplified by widening the elements being shuffled.
4750///
4751/// Appends the mask for wider elements in WidenedMask if valid. Otherwise
4752/// leaves it in an unspecified state.
4753///
4754/// NOTE: This must handle normal vector shuffle masks and *target* vector
4755/// shuffle masks. The latter have the special property of a '-2' representing
4756/// a zero-ed lane of a vector.
4757static bool canWidenShuffleElements(ArrayRef<int> Mask,
4758 SmallVectorImpl<int> &WidenedMask) {
4759 WidenedMask.assign(Mask.size() / 2, 0);
4760 for (int i = 0, Size = Mask.size(); i < Size; i += 2) {
4761 int M0 = Mask[i];
4762 int M1 = Mask[i + 1];
4763
4764 // If both elements are undef, its trivial.
4765 if (M0 == SM_SentinelUndef && M1 == SM_SentinelUndef) {
4766 WidenedMask[i / 2] = SM_SentinelUndef;
4767 continue;
4768 }
4769
4770 // Check for an undef mask and a mask value properly aligned to fit with
4771 // a pair of values. If we find such a case, use the non-undef mask's value.
4772 if (M0 == SM_SentinelUndef && M1 >= 0 && (M1 % 2) == 1) {
4773 WidenedMask[i / 2] = M1 / 2;
4774 continue;
4775 }
4776 if (M1 == SM_SentinelUndef && M0 >= 0 && (M0 % 2) == 0) {
4777 WidenedMask[i / 2] = M0 / 2;
4778 continue;
4779 }
4780
4781 // When zeroing, we need to spread the zeroing across both lanes to widen.
4782 if (M0 == SM_SentinelZero || M1 == SM_SentinelZero) {
4783 if ((M0 == SM_SentinelZero || M0 == SM_SentinelUndef) &&
4784 (M1 == SM_SentinelZero || M1 == SM_SentinelUndef)) {
4785 WidenedMask[i / 2] = SM_SentinelZero;
4786 continue;
4787 }
4788 return false;
4789 }
4790
4791 // Finally check if the two mask values are adjacent and aligned with
4792 // a pair.
4793 if (M0 != SM_SentinelUndef && (M0 % 2) == 0 && (M0 + 1) == M1) {
4794 WidenedMask[i / 2] = M0 / 2;
4795 continue;
4796 }
4797
4798 // Otherwise we can't safely widen the elements used in this shuffle.
4799 return false;
4800 }
4801 assert(WidenedMask.size() == Mask.size() / 2 &&(static_cast <bool> (WidenedMask.size() == Mask.size() /
2 && "Incorrect size of mask after widening the elements!"
) ? void (0) : __assert_fail ("WidenedMask.size() == Mask.size() / 2 && \"Incorrect size of mask after widening the elements!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 4802, __extension__ __PRETTY_FUNCTION__))
4802 "Incorrect size of mask after widening the elements!")(static_cast <bool> (WidenedMask.size() == Mask.size() /
2 && "Incorrect size of mask after widening the elements!"
) ? void (0) : __assert_fail ("WidenedMask.size() == Mask.size() / 2 && \"Incorrect size of mask after widening the elements!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 4802, __extension__ __PRETTY_FUNCTION__))
;
4803
4804 return true;
4805}
4806
4807/// Returns true if Elt is a constant zero or a floating point constant +0.0.
4808bool X86::isZeroNode(SDValue Elt) {
4809 return isNullConstant(Elt) || isNullFPConstant(Elt);
4810}
4811
4812// Build a vector of constants.
4813// Use an UNDEF node if MaskElt == -1.
4814// Split 64-bit constants in the 32-bit mode.
4815static SDValue getConstVector(ArrayRef<int> Values, MVT VT, SelectionDAG &DAG,
4816 const SDLoc &dl, bool IsMask = false) {
4817
4818 SmallVector<SDValue, 32> Ops;
4819 bool Split = false;
4820
4821 MVT ConstVecVT = VT;
4822 unsigned NumElts = VT.getVectorNumElements();
4823 bool In64BitMode = DAG.getTargetLoweringInfo().isTypeLegal(MVT::i64);
4824 if (!In64BitMode && VT.getVectorElementType() == MVT::i64) {
4825 ConstVecVT = MVT::getVectorVT(MVT::i32, NumElts * 2);
4826 Split = true;
4827 }
4828
4829 MVT EltVT = ConstVecVT.getVectorElementType();
4830 for (unsigned i = 0; i < NumElts; ++i) {
4831 bool IsUndef = Values[i] < 0 && IsMask;
4832 SDValue OpNode = IsUndef ? DAG.getUNDEF(EltVT) :
4833 DAG.getConstant(Values[i], dl, EltVT);
4834 Ops.push_back(OpNode);
4835 if (Split)
4836 Ops.push_back(IsUndef ? DAG.getUNDEF(EltVT) :
4837 DAG.getConstant(0, dl, EltVT));
4838 }
4839 SDValue ConstsNode = DAG.getBuildVector(ConstVecVT, dl, Ops);
4840 if (Split)
4841 ConstsNode = DAG.getBitcast(VT, ConstsNode);
4842 return ConstsNode;
4843}
4844
4845static SDValue getConstVector(ArrayRef<APInt> Bits, APInt &Undefs,
4846 MVT VT, SelectionDAG &DAG, const SDLoc &dl) {
4847 assert(Bits.size() == Undefs.getBitWidth() &&(static_cast <bool> (Bits.size() == Undefs.getBitWidth(
) && "Unequal constant and undef arrays") ? void (0) :
__assert_fail ("Bits.size() == Undefs.getBitWidth() && \"Unequal constant and undef arrays\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 4848, __extension__ __PRETTY_FUNCTION__))
4848 "Unequal constant and undef arrays")(static_cast <bool> (Bits.size() == Undefs.getBitWidth(
) && "Unequal constant and undef arrays") ? void (0) :
__assert_fail ("Bits.size() == Undefs.getBitWidth() && \"Unequal constant and undef arrays\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 4848, __extension__ __PRETTY_FUNCTION__))
;
4849 SmallVector<SDValue, 32> Ops;
4850 bool Split = false;
4851
4852 MVT ConstVecVT = VT;
4853 unsigned NumElts = VT.getVectorNumElements();
4854 bool In64BitMode = DAG.getTargetLoweringInfo().isTypeLegal(MVT::i64);
4855 if (!In64BitMode && VT.getVectorElementType() == MVT::i64) {
4856 ConstVecVT = MVT::getVectorVT(MVT::i32, NumElts * 2);
4857 Split = true;
4858 }
4859
4860 MVT EltVT = ConstVecVT.getVectorElementType();
4861 for (unsigned i = 0, e = Bits.size(); i != e; ++i) {
4862 if (Undefs[i]) {
4863 Ops.append(Split ? 2 : 1, DAG.getUNDEF(EltVT));
4864 continue;
4865 }
4866 const APInt &V = Bits[i];
4867 assert(V.getBitWidth() == VT.getScalarSizeInBits() && "Unexpected sizes")(static_cast <bool> (V.getBitWidth() == VT.getScalarSizeInBits
() && "Unexpected sizes") ? void (0) : __assert_fail (
"V.getBitWidth() == VT.getScalarSizeInBits() && \"Unexpected sizes\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 4867, __extension__ __PRETTY_FUNCTION__))
;
4868 if (Split) {
4869 Ops.push_back(DAG.getConstant(V.trunc(32), dl, EltVT));
4870 Ops.push_back(DAG.getConstant(V.lshr(32).trunc(32), dl, EltVT));
4871 } else if (EltVT == MVT::f32) {
4872 APFloat FV(APFloat::IEEEsingle(), V);
4873 Ops.push_back(DAG.getConstantFP(FV, dl, EltVT));
4874 } else if (EltVT == MVT::f64) {
4875 APFloat FV(APFloat::IEEEdouble(), V);
4876 Ops.push_back(DAG.getConstantFP(FV, dl, EltVT));
4877 } else {
4878 Ops.push_back(DAG.getConstant(V, dl, EltVT));
4879 }
4880 }
4881
4882 SDValue ConstsNode = DAG.getBuildVector(ConstVecVT, dl, Ops);
4883 return DAG.getBitcast(VT, ConstsNode);
4884}
4885
4886/// Returns a vector of specified type with all zero elements.
4887static SDValue getZeroVector(MVT VT, const X86Subtarget &Subtarget,
4888 SelectionDAG &DAG, const SDLoc &dl) {
4889 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector() ||(static_cast <bool> ((VT.is128BitVector() || VT.is256BitVector
() || VT.is512BitVector() || VT.getVectorElementType() == MVT
::i1) && "Unexpected vector type") ? void (0) : __assert_fail
("(VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector() || VT.getVectorElementType() == MVT::i1) && \"Unexpected vector type\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 4891, __extension__ __PRETTY_FUNCTION__))
4890 VT.getVectorElementType() == MVT::i1) &&(static_cast <bool> ((VT.is128BitVector() || VT.is256BitVector
() || VT.is512BitVector() || VT.getVectorElementType() == MVT
::i1) && "Unexpected vector type") ? void (0) : __assert_fail
("(VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector() || VT.getVectorElementType() == MVT::i1) && \"Unexpected vector type\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 4891, __extension__ __PRETTY_FUNCTION__))
4891 "Unexpected vector type")(static_cast <bool> ((VT.is128BitVector() || VT.is256BitVector
() || VT.is512BitVector() || VT.getVectorElementType() == MVT
::i1) && "Unexpected vector type") ? void (0) : __assert_fail
("(VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector() || VT.getVectorElementType() == MVT::i1) && \"Unexpected vector type\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 4891, __extension__ __PRETTY_FUNCTION__))
;
4892
4893 // Try to build SSE/AVX zero vectors as <N x i32> bitcasted to their dest
4894 // type. This ensures they get CSE'd. But if the integer type is not
4895 // available, use a floating-point +0.0 instead.
4896 SDValue Vec;
4897 if (!Subtarget.hasSSE2() && VT.is128BitVector()) {
4898 Vec = DAG.getConstantFP(+0.0, dl, MVT::v4f32);
4899 } else if (VT.getVectorElementType() == MVT::i1) {
4900 assert((Subtarget.hasBWI() || VT.getVectorNumElements() <= 16) &&(static_cast <bool> ((Subtarget.hasBWI() || VT.getVectorNumElements
() <= 16) && "Unexpected vector type") ? void (0) :
__assert_fail ("(Subtarget.hasBWI() || VT.getVectorNumElements() <= 16) && \"Unexpected vector type\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 4901, __extension__ __PRETTY_FUNCTION__))
4901 "Unexpected vector type")(static_cast <bool> ((Subtarget.hasBWI() || VT.getVectorNumElements
() <= 16) && "Unexpected vector type") ? void (0) :
__assert_fail ("(Subtarget.hasBWI() || VT.getVectorNumElements() <= 16) && \"Unexpected vector type\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 4901, __extension__ __PRETTY_FUNCTION__))
;
4902 assert((Subtarget.hasVLX() || VT.getVectorNumElements() >= 8) &&(static_cast <bool> ((Subtarget.hasVLX() || VT.getVectorNumElements
() >= 8) && "Unexpected vector type") ? void (0) :
__assert_fail ("(Subtarget.hasVLX() || VT.getVectorNumElements() >= 8) && \"Unexpected vector type\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 4903, __extension__ __PRETTY_FUNCTION__))
4903 "Unexpected vector type")(static_cast <bool> ((Subtarget.hasVLX() || VT.getVectorNumElements
() >= 8) && "Unexpected vector type") ? void (0) :
__assert_fail ("(Subtarget.hasVLX() || VT.getVectorNumElements() >= 8) && \"Unexpected vector type\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 4903, __extension__ __PRETTY_FUNCTION__))
;
4904 Vec = DAG.getConstant(0, dl, VT);
4905 } else {
4906 unsigned Num32BitElts = VT.getSizeInBits() / 32;
4907 Vec = DAG.getConstant(0, dl, MVT::getVectorVT(MVT::i32, Num32BitElts));
4908 }
4909 return DAG.getBitcast(VT, Vec);
4910}
4911
4912static SDValue extractSubVector(SDValue Vec, unsigned IdxVal, SelectionDAG &DAG,
4913 const SDLoc &dl, unsigned vectorWidth) {
4914 EVT VT = Vec.getValueType();
4915 EVT ElVT = VT.getVectorElementType();
4916 unsigned Factor = VT.getSizeInBits()/vectorWidth;
4917 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
4918 VT.getVectorNumElements()/Factor);
4919
4920 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
4921 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
4922 assert(isPowerOf2_32(ElemsPerChunk) && "Elements per chunk not power of 2")(static_cast <bool> (isPowerOf2_32(ElemsPerChunk) &&
"Elements per chunk not power of 2") ? void (0) : __assert_fail
("isPowerOf2_32(ElemsPerChunk) && \"Elements per chunk not power of 2\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 4922, __extension__ __PRETTY_FUNCTION__))
;
4923
4924 // This is the index of the first element of the vectorWidth-bit chunk
4925 // we want. Since ElemsPerChunk is a power of 2 just need to clear bits.
4926 IdxVal &= ~(ElemsPerChunk - 1);
4927
4928 // If the input is a buildvector just emit a smaller one.
4929 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
4930 return DAG.getBuildVector(ResultVT, dl,
4931 Vec->ops().slice(IdxVal, ElemsPerChunk));
4932
4933 SDValue VecIdx = DAG.getIntPtrConstant(IdxVal, dl);
4934 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, VecIdx);
4935}
4936
4937/// Generate a DAG to grab 128-bits from a vector > 128 bits. This
4938/// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
4939/// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
4940/// instructions or a simple subregister reference. Idx is an index in the
4941/// 128 bits we want. It need not be aligned to a 128-bit boundary. That makes
4942/// lowering EXTRACT_VECTOR_ELT operations easier.
4943static SDValue extract128BitVector(SDValue Vec, unsigned IdxVal,
4944 SelectionDAG &DAG, const SDLoc &dl) {
4945 assert((Vec.getValueType().is256BitVector() ||(static_cast <bool> ((Vec.getValueType().is256BitVector
() || Vec.getValueType().is512BitVector()) && "Unexpected vector size!"
) ? void (0) : __assert_fail ("(Vec.getValueType().is256BitVector() || Vec.getValueType().is512BitVector()) && \"Unexpected vector size!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 4946, __extension__ __PRETTY_FUNCTION__))
4946 Vec.getValueType().is512BitVector()) && "Unexpected vector size!")(static_cast <bool> ((Vec.getValueType().is256BitVector
() || Vec.getValueType().is512BitVector()) && "Unexpected vector size!"
) ? void (0) : __assert_fail ("(Vec.getValueType().is256BitVector() || Vec.getValueType().is512BitVector()) && \"Unexpected vector size!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 4946, __extension__ __PRETTY_FUNCTION__))
;
4947 return extractSubVector(Vec, IdxVal, DAG, dl, 128);
4948}
4949
4950/// Generate a DAG to grab 256-bits from a 512-bit vector.
4951static SDValue extract256BitVector(SDValue Vec, unsigned IdxVal,
4952 SelectionDAG &DAG, const SDLoc &dl) {
4953 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!")(static_cast <bool> (Vec.getValueType().is512BitVector(
) && "Unexpected vector size!") ? void (0) : __assert_fail
("Vec.getValueType().is512BitVector() && \"Unexpected vector size!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 4953, __extension__ __PRETTY_FUNCTION__))
;
4954 return extractSubVector(Vec, IdxVal, DAG, dl, 256);
4955}
4956
4957static SDValue insertSubVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4958 SelectionDAG &DAG, const SDLoc &dl,
4959 unsigned vectorWidth) {
4960 assert((vectorWidth == 128 || vectorWidth == 256) &&(static_cast <bool> ((vectorWidth == 128 || vectorWidth
== 256) && "Unsupported vector width") ? void (0) : __assert_fail
("(vectorWidth == 128 || vectorWidth == 256) && \"Unsupported vector width\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 4961, __extension__ __PRETTY_FUNCTION__))
4961 "Unsupported vector width")(static_cast <bool> ((vectorWidth == 128 || vectorWidth
== 256) && "Unsupported vector width") ? void (0) : __assert_fail
("(vectorWidth == 128 || vectorWidth == 256) && \"Unsupported vector width\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 4961, __extension__ __PRETTY_FUNCTION__))
;
4962 // Inserting UNDEF is Result
4963 if (Vec.isUndef())
4964 return Result;
4965 EVT VT = Vec.getValueType();
4966 EVT ElVT = VT.getVectorElementType();
4967 EVT ResultVT = Result.getValueType();
4968
4969 // Insert the relevant vectorWidth bits.
4970 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
4971 assert(isPowerOf2_32(ElemsPerChunk) && "Elements per chunk not power of 2")(static_cast <bool> (isPowerOf2_32(ElemsPerChunk) &&
"Elements per chunk not power of 2") ? void (0) : __assert_fail
("isPowerOf2_32(ElemsPerChunk) && \"Elements per chunk not power of 2\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 4971, __extension__ __PRETTY_FUNCTION__))
;
4972
4973 // This is the index of the first element of the vectorWidth-bit chunk
4974 // we want. Since ElemsPerChunk is a power of 2 just need to clear bits.
4975 IdxVal &= ~(ElemsPerChunk - 1);
4976
4977 SDValue VecIdx = DAG.getIntPtrConstant(IdxVal, dl);
4978 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, VecIdx);
4979}
4980
4981/// Generate a DAG to put 128-bits into a vector > 128 bits. This
4982/// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
4983/// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
4984/// simple superregister reference. Idx is an index in the 128 bits
4985/// we want. It need not be aligned to a 128-bit boundary. That makes
4986/// lowering INSERT_VECTOR_ELT operations easier.
4987static SDValue insert128BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4988 SelectionDAG &DAG, const SDLoc &dl) {
4989 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!")(static_cast <bool> (Vec.getValueType().is128BitVector(
) && "Unexpected vector size!") ? void (0) : __assert_fail
("Vec.getValueType().is128BitVector() && \"Unexpected vector size!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 4989, __extension__ __PRETTY_FUNCTION__))
;
4990 return insertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
4991}
4992
4993static SDValue insert256BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4994 SelectionDAG &DAG, const SDLoc &dl) {
4995 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!")(static_cast <bool> (Vec.getValueType().is256BitVector(
) && "Unexpected vector size!") ? void (0) : __assert_fail
("Vec.getValueType().is256BitVector() && \"Unexpected vector size!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 4995, __extension__ __PRETTY_FUNCTION__))
;
4996 return insertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
4997}
4998
4999// Return true if the instruction zeroes the unused upper part of the
5000// destination and accepts mask.
5001static bool isMaskedZeroUpperBitsvXi1(unsigned int Opcode) {
5002 switch (Opcode) {
5003 default:
5004 return false;
5005 case X86ISD::TESTM:
5006 case X86ISD::TESTNM:
5007 case X86ISD::PCMPEQM:
5008 case X86ISD::PCMPGTM:
5009 case X86ISD::CMPM:
5010 case X86ISD::CMPMU:
5011 return true;
5012 }
5013}
5014
5015/// Insert i1-subvector to i1-vector.
5016static SDValue insert1BitVector(SDValue Op, SelectionDAG &DAG,
5017 const X86Subtarget &Subtarget) {
5018
5019 SDLoc dl(Op);
5020 SDValue Vec = Op.getOperand(0);
5021 SDValue SubVec = Op.getOperand(1);
5022 SDValue Idx = Op.getOperand(2);
5023
5024 if (!isa<ConstantSDNode>(Idx))
5025 return SDValue();
5026
5027 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
5028 if (IdxVal == 0 && Vec.isUndef()) // the operation is legal
5029 return Op;
5030
5031 MVT OpVT = Op.getSimpleValueType();
5032 MVT SubVecVT = SubVec.getSimpleValueType();
5033 unsigned NumElems = OpVT.getVectorNumElements();
5034 unsigned SubVecNumElems = SubVecVT.getVectorNumElements();
5035
5036 assert(IdxVal + SubVecNumElems <= NumElems &&(static_cast <bool> (IdxVal + SubVecNumElems <= NumElems
&& IdxVal % SubVecVT.getSizeInBits() == 0 &&
"Unexpected index value in INSERT_SUBVECTOR") ? void (0) : __assert_fail
("IdxVal + SubVecNumElems <= NumElems && IdxVal % SubVecVT.getSizeInBits() == 0 && \"Unexpected index value in INSERT_SUBVECTOR\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 5038, __extension__ __PRETTY_FUNCTION__))
5037 IdxVal % SubVecVT.getSizeInBits() == 0 &&(static_cast <bool> (IdxVal + SubVecNumElems <= NumElems
&& IdxVal % SubVecVT.getSizeInBits() == 0 &&
"Unexpected index value in INSERT_SUBVECTOR") ? void (0) : __assert_fail
("IdxVal + SubVecNumElems <= NumElems && IdxVal % SubVecVT.getSizeInBits() == 0 && \"Unexpected index value in INSERT_SUBVECTOR\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 5038, __extension__ __PRETTY_FUNCTION__))
5038 "Unexpected index value in INSERT_SUBVECTOR")(static_cast <bool> (IdxVal + SubVecNumElems <= NumElems
&& IdxVal % SubVecVT.getSizeInBits() == 0 &&
"Unexpected index value in INSERT_SUBVECTOR") ? void (0) : __assert_fail
("IdxVal + SubVecNumElems <= NumElems && IdxVal % SubVecVT.getSizeInBits() == 0 && \"Unexpected index value in INSERT_SUBVECTOR\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 5038, __extension__ __PRETTY_FUNCTION__))
;
5039
5040 // There are 3 possible cases:
5041 // 1. Subvector should be inserted in the lower part (IdxVal == 0)
5042 // 2. Subvector should be inserted in the upper part
5043 // (IdxVal + SubVecNumElems == NumElems)
5044 // 3. Subvector should be inserted in the middle (for example v2i1
5045 // to v16i1, index 2)
5046
5047 // If this node widens - by concatenating zeroes - the type of the result
5048 // of a node with instruction that zeroes all upper (irrelevant) bits of the
5049 // output register, mark this node as legal to enable replacing them with
5050 // the v8i1 version of the previous instruction during instruction selection.
5051 // For example, VPCMPEQDZ128rr instruction stores its v4i1 result in a k-reg,
5052 // while zeroing all the upper remaining 60 bits of the register. if the
5053 // result of such instruction is inserted into an allZeroVector, then we can
5054 // safely remove insert_vector (in instruction selection) as the cmp instr
5055 // already zeroed the rest of the register.
5056 if (ISD::isBuildVectorAllZeros(Vec.getNode()) && IdxVal == 0 &&
5057 (isMaskedZeroUpperBitsvXi1(SubVec.getOpcode()) ||
5058 (SubVec.getOpcode() == ISD::AND &&
5059 (isMaskedZeroUpperBitsvXi1(SubVec.getOperand(0).getOpcode()) ||
5060 isMaskedZeroUpperBitsvXi1(SubVec.getOperand(1).getOpcode())))))
5061 return Op;
5062
5063 // extend to natively supported kshift
5064 MVT MinVT = Subtarget.hasDQI() ? MVT::v8i1 : MVT::v16i1;
5065 MVT WideOpVT = OpVT;
5066 if (OpVT.getSizeInBits() < MinVT.getStoreSizeInBits())
5067 WideOpVT = MinVT;
5068
5069 SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
5070 SDValue Undef = DAG.getUNDEF(WideOpVT);
5071 SDValue WideSubVec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, WideOpVT,
5072 Undef, SubVec, ZeroIdx);
5073
5074 // Extract sub-vector if require.
5075 auto ExtractSubVec = [&](SDValue V) {
5076 return (WideOpVT == OpVT) ? V : DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl,
5077 OpVT, V, ZeroIdx);
5078 };
5079
5080 if (Vec.isUndef()) {
5081 if (IdxVal != 0) {
5082 SDValue ShiftBits = DAG.getConstant(IdxVal, dl, MVT::i8);
5083 WideSubVec = DAG.getNode(X86ISD::KSHIFTL, dl, WideOpVT, WideSubVec,
5084 ShiftBits);
5085 }
5086 return ExtractSubVec(WideSubVec);
5087 }
5088
5089 if (ISD::isBuildVectorAllZeros(Vec.getNode())) {
5090 NumElems = WideOpVT.getVectorNumElements();
5091 unsigned ShiftLeft = NumElems - SubVecNumElems;
5092 unsigned ShiftRight = NumElems - SubVecNumElems - IdxVal;
5093 Vec = DAG.getNode(X86ISD::KSHIFTL, dl, WideOpVT, WideSubVec,
5094 DAG.getConstant(ShiftLeft, dl, MVT::i8));
5095 Vec = ShiftRight ? DAG.getNode(X86ISD::KSHIFTR, dl, WideOpVT, Vec,
5096 DAG.getConstant(ShiftRight, dl, MVT::i8)) : Vec;
5097 return ExtractSubVec(Vec);
5098 }
5099
5100 if (IdxVal == 0) {
5101 // Zero lower bits of the Vec
5102 SDValue ShiftBits = DAG.getConstant(SubVecNumElems, dl, MVT::i8);
5103 Vec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, WideOpVT, Undef, Vec, ZeroIdx);
5104 Vec = DAG.getNode(X86ISD::KSHIFTR, dl, WideOpVT, Vec, ShiftBits);
5105 Vec = DAG.getNode(X86ISD::KSHIFTL, dl, WideOpVT, Vec, ShiftBits);
5106 // Merge them together, SubVec should be zero extended.
5107 WideSubVec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, WideOpVT,
5108 getZeroVector(WideOpVT, Subtarget, DAG, dl),
5109 SubVec, ZeroIdx);
5110 Vec = DAG.getNode(ISD::OR, dl, WideOpVT, Vec, WideSubVec);
5111 return ExtractSubVec(Vec);
5112 }
5113
5114 // Simple case when we put subvector in the upper part
5115 if (IdxVal + SubVecNumElems == NumElems) {
5116 // Zero upper bits of the Vec
5117 WideSubVec = DAG.getNode(X86ISD::KSHIFTL, dl, WideOpVT, WideSubVec,
5118 DAG.getConstant(IdxVal, dl, MVT::i8));
5119 SDValue ShiftBits = DAG.getConstant(SubVecNumElems, dl, MVT::i8);
5120 Vec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, WideOpVT, Undef, Vec, ZeroIdx);
5121 Vec = DAG.getNode(X86ISD::KSHIFTL, dl, WideOpVT, Vec, ShiftBits);
5122 Vec = DAG.getNode(X86ISD::KSHIFTR, dl, WideOpVT, Vec, ShiftBits);
5123 Vec = DAG.getNode(ISD::OR, dl, WideOpVT, Vec, WideSubVec);
5124 return ExtractSubVec(Vec);
5125 }
5126 // Subvector should be inserted in the middle - use shuffle
5127 WideSubVec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, Undef,
5128 SubVec, ZeroIdx);
5129 SmallVector<int, 64> Mask;
5130 for (unsigned i = 0; i < NumElems; ++i)
5131 Mask.push_back(i >= IdxVal && i < IdxVal + SubVecNumElems ?
5132 i : i + NumElems);
5133 return DAG.getVectorShuffle(OpVT, dl, WideSubVec, Vec, Mask);
5134}
5135
5136/// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
5137/// instructions. This is used because creating CONCAT_VECTOR nodes of
5138/// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
5139/// large BUILD_VECTORS.
5140static SDValue concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
5141 unsigned NumElems, SelectionDAG &DAG,
5142 const SDLoc &dl) {
5143 SDValue V = insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
5144 return insert128BitVector(V, V2, NumElems / 2, DAG, dl);
5145}
5146
5147static SDValue concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
5148 unsigned NumElems, SelectionDAG &DAG,
5149 const SDLoc &dl) {
5150 SDValue V = insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
5151 return insert256BitVector(V, V2, NumElems / 2, DAG, dl);
5152}
5153
5154/// Returns a vector of specified type with all bits set.
5155/// Always build ones vectors as <4 x i32>, <8 x i32> or <16 x i32>.
5156/// Then bitcast to their original type, ensuring they get CSE'd.
5157static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, const SDLoc &dl) {
5158 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&(static_cast <bool> ((VT.is128BitVector() || VT.is256BitVector
() || VT.is512BitVector()) && "Expected a 128/256/512-bit vector type"
) ? void (0) : __assert_fail ("(VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) && \"Expected a 128/256/512-bit vector type\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 5159, __extension__ __PRETTY_FUNCTION__))
5159 "Expected a 128/256/512-bit vector type")(static_cast <bool> ((VT.is128BitVector() || VT.is256BitVector
() || VT.is512BitVector()) && "Expected a 128/256/512-bit vector type"
) ? void (0) : __assert_fail ("(VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) && \"Expected a 128/256/512-bit vector type\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 5159, __extension__ __PRETTY_FUNCTION__))
;
5160
5161 APInt Ones = APInt::getAllOnesValue(32);
5162 unsigned NumElts = VT.getSizeInBits() / 32;
5163 SDValue Vec = DAG.getConstant(Ones, dl, MVT::getVectorVT(MVT::i32, NumElts));
5164 return DAG.getBitcast(VT, Vec);
5165}
5166
5167static SDValue getExtendInVec(unsigned Opc, const SDLoc &DL, EVT VT, SDValue In,
5168 SelectionDAG &DAG) {
5169 EVT InVT = In.getValueType();
5170 assert((X86ISD::VSEXT == Opc || X86ISD::VZEXT == Opc) && "Unexpected opcode")(static_cast <bool> ((X86ISD::VSEXT == Opc || X86ISD::VZEXT
== Opc) && "Unexpected opcode") ? void (0) : __assert_fail
("(X86ISD::VSEXT == Opc || X86ISD::VZEXT == Opc) && \"Unexpected opcode\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 5170, __extension__ __PRETTY_FUNCTION__))
;
5171
5172 if (VT.is128BitVector() && InVT.is128BitVector())
5173 return X86ISD::VSEXT == Opc ? DAG.getSignExtendVectorInReg(In, DL, VT)
5174 : DAG.getZeroExtendVectorInReg(In, DL, VT);
5175
5176 // For 256-bit vectors, we only need the lower (128-bit) input half.
5177 // For 512-bit vectors, we only need the lower input half or quarter.
5178 if (VT.getSizeInBits() > 128 && InVT.getSizeInBits() > 128) {
5179 int Scale = VT.getScalarSizeInBits() / InVT.getScalarSizeInBits();
5180 In = extractSubVector(In, 0, DAG, DL,
5181 std::max(128, (int)VT.getSizeInBits() / Scale));
5182 }
5183
5184 return DAG.getNode(Opc, DL, VT, In);
5185}
5186
5187/// Returns a vector_shuffle node for an unpackl operation.
5188static SDValue getUnpackl(SelectionDAG &DAG, const SDLoc &dl, MVT VT,
5189 SDValue V1, SDValue V2) {
5190 SmallVector<int, 8> Mask;
5191 createUnpackShuffleMask(VT, Mask, /* Lo = */ true, /* Unary = */ false);
5192 return DAG.getVectorShuffle(VT, dl, V1, V2, Mask);
5193}
5194
5195/// Returns a vector_shuffle node for an unpackh operation.
5196static SDValue getUnpackh(SelectionDAG &DAG, const SDLoc &dl, MVT VT,
5197 SDValue V1, SDValue V2) {
5198 SmallVector<int, 8> Mask;
5199 createUnpackShuffleMask(VT, Mask, /* Lo = */ false, /* Unary = */ false);
5200 return DAG.getVectorShuffle(VT, dl, V1, V2, Mask);
5201}
5202
5203/// Return a vector_shuffle of the specified vector of zero or undef vector.
5204/// This produces a shuffle where the low element of V2 is swizzled into the
5205/// zero/undef vector, landing at element Idx.
5206/// This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
5207static SDValue getShuffleVectorZeroOrUndef(SDValue V2, int Idx,
5208 bool IsZero,
5209 const X86Subtarget &Subtarget,
5210 SelectionDAG &DAG) {
5211 MVT VT = V2.getSimpleValueType();
5212 SDValue V1 = IsZero
5213 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
5214 int NumElems = VT.getVectorNumElements();
5215 SmallVector<int, 16> MaskVec(NumElems);
5216 for (int i = 0; i != NumElems; ++i)
5217 // If this is the insertion idx, put the low elt of V2 here.
5218 MaskVec[i] = (i == Idx) ? NumElems : i;
5219 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, MaskVec);
5220}
5221
5222static SDValue peekThroughBitcasts(SDValue V) {
5223 while (V.getNode() && V.getOpcode() == ISD::BITCAST)
5224 V = V.getOperand(0);
5225 return V;
5226}
5227
5228static SDValue peekThroughOneUseBitcasts(SDValue V) {
5229 while (V.getNode() && V.getOpcode() == ISD::BITCAST &&
5230 V.getOperand(0).hasOneUse())
5231 V = V.getOperand(0);
5232 return V;
5233}
5234
5235static const Constant *getTargetConstantFromNode(SDValue Op) {
5236 Op = peekThroughBitcasts(Op);
5237
5238 auto *Load = dyn_cast<LoadSDNode>(Op);
5239 if (!Load)
5240 return nullptr;
5241
5242 SDValue Ptr = Load->getBasePtr();
5243 if (Ptr->getOpcode() == X86ISD::Wrapper ||
5244 Ptr->getOpcode() == X86ISD::WrapperRIP)
5245 Ptr = Ptr->getOperand(0);
5246
5247 auto *CNode = dyn_cast<ConstantPoolSDNode>(Ptr);
5248 if (!CNode || CNode->isMachineConstantPoolEntry())
5249 return nullptr;
5250
5251 return dyn_cast<Constant>(CNode->getConstVal());
5252}
5253
5254// Extract raw constant bits from constant pools.
5255static bool getTargetConstantBitsFromNode(SDValue Op, unsigned EltSizeInBits,
5256 APInt &UndefElts,
5257 SmallVectorImpl<APInt> &EltBits,
5258 bool AllowWholeUndefs = true,
5259 bool AllowPartialUndefs = true) {
5260 assert(EltBits.empty() && "Expected an empty EltBits vector")(static_cast <bool> (EltBits.empty() && "Expected an empty EltBits vector"
) ? void (0) : __assert_fail ("EltBits.empty() && \"Expected an empty EltBits vector\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 5260, __extension__ __PRETTY_FUNCTION__))
;
5261
5262 Op = peekThroughBitcasts(Op);
5263
5264 EVT VT = Op.getValueType();
5265 unsigned SizeInBits = VT.getSizeInBits();
5266 assert((SizeInBits % EltSizeInBits) == 0 && "Can't split constant!")(static_cast <bool> ((SizeInBits % EltSizeInBits) == 0 &&
"Can't split constant!") ? void (0) : __assert_fail ("(SizeInBits % EltSizeInBits) == 0 && \"Can't split constant!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 5266, __extension__ __PRETTY_FUNCTION__))
;
5267 unsigned NumElts = SizeInBits / EltSizeInBits;
5268
5269 // Bitcast a source array of element bits to the target size.
5270 auto CastBitData = [&](APInt &UndefSrcElts, ArrayRef<APInt> SrcEltBits) {
5271 unsigned NumSrcElts = UndefSrcElts.getBitWidth();
5272 unsigned SrcEltSizeInBits = SrcEltBits[0].getBitWidth();
5273 assert((NumSrcElts * SrcEltSizeInBits) == SizeInBits &&(static_cast <bool> ((NumSrcElts * SrcEltSizeInBits) ==
SizeInBits && "Constant bit sizes don't match") ? void
(0) : __assert_fail ("(NumSrcElts * SrcEltSizeInBits) == SizeInBits && \"Constant bit sizes don't match\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 5274, __extension__ __PRETTY_FUNCTION__))
5274 "Constant bit sizes don't match")(static_cast <bool> ((NumSrcElts * SrcEltSizeInBits) ==
SizeInBits && "Constant bit sizes don't match") ? void
(0) : __assert_fail ("(NumSrcElts * SrcEltSizeInBits) == SizeInBits && \"Constant bit sizes don't match\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 5274, __extension__ __PRETTY_FUNCTION__))
;
5275
5276 // Don't split if we don't allow undef bits.
5277 bool AllowUndefs = AllowWholeUndefs || AllowPartialUndefs;
5278 if (UndefSrcElts.getBoolValue() && !AllowUndefs)
5279 return false;
5280
5281 // If we're already the right size, don't bother bitcasting.
5282 if (NumSrcElts == NumElts) {
5283 UndefElts = UndefSrcElts;
5284 EltBits.assign(SrcEltBits.begin(), SrcEltBits.end());
5285 return true;
5286 }
5287
5288 // Extract all the undef/constant element data and pack into single bitsets.
5289 APInt UndefBits(SizeInBits, 0);
5290 APInt MaskBits(SizeInBits, 0);
5291
5292 for (unsigned i = 0; i != NumSrcElts; ++i) {
5293 unsigned BitOffset = i * SrcEltSizeInBits;
5294 if (UndefSrcElts[i])
5295 UndefBits.setBits(BitOffset, BitOffset + SrcEltSizeInBits);
5296 MaskBits.insertBits(SrcEltBits[i], BitOffset);
5297 }
5298
5299 // Split the undef/constant single bitset data into the target elements.
5300 UndefElts = APInt(NumElts, 0);
5301 EltBits.resize(NumElts, APInt(EltSizeInBits, 0));
5302
5303 for (unsigned i = 0; i != NumElts; ++i) {
5304 unsigned BitOffset = i * EltSizeInBits;
5305 APInt UndefEltBits = UndefBits.extractBits(EltSizeInBits, BitOffset);
5306
5307 // Only treat an element as UNDEF if all bits are UNDEF.
5308 if (UndefEltBits.isAllOnesValue()) {
5309 if (!AllowWholeUndefs)
5310 return false;
5311 UndefElts.setBit(i);
5312 continue;
5313 }
5314
5315 // If only some bits are UNDEF then treat them as zero (or bail if not
5316 // supported).
5317 if (UndefEltBits.getBoolValue() && !AllowPartialUndefs)
5318 return false;
5319
5320 APInt Bits = MaskBits.extractBits(EltSizeInBits, BitOffset);
5321 EltBits[i] = Bits.getZExtValue();
5322 }
5323 return true;
5324 };
5325
5326 // Collect constant bits and insert into mask/undef bit masks.
5327 auto CollectConstantBits = [](const Constant *Cst, APInt &Mask, APInt &Undefs,
5328 unsigned UndefBitIndex) {
5329 if (!Cst)
5330 return false;
5331 if (isa<UndefValue>(Cst)) {
5332 Undefs.setBit(UndefBitIndex);
5333 return true;
5334 }
5335 if (auto *CInt = dyn_cast<ConstantInt>(Cst)) {
5336 Mask = CInt->getValue();
5337 return true;
5338 }
5339 if (auto *CFP = dyn_cast<ConstantFP>(Cst)) {
5340 Mask = CFP->getValueAPF().bitcastToAPInt();
5341 return true;
5342 }
5343 return false;
5344 };
5345
5346 // Handle UNDEFs.
5347 if (Op.isUndef()) {
5348 APInt UndefSrcElts = APInt::getAllOnesValue(NumElts);
5349 SmallVector<APInt, 64> SrcEltBits(NumElts, APInt(EltSizeInBits, 0));
5350 return CastBitData(UndefSrcElts, SrcEltBits);
5351 }
5352
5353 // Extract scalar constant bits.
5354 if (auto *Cst = dyn_cast<ConstantSDNode>(Op)) {
5355 APInt UndefSrcElts = APInt::getNullValue(1);
5356 SmallVector<APInt, 64> SrcEltBits(1, Cst->getAPIntValue());
5357 return CastBitData(UndefSrcElts, SrcEltBits);
5358 }
5359
5360 // Extract constant bits from build vector.
5361 if (ISD::isBuildVectorOfConstantSDNodes(Op.getNode())) {
5362 unsigned SrcEltSizeInBits = VT.getScalarSizeInBits();
5363 unsigned NumSrcElts = SizeInBits / SrcEltSizeInBits;
5364
5365 APInt UndefSrcElts(NumSrcElts, 0);
5366 SmallVector<APInt, 64> SrcEltBits(NumSrcElts, APInt(SrcEltSizeInBits, 0));
5367 for (unsigned i = 0, e = Op.getNumOperands(); i != e; ++i) {
5368 const SDValue &Src = Op.getOperand(i);
5369 if (Src.isUndef()) {
5370 UndefSrcElts.setBit(i);
5371 continue;
5372 }
5373 auto *Cst = cast<ConstantSDNode>(Src);
5374 SrcEltBits[i] = Cst->getAPIntValue().zextOrTrunc(SrcEltSizeInBits);
5375 }
5376 return CastBitData(UndefSrcElts, SrcEltBits);
5377 }
5378
5379 // Extract constant bits from constant pool vector.
5380 if (auto *Cst = getTargetConstantFromNode(Op)) {
5381 Type *CstTy = Cst->getType();
5382 if (!CstTy->isVectorTy() || (SizeInBits != CstTy->getPrimitiveSizeInBits()))
5383 return false;
5384
5385 unsigned SrcEltSizeInBits = CstTy->getScalarSizeInBits();
5386 unsigned NumSrcElts = CstTy->getVectorNumElements();
5387
5388 APInt UndefSrcElts(NumSrcElts, 0);
5389 SmallVector<APInt, 64> SrcEltBits(NumSrcElts, APInt(SrcEltSizeInBits, 0));
5390 for (unsigned i = 0; i != NumSrcElts; ++i)
5391 if (!CollectConstantBits(Cst->getAggregateElement(i), SrcEltBits[i],
5392 UndefSrcElts, i))
5393 return false;
5394
5395 return CastBitData(UndefSrcElts, SrcEltBits);
5396 }
5397
5398 // Extract constant bits from a broadcasted constant pool scalar.
5399 if (Op.getOpcode() == X86ISD::VBROADCAST &&
5400 EltSizeInBits <= VT.getScalarSizeInBits()) {
5401 if (auto *Broadcast = getTargetConstantFromNode(Op.getOperand(0))) {
5402 unsigned SrcEltSizeInBits = Broadcast->getType()->getScalarSizeInBits();
5403 unsigned NumSrcElts = SizeInBits / SrcEltSizeInBits;
5404
5405 APInt UndefSrcElts(NumSrcElts, 0);
5406 SmallVector<APInt, 64> SrcEltBits(1, APInt(SrcEltSizeInBits, 0));
5407 if (CollectConstantBits(Broadcast, SrcEltBits[0], UndefSrcElts, 0)) {
5408 if (UndefSrcElts[0])
5409 UndefSrcElts.setBits(0, NumSrcElts);
5410 SrcEltBits.append(NumSrcElts - 1, SrcEltBits[0]);
5411 return CastBitData(UndefSrcElts, SrcEltBits);
5412 }
5413 }
5414 }
5415
5416 // Extract a rematerialized scalar constant insertion.
5417 if (Op.getOpcode() == X86ISD::VZEXT_MOVL &&
5418 Op.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
5419 isa<ConstantSDNode>(Op.getOperand(0).getOperand(0))) {
5420 unsigned SrcEltSizeInBits = VT.getScalarSizeInBits();
5421 unsigned NumSrcElts = SizeInBits / SrcEltSizeInBits;
5422
5423 APInt UndefSrcElts(NumSrcElts, 0);
5424 SmallVector<APInt, 64> SrcEltBits;
5425 auto *CN = cast<ConstantSDNode>(Op.getOperand(0).getOperand(0));
5426 SrcEltBits.push_back(CN->getAPIntValue().zextOrTrunc(SrcEltSizeInBits));
5427 SrcEltBits.append(NumSrcElts - 1, APInt(SrcEltSizeInBits, 0));
5428 return CastBitData(UndefSrcElts, SrcEltBits);
5429 }
5430
5431 return false;
5432}
5433
5434static bool getTargetShuffleMaskIndices(SDValue MaskNode,
5435 unsigned MaskEltSizeInBits,
5436 SmallVectorImpl<uint64_t> &RawMask) {
5437 APInt UndefElts;
5438 SmallVector<APInt, 64> EltBits;
5439
5440 // Extract the raw target constant bits.
5441 // FIXME: We currently don't support UNDEF bits or mask entries.
5442 if (!getTargetConstantBitsFromNode(MaskNode, MaskEltSizeInBits, UndefElts,
5443 EltBits, /* AllowWholeUndefs */ false,
5444 /* AllowPartialUndefs */ false))
5445 return false;
5446
5447 // Insert the extracted elements into the mask.
5448 for (APInt Elt : EltBits)
5449 RawMask.push_back(Elt.getZExtValue());
5450
5451 return true;
5452}
5453
5454/// Create a shuffle mask that matches the PACKSS/PACKUS truncation.
5455/// Note: This ignores saturation, so inputs must be checked first.
5456static void createPackShuffleMask(MVT VT, SmallVectorImpl<int> &Mask,
5457 bool Unary) {
5458 assert(Mask.empty() && "Expected an empty shuffle mask vector")(static_cast <bool> (Mask.empty() && "Expected an empty shuffle mask vector"
) ? void (0) : __assert_fail ("Mask.empty() && \"Expected an empty shuffle mask vector\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 5458, __extension__ __PRETTY_FUNCTION__))
;
5459 unsigned NumElts = VT.getVectorNumElements();
5460 unsigned NumLanes = VT.getSizeInBits() / 128;
5461 unsigned NumEltsPerLane = 128 / VT.getScalarSizeInBits();
5462 unsigned Offset = Unary ? 0 : NumElts;
5463
5464 for (unsigned Lane = 0; Lane != NumLanes; ++Lane) {
5465 for (unsigned Elt = 0; Elt != NumEltsPerLane; Elt += 2)
5466 Mask.push_back(Elt + (Lane * NumEltsPerLane));
5467 for (unsigned Elt = 0; Elt != NumEltsPerLane; Elt += 2)
5468 Mask.push_back(Elt + (Lane * NumEltsPerLane) + Offset);
5469 }
5470}
5471
5472/// Calculates the shuffle mask corresponding to the target-specific opcode.
5473/// If the mask could be calculated, returns it in \p Mask, returns the shuffle
5474/// operands in \p Ops, and returns true.
5475/// Sets \p IsUnary to true if only one source is used. Note that this will set
5476/// IsUnary for shuffles which use a single input multiple times, and in those
5477/// cases it will adjust the mask to only have indices within that single input.
5478/// It is an error to call this with non-empty Mask/Ops vectors.
5479static bool getTargetShuffleMask(SDNode *N, MVT VT, bool AllowSentinelZero,
5480 SmallVectorImpl<SDValue> &Ops,
5481 SmallVectorImpl<int> &Mask, bool &IsUnary) {
5482 unsigned NumElems = VT.getVectorNumElements();
5483 SDValue ImmN;
5484
5485 assert(Mask.empty() && "getTargetShuffleMask expects an empty Mask vector")(static_cast <bool> (Mask.empty() && "getTargetShuffleMask expects an empty Mask vector"
) ? void (0) : __assert_fail ("Mask.empty() && \"getTargetShuffleMask expects an empty Mask vector\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 5485, __extension__ __PRETTY_FUNCTION__))
;
5486 assert(Ops.empty() && "getTargetShuffleMask expects an empty Ops vector")(static_cast <bool> (Ops.empty() && "getTargetShuffleMask expects an empty Ops vector"
) ? void (0) : __assert_fail ("Ops.empty() && \"getTargetShuffleMask expects an empty Ops vector\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 5486, __extension__ __PRETTY_FUNCTION__))
;
5487
5488 IsUnary = false;
5489 bool IsFakeUnary = false;
5490 switch(N->getOpcode()) {
5491 case X86ISD::BLENDI:
5492 assert(N->getOperand(0).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(0).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(0).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 5492, __extension__ __PRETTY_FUNCTION__))
;
5493 assert(N->getOperand(1).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(1).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(1).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 5493, __extension__ __PRETTY_FUNCTION__))
;
5494 ImmN = N->getOperand(N->getNumOperands()-1);
5495 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5496 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5497 break;
5498 case X86ISD::SHUFP:
5499 assert(N->getOperand(0).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(0).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(0).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 5499, __extension__ __PRETTY_FUNCTION__))
;
5500 assert(N->getOperand(1).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(1).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(1).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 5500, __extension__ __PRETTY_FUNCTION__))
;
5501 ImmN = N->getOperand(N->getNumOperands()-1);
5502 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5503 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5504 break;
5505 case X86ISD::INSERTPS:
5506 assert(N->getOperand(0).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(0).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(0).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 5506, __extension__ __PRETTY_FUNCTION__))
;
5507 assert(N->getOperand(1).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(1).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(1).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 5507, __extension__ __PRETTY_FUNCTION__))
;
5508 ImmN = N->getOperand(N->getNumOperands()-1);
5509 DecodeINSERTPSMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5510 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5511 break;
5512 case X86ISD::EXTRQI:
5513 assert(N->getOperand(0).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(0).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(0).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 5513, __extension__ __PRETTY_FUNCTION__))
;
5514 if (isa<ConstantSDNode>(N->getOperand(1)) &&
5515 isa<ConstantSDNode>(N->getOperand(2))) {
5516 int BitLen = N->getConstantOperandVal(1);
5517 int BitIdx = N->getConstantOperandVal(2);
5518 DecodeEXTRQIMask(VT, BitLen, BitIdx, Mask);
5519 IsUnary = true;
5520 }
5521 break;
5522 case X86ISD::INSERTQI:
5523 assert(N->getOperand(0).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(0).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(0).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 5523, __extension__ __PRETTY_FUNCTION__))
;
5524 assert(N->getOperand(1).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(1).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(1).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 5524, __extension__ __PRETTY_FUNCTION__))
;
5525 if (isa<ConstantSDNode>(N->getOperand(2)) &&
5526 isa<ConstantSDNode>(N->getOperand(3))) {
5527 int BitLen = N->getConstantOperandVal(2);
5528 int BitIdx = N->getConstantOperandVal(3);
5529 DecodeINSERTQIMask(VT, BitLen, BitIdx, Mask);
5530 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5531 }
5532 break;
5533 case X86ISD::UNPCKH:
5534 assert(N->getOperand(0).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(0).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(0).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 5534, __extension__ __PRETTY_FUNCTION__))
;
5535 assert(N->getOperand(1).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(1).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(1).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 5535, __extension__ __PRETTY_FUNCTION__))
;
5536 DecodeUNPCKHMask(VT, Mask);
5537 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5538 break;
5539 case X86ISD::UNPCKL:
5540 assert(N->getOperand(0).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(0).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(0).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 5540, __extension__ __PRETTY_FUNCTION__))
;
5541 assert(N->getOperand(1).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(1).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(1).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 5541, __extension__ __PRETTY_FUNCTION__))
;
5542 DecodeUNPCKLMask(VT, Mask);
5543 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5544 break;
5545 case X86ISD::MOVHLPS:
5546 assert(N->getOperand(0).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(0).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(0).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 5546, __extension__ __PRETTY_FUNCTION__))
;
5547 assert(N->getOperand(1).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(1).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(1).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 5547, __extension__ __PRETTY_FUNCTION__))
;
5548 DecodeMOVHLPSMask(NumElems, Mask);
5549 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5550 break;
5551 case X86ISD::MOVLHPS:
5552 assert(N->getOperand(0).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(0).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(0).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 5552, __extension__ __PRETTY_FUNCTION__))
;
5553 assert(N->getOperand(1).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(1).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(1).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 5553, __extension__ __PRETTY_FUNCTION__))
;
5554 DecodeMOVLHPSMask(NumElems, Mask);
5555 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5556 break;
5557 case X86ISD::PALIGNR:
5558 assert(VT.getScalarType() == MVT::i8 && "Byte vector expected")(static_cast <bool> (VT.getScalarType() == MVT::i8 &&
"Byte vector expected") ? void (0) : __assert_fail ("VT.getScalarType() == MVT::i8 && \"Byte vector expected\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 5558, __extension__ __PRETTY_FUNCTION__))
;
5559 assert(N->getOperand(0).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(0).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(0).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 5559, __extension__ __PRETTY_FUNCTION__))
;
5560 assert(N->getOperand(1).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(1).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(1).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 5560, __extension__ __PRETTY_FUNCTION__))
;
5561 ImmN = N->getOperand(N->getNumOperands()-1);
5562 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5563 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5564 Ops.push_back(N->getOperand(1));
5565 Ops.push_back(N->getOperand(0));
5566 break;
5567 case X86ISD::VSHLDQ:
5568 assert(VT.getScalarType() == MVT::i8 && "Byte vector expected")(static_cast <bool> (VT.getScalarType() == MVT::i8 &&
"Byte vector expected") ? void (0) : __assert_fail ("VT.getScalarType() == MVT::i8 && \"Byte vector expected\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 5568, __extension__ __PRETTY_FUNCTION__))
;
5569 assert(N->getOperand(0).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(0).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(0).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 5569, __extension__ __PRETTY_FUNCTION__))
;
5570 ImmN = N->getOperand(N->getNumOperands() - 1);
5571 DecodePSLLDQMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5572 IsUnary = true;
5573 break;
5574 case X86ISD::VSRLDQ:
5575 assert(VT.getScalarType() == MVT::i8 && "Byte vector expected")(static_cast <bool> (VT.getScalarType() == MVT::i8 &&
"Byte vector expected") ? void (0) : __assert_fail ("VT.getScalarType() == MVT::i8 && \"Byte vector expected\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 5575, __extension__ __PRETTY_FUNCTION__))
;
5576 assert(N->getOperand(0).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(0).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(0).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 5576, __extension__ __PRETTY_FUNCTION__))
;
5577 ImmN = N->getOperand(N->getNumOperands() - 1);
5578 DecodePSRLDQMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5579 IsUnary = true;
5580 break;
5581 case X86ISD::PSHUFD:
5582 case X86ISD::VPERMILPI:
5583 assert(N->getOperand(0).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(0).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(0).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 5583, __extension__ __PRETTY_FUNCTION__))
;
5584 ImmN = N->getOperand(N->getNumOperands()-1);
5585 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5586 IsUnary = true;
5587 break;
5588 case X86ISD::PSHUFHW:
5589 assert(N->getOperand(0).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(0).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(0).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 5589, __extension__ __PRETTY_FUNCTION__))
;
5590 ImmN = N->getOperand(N->getNumOperands()-1);
5591 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5592 IsUnary = true;
5593 break;
5594 case X86ISD::PSHUFLW:
5595 assert(N->getOperand(0).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(0).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(0).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 5595, __extension__ __PRETTY_FUNCTION__))
;
5596 ImmN = N->getOperand(N->getNumOperands()-1);
5597 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5598 IsUnary = true;
5599 break;
5600 case X86ISD::VZEXT_MOVL:
5601 assert(N->getOperand(0).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(0).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(0).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 5601, __extension__ __PRETTY_FUNCTION__))
;
5602 DecodeZeroMoveLowMask(VT, Mask);
5603 IsUnary = true;
5604 break;
5605 case X86ISD::VBROADCAST: {
5606 SDValue N0 = N->getOperand(0);
5607 // See if we're broadcasting from index 0 of an EXTRACT_SUBVECTOR. If so,
5608 // add the pre-extracted value to the Ops vector.
5609 if (N0.getOpcode() == ISD::EXTRACT_SUBVECTOR &&
5610 N0.getOperand(0).getValueType() == VT &&
5611 N0.getConstantOperandVal(1) == 0)
5612 Ops.push_back(N0.getOperand(0));
5613
5614 // We only decode broadcasts of same-sized vectors, unless the broadcast
5615 // came from an extract from the original width. If we found one, we
5616 // pushed it the Ops vector above.
5617 if (N0.getValueType() == VT || !Ops.empty()) {
5618 DecodeVectorBroadcast(VT, Mask);
5619 IsUnary = true;
5620 break;
5621 }
5622 return false;
5623 }
5624 case X86ISD::VPERMILPV: {
5625 assert(N->getOperand(0).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(0).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(0).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 5625, __extension__ __PRETTY_FUNCTION__))
;
5626 IsUnary = true;
5627 SDValue MaskNode = N->getOperand(1);
5628 unsigned MaskEltSize = VT.getScalarSizeInBits();
5629 SmallVector<uint64_t, 32> RawMask;
5630 if (getTargetShuffleMaskIndices(MaskNode, MaskEltSize, RawMask)) {
5631 DecodeVPERMILPMask(VT, RawMask, Mask);
5632 break;
5633 }
5634 if (auto *C = getTargetConstantFromNode(MaskNode)) {
5635 DecodeVPERMILPMask(C, MaskEltSize, Mask);
5636 break;
5637 }
5638 return false;
5639 }
5640 case X86ISD::PSHUFB: {
5641 assert(VT.getScalarType() == MVT::i8 && "Byte vector expected")(static_cast <bool> (VT.getScalarType() == MVT::i8 &&
"Byte vector expected") ? void (0) : __assert_fail ("VT.getScalarType() == MVT::i8 && \"Byte vector expected\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 5641, __extension__ __PRETTY_FUNCTION__))
;
5642 assert(N->getOperand(0).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(0).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(0).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 5642, __extension__ __PRETTY_FUNCTION__))
;
5643 assert(N->getOperand(1).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(1).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(1).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 5643, __extension__ __PRETTY_FUNCTION__))
;
5644 IsUnary = true;
5645 SDValue MaskNode = N->getOperand(1);
5646 SmallVector<uint64_t, 32> RawMask;
5647 if (getTargetShuffleMaskIndices(MaskNode, 8, RawMask)) {
5648 DecodePSHUFBMask(RawMask, Mask);
5649 break;
5650 }
5651 if (auto *C = getTargetConstantFromNode(MaskNode)) {
5652 DecodePSHUFBMask(C, Mask);
5653 break;
5654 }
5655 return false;
5656 }
5657 case X86ISD::VPERMI:
5658 assert(N->getOperand(0).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(0).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(0).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 5658, __extension__ __PRETTY_FUNCTION__))
;
5659 ImmN = N->getOperand(N->getNumOperands()-1);
5660 DecodeVPERMMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5661 IsUnary = true;
5662 break;
5663 case X86ISD::MOVSS:
5664 case X86ISD::MOVSD:
5665 assert(N->getOperand(0).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(0).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(0).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 5665, __extension__ __PRETTY_FUNCTION__))
;
5666 assert(N->getOperand(1).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(1).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(1).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 5666, __extension__ __PRETTY_FUNCTION__))
;
5667 DecodeScalarMoveMask(VT, /* IsLoad */ false, Mask);
5668 break;
5669 case X86ISD::VPERM2X128:
5670 assert(N->getOperand(0).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(0).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(0).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 5670, __extension__ __PRETTY_FUNCTION__))
;
5671 assert(N->getOperand(1).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(1).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(1).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 5671, __extension__ __PRETTY_FUNCTION__))
;
5672 ImmN = N->getOperand(N->getNumOperands()-1);
5673 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5674 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5675 break;
5676 case X86ISD::MOVSLDUP:
5677 assert(N->getOperand(0).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(0).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(0).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 5677, __extension__ __PRETTY_FUNCTION__))
;
5678 DecodeMOVSLDUPMask(VT, Mask);
5679 IsUnary = true;
5680 break;
5681 case X86ISD::MOVSHDUP:
5682 assert(N->getOperand(0).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(0).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(0).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 5682, __extension__ __PRETTY_FUNCTION__))
;
5683 DecodeMOVSHDUPMask(VT, Mask);
5684 IsUnary = true;
5685 break;
5686 case X86ISD::MOVDDUP:
5687 assert(N->getOperand(0).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(0).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(0).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 5687, __extension__ __PRETTY_FUNCTION__))
;
5688 DecodeMOVDDUPMask(VT, Mask);
5689 IsUnary = true;
5690 break;
5691 case X86ISD::MOVLPD:
5692 case X86ISD::MOVLPS:
5693 // Not yet implemented
5694 return false;
5695 case X86ISD::VPERMIL2: {
5696 assert(N->getOperand(0).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(0).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(0).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 5696, __extension__ __PRETTY_FUNCTION__))
;
5697 assert(N->getOperand(1).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(1).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(1).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 5697, __extension__ __PRETTY_FUNCTION__))
;
5698 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5699 unsigned MaskEltSize = VT.getScalarSizeInBits();
5700 SDValue MaskNode = N->getOperand(2);
5701 SDValue CtrlNode = N->getOperand(3);
5702 if (ConstantSDNode *CtrlOp = dyn_cast<ConstantSDNode>(CtrlNode)) {
5703 unsigned CtrlImm = CtrlOp->getZExtValue();
5704 SmallVector<uint64_t, 32> RawMask;
5705 if (getTargetShuffleMaskIndices(MaskNode, MaskEltSize, RawMask)) {
5706 DecodeVPERMIL2PMask(VT, CtrlImm, RawMask, Mask);
5707 break;
5708 }
5709 if (auto *C = getTargetConstantFromNode(MaskNode)) {
5710 DecodeVPERMIL2PMask(C, CtrlImm, MaskEltSize, Mask);
5711 break;
5712 }
5713 }
5714 return false;
5715 }
5716 case X86ISD::VPPERM: {
5717 assert(N->getOperand(0).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(0).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(0).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 5717, __extension__ __PRETTY_FUNCTION__))
;
5718 assert(N->getOperand(1).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(1).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(1).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 5718, __extension__ __PRETTY_FUNCTION__))
;
5719 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5720 SDValue MaskNode = N->getOperand(2);
5721 SmallVector<uint64_t, 32> RawMask;
5722 if (getTargetShuffleMaskIndices(MaskNode, 8, RawMask)) {
5723 DecodeVPPERMMask(RawMask, Mask);
5724 break;
5725 }
5726 if (auto *C = getTargetConstantFromNode(MaskNode)) {
5727 DecodeVPPERMMask(C, Mask);
5728 break;
5729 }
5730 return false;
5731 }
5732 case X86ISD::VPERMV: {
5733 assert(N->getOperand(1).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(1).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(1).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 5733, __extension__ __PRETTY_FUNCTION__))
;
5734 IsUnary = true;
5735 // Unlike most shuffle nodes, VPERMV's mask operand is operand 0.
5736 Ops.push_back(N->getOperand(1));
5737 SDValue MaskNode = N->getOperand(0);
5738 SmallVector<uint64_t, 32> RawMask;
5739 unsigned MaskEltSize = VT.getScalarSizeInBits();
5740 if (getTargetShuffleMaskIndices(MaskNode, MaskEltSize, RawMask)) {
5741 DecodeVPERMVMask(RawMask, Mask);
5742 break;
5743 }
5744 if (auto *C = getTargetConstantFromNode(MaskNode)) {
5745 DecodeVPERMVMask(C, MaskEltSize, Mask);
5746 break;
5747 }
5748 return false;
5749 }
5750 case X86ISD::VPERMV3: {
5751 assert(N->getOperand(0).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(0).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(0).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 5751, __extension__ __PRETTY_FUNCTION__))
;
5752 assert(N->getOperand(2).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(2).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(2).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 5752, __extension__ __PRETTY_FUNCTION__))
;
5753 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(2);
5754 // Unlike most shuffle nodes, VPERMV3's mask operand is the middle one.
5755 Ops.push_back(N->getOperand(0));
5756 Ops.push_back(N->getOperand(2));
5757 SDValue MaskNode = N->getOperand(1);
5758 unsigned MaskEltSize = VT.getScalarSizeInBits();
5759 if (auto *C = getTargetConstantFromNode(MaskNode)) {
5760 DecodeVPERMV3Mask(C, MaskEltSize, Mask);
5761 break;
5762 }
5763 return false;
5764 }
5765 case X86ISD::VPERMIV3: {
5766 assert(N->getOperand(1).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(1).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(1).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 5766, __extension__ __PRETTY_FUNCTION__))
;
5767 assert(N->getOperand(2).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(2).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(2).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 5767, __extension__ __PRETTY_FUNCTION__))
;
5768 IsUnary = IsFakeUnary = N->getOperand(1) == N->getOperand(2);
5769 // Unlike most shuffle nodes, VPERMIV3's mask operand is the first one.
5770 Ops.push_back(N->getOperand(1));
5771 Ops.push_back(N->getOperand(2));
5772 SDValue MaskNode = N->getOperand(0);
5773 unsigned MaskEltSize = VT.getScalarSizeInBits();
5774 if (auto *C = getTargetConstantFromNode(MaskNode)) {
5775 DecodeVPERMV3Mask(C, MaskEltSize, Mask);
5776 break;
5777 }
5778 return false;
5779 }
5780 default: llvm_unreachable("unknown target shuffle node")::llvm::llvm_unreachable_internal("unknown target shuffle node"
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 5780)
;
5781 }
5782
5783 // Empty mask indicates the decode failed.
5784 if (Mask.empty())
5785 return false;
5786
5787 // Check if we're getting a shuffle mask with zero'd elements.
5788 if (!AllowSentinelZero)
5789 if (any_of(Mask, [](int M) { return M == SM_SentinelZero; }))
5790 return false;
5791
5792 // If we have a fake unary shuffle, the shuffle mask is spread across two
5793 // inputs that are actually the same node. Re-map the mask to always point
5794 // into the first input.
5795 if (IsFakeUnary)
5796 for (int &M : Mask)
5797 if (M >= (int)Mask.size())
5798 M -= Mask.size();
5799
5800 // If we didn't already add operands in the opcode-specific code, default to
5801 // adding 1 or 2 operands starting at 0.
5802 if (Ops.empty()) {
5803 Ops.push_back(N->getOperand(0));
5804 if (!IsUnary || IsFakeUnary)
5805 Ops.push_back(N->getOperand(1));
5806 }
5807
5808 return true;
5809}
5810
5811/// Check a target shuffle mask's inputs to see if we can set any values to
5812/// SM_SentinelZero - this is for elements that are known to be zero
5813/// (not just zeroable) from their inputs.
5814/// Returns true if the target shuffle mask was decoded.
5815static bool setTargetShuffleZeroElements(SDValue N,
5816 SmallVectorImpl<int> &Mask,
5817 SmallVectorImpl<SDValue> &Ops) {
5818 bool IsUnary;
5819 if (!isTargetShuffle(N.getOpcode()))
5820 return false;
5821
5822 MVT VT = N.getSimpleValueType();
5823 if (!getTargetShuffleMask(N.getNode(), VT, true, Ops, Mask, IsUnary))
5824 return false;
5825
5826 SDValue V1 = Ops[0];
5827 SDValue V2 = IsUnary ? V1 : Ops[1];
5828
5829 V1 = peekThroughBitcasts(V1);
5830 V2 = peekThroughBitcasts(V2);
5831
5832 assert((VT.getSizeInBits() % Mask.size()) == 0 &&(static_cast <bool> ((VT.getSizeInBits() % Mask.size())
== 0 && "Illegal split of shuffle value type") ? void
(0) : __assert_fail ("(VT.getSizeInBits() % Mask.size()) == 0 && \"Illegal split of shuffle value type\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 5833, __extension__ __PRETTY_FUNCTION__))
5833 "Illegal split of shuffle value type")(static_cast <bool> ((VT.getSizeInBits() % Mask.size())
== 0 && "Illegal split of shuffle value type") ? void
(0) : __assert_fail ("(VT.getSizeInBits() % Mask.size()) == 0 && \"Illegal split of shuffle value type\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 5833, __extension__ __PRETTY_FUNCTION__))
;
5834 unsigned EltSizeInBits = VT.getSizeInBits() / Mask.size();
5835
5836 // Extract known constant input data.
5837 APInt UndefSrcElts[2];
5838 SmallVector<APInt, 32> SrcEltBits[2];
5839 bool IsSrcConstant[2] = {
5840 getTargetConstantBitsFromNode(V1, EltSizeInBits, UndefSrcElts[0],
5841 SrcEltBits[0], true, false),
5842 getTargetConstantBitsFromNode(V2, EltSizeInBits, UndefSrcElts[1],
5843 SrcEltBits[1], true, false)};
5844
5845 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
5846 int M = Mask[i];
5847
5848 // Already decoded as SM_SentinelZero / SM_SentinelUndef.
5849 if (M < 0)
5850 continue;
5851
5852 // Determine shuffle input and normalize the mask.
5853 unsigned SrcIdx = M / Size;
5854 SDValue V = M < Size ? V1 : V2;
5855 M %= Size;
5856
5857 // We are referencing an UNDEF input.
5858 if (V.isUndef()) {
5859 Mask[i] = SM_SentinelUndef;
5860 continue;
5861 }
5862
5863 // SCALAR_TO_VECTOR - only the first element is defined, and the rest UNDEF.
5864 // TODO: We currently only set UNDEF for integer types - floats use the same
5865 // registers as vectors and many of the scalar folded loads rely on the
5866 // SCALAR_TO_VECTOR pattern.
5867 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR &&
5868 (Size % V.getValueType().getVectorNumElements()) == 0) {
5869 int Scale = Size / V.getValueType().getVectorNumElements();
5870 int Idx = M / Scale;
5871 if (Idx != 0 && !VT.isFloatingPoint())
5872 Mask[i] = SM_SentinelUndef;
5873 else if (Idx == 0 && X86::isZeroNode(V.getOperand(0)))
5874 Mask[i] = SM_SentinelZero;
5875 continue;
5876 }
5877
5878 // Attempt to extract from the source's constant bits.
5879 if (IsSrcConstant[SrcIdx]) {
5880 if (UndefSrcElts[SrcIdx][M])
5881 Mask[i] = SM_SentinelUndef;
5882 else if (SrcEltBits[SrcIdx][M] == 0)
5883 Mask[i] = SM_SentinelZero;
5884 }
5885 }
5886
5887 assert(VT.getVectorNumElements() == Mask.size() &&(static_cast <bool> (VT.getVectorNumElements() == Mask.
size() && "Different mask size from vector size!") ? void
(0) : __assert_fail ("VT.getVectorNumElements() == Mask.size() && \"Different mask size from vector size!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 5888, __extension__ __PRETTY_FUNCTION__))
5888 "Different mask size from vector size!")(static_cast <bool> (VT.getVectorNumElements() == Mask.
size() && "Different mask size from vector size!") ? void
(0) : __assert_fail ("VT.getVectorNumElements() == Mask.size() && \"Different mask size from vector size!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 5888, __extension__ __PRETTY_FUNCTION__))
;
5889 return true;
5890}
5891
5892// Attempt to decode ops that could be represented as a shuffle mask.
5893// The decoded shuffle mask may contain a different number of elements to the
5894// destination value type.
5895static bool getFauxShuffleMask(SDValue N, SmallVectorImpl<int> &Mask,
5896 SmallVectorImpl<SDValue> &Ops,
5897 SelectionDAG &DAG) {
5898 Mask.clear();
5899 Ops.clear();
5900
5901 MVT VT = N.getSimpleValueType();
5902 unsigned NumElts = VT.getVectorNumElements();
5903 unsigned NumSizeInBits = VT.getSizeInBits();
5904 unsigned NumBitsPerElt = VT.getScalarSizeInBits();
5905 assert((NumBitsPerElt % 8) == 0 && (NumSizeInBits % 8) == 0 &&(static_cast <bool> ((NumBitsPerElt % 8) == 0 &&
(NumSizeInBits % 8) == 0 && "Expected byte aligned value types"
) ? void (0) : __assert_fail ("(NumBitsPerElt % 8) == 0 && (NumSizeInBits % 8) == 0 && \"Expected byte aligned value types\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 5906, __extension__ __PRETTY_FUNCTION__))
5906 "Expected byte aligned value types")(static_cast <bool> ((NumBitsPerElt % 8) == 0 &&
(NumSizeInBits % 8) == 0 && "Expected byte aligned value types"
) ? void (0) : __assert_fail ("(NumBitsPerElt % 8) == 0 && (NumSizeInBits % 8) == 0 && \"Expected byte aligned value types\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 5906, __extension__ __PRETTY_FUNCTION__))
;
5907
5908 unsigned Opcode = N.getOpcode();
5909 switch (Opcode) {
5910 case ISD::AND:
5911 case X86ISD::ANDNP: {
5912 // Attempt to decode as a per-byte mask.
5913 APInt UndefElts;
5914 SmallVector<APInt, 32> EltBits;
5915 SDValue N0 = N.getOperand(0);
5916 SDValue N1 = N.getOperand(1);
5917 bool IsAndN = (X86ISD::ANDNP == Opcode);
5918 uint64_t ZeroMask = IsAndN ? 255 : 0;
5919 if (!getTargetConstantBitsFromNode(IsAndN ? N0 : N1, 8, UndefElts, EltBits))
5920 return false;
5921 for (int i = 0, e = (int)EltBits.size(); i != e; ++i) {
5922 if (UndefElts[i]) {
5923 Mask.push_back(SM_SentinelUndef);
5924 continue;
5925 }
5926 uint64_t ByteBits = EltBits[i].getZExtValue();
5927 if (ByteBits != 0 && ByteBits != 255)
5928 return false;
5929 Mask.push_back(ByteBits == ZeroMask ? SM_SentinelZero : i);
5930 }
5931 Ops.push_back(IsAndN ? N1 : N0);
5932 return true;
5933 }
5934 case ISD::SCALAR_TO_VECTOR: {
5935 // Match against a scalar_to_vector of an extract from a vector,
5936 // for PEXTRW/PEXTRB we must handle the implicit zext of the scalar.
5937 SDValue N0 = N.getOperand(0);
5938 SDValue SrcExtract;
5939
5940 if ((N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5941 N0.getOperand(0).getValueType() == VT) ||
5942 (N0.getOpcode() == X86ISD::PEXTRW &&
5943 N0.getOperand(0).getValueType() == MVT::v8i16) ||
5944 (N0.getOpcode() == X86ISD::PEXTRB &&
5945 N0.getOperand(0).getValueType() == MVT::v16i8)) {
5946 SrcExtract = N0;
5947 }
5948
5949 if (!SrcExtract || !isa<ConstantSDNode>(SrcExtract.getOperand(1)))
5950 return false;
5951
5952 SDValue SrcVec = SrcExtract.getOperand(0);
5953 EVT SrcVT = SrcVec.getValueType();
5954 unsigned NumSrcElts = SrcVT.getVectorNumElements();
5955 unsigned NumZeros = (NumBitsPerElt / SrcVT.getScalarSizeInBits()) - 1;
5956
5957 unsigned SrcIdx = SrcExtract.getConstantOperandVal(1);
5958 if (NumSrcElts <= SrcIdx)
5959 return false;
5960
5961 Ops.push_back(SrcVec);
5962 Mask.push_back(SrcIdx);
5963 Mask.append(NumZeros, SM_SentinelZero);
5964 Mask.append(NumSrcElts - Mask.size(), SM_SentinelUndef);
5965 return true;
5966 }
5967 case X86ISD::PINSRB:
5968 case X86ISD::PINSRW: {
5969 SDValue InVec = N.getOperand(0);
5970 SDValue InScl = N.getOperand(1);
5971 uint64_t InIdx = N.getConstantOperandVal(2);
5972 assert(InIdx < NumElts && "Illegal insertion index")(static_cast <bool> (InIdx < NumElts && "Illegal insertion index"
) ? void (0) : __assert_fail ("InIdx < NumElts && \"Illegal insertion index\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 5972, __extension__ __PRETTY_FUNCTION__))
;
5973
5974 // Attempt to recognise a PINSR*(VEC, 0, Idx) shuffle pattern.
5975 if (X86::isZeroNode(InScl)) {
5976 Ops.push_back(InVec);
5977 for (unsigned i = 0; i != NumElts; ++i)
5978 Mask.push_back(i == InIdx ? SM_SentinelZero : (int)i);
5979 return true;
5980 }
5981
5982 // Attempt to recognise a PINSR*(PEXTR*) shuffle pattern.
5983 // TODO: Expand this to support INSERT_VECTOR_ELT/etc.
5984 unsigned ExOp =
5985 (X86ISD::PINSRB == Opcode ? X86ISD::PEXTRB : X86ISD::PEXTRW);
5986 if (InScl.getOpcode() != ExOp)
5987 return false;
5988
5989 SDValue ExVec = InScl.getOperand(0);
5990 uint64_t ExIdx = InScl.getConstantOperandVal(1);
5991 assert(ExIdx < NumElts && "Illegal extraction index")(static_cast <bool> (ExIdx < NumElts && "Illegal extraction index"
) ? void (0) : __assert_fail ("ExIdx < NumElts && \"Illegal extraction index\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 5991, __extension__ __PRETTY_FUNCTION__))
;
5992 Ops.push_back(InVec);
5993 Ops.push_back(ExVec);
5994 for (unsigned i = 0; i != NumElts; ++i)
5995 Mask.push_back(i == InIdx ? NumElts + ExIdx : i);
5996 return true;
5997 }
5998 case X86ISD::PACKSS:
5999 case X86ISD::PACKUS: {
6000 SDValue N0 = N.getOperand(0);
6001 SDValue N1 = N.getOperand(1);
6002 assert(N0.getValueType().getVectorNumElements() == (NumElts / 2) &&(static_cast <bool> (N0.getValueType().getVectorNumElements
() == (NumElts / 2) && N1.getValueType().getVectorNumElements
() == (NumElts / 2) && "Unexpected input value type")
? void (0) : __assert_fail ("N0.getValueType().getVectorNumElements() == (NumElts / 2) && N1.getValueType().getVectorNumElements() == (NumElts / 2) && \"Unexpected input value type\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 6004, __extension__ __PRETTY_FUNCTION__))
6003 N1.getValueType().getVectorNumElements() == (NumElts / 2) &&(static_cast <bool> (N0.getValueType().getVectorNumElements
() == (NumElts / 2) && N1.getValueType().getVectorNumElements
() == (NumElts / 2) && "Unexpected input value type")
? void (0) : __assert_fail ("N0.getValueType().getVectorNumElements() == (NumElts / 2) && N1.getValueType().getVectorNumElements() == (NumElts / 2) && \"Unexpected input value type\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 6004, __extension__ __PRETTY_FUNCTION__))
6004 "Unexpected input value type")(static_cast <bool> (N0.getValueType().getVectorNumElements
() == (NumElts / 2) && N1.getValueType().getVectorNumElements
() == (NumElts / 2) && "Unexpected input value type")
? void (0) : __assert_fail ("N0.getValueType().getVectorNumElements() == (NumElts / 2) && N1.getValueType().getVectorNumElements() == (NumElts / 2) && \"Unexpected input value type\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 6004, __extension__ __PRETTY_FUNCTION__))
;
6005
6006 // If we know input saturation won't happen we can treat this
6007 // as a truncation shuffle.
6008 if (Opcode == X86ISD::PACKSS) {
6009 if ((!N0.isUndef() && DAG.ComputeNumSignBits(N0) <= NumBitsPerElt) ||
6010 (!N1.isUndef() && DAG.ComputeNumSignBits(N1) <= NumBitsPerElt))
6011 return false;
6012 } else {
6013 APInt ZeroMask = APInt::getHighBitsSet(2 * NumBitsPerElt, NumBitsPerElt);
6014 if ((!N0.isUndef() && !DAG.MaskedValueIsZero(N0, ZeroMask)) ||
6015 (!N1.isUndef() && !DAG.MaskedValueIsZero(N1, ZeroMask)))
6016 return false;
6017 }
6018
6019 bool IsUnary = (N0 == N1);
6020
6021 Ops.push_back(N0);
6022 if (!IsUnary)
6023 Ops.push_back(N1);
6024
6025 createPackShuffleMask(VT, Mask, IsUnary);
6026 return true;
6027 }
6028 case X86ISD::VSHLI:
6029 case X86ISD::VSRLI: {
6030 uint64_t ShiftVal = N.getConstantOperandVal(1);
6031 // Out of range bit shifts are guaranteed to be zero.
6032 if (NumBitsPerElt <= ShiftVal) {
6033 Mask.append(NumElts, SM_SentinelZero);
6034 return true;
6035 }
6036
6037 // We can only decode 'whole byte' bit shifts as shuffles.
6038 if ((ShiftVal % 8) != 0)
6039 break;
6040
6041 uint64_t ByteShift = ShiftVal / 8;
6042 unsigned NumBytes = NumSizeInBits / 8;
6043 unsigned NumBytesPerElt = NumBitsPerElt / 8;
6044 Ops.push_back(N.getOperand(0));
6045
6046 // Clear mask to all zeros and insert the shifted byte indices.
6047 Mask.append(NumBytes, SM_SentinelZero);
6048
6049 if (X86ISD::VSHLI == Opcode) {
6050 for (unsigned i = 0; i != NumBytes; i += NumBytesPerElt)
6051 for (unsigned j = ByteShift; j != NumBytesPerElt; ++j)
6052 Mask[i + j] = i + j - ByteShift;
6053 } else {
6054 for (unsigned i = 0; i != NumBytes; i += NumBytesPerElt)
6055 for (unsigned j = ByteShift; j != NumBytesPerElt; ++j)
6056 Mask[i + j - ByteShift] = i + j;
6057 }
6058 return true;
6059 }
6060 case ISD::ZERO_EXTEND_VECTOR_INREG:
6061 case X86ISD::VZEXT: {
6062 // TODO - add support for VPMOVZX with smaller input vector types.
6063 SDValue Src = N.getOperand(0);
6064 MVT SrcVT = Src.getSimpleValueType();
6065 if (NumSizeInBits != SrcVT.getSizeInBits())
6066 break;
6067 DecodeZeroExtendMask(SrcVT.getScalarType(), VT, Mask);
6068 Ops.push_back(Src);
6069 return true;
6070 }
6071 }
6072
6073 return false;
6074}
6075
6076/// Removes unused shuffle source inputs and adjusts the shuffle mask accordingly.
6077static void resolveTargetShuffleInputsAndMask(SmallVectorImpl<SDValue> &Inputs,
6078 SmallVectorImpl<int> &Mask) {
6079 int MaskWidth = Mask.size();
6080 SmallVector<SDValue, 16> UsedInputs;
6081 for (int i = 0, e = Inputs.size(); i < e; ++i) {
6082 int lo = UsedInputs.size() * MaskWidth;
6083 int hi = lo + MaskWidth;
6084
6085 // Strip UNDEF input usage.
6086 if (Inputs[i].isUndef())
6087 for (int &M : Mask)
6088 if ((lo <= M) && (M < hi))
6089 M = SM_SentinelUndef;
6090
6091 // Check for unused inputs.
6092 if (any_of(Mask, [lo, hi](int i) { return (lo <= i) && (i < hi); })) {
6093 UsedInputs.push_back(Inputs[i]);
6094 continue;
6095 }
6096 for (int &M : Mask)
6097 if (lo <= M)
6098 M -= MaskWidth;
6099 }
6100 Inputs = UsedInputs;
6101}
6102
6103/// Calls setTargetShuffleZeroElements to resolve a target shuffle mask's inputs
6104/// and set the SM_SentinelUndef and SM_SentinelZero values. Then check the
6105/// remaining input indices in case we now have a unary shuffle and adjust the
6106/// inputs accordingly.
6107/// Returns true if the target shuffle mask was decoded.
6108static bool resolveTargetShuffleInputs(SDValue Op,
6109 SmallVectorImpl<SDValue> &Inputs,
6110 SmallVectorImpl<int> &Mask,
6111 SelectionDAG &DAG) {
6112 if (!setTargetShuffleZeroElements(Op, Mask, Inputs))
6113 if (!getFauxShuffleMask(Op, Mask, Inputs, DAG))
6114 return false;
6115
6116 resolveTargetShuffleInputsAndMask(Inputs, Mask);
6117 return true;
6118}
6119
6120/// Returns the scalar element that will make up the ith
6121/// element of the result of the vector shuffle.
6122static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
6123 unsigned Depth) {
6124 if (Depth == 6)
6125 return SDValue(); // Limit search depth.
6126
6127 SDValue V = SDValue(N, 0);
6128 EVT VT = V.getValueType();
6129 unsigned Opcode = V.getOpcode();
6130
6131 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
6132 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
6133 int Elt = SV->getMaskElt(Index);
6134
6135 if (Elt < 0)
6136 return DAG.getUNDEF(VT.getVectorElementType());
6137
6138 unsigned NumElems = VT.getVectorNumElements();
6139 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
6140 : SV->getOperand(1);
6141 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
6142 }
6143
6144 // Recurse into target specific vector shuffles to find scalars.
6145 if (isTargetShuffle(Opcode)) {
6146 MVT ShufVT = V.getSimpleValueType();
6147 MVT ShufSVT = ShufVT.getVectorElementType();
6148 int NumElems = (int)ShufVT.getVectorNumElements();
6149 SmallVector<int, 16> ShuffleMask;
6150 SmallVector<SDValue, 16> ShuffleOps;
6151 bool IsUnary;
6152
6153 if (!getTargetShuffleMask(N, ShufVT, true, ShuffleOps, ShuffleMask, IsUnary))
6154 return SDValue();
6155
6156 int Elt = ShuffleMask[Index];
6157 if (Elt == SM_SentinelZero)
6158 return ShufSVT.isInteger() ? DAG.getConstant(0, SDLoc(N), ShufSVT)
6159 : DAG.getConstantFP(+0.0, SDLoc(N), ShufSVT);
6160 if (Elt == SM_SentinelUndef)
6161 return DAG.getUNDEF(ShufSVT);
6162
6163 assert(0 <= Elt && Elt < (2*NumElems) && "Shuffle index out of range")(static_cast <bool> (0 <= Elt && Elt < (2
*NumElems) && "Shuffle index out of range") ? void (0
) : __assert_fail ("0 <= Elt && Elt < (2*NumElems) && \"Shuffle index out of range\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 6163, __extension__ __PRETTY_FUNCTION__))
;
6164 SDValue NewV = (Elt < NumElems) ? ShuffleOps[0] : ShuffleOps[1];
6165 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
6166 Depth+1);
6167 }
6168
6169 // Actual nodes that may contain scalar elements
6170 if (Opcode == ISD::BITCAST) {
6171 V = V.getOperand(0);
6172 EVT SrcVT = V.getValueType();
6173 unsigned NumElems = VT.getVectorNumElements();
6174
6175 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
6176 return SDValue();
6177 }
6178
6179 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6180 return (Index == 0) ? V.getOperand(0)
6181 : DAG.getUNDEF(VT.getVectorElementType());
6182
6183 if (V.getOpcode() == ISD::BUILD_VECTOR)
6184 return V.getOperand(Index);
6185
6186 return SDValue();
6187}
6188
6189// Use PINSRB/PINSRW/PINSRD to create a build vector.
6190static SDValue LowerBuildVectorAsInsert(SDValue Op, unsigned NonZeros,
6191 unsigned NumNonZero, unsigned NumZero,
6192 SelectionDAG &DAG,
6193 const X86Subtarget &Subtarget) {
6194 MVT VT = Op.getSimpleValueType();
6195 unsigned NumElts = VT.getVectorNumElements();
6196 assert(((VT == MVT::v8i16 && Subtarget.hasSSE2()) ||(static_cast <bool> (((VT == MVT::v8i16 && Subtarget
.hasSSE2()) || ((VT == MVT::v16i8 || VT == MVT::v4i32) &&
Subtarget.hasSSE41())) && "Illegal vector insertion"
) ? void (0) : __assert_fail ("((VT == MVT::v8i16 && Subtarget.hasSSE2()) || ((VT == MVT::v16i8 || VT == MVT::v4i32) && Subtarget.hasSSE41())) && \"Illegal vector insertion\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 6198, __extension__ __PRETTY_FUNCTION__))
6197 ((VT == MVT::v16i8 || VT == MVT::v4i32) && Subtarget.hasSSE41())) &&(static_cast <bool> (((VT == MVT::v8i16 && Subtarget
.hasSSE2()) || ((VT == MVT::v16i8 || VT == MVT::v4i32) &&
Subtarget.hasSSE41())) && "Illegal vector insertion"
) ? void (0) : __assert_fail ("((VT == MVT::v8i16 && Subtarget.hasSSE2()) || ((VT == MVT::v16i8 || VT == MVT::v4i32) && Subtarget.hasSSE41())) && \"Illegal vector insertion\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 6198, __extension__ __PRETTY_FUNCTION__))
6198 "Illegal vector insertion")(static_cast <bool> (((VT == MVT::v8i16 && Subtarget
.hasSSE2()) || ((VT == MVT::v16i8 || VT == MVT::v4i32) &&
Subtarget.hasSSE41())) && "Illegal vector insertion"
) ? void (0) : __assert_fail ("((VT == MVT::v8i16 && Subtarget.hasSSE2()) || ((VT == MVT::v16i8 || VT == MVT::v4i32) && Subtarget.hasSSE41())) && \"Illegal vector insertion\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 6198, __extension__ __PRETTY_FUNCTION__))
;
6199
6200 SDLoc dl(Op);
6201 SDValue V;
6202 bool First = true;
6203
6204 for (unsigned i = 0; i < NumElts; ++i) {
6205 bool IsNonZero = (NonZeros & (1 << i)) != 0;
6206 if (!IsNonZero)
6207 continue;
6208
6209 // If the build vector contains zeros or our first insertion is not the
6210 // first index then insert into zero vector to break any register
6211 // dependency else use SCALAR_TO_VECTOR/VZEXT_MOVL.
6212 if (First) {
6213 First = false;
6214 if (NumZero || 0 != i)
6215 V = getZeroVector(VT, Subtarget, DAG, dl);
6216 else {
6217 assert(0 == i && "Expected insertion into zero-index")(static_cast <bool> (0 == i && "Expected insertion into zero-index"
) ? void (0) : __assert_fail ("0 == i && \"Expected insertion into zero-index\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 6217, __extension__ __PRETTY_FUNCTION__))
;
6218 V = DAG.getAnyExtOrTrunc(Op.getOperand(i), dl, MVT::i32);
6219 V = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, V);
6220 V = DAG.getNode(X86ISD::VZEXT_MOVL, dl, MVT::v4i32, V);
6221 V = DAG.getBitcast(VT, V);
6222 continue;
6223 }
6224 }
6225 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, V, Op.getOperand(i),
6226 DAG.getIntPtrConstant(i, dl));
6227 }
6228
6229 return V;
6230}
6231
6232/// Custom lower build_vector of v16i8.
6233static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
6234 unsigned NumNonZero, unsigned NumZero,
6235 SelectionDAG &DAG,
6236 const X86Subtarget &Subtarget) {
6237 if (NumNonZero > 8 && !Subtarget.hasSSE41())
6238 return SDValue();
6239
6240 // SSE4.1 - use PINSRB to insert each byte directly.
6241 if (Subtarget.hasSSE41())
6242 return LowerBuildVectorAsInsert(Op, NonZeros, NumNonZero, NumZero, DAG,
6243 Subtarget);
6244
6245 SDLoc dl(Op);
6246 SDValue V;
6247 bool First = true;
6248
6249 // Pre-SSE4.1 - merge byte pairs and insert with PINSRW.
6250 for (unsigned i = 0; i < 16; ++i) {
6251 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
6252 if (ThisIsNonZero && First) {
6253 if (NumZero)
6254 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
6255 else
6256 V = DAG.getUNDEF(MVT::v8i16);
6257 First = false;
6258 }
6259
6260 if ((i & 1) != 0) {
6261 // FIXME: Investigate extending to i32 instead of just i16.
6262 // FIXME: Investigate combining the first 4 bytes as a i32 instead.
6263 SDValue ThisElt, LastElt;
6264 bool LastIsNonZero = (NonZeros & (1 << (i - 1))) != 0;
6265 if (LastIsNonZero) {
6266 LastElt =
6267 DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i - 1));
6268 }
6269 if (ThisIsNonZero) {
6270 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
6271 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16, ThisElt,
6272 DAG.getConstant(8, dl, MVT::i8));
6273 if (LastIsNonZero)
6274 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
6275 } else
6276 ThisElt = LastElt;
6277
6278 if (ThisElt) {
6279 if (1 == i) {
6280 V = NumZero ? DAG.getZExtOrTrunc(ThisElt, dl, MVT::i32)
6281 : DAG.getAnyExtOrTrunc(ThisElt, dl, MVT::i32);
6282 V = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, V);
6283 V = DAG.getNode(X86ISD::VZEXT_MOVL, dl, MVT::v4i32, V);
6284 V = DAG.getBitcast(MVT::v8i16, V);
6285 } else {
6286 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
6287 DAG.getIntPtrConstant(i / 2, dl));
6288 }
6289 }
6290 }
6291 }
6292
6293 return DAG.getBitcast(MVT::v16i8, V);
6294}
6295
6296/// Custom lower build_vector of v8i16.
6297static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
6298 unsigned NumNonZero, unsigned NumZero,
6299 SelectionDAG &DAG,
6300 const X86Subtarget &Subtarget) {
6301 if (NumNonZero > 4 && !Subtarget.hasSSE41())
6302 return SDValue();
6303
6304 // Use PINSRW to insert each byte directly.
6305 return LowerBuildVectorAsInsert(Op, NonZeros, NumNonZero, NumZero, DAG,
6306 Subtarget);
6307}
6308
6309/// Custom lower build_vector of v4i32 or v4f32.
6310static SDValue LowerBuildVectorv4x32(SDValue Op, SelectionDAG &DAG,
6311 const X86Subtarget &Subtarget) {
6312 // Find all zeroable elements.
6313 std::bitset<4> Zeroable;
6314 for (int i=0; i < 4; ++i) {
6315 SDValue Elt = Op->getOperand(i);
6316 Zeroable[i] = (Elt.isUndef() || X86::isZeroNode(Elt));
6317 }
6318 assert(Zeroable.size() - Zeroable.count() > 1 &&(static_cast <bool> (Zeroable.size() - Zeroable.count()
> 1 && "We expect at least two non-zero elements!"
) ? void (0) : __assert_fail ("Zeroable.size() - Zeroable.count() > 1 && \"We expect at least two non-zero elements!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 6319, __extension__ __PRETTY_FUNCTION__))
6319 "We expect at least two non-zero elements!")(static_cast <bool> (Zeroable.size() - Zeroable.count()
> 1 && "We expect at least two non-zero elements!"
) ? void (0) : __assert_fail ("Zeroable.size() - Zeroable.count() > 1 && \"We expect at least two non-zero elements!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 6319, __extension__ __PRETTY_FUNCTION__))
;
6320
6321 // We only know how to deal with build_vector nodes where elements are either
6322 // zeroable or extract_vector_elt with constant index.
6323 SDValue FirstNonZero;
6324 unsigned FirstNonZeroIdx;
6325 for (unsigned i=0; i < 4; ++i) {
6326 if (Zeroable[i])
6327 continue;
6328 SDValue Elt = Op->getOperand(i);
6329 if (Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6330 !isa<ConstantSDNode>(Elt.getOperand(1)))
6331 return SDValue();
6332 // Make sure that this node is extracting from a 128-bit vector.
6333 MVT VT = Elt.getOperand(0).getSimpleValueType();
6334 if (!VT.is128BitVector())
6335 return SDValue();
6336 if (!FirstNonZero.getNode()) {
6337 FirstNonZero = Elt;
6338 FirstNonZeroIdx = i;
6339 }
6340 }
6341
6342 assert(FirstNonZero.getNode() && "Unexpected build vector of all zeros!")(static_cast <bool> (FirstNonZero.getNode() && "Unexpected build vector of all zeros!"
) ? void (0) : __assert_fail ("FirstNonZero.getNode() && \"Unexpected build vector of all zeros!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 6342, __extension__ __PRETTY_FUNCTION__))
;
6343 SDValue V1 = FirstNonZero.getOperand(0);
6344 MVT VT = V1.getSimpleValueType();
6345
6346 // See if this build_vector can be lowered as a blend with zero.
6347 SDValue Elt;
6348 unsigned EltMaskIdx, EltIdx;
6349 int Mask[4];
6350 for (EltIdx = 0; EltIdx < 4; ++EltIdx) {
6351 if (Zeroable[EltIdx]) {
6352 // The zero vector will be on the right hand side.
6353 Mask[EltIdx] = EltIdx+4;
6354 continue;
6355 }
6356
6357 Elt = Op->getOperand(EltIdx);
6358 // By construction, Elt is a EXTRACT_VECTOR_ELT with constant index.
6359 EltMaskIdx = Elt.getConstantOperandVal(1);
6360 if (Elt.getOperand(0) != V1 || EltMaskIdx != EltIdx)
6361 break;
6362 Mask[EltIdx] = EltIdx;
6363 }
6364
6365 if (EltIdx == 4) {
6366 // Let the shuffle legalizer deal with blend operations.
6367 SDValue VZero = getZeroVector(VT, Subtarget, DAG, SDLoc(Op));
6368 if (V1.getSimpleValueType() != VT)
6369 V1 = DAG.getBitcast(VT, V1);
6370 return DAG.getVectorShuffle(VT, SDLoc(V1), V1, VZero, Mask);
6371 }
6372
6373 // See if we can lower this build_vector to a INSERTPS.
6374 if (!Subtarget.hasSSE41())
6375 return SDValue();
6376
6377 SDValue V2 = Elt.getOperand(0);
6378 if (Elt == FirstNonZero && EltIdx == FirstNonZeroIdx)
6379 V1 = SDValue();
6380
6381 bool CanFold = true;
6382 for (unsigned i = EltIdx + 1; i < 4 && CanFold; ++i) {
6383 if (Zeroable[i])
6384 continue;
6385
6386 SDValue Current = Op->getOperand(i);
6387 SDValue SrcVector = Current->getOperand(0);
6388 if (!V1.getNode())
6389 V1 = SrcVector;
6390 CanFold = (SrcVector == V1) && (Current.getConstantOperandVal(1) == i);
6391 }
6392
6393 if (!CanFold)
6394 return SDValue();
6395
6396 assert(V1.getNode() && "Expected at least two non-zero elements!")(static_cast <bool> (V1.getNode() && "Expected at least two non-zero elements!"
) ? void (0) : __assert_fail ("V1.getNode() && \"Expected at least two non-zero elements!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 6396, __extension__ __PRETTY_FUNCTION__))
;
6397 if (V1.getSimpleValueType() != MVT::v4f32)
6398 V1 = DAG.getBitcast(MVT::v4f32, V1);
6399 if (V2.getSimpleValueType() != MVT::v4f32)
6400 V2 = DAG.getBitcast(MVT::v4f32, V2);
6401
6402 // Ok, we can emit an INSERTPS instruction.
6403 unsigned ZMask = Zeroable.to_ulong();
6404
6405 unsigned InsertPSMask = EltMaskIdx << 6 | EltIdx << 4 | ZMask;
6406 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!")(static_cast <bool> ((InsertPSMask & ~0xFFu) == 0 &&
"Invalid mask!") ? void (0) : __assert_fail ("(InsertPSMask & ~0xFFu) == 0 && \"Invalid mask!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 6406, __extension__ __PRETTY_FUNCTION__))
;
6407 SDLoc DL(Op);
6408 SDValue Result = DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
6409 DAG.getIntPtrConstant(InsertPSMask, DL));
6410 return DAG.getBitcast(VT, Result);
6411}
6412
6413/// Return a vector logical shift node.
6414static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp, unsigned NumBits,
6415 SelectionDAG &DAG, const TargetLowering &TLI,
6416 const SDLoc &dl) {
6417 assert(VT.is128BitVector() && "Unknown type for VShift")(static_cast <bool> (VT.is128BitVector() && "Unknown type for VShift"
) ? void (0) : __assert_fail ("VT.is128BitVector() && \"Unknown type for VShift\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 6417, __extension__ __PRETTY_FUNCTION__))
;
6418 MVT ShVT = MVT::v16i8;
6419 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
6420 SrcOp = DAG.getBitcast(ShVT, SrcOp);
6421 MVT ScalarShiftTy = TLI.getScalarShiftAmountTy(DAG.getDataLayout(), VT);
6422 assert(NumBits % 8 == 0 && "Only support byte sized shifts")(static_cast <bool> (NumBits % 8 == 0 && "Only support byte sized shifts"
) ? void (0) : __assert_fail ("NumBits % 8 == 0 && \"Only support byte sized shifts\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 6422, __extension__ __PRETTY_FUNCTION__))
;
6423 SDValue ShiftVal = DAG.getConstant(NumBits/8, dl, ScalarShiftTy);
6424 return DAG.getBitcast(VT, DAG.getNode(Opc, dl, ShVT, SrcOp, ShiftVal));
6425}
6426
6427static SDValue LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, const SDLoc &dl,
6428 SelectionDAG &DAG) {
6429
6430 // Check if the scalar load can be widened into a vector load. And if
6431 // the address is "base + cst" see if the cst can be "absorbed" into
6432 // the shuffle mask.
6433 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
6434 SDValue Ptr = LD->getBasePtr();
6435 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
6436 return SDValue();
6437 EVT PVT = LD->getValueType(0);
6438 if (PVT != MVT::i32 && PVT != MVT::f32)
6439 return SDValue();
6440
6441 int FI = -1;
6442 int64_t Offset = 0;
6443 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
6444 FI = FINode->getIndex();
6445 Offset = 0;
6446 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
6447 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
6448 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
6449 Offset = Ptr.getConstantOperandVal(1);
6450 Ptr = Ptr.getOperand(0);
6451 } else {
6452 return SDValue();
6453 }
6454
6455 // FIXME: 256-bit vector instructions don't require a strict alignment,
6456 // improve this code to support it better.
6457 unsigned RequiredAlign = VT.getSizeInBits()/8;
6458 SDValue Chain = LD->getChain();
6459 // Make sure the stack object alignment is at least 16 or 32.
6460 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
6461 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
6462 if (MFI.isFixedObjectIndex(FI)) {
6463 // Can't change the alignment. FIXME: It's possible to compute
6464 // the exact stack offset and reference FI + adjust offset instead.
6465 // If someone *really* cares about this. That's the way to implement it.
6466 return SDValue();
6467 } else {
6468 MFI.setObjectAlignment(FI, RequiredAlign);
6469 }
6470 }
6471
6472 // (Offset % 16 or 32) must be multiple of 4. Then address is then
6473 // Ptr + (Offset & ~15).
6474 if (Offset < 0)
6475 return SDValue();
6476 if ((Offset % RequiredAlign) & 3)
6477 return SDValue();
6478 int64_t StartOffset = Offset & ~int64_t(RequiredAlign - 1);
6479 if (StartOffset) {
6480 SDLoc DL(Ptr);
6481 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
6482 DAG.getConstant(StartOffset, DL, Ptr.getValueType()));
6483 }
6484
6485 int EltNo = (Offset - StartOffset) >> 2;
6486 unsigned NumElems = VT.getVectorNumElements();
6487
6488 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
6489 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
6490 LD->getPointerInfo().getWithOffset(StartOffset));
6491
6492 SmallVector<int, 8> Mask(NumElems, EltNo);
6493
6494 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), Mask);
6495 }
6496
6497 return SDValue();
6498}
6499
6500/// Given the initializing elements 'Elts' of a vector of type 'VT', see if the
6501/// elements can be replaced by a single large load which has the same value as
6502/// a build_vector or insert_subvector whose loaded operands are 'Elts'.
6503///
6504/// Example: <load i32 *a, load i32 *a+4, zero, undef> -> zextload a
6505static SDValue EltsFromConsecutiveLoads(EVT VT, ArrayRef<SDValue> Elts,
6506 const SDLoc &DL, SelectionDAG &DAG,
6507 const X86Subtarget &Subtarget,
6508 bool isAfterLegalize) {
6509 unsigned NumElems = Elts.size();
6510
6511 int LastLoadedElt = -1;
6512 SmallBitVector LoadMask(NumElems, false);
6513 SmallBitVector ZeroMask(NumElems, false);
6514 SmallBitVector UndefMask(NumElems, false);
6
Calling constructor for 'SmallBitVector'
9
Returning from constructor for 'SmallBitVector'
6515
6516 // For each element in the initializer, see if we've found a load, zero or an
6517 // undef.
6518 for (unsigned i = 0; i < NumElems; ++i) {
10
Loop condition is true. Entering loop body
6519 SDValue Elt = peekThroughBitcasts(Elts[i]);
6520 if (!Elt.getNode())
11
Assuming the condition is false
12
Taking false branch
6521 return SDValue();
6522
6523 if (Elt.isUndef())
13
Taking false branch
6524 UndefMask[i] = true;
6525 else if (X86::isZeroNode(Elt) || ISD::isBuildVectorAllZeros(Elt.getNode()))
14
Assuming the condition is false
15
Assuming the condition is false
16
Taking false branch
6526 ZeroMask[i] = true;
6527 else if (ISD::isNON_EXTLoad(Elt.getNode())) {
17
Taking false branch
6528 LoadMask[i] = true;
6529 LastLoadedElt = i;
6530 // Each loaded element must be the correct fractional portion of the
6531 // requested vector load.
6532 if ((NumElems * Elt.getValueSizeInBits()) != VT.getSizeInBits())
6533 return SDValue();
6534 } else
6535 return SDValue();
6536 }
6537 assert((ZeroMask | UndefMask | LoadMask).count() == NumElems &&(static_cast <bool> ((ZeroMask | UndefMask | LoadMask).
count() == NumElems && "Incomplete element masks") ? void
(0) : __assert_fail ("(ZeroMask | UndefMask | LoadMask).count() == NumElems && \"Incomplete element masks\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 6538, __extension__ __PRETTY_FUNCTION__))
6538 "Incomplete element masks")(static_cast <bool> ((ZeroMask | UndefMask | LoadMask).
count() == NumElems && "Incomplete element masks") ? void
(0) : __assert_fail ("(ZeroMask | UndefMask | LoadMask).count() == NumElems && \"Incomplete element masks\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 6538, __extension__ __PRETTY_FUNCTION__))
;
6539
6540 // Handle Special Cases - all undef or undef/zero.
6541 if (UndefMask.count() == NumElems)
6542 return DAG.getUNDEF(VT);
6543
6544 // FIXME: Should we return this as a BUILD_VECTOR instead?
6545 if ((ZeroMask | UndefMask).count() == NumElems)
6546 return VT.isInteger() ? DAG.getConstant(0, DL, VT)
6547 : DAG.getConstantFP(0.0, DL, VT);
6548
6549 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6550 int FirstLoadedElt = LoadMask.find_first();
6551 SDValue EltBase = peekThroughBitcasts(Elts[FirstLoadedElt]);
6552 LoadSDNode *LDBase = cast<LoadSDNode>(EltBase);
6553 EVT LDBaseVT = EltBase.getValueType();
6554
6555 // Consecutive loads can contain UNDEFS but not ZERO elements.
6556 // Consecutive loads with UNDEFs and ZEROs elements require a
6557 // an additional shuffle stage to clear the ZERO elements.
6558 bool IsConsecutiveLoad = true;
6559 bool IsConsecutiveLoadWithZeros = true;
6560 for (int i = FirstLoadedElt + 1; i <= LastLoadedElt; ++i) {
6561 if (LoadMask[i]) {
6562 SDValue Elt = peekThroughBitcasts(Elts[i]);
6563 LoadSDNode *LD = cast<LoadSDNode>(Elt);
6564 if (!DAG.areNonVolatileConsecutiveLoads(
6565 LD, LDBase, Elt.getValueType().getStoreSizeInBits() / 8,
6566 i - FirstLoadedElt)) {
6567 IsConsecutiveLoad = false;
6568 IsConsecutiveLoadWithZeros = false;
6569 break;
6570 }
6571 } else if (ZeroMask[i]) {
6572 IsConsecutiveLoad = false;
6573 }
6574 }
6575
6576 SmallVector<LoadSDNode *, 8> Loads;
6577 for (int i = FirstLoadedElt; i <= LastLoadedElt; ++i)
6578 if (LoadMask[i])
6579 Loads.push_back(cast<LoadSDNode>(peekThroughBitcasts(Elts[i])));
6580
6581 auto CreateLoad = [&DAG, &DL, &Loads](EVT VT, LoadSDNode *LDBase) {
6582 auto MMOFlags = LDBase->getMemOperand()->getFlags();
6583 assert(!(MMOFlags & MachineMemOperand::MOVolatile) &&(static_cast <bool> (!(MMOFlags & MachineMemOperand
::MOVolatile) && "Cannot merge volatile loads.") ? void
(0) : __assert_fail ("!(MMOFlags & MachineMemOperand::MOVolatile) && \"Cannot merge volatile loads.\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 6584, __extension__ __PRETTY_FUNCTION__))
6584 "Cannot merge volatile loads.")(static_cast <bool> (!(MMOFlags & MachineMemOperand
::MOVolatile) && "Cannot merge volatile loads.") ? void
(0) : __assert_fail ("!(MMOFlags & MachineMemOperand::MOVolatile) && \"Cannot merge volatile loads.\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 6584, __extension__ __PRETTY_FUNCTION__))
;
6585 SDValue NewLd =
6586 DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
6587 LDBase->getPointerInfo(), LDBase->getAlignment(), MMOFlags);
6588 for (auto *LD : Loads)
6589 DAG.makeEquivalentMemoryOrdering(LD, NewLd);
6590 return NewLd;
6591 };
6592
6593 // LOAD - all consecutive load/undefs (must start/end with a load).
6594 // If we have found an entire vector of loads and undefs, then return a large
6595 // load of the entire vector width starting at the base pointer.
6596 // If the vector contains zeros, then attempt to shuffle those elements.
6597 if (FirstLoadedElt == 0 && LastLoadedElt == (int)(NumElems - 1) &&
6598 (IsConsecutiveLoad || IsConsecutiveLoadWithZeros)) {
6599 assert(LDBase && "Did not find base load for merging consecutive loads")(static_cast <bool> (LDBase && "Did not find base load for merging consecutive loads"
) ? void (0) : __assert_fail ("LDBase && \"Did not find base load for merging consecutive loads\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 6599, __extension__ __PRETTY_FUNCTION__))
;
6600 EVT EltVT = LDBase->getValueType(0);
6601 // Ensure that the input vector size for the merged loads matches the
6602 // cumulative size of the input elements.
6603 if (VT.getSizeInBits() != EltVT.getSizeInBits() * NumElems)
6604 return SDValue();
6605
6606 if (isAfterLegalize && !TLI.isOperationLegal(ISD::LOAD, VT))
6607 return SDValue();
6608
6609 // Don't create 256-bit non-temporal aligned loads without AVX2 as these
6610 // will lower to regular temporal loads and use the cache.
6611 if (LDBase->isNonTemporal() && LDBase->getAlignment() >= 32 &&
6612 VT.is256BitVector() && !Subtarget.hasInt256())
6613 return SDValue();
6614
6615 if (IsConsecutiveLoad)
6616 return CreateLoad(VT, LDBase);
6617
6618 // IsConsecutiveLoadWithZeros - we need to create a shuffle of the loaded
6619 // vector and a zero vector to clear out the zero elements.
6620 if (!isAfterLegalize && NumElems == VT.getVectorNumElements()) {
6621 SmallVector<int, 4> ClearMask(NumElems, -1);
6622 for (unsigned i = 0; i < NumElems; ++i) {
6623 if (ZeroMask[i])
6624 ClearMask[i] = i + NumElems;
6625 else if (LoadMask[i])
6626 ClearMask[i] = i;
6627 }
6628 SDValue V = CreateLoad(VT, LDBase);
6629 SDValue Z = VT.isInteger() ? DAG.getConstant(0, DL, VT)
6630 : DAG.getConstantFP(0.0, DL, VT);
6631 return DAG.getVectorShuffle(VT, DL, V, Z, ClearMask);
6632 }
6633 }
6634
6635 int LoadSize =
6636 (1 + LastLoadedElt - FirstLoadedElt) * LDBaseVT.getStoreSizeInBits();
6637
6638 // VZEXT_LOAD - consecutive 32/64-bit load/undefs followed by zeros/undefs.
6639 if (IsConsecutiveLoad && FirstLoadedElt == 0 &&
6640 (LoadSize == 32 || LoadSize == 64) &&
6641 ((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()))) {
6642 MVT VecSVT = VT.isFloatingPoint() ? MVT::getFloatingPointVT(LoadSize)
6643 : MVT::getIntegerVT(LoadSize);
6644 MVT VecVT = MVT::getVectorVT(VecSVT, VT.getSizeInBits() / LoadSize);
6645 if (TLI.isTypeLegal(VecVT)) {
6646 SDVTList Tys = DAG.getVTList(VecVT, MVT::Other);
6647 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
6648 SDValue ResNode =
6649 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, VecSVT,
6650 LDBase->getPointerInfo(),
6651 LDBase->getAlignment(),
6652 false/*isVolatile*/, true/*ReadMem*/,
6653 false/*WriteMem*/);
6654 for (auto *LD : Loads)
6655 DAG.makeEquivalentMemoryOrdering(LD, ResNode);
6656 return DAG.getBitcast(VT, ResNode);
6657 }
6658 }
6659
6660 return SDValue();
6661}
18
Potential leak of memory pointed to by 'UndefMask.X'
6662
6663static Constant *getConstantVector(MVT VT, const APInt &SplatValue,
6664 unsigned SplatBitSize, LLVMContext &C) {
6665 unsigned ScalarSize = VT.getScalarSizeInBits();
6666 unsigned NumElm = SplatBitSize / ScalarSize;
6667
6668 SmallVector<Constant *, 32> ConstantVec;
6669 for (unsigned i = 0; i < NumElm; i++) {
6670 APInt Val = SplatValue.extractBits(ScalarSize, ScalarSize * i);
6671 Constant *Const;
6672 if (VT.isFloatingPoint()) {
6673 if (ScalarSize == 32) {
6674 Const = ConstantFP::get(C, APFloat(APFloat::IEEEsingle(), Val));
6675 } else {
6676 assert(ScalarSize == 64 && "Unsupported floating point scalar size")(static_cast <bool> (ScalarSize == 64 && "Unsupported floating point scalar size"
) ? void (0) : __assert_fail ("ScalarSize == 64 && \"Unsupported floating point scalar size\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 6676, __extension__ __PRETTY_FUNCTION__))
;
6677 Const = ConstantFP::get(C, APFloat(APFloat::IEEEdouble(), Val));
6678 }
6679 } else
6680 Const = Constant::getIntegerValue(Type::getIntNTy(C, ScalarSize), Val);
6681 ConstantVec.push_back(Const);
6682 }
6683 return ConstantVector::get(ArrayRef<Constant *>(ConstantVec));
6684}
6685
6686static bool isUseOfShuffle(SDNode *N) {
6687 for (auto *U : N->uses()) {
6688 if (isTargetShuffle(U->getOpcode()))
6689 return true;
6690 if (U->getOpcode() == ISD::BITCAST) // Ignore bitcasts
6691 return isUseOfShuffle(U);
6692 }
6693 return false;
6694}
6695
6696// Check if the current node of build vector is a zero extended vector.
6697// // If so, return the value extended.
6698// // For example: (0,0,0,a,0,0,0,a,0,0,0,a,0,0,0,a) returns a.
6699// // NumElt - return the number of zero extended identical values.
6700// // EltType - return the type of the value include the zero extend.
6701static SDValue isSplatZeroExtended(const BuildVectorSDNode *Op,
6702 unsigned &NumElt, MVT &EltType) {
6703 SDValue ExtValue = Op->getOperand(0);
6704 unsigned NumElts = Op->getNumOperands();
6705 unsigned Delta = NumElts;
6706
6707 for (unsigned i = 1; i < NumElts; i++) {
6708 if (Op->getOperand(i) == ExtValue) {
6709 Delta = i;
6710 break;
6711 }
6712 if (!(Op->getOperand(i).isUndef() || isNullConstant(Op->getOperand(i))))
6713 return SDValue();
6714 }
6715 if (!isPowerOf2_32(Delta) || Delta == 1)
6716 return SDValue();
6717
6718 for (unsigned i = Delta; i < NumElts; i++) {
6719 if (i % Delta == 0) {
6720 if (Op->getOperand(i) != ExtValue)
6721 return SDValue();
6722 } else if (!(isNullConstant(Op->getOperand(i)) ||
6723 Op->getOperand(i).isUndef()))
6724 return SDValue();
6725 }
6726 unsigned EltSize = Op->getSimpleValueType(0).getScalarSizeInBits();
6727 unsigned ExtVTSize = EltSize * Delta;
6728 EltType = MVT::getIntegerVT(ExtVTSize);
6729 NumElt = NumElts / Delta;
6730 return ExtValue;
6731}
6732
6733/// Attempt to use the vbroadcast instruction to generate a splat value
6734/// from a splat BUILD_VECTOR which uses:
6735/// a. A single scalar load, or a constant.
6736/// b. Repeated pattern of constants (e.g. <0,1,0,1> or <0,1,2,3,0,1,2,3>).
6737///
6738/// The VBROADCAST node is returned when a pattern is found,
6739/// or SDValue() otherwise.
6740static SDValue lowerBuildVectorAsBroadcast(BuildVectorSDNode *BVOp,
6741 const X86Subtarget &Subtarget,
6742 SelectionDAG &DAG) {
6743 // VBROADCAST requires AVX.
6744 // TODO: Splats could be generated for non-AVX CPUs using SSE
6745 // instructions, but there's less potential gain for only 128-bit vectors.
6746 if (!Subtarget.hasAVX())
6747 return SDValue();
6748
6749 MVT VT = BVOp->getSimpleValueType(0);
6750 SDLoc dl(BVOp);
6751
6752 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&(static_cast <bool> ((VT.is128BitVector() || VT.is256BitVector
() || VT.is512BitVector()) && "Unsupported vector type for broadcast."
) ? void (0) : __assert_fail ("(VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) && \"Unsupported vector type for broadcast.\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 6753, __extension__ __PRETTY_FUNCTION__))
6753 "Unsupported vector type for broadcast.")(static_cast <bool> ((VT.is128BitVector() || VT.is256BitVector
() || VT.is512BitVector()) && "Unsupported vector type for broadcast."
) ? void (0) : __assert_fail ("(VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) && \"Unsupported vector type for broadcast.\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 6753, __extension__ __PRETTY_FUNCTION__))
;
6754
6755 BitVector UndefElements;
6756 SDValue Ld = BVOp->getSplatValue(&UndefElements);
6757
6758 // Attempt to use VBROADCASTM
6759 // From this paterrn:
6760 // a. t0 = (zext_i64 (bitcast_i8 v2i1 X))
6761 // b. t1 = (build_vector t0 t0)
6762 //
6763 // Create (VBROADCASTM v2i1 X)
6764 if (Subtarget.hasCDI() && (VT.is512BitVector() || Subtarget.hasVLX())) {
6765 MVT EltType = VT.getScalarType();
6766 unsigned NumElts = VT.getVectorNumElements();
6767 SDValue BOperand;
6768 SDValue ZeroExtended = isSplatZeroExtended(BVOp, NumElts, EltType);
6769 if ((ZeroExtended && ZeroExtended.getOpcode() == ISD::BITCAST) ||
6770 (Ld && Ld.getOpcode() == ISD::ZERO_EXTEND &&
6771 Ld.getOperand(0).getOpcode() == ISD::BITCAST)) {
6772 if (ZeroExtended)
6773 BOperand = ZeroExtended.getOperand(0);
6774 else
6775 BOperand = Ld.getOperand(0).getOperand(0);
6776 if (BOperand.getValueType().isVector() &&
6777 BOperand.getSimpleValueType().getVectorElementType() == MVT::i1) {
6778 if ((EltType == MVT::i64 && (VT.getVectorElementType() == MVT::i8 ||
6779 NumElts == 8)) || // for broadcastmb2q
6780 (EltType == MVT::i32 && (VT.getVectorElementType() == MVT::i16 ||
6781 NumElts == 16))) { // for broadcastmw2d
6782 SDValue Brdcst =
6783 DAG.getNode(X86ISD::VBROADCASTM, dl,
6784 MVT::getVectorVT(EltType, NumElts), BOperand);
6785 return DAG.getBitcast(VT, Brdcst);
6786 }
6787 }
6788 }
6789 }
6790
6791 // We need a splat of a single value to use broadcast, and it doesn't
6792 // make any sense if the value is only in one element of the vector.
6793 if (!Ld || (VT.getVectorNumElements() - UndefElements.count()) <= 1) {
6794 APInt SplatValue, Undef;
6795 unsigned SplatBitSize;
6796 bool HasUndef;
6797 // Check if this is a repeated constant pattern suitable for broadcasting.
6798 if (BVOp->isConstantSplat(SplatValue, Undef, SplatBitSize, HasUndef) &&
6799 SplatBitSize > VT.getScalarSizeInBits() &&
6800 SplatBitSize < VT.getSizeInBits()) {
6801 // Avoid replacing with broadcast when it's a use of a shuffle
6802 // instruction to preserve the present custom lowering of shuffles.
6803 if (isUseOfShuffle(BVOp) || BVOp->hasOneUse())
6804 return SDValue();
6805 // replace BUILD_VECTOR with broadcast of the repeated constants.
6806 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6807 LLVMContext *Ctx = DAG.getContext();
6808 MVT PVT = TLI.getPointerTy(DAG.getDataLayout());
6809 if (Subtarget.hasAVX()) {
6810 if (SplatBitSize <= 64 && Subtarget.hasAVX2() &&
6811 !(SplatBitSize == 64 && Subtarget.is32Bit())) {
6812 // Splatted value can fit in one INTEGER constant in constant pool.
6813 // Load the constant and broadcast it.
6814 MVT CVT = MVT::getIntegerVT(SplatBitSize);
6815 Type *ScalarTy = Type::getIntNTy(*Ctx, SplatBitSize);
6816 Constant *C = Constant::getIntegerValue(ScalarTy, SplatValue);
6817 SDValue CP = DAG.getConstantPool(C, PVT);
6818 unsigned Repeat = VT.getSizeInBits() / SplatBitSize;
6819
6820 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
6821 Ld = DAG.getLoad(
6822 CVT, dl, DAG.getEntryNode(), CP,
6823 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
6824 Alignment);
6825 SDValue Brdcst = DAG.getNode(X86ISD::VBROADCAST, dl,
6826 MVT::getVectorVT(CVT, Repeat), Ld);
6827 return DAG.getBitcast(VT, Brdcst);
6828 } else if (SplatBitSize == 32 || SplatBitSize == 64) {
6829 // Splatted value can fit in one FLOAT constant in constant pool.
6830 // Load the constant and broadcast it.
6831 // AVX have support for 32 and 64 bit broadcast for floats only.
6832 // No 64bit integer in 32bit subtarget.
6833 MVT CVT = MVT::getFloatingPointVT(SplatBitSize);
6834 // Lower the splat via APFloat directly, to avoid any conversion.
6835 Constant *C =
6836 SplatBitSize == 32
6837 ? ConstantFP::get(*Ctx,
6838 APFloat(APFloat::IEEEsingle(), SplatValue))
6839 : ConstantFP::get(*Ctx,
6840 APFloat(APFloat::IEEEdouble(), SplatValue));
6841 SDValue CP = DAG.getConstantPool(C, PVT);
6842 unsigned Repeat = VT.getSizeInBits() / SplatBitSize;
6843
6844 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
6845 Ld = DAG.getLoad(
6846 CVT, dl, DAG.getEntryNode(), CP,
6847 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
6848 Alignment);
6849 SDValue Brdcst = DAG.getNode(X86ISD::VBROADCAST, dl,
6850 MVT::getVectorVT(CVT, Repeat), Ld);
6851 return DAG.getBitcast(VT, Brdcst);
6852 } else if (SplatBitSize > 64) {
6853 // Load the vector of constants and broadcast it.
6854 MVT CVT = VT.getScalarType();
6855 Constant *VecC = getConstantVector(VT, SplatValue, SplatBitSize,
6856 *Ctx);
6857 SDValue VCP = DAG.getConstantPool(VecC, PVT);
6858 unsigned NumElm = SplatBitSize / VT.getScalarSizeInBits();
6859 unsigned Alignment = cast<ConstantPoolSDNode>(VCP)->getAlignment();
6860 Ld = DAG.getLoad(
6861 MVT::getVectorVT(CVT, NumElm), dl, DAG.getEntryNode(), VCP,
6862 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
6863 Alignment);
6864 SDValue Brdcst = DAG.getNode(X86ISD::SUBV_BROADCAST, dl, VT, Ld);
6865 return DAG.getBitcast(VT, Brdcst);
6866 }
6867 }
6868 }
6869 return SDValue();
6870 }
6871
6872 bool ConstSplatVal =
6873 (Ld.getOpcode() == ISD::Constant || Ld.getOpcode() == ISD::ConstantFP);
6874
6875 // Make sure that all of the users of a non-constant load are from the
6876 // BUILD_VECTOR node.
6877 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
6878 return SDValue();
6879
6880 unsigned ScalarSize = Ld.getValueSizeInBits();
6881 bool IsGE256 = (VT.getSizeInBits() >= 256);
6882
6883 // When optimizing for size, generate up to 5 extra bytes for a broadcast
6884 // instruction to save 8 or more bytes of constant pool data.
6885 // TODO: If multiple splats are generated to load the same constant,
6886 // it may be detrimental to overall size. There needs to be a way to detect
6887 // that condition to know if this is truly a size win.
6888 bool OptForSize = DAG.getMachineFunction().getFunction()->optForSize();
6889
6890 // Handle broadcasting a single constant scalar from the constant pool
6891 // into a vector.
6892 // On Sandybridge (no AVX2), it is still better to load a constant vector
6893 // from the constant pool and not to broadcast it from a scalar.
6894 // But override that restriction when optimizing for size.
6895 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
6896 if (ConstSplatVal && (Subtarget.hasAVX2() || OptForSize)) {
6897 EVT CVT = Ld.getValueType();
6898 assert(!CVT.isVector() && "Must not broadcast a vector type")(static_cast <bool> (!CVT.isVector() && "Must not broadcast a vector type"
) ? void (0) : __assert_fail ("!CVT.isVector() && \"Must not broadcast a vector type\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 6898, __extension__ __PRETTY_FUNCTION__))
;
6899
6900 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
6901 // For size optimization, also splat v2f64 and v2i64, and for size opt
6902 // with AVX2, also splat i8 and i16.
6903 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
6904 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
6905 (OptForSize && (ScalarSize == 64 || Subtarget.hasAVX2()))) {
6906 const Constant *C = nullptr;
6907 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
6908 C = CI->getConstantIntValue();
6909 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
6910 C = CF->getConstantFPValue();
6911
6912 assert(C && "Invalid constant type")(static_cast <bool> (C && "Invalid constant type"
) ? void (0) : __assert_fail ("C && \"Invalid constant type\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 6912, __extension__ __PRETTY_FUNCTION__))
;
6913
6914 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6915 SDValue CP =
6916 DAG.getConstantPool(C, TLI.getPointerTy(DAG.getDataLayout()));
6917 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
6918 Ld = DAG.getLoad(
6919 CVT, dl, DAG.getEntryNode(), CP,
6920 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
6921 Alignment);
6922
6923 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6924 }
6925 }
6926
6927 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
6928
6929 // Handle AVX2 in-register broadcasts.
6930 if (!IsLoad && Subtarget.hasInt256() &&
6931 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
6932 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6933
6934 // The scalar source must be a normal load.
6935 if (!IsLoad)
6936 return SDValue();
6937
6938 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
6939 (Subtarget.hasVLX() && ScalarSize == 64))
6940 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6941
6942 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
6943 // double since there is no vbroadcastsd xmm
6944 if (Subtarget.hasInt256() && Ld.getValueType().isInteger()) {
6945 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
6946 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6947 }
6948
6949 // Unsupported broadcast.
6950 return SDValue();
6951}
6952
6953/// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
6954/// underlying vector and index.
6955///
6956/// Modifies \p ExtractedFromVec to the real vector and returns the real
6957/// index.
6958static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
6959 SDValue ExtIdx) {
6960 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
6961 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
6962 return Idx;
6963
6964 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
6965 // lowered this:
6966 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
6967 // to:
6968 // (extract_vector_elt (vector_shuffle<2,u,u,u>
6969 // (extract_subvector (v8f32 %vreg0), Constant<4>),
6970 // undef)
6971 // Constant<0>)
6972 // In this case the vector is the extract_subvector expression and the index
6973 // is 2, as specified by the shuffle.
6974 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
6975 SDValue ShuffleVec = SVOp->getOperand(0);
6976 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
6977 assert(ShuffleVecVT.getVectorElementType() ==(static_cast <bool> (ShuffleVecVT.getVectorElementType(
) == ExtractedFromVec.getSimpleValueType().getVectorElementType
()) ? void (0) : __assert_fail ("ShuffleVecVT.getVectorElementType() == ExtractedFromVec.getSimpleValueType().getVectorElementType()"
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 6978, __extension__ __PRETTY_FUNCTION__))
6978 ExtractedFromVec.getSimpleValueType().getVectorElementType())(static_cast <bool> (ShuffleVecVT.getVectorElementType(
) == ExtractedFromVec.getSimpleValueType().getVectorElementType
()) ? void (0) : __assert_fail ("ShuffleVecVT.getVectorElementType() == ExtractedFromVec.getSimpleValueType().getVectorElementType()"
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 6978, __extension__ __PRETTY_FUNCTION__))
;
6979
6980 int ShuffleIdx = SVOp->getMaskElt(Idx);
6981 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
6982 ExtractedFromVec = ShuffleVec;
6983 return ShuffleIdx;
6984 }
6985 return Idx;
6986}
6987
6988static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
6989 MVT VT = Op.getSimpleValueType();
6990
6991 // Skip if insert_vec_elt is not supported.
6992 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6993 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
6994 return SDValue();
6995
6996 SDLoc DL(Op);
6997 unsigned NumElems = Op.getNumOperands();
6998
6999 SDValue VecIn1;
7000 SDValue VecIn2;
7001 SmallVector<unsigned, 4> InsertIndices;
7002 SmallVector<int, 8> Mask(NumElems, -1);
7003
7004 for (unsigned i = 0; i != NumElems; ++i) {
7005 unsigned Opc = Op.getOperand(i).getOpcode();
7006
7007 if (Opc == ISD::UNDEF)
7008 continue;
7009
7010 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
7011 // Quit if more than 1 elements need inserting.
7012 if (InsertIndices.size() > 1)
7013 return SDValue();
7014
7015 InsertIndices.push_back(i);
7016 continue;
7017 }
7018
7019 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
7020 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
7021
7022 // Quit if non-constant index.
7023 if (!isa<ConstantSDNode>(ExtIdx))
7024 return SDValue();
7025 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
7026
7027 // Quit if extracted from vector of different type.
7028 if (ExtractedFromVec.getValueType() != VT)
7029 return SDValue();
7030
7031 if (!VecIn1.getNode())
7032 VecIn1 = ExtractedFromVec;
7033 else if (VecIn1 != ExtractedFromVec) {
7034 if (!VecIn2.getNode())
7035 VecIn2 = ExtractedFromVec;
7036 else if (VecIn2 != ExtractedFromVec)
7037 // Quit if more than 2 vectors to shuffle
7038 return SDValue();
7039 }
7040
7041 if (ExtractedFromVec == VecIn1)
7042 Mask[i] = Idx;
7043 else if (ExtractedFromVec == VecIn2)
7044 Mask[i] = Idx + NumElems;
7045 }
7046
7047 if (!VecIn1.getNode())
7048 return SDValue();
7049
7050 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
7051 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, Mask);
7052
7053 for (unsigned Idx : InsertIndices)
7054 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
7055 DAG.getIntPtrConstant(Idx, DL));
7056
7057 return NV;
7058}
7059
7060static SDValue ConvertI1VectorToInteger(SDValue Op, SelectionDAG &DAG) {
7061 assert(ISD::isBuildVectorOfConstantSDNodes(Op.getNode()) &&(static_cast <bool> (ISD::isBuildVectorOfConstantSDNodes
(Op.getNode()) && Op.getScalarValueSizeInBits() == 1 &&
"Can not convert non-constant vector") ? void (0) : __assert_fail
("ISD::isBuildVectorOfConstantSDNodes(Op.getNode()) && Op.getScalarValueSizeInBits() == 1 && \"Can not convert non-constant vector\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 7063, __extension__ __PRETTY_FUNCTION__))
7062 Op.getScalarValueSizeInBits() == 1 &&(static_cast <bool> (ISD::isBuildVectorOfConstantSDNodes
(Op.getNode()) && Op.getScalarValueSizeInBits() == 1 &&
"Can not convert non-constant vector") ? void (0) : __assert_fail
("ISD::isBuildVectorOfConstantSDNodes(Op.getNode()) && Op.getScalarValueSizeInBits() == 1 && \"Can not convert non-constant vector\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 7063, __extension__ __PRETTY_FUNCTION__))
7063 "Can not convert non-constant vector")(static_cast <bool> (ISD::isBuildVectorOfConstantSDNodes
(Op.getNode()) && Op.getScalarValueSizeInBits() == 1 &&
"Can not convert non-constant vector") ? void (0) : __assert_fail
("ISD::isBuildVectorOfConstantSDNodes(Op.getNode()) && Op.getScalarValueSizeInBits() == 1 && \"Can not convert non-constant vector\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 7063, __extension__ __PRETTY_FUNCTION__))
;
7064 uint64_t Immediate = 0;
7065 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
7066 SDValue In = Op.getOperand(idx);
7067 if (!In.isUndef())
7068 Immediate |= (cast<ConstantSDNode>(In)->getZExtValue() & 0x1) << idx;
7069 }
7070 SDLoc dl(Op);
7071 MVT VT = MVT::getIntegerVT(std::max((int)Op.getValueSizeInBits(), 8));
7072 return DAG.getConstant(Immediate, dl, VT);
7073}
7074// Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
7075SDValue
7076X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
7077
7078 MVT VT = Op.getSimpleValueType();
7079 assert((VT.getVectorElementType() == MVT::i1) &&(static_cast <bool> ((VT.getVectorElementType() == MVT::
i1) && "Unexpected type in LowerBUILD_VECTORvXi1!") ?
void (0) : __assert_fail ("(VT.getVectorElementType() == MVT::i1) && \"Unexpected type in LowerBUILD_VECTORvXi1!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 7080, __extension__ __PRETTY_FUNCTION__))
7080 "Unexpected type in LowerBUILD_VECTORvXi1!")(static_cast <bool> ((VT.getVectorElementType() == MVT::
i1) && "Unexpected type in LowerBUILD_VECTORvXi1!") ?
void (0) : __assert_fail ("(VT.getVectorElementType() == MVT::i1) && \"Unexpected type in LowerBUILD_VECTORvXi1!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 7080, __extension__ __PRETTY_FUNCTION__))
;
7081
7082 SDLoc dl(Op);
7083 if (ISD::isBuildVectorAllZeros(Op.getNode()))
7084 return DAG.getTargetConstant(0, dl, VT);
7085
7086 if (ISD::isBuildVectorAllOnes(Op.getNode()))
7087 return DAG.getTargetConstant(1, dl, VT);
7088
7089 if (ISD::isBuildVectorOfConstantSDNodes(Op.getNode())) {
7090 if (VT == MVT::v64i1 && !Subtarget.is64Bit()) {
7091 // Split the pieces.
7092 SDValue Lower =
7093 DAG.getBuildVector(MVT::v32i1, dl, Op.getNode()->ops().slice(0, 32));
7094 SDValue Upper =
7095 DAG.getBuildVector(MVT::v32i1, dl, Op.getNode()->ops().slice(32, 32));
7096 // We have to manually lower both halves so getNode doesn't try to
7097 // reassemble the build_vector.
7098 Lower = LowerBUILD_VECTORvXi1(Lower, DAG);
7099 Upper = LowerBUILD_VECTORvXi1(Upper, DAG);
7100 return DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v64i1, Lower, Upper);
7101 }
7102 SDValue Imm = ConvertI1VectorToInteger(Op, DAG);
7103 if (Imm.getValueSizeInBits() == VT.getSizeInBits())
7104 return DAG.getBitcast(VT, Imm);
7105 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, Imm);
7106 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, ExtVec,
7107 DAG.getIntPtrConstant(0, dl));
7108 }
7109
7110 // Vector has one or more non-const elements
7111 uint64_t Immediate = 0;
7112 SmallVector<unsigned, 16> NonConstIdx;
7113 bool IsSplat = true;
7114 bool HasConstElts = false;
7115 int SplatIdx = -1;
7116 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
7117 SDValue In = Op.getOperand(idx);
7118 if (In.isUndef())
7119 continue;
7120 if (!isa<ConstantSDNode>(In))
7121 NonConstIdx.push_back(idx);
7122 else {
7123 Immediate |= (cast<ConstantSDNode>(In)->getZExtValue() & 0x1) << idx;
7124 HasConstElts = true;
7125 }
7126 if (SplatIdx < 0)
7127 SplatIdx = idx;
7128 else if (In != Op.getOperand(SplatIdx))
7129 IsSplat = false;
7130 }
7131
7132 // for splat use " (select i1 splat_elt, all-ones, all-zeroes)"
7133 if (IsSplat)
7134 return DAG.getSelect(dl, VT, Op.getOperand(SplatIdx),
7135 DAG.getConstant(1, dl, VT),
7136 DAG.getConstant(0, dl, VT));
7137
7138 // insert elements one by one
7139 SDValue DstVec;
7140 SDValue Imm;
7141 if (Immediate) {
7142 MVT ImmVT = MVT::getIntegerVT(std::max((int)VT.getSizeInBits(), 8));
7143 Imm = DAG.getConstant(Immediate, dl, ImmVT);
7144 }
7145 else if (HasConstElts)
7146 Imm = DAG.getConstant(0, dl, VT);
7147 else
7148 Imm = DAG.getUNDEF(VT);
7149 if (Imm.getValueSizeInBits() == VT.getSizeInBits())
7150 DstVec = DAG.getBitcast(VT, Imm);
7151 else {
7152 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, Imm);
7153 DstVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, ExtVec,
7154 DAG.getIntPtrConstant(0, dl));
7155 }
7156
7157 for (unsigned i = 0, e = NonConstIdx.size(); i != e; ++i) {
7158 unsigned InsertIdx = NonConstIdx[i];
7159 DstVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
7160 Op.getOperand(InsertIdx),
7161 DAG.getIntPtrConstant(InsertIdx, dl));
7162 }
7163 return DstVec;
7164}
7165
7166/// \brief Return true if \p N implements a horizontal binop and return the
7167/// operands for the horizontal binop into V0 and V1.
7168///
7169/// This is a helper function of LowerToHorizontalOp().
7170/// This function checks that the build_vector \p N in input implements a
7171/// horizontal operation. Parameter \p Opcode defines the kind of horizontal
7172/// operation to match.
7173/// For example, if \p Opcode is equal to ISD::ADD, then this function
7174/// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
7175/// is equal to ISD::SUB, then this function checks if this is a horizontal
7176/// arithmetic sub.
7177///
7178/// This function only analyzes elements of \p N whose indices are
7179/// in range [BaseIdx, LastIdx).
7180static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
7181 SelectionDAG &DAG,
7182 unsigned BaseIdx, unsigned LastIdx,
7183 SDValue &V0, SDValue &V1) {
7184 EVT VT = N->getValueType(0);
7185
7186 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!")(static_cast <bool> (BaseIdx * 2 <= LastIdx &&
"Invalid Indices in input!") ? void (0) : __assert_fail ("BaseIdx * 2 <= LastIdx && \"Invalid Indices in input!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 7186, __extension__ __PRETTY_FUNCTION__))
;
7187 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&(static_cast <bool> (VT.isVector() && VT.getVectorNumElements
() >= LastIdx && "Invalid Vector in input!") ? void
(0) : __assert_fail ("VT.isVector() && VT.getVectorNumElements() >= LastIdx && \"Invalid Vector in input!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 7188, __extension__ __PRETTY_FUNCTION__))
7188 "Invalid Vector in input!")(static_cast <bool> (VT.isVector() && VT.getVectorNumElements
() >= LastIdx && "Invalid Vector in input!") ? void
(0) : __assert_fail ("VT.isVector() && VT.getVectorNumElements() >= LastIdx && \"Invalid Vector in input!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 7188, __extension__ __PRETTY_FUNCTION__))
;
7189
7190 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
7191 bool CanFold = true;
7192 unsigned ExpectedVExtractIdx = BaseIdx;
7193 unsigned NumElts = LastIdx - BaseIdx;
7194 V0 = DAG.getUNDEF(VT);
7195 V1 = DAG.getUNDEF(VT);
7196
7197 // Check if N implements a horizontal binop.
7198 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
7199 SDValue Op = N->getOperand(i + BaseIdx);
7200
7201 // Skip UNDEFs.
7202 if (Op->isUndef()) {
7203 // Update the expected vector extract index.
7204 if (i * 2 == NumElts)
7205 ExpectedVExtractIdx = BaseIdx;
7206 ExpectedVExtractIdx += 2;
7207 continue;
7208 }
7209
7210 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
7211
7212 if (!CanFold)
7213 break;
7214
7215 SDValue Op0 = Op.getOperand(0);
7216 SDValue Op1 = Op.getOperand(1);
7217
7218 // Try to match the following pattern:
7219 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
7220 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
7221 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
7222 Op0.getOperand(0) == Op1.getOperand(0) &&
7223 isa<ConstantSDNode>(Op0.getOperand(1)) &&
7224 isa<ConstantSDNode>(Op1.getOperand(1)));
7225 if (!CanFold)
7226 break;
7227
7228 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
7229 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
7230
7231 if (i * 2 < NumElts) {
7232 if (V0.isUndef()) {
7233 V0 = Op0.getOperand(0);
7234 if (V0.getValueType() != VT)
7235 return false;
7236 }
7237 } else {
7238 if (V1.isUndef()) {
7239 V1 = Op0.getOperand(0);
7240 if (V1.getValueType() != VT)
7241 return false;
7242 }
7243 if (i * 2 == NumElts)
7244 ExpectedVExtractIdx = BaseIdx;
7245 }
7246
7247 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
7248 if (I0 == ExpectedVExtractIdx)
7249 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
7250 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
7251 // Try to match the following dag sequence:
7252 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
7253 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
7254 } else
7255 CanFold = false;
7256
7257 ExpectedVExtractIdx += 2;
7258 }
7259
7260 return CanFold;
7261}
7262
7263/// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
7264/// a concat_vector.
7265///
7266/// This is a helper function of LowerToHorizontalOp().
7267/// This function expects two 256-bit vectors called V0 and V1.
7268/// At first, each vector is split into two separate 128-bit vectors.
7269/// Then, the resulting 128-bit vectors are used to implement two
7270/// horizontal binary operations.
7271///
7272/// The kind of horizontal binary operation is defined by \p X86Opcode.
7273///
7274/// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
7275/// the two new horizontal binop.
7276/// When Mode is set, the first horizontal binop dag node would take as input
7277/// the lower 128-bit of V0 and the upper 128-bit of V0. The second
7278/// horizontal binop dag node would take as input the lower 128-bit of V1
7279/// and the upper 128-bit of V1.
7280/// Example:
7281/// HADD V0_LO, V0_HI
7282/// HADD V1_LO, V1_HI
7283///
7284/// Otherwise, the first horizontal binop dag node takes as input the lower
7285/// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
7286/// dag node takes the upper 128-bit of V0 and the upper 128-bit of V1.
7287/// Example:
7288/// HADD V0_LO, V1_LO
7289/// HADD V0_HI, V1_HI
7290///
7291/// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
7292/// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
7293/// the upper 128-bits of the result.
7294static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
7295 const SDLoc &DL, SelectionDAG &DAG,
7296 unsigned X86Opcode, bool Mode,
7297 bool isUndefLO, bool isUndefHI) {
7298 MVT VT = V0.getSimpleValueType();
7299 assert(VT.is256BitVector() && VT == V1.getSimpleValueType() &&(static_cast <bool> (VT.is256BitVector() && VT ==
V1.getSimpleValueType() && "Invalid nodes in input!"
) ? void (0) : __assert_fail ("VT.is256BitVector() && VT == V1.getSimpleValueType() && \"Invalid nodes in input!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 7300, __extension__ __PRETTY_FUNCTION__))
7300 "Invalid nodes in input!")(static_cast <bool> (VT.is256BitVector() && VT ==
V1.getSimpleValueType() && "Invalid nodes in input!"
) ? void (0) : __assert_fail ("VT.is256BitVector() && VT == V1.getSimpleValueType() && \"Invalid nodes in input!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318601/lib/Target/X86/X86ISelLowering.cpp"
, 7300, __extension__ __PRETTY_FUNCTION__))
;
7301
7302 unsigned NumElts = VT.getVectorNumElements();
7303 SDValue V0_LO = extract128BitVector(V0, 0, DAG, DL);
7304 SDValue V0_HI = extract128BitVector(V0, NumElts/2, DAG, DL);
7305 SDValue V1_LO = extract128BitVector(V1, 0, DAG, DL);
7306 SDValue V1_HI = extract128BitVector(V1, NumElts/2, DAG, DL);
7307 MVT NewVT = V0_LO.getSimpleValueType();
7308
7309 SDValue LO = DAG.getUNDEF(NewVT);
7310 SDValue HI = DAG.getUNDEF(NewVT);
7311
7312 if (Mode) {
7313 // Don't emit a horizontal binop if the result is expected to be UNDEF.
7314 if (!isUndefLO && !V0->isUndef())
7315 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
7316 if (!isUndefHI && !V1->isUndef())
7317 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
7318 } else {
7319 // Don't emit a horizontal binop if the result is expected to be UNDEF.
7320 if (!isUndefLO && (!V0_LO->isUndef() || !V1_LO->isUndef()))
7321 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
7322
7323 if (!isUndefHI && (!V0_HI->isUndef() || !V1_HI->isUndef()))
7324 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
7325 }
7326
7327 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
7328}
7329
7330/// Returns true iff \p BV builds a vector with the result equivalent to
7331/// the result of ADDSUB operation.
7332/// If true is returned then the operands of ADDSUB = Opnd0 +- Opnd1 operation
7333/// are written to the parameters \p Opnd0 and \p Opnd1.
7334static bool isAddSub(const BuildVectorSDNode *BV,
7335 const X86Subtarget &Subtarget, SelectionDAG &DAG,
7336 SDValue &Opnd0, SDValue &Opnd1) {
7337
7338 MVT VT = BV->getSimpleValueType(0);
7339 if ((!Subtarget.hasSSE3() || (VT != MVT::v4f32 && VT != MVT::v2f64)) &&
7340 (!Subtarget.hasAVX() || (VT != MVT::v8f32 && VT != MVT::v4f64)) &&
7341 (!Subtarget.hasAVX512() || (VT != MVT::v16f32 && VT != MVT::v8f64)))
7342 return false;
7343
7344 unsigned NumElts = VT.getVectorNumElements();
7345 SDValue InVec0 = DAG.getUNDEF(VT);
7346 SDValue InVec1 = DAG.getUNDEF(VT);
7347
7348 // Odd-numbered elements in the input build vector are obtained from
7349 // adding two integer/float elements.
7350 // Even-numbered elements in the input build vector are obtained from
7351 // subtracting two integer/float elements.
7352 unsigned ExpectedOpcode = ISD::FSUB;
7353 unsigned NextExpectedOpcode = ISD::FADD;
7354 bool AddFound = false;
7355 bool SubFound = false;
7356
7357 for (unsigned i = 0, e = NumElts; i != e; ++i) {
7358 SDValue Op = BV->getOperand(i);
7359
7360 // Skip 'undef' values.
7361 unsigned Opcode = Op.getOpcode();
7362 if (Opcode == ISD::UNDEF) {
7363 std::swap(ExpectedOpcode, NextExpectedOpcode);
7364 continue;
7365 }
7366
7367 // Early exit if we found an unexpected opcode.
7368 if (Opcode != ExpectedOpcode)
7369 return false;
7370
7371 SDValue Op0 = Op.getOperand(0);
7372 SDValue Op1 = Op.getOperand(1);
7373
7374 // Try to match the following pattern:
7375 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
7376 // Early exit if we cannot match that sequence.
7377 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
7378 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
7379 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
7380 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
7381 Op0.getOperand(1) != Op1.getOperand(1))
7382 return false;
7383
7384 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
7385 if (I0 != i)
7386 return false;
7387
7388 // We found a valid add/sub node. Update the information accordingly.
7389 if (i & 1)
7390 AddFound = true;
7391 else
7392 SubFound = true;
7393
7394 // Update InVec0 and InVec1.
7395 if (InVec0.isUndef()) {
7396 InVec0 = Op0.getOperand(0);
7397 if (InVec0.getSimpleValueType() != VT)
7398 return false;
7399 }
7400 if (InVec1.isUndef()) {
7401 InVec1 = Op1.getOperand(0);
7402 if (InVec1.getSimpleValueType() != VT)
7403 return false;
7404 }
7405
7406 // Make sure that operands in input to each add/sub node always
7407 // come from a same pair of vectors.
7408 if (InVec0 != Op0.getOperand(0)) {
7409 if (ExpectedOpcode == ISD::FSUB)
7410 return false;
7411
7412 // FADD is commutable. Try to commute the operands
7413 // and then test again.
7414 std::swap(Op0, Op1);
7415 if (InVec0 != Op0.getOperand(0))
7416 return false;
7417 }
7418
7419 if (InVec1 != Op1.getOperand(0))
7420 return false;
7421
7422 // Update the pair of expected opcodes.
7423 std::swap(ExpectedOpcode, NextExpectedOpcode);
7424 }
7425
7426 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
7427 if (!AddFound || !SubFound || InVec0.isUndef() || InVec1.isUndef())
7428 return false;
7429
7430 Opnd0 = InVec0;
7431 Opnd1 = InVec1;
7432 return true;
7433}
7434
7435/// Returns true if is possible to fold MUL and an idiom that has already been
7436/// recognized as ADDSUB(\p Opnd0, \p Opnd1) into FMADDSUB(x, y, \p Opnd1).
7437/// If (and only if) true is returned, the operands of FMADDSUB are written to
7438/// parameters \p Opnd0, \p Opnd1, \p Opnd2.
7439///
7440/// Prior to calling this function it should be known that there is some
7441/// SDNode that potentially can be replaced with an X86ISD::ADDSUB operation
7442/// using \p Opnd0 and \p Opnd1 as operands. Also, this method is called
7443/// before replacement of such SDNode with ADDSUB operation. Thus the number
7444/// of \p Opnd0 uses is expected to be equal to 2.
7445/// For example, this function may be called for the following IR:
7446/// %AB = fmul fast <2 x double> %A, %B
7447/// %Sub = fsub fast <2 x double> %AB, %C
7448/// %Add = fadd fast <2 x double> %AB, %C
7449/// %Addsub = shufflevector <2 x double> %Sub, <2 x double> %Add,
7450/// <2 x i32> <i32 0, i32 3>
7451/// There is a def for %Addsub here, which potentially can be replaced by
7452/// X86ISD::ADDSUB operation:
7453/// %Addsub = X86ISD::ADDSUB %AB, %C
7454/// and such ADDSUB can further be replaced with FMADDSUB:
7455/// %Addsub = FMADDSUB %A, %B, %C.
7456///
7457/// The main reason why this method is called before the replacement of the
7458/// recognized ADDSUB idiom with ADDSUB operation is that such replacement
7459/// is illegal sometimes. E.g. 512-bit ADDSUB is not available, while 512-bit
7460/// FMADDSUB is.
7461static bool isFMAddSub(const X86Subtarget &Subtarget, SelectionDAG &DAG,
7462 SDValue &Opnd0, SDValue &Opnd1, SDValue &Opnd2) {
7463 if (Opnd0.getOpcode() != ISD::FMUL || Opnd0->use_size() != 2 ||
7464 !Subtarget.hasAnyFMA())
7465 return false;
7466
7467 // FIXME: These checks must match the similar ones in
7468 // DAGCombiner::visitFADDForFMACombine. It would be good to have one
7469 // function that would answer if it is Ok to fuse MUL + ADD to FMADD
7470 // or MUL + ADDSUB to FMADDSUB.
7471 const TargetOptions &Options = DAG.getTarget().Options;
7472 bool AllowFusion =
7473 (Options.AllowFPOpFusion == FPOpFusion::Fast || Options.UnsafeFPMath);
7474 if (!AllowFusion)
7475 return false;
7476
7477 Opnd2 = Opnd1;
7478 Opnd1 = Opnd0.getOperand(1);
7479 Opnd0 = Opnd0.getOperand(0);
7480
7481 return true;
7482}
7483
7484/// Try to fold a build_vector that performs an 'addsub' or 'fmaddsub' operation
7485/// accordingly to X86ISD::ADDSUB or X86ISD::FMADDSUB node.
7486static SDValue lowerToAddSubOrFMAddSub(const BuildVectorSDNode *BV,
7487 const X86Subtarget &Subtarget,
7488 SelectionDAG &DAG) {
7489 SDValue Opnd0, Opnd1;
7490 if (!isAddSub(BV, Subtarget, DAG, Opnd0, Opnd1))
7491 return SDValue();
7492
7493 MVT VT = BV->getSimpleValueType(0);
7494 SDLoc DL(BV);
7495
7496 // Try to generate X86ISD::FMADDSUB node here.
7497 SDValue Opnd2;
7498 if (isFMAddSub(Subtarget, DAG, Opnd0, Opnd1, Opnd2))
7499 return DAG.getNode(X86ISD::FMADDSUB, DL, VT, Opnd0, Opnd1, Opnd2);
7500
7501 // Do not generate X86ISD::ADDSUB node for 512-bit types even though
7502 // the ADDSUB idiom has been successfully recognized. There are no known
7503 // X86 targets with 512-bit ADDSUB instructions!
7504 // 512-bit ADDSUB idiom recognition was needed only as part of FMADDSUB idiom
7505 // recognition.
7506 if (VT.i