Bug Summary

File:lib/Target/X86/X86ISelLowering.cpp
Warning:line 1116, column 10
Called C++ object pointer is null

Annotated Source Code

Press '?' to see keyboard shortcuts

clang -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name X86ISelLowering.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-eagerly-assume -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -mrelocation-model pic -pic-level 2 -mthread-model posix -fmath-errno -masm-verbose -mconstructor-aliases -munwind-tables -fuse-init-array -target-cpu x86-64 -dwarf-column-info -debugger-tuning=gdb -momit-leaf-frame-pointer -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-7/lib/clang/7.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-7~svn329677/build-llvm/lib/Target/X86 -I /build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86 -I /build/llvm-toolchain-snapshot-7~svn329677/build-llvm/include -I /build/llvm-toolchain-snapshot-7~svn329677/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/7.3.0/../../../../include/c++/7.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/7.3.0/../../../../include/x86_64-linux-gnu/c++/7.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/7.3.0/../../../../include/x86_64-linux-gnu/c++/7.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/7.3.0/../../../../include/c++/7.3.0/backward -internal-isystem /usr/include/clang/7.0.0/include/ -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-7/lib/clang/7.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++11 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-7~svn329677/build-llvm/lib/Target/X86 -ferror-limit 19 -fmessage-length 0 -fvisibility-inlines-hidden -fobjc-runtime=gcc -fdiagnostics-show-option -vectorize-loops -vectorize-slp -analyzer-checker optin.performance.Padding -analyzer-output=html -analyzer-config stable-report-filename=true -o /tmp/scan-build-2018-04-11-031539-24776-1 -x c++ /build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp

/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp

1//===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that X86 uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#include "X86ISelLowering.h"
16#include "Utils/X86ShuffleDecode.h"
17#include "X86CallingConv.h"
18#include "X86FrameLowering.h"
19#include "X86InstrBuilder.h"
20#include "X86IntrinsicsInfo.h"
21#include "X86MachineFunctionInfo.h"
22#include "X86ShuffleDecodeConstantPool.h"
23#include "X86TargetMachine.h"
24#include "X86TargetObjectFile.h"
25#include "llvm/ADT/SmallBitVector.h"
26#include "llvm/ADT/SmallSet.h"
27#include "llvm/ADT/Statistic.h"
28#include "llvm/ADT/StringExtras.h"
29#include "llvm/ADT/StringSwitch.h"
30#include "llvm/Analysis/EHPersonalities.h"
31#include "llvm/CodeGen/IntrinsicLowering.h"
32#include "llvm/CodeGen/MachineFrameInfo.h"
33#include "llvm/CodeGen/MachineFunction.h"
34#include "llvm/CodeGen/MachineInstrBuilder.h"
35#include "llvm/CodeGen/MachineJumpTableInfo.h"
36#include "llvm/CodeGen/MachineModuleInfo.h"
37#include "llvm/CodeGen/MachineRegisterInfo.h"
38#include "llvm/CodeGen/TargetLowering.h"
39#include "llvm/CodeGen/WinEHFuncInfo.h"
40#include "llvm/IR/CallSite.h"
41#include "llvm/IR/CallingConv.h"
42#include "llvm/IR/Constants.h"
43#include "llvm/IR/DerivedTypes.h"
44#include "llvm/IR/DiagnosticInfo.h"
45#include "llvm/IR/Function.h"
46#include "llvm/IR/GlobalAlias.h"
47#include "llvm/IR/GlobalVariable.h"
48#include "llvm/IR/Instructions.h"
49#include "llvm/IR/Intrinsics.h"
50#include "llvm/MC/MCAsmInfo.h"
51#include "llvm/MC/MCContext.h"
52#include "llvm/MC/MCExpr.h"
53#include "llvm/MC/MCSymbol.h"
54#include "llvm/Support/CommandLine.h"
55#include "llvm/Support/Debug.h"
56#include "llvm/Support/ErrorHandling.h"
57#include "llvm/Support/KnownBits.h"
58#include "llvm/Support/MathExtras.h"
59#include "llvm/Target/TargetOptions.h"
60#include <algorithm>
61#include <bitset>
62#include <cctype>
63#include <numeric>
64using namespace llvm;
65
66#define DEBUG_TYPE"x86-isel" "x86-isel"
67
68STATISTIC(NumTailCalls, "Number of tail calls")static llvm::Statistic NumTailCalls = {"x86-isel", "NumTailCalls"
, "Number of tail calls", {0}, {false}}
;
69
70static cl::opt<bool> ExperimentalVectorWideningLegalization(
71 "x86-experimental-vector-widening-legalization", cl::init(false),
72 cl::desc("Enable an experimental vector type legalization through widening "
73 "rather than promotion."),
74 cl::Hidden);
75
76static cl::opt<int> ExperimentalPrefLoopAlignment(
77 "x86-experimental-pref-loop-alignment", cl::init(4),
78 cl::desc("Sets the preferable loop alignment for experiments "
79 "(the last x86-experimental-pref-loop-alignment bits"
80 " of the loop header PC will be 0)."),
81 cl::Hidden);
82
83static cl::opt<bool> MulConstantOptimization(
84 "mul-constant-optimization", cl::init(true),
85 cl::desc("Replace 'mul x, Const' with more effective instructions like "
86 "SHIFT, LEA, etc."),
87 cl::Hidden);
88
89/// Call this when the user attempts to do something unsupported, like
90/// returning a double without SSE2 enabled on x86_64. This is not fatal, unlike
91/// report_fatal_error, so calling code should attempt to recover without
92/// crashing.
93static void errorUnsupported(SelectionDAG &DAG, const SDLoc &dl,
94 const char *Msg) {
95 MachineFunction &MF = DAG.getMachineFunction();
96 DAG.getContext()->diagnose(
97 DiagnosticInfoUnsupported(MF.getFunction(), Msg, dl.getDebugLoc()));
98}
99
100X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
101 const X86Subtarget &STI)
102 : TargetLowering(TM), Subtarget(STI) {
103 bool UseX87 = !Subtarget.useSoftFloat() && Subtarget.hasX87();
104 X86ScalarSSEf64 = Subtarget.hasSSE2();
105 X86ScalarSSEf32 = Subtarget.hasSSE1();
106 MVT PtrVT = MVT::getIntegerVT(TM.getPointerSizeInBits(0));
107
108 // Set up the TargetLowering object.
109
110 // X86 is weird. It always uses i8 for shift amounts and setcc results.
111 setBooleanContents(ZeroOrOneBooleanContent);
112 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
113 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
114
115 // For 64-bit, since we have so many registers, use the ILP scheduler.
116 // For 32-bit, use the register pressure specific scheduling.
117 // For Atom, always use ILP scheduling.
118 if (Subtarget.isAtom())
119 setSchedulingPreference(Sched::ILP);
120 else if (Subtarget.is64Bit())
121 setSchedulingPreference(Sched::ILP);
122 else
123 setSchedulingPreference(Sched::RegPressure);
124 const X86RegisterInfo *RegInfo = Subtarget.getRegisterInfo();
125 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
126
127 // Bypass expensive divides and use cheaper ones.
128 if (TM.getOptLevel() >= CodeGenOpt::Default) {
129 if (Subtarget.hasSlowDivide32())
130 addBypassSlowDiv(32, 8);
131 if (Subtarget.hasSlowDivide64() && Subtarget.is64Bit())
132 addBypassSlowDiv(64, 32);
133 }
134
135 if (Subtarget.isTargetKnownWindowsMSVC() ||
136 Subtarget.isTargetWindowsItanium()) {
137 // Setup Windows compiler runtime calls.
138 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
139 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
140 setLibcallName(RTLIB::SREM_I64, "_allrem");
141 setLibcallName(RTLIB::UREM_I64, "_aullrem");
142 setLibcallName(RTLIB::MUL_I64, "_allmul");
143 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
144 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
145 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
146 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
147 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
148 }
149
150 if (Subtarget.isTargetDarwin()) {
151 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
152 setUseUnderscoreSetJmp(false);
153 setUseUnderscoreLongJmp(false);
154 } else if (Subtarget.isTargetWindowsGNU()) {
155 // MS runtime is weird: it exports _setjmp, but longjmp!
156 setUseUnderscoreSetJmp(true);
157 setUseUnderscoreLongJmp(false);
158 } else {
159 setUseUnderscoreSetJmp(true);
160 setUseUnderscoreLongJmp(true);
161 }
162
163 // Set up the register classes.
164 addRegisterClass(MVT::i8, &X86::GR8RegClass);
165 addRegisterClass(MVT::i16, &X86::GR16RegClass);
166 addRegisterClass(MVT::i32, &X86::GR32RegClass);
167 if (Subtarget.is64Bit())
168 addRegisterClass(MVT::i64, &X86::GR64RegClass);
169
170 for (MVT VT : MVT::integer_valuetypes())
171 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
172
173 // We don't accept any truncstore of integer registers.
174 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
175 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
176 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
177 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
178 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
179 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
180
181 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
182
183 // SETOEQ and SETUNE require checking two conditions.
184 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
185 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
186 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
187 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
188 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
189 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
190
191 // Integer absolute.
192 if (Subtarget.hasCMov()) {
193 setOperationAction(ISD::ABS , MVT::i16 , Custom);
194 setOperationAction(ISD::ABS , MVT::i32 , Custom);
195 if (Subtarget.is64Bit())
196 setOperationAction(ISD::ABS , MVT::i64 , Custom);
197 }
198
199 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
200 // operation.
201 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
202 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
203 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
204
205 if (Subtarget.is64Bit()) {
206 if (!Subtarget.useSoftFloat() && Subtarget.hasAVX512())
207 // f32/f64 are legal, f80 is custom.
208 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
209 else
210 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
211 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
212 } else if (!Subtarget.useSoftFloat()) {
213 // We have an algorithm for SSE2->double, and we turn this into a
214 // 64-bit FILD followed by conditional FADD for other targets.
215 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
216 // We have an algorithm for SSE2, and we turn this into a 64-bit
217 // FILD or VCVTUSI2SS/SD for other targets.
218 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
219 }
220
221 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
222 // this operation.
223 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
224 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
225
226 if (!Subtarget.useSoftFloat()) {
227 // SSE has no i16 to fp conversion, only i32.
228 if (X86ScalarSSEf32) {
229 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
230 // f32 and f64 cases are Legal, f80 case is not
231 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
232 } else {
233 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
234 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
235 }
236 } else {
237 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
238 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
239 }
240
241 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
242 // this operation.
243 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
244 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
245
246 if (!Subtarget.useSoftFloat()) {
247 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
248 // are Legal, f80 is custom lowered.
249 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
250 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
251
252 if (X86ScalarSSEf32) {
253 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
254 // f32 and f64 cases are Legal, f80 case is not
255 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
256 } else {
257 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
258 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
259 }
260 } else {
261 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
262 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Expand);
263 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Expand);
264 }
265
266 // Handle FP_TO_UINT by promoting the destination to a larger signed
267 // conversion.
268 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
269 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
270 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
271
272 if (Subtarget.is64Bit()) {
273 if (!Subtarget.useSoftFloat() && Subtarget.hasAVX512()) {
274 // FP_TO_UINT-i32/i64 is legal for f32/f64, but custom for f80.
275 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
276 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
277 } else {
278 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
279 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
280 }
281 } else if (!Subtarget.useSoftFloat()) {
282 // Since AVX is a superset of SSE3, only check for SSE here.
283 if (Subtarget.hasSSE1() && !Subtarget.hasSSE3())
284 // Expand FP_TO_UINT into a select.
285 // FIXME: We would like to use a Custom expander here eventually to do
286 // the optimal thing for SSE vs. the default expansion in the legalizer.
287 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
288 else
289 // With AVX512 we can use vcvts[ds]2usi for f32/f64->i32, f80 is custom.
290 // With SSE3 we can use fisttpll to convert to a signed i64; without
291 // SSE, we're stuck with a fistpll.
292 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
293
294 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
295 }
296
297 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
298 if (!X86ScalarSSEf64) {
299 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
300 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
301 if (Subtarget.is64Bit()) {
302 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
303 // Without SSE, i64->f64 goes through memory.
304 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
305 }
306 } else if (!Subtarget.is64Bit())
307 setOperationAction(ISD::BITCAST , MVT::i64 , Custom);
308
309 // Scalar integer divide and remainder are lowered to use operations that
310 // produce two results, to match the available instructions. This exposes
311 // the two-result form to trivial CSE, which is able to combine x/y and x%y
312 // into a single instruction.
313 //
314 // Scalar integer multiply-high is also lowered to use two-result
315 // operations, to match the available instructions. However, plain multiply
316 // (low) operations are left as Legal, as there are single-result
317 // instructions for this in x86. Using the two-result multiply instructions
318 // when both high and low results are needed must be arranged by dagcombine.
319 for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
320 setOperationAction(ISD::MULHS, VT, Expand);
321 setOperationAction(ISD::MULHU, VT, Expand);
322 setOperationAction(ISD::SDIV, VT, Expand);
323 setOperationAction(ISD::UDIV, VT, Expand);
324 setOperationAction(ISD::SREM, VT, Expand);
325 setOperationAction(ISD::UREM, VT, Expand);
326 }
327
328 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
329 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
330 for (auto VT : { MVT::f32, MVT::f64, MVT::f80, MVT::f128,
331 MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
332 setOperationAction(ISD::BR_CC, VT, Expand);
333 setOperationAction(ISD::SELECT_CC, VT, Expand);
334 }
335 if (Subtarget.is64Bit())
336 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
337 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
338 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
339 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
340 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
341
342 setOperationAction(ISD::FREM , MVT::f32 , Expand);
343 setOperationAction(ISD::FREM , MVT::f64 , Expand);
344 setOperationAction(ISD::FREM , MVT::f80 , Expand);
345 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
346
347 // Promote the i8 variants and force them on up to i32 which has a shorter
348 // encoding.
349 setOperationPromotedToType(ISD::CTTZ , MVT::i8 , MVT::i32);
350 setOperationPromotedToType(ISD::CTTZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
351 if (!Subtarget.hasBMI()) {
352 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
353 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
354 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Legal);
355 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Legal);
356 if (Subtarget.is64Bit()) {
357 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
358 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Legal);
359 }
360 }
361
362 if (Subtarget.hasLZCNT()) {
363 // When promoting the i8 variants, force them to i32 for a shorter
364 // encoding.
365 setOperationPromotedToType(ISD::CTLZ , MVT::i8 , MVT::i32);
366 setOperationPromotedToType(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
367 } else {
368 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
369 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
370 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
371 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
372 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
373 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
374 if (Subtarget.is64Bit()) {
375 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
376 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
377 }
378 }
379
380 // Special handling for half-precision floating point conversions.
381 // If we don't have F16C support, then lower half float conversions
382 // into library calls.
383 if (Subtarget.useSoftFloat() || !Subtarget.hasF16C()) {
384 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
385 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
386 }
387
388 // There's never any support for operations beyond MVT::f32.
389 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
390 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
391 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
392 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
393
394 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
395 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
396 setLoadExtAction(ISD::EXTLOAD, MVT::f80, MVT::f16, Expand);
397 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
398 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
399 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
400
401 if (Subtarget.hasPOPCNT()) {
402 setOperationPromotedToType(ISD::CTPOP, MVT::i8, MVT::i32);
403 } else {
404 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
405 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
406 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
407 if (Subtarget.is64Bit())
408 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
409 }
410
411 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
412
413 if (!Subtarget.hasMOVBE())
414 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
415
416 // These should be promoted to a larger select which is supported.
417 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
418 // X86 wants to expand cmov itself.
419 for (auto VT : { MVT::f32, MVT::f64, MVT::f80, MVT::f128 }) {
420 setOperationAction(ISD::SELECT, VT, Custom);
421 setOperationAction(ISD::SETCC, VT, Custom);
422 }
423 for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
424 if (VT == MVT::i64 && !Subtarget.is64Bit())
425 continue;
426 setOperationAction(ISD::SELECT, VT, Custom);
427 setOperationAction(ISD::SETCC, VT, Custom);
428 }
429
430 // Custom action for SELECT MMX and expand action for SELECT_CC MMX
431 setOperationAction(ISD::SELECT, MVT::x86mmx, Custom);
432 setOperationAction(ISD::SELECT_CC, MVT::x86mmx, Expand);
433
434 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
435 // NOTE: EH_SJLJ_SETJMP/_LONGJMP are not recommended, since
436 // LLVM/Clang supports zero-cost DWARF and SEH exception handling.
437 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
438 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
439 setOperationAction(ISD::EH_SJLJ_SETUP_DISPATCH, MVT::Other, Custom);
440 if (TM.Options.ExceptionModel == ExceptionHandling::SjLj)
441 setLibcallName(RTLIB::UNWIND_RESUME, "_Unwind_SjLj_Resume");
442
443 // Darwin ABI issue.
444 for (auto VT : { MVT::i32, MVT::i64 }) {
445 if (VT == MVT::i64 && !Subtarget.is64Bit())
446 continue;
447 setOperationAction(ISD::ConstantPool , VT, Custom);
448 setOperationAction(ISD::JumpTable , VT, Custom);
449 setOperationAction(ISD::GlobalAddress , VT, Custom);
450 setOperationAction(ISD::GlobalTLSAddress, VT, Custom);
451 setOperationAction(ISD::ExternalSymbol , VT, Custom);
452 setOperationAction(ISD::BlockAddress , VT, Custom);
453 }
454
455 // 64-bit shl, sra, srl (iff 32-bit x86)
456 for (auto VT : { MVT::i32, MVT::i64 }) {
457 if (VT == MVT::i64 && !Subtarget.is64Bit())
458 continue;
459 setOperationAction(ISD::SHL_PARTS, VT, Custom);
460 setOperationAction(ISD::SRA_PARTS, VT, Custom);
461 setOperationAction(ISD::SRL_PARTS, VT, Custom);
462 }
463
464 if (Subtarget.hasSSEPrefetch() || Subtarget.has3DNow())
465 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
466
467 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
468
469 // Expand certain atomics
470 for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
471 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
472 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
473 setOperationAction(ISD::ATOMIC_LOAD_ADD, VT, Custom);
474 setOperationAction(ISD::ATOMIC_LOAD_OR, VT, Custom);
475 setOperationAction(ISD::ATOMIC_LOAD_XOR, VT, Custom);
476 setOperationAction(ISD::ATOMIC_LOAD_AND, VT, Custom);
477 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
478 }
479
480 if (Subtarget.hasCmpxchg16b()) {
481 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
482 }
483
484 // FIXME - use subtarget debug flags
485 if (!Subtarget.isTargetDarwin() && !Subtarget.isTargetELF() &&
486 !Subtarget.isTargetCygMing() && !Subtarget.isTargetWin64() &&
487 TM.Options.ExceptionModel != ExceptionHandling::SjLj) {
488 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
489 }
490
491 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
492 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
493
494 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
495 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
496
497 setOperationAction(ISD::TRAP, MVT::Other, Legal);
498 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
499
500 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
501 setOperationAction(ISD::VASTART , MVT::Other, Custom);
502 setOperationAction(ISD::VAEND , MVT::Other, Expand);
503 bool Is64Bit = Subtarget.is64Bit();
504 setOperationAction(ISD::VAARG, MVT::Other, Is64Bit ? Custom : Expand);
505 setOperationAction(ISD::VACOPY, MVT::Other, Is64Bit ? Custom : Expand);
506
507 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
508 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
509
510 setOperationAction(ISD::DYNAMIC_STACKALLOC, PtrVT, Custom);
511
512 // GC_TRANSITION_START and GC_TRANSITION_END need custom lowering.
513 setOperationAction(ISD::GC_TRANSITION_START, MVT::Other, Custom);
514 setOperationAction(ISD::GC_TRANSITION_END, MVT::Other, Custom);
515
516 if (!Subtarget.useSoftFloat() && X86ScalarSSEf64) {
517 // f32 and f64 use SSE.
518 // Set up the FP register classes.
519 addRegisterClass(MVT::f32, Subtarget.hasAVX512() ? &X86::FR32XRegClass
520 : &X86::FR32RegClass);
521 addRegisterClass(MVT::f64, Subtarget.hasAVX512() ? &X86::FR64XRegClass
522 : &X86::FR64RegClass);
523
524 for (auto VT : { MVT::f32, MVT::f64 }) {
525 // Use ANDPD to simulate FABS.
526 setOperationAction(ISD::FABS, VT, Custom);
527
528 // Use XORP to simulate FNEG.
529 setOperationAction(ISD::FNEG, VT, Custom);
530
531 // Use ANDPD and ORPD to simulate FCOPYSIGN.
532 setOperationAction(ISD::FCOPYSIGN, VT, Custom);
533
534 // We don't support sin/cos/fmod
535 setOperationAction(ISD::FSIN , VT, Expand);
536 setOperationAction(ISD::FCOS , VT, Expand);
537 setOperationAction(ISD::FSINCOS, VT, Expand);
538 }
539
540 // Lower this to MOVMSK plus an AND.
541 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
542 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
543
544 // Expand FP immediates into loads from the stack, except for the special
545 // cases we handle.
546 addLegalFPImmediate(APFloat(+0.0)); // xorpd
547 addLegalFPImmediate(APFloat(+0.0f)); // xorps
548 } else if (UseX87 && X86ScalarSSEf32) {
549 // Use SSE for f32, x87 for f64.
550 // Set up the FP register classes.
551 addRegisterClass(MVT::f32, &X86::FR32RegClass);
552 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
553
554 // Use ANDPS to simulate FABS.
555 setOperationAction(ISD::FABS , MVT::f32, Custom);
556
557 // Use XORP to simulate FNEG.
558 setOperationAction(ISD::FNEG , MVT::f32, Custom);
559
560 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
561
562 // Use ANDPS and ORPS to simulate FCOPYSIGN.
563 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
564 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
565
566 // We don't support sin/cos/fmod
567 setOperationAction(ISD::FSIN , MVT::f32, Expand);
568 setOperationAction(ISD::FCOS , MVT::f32, Expand);
569 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
570
571 // Special cases we handle for FP constants.
572 addLegalFPImmediate(APFloat(+0.0f)); // xorps
573 addLegalFPImmediate(APFloat(+0.0)); // FLD0
574 addLegalFPImmediate(APFloat(+1.0)); // FLD1
575 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
576 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
577
578 // Always expand sin/cos functions even though x87 has an instruction.
579 setOperationAction(ISD::FSIN , MVT::f64, Expand);
580 setOperationAction(ISD::FCOS , MVT::f64, Expand);
581 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
582 } else if (UseX87) {
583 // f32 and f64 in x87.
584 // Set up the FP register classes.
585 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
586 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
587
588 for (auto VT : { MVT::f32, MVT::f64 }) {
589 setOperationAction(ISD::UNDEF, VT, Expand);
590 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
591
592 // Always expand sin/cos functions even though x87 has an instruction.
593 setOperationAction(ISD::FSIN , VT, Expand);
594 setOperationAction(ISD::FCOS , VT, Expand);
595 setOperationAction(ISD::FSINCOS, VT, Expand);
596 }
597 addLegalFPImmediate(APFloat(+0.0)); // FLD0
598 addLegalFPImmediate(APFloat(+1.0)); // FLD1
599 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
600 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
601 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
602 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
603 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
604 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
605 }
606
607 // We don't support FMA.
608 setOperationAction(ISD::FMA, MVT::f64, Expand);
609 setOperationAction(ISD::FMA, MVT::f32, Expand);
610
611 // Long double always uses X87, except f128 in MMX.
612 if (UseX87) {
613 if (Subtarget.is64Bit() && Subtarget.hasMMX()) {
614 addRegisterClass(MVT::f128, &X86::FR128RegClass);
615 ValueTypeActions.setTypeAction(MVT::f128, TypeSoftenFloat);
616 setOperationAction(ISD::FABS , MVT::f128, Custom);
617 setOperationAction(ISD::FNEG , MVT::f128, Custom);
618 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Custom);
619 }
620
621 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
622 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
623 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
624 {
625 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended());
626 addLegalFPImmediate(TmpFlt); // FLD0
627 TmpFlt.changeSign();
628 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
629
630 bool ignored;
631 APFloat TmpFlt2(+1.0);
632 TmpFlt2.convert(APFloat::x87DoubleExtended(), APFloat::rmNearestTiesToEven,
633 &ignored);
634 addLegalFPImmediate(TmpFlt2); // FLD1
635 TmpFlt2.changeSign();
636 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
637 }
638
639 // Always expand sin/cos functions even though x87 has an instruction.
640 setOperationAction(ISD::FSIN , MVT::f80, Expand);
641 setOperationAction(ISD::FCOS , MVT::f80, Expand);
642 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
643
644 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
645 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
646 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
647 setOperationAction(ISD::FRINT, MVT::f80, Expand);
648 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
649 setOperationAction(ISD::FMA, MVT::f80, Expand);
650 }
651
652 // Always use a library call for pow.
653 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
654 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
655 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
656
657 setOperationAction(ISD::FLOG, MVT::f80, Expand);
658 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
659 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
660 setOperationAction(ISD::FEXP, MVT::f80, Expand);
661 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
662 setOperationAction(ISD::FMINNUM, MVT::f80, Expand);
663 setOperationAction(ISD::FMAXNUM, MVT::f80, Expand);
664
665 // Some FP actions are always expanded for vector types.
666 for (auto VT : { MVT::v4f32, MVT::v8f32, MVT::v16f32,
667 MVT::v2f64, MVT::v4f64, MVT::v8f64 }) {
668 setOperationAction(ISD::FSIN, VT, Expand);
669 setOperationAction(ISD::FSINCOS, VT, Expand);
670 setOperationAction(ISD::FCOS, VT, Expand);
671 setOperationAction(ISD::FREM, VT, Expand);
672 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
673 setOperationAction(ISD::FPOW, VT, Expand);
674 setOperationAction(ISD::FLOG, VT, Expand);
675 setOperationAction(ISD::FLOG2, VT, Expand);
676 setOperationAction(ISD::FLOG10, VT, Expand);
677 setOperationAction(ISD::FEXP, VT, Expand);
678 setOperationAction(ISD::FEXP2, VT, Expand);
679 }
680
681 // First set operation action for all vector types to either promote
682 // (for widening) or expand (for scalarization). Then we will selectively
683 // turn on ones that can be effectively codegen'd.
684 for (MVT VT : MVT::vector_valuetypes()) {
685 setOperationAction(ISD::SDIV, VT, Expand);
686 setOperationAction(ISD::UDIV, VT, Expand);
687 setOperationAction(ISD::SREM, VT, Expand);
688 setOperationAction(ISD::UREM, VT, Expand);
689 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
690 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
691 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
692 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
693 setOperationAction(ISD::FMA, VT, Expand);
694 setOperationAction(ISD::FFLOOR, VT, Expand);
695 setOperationAction(ISD::FCEIL, VT, Expand);
696 setOperationAction(ISD::FTRUNC, VT, Expand);
697 setOperationAction(ISD::FRINT, VT, Expand);
698 setOperationAction(ISD::FNEARBYINT, VT, Expand);
699 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
700 setOperationAction(ISD::MULHS, VT, Expand);
701 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
702 setOperationAction(ISD::MULHU, VT, Expand);
703 setOperationAction(ISD::SDIVREM, VT, Expand);
704 setOperationAction(ISD::UDIVREM, VT, Expand);
705 setOperationAction(ISD::CTPOP, VT, Expand);
706 setOperationAction(ISD::CTTZ, VT, Expand);
707 setOperationAction(ISD::CTLZ, VT, Expand);
708 setOperationAction(ISD::ROTL, VT, Expand);
709 setOperationAction(ISD::ROTR, VT, Expand);
710 setOperationAction(ISD::BSWAP, VT, Expand);
711 setOperationAction(ISD::SETCC, VT, Expand);
712 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
713 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
714 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
715 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
716 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
717 setOperationAction(ISD::TRUNCATE, VT, Expand);
718 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
719 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
720 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
721 setOperationAction(ISD::SELECT_CC, VT, Expand);
722 for (MVT InnerVT : MVT::vector_valuetypes()) {
723 setTruncStoreAction(InnerVT, VT, Expand);
724
725 setLoadExtAction(ISD::SEXTLOAD, InnerVT, VT, Expand);
726 setLoadExtAction(ISD::ZEXTLOAD, InnerVT, VT, Expand);
727
728 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like
729 // types, we have to deal with them whether we ask for Expansion or not.
730 // Setting Expand causes its own optimisation problems though, so leave
731 // them legal.
732 if (VT.getVectorElementType() == MVT::i1)
733 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
734
735 // EXTLOAD for MVT::f16 vectors is not legal because f16 vectors are
736 // split/scalarized right now.
737 if (VT.getVectorElementType() == MVT::f16)
738 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
739 }
740 }
741
742 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
743 // with -msoft-float, disable use of MMX as well.
744 if (!Subtarget.useSoftFloat() && Subtarget.hasMMX()) {
745 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
746 // No operations on x86mmx supported, everything uses intrinsics.
747 }
748
749 if (!Subtarget.useSoftFloat() && Subtarget.hasSSE1()) {
750 addRegisterClass(MVT::v4f32, Subtarget.hasVLX() ? &X86::VR128XRegClass
751 : &X86::VR128RegClass);
752
753 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
754 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
755 setOperationAction(ISD::FCOPYSIGN, MVT::v4f32, Custom);
756 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
757 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
758 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
759 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
760 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
761 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
762 }
763
764 if (!Subtarget.useSoftFloat() && Subtarget.hasSSE2()) {
765 addRegisterClass(MVT::v2f64, Subtarget.hasVLX() ? &X86::VR128XRegClass
766 : &X86::VR128RegClass);
767
768 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
769 // registers cannot be used even for integer operations.
770 addRegisterClass(MVT::v16i8, Subtarget.hasVLX() ? &X86::VR128XRegClass
771 : &X86::VR128RegClass);
772 addRegisterClass(MVT::v8i16, Subtarget.hasVLX() ? &X86::VR128XRegClass
773 : &X86::VR128RegClass);
774 addRegisterClass(MVT::v4i32, Subtarget.hasVLX() ? &X86::VR128XRegClass
775 : &X86::VR128RegClass);
776 addRegisterClass(MVT::v2i64, Subtarget.hasVLX() ? &X86::VR128XRegClass
777 : &X86::VR128RegClass);
778
779 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
780 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
781 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
782 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
783 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
784 setOperationAction(ISD::MULHU, MVT::v16i8, Custom);
785 setOperationAction(ISD::MULHS, MVT::v16i8, Custom);
786 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
787 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
788 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
789 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
790 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
791 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Custom);
792
793 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
794 setOperationAction(ISD::SMAX, VT, VT == MVT::v8i16 ? Legal : Custom);
795 setOperationAction(ISD::SMIN, VT, VT == MVT::v8i16 ? Legal : Custom);
796 setOperationAction(ISD::UMAX, VT, VT == MVT::v16i8 ? Legal : Custom);
797 setOperationAction(ISD::UMIN, VT, VT == MVT::v16i8 ? Legal : Custom);
798 }
799
800 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
801 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
802 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
803
804 // Provide custom widening for v2f32 setcc. This is really for VLX when
805 // setcc result type returns v2i1/v4i1 vector for v2f32/v4f32 leading to
806 // type legalization changing the result type to v4i1 during widening.
807 // It works fine for SSE2 and is probably faster so no need to qualify with
808 // VLX support.
809 setOperationAction(ISD::SETCC, MVT::v2i32, Custom);
810
811 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
812 setOperationAction(ISD::SETCC, VT, Custom);
813 setOperationAction(ISD::CTPOP, VT, Custom);
814 setOperationAction(ISD::CTTZ, VT, Custom);
815 }
816
817 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32 }) {
818 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
819 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
820 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
821 setOperationAction(ISD::VSELECT, VT, Custom);
822 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
823 }
824
825 // We support custom legalizing of sext and anyext loads for specific
826 // memory vector types which we can load as a scalar (or sequence of
827 // scalars) and extend in-register to a legal 128-bit vector type. For sext
828 // loads these must work with a single scalar load.
829 for (MVT VT : MVT::integer_vector_valuetypes()) {
830 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i8, Custom);
831 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i16, Custom);
832 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v8i8, Custom);
833 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Custom);
834 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Custom);
835 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i32, Custom);
836 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i8, Custom);
837 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Custom);
838 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8i8, Custom);
839 }
840
841 for (auto VT : { MVT::v2f64, MVT::v2i64 }) {
842 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
843 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
844 setOperationAction(ISD::VSELECT, VT, Custom);
845
846 if (VT == MVT::v2i64 && !Subtarget.is64Bit())
847 continue;
848
849 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
850 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
851 }
852
853 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
854 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32 }) {
855 setOperationPromotedToType(ISD::AND, VT, MVT::v2i64);
856 setOperationPromotedToType(ISD::OR, VT, MVT::v2i64);
857 setOperationPromotedToType(ISD::XOR, VT, MVT::v2i64);
858 setOperationPromotedToType(ISD::LOAD, VT, MVT::v2i64);
859 setOperationPromotedToType(ISD::SELECT, VT, MVT::v2i64);
860 }
861
862 // Custom lower v2i64 and v2f64 selects.
863 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
864 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
865
866 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
867 setOperationAction(ISD::FP_TO_SINT, MVT::v2i32, Custom);
868
869 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
870 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
871
872 setOperationAction(ISD::UINT_TO_FP, MVT::v2i32, Custom);
873
874 // Fast v2f32 UINT_TO_FP( v2i32 ) custom conversion.
875 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
876
877 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
878 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
879
880 for (MVT VT : MVT::fp_vector_valuetypes())
881 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2f32, Legal);
882
883 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
884 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
885 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
886 if (!Subtarget.hasAVX512())
887 setOperationAction(ISD::BITCAST, MVT::v16i1, Custom);
888
889 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v2i64, Custom);
890 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v4i32, Custom);
891 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v8i16, Custom);
892
893 // In the customized shift lowering, the legal v4i32/v2i64 cases
894 // in AVX2 will be recognized.
895 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
896 setOperationAction(ISD::SRL, VT, Custom);
897 setOperationAction(ISD::SHL, VT, Custom);
898 setOperationAction(ISD::SRA, VT, Custom);
899 }
900 }
901
902 if (!Subtarget.useSoftFloat() && Subtarget.hasSSSE3()) {
903 setOperationAction(ISD::ABS, MVT::v16i8, Legal);
904 setOperationAction(ISD::ABS, MVT::v8i16, Legal);
905 setOperationAction(ISD::ABS, MVT::v4i32, Legal);
906 setOperationAction(ISD::BITREVERSE, MVT::v16i8, Custom);
907 setOperationAction(ISD::CTLZ, MVT::v16i8, Custom);
908 setOperationAction(ISD::CTLZ, MVT::v8i16, Custom);
909 setOperationAction(ISD::CTLZ, MVT::v4i32, Custom);
910 setOperationAction(ISD::CTLZ, MVT::v2i64, Custom);
911 }
912
913 if (!Subtarget.useSoftFloat() && Subtarget.hasSSE41()) {
914 for (MVT RoundedTy : {MVT::f32, MVT::f64, MVT::v4f32, MVT::v2f64}) {
915 setOperationAction(ISD::FFLOOR, RoundedTy, Legal);
916 setOperationAction(ISD::FCEIL, RoundedTy, Legal);
917 setOperationAction(ISD::FTRUNC, RoundedTy, Legal);
918 setOperationAction(ISD::FRINT, RoundedTy, Legal);
919 setOperationAction(ISD::FNEARBYINT, RoundedTy, Legal);
920 }
921
922 setOperationAction(ISD::SMAX, MVT::v16i8, Legal);
923 setOperationAction(ISD::SMAX, MVT::v4i32, Legal);
924 setOperationAction(ISD::UMAX, MVT::v8i16, Legal);
925 setOperationAction(ISD::UMAX, MVT::v4i32, Legal);
926 setOperationAction(ISD::SMIN, MVT::v16i8, Legal);
927 setOperationAction(ISD::SMIN, MVT::v4i32, Legal);
928 setOperationAction(ISD::UMIN, MVT::v8i16, Legal);
929 setOperationAction(ISD::UMIN, MVT::v4i32, Legal);
930
931 // FIXME: Do we need to handle scalar-to-vector here?
932 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
933
934 // We directly match byte blends in the backend as they match the VSELECT
935 // condition form.
936 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
937
938 // SSE41 brings specific instructions for doing vector sign extend even in
939 // cases where we don't have SRA.
940 for (auto VT : { MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
941 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Legal);
942 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, VT, Legal);
943 }
944
945 for (MVT VT : MVT::integer_vector_valuetypes()) {
946 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i8, Custom);
947 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i16, Custom);
948 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i32, Custom);
949 }
950
951 // SSE41 also has vector sign/zero extending loads, PMOV[SZ]X
952 for (auto LoadExtOp : { ISD::SEXTLOAD, ISD::ZEXTLOAD }) {
953 setLoadExtAction(LoadExtOp, MVT::v8i16, MVT::v8i8, Legal);
954 setLoadExtAction(LoadExtOp, MVT::v4i32, MVT::v4i8, Legal);
955 setLoadExtAction(LoadExtOp, MVT::v2i32, MVT::v2i8, Legal);
956 setLoadExtAction(LoadExtOp, MVT::v2i64, MVT::v2i8, Legal);
957 setLoadExtAction(LoadExtOp, MVT::v4i32, MVT::v4i16, Legal);
958 setLoadExtAction(LoadExtOp, MVT::v2i64, MVT::v2i16, Legal);
959 setLoadExtAction(LoadExtOp, MVT::v2i64, MVT::v2i32, Legal);
960 }
961
962 // i8 vectors are custom because the source register and source
963 // source memory operand types are not the same width.
964 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
965 }
966
967 if (!Subtarget.useSoftFloat() && Subtarget.hasXOP()) {
968 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64,
969 MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 })
970 setOperationAction(ISD::ROTL, VT, Custom);
971
972 // XOP can efficiently perform BITREVERSE with VPPERM.
973 for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 })
974 setOperationAction(ISD::BITREVERSE, VT, Custom);
975
976 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64,
977 MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 })
978 setOperationAction(ISD::BITREVERSE, VT, Custom);
979 }
980
981 if (!Subtarget.useSoftFloat() && Subtarget.hasAVX()) {
982 bool HasInt256 = Subtarget.hasInt256();
983
984 addRegisterClass(MVT::v32i8, Subtarget.hasVLX() ? &X86::VR256XRegClass
985 : &X86::VR256RegClass);
986 addRegisterClass(MVT::v16i16, Subtarget.hasVLX() ? &X86::VR256XRegClass
987 : &X86::VR256RegClass);
988 addRegisterClass(MVT::v8i32, Subtarget.hasVLX() ? &X86::VR256XRegClass
989 : &X86::VR256RegClass);
990 addRegisterClass(MVT::v8f32, Subtarget.hasVLX() ? &X86::VR256XRegClass
991 : &X86::VR256RegClass);
992 addRegisterClass(MVT::v4i64, Subtarget.hasVLX() ? &X86::VR256XRegClass
993 : &X86::VR256RegClass);
994 addRegisterClass(MVT::v4f64, Subtarget.hasVLX() ? &X86::VR256XRegClass
995 : &X86::VR256RegClass);
996
997 for (auto VT : { MVT::v8f32, MVT::v4f64 }) {
998 setOperationAction(ISD::FFLOOR, VT, Legal);
999 setOperationAction(ISD::FCEIL, VT, Legal);
1000 setOperationAction(ISD::FTRUNC, VT, Legal);
1001 setOperationAction(ISD::FRINT, VT, Legal);
1002 setOperationAction(ISD::FNEARBYINT, VT, Legal);
1003 setOperationAction(ISD::FNEG, VT, Custom);
1004 setOperationAction(ISD::FABS, VT, Custom);
1005 setOperationAction(ISD::FCOPYSIGN, VT, Custom);
1006 }
1007
1008 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1009 // even though v8i16 is a legal type.
1010 setOperationPromotedToType(ISD::FP_TO_SINT, MVT::v8i16, MVT::v8i32);
1011 setOperationPromotedToType(ISD::FP_TO_UINT, MVT::v8i16, MVT::v8i32);
1012 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1013
1014 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1015 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1016
1017 if (!Subtarget.hasAVX512())
1018 setOperationAction(ISD::BITCAST, MVT::v32i1, Custom);
1019
1020 for (MVT VT : MVT::fp_vector_valuetypes())
1021 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4f32, Legal);
1022
1023 // In the customized shift lowering, the legal v8i32/v4i64 cases
1024 // in AVX2 will be recognized.
1025 for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 }) {
1026 setOperationAction(ISD::SRL, VT, Custom);
1027 setOperationAction(ISD::SHL, VT, Custom);
1028 setOperationAction(ISD::SRA, VT, Custom);
1029 }
1030
1031 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1032 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1033 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1034
1035 for (auto VT : { MVT::v16i16, MVT::v8i32, MVT::v4i64 }) {
1036 setOperationAction(ISD::SIGN_EXTEND, VT, Custom);
1037 setOperationAction(ISD::ZERO_EXTEND, VT, Custom);
1038 setOperationAction(ISD::ANY_EXTEND, VT, Custom);
1039 }
1040
1041 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1042 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1043 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1044 setOperationAction(ISD::BITREVERSE, MVT::v32i8, Custom);
1045
1046 for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 }) {
1047 setOperationAction(ISD::SETCC, VT, Custom);
1048 setOperationAction(ISD::CTPOP, VT, Custom);
1049 setOperationAction(ISD::CTTZ, VT, Custom);
1050 setOperationAction(ISD::CTLZ, VT, Custom);
1051 }
1052
1053 if (Subtarget.hasAnyFMA()) {
1054 for (auto VT : { MVT::f32, MVT::f64, MVT::v4f32, MVT::v8f32,
1055 MVT::v2f64, MVT::v4f64 })
1056 setOperationAction(ISD::FMA, VT, Legal);
1057 }
1058
1059 for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 }) {
1060 setOperationAction(ISD::ADD, VT, HasInt256 ? Legal : Custom);
1061 setOperationAction(ISD::SUB, VT, HasInt256 ? Legal : Custom);
1062 }
1063
1064 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1065 setOperationAction(ISD::MUL, MVT::v8i32, HasInt256 ? Legal : Custom);
1066 setOperationAction(ISD::MUL, MVT::v16i16, HasInt256 ? Legal : Custom);
1067 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1068
1069 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1070 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1071
1072 setOperationAction(ISD::MULHU, MVT::v16i16, HasInt256 ? Legal : Custom);
1073 setOperationAction(ISD::MULHS, MVT::v16i16, HasInt256 ? Legal : Custom);
1074 setOperationAction(ISD::MULHU, MVT::v32i8, Custom);
1075 setOperationAction(ISD::MULHS, MVT::v32i8, Custom);
1076
1077 setOperationAction(ISD::SMAX, MVT::v4i64, Custom);
1078 setOperationAction(ISD::UMAX, MVT::v4i64, Custom);
1079 setOperationAction(ISD::SMIN, MVT::v4i64, Custom);
1080 setOperationAction(ISD::UMIN, MVT::v4i64, Custom);
1081
1082 for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32 }) {
1083 setOperationAction(ISD::ABS, VT, HasInt256 ? Legal : Custom);
1084 setOperationAction(ISD::SMAX, VT, HasInt256 ? Legal : Custom);
1085 setOperationAction(ISD::UMAX, VT, HasInt256 ? Legal : Custom);
1086 setOperationAction(ISD::SMIN, VT, HasInt256 ? Legal : Custom);
1087 setOperationAction(ISD::UMIN, VT, HasInt256 ? Legal : Custom);
1088 }
1089
1090 if (HasInt256) {
1091 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v4i64, Custom);
1092 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v8i32, Custom);
1093 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v16i16, Custom);
1094
1095 // The custom lowering for UINT_TO_FP for v8i32 becomes interesting
1096 // when we have a 256bit-wide blend with immediate.
1097 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Custom);
1098
1099 // AVX2 also has wider vector sign/zero extending loads, VPMOV[SZ]X
1100 for (auto LoadExtOp : { ISD::SEXTLOAD, ISD::ZEXTLOAD }) {
1101 setLoadExtAction(LoadExtOp, MVT::v16i16, MVT::v16i8, Legal);
1102 setLoadExtAction(LoadExtOp, MVT::v8i32, MVT::v8i8, Legal);
1103 setLoadExtAction(LoadExtOp, MVT::v4i64, MVT::v4i8, Legal);
1104 setLoadExtAction(LoadExtOp, MVT::v8i32, MVT::v8i16, Legal);
1105 setLoadExtAction(LoadExtOp, MVT::v4i64, MVT::v4i16, Legal);
1106 setLoadExtAction(LoadExtOp, MVT::v4i64, MVT::v4i32, Legal);
1107 }
1108 }
1109
1110 for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64,
1111 MVT::v4f32, MVT::v8f32, MVT::v2f64, MVT::v4f64 }) {
1112 setOperationAction(ISD::MLOAD, VT, Legal);
1113 setOperationAction(ISD::MSTORE, VT, Legal);
1114 }
1115
1116 // Extract subvector is special because the value type
1117 // (result) is 128-bit but the source is 256-bit wide.
1118 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64,
1119 MVT::v4f32, MVT::v2f64 }) {
1120 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1121 }
1122
1123 // Custom lower several nodes for 256-bit types.
1124 for (MVT VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64,
1125 MVT::v8f32, MVT::v4f64 }) {
1126 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1127 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1128 setOperationAction(ISD::VSELECT, VT, Custom);
1129 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1130 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1131 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1132 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Legal);
1133 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1134 }
1135
1136 if (HasInt256)
1137 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1138
1139 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1140 for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32 }) {
1141 setOperationPromotedToType(ISD::AND, VT, MVT::v4i64);
1142 setOperationPromotedToType(ISD::OR, VT, MVT::v4i64);
1143 setOperationPromotedToType(ISD::XOR, VT, MVT::v4i64);
1144 setOperationPromotedToType(ISD::LOAD, VT, MVT::v4i64);
1145 setOperationPromotedToType(ISD::SELECT, VT, MVT::v4i64);
1146 }
1147
1148 if (HasInt256) {
1149 // Custom legalize 2x32 to get a little better code.
1150 setOperationAction(ISD::MGATHER, MVT::v2f32, Custom);
1151 setOperationAction(ISD::MGATHER, MVT::v2i32, Custom);
1152
1153 for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64,
1154 MVT::v4f32, MVT::v8f32, MVT::v2f64, MVT::v4f64 })
1155 setOperationAction(ISD::MGATHER, VT, Custom);
1156 }
1157 }
1158
1159 // This block controls legalization of the mask vector sizes that are
1160 // available with AVX512. 512-bit vectors are in a separate block controlled
1161 // by useAVX512Regs.
1162 if (!Subtarget.useSoftFloat() && Subtarget.hasAVX512()) {
1163 addRegisterClass(MVT::v1i1, &X86::VK1RegClass);
1164 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1165 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1166 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1167 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1168
1169 setOperationAction(ISD::SELECT, MVT::v1i1, Custom);
1170 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v1i1, Custom);
1171 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i1, Custom);
1172
1173 setOperationPromotedToType(ISD::FP_TO_SINT, MVT::v8i1, MVT::v8i32);
1174 setOperationPromotedToType(ISD::FP_TO_UINT, MVT::v8i1, MVT::v8i32);
1175 setOperationPromotedToType(ISD::FP_TO_SINT, MVT::v4i1, MVT::v4i32);
1176 setOperationPromotedToType(ISD::FP_TO_UINT, MVT::v4i1, MVT::v4i32);
1177 setOperationAction(ISD::FP_TO_SINT, MVT::v2i1, Custom);
1178 setOperationAction(ISD::FP_TO_UINT, MVT::v2i1, Custom);
1179
1180 // There is no byte sized k-register load or store without AVX512DQ.
1181 if (!Subtarget.hasDQI()) {
1182 setOperationAction(ISD::LOAD, MVT::v1i1, Custom);
1183 setOperationAction(ISD::LOAD, MVT::v2i1, Custom);
1184 setOperationAction(ISD::LOAD, MVT::v4i1, Custom);
1185 setOperationAction(ISD::LOAD, MVT::v8i1, Custom);
1186
1187 setOperationAction(ISD::STORE, MVT::v1i1, Custom);
1188 setOperationAction(ISD::STORE, MVT::v2i1, Custom);
1189 setOperationAction(ISD::STORE, MVT::v4i1, Custom);
1190 setOperationAction(ISD::STORE, MVT::v8i1, Custom);
1191 }
1192
1193 // Extends of v16i1/v8i1/v4i1/v2i1 to 128-bit vectors.
1194 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
1195 setOperationAction(ISD::SIGN_EXTEND, VT, Custom);
1196 setOperationAction(ISD::ZERO_EXTEND, VT, Custom);
1197 setOperationAction(ISD::ANY_EXTEND, VT, Custom);
1198 }
1199
1200 for (auto VT : { MVT::v2i1, MVT::v4i1, MVT::v8i1, MVT::v16i1 }) {
1201 setOperationAction(ISD::ADD, VT, Custom);
1202 setOperationAction(ISD::SUB, VT, Custom);
1203 setOperationAction(ISD::MUL, VT, Custom);
1204 setOperationAction(ISD::SETCC, VT, Custom);
1205 setOperationAction(ISD::SELECT, VT, Custom);
1206 setOperationAction(ISD::TRUNCATE, VT, Custom);
1207
1208 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1209 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1210 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1211 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1212 setOperationAction(ISD::VSELECT, VT, Expand);
1213 }
1214
1215 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Custom);
1216 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1217 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i1, Custom);
1218 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v2i1, Custom);
1219 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v4i1, Custom);
1220 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Custom);
1221 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v16i1, Custom);
1222 for (auto VT : { MVT::v1i1, MVT::v2i1, MVT::v4i1, MVT::v8i1 })
1223 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1224 }
1225
1226 // This block controls legalization for 512-bit operations with 32/64 bit
1227 // elements. 512-bits can be disabled based on prefer-vector-width and
1228 // required-vector-width function attributes.
1229 if (!Subtarget.useSoftFloat() && Subtarget.useAVX512Regs()) {
1230 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1231 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1232 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1233 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1234
1235 for (MVT VT : MVT::fp_vector_valuetypes())
1236 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8f32, Legal);
1237
1238 for (auto ExtType : {ISD::ZEXTLOAD, ISD::SEXTLOAD}) {
1239 setLoadExtAction(ExtType, MVT::v16i32, MVT::v16i8, Legal);
1240 setLoadExtAction(ExtType, MVT::v16i32, MVT::v16i16, Legal);
1241 setLoadExtAction(ExtType, MVT::v8i64, MVT::v8i8, Legal);
1242 setLoadExtAction(ExtType, MVT::v8i64, MVT::v8i16, Legal);
1243 setLoadExtAction(ExtType, MVT::v8i64, MVT::v8i32, Legal);
1244 }
1245
1246 for (MVT VT : { MVT::v16f32, MVT::v8f64 }) {
1247 setOperationAction(ISD::FNEG, VT, Custom);
1248 setOperationAction(ISD::FABS, VT, Custom);
1249 setOperationAction(ISD::FMA, VT, Legal);
1250 setOperationAction(ISD::FCOPYSIGN, VT, Custom);
1251 }
1252
1253 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1254 setOperationPromotedToType(ISD::FP_TO_SINT, MVT::v16i16, MVT::v16i32);
1255 setOperationPromotedToType(ISD::FP_TO_SINT, MVT::v16i8, MVT::v16i32);
1256 setOperationPromotedToType(ISD::FP_TO_SINT, MVT::v16i1, MVT::v16i32);
1257 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1258 setOperationPromotedToType(ISD::FP_TO_UINT, MVT::v16i1, MVT::v16i32);
1259 setOperationPromotedToType(ISD::FP_TO_UINT, MVT::v16i8, MVT::v16i32);
1260 setOperationPromotedToType(ISD::FP_TO_UINT, MVT::v16i16, MVT::v16i32);
1261 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1262 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1263
1264 setTruncStoreAction(MVT::v8i64, MVT::v8i8, Legal);
1265 setTruncStoreAction(MVT::v8i64, MVT::v8i16, Legal);
1266 setTruncStoreAction(MVT::v8i64, MVT::v8i32, Legal);
1267 setTruncStoreAction(MVT::v16i32, MVT::v16i8, Legal);
1268 setTruncStoreAction(MVT::v16i32, MVT::v16i16, Legal);
1269
1270 if (!Subtarget.hasVLX()) {
1271 // With 512-bit vectors and no VLX, we prefer to widen MLOAD/MSTORE
1272 // to 512-bit rather than use the AVX2 instructions so that we can use
1273 // k-masks.
1274 for (auto VT : {MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64,
1275 MVT::v4f32, MVT::v8f32, MVT::v2f64, MVT::v4f64}) {
1276 setOperationAction(ISD::MLOAD, VT, Custom);
1277 setOperationAction(ISD::MSTORE, VT, Custom);
1278 }
1279 }
1280
1281 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1282 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1283 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1284 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1285 setOperationAction(ISD::ANY_EXTEND, MVT::v16i32, Custom);
1286 setOperationAction(ISD::ANY_EXTEND, MVT::v8i64, Custom);
1287 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1288 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1289
1290 for (auto VT : { MVT::v16f32, MVT::v8f64 }) {
1291 setOperationAction(ISD::FFLOOR, VT, Legal);
1292 setOperationAction(ISD::FCEIL, VT, Legal);
1293 setOperationAction(ISD::FTRUNC, VT, Legal);
1294 setOperationAction(ISD::FRINT, VT, Legal);
1295 setOperationAction(ISD::FNEARBYINT, VT, Legal);
1296 }
1297
1298 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v8i64, Custom);
1299 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v16i32, Custom);
1300
1301 // Without BWI we need to use custom lowering to handle MVT::v64i8 input.
1302 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v64i8, Custom);
1303 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, MVT::v64i8, Custom);
1304
1305 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1306 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1307 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1308 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1309
1310 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1311 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1312
1313 setOperationAction(ISD::UMUL_LOHI, MVT::v16i32, Custom);
1314 setOperationAction(ISD::SMUL_LOHI, MVT::v16i32, Custom);
1315
1316 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1317 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1318 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1319
1320 for (auto VT : { MVT::v16i32, MVT::v8i64 }) {
1321 setOperationAction(ISD::SMAX, VT, Legal);
1322 setOperationAction(ISD::UMAX, VT, Legal);
1323 setOperationAction(ISD::SMIN, VT, Legal);
1324 setOperationAction(ISD::UMIN, VT, Legal);
1325 setOperationAction(ISD::ABS, VT, Legal);
1326 setOperationAction(ISD::SRL, VT, Custom);
1327 setOperationAction(ISD::SHL, VT, Custom);
1328 setOperationAction(ISD::SRA, VT, Custom);
1329 setOperationAction(ISD::CTPOP, VT, Custom);
1330 setOperationAction(ISD::CTTZ, VT, Custom);
1331 setOperationAction(ISD::ROTL, VT, Custom);
1332 setOperationAction(ISD::ROTR, VT, Custom);
1333 }
1334
1335 // Need to promote to 64-bit even though we have 32-bit masked instructions
1336 // because the IR optimizers rearrange bitcasts around logic ops leaving
1337 // too many variations to handle if we don't promote them.
1338 setOperationPromotedToType(ISD::AND, MVT::v16i32, MVT::v8i64);
1339 setOperationPromotedToType(ISD::OR, MVT::v16i32, MVT::v8i64);
1340 setOperationPromotedToType(ISD::XOR, MVT::v16i32, MVT::v8i64);
1341
1342 if (Subtarget.hasDQI()) {
1343 setOperationAction(ISD::SINT_TO_FP, MVT::v8i64, Legal);
1344 setOperationAction(ISD::UINT_TO_FP, MVT::v8i64, Legal);
1345 setOperationAction(ISD::FP_TO_SINT, MVT::v8i64, Legal);
1346 setOperationAction(ISD::FP_TO_UINT, MVT::v8i64, Legal);
1347
1348 setOperationAction(ISD::MUL, MVT::v8i64, Legal);
1349 }
1350
1351 if (Subtarget.hasCDI()) {
1352 // NonVLX sub-targets extend 128/256 vectors to use the 512 version.
1353 for (auto VT : { MVT::v16i32, MVT::v8i64} ) {
1354 setOperationAction(ISD::CTLZ, VT, Legal);
1355 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Custom);
1356 }
1357 } // Subtarget.hasCDI()
1358
1359 if (Subtarget.hasVPOPCNTDQ()) {
1360 for (auto VT : { MVT::v16i32, MVT::v8i64 })
1361 setOperationAction(ISD::CTPOP, VT, Legal);
1362 }
1363
1364 // Extract subvector is special because the value type
1365 // (result) is 256-bit but the source is 512-bit wide.
1366 // 128-bit was made Legal under AVX1.
1367 for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64,
1368 MVT::v8f32, MVT::v4f64 })
1369 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1370
1371 for (auto VT : { MVT::v16i32, MVT::v8i64, MVT::v16f32, MVT::v8f64 }) {
1372 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1373 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1374 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1375 setOperationAction(ISD::VSELECT, VT, Custom);
1376 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1377 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1378 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Legal);
1379 setOperationAction(ISD::MLOAD, VT, Legal);
1380 setOperationAction(ISD::MSTORE, VT, Legal);
1381 setOperationAction(ISD::MGATHER, VT, Custom);
1382 setOperationAction(ISD::MSCATTER, VT, Custom);
1383 }
1384 for (auto VT : { MVT::v64i8, MVT::v32i16, MVT::v16i32 }) {
1385 setOperationPromotedToType(ISD::LOAD, VT, MVT::v8i64);
1386 setOperationPromotedToType(ISD::SELECT, VT, MVT::v8i64);
1387 }
1388
1389 // Need to custom split v32i16/v64i8 bitcasts.
1390 if (!Subtarget.hasBWI()) {
1391 setOperationAction(ISD::BITCAST, MVT::v32i16, Custom);
1392 setOperationAction(ISD::BITCAST, MVT::v64i8, Custom);
1393 }
1394 }// has AVX-512
1395
1396 // This block controls legalization for operations that don't have
1397 // pre-AVX512 equivalents. Without VLX we use 512-bit operations for
1398 // narrower widths.
1399 if (!Subtarget.useSoftFloat() && Subtarget.hasAVX512()) {
1400 // These operations are handled on non-VLX by artificially widening in
1401 // isel patterns.
1402 // TODO: Custom widen in lowering on non-VLX and drop the isel patterns?
1403
1404 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1405 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1406 setOperationAction(ISD::FP_TO_UINT, MVT::v2i32, Custom);
1407 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1408 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1409
1410 for (auto VT : { MVT::v2i64, MVT::v4i64 }) {
1411 setOperationAction(ISD::SMAX, VT, Legal);
1412 setOperationAction(ISD::UMAX, VT, Legal);
1413 setOperationAction(ISD::SMIN, VT, Legal);
1414 setOperationAction(ISD::UMIN, VT, Legal);
1415 setOperationAction(ISD::ABS, VT, Legal);
1416 }
1417
1418 for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64 }) {
1419 setOperationAction(ISD::ROTL, VT, Custom);
1420 setOperationAction(ISD::ROTR, VT, Custom);
1421 }
1422
1423 // Custom legalize 2x32 to get a little better code.
1424 setOperationAction(ISD::MSCATTER, MVT::v2f32, Custom);
1425 setOperationAction(ISD::MSCATTER, MVT::v2i32, Custom);
1426
1427 for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64,
1428 MVT::v4f32, MVT::v8f32, MVT::v2f64, MVT::v4f64 })
1429 setOperationAction(ISD::MSCATTER, VT, Custom);
1430
1431 if (Subtarget.hasDQI()) {
1432 for (auto VT : { MVT::v2i64, MVT::v4i64 }) {
1433 setOperationAction(ISD::SINT_TO_FP, VT, Legal);
1434 setOperationAction(ISD::UINT_TO_FP, VT, Legal);
1435 setOperationAction(ISD::FP_TO_SINT, VT, Legal);
1436 setOperationAction(ISD::FP_TO_UINT, VT, Legal);
1437
1438 setOperationAction(ISD::MUL, VT, Legal);
1439 }
1440 }
1441
1442 if (Subtarget.hasCDI()) {
1443 for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64 }) {
1444 setOperationAction(ISD::CTLZ, VT, Legal);
1445 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Custom);
1446 }
1447 } // Subtarget.hasCDI()
1448
1449 if (Subtarget.hasVPOPCNTDQ()) {
1450 for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64 })
1451 setOperationAction(ISD::CTPOP, VT, Legal);
1452 }
1453 }
1454
1455 // This block control legalization of v32i1/v64i1 which are available with
1456 // AVX512BW. 512-bit v32i16 and v64i8 vector legalization is controlled with
1457 // useBWIRegs.
1458 if (!Subtarget.useSoftFloat() && Subtarget.hasBWI()) {
1459 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1460 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1461
1462 for (auto VT : { MVT::v32i1, MVT::v64i1 }) {
1463 setOperationAction(ISD::ADD, VT, Custom);
1464 setOperationAction(ISD::SUB, VT, Custom);
1465 setOperationAction(ISD::MUL, VT, Custom);
1466 setOperationAction(ISD::VSELECT, VT, Expand);
1467
1468 setOperationAction(ISD::TRUNCATE, VT, Custom);
1469 setOperationAction(ISD::SETCC, VT, Custom);
1470 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1471 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1472 setOperationAction(ISD::SELECT, VT, Custom);
1473 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1474 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1475 }
1476
1477 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i1, Custom);
1478 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i1, Custom);
1479 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i1, Custom);
1480 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i1, Custom);
1481 for (auto VT : { MVT::v16i1, MVT::v32i1 })
1482 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1483
1484 // Extends from v32i1 masks to 256-bit vectors.
1485 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i8, Custom);
1486 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i8, Custom);
1487 setOperationAction(ISD::ANY_EXTEND, MVT::v32i8, Custom);
1488 }
1489
1490 // This block controls legalization for v32i16 and v64i8. 512-bits can be
1491 // disabled based on prefer-vector-width and required-vector-width function
1492 // attributes.
1493 if (!Subtarget.useSoftFloat() && Subtarget.useBWIRegs()) {
1494 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1495 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1496
1497 // Extends from v64i1 masks to 512-bit vectors.
1498 setOperationAction(ISD::SIGN_EXTEND, MVT::v64i8, Custom);
1499 setOperationAction(ISD::ZERO_EXTEND, MVT::v64i8, Custom);
1500 setOperationAction(ISD::ANY_EXTEND, MVT::v64i8, Custom);
1501
1502 setOperationAction(ISD::MUL, MVT::v32i16, Legal);
1503 setOperationAction(ISD::MUL, MVT::v64i8, Custom);
1504 setOperationAction(ISD::MULHS, MVT::v32i16, Legal);
1505 setOperationAction(ISD::MULHU, MVT::v32i16, Legal);
1506 setOperationAction(ISD::MULHS, MVT::v64i8, Custom);
1507 setOperationAction(ISD::MULHU, MVT::v64i8, Custom);
1508 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i16, Custom);
1509 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i8, Custom);
1510 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i16, Legal);
1511 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i8, Legal);
1512 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v32i16, Custom);
1513 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v64i8, Custom);
1514 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v32i16, Custom);
1515 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v64i8, Custom);
1516 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i16, Custom);
1517 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i16, Custom);
1518 setOperationAction(ISD::ANY_EXTEND, MVT::v32i16, Custom);
1519 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v32i16, Custom);
1520 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v64i8, Custom);
1521 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v32i16, Custom);
1522 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v64i8, Custom);
1523 setOperationAction(ISD::TRUNCATE, MVT::v32i8, Custom);
1524 setOperationAction(ISD::BITREVERSE, MVT::v64i8, Custom);
1525
1526 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v32i16, Custom);
1527
1528 setTruncStoreAction(MVT::v32i16, MVT::v32i8, Legal);
1529
1530 for (auto VT : { MVT::v64i8, MVT::v32i16 }) {
1531 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1532 setOperationAction(ISD::VSELECT, VT, Custom);
1533 setOperationAction(ISD::ABS, VT, Legal);
1534 setOperationAction(ISD::SRL, VT, Custom);
1535 setOperationAction(ISD::SHL, VT, Custom);
1536 setOperationAction(ISD::SRA, VT, Custom);
1537 setOperationAction(ISD::MLOAD, VT, Legal);
1538 setOperationAction(ISD::MSTORE, VT, Legal);
1539 setOperationAction(ISD::CTPOP, VT, Custom);
1540 setOperationAction(ISD::CTTZ, VT, Custom);
1541 setOperationAction(ISD::CTLZ, VT, Custom);
1542 setOperationAction(ISD::SMAX, VT, Legal);
1543 setOperationAction(ISD::UMAX, VT, Legal);
1544 setOperationAction(ISD::SMIN, VT, Legal);
1545 setOperationAction(ISD::UMIN, VT, Legal);
1546
1547 setOperationPromotedToType(ISD::AND, VT, MVT::v8i64);
1548 setOperationPromotedToType(ISD::OR, VT, MVT::v8i64);
1549 setOperationPromotedToType(ISD::XOR, VT, MVT::v8i64);
1550 }
1551
1552 for (auto ExtType : {ISD::ZEXTLOAD, ISD::SEXTLOAD}) {
1553 setLoadExtAction(ExtType, MVT::v32i16, MVT::v32i8, Legal);
1554 }
1555
1556 if (Subtarget.hasBITALG()) {
1557 for (auto VT : { MVT::v64i8, MVT::v32i16 })
1558 setOperationAction(ISD::CTPOP, VT, Legal);
1559 }
1560 }
1561
1562 if (!Subtarget.useSoftFloat() && Subtarget.hasBWI()) {
1563 for (auto VT : { MVT::v32i8, MVT::v16i8, MVT::v16i16, MVT::v8i16 }) {
1564 setOperationAction(ISD::MLOAD, VT, Subtarget.hasVLX() ? Legal : Custom);
1565 setOperationAction(ISD::MSTORE, VT, Subtarget.hasVLX() ? Legal : Custom);
1566 }
1567
1568 // These operations are handled on non-VLX by artificially widening in
1569 // isel patterns.
1570 // TODO: Custom widen in lowering on non-VLX and drop the isel patterns?
1571
1572 if (Subtarget.hasBITALG()) {
1573 for (auto VT : { MVT::v16i8, MVT::v32i8, MVT::v8i16, MVT::v16i16 })
1574 setOperationAction(ISD::CTPOP, VT, Legal);
1575 }
1576 }
1577
1578 if (!Subtarget.useSoftFloat() && Subtarget.hasVLX()) {
1579 setTruncStoreAction(MVT::v4i64, MVT::v4i8, Legal);
1580 setTruncStoreAction(MVT::v4i64, MVT::v4i16, Legal);
1581 setTruncStoreAction(MVT::v4i64, MVT::v4i32, Legal);
1582 setTruncStoreAction(MVT::v8i32, MVT::v8i8, Legal);
1583 setTruncStoreAction(MVT::v8i32, MVT::v8i16, Legal);
1584
1585 setTruncStoreAction(MVT::v2i64, MVT::v2i8, Legal);
1586 setTruncStoreAction(MVT::v2i64, MVT::v2i16, Legal);
1587 setTruncStoreAction(MVT::v2i64, MVT::v2i32, Legal);
1588 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Legal);
1589 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Legal);
1590
1591 if (Subtarget.hasDQI()) {
1592 // Fast v2f32 SINT_TO_FP( v2i64 ) custom conversion.
1593 // v2f32 UINT_TO_FP is already custom under SSE2.
1594 setOperationAction(ISD::SINT_TO_FP, MVT::v2f32, Custom);
1595 assert(isOperationCustom(ISD::UINT_TO_FP, MVT::v2f32) &&(static_cast <bool> (isOperationCustom(ISD::UINT_TO_FP,
MVT::v2f32) && "Unexpected operation action!") ? void
(0) : __assert_fail ("isOperationCustom(ISD::UINT_TO_FP, MVT::v2f32) && \"Unexpected operation action!\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 1596, __extension__ __PRETTY_FUNCTION__))
1596 "Unexpected operation action!")(static_cast <bool> (isOperationCustom(ISD::UINT_TO_FP,
MVT::v2f32) && "Unexpected operation action!") ? void
(0) : __assert_fail ("isOperationCustom(ISD::UINT_TO_FP, MVT::v2f32) && \"Unexpected operation action!\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 1596, __extension__ __PRETTY_FUNCTION__))
;
1597 // v2i64 FP_TO_S/UINT(v2f32) custom conversion.
1598 setOperationAction(ISD::FP_TO_SINT, MVT::v2f32, Custom);
1599 setOperationAction(ISD::FP_TO_UINT, MVT::v2f32, Custom);
1600 }
1601
1602 if (Subtarget.hasBWI()) {
1603 setTruncStoreAction(MVT::v16i16, MVT::v16i8, Legal);
1604 setTruncStoreAction(MVT::v8i16, MVT::v8i8, Legal);
1605 }
1606 }
1607
1608 // We want to custom lower some of our intrinsics.
1609 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1610 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1611 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1612 if (!Subtarget.is64Bit()) {
1613 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1614 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom);
1615 }
1616
1617 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1618 // handle type legalization for these operations here.
1619 //
1620 // FIXME: We really should do custom legalization for addition and
1621 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1622 // than generic legalization for 64-bit multiplication-with-overflow, though.
1623 for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
1624 if (VT == MVT::i64 && !Subtarget.is64Bit())
1625 continue;
1626 // Add/Sub/Mul with overflow operations are custom lowered.
1627 setOperationAction(ISD::SADDO, VT, Custom);
1628 setOperationAction(ISD::UADDO, VT, Custom);
1629 setOperationAction(ISD::SSUBO, VT, Custom);
1630 setOperationAction(ISD::USUBO, VT, Custom);
1631 setOperationAction(ISD::SMULO, VT, Custom);
1632 setOperationAction(ISD::UMULO, VT, Custom);
1633
1634 // Support carry in as value rather than glue.
1635 setOperationAction(ISD::ADDCARRY, VT, Custom);
1636 setOperationAction(ISD::SUBCARRY, VT, Custom);
1637 setOperationAction(ISD::SETCCCARRY, VT, Custom);
1638 }
1639
1640 if (!Subtarget.is64Bit()) {
1641 // These libcalls are not available in 32-bit.
1642 setLibcallName(RTLIB::SHL_I128, nullptr);
1643 setLibcallName(RTLIB::SRL_I128, nullptr);
1644 setLibcallName(RTLIB::SRA_I128, nullptr);
1645 setLibcallName(RTLIB::MUL_I128, nullptr);
1646 }
1647
1648 // Combine sin / cos into _sincos_stret if it is available.
1649 if (getLibcallName(RTLIB::SINCOS_STRET_F32) != nullptr &&
1650 getLibcallName(RTLIB::SINCOS_STRET_F64) != nullptr) {
1651 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1652 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1653 }
1654
1655 if (Subtarget.isTargetWin64()) {
1656 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1657 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1658 setOperationAction(ISD::SREM, MVT::i128, Custom);
1659 setOperationAction(ISD::UREM, MVT::i128, Custom);
1660 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1661 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1662 }
1663
1664 // On 32 bit MSVC, `fmodf(f32)` is not defined - only `fmod(f64)`
1665 // is. We should promote the value to 64-bits to solve this.
1666 // This is what the CRT headers do - `fmodf` is an inline header
1667 // function casting to f64 and calling `fmod`.
1668 if (Subtarget.is32Bit() && (Subtarget.isTargetKnownWindowsMSVC() ||
1669 Subtarget.isTargetWindowsItanium()))
1670 for (ISD::NodeType Op :
1671 {ISD::FCEIL, ISD::FCOS, ISD::FEXP, ISD::FFLOOR, ISD::FREM, ISD::FLOG,
1672 ISD::FLOG10, ISD::FPOW, ISD::FSIN})
1673 if (isOperationExpand(Op, MVT::f32))
1674 setOperationAction(Op, MVT::f32, Promote);
1675
1676 // We have target-specific dag combine patterns for the following nodes:
1677 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1678 setTargetDAGCombine(ISD::SCALAR_TO_VECTOR);
1679 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1680 setTargetDAGCombine(ISD::INSERT_SUBVECTOR);
1681 setTargetDAGCombine(ISD::EXTRACT_SUBVECTOR);
1682 setTargetDAGCombine(ISD::BITCAST);
1683 setTargetDAGCombine(ISD::VSELECT);
1684 setTargetDAGCombine(ISD::SELECT);
1685 setTargetDAGCombine(ISD::SHL);
1686 setTargetDAGCombine(ISD::SRA);
1687 setTargetDAGCombine(ISD::SRL);
1688 setTargetDAGCombine(ISD::OR);
1689 setTargetDAGCombine(ISD::AND);
1690 setTargetDAGCombine(ISD::ADD);
1691 setTargetDAGCombine(ISD::FADD);
1692 setTargetDAGCombine(ISD::FSUB);
1693 setTargetDAGCombine(ISD::FNEG);
1694 setTargetDAGCombine(ISD::FMA);
1695 setTargetDAGCombine(ISD::FMINNUM);
1696 setTargetDAGCombine(ISD::FMAXNUM);
1697 setTargetDAGCombine(ISD::SUB);
1698 setTargetDAGCombine(ISD::LOAD);
1699 setTargetDAGCombine(ISD::MLOAD);
1700 setTargetDAGCombine(ISD::STORE);
1701 setTargetDAGCombine(ISD::MSTORE);
1702 setTargetDAGCombine(ISD::TRUNCATE);
1703 setTargetDAGCombine(ISD::ZERO_EXTEND);
1704 setTargetDAGCombine(ISD::ANY_EXTEND);
1705 setTargetDAGCombine(ISD::SIGN_EXTEND);
1706 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1707 setTargetDAGCombine(ISD::SIGN_EXTEND_VECTOR_INREG);
1708 setTargetDAGCombine(ISD::ZERO_EXTEND_VECTOR_INREG);
1709 setTargetDAGCombine(ISD::SINT_TO_FP);
1710 setTargetDAGCombine(ISD::UINT_TO_FP);
1711 setTargetDAGCombine(ISD::SETCC);
1712 setTargetDAGCombine(ISD::MUL);
1713 setTargetDAGCombine(ISD::XOR);
1714 setTargetDAGCombine(ISD::MSCATTER);
1715 setTargetDAGCombine(ISD::MGATHER);
1716
1717 computeRegisterProperties(Subtarget.getRegisterInfo());
1718
1719 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1720 MaxStoresPerMemsetOptSize = 8;
1721 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1722 MaxStoresPerMemcpyOptSize = 4;
1723 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1724 MaxStoresPerMemmoveOptSize = 4;
1725
1726 // TODO: These control memcmp expansion in CGP and could be raised higher, but
1727 // that needs to benchmarked and balanced with the potential use of vector
1728 // load/store types (PR33329, PR33914).
1729 MaxLoadsPerMemcmp = 2;
1730 MaxLoadsPerMemcmpOptSize = 2;
1731
1732 // Set loop alignment to 2^ExperimentalPrefLoopAlignment bytes (default: 2^4).
1733 setPrefLoopAlignment(ExperimentalPrefLoopAlignment);
1734
1735 // An out-of-order CPU can speculatively execute past a predictable branch,
1736 // but a conditional move could be stalled by an expensive earlier operation.
1737 PredictableSelectIsExpensive = Subtarget.getSchedModel().isOutOfOrder();
1738 EnableExtLdPromotion = true;
1739 setPrefFunctionAlignment(4); // 2^4 bytes.
1740
1741 verifyIntrinsicTables();
1742}
1743
1744// This has so far only been implemented for 64-bit MachO.
1745bool X86TargetLowering::useLoadStackGuardNode() const {
1746 return Subtarget.isTargetMachO() && Subtarget.is64Bit();
1747}
1748
1749bool X86TargetLowering::useStackGuardXorFP() const {
1750 // Currently only MSVC CRTs XOR the frame pointer into the stack guard value.
1751 return Subtarget.getTargetTriple().isOSMSVCRT();
1752}
1753
1754SDValue X86TargetLowering::emitStackGuardXorFP(SelectionDAG &DAG, SDValue Val,
1755 const SDLoc &DL) const {
1756 EVT PtrTy = getPointerTy(DAG.getDataLayout());
1757 unsigned XorOp = Subtarget.is64Bit() ? X86::XOR64_FP : X86::XOR32_FP;
1758 MachineSDNode *Node = DAG.getMachineNode(XorOp, DL, PtrTy, Val);
1759 return SDValue(Node, 0);
1760}
1761
1762TargetLoweringBase::LegalizeTypeAction
1763X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1764 if (VT == MVT::v32i1 && Subtarget.hasAVX512() && !Subtarget.hasBWI())
1765 return TypeSplitVector;
1766
1767 if (ExperimentalVectorWideningLegalization &&
1768 VT.getVectorNumElements() != 1 &&
1769 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1770 return TypeWidenVector;
1771
1772 return TargetLoweringBase::getPreferredVectorAction(VT);
1773}
1774
1775MVT X86TargetLowering::getRegisterTypeForCallingConv(MVT VT) const {
1776 if (VT == MVT::v32i1 && Subtarget.hasAVX512() && !Subtarget.hasBWI())
1777 return MVT::v32i8;
1778 return TargetLowering::getRegisterTypeForCallingConv(VT);
1779}
1780
1781MVT X86TargetLowering::getRegisterTypeForCallingConv(LLVMContext &Context,
1782 EVT VT) const {
1783 if (VT == MVT::v32i1 && Subtarget.hasAVX512() && !Subtarget.hasBWI())
1784 return MVT::v32i8;
1785 return TargetLowering::getRegisterTypeForCallingConv(Context, VT);
1786}
1787
1788unsigned X86TargetLowering::getNumRegistersForCallingConv(LLVMContext &Context,
1789 EVT VT) const {
1790 if (VT == MVT::v32i1 && Subtarget.hasAVX512() && !Subtarget.hasBWI())
1791 return 1;
1792 return TargetLowering::getNumRegistersForCallingConv(Context, VT);
1793}
1794
1795EVT X86TargetLowering::getSetCCResultType(const DataLayout &DL,
1796 LLVMContext& Context,
1797 EVT VT) const {
1798 if (!VT.isVector())
1799 return MVT::i8;
1800
1801 if (Subtarget.hasAVX512()) {
1802 const unsigned NumElts = VT.getVectorNumElements();
1803
1804 // Figure out what this type will be legalized to.
1805 EVT LegalVT = VT;
1806 while (getTypeAction(Context, LegalVT) != TypeLegal)
1807 LegalVT = getTypeToTransformTo(Context, LegalVT);
1808
1809 // If we got a 512-bit vector then we'll definitely have a vXi1 compare.
1810 if (LegalVT.getSimpleVT().is512BitVector())
1811 return EVT::getVectorVT(Context, MVT::i1, NumElts);
1812
1813 if (LegalVT.getSimpleVT().isVector() && Subtarget.hasVLX()) {
1814 // If we legalized to less than a 512-bit vector, then we will use a vXi1
1815 // compare for vXi32/vXi64 for sure. If we have BWI we will also support
1816 // vXi16/vXi8.
1817 MVT EltVT = LegalVT.getSimpleVT().getVectorElementType();
1818 if (Subtarget.hasBWI() || EltVT.getSizeInBits() >= 32)
1819 return EVT::getVectorVT(Context, MVT::i1, NumElts);
1820 }
1821 }
1822
1823 return VT.changeVectorElementTypeToInteger();
1824}
1825
1826/// Helper for getByValTypeAlignment to determine
1827/// the desired ByVal argument alignment.
1828static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1829 if (MaxAlign == 16)
1830 return;
1831 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1832 if (VTy->getBitWidth() == 128)
1833 MaxAlign = 16;
1834 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1835 unsigned EltAlign = 0;
1836 getMaxByValAlign(ATy->getElementType(), EltAlign);
1837 if (EltAlign > MaxAlign)
1838 MaxAlign = EltAlign;
1839 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1840 for (auto *EltTy : STy->elements()) {
1841 unsigned EltAlign = 0;
1842 getMaxByValAlign(EltTy, EltAlign);
1843 if (EltAlign > MaxAlign)
1844 MaxAlign = EltAlign;
1845 if (MaxAlign == 16)
1846 break;
1847 }
1848 }
1849}
1850
1851/// Return the desired alignment for ByVal aggregate
1852/// function arguments in the caller parameter area. For X86, aggregates
1853/// that contain SSE vectors are placed at 16-byte boundaries while the rest
1854/// are at 4-byte boundaries.
1855unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty,
1856 const DataLayout &DL) const {
1857 if (Subtarget.is64Bit()) {
1858 // Max of 8 and alignment of type.
1859 unsigned TyAlign = DL.getABITypeAlignment(Ty);
1860 if (TyAlign > 8)
1861 return TyAlign;
1862 return 8;
1863 }
1864
1865 unsigned Align = 4;
1866 if (Subtarget.hasSSE1())
1867 getMaxByValAlign(Ty, Align);
1868 return Align;
1869}
1870
1871/// Returns the target specific optimal type for load
1872/// and store operations as a result of memset, memcpy, and memmove
1873/// lowering. If DstAlign is zero that means it's safe to destination
1874/// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1875/// means there isn't a need to check it against alignment requirement,
1876/// probably because the source does not need to be loaded. If 'IsMemset' is
1877/// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1878/// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1879/// source is constant so it does not need to be loaded.
1880/// It returns EVT::Other if the type should be determined using generic
1881/// target-independent logic.
1882EVT
1883X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1884 unsigned DstAlign, unsigned SrcAlign,
1885 bool IsMemset, bool ZeroMemset,
1886 bool MemcpyStrSrc,
1887 MachineFunction &MF) const {
1888 const Function &F = MF.getFunction();
1889 if (!F.hasFnAttribute(Attribute::NoImplicitFloat)) {
1890 if (Size >= 16 &&
1891 (!Subtarget.isUnalignedMem16Slow() ||
1892 ((DstAlign == 0 || DstAlign >= 16) &&
1893 (SrcAlign == 0 || SrcAlign >= 16)))) {
1894 // FIXME: Check if unaligned 32-byte accesses are slow.
1895 if (Size >= 32 && Subtarget.hasAVX()) {
1896 // Although this isn't a well-supported type for AVX1, we'll let
1897 // legalization and shuffle lowering produce the optimal codegen. If we
1898 // choose an optimal type with a vector element larger than a byte,
1899 // getMemsetStores() may create an intermediate splat (using an integer
1900 // multiply) before we splat as a vector.
1901 return MVT::v32i8;
1902 }
1903 if (Subtarget.hasSSE2())
1904 return MVT::v16i8;
1905 // TODO: Can SSE1 handle a byte vector?
1906 if (Subtarget.hasSSE1())
1907 return MVT::v4f32;
1908 } else if ((!IsMemset || ZeroMemset) && !MemcpyStrSrc && Size >= 8 &&
1909 !Subtarget.is64Bit() && Subtarget.hasSSE2()) {
1910 // Do not use f64 to lower memcpy if source is string constant. It's
1911 // better to use i32 to avoid the loads.
1912 // Also, do not use f64 to lower memset unless this is a memset of zeros.
1913 // The gymnastics of splatting a byte value into an XMM register and then
1914 // only using 8-byte stores (because this is a CPU with slow unaligned
1915 // 16-byte accesses) makes that a loser.
1916 return MVT::f64;
1917 }
1918 }
1919 // This is a compromise. If we reach here, unaligned accesses may be slow on
1920 // this target. However, creating smaller, aligned accesses could be even
1921 // slower and would certainly be a lot more code.
1922 if (Subtarget.is64Bit() && Size >= 8)
1923 return MVT::i64;
1924 return MVT::i32;
1925}
1926
1927bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1928 if (VT == MVT::f32)
1929 return X86ScalarSSEf32;
1930 else if (VT == MVT::f64)
1931 return X86ScalarSSEf64;
1932 return true;
1933}
1934
1935bool
1936X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1937 unsigned,
1938 unsigned,
1939 bool *Fast) const {
1940 if (Fast) {
1941 switch (VT.getSizeInBits()) {
1942 default:
1943 // 8-byte and under are always assumed to be fast.
1944 *Fast = true;
1945 break;
1946 case 128:
1947 *Fast = !Subtarget.isUnalignedMem16Slow();
1948 break;
1949 case 256:
1950 *Fast = !Subtarget.isUnalignedMem32Slow();
1951 break;
1952 // TODO: What about AVX-512 (512-bit) accesses?
1953 }
1954 }
1955 // Misaligned accesses of any size are always allowed.
1956 return true;
1957}
1958
1959/// Return the entry encoding for a jump table in the
1960/// current function. The returned value is a member of the
1961/// MachineJumpTableInfo::JTEntryKind enum.
1962unsigned X86TargetLowering::getJumpTableEncoding() const {
1963 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1964 // symbol.
1965 if (isPositionIndependent() && Subtarget.isPICStyleGOT())
1966 return MachineJumpTableInfo::EK_Custom32;
1967
1968 // Otherwise, use the normal jump table encoding heuristics.
1969 return TargetLowering::getJumpTableEncoding();
1970}
1971
1972bool X86TargetLowering::useSoftFloat() const {
1973 return Subtarget.useSoftFloat();
1974}
1975
1976void X86TargetLowering::markLibCallAttributes(MachineFunction *MF, unsigned CC,
1977 ArgListTy &Args) const {
1978
1979 // Only relabel X86-32 for C / Stdcall CCs.
1980 if (Subtarget.is64Bit())
1981 return;
1982 if (CC != CallingConv::C && CC != CallingConv::X86_StdCall)
1983 return;
1984 unsigned ParamRegs = 0;
1985 if (auto *M = MF->getFunction().getParent())
1986 ParamRegs = M->getNumberRegisterParameters();
1987
1988 // Mark the first N int arguments as having reg
1989 for (unsigned Idx = 0; Idx < Args.size(); Idx++) {
1990 Type *T = Args[Idx].Ty;
1991 if (T->isPointerTy() || T->isIntegerTy())
1992 if (MF->getDataLayout().getTypeAllocSize(T) <= 8) {
1993 unsigned numRegs = 1;
1994 if (MF->getDataLayout().getTypeAllocSize(T) > 4)
1995 numRegs = 2;
1996 if (ParamRegs < numRegs)
1997 return;
1998 ParamRegs -= numRegs;
1999 Args[Idx].IsInReg = true;
2000 }
2001 }
2002}
2003
2004const MCExpr *
2005X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
2006 const MachineBasicBlock *MBB,
2007 unsigned uid,MCContext &Ctx) const{
2008 assert(isPositionIndependent() && Subtarget.isPICStyleGOT())(static_cast <bool> (isPositionIndependent() &&
Subtarget.isPICStyleGOT()) ? void (0) : __assert_fail ("isPositionIndependent() && Subtarget.isPICStyleGOT()"
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 2008, __extension__ __PRETTY_FUNCTION__))
;
2009 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
2010 // entries.
2011 return MCSymbolRefExpr::create(MBB->getSymbol(),
2012 MCSymbolRefExpr::VK_GOTOFF, Ctx);
2013}
2014
2015/// Returns relocation base for the given PIC jumptable.
2016SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
2017 SelectionDAG &DAG) const {
2018 if (!Subtarget.is64Bit())
2019 // This doesn't have SDLoc associated with it, but is not really the
2020 // same as a Register.
2021 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(),
2022 getPointerTy(DAG.getDataLayout()));
2023 return Table;
2024}
2025
2026/// This returns the relocation base for the given PIC jumptable,
2027/// the same as getPICJumpTableRelocBase, but as an MCExpr.
2028const MCExpr *X86TargetLowering::
2029getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
2030 MCContext &Ctx) const {
2031 // X86-64 uses RIP relative addressing based on the jump table label.
2032 if (Subtarget.isPICStyleRIPRel())
2033 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
2034
2035 // Otherwise, the reference is relative to the PIC base.
2036 return MCSymbolRefExpr::create(MF->getPICBaseSymbol(), Ctx);
2037}
2038
2039std::pair<const TargetRegisterClass *, uint8_t>
2040X86TargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
2041 MVT VT) const {
2042 const TargetRegisterClass *RRC = nullptr;
2043 uint8_t Cost = 1;
2044 switch (VT.SimpleTy) {
2045 default:
2046 return TargetLowering::findRepresentativeClass(TRI, VT);
2047 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
2048 RRC = Subtarget.is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
2049 break;
2050 case MVT::x86mmx:
2051 RRC = &X86::VR64RegClass;
2052 break;
2053 case MVT::f32: case MVT::f64:
2054 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
2055 case MVT::v4f32: case MVT::v2f64:
2056 case MVT::v32i8: case MVT::v16i16: case MVT::v8i32: case MVT::v4i64:
2057 case MVT::v8f32: case MVT::v4f64:
2058 case MVT::v64i8: case MVT::v32i16: case MVT::v16i32: case MVT::v8i64:
2059 case MVT::v16f32: case MVT::v8f64:
2060 RRC = &X86::VR128XRegClass;
2061 break;
2062 }
2063 return std::make_pair(RRC, Cost);
2064}
2065
2066unsigned X86TargetLowering::getAddressSpace() const {
2067 if (Subtarget.is64Bit())
2068 return (getTargetMachine().getCodeModel() == CodeModel::Kernel) ? 256 : 257;
2069 return 256;
2070}
2071
2072static bool hasStackGuardSlotTLS(const Triple &TargetTriple) {
2073 return TargetTriple.isOSGlibc() || TargetTriple.isOSFuchsia() ||
2074 (TargetTriple.isAndroid() && !TargetTriple.isAndroidVersionLT(17));
2075}
2076
2077static Constant* SegmentOffset(IRBuilder<> &IRB,
2078 unsigned Offset, unsigned AddressSpace) {
2079 return ConstantExpr::getIntToPtr(
2080 ConstantInt::get(Type::getInt32Ty(IRB.getContext()), Offset),
2081 Type::getInt8PtrTy(IRB.getContext())->getPointerTo(AddressSpace));
2082}
2083
2084Value *X86TargetLowering::getIRStackGuard(IRBuilder<> &IRB) const {
2085 // glibc, bionic, and Fuchsia have a special slot for the stack guard in
2086 // tcbhead_t; use it instead of the usual global variable (see
2087 // sysdeps/{i386,x86_64}/nptl/tls.h)
2088 if (hasStackGuardSlotTLS(Subtarget.getTargetTriple())) {
2089 if (Subtarget.isTargetFuchsia()) {
2090 // <zircon/tls.h> defines ZX_TLS_STACK_GUARD_OFFSET with this value.
2091 return SegmentOffset(IRB, 0x10, getAddressSpace());
2092 } else {
2093 // %fs:0x28, unless we're using a Kernel code model, in which case
2094 // it's %gs:0x28. gs:0x14 on i386.
2095 unsigned Offset = (Subtarget.is64Bit()) ? 0x28 : 0x14;
2096 return SegmentOffset(IRB, Offset, getAddressSpace());
2097 }
2098 }
2099
2100 return TargetLowering::getIRStackGuard(IRB);
2101}
2102
2103void X86TargetLowering::insertSSPDeclarations(Module &M) const {
2104 // MSVC CRT provides functionalities for stack protection.
2105 if (Subtarget.getTargetTriple().isWindowsMSVCEnvironment() ||
2106 Subtarget.getTargetTriple().isWindowsItaniumEnvironment()) {
2107 // MSVC CRT has a global variable holding security cookie.
2108 M.getOrInsertGlobal("__security_cookie",
2109 Type::getInt8PtrTy(M.getContext()));
2110
2111 // MSVC CRT has a function to validate security cookie.
2112 auto *SecurityCheckCookie = cast<Function>(
2113 M.getOrInsertFunction("__security_check_cookie",
2114 Type::getVoidTy(M.getContext()),
2115 Type::getInt8PtrTy(M.getContext())));
2116 SecurityCheckCookie->setCallingConv(CallingConv::X86_FastCall);
2117 SecurityCheckCookie->addAttribute(1, Attribute::AttrKind::InReg);
2118 return;
2119 }
2120 // glibc, bionic, and Fuchsia have a special slot for the stack guard.
2121 if (hasStackGuardSlotTLS(Subtarget.getTargetTriple()))
2122 return;
2123 TargetLowering::insertSSPDeclarations(M);
2124}
2125
2126Value *X86TargetLowering::getSDagStackGuard(const Module &M) const {
2127 // MSVC CRT has a global variable holding security cookie.
2128 if (Subtarget.getTargetTriple().isWindowsMSVCEnvironment() ||
2129 Subtarget.getTargetTriple().isWindowsItaniumEnvironment()) {
2130 return M.getGlobalVariable("__security_cookie");
2131 }
2132 return TargetLowering::getSDagStackGuard(M);
2133}
2134
2135Value *X86TargetLowering::getSSPStackGuardCheck(const Module &M) const {
2136 // MSVC CRT has a function to validate security cookie.
2137 if (Subtarget.getTargetTriple().isWindowsMSVCEnvironment() ||
2138 Subtarget.getTargetTriple().isWindowsItaniumEnvironment()) {
2139 return M.getFunction("__security_check_cookie");
2140 }
2141 return TargetLowering::getSSPStackGuardCheck(M);
2142}
2143
2144Value *X86TargetLowering::getSafeStackPointerLocation(IRBuilder<> &IRB) const {
2145 if (Subtarget.getTargetTriple().isOSContiki())
2146 return getDefaultSafeStackPointerLocation(IRB, false);
2147
2148 // Android provides a fixed TLS slot for the SafeStack pointer. See the
2149 // definition of TLS_SLOT_SAFESTACK in
2150 // https://android.googlesource.com/platform/bionic/+/master/libc/private/bionic_tls.h
2151 if (Subtarget.isTargetAndroid()) {
2152 // %fs:0x48, unless we're using a Kernel code model, in which case it's %gs:
2153 // %gs:0x24 on i386
2154 unsigned Offset = (Subtarget.is64Bit()) ? 0x48 : 0x24;
2155 return SegmentOffset(IRB, Offset, getAddressSpace());
2156 }
2157
2158 // Fuchsia is similar.
2159 if (Subtarget.isTargetFuchsia()) {
2160 // <zircon/tls.h> defines ZX_TLS_UNSAFE_SP_OFFSET with this value.
2161 return SegmentOffset(IRB, 0x18, getAddressSpace());
2162 }
2163
2164 return TargetLowering::getSafeStackPointerLocation(IRB);
2165}
2166
2167bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
2168 unsigned DestAS) const {
2169 assert(SrcAS != DestAS && "Expected different address spaces!")(static_cast <bool> (SrcAS != DestAS && "Expected different address spaces!"
) ? void (0) : __assert_fail ("SrcAS != DestAS && \"Expected different address spaces!\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 2169, __extension__ __PRETTY_FUNCTION__))
;
2170
2171 return SrcAS < 256 && DestAS < 256;
2172}
2173
2174//===----------------------------------------------------------------------===//
2175// Return Value Calling Convention Implementation
2176//===----------------------------------------------------------------------===//
2177
2178#include "X86GenCallingConv.inc"
2179
2180bool X86TargetLowering::CanLowerReturn(
2181 CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
2182 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
2183 SmallVector<CCValAssign, 16> RVLocs;
2184 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
2185 return CCInfo.CheckReturn(Outs, RetCC_X86);
2186}
2187
2188const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
2189 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
2190 return ScratchRegs;
2191}
2192
2193/// Lowers masks values (v*i1) to the local register values
2194/// \returns DAG node after lowering to register type
2195static SDValue lowerMasksToReg(const SDValue &ValArg, const EVT &ValLoc,
2196 const SDLoc &Dl, SelectionDAG &DAG) {
2197 EVT ValVT = ValArg.getValueType();
2198
2199 if (ValVT == MVT::v1i1)
2200 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, Dl, ValLoc, ValArg,
2201 DAG.getIntPtrConstant(0, Dl));
2202
2203 if ((ValVT == MVT::v8i1 && (ValLoc == MVT::i8 || ValLoc == MVT::i32)) ||
2204 (ValVT == MVT::v16i1 && (ValLoc == MVT::i16 || ValLoc == MVT::i32))) {
2205 // Two stage lowering might be required
2206 // bitcast: v8i1 -> i8 / v16i1 -> i16
2207 // anyextend: i8 -> i32 / i16 -> i32
2208 EVT TempValLoc = ValVT == MVT::v8i1 ? MVT::i8 : MVT::i16;
2209 SDValue ValToCopy = DAG.getBitcast(TempValLoc, ValArg);
2210 if (ValLoc == MVT::i32)
2211 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, Dl, ValLoc, ValToCopy);
2212 return ValToCopy;
2213 }
2214
2215 if ((ValVT == MVT::v32i1 && ValLoc == MVT::i32) ||
2216 (ValVT == MVT::v64i1 && ValLoc == MVT::i64)) {
2217 // One stage lowering is required
2218 // bitcast: v32i1 -> i32 / v64i1 -> i64
2219 return DAG.getBitcast(ValLoc, ValArg);
2220 }
2221
2222 return DAG.getNode(ISD::ANY_EXTEND, Dl, ValLoc, ValArg);
2223}
2224
2225/// Breaks v64i1 value into two registers and adds the new node to the DAG
2226static void Passv64i1ArgInRegs(
2227 const SDLoc &Dl, SelectionDAG &DAG, SDValue Chain, SDValue &Arg,
2228 SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass, CCValAssign &VA,
2229 CCValAssign &NextVA, const X86Subtarget &Subtarget) {
2230 assert(Subtarget.hasBWI() && "Expected AVX512BW target!")(static_cast <bool> (Subtarget.hasBWI() && "Expected AVX512BW target!"
) ? void (0) : __assert_fail ("Subtarget.hasBWI() && \"Expected AVX512BW target!\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 2230, __extension__ __PRETTY_FUNCTION__))
;
2231 assert(Subtarget.is32Bit() && "Expecting 32 bit target")(static_cast <bool> (Subtarget.is32Bit() && "Expecting 32 bit target"
) ? void (0) : __assert_fail ("Subtarget.is32Bit() && \"Expecting 32 bit target\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 2231, __extension__ __PRETTY_FUNCTION__))
;
2232 assert(Arg.getValueType() == MVT::i64 && "Expecting 64 bit value")(static_cast <bool> (Arg.getValueType() == MVT::i64 &&
"Expecting 64 bit value") ? void (0) : __assert_fail ("Arg.getValueType() == MVT::i64 && \"Expecting 64 bit value\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 2232, __extension__ __PRETTY_FUNCTION__))
;
2233 assert(VA.isRegLoc() && NextVA.isRegLoc() &&(static_cast <bool> (VA.isRegLoc() && NextVA.isRegLoc
() && "The value should reside in two registers") ? void
(0) : __assert_fail ("VA.isRegLoc() && NextVA.isRegLoc() && \"The value should reside in two registers\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 2234, __extension__ __PRETTY_FUNCTION__))
2234 "The value should reside in two registers")(static_cast <bool> (VA.isRegLoc() && NextVA.isRegLoc
() && "The value should reside in two registers") ? void
(0) : __assert_fail ("VA.isRegLoc() && NextVA.isRegLoc() && \"The value should reside in two registers\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 2234, __extension__ __PRETTY_FUNCTION__))
;
2235
2236 // Before splitting the value we cast it to i64
2237 Arg = DAG.getBitcast(MVT::i64, Arg);
2238
2239 // Splitting the value into two i32 types
2240 SDValue Lo, Hi;
2241 Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, Dl, MVT::i32, Arg,
2242 DAG.getConstant(0, Dl, MVT::i32));
2243 Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, Dl, MVT::i32, Arg,
2244 DAG.getConstant(1, Dl, MVT::i32));
2245
2246 // Attach the two i32 types into corresponding registers
2247 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Lo));
2248 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), Hi));
2249}
2250
2251SDValue
2252X86TargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
2253 bool isVarArg,
2254 const SmallVectorImpl<ISD::OutputArg> &Outs,
2255 const SmallVectorImpl<SDValue> &OutVals,
2256 const SDLoc &dl, SelectionDAG &DAG) const {
2257 MachineFunction &MF = DAG.getMachineFunction();
2258 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2259
2260 // In some cases we need to disable registers from the default CSR list.
2261 // For example, when they are used for argument passing.
2262 bool ShouldDisableCalleeSavedRegister =
2263 CallConv == CallingConv::X86_RegCall ||
2264 MF.getFunction().hasFnAttribute("no_caller_saved_registers");
2265
2266 if (CallConv == CallingConv::X86_INTR && !Outs.empty())
2267 report_fatal_error("X86 interrupts may not return any value");
2268
2269 SmallVector<CCValAssign, 16> RVLocs;
2270 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
2271 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
2272
2273 SDValue Flag;
2274 SmallVector<SDValue, 6> RetOps;
2275 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
2276 // Operand #1 = Bytes To Pop
2277 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(), dl,
2278 MVT::i32));
2279
2280 // Copy the result values into the output registers.
2281 for (unsigned I = 0, OutsIndex = 0, E = RVLocs.size(); I != E;
2282 ++I, ++OutsIndex) {
2283 CCValAssign &VA = RVLocs[I];
2284 assert(VA.isRegLoc() && "Can only return in registers!")(static_cast <bool> (VA.isRegLoc() && "Can only return in registers!"
) ? void (0) : __assert_fail ("VA.isRegLoc() && \"Can only return in registers!\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 2284, __extension__ __PRETTY_FUNCTION__))
;
2285
2286 // Add the register to the CalleeSaveDisableRegs list.
2287 if (ShouldDisableCalleeSavedRegister)
2288 MF.getRegInfo().disableCalleeSavedRegister(VA.getLocReg());
2289
2290 SDValue ValToCopy = OutVals[OutsIndex];
2291 EVT ValVT = ValToCopy.getValueType();
2292
2293 // Promote values to the appropriate types.
2294 if (VA.getLocInfo() == CCValAssign::SExt)
2295 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2296 else if (VA.getLocInfo() == CCValAssign::ZExt)
2297 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2298 else if (VA.getLocInfo() == CCValAssign::AExt) {
2299 if (ValVT.isVector() && ValVT.getVectorElementType() == MVT::i1)
2300 ValToCopy = lowerMasksToReg(ValToCopy, VA.getLocVT(), dl, DAG);
2301 else
2302 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2303 }
2304 else if (VA.getLocInfo() == CCValAssign::BCvt)
2305 ValToCopy = DAG.getBitcast(VA.getLocVT(), ValToCopy);
2306
2307 assert(VA.getLocInfo() != CCValAssign::FPExt &&(static_cast <bool> (VA.getLocInfo() != CCValAssign::FPExt
&& "Unexpected FP-extend for return value.") ? void (
0) : __assert_fail ("VA.getLocInfo() != CCValAssign::FPExt && \"Unexpected FP-extend for return value.\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 2308, __extension__ __PRETTY_FUNCTION__))
2308 "Unexpected FP-extend for return value.")(static_cast <bool> (VA.getLocInfo() != CCValAssign::FPExt
&& "Unexpected FP-extend for return value.") ? void (
0) : __assert_fail ("VA.getLocInfo() != CCValAssign::FPExt && \"Unexpected FP-extend for return value.\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 2308, __extension__ __PRETTY_FUNCTION__))
;
2309
2310 // If this is x86-64, and we disabled SSE, we can't return FP values,
2311 // or SSE or MMX vectors.
2312 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2313 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2314 (Subtarget.is64Bit() && !Subtarget.hasSSE1())) {
2315 errorUnsupported(DAG, dl, "SSE register return with SSE disabled");
2316 VA.convertToReg(X86::FP0); // Set reg to FP0, avoid hitting asserts.
2317 } else if (ValVT == MVT::f64 &&
2318 (Subtarget.is64Bit() && !Subtarget.hasSSE2())) {
2319 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
2320 // llvm-gcc has never done it right and no one has noticed, so this
2321 // should be OK for now.
2322 errorUnsupported(DAG, dl, "SSE2 register return with SSE2 disabled");
2323 VA.convertToReg(X86::FP0); // Set reg to FP0, avoid hitting asserts.
2324 }
2325
2326 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2327 // the RET instruction and handled by the FP Stackifier.
2328 if (VA.getLocReg() == X86::FP0 ||
2329 VA.getLocReg() == X86::FP1) {
2330 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2331 // change the value to the FP stack register class.
2332 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2333 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2334 RetOps.push_back(ValToCopy);
2335 // Don't emit a copytoreg.
2336 continue;
2337 }
2338
2339 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2340 // which is returned in RAX / RDX.
2341 if (Subtarget.is64Bit()) {
2342 if (ValVT == MVT::x86mmx) {
2343 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2344 ValToCopy = DAG.getBitcast(MVT::i64, ValToCopy);
2345 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2346 ValToCopy);
2347 // If we don't have SSE2 available, convert to v4f32 so the generated
2348 // register is legal.
2349 if (!Subtarget.hasSSE2())
2350 ValToCopy = DAG.getBitcast(MVT::v4f32, ValToCopy);
2351 }
2352 }
2353 }
2354
2355 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2356
2357 if (VA.needsCustom()) {
2358 assert(VA.getValVT() == MVT::v64i1 &&(static_cast <bool> (VA.getValVT() == MVT::v64i1 &&
"Currently the only custom case is when we split v64i1 to 2 regs"
) ? void (0) : __assert_fail ("VA.getValVT() == MVT::v64i1 && \"Currently the only custom case is when we split v64i1 to 2 regs\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 2359, __extension__ __PRETTY_FUNCTION__))
2359 "Currently the only custom case is when we split v64i1 to 2 regs")(static_cast <bool> (VA.getValVT() == MVT::v64i1 &&
"Currently the only custom case is when we split v64i1 to 2 regs"
) ? void (0) : __assert_fail ("VA.getValVT() == MVT::v64i1 && \"Currently the only custom case is when we split v64i1 to 2 regs\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 2359, __extension__ __PRETTY_FUNCTION__))
;
2360
2361 Passv64i1ArgInRegs(dl, DAG, Chain, ValToCopy, RegsToPass, VA, RVLocs[++I],
2362 Subtarget);
2363
2364 assert(2 == RegsToPass.size() &&(static_cast <bool> (2 == RegsToPass.size() && "Expecting two registers after Pass64BitArgInRegs"
) ? void (0) : __assert_fail ("2 == RegsToPass.size() && \"Expecting two registers after Pass64BitArgInRegs\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 2365, __extension__ __PRETTY_FUNCTION__))
2365 "Expecting two registers after Pass64BitArgInRegs")(static_cast <bool> (2 == RegsToPass.size() && "Expecting two registers after Pass64BitArgInRegs"
) ? void (0) : __assert_fail ("2 == RegsToPass.size() && \"Expecting two registers after Pass64BitArgInRegs\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 2365, __extension__ __PRETTY_FUNCTION__))
;
2366
2367 // Add the second register to the CalleeSaveDisableRegs list.
2368 if (ShouldDisableCalleeSavedRegister)
2369 MF.getRegInfo().disableCalleeSavedRegister(RVLocs[I].getLocReg());
2370 } else {
2371 RegsToPass.push_back(std::make_pair(VA.getLocReg(), ValToCopy));
2372 }
2373
2374 // Add nodes to the DAG and add the values into the RetOps list
2375 for (auto &Reg : RegsToPass) {
2376 Chain = DAG.getCopyToReg(Chain, dl, Reg.first, Reg.second, Flag);
2377 Flag = Chain.getValue(1);
2378 RetOps.push_back(DAG.getRegister(Reg.first, Reg.second.getValueType()));
2379 }
2380 }
2381
2382 // Swift calling convention does not require we copy the sret argument
2383 // into %rax/%eax for the return, and SRetReturnReg is not set for Swift.
2384
2385 // All x86 ABIs require that for returning structs by value we copy
2386 // the sret argument into %rax/%eax (depending on ABI) for the return.
2387 // We saved the argument into a virtual register in the entry block,
2388 // so now we copy the value out and into %rax/%eax.
2389 //
2390 // Checking Function.hasStructRetAttr() here is insufficient because the IR
2391 // may not have an explicit sret argument. If FuncInfo.CanLowerReturn is
2392 // false, then an sret argument may be implicitly inserted in the SelDAG. In
2393 // either case FuncInfo->setSRetReturnReg() will have been called.
2394 if (unsigned SRetReg = FuncInfo->getSRetReturnReg()) {
2395 // When we have both sret and another return value, we should use the
2396 // original Chain stored in RetOps[0], instead of the current Chain updated
2397 // in the above loop. If we only have sret, RetOps[0] equals to Chain.
2398
2399 // For the case of sret and another return value, we have
2400 // Chain_0 at the function entry
2401 // Chain_1 = getCopyToReg(Chain_0) in the above loop
2402 // If we use Chain_1 in getCopyFromReg, we will have
2403 // Val = getCopyFromReg(Chain_1)
2404 // Chain_2 = getCopyToReg(Chain_1, Val) from below
2405
2406 // getCopyToReg(Chain_0) will be glued together with
2407 // getCopyToReg(Chain_1, Val) into Unit A, getCopyFromReg(Chain_1) will be
2408 // in Unit B, and we will have cyclic dependency between Unit A and Unit B:
2409 // Data dependency from Unit B to Unit A due to usage of Val in
2410 // getCopyToReg(Chain_1, Val)
2411 // Chain dependency from Unit A to Unit B
2412
2413 // So here, we use RetOps[0] (i.e Chain_0) for getCopyFromReg.
2414 SDValue Val = DAG.getCopyFromReg(RetOps[0], dl, SRetReg,
2415 getPointerTy(MF.getDataLayout()));
2416
2417 unsigned RetValReg
2418 = (Subtarget.is64Bit() && !Subtarget.isTarget64BitILP32()) ?
2419 X86::RAX : X86::EAX;
2420 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2421 Flag = Chain.getValue(1);
2422
2423 // RAX/EAX now acts like a return value.
2424 RetOps.push_back(
2425 DAG.getRegister(RetValReg, getPointerTy(DAG.getDataLayout())));
2426
2427 // Add the returned register to the CalleeSaveDisableRegs list.
2428 if (ShouldDisableCalleeSavedRegister)
2429 MF.getRegInfo().disableCalleeSavedRegister(RetValReg);
2430 }
2431
2432 const X86RegisterInfo *TRI = Subtarget.getRegisterInfo();
2433 const MCPhysReg *I =
2434 TRI->getCalleeSavedRegsViaCopy(&DAG.getMachineFunction());
2435 if (I) {
2436 for (; *I; ++I) {
2437 if (X86::GR64RegClass.contains(*I))
2438 RetOps.push_back(DAG.getRegister(*I, MVT::i64));
2439 else
2440 llvm_unreachable("Unexpected register class in CSRsViaCopy!")::llvm::llvm_unreachable_internal("Unexpected register class in CSRsViaCopy!"
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 2440)
;
2441 }
2442 }
2443
2444 RetOps[0] = Chain; // Update chain.
2445
2446 // Add the flag if we have it.
2447 if (Flag.getNode())
2448 RetOps.push_back(Flag);
2449
2450 X86ISD::NodeType opcode = X86ISD::RET_FLAG;
2451 if (CallConv == CallingConv::X86_INTR)
2452 opcode = X86ISD::IRET;
2453 return DAG.getNode(opcode, dl, MVT::Other, RetOps);
2454}
2455
2456bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2457 if (N->getNumValues() != 1 || !N->hasNUsesOfValue(1, 0))
2458 return false;
2459
2460 SDValue TCChain = Chain;
2461 SDNode *Copy = *N->use_begin();
2462 if (Copy->getOpcode() == ISD::CopyToReg) {
2463 // If the copy has a glue operand, we conservatively assume it isn't safe to
2464 // perform a tail call.
2465 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2466 return false;
2467 TCChain = Copy->getOperand(0);
2468 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2469 return false;
2470
2471 bool HasRet = false;
2472 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2473 UI != UE; ++UI) {
2474 if (UI->getOpcode() != X86ISD::RET_FLAG)
2475 return false;
2476 // If we are returning more than one value, we can definitely
2477 // not make a tail call see PR19530
2478 if (UI->getNumOperands() > 4)
2479 return false;
2480 if (UI->getNumOperands() == 4 &&
2481 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2482 return false;
2483 HasRet = true;
2484 }
2485
2486 if (!HasRet)
2487 return false;
2488
2489 Chain = TCChain;
2490 return true;
2491}
2492
2493EVT X86TargetLowering::getTypeForExtReturn(LLVMContext &Context, EVT VT,
2494 ISD::NodeType ExtendKind) const {
2495 MVT ReturnMVT = MVT::i32;
2496
2497 bool Darwin = Subtarget.getTargetTriple().isOSDarwin();
2498 if (VT == MVT::i1 || (!Darwin && (VT == MVT::i8 || VT == MVT::i16))) {
2499 // The ABI does not require i1, i8 or i16 to be extended.
2500 //
2501 // On Darwin, there is code in the wild relying on Clang's old behaviour of
2502 // always extending i8/i16 return values, so keep doing that for now.
2503 // (PR26665).
2504 ReturnMVT = MVT::i8;
2505 }
2506
2507 EVT MinVT = getRegisterType(Context, ReturnMVT);
2508 return VT.bitsLT(MinVT) ? MinVT : VT;
2509}
2510
2511/// Reads two 32 bit registers and creates a 64 bit mask value.
2512/// \param VA The current 32 bit value that need to be assigned.
2513/// \param NextVA The next 32 bit value that need to be assigned.
2514/// \param Root The parent DAG node.
2515/// \param [in,out] InFlag Represents SDvalue in the parent DAG node for
2516/// glue purposes. In the case the DAG is already using
2517/// physical register instead of virtual, we should glue
2518/// our new SDValue to InFlag SDvalue.
2519/// \return a new SDvalue of size 64bit.
2520static SDValue getv64i1Argument(CCValAssign &VA, CCValAssign &NextVA,
2521 SDValue &Root, SelectionDAG &DAG,
2522 const SDLoc &Dl, const X86Subtarget &Subtarget,
2523 SDValue *InFlag = nullptr) {
2524 assert((Subtarget.hasBWI()) && "Expected AVX512BW target!")(static_cast <bool> ((Subtarget.hasBWI()) && "Expected AVX512BW target!"
) ? void (0) : __assert_fail ("(Subtarget.hasBWI()) && \"Expected AVX512BW target!\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 2524, __extension__ __PRETTY_FUNCTION__))
;
2525 assert(Subtarget.is32Bit() && "Expecting 32 bit target")(static_cast <bool> (Subtarget.is32Bit() && "Expecting 32 bit target"
) ? void (0) : __assert_fail ("Subtarget.is32Bit() && \"Expecting 32 bit target\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 2525, __extension__ __PRETTY_FUNCTION__))
;
2526 assert(VA.getValVT() == MVT::v64i1 &&(static_cast <bool> (VA.getValVT() == MVT::v64i1 &&
"Expecting first location of 64 bit width type") ? void (0) :
__assert_fail ("VA.getValVT() == MVT::v64i1 && \"Expecting first location of 64 bit width type\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 2527, __extension__ __PRETTY_FUNCTION__))
2527 "Expecting first location of 64 bit width type")(static_cast <bool> (VA.getValVT() == MVT::v64i1 &&
"Expecting first location of 64 bit width type") ? void (0) :
__assert_fail ("VA.getValVT() == MVT::v64i1 && \"Expecting first location of 64 bit width type\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 2527, __extension__ __PRETTY_FUNCTION__))
;
2528 assert(NextVA.getValVT() == VA.getValVT() &&(static_cast <bool> (NextVA.getValVT() == VA.getValVT()
&& "The locations should have the same type") ? void
(0) : __assert_fail ("NextVA.getValVT() == VA.getValVT() && \"The locations should have the same type\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 2529, __extension__ __PRETTY_FUNCTION__))
2529 "The locations should have the same type")(static_cast <bool> (NextVA.getValVT() == VA.getValVT()
&& "The locations should have the same type") ? void
(0) : __assert_fail ("NextVA.getValVT() == VA.getValVT() && \"The locations should have the same type\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 2529, __extension__ __PRETTY_FUNCTION__))
;
2530 assert(VA.isRegLoc() && NextVA.isRegLoc() &&(static_cast <bool> (VA.isRegLoc() && NextVA.isRegLoc
() && "The values should reside in two registers") ? void
(0) : __assert_fail ("VA.isRegLoc() && NextVA.isRegLoc() && \"The values should reside in two registers\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 2531, __extension__ __PRETTY_FUNCTION__))
2531 "The values should reside in two registers")(static_cast <bool> (VA.isRegLoc() && NextVA.isRegLoc
() && "The values should reside in two registers") ? void
(0) : __assert_fail ("VA.isRegLoc() && NextVA.isRegLoc() && \"The values should reside in two registers\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 2531, __extension__ __PRETTY_FUNCTION__))
;
2532
2533 SDValue Lo, Hi;
2534 unsigned Reg;
2535 SDValue ArgValueLo, ArgValueHi;
2536
2537 MachineFunction &MF = DAG.getMachineFunction();
2538 const TargetRegisterClass *RC = &X86::GR32RegClass;
2539
2540 // Read a 32 bit value from the registers
2541 if (nullptr == InFlag) {
2542 // When no physical register is present,
2543 // create an intermediate virtual register
2544 Reg = MF.addLiveIn(VA.getLocReg(), RC);
2545 ArgValueLo = DAG.getCopyFromReg(Root, Dl, Reg, MVT::i32);
2546 Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
2547 ArgValueHi = DAG.getCopyFromReg(Root, Dl, Reg, MVT::i32);
2548 } else {
2549 // When a physical register is available read the value from it and glue
2550 // the reads together.
2551 ArgValueLo =
2552 DAG.getCopyFromReg(Root, Dl, VA.getLocReg(), MVT::i32, *InFlag);
2553 *InFlag = ArgValueLo.getValue(2);
2554 ArgValueHi =
2555 DAG.getCopyFromReg(Root, Dl, NextVA.getLocReg(), MVT::i32, *InFlag);
2556 *InFlag = ArgValueHi.getValue(2);
2557 }
2558
2559 // Convert the i32 type into v32i1 type
2560 Lo = DAG.getBitcast(MVT::v32i1, ArgValueLo);
2561
2562 // Convert the i32 type into v32i1 type
2563 Hi = DAG.getBitcast(MVT::v32i1, ArgValueHi);
2564
2565 // Concatenate the two values together
2566 return DAG.getNode(ISD::CONCAT_VECTORS, Dl, MVT::v64i1, Lo, Hi);
2567}
2568
2569/// The function will lower a register of various sizes (8/16/32/64)
2570/// to a mask value of the expected size (v8i1/v16i1/v32i1/v64i1)
2571/// \returns a DAG node contains the operand after lowering to mask type.
2572static SDValue lowerRegToMasks(const SDValue &ValArg, const EVT &ValVT,
2573 const EVT &ValLoc, const SDLoc &Dl,
2574 SelectionDAG &DAG) {
2575 SDValue ValReturned = ValArg;
2576
2577 if (ValVT == MVT::v1i1)
2578 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Dl, MVT::v1i1, ValReturned);
2579
2580 if (ValVT == MVT::v64i1) {
2581 // In 32 bit machine, this case is handled by getv64i1Argument
2582 assert(ValLoc == MVT::i64 && "Expecting only i64 locations")(static_cast <bool> (ValLoc == MVT::i64 && "Expecting only i64 locations"
) ? void (0) : __assert_fail ("ValLoc == MVT::i64 && \"Expecting only i64 locations\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 2582, __extension__ __PRETTY_FUNCTION__))
;
2583 // In 64 bit machine, There is no need to truncate the value only bitcast
2584 } else {
2585 MVT maskLen;
2586 switch (ValVT.getSimpleVT().SimpleTy) {
2587 case MVT::v8i1:
2588 maskLen = MVT::i8;
2589 break;
2590 case MVT::v16i1:
2591 maskLen = MVT::i16;
2592 break;
2593 case MVT::v32i1:
2594 maskLen = MVT::i32;
2595 break;
2596 default:
2597 llvm_unreachable("Expecting a vector of i1 types")::llvm::llvm_unreachable_internal("Expecting a vector of i1 types"
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 2597)
;
2598 }
2599
2600 ValReturned = DAG.getNode(ISD::TRUNCATE, Dl, maskLen, ValReturned);
2601 }
2602 return DAG.getBitcast(ValVT, ValReturned);
2603}
2604
2605/// Lower the result values of a call into the
2606/// appropriate copies out of appropriate physical registers.
2607///
2608SDValue X86TargetLowering::LowerCallResult(
2609 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
2610 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
2611 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals,
2612 uint32_t *RegMask) const {
2613
2614 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
2615 // Assign locations to each value returned by this call.
2616 SmallVector<CCValAssign, 16> RVLocs;
2617 bool Is64Bit = Subtarget.is64Bit();
2618 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2619 *DAG.getContext());
2620 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2621
2622 // Copy all of the result registers out of their specified physreg.
2623 for (unsigned I = 0, InsIndex = 0, E = RVLocs.size(); I != E;
2624 ++I, ++InsIndex) {
2625 CCValAssign &VA = RVLocs[I];
2626 EVT CopyVT = VA.getLocVT();
2627
2628 // In some calling conventions we need to remove the used registers
2629 // from the register mask.
2630 if (RegMask) {
2631 for (MCSubRegIterator SubRegs(VA.getLocReg(), TRI, /*IncludeSelf=*/true);
2632 SubRegs.isValid(); ++SubRegs)
2633 RegMask[*SubRegs / 32] &= ~(1u << (*SubRegs % 32));
2634 }
2635
2636 // If this is x86-64, and we disabled SSE, we can't return FP values
2637 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64 || CopyVT == MVT::f128) &&
2638 ((Is64Bit || Ins[InsIndex].Flags.isInReg()) && !Subtarget.hasSSE1())) {
2639 errorUnsupported(DAG, dl, "SSE register return with SSE disabled");
2640 VA.convertToReg(X86::FP0); // Set reg to FP0, avoid hitting asserts.
2641 }
2642
2643 // If we prefer to use the value in xmm registers, copy it out as f80 and
2644 // use a truncate to move it from fp stack reg to xmm reg.
2645 bool RoundAfterCopy = false;
2646 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2647 isScalarFPTypeInSSEReg(VA.getValVT())) {
2648 if (!Subtarget.hasX87())
2649 report_fatal_error("X87 register return with X87 disabled");
2650 CopyVT = MVT::f80;
2651 RoundAfterCopy = (CopyVT != VA.getLocVT());
2652 }
2653
2654 SDValue Val;
2655 if (VA.needsCustom()) {
2656 assert(VA.getValVT() == MVT::v64i1 &&(static_cast <bool> (VA.getValVT() == MVT::v64i1 &&
"Currently the only custom case is when we split v64i1 to 2 regs"
) ? void (0) : __assert_fail ("VA.getValVT() == MVT::v64i1 && \"Currently the only custom case is when we split v64i1 to 2 regs\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 2657, __extension__ __PRETTY_FUNCTION__))
2657 "Currently the only custom case is when we split v64i1 to 2 regs")(static_cast <bool> (VA.getValVT() == MVT::v64i1 &&
"Currently the only custom case is when we split v64i1 to 2 regs"
) ? void (0) : __assert_fail ("VA.getValVT() == MVT::v64i1 && \"Currently the only custom case is when we split v64i1 to 2 regs\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 2657, __extension__ __PRETTY_FUNCTION__))
;
2658 Val =
2659 getv64i1Argument(VA, RVLocs[++I], Chain, DAG, dl, Subtarget, &InFlag);
2660 } else {
2661 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), CopyVT, InFlag)
2662 .getValue(1);
2663 Val = Chain.getValue(0);
2664 InFlag = Chain.getValue(2);
2665 }
2666
2667 if (RoundAfterCopy)
2668 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2669 // This truncation won't change the value.
2670 DAG.getIntPtrConstant(1, dl));
2671
2672 if (VA.isExtInLoc() && (VA.getValVT().getScalarType() == MVT::i1)) {
2673 if (VA.getValVT().isVector() &&
2674 ((VA.getLocVT() == MVT::i64) || (VA.getLocVT() == MVT::i32) ||
2675 (VA.getLocVT() == MVT::i16) || (VA.getLocVT() == MVT::i8))) {
2676 // promoting a mask type (v*i1) into a register of type i64/i32/i16/i8
2677 Val = lowerRegToMasks(Val, VA.getValVT(), VA.getLocVT(), dl, DAG);
2678 } else
2679 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
2680 }
2681
2682 InVals.push_back(Val);
2683 }
2684
2685 return Chain;
2686}
2687
2688//===----------------------------------------------------------------------===//
2689// C & StdCall & Fast Calling Convention implementation
2690//===----------------------------------------------------------------------===//
2691// StdCall calling convention seems to be standard for many Windows' API
2692// routines and around. It differs from C calling convention just a little:
2693// callee should clean up the stack, not caller. Symbols should be also
2694// decorated in some fancy way :) It doesn't support any vector arguments.
2695// For info on fast calling convention see Fast Calling Convention (tail call)
2696// implementation LowerX86_32FastCCCallTo.
2697
2698/// CallIsStructReturn - Determines whether a call uses struct return
2699/// semantics.
2700enum StructReturnType {
2701 NotStructReturn,
2702 RegStructReturn,
2703 StackStructReturn
2704};
2705static StructReturnType
2706callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs, bool IsMCU) {
2707 if (Outs.empty())
2708 return NotStructReturn;
2709
2710 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2711 if (!Flags.isSRet())
2712 return NotStructReturn;
2713 if (Flags.isInReg() || IsMCU)
2714 return RegStructReturn;
2715 return StackStructReturn;
2716}
2717
2718/// Determines whether a function uses struct return semantics.
2719static StructReturnType
2720argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins, bool IsMCU) {
2721 if (Ins.empty())
2722 return NotStructReturn;
2723
2724 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2725 if (!Flags.isSRet())
2726 return NotStructReturn;
2727 if (Flags.isInReg() || IsMCU)
2728 return RegStructReturn;
2729 return StackStructReturn;
2730}
2731
2732/// Make a copy of an aggregate at address specified by "Src" to address
2733/// "Dst" with size and alignment information specified by the specific
2734/// parameter attribute. The copy will be passed as a byval function parameter.
2735static SDValue CreateCopyOfByValArgument(SDValue Src, SDValue Dst,
2736 SDValue Chain, ISD::ArgFlagsTy Flags,
2737 SelectionDAG &DAG, const SDLoc &dl) {
2738 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
2739
2740 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2741 /*isVolatile*/false, /*AlwaysInline=*/true,
2742 /*isTailCall*/false,
2743 MachinePointerInfo(), MachinePointerInfo());
2744}
2745
2746/// Return true if the calling convention is one that we can guarantee TCO for.
2747static bool canGuaranteeTCO(CallingConv::ID CC) {
2748 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2749 CC == CallingConv::X86_RegCall || CC == CallingConv::HiPE ||
2750 CC == CallingConv::HHVM);
2751}
2752
2753/// Return true if we might ever do TCO for calls with this calling convention.
2754static bool mayTailCallThisCC(CallingConv::ID CC) {
2755 switch (CC) {
2756 // C calling conventions:
2757 case CallingConv::C:
2758 case CallingConv::Win64:
2759 case CallingConv::X86_64_SysV:
2760 // Callee pop conventions:
2761 case CallingConv::X86_ThisCall:
2762 case CallingConv::X86_StdCall:
2763 case CallingConv::X86_VectorCall:
2764 case CallingConv::X86_FastCall:
2765 return true;
2766 default:
2767 return canGuaranteeTCO(CC);
2768 }
2769}
2770
2771/// Return true if the function is being made into a tailcall target by
2772/// changing its ABI.
2773static bool shouldGuaranteeTCO(CallingConv::ID CC, bool GuaranteedTailCallOpt) {
2774 return GuaranteedTailCallOpt && canGuaranteeTCO(CC);
2775}
2776
2777bool X86TargetLowering::mayBeEmittedAsTailCall(const CallInst *CI) const {
2778 auto Attr =
2779 CI->getParent()->getParent()->getFnAttribute("disable-tail-calls");
2780 if (!CI->isTailCall() || Attr.getValueAsString() == "true")
2781 return false;
2782
2783 ImmutableCallSite CS(CI);
2784 CallingConv::ID CalleeCC = CS.getCallingConv();
2785 if (!mayTailCallThisCC(CalleeCC))
2786 return false;
2787
2788 return true;
2789}
2790
2791SDValue
2792X86TargetLowering::LowerMemArgument(SDValue Chain, CallingConv::ID CallConv,
2793 const SmallVectorImpl<ISD::InputArg> &Ins,
2794 const SDLoc &dl, SelectionDAG &DAG,
2795 const CCValAssign &VA,
2796 MachineFrameInfo &MFI, unsigned i) const {
2797 // Create the nodes corresponding to a load from this parameter slot.
2798 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2799 bool AlwaysUseMutable = shouldGuaranteeTCO(
2800 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2801 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2802 EVT ValVT;
2803 MVT PtrVT = getPointerTy(DAG.getDataLayout());
2804
2805 // If value is passed by pointer we have address passed instead of the value
2806 // itself. No need to extend if the mask value and location share the same
2807 // absolute size.
2808 bool ExtendedInMem =
2809 VA.isExtInLoc() && VA.getValVT().getScalarType() == MVT::i1 &&
2810 VA.getValVT().getSizeInBits() != VA.getLocVT().getSizeInBits();
2811
2812 if (VA.getLocInfo() == CCValAssign::Indirect || ExtendedInMem)
2813 ValVT = VA.getLocVT();
2814 else
2815 ValVT = VA.getValVT();
2816
2817 // Calculate SP offset of interrupt parameter, re-arrange the slot normally
2818 // taken by a return address.
2819 int Offset = 0;
2820 if (CallConv == CallingConv::X86_INTR) {
2821 // X86 interrupts may take one or two arguments.
2822 // On the stack there will be no return address as in regular call.
2823 // Offset of last argument need to be set to -4/-8 bytes.
2824 // Where offset of the first argument out of two, should be set to 0 bytes.
2825 Offset = (Subtarget.is64Bit() ? 8 : 4) * ((i + 1) % Ins.size() - 1);
2826 if (Subtarget.is64Bit() && Ins.size() == 2) {
2827 // The stack pointer needs to be realigned for 64 bit handlers with error
2828 // code, so the argument offset changes by 8 bytes.
2829 Offset += 8;
2830 }
2831 }
2832
2833 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2834 // changed with more analysis.
2835 // In case of tail call optimization mark all arguments mutable. Since they
2836 // could be overwritten by lowering of arguments in case of a tail call.
2837 if (Flags.isByVal()) {
2838 unsigned Bytes = Flags.getByValSize();
2839 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2840 int FI = MFI.CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2841 // Adjust SP offset of interrupt parameter.
2842 if (CallConv == CallingConv::X86_INTR) {
2843 MFI.setObjectOffset(FI, Offset);
2844 }
2845 return DAG.getFrameIndex(FI, PtrVT);
2846 }
2847
2848 // This is an argument in memory. We might be able to perform copy elision.
2849 if (Flags.isCopyElisionCandidate()) {
2850 EVT ArgVT = Ins[i].ArgVT;
2851 SDValue PartAddr;
2852 if (Ins[i].PartOffset == 0) {
2853 // If this is a one-part value or the first part of a multi-part value,
2854 // create a stack object for the entire argument value type and return a
2855 // load from our portion of it. This assumes that if the first part of an
2856 // argument is in memory, the rest will also be in memory.
2857 int FI = MFI.CreateFixedObject(ArgVT.getStoreSize(), VA.getLocMemOffset(),
2858 /*Immutable=*/false);
2859 PartAddr = DAG.getFrameIndex(FI, PtrVT);
2860 return DAG.getLoad(
2861 ValVT, dl, Chain, PartAddr,
2862 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI));
2863 } else {
2864 // This is not the first piece of an argument in memory. See if there is
2865 // already a fixed stack object including this offset. If so, assume it
2866 // was created by the PartOffset == 0 branch above and create a load from
2867 // the appropriate offset into it.
2868 int64_t PartBegin = VA.getLocMemOffset();
2869 int64_t PartEnd = PartBegin + ValVT.getSizeInBits() / 8;
2870 int FI = MFI.getObjectIndexBegin();
2871 for (; MFI.isFixedObjectIndex(FI); ++FI) {
2872 int64_t ObjBegin = MFI.getObjectOffset(FI);
2873 int64_t ObjEnd = ObjBegin + MFI.getObjectSize(FI);
2874 if (ObjBegin <= PartBegin && PartEnd <= ObjEnd)
2875 break;
2876 }
2877 if (MFI.isFixedObjectIndex(FI)) {
2878 SDValue Addr =
2879 DAG.getNode(ISD::ADD, dl, PtrVT, DAG.getFrameIndex(FI, PtrVT),
2880 DAG.getIntPtrConstant(Ins[i].PartOffset, dl));
2881 return DAG.getLoad(
2882 ValVT, dl, Chain, Addr,
2883 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI,
2884 Ins[i].PartOffset));
2885 }
2886 }
2887 }
2888
2889 int FI = MFI.CreateFixedObject(ValVT.getSizeInBits() / 8,
2890 VA.getLocMemOffset(), isImmutable);
2891
2892 // Set SExt or ZExt flag.
2893 if (VA.getLocInfo() == CCValAssign::ZExt) {
2894 MFI.setObjectZExt(FI, true);
2895 } else if (VA.getLocInfo() == CCValAssign::SExt) {
2896 MFI.setObjectSExt(FI, true);
2897 }
2898
2899 // Adjust SP offset of interrupt parameter.
2900 if (CallConv == CallingConv::X86_INTR) {
2901 MFI.setObjectOffset(FI, Offset);
2902 }
2903
2904 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2905 SDValue Val = DAG.getLoad(
2906 ValVT, dl, Chain, FIN,
2907 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI));
2908 return ExtendedInMem
2909 ? (VA.getValVT().isVector()
2910 ? DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VA.getValVT(), Val)
2911 : DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val))
2912 : Val;
2913}
2914
2915// FIXME: Get this from tablegen.
2916static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2917 const X86Subtarget &Subtarget) {
2918 assert(Subtarget.is64Bit())(static_cast <bool> (Subtarget.is64Bit()) ? void (0) : __assert_fail
("Subtarget.is64Bit()", "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 2918, __extension__ __PRETTY_FUNCTION__))
;
2919
2920 if (Subtarget.isCallingConvWin64(CallConv)) {
2921 static const MCPhysReg GPR64ArgRegsWin64[] = {
2922 X86::RCX, X86::RDX, X86::R8, X86::R9
2923 };
2924 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2925 }
2926
2927 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2928 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2929 };
2930 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2931}
2932
2933// FIXME: Get this from tablegen.
2934static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2935 CallingConv::ID CallConv,
2936 const X86Subtarget &Subtarget) {
2937 assert(Subtarget.is64Bit())(static_cast <bool> (Subtarget.is64Bit()) ? void (0) : __assert_fail
("Subtarget.is64Bit()", "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 2937, __extension__ __PRETTY_FUNCTION__))
;
2938 if (Subtarget.isCallingConvWin64(CallConv)) {
2939 // The XMM registers which might contain var arg parameters are shadowed
2940 // in their paired GPR. So we only need to save the GPR to their home
2941 // slots.
2942 // TODO: __vectorcall will change this.
2943 return None;
2944 }
2945
2946 const Function &F = MF.getFunction();
2947 bool NoImplicitFloatOps = F.hasFnAttribute(Attribute::NoImplicitFloat);
2948 bool isSoftFloat = Subtarget.useSoftFloat();
2949 assert(!(isSoftFloat && NoImplicitFloatOps) &&(static_cast <bool> (!(isSoftFloat && NoImplicitFloatOps
) && "SSE register cannot be used when SSE is disabled!"
) ? void (0) : __assert_fail ("!(isSoftFloat && NoImplicitFloatOps) && \"SSE register cannot be used when SSE is disabled!\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 2950, __extension__ __PRETTY_FUNCTION__))
2950 "SSE register cannot be used when SSE is disabled!")(static_cast <bool> (!(isSoftFloat && NoImplicitFloatOps
) && "SSE register cannot be used when SSE is disabled!"
) ? void (0) : __assert_fail ("!(isSoftFloat && NoImplicitFloatOps) && \"SSE register cannot be used when SSE is disabled!\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 2950, __extension__ __PRETTY_FUNCTION__))
;
2951 if (isSoftFloat || NoImplicitFloatOps || !Subtarget.hasSSE1())
2952 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2953 // registers.
2954 return None;
2955
2956 static const MCPhysReg XMMArgRegs64Bit[] = {
2957 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2958 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2959 };
2960 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2961}
2962
2963#ifndef NDEBUG
2964static bool isSortedByValueNo(const SmallVectorImpl<CCValAssign> &ArgLocs) {
2965 return std::is_sorted(ArgLocs.begin(), ArgLocs.end(),
2966 [](const CCValAssign &A, const CCValAssign &B) -> bool {
2967 return A.getValNo() < B.getValNo();
2968 });
2969}
2970#endif
2971
2972SDValue X86TargetLowering::LowerFormalArguments(
2973 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
2974 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
2975 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
2976 MachineFunction &MF = DAG.getMachineFunction();
2977 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2978 const TargetFrameLowering &TFI = *Subtarget.getFrameLowering();
2979
2980 const Function &F = MF.getFunction();
2981 if (F.hasExternalLinkage() && Subtarget.isTargetCygMing() &&
2982 F.getName() == "main")
2983 FuncInfo->setForceFramePointer(true);
2984
2985 MachineFrameInfo &MFI = MF.getFrameInfo();
2986 bool Is64Bit = Subtarget.is64Bit();
2987 bool IsWin64 = Subtarget.isCallingConvWin64(CallConv);
2988
2989 assert((static_cast <bool> (!(isVarArg && canGuaranteeTCO
(CallConv)) && "Var args not supported with calling conv' regcall, fastcc, ghc or hipe"
) ? void (0) : __assert_fail ("!(isVarArg && canGuaranteeTCO(CallConv)) && \"Var args not supported with calling conv' regcall, fastcc, ghc or hipe\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 2991, __extension__ __PRETTY_FUNCTION__))
2990 !(isVarArg && canGuaranteeTCO(CallConv)) &&(static_cast <bool> (!(isVarArg && canGuaranteeTCO
(CallConv)) && "Var args not supported with calling conv' regcall, fastcc, ghc or hipe"
) ? void (0) : __assert_fail ("!(isVarArg && canGuaranteeTCO(CallConv)) && \"Var args not supported with calling conv' regcall, fastcc, ghc or hipe\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 2991, __extension__ __PRETTY_FUNCTION__))
2991 "Var args not supported with calling conv' regcall, fastcc, ghc or hipe")(static_cast <bool> (!(isVarArg && canGuaranteeTCO
(CallConv)) && "Var args not supported with calling conv' regcall, fastcc, ghc or hipe"
) ? void (0) : __assert_fail ("!(isVarArg && canGuaranteeTCO(CallConv)) && \"Var args not supported with calling conv' regcall, fastcc, ghc or hipe\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 2991, __extension__ __PRETTY_FUNCTION__))
;
2992
2993 if (CallConv == CallingConv::X86_INTR) {
2994 bool isLegal = Ins.size() == 1 ||
2995 (Ins.size() == 2 && ((Is64Bit && Ins[1].VT == MVT::i64) ||
2996 (!Is64Bit && Ins[1].VT == MVT::i32)));
2997 if (!isLegal)
2998 report_fatal_error("X86 interrupts may take one or two arguments");
2999 }
3000
3001 // Assign locations to all of the incoming arguments.
3002 SmallVector<CCValAssign, 16> ArgLocs;
3003 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
3004
3005 // Allocate shadow area for Win64.
3006 if (IsWin64)
3007 CCInfo.AllocateStack(32, 8);
3008
3009 CCInfo.AnalyzeArguments(Ins, CC_X86);
3010
3011 // In vectorcall calling convention a second pass is required for the HVA
3012 // types.
3013 if (CallingConv::X86_VectorCall == CallConv) {
3014 CCInfo.AnalyzeArgumentsSecondPass(Ins, CC_X86);
3015 }
3016
3017 // The next loop assumes that the locations are in the same order of the
3018 // input arguments.
3019 assert(isSortedByValueNo(ArgLocs) &&(static_cast <bool> (isSortedByValueNo(ArgLocs) &&
"Argument Location list must be sorted before lowering") ? void
(0) : __assert_fail ("isSortedByValueNo(ArgLocs) && \"Argument Location list must be sorted before lowering\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 3020, __extension__ __PRETTY_FUNCTION__))
3020 "Argument Location list must be sorted before lowering")(static_cast <bool> (isSortedByValueNo(ArgLocs) &&
"Argument Location list must be sorted before lowering") ? void
(0) : __assert_fail ("isSortedByValueNo(ArgLocs) && \"Argument Location list must be sorted before lowering\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 3020, __extension__ __PRETTY_FUNCTION__))
;
3021
3022 SDValue ArgValue;
3023 for (unsigned I = 0, InsIndex = 0, E = ArgLocs.size(); I != E;
3024 ++I, ++InsIndex) {
3025 assert(InsIndex < Ins.size() && "Invalid Ins index")(static_cast <bool> (InsIndex < Ins.size() &&
"Invalid Ins index") ? void (0) : __assert_fail ("InsIndex < Ins.size() && \"Invalid Ins index\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 3025, __extension__ __PRETTY_FUNCTION__))
;
3026 CCValAssign &VA = ArgLocs[I];
3027
3028 if (VA.isRegLoc()) {
3029 EVT RegVT = VA.getLocVT();
3030 if (VA.needsCustom()) {
3031 assert((static_cast <bool> (VA.getValVT() == MVT::v64i1 &&
"Currently the only custom case is when we split v64i1 to 2 regs"
) ? void (0) : __assert_fail ("VA.getValVT() == MVT::v64i1 && \"Currently the only custom case is when we split v64i1 to 2 regs\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 3033, __extension__ __PRETTY_FUNCTION__))
3032 VA.getValVT() == MVT::v64i1 &&(static_cast <bool> (VA.getValVT() == MVT::v64i1 &&
"Currently the only custom case is when we split v64i1 to 2 regs"
) ? void (0) : __assert_fail ("VA.getValVT() == MVT::v64i1 && \"Currently the only custom case is when we split v64i1 to 2 regs\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 3033, __extension__ __PRETTY_FUNCTION__))
3033 "Currently the only custom case is when we split v64i1 to 2 regs")(static_cast <bool> (VA.getValVT() == MVT::v64i1 &&
"Currently the only custom case is when we split v64i1 to 2 regs"
) ? void (0) : __assert_fail ("VA.getValVT() == MVT::v64i1 && \"Currently the only custom case is when we split v64i1 to 2 regs\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 3033, __extension__ __PRETTY_FUNCTION__))
;
3034
3035 // v64i1 values, in regcall calling convention, that are
3036 // compiled to 32 bit arch, are split up into two registers.
3037 ArgValue =
3038 getv64i1Argument(VA, ArgLocs[++I], Chain, DAG, dl, Subtarget);
3039 } else {
3040 const TargetRegisterClass *RC;
3041 if (RegVT == MVT::i8)
3042 RC = &X86::GR8RegClass;
3043 else if (RegVT == MVT::i16)
3044 RC = &X86::GR16RegClass;
3045 else if (RegVT == MVT::i32)
3046 RC = &X86::GR32RegClass;
3047 else if (Is64Bit && RegVT == MVT::i64)
3048 RC = &X86::GR64RegClass;
3049 else if (RegVT == MVT::f32)
3050 RC = Subtarget.hasAVX512() ? &X86::FR32XRegClass : &X86::FR32RegClass;
3051 else if (RegVT == MVT::f64)
3052 RC = Subtarget.hasAVX512() ? &X86::FR64XRegClass : &X86::FR64RegClass;
3053 else if (RegVT == MVT::f80)
3054 RC = &X86::RFP80RegClass;
3055 else if (RegVT == MVT::f128)
3056 RC = &X86::FR128RegClass;
3057 else if (RegVT.is512BitVector())
3058 RC = &X86::VR512RegClass;
3059 else if (RegVT.is256BitVector())
3060 RC = Subtarget.hasVLX() ? &X86::VR256XRegClass : &X86::VR256RegClass;
3061 else if (RegVT.is128BitVector())
3062 RC = Subtarget.hasVLX() ? &X86::VR128XRegClass : &X86::VR128RegClass;
3063 else if (RegVT == MVT::x86mmx)
3064 RC = &X86::VR64RegClass;
3065 else if (RegVT == MVT::v1i1)
3066 RC = &X86::VK1RegClass;
3067 else if (RegVT == MVT::v8i1)
3068 RC = &X86::VK8RegClass;
3069 else if (RegVT == MVT::v16i1)
3070 RC = &X86::VK16RegClass;
3071 else if (RegVT == MVT::v32i1)
3072 RC = &X86::VK32RegClass;
3073 else if (RegVT == MVT::v64i1)
3074 RC = &X86::VK64RegClass;
3075 else
3076 llvm_unreachable("Unknown argument type!")::llvm::llvm_unreachable_internal("Unknown argument type!", "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 3076)
;
3077
3078 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
3079 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
3080 }
3081
3082 // If this is an 8 or 16-bit value, it is really passed promoted to 32
3083 // bits. Insert an assert[sz]ext to capture this, then truncate to the
3084 // right size.
3085 if (VA.getLocInfo() == CCValAssign::SExt)
3086 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
3087 DAG.getValueType(VA.getValVT()));
3088 else if (VA.getLocInfo() == CCValAssign::ZExt)
3089 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
3090 DAG.getValueType(VA.getValVT()));
3091 else if (VA.getLocInfo() == CCValAssign::BCvt)
3092 ArgValue = DAG.getBitcast(VA.getValVT(), ArgValue);
3093
3094 if (VA.isExtInLoc()) {
3095 // Handle MMX values passed in XMM regs.
3096 if (RegVT.isVector() && VA.getValVT().getScalarType() != MVT::i1)
3097 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
3098 else if (VA.getValVT().isVector() &&
3099 VA.getValVT().getScalarType() == MVT::i1 &&
3100 ((VA.getLocVT() == MVT::i64) || (VA.getLocVT() == MVT::i32) ||
3101 (VA.getLocVT() == MVT::i16) || (VA.getLocVT() == MVT::i8))) {
3102 // Promoting a mask type (v*i1) into a register of type i64/i32/i16/i8
3103 ArgValue = lowerRegToMasks(ArgValue, VA.getValVT(), RegVT, dl, DAG);
3104 } else
3105 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
3106 }
3107 } else {
3108 assert(VA.isMemLoc())(static_cast <bool> (VA.isMemLoc()) ? void (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 3108, __extension__ __PRETTY_FUNCTION__))
;
3109 ArgValue =
3110 LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, InsIndex);
3111 }
3112
3113 // If value is passed via pointer - do a load.
3114 if (VA.getLocInfo() == CCValAssign::Indirect)
3115 ArgValue =
3116 DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue, MachinePointerInfo());
3117
3118 InVals.push_back(ArgValue);
3119 }
3120
3121 for (unsigned I = 0, E = Ins.size(); I != E; ++I) {
3122 // Swift calling convention does not require we copy the sret argument
3123 // into %rax/%eax for the return. We don't set SRetReturnReg for Swift.
3124 if (CallConv == CallingConv::Swift)
3125 continue;
3126
3127 // All x86 ABIs require that for returning structs by value we copy the
3128 // sret argument into %rax/%eax (depending on ABI) for the return. Save
3129 // the argument into a virtual register so that we can access it from the
3130 // return points.
3131 if (Ins[I].Flags.isSRet()) {
3132 unsigned Reg = FuncInfo->getSRetReturnReg();
3133 if (!Reg) {
3134 MVT PtrTy = getPointerTy(DAG.getDataLayout());
3135 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
3136 FuncInfo->setSRetReturnReg(Reg);
3137 }
3138 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[I]);
3139 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
3140 break;
3141 }
3142 }
3143
3144 unsigned StackSize = CCInfo.getNextStackOffset();
3145 // Align stack specially for tail calls.
3146 if (shouldGuaranteeTCO(CallConv,
3147 MF.getTarget().Options.GuaranteedTailCallOpt))
3148 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
3149
3150 // If the function takes variable number of arguments, make a frame index for
3151 // the start of the first vararg value... for expansion of llvm.va_start. We
3152 // can skip this if there are no va_start calls.
3153 if (MFI.hasVAStart() &&
3154 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
3155 CallConv != CallingConv::X86_ThisCall))) {
3156 FuncInfo->setVarArgsFrameIndex(MFI.CreateFixedObject(1, StackSize, true));
3157 }
3158
3159 // Figure out if XMM registers are in use.
3160 assert(!(Subtarget.useSoftFloat() &&(static_cast <bool> (!(Subtarget.useSoftFloat() &&
F.hasFnAttribute(Attribute::NoImplicitFloat)) && "SSE register cannot be used when SSE is disabled!"
) ? void (0) : __assert_fail ("!(Subtarget.useSoftFloat() && F.hasFnAttribute(Attribute::NoImplicitFloat)) && \"SSE register cannot be used when SSE is disabled!\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 3162, __extension__ __PRETTY_FUNCTION__))
3161 F.hasFnAttribute(Attribute::NoImplicitFloat)) &&(static_cast <bool> (!(Subtarget.useSoftFloat() &&
F.hasFnAttribute(Attribute::NoImplicitFloat)) && "SSE register cannot be used when SSE is disabled!"
) ? void (0) : __assert_fail ("!(Subtarget.useSoftFloat() && F.hasFnAttribute(Attribute::NoImplicitFloat)) && \"SSE register cannot be used when SSE is disabled!\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 3162, __extension__ __PRETTY_FUNCTION__))
3162 "SSE register cannot be used when SSE is disabled!")(static_cast <bool> (!(Subtarget.useSoftFloat() &&
F.hasFnAttribute(Attribute::NoImplicitFloat)) && "SSE register cannot be used when SSE is disabled!"
) ? void (0) : __assert_fail ("!(Subtarget.useSoftFloat() && F.hasFnAttribute(Attribute::NoImplicitFloat)) && \"SSE register cannot be used when SSE is disabled!\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 3162, __extension__ __PRETTY_FUNCTION__))
;
3163
3164 // 64-bit calling conventions support varargs and register parameters, so we
3165 // have to do extra work to spill them in the prologue.
3166 if (Is64Bit && isVarArg && MFI.hasVAStart()) {
3167 // Find the first unallocated argument registers.
3168 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
3169 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
3170 unsigned NumIntRegs = CCInfo.getFirstUnallocated(ArgGPRs);
3171 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(ArgXMMs);
3172 assert(!(NumXMMRegs && !Subtarget.hasSSE1()) &&(static_cast <bool> (!(NumXMMRegs && !Subtarget
.hasSSE1()) && "SSE register cannot be used when SSE is disabled!"
) ? void (0) : __assert_fail ("!(NumXMMRegs && !Subtarget.hasSSE1()) && \"SSE register cannot be used when SSE is disabled!\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 3173, __extension__ __PRETTY_FUNCTION__))
3173 "SSE register cannot be used when SSE is disabled!")(static_cast <bool> (!(NumXMMRegs && !Subtarget
.hasSSE1()) && "SSE register cannot be used when SSE is disabled!"
) ? void (0) : __assert_fail ("!(NumXMMRegs && !Subtarget.hasSSE1()) && \"SSE register cannot be used when SSE is disabled!\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 3173, __extension__ __PRETTY_FUNCTION__))
;
3174
3175 // Gather all the live in physical registers.
3176 SmallVector<SDValue, 6> LiveGPRs;
3177 SmallVector<SDValue, 8> LiveXMMRegs;
3178 SDValue ALVal;
3179 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
3180 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
3181 LiveGPRs.push_back(
3182 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
3183 }
3184 if (!ArgXMMs.empty()) {
3185 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
3186 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
3187 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
3188 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
3189 LiveXMMRegs.push_back(
3190 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
3191 }
3192 }
3193
3194 if (IsWin64) {
3195 // Get to the caller-allocated home save location. Add 8 to account
3196 // for the return address.
3197 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
3198 FuncInfo->setRegSaveFrameIndex(
3199 MFI.CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
3200 // Fixup to set vararg frame on shadow area (4 x i64).
3201 if (NumIntRegs < 4)
3202 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
3203 } else {
3204 // For X86-64, if there are vararg parameters that are passed via
3205 // registers, then we must store them to their spots on the stack so
3206 // they may be loaded by dereferencing the result of va_next.
3207 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
3208 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
3209 FuncInfo->setRegSaveFrameIndex(MFI.CreateStackObject(
3210 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
3211 }
3212
3213 // Store the integer parameter registers.
3214 SmallVector<SDValue, 8> MemOps;
3215 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
3216 getPointerTy(DAG.getDataLayout()));
3217 unsigned Offset = FuncInfo->getVarArgsGPOffset();
3218 for (SDValue Val : LiveGPRs) {
3219 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
3220 RSFIN, DAG.getIntPtrConstant(Offset, dl));
3221 SDValue Store =
3222 DAG.getStore(Val.getValue(1), dl, Val, FIN,
3223 MachinePointerInfo::getFixedStack(
3224 DAG.getMachineFunction(),
3225 FuncInfo->getRegSaveFrameIndex(), Offset));
3226 MemOps.push_back(Store);
3227 Offset += 8;
3228 }
3229
3230 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
3231 // Now store the XMM (fp + vector) parameter registers.
3232 SmallVector<SDValue, 12> SaveXMMOps;
3233 SaveXMMOps.push_back(Chain);
3234 SaveXMMOps.push_back(ALVal);
3235 SaveXMMOps.push_back(DAG.getIntPtrConstant(
3236 FuncInfo->getRegSaveFrameIndex(), dl));
3237 SaveXMMOps.push_back(DAG.getIntPtrConstant(
3238 FuncInfo->getVarArgsFPOffset(), dl));
3239 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
3240 LiveXMMRegs.end());
3241 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
3242 MVT::Other, SaveXMMOps));
3243 }
3244
3245 if (!MemOps.empty())
3246 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
3247 }
3248
3249 if (isVarArg && MFI.hasMustTailInVarArgFunc()) {
3250 // Find the largest legal vector type.
3251 MVT VecVT = MVT::Other;
3252 // FIXME: Only some x86_32 calling conventions support AVX512.
3253 if (Subtarget.hasAVX512() &&
3254 (Is64Bit || (CallConv == CallingConv::X86_VectorCall ||
3255 CallConv == CallingConv::Intel_OCL_BI)))
3256 VecVT = MVT::v16f32;
3257 else if (Subtarget.hasAVX())
3258 VecVT = MVT::v8f32;
3259 else if (Subtarget.hasSSE2())
3260 VecVT = MVT::v4f32;
3261
3262 // We forward some GPRs and some vector types.
3263 SmallVector<MVT, 2> RegParmTypes;
3264 MVT IntVT = Is64Bit ? MVT::i64 : MVT::i32;
3265 RegParmTypes.push_back(IntVT);
3266 if (VecVT != MVT::Other)
3267 RegParmTypes.push_back(VecVT);
3268
3269 // Compute the set of forwarded registers. The rest are scratch.
3270 SmallVectorImpl<ForwardedRegister> &Forwards =
3271 FuncInfo->getForwardedMustTailRegParms();
3272 CCInfo.analyzeMustTailForwardedRegisters(Forwards, RegParmTypes, CC_X86);
3273
3274 // Conservatively forward AL on x86_64, since it might be used for varargs.
3275 if (Is64Bit && !CCInfo.isAllocated(X86::AL)) {
3276 unsigned ALVReg = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
3277 Forwards.push_back(ForwardedRegister(ALVReg, X86::AL, MVT::i8));
3278 }
3279
3280 // Copy all forwards from physical to virtual registers.
3281 for (ForwardedRegister &F : Forwards) {
3282 // FIXME: Can we use a less constrained schedule?
3283 SDValue RegVal = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
3284 F.VReg = MF.getRegInfo().createVirtualRegister(getRegClassFor(F.VT));
3285 Chain = DAG.getCopyToReg(Chain, dl, F.VReg, RegVal);
3286 }
3287 }
3288
3289 // Some CCs need callee pop.
3290 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3291 MF.getTarget().Options.GuaranteedTailCallOpt)) {
3292 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
3293 } else if (CallConv == CallingConv::X86_INTR && Ins.size() == 2) {
3294 // X86 interrupts must pop the error code (and the alignment padding) if
3295 // present.
3296 FuncInfo->setBytesToPopOnReturn(Is64Bit ? 16 : 4);
3297 } else {
3298 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
3299 // If this is an sret function, the return should pop the hidden pointer.
3300 if (!Is64Bit && !canGuaranteeTCO(CallConv) &&
3301 !Subtarget.getTargetTriple().isOSMSVCRT() &&
3302 argsAreStructReturn(Ins, Subtarget.isTargetMCU()) == StackStructReturn)
3303 FuncInfo->setBytesToPopOnReturn(4);
3304 }
3305
3306 if (!Is64Bit) {
3307 // RegSaveFrameIndex is X86-64 only.
3308 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
3309 if (CallConv == CallingConv::X86_FastCall ||
3310 CallConv == CallingConv::X86_ThisCall)
3311 // fastcc functions can't have varargs.
3312 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
3313 }
3314
3315 FuncInfo->setArgumentStackSize(StackSize);
3316
3317 if (WinEHFuncInfo *EHInfo = MF.getWinEHFuncInfo()) {
3318 EHPersonality Personality = classifyEHPersonality(F.getPersonalityFn());
3319 if (Personality == EHPersonality::CoreCLR) {
3320 assert(Is64Bit)(static_cast <bool> (Is64Bit) ? void (0) : __assert_fail
("Is64Bit", "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 3320, __extension__ __PRETTY_FUNCTION__))
;
3321 // TODO: Add a mechanism to frame lowering that will allow us to indicate
3322 // that we'd prefer this slot be allocated towards the bottom of the frame
3323 // (i.e. near the stack pointer after allocating the frame). Every
3324 // funclet needs a copy of this slot in its (mostly empty) frame, and the
3325 // offset from the bottom of this and each funclet's frame must be the
3326 // same, so the size of funclets' (mostly empty) frames is dictated by
3327 // how far this slot is from the bottom (since they allocate just enough
3328 // space to accommodate holding this slot at the correct offset).
3329 int PSPSymFI = MFI.CreateStackObject(8, 8, /*isSS=*/false);
3330 EHInfo->PSPSymFrameIdx = PSPSymFI;
3331 }
3332 }
3333
3334 if (CallConv == CallingConv::X86_RegCall ||
3335 F.hasFnAttribute("no_caller_saved_registers")) {
3336 MachineRegisterInfo &MRI = MF.getRegInfo();
3337 for (std::pair<unsigned, unsigned> Pair : MRI.liveins())
3338 MRI.disableCalleeSavedRegister(Pair.first);
3339 }
3340
3341 return Chain;
3342}
3343
3344SDValue X86TargetLowering::LowerMemOpCallTo(SDValue Chain, SDValue StackPtr,
3345 SDValue Arg, const SDLoc &dl,
3346 SelectionDAG &DAG,
3347 const CCValAssign &VA,
3348 ISD::ArgFlagsTy Flags) const {
3349 unsigned LocMemOffset = VA.getLocMemOffset();
3350 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
3351 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
3352 StackPtr, PtrOff);
3353 if (Flags.isByVal())
3354 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
3355
3356 return DAG.getStore(
3357 Chain, dl, Arg, PtrOff,
3358 MachinePointerInfo::getStack(DAG.getMachineFunction(), LocMemOffset));
3359}
3360
3361/// Emit a load of return address if tail call
3362/// optimization is performed and it is required.
3363SDValue X86TargetLowering::EmitTailCallLoadRetAddr(
3364 SelectionDAG &DAG, SDValue &OutRetAddr, SDValue Chain, bool IsTailCall,
3365 bool Is64Bit, int FPDiff, const SDLoc &dl) const {
3366 // Adjust the Return address stack slot.
3367 EVT VT = getPointerTy(DAG.getDataLayout());
3368 OutRetAddr = getReturnAddressFrameIndex(DAG);
3369
3370 // Load the "old" Return address.
3371 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo());
3372 return SDValue(OutRetAddr.getNode(), 1);
3373}
3374
3375/// Emit a store of the return address if tail call
3376/// optimization is performed and it is required (FPDiff!=0).
3377static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
3378 SDValue Chain, SDValue RetAddrFrIdx,
3379 EVT PtrVT, unsigned SlotSize,
3380 int FPDiff, const SDLoc &dl) {
3381 // Store the return address to the appropriate stack slot.
3382 if (!FPDiff) return Chain;
3383 // Calculate the new stack slot for the return address.
3384 int NewReturnAddrFI =
3385 MF.getFrameInfo().CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
3386 false);
3387 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
3388 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
3389 MachinePointerInfo::getFixedStack(
3390 DAG.getMachineFunction(), NewReturnAddrFI));
3391 return Chain;
3392}
3393
3394/// Returns a vector_shuffle mask for an movs{s|d}, movd
3395/// operation of specified width.
3396static SDValue getMOVL(SelectionDAG &DAG, const SDLoc &dl, MVT VT, SDValue V1,
3397 SDValue V2) {
3398 unsigned NumElems = VT.getVectorNumElements();
3399 SmallVector<int, 8> Mask;
3400 Mask.push_back(NumElems);
3401 for (unsigned i = 1; i != NumElems; ++i)
3402 Mask.push_back(i);
3403 return DAG.getVectorShuffle(VT, dl, V1, V2, Mask);
3404}
3405
3406SDValue
3407X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
3408 SmallVectorImpl<SDValue> &InVals) const {
3409 SelectionDAG &DAG = CLI.DAG;
3410 SDLoc &dl = CLI.DL;
3411 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
3412 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
3413 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
3414 SDValue Chain = CLI.Chain;
3415 SDValue Callee = CLI.Callee;
3416 CallingConv::ID CallConv = CLI.CallConv;
3417 bool &isTailCall = CLI.IsTailCall;
3418 bool isVarArg = CLI.IsVarArg;
3419
3420 MachineFunction &MF = DAG.getMachineFunction();
3421 bool Is64Bit = Subtarget.is64Bit();
3422 bool IsWin64 = Subtarget.isCallingConvWin64(CallConv);
3423 StructReturnType SR = callIsStructReturn(Outs, Subtarget.isTargetMCU());
3424 bool IsSibcall = false;
3425 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
3426 auto Attr = MF.getFunction().getFnAttribute("disable-tail-calls");
3427 const auto *CI = dyn_cast_or_null<CallInst>(CLI.CS.getInstruction());
3428 const Function *Fn = CI ? CI->getCalledFunction() : nullptr;
3429 bool HasNCSR = (CI && CI->hasFnAttr("no_caller_saved_registers")) ||
3430 (Fn && Fn->hasFnAttribute("no_caller_saved_registers"));
3431 const auto *II = dyn_cast_or_null<InvokeInst>(CLI.CS.getInstruction());
3432 bool HasNoCfCheck =
3433 (CI && CI->doesNoCfCheck()) || (II && II->doesNoCfCheck());
3434 const Module *M = MF.getMMI().getModule();
3435 Metadata *IsCFProtectionSupported = M->getModuleFlag("cf-protection-branch");
3436
3437 if (CallConv == CallingConv::X86_INTR)
3438 report_fatal_error("X86 interrupts may not be called directly");
3439
3440 if (Attr.getValueAsString() == "true")
3441 isTailCall = false;
3442
3443 if (Subtarget.isPICStyleGOT() &&
3444 !MF.getTarget().Options.GuaranteedTailCallOpt) {
3445 // If we are using a GOT, disable tail calls to external symbols with
3446 // default visibility. Tail calling such a symbol requires using a GOT
3447 // relocation, which forces early binding of the symbol. This breaks code
3448 // that require lazy function symbol resolution. Using musttail or
3449 // GuaranteedTailCallOpt will override this.
3450 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
3451 if (!G || (!G->getGlobal()->hasLocalLinkage() &&
3452 G->getGlobal()->hasDefaultVisibility()))
3453 isTailCall = false;
3454 }
3455
3456 bool IsMustTail = CLI.CS && CLI.CS.isMustTailCall();
3457 if (IsMustTail) {
3458 // Force this to be a tail call. The verifier rules are enough to ensure
3459 // that we can lower this successfully without moving the return address
3460 // around.
3461 isTailCall = true;
3462 } else if (isTailCall) {
3463 // Check if it's really possible to do a tail call.
3464 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
3465 isVarArg, SR != NotStructReturn,
3466 MF.getFunction().hasStructRetAttr(), CLI.RetTy,
3467 Outs, OutVals, Ins, DAG);
3468
3469 // Sibcalls are automatically detected tailcalls which do not require
3470 // ABI changes.
3471 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
3472 IsSibcall = true;
3473
3474 if (isTailCall)
3475 ++NumTailCalls;
3476 }
3477
3478 assert(!(isVarArg && canGuaranteeTCO(CallConv)) &&(static_cast <bool> (!(isVarArg && canGuaranteeTCO
(CallConv)) && "Var args not supported with calling convention fastcc, ghc or hipe"
) ? void (0) : __assert_fail ("!(isVarArg && canGuaranteeTCO(CallConv)) && \"Var args not supported with calling convention fastcc, ghc or hipe\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 3479, __extension__ __PRETTY_FUNCTION__))
3479 "Var args not supported with calling convention fastcc, ghc or hipe")(static_cast <bool> (!(isVarArg && canGuaranteeTCO
(CallConv)) && "Var args not supported with calling convention fastcc, ghc or hipe"
) ? void (0) : __assert_fail ("!(isVarArg && canGuaranteeTCO(CallConv)) && \"Var args not supported with calling convention fastcc, ghc or hipe\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 3479, __extension__ __PRETTY_FUNCTION__))
;
3480
3481 // Analyze operands of the call, assigning locations to each operand.
3482 SmallVector<CCValAssign, 16> ArgLocs;
3483 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
3484
3485 // Allocate shadow area for Win64.
3486 if (IsWin64)
3487 CCInfo.AllocateStack(32, 8);
3488
3489 CCInfo.AnalyzeArguments(Outs, CC_X86);
3490
3491 // In vectorcall calling convention a second pass is required for the HVA
3492 // types.
3493 if (CallingConv::X86_VectorCall == CallConv) {
3494 CCInfo.AnalyzeArgumentsSecondPass(Outs, CC_X86);
3495 }
3496
3497 // Get a count of how many bytes are to be pushed on the stack.
3498 unsigned NumBytes = CCInfo.getAlignedCallFrameSize();
3499 if (IsSibcall)
3500 // This is a sibcall. The memory operands are available in caller's
3501 // own caller's stack.
3502 NumBytes = 0;
3503 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
3504 canGuaranteeTCO(CallConv))
3505 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
3506
3507 int FPDiff = 0;
3508 if (isTailCall && !IsSibcall && !IsMustTail) {
3509 // Lower arguments at fp - stackoffset + fpdiff.
3510 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
3511
3512 FPDiff = NumBytesCallerPushed - NumBytes;
3513
3514 // Set the delta of movement of the returnaddr stackslot.
3515 // But only set if delta is greater than previous delta.
3516 if (FPDiff < X86Info->getTCReturnAddrDelta())
3517 X86Info->setTCReturnAddrDelta(FPDiff);
3518 }
3519
3520 unsigned NumBytesToPush = NumBytes;
3521 unsigned NumBytesToPop = NumBytes;
3522
3523 // If we have an inalloca argument, all stack space has already been allocated
3524 // for us and be right at the top of the stack. We don't support multiple
3525 // arguments passed in memory when using inalloca.
3526 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
3527 NumBytesToPush = 0;
3528 if (!ArgLocs.back().isMemLoc())
3529 report_fatal_error("cannot use inalloca attribute on a register "
3530 "parameter");
3531 if (ArgLocs.back().getLocMemOffset() != 0)
3532 report_fatal_error("any parameter with the inalloca attribute must be "
3533 "the only memory argument");
3534 }
3535
3536 if (!IsSibcall)
3537 Chain = DAG.getCALLSEQ_START(Chain, NumBytesToPush,
3538 NumBytes - NumBytesToPush, dl);
3539
3540 SDValue RetAddrFrIdx;
3541 // Load return address for tail calls.
3542 if (isTailCall && FPDiff)
3543 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
3544 Is64Bit, FPDiff, dl);
3545
3546 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
3547 SmallVector<SDValue, 8> MemOpChains;
3548 SDValue StackPtr;
3549
3550 // The next loop assumes that the locations are in the same order of the
3551 // input arguments.
3552 assert(isSortedByValueNo(ArgLocs) &&(static_cast <bool> (isSortedByValueNo(ArgLocs) &&
"Argument Location list must be sorted before lowering") ? void
(0) : __assert_fail ("isSortedByValueNo(ArgLocs) && \"Argument Location list must be sorted before lowering\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 3553, __extension__ __PRETTY_FUNCTION__))
3553 "Argument Location list must be sorted before lowering")(static_cast <bool> (isSortedByValueNo(ArgLocs) &&
"Argument Location list must be sorted before lowering") ? void
(0) : __assert_fail ("isSortedByValueNo(ArgLocs) && \"Argument Location list must be sorted before lowering\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 3553, __extension__ __PRETTY_FUNCTION__))
;
3554
3555 // Walk the register/memloc assignments, inserting copies/loads. In the case
3556 // of tail call optimization arguments are handle later.
3557 const X86RegisterInfo *RegInfo = Subtarget.getRegisterInfo();
3558 for (unsigned I = 0, OutIndex = 0, E = ArgLocs.size(); I != E;
3559 ++I, ++OutIndex) {
3560 assert(OutIndex < Outs.size() && "Invalid Out index")(static_cast <bool> (OutIndex < Outs.size() &&
"Invalid Out index") ? void (0) : __assert_fail ("OutIndex < Outs.size() && \"Invalid Out index\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 3560, __extension__ __PRETTY_FUNCTION__))
;
3561 // Skip inalloca arguments, they have already been written.
3562 ISD::ArgFlagsTy Flags = Outs[OutIndex].Flags;
3563 if (Flags.isInAlloca())
3564 continue;
3565
3566 CCValAssign &VA = ArgLocs[I];
3567 EVT RegVT = VA.getLocVT();
3568 SDValue Arg = OutVals[OutIndex];
3569 bool isByVal = Flags.isByVal();
3570
3571 // Promote the value if needed.
3572 switch (VA.getLocInfo()) {
3573 default: llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 3573)
;
3574 case CCValAssign::Full: break;
3575 case CCValAssign::SExt:
3576 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
3577 break;
3578 case CCValAssign::ZExt:
3579 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
3580 break;
3581 case CCValAssign::AExt:
3582 if (Arg.getValueType().isVector() &&
3583 Arg.getValueType().getVectorElementType() == MVT::i1)
3584 Arg = lowerMasksToReg(Arg, RegVT, dl, DAG);
3585 else if (RegVT.is128BitVector()) {
3586 // Special case: passing MMX values in XMM registers.
3587 Arg = DAG.getBitcast(MVT::i64, Arg);
3588 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
3589 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
3590 } else
3591 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
3592 break;
3593 case CCValAssign::BCvt:
3594 Arg = DAG.getBitcast(RegVT, Arg);
3595 break;
3596 case CCValAssign::Indirect: {
3597 // Store the argument.
3598 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
3599 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
3600 Chain = DAG.getStore(
3601 Chain, dl, Arg, SpillSlot,
3602 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI));
3603 Arg = SpillSlot;
3604 break;
3605 }
3606 }
3607
3608 if (VA.needsCustom()) {
3609 assert(VA.getValVT() == MVT::v64i1 &&(static_cast <bool> (VA.getValVT() == MVT::v64i1 &&
"Currently the only custom case is when we split v64i1 to 2 regs"
) ? void (0) : __assert_fail ("VA.getValVT() == MVT::v64i1 && \"Currently the only custom case is when we split v64i1 to 2 regs\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 3610, __extension__ __PRETTY_FUNCTION__))
3610 "Currently the only custom case is when we split v64i1 to 2 regs")(static_cast <bool> (VA.getValVT() == MVT::v64i1 &&
"Currently the only custom case is when we split v64i1 to 2 regs"
) ? void (0) : __assert_fail ("VA.getValVT() == MVT::v64i1 && \"Currently the only custom case is when we split v64i1 to 2 regs\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 3610, __extension__ __PRETTY_FUNCTION__))
;
3611 // Split v64i1 value into two registers
3612 Passv64i1ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++I],
3613 Subtarget);
3614 } else if (VA.isRegLoc()) {
3615 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
3616 if (isVarArg && IsWin64) {
3617 // Win64 ABI requires argument XMM reg to be copied to the corresponding
3618 // shadow reg if callee is a varargs function.
3619 unsigned ShadowReg = 0;
3620 switch (VA.getLocReg()) {
3621 case X86::XMM0: ShadowReg = X86::RCX; break;
3622 case X86::XMM1: ShadowReg = X86::RDX; break;
3623 case X86::XMM2: ShadowReg = X86::R8; break;
3624 case X86::XMM3: ShadowReg = X86::R9; break;
3625 }
3626 if (ShadowReg)
3627 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
3628 }
3629 } else if (!IsSibcall && (!isTailCall || isByVal)) {
3630 assert(VA.isMemLoc())(static_cast <bool> (VA.isMemLoc()) ? void (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 3630, __extension__ __PRETTY_FUNCTION__))
;
3631 if (!StackPtr.getNode())
3632 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
3633 getPointerTy(DAG.getDataLayout()));
3634 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
3635 dl, DAG, VA, Flags));
3636 }
3637 }
3638
3639 if (!MemOpChains.empty())
3640 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
3641
3642 if (Subtarget.isPICStyleGOT()) {
3643 // ELF / PIC requires GOT in the EBX register before function calls via PLT
3644 // GOT pointer.
3645 if (!isTailCall) {
3646 RegsToPass.push_back(std::make_pair(
3647 unsigned(X86::EBX), DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(),
3648 getPointerTy(DAG.getDataLayout()))));
3649 } else {
3650 // If we are tail calling and generating PIC/GOT style code load the
3651 // address of the callee into ECX. The value in ecx is used as target of
3652 // the tail jump. This is done to circumvent the ebx/callee-saved problem
3653 // for tail calls on PIC/GOT architectures. Normally we would just put the
3654 // address of GOT into ebx and then call target@PLT. But for tail calls
3655 // ebx would be restored (since ebx is callee saved) before jumping to the
3656 // target@PLT.
3657
3658 // Note: The actual moving to ECX is done further down.
3659 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
3660 if (G && !G->getGlobal()->hasLocalLinkage() &&
3661 G->getGlobal()->hasDefaultVisibility())
3662 Callee = LowerGlobalAddress(Callee, DAG);
3663 else if (isa<ExternalSymbolSDNode>(Callee))
3664 Callee = LowerExternalSymbol(Callee, DAG);
3665 }
3666 }
3667
3668 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
3669 // From AMD64 ABI document:
3670 // For calls that may call functions that use varargs or stdargs
3671 // (prototype-less calls or calls to functions containing ellipsis (...) in
3672 // the declaration) %al is used as hidden argument to specify the number
3673 // of SSE registers used. The contents of %al do not need to match exactly
3674 // the number of registers, but must be an ubound on the number of SSE
3675 // registers used and is in the range 0 - 8 inclusive.
3676
3677 // Count the number of XMM registers allocated.
3678 static const MCPhysReg XMMArgRegs[] = {
3679 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
3680 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
3681 };
3682 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs);
3683 assert((Subtarget.hasSSE1() || !NumXMMRegs)(static_cast <bool> ((Subtarget.hasSSE1() || !NumXMMRegs
) && "SSE registers cannot be used when SSE is disabled"
) ? void (0) : __assert_fail ("(Subtarget.hasSSE1() || !NumXMMRegs) && \"SSE registers cannot be used when SSE is disabled\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 3684, __extension__ __PRETTY_FUNCTION__))
3684 && "SSE registers cannot be used when SSE is disabled")(static_cast <bool> ((Subtarget.hasSSE1() || !NumXMMRegs
) && "SSE registers cannot be used when SSE is disabled"
) ? void (0) : __assert_fail ("(Subtarget.hasSSE1() || !NumXMMRegs) && \"SSE registers cannot be used when SSE is disabled\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 3684, __extension__ __PRETTY_FUNCTION__))
;
3685
3686 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
3687 DAG.getConstant(NumXMMRegs, dl,
3688 MVT::i8)));
3689 }
3690
3691 if (isVarArg && IsMustTail) {
3692 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
3693 for (const auto &F : Forwards) {
3694 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
3695 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
3696 }
3697 }
3698
3699 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
3700 // don't need this because the eligibility check rejects calls that require
3701 // shuffling arguments passed in memory.
3702 if (!IsSibcall && isTailCall) {
3703 // Force all the incoming stack arguments to be loaded from the stack
3704 // before any new outgoing arguments are stored to the stack, because the
3705 // outgoing stack slots may alias the incoming argument stack slots, and
3706 // the alias isn't otherwise explicit. This is slightly more conservative
3707 // than necessary, because it means that each store effectively depends
3708 // on every argument instead of just those arguments it would clobber.
3709 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
3710
3711 SmallVector<SDValue, 8> MemOpChains2;
3712 SDValue FIN;
3713 int FI = 0;
3714 for (unsigned I = 0, OutsIndex = 0, E = ArgLocs.size(); I != E;
3715 ++I, ++OutsIndex) {
3716 CCValAssign &VA = ArgLocs[I];
3717
3718 if (VA.isRegLoc()) {
3719 if (VA.needsCustom()) {
3720 assert((CallConv == CallingConv::X86_RegCall) &&(static_cast <bool> ((CallConv == CallingConv::X86_RegCall
) && "Expecting custom case only in regcall calling convention"
) ? void (0) : __assert_fail ("(CallConv == CallingConv::X86_RegCall) && \"Expecting custom case only in regcall calling convention\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 3721, __extension__ __PRETTY_FUNCTION__))
3721 "Expecting custom case only in regcall calling convention")(static_cast <bool> ((CallConv == CallingConv::X86_RegCall
) && "Expecting custom case only in regcall calling convention"
) ? void (0) : __assert_fail ("(CallConv == CallingConv::X86_RegCall) && \"Expecting custom case only in regcall calling convention\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 3721, __extension__ __PRETTY_FUNCTION__))
;
3722 // This means that we are in special case where one argument was
3723 // passed through two register locations - Skip the next location
3724 ++I;
3725 }
3726
3727 continue;
3728 }
3729
3730 assert(VA.isMemLoc())(static_cast <bool> (VA.isMemLoc()) ? void (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 3730, __extension__ __PRETTY_FUNCTION__))
;
3731 SDValue Arg = OutVals[OutsIndex];
3732 ISD::ArgFlagsTy Flags = Outs[OutsIndex].Flags;
3733 // Skip inalloca arguments. They don't require any work.
3734 if (Flags.isInAlloca())
3735 continue;
3736 // Create frame index.
3737 int32_t Offset = VA.getLocMemOffset()+FPDiff;
3738 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
3739 FI = MF.getFrameInfo().CreateFixedObject(OpSize, Offset, true);
3740 FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
3741
3742 if (Flags.isByVal()) {
3743 // Copy relative to framepointer.
3744 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset(), dl);
3745 if (!StackPtr.getNode())
3746 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
3747 getPointerTy(DAG.getDataLayout()));
3748 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
3749 StackPtr, Source);
3750
3751 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3752 ArgChain,
3753 Flags, DAG, dl));
3754 } else {
3755 // Store relative to framepointer.
3756 MemOpChains2.push_back(DAG.getStore(
3757 ArgChain, dl, Arg, FIN,
3758 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI)));
3759 }
3760 }
3761
3762 if (!MemOpChains2.empty())
3763 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3764
3765 // Store the return address to the appropriate stack slot.
3766 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3767 getPointerTy(DAG.getDataLayout()),
3768 RegInfo->getSlotSize(), FPDiff, dl);
3769 }
3770
3771 // Build a sequence of copy-to-reg nodes chained together with token chain
3772 // and flag operands which copy the outgoing args into registers.
3773 SDValue InFlag;
3774 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3775 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3776 RegsToPass[i].second, InFlag);
3777 InFlag = Chain.getValue(1);
3778 }
3779
3780 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3781 assert(Is64Bit && "Large code model is only legal in 64-bit mode.")(static_cast <bool> (Is64Bit && "Large code model is only legal in 64-bit mode."
) ? void (0) : __assert_fail ("Is64Bit && \"Large code model is only legal in 64-bit mode.\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 3781, __extension__ __PRETTY_FUNCTION__))
;
3782 // In the 64-bit large code model, we have to make all calls
3783 // through a register, since the call instruction's 32-bit
3784 // pc-relative offset may not be large enough to hold the whole
3785 // address.
3786 } else if (Callee->getOpcode() == ISD::GlobalAddress) {
3787 // If the callee is a GlobalAddress node (quite common, every direct call
3788 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3789 // it.
3790 GlobalAddressSDNode* G = cast<GlobalAddressSDNode>(Callee);
3791
3792 // We should use extra load for direct calls to dllimported functions in
3793 // non-JIT mode.
3794 const GlobalValue *GV = G->getGlobal();
3795 if (!GV->hasDLLImportStorageClass()) {
3796 unsigned char OpFlags = Subtarget.classifyGlobalFunctionReference(GV);
3797
3798 Callee = DAG.getTargetGlobalAddress(
3799 GV, dl, getPointerTy(DAG.getDataLayout()), G->getOffset(), OpFlags);
3800
3801 if (OpFlags == X86II::MO_GOTPCREL) {
3802 // Add a wrapper.
3803 Callee = DAG.getNode(X86ISD::WrapperRIP, dl,
3804 getPointerTy(DAG.getDataLayout()), Callee);
3805 // Add extra indirection
3806 Callee = DAG.getLoad(
3807 getPointerTy(DAG.getDataLayout()), dl, DAG.getEntryNode(), Callee,
3808 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
3809 }
3810 }
3811 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3812 const Module *Mod = DAG.getMachineFunction().getFunction().getParent();
3813 unsigned char OpFlags =
3814 Subtarget.classifyGlobalFunctionReference(nullptr, *Mod);
3815
3816 Callee = DAG.getTargetExternalSymbol(
3817 S->getSymbol(), getPointerTy(DAG.getDataLayout()), OpFlags);
3818
3819 if (OpFlags == X86II::MO_GOTPCREL) {
3820 Callee = DAG.getNode(X86ISD::WrapperRIP, dl,
3821 getPointerTy(DAG.getDataLayout()), Callee);
3822 Callee = DAG.getLoad(
3823 getPointerTy(DAG.getDataLayout()), dl, DAG.getEntryNode(), Callee,
3824 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
3825 }
3826 } else if (Subtarget.isTarget64BitILP32() &&
3827 Callee->getValueType(0) == MVT::i32) {
3828 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3829 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3830 }
3831
3832 // Returns a chain & a flag for retval copy to use.
3833 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3834 SmallVector<SDValue, 8> Ops;
3835
3836 if (!IsSibcall && isTailCall) {
3837 Chain = DAG.getCALLSEQ_END(Chain,
3838 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
3839 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
3840 InFlag = Chain.getValue(1);
3841 }
3842
3843 Ops.push_back(Chain);
3844 Ops.push_back(Callee);
3845
3846 if (isTailCall)
3847 Ops.push_back(DAG.getConstant(FPDiff, dl, MVT::i32));
3848
3849 // Add argument registers to the end of the list so that they are known live
3850 // into the call.
3851 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3852 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3853 RegsToPass[i].second.getValueType()));
3854
3855 // Add a register mask operand representing the call-preserved registers.
3856 // If HasNCSR is asserted (attribute NoCallerSavedRegisters exists) then we
3857 // set X86_INTR calling convention because it has the same CSR mask
3858 // (same preserved registers).
3859 const uint32_t *Mask = RegInfo->getCallPreservedMask(
3860 MF, HasNCSR ? (CallingConv::ID)CallingConv::X86_INTR : CallConv);
3861 assert(Mask && "Missing call preserved mask for calling convention")(static_cast <bool> (Mask && "Missing call preserved mask for calling convention"
) ? void (0) : __assert_fail ("Mask && \"Missing call preserved mask for calling convention\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 3861, __extension__ __PRETTY_FUNCTION__))
;
3862
3863 // If this is an invoke in a 32-bit function using a funclet-based
3864 // personality, assume the function clobbers all registers. If an exception
3865 // is thrown, the runtime will not restore CSRs.
3866 // FIXME: Model this more precisely so that we can register allocate across
3867 // the normal edge and spill and fill across the exceptional edge.
3868 if (!Is64Bit && CLI.CS && CLI.CS.isInvoke()) {
3869 const Function &CallerFn = MF.getFunction();
3870 EHPersonality Pers =
3871 CallerFn.hasPersonalityFn()
3872 ? classifyEHPersonality(CallerFn.getPersonalityFn())
3873 : EHPersonality::Unknown;
3874 if (isFuncletEHPersonality(Pers))
3875 Mask = RegInfo->getNoPreservedMask();
3876 }
3877
3878 // Define a new register mask from the existing mask.
3879 uint32_t *RegMask = nullptr;
3880
3881 // In some calling conventions we need to remove the used physical registers
3882 // from the reg mask.
3883 if (CallConv == CallingConv::X86_RegCall || HasNCSR) {
3884 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
3885
3886 // Allocate a new Reg Mask and copy Mask.
3887 RegMask = MF.allocateRegisterMask(TRI->getNumRegs());
3888 unsigned RegMaskSize = (TRI->getNumRegs() + 31) / 32;
3889 memcpy(RegMask, Mask, sizeof(uint32_t) * RegMaskSize);
3890
3891 // Make sure all sub registers of the argument registers are reset
3892 // in the RegMask.
3893 for (auto const &RegPair : RegsToPass)
3894 for (MCSubRegIterator SubRegs(RegPair.first, TRI, /*IncludeSelf=*/true);
3895 SubRegs.isValid(); ++SubRegs)
3896 RegMask[*SubRegs / 32] &= ~(1u << (*SubRegs % 32));
3897
3898 // Create the RegMask Operand according to our updated mask.
3899 Ops.push_back(DAG.getRegisterMask(RegMask));
3900 } else {
3901 // Create the RegMask Operand according to the static mask.
3902 Ops.push_back(DAG.getRegisterMask(Mask));
3903 }
3904
3905 if (InFlag.getNode())
3906 Ops.push_back(InFlag);
3907
3908 if (isTailCall) {
3909 // We used to do:
3910 //// If this is the first return lowered for this function, add the regs
3911 //// to the liveout set for the function.
3912 // This isn't right, although it's probably harmless on x86; liveouts
3913 // should be computed from returns not tail calls. Consider a void
3914 // function making a tail call to a function returning int.
3915 MF.getFrameInfo().setHasTailCall();
3916 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3917 }
3918
3919 if (HasNoCfCheck && IsCFProtectionSupported) {
3920 Chain = DAG.getNode(X86ISD::NT_CALL, dl, NodeTys, Ops);
3921 } else {
3922 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3923 }
3924 InFlag = Chain.getValue(1);
3925
3926 // Create the CALLSEQ_END node.
3927 unsigned NumBytesForCalleeToPop;
3928 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3929 DAG.getTarget().Options.GuaranteedTailCallOpt))
3930 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3931 else if (!Is64Bit && !canGuaranteeTCO(CallConv) &&
3932 !Subtarget.getTargetTriple().isOSMSVCRT() &&
3933 SR == StackStructReturn)
3934 // If this is a call to a struct-return function, the callee
3935 // pops the hidden struct pointer, so we have to push it back.
3936 // This is common for Darwin/X86, Linux & Mingw32 targets.
3937 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3938 NumBytesForCalleeToPop = 4;
3939 else
3940 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3941
3942 if (CLI.DoesNotReturn && !getTargetMachine().Options.TrapUnreachable) {
3943 // No need to reset the stack after the call if the call doesn't return. To
3944 // make the MI verify, we'll pretend the callee does it for us.
3945 NumBytesForCalleeToPop = NumBytes;
3946 }
3947
3948 // Returns a flag for retval copy to use.
3949 if (!IsSibcall) {
3950 Chain = DAG.getCALLSEQ_END(Chain,
3951 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
3952 DAG.getIntPtrConstant(NumBytesForCalleeToPop, dl,
3953 true),
3954 InFlag, dl);
3955 InFlag = Chain.getValue(1);
3956 }
3957
3958 // Handle result values, copying them out of physregs into vregs that we
3959 // return.
3960 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl, DAG,
3961 InVals, RegMask);
3962}
3963
3964//===----------------------------------------------------------------------===//
3965// Fast Calling Convention (tail call) implementation
3966//===----------------------------------------------------------------------===//
3967
3968// Like std call, callee cleans arguments, convention except that ECX is
3969// reserved for storing the tail called function address. Only 2 registers are
3970// free for argument passing (inreg). Tail call optimization is performed
3971// provided:
3972// * tailcallopt is enabled
3973// * caller/callee are fastcc
3974// On X86_64 architecture with GOT-style position independent code only local
3975// (within module) calls are supported at the moment.
3976// To keep the stack aligned according to platform abi the function
3977// GetAlignedArgumentStackSize ensures that argument delta is always multiples
3978// of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3979// If a tail called function callee has more arguments than the caller the
3980// caller needs to make sure that there is room to move the RETADDR to. This is
3981// achieved by reserving an area the size of the argument delta right after the
3982// original RETADDR, but before the saved framepointer or the spilled registers
3983// e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3984// stack layout:
3985// arg1
3986// arg2
3987// RETADDR
3988// [ new RETADDR
3989// move area ]
3990// (possible EBP)
3991// ESI
3992// EDI
3993// local1 ..
3994
3995/// Make the stack size align e.g 16n + 12 aligned for a 16-byte align
3996/// requirement.
3997unsigned
3998X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3999 SelectionDAG& DAG) const {
4000 const X86RegisterInfo *RegInfo = Subtarget.getRegisterInfo();
4001 const TargetFrameLowering &TFI = *Subtarget.getFrameLowering();
4002 unsigned StackAlignment = TFI.getStackAlignment();
4003 uint64_t AlignMask = StackAlignment - 1;
4004 int64_t Offset = StackSize;
4005 unsigned SlotSize = RegInfo->getSlotSize();
4006 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
4007 // Number smaller than 12 so just add the difference.
4008 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
4009 } else {
4010 // Mask out lower bits, add stackalignment once plus the 12 bytes.
4011 Offset = ((~AlignMask) & Offset) + StackAlignment +
4012 (StackAlignment-SlotSize);
4013 }
4014 return Offset;
4015}
4016
4017/// Return true if the given stack call argument is already available in the
4018/// same position (relatively) of the caller's incoming argument stack.
4019static
4020bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
4021 MachineFrameInfo &MFI, const MachineRegisterInfo *MRI,
4022 const X86InstrInfo *TII, const CCValAssign &VA) {
4023 unsigned Bytes = Arg.getValueSizeInBits() / 8;
4024
4025 for (;;) {
4026 // Look through nodes that don't alter the bits of the incoming value.
4027 unsigned Op = Arg.getOpcode();
4028 if (Op == ISD::ZERO_EXTEND || Op == ISD::ANY_EXTEND || Op == ISD::BITCAST) {
4029 Arg = Arg.getOperand(0);
4030 continue;
4031 }
4032 if (Op == ISD::TRUNCATE) {
4033 const SDValue &TruncInput = Arg.getOperand(0);
4034 if (TruncInput.getOpcode() == ISD::AssertZext &&
4035 cast<VTSDNode>(TruncInput.getOperand(1))->getVT() ==
4036 Arg.getValueType()) {
4037 Arg = TruncInput.getOperand(0);
4038 continue;
4039 }
4040 }
4041 break;
4042 }
4043
4044 int FI = INT_MAX2147483647;
4045 if (Arg.getOpcode() == ISD::CopyFromReg) {
4046 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
4047 if (!TargetRegisterInfo::isVirtualRegister(VR))
4048 return false;
4049 MachineInstr *Def = MRI->getVRegDef(VR);
4050 if (!Def)
4051 return false;
4052 if (!Flags.isByVal()) {
4053 if (!TII->isLoadFromStackSlot(*Def, FI))
4054 return false;
4055 } else {
4056 unsigned Opcode = Def->getOpcode();
4057 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r ||
4058 Opcode == X86::LEA64_32r) &&
4059 Def->getOperand(1).isFI()) {
4060 FI = Def->getOperand(1).getIndex();
4061 Bytes = Flags.getByValSize();
4062 } else
4063 return false;
4064 }
4065 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
4066 if (Flags.isByVal())
4067 // ByVal argument is passed in as a pointer but it's now being
4068 // dereferenced. e.g.
4069 // define @foo(%struct.X* %A) {
4070 // tail call @bar(%struct.X* byval %A)
4071 // }
4072 return false;
4073 SDValue Ptr = Ld->getBasePtr();
4074 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
4075 if (!FINode)
4076 return false;
4077 FI = FINode->getIndex();
4078 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
4079 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
4080 FI = FINode->getIndex();
4081 Bytes = Flags.getByValSize();
4082 } else
4083 return false;
4084
4085 assert(FI != INT_MAX)(static_cast <bool> (FI != 2147483647) ? void (0) : __assert_fail
("FI != INT_MAX", "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 4085, __extension__ __PRETTY_FUNCTION__))
;
4086 if (!MFI.isFixedObjectIndex(FI))
4087 return false;
4088
4089 if (Offset != MFI.getObjectOffset(FI))
4090 return false;
4091
4092 // If this is not byval, check that the argument stack object is immutable.
4093 // inalloca and argument copy elision can create mutable argument stack
4094 // objects. Byval objects can be mutated, but a byval call intends to pass the
4095 // mutated memory.
4096 if (!Flags.isByVal() && !MFI.isImmutableObjectIndex(FI))
4097 return false;
4098
4099 if (VA.getLocVT().getSizeInBits() > Arg.getValueSizeInBits()) {
4100 // If the argument location is wider than the argument type, check that any
4101 // extension flags match.
4102 if (Flags.isZExt() != MFI.isObjectZExt(FI) ||
4103 Flags.isSExt() != MFI.isObjectSExt(FI)) {
4104 return false;
4105 }
4106 }
4107
4108 return Bytes == MFI.getObjectSize(FI);
4109}
4110
4111/// Check whether the call is eligible for tail call optimization. Targets
4112/// that want to do tail call optimization should implement this function.
4113bool X86TargetLowering::IsEligibleForTailCallOptimization(
4114 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
4115 bool isCalleeStructRet, bool isCallerStructRet, Type *RetTy,
4116 const SmallVectorImpl<ISD::OutputArg> &Outs,
4117 const SmallVectorImpl<SDValue> &OutVals,
4118 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const {
4119 if (!mayTailCallThisCC(CalleeCC))
4120 return false;
4121
4122 // If -tailcallopt is specified, make fastcc functions tail-callable.
4123 MachineFunction &MF = DAG.getMachineFunction();
4124 const Function &CallerF = MF.getFunction();
4125
4126 // If the function return type is x86_fp80 and the callee return type is not,
4127 // then the FP_EXTEND of the call result is not a nop. It's not safe to
4128 // perform a tailcall optimization here.
4129 if (CallerF.getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
4130 return false;
4131
4132 CallingConv::ID CallerCC = CallerF.getCallingConv();
4133 bool CCMatch = CallerCC == CalleeCC;
4134 bool IsCalleeWin64 = Subtarget.isCallingConvWin64(CalleeCC);
4135 bool IsCallerWin64 = Subtarget.isCallingConvWin64(CallerCC);
4136
4137 // Win64 functions have extra shadow space for argument homing. Don't do the
4138 // sibcall if the caller and callee have mismatched expectations for this
4139 // space.
4140 if (IsCalleeWin64 != IsCallerWin64)
4141 return false;
4142
4143 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
4144 if (canGuaranteeTCO(CalleeCC) && CCMatch)
4145 return true;
4146 return false;
4147 }
4148
4149 // Look for obvious safe cases to perform tail call optimization that do not
4150 // require ABI changes. This is what gcc calls sibcall.
4151
4152 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
4153 // emit a special epilogue.
4154 const X86RegisterInfo *RegInfo = Subtarget.getRegisterInfo();
4155 if (RegInfo->needsStackRealignment(MF))
4156 return false;
4157
4158 // Also avoid sibcall optimization if either caller or callee uses struct
4159 // return semantics.
4160 if (isCalleeStructRet || isCallerStructRet)
4161 return false;
4162
4163 // Do not sibcall optimize vararg calls unless all arguments are passed via
4164 // registers.
4165 LLVMContext &C = *DAG.getContext();
4166 if (isVarArg && !Outs.empty()) {
4167 // Optimizing for varargs on Win64 is unlikely to be safe without
4168 // additional testing.
4169 if (IsCalleeWin64 || IsCallerWin64)
4170 return false;
4171
4172 SmallVector<CCValAssign, 16> ArgLocs;
4173 CCState CCInfo(CalleeCC, isVarArg, MF, ArgLocs, C);
4174
4175 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
4176 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
4177 if (!ArgLocs[i].isRegLoc())
4178 return false;
4179 }
4180
4181 // If the call result is in ST0 / ST1, it needs to be popped off the x87
4182 // stack. Therefore, if it's not used by the call it is not safe to optimize
4183 // this into a sibcall.
4184 bool Unused = false;
4185 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
4186 if (!Ins[i].Used) {
4187 Unused = true;
4188 break;
4189 }
4190 }
4191 if (Unused) {
4192 SmallVector<CCValAssign, 16> RVLocs;
4193 CCState CCInfo(CalleeCC, false, MF, RVLocs, C);
4194 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
4195 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
4196 CCValAssign &VA = RVLocs[i];
4197 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
4198 return false;
4199 }
4200 }
4201
4202 // Check that the call results are passed in the same way.
4203 if (!CCState::resultsCompatible(CalleeCC, CallerCC, MF, C, Ins,
4204 RetCC_X86, RetCC_X86))
4205 return false;
4206 // The callee has to preserve all registers the caller needs to preserve.
4207 const X86RegisterInfo *TRI = Subtarget.getRegisterInfo();
4208 const uint32_t *CallerPreserved = TRI->getCallPreservedMask(MF, CallerCC);
4209 if (!CCMatch) {
4210 const uint32_t *CalleePreserved = TRI->getCallPreservedMask(MF, CalleeCC);
4211 if (!TRI->regmaskSubsetEqual(CallerPreserved, CalleePreserved))
4212 return false;
4213 }
4214
4215 unsigned StackArgsSize = 0;
4216
4217 // If the callee takes no arguments then go on to check the results of the
4218 // call.
4219 if (!Outs.empty()) {
4220 // Check if stack adjustment is needed. For now, do not do this if any
4221 // argument is passed on the stack.
4222 SmallVector<CCValAssign, 16> ArgLocs;
4223 CCState CCInfo(CalleeCC, isVarArg, MF, ArgLocs, C);
4224
4225 // Allocate shadow area for Win64
4226 if (IsCalleeWin64)
4227 CCInfo.AllocateStack(32, 8);
4228
4229 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
4230 StackArgsSize = CCInfo.getNextStackOffset();
4231
4232 if (CCInfo.getNextStackOffset()) {
4233 // Check if the arguments are already laid out in the right way as
4234 // the caller's fixed stack objects.
4235 MachineFrameInfo &MFI = MF.getFrameInfo();
4236 const MachineRegisterInfo *MRI = &MF.getRegInfo();
4237 const X86InstrInfo *TII = Subtarget.getInstrInfo();
4238 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
4239 CCValAssign &VA = ArgLocs[i];
4240 SDValue Arg = OutVals[i];
4241 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4242 if (VA.getLocInfo() == CCValAssign::Indirect)
4243 return false;
4244 if (!VA.isRegLoc()) {
4245 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
4246 MFI, MRI, TII, VA))
4247 return false;
4248 }
4249 }
4250 }
4251
4252 bool PositionIndependent = isPositionIndependent();
4253 // If the tailcall address may be in a register, then make sure it's
4254 // possible to register allocate for it. In 32-bit, the call address can
4255 // only target EAX, EDX, or ECX since the tail call must be scheduled after
4256 // callee-saved registers are restored. These happen to be the same
4257 // registers used to pass 'inreg' arguments so watch out for those.
4258 if (!Subtarget.is64Bit() && ((!isa<GlobalAddressSDNode>(Callee) &&
4259 !isa<ExternalSymbolSDNode>(Callee)) ||
4260 PositionIndependent)) {
4261 unsigned NumInRegs = 0;
4262 // In PIC we need an extra register to formulate the address computation
4263 // for the callee.
4264 unsigned MaxInRegs = PositionIndependent ? 2 : 3;
4265
4266 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
4267 CCValAssign &VA = ArgLocs[i];
4268 if (!VA.isRegLoc())
4269 continue;
4270 unsigned Reg = VA.getLocReg();
4271 switch (Reg) {
4272 default: break;
4273 case X86::EAX: case X86::EDX: case X86::ECX:
4274 if (++NumInRegs == MaxInRegs)
4275 return false;
4276 break;
4277 }
4278 }
4279 }
4280
4281 const MachineRegisterInfo &MRI = MF.getRegInfo();
4282 if (!parametersInCSRMatch(MRI, CallerPreserved, ArgLocs, OutVals))
4283 return false;
4284 }
4285
4286 bool CalleeWillPop =
4287 X86::isCalleePop(CalleeCC, Subtarget.is64Bit(), isVarArg,
4288 MF.getTarget().Options.GuaranteedTailCallOpt);
4289
4290 if (unsigned BytesToPop =
4291 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn()) {
4292 // If we have bytes to pop, the callee must pop them.
4293 bool CalleePopMatches = CalleeWillPop && BytesToPop == StackArgsSize;
4294 if (!CalleePopMatches)
4295 return false;
4296 } else if (CalleeWillPop && StackArgsSize > 0) {
4297 // If we don't have bytes to pop, make sure the callee doesn't pop any.
4298 return false;
4299 }
4300
4301 return true;
4302}
4303
4304FastISel *
4305X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
4306 const TargetLibraryInfo *libInfo) const {
4307 return X86::createFastISel(funcInfo, libInfo);
4308}
4309
4310//===----------------------------------------------------------------------===//
4311// Other Lowering Hooks
4312//===----------------------------------------------------------------------===//
4313
4314static bool MayFoldLoad(SDValue Op) {
4315 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
4316}
4317
4318static bool MayFoldIntoStore(SDValue Op) {
4319 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
4320}
4321
4322static bool MayFoldIntoZeroExtend(SDValue Op) {
4323 if (Op.hasOneUse()) {
4324 unsigned Opcode = Op.getNode()->use_begin()->getOpcode();
4325 return (ISD::ZERO_EXTEND == Opcode);
4326 }
4327 return false;
4328}
4329
4330static bool isTargetShuffle(unsigned Opcode) {
4331 switch(Opcode) {
4332 default: return false;
4333 case X86ISD::BLENDI:
4334 case X86ISD::PSHUFB:
4335 case X86ISD::PSHUFD:
4336 case X86ISD::PSHUFHW:
4337 case X86ISD::PSHUFLW:
4338 case X86ISD::SHUFP:
4339 case X86ISD::INSERTPS:
4340 case X86ISD::EXTRQI:
4341 case X86ISD::INSERTQI:
4342 case X86ISD::PALIGNR:
4343 case X86ISD::VSHLDQ:
4344 case X86ISD::VSRLDQ:
4345 case X86ISD::MOVLHPS:
4346 case X86ISD::MOVHLPS:
4347 case X86ISD::MOVLPS:
4348 case X86ISD::MOVLPD:
4349 case X86ISD::MOVSHDUP:
4350 case X86ISD::MOVSLDUP:
4351 case X86ISD::MOVDDUP:
4352 case X86ISD::MOVSS:
4353 case X86ISD::MOVSD:
4354 case X86ISD::UNPCKL:
4355 case X86ISD::UNPCKH:
4356 case X86ISD::VBROADCAST:
4357 case X86ISD::VPERMILPI:
4358 case X86ISD::VPERMILPV:
4359 case X86ISD::VPERM2X128:
4360 case X86ISD::VPERMIL2:
4361 case X86ISD::VPERMI:
4362 case X86ISD::VPPERM:
4363 case X86ISD::VPERMV:
4364 case X86ISD::VPERMV3:
4365 case X86ISD::VPERMIV3:
4366 case X86ISD::VZEXT_MOVL:
4367 return true;
4368 }
4369}
4370
4371static bool isTargetShuffleVariableMask(unsigned Opcode) {
4372 switch (Opcode) {
4373 default: return false;
4374 // Target Shuffles.
4375 case X86ISD::PSHUFB:
4376 case X86ISD::VPERMILPV:
4377 case X86ISD::VPERMIL2:
4378 case X86ISD::VPPERM:
4379 case X86ISD::VPERMV:
4380 case X86ISD::VPERMV3:
4381 case X86ISD::VPERMIV3:
4382 return true;
4383 // 'Faux' Target Shuffles.
4384 case ISD::AND:
4385 case X86ISD::ANDNP:
4386 return true;
4387 }
4388}
4389
4390SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
4391 MachineFunction &MF = DAG.getMachineFunction();
4392 const X86RegisterInfo *RegInfo = Subtarget.getRegisterInfo();
4393 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
4394 int ReturnAddrIndex = FuncInfo->getRAIndex();
4395
4396 if (ReturnAddrIndex == 0) {
4397 // Set up a frame object for the return address.
4398 unsigned SlotSize = RegInfo->getSlotSize();
4399 ReturnAddrIndex = MF.getFrameInfo().CreateFixedObject(SlotSize,
4400 -(int64_t)SlotSize,
4401 false);
4402 FuncInfo->setRAIndex(ReturnAddrIndex);
4403 }
4404
4405 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy(DAG.getDataLayout()));
4406}
4407
4408bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
4409 bool hasSymbolicDisplacement) {
4410 // Offset should fit into 32 bit immediate field.
4411 if (!isInt<32>(Offset))
4412 return false;
4413
4414 // If we don't have a symbolic displacement - we don't have any extra
4415 // restrictions.
4416 if (!hasSymbolicDisplacement)
4417 return true;
4418
4419 // FIXME: Some tweaks might be needed for medium code model.
4420 if (M != CodeModel::Small && M != CodeModel::Kernel)
4421 return false;
4422
4423 // For small code model we assume that latest object is 16MB before end of 31
4424 // bits boundary. We may also accept pretty large negative constants knowing
4425 // that all objects are in the positive half of address space.
4426 if (M == CodeModel::Small && Offset < 16*1024*1024)
4427 return true;
4428
4429 // For kernel code model we know that all object resist in the negative half
4430 // of 32bits address space. We may not accept negative offsets, since they may
4431 // be just off and we may accept pretty large positive ones.
4432 if (M == CodeModel::Kernel && Offset >= 0)
4433 return true;
4434
4435 return false;
4436}
4437
4438/// Determines whether the callee is required to pop its own arguments.
4439/// Callee pop is necessary to support tail calls.
4440bool X86::isCalleePop(CallingConv::ID CallingConv,
4441 bool is64Bit, bool IsVarArg, bool GuaranteeTCO) {
4442 // If GuaranteeTCO is true, we force some calls to be callee pop so that we
4443 // can guarantee TCO.
4444 if (!IsVarArg && shouldGuaranteeTCO(CallingConv, GuaranteeTCO))
4445 return true;
4446
4447 switch (CallingConv) {
4448 default:
4449 return false;
4450 case CallingConv::X86_StdCall:
4451 case CallingConv::X86_FastCall:
4452 case CallingConv::X86_ThisCall:
4453 case CallingConv::X86_VectorCall:
4454 return !is64Bit;
4455 }
4456}
4457
4458/// \brief Return true if the condition is an unsigned comparison operation.
4459static bool isX86CCUnsigned(unsigned X86CC) {
4460 switch (X86CC) {
4461 default:
4462 llvm_unreachable("Invalid integer condition!")::llvm::llvm_unreachable_internal("Invalid integer condition!"
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 4462)
;
4463 case X86::COND_E:
4464 case X86::COND_NE:
4465 case X86::COND_B:
4466 case X86::COND_A:
4467 case X86::COND_BE:
4468 case X86::COND_AE:
4469 return true;
4470 case X86::COND_G:
4471 case X86::COND_GE:
4472 case X86::COND_L:
4473 case X86::COND_LE:
4474 return false;
4475 }
4476}
4477
4478static X86::CondCode TranslateIntegerX86CC(ISD::CondCode SetCCOpcode) {
4479 switch (SetCCOpcode) {
4480 default: llvm_unreachable("Invalid integer condition!")::llvm::llvm_unreachable_internal("Invalid integer condition!"
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 4480)
;
4481 case ISD::SETEQ: return X86::COND_E;
4482 case ISD::SETGT: return X86::COND_G;
4483 case ISD::SETGE: return X86::COND_GE;
4484 case ISD::SETLT: return X86::COND_L;
4485 case ISD::SETLE: return X86::COND_LE;
4486 case ISD::SETNE: return X86::COND_NE;
4487 case ISD::SETULT: return X86::COND_B;
4488 case ISD::SETUGT: return X86::COND_A;
4489 case ISD::SETULE: return X86::COND_BE;
4490 case ISD::SETUGE: return X86::COND_AE;
4491 }
4492}
4493
4494/// Do a one-to-one translation of a ISD::CondCode to the X86-specific
4495/// condition code, returning the condition code and the LHS/RHS of the
4496/// comparison to make.
4497static X86::CondCode TranslateX86CC(ISD::CondCode SetCCOpcode, const SDLoc &DL,
4498 bool isFP, SDValue &LHS, SDValue &RHS,
4499 SelectionDAG &DAG) {
4500 if (!isFP) {
4501 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
4502 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
4503 // X > -1 -> X == 0, jump !sign.
4504 RHS = DAG.getConstant(0, DL, RHS.getValueType());
4505 return X86::COND_NS;
4506 }
4507 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
4508 // X < 0 -> X == 0, jump on sign.
4509 return X86::COND_S;
4510 }
4511 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
4512 // X < 1 -> X <= 0
4513 RHS = DAG.getConstant(0, DL, RHS.getValueType());
4514 return X86::COND_LE;
4515 }
4516 }
4517
4518 return TranslateIntegerX86CC(SetCCOpcode);
4519 }
4520
4521 // First determine if it is required or is profitable to flip the operands.
4522
4523 // If LHS is a foldable load, but RHS is not, flip the condition.
4524 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
4525 !ISD::isNON_EXTLoad(RHS.getNode())) {
4526 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
4527 std::swap(LHS, RHS);
4528 }
4529
4530 switch (SetCCOpcode) {
4531 default: break;
4532 case ISD::SETOLT:
4533 case ISD::SETOLE:
4534 case ISD::SETUGT:
4535 case ISD::SETUGE:
4536 std::swap(LHS, RHS);
4537 break;
4538 }
4539
4540 // On a floating point condition, the flags are set as follows:
4541 // ZF PF CF op
4542 // 0 | 0 | 0 | X > Y
4543 // 0 | 0 | 1 | X < Y
4544 // 1 | 0 | 0 | X == Y
4545 // 1 | 1 | 1 | unordered
4546 switch (SetCCOpcode) {
4547 default: llvm_unreachable("Condcode should be pre-legalized away")::llvm::llvm_unreachable_internal("Condcode should be pre-legalized away"
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 4547)
;
4548 case ISD::SETUEQ:
4549 case ISD::SETEQ: return X86::COND_E;
4550 case ISD::SETOLT: // flipped
4551 case ISD::SETOGT:
4552 case ISD::SETGT: return X86::COND_A;
4553 case ISD::SETOLE: // flipped
4554 case ISD::SETOGE:
4555 case ISD::SETGE: return X86::COND_AE;
4556 case ISD::SETUGT: // flipped
4557 case ISD::SETULT:
4558 case ISD::SETLT: return X86::COND_B;
4559 case ISD::SETUGE: // flipped
4560 case ISD::SETULE:
4561 case ISD::SETLE: return X86::COND_BE;
4562 case ISD::SETONE:
4563 case ISD::SETNE: return X86::COND_NE;
4564 case ISD::SETUO: return X86::COND_P;
4565 case ISD::SETO: return X86::COND_NP;
4566 case ISD::SETOEQ:
4567 case ISD::SETUNE: return X86::COND_INVALID;
4568 }
4569}
4570
4571/// Is there a floating point cmov for the specific X86 condition code?
4572/// Current x86 isa includes the following FP cmov instructions:
4573/// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
4574static bool hasFPCMov(unsigned X86CC) {
4575 switch (X86CC) {
4576 default:
4577 return false;
4578 case X86::COND_B:
4579 case X86::COND_BE:
4580 case X86::COND_E:
4581 case X86::COND_P:
4582 case X86::COND_A:
4583 case X86::COND_AE:
4584 case X86::COND_NE:
4585 case X86::COND_NP:
4586 return true;
4587 }
4588}
4589
4590
4591bool X86TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
4592 const CallInst &I,
4593 MachineFunction &MF,
4594 unsigned Intrinsic) const {
4595
4596 const IntrinsicData* IntrData = getIntrinsicWithChain(Intrinsic);
4597 if (!IntrData)
4598 return false;
4599
4600 Info.opc = ISD::INTRINSIC_W_CHAIN;
4601 Info.flags = MachineMemOperand::MONone;
4602 Info.offset = 0;
4603
4604 switch (IntrData->Type) {
4605 case EXPAND_FROM_MEM: {
4606 Info.ptrVal = I.getArgOperand(0);
4607 Info.memVT = MVT::getVT(I.getType());
4608 Info.align = 1;
4609 Info.flags |= MachineMemOperand::MOLoad;
4610 break;
4611 }
4612 case COMPRESS_TO_MEM: {
4613 Info.ptrVal = I.getArgOperand(0);
4614 Info.memVT = MVT::getVT(I.getArgOperand(1)->getType());
4615 Info.align = 1;
4616 Info.flags |= MachineMemOperand::MOStore;
4617 break;
4618 }
4619 case TRUNCATE_TO_MEM_VI8:
4620 case TRUNCATE_TO_MEM_VI16:
4621 case TRUNCATE_TO_MEM_VI32: {
4622 Info.ptrVal = I.getArgOperand(0);
4623 MVT VT = MVT::getVT(I.getArgOperand(1)->getType());
4624 MVT ScalarVT = MVT::INVALID_SIMPLE_VALUE_TYPE;
4625 if (IntrData->Type == TRUNCATE_TO_MEM_VI8)
4626 ScalarVT = MVT::i8;
4627 else if (IntrData->Type == TRUNCATE_TO_MEM_VI16)
4628 ScalarVT = MVT::i16;
4629 else if (IntrData->Type == TRUNCATE_TO_MEM_VI32)
4630 ScalarVT = MVT::i32;
4631
4632 Info.memVT = MVT::getVectorVT(ScalarVT, VT.getVectorNumElements());
4633 Info.align = 1;
4634 Info.flags |= MachineMemOperand::MOStore;
4635 break;
4636 }
4637 default:
4638 return false;
4639 }
4640
4641 return true;
4642}
4643
4644/// Returns true if the target can instruction select the
4645/// specified FP immediate natively. If false, the legalizer will
4646/// materialize the FP immediate as a load from a constant pool.
4647bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
4648 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
4649 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
4650 return true;
4651 }
4652 return false;
4653}
4654
4655bool X86TargetLowering::shouldReduceLoadWidth(SDNode *Load,
4656 ISD::LoadExtType ExtTy,
4657 EVT NewVT) const {
4658 // "ELF Handling for Thread-Local Storage" specifies that R_X86_64_GOTTPOFF
4659 // relocation target a movq or addq instruction: don't let the load shrink.
4660 SDValue BasePtr = cast<LoadSDNode>(Load)->getBasePtr();
4661 if (BasePtr.getOpcode() == X86ISD::WrapperRIP)
4662 if (const auto *GA = dyn_cast<GlobalAddressSDNode>(BasePtr.getOperand(0)))
4663 return GA->getTargetFlags() != X86II::MO_GOTTPOFF;
4664 return true;
4665}
4666
4667/// \brief Returns true if it is beneficial to convert a load of a constant
4668/// to just the constant itself.
4669bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
4670 Type *Ty) const {
4671 assert(Ty->isIntegerTy())(static_cast <bool> (Ty->isIntegerTy()) ? void (0) :
__assert_fail ("Ty->isIntegerTy()", "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 4671, __extension__ __PRETTY_FUNCTION__))
;
4672
4673 unsigned BitSize = Ty->getPrimitiveSizeInBits();
4674 if (BitSize == 0 || BitSize > 64)
4675 return false;
4676 return true;
4677}
4678
4679bool X86TargetLowering::convertSelectOfConstantsToMath(EVT VT) const {
4680 // TODO: It might be a win to ease or lift this restriction, but the generic
4681 // folds in DAGCombiner conflict with vector folds for an AVX512 target.
4682 if (VT.isVector() && Subtarget.hasAVX512())
4683 return false;
4684
4685 return true;
4686}
4687
4688bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
4689 unsigned Index) const {
4690 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))
4691 return false;
4692
4693 // Mask vectors support all subregister combinations and operations that
4694 // extract half of vector.
4695 if (ResVT.getVectorElementType() == MVT::i1)
4696 return Index == 0 || ((ResVT.getSizeInBits() == SrcVT.getSizeInBits()*2) &&
4697 (Index == ResVT.getVectorNumElements()));
4698
4699 return (Index % ResVT.getVectorNumElements()) == 0;
4700}
4701
4702bool X86TargetLowering::isCheapToSpeculateCttz() const {
4703 // Speculate cttz only if we can directly use TZCNT.
4704 return Subtarget.hasBMI();
4705}
4706
4707bool X86TargetLowering::isCheapToSpeculateCtlz() const {
4708 // Speculate ctlz only if we can directly use LZCNT.
4709 return Subtarget.hasLZCNT();
4710}
4711
4712bool X86TargetLowering::isLoadBitCastBeneficial(EVT LoadVT,
4713 EVT BitcastVT) const {
4714 if (!Subtarget.hasDQI() && BitcastVT == MVT::v8i1)
4715 return false;
4716
4717 return TargetLowering::isLoadBitCastBeneficial(LoadVT, BitcastVT);
4718}
4719
4720bool X86TargetLowering::canMergeStoresTo(unsigned AddressSpace, EVT MemVT,
4721 const SelectionDAG &DAG) const {
4722 // Do not merge to float value size (128 bytes) if no implicit
4723 // float attribute is set.
4724 bool NoFloat = DAG.getMachineFunction().getFunction().hasFnAttribute(
4725 Attribute::NoImplicitFloat);
4726
4727 if (NoFloat) {
4728 unsigned MaxIntSize = Subtarget.is64Bit() ? 64 : 32;
4729 return (MemVT.getSizeInBits() <= MaxIntSize);
4730 }
4731 return true;
4732}
4733
4734bool X86TargetLowering::isCtlzFast() const {
4735 return Subtarget.hasFastLZCNT();
4736}
4737
4738bool X86TargetLowering::isMaskAndCmp0FoldingBeneficial(
4739 const Instruction &AndI) const {
4740 return true;
4741}
4742
4743bool X86TargetLowering::hasAndNotCompare(SDValue Y) const {
4744 if (!Subtarget.hasBMI())
4745 return false;
4746
4747 // There are only 32-bit and 64-bit forms for 'andn'.
4748 EVT VT = Y.getValueType();
4749 if (VT != MVT::i32 && VT != MVT::i64)
4750 return false;
4751
4752 return true;
4753}
4754
4755MVT X86TargetLowering::hasFastEqualityCompare(unsigned NumBits) const {
4756 MVT VT = MVT::getIntegerVT(NumBits);
4757 if (isTypeLegal(VT))
4758 return VT;
4759
4760 // PMOVMSKB can handle this.
4761 if (NumBits == 128 && isTypeLegal(MVT::v16i8))
4762 return MVT::v16i8;
4763
4764 // VPMOVMSKB can handle this.
4765 if (NumBits == 256 && isTypeLegal(MVT::v32i8))
4766 return MVT::v32i8;
4767
4768 // TODO: Allow 64-bit type for 32-bit target.
4769 // TODO: 512-bit types should be allowed, but make sure that those
4770 // cases are handled in combineVectorSizedSetCCEquality().
4771
4772 return MVT::INVALID_SIMPLE_VALUE_TYPE;
4773}
4774
4775/// Val is the undef sentinel value or equal to the specified value.
4776static bool isUndefOrEqual(int Val, int CmpVal) {
4777 return ((Val == SM_SentinelUndef) || (Val == CmpVal));
4778}
4779
4780/// Val is either the undef or zero sentinel value.
4781static bool isUndefOrZero(int Val) {
4782 return ((Val == SM_SentinelUndef) || (Val == SM_SentinelZero));
4783}
4784
4785/// Return true if every element in Mask, beginning
4786/// from position Pos and ending in Pos+Size is the undef sentinel value.
4787static bool isUndefInRange(ArrayRef<int> Mask, unsigned Pos, unsigned Size) {
4788 for (unsigned i = Pos, e = Pos + Size; i != e; ++i)
4789 if (Mask[i] != SM_SentinelUndef)
4790 return false;
4791 return true;
4792}
4793
4794/// Return true if Val is undef or if its value falls within the
4795/// specified range (L, H].
4796static bool isUndefOrInRange(int Val, int Low, int Hi) {
4797 return (Val == SM_SentinelUndef) || (Val >= Low && Val < Hi);
4798}
4799
4800/// Return true if every element in Mask is undef or if its value
4801/// falls within the specified range (L, H].
4802static bool isUndefOrInRange(ArrayRef<int> Mask,
4803 int Low, int Hi) {
4804 for (int M : Mask)
4805 if (!isUndefOrInRange(M, Low, Hi))
4806 return false;
4807 return true;
4808}
4809
4810/// Return true if Val is undef, zero or if its value falls within the
4811/// specified range (L, H].
4812static bool isUndefOrZeroOrInRange(int Val, int Low, int Hi) {
4813 return isUndefOrZero(Val) || (Val >= Low && Val < Hi);
4814}
4815
4816/// Return true if every element in Mask is undef, zero or if its value
4817/// falls within the specified range (L, H].
4818static bool isUndefOrZeroOrInRange(ArrayRef<int> Mask, int Low, int Hi) {
4819 for (int M : Mask)
4820 if (!isUndefOrZeroOrInRange(M, Low, Hi))
4821 return false;
4822 return true;
4823}
4824
4825/// Return true if every element in Mask, beginning
4826/// from position Pos and ending in Pos+Size, falls within the specified
4827/// sequential range (Low, Low+Size]. or is undef.
4828static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
4829 unsigned Pos, unsigned Size, int Low) {
4830 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
4831 if (!isUndefOrEqual(Mask[i], Low))
4832 return false;
4833 return true;
4834}
4835
4836/// Return true if every element in Mask, beginning
4837/// from position Pos and ending in Pos+Size, falls within the specified
4838/// sequential range (Low, Low+Size], or is undef or is zero.
4839static bool isSequentialOrUndefOrZeroInRange(ArrayRef<int> Mask, unsigned Pos,
4840 unsigned Size, int Low) {
4841 for (unsigned i = Pos, e = Pos + Size; i != e; ++i, ++Low)
4842 if (!isUndefOrZero(Mask[i]) && Mask[i] != Low)
4843 return false;
4844 return true;
4845}
4846
4847/// Return true if every element in Mask, beginning
4848/// from position Pos and ending in Pos+Size is undef or is zero.
4849static bool isUndefOrZeroInRange(ArrayRef<int> Mask, unsigned Pos,
4850 unsigned Size) {
4851 for (unsigned i = Pos, e = Pos + Size; i != e; ++i)
4852 if (!isUndefOrZero(Mask[i]))
4853 return false;
4854 return true;
4855}
4856
4857/// \brief Helper function to test whether a shuffle mask could be
4858/// simplified by widening the elements being shuffled.
4859///
4860/// Appends the mask for wider elements in WidenedMask if valid. Otherwise
4861/// leaves it in an unspecified state.
4862///
4863/// NOTE: This must handle normal vector shuffle masks and *target* vector
4864/// shuffle masks. The latter have the special property of a '-2' representing
4865/// a zero-ed lane of a vector.
4866static bool canWidenShuffleElements(ArrayRef<int> Mask,
4867 SmallVectorImpl<int> &WidenedMask) {
4868 WidenedMask.assign(Mask.size() / 2, 0);
4869 for (int i = 0, Size = Mask.size(); i < Size; i += 2) {
4870 int M0 = Mask[i];
4871 int M1 = Mask[i + 1];
4872
4873 // If both elements are undef, its trivial.
4874 if (M0 == SM_SentinelUndef && M1 == SM_SentinelUndef) {
4875 WidenedMask[i / 2] = SM_SentinelUndef;
4876 continue;
4877 }
4878
4879 // Check for an undef mask and a mask value properly aligned to fit with
4880 // a pair of values. If we find such a case, use the non-undef mask's value.
4881 if (M0 == SM_SentinelUndef && M1 >= 0 && (M1 % 2) == 1) {
4882 WidenedMask[i / 2] = M1 / 2;
4883 continue;
4884 }
4885 if (M1 == SM_SentinelUndef && M0 >= 0 && (M0 % 2) == 0) {
4886 WidenedMask[i / 2] = M0 / 2;
4887 continue;
4888 }
4889
4890 // When zeroing, we need to spread the zeroing across both lanes to widen.
4891 if (M0 == SM_SentinelZero || M1 == SM_SentinelZero) {
4892 if ((M0 == SM_SentinelZero || M0 == SM_SentinelUndef) &&
4893 (M1 == SM_SentinelZero || M1 == SM_SentinelUndef)) {
4894 WidenedMask[i / 2] = SM_SentinelZero;
4895 continue;
4896 }
4897 return false;
4898 }
4899
4900 // Finally check if the two mask values are adjacent and aligned with
4901 // a pair.
4902 if (M0 != SM_SentinelUndef && (M0 % 2) == 0 && (M0 + 1) == M1) {
4903 WidenedMask[i / 2] = M0 / 2;
4904 continue;
4905 }
4906
4907 // Otherwise we can't safely widen the elements used in this shuffle.
4908 return false;
4909 }
4910 assert(WidenedMask.size() == Mask.size() / 2 &&(static_cast <bool> (WidenedMask.size() == Mask.size() /
2 && "Incorrect size of mask after widening the elements!"
) ? void (0) : __assert_fail ("WidenedMask.size() == Mask.size() / 2 && \"Incorrect size of mask after widening the elements!\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 4911, __extension__ __PRETTY_FUNCTION__))
4911 "Incorrect size of mask after widening the elements!")(static_cast <bool> (WidenedMask.size() == Mask.size() /
2 && "Incorrect size of mask after widening the elements!"
) ? void (0) : __assert_fail ("WidenedMask.size() == Mask.size() / 2 && \"Incorrect size of mask after widening the elements!\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 4911, __extension__ __PRETTY_FUNCTION__))
;
4912
4913 return true;
4914}
4915
4916/// Returns true if Elt is a constant zero or a floating point constant +0.0.
4917bool X86::isZeroNode(SDValue Elt) {
4918 return isNullConstant(Elt) || isNullFPConstant(Elt);
4919}
4920
4921// Build a vector of constants.
4922// Use an UNDEF node if MaskElt == -1.
4923// Split 64-bit constants in the 32-bit mode.
4924static SDValue getConstVector(ArrayRef<int> Values, MVT VT, SelectionDAG &DAG,
4925 const SDLoc &dl, bool IsMask = false) {
4926
4927 SmallVector<SDValue, 32> Ops;
4928 bool Split = false;
4929
4930 MVT ConstVecVT = VT;
4931 unsigned NumElts = VT.getVectorNumElements();
4932 bool In64BitMode = DAG.getTargetLoweringInfo().isTypeLegal(MVT::i64);
4933 if (!In64BitMode && VT.getVectorElementType() == MVT::i64) {
4934 ConstVecVT = MVT::getVectorVT(MVT::i32, NumElts * 2);
4935 Split = true;
4936 }
4937
4938 MVT EltVT = ConstVecVT.getVectorElementType();
4939 for (unsigned i = 0; i < NumElts; ++i) {
4940 bool IsUndef = Values[i] < 0 && IsMask;
4941 SDValue OpNode = IsUndef ? DAG.getUNDEF(EltVT) :
4942 DAG.getConstant(Values[i], dl, EltVT);
4943 Ops.push_back(OpNode);
4944 if (Split)
4945 Ops.push_back(IsUndef ? DAG.getUNDEF(EltVT) :
4946 DAG.getConstant(0, dl, EltVT));
4947 }
4948 SDValue ConstsNode = DAG.getBuildVector(ConstVecVT, dl, Ops);
4949 if (Split)
4950 ConstsNode = DAG.getBitcast(VT, ConstsNode);
4951 return ConstsNode;
4952}
4953
4954static SDValue getConstVector(ArrayRef<APInt> Bits, APInt &Undefs,
4955 MVT VT, SelectionDAG &DAG, const SDLoc &dl) {
4956 assert(Bits.size() == Undefs.getBitWidth() &&(static_cast <bool> (Bits.size() == Undefs.getBitWidth(
) && "Unequal constant and undef arrays") ? void (0) :
__assert_fail ("Bits.size() == Undefs.getBitWidth() && \"Unequal constant and undef arrays\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 4957, __extension__ __PRETTY_FUNCTION__))
4957 "Unequal constant and undef arrays")(static_cast <bool> (Bits.size() == Undefs.getBitWidth(
) && "Unequal constant and undef arrays") ? void (0) :
__assert_fail ("Bits.size() == Undefs.getBitWidth() && \"Unequal constant and undef arrays\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 4957, __extension__ __PRETTY_FUNCTION__))
;
4958 SmallVector<SDValue, 32> Ops;
4959 bool Split = false;
4960
4961 MVT ConstVecVT = VT;
4962 unsigned NumElts = VT.getVectorNumElements();
4963 bool In64BitMode = DAG.getTargetLoweringInfo().isTypeLegal(MVT::i64);
4964 if (!In64BitMode && VT.getVectorElementType() == MVT::i64) {
4965 ConstVecVT = MVT::getVectorVT(MVT::i32, NumElts * 2);
4966 Split = true;
4967 }
4968
4969 MVT EltVT = ConstVecVT.getVectorElementType();
4970 for (unsigned i = 0, e = Bits.size(); i != e; ++i) {
4971 if (Undefs[i]) {
4972 Ops.append(Split ? 2 : 1, DAG.getUNDEF(EltVT));
4973 continue;
4974 }
4975 const APInt &V = Bits[i];
4976 assert(V.getBitWidth() == VT.getScalarSizeInBits() && "Unexpected sizes")(static_cast <bool> (V.getBitWidth() == VT.getScalarSizeInBits
() && "Unexpected sizes") ? void (0) : __assert_fail (
"V.getBitWidth() == VT.getScalarSizeInBits() && \"Unexpected sizes\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 4976, __extension__ __PRETTY_FUNCTION__))
;
4977 if (Split) {
4978 Ops.push_back(DAG.getConstant(V.trunc(32), dl, EltVT));
4979 Ops.push_back(DAG.getConstant(V.lshr(32).trunc(32), dl, EltVT));
4980 } else if (EltVT == MVT::f32) {
4981 APFloat FV(APFloat::IEEEsingle(), V);
4982 Ops.push_back(DAG.getConstantFP(FV, dl, EltVT));
4983 } else if (EltVT == MVT::f64) {
4984 APFloat FV(APFloat::IEEEdouble(), V);
4985 Ops.push_back(DAG.getConstantFP(FV, dl, EltVT));
4986 } else {
4987 Ops.push_back(DAG.getConstant(V, dl, EltVT));
4988 }
4989 }
4990
4991 SDValue ConstsNode = DAG.getBuildVector(ConstVecVT, dl, Ops);
4992 return DAG.getBitcast(VT, ConstsNode);
4993}
4994
4995/// Returns a vector of specified type with all zero elements.
4996static SDValue getZeroVector(MVT VT, const X86Subtarget &Subtarget,
4997 SelectionDAG &DAG, const SDLoc &dl) {
4998 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector() ||(static_cast <bool> ((VT.is128BitVector() || VT.is256BitVector
() || VT.is512BitVector() || VT.getVectorElementType() == MVT
::i1) && "Unexpected vector type") ? void (0) : __assert_fail
("(VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector() || VT.getVectorElementType() == MVT::i1) && \"Unexpected vector type\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 5000, __extension__ __PRETTY_FUNCTION__))
4999 VT.getVectorElementType() == MVT::i1) &&(static_cast <bool> ((VT.is128BitVector() || VT.is256BitVector
() || VT.is512BitVector() || VT.getVectorElementType() == MVT
::i1) && "Unexpected vector type") ? void (0) : __assert_fail
("(VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector() || VT.getVectorElementType() == MVT::i1) && \"Unexpected vector type\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 5000, __extension__ __PRETTY_FUNCTION__))
5000 "Unexpected vector type")(static_cast <bool> ((VT.is128BitVector() || VT.is256BitVector
() || VT.is512BitVector() || VT.getVectorElementType() == MVT
::i1) && "Unexpected vector type") ? void (0) : __assert_fail
("(VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector() || VT.getVectorElementType() == MVT::i1) && \"Unexpected vector type\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 5000, __extension__ __PRETTY_FUNCTION__))
;
5001
5002 // Try to build SSE/AVX zero vectors as <N x i32> bitcasted to their dest
5003 // type. This ensures they get CSE'd. But if the integer type is not
5004 // available, use a floating-point +0.0 instead.
5005 SDValue Vec;
5006 if (!Subtarget.hasSSE2() && VT.is128BitVector()) {
5007 Vec = DAG.getConstantFP(+0.0, dl, MVT::v4f32);
5008 } else if (VT.getVectorElementType() == MVT::i1) {
5009 assert((Subtarget.hasBWI() || VT.getVectorNumElements() <= 16) &&(static_cast <bool> ((Subtarget.hasBWI() || VT.getVectorNumElements
() <= 16) && "Unexpected vector type") ? void (0) :
__assert_fail ("(Subtarget.hasBWI() || VT.getVectorNumElements() <= 16) && \"Unexpected vector type\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 5010, __extension__ __PRETTY_FUNCTION__))
5010 "Unexpected vector type")(static_cast <bool> ((Subtarget.hasBWI() || VT.getVectorNumElements
() <= 16) && "Unexpected vector type") ? void (0) :
__assert_fail ("(Subtarget.hasBWI() || VT.getVectorNumElements() <= 16) && \"Unexpected vector type\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 5010, __extension__ __PRETTY_FUNCTION__))
;
5011 Vec = DAG.getConstant(0, dl, VT);
5012 } else {
5013 unsigned Num32BitElts = VT.getSizeInBits() / 32;
5014 Vec = DAG.getConstant(0, dl, MVT::getVectorVT(MVT::i32, Num32BitElts));
5015 }
5016 return DAG.getBitcast(VT, Vec);
5017}
5018
5019static SDValue extractSubVector(SDValue Vec, unsigned IdxVal, SelectionDAG &DAG,
5020 const SDLoc &dl, unsigned vectorWidth) {
5021 EVT VT = Vec.getValueType();
5022 EVT ElVT = VT.getVectorElementType();
5023 unsigned Factor = VT.getSizeInBits()/vectorWidth;
5024 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
5025 VT.getVectorNumElements()/Factor);
5026
5027 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
5028 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
5029 assert(isPowerOf2_32(ElemsPerChunk) && "Elements per chunk not power of 2")(static_cast <bool> (isPowerOf2_32(ElemsPerChunk) &&
"Elements per chunk not power of 2") ? void (0) : __assert_fail
("isPowerOf2_32(ElemsPerChunk) && \"Elements per chunk not power of 2\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 5029, __extension__ __PRETTY_FUNCTION__))
;
5030
5031 // This is the index of the first element of the vectorWidth-bit chunk
5032 // we want. Since ElemsPerChunk is a power of 2 just need to clear bits.
5033 IdxVal &= ~(ElemsPerChunk - 1);
5034
5035 // If the input is a buildvector just emit a smaller one.
5036 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
5037 return DAG.getBuildVector(ResultVT, dl,
5038 Vec->ops().slice(IdxVal, ElemsPerChunk));
5039
5040 SDValue VecIdx = DAG.getIntPtrConstant(IdxVal, dl);
5041 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, VecIdx);
5042}
5043
5044/// Generate a DAG to grab 128-bits from a vector > 128 bits. This
5045/// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
5046/// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
5047/// instructions or a simple subregister reference. Idx is an index in the
5048/// 128 bits we want. It need not be aligned to a 128-bit boundary. That makes
5049/// lowering EXTRACT_VECTOR_ELT operations easier.
5050static SDValue extract128BitVector(SDValue Vec, unsigned IdxVal,
5051 SelectionDAG &DAG, const SDLoc &dl) {
5052 assert((Vec.getValueType().is256BitVector() ||(static_cast <bool> ((Vec.getValueType().is256BitVector
() || Vec.getValueType().is512BitVector()) && "Unexpected vector size!"
) ? void (0) : __assert_fail ("(Vec.getValueType().is256BitVector() || Vec.getValueType().is512BitVector()) && \"Unexpected vector size!\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 5053, __extension__ __PRETTY_FUNCTION__))
5053 Vec.getValueType().is512BitVector()) && "Unexpected vector size!")(static_cast <bool> ((Vec.getValueType().is256BitVector
() || Vec.getValueType().is512BitVector()) && "Unexpected vector size!"
) ? void (0) : __assert_fail ("(Vec.getValueType().is256BitVector() || Vec.getValueType().is512BitVector()) && \"Unexpected vector size!\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 5053, __extension__ __PRETTY_FUNCTION__))
;
5054 return extractSubVector(Vec, IdxVal, DAG, dl, 128);
5055}
5056
5057/// Generate a DAG to grab 256-bits from a 512-bit vector.
5058static SDValue extract256BitVector(SDValue Vec, unsigned IdxVal,
5059 SelectionDAG &DAG, const SDLoc &dl) {
5060 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!")(static_cast <bool> (Vec.getValueType().is512BitVector(
) && "Unexpected vector size!") ? void (0) : __assert_fail
("Vec.getValueType().is512BitVector() && \"Unexpected vector size!\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 5060, __extension__ __PRETTY_FUNCTION__))
;
5061 return extractSubVector(Vec, IdxVal, DAG, dl, 256);
5062}
5063
5064static SDValue insertSubVector(SDValue Result, SDValue Vec, unsigned IdxVal,
5065 SelectionDAG &DAG, const SDLoc &dl,
5066 unsigned vectorWidth) {
5067 assert((vectorWidth == 128 || vectorWidth == 256) &&(static_cast <bool> ((vectorWidth == 128 || vectorWidth
== 256) && "Unsupported vector width") ? void (0) : __assert_fail
("(vectorWidth == 128 || vectorWidth == 256) && \"Unsupported vector width\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 5068, __extension__ __PRETTY_FUNCTION__))
5068 "Unsupported vector width")(static_cast <bool> ((vectorWidth == 128 || vectorWidth
== 256) && "Unsupported vector width") ? void (0) : __assert_fail
("(vectorWidth == 128 || vectorWidth == 256) && \"Unsupported vector width\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 5068, __extension__ __PRETTY_FUNCTION__))
;
5069 // Inserting UNDEF is Result
5070 if (Vec.isUndef())
5071 return Result;
5072 EVT VT = Vec.getValueType();
5073 EVT ElVT = VT.getVectorElementType();
5074 EVT ResultVT = Result.getValueType();
5075
5076 // Insert the relevant vectorWidth bits.
5077 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
5078 assert(isPowerOf2_32(ElemsPerChunk) && "Elements per chunk not power of 2")(static_cast <bool> (isPowerOf2_32(ElemsPerChunk) &&
"Elements per chunk not power of 2") ? void (0) : __assert_fail
("isPowerOf2_32(ElemsPerChunk) && \"Elements per chunk not power of 2\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 5078, __extension__ __PRETTY_FUNCTION__))
;
5079
5080 // This is the index of the first element of the vectorWidth-bit chunk
5081 // we want. Since ElemsPerChunk is a power of 2 just need to clear bits.
5082 IdxVal &= ~(ElemsPerChunk - 1);
5083
5084 SDValue VecIdx = DAG.getIntPtrConstant(IdxVal, dl);
5085 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, VecIdx);
5086}
5087
5088/// Generate a DAG to put 128-bits into a vector > 128 bits. This
5089/// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
5090/// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
5091/// simple superregister reference. Idx is an index in the 128 bits
5092/// we want. It need not be aligned to a 128-bit boundary. That makes
5093/// lowering INSERT_VECTOR_ELT operations easier.
5094static SDValue insert128BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
5095 SelectionDAG &DAG, const SDLoc &dl) {
5096 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!")(static_cast <bool> (Vec.getValueType().is128BitVector(
) && "Unexpected vector size!") ? void (0) : __assert_fail
("Vec.getValueType().is128BitVector() && \"Unexpected vector size!\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 5096, __extension__ __PRETTY_FUNCTION__))
;
5097 return insertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
5098}
5099
5100/// Widen a vector to a larger size with the same scalar type, with the new
5101/// elements either zero or undef.
5102static SDValue widenSubVector(MVT VT, SDValue Vec, bool ZeroNewElements,
5103 const X86Subtarget &Subtarget, SelectionDAG &DAG,
5104 const SDLoc &dl) {
5105 assert(Vec.getValueSizeInBits() < VT.getSizeInBits() &&(static_cast <bool> (Vec.getValueSizeInBits() < VT.getSizeInBits
() && Vec.getValueType().getScalarType() == VT.getScalarType
() && "Unsupported vector widening type") ? void (0) :
__assert_fail ("Vec.getValueSizeInBits() < VT.getSizeInBits() && Vec.getValueType().getScalarType() == VT.getScalarType() && \"Unsupported vector widening type\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 5107, __extension__ __PRETTY_FUNCTION__))
5106 Vec.getValueType().getScalarType() == VT.getScalarType() &&(static_cast <bool> (Vec.getValueSizeInBits() < VT.getSizeInBits
() && Vec.getValueType().getScalarType() == VT.getScalarType
() && "Unsupported vector widening type") ? void (0) :
__assert_fail ("Vec.getValueSizeInBits() < VT.getSizeInBits() && Vec.getValueType().getScalarType() == VT.getScalarType() && \"Unsupported vector widening type\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 5107, __extension__ __PRETTY_FUNCTION__))
5107 "Unsupported vector widening type")(static_cast <bool> (Vec.getValueSizeInBits() < VT.getSizeInBits
() && Vec.getValueType().getScalarType() == VT.getScalarType
() && "Unsupported vector widening type") ? void (0) :
__assert_fail ("Vec.getValueSizeInBits() < VT.getSizeInBits() && Vec.getValueType().getScalarType() == VT.getScalarType() && \"Unsupported vector widening type\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 5107, __extension__ __PRETTY_FUNCTION__))
;
5108 SDValue Res = ZeroNewElements ? getZeroVector(VT, Subtarget, DAG, dl)
5109 : DAG.getUNDEF(VT);
5110 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, VT, Res, Vec,
5111 DAG.getIntPtrConstant(0, dl));
5112}
5113
5114// Helper for splitting operands of an operation to legal target size and
5115// apply a function on each part.
5116// Useful for operations that are available on SSE2 in 128-bit, on AVX2 in
5117// 256-bit and on AVX512BW in 512-bit. The argument VT is the type used for
5118// deciding if/how to split Ops. Ops elements do *not* have to be of type VT.
5119// The argument Builder is a function that will be applied on each split part:
5120// SDValue Builder(SelectionDAG&G, SDLoc, ArrayRef<SDValue>)
5121template <typename F>
5122SDValue SplitOpsAndApply(SelectionDAG &DAG, const X86Subtarget &Subtarget,
5123 const SDLoc &DL, EVT VT, ArrayRef<SDValue> Ops,
5124 F Builder, bool CheckBWI = true) {
5125 assert(Subtarget.hasSSE2() && "Target assumed to support at least SSE2")(static_cast <bool> (Subtarget.hasSSE2() && "Target assumed to support at least SSE2"
) ? void (0) : __assert_fail ("Subtarget.hasSSE2() && \"Target assumed to support at least SSE2\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 5125, __extension__ __PRETTY_FUNCTION__))
;
5126 unsigned NumSubs = 1;
5127 if ((CheckBWI && Subtarget.useBWIRegs()) ||
5128 (!CheckBWI && Subtarget.useAVX512Regs())) {
5129 if (VT.getSizeInBits() > 512) {
5130 NumSubs = VT.getSizeInBits() / 512;
5131 assert((VT.getSizeInBits() % 512) == 0 && "Illegal vector size")(static_cast <bool> ((VT.getSizeInBits() % 512) == 0 &&
"Illegal vector size") ? void (0) : __assert_fail ("(VT.getSizeInBits() % 512) == 0 && \"Illegal vector size\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 5131, __extension__ __PRETTY_FUNCTION__))
;
5132 }
5133 } else if (Subtarget.hasAVX2()) {
5134 if (VT.getSizeInBits() > 256) {
5135 NumSubs = VT.getSizeInBits() / 256;
5136 assert((VT.getSizeInBits() % 256) == 0 && "Illegal vector size")(static_cast <bool> ((VT.getSizeInBits() % 256) == 0 &&
"Illegal vector size") ? void (0) : __assert_fail ("(VT.getSizeInBits() % 256) == 0 && \"Illegal vector size\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 5136, __extension__ __PRETTY_FUNCTION__))
;
5137 }
5138 } else {
5139 if (VT.getSizeInBits() > 128) {
5140 NumSubs = VT.getSizeInBits() / 128;
5141 assert((VT.getSizeInBits() % 128) == 0 && "Illegal vector size")(static_cast <bool> ((VT.getSizeInBits() % 128) == 0 &&
"Illegal vector size") ? void (0) : __assert_fail ("(VT.getSizeInBits() % 128) == 0 && \"Illegal vector size\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 5141, __extension__ __PRETTY_FUNCTION__))
;
5142 }
5143 }
5144
5145 if (NumSubs == 1)
5146 return Builder(DAG, DL, Ops);
5147
5148 SmallVector<SDValue, 4> Subs;
5149 for (unsigned i = 0; i != NumSubs; ++i) {
5150 SmallVector<SDValue, 2> SubOps;
5151 for (SDValue Op : Ops) {
5152 EVT OpVT = Op.getValueType();
5153 unsigned NumSubElts = OpVT.getVectorNumElements() / NumSubs;
5154 unsigned SizeSub = OpVT.getSizeInBits() / NumSubs;
5155 SubOps.push_back(extractSubVector(Op, i * NumSubElts, DAG, DL, SizeSub));
5156 }
5157 Subs.push_back(Builder(DAG, DL, SubOps));
5158 }
5159 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Subs);
5160}
5161
5162// Return true if the instruction zeroes the unused upper part of the
5163// destination and accepts mask.
5164static bool isMaskedZeroUpperBitsvXi1(unsigned int Opcode) {
5165 switch (Opcode) {
5166 default:
5167 return false;
5168 case X86ISD::CMPM:
5169 case X86ISD::CMPMU:
5170 case X86ISD::CMPM_RND:
5171 return true;
5172 }
5173}
5174
5175/// Insert i1-subvector to i1-vector.
5176static SDValue insert1BitVector(SDValue Op, SelectionDAG &DAG,
5177 const X86Subtarget &Subtarget) {
5178
5179 SDLoc dl(Op);
5180 SDValue Vec = Op.getOperand(0);
5181 SDValue SubVec = Op.getOperand(1);
5182 SDValue Idx = Op.getOperand(2);
5183
5184 if (!isa<ConstantSDNode>(Idx))
5185 return SDValue();
5186
5187 // Inserting undef is a nop. We can just return the original vector.
5188 if (SubVec.isUndef())
5189 return Vec;
5190
5191 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
5192 if (IdxVal == 0 && Vec.isUndef()) // the operation is legal
5193 return Op;
5194
5195 MVT OpVT = Op.getSimpleValueType();
5196 unsigned NumElems = OpVT.getVectorNumElements();
5197
5198 SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
5199
5200 // Extend to natively supported kshift.
5201 MVT WideOpVT = OpVT;
5202 if ((!Subtarget.hasDQI() && NumElems == 8) || NumElems < 8)
5203 WideOpVT = Subtarget.hasDQI() ? MVT::v8i1 : MVT::v16i1;
5204
5205 // Inserting into the lsbs of a zero vector is legal. ISel will insert shifts
5206 // if necessary.
5207 if (IdxVal == 0 && ISD::isBuildVectorAllZeros(Vec.getNode())) {
5208 // May need to promote to a legal type.
5209 Op = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, WideOpVT,
5210 getZeroVector(WideOpVT, Subtarget, DAG, dl),
5211 SubVec, Idx);
5212 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OpVT, Op, ZeroIdx);
5213 }
5214
5215 MVT SubVecVT = SubVec.getSimpleValueType();
5216 unsigned SubVecNumElems = SubVecVT.getVectorNumElements();
5217
5218 assert(IdxVal + SubVecNumElems <= NumElems &&(static_cast <bool> (IdxVal + SubVecNumElems <= NumElems
&& IdxVal % SubVecVT.getSizeInBits() == 0 &&
"Unexpected index value in INSERT_SUBVECTOR") ? void (0) : __assert_fail
("IdxVal + SubVecNumElems <= NumElems && IdxVal % SubVecVT.getSizeInBits() == 0 && \"Unexpected index value in INSERT_SUBVECTOR\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 5220, __extension__ __PRETTY_FUNCTION__))
5219 IdxVal % SubVecVT.getSizeInBits() == 0 &&(static_cast <bool> (IdxVal + SubVecNumElems <= NumElems
&& IdxVal % SubVecVT.getSizeInBits() == 0 &&
"Unexpected index value in INSERT_SUBVECTOR") ? void (0) : __assert_fail
("IdxVal + SubVecNumElems <= NumElems && IdxVal % SubVecVT.getSizeInBits() == 0 && \"Unexpected index value in INSERT_SUBVECTOR\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 5220, __extension__ __PRETTY_FUNCTION__))
5220 "Unexpected index value in INSERT_SUBVECTOR")(static_cast <bool> (IdxVal + SubVecNumElems <= NumElems
&& IdxVal % SubVecVT.getSizeInBits() == 0 &&
"Unexpected index value in INSERT_SUBVECTOR") ? void (0) : __assert_fail
("IdxVal + SubVecNumElems <= NumElems && IdxVal % SubVecVT.getSizeInBits() == 0 && \"Unexpected index value in INSERT_SUBVECTOR\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 5220, __extension__ __PRETTY_FUNCTION__))
;
5221
5222 SDValue Undef = DAG.getUNDEF(WideOpVT);
5223
5224 if (IdxVal == 0) {
5225 // Zero lower bits of the Vec
5226 SDValue ShiftBits = DAG.getConstant(SubVecNumElems, dl, MVT::i8);
5227 Vec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, WideOpVT, Undef, Vec,
5228 ZeroIdx);
5229 Vec = DAG.getNode(X86ISD::KSHIFTR, dl, WideOpVT, Vec, ShiftBits);
5230 Vec = DAG.getNode(X86ISD::KSHIFTL, dl, WideOpVT, Vec, ShiftBits);
5231 // Merge them together, SubVec should be zero extended.
5232 SubVec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, WideOpVT,
5233 getZeroVector(WideOpVT, Subtarget, DAG, dl),
5234 SubVec, ZeroIdx);
5235 Op = DAG.getNode(ISD::OR, dl, WideOpVT, Vec, SubVec);
5236 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OpVT, Op, ZeroIdx);
5237 }
5238
5239 SubVec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, WideOpVT,
5240 Undef, SubVec, ZeroIdx);
5241
5242 if (Vec.isUndef()) {
5243 assert(IdxVal != 0 && "Unexpected index")(static_cast <bool> (IdxVal != 0 && "Unexpected index"
) ? void (0) : __assert_fail ("IdxVal != 0 && \"Unexpected index\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 5243, __extension__ __PRETTY_FUNCTION__))
;
5244 SubVec = DAG.getNode(X86ISD::KSHIFTL, dl, WideOpVT, SubVec,
5245 DAG.getConstant(IdxVal, dl, MVT::i8));
5246 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OpVT, SubVec, ZeroIdx);
5247 }
5248
5249 if (ISD::isBuildVectorAllZeros(Vec.getNode())) {
5250 assert(IdxVal != 0 && "Unexpected index")(static_cast <bool> (IdxVal != 0 && "Unexpected index"
) ? void (0) : __assert_fail ("IdxVal != 0 && \"Unexpected index\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 5250, __extension__ __PRETTY_FUNCTION__))
;
5251 NumElems = WideOpVT.getVectorNumElements();
5252 unsigned ShiftLeft = NumElems - SubVecNumElems;
5253 unsigned ShiftRight = NumElems - SubVecNumElems - IdxVal;
5254 SubVec = DAG.getNode(X86ISD::KSHIFTL, dl, WideOpVT, SubVec,
5255 DAG.getConstant(ShiftLeft, dl, MVT::i8));
5256 if (ShiftRight != 0)
5257 SubVec = DAG.getNode(X86ISD::KSHIFTR, dl, WideOpVT, SubVec,
5258 DAG.getConstant(ShiftRight, dl, MVT::i8));
5259 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OpVT, SubVec, ZeroIdx);
5260 }
5261
5262 // Simple case when we put subvector in the upper part
5263 if (IdxVal + SubVecNumElems == NumElems) {
5264 SubVec = DAG.getNode(X86ISD::KSHIFTL, dl, WideOpVT, SubVec,
5265 DAG.getConstant(IdxVal, dl, MVT::i8));
5266 if (SubVecNumElems * 2 == NumElems) {
5267 // Special case, use legal zero extending insert_subvector. This allows
5268 // isel to opimitize when bits are known zero.
5269 Vec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVecVT, Vec, ZeroIdx);
5270 Vec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, WideOpVT,
5271 getZeroVector(WideOpVT, Subtarget, DAG, dl),
5272 Vec, ZeroIdx);
5273 } else {
5274 // Otherwise use explicit shifts to zero the bits.
5275 Vec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, WideOpVT,
5276 Undef, Vec, ZeroIdx);
5277 NumElems = WideOpVT.getVectorNumElements();
5278 SDValue ShiftBits = DAG.getConstant(NumElems - IdxVal, dl, MVT::i8);
5279 Vec = DAG.getNode(X86ISD::KSHIFTL, dl, WideOpVT, Vec, ShiftBits);
5280 Vec = DAG.getNode(X86ISD::KSHIFTR, dl, WideOpVT, Vec, ShiftBits);
5281 }
5282 Op = DAG.getNode(ISD::OR, dl, WideOpVT, Vec, SubVec);
5283 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OpVT, Op, ZeroIdx);
5284 }
5285
5286 // Inserting into the middle is more complicated.
5287
5288 NumElems = WideOpVT.getVectorNumElements();
5289
5290 // Widen the vector if needed.
5291 Vec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, WideOpVT, Undef, Vec, ZeroIdx);
5292 // Move the current value of the bit to be replace to the lsbs.
5293 Op = DAG.getNode(X86ISD::KSHIFTR, dl, WideOpVT, Vec,
5294 DAG.getConstant(IdxVal, dl, MVT::i8));
5295 // Xor with the new bit.
5296 Op = DAG.getNode(ISD::XOR, dl, WideOpVT, Op, SubVec);
5297 // Shift to MSB, filling bottom bits with 0.
5298 unsigned ShiftLeft = NumElems - SubVecNumElems;
5299 Op = DAG.getNode(X86ISD::KSHIFTL, dl, WideOpVT, Op,
5300 DAG.getConstant(ShiftLeft, dl, MVT::i8));
5301 // Shift to the final position, filling upper bits with 0.
5302 unsigned ShiftRight = NumElems - SubVecNumElems - IdxVal;
5303 Op = DAG.getNode(X86ISD::KSHIFTR, dl, WideOpVT, Op,
5304 DAG.getConstant(ShiftRight, dl, MVT::i8));
5305 // Xor with original vector leaving the new value.
5306 Op = DAG.getNode(ISD::XOR, dl, WideOpVT, Vec, Op);
5307 // Reduce to original width if needed.
5308 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OpVT, Op, ZeroIdx);
5309}
5310
5311static SDValue concatSubVectors(SDValue V1, SDValue V2, EVT VT,
5312 unsigned NumElems, SelectionDAG &DAG,
5313 const SDLoc &dl, unsigned VectorWidth) {
5314 SDValue V = insertSubVector(DAG.getUNDEF(VT), V1, 0, DAG, dl, VectorWidth);
5315 return insertSubVector(V, V2, NumElems / 2, DAG, dl, VectorWidth);
5316}
5317
5318/// Returns a vector of specified type with all bits set.
5319/// Always build ones vectors as <4 x i32>, <8 x i32> or <16 x i32>.
5320/// Then bitcast to their original type, ensuring they get CSE'd.
5321static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, const SDLoc &dl) {
5322 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&(static_cast <bool> ((VT.is128BitVector() || VT.is256BitVector
() || VT.is512BitVector()) && "Expected a 128/256/512-bit vector type"
) ? void (0) : __assert_fail ("(VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) && \"Expected a 128/256/512-bit vector type\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 5323, __extension__ __PRETTY_FUNCTION__))
5323 "Expected a 128/256/512-bit vector type")(static_cast <bool> ((VT.is128BitVector() || VT.is256BitVector
() || VT.is512BitVector()) && "Expected a 128/256/512-bit vector type"
) ? void (0) : __assert_fail ("(VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) && \"Expected a 128/256/512-bit vector type\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 5323, __extension__ __PRETTY_FUNCTION__))
;
5324
5325 APInt Ones = APInt::getAllOnesValue(32);
5326 unsigned NumElts = VT.getSizeInBits() / 32;
5327 SDValue Vec = DAG.getConstant(Ones, dl, MVT::getVectorVT(MVT::i32, NumElts));
5328 return DAG.getBitcast(VT, Vec);
5329}
5330
5331static SDValue getExtendInVec(unsigned Opc, const SDLoc &DL, EVT VT, SDValue In,
5332 SelectionDAG &DAG) {
5333 EVT InVT = In.getValueType();
5334 assert((X86ISD::VSEXT == Opc || X86ISD::VZEXT == Opc) && "Unexpected opcode")(static_cast <bool> ((X86ISD::VSEXT == Opc || X86ISD::VZEXT
== Opc) && "Unexpected opcode") ? void (0) : __assert_fail
("(X86ISD::VSEXT == Opc || X86ISD::VZEXT == Opc) && \"Unexpected opcode\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 5334, __extension__ __PRETTY_FUNCTION__))
;
5335
5336 if (VT.is128BitVector() && InVT.is128BitVector())
5337 return X86ISD::VSEXT == Opc ? DAG.getSignExtendVectorInReg(In, DL, VT)
5338 : DAG.getZeroExtendVectorInReg(In, DL, VT);
5339
5340 // For 256-bit vectors, we only need the lower (128-bit) input half.
5341 // For 512-bit vectors, we only need the lower input half or quarter.
5342 if (VT.getSizeInBits() > 128 && InVT.getSizeInBits() > 128) {
5343 int Scale = VT.getScalarSizeInBits() / InVT.getScalarSizeInBits();
5344 In = extractSubVector(In, 0, DAG, DL,
5345 std::max(128, (int)VT.getSizeInBits() / Scale));
5346 }
5347
5348 return DAG.getNode(Opc, DL, VT, In);
5349}
5350
5351/// Returns a vector_shuffle node for an unpackl operation.
5352static SDValue getUnpackl(SelectionDAG &DAG, const SDLoc &dl, MVT VT,
5353 SDValue V1, SDValue V2) {
5354 SmallVector<int, 8> Mask;
5355 createUnpackShuffleMask(VT, Mask, /* Lo = */ true, /* Unary = */ false);
5356 return DAG.getVectorShuffle(VT, dl, V1, V2, Mask);
5357}
5358
5359/// Returns a vector_shuffle node for an unpackh operation.
5360static SDValue getUnpackh(SelectionDAG &DAG, const SDLoc &dl, MVT VT,
5361 SDValue V1, SDValue V2) {
5362 SmallVector<int, 8> Mask;
5363 createUnpackShuffleMask(VT, Mask, /* Lo = */ false, /* Unary = */ false);
5364 return DAG.getVectorShuffle(VT, dl, V1, V2, Mask);
5365}
5366
5367/// Return a vector_shuffle of the specified vector of zero or undef vector.
5368/// This produces a shuffle where the low element of V2 is swizzled into the
5369/// zero/undef vector, landing at element Idx.
5370/// This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
5371static SDValue getShuffleVectorZeroOrUndef(SDValue V2, int Idx,
5372 bool IsZero,
5373 const X86Subtarget &Subtarget,
5374 SelectionDAG &DAG) {
5375 MVT VT = V2.getSimpleValueType();
5376 SDValue V1 = IsZero
5377 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
5378 int NumElems = VT.getVectorNumElements();
5379 SmallVector<int, 16> MaskVec(NumElems);
5380 for (int i = 0; i != NumElems; ++i)
5381 // If this is the insertion idx, put the low elt of V2 here.
5382 MaskVec[i] = (i == Idx) ? NumElems : i;
5383 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, MaskVec);
5384}
5385
5386static SDValue peekThroughBitcasts(SDValue V) {
5387 while (V.getNode() && V.getOpcode() == ISD::BITCAST)
5388 V = V.getOperand(0);
5389 return V;
5390}
5391
5392static SDValue peekThroughOneUseBitcasts(SDValue V) {
5393 while (V.getNode() && V.getOpcode() == ISD::BITCAST &&
5394 V.getOperand(0).hasOneUse())
5395 V = V.getOperand(0);
5396 return V;
5397}
5398
5399static const Constant *getTargetConstantFromNode(SDValue Op) {
5400 Op = peekThroughBitcasts(Op);
5401
5402 auto *Load = dyn_cast<LoadSDNode>(Op);
5403 if (!Load)
5404 return nullptr;
5405
5406 SDValue Ptr = Load->getBasePtr();
5407 if (Ptr->getOpcode() == X86ISD::Wrapper ||
5408 Ptr->getOpcode() == X86ISD::WrapperRIP)
5409 Ptr = Ptr->getOperand(0);
5410
5411 auto *CNode = dyn_cast<ConstantPoolSDNode>(Ptr);
5412 if (!CNode || CNode->isMachineConstantPoolEntry())
5413 return nullptr;
5414
5415 return dyn_cast<Constant>(CNode->getConstVal());
5416}
5417
5418// Extract raw constant bits from constant pools.
5419static bool getTargetConstantBitsFromNode(SDValue Op, unsigned EltSizeInBits,
5420 APInt &UndefElts,
5421 SmallVectorImpl<APInt> &EltBits,
5422 bool AllowWholeUndefs = true,
5423 bool AllowPartialUndefs = true) {
5424 assert(EltBits.empty() && "Expected an empty EltBits vector")(static_cast <bool> (EltBits.empty() && "Expected an empty EltBits vector"
) ? void (0) : __assert_fail ("EltBits.empty() && \"Expected an empty EltBits vector\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 5424, __extension__ __PRETTY_FUNCTION__))
;
5425
5426 Op = peekThroughBitcasts(Op);
5427
5428 EVT VT = Op.getValueType();
5429 unsigned SizeInBits = VT.getSizeInBits();
5430 assert((SizeInBits % EltSizeInBits) == 0 && "Can't split constant!")(static_cast <bool> ((SizeInBits % EltSizeInBits) == 0 &&
"Can't split constant!") ? void (0) : __assert_fail ("(SizeInBits % EltSizeInBits) == 0 && \"Can't split constant!\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 5430, __extension__ __PRETTY_FUNCTION__))
;
5431 unsigned NumElts = SizeInBits / EltSizeInBits;
5432
5433 // Bitcast a source array of element bits to the target size.
5434 auto CastBitData = [&](APInt &UndefSrcElts, ArrayRef<APInt> SrcEltBits) {
5435 unsigned NumSrcElts = UndefSrcElts.getBitWidth();
5436 unsigned SrcEltSizeInBits = SrcEltBits[0].getBitWidth();
5437 assert((NumSrcElts * SrcEltSizeInBits) == SizeInBits &&(static_cast <bool> ((NumSrcElts * SrcEltSizeInBits) ==
SizeInBits && "Constant bit sizes don't match") ? void
(0) : __assert_fail ("(NumSrcElts * SrcEltSizeInBits) == SizeInBits && \"Constant bit sizes don't match\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 5438, __extension__ __PRETTY_FUNCTION__))
5438 "Constant bit sizes don't match")(static_cast <bool> ((NumSrcElts * SrcEltSizeInBits) ==
SizeInBits && "Constant bit sizes don't match") ? void
(0) : __assert_fail ("(NumSrcElts * SrcEltSizeInBits) == SizeInBits && \"Constant bit sizes don't match\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 5438, __extension__ __PRETTY_FUNCTION__))
;
5439
5440 // Don't split if we don't allow undef bits.
5441 bool AllowUndefs = AllowWholeUndefs || AllowPartialUndefs;
5442 if (UndefSrcElts.getBoolValue() && !AllowUndefs)
5443 return false;
5444
5445 // If we're already the right size, don't bother bitcasting.
5446 if (NumSrcElts == NumElts) {
5447 UndefElts = UndefSrcElts;
5448 EltBits.assign(SrcEltBits.begin(), SrcEltBits.end());
5449 return true;
5450 }
5451
5452 // Extract all the undef/constant element data and pack into single bitsets.
5453 APInt UndefBits(SizeInBits, 0);
5454 APInt MaskBits(SizeInBits, 0);
5455
5456 for (unsigned i = 0; i != NumSrcElts; ++i) {
5457 unsigned BitOffset = i * SrcEltSizeInBits;
5458 if (UndefSrcElts[i])
5459 UndefBits.setBits(BitOffset, BitOffset + SrcEltSizeInBits);
5460 MaskBits.insertBits(SrcEltBits[i], BitOffset);
5461 }
5462
5463 // Split the undef/constant single bitset data into the target elements.
5464 UndefElts = APInt(NumElts, 0);
5465 EltBits.resize(NumElts, APInt(EltSizeInBits, 0));
5466
5467 for (unsigned i = 0; i != NumElts; ++i) {
5468 unsigned BitOffset = i * EltSizeInBits;
5469 APInt UndefEltBits = UndefBits.extractBits(EltSizeInBits, BitOffset);
5470
5471 // Only treat an element as UNDEF if all bits are UNDEF.
5472 if (UndefEltBits.isAllOnesValue()) {
5473 if (!AllowWholeUndefs)
5474 return false;
5475 UndefElts.setBit(i);
5476 continue;
5477 }
5478
5479 // If only some bits are UNDEF then treat them as zero (or bail if not
5480 // supported).
5481 if (UndefEltBits.getBoolValue() && !AllowPartialUndefs)
5482 return false;
5483
5484 APInt Bits = MaskBits.extractBits(EltSizeInBits, BitOffset);
5485 EltBits[i] = Bits.getZExtValue();
5486 }
5487 return true;
5488 };
5489
5490 // Collect constant bits and insert into mask/undef bit masks.
5491 auto CollectConstantBits = [](const Constant *Cst, APInt &Mask, APInt &Undefs,
5492 unsigned UndefBitIndex) {
5493 if (!Cst)
5494 return false;
5495 if (isa<UndefValue>(Cst)) {
5496 Undefs.setBit(UndefBitIndex);
5497 return true;
5498 }
5499 if (auto *CInt = dyn_cast<ConstantInt>(Cst)) {
5500 Mask = CInt->getValue();
5501 return true;
5502 }
5503 if (auto *CFP = dyn_cast<ConstantFP>(Cst)) {
5504 Mask = CFP->getValueAPF().bitcastToAPInt();
5505 return true;
5506 }
5507 return false;
5508 };
5509
5510 // Handle UNDEFs.
5511 if (Op.isUndef()) {
5512 APInt UndefSrcElts = APInt::getAllOnesValue(NumElts);
5513 SmallVector<APInt, 64> SrcEltBits(NumElts, APInt(EltSizeInBits, 0));
5514 return CastBitData(UndefSrcElts, SrcEltBits);
5515 }
5516
5517 // Extract scalar constant bits.
5518 if (auto *Cst = dyn_cast<ConstantSDNode>(Op)) {
5519 APInt UndefSrcElts = APInt::getNullValue(1);
5520 SmallVector<APInt, 64> SrcEltBits(1, Cst->getAPIntValue());
5521 return CastBitData(UndefSrcElts, SrcEltBits);
5522 }
5523 if (auto *Cst = dyn_cast<ConstantFPSDNode>(Op)) {
5524 APInt UndefSrcElts = APInt::getNullValue(1);
5525 APInt RawBits = Cst->getValueAPF().bitcastToAPInt();
5526 SmallVector<APInt, 64> SrcEltBits(1, RawBits);
5527 return CastBitData(UndefSrcElts, SrcEltBits);
5528 }
5529
5530 // Extract constant bits from build vector.
5531 if (ISD::isBuildVectorOfConstantSDNodes(Op.getNode())) {
5532 unsigned SrcEltSizeInBits = VT.getScalarSizeInBits();
5533 unsigned NumSrcElts = SizeInBits / SrcEltSizeInBits;
5534
5535 APInt UndefSrcElts(NumSrcElts, 0);
5536 SmallVector<APInt, 64> SrcEltBits(NumSrcElts, APInt(SrcEltSizeInBits, 0));
5537 for (unsigned i = 0, e = Op.getNumOperands(); i != e; ++i) {
5538 const SDValue &Src = Op.getOperand(i);
5539 if (Src.isUndef()) {
5540 UndefSrcElts.setBit(i);
5541 continue;
5542 }
5543 auto *Cst = cast<ConstantSDNode>(Src);
5544 SrcEltBits[i] = Cst->getAPIntValue().zextOrTrunc(SrcEltSizeInBits);
5545 }
5546 return CastBitData(UndefSrcElts, SrcEltBits);
5547 }
5548
5549 // Extract constant bits from constant pool vector.
5550 if (auto *Cst = getTargetConstantFromNode(Op)) {
5551 Type *CstTy = Cst->getType();
5552 if (!CstTy->isVectorTy() || (SizeInBits != CstTy->getPrimitiveSizeInBits()))
5553 return false;
5554
5555 unsigned SrcEltSizeInBits = CstTy->getScalarSizeInBits();
5556 unsigned NumSrcElts = CstTy->getVectorNumElements();
5557
5558 APInt UndefSrcElts(NumSrcElts, 0);
5559 SmallVector<APInt, 64> SrcEltBits(NumSrcElts, APInt(SrcEltSizeInBits, 0));
5560 for (unsigned i = 0; i != NumSrcElts; ++i)
5561 if (!CollectConstantBits(Cst->getAggregateElement(i), SrcEltBits[i],
5562 UndefSrcElts, i))
5563 return false;
5564
5565 return CastBitData(UndefSrcElts, SrcEltBits);
5566 }
5567
5568 // Extract constant bits from a broadcasted constant pool scalar.
5569 if (Op.getOpcode() == X86ISD::VBROADCAST &&
5570 EltSizeInBits <= VT.getScalarSizeInBits()) {
5571 if (auto *Broadcast = getTargetConstantFromNode(Op.getOperand(0))) {
5572 unsigned SrcEltSizeInBits = Broadcast->getType()->getScalarSizeInBits();
5573 unsigned NumSrcElts = SizeInBits / SrcEltSizeInBits;
5574
5575 APInt UndefSrcElts(NumSrcElts, 0);
5576 SmallVector<APInt, 64> SrcEltBits(1, APInt(SrcEltSizeInBits, 0));
5577 if (CollectConstantBits(Broadcast, SrcEltBits[0], UndefSrcElts, 0)) {
5578 if (UndefSrcElts[0])
5579 UndefSrcElts.setBits(0, NumSrcElts);
5580 SrcEltBits.append(NumSrcElts - 1, SrcEltBits[0]);
5581 return CastBitData(UndefSrcElts, SrcEltBits);
5582 }
5583 }
5584 }
5585
5586 // Extract a rematerialized scalar constant insertion.
5587 if (Op.getOpcode() == X86ISD::VZEXT_MOVL &&
5588 Op.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
5589 isa<ConstantSDNode>(Op.getOperand(0).getOperand(0))) {
5590 unsigned SrcEltSizeInBits = VT.getScalarSizeInBits();
5591 unsigned NumSrcElts = SizeInBits / SrcEltSizeInBits;
5592
5593 APInt UndefSrcElts(NumSrcElts, 0);
5594 SmallVector<APInt, 64> SrcEltBits;
5595 auto *CN = cast<ConstantSDNode>(Op.getOperand(0).getOperand(0));
5596 SrcEltBits.push_back(CN->getAPIntValue().zextOrTrunc(SrcEltSizeInBits));
5597 SrcEltBits.append(NumSrcElts - 1, APInt(SrcEltSizeInBits, 0));
5598 return CastBitData(UndefSrcElts, SrcEltBits);
5599 }
5600
5601 return false;
5602}
5603
5604static bool getTargetShuffleMaskIndices(SDValue MaskNode,
5605 unsigned MaskEltSizeInBits,
5606 SmallVectorImpl<uint64_t> &RawMask) {
5607 APInt UndefElts;
5608 SmallVector<APInt, 64> EltBits;
5609
5610 // Extract the raw target constant bits.
5611 // FIXME: We currently don't support UNDEF bits or mask entries.
5612 if (!getTargetConstantBitsFromNode(MaskNode, MaskEltSizeInBits, UndefElts,
5613 EltBits, /* AllowWholeUndefs */ false,
5614 /* AllowPartialUndefs */ false))
5615 return false;
5616
5617 // Insert the extracted elements into the mask.
5618 for (APInt Elt : EltBits)
5619 RawMask.push_back(Elt.getZExtValue());
5620
5621 return true;
5622}
5623
5624/// Create a shuffle mask that matches the PACKSS/PACKUS truncation.
5625/// Note: This ignores saturation, so inputs must be checked first.
5626static void createPackShuffleMask(MVT VT, SmallVectorImpl<int> &Mask,
5627 bool Unary) {
5628 assert(Mask.empty() && "Expected an empty shuffle mask vector")(static_cast <bool> (Mask.empty() && "Expected an empty shuffle mask vector"
) ? void (0) : __assert_fail ("Mask.empty() && \"Expected an empty shuffle mask vector\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 5628, __extension__ __PRETTY_FUNCTION__))
;
5629 unsigned NumElts = VT.getVectorNumElements();
5630 unsigned NumLanes = VT.getSizeInBits() / 128;
5631 unsigned NumEltsPerLane = 128 / VT.getScalarSizeInBits();
5632 unsigned Offset = Unary ? 0 : NumElts;
5633
5634 for (unsigned Lane = 0; Lane != NumLanes; ++Lane) {
5635 for (unsigned Elt = 0; Elt != NumEltsPerLane; Elt += 2)
5636 Mask.push_back(Elt + (Lane * NumEltsPerLane));
5637 for (unsigned Elt = 0; Elt != NumEltsPerLane; Elt += 2)
5638 Mask.push_back(Elt + (Lane * NumEltsPerLane) + Offset);
5639 }
5640}
5641
5642/// Calculates the shuffle mask corresponding to the target-specific opcode.
5643/// If the mask could be calculated, returns it in \p Mask, returns the shuffle
5644/// operands in \p Ops, and returns true.
5645/// Sets \p IsUnary to true if only one source is used. Note that this will set
5646/// IsUnary for shuffles which use a single input multiple times, and in those
5647/// cases it will adjust the mask to only have indices within that single input.
5648/// It is an error to call this with non-empty Mask/Ops vectors.
5649static bool getTargetShuffleMask(SDNode *N, MVT VT, bool AllowSentinelZero,
5650 SmallVectorImpl<SDValue> &Ops,
5651 SmallVectorImpl<int> &Mask, bool &IsUnary) {
5652 unsigned NumElems = VT.getVectorNumElements();
5653 SDValue ImmN;
5654
5655 assert(Mask.empty() && "getTargetShuffleMask expects an empty Mask vector")(static_cast <bool> (Mask.empty() && "getTargetShuffleMask expects an empty Mask vector"
) ? void (0) : __assert_fail ("Mask.empty() && \"getTargetShuffleMask expects an empty Mask vector\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 5655, __extension__ __PRETTY_FUNCTION__))
;
5656 assert(Ops.empty() && "getTargetShuffleMask expects an empty Ops vector")(static_cast <bool> (Ops.empty() && "getTargetShuffleMask expects an empty Ops vector"
) ? void (0) : __assert_fail ("Ops.empty() && \"getTargetShuffleMask expects an empty Ops vector\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 5656, __extension__ __PRETTY_FUNCTION__))
;
5657
5658 IsUnary = false;
5659 bool IsFakeUnary = false;
5660 switch(N->getOpcode()) {
5661 case X86ISD::BLENDI:
5662 assert(N->getOperand(0).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(0).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(0).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 5662, __extension__ __PRETTY_FUNCTION__))
;
5663 assert(N->getOperand(1).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(1).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(1).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 5663, __extension__ __PRETTY_FUNCTION__))
;
5664 ImmN = N->getOperand(N->getNumOperands()-1);
5665 DecodeBLENDMask(NumElems, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5666 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5667 break;
5668 case X86ISD::SHUFP:
5669 assert(N->getOperand(0).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(0).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(0).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 5669, __extension__ __PRETTY_FUNCTION__))
;
5670 assert(N->getOperand(1).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(1).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(1).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 5670, __extension__ __PRETTY_FUNCTION__))
;
5671 ImmN = N->getOperand(N->getNumOperands()-1);
5672 DecodeSHUFPMask(NumElems, VT.getScalarSizeInBits(),
5673 cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5674 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5675 break;
5676 case X86ISD::INSERTPS:
5677 assert(N->getOperand(0).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(0).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(0).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 5677, __extension__ __PRETTY_FUNCTION__))
;
5678 assert(N->getOperand(1).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(1).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(1).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 5678, __extension__ __PRETTY_FUNCTION__))
;
5679 ImmN = N->getOperand(N->getNumOperands()-1);
5680 DecodeINSERTPSMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5681 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5682 break;
5683 case X86ISD::EXTRQI:
5684 assert(N->getOperand(0).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(0).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(0).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 5684, __extension__ __PRETTY_FUNCTION__))
;
5685 if (isa<ConstantSDNode>(N->getOperand(1)) &&
5686 isa<ConstantSDNode>(N->getOperand(2))) {
5687 int BitLen = N->getConstantOperandVal(1);
5688 int BitIdx = N->getConstantOperandVal(2);
5689 DecodeEXTRQIMask(NumElems, VT.getScalarSizeInBits(), BitLen, BitIdx,
5690 Mask);
5691 IsUnary = true;
5692 }
5693 break;
5694 case X86ISD::INSERTQI:
5695 assert(N->getOperand(0).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(0).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(0).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 5695, __extension__ __PRETTY_FUNCTION__))
;
5696 assert(N->getOperand(1).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(1).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(1).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 5696, __extension__ __PRETTY_FUNCTION__))
;
5697 if (isa<ConstantSDNode>(N->getOperand(2)) &&
5698 isa<ConstantSDNode>(N->getOperand(3))) {
5699 int BitLen = N->getConstantOperandVal(2);
5700 int BitIdx = N->getConstantOperandVal(3);
5701 DecodeINSERTQIMask(NumElems, VT.getScalarSizeInBits(), BitLen, BitIdx,
5702 Mask);
5703 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5704 }
5705 break;
5706 case X86ISD::UNPCKH:
5707 assert(N->getOperand(0).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(0).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(0).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 5707, __extension__ __PRETTY_FUNCTION__))
;
5708 assert(N->getOperand(1).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(1).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(1).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 5708, __extension__ __PRETTY_FUNCTION__))
;
5709 DecodeUNPCKHMask(NumElems, VT.getScalarSizeInBits(), Mask);
5710 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5711 break;
5712 case X86ISD::UNPCKL:
5713 assert(N->getOperand(0).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(0).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(0).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 5713, __extension__ __PRETTY_FUNCTION__))
;
5714 assert(N->getOperand(1).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(1).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(1).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 5714, __extension__ __PRETTY_FUNCTION__))
;
5715 DecodeUNPCKLMask(NumElems, VT.getScalarSizeInBits(), Mask);
5716 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5717 break;
5718 case X86ISD::MOVHLPS:
5719 assert(N->getOperand(0).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(0).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(0).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 5719, __extension__ __PRETTY_FUNCTION__))
;
5720 assert(N->getOperand(1).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(1).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(1).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 5720, __extension__ __PRETTY_FUNCTION__))
;
5721 DecodeMOVHLPSMask(NumElems, Mask);
5722 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5723 break;
5724 case X86ISD::MOVLHPS:
5725 assert(N->getOperand(0).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(0).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(0).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 5725, __extension__ __PRETTY_FUNCTION__))
;
5726 assert(N->getOperand(1).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(1).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(1).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 5726, __extension__ __PRETTY_FUNCTION__))
;
5727 DecodeMOVLHPSMask(NumElems, Mask);
5728 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5729 break;
5730 case X86ISD::PALIGNR:
5731 assert(VT.getScalarType() == MVT::i8 && "Byte vector expected")(static_cast <bool> (VT.getScalarType() == MVT::i8 &&
"Byte vector expected") ? void (0) : __assert_fail ("VT.getScalarType() == MVT::i8 && \"Byte vector expected\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 5731, __extension__ __PRETTY_FUNCTION__))
;
5732 assert(N->getOperand(0).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(0).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(0).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 5732, __extension__ __PRETTY_FUNCTION__))
;
5733 assert(N->getOperand(1).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(1).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(1).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 5733, __extension__ __PRETTY_FUNCTION__))
;
5734 ImmN = N->getOperand(N->getNumOperands()-1);
5735 DecodePALIGNRMask(NumElems, cast<ConstantSDNode>(ImmN)->getZExtValue(),
5736 Mask);
5737 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5738 Ops.push_back(N->getOperand(1));
5739 Ops.push_back(N->getOperand(0));
5740 break;
5741 case X86ISD::VSHLDQ:
5742 assert(VT.getScalarType() == MVT::i8 && "Byte vector expected")(static_cast <bool> (VT.getScalarType() == MVT::i8 &&
"Byte vector expected") ? void (0) : __assert_fail ("VT.getScalarType() == MVT::i8 && \"Byte vector expected\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 5742, __extension__ __PRETTY_FUNCTION__))
;
5743 assert(N->getOperand(0).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(0).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(0).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 5743, __extension__ __PRETTY_FUNCTION__))
;
5744 ImmN = N->getOperand(N->getNumOperands() - 1);
5745 DecodePSLLDQMask(NumElems, cast<ConstantSDNode>(ImmN)->getZExtValue(),
5746 Mask);
5747 IsUnary = true;
5748 break;
5749 case X86ISD::VSRLDQ:
5750 assert(VT.getScalarType() == MVT::i8 && "Byte vector expected")(static_cast <bool> (VT.getScalarType() == MVT::i8 &&
"Byte vector expected") ? void (0) : __assert_fail ("VT.getScalarType() == MVT::i8 && \"Byte vector expected\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 5750, __extension__ __PRETTY_FUNCTION__))
;
5751 assert(N->getOperand(0).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(0).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(0).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 5751, __extension__ __PRETTY_FUNCTION__))
;
5752 ImmN = N->getOperand(N->getNumOperands() - 1);
5753 DecodePSRLDQMask(NumElems, cast<ConstantSDNode>(ImmN)->getZExtValue(),
5754 Mask);
5755 IsUnary = true;
5756 break;
5757 case X86ISD::PSHUFD:
5758 case X86ISD::VPERMILPI:
5759 assert(N->getOperand(0).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(0).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(0).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 5759, __extension__ __PRETTY_FUNCTION__))
;
5760 ImmN = N->getOperand(N->getNumOperands()-1);
5761 DecodePSHUFMask(NumElems, VT.getScalarSizeInBits(),
5762 cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5763 IsUnary = true;
5764 break;
5765 case X86ISD::PSHUFHW:
5766 assert(N->getOperand(0).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(0).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(0).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 5766, __extension__ __PRETTY_FUNCTION__))
;
5767 ImmN = N->getOperand(N->getNumOperands()-1);
5768 DecodePSHUFHWMask(NumElems, cast<ConstantSDNode>(ImmN)->getZExtValue(),
5769 Mask);
5770 IsUnary = true;
5771 break;
5772 case X86ISD::PSHUFLW:
5773 assert(N->getOperand(0).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(0).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(0).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 5773, __extension__ __PRETTY_FUNCTION__))
;
5774 ImmN = N->getOperand(N->getNumOperands()-1);
5775 DecodePSHUFLWMask(NumElems, cast<ConstantSDNode>(ImmN)->getZExtValue(),
5776 Mask);
5777 IsUnary = true;
5778 break;
5779 case X86ISD::VZEXT_MOVL:
5780 assert(N->getOperand(0).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(0).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(0).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 5780, __extension__ __PRETTY_FUNCTION__))
;
5781 DecodeZeroMoveLowMask(NumElems, Mask);
5782 IsUnary = true;
5783 break;
5784 case X86ISD::VBROADCAST: {
5785 SDValue N0 = N->getOperand(0);
5786 // See if we're broadcasting from index 0 of an EXTRACT_SUBVECTOR. If so,
5787 // add the pre-extracted value to the Ops vector.
5788 if (N0.getOpcode() == ISD::EXTRACT_SUBVECTOR &&
5789 N0.getOperand(0).getValueType() == VT &&
5790 N0.getConstantOperandVal(1) == 0)
5791 Ops.push_back(N0.getOperand(0));
5792
5793 // We only decode broadcasts of same-sized vectors, unless the broadcast
5794 // came from an extract from the original width. If we found one, we
5795 // pushed it the Ops vector above.
5796 if (N0.getValueType() == VT || !Ops.empty()) {
5797 DecodeVectorBroadcast(NumElems, Mask);
5798 IsUnary = true;
5799 break;
5800 }
5801 return false;
5802 }
5803 case X86ISD::VPERMILPV: {
5804 assert(N->getOperand(0).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(0).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(0).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 5804, __extension__ __PRETTY_FUNCTION__))
;
5805 IsUnary = true;
5806 SDValue MaskNode = N->getOperand(1);
5807 unsigned MaskEltSize = VT.getScalarSizeInBits();
5808 SmallVector<uint64_t, 32> RawMask;
5809 if (getTargetShuffleMaskIndices(MaskNode, MaskEltSize, RawMask)) {
5810 DecodeVPERMILPMask(NumElems, VT.getScalarSizeInBits(), RawMask, Mask);
5811 break;
5812 }
5813 if (auto *C = getTargetConstantFromNode(MaskNode)) {
5814 DecodeVPERMILPMask(C, MaskEltSize, Mask);
5815 break;
5816 }
5817 return false;
5818 }
5819 case X86ISD::PSHUFB: {
5820 assert(VT.getScalarType() == MVT::i8 && "Byte vector expected")(static_cast <bool> (VT.getScalarType() == MVT::i8 &&
"Byte vector expected") ? void (0) : __assert_fail ("VT.getScalarType() == MVT::i8 && \"Byte vector expected\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 5820, __extension__ __PRETTY_FUNCTION__))
;
5821 assert(N->getOperand(0).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(0).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(0).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 5821, __extension__ __PRETTY_FUNCTION__))
;
5822 assert(N->getOperand(1).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(1).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(1).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86ISelLowering.cpp"
, 5822, __extension__ __PRETTY_FUNCTION__))
;
5823 IsUnary = true;
5824 SDValue MaskNode = N->getOperand(1);
5825 SmallVector<uint64_t, 32> RawMask;
5826 if (getTargetShuffleMaskIndices(MaskNode, 8, RawMask)) {
5827 DecodePSHUFBMask(RawMask, Mask);