Bug Summary

File:lib/Target/X86/X86ISelLowering.cpp
Warning:line 125, column 3
Potential memory leak

Annotated Source Code

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clang -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name X86ISelLowering.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-eagerly-assume -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -mrelocation-model pic -pic-level 2 -mthread-model posix -fmath-errno -masm-verbose -mconstructor-aliases -munwind-tables -fuse-init-array -target-cpu x86-64 -dwarf-column-info -debugger-tuning=gdb -momit-leaf-frame-pointer -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-7/lib/clang/7.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-7~svn326246/build-llvm/lib/Target/X86 -I /build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86 -I /build/llvm-toolchain-snapshot-7~svn326246/build-llvm/include -I /build/llvm-toolchain-snapshot-7~svn326246/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/7.3.0/../../../../include/c++/7.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/7.3.0/../../../../include/x86_64-linux-gnu/c++/7.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/7.3.0/../../../../include/x86_64-linux-gnu/c++/7.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/7.3.0/../../../../include/c++/7.3.0/backward -internal-isystem /usr/include/clang/7.0.0/include/ -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-7/lib/clang/7.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++11 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-7~svn326246/build-llvm/lib/Target/X86 -ferror-limit 19 -fmessage-length 0 -fvisibility-inlines-hidden -fobjc-runtime=gcc -fdiagnostics-show-option -vectorize-loops -vectorize-slp -analyzer-checker optin.performance.Padding -analyzer-output=html -analyzer-config stable-report-filename=true -o /tmp/scan-build-2018-02-28-041547-14988-1 -x c++ /build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp

/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp

1//===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that X86 uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#include "X86ISelLowering.h"
16#include "Utils/X86ShuffleDecode.h"
17#include "X86CallingConv.h"
18#include "X86FrameLowering.h"
19#include "X86InstrBuilder.h"
20#include "X86IntrinsicsInfo.h"
21#include "X86MachineFunctionInfo.h"
22#include "X86ShuffleDecodeConstantPool.h"
23#include "X86TargetMachine.h"
24#include "X86TargetObjectFile.h"
25#include "llvm/ADT/SmallBitVector.h"
26#include "llvm/ADT/SmallSet.h"
27#include "llvm/ADT/Statistic.h"
28#include "llvm/ADT/StringExtras.h"
29#include "llvm/ADT/StringSwitch.h"
30#include "llvm/Analysis/EHPersonalities.h"
31#include "llvm/CodeGen/IntrinsicLowering.h"
32#include "llvm/CodeGen/MachineFrameInfo.h"
33#include "llvm/CodeGen/MachineFunction.h"
34#include "llvm/CodeGen/MachineInstrBuilder.h"
35#include "llvm/CodeGen/MachineJumpTableInfo.h"
36#include "llvm/CodeGen/MachineModuleInfo.h"
37#include "llvm/CodeGen/MachineRegisterInfo.h"
38#include "llvm/CodeGen/TargetLowering.h"
39#include "llvm/CodeGen/WinEHFuncInfo.h"
40#include "llvm/IR/CallSite.h"
41#include "llvm/IR/CallingConv.h"
42#include "llvm/IR/Constants.h"
43#include "llvm/IR/DerivedTypes.h"
44#include "llvm/IR/DiagnosticInfo.h"
45#include "llvm/IR/Function.h"
46#include "llvm/IR/GlobalAlias.h"
47#include "llvm/IR/GlobalVariable.h"
48#include "llvm/IR/Instructions.h"
49#include "llvm/IR/Intrinsics.h"
50#include "llvm/MC/MCAsmInfo.h"
51#include "llvm/MC/MCContext.h"
52#include "llvm/MC/MCExpr.h"
53#include "llvm/MC/MCSymbol.h"
54#include "llvm/Support/CommandLine.h"
55#include "llvm/Support/Debug.h"
56#include "llvm/Support/ErrorHandling.h"
57#include "llvm/Support/KnownBits.h"
58#include "llvm/Support/MathExtras.h"
59#include "llvm/Target/TargetOptions.h"
60#include <algorithm>
61#include <bitset>
62#include <cctype>
63#include <numeric>
64using namespace llvm;
65
66#define DEBUG_TYPE"x86-isel" "x86-isel"
67
68STATISTIC(NumTailCalls, "Number of tail calls")static llvm::Statistic NumTailCalls = {"x86-isel", "NumTailCalls"
, "Number of tail calls", {0}, {false}}
;
69
70static cl::opt<bool> ExperimentalVectorWideningLegalization(
71 "x86-experimental-vector-widening-legalization", cl::init(false),
72 cl::desc("Enable an experimental vector type legalization through widening "
73 "rather than promotion."),
74 cl::Hidden);
75
76static cl::opt<int> ExperimentalPrefLoopAlignment(
77 "x86-experimental-pref-loop-alignment", cl::init(4),
78 cl::desc("Sets the preferable loop alignment for experiments "
79 "(the last x86-experimental-pref-loop-alignment bits"
80 " of the loop header PC will be 0)."),
81 cl::Hidden);
82
83static cl::opt<bool> MulConstantOptimization(
84 "mul-constant-optimization", cl::init(true),
85 cl::desc("Replace 'mul x, Const' with more effective instructions like "
86 "SHIFT, LEA, etc."),
87 cl::Hidden);
88
89/// Call this when the user attempts to do something unsupported, like
90/// returning a double without SSE2 enabled on x86_64. This is not fatal, unlike
91/// report_fatal_error, so calling code should attempt to recover without
92/// crashing.
93static void errorUnsupported(SelectionDAG &DAG, const SDLoc &dl,
94 const char *Msg) {
95 MachineFunction &MF = DAG.getMachineFunction();
96 DAG.getContext()->diagnose(
97 DiagnosticInfoUnsupported(MF.getFunction(), Msg, dl.getDebugLoc()));
98}
99
100X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
101 const X86Subtarget &STI)
102 : TargetLowering(TM), Subtarget(STI) {
103 bool UseX87 = !Subtarget.useSoftFloat() && Subtarget.hasX87();
104 X86ScalarSSEf64 = Subtarget.hasSSE2();
105 X86ScalarSSEf32 = Subtarget.hasSSE1();
106 MVT PtrVT = MVT::getIntegerVT(8 * TM.getPointerSize());
107
108 // Set up the TargetLowering object.
109
110 // X86 is weird. It always uses i8 for shift amounts and setcc results.
111 setBooleanContents(ZeroOrOneBooleanContent);
112 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
113 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
114
115 // For 64-bit, since we have so many registers, use the ILP scheduler.
116 // For 32-bit, use the register pressure specific scheduling.
117 // For Atom, always use ILP scheduling.
118 if (Subtarget.isAtom())
119 setSchedulingPreference(Sched::ILP);
120 else if (Subtarget.is64Bit())
121 setSchedulingPreference(Sched::ILP);
122 else
123 setSchedulingPreference(Sched::RegPressure);
124 const X86RegisterInfo *RegInfo = Subtarget.getRegisterInfo();
125 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
126
127 // Bypass expensive divides and use cheaper ones.
128 if (TM.getOptLevel() >= CodeGenOpt::Default) {
129 if (Subtarget.hasSlowDivide32())
130 addBypassSlowDiv(32, 8);
131 if (Subtarget.hasSlowDivide64() && Subtarget.is64Bit())
132 addBypassSlowDiv(64, 32);
133 }
134
135 if (Subtarget.isTargetKnownWindowsMSVC() ||
136 Subtarget.isTargetWindowsItanium()) {
137 // Setup Windows compiler runtime calls.
138 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
139 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
140 setLibcallName(RTLIB::SREM_I64, "_allrem");
141 setLibcallName(RTLIB::UREM_I64, "_aullrem");
142 setLibcallName(RTLIB::MUL_I64, "_allmul");
143 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
144 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
145 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
146 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
147 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
148 }
149
150 if (Subtarget.isTargetDarwin()) {
151 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
152 setUseUnderscoreSetJmp(false);
153 setUseUnderscoreLongJmp(false);
154 } else if (Subtarget.isTargetWindowsGNU()) {
155 // MS runtime is weird: it exports _setjmp, but longjmp!
156 setUseUnderscoreSetJmp(true);
157 setUseUnderscoreLongJmp(false);
158 } else {
159 setUseUnderscoreSetJmp(true);
160 setUseUnderscoreLongJmp(true);
161 }
162
163 // Set up the register classes.
164 addRegisterClass(MVT::i8, &X86::GR8RegClass);
165 addRegisterClass(MVT::i16, &X86::GR16RegClass);
166 addRegisterClass(MVT::i32, &X86::GR32RegClass);
167 if (Subtarget.is64Bit())
168 addRegisterClass(MVT::i64, &X86::GR64RegClass);
169
170 for (MVT VT : MVT::integer_valuetypes())
171 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
172
173 // We don't accept any truncstore of integer registers.
174 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
175 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
176 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
177 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
178 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
179 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
180
181 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
182
183 // SETOEQ and SETUNE require checking two conditions.
184 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
185 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
186 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
187 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
188 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
189 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
190
191 // Integer absolute.
192 if (Subtarget.hasCMov()) {
193 setOperationAction(ISD::ABS , MVT::i16 , Custom);
194 setOperationAction(ISD::ABS , MVT::i32 , Custom);
195 if (Subtarget.is64Bit())
196 setOperationAction(ISD::ABS , MVT::i64 , Custom);
197 }
198
199 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
200 // operation.
201 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
202 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
203 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
204
205 if (Subtarget.is64Bit()) {
206 if (!Subtarget.useSoftFloat() && Subtarget.hasAVX512())
207 // f32/f64 are legal, f80 is custom.
208 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
209 else
210 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
211 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
212 } else if (!Subtarget.useSoftFloat()) {
213 // We have an algorithm for SSE2->double, and we turn this into a
214 // 64-bit FILD followed by conditional FADD for other targets.
215 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
216 // We have an algorithm for SSE2, and we turn this into a 64-bit
217 // FILD or VCVTUSI2SS/SD for other targets.
218 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
219 }
220
221 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
222 // this operation.
223 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
224 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
225
226 if (!Subtarget.useSoftFloat()) {
227 // SSE has no i16 to fp conversion, only i32.
228 if (X86ScalarSSEf32) {
229 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
230 // f32 and f64 cases are Legal, f80 case is not
231 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
232 } else {
233 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
234 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
235 }
236 } else {
237 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
238 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
239 }
240
241 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
242 // this operation.
243 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
244 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
245
246 if (!Subtarget.useSoftFloat()) {
247 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
248 // are Legal, f80 is custom lowered.
249 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
250 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
251
252 if (X86ScalarSSEf32) {
253 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
254 // f32 and f64 cases are Legal, f80 case is not
255 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
256 } else {
257 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
258 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
259 }
260 } else {
261 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
262 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Expand);
263 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Expand);
264 }
265
266 // Handle FP_TO_UINT by promoting the destination to a larger signed
267 // conversion.
268 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
269 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
270 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
271
272 if (Subtarget.is64Bit()) {
273 if (!Subtarget.useSoftFloat() && Subtarget.hasAVX512()) {
274 // FP_TO_UINT-i32/i64 is legal for f32/f64, but custom for f80.
275 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
276 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
277 } else {
278 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
279 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
280 }
281 } else if (!Subtarget.useSoftFloat()) {
282 // Since AVX is a superset of SSE3, only check for SSE here.
283 if (Subtarget.hasSSE1() && !Subtarget.hasSSE3())
284 // Expand FP_TO_UINT into a select.
285 // FIXME: We would like to use a Custom expander here eventually to do
286 // the optimal thing for SSE vs. the default expansion in the legalizer.
287 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
288 else
289 // With AVX512 we can use vcvts[ds]2usi for f32/f64->i32, f80 is custom.
290 // With SSE3 we can use fisttpll to convert to a signed i64; without
291 // SSE, we're stuck with a fistpll.
292 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
293
294 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
295 }
296
297 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
298 if (!X86ScalarSSEf64) {
299 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
300 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
301 if (Subtarget.is64Bit()) {
302 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
303 // Without SSE, i64->f64 goes through memory.
304 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
305 }
306 } else if (!Subtarget.is64Bit())
307 setOperationAction(ISD::BITCAST , MVT::i64 , Custom);
308
309 // Scalar integer divide and remainder are lowered to use operations that
310 // produce two results, to match the available instructions. This exposes
311 // the two-result form to trivial CSE, which is able to combine x/y and x%y
312 // into a single instruction.
313 //
314 // Scalar integer multiply-high is also lowered to use two-result
315 // operations, to match the available instructions. However, plain multiply
316 // (low) operations are left as Legal, as there are single-result
317 // instructions for this in x86. Using the two-result multiply instructions
318 // when both high and low results are needed must be arranged by dagcombine.
319 for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
320 setOperationAction(ISD::MULHS, VT, Expand);
321 setOperationAction(ISD::MULHU, VT, Expand);
322 setOperationAction(ISD::SDIV, VT, Expand);
323 setOperationAction(ISD::UDIV, VT, Expand);
324 setOperationAction(ISD::SREM, VT, Expand);
325 setOperationAction(ISD::UREM, VT, Expand);
326 }
327
328 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
329 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
330 for (auto VT : { MVT::f32, MVT::f64, MVT::f80, MVT::f128,
331 MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
332 setOperationAction(ISD::BR_CC, VT, Expand);
333 setOperationAction(ISD::SELECT_CC, VT, Expand);
334 }
335 if (Subtarget.is64Bit())
336 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
337 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
338 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
339 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
340 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
341
342 setOperationAction(ISD::FREM , MVT::f32 , Expand);
343 setOperationAction(ISD::FREM , MVT::f64 , Expand);
344 setOperationAction(ISD::FREM , MVT::f80 , Expand);
345 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
346
347 // Promote the i8 variants and force them on up to i32 which has a shorter
348 // encoding.
349 setOperationPromotedToType(ISD::CTTZ , MVT::i8 , MVT::i32);
350 setOperationPromotedToType(ISD::CTTZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
351 if (!Subtarget.hasBMI()) {
352 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
353 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
354 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Legal);
355 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Legal);
356 if (Subtarget.is64Bit()) {
357 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
358 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Legal);
359 }
360 }
361
362 if (Subtarget.hasLZCNT()) {
363 // When promoting the i8 variants, force them to i32 for a shorter
364 // encoding.
365 setOperationPromotedToType(ISD::CTLZ , MVT::i8 , MVT::i32);
366 setOperationPromotedToType(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
367 } else {
368 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
369 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
370 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
371 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
372 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
373 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
374 if (Subtarget.is64Bit()) {
375 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
376 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
377 }
378 }
379
380 // Special handling for half-precision floating point conversions.
381 // If we don't have F16C support, then lower half float conversions
382 // into library calls.
383 if (Subtarget.useSoftFloat() || !Subtarget.hasF16C()) {
384 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
385 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
386 }
387
388 // There's never any support for operations beyond MVT::f32.
389 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
390 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
391 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
392 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
393
394 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
395 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
396 setLoadExtAction(ISD::EXTLOAD, MVT::f80, MVT::f16, Expand);
397 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
398 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
399 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
400
401 if (Subtarget.hasPOPCNT()) {
402 setOperationPromotedToType(ISD::CTPOP, MVT::i8, MVT::i32);
403 } else {
404 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
405 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
406 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
407 if (Subtarget.is64Bit())
408 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
409 }
410
411 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
412
413 if (!Subtarget.hasMOVBE())
414 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
415
416 // These should be promoted to a larger select which is supported.
417 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
418 // X86 wants to expand cmov itself.
419 for (auto VT : { MVT::f32, MVT::f64, MVT::f80, MVT::f128 }) {
420 setOperationAction(ISD::SELECT, VT, Custom);
421 setOperationAction(ISD::SETCC, VT, Custom);
422 }
423 for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
424 if (VT == MVT::i64 && !Subtarget.is64Bit())
425 continue;
426 setOperationAction(ISD::SELECT, VT, Custom);
427 setOperationAction(ISD::SETCC, VT, Custom);
428 }
429
430 // Custom action for SELECT MMX and expand action for SELECT_CC MMX
431 setOperationAction(ISD::SELECT, MVT::x86mmx, Custom);
432 setOperationAction(ISD::SELECT_CC, MVT::x86mmx, Expand);
433
434 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
435 // NOTE: EH_SJLJ_SETJMP/_LONGJMP are not recommended, since
436 // LLVM/Clang supports zero-cost DWARF and SEH exception handling.
437 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
438 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
439 setOperationAction(ISD::EH_SJLJ_SETUP_DISPATCH, MVT::Other, Custom);
440 if (TM.Options.ExceptionModel == ExceptionHandling::SjLj)
441 setLibcallName(RTLIB::UNWIND_RESUME, "_Unwind_SjLj_Resume");
442
443 // Darwin ABI issue.
444 for (auto VT : { MVT::i32, MVT::i64 }) {
445 if (VT == MVT::i64 && !Subtarget.is64Bit())
446 continue;
447 setOperationAction(ISD::ConstantPool , VT, Custom);
448 setOperationAction(ISD::JumpTable , VT, Custom);
449 setOperationAction(ISD::GlobalAddress , VT, Custom);
450 setOperationAction(ISD::GlobalTLSAddress, VT, Custom);
451 setOperationAction(ISD::ExternalSymbol , VT, Custom);
452 setOperationAction(ISD::BlockAddress , VT, Custom);
453 }
454
455 // 64-bit shl, sra, srl (iff 32-bit x86)
456 for (auto VT : { MVT::i32, MVT::i64 }) {
457 if (VT == MVT::i64 && !Subtarget.is64Bit())
458 continue;
459 setOperationAction(ISD::SHL_PARTS, VT, Custom);
460 setOperationAction(ISD::SRA_PARTS, VT, Custom);
461 setOperationAction(ISD::SRL_PARTS, VT, Custom);
462 }
463
464 if (Subtarget.hasSSEPrefetch() || Subtarget.has3DNow())
465 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
466
467 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
468
469 // Expand certain atomics
470 for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
471 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
472 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
473 setOperationAction(ISD::ATOMIC_LOAD_ADD, VT, Custom);
474 setOperationAction(ISD::ATOMIC_LOAD_OR, VT, Custom);
475 setOperationAction(ISD::ATOMIC_LOAD_XOR, VT, Custom);
476 setOperationAction(ISD::ATOMIC_LOAD_AND, VT, Custom);
477 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
478 }
479
480 if (Subtarget.hasCmpxchg16b()) {
481 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
482 }
483
484 // FIXME - use subtarget debug flags
485 if (!Subtarget.isTargetDarwin() && !Subtarget.isTargetELF() &&
486 !Subtarget.isTargetCygMing() && !Subtarget.isTargetWin64() &&
487 TM.Options.ExceptionModel != ExceptionHandling::SjLj) {
488 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
489 }
490
491 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
492 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
493
494 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
495 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
496
497 setOperationAction(ISD::TRAP, MVT::Other, Legal);
498 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
499
500 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
501 setOperationAction(ISD::VASTART , MVT::Other, Custom);
502 setOperationAction(ISD::VAEND , MVT::Other, Expand);
503 bool Is64Bit = Subtarget.is64Bit();
504 setOperationAction(ISD::VAARG, MVT::Other, Is64Bit ? Custom : Expand);
505 setOperationAction(ISD::VACOPY, MVT::Other, Is64Bit ? Custom : Expand);
506
507 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
508 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
509
510 setOperationAction(ISD::DYNAMIC_STACKALLOC, PtrVT, Custom);
511
512 // GC_TRANSITION_START and GC_TRANSITION_END need custom lowering.
513 setOperationAction(ISD::GC_TRANSITION_START, MVT::Other, Custom);
514 setOperationAction(ISD::GC_TRANSITION_END, MVT::Other, Custom);
515
516 if (!Subtarget.useSoftFloat() && X86ScalarSSEf64) {
517 // f32 and f64 use SSE.
518 // Set up the FP register classes.
519 addRegisterClass(MVT::f32, Subtarget.hasAVX512() ? &X86::FR32XRegClass
520 : &X86::FR32RegClass);
521 addRegisterClass(MVT::f64, Subtarget.hasAVX512() ? &X86::FR64XRegClass
522 : &X86::FR64RegClass);
523
524 for (auto VT : { MVT::f32, MVT::f64 }) {
525 // Use ANDPD to simulate FABS.
526 setOperationAction(ISD::FABS, VT, Custom);
527
528 // Use XORP to simulate FNEG.
529 setOperationAction(ISD::FNEG, VT, Custom);
530
531 // Use ANDPD and ORPD to simulate FCOPYSIGN.
532 setOperationAction(ISD::FCOPYSIGN, VT, Custom);
533
534 // We don't support sin/cos/fmod
535 setOperationAction(ISD::FSIN , VT, Expand);
536 setOperationAction(ISD::FCOS , VT, Expand);
537 setOperationAction(ISD::FSINCOS, VT, Expand);
538 }
539
540 // Lower this to MOVMSK plus an AND.
541 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
542 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
543
544 // Expand FP immediates into loads from the stack, except for the special
545 // cases we handle.
546 addLegalFPImmediate(APFloat(+0.0)); // xorpd
547 addLegalFPImmediate(APFloat(+0.0f)); // xorps
548 } else if (UseX87 && X86ScalarSSEf32) {
549 // Use SSE for f32, x87 for f64.
550 // Set up the FP register classes.
551 addRegisterClass(MVT::f32, &X86::FR32RegClass);
552 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
553
554 // Use ANDPS to simulate FABS.
555 setOperationAction(ISD::FABS , MVT::f32, Custom);
556
557 // Use XORP to simulate FNEG.
558 setOperationAction(ISD::FNEG , MVT::f32, Custom);
559
560 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
561
562 // Use ANDPS and ORPS to simulate FCOPYSIGN.
563 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
564 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
565
566 // We don't support sin/cos/fmod
567 setOperationAction(ISD::FSIN , MVT::f32, Expand);
568 setOperationAction(ISD::FCOS , MVT::f32, Expand);
569 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
570
571 // Special cases we handle for FP constants.
572 addLegalFPImmediate(APFloat(+0.0f)); // xorps
573 addLegalFPImmediate(APFloat(+0.0)); // FLD0
574 addLegalFPImmediate(APFloat(+1.0)); // FLD1
575 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
576 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
577
578 // Always expand sin/cos functions even though x87 has an instruction.
579 setOperationAction(ISD::FSIN , MVT::f64, Expand);
580 setOperationAction(ISD::FCOS , MVT::f64, Expand);
581 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
582 } else if (UseX87) {
583 // f32 and f64 in x87.
584 // Set up the FP register classes.
585 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
586 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
587
588 for (auto VT : { MVT::f32, MVT::f64 }) {
589 setOperationAction(ISD::UNDEF, VT, Expand);
590 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
591
592 // Always expand sin/cos functions even though x87 has an instruction.
593 setOperationAction(ISD::FSIN , VT, Expand);
594 setOperationAction(ISD::FCOS , VT, Expand);
595 setOperationAction(ISD::FSINCOS, VT, Expand);
596 }
597 addLegalFPImmediate(APFloat(+0.0)); // FLD0
598 addLegalFPImmediate(APFloat(+1.0)); // FLD1
599 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
600 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
601 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
602 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
603 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
604 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
605 }
606
607 // We don't support FMA.
608 setOperationAction(ISD::FMA, MVT::f64, Expand);
609 setOperationAction(ISD::FMA, MVT::f32, Expand);
610
611 // Long double always uses X87, except f128 in MMX.
612 if (UseX87) {
613 if (Subtarget.is64Bit() && Subtarget.hasMMX()) {
614 addRegisterClass(MVT::f128, &X86::FR128RegClass);
615 ValueTypeActions.setTypeAction(MVT::f128, TypeSoftenFloat);
616 setOperationAction(ISD::FABS , MVT::f128, Custom);
617 setOperationAction(ISD::FNEG , MVT::f128, Custom);
618 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Custom);
619 }
620
621 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
622 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
623 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
624 {
625 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended());
626 addLegalFPImmediate(TmpFlt); // FLD0
627 TmpFlt.changeSign();
628 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
629
630 bool ignored;
631 APFloat TmpFlt2(+1.0);
632 TmpFlt2.convert(APFloat::x87DoubleExtended(), APFloat::rmNearestTiesToEven,
633 &ignored);
634 addLegalFPImmediate(TmpFlt2); // FLD1
635 TmpFlt2.changeSign();
636 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
637 }
638
639 // Always expand sin/cos functions even though x87 has an instruction.
640 setOperationAction(ISD::FSIN , MVT::f80, Expand);
641 setOperationAction(ISD::FCOS , MVT::f80, Expand);
642 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
643
644 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
645 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
646 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
647 setOperationAction(ISD::FRINT, MVT::f80, Expand);
648 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
649 setOperationAction(ISD::FMA, MVT::f80, Expand);
650 }
651
652 // Always use a library call for pow.
653 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
654 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
655 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
656
657 setOperationAction(ISD::FLOG, MVT::f80, Expand);
658 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
659 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
660 setOperationAction(ISD::FEXP, MVT::f80, Expand);
661 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
662 setOperationAction(ISD::FMINNUM, MVT::f80, Expand);
663 setOperationAction(ISD::FMAXNUM, MVT::f80, Expand);
664
665 // Some FP actions are always expanded for vector types.
666 for (auto VT : { MVT::v4f32, MVT::v8f32, MVT::v16f32,
667 MVT::v2f64, MVT::v4f64, MVT::v8f64 }) {
668 setOperationAction(ISD::FSIN, VT, Expand);
669 setOperationAction(ISD::FSINCOS, VT, Expand);
670 setOperationAction(ISD::FCOS, VT, Expand);
671 setOperationAction(ISD::FREM, VT, Expand);
672 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
673 setOperationAction(ISD::FPOW, VT, Expand);
674 setOperationAction(ISD::FLOG, VT, Expand);
675 setOperationAction(ISD::FLOG2, VT, Expand);
676 setOperationAction(ISD::FLOG10, VT, Expand);
677 setOperationAction(ISD::FEXP, VT, Expand);
678 setOperationAction(ISD::FEXP2, VT, Expand);
679 }
680
681 // First set operation action for all vector types to either promote
682 // (for widening) or expand (for scalarization). Then we will selectively
683 // turn on ones that can be effectively codegen'd.
684 for (MVT VT : MVT::vector_valuetypes()) {
685 setOperationAction(ISD::SDIV, VT, Expand);
686 setOperationAction(ISD::UDIV, VT, Expand);
687 setOperationAction(ISD::SREM, VT, Expand);
688 setOperationAction(ISD::UREM, VT, Expand);
689 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
690 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
691 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
692 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
693 setOperationAction(ISD::FMA, VT, Expand);
694 setOperationAction(ISD::FFLOOR, VT, Expand);
695 setOperationAction(ISD::FCEIL, VT, Expand);
696 setOperationAction(ISD::FTRUNC, VT, Expand);
697 setOperationAction(ISD::FRINT, VT, Expand);
698 setOperationAction(ISD::FNEARBYINT, VT, Expand);
699 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
700 setOperationAction(ISD::MULHS, VT, Expand);
701 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
702 setOperationAction(ISD::MULHU, VT, Expand);
703 setOperationAction(ISD::SDIVREM, VT, Expand);
704 setOperationAction(ISD::UDIVREM, VT, Expand);
705 setOperationAction(ISD::CTPOP, VT, Expand);
706 setOperationAction(ISD::CTTZ, VT, Expand);
707 setOperationAction(ISD::CTLZ, VT, Expand);
708 setOperationAction(ISD::ROTL, VT, Expand);
709 setOperationAction(ISD::ROTR, VT, Expand);
710 setOperationAction(ISD::BSWAP, VT, Expand);
711 setOperationAction(ISD::SETCC, VT, Expand);
712 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
713 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
714 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
715 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
716 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
717 setOperationAction(ISD::TRUNCATE, VT, Expand);
718 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
719 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
720 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
721 setOperationAction(ISD::SELECT_CC, VT, Expand);
722 for (MVT InnerVT : MVT::vector_valuetypes()) {
723 setTruncStoreAction(InnerVT, VT, Expand);
724
725 setLoadExtAction(ISD::SEXTLOAD, InnerVT, VT, Expand);
726 setLoadExtAction(ISD::ZEXTLOAD, InnerVT, VT, Expand);
727
728 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like
729 // types, we have to deal with them whether we ask for Expansion or not.
730 // Setting Expand causes its own optimisation problems though, so leave
731 // them legal.
732 if (VT.getVectorElementType() == MVT::i1)
733 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
734
735 // EXTLOAD for MVT::f16 vectors is not legal because f16 vectors are
736 // split/scalarized right now.
737 if (VT.getVectorElementType() == MVT::f16)
738 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
739 }
740 }
741
742 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
743 // with -msoft-float, disable use of MMX as well.
744 if (!Subtarget.useSoftFloat() && Subtarget.hasMMX()) {
745 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
746 // No operations on x86mmx supported, everything uses intrinsics.
747 }
748
749 if (!Subtarget.useSoftFloat() && Subtarget.hasSSE1()) {
750 addRegisterClass(MVT::v4f32, Subtarget.hasVLX() ? &X86::VR128XRegClass
751 : &X86::VR128RegClass);
752
753 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
754 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
755 setOperationAction(ISD::FCOPYSIGN, MVT::v4f32, Custom);
756 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
757 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
758 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
759 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
760 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
761 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
762 }
763
764 if (!Subtarget.useSoftFloat() && Subtarget.hasSSE2()) {
765 addRegisterClass(MVT::v2f64, Subtarget.hasVLX() ? &X86::VR128XRegClass
766 : &X86::VR128RegClass);
767
768 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
769 // registers cannot be used even for integer operations.
770 addRegisterClass(MVT::v16i8, Subtarget.hasVLX() ? &X86::VR128XRegClass
771 : &X86::VR128RegClass);
772 addRegisterClass(MVT::v8i16, Subtarget.hasVLX() ? &X86::VR128XRegClass
773 : &X86::VR128RegClass);
774 addRegisterClass(MVT::v4i32, Subtarget.hasVLX() ? &X86::VR128XRegClass
775 : &X86::VR128RegClass);
776 addRegisterClass(MVT::v2i64, Subtarget.hasVLX() ? &X86::VR128XRegClass
777 : &X86::VR128RegClass);
778
779 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
780 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
781 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
782 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
783 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
784 setOperationAction(ISD::MULHU, MVT::v16i8, Custom);
785 setOperationAction(ISD::MULHS, MVT::v16i8, Custom);
786 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
787 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
788 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
789 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
790 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
791 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Custom);
792
793 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
794 setOperationAction(ISD::SMAX, VT, VT == MVT::v8i16 ? Legal : Custom);
795 setOperationAction(ISD::SMIN, VT, VT == MVT::v8i16 ? Legal : Custom);
796 setOperationAction(ISD::UMAX, VT, VT == MVT::v16i8 ? Legal : Custom);
797 setOperationAction(ISD::UMIN, VT, VT == MVT::v16i8 ? Legal : Custom);
798 }
799
800 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
801 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
802 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
803
804 // Provide custom widening for v2f32 setcc. This is really for VLX when
805 // setcc result type returns v2i1/v4i1 vector for v2f32/v4f32 leading to
806 // type legalization changing the result type to v4i1 during widening.
807 // It works fine for SSE2 and is probably faster so no need to qualify with
808 // VLX support.
809 setOperationAction(ISD::SETCC, MVT::v2i32, Custom);
810
811 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
812 setOperationAction(ISD::SETCC, VT, Custom);
813 setOperationAction(ISD::CTPOP, VT, Custom);
814 setOperationAction(ISD::CTTZ, VT, Custom);
815 }
816
817 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32 }) {
818 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
819 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
820 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
821 setOperationAction(ISD::VSELECT, VT, Custom);
822 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
823 }
824
825 // We support custom legalizing of sext and anyext loads for specific
826 // memory vector types which we can load as a scalar (or sequence of
827 // scalars) and extend in-register to a legal 128-bit vector type. For sext
828 // loads these must work with a single scalar load.
829 for (MVT VT : MVT::integer_vector_valuetypes()) {
830 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i8, Custom);
831 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i16, Custom);
832 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v8i8, Custom);
833 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Custom);
834 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Custom);
835 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i32, Custom);
836 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i8, Custom);
837 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Custom);
838 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8i8, Custom);
839 }
840
841 for (auto VT : { MVT::v2f64, MVT::v2i64 }) {
842 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
843 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
844 setOperationAction(ISD::VSELECT, VT, Custom);
845
846 if (VT == MVT::v2i64 && !Subtarget.is64Bit())
847 continue;
848
849 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
850 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
851 }
852
853 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
854 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32 }) {
855 setOperationPromotedToType(ISD::AND, VT, MVT::v2i64);
856 setOperationPromotedToType(ISD::OR, VT, MVT::v2i64);
857 setOperationPromotedToType(ISD::XOR, VT, MVT::v2i64);
858 setOperationPromotedToType(ISD::LOAD, VT, MVT::v2i64);
859 setOperationPromotedToType(ISD::SELECT, VT, MVT::v2i64);
860 }
861
862 // Custom lower v2i64 and v2f64 selects.
863 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
864 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
865
866 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
867 setOperationAction(ISD::FP_TO_SINT, MVT::v2i32, Custom);
868
869 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
870 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
871
872 setOperationAction(ISD::UINT_TO_FP, MVT::v2i32, Custom);
873
874 // Fast v2f32 UINT_TO_FP( v2i32 ) custom conversion.
875 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
876
877 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
878 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
879
880 for (MVT VT : MVT::fp_vector_valuetypes())
881 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2f32, Legal);
882
883 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
884 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
885 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
886 if (!Subtarget.hasAVX512())
887 setOperationAction(ISD::BITCAST, MVT::v16i1, Custom);
888
889 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v2i64, Custom);
890 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v4i32, Custom);
891 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v8i16, Custom);
892
893 // In the customized shift lowering, the legal v4i32/v2i64 cases
894 // in AVX2 will be recognized.
895 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
896 setOperationAction(ISD::SRL, VT, Custom);
897 setOperationAction(ISD::SHL, VT, Custom);
898 setOperationAction(ISD::SRA, VT, Custom);
899 }
900 }
901
902 if (!Subtarget.useSoftFloat() && Subtarget.hasSSSE3()) {
903 setOperationAction(ISD::ABS, MVT::v16i8, Legal);
904 setOperationAction(ISD::ABS, MVT::v8i16, Legal);
905 setOperationAction(ISD::ABS, MVT::v4i32, Legal);
906 setOperationAction(ISD::BITREVERSE, MVT::v16i8, Custom);
907 setOperationAction(ISD::CTLZ, MVT::v16i8, Custom);
908 setOperationAction(ISD::CTLZ, MVT::v8i16, Custom);
909 setOperationAction(ISD::CTLZ, MVT::v4i32, Custom);
910 setOperationAction(ISD::CTLZ, MVT::v2i64, Custom);
911 }
912
913 if (!Subtarget.useSoftFloat() && Subtarget.hasSSE41()) {
914 for (MVT RoundedTy : {MVT::f32, MVT::f64, MVT::v4f32, MVT::v2f64}) {
915 setOperationAction(ISD::FFLOOR, RoundedTy, Legal);
916 setOperationAction(ISD::FCEIL, RoundedTy, Legal);
917 setOperationAction(ISD::FTRUNC, RoundedTy, Legal);
918 setOperationAction(ISD::FRINT, RoundedTy, Legal);
919 setOperationAction(ISD::FNEARBYINT, RoundedTy, Legal);
920 }
921
922 setOperationAction(ISD::SMAX, MVT::v16i8, Legal);
923 setOperationAction(ISD::SMAX, MVT::v4i32, Legal);
924 setOperationAction(ISD::UMAX, MVT::v8i16, Legal);
925 setOperationAction(ISD::UMAX, MVT::v4i32, Legal);
926 setOperationAction(ISD::SMIN, MVT::v16i8, Legal);
927 setOperationAction(ISD::SMIN, MVT::v4i32, Legal);
928 setOperationAction(ISD::UMIN, MVT::v8i16, Legal);
929 setOperationAction(ISD::UMIN, MVT::v4i32, Legal);
930
931 // FIXME: Do we need to handle scalar-to-vector here?
932 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
933
934 // We directly match byte blends in the backend as they match the VSELECT
935 // condition form.
936 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
937
938 // SSE41 brings specific instructions for doing vector sign extend even in
939 // cases where we don't have SRA.
940 for (auto VT : { MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
941 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Legal);
942 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, VT, Legal);
943 }
944
945 for (MVT VT : MVT::integer_vector_valuetypes()) {
946 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i8, Custom);
947 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i16, Custom);
948 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i32, Custom);
949 }
950
951 // SSE41 also has vector sign/zero extending loads, PMOV[SZ]X
952 for (auto LoadExtOp : { ISD::SEXTLOAD, ISD::ZEXTLOAD }) {
953 setLoadExtAction(LoadExtOp, MVT::v8i16, MVT::v8i8, Legal);
954 setLoadExtAction(LoadExtOp, MVT::v4i32, MVT::v4i8, Legal);
955 setLoadExtAction(LoadExtOp, MVT::v2i32, MVT::v2i8, Legal);
956 setLoadExtAction(LoadExtOp, MVT::v2i64, MVT::v2i8, Legal);
957 setLoadExtAction(LoadExtOp, MVT::v4i32, MVT::v4i16, Legal);
958 setLoadExtAction(LoadExtOp, MVT::v2i64, MVT::v2i16, Legal);
959 setLoadExtAction(LoadExtOp, MVT::v2i64, MVT::v2i32, Legal);
960 }
961
962 // i8 vectors are custom because the source register and source
963 // source memory operand types are not the same width.
964 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
965 }
966
967 if (!Subtarget.useSoftFloat() && Subtarget.hasXOP()) {
968 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64,
969 MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 })
970 setOperationAction(ISD::ROTL, VT, Custom);
971
972 // XOP can efficiently perform BITREVERSE with VPPERM.
973 for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 })
974 setOperationAction(ISD::BITREVERSE, VT, Custom);
975
976 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64,
977 MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 })
978 setOperationAction(ISD::BITREVERSE, VT, Custom);
979 }
980
981 if (!Subtarget.useSoftFloat() && Subtarget.hasFp256()) {
982 bool HasInt256 = Subtarget.hasInt256();
983
984 addRegisterClass(MVT::v32i8, Subtarget.hasVLX() ? &X86::VR256XRegClass
985 : &X86::VR256RegClass);
986 addRegisterClass(MVT::v16i16, Subtarget.hasVLX() ? &X86::VR256XRegClass
987 : &X86::VR256RegClass);
988 addRegisterClass(MVT::v8i32, Subtarget.hasVLX() ? &X86::VR256XRegClass
989 : &X86::VR256RegClass);
990 addRegisterClass(MVT::v8f32, Subtarget.hasVLX() ? &X86::VR256XRegClass
991 : &X86::VR256RegClass);
992 addRegisterClass(MVT::v4i64, Subtarget.hasVLX() ? &X86::VR256XRegClass
993 : &X86::VR256RegClass);
994 addRegisterClass(MVT::v4f64, Subtarget.hasVLX() ? &X86::VR256XRegClass
995 : &X86::VR256RegClass);
996
997 for (auto VT : { MVT::v8f32, MVT::v4f64 }) {
998 setOperationAction(ISD::FFLOOR, VT, Legal);
999 setOperationAction(ISD::FCEIL, VT, Legal);
1000 setOperationAction(ISD::FTRUNC, VT, Legal);
1001 setOperationAction(ISD::FRINT, VT, Legal);
1002 setOperationAction(ISD::FNEARBYINT, VT, Legal);
1003 setOperationAction(ISD::FNEG, VT, Custom);
1004 setOperationAction(ISD::FABS, VT, Custom);
1005 setOperationAction(ISD::FCOPYSIGN, VT, Custom);
1006 }
1007
1008 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1009 // even though v8i16 is a legal type.
1010 setOperationPromotedToType(ISD::FP_TO_SINT, MVT::v8i16, MVT::v8i32);
1011 setOperationPromotedToType(ISD::FP_TO_UINT, MVT::v8i16, MVT::v8i32);
1012 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1013
1014 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1015 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1016
1017 if (!Subtarget.hasAVX512())
1018 setOperationAction(ISD::BITCAST, MVT::v32i1, Custom);
1019
1020 for (MVT VT : MVT::fp_vector_valuetypes())
1021 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4f32, Legal);
1022
1023 // In the customized shift lowering, the legal v8i32/v4i64 cases
1024 // in AVX2 will be recognized.
1025 for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 }) {
1026 setOperationAction(ISD::SRL, VT, Custom);
1027 setOperationAction(ISD::SHL, VT, Custom);
1028 setOperationAction(ISD::SRA, VT, Custom);
1029 }
1030
1031 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1032 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1033 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1034
1035 for (auto VT : { MVT::v16i16, MVT::v8i32, MVT::v4i64 }) {
1036 setOperationAction(ISD::SIGN_EXTEND, VT, Custom);
1037 setOperationAction(ISD::ZERO_EXTEND, VT, Custom);
1038 setOperationAction(ISD::ANY_EXTEND, VT, Custom);
1039 }
1040
1041 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1042 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1043 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1044 setOperationAction(ISD::BITREVERSE, MVT::v32i8, Custom);
1045
1046 for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 }) {
1047 setOperationAction(ISD::SETCC, VT, Custom);
1048 setOperationAction(ISD::CTPOP, VT, Custom);
1049 setOperationAction(ISD::CTTZ, VT, Custom);
1050 setOperationAction(ISD::CTLZ, VT, Custom);
1051 }
1052
1053 if (Subtarget.hasAnyFMA()) {
1054 for (auto VT : { MVT::f32, MVT::f64, MVT::v4f32, MVT::v8f32,
1055 MVT::v2f64, MVT::v4f64 })
1056 setOperationAction(ISD::FMA, VT, Legal);
1057 }
1058
1059 for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 }) {
1060 setOperationAction(ISD::ADD, VT, HasInt256 ? Legal : Custom);
1061 setOperationAction(ISD::SUB, VT, HasInt256 ? Legal : Custom);
1062 }
1063
1064 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1065 setOperationAction(ISD::MUL, MVT::v8i32, HasInt256 ? Legal : Custom);
1066 setOperationAction(ISD::MUL, MVT::v16i16, HasInt256 ? Legal : Custom);
1067 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1068
1069 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1070 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1071
1072 setOperationAction(ISD::MULHU, MVT::v16i16, HasInt256 ? Legal : Custom);
1073 setOperationAction(ISD::MULHS, MVT::v16i16, HasInt256 ? Legal : Custom);
1074 setOperationAction(ISD::MULHU, MVT::v32i8, Custom);
1075 setOperationAction(ISD::MULHS, MVT::v32i8, Custom);
1076
1077 setOperationAction(ISD::SMAX, MVT::v4i64, Custom);
1078 setOperationAction(ISD::UMAX, MVT::v4i64, Custom);
1079 setOperationAction(ISD::SMIN, MVT::v4i64, Custom);
1080 setOperationAction(ISD::UMIN, MVT::v4i64, Custom);
1081
1082 for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32 }) {
1083 setOperationAction(ISD::ABS, VT, HasInt256 ? Legal : Custom);
1084 setOperationAction(ISD::SMAX, VT, HasInt256 ? Legal : Custom);
1085 setOperationAction(ISD::UMAX, VT, HasInt256 ? Legal : Custom);
1086 setOperationAction(ISD::SMIN, VT, HasInt256 ? Legal : Custom);
1087 setOperationAction(ISD::UMIN, VT, HasInt256 ? Legal : Custom);
1088 }
1089
1090 if (HasInt256) {
1091 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v4i64, Custom);
1092 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v8i32, Custom);
1093 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v16i16, Custom);
1094
1095 // The custom lowering for UINT_TO_FP for v8i32 becomes interesting
1096 // when we have a 256bit-wide blend with immediate.
1097 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Custom);
1098
1099 // AVX2 also has wider vector sign/zero extending loads, VPMOV[SZ]X
1100 for (auto LoadExtOp : { ISD::SEXTLOAD, ISD::ZEXTLOAD }) {
1101 setLoadExtAction(LoadExtOp, MVT::v16i16, MVT::v16i8, Legal);
1102 setLoadExtAction(LoadExtOp, MVT::v8i32, MVT::v8i8, Legal);
1103 setLoadExtAction(LoadExtOp, MVT::v4i64, MVT::v4i8, Legal);
1104 setLoadExtAction(LoadExtOp, MVT::v8i32, MVT::v8i16, Legal);
1105 setLoadExtAction(LoadExtOp, MVT::v4i64, MVT::v4i16, Legal);
1106 setLoadExtAction(LoadExtOp, MVT::v4i64, MVT::v4i32, Legal);
1107 }
1108 }
1109
1110 for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64,
1111 MVT::v4f32, MVT::v8f32, MVT::v2f64, MVT::v4f64 }) {
1112 setOperationAction(ISD::MLOAD, VT, Legal);
1113 setOperationAction(ISD::MSTORE, VT, Legal);
1114 }
1115
1116 // Extract subvector is special because the value type
1117 // (result) is 128-bit but the source is 256-bit wide.
1118 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64,
1119 MVT::v4f32, MVT::v2f64 }) {
1120 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1121 }
1122
1123 // Custom lower several nodes for 256-bit types.
1124 for (MVT VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64,
1125 MVT::v8f32, MVT::v4f64 }) {
1126 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1127 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1128 setOperationAction(ISD::VSELECT, VT, Custom);
1129 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1130 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1131 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1132 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Legal);
1133 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1134 }
1135
1136 if (HasInt256)
1137 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1138
1139 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1140 for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32 }) {
1141 setOperationPromotedToType(ISD::AND, VT, MVT::v4i64);
1142 setOperationPromotedToType(ISD::OR, VT, MVT::v4i64);
1143 setOperationPromotedToType(ISD::XOR, VT, MVT::v4i64);
1144 setOperationPromotedToType(ISD::LOAD, VT, MVT::v4i64);
1145 setOperationPromotedToType(ISD::SELECT, VT, MVT::v4i64);
1146 }
1147
1148 if (HasInt256) {
1149 // Custom legalize 2x32 to get a little better code.
1150 setOperationAction(ISD::MGATHER, MVT::v2f32, Custom);
1151 setOperationAction(ISD::MGATHER, MVT::v2i32, Custom);
1152
1153 for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64,
1154 MVT::v4f32, MVT::v8f32, MVT::v2f64, MVT::v4f64 })
1155 setOperationAction(ISD::MGATHER, VT, Custom);
1156 }
1157 }
1158
1159 // This block controls legalization of the mask vector sizes that are
1160 // available with AVX512. 512-bit vectors are in a separate block controlled
1161 // by useAVX512Regs.
1162 if (!Subtarget.useSoftFloat() && Subtarget.hasAVX512()) {
1163 addRegisterClass(MVT::v1i1, &X86::VK1RegClass);
1164 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1165 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1166 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1167 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1168
1169 setOperationAction(ISD::SELECT, MVT::v1i1, Custom);
1170 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v1i1, Custom);
1171 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i1, Custom);
1172
1173 setOperationPromotedToType(ISD::FP_TO_SINT, MVT::v8i1, MVT::v8i32);
1174 setOperationPromotedToType(ISD::FP_TO_UINT, MVT::v8i1, MVT::v8i32);
1175 setOperationPromotedToType(ISD::FP_TO_SINT, MVT::v4i1, MVT::v4i32);
1176 setOperationPromotedToType(ISD::FP_TO_UINT, MVT::v4i1, MVT::v4i32);
1177 setOperationAction(ISD::FP_TO_SINT, MVT::v2i1, Custom);
1178 setOperationAction(ISD::FP_TO_UINT, MVT::v2i1, Custom);
1179
1180 // Extends of v16i1/v8i1/v4i1/v2i1 to 128-bit vectors.
1181 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
1182 setOperationAction(ISD::SIGN_EXTEND, VT, Custom);
1183 setOperationAction(ISD::ZERO_EXTEND, VT, Custom);
1184 setOperationAction(ISD::ANY_EXTEND, VT, Custom);
1185 }
1186
1187 for (auto VT : { MVT::v2i1, MVT::v4i1, MVT::v8i1, MVT::v16i1 }) {
1188 setOperationAction(ISD::ADD, VT, Custom);
1189 setOperationAction(ISD::SUB, VT, Custom);
1190 setOperationAction(ISD::MUL, VT, Custom);
1191 setOperationAction(ISD::SETCC, VT, Custom);
1192 setOperationAction(ISD::SELECT, VT, Custom);
1193 setOperationAction(ISD::TRUNCATE, VT, Custom);
1194
1195 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1196 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1197 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1198 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1199 setOperationAction(ISD::VSELECT, VT, Expand);
1200 }
1201
1202 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Custom);
1203 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1204 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i1, Custom);
1205 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v2i1, Custom);
1206 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v4i1, Custom);
1207 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Custom);
1208 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v16i1, Custom);
1209 for (auto VT : { MVT::v1i1, MVT::v2i1, MVT::v4i1, MVT::v8i1 })
1210 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1211 }
1212
1213 // This block controls legalization for 512-bit operations with 32/64 bit
1214 // elements. 512-bits can be disabled based on prefer-vector-width and
1215 // required-vector-width function attributes.
1216 if (!Subtarget.useSoftFloat() && Subtarget.useAVX512Regs()) {
1217 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1218 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1219 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1220 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1221
1222 for (MVT VT : MVT::fp_vector_valuetypes())
1223 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8f32, Legal);
1224
1225 for (auto ExtType : {ISD::ZEXTLOAD, ISD::SEXTLOAD}) {
1226 setLoadExtAction(ExtType, MVT::v16i32, MVT::v16i8, Legal);
1227 setLoadExtAction(ExtType, MVT::v16i32, MVT::v16i16, Legal);
1228 setLoadExtAction(ExtType, MVT::v8i64, MVT::v8i8, Legal);
1229 setLoadExtAction(ExtType, MVT::v8i64, MVT::v8i16, Legal);
1230 setLoadExtAction(ExtType, MVT::v8i64, MVT::v8i32, Legal);
1231 }
1232
1233 for (MVT VT : { MVT::v16f32, MVT::v8f64 }) {
1234 setOperationAction(ISD::FNEG, VT, Custom);
1235 setOperationAction(ISD::FABS, VT, Custom);
1236 setOperationAction(ISD::FMA, VT, Legal);
1237 setOperationAction(ISD::FCOPYSIGN, VT, Custom);
1238 }
1239
1240 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1241 setOperationPromotedToType(ISD::FP_TO_SINT, MVT::v16i16, MVT::v16i32);
1242 setOperationPromotedToType(ISD::FP_TO_SINT, MVT::v16i8, MVT::v16i32);
1243 setOperationPromotedToType(ISD::FP_TO_SINT, MVT::v16i1, MVT::v16i32);
1244 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1245 setOperationPromotedToType(ISD::FP_TO_UINT, MVT::v16i1, MVT::v16i32);
1246 setOperationPromotedToType(ISD::FP_TO_UINT, MVT::v16i8, MVT::v16i32);
1247 setOperationPromotedToType(ISD::FP_TO_UINT, MVT::v16i16, MVT::v16i32);
1248 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1249 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1250
1251 setTruncStoreAction(MVT::v8i64, MVT::v8i8, Legal);
1252 setTruncStoreAction(MVT::v8i64, MVT::v8i16, Legal);
1253 setTruncStoreAction(MVT::v8i64, MVT::v8i32, Legal);
1254 setTruncStoreAction(MVT::v16i32, MVT::v16i8, Legal);
1255 setTruncStoreAction(MVT::v16i32, MVT::v16i16, Legal);
1256
1257 if (!Subtarget.hasVLX()) {
1258 // With 512-bit vectors and no VLX, we prefer to widen MLOAD/MSTORE
1259 // to 512-bit rather than use the AVX2 instructions so that we can use
1260 // k-masks.
1261 for (auto VT : {MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64,
1262 MVT::v4f32, MVT::v8f32, MVT::v2f64, MVT::v4f64}) {
1263 setOperationAction(ISD::MLOAD, VT, Custom);
1264 setOperationAction(ISD::MSTORE, VT, Custom);
1265 }
1266 }
1267
1268 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1269 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1270 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1271 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1272 setOperationAction(ISD::ANY_EXTEND, MVT::v16i32, Custom);
1273 setOperationAction(ISD::ANY_EXTEND, MVT::v8i64, Custom);
1274 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1275 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1276
1277 for (auto VT : { MVT::v16f32, MVT::v8f64 }) {
1278 setOperationAction(ISD::FFLOOR, VT, Legal);
1279 setOperationAction(ISD::FCEIL, VT, Legal);
1280 setOperationAction(ISD::FTRUNC, VT, Legal);
1281 setOperationAction(ISD::FRINT, VT, Legal);
1282 setOperationAction(ISD::FNEARBYINT, VT, Legal);
1283 }
1284
1285 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v8i64, Custom);
1286 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v16i32, Custom);
1287
1288 // Without BWI we need to use custom lowering to handle MVT::v64i8 input.
1289 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v64i8, Custom);
1290 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, MVT::v64i8, Custom);
1291
1292 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1293 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1294 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1295 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1296
1297 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1298 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1299
1300 setOperationAction(ISD::UMUL_LOHI, MVT::v16i32, Custom);
1301 setOperationAction(ISD::SMUL_LOHI, MVT::v16i32, Custom);
1302
1303 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1304 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1305 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1306
1307 for (auto VT : { MVT::v16i32, MVT::v8i64 }) {
1308 setOperationAction(ISD::SMAX, VT, Legal);
1309 setOperationAction(ISD::UMAX, VT, Legal);
1310 setOperationAction(ISD::SMIN, VT, Legal);
1311 setOperationAction(ISD::UMIN, VT, Legal);
1312 setOperationAction(ISD::ABS, VT, Legal);
1313 setOperationAction(ISD::SRL, VT, Custom);
1314 setOperationAction(ISD::SHL, VT, Custom);
1315 setOperationAction(ISD::SRA, VT, Custom);
1316 setOperationAction(ISD::CTPOP, VT, Custom);
1317 setOperationAction(ISD::CTTZ, VT, Custom);
1318 setOperationAction(ISD::ROTL, VT, Custom);
1319 setOperationAction(ISD::ROTR, VT, Custom);
1320 }
1321
1322 // Need to promote to 64-bit even though we have 32-bit masked instructions
1323 // because the IR optimizers rearrange bitcasts around logic ops leaving
1324 // too many variations to handle if we don't promote them.
1325 setOperationPromotedToType(ISD::AND, MVT::v16i32, MVT::v8i64);
1326 setOperationPromotedToType(ISD::OR, MVT::v16i32, MVT::v8i64);
1327 setOperationPromotedToType(ISD::XOR, MVT::v16i32, MVT::v8i64);
1328
1329 if (Subtarget.hasDQI()) {
1330 setOperationAction(ISD::SINT_TO_FP, MVT::v8i64, Legal);
1331 setOperationAction(ISD::UINT_TO_FP, MVT::v8i64, Legal);
1332 setOperationAction(ISD::FP_TO_SINT, MVT::v8i64, Legal);
1333 setOperationAction(ISD::FP_TO_UINT, MVT::v8i64, Legal);
1334 }
1335
1336 if (Subtarget.hasCDI()) {
1337 // NonVLX sub-targets extend 128/256 vectors to use the 512 version.
1338 for (auto VT : { MVT::v16i32, MVT::v8i64} ) {
1339 setOperationAction(ISD::CTLZ, VT, Legal);
1340 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Custom);
1341 }
1342 } // Subtarget.hasCDI()
1343
1344 if (Subtarget.hasVPOPCNTDQ()) {
1345 for (auto VT : { MVT::v16i32, MVT::v8i64 })
1346 setOperationAction(ISD::CTPOP, VT, Legal);
1347 }
1348
1349 // Extract subvector is special because the value type
1350 // (result) is 256-bit but the source is 512-bit wide.
1351 // 128-bit was made Legal under AVX1.
1352 for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64,
1353 MVT::v8f32, MVT::v4f64 })
1354 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1355
1356 for (auto VT : { MVT::v16i32, MVT::v8i64, MVT::v16f32, MVT::v8f64 }) {
1357 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1358 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1359 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1360 setOperationAction(ISD::VSELECT, VT, Custom);
1361 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1362 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1363 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Legal);
1364 setOperationAction(ISD::MLOAD, VT, Legal);
1365 setOperationAction(ISD::MSTORE, VT, Legal);
1366 setOperationAction(ISD::MGATHER, VT, Custom);
1367 setOperationAction(ISD::MSCATTER, VT, Custom);
1368 }
1369 for (auto VT : { MVT::v64i8, MVT::v32i16, MVT::v16i32 }) {
1370 setOperationPromotedToType(ISD::LOAD, VT, MVT::v8i64);
1371 setOperationPromotedToType(ISD::SELECT, VT, MVT::v8i64);
1372 }
1373
1374 // Need to custom split v32i16/v64i8 bitcasts.
1375 if (!Subtarget.hasBWI()) {
1376 setOperationAction(ISD::BITCAST, MVT::v32i16, Custom);
1377 setOperationAction(ISD::BITCAST, MVT::v64i8, Custom);
1378 }
1379 }// has AVX-512
1380
1381 // This block controls legalization for operations that don't have
1382 // pre-AVX512 equivalents. Without VLX we use 512-bit operations for
1383 // narrower widths.
1384 if (!Subtarget.useSoftFloat() && Subtarget.hasAVX512()) {
1385 // These operations are handled on non-VLX by artificially widening in
1386 // isel patterns.
1387 // TODO: Custom widen in lowering on non-VLX and drop the isel patterns?
1388
1389 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1390 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1391 setOperationAction(ISD::FP_TO_UINT, MVT::v2i32, Custom);
1392 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1393 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1394
1395 for (auto VT : { MVT::v2i64, MVT::v4i64 }) {
1396 setOperationAction(ISD::SMAX, VT, Legal);
1397 setOperationAction(ISD::UMAX, VT, Legal);
1398 setOperationAction(ISD::SMIN, VT, Legal);
1399 setOperationAction(ISD::UMIN, VT, Legal);
1400 setOperationAction(ISD::ABS, VT, Legal);
1401 }
1402
1403 for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64 }) {
1404 setOperationAction(ISD::ROTL, VT, Custom);
1405 setOperationAction(ISD::ROTR, VT, Custom);
1406 }
1407
1408 // Custom legalize 2x32 to get a little better code.
1409 setOperationAction(ISD::MSCATTER, MVT::v2f32, Custom);
1410 setOperationAction(ISD::MSCATTER, MVT::v2i32, Custom);
1411
1412 for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64,
1413 MVT::v4f32, MVT::v8f32, MVT::v2f64, MVT::v4f64 })
1414 setOperationAction(ISD::MSCATTER, VT, Custom);
1415
1416 if (Subtarget.hasDQI()) {
1417 for (auto VT : { MVT::v2i64, MVT::v4i64 }) {
1418 setOperationAction(ISD::SINT_TO_FP, VT, Legal);
1419 setOperationAction(ISD::UINT_TO_FP, VT, Legal);
1420 setOperationAction(ISD::FP_TO_SINT, VT, Legal);
1421 setOperationAction(ISD::FP_TO_UINT, VT, Legal);
1422 }
1423 }
1424
1425 if (Subtarget.hasCDI()) {
1426 for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64 }) {
1427 setOperationAction(ISD::CTLZ, VT, Legal);
1428 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Custom);
1429 }
1430 } // Subtarget.hasCDI()
1431
1432 if (Subtarget.hasVPOPCNTDQ()) {
1433 for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64 })
1434 setOperationAction(ISD::CTPOP, VT, Legal);
1435 }
1436 }
1437
1438 // This block control legalization of v32i1/v64i1 which are available with
1439 // AVX512BW. 512-bit v32i16 and v64i8 vector legalization is controlled with
1440 // useBWIRegs.
1441 if (!Subtarget.useSoftFloat() && Subtarget.hasBWI()) {
1442 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1443 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1444
1445 for (auto VT : { MVT::v32i1, MVT::v64i1 }) {
1446 setOperationAction(ISD::ADD, VT, Custom);
1447 setOperationAction(ISD::SUB, VT, Custom);
1448 setOperationAction(ISD::MUL, VT, Custom);
1449 setOperationAction(ISD::VSELECT, VT, Expand);
1450
1451 setOperationAction(ISD::TRUNCATE, VT, Custom);
1452 setOperationAction(ISD::SETCC, VT, Custom);
1453 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1454 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1455 setOperationAction(ISD::SELECT, VT, Custom);
1456 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1457 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1458 }
1459
1460 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i1, Custom);
1461 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i1, Custom);
1462 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i1, Custom);
1463 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i1, Custom);
1464 for (auto VT : { MVT::v16i1, MVT::v32i1 })
1465 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1466
1467 // Extends from v32i1 masks to 256-bit vectors.
1468 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i8, Custom);
1469 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i8, Custom);
1470 setOperationAction(ISD::ANY_EXTEND, MVT::v32i8, Custom);
1471 }
1472
1473 // This block controls legalization for v32i16 and v64i8. 512-bits can be
1474 // disabled based on prefer-vector-width and required-vector-width function
1475 // attributes.
1476 if (!Subtarget.useSoftFloat() && Subtarget.useBWIRegs()) {
1477 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1478 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1479
1480 // Extends from v64i1 masks to 512-bit vectors.
1481 setOperationAction(ISD::SIGN_EXTEND, MVT::v64i8, Custom);
1482 setOperationAction(ISD::ZERO_EXTEND, MVT::v64i8, Custom);
1483 setOperationAction(ISD::ANY_EXTEND, MVT::v64i8, Custom);
1484
1485 setOperationAction(ISD::MUL, MVT::v32i16, Legal);
1486 setOperationAction(ISD::MUL, MVT::v64i8, Custom);
1487 setOperationAction(ISD::MULHS, MVT::v32i16, Legal);
1488 setOperationAction(ISD::MULHU, MVT::v32i16, Legal);
1489 setOperationAction(ISD::MULHS, MVT::v64i8, Custom);
1490 setOperationAction(ISD::MULHU, MVT::v64i8, Custom);
1491 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i16, Custom);
1492 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i8, Custom);
1493 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i16, Legal);
1494 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i8, Legal);
1495 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v32i16, Custom);
1496 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v64i8, Custom);
1497 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v32i16, Custom);
1498 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v64i8, Custom);
1499 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i16, Custom);
1500 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i16, Custom);
1501 setOperationAction(ISD::ANY_EXTEND, MVT::v32i16, Custom);
1502 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v32i16, Custom);
1503 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v64i8, Custom);
1504 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v32i16, Custom);
1505 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v64i8, Custom);
1506 setOperationAction(ISD::TRUNCATE, MVT::v32i8, Custom);
1507 setOperationAction(ISD::BITREVERSE, MVT::v64i8, Custom);
1508
1509 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v32i16, Custom);
1510
1511 setTruncStoreAction(MVT::v32i16, MVT::v32i8, Legal);
1512
1513 for (auto VT : { MVT::v64i8, MVT::v32i16 }) {
1514 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1515 setOperationAction(ISD::VSELECT, VT, Custom);
1516 setOperationAction(ISD::ABS, VT, Legal);
1517 setOperationAction(ISD::SRL, VT, Custom);
1518 setOperationAction(ISD::SHL, VT, Custom);
1519 setOperationAction(ISD::SRA, VT, Custom);
1520 setOperationAction(ISD::MLOAD, VT, Legal);
1521 setOperationAction(ISD::MSTORE, VT, Legal);
1522 setOperationAction(ISD::CTPOP, VT, Custom);
1523 setOperationAction(ISD::CTTZ, VT, Custom);
1524 setOperationAction(ISD::CTLZ, VT, Custom);
1525 setOperationAction(ISD::SMAX, VT, Legal);
1526 setOperationAction(ISD::UMAX, VT, Legal);
1527 setOperationAction(ISD::SMIN, VT, Legal);
1528 setOperationAction(ISD::UMIN, VT, Legal);
1529
1530 setOperationPromotedToType(ISD::AND, VT, MVT::v8i64);
1531 setOperationPromotedToType(ISD::OR, VT, MVT::v8i64);
1532 setOperationPromotedToType(ISD::XOR, VT, MVT::v8i64);
1533 }
1534
1535 for (auto ExtType : {ISD::ZEXTLOAD, ISD::SEXTLOAD}) {
1536 setLoadExtAction(ExtType, MVT::v32i16, MVT::v32i8, Legal);
1537 }
1538
1539 if (Subtarget.hasBITALG()) {
1540 for (auto VT : { MVT::v64i8, MVT::v32i16 })
1541 setOperationAction(ISD::CTPOP, VT, Legal);
1542 }
1543 }
1544
1545 if (!Subtarget.useSoftFloat() && Subtarget.hasBWI()) {
1546 for (auto VT : { MVT::v32i8, MVT::v16i8, MVT::v16i16, MVT::v8i16 }) {
1547 setOperationAction(ISD::MLOAD, VT, Subtarget.hasVLX() ? Legal : Custom);
1548 setOperationAction(ISD::MSTORE, VT, Subtarget.hasVLX() ? Legal : Custom);
1549 }
1550
1551 // These operations are handled on non-VLX by artificially widening in
1552 // isel patterns.
1553 // TODO: Custom widen in lowering on non-VLX and drop the isel patterns?
1554
1555 if (Subtarget.hasBITALG()) {
1556 for (auto VT : { MVT::v16i8, MVT::v32i8, MVT::v8i16, MVT::v16i16 })
1557 setOperationAction(ISD::CTPOP, VT, Legal);
1558 }
1559 }
1560
1561 if (!Subtarget.useSoftFloat() && Subtarget.hasVLX()) {
1562 setTruncStoreAction(MVT::v4i64, MVT::v4i8, Legal);
1563 setTruncStoreAction(MVT::v4i64, MVT::v4i16, Legal);
1564 setTruncStoreAction(MVT::v4i64, MVT::v4i32, Legal);
1565 setTruncStoreAction(MVT::v8i32, MVT::v8i8, Legal);
1566 setTruncStoreAction(MVT::v8i32, MVT::v8i16, Legal);
1567
1568 setTruncStoreAction(MVT::v2i64, MVT::v2i8, Legal);
1569 setTruncStoreAction(MVT::v2i64, MVT::v2i16, Legal);
1570 setTruncStoreAction(MVT::v2i64, MVT::v2i32, Legal);
1571 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Legal);
1572 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Legal);
1573
1574 if (Subtarget.hasDQI()) {
1575 // Fast v2f32 SINT_TO_FP( v2i64 ) custom conversion.
1576 // v2f32 UINT_TO_FP is already custom under SSE2.
1577 setOperationAction(ISD::SINT_TO_FP, MVT::v2f32, Custom);
1578 assert(isOperationCustom(ISD::UINT_TO_FP, MVT::v2f32) &&(static_cast <bool> (isOperationCustom(ISD::UINT_TO_FP,
MVT::v2f32) && "Unexpected operation action!") ? void
(0) : __assert_fail ("isOperationCustom(ISD::UINT_TO_FP, MVT::v2f32) && \"Unexpected operation action!\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 1579, __extension__ __PRETTY_FUNCTION__))
1579 "Unexpected operation action!")(static_cast <bool> (isOperationCustom(ISD::UINT_TO_FP,
MVT::v2f32) && "Unexpected operation action!") ? void
(0) : __assert_fail ("isOperationCustom(ISD::UINT_TO_FP, MVT::v2f32) && \"Unexpected operation action!\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 1579, __extension__ __PRETTY_FUNCTION__))
;
1580 // v2i64 FP_TO_S/UINT(v2f32) custom conversion.
1581 setOperationAction(ISD::FP_TO_SINT, MVT::v2f32, Custom);
1582 setOperationAction(ISD::FP_TO_UINT, MVT::v2f32, Custom);
1583 }
1584
1585 if (Subtarget.hasBWI()) {
1586 setTruncStoreAction(MVT::v16i16, MVT::v16i8, Legal);
1587 setTruncStoreAction(MVT::v8i16, MVT::v8i8, Legal);
1588 }
1589 }
1590
1591 // We want to custom lower some of our intrinsics.
1592 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1593 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1594 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1595 if (!Subtarget.is64Bit()) {
1596 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1597 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom);
1598 }
1599
1600 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1601 // handle type legalization for these operations here.
1602 //
1603 // FIXME: We really should do custom legalization for addition and
1604 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1605 // than generic legalization for 64-bit multiplication-with-overflow, though.
1606 for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
1607 if (VT == MVT::i64 && !Subtarget.is64Bit())
1608 continue;
1609 // Add/Sub/Mul with overflow operations are custom lowered.
1610 setOperationAction(ISD::SADDO, VT, Custom);
1611 setOperationAction(ISD::UADDO, VT, Custom);
1612 setOperationAction(ISD::SSUBO, VT, Custom);
1613 setOperationAction(ISD::USUBO, VT, Custom);
1614 setOperationAction(ISD::SMULO, VT, Custom);
1615 setOperationAction(ISD::UMULO, VT, Custom);
1616
1617 // Support carry in as value rather than glue.
1618 setOperationAction(ISD::ADDCARRY, VT, Custom);
1619 setOperationAction(ISD::SUBCARRY, VT, Custom);
1620 setOperationAction(ISD::SETCCCARRY, VT, Custom);
1621 }
1622
1623 if (!Subtarget.is64Bit()) {
1624 // These libcalls are not available in 32-bit.
1625 setLibcallName(RTLIB::SHL_I128, nullptr);
1626 setLibcallName(RTLIB::SRL_I128, nullptr);
1627 setLibcallName(RTLIB::SRA_I128, nullptr);
1628 setLibcallName(RTLIB::MUL_I128, nullptr);
1629 }
1630
1631 // Combine sin / cos into _sincos_stret if it is available.
1632 if (getLibcallName(RTLIB::SINCOS_STRET_F32) != nullptr &&
1633 getLibcallName(RTLIB::SINCOS_STRET_F64) != nullptr) {
1634 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1635 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1636 }
1637
1638 if (Subtarget.isTargetWin64()) {
1639 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1640 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1641 setOperationAction(ISD::SREM, MVT::i128, Custom);
1642 setOperationAction(ISD::UREM, MVT::i128, Custom);
1643 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1644 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1645 }
1646
1647 // On 32 bit MSVC, `fmodf(f32)` is not defined - only `fmod(f64)`
1648 // is. We should promote the value to 64-bits to solve this.
1649 // This is what the CRT headers do - `fmodf` is an inline header
1650 // function casting to f64 and calling `fmod`.
1651 if (Subtarget.is32Bit() && (Subtarget.isTargetKnownWindowsMSVC() ||
1652 Subtarget.isTargetWindowsItanium()))
1653 for (ISD::NodeType Op :
1654 {ISD::FCEIL, ISD::FCOS, ISD::FEXP, ISD::FFLOOR, ISD::FREM, ISD::FLOG,
1655 ISD::FLOG10, ISD::FPOW, ISD::FSIN})
1656 if (isOperationExpand(Op, MVT::f32))
1657 setOperationAction(Op, MVT::f32, Promote);
1658
1659 // We have target-specific dag combine patterns for the following nodes:
1660 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1661 setTargetDAGCombine(ISD::SCALAR_TO_VECTOR);
1662 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1663 setTargetDAGCombine(ISD::INSERT_SUBVECTOR);
1664 setTargetDAGCombine(ISD::EXTRACT_SUBVECTOR);
1665 setTargetDAGCombine(ISD::BITCAST);
1666 setTargetDAGCombine(ISD::VSELECT);
1667 setTargetDAGCombine(ISD::SELECT);
1668 setTargetDAGCombine(ISD::SHL);
1669 setTargetDAGCombine(ISD::SRA);
1670 setTargetDAGCombine(ISD::SRL);
1671 setTargetDAGCombine(ISD::OR);
1672 setTargetDAGCombine(ISD::AND);
1673 setTargetDAGCombine(ISD::ADD);
1674 setTargetDAGCombine(ISD::FADD);
1675 setTargetDAGCombine(ISD::FSUB);
1676 setTargetDAGCombine(ISD::FNEG);
1677 setTargetDAGCombine(ISD::FMA);
1678 setTargetDAGCombine(ISD::FMINNUM);
1679 setTargetDAGCombine(ISD::FMAXNUM);
1680 setTargetDAGCombine(ISD::SUB);
1681 setTargetDAGCombine(ISD::LOAD);
1682 setTargetDAGCombine(ISD::MLOAD);
1683 setTargetDAGCombine(ISD::STORE);
1684 setTargetDAGCombine(ISD::MSTORE);
1685 setTargetDAGCombine(ISD::TRUNCATE);
1686 setTargetDAGCombine(ISD::ZERO_EXTEND);
1687 setTargetDAGCombine(ISD::ANY_EXTEND);
1688 setTargetDAGCombine(ISD::SIGN_EXTEND);
1689 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1690 setTargetDAGCombine(ISD::SIGN_EXTEND_VECTOR_INREG);
1691 setTargetDAGCombine(ISD::ZERO_EXTEND_VECTOR_INREG);
1692 setTargetDAGCombine(ISD::SINT_TO_FP);
1693 setTargetDAGCombine(ISD::UINT_TO_FP);
1694 setTargetDAGCombine(ISD::SETCC);
1695 setTargetDAGCombine(ISD::MUL);
1696 setTargetDAGCombine(ISD::XOR);
1697 setTargetDAGCombine(ISD::MSCATTER);
1698 setTargetDAGCombine(ISD::MGATHER);
1699
1700 computeRegisterProperties(Subtarget.getRegisterInfo());
1701
1702 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1703 MaxStoresPerMemsetOptSize = 8;
1704 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1705 MaxStoresPerMemcpyOptSize = 4;
1706 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1707 MaxStoresPerMemmoveOptSize = 4;
1708
1709 // TODO: These control memcmp expansion in CGP and could be raised higher, but
1710 // that needs to benchmarked and balanced with the potential use of vector
1711 // load/store types (PR33329, PR33914).
1712 MaxLoadsPerMemcmp = 2;
1713 MaxLoadsPerMemcmpOptSize = 2;
1714
1715 // Set loop alignment to 2^ExperimentalPrefLoopAlignment bytes (default: 2^4).
1716 setPrefLoopAlignment(ExperimentalPrefLoopAlignment);
1717
1718 // An out-of-order CPU can speculatively execute past a predictable branch,
1719 // but a conditional move could be stalled by an expensive earlier operation.
1720 PredictableSelectIsExpensive = Subtarget.getSchedModel().isOutOfOrder();
1721 EnableExtLdPromotion = true;
1722 setPrefFunctionAlignment(4); // 2^4 bytes.
1723
1724 verifyIntrinsicTables();
1725}
1726
1727// This has so far only been implemented for 64-bit MachO.
1728bool X86TargetLowering::useLoadStackGuardNode() const {
1729 return Subtarget.isTargetMachO() && Subtarget.is64Bit();
1730}
1731
1732bool X86TargetLowering::useStackGuardXorFP() const {
1733 // Currently only MSVC CRTs XOR the frame pointer into the stack guard value.
1734 return Subtarget.getTargetTriple().isOSMSVCRT();
1735}
1736
1737SDValue X86TargetLowering::emitStackGuardXorFP(SelectionDAG &DAG, SDValue Val,
1738 const SDLoc &DL) const {
1739 EVT PtrTy = getPointerTy(DAG.getDataLayout());
1740 unsigned XorOp = Subtarget.is64Bit() ? X86::XOR64_FP : X86::XOR32_FP;
1741 MachineSDNode *Node = DAG.getMachineNode(XorOp, DL, PtrTy, Val);
1742 return SDValue(Node, 0);
1743}
1744
1745TargetLoweringBase::LegalizeTypeAction
1746X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1747 if (VT == MVT::v32i1 && Subtarget.hasAVX512() && !Subtarget.hasBWI())
1748 return TypeSplitVector;
1749
1750 if (ExperimentalVectorWideningLegalization &&
1751 VT.getVectorNumElements() != 1 &&
1752 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1753 return TypeWidenVector;
1754
1755 return TargetLoweringBase::getPreferredVectorAction(VT);
1756}
1757
1758MVT X86TargetLowering::getRegisterTypeForCallingConv(MVT VT) const {
1759 if (VT == MVT::v32i1 && Subtarget.hasAVX512() && !Subtarget.hasBWI())
1760 return MVT::v32i8;
1761 return TargetLowering::getRegisterTypeForCallingConv(VT);
1762}
1763
1764MVT X86TargetLowering::getRegisterTypeForCallingConv(LLVMContext &Context,
1765 EVT VT) const {
1766 if (VT == MVT::v32i1 && Subtarget.hasAVX512() && !Subtarget.hasBWI())
1767 return MVT::v32i8;
1768 return TargetLowering::getRegisterTypeForCallingConv(Context, VT);
1769}
1770
1771unsigned X86TargetLowering::getNumRegistersForCallingConv(LLVMContext &Context,
1772 EVT VT) const {
1773 if (VT == MVT::v32i1 && Subtarget.hasAVX512() && !Subtarget.hasBWI())
1774 return 1;
1775 return TargetLowering::getNumRegistersForCallingConv(Context, VT);
1776}
1777
1778EVT X86TargetLowering::getSetCCResultType(const DataLayout &DL,
1779 LLVMContext& Context,
1780 EVT VT) const {
1781 if (!VT.isVector())
1782 return MVT::i8;
1783
1784 if (Subtarget.hasAVX512()) {
1785 const unsigned NumElts = VT.getVectorNumElements();
1786
1787 // Figure out what this type will be legalized to.
1788 EVT LegalVT = VT;
1789 while (getTypeAction(Context, LegalVT) != TypeLegal)
1790 LegalVT = getTypeToTransformTo(Context, LegalVT);
1791
1792 // If we got a 512-bit vector then we'll definitely have a vXi1 compare.
1793 if (LegalVT.getSimpleVT().is512BitVector())
1794 return EVT::getVectorVT(Context, MVT::i1, NumElts);
1795
1796 if (LegalVT.getSimpleVT().isVector() && Subtarget.hasVLX()) {
1797 // If we legalized to less than a 512-bit vector, then we will use a vXi1
1798 // compare for vXi32/vXi64 for sure. If we have BWI we will also support
1799 // vXi16/vXi8.
1800 MVT EltVT = LegalVT.getSimpleVT().getVectorElementType();
1801 if (Subtarget.hasBWI() || EltVT.getSizeInBits() >= 32)
1802 return EVT::getVectorVT(Context, MVT::i1, NumElts);
1803 }
1804 }
1805
1806 return VT.changeVectorElementTypeToInteger();
1807}
1808
1809/// Helper for getByValTypeAlignment to determine
1810/// the desired ByVal argument alignment.
1811static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1812 if (MaxAlign == 16)
1813 return;
1814 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1815 if (VTy->getBitWidth() == 128)
1816 MaxAlign = 16;
1817 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1818 unsigned EltAlign = 0;
1819 getMaxByValAlign(ATy->getElementType(), EltAlign);
1820 if (EltAlign > MaxAlign)
1821 MaxAlign = EltAlign;
1822 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1823 for (auto *EltTy : STy->elements()) {
1824 unsigned EltAlign = 0;
1825 getMaxByValAlign(EltTy, EltAlign);
1826 if (EltAlign > MaxAlign)
1827 MaxAlign = EltAlign;
1828 if (MaxAlign == 16)
1829 break;
1830 }
1831 }
1832}
1833
1834/// Return the desired alignment for ByVal aggregate
1835/// function arguments in the caller parameter area. For X86, aggregates
1836/// that contain SSE vectors are placed at 16-byte boundaries while the rest
1837/// are at 4-byte boundaries.
1838unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty,
1839 const DataLayout &DL) const {
1840 if (Subtarget.is64Bit()) {
1841 // Max of 8 and alignment of type.
1842 unsigned TyAlign = DL.getABITypeAlignment(Ty);
1843 if (TyAlign > 8)
1844 return TyAlign;
1845 return 8;
1846 }
1847
1848 unsigned Align = 4;
1849 if (Subtarget.hasSSE1())
1850 getMaxByValAlign(Ty, Align);
1851 return Align;
1852}
1853
1854/// Returns the target specific optimal type for load
1855/// and store operations as a result of memset, memcpy, and memmove
1856/// lowering. If DstAlign is zero that means it's safe to destination
1857/// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1858/// means there isn't a need to check it against alignment requirement,
1859/// probably because the source does not need to be loaded. If 'IsMemset' is
1860/// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1861/// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1862/// source is constant so it does not need to be loaded.
1863/// It returns EVT::Other if the type should be determined using generic
1864/// target-independent logic.
1865EVT
1866X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1867 unsigned DstAlign, unsigned SrcAlign,
1868 bool IsMemset, bool ZeroMemset,
1869 bool MemcpyStrSrc,
1870 MachineFunction &MF) const {
1871 const Function &F = MF.getFunction();
1872 if (!F.hasFnAttribute(Attribute::NoImplicitFloat)) {
1873 if (Size >= 16 &&
1874 (!Subtarget.isUnalignedMem16Slow() ||
1875 ((DstAlign == 0 || DstAlign >= 16) &&
1876 (SrcAlign == 0 || SrcAlign >= 16)))) {
1877 // FIXME: Check if unaligned 32-byte accesses are slow.
1878 if (Size >= 32 && Subtarget.hasAVX()) {
1879 // Although this isn't a well-supported type for AVX1, we'll let
1880 // legalization and shuffle lowering produce the optimal codegen. If we
1881 // choose an optimal type with a vector element larger than a byte,
1882 // getMemsetStores() may create an intermediate splat (using an integer
1883 // multiply) before we splat as a vector.
1884 return MVT::v32i8;
1885 }
1886 if (Subtarget.hasSSE2())
1887 return MVT::v16i8;
1888 // TODO: Can SSE1 handle a byte vector?
1889 if (Subtarget.hasSSE1())
1890 return MVT::v4f32;
1891 } else if ((!IsMemset || ZeroMemset) && !MemcpyStrSrc && Size >= 8 &&
1892 !Subtarget.is64Bit() && Subtarget.hasSSE2()) {
1893 // Do not use f64 to lower memcpy if source is string constant. It's
1894 // better to use i32 to avoid the loads.
1895 // Also, do not use f64 to lower memset unless this is a memset of zeros.
1896 // The gymnastics of splatting a byte value into an XMM register and then
1897 // only using 8-byte stores (because this is a CPU with slow unaligned
1898 // 16-byte accesses) makes that a loser.
1899 return MVT::f64;
1900 }
1901 }
1902 // This is a compromise. If we reach here, unaligned accesses may be slow on
1903 // this target. However, creating smaller, aligned accesses could be even
1904 // slower and would certainly be a lot more code.
1905 if (Subtarget.is64Bit() && Size >= 8)
1906 return MVT::i64;
1907 return MVT::i32;
1908}
1909
1910bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1911 if (VT == MVT::f32)
1912 return X86ScalarSSEf32;
1913 else if (VT == MVT::f64)
1914 return X86ScalarSSEf64;
1915 return true;
1916}
1917
1918bool
1919X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1920 unsigned,
1921 unsigned,
1922 bool *Fast) const {
1923 if (Fast) {
1924 switch (VT.getSizeInBits()) {
1925 default:
1926 // 8-byte and under are always assumed to be fast.
1927 *Fast = true;
1928 break;
1929 case 128:
1930 *Fast = !Subtarget.isUnalignedMem16Slow();
1931 break;
1932 case 256:
1933 *Fast = !Subtarget.isUnalignedMem32Slow();
1934 break;
1935 // TODO: What about AVX-512 (512-bit) accesses?
1936 }
1937 }
1938 // Misaligned accesses of any size are always allowed.
1939 return true;
1940}
1941
1942/// Return the entry encoding for a jump table in the
1943/// current function. The returned value is a member of the
1944/// MachineJumpTableInfo::JTEntryKind enum.
1945unsigned X86TargetLowering::getJumpTableEncoding() const {
1946 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1947 // symbol.
1948 if (isPositionIndependent() && Subtarget.isPICStyleGOT())
1949 return MachineJumpTableInfo::EK_Custom32;
1950
1951 // Otherwise, use the normal jump table encoding heuristics.
1952 return TargetLowering::getJumpTableEncoding();
1953}
1954
1955bool X86TargetLowering::useSoftFloat() const {
1956 return Subtarget.useSoftFloat();
1957}
1958
1959void X86TargetLowering::markLibCallAttributes(MachineFunction *MF, unsigned CC,
1960 ArgListTy &Args) const {
1961
1962 // Only relabel X86-32 for C / Stdcall CCs.
1963 if (Subtarget.is64Bit())
1964 return;
1965 if (CC != CallingConv::C && CC != CallingConv::X86_StdCall)
1966 return;
1967 unsigned ParamRegs = 0;
1968 if (auto *M = MF->getFunction().getParent())
1969 ParamRegs = M->getNumberRegisterParameters();
1970
1971 // Mark the first N int arguments as having reg
1972 for (unsigned Idx = 0; Idx < Args.size(); Idx++) {
1973 Type *T = Args[Idx].Ty;
1974 if (T->isPointerTy() || T->isIntegerTy())
1975 if (MF->getDataLayout().getTypeAllocSize(T) <= 8) {
1976 unsigned numRegs = 1;
1977 if (MF->getDataLayout().getTypeAllocSize(T) > 4)
1978 numRegs = 2;
1979 if (ParamRegs < numRegs)
1980 return;
1981 ParamRegs -= numRegs;
1982 Args[Idx].IsInReg = true;
1983 }
1984 }
1985}
1986
1987const MCExpr *
1988X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1989 const MachineBasicBlock *MBB,
1990 unsigned uid,MCContext &Ctx) const{
1991 assert(isPositionIndependent() && Subtarget.isPICStyleGOT())(static_cast <bool> (isPositionIndependent() &&
Subtarget.isPICStyleGOT()) ? void (0) : __assert_fail ("isPositionIndependent() && Subtarget.isPICStyleGOT()"
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 1991, __extension__ __PRETTY_FUNCTION__))
;
1992 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1993 // entries.
1994 return MCSymbolRefExpr::create(MBB->getSymbol(),
1995 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1996}
1997
1998/// Returns relocation base for the given PIC jumptable.
1999SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
2000 SelectionDAG &DAG) const {
2001 if (!Subtarget.is64Bit())
2002 // This doesn't have SDLoc associated with it, but is not really the
2003 // same as a Register.
2004 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(),
2005 getPointerTy(DAG.getDataLayout()));
2006 return Table;
2007}
2008
2009/// This returns the relocation base for the given PIC jumptable,
2010/// the same as getPICJumpTableRelocBase, but as an MCExpr.
2011const MCExpr *X86TargetLowering::
2012getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
2013 MCContext &Ctx) const {
2014 // X86-64 uses RIP relative addressing based on the jump table label.
2015 if (Subtarget.isPICStyleRIPRel())
2016 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
2017
2018 // Otherwise, the reference is relative to the PIC base.
2019 return MCSymbolRefExpr::create(MF->getPICBaseSymbol(), Ctx);
2020}
2021
2022std::pair<const TargetRegisterClass *, uint8_t>
2023X86TargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
2024 MVT VT) const {
2025 const TargetRegisterClass *RRC = nullptr;
2026 uint8_t Cost = 1;
2027 switch (VT.SimpleTy) {
2028 default:
2029 return TargetLowering::findRepresentativeClass(TRI, VT);
2030 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
2031 RRC = Subtarget.is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
2032 break;
2033 case MVT::x86mmx:
2034 RRC = &X86::VR64RegClass;
2035 break;
2036 case MVT::f32: case MVT::f64:
2037 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
2038 case MVT::v4f32: case MVT::v2f64:
2039 case MVT::v32i8: case MVT::v16i16: case MVT::v8i32: case MVT::v4i64:
2040 case MVT::v8f32: case MVT::v4f64:
2041 case MVT::v64i8: case MVT::v32i16: case MVT::v16i32: case MVT::v8i64:
2042 case MVT::v16f32: case MVT::v8f64:
2043 RRC = &X86::VR128XRegClass;
2044 break;
2045 }
2046 return std::make_pair(RRC, Cost);
2047}
2048
2049unsigned X86TargetLowering::getAddressSpace() const {
2050 if (Subtarget.is64Bit())
2051 return (getTargetMachine().getCodeModel() == CodeModel::Kernel) ? 256 : 257;
2052 return 256;
2053}
2054
2055static bool hasStackGuardSlotTLS(const Triple &TargetTriple) {
2056 return TargetTriple.isOSGlibc() || TargetTriple.isOSFuchsia() ||
2057 (TargetTriple.isAndroid() && !TargetTriple.isAndroidVersionLT(17));
2058}
2059
2060static Constant* SegmentOffset(IRBuilder<> &IRB,
2061 unsigned Offset, unsigned AddressSpace) {
2062 return ConstantExpr::getIntToPtr(
2063 ConstantInt::get(Type::getInt32Ty(IRB.getContext()), Offset),
2064 Type::getInt8PtrTy(IRB.getContext())->getPointerTo(AddressSpace));
2065}
2066
2067Value *X86TargetLowering::getIRStackGuard(IRBuilder<> &IRB) const {
2068 // glibc, bionic, and Fuchsia have a special slot for the stack guard in
2069 // tcbhead_t; use it instead of the usual global variable (see
2070 // sysdeps/{i386,x86_64}/nptl/tls.h)
2071 if (hasStackGuardSlotTLS(Subtarget.getTargetTriple())) {
2072 if (Subtarget.isTargetFuchsia()) {
2073 // <zircon/tls.h> defines ZX_TLS_STACK_GUARD_OFFSET with this value.
2074 return SegmentOffset(IRB, 0x10, getAddressSpace());
2075 } else {
2076 // %fs:0x28, unless we're using a Kernel code model, in which case
2077 // it's %gs:0x28. gs:0x14 on i386.
2078 unsigned Offset = (Subtarget.is64Bit()) ? 0x28 : 0x14;
2079 return SegmentOffset(IRB, Offset, getAddressSpace());
2080 }
2081 }
2082
2083 return TargetLowering::getIRStackGuard(IRB);
2084}
2085
2086void X86TargetLowering::insertSSPDeclarations(Module &M) const {
2087 // MSVC CRT provides functionalities for stack protection.
2088 if (Subtarget.getTargetTriple().isOSMSVCRT()) {
2089 // MSVC CRT has a global variable holding security cookie.
2090 M.getOrInsertGlobal("__security_cookie",
2091 Type::getInt8PtrTy(M.getContext()));
2092
2093 // MSVC CRT has a function to validate security cookie.
2094 auto *SecurityCheckCookie = cast<Function>(
2095 M.getOrInsertFunction("__security_check_cookie",
2096 Type::getVoidTy(M.getContext()),
2097 Type::getInt8PtrTy(M.getContext())));
2098 SecurityCheckCookie->setCallingConv(CallingConv::X86_FastCall);
2099 SecurityCheckCookie->addAttribute(1, Attribute::AttrKind::InReg);
2100 return;
2101 }
2102 // glibc, bionic, and Fuchsia have a special slot for the stack guard.
2103 if (hasStackGuardSlotTLS(Subtarget.getTargetTriple()))
2104 return;
2105 TargetLowering::insertSSPDeclarations(M);
2106}
2107
2108Value *X86TargetLowering::getSDagStackGuard(const Module &M) const {
2109 // MSVC CRT has a global variable holding security cookie.
2110 if (Subtarget.getTargetTriple().isOSMSVCRT())
2111 return M.getGlobalVariable("__security_cookie");
2112 return TargetLowering::getSDagStackGuard(M);
2113}
2114
2115Value *X86TargetLowering::getSSPStackGuardCheck(const Module &M) const {
2116 // MSVC CRT has a function to validate security cookie.
2117 if (Subtarget.getTargetTriple().isOSMSVCRT())
2118 return M.getFunction("__security_check_cookie");
2119 return TargetLowering::getSSPStackGuardCheck(M);
2120}
2121
2122Value *X86TargetLowering::getSafeStackPointerLocation(IRBuilder<> &IRB) const {
2123 if (Subtarget.getTargetTriple().isOSContiki())
2124 return getDefaultSafeStackPointerLocation(IRB, false);
2125
2126 // Android provides a fixed TLS slot for the SafeStack pointer. See the
2127 // definition of TLS_SLOT_SAFESTACK in
2128 // https://android.googlesource.com/platform/bionic/+/master/libc/private/bionic_tls.h
2129 if (Subtarget.isTargetAndroid()) {
2130 // %fs:0x48, unless we're using a Kernel code model, in which case it's %gs:
2131 // %gs:0x24 on i386
2132 unsigned Offset = (Subtarget.is64Bit()) ? 0x48 : 0x24;
2133 return SegmentOffset(IRB, Offset, getAddressSpace());
2134 }
2135
2136 // Fuchsia is similar.
2137 if (Subtarget.isTargetFuchsia()) {
2138 // <zircon/tls.h> defines ZX_TLS_UNSAFE_SP_OFFSET with this value.
2139 return SegmentOffset(IRB, 0x18, getAddressSpace());
2140 }
2141
2142 return TargetLowering::getSafeStackPointerLocation(IRB);
2143}
2144
2145bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
2146 unsigned DestAS) const {
2147 assert(SrcAS != DestAS && "Expected different address spaces!")(static_cast <bool> (SrcAS != DestAS && "Expected different address spaces!"
) ? void (0) : __assert_fail ("SrcAS != DestAS && \"Expected different address spaces!\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 2147, __extension__ __PRETTY_FUNCTION__))
;
2148
2149 return SrcAS < 256 && DestAS < 256;
2150}
2151
2152//===----------------------------------------------------------------------===//
2153// Return Value Calling Convention Implementation
2154//===----------------------------------------------------------------------===//
2155
2156#include "X86GenCallingConv.inc"
2157
2158bool X86TargetLowering::CanLowerReturn(
2159 CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
2160 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
2161 SmallVector<CCValAssign, 16> RVLocs;
2162 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
2163 return CCInfo.CheckReturn(Outs, RetCC_X86);
2164}
2165
2166const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
2167 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
2168 return ScratchRegs;
2169}
2170
2171/// Lowers masks values (v*i1) to the local register values
2172/// \returns DAG node after lowering to register type
2173static SDValue lowerMasksToReg(const SDValue &ValArg, const EVT &ValLoc,
2174 const SDLoc &Dl, SelectionDAG &DAG) {
2175 EVT ValVT = ValArg.getValueType();
2176
2177 if (ValVT == MVT::v1i1)
2178 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, Dl, ValLoc, ValArg,
2179 DAG.getIntPtrConstant(0, Dl));
2180
2181 if ((ValVT == MVT::v8i1 && (ValLoc == MVT::i8 || ValLoc == MVT::i32)) ||
2182 (ValVT == MVT::v16i1 && (ValLoc == MVT::i16 || ValLoc == MVT::i32))) {
2183 // Two stage lowering might be required
2184 // bitcast: v8i1 -> i8 / v16i1 -> i16
2185 // anyextend: i8 -> i32 / i16 -> i32
2186 EVT TempValLoc = ValVT == MVT::v8i1 ? MVT::i8 : MVT::i16;
2187 SDValue ValToCopy = DAG.getBitcast(TempValLoc, ValArg);
2188 if (ValLoc == MVT::i32)
2189 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, Dl, ValLoc, ValToCopy);
2190 return ValToCopy;
2191 }
2192
2193 if ((ValVT == MVT::v32i1 && ValLoc == MVT::i32) ||
2194 (ValVT == MVT::v64i1 && ValLoc == MVT::i64)) {
2195 // One stage lowering is required
2196 // bitcast: v32i1 -> i32 / v64i1 -> i64
2197 return DAG.getBitcast(ValLoc, ValArg);
2198 }
2199
2200 return DAG.getNode(ISD::ANY_EXTEND, Dl, ValLoc, ValArg);
2201}
2202
2203/// Breaks v64i1 value into two registers and adds the new node to the DAG
2204static void Passv64i1ArgInRegs(
2205 const SDLoc &Dl, SelectionDAG &DAG, SDValue Chain, SDValue &Arg,
2206 SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass, CCValAssign &VA,
2207 CCValAssign &NextVA, const X86Subtarget &Subtarget) {
2208 assert(Subtarget.hasBWI() && "Expected AVX512BW target!")(static_cast <bool> (Subtarget.hasBWI() && "Expected AVX512BW target!"
) ? void (0) : __assert_fail ("Subtarget.hasBWI() && \"Expected AVX512BW target!\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 2208, __extension__ __PRETTY_FUNCTION__))
;
2209 assert(Subtarget.is32Bit() && "Expecting 32 bit target")(static_cast <bool> (Subtarget.is32Bit() && "Expecting 32 bit target"
) ? void (0) : __assert_fail ("Subtarget.is32Bit() && \"Expecting 32 bit target\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 2209, __extension__ __PRETTY_FUNCTION__))
;
2210 assert(Arg.getValueType() == MVT::i64 && "Expecting 64 bit value")(static_cast <bool> (Arg.getValueType() == MVT::i64 &&
"Expecting 64 bit value") ? void (0) : __assert_fail ("Arg.getValueType() == MVT::i64 && \"Expecting 64 bit value\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 2210, __extension__ __PRETTY_FUNCTION__))
;
2211 assert(VA.isRegLoc() && NextVA.isRegLoc() &&(static_cast <bool> (VA.isRegLoc() && NextVA.isRegLoc
() && "The value should reside in two registers") ? void
(0) : __assert_fail ("VA.isRegLoc() && NextVA.isRegLoc() && \"The value should reside in two registers\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 2212, __extension__ __PRETTY_FUNCTION__))
2212 "The value should reside in two registers")(static_cast <bool> (VA.isRegLoc() && NextVA.isRegLoc
() && "The value should reside in two registers") ? void
(0) : __assert_fail ("VA.isRegLoc() && NextVA.isRegLoc() && \"The value should reside in two registers\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 2212, __extension__ __PRETTY_FUNCTION__))
;
2213
2214 // Before splitting the value we cast it to i64
2215 Arg = DAG.getBitcast(MVT::i64, Arg);
2216
2217 // Splitting the value into two i32 types
2218 SDValue Lo, Hi;
2219 Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, Dl, MVT::i32, Arg,
2220 DAG.getConstant(0, Dl, MVT::i32));
2221 Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, Dl, MVT::i32, Arg,
2222 DAG.getConstant(1, Dl, MVT::i32));
2223
2224 // Attach the two i32 types into corresponding registers
2225 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Lo));
2226 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), Hi));
2227}
2228
2229SDValue
2230X86TargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
2231 bool isVarArg,
2232 const SmallVectorImpl<ISD::OutputArg> &Outs,
2233 const SmallVectorImpl<SDValue> &OutVals,
2234 const SDLoc &dl, SelectionDAG &DAG) const {
2235 MachineFunction &MF = DAG.getMachineFunction();
2236 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2237
2238 // In some cases we need to disable registers from the default CSR list.
2239 // For example, when they are used for argument passing.
2240 bool ShouldDisableCalleeSavedRegister =
2241 CallConv == CallingConv::X86_RegCall ||
2242 MF.getFunction().hasFnAttribute("no_caller_saved_registers");
2243
2244 if (CallConv == CallingConv::X86_INTR && !Outs.empty())
2245 report_fatal_error("X86 interrupts may not return any value");
2246
2247 SmallVector<CCValAssign, 16> RVLocs;
2248 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
2249 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
2250
2251 SDValue Flag;
2252 SmallVector<SDValue, 6> RetOps;
2253 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
2254 // Operand #1 = Bytes To Pop
2255 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(), dl,
2256 MVT::i32));
2257
2258 // Copy the result values into the output registers.
2259 for (unsigned I = 0, OutsIndex = 0, E = RVLocs.size(); I != E;
2260 ++I, ++OutsIndex) {
2261 CCValAssign &VA = RVLocs[I];
2262 assert(VA.isRegLoc() && "Can only return in registers!")(static_cast <bool> (VA.isRegLoc() && "Can only return in registers!"
) ? void (0) : __assert_fail ("VA.isRegLoc() && \"Can only return in registers!\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 2262, __extension__ __PRETTY_FUNCTION__))
;
2263
2264 // Add the register to the CalleeSaveDisableRegs list.
2265 if (ShouldDisableCalleeSavedRegister)
2266 MF.getRegInfo().disableCalleeSavedRegister(VA.getLocReg());
2267
2268 SDValue ValToCopy = OutVals[OutsIndex];
2269 EVT ValVT = ValToCopy.getValueType();
2270
2271 // Promote values to the appropriate types.
2272 if (VA.getLocInfo() == CCValAssign::SExt)
2273 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2274 else if (VA.getLocInfo() == CCValAssign::ZExt)
2275 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2276 else if (VA.getLocInfo() == CCValAssign::AExt) {
2277 if (ValVT.isVector() && ValVT.getVectorElementType() == MVT::i1)
2278 ValToCopy = lowerMasksToReg(ValToCopy, VA.getLocVT(), dl, DAG);
2279 else
2280 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2281 }
2282 else if (VA.getLocInfo() == CCValAssign::BCvt)
2283 ValToCopy = DAG.getBitcast(VA.getLocVT(), ValToCopy);
2284
2285 assert(VA.getLocInfo() != CCValAssign::FPExt &&(static_cast <bool> (VA.getLocInfo() != CCValAssign::FPExt
&& "Unexpected FP-extend for return value.") ? void (
0) : __assert_fail ("VA.getLocInfo() != CCValAssign::FPExt && \"Unexpected FP-extend for return value.\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 2286, __extension__ __PRETTY_FUNCTION__))
2286 "Unexpected FP-extend for return value.")(static_cast <bool> (VA.getLocInfo() != CCValAssign::FPExt
&& "Unexpected FP-extend for return value.") ? void (
0) : __assert_fail ("VA.getLocInfo() != CCValAssign::FPExt && \"Unexpected FP-extend for return value.\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 2286, __extension__ __PRETTY_FUNCTION__))
;
2287
2288 // If this is x86-64, and we disabled SSE, we can't return FP values,
2289 // or SSE or MMX vectors.
2290 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2291 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2292 (Subtarget.is64Bit() && !Subtarget.hasSSE1())) {
2293 errorUnsupported(DAG, dl, "SSE register return with SSE disabled");
2294 VA.convertToReg(X86::FP0); // Set reg to FP0, avoid hitting asserts.
2295 } else if (ValVT == MVT::f64 &&
2296 (Subtarget.is64Bit() && !Subtarget.hasSSE2())) {
2297 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
2298 // llvm-gcc has never done it right and no one has noticed, so this
2299 // should be OK for now.
2300 errorUnsupported(DAG, dl, "SSE2 register return with SSE2 disabled");
2301 VA.convertToReg(X86::FP0); // Set reg to FP0, avoid hitting asserts.
2302 }
2303
2304 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2305 // the RET instruction and handled by the FP Stackifier.
2306 if (VA.getLocReg() == X86::FP0 ||
2307 VA.getLocReg() == X86::FP1) {
2308 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2309 // change the value to the FP stack register class.
2310 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2311 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2312 RetOps.push_back(ValToCopy);
2313 // Don't emit a copytoreg.
2314 continue;
2315 }
2316
2317 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2318 // which is returned in RAX / RDX.
2319 if (Subtarget.is64Bit()) {
2320 if (ValVT == MVT::x86mmx) {
2321 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2322 ValToCopy = DAG.getBitcast(MVT::i64, ValToCopy);
2323 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2324 ValToCopy);
2325 // If we don't have SSE2 available, convert to v4f32 so the generated
2326 // register is legal.
2327 if (!Subtarget.hasSSE2())
2328 ValToCopy = DAG.getBitcast(MVT::v4f32, ValToCopy);
2329 }
2330 }
2331 }
2332
2333 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2334
2335 if (VA.needsCustom()) {
2336 assert(VA.getValVT() == MVT::v64i1 &&(static_cast <bool> (VA.getValVT() == MVT::v64i1 &&
"Currently the only custom case is when we split v64i1 to 2 regs"
) ? void (0) : __assert_fail ("VA.getValVT() == MVT::v64i1 && \"Currently the only custom case is when we split v64i1 to 2 regs\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 2337, __extension__ __PRETTY_FUNCTION__))
2337 "Currently the only custom case is when we split v64i1 to 2 regs")(static_cast <bool> (VA.getValVT() == MVT::v64i1 &&
"Currently the only custom case is when we split v64i1 to 2 regs"
) ? void (0) : __assert_fail ("VA.getValVT() == MVT::v64i1 && \"Currently the only custom case is when we split v64i1 to 2 regs\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 2337, __extension__ __PRETTY_FUNCTION__))
;
2338
2339 Passv64i1ArgInRegs(dl, DAG, Chain, ValToCopy, RegsToPass, VA, RVLocs[++I],
2340 Subtarget);
2341
2342 assert(2 == RegsToPass.size() &&(static_cast <bool> (2 == RegsToPass.size() && "Expecting two registers after Pass64BitArgInRegs"
) ? void (0) : __assert_fail ("2 == RegsToPass.size() && \"Expecting two registers after Pass64BitArgInRegs\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 2343, __extension__ __PRETTY_FUNCTION__))
2343 "Expecting two registers after Pass64BitArgInRegs")(static_cast <bool> (2 == RegsToPass.size() && "Expecting two registers after Pass64BitArgInRegs"
) ? void (0) : __assert_fail ("2 == RegsToPass.size() && \"Expecting two registers after Pass64BitArgInRegs\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 2343, __extension__ __PRETTY_FUNCTION__))
;
2344
2345 // Add the second register to the CalleeSaveDisableRegs list.
2346 if (ShouldDisableCalleeSavedRegister)
2347 MF.getRegInfo().disableCalleeSavedRegister(RVLocs[I].getLocReg());
2348 } else {
2349 RegsToPass.push_back(std::make_pair(VA.getLocReg(), ValToCopy));
2350 }
2351
2352 // Add nodes to the DAG and add the values into the RetOps list
2353 for (auto &Reg : RegsToPass) {
2354 Chain = DAG.getCopyToReg(Chain, dl, Reg.first, Reg.second, Flag);
2355 Flag = Chain.getValue(1);
2356 RetOps.push_back(DAG.getRegister(Reg.first, Reg.second.getValueType()));
2357 }
2358 }
2359
2360 // Swift calling convention does not require we copy the sret argument
2361 // into %rax/%eax for the return, and SRetReturnReg is not set for Swift.
2362
2363 // All x86 ABIs require that for returning structs by value we copy
2364 // the sret argument into %rax/%eax (depending on ABI) for the return.
2365 // We saved the argument into a virtual register in the entry block,
2366 // so now we copy the value out and into %rax/%eax.
2367 //
2368 // Checking Function.hasStructRetAttr() here is insufficient because the IR
2369 // may not have an explicit sret argument. If FuncInfo.CanLowerReturn is
2370 // false, then an sret argument may be implicitly inserted in the SelDAG. In
2371 // either case FuncInfo->setSRetReturnReg() will have been called.
2372 if (unsigned SRetReg = FuncInfo->getSRetReturnReg()) {
2373 // When we have both sret and another return value, we should use the
2374 // original Chain stored in RetOps[0], instead of the current Chain updated
2375 // in the above loop. If we only have sret, RetOps[0] equals to Chain.
2376
2377 // For the case of sret and another return value, we have
2378 // Chain_0 at the function entry
2379 // Chain_1 = getCopyToReg(Chain_0) in the above loop
2380 // If we use Chain_1 in getCopyFromReg, we will have
2381 // Val = getCopyFromReg(Chain_1)
2382 // Chain_2 = getCopyToReg(Chain_1, Val) from below
2383
2384 // getCopyToReg(Chain_0) will be glued together with
2385 // getCopyToReg(Chain_1, Val) into Unit A, getCopyFromReg(Chain_1) will be
2386 // in Unit B, and we will have cyclic dependency between Unit A and Unit B:
2387 // Data dependency from Unit B to Unit A due to usage of Val in
2388 // getCopyToReg(Chain_1, Val)
2389 // Chain dependency from Unit A to Unit B
2390
2391 // So here, we use RetOps[0] (i.e Chain_0) for getCopyFromReg.
2392 SDValue Val = DAG.getCopyFromReg(RetOps[0], dl, SRetReg,
2393 getPointerTy(MF.getDataLayout()));
2394
2395 unsigned RetValReg
2396 = (Subtarget.is64Bit() && !Subtarget.isTarget64BitILP32()) ?
2397 X86::RAX : X86::EAX;
2398 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2399 Flag = Chain.getValue(1);
2400
2401 // RAX/EAX now acts like a return value.
2402 RetOps.push_back(
2403 DAG.getRegister(RetValReg, getPointerTy(DAG.getDataLayout())));
2404
2405 // Add the returned register to the CalleeSaveDisableRegs list.
2406 if (ShouldDisableCalleeSavedRegister)
2407 MF.getRegInfo().disableCalleeSavedRegister(RetValReg);
2408 }
2409
2410 const X86RegisterInfo *TRI = Subtarget.getRegisterInfo();
2411 const MCPhysReg *I =
2412 TRI->getCalleeSavedRegsViaCopy(&DAG.getMachineFunction());
2413 if (I) {
2414 for (; *I; ++I) {
2415 if (X86::GR64RegClass.contains(*I))
2416 RetOps.push_back(DAG.getRegister(*I, MVT::i64));
2417 else
2418 llvm_unreachable("Unexpected register class in CSRsViaCopy!")::llvm::llvm_unreachable_internal("Unexpected register class in CSRsViaCopy!"
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 2418)
;
2419 }
2420 }
2421
2422 RetOps[0] = Chain; // Update chain.
2423
2424 // Add the flag if we have it.
2425 if (Flag.getNode())
2426 RetOps.push_back(Flag);
2427
2428 X86ISD::NodeType opcode = X86ISD::RET_FLAG;
2429 if (CallConv == CallingConv::X86_INTR)
2430 opcode = X86ISD::IRET;
2431 return DAG.getNode(opcode, dl, MVT::Other, RetOps);
2432}
2433
2434bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2435 if (N->getNumValues() != 1 || !N->hasNUsesOfValue(1, 0))
2436 return false;
2437
2438 SDValue TCChain = Chain;
2439 SDNode *Copy = *N->use_begin();
2440 if (Copy->getOpcode() == ISD::CopyToReg) {
2441 // If the copy has a glue operand, we conservatively assume it isn't safe to
2442 // perform a tail call.
2443 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2444 return false;
2445 TCChain = Copy->getOperand(0);
2446 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2447 return false;
2448
2449 bool HasRet = false;
2450 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2451 UI != UE; ++UI) {
2452 if (UI->getOpcode() != X86ISD::RET_FLAG)
2453 return false;
2454 // If we are returning more than one value, we can definitely
2455 // not make a tail call see PR19530
2456 if (UI->getNumOperands() > 4)
2457 return false;
2458 if (UI->getNumOperands() == 4 &&
2459 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2460 return false;
2461 HasRet = true;
2462 }
2463
2464 if (!HasRet)
2465 return false;
2466
2467 Chain = TCChain;
2468 return true;
2469}
2470
2471EVT X86TargetLowering::getTypeForExtReturn(LLVMContext &Context, EVT VT,
2472 ISD::NodeType ExtendKind) const {
2473 MVT ReturnMVT = MVT::i32;
2474
2475 bool Darwin = Subtarget.getTargetTriple().isOSDarwin();
2476 if (VT == MVT::i1 || (!Darwin && (VT == MVT::i8 || VT == MVT::i16))) {
2477 // The ABI does not require i1, i8 or i16 to be extended.
2478 //
2479 // On Darwin, there is code in the wild relying on Clang's old behaviour of
2480 // always extending i8/i16 return values, so keep doing that for now.
2481 // (PR26665).
2482 ReturnMVT = MVT::i8;
2483 }
2484
2485 EVT MinVT = getRegisterType(Context, ReturnMVT);
2486 return VT.bitsLT(MinVT) ? MinVT : VT;
2487}
2488
2489/// Reads two 32 bit registers and creates a 64 bit mask value.
2490/// \param VA The current 32 bit value that need to be assigned.
2491/// \param NextVA The next 32 bit value that need to be assigned.
2492/// \param Root The parent DAG node.
2493/// \param [in,out] InFlag Represents SDvalue in the parent DAG node for
2494/// glue purposes. In the case the DAG is already using
2495/// physical register instead of virtual, we should glue
2496/// our new SDValue to InFlag SDvalue.
2497/// \return a new SDvalue of size 64bit.
2498static SDValue getv64i1Argument(CCValAssign &VA, CCValAssign &NextVA,
2499 SDValue &Root, SelectionDAG &DAG,
2500 const SDLoc &Dl, const X86Subtarget &Subtarget,
2501 SDValue *InFlag = nullptr) {
2502 assert((Subtarget.hasBWI()) && "Expected AVX512BW target!")(static_cast <bool> ((Subtarget.hasBWI()) && "Expected AVX512BW target!"
) ? void (0) : __assert_fail ("(Subtarget.hasBWI()) && \"Expected AVX512BW target!\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 2502, __extension__ __PRETTY_FUNCTION__))
;
2503 assert(Subtarget.is32Bit() && "Expecting 32 bit target")(static_cast <bool> (Subtarget.is32Bit() && "Expecting 32 bit target"
) ? void (0) : __assert_fail ("Subtarget.is32Bit() && \"Expecting 32 bit target\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 2503, __extension__ __PRETTY_FUNCTION__))
;
2504 assert(VA.getValVT() == MVT::v64i1 &&(static_cast <bool> (VA.getValVT() == MVT::v64i1 &&
"Expecting first location of 64 bit width type") ? void (0) :
__assert_fail ("VA.getValVT() == MVT::v64i1 && \"Expecting first location of 64 bit width type\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 2505, __extension__ __PRETTY_FUNCTION__))
2505 "Expecting first location of 64 bit width type")(static_cast <bool> (VA.getValVT() == MVT::v64i1 &&
"Expecting first location of 64 bit width type") ? void (0) :
__assert_fail ("VA.getValVT() == MVT::v64i1 && \"Expecting first location of 64 bit width type\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 2505, __extension__ __PRETTY_FUNCTION__))
;
2506 assert(NextVA.getValVT() == VA.getValVT() &&(static_cast <bool> (NextVA.getValVT() == VA.getValVT()
&& "The locations should have the same type") ? void
(0) : __assert_fail ("NextVA.getValVT() == VA.getValVT() && \"The locations should have the same type\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 2507, __extension__ __PRETTY_FUNCTION__))
2507 "The locations should have the same type")(static_cast <bool> (NextVA.getValVT() == VA.getValVT()
&& "The locations should have the same type") ? void
(0) : __assert_fail ("NextVA.getValVT() == VA.getValVT() && \"The locations should have the same type\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 2507, __extension__ __PRETTY_FUNCTION__))
;
2508 assert(VA.isRegLoc() && NextVA.isRegLoc() &&(static_cast <bool> (VA.isRegLoc() && NextVA.isRegLoc
() && "The values should reside in two registers") ? void
(0) : __assert_fail ("VA.isRegLoc() && NextVA.isRegLoc() && \"The values should reside in two registers\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 2509, __extension__ __PRETTY_FUNCTION__))
2509 "The values should reside in two registers")(static_cast <bool> (VA.isRegLoc() && NextVA.isRegLoc
() && "The values should reside in two registers") ? void
(0) : __assert_fail ("VA.isRegLoc() && NextVA.isRegLoc() && \"The values should reside in two registers\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 2509, __extension__ __PRETTY_FUNCTION__))
;
2510
2511 SDValue Lo, Hi;
2512 unsigned Reg;
2513 SDValue ArgValueLo, ArgValueHi;
2514
2515 MachineFunction &MF = DAG.getMachineFunction();
2516 const TargetRegisterClass *RC = &X86::GR32RegClass;
2517
2518 // Read a 32 bit value from the registers
2519 if (nullptr == InFlag) {
2520 // When no physical register is present,
2521 // create an intermediate virtual register
2522 Reg = MF.addLiveIn(VA.getLocReg(), RC);
2523 ArgValueLo = DAG.getCopyFromReg(Root, Dl, Reg, MVT::i32);
2524 Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
2525 ArgValueHi = DAG.getCopyFromReg(Root, Dl, Reg, MVT::i32);
2526 } else {
2527 // When a physical register is available read the value from it and glue
2528 // the reads together.
2529 ArgValueLo =
2530 DAG.getCopyFromReg(Root, Dl, VA.getLocReg(), MVT::i32, *InFlag);
2531 *InFlag = ArgValueLo.getValue(2);
2532 ArgValueHi =
2533 DAG.getCopyFromReg(Root, Dl, NextVA.getLocReg(), MVT::i32, *InFlag);
2534 *InFlag = ArgValueHi.getValue(2);
2535 }
2536
2537 // Convert the i32 type into v32i1 type
2538 Lo = DAG.getBitcast(MVT::v32i1, ArgValueLo);
2539
2540 // Convert the i32 type into v32i1 type
2541 Hi = DAG.getBitcast(MVT::v32i1, ArgValueHi);
2542
2543 // Concatenate the two values together
2544 return DAG.getNode(ISD::CONCAT_VECTORS, Dl, MVT::v64i1, Lo, Hi);
2545}
2546
2547/// The function will lower a register of various sizes (8/16/32/64)
2548/// to a mask value of the expected size (v8i1/v16i1/v32i1/v64i1)
2549/// \returns a DAG node contains the operand after lowering to mask type.
2550static SDValue lowerRegToMasks(const SDValue &ValArg, const EVT &ValVT,
2551 const EVT &ValLoc, const SDLoc &Dl,
2552 SelectionDAG &DAG) {
2553 SDValue ValReturned = ValArg;
2554
2555 if (ValVT == MVT::v1i1)
2556 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Dl, MVT::v1i1, ValReturned);
2557
2558 if (ValVT == MVT::v64i1) {
2559 // In 32 bit machine, this case is handled by getv64i1Argument
2560 assert(ValLoc == MVT::i64 && "Expecting only i64 locations")(static_cast <bool> (ValLoc == MVT::i64 && "Expecting only i64 locations"
) ? void (0) : __assert_fail ("ValLoc == MVT::i64 && \"Expecting only i64 locations\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 2560, __extension__ __PRETTY_FUNCTION__))
;
2561 // In 64 bit machine, There is no need to truncate the value only bitcast
2562 } else {
2563 MVT maskLen;
2564 switch (ValVT.getSimpleVT().SimpleTy) {
2565 case MVT::v8i1:
2566 maskLen = MVT::i8;
2567 break;
2568 case MVT::v16i1:
2569 maskLen = MVT::i16;
2570 break;
2571 case MVT::v32i1:
2572 maskLen = MVT::i32;
2573 break;
2574 default:
2575 llvm_unreachable("Expecting a vector of i1 types")::llvm::llvm_unreachable_internal("Expecting a vector of i1 types"
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 2575)
;
2576 }
2577
2578 ValReturned = DAG.getNode(ISD::TRUNCATE, Dl, maskLen, ValReturned);
2579 }
2580 return DAG.getBitcast(ValVT, ValReturned);
2581}
2582
2583/// Lower the result values of a call into the
2584/// appropriate copies out of appropriate physical registers.
2585///
2586SDValue X86TargetLowering::LowerCallResult(
2587 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
2588 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
2589 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals,
2590 uint32_t *RegMask) const {
2591
2592 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
2593 // Assign locations to each value returned by this call.
2594 SmallVector<CCValAssign, 16> RVLocs;
2595 bool Is64Bit = Subtarget.is64Bit();
2596 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2597 *DAG.getContext());
2598 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2599
2600 // Copy all of the result registers out of their specified physreg.
2601 for (unsigned I = 0, InsIndex = 0, E = RVLocs.size(); I != E;
2602 ++I, ++InsIndex) {
2603 CCValAssign &VA = RVLocs[I];
2604 EVT CopyVT = VA.getLocVT();
2605
2606 // In some calling conventions we need to remove the used registers
2607 // from the register mask.
2608 if (RegMask) {
2609 for (MCSubRegIterator SubRegs(VA.getLocReg(), TRI, /*IncludeSelf=*/true);
2610 SubRegs.isValid(); ++SubRegs)
2611 RegMask[*SubRegs / 32] &= ~(1u << (*SubRegs % 32));
2612 }
2613
2614 // If this is x86-64, and we disabled SSE, we can't return FP values
2615 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64 || CopyVT == MVT::f128) &&
2616 ((Is64Bit || Ins[InsIndex].Flags.isInReg()) && !Subtarget.hasSSE1())) {
2617 errorUnsupported(DAG, dl, "SSE register return with SSE disabled");
2618 VA.convertToReg(X86::FP0); // Set reg to FP0, avoid hitting asserts.
2619 }
2620
2621 // If we prefer to use the value in xmm registers, copy it out as f80 and
2622 // use a truncate to move it from fp stack reg to xmm reg.
2623 bool RoundAfterCopy = false;
2624 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2625 isScalarFPTypeInSSEReg(VA.getValVT())) {
2626 if (!Subtarget.hasX87())
2627 report_fatal_error("X87 register return with X87 disabled");
2628 CopyVT = MVT::f80;
2629 RoundAfterCopy = (CopyVT != VA.getLocVT());
2630 }
2631
2632 SDValue Val;
2633 if (VA.needsCustom()) {
2634 assert(VA.getValVT() == MVT::v64i1 &&(static_cast <bool> (VA.getValVT() == MVT::v64i1 &&
"Currently the only custom case is when we split v64i1 to 2 regs"
) ? void (0) : __assert_fail ("VA.getValVT() == MVT::v64i1 && \"Currently the only custom case is when we split v64i1 to 2 regs\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 2635, __extension__ __PRETTY_FUNCTION__))
2635 "Currently the only custom case is when we split v64i1 to 2 regs")(static_cast <bool> (VA.getValVT() == MVT::v64i1 &&
"Currently the only custom case is when we split v64i1 to 2 regs"
) ? void (0) : __assert_fail ("VA.getValVT() == MVT::v64i1 && \"Currently the only custom case is when we split v64i1 to 2 regs\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 2635, __extension__ __PRETTY_FUNCTION__))
;
2636 Val =
2637 getv64i1Argument(VA, RVLocs[++I], Chain, DAG, dl, Subtarget, &InFlag);
2638 } else {
2639 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), CopyVT, InFlag)
2640 .getValue(1);
2641 Val = Chain.getValue(0);
2642 InFlag = Chain.getValue(2);
2643 }
2644
2645 if (RoundAfterCopy)
2646 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2647 // This truncation won't change the value.
2648 DAG.getIntPtrConstant(1, dl));
2649
2650 if (VA.isExtInLoc() && (VA.getValVT().getScalarType() == MVT::i1)) {
2651 if (VA.getValVT().isVector() &&
2652 ((VA.getLocVT() == MVT::i64) || (VA.getLocVT() == MVT::i32) ||
2653 (VA.getLocVT() == MVT::i16) || (VA.getLocVT() == MVT::i8))) {
2654 // promoting a mask type (v*i1) into a register of type i64/i32/i16/i8
2655 Val = lowerRegToMasks(Val, VA.getValVT(), VA.getLocVT(), dl, DAG);
2656 } else
2657 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
2658 }
2659
2660 InVals.push_back(Val);
2661 }
2662
2663 return Chain;
2664}
2665
2666//===----------------------------------------------------------------------===//
2667// C & StdCall & Fast Calling Convention implementation
2668//===----------------------------------------------------------------------===//
2669// StdCall calling convention seems to be standard for many Windows' API
2670// routines and around. It differs from C calling convention just a little:
2671// callee should clean up the stack, not caller. Symbols should be also
2672// decorated in some fancy way :) It doesn't support any vector arguments.
2673// For info on fast calling convention see Fast Calling Convention (tail call)
2674// implementation LowerX86_32FastCCCallTo.
2675
2676/// CallIsStructReturn - Determines whether a call uses struct return
2677/// semantics.
2678enum StructReturnType {
2679 NotStructReturn,
2680 RegStructReturn,
2681 StackStructReturn
2682};
2683static StructReturnType
2684callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs, bool IsMCU) {
2685 if (Outs.empty())
2686 return NotStructReturn;
2687
2688 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2689 if (!Flags.isSRet())
2690 return NotStructReturn;
2691 if (Flags.isInReg() || IsMCU)
2692 return RegStructReturn;
2693 return StackStructReturn;
2694}
2695
2696/// Determines whether a function uses struct return semantics.
2697static StructReturnType
2698argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins, bool IsMCU) {
2699 if (Ins.empty())
2700 return NotStructReturn;
2701
2702 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2703 if (!Flags.isSRet())
2704 return NotStructReturn;
2705 if (Flags.isInReg() || IsMCU)
2706 return RegStructReturn;
2707 return StackStructReturn;
2708}
2709
2710/// Make a copy of an aggregate at address specified by "Src" to address
2711/// "Dst" with size and alignment information specified by the specific
2712/// parameter attribute. The copy will be passed as a byval function parameter.
2713static SDValue CreateCopyOfByValArgument(SDValue Src, SDValue Dst,
2714 SDValue Chain, ISD::ArgFlagsTy Flags,
2715 SelectionDAG &DAG, const SDLoc &dl) {
2716 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
2717
2718 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2719 /*isVolatile*/false, /*AlwaysInline=*/true,
2720 /*isTailCall*/false,
2721 MachinePointerInfo(), MachinePointerInfo());
2722}
2723
2724/// Return true if the calling convention is one that we can guarantee TCO for.
2725static bool canGuaranteeTCO(CallingConv::ID CC) {
2726 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2727 CC == CallingConv::X86_RegCall || CC == CallingConv::HiPE ||
2728 CC == CallingConv::HHVM);
2729}
2730
2731/// Return true if we might ever do TCO for calls with this calling convention.
2732static bool mayTailCallThisCC(CallingConv::ID CC) {
2733 switch (CC) {
2734 // C calling conventions:
2735 case CallingConv::C:
2736 case CallingConv::Win64:
2737 case CallingConv::X86_64_SysV:
2738 // Callee pop conventions:
2739 case CallingConv::X86_ThisCall:
2740 case CallingConv::X86_StdCall:
2741 case CallingConv::X86_VectorCall:
2742 case CallingConv::X86_FastCall:
2743 return true;
2744 default:
2745 return canGuaranteeTCO(CC);
2746 }
2747}
2748
2749/// Return true if the function is being made into a tailcall target by
2750/// changing its ABI.
2751static bool shouldGuaranteeTCO(CallingConv::ID CC, bool GuaranteedTailCallOpt) {
2752 return GuaranteedTailCallOpt && canGuaranteeTCO(CC);
2753}
2754
2755bool X86TargetLowering::mayBeEmittedAsTailCall(const CallInst *CI) const {
2756 auto Attr =
2757 CI->getParent()->getParent()->getFnAttribute("disable-tail-calls");
2758 if (!CI->isTailCall() || Attr.getValueAsString() == "true")
2759 return false;
2760
2761 ImmutableCallSite CS(CI);
2762 CallingConv::ID CalleeCC = CS.getCallingConv();
2763 if (!mayTailCallThisCC(CalleeCC))
2764 return false;
2765
2766 return true;
2767}
2768
2769SDValue
2770X86TargetLowering::LowerMemArgument(SDValue Chain, CallingConv::ID CallConv,
2771 const SmallVectorImpl<ISD::InputArg> &Ins,
2772 const SDLoc &dl, SelectionDAG &DAG,
2773 const CCValAssign &VA,
2774 MachineFrameInfo &MFI, unsigned i) const {
2775 // Create the nodes corresponding to a load from this parameter slot.
2776 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2777 bool AlwaysUseMutable = shouldGuaranteeTCO(
2778 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2779 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2780 EVT ValVT;
2781 MVT PtrVT = getPointerTy(DAG.getDataLayout());
2782
2783 // If value is passed by pointer we have address passed instead of the value
2784 // itself. No need to extend if the mask value and location share the same
2785 // absolute size.
2786 bool ExtendedInMem =
2787 VA.isExtInLoc() && VA.getValVT().getScalarType() == MVT::i1 &&
2788 VA.getValVT().getSizeInBits() != VA.getLocVT().getSizeInBits();
2789
2790 if (VA.getLocInfo() == CCValAssign::Indirect || ExtendedInMem)
2791 ValVT = VA.getLocVT();
2792 else
2793 ValVT = VA.getValVT();
2794
2795 // Calculate SP offset of interrupt parameter, re-arrange the slot normally
2796 // taken by a return address.
2797 int Offset = 0;
2798 if (CallConv == CallingConv::X86_INTR) {
2799 // X86 interrupts may take one or two arguments.
2800 // On the stack there will be no return address as in regular call.
2801 // Offset of last argument need to be set to -4/-8 bytes.
2802 // Where offset of the first argument out of two, should be set to 0 bytes.
2803 Offset = (Subtarget.is64Bit() ? 8 : 4) * ((i + 1) % Ins.size() - 1);
2804 if (Subtarget.is64Bit() && Ins.size() == 2) {
2805 // The stack pointer needs to be realigned for 64 bit handlers with error
2806 // code, so the argument offset changes by 8 bytes.
2807 Offset += 8;
2808 }
2809 }
2810
2811 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2812 // changed with more analysis.
2813 // In case of tail call optimization mark all arguments mutable. Since they
2814 // could be overwritten by lowering of arguments in case of a tail call.
2815 if (Flags.isByVal()) {
2816 unsigned Bytes = Flags.getByValSize();
2817 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2818 int FI = MFI.CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2819 // Adjust SP offset of interrupt parameter.
2820 if (CallConv == CallingConv::X86_INTR) {
2821 MFI.setObjectOffset(FI, Offset);
2822 }
2823 return DAG.getFrameIndex(FI, PtrVT);
2824 }
2825
2826 // This is an argument in memory. We might be able to perform copy elision.
2827 if (Flags.isCopyElisionCandidate()) {
2828 EVT ArgVT = Ins[i].ArgVT;
2829 SDValue PartAddr;
2830 if (Ins[i].PartOffset == 0) {
2831 // If this is a one-part value or the first part of a multi-part value,
2832 // create a stack object for the entire argument value type and return a
2833 // load from our portion of it. This assumes that if the first part of an
2834 // argument is in memory, the rest will also be in memory.
2835 int FI = MFI.CreateFixedObject(ArgVT.getStoreSize(), VA.getLocMemOffset(),
2836 /*Immutable=*/false);
2837 PartAddr = DAG.getFrameIndex(FI, PtrVT);
2838 return DAG.getLoad(
2839 ValVT, dl, Chain, PartAddr,
2840 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI));
2841 } else {
2842 // This is not the first piece of an argument in memory. See if there is
2843 // already a fixed stack object including this offset. If so, assume it
2844 // was created by the PartOffset == 0 branch above and create a load from
2845 // the appropriate offset into it.
2846 int64_t PartBegin = VA.getLocMemOffset();
2847 int64_t PartEnd = PartBegin + ValVT.getSizeInBits() / 8;
2848 int FI = MFI.getObjectIndexBegin();
2849 for (; MFI.isFixedObjectIndex(FI); ++FI) {
2850 int64_t ObjBegin = MFI.getObjectOffset(FI);
2851 int64_t ObjEnd = ObjBegin + MFI.getObjectSize(FI);
2852 if (ObjBegin <= PartBegin && PartEnd <= ObjEnd)
2853 break;
2854 }
2855 if (MFI.isFixedObjectIndex(FI)) {
2856 SDValue Addr =
2857 DAG.getNode(ISD::ADD, dl, PtrVT, DAG.getFrameIndex(FI, PtrVT),
2858 DAG.getIntPtrConstant(Ins[i].PartOffset, dl));
2859 return DAG.getLoad(
2860 ValVT, dl, Chain, Addr,
2861 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI,
2862 Ins[i].PartOffset));
2863 }
2864 }
2865 }
2866
2867 int FI = MFI.CreateFixedObject(ValVT.getSizeInBits() / 8,
2868 VA.getLocMemOffset(), isImmutable);
2869
2870 // Set SExt or ZExt flag.
2871 if (VA.getLocInfo() == CCValAssign::ZExt) {
2872 MFI.setObjectZExt(FI, true);
2873 } else if (VA.getLocInfo() == CCValAssign::SExt) {
2874 MFI.setObjectSExt(FI, true);
2875 }
2876
2877 // Adjust SP offset of interrupt parameter.
2878 if (CallConv == CallingConv::X86_INTR) {
2879 MFI.setObjectOffset(FI, Offset);
2880 }
2881
2882 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2883 SDValue Val = DAG.getLoad(
2884 ValVT, dl, Chain, FIN,
2885 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI));
2886 return ExtendedInMem
2887 ? (VA.getValVT().isVector()
2888 ? DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VA.getValVT(), Val)
2889 : DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val))
2890 : Val;
2891}
2892
2893// FIXME: Get this from tablegen.
2894static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2895 const X86Subtarget &Subtarget) {
2896 assert(Subtarget.is64Bit())(static_cast <bool> (Subtarget.is64Bit()) ? void (0) : __assert_fail
("Subtarget.is64Bit()", "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 2896, __extension__ __PRETTY_FUNCTION__))
;
2897
2898 if (Subtarget.isCallingConvWin64(CallConv)) {
2899 static const MCPhysReg GPR64ArgRegsWin64[] = {
2900 X86::RCX, X86::RDX, X86::R8, X86::R9
2901 };
2902 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2903 }
2904
2905 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2906 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2907 };
2908 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2909}
2910
2911// FIXME: Get this from tablegen.
2912static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2913 CallingConv::ID CallConv,
2914 const X86Subtarget &Subtarget) {
2915 assert(Subtarget.is64Bit())(static_cast <bool> (Subtarget.is64Bit()) ? void (0) : __assert_fail
("Subtarget.is64Bit()", "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 2915, __extension__ __PRETTY_FUNCTION__))
;
2916 if (Subtarget.isCallingConvWin64(CallConv)) {
2917 // The XMM registers which might contain var arg parameters are shadowed
2918 // in their paired GPR. So we only need to save the GPR to their home
2919 // slots.
2920 // TODO: __vectorcall will change this.
2921 return None;
2922 }
2923
2924 const Function &F = MF.getFunction();
2925 bool NoImplicitFloatOps = F.hasFnAttribute(Attribute::NoImplicitFloat);
2926 bool isSoftFloat = Subtarget.useSoftFloat();
2927 assert(!(isSoftFloat && NoImplicitFloatOps) &&(static_cast <bool> (!(isSoftFloat && NoImplicitFloatOps
) && "SSE register cannot be used when SSE is disabled!"
) ? void (0) : __assert_fail ("!(isSoftFloat && NoImplicitFloatOps) && \"SSE register cannot be used when SSE is disabled!\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 2928, __extension__ __PRETTY_FUNCTION__))
2928 "SSE register cannot be used when SSE is disabled!")(static_cast <bool> (!(isSoftFloat && NoImplicitFloatOps
) && "SSE register cannot be used when SSE is disabled!"
) ? void (0) : __assert_fail ("!(isSoftFloat && NoImplicitFloatOps) && \"SSE register cannot be used when SSE is disabled!\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 2928, __extension__ __PRETTY_FUNCTION__))
;
2929 if (isSoftFloat || NoImplicitFloatOps || !Subtarget.hasSSE1())
2930 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2931 // registers.
2932 return None;
2933
2934 static const MCPhysReg XMMArgRegs64Bit[] = {
2935 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2936 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2937 };
2938 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2939}
2940
2941#ifndef NDEBUG
2942static bool isSortedByValueNo(const SmallVectorImpl<CCValAssign> &ArgLocs) {
2943 return std::is_sorted(ArgLocs.begin(), ArgLocs.end(),
2944 [](const CCValAssign &A, const CCValAssign &B) -> bool {
2945 return A.getValNo() < B.getValNo();
2946 });
2947}
2948#endif
2949
2950SDValue X86TargetLowering::LowerFormalArguments(
2951 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
2952 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
2953 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
2954 MachineFunction &MF = DAG.getMachineFunction();
2955 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2956 const TargetFrameLowering &TFI = *Subtarget.getFrameLowering();
2957
2958 const Function &F = MF.getFunction();
2959 if (F.hasExternalLinkage() && Subtarget.isTargetCygMing() &&
2960 F.getName() == "main")
2961 FuncInfo->setForceFramePointer(true);
2962
2963 MachineFrameInfo &MFI = MF.getFrameInfo();
2964 bool Is64Bit = Subtarget.is64Bit();
2965 bool IsWin64 = Subtarget.isCallingConvWin64(CallConv);
2966
2967 assert((static_cast <bool> (!(isVarArg && canGuaranteeTCO
(CallConv)) && "Var args not supported with calling conv' regcall, fastcc, ghc or hipe"
) ? void (0) : __assert_fail ("!(isVarArg && canGuaranteeTCO(CallConv)) && \"Var args not supported with calling conv' regcall, fastcc, ghc or hipe\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 2969, __extension__ __PRETTY_FUNCTION__))
2968 !(isVarArg && canGuaranteeTCO(CallConv)) &&(static_cast <bool> (!(isVarArg && canGuaranteeTCO
(CallConv)) && "Var args not supported with calling conv' regcall, fastcc, ghc or hipe"
) ? void (0) : __assert_fail ("!(isVarArg && canGuaranteeTCO(CallConv)) && \"Var args not supported with calling conv' regcall, fastcc, ghc or hipe\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 2969, __extension__ __PRETTY_FUNCTION__))
2969 "Var args not supported with calling conv' regcall, fastcc, ghc or hipe")(static_cast <bool> (!(isVarArg && canGuaranteeTCO
(CallConv)) && "Var args not supported with calling conv' regcall, fastcc, ghc or hipe"
) ? void (0) : __assert_fail ("!(isVarArg && canGuaranteeTCO(CallConv)) && \"Var args not supported with calling conv' regcall, fastcc, ghc or hipe\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 2969, __extension__ __PRETTY_FUNCTION__))
;
2970
2971 if (CallConv == CallingConv::X86_INTR) {
2972 bool isLegal = Ins.size() == 1 ||
2973 (Ins.size() == 2 && ((Is64Bit && Ins[1].VT == MVT::i64) ||
2974 (!Is64Bit && Ins[1].VT == MVT::i32)));
2975 if (!isLegal)
2976 report_fatal_error("X86 interrupts may take one or two arguments");
2977 }
2978
2979 // Assign locations to all of the incoming arguments.
2980 SmallVector<CCValAssign, 16> ArgLocs;
2981 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2982
2983 // Allocate shadow area for Win64.
2984 if (IsWin64)
2985 CCInfo.AllocateStack(32, 8);
2986
2987 CCInfo.AnalyzeArguments(Ins, CC_X86);
2988
2989 // In vectorcall calling convention a second pass is required for the HVA
2990 // types.
2991 if (CallingConv::X86_VectorCall == CallConv) {
2992 CCInfo.AnalyzeArgumentsSecondPass(Ins, CC_X86);
2993 }
2994
2995 // The next loop assumes that the locations are in the same order of the
2996 // input arguments.
2997 assert(isSortedByValueNo(ArgLocs) &&(static_cast <bool> (isSortedByValueNo(ArgLocs) &&
"Argument Location list must be sorted before lowering") ? void
(0) : __assert_fail ("isSortedByValueNo(ArgLocs) && \"Argument Location list must be sorted before lowering\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 2998, __extension__ __PRETTY_FUNCTION__))
2998 "Argument Location list must be sorted before lowering")(static_cast <bool> (isSortedByValueNo(ArgLocs) &&
"Argument Location list must be sorted before lowering") ? void
(0) : __assert_fail ("isSortedByValueNo(ArgLocs) && \"Argument Location list must be sorted before lowering\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 2998, __extension__ __PRETTY_FUNCTION__))
;
2999
3000 SDValue ArgValue;
3001 for (unsigned I = 0, InsIndex = 0, E = ArgLocs.size(); I != E;
3002 ++I, ++InsIndex) {
3003 assert(InsIndex < Ins.size() && "Invalid Ins index")(static_cast <bool> (InsIndex < Ins.size() &&
"Invalid Ins index") ? void (0) : __assert_fail ("InsIndex < Ins.size() && \"Invalid Ins index\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 3003, __extension__ __PRETTY_FUNCTION__))
;
3004 CCValAssign &VA = ArgLocs[I];
3005
3006 if (VA.isRegLoc()) {
3007 EVT RegVT = VA.getLocVT();
3008 if (VA.needsCustom()) {
3009 assert((static_cast <bool> (VA.getValVT() == MVT::v64i1 &&
"Currently the only custom case is when we split v64i1 to 2 regs"
) ? void (0) : __assert_fail ("VA.getValVT() == MVT::v64i1 && \"Currently the only custom case is when we split v64i1 to 2 regs\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 3011, __extension__ __PRETTY_FUNCTION__))
3010 VA.getValVT() == MVT::v64i1 &&(static_cast <bool> (VA.getValVT() == MVT::v64i1 &&
"Currently the only custom case is when we split v64i1 to 2 regs"
) ? void (0) : __assert_fail ("VA.getValVT() == MVT::v64i1 && \"Currently the only custom case is when we split v64i1 to 2 regs\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 3011, __extension__ __PRETTY_FUNCTION__))
3011 "Currently the only custom case is when we split v64i1 to 2 regs")(static_cast <bool> (VA.getValVT() == MVT::v64i1 &&
"Currently the only custom case is when we split v64i1 to 2 regs"
) ? void (0) : __assert_fail ("VA.getValVT() == MVT::v64i1 && \"Currently the only custom case is when we split v64i1 to 2 regs\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 3011, __extension__ __PRETTY_FUNCTION__))
;
3012
3013 // v64i1 values, in regcall calling convention, that are
3014 // compiled to 32 bit arch, are split up into two registers.
3015 ArgValue =
3016 getv64i1Argument(VA, ArgLocs[++I], Chain, DAG, dl, Subtarget);
3017 } else {
3018 const TargetRegisterClass *RC;
3019 if (RegVT == MVT::i32)
3020 RC = &X86::GR32RegClass;
3021 else if (Is64Bit && RegVT == MVT::i64)
3022 RC = &X86::GR64RegClass;
3023 else if (RegVT == MVT::f32)
3024 RC = Subtarget.hasAVX512() ? &X86::FR32XRegClass : &X86::FR32RegClass;
3025 else if (RegVT == MVT::f64)
3026 RC = Subtarget.hasAVX512() ? &X86::FR64XRegClass : &X86::FR64RegClass;
3027 else if (RegVT == MVT::f80)
3028 RC = &X86::RFP80RegClass;
3029 else if (RegVT == MVT::f128)
3030 RC = &X86::FR128RegClass;
3031 else if (RegVT.is512BitVector())
3032 RC = &X86::VR512RegClass;
3033 else if (RegVT.is256BitVector())
3034 RC = Subtarget.hasVLX() ? &X86::VR256XRegClass : &X86::VR256RegClass;
3035 else if (RegVT.is128BitVector())
3036 RC = Subtarget.hasVLX() ? &X86::VR128XRegClass : &X86::VR128RegClass;
3037 else if (RegVT == MVT::x86mmx)
3038 RC = &X86::VR64RegClass;
3039 else if (RegVT == MVT::v1i1)
3040 RC = &X86::VK1RegClass;
3041 else if (RegVT == MVT::v8i1)
3042 RC = &X86::VK8RegClass;
3043 else if (RegVT == MVT::v16i1)
3044 RC = &X86::VK16RegClass;
3045 else if (RegVT == MVT::v32i1)
3046 RC = &X86::VK32RegClass;
3047 else if (RegVT == MVT::v64i1)
3048 RC = &X86::VK64RegClass;
3049 else
3050 llvm_unreachable("Unknown argument type!")::llvm::llvm_unreachable_internal("Unknown argument type!", "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 3050)
;
3051
3052 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
3053 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
3054 }
3055
3056 // If this is an 8 or 16-bit value, it is really passed promoted to 32
3057 // bits. Insert an assert[sz]ext to capture this, then truncate to the
3058 // right size.
3059 if (VA.getLocInfo() == CCValAssign::SExt)
3060 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
3061 DAG.getValueType(VA.getValVT()));
3062 else if (VA.getLocInfo() == CCValAssign::ZExt)
3063 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
3064 DAG.getValueType(VA.getValVT()));
3065 else if (VA.getLocInfo() == CCValAssign::BCvt)
3066 ArgValue = DAG.getBitcast(VA.getValVT(), ArgValue);
3067
3068 if (VA.isExtInLoc()) {
3069 // Handle MMX values passed in XMM regs.
3070 if (RegVT.isVector() && VA.getValVT().getScalarType() != MVT::i1)
3071 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
3072 else if (VA.getValVT().isVector() &&
3073 VA.getValVT().getScalarType() == MVT::i1 &&
3074 ((VA.getLocVT() == MVT::i64) || (VA.getLocVT() == MVT::i32) ||
3075 (VA.getLocVT() == MVT::i16) || (VA.getLocVT() == MVT::i8))) {
3076 // Promoting a mask type (v*i1) into a register of type i64/i32/i16/i8
3077 ArgValue = lowerRegToMasks(ArgValue, VA.getValVT(), RegVT, dl, DAG);
3078 } else
3079 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
3080 }
3081 } else {
3082 assert(VA.isMemLoc())(static_cast <bool> (VA.isMemLoc()) ? void (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 3082, __extension__ __PRETTY_FUNCTION__))
;
3083 ArgValue =
3084 LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, InsIndex);
3085 }
3086
3087 // If value is passed via pointer - do a load.
3088 if (VA.getLocInfo() == CCValAssign::Indirect)
3089 ArgValue =
3090 DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue, MachinePointerInfo());
3091
3092 InVals.push_back(ArgValue);
3093 }
3094
3095 for (unsigned I = 0, E = Ins.size(); I != E; ++I) {
3096 // Swift calling convention does not require we copy the sret argument
3097 // into %rax/%eax for the return. We don't set SRetReturnReg for Swift.
3098 if (CallConv == CallingConv::Swift)
3099 continue;
3100
3101 // All x86 ABIs require that for returning structs by value we copy the
3102 // sret argument into %rax/%eax (depending on ABI) for the return. Save
3103 // the argument into a virtual register so that we can access it from the
3104 // return points.
3105 if (Ins[I].Flags.isSRet()) {
3106 unsigned Reg = FuncInfo->getSRetReturnReg();
3107 if (!Reg) {
3108 MVT PtrTy = getPointerTy(DAG.getDataLayout());
3109 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
3110 FuncInfo->setSRetReturnReg(Reg);
3111 }
3112 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[I]);
3113 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
3114 break;
3115 }
3116 }
3117
3118 unsigned StackSize = CCInfo.getNextStackOffset();
3119 // Align stack specially for tail calls.
3120 if (shouldGuaranteeTCO(CallConv,
3121 MF.getTarget().Options.GuaranteedTailCallOpt))
3122 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
3123
3124 // If the function takes variable number of arguments, make a frame index for
3125 // the start of the first vararg value... for expansion of llvm.va_start. We
3126 // can skip this if there are no va_start calls.
3127 if (MFI.hasVAStart() &&
3128 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
3129 CallConv != CallingConv::X86_ThisCall))) {
3130 FuncInfo->setVarArgsFrameIndex(MFI.CreateFixedObject(1, StackSize, true));
3131 }
3132
3133 // Figure out if XMM registers are in use.
3134 assert(!(Subtarget.useSoftFloat() &&(static_cast <bool> (!(Subtarget.useSoftFloat() &&
F.hasFnAttribute(Attribute::NoImplicitFloat)) && "SSE register cannot be used when SSE is disabled!"
) ? void (0) : __assert_fail ("!(Subtarget.useSoftFloat() && F.hasFnAttribute(Attribute::NoImplicitFloat)) && \"SSE register cannot be used when SSE is disabled!\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 3136, __extension__ __PRETTY_FUNCTION__))
3135 F.hasFnAttribute(Attribute::NoImplicitFloat)) &&(static_cast <bool> (!(Subtarget.useSoftFloat() &&
F.hasFnAttribute(Attribute::NoImplicitFloat)) && "SSE register cannot be used when SSE is disabled!"
) ? void (0) : __assert_fail ("!(Subtarget.useSoftFloat() && F.hasFnAttribute(Attribute::NoImplicitFloat)) && \"SSE register cannot be used when SSE is disabled!\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 3136, __extension__ __PRETTY_FUNCTION__))
3136 "SSE register cannot be used when SSE is disabled!")(static_cast <bool> (!(Subtarget.useSoftFloat() &&
F.hasFnAttribute(Attribute::NoImplicitFloat)) && "SSE register cannot be used when SSE is disabled!"
) ? void (0) : __assert_fail ("!(Subtarget.useSoftFloat() && F.hasFnAttribute(Attribute::NoImplicitFloat)) && \"SSE register cannot be used when SSE is disabled!\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 3136, __extension__ __PRETTY_FUNCTION__))
;
3137
3138 // 64-bit calling conventions support varargs and register parameters, so we
3139 // have to do extra work to spill them in the prologue.
3140 if (Is64Bit && isVarArg && MFI.hasVAStart()) {
3141 // Find the first unallocated argument registers.
3142 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
3143 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
3144 unsigned NumIntRegs = CCInfo.getFirstUnallocated(ArgGPRs);
3145 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(ArgXMMs);
3146 assert(!(NumXMMRegs && !Subtarget.hasSSE1()) &&(static_cast <bool> (!(NumXMMRegs && !Subtarget
.hasSSE1()) && "SSE register cannot be used when SSE is disabled!"
) ? void (0) : __assert_fail ("!(NumXMMRegs && !Subtarget.hasSSE1()) && \"SSE register cannot be used when SSE is disabled!\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 3147, __extension__ __PRETTY_FUNCTION__))
3147 "SSE register cannot be used when SSE is disabled!")(static_cast <bool> (!(NumXMMRegs && !Subtarget
.hasSSE1()) && "SSE register cannot be used when SSE is disabled!"
) ? void (0) : __assert_fail ("!(NumXMMRegs && !Subtarget.hasSSE1()) && \"SSE register cannot be used when SSE is disabled!\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 3147, __extension__ __PRETTY_FUNCTION__))
;
3148
3149 // Gather all the live in physical registers.
3150 SmallVector<SDValue, 6> LiveGPRs;
3151 SmallVector<SDValue, 8> LiveXMMRegs;
3152 SDValue ALVal;
3153 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
3154 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
3155 LiveGPRs.push_back(
3156 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
3157 }
3158 if (!ArgXMMs.empty()) {
3159 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
3160 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
3161 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
3162 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
3163 LiveXMMRegs.push_back(
3164 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
3165 }
3166 }
3167
3168 if (IsWin64) {
3169 // Get to the caller-allocated home save location. Add 8 to account
3170 // for the return address.
3171 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
3172 FuncInfo->setRegSaveFrameIndex(
3173 MFI.CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
3174 // Fixup to set vararg frame on shadow area (4 x i64).
3175 if (NumIntRegs < 4)
3176 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
3177 } else {
3178 // For X86-64, if there are vararg parameters that are passed via
3179 // registers, then we must store them to their spots on the stack so
3180 // they may be loaded by dereferencing the result of va_next.
3181 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
3182 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
3183 FuncInfo->setRegSaveFrameIndex(MFI.CreateStackObject(
3184 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
3185 }
3186
3187 // Store the integer parameter registers.
3188 SmallVector<SDValue, 8> MemOps;
3189 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
3190 getPointerTy(DAG.getDataLayout()));
3191 unsigned Offset = FuncInfo->getVarArgsGPOffset();
3192 for (SDValue Val : LiveGPRs) {
3193 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
3194 RSFIN, DAG.getIntPtrConstant(Offset, dl));
3195 SDValue Store =
3196 DAG.getStore(Val.getValue(1), dl, Val, FIN,
3197 MachinePointerInfo::getFixedStack(
3198 DAG.getMachineFunction(),
3199 FuncInfo->getRegSaveFrameIndex(), Offset));
3200 MemOps.push_back(Store);
3201 Offset += 8;
3202 }
3203
3204 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
3205 // Now store the XMM (fp + vector) parameter registers.
3206 SmallVector<SDValue, 12> SaveXMMOps;
3207 SaveXMMOps.push_back(Chain);
3208 SaveXMMOps.push_back(ALVal);
3209 SaveXMMOps.push_back(DAG.getIntPtrConstant(
3210 FuncInfo->getRegSaveFrameIndex(), dl));
3211 SaveXMMOps.push_back(DAG.getIntPtrConstant(
3212 FuncInfo->getVarArgsFPOffset(), dl));
3213 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
3214 LiveXMMRegs.end());
3215 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
3216 MVT::Other, SaveXMMOps));
3217 }
3218
3219 if (!MemOps.empty())
3220 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
3221 }
3222
3223 if (isVarArg && MFI.hasMustTailInVarArgFunc()) {
3224 // Find the largest legal vector type.
3225 MVT VecVT = MVT::Other;
3226 // FIXME: Only some x86_32 calling conventions support AVX512.
3227 if (Subtarget.hasAVX512() &&
3228 (Is64Bit || (CallConv == CallingConv::X86_VectorCall ||
3229 CallConv == CallingConv::Intel_OCL_BI)))
3230 VecVT = MVT::v16f32;
3231 else if (Subtarget.hasAVX())
3232 VecVT = MVT::v8f32;
3233 else if (Subtarget.hasSSE2())
3234 VecVT = MVT::v4f32;
3235
3236 // We forward some GPRs and some vector types.
3237 SmallVector<MVT, 2> RegParmTypes;
3238 MVT IntVT = Is64Bit ? MVT::i64 : MVT::i32;
3239 RegParmTypes.push_back(IntVT);
3240 if (VecVT != MVT::Other)
3241 RegParmTypes.push_back(VecVT);
3242
3243 // Compute the set of forwarded registers. The rest are scratch.
3244 SmallVectorImpl<ForwardedRegister> &Forwards =
3245 FuncInfo->getForwardedMustTailRegParms();
3246 CCInfo.analyzeMustTailForwardedRegisters(Forwards, RegParmTypes, CC_X86);
3247
3248 // Conservatively forward AL on x86_64, since it might be used for varargs.
3249 if (Is64Bit && !CCInfo.isAllocated(X86::AL)) {
3250 unsigned ALVReg = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
3251 Forwards.push_back(ForwardedRegister(ALVReg, X86::AL, MVT::i8));
3252 }
3253
3254 // Copy all forwards from physical to virtual registers.
3255 for (ForwardedRegister &F : Forwards) {
3256 // FIXME: Can we use a less constrained schedule?
3257 SDValue RegVal = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
3258 F.VReg = MF.getRegInfo().createVirtualRegister(getRegClassFor(F.VT));
3259 Chain = DAG.getCopyToReg(Chain, dl, F.VReg, RegVal);
3260 }
3261 }
3262
3263 // Some CCs need callee pop.
3264 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3265 MF.getTarget().Options.GuaranteedTailCallOpt)) {
3266 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
3267 } else if (CallConv == CallingConv::X86_INTR && Ins.size() == 2) {
3268 // X86 interrupts must pop the error code (and the alignment padding) if
3269 // present.
3270 FuncInfo->setBytesToPopOnReturn(Is64Bit ? 16 : 4);
3271 } else {
3272 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
3273 // If this is an sret function, the return should pop the hidden pointer.
3274 if (!Is64Bit && !canGuaranteeTCO(CallConv) &&
3275 !Subtarget.getTargetTriple().isOSMSVCRT() &&
3276 argsAreStructReturn(Ins, Subtarget.isTargetMCU()) == StackStructReturn)
3277 FuncInfo->setBytesToPopOnReturn(4);
3278 }
3279
3280 if (!Is64Bit) {
3281 // RegSaveFrameIndex is X86-64 only.
3282 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
3283 if (CallConv == CallingConv::X86_FastCall ||
3284 CallConv == CallingConv::X86_ThisCall)
3285 // fastcc functions can't have varargs.
3286 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
3287 }
3288
3289 FuncInfo->setArgumentStackSize(StackSize);
3290
3291 if (WinEHFuncInfo *EHInfo = MF.getWinEHFuncInfo()) {
3292 EHPersonality Personality = classifyEHPersonality(F.getPersonalityFn());
3293 if (Personality == EHPersonality::CoreCLR) {
3294 assert(Is64Bit)(static_cast <bool> (Is64Bit) ? void (0) : __assert_fail
("Is64Bit", "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 3294, __extension__ __PRETTY_FUNCTION__))
;
3295 // TODO: Add a mechanism to frame lowering that will allow us to indicate
3296 // that we'd prefer this slot be allocated towards the bottom of the frame
3297 // (i.e. near the stack pointer after allocating the frame). Every
3298 // funclet needs a copy of this slot in its (mostly empty) frame, and the
3299 // offset from the bottom of this and each funclet's frame must be the
3300 // same, so the size of funclets' (mostly empty) frames is dictated by
3301 // how far this slot is from the bottom (since they allocate just enough
3302 // space to accommodate holding this slot at the correct offset).
3303 int PSPSymFI = MFI.CreateStackObject(8, 8, /*isSS=*/false);
3304 EHInfo->PSPSymFrameIdx = PSPSymFI;
3305 }
3306 }
3307
3308 if (CallConv == CallingConv::X86_RegCall ||
3309 F.hasFnAttribute("no_caller_saved_registers")) {
3310 MachineRegisterInfo &MRI = MF.getRegInfo();
3311 for (std::pair<unsigned, unsigned> Pair : MRI.liveins())
3312 MRI.disableCalleeSavedRegister(Pair.first);
3313 }
3314
3315 return Chain;
3316}
3317
3318SDValue X86TargetLowering::LowerMemOpCallTo(SDValue Chain, SDValue StackPtr,
3319 SDValue Arg, const SDLoc &dl,
3320 SelectionDAG &DAG,
3321 const CCValAssign &VA,
3322 ISD::ArgFlagsTy Flags) const {
3323 unsigned LocMemOffset = VA.getLocMemOffset();
3324 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
3325 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
3326 StackPtr, PtrOff);
3327 if (Flags.isByVal())
3328 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
3329
3330 return DAG.getStore(
3331 Chain, dl, Arg, PtrOff,
3332 MachinePointerInfo::getStack(DAG.getMachineFunction(), LocMemOffset));
3333}
3334
3335/// Emit a load of return address if tail call
3336/// optimization is performed and it is required.
3337SDValue X86TargetLowering::EmitTailCallLoadRetAddr(
3338 SelectionDAG &DAG, SDValue &OutRetAddr, SDValue Chain, bool IsTailCall,
3339 bool Is64Bit, int FPDiff, const SDLoc &dl) const {
3340 // Adjust the Return address stack slot.
3341 EVT VT = getPointerTy(DAG.getDataLayout());
3342 OutRetAddr = getReturnAddressFrameIndex(DAG);
3343
3344 // Load the "old" Return address.
3345 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo());
3346 return SDValue(OutRetAddr.getNode(), 1);
3347}
3348
3349/// Emit a store of the return address if tail call
3350/// optimization is performed and it is required (FPDiff!=0).
3351static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
3352 SDValue Chain, SDValue RetAddrFrIdx,
3353 EVT PtrVT, unsigned SlotSize,
3354 int FPDiff, const SDLoc &dl) {
3355 // Store the return address to the appropriate stack slot.
3356 if (!FPDiff) return Chain;
3357 // Calculate the new stack slot for the return address.
3358 int NewReturnAddrFI =
3359 MF.getFrameInfo().CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
3360 false);
3361 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
3362 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
3363 MachinePointerInfo::getFixedStack(
3364 DAG.getMachineFunction(), NewReturnAddrFI));
3365 return Chain;
3366}
3367
3368/// Returns a vector_shuffle mask for an movs{s|d}, movd
3369/// operation of specified width.
3370static SDValue getMOVL(SelectionDAG &DAG, const SDLoc &dl, MVT VT, SDValue V1,
3371 SDValue V2) {
3372 unsigned NumElems = VT.getVectorNumElements();
3373 SmallVector<int, 8> Mask;
3374 Mask.push_back(NumElems);
3375 for (unsigned i = 1; i != NumElems; ++i)
3376 Mask.push_back(i);
3377 return DAG.getVectorShuffle(VT, dl, V1, V2, Mask);
3378}
3379
3380SDValue
3381X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
3382 SmallVectorImpl<SDValue> &InVals) const {
3383 SelectionDAG &DAG = CLI.DAG;
3384 SDLoc &dl = CLI.DL;
3385 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
3386 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
3387 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
3388 SDValue Chain = CLI.Chain;
3389 SDValue Callee = CLI.Callee;
3390 CallingConv::ID CallConv = CLI.CallConv;
3391 bool &isTailCall = CLI.IsTailCall;
3392 bool isVarArg = CLI.IsVarArg;
3393
3394 MachineFunction &MF = DAG.getMachineFunction();
3395 bool Is64Bit = Subtarget.is64Bit();
3396 bool IsWin64 = Subtarget.isCallingConvWin64(CallConv);
3397 StructReturnType SR = callIsStructReturn(Outs, Subtarget.isTargetMCU());
3398 bool IsSibcall = false;
3399 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
3400 auto Attr = MF.getFunction().getFnAttribute("disable-tail-calls");
3401 const auto *CI = dyn_cast_or_null<CallInst>(CLI.CS.getInstruction());
3402 const Function *Fn = CI ? CI->getCalledFunction() : nullptr;
3403 bool HasNCSR = (CI && CI->hasFnAttr("no_caller_saved_registers")) ||
3404 (Fn && Fn->hasFnAttribute("no_caller_saved_registers"));
3405
3406 if (CallConv == CallingConv::X86_INTR)
3407 report_fatal_error("X86 interrupts may not be called directly");
3408
3409 if (Attr.getValueAsString() == "true")
3410 isTailCall = false;
3411
3412 if (Subtarget.isPICStyleGOT() &&
3413 !MF.getTarget().Options.GuaranteedTailCallOpt) {
3414 // If we are using a GOT, disable tail calls to external symbols with
3415 // default visibility. Tail calling such a symbol requires using a GOT
3416 // relocation, which forces early binding of the symbol. This breaks code
3417 // that require lazy function symbol resolution. Using musttail or
3418 // GuaranteedTailCallOpt will override this.
3419 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
3420 if (!G || (!G->getGlobal()->hasLocalLinkage() &&
3421 G->getGlobal()->hasDefaultVisibility()))
3422 isTailCall = false;
3423 }
3424
3425 bool IsMustTail = CLI.CS && CLI.CS.isMustTailCall();
3426 if (IsMustTail) {
3427 // Force this to be a tail call. The verifier rules are enough to ensure
3428 // that we can lower this successfully without moving the return address
3429 // around.
3430 isTailCall = true;
3431 } else if (isTailCall) {
3432 // Check if it's really possible to do a tail call.
3433 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
3434 isVarArg, SR != NotStructReturn,
3435 MF.getFunction().hasStructRetAttr(), CLI.RetTy,
3436 Outs, OutVals, Ins, DAG);
3437
3438 // Sibcalls are automatically detected tailcalls which do not require
3439 // ABI changes.
3440 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
3441 IsSibcall = true;
3442
3443 if (isTailCall)
3444 ++NumTailCalls;
3445 }
3446
3447 assert(!(isVarArg && canGuaranteeTCO(CallConv)) &&(static_cast <bool> (!(isVarArg && canGuaranteeTCO
(CallConv)) && "Var args not supported with calling convention fastcc, ghc or hipe"
) ? void (0) : __assert_fail ("!(isVarArg && canGuaranteeTCO(CallConv)) && \"Var args not supported with calling convention fastcc, ghc or hipe\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 3448, __extension__ __PRETTY_FUNCTION__))
3448 "Var args not supported with calling convention fastcc, ghc or hipe")(static_cast <bool> (!(isVarArg && canGuaranteeTCO
(CallConv)) && "Var args not supported with calling convention fastcc, ghc or hipe"
) ? void (0) : __assert_fail ("!(isVarArg && canGuaranteeTCO(CallConv)) && \"Var args not supported with calling convention fastcc, ghc or hipe\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 3448, __extension__ __PRETTY_FUNCTION__))
;
3449
3450 // Analyze operands of the call, assigning locations to each operand.
3451 SmallVector<CCValAssign, 16> ArgLocs;
3452 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
3453
3454 // Allocate shadow area for Win64.
3455 if (IsWin64)
3456 CCInfo.AllocateStack(32, 8);
3457
3458 CCInfo.AnalyzeArguments(Outs, CC_X86);
3459
3460 // In vectorcall calling convention a second pass is required for the HVA
3461 // types.
3462 if (CallingConv::X86_VectorCall == CallConv) {
3463 CCInfo.AnalyzeArgumentsSecondPass(Outs, CC_X86);
3464 }
3465
3466 // Get a count of how many bytes are to be pushed on the stack.
3467 unsigned NumBytes = CCInfo.getAlignedCallFrameSize();
3468 if (IsSibcall)
3469 // This is a sibcall. The memory operands are available in caller's
3470 // own caller's stack.
3471 NumBytes = 0;
3472 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
3473 canGuaranteeTCO(CallConv))
3474 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
3475
3476 int FPDiff = 0;
3477 if (isTailCall && !IsSibcall && !IsMustTail) {
3478 // Lower arguments at fp - stackoffset + fpdiff.
3479 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
3480
3481 FPDiff = NumBytesCallerPushed - NumBytes;
3482
3483 // Set the delta of movement of the returnaddr stackslot.
3484 // But only set if delta is greater than previous delta.
3485 if (FPDiff < X86Info->getTCReturnAddrDelta())
3486 X86Info->setTCReturnAddrDelta(FPDiff);
3487 }
3488
3489 unsigned NumBytesToPush = NumBytes;
3490 unsigned NumBytesToPop = NumBytes;
3491
3492 // If we have an inalloca argument, all stack space has already been allocated
3493 // for us and be right at the top of the stack. We don't support multiple
3494 // arguments passed in memory when using inalloca.
3495 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
3496 NumBytesToPush = 0;
3497 if (!ArgLocs.back().isMemLoc())
3498 report_fatal_error("cannot use inalloca attribute on a register "
3499 "parameter");
3500 if (ArgLocs.back().getLocMemOffset() != 0)
3501 report_fatal_error("any parameter with the inalloca attribute must be "
3502 "the only memory argument");
3503 }
3504
3505 if (!IsSibcall)
3506 Chain = DAG.getCALLSEQ_START(Chain, NumBytesToPush,
3507 NumBytes - NumBytesToPush, dl);
3508
3509 SDValue RetAddrFrIdx;
3510 // Load return address for tail calls.
3511 if (isTailCall && FPDiff)
3512 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
3513 Is64Bit, FPDiff, dl);
3514
3515 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
3516 SmallVector<SDValue, 8> MemOpChains;
3517 SDValue StackPtr;
3518
3519 // The next loop assumes that the locations are in the same order of the
3520 // input arguments.
3521 assert(isSortedByValueNo(ArgLocs) &&(static_cast <bool> (isSortedByValueNo(ArgLocs) &&
"Argument Location list must be sorted before lowering") ? void
(0) : __assert_fail ("isSortedByValueNo(ArgLocs) && \"Argument Location list must be sorted before lowering\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 3522, __extension__ __PRETTY_FUNCTION__))
3522 "Argument Location list must be sorted before lowering")(static_cast <bool> (isSortedByValueNo(ArgLocs) &&
"Argument Location list must be sorted before lowering") ? void
(0) : __assert_fail ("isSortedByValueNo(ArgLocs) && \"Argument Location list must be sorted before lowering\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 3522, __extension__ __PRETTY_FUNCTION__))
;
3523
3524 // Walk the register/memloc assignments, inserting copies/loads. In the case
3525 // of tail call optimization arguments are handle later.
3526 const X86RegisterInfo *RegInfo = Subtarget.getRegisterInfo();
3527 for (unsigned I = 0, OutIndex = 0, E = ArgLocs.size(); I != E;
3528 ++I, ++OutIndex) {
3529 assert(OutIndex < Outs.size() && "Invalid Out index")(static_cast <bool> (OutIndex < Outs.size() &&
"Invalid Out index") ? void (0) : __assert_fail ("OutIndex < Outs.size() && \"Invalid Out index\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 3529, __extension__ __PRETTY_FUNCTION__))
;
3530 // Skip inalloca arguments, they have already been written.
3531 ISD::ArgFlagsTy Flags = Outs[OutIndex].Flags;
3532 if (Flags.isInAlloca())
3533 continue;
3534
3535 CCValAssign &VA = ArgLocs[I];
3536 EVT RegVT = VA.getLocVT();
3537 SDValue Arg = OutVals[OutIndex];
3538 bool isByVal = Flags.isByVal();
3539
3540 // Promote the value if needed.
3541 switch (VA.getLocInfo()) {
3542 default: llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 3542)
;
3543 case CCValAssign::Full: break;
3544 case CCValAssign::SExt:
3545 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
3546 break;
3547 case CCValAssign::ZExt:
3548 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
3549 break;
3550 case CCValAssign::AExt:
3551 if (Arg.getValueType().isVector() &&
3552 Arg.getValueType().getVectorElementType() == MVT::i1)
3553 Arg = lowerMasksToReg(Arg, RegVT, dl, DAG);
3554 else if (RegVT.is128BitVector()) {
3555 // Special case: passing MMX values in XMM registers.
3556 Arg = DAG.getBitcast(MVT::i64, Arg);
3557 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
3558 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
3559 } else
3560 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
3561 break;
3562 case CCValAssign::BCvt:
3563 Arg = DAG.getBitcast(RegVT, Arg);
3564 break;
3565 case CCValAssign::Indirect: {
3566 // Store the argument.
3567 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
3568 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
3569 Chain = DAG.getStore(
3570 Chain, dl, Arg, SpillSlot,
3571 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI));
3572 Arg = SpillSlot;
3573 break;
3574 }
3575 }
3576
3577 if (VA.needsCustom()) {
3578 assert(VA.getValVT() == MVT::v64i1 &&(static_cast <bool> (VA.getValVT() == MVT::v64i1 &&
"Currently the only custom case is when we split v64i1 to 2 regs"
) ? void (0) : __assert_fail ("VA.getValVT() == MVT::v64i1 && \"Currently the only custom case is when we split v64i1 to 2 regs\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 3579, __extension__ __PRETTY_FUNCTION__))
3579 "Currently the only custom case is when we split v64i1 to 2 regs")(static_cast <bool> (VA.getValVT() == MVT::v64i1 &&
"Currently the only custom case is when we split v64i1 to 2 regs"
) ? void (0) : __assert_fail ("VA.getValVT() == MVT::v64i1 && \"Currently the only custom case is when we split v64i1 to 2 regs\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 3579, __extension__ __PRETTY_FUNCTION__))
;
3580 // Split v64i1 value into two registers
3581 Passv64i1ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++I],
3582 Subtarget);
3583 } else if (VA.isRegLoc()) {
3584 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
3585 if (isVarArg && IsWin64) {
3586 // Win64 ABI requires argument XMM reg to be copied to the corresponding
3587 // shadow reg if callee is a varargs function.
3588 unsigned ShadowReg = 0;
3589 switch (VA.getLocReg()) {
3590 case X86::XMM0: ShadowReg = X86::RCX; break;
3591 case X86::XMM1: ShadowReg = X86::RDX; break;
3592 case X86::XMM2: ShadowReg = X86::R8; break;
3593 case X86::XMM3: ShadowReg = X86::R9; break;
3594 }
3595 if (ShadowReg)
3596 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
3597 }
3598 } else if (!IsSibcall && (!isTailCall || isByVal)) {
3599 assert(VA.isMemLoc())(static_cast <bool> (VA.isMemLoc()) ? void (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 3599, __extension__ __PRETTY_FUNCTION__))
;
3600 if (!StackPtr.getNode())
3601 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
3602 getPointerTy(DAG.getDataLayout()));
3603 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
3604 dl, DAG, VA, Flags));
3605 }
3606 }
3607
3608 if (!MemOpChains.empty())
3609 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
3610
3611 if (Subtarget.isPICStyleGOT()) {
3612 // ELF / PIC requires GOT in the EBX register before function calls via PLT
3613 // GOT pointer.
3614 if (!isTailCall) {
3615 RegsToPass.push_back(std::make_pair(
3616 unsigned(X86::EBX), DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(),
3617 getPointerTy(DAG.getDataLayout()))));
3618 } else {
3619 // If we are tail calling and generating PIC/GOT style code load the
3620 // address of the callee into ECX. The value in ecx is used as target of
3621 // the tail jump. This is done to circumvent the ebx/callee-saved problem
3622 // for tail calls on PIC/GOT architectures. Normally we would just put the
3623 // address of GOT into ebx and then call target@PLT. But for tail calls
3624 // ebx would be restored (since ebx is callee saved) before jumping to the
3625 // target@PLT.
3626
3627 // Note: The actual moving to ECX is done further down.
3628 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
3629 if (G && !G->getGlobal()->hasLocalLinkage() &&
3630 G->getGlobal()->hasDefaultVisibility())
3631 Callee = LowerGlobalAddress(Callee, DAG);
3632 else if (isa<ExternalSymbolSDNode>(Callee))
3633 Callee = LowerExternalSymbol(Callee, DAG);
3634 }
3635 }
3636
3637 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
3638 // From AMD64 ABI document:
3639 // For calls that may call functions that use varargs or stdargs
3640 // (prototype-less calls or calls to functions containing ellipsis (...) in
3641 // the declaration) %al is used as hidden argument to specify the number
3642 // of SSE registers used. The contents of %al do not need to match exactly
3643 // the number of registers, but must be an ubound on the number of SSE
3644 // registers used and is in the range 0 - 8 inclusive.
3645
3646 // Count the number of XMM registers allocated.
3647 static const MCPhysReg XMMArgRegs[] = {
3648 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
3649 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
3650 };
3651 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs);
3652 assert((Subtarget.hasSSE1() || !NumXMMRegs)(static_cast <bool> ((Subtarget.hasSSE1() || !NumXMMRegs
) && "SSE registers cannot be used when SSE is disabled"
) ? void (0) : __assert_fail ("(Subtarget.hasSSE1() || !NumXMMRegs) && \"SSE registers cannot be used when SSE is disabled\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 3653, __extension__ __PRETTY_FUNCTION__))
3653 && "SSE registers cannot be used when SSE is disabled")(static_cast <bool> ((Subtarget.hasSSE1() || !NumXMMRegs
) && "SSE registers cannot be used when SSE is disabled"
) ? void (0) : __assert_fail ("(Subtarget.hasSSE1() || !NumXMMRegs) && \"SSE registers cannot be used when SSE is disabled\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 3653, __extension__ __PRETTY_FUNCTION__))
;
3654
3655 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
3656 DAG.getConstant(NumXMMRegs, dl,
3657 MVT::i8)));
3658 }
3659
3660 if (isVarArg && IsMustTail) {
3661 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
3662 for (const auto &F : Forwards) {
3663 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
3664 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
3665 }
3666 }
3667
3668 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
3669 // don't need this because the eligibility check rejects calls that require
3670 // shuffling arguments passed in memory.
3671 if (!IsSibcall && isTailCall) {
3672 // Force all the incoming stack arguments to be loaded from the stack
3673 // before any new outgoing arguments are stored to the stack, because the
3674 // outgoing stack slots may alias the incoming argument stack slots, and
3675 // the alias isn't otherwise explicit. This is slightly more conservative
3676 // than necessary, because it means that each store effectively depends
3677 // on every argument instead of just those arguments it would clobber.
3678 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
3679
3680 SmallVector<SDValue, 8> MemOpChains2;
3681 SDValue FIN;
3682 int FI = 0;
3683 for (unsigned I = 0, OutsIndex = 0, E = ArgLocs.size(); I != E;
3684 ++I, ++OutsIndex) {
3685 CCValAssign &VA = ArgLocs[I];
3686
3687 if (VA.isRegLoc()) {
3688 if (VA.needsCustom()) {
3689 assert((CallConv == CallingConv::X86_RegCall) &&(static_cast <bool> ((CallConv == CallingConv::X86_RegCall
) && "Expecting custom case only in regcall calling convention"
) ? void (0) : __assert_fail ("(CallConv == CallingConv::X86_RegCall) && \"Expecting custom case only in regcall calling convention\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 3690, __extension__ __PRETTY_FUNCTION__))
3690 "Expecting custom case only in regcall calling convention")(static_cast <bool> ((CallConv == CallingConv::X86_RegCall
) && "Expecting custom case only in regcall calling convention"
) ? void (0) : __assert_fail ("(CallConv == CallingConv::X86_RegCall) && \"Expecting custom case only in regcall calling convention\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 3690, __extension__ __PRETTY_FUNCTION__))
;
3691 // This means that we are in special case where one argument was
3692 // passed through two register locations - Skip the next location
3693 ++I;
3694 }
3695
3696 continue;
3697 }
3698
3699 assert(VA.isMemLoc())(static_cast <bool> (VA.isMemLoc()) ? void (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 3699, __extension__ __PRETTY_FUNCTION__))
;
3700 SDValue Arg = OutVals[OutsIndex];
3701 ISD::ArgFlagsTy Flags = Outs[OutsIndex].Flags;
3702 // Skip inalloca arguments. They don't require any work.
3703 if (Flags.isInAlloca())
3704 continue;
3705 // Create frame index.
3706 int32_t Offset = VA.getLocMemOffset()+FPDiff;
3707 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
3708 FI = MF.getFrameInfo().CreateFixedObject(OpSize, Offset, true);
3709 FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
3710
3711 if (Flags.isByVal()) {
3712 // Copy relative to framepointer.
3713 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset(), dl);
3714 if (!StackPtr.getNode())
3715 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
3716 getPointerTy(DAG.getDataLayout()));
3717 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
3718 StackPtr, Source);
3719
3720 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3721 ArgChain,
3722 Flags, DAG, dl));
3723 } else {
3724 // Store relative to framepointer.
3725 MemOpChains2.push_back(DAG.getStore(
3726 ArgChain, dl, Arg, FIN,
3727 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI)));
3728 }
3729 }
3730
3731 if (!MemOpChains2.empty())
3732 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3733
3734 // Store the return address to the appropriate stack slot.
3735 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3736 getPointerTy(DAG.getDataLayout()),
3737 RegInfo->getSlotSize(), FPDiff, dl);
3738 }
3739
3740 // Build a sequence of copy-to-reg nodes chained together with token chain
3741 // and flag operands which copy the outgoing args into registers.
3742 SDValue InFlag;
3743 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3744 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3745 RegsToPass[i].second, InFlag);
3746 InFlag = Chain.getValue(1);
3747 }
3748
3749 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3750 assert(Is64Bit && "Large code model is only legal in 64-bit mode.")(static_cast <bool> (Is64Bit && "Large code model is only legal in 64-bit mode."
) ? void (0) : __assert_fail ("Is64Bit && \"Large code model is only legal in 64-bit mode.\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 3750, __extension__ __PRETTY_FUNCTION__))
;
3751 // In the 64-bit large code model, we have to make all calls
3752 // through a register, since the call instruction's 32-bit
3753 // pc-relative offset may not be large enough to hold the whole
3754 // address.
3755 } else if (Callee->getOpcode() == ISD::GlobalAddress) {
3756 // If the callee is a GlobalAddress node (quite common, every direct call
3757 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3758 // it.
3759 GlobalAddressSDNode* G = cast<GlobalAddressSDNode>(Callee);
3760
3761 // We should use extra load for direct calls to dllimported functions in
3762 // non-JIT mode.
3763 const GlobalValue *GV = G->getGlobal();
3764 if (!GV->hasDLLImportStorageClass()) {
3765 unsigned char OpFlags = Subtarget.classifyGlobalFunctionReference(GV);
3766
3767 Callee = DAG.getTargetGlobalAddress(
3768 GV, dl, getPointerTy(DAG.getDataLayout()), G->getOffset(), OpFlags);
3769
3770 if (OpFlags == X86II::MO_GOTPCREL) {
3771 // Add a wrapper.
3772 Callee = DAG.getNode(X86ISD::WrapperRIP, dl,
3773 getPointerTy(DAG.getDataLayout()), Callee);
3774 // Add extra indirection
3775 Callee = DAG.getLoad(
3776 getPointerTy(DAG.getDataLayout()), dl, DAG.getEntryNode(), Callee,
3777 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
3778 }
3779 }
3780 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3781 const Module *Mod = DAG.getMachineFunction().getFunction().getParent();
3782 unsigned char OpFlags =
3783 Subtarget.classifyGlobalFunctionReference(nullptr, *Mod);
3784
3785 Callee = DAG.getTargetExternalSymbol(
3786 S->getSymbol(), getPointerTy(DAG.getDataLayout()), OpFlags);
3787
3788 if (OpFlags == X86II::MO_GOTPCREL) {
3789 Callee = DAG.getNode(X86ISD::WrapperRIP, dl,
3790 getPointerTy(DAG.getDataLayout()), Callee);
3791 Callee = DAG.getLoad(
3792 getPointerTy(DAG.getDataLayout()), dl, DAG.getEntryNode(), Callee,
3793 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
3794 }
3795 } else if (Subtarget.isTarget64BitILP32() &&
3796 Callee->getValueType(0) == MVT::i32) {
3797 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3798 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3799 }
3800
3801 // Returns a chain & a flag for retval copy to use.
3802 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3803 SmallVector<SDValue, 8> Ops;
3804
3805 if (!IsSibcall && isTailCall) {
3806 Chain = DAG.getCALLSEQ_END(Chain,
3807 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
3808 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
3809 InFlag = Chain.getValue(1);
3810 }
3811
3812 Ops.push_back(Chain);
3813 Ops.push_back(Callee);
3814
3815 if (isTailCall)
3816 Ops.push_back(DAG.getConstant(FPDiff, dl, MVT::i32));
3817
3818 // Add argument registers to the end of the list so that they are known live
3819 // into the call.
3820 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3821 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3822 RegsToPass[i].second.getValueType()));
3823
3824 // Add a register mask operand representing the call-preserved registers.
3825 // If HasNCSR is asserted (attribute NoCallerSavedRegisters exists) then we
3826 // set X86_INTR calling convention because it has the same CSR mask
3827 // (same preserved registers).
3828 const uint32_t *Mask = RegInfo->getCallPreservedMask(
3829 MF, HasNCSR ? (CallingConv::ID)CallingConv::X86_INTR : CallConv);
3830 assert(Mask && "Missing call preserved mask for calling convention")(static_cast <bool> (Mask && "Missing call preserved mask for calling convention"
) ? void (0) : __assert_fail ("Mask && \"Missing call preserved mask for calling convention\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 3830, __extension__ __PRETTY_FUNCTION__))
;
3831
3832 // If this is an invoke in a 32-bit function using a funclet-based
3833 // personality, assume the function clobbers all registers. If an exception
3834 // is thrown, the runtime will not restore CSRs.
3835 // FIXME: Model this more precisely so that we can register allocate across
3836 // the normal edge and spill and fill across the exceptional edge.
3837 if (!Is64Bit && CLI.CS && CLI.CS.isInvoke()) {
3838 const Function &CallerFn = MF.getFunction();
3839 EHPersonality Pers =
3840 CallerFn.hasPersonalityFn()
3841 ? classifyEHPersonality(CallerFn.getPersonalityFn())
3842 : EHPersonality::Unknown;
3843 if (isFuncletEHPersonality(Pers))
3844 Mask = RegInfo->getNoPreservedMask();
3845 }
3846
3847 // Define a new register mask from the existing mask.
3848 uint32_t *RegMask = nullptr;
3849
3850 // In some calling conventions we need to remove the used physical registers
3851 // from the reg mask.
3852 if (CallConv == CallingConv::X86_RegCall || HasNCSR) {
3853 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
3854
3855 // Allocate a new Reg Mask and copy Mask.
3856 RegMask = MF.allocateRegisterMask(TRI->getNumRegs());
3857 unsigned RegMaskSize = (TRI->getNumRegs() + 31) / 32;
3858 memcpy(RegMask, Mask, sizeof(uint32_t) * RegMaskSize);
3859
3860 // Make sure all sub registers of the argument registers are reset
3861 // in the RegMask.
3862 for (auto const &RegPair : RegsToPass)
3863 for (MCSubRegIterator SubRegs(RegPair.first, TRI, /*IncludeSelf=*/true);
3864 SubRegs.isValid(); ++SubRegs)
3865 RegMask[*SubRegs / 32] &= ~(1u << (*SubRegs % 32));
3866
3867 // Create the RegMask Operand according to our updated mask.
3868 Ops.push_back(DAG.getRegisterMask(RegMask));
3869 } else {
3870 // Create the RegMask Operand according to the static mask.
3871 Ops.push_back(DAG.getRegisterMask(Mask));
3872 }
3873
3874 if (InFlag.getNode())
3875 Ops.push_back(InFlag);
3876
3877 if (isTailCall) {
3878 // We used to do:
3879 //// If this is the first return lowered for this function, add the regs
3880 //// to the liveout set for the function.
3881 // This isn't right, although it's probably harmless on x86; liveouts
3882 // should be computed from returns not tail calls. Consider a void
3883 // function making a tail call to a function returning int.
3884 MF.getFrameInfo().setHasTailCall();
3885 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3886 }
3887
3888 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3889 InFlag = Chain.getValue(1);
3890
3891 // Create the CALLSEQ_END node.
3892 unsigned NumBytesForCalleeToPop;
3893 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3894 DAG.getTarget().Options.GuaranteedTailCallOpt))
3895 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3896 else if (!Is64Bit && !canGuaranteeTCO(CallConv) &&
3897 !Subtarget.getTargetTriple().isOSMSVCRT() &&
3898 SR == StackStructReturn)
3899 // If this is a call to a struct-return function, the callee
3900 // pops the hidden struct pointer, so we have to push it back.
3901 // This is common for Darwin/X86, Linux & Mingw32 targets.
3902 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3903 NumBytesForCalleeToPop = 4;
3904 else
3905 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3906
3907 if (CLI.DoesNotReturn && !getTargetMachine().Options.TrapUnreachable) {
3908 // No need to reset the stack after the call if the call doesn't return. To
3909 // make the MI verify, we'll pretend the callee does it for us.
3910 NumBytesForCalleeToPop = NumBytes;
3911 }
3912
3913 // Returns a flag for retval copy to use.
3914 if (!IsSibcall) {
3915 Chain = DAG.getCALLSEQ_END(Chain,
3916 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
3917 DAG.getIntPtrConstant(NumBytesForCalleeToPop, dl,
3918 true),
3919 InFlag, dl);
3920 InFlag = Chain.getValue(1);
3921 }
3922
3923 // Handle result values, copying them out of physregs into vregs that we
3924 // return.
3925 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl, DAG,
3926 InVals, RegMask);
3927}
3928
3929//===----------------------------------------------------------------------===//
3930// Fast Calling Convention (tail call) implementation
3931//===----------------------------------------------------------------------===//
3932
3933// Like std call, callee cleans arguments, convention except that ECX is
3934// reserved for storing the tail called function address. Only 2 registers are
3935// free for argument passing (inreg). Tail call optimization is performed
3936// provided:
3937// * tailcallopt is enabled
3938// * caller/callee are fastcc
3939// On X86_64 architecture with GOT-style position independent code only local
3940// (within module) calls are supported at the moment.
3941// To keep the stack aligned according to platform abi the function
3942// GetAlignedArgumentStackSize ensures that argument delta is always multiples
3943// of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3944// If a tail called function callee has more arguments than the caller the
3945// caller needs to make sure that there is room to move the RETADDR to. This is
3946// achieved by reserving an area the size of the argument delta right after the
3947// original RETADDR, but before the saved framepointer or the spilled registers
3948// e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3949// stack layout:
3950// arg1
3951// arg2
3952// RETADDR
3953// [ new RETADDR
3954// move area ]
3955// (possible EBP)
3956// ESI
3957// EDI
3958// local1 ..
3959
3960/// Make the stack size align e.g 16n + 12 aligned for a 16-byte align
3961/// requirement.
3962unsigned
3963X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3964 SelectionDAG& DAG) const {
3965 const X86RegisterInfo *RegInfo = Subtarget.getRegisterInfo();
3966 const TargetFrameLowering &TFI = *Subtarget.getFrameLowering();
3967 unsigned StackAlignment = TFI.getStackAlignment();
3968 uint64_t AlignMask = StackAlignment - 1;
3969 int64_t Offset = StackSize;
3970 unsigned SlotSize = RegInfo->getSlotSize();
3971 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3972 // Number smaller than 12 so just add the difference.
3973 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3974 } else {
3975 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3976 Offset = ((~AlignMask) & Offset) + StackAlignment +
3977 (StackAlignment-SlotSize);
3978 }
3979 return Offset;
3980}
3981
3982/// Return true if the given stack call argument is already available in the
3983/// same position (relatively) of the caller's incoming argument stack.
3984static
3985bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3986 MachineFrameInfo &MFI, const MachineRegisterInfo *MRI,
3987 const X86InstrInfo *TII, const CCValAssign &VA) {
3988 unsigned Bytes = Arg.getValueSizeInBits() / 8;
3989
3990 for (;;) {
3991 // Look through nodes that don't alter the bits of the incoming value.
3992 unsigned Op = Arg.getOpcode();
3993 if (Op == ISD::ZERO_EXTEND || Op == ISD::ANY_EXTEND || Op == ISD::BITCAST) {
3994 Arg = Arg.getOperand(0);
3995 continue;
3996 }
3997 if (Op == ISD::TRUNCATE) {
3998 const SDValue &TruncInput = Arg.getOperand(0);
3999 if (TruncInput.getOpcode() == ISD::AssertZext &&
4000 cast<VTSDNode>(TruncInput.getOperand(1))->getVT() ==
4001 Arg.getValueType()) {
4002 Arg = TruncInput.getOperand(0);
4003 continue;
4004 }
4005 }
4006 break;
4007 }
4008
4009 int FI = INT_MAX2147483647;
4010 if (Arg.getOpcode() == ISD::CopyFromReg) {
4011 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
4012 if (!TargetRegisterInfo::isVirtualRegister(VR))
4013 return false;
4014 MachineInstr *Def = MRI->getVRegDef(VR);
4015 if (!Def)
4016 return false;
4017 if (!Flags.isByVal()) {
4018 if (!TII->isLoadFromStackSlot(*Def, FI))
4019 return false;
4020 } else {
4021 unsigned Opcode = Def->getOpcode();
4022 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r ||
4023 Opcode == X86::LEA64_32r) &&
4024 Def->getOperand(1).isFI()) {
4025 FI = Def->getOperand(1).getIndex();
4026 Bytes = Flags.getByValSize();
4027 } else
4028 return false;
4029 }
4030 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
4031 if (Flags.isByVal())
4032 // ByVal argument is passed in as a pointer but it's now being
4033 // dereferenced. e.g.
4034 // define @foo(%struct.X* %A) {
4035 // tail call @bar(%struct.X* byval %A)
4036 // }
4037 return false;
4038 SDValue Ptr = Ld->getBasePtr();
4039 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
4040 if (!FINode)
4041 return false;
4042 FI = FINode->getIndex();
4043 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
4044 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
4045 FI = FINode->getIndex();
4046 Bytes = Flags.getByValSize();
4047 } else
4048 return false;
4049
4050 assert(FI != INT_MAX)(static_cast <bool> (FI != 2147483647) ? void (0) : __assert_fail
("FI != INT_MAX", "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 4050, __extension__ __PRETTY_FUNCTION__))
;
4051 if (!MFI.isFixedObjectIndex(FI))
4052 return false;
4053
4054 if (Offset != MFI.getObjectOffset(FI))
4055 return false;
4056
4057 // If this is not byval, check that the argument stack object is immutable.
4058 // inalloca and argument copy elision can create mutable argument stack
4059 // objects. Byval objects can be mutated, but a byval call intends to pass the
4060 // mutated memory.
4061 if (!Flags.isByVal() && !MFI.isImmutableObjectIndex(FI))
4062 return false;
4063
4064 if (VA.getLocVT().getSizeInBits() > Arg.getValueSizeInBits()) {
4065 // If the argument location is wider than the argument type, check that any
4066 // extension flags match.
4067 if (Flags.isZExt() != MFI.isObjectZExt(FI) ||
4068 Flags.isSExt() != MFI.isObjectSExt(FI)) {
4069 return false;
4070 }
4071 }
4072
4073 return Bytes == MFI.getObjectSize(FI);
4074}
4075
4076/// Check whether the call is eligible for tail call optimization. Targets
4077/// that want to do tail call optimization should implement this function.
4078bool X86TargetLowering::IsEligibleForTailCallOptimization(
4079 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
4080 bool isCalleeStructRet, bool isCallerStructRet, Type *RetTy,
4081 const SmallVectorImpl<ISD::OutputArg> &Outs,
4082 const SmallVectorImpl<SDValue> &OutVals,
4083 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const {
4084 if (!mayTailCallThisCC(CalleeCC))
4085 return false;
4086
4087 // If -tailcallopt is specified, make fastcc functions tail-callable.
4088 MachineFunction &MF = DAG.getMachineFunction();
4089 const Function &CallerF = MF.getFunction();
4090
4091 // If the function return type is x86_fp80 and the callee return type is not,
4092 // then the FP_EXTEND of the call result is not a nop. It's not safe to
4093 // perform a tailcall optimization here.
4094 if (CallerF.getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
4095 return false;
4096
4097 CallingConv::ID CallerCC = CallerF.getCallingConv();
4098 bool CCMatch = CallerCC == CalleeCC;
4099 bool IsCalleeWin64 = Subtarget.isCallingConvWin64(CalleeCC);
4100 bool IsCallerWin64 = Subtarget.isCallingConvWin64(CallerCC);
4101
4102 // Win64 functions have extra shadow space for argument homing. Don't do the
4103 // sibcall if the caller and callee have mismatched expectations for this
4104 // space.
4105 if (IsCalleeWin64 != IsCallerWin64)
4106 return false;
4107
4108 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
4109 if (canGuaranteeTCO(CalleeCC) && CCMatch)
4110 return true;
4111 return false;
4112 }
4113
4114 // Look for obvious safe cases to perform tail call optimization that do not
4115 // require ABI changes. This is what gcc calls sibcall.
4116
4117 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
4118 // emit a special epilogue.
4119 const X86RegisterInfo *RegInfo = Subtarget.getRegisterInfo();
4120 if (RegInfo->needsStackRealignment(MF))
4121 return false;
4122
4123 // Also avoid sibcall optimization if either caller or callee uses struct
4124 // return semantics.
4125 if (isCalleeStructRet || isCallerStructRet)
4126 return false;
4127
4128 // Do not sibcall optimize vararg calls unless all arguments are passed via
4129 // registers.
4130 LLVMContext &C = *DAG.getContext();
4131 if (isVarArg && !Outs.empty()) {
4132 // Optimizing for varargs on Win64 is unlikely to be safe without
4133 // additional testing.
4134 if (IsCalleeWin64 || IsCallerWin64)
4135 return false;
4136
4137 SmallVector<CCValAssign, 16> ArgLocs;
4138 CCState CCInfo(CalleeCC, isVarArg, MF, ArgLocs, C);
4139
4140 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
4141 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
4142 if (!ArgLocs[i].isRegLoc())
4143 return false;
4144 }
4145
4146 // If the call result is in ST0 / ST1, it needs to be popped off the x87
4147 // stack. Therefore, if it's not used by the call it is not safe to optimize
4148 // this into a sibcall.
4149 bool Unused = false;
4150 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
4151 if (!Ins[i].Used) {
4152 Unused = true;
4153 break;
4154 }
4155 }
4156 if (Unused) {
4157 SmallVector<CCValAssign, 16> RVLocs;
4158 CCState CCInfo(CalleeCC, false, MF, RVLocs, C);
4159 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
4160 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
4161 CCValAssign &VA = RVLocs[i];
4162 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
4163 return false;
4164 }
4165 }
4166
4167 // Check that the call results are passed in the same way.
4168 if (!CCState::resultsCompatible(CalleeCC, CallerCC, MF, C, Ins,
4169 RetCC_X86, RetCC_X86))
4170 return false;
4171 // The callee has to preserve all registers the caller needs to preserve.
4172 const X86RegisterInfo *TRI = Subtarget.getRegisterInfo();
4173 const uint32_t *CallerPreserved = TRI->getCallPreservedMask(MF, CallerCC);
4174 if (!CCMatch) {
4175 const uint32_t *CalleePreserved = TRI->getCallPreservedMask(MF, CalleeCC);
4176 if (!TRI->regmaskSubsetEqual(CallerPreserved, CalleePreserved))
4177 return false;
4178 }
4179
4180 unsigned StackArgsSize = 0;
4181
4182 // If the callee takes no arguments then go on to check the results of the
4183 // call.
4184 if (!Outs.empty()) {
4185 // Check if stack adjustment is needed. For now, do not do this if any
4186 // argument is passed on the stack.
4187 SmallVector<CCValAssign, 16> ArgLocs;
4188 CCState CCInfo(CalleeCC, isVarArg, MF, ArgLocs, C);
4189
4190 // Allocate shadow area for Win64
4191 if (IsCalleeWin64)
4192 CCInfo.AllocateStack(32, 8);
4193
4194 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
4195 StackArgsSize = CCInfo.getNextStackOffset();
4196
4197 if (CCInfo.getNextStackOffset()) {
4198 // Check if the arguments are already laid out in the right way as
4199 // the caller's fixed stack objects.
4200 MachineFrameInfo &MFI = MF.getFrameInfo();
4201 const MachineRegisterInfo *MRI = &MF.getRegInfo();
4202 const X86InstrInfo *TII = Subtarget.getInstrInfo();
4203 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
4204 CCValAssign &VA = ArgLocs[i];
4205 SDValue Arg = OutVals[i];
4206 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4207 if (VA.getLocInfo() == CCValAssign::Indirect)
4208 return false;
4209 if (!VA.isRegLoc()) {
4210 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
4211 MFI, MRI, TII, VA))
4212 return false;
4213 }
4214 }
4215 }
4216
4217 bool PositionIndependent = isPositionIndependent();
4218 // If the tailcall address may be in a register, then make sure it's
4219 // possible to register allocate for it. In 32-bit, the call address can
4220 // only target EAX, EDX, or ECX since the tail call must be scheduled after
4221 // callee-saved registers are restored. These happen to be the same
4222 // registers used to pass 'inreg' arguments so watch out for those.
4223 if (!Subtarget.is64Bit() && ((!isa<GlobalAddressSDNode>(Callee) &&
4224 !isa<ExternalSymbolSDNode>(Callee)) ||
4225 PositionIndependent)) {
4226 unsigned NumInRegs = 0;
4227 // In PIC we need an extra register to formulate the address computation
4228 // for the callee.
4229 unsigned MaxInRegs = PositionIndependent ? 2 : 3;
4230
4231 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
4232 CCValAssign &VA = ArgLocs[i];
4233 if (!VA.isRegLoc())
4234 continue;
4235 unsigned Reg = VA.getLocReg();
4236 switch (Reg) {
4237 default: break;
4238 case X86::EAX: case X86::EDX: case X86::ECX:
4239 if (++NumInRegs == MaxInRegs)
4240 return false;
4241 break;
4242 }
4243 }
4244 }
4245
4246 const MachineRegisterInfo &MRI = MF.getRegInfo();
4247 if (!parametersInCSRMatch(MRI, CallerPreserved, ArgLocs, OutVals))
4248 return false;
4249 }
4250
4251 bool CalleeWillPop =
4252 X86::isCalleePop(CalleeCC, Subtarget.is64Bit(), isVarArg,
4253 MF.getTarget().Options.GuaranteedTailCallOpt);
4254
4255 if (unsigned BytesToPop =
4256 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn()) {
4257 // If we have bytes to pop, the callee must pop them.
4258 bool CalleePopMatches = CalleeWillPop && BytesToPop == StackArgsSize;
4259 if (!CalleePopMatches)
4260 return false;
4261 } else if (CalleeWillPop && StackArgsSize > 0) {
4262 // If we don't have bytes to pop, make sure the callee doesn't pop any.
4263 return false;
4264 }
4265
4266 return true;
4267}
4268
4269FastISel *
4270X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
4271 const TargetLibraryInfo *libInfo) const {
4272 return X86::createFastISel(funcInfo, libInfo);
4273}
4274
4275//===----------------------------------------------------------------------===//
4276// Other Lowering Hooks
4277//===----------------------------------------------------------------------===//
4278
4279static bool MayFoldLoad(SDValue Op) {
4280 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
4281}
4282
4283static bool MayFoldIntoStore(SDValue Op) {
4284 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
4285}
4286
4287static bool MayFoldIntoZeroExtend(SDValue Op) {
4288 if (Op.hasOneUse()) {
4289 unsigned Opcode = Op.getNode()->use_begin()->getOpcode();
4290 return (ISD::ZERO_EXTEND == Opcode);
4291 }
4292 return false;
4293}
4294
4295static bool isTargetShuffle(unsigned Opcode) {
4296 switch(Opcode) {
4297 default: return false;
4298 case X86ISD::BLENDI:
4299 case X86ISD::PSHUFB:
4300 case X86ISD::PSHUFD:
4301 case X86ISD::PSHUFHW:
4302 case X86ISD::PSHUFLW:
4303 case X86ISD::SHUFP:
4304 case X86ISD::INSERTPS:
4305 case X86ISD::EXTRQI:
4306 case X86ISD::INSERTQI:
4307 case X86ISD::PALIGNR:
4308 case X86ISD::VSHLDQ:
4309 case X86ISD::VSRLDQ:
4310 case X86ISD::MOVLHPS:
4311 case X86ISD::MOVHLPS:
4312 case X86ISD::MOVLPS:
4313 case X86ISD::MOVLPD:
4314 case X86ISD::MOVSHDUP:
4315 case X86ISD::MOVSLDUP:
4316 case X86ISD::MOVDDUP:
4317 case X86ISD::MOVSS:
4318 case X86ISD::MOVSD:
4319 case X86ISD::UNPCKL:
4320 case X86ISD::UNPCKH:
4321 case X86ISD::VBROADCAST:
4322 case X86ISD::VPERMILPI:
4323 case X86ISD::VPERMILPV:
4324 case X86ISD::VPERM2X128:
4325 case X86ISD::VPERMIL2:
4326 case X86ISD::VPERMI:
4327 case X86ISD::VPPERM:
4328 case X86ISD::VPERMV:
4329 case X86ISD::VPERMV3:
4330 case X86ISD::VPERMIV3:
4331 case X86ISD::VZEXT_MOVL:
4332 return true;
4333 }
4334}
4335
4336static bool isTargetShuffleVariableMask(unsigned Opcode) {
4337 switch (Opcode) {
4338 default: return false;
4339 // Target Shuffles.
4340 case X86ISD::PSHUFB:
4341 case X86ISD::VPERMILPV:
4342 case X86ISD::VPERMIL2:
4343 case X86ISD::VPPERM:
4344 case X86ISD::VPERMV:
4345 case X86ISD::VPERMV3:
4346 case X86ISD::VPERMIV3:
4347 return true;
4348 // 'Faux' Target Shuffles.
4349 case ISD::AND:
4350 case X86ISD::ANDNP:
4351 return true;
4352 }
4353}
4354
4355SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
4356 MachineFunction &MF = DAG.getMachineFunction();
4357 const X86RegisterInfo *RegInfo = Subtarget.getRegisterInfo();
4358 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
4359 int ReturnAddrIndex = FuncInfo->getRAIndex();
4360
4361 if (ReturnAddrIndex == 0) {
4362 // Set up a frame object for the return address.
4363 unsigned SlotSize = RegInfo->getSlotSize();
4364 ReturnAddrIndex = MF.getFrameInfo().CreateFixedObject(SlotSize,
4365 -(int64_t)SlotSize,
4366 false);
4367 FuncInfo->setRAIndex(ReturnAddrIndex);
4368 }
4369
4370 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy(DAG.getDataLayout()));
4371}
4372
4373bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
4374 bool hasSymbolicDisplacement) {
4375 // Offset should fit into 32 bit immediate field.
4376 if (!isInt<32>(Offset))
4377 return false;
4378
4379 // If we don't have a symbolic displacement - we don't have any extra
4380 // restrictions.
4381 if (!hasSymbolicDisplacement)
4382 return true;
4383
4384 // FIXME: Some tweaks might be needed for medium code model.
4385 if (M != CodeModel::Small && M != CodeModel::Kernel)
4386 return false;
4387
4388 // For small code model we assume that latest object is 16MB before end of 31
4389 // bits boundary. We may also accept pretty large negative constants knowing
4390 // that all objects are in the positive half of address space.
4391 if (M == CodeModel::Small && Offset < 16*1024*1024)
4392 return true;
4393
4394 // For kernel code model we know that all object resist in the negative half
4395 // of 32bits address space. We may not accept negative offsets, since they may
4396 // be just off and we may accept pretty large positive ones.
4397 if (M == CodeModel::Kernel && Offset >= 0)
4398 return true;
4399
4400 return false;
4401}
4402
4403/// Determines whether the callee is required to pop its own arguments.
4404/// Callee pop is necessary to support tail calls.
4405bool X86::isCalleePop(CallingConv::ID CallingConv,
4406 bool is64Bit, bool IsVarArg, bool GuaranteeTCO) {
4407 // If GuaranteeTCO is true, we force some calls to be callee pop so that we
4408 // can guarantee TCO.
4409 if (!IsVarArg && shouldGuaranteeTCO(CallingConv, GuaranteeTCO))
4410 return true;
4411
4412 switch (CallingConv) {
4413 default:
4414 return false;
4415 case CallingConv::X86_StdCall:
4416 case CallingConv::X86_FastCall:
4417 case CallingConv::X86_ThisCall:
4418 case CallingConv::X86_VectorCall:
4419 return !is64Bit;
4420 }
4421}
4422
4423/// \brief Return true if the condition is an unsigned comparison operation.
4424static bool isX86CCUnsigned(unsigned X86CC) {
4425 switch (X86CC) {
4426 default:
4427 llvm_unreachable("Invalid integer condition!")::llvm::llvm_unreachable_internal("Invalid integer condition!"
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 4427)
;
4428 case X86::COND_E:
4429 case X86::COND_NE:
4430 case X86::COND_B:
4431 case X86::COND_A:
4432 case X86::COND_BE:
4433 case X86::COND_AE:
4434 return true;
4435 case X86::COND_G:
4436 case X86::COND_GE:
4437 case X86::COND_L:
4438 case X86::COND_LE:
4439 return false;
4440 }
4441}
4442
4443static X86::CondCode TranslateIntegerX86CC(ISD::CondCode SetCCOpcode) {
4444 switch (SetCCOpcode) {
4445 default: llvm_unreachable("Invalid integer condition!")::llvm::llvm_unreachable_internal("Invalid integer condition!"
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 4445)
;
4446 case ISD::SETEQ: return X86::COND_E;
4447 case ISD::SETGT: return X86::COND_G;
4448 case ISD::SETGE: return X86::COND_GE;
4449 case ISD::SETLT: return X86::COND_L;
4450 case ISD::SETLE: return X86::COND_LE;
4451 case ISD::SETNE: return X86::COND_NE;
4452 case ISD::SETULT: return X86::COND_B;
4453 case ISD::SETUGT: return X86::COND_A;
4454 case ISD::SETULE: return X86::COND_BE;
4455 case ISD::SETUGE: return X86::COND_AE;
4456 }
4457}
4458
4459/// Do a one-to-one translation of a ISD::CondCode to the X86-specific
4460/// condition code, returning the condition code and the LHS/RHS of the
4461/// comparison to make.
4462static X86::CondCode TranslateX86CC(ISD::CondCode SetCCOpcode, const SDLoc &DL,
4463 bool isFP, SDValue &LHS, SDValue &RHS,
4464 SelectionDAG &DAG) {
4465 if (!isFP) {
4466 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
4467 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
4468 // X > -1 -> X == 0, jump !sign.
4469 RHS = DAG.getConstant(0, DL, RHS.getValueType());
4470 return X86::COND_NS;
4471 }
4472 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
4473 // X < 0 -> X == 0, jump on sign.
4474 return X86::COND_S;
4475 }
4476 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
4477 // X < 1 -> X <= 0
4478 RHS = DAG.getConstant(0, DL, RHS.getValueType());
4479 return X86::COND_LE;
4480 }
4481 }
4482
4483 return TranslateIntegerX86CC(SetCCOpcode);
4484 }
4485
4486 // First determine if it is required or is profitable to flip the operands.
4487
4488 // If LHS is a foldable load, but RHS is not, flip the condition.
4489 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
4490 !ISD::isNON_EXTLoad(RHS.getNode())) {
4491 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
4492 std::swap(LHS, RHS);
4493 }
4494
4495 switch (SetCCOpcode) {
4496 default: break;
4497 case ISD::SETOLT:
4498 case ISD::SETOLE:
4499 case ISD::SETUGT:
4500 case ISD::SETUGE:
4501 std::swap(LHS, RHS);
4502 break;
4503 }
4504
4505 // On a floating point condition, the flags are set as follows:
4506 // ZF PF CF op
4507 // 0 | 0 | 0 | X > Y
4508 // 0 | 0 | 1 | X < Y
4509 // 1 | 0 | 0 | X == Y
4510 // 1 | 1 | 1 | unordered
4511 switch (SetCCOpcode) {
4512 default: llvm_unreachable("Condcode should be pre-legalized away")::llvm::llvm_unreachable_internal("Condcode should be pre-legalized away"
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 4512)
;
4513 case ISD::SETUEQ:
4514 case ISD::SETEQ: return X86::COND_E;
4515 case ISD::SETOLT: // flipped
4516 case ISD::SETOGT:
4517 case ISD::SETGT: return X86::COND_A;
4518 case ISD::SETOLE: // flipped
4519 case ISD::SETOGE:
4520 case ISD::SETGE: return X86::COND_AE;
4521 case ISD::SETUGT: // flipped
4522 case ISD::SETULT:
4523 case ISD::SETLT: return X86::COND_B;
4524 case ISD::SETUGE: // flipped
4525 case ISD::SETULE:
4526 case ISD::SETLE: return X86::COND_BE;
4527 case ISD::SETONE:
4528 case ISD::SETNE: return X86::COND_NE;
4529 case ISD::SETUO: return X86::COND_P;
4530 case ISD::SETO: return X86::COND_NP;
4531 case ISD::SETOEQ:
4532 case ISD::SETUNE: return X86::COND_INVALID;
4533 }
4534}
4535
4536/// Is there a floating point cmov for the specific X86 condition code?
4537/// Current x86 isa includes the following FP cmov instructions:
4538/// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
4539static bool hasFPCMov(unsigned X86CC) {
4540 switch (X86CC) {
4541 default:
4542 return false;
4543 case X86::COND_B:
4544 case X86::COND_BE:
4545 case X86::COND_E:
4546 case X86::COND_P:
4547 case X86::COND_A:
4548 case X86::COND_AE:
4549 case X86::COND_NE:
4550 case X86::COND_NP:
4551 return true;
4552 }
4553}
4554
4555
4556bool X86TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
4557 const CallInst &I,
4558 MachineFunction &MF,
4559 unsigned Intrinsic) const {
4560
4561 const IntrinsicData* IntrData = getIntrinsicWithChain(Intrinsic);
4562 if (!IntrData)
4563 return false;
4564
4565 Info.opc = ISD::INTRINSIC_W_CHAIN;
4566 Info.flags = MachineMemOperand::MONone;
4567 Info.offset = 0;
4568
4569 switch (IntrData->Type) {
4570 case EXPAND_FROM_MEM: {
4571 Info.ptrVal = I.getArgOperand(0);
4572 Info.memVT = MVT::getVT(I.getType());
4573 Info.align = 1;
4574 Info.flags |= MachineMemOperand::MOLoad;
4575 break;
4576 }
4577 case COMPRESS_TO_MEM: {
4578 Info.ptrVal = I.getArgOperand(0);
4579 Info.memVT = MVT::getVT(I.getArgOperand(1)->getType());
4580 Info.align = 1;
4581 Info.flags |= MachineMemOperand::MOStore;
4582 break;
4583 }
4584 case TRUNCATE_TO_MEM_VI8:
4585 case TRUNCATE_TO_MEM_VI16:
4586 case TRUNCATE_TO_MEM_VI32: {
4587 Info.ptrVal = I.getArgOperand(0);
4588 MVT VT = MVT::getVT(I.getArgOperand(1)->getType());
4589 MVT ScalarVT = MVT::INVALID_SIMPLE_VALUE_TYPE;
4590 if (IntrData->Type == TRUNCATE_TO_MEM_VI8)
4591 ScalarVT = MVT::i8;
4592 else if (IntrData->Type == TRUNCATE_TO_MEM_VI16)
4593 ScalarVT = MVT::i16;
4594 else if (IntrData->Type == TRUNCATE_TO_MEM_VI32)
4595 ScalarVT = MVT::i32;
4596
4597 Info.memVT = MVT::getVectorVT(ScalarVT, VT.getVectorNumElements());
4598 Info.align = 1;
4599 Info.flags |= MachineMemOperand::MOStore;
4600 break;
4601 }
4602 default:
4603 return false;
4604 }
4605
4606 return true;
4607}
4608
4609/// Returns true if the target can instruction select the
4610/// specified FP immediate natively. If false, the legalizer will
4611/// materialize the FP immediate as a load from a constant pool.
4612bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
4613 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
4614 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
4615 return true;
4616 }
4617 return false;
4618}
4619
4620bool X86TargetLowering::shouldReduceLoadWidth(SDNode *Load,
4621 ISD::LoadExtType ExtTy,
4622 EVT NewVT) const {
4623 // "ELF Handling for Thread-Local Storage" specifies that R_X86_64_GOTTPOFF
4624 // relocation target a movq or addq instruction: don't let the load shrink.
4625 SDValue BasePtr = cast<LoadSDNode>(Load)->getBasePtr();
4626 if (BasePtr.getOpcode() == X86ISD::WrapperRIP)
4627 if (const auto *GA = dyn_cast<GlobalAddressSDNode>(BasePtr.getOperand(0)))
4628 return GA->getTargetFlags() != X86II::MO_GOTTPOFF;
4629 return true;
4630}
4631
4632/// \brief Returns true if it is beneficial to convert a load of a constant
4633/// to just the constant itself.
4634bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
4635 Type *Ty) const {
4636 assert(Ty->isIntegerTy())(static_cast <bool> (Ty->isIntegerTy()) ? void (0) :
__assert_fail ("Ty->isIntegerTy()", "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 4636, __extension__ __PRETTY_FUNCTION__))
;
4637
4638 unsigned BitSize = Ty->getPrimitiveSizeInBits();
4639 if (BitSize == 0 || BitSize > 64)
4640 return false;
4641 return true;
4642}
4643
4644bool X86TargetLowering::convertSelectOfConstantsToMath(EVT VT) const {
4645 // TODO: It might be a win to ease or lift this restriction, but the generic
4646 // folds in DAGCombiner conflict with vector folds for an AVX512 target.
4647 if (VT.isVector() && Subtarget.hasAVX512())
4648 return false;
4649
4650 return true;
4651}
4652
4653bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
4654 unsigned Index) const {
4655 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))
4656 return false;
4657
4658 // Mask vectors support all subregister combinations and operations that
4659 // extract half of vector.
4660 if (ResVT.getVectorElementType() == MVT::i1)
4661 return Index == 0 || ((ResVT.getSizeInBits() == SrcVT.getSizeInBits()*2) &&
4662 (Index == ResVT.getVectorNumElements()));
4663
4664 return (Index % ResVT.getVectorNumElements()) == 0;
4665}
4666
4667bool X86TargetLowering::isCheapToSpeculateCttz() const {
4668 // Speculate cttz only if we can directly use TZCNT.
4669 return Subtarget.hasBMI();
4670}
4671
4672bool X86TargetLowering::isCheapToSpeculateCtlz() const {
4673 // Speculate ctlz only if we can directly use LZCNT.
4674 return Subtarget.hasLZCNT();
4675}
4676
4677bool X86TargetLowering::isLoadBitCastBeneficial(EVT LoadVT,
4678 EVT BitcastVT) const {
4679 if (!Subtarget.hasDQI() && BitcastVT == MVT::v8i1)
4680 return false;
4681
4682 return TargetLowering::isLoadBitCastBeneficial(LoadVT, BitcastVT);
4683}
4684
4685bool X86TargetLowering::canMergeStoresTo(unsigned AddressSpace, EVT MemVT,
4686 const SelectionDAG &DAG) const {
4687 // Do not merge to float value size (128 bytes) if no implicit
4688 // float attribute is set.
4689 bool NoFloat = DAG.getMachineFunction().getFunction().hasFnAttribute(
4690 Attribute::NoImplicitFloat);
4691
4692 if (NoFloat) {
4693 unsigned MaxIntSize = Subtarget.is64Bit() ? 64 : 32;
4694 return (MemVT.getSizeInBits() <= MaxIntSize);
4695 }
4696 return true;
4697}
4698
4699bool X86TargetLowering::isCtlzFast() const {
4700 return Subtarget.hasFastLZCNT();
4701}
4702
4703bool X86TargetLowering::isMaskAndCmp0FoldingBeneficial(
4704 const Instruction &AndI) const {
4705 return true;
4706}
4707
4708bool X86TargetLowering::hasAndNotCompare(SDValue Y) const {
4709 if (!Subtarget.hasBMI())
4710 return false;
4711
4712 // There are only 32-bit and 64-bit forms for 'andn'.
4713 EVT VT = Y.getValueType();
4714 if (VT != MVT::i32 && VT != MVT::i64)
4715 return false;
4716
4717 return true;
4718}
4719
4720MVT X86TargetLowering::hasFastEqualityCompare(unsigned NumBits) const {
4721 MVT VT = MVT::getIntegerVT(NumBits);
4722 if (isTypeLegal(VT))
4723 return VT;
4724
4725 // PMOVMSKB can handle this.
4726 if (NumBits == 128 && isTypeLegal(MVT::v16i8))
4727 return MVT::v16i8;
4728
4729 // VPMOVMSKB can handle this.
4730 if (NumBits == 256 && isTypeLegal(MVT::v32i8))
4731 return MVT::v32i8;
4732
4733 // TODO: Allow 64-bit type for 32-bit target.
4734 // TODO: 512-bit types should be allowed, but make sure that those
4735 // cases are handled in combineVectorSizedSetCCEquality().
4736
4737 return MVT::INVALID_SIMPLE_VALUE_TYPE;
4738}
4739
4740/// Val is the undef sentinel value or equal to the specified value.
4741static bool isUndefOrEqual(int Val, int CmpVal) {
4742 return ((Val == SM_SentinelUndef) || (Val == CmpVal));
4743}
4744
4745/// Val is either the undef or zero sentinel value.
4746static bool isUndefOrZero(int Val) {
4747 return ((Val == SM_SentinelUndef) || (Val == SM_SentinelZero));
4748}
4749
4750/// Return true if every element in Mask, beginning
4751/// from position Pos and ending in Pos+Size is the undef sentinel value.
4752static bool isUndefInRange(ArrayRef<int> Mask, unsigned Pos, unsigned Size) {
4753 for (unsigned i = Pos, e = Pos + Size; i != e; ++i)
4754 if (Mask[i] != SM_SentinelUndef)
4755 return false;
4756 return true;
4757}
4758
4759/// Return true if Val is undef or if its value falls within the
4760/// specified range (L, H].
4761static bool isUndefOrInRange(int Val, int Low, int Hi) {
4762 return (Val == SM_SentinelUndef) || (Val >= Low && Val < Hi);
4763}
4764
4765/// Return true if every element in Mask is undef or if its value
4766/// falls within the specified range (L, H].
4767static bool isUndefOrInRange(ArrayRef<int> Mask,
4768 int Low, int Hi) {
4769 for (int M : Mask)
4770 if (!isUndefOrInRange(M, Low, Hi))
4771 return false;
4772 return true;
4773}
4774
4775/// Return true if Val is undef, zero or if its value falls within the
4776/// specified range (L, H].
4777static bool isUndefOrZeroOrInRange(int Val, int Low, int Hi) {
4778 return isUndefOrZero(Val) || (Val >= Low && Val < Hi);
4779}
4780
4781/// Return true if every element in Mask is undef, zero or if its value
4782/// falls within the specified range (L, H].
4783static bool isUndefOrZeroOrInRange(ArrayRef<int> Mask, int Low, int Hi) {
4784 for (int M : Mask)
4785 if (!isUndefOrZeroOrInRange(M, Low, Hi))
4786 return false;
4787 return true;
4788}
4789
4790/// Return true if every element in Mask, beginning
4791/// from position Pos and ending in Pos+Size, falls within the specified
4792/// sequential range (Low, Low+Size]. or is undef.
4793static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
4794 unsigned Pos, unsigned Size, int Low) {
4795 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
4796 if (!isUndefOrEqual(Mask[i], Low))
4797 return false;
4798 return true;
4799}
4800
4801/// Return true if every element in Mask, beginning
4802/// from position Pos and ending in Pos+Size, falls within the specified
4803/// sequential range (Low, Low+Size], or is undef or is zero.
4804static bool isSequentialOrUndefOrZeroInRange(ArrayRef<int> Mask, unsigned Pos,
4805 unsigned Size, int Low) {
4806 for (unsigned i = Pos, e = Pos + Size; i != e; ++i, ++Low)
4807 if (!isUndefOrZero(Mask[i]) && Mask[i] != Low)
4808 return false;
4809 return true;
4810}
4811
4812/// Return true if every element in Mask, beginning
4813/// from position Pos and ending in Pos+Size is undef or is zero.
4814static bool isUndefOrZeroInRange(ArrayRef<int> Mask, unsigned Pos,
4815 unsigned Size) {
4816 for (unsigned i = Pos, e = Pos + Size; i != e; ++i)
4817 if (!isUndefOrZero(Mask[i]))
4818 return false;
4819 return true;
4820}
4821
4822/// \brief Helper function to test whether a shuffle mask could be
4823/// simplified by widening the elements being shuffled.
4824///
4825/// Appends the mask for wider elements in WidenedMask if valid. Otherwise
4826/// leaves it in an unspecified state.
4827///
4828/// NOTE: This must handle normal vector shuffle masks and *target* vector
4829/// shuffle masks. The latter have the special property of a '-2' representing
4830/// a zero-ed lane of a vector.
4831static bool canWidenShuffleElements(ArrayRef<int> Mask,
4832 SmallVectorImpl<int> &WidenedMask) {
4833 WidenedMask.assign(Mask.size() / 2, 0);
4834 for (int i = 0, Size = Mask.size(); i < Size; i += 2) {
4835 int M0 = Mask[i];
4836 int M1 = Mask[i + 1];
4837
4838 // If both elements are undef, its trivial.
4839 if (M0 == SM_SentinelUndef && M1 == SM_SentinelUndef) {
4840 WidenedMask[i / 2] = SM_SentinelUndef;
4841 continue;
4842 }
4843
4844 // Check for an undef mask and a mask value properly aligned to fit with
4845 // a pair of values. If we find such a case, use the non-undef mask's value.
4846 if (M0 == SM_SentinelUndef && M1 >= 0 && (M1 % 2) == 1) {
4847 WidenedMask[i / 2] = M1 / 2;
4848 continue;
4849 }
4850 if (M1 == SM_SentinelUndef && M0 >= 0 && (M0 % 2) == 0) {
4851 WidenedMask[i / 2] = M0 / 2;
4852 continue;
4853 }
4854
4855 // When zeroing, we need to spread the zeroing across both lanes to widen.
4856 if (M0 == SM_SentinelZero || M1 == SM_SentinelZero) {
4857 if ((M0 == SM_SentinelZero || M0 == SM_SentinelUndef) &&
4858 (M1 == SM_SentinelZero || M1 == SM_SentinelUndef)) {
4859 WidenedMask[i / 2] = SM_SentinelZero;
4860 continue;
4861 }
4862 return false;
4863 }
4864
4865 // Finally check if the two mask values are adjacent and aligned with
4866 // a pair.
4867 if (M0 != SM_SentinelUndef && (M0 % 2) == 0 && (M0 + 1) == M1) {
4868 WidenedMask[i / 2] = M0 / 2;
4869 continue;
4870 }
4871
4872 // Otherwise we can't safely widen the elements used in this shuffle.
4873 return false;
4874 }
4875 assert(WidenedMask.size() == Mask.size() / 2 &&(static_cast <bool> (WidenedMask.size() == Mask.size() /
2 && "Incorrect size of mask after widening the elements!"
) ? void (0) : __assert_fail ("WidenedMask.size() == Mask.size() / 2 && \"Incorrect size of mask after widening the elements!\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 4876, __extension__ __PRETTY_FUNCTION__))
4876 "Incorrect size of mask after widening the elements!")(static_cast <bool> (WidenedMask.size() == Mask.size() /
2 && "Incorrect size of mask after widening the elements!"
) ? void (0) : __assert_fail ("WidenedMask.size() == Mask.size() / 2 && \"Incorrect size of mask after widening the elements!\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 4876, __extension__ __PRETTY_FUNCTION__))
;
4877
4878 return true;
4879}
4880
4881/// Returns true if Elt is a constant zero or a floating point constant +0.0.
4882bool X86::isZeroNode(SDValue Elt) {
4883 return isNullConstant(Elt) || isNullFPConstant(Elt);
4884}
4885
4886// Build a vector of constants.
4887// Use an UNDEF node if MaskElt == -1.
4888// Split 64-bit constants in the 32-bit mode.
4889static SDValue getConstVector(ArrayRef<int> Values, MVT VT, SelectionDAG &DAG,
4890 const SDLoc &dl, bool IsMask = false) {
4891
4892 SmallVector<SDValue, 32> Ops;
4893 bool Split = false;
4894
4895 MVT ConstVecVT = VT;
4896 unsigned NumElts = VT.getVectorNumElements();
4897 bool In64BitMode = DAG.getTargetLoweringInfo().isTypeLegal(MVT::i64);
4898 if (!In64BitMode && VT.getVectorElementType() == MVT::i64) {
4899 ConstVecVT = MVT::getVectorVT(MVT::i32, NumElts * 2);
4900 Split = true;
4901 }
4902
4903 MVT EltVT = ConstVecVT.getVectorElementType();
4904 for (unsigned i = 0; i < NumElts; ++i) {
4905 bool IsUndef = Values[i] < 0 && IsMask;
4906 SDValue OpNode = IsUndef ? DAG.getUNDEF(EltVT) :
4907 DAG.getConstant(Values[i], dl, EltVT);
4908 Ops.push_back(OpNode);
4909 if (Split)
4910 Ops.push_back(IsUndef ? DAG.getUNDEF(EltVT) :
4911 DAG.getConstant(0, dl, EltVT));
4912 }
4913 SDValue ConstsNode = DAG.getBuildVector(ConstVecVT, dl, Ops);
4914 if (Split)
4915 ConstsNode = DAG.getBitcast(VT, ConstsNode);
4916 return ConstsNode;
4917}
4918
4919static SDValue getConstVector(ArrayRef<APInt> Bits, APInt &Undefs,
4920 MVT VT, SelectionDAG &DAG, const SDLoc &dl) {
4921 assert(Bits.size() == Undefs.getBitWidth() &&(static_cast <bool> (Bits.size() == Undefs.getBitWidth(
) && "Unequal constant and undef arrays") ? void (0) :
__assert_fail ("Bits.size() == Undefs.getBitWidth() && \"Unequal constant and undef arrays\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 4922, __extension__ __PRETTY_FUNCTION__))
4922 "Unequal constant and undef arrays")(static_cast <bool> (Bits.size() == Undefs.getBitWidth(
) && "Unequal constant and undef arrays") ? void (0) :
__assert_fail ("Bits.size() == Undefs.getBitWidth() && \"Unequal constant and undef arrays\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 4922, __extension__ __PRETTY_FUNCTION__))
;
4923 SmallVector<SDValue, 32> Ops;
4924 bool Split = false;
4925
4926 MVT ConstVecVT = VT;
4927 unsigned NumElts = VT.getVectorNumElements();
4928 bool In64BitMode = DAG.getTargetLoweringInfo().isTypeLegal(MVT::i64);
4929 if (!In64BitMode && VT.getVectorElementType() == MVT::i64) {
4930 ConstVecVT = MVT::getVectorVT(MVT::i32, NumElts * 2);
4931 Split = true;
4932 }
4933
4934 MVT EltVT = ConstVecVT.getVectorElementType();
4935 for (unsigned i = 0, e = Bits.size(); i != e; ++i) {
4936 if (Undefs[i]) {
4937 Ops.append(Split ? 2 : 1, DAG.getUNDEF(EltVT));
4938 continue;
4939 }
4940 const APInt &V = Bits[i];
4941 assert(V.getBitWidth() == VT.getScalarSizeInBits() && "Unexpected sizes")(static_cast <bool> (V.getBitWidth() == VT.getScalarSizeInBits
() && "Unexpected sizes") ? void (0) : __assert_fail (
"V.getBitWidth() == VT.getScalarSizeInBits() && \"Unexpected sizes\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 4941, __extension__ __PRETTY_FUNCTION__))
;
4942 if (Split) {
4943 Ops.push_back(DAG.getConstant(V.trunc(32), dl, EltVT));
4944 Ops.push_back(DAG.getConstant(V.lshr(32).trunc(32), dl, EltVT));
4945 } else if (EltVT == MVT::f32) {
4946 APFloat FV(APFloat::IEEEsingle(), V);
4947 Ops.push_back(DAG.getConstantFP(FV, dl, EltVT));
4948 } else if (EltVT == MVT::f64) {
4949 APFloat FV(APFloat::IEEEdouble(), V);
4950 Ops.push_back(DAG.getConstantFP(FV, dl, EltVT));
4951 } else {
4952 Ops.push_back(DAG.getConstant(V, dl, EltVT));
4953 }
4954 }
4955
4956 SDValue ConstsNode = DAG.getBuildVector(ConstVecVT, dl, Ops);
4957 return DAG.getBitcast(VT, ConstsNode);
4958}
4959
4960/// Returns a vector of specified type with all zero elements.
4961static SDValue getZeroVector(MVT VT, const X86Subtarget &Subtarget,
4962 SelectionDAG &DAG, const SDLoc &dl) {
4963 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector() ||(static_cast <bool> ((VT.is128BitVector() || VT.is256BitVector
() || VT.is512BitVector() || VT.getVectorElementType() == MVT
::i1) && "Unexpected vector type") ? void (0) : __assert_fail
("(VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector() || VT.getVectorElementType() == MVT::i1) && \"Unexpected vector type\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 4965, __extension__ __PRETTY_FUNCTION__))
4964 VT.getVectorElementType() == MVT::i1) &&(static_cast <bool> ((VT.is128BitVector() || VT.is256BitVector
() || VT.is512BitVector() || VT.getVectorElementType() == MVT
::i1) && "Unexpected vector type") ? void (0) : __assert_fail
("(VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector() || VT.getVectorElementType() == MVT::i1) && \"Unexpected vector type\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 4965, __extension__ __PRETTY_FUNCTION__))
4965 "Unexpected vector type")(static_cast <bool> ((VT.is128BitVector() || VT.is256BitVector
() || VT.is512BitVector() || VT.getVectorElementType() == MVT
::i1) && "Unexpected vector type") ? void (0) : __assert_fail
("(VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector() || VT.getVectorElementType() == MVT::i1) && \"Unexpected vector type\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 4965, __extension__ __PRETTY_FUNCTION__))
;
4966
4967 // Try to build SSE/AVX zero vectors as <N x i32> bitcasted to their dest
4968 // type. This ensures they get CSE'd. But if the integer type is not
4969 // available, use a floating-point +0.0 instead.
4970 SDValue Vec;
4971 if (!Subtarget.hasSSE2() && VT.is128BitVector()) {
4972 Vec = DAG.getConstantFP(+0.0, dl, MVT::v4f32);
4973 } else if (VT.getVectorElementType() == MVT::i1) {
4974 assert((Subtarget.hasBWI() || VT.getVectorNumElements() <= 16) &&(static_cast <bool> ((Subtarget.hasBWI() || VT.getVectorNumElements
() <= 16) && "Unexpected vector type") ? void (0) :
__assert_fail ("(Subtarget.hasBWI() || VT.getVectorNumElements() <= 16) && \"Unexpected vector type\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 4975, __extension__ __PRETTY_FUNCTION__))
4975 "Unexpected vector type")(static_cast <bool> ((Subtarget.hasBWI() || VT.getVectorNumElements
() <= 16) && "Unexpected vector type") ? void (0) :
__assert_fail ("(Subtarget.hasBWI() || VT.getVectorNumElements() <= 16) && \"Unexpected vector type\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 4975, __extension__ __PRETTY_FUNCTION__))
;
4976 Vec = DAG.getConstant(0, dl, VT);
4977 } else {
4978 unsigned Num32BitElts = VT.getSizeInBits() / 32;
4979 Vec = DAG.getConstant(0, dl, MVT::getVectorVT(MVT::i32, Num32BitElts));
4980 }
4981 return DAG.getBitcast(VT, Vec);
4982}
4983
4984static SDValue extractSubVector(SDValue Vec, unsigned IdxVal, SelectionDAG &DAG,
4985 const SDLoc &dl, unsigned vectorWidth) {
4986 EVT VT = Vec.getValueType();
4987 EVT ElVT = VT.getVectorElementType();
4988 unsigned Factor = VT.getSizeInBits()/vectorWidth;
4989 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
4990 VT.getVectorNumElements()/Factor);
4991
4992 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
4993 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
4994 assert(isPowerOf2_32(ElemsPerChunk) && "Elements per chunk not power of 2")(static_cast <bool> (isPowerOf2_32(ElemsPerChunk) &&
"Elements per chunk not power of 2") ? void (0) : __assert_fail
("isPowerOf2_32(ElemsPerChunk) && \"Elements per chunk not power of 2\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 4994, __extension__ __PRETTY_FUNCTION__))
;
4995
4996 // This is the index of the first element of the vectorWidth-bit chunk
4997 // we want. Since ElemsPerChunk is a power of 2 just need to clear bits.
4998 IdxVal &= ~(ElemsPerChunk - 1);
4999
5000 // If the input is a buildvector just emit a smaller one.
5001 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
5002 return DAG.getBuildVector(ResultVT, dl,
5003 Vec->ops().slice(IdxVal, ElemsPerChunk));
5004
5005 SDValue VecIdx = DAG.getIntPtrConstant(IdxVal, dl);
5006 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, VecIdx);
5007}
5008
5009/// Generate a DAG to grab 128-bits from a vector > 128 bits. This
5010/// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
5011/// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
5012/// instructions or a simple subregister reference. Idx is an index in the
5013/// 128 bits we want. It need not be aligned to a 128-bit boundary. That makes
5014/// lowering EXTRACT_VECTOR_ELT operations easier.
5015static SDValue extract128BitVector(SDValue Vec, unsigned IdxVal,
5016 SelectionDAG &DAG, const SDLoc &dl) {
5017 assert((Vec.getValueType().is256BitVector() ||(static_cast <bool> ((Vec.getValueType().is256BitVector
() || Vec.getValueType().is512BitVector()) && "Unexpected vector size!"
) ? void (0) : __assert_fail ("(Vec.getValueType().is256BitVector() || Vec.getValueType().is512BitVector()) && \"Unexpected vector size!\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 5018, __extension__ __PRETTY_FUNCTION__))
5018 Vec.getValueType().is512BitVector()) && "Unexpected vector size!")(static_cast <bool> ((Vec.getValueType().is256BitVector
() || Vec.getValueType().is512BitVector()) && "Unexpected vector size!"
) ? void (0) : __assert_fail ("(Vec.getValueType().is256BitVector() || Vec.getValueType().is512BitVector()) && \"Unexpected vector size!\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 5018, __extension__ __PRETTY_FUNCTION__))
;
5019 return extractSubVector(Vec, IdxVal, DAG, dl, 128);
5020}
5021
5022/// Generate a DAG to grab 256-bits from a 512-bit vector.
5023static SDValue extract256BitVector(SDValue Vec, unsigned IdxVal,
5024 SelectionDAG &DAG, const SDLoc &dl) {
5025 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!")(static_cast <bool> (Vec.getValueType().is512BitVector(
) && "Unexpected vector size!") ? void (0) : __assert_fail
("Vec.getValueType().is512BitVector() && \"Unexpected vector size!\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 5025, __extension__ __PRETTY_FUNCTION__))
;
5026 return extractSubVector(Vec, IdxVal, DAG, dl, 256);
5027}
5028
5029static SDValue insertSubVector(SDValue Result, SDValue Vec, unsigned IdxVal,
5030 SelectionDAG &DAG, const SDLoc &dl,
5031 unsigned vectorWidth) {
5032 assert((vectorWidth == 128 || vectorWidth == 256) &&(static_cast <bool> ((vectorWidth == 128 || vectorWidth
== 256) && "Unsupported vector width") ? void (0) : __assert_fail
("(vectorWidth == 128 || vectorWidth == 256) && \"Unsupported vector width\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 5033, __extension__ __PRETTY_FUNCTION__))
5033 "Unsupported vector width")(static_cast <bool> ((vectorWidth == 128 || vectorWidth
== 256) && "Unsupported vector width") ? void (0) : __assert_fail
("(vectorWidth == 128 || vectorWidth == 256) && \"Unsupported vector width\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 5033, __extension__ __PRETTY_FUNCTION__))
;
5034 // Inserting UNDEF is Result
5035 if (Vec.isUndef())
5036 return Result;
5037 EVT VT = Vec.getValueType();
5038 EVT ElVT = VT.getVectorElementType();
5039 EVT ResultVT = Result.getValueType();
5040
5041 // Insert the relevant vectorWidth bits.
5042 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
5043 assert(isPowerOf2_32(ElemsPerChunk) && "Elements per chunk not power of 2")(static_cast <bool> (isPowerOf2_32(ElemsPerChunk) &&
"Elements per chunk not power of 2") ? void (0) : __assert_fail
("isPowerOf2_32(ElemsPerChunk) && \"Elements per chunk not power of 2\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 5043, __extension__ __PRETTY_FUNCTION__))
;
5044
5045 // This is the index of the first element of the vectorWidth-bit chunk
5046 // we want. Since ElemsPerChunk is a power of 2 just need to clear bits.
5047 IdxVal &= ~(ElemsPerChunk - 1);
5048
5049 SDValue VecIdx = DAG.getIntPtrConstant(IdxVal, dl);
5050 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, VecIdx);
5051}
5052
5053/// Generate a DAG to put 128-bits into a vector > 128 bits. This
5054/// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
5055/// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
5056/// simple superregister reference. Idx is an index in the 128 bits
5057/// we want. It need not be aligned to a 128-bit boundary. That makes
5058/// lowering INSERT_VECTOR_ELT operations easier.
5059static SDValue insert128BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
5060 SelectionDAG &DAG, const SDLoc &dl) {
5061 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!")(static_cast <bool> (Vec.getValueType().is128BitVector(
) && "Unexpected vector size!") ? void (0) : __assert_fail
("Vec.getValueType().is128BitVector() && \"Unexpected vector size!\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 5061, __extension__ __PRETTY_FUNCTION__))
;
5062 return insertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
5063}
5064
5065static SDValue insert256BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
5066 SelectionDAG &DAG, const SDLoc &dl) {
5067 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!")(static_cast <bool> (Vec.getValueType().is256BitVector(
) && "Unexpected vector size!") ? void (0) : __assert_fail
("Vec.getValueType().is256BitVector() && \"Unexpected vector size!\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 5067, __extension__ __PRETTY_FUNCTION__))
;
5068 return insertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
5069}
5070
5071// Helper for splitting operands of a binary operation to legal target size and
5072// apply a function on each part.
5073// Useful for operations that are available on SSE2 in 128-bit, on AVX2 in
5074// 256-bit and on AVX512BW in 512-bit.
5075// The argument VT is the type used for deciding if/how to split the operands
5076// Op0 and Op1. Op0 and Op1 do *not* have to be of type VT.
5077// The argument Builder is a function that will be applied on each split psrt:
5078// SDValue Builder(SelectionDAG&G, SDLoc, SDValue, SDValue)
5079template <typename F>
5080SDValue SplitBinaryOpsAndApply(SelectionDAG &DAG, const X86Subtarget &Subtarget,
5081 const SDLoc &DL, EVT VT, SDValue Op0,
5082 SDValue Op1, F Builder) {
5083 assert(Subtarget.hasSSE2() && "Target assumed to support at least SSE2")(static_cast <bool> (Subtarget.hasSSE2() && "Target assumed to support at least SSE2"
) ? void (0) : __assert_fail ("Subtarget.hasSSE2() && \"Target assumed to support at least SSE2\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 5083, __extension__ __PRETTY_FUNCTION__))
;
5084 unsigned NumSubs = 1;
5085 if (Subtarget.useBWIRegs()) {
5086 if (VT.getSizeInBits() > 512) {
5087 NumSubs = VT.getSizeInBits() / 512;
5088 assert((VT.getSizeInBits() % 512) == 0 && "Illegal vector size")(static_cast <bool> ((VT.getSizeInBits() % 512) == 0 &&
"Illegal vector size") ? void (0) : __assert_fail ("(VT.getSizeInBits() % 512) == 0 && \"Illegal vector size\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 5088, __extension__ __PRETTY_FUNCTION__))
;
5089 }
5090 } else if (Subtarget.hasAVX2()) {
5091 if (VT.getSizeInBits() > 256) {
5092 NumSubs = VT.getSizeInBits() / 256;
5093 assert((VT.getSizeInBits() % 256) == 0 && "Illegal vector size")(static_cast <bool> ((VT.getSizeInBits() % 256) == 0 &&
"Illegal vector size") ? void (0) : __assert_fail ("(VT.getSizeInBits() % 256) == 0 && \"Illegal vector size\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 5093, __extension__ __PRETTY_FUNCTION__))
;
5094 }
5095 } else {
5096 if (VT.getSizeInBits() > 128) {
5097 NumSubs = VT.getSizeInBits() / 128;
5098 assert((VT.getSizeInBits() % 128) == 0 && "Illegal vector size")(static_cast <bool> ((VT.getSizeInBits() % 128) == 0 &&
"Illegal vector size") ? void (0) : __assert_fail ("(VT.getSizeInBits() % 128) == 0 && \"Illegal vector size\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 5098, __extension__ __PRETTY_FUNCTION__))
;
5099 }
5100 }
5101
5102 if (NumSubs == 1)
5103 return Builder(DAG, DL, Op0, Op1);
5104
5105 SmallVector<SDValue, 4> Subs;
5106 EVT InVT = Op0.getValueType();
5107 EVT SubVT = EVT::getVectorVT(*DAG.getContext(), InVT.getScalarType(),
5108 InVT.getVectorNumElements() / NumSubs);
5109 for (unsigned i = 0; i != NumSubs; ++i) {
5110 unsigned Idx = i * SubVT.getVectorNumElements();
5111 SDValue LHS = extractSubVector(Op0, Idx, DAG, DL, SubVT.getSizeInBits());
5112 SDValue RHS = extractSubVector(Op1, Idx, DAG, DL, SubVT.getSizeInBits());
5113 Subs.push_back(Builder(DAG, DL, LHS, RHS));
5114 }
5115 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Subs);
5116}
5117
5118// Return true if the instruction zeroes the unused upper part of the
5119// destination and accepts mask.
5120static bool isMaskedZeroUpperBitsvXi1(unsigned int Opcode) {
5121 switch (Opcode) {
5122 default:
5123 return false;
5124 case X86ISD::CMPM:
5125 case X86ISD::CMPMU:
5126 case X86ISD::CMPM_RND:
5127 return true;
5128 }
5129}
5130
5131/// Insert i1-subvector to i1-vector.
5132static SDValue insert1BitVector(SDValue Op, SelectionDAG &DAG,
5133 const X86Subtarget &Subtarget) {
5134
5135 SDLoc dl(Op);
5136 SDValue Vec = Op.getOperand(0);
5137 SDValue SubVec = Op.getOperand(1);
5138 SDValue Idx = Op.getOperand(2);
5139
5140 if (!isa<ConstantSDNode>(Idx))
5141 return SDValue();
5142
5143 // Inserting undef is a nop. We can just return the original vector.
5144 if (SubVec.isUndef())
5145 return Vec;
5146
5147 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
5148 if (IdxVal == 0 && Vec.isUndef()) // the operation is legal
5149 return Op;
5150
5151 MVT OpVT = Op.getSimpleValueType();
5152 unsigned NumElems = OpVT.getVectorNumElements();
5153
5154 SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
5155
5156 // Extend to natively supported kshift.
5157 MVT WideOpVT = OpVT;
5158 if ((!Subtarget.hasDQI() && NumElems == 8) || NumElems < 8)
5159 WideOpVT = Subtarget.hasDQI() ? MVT::v8i1 : MVT::v16i1;
5160
5161 // Inserting into the lsbs of a zero vector is legal. ISel will insert shifts
5162 // if necessary.
5163 if (IdxVal == 0 && ISD::isBuildVectorAllZeros(Vec.getNode())) {
5164 // May need to promote to a legal type.
5165 Op = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, WideOpVT,
5166 getZeroVector(WideOpVT, Subtarget, DAG, dl),
5167 SubVec, Idx);
5168 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OpVT, Op, ZeroIdx);
5169 }
5170
5171 MVT SubVecVT = SubVec.getSimpleValueType();
5172 unsigned SubVecNumElems = SubVecVT.getVectorNumElements();
5173
5174 assert(IdxVal + SubVecNumElems <= NumElems &&(static_cast <bool> (IdxVal + SubVecNumElems <= NumElems
&& IdxVal % SubVecVT.getSizeInBits() == 0 &&
"Unexpected index value in INSERT_SUBVECTOR") ? void (0) : __assert_fail
("IdxVal + SubVecNumElems <= NumElems && IdxVal % SubVecVT.getSizeInBits() == 0 && \"Unexpected index value in INSERT_SUBVECTOR\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 5176, __extension__ __PRETTY_FUNCTION__))
5175 IdxVal % SubVecVT.getSizeInBits() == 0 &&(static_cast <bool> (IdxVal + SubVecNumElems <= NumElems
&& IdxVal % SubVecVT.getSizeInBits() == 0 &&
"Unexpected index value in INSERT_SUBVECTOR") ? void (0) : __assert_fail
("IdxVal + SubVecNumElems <= NumElems && IdxVal % SubVecVT.getSizeInBits() == 0 && \"Unexpected index value in INSERT_SUBVECTOR\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 5176, __extension__ __PRETTY_FUNCTION__))
5176 "Unexpected index value in INSERT_SUBVECTOR")(static_cast <bool> (IdxVal + SubVecNumElems <= NumElems
&& IdxVal % SubVecVT.getSizeInBits() == 0 &&
"Unexpected index value in INSERT_SUBVECTOR") ? void (0) : __assert_fail
("IdxVal + SubVecNumElems <= NumElems && IdxVal % SubVecVT.getSizeInBits() == 0 && \"Unexpected index value in INSERT_SUBVECTOR\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 5176, __extension__ __PRETTY_FUNCTION__))
;
5177
5178 SDValue Undef = DAG.getUNDEF(WideOpVT);
5179
5180 if (IdxVal == 0) {
5181 // Zero lower bits of the Vec
5182 SDValue ShiftBits = DAG.getConstant(SubVecNumElems, dl, MVT::i8);
5183 Vec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, WideOpVT, Undef, Vec,
5184 ZeroIdx);
5185 Vec = DAG.getNode(X86ISD::KSHIFTR, dl, WideOpVT, Vec, ShiftBits);
5186 Vec = DAG.getNode(X86ISD::KSHIFTL, dl, WideOpVT, Vec, ShiftBits);
5187 // Merge them together, SubVec should be zero extended.
5188 SubVec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, WideOpVT,
5189 getZeroVector(WideOpVT, Subtarget, DAG, dl),
5190 SubVec, ZeroIdx);
5191 Op = DAG.getNode(ISD::OR, dl, WideOpVT, Vec, SubVec);
5192 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OpVT, Op, ZeroIdx);
5193 }
5194
5195 SubVec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, WideOpVT,
5196 Undef, SubVec, ZeroIdx);
5197
5198 if (Vec.isUndef()) {
5199 assert(IdxVal != 0 && "Unexpected index")(static_cast <bool> (IdxVal != 0 && "Unexpected index"
) ? void (0) : __assert_fail ("IdxVal != 0 && \"Unexpected index\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 5199, __extension__ __PRETTY_FUNCTION__))
;
5200 SubVec = DAG.getNode(X86ISD::KSHIFTL, dl, WideOpVT, SubVec,
5201 DAG.getConstant(IdxVal, dl, MVT::i8));
5202 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OpVT, SubVec, ZeroIdx);
5203 }
5204
5205 if (ISD::isBuildVectorAllZeros(Vec.getNode())) {
5206 assert(IdxVal != 0 && "Unexpected index")(static_cast <bool> (IdxVal != 0 && "Unexpected index"
) ? void (0) : __assert_fail ("IdxVal != 0 && \"Unexpected index\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 5206, __extension__ __PRETTY_FUNCTION__))
;
5207 NumElems = WideOpVT.getVectorNumElements();
5208 unsigned ShiftLeft = NumElems - SubVecNumElems;
5209 unsigned ShiftRight = NumElems - SubVecNumElems - IdxVal;
5210 SubVec = DAG.getNode(X86ISD::KSHIFTL, dl, WideOpVT, SubVec,
5211 DAG.getConstant(ShiftLeft, dl, MVT::i8));
5212 if (ShiftRight != 0)
5213 SubVec = DAG.getNode(X86ISD::KSHIFTR, dl, WideOpVT, SubVec,
5214 DAG.getConstant(ShiftRight, dl, MVT::i8));
5215 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OpVT, SubVec, ZeroIdx);
5216 }
5217
5218 // Simple case when we put subvector in the upper part
5219 if (IdxVal + SubVecNumElems == NumElems) {
5220 SubVec = DAG.getNode(X86ISD::KSHIFTL, dl, WideOpVT, SubVec,
5221 DAG.getConstant(IdxVal, dl, MVT::i8));
5222 if (SubVecNumElems * 2 == NumElems) {
5223 // Special case, use legal zero extending insert_subvector. This allows
5224 // isel to opimitize when bits are known zero.
5225 Vec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVecVT, Vec, ZeroIdx);
5226 Vec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, WideOpVT,
5227 getZeroVector(WideOpVT, Subtarget, DAG, dl),
5228 Vec, ZeroIdx);
5229 } else {
5230 // Otherwise use explicit shifts to zero the bits.
5231 Vec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, WideOpVT,
5232 Undef, Vec, ZeroIdx);
5233 NumElems = WideOpVT.getVectorNumElements();
5234 SDValue ShiftBits = DAG.getConstant(NumElems - IdxVal, dl, MVT::i8);
5235 Vec = DAG.getNode(X86ISD::KSHIFTL, dl, WideOpVT, Vec, ShiftBits);
5236 Vec = DAG.getNode(X86ISD::KSHIFTR, dl, WideOpVT, Vec, ShiftBits);
5237 }
5238 Op = DAG.getNode(ISD::OR, dl, WideOpVT, Vec, SubVec);
5239 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OpVT, Op, ZeroIdx);
5240 }
5241
5242 // Inserting into the middle is more complicated.
5243
5244 NumElems = WideOpVT.getVectorNumElements();
5245
5246 // Widen the vector if needed.
5247 Vec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, WideOpVT, Undef, Vec, ZeroIdx);
5248 // Move the current value of the bit to be replace to the lsbs.
5249 Op = DAG.getNode(X86ISD::KSHIFTR, dl, WideOpVT, Vec,
5250 DAG.getConstant(IdxVal, dl, MVT::i8));
5251 // Xor with the new bit.
5252 Op = DAG.getNode(ISD::XOR, dl, WideOpVT, Op, SubVec);
5253 // Shift to MSB, filling bottom bits with 0.
5254 unsigned ShiftLeft = NumElems - SubVecNumElems;
5255 Op = DAG.getNode(X86ISD::KSHIFTL, dl, WideOpVT, Op,
5256 DAG.getConstant(ShiftLeft, dl, MVT::i8));
5257 // Shift to the final position, filling upper bits with 0.
5258 unsigned ShiftRight = NumElems - SubVecNumElems - IdxVal;
5259 Op = DAG.getNode(X86ISD::KSHIFTR, dl, WideOpVT, Op,
5260 DAG.getConstant(ShiftRight, dl, MVT::i8));
5261 // Xor with original vector leaving the new value.
5262 Op = DAG.getNode(ISD::XOR, dl, WideOpVT, Vec, Op);
5263 // Reduce to original width if needed.
5264 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OpVT, Op, ZeroIdx);
5265}
5266
5267/// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
5268/// instructions. This is used because creating CONCAT_VECTOR nodes of
5269/// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
5270/// large BUILD_VECTORS.
5271static SDValue concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
5272 unsigned NumElems, SelectionDAG &DAG,
5273 const SDLoc &dl) {
5274 SDValue V = insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
5275 return insert128BitVector(V, V2, NumElems / 2, DAG, dl);
5276}
5277
5278static SDValue concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
5279 unsigned NumElems, SelectionDAG &DAG,
5280 const SDLoc &dl) {
5281 SDValue V = insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
5282 return insert256BitVector(V, V2, NumElems / 2, DAG, dl);
5283}
5284
5285static SDValue concatSubVectors(SDValue V1, SDValue V2, EVT VT,
5286 unsigned NumElems, SelectionDAG &DAG,
5287 const SDLoc &dl, unsigned VectorWidth) {
5288 SDValue V = insertSubVector(DAG.getUNDEF(VT), V1, 0, DAG, dl, VectorWidth);
5289 return insertSubVector(V, V2, NumElems / 2, DAG, dl, VectorWidth);
5290}
5291
5292/// Returns a vector of specified type with all bits set.
5293/// Always build ones vectors as <4 x i32>, <8 x i32> or <16 x i32>.
5294/// Then bitcast to their original type, ensuring they get CSE'd.
5295static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, const SDLoc &dl) {
5296 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&(static_cast <bool> ((VT.is128BitVector() || VT.is256BitVector
() || VT.is512BitVector()) && "Expected a 128/256/512-bit vector type"
) ? void (0) : __assert_fail ("(VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) && \"Expected a 128/256/512-bit vector type\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 5297, __extension__ __PRETTY_FUNCTION__))
5297 "Expected a 128/256/512-bit vector type")(static_cast <bool> ((VT.is128BitVector() || VT.is256BitVector
() || VT.is512BitVector()) && "Expected a 128/256/512-bit vector type"
) ? void (0) : __assert_fail ("(VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) && \"Expected a 128/256/512-bit vector type\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 5297, __extension__ __PRETTY_FUNCTION__))
;
5298
5299 APInt Ones = APInt::getAllOnesValue(32);
5300 unsigned NumElts = VT.getSizeInBits() / 32;
5301 SDValue Vec = DAG.getConstant(Ones, dl, MVT::getVectorVT(MVT::i32, NumElts));
5302 return DAG.getBitcast(VT, Vec);
5303}
5304
5305static SDValue getExtendInVec(unsigned Opc, const SDLoc &DL, EVT VT, SDValue In,
5306 SelectionDAG &DAG) {
5307 EVT InVT = In.getValueType();
5308 assert((X86ISD::VSEXT == Opc || X86ISD::VZEXT == Opc) && "Unexpected opcode")(static_cast <bool> ((X86ISD::VSEXT == Opc || X86ISD::VZEXT
== Opc) && "Unexpected opcode") ? void (0) : __assert_fail
("(X86ISD::VSEXT == Opc || X86ISD::VZEXT == Opc) && \"Unexpected opcode\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 5308, __extension__ __PRETTY_FUNCTION__))
;
5309
5310 if (VT.is128BitVector() && InVT.is128BitVector())
5311 return X86ISD::VSEXT == Opc ? DAG.getSignExtendVectorInReg(In, DL, VT)
5312 : DAG.getZeroExtendVectorInReg(In, DL, VT);
5313
5314 // For 256-bit vectors, we only need the lower (128-bit) input half.
5315 // For 512-bit vectors, we only need the lower input half or quarter.
5316 if (VT.getSizeInBits() > 128 && InVT.getSizeInBits() > 128) {
5317 int Scale = VT.getScalarSizeInBits() / InVT.getScalarSizeInBits();
5318 In = extractSubVector(In, 0, DAG, DL,
5319 std::max(128, (int)VT.getSizeInBits() / Scale));
5320 }
5321
5322 return DAG.getNode(Opc, DL, VT, In);
5323}
5324
5325/// Returns a vector_shuffle node for an unpackl operation.
5326static SDValue getUnpackl(SelectionDAG &DAG, const SDLoc &dl, MVT VT,
5327 SDValue V1, SDValue V2) {
5328 SmallVector<int, 8> Mask;
5329 createUnpackShuffleMask(VT, Mask, /* Lo = */ true, /* Unary = */ false);
5330 return DAG.getVectorShuffle(VT, dl, V1, V2, Mask);
5331}
5332
5333/// Returns a vector_shuffle node for an unpackh operation.
5334static SDValue getUnpackh(SelectionDAG &DAG, const SDLoc &dl, MVT VT,
5335 SDValue V1, SDValue V2) {
5336 SmallVector<int, 8> Mask;
5337 createUnpackShuffleMask(VT, Mask, /* Lo = */ false, /* Unary = */ false);
5338 return DAG.getVectorShuffle(VT, dl, V1, V2, Mask);
5339}
5340
5341/// Return a vector_shuffle of the specified vector of zero or undef vector.
5342/// This produces a shuffle where the low element of V2 is swizzled into the
5343/// zero/undef vector, landing at element Idx.
5344/// This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
5345static SDValue getShuffleVectorZeroOrUndef(SDValue V2, int Idx,
5346 bool IsZero,
5347 const X86Subtarget &Subtarget,
5348 SelectionDAG &DAG) {
5349 MVT VT = V2.getSimpleValueType();
5350 SDValue V1 = IsZero
5351 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
5352 int NumElems = VT.getVectorNumElements();
5353 SmallVector<int, 16> MaskVec(NumElems);
5354 for (int i = 0; i != NumElems; ++i)
5355 // If this is the insertion idx, put the low elt of V2 here.
5356 MaskVec[i] = (i == Idx) ? NumElems : i;
5357 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, MaskVec);
5358}
5359
5360static SDValue peekThroughBitcasts(SDValue V) {
5361 while (V.getNode() && V.getOpcode() == ISD::BITCAST)
5362 V = V.getOperand(0);
5363 return V;
5364}
5365
5366static SDValue peekThroughOneUseBitcasts(SDValue V) {
5367 while (V.getNode() && V.getOpcode() == ISD::BITCAST &&
5368 V.getOperand(0).hasOneUse())
5369 V = V.getOperand(0);
5370 return V;
5371}
5372
5373static const Constant *getTargetConstantFromNode(SDValue Op) {
5374 Op = peekThroughBitcasts(Op);
5375
5376 auto *Load = dyn_cast<LoadSDNode>(Op);
5377 if (!Load)
5378 return nullptr;
5379
5380 SDValue Ptr = Load->getBasePtr();
5381 if (Ptr->getOpcode() == X86ISD::Wrapper ||
5382 Ptr->getOpcode() == X86ISD::WrapperRIP)
5383 Ptr = Ptr->getOperand(0);
5384
5385 auto *CNode = dyn_cast<ConstantPoolSDNode>(Ptr);
5386 if (!CNode || CNode->isMachineConstantPoolEntry())
5387 return nullptr;
5388
5389 return dyn_cast<Constant>(CNode->getConstVal());
5390}
5391
5392// Extract raw constant bits from constant pools.
5393static bool getTargetConstantBitsFromNode(SDValue Op, unsigned EltSizeInBits,
5394 APInt &UndefElts,
5395 SmallVectorImpl<APInt> &EltBits,
5396 bool AllowWholeUndefs = true,
5397 bool AllowPartialUndefs = true) {
5398 assert(EltBits.empty() && "Expected an empty EltBits vector")(static_cast <bool> (EltBits.empty() && "Expected an empty EltBits vector"
) ? void (0) : __assert_fail ("EltBits.empty() && \"Expected an empty EltBits vector\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 5398, __extension__ __PRETTY_FUNCTION__))
;
5399
5400 Op = peekThroughBitcasts(Op);
5401
5402 EVT VT = Op.getValueType();
5403 unsigned SizeInBits = VT.getSizeInBits();
5404 assert((SizeInBits % EltSizeInBits) == 0 && "Can't split constant!")(static_cast <bool> ((SizeInBits % EltSizeInBits) == 0 &&
"Can't split constant!") ? void (0) : __assert_fail ("(SizeInBits % EltSizeInBits) == 0 && \"Can't split constant!\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 5404, __extension__ __PRETTY_FUNCTION__))
;
5405 unsigned NumElts = SizeInBits / EltSizeInBits;
5406
5407 // Bitcast a source array of element bits to the target size.
5408 auto CastBitData = [&](APInt &UndefSrcElts, ArrayRef<APInt> SrcEltBits) {
5409 unsigned NumSrcElts = UndefSrcElts.getBitWidth();
5410 unsigned SrcEltSizeInBits = SrcEltBits[0].getBitWidth();
5411 assert((NumSrcElts * SrcEltSizeInBits) == SizeInBits &&(static_cast <bool> ((NumSrcElts * SrcEltSizeInBits) ==
SizeInBits && "Constant bit sizes don't match") ? void
(0) : __assert_fail ("(NumSrcElts * SrcEltSizeInBits) == SizeInBits && \"Constant bit sizes don't match\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 5412, __extension__ __PRETTY_FUNCTION__))
5412 "Constant bit sizes don't match")(static_cast <bool> ((NumSrcElts * SrcEltSizeInBits) ==
SizeInBits && "Constant bit sizes don't match") ? void
(0) : __assert_fail ("(NumSrcElts * SrcEltSizeInBits) == SizeInBits && \"Constant bit sizes don't match\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 5412, __extension__ __PRETTY_FUNCTION__))
;
5413
5414 // Don't split if we don't allow undef bits.
5415 bool AllowUndefs = AllowWholeUndefs || AllowPartialUndefs;
5416 if (UndefSrcElts.getBoolValue() && !AllowUndefs)
5417 return false;
5418
5419 // If we're already the right size, don't bother bitcasting.
5420 if (NumSrcElts == NumElts) {
5421 UndefElts = UndefSrcElts;
5422 EltBits.assign(SrcEltBits.begin(), SrcEltBits.end());
5423 return true;
5424 }
5425
5426 // Extract all the undef/constant element data and pack into single bitsets.
5427 APInt UndefBits(SizeInBits, 0);
5428 APInt MaskBits(SizeInBits, 0);
5429
5430 for (unsigned i = 0; i != NumSrcElts; ++i) {
5431 unsigned BitOffset = i * SrcEltSizeInBits;
5432 if (UndefSrcElts[i])
5433 UndefBits.setBits(BitOffset, BitOffset + SrcEltSizeInBits);
5434 MaskBits.insertBits(SrcEltBits[i], BitOffset);
5435 }
5436
5437 // Split the undef/constant single bitset data into the target elements.
5438 UndefElts = APInt(NumElts, 0);
5439 EltBits.resize(NumElts, APInt(EltSizeInBits, 0));
5440
5441 for (unsigned i = 0; i != NumElts; ++i) {
5442 unsigned BitOffset = i * EltSizeInBits;
5443 APInt UndefEltBits = UndefBits.extractBits(EltSizeInBits, BitOffset);
5444
5445 // Only treat an element as UNDEF if all bits are UNDEF.
5446 if (UndefEltBits.isAllOnesValue()) {
5447 if (!AllowWholeUndefs)
5448 return false;
5449 UndefElts.setBit(i);
5450 continue;
5451 }
5452
5453 // If only some bits are UNDEF then treat them as zero (or bail if not
5454 // supported).
5455 if (UndefEltBits.getBoolValue() && !AllowPartialUndefs)
5456 return false;
5457
5458 APInt Bits = MaskBits.extractBits(EltSizeInBits, BitOffset);
5459 EltBits[i] = Bits.getZExtValue();
5460 }
5461 return true;
5462 };
5463
5464 // Collect constant bits and insert into mask/undef bit masks.
5465 auto CollectConstantBits = [](const Constant *Cst, APInt &Mask, APInt &Undefs,
5466 unsigned UndefBitIndex) {
5467 if (!Cst)
5468 return false;
5469 if (isa<UndefValue>(Cst)) {
5470 Undefs.setBit(UndefBitIndex);
5471 return true;
5472 }
5473 if (auto *CInt = dyn_cast<ConstantInt>(Cst)) {
5474 Mask = CInt->getValue();
5475 return true;
5476 }
5477 if (auto *CFP = dyn_cast<ConstantFP>(Cst)) {
5478 Mask = CFP->getValueAPF().bitcastToAPInt();
5479 return true;
5480 }
5481 return false;
5482 };
5483
5484 // Handle UNDEFs.
5485 if (Op.isUndef()) {
5486 APInt UndefSrcElts = APInt::getAllOnesValue(NumElts);
5487 SmallVector<APInt, 64> SrcEltBits(NumElts, APInt(EltSizeInBits, 0));
5488 return CastBitData(UndefSrcElts, SrcEltBits);
5489 }
5490
5491 // Extract scalar constant bits.
5492 if (auto *Cst = dyn_cast<ConstantSDNode>(Op)) {
5493 APInt UndefSrcElts = APInt::getNullValue(1);
5494 SmallVector<APInt, 64> SrcEltBits(1, Cst->getAPIntValue());
5495 return CastBitData(UndefSrcElts, SrcEltBits);
5496 }
5497 if (auto *Cst = dyn_cast<ConstantFPSDNode>(Op)) {
5498 APInt UndefSrcElts = APInt::getNullValue(1);
5499 APInt RawBits = Cst->getValueAPF().bitcastToAPInt();
5500 SmallVector<APInt, 64> SrcEltBits(1, RawBits);
5501 return CastBitData(UndefSrcElts, SrcEltBits);
5502 }
5503
5504 // Extract constant bits from build vector.
5505 if (ISD::isBuildVectorOfConstantSDNodes(Op.getNode())) {
5506 unsigned SrcEltSizeInBits = VT.getScalarSizeInBits();
5507 unsigned NumSrcElts = SizeInBits / SrcEltSizeInBits;
5508
5509 APInt UndefSrcElts(NumSrcElts, 0);
5510 SmallVector<APInt, 64> SrcEltBits(NumSrcElts, APInt(SrcEltSizeInBits, 0));
5511 for (unsigned i = 0, e = Op.getNumOperands(); i != e; ++i) {
5512 const SDValue &Src = Op.getOperand(i);
5513 if (Src.isUndef()) {
5514 UndefSrcElts.setBit(i);
5515 continue;
5516 }
5517 auto *Cst = cast<ConstantSDNode>(Src);
5518 SrcEltBits[i] = Cst->getAPIntValue().zextOrTrunc(SrcEltSizeInBits);
5519 }
5520 return CastBitData(UndefSrcElts, SrcEltBits);
5521 }
5522
5523 // Extract constant bits from constant pool vector.
5524 if (auto *Cst = getTargetConstantFromNode(Op)) {
5525 Type *CstTy = Cst->getType();
5526 if (!CstTy->isVectorTy() || (SizeInBits != CstTy->getPrimitiveSizeInBits()))
5527 return false;
5528
5529 unsigned SrcEltSizeInBits = CstTy->getScalarSizeInBits();
5530 unsigned NumSrcElts = CstTy->getVectorNumElements();
5531
5532 APInt UndefSrcElts(NumSrcElts, 0);
5533 SmallVector<APInt, 64> SrcEltBits(NumSrcElts, APInt(SrcEltSizeInBits, 0));
5534 for (unsigned i = 0; i != NumSrcElts; ++i)
5535 if (!CollectConstantBits(Cst->getAggregateElement(i), SrcEltBits[i],
5536 UndefSrcElts, i))
5537 return false;
5538
5539 return CastBitData(UndefSrcElts, SrcEltBits);
5540 }
5541
5542 // Extract constant bits from a broadcasted constant pool scalar.
5543 if (Op.getOpcode() == X86ISD::VBROADCAST &&
5544 EltSizeInBits <= VT.getScalarSizeInBits()) {
5545 if (auto *Broadcast = getTargetConstantFromNode(Op.getOperand(0))) {
5546 unsigned SrcEltSizeInBits = Broadcast->getType()->getScalarSizeInBits();
5547 unsigned NumSrcElts = SizeInBits / SrcEltSizeInBits;
5548
5549 APInt UndefSrcElts(NumSrcElts, 0);
5550 SmallVector<APInt, 64> SrcEltBits(1, APInt(SrcEltSizeInBits, 0));
5551 if (CollectConstantBits(Broadcast, SrcEltBits[0], UndefSrcElts, 0)) {
5552 if (UndefSrcElts[0])
5553 UndefSrcElts.setBits(0, NumSrcElts);
5554 SrcEltBits.append(NumSrcElts - 1, SrcEltBits[0]);
5555 return CastBitData(UndefSrcElts, SrcEltBits);
5556 }
5557 }
5558 }
5559
5560 // Extract a rematerialized scalar constant insertion.
5561 if (Op.getOpcode() == X86ISD::VZEXT_MOVL &&
5562 Op.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
5563 isa<ConstantSDNode>(Op.getOperand(0).getOperand(0))) {
5564 unsigned SrcEltSizeInBits = VT.getScalarSizeInBits();
5565 unsigned NumSrcElts = SizeInBits / SrcEltSizeInBits;
5566
5567 APInt UndefSrcElts(NumSrcElts, 0);
5568 SmallVector<APInt, 64> SrcEltBits;
5569 auto *CN = cast<ConstantSDNode>(Op.getOperand(0).getOperand(0));
5570 SrcEltBits.push_back(CN->getAPIntValue().zextOrTrunc(SrcEltSizeInBits));
5571 SrcEltBits.append(NumSrcElts - 1, APInt(SrcEltSizeInBits, 0));
5572 return CastBitData(UndefSrcElts, SrcEltBits);
5573 }
5574
5575 return false;
5576}
5577
5578static bool getTargetShuffleMaskIndices(SDValue MaskNode,
5579 unsigned MaskEltSizeInBits,
5580 SmallVectorImpl<uint64_t> &RawMask) {
5581 APInt UndefElts;
5582 SmallVector<APInt, 64> EltBits;
5583
5584 // Extract the raw target constant bits.
5585 // FIXME: We currently don't support UNDEF bits or mask entries.
5586 if (!getTargetConstantBitsFromNode(MaskNode, MaskEltSizeInBits, UndefElts,
5587 EltBits, /* AllowWholeUndefs */ false,
5588 /* AllowPartialUndefs */ false))
5589 return false;
5590
5591 // Insert the extracted elements into the mask.
5592 for (APInt Elt : EltBits)
5593 RawMask.push_back(Elt.getZExtValue());
5594
5595 return true;
5596}
5597
5598/// Create a shuffle mask that matches the PACKSS/PACKUS truncation.
5599/// Note: This ignores saturation, so inputs must be checked first.
5600static void createPackShuffleMask(MVT VT, SmallVectorImpl<int> &Mask,
5601 bool Unary) {
5602 assert(Mask.empty() && "Expected an empty shuffle mask vector")(static_cast <bool> (Mask.empty() && "Expected an empty shuffle mask vector"
) ? void (0) : __assert_fail ("Mask.empty() && \"Expected an empty shuffle mask vector\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 5602, __extension__ __PRETTY_FUNCTION__))
;
5603 unsigned NumElts = VT.getVectorNumElements();
5604 unsigned NumLanes = VT.getSizeInBits() / 128;
5605 unsigned NumEltsPerLane = 128 / VT.getScalarSizeInBits();
5606 unsigned Offset = Unary ? 0 : NumElts;
5607
5608 for (unsigned Lane = 0; Lane != NumLanes; ++Lane) {
5609 for (unsigned Elt = 0; Elt != NumEltsPerLane; Elt += 2)
5610 Mask.push_back(Elt + (Lane * NumEltsPerLane));
5611 for (unsigned Elt = 0; Elt != NumEltsPerLane; Elt += 2)
5612 Mask.push_back(Elt + (Lane * NumEltsPerLane) + Offset);
5613 }
5614}
5615
5616/// Calculates the shuffle mask corresponding to the target-specific opcode.
5617/// If the mask could be calculated, returns it in \p Mask, returns the shuffle
5618/// operands in \p Ops, and returns true.
5619/// Sets \p IsUnary to true if only one source is used. Note that this will set
5620/// IsUnary for shuffles which use a single input multiple times, and in those
5621/// cases it will adjust the mask to only have indices within that single input.
5622/// It is an error to call this with non-empty Mask/Ops vectors.
5623static bool getTargetShuffleMask(SDNode *N, MVT VT, bool AllowSentinelZero,
5624 SmallVectorImpl<SDValue> &Ops,
5625 SmallVectorImpl<int> &Mask, bool &IsUnary) {
5626 unsigned NumElems = VT.getVectorNumElements();
5627 SDValue ImmN;
5628
5629 assert(Mask.empty() && "getTargetShuffleMask expects an empty Mask vector")(static_cast <bool> (Mask.empty() && "getTargetShuffleMask expects an empty Mask vector"
) ? void (0) : __assert_fail ("Mask.empty() && \"getTargetShuffleMask expects an empty Mask vector\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 5629, __extension__ __PRETTY_FUNCTION__))
;
5630 assert(Ops.empty() && "getTargetShuffleMask expects an empty Ops vector")(static_cast <bool> (Ops.empty() && "getTargetShuffleMask expects an empty Ops vector"
) ? void (0) : __assert_fail ("Ops.empty() && \"getTargetShuffleMask expects an empty Ops vector\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 5630, __extension__ __PRETTY_FUNCTION__))
;
5631
5632 IsUnary = false;
5633 bool IsFakeUnary = false;
5634 switch(N->getOpcode()) {
5635 case X86ISD::BLENDI:
5636 assert(N->getOperand(0).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(0).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(0).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 5636, __extension__ __PRETTY_FUNCTION__))
;
5637 assert(N->getOperand(1).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(1).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(1).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 5637, __extension__ __PRETTY_FUNCTION__))
;
5638 ImmN = N->getOperand(N->getNumOperands()-1);
5639 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5640 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5641 break;
5642 case X86ISD::SHUFP:
5643 assert(N->getOperand(0).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(0).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(0).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 5643, __extension__ __PRETTY_FUNCTION__))
;
5644 assert(N->getOperand(1).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(1).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(1).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 5644, __extension__ __PRETTY_FUNCTION__))
;
5645 ImmN = N->getOperand(N->getNumOperands()-1);
5646 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5647 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5648 break;
5649 case X86ISD::INSERTPS:
5650 assert(N->getOperand(0).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(0).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(0).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 5650, __extension__ __PRETTY_FUNCTION__))
;
5651 assert(N->getOperand(1).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(1).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(1).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 5651, __extension__ __PRETTY_FUNCTION__))
;
5652 ImmN = N->getOperand(N->getNumOperands()-1);
5653 DecodeINSERTPSMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5654 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5655 break;
5656 case X86ISD::EXTRQI:
5657 assert(N->getOperand(0).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(0).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(0).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 5657, __extension__ __PRETTY_FUNCTION__))
;
5658 if (isa<ConstantSDNode>(N->getOperand(1)) &&
5659 isa<ConstantSDNode>(N->getOperand(2))) {
5660 int BitLen = N->getConstantOperandVal(1);
5661 int BitIdx = N->getConstantOperandVal(2);
5662 DecodeEXTRQIMask(VT, BitLen, BitIdx, Mask);
5663 IsUnary = true;
5664 }
5665 break;
5666 case X86ISD::INSERTQI:
5667 assert(N->getOperand(0).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(0).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(0).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 5667, __extension__ __PRETTY_FUNCTION__))
;
5668 assert(N->getOperand(1).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(1).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(1).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 5668, __extension__ __PRETTY_FUNCTION__))
;
5669 if (isa<ConstantSDNode>(N->getOperand(2)) &&
5670 isa<ConstantSDNode>(N->getOperand(3))) {
5671 int BitLen = N->getConstantOperandVal(2);
5672 int BitIdx = N->getConstantOperandVal(3);
5673 DecodeINSERTQIMask(VT, BitLen, BitIdx, Mask);
5674 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5675 }
5676 break;
5677 case X86ISD::UNPCKH:
5678 assert(N->getOperand(0).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(0).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(0).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 5678, __extension__ __PRETTY_FUNCTION__))
;
5679 assert(N->getOperand(1).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(1).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(1).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 5679, __extension__ __PRETTY_FUNCTION__))
;
5680 DecodeUNPCKHMask(VT, Mask);
5681 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5682 break;
5683 case X86ISD::UNPCKL:
5684 assert(N->getOperand(0).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(0).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(0).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 5684, __extension__ __PRETTY_FUNCTION__))
;
5685 assert(N->getOperand(1).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(1).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(1).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 5685, __extension__ __PRETTY_FUNCTION__))
;
5686 DecodeUNPCKLMask(VT, Mask);
5687 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5688 break;
5689 case X86ISD::MOVHLPS:
5690 assert(N->getOperand(0).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(0).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(0).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 5690, __extension__ __PRETTY_FUNCTION__))
;
5691 assert(N->getOperand(1).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(1).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(1).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 5691, __extension__ __PRETTY_FUNCTION__))
;
5692 DecodeMOVHLPSMask(NumElems, Mask);
5693 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5694 break;
5695 case X86ISD::MOVLHPS:
5696 assert(N->getOperand(0).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(0).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(0).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 5696, __extension__ __PRETTY_FUNCTION__))
;
5697 assert(N->getOperand(1).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(1).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(1).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 5697, __extension__ __PRETTY_FUNCTION__))
;
5698 DecodeMOVLHPSMask(NumElems, Mask);
5699 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5700 break;
5701 case X86ISD::PALIGNR:
5702 assert(VT.getScalarType() == MVT::i8 && "Byte vector expected")(static_cast <bool> (VT.getScalarType() == MVT::i8 &&
"Byte vector expected") ? void (0) : __assert_fail ("VT.getScalarType() == MVT::i8 && \"Byte vector expected\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 5702, __extension__ __PRETTY_FUNCTION__))
;
5703 assert(N->getOperand(0).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(0).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(0).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 5703, __extension__ __PRETTY_FUNCTION__))
;
5704 assert(N->getOperand(1).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(1).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(1).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 5704, __extension__ __PRETTY_FUNCTION__))
;
5705 ImmN = N->getOperand(N->getNumOperands()-1);
5706 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5707 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5708 Ops.push_back(N->getOperand(1));
5709 Ops.push_back(N->getOperand(0));
5710 break;
5711 case X86ISD::VSHLDQ:
5712 assert(VT.getScalarType() == MVT::i8 && "Byte vector expected")(static_cast <bool> (VT.getScalarType() == MVT::i8 &&
"Byte vector expected") ? void (0) : __assert_fail ("VT.getScalarType() == MVT::i8 && \"Byte vector expected\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 5712, __extension__ __PRETTY_FUNCTION__))
;
5713 assert(N->getOperand(0).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(0).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(0).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 5713, __extension__ __PRETTY_FUNCTION__))
;
5714 ImmN = N->getOperand(N->getNumOperands() - 1);
5715 DecodePSLLDQMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5716 IsUnary = true;
5717 break;
5718 case X86ISD::VSRLDQ:
5719 assert(VT.getScalarType() == MVT::i8 && "Byte vector expected")(static_cast <bool> (VT.getScalarType() == MVT::i8 &&
"Byte vector expected") ? void (0) : __assert_fail ("VT.getScalarType() == MVT::i8 && \"Byte vector expected\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 5719, __extension__ __PRETTY_FUNCTION__))
;
5720 assert(N->getOperand(0).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(0).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(0).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 5720, __extension__ __PRETTY_FUNCTION__))
;
5721 ImmN = N->getOperand(N->getNumOperands() - 1);
5722 DecodePSRLDQMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5723 IsUnary = true;
5724 break;
5725 case X86ISD::PSHUFD:
5726 case X86ISD::VPERMILPI:
5727 assert(N->getOperand(0).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(0).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(0).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 5727, __extension__ __PRETTY_FUNCTION__))
;
5728 ImmN = N->getOperand(N->getNumOperands()-1);
5729 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5730 IsUnary = true;
5731 break;
5732 case X86ISD::PSHUFHW:
5733 assert(N->getOperand(0).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(0).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(0).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 5733, __extension__ __PRETTY_FUNCTION__))
;
5734 ImmN = N->getOperand(N->getNumOperands()-1);
5735 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5736 IsUnary = true;
5737 break;
5738 case X86ISD::PSHUFLW:
5739 assert(N->getOperand(0).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(0).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(0).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 5739, __extension__ __PRETTY_FUNCTION__))
;
5740 ImmN = N->getOperand(N->getNumOperands()-1);
5741 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5742 IsUnary = true;
5743 break;
5744 case X86ISD::VZEXT_MOVL:
5745 assert(N->getOperand(0).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(0).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(0).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 5745, __extension__ __PRETTY_FUNCTION__))
;
5746 DecodeZeroMoveLowMask(VT, Mask);
5747 IsUnary = true;
5748 break;
5749 case X86ISD::VBROADCAST: {
5750 SDValue N0 = N->getOperand(0);
5751 // See if we're broadcasting from index 0 of an EXTRACT_SUBVECTOR. If so,
5752 // add the pre-extracted value to the Ops vector.
5753 if (N0.getOpcode() == ISD::EXTRACT_SUBVECTOR &&
5754 N0.getOperand(0).getValueType() == VT &&
5755 N0.getConstantOperandVal(1) == 0)
5756 Ops.push_back(N0.getOperand(0));
5757
5758 // We only decode broadcasts of same-sized vectors, unless the broadcast
5759 // came from an extract from the original width. If we found one, we
5760 // pushed it the Ops vector above.
5761 if (N0.getValueType() == VT || !Ops.empty()) {
5762 DecodeVectorBroadcast(VT, Mask);
5763 IsUnary = true;
5764 break;
5765 }
5766 return false;
5767 }
5768 case X86ISD::VPERMILPV: {
5769 assert(N->getOperand(0).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(0).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(0).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 5769, __extension__ __PRETTY_FUNCTION__))
;
5770 IsUnary = true;
5771 SDValue MaskNode = N->getOperand(1);
5772 unsigned MaskEltSize = VT.getScalarSizeInBits();
5773 SmallVector<uint64_t, 32> RawMask;
5774 if (getTargetShuffleMaskIndices(MaskNode, MaskEltSize, RawMask)) {
5775 DecodeVPERMILPMask(VT, RawMask, Mask);
5776 break;
5777 }
5778 if (auto *C = getTargetConstantFromNode(MaskNode)) {
5779 DecodeVPERMILPMask(C, MaskEltSize, Mask);
5780 break;
5781 }
5782 return false;
5783 }
5784 case X86ISD::PSHUFB: {
5785 assert(VT.getScalarType() == MVT::i8 && "Byte vector expected")(static_cast <bool> (VT.getScalarType() == MVT::i8 &&
"Byte vector expected") ? void (0) : __assert_fail ("VT.getScalarType() == MVT::i8 && \"Byte vector expected\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 5785, __extension__ __PRETTY_FUNCTION__))
;
5786 assert(N->getOperand(0).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(0).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(0).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 5786, __extension__ __PRETTY_FUNCTION__))
;
5787 assert(N->getOperand(1).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(1).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(1).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 5787, __extension__ __PRETTY_FUNCTION__))
;
5788 IsUnary = true;
5789 SDValue MaskNode = N->getOperand(1);
5790 SmallVector<uint64_t, 32> RawMask;
5791 if (getTargetShuffleMaskIndices(MaskNode, 8, RawMask)) {
5792 DecodePSHUFBMask(RawMask, Mask);
5793 break;
5794 }
5795 if (auto *C = getTargetConstantFromNode(MaskNode)) {
5796 DecodePSHUFBMask(C, Mask);
5797 break;
5798 }
5799 return false;
5800 }
5801 case X86ISD::VPERMI:
5802 assert(N->getOperand(0).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(0).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(0).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 5802, __extension__ __PRETTY_FUNCTION__))
;
5803 ImmN = N->getOperand(N->getNumOperands()-1);
5804 DecodeVPERMMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5805 IsUnary = true;
5806 break;
5807 case X86ISD::MOVSS:
5808 case X86ISD::MOVSD:
5809 assert(N->getOperand(0).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(0).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(0).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 5809, __extension__ __PRETTY_FUNCTION__))
;
5810 assert(N->getOperand(1).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(1).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(1).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 5810, __extension__ __PRETTY_FUNCTION__))
;
5811 DecodeScalarMoveMask(VT, /* IsLoad */ false, Mask);
5812 break;
5813 case X86ISD::VPERM2X128:
5814 assert(N->getOperand(0).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(0).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(0).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 5814, __extension__ __PRETTY_FUNCTION__))
;
5815 assert(N->getOperand(1).getValueType() == VT && "Unexpected value type")(static_cast <bool> (N->getOperand(1).getValueType()
== VT && "Unexpected value type") ? void (0) : __assert_fail
("N->getOperand(1).getValueType() == VT && \"Unexpected value type\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/X86/X86ISelLowering.cpp"
, 5815, __extension__ __PRETTY_FUNCTION__))
;
5816 ImmN = N->getOperand(N->getNumOperands()-1);
5817 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5818 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5819 break;
5820 case X86ISD::MOVSLDUP: