Bug Summary

File:lib/Target/X86/X86InstrInfo.cpp
Warning:line 5400, column 14
Value stored to 'CommutableOpIdx1' during its initialization is never read

Annotated Source Code

1//===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the X86 implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "X86InstrInfo.h"
15#include "X86.h"
16#include "X86InstrBuilder.h"
17#include "X86MachineFunctionInfo.h"
18#include "X86Subtarget.h"
19#include "X86TargetMachine.h"
20#include "llvm/ADT/STLExtras.h"
21#include "llvm/CodeGen/LivePhysRegs.h"
22#include "llvm/CodeGen/LiveVariables.h"
23#include "llvm/CodeGen/MachineConstantPool.h"
24#include "llvm/CodeGen/MachineDominators.h"
25#include "llvm/CodeGen/MachineFrameInfo.h"
26#include "llvm/CodeGen/MachineInstrBuilder.h"
27#include "llvm/CodeGen/MachineModuleInfo.h"
28#include "llvm/CodeGen/MachineRegisterInfo.h"
29#include "llvm/CodeGen/StackMaps.h"
30#include "llvm/IR/DerivedTypes.h"
31#include "llvm/IR/Function.h"
32#include "llvm/IR/LLVMContext.h"
33#include "llvm/MC/MCAsmInfo.h"
34#include "llvm/MC/MCExpr.h"
35#include "llvm/MC/MCInst.h"
36#include "llvm/Support/CommandLine.h"
37#include "llvm/Support/Debug.h"
38#include "llvm/Support/ErrorHandling.h"
39#include "llvm/Support/raw_ostream.h"
40#include "llvm/Target/TargetOptions.h"
41
42using namespace llvm;
43
44#define DEBUG_TYPE"x86-instr-info" "x86-instr-info"
45
46#define GET_INSTRINFO_CTOR_DTOR
47#include "X86GenInstrInfo.inc"
48
49static cl::opt<bool>
50NoFusing("disable-spill-fusing",
51 cl::desc("Disable fusing of spill code into instructions"));
52static cl::opt<bool>
53PrintFailedFusing("print-failed-fuse-candidates",
54 cl::desc("Print instructions that the allocator wants to"
55 " fuse, but the X86 backend currently can't"),
56 cl::Hidden);
57static cl::opt<bool>
58ReMatPICStubLoad("remat-pic-stub-load",
59 cl::desc("Re-materialize load from stub in PIC mode"),
60 cl::init(false), cl::Hidden);
61static cl::opt<unsigned>
62PartialRegUpdateClearance("partial-reg-update-clearance",
63 cl::desc("Clearance between two register writes "
64 "for inserting XOR to avoid partial "
65 "register update"),
66 cl::init(64), cl::Hidden);
67static cl::opt<unsigned>
68UndefRegClearance("undef-reg-clearance",
69 cl::desc("How many idle instructions we would like before "
70 "certain undef register reads"),
71 cl::init(128), cl::Hidden);
72
73enum {
74 // Select which memory operand is being unfolded.
75 // (stored in bits 0 - 3)
76 TB_INDEX_0 = 0,
77 TB_INDEX_1 = 1,
78 TB_INDEX_2 = 2,
79 TB_INDEX_3 = 3,
80 TB_INDEX_4 = 4,
81 TB_INDEX_MASK = 0xf,
82
83 // Do not insert the reverse map (MemOp -> RegOp) into the table.
84 // This may be needed because there is a many -> one mapping.
85 TB_NO_REVERSE = 1 << 4,
86
87 // Do not insert the forward map (RegOp -> MemOp) into the table.
88 // This is needed for Native Client, which prohibits branch
89 // instructions from using a memory operand.
90 TB_NO_FORWARD = 1 << 5,
91
92 TB_FOLDED_LOAD = 1 << 6,
93 TB_FOLDED_STORE = 1 << 7,
94
95 // Minimum alignment required for load/store.
96 // Used for RegOp->MemOp conversion.
97 // (stored in bits 8 - 15)
98 TB_ALIGN_SHIFT = 8,
99 TB_ALIGN_NONE = 0 << TB_ALIGN_SHIFT,
100 TB_ALIGN_16 = 16 << TB_ALIGN_SHIFT,
101 TB_ALIGN_32 = 32 << TB_ALIGN_SHIFT,
102 TB_ALIGN_64 = 64 << TB_ALIGN_SHIFT,
103 TB_ALIGN_MASK = 0xff << TB_ALIGN_SHIFT
104};
105
106struct X86MemoryFoldTableEntry {
107 uint16_t RegOp;
108 uint16_t MemOp;
109 uint16_t Flags;
110};
111
112// Pin the vtable to this file.
113void X86InstrInfo::anchor() {}
114
115X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
116 : X86GenInstrInfo((STI.isTarget64BitLP64() ? X86::ADJCALLSTACKDOWN64
117 : X86::ADJCALLSTACKDOWN32),
118 (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64
119 : X86::ADJCALLSTACKUP32),
120 X86::CATCHRET,
121 (STI.is64Bit() ? X86::RETQ : X86::RETL)),
122 Subtarget(STI), RI(STI.getTargetTriple()) {
123
124 static const X86MemoryFoldTableEntry MemoryFoldTable2Addr[] = {
125 { X86::ADC32ri, X86::ADC32mi, 0 },
126 { X86::ADC32ri8, X86::ADC32mi8, 0 },
127 { X86::ADC32rr, X86::ADC32mr, 0 },
128 { X86::ADC64ri32, X86::ADC64mi32, 0 },
129 { X86::ADC64ri8, X86::ADC64mi8, 0 },
130 { X86::ADC64rr, X86::ADC64mr, 0 },
131 { X86::ADD16ri, X86::ADD16mi, 0 },
132 { X86::ADD16ri8, X86::ADD16mi8, 0 },
133 { X86::ADD16ri_DB, X86::ADD16mi, TB_NO_REVERSE },
134 { X86::ADD16ri8_DB, X86::ADD16mi8, TB_NO_REVERSE },
135 { X86::ADD16rr, X86::ADD16mr, 0 },
136 { X86::ADD16rr_DB, X86::ADD16mr, TB_NO_REVERSE },
137 { X86::ADD32ri, X86::ADD32mi, 0 },
138 { X86::ADD32ri8, X86::ADD32mi8, 0 },
139 { X86::ADD32ri_DB, X86::ADD32mi, TB_NO_REVERSE },
140 { X86::ADD32ri8_DB, X86::ADD32mi8, TB_NO_REVERSE },
141 { X86::ADD32rr, X86::ADD32mr, 0 },
142 { X86::ADD32rr_DB, X86::ADD32mr, TB_NO_REVERSE },
143 { X86::ADD64ri32, X86::ADD64mi32, 0 },
144 { X86::ADD64ri8, X86::ADD64mi8, 0 },
145 { X86::ADD64ri32_DB,X86::ADD64mi32, TB_NO_REVERSE },
146 { X86::ADD64ri8_DB, X86::ADD64mi8, TB_NO_REVERSE },
147 { X86::ADD64rr, X86::ADD64mr, 0 },
148 { X86::ADD64rr_DB, X86::ADD64mr, TB_NO_REVERSE },
149 { X86::ADD8ri, X86::ADD8mi, 0 },
150 { X86::ADD8rr, X86::ADD8mr, 0 },
151 { X86::AND16ri, X86::AND16mi, 0 },
152 { X86::AND16ri8, X86::AND16mi8, 0 },
153 { X86::AND16rr, X86::AND16mr, 0 },
154 { X86::AND32ri, X86::AND32mi, 0 },
155 { X86::AND32ri8, X86::AND32mi8, 0 },
156 { X86::AND32rr, X86::AND32mr, 0 },
157 { X86::AND64ri32, X86::AND64mi32, 0 },
158 { X86::AND64ri8, X86::AND64mi8, 0 },
159 { X86::AND64rr, X86::AND64mr, 0 },
160 { X86::AND8ri, X86::AND8mi, 0 },
161 { X86::AND8rr, X86::AND8mr, 0 },
162 { X86::DEC16r, X86::DEC16m, 0 },
163 { X86::DEC32r, X86::DEC32m, 0 },
164 { X86::DEC64r, X86::DEC64m, 0 },
165 { X86::DEC8r, X86::DEC8m, 0 },
166 { X86::INC16r, X86::INC16m, 0 },
167 { X86::INC32r, X86::INC32m, 0 },
168 { X86::INC64r, X86::INC64m, 0 },
169 { X86::INC8r, X86::INC8m, 0 },
170 { X86::NEG16r, X86::NEG16m, 0 },
171 { X86::NEG32r, X86::NEG32m, 0 },
172 { X86::NEG64r, X86::NEG64m, 0 },
173 { X86::NEG8r, X86::NEG8m, 0 },
174 { X86::NOT16r, X86::NOT16m, 0 },
175 { X86::NOT32r, X86::NOT32m, 0 },
176 { X86::NOT64r, X86::NOT64m, 0 },
177 { X86::NOT8r, X86::NOT8m, 0 },
178 { X86::OR16ri, X86::OR16mi, 0 },
179 { X86::OR16ri8, X86::OR16mi8, 0 },
180 { X86::OR16rr, X86::OR16mr, 0 },
181 { X86::OR32ri, X86::OR32mi, 0 },
182 { X86::OR32ri8, X86::OR32mi8, 0 },
183 { X86::OR32rr, X86::OR32mr, 0 },
184 { X86::OR64ri32, X86::OR64mi32, 0 },
185 { X86::OR64ri8, X86::OR64mi8, 0 },
186 { X86::OR64rr, X86::OR64mr, 0 },
187 { X86::OR8ri, X86::OR8mi, 0 },
188 { X86::OR8rr, X86::OR8mr, 0 },
189 { X86::ROL16r1, X86::ROL16m1, 0 },
190 { X86::ROL16rCL, X86::ROL16mCL, 0 },
191 { X86::ROL16ri, X86::ROL16mi, 0 },
192 { X86::ROL32r1, X86::ROL32m1, 0 },
193 { X86::ROL32rCL, X86::ROL32mCL, 0 },
194 { X86::ROL32ri, X86::ROL32mi, 0 },
195 { X86::ROL64r1, X86::ROL64m1, 0 },
196 { X86::ROL64rCL, X86::ROL64mCL, 0 },
197 { X86::ROL64ri, X86::ROL64mi, 0 },
198 { X86::ROL8r1, X86::ROL8m1, 0 },
199 { X86::ROL8rCL, X86::ROL8mCL, 0 },
200 { X86::ROL8ri, X86::ROL8mi, 0 },
201 { X86::ROR16r1, X86::ROR16m1, 0 },
202 { X86::ROR16rCL, X86::ROR16mCL, 0 },
203 { X86::ROR16ri, X86::ROR16mi, 0 },
204 { X86::ROR32r1, X86::ROR32m1, 0 },
205 { X86::ROR32rCL, X86::ROR32mCL, 0 },
206 { X86::ROR32ri, X86::ROR32mi, 0 },
207 { X86::ROR64r1, X86::ROR64m1, 0 },
208 { X86::ROR64rCL, X86::ROR64mCL, 0 },
209 { X86::ROR64ri, X86::ROR64mi, 0 },
210 { X86::ROR8r1, X86::ROR8m1, 0 },
211 { X86::ROR8rCL, X86::ROR8mCL, 0 },
212 { X86::ROR8ri, X86::ROR8mi, 0 },
213 { X86::SAR16r1, X86::SAR16m1, 0 },
214 { X86::SAR16rCL, X86::SAR16mCL, 0 },
215 { X86::SAR16ri, X86::SAR16mi, 0 },
216 { X86::SAR32r1, X86::SAR32m1, 0 },
217 { X86::SAR32rCL, X86::SAR32mCL, 0 },
218 { X86::SAR32ri, X86::SAR32mi, 0 },
219 { X86::SAR64r1, X86::SAR64m1, 0 },
220 { X86::SAR64rCL, X86::SAR64mCL, 0 },
221 { X86::SAR64ri, X86::SAR64mi, 0 },
222 { X86::SAR8r1, X86::SAR8m1, 0 },
223 { X86::SAR8rCL, X86::SAR8mCL, 0 },
224 { X86::SAR8ri, X86::SAR8mi, 0 },
225 { X86::SBB32ri, X86::SBB32mi, 0 },
226 { X86::SBB32ri8, X86::SBB32mi8, 0 },
227 { X86::SBB32rr, X86::SBB32mr, 0 },
228 { X86::SBB64ri32, X86::SBB64mi32, 0 },
229 { X86::SBB64ri8, X86::SBB64mi8, 0 },
230 { X86::SBB64rr, X86::SBB64mr, 0 },
231 { X86::SHL16r1, X86::SHL16m1, 0 },
232 { X86::SHL16rCL, X86::SHL16mCL, 0 },
233 { X86::SHL16ri, X86::SHL16mi, 0 },
234 { X86::SHL32r1, X86::SHL32m1, 0 },
235 { X86::SHL32rCL, X86::SHL32mCL, 0 },
236 { X86::SHL32ri, X86::SHL32mi, 0 },
237 { X86::SHL64r1, X86::SHL64m1, 0 },
238 { X86::SHL64rCL, X86::SHL64mCL, 0 },
239 { X86::SHL64ri, X86::SHL64mi, 0 },
240 { X86::SHL8r1, X86::SHL8m1, 0 },
241 { X86::SHL8rCL, X86::SHL8mCL, 0 },
242 { X86::SHL8ri, X86::SHL8mi, 0 },
243 { X86::SHLD16rrCL, X86::SHLD16mrCL, 0 },
244 { X86::SHLD16rri8, X86::SHLD16mri8, 0 },
245 { X86::SHLD32rrCL, X86::SHLD32mrCL, 0 },
246 { X86::SHLD32rri8, X86::SHLD32mri8, 0 },
247 { X86::SHLD64rrCL, X86::SHLD64mrCL, 0 },
248 { X86::SHLD64rri8, X86::SHLD64mri8, 0 },
249 { X86::SHR16r1, X86::SHR16m1, 0 },
250 { X86::SHR16rCL, X86::SHR16mCL, 0 },
251 { X86::SHR16ri, X86::SHR16mi, 0 },
252 { X86::SHR32r1, X86::SHR32m1, 0 },
253 { X86::SHR32rCL, X86::SHR32mCL, 0 },
254 { X86::SHR32ri, X86::SHR32mi, 0 },
255 { X86::SHR64r1, X86::SHR64m1, 0 },
256 { X86::SHR64rCL, X86::SHR64mCL, 0 },
257 { X86::SHR64ri, X86::SHR64mi, 0 },
258 { X86::SHR8r1, X86::SHR8m1, 0 },
259 { X86::SHR8rCL, X86::SHR8mCL, 0 },
260 { X86::SHR8ri, X86::SHR8mi, 0 },
261 { X86::SHRD16rrCL, X86::SHRD16mrCL, 0 },
262 { X86::SHRD16rri8, X86::SHRD16mri8, 0 },
263 { X86::SHRD32rrCL, X86::SHRD32mrCL, 0 },
264 { X86::SHRD32rri8, X86::SHRD32mri8, 0 },
265 { X86::SHRD64rrCL, X86::SHRD64mrCL, 0 },
266 { X86::SHRD64rri8, X86::SHRD64mri8, 0 },
267 { X86::SUB16ri, X86::SUB16mi, 0 },
268 { X86::SUB16ri8, X86::SUB16mi8, 0 },
269 { X86::SUB16rr, X86::SUB16mr, 0 },
270 { X86::SUB32ri, X86::SUB32mi, 0 },
271 { X86::SUB32ri8, X86::SUB32mi8, 0 },
272 { X86::SUB32rr, X86::SUB32mr, 0 },
273 { X86::SUB64ri32, X86::SUB64mi32, 0 },
274 { X86::SUB64ri8, X86::SUB64mi8, 0 },
275 { X86::SUB64rr, X86::SUB64mr, 0 },
276 { X86::SUB8ri, X86::SUB8mi, 0 },
277 { X86::SUB8rr, X86::SUB8mr, 0 },
278 { X86::XOR16ri, X86::XOR16mi, 0 },
279 { X86::XOR16ri8, X86::XOR16mi8, 0 },
280 { X86::XOR16rr, X86::XOR16mr, 0 },
281 { X86::XOR32ri, X86::XOR32mi, 0 },
282 { X86::XOR32ri8, X86::XOR32mi8, 0 },
283 { X86::XOR32rr, X86::XOR32mr, 0 },
284 { X86::XOR64ri32, X86::XOR64mi32, 0 },
285 { X86::XOR64ri8, X86::XOR64mi8, 0 },
286 { X86::XOR64rr, X86::XOR64mr, 0 },
287 { X86::XOR8ri, X86::XOR8mi, 0 },
288 { X86::XOR8rr, X86::XOR8mr, 0 }
289 };
290
291 for (X86MemoryFoldTableEntry Entry : MemoryFoldTable2Addr) {
292 AddTableEntry(RegOp2MemOpTable2Addr, MemOp2RegOpTable,
293 Entry.RegOp, Entry.MemOp,
294 // Index 0, folded load and store, no alignment requirement.
295 Entry.Flags | TB_INDEX_0 | TB_FOLDED_LOAD | TB_FOLDED_STORE);
296 }
297
298 static const X86MemoryFoldTableEntry MemoryFoldTable0[] = {
299 { X86::BT16ri8, X86::BT16mi8, TB_FOLDED_LOAD },
300 { X86::BT32ri8, X86::BT32mi8, TB_FOLDED_LOAD },
301 { X86::BT64ri8, X86::BT64mi8, TB_FOLDED_LOAD },
302 { X86::CALL32r, X86::CALL32m, TB_FOLDED_LOAD },
303 { X86::CALL64r, X86::CALL64m, TB_FOLDED_LOAD },
304 { X86::CMP16ri, X86::CMP16mi, TB_FOLDED_LOAD },
305 { X86::CMP16ri8, X86::CMP16mi8, TB_FOLDED_LOAD },
306 { X86::CMP16rr, X86::CMP16mr, TB_FOLDED_LOAD },
307 { X86::CMP32ri, X86::CMP32mi, TB_FOLDED_LOAD },
308 { X86::CMP32ri8, X86::CMP32mi8, TB_FOLDED_LOAD },
309 { X86::CMP32rr, X86::CMP32mr, TB_FOLDED_LOAD },
310 { X86::CMP64ri32, X86::CMP64mi32, TB_FOLDED_LOAD },
311 { X86::CMP64ri8, X86::CMP64mi8, TB_FOLDED_LOAD },
312 { X86::CMP64rr, X86::CMP64mr, TB_FOLDED_LOAD },
313 { X86::CMP8ri, X86::CMP8mi, TB_FOLDED_LOAD },
314 { X86::CMP8rr, X86::CMP8mr, TB_FOLDED_LOAD },
315 { X86::DIV16r, X86::DIV16m, TB_FOLDED_LOAD },
316 { X86::DIV32r, X86::DIV32m, TB_FOLDED_LOAD },
317 { X86::DIV64r, X86::DIV64m, TB_FOLDED_LOAD },
318 { X86::DIV8r, X86::DIV8m, TB_FOLDED_LOAD },
319 { X86::EXTRACTPSrr, X86::EXTRACTPSmr, TB_FOLDED_STORE },
320 { X86::IDIV16r, X86::IDIV16m, TB_FOLDED_LOAD },
321 { X86::IDIV32r, X86::IDIV32m, TB_FOLDED_LOAD },
322 { X86::IDIV64r, X86::IDIV64m, TB_FOLDED_LOAD },
323 { X86::IDIV8r, X86::IDIV8m, TB_FOLDED_LOAD },
324 { X86::IMUL16r, X86::IMUL16m, TB_FOLDED_LOAD },
325 { X86::IMUL32r, X86::IMUL32m, TB_FOLDED_LOAD },
326 { X86::IMUL64r, X86::IMUL64m, TB_FOLDED_LOAD },
327 { X86::IMUL8r, X86::IMUL8m, TB_FOLDED_LOAD },
328 { X86::JMP32r, X86::JMP32m, TB_FOLDED_LOAD },
329 { X86::JMP64r, X86::JMP64m, TB_FOLDED_LOAD },
330 { X86::MOV16ri, X86::MOV16mi, TB_FOLDED_STORE },
331 { X86::MOV16rr, X86::MOV16mr, TB_FOLDED_STORE },
332 { X86::MOV32ri, X86::MOV32mi, TB_FOLDED_STORE },
333 { X86::MOV32rr, X86::MOV32mr, TB_FOLDED_STORE },
334 { X86::MOV64ri32, X86::MOV64mi32, TB_FOLDED_STORE },
335 { X86::MOV64rr, X86::MOV64mr, TB_FOLDED_STORE },
336 { X86::MOV8ri, X86::MOV8mi, TB_FOLDED_STORE },
337 { X86::MOV8rr, X86::MOV8mr, TB_FOLDED_STORE },
338 { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, TB_FOLDED_STORE },
339 { X86::MOVAPDrr, X86::MOVAPDmr, TB_FOLDED_STORE | TB_ALIGN_16 },
340 { X86::MOVAPSrr, X86::MOVAPSmr, TB_FOLDED_STORE | TB_ALIGN_16 },
341 { X86::MOVDQArr, X86::MOVDQAmr, TB_FOLDED_STORE | TB_ALIGN_16 },
342 { X86::MOVDQUrr, X86::MOVDQUmr, TB_FOLDED_STORE },
343 { X86::MOVPDI2DIrr, X86::MOVPDI2DImr, TB_FOLDED_STORE },
344 { X86::MOVPQIto64rr,X86::MOVPQI2QImr, TB_FOLDED_STORE },
345 { X86::MOVSDto64rr, X86::MOVSDto64mr, TB_FOLDED_STORE },
346 { X86::MOVSS2DIrr, X86::MOVSS2DImr, TB_FOLDED_STORE },
347 { X86::MOVUPDrr, X86::MOVUPDmr, TB_FOLDED_STORE },
348 { X86::MOVUPSrr, X86::MOVUPSmr, TB_FOLDED_STORE },
349 { X86::MUL16r, X86::MUL16m, TB_FOLDED_LOAD },
350 { X86::MUL32r, X86::MUL32m, TB_FOLDED_LOAD },
351 { X86::MUL64r, X86::MUL64m, TB_FOLDED_LOAD },
352 { X86::MUL8r, X86::MUL8m, TB_FOLDED_LOAD },
353 { X86::PEXTRDrr, X86::PEXTRDmr, TB_FOLDED_STORE },
354 { X86::PEXTRQrr, X86::PEXTRQmr, TB_FOLDED_STORE },
355 { X86::PUSH16r, X86::PUSH16rmm, TB_FOLDED_LOAD },
356 { X86::PUSH32r, X86::PUSH32rmm, TB_FOLDED_LOAD },
357 { X86::PUSH64r, X86::PUSH64rmm, TB_FOLDED_LOAD },
358 { X86::SETAEr, X86::SETAEm, TB_FOLDED_STORE },
359 { X86::SETAr, X86::SETAm, TB_FOLDED_STORE },
360 { X86::SETBEr, X86::SETBEm, TB_FOLDED_STORE },
361 { X86::SETBr, X86::SETBm, TB_FOLDED_STORE },
362 { X86::SETEr, X86::SETEm, TB_FOLDED_STORE },
363 { X86::SETGEr, X86::SETGEm, TB_FOLDED_STORE },
364 { X86::SETGr, X86::SETGm, TB_FOLDED_STORE },
365 { X86::SETLEr, X86::SETLEm, TB_FOLDED_STORE },
366 { X86::SETLr, X86::SETLm, TB_FOLDED_STORE },
367 { X86::SETNEr, X86::SETNEm, TB_FOLDED_STORE },
368 { X86::SETNOr, X86::SETNOm, TB_FOLDED_STORE },
369 { X86::SETNPr, X86::SETNPm, TB_FOLDED_STORE },
370 { X86::SETNSr, X86::SETNSm, TB_FOLDED_STORE },
371 { X86::SETOr, X86::SETOm, TB_FOLDED_STORE },
372 { X86::SETPr, X86::SETPm, TB_FOLDED_STORE },
373 { X86::SETSr, X86::SETSm, TB_FOLDED_STORE },
374 { X86::TAILJMPr, X86::TAILJMPm, TB_FOLDED_LOAD },
375 { X86::TAILJMPr64, X86::TAILJMPm64, TB_FOLDED_LOAD },
376 { X86::TAILJMPr64_REX, X86::TAILJMPm64_REX, TB_FOLDED_LOAD },
377 { X86::TEST16ri, X86::TEST16mi, TB_FOLDED_LOAD },
378 { X86::TEST32ri, X86::TEST32mi, TB_FOLDED_LOAD },
379 { X86::TEST64ri32, X86::TEST64mi32, TB_FOLDED_LOAD },
380 { X86::TEST8ri, X86::TEST8mi, TB_FOLDED_LOAD },
381
382 // AVX 128-bit versions of foldable instructions
383 { X86::VEXTRACTPSrr,X86::VEXTRACTPSmr, TB_FOLDED_STORE },
384 { X86::VEXTRACTF128rr, X86::VEXTRACTF128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
385 { X86::VMOVAPDrr, X86::VMOVAPDmr, TB_FOLDED_STORE | TB_ALIGN_16 },
386 { X86::VMOVAPSrr, X86::VMOVAPSmr, TB_FOLDED_STORE | TB_ALIGN_16 },
387 { X86::VMOVDQArr, X86::VMOVDQAmr, TB_FOLDED_STORE | TB_ALIGN_16 },
388 { X86::VMOVDQUrr, X86::VMOVDQUmr, TB_FOLDED_STORE },
389 { X86::VMOVPDI2DIrr,X86::VMOVPDI2DImr, TB_FOLDED_STORE },
390 { X86::VMOVPQIto64rr, X86::VMOVPQI2QImr,TB_FOLDED_STORE },
391 { X86::VMOVSDto64rr,X86::VMOVSDto64mr, TB_FOLDED_STORE },
392 { X86::VMOVSS2DIrr, X86::VMOVSS2DImr, TB_FOLDED_STORE },
393 { X86::VMOVUPDrr, X86::VMOVUPDmr, TB_FOLDED_STORE },
394 { X86::VMOVUPSrr, X86::VMOVUPSmr, TB_FOLDED_STORE },
395 { X86::VPEXTRDrr, X86::VPEXTRDmr, TB_FOLDED_STORE },
396 { X86::VPEXTRQrr, X86::VPEXTRQmr, TB_FOLDED_STORE },
397
398 // AVX 256-bit foldable instructions
399 { X86::VEXTRACTI128rr, X86::VEXTRACTI128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
400 { X86::VMOVAPDYrr, X86::VMOVAPDYmr, TB_FOLDED_STORE | TB_ALIGN_32 },
401 { X86::VMOVAPSYrr, X86::VMOVAPSYmr, TB_FOLDED_STORE | TB_ALIGN_32 },
402 { X86::VMOVDQAYrr, X86::VMOVDQAYmr, TB_FOLDED_STORE | TB_ALIGN_32 },
403 { X86::VMOVDQUYrr, X86::VMOVDQUYmr, TB_FOLDED_STORE },
404 { X86::VMOVUPDYrr, X86::VMOVUPDYmr, TB_FOLDED_STORE },
405 { X86::VMOVUPSYrr, X86::VMOVUPSYmr, TB_FOLDED_STORE },
406
407 // AVX-512 foldable instructions
408 { X86::VEXTRACTF32x4Zrr,X86::VEXTRACTF32x4Zmr, TB_FOLDED_STORE },
409 { X86::VEXTRACTF32x8Zrr,X86::VEXTRACTF32x8Zmr, TB_FOLDED_STORE },
410 { X86::VEXTRACTF64x2Zrr,X86::VEXTRACTF64x2Zmr, TB_FOLDED_STORE },
411 { X86::VEXTRACTF64x4Zrr,X86::VEXTRACTF64x4Zmr, TB_FOLDED_STORE },
412 { X86::VEXTRACTI32x4Zrr,X86::VEXTRACTI32x4Zmr, TB_FOLDED_STORE },
413 { X86::VEXTRACTI32x8Zrr,X86::VEXTRACTI32x8Zmr, TB_FOLDED_STORE },
414 { X86::VEXTRACTI64x2Zrr,X86::VEXTRACTI64x2Zmr, TB_FOLDED_STORE },
415 { X86::VEXTRACTI64x4Zrr,X86::VEXTRACTI64x4Zmr, TB_FOLDED_STORE },
416 { X86::VEXTRACTPSZrr, X86::VEXTRACTPSZmr, TB_FOLDED_STORE },
417 { X86::VMOVAPDZrr, X86::VMOVAPDZmr, TB_FOLDED_STORE | TB_ALIGN_64 },
418 { X86::VMOVAPSZrr, X86::VMOVAPSZmr, TB_FOLDED_STORE | TB_ALIGN_64 },
419 { X86::VMOVDQA32Zrr, X86::VMOVDQA32Zmr, TB_FOLDED_STORE | TB_ALIGN_64 },
420 { X86::VMOVDQA64Zrr, X86::VMOVDQA64Zmr, TB_FOLDED_STORE | TB_ALIGN_64 },
421 { X86::VMOVDQU8Zrr, X86::VMOVDQU8Zmr, TB_FOLDED_STORE },
422 { X86::VMOVDQU16Zrr, X86::VMOVDQU16Zmr, TB_FOLDED_STORE },
423 { X86::VMOVDQU32Zrr, X86::VMOVDQU32Zmr, TB_FOLDED_STORE },
424 { X86::VMOVDQU64Zrr, X86::VMOVDQU64Zmr, TB_FOLDED_STORE },
425 { X86::VMOVPDI2DIZrr, X86::VMOVPDI2DIZmr, TB_FOLDED_STORE },
426 { X86::VMOVPQIto64Zrr, X86::VMOVPQI2QIZmr, TB_FOLDED_STORE },
427 { X86::VMOVSDto64Zrr, X86::VMOVSDto64Zmr, TB_FOLDED_STORE },
428 { X86::VMOVSS2DIZrr, X86::VMOVSS2DIZmr, TB_FOLDED_STORE },
429 { X86::VMOVUPDZrr, X86::VMOVUPDZmr, TB_FOLDED_STORE },
430 { X86::VMOVUPSZrr, X86::VMOVUPSZmr, TB_FOLDED_STORE },
431 { X86::VPEXTRDZrr, X86::VPEXTRDZmr, TB_FOLDED_STORE },
432 { X86::VPEXTRQZrr, X86::VPEXTRQZmr, TB_FOLDED_STORE },
433 { X86::VPMOVDBZrr, X86::VPMOVDBZmr, TB_FOLDED_STORE },
434 { X86::VPMOVDWZrr, X86::VPMOVDWZmr, TB_FOLDED_STORE },
435 { X86::VPMOVQDZrr, X86::VPMOVQDZmr, TB_FOLDED_STORE },
436 { X86::VPMOVQWZrr, X86::VPMOVQWZmr, TB_FOLDED_STORE },
437 { X86::VPMOVWBZrr, X86::VPMOVWBZmr, TB_FOLDED_STORE },
438 { X86::VPMOVSDBZrr, X86::VPMOVSDBZmr, TB_FOLDED_STORE },
439 { X86::VPMOVSDWZrr, X86::VPMOVSDWZmr, TB_FOLDED_STORE },
440 { X86::VPMOVSQDZrr, X86::VPMOVSQDZmr, TB_FOLDED_STORE },
441 { X86::VPMOVSQWZrr, X86::VPMOVSQWZmr, TB_FOLDED_STORE },
442 { X86::VPMOVSWBZrr, X86::VPMOVSWBZmr, TB_FOLDED_STORE },
443 { X86::VPMOVUSDBZrr, X86::VPMOVUSDBZmr, TB_FOLDED_STORE },
444 { X86::VPMOVUSDWZrr, X86::VPMOVUSDWZmr, TB_FOLDED_STORE },
445 { X86::VPMOVUSQDZrr, X86::VPMOVUSQDZmr, TB_FOLDED_STORE },
446 { X86::VPMOVUSQWZrr, X86::VPMOVUSQWZmr, TB_FOLDED_STORE },
447 { X86::VPMOVUSWBZrr, X86::VPMOVUSWBZmr, TB_FOLDED_STORE },
448
449 // AVX-512 foldable instructions (256-bit versions)
450 { X86::VEXTRACTF32x4Z256rr,X86::VEXTRACTF32x4Z256mr, TB_FOLDED_STORE },
451 { X86::VEXTRACTF64x2Z256rr,X86::VEXTRACTF64x2Z256mr, TB_FOLDED_STORE },
452 { X86::VEXTRACTI32x4Z256rr,X86::VEXTRACTI32x4Z256mr, TB_FOLDED_STORE },
453 { X86::VEXTRACTI64x2Z256rr,X86::VEXTRACTI64x2Z256mr, TB_FOLDED_STORE },
454 { X86::VMOVAPDZ256rr, X86::VMOVAPDZ256mr, TB_FOLDED_STORE | TB_ALIGN_32 },
455 { X86::VMOVAPSZ256rr, X86::VMOVAPSZ256mr, TB_FOLDED_STORE | TB_ALIGN_32 },
456 { X86::VMOVDQA32Z256rr, X86::VMOVDQA32Z256mr, TB_FOLDED_STORE | TB_ALIGN_32 },
457 { X86::VMOVDQA64Z256rr, X86::VMOVDQA64Z256mr, TB_FOLDED_STORE | TB_ALIGN_32 },
458 { X86::VMOVUPDZ256rr, X86::VMOVUPDZ256mr, TB_FOLDED_STORE },
459 { X86::VMOVUPSZ256rr, X86::VMOVUPSZ256mr, TB_FOLDED_STORE },
460 { X86::VMOVDQU8Z256rr, X86::VMOVDQU8Z256mr, TB_FOLDED_STORE },
461 { X86::VMOVDQU16Z256rr, X86::VMOVDQU16Z256mr, TB_FOLDED_STORE },
462 { X86::VMOVDQU32Z256rr, X86::VMOVDQU32Z256mr, TB_FOLDED_STORE },
463 { X86::VMOVDQU64Z256rr, X86::VMOVDQU64Z256mr, TB_FOLDED_STORE },
464 { X86::VPMOVDWZ256rr, X86::VPMOVDWZ256mr, TB_FOLDED_STORE },
465 { X86::VPMOVQDZ256rr, X86::VPMOVQDZ256mr, TB_FOLDED_STORE },
466 { X86::VPMOVWBZ256rr, X86::VPMOVWBZ256mr, TB_FOLDED_STORE },
467 { X86::VPMOVSDWZ256rr, X86::VPMOVSDWZ256mr, TB_FOLDED_STORE },
468 { X86::VPMOVSQDZ256rr, X86::VPMOVSQDZ256mr, TB_FOLDED_STORE },
469 { X86::VPMOVSWBZ256rr, X86::VPMOVSWBZ256mr, TB_FOLDED_STORE },
470 { X86::VPMOVUSDWZ256rr, X86::VPMOVUSDWZ256mr, TB_FOLDED_STORE },
471 { X86::VPMOVUSQDZ256rr, X86::VPMOVUSQDZ256mr, TB_FOLDED_STORE },
472 { X86::VPMOVUSWBZ256rr, X86::VPMOVUSWBZ256mr, TB_FOLDED_STORE },
473
474 // AVX-512 foldable instructions (128-bit versions)
475 { X86::VMOVAPDZ128rr, X86::VMOVAPDZ128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
476 { X86::VMOVAPSZ128rr, X86::VMOVAPSZ128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
477 { X86::VMOVDQA32Z128rr, X86::VMOVDQA32Z128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
478 { X86::VMOVDQA64Z128rr, X86::VMOVDQA64Z128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
479 { X86::VMOVUPDZ128rr, X86::VMOVUPDZ128mr, TB_FOLDED_STORE },
480 { X86::VMOVUPSZ128rr, X86::VMOVUPSZ128mr, TB_FOLDED_STORE },
481 { X86::VMOVDQU8Z128rr, X86::VMOVDQU8Z128mr, TB_FOLDED_STORE },
482 { X86::VMOVDQU16Z128rr, X86::VMOVDQU16Z128mr, TB_FOLDED_STORE },
483 { X86::VMOVDQU32Z128rr, X86::VMOVDQU32Z128mr, TB_FOLDED_STORE },
484 { X86::VMOVDQU64Z128rr, X86::VMOVDQU64Z128mr, TB_FOLDED_STORE },
485
486 // F16C foldable instructions
487 { X86::VCVTPS2PHrr, X86::VCVTPS2PHmr, TB_FOLDED_STORE },
488 { X86::VCVTPS2PHYrr, X86::VCVTPS2PHYmr, TB_FOLDED_STORE }
489 };
490
491 for (X86MemoryFoldTableEntry Entry : MemoryFoldTable0) {
492 AddTableEntry(RegOp2MemOpTable0, MemOp2RegOpTable,
493 Entry.RegOp, Entry.MemOp, TB_INDEX_0 | Entry.Flags);
494 }
495
496 static const X86MemoryFoldTableEntry MemoryFoldTable1[] = {
497 { X86::BSF16rr, X86::BSF16rm, 0 },
498 { X86::BSF32rr, X86::BSF32rm, 0 },
499 { X86::BSF64rr, X86::BSF64rm, 0 },
500 { X86::BSR16rr, X86::BSR16rm, 0 },
501 { X86::BSR32rr, X86::BSR32rm, 0 },
502 { X86::BSR64rr, X86::BSR64rm, 0 },
503 { X86::CMP16rr, X86::CMP16rm, 0 },
504 { X86::CMP32rr, X86::CMP32rm, 0 },
505 { X86::CMP64rr, X86::CMP64rm, 0 },
506 { X86::CMP8rr, X86::CMP8rm, 0 },
507 { X86::CVTSD2SSrr, X86::CVTSD2SSrm, 0 },
508 { X86::CVTSI2SD64rr, X86::CVTSI2SD64rm, 0 },
509 { X86::CVTSI2SDrr, X86::CVTSI2SDrm, 0 },
510 { X86::CVTSI2SS64rr, X86::CVTSI2SS64rm, 0 },
511 { X86::CVTSI2SSrr, X86::CVTSI2SSrm, 0 },
512 { X86::CVTSS2SDrr, X86::CVTSS2SDrm, 0 },
513 { X86::CVTTSD2SI64rr, X86::CVTTSD2SI64rm, 0 },
514 { X86::CVTTSD2SIrr, X86::CVTTSD2SIrm, 0 },
515 { X86::CVTTSS2SI64rr, X86::CVTTSS2SI64rm, 0 },
516 { X86::CVTTSS2SIrr, X86::CVTTSS2SIrm, 0 },
517 { X86::IMUL16rri, X86::IMUL16rmi, 0 },
518 { X86::IMUL16rri8, X86::IMUL16rmi8, 0 },
519 { X86::IMUL32rri, X86::IMUL32rmi, 0 },
520 { X86::IMUL32rri8, X86::IMUL32rmi8, 0 },
521 { X86::IMUL64rri32, X86::IMUL64rmi32, 0 },
522 { X86::IMUL64rri8, X86::IMUL64rmi8, 0 },
523 { X86::Int_COMISDrr, X86::Int_COMISDrm, TB_NO_REVERSE },
524 { X86::Int_COMISSrr, X86::Int_COMISSrm, TB_NO_REVERSE },
525 { X86::CVTSD2SI64rr, X86::CVTSD2SI64rm, TB_NO_REVERSE },
526 { X86::CVTSD2SIrr, X86::CVTSD2SIrm, TB_NO_REVERSE },
527 { X86::CVTSS2SI64rr, X86::CVTSS2SI64rm, TB_NO_REVERSE },
528 { X86::CVTSS2SIrr, X86::CVTSS2SIrm, TB_NO_REVERSE },
529 { X86::CVTDQ2PDrr, X86::CVTDQ2PDrm, TB_NO_REVERSE },
530 { X86::CVTDQ2PSrr, X86::CVTDQ2PSrm, TB_ALIGN_16 },
531 { X86::CVTPD2DQrr, X86::CVTPD2DQrm, TB_ALIGN_16 },
532 { X86::CVTPD2PSrr, X86::CVTPD2PSrm, TB_ALIGN_16 },
533 { X86::CVTPS2DQrr, X86::CVTPS2DQrm, TB_ALIGN_16 },
534 { X86::CVTPS2PDrr, X86::CVTPS2PDrm, TB_NO_REVERSE },
535 { X86::CVTTPD2DQrr, X86::CVTTPD2DQrm, TB_ALIGN_16 },
536 { X86::CVTTPS2DQrr, X86::CVTTPS2DQrm, TB_ALIGN_16 },
537 { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm, TB_NO_REVERSE },
538 { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm, TB_NO_REVERSE },
539 { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm, TB_NO_REVERSE },
540 { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm, TB_NO_REVERSE },
541 { X86::Int_UCOMISDrr, X86::Int_UCOMISDrm, TB_NO_REVERSE },
542 { X86::Int_UCOMISSrr, X86::Int_UCOMISSrm, TB_NO_REVERSE },
543 { X86::MOV16rr, X86::MOV16rm, 0 },
544 { X86::MOV32rr, X86::MOV32rm, 0 },
545 { X86::MOV64rr, X86::MOV64rm, 0 },
546 { X86::MOV64toPQIrr, X86::MOVQI2PQIrm, 0 },
547 { X86::MOV64toSDrr, X86::MOV64toSDrm, 0 },
548 { X86::MOV8rr, X86::MOV8rm, 0 },
549 { X86::MOVAPDrr, X86::MOVAPDrm, TB_ALIGN_16 },
550 { X86::MOVAPSrr, X86::MOVAPSrm, TB_ALIGN_16 },
551 { X86::MOVDDUPrr, X86::MOVDDUPrm, TB_NO_REVERSE },
552 { X86::MOVDI2PDIrr, X86::MOVDI2PDIrm, 0 },
553 { X86::MOVDI2SSrr, X86::MOVDI2SSrm, 0 },
554 { X86::MOVDQArr, X86::MOVDQArm, TB_ALIGN_16 },
555 { X86::MOVDQUrr, X86::MOVDQUrm, 0 },
556 { X86::MOVSHDUPrr, X86::MOVSHDUPrm, TB_ALIGN_16 },
557 { X86::MOVSLDUPrr, X86::MOVSLDUPrm, TB_ALIGN_16 },
558 { X86::MOVSX16rr8, X86::MOVSX16rm8, 0 },
559 { X86::MOVSX32rr16, X86::MOVSX32rm16, 0 },
560 { X86::MOVSX32rr8, X86::MOVSX32rm8, 0 },
561 { X86::MOVSX64rr16, X86::MOVSX64rm16, 0 },
562 { X86::MOVSX64rr32, X86::MOVSX64rm32, 0 },
563 { X86::MOVSX64rr8, X86::MOVSX64rm8, 0 },
564 { X86::MOVUPDrr, X86::MOVUPDrm, 0 },
565 { X86::MOVUPSrr, X86::MOVUPSrm, 0 },
566 { X86::MOVZPQILo2PQIrr, X86::MOVQI2PQIrm, TB_NO_REVERSE },
567 { X86::MOVZX16rr8, X86::MOVZX16rm8, 0 },
568 { X86::MOVZX32rr16, X86::MOVZX32rm16, 0 },
569 { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8, 0 },
570 { X86::MOVZX32rr8, X86::MOVZX32rm8, 0 },
571 { X86::PABSBrr, X86::PABSBrm, TB_ALIGN_16 },
572 { X86::PABSDrr, X86::PABSDrm, TB_ALIGN_16 },
573 { X86::PABSWrr, X86::PABSWrm, TB_ALIGN_16 },
574 { X86::PCMPESTRIrr, X86::PCMPESTRIrm, TB_ALIGN_16 },
575 { X86::PCMPESTRM128rr, X86::PCMPESTRM128rm, TB_ALIGN_16 },
576 { X86::PCMPISTRIrr, X86::PCMPISTRIrm, TB_ALIGN_16 },
577 { X86::PCMPISTRM128rr, X86::PCMPISTRM128rm, TB_ALIGN_16 },
578 { X86::PHMINPOSUWrr128, X86::PHMINPOSUWrm128, TB_ALIGN_16 },
579 { X86::PMOVSXBDrr, X86::PMOVSXBDrm, TB_NO_REVERSE },
580 { X86::PMOVSXBQrr, X86::PMOVSXBQrm, TB_NO_REVERSE },
581 { X86::PMOVSXBWrr, X86::PMOVSXBWrm, TB_NO_REVERSE },
582 { X86::PMOVSXDQrr, X86::PMOVSXDQrm, TB_NO_REVERSE },
583 { X86::PMOVSXWDrr, X86::PMOVSXWDrm, TB_NO_REVERSE },
584 { X86::PMOVSXWQrr, X86::PMOVSXWQrm, TB_NO_REVERSE },
585 { X86::PMOVZXBDrr, X86::PMOVZXBDrm, TB_NO_REVERSE },
586 { X86::PMOVZXBQrr, X86::PMOVZXBQrm, TB_NO_REVERSE },
587 { X86::PMOVZXBWrr, X86::PMOVZXBWrm, TB_NO_REVERSE },
588 { X86::PMOVZXDQrr, X86::PMOVZXDQrm, TB_NO_REVERSE },
589 { X86::PMOVZXWDrr, X86::PMOVZXWDrm, TB_NO_REVERSE },
590 { X86::PMOVZXWQrr, X86::PMOVZXWQrm, TB_NO_REVERSE },
591 { X86::PSHUFDri, X86::PSHUFDmi, TB_ALIGN_16 },
592 { X86::PSHUFHWri, X86::PSHUFHWmi, TB_ALIGN_16 },
593 { X86::PSHUFLWri, X86::PSHUFLWmi, TB_ALIGN_16 },
594 { X86::PTESTrr, X86::PTESTrm, TB_ALIGN_16 },
595 { X86::RCPPSr, X86::RCPPSm, TB_ALIGN_16 },
596 { X86::RCPSSr, X86::RCPSSm, 0 },
597 { X86::RCPSSr_Int, X86::RCPSSm_Int, TB_NO_REVERSE },
598 { X86::ROUNDPDr, X86::ROUNDPDm, TB_ALIGN_16 },
599 { X86::ROUNDPSr, X86::ROUNDPSm, TB_ALIGN_16 },
600 { X86::ROUNDSDr, X86::ROUNDSDm, 0 },
601 { X86::ROUNDSSr, X86::ROUNDSSm, 0 },
602 { X86::RSQRTPSr, X86::RSQRTPSm, TB_ALIGN_16 },
603 { X86::RSQRTSSr, X86::RSQRTSSm, 0 },
604 { X86::RSQRTSSr_Int, X86::RSQRTSSm_Int, TB_NO_REVERSE },
605 { X86::SQRTPDr, X86::SQRTPDm, TB_ALIGN_16 },
606 { X86::SQRTPSr, X86::SQRTPSm, TB_ALIGN_16 },
607 { X86::SQRTSDr, X86::SQRTSDm, 0 },
608 { X86::SQRTSDr_Int, X86::SQRTSDm_Int, TB_NO_REVERSE },
609 { X86::SQRTSSr, X86::SQRTSSm, 0 },
610 { X86::SQRTSSr_Int, X86::SQRTSSm_Int, TB_NO_REVERSE },
611 { X86::TEST16rr, X86::TEST16rm, 0 },
612 { X86::TEST32rr, X86::TEST32rm, 0 },
613 { X86::TEST64rr, X86::TEST64rm, 0 },
614 { X86::TEST8rr, X86::TEST8rm, 0 },
615 // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
616 { X86::UCOMISDrr, X86::UCOMISDrm, 0 },
617 { X86::UCOMISSrr, X86::UCOMISSrm, 0 },
618
619 // MMX version of foldable instructions
620 { X86::MMX_CVTPD2PIirr, X86::MMX_CVTPD2PIirm, 0 },
621 { X86::MMX_CVTPI2PDirr, X86::MMX_CVTPI2PDirm, 0 },
622 { X86::MMX_CVTPS2PIirr, X86::MMX_CVTPS2PIirm, 0 },
623 { X86::MMX_CVTTPD2PIirr, X86::MMX_CVTTPD2PIirm, 0 },
624 { X86::MMX_CVTTPS2PIirr, X86::MMX_CVTTPS2PIirm, 0 },
625 { X86::MMX_MOVD64to64rr, X86::MMX_MOVQ64rm, 0 },
626 { X86::MMX_PABSBrr64, X86::MMX_PABSBrm64, 0 },
627 { X86::MMX_PABSDrr64, X86::MMX_PABSDrm64, 0 },
628 { X86::MMX_PABSWrr64, X86::MMX_PABSWrm64, 0 },
629 { X86::MMX_PSHUFWri, X86::MMX_PSHUFWmi, 0 },
630
631 // 3DNow! version of foldable instructions
632 { X86::PF2IDrr, X86::PF2IDrm, 0 },
633 { X86::PF2IWrr, X86::PF2IWrm, 0 },
634 { X86::PFRCPrr, X86::PFRCPrm, 0 },
635 { X86::PFRSQRTrr, X86::PFRSQRTrm, 0 },
636 { X86::PI2FDrr, X86::PI2FDrm, 0 },
637 { X86::PI2FWrr, X86::PI2FWrm, 0 },
638 { X86::PSWAPDrr, X86::PSWAPDrm, 0 },
639
640 // AVX 128-bit versions of foldable instructions
641 { X86::Int_VCOMISDrr, X86::Int_VCOMISDrm, TB_NO_REVERSE },
642 { X86::Int_VCOMISSrr, X86::Int_VCOMISSrm, TB_NO_REVERSE },
643 { X86::Int_VUCOMISDrr, X86::Int_VUCOMISDrm, TB_NO_REVERSE },
644 { X86::Int_VUCOMISSrr, X86::Int_VUCOMISSrm, TB_NO_REVERSE },
645 { X86::VCVTTSD2SI64rr, X86::VCVTTSD2SI64rm, 0 },
646 { X86::Int_VCVTTSD2SI64rr,X86::Int_VCVTTSD2SI64rm,TB_NO_REVERSE },
647 { X86::VCVTTSD2SIrr, X86::VCVTTSD2SIrm, 0 },
648 { X86::Int_VCVTTSD2SIrr,X86::Int_VCVTTSD2SIrm, TB_NO_REVERSE },
649 { X86::VCVTTSS2SI64rr, X86::VCVTTSS2SI64rm, 0 },
650 { X86::Int_VCVTTSS2SI64rr,X86::Int_VCVTTSS2SI64rm,TB_NO_REVERSE },
651 { X86::VCVTTSS2SIrr, X86::VCVTTSS2SIrm, 0 },
652 { X86::Int_VCVTTSS2SIrr,X86::Int_VCVTTSS2SIrm, TB_NO_REVERSE },
653 { X86::VCVTSD2SI64rr, X86::VCVTSD2SI64rm, TB_NO_REVERSE },
654 { X86::VCVTSD2SIrr, X86::VCVTSD2SIrm, TB_NO_REVERSE },
655 { X86::VCVTSS2SI64rr, X86::VCVTSS2SI64rm, TB_NO_REVERSE },
656 { X86::VCVTSS2SIrr, X86::VCVTSS2SIrm, TB_NO_REVERSE },
657 { X86::VCVTDQ2PDrr, X86::VCVTDQ2PDrm, TB_NO_REVERSE },
658 { X86::VCVTDQ2PSrr, X86::VCVTDQ2PSrm, 0 },
659 { X86::VCVTPD2DQrr, X86::VCVTPD2DQrm, 0 },
660 { X86::VCVTPD2PSrr, X86::VCVTPD2PSrm, 0 },
661 { X86::VCVTPS2DQrr, X86::VCVTPS2DQrm, 0 },
662 { X86::VCVTPS2PDrr, X86::VCVTPS2PDrm, TB_NO_REVERSE },
663 { X86::VCVTTPD2DQrr, X86::VCVTTPD2DQrm, 0 },
664 { X86::VCVTTPS2DQrr, X86::VCVTTPS2DQrm, 0 },
665 { X86::VMOV64toPQIrr, X86::VMOVQI2PQIrm, 0 },
666 { X86::VMOV64toSDrr, X86::VMOV64toSDrm, 0 },
667 { X86::VMOVAPDrr, X86::VMOVAPDrm, TB_ALIGN_16 },
668 { X86::VMOVAPSrr, X86::VMOVAPSrm, TB_ALIGN_16 },
669 { X86::VMOVDDUPrr, X86::VMOVDDUPrm, TB_NO_REVERSE },
670 { X86::VMOVDI2PDIrr, X86::VMOVDI2PDIrm, 0 },
671 { X86::VMOVDI2SSrr, X86::VMOVDI2SSrm, 0 },
672 { X86::VMOVDQArr, X86::VMOVDQArm, TB_ALIGN_16 },
673 { X86::VMOVDQUrr, X86::VMOVDQUrm, 0 },
674 { X86::VMOVSLDUPrr, X86::VMOVSLDUPrm, 0 },
675 { X86::VMOVSHDUPrr, X86::VMOVSHDUPrm, 0 },
676 { X86::VMOVUPDrr, X86::VMOVUPDrm, 0 },
677 { X86::VMOVUPSrr, X86::VMOVUPSrm, 0 },
678 { X86::VMOVZPQILo2PQIrr,X86::VMOVQI2PQIrm, TB_NO_REVERSE },
679 { X86::VPABSBrr, X86::VPABSBrm, 0 },
680 { X86::VPABSDrr, X86::VPABSDrm, 0 },
681 { X86::VPABSWrr, X86::VPABSWrm, 0 },
682 { X86::VPCMPESTRIrr, X86::VPCMPESTRIrm, 0 },
683 { X86::VPCMPESTRM128rr, X86::VPCMPESTRM128rm, 0 },
684 { X86::VPCMPISTRIrr, X86::VPCMPISTRIrm, 0 },
685 { X86::VPCMPISTRM128rr, X86::VPCMPISTRM128rm, 0 },
686 { X86::VPHMINPOSUWrr128, X86::VPHMINPOSUWrm128, 0 },
687 { X86::VPERMILPDri, X86::VPERMILPDmi, 0 },
688 { X86::VPERMILPSri, X86::VPERMILPSmi, 0 },
689 { X86::VPMOVSXBDrr, X86::VPMOVSXBDrm, TB_NO_REVERSE },
690 { X86::VPMOVSXBQrr, X86::VPMOVSXBQrm, TB_NO_REVERSE },
691 { X86::VPMOVSXBWrr, X86::VPMOVSXBWrm, TB_NO_REVERSE },
692 { X86::VPMOVSXDQrr, X86::VPMOVSXDQrm, TB_NO_REVERSE },
693 { X86::VPMOVSXWDrr, X86::VPMOVSXWDrm, TB_NO_REVERSE },
694 { X86::VPMOVSXWQrr, X86::VPMOVSXWQrm, TB_NO_REVERSE },
695 { X86::VPMOVZXBDrr, X86::VPMOVZXBDrm, TB_NO_REVERSE },
696 { X86::VPMOVZXBQrr, X86::VPMOVZXBQrm, TB_NO_REVERSE },
697 { X86::VPMOVZXBWrr, X86::VPMOVZXBWrm, TB_NO_REVERSE },
698 { X86::VPMOVZXDQrr, X86::VPMOVZXDQrm, TB_NO_REVERSE },
699 { X86::VPMOVZXWDrr, X86::VPMOVZXWDrm, TB_NO_REVERSE },
700 { X86::VPMOVZXWQrr, X86::VPMOVZXWQrm, TB_NO_REVERSE },
701 { X86::VPSHUFDri, X86::VPSHUFDmi, 0 },
702 { X86::VPSHUFHWri, X86::VPSHUFHWmi, 0 },
703 { X86::VPSHUFLWri, X86::VPSHUFLWmi, 0 },
704 { X86::VPTESTrr, X86::VPTESTrm, 0 },
705 { X86::VRCPPSr, X86::VRCPPSm, 0 },
706 { X86::VROUNDPDr, X86::VROUNDPDm, 0 },
707 { X86::VROUNDPSr, X86::VROUNDPSm, 0 },
708 { X86::VRSQRTPSr, X86::VRSQRTPSm, 0 },
709 { X86::VSQRTPDr, X86::VSQRTPDm, 0 },
710 { X86::VSQRTPSr, X86::VSQRTPSm, 0 },
711 { X86::VTESTPDrr, X86::VTESTPDrm, 0 },
712 { X86::VTESTPSrr, X86::VTESTPSrm, 0 },
713 { X86::VUCOMISDrr, X86::VUCOMISDrm, 0 },
714 { X86::VUCOMISSrr, X86::VUCOMISSrm, 0 },
715
716 // AVX 256-bit foldable instructions
717 { X86::VCVTDQ2PDYrr, X86::VCVTDQ2PDYrm, TB_NO_REVERSE },
718 { X86::VCVTDQ2PSYrr, X86::VCVTDQ2PSYrm, 0 },
719 { X86::VCVTPD2DQYrr, X86::VCVTPD2DQYrm, 0 },
720 { X86::VCVTPD2PSYrr, X86::VCVTPD2PSYrm, 0 },
721 { X86::VCVTPS2DQYrr, X86::VCVTPS2DQYrm, 0 },
722 { X86::VCVTPS2PDYrr, X86::VCVTPS2PDYrm, TB_NO_REVERSE },
723 { X86::VCVTTPD2DQYrr, X86::VCVTTPD2DQYrm, 0 },
724 { X86::VCVTTPS2DQYrr, X86::VCVTTPS2DQYrm, 0 },
725 { X86::VMOVAPDYrr, X86::VMOVAPDYrm, TB_ALIGN_32 },
726 { X86::VMOVAPSYrr, X86::VMOVAPSYrm, TB_ALIGN_32 },
727 { X86::VMOVDDUPYrr, X86::VMOVDDUPYrm, 0 },
728 { X86::VMOVDQAYrr, X86::VMOVDQAYrm, TB_ALIGN_32 },
729 { X86::VMOVDQUYrr, X86::VMOVDQUYrm, 0 },
730 { X86::VMOVSLDUPYrr, X86::VMOVSLDUPYrm, 0 },
731 { X86::VMOVSHDUPYrr, X86::VMOVSHDUPYrm, 0 },
732 { X86::VMOVUPDYrr, X86::VMOVUPDYrm, 0 },
733 { X86::VMOVUPSYrr, X86::VMOVUPSYrm, 0 },
734 { X86::VPERMILPDYri, X86::VPERMILPDYmi, 0 },
735 { X86::VPERMILPSYri, X86::VPERMILPSYmi, 0 },
736 { X86::VPTESTYrr, X86::VPTESTYrm, 0 },
737 { X86::VRCPPSYr, X86::VRCPPSYm, 0 },
738 { X86::VROUNDYPDr, X86::VROUNDYPDm, 0 },
739 { X86::VROUNDYPSr, X86::VROUNDYPSm, 0 },
740 { X86::VRSQRTPSYr, X86::VRSQRTPSYm, 0 },
741 { X86::VSQRTPDYr, X86::VSQRTPDYm, 0 },
742 { X86::VSQRTPSYr, X86::VSQRTPSYm, 0 },
743 { X86::VTESTPDYrr, X86::VTESTPDYrm, 0 },
744 { X86::VTESTPSYrr, X86::VTESTPSYrm, 0 },
745
746 // AVX2 foldable instructions
747
748 // VBROADCASTS{SD}rr register instructions were an AVX2 addition while the
749 // VBROADCASTS{SD}rm memory instructions were available from AVX1.
750 // TB_NO_REVERSE prevents unfolding from introducing an illegal instruction
751 // on AVX1 targets. The VPBROADCAST instructions are all AVX2 instructions
752 // so they don't need an equivalent limitation.
753 { X86::VBROADCASTSSrr, X86::VBROADCASTSSrm, TB_NO_REVERSE },
754 { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrm, TB_NO_REVERSE },
755 { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrm, TB_NO_REVERSE },
756 { X86::VPABSBYrr, X86::VPABSBYrm, 0 },
757 { X86::VPABSDYrr, X86::VPABSDYrm, 0 },
758 { X86::VPABSWYrr, X86::VPABSWYrm, 0 },
759 { X86::VPBROADCASTBrr, X86::VPBROADCASTBrm, TB_NO_REVERSE },
760 { X86::VPBROADCASTBYrr, X86::VPBROADCASTBYrm, TB_NO_REVERSE },
761 { X86::VPBROADCASTDrr, X86::VPBROADCASTDrm, TB_NO_REVERSE },
762 { X86::VPBROADCASTDYrr, X86::VPBROADCASTDYrm, TB_NO_REVERSE },
763 { X86::VPBROADCASTQrr, X86::VPBROADCASTQrm, TB_NO_REVERSE },
764 { X86::VPBROADCASTQYrr, X86::VPBROADCASTQYrm, TB_NO_REVERSE },
765 { X86::VPBROADCASTWrr, X86::VPBROADCASTWrm, TB_NO_REVERSE },
766 { X86::VPBROADCASTWYrr, X86::VPBROADCASTWYrm, TB_NO_REVERSE },
767 { X86::VPERMPDYri, X86::VPERMPDYmi, 0 },
768 { X86::VPERMQYri, X86::VPERMQYmi, 0 },
769 { X86::VPMOVSXBDYrr, X86::VPMOVSXBDYrm, TB_NO_REVERSE },
770 { X86::VPMOVSXBQYrr, X86::VPMOVSXBQYrm, TB_NO_REVERSE },
771 { X86::VPMOVSXBWYrr, X86::VPMOVSXBWYrm, 0 },
772 { X86::VPMOVSXDQYrr, X86::VPMOVSXDQYrm, 0 },
773 { X86::VPMOVSXWDYrr, X86::VPMOVSXWDYrm, 0 },
774 { X86::VPMOVSXWQYrr, X86::VPMOVSXWQYrm, TB_NO_REVERSE },
775 { X86::VPMOVZXBDYrr, X86::VPMOVZXBDYrm, TB_NO_REVERSE },
776 { X86::VPMOVZXBQYrr, X86::VPMOVZXBQYrm, TB_NO_REVERSE },
777 { X86::VPMOVZXBWYrr, X86::VPMOVZXBWYrm, 0 },
778 { X86::VPMOVZXDQYrr, X86::VPMOVZXDQYrm, 0 },
779 { X86::VPMOVZXWDYrr, X86::VPMOVZXWDYrm, 0 },
780 { X86::VPMOVZXWQYrr, X86::VPMOVZXWQYrm, TB_NO_REVERSE },
781 { X86::VPSHUFDYri, X86::VPSHUFDYmi, 0 },
782 { X86::VPSHUFHWYri, X86::VPSHUFHWYmi, 0 },
783 { X86::VPSHUFLWYri, X86::VPSHUFLWYmi, 0 },
784
785 // XOP foldable instructions
786 { X86::VFRCZPDrr, X86::VFRCZPDrm, 0 },
787 { X86::VFRCZPDrrY, X86::VFRCZPDrmY, 0 },
788 { X86::VFRCZPSrr, X86::VFRCZPSrm, 0 },
789 { X86::VFRCZPSrrY, X86::VFRCZPSrmY, 0 },
790 { X86::VFRCZSDrr, X86::VFRCZSDrm, 0 },
791 { X86::VFRCZSSrr, X86::VFRCZSSrm, 0 },
792 { X86::VPHADDBDrr, X86::VPHADDBDrm, 0 },
793 { X86::VPHADDBQrr, X86::VPHADDBQrm, 0 },
794 { X86::VPHADDBWrr, X86::VPHADDBWrm, 0 },
795 { X86::VPHADDDQrr, X86::VPHADDDQrm, 0 },
796 { X86::VPHADDWDrr, X86::VPHADDWDrm, 0 },
797 { X86::VPHADDWQrr, X86::VPHADDWQrm, 0 },
798 { X86::VPHADDUBDrr, X86::VPHADDUBDrm, 0 },
799 { X86::VPHADDUBQrr, X86::VPHADDUBQrm, 0 },
800 { X86::VPHADDUBWrr, X86::VPHADDUBWrm, 0 },
801 { X86::VPHADDUDQrr, X86::VPHADDUDQrm, 0 },
802 { X86::VPHADDUWDrr, X86::VPHADDUWDrm, 0 },
803 { X86::VPHADDUWQrr, X86::VPHADDUWQrm, 0 },
804 { X86::VPHSUBBWrr, X86::VPHSUBBWrm, 0 },
805 { X86::VPHSUBDQrr, X86::VPHSUBDQrm, 0 },
806 { X86::VPHSUBWDrr, X86::VPHSUBWDrm, 0 },
807 { X86::VPROTBri, X86::VPROTBmi, 0 },
808 { X86::VPROTBrr, X86::VPROTBmr, 0 },
809 { X86::VPROTDri, X86::VPROTDmi, 0 },
810 { X86::VPROTDrr, X86::VPROTDmr, 0 },
811 { X86::VPROTQri, X86::VPROTQmi, 0 },
812 { X86::VPROTQrr, X86::VPROTQmr, 0 },
813 { X86::VPROTWri, X86::VPROTWmi, 0 },
814 { X86::VPROTWrr, X86::VPROTWmr, 0 },
815 { X86::VPSHABrr, X86::VPSHABmr, 0 },
816 { X86::VPSHADrr, X86::VPSHADmr, 0 },
817 { X86::VPSHAQrr, X86::VPSHAQmr, 0 },
818 { X86::VPSHAWrr, X86::VPSHAWmr, 0 },
819 { X86::VPSHLBrr, X86::VPSHLBmr, 0 },
820 { X86::VPSHLDrr, X86::VPSHLDmr, 0 },
821 { X86::VPSHLQrr, X86::VPSHLQmr, 0 },
822 { X86::VPSHLWrr, X86::VPSHLWmr, 0 },
823
824 // LWP foldable instructions
825 { X86::LWPINS32rri, X86::LWPINS32rmi, 0 },
826 { X86::LWPINS64rri, X86::LWPINS64rmi, 0 },
827 { X86::LWPVAL32rri, X86::LWPVAL32rmi, 0 },
828 { X86::LWPVAL64rri, X86::LWPVAL64rmi, 0 },
829
830 // BMI/BMI2/LZCNT/POPCNT/TBM foldable instructions
831 { X86::BEXTR32rr, X86::BEXTR32rm, 0 },
832 { X86::BEXTR64rr, X86::BEXTR64rm, 0 },
833 { X86::BEXTRI32ri, X86::BEXTRI32mi, 0 },
834 { X86::BEXTRI64ri, X86::BEXTRI64mi, 0 },
835 { X86::BLCFILL32rr, X86::BLCFILL32rm, 0 },
836 { X86::BLCFILL64rr, X86::BLCFILL64rm, 0 },
837 { X86::BLCI32rr, X86::BLCI32rm, 0 },
838 { X86::BLCI64rr, X86::BLCI64rm, 0 },
839 { X86::BLCIC32rr, X86::BLCIC32rm, 0 },
840 { X86::BLCIC64rr, X86::BLCIC64rm, 0 },
841 { X86::BLCMSK32rr, X86::BLCMSK32rm, 0 },
842 { X86::BLCMSK64rr, X86::BLCMSK64rm, 0 },
843 { X86::BLCS32rr, X86::BLCS32rm, 0 },
844 { X86::BLCS64rr, X86::BLCS64rm, 0 },
845 { X86::BLSFILL32rr, X86::BLSFILL32rm, 0 },
846 { X86::BLSFILL64rr, X86::BLSFILL64rm, 0 },
847 { X86::BLSI32rr, X86::BLSI32rm, 0 },
848 { X86::BLSI64rr, X86::BLSI64rm, 0 },
849 { X86::BLSIC32rr, X86::BLSIC32rm, 0 },
850 { X86::BLSIC64rr, X86::BLSIC64rm, 0 },
851 { X86::BLSMSK32rr, X86::BLSMSK32rm, 0 },
852 { X86::BLSMSK64rr, X86::BLSMSK64rm, 0 },
853 { X86::BLSR32rr, X86::BLSR32rm, 0 },
854 { X86::BLSR64rr, X86::BLSR64rm, 0 },
855 { X86::BZHI32rr, X86::BZHI32rm, 0 },
856 { X86::BZHI64rr, X86::BZHI64rm, 0 },
857 { X86::LZCNT16rr, X86::LZCNT16rm, 0 },
858 { X86::LZCNT32rr, X86::LZCNT32rm, 0 },
859 { X86::LZCNT64rr, X86::LZCNT64rm, 0 },
860 { X86::POPCNT16rr, X86::POPCNT16rm, 0 },
861 { X86::POPCNT32rr, X86::POPCNT32rm, 0 },
862 { X86::POPCNT64rr, X86::POPCNT64rm, 0 },
863 { X86::RORX32ri, X86::RORX32mi, 0 },
864 { X86::RORX64ri, X86::RORX64mi, 0 },
865 { X86::SARX32rr, X86::SARX32rm, 0 },
866 { X86::SARX64rr, X86::SARX64rm, 0 },
867 { X86::SHRX32rr, X86::SHRX32rm, 0 },
868 { X86::SHRX64rr, X86::SHRX64rm, 0 },
869 { X86::SHLX32rr, X86::SHLX32rm, 0 },
870 { X86::SHLX64rr, X86::SHLX64rm, 0 },
871 { X86::T1MSKC32rr, X86::T1MSKC32rm, 0 },
872 { X86::T1MSKC64rr, X86::T1MSKC64rm, 0 },
873 { X86::TZCNT16rr, X86::TZCNT16rm, 0 },
874 { X86::TZCNT32rr, X86::TZCNT32rm, 0 },
875 { X86::TZCNT64rr, X86::TZCNT64rm, 0 },
876 { X86::TZMSK32rr, X86::TZMSK32rm, 0 },
877 { X86::TZMSK64rr, X86::TZMSK64rm, 0 },
878
879 // AVX-512 foldable instructions
880 { X86::VBROADCASTSSZr, X86::VBROADCASTSSZm, TB_NO_REVERSE },
881 { X86::VBROADCASTSDZr, X86::VBROADCASTSDZm, TB_NO_REVERSE },
882 { X86::VMOV64toPQIZrr, X86::VMOVQI2PQIZrm, 0 },
883 { X86::VMOV64toSDZrr, X86::VMOV64toSDZrm, 0 },
884 { X86::VMOVDI2PDIZrr, X86::VMOVDI2PDIZrm, 0 },
885 { X86::VMOVDI2SSZrr, X86::VMOVDI2SSZrm, 0 },
886 { X86::VMOVAPDZrr, X86::VMOVAPDZrm, TB_ALIGN_64 },
887 { X86::VMOVAPSZrr, X86::VMOVAPSZrm, TB_ALIGN_64 },
888 { X86::VMOVDQA32Zrr, X86::VMOVDQA32Zrm, TB_ALIGN_64 },
889 { X86::VMOVDQA64Zrr, X86::VMOVDQA64Zrm, TB_ALIGN_64 },
890 { X86::VMOVDQU8Zrr, X86::VMOVDQU8Zrm, 0 },
891 { X86::VMOVDQU16Zrr, X86::VMOVDQU16Zrm, 0 },
892 { X86::VMOVDQU32Zrr, X86::VMOVDQU32Zrm, 0 },
893 { X86::VMOVDQU64Zrr, X86::VMOVDQU64Zrm, 0 },
894 { X86::VMOVUPDZrr, X86::VMOVUPDZrm, 0 },
895 { X86::VMOVUPSZrr, X86::VMOVUPSZrm, 0 },
896 { X86::VMOVZPQILo2PQIZrr,X86::VMOVQI2PQIZrm, TB_NO_REVERSE },
897 { X86::VPABSBZrr, X86::VPABSBZrm, 0 },
898 { X86::VPABSDZrr, X86::VPABSDZrm, 0 },
899 { X86::VPABSQZrr, X86::VPABSQZrm, 0 },
900 { X86::VPABSWZrr, X86::VPABSWZrm, 0 },
901 { X86::VPERMILPDZri, X86::VPERMILPDZmi, 0 },
902 { X86::VPERMILPSZri, X86::VPERMILPSZmi, 0 },
903 { X86::VPERMPDZri, X86::VPERMPDZmi, 0 },
904 { X86::VPERMQZri, X86::VPERMQZmi, 0 },
905 { X86::VPMOVSXBDZrr, X86::VPMOVSXBDZrm, 0 },
906 { X86::VPMOVSXBQZrr, X86::VPMOVSXBQZrm, TB_NO_REVERSE },
907 { X86::VPMOVSXBWZrr, X86::VPMOVSXBWZrm, 0 },
908 { X86::VPMOVSXDQZrr, X86::VPMOVSXDQZrm, 0 },
909 { X86::VPMOVSXWDZrr, X86::VPMOVSXWDZrm, 0 },
910 { X86::VPMOVSXWQZrr, X86::VPMOVSXWQZrm, 0 },
911 { X86::VPMOVZXBDZrr, X86::VPMOVZXBDZrm, 0 },
912 { X86::VPMOVZXBQZrr, X86::VPMOVZXBQZrm, TB_NO_REVERSE },
913 { X86::VPMOVZXBWZrr, X86::VPMOVZXBWZrm, 0 },
914 { X86::VPMOVZXDQZrr, X86::VPMOVZXDQZrm, 0 },
915 { X86::VPMOVZXWDZrr, X86::VPMOVZXWDZrm, 0 },
916 { X86::VPMOVZXWQZrr, X86::VPMOVZXWQZrm, 0 },
917 { X86::VPSHUFDZri, X86::VPSHUFDZmi, 0 },
918 { X86::VPSHUFHWZri, X86::VPSHUFHWZmi, 0 },
919 { X86::VPSHUFLWZri, X86::VPSHUFLWZmi, 0 },
920 { X86::VPSLLDQZ512rr, X86::VPSLLDQZ512rm, 0 },
921 { X86::VPSLLDZri, X86::VPSLLDZmi, 0 },
922 { X86::VPSLLQZri, X86::VPSLLQZmi, 0 },
923 { X86::VPSLLWZri, X86::VPSLLWZmi, 0 },
924 { X86::VPSRADZri, X86::VPSRADZmi, 0 },
925 { X86::VPSRAQZri, X86::VPSRAQZmi, 0 },
926 { X86::VPSRAWZri, X86::VPSRAWZmi, 0 },
927 { X86::VPSRLDQZ512rr, X86::VPSRLDQZ512rm, 0 },
928 { X86::VPSRLDZri, X86::VPSRLDZmi, 0 },
929 { X86::VPSRLQZri, X86::VPSRLQZmi, 0 },
930 { X86::VPSRLWZri, X86::VPSRLWZmi, 0 },
931
932 // AVX-512 foldable instructions (256-bit versions)
933 { X86::VBROADCASTSSZ256r, X86::VBROADCASTSSZ256m, TB_NO_REVERSE },
934 { X86::VBROADCASTSDZ256r, X86::VBROADCASTSDZ256m, TB_NO_REVERSE },
935 { X86::VMOVAPDZ256rr, X86::VMOVAPDZ256rm, TB_ALIGN_32 },
936 { X86::VMOVAPSZ256rr, X86::VMOVAPSZ256rm, TB_ALIGN_32 },
937 { X86::VMOVDQA32Z256rr, X86::VMOVDQA32Z256rm, TB_ALIGN_32 },
938 { X86::VMOVDQA64Z256rr, X86::VMOVDQA64Z256rm, TB_ALIGN_32 },
939 { X86::VMOVDQU8Z256rr, X86::VMOVDQU8Z256rm, 0 },
940 { X86::VMOVDQU16Z256rr, X86::VMOVDQU16Z256rm, 0 },
941 { X86::VMOVDQU32Z256rr, X86::VMOVDQU32Z256rm, 0 },
942 { X86::VMOVDQU64Z256rr, X86::VMOVDQU64Z256rm, 0 },
943 { X86::VMOVUPDZ256rr, X86::VMOVUPDZ256rm, 0 },
944 { X86::VMOVUPSZ256rr, X86::VMOVUPSZ256rm, 0 },
945 { X86::VPABSBZ256rr, X86::VPABSBZ256rm, 0 },
946 { X86::VPABSDZ256rr, X86::VPABSDZ256rm, 0 },
947 { X86::VPABSQZ256rr, X86::VPABSQZ256rm, 0 },
948 { X86::VPABSWZ256rr, X86::VPABSWZ256rm, 0 },
949 { X86::VPERMILPDZ256ri, X86::VPERMILPDZ256mi, 0 },
950 { X86::VPERMILPSZ256ri, X86::VPERMILPSZ256mi, 0 },
951 { X86::VPERMPDZ256ri, X86::VPERMPDZ256mi, 0 },
952 { X86::VPERMQZ256ri, X86::VPERMQZ256mi, 0 },
953 { X86::VPMOVSXBDZ256rr, X86::VPMOVSXBDZ256rm, TB_NO_REVERSE },
954 { X86::VPMOVSXBQZ256rr, X86::VPMOVSXBQZ256rm, TB_NO_REVERSE },
955 { X86::VPMOVSXBWZ256rr, X86::VPMOVSXBWZ256rm, 0 },
956 { X86::VPMOVSXDQZ256rr, X86::VPMOVSXDQZ256rm, 0 },
957 { X86::VPMOVSXWDZ256rr, X86::VPMOVSXWDZ256rm, 0 },
958 { X86::VPMOVSXWQZ256rr, X86::VPMOVSXWQZ256rm, TB_NO_REVERSE },
959 { X86::VPMOVZXBDZ256rr, X86::VPMOVZXBDZ256rm, TB_NO_REVERSE },
960 { X86::VPMOVZXBQZ256rr, X86::VPMOVZXBQZ256rm, TB_NO_REVERSE },
961 { X86::VPMOVZXBWZ256rr, X86::VPMOVZXBWZ256rm, 0 },
962 { X86::VPMOVZXDQZ256rr, X86::VPMOVZXDQZ256rm, 0 },
963 { X86::VPMOVZXWDZ256rr, X86::VPMOVZXWDZ256rm, 0 },
964 { X86::VPMOVZXWQZ256rr, X86::VPMOVZXWQZ256rm, TB_NO_REVERSE },
965 { X86::VPSHUFDZ256ri, X86::VPSHUFDZ256mi, 0 },
966 { X86::VPSHUFHWZ256ri, X86::VPSHUFHWZ256mi, 0 },
967 { X86::VPSHUFLWZ256ri, X86::VPSHUFLWZ256mi, 0 },
968 { X86::VPSLLDQZ256rr, X86::VPSLLDQZ256rm, 0 },
969 { X86::VPSLLDZ256ri, X86::VPSLLDZ256mi, 0 },
970 { X86::VPSLLQZ256ri, X86::VPSLLQZ256mi, 0 },
971 { X86::VPSLLWZ256ri, X86::VPSLLWZ256mi, 0 },
972 { X86::VPSRADZ256ri, X86::VPSRADZ256mi, 0 },
973 { X86::VPSRAQZ256ri, X86::VPSRAQZ256mi, 0 },
974 { X86::VPSRAWZ256ri, X86::VPSRAWZ256mi, 0 },
975 { X86::VPSRLDQZ256rr, X86::VPSRLDQZ256rm, 0 },
976 { X86::VPSRLDZ256ri, X86::VPSRLDZ256mi, 0 },
977 { X86::VPSRLQZ256ri, X86::VPSRLQZ256mi, 0 },
978 { X86::VPSRLWZ256ri, X86::VPSRLWZ256mi, 0 },
979
980 // AVX-512 foldable instructions (128-bit versions)
981 { X86::VBROADCASTSSZ128r, X86::VBROADCASTSSZ128m, TB_NO_REVERSE },
982 { X86::VMOVAPDZ128rr, X86::VMOVAPDZ128rm, TB_ALIGN_16 },
983 { X86::VMOVAPSZ128rr, X86::VMOVAPSZ128rm, TB_ALIGN_16 },
984 { X86::VMOVDQA32Z128rr, X86::VMOVDQA32Z128rm, TB_ALIGN_16 },
985 { X86::VMOVDQA64Z128rr, X86::VMOVDQA64Z128rm, TB_ALIGN_16 },
986 { X86::VMOVDQU8Z128rr, X86::VMOVDQU8Z128rm, 0 },
987 { X86::VMOVDQU16Z128rr, X86::VMOVDQU16Z128rm, 0 },
988 { X86::VMOVDQU32Z128rr, X86::VMOVDQU32Z128rm, 0 },
989 { X86::VMOVDQU64Z128rr, X86::VMOVDQU64Z128rm, 0 },
990 { X86::VMOVUPDZ128rr, X86::VMOVUPDZ128rm, 0 },
991 { X86::VMOVUPSZ128rr, X86::VMOVUPSZ128rm, 0 },
992 { X86::VPABSBZ128rr, X86::VPABSBZ128rm, 0 },
993 { X86::VPABSDZ128rr, X86::VPABSDZ128rm, 0 },
994 { X86::VPABSQZ128rr, X86::VPABSQZ128rm, 0 },
995 { X86::VPABSWZ128rr, X86::VPABSWZ128rm, 0 },
996 { X86::VPERMILPDZ128ri, X86::VPERMILPDZ128mi, 0 },
997 { X86::VPERMILPSZ128ri, X86::VPERMILPSZ128mi, 0 },
998 { X86::VPMOVSXBDZ128rr, X86::VPMOVSXBDZ128rm, TB_NO_REVERSE },
999 { X86::VPMOVSXBQZ128rr, X86::VPMOVSXBQZ128rm, TB_NO_REVERSE },
1000 { X86::VPMOVSXBWZ128rr, X86::VPMOVSXBWZ128rm, TB_NO_REVERSE },
1001 { X86::VPMOVSXDQZ128rr, X86::VPMOVSXDQZ128rm, TB_NO_REVERSE },
1002 { X86::VPMOVSXWDZ128rr, X86::VPMOVSXWDZ128rm, TB_NO_REVERSE },
1003 { X86::VPMOVSXWQZ128rr, X86::VPMOVSXWQZ128rm, TB_NO_REVERSE },
1004 { X86::VPMOVZXBDZ128rr, X86::VPMOVZXBDZ128rm, TB_NO_REVERSE },
1005 { X86::VPMOVZXBQZ128rr, X86::VPMOVZXBQZ128rm, TB_NO_REVERSE },
1006 { X86::VPMOVZXBWZ128rr, X86::VPMOVZXBWZ128rm, TB_NO_REVERSE },
1007 { X86::VPMOVZXDQZ128rr, X86::VPMOVZXDQZ128rm, TB_NO_REVERSE },
1008 { X86::VPMOVZXWDZ128rr, X86::VPMOVZXWDZ128rm, TB_NO_REVERSE },
1009 { X86::VPMOVZXWQZ128rr, X86::VPMOVZXWQZ128rm, TB_NO_REVERSE },
1010 { X86::VPSHUFDZ128ri, X86::VPSHUFDZ128mi, 0 },
1011 { X86::VPSHUFHWZ128ri, X86::VPSHUFHWZ128mi, 0 },
1012 { X86::VPSHUFLWZ128ri, X86::VPSHUFLWZ128mi, 0 },
1013 { X86::VPSLLDQZ128rr, X86::VPSLLDQZ128rm, 0 },
1014 { X86::VPSLLDZ128ri, X86::VPSLLDZ128mi, 0 },
1015 { X86::VPSLLQZ128ri, X86::VPSLLQZ128mi, 0 },
1016 { X86::VPSLLWZ128ri, X86::VPSLLWZ128mi, 0 },
1017 { X86::VPSRADZ128ri, X86::VPSRADZ128mi, 0 },
1018 { X86::VPSRAQZ128ri, X86::VPSRAQZ128mi, 0 },
1019 { X86::VPSRAWZ128ri, X86::VPSRAWZ128mi, 0 },
1020 { X86::VPSRLDQZ128rr, X86::VPSRLDQZ128rm, 0 },
1021 { X86::VPSRLDZ128ri, X86::VPSRLDZ128mi, 0 },
1022 { X86::VPSRLQZ128ri, X86::VPSRLQZ128mi, 0 },
1023 { X86::VPSRLWZ128ri, X86::VPSRLWZ128mi, 0 },
1024
1025 // F16C foldable instructions
1026 { X86::VCVTPH2PSrr, X86::VCVTPH2PSrm, 0 },
1027 { X86::VCVTPH2PSYrr, X86::VCVTPH2PSYrm, 0 },
1028
1029 // AES foldable instructions
1030 { X86::AESIMCrr, X86::AESIMCrm, TB_ALIGN_16 },
1031 { X86::AESKEYGENASSIST128rr, X86::AESKEYGENASSIST128rm, TB_ALIGN_16 },
1032 { X86::VAESIMCrr, X86::VAESIMCrm, 0 },
1033 { X86::VAESKEYGENASSIST128rr, X86::VAESKEYGENASSIST128rm, 0 }
1034 };
1035
1036 for (X86MemoryFoldTableEntry Entry : MemoryFoldTable1) {
1037 AddTableEntry(RegOp2MemOpTable1, MemOp2RegOpTable,
1038 Entry.RegOp, Entry.MemOp,
1039 // Index 1, folded load
1040 Entry.Flags | TB_INDEX_1 | TB_FOLDED_LOAD);
1041 }
1042
1043 static const X86MemoryFoldTableEntry MemoryFoldTable2[] = {
1044 { X86::ADC32rr, X86::ADC32rm, 0 },
1045 { X86::ADC64rr, X86::ADC64rm, 0 },
1046 { X86::ADD16rr, X86::ADD16rm, 0 },
1047 { X86::ADD16rr_DB, X86::ADD16rm, TB_NO_REVERSE },
1048 { X86::ADD32rr, X86::ADD32rm, 0 },
1049 { X86::ADD32rr_DB, X86::ADD32rm, TB_NO_REVERSE },
1050 { X86::ADD64rr, X86::ADD64rm, 0 },
1051 { X86::ADD64rr_DB, X86::ADD64rm, TB_NO_REVERSE },
1052 { X86::ADD8rr, X86::ADD8rm, 0 },
1053 { X86::ADDPDrr, X86::ADDPDrm, TB_ALIGN_16 },
1054 { X86::ADDPSrr, X86::ADDPSrm, TB_ALIGN_16 },
1055 { X86::ADDSDrr, X86::ADDSDrm, 0 },
1056 { X86::ADDSDrr_Int, X86::ADDSDrm_Int, TB_NO_REVERSE },
1057 { X86::ADDSSrr, X86::ADDSSrm, 0 },
1058 { X86::ADDSSrr_Int, X86::ADDSSrm_Int, TB_NO_REVERSE },
1059 { X86::ADDSUBPDrr, X86::ADDSUBPDrm, TB_ALIGN_16 },
1060 { X86::ADDSUBPSrr, X86::ADDSUBPSrm, TB_ALIGN_16 },
1061 { X86::AND16rr, X86::AND16rm, 0 },
1062 { X86::AND32rr, X86::AND32rm, 0 },
1063 { X86::AND64rr, X86::AND64rm, 0 },
1064 { X86::AND8rr, X86::AND8rm, 0 },
1065 { X86::ANDNPDrr, X86::ANDNPDrm, TB_ALIGN_16 },
1066 { X86::ANDNPSrr, X86::ANDNPSrm, TB_ALIGN_16 },
1067 { X86::ANDPDrr, X86::ANDPDrm, TB_ALIGN_16 },
1068 { X86::ANDPSrr, X86::ANDPSrm, TB_ALIGN_16 },
1069 { X86::BLENDPDrri, X86::BLENDPDrmi, TB_ALIGN_16 },
1070 { X86::BLENDPSrri, X86::BLENDPSrmi, TB_ALIGN_16 },
1071 { X86::BLENDVPDrr0, X86::BLENDVPDrm0, TB_ALIGN_16 },
1072 { X86::BLENDVPSrr0, X86::BLENDVPSrm0, TB_ALIGN_16 },
1073 { X86::CMOVA16rr, X86::CMOVA16rm, 0 },
1074 { X86::CMOVA32rr, X86::CMOVA32rm, 0 },
1075 { X86::CMOVA64rr, X86::CMOVA64rm, 0 },
1076 { X86::CMOVAE16rr, X86::CMOVAE16rm, 0 },
1077 { X86::CMOVAE32rr, X86::CMOVAE32rm, 0 },
1078 { X86::CMOVAE64rr, X86::CMOVAE64rm, 0 },
1079 { X86::CMOVB16rr, X86::CMOVB16rm, 0 },
1080 { X86::CMOVB32rr, X86::CMOVB32rm, 0 },
1081 { X86::CMOVB64rr, X86::CMOVB64rm, 0 },
1082 { X86::CMOVBE16rr, X86::CMOVBE16rm, 0 },
1083 { X86::CMOVBE32rr, X86::CMOVBE32rm, 0 },
1084 { X86::CMOVBE64rr, X86::CMOVBE64rm, 0 },
1085 { X86::CMOVE16rr, X86::CMOVE16rm, 0 },
1086 { X86::CMOVE32rr, X86::CMOVE32rm, 0 },
1087 { X86::CMOVE64rr, X86::CMOVE64rm, 0 },
1088 { X86::CMOVG16rr, X86::CMOVG16rm, 0 },
1089 { X86::CMOVG32rr, X86::CMOVG32rm, 0 },
1090 { X86::CMOVG64rr, X86::CMOVG64rm, 0 },
1091 { X86::CMOVGE16rr, X86::CMOVGE16rm, 0 },
1092 { X86::CMOVGE32rr, X86::CMOVGE32rm, 0 },
1093 { X86::CMOVGE64rr, X86::CMOVGE64rm, 0 },
1094 { X86::CMOVL16rr, X86::CMOVL16rm, 0 },
1095 { X86::CMOVL32rr, X86::CMOVL32rm, 0 },
1096 { X86::CMOVL64rr, X86::CMOVL64rm, 0 },
1097 { X86::CMOVLE16rr, X86::CMOVLE16rm, 0 },
1098 { X86::CMOVLE32rr, X86::CMOVLE32rm, 0 },
1099 { X86::CMOVLE64rr, X86::CMOVLE64rm, 0 },
1100 { X86::CMOVNE16rr, X86::CMOVNE16rm, 0 },
1101 { X86::CMOVNE32rr, X86::CMOVNE32rm, 0 },
1102 { X86::CMOVNE64rr, X86::CMOVNE64rm, 0 },
1103 { X86::CMOVNO16rr, X86::CMOVNO16rm, 0 },
1104 { X86::CMOVNO32rr, X86::CMOVNO32rm, 0 },
1105 { X86::CMOVNO64rr, X86::CMOVNO64rm, 0 },
1106 { X86::CMOVNP16rr, X86::CMOVNP16rm, 0 },
1107 { X86::CMOVNP32rr, X86::CMOVNP32rm, 0 },
1108 { X86::CMOVNP64rr, X86::CMOVNP64rm, 0 },
1109 { X86::CMOVNS16rr, X86::CMOVNS16rm, 0 },
1110 { X86::CMOVNS32rr, X86::CMOVNS32rm, 0 },
1111 { X86::CMOVNS64rr, X86::CMOVNS64rm, 0 },
1112 { X86::CMOVO16rr, X86::CMOVO16rm, 0 },
1113 { X86::CMOVO32rr, X86::CMOVO32rm, 0 },
1114 { X86::CMOVO64rr, X86::CMOVO64rm, 0 },
1115 { X86::CMOVP16rr, X86::CMOVP16rm, 0 },
1116 { X86::CMOVP32rr, X86::CMOVP32rm, 0 },
1117 { X86::CMOVP64rr, X86::CMOVP64rm, 0 },
1118 { X86::CMOVS16rr, X86::CMOVS16rm, 0 },
1119 { X86::CMOVS32rr, X86::CMOVS32rm, 0 },
1120 { X86::CMOVS64rr, X86::CMOVS64rm, 0 },
1121 { X86::CMPPDrri, X86::CMPPDrmi, TB_ALIGN_16 },
1122 { X86::CMPPSrri, X86::CMPPSrmi, TB_ALIGN_16 },
1123 { X86::CMPSDrr, X86::CMPSDrm, 0 },
1124 { X86::CMPSSrr, X86::CMPSSrm, 0 },
1125 { X86::CRC32r32r32, X86::CRC32r32m32, 0 },
1126 { X86::CRC32r64r64, X86::CRC32r64m64, 0 },
1127 { X86::DIVPDrr, X86::DIVPDrm, TB_ALIGN_16 },
1128 { X86::DIVPSrr, X86::DIVPSrm, TB_ALIGN_16 },
1129 { X86::DIVSDrr, X86::DIVSDrm, 0 },
1130 { X86::DIVSDrr_Int, X86::DIVSDrm_Int, TB_NO_REVERSE },
1131 { X86::DIVSSrr, X86::DIVSSrm, 0 },
1132 { X86::DIVSSrr_Int, X86::DIVSSrm_Int, TB_NO_REVERSE },
1133 { X86::DPPDrri, X86::DPPDrmi, TB_ALIGN_16 },
1134 { X86::DPPSrri, X86::DPPSrmi, TB_ALIGN_16 },
1135 { X86::HADDPDrr, X86::HADDPDrm, TB_ALIGN_16 },
1136 { X86::HADDPSrr, X86::HADDPSrm, TB_ALIGN_16 },
1137 { X86::HSUBPDrr, X86::HSUBPDrm, TB_ALIGN_16 },
1138 { X86::HSUBPSrr, X86::HSUBPSrm, TB_ALIGN_16 },
1139 { X86::IMUL16rr, X86::IMUL16rm, 0 },
1140 { X86::IMUL32rr, X86::IMUL32rm, 0 },
1141 { X86::IMUL64rr, X86::IMUL64rm, 0 },
1142 { X86::Int_CMPSDrr, X86::Int_CMPSDrm, TB_NO_REVERSE },
1143 { X86::Int_CMPSSrr, X86::Int_CMPSSrm, TB_NO_REVERSE },
1144 { X86::Int_CVTSD2SSrr, X86::Int_CVTSD2SSrm, TB_NO_REVERSE },
1145 { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm, 0 },
1146 { X86::Int_CVTSI2SDrr, X86::Int_CVTSI2SDrm, 0 },
1147 { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm, 0 },
1148 { X86::Int_CVTSI2SSrr, X86::Int_CVTSI2SSrm, 0 },
1149 { X86::Int_CVTSS2SDrr, X86::Int_CVTSS2SDrm, TB_NO_REVERSE },
1150 { X86::MAXPDrr, X86::MAXPDrm, TB_ALIGN_16 },
1151 { X86::MAXCPDrr, X86::MAXCPDrm, TB_ALIGN_16 },
1152 { X86::MAXPSrr, X86::MAXPSrm, TB_ALIGN_16 },
1153 { X86::MAXCPSrr, X86::MAXCPSrm, TB_ALIGN_16 },
1154 { X86::MAXSDrr, X86::MAXSDrm, 0 },
1155 { X86::MAXCSDrr, X86::MAXCSDrm, 0 },
1156 { X86::MAXSDrr_Int, X86::MAXSDrm_Int, TB_NO_REVERSE },
1157 { X86::MAXSSrr, X86::MAXSSrm, 0 },
1158 { X86::MAXCSSrr, X86::MAXCSSrm, 0 },
1159 { X86::MAXSSrr_Int, X86::MAXSSrm_Int, TB_NO_REVERSE },
1160 { X86::MINPDrr, X86::MINPDrm, TB_ALIGN_16 },
1161 { X86::MINCPDrr, X86::MINCPDrm, TB_ALIGN_16 },
1162 { X86::MINPSrr, X86::MINPSrm, TB_ALIGN_16 },
1163 { X86::MINCPSrr, X86::MINCPSrm, TB_ALIGN_16 },
1164 { X86::MINSDrr, X86::MINSDrm, 0 },
1165 { X86::MINCSDrr, X86::MINCSDrm, 0 },
1166 { X86::MINSDrr_Int, X86::MINSDrm_Int, TB_NO_REVERSE },
1167 { X86::MINSSrr, X86::MINSSrm, 0 },
1168 { X86::MINCSSrr, X86::MINCSSrm, 0 },
1169 { X86::MINSSrr_Int, X86::MINSSrm_Int, TB_NO_REVERSE },
1170 { X86::MOVLHPSrr, X86::MOVHPSrm, TB_NO_REVERSE },
1171 { X86::MPSADBWrri, X86::MPSADBWrmi, TB_ALIGN_16 },
1172 { X86::MULPDrr, X86::MULPDrm, TB_ALIGN_16 },
1173 { X86::MULPSrr, X86::MULPSrm, TB_ALIGN_16 },
1174 { X86::MULSDrr, X86::MULSDrm, 0 },
1175 { X86::MULSDrr_Int, X86::MULSDrm_Int, TB_NO_REVERSE },
1176 { X86::MULSSrr, X86::MULSSrm, 0 },
1177 { X86::MULSSrr_Int, X86::MULSSrm_Int, TB_NO_REVERSE },
1178 { X86::OR16rr, X86::OR16rm, 0 },
1179 { X86::OR32rr, X86::OR32rm, 0 },
1180 { X86::OR64rr, X86::OR64rm, 0 },
1181 { X86::OR8rr, X86::OR8rm, 0 },
1182 { X86::ORPDrr, X86::ORPDrm, TB_ALIGN_16 },
1183 { X86::ORPSrr, X86::ORPSrm, TB_ALIGN_16 },
1184 { X86::PACKSSDWrr, X86::PACKSSDWrm, TB_ALIGN_16 },
1185 { X86::PACKSSWBrr, X86::PACKSSWBrm, TB_ALIGN_16 },
1186 { X86::PACKUSDWrr, X86::PACKUSDWrm, TB_ALIGN_16 },
1187 { X86::PACKUSWBrr, X86::PACKUSWBrm, TB_ALIGN_16 },
1188 { X86::PADDBrr, X86::PADDBrm, TB_ALIGN_16 },
1189 { X86::PADDDrr, X86::PADDDrm, TB_ALIGN_16 },
1190 { X86::PADDQrr, X86::PADDQrm, TB_ALIGN_16 },
1191 { X86::PADDSBrr, X86::PADDSBrm, TB_ALIGN_16 },
1192 { X86::PADDSWrr, X86::PADDSWrm, TB_ALIGN_16 },
1193 { X86::PADDUSBrr, X86::PADDUSBrm, TB_ALIGN_16 },
1194 { X86::PADDUSWrr, X86::PADDUSWrm, TB_ALIGN_16 },
1195 { X86::PADDWrr, X86::PADDWrm, TB_ALIGN_16 },
1196 { X86::PALIGNRrri, X86::PALIGNRrmi, TB_ALIGN_16 },
1197 { X86::PANDNrr, X86::PANDNrm, TB_ALIGN_16 },
1198 { X86::PANDrr, X86::PANDrm, TB_ALIGN_16 },
1199 { X86::PAVGBrr, X86::PAVGBrm, TB_ALIGN_16 },
1200 { X86::PAVGWrr, X86::PAVGWrm, TB_ALIGN_16 },
1201 { X86::PBLENDVBrr0, X86::PBLENDVBrm0, TB_ALIGN_16 },
1202 { X86::PBLENDWrri, X86::PBLENDWrmi, TB_ALIGN_16 },
1203 { X86::PCLMULQDQrr, X86::PCLMULQDQrm, TB_ALIGN_16 },
1204 { X86::PCMPEQBrr, X86::PCMPEQBrm, TB_ALIGN_16 },
1205 { X86::PCMPEQDrr, X86::PCMPEQDrm, TB_ALIGN_16 },
1206 { X86::PCMPEQQrr, X86::PCMPEQQrm, TB_ALIGN_16 },
1207 { X86::PCMPEQWrr, X86::PCMPEQWrm, TB_ALIGN_16 },
1208 { X86::PCMPGTBrr, X86::PCMPGTBrm, TB_ALIGN_16 },
1209 { X86::PCMPGTDrr, X86::PCMPGTDrm, TB_ALIGN_16 },
1210 { X86::PCMPGTQrr, X86::PCMPGTQrm, TB_ALIGN_16 },
1211 { X86::PCMPGTWrr, X86::PCMPGTWrm, TB_ALIGN_16 },
1212 { X86::PHADDDrr, X86::PHADDDrm, TB_ALIGN_16 },
1213 { X86::PHADDWrr, X86::PHADDWrm, TB_ALIGN_16 },
1214 { X86::PHADDSWrr128, X86::PHADDSWrm128, TB_ALIGN_16 },
1215 { X86::PHSUBDrr, X86::PHSUBDrm, TB_ALIGN_16 },
1216 { X86::PHSUBSWrr128, X86::PHSUBSWrm128, TB_ALIGN_16 },
1217 { X86::PHSUBWrr, X86::PHSUBWrm, TB_ALIGN_16 },
1218 { X86::PINSRBrr, X86::PINSRBrm, 0 },
1219 { X86::PINSRDrr, X86::PINSRDrm, 0 },
1220 { X86::PINSRQrr, X86::PINSRQrm, 0 },
1221 { X86::PINSRWrri, X86::PINSRWrmi, 0 },
1222 { X86::PMADDUBSWrr, X86::PMADDUBSWrm, TB_ALIGN_16 },
1223 { X86::PMADDWDrr, X86::PMADDWDrm, TB_ALIGN_16 },
1224 { X86::PMAXSBrr, X86::PMAXSBrm, TB_ALIGN_16 },
1225 { X86::PMAXSDrr, X86::PMAXSDrm, TB_ALIGN_16 },
1226 { X86::PMAXSWrr, X86::PMAXSWrm, TB_ALIGN_16 },
1227 { X86::PMAXUBrr, X86::PMAXUBrm, TB_ALIGN_16 },
1228 { X86::PMAXUDrr, X86::PMAXUDrm, TB_ALIGN_16 },
1229 { X86::PMAXUWrr, X86::PMAXUWrm, TB_ALIGN_16 },
1230 { X86::PMINSBrr, X86::PMINSBrm, TB_ALIGN_16 },
1231 { X86::PMINSDrr, X86::PMINSDrm, TB_ALIGN_16 },
1232 { X86::PMINSWrr, X86::PMINSWrm, TB_ALIGN_16 },
1233 { X86::PMINUBrr, X86::PMINUBrm, TB_ALIGN_16 },
1234 { X86::PMINUDrr, X86::PMINUDrm, TB_ALIGN_16 },
1235 { X86::PMINUWrr, X86::PMINUWrm, TB_ALIGN_16 },
1236 { X86::PMULDQrr, X86::PMULDQrm, TB_ALIGN_16 },
1237 { X86::PMULHRSWrr, X86::PMULHRSWrm, TB_ALIGN_16 },
1238 { X86::PMULHUWrr, X86::PMULHUWrm, TB_ALIGN_16 },
1239 { X86::PMULHWrr, X86::PMULHWrm, TB_ALIGN_16 },
1240 { X86::PMULLDrr, X86::PMULLDrm, TB_ALIGN_16 },
1241 { X86::PMULLWrr, X86::PMULLWrm, TB_ALIGN_16 },
1242 { X86::PMULUDQrr, X86::PMULUDQrm, TB_ALIGN_16 },
1243 { X86::PORrr, X86::PORrm, TB_ALIGN_16 },
1244 { X86::PSADBWrr, X86::PSADBWrm, TB_ALIGN_16 },
1245 { X86::PSHUFBrr, X86::PSHUFBrm, TB_ALIGN_16 },
1246 { X86::PSIGNBrr128, X86::PSIGNBrm128, TB_ALIGN_16 },
1247 { X86::PSIGNWrr128, X86::PSIGNWrm128, TB_ALIGN_16 },
1248 { X86::PSIGNDrr128, X86::PSIGNDrm128, TB_ALIGN_16 },
1249 { X86::PSLLDrr, X86::PSLLDrm, TB_ALIGN_16 },
1250 { X86::PSLLQrr, X86::PSLLQrm, TB_ALIGN_16 },
1251 { X86::PSLLWrr, X86::PSLLWrm, TB_ALIGN_16 },
1252 { X86::PSRADrr, X86::PSRADrm, TB_ALIGN_16 },
1253 { X86::PSRAWrr, X86::PSRAWrm, TB_ALIGN_16 },
1254 { X86::PSRLDrr, X86::PSRLDrm, TB_ALIGN_16 },
1255 { X86::PSRLQrr, X86::PSRLQrm, TB_ALIGN_16 },
1256 { X86::PSRLWrr, X86::PSRLWrm, TB_ALIGN_16 },
1257 { X86::PSUBBrr, X86::PSUBBrm, TB_ALIGN_16 },
1258 { X86::PSUBDrr, X86::PSUBDrm, TB_ALIGN_16 },
1259 { X86::PSUBQrr, X86::PSUBQrm, TB_ALIGN_16 },
1260 { X86::PSUBSBrr, X86::PSUBSBrm, TB_ALIGN_16 },
1261 { X86::PSUBSWrr, X86::PSUBSWrm, TB_ALIGN_16 },
1262 { X86::PSUBUSBrr, X86::PSUBUSBrm, TB_ALIGN_16 },
1263 { X86::PSUBUSWrr, X86::PSUBUSWrm, TB_ALIGN_16 },
1264 { X86::PSUBWrr, X86::PSUBWrm, TB_ALIGN_16 },
1265 { X86::PUNPCKHBWrr, X86::PUNPCKHBWrm, TB_ALIGN_16 },
1266 { X86::PUNPCKHDQrr, X86::PUNPCKHDQrm, TB_ALIGN_16 },
1267 { X86::PUNPCKHQDQrr, X86::PUNPCKHQDQrm, TB_ALIGN_16 },
1268 { X86::PUNPCKHWDrr, X86::PUNPCKHWDrm, TB_ALIGN_16 },
1269 { X86::PUNPCKLBWrr, X86::PUNPCKLBWrm, TB_ALIGN_16 },
1270 { X86::PUNPCKLDQrr, X86::PUNPCKLDQrm, TB_ALIGN_16 },
1271 { X86::PUNPCKLQDQrr, X86::PUNPCKLQDQrm, TB_ALIGN_16 },
1272 { X86::PUNPCKLWDrr, X86::PUNPCKLWDrm, TB_ALIGN_16 },
1273 { X86::PXORrr, X86::PXORrm, TB_ALIGN_16 },
1274 { X86::ROUNDSDr_Int, X86::ROUNDSDm_Int, TB_NO_REVERSE },
1275 { X86::ROUNDSSr_Int, X86::ROUNDSSm_Int, TB_NO_REVERSE },
1276 { X86::SBB32rr, X86::SBB32rm, 0 },
1277 { X86::SBB64rr, X86::SBB64rm, 0 },
1278 { X86::SHUFPDrri, X86::SHUFPDrmi, TB_ALIGN_16 },
1279 { X86::SHUFPSrri, X86::SHUFPSrmi, TB_ALIGN_16 },
1280 { X86::SUB16rr, X86::SUB16rm, 0 },
1281 { X86::SUB32rr, X86::SUB32rm, 0 },
1282 { X86::SUB64rr, X86::SUB64rm, 0 },
1283 { X86::SUB8rr, X86::SUB8rm, 0 },
1284 { X86::SUBPDrr, X86::SUBPDrm, TB_ALIGN_16 },
1285 { X86::SUBPSrr, X86::SUBPSrm, TB_ALIGN_16 },
1286 { X86::SUBSDrr, X86::SUBSDrm, 0 },
1287 { X86::SUBSDrr_Int, X86::SUBSDrm_Int, TB_NO_REVERSE },
1288 { X86::SUBSSrr, X86::SUBSSrm, 0 },
1289 { X86::SUBSSrr_Int, X86::SUBSSrm_Int, TB_NO_REVERSE },
1290 // FIXME: TEST*rr -> swapped operand of TEST*mr.
1291 { X86::UNPCKHPDrr, X86::UNPCKHPDrm, TB_ALIGN_16 },
1292 { X86::UNPCKHPSrr, X86::UNPCKHPSrm, TB_ALIGN_16 },
1293 { X86::UNPCKLPDrr, X86::UNPCKLPDrm, TB_ALIGN_16 },
1294 { X86::UNPCKLPSrr, X86::UNPCKLPSrm, TB_ALIGN_16 },
1295 { X86::XOR16rr, X86::XOR16rm, 0 },
1296 { X86::XOR32rr, X86::XOR32rm, 0 },
1297 { X86::XOR64rr, X86::XOR64rm, 0 },
1298 { X86::XOR8rr, X86::XOR8rm, 0 },
1299 { X86::XORPDrr, X86::XORPDrm, TB_ALIGN_16 },
1300 { X86::XORPSrr, X86::XORPSrm, TB_ALIGN_16 },
1301
1302 // MMX version of foldable instructions
1303 { X86::MMX_CVTPI2PSirr, X86::MMX_CVTPI2PSirm, 0 },
1304 { X86::MMX_PACKSSDWirr, X86::MMX_PACKSSDWirm, 0 },
1305 { X86::MMX_PACKSSWBirr, X86::MMX_PACKSSWBirm, 0 },
1306 { X86::MMX_PACKUSWBirr, X86::MMX_PACKUSWBirm, 0 },
1307 { X86::MMX_PADDBirr, X86::MMX_PADDBirm, 0 },
1308 { X86::MMX_PADDDirr, X86::MMX_PADDDirm, 0 },
1309 { X86::MMX_PADDQirr, X86::MMX_PADDQirm, 0 },
1310 { X86::MMX_PADDSBirr, X86::MMX_PADDSBirm, 0 },
1311 { X86::MMX_PADDSWirr, X86::MMX_PADDSWirm, 0 },
1312 { X86::MMX_PADDUSBirr, X86::MMX_PADDUSBirm, 0 },
1313 { X86::MMX_PADDUSWirr, X86::MMX_PADDUSWirm, 0 },
1314 { X86::MMX_PADDWirr, X86::MMX_PADDWirm, 0 },
1315 { X86::MMX_PALIGNR64irr, X86::MMX_PALIGNR64irm, 0 },
1316 { X86::MMX_PANDNirr, X86::MMX_PANDNirm, 0 },
1317 { X86::MMX_PANDirr, X86::MMX_PANDirm, 0 },
1318 { X86::MMX_PAVGBirr, X86::MMX_PAVGBirm, 0 },
1319 { X86::MMX_PAVGWirr, X86::MMX_PAVGWirm, 0 },
1320 { X86::MMX_PCMPEQBirr, X86::MMX_PCMPEQBirm, 0 },
1321 { X86::MMX_PCMPEQDirr, X86::MMX_PCMPEQDirm, 0 },
1322 { X86::MMX_PCMPEQWirr, X86::MMX_PCMPEQWirm, 0 },
1323 { X86::MMX_PCMPGTBirr, X86::MMX_PCMPGTBirm, 0 },
1324 { X86::MMX_PCMPGTDirr, X86::MMX_PCMPGTDirm, 0 },
1325 { X86::MMX_PCMPGTWirr, X86::MMX_PCMPGTWirm, 0 },
1326 { X86::MMX_PHADDSWrr64, X86::MMX_PHADDSWrm64, 0 },
1327 { X86::MMX_PHADDWrr64, X86::MMX_PHADDWrm64, 0 },
1328 { X86::MMX_PHADDrr64, X86::MMX_PHADDrm64, 0 },
1329 { X86::MMX_PHSUBDrr64, X86::MMX_PHSUBDrm64, 0 },
1330 { X86::MMX_PHSUBSWrr64, X86::MMX_PHSUBSWrm64, 0 },
1331 { X86::MMX_PHSUBWrr64, X86::MMX_PHSUBWrm64, 0 },
1332 { X86::MMX_PINSRWirri, X86::MMX_PINSRWirmi, 0 },
1333 { X86::MMX_PMADDUBSWrr64, X86::MMX_PMADDUBSWrm64, 0 },
1334 { X86::MMX_PMADDWDirr, X86::MMX_PMADDWDirm, 0 },
1335 { X86::MMX_PMAXSWirr, X86::MMX_PMAXSWirm, 0 },
1336 { X86::MMX_PMAXUBirr, X86::MMX_PMAXUBirm, 0 },
1337 { X86::MMX_PMINSWirr, X86::MMX_PMINSWirm, 0 },
1338 { X86::MMX_PMINUBirr, X86::MMX_PMINUBirm, 0 },
1339 { X86::MMX_PMULHRSWrr64, X86::MMX_PMULHRSWrm64, 0 },
1340 { X86::MMX_PMULHUWirr, X86::MMX_PMULHUWirm, 0 },
1341 { X86::MMX_PMULHWirr, X86::MMX_PMULHWirm, 0 },
1342 { X86::MMX_PMULLWirr, X86::MMX_PMULLWirm, 0 },
1343 { X86::MMX_PMULUDQirr, X86::MMX_PMULUDQirm, 0 },
1344 { X86::MMX_PORirr, X86::MMX_PORirm, 0 },
1345 { X86::MMX_PSADBWirr, X86::MMX_PSADBWirm, 0 },
1346 { X86::MMX_PSHUFBrr64, X86::MMX_PSHUFBrm64, 0 },
1347 { X86::MMX_PSIGNBrr64, X86::MMX_PSIGNBrm64, 0 },
1348 { X86::MMX_PSIGNDrr64, X86::MMX_PSIGNDrm64, 0 },
1349 { X86::MMX_PSIGNWrr64, X86::MMX_PSIGNWrm64, 0 },
1350 { X86::MMX_PSLLDrr, X86::MMX_PSLLDrm, 0 },
1351 { X86::MMX_PSLLQrr, X86::MMX_PSLLQrm, 0 },
1352 { X86::MMX_PSLLWrr, X86::MMX_PSLLWrm, 0 },
1353 { X86::MMX_PSRADrr, X86::MMX_PSRADrm, 0 },
1354 { X86::MMX_PSRAWrr, X86::MMX_PSRAWrm, 0 },
1355 { X86::MMX_PSRLDrr, X86::MMX_PSRLDrm, 0 },
1356 { X86::MMX_PSRLQrr, X86::MMX_PSRLQrm, 0 },
1357 { X86::MMX_PSRLWrr, X86::MMX_PSRLWrm, 0 },
1358 { X86::MMX_PSUBBirr, X86::MMX_PSUBBirm, 0 },
1359 { X86::MMX_PSUBDirr, X86::MMX_PSUBDirm, 0 },
1360 { X86::MMX_PSUBQirr, X86::MMX_PSUBQirm, 0 },
1361 { X86::MMX_PSUBSBirr, X86::MMX_PSUBSBirm, 0 },
1362 { X86::MMX_PSUBSWirr, X86::MMX_PSUBSWirm, 0 },
1363 { X86::MMX_PSUBUSBirr, X86::MMX_PSUBUSBirm, 0 },
1364 { X86::MMX_PSUBUSWirr, X86::MMX_PSUBUSWirm, 0 },
1365 { X86::MMX_PSUBWirr, X86::MMX_PSUBWirm, 0 },
1366 { X86::MMX_PUNPCKHBWirr, X86::MMX_PUNPCKHBWirm, 0 },
1367 { X86::MMX_PUNPCKHDQirr, X86::MMX_PUNPCKHDQirm, 0 },
1368 { X86::MMX_PUNPCKHWDirr, X86::MMX_PUNPCKHWDirm, 0 },
1369 { X86::MMX_PUNPCKLBWirr, X86::MMX_PUNPCKLBWirm, 0 },
1370 { X86::MMX_PUNPCKLDQirr, X86::MMX_PUNPCKLDQirm, 0 },
1371 { X86::MMX_PUNPCKLWDirr, X86::MMX_PUNPCKLWDirm, 0 },
1372 { X86::MMX_PXORirr, X86::MMX_PXORirm, 0 },
1373
1374 // 3DNow! version of foldable instructions
1375 { X86::PAVGUSBrr, X86::PAVGUSBrm, 0 },
1376 { X86::PFACCrr, X86::PFACCrm, 0 },
1377 { X86::PFADDrr, X86::PFADDrm, 0 },
1378 { X86::PFCMPEQrr, X86::PFCMPEQrm, 0 },
1379 { X86::PFCMPGErr, X86::PFCMPGErm, 0 },
1380 { X86::PFCMPGTrr, X86::PFCMPGTrm, 0 },
1381 { X86::PFMAXrr, X86::PFMAXrm, 0 },
1382 { X86::PFMINrr, X86::PFMINrm, 0 },
1383 { X86::PFMULrr, X86::PFMULrm, 0 },
1384 { X86::PFNACCrr, X86::PFNACCrm, 0 },
1385 { X86::PFPNACCrr, X86::PFPNACCrm, 0 },
1386 { X86::PFRCPIT1rr, X86::PFRCPIT1rm, 0 },
1387 { X86::PFRCPIT2rr, X86::PFRCPIT2rm, 0 },
1388 { X86::PFRSQIT1rr, X86::PFRSQIT1rm, 0 },
1389 { X86::PFSUBrr, X86::PFSUBrm, 0 },
1390 { X86::PFSUBRrr, X86::PFSUBRrm, 0 },
1391 { X86::PMULHRWrr, X86::PMULHRWrm, 0 },
1392
1393 // AVX 128-bit versions of foldable instructions
1394 { X86::VCVTSI2SD64rr, X86::VCVTSI2SD64rm, 0 },
1395 { X86::Int_VCVTSI2SD64rr, X86::Int_VCVTSI2SD64rm, 0 },
1396 { X86::VCVTSI2SDrr, X86::VCVTSI2SDrm, 0 },
1397 { X86::Int_VCVTSI2SDrr, X86::Int_VCVTSI2SDrm, 0 },
1398 { X86::VCVTSI2SS64rr, X86::VCVTSI2SS64rm, 0 },
1399 { X86::Int_VCVTSI2SS64rr, X86::Int_VCVTSI2SS64rm, 0 },
1400 { X86::VCVTSI2SSrr, X86::VCVTSI2SSrm, 0 },
1401 { X86::Int_VCVTSI2SSrr, X86::Int_VCVTSI2SSrm, 0 },
1402 { X86::VADDPDrr, X86::VADDPDrm, 0 },
1403 { X86::VADDPSrr, X86::VADDPSrm, 0 },
1404 { X86::VADDSDrr, X86::VADDSDrm, 0 },
1405 { X86::VADDSDrr_Int, X86::VADDSDrm_Int, TB_NO_REVERSE },
1406 { X86::VADDSSrr, X86::VADDSSrm, 0 },
1407 { X86::VADDSSrr_Int, X86::VADDSSrm_Int, TB_NO_REVERSE },
1408 { X86::VADDSUBPDrr, X86::VADDSUBPDrm, 0 },
1409 { X86::VADDSUBPSrr, X86::VADDSUBPSrm, 0 },
1410 { X86::VANDNPDrr, X86::VANDNPDrm, 0 },
1411 { X86::VANDNPSrr, X86::VANDNPSrm, 0 },
1412 { X86::VANDPDrr, X86::VANDPDrm, 0 },
1413 { X86::VANDPSrr, X86::VANDPSrm, 0 },
1414 { X86::VBLENDPDrri, X86::VBLENDPDrmi, 0 },
1415 { X86::VBLENDPSrri, X86::VBLENDPSrmi, 0 },
1416 { X86::VBLENDVPDrr, X86::VBLENDVPDrm, 0 },
1417 { X86::VBLENDVPSrr, X86::VBLENDVPSrm, 0 },
1418 { X86::VCMPPDrri, X86::VCMPPDrmi, 0 },
1419 { X86::VCMPPSrri, X86::VCMPPSrmi, 0 },
1420 { X86::VCMPSDrr, X86::VCMPSDrm, 0 },
1421 { X86::VCMPSSrr, X86::VCMPSSrm, 0 },
1422 { X86::VDIVPDrr, X86::VDIVPDrm, 0 },
1423 { X86::VDIVPSrr, X86::VDIVPSrm, 0 },
1424 { X86::VDIVSDrr, X86::VDIVSDrm, 0 },
1425 { X86::VDIVSDrr_Int, X86::VDIVSDrm_Int, TB_NO_REVERSE },
1426 { X86::VDIVSSrr, X86::VDIVSSrm, 0 },
1427 { X86::VDIVSSrr_Int, X86::VDIVSSrm_Int, TB_NO_REVERSE },
1428 { X86::VDPPDrri, X86::VDPPDrmi, 0 },
1429 { X86::VDPPSrri, X86::VDPPSrmi, 0 },
1430 { X86::VHADDPDrr, X86::VHADDPDrm, 0 },
1431 { X86::VHADDPSrr, X86::VHADDPSrm, 0 },
1432 { X86::VHSUBPDrr, X86::VHSUBPDrm, 0 },
1433 { X86::VHSUBPSrr, X86::VHSUBPSrm, 0 },
1434 { X86::Int_VCMPSDrr, X86::Int_VCMPSDrm, TB_NO_REVERSE },
1435 { X86::Int_VCMPSSrr, X86::Int_VCMPSSrm, TB_NO_REVERSE },
1436 { X86::VMAXCPDrr, X86::VMAXCPDrm, 0 },
1437 { X86::VMAXCPSrr, X86::VMAXCPSrm, 0 },
1438 { X86::VMAXCSDrr, X86::VMAXCSDrm, 0 },
1439 { X86::VMAXCSSrr, X86::VMAXCSSrm, 0 },
1440 { X86::VMAXPDrr, X86::VMAXPDrm, 0 },
1441 { X86::VMAXPSrr, X86::VMAXPSrm, 0 },
1442 { X86::VMAXSDrr, X86::VMAXSDrm, 0 },
1443 { X86::VMAXSDrr_Int, X86::VMAXSDrm_Int, TB_NO_REVERSE },
1444 { X86::VMAXSSrr, X86::VMAXSSrm, 0 },
1445 { X86::VMAXSSrr_Int, X86::VMAXSSrm_Int, TB_NO_REVERSE },
1446 { X86::VMINCPDrr, X86::VMINCPDrm, 0 },
1447 { X86::VMINCPSrr, X86::VMINCPSrm, 0 },
1448 { X86::VMINCSDrr, X86::VMINCSDrm, 0 },
1449 { X86::VMINCSSrr, X86::VMINCSSrm, 0 },
1450 { X86::VMINPDrr, X86::VMINPDrm, 0 },
1451 { X86::VMINPSrr, X86::VMINPSrm, 0 },
1452 { X86::VMINSDrr, X86::VMINSDrm, 0 },
1453 { X86::VMINSDrr_Int, X86::VMINSDrm_Int, TB_NO_REVERSE },
1454 { X86::VMINSSrr, X86::VMINSSrm, 0 },
1455 { X86::VMINSSrr_Int, X86::VMINSSrm_Int, TB_NO_REVERSE },
1456 { X86::VMOVLHPSrr, X86::VMOVHPSrm, TB_NO_REVERSE },
1457 { X86::VMPSADBWrri, X86::VMPSADBWrmi, 0 },
1458 { X86::VMULPDrr, X86::VMULPDrm, 0 },
1459 { X86::VMULPSrr, X86::VMULPSrm, 0 },
1460 { X86::VMULSDrr, X86::VMULSDrm, 0 },
1461 { X86::VMULSDrr_Int, X86::VMULSDrm_Int, TB_NO_REVERSE },
1462 { X86::VMULSSrr, X86::VMULSSrm, 0 },
1463 { X86::VMULSSrr_Int, X86::VMULSSrm_Int, TB_NO_REVERSE },
1464 { X86::VORPDrr, X86::VORPDrm, 0 },
1465 { X86::VORPSrr, X86::VORPSrm, 0 },
1466 { X86::VPACKSSDWrr, X86::VPACKSSDWrm, 0 },
1467 { X86::VPACKSSWBrr, X86::VPACKSSWBrm, 0 },
1468 { X86::VPACKUSDWrr, X86::VPACKUSDWrm, 0 },
1469 { X86::VPACKUSWBrr, X86::VPACKUSWBrm, 0 },
1470 { X86::VPADDBrr, X86::VPADDBrm, 0 },
1471 { X86::VPADDDrr, X86::VPADDDrm, 0 },
1472 { X86::VPADDQrr, X86::VPADDQrm, 0 },
1473 { X86::VPADDSBrr, X86::VPADDSBrm, 0 },
1474 { X86::VPADDSWrr, X86::VPADDSWrm, 0 },
1475 { X86::VPADDUSBrr, X86::VPADDUSBrm, 0 },
1476 { X86::VPADDUSWrr, X86::VPADDUSWrm, 0 },
1477 { X86::VPADDWrr, X86::VPADDWrm, 0 },
1478 { X86::VPALIGNRrri, X86::VPALIGNRrmi, 0 },
1479 { X86::VPANDNrr, X86::VPANDNrm, 0 },
1480 { X86::VPANDrr, X86::VPANDrm, 0 },
1481 { X86::VPAVGBrr, X86::VPAVGBrm, 0 },
1482 { X86::VPAVGWrr, X86::VPAVGWrm, 0 },
1483 { X86::VPBLENDVBrr, X86::VPBLENDVBrm, 0 },
1484 { X86::VPBLENDWrri, X86::VPBLENDWrmi, 0 },
1485 { X86::VPCLMULQDQrr, X86::VPCLMULQDQrm, 0 },
1486 { X86::VPCMPEQBrr, X86::VPCMPEQBrm, 0 },
1487 { X86::VPCMPEQDrr, X86::VPCMPEQDrm, 0 },
1488 { X86::VPCMPEQQrr, X86::VPCMPEQQrm, 0 },
1489 { X86::VPCMPEQWrr, X86::VPCMPEQWrm, 0 },
1490 { X86::VPCMPGTBrr, X86::VPCMPGTBrm, 0 },
1491 { X86::VPCMPGTDrr, X86::VPCMPGTDrm, 0 },
1492 { X86::VPCMPGTQrr, X86::VPCMPGTQrm, 0 },
1493 { X86::VPCMPGTWrr, X86::VPCMPGTWrm, 0 },
1494 { X86::VPHADDDrr, X86::VPHADDDrm, 0 },
1495 { X86::VPHADDSWrr128, X86::VPHADDSWrm128, 0 },
1496 { X86::VPHADDWrr, X86::VPHADDWrm, 0 },
1497 { X86::VPHSUBDrr, X86::VPHSUBDrm, 0 },
1498 { X86::VPHSUBSWrr128, X86::VPHSUBSWrm128, 0 },
1499 { X86::VPHSUBWrr, X86::VPHSUBWrm, 0 },
1500 { X86::VPERMILPDrr, X86::VPERMILPDrm, 0 },
1501 { X86::VPERMILPSrr, X86::VPERMILPSrm, 0 },
1502 { X86::VPINSRBrr, X86::VPINSRBrm, 0 },
1503 { X86::VPINSRDrr, X86::VPINSRDrm, 0 },
1504 { X86::VPINSRQrr, X86::VPINSRQrm, 0 },
1505 { X86::VPINSRWrri, X86::VPINSRWrmi, 0 },
1506 { X86::VPMADDUBSWrr, X86::VPMADDUBSWrm, 0 },
1507 { X86::VPMADDWDrr, X86::VPMADDWDrm, 0 },
1508 { X86::VPMAXSBrr, X86::VPMAXSBrm, 0 },
1509 { X86::VPMAXSDrr, X86::VPMAXSDrm, 0 },
1510 { X86::VPMAXSWrr, X86::VPMAXSWrm, 0 },
1511 { X86::VPMAXUBrr, X86::VPMAXUBrm, 0 },
1512 { X86::VPMAXUDrr, X86::VPMAXUDrm, 0 },
1513 { X86::VPMAXUWrr, X86::VPMAXUWrm, 0 },
1514 { X86::VPMINSBrr, X86::VPMINSBrm, 0 },
1515 { X86::VPMINSDrr, X86::VPMINSDrm, 0 },
1516 { X86::VPMINSWrr, X86::VPMINSWrm, 0 },
1517 { X86::VPMINUBrr, X86::VPMINUBrm, 0 },
1518 { X86::VPMINUDrr, X86::VPMINUDrm, 0 },
1519 { X86::VPMINUWrr, X86::VPMINUWrm, 0 },
1520 { X86::VPMULDQrr, X86::VPMULDQrm, 0 },
1521 { X86::VPMULHRSWrr, X86::VPMULHRSWrm, 0 },
1522 { X86::VPMULHUWrr, X86::VPMULHUWrm, 0 },
1523 { X86::VPMULHWrr, X86::VPMULHWrm, 0 },
1524 { X86::VPMULLDrr, X86::VPMULLDrm, 0 },
1525 { X86::VPMULLWrr, X86::VPMULLWrm, 0 },
1526 { X86::VPMULUDQrr, X86::VPMULUDQrm, 0 },
1527 { X86::VPORrr, X86::VPORrm, 0 },
1528 { X86::VPSADBWrr, X86::VPSADBWrm, 0 },
1529 { X86::VPSHUFBrr, X86::VPSHUFBrm, 0 },
1530 { X86::VPSIGNBrr128, X86::VPSIGNBrm128, 0 },
1531 { X86::VPSIGNWrr128, X86::VPSIGNWrm128, 0 },
1532 { X86::VPSIGNDrr128, X86::VPSIGNDrm128, 0 },
1533 { X86::VPSLLDrr, X86::VPSLLDrm, 0 },
1534 { X86::VPSLLQrr, X86::VPSLLQrm, 0 },
1535 { X86::VPSLLWrr, X86::VPSLLWrm, 0 },
1536 { X86::VPSRADrr, X86::VPSRADrm, 0 },
1537 { X86::VPSRAWrr, X86::VPSRAWrm, 0 },
1538 { X86::VPSRLDrr, X86::VPSRLDrm, 0 },
1539 { X86::VPSRLQrr, X86::VPSRLQrm, 0 },
1540 { X86::VPSRLWrr, X86::VPSRLWrm, 0 },
1541 { X86::VPSUBBrr, X86::VPSUBBrm, 0 },
1542 { X86::VPSUBDrr, X86::VPSUBDrm, 0 },
1543 { X86::VPSUBQrr, X86::VPSUBQrm, 0 },
1544 { X86::VPSUBSBrr, X86::VPSUBSBrm, 0 },
1545 { X86::VPSUBSWrr, X86::VPSUBSWrm, 0 },
1546 { X86::VPSUBUSBrr, X86::VPSUBUSBrm, 0 },
1547 { X86::VPSUBUSWrr, X86::VPSUBUSWrm, 0 },
1548 { X86::VPSUBWrr, X86::VPSUBWrm, 0 },
1549 { X86::VPUNPCKHBWrr, X86::VPUNPCKHBWrm, 0 },
1550 { X86::VPUNPCKHDQrr, X86::VPUNPCKHDQrm, 0 },
1551 { X86::VPUNPCKHQDQrr, X86::VPUNPCKHQDQrm, 0 },
1552 { X86::VPUNPCKHWDrr, X86::VPUNPCKHWDrm, 0 },
1553 { X86::VPUNPCKLBWrr, X86::VPUNPCKLBWrm, 0 },
1554 { X86::VPUNPCKLDQrr, X86::VPUNPCKLDQrm, 0 },
1555 { X86::VPUNPCKLQDQrr, X86::VPUNPCKLQDQrm, 0 },
1556 { X86::VPUNPCKLWDrr, X86::VPUNPCKLWDrm, 0 },
1557 { X86::VPXORrr, X86::VPXORrm, 0 },
1558 { X86::VRCPSSr, X86::VRCPSSm, 0 },
1559 { X86::VRCPSSr_Int, X86::VRCPSSm_Int, TB_NO_REVERSE },
1560 { X86::VRSQRTSSr, X86::VRSQRTSSm, 0 },
1561 { X86::VRSQRTSSr_Int, X86::VRSQRTSSm_Int, TB_NO_REVERSE },
1562 { X86::VROUNDSDr, X86::VROUNDSDm, 0 },
1563 { X86::VROUNDSDr_Int, X86::VROUNDSDm_Int, TB_NO_REVERSE },
1564 { X86::VROUNDSSr, X86::VROUNDSSm, 0 },
1565 { X86::VROUNDSSr_Int, X86::VROUNDSSm_Int, TB_NO_REVERSE },
1566 { X86::VSHUFPDrri, X86::VSHUFPDrmi, 0 },
1567 { X86::VSHUFPSrri, X86::VSHUFPSrmi, 0 },
1568 { X86::VSQRTSDr, X86::VSQRTSDm, 0 },
1569 { X86::VSQRTSDr_Int, X86::VSQRTSDm_Int, TB_NO_REVERSE },
1570 { X86::VSQRTSSr, X86::VSQRTSSm, 0 },
1571 { X86::VSQRTSSr_Int, X86::VSQRTSSm_Int, TB_NO_REVERSE },
1572 { X86::VSUBPDrr, X86::VSUBPDrm, 0 },
1573 { X86::VSUBPSrr, X86::VSUBPSrm, 0 },
1574 { X86::VSUBSDrr, X86::VSUBSDrm, 0 },
1575 { X86::VSUBSDrr_Int, X86::VSUBSDrm_Int, TB_NO_REVERSE },
1576 { X86::VSUBSSrr, X86::VSUBSSrm, 0 },
1577 { X86::VSUBSSrr_Int, X86::VSUBSSrm_Int, TB_NO_REVERSE },
1578 { X86::VUNPCKHPDrr, X86::VUNPCKHPDrm, 0 },
1579 { X86::VUNPCKHPSrr, X86::VUNPCKHPSrm, 0 },
1580 { X86::VUNPCKLPDrr, X86::VUNPCKLPDrm, 0 },
1581 { X86::VUNPCKLPSrr, X86::VUNPCKLPSrm, 0 },
1582 { X86::VXORPDrr, X86::VXORPDrm, 0 },
1583 { X86::VXORPSrr, X86::VXORPSrm, 0 },
1584
1585 // AVX 256-bit foldable instructions
1586 { X86::VADDPDYrr, X86::VADDPDYrm, 0 },
1587 { X86::VADDPSYrr, X86::VADDPSYrm, 0 },
1588 { X86::VADDSUBPDYrr, X86::VADDSUBPDYrm, 0 },
1589 { X86::VADDSUBPSYrr, X86::VADDSUBPSYrm, 0 },
1590 { X86::VANDNPDYrr, X86::VANDNPDYrm, 0 },
1591 { X86::VANDNPSYrr, X86::VANDNPSYrm, 0 },
1592 { X86::VANDPDYrr, X86::VANDPDYrm, 0 },
1593 { X86::VANDPSYrr, X86::VANDPSYrm, 0 },
1594 { X86::VBLENDPDYrri, X86::VBLENDPDYrmi, 0 },
1595 { X86::VBLENDPSYrri, X86::VBLENDPSYrmi, 0 },
1596 { X86::VBLENDVPDYrr, X86::VBLENDVPDYrm, 0 },
1597 { X86::VBLENDVPSYrr, X86::VBLENDVPSYrm, 0 },
1598 { X86::VCMPPDYrri, X86::VCMPPDYrmi, 0 },
1599 { X86::VCMPPSYrri, X86::VCMPPSYrmi, 0 },
1600 { X86::VDIVPDYrr, X86::VDIVPDYrm, 0 },
1601 { X86::VDIVPSYrr, X86::VDIVPSYrm, 0 },
1602 { X86::VDPPSYrri, X86::VDPPSYrmi, 0 },
1603 { X86::VHADDPDYrr, X86::VHADDPDYrm, 0 },
1604 { X86::VHADDPSYrr, X86::VHADDPSYrm, 0 },
1605 { X86::VHSUBPDYrr, X86::VHSUBPDYrm, 0 },
1606 { X86::VHSUBPSYrr, X86::VHSUBPSYrm, 0 },
1607 { X86::VINSERTF128rr, X86::VINSERTF128rm, 0 },
1608 { X86::VMAXCPDYrr, X86::VMAXCPDYrm, 0 },
1609 { X86::VMAXCPSYrr, X86::VMAXCPSYrm, 0 },
1610 { X86::VMAXPDYrr, X86::VMAXPDYrm, 0 },
1611 { X86::VMAXPSYrr, X86::VMAXPSYrm, 0 },
1612 { X86::VMINCPDYrr, X86::VMINCPDYrm, 0 },
1613 { X86::VMINCPSYrr, X86::VMINCPSYrm, 0 },
1614 { X86::VMINPDYrr, X86::VMINPDYrm, 0 },
1615 { X86::VMINPSYrr, X86::VMINPSYrm, 0 },
1616 { X86::VMULPDYrr, X86::VMULPDYrm, 0 },
1617 { X86::VMULPSYrr, X86::VMULPSYrm, 0 },
1618 { X86::VORPDYrr, X86::VORPDYrm, 0 },
1619 { X86::VORPSYrr, X86::VORPSYrm, 0 },
1620 { X86::VPERM2F128rr, X86::VPERM2F128rm, 0 },
1621 { X86::VPERMILPDYrr, X86::VPERMILPDYrm, 0 },
1622 { X86::VPERMILPSYrr, X86::VPERMILPSYrm, 0 },
1623 { X86::VSHUFPDYrri, X86::VSHUFPDYrmi, 0 },
1624 { X86::VSHUFPSYrri, X86::VSHUFPSYrmi, 0 },
1625 { X86::VSUBPDYrr, X86::VSUBPDYrm, 0 },
1626 { X86::VSUBPSYrr, X86::VSUBPSYrm, 0 },
1627 { X86::VUNPCKHPDYrr, X86::VUNPCKHPDYrm, 0 },
1628 { X86::VUNPCKHPSYrr, X86::VUNPCKHPSYrm, 0 },
1629 { X86::VUNPCKLPDYrr, X86::VUNPCKLPDYrm, 0 },
1630 { X86::VUNPCKLPSYrr, X86::VUNPCKLPSYrm, 0 },
1631 { X86::VXORPDYrr, X86::VXORPDYrm, 0 },
1632 { X86::VXORPSYrr, X86::VXORPSYrm, 0 },
1633
1634 // AVX2 foldable instructions
1635 { X86::VINSERTI128rr, X86::VINSERTI128rm, 0 },
1636 { X86::VPACKSSDWYrr, X86::VPACKSSDWYrm, 0 },
1637 { X86::VPACKSSWBYrr, X86::VPACKSSWBYrm, 0 },
1638 { X86::VPACKUSDWYrr, X86::VPACKUSDWYrm, 0 },
1639 { X86::VPACKUSWBYrr, X86::VPACKUSWBYrm, 0 },
1640 { X86::VPADDBYrr, X86::VPADDBYrm, 0 },
1641 { X86::VPADDDYrr, X86::VPADDDYrm, 0 },
1642 { X86::VPADDQYrr, X86::VPADDQYrm, 0 },
1643 { X86::VPADDSBYrr, X86::VPADDSBYrm, 0 },
1644 { X86::VPADDSWYrr, X86::VPADDSWYrm, 0 },
1645 { X86::VPADDUSBYrr, X86::VPADDUSBYrm, 0 },
1646 { X86::VPADDUSWYrr, X86::VPADDUSWYrm, 0 },
1647 { X86::VPADDWYrr, X86::VPADDWYrm, 0 },
1648 { X86::VPALIGNRYrri, X86::VPALIGNRYrmi, 0 },
1649 { X86::VPANDNYrr, X86::VPANDNYrm, 0 },
1650 { X86::VPANDYrr, X86::VPANDYrm, 0 },
1651 { X86::VPAVGBYrr, X86::VPAVGBYrm, 0 },
1652 { X86::VPAVGWYrr, X86::VPAVGWYrm, 0 },
1653 { X86::VPBLENDDrri, X86::VPBLENDDrmi, 0 },
1654 { X86::VPBLENDDYrri, X86::VPBLENDDYrmi, 0 },
1655 { X86::VPBLENDVBYrr, X86::VPBLENDVBYrm, 0 },
1656 { X86::VPBLENDWYrri, X86::VPBLENDWYrmi, 0 },
1657 { X86::VPCMPEQBYrr, X86::VPCMPEQBYrm, 0 },
1658 { X86::VPCMPEQDYrr, X86::VPCMPEQDYrm, 0 },
1659 { X86::VPCMPEQQYrr, X86::VPCMPEQQYrm, 0 },
1660 { X86::VPCMPEQWYrr, X86::VPCMPEQWYrm, 0 },
1661 { X86::VPCMPGTBYrr, X86::VPCMPGTBYrm, 0 },
1662 { X86::VPCMPGTDYrr, X86::VPCMPGTDYrm, 0 },
1663 { X86::VPCMPGTQYrr, X86::VPCMPGTQYrm, 0 },
1664 { X86::VPCMPGTWYrr, X86::VPCMPGTWYrm, 0 },
1665 { X86::VPERM2I128rr, X86::VPERM2I128rm, 0 },
1666 { X86::VPERMDYrr, X86::VPERMDYrm, 0 },
1667 { X86::VPERMPSYrr, X86::VPERMPSYrm, 0 },
1668 { X86::VPHADDDYrr, X86::VPHADDDYrm, 0 },
1669 { X86::VPHADDSWrr256, X86::VPHADDSWrm256, 0 },
1670 { X86::VPHADDWYrr, X86::VPHADDWYrm, 0 },
1671 { X86::VPHSUBDYrr, X86::VPHSUBDYrm, 0 },
1672 { X86::VPHSUBSWrr256, X86::VPHSUBSWrm256, 0 },
1673 { X86::VPHSUBWYrr, X86::VPHSUBWYrm, 0 },
1674 { X86::VPMADDUBSWYrr, X86::VPMADDUBSWYrm, 0 },
1675 { X86::VPMADDWDYrr, X86::VPMADDWDYrm, 0 },
1676 { X86::VPMAXSBYrr, X86::VPMAXSBYrm, 0 },
1677 { X86::VPMAXSDYrr, X86::VPMAXSDYrm, 0 },
1678 { X86::VPMAXSWYrr, X86::VPMAXSWYrm, 0 },
1679 { X86::VPMAXUBYrr, X86::VPMAXUBYrm, 0 },
1680 { X86::VPMAXUDYrr, X86::VPMAXUDYrm, 0 },
1681 { X86::VPMAXUWYrr, X86::VPMAXUWYrm, 0 },
1682 { X86::VPMINSBYrr, X86::VPMINSBYrm, 0 },
1683 { X86::VPMINSDYrr, X86::VPMINSDYrm, 0 },
1684 { X86::VPMINSWYrr, X86::VPMINSWYrm, 0 },
1685 { X86::VPMINUBYrr, X86::VPMINUBYrm, 0 },
1686 { X86::VPMINUDYrr, X86::VPMINUDYrm, 0 },
1687 { X86::VPMINUWYrr, X86::VPMINUWYrm, 0 },
1688 { X86::VMPSADBWYrri, X86::VMPSADBWYrmi, 0 },
1689 { X86::VPMULDQYrr, X86::VPMULDQYrm, 0 },
1690 { X86::VPMULHRSWYrr, X86::VPMULHRSWYrm, 0 },
1691 { X86::VPMULHUWYrr, X86::VPMULHUWYrm, 0 },
1692 { X86::VPMULHWYrr, X86::VPMULHWYrm, 0 },
1693 { X86::VPMULLDYrr, X86::VPMULLDYrm, 0 },
1694 { X86::VPMULLWYrr, X86::VPMULLWYrm, 0 },
1695 { X86::VPMULUDQYrr, X86::VPMULUDQYrm, 0 },
1696 { X86::VPORYrr, X86::VPORYrm, 0 },
1697 { X86::VPSADBWYrr, X86::VPSADBWYrm, 0 },
1698 { X86::VPSHUFBYrr, X86::VPSHUFBYrm, 0 },
1699 { X86::VPSIGNBYrr256, X86::VPSIGNBYrm256, 0 },
1700 { X86::VPSIGNWYrr256, X86::VPSIGNWYrm256, 0 },
1701 { X86::VPSIGNDYrr256, X86::VPSIGNDYrm256, 0 },
1702 { X86::VPSLLDYrr, X86::VPSLLDYrm, 0 },
1703 { X86::VPSLLQYrr, X86::VPSLLQYrm, 0 },
1704 { X86::VPSLLWYrr, X86::VPSLLWYrm, 0 },
1705 { X86::VPSLLVDrr, X86::VPSLLVDrm, 0 },
1706 { X86::VPSLLVDYrr, X86::VPSLLVDYrm, 0 },
1707 { X86::VPSLLVQrr, X86::VPSLLVQrm, 0 },
1708 { X86::VPSLLVQYrr, X86::VPSLLVQYrm, 0 },
1709 { X86::VPSRADYrr, X86::VPSRADYrm, 0 },
1710 { X86::VPSRAWYrr, X86::VPSRAWYrm, 0 },
1711 { X86::VPSRAVDrr, X86::VPSRAVDrm, 0 },
1712 { X86::VPSRAVDYrr, X86::VPSRAVDYrm, 0 },
1713 { X86::VPSRLDYrr, X86::VPSRLDYrm, 0 },
1714 { X86::VPSRLQYrr, X86::VPSRLQYrm, 0 },
1715 { X86::VPSRLWYrr, X86::VPSRLWYrm, 0 },
1716 { X86::VPSRLVDrr, X86::VPSRLVDrm, 0 },
1717 { X86::VPSRLVDYrr, X86::VPSRLVDYrm, 0 },
1718 { X86::VPSRLVQrr, X86::VPSRLVQrm, 0 },
1719 { X86::VPSRLVQYrr, X86::VPSRLVQYrm, 0 },
1720 { X86::VPSUBBYrr, X86::VPSUBBYrm, 0 },
1721 { X86::VPSUBDYrr, X86::VPSUBDYrm, 0 },
1722 { X86::VPSUBQYrr, X86::VPSUBQYrm, 0 },
1723 { X86::VPSUBSBYrr, X86::VPSUBSBYrm, 0 },
1724 { X86::VPSUBSWYrr, X86::VPSUBSWYrm, 0 },
1725 { X86::VPSUBUSBYrr, X86::VPSUBUSBYrm, 0 },
1726 { X86::VPSUBUSWYrr, X86::VPSUBUSWYrm, 0 },
1727 { X86::VPSUBWYrr, X86::VPSUBWYrm, 0 },
1728 { X86::VPUNPCKHBWYrr, X86::VPUNPCKHBWYrm, 0 },
1729 { X86::VPUNPCKHDQYrr, X86::VPUNPCKHDQYrm, 0 },
1730 { X86::VPUNPCKHQDQYrr, X86::VPUNPCKHQDQYrm, 0 },
1731 { X86::VPUNPCKHWDYrr, X86::VPUNPCKHWDYrm, 0 },
1732 { X86::VPUNPCKLBWYrr, X86::VPUNPCKLBWYrm, 0 },
1733 { X86::VPUNPCKLDQYrr, X86::VPUNPCKLDQYrm, 0 },
1734 { X86::VPUNPCKLQDQYrr, X86::VPUNPCKLQDQYrm, 0 },
1735 { X86::VPUNPCKLWDYrr, X86::VPUNPCKLWDYrm, 0 },
1736 { X86::VPXORYrr, X86::VPXORYrm, 0 },
1737
1738 // FMA4 foldable patterns
1739 { X86::VFMADDSS4rr, X86::VFMADDSS4mr, TB_ALIGN_NONE },
1740 { X86::VFMADDSS4rr_Int, X86::VFMADDSS4mr_Int, TB_NO_REVERSE },
1741 { X86::VFMADDSD4rr, X86::VFMADDSD4mr, TB_ALIGN_NONE },
1742 { X86::VFMADDSD4rr_Int, X86::VFMADDSD4mr_Int, TB_NO_REVERSE },
1743 { X86::VFMADDPS4rr, X86::VFMADDPS4mr, TB_ALIGN_NONE },
1744 { X86::VFMADDPD4rr, X86::VFMADDPD4mr, TB_ALIGN_NONE },
1745 { X86::VFMADDPS4Yrr, X86::VFMADDPS4Ymr, TB_ALIGN_NONE },
1746 { X86::VFMADDPD4Yrr, X86::VFMADDPD4Ymr, TB_ALIGN_NONE },
1747 { X86::VFNMADDSS4rr, X86::VFNMADDSS4mr, TB_ALIGN_NONE },
1748 { X86::VFNMADDSS4rr_Int, X86::VFNMADDSS4mr_Int, TB_NO_REVERSE },
1749 { X86::VFNMADDSD4rr, X86::VFNMADDSD4mr, TB_ALIGN_NONE },
1750 { X86::VFNMADDSD4rr_Int, X86::VFNMADDSD4mr_Int, TB_NO_REVERSE },
1751 { X86::VFNMADDPS4rr, X86::VFNMADDPS4mr, TB_ALIGN_NONE },
1752 { X86::VFNMADDPD4rr, X86::VFNMADDPD4mr, TB_ALIGN_NONE },
1753 { X86::VFNMADDPS4Yrr, X86::VFNMADDPS4Ymr, TB_ALIGN_NONE },
1754 { X86::VFNMADDPD4Yrr, X86::VFNMADDPD4Ymr, TB_ALIGN_NONE },
1755 { X86::VFMSUBSS4rr, X86::VFMSUBSS4mr, TB_ALIGN_NONE },
1756 { X86::VFMSUBSS4rr_Int, X86::VFMSUBSS4mr_Int, TB_NO_REVERSE },
1757 { X86::VFMSUBSD4rr, X86::VFMSUBSD4mr, TB_ALIGN_NONE },
1758 { X86::VFMSUBSD4rr_Int, X86::VFMSUBSD4mr_Int, TB_NO_REVERSE },
1759 { X86::VFMSUBPS4rr, X86::VFMSUBPS4mr, TB_ALIGN_NONE },
1760 { X86::VFMSUBPD4rr, X86::VFMSUBPD4mr, TB_ALIGN_NONE },
1761 { X86::VFMSUBPS4Yrr, X86::VFMSUBPS4Ymr, TB_ALIGN_NONE },
1762 { X86::VFMSUBPD4Yrr, X86::VFMSUBPD4Ymr, TB_ALIGN_NONE },
1763 { X86::VFNMSUBSS4rr, X86::VFNMSUBSS4mr, TB_ALIGN_NONE },
1764 { X86::VFNMSUBSS4rr_Int, X86::VFNMSUBSS4mr_Int, TB_NO_REVERSE },
1765 { X86::VFNMSUBSD4rr, X86::VFNMSUBSD4mr, TB_ALIGN_NONE },
1766 { X86::VFNMSUBSD4rr_Int, X86::VFNMSUBSD4mr_Int, TB_NO_REVERSE },
1767 { X86::VFNMSUBPS4rr, X86::VFNMSUBPS4mr, TB_ALIGN_NONE },
1768 { X86::VFNMSUBPD4rr, X86::VFNMSUBPD4mr, TB_ALIGN_NONE },
1769 { X86::VFNMSUBPS4Yrr, X86::VFNMSUBPS4Ymr, TB_ALIGN_NONE },
1770 { X86::VFNMSUBPD4Yrr, X86::VFNMSUBPD4Ymr, TB_ALIGN_NONE },
1771 { X86::VFMADDSUBPS4rr, X86::VFMADDSUBPS4mr, TB_ALIGN_NONE },
1772 { X86::VFMADDSUBPD4rr, X86::VFMADDSUBPD4mr, TB_ALIGN_NONE },
1773 { X86::VFMADDSUBPS4Yrr, X86::VFMADDSUBPS4Ymr, TB_ALIGN_NONE },
1774 { X86::VFMADDSUBPD4Yrr, X86::VFMADDSUBPD4Ymr, TB_ALIGN_NONE },
1775 { X86::VFMSUBADDPS4rr, X86::VFMSUBADDPS4mr, TB_ALIGN_NONE },
1776 { X86::VFMSUBADDPD4rr, X86::VFMSUBADDPD4mr, TB_ALIGN_NONE },
1777 { X86::VFMSUBADDPS4Yrr, X86::VFMSUBADDPS4Ymr, TB_ALIGN_NONE },
1778 { X86::VFMSUBADDPD4Yrr, X86::VFMSUBADDPD4Ymr, TB_ALIGN_NONE },
1779
1780 // XOP foldable instructions
1781 { X86::VPCMOVrrr, X86::VPCMOVrmr, 0 },
1782 { X86::VPCMOVYrrr, X86::VPCMOVYrmr, 0 },
1783 { X86::VPCOMBri, X86::VPCOMBmi, 0 },
1784 { X86::VPCOMDri, X86::VPCOMDmi, 0 },
1785 { X86::VPCOMQri, X86::VPCOMQmi, 0 },
1786 { X86::VPCOMWri, X86::VPCOMWmi, 0 },
1787 { X86::VPCOMUBri, X86::VPCOMUBmi, 0 },
1788 { X86::VPCOMUDri, X86::VPCOMUDmi, 0 },
1789 { X86::VPCOMUQri, X86::VPCOMUQmi, 0 },
1790 { X86::VPCOMUWri, X86::VPCOMUWmi, 0 },
1791 { X86::VPERMIL2PDrr, X86::VPERMIL2PDmr, 0 },
1792 { X86::VPERMIL2PDYrr, X86::VPERMIL2PDYmr, 0 },
1793 { X86::VPERMIL2PSrr, X86::VPERMIL2PSmr, 0 },
1794 { X86::VPERMIL2PSYrr, X86::VPERMIL2PSYmr, 0 },
1795 { X86::VPMACSDDrr, X86::VPMACSDDrm, 0 },
1796 { X86::VPMACSDQHrr, X86::VPMACSDQHrm, 0 },
1797 { X86::VPMACSDQLrr, X86::VPMACSDQLrm, 0 },
1798 { X86::VPMACSSDDrr, X86::VPMACSSDDrm, 0 },
1799 { X86::VPMACSSDQHrr, X86::VPMACSSDQHrm, 0 },
1800 { X86::VPMACSSDQLrr, X86::VPMACSSDQLrm, 0 },
1801 { X86::VPMACSSWDrr, X86::VPMACSSWDrm, 0 },
1802 { X86::VPMACSSWWrr, X86::VPMACSSWWrm, 0 },
1803 { X86::VPMACSWDrr, X86::VPMACSWDrm, 0 },
1804 { X86::VPMACSWWrr, X86::VPMACSWWrm, 0 },
1805 { X86::VPMADCSSWDrr, X86::VPMADCSSWDrm, 0 },
1806 { X86::VPMADCSWDrr, X86::VPMADCSWDrm, 0 },
1807 { X86::VPPERMrrr, X86::VPPERMrmr, 0 },
1808 { X86::VPROTBrr, X86::VPROTBrm, 0 },
1809 { X86::VPROTDrr, X86::VPROTDrm, 0 },
1810 { X86::VPROTQrr, X86::VPROTQrm, 0 },
1811 { X86::VPROTWrr, X86::VPROTWrm, 0 },
1812 { X86::VPSHABrr, X86::VPSHABrm, 0 },
1813 { X86::VPSHADrr, X86::VPSHADrm, 0 },
1814 { X86::VPSHAQrr, X86::VPSHAQrm, 0 },
1815 { X86::VPSHAWrr, X86::VPSHAWrm, 0 },
1816 { X86::VPSHLBrr, X86::VPSHLBrm, 0 },
1817 { X86::VPSHLDrr, X86::VPSHLDrm, 0 },
1818 { X86::VPSHLQrr, X86::VPSHLQrm, 0 },
1819 { X86::VPSHLWrr, X86::VPSHLWrm, 0 },
1820
1821 // BMI/BMI2 foldable instructions
1822 { X86::ANDN32rr, X86::ANDN32rm, 0 },
1823 { X86::ANDN64rr, X86::ANDN64rm, 0 },
1824 { X86::MULX32rr, X86::MULX32rm, 0 },
1825 { X86::MULX64rr, X86::MULX64rm, 0 },
1826 { X86::PDEP32rr, X86::PDEP32rm, 0 },
1827 { X86::PDEP64rr, X86::PDEP64rm, 0 },
1828 { X86::PEXT32rr, X86::PEXT32rm, 0 },
1829 { X86::PEXT64rr, X86::PEXT64rm, 0 },
1830
1831 // ADX foldable instructions
1832 { X86::ADCX32rr, X86::ADCX32rm, 0 },
1833 { X86::ADCX64rr, X86::ADCX64rm, 0 },
1834 { X86::ADOX32rr, X86::ADOX32rm, 0 },
1835 { X86::ADOX64rr, X86::ADOX64rm, 0 },
1836
1837 // AVX-512 foldable instructions
1838 { X86::VADDPDZrr, X86::VADDPDZrm, 0 },
1839 { X86::VADDPSZrr, X86::VADDPSZrm, 0 },
1840 { X86::VADDSDZrr, X86::VADDSDZrm, 0 },
1841 { X86::VADDSDZrr_Int, X86::VADDSDZrm_Int, TB_NO_REVERSE },
1842 { X86::VADDSSZrr, X86::VADDSSZrm, 0 },
1843 { X86::VADDSSZrr_Int, X86::VADDSSZrm_Int, TB_NO_REVERSE },
1844 { X86::VALIGNDZrri, X86::VALIGNDZrmi, 0 },
1845 { X86::VALIGNQZrri, X86::VALIGNQZrmi, 0 },
1846 { X86::VANDNPDZrr, X86::VANDNPDZrm, 0 },
1847 { X86::VANDNPSZrr, X86::VANDNPSZrm, 0 },
1848 { X86::VANDPDZrr, X86::VANDPDZrm, 0 },
1849 { X86::VANDPSZrr, X86::VANDPSZrm, 0 },
1850 { X86::VCMPPDZrri, X86::VCMPPDZrmi, 0 },
1851 { X86::VCMPPSZrri, X86::VCMPPSZrmi, 0 },
1852 { X86::VCMPSDZrr, X86::VCMPSDZrm, 0 },
1853 { X86::VCMPSDZrr_Int, X86::VCMPSDZrm_Int, TB_NO_REVERSE },
1854 { X86::VCMPSSZrr, X86::VCMPSSZrm, 0 },
1855 { X86::VCMPSSZrr_Int, X86::VCMPSSZrm_Int, TB_NO_REVERSE },
1856 { X86::VDIVPDZrr, X86::VDIVPDZrm, 0 },
1857 { X86::VDIVPSZrr, X86::VDIVPSZrm, 0 },
1858 { X86::VDIVSDZrr, X86::VDIVSDZrm, 0 },
1859 { X86::VDIVSDZrr_Int, X86::VDIVSDZrm_Int, TB_NO_REVERSE },
1860 { X86::VDIVSSZrr, X86::VDIVSSZrm, 0 },
1861 { X86::VDIVSSZrr_Int, X86::VDIVSSZrm_Int, TB_NO_REVERSE },
1862 { X86::VINSERTF32x4Zrr, X86::VINSERTF32x4Zrm, 0 },
1863 { X86::VINSERTF32x8Zrr, X86::VINSERTF32x8Zrm, 0 },
1864 { X86::VINSERTF64x2Zrr, X86::VINSERTF64x2Zrm, 0 },
1865 { X86::VINSERTF64x4Zrr, X86::VINSERTF64x4Zrm, 0 },
1866 { X86::VINSERTI32x4Zrr, X86::VINSERTI32x4Zrm, 0 },
1867 { X86::VINSERTI32x8Zrr, X86::VINSERTI32x8Zrm, 0 },
1868 { X86::VINSERTI64x2Zrr, X86::VINSERTI64x2Zrm, 0 },
1869 { X86::VINSERTI64x4Zrr, X86::VINSERTI64x4Zrm, 0 },
1870 { X86::VMAXCPDZrr, X86::VMAXCPDZrm, 0 },
1871 { X86::VMAXCPSZrr, X86::VMAXCPSZrm, 0 },
1872 { X86::VMAXCSDZrr, X86::VMAXCSDZrm, 0 },
1873 { X86::VMAXCSSZrr, X86::VMAXCSSZrm, 0 },
1874 { X86::VMAXPDZrr, X86::VMAXPDZrm, 0 },
1875 { X86::VMAXPSZrr, X86::VMAXPSZrm, 0 },
1876 { X86::VMAXSDZrr, X86::VMAXSDZrm, 0 },
1877 { X86::VMAXSDZrr_Int, X86::VMAXSDZrm_Int, TB_NO_REVERSE },
1878 { X86::VMAXSSZrr, X86::VMAXSSZrm, 0 },
1879 { X86::VMAXSSZrr_Int, X86::VMAXSSZrm_Int, TB_NO_REVERSE },
1880 { X86::VMINCPDZrr, X86::VMINCPDZrm, 0 },
1881 { X86::VMINCPSZrr, X86::VMINCPSZrm, 0 },
1882 { X86::VMINCSDZrr, X86::VMINCSDZrm, 0 },
1883 { X86::VMINCSSZrr, X86::VMINCSSZrm, 0 },
1884 { X86::VMINPDZrr, X86::VMINPDZrm, 0 },
1885 { X86::VMINPSZrr, X86::VMINPSZrm, 0 },
1886 { X86::VMINSDZrr, X86::VMINSDZrm, 0 },
1887 { X86::VMINSDZrr_Int, X86::VMINSDZrm_Int, TB_NO_REVERSE },
1888 { X86::VMINSSZrr, X86::VMINSSZrm, 0 },
1889 { X86::VMINSSZrr_Int, X86::VMINSSZrm_Int, TB_NO_REVERSE },
1890 { X86::VMOVLHPSZrr, X86::VMOVHPSZ128rm, TB_NO_REVERSE },
1891 { X86::VMULPDZrr, X86::VMULPDZrm, 0 },
1892 { X86::VMULPSZrr, X86::VMULPSZrm, 0 },
1893 { X86::VMULSDZrr, X86::VMULSDZrm, 0 },
1894 { X86::VMULSDZrr_Int, X86::VMULSDZrm_Int, TB_NO_REVERSE },
1895 { X86::VMULSSZrr, X86::VMULSSZrm, 0 },
1896 { X86::VMULSSZrr_Int, X86::VMULSSZrm_Int, TB_NO_REVERSE },
1897 { X86::VORPDZrr, X86::VORPDZrm, 0 },
1898 { X86::VORPSZrr, X86::VORPSZrm, 0 },
1899 { X86::VPACKSSDWZrr, X86::VPACKSSDWZrm, 0 },
1900 { X86::VPACKSSWBZrr, X86::VPACKSSWBZrm, 0 },
1901 { X86::VPACKUSDWZrr, X86::VPACKUSDWZrm, 0 },
1902 { X86::VPACKUSWBZrr, X86::VPACKUSWBZrm, 0 },
1903 { X86::VPADDBZrr, X86::VPADDBZrm, 0 },
1904 { X86::VPADDDZrr, X86::VPADDDZrm, 0 },
1905 { X86::VPADDQZrr, X86::VPADDQZrm, 0 },
1906 { X86::VPADDSBZrr, X86::VPADDSBZrm, 0 },
1907 { X86::VPADDSWZrr, X86::VPADDSWZrm, 0 },
1908 { X86::VPADDUSBZrr, X86::VPADDUSBZrm, 0 },
1909 { X86::VPADDUSWZrr, X86::VPADDUSWZrm, 0 },
1910 { X86::VPADDWZrr, X86::VPADDWZrm, 0 },
1911 { X86::VPALIGNRZrri, X86::VPALIGNRZrmi, 0 },
1912 { X86::VPANDDZrr, X86::VPANDDZrm, 0 },
1913 { X86::VPANDNDZrr, X86::VPANDNDZrm, 0 },
1914 { X86::VPANDNQZrr, X86::VPANDNQZrm, 0 },
1915 { X86::VPANDQZrr, X86::VPANDQZrm, 0 },
1916 { X86::VPAVGBZrr, X86::VPAVGBZrm, 0 },
1917 { X86::VPAVGWZrr, X86::VPAVGWZrm, 0 },
1918 { X86::VPCMPBZrri, X86::VPCMPBZrmi, 0 },
1919 { X86::VPCMPDZrri, X86::VPCMPDZrmi, 0 },
1920 { X86::VPCMPEQBZrr, X86::VPCMPEQBZrm, 0 },
1921 { X86::VPCMPEQDZrr, X86::VPCMPEQDZrm, 0 },
1922 { X86::VPCMPEQQZrr, X86::VPCMPEQQZrm, 0 },
1923 { X86::VPCMPEQWZrr, X86::VPCMPEQWZrm, 0 },
1924 { X86::VPCMPGTBZrr, X86::VPCMPGTBZrm, 0 },
1925 { X86::VPCMPGTDZrr, X86::VPCMPGTDZrm, 0 },
1926 { X86::VPCMPGTQZrr, X86::VPCMPGTQZrm, 0 },
1927 { X86::VPCMPGTWZrr, X86::VPCMPGTWZrm, 0 },
1928 { X86::VPCMPQZrri, X86::VPCMPQZrmi, 0 },
1929 { X86::VPCMPUBZrri, X86::VPCMPUBZrmi, 0 },
1930 { X86::VPCMPUDZrri, X86::VPCMPUDZrmi, 0 },
1931 { X86::VPCMPUQZrri, X86::VPCMPUQZrmi, 0 },
1932 { X86::VPCMPUWZrri, X86::VPCMPUWZrmi, 0 },
1933 { X86::VPCMPWZrri, X86::VPCMPWZrmi, 0 },
1934 { X86::VPERMBZrr, X86::VPERMBZrm, 0 },
1935 { X86::VPERMDZrr, X86::VPERMDZrm, 0 },
1936 { X86::VPERMILPDZrr, X86::VPERMILPDZrm, 0 },
1937 { X86::VPERMILPSZrr, X86::VPERMILPSZrm, 0 },
1938 { X86::VPERMPDZrr, X86::VPERMPDZrm, 0 },
1939 { X86::VPERMPSZrr, X86::VPERMPSZrm, 0 },
1940 { X86::VPERMQZrr, X86::VPERMQZrm, 0 },
1941 { X86::VPERMWZrr, X86::VPERMWZrm, 0 },
1942 { X86::VPINSRBZrr, X86::VPINSRBZrm, 0 },
1943 { X86::VPINSRDZrr, X86::VPINSRDZrm, 0 },
1944 { X86::VPINSRQZrr, X86::VPINSRQZrm, 0 },
1945 { X86::VPINSRWZrr, X86::VPINSRWZrm, 0 },
1946 { X86::VPMADDUBSWZrr, X86::VPMADDUBSWZrm, 0 },
1947 { X86::VPMADDWDZrr, X86::VPMADDWDZrm, 0 },
1948 { X86::VPMAXSBZrr, X86::VPMAXSBZrm, 0 },
1949 { X86::VPMAXSDZrr, X86::VPMAXSDZrm, 0 },
1950 { X86::VPMAXSQZrr, X86::VPMAXSQZrm, 0 },
1951 { X86::VPMAXSWZrr, X86::VPMAXSWZrm, 0 },
1952 { X86::VPMAXUBZrr, X86::VPMAXUBZrm, 0 },
1953 { X86::VPMAXUDZrr, X86::VPMAXUDZrm, 0 },
1954 { X86::VPMAXUQZrr, X86::VPMAXUQZrm, 0 },
1955 { X86::VPMAXUWZrr, X86::VPMAXUWZrm, 0 },
1956 { X86::VPMINSBZrr, X86::VPMINSBZrm, 0 },
1957 { X86::VPMINSDZrr, X86::VPMINSDZrm, 0 },
1958 { X86::VPMINSQZrr, X86::VPMINSQZrm, 0 },
1959 { X86::VPMINSWZrr, X86::VPMINSWZrm, 0 },
1960 { X86::VPMINUBZrr, X86::VPMINUBZrm, 0 },
1961 { X86::VPMINUDZrr, X86::VPMINUDZrm, 0 },
1962 { X86::VPMINUQZrr, X86::VPMINUQZrm, 0 },
1963 { X86::VPMINUWZrr, X86::VPMINUWZrm, 0 },
1964 { X86::VPMULDQZrr, X86::VPMULDQZrm, 0 },
1965 { X86::VPMULLDZrr, X86::VPMULLDZrm, 0 },
1966 { X86::VPMULLQZrr, X86::VPMULLQZrm, 0 },
1967 { X86::VPMULLWZrr, X86::VPMULLWZrm, 0 },
1968 { X86::VPMULUDQZrr, X86::VPMULUDQZrm, 0 },
1969 { X86::VPORDZrr, X86::VPORDZrm, 0 },
1970 { X86::VPORQZrr, X86::VPORQZrm, 0 },
1971 { X86::VPSADBWZ512rr, X86::VPSADBWZ512rm, 0 },
1972 { X86::VPSHUFBZrr, X86::VPSHUFBZrm, 0 },
1973 { X86::VPSLLDZrr, X86::VPSLLDZrm, 0 },
1974 { X86::VPSLLQZrr, X86::VPSLLQZrm, 0 },
1975 { X86::VPSLLVDZrr, X86::VPSLLVDZrm, 0 },
1976 { X86::VPSLLVQZrr, X86::VPSLLVQZrm, 0 },
1977 { X86::VPSLLVWZrr, X86::VPSLLVWZrm, 0 },
1978 { X86::VPSLLWZrr, X86::VPSLLWZrm, 0 },
1979 { X86::VPSRADZrr, X86::VPSRADZrm, 0 },
1980 { X86::VPSRAQZrr, X86::VPSRAQZrm, 0 },
1981 { X86::VPSRAVDZrr, X86::VPSRAVDZrm, 0 },
1982 { X86::VPSRAVQZrr, X86::VPSRAVQZrm, 0 },
1983 { X86::VPSRAVWZrr, X86::VPSRAVWZrm, 0 },
1984 { X86::VPSRAWZrr, X86::VPSRAWZrm, 0 },
1985 { X86::VPSRLDZrr, X86::VPSRLDZrm, 0 },
1986 { X86::VPSRLQZrr, X86::VPSRLQZrm, 0 },
1987 { X86::VPSRLVDZrr, X86::VPSRLVDZrm, 0 },
1988 { X86::VPSRLVQZrr, X86::VPSRLVQZrm, 0 },
1989 { X86::VPSRLVWZrr, X86::VPSRLVWZrm, 0 },
1990 { X86::VPSRLWZrr, X86::VPSRLWZrm, 0 },
1991 { X86::VPSUBBZrr, X86::VPSUBBZrm, 0 },
1992 { X86::VPSUBDZrr, X86::VPSUBDZrm, 0 },
1993 { X86::VPSUBQZrr, X86::VPSUBQZrm, 0 },
1994 { X86::VPSUBSBZrr, X86::VPSUBSBZrm, 0 },
1995 { X86::VPSUBSWZrr, X86::VPSUBSWZrm, 0 },
1996 { X86::VPSUBUSBZrr, X86::VPSUBUSBZrm, 0 },
1997 { X86::VPSUBUSWZrr, X86::VPSUBUSWZrm, 0 },
1998 { X86::VPSUBWZrr, X86::VPSUBWZrm, 0 },
1999 { X86::VPUNPCKHBWZrr, X86::VPUNPCKHBWZrm, 0 },
2000 { X86::VPUNPCKHDQZrr, X86::VPUNPCKHDQZrm, 0 },
2001 { X86::VPUNPCKHQDQZrr, X86::VPUNPCKHQDQZrm, 0 },
2002 { X86::VPUNPCKHWDZrr, X86::VPUNPCKHWDZrm, 0 },
2003 { X86::VPUNPCKLBWZrr, X86::VPUNPCKLBWZrm, 0 },
2004 { X86::VPUNPCKLDQZrr, X86::VPUNPCKLDQZrm, 0 },
2005 { X86::VPUNPCKLQDQZrr, X86::VPUNPCKLQDQZrm, 0 },
2006 { X86::VPUNPCKLWDZrr, X86::VPUNPCKLWDZrm, 0 },
2007 { X86::VPXORDZrr, X86::VPXORDZrm, 0 },
2008 { X86::VPXORQZrr, X86::VPXORQZrm, 0 },
2009 { X86::VSHUFPDZrri, X86::VSHUFPDZrmi, 0 },
2010 { X86::VSHUFPSZrri, X86::VSHUFPSZrmi, 0 },
2011 { X86::VSUBPDZrr, X86::VSUBPDZrm, 0 },
2012 { X86::VSUBPSZrr, X86::VSUBPSZrm, 0 },
2013 { X86::VSUBSDZrr, X86::VSUBSDZrm, 0 },
2014 { X86::VSUBSDZrr_Int, X86::VSUBSDZrm_Int, TB_NO_REVERSE },
2015 { X86::VSUBSSZrr, X86::VSUBSSZrm, 0 },
2016 { X86::VSUBSSZrr_Int, X86::VSUBSSZrm_Int, TB_NO_REVERSE },
2017 { X86::VUNPCKHPDZrr, X86::VUNPCKHPDZrm, 0 },
2018 { X86::VUNPCKHPSZrr, X86::VUNPCKHPSZrm, 0 },
2019 { X86::VUNPCKLPDZrr, X86::VUNPCKLPDZrm, 0 },
2020 { X86::VUNPCKLPSZrr, X86::VUNPCKLPSZrm, 0 },
2021 { X86::VXORPDZrr, X86::VXORPDZrm, 0 },
2022 { X86::VXORPSZrr, X86::VXORPSZrm, 0 },
2023
2024 // AVX-512{F,VL} foldable instructions
2025 { X86::VADDPDZ128rr, X86::VADDPDZ128rm, 0 },
2026 { X86::VADDPDZ256rr, X86::VADDPDZ256rm, 0 },
2027 { X86::VADDPSZ128rr, X86::VADDPSZ128rm, 0 },
2028 { X86::VADDPSZ256rr, X86::VADDPSZ256rm, 0 },
2029 { X86::VALIGNDZ128rri, X86::VALIGNDZ128rmi, 0 },
2030 { X86::VALIGNDZ256rri, X86::VALIGNDZ256rmi, 0 },
2031 { X86::VALIGNQZ128rri, X86::VALIGNQZ128rmi, 0 },
2032 { X86::VALIGNQZ256rri, X86::VALIGNQZ256rmi, 0 },
2033 { X86::VANDNPDZ128rr, X86::VANDNPDZ128rm, 0 },
2034 { X86::VANDNPDZ256rr, X86::VANDNPDZ256rm, 0 },
2035 { X86::VANDNPSZ128rr, X86::VANDNPSZ128rm, 0 },
2036 { X86::VANDNPSZ256rr, X86::VANDNPSZ256rm, 0 },
2037 { X86::VANDPDZ128rr, X86::VANDPDZ128rm, 0 },
2038 { X86::VANDPDZ256rr, X86::VANDPDZ256rm, 0 },
2039 { X86::VANDPSZ128rr, X86::VANDPSZ128rm, 0 },
2040 { X86::VANDPSZ256rr, X86::VANDPSZ256rm, 0 },
2041 { X86::VCMPPDZ128rri, X86::VCMPPDZ128rmi, 0 },
2042 { X86::VCMPPDZ256rri, X86::VCMPPDZ256rmi, 0 },
2043 { X86::VCMPPSZ128rri, X86::VCMPPSZ128rmi, 0 },
2044 { X86::VCMPPSZ256rri, X86::VCMPPSZ256rmi, 0 },
2045 { X86::VDIVPDZ128rr, X86::VDIVPDZ128rm, 0 },
2046 { X86::VDIVPDZ256rr, X86::VDIVPDZ256rm, 0 },
2047 { X86::VDIVPSZ128rr, X86::VDIVPSZ128rm, 0 },
2048 { X86::VDIVPSZ256rr, X86::VDIVPSZ256rm, 0 },
2049 { X86::VINSERTF32x4Z256rr,X86::VINSERTF32x4Z256rm, 0 },
2050 { X86::VINSERTF64x2Z256rr,X86::VINSERTF64x2Z256rm, 0 },
2051 { X86::VINSERTI32x4Z256rr,X86::VINSERTI32x4Z256rm, 0 },
2052 { X86::VINSERTI64x2Z256rr,X86::VINSERTI64x2Z256rm, 0 },
2053 { X86::VMAXCPDZ128rr, X86::VMAXCPDZ128rm, 0 },
2054 { X86::VMAXCPDZ256rr, X86::VMAXCPDZ256rm, 0 },
2055 { X86::VMAXCPSZ128rr, X86::VMAXCPSZ128rm, 0 },
2056 { X86::VMAXCPSZ256rr, X86::VMAXCPSZ256rm, 0 },
2057 { X86::VMAXPDZ128rr, X86::VMAXPDZ128rm, 0 },
2058 { X86::VMAXPDZ256rr, X86::VMAXPDZ256rm, 0 },
2059 { X86::VMAXPSZ128rr, X86::VMAXPSZ128rm, 0 },
2060 { X86::VMAXPSZ256rr, X86::VMAXPSZ256rm, 0 },
2061 { X86::VMINCPDZ128rr, X86::VMINCPDZ128rm, 0 },
2062 { X86::VMINCPDZ256rr, X86::VMINCPDZ256rm, 0 },
2063 { X86::VMINCPSZ128rr, X86::VMINCPSZ128rm, 0 },
2064 { X86::VMINCPSZ256rr, X86::VMINCPSZ256rm, 0 },
2065 { X86::VMINPDZ128rr, X86::VMINPDZ128rm, 0 },
2066 { X86::VMINPDZ256rr, X86::VMINPDZ256rm, 0 },
2067 { X86::VMINPSZ128rr, X86::VMINPSZ128rm, 0 },
2068 { X86::VMINPSZ256rr, X86::VMINPSZ256rm, 0 },
2069 { X86::VMULPDZ128rr, X86::VMULPDZ128rm, 0 },
2070 { X86::VMULPDZ256rr, X86::VMULPDZ256rm, 0 },
2071 { X86::VMULPSZ128rr, X86::VMULPSZ128rm, 0 },
2072 { X86::VMULPSZ256rr, X86::VMULPSZ256rm, 0 },
2073 { X86::VORPDZ128rr, X86::VORPDZ128rm, 0 },
2074 { X86::VORPDZ256rr, X86::VORPDZ256rm, 0 },
2075 { X86::VORPSZ128rr, X86::VORPSZ128rm, 0 },
2076 { X86::VORPSZ256rr, X86::VORPSZ256rm, 0 },
2077 { X86::VPACKSSDWZ256rr, X86::VPACKSSDWZ256rm, 0 },
2078 { X86::VPACKSSDWZ128rr, X86::VPACKSSDWZ128rm, 0 },
2079 { X86::VPACKSSWBZ256rr, X86::VPACKSSWBZ256rm, 0 },
2080 { X86::VPACKSSWBZ128rr, X86::VPACKSSWBZ128rm, 0 },
2081 { X86::VPACKUSDWZ256rr, X86::VPACKUSDWZ256rm, 0 },
2082 { X86::VPACKUSDWZ128rr, X86::VPACKUSDWZ128rm, 0 },
2083 { X86::VPACKUSWBZ256rr, X86::VPACKUSWBZ256rm, 0 },
2084 { X86::VPACKUSWBZ128rr, X86::VPACKUSWBZ128rm, 0 },
2085 { X86::VPADDBZ128rr, X86::VPADDBZ128rm, 0 },
2086 { X86::VPADDBZ256rr, X86::VPADDBZ256rm, 0 },
2087 { X86::VPADDDZ128rr, X86::VPADDDZ128rm, 0 },
2088 { X86::VPADDDZ256rr, X86::VPADDDZ256rm, 0 },
2089 { X86::VPADDQZ128rr, X86::VPADDQZ128rm, 0 },
2090 { X86::VPADDQZ256rr, X86::VPADDQZ256rm, 0 },
2091 { X86::VPADDSBZ128rr, X86::VPADDSBZ128rm, 0 },
2092 { X86::VPADDSBZ256rr, X86::VPADDSBZ256rm, 0 },
2093 { X86::VPADDSWZ128rr, X86::VPADDSWZ128rm, 0 },
2094 { X86::VPADDSWZ256rr, X86::VPADDSWZ256rm, 0 },
2095 { X86::VPADDUSBZ128rr, X86::VPADDUSBZ128rm, 0 },
2096 { X86::VPADDUSBZ256rr, X86::VPADDUSBZ256rm, 0 },
2097 { X86::VPADDUSWZ128rr, X86::VPADDUSWZ128rm, 0 },
2098 { X86::VPADDUSWZ256rr, X86::VPADDUSWZ256rm, 0 },
2099 { X86::VPADDWZ128rr, X86::VPADDWZ128rm, 0 },
2100 { X86::VPADDWZ256rr, X86::VPADDWZ256rm, 0 },
2101 { X86::VPALIGNRZ128rri, X86::VPALIGNRZ128rmi, 0 },
2102 { X86::VPALIGNRZ256rri, X86::VPALIGNRZ256rmi, 0 },
2103 { X86::VPANDDZ128rr, X86::VPANDDZ128rm, 0 },
2104 { X86::VPANDDZ256rr, X86::VPANDDZ256rm, 0 },
2105 { X86::VPANDNDZ128rr, X86::VPANDNDZ128rm, 0 },
2106 { X86::VPANDNDZ256rr, X86::VPANDNDZ256rm, 0 },
2107 { X86::VPANDNQZ128rr, X86::VPANDNQZ128rm, 0 },
2108 { X86::VPANDNQZ256rr, X86::VPANDNQZ256rm, 0 },
2109 { X86::VPANDQZ128rr, X86::VPANDQZ128rm, 0 },
2110 { X86::VPANDQZ256rr, X86::VPANDQZ256rm, 0 },
2111 { X86::VPAVGBZ128rr, X86::VPAVGBZ128rm, 0 },
2112 { X86::VPAVGBZ256rr, X86::VPAVGBZ256rm, 0 },
2113 { X86::VPAVGWZ128rr, X86::VPAVGWZ128rm, 0 },
2114 { X86::VPAVGWZ256rr, X86::VPAVGWZ256rm, 0 },
2115 { X86::VPCMPBZ128rri, X86::VPCMPBZ128rmi, 0 },
2116 { X86::VPCMPBZ256rri, X86::VPCMPBZ256rmi, 0 },
2117 { X86::VPCMPDZ128rri, X86::VPCMPDZ128rmi, 0 },
2118 { X86::VPCMPDZ256rri, X86::VPCMPDZ256rmi, 0 },
2119 { X86::VPCMPEQBZ128rr, X86::VPCMPEQBZ128rm, 0 },
2120 { X86::VPCMPEQBZ256rr, X86::VPCMPEQBZ256rm, 0 },
2121 { X86::VPCMPEQDZ128rr, X86::VPCMPEQDZ128rm, 0 },
2122 { X86::VPCMPEQDZ256rr, X86::VPCMPEQDZ256rm, 0 },
2123 { X86::VPCMPEQQZ128rr, X86::VPCMPEQQZ128rm, 0 },
2124 { X86::VPCMPEQQZ256rr, X86::VPCMPEQQZ256rm, 0 },
2125 { X86::VPCMPEQWZ128rr, X86::VPCMPEQWZ128rm, 0 },
2126 { X86::VPCMPEQWZ256rr, X86::VPCMPEQWZ256rm, 0 },
2127 { X86::VPCMPGTBZ128rr, X86::VPCMPGTBZ128rm, 0 },
2128 { X86::VPCMPGTBZ256rr, X86::VPCMPGTBZ256rm, 0 },
2129 { X86::VPCMPGTDZ128rr, X86::VPCMPGTDZ128rm, 0 },
2130 { X86::VPCMPGTDZ256rr, X86::VPCMPGTDZ256rm, 0 },
2131 { X86::VPCMPGTQZ128rr, X86::VPCMPGTQZ128rm, 0 },
2132 { X86::VPCMPGTQZ256rr, X86::VPCMPGTQZ256rm, 0 },
2133 { X86::VPCMPGTWZ128rr, X86::VPCMPGTWZ128rm, 0 },
2134 { X86::VPCMPGTWZ256rr, X86::VPCMPGTWZ256rm, 0 },
2135 { X86::VPCMPQZ128rri, X86::VPCMPQZ128rmi, 0 },
2136 { X86::VPCMPQZ256rri, X86::VPCMPQZ256rmi, 0 },
2137 { X86::VPCMPUBZ128rri, X86::VPCMPUBZ128rmi, 0 },
2138 { X86::VPCMPUBZ256rri, X86::VPCMPUBZ256rmi, 0 },
2139 { X86::VPCMPUDZ128rri, X86::VPCMPUDZ128rmi, 0 },
2140 { X86::VPCMPUDZ256rri, X86::VPCMPUDZ256rmi, 0 },
2141 { X86::VPCMPUQZ128rri, X86::VPCMPUQZ128rmi, 0 },
2142 { X86::VPCMPUQZ256rri, X86::VPCMPUQZ256rmi, 0 },
2143 { X86::VPCMPUWZ128rri, X86::VPCMPUWZ128rmi, 0 },
2144 { X86::VPCMPUWZ256rri, X86::VPCMPUWZ256rmi, 0 },
2145 { X86::VPCMPWZ128rri, X86::VPCMPWZ128rmi, 0 },
2146 { X86::VPCMPWZ256rri, X86::VPCMPWZ256rmi, 0 },
2147 { X86::VPERMBZ128rr, X86::VPERMBZ128rm, 0 },
2148 { X86::VPERMBZ256rr, X86::VPERMBZ256rm, 0 },
2149 { X86::VPERMDZ256rr, X86::VPERMDZ256rm, 0 },
2150 { X86::VPERMILPDZ128rr, X86::VPERMILPDZ128rm, 0 },
2151 { X86::VPERMILPDZ256rr, X86::VPERMILPDZ256rm, 0 },
2152 { X86::VPERMILPSZ128rr, X86::VPERMILPSZ128rm, 0 },
2153 { X86::VPERMILPSZ256rr, X86::VPERMILPSZ256rm, 0 },
2154 { X86::VPERMPDZ256rr, X86::VPERMPDZ256rm, 0 },
2155 { X86::VPERMPSZ256rr, X86::VPERMPSZ256rm, 0 },
2156 { X86::VPERMQZ256rr, X86::VPERMQZ256rm, 0 },
2157 { X86::VPERMWZ128rr, X86::VPERMWZ128rm, 0 },
2158 { X86::VPERMWZ256rr, X86::VPERMWZ256rm, 0 },
2159 { X86::VPMADDUBSWZ128rr, X86::VPMADDUBSWZ128rm, 0 },
2160 { X86::VPMADDUBSWZ256rr, X86::VPMADDUBSWZ256rm, 0 },
2161 { X86::VPMADDWDZ128rr, X86::VPMADDWDZ128rm, 0 },
2162 { X86::VPMADDWDZ256rr, X86::VPMADDWDZ256rm, 0 },
2163 { X86::VPMAXSBZ128rr, X86::VPMAXSBZ128rm, 0 },
2164 { X86::VPMAXSBZ256rr, X86::VPMAXSBZ256rm, 0 },
2165 { X86::VPMAXSDZ128rr, X86::VPMAXSDZ128rm, 0 },
2166 { X86::VPMAXSDZ256rr, X86::VPMAXSDZ256rm, 0 },
2167 { X86::VPMAXSQZ128rr, X86::VPMAXSQZ128rm, 0 },
2168 { X86::VPMAXSQZ256rr, X86::VPMAXSQZ256rm, 0 },
2169 { X86::VPMAXSWZ128rr, X86::VPMAXSWZ128rm, 0 },
2170 { X86::VPMAXSWZ256rr, X86::VPMAXSWZ256rm, 0 },
2171 { X86::VPMAXUBZ128rr, X86::VPMAXUBZ128rm, 0 },
2172 { X86::VPMAXUBZ256rr, X86::VPMAXUBZ256rm, 0 },
2173 { X86::VPMAXUDZ128rr, X86::VPMAXUDZ128rm, 0 },
2174 { X86::VPMAXUDZ256rr, X86::VPMAXUDZ256rm, 0 },
2175 { X86::VPMAXUQZ128rr, X86::VPMAXUQZ128rm, 0 },
2176 { X86::VPMAXUQZ256rr, X86::VPMAXUQZ256rm, 0 },
2177 { X86::VPMAXUWZ128rr, X86::VPMAXUWZ128rm, 0 },
2178 { X86::VPMAXUWZ256rr, X86::VPMAXUWZ256rm, 0 },
2179 { X86::VPMINSBZ128rr, X86::VPMINSBZ128rm, 0 },
2180 { X86::VPMINSBZ256rr, X86::VPMINSBZ256rm, 0 },
2181 { X86::VPMINSDZ128rr, X86::VPMINSDZ128rm, 0 },
2182 { X86::VPMINSDZ256rr, X86::VPMINSDZ256rm, 0 },
2183 { X86::VPMINSQZ128rr, X86::VPMINSQZ128rm, 0 },
2184 { X86::VPMINSQZ256rr, X86::VPMINSQZ256rm, 0 },
2185 { X86::VPMINSWZ128rr, X86::VPMINSWZ128rm, 0 },
2186 { X86::VPMINSWZ256rr, X86::VPMINSWZ256rm, 0 },
2187 { X86::VPMINUBZ128rr, X86::VPMINUBZ128rm, 0 },
2188 { X86::VPMINUBZ256rr, X86::VPMINUBZ256rm, 0 },
2189 { X86::VPMINUDZ128rr, X86::VPMINUDZ128rm, 0 },
2190 { X86::VPMINUDZ256rr, X86::VPMINUDZ256rm, 0 },
2191 { X86::VPMINUQZ128rr, X86::VPMINUQZ128rm, 0 },
2192 { X86::VPMINUQZ256rr, X86::VPMINUQZ256rm, 0 },
2193 { X86::VPMINUWZ128rr, X86::VPMINUWZ128rm, 0 },
2194 { X86::VPMINUWZ256rr, X86::VPMINUWZ256rm, 0 },
2195 { X86::VPMULDQZ128rr, X86::VPMULDQZ128rm, 0 },
2196 { X86::VPMULDQZ256rr, X86::VPMULDQZ256rm, 0 },
2197 { X86::VPMULLDZ128rr, X86::VPMULLDZ128rm, 0 },
2198 { X86::VPMULLDZ256rr, X86::VPMULLDZ256rm, 0 },
2199 { X86::VPMULLQZ128rr, X86::VPMULLQZ128rm, 0 },
2200 { X86::VPMULLQZ256rr, X86::VPMULLQZ256rm, 0 },
2201 { X86::VPMULLWZ128rr, X86::VPMULLWZ128rm, 0 },
2202 { X86::VPMULLWZ256rr, X86::VPMULLWZ256rm, 0 },
2203 { X86::VPMULUDQZ128rr, X86::VPMULUDQZ128rm, 0 },
2204 { X86::VPMULUDQZ256rr, X86::VPMULUDQZ256rm, 0 },
2205 { X86::VPORDZ128rr, X86::VPORDZ128rm, 0 },
2206 { X86::VPORDZ256rr, X86::VPORDZ256rm, 0 },
2207 { X86::VPORQZ128rr, X86::VPORQZ128rm, 0 },
2208 { X86::VPORQZ256rr, X86::VPORQZ256rm, 0 },
2209 { X86::VPSADBWZ128rr, X86::VPSADBWZ128rm, 0 },
2210 { X86::VPSADBWZ256rr, X86::VPSADBWZ256rm, 0 },
2211 { X86::VPSHUFBZ128rr, X86::VPSHUFBZ128rm, 0 },
2212 { X86::VPSHUFBZ256rr, X86::VPSHUFBZ256rm, 0 },
2213 { X86::VPSLLDZ128rr, X86::VPSLLDZ128rm, 0 },
2214 { X86::VPSLLDZ256rr, X86::VPSLLDZ256rm, 0 },
2215 { X86::VPSLLQZ128rr, X86::VPSLLQZ128rm, 0 },
2216 { X86::VPSLLQZ256rr, X86::VPSLLQZ256rm, 0 },
2217 { X86::VPSLLVDZ128rr, X86::VPSLLVDZ128rm, 0 },
2218 { X86::VPSLLVDZ256rr, X86::VPSLLVDZ256rm, 0 },
2219 { X86::VPSLLVQZ128rr, X86::VPSLLVQZ128rm, 0 },
2220 { X86::VPSLLVQZ256rr, X86::VPSLLVQZ256rm, 0 },
2221 { X86::VPSLLVWZ128rr, X86::VPSLLVWZ128rm, 0 },
2222 { X86::VPSLLVWZ256rr, X86::VPSLLVWZ256rm, 0 },
2223 { X86::VPSLLWZ128rr, X86::VPSLLWZ128rm, 0 },
2224 { X86::VPSLLWZ256rr, X86::VPSLLWZ256rm, 0 },
2225 { X86::VPSRADZ128rr, X86::VPSRADZ128rm, 0 },
2226 { X86::VPSRADZ256rr, X86::VPSRADZ256rm, 0 },
2227 { X86::VPSRAQZ128rr, X86::VPSRAQZ128rm, 0 },
2228 { X86::VPSRAQZ256rr, X86::VPSRAQZ256rm, 0 },
2229 { X86::VPSRAVDZ128rr, X86::VPSRAVDZ128rm, 0 },
2230 { X86::VPSRAVDZ256rr, X86::VPSRAVDZ256rm, 0 },
2231 { X86::VPSRAVQZ128rr, X86::VPSRAVQZ128rm, 0 },
2232 { X86::VPSRAVQZ256rr, X86::VPSRAVQZ256rm, 0 },
2233 { X86::VPSRAVWZ128rr, X86::VPSRAVWZ128rm, 0 },
2234 { X86::VPSRAVWZ256rr, X86::VPSRAVWZ256rm, 0 },
2235 { X86::VPSRAWZ128rr, X86::VPSRAWZ128rm, 0 },
2236 { X86::VPSRAWZ256rr, X86::VPSRAWZ256rm, 0 },
2237 { X86::VPSRLDZ128rr, X86::VPSRLDZ128rm, 0 },
2238 { X86::VPSRLDZ256rr, X86::VPSRLDZ256rm, 0 },
2239 { X86::VPSRLQZ128rr, X86::VPSRLQZ128rm, 0 },
2240 { X86::VPSRLQZ256rr, X86::VPSRLQZ256rm, 0 },
2241 { X86::VPSRLVDZ128rr, X86::VPSRLVDZ128rm, 0 },
2242 { X86::VPSRLVDZ256rr, X86::VPSRLVDZ256rm, 0 },
2243 { X86::VPSRLVQZ128rr, X86::VPSRLVQZ128rm, 0 },
2244 { X86::VPSRLVQZ256rr, X86::VPSRLVQZ256rm, 0 },
2245 { X86::VPSRLVWZ128rr, X86::VPSRLVWZ128rm, 0 },
2246 { X86::VPSRLVWZ256rr, X86::VPSRLVWZ256rm, 0 },
2247 { X86::VPSRLWZ128rr, X86::VPSRLWZ128rm, 0 },
2248 { X86::VPSRLWZ256rr, X86::VPSRLWZ256rm, 0 },
2249 { X86::VPSUBBZ128rr, X86::VPSUBBZ128rm, 0 },
2250 { X86::VPSUBBZ256rr, X86::VPSUBBZ256rm, 0 },
2251 { X86::VPSUBDZ128rr, X86::VPSUBDZ128rm, 0 },
2252 { X86::VPSUBDZ256rr, X86::VPSUBDZ256rm, 0 },
2253 { X86::VPSUBQZ128rr, X86::VPSUBQZ128rm, 0 },
2254 { X86::VPSUBQZ256rr, X86::VPSUBQZ256rm, 0 },
2255 { X86::VPSUBSBZ128rr, X86::VPSUBSBZ128rm, 0 },
2256 { X86::VPSUBSBZ256rr, X86::VPSUBSBZ256rm, 0 },
2257 { X86::VPSUBSWZ128rr, X86::VPSUBSWZ128rm, 0 },
2258 { X86::VPSUBSWZ256rr, X86::VPSUBSWZ256rm, 0 },
2259 { X86::VPSUBUSBZ128rr, X86::VPSUBUSBZ128rm, 0 },
2260 { X86::VPSUBUSBZ256rr, X86::VPSUBUSBZ256rm, 0 },
2261 { X86::VPSUBUSWZ128rr, X86::VPSUBUSWZ128rm, 0 },
2262 { X86::VPSUBUSWZ256rr, X86::VPSUBUSWZ256rm, 0 },
2263 { X86::VPSUBWZ128rr, X86::VPSUBWZ128rm, 0 },
2264 { X86::VPSUBWZ256rr, X86::VPSUBWZ256rm, 0 },
2265 { X86::VPUNPCKHBWZ128rr, X86::VPUNPCKHBWZ128rm, 0 },
2266 { X86::VPUNPCKHBWZ256rr, X86::VPUNPCKHBWZ256rm, 0 },
2267 { X86::VPUNPCKHDQZ128rr, X86::VPUNPCKHDQZ128rm, 0 },
2268 { X86::VPUNPCKHDQZ256rr, X86::VPUNPCKHDQZ256rm, 0 },
2269 { X86::VPUNPCKHQDQZ128rr, X86::VPUNPCKHQDQZ128rm, 0 },
2270 { X86::VPUNPCKHQDQZ256rr, X86::VPUNPCKHQDQZ256rm, 0 },
2271 { X86::VPUNPCKHWDZ128rr, X86::VPUNPCKHWDZ128rm, 0 },
2272 { X86::VPUNPCKHWDZ256rr, X86::VPUNPCKHWDZ256rm, 0 },
2273 { X86::VPUNPCKLBWZ128rr, X86::VPUNPCKLBWZ128rm, 0 },
2274 { X86::VPUNPCKLBWZ256rr, X86::VPUNPCKLBWZ256rm, 0 },
2275 { X86::VPUNPCKLDQZ128rr, X86::VPUNPCKLDQZ128rm, 0 },
2276 { X86::VPUNPCKLDQZ256rr, X86::VPUNPCKLDQZ256rm, 0 },
2277 { X86::VPUNPCKLQDQZ128rr, X86::VPUNPCKLQDQZ128rm, 0 },
2278 { X86::VPUNPCKLQDQZ256rr, X86::VPUNPCKLQDQZ256rm, 0 },
2279 { X86::VPUNPCKLWDZ128rr, X86::VPUNPCKLWDZ128rm, 0 },
2280 { X86::VPUNPCKLWDZ256rr, X86::VPUNPCKLWDZ256rm, 0 },
2281 { X86::VPXORDZ128rr, X86::VPXORDZ128rm, 0 },
2282 { X86::VPXORDZ256rr, X86::VPXORDZ256rm, 0 },
2283 { X86::VPXORQZ128rr, X86::VPXORQZ128rm, 0 },
2284 { X86::VPXORQZ256rr, X86::VPXORQZ256rm, 0 },
2285 { X86::VSHUFPDZ128rri, X86::VSHUFPDZ128rmi, 0 },
2286 { X86::VSHUFPDZ256rri, X86::VSHUFPDZ256rmi, 0 },
2287 { X86::VSHUFPSZ128rri, X86::VSHUFPSZ128rmi, 0 },
2288 { X86::VSHUFPSZ256rri, X86::VSHUFPSZ256rmi, 0 },
2289 { X86::VSUBPDZ128rr, X86::VSUBPDZ128rm, 0 },
2290 { X86::VSUBPDZ256rr, X86::VSUBPDZ256rm, 0 },
2291 { X86::VSUBPSZ128rr, X86::VSUBPSZ128rm, 0 },
2292 { X86::VSUBPSZ256rr, X86::VSUBPSZ256rm, 0 },
2293 { X86::VUNPCKHPDZ128rr, X86::VUNPCKHPDZ128rm, 0 },
2294 { X86::VUNPCKHPDZ256rr, X86::VUNPCKHPDZ256rm, 0 },
2295 { X86::VUNPCKHPSZ128rr, X86::VUNPCKHPSZ128rm, 0 },
2296 { X86::VUNPCKHPSZ256rr, X86::VUNPCKHPSZ256rm, 0 },
2297 { X86::VUNPCKLPDZ128rr, X86::VUNPCKLPDZ128rm, 0 },
2298 { X86::VUNPCKLPDZ256rr, X86::VUNPCKLPDZ256rm, 0 },
2299 { X86::VUNPCKLPSZ128rr, X86::VUNPCKLPSZ128rm, 0 },
2300 { X86::VUNPCKLPSZ256rr, X86::VUNPCKLPSZ256rm, 0 },
2301 { X86::VXORPDZ128rr, X86::VXORPDZ128rm, 0 },
2302 { X86::VXORPDZ256rr, X86::VXORPDZ256rm, 0 },
2303 { X86::VXORPSZ128rr, X86::VXORPSZ128rm, 0 },
2304 { X86::VXORPSZ256rr, X86::VXORPSZ256rm, 0 },
2305
2306 // AVX-512 masked foldable instructions
2307 { X86::VBROADCASTSSZrkz, X86::VBROADCASTSSZmkz, TB_NO_REVERSE },
2308 { X86::VBROADCASTSDZrkz, X86::VBROADCASTSDZmkz, TB_NO_REVERSE },
2309 { X86::VPABSBZrrkz, X86::VPABSBZrmkz, 0 },
2310 { X86::VPABSDZrrkz, X86::VPABSDZrmkz, 0 },
2311 { X86::VPABSQZrrkz, X86::VPABSQZrmkz, 0 },
2312 { X86::VPABSWZrrkz, X86::VPABSWZrmkz, 0 },
2313 { X86::VPERMILPDZrikz, X86::VPERMILPDZmikz, 0 },
2314 { X86::VPERMILPSZrikz, X86::VPERMILPSZmikz, 0 },
2315 { X86::VPERMPDZrikz, X86::VPERMPDZmikz, 0 },
2316 { X86::VPERMQZrikz, X86::VPERMQZmikz, 0 },
2317 { X86::VPMOVSXBDZrrkz, X86::VPMOVSXBDZrmkz, 0 },
2318 { X86::VPMOVSXBQZrrkz, X86::VPMOVSXBQZrmkz, TB_NO_REVERSE },
2319 { X86::VPMOVSXBWZrrkz, X86::VPMOVSXBWZrmkz, 0 },
2320 { X86::VPMOVSXDQZrrkz, X86::VPMOVSXDQZrmkz, 0 },
2321 { X86::VPMOVSXWDZrrkz, X86::VPMOVSXWDZrmkz, 0 },
2322 { X86::VPMOVSXWQZrrkz, X86::VPMOVSXWQZrmkz, 0 },
2323 { X86::VPMOVZXBDZrrkz, X86::VPMOVZXBDZrmkz, 0 },
2324 { X86::VPMOVZXBQZrrkz, X86::VPMOVZXBQZrmkz, TB_NO_REVERSE },
2325 { X86::VPMOVZXBWZrrkz, X86::VPMOVZXBWZrmkz, 0 },
2326 { X86::VPMOVZXDQZrrkz, X86::VPMOVZXDQZrmkz, 0 },
2327 { X86::VPMOVZXWDZrrkz, X86::VPMOVZXWDZrmkz, 0 },
2328 { X86::VPMOVZXWQZrrkz, X86::VPMOVZXWQZrmkz, 0 },
2329 { X86::VPSHUFDZrikz, X86::VPSHUFDZmikz, 0 },
2330 { X86::VPSHUFHWZrikz, X86::VPSHUFHWZmikz, 0 },
2331 { X86::VPSHUFLWZrikz, X86::VPSHUFLWZmikz, 0 },
2332 { X86::VPSLLDZrikz, X86::VPSLLDZmikz, 0 },
2333 { X86::VPSLLQZrikz, X86::VPSLLQZmikz, 0 },
2334 { X86::VPSLLWZrikz, X86::VPSLLWZmikz, 0 },
2335 { X86::VPSRADZrikz, X86::VPSRADZmikz, 0 },
2336 { X86::VPSRAQZrikz, X86::VPSRAQZmikz, 0 },
2337 { X86::VPSRAWZrikz, X86::VPSRAWZmikz, 0 },
2338 { X86::VPSRLDZrikz, X86::VPSRLDZmikz, 0 },
2339 { X86::VPSRLQZrikz, X86::VPSRLQZmikz, 0 },
2340 { X86::VPSRLWZrikz, X86::VPSRLWZmikz, 0 },
2341
2342 // AVX-512VL 256-bit masked foldable instructions
2343 { X86::VBROADCASTSDZ256rkz, X86::VBROADCASTSDZ256mkz, TB_NO_REVERSE },
2344 { X86::VBROADCASTSSZ256rkz, X86::VBROADCASTSSZ256mkz, TB_NO_REVERSE },
2345 { X86::VPABSBZ256rrkz, X86::VPABSBZ256rmkz, 0 },
2346 { X86::VPABSDZ256rrkz, X86::VPABSDZ256rmkz, 0 },
2347 { X86::VPABSQZ256rrkz, X86::VPABSQZ256rmkz, 0 },
2348 { X86::VPABSWZ256rrkz, X86::VPABSWZ256rmkz, 0 },
2349 { X86::VPERMILPDZ256rikz, X86::VPERMILPDZ256mikz, 0 },
2350 { X86::VPERMILPSZ256rikz, X86::VPERMILPSZ256mikz, 0 },
2351 { X86::VPERMPDZ256rikz, X86::VPERMPDZ256mikz, 0 },
2352 { X86::VPERMQZ256rikz, X86::VPERMQZ256mikz, 0 },
2353 { X86::VPMOVSXBDZ256rrkz, X86::VPMOVSXBDZ256rmkz, TB_NO_REVERSE },
2354 { X86::VPMOVSXBQZ256rrkz, X86::VPMOVSXBQZ256rmkz, TB_NO_REVERSE },
2355 { X86::VPMOVSXBWZ256rrkz, X86::VPMOVSXBWZ256rmkz, 0 },
2356 { X86::VPMOVSXDQZ256rrkz, X86::VPMOVSXDQZ256rmkz, 0 },
2357 { X86::VPMOVSXWDZ256rrkz, X86::VPMOVSXWDZ256rmkz, 0 },
2358 { X86::VPMOVSXWQZ256rrkz, X86::VPMOVSXWQZ256rmkz, TB_NO_REVERSE },
2359 { X86::VPMOVZXBDZ256rrkz, X86::VPMOVZXBDZ256rmkz, TB_NO_REVERSE },
2360 { X86::VPMOVZXBQZ256rrkz, X86::VPMOVZXBQZ256rmkz, TB_NO_REVERSE },
2361 { X86::VPMOVZXBWZ256rrkz, X86::VPMOVZXBWZ256rmkz, 0 },
2362 { X86::VPMOVZXDQZ256rrkz, X86::VPMOVZXDQZ256rmkz, 0 },
2363 { X86::VPMOVZXWDZ256rrkz, X86::VPMOVZXWDZ256rmkz, 0 },
2364 { X86::VPMOVZXWQZ256rrkz, X86::VPMOVZXWQZ256rmkz, TB_NO_REVERSE },
2365 { X86::VPSHUFDZ256rikz, X86::VPSHUFDZ256mikz, 0 },
2366 { X86::VPSHUFHWZ256rikz, X86::VPSHUFHWZ256mikz, 0 },
2367 { X86::VPSHUFLWZ256rikz, X86::VPSHUFLWZ256mikz, 0 },
2368 { X86::VPSLLDZ256rikz, X86::VPSLLDZ256mikz, 0 },
2369 { X86::VPSLLQZ256rikz, X86::VPSLLQZ256mikz, 0 },
2370 { X86::VPSLLWZ256rikz, X86::VPSLLWZ256mikz, 0 },
2371 { X86::VPSRADZ256rikz, X86::VPSRADZ256mikz, 0 },
2372 { X86::VPSRAQZ256rikz, X86::VPSRAQZ256mikz, 0 },
2373 { X86::VPSRAWZ256rikz, X86::VPSRAWZ256mikz, 0 },
2374 { X86::VPSRLDZ256rikz, X86::VPSRLDZ256mikz, 0 },
2375 { X86::VPSRLQZ256rikz, X86::VPSRLQZ256mikz, 0 },
2376 { X86::VPSRLWZ256rikz, X86::VPSRLWZ256mikz, 0 },
2377
2378 // AVX-512VL 128-bit masked foldable instructions
2379 { X86::VBROADCASTSSZ128rkz, X86::VBROADCASTSSZ128mkz, TB_NO_REVERSE },
2380 { X86::VPABSBZ128rrkz, X86::VPABSBZ128rmkz, 0 },
2381 { X86::VPABSDZ128rrkz, X86::VPABSDZ128rmkz, 0 },
2382 { X86::VPABSQZ128rrkz, X86::VPABSQZ128rmkz, 0 },
2383 { X86::VPABSWZ128rrkz, X86::VPABSWZ128rmkz, 0 },
2384 { X86::VPERMILPDZ128rikz, X86::VPERMILPDZ128mikz, 0 },
2385 { X86::VPERMILPSZ128rikz, X86::VPERMILPSZ128mikz, 0 },
2386 { X86::VPMOVSXBDZ128rrkz, X86::VPMOVSXBDZ128rmkz, TB_NO_REVERSE },
2387 { X86::VPMOVSXBQZ128rrkz, X86::VPMOVSXBQZ128rmkz, TB_NO_REVERSE },
2388 { X86::VPMOVSXBWZ128rrkz, X86::VPMOVSXBWZ128rmkz, TB_NO_REVERSE },
2389 { X86::VPMOVSXDQZ128rrkz, X86::VPMOVSXDQZ128rmkz, TB_NO_REVERSE },
2390 { X86::VPMOVSXWDZ128rrkz, X86::VPMOVSXWDZ128rmkz, TB_NO_REVERSE },
2391 { X86::VPMOVSXWQZ128rrkz, X86::VPMOVSXWQZ128rmkz, TB_NO_REVERSE },
2392 { X86::VPMOVZXBDZ128rrkz, X86::VPMOVZXBDZ128rmkz, TB_NO_REVERSE },
2393 { X86::VPMOVZXBQZ128rrkz, X86::VPMOVZXBQZ128rmkz, TB_NO_REVERSE },
2394 { X86::VPMOVZXBWZ128rrkz, X86::VPMOVZXBWZ128rmkz, TB_NO_REVERSE },
2395 { X86::VPMOVZXDQZ128rrkz, X86::VPMOVZXDQZ128rmkz, TB_NO_REVERSE },
2396 { X86::VPMOVZXWDZ128rrkz, X86::VPMOVZXWDZ128rmkz, TB_NO_REVERSE },
2397 { X86::VPMOVZXWQZ128rrkz, X86::VPMOVZXWQZ128rmkz, TB_NO_REVERSE },
2398 { X86::VPSHUFDZ128rikz, X86::VPSHUFDZ128mikz, 0 },
2399 { X86::VPSHUFHWZ128rikz, X86::VPSHUFHWZ128mikz, 0 },
2400 { X86::VPSHUFLWZ128rikz, X86::VPSHUFLWZ128mikz, 0 },
2401 { X86::VPSLLDZ128rikz, X86::VPSLLDZ128mikz, 0 },
2402 { X86::VPSLLQZ128rikz, X86::VPSLLQZ128mikz, 0 },
2403 { X86::VPSLLWZ128rikz, X86::VPSLLWZ128mikz, 0 },
2404 { X86::VPSRADZ128rikz, X86::VPSRADZ128mikz, 0 },
2405 { X86::VPSRAQZ128rikz, X86::VPSRAQZ128mikz, 0 },
2406 { X86::VPSRAWZ128rikz, X86::VPSRAWZ128mikz, 0 },
2407 { X86::VPSRLDZ128rikz, X86::VPSRLDZ128mikz, 0 },
2408 { X86::VPSRLQZ128rikz, X86::VPSRLQZ128mikz, 0 },
2409 { X86::VPSRLWZ128rikz, X86::VPSRLWZ128mikz, 0 },
2410
2411 // AES foldable instructions
2412 { X86::AESDECLASTrr, X86::AESDECLASTrm, TB_ALIGN_16 },
2413 { X86::AESDECrr, X86::AESDECrm, TB_ALIGN_16 },
2414 { X86::AESENCLASTrr, X86::AESENCLASTrm, TB_ALIGN_16 },
2415 { X86::AESENCrr, X86::AESENCrm, TB_ALIGN_16 },
2416 { X86::VAESDECLASTrr, X86::VAESDECLASTrm, 0 },
2417 { X86::VAESDECrr, X86::VAESDECrm, 0 },
2418 { X86::VAESENCLASTrr, X86::VAESENCLASTrm, 0 },
2419 { X86::VAESENCrr, X86::VAESENCrm, 0 },
2420
2421 // SHA foldable instructions
2422 { X86::SHA1MSG1rr, X86::SHA1MSG1rm, TB_ALIGN_16 },
2423 { X86::SHA1MSG2rr, X86::SHA1MSG2rm, TB_ALIGN_16 },
2424 { X86::SHA1NEXTErr, X86::SHA1NEXTErm, TB_ALIGN_16 },
2425 { X86::SHA1RNDS4rri, X86::SHA1RNDS4rmi, TB_ALIGN_16 },
2426 { X86::SHA256MSG1rr, X86::SHA256MSG1rm, TB_ALIGN_16 },
2427 { X86::SHA256MSG2rr, X86::SHA256MSG2rm, TB_ALIGN_16 },
2428 { X86::SHA256RNDS2rr, X86::SHA256RNDS2rm, TB_ALIGN_16 }
2429 };
2430
2431 for (X86MemoryFoldTableEntry Entry : MemoryFoldTable2) {
2432 AddTableEntry(RegOp2MemOpTable2, MemOp2RegOpTable,
2433 Entry.RegOp, Entry.MemOp,
2434 // Index 2, folded load
2435 Entry.Flags | TB_INDEX_2 | TB_FOLDED_LOAD);
2436 }
2437
2438 static const X86MemoryFoldTableEntry MemoryFoldTable3[] = {
2439 // FMA4 foldable patterns
2440 { X86::VFMADDSS4rr, X86::VFMADDSS4rm, TB_ALIGN_NONE },
2441 { X86::VFMADDSS4rr_Int, X86::VFMADDSS4rm_Int, TB_NO_REVERSE },
2442 { X86::VFMADDSD4rr, X86::VFMADDSD4rm, TB_ALIGN_NONE },
2443 { X86::VFMADDSD4rr_Int, X86::VFMADDSD4rm_Int, TB_NO_REVERSE },
2444 { X86::VFMADDPS4rr, X86::VFMADDPS4rm, TB_ALIGN_NONE },
2445 { X86::VFMADDPD4rr, X86::VFMADDPD4rm, TB_ALIGN_NONE },
2446 { X86::VFMADDPS4Yrr, X86::VFMADDPS4Yrm, TB_ALIGN_NONE },
2447 { X86::VFMADDPD4Yrr, X86::VFMADDPD4Yrm, TB_ALIGN_NONE },
2448 { X86::VFNMADDSS4rr, X86::VFNMADDSS4rm, TB_ALIGN_NONE },
2449 { X86::VFNMADDSS4rr_Int, X86::VFNMADDSS4rm_Int, TB_NO_REVERSE },
2450 { X86::VFNMADDSD4rr, X86::VFNMADDSD4rm, TB_ALIGN_NONE },
2451 { X86::VFNMADDSD4rr_Int, X86::VFNMADDSD4rm_Int, TB_NO_REVERSE },
2452 { X86::VFNMADDPS4rr, X86::VFNMADDPS4rm, TB_ALIGN_NONE },
2453 { X86::VFNMADDPD4rr, X86::VFNMADDPD4rm, TB_ALIGN_NONE },
2454 { X86::VFNMADDPS4Yrr, X86::VFNMADDPS4Yrm, TB_ALIGN_NONE },
2455 { X86::VFNMADDPD4Yrr, X86::VFNMADDPD4Yrm, TB_ALIGN_NONE },
2456 { X86::VFMSUBSS4rr, X86::VFMSUBSS4rm, TB_ALIGN_NONE },
2457 { X86::VFMSUBSS4rr_Int, X86::VFMSUBSS4rm_Int, TB_NO_REVERSE },
2458 { X86::VFMSUBSD4rr, X86::VFMSUBSD4rm, TB_ALIGN_NONE },
2459 { X86::VFMSUBSD4rr_Int, X86::VFMSUBSD4rm_Int, TB_NO_REVERSE },
2460 { X86::VFMSUBPS4rr, X86::VFMSUBPS4rm, TB_ALIGN_NONE },
2461 { X86::VFMSUBPD4rr, X86::VFMSUBPD4rm, TB_ALIGN_NONE },
2462 { X86::VFMSUBPS4Yrr, X86::VFMSUBPS4Yrm, TB_ALIGN_NONE },
2463 { X86::VFMSUBPD4Yrr, X86::VFMSUBPD4Yrm, TB_ALIGN_NONE },
2464 { X86::VFNMSUBSS4rr, X86::VFNMSUBSS4rm, TB_ALIGN_NONE },
2465 { X86::VFNMSUBSS4rr_Int, X86::VFNMSUBSS4rm_Int, TB_NO_REVERSE },
2466 { X86::VFNMSUBSD4rr, X86::VFNMSUBSD4rm, TB_ALIGN_NONE },
2467 { X86::VFNMSUBSD4rr_Int, X86::VFNMSUBSD4rm_Int, TB_NO_REVERSE },
2468 { X86::VFNMSUBPS4rr, X86::VFNMSUBPS4rm, TB_ALIGN_NONE },
2469 { X86::VFNMSUBPD4rr, X86::VFNMSUBPD4rm, TB_ALIGN_NONE },
2470 { X86::VFNMSUBPS4Yrr, X86::VFNMSUBPS4Yrm, TB_ALIGN_NONE },
2471 { X86::VFNMSUBPD4Yrr, X86::VFNMSUBPD4Yrm, TB_ALIGN_NONE },
2472 { X86::VFMADDSUBPS4rr, X86::VFMADDSUBPS4rm, TB_ALIGN_NONE },
2473 { X86::VFMADDSUBPD4rr, X86::VFMADDSUBPD4rm, TB_ALIGN_NONE },
2474 { X86::VFMADDSUBPS4Yrr, X86::VFMADDSUBPS4Yrm, TB_ALIGN_NONE },
2475 { X86::VFMADDSUBPD4Yrr, X86::VFMADDSUBPD4Yrm, TB_ALIGN_NONE },
2476 { X86::VFMSUBADDPS4rr, X86::VFMSUBADDPS4rm, TB_ALIGN_NONE },
2477 { X86::VFMSUBADDPD4rr, X86::VFMSUBADDPD4rm, TB_ALIGN_NONE },
2478 { X86::VFMSUBADDPS4Yrr, X86::VFMSUBADDPS4Yrm, TB_ALIGN_NONE },
2479 { X86::VFMSUBADDPD4Yrr, X86::VFMSUBADDPD4Yrm, TB_ALIGN_NONE },
2480
2481 // XOP foldable instructions
2482 { X86::VPCMOVrrr, X86::VPCMOVrrm, 0 },
2483 { X86::VPCMOVYrrr, X86::VPCMOVYrrm, 0 },
2484 { X86::VPERMIL2PDrr, X86::VPERMIL2PDrm, 0 },
2485 { X86::VPERMIL2PDYrr, X86::VPERMIL2PDYrm, 0 },
2486 { X86::VPERMIL2PSrr, X86::VPERMIL2PSrm, 0 },
2487 { X86::VPERMIL2PSYrr, X86::VPERMIL2PSYrm, 0 },
2488 { X86::VPPERMrrr, X86::VPPERMrrm, 0 },
2489
2490 // AVX-512 instructions with 3 source operands.
2491 { X86::VPERMI2Brr, X86::VPERMI2Brm, 0 },
2492 { X86::VPERMI2Drr, X86::VPERMI2Drm, 0 },
2493 { X86::VPERMI2PSrr, X86::VPERMI2PSrm, 0 },
2494 { X86::VPERMI2PDrr, X86::VPERMI2PDrm, 0 },
2495 { X86::VPERMI2Qrr, X86::VPERMI2Qrm, 0 },
2496 { X86::VPERMI2Wrr, X86::VPERMI2Wrm, 0 },
2497 { X86::VPERMT2Brr, X86::VPERMT2Brm, 0 },
2498 { X86::VPERMT2Drr, X86::VPERMT2Drm, 0 },
2499 { X86::VPERMT2PSrr, X86::VPERMT2PSrm, 0 },
2500 { X86::VPERMT2PDrr, X86::VPERMT2PDrm, 0 },
2501 { X86::VPERMT2Qrr, X86::VPERMT2Qrm, 0 },
2502 { X86::VPERMT2Wrr, X86::VPERMT2Wrm, 0 },
2503 { X86::VPTERNLOGDZrri, X86::VPTERNLOGDZrmi, 0 },
2504 { X86::VPTERNLOGQZrri, X86::VPTERNLOGQZrmi, 0 },
2505
2506 // AVX-512VL 256-bit instructions with 3 source operands.
2507 { X86::VPERMI2B256rr, X86::VPERMI2B256rm, 0 },
2508 { X86::VPERMI2D256rr, X86::VPERMI2D256rm, 0 },
2509 { X86::VPERMI2PD256rr, X86::VPERMI2PD256rm, 0 },
2510 { X86::VPERMI2PS256rr, X86::VPERMI2PS256rm, 0 },
2511 { X86::VPERMI2Q256rr, X86::VPERMI2Q256rm, 0 },
2512 { X86::VPERMI2W256rr, X86::VPERMI2W256rm, 0 },
2513 { X86::VPERMT2B256rr, X86::VPERMT2B256rm, 0 },
2514 { X86::VPERMT2D256rr, X86::VPERMT2D256rm, 0 },
2515 { X86::VPERMT2PD256rr, X86::VPERMT2PD256rm, 0 },
2516 { X86::VPERMT2PS256rr, X86::VPERMT2PS256rm, 0 },
2517 { X86::VPERMT2Q256rr, X86::VPERMT2Q256rm, 0 },
2518 { X86::VPERMT2W256rr, X86::VPERMT2W256rm, 0 },
2519 { X86::VPTERNLOGDZ256rri, X86::VPTERNLOGDZ256rmi, 0 },
2520 { X86::VPTERNLOGQZ256rri, X86::VPTERNLOGQZ256rmi, 0 },
2521
2522 // AVX-512VL 128-bit instructions with 3 source operands.
2523 { X86::VPERMI2B128rr, X86::VPERMI2B128rm, 0 },
2524 { X86::VPERMI2D128rr, X86::VPERMI2D128rm, 0 },
2525 { X86::VPERMI2PD128rr, X86::VPERMI2PD128rm, 0 },
2526 { X86::VPERMI2PS128rr, X86::VPERMI2PS128rm, 0 },
2527 { X86::VPERMI2Q128rr, X86::VPERMI2Q128rm, 0 },
2528 { X86::VPERMI2W128rr, X86::VPERMI2W128rm, 0 },
2529 { X86::VPERMT2B128rr, X86::VPERMT2B128rm, 0 },
2530 { X86::VPERMT2D128rr, X86::VPERMT2D128rm, 0 },
2531 { X86::VPERMT2PD128rr, X86::VPERMT2PD128rm, 0 },
2532 { X86::VPERMT2PS128rr, X86::VPERMT2PS128rm, 0 },
2533 { X86::VPERMT2Q128rr, X86::VPERMT2Q128rm, 0 },
2534 { X86::VPERMT2W128rr, X86::VPERMT2W128rm, 0 },
2535 { X86::VPTERNLOGDZ128rri, X86::VPTERNLOGDZ128rmi, 0 },
2536 { X86::VPTERNLOGQZ128rri, X86::VPTERNLOGQZ128rmi, 0 },
2537
2538 // AVX-512 masked instructions
2539 { X86::VADDPDZrrkz, X86::VADDPDZrmkz, 0 },
2540 { X86::VADDPSZrrkz, X86::VADDPSZrmkz, 0 },
2541 { X86::VADDSDZrr_Intkz, X86::VADDSDZrm_Intkz, TB_NO_REVERSE },
2542 { X86::VADDSSZrr_Intkz, X86::VADDSSZrm_Intkz, TB_NO_REVERSE },
2543 { X86::VALIGNDZrrikz, X86::VALIGNDZrmikz, 0 },
2544 { X86::VALIGNQZrrikz, X86::VALIGNQZrmikz, 0 },
2545 { X86::VANDNPDZrrkz, X86::VANDNPDZrmkz, 0 },
2546 { X86::VANDNPSZrrkz, X86::VANDNPSZrmkz, 0 },
2547 { X86::VANDPDZrrkz, X86::VANDPDZrmkz, 0 },
2548 { X86::VANDPSZrrkz, X86::VANDPSZrmkz, 0 },
2549 { X86::VDIVPDZrrkz, X86::VDIVPDZrmkz, 0 },
2550 { X86::VDIVPSZrrkz, X86::VDIVPSZrmkz, 0 },
2551 { X86::VDIVSDZrr_Intkz, X86::VDIVSDZrm_Intkz, TB_NO_REVERSE },
2552 { X86::VDIVSSZrr_Intkz, X86::VDIVSSZrm_Intkz, TB_NO_REVERSE },
2553 { X86::VINSERTF32x4Zrrkz, X86::VINSERTF32x4Zrmkz, 0 },
2554 { X86::VINSERTF32x8Zrrkz, X86::VINSERTF32x8Zrmkz, 0 },
2555 { X86::VINSERTF64x2Zrrkz, X86::VINSERTF64x2Zrmkz, 0 },
2556 { X86::VINSERTF64x4Zrrkz, X86::VINSERTF64x4Zrmkz, 0 },
2557 { X86::VINSERTI32x4Zrrkz, X86::VINSERTI32x4Zrmkz, 0 },
2558 { X86::VINSERTI32x8Zrrkz, X86::VINSERTI32x8Zrmkz, 0 },
2559 { X86::VINSERTI64x2Zrrkz, X86::VINSERTI64x2Zrmkz, 0 },
2560 { X86::VINSERTI64x4Zrrkz, X86::VINSERTI64x4Zrmkz, 0 },
2561 { X86::VMAXCPDZrrkz, X86::VMAXCPDZrmkz, 0 },
2562 { X86::VMAXCPSZrrkz, X86::VMAXCPSZrmkz, 0 },
2563 { X86::VMAXPDZrrkz, X86::VMAXPDZrmkz, 0 },
2564 { X86::VMAXPSZrrkz, X86::VMAXPSZrmkz, 0 },
2565 { X86::VMAXSDZrr_Intkz, X86::VMAXSDZrm_Intkz, 0 },
2566 { X86::VMAXSSZrr_Intkz, X86::VMAXSSZrm_Intkz, 0 },
2567 { X86::VMINCPDZrrkz, X86::VMINCPDZrmkz, 0 },
2568 { X86::VMINCPSZrrkz, X86::VMINCPSZrmkz, 0 },
2569 { X86::VMINPDZrrkz, X86::VMINPDZrmkz, 0 },
2570 { X86::VMINPSZrrkz, X86::VMINPSZrmkz, 0 },
2571 { X86::VMINSDZrr_Intkz, X86::VMINSDZrm_Intkz, 0 },
2572 { X86::VMINSSZrr_Intkz, X86::VMINSSZrm_Intkz, 0 },
2573 { X86::VMULPDZrrkz, X86::VMULPDZrmkz, 0 },
2574 { X86::VMULPSZrrkz, X86::VMULPSZrmkz, 0 },
2575 { X86::VMULSDZrr_Intkz, X86::VMULSDZrm_Intkz, TB_NO_REVERSE },
2576 { X86::VMULSSZrr_Intkz, X86::VMULSSZrm_Intkz, TB_NO_REVERSE },
2577 { X86::VORPDZrrkz, X86::VORPDZrmkz, 0 },
2578 { X86::VORPSZrrkz, X86::VORPSZrmkz, 0 },
2579 { X86::VPACKSSDWZrrkz, X86::VPACKSSDWZrmkz, 0 },
2580 { X86::VPACKSSWBZrrkz, X86::VPACKSSWBZrmkz, 0 },
2581 { X86::VPACKUSDWZrrkz, X86::VPACKUSDWZrmkz, 0 },
2582 { X86::VPACKUSWBZrrkz, X86::VPACKUSWBZrmkz, 0 },
2583 { X86::VPADDBZrrkz, X86::VPADDBZrmkz, 0 },
2584 { X86::VPADDDZrrkz, X86::VPADDDZrmkz, 0 },
2585 { X86::VPADDQZrrkz, X86::VPADDQZrmkz, 0 },
2586 { X86::VPADDSBZrrkz, X86::VPADDSBZrmkz, 0 },
2587 { X86::VPADDSWZrrkz, X86::VPADDSWZrmkz, 0 },
2588 { X86::VPADDUSBZrrkz, X86::VPADDUSBZrmkz, 0 },
2589 { X86::VPADDUSWZrrkz, X86::VPADDUSWZrmkz, 0 },
2590 { X86::VPADDWZrrkz, X86::VPADDWZrmkz, 0 },
2591 { X86::VPALIGNRZrrikz, X86::VPALIGNRZrmikz, 0 },
2592 { X86::VPANDDZrrkz, X86::VPANDDZrmkz, 0 },
2593 { X86::VPANDNDZrrkz, X86::VPANDNDZrmkz, 0 },
2594 { X86::VPANDNQZrrkz, X86::VPANDNQZrmkz, 0 },
2595 { X86::VPANDQZrrkz, X86::VPANDQZrmkz, 0 },
2596 { X86::VPAVGBZrrkz, X86::VPAVGBZrmkz, 0 },
2597 { X86::VPAVGWZrrkz, X86::VPAVGWZrmkz, 0 },
2598 { X86::VPERMBZrrkz, X86::VPERMBZrmkz, 0 },
2599 { X86::VPERMDZrrkz, X86::VPERMDZrmkz, 0 },
2600 { X86::VPERMILPDZrrkz, X86::VPERMILPDZrmkz, 0 },
2601 { X86::VPERMILPSZrrkz, X86::VPERMILPSZrmkz, 0 },
2602 { X86::VPERMPDZrrkz, X86::VPERMPDZrmkz, 0 },
2603 { X86::VPERMPSZrrkz, X86::VPERMPSZrmkz, 0 },
2604 { X86::VPERMQZrrkz, X86::VPERMQZrmkz, 0 },
2605 { X86::VPERMWZrrkz, X86::VPERMWZrmkz, 0 },
2606 { X86::VPMADDUBSWZrrkz, X86::VPMADDUBSWZrmkz, 0 },
2607 { X86::VPMADDWDZrrkz, X86::VPMADDWDZrmkz, 0 },
2608 { X86::VPMAXSBZrrkz, X86::VPMAXSBZrmkz, 0 },
2609 { X86::VPMAXSDZrrkz, X86::VPMAXSDZrmkz, 0 },
2610 { X86::VPMAXSQZrrkz, X86::VPMAXSQZrmkz, 0 },
2611 { X86::VPMAXSWZrrkz, X86::VPMAXSWZrmkz, 0 },
2612 { X86::VPMAXUBZrrkz, X86::VPMAXUBZrmkz, 0 },
2613 { X86::VPMAXUDZrrkz, X86::VPMAXUDZrmkz, 0 },
2614 { X86::VPMAXUQZrrkz, X86::VPMAXUQZrmkz, 0 },
2615 { X86::VPMAXUWZrrkz, X86::VPMAXUWZrmkz, 0 },
2616 { X86::VPMINSBZrrkz, X86::VPMINSBZrmkz, 0 },
2617 { X86::VPMINSDZrrkz, X86::VPMINSDZrmkz, 0 },
2618 { X86::VPMINSQZrrkz, X86::VPMINSQZrmkz, 0 },
2619 { X86::VPMINSWZrrkz, X86::VPMINSWZrmkz, 0 },
2620 { X86::VPMINUBZrrkz, X86::VPMINUBZrmkz, 0 },
2621 { X86::VPMINUDZrrkz, X86::VPMINUDZrmkz, 0 },
2622 { X86::VPMINUQZrrkz, X86::VPMINUQZrmkz, 0 },
2623 { X86::VPMINUWZrrkz, X86::VPMINUWZrmkz, 0 },
2624 { X86::VPMULLDZrrkz, X86::VPMULLDZrmkz, 0 },
2625 { X86::VPMULLQZrrkz, X86::VPMULLQZrmkz, 0 },
2626 { X86::VPMULLWZrrkz, X86::VPMULLWZrmkz, 0 },
2627 { X86::VPMULDQZrrkz, X86::VPMULDQZrmkz, 0 },
2628 { X86::VPMULUDQZrrkz, X86::VPMULUDQZrmkz, 0 },
2629 { X86::VPORDZrrkz, X86::VPORDZrmkz, 0 },
2630 { X86::VPORQZrrkz, X86::VPORQZrmkz, 0 },
2631 { X86::VPSHUFBZrrkz, X86::VPSHUFBZrmkz, 0 },
2632 { X86::VPSLLDZrrkz, X86::VPSLLDZrmkz, 0 },
2633 { X86::VPSLLQZrrkz, X86::VPSLLQZrmkz, 0 },
2634 { X86::VPSLLVDZrrkz, X86::VPSLLVDZrmkz, 0 },
2635 { X86::VPSLLVQZrrkz, X86::VPSLLVQZrmkz, 0 },
2636 { X86::VPSLLVWZrrkz, X86::VPSLLVWZrmkz, 0 },
2637 { X86::VPSLLWZrrkz, X86::VPSLLWZrmkz, 0 },
2638 { X86::VPSRADZrrkz, X86::VPSRADZrmkz, 0 },
2639 { X86::VPSRAQZrrkz, X86::VPSRAQZrmkz, 0 },
2640 { X86::VPSRAVDZrrkz, X86::VPSRAVDZrmkz, 0 },
2641 { X86::VPSRAVQZrrkz, X86::VPSRAVQZrmkz, 0 },
2642 { X86::VPSRAVWZrrkz, X86::VPSRAVWZrmkz, 0 },
2643 { X86::VPSRAWZrrkz, X86::VPSRAWZrmkz, 0 },
2644 { X86::VPSRLDZrrkz, X86::VPSRLDZrmkz, 0 },
2645 { X86::VPSRLQZrrkz, X86::VPSRLQZrmkz, 0 },
2646 { X86::VPSRLVDZrrkz, X86::VPSRLVDZrmkz, 0 },
2647 { X86::VPSRLVQZrrkz, X86::VPSRLVQZrmkz, 0 },
2648 { X86::VPSRLVWZrrkz, X86::VPSRLVWZrmkz, 0 },
2649 { X86::VPSRLWZrrkz, X86::VPSRLWZrmkz, 0 },
2650 { X86::VPSUBBZrrkz, X86::VPSUBBZrmkz, 0 },
2651 { X86::VPSUBDZrrkz, X86::VPSUBDZrmkz, 0 },
2652 { X86::VPSUBQZrrkz, X86::VPSUBQZrmkz, 0 },
2653 { X86::VPSUBSBZrrkz, X86::VPSUBSBZrmkz, 0 },
2654 { X86::VPSUBSWZrrkz, X86::VPSUBSWZrmkz, 0 },
2655 { X86::VPSUBUSBZrrkz, X86::VPSUBUSBZrmkz, 0 },
2656 { X86::VPSUBUSWZrrkz, X86::VPSUBUSWZrmkz, 0 },
2657 { X86::VPSUBWZrrkz, X86::VPSUBWZrmkz, 0 },
2658 { X86::VPUNPCKHBWZrrkz, X86::VPUNPCKHBWZrmkz, 0 },
2659 { X86::VPUNPCKHDQZrrkz, X86::VPUNPCKHDQZrmkz, 0 },
2660 { X86::VPUNPCKHQDQZrrkz, X86::VPUNPCKHQDQZrmkz, 0 },
2661 { X86::VPUNPCKHWDZrrkz, X86::VPUNPCKHWDZrmkz, 0 },
2662 { X86::VPUNPCKLBWZrrkz, X86::VPUNPCKLBWZrmkz, 0 },
2663 { X86::VPUNPCKLDQZrrkz, X86::VPUNPCKLDQZrmkz, 0 },
2664 { X86::VPUNPCKLQDQZrrkz, X86::VPUNPCKLQDQZrmkz, 0 },
2665 { X86::VPUNPCKLWDZrrkz, X86::VPUNPCKLWDZrmkz, 0 },
2666 { X86::VPXORDZrrkz, X86::VPXORDZrmkz, 0 },
2667 { X86::VPXORQZrrkz, X86::VPXORQZrmkz, 0 },
2668 { X86::VSHUFPDZrrikz, X86::VSHUFPDZrmikz, 0 },
2669 { X86::VSHUFPSZrrikz, X86::VSHUFPSZrmikz, 0 },
2670 { X86::VSUBPDZrrkz, X86::VSUBPDZrmkz, 0 },
2671 { X86::VSUBPSZrrkz, X86::VSUBPSZrmkz, 0 },
2672 { X86::VSUBSDZrr_Intkz, X86::VSUBSDZrm_Intkz, TB_NO_REVERSE },
2673 { X86::VSUBSSZrr_Intkz, X86::VSUBSSZrm_Intkz, TB_NO_REVERSE },
2674 { X86::VUNPCKHPDZrrkz, X86::VUNPCKHPDZrmkz, 0 },
2675 { X86::VUNPCKHPSZrrkz, X86::VUNPCKHPSZrmkz, 0 },
2676 { X86::VUNPCKLPDZrrkz, X86::VUNPCKLPDZrmkz, 0 },
2677 { X86::VUNPCKLPSZrrkz, X86::VUNPCKLPSZrmkz, 0 },
2678 { X86::VXORPDZrrkz, X86::VXORPDZrmkz, 0 },
2679 { X86::VXORPSZrrkz, X86::VXORPSZrmkz, 0 },
2680
2681 // AVX-512{F,VL} masked arithmetic instructions 256-bit
2682 { X86::VADDPDZ256rrkz, X86::VADDPDZ256rmkz, 0 },
2683 { X86::VADDPSZ256rrkz, X86::VADDPSZ256rmkz, 0 },
2684 { X86::VALIGNDZ256rrikz, X86::VALIGNDZ256rmikz, 0 },
2685 { X86::VALIGNQZ256rrikz, X86::VALIGNQZ256rmikz, 0 },
2686 { X86::VANDNPDZ256rrkz, X86::VANDNPDZ256rmkz, 0 },
2687 { X86::VANDNPSZ256rrkz, X86::VANDNPSZ256rmkz, 0 },
2688 { X86::VANDPDZ256rrkz, X86::VANDPDZ256rmkz, 0 },
2689 { X86::VANDPSZ256rrkz, X86::VANDPSZ256rmkz, 0 },
2690 { X86::VDIVPDZ256rrkz, X86::VDIVPDZ256rmkz, 0 },
2691 { X86::VDIVPSZ256rrkz, X86::VDIVPSZ256rmkz, 0 },
2692 { X86::VINSERTF32x4Z256rrkz, X86::VINSERTF32x4Z256rmkz, 0 },
2693 { X86::VINSERTF64x2Z256rrkz, X86::VINSERTF64x2Z256rmkz, 0 },
2694 { X86::VINSERTI32x4Z256rrkz, X86::VINSERTI32x4Z256rmkz, 0 },
2695 { X86::VINSERTI64x2Z256rrkz, X86::VINSERTI64x2Z256rmkz, 0 },
2696 { X86::VMAXCPDZ256rrkz, X86::VMAXCPDZ256rmkz, 0 },
2697 { X86::VMAXCPSZ256rrkz, X86::VMAXCPSZ256rmkz, 0 },
2698 { X86::VMAXPDZ256rrkz, X86::VMAXPDZ256rmkz, 0 },
2699 { X86::VMAXPSZ256rrkz, X86::VMAXPSZ256rmkz, 0 },
2700 { X86::VMINCPDZ256rrkz, X86::VMINCPDZ256rmkz, 0 },
2701 { X86::VMINCPSZ256rrkz, X86::VMINCPSZ256rmkz, 0 },
2702 { X86::VMINPDZ256rrkz, X86::VMINPDZ256rmkz, 0 },
2703 { X86::VMINPSZ256rrkz, X86::VMINPSZ256rmkz, 0 },
2704 { X86::VMULPDZ256rrkz, X86::VMULPDZ256rmkz, 0 },
2705 { X86::VMULPSZ256rrkz, X86::VMULPSZ256rmkz, 0 },
2706 { X86::VORPDZ256rrkz, X86::VORPDZ256rmkz, 0 },
2707 { X86::VORPSZ256rrkz, X86::VORPSZ256rmkz, 0 },
2708 { X86::VPACKSSDWZ256rrkz, X86::VPACKSSDWZ256rmkz, 0 },
2709 { X86::VPACKSSWBZ256rrkz, X86::VPACKSSWBZ256rmkz, 0 },
2710 { X86::VPACKUSDWZ256rrkz, X86::VPACKUSDWZ256rmkz, 0 },
2711 { X86::VPACKUSWBZ256rrkz, X86::VPACKUSWBZ256rmkz, 0 },
2712 { X86::VPADDBZ256rrkz, X86::VPADDBZ256rmkz, 0 },
2713 { X86::VPADDDZ256rrkz, X86::VPADDDZ256rmkz, 0 },
2714 { X86::VPADDQZ256rrkz, X86::VPADDQZ256rmkz, 0 },
2715 { X86::VPADDSBZ256rrkz, X86::VPADDSBZ256rmkz, 0 },
2716 { X86::VPADDSWZ256rrkz, X86::VPADDSWZ256rmkz, 0 },
2717 { X86::VPADDUSBZ256rrkz, X86::VPADDUSBZ256rmkz, 0 },
2718 { X86::VPADDUSWZ256rrkz, X86::VPADDUSWZ256rmkz, 0 },
2719 { X86::VPADDWZ256rrkz, X86::VPADDWZ256rmkz, 0 },
2720 { X86::VPALIGNRZ256rrikz, X86::VPALIGNRZ256rmikz, 0 },
2721 { X86::VPANDDZ256rrkz, X86::VPANDDZ256rmkz, 0 },
2722 { X86::VPANDNDZ256rrkz, X86::VPANDNDZ256rmkz, 0 },
2723 { X86::VPANDNQZ256rrkz, X86::VPANDNQZ256rmkz, 0 },
2724 { X86::VPANDQZ256rrkz, X86::VPANDQZ256rmkz, 0 },
2725 { X86::VPAVGBZ256rrkz, X86::VPAVGBZ256rmkz, 0 },
2726 { X86::VPAVGWZ256rrkz, X86::VPAVGWZ256rmkz, 0 },
2727 { X86::VPERMBZ256rrkz, X86::VPERMBZ256rmkz, 0 },
2728 { X86::VPERMDZ256rrkz, X86::VPERMDZ256rmkz, 0 },
2729 { X86::VPERMILPDZ256rrkz, X86::VPERMILPDZ256rmkz, 0 },
2730 { X86::VPERMILPSZ256rrkz, X86::VPERMILPSZ256rmkz, 0 },
2731 { X86::VPERMPDZ256rrkz, X86::VPERMPDZ256rmkz, 0 },
2732 { X86::VPERMPSZ256rrkz, X86::VPERMPSZ256rmkz, 0 },
2733 { X86::VPERMQZ256rrkz, X86::VPERMQZ256rmkz, 0 },
2734 { X86::VPERMWZ256rrkz, X86::VPERMWZ256rmkz, 0 },
2735 { X86::VPMADDUBSWZ256rrkz, X86::VPMADDUBSWZ256rmkz, 0 },
2736 { X86::VPMADDWDZ256rrkz, X86::VPMADDWDZ256rmkz, 0 },
2737 { X86::VPMAXSBZ256rrkz, X86::VPMAXSBZ256rmkz, 0 },
2738 { X86::VPMAXSDZ256rrkz, X86::VPMAXSDZ256rmkz, 0 },
2739 { X86::VPMAXSQZ256rrkz, X86::VPMAXSQZ256rmkz, 0 },
2740 { X86::VPMAXSWZ256rrkz, X86::VPMAXSWZ256rmkz, 0 },
2741 { X86::VPMAXUBZ256rrkz, X86::VPMAXUBZ256rmkz, 0 },
2742 { X86::VPMAXUDZ256rrkz, X86::VPMAXUDZ256rmkz, 0 },
2743 { X86::VPMAXUQZ256rrkz, X86::VPMAXUQZ256rmkz, 0 },
2744 { X86::VPMAXUWZ256rrkz, X86::VPMAXUWZ256rmkz, 0 },
2745 { X86::VPMINSBZ256rrkz, X86::VPMINSBZ256rmkz, 0 },
2746 { X86::VPMINSDZ256rrkz, X86::VPMINSDZ256rmkz, 0 },
2747 { X86::VPMINSQZ256rrkz, X86::VPMINSQZ256rmkz, 0 },
2748 { X86::VPMINSWZ256rrkz, X86::VPMINSWZ256rmkz, 0 },
2749 { X86::VPMINUBZ256rrkz, X86::VPMINUBZ256rmkz, 0 },
2750 { X86::VPMINUDZ256rrkz, X86::VPMINUDZ256rmkz, 0 },
2751 { X86::VPMINUQZ256rrkz, X86::VPMINUQZ256rmkz, 0 },
2752 { X86::VPMINUWZ256rrkz, X86::VPMINUWZ256rmkz, 0 },
2753 { X86::VPMULDQZ256rrkz, X86::VPMULDQZ256rmkz, 0 },
2754 { X86::VPMULLDZ256rrkz, X86::VPMULLDZ256rmkz, 0 },
2755 { X86::VPMULLQZ256rrkz, X86::VPMULLQZ256rmkz, 0 },
2756 { X86::VPMULLWZ256rrkz, X86::VPMULLWZ256rmkz, 0 },
2757 { X86::VPMULUDQZ256rrkz, X86::VPMULUDQZ256rmkz, 0 },
2758 { X86::VPORDZ256rrkz, X86::VPORDZ256rmkz, 0 },
2759 { X86::VPORQZ256rrkz, X86::VPORQZ256rmkz, 0 },
2760 { X86::VPSHUFBZ256rrkz, X86::VPSHUFBZ256rmkz, 0 },
2761 { X86::VPSLLDZ256rrkz, X86::VPSLLDZ256rmkz, 0 },
2762 { X86::VPSLLQZ256rrkz, X86::VPSLLQZ256rmkz, 0 },
2763 { X86::VPSLLVDZ256rrkz, X86::VPSLLVDZ256rmkz, 0 },
2764 { X86::VPSLLVQZ256rrkz, X86::VPSLLVQZ256rmkz, 0 },
2765 { X86::VPSLLVWZ256rrkz, X86::VPSLLVWZ256rmkz, 0 },
2766 { X86::VPSLLWZ256rrkz, X86::VPSLLWZ256rmkz, 0 },
2767 { X86::VPSRADZ256rrkz, X86::VPSRADZ256rmkz, 0 },
2768 { X86::VPSRAQZ256rrkz, X86::VPSRAQZ256rmkz, 0 },
2769 { X86::VPSRAVDZ256rrkz, X86::VPSRAVDZ256rmkz, 0 },
2770 { X86::VPSRAVQZ256rrkz, X86::VPSRAVQZ256rmkz, 0 },
2771 { X86::VPSRAVWZ256rrkz, X86::VPSRAVWZ256rmkz, 0 },
2772 { X86::VPSRAWZ256rrkz, X86::VPSRAWZ256rmkz, 0 },
2773 { X86::VPSRLDZ256rrkz, X86::VPSRLDZ256rmkz, 0 },
2774 { X86::VPSRLQZ256rrkz, X86::VPSRLQZ256rmkz, 0 },
2775 { X86::VPSRLVDZ256rrkz, X86::VPSRLVDZ256rmkz, 0 },
2776 { X86::VPSRLVQZ256rrkz, X86::VPSRLVQZ256rmkz, 0 },
2777 { X86::VPSRLVWZ256rrkz, X86::VPSRLVWZ256rmkz, 0 },
2778 { X86::VPSRLWZ256rrkz, X86::VPSRLWZ256rmkz, 0 },
2779 { X86::VPSUBBZ256rrkz, X86::VPSUBBZ256rmkz, 0 },
2780 { X86::VPSUBDZ256rrkz, X86::VPSUBDZ256rmkz, 0 },
2781 { X86::VPSUBQZ256rrkz, X86::VPSUBQZ256rmkz, 0 },
2782 { X86::VPSUBSBZ256rrkz, X86::VPSUBSBZ256rmkz, 0 },
2783 { X86::VPSUBSWZ256rrkz, X86::VPSUBSWZ256rmkz, 0 },
2784 { X86::VPSUBUSBZ256rrkz, X86::VPSUBUSBZ256rmkz, 0 },
2785 { X86::VPSUBUSWZ256rrkz, X86::VPSUBUSWZ256rmkz, 0 },
2786 { X86::VPSUBWZ256rrkz, X86::VPSUBWZ256rmkz, 0 },
2787 { X86::VPUNPCKHBWZ256rrkz, X86::VPUNPCKHBWZ256rmkz, 0 },
2788 { X86::VPUNPCKHDQZ256rrkz, X86::VPUNPCKHDQZ256rmkz, 0 },
2789 { X86::VPUNPCKHQDQZ256rrkz, X86::VPUNPCKHQDQZ256rmkz, 0 },
2790 { X86::VPUNPCKHWDZ256rrkz, X86::VPUNPCKHWDZ256rmkz, 0 },
2791 { X86::VPUNPCKLBWZ256rrkz, X86::VPUNPCKLBWZ256rmkz, 0 },
2792 { X86::VPUNPCKLDQZ256rrkz, X86::VPUNPCKLDQZ256rmkz, 0 },
2793 { X86::VPUNPCKLQDQZ256rrkz, X86::VPUNPCKLQDQZ256rmkz, 0 },
2794 { X86::VPUNPCKLWDZ256rrkz, X86::VPUNPCKLWDZ256rmkz, 0 },
2795 { X86::VPXORDZ256rrkz, X86::VPXORDZ256rmkz, 0 },
2796 { X86::VPXORQZ256rrkz, X86::VPXORQZ256rmkz, 0 },
2797 { X86::VSHUFPDZ256rrikz, X86::VSHUFPDZ256rmikz, 0 },
2798 { X86::VSHUFPSZ256rrikz, X86::VSHUFPSZ256rmikz, 0 },
2799 { X86::VSUBPDZ256rrkz, X86::VSUBPDZ256rmkz, 0 },
2800 { X86::VSUBPSZ256rrkz, X86::VSUBPSZ256rmkz, 0 },
2801 { X86::VUNPCKHPDZ256rrkz, X86::VUNPCKHPDZ256rmkz, 0 },
2802 { X86::VUNPCKHPSZ256rrkz, X86::VUNPCKHPSZ256rmkz, 0 },
2803 { X86::VUNPCKLPDZ256rrkz, X86::VUNPCKLPDZ256rmkz, 0 },
2804 { X86::VUNPCKLPSZ256rrkz, X86::VUNPCKLPSZ256rmkz, 0 },
2805 { X86::VXORPDZ256rrkz, X86::VXORPDZ256rmkz, 0 },
2806 { X86::VXORPSZ256rrkz, X86::VXORPSZ256rmkz, 0 },
2807
2808 // AVX-512{F,VL} masked arithmetic instructions 128-bit
2809 { X86::VADDPDZ128rrkz, X86::VADDPDZ128rmkz, 0 },
2810 { X86::VADDPSZ128rrkz, X86::VADDPSZ128rmkz, 0 },
2811 { X86::VALIGNDZ128rrikz, X86::VALIGNDZ128rmikz, 0 },
2812 { X86::VALIGNQZ128rrikz, X86::VALIGNQZ128rmikz, 0 },
2813 { X86::VANDNPDZ128rrkz, X86::VANDNPDZ128rmkz, 0 },
2814 { X86::VANDNPSZ128rrkz, X86::VANDNPSZ128rmkz, 0 },
2815 { X86::VANDPDZ128rrkz, X86::VANDPDZ128rmkz, 0 },
2816 { X86::VANDPSZ128rrkz, X86::VANDPSZ128rmkz, 0 },
2817 { X86::VDIVPDZ128rrkz, X86::VDIVPDZ128rmkz, 0 },
2818 { X86::VDIVPSZ128rrkz, X86::VDIVPSZ128rmkz, 0 },
2819 { X86::VMAXCPDZ128rrkz, X86::VMAXCPDZ128rmkz, 0 },
2820 { X86::VMAXCPSZ128rrkz, X86::VMAXCPSZ128rmkz, 0 },
2821 { X86::VMAXPDZ128rrkz, X86::VMAXPDZ128rmkz, 0 },
2822 { X86::VMAXPSZ128rrkz, X86::VMAXPSZ128rmkz, 0 },
2823 { X86::VMINCPDZ128rrkz, X86::VMINCPDZ128rmkz, 0 },
2824 { X86::VMINCPSZ128rrkz, X86::VMINCPSZ128rmkz, 0 },
2825 { X86::VMINPDZ128rrkz, X86::VMINPDZ128rmkz, 0 },
2826 { X86::VMINPSZ128rrkz, X86::VMINPSZ128rmkz, 0 },
2827 { X86::VMULPDZ128rrkz, X86::VMULPDZ128rmkz, 0 },
2828 { X86::VMULPSZ128rrkz, X86::VMULPSZ128rmkz, 0 },
2829 { X86::VORPDZ128rrkz, X86::VORPDZ128rmkz, 0 },
2830 { X86::VORPSZ128rrkz, X86::VORPSZ128rmkz, 0 },
2831 { X86::VPACKSSDWZ128rrkz, X86::VPACKSSDWZ128rmkz, 0 },
2832 { X86::VPACKSSWBZ128rrkz, X86::VPACKSSWBZ128rmkz, 0 },
2833 { X86::VPACKUSDWZ128rrkz, X86::VPACKUSDWZ128rmkz, 0 },
2834 { X86::VPACKUSWBZ128rrkz, X86::VPACKUSWBZ128rmkz, 0 },
2835 { X86::VPADDBZ128rrkz, X86::VPADDBZ128rmkz, 0 },
2836 { X86::VPADDDZ128rrkz, X86::VPADDDZ128rmkz, 0 },
2837 { X86::VPADDQZ128rrkz, X86::VPADDQZ128rmkz, 0 },
2838 { X86::VPADDSBZ128rrkz, X86::VPADDSBZ128rmkz, 0 },
2839 { X86::VPADDSWZ128rrkz, X86::VPADDSWZ128rmkz, 0 },
2840 { X86::VPADDUSBZ128rrkz, X86::VPADDUSBZ128rmkz, 0 },
2841 { X86::VPADDUSWZ128rrkz, X86::VPADDUSWZ128rmkz, 0 },
2842 { X86::VPADDWZ128rrkz, X86::VPADDWZ128rmkz, 0 },
2843 { X86::VPALIGNRZ128rrikz, X86::VPALIGNRZ128rmikz, 0 },
2844 { X86::VPANDDZ128rrkz, X86::VPANDDZ128rmkz, 0 },
2845 { X86::VPANDNDZ128rrkz, X86::VPANDNDZ128rmkz, 0 },
2846 { X86::VPANDNQZ128rrkz, X86::VPANDNQZ128rmkz, 0 },
2847 { X86::VPANDQZ128rrkz, X86::VPANDQZ128rmkz, 0 },
2848 { X86::VPAVGBZ128rrkz, X86::VPAVGBZ128rmkz, 0 },
2849 { X86::VPAVGWZ128rrkz, X86::VPAVGWZ128rmkz, 0 },
2850 { X86::VPERMBZ128rrkz, X86::VPERMBZ128rmkz, 0 },
2851 { X86::VPERMILPDZ128rrkz, X86::VPERMILPDZ128rmkz, 0 },
2852 { X86::VPERMILPSZ128rrkz, X86::VPERMILPSZ128rmkz, 0 },
2853 { X86::VPERMWZ128rrkz, X86::VPERMWZ128rmkz, 0 },
2854 { X86::VPMADDUBSWZ128rrkz, X86::VPMADDUBSWZ128rmkz, 0 },
2855 { X86::VPMADDWDZ128rrkz, X86::VPMADDWDZ128rmkz, 0 },
2856 { X86::VPMAXSBZ128rrkz, X86::VPMAXSBZ128rmkz, 0 },
2857 { X86::VPMAXSDZ128rrkz, X86::VPMAXSDZ128rmkz, 0 },
2858 { X86::VPMAXSQZ128rrkz, X86::VPMAXSQZ128rmkz, 0 },
2859 { X86::VPMAXSWZ128rrkz, X86::VPMAXSWZ128rmkz, 0 },
2860 { X86::VPMAXUBZ128rrkz, X86::VPMAXUBZ128rmkz, 0 },
2861 { X86::VPMAXUDZ128rrkz, X86::VPMAXUDZ128rmkz, 0 },
2862 { X86::VPMAXUQZ128rrkz, X86::VPMAXUQZ128rmkz, 0 },
2863 { X86::VPMAXUWZ128rrkz, X86::VPMAXUWZ128rmkz, 0 },
2864 { X86::VPMINSBZ128rrkz, X86::VPMINSBZ128rmkz, 0 },
2865 { X86::VPMINSDZ128rrkz, X86::VPMINSDZ128rmkz, 0 },
2866 { X86::VPMINSQZ128rrkz, X86::VPMINSQZ128rmkz, 0 },
2867 { X86::VPMINSWZ128rrkz, X86::VPMINSWZ128rmkz, 0 },
2868 { X86::VPMINUBZ128rrkz, X86::VPMINUBZ128rmkz, 0 },
2869 { X86::VPMINUDZ128rrkz, X86::VPMINUDZ128rmkz, 0 },
2870 { X86::VPMINUQZ128rrkz, X86::VPMINUQZ128rmkz, 0 },
2871 { X86::VPMINUWZ128rrkz, X86::VPMINUWZ128rmkz, 0 },
2872 { X86::VPMULDQZ128rrkz, X86::VPMULDQZ128rmkz, 0 },
2873 { X86::VPMULLDZ128rrkz, X86::VPMULLDZ128rmkz, 0 },
2874 { X86::VPMULLQZ128rrkz, X86::VPMULLQZ128rmkz, 0 },
2875 { X86::VPMULLWZ128rrkz, X86::VPMULLWZ128rmkz, 0 },
2876 { X86::VPMULUDQZ128rrkz, X86::VPMULUDQZ128rmkz, 0 },
2877 { X86::VPORDZ128rrkz, X86::VPORDZ128rmkz, 0 },
2878 { X86::VPORQZ128rrkz, X86::VPORQZ128rmkz, 0 },
2879 { X86::VPSHUFBZ128rrkz, X86::VPSHUFBZ128rmkz, 0 },
2880 { X86::VPSLLDZ128rrkz, X86::VPSLLDZ128rmkz, 0 },
2881 { X86::VPSLLQZ128rrkz, X86::VPSLLQZ128rmkz, 0 },
2882 { X86::VPSLLVDZ128rrkz, X86::VPSLLVDZ128rmkz, 0 },
2883 { X86::VPSLLVQZ128rrkz, X86::VPSLLVQZ128rmkz, 0 },
2884 { X86::VPSLLVWZ128rrkz, X86::VPSLLVWZ128rmkz, 0 },
2885 { X86::VPSLLWZ128rrkz, X86::VPSLLWZ128rmkz, 0 },
2886 { X86::VPSRADZ128rrkz, X86::VPSRADZ128rmkz, 0 },
2887 { X86::VPSRAQZ128rrkz, X86::VPSRAQZ128rmkz, 0 },
2888 { X86::VPSRAVDZ128rrkz, X86::VPSRAVDZ128rmkz, 0 },
2889 { X86::VPSRAVQZ128rrkz, X86::VPSRAVQZ128rmkz, 0 },
2890 { X86::VPSRAVWZ128rrkz, X86::VPSRAVWZ128rmkz, 0 },
2891 { X86::VPSRAWZ128rrkz, X86::VPSRAWZ128rmkz, 0 },
2892 { X86::VPSRLDZ128rrkz, X86::VPSRLDZ128rmkz, 0 },
2893 { X86::VPSRLQZ128rrkz, X86::VPSRLQZ128rmkz, 0 },
2894 { X86::VPSRLVDZ128rrkz, X86::VPSRLVDZ128rmkz, 0 },
2895 { X86::VPSRLVQZ128rrkz, X86::VPSRLVQZ128rmkz, 0 },
2896 { X86::VPSRLVWZ128rrkz, X86::VPSRLVWZ128rmkz, 0 },
2897 { X86::VPSRLWZ128rrkz, X86::VPSRLWZ128rmkz, 0 },
2898 { X86::VPSUBBZ128rrkz, X86::VPSUBBZ128rmkz, 0 },
2899 { X86::VPSUBDZ128rrkz, X86::VPSUBDZ128rmkz, 0 },
2900 { X86::VPSUBQZ128rrkz, X86::VPSUBQZ128rmkz, 0 },
2901 { X86::VPSUBSBZ128rrkz, X86::VPSUBSBZ128rmkz, 0 },
2902 { X86::VPSUBSWZ128rrkz, X86::VPSUBSWZ128rmkz, 0 },
2903 { X86::VPSUBUSBZ128rrkz, X86::VPSUBUSBZ128rmkz, 0 },
2904 { X86::VPSUBUSWZ128rrkz, X86::VPSUBUSWZ128rmkz, 0 },
2905 { X86::VPSUBWZ128rrkz, X86::VPSUBWZ128rmkz, 0 },
2906 { X86::VPUNPCKHBWZ128rrkz, X86::VPUNPCKHBWZ128rmkz, 0 },
2907 { X86::VPUNPCKHDQZ128rrkz, X86::VPUNPCKHDQZ128rmkz, 0 },
2908 { X86::VPUNPCKHQDQZ128rrkz, X86::VPUNPCKHQDQZ128rmkz, 0 },
2909 { X86::VPUNPCKHWDZ128rrkz, X86::VPUNPCKHWDZ128rmkz, 0 },
2910 { X86::VPUNPCKLBWZ128rrkz, X86::VPUNPCKLBWZ128rmkz, 0 },
2911 { X86::VPUNPCKLDQZ128rrkz, X86::VPUNPCKLDQZ128rmkz, 0 },
2912 { X86::VPUNPCKLQDQZ128rrkz, X86::VPUNPCKLQDQZ128rmkz, 0 },
2913 { X86::VPUNPCKLWDZ128rrkz, X86::VPUNPCKLWDZ128rmkz, 0 },
2914 { X86::VPXORDZ128rrkz, X86::VPXORDZ128rmkz, 0 },
2915 { X86::VPXORQZ128rrkz, X86::VPXORQZ128rmkz, 0 },
2916 { X86::VSHUFPDZ128rrikz, X86::VSHUFPDZ128rmikz, 0 },
2917 { X86::VSHUFPSZ128rrikz, X86::VSHUFPSZ128rmikz, 0 },
2918 { X86::VSUBPDZ128rrkz, X86::VSUBPDZ128rmkz, 0 },
2919 { X86::VSUBPSZ128rrkz, X86::VSUBPSZ128rmkz, 0 },
2920 { X86::VUNPCKHPDZ128rrkz, X86::VUNPCKHPDZ128rmkz, 0 },
2921 { X86::VUNPCKHPSZ128rrkz, X86::VUNPCKHPSZ128rmkz, 0 },
2922 { X86::VUNPCKLPDZ128rrkz, X86::VUNPCKLPDZ128rmkz, 0 },
2923 { X86::VUNPCKLPSZ128rrkz, X86::VUNPCKLPSZ128rmkz, 0 },
2924 { X86::VXORPDZ128rrkz, X86::VXORPDZ128rmkz, 0 },
2925 { X86::VXORPSZ128rrkz, X86::VXORPSZ128rmkz, 0 },
2926
2927 // AVX-512 masked foldable instructions
2928 { X86::VBROADCASTSSZrk, X86::VBROADCASTSSZmk, TB_NO_REVERSE },
2929 { X86::VBROADCASTSDZrk, X86::VBROADCASTSDZmk, TB_NO_REVERSE },
2930 { X86::VPABSBZrrk, X86::VPABSBZrmk, 0 },
2931 { X86::VPABSDZrrk, X86::VPABSDZrmk, 0 },
2932 { X86::VPABSQZrrk, X86::VPABSQZrmk, 0 },
2933 { X86::VPABSWZrrk, X86::VPABSWZrmk, 0 },
2934 { X86::VPERMILPDZrik, X86::VPERMILPDZmik, 0 },
2935 { X86::VPERMILPSZrik, X86::VPERMILPSZmik, 0 },
2936 { X86::VPERMPDZrik, X86::VPERMPDZmik, 0 },
2937 { X86::VPERMQZrik, X86::VPERMQZmik, 0 },
2938 { X86::VPMOVSXBDZrrk, X86::VPMOVSXBDZrmk, 0 },
2939 { X86::VPMOVSXBQZrrk, X86::VPMOVSXBQZrmk, TB_NO_REVERSE },
2940 { X86::VPMOVSXBWZrrk, X86::VPMOVSXBWZrmk, 0 },
2941 { X86::VPMOVSXDQZrrk, X86::VPMOVSXDQZrmk, 0 },
2942 { X86::VPMOVSXWDZrrk, X86::VPMOVSXWDZrmk, 0 },
2943 { X86::VPMOVSXWQZrrk, X86::VPMOVSXWQZrmk, 0 },
2944 { X86::VPMOVZXBDZrrk, X86::VPMOVZXBDZrmk, 0 },
2945 { X86::VPMOVZXBQZrrk, X86::VPMOVZXBQZrmk, TB_NO_REVERSE },
2946 { X86::VPMOVZXBWZrrk, X86::VPMOVZXBWZrmk, 0 },
2947 { X86::VPMOVZXDQZrrk, X86::VPMOVZXDQZrmk, 0 },
2948 { X86::VPMOVZXWDZrrk, X86::VPMOVZXWDZrmk, 0 },
2949 { X86::VPMOVZXWQZrrk, X86::VPMOVZXWQZrmk, 0 },
2950 { X86::VPSHUFDZrik, X86::VPSHUFDZmik, 0 },
2951 { X86::VPSHUFHWZrik, X86::VPSHUFHWZmik, 0 },
2952 { X86::VPSHUFLWZrik, X86::VPSHUFLWZmik, 0 },
2953 { X86::VPSLLDZrik, X86::VPSLLDZmik, 0 },
2954 { X86::VPSLLQZrik, X86::VPSLLQZmik, 0 },
2955 { X86::VPSLLWZrik, X86::VPSLLWZmik, 0 },
2956 { X86::VPSRADZrik, X86::VPSRADZmik, 0 },
2957 { X86::VPSRAQZrik, X86::VPSRAQZmik, 0 },
2958 { X86::VPSRAWZrik, X86::VPSRAWZmik, 0 },
2959 { X86::VPSRLDZrik, X86::VPSRLDZmik, 0 },
2960 { X86::VPSRLQZrik, X86::VPSRLQZmik, 0 },
2961 { X86::VPSRLWZrik, X86::VPSRLWZmik, 0 },
2962
2963 // AVX-512VL 256-bit masked foldable instructions
2964 { X86::VBROADCASTSSZ256rk, X86::VBROADCASTSSZ256mk, TB_NO_REVERSE },
2965 { X86::VBROADCASTSDZ256rk, X86::VBROADCASTSDZ256mk, TB_NO_REVERSE },
2966 { X86::VPABSBZ256rrk, X86::VPABSBZ256rmk, 0 },
2967 { X86::VPABSDZ256rrk, X86::VPABSDZ256rmk, 0 },
2968 { X86::VPABSQZ256rrk, X86::VPABSQZ256rmk, 0 },
2969 { X86::VPABSWZ256rrk, X86::VPABSWZ256rmk, 0 },
2970 { X86::VPERMILPDZ256rik, X86::VPERMILPDZ256mik, 0 },
2971 { X86::VPERMILPSZ256rik, X86::VPERMILPSZ256mik, 0 },
2972 { X86::VPERMPDZ256rik, X86::VPERMPDZ256mik, 0 },
2973 { X86::VPERMQZ256rik, X86::VPERMQZ256mik, 0 },
2974 { X86::VPMOVSXBDZ256rrk, X86::VPMOVSXBDZ256rmk, TB_NO_REVERSE },
2975 { X86::VPMOVSXBQZ256rrk, X86::VPMOVSXBQZ256rmk, TB_NO_REVERSE },
2976 { X86::VPMOVSXBWZ256rrk, X86::VPMOVSXBWZ256rmk, 0 },
2977 { X86::VPMOVSXDQZ256rrk, X86::VPMOVSXDQZ256rmk, 0 },
2978 { X86::VPMOVSXWDZ256rrk, X86::VPMOVSXWDZ256rmk, 0 },
2979 { X86::VPMOVSXWQZ256rrk, X86::VPMOVSXWQZ256rmk, TB_NO_REVERSE },
2980 { X86::VPMOVZXBDZ256rrk, X86::VPMOVZXBDZ256rmk, TB_NO_REVERSE },
2981 { X86::VPMOVZXBQZ256rrk, X86::VPMOVZXBQZ256rmk, TB_NO_REVERSE },
2982 { X86::VPMOVZXBWZ256rrk, X86::VPMOVZXBWZ256rmk, 0 },
2983 { X86::VPMOVZXDQZ256rrk, X86::VPMOVZXDQZ256rmk, 0 },
2984 { X86::VPMOVZXWDZ256rrk, X86::VPMOVZXWDZ256rmk, 0 },
2985 { X86::VPMOVZXWQZ256rrk, X86::VPMOVZXWQZ256rmk, TB_NO_REVERSE },
2986 { X86::VPSHUFDZ256rik, X86::VPSHUFDZ256mik, 0 },
2987 { X86::VPSHUFHWZ256rik, X86::VPSHUFHWZ256mik, 0 },
2988 { X86::VPSHUFLWZ256rik, X86::VPSHUFLWZ256mik, 0 },
2989 { X86::VPSLLDZ256rik, X86::VPSLLDZ256mik, 0 },
2990 { X86::VPSLLQZ256rik, X86::VPSLLQZ256mik, 0 },
2991 { X86::VPSLLWZ256rik, X86::VPSLLWZ256mik, 0 },
2992 { X86::VPSRADZ256rik, X86::VPSRADZ256mik, 0 },
2993 { X86::VPSRAQZ256rik, X86::VPSRAQZ256mik, 0 },
2994 { X86::VPSRAWZ256rik, X86::VPSRAWZ256mik, 0 },
2995 { X86::VPSRLDZ256rik, X86::VPSRLDZ256mik, 0 },
2996 { X86::VPSRLQZ256rik, X86::VPSRLQZ256mik, 0 },
2997 { X86::VPSRLWZ256rik, X86::VPSRLWZ256mik, 0 },
2998
2999 // AVX-512VL 128-bit masked foldable instructions
3000 { X86::VBROADCASTSSZ128rk, X86::VBROADCASTSSZ128mk, TB_NO_REVERSE },
3001 { X86::VPABSBZ128rrk, X86::VPABSBZ128rmk, 0 },
3002 { X86::VPABSDZ128rrk, X86::VPABSDZ128rmk, 0 },
3003 { X86::VPABSQZ128rrk, X86::VPABSQZ128rmk, 0 },
3004 { X86::VPABSWZ128rrk, X86::VPABSWZ128rmk, 0 },
3005 { X86::VPERMILPDZ128rik, X86::VPERMILPDZ128mik, 0 },
3006 { X86::VPERMILPSZ128rik, X86::VPERMILPSZ128mik, 0 },
3007 { X86::VPMOVSXBDZ128rrk, X86::VPMOVSXBDZ128rmk, TB_NO_REVERSE },
3008 { X86::VPMOVSXBQZ128rrk, X86::VPMOVSXBQZ128rmk, TB_NO_REVERSE },
3009 { X86::VPMOVSXBWZ128rrk, X86::VPMOVSXBWZ128rmk, TB_NO_REVERSE },
3010 { X86::VPMOVSXDQZ128rrk, X86::VPMOVSXDQZ128rmk, TB_NO_REVERSE },
3011 { X86::VPMOVSXWDZ128rrk, X86::VPMOVSXWDZ128rmk, TB_NO_REVERSE },
3012 { X86::VPMOVSXWQZ128rrk, X86::VPMOVSXWQZ128rmk, TB_NO_REVERSE },
3013 { X86::VPMOVZXBDZ128rrk, X86::VPMOVZXBDZ128rmk, TB_NO_REVERSE },
3014 { X86::VPMOVZXBQZ128rrk, X86::VPMOVZXBQZ128rmk, TB_NO_REVERSE },
3015 { X86::VPMOVZXBWZ128rrk, X86::VPMOVZXBWZ128rmk, TB_NO_REVERSE },
3016 { X86::VPMOVZXDQZ128rrk, X86::VPMOVZXDQZ128rmk, TB_NO_REVERSE },
3017 { X86::VPMOVZXWDZ128rrk, X86::VPMOVZXWDZ128rmk, TB_NO_REVERSE },
3018 { X86::VPMOVZXWQZ128rrk, X86::VPMOVZXWQZ128rmk, TB_NO_REVERSE },
3019 { X86::VPSHUFDZ128rik, X86::VPSHUFDZ128mik, 0 },
3020 { X86::VPSHUFHWZ128rik, X86::VPSHUFHWZ128mik, 0 },
3021 { X86::VPSHUFLWZ128rik, X86::VPSHUFLWZ128mik, 0 },
3022 { X86::VPSLLDZ128rik, X86::VPSLLDZ128mik, 0 },
3023 { X86::VPSLLQZ128rik, X86::VPSLLQZ128mik, 0 },
3024 { X86::VPSLLWZ128rik, X86::VPSLLWZ128mik, 0 },
3025 { X86::VPSRADZ128rik, X86::VPSRADZ128mik, 0 },
3026 { X86::VPSRAQZ128rik, X86::VPSRAQZ128mik, 0 },
3027 { X86::VPSRAWZ128rik, X86::VPSRAWZ128mik, 0 },
3028 { X86::VPSRLDZ128rik, X86::VPSRLDZ128mik, 0 },
3029 { X86::VPSRLQZ128rik, X86::VPSRLQZ128mik, 0 },
3030 { X86::VPSRLWZ128rik, X86::VPSRLWZ128mik, 0 },
3031 };
3032
3033 for (X86MemoryFoldTableEntry Entry : MemoryFoldTable3) {
3034 AddTableEntry(RegOp2MemOpTable3, MemOp2RegOpTable,
3035 Entry.RegOp, Entry.MemOp,
3036 // Index 3, folded load
3037 Entry.Flags | TB_INDEX_3 | TB_FOLDED_LOAD);
3038 }
3039 auto I = X86InstrFMA3Info::rm_begin();
3040 auto E = X86InstrFMA3Info::rm_end();
3041 for (; I != E; ++I) {
3042 if (!I.getGroup()->isKMasked()) {
3043 // Intrinsic forms need to pass TB_NO_REVERSE.
3044 if (I.getGroup()->isIntrinsic()) {
3045 AddTableEntry(RegOp2MemOpTable3, MemOp2RegOpTable,
3046 I.getRegOpcode(), I.getMemOpcode(),
3047 TB_ALIGN_NONE | TB_INDEX_3 | TB_FOLDED_LOAD | TB_NO_REVERSE);
3048 } else {
3049 AddTableEntry(RegOp2MemOpTable3, MemOp2RegOpTable,
3050 I.getRegOpcode(), I.getMemOpcode(),
3051 TB_ALIGN_NONE | TB_INDEX_3 | TB_FOLDED_LOAD);
3052 }
3053 }
3054 }
3055
3056 static const X86MemoryFoldTableEntry MemoryFoldTable4[] = {
3057 // AVX-512 foldable masked instructions
3058 { X86::VADDPDZrrk, X86::VADDPDZrmk, 0 },
3059 { X86::VADDPSZrrk, X86::VADDPSZrmk, 0 },
3060 { X86::VADDSDZrr_Intk, X86::VADDSDZrm_Intk, TB_NO_REVERSE },
3061 { X86::VADDSSZrr_Intk, X86::VADDSSZrm_Intk, TB_NO_REVERSE },
3062 { X86::VALIGNDZrrik, X86::VALIGNDZrmik, 0 },
3063 { X86::VALIGNQZrrik, X86::VALIGNQZrmik, 0 },
3064 { X86::VANDNPDZrrk, X86::VANDNPDZrmk, 0 },
3065 { X86::VANDNPSZrrk, X86::VANDNPSZrmk, 0 },
3066 { X86::VANDPDZrrk, X86::VANDPDZrmk, 0 },
3067 { X86::VANDPSZrrk, X86::VANDPSZrmk, 0 },
3068 { X86::VDIVPDZrrk, X86::VDIVPDZrmk, 0 },
3069 { X86::VDIVPSZrrk, X86::VDIVPSZrmk, 0 },
3070 { X86::VDIVSDZrr_Intk, X86::VDIVSDZrm_Intk, TB_NO_REVERSE },
3071 { X86::VDIVSSZrr_Intk, X86::VDIVSSZrm_Intk, TB_NO_REVERSE },
3072 { X86::VINSERTF32x4Zrrk, X86::VINSERTF32x4Zrmk, 0 },
3073 { X86::VINSERTF32x8Zrrk, X86::VINSERTF32x8Zrmk, 0 },
3074 { X86::VINSERTF64x2Zrrk, X86::VINSERTF64x2Zrmk, 0 },
3075 { X86::VINSERTF64x4Zrrk, X86::VINSERTF64x4Zrmk, 0 },
3076 { X86::VINSERTI32x4Zrrk, X86::VINSERTI32x4Zrmk, 0 },
3077 { X86::VINSERTI32x8Zrrk, X86::VINSERTI32x8Zrmk, 0 },
3078 { X86::VINSERTI64x2Zrrk, X86::VINSERTI64x2Zrmk, 0 },
3079 { X86::VINSERTI64x4Zrrk, X86::VINSERTI64x4Zrmk, 0 },
3080 { X86::VMAXCPDZrrk, X86::VMAXCPDZrmk, 0 },
3081 { X86::VMAXCPSZrrk, X86::VMAXCPSZrmk, 0 },
3082 { X86::VMAXPDZrrk, X86::VMAXPDZrmk, 0 },
3083 { X86::VMAXPSZrrk, X86::VMAXPSZrmk, 0 },
3084 { X86::VMAXSDZrr_Intk, X86::VMAXSDZrm_Intk, 0 },
3085 { X86::VMAXSSZrr_Intk, X86::VMAXSSZrm_Intk, 0 },
3086 { X86::VMINCPDZrrk, X86::VMINCPDZrmk, 0 },
3087 { X86::VMINCPSZrrk, X86::VMINCPSZrmk, 0 },
3088 { X86::VMINPDZrrk, X86::VMINPDZrmk, 0 },
3089 { X86::VMINPSZrrk, X86::VMINPSZrmk, 0 },
3090 { X86::VMINSDZrr_Intk, X86::VMINSDZrm_Intk, 0 },
3091 { X86::VMINSSZrr_Intk, X86::VMINSSZrm_Intk, 0 },
3092 { X86::VMULPDZrrk, X86::VMULPDZrmk, 0 },
3093 { X86::VMULPSZrrk, X86::VMULPSZrmk, 0 },
3094 { X86::VMULSDZrr_Intk, X86::VMULSDZrm_Intk, TB_NO_REVERSE },
3095 { X86::VMULSSZrr_Intk, X86::VMULSSZrm_Intk, TB_NO_REVERSE },
3096 { X86::VORPDZrrk, X86::VORPDZrmk, 0 },
3097 { X86::VORPSZrrk, X86::VORPSZrmk, 0 },
3098 { X86::VPACKSSDWZrrk, X86::VPACKSSDWZrmk, 0 },
3099 { X86::VPACKSSWBZrrk, X86::VPACKSSWBZrmk, 0 },
3100 { X86::VPACKUSDWZrrk, X86::VPACKUSDWZrmk, 0 },
3101 { X86::VPACKUSWBZrrk, X86::VPACKUSWBZrmk, 0 },
3102 { X86::VPADDBZrrk, X86::VPADDBZrmk, 0 },
3103 { X86::VPADDDZrrk, X86::VPADDDZrmk, 0 },
3104 { X86::VPADDQZrrk, X86::VPADDQZrmk, 0 },
3105 { X86::VPADDSBZrrk, X86::VPADDSBZrmk, 0 },
3106 { X86::VPADDSWZrrk, X86::VPADDSWZrmk, 0 },
3107 { X86::VPADDUSBZrrk, X86::VPADDUSBZrmk, 0 },
3108 { X86::VPADDUSWZrrk, X86::VPADDUSWZrmk, 0 },
3109 { X86::VPADDWZrrk, X86::VPADDWZrmk, 0 },
3110 { X86::VPALIGNRZrrik, X86::VPALIGNRZrmik, 0 },
3111 { X86::VPANDDZrrk, X86::VPANDDZrmk, 0 },
3112 { X86::VPANDNDZrrk, X86::VPANDNDZrmk, 0 },
3113 { X86::VPANDNQZrrk, X86::VPANDNQZrmk, 0 },
3114 { X86::VPANDQZrrk, X86::VPANDQZrmk, 0 },
3115 { X86::VPAVGBZrrk, X86::VPAVGBZrmk, 0 },
3116 { X86::VPAVGWZrrk, X86::VPAVGWZrmk, 0 },
3117 { X86::VPERMBZrrk, X86::VPERMBZrmk, 0 },
3118 { X86::VPERMDZrrk, X86::VPERMDZrmk, 0 },
3119 { X86::VPERMI2Brrk, X86::VPERMI2Brmk, 0 },
3120 { X86::VPERMI2Drrk, X86::VPERMI2Drmk, 0 },
3121 { X86::VPERMI2PSrrk, X86::VPERMI2PSrmk, 0 },
3122 { X86::VPERMI2PDrrk, X86::VPERMI2PDrmk, 0 },
3123 { X86::VPERMI2Qrrk, X86::VPERMI2Qrmk, 0 },
3124 { X86::VPERMI2Wrrk, X86::VPERMI2Wrmk, 0 },
3125 { X86::VPERMILPDZrrk, X86::VPERMILPDZrmk, 0 },
3126 { X86::VPERMILPSZrrk, X86::VPERMILPSZrmk, 0 },
3127 { X86::VPERMPDZrrk, X86::VPERMPDZrmk, 0 },
3128 { X86::VPERMPSZrrk, X86::VPERMPSZrmk, 0 },
3129 { X86::VPERMQZrrk, X86::VPERMQZrmk, 0 },
3130 { X86::VPERMT2Brrk, X86::VPERMT2Brmk, 0 },
3131 { X86::VPERMT2Drrk, X86::VPERMT2Drmk, 0 },
3132 { X86::VPERMT2PSrrk, X86::VPERMT2PSrmk, 0 },
3133 { X86::VPERMT2PDrrk, X86::VPERMT2PDrmk, 0 },
3134 { X86::VPERMT2Qrrk, X86::VPERMT2Qrmk, 0 },
3135 { X86::VPERMT2Wrrk, X86::VPERMT2Wrmk, 0 },
3136 { X86::VPERMWZrrk, X86::VPERMWZrmk, 0 },
3137 { X86::VPMADDUBSWZrrk, X86::VPMADDUBSWZrmk, 0 },
3138 { X86::VPMADDWDZrrk, X86::VPMADDWDZrmk, 0 },
3139 { X86::VPMAXSBZrrk, X86::VPMAXSBZrmk, 0 },
3140 { X86::VPMAXSDZrrk, X86::VPMAXSDZrmk, 0 },
3141 { X86::VPMAXSQZrrk, X86::VPMAXSQZrmk, 0 },
3142 { X86::VPMAXSWZrrk, X86::VPMAXSWZrmk, 0 },
3143 { X86::VPMAXUBZrrk, X86::VPMAXUBZrmk, 0 },
3144 { X86::VPMAXUDZrrk, X86::VPMAXUDZrmk, 0 },
3145 { X86::VPMAXUQZrrk, X86::VPMAXUQZrmk, 0 },
3146 { X86::VPMAXUWZrrk, X86::VPMAXUWZrmk, 0 },
3147 { X86::VPMINSBZrrk, X86::VPMINSBZrmk, 0 },
3148 { X86::VPMINSDZrrk, X86::VPMINSDZrmk, 0 },
3149 { X86::VPMINSQZrrk, X86::VPMINSQZrmk, 0 },
3150 { X86::VPMINSWZrrk, X86::VPMINSWZrmk, 0 },
3151 { X86::VPMINUBZrrk, X86::VPMINUBZrmk, 0 },
3152 { X86::VPMINUDZrrk, X86::VPMINUDZrmk, 0 },
3153 { X86::VPMINUQZrrk, X86::VPMINUQZrmk, 0 },
3154 { X86::VPMINUWZrrk, X86::VPMINUWZrmk, 0 },
3155 { X86::VPMULDQZrrk, X86::VPMULDQZrmk, 0 },
3156 { X86::VPMULLDZrrk, X86::VPMULLDZrmk, 0 },
3157 { X86::VPMULLQZrrk, X86::VPMULLQZrmk, 0 },
3158 { X86::VPMULLWZrrk, X86::VPMULLWZrmk, 0 },
3159 { X86::VPMULUDQZrrk, X86::VPMULUDQZrmk, 0 },
3160 { X86::VPORDZrrk, X86::VPORDZrmk, 0 },
3161 { X86::VPORQZrrk, X86::VPORQZrmk, 0 },
3162 { X86::VPSHUFBZrrk, X86::VPSHUFBZrmk, 0 },
3163 { X86::VPSLLDZrrk, X86::VPSLLDZrmk, 0 },
3164 { X86::VPSLLQZrrk, X86::VPSLLQZrmk, 0 },
3165 { X86::VPSLLVDZrrk, X86::VPSLLVDZrmk, 0 },
3166 { X86::VPSLLVQZrrk, X86::VPSLLVQZrmk, 0 },
3167 { X86::VPSLLVWZrrk, X86::VPSLLVWZrmk, 0 },
3168 { X86::VPSLLWZrrk, X86::VPSLLWZrmk, 0 },
3169 { X86::VPSRADZrrk, X86::VPSRADZrmk, 0 },
3170 { X86::VPSRAQZrrk, X86::VPSRAQZrmk, 0 },
3171 { X86::VPSRAVDZrrk, X86::VPSRAVDZrmk, 0 },
3172 { X86::VPSRAVQZrrk, X86::VPSRAVQZrmk, 0 },
3173 { X86::VPSRAVWZrrk, X86::VPSRAVWZrmk, 0 },
3174 { X86::VPSRAWZrrk, X86::VPSRAWZrmk, 0 },
3175 { X86::VPSRLDZrrk, X86::VPSRLDZrmk, 0 },
3176 { X86::VPSRLQZrrk, X86::VPSRLQZrmk, 0 },
3177 { X86::VPSRLVDZrrk, X86::VPSRLVDZrmk, 0 },
3178 { X86::VPSRLVQZrrk, X86::VPSRLVQZrmk, 0 },
3179 { X86::VPSRLVWZrrk, X86::VPSRLVWZrmk, 0 },
3180 { X86::VPSRLWZrrk, X86::VPSRLWZrmk, 0 },
3181 { X86::VPSUBBZrrk, X86::VPSUBBZrmk, 0 },
3182 { X86::VPSUBDZrrk, X86::VPSUBDZrmk, 0 },
3183 { X86::VPSUBQZrrk, X86::VPSUBQZrmk, 0 },
3184 { X86::VPSUBSBZrrk, X86::VPSUBSBZrmk, 0 },
3185 { X86::VPSUBSWZrrk, X86::VPSUBSWZrmk, 0 },
3186 { X86::VPSUBUSBZrrk, X86::VPSUBUSBZrmk, 0 },
3187 { X86::VPSUBUSWZrrk, X86::VPSUBUSWZrmk, 0 },
3188 { X86::VPTERNLOGDZrrik, X86::VPTERNLOGDZrmik, 0 },
3189 { X86::VPTERNLOGQZrrik, X86::VPTERNLOGQZrmik, 0 },
3190 { X86::VPUNPCKHBWZrrk, X86::VPUNPCKHBWZrmk, 0 },
3191 { X86::VPUNPCKHDQZrrk, X86::VPUNPCKHDQZrmk, 0 },
3192 { X86::VPUNPCKHQDQZrrk, X86::VPUNPCKHQDQZrmk, 0 },
3193 { X86::VPUNPCKHWDZrrk, X86::VPUNPCKHWDZrmk, 0 },
3194 { X86::VPUNPCKLBWZrrk, X86::VPUNPCKLBWZrmk, 0 },
3195 { X86::VPUNPCKLDQZrrk, X86::VPUNPCKLDQZrmk, 0 },
3196 { X86::VPUNPCKLQDQZrrk, X86::VPUNPCKLQDQZrmk, 0 },
3197 { X86::VPUNPCKLWDZrrk, X86::VPUNPCKLWDZrmk, 0 },
3198 { X86::VPXORDZrrk, X86::VPXORDZrmk, 0 },
3199 { X86::VPXORQZrrk, X86::VPXORQZrmk, 0 },
3200 { X86::VSHUFPDZrrik, X86::VSHUFPDZrmik, 0 },
3201 { X86::VSHUFPSZrrik, X86::VSHUFPSZrmik, 0 },
3202 { X86::VSUBPDZrrk, X86::VSUBPDZrmk, 0 },
3203 { X86::VSUBPSZrrk, X86::VSUBPSZrmk, 0 },
3204 { X86::VSUBSDZrr_Intk, X86::VSUBSDZrm_Intk, TB_NO_REVERSE },
3205 { X86::VSUBSSZrr_Intk, X86::VSUBSSZrm_Intk, TB_NO_REVERSE },
3206 { X86::VUNPCKHPDZrrk, X86::VUNPCKHPDZrmk, 0 },
3207 { X86::VUNPCKHPSZrrk, X86::VUNPCKHPSZrmk, 0 },
3208 { X86::VUNPCKLPDZrrk, X86::VUNPCKLPDZrmk, 0 },
3209 { X86::VUNPCKLPSZrrk, X86::VUNPCKLPSZrmk, 0 },
3210 { X86::VXORPDZrrk, X86::VXORPDZrmk, 0 },
3211 { X86::VXORPSZrrk, X86::VXORPSZrmk, 0 },
3212
3213 // AVX-512{F,VL} foldable masked instructions 256-bit
3214 { X86::VADDPDZ256rrk, X86::VADDPDZ256rmk, 0 },
3215 { X86::VADDPSZ256rrk, X86::VADDPSZ256rmk, 0 },
3216 { X86::VALIGNDZ256rrik, X86::VALIGNDZ256rmik, 0 },
3217 { X86::VALIGNQZ256rrik, X86::VALIGNQZ256rmik, 0 },
3218 { X86::VANDNPDZ256rrk, X86::VANDNPDZ256rmk, 0 },
3219 { X86::VANDNPSZ256rrk, X86::VANDNPSZ256rmk, 0 },
3220 { X86::VANDPDZ256rrk, X86::VANDPDZ256rmk, 0 },
3221 { X86::VANDPSZ256rrk, X86::VANDPSZ256rmk, 0 },
3222 { X86::VDIVPDZ256rrk, X86::VDIVPDZ256rmk, 0 },
3223 { X86::VDIVPSZ256rrk, X86::VDIVPSZ256rmk, 0 },
3224 { X86::VINSERTF32x4Z256rrk,X86::VINSERTF32x4Z256rmk, 0 },
3225 { X86::VINSERTF64x2Z256rrk,X86::VINSERTF64x2Z256rmk, 0 },
3226 { X86::VINSERTI32x4Z256rrk,X86::VINSERTI32x4Z256rmk, 0 },
3227 { X86::VINSERTI64x2Z256rrk,X86::VINSERTI64x2Z256rmk, 0 },
3228 { X86::VMAXCPDZ256rrk, X86::VMAXCPDZ256rmk, 0 },
3229 { X86::VMAXCPSZ256rrk, X86::VMAXCPSZ256rmk, 0 },
3230 { X86::VMAXPDZ256rrk, X86::VMAXPDZ256rmk, 0 },
3231 { X86::VMAXPSZ256rrk, X86::VMAXPSZ256rmk, 0 },
3232 { X86::VMINCPDZ256rrk, X86::VMINCPDZ256rmk, 0 },
3233 { X86::VMINCPSZ256rrk, X86::VMINCPSZ256rmk, 0 },
3234 { X86::VMINPDZ256rrk, X86::VMINPDZ256rmk, 0 },
3235 { X86::VMINPSZ256rrk, X86::VMINPSZ256rmk, 0 },
3236 { X86::VMULPDZ256rrk, X86::VMULPDZ256rmk, 0 },
3237 { X86::VMULPSZ256rrk, X86::VMULPSZ256rmk, 0 },
3238 { X86::VORPDZ256rrk, X86::VORPDZ256rmk, 0 },
3239 { X86::VORPSZ256rrk, X86::VORPSZ256rmk, 0 },
3240 { X86::VPACKSSDWZ256rrk, X86::VPACKSSDWZ256rmk, 0 },
3241 { X86::VPACKSSWBZ256rrk, X86::VPACKSSWBZ256rmk, 0 },
3242 { X86::VPACKUSDWZ256rrk, X86::VPACKUSDWZ256rmk, 0 },
3243 { X86::VPACKUSWBZ256rrk, X86::VPACKUSWBZ256rmk, 0 },
3244 { X86::VPADDBZ256rrk, X86::VPADDBZ256rmk, 0 },
3245 { X86::VPADDDZ256rrk, X86::VPADDDZ256rmk, 0 },
3246 { X86::VPADDQZ256rrk, X86::VPADDQZ256rmk, 0 },
3247 { X86::VPADDSBZ256rrk, X86::VPADDSBZ256rmk, 0 },
3248 { X86::VPADDSWZ256rrk, X86::VPADDSWZ256rmk, 0 },
3249 { X86::VPADDUSBZ256rrk, X86::VPADDUSBZ256rmk, 0 },
3250 { X86::VPADDUSWZ256rrk, X86::VPADDUSWZ256rmk, 0 },
3251 { X86::VPADDWZ256rrk, X86::VPADDWZ256rmk, 0 },
3252 { X86::VPALIGNRZ256rrik, X86::VPALIGNRZ256rmik, 0 },
3253 { X86::VPANDDZ256rrk, X86::VPANDDZ256rmk, 0 },
3254 { X86::VPANDNDZ256rrk, X86::VPANDNDZ256rmk, 0 },
3255 { X86::VPANDNQZ256rrk, X86::VPANDNQZ256rmk, 0 },
3256 { X86::VPANDQZ256rrk, X86::VPANDQZ256rmk, 0 },
3257 { X86::VPAVGBZ256rrk, X86::VPAVGBZ256rmk, 0 },
3258 { X86::VPAVGWZ256rrk, X86::VPAVGWZ256rmk, 0 },
3259 { X86::VPERMBZ256rrk, X86::VPERMBZ256rmk, 0 },
3260 { X86::VPERMDZ256rrk, X86::VPERMDZ256rmk, 0 },
3261 { X86::VPERMI2B256rrk, X86::VPERMI2B256rmk, 0 },
3262 { X86::VPERMI2D256rrk, X86::VPERMI2D256rmk, 0 },
3263 { X86::VPERMI2PD256rrk, X86::VPERMI2PD256rmk, 0 },
3264 { X86::VPERMI2PS256rrk, X86::VPERMI2PS256rmk, 0 },
3265 { X86::VPERMI2Q256rrk, X86::VPERMI2Q256rmk, 0 },
3266 { X86::VPERMI2W256rrk, X86::VPERMI2W256rmk, 0 },
3267 { X86::VPERMILPDZ256rrk, X86::VPERMILPDZ256rmk, 0 },
3268 { X86::VPERMILPSZ256rrk, X86::VPERMILPSZ256rmk, 0 },
3269 { X86::VPERMPDZ256rrk, X86::VPERMPDZ256rmk, 0 },
3270 { X86::VPERMPSZ256rrk, X86::VPERMPSZ256rmk, 0 },
3271 { X86::VPERMQZ256rrk, X86::VPERMQZ256rmk, 0 },
3272 { X86::VPERMT2B256rrk, X86::VPERMT2B256rmk, 0 },
3273 { X86::VPERMT2D256rrk, X86::VPERMT2D256rmk, 0 },
3274 { X86::VPERMT2PD256rrk, X86::VPERMT2PD256rmk, 0 },
3275 { X86::VPERMT2PS256rrk, X86::VPERMT2PS256rmk, 0 },
3276 { X86::VPERMT2Q256rrk, X86::VPERMT2Q256rmk, 0 },
3277 { X86::VPERMT2W256rrk, X86::VPERMT2W256rmk, 0 },
3278 { X86::VPERMWZ256rrk, X86::VPERMWZ256rmk, 0 },
3279 { X86::VPMADDUBSWZ256rrk, X86::VPMADDUBSWZ256rmk, 0 },
3280 { X86::VPMADDWDZ256rrk, X86::VPMADDWDZ256rmk, 0 },
3281 { X86::VPMAXSBZ256rrk, X86::VPMAXSBZ256rmk, 0 },
3282 { X86::VPMAXSDZ256rrk, X86::VPMAXSDZ256rmk, 0 },
3283 { X86::VPMAXSQZ256rrk, X86::VPMAXSQZ256rmk, 0 },
3284 { X86::VPMAXSWZ256rrk, X86::VPMAXSWZ256rmk, 0 },
3285 { X86::VPMAXUBZ256rrk, X86::VPMAXUBZ256rmk, 0 },
3286 { X86::VPMAXUDZ256rrk, X86::VPMAXUDZ256rmk, 0 },
3287 { X86::VPMAXUQZ256rrk, X86::VPMAXUQZ256rmk, 0 },
3288 { X86::VPMAXUWZ256rrk, X86::VPMAXUWZ256rmk, 0 },
3289 { X86::VPMINSBZ256rrk, X86::VPMINSBZ256rmk, 0 },
3290 { X86::VPMINSDZ256rrk, X86::VPMINSDZ256rmk, 0 },
3291 { X86::VPMINSQZ256rrk, X86::VPMINSQZ256rmk, 0 },
3292 { X86::VPMINSWZ256rrk, X86::VPMINSWZ256rmk, 0 },
3293 { X86::VPMINUBZ256rrk, X86::VPMINUBZ256rmk, 0 },
3294 { X86::VPMINUDZ256rrk, X86::VPMINUDZ256rmk, 0 },
3295 { X86::VPMINUQZ256rrk, X86::VPMINUQZ256rmk, 0 },
3296 { X86::VPMINUWZ256rrk, X86::VPMINUWZ256rmk, 0 },
3297 { X86::VPMULDQZ256rrk, X86::VPMULDQZ256rmk, 0 },
3298 { X86::VPMULLDZ256rrk, X86::VPMULLDZ256rmk, 0 },
3299 { X86::VPMULLQZ256rrk, X86::VPMULLQZ256rmk, 0 },
3300 { X86::VPMULLWZ256rrk, X86::VPMULLWZ256rmk, 0 },
3301 { X86::VPMULUDQZ256rrk, X86::VPMULUDQZ256rmk, 0 },
3302 { X86::VPORDZ256rrk, X86::VPORDZ256rmk, 0 },
3303 { X86::VPORQZ256rrk, X86::VPORQZ256rmk, 0 },
3304 { X86::VPSHUFBZ256rrk, X86::VPSHUFBZ256rmk, 0 },
3305 { X86::VPSLLDZ256rrk, X86::VPSLLDZ256rmk, 0 },
3306 { X86::VPSLLQZ256rrk, X86::VPSLLQZ256rmk, 0 },
3307 { X86::VPSLLVDZ256rrk, X86::VPSLLVDZ256rmk, 0 },
3308 { X86::VPSLLVQZ256rrk, X86::VPSLLVQZ256rmk, 0 },
3309 { X86::VPSLLVWZ256rrk, X86::VPSLLVWZ256rmk, 0 },
3310 { X86::VPSLLWZ256rrk, X86::VPSLLWZ256rmk, 0 },
3311 { X86::VPSRADZ256rrk, X86::VPSRADZ256rmk, 0 },
3312 { X86::VPSRAQZ256rrk, X86::VPSRAQZ256rmk, 0 },
3313 { X86::VPSRAVDZ256rrk, X86::VPSRAVDZ256rmk, 0 },
3314 { X86::VPSRAVQZ256rrk, X86::VPSRAVQZ256rmk, 0 },
3315 { X86::VPSRAVWZ256rrk, X86::VPSRAVWZ256rmk, 0 },
3316 { X86::VPSRAWZ256rrk, X86::VPSRAWZ256rmk, 0 },
3317 { X86::VPSRLDZ256rrk, X86::VPSRLDZ256rmk, 0 },
3318 { X86::VPSRLQZ256rrk, X86::VPSRLQZ256rmk, 0 },
3319 { X86::VPSRLVDZ256rrk, X86::VPSRLVDZ256rmk, 0 },
3320 { X86::VPSRLVQZ256rrk, X86::VPSRLVQZ256rmk, 0 },
3321 { X86::VPSRLVWZ256rrk, X86::VPSRLVWZ256rmk, 0 },
3322 { X86::VPSRLWZ256rrk, X86::VPSRLWZ256rmk, 0 },
3323 { X86::VPSUBBZ256rrk, X86::VPSUBBZ256rmk, 0 },
3324 { X86::VPSUBDZ256rrk, X86::VPSUBDZ256rmk, 0 },
3325 { X86::VPSUBQZ256rrk, X86::VPSUBQZ256rmk, 0 },
3326 { X86::VPSUBSBZ256rrk, X86::VPSUBSBZ256rmk, 0 },
3327 { X86::VPSUBSWZ256rrk, X86::VPSUBSWZ256rmk, 0 },
3328 { X86::VPSUBUSBZ256rrk, X86::VPSUBUSBZ256rmk, 0 },
3329 { X86::VPSUBUSWZ256rrk, X86::VPSUBUSWZ256rmk, 0 },
3330 { X86::VPSUBWZ256rrk, X86::VPSUBWZ256rmk, 0 },
3331 { X86::VPTERNLOGDZ256rrik, X86::VPTERNLOGDZ256rmik, 0 },
3332 { X86::VPTERNLOGQZ256rrik, X86::VPTERNLOGQZ256rmik, 0 },
3333 { X86::VPUNPCKHBWZ256rrk, X86::VPUNPCKHBWZ256rmk, 0 },
3334 { X86::VPUNPCKHDQZ256rrk, X86::VPUNPCKHDQZ256rmk, 0 },
3335 { X86::VPUNPCKHQDQZ256rrk, X86::VPUNPCKHQDQZ256rmk, 0 },
3336 { X86::VPUNPCKHWDZ256rrk, X86::VPUNPCKHWDZ256rmk, 0 },
3337 { X86::VPUNPCKLBWZ256rrk, X86::VPUNPCKLBWZ256rmk, 0 },
3338 { X86::VPUNPCKLDQZ256rrk, X86::VPUNPCKLDQZ256rmk, 0 },
3339 { X86::VPUNPCKLQDQZ256rrk, X86::VPUNPCKLQDQZ256rmk, 0 },
3340 { X86::VPUNPCKLWDZ256rrk, X86::VPUNPCKLWDZ256rmk, 0 },
3341 { X86::VPXORDZ256rrk, X86::VPXORDZ256rmk, 0 },
3342 { X86::VPXORQZ256rrk, X86::VPXORQZ256rmk, 0 },
3343 { X86::VSHUFPDZ256rrik, X86::VSHUFPDZ256rmik, 0 },
3344 { X86::VSHUFPSZ256rrik, X86::VSHUFPSZ256rmik, 0 },
3345 { X86::VSUBPDZ256rrk, X86::VSUBPDZ256rmk, 0 },
3346 { X86::VSUBPSZ256rrk, X86::VSUBPSZ256rmk, 0 },
3347 { X86::VUNPCKHPDZ256rrk, X86::VUNPCKHPDZ256rmk, 0 },
3348 { X86::VUNPCKHPSZ256rrk, X86::VUNPCKHPSZ256rmk, 0 },
3349 { X86::VUNPCKLPDZ256rrk, X86::VUNPCKLPDZ256rmk, 0 },
3350 { X86::VUNPCKLPSZ256rrk, X86::VUNPCKLPSZ256rmk, 0 },
3351 { X86::VXORPDZ256rrk, X86::VXORPDZ256rmk, 0 },
3352 { X86::VXORPSZ256rrk, X86::VXORPSZ256rmk, 0 },
3353
3354 // AVX-512{F,VL} foldable instructions 128-bit
3355 { X86::VADDPDZ128rrk, X86::VADDPDZ128rmk, 0 },
3356 { X86::VADDPSZ128rrk, X86::VADDPSZ128rmk, 0 },
3357 { X86::VALIGNDZ128rrik, X86::VALIGNDZ128rmik, 0 },
3358 { X86::VALIGNQZ128rrik, X86::VALIGNQZ128rmik, 0 },
3359 { X86::VANDNPDZ128rrk, X86::VANDNPDZ128rmk, 0 },
3360 { X86::VANDNPSZ128rrk, X86::VANDNPSZ128rmk, 0 },
3361 { X86::VANDPDZ128rrk, X86::VANDPDZ128rmk, 0 },
3362 { X86::VANDPSZ128rrk, X86::VANDPSZ128rmk, 0 },
3363 { X86::VDIVPDZ128rrk, X86::VDIVPDZ128rmk, 0 },
3364 { X86::VDIVPSZ128rrk, X86::VDIVPSZ128rmk, 0 },
3365 { X86::VMAXCPDZ128rrk, X86::VMAXCPDZ128rmk, 0 },
3366 { X86::VMAXCPSZ128rrk, X86::VMAXCPSZ128rmk, 0 },
3367 { X86::VMAXPDZ128rrk, X86::VMAXPDZ128rmk, 0 },
3368 { X86::VMAXPSZ128rrk, X86::VMAXPSZ128rmk, 0 },
3369 { X86::VMINCPDZ128rrk, X86::VMINCPDZ128rmk, 0 },
3370 { X86::VMINCPSZ128rrk, X86::VMINCPSZ128rmk, 0 },
3371 { X86::VMINPDZ128rrk, X86::VMINPDZ128rmk, 0 },
3372 { X86::VMINPSZ128rrk, X86::VMINPSZ128rmk, 0 },
3373 { X86::VMULPDZ128rrk, X86::VMULPDZ128rmk, 0 },
3374 { X86::VMULPSZ128rrk, X86::VMULPSZ128rmk, 0 },
3375 { X86::VORPDZ128rrk, X86::VORPDZ128rmk, 0 },
3376 { X86::VORPSZ128rrk, X86::VORPSZ128rmk, 0 },
3377 { X86::VPACKSSDWZ128rrk, X86::VPACKSSDWZ128rmk, 0 },
3378 { X86::VPACKSSWBZ128rrk, X86::VPACKSSWBZ128rmk, 0 },
3379 { X86::VPACKUSDWZ128rrk, X86::VPACKUSDWZ128rmk, 0 },
3380 { X86::VPACKUSWBZ128rrk, X86::VPACKUSWBZ128rmk, 0 },
3381 { X86::VPADDBZ128rrk, X86::VPADDBZ128rmk, 0 },
3382 { X86::VPADDDZ128rrk, X86::VPADDDZ128rmk, 0 },
3383 { X86::VPADDQZ128rrk, X86::VPADDQZ128rmk, 0 },
3384 { X86::VPADDSBZ128rrk, X86::VPADDSBZ128rmk, 0 },
3385 { X86::VPADDSWZ128rrk, X86::VPADDSWZ128rmk, 0 },
3386 { X86::VPADDUSBZ128rrk, X86::VPADDUSBZ128rmk, 0 },
3387 { X86::VPADDUSWZ128rrk, X86::VPADDUSWZ128rmk, 0 },
3388 { X86::VPADDWZ128rrk, X86::VPADDWZ128rmk, 0 },
3389 { X86::VPALIGNRZ128rrik, X86::VPALIGNRZ128rmik, 0 },
3390 { X86::VPANDDZ128rrk, X86::VPANDDZ128rmk, 0 },
3391 { X86::VPANDNDZ128rrk, X86::VPANDNDZ128rmk, 0 },
3392 { X86::VPANDNQZ128rrk, X86::VPANDNQZ128rmk, 0 },
3393 { X86::VPANDQZ128rrk, X86::VPANDQZ128rmk, 0 },
3394 { X86::VPAVGBZ128rrk, X86::VPAVGBZ128rmk, 0 },
3395 { X86::VPAVGWZ128rrk, X86::VPAVGWZ128rmk, 0 },
3396 { X86::VPERMBZ128rrk, X86::VPERMBZ128rmk, 0 },
3397 { X86::VPERMI2B128rrk, X86::VPERMI2B128rmk, 0 },
3398 { X86::VPERMI2D128rrk, X86::VPERMI2D128rmk, 0 },
3399 { X86::VPERMI2PD128rrk, X86::VPERMI2PD128rmk, 0 },
3400 { X86::VPERMI2PS128rrk, X86::VPERMI2PS128rmk, 0 },
3401 { X86::VPERMI2Q128rrk, X86::VPERMI2Q128rmk, 0 },
3402 { X86::VPERMI2W128rrk, X86::VPERMI2W128rmk, 0 },
3403 { X86::VPERMILPDZ128rrk, X86::VPERMILPDZ128rmk, 0 },
3404 { X86::VPERMILPSZ128rrk, X86::VPERMILPSZ128rmk, 0 },
3405 { X86::VPERMT2B128rrk, X86::VPERMT2B128rmk, 0 },
3406 { X86::VPERMT2D128rrk, X86::VPERMT2D128rmk, 0 },
3407 { X86::VPERMT2PD128rrk, X86::VPERMT2PD128rmk, 0 },
3408 { X86::VPERMT2PS128rrk, X86::VPERMT2PS128rmk, 0 },
3409 { X86::VPERMT2Q128rrk, X86::VPERMT2Q128rmk, 0 },
3410 { X86::VPERMT2W128rrk, X86::VPERMT2W128rmk, 0 },
3411 { X86::VPERMWZ128rrk, X86::VPERMWZ128rmk, 0 },
3412 { X86::VPMADDUBSWZ128rrk, X86::VPMADDUBSWZ128rmk, 0 },
3413 { X86::VPMADDWDZ128rrk, X86::VPMADDWDZ128rmk, 0 },
3414 { X86::VPMAXSBZ128rrk, X86::VPMAXSBZ128rmk, 0 },
3415 { X86::VPMAXSDZ128rrk, X86::VPMAXSDZ128rmk, 0 },
3416 { X86::VPMAXSQZ128rrk, X86::VPMAXSQZ128rmk, 0 },
3417 { X86::VPMAXSWZ128rrk, X86::VPMAXSWZ128rmk, 0 },
3418 { X86::VPMAXUBZ128rrk, X86::VPMAXUBZ128rmk, 0 },
3419 { X86::VPMAXUDZ128rrk, X86::VPMAXUDZ128rmk, 0 },
3420 { X86::VPMAXUQZ128rrk, X86::VPMAXUQZ128rmk, 0 },
3421 { X86::VPMAXUWZ128rrk, X86::VPMAXUWZ128rmk, 0 },
3422 { X86::VPMINSBZ128rrk, X86::VPMINSBZ128rmk, 0 },
3423 { X86::VPMINSDZ128rrk, X86::VPMINSDZ128rmk, 0 },
3424 { X86::VPMINSQZ128rrk, X86::VPMINSQZ128rmk, 0 },
3425 { X86::VPMINSWZ128rrk, X86::VPMINSWZ128rmk, 0 },
3426 { X86::VPMINUBZ128rrk, X86::VPMINUBZ128rmk, 0 },
3427 { X86::VPMINUDZ128rrk, X86::VPMINUDZ128rmk, 0 },
3428 { X86::VPMINUQZ128rrk, X86::VPMINUQZ128rmk, 0 },
3429 { X86::VPMINUWZ128rrk, X86::VPMINUWZ128rmk, 0 },
3430 { X86::VPMULDQZ128rrk, X86::VPMULDQZ128rmk, 0 },
3431 { X86::VPMULLDZ128rrk, X86::VPMULLDZ128rmk, 0 },
3432 { X86::VPMULLQZ128rrk, X86::VPMULLQZ128rmk, 0 },
3433 { X86::VPMULLWZ128rrk, X86::VPMULLWZ128rmk, 0 },
3434 { X86::VPMULUDQZ128rrk, X86::VPMULUDQZ128rmk, 0 },
3435 { X86::VPORDZ128rrk, X86::VPORDZ128rmk, 0 },
3436 { X86::VPORQZ128rrk, X86::VPORQZ128rmk, 0 },
3437 { X86::VPSHUFBZ128rrk, X86::VPSHUFBZ128rmk, 0 },
3438 { X86::VPSLLDZ128rrk, X86::VPSLLDZ128rmk, 0 },
3439 { X86::VPSLLQZ128rrk, X86::VPSLLQZ128rmk, 0 },
3440 { X86::VPSLLVDZ128rrk, X86::VPSLLVDZ128rmk, 0 },
3441 { X86::VPSLLVQZ128rrk, X86::VPSLLVQZ128rmk, 0 },
3442 { X86::VPSLLVWZ128rrk, X86::VPSLLVWZ128rmk, 0 },
3443 { X86::VPSLLWZ128rrk, X86::VPSLLWZ128rmk, 0 },
3444 { X86::VPSRADZ128rrk, X86::VPSRADZ128rmk, 0 },
3445 { X86::VPSRAQZ128rrk, X86::VPSRAQZ128rmk, 0 },
3446 { X86::VPSRAVDZ128rrk, X86::VPSRAVDZ128rmk, 0 },
3447 { X86::VPSRAVQZ128rrk, X86::VPSRAVQZ128rmk, 0 },
3448 { X86::VPSRAVWZ128rrk, X86::VPSRAVWZ128rmk, 0 },
3449 { X86::VPSRAWZ128rrk, X86::VPSRAWZ128rmk, 0 },
3450 { X86::VPSRLDZ128rrk, X86::VPSRLDZ128rmk, 0 },
3451 { X86::VPSRLQZ128rrk, X86::VPSRLQZ128rmk, 0 },
3452 { X86::VPSRLVDZ128rrk, X86::VPSRLVDZ128rmk, 0 },
3453 { X86::VPSRLVQZ128rrk, X86::VPSRLVQZ128rmk, 0 },
3454 { X86::VPSRLVWZ128rrk, X86::VPSRLVWZ128rmk, 0 },
3455 { X86::VPSRLWZ128rrk, X86::VPSRLWZ128rmk, 0 },
3456 { X86::VPSUBBZ128rrk, X86::VPSUBBZ128rmk, 0 },
3457 { X86::VPSUBDZ128rrk, X86::VPSUBDZ128rmk, 0 },
3458 { X86::VPSUBQZ128rrk, X86::VPSUBQZ128rmk, 0 },
3459 { X86::VPSUBSBZ128rrk, X86::VPSUBSBZ128rmk, 0 },
3460 { X86::VPSUBSWZ128rrk, X86::VPSUBSWZ128rmk, 0 },
3461 { X86::VPSUBUSBZ128rrk, X86::VPSUBUSBZ128rmk, 0 },
3462 { X86::VPSUBUSWZ128rrk, X86::VPSUBUSWZ128rmk, 0 },
3463 { X86::VPSUBWZ128rrk, X86::VPSUBWZ128rmk, 0 },
3464 { X86::VPTERNLOGDZ128rrik, X86::VPTERNLOGDZ128rmik, 0 },
3465 { X86::VPTERNLOGQZ128rrik, X86::VPTERNLOGQZ128rmik, 0 },
3466 { X86::VPUNPCKHBWZ128rrk, X86::VPUNPCKHBWZ128rmk, 0 },
3467 { X86::VPUNPCKHDQZ128rrk, X86::VPUNPCKHDQZ128rmk, 0 },
3468 { X86::VPUNPCKHQDQZ128rrk, X86::VPUNPCKHQDQZ128rmk, 0 },
3469 { X86::VPUNPCKHWDZ128rrk, X86::VPUNPCKHWDZ128rmk, 0 },
3470 { X86::VPUNPCKLBWZ128rrk, X86::VPUNPCKLBWZ128rmk, 0 },
3471 { X86::VPUNPCKLDQZ128rrk, X86::VPUNPCKLDQZ128rmk, 0 },
3472 { X86::VPUNPCKLQDQZ128rrk, X86::VPUNPCKLQDQZ128rmk, 0 },
3473 { X86::VPUNPCKLWDZ128rrk, X86::VPUNPCKLWDZ128rmk, 0 },
3474 { X86::VPXORDZ128rrk, X86::VPXORDZ128rmk, 0 },
3475 { X86::VPXORQZ128rrk, X86::VPXORQZ128rmk, 0 },
3476 { X86::VSHUFPDZ128rrik, X86::VSHUFPDZ128rmik, 0 },
3477 { X86::VSHUFPSZ128rrik, X86::VSHUFPSZ128rmik, 0 },
3478 { X86::VSUBPDZ128rrk, X86::VSUBPDZ128rmk, 0 },
3479 { X86::VSUBPSZ128rrk, X86::VSUBPSZ128rmk, 0 },
3480 { X86::VUNPCKHPDZ128rrk, X86::VUNPCKHPDZ128rmk, 0 },
3481 { X86::VUNPCKHPSZ128rrk, X86::VUNPCKHPSZ128rmk, 0 },
3482 { X86::VUNPCKLPDZ128rrk, X86::VUNPCKLPDZ128rmk, 0 },
3483 { X86::VUNPCKLPSZ128rrk, X86::VUNPCKLPSZ128rmk, 0 },
3484 { X86::VXORPDZ128rrk, X86::VXORPDZ128rmk, 0 },
3485 { X86::VXORPSZ128rrk, X86::VXORPSZ128rmk, 0 },
3486
3487 // 512-bit three source instructions with zero masking.
3488 { X86::VPERMI2Brrkz, X86::VPERMI2Brmkz, 0 },
3489 { X86::VPERMI2Drrkz, X86::VPERMI2Drmkz, 0 },
3490 { X86::VPERMI2PSrrkz, X86::VPERMI2PSrmkz, 0 },
3491 { X86::VPERMI2PDrrkz, X86::VPERMI2PDrmkz, 0 },
3492 { X86::VPERMI2Qrrkz, X86::VPERMI2Qrmkz, 0 },
3493 { X86::VPERMI2Wrrkz, X86::VPERMI2Wrmkz, 0 },
3494 { X86::VPERMT2Brrkz, X86::VPERMT2Brmkz, 0 },
3495 { X86::VPERMT2Drrkz, X86::VPERMT2Drmkz, 0 },
3496 { X86::VPERMT2PSrrkz, X86::VPERMT2PSrmkz, 0 },
3497 { X86::VPERMT2PDrrkz, X86::VPERMT2PDrmkz, 0 },
3498 { X86::VPERMT2Qrrkz, X86::VPERMT2Qrmkz, 0 },
3499 { X86::VPERMT2Wrrkz, X86::VPERMT2Wrmkz, 0 },
3500 { X86::VPTERNLOGDZrrikz, X86::VPTERNLOGDZrmikz, 0 },
3501 { X86::VPTERNLOGQZrrikz, X86::VPTERNLOGQZrmikz, 0 },
3502
3503 // 256-bit three source instructions with zero masking.
3504 { X86::VPERMI2B256rrkz, X86::VPERMI2B256rmkz, 0 },
3505 { X86::VPERMI2D256rrkz, X86::VPERMI2D256rmkz, 0 },
3506 { X86::VPERMI2PD256rrkz, X86::VPERMI2PD256rmkz, 0 },
3507 { X86::VPERMI2PS256rrkz, X86::VPERMI2PS256rmkz, 0 },
3508 { X86::VPERMI2Q256rrkz, X86::VPERMI2Q256rmkz, 0 },
3509 { X86::VPERMI2W256rrkz, X86::VPERMI2W256rmkz, 0 },
3510 { X86::VPERMT2B256rrkz, X86::VPERMT2B256rmkz, 0 },
3511 { X86::VPERMT2D256rrkz, X86::VPERMT2D256rmkz, 0 },
3512 { X86::VPERMT2PD256rrkz, X86::VPERMT2PD256rmkz, 0 },
3513 { X86::VPERMT2PS256rrkz, X86::VPERMT2PS256rmkz, 0 },
3514 { X86::VPERMT2Q256rrkz, X86::VPERMT2Q256rmkz, 0 },
3515 { X86::VPERMT2W256rrkz, X86::VPERMT2W256rmkz, 0 },
3516 { X86::VPTERNLOGDZ256rrikz,X86::VPTERNLOGDZ256rmikz, 0 },
3517 { X86::VPTERNLOGQZ256rrikz,X86::VPTERNLOGQZ256rmikz, 0 },
3518
3519 // 128-bit three source instructions with zero masking.
3520 { X86::VPERMI2B128rrkz, X86::VPERMI2B128rmkz, 0 },
3521 { X86::VPERMI2D128rrkz, X86::VPERMI2D128rmkz, 0 },
3522 { X86::VPERMI2PD128rrkz, X86::VPERMI2PD128rmkz, 0 },
3523 { X86::VPERMI2PS128rrkz, X86::VPERMI2PS128rmkz, 0 },
3524 { X86::VPERMI2Q128rrkz, X86::VPERMI2Q128rmkz, 0 },
3525 { X86::VPERMI2W128rrkz, X86::VPERMI2W128rmkz, 0 },
3526 { X86::VPERMT2B128rrkz, X86::VPERMT2B128rmkz, 0 },
3527 { X86::VPERMT2D128rrkz, X86::VPERMT2D128rmkz, 0 },
3528 { X86::VPERMT2PD128rrkz, X86::VPERMT2PD128rmkz, 0 },
3529 { X86::VPERMT2PS128rrkz, X86::VPERMT2PS128rmkz, 0 },
3530 { X86::VPERMT2Q128rrkz, X86::VPERMT2Q128rmkz, 0 },
3531 { X86::VPERMT2W128rrkz, X86::VPERMT2W128rmkz, 0 },
3532 { X86::VPTERNLOGDZ128rrikz,X86::VPTERNLOGDZ128rmikz, 0 },
3533 { X86::VPTERNLOGQZ128rrikz,X86::VPTERNLOGQZ128rmikz, 0 },
3534 };
3535
3536 for (X86MemoryFoldTableEntry Entry : MemoryFoldTable4) {
3537 AddTableEntry(RegOp2MemOpTable4, MemOp2RegOpTable,
3538 Entry.RegOp, Entry.MemOp,
3539 // Index 4, folded load
3540 Entry.Flags | TB_INDEX_4 | TB_FOLDED_LOAD);
3541 }
3542 for (I = X86InstrFMA3Info::rm_begin(); I != E; ++I) {
3543 if (I.getGroup()->isKMasked()) {
3544 // Intrinsics need to pass TB_NO_REVERSE.
3545 if (I.getGroup()->isIntrinsic()) {
3546 AddTableEntry(RegOp2MemOpTable4, MemOp2RegOpTable,
3547 I.getRegOpcode(), I.getMemOpcode(),
3548 TB_ALIGN_NONE | TB_INDEX_4 | TB_FOLDED_LOAD | TB_NO_REVERSE);
3549 } else {
3550 AddTableEntry(RegOp2MemOpTable4, MemOp2RegOpTable,
3551 I.getRegOpcode(), I.getMemOpcode(),
3552 TB_ALIGN_NONE | TB_INDEX_4 | TB_FOLDED_LOAD);
3553 }
3554 }
3555 }
3556}
3557
3558void
3559X86InstrInfo::AddTableEntry(RegOp2MemOpTableType &R2MTable,
3560 MemOp2RegOpTableType &M2RTable,
3561 uint16_t RegOp, uint16_t MemOp, uint16_t Flags) {
3562 if ((Flags & TB_NO_FORWARD) == 0) {
3563 assert(!R2MTable.count(RegOp) && "Duplicate entry!")((!R2MTable.count(RegOp) && "Duplicate entry!") ? static_cast
<void> (0) : __assert_fail ("!R2MTable.count(RegOp) && \"Duplicate entry!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/Target/X86/X86InstrInfo.cpp"
, 3563, __PRETTY_FUNCTION__))
;
3564 R2MTable[RegOp] = std::make_pair(MemOp, Flags);
3565 }
3566 if ((Flags & TB_NO_REVERSE) == 0) {
3567 assert(!M2RTable.count(MemOp) &&((!M2RTable.count(MemOp) && "Duplicated entries in unfolding maps?"
) ? static_cast<void> (0) : __assert_fail ("!M2RTable.count(MemOp) && \"Duplicated entries in unfolding maps?\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/Target/X86/X86InstrInfo.cpp"
, 3568, __PRETTY_FUNCTION__))
3568 "Duplicated entries in unfolding maps?")((!M2RTable.count(MemOp) && "Duplicated entries in unfolding maps?"
) ? static_cast<void> (0) : __assert_fail ("!M2RTable.count(MemOp) && \"Duplicated entries in unfolding maps?\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/Target/X86/X86InstrInfo.cpp"
, 3568, __PRETTY_FUNCTION__))
;
3569 M2RTable[MemOp] = std::make_pair(RegOp, Flags);
3570 }
3571}
3572
3573bool
3574X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
3575 unsigned &SrcReg, unsigned &DstReg,
3576 unsigned &SubIdx) const {
3577 switch (MI.getOpcode()) {
3578 default: break;
3579 case X86::MOVSX16rr8:
3580 case X86::MOVZX16rr8:
3581 case X86::MOVSX32rr8:
3582 case X86::MOVZX32rr8:
3583 case X86::MOVSX64rr8:
3584 if (!Subtarget.is64Bit())
3585 // It's not always legal to reference the low 8-bit of the larger
3586 // register in 32-bit mode.
3587 return false;
3588 case X86::MOVSX32rr16:
3589 case X86::MOVZX32rr16:
3590 case X86::MOVSX64rr16:
3591 case X86::MOVSX64rr32: {
3592 if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
3593 // Be conservative.
3594 return false;
3595 SrcReg = MI.getOperand(1).getReg();
3596 DstReg = MI.getOperand(0).getReg();
3597 switch (MI.getOpcode()) {
3598 default: llvm_unreachable("Unreachable!")::llvm::llvm_unreachable_internal("Unreachable!", "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/Target/X86/X86InstrInfo.cpp"
, 3598)
;
3599 case X86::MOVSX16rr8:
3600 case X86::MOVZX16rr8:
3601 case X86::MOVSX32rr8:
3602 case X86::MOVZX32rr8:
3603 case X86::MOVSX64rr8:
3604 SubIdx = X86::sub_8bit;
3605 break;
3606 case X86::MOVSX32rr16:
3607 case X86::MOVZX32rr16:
3608 case X86::MOVSX64rr16:
3609 SubIdx = X86::sub_16bit;
3610 break;
3611 case X86::MOVSX64rr32:
3612 SubIdx = X86::sub_32bit;
3613 break;
3614 }
3615 return true;
3616 }
3617 }
3618 return false;
3619}
3620
3621int X86InstrInfo::getSPAdjust(const MachineInstr &MI) const {
3622 const MachineFunction *MF = MI.getParent()->getParent();
3623 const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering();
3624
3625 if (isFrameInstr(MI)) {
3626 unsigned StackAlign = TFI->getStackAlignment();
3627 int SPAdj = alignTo(getFrameSize(MI), StackAlign);
3628 SPAdj -= getFrameAdjustment(MI);
3629 if (!isFrameSetup(MI))
3630 SPAdj = -SPAdj;
3631 return SPAdj;
3632 }
3633
3634 // To know whether a call adjusts the stack, we need information
3635 // that is bound to the following ADJCALLSTACKUP pseudo.
3636 // Look for the next ADJCALLSTACKUP that follows the call.
3637 if (MI.isCall()) {
3638 const MachineBasicBlock *MBB = MI.getParent();
3639 auto I = ++MachineBasicBlock::const_iterator(MI);
3640 for (auto E = MBB->end(); I != E; ++I) {
3641 if (I->getOpcode() == getCallFrameDestroyOpcode() ||
3642 I->isCall())
3643 break;
3644 }
3645
3646 // If we could not find a frame destroy opcode, then it has already
3647 // been simplified, so we don't care.
3648 if (I->getOpcode() != getCallFrameDestroyOpcode())
3649 return 0;
3650
3651 return -(I->getOperand(1).getImm());
3652 }
3653
3654 // Currently handle only PUSHes we can reasonably expect to see
3655 // in call sequences
3656 switch (MI.getOpcode()) {
3657 default:
3658 return 0;
3659 case X86::PUSH32i8:
3660 case X86::PUSH32r:
3661 case X86::PUSH32rmm:
3662 case X86::PUSH32rmr:
3663 case X86::PUSHi32:
3664 return 4;
3665 case X86::PUSH64i8:
3666 case X86::PUSH64r:
3667 case X86::PUSH64rmm:
3668 case X86::PUSH64rmr:
3669 case X86::PUSH64i32:
3670 return 8;
3671 }
3672}
3673
3674/// Return true and the FrameIndex if the specified
3675/// operand and follow operands form a reference to the stack frame.
3676bool X86InstrInfo::isFrameOperand(const MachineInstr &MI, unsigned int Op,
3677 int &FrameIndex) const {
3678 if (MI.getOperand(Op + X86::AddrBaseReg).isFI() &&
3679 MI.getOperand(Op + X86::AddrScaleAmt).isImm() &&
3680 MI.getOperand(Op + X86::AddrIndexReg).isReg() &&
3681 MI.getOperand(Op + X86::AddrDisp).isImm() &&
3682 MI.getOperand(Op + X86::AddrScaleAmt).getImm() == 1 &&
3683 MI.getOperand(Op + X86::AddrIndexReg).getReg() == 0 &&
3684 MI.getOperand(Op + X86::AddrDisp).getImm() == 0) {
3685 FrameIndex = MI.getOperand(Op + X86::AddrBaseReg).getIndex();
3686 return true;
3687 }
3688 return false;
3689}
3690
3691static bool isFrameLoadOpcode(int Opcode) {
3692 switch (Opcode) {
3693 default:
3694 return false;
3695 case X86::MOV8rm:
3696 case X86::MOV16rm:
3697 case X86::MOV32rm:
3698 case X86::MOV64rm:
3699 case X86::LD_Fp64m:
3700 case X86::MOVSSrm:
3701 case X86::MOVSDrm:
3702 case X86::MOVAPSrm:
3703 case X86::MOVUPSrm:
3704 case X86::MOVAPDrm:
3705 case X86::MOVUPDrm:
3706 case X86::MOVDQArm:
3707 case X86::MOVDQUrm:
3708 case X86::VMOVSSrm:
3709 case X86::VMOVSDrm:
3710 case X86::VMOVAPSrm:
3711 case X86::VMOVUPSrm:
3712 case X86::VMOVAPDrm:
3713 case X86::VMOVUPDrm:
3714 case X86::VMOVDQArm:
3715 case X86::VMOVDQUrm:
3716 case X86::VMOVUPSYrm:
3717 case X86::VMOVAPSYrm:
3718 case X86::VMOVUPDYrm:
3719 case X86::VMOVAPDYrm:
3720 case X86::VMOVDQUYrm:
3721 case X86::VMOVDQAYrm:
3722 case X86::MMX_MOVD64rm:
3723 case X86::MMX_MOVQ64rm:
3724 case X86::VMOVSSZrm:
3725 case X86::VMOVSDZrm:
3726 case X86::VMOVAPSZrm:
3727 case X86::VMOVAPSZ128rm:
3728 case X86::VMOVAPSZ256rm:
3729 case X86::VMOVAPSZ128rm_NOVLX:
3730 case X86::VMOVAPSZ256rm_NOVLX:
3731 case X86::VMOVUPSZrm:
3732 case X86::VMOVUPSZ128rm:
3733 case X86::VMOVUPSZ256rm:
3734 case X86::VMOVUPSZ128rm_NOVLX:
3735 case X86::VMOVUPSZ256rm_NOVLX:
3736 case X86::VMOVAPDZrm:
3737 case X86::VMOVAPDZ128rm:
3738 case X86::VMOVAPDZ256rm:
3739 case X86::VMOVUPDZrm:
3740 case X86::VMOVUPDZ128rm:
3741 case X86::VMOVUPDZ256rm:
3742 case X86::VMOVDQA32Zrm:
3743 case X86::VMOVDQA32Z128rm:
3744 case X86::VMOVDQA32Z256rm:
3745 case X86::VMOVDQU32Zrm:
3746 case X86::VMOVDQU32Z128rm:
3747 case X86::VMOVDQU32Z256rm:
3748 case X86::VMOVDQA64Zrm:
3749 case X86::VMOVDQA64Z128rm:
3750 case X86::VMOVDQA64Z256rm:
3751 case X86::VMOVDQU64Zrm:
3752 case X86::VMOVDQU64Z128rm:
3753 case X86::VMOVDQU64Z256rm:
3754 case X86::VMOVDQU8Zrm:
3755 case X86::VMOVDQU8Z128rm:
3756 case X86::VMOVDQU8Z256rm:
3757 case X86::VMOVDQU16Zrm:
3758 case X86::VMOVDQU16Z128rm:
3759 case X86::VMOVDQU16Z256rm:
3760 case X86::KMOVBkm:
3761 case X86::KMOVWkm:
3762 case X86::KMOVDkm:
3763 case X86::KMOVQkm:
3764 return true;
3765 }
3766}
3767
3768static bool isFrameStoreOpcode(int Opcode) {
3769 switch (Opcode) {
3770 default: break;
3771 case X86::MOV8mr:
3772 case X86::MOV16mr:
3773 case X86::MOV32mr:
3774 case X86::MOV64mr:
3775 case X86::ST_FpP64m:
3776 case X86::MOVSSmr:
3777 case X86::MOVSDmr:
3778 case X86::MOVAPSmr:
3779 case X86::MOVUPSmr:
3780 case X86::MOVAPDmr:
3781 case X86::MOVUPDmr:
3782 case X86::MOVDQAmr:
3783 case X86::MOVDQUmr:
3784 case X86::VMOVSSmr:
3785 case X86::VMOVSDmr:
3786 case X86::VMOVAPSmr:
3787 case X86::VMOVUPSmr:
3788 case X86::VMOVAPDmr:
3789 case X86::VMOVUPDmr:
3790 case X86::VMOVDQAmr:
3791 case X86::VMOVDQUmr:
3792 case X86::VMOVUPSYmr:
3793 case X86::VMOVAPSYmr:
3794 case X86::VMOVUPDYmr:
3795 case X86::VMOVAPDYmr:
3796 case X86::VMOVDQUYmr:
3797 case X86::VMOVDQAYmr:
3798 case X86::VMOVSSZmr:
3799 case X86::VMOVSDZmr:
3800 case X86::VMOVUPSZmr:
3801 case X86::VMOVUPSZ128mr:
3802 case X86::VMOVUPSZ256mr:
3803 case X86::VMOVUPSZ128mr_NOVLX:
3804 case X86::VMOVUPSZ256mr_NOVLX:
3805 case X86::VMOVAPSZmr:
3806 case X86::VMOVAPSZ128mr:
3807 case X86::VMOVAPSZ256mr:
3808 case X86::VMOVAPSZ128mr_NOVLX:
3809 case X86::VMOVAPSZ256mr_NOVLX:
3810 case X86::VMOVUPDZmr:
3811 case X86::VMOVUPDZ128mr:
3812 case X86::VMOVUPDZ256mr:
3813 case X86::VMOVAPDZmr:
3814 case X86::VMOVAPDZ128mr:
3815 case X86::VMOVAPDZ256mr:
3816 case X86::VMOVDQA32Zmr:
3817 case X86::VMOVDQA32Z128mr:
3818 case X86::VMOVDQA32Z256mr:
3819 case X86::VMOVDQU32Zmr:
3820 case X86::VMOVDQU32Z128mr:
3821 case X86::VMOVDQU32Z256mr:
3822 case X86::VMOVDQA64Zmr:
3823 case X86::VMOVDQA64Z128mr:
3824 case X86::VMOVDQA64Z256mr:
3825 case X86::VMOVDQU64Zmr:
3826 case X86::VMOVDQU64Z128mr:
3827 case X86::VMOVDQU64Z256mr:
3828 case X86::VMOVDQU8Zmr:
3829 case X86::VMOVDQU8Z128mr:
3830 case X86::VMOVDQU8Z256mr:
3831 case X86::VMOVDQU16Zmr:
3832 case X86::VMOVDQU16Z128mr:
3833 case X86::VMOVDQU16Z256mr:
3834 case X86::MMX_MOVD64mr:
3835 case X86::MMX_MOVQ64mr:
3836 case X86::MMX_MOVNTQmr:
3837 case X86::KMOVBmk:
3838 case X86::KMOVWmk:
3839 case X86::KMOVDmk:
3840 case X86::KMOVQmk:
3841 return true;
3842 }
3843 return false;
3844}
3845
3846unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
3847 int &FrameIndex) const {
3848 if (isFrameLoadOpcode(MI.getOpcode()))
3849 if (MI.getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex))
3850 return MI.getOperand(0).getReg();
3851 return 0;
3852}
3853
3854unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr &MI,
3855 int &FrameIndex) const {
3856 if (isFrameLoadOpcode(MI.getOpcode())) {
3857 unsigned Reg;
3858 if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
3859 return Reg;
3860 // Check for post-frame index elimination operations
3861 const MachineMemOperand *Dummy;
3862 return hasLoadFromStackSlot(MI, Dummy, FrameIndex);
3863 }
3864 return 0;
3865}
3866
3867unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
3868 int &FrameIndex) const {
3869 if (isFrameStoreOpcode(MI.getOpcode()))
3870 if (MI.getOperand(X86::AddrNumOperands).getSubReg() == 0 &&
3871 isFrameOperand(MI, 0, FrameIndex))
3872 return MI.getOperand(X86::AddrNumOperands).getReg();
3873 return 0;
3874}
3875
3876unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr &MI,
3877 int &FrameIndex) const {
3878 if (isFrameStoreOpcode(MI.getOpcode())) {
3879 unsigned Reg;
3880 if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
3881 return Reg;
3882 // Check for post-frame index elimination operations
3883 const MachineMemOperand *Dummy;
3884 return hasStoreToStackSlot(MI, Dummy, FrameIndex);
3885 }
3886 return 0;
3887}
3888
3889/// Return true if register is PIC base; i.e.g defined by X86::MOVPC32r.
3890static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
3891 // Don't waste compile time scanning use-def chains of physregs.
3892 if (!TargetRegisterInfo::isVirtualRegister(BaseReg))
3893 return false;
3894 bool isPICBase = false;
3895 for (MachineRegisterInfo::def_instr_iterator I = MRI.def_instr_begin(BaseReg),
3896 E = MRI.def_instr_end(); I != E; ++I) {
3897 MachineInstr *DefMI = &*I;
3898 if (DefMI->getOpcode() != X86::MOVPC32r)
3899 return false;
3900 assert(!isPICBase && "More than one PIC base?")((!isPICBase && "More than one PIC base?") ? static_cast
<void> (0) : __assert_fail ("!isPICBase && \"More than one PIC base?\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/Target/X86/X86InstrInfo.cpp"
, 3900, __PRETTY_FUNCTION__))
;
3901 isPICBase = true;
3902 }
3903 return isPICBase;
3904}
3905
3906bool X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr &MI,
3907 AliasAnalysis *AA) const {
3908 switch (MI.getOpcode()) {
3909 default: break;
3910 case X86::MOV8rm:
3911 case X86::MOV8rm_NOREX:
3912 case X86::MOV16rm:
3913 case X86::MOV32rm:
3914 case X86::MOV64rm:
3915 case X86::LD_Fp64m:
3916 case X86::MOVSSrm:
3917 case X86::MOVSDrm:
3918 case X86::MOVAPSrm:
3919 case X86::MOVUPSrm:
3920 case X86::MOVAPDrm:
3921 case X86::MOVUPDrm:
3922 case X86::MOVDQArm:
3923 case X86::MOVDQUrm:
3924 case X86::VMOVSSrm:
3925 case X86::VMOVSDrm:
3926 case X86::VMOVAPSrm:
3927 case X86::VMOVUPSrm:
3928 case X86::VMOVAPDrm:
3929 case X86::VMOVUPDrm:
3930 case X86::VMOVDQArm:
3931 case X86::VMOVDQUrm:
3932 case X86::VMOVAPSYrm:
3933 case X86::VMOVUPSYrm:
3934 case X86::VMOVAPDYrm:
3935 case X86::VMOVUPDYrm:
3936 case X86::VMOVDQAYrm:
3937 case X86::VMOVDQUYrm:
3938 case X86::MMX_MOVD64rm:
3939 case X86::MMX_MOVQ64rm:
3940 // AVX-512
3941 case X86::VMOVSSZrm:
3942 case X86::VMOVSDZrm:
3943 case X86::VMOVAPDZ128rm:
3944 case X86::VMOVAPDZ256rm:
3945 case X86::VMOVAPDZrm:
3946 case X86::VMOVAPSZ128rm:
3947 case X86::VMOVAPSZ256rm:
3948 case X86::VMOVAPSZ128rm_NOVLX:
3949 case X86::VMOVAPSZ256rm_NOVLX:
3950 case X86::VMOVAPSZrm:
3951 case X86::VMOVDQA32Z128rm:
3952 case X86::VMOVDQA32Z256rm:
3953 case X86::VMOVDQA32Zrm:
3954 case X86::VMOVDQA64Z128rm:
3955 case X86::VMOVDQA64Z256rm:
3956 case X86::VMOVDQA64Zrm:
3957 case X86::VMOVDQU16Z128rm:
3958 case X86::VMOVDQU16Z256rm:
3959 case X86::VMOVDQU16Zrm:
3960 case X86::VMOVDQU32Z128rm:
3961 case X86::VMOVDQU32Z256rm:
3962 case X86::VMOVDQU32Zrm:
3963 case X86::VMOVDQU64Z128rm:
3964 case X86::VMOVDQU64Z256rm:
3965 case X86::VMOVDQU64Zrm:
3966 case X86::VMOVDQU8Z128rm:
3967 case X86::VMOVDQU8Z256rm:
3968 case X86::VMOVDQU8Zrm:
3969 case X86::VMOVUPDZ128rm:
3970 case X86::VMOVUPDZ256rm:
3971 case X86::VMOVUPDZrm:
3972 case X86::VMOVUPSZ128rm:
3973 case X86::VMOVUPSZ256rm:
3974 case X86::VMOVUPSZ128rm_NOVLX:
3975 case X86::VMOVUPSZ256rm_NOVLX:
3976 case X86::VMOVUPSZrm: {
3977 // Loads from constant pools are trivially rematerializable.
3978 if (MI.getOperand(1 + X86::AddrBaseReg).isReg() &&
3979 MI.getOperand(1 + X86::AddrScaleAmt).isImm() &&
3980 MI.getOperand(1 + X86::AddrIndexReg).isReg() &&
3981 MI.getOperand(1 + X86::AddrIndexReg).getReg() == 0 &&
3982 MI.isDereferenceableInvariantLoad(AA)) {
3983 unsigned BaseReg = MI.getOperand(1 + X86::AddrBaseReg).getReg();
3984 if (BaseReg == 0 || BaseReg == X86::RIP)
3985 return true;
3986 // Allow re-materialization of PIC load.
3987 if (!ReMatPICStubLoad && MI.getOperand(1 + X86::AddrDisp).isGlobal())
3988 return false;
3989 const MachineFunction &MF = *MI.getParent()->getParent();
3990 const MachineRegisterInfo &MRI = MF.getRegInfo();
3991 return regIsPICBase(BaseReg, MRI);
3992 }
3993 return false;
3994 }
3995
3996 case X86::LEA32r:
3997 case X86::LEA64r: {
3998 if (MI.getOperand(1 + X86::AddrScaleAmt).isImm() &&
3999 MI.getOperand(1 + X86::AddrIndexReg).isReg() &&
4000 MI.getOperand(1 + X86::AddrIndexReg).getReg() == 0 &&
4001 !MI.getOperand(1 + X86::AddrDisp).isReg()) {
4002 // lea fi#, lea GV, etc. are all rematerializable.
4003 if (!MI.getOperand(1 + X86::AddrBaseReg).isReg())
4004 return true;
4005 unsigned BaseReg = MI.getOperand(1 + X86::AddrBaseReg).getReg();
4006 if (BaseReg == 0)
4007 return true;
4008 // Allow re-materialization of lea PICBase + x.
4009 const MachineFunction &MF = *MI.getParent()->getParent();
4010 const MachineRegisterInfo &MRI = MF.getRegInfo();
4011 return regIsPICBase(BaseReg, MRI);
4012 }
4013 return false;
4014 }
4015 }
4016
4017 // All other instructions marked M_REMATERIALIZABLE are always trivially
4018 // rematerializable.
4019 return true;
4020}
4021
4022bool X86InstrInfo::isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
4023 MachineBasicBlock::iterator I) const {
4024 MachineBasicBlock::iterator E = MBB.end();
4025
4026 // For compile time consideration, if we are not able to determine the
4027 // safety after visiting 4 instructions in each direction, we will assume
4028 // it's not safe.
4029 MachineBasicBlock::iterator Iter = I;
4030 for (unsigned i = 0; Iter != E && i < 4; ++i) {
4031 bool SeenDef = false;
4032 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
4033 MachineOperand &MO = Iter->getOperand(j);
4034 if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
4035 SeenDef = true;
4036 if (!MO.isReg())
4037 continue;
4038 if (MO.getReg() == X86::EFLAGS) {
4039 if (MO.isUse())
4040 return false;
4041 SeenDef = true;
4042 }
4043 }
4044
4045 if (SeenDef)
4046 // This instruction defines EFLAGS, no need to look any further.
4047 return true;
4048 ++Iter;
4049 // Skip over DBG_VALUE.
4050 while (Iter != E && Iter->isDebugValue())
4051 ++Iter;
4052 }
4053
4054 // It is safe to clobber EFLAGS at the end of a block of no successor has it
4055 // live in.
4056 if (Iter == E) {
4057 for (MachineBasicBlock *S : MBB.successors())
4058 if (S->isLiveIn(X86::EFLAGS))
4059 return false;
4060 return true;
4061 }
4062
4063 MachineBasicBlock::iterator B = MBB.begin();
4064 Iter = I;
4065 for (unsigned i = 0; i < 4; ++i) {
4066 // If we make it to the beginning of the block, it's safe to clobber
4067 // EFLAGS iff EFLAGS is not live-in.
4068 if (Iter == B)
4069 return !MBB.isLiveIn(X86::EFLAGS);
4070
4071 --Iter;
4072 // Skip over DBG_VALUE.
4073 while (Iter != B && Iter->isDebugValue())
4074 --Iter;
4075
4076 bool SawKill = false;
4077 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
4078 MachineOperand &MO = Iter->getOperand(j);
4079 // A register mask may clobber EFLAGS, but we should still look for a
4080 // live EFLAGS def.
4081 if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
4082 SawKill = true;
4083 if (MO.isReg() && MO.getReg() == X86::EFLAGS) {
4084 if (MO.isDef()) return MO.isDead();
4085 if (MO.isKill()) SawKill = true;
4086 }
4087 }
4088
4089 if (SawKill)
4090 // This instruction kills EFLAGS and doesn't redefine it, so
4091 // there's no need to look further.
4092 return true;
4093 }
4094
4095 // Conservative answer.
4096 return false;
4097}
4098
4099void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
4100 MachineBasicBlock::iterator I,
4101 unsigned DestReg, unsigned SubIdx,
4102 const MachineInstr &Orig,
4103 const TargetRegisterInfo &TRI) const {
4104 bool ClobbersEFLAGS = false;
4105 for (const MachineOperand &MO : Orig.operands()) {
4106 if (MO.isReg() && MO.isDef() && MO.getReg() == X86::EFLAGS) {
4107 ClobbersEFLAGS = true;
4108 break;
4109 }
4110 }
4111
4112 if (ClobbersEFLAGS && !isSafeToClobberEFLAGS(MBB, I)) {
4113 // The instruction clobbers EFLAGS. Re-materialize as MOV32ri to avoid side
4114 // effects.
4115 int Value;
4116 switch (Orig.getOpcode()) {
4117 case X86::MOV32r0: Value = 0; break;
4118 case X86::MOV32r1: Value = 1; break;
4119 case X86::MOV32r_1: Value = -1; break;
4120 default:
4121 llvm_unreachable("Unexpected instruction!")::llvm::llvm_unreachable_internal("Unexpected instruction!", "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/Target/X86/X86InstrInfo.cpp"
, 4121)
;
4122 }
4123
4124 const DebugLoc &DL = Orig.getDebugLoc();
4125 BuildMI(MBB, I, DL, get(X86::MOV32ri))
4126 .add(Orig.getOperand(0))
4127 .addImm(Value);
4128 } else {
4129 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(&Orig);
4130 MBB.insert(I, MI);
4131 }
4132
4133 MachineInstr &NewMI = *std::prev(I);
4134 NewMI.substituteRegister(Orig.getOperand(0).getReg(), DestReg, SubIdx, TRI);
4135}
4136
4137/// True if MI has a condition code def, e.g. EFLAGS, that is not marked dead.
4138bool X86InstrInfo::hasLiveCondCodeDef(MachineInstr &MI) const {
4139 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
4140 MachineOperand &MO = MI.getOperand(i);
4141 if (MO.isReg() && MO.isDef() &&
4142 MO.getReg() == X86::EFLAGS && !MO.isDead()) {
4143 return true;
4144 }
4145 }
4146 return false;
4147}
4148
4149/// Check whether the shift count for a machine operand is non-zero.
4150inline static unsigned getTruncatedShiftCount(MachineInstr &MI,
4151 unsigned ShiftAmtOperandIdx) {
4152 // The shift count is six bits with the REX.W prefix and five bits without.
4153 unsigned ShiftCountMask = (MI.getDesc().TSFlags & X86II::REX_W) ? 63 : 31;
4154 unsigned Imm = MI.getOperand(ShiftAmtOperandIdx).getImm();
4155 return Imm & ShiftCountMask;
4156}
4157
4158/// Check whether the given shift count is appropriate
4159/// can be represented by a LEA instruction.
4160inline static bool isTruncatedShiftCountForLEA(unsigned ShAmt) {
4161 // Left shift instructions can be transformed into load-effective-address
4162 // instructions if we can encode them appropriately.
4163 // A LEA instruction utilizes a SIB byte to encode its scale factor.
4164 // The SIB.scale field is two bits wide which means that we can encode any
4165 // shift amount less than 4.
4166 return ShAmt < 4 && ShAmt > 0;
4167}
4168
4169bool X86InstrInfo::classifyLEAReg(MachineInstr &MI, const MachineOperand &Src,
4170 unsigned Opc, bool AllowSP, unsigned &NewSrc,
4171 bool &isKill, bool &isUndef,
4172 MachineOperand &ImplicitOp,
4173 LiveVariables *LV) const {
4174 MachineFunction &MF = *MI.getParent()->getParent();
4175 const TargetRegisterClass *RC;
4176 if (AllowSP) {
4177 RC = Opc != X86::LEA32r ? &X86::GR64RegClass : &X86::GR32RegClass;
4178 } else {
4179 RC = Opc != X86::LEA32r ?
4180 &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass;
4181 }
4182 unsigned SrcReg = Src.getReg();
4183
4184 // For both LEA64 and LEA32 the register already has essentially the right
4185 // type (32-bit or 64-bit) we may just need to forbid SP.
4186 if (Opc != X86::LEA64_32r) {
4187 NewSrc = SrcReg;
4188 isKill = Src.isKill();
4189 isUndef = Src.isUndef();
4190
4191 if (TargetRegisterInfo::isVirtualRegister(NewSrc) &&
4192 !MF.getRegInfo().constrainRegClass(NewSrc, RC))
4193 return false;
4194
4195 return true;
4196 }
4197
4198 // This is for an LEA64_32r and incoming registers are 32-bit. One way or
4199 // another we need to add 64-bit registers to the final MI.
4200 if (TargetRegisterInfo::isPhysicalRegister(SrcReg)) {
4201 ImplicitOp = Src;
4202 ImplicitOp.setImplicit();
4203
4204 NewSrc = getX86SubSuperRegister(Src.getReg(), 64);
4205 isKill = Src.isKill();
4206 isUndef = Src.isUndef();
4207 } else {
4208 // Virtual register of the wrong class, we have to create a temporary 64-bit
4209 // vreg to feed into the LEA.
4210 NewSrc = MF.getRegInfo().createVirtualRegister(RC);
4211 MachineInstr *Copy =
4212 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(TargetOpcode::COPY))
4213 .addReg(NewSrc, RegState::Define | RegState::Undef, X86::sub_32bit)
4214 .add(Src);
4215
4216 // Which is obviously going to be dead after we're done with it.
4217 isKill = true;
4218 isUndef = false;
4219
4220 if (LV)
4221 LV->replaceKillInstruction(SrcReg, MI, *Copy);
4222 }
4223
4224 // We've set all the parameters without issue.
4225 return true;
4226}
4227
4228/// Helper for convertToThreeAddress when 16-bit LEA is disabled, use 32-bit
4229/// LEA to form 3-address code by promoting to a 32-bit superregister and then
4230/// truncating back down to a 16-bit subregister.
4231MachineInstr *X86InstrInfo::convertToThreeAddressWithLEA(
4232 unsigned MIOpc, MachineFunction::iterator &MFI, MachineInstr &MI,
4233 LiveVariables *LV) const {
4234 MachineBasicBlock::iterator MBBI = MI.getIterator();
4235 unsigned Dest = MI.getOperand(0).getReg();
4236 unsigned Src = MI.getOperand(1).getReg();
4237 bool isDead = MI.getOperand(0).isDead();
4238 bool isKill = MI.getOperand(1).isKill();
4239
4240 MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
4241 unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
4242 unsigned Opc, leaInReg;
4243 if (Subtarget.is64Bit()) {
4244 Opc = X86::LEA64_32r;
4245 leaInReg = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
4246 } else {
4247 Opc = X86::LEA32r;
4248 leaInReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
4249 }
4250
4251 // Build and insert into an implicit UNDEF value. This is OK because
4252 // well be shifting and then extracting the lower 16-bits.
4253 // This has the potential to cause partial register stall. e.g.
4254 // movw (%rbp,%rcx,2), %dx
4255 // leal -65(%rdx), %esi
4256 // But testing has shown this *does* help performance in 64-bit mode (at
4257 // least on modern x86 machines).
4258 BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg);
4259 MachineInstr *InsMI =
4260 BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(TargetOpcode::COPY))
4261 .addReg(leaInReg, RegState::Define, X86::sub_16bit)
4262 .addReg(Src, getKillRegState(isKill));
4263
4264 MachineInstrBuilder MIB =
4265 BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(Opc), leaOutReg);
4266 switch (MIOpc) {
4267 default: llvm_unreachable("Unreachable!")::llvm::llvm_unreachable_internal("Unreachable!", "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/Target/X86/X86InstrInfo.cpp"
, 4267)
;
4268 case X86::SHL16ri: {
4269 unsigned ShAmt = MI.getOperand(2).getImm();
4270 MIB.addReg(0).addImm(1ULL << ShAmt)
4271 .addReg(leaInReg, RegState::Kill).addImm(0).addReg(0);
4272 break;
4273 }
4274 case X86::INC16r:
4275 addRegOffset(MIB, leaInReg, true, 1);
4276 break;
4277 case X86::DEC16r:
4278 addRegOffset(MIB, leaInReg, true, -1);
4279 break;
4280 case X86::ADD16ri:
4281 case X86::ADD16ri8:
4282 case X86::ADD16ri_DB:
4283 case X86::ADD16ri8_DB:
4284 addRegOffset(MIB, leaInReg, true, MI.getOperand(2).getImm());
4285 break;
4286 case X86::ADD16rr:
4287 case X86::ADD16rr_DB: {
4288 unsigned Src2 = MI.getOperand(2).getReg();
4289 bool isKill2 = MI.getOperand(2).isKill();
4290 unsigned leaInReg2 = 0;
4291 MachineInstr *InsMI2 = nullptr;
4292 if (Src == Src2) {
4293 // ADD16rr %reg1028<kill>, %reg1028
4294 // just a single insert_subreg.
4295 addRegReg(MIB, leaInReg, true, leaInReg, false);
4296 } else {
4297 if (Subtarget.is64Bit())
4298 leaInReg2 = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
4299 else
4300 leaInReg2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
4301 // Build and insert into an implicit UNDEF value. This is OK because
4302 // well be shifting and then extracting the lower 16-bits.
4303 BuildMI(*MFI, &*MIB, MI.getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg2);
4304 InsMI2 = BuildMI(*MFI, &*MIB, MI.getDebugLoc(), get(TargetOpcode::COPY))
4305 .addReg(leaInReg2, RegState::Define, X86::sub_16bit)
4306 .addReg(Src2, getKillRegState(isKill2));
4307 addRegReg(MIB, leaInReg, true, leaInReg2, true);
4308 }
4309 if (LV && isKill2 && InsMI2)
4310 LV->replaceKillInstruction(Src2, MI, *InsMI2);
4311 break;
4312 }
4313 }
4314
4315 MachineInstr *NewMI = MIB;
4316 MachineInstr *ExtMI =
4317 BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(TargetOpcode::COPY))
4318 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
4319 .addReg(leaOutReg, RegState::Kill, X86::sub_16bit);
4320
4321 if (LV) {
4322 // Update live variables
4323 LV->getVarInfo(leaInReg).Kills.push_back(NewMI);
4324 LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI);
4325 if (isKill)
4326 LV->replaceKillInstruction(Src, MI, *InsMI);
4327 if (isDead)
4328 LV->replaceKillInstruction(Dest, MI, *ExtMI);
4329 }
4330
4331 return ExtMI;
4332}
4333
4334/// This method must be implemented by targets that
4335/// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
4336/// may be able to convert a two-address instruction into a true
4337/// three-address instruction on demand. This allows the X86 target (for
4338/// example) to convert ADD and SHL instructions into LEA instructions if they
4339/// would require register copies due to two-addressness.
4340///
4341/// This method returns a null pointer if the transformation cannot be
4342/// performed, otherwise it returns the new instruction.
4343///
4344MachineInstr *
4345X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
4346 MachineInstr &MI, LiveVariables *LV) const {
4347 // The following opcodes also sets the condition code register(s). Only
4348 // convert them to equivalent lea if the condition code register def's
4349 // are dead!
4350 if (hasLiveCondCodeDef(MI))
4351 return nullptr;
4352
4353 MachineFunction &MF = *MI.getParent()->getParent();
4354 // All instructions input are two-addr instructions. Get the known operands.
4355 const MachineOperand &Dest = MI.getOperand(0);
4356 const MachineOperand &Src = MI.getOperand(1);
4357
4358 MachineInstr *NewMI = nullptr;
4359 // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When
4360 // we have better subtarget support, enable the 16-bit LEA generation here.
4361 // 16-bit LEA is also slow on Core2.
4362 bool DisableLEA16 = true;
4363 bool is64Bit = Subtarget.is64Bit();
4364
4365 unsigned MIOpc = MI.getOpcode();
4366 switch (MIOpc) {
4367 default: return nullptr;
4368 case X86::SHL64ri: {
4369 assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!")((MI.getNumOperands() >= 3 && "Unknown shift instruction!"
) ? static_cast<void> (0) : __assert_fail ("MI.getNumOperands() >= 3 && \"Unknown shift instruction!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/Target/X86/X86InstrInfo.cpp"
, 4369, __PRETTY_FUNCTION__))
;
4370 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
4371 if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
4372
4373 // LEA can't handle RSP.
4374 if (TargetRegisterInfo::isVirtualRegister(Src.getReg()) &&
4375 !MF.getRegInfo().constrainRegClass(Src.getReg(),
4376 &X86::GR64_NOSPRegClass))
4377 return nullptr;
4378
4379 NewMI = BuildMI(MF, MI.getDebugLoc(), get(X86::LEA64r))
4380 .add(Dest)
4381 .addReg(0)
4382 .addImm(1ULL << ShAmt)
4383 .add(Src)
4384 .addImm(0)
4385 .addReg(0);
4386 break;
4387 }
4388 case X86::SHL32ri: {
4389 assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!")((MI.getNumOperands() >= 3 && "Unknown shift instruction!"
) ? static_cast<void> (0) : __assert_fail ("MI.getNumOperands() >= 3 && \"Unknown shift instruction!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/Target/X86/X86InstrInfo.cpp"
, 4389, __PRETTY_FUNCTION__))
;
4390 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
4391 if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
4392
4393 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
4394
4395 // LEA can't handle ESP.
4396 bool isKill, isUndef;
4397 unsigned SrcReg;
4398 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
4399 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
4400 SrcReg, isKill, isUndef, ImplicitOp, LV))
4401 return nullptr;
4402
4403 MachineInstrBuilder MIB =
4404 BuildMI(MF, MI.getDebugLoc(), get(Opc))
4405 .add(Dest)
4406 .addReg(0)
4407 .addImm(1ULL << ShAmt)
4408 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
4409 .addImm(0)
4410 .addReg(0);
4411 if (ImplicitOp.getReg() != 0)
4412 MIB.add(ImplicitOp);
4413 NewMI = MIB;
4414
4415 break;
4416 }
4417 case X86::SHL16ri: {
4418 assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!")((MI.getNumOperands() >= 3 && "Unknown shift instruction!"
) ? static_cast<void> (0) : __assert_fail ("MI.getNumOperands() >= 3 && \"Unknown shift instruction!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/Target/X86/X86InstrInfo.cpp"
, 4418, __PRETTY_FUNCTION__))
;
4419 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
4420 if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
4421
4422 if (DisableLEA16)
4423 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV)
4424 : nullptr;
4425 NewMI = BuildMI(MF, MI.getDebugLoc(), get(X86::LEA16r))
4426 .add(Dest)
4427 .addReg(0)
4428 .addImm(1ULL << ShAmt)
4429 .add(Src)
4430 .addImm(0)
4431 .addReg(0);
4432 break;
4433 }
4434 case X86::INC64r:
4435 case X86::INC32r: {
4436 assert(MI.getNumOperands() >= 2 && "Unknown inc instruction!")((MI.getNumOperands() >= 2 && "Unknown inc instruction!"
) ? static_cast<void> (0) : __assert_fail ("MI.getNumOperands() >= 2 && \"Unknown inc instruction!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/Target/X86/X86InstrInfo.cpp"
, 4436, __PRETTY_FUNCTION__))
;
4437 unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
4438 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
4439 bool isKill, isUndef;
4440 unsigned SrcReg;
4441 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
4442 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
4443 SrcReg, isKill, isUndef, ImplicitOp, LV))
4444 return nullptr;
4445
4446 MachineInstrBuilder MIB =
4447 BuildMI(MF, MI.getDebugLoc(), get(Opc))
4448 .add(Dest)
4449 .addReg(SrcReg,
4450 getKillRegState(isKill) | getUndefRegState(isUndef));
4451 if (ImplicitOp.getReg() != 0)
4452 MIB.add(ImplicitOp);
4453
4454 NewMI = addOffset(MIB, 1);
4455 break;
4456 }
4457 case X86::INC16r:
4458 if (DisableLEA16)
4459 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV)
4460 : nullptr;
4461 assert(MI.getNumOperands() >= 2 && "Unknown inc instruction!")((MI.getNumOperands() >= 2 && "Unknown inc instruction!"
) ? static_cast<void> (0) : __assert_fail ("MI.getNumOperands() >= 2 && \"Unknown inc instruction!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/Target/X86/X86InstrInfo.cpp"
, 4461, __PRETTY_FUNCTION__))
;
4462 NewMI = addOffset(
4463 BuildMI(MF, MI.getDebugLoc(), get(X86::LEA16r)).add(Dest).add(Src), 1);
4464 break;
4465 case X86::DEC64r:
4466 case X86::DEC32r: {
4467 assert(MI.getNumOperands() >= 2 && "Unknown dec instruction!")((MI.getNumOperands() >= 2 && "Unknown dec instruction!"
) ? static_cast<void> (0) : __assert_fail ("MI.getNumOperands() >= 2 && \"Unknown dec instruction!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/Target/X86/X86InstrInfo.cpp"
, 4467, __PRETTY_FUNCTION__))
;
4468 unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
4469 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
4470
4471 bool isKill, isUndef;
4472 unsigned SrcReg;
4473 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
4474 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
4475 SrcReg, isKill, isUndef, ImplicitOp, LV))
4476 return nullptr;
4477
4478 MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
4479 .add(Dest)
4480 .addReg(SrcReg, getUndefRegState(isUndef) |
4481 getKillRegState(isKill));
4482 if (ImplicitOp.getReg() != 0)
4483 MIB.add(ImplicitOp);
4484
4485 NewMI = addOffset(MIB, -1);
4486
4487 break;
4488 }
4489 case X86::DEC16r:
4490 if (DisableLEA16)
4491 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV)
4492 : nullptr;
4493 assert(MI.getNumOperands() >= 2 && "Unknown dec instruction!")((MI.getNumOperands() >= 2 && "Unknown dec instruction!"
) ? static_cast<void> (0) : __assert_fail ("MI.getNumOperands() >= 2 && \"Unknown dec instruction!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/Target/X86/X86InstrInfo.cpp"
, 4493, __PRETTY_FUNCTION__))
;
4494 NewMI = addOffset(
4495 BuildMI(MF, MI.getDebugLoc(), get(X86::LEA16r)).add(Dest).add(Src), -1);
4496 break;
4497 case X86::ADD64rr:
4498 case X86::ADD64rr_DB:
4499 case X86::ADD32rr:
4500 case X86::ADD32rr_DB: {
4501 assert(MI.getNumOperands() >= 3 && "Unknown add instruction!")((MI.getNumOperands() >= 3 && "Unknown add instruction!"
) ? static_cast<void> (0) : __assert_fail ("MI.getNumOperands() >= 3 && \"Unknown add instruction!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/Target/X86/X86InstrInfo.cpp"
, 4501, __PRETTY_FUNCTION__))
;
4502 unsigned Opc;
4503 if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB)
4504 Opc = X86::LEA64r;
4505 else
4506 Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
4507
4508 bool isKill, isUndef;
4509 unsigned SrcReg;
4510 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
4511 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
4512 SrcReg, isKill, isUndef, ImplicitOp, LV))
4513 return nullptr;
4514
4515 const MachineOperand &Src2 = MI.getOperand(2);
4516 bool isKill2, isUndef2;
4517 unsigned SrcReg2;
4518 MachineOperand ImplicitOp2 = MachineOperand::CreateReg(0, false);
4519 if (!classifyLEAReg(MI, Src2, Opc, /*AllowSP=*/ false,
4520 SrcReg2, isKill2, isUndef2, ImplicitOp2, LV))
4521 return nullptr;
4522
4523 MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc)).add(Dest);
4524 if (ImplicitOp.getReg() != 0)
4525 MIB.add(ImplicitOp);
4526 if (ImplicitOp2.getReg() != 0)
4527 MIB.add(ImplicitOp2);
4528
4529 NewMI = addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2);
4530
4531 // Preserve undefness of the operands.
4532 NewMI->getOperand(1).setIsUndef(isUndef);
4533 NewMI->getOperand(3).setIsUndef(isUndef2);
4534
4535 if (LV && Src2.isKill())
4536 LV->replaceKillInstruction(SrcReg2, MI, *NewMI);
4537 break;
4538 }
4539 case X86::ADD16rr:
4540 case X86::ADD16rr_DB: {
4541 if (DisableLEA16)
4542 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV)
4543 : nullptr;
4544 assert(MI.getNumOperands() >= 3 && "Unknown add instruction!")((MI.getNumOperands() >= 3 && "Unknown add instruction!"
) ? static_cast<void> (0) : __assert_fail ("MI.getNumOperands() >= 3 && \"Unknown add instruction!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/Target/X86/X86InstrInfo.cpp"
, 4544, __PRETTY_FUNCTION__))
;
4545 unsigned Src2 = MI.getOperand(2).getReg();
4546 bool isKill2 = MI.getOperand(2).isKill();
4547 NewMI = addRegReg(BuildMI(MF, MI.getDebugLoc(), get(X86::LEA16r)).add(Dest),
4548 Src.getReg(), Src.isKill(), Src2, isKill2);
4549
4550 // Preserve undefness of the operands.
4551 bool isUndef = MI.getOperand(1).isUndef();
4552 bool isUndef2 = MI.getOperand(2).isUndef();
4553 NewMI->getOperand(1).setIsUndef(isUndef);
4554 NewMI->getOperand(3).setIsUndef(isUndef2);
4555
4556 if (LV && isKill2)
4557 LV->replaceKillInstruction(Src2, MI, *NewMI);
4558 break;
4559 }
4560 case X86::ADD64ri32:
4561 case X86::ADD64ri8:
4562 case X86::ADD64ri32_DB:
4563 case X86::ADD64ri8_DB:
4564 assert(MI.getNumOperands() >= 3 && "Unknown add instruction!")((MI.getNumOperands() >= 3 && "Unknown add instruction!"
) ? static_cast<void> (0) : __assert_fail ("MI.getNumOperands() >= 3 && \"Unknown add instruction!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/Target/X86/X86InstrInfo.cpp"
, 4564, __PRETTY_FUNCTION__))
;
4565 NewMI = addOffset(
4566 BuildMI(MF, MI.getDebugLoc(), get(X86::LEA64r)).add(Dest).add(Src),
4567 MI.getOperand(2));
4568 break;
4569 case X86::ADD32ri:
4570 case X86::ADD32ri8:
4571 case X86::ADD32ri_DB:
4572 case X86::ADD32ri8_DB: {
4573 assert(MI.getNumOperands() >= 3 && "Unknown add instruction!")((MI.getNumOperands() >= 3 && "Unknown add instruction!"
) ? static_cast<void> (0) : __assert_fail ("MI.getNumOperands() >= 3 && \"Unknown add instruction!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/Target/X86/X86InstrInfo.cpp"
, 4573, __PRETTY_FUNCTION__))
;
4574 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
4575
4576 bool isKill, isUndef;
4577 unsigned SrcReg;
4578 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
4579 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
4580 SrcReg, isKill, isUndef, ImplicitOp, LV))
4581 return nullptr;
4582
4583 MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
4584 .add(Dest)
4585 .addReg(SrcReg, getUndefRegState(isUndef) |
4586 getKillRegState(isKill));
4587 if (ImplicitOp.getReg() != 0)
4588 MIB.add(ImplicitOp);
4589
4590 NewMI = addOffset(MIB, MI.getOperand(2));
4591 break;
4592 }
4593 case X86::ADD16ri:
4594 case X86::ADD16ri8:
4595 case X86::ADD16ri_DB:
4596 case X86::ADD16ri8_DB:
4597 if (DisableLEA16)
4598 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV)
4599 : nullptr;
4600 assert(MI.getNumOperands() >= 3 && "Unknown add instruction!")((MI.getNumOperands() >= 3 && "Unknown add instruction!"
) ? static_cast<void> (0) : __assert_fail ("MI.getNumOperands() >= 3 && \"Unknown add instruction!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/Target/X86/X86InstrInfo.cpp"
, 4600, __PRETTY_FUNCTION__))
;
4601 NewMI = addOffset(
4602 BuildMI(MF, MI.getDebugLoc(), get(X86::LEA16r)).add(Dest).add(Src),
4603 MI.getOperand(2));
4604 break;
4605
4606 case X86::VMOVDQU8Z128rmk:
4607 case X86::VMOVDQU8Z256rmk:
4608 case X86::VMOVDQU8Zrmk:
4609 case X86::VMOVDQU16Z128rmk:
4610 case X86::VMOVDQU16Z256rmk:
4611 case X86::VMOVDQU16Zrmk:
4612 case X86::VMOVDQU32Z128rmk: case X86::VMOVDQA32Z128rmk:
4613 case X86::VMOVDQU32Z256rmk: case X86::VMOVDQA32Z256rmk:
4614 case X86::VMOVDQU32Zrmk: case X86::VMOVDQA32Zrmk:
4615 case X86::VMOVDQU64Z128rmk: case X86::VMOVDQA64Z128rmk:
4616 case X86::VMOVDQU64Z256rmk: case X86::VMOVDQA64Z256rmk:
4617 case X86::VMOVDQU64Zrmk: case X86::VMOVDQA64Zrmk:
4618 case X86::VMOVUPDZ128rmk: case X86::VMOVAPDZ128rmk:
4619 case X86::VMOVUPDZ256rmk: case X86::VMOVAPDZ256rmk:
4620 case X86::VMOVUPDZrmk: case X86::VMOVAPDZrmk:
4621 case X86::VMOVUPSZ128rmk: case X86::VMOVAPSZ128rmk:
4622 case X86::VMOVUPSZ256rmk: case X86::VMOVAPSZ256rmk:
4623 case X86::VMOVUPSZrmk: case X86::VMOVAPSZrmk: {
4624 unsigned Opc;
4625 switch (MIOpc) {
4626 default: llvm_unreachable("Unreachable!")::llvm::llvm_unreachable_internal("Unreachable!", "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/Target/X86/X86InstrInfo.cpp"
, 4626)
;
4627 case X86::VMOVDQU8Z128rmk: Opc = X86::VPBLENDMBZ128rmk; break;
4628 case X86::VMOVDQU8Z256rmk: Opc = X86::VPBLENDMBZ256rmk; break;
4629 case X86::VMOVDQU8Zrmk: Opc = X86::VPBLENDMBZrmk; break;
4630 case X86::VMOVDQU16Z128rmk: Opc = X86::VPBLENDMWZ128rmk; break;
4631 case X86::VMOVDQU16Z256rmk: Opc = X86::VPBLENDMWZ256rmk; break;
4632 case X86::VMOVDQU16Zrmk: Opc = X86::VPBLENDMWZrmk; break;
4633 case X86::VMOVDQU32Z128rmk: Opc = X86::VPBLENDMDZ128rmk; break;
4634 case X86::VMOVDQU32Z256rmk: Opc = X86::VPBLENDMDZ256rmk; break;
4635 case X86::VMOVDQU32Zrmk: Opc = X86::VPBLENDMDZrmk; break;
4636 case X86::VMOVDQU64Z128rmk: Opc = X86::VPBLENDMQZ128rmk; break;
4637 case X86::VMOVDQU64Z256rmk: Opc = X86::VPBLENDMQZ256rmk; break;
4638 case X86::VMOVDQU64Zrmk: Opc = X86::VPBLENDMQZrmk; break;
4639 case X86::VMOVUPDZ128rmk: Opc = X86::VBLENDMPDZ128rmk; break;
4640 case X86::VMOVUPDZ256rmk: Opc = X86::VBLENDMPDZ256rmk; break;
4641 case X86::VMOVUPDZrmk: Opc = X86::VBLENDMPDZrmk; break;
4642 case X86::VMOVUPSZ128rmk: Opc = X86::VBLENDMPSZ128rmk; break;
4643 case X86::VMOVUPSZ256rmk: Opc = X86::VBLENDMPSZ256rmk; break;
4644 case X86::VMOVUPSZrmk: Opc = X86::VBLENDMPSZrmk; break;
4645 case X86::VMOVDQA32Z128rmk: Opc = X86::VPBLENDMDZ128rmk; break;
4646 case X86::VMOVDQA32Z256rmk: Opc = X86::VPBLENDMDZ256rmk; break;
4647 case X86::VMOVDQA32Zrmk: Opc = X86::VPBLENDMDZrmk; break;
4648 case X86::VMOVDQA64Z128rmk: Opc = X86::VPBLENDMQZ128rmk; break;
4649 case X86::VMOVDQA64Z256rmk: Opc = X86::VPBLENDMQZ256rmk; break;
4650 case X86::VMOVDQA64Zrmk: Opc = X86::VPBLENDMQZrmk; break;
4651 case X86::VMOVAPDZ128rmk: Opc = X86::VBLENDMPDZ128rmk; break;
4652 case X86::VMOVAPDZ256rmk: Opc = X86::VBLENDMPDZ256rmk; break;
4653 case X86::VMOVAPDZrmk: Opc = X86::VBLENDMPDZrmk; break;
4654 case X86::VMOVAPSZ128rmk: Opc = X86::VBLENDMPSZ128rmk; break;
4655 case X86::VMOVAPSZ256rmk: Opc = X86::VBLENDMPSZ256rmk; break;
4656 case X86::VMOVAPSZrmk: Opc = X86::VBLENDMPSZrmk; break;
4657 }
4658
4659 NewMI = BuildMI(MF, MI.getDebugLoc(), get(Opc))
4660 .add(Dest)
4661 .add(MI.getOperand(2))
4662 .add(Src)
4663 .add(MI.getOperand(3))
4664 .add(MI.getOperand(4))
4665 .add(MI.getOperand(5))
4666 .add(MI.getOperand(6))
4667 .add(MI.getOperand(7));
4668 break;
4669 }
4670 case X86::VMOVDQU8Z128rrk:
4671 case X86::VMOVDQU8Z256rrk:
4672 case X86::VMOVDQU8Zrrk:
4673 case X86::VMOVDQU16Z128rrk:
4674 case X86::VMOVDQU16Z256rrk:
4675 case X86::VMOVDQU16Zrrk:
4676 case X86::VMOVDQU32Z128rrk: case X86::VMOVDQA32Z128rrk:
4677 case X86::VMOVDQU32Z256rrk: case X86::VMOVDQA32Z256rrk:
4678 case X86::VMOVDQU32Zrrk: case X86::VMOVDQA32Zrrk:
4679 case X86::VMOVDQU64Z128rrk: case X86::VMOVDQA64Z128rrk:
4680 case X86::VMOVDQU64Z256rrk: case X86::VMOVDQA64Z256rrk:
4681 case X86::VMOVDQU64Zrrk: case X86::VMOVDQA64Zrrk:
4682 case X86::VMOVUPDZ128rrk: case X86::VMOVAPDZ128rrk:
4683 case X86::VMOVUPDZ256rrk: case X86::VMOVAPDZ256rrk:
4684 case X86::VMOVUPDZrrk: case X86::VMOVAPDZrrk:
4685 case X86::VMOVUPSZ128rrk: case X86::VMOVAPSZ128rrk:
4686 case X86::VMOVUPSZ256rrk: case X86::VMOVAPSZ256rrk:
4687 case X86::VMOVUPSZrrk: case X86::VMOVAPSZrrk: {
4688 unsigned Opc;
4689 switch (MIOpc) {
4690 default: llvm_unreachable("Unreachable!")::llvm::llvm_unreachable_internal("Unreachable!", "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/Target/X86/X86InstrInfo.cpp"
, 4690)
;
4691 case X86::VMOVDQU8Z128rrk: Opc = X86::VPBLENDMBZ128rrk; break;
4692 case X86::VMOVDQU8Z256rrk: Opc = X86::VPBLENDMBZ256rrk; break;
4693 case X86::VMOVDQU8Zrrk: Opc = X86::VPBLENDMBZrrk; break;
4694 case X86::VMOVDQU16Z128rrk: Opc = X86::VPBLENDMWZ128rrk; break;
4695 case X86::VMOVDQU16Z256rrk: Opc = X86::VPBLENDMWZ256rrk; break;
4696 case X86::VMOVDQU16Zrrk: Opc = X86::VPBLENDMWZrrk; break;
4697 case X86::VMOVDQU32Z128rrk: Opc = X86::VPBLENDMDZ128rrk; break;
4698 case X86::VMOVDQU32Z256rrk: Opc = X86::VPBLENDMDZ256rrk; break;
4699 case X86::VMOVDQU32Zrrk: Opc = X86::VPBLENDMDZrrk; break;
4700 case X86::VMOVDQU64Z128rrk: Opc = X86::VPBLENDMQZ128rrk; break;
4701 case X86::VMOVDQU64Z256rrk: Opc = X86::VPBLENDMQZ256rrk; break;
4702 case X86::VMOVDQU64Zrrk: Opc = X86::VPBLENDMQZrrk; break;
4703 case X86::VMOVUPDZ128rrk: Opc = X86::VBLENDMPDZ128rrk; break;
4704 case X86::VMOVUPDZ256rrk: Opc = X86::VBLENDMPDZ256rrk; break;
4705 case X86::VMOVUPDZrrk: Opc = X86::VBLENDMPDZrrk; break;
4706 case X86::VMOVUPSZ128rrk: Opc = X86::VBLENDMPSZ128rrk; break;
4707 case X86::VMOVUPSZ256rrk: Opc = X86::VBLENDMPSZ256rrk; break;
4708 case X86::VMOVUPSZrrk: Opc = X86::VBLENDMPSZrrk; break;
4709 case X86::VMOVDQA32Z128rrk: Opc = X86::VPBLENDMDZ128rrk; break;
4710 case X86::VMOVDQA32Z256rrk: Opc = X86::VPBLENDMDZ256rrk; break;
4711 case X86::VMOVDQA32Zrrk: Opc = X86::VPBLENDMDZrrk; break;
4712 case X86::VMOVDQA64Z128rrk: Opc = X86::VPBLENDMQZ128rrk; break;
4713 case X86::VMOVDQA64Z256rrk: Opc = X86::VPBLENDMQZ256rrk; break;
4714 case X86::VMOVDQA64Zrrk: Opc = X86::VPBLENDMQZrrk; break;
4715 case X86::VMOVAPDZ128rrk: Opc = X86::VBLENDMPDZ128rrk; break;
4716 case X86::VMOVAPDZ256rrk: Opc = X86::VBLENDMPDZ256rrk; break;
4717 case X86::VMOVAPDZrrk: Opc = X86::VBLENDMPDZrrk; break;
4718 case X86::VMOVAPSZ128rrk: Opc = X86::VBLENDMPSZ128rrk; break;
4719 case X86::VMOVAPSZ256rrk: Opc = X86::VBLENDMPSZ256rrk; break;
4720 case X86::VMOVAPSZrrk: Opc = X86::VBLENDMPSZrrk; break;
4721 }
4722
4723 NewMI = BuildMI(MF, MI.getDebugLoc(), get(Opc))
4724 .add(Dest)
4725 .add(MI.getOperand(2))
4726 .add(Src)
4727 .add(MI.getOperand(3));
4728 break;
4729 }
4730 }
4731
4732 if (!NewMI) return nullptr;
4733
4734 if (LV) { // Update live variables
4735 if (Src.isKill())
4736 LV->replaceKillInstruction(Src.getReg(), MI, *NewMI);
4737 if (Dest.isDead())
4738 LV->replaceKillInstruction(Dest.getReg(), MI, *NewMI);
4739 }
4740
4741 MFI->insert(MI.getIterator(), NewMI); // Insert the new inst
4742 return NewMI;
4743}
4744
4745/// This determines which of three possible cases of a three source commute
4746/// the source indexes correspond to taking into account any mask operands.
4747/// All prevents commuting a passthru operand. Returns -1 if the commute isn't
4748/// possible.
4749/// Case 0 - Possible to commute the first and second operands.
4750/// Case 1 - Possible to commute the first and third operands.
4751/// Case 2 - Possible to commute the second and third operands.
4752static int getThreeSrcCommuteCase(uint64_t TSFlags, unsigned SrcOpIdx1,
4753 unsigned SrcOpIdx2) {
4754 // Put the lowest index to SrcOpIdx1 to simplify the checks below.
4755 if (SrcOpIdx1 > SrcOpIdx2)
4756 std::swap(SrcOpIdx1, SrcOpIdx2);
4757
4758 unsigned Op1 = 1, Op2 = 2, Op3 = 3;
4759 if (X86II::isKMasked(TSFlags)) {
4760 // The k-mask operand cannot be commuted.
4761 if (SrcOpIdx1 == 2)
4762 return -1;
4763
4764 // For k-zero-masked operations it is Ok to commute the first vector
4765 // operand.
4766 // For regular k-masked operations a conservative choice is done as the
4767 // elements of the first vector operand, for which the corresponding bit
4768 // in the k-mask operand is set to 0, are copied to the result of the
4769 // instruction.
4770 // TODO/FIXME: The commute still may be legal if it is known that the
4771 // k-mask operand is set to either all ones or all zeroes.
4772 // It is also Ok to commute the 1st operand if all users of MI use only
4773 // the elements enabled by the k-mask operand. For example,
4774 // v4 = VFMADD213PSZrk v1, k, v2, v3; // v1[i] = k[i] ? v2[i]*v1[i]+v3[i]
4775 // : v1[i];
4776 // VMOVAPSZmrk <mem_addr>, k, v4; // this is the ONLY user of v4 ->
4777 // // Ok, to commute v1 in FMADD213PSZrk.
4778 if (X86II::isKMergeMasked(TSFlags) && SrcOpIdx1 == Op1)
4779 return -1;
4780 Op2++;
4781 Op3++;
4782 }
4783
4784 if (SrcOpIdx1 == Op1 && SrcOpIdx2 == Op2)
4785 return 0;
4786 if (SrcOpIdx1 == Op1 && SrcOpIdx2 == Op3)
4787 return 1;
4788 if (SrcOpIdx1 == Op2 && SrcOpIdx2 == Op3)
4789 return 2;
4790 return -1;
4791}
4792
4793unsigned X86InstrInfo::getFMA3OpcodeToCommuteOperands(
4794 const MachineInstr &MI, unsigned SrcOpIdx1, unsigned SrcOpIdx2,
4795 const X86InstrFMA3Group &FMA3Group) const {
4796
4797 unsigned Opc = MI.getOpcode();
4798
4799 // Put the lowest index to SrcOpIdx1 to simplify the checks below.
4800 if (SrcOpIdx1 > SrcOpIdx2)
4801 std::swap(SrcOpIdx1, SrcOpIdx2);
4802
4803 // TODO: Commuting the 1st operand of FMA*_Int requires some additional
4804 // analysis. The commute optimization is legal only if all users of FMA*_Int
4805 // use only the lowest element of the FMA*_Int instruction. Such analysis are
4806 // not implemented yet. So, just return 0 in that case.
4807 // When such analysis are available this place will be the right place for
4808 // calling it.
4809 if (FMA3Group.isIntrinsic() && SrcOpIdx1 == 1)
4810 return 0;
4811
4812 // Determine which case this commute is or if it can't be done.
4813 int Case = getThreeSrcCommuteCase(MI.getDesc().TSFlags, SrcOpIdx1, SrcOpIdx2);
4814 if (Case < 0)
4815 return 0;
4816
4817 // Define the FMA forms mapping array that helps to map input FMA form
4818 // to output FMA form to preserve the operation semantics after
4819 // commuting the operands.
4820 const unsigned Form132Index = 0;
4821 const unsigned Form213Index = 1;
4822 const unsigned Form231Index = 2;
4823 static const unsigned FormMapping[][3] = {
4824 // 0: SrcOpIdx1 == 1 && SrcOpIdx2 == 2;
4825 // FMA132 A, C, b; ==> FMA231 C, A, b;
4826 // FMA213 B, A, c; ==> FMA213 A, B, c;
4827 // FMA231 C, A, b; ==> FMA132 A, C, b;
4828 { Form231Index, Form213Index, Form132Index },
4829 // 1: SrcOpIdx1 == 1 && SrcOpIdx2 == 3;
4830 // FMA132 A, c, B; ==> FMA132 B, c, A;
4831 // FMA213 B, a, C; ==> FMA231 C, a, B;
4832 // FMA231 C, a, B; ==> FMA213 B, a, C;
4833 { Form132Index, Form231Index, Form213Index },
4834 // 2: SrcOpIdx1 == 2 && SrcOpIdx2 == 3;
4835 // FMA132 a, C, B; ==> FMA213 a, B, C;
4836 // FMA213 b, A, C; ==> FMA132 b, C, A;
4837 // FMA231 c, A, B; ==> FMA231 c, B, A;
4838 { Form213Index, Form132Index, Form231Index }
4839 };
4840
4841 unsigned FMAForms[3];
4842 if (FMA3Group.isRegOpcodeFromGroup(Opc)) {
4843 FMAForms[0] = FMA3Group.getReg132Opcode();
4844 FMAForms[1] = FMA3Group.getReg213Opcode();
4845 FMAForms[2] = FMA3Group.getReg231Opcode();
4846 } else {
4847 FMAForms[0] = FMA3Group.getMem132Opcode();
4848 FMAForms[1] = FMA3Group.getMem213Opcode();
4849 FMAForms[2] = FMA3Group.getMem231Opcode();
4850 }
4851 unsigned FormIndex;
4852 for (FormIndex = 0; FormIndex < 3; FormIndex++)
4853 if (Opc == FMAForms[FormIndex])
4854 break;
4855
4856 // Everything is ready, just adjust the FMA opcode and return it.
4857 FormIndex = FormMapping[Case][FormIndex];
4858 return FMAForms[FormIndex];
4859}
4860
4861static bool commuteVPTERNLOG(MachineInstr &MI, unsigned SrcOpIdx1,
4862 unsigned SrcOpIdx2) {
4863 uint64_t TSFlags = MI.getDesc().TSFlags;
4864
4865 // Determine which case this commute is or if it can't be done.
4866 int Case = getThreeSrcCommuteCase(TSFlags, SrcOpIdx1, SrcOpIdx2);
4867 if (Case < 0)
4868 return false;
4869
4870 // For each case we need to swap two pairs of bits in the final immediate.
4871 static const uint8_t SwapMasks[3][4] = {
4872 { 0x04, 0x10, 0x08, 0x20 }, // Swap bits 2/4 and 3/5.
4873 { 0x02, 0x10, 0x08, 0x40 }, // Swap bits 1/4 and 3/6.
4874 { 0x02, 0x04, 0x20, 0x40 }, // Swap bits 1/2 and 5/6.
4875 };
4876
4877 uint8_t Imm = MI.getOperand(MI.getNumOperands()-1).getImm();
4878 // Clear out the bits we are swapping.
4879 uint8_t NewImm = Imm & ~(SwapMasks[Case][0] | SwapMasks[Case][1] |
4880 SwapMasks[Case][2] | SwapMasks[Case][3]);
4881 // If the immediate had a bit of the pair set, then set the opposite bit.
4882 if (Imm & SwapMasks[Case][0]) NewImm |= SwapMasks[Case][1];
4883 if (Imm & SwapMasks[Case][1]) NewImm |= SwapMasks[Case][0];
4884 if (Imm & SwapMasks[Case][2]) NewImm |= SwapMasks[Case][3];
4885 if (Imm & SwapMasks[Case][3]) NewImm |= SwapMasks[Case][2];
4886 MI.getOperand(MI.getNumOperands()-1).setImm(NewImm);
4887
4888 return true;
4889}
4890
4891// Returns true if this is a VPERMI2 or VPERMT2 instrution that can be
4892// commuted.
4893static bool isCommutableVPERMV3Instruction(unsigned Opcode) {
4894#define VPERM_CASES(Suffix) \
4895 case X86::VPERMI2##Suffix##128rr: case X86::VPERMT2##Suffix##128rr: \
4896 case X86::VPERMI2##Suffix##256rr: case X86::VPERMT2##Suffix##256rr: \
4897 case X86::VPERMI2##Suffix##rr: case X86::VPERMT2##Suffix##rr: \
4898 case X86::VPERMI2##Suffix##128rm: case X86::VPERMT2##Suffix##128rm: \
4899 case X86::VPERMI2##Suffix##256rm: case X86::VPERMT2##Suffix##256rm: \
4900 case X86::VPERMI2##Suffix##rm: case X86::VPERMT2##Suffix##rm: \
4901 case X86::VPERMI2##Suffix##128rrkz: case X86::VPERMT2##Suffix##128rrkz: \
4902 case X86::VPERMI2##Suffix##256rrkz: case X86::VPERMT2##Suffix##256rrkz: \
4903 case X86::VPERMI2##Suffix##rrkz: case X86::VPERMT2##Suffix##rrkz: \
4904 case X86::VPERMI2##Suffix##128rmkz: case X86::VPERMT2##Suffix##128rmkz: \
4905 case X86::VPERMI2##Suffix##256rmkz: case X86::VPERMT2##Suffix##256rmkz: \
4906 case X86::VPERMI2##Suffix##rmkz: case X86::VPERMT2##Suffix##rmkz:
4907
4908#define VPERM_CASES_BROADCAST(Suffix) \
4909 VPERM_CASES(Suffix) \
4910 case X86::VPERMI2##Suffix##128rmb: case X86::VPERMT2##Suffix##128rmb: \
4911 case X86::VPERMI2##Suffix##256rmb: case X86::VPERMT2##Suffix##256rmb: \
4912 case X86::VPERMI2##Suffix##rmb: case X86::VPERMT2##Suffix##rmb: \
4913 case X86::VPERMI2##Suffix##128rmbkz: case X86::VPERMT2##Suffix##128rmbkz: \
4914 case X86::VPERMI2##Suffix##256rmbkz: case X86::VPERMT2##Suffix##256rmbkz: \
4915 case X86::VPERMI2##Suffix##rmbkz: case X86::VPERMT2##Suffix##rmbkz:
4916
4917 switch (Opcode) {
4918 default: return false;
4919 VPERM_CASES(B)
4920 VPERM_CASES_BROADCAST(D)
4921 VPERM_CASES_BROADCAST(PD)
4922 VPERM_CASES_BROADCAST(PS)
4923 VPERM_CASES_BROADCAST(Q)
4924 VPERM_CASES(W)
4925 return true;
4926 }
4927#undef VPERM_CASES_BROADCAST
4928#undef VPERM_CASES
4929}
4930
4931// Returns commuted opcode for VPERMI2 and VPERMT2 instructions by switching
4932// from the I opcod to the T opcode and vice versa.
4933static unsigned getCommutedVPERMV3Opcode(unsigned Opcode) {
4934#define VPERM_CASES(Orig, New) \
4935 case X86::Orig##128rr: return X86::New##128rr; \
4936 case X86::Orig##128rrkz: return X86::New##128rrkz; \
4937 case X86::Orig##128rm: return X86::New##128rm; \
4938 case X86::Orig##128rmkz: return X86::New##128rmkz; \
4939 case X86::Orig##256rr: return X86::New##256rr; \
4940 case X86::Orig##256rrkz: return X86::New##256rrkz; \
4941 case X86::Orig##256rm: return X86::New##256rm; \
4942 case X86::Orig##256rmkz: return X86::New##256rmkz; \
4943 case X86::Orig##rr: return X86::New##rr; \
4944 case X86::Orig##rrkz: return X86::New##rrkz; \
4945 case X86::Orig##rm: return X86::New##rm; \
4946 case X86::Orig##rmkz: return X86::New##rmkz;
4947
4948#define VPERM_CASES_BROADCAST(Orig, New) \
4949 VPERM_CASES(Orig, New) \
4950 case X86::Orig##128rmb: return X86::New##128rmb; \
4951 case X86::Orig##128rmbkz: return X86::New##128rmbkz; \
4952 case X86::Orig##256rmb: return X86::New##256rmb; \
4953 case X86::Orig##256rmbkz: return X86::New##256rmbkz; \
4954 case X86::Orig##rmb: return X86::New##rmb; \
4955 case X86::Orig##rmbkz: return X86::New##rmbkz;
4956
4957 switch (Opcode) {
4958 VPERM_CASES(VPERMI2B, VPERMT2B)
4959 VPERM_CASES_BROADCAST(VPERMI2D, VPERMT2D)
4960 VPERM_CASES_BROADCAST(VPERMI2PD, VPERMT2PD)
4961 VPERM_CASES_BROADCAST(VPERMI2PS, VPERMT2PS)
4962 VPERM_CASES_BROADCAST(VPERMI2Q, VPERMT2Q)
4963 VPERM_CASES(VPERMI2W, VPERMT2W)
4964 VPERM_CASES(VPERMT2B, VPERMI2B)
4965 VPERM_CASES_BROADCAST(VPERMT2D, VPERMI2D)
4966 VPERM_CASES_BROADCAST(VPERMT2PD, VPERMI2PD)
4967 VPERM_CASES_BROADCAST(VPERMT2PS, VPERMI2PS)
4968 VPERM_CASES_BROADCAST(VPERMT2Q, VPERMI2Q)
4969 VPERM_CASES(VPERMT2W, VPERMI2W)
4970 }
4971
4972 llvm_unreachable("Unreachable!")::llvm::llvm_unreachable_internal("Unreachable!", "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/Target/X86/X86InstrInfo.cpp"
, 4972)
;
4973#undef VPERM_CASES_BROADCAST
4974#undef VPERM_CASES
4975}
4976
4977MachineInstr *X86InstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI,
4978 unsigned OpIdx1,
4979 unsigned OpIdx2) const {
4980 auto cloneIfNew = [NewMI](MachineInstr &MI) -> MachineInstr & {
4981 if (NewMI)
4982 return *MI.getParent()->getParent()->CloneMachineInstr(&MI);
4983 return MI;
4984 };
4985
4986 switch (MI.getOpcode()) {
4987 case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
4988 case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
4989 case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
4990 case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
4991 case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
4992 case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
4993 unsigned Opc;
4994 unsigned Size;
4995 switch (MI.getOpcode()) {
4996 default: llvm_unreachable("Unreachable!")::llvm::llvm_unreachable_internal("Unreachable!", "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/Target/X86/X86InstrInfo.cpp"
, 4996)
;
4997 case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
4998 case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
4999 case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
5000 case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
5001 case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
5002 case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
5003 }
5004 unsigned Amt = MI.getOperand(3).getImm();
5005 auto &WorkingMI = cloneIfNew(MI);
5006 WorkingMI.setDesc(get(Opc));
5007 WorkingMI.getOperand(3).setImm(Size - Amt);
5008 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
5009 OpIdx1, OpIdx2);
5010 }
5011 case X86::PFSUBrr:
5012 case X86::PFSUBRrr: {
5013 // PFSUB x, y: x = x - y
5014 // PFSUBR x, y: x = y - x
5015 unsigned Opc =
5016 (X86::PFSUBRrr == MI.getOpcode() ? X86::PFSUBrr : X86::PFSUBRrr);
5017 auto &WorkingMI = cloneIfNew(MI);
5018 WorkingMI.setDesc(get(Opc));
5019 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
5020 OpIdx1, OpIdx2);
5021 break;
5022 }
5023 case X86::BLENDPDrri:
5024 case X86::BLENDPSrri:
5025 case X86::PBLENDWrri:
5026 case X86::VBLENDPDrri:
5027 case X86::VBLENDPSrri:
5028 case X86::VBLENDPDYrri:
5029 case X86::VBLENDPSYrri:
5030 case X86::VPBLENDDrri:
5031 case X86::VPBLENDWrri:
5032 case X86::VPBLENDDYrri:
5033 case X86::VPBLENDWYrri:{
5034 unsigned Mask;
5035 switch (MI.getOpcode()) {
5036 default: llvm_unreachable("Unreachable!")::llvm::llvm_unreachable_internal("Unreachable!", "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/Target/X86/X86InstrInfo.cpp"
, 5036)
;
5037 case X86::BLENDPDrri: Mask = 0x03; break;
5038 case X86::BLENDPSrri: Mask = 0x0F; break;
5039 case X86::PBLENDWrri: Mask = 0xFF; break;
5040 case X86::VBLENDPDrri: Mask = 0x03; break;
5041 case X86::VBLENDPSrri: Mask = 0x0F; break;
5042 case X86::VBLENDPDYrri: Mask = 0x0F; break;
5043 case X86::VBLENDPSYrri: Mask = 0xFF; break;
5044 case X86::VPBLENDDrri: Mask = 0x0F; break;
5045 case X86::VPBLENDWrri: Mask = 0xFF; break;
5046 case X86::VPBLENDDYrri: Mask = 0xFF; break;
5047 case X86::VPBLENDWYrri: Mask = 0xFF; break;
5048 }
5049 // Only the least significant bits of Imm are used.
5050 unsigned Imm = MI.getOperand(3).getImm() & Mask;
5051 auto &WorkingMI = cloneIfNew(MI);
5052 WorkingMI.getOperand(3).setImm(Mask ^ Imm);
5053 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
5054 OpIdx1, OpIdx2);
5055 }
5056 case X86::MOVSDrr:
5057 case X86::MOVSSrr:
5058 case X86::VMOVSDrr:
5059 case X86::VMOVSSrr:{
5060 // On SSE41 or later we can commute a MOVSS/MOVSD to a BLENDPS/BLENDPD.
5061 if (!Subtarget.hasSSE41())
5062 return nullptr;
5063
5064 unsigned Mask, Opc;
5065 switch (MI.getOpcode()) {
5066 default: llvm_unreachable("Unreachable!")::llvm::llvm_unreachable_internal("Unreachable!", "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/Target/X86/X86InstrInfo.cpp"
, 5066)
;
5067 case X86::MOVSDrr: Opc = X86::BLENDPDrri; Mask = 0x02; break;
5068 case X86::MOVSSrr: Opc = X86::BLENDPSrri; Mask = 0x0E; break;
5069 case X86::VMOVSDrr: Opc = X86::VBLENDPDrri; Mask = 0x02; break;
5070 case X86::VMOVSSrr: Opc = X86::VBLENDPSrri; Mask = 0x0E; break;
5071 }
5072
5073 // MOVSD/MOVSS's 2nd operand is a FR64/FR32 reg class - we need to copy
5074 // this over to a VR128 class like the 1st operand to use a BLENDPD/BLENDPS.
5075 auto &MRI = MI.getParent()->getParent()->getRegInfo();
5076 auto VR128RC = MRI.getRegClass(MI.getOperand(1).getReg());
5077 unsigned VR128 = MRI.createVirtualRegister(VR128RC);
5078 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(TargetOpcode::COPY),
5079 VR128)
5080 .addReg(MI.getOperand(2).getReg());
5081
5082 auto &WorkingMI = cloneIfNew(MI);
5083 WorkingMI.setDesc(get(Opc));
5084 WorkingMI.getOperand(2).setReg(VR128);
5085 WorkingMI.addOperand(MachineOperand::CreateImm(Mask));
5086 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
5087 OpIdx1, OpIdx2);
5088 }
5089 case X86::PCLMULQDQrr:
5090 case X86::VPCLMULQDQrr:{
5091 // SRC1 64bits = Imm[0] ? SRC1[127:64] : SRC1[63:0]
5092 // SRC2 64bits = Imm[4] ? SRC2[127:64] : SRC2[63:0]
5093 unsigned Imm = MI.getOperand(3).getImm();
5094 unsigned Src1Hi = Imm & 0x01;
5095 unsigned Src2Hi = Imm & 0x10;
5096 auto &WorkingMI = cloneIfNew(MI);
5097 WorkingMI.getOperand(3).setImm((Src1Hi << 4) | (Src2Hi >> 4));
5098 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
5099 OpIdx1, OpIdx2);
5100 }
5101 case X86::CMPSDrr:
5102 case X86::CMPSSrr:
5103 case X86::CMPPDrri:
5104 case X86::CMPPSrri:
5105 case X86::VCMPSDrr:
5106 case X86::VCMPSSrr:
5107 case X86::VCMPPDrri:
5108 case X86::VCMPPSrri:
5109 case X86::VCMPPDYrri:
5110 case X86::VCMPPSYrri:
5111 case X86::VCMPSDZrr:
5112 case X86::VCMPSSZrr:
5113 case X86::VCMPPDZrri:
5114 case X86::VCMPPSZrri:
5115 case X86::VCMPPDZ128rri:
5116 case X86::VCMPPSZ128rri:
5117 case X86::VCMPPDZ256rri:
5118 case X86::VCMPPSZ256rri: {
5119 // Float comparison can be safely commuted for
5120 // Ordered/Unordered/Equal/NotEqual tests
5121 unsigned Imm = MI.getOperand(3).getImm() & 0x7;
5122 switch (Imm) {
5123 case 0x00: // EQUAL
5124 case 0x03: // UNORDERED
5125 case 0x04: // NOT EQUAL
5126 case 0x07: // ORDERED
5127 return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
5128 default:
5129 return nullptr;
5130 }
5131 }
5132 case X86::VPCMPBZ128rri: case X86::VPCMPUBZ128rri:
5133 case X86::VPCMPBZ256rri: case X86::VPCMPUBZ256rri:
5134 case X86::VPCMPBZrri: case X86::VPCMPUBZrri:
5135 case X86::VPCMPDZ128rri: case X86::VPCMPUDZ128rri:
5136 case X86::VPCMPDZ256rri: case X86::VPCMPUDZ256rri:
5137 case X86::VPCMPDZrri: case X86::VPCMPUDZrri:
5138 case X86::VPCMPQZ128rri: case X86::VPCMPUQZ128rri:
5139 case X86::VPCMPQZ256rri: case X86::VPCMPUQZ256rri:
5140 case X86::VPCMPQZrri: case X86::VPCMPUQZrri:
5141 case X86::VPCMPWZ128rri: case X86::VPCMPUWZ128rri:
5142 case X86::VPCMPWZ256rri: case X86::VPCMPUWZ256rri:
5143 case X86::VPCMPWZrri: case X86::VPCMPUWZrri: {
5144 // Flip comparison mode immediate (if necessary).
5145 unsigned Imm = MI.getOperand(3).getImm() & 0x7;
5146 switch (Imm) {
5147 default: llvm_unreachable("Unreachable!")::llvm::llvm_unreachable_internal("Unreachable!", "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/Target/X86/X86InstrInfo.cpp"
, 5147)
;
5148 case 0x01: Imm = 0x06; break; // LT -> NLE
5149 case 0x02: Imm = 0x05; break; // LE -> NLT
5150 case 0x05: Imm = 0x02; break; // NLT -> LE
5151 case 0x06: Imm = 0x01; break; // NLE -> LT
5152 case 0x00: // EQ
5153 case 0x03: // FALSE
5154 case 0x04: // NE
5155 case 0x07: // TRUE
5156 break;
5157 }
5158 auto &WorkingMI = cloneIfNew(MI);
5159 WorkingMI.getOperand(3).setImm(Imm);
5160 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
5161 OpIdx1, OpIdx2);
5162 }
5163 case X86::VPCOMBri: case X86::VPCOMUBri:
5164 case X86::VPCOMDri: case X86::VPCOMUDri:
5165 case X86::VPCOMQri: case X86::VPCOMUQri:
5166 case X86::VPCOMWri: case X86::VPCOMUWri: {
5167 // Flip comparison mode immediate (if necessary).
5168 unsigned Imm = MI.getOperand(3).getImm() & 0x7;
5169 switch (Imm) {
5170 default: llvm_unreachable("Unreachable!")::llvm::llvm_unreachable_internal("Unreachable!", "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/Target/X86/X86InstrInfo.cpp"
, 5170)
;
5171 case 0x00: Imm = 0x02; break; // LT -> GT
5172 case 0x01: Imm = 0x03; break; // LE -> GE
5173 case 0x02: Imm = 0x00; break; // GT -> LT
5174 case 0x03: Imm = 0x01; break; // GE -> LE
5175 case 0x04: // EQ
5176 case 0x05: // NE
5177 case 0x06: // FALSE
5178 case 0x07: // TRUE
5179 break;
5180 }
5181 auto &WorkingMI = cloneIfNew(MI);
5182 WorkingMI.getOperand(3).setImm(Imm);
5183 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
5184 OpIdx1, OpIdx2);
5185 }
5186 case X86::VPERM2F128rr:
5187 case X86::VPERM2I128rr: {
5188 // Flip permute source immediate.
5189 // Imm & 0x02: lo = if set, select Op1.lo/hi else Op0.lo/hi.
5190 // Imm & 0x20: hi = if set, select Op1.lo/hi else Op0.lo/hi.
5191 unsigned Imm = MI.getOperand(3).getImm() & 0xFF;
5192 auto &WorkingMI = cloneIfNew(MI);
5193 WorkingMI.getOperand(3).setImm(Imm ^ 0x22);
5194 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
5195 OpIdx1, OpIdx2);
5196 }
5197 case X86::MOVHLPSrr:
5198 case X86::UNPCKHPDrr: {
5199 if (!Subtarget.hasSSE2())
5200 return nullptr;
5201
5202 unsigned Opc = MI.getOpcode();
5203 switch (Opc) {
5204 default: llvm_unreachable("Unreachable!")::llvm::llvm_unreachable_internal("Unreachable!", "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/Target/X86/X86InstrInfo.cpp"
, 5204)
;
5205 case X86::MOVHLPSrr: Opc = X86::UNPCKHPDrr; break;
5206 case X86::UNPCKHPDrr: Opc = X86::MOVHLPSrr; break;
5207 }
5208 auto &WorkingMI = cloneIfNew(MI);
5209 WorkingMI.setDesc(get(Opc));
5210 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
5211 OpIdx1, OpIdx2);
5212 }
5213 case X86::CMOVB16rr: case X86::CMOVB32rr: case X86::CMOVB64rr:
5214 case X86::CMOVAE16rr: case X86::CMOVAE32rr: case X86::CMOVAE64rr:
5215 case X86::CMOVE16rr: case X86::CMOVE32rr: case X86::CMOVE64rr:
5216 case X86::CMOVNE16rr: case X86::CMOVNE32rr: case X86::CMOVNE64rr:
5217 case X86::CMOVBE16rr: case X86::CMOVBE32rr: case X86::CMOVBE64rr:
5218 case X86::CMOVA16rr: case X86::CMOVA32rr: case X86::CMOVA64rr:
5219 case X86::CMOVL16rr: case X86::CMOVL32rr: case X86::CMOVL64rr:
5220 case X86::CMOVGE16rr: case X86::CMOVGE32rr: case X86::CMOVGE64rr:
5221 case X86::CMOVLE16rr: case X86::CMOVLE32rr: case X86::CMOVLE64rr:
5222 case X86::CMOVG16rr: case X86::CMOVG32rr: case X86::CMOVG64rr:
5223 case X86::CMOVS16rr: case X86::CMOVS32rr: case X86::CMOVS64rr:
5224 case X86::CMOVNS16rr: case X86::CMOVNS32rr: case X86::CMOVNS64rr:
5225 case X86::CMOVP16rr: case X86::CMOVP32rr: case X86::CMOVP64rr:
5226 case X86::CMOVNP16rr: case X86::CMOVNP32rr: case X86::CMOVNP64rr:
5227 case X86::CMOVO16rr: case X86::CMOVO32rr: case X86::CMOVO64rr:
5228 case X86::CMOVNO16rr: case X86::CMOVNO32rr: case X86::CMOVNO64rr: {
5229 unsigned Opc;
5230 switch (MI.getOpcode()) {
5231 default: llvm_unreachable("Unreachable!")::llvm::llvm_unreachable_internal("Unreachable!", "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/Target/X86/X86InstrInfo.cpp"
, 5231)
;
5232 case X86::CMOVB16rr: Opc = X86::CMOVAE16rr; break;
5233 case X86::CMOVB32rr: Opc = X86::CMOVAE32rr; break;
5234 case X86::CMOVB64rr: Opc = X86::CMOVAE64rr; break;
5235 case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
5236 case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
5237 case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
5238 case X86::CMOVE16rr: Opc = X86::CMOVNE16rr; break;
5239 case X86::CMOVE32rr: Opc = X86::CMOVNE32rr; break;
5240 case X86::CMOVE64rr: Opc = X86::CMOVNE64rr; break;
5241 case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
5242 case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
5243 case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
5244 case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
5245 case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
5246 case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
5247 case X86::CMOVA16rr: Opc = X86::CMOVBE16rr; break;
5248 case X86::CMOVA32rr: Opc = X86::CMOVBE32rr; break;
5249 case X86::CMOVA64rr: Opc = X86::CMOVBE64rr; break;
5250 case X86::CMOVL16rr: Opc = X86::CMOVGE16rr; break;
5251 case X86::CMOVL32rr: Opc = X86::CMOVGE32rr; break;
5252 case X86::CMOVL64rr: Opc = X86::CMOVGE64rr; break;
5253 case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
5254 case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
5255 case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
5256 case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
5257 case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
5258 case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
5259 case X86::CMOVG16rr: Opc = X86::CMOVLE16rr; break;
5260 case X86::CMOVG32rr: Opc = X86::CMOVLE32rr; break;
5261 case X86::CMOVG64rr: Opc = X86::CMOVLE64rr; break;
5262 case X86::CMOVS16rr: Opc = X86::CMOVNS16rr; break;
5263 case X86::CMOVS32rr: Opc = X86::CMOVNS32rr; break;
5264 case X86::CMOVS64rr: Opc = X86::CMOVNS64rr; break;
5265 case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
5266 case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
5267 case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
5268 case X86::CMOVP16rr: Opc = X86::CMOVNP16rr; break;
5269 case X86::CMOVP32rr: Opc = X86::CMOVNP32rr; break;
5270 case X86::CMOVP64rr: Opc = X86::CMOVNP64rr; break;
5271 case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
5272 case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
5273 case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
5274 case X86::CMOVO16rr: Opc = X86::CMOVNO16rr; break;
5275 case X86::CMOVO32rr: Opc = X86::CMOVNO32rr; break;
5276 case X86::CMOVO64rr: Opc = X86::CMOVNO64rr; break;
5277 case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break;
5278 case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break;
5279 case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break;
5280 }
5281 auto &WorkingMI = cloneIfNew(MI);
5282 WorkingMI.setDesc(get(Opc));
5283 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
5284 OpIdx1, OpIdx2);
5285 }
5286 case X86::VPTERNLOGDZrri: case X86::VPTERNLOGDZrmi:
5287 case X86::VPTERNLOGDZ128rri: case X86::VPTERNLOGDZ128rmi:
5288 case X86::VPTERNLOGDZ256rri: case X86::VPTERNLOGDZ256rmi:
5289 case X86::VPTERNLOGQZrri: case X86::VPTERNLOGQZrmi:
5290 case X86::VPTERNLOGQZ128rri: case X86::VPTERNLOGQZ128rmi:
5291 case X86::VPTERNLOGQZ256rri: case X86::VPTERNLOGQZ256rmi:
5292 case X86::VPTERNLOGDZrrik:
5293 case X86::VPTERNLOGDZ128rrik:
5294 case X86::VPTERNLOGDZ256rrik:
5295 case X86::VPTERNLOGQZrrik:
5296 case X86::VPTERNLOGQZ128rrik:
5297 case X86::VPTERNLOGQZ256rrik:
5298 case X86::VPTERNLOGDZrrikz: case X86::VPTERNLOGDZrmikz:
5299 case X86::VPTERNLOGDZ128rrikz: case X86::VPTERNLOGDZ128rmikz:
5300 case X86::VPTERNLOGDZ256rrikz: case X86::VPTERNLOGDZ256rmikz:
5301 case X86::VPTERNLOGQZrrikz: case X86::VPTERNLOGQZrmikz:
5302 case X86::VPTERNLOGQZ128rrikz: case X86::VPTERNLOGQZ128rmikz:
5303 case X86::VPTERNLOGQZ256rrikz: case X86::VPTERNLOGQZ256rmikz:
5304 case X86::VPTERNLOGDZ128rmbi:
5305 case X86::VPTERNLOGDZ256rmbi:
5306 case X86::VPTERNLOGDZrmbi:
5307 case X86::VPTERNLOGQZ128rmbi:
5308 case X86::VPTERNLOGQZ256rmbi:
5309 case X86::VPTERNLOGQZrmbi:
5310 case X86::VPTERNLOGDZ128rmbikz:
5311 case X86::VPTERNLOGDZ256rmbikz:
5312 case X86::VPTERNLOGDZrmbikz:
5313 case X86::VPTERNLOGQZ128rmbikz:
5314 case X86::VPTERNLOGQZ256rmbikz:
5315 case X86::VPTERNLOGQZrmbikz: {
5316 auto &WorkingMI = cloneIfNew(MI);
5317 if (!commuteVPTERNLOG(WorkingMI, OpIdx1, OpIdx2))
5318 return nullptr;
5319 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
5320 OpIdx1, OpIdx2);
5321 }
5322 default: {
5323 if (isCommutableVPERMV3Instruction(MI.getOpcode())) {
5324 unsigned Opc = getCommutedVPERMV3Opcode(MI.getOpcode());
5325 auto &WorkingMI = cloneIfNew(MI);
5326 WorkingMI.setDesc(get(Opc));
5327 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
5328 OpIdx1, OpIdx2);
5329 }
5330
5331 const X86InstrFMA3Group *FMA3Group =
5332 X86InstrFMA3Info::getFMA3Group(MI.getOpcode());
5333 if (FMA3Group) {
5334 unsigned Opc =
5335 getFMA3OpcodeToCommuteOperands(MI, OpIdx1, OpIdx2, *FMA3Group);
5336 if (Opc == 0)
5337 return nullptr;
5338 auto &WorkingMI = cloneIfNew(MI);
5339 WorkingMI.setDesc(get(Opc));
5340 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
5341 OpIdx1, OpIdx2);
5342 }
5343
5344 return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
5345 }
5346 }
5347}
5348
5349bool X86InstrInfo::findFMA3CommutedOpIndices(
5350 const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2,
5351 const X86InstrFMA3Group &FMA3Group) const {
5352
5353 if (!findThreeSrcCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2))
5354 return false;
5355
5356 // Check if we can adjust the opcode to preserve the semantics when
5357 // commute the register operands.
5358 return getFMA3OpcodeToCommuteOperands(MI, SrcOpIdx1, SrcOpIdx2, FMA3Group) != 0;
5359}
5360
5361bool X86InstrInfo::findThreeSrcCommutedOpIndices(const MachineInstr &MI,
5362 unsigned &SrcOpIdx1,
5363 unsigned &SrcOpIdx2) const {
5364 uint64_t TSFlags = MI.getDesc().TSFlags;
5365
5366 unsigned FirstCommutableVecOp = 1;
5367 unsigned LastCommutableVecOp = 3;
5368 unsigned KMaskOp = 0;
5369 if (X86II::isKMasked(TSFlags)) {
5370 // The k-mask operand has index = 2 for masked and zero-masked operations.
5371 KMaskOp = 2;
5372
5373 // The operand with index = 1 is used as a source for those elements for
5374 // which the corresponding bit in the k-mask is set to 0.
5375 if (X86II::isKMergeMasked(TSFlags))
5376 FirstCommutableVecOp = 3;
5377
5378 LastCommutableVecOp++;
5379 }
5380
5381 if (isMem(MI, LastCommutableVecOp))
5382 LastCommutableVecOp--;
5383
5384 // Only the first RegOpsNum operands are commutable.
5385 // Also, the value 'CommuteAnyOperandIndex' is valid here as it means
5386 // that the operand is not specified/fixed.
5387 if (SrcOpIdx1 != CommuteAnyOperandIndex &&
5388 (SrcOpIdx1 < FirstCommutableVecOp || SrcOpIdx1 > LastCommutableVecOp ||
5389 SrcOpIdx1 == KMaskOp))
5390 return false;
5391 if (SrcOpIdx2 != CommuteAnyOperandIndex &&
5392 (SrcOpIdx2 < FirstCommutableVecOp || SrcOpIdx2 > LastCommutableVecOp ||
5393 SrcOpIdx2 == KMaskOp))
5394 return false;
5395
5396 // Look for two different register operands assumed to be commutable
5397 // regardless of the FMA opcode. The FMA opcode is adjusted later.
5398 if (SrcOpIdx1 == CommuteAnyOperandIndex ||
5399 SrcOpIdx2 == CommuteAnyOperandIndex) {
5400 unsigned CommutableOpIdx1 = SrcOpIdx1;
Value stored to 'CommutableOpIdx1' during its initialization is never read
5401 unsigned CommutableOpIdx2 = SrcOpIdx2;
5402
5403 // At least one of operands to be commuted is not specified and
5404 // this method is free to choose appropriate commutable operands.
5405 if (SrcOpIdx1 == SrcOpIdx2)
5406 // Both of operands are not fixed. By default set one of commutable
5407 // operands to the last register operand of the instruction.
5408 CommutableOpIdx2 = LastCommutableVecOp;
5409 else if (SrcOpIdx2 == CommuteAnyOperandIndex)
5410 // Only one of operands is not fixed.
5411 CommutableOpIdx2 = SrcOpIdx1;
5412
5413 // CommutableOpIdx2 is well defined now. Let's choose another commutable
5414 // operand and assign its index to CommutableOpIdx1.
5415 unsigned Op2Reg = MI.getOperand(CommutableOpIdx2).getReg();
5416 for (CommutableOpIdx1 = LastCommutableVecOp;
5417 CommutableOpIdx1 >= FirstCommutableVecOp; CommutableOpIdx1--) {
5418 // Just ignore and skip the k-mask operand.
5419 if (CommutableOpIdx1 == KMaskOp)
5420 continue;
5421
5422 // The commuted operands must have different registers.
5423 // Otherwise, the commute transformation does not change anything and
5424 // is useless then.
5425 if (Op2Reg != MI.getOperand(CommutableOpIdx1).getReg())
5426 break;
5427 }
5428
5429 // No appropriate commutable operands were found.
5430 if (CommutableOpIdx1 < FirstCommutableVecOp)
5431 return false;
5432
5433 // Assign the found pair of commutable indices to SrcOpIdx1 and SrcOpidx2
5434 // to return those values.
5435 if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
5436 CommutableOpIdx1, CommutableOpIdx2))
5437 return false;
5438 }
5439
5440 return true;
5441}
5442
5443bool X86InstrInfo::findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1,
5444 unsigned &SrcOpIdx2) const {
5445 const MCInstrDesc &Desc = MI.getDesc();
5446 if (!Desc.isCommutable())
5447 return false;
5448
5449 switch (MI.getOpcode()) {
5450 case X86::CMPSDrr:
5451 case X86::CMPSSrr:
5452 case X86::CMPPDrri:
5453 case X86::CMPPSrri:
5454 case X86::VCMPSDrr:
5455 case X86::VCMPSSrr:
5456 case X86::VCMPPDrri:
5457 case X86::VCMPPSrri:
5458 case X86::VCMPPDYrri:
5459 case X86::VCMPPSYrri:
5460 case X86::VCMPSDZrr:
5461 case X86::VCMPSSZrr:
5462 case X86::VCMPPDZrri:
5463 case X86::VCMPPSZrri:
5464 case X86::VCMPPDZ128rri:
5465 case X86::VCMPPSZ128rri:
5466 case X86::VCMPPDZ256rri:
5467 case X86::VCMPPSZ256rri: {
5468 // Float comparison can be safely commuted for
5469 // Ordered/Unordered/Equal/NotEqual tests
5470 unsigned Imm = MI.getOperand(3).getImm() & 0x7;
5471 switch (Imm) {
5472 case 0x00: // EQUAL
5473 case 0x03: // UNORDERED
5474 case 0x04: // NOT EQUAL
5475 case 0x07: // ORDERED
5476 // The indices of the commutable operands are 1 and 2.
5477 // Assign them to the returned operand indices here.
5478 return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 1, 2);
5479 }
5480 return false;
5481 }
5482 case X86::MOVSDrr:
5483 case X86::MOVSSrr:
5484 case X86::VMOVSDrr:
5485 case X86::VMOVSSrr: {
5486 if (Subtarget.hasSSE41())
5487 return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
5488 return false;
5489 }
5490 case X86::VPTERNLOGDZrri: case X86::VPTERNLOGDZrmi:
5491 case X86::VPTERNLOGDZ128rri: case X86::VPTERNLOGDZ128rmi:
5492 case X86::VPTERNLOGDZ256rri: case X86::VPTERNLOGDZ256rmi:
5493 case X86::VPTERNLOGQZrri: case X86::VPTERNLOGQZrmi:
5494 case X86::VPTERNLOGQZ128rri: case X86::VPTERNLOGQZ128rmi:
5495 case X86::VPTERNLOGQZ256rri: case X86::VPTERNLOGQZ256rmi:
5496 case X86::VPTERNLOGDZrrik:
5497 case X86::VPTERNLOGDZ128rrik:
5498 case X86::VPTERNLOGDZ256rrik:
5499 case X86::VPTERNLOGQZrrik:
5500 case X86::VPTERNLOGQZ128rrik:
5501 case X86::VPTERNLOGQZ256rrik:
5502 case X86::VPTERNLOGDZrrikz: case X86::VPTERNLOGDZrmikz:
5503 case X86::VPTERNLOGDZ128rrikz: case X86::VPTERNLOGDZ128rmikz:
5504 case X86::VPTERNLOGDZ256rrikz: case X86::VPTERNLOGDZ256rmikz:
5505 case X86::VPTERNLOGQZrrikz: case X86::VPTERNLOGQZrmikz:
5506 case X86::VPTERNLOGQZ128rrikz: case X86::VPTERNLOGQZ128rmikz:
5507 case X86::VPTERNLOGQZ256rrikz: case X86::VPTERNLOGQZ256rmikz:
5508 case X86::VPTERNLOGDZ128rmbi:
5509 case X86::VPTERNLOGDZ256rmbi:
5510 case X86::VPTERNLOGDZrmbi:
5511 case X86::VPTERNLOGQZ128rmbi:
5512 case X86::VPTERNLOGQZ256rmbi:
5513 case X86::VPTERNLOGQZrmbi:
5514 case X86::VPTERNLOGDZ128rmbikz:
5515 case X86::VPTERNLOGDZ256rmbikz:
5516 case X86::VPTERNLOGDZrmbikz:
5517 case X86::VPTERNLOGQZ128rmbikz:
5518 case X86::VPTERNLOGQZ256rmbikz:
5519 case X86::VPTERNLOGQZrmbikz:
5520 return findThreeSrcCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
5521 default:
5522 const X86InstrFMA3Group *FMA3Group =
5523 X86InstrFMA3Info::getFMA3Group(MI.getOpcode());
5524 if (FMA3Group)
5525 return findFMA3CommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2, *FMA3Group);
5526
5527 // Handled masked instructions since we need to skip over the mask input
5528 // and the preserved input.
5529 if (Desc.TSFlags & X86II::EVEX_K) {
5530 // First assume that the first input is the mask operand and skip past it.
5531 unsigned CommutableOpIdx1 = Desc.getNumDefs() + 1;
5532 unsigned CommutableOpIdx2 = Desc.getNumDefs() + 2;
5533 // Check if the first input is tied. If there isn't one then we only
5534 // need to skip the mask operand which we did above.
5535 if ((MI.getDesc().getOperandConstraint(Desc.getNumDefs(),
5536 MCOI::TIED_TO) != -1)) {
5537 // If this is zero masking instruction with a tied operand, we need to
5538 // move the first index back to the first input since this must
5539 // be a 3 input instruction and we want the first two non-mask inputs.
5540 // Otherwise this is a 2 input instruction with a preserved input and
5541 // mask, so we need to move the indices to skip one more input.
5542 if (Desc.TSFlags & X86II::EVEX_Z)
5543 --CommutableOpIdx1;
5544 else {
5545 ++CommutableOpIdx1;
5546 ++CommutableOpIdx2;
5547 }
5548 }
5549
5550 if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
5551 CommutableOpIdx1, CommutableOpIdx2))
5552 return false;
5553
5554 if (!MI.getOperand(SrcOpIdx1).isReg() ||
5555 !MI.getOperand(SrcOpIdx2).isReg())
5556 // No idea.
5557 return false;
5558 return true;
5559 }
5560
5561 return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
5562 }
5563 return false;
5564}
5565
5566static X86::CondCode getCondFromBranchOpc(unsigned BrOpc) {
5567 switch (BrOpc) {
5568 default: return X86::COND_INVALID;
5569 case X86::JE_1: return X86::COND_E;
5570 case X86::JNE_1: return X86::COND_NE;
5571 case X86::JL_1: return X86::COND_L;
5572 case X86::JLE_1: return X86::COND_LE;
5573 case X86::JG_1: return X86::COND_G;
5574 case X86::JGE_1: return X86::COND_GE;
5575 case X86::JB_1: return X86::COND_B;
5576 case X86::JBE_1: return X86::COND_BE;
5577 case X86::JA_1: return X86::COND_A;
5578 case X86::JAE_1: return X86::COND_AE;
5579 case X86::JS_1: return X86::COND_S;
5580 case X86::JNS_1: return X86::COND_NS;
5581 case X86::JP_1: return X86::COND_P;
5582 case X86::JNP_1: return X86::COND_NP;
5583 case X86::JO_1: return X86::COND_O;
5584 case X86::JNO_1: return X86::COND_NO;
5585 }
5586}
5587
5588/// Return condition code of a SET opcode.
5589static X86::CondCode getCondFromSETOpc(unsigned Opc) {
5590 switch (Opc) {
5591 default: return X86::COND_INVALID;
5592 case X86::SETAr: case X86::SETAm: return X86::COND_A;
5593 case X86::SETAEr: case X86::SETAEm: return X86::COND_AE;
5594 case X86::SETBr: case X86::SETBm: return X86::COND_B;
5595 case X86::SETBEr: case X86::SETBEm: return X86::COND_BE;
5596 case X86::SETEr: case X86::SETEm: return X86::COND_E;
5597 case X86::SETGr: case X86::SETGm: return X86::COND_G;
5598 case X86::SETGEr: case X86::SETGEm: return X86::COND_GE;
5599 case X86::SETLr: case X86::SETLm: return X86::COND_L;
5600 case X86::SETLEr: case X86::SETLEm: return X86::COND_LE;
5601 case X86::SETNEr: case X86::SETNEm: return X86::COND_NE;
5602 case X86::SETNOr: case X86::SETNOm: return X86::COND_NO;
5603 case X86::SETNPr: case X86::SETNPm: return X86::COND_NP;
5604 case X86::SETNSr: case X86::SETNSm: return X86::COND_NS;
5605 case X86::SETOr: case X86::SETOm: return X86::COND_O;
5606 case X86::SETPr: case X86::SETPm: return X86::COND_P;
5607 case X86::SETSr: case X86::SETSm: return X86::COND_S;
5608 }
5609}
5610
5611/// Return condition code of a CMov opcode.
5612X86::CondCode X86::getCondFromCMovOpc(unsigned Opc) {
5613 switch (Opc) {
5614 default: return X86::COND_INVALID;
5615 case X86::CMOVA16rm: case X86::CMOVA16rr: case X86::CMOVA32rm:
5616 case X86::CMOVA32rr: case X86::CMOVA64rm: case X86::CMOVA64rr:
5617 return X86::COND_A;
5618 case X86::CMOVAE16rm: case X86::CMOVAE16rr: case X86::CMOVAE32rm:
5619 case X86::CMOVAE32rr: case X86::CMOVAE64rm: case X86::CMOVAE64rr:
5620 return X86::COND_AE;
5621 case X86::CMOVB16rm: case X86::CMOVB16rr: case X86::CMOVB32rm:
5622 case X86::CMOVB32rr: case X86::CMOVB64rm: case X86::CMOVB64rr:
5623 return X86::COND_B;
5624 case X86::CMOVBE16rm: case X86::CMOVBE16rr: case X86::CMOVBE32rm:
5625 case X86::CMOVBE32rr: case X86::CMOVBE64rm: case X86::CMOVBE64rr:
5626 return X86::COND_BE;
5627 case X86::CMOVE16rm: case X86::CMOVE16rr: case X86::CMOVE32rm:
5628 case X86::CMOVE32rr: case X86::CMOVE64rm: case X86::CMOVE64rr:
5629 return X86::COND_E;
5630 case X86::CMOVG16rm: case X86::CMOVG16rr: case X86::CMOVG32rm:
5631 case X86::CMOVG32rr: case X86::CMOVG64rm: case X86::CMOVG64rr:
5632 return X86::COND_G;
5633 case X86::CMOVGE16rm: case X86::CMOVGE16rr: case X86::CMOVGE32rm:
5634 case X86::CMOVGE32rr: case X86::CMOVGE64rm: case X86::CMOVGE64rr:
5635 return X86::COND_GE;
5636 case X86::CMOVL16rm: case X86::CMOVL16rr: case X86::CMOVL32rm:
5637 case X86::CMOVL32rr: case X86::CMOVL64rm: case X86::CMOVL64rr:
5638 return X86::COND_L;
5639 case X86::CMOVLE16rm: case X86::CMOVLE16rr: case X86::CMOVLE32rm:
5640 case X86::CMOVLE32rr: case X86::CMOVLE64rm: case X86::CMOVLE64rr:
5641 return X86::COND_LE;
5642 case X86::CMOVNE16rm: case X86::CMOVNE16rr: case X86::CMOVNE32rm:
5643 case X86::CMOVNE32rr: case X86::CMOVNE64rm: case X86::CMOVNE64rr:
5644 return X86::COND_NE;
5645 case X86::CMOVNO16rm: case X86::CMOVNO16rr: case X86::CMOVNO32rm:
5646 case X86::CMOVNO32rr: case X86::CMOVNO64rm: case X86::CMOVNO64rr:
5647 return X86::COND_NO;
5648 case X86::CMOVNP16rm: case X86::CMOVNP16rr: case X86::CMOVNP32rm:
5649 case X86::CMOVNP32rr: case X86::CMOVNP64rm: case X86::CMOVNP64rr:
5650 return X86::COND_NP;
5651 case X86::CMOVNS16rm: case X86::CMOVNS16rr: case X86::CMOVNS32rm:
5652 case X86::CMOVNS32rr: case X86::CMOVNS64rm: case X86::CMOVNS64rr:
5653 return X86::COND_NS;
5654 case X86::CMOVO16rm: case X86::CMOVO16rr: case X86::CMOVO32rm:
5655 case X86::CMOVO32rr: case X86::CMOVO64rm: case X86::CMOVO64rr:
5656 return X86::COND_O;
5657 case X86::CMOVP16rm: case X86::CMOVP16rr: case X86::CMOVP32rm:
5658 case X86::CMOVP32rr: case X86::CMOVP64rm: case X86::CMOVP64rr:
5659 return X86::COND_P;
5660 case X86::CMOVS16rm: case X86::CMOVS16rr: case X86::CMOVS32rm:
5661 case X86::CMOVS32rr: case X86::CMOVS64rm: case X86::CMOVS64rr:
5662 return X86::COND_S;
5663 }
5664}
5665
5666unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
5667 switch (CC) {
5668 default: llvm_unreachable("Illegal condition code!")::llvm::llvm_unreachable_internal("Illegal condition code!", "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/Target/X86/X86InstrInfo.cpp"
, 5668)
;
5669 case X86::COND_E: return X86::JE_1;
5670 case X86::COND_NE: return X86::JNE_1;
5671 case X86::COND_L: return X86::JL_1;
5672 case X86::COND_LE: return X86::JLE_1;
5673 case X86::COND_G: return X86::JG_1;
5674 case X86::COND_GE: return X86::JGE_1;
5675 case X86::COND_B: return X86::JB_1;
5676 case X86::COND_BE: return X86::JBE_1;
5677 case X86::COND_A: return X86::JA_1;
5678 case X86::COND_AE: return X86::JAE_1;
5679 case X86::COND_S: return X86::JS_1;
5680 case X86::COND_NS: return X86::JNS_1;
5681 case X86::COND_P: return X86::JP_1;
5682 case X86::COND_NP: return X86::JNP_1;
5683 case X86::COND_O: return X86::JO_1;
5684 case X86::COND_NO: return X86::JNO_1;
5685 }
5686}
5687
5688/// Return the inverse of the specified condition,
5689/// e.g. turning COND_E to COND_NE.
5690X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
5691 switch (CC) {
5692 default: llvm_unreachable("Illegal condition code!")::llvm::llvm_unreachable_internal("Illegal condition code!", "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/Target/X86/X86InstrInfo.cpp"
, 5692)
;
5693 case X86::COND_E: return X86::COND_NE;
5694 case X86::COND_NE: return X86::COND_E;
5695 case X86::COND_L: return X86::COND_GE;
5696 case X86::COND_LE: return X86::COND_G;
5697 case X86::COND_G: return X86::COND_LE;
5698 case X86::COND_GE: return X86::COND_L;
5699 case X86::COND_B: return X86::COND_AE;
5700 case X86::COND_BE: return X86::COND_A;
5701 case X86::COND_A: return X86::COND_BE;
5702 case X86::COND_AE: return X86::COND_B;
5703 case X86::COND_S: return X86::COND_NS;
5704 case X86::COND_NS: return X86::COND_S;
5705 case X86::COND_P: return X86::COND_NP;
5706 case X86::COND_NP: return X86::COND_P;
5707 case X86::COND_O: return X86::COND_NO;
5708 case X86::COND_NO: return X86::COND_O;
5709 case X86::COND_NE_OR_P: return X86::COND_E_AND_NP;
5710 case X86::COND_E_AND_NP: return X86::COND_NE_OR_P;
5711 }
5712}
5713
5714/// Assuming the flags are set by MI(a,b), return the condition code if we
5715/// modify the instructions such that flags are set by MI(b,a).
5716static X86::CondCode getSwappedCondition(X86::CondCode CC) {
5717 switch (CC) {
5718 default: return X86::COND_INVALID;
5719 case X86::COND_E: return X86::COND_E;
5720 case X86::COND_NE: return X86::COND_NE;
5721 case X86::COND_L: return X86::COND_G;
5722 case X86::COND_LE: return X86::COND_GE;
5723 case X86::COND_G: return X86::COND_L;
5724 case X86::COND_GE: return X86::COND_LE;
5725 case X86::COND_B: return X86::COND_A;
5726 case X86::COND_BE: return X86::COND_AE;
5727 case X86::COND_A: return X86::COND_B;
5728 case X86::COND_AE: return X86::COND_BE;
5729 }
5730}
5731
5732std::pair<X86::CondCode, bool>
5733X86::getX86ConditionCode(CmpInst::Predicate Predicate) {
5734 X86::CondCode CC = X86::COND_INVALID;
5735 bool NeedSwap = false;
5736 switch (Predicate) {
5737 default: break;
5738 // Floating-point Predicates
5739 case CmpInst::FCMP_UEQ: CC = X86::COND_E; break;
5740 case CmpInst::FCMP_OLT: NeedSwap = true; LLVM_FALLTHROUGH[[clang::fallthrough]];
5741 case CmpInst::FCMP_OGT: CC = X86::COND_A; break;
5742 case CmpInst::FCMP_OLE: NeedSwap = true; LLVM_FALLTHROUGH[[clang::fallthrough]];
5743 case CmpInst::FCMP_OGE: CC = X86::COND_AE; break;
5744 case CmpInst::FCMP_UGT: NeedSwap = true; LLVM_FALLTHROUGH[[clang::fallthrough]];
5745 case CmpInst::FCMP_ULT: CC = X86::COND_B; break;
5746 case CmpInst::FCMP_UGE: NeedSwap = true; LLVM_FALLTHROUGH[[clang::fallthrough]];
5747 case CmpInst::FCMP_ULE: CC = X86::COND_BE; break;
5748 case CmpInst::FCMP_ONE: CC = X86::COND_NE; break;
5749 case CmpInst::FCMP_UNO: CC = X86::COND_P; break;
5750 case CmpInst::FCMP_ORD: CC = X86::COND_NP; break;
5751 case CmpInst::FCMP_OEQ: LLVM_FALLTHROUGH[[clang::fallthrough]];
5752 case CmpInst::FCMP_UNE: CC = X86::COND_INVALID; break;
5753
5754 // Integer Predicates
5755 case CmpInst::ICMP_EQ: CC = X86::COND_E; break;
5756 case CmpInst::ICMP_NE: CC = X86::COND_NE; break;
5757 case CmpInst::ICMP_UGT: CC = X86::COND_A; break;
5758 case CmpInst::ICMP_UGE: CC = X86::COND_AE; break;
5759 case CmpInst::ICMP_ULT: CC = X86::COND_B; break;
5760 case CmpInst::ICMP_ULE: CC = X86::COND_BE; break;
5761 case CmpInst::ICMP_SGT: CC = X86::COND_G; break;
5762 case CmpInst::ICMP_SGE: CC = X86::COND_GE; break;
5763 case CmpInst::ICMP_SLT: CC = X86::COND_L; break;
5764 case CmpInst::ICMP_SLE: CC = X86::COND_LE; break;
5765 }
5766
5767 return std::make_pair(CC, NeedSwap);
5768}
5769
5770/// Return a set opcode for the given condition and
5771/// whether it has memory operand.
5772unsigned X86::getSETFromCond(CondCode CC, bool HasMemoryOperand) {
5773 static const uint16_t Opc[16][2] = {
5774 { X86::SETAr, X86::SETAm },
5775 { X86::SETAEr, X86::SETAEm },
5776 { X86::SETBr, X86::SETBm },
5777 { X86::SETBEr, X86::SETBEm },
5778 { X86::SETEr, X86::SETEm },
5779 { X86::SETGr, X86::SETGm },
5780 { X86::SETGEr, X86::SETGEm },
5781 { X86::SETLr, X86::SETLm },
5782 { X86::SETLEr, X86::SETLEm },
5783 { X86::SETNEr, X86::SETNEm },
5784 { X86::SETNOr, X86::SETNOm },
5785 { X86::SETNPr, X86::SETNPm },
5786 { X86::SETNSr, X86::SETNSm },
5787 { X86::SETOr, X86::SETOm },
5788 { X86::SETPr, X86::SETPm },
5789 { X86::SETSr, X86::SETSm }
5790 };
5791
5792 assert(CC <= LAST_VALID_COND && "Can only handle standard cond codes")((CC <= LAST_VALID_COND && "Can only handle standard cond codes"
) ? static_cast<void> (0) : __assert_fail ("CC <= LAST_VALID_COND && \"Can only handle standard cond codes\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/Target/X86/X86InstrInfo.cpp"
, 5792, __PRETTY_FUNCTION__))
;
5793 return Opc[CC][HasMemoryOperand ? 1 : 0];
5794}
5795
5796/// Return a cmov opcode for the given condition,
5797/// register size in bytes, and operand type.
5798unsigned X86::getCMovFromCond(CondCode CC, unsigned RegBytes,
5799 bool HasMemoryOperand) {
5800 static const uint16_t Opc[32][3] = {
5801 { X86::CMOVA16rr, X86::CMOVA32rr, X86::CMOVA64rr },
5802 { X86::CMOVAE16rr, X86::CMOVAE32rr, X86::CMOVAE64rr },
5803 { X86::CMOVB16rr, X86::CMOVB32rr, X86::CMOVB64rr },
5804 { X86::CMOVBE16rr, X86::CMOVBE32rr, X86::CMOVBE64rr },
5805 { X86::CMOVE16rr, X86::CMOVE32rr, X86::CMOVE64rr },
5806 { X86::CMOVG16rr, X86::CMOVG32rr, X86::CMOVG64rr },
5807 { X86::CMOVGE16rr, X86::CMOVGE32rr, X86::CMOVGE64rr },
5808 { X86::CMOVL16rr, X86::CMOVL32rr, X86::CMOVL64rr },
5809 { X86::CMOVLE16rr, X86::CMOVLE32rr, X86::CMOVLE64rr },
5810 { X86::CMOVNE16rr, X86::CMOVNE32rr, X86::CMOVNE64rr },
5811 { X86::CMOVNO16rr, X86::CMOVNO32rr, X86::CMOVNO64rr },
5812 { X86::CMOVNP16rr, X86::CMOVNP32rr, X86::CMOVNP64rr },
5813 { X86::CMOVNS16rr, X86::CMOVNS32rr, X86::CMOVNS64rr },
5814 { X86::CMOVO16rr, X86::CMOVO32rr, X86::CMOVO64rr },
5815 { X86::CMOVP16rr, X86::CMOVP32rr, X86::CMOVP64rr },
5816 { X86::CMOVS16rr, X86::CMOVS32rr, X86::CMOVS64rr },
5817 { X86::CMOVA16rm, X86::CMOVA32rm, X86::CMOVA64rm },
5818 { X86::CMOVAE16rm, X86::CMOVAE32rm, X86::CMOVAE64rm },
5819 { X86::CMOVB16rm, X86::CMOVB32rm, X86::CMOVB64rm },
5820 { X86::CMOVBE16rm, X86::CMOVBE32rm, X86::CMOVBE64rm },
5821 { X86::CMOVE16rm, X86::CMOVE32rm, X86::CMOVE64rm },
5822 { X86::CMOVG16rm, X86::CMOVG32rm, X86::CMOVG64rm },
5823 { X86::CMOVGE16rm, X86::CMOVGE32rm, X86::CMOVGE64rm },
5824 { X86::CMOVL16rm, X86::CMOVL32rm, X86::CMOVL64rm },
5825 { X86::CMOVLE16rm, X86::CMOVLE32rm, X86::CMOVLE64rm },
5826 { X86::CMOVNE16rm, X86::CMOVNE32rm, X86::CMOVNE64rm },
5827 { X86::CMOVNO16rm, X86::CMOVNO32rm, X86::CMOVNO64rm },
5828 { X86::CMOVNP16rm, X86::CMOVNP32rm, X86::CMOVNP64rm },
5829 { X86::CMOVNS16rm, X86::CMOVNS32rm, X86::CMOVNS64rm },
5830 { X86::CMOVO16rm, X86::CMOVO32rm, X86::CMOVO64rm },
5831 { X86::CMOVP16rm, X86::CMOVP32rm, X86::CMOVP64rm },
5832 { X86::CMOVS16rm, X86::CMOVS32rm, X86::CMOVS64rm }
5833 };
5834
5835 assert(CC < 16 && "Can only handle standard cond codes")((CC < 16 && "Can only handle standard cond codes"
) ? static_cast<void> (0) : __assert_fail ("CC < 16 && \"Can only handle standard cond codes\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/Target/X86/X86InstrInfo.cpp"
, 5835, __PRETTY_FUNCTION__))
;
5836 unsigned Idx = HasMemoryOperand ? 16+CC : CC;
5837 switch(RegBytes) {
5838 default: llvm_unreachable("Illegal register size!")::llvm::llvm_unreachable_internal("Illegal register size!", "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/Target/X86/X86InstrInfo.cpp"
, 5838)
;
5839 case 2: return Opc[Idx][0];
5840 case 4: return Opc[Idx][1];
5841 case 8: return Opc[Idx][2];
5842 }
5843}
5844
5845bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr &MI) const {
5846 if (!MI.isTerminator()) return false;
5847
5848 // Conditional branch is a special case.
5849 if (MI.isBranch() && !MI.isBarrier())
5850 return true;
5851 if (!MI.isPredicable())
5852 return true;
5853 return !isPredicated(MI);
5854}
5855
5856bool X86InstrInfo::isUnconditionalTailCall(const MachineInstr &MI) const {
5857 switch (MI.getOpcode()) {
5858 case X86::TCRETURNdi:
5859 case X86::TCRETURNri:
5860 case X86::TCRETURNmi:
5861 case X86::TCRETURNdi64:
5862 case X86::TCRETURNri64:
5863 case X86::TCRETURNmi64:
5864 return true;
5865 default:
5866 return false;
5867 }
5868}
5869
5870bool X86InstrInfo::canMakeTailCallConditional(
5871 SmallVectorImpl<MachineOperand> &BranchCond,
5872 const MachineInstr &TailCall) const {
5873 if (TailCall.getOpcode() != X86::TCRETURNdi &&
5874 TailCall.getOpcode() != X86::TCRETURNdi64) {
5875 // Only direct calls can be done with a conditional branch.
5876 return false;
5877 }
5878
5879 const MachineFunction *MF = TailCall.getParent()->getParent();
5880 if (Subtarget.isTargetWin64() && MF->hasWinCFI()) {
5881 // Conditional tail calls confuse the Win64 unwinder.
5882 return false;
5883 }
5884
5885 assert(BranchCond.size() == 1)((BranchCond.size() == 1) ? static_cast<void> (0) : __assert_fail
("BranchCond.size() == 1", "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/Target/X86/X86InstrInfo.cpp"
, 5885, __PRETTY_FUNCTION__))
;
5886 if (BranchCond[0].getImm() > X86::LAST_VALID_COND) {
5887 // Can't make a conditional tail call with this condition.
5888 return false;
5889 }
5890
5891 const X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
5892 if (X86FI->getTCReturnAddrDelta() != 0 ||
5893 TailCall.getOperand(1).getImm() != 0) {
5894 // A conditional tail call cannot do any stack adjustment.
5895 return false;
5896 }
5897
5898 return true;
5899}
5900
5901void X86InstrInfo::replaceBranchWithTailCall(
5902 MachineBasicBlock &MBB, SmallVectorImpl<MachineOperand> &BranchCond,
5903 const MachineInstr &TailCall) const {
5904 assert(canMakeTailCallConditional(BranchCond, TailCall))((canMakeTailCallConditional(BranchCond, TailCall)) ? static_cast
<void> (0) : __assert_fail ("canMakeTailCallConditional(BranchCond, TailCall)"
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/Target/X86/X86InstrInfo.cpp"
, 5904, __PRETTY_FUNCTION__))
;
5905
5906 MachineBasicBlock::iterator I = MBB.end();
5907 while (I != MBB.begin()) {
5908 --I;
5909 if (I->isDebugValue())
5910 continue;
5911 if (!I->isBranch())
5912 assert(0 && "Can't find the branch to replace!")((0 && "Can't find the branch to replace!") ? static_cast
<void> (0) : __assert_fail ("0 && \"Can't find the branch to replace!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/Target/X86/X86InstrInfo.cpp"
, 5912, __PRETTY_FUNCTION__))
;
5913
5914 X86::CondCode CC = getCondFromBranchOpc(I->getOpcode());
5915 assert(BranchCond.size() == 1)((BranchCond.size() == 1) ? static_cast<void> (0) : __assert_fail
("BranchCond.size() == 1", "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/Target/X86/X86InstrInfo.cpp"
, 5915, __PRETTY_FUNCTION__))
;
5916 if (CC != BranchCond[0].getImm())
5917 continue;
5918
5919 break;
5920 }
5921
5922 unsigned Opc = TailCall.getOpcode() == X86::TCRETURNdi ? X86::TCRETURNdicc
5923 : X86::TCRETURNdi64cc;
5924
5925 auto MIB = BuildMI(MBB, I, MBB.findDebugLoc(I), get(Opc));
5926 MIB->addOperand(TailCall.getOperand(0)); // Destination.
5927 MIB.addImm(0); // Stack offset (not used).
5928 MIB->addOperand(BranchCond[0]); // Condition.
5929 MIB.copyImplicitOps(TailCall); // Regmask and (imp-used) parameters.
5930
5931 // Add implicit uses and defs of all live regs potentially clobbered by the
5932 // call. This way they still appear live across the call.
5933 LivePhysRegs LiveRegs(&getRegisterInfo());
5934 LiveRegs.addLiveOuts(MBB);
5935 SmallVector<std::pair<unsigned, const MachineOperand *>, 8> Clobbers;
5936 LiveRegs.stepForward(*MIB, Clobbers);
5937 for (const auto &C : Clobbers) {
5938 MIB.addReg(C.first, RegState::Implicit);
5939 MIB.addReg(C.first, RegState::Implicit | RegState::Define);
5940 }
5941
5942 I->eraseFromParent();
5943}
5944
5945// Given a MBB and its TBB, find the FBB which was a fallthrough MBB (it may
5946// not be a fallthrough MBB now due to layout changes). Return nullptr if the
5947// fallthrough MBB cannot be identified.
5948static MachineBasicBlock *getFallThroughMBB(MachineBasicBlock *MBB,
5949 MachineBasicBlock *TBB) {
5950 // Look for non-EHPad successors other than TBB. If we find exactly one, it
5951 // is the fallthrough MBB. If we find zero, then TBB is both the target MBB
5952 // and fallthrough MBB. If we find more than one, we cannot identify the
5953 // fallthrough MBB and should return nullptr.
5954 MachineBasicBlock *FallthroughBB = nullptr;
5955 for (auto SI = MBB->succ_begin(), SE = MBB->succ_end(); SI != SE; ++SI) {
5956 if ((*SI)->isEHPad() || (*SI == TBB && FallthroughBB))
5957 continue;
5958 // Return a nullptr if we found more than one fallthrough successor.
5959 if (FallthroughBB && FallthroughBB != TBB)
5960 return nullptr;
5961 FallthroughBB = *SI;
5962 }
5963 return FallthroughBB;
5964}
5965
5966bool X86InstrInfo::AnalyzeBranchImpl(
5967 MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
5968 SmallVectorImpl<MachineOperand> &Cond,
5969 SmallVectorImpl<MachineInstr *> &CondBranches, bool AllowModify) const {
5970
5971 // Start from the bottom of the block and work up, examining the
5972 // terminator instructions.
5973 MachineBasicBlock::iterator I = MBB.end();
5974 MachineBasicBlock::iterator UnCondBrIter = MBB.end();
5975 while (I != MBB.begin()) {
5976 --I;
5977 if (I->isDebugValue())
5978 continue;
5979
5980 // Working from the bottom, when we see a non-terminator instruction, we're
5981 // done.
5982 if (!isUnpredicatedTerminator(*I))
5983 break;
5984
5985 // A terminator that isn't a branch can't easily be handled by this
5986 // analysis.
5987 if (!I->isBranch())
5988 return true;
5989
5990 // Handle unconditional branches.
5991 if (I->getOpcode() == X86::JMP_1) {
5992 UnCondBrIter = I;
5993
5994 if (!AllowModify) {
5995 TBB = I->getOperand(0).getMBB();
5996 continue;
5997 }
5998
5999 // If the block has any instructions after a JMP, delete them.
6000 while (std::next(I) != MBB.end())
6001 std::next(I)->eraseFromParent();
6002
6003 Cond.clear();
6004 FBB = nullptr;
6005
6006 // Delete the JMP if it's equivalent to a fall-through.
6007 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
6008 TBB = nullptr;
6009 I->eraseFromParent();
6010 I = MBB.end();
6011 UnCondBrIter = MBB.end();
6012 continue;
6013 }
6014
6015 // TBB is used to indicate the unconditional destination.
6016 TBB = I->getOperand(0).getMBB();
6017 continue;
6018 }
6019
6020 // Handle conditional branches.
6021 X86::CondCode BranchCode = getCondFromBranchOpc(I->getOpcode());
6022 if (BranchCode == X86::COND_INVALID)
6023 return true; // Can't handle indirect branch.
6024
6025 // Working from the bottom, handle the first conditional branch.
6026 if (Cond.empty()) {
6027 MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
6028 if (AllowModify && UnCondBrIter != MBB.end() &&
6029 MBB.isLayoutSuccessor(TargetBB)) {
6030 // If we can modify the code and it ends in something like:
6031 //
6032 // jCC L1
6033 // jmp L2
6034 // L1:
6035 // ...
6036 // L2:
6037 //
6038 // Then we can change this to:
6039 //
6040 // jnCC L2
6041 // L1:
6042 // ...
6043 // L2:
6044 //
6045 // Which is a bit more efficient.
6046 // We conditionally jump to the fall-through block.
6047 BranchCode = GetOppositeBranchCondition(BranchCode);
6048 unsigned JNCC = GetCondBranchFromCond(BranchCode);
6049 MachineBasicBlock::iterator OldInst = I;
6050
6051 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(JNCC))
6052 .addMBB(UnCondBrIter->getOperand(0).getMBB());
6053 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_1))
6054 .addMBB(TargetBB);
6055
6056 OldInst->eraseFromParent();
6057 UnCondBrIter->eraseFromParent();
6058
6059 // Restart the analysis.
6060 UnCondBrIter = MBB.end();
6061 I = MBB.end();
6062 continue;
6063 }
6064
6065 FBB = TBB;
6066 TBB = I->getOperand(0).getMBB();
6067 Cond.push_back(MachineOperand::CreateImm(BranchCode));
6068 CondBranches.push_back(&*I);
6069 continue;
6070 }
6071
6072 // Handle subsequent conditional branches. Only handle the case where all
6073 // conditional branches branch to the same destination and their condition
6074 // opcodes fit one of the special multi-branch idioms.
6075 assert(Cond.size() == 1)((Cond.size() == 1) ? static_cast<void> (0) : __assert_fail
("Cond.size() == 1", "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/Target/X86/X86InstrInfo.cpp"
, 6075, __PRETTY_FUNCTION__))
;
6076 assert(TBB)((TBB) ? static_cast<void> (0) : __assert_fail ("TBB", "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/Target/X86/X86InstrInfo.cpp"
, 6076, __PRETTY_FUNCTION__))
;
6077
6078 // If the conditions are the same, we can leave them alone.
6079 X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
6080 auto NewTBB = I->getOperand(0).getMBB();
6081 if (OldBranchCode == BranchCode && TBB == NewTBB)
6082 continue;
6083
6084 // If they differ, see if they fit one of the known patterns. Theoretically,
6085 // we could handle more patterns here, but we shouldn't expect to see them
6086 // if instruction selection has done a reasonable job.
6087 if (TBB == NewTBB &&
6088 ((OldBranchCode == X86::COND_P && BranchCode == X86::COND_NE) ||
6089 (OldBranchCode == X86::COND_NE && BranchCode == X86::COND_P))) {
6090 BranchCode = X86::COND_NE_OR_P;
6091 } else if ((OldBranchCode == X86::COND_NP && BranchCode == X86::COND_NE) ||
6092 (OldBranchCode == X86::COND_E && BranchCode == X86::COND_P)) {
6093 if (NewTBB != (FBB ? FBB : getFallThroughMBB(&MBB, TBB)))
6094 return true;
6095
6096 // X86::COND_E_AND_NP usually has two different branch destinations.
6097 //
6098 // JP B1
6099 // JE B2
6100 // JMP B1
6101 // B1:
6102 // B2:
6103 //
6104 // Here this condition branches to B2 only if NP && E. It has another
6105 // equivalent form:
6106 //
6107 // JNE B1
6108 // JNP B2
6109 // JMP B1
6110 // B1:
6111 // B2:
6112 //
6113 // Similarly it branches to B2 only if E && NP. That is why this condition
6114 // is named with COND_E_AND_NP.
6115 BranchCode = X86::COND_E_AND_NP;
6116 } else
6117 return true;
6118
6119 // Update the MachineOperand.
6120 Cond[0].setImm(BranchCode);
6121 CondBranches.push_back(&*I);
6122 }
6123
6124 return false;
6125}
6126
6127bool X86InstrInfo::analyzeBranch(MachineBasicBlock &MBB,
6128 MachineBasicBlock *&TBB,
6129 MachineBasicBlock *&FBB,
6130 SmallVectorImpl<MachineOperand> &Cond,
6131 bool AllowModify) const {
6132 SmallVector<MachineInstr *, 4> CondBranches;
6133 return AnalyzeBranchImpl(MBB, TBB, FBB, Cond, CondBranches, AllowModify);
6134}
6135
6136bool X86InstrInfo::analyzeBranchPredicate(MachineBasicBlock &MBB,
6137 MachineBranchPredicate &MBP,
6138 bool AllowModify) const {
6139 using namespace std::placeholders;
6140
6141 SmallVector<MachineOperand, 4> Cond;
6142 SmallVector<MachineInstr *, 4> CondBranches;
6143 if (AnalyzeBranchImpl(MBB, MBP.TrueDest, MBP.FalseDest, Cond, CondBranches,
6144 AllowModify))
6145 return true;
6146
6147 if (Cond.size() != 1)
6148 return true;
6149
6150 assert(MBP.TrueDest && "expected!")((MBP.TrueDest && "expected!") ? static_cast<void>
(0) : __assert_fail ("MBP.TrueDest && \"expected!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/Target/X86/X86InstrInfo.cpp"
, 6150, __PRETTY_FUNCTION__))
;
6151
6152 if (!MBP.FalseDest)
6153 MBP.FalseDest = MBB.getNextNode();
6154
6155 const TargetRegisterInfo *TRI = &getRegisterInfo();
6156
6157 MachineInstr *ConditionDef = nullptr;
6158 bool SingleUseCondition = true;
6159
6160 for (auto I = std::next(MBB.rbegin()), E = MBB.rend(); I != E; ++I) {
6161 if (I->modifiesRegister(X86::EFLAGS, TRI)) {
6162 ConditionDef = &*I;
6163 break;
6164 }
6165
6166 if (I->readsRegister(X86::EFLAGS, TRI))
6167 SingleUseCondition = false;
6168 }
6169
6170 if (!ConditionDef)
6171 return true;
6172
6173 if (SingleUseCondition) {
6174 for (auto *Succ : MBB.successors())
6175 if (Succ->isLiveIn(X86::EFLAGS))
6176 SingleUseCondition = false;
6177 }
6178
6179 MBP.ConditionDef = ConditionDef;
6180 MBP.SingleUseCondition = SingleUseCondition;
6181
6182 // Currently we only recognize the simple pattern:
6183 //
6184 // test %reg, %reg
6185 // je %label
6186 //
6187 const unsigned TestOpcode =
6188 Subtarget.is64Bit() ? X86::TEST64rr : X86::TEST32rr;
6189
6190 if (ConditionDef->getOpcode() == TestOpcode &&
6191 ConditionDef->getNumOperands() == 3 &&
6192 ConditionDef->getOperand(0).isIdenticalTo(ConditionDef->getOperand(1)) &&
6193 (Cond[0].getImm() == X86::COND_NE || Cond[0].getImm() == X86::COND_E)) {
6194 MBP.LHS = ConditionDef->getOperand(0);
6195 MBP.RHS = MachineOperand::CreateImm(0);
6196 MBP.Predicate = Cond[0].getImm() == X86::COND_NE
6197 ? MachineBranchPredicate::PRED_NE
6198 : MachineBranchPredicate::PRED_EQ;
6199 return false;
6200 }
6201
6202 return true;
6203}
6204
6205unsigned X86InstrInfo::removeBranch(MachineBasicBlock &MBB,
6206 int *BytesRemoved) const {
6207 assert(!BytesRemoved && "code size not handled")((!BytesRemoved && "code size not handled") ? static_cast
<void> (0) : __assert_fail ("!BytesRemoved && \"code size not handled\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/Target/X86/X86InstrInfo.cpp"
, 6207, __PRETTY_FUNCTION__))
;
6208
6209 MachineBasicBlock::iterator I = MBB.end();
6210 unsigned Count = 0;
6211
6212 while (I != MBB.begin()) {
6213 --I;
6214 if (I->isDebugValue())
6215 continue;
6216 if (I->getOpcode() != X86::JMP_1 &&
6217 getCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
6218 break;
6219 // Remove the branch.
6220 I->eraseFromParent();
6221 I = MBB.end();
6222 ++Count;
6223 }
6224
6225 return Count;
6226}
6227
6228unsigned X86InstrInfo::insertBranch(MachineBasicBlock &MBB,
6229 MachineBasicBlock *TBB,
6230 MachineBasicBlock *FBB,
6231 ArrayRef<MachineOperand> Cond,
6232 const DebugLoc &DL,
6233 int *BytesAdded) const {
6234 // Shouldn't be a fall through.
6235 assert(TBB && "insertBranch must not be told to insert a fallthrough")((TBB && "insertBranch must not be told to insert a fallthrough"
) ? static_cast<void> (0) : __assert_fail ("TBB && \"insertBranch must not be told to insert a fallthrough\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/Target/X86/X86InstrInfo.cpp"
, 6235, __PRETTY_FUNCTION__))
;
6236 assert((Cond.size() == 1 || Cond.size() == 0) &&(((Cond.size() == 1 || Cond.size() == 0) && "X86 branch conditions have one component!"
) ? static_cast<void> (0) : __assert_fail ("(Cond.size() == 1 || Cond.size() == 0) && \"X86 branch conditions have one component!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/Target/X86/X86InstrInfo.cpp"
, 6237, __PRETTY_FUNCTION__))
6237 "X86 branch conditions have one component!")(((Cond.size() == 1 || Cond.size() == 0) && "X86 branch conditions have one component!"
) ? static_cast<void> (0) : __assert_fail ("(Cond.size() == 1 || Cond.size() == 0) && \"X86 branch conditions have one component!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/Target/X86/X86InstrInfo.cpp"
, 6237, __PRETTY_FUNCTION__))
;
6238 assert(!BytesAdded && "code size not handled")((!BytesAdded && "code size not handled") ? static_cast
<void> (0) : __assert_fail ("!BytesAdded && \"code size not handled\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/Target/X86/X86InstrInfo.cpp"
, 6238, __PRETTY_FUNCTION__))
;
6239
6240 if (Cond.empty()) {
6241 // Unconditional branch?
6242 assert(!FBB && "Unconditional branch with multiple successors!")((!FBB && "Unconditional branch with multiple successors!"
) ? static_cast<void> (0) : __assert_fail ("!FBB && \"Unconditional branch with multiple successors!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/Target/X86/X86InstrInfo.cpp"
, 6242, __PRETTY_FUNCTION__))
;
6243 BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(TBB);
6244 return 1;
6245 }
6246
6247 // If FBB is null, it is implied to be a fall-through block.
6248 bool FallThru = FBB == nullptr;
6249
6250 // Conditional branch.
6251 unsigned Count = 0;
6252 X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
6253 switch (CC) {
6254 case X86::COND_NE_OR_P:
6255 // Synthesize NE_OR_P with two branches.
6256 BuildMI(&MBB, DL, get(X86::JNE_1)).addMBB(TBB);
6257 ++Count;
6258 BuildMI(&MBB, DL, get(X86::JP_1)).addMBB(TBB);
6259 ++Count;
6260 break;
6261 case X86::COND_E_AND_NP:
6262 // Use the next block of MBB as FBB if it is null.
6263 if (FBB == nullptr) {
6264 FBB = getFallThroughMBB(&MBB, TBB);
6265 assert(FBB && "MBB cannot be the last block in function when the false "((FBB && "MBB cannot be the last block in function when the false "
"body is a fall-through.") ? static_cast<void> (0) : __assert_fail
("FBB && \"MBB cannot be the last block in function when the false \" \"body is a fall-through.\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/Target/X86/X86InstrInfo.cpp"
, 6266, __PRETTY_FUNCTION__))
6266 "body is a fall-through.")((FBB && "MBB cannot be the last block in function when the false "
"body is a fall-through.") ? static_cast<void> (0) : __assert_fail
("FBB && \"MBB cannot be the last block in function when the false \" \"body is a fall-through.\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/Target/X86/X86InstrInfo.cpp"
, 6266, __PRETTY_FUNCTION__))
;
6267 }
6268 // Synthesize COND_E_AND_NP with two branches.
6269 BuildMI(&MBB, DL, get(X86::JNE_1)).addMBB(FBB);
6270 ++Count;
6271 BuildMI(&MBB, DL, get(X86::JNP_1)).addMBB(TBB);
6272 ++Count;
6273 break;
6274 default: {
6275 unsigned Opc = GetCondBranchFromCond(CC);
6276 BuildMI(&MBB, DL, get(Opc)).addMBB(TBB);
6277 ++Count;
6278 }
6279 }
6280 if (!FallThru) {
6281 // Two-way Conditional branch. Insert the second branch.
6282 BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(FBB);
6283 ++Count;
6284 }
6285 return Count;
6286}
6287
6288bool X86InstrInfo::
6289canInsertSelect(const MachineBasicBlock &MBB,
6290 ArrayRef<MachineOperand> Cond,
6291 unsigned TrueReg, unsigned FalseReg,
6292 int &CondCycles, int &TrueCycles, int &FalseCycles) const {
6293 // Not all subtargets have cmov instructions.
6294 if (!Subtarget.hasCMov())
6295 return false;
6296 if (Cond.size() != 1)
6297 return false;
6298 // We cannot do the composite conditions, at least not in SSA form.
6299 if ((X86::CondCode)Cond[0].getImm() > X86::COND_S)
6300 return false;
6301
6302 // Check register classes.
6303 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
6304 const TargetRegisterClass *RC =
6305 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
6306 if (!RC)
6307 return false;
6308
6309 // We have cmov instructions for 16, 32, and 64 bit general purpose registers.
6310 if (X86::GR16RegClass.hasSubClassEq(RC) ||
6311 X86::GR32RegClass.hasSubClassEq(RC) ||
6312 X86::GR64RegClass.hasSubClassEq(RC)) {
6313 // This latency applies to Pentium M, Merom, Wolfdale, Nehalem, and Sandy
6314 // Bridge. Probably Ivy Bridge as well.
6315 CondCycles = 2;
6316 TrueCycles = 2;
6317 FalseCycles = 2;
6318 return true;
6319 }
6320
6321 // Can't do vectors.
6322 return false;
6323}
6324
6325void X86InstrInfo::insertSelect(MachineBasicBlock &MBB,
6326 MachineBasicBlock::iterator I,
6327 const DebugLoc &DL, unsigned DstReg,
6328 ArrayRef<MachineOperand> Cond, unsigned TrueReg,
6329 unsigned FalseReg) const {
6330 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
6331 const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
6332 const TargetRegisterClass &RC = *MRI.getRegClass(DstReg);
6333 assert(Cond.size() == 1 && "Invalid Cond array")((Cond.size() == 1 && "Invalid Cond array") ? static_cast
<void> (0) : __assert_fail ("Cond.size() == 1 && \"Invalid Cond array\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/Target/X86/X86InstrInfo.cpp"
, 6333, __PRETTY_FUNCTION__))
;
6334 unsigned Opc = getCMovFromCond((X86::CondCode)Cond[0].getImm(),
6335 TRI.getRegSizeInBits(RC) / 8,
6336 false /*HasMemoryOperand*/);
6337 BuildMI(MBB, I, DL, get(Opc), DstReg).addReg(FalseReg).addReg(TrueReg);
6338}
6339
6340/// Test if the given register is a physical h register.
6341static bool isHReg(unsigned Reg) {
6342 return X86::GR8_ABCD_HRegClass.contains(Reg);
6343}
6344
6345// Try and copy between VR128/VR64 and GR64 registers.
6346static unsigned CopyToFromAsymmetricReg(unsigned &DestReg, unsigned &SrcReg,
6347 const X86Subtarget &Subtarget) {
6348 bool HasAVX = Subtarget.hasAVX();
6349 bool HasAVX512 = Subtarget.hasAVX512();
6350
6351 // SrcReg(MaskReg) -> DestReg(GR64)
6352 // SrcReg(MaskReg) -> DestReg(GR32)
6353
6354 // All KMASK RegClasses hold the same k registers, can be tested against anyone.
6355 if (X86::VK16RegClass.contains(SrcReg)) {
6356 if (X86::GR64RegClass.contains(DestReg)) {
6357 assert(Subtarget.hasBWI())((Subtarget.hasBWI()) ? static_cast<void> (0) : __assert_fail
("Subtarget.hasBWI()", "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/Target/X86/X86InstrInfo.cpp"
, 6357, __PRETTY_FUNCTION__))
;
6358 return X86::KMOVQrk;
6359 }
6360 if (X86::GR32RegClass.contains(DestReg))
6361 return Subtarget.hasBWI() ? X86::KMOVDrk : X86::KMOVWrk;
6362 }
6363
6364 // SrcReg(GR64) -> DestReg(MaskReg)
6365 // SrcReg(GR32) -> DestReg(MaskReg)
6366
6367 // All KMASK RegClasses hold the same k registers, can be tested against anyone.
6368 if (X86::VK16RegClass.contains(DestReg)) {
6369 if (X86::GR64RegClass.contains(SrcReg)) {
6370 assert(Subtarget.hasBWI())((Subtarget.hasBWI()) ? static_cast<void> (0) : __assert_fail
("Subtarget.hasBWI()", "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/Target/X86/X86InstrInfo.cpp"
, 6370, __PRETTY_FUNCTION__))
;
6371 return X86::KMOVQkr;
6372 }
6373 if (X86::GR32RegClass.contains(SrcReg))
6374 return Subtarget.hasBWI() ? X86::KMOVDkr : X86::KMOVWkr;
6375 }
6376
6377
6378 // SrcReg(VR128) -> DestReg(GR64)
6379 // SrcReg(VR64) -> DestReg(GR64)
6380 // SrcReg(GR64) -> DestReg(VR128)
6381 // SrcReg(GR64) -> DestReg(VR64)
6382
6383 if (X86::GR64RegClass.contains(DestReg)) {
6384 if (X86::VR128XRegClass.contains(SrcReg))
6385 // Copy from a VR128 register to a GR64 register.
6386 return HasAVX512 ? X86::VMOVPQIto64Zrr :
6387 HasAVX ? X86::VMOVPQIto64rr :
6388 X86::MOVPQIto64rr;
6389 if (X86::VR64RegClass.contains(SrcReg))
6390 // Copy from a VR64 register to a GR64 register.
6391 return X86::MMX_MOVD64from64rr;
6392 } else if (X86::GR64RegClass.contains(SrcReg)) {
6393 // Copy from a GR64 register to a VR128 register.
6394 if (X86::VR128XRegClass.contains(DestReg))
6395 return HasAVX512 ? X86::VMOV64toPQIZrr :
6396 HasAVX ? X86::VMOV64toPQIrr :
6397 X86::MOV64toPQIrr;
6398 // Copy from a GR64 register to a VR64 register.
6399 if (X86::VR64RegClass.contains(DestReg))
6400 return X86::MMX_MOVD64to64rr;
6401 }
6402
6403 // SrcReg(FR32) -> DestReg(GR32)
6404 // SrcReg(GR32) -> DestReg(FR32)
6405
6406 if (X86::GR32RegClass.contains(DestReg) &&
6407 X86::FR32XRegClass.contains(SrcReg))
6408 // Copy from a FR32 register to a GR32 register.
6409 return HasAVX512 ? X86::VMOVSS2DIZrr :
6410 HasAVX ? X86::VMOVSS2DIrr :
6411 X86::MOVSS2DIrr;
6412
6413 if (X86::FR32XRegClass.contains(DestReg) &&
6414 X86::GR32RegClass.contains(SrcReg))
6415 // Copy from a GR32 register to a FR32 register.
6416 return HasAVX512 ? X86::VMOVDI2SSZrr :
6417 HasAVX ? X86::VMOVDI2SSrr :
6418 X86::MOVDI2SSrr;
6419 return 0;
6420}
6421
6422void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
6423 MachineBasicBlock::iterator MI,
6424 const DebugLoc &DL, unsigned DestReg,
6425 unsigned SrcReg, bool KillSrc) const {
6426 // First deal with the normal symmetric copies.
6427 bool HasAVX = Subtarget.hasAVX();
6428 bool HasVLX = Subtarget.hasVLX();
6429 unsigned Opc = 0;
6430 if (X86::GR64RegClass.contains(DestReg, SrcReg))
6431 Opc = X86::MOV64rr;
6432 else if (X86::GR32RegClass.contains(DestReg, SrcReg))
6433 Opc = X86::MOV32rr;
6434 else if (X86::GR16RegClass.contains(DestReg, SrcReg))
6435 Opc = X86::MOV16rr;
6436 else if (X86::GR8RegClass.contains(DestReg, SrcReg)) {
6437 // Copying to or from a physical H register on x86-64 requires a NOREX
6438 // move. Otherwise use a normal move.
6439 if ((isHReg(DestReg) || isHReg(SrcReg)) &&
6440 Subtarget.is64Bit()) {
6441 Opc = X86::MOV8rr_NOREX;
6442 // Both operands must be encodable without an REX prefix.
6443 assert(X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) &&((X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) &&
"8-bit H register can not be copied outside GR8_NOREX") ? static_cast
<void> (0) : __assert_fail ("X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) && \"8-bit H register can not be copied outside GR8_NOREX\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/Target/X86/X86InstrInfo.cpp"
, 6444, __PRETTY_FUNCTION__))
6444 "8-bit H register can not be copied outside GR8_NOREX")((X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) &&
"8-bit H register can not be copied outside GR8_NOREX") ? static_cast
<void> (0) : __assert_fail ("X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) && \"8-bit H register can not be copied outside GR8_NOREX\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/Target/X86/X86InstrInfo.cpp"
, 6444, __PRETTY_FUNCTION__))
;
6445 } else
6446 Opc = X86::MOV8rr;
6447 }
6448 else if (X86::VR64RegClass.contains(DestReg, SrcReg))
6449 Opc = X86::MMX_MOVQ64rr;
6450 else if (X86::VR128XRegClass.contains(DestReg, SrcReg)) {
6451 if (HasVLX)
6452 Opc = X86::VMOVAPSZ128rr;
6453 else if (X86::VR128RegClass.contains(DestReg, SrcReg))
6454 Opc = HasAVX ? X86::VMOVAPSrr : X86::MOVAPSrr;
6455 else {
6456 // If this an extended register and we don't have VLX we need to use a
6457 // 512-bit move.
6458 Opc = X86::VMOVAPSZrr;
6459 const TargetRegisterInfo *TRI = &getRegisterInfo();
6460 DestReg = TRI->getMatchingSuperReg(DestReg, X86::sub_xmm,
6461 &X86::VR512RegClass);
6462 SrcReg = TRI->getMatchingSuperReg(SrcReg, X86::sub_xmm,
6463 &X86::VR512RegClass);
6464 }
6465 } else if (X86::VR256XRegClass.contains(DestReg, SrcReg)) {
6466 if (HasVLX)
6467 Opc = X86::VMOVAPSZ256rr;
6468 else if (X86::VR256RegClass.contains(DestReg, SrcReg))
6469 Opc = X86::VMOVAPSYrr;
6470 else {
6471 // If this an extended register and we don't have VLX we need to use a
6472 // 512-bit move.
6473 Opc = X86::VMOVAPSZrr;
6474 const TargetRegisterInfo *TRI = &getRegisterInfo();
6475 DestReg = TRI->getMatchingSuperReg(DestReg, X86::sub_ymm,
6476 &X86::VR512RegClass);
6477 SrcReg = TRI->getMatchingSuperReg(SrcReg, X86::sub_ymm,
6478 &X86::VR512RegClass);
6479 }
6480 } else if (X86::VR512RegClass.contains(DestReg, SrcReg))
6481 Opc = X86::VMOVAPSZrr;
6482 // All KMASK RegClasses hold the same k registers, can be tested against anyone.
6483 else if (X86::VK16RegClass.contains(DestReg, SrcReg))
6484 Opc = Subtarget.hasBWI() ? X86::KMOVQkk : X86::KMOVWkk;
6485 if (!Opc)
6486 Opc = CopyToFromAsymmetricReg(DestReg, SrcReg, Subtarget);
6487
6488 if (Opc) {
6489 BuildMI(MBB, MI, DL, get(Opc), DestReg)
6490 .addReg(SrcReg, getKillRegState(KillSrc));
6491 return;
6492 }
6493
6494 bool FromEFLAGS = SrcReg == X86::EFLAGS;
6495 bool ToEFLAGS = DestReg == X86::EFLAGS;
6496 int Reg = FromEFLAGS ? DestReg : SrcReg;
6497 bool is32 = X86::GR32RegClass.contains(Reg);
6498 bool is64 = X86::GR64RegClass.contains(Reg);
6499
6500 if ((FromEFLAGS || ToEFLAGS) && (is32 || is64)) {
6501 int Mov = is64 ? X86::MOV64rr : X86::MOV32rr;
6502 int Push = is64 ? X86::PUSH64r : X86::PUSH32r;
6503 int PushF = is64 ? X86::PUSHF64 : X86::PUSHF32;
6504 int Pop = is64 ? X86::POP64r : X86::POP32r;
6505 int PopF = is64 ? X86::POPF64 : X86::POPF32;
6506 int AX = is64 ? X86::RAX : X86::EAX;
6507
6508 if (!Subtarget.hasLAHFSAHF()) {
6509 assert(Subtarget.is64Bit() &&((Subtarget.is64Bit() && "Not having LAHF/SAHF only happens on 64-bit."
) ? static_cast<void> (0) : __assert_fail ("Subtarget.is64Bit() && \"Not having LAHF/SAHF only happens on 64-bit.\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/Target/X86/X86InstrInfo.cpp"
, 6510, __PRETTY_FUNCTION__))
6510 "Not having LAHF/SAHF only happens on 64-bit.")((Subtarget.is64Bit() && "Not having LAHF/SAHF only happens on 64-bit."
) ? static_cast<void> (0) : __assert_fail ("Subtarget.is64Bit() && \"Not having LAHF/SAHF only happens on 64-bit.\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/Target/X86/X86InstrInfo.cpp"
, 6510, __PRETTY_FUNCTION__))
;
6511 // Moving EFLAGS to / from another register requires a push and a pop.
6512 // Notice that we have to adjust the stack if we don't want to clobber the
6513 // first frame index. See X86FrameLowering.cpp - usesTheStack.
6514 if (FromEFLAGS) {
6515 BuildMI(MBB, MI, DL, get(PushF));
6516 BuildMI(MBB, MI, DL, get(Pop), DestReg);
6517 }
6518 if (ToEFLAGS) {
6519 BuildMI(MBB, MI, DL, get(Push))
6520 .addReg(SrcReg, getKillRegState(KillSrc));
6521 BuildMI(MBB, MI, DL, get(PopF));
6522 }
6523 return;
6524 }
6525
6526 // The flags need to be saved, but saving EFLAGS with PUSHF/POPF is
6527 // inefficient. Instead:
6528 // - Save the overflow flag OF into AL using SETO, and restore it using a
6529 // signed 8-bit addition of AL and INT8_MAX.
6530 // - Save/restore the bottom 8 EFLAGS bits (CF, PF, AF, ZF, SF) to/from AH
6531 // using LAHF/SAHF.
6532 // - When RAX/EAX is live and isn't the destination register, make sure it
6533 // isn't clobbered by PUSH/POP'ing it before and after saving/restoring
6534 // the flags.
6535 // This approach is ~2.25x faster than using PUSHF/POPF.
6536 //
6537 // This is still somewhat inefficient because we don't know which flags are
6538 // actually live inside EFLAGS. Were we able to do a single SETcc instead of
6539 // SETO+LAHF / ADDB+SAHF the code could be 1.02x faster.
6540 //
6541 // PUSHF/POPF is also potentially incorrect because it affects other flags
6542 // such as TF/IF/DF, which LLVM doesn't model.
6543 //
6544 // Notice that we have to adjust the stack if we don't want to clobber the
6545 // first frame index.
6546 // See X86ISelLowering.cpp - X86::hasCopyImplyingStackAdjustment.
6547
6548 const TargetRegisterInfo *TRI = &getRegisterInfo();
6549 MachineBasicBlock::LivenessQueryResult LQR =
6550 MBB.computeRegisterLiveness(TRI, AX, MI);
6551 // We do not want to save and restore AX if we do not have to.
6552 // Moreover, if we do so whereas AX is dead, we would need to set
6553 // an undef flag on the use of AX, otherwise the verifier will
6554 // complain that we read an undef value.
6555 // We do not want to change the behavior of the machine verifier
6556 // as this is usually wrong to read an undef value.
6557 if (MachineBasicBlock::LQR_Unknown == LQR) {
6558 LivePhysRegs LPR(TRI);
6559 LPR.addLiveOuts(MBB);
6560 MachineBasicBlock::iterator I = MBB.end();
6561 while (I != MI) {
6562 --I;
6563 LPR.stepBackward(*I);
6564 }
6565 // AX contains the top most register in the aliasing hierarchy.
6566 // It may not be live, but one of its aliases may be.
6567 for (MCRegAliasIterator AI(AX, TRI, true);
6568 AI.isValid() && LQR != MachineBasicBlock::LQR_Live; ++AI)
6569 LQR = LPR.contains(*AI) ? MachineBasicBlock::LQR_Live
6570 : MachineBasicBlock::LQR_Dead;
6571 }
6572 bool AXDead = (Reg == AX) || (MachineBasicBlock::LQR_Dead == LQR);
6573 if (!AXDead)
6574 BuildMI(MBB, MI, DL, get(Push)).addReg(AX, getKillRegState(true));
6575 if (FromEFLAGS) {
6576 BuildMI(MBB, MI, DL, get(X86::SETOr), X86::AL);
6577 BuildMI(MBB, MI, DL, get(X86::LAHF));
6578 BuildMI(MBB, MI, DL, get(Mov), Reg).addReg(AX);
6579 }
6580 if (ToEFLAGS) {
6581 BuildMI(MBB, MI, DL, get(Mov), AX).addReg(Reg, getKillRegState(KillSrc));
6582 BuildMI(MBB, MI, DL, get(X86::ADD8ri), X86::AL)
6583 .addReg(X86::AL)
6584 .addImm(INT8_MAX(127));
6585 BuildMI(MBB, MI, DL, get(X86::SAHF));
6586 }
6587 if (!AXDead)
6588 BuildMI(MBB, MI, DL, get(Pop), AX);
6589 return;
6590 }
6591
6592 DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("x86-instr-info")) { dbgs() << "Cannot copy " <<
RI.getName(SrcReg) << " to " << RI.getName(DestReg
) << '\n'; } } while (false)
6593 << " to " << RI.getName(DestReg) << '\n')do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("x86-instr-info")) { dbgs() << "Cannot copy " <<
RI.getName(SrcReg) << " to " << RI.getName(DestReg
) << '\n'; } } while (false)
;
6594 llvm_unreachable("Cannot emit physreg copy instruction")::llvm::llvm_unreachable_internal("Cannot emit physreg copy instruction"
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/Target/X86/X86InstrInfo.cpp"
, 6594)
;
6595}
6596
6597static unsigned getLoadStoreRegOpcode(unsigned Reg,
6598 const TargetRegisterClass *RC,
6599 bool isStackAligned,
6600 const X86Subtarget &STI,
6601 bool load) {
6602 bool HasAVX = STI.hasAVX();
6603 bool HasAVX512 = STI.hasAVX512();
6604 bool HasVLX = STI.hasVLX();
6605
6606 switch (STI.getRegisterInfo()->getSpillSize(*RC)) {
6607 default:
6608 llvm_unreachable("Unknown spill size")::llvm::llvm_unreachable_internal("Unknown spill size", "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/Target/X86/X86InstrInfo.cpp"
, 6608)
;
6609 case 1:
6610 assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass")((X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass"
) ? static_cast<void> (0) : __assert_fail ("X86::GR8RegClass.hasSubClassEq(RC) && \"Unknown 1-byte regclass\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/Target/X86/X86InstrInfo.cpp"
, 6610, __PRETTY_FUNCTION__))
;
6611 if (STI.is64Bit())
6612 // Copying to or from a physical H register on x86-64 requires a NOREX
6613 // move. Otherwise use a normal move.
6614 if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC))
6615 return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
6616 return load ? X86::MOV8rm : X86::MOV8mr;
6617 case 2:
6618 if (X86::VK16RegClass.hasSubClassEq(RC))
6619 return load ? X86::KMOVWkm : X86::KMOVWmk;
6620 assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass")((X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass"
) ? static_cast<void> (0) : __assert_fail ("X86::GR16RegClass.hasSubClassEq(RC) && \"Unknown 2-byte regclass\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/Target/X86/X86InstrInfo.cpp"
, 6620, __PRETTY_FUNCTION__))
;
6621 return load ? X86::MOV16rm : X86::MOV16mr;
6622 case 4:
6623 if (X86::GR32RegClass.hasSubClassEq(RC))
6624 return load ? X86::MOV32rm : X86::MOV32mr;
6625 if (X86::FR32XRegClass.hasSubClassEq(RC))
6626 return load ?
6627 (HasAVX512 ? X86::VMOVSSZrm : HasAVX ? X86::VMOVSSrm : X86::MOVSSrm) :
6628 (HasAVX512 ? X86::VMOVSSZmr : HasAVX ? X86::VMOVSSmr : X86::MOVSSmr);
6629 if (X86::RFP32RegClass.hasSubClassEq(RC))
6630 return load ? X86::LD_Fp32m : X86::ST_Fp32m;
6631 if (X86::VK32RegClass.hasSubClassEq(RC))
6632 return load ? X86::KMOVDkm : X86::KMOVDmk;
6633 llvm_unreachable("Unknown 4-byte regclass")::llvm::llvm_unreachable_internal("Unknown 4-byte regclass", "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/Target/X86/X86InstrInfo.cpp"
, 6633)
;
6634 case 8:
6635 if (X86::GR64RegClass.hasSubClassEq(RC))
6636 return load ? X86::MOV64rm : X86::MOV64mr;
6637 if (X86::FR64XRegClass.hasSubClassEq(RC))
6638 return load ?
6639 (HasAVX512 ? X86::VMOVSDZrm : HasAVX ? X86::VMOVSDrm : X86::MOVSDrm) :
6640 (HasAVX512 ? X86::VMOVSDZmr : HasAVX ? X86::VMOVSDmr : X86::MOVSDmr);
6641 if (X86::VR64RegClass.hasSubClassEq(RC))
6642 return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr;
6643 if (X86::RFP64RegClass.hasSubClassEq(RC))
6644 return load ? X86::LD_Fp64m : X86::ST_Fp64m;
6645 if (X86::VK64RegClass.hasSubClassEq(RC))
6646 return load ? X86::KMOVQkm : X86::KMOVQmk;
6647 llvm_unreachable("Unknown 8-byte regclass")::llvm::llvm_unreachable_internal("Unknown 8-byte regclass", "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/Target/X86/X86InstrInfo.cpp"
, 6647)
;
6648 case 10:
6649 assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass")((X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass"
) ? static_cast<void> (0) : __assert_fail ("X86::RFP80RegClass.hasSubClassEq(RC) && \"Unknown 10-byte regclass\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/Target/X86/X86InstrInfo.cpp"
, 6649, __PRETTY_FUNCTION__))
;
6650 return load ? X86::LD_Fp80m : X86::ST_FpP80m;
6651 case 16: {
6652 if (X86::VR128XRegClass.hasSubClassEq(RC)) {
6653 // If stack is realigned we can use aligned stores.
6654 if (isStackAligned)
6655 return load ?
6656 (HasVLX ? X86::VMOVAPSZ128rm :
6657 HasAVX512 ? X86::VMOVAPSZ128rm_NOVLX :
6658 HasAVX ? X86::VMOVAPSrm :
6659 X86::MOVAPSrm):
6660 (HasVLX ? X86::VMOVAPSZ128mr :
6661 HasAVX512 ? X86::VMOVAPSZ128mr_NOVLX :
6662 HasAVX ? X86::VMOVAPSmr :
6663 X86::MOVAPSmr);
6664 else
6665 return load ?
6666 (HasVLX ? X86::VMOVUPSZ128rm :
6667 HasAVX512 ? X86::VMOVUPSZ128rm_NOVLX :
6668 HasAVX ? X86::VMOVUPSrm :
6669 X86::MOVUPSrm):
6670 (HasVLX ? X86::VMOVUPSZ128mr :
6671 HasAVX512 ? X86::VMOVUPSZ128mr_NOVLX :
6672 HasAVX ? X86::VMOVUPSmr :
6673 X86::MOVUPSmr);
6674 }
6675 if (X86::BNDRRegClass.hasSubClassEq(RC)) {
6676 if (STI.is64Bit())
6677 return load ? X86::BNDMOVRM64rm : X86::BNDMOVMR64mr;
6678 else
6679 return load ? X86::BNDMOVRM32rm : X86::BNDMOVMR32mr;
6680 }
6681 llvm_unreachable("Unknown 16-byte regclass")::llvm::llvm_unreachable_internal("Unknown 16-byte regclass",
"/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/Target/X86/X86InstrInfo.cpp"
, 6681)
;
6682 }
6683 case 32:
6684 assert(X86::VR256XRegClass.hasSubClassEq(RC) && "Unknown 32-byte regclass")((X86::VR256XRegClass.hasSubClassEq(RC) && "Unknown 32-byte regclass"
) ? static_cast<void> (0) : __assert_fail ("X86::VR256XRegClass.hasSubClassEq(RC) && \"Unknown 32-byte regclass\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/Target/X86/X86InstrInfo.cpp"
, 6684, __PRETTY_FUNCTION__))
;
6685 // If stack is realigned we can use aligned stores.
6686 if (isStackAligned)
6687 return load ?
6688 (HasVLX ? X86::VMOVAPSZ256rm :
6689 HasAVX512 ? X86::VMOVAPSZ256rm_NOVLX :
6690 X86::VMOVAPSYrm) :
6691 (HasVLX ? X86::VMOVAPSZ256mr :
6692 HasAVX512 ? X86::VMOVAPSZ256mr_NOVLX :
6693 X86::VMOVAPSYmr);
6694 else
6695 return load ?
6696 (HasVLX ? X86::VMOVUPSZ256rm :
6697 HasAVX512 ? X86::VMOVUPSZ256rm_NOVLX :
6698 X86::VMOVUPSYrm) :
6699 (HasVLX ? X86::VMOVUPSZ256mr :
6700 HasAVX512 ? X86::VMOVUPSZ256mr_NOVLX :
6701 X86::VMOVUPSYmr);
6702 case 64:
6703 assert(X86::VR512RegClass.hasSubClassEq(RC) && "Unknown 64-byte regclass")((X86::VR512RegClass.hasSubClassEq(RC) && "Unknown 64-byte regclass"
) ? static_cast<void> (0) : __assert_fail ("X86::VR512RegClass.hasSubClassEq(RC) && \"Unknown 64-byte regclass\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/Target/X86/X86InstrInfo.cpp"
, 6703, __PRETTY_FUNCTION__))
;
6704 assert(STI.hasAVX512() && "Using 512-bit register requires AVX512")((STI.hasAVX512() && "Using 512-bit register requires AVX512"
) ? static_cast<void> (0) : __assert_fail ("STI.hasAVX512() && \"Using 512-bit register requires AVX512\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/Target/X86/X86InstrInfo.cpp"
, 6704, __PRETTY_FUNCTION__))
;
6705 if (isStackAligned)
6706 return load ? X86::VMOVAPSZrm : X86::VMOVAPSZmr;
6707 else
6708 return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
6709 }
6710}
6711
6712bool X86InstrInfo::getMemOpBaseRegImmOfs(MachineInstr &MemOp, unsigned &BaseReg,
6713 int64_t &Offset,
6714 const TargetRegisterInfo *TRI) const {
6715 const MCInstrDesc &Desc = MemOp.getDesc();
6716 int MemRefBegin = X86II::getMemoryOperandNo(Desc.TSFlags);
6717 if (MemRefBegin < 0)
6718 return false;
6719
6720 MemRefBegin += X86II::getOperandBias(Desc);
6721
6722 MachineOperand &BaseMO = MemOp.getOperand(MemRefBegin + X86::AddrBaseReg);
6723 if (!BaseMO.isReg()) // Can be an MO_FrameIndex
6724 return false;
6725
6726 BaseReg = BaseMO.getReg();
6727 if (MemOp.getOperand(MemRefBegin + X86::AddrScaleAmt).getImm() != 1)
6728 return false;
6729
6730 if (MemOp.getOperand(MemRefBegin + X86::AddrIndexReg).getReg() !=
6731 X86::NoRegister)
6732 return false;
6733
6734 const MachineOperand &DispMO = MemOp.getOperand(MemRefBegin + X86::AddrDisp);
6735
6736 // Displacement can be symbolic
6737 if (!DispMO.isImm())
6738 return false;
6739
6740 Offset = DispMO.getImm();
6741
6742 return true;
6743}
6744
6745static unsigned getStoreRegOpcode(unsigned SrcReg,
6746 const TargetRegisterClass *RC,
6747 bool isStackAligned,
6748 const X86Subtarget &STI) {
6749 return getLoadStoreRegOpcode(SrcReg, RC, isStackAligned, STI, false);
6750}
6751
6752
6753static unsigned getLoadRegOpcode(unsigned DestReg,
6754 const TargetRegisterClass *RC,
6755 bool isStackAligned,
6756 const X86Subtarget &STI) {
6757 return getLoadStoreRegOpcode(DestReg, RC, isStackAligned, STI, true);
6758}
6759
6760void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
6761 MachineBasicBlock::iterator MI,
6762 unsigned SrcReg, bool isKill, int FrameIdx,
6763 const TargetRegisterClass *RC,
6764 const TargetRegisterInfo *TRI) const {
6765 const MachineFunction &MF = *MBB.getParent();
6766 assert(MF.getFrameInfo().getObjectSize(FrameIdx) >= TRI->getSpillSize(*RC) &&((MF.getFrameInfo().getObjectSize(FrameIdx) >= TRI->getSpillSize
(*RC) && "Stack slot too small for store") ? static_cast
<void> (0) : __assert_fail ("MF.getFrameInfo().getObjectSize(FrameIdx) >= TRI->getSpillSize(*RC) && \"Stack slot too small for store\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/Target/X86/X86InstrInfo.cpp"
, 6767, __PRETTY_FUNCTION__))
6767 "Stack slot too small for store")((MF.getFrameInfo().getObjectSize(FrameIdx) >= TRI->getSpillSize
(*RC) && "Stack slot too small for store") ? static_cast
<void> (0) : __assert_fail ("MF.getFrameInfo().getObjectSize(FrameIdx) >= TRI->getSpillSize(*RC) && \"Stack slot too small for store\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/Target/X86/X86InstrInfo.cpp"
, 6767, __PRETTY_FUNCTION__))
;
6768 unsigned Alignment = std::max<uint32_t>(TRI->getSpillSize(*RC), 16);
6769 bool isAligned =
6770 (Subtarget.getFrameLowering()->getStackAlignment() >= Alignment) ||
6771 RI.canRealignStack(MF);
6772 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
6773 DebugLoc DL = MBB.findDebugLoc(MI);
6774 addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
6775 .addReg(SrcReg, getKillRegState(isKill));
6776}
6777
6778void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
6779 bool isKill,
6780 SmallVectorImpl<MachineOperand> &Addr,
6781 const TargetRegisterClass *RC,
6782 MachineInstr::mmo_iterator MMOBegin,
6783 MachineInstr::mmo_iterator MMOEnd,
6784 SmallVectorImpl<MachineInstr*> &NewMIs) const {
6785 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
6786 unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*RC), 16);
6787 bool isAligned = MMOBegin != MMOEnd &&
6788 (*MMOBegin)->getAlignment() >= Alignment;
6789 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
6790 DebugLoc DL;
6791 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
6792 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
6793 MIB.add(Addr[i]);
6794 MIB.addReg(SrcReg, getKillRegState(isKill));
6795 (*MIB).setMemRefs(MMOBegin, MMOEnd);
6796 NewMIs.push_back(MIB);
6797}
6798
6799
6800void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
6801 MachineBasicBlock::iterator MI,
6802 unsigned DestReg, int FrameIdx,
6803 const TargetRegisterClass *RC,
6804 const TargetRegisterInfo *TRI) const {
6805 const MachineFunction &MF = *MBB.getParent();
6806 unsigned Alignment = std::max<uint32_t>(TRI->getSpillSize(*RC), 16);
6807 bool isAligned =
6808 (Subtarget.getFrameLowering()->getStackAlignment() >= Alignment) ||
6809 RI.canRealignStack(MF);
6810 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
6811 DebugLoc DL = MBB.findDebugLoc(MI);
6812 addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
6813}
6814
6815void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
6816 SmallVectorImpl<MachineOperand> &Addr,
6817 const TargetRegisterClass *RC,
6818 MachineInstr::mmo_iterator MMOBegin,
6819 MachineInstr::mmo_iterator MMOEnd,
6820 SmallVectorImpl<MachineInstr*> &NewMIs) const {
6821 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
6822 unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*RC), 16);
6823 bool isAligned = MMOBegin != MMOEnd &&
6824 (*MMOBegin)->getAlignment() >= Alignment;
6825 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
6826 DebugLoc DL;
6827 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
6828 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
6829 MIB.add(Addr[i]);
6830 (*MIB).setMemRefs(MMOBegin, MMOEnd);
6831 NewMIs.push_back(MIB);
6832}
6833
6834bool X86InstrInfo::analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
6835 unsigned &SrcReg2, int &CmpMask,
6836 int &CmpValue) const {
6837 switch (MI.getOpcode()) {
6838 default: break;
6839 case X86::CMP64ri32:
6840 case X86::CMP64ri8:
6841 case X86::CMP32ri:
6842 case X86::CMP32ri8:
6843 case X86::CMP16ri:
6844 case X86::CMP16ri8:
6845 case X86::CMP8ri:
6846 SrcReg = MI.getOperand(0).getReg();
6847 SrcReg2 = 0;
6848 if (MI.getOperand(1).isImm()) {
6849 CmpMask = ~0;
6850 CmpValue = MI.getOperand(1).getImm();
6851 } else {
6852 CmpMask = CmpValue = 0;
6853 }
6854 return true;
6855 // A SUB can be used to perform comparison.
6856 case X86::SUB64rm:
6857 case X86::SUB32rm:
6858 case X86::SUB16rm:
6859 case X86::SUB8rm:
6860 SrcReg = MI.getOperand(1).getReg();
6861 SrcReg2 = 0;
6862 CmpMask = 0;
6863 CmpValue = 0;
6864 return true;
6865 case X86::SUB64rr:
6866 case X86::SUB32rr:
6867 case X86::SUB16rr:
6868 case X86::SUB8rr:
6869 SrcReg = MI.getOperand(1).getReg();
6870 SrcReg2 = MI.getOperand(2).getReg();
6871 CmpMask = 0;
6872 CmpValue = 0;
6873 return true;
6874 case X86::SUB64ri32:
6875 case X86::SUB64ri8:
6876 case X86::SUB32ri:
6877 case X86::SUB32ri8:
6878 case X86::SUB16ri:
6879 case X86::SUB16ri8:
6880 case X86::SUB8ri:
6881 SrcReg = MI.getOperand(1).getReg();
6882 SrcReg2 = 0;
6883 if (MI.getOperand(2).isImm()) {
6884 CmpMask = ~0;
6885 CmpValue = MI.getOperand(2).getImm();
6886 } else {
6887 CmpMask = CmpValue = 0;
6888 }
6889 return true;
6890 case X86::CMP64rr:
6891 case X86::CMP32rr:
6892 case X86::CMP16rr:
6893 case X86::CMP8rr:
6894 SrcReg = MI.getOperand(0).getReg();
6895 SrcReg2 = MI.getOperand(1).getReg();
6896 CmpMask = 0;
6897 CmpValue = 0;
6898 return true;
6899 case X86::TEST8rr:
6900 case X86::TEST16rr:
6901 case X86::TEST32rr:
6902 case X86::TEST64rr:
6903 SrcReg = MI.getOperand(0).getReg();
6904 if (MI.getOperand(1).getReg() != SrcReg)
6905 return false;
6906 // Compare against zero.
6907 SrcReg2 = 0;
6908 CmpMask = ~0;
6909 CmpValue = 0;
6910 return true;
6911 }
6912 return false;
6913}
6914
6915/// Check whether the first instruction, whose only
6916/// purpose is to update flags, can be made redundant.
6917/// CMPrr can be made redundant by SUBrr if the operands are the same.
6918/// This function can be extended later on.
6919/// SrcReg, SrcRegs: register operands for FlagI.
6920/// ImmValue: immediate for FlagI if it takes an immediate.
6921inline static bool isRedundantFlagInstr(MachineInstr &FlagI, unsigned SrcReg,
6922 unsigned SrcReg2, int ImmMask,
6923 int ImmValue, MachineInstr &OI) {
6924 if (((FlagI.getOpcode() == X86::CMP64rr && OI.getOpcode() == X86::SUB64rr) ||
6925 (FlagI.getOpcode() == X86::CMP32rr && OI.getOpcode() == X86::SUB32rr) ||
6926 (FlagI.getOpcode() == X86::CMP16rr && OI.getOpcode() == X86::SUB16rr) ||
6927 (FlagI.getOpcode() == X86::CMP8rr && OI.getOpcode() == X86::SUB8rr)) &&
6928 ((OI.getOperand(1).getReg() == SrcReg &&
6929 OI.getOperand(2).getReg() == SrcReg2) ||
6930 (OI.getOperand(1).getReg() == SrcReg2 &&
6931 OI.getOperand(2).getReg() == SrcReg)))
6932 return true;
6933
6934 if (ImmMask != 0 &&
6935 ((FlagI.getOpcode() == X86::CMP64ri32 &&
6936 OI.getOpcode() == X86::SUB64ri32) ||
6937 (FlagI.getOpcode() == X86::CMP64ri8 &&
6938 OI.getOpcode() == X86::SUB64ri8) ||
6939 (FlagI.getOpcode() == X86::CMP32ri && OI.getOpcode() == X86::SUB32ri) ||
6940 (FlagI.getOpcode() == X86::CMP32ri8 &&
6941 OI.getOpcode() == X86::SUB32ri8) ||
6942 (FlagI.getOpcode() == X86::CMP16ri && OI.getOpcode() == X86::SUB16ri) ||
6943 (FlagI.getOpcode() == X86::CMP16ri8 &&
6944 OI.getOpcode() == X86::SUB16ri8) ||
6945 (FlagI.getOpcode() == X86::CMP8ri && OI.getOpcode() == X86::SUB8ri)) &&
6946 OI.getOperand(1).getReg() == SrcReg &&
6947 OI.getOperand(2).getImm() == ImmValue)
6948 return true;
6949 return false;
6950}
6951
6952/// Check whether the definition can be converted
6953/// to remove a comparison against zero.
6954inline static bool isDefConvertible(MachineInstr &MI) {
6955 switch (MI.getOpcode()) {
6956 default: return false;
6957
6958 // The shift instructions only modify ZF if their shift count is non-zero.
6959 // N.B.: The processor truncates the shift count depending on the encoding.
6960 case X86::SAR8ri: case X86::SAR16ri: case X86::SAR32ri:case X86::SAR64ri:
6961 case X86::SHR8ri: case X86::SHR16ri: case X86::SHR32ri:case X86::SHR64ri:
6962 return getTruncatedShiftCount(MI, 2) != 0;
6963
6964 // Some left shift instructions can be turned into LEA instructions but only
6965 // if their flags aren't used. Avoid transforming such instructions.
6966 case X86::SHL8ri: case X86::SHL16ri: case X86::SHL32ri:case X86::SHL64ri:{
6967 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
6968 if (isTruncatedShiftCountForLEA(ShAmt)) return false;
6969 return ShAmt != 0;
6970 }
6971
6972 case X86::SHRD16rri8:case X86::SHRD32rri8:case X86::SHRD64rri8:
6973 case X86::SHLD16rri8:case X86::SHLD32rri8:case X86::SHLD64rri8:
6974 return getTruncatedShiftCount(MI, 3) != 0;
6975
6976 case X86::SUB64ri32: case X86::SUB64ri8: case X86::SUB32ri:
6977 case X86::SUB32ri8: case X86::SUB16ri: case X86::SUB16ri8:
6978 case X86::SUB8ri: case X86::SUB64rr: case X86::SUB32rr:
6979 case X86::SUB16rr: case X86::SUB8rr: case X86::SUB64rm:
6980 case X86::SUB32rm: case X86::SUB16rm: case X86::SUB8rm:
6981 case X86::DEC64r: case X86::DEC32r: case X86::DEC16r: case X86::DEC8r:
6982 case X86::ADD64ri32: case X86::ADD64ri8: case X86::ADD32ri:
6983 case X86::ADD32ri8: case X86::ADD16ri: case X86::ADD16ri8:
6984 case X86::ADD8ri: case X86::ADD64rr: case X86::ADD32rr:
6985 case X86::ADD16rr: case X86::ADD8rr: case X86::ADD64rm:
6986 case X86::ADD32rm: case X86::ADD16rm: case X86::ADD8rm:
6987 case X86::INC64r: case X86::INC32r: case X86::INC16r: case X86::INC8r:
6988 case X86::AND64ri32: case X86::AND64ri8: case X86::AND32ri:
6989 case X86::AND32ri8: case X86::AND16ri: case X86::AND16ri8:
6990 case X86::AND8ri: case X86::AND64rr: case X86::AND32rr:
6991 case X86::AND16rr: case X86::AND8rr: case X86::AND64rm:
6992 case X86::AND32rm: case X86::AND16rm: case X86::AND8rm:
6993 case X86::XOR64ri32: case X86::XOR64ri8: case X86::XOR32ri:
6994 case X86::XOR32ri8: case X86::XOR16ri: case X86::XOR16ri8:
6995 case X86::XOR8ri: case X86::XOR64rr: case X86::XOR32rr:
6996 case X86::XOR16rr: case X86::XOR8rr: case X86::XOR64rm:
6997 case X86::XOR32rm: case X86::XOR16rm: case X86::XOR8rm:
6998 case X86::OR64ri32: case X86::OR64ri8: case X86::OR32ri:
6999 case X86::OR32ri8: case X86::OR16ri: case X86::OR16ri8:
7000 case X86::OR8ri: case X86::OR64rr: case X86::OR32rr:
7001 case X86::OR16rr: case X86::OR8rr: case X86::OR64rm:
7002 case X86::OR32rm: case X86::OR16rm: case X86::OR8rm:
7003 case X86::NEG8r: case X86::NEG16r: case X86::NEG32r: case X86::NEG64r:
7004 case X86::SAR8r1: case X86::SAR16r1: case X86::SAR32r1:case X86::SAR64r1:
7005 case X86::SHR8r1: case X86::SHR16r1: case X86::SHR32r1:case X86::SHR64r1:
7006 case X86::SHL8r1: case X86::SHL16r1: case X86::SHL32r1:case X86::SHL64r1:
7007 case X86::ADC32ri: case X86::ADC32ri8:
7008 case X86::ADC32rr: case X86::ADC64ri32:
7009 case X86::ADC64ri8: case X86::ADC64rr:
7010 case X86::SBB32ri: case X86::SBB32ri8:
7011 case X86::SBB32rr: case X86::SBB64ri32:
7012 case X86::SBB64ri8: case X86::SBB64rr:
7013 case X86::ANDN32rr: case X86::ANDN32rm:
7014 case X86::ANDN64rr: case X86::ANDN64rm:
7015 case X86::BEXTR32rr: case X86::BEXTR64rr:
7016 case X86::BEXTR32rm: case X86::BEXTR64rm:
7017 case X86::BLSI32rr: case X86::BLSI32rm:
7018 case X86::BLSI64rr: case X86::BLSI64rm:
7019 case X86::BLSMSK32rr:case X86::BLSMSK32rm:
7020 case X86::BLSMSK64rr:case X86::BLSMSK64rm:
7021 case X86::BLSR32rr: case X86::BLSR32rm:
7022 case X86::BLSR64rr: case X86::BLSR64rm:
7023 case X86::BZHI32rr: case X86::BZHI32rm:
7024 case X86::BZHI64rr: case X86::BZHI64rm:
7025 case X86::LZCNT16rr: case X86::LZCNT16rm:
7026 case X86::LZCNT32rr: case X86::LZCNT32rm:
7027 case X86::LZCNT64rr: case X86::LZCNT64rm:
7028 case X86::POPCNT16rr:case X86::POPCNT16rm:
7029 case X86::POPCNT32rr:case X86::POPCNT32rm:
7030 case X86::POPCNT64rr:case X86::POPCNT64rm:
7031 case X86::TZCNT16rr: case X86::TZCNT16rm:
7032 case X86::TZCNT32rr: case X86::TZCNT32rm:
7033 case X86::TZCNT64rr: case X86::TZCNT64rm:
7034 return true;
7035 }
7036}
7037
7038/// Check whether the use can be converted to remove a comparison against zero.
7039static X86::CondCode isUseDefConvertible(MachineInstr &MI) {
7040 switch (MI.getOpcode()) {
7041 default: return X86::COND_INVALID;
7042 case X86::LZCNT16rr: case X86::LZCNT16rm:
7043 case X86::LZCNT32rr: case X86::LZCNT32rm:
7044 case X86::LZCNT64rr: case X86::LZCNT64rm:
7045 return X86::COND_B;
7046 case X86::POPCNT16rr:case X86::POPCNT16rm:
7047 case X86::POPCNT32rr:case X86::POPCNT32rm:
7048 case X86::POPCNT64rr:case X86::POPCNT64rm:
7049 return X86::COND_E;
7050 case X86::TZCNT16rr: case X86::TZCNT16rm:
7051 case X86::TZCNT32rr: case X86::TZCNT32rm:
7052 case X86::TZCNT64rr: case X86::TZCNT64rm:
7053 return X86::COND_B;
7054 }
7055}
7056
7057/// Check if there exists an earlier instruction that
7058/// operates on the same source operands and sets flags in the same way as
7059/// Compare; remove Compare if possible.
7060bool X86InstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
7061 unsigned SrcReg2, int CmpMask,
7062 int CmpValue,
7063 const MachineRegisterInfo *MRI) const {
7064 // Check whether we can replace SUB with CMP.
7065 unsigned NewOpcode = 0;
7066 switch (CmpInstr.getOpcode()) {
7067 default: break;
7068 case X86::SUB64ri32:
7069 case X86::SUB64ri8:
7070 case X86::SUB32ri:
7071 case X86::SUB32ri8:
7072 case X86::SUB16ri:
7073 case X86::SUB16ri8:
7074 case X86::SUB8ri:
7075 case X86::SUB64rm:
7076 case X86::SUB32rm:
7077 case X86::SUB16rm:
7078 case X86::SUB8rm:
7079 case X86::SUB64rr:
7080 case X86::SUB32rr:
7081 case X86::SUB16rr:
7082 case X86::SUB8rr: {
7083 if (!MRI->use_nodbg_empty(CmpInstr.getOperand(0).getReg()))
7084 return false;
7085 // There is no use of the destination register, we can replace SUB with CMP.
7086 switch (CmpInstr.getOpcode()) {
7087 default: llvm_unreachable("Unreachable!")::llvm::llvm_unreachable_internal("Unreachable!", "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/Target/X86/X86InstrInfo.cpp"
, 7087)
;
7088 case X86::SUB64rm: NewOpcode = X86::CMP64rm; break;
7089 case X86::SUB32rm: NewOpcode = X86::CMP32rm; break;
7090 case X86::SUB16rm: NewOpcode = X86::CMP16rm; break;
7091 case X86::SUB8rm: NewOpcode = X86::CMP8rm; break;
7092 case X86::SUB64rr: NewOpcode = X86::CMP64rr; break;
7093 case X86::SUB32rr: NewOpcode = X86::CMP32rr; break;
7094 case X86::SUB16rr: NewOpcode = X86::CMP16rr; break;
7095 case X86::SUB8rr: NewOpcode = X86::CMP8rr; break;
7096 case X86::SUB64ri32: NewOpcode = X86::CMP64ri32; break;
7097 case X86::SUB64ri8: NewOpcode = X86::CMP64ri8; break;
7098 case X86::SUB32ri: NewOpcode = X86::CMP32ri; break;
7099 case X86::SUB32ri8: NewOpcode = X86::CMP32ri8; break;
7100 case X86::SUB16ri: NewOpcode = X86::CMP16ri; break;
7101 case X86::SUB16ri8: NewOpcode = X86::CMP16ri8; break;
7102 case X86::SUB8ri: NewOpcode = X86::CMP8ri; break;
7103 }
7104 CmpInstr.setDesc(get(NewOpcode));
7105 CmpInstr.RemoveOperand(0);
7106 // Fall through to optimize Cmp if Cmp is CMPrr or CMPri.
7107 if (NewOpcode == X86::CMP64rm || NewOpcode == X86::CMP32rm ||
7108 NewOpcode == X86::CMP16rm || NewOpcode == X86::CMP8rm)
7109 return false;
7110 }
7111 }
7112
7113 // Get the unique definition of SrcReg.
7114 MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
7115 if (!MI) return false;
7116
7117 // CmpInstr is the first instruction of the BB.
7118 MachineBasicBlock::iterator I = CmpInstr, Def = MI;
7119
7120 // If we are comparing against zero, check whether we can use MI to update
7121 // EFLAGS. If MI is not in the same BB as CmpInstr, do not optimize.
7122 bool IsCmpZero = (CmpMask != 0 && CmpValue == 0);
7123 if (IsCmpZero && MI->getParent() != CmpInstr.getParent())
7124 return false;
7125
7126 // If we have a use of the source register between the def and our compare
7127 // instruction we can eliminate the compare iff the use sets EFLAGS in the
7128 // right way.
7129 bool ShouldUpdateCC = false;
7130 X86::CondCode NewCC = X86::COND_INVALID;
7131 if (IsCmpZero && !isDefConvertible(*MI)) {
7132 // Scan forward from the use until we hit the use we're looking for or the
7133 // compare instruction.
7134 for (MachineBasicBlock::iterator J = MI;; ++J) {
7135 // Do we have a convertible instruction?
7136 NewCC = isUseDefConvertible(*J);
7137 if (NewCC != X86::COND_INVALID && J->getOperand(1).isReg() &&
7138 J->getOperand(1).getReg() == SrcReg) {
7139 assert(J->definesRegister(X86::EFLAGS) && "Must be an EFLAGS def!")((J->definesRegister(X86::EFLAGS) && "Must be an EFLAGS def!"
) ? static_cast<void> (0) : __assert_fail ("J->definesRegister(X86::EFLAGS) && \"Must be an EFLAGS def!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/Target/X86/X86InstrInfo.cpp"
, 7139, __PRETTY_FUNCTION__))
;
7140 ShouldUpdateCC = true; // Update CC later on.
7141 // This is not a def of SrcReg, but still a def of EFLAGS. Keep going
7142 // with the new def.
7143 Def = J;
7144 MI = &*Def;
7145 break;
7146 }
7147
7148 if (J == I)
7149 return false;
7150 }
7151 }
7152
7153 // We are searching for an earlier instruction that can make CmpInstr
7154 // redundant and that instruction will be saved in Sub.
7155 MachineInstr *Sub = nullptr;
7156 const TargetRegisterInfo *TRI = &getRegisterInfo();
7157
7158 // We iterate backward, starting from the instruction before CmpInstr and
7159 // stop when reaching the definition of a source register or done with the BB.
7160 // RI points to the instruction before CmpInstr.
7161 // If the definition is in this basic block, RE points to the definition;
7162 // otherwise, RE is the rend of the basic block.
7163 MachineBasicBlock::reverse_iterator
7164 RI = ++I.getReverse(),
7165 RE = CmpInstr.getParent() == MI->getParent()
7166 ? Def.getReverse() /* points to MI */
7167 : CmpInstr.getParent()->rend();
7168 MachineInstr *Movr0Inst = nullptr;
7169 for (; RI != RE; ++RI) {
7170 MachineInstr &Instr = *RI;
7171 // Check whether CmpInstr can be made redundant by the current instruction.
7172 if (!IsCmpZero && isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpMask,
7173 CmpValue, Instr)) {
7174 Sub = &Instr;
7175 break;
7176 }
7177
7178 if (Instr.modifiesRegister(X86::EFLAGS, TRI) ||
7179 Instr.readsRegister(X86::EFLAGS, TRI)) {
7180 // This instruction modifies or uses EFLAGS.
7181
7182 // MOV32r0 etc. are implemented with xor which clobbers condition code.
7183 // They are safe to move up, if the definition to EFLAGS is dead and
7184 // earlier instructions do not read or write EFLAGS.
7185 if (!Movr0Inst && Instr.getOpcode() == X86::MOV32r0 &&
7186 Instr.registerDefIsDead(X86::EFLAGS, TRI)) {
7187 Movr0Inst = &Instr;
7188 continue;
7189 }
7190
7191 // We can't remove CmpInstr.
7192 return false;
7193 }
7194 }
7195
7196 // Return false if no candidates exist.
7197 if (!IsCmpZero && !Sub)
7198 return false;
7199
7200 bool IsSwapped = (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
7201 Sub->getOperand(2).getReg() == SrcReg);
7202
7203 // Scan forward from the instruction after CmpInstr for uses of EFLAGS.
7204 // It is safe to remove CmpInstr if EFLAGS is redefined or killed.
7205 // If we are done with the basic block, we need to check whether EFLAGS is
7206 // live-out.
7207 bool IsSafe = false;
7208 SmallVector<std::pair<MachineInstr*, unsigned /*NewOpc*/>, 4> OpsToUpdate;
7209 MachineBasicBlock::iterator E = CmpInstr.getParent()->end();
7210 for (++I; I != E; ++I) {
7211 const MachineInstr &Instr = *I;
7212 bool ModifyEFLAGS = Instr.modifiesRegister(X86::EFLAGS, TRI);
7213 bool UseEFLAGS = Instr.readsRegister(X86::EFLAGS, TRI);
7214 // We should check the usage if this instruction uses and updates EFLAGS.
7215 if (!UseEFLAGS && ModifyEFLAGS) {
7216 // It is safe to remove CmpInstr if EFLAGS is updated again.
7217 IsSafe = true;
7218 break;
7219 }
7220 if (!UseEFLAGS && !ModifyEFLAGS)
7221 continue;
7222
7223 // EFLAGS is used by this instruction.
7224 X86::CondCode OldCC = X86::COND_INVALID;
7225 bool OpcIsSET = false;
7226 if (IsCmpZero || IsSwapped) {
7227 // We decode the condition code from opcode.
7228 if (Instr.isBranch())
7229 OldCC = getCondFromBranchOpc(Instr.getOpcode());
7230 else {
7231 OldCC = getCondFromSETOpc(Instr.getOpcode());
7232 if (OldCC != X86::COND_INVALID)
7233 OpcIsSET = true;
7234 else
7235 OldCC = X86::getCondFromCMovOpc(Instr.getOpcode());
7236 }
7237 if (OldCC == X86::COND_INVALID) return false;
7238 }
7239 if (IsCmpZero) {
7240 switch (OldCC) {
7241 default: break;
7242 case X86::COND_A: case X86::COND_AE:
7243 case X86::COND_B: case X86::COND_BE:
7244 case X86::COND_G: case X86::COND_GE:
7245 case X86::COND_L: case X86::COND_LE:
7246 case X86::COND_O: case X86::COND_NO:
7247 // CF and OF are used, we can't perform this optimization.
7248 return false;
7249 }
7250
7251 // If we're updating the condition code check if we have to reverse the
7252 // condition.
7253 if (ShouldUpdateCC)
7254 switch (OldCC) {
7255 default:
7256 return false;
7257 case X86::COND_E:
7258 break;
7259 case X86::COND_NE:
7260 NewCC = GetOppositeBranchCondition(NewCC);
7261 break;
7262 }
7263 } else if (IsSwapped) {
7264 // If we have SUB(r1, r2) and CMP(r2, r1), the condition code needs
7265 // to be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
7266 // We swap the condition code and synthesize the new opcode.
7267 NewCC = getSwappedCondition(OldCC);
7268 if (NewCC == X86::COND_INVALID) return false;
7269 }
7270
7271 if ((ShouldUpdateCC || IsSwapped) && NewCC != OldCC) {
7272 // Synthesize the new opcode.
7273 bool HasMemoryOperand = Instr.hasOneMemOperand();
7274 unsigned NewOpc;
7275 if (Instr.isBranch())
7276 NewOpc = GetCondBranchFromCond(NewCC);
7277 else if(OpcIsSET)
7278 NewOpc = getSETFromCond(NewCC, HasMemoryOperand);
7279 else {
7280 unsigned DstReg = Instr.getOperand(0).getReg();
7281 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg);
7282 NewOpc = getCMovFromCond(NewCC, TRI->getRegSizeInBits(*DstRC)/8,
7283 HasMemoryOperand);
7284 }
7285
7286 // Push the MachineInstr to OpsToUpdate.
7287 // If it is safe to remove CmpInstr, the condition code of these
7288 // instructions will be modified.
7289 OpsToUpdate.push_back(std::make_pair(&*I, NewOpc));
7290 }
7291 if (ModifyEFLAGS || Instr.killsRegister(X86::EFLAGS, TRI)) {
7292 // It is safe to remove CmpInstr if EFLAGS is updated again or killed.
7293 IsSafe = true;
7294 break;
7295 }
7296 }
7297
7298 // If EFLAGS is not killed nor re-defined, we should check whether it is
7299 // live-out. If it is live-out, do not optimize.
7300 if ((IsCmpZero || IsSwapped) && !IsSafe) {
7301 MachineBasicBlock *MBB = CmpInstr.getParent();
7302 for (MachineBasicBlock *Successor : MBB->successors())
7303 if (Successor->isLiveIn(X86::EFLAGS))
7304 return false;
7305 }
7306
7307 // The instruction to be updated is either Sub or MI.
7308 Sub = IsCmpZero ? MI : Sub;
7309 // Move Movr0Inst to the appropriate place before Sub.
7310 if (Movr0Inst) {
7311 // Look backwards until we find a def that doesn't use the current EFLAGS.
7312 Def = Sub;
7313 MachineBasicBlock::reverse_iterator InsertI = Def.getReverse(),
7314 InsertE = Sub->getParent()->rend();
7315 for (; InsertI != InsertE; ++InsertI) {
7316 MachineInstr *Instr = &*InsertI;
7317 if (!Instr->readsRegister(X86::EFLAGS, TRI) &&
7318 Instr->modifiesRegister(X86::EFLAGS, TRI)) {
7319 Sub->getParent()->remove(Movr0Inst);
7320 Instr->getParent()->insert(MachineBasicBlock::iterator(Instr),
7321 Movr0Inst);
7322 break;
7323 }
7324 }
7325 if (InsertI == InsertE)
7326 return false;
7327 }
7328
7329 // Make sure Sub instruction defines EFLAGS and mark the def live.
7330 unsigned i = 0, e = Sub->getNumOperands();
7331 for (; i != e; ++i) {
7332 MachineOperand &MO = Sub->getOperand(i);
7333 if (MO.isReg() && MO.isDef() && MO.getReg() == X86::EFLAGS) {
7334 MO.setIsDead(false);
7335 break;
7336 }
7337 }
7338 assert(i != e && "Unable to locate a def EFLAGS operand")((i != e && "Unable to locate a def EFLAGS operand") ?
static_cast<void> (0) : __assert_fail ("i != e && \"Unable to locate a def EFLAGS operand\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/Target/X86/X86InstrInfo.cpp"
, 7338, __PRETTY_FUNCTION__))
;
7339
7340 CmpInstr.eraseFromParent();
7341
7342 // Modify the condition code of instructions in OpsToUpdate.
7343 for (auto &Op : OpsToUpdate)
7344 Op.first->setDesc(get(Op.second));
7345 return true;
7346}
7347
7348/// Try to remove the load by folding it to a register
7349/// operand at the use. We fold the load instructions if load defines a virtual
7350/// register, the virtual register is used once in the same BB, and the
7351/// instructions in-between do not load or store, and have no side effects.
7352MachineInstr *X86InstrInfo::optimizeLoadInstr(MachineInstr &MI,
7353 const MachineRegisterInfo *MRI,
7354 unsigned &FoldAsLoadDefReg,
7355 MachineInstr *&DefMI) const {
7356 // Check whether we can move DefMI here.
7357 DefMI = MRI->getVRegDef(FoldAsLoadDefReg);
7358 assert(DefMI)((DefMI) ? static_cast<void> (0) : __assert_fail ("DefMI"
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/Target/X86/X86InstrInfo.cpp"
, 7358, __PRETTY_FUNCTION__))
;
7359 bool SawStore = false;
7360 if (!DefMI->isSafeToMove(nullptr, SawStore))
7361 return nullptr;
7362
7363 // Collect information about virtual register operands of MI.
7364 SmallVector<unsigned, 1> SrcOperandIds;
7365 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
7366 MachineOperand &MO = MI.getOperand(i);
7367 if (!MO.isReg())
7368 continue;
7369 unsigned Reg = MO.getReg();
7370 if (Reg != FoldAsLoadDefReg)
7371 continue;
7372 // Do not fold if we have a subreg use or a def.
7373 if (MO.getSubReg() || MO.isDef())
7374 return nullptr;
7375 SrcOperandIds.push_back(i);
7376 }
7377 if (SrcOperandIds.empty())
7378 return nullptr;
7379
7380 // Check whether we can fold the def into SrcOperandId.
7381 if (MachineInstr *FoldMI = foldMemoryOperand(MI, SrcOperandIds, *DefMI)) {
7382 FoldAsLoadDefReg = 0;
7383 return FoldMI;
7384 }
7385
7386 return nullptr;
7387}
7388
7389/// Expand a single-def pseudo instruction to a two-addr
7390/// instruction with two undef reads of the register being defined.
7391/// This is used for mapping:
7392/// %xmm4 = V_SET0
7393/// to:
7394/// %xmm4 = PXORrr %xmm4<undef>, %xmm4<undef>
7395///
7396static bool Expand2AddrUndef(MachineInstrBuilder &MIB,
7397 const MCInstrDesc &Desc) {
7398 assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.")((Desc.getNumOperands() == 3 && "Expected two-addr instruction."
) ? static_cast<void> (0) : __assert_fail ("Desc.getNumOperands() == 3 && \"Expected two-addr instruction.\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/Target/X86/X86InstrInfo.cpp"
, 7398, __PRETTY_FUNCTION__))
;
7399 unsigned Reg = MIB->getOperand(0).getReg();
7400 MIB->setDesc(Desc);
7401
7402 // MachineInstr::addOperand() will insert explicit operands before any
7403 // implicit operands.
7404 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
7405 // But we don't trust that.
7406 assert(MIB->getOperand(1).getReg() == Reg &&((MIB->getOperand(1).getReg() == Reg && MIB->getOperand
(2).getReg() == Reg && "Misplaced operand") ? static_cast
<void> (0) : __assert_fail ("MIB->getOperand(1).getReg() == Reg && MIB->getOperand(2).getReg() == Reg && \"Misplaced operand\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/Target/X86/X86InstrInfo.cpp"
, 7407, __PRETTY_FUNCTION__))
7407 MIB->getOperand(2).getReg() == Reg && "Misplaced operand")((MIB->getOperand(1).getReg() == Reg && MIB->getOperand
(2).getReg() == Reg && "Misplaced operand") ? static_cast
<void> (0) : __assert_fail ("MIB->getOperand(1).getReg() == Reg && MIB->getOperand(2).getReg() == Reg && \"Misplaced operand\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/Target/X86/X86InstrInfo.cpp"
, 7407, __PRETTY_FUNCTION__))
;
7408 return true;
7409}
7410
7411/// Expand a single-def pseudo instruction to a two-addr
7412/// instruction with two %k0 reads.
7413/// This is used for mapping:
7414/// %k4 = K_SET1
7415/// to:
7416/// %k4 = KXNORrr %k0, %k0
7417static bool Expand2AddrKreg(MachineInstrBuilder &MIB,
7418 const MCInstrDesc &Desc, unsigned Reg) {
7419 assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.")((Desc.getNumOperands() == 3 && "Expected two-addr instruction."
) ? static_cast<void> (0) : __assert_fail ("Desc.getNumOperands() == 3 && \"Expected two-addr instruction.\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/Target/X86/X86InstrInfo.cpp"
, 7419, __PRETTY_FUNCTION__))
;
7420 MIB->setDesc(Desc);
7421 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
7422 return true;
7423}
7424
7425static bool expandMOV32r1(MachineInstrBuilder &MIB, const TargetInstrInfo &TII,
7426 bool MinusOne) {
7427 MachineBasicBlock &MBB = *MIB->getParent();
7428 DebugLoc DL = MIB->getDebugLoc();
7429 unsigned Reg = MIB->getOperand(0).getReg();
7430
7431 // Insert the XOR.
7432 BuildMI(MBB, MIB.getInstr(), DL, TII.get(X86::XOR32rr), Reg)
7433 .addReg(Reg, RegState::Undef)
7434 .addReg(Reg, RegState::Undef);
7435
7436 // Turn the pseudo into an INC or DEC.
7437 MIB->setDesc(TII.get(MinusOne ? X86::DEC32r : X86::INC32r));
7438 MIB.addReg(Reg);
7439
7440 return true;
7441}
7442
7443static bool ExpandMOVImmSExti8(MachineInstrBuilder &MIB,
7444 const TargetInstrInfo &TII,
7445 const X86Subtarget &Subtarget) {
7446 MachineBasicBlock &MBB = *MIB->getParent();
7447 DebugLoc DL = MIB->getDebugLoc();
7448 int64_t Imm = MIB->getOperand(1).getImm();
7449 assert(Imm != 0 && "Using push/pop for 0 is not efficient.")((Imm != 0 && "Using push/pop for 0 is not efficient."
) ? static_cast<void> (0) : __assert_fail ("Imm != 0 && \"Using push/pop for 0 is not efficient.\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/Target/X86/X86InstrInfo.cpp"
, 7449, __PRETTY_FUNCTION__))
;
7450 MachineBasicBlock::iterator I = MIB.getInstr();
7451
7452 int StackAdjustment;
7453
7454 if (Subtarget.is64Bit()) {
7455 assert(MIB->getOpcode() == X86::MOV64ImmSExti8 ||((MIB->getOpcode() == X86::MOV64ImmSExti8 || MIB->getOpcode
() == X86::MOV32ImmSExti8) ? static_cast<void> (0) : __assert_fail
("MIB->getOpcode() == X86::MOV64ImmSExti8 || MIB->getOpcode() == X86::MOV32ImmSExti8"
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/Target/X86/X86InstrInfo.cpp"
, 7456, __PRETTY_FUNCTION__))
7456 MIB->getOpcode() == X86::MOV32ImmSExti8)((MIB->getOpcode() == X86::MOV64ImmSExti8 || MIB->getOpcode
() == X86::MOV32ImmSExti8) ? static_cast<void> (0) : __assert_fail
("MIB->getOpcode() == X86::MOV64ImmSExti8 || MIB->getOpcode() == X86::MOV32ImmSExti8"
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/Target/X86/X86InstrInfo.cpp"
, 7456, __PRETTY_FUNCTION__))
;
7457
7458 // Can't use push/pop lowering if the function might write to the red zone.
7459 X86MachineFunctionInfo *X86FI =
7460 MBB.getParent()->getInfo<X86MachineFunctionInfo>();
7461 if (X86FI->getUsesRedZone()) {
7462 MIB->setDesc(TII.get(MIB->getOpcode() ==
7463 X86::MOV32ImmSExti8 ? X86::MOV32ri : X86::MOV64ri));
7464 return true;
7465 }
7466
7467 // 64-bit mode doesn't have 32-bit push/pop, so use 64-bit operations and
7468 // widen the register if necessary.
7469 StackAdjustment = 8;
7470 BuildMI(MBB, I, DL, TII.get(X86::PUSH64i8)).addImm(Imm);
7471 MIB->setDesc(TII.get(X86::POP64r));
7472 MIB->getOperand(0)
7473 .setReg(getX86SubSuperRegister(MIB->getOperand(0).getReg(), 64));
7474 } else {
7475 assert(MIB->getOpcode() == X86::MOV32ImmSExti8)((MIB->getOpcode() == X86::MOV32ImmSExti8) ? static_cast<
void> (0) : __assert_fail ("MIB->getOpcode() == X86::MOV32ImmSExti8"
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/Target/X86/X86InstrInfo.cpp"
, 7475, __PRETTY_FUNCTION__))
;
7476 StackAdjustment = 4;
7477 BuildMI(MBB, I, DL, TII.get(X86::PUSH32i8)).addImm(Imm);
7478 MIB->setDesc(TII.get(X86::POP32r));
7479 }
7480
7481 // Build CFI if necessary.
7482 MachineFunction &MF = *MBB.getParent();
7483 const X86FrameLowering *TFL = Subtarget.getFrameLowering();
7484 bool IsWin64Prologue = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
7485 bool NeedsDwarfCFI =
7486 !IsWin64Prologue &&
7487 (MF.getMMI().hasDebugInfo() || MF.getFunction()->needsUnwindTableEntry());
7488 bool EmitCFI = !TFL->hasFP(MF) && NeedsDwarfCFI;
7489 if (EmitCFI) {
7490 TFL->BuildCFI(MBB, I, DL,
7491 MCCFIInstruction::createAdjustCfaOffset(nullptr, StackAdjustment));
7492 TFL->BuildCFI(MBB, std::next(I), DL,
7493 MCCFIInstruction::createAdjustCfaOffset(nullptr, -StackAdjustment));
7494 }
7495
7496 return true;
7497}
7498
7499// LoadStackGuard has so far only been implemented for 64-bit MachO. Different
7500// code sequence is needed for other targets.
7501static void expandLoadStackGuard(MachineInstrBuilder &MIB,
7502 const TargetInstrInfo &TII) {
7503 MachineBasicBlock &MBB = *MIB->getParent();
7504 DebugLoc DL = MIB->getDebugLoc();
7505 unsigned Reg = MIB->getOperand(0).getReg();
7506 const GlobalValue *GV =
7507 cast<GlobalValue>((*MIB->memoperands_begin())->getValue());
7508 auto Flags = MachineMemOperand::MOLoad |
7509 MachineMemOperand::MODereferenceable |
7510 MachineMemOperand::MOInvariant;
7511 MachineMemOperand *MMO = MBB.getParent()->getMachineMemOperand(
7512 MachinePointerInfo::getGOT(*MBB.getParent()), Flags, 8, 8);
7513 MachineBasicBlock::iterator I = MIB.getInstr();
7514
7515 BuildMI(MBB, I, DL, TII.get(X86::MOV64rm), Reg).addReg(X86::RIP).addImm(1)
7516 .addReg(0).addGlobalAddress(GV, 0, X86II::MO_GOTPCREL).addReg(0)
7517 .addMemOperand(MMO);
7518 MIB->setDebugLoc(DL);
7519 MIB->setDesc(TII.get(X86::MOV64rm));
7520 MIB.addReg(Reg, RegState::Kill).addImm(1).addReg(0).addImm(0).addReg(0);
7521}
7522
7523// This is used to handle spills for 128/256-bit registers when we have AVX512,
7524// but not VLX. If it uses an extended register we need to use an instruction
7525// that loads the lower 128/256-bit, but is available with only AVX512F.
7526static bool expandNOVLXLoad(MachineInstrBuilder &MIB,
7527 const TargetRegisterInfo *TRI,
7528 const MCInstrDesc &LoadDesc,
7529 const MCInstrDesc &BroadcastDesc,
7530 unsigned SubIdx) {
7531 unsigned DestReg = MIB->getOperand(0).getReg();
7532 // Check if DestReg is XMM16-31 or YMM16-31.
7533 if (TRI->getEncodingValue(DestReg) < 16) {
7534 // We can use a normal VEX encoded load.
7535 MIB->setDesc(LoadDesc);
7536 } else {
7537 // Use a 128/256-bit VBROADCAST instruction.
7538 MIB->setDesc(BroadcastDesc);
7539 // Change the destination to a 512-bit register.
7540 DestReg = TRI->getMatchingSuperReg(DestReg, SubIdx, &X86::VR512RegClass);
7541 MIB->getOperand(0).setReg(DestReg);
7542 }
7543 return true;
7544}
7545
7546// This is used to handle spills for 128/256-bit registers when we have AVX512,
7547// but not VLX. If it uses an extended register we need to use an instruction
7548// that stores the lower 128/256-bit, but is available with only AVX512F.
7549static bool expandNOVLXStore(MachineInstrBuilder &MIB,
7550 const TargetRegisterInfo *TRI,
7551 const MCInstrDesc &StoreDesc,
7552 const MCInstrDesc &ExtractDesc,
7553 unsigned SubIdx) {
7554 unsigned SrcReg = MIB->getOperand(X86::AddrNumOperands).getReg();
7555 // Check if DestReg is XMM16-31 or YMM16-31.
7556 if (TRI->getEncodingValue(SrcReg) < 16) {
7557 // We can use a normal VEX encoded store.
7558 MIB->setDesc(StoreDesc);
7559 } else {
7560 // Use a VEXTRACTF instruction.
7561 MIB->setDesc(ExtractDesc);
7562 // Change the destination to a 512-bit register.
7563 SrcReg = TRI->getMatchingSuperReg(SrcReg, SubIdx, &X86::VR512RegClass);
7564 MIB->getOperand(X86::AddrNumOperands).setReg(SrcReg);
7565 MIB.addImm(0x0); // Append immediate to extract from the lower bits.
7566 }
7567
7568 return true;
7569}
7570bool X86InstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
7571 bool HasAVX = Subtarget.hasAVX();
7572 MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI);
7573 switch (MI.getOpcode()) {
7574 case X86::MOV32r0:
7575 return Expand2AddrUndef(MIB, get(X86::XOR32rr));
7576 case X86::MOV32r1:
7577 return expandMOV32r1(MIB, *this, /*MinusOne=*/ false);
7578 case X86::MOV32r_1:
7579 return expandMOV32r1(MIB, *this, /*MinusOne=*/ true);
7580 case X86::MOV32ImmSExti8:
7581 case X86::MOV64ImmSExti8:
7582 return ExpandMOVImmSExti8(MIB, *this, Subtarget);
7583 case X86::SETB_C8r:
7584 return Expand2AddrUndef(MIB, get(X86::SBB8rr));
7585 case X86::SETB_C16r:
7586 return Expand2AddrUndef(MIB, get(X86::SBB16rr));
7587 case X86::SETB_C32r:
7588 return Expand2AddrUndef(MIB, get(X86::SBB32rr));
7589 case X86::SETB_C64r:
7590 return Expand2AddrUndef(MIB, get(X86::SBB64rr));
7591 case X86::V_SET0:
7592 case X86::FsFLD0SS:
7593 case X86::FsFLD0SD:
7594 return Expand2AddrUndef(MIB, get(HasAVX ? X86::VXORPSrr : X86::XORPSrr));
7595 case X86::AVX_SET0:
7596 assert(HasAVX && "AVX not supported")((HasAVX && "AVX not supported") ? static_cast<void
> (0) : __assert_fail ("HasAVX && \"AVX not supported\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/Target/X86/X86InstrInfo.cpp"
, 7596, __PRETTY_FUNCTION__))
;
7597 return Expand2AddrUndef(MIB, get(X86::VXORPSYrr));
7598 case X86::AVX512_128_SET0:
7599 case X86::AVX512_FsFLD0SS:
7600 case X86::AVX512_FsFLD0SD: {
7601 bool HasVLX = Subtarget.hasVLX();
7602 unsigned SrcReg = MIB->getOperand(0).getReg();
7603 const TargetRegisterInfo *TRI = &getRegisterInfo();
7604 if (HasVLX || TRI->getEncodingValue(SrcReg) < 16)
7605 return Expand2AddrUndef(MIB,
7606 get(HasVLX ? X86::VPXORDZ128rr : X86::VXORPSrr));
7607 // Extended register without VLX. Use a larger XOR.
7608 SrcReg = TRI->getMatchingSuperReg(SrcReg, X86::sub_xmm, &X86::VR512RegClass);
7609 MIB->getOperand(0).setReg(SrcReg);
7610 return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
7611 }
7612 case X86::AVX512_256_SET0: {
7613 bool HasVLX = Subtarget.hasVLX();
7614 unsigned SrcReg = MIB->getOperand(0).getReg();
7615 const TargetRegisterInfo *TRI = &getRegisterInfo();
7616 if (HasVLX || TRI->getEncodingValue(SrcReg) < 16)
7617 return Expand2AddrUndef(MIB,
7618 get(HasVLX ? X86::VPXORDZ256rr : X86::VXORPSYrr));
7619 // Extended register without VLX. Use a larger XOR.
7620 SrcReg = TRI->getMatchingSuperReg(SrcReg, X86::sub_ymm, &X86::VR512RegClass);
7621 MIB->getOperand(0).setReg(SrcReg);
7622 return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
7623 }
7624 case X86::AVX512_512_SET0:
7625 return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
7626 case X86::V_SETALLONES:
7627 return Expand2AddrUndef(MIB, get(HasAVX ? X86::VPCMPEQDrr : X86::PCMPEQDrr));
7628 case X86::AVX2_SETALLONES:
7629 return Expand2AddrUndef(MIB, get(X86::VPCMPEQDYrr));
7630 case X86::AVX1_SETALLONES: {
7631 unsigned Reg = MIB->getOperand(0).getReg();
7632 // VCMPPSYrri with an immediate 0xf should produce VCMPTRUEPS.
7633 MIB->setDesc(get(X86::VCMPPSYrri));
7634 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef).addImm(0xf);
7635 return true;
7636 }
7637 case X86::AVX512_512_SETALLONES: {
7638 unsigned Reg = MIB->getOperand(0).getReg();
7639 MIB->setDesc(get(X86::VPTERNLOGDZrri));
7640 // VPTERNLOGD needs 3 register inputs and an immediate.
7641 // 0xff will return 1s for any input.
7642 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef)
7643 .addReg(Reg, RegState::Undef).addImm(0xff);
7644 return true;
7645 }
7646 case X86::AVX512_512_SEXT_MASK_32:
7647 case X86::AVX512_512_SEXT_MASK_64: {
7648 unsigned Reg = MIB->getOperand(0).getReg();
7649 unsigned MaskReg = MIB->getOperand(1).getReg();
7650 unsigned MaskState = getRegState(MIB->getOperand(1));
7651 unsigned Opc = (MI.getOpcode() == X86::AVX512_512_SEXT_MASK_64) ?
7652 X86::VPTERNLOGQZrrikz : X86::VPTERNLOGDZrrikz;
7653 MI.RemoveOperand(1);
7654 MIB->setDesc(get(Opc));
7655 // VPTERNLOG needs 3 register inputs and an immediate.
7656 // 0xff will return 1s for any input.
7657 MIB.addReg(Reg, RegState::Undef).addReg(MaskReg, MaskState)
7658 .addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef).addImm(0xff);
7659 return true;
7660 }
7661 case X86::VMOVAPSZ128rm_NOVLX:
7662 return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVAPSrm),
7663 get(X86::VBROADCASTF32X4rm), X86::sub_xmm);
7664 case X86::VMOVUPSZ128rm_NOVLX:
7665 return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVUPSrm),
7666 get(X86::VBROADCASTF32X4rm), X86::sub_xmm);
7667 case X86::VMOVAPSZ256rm_NOVLX:
7668 return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVAPSYrm),
7669 get(X86::VBROADCASTF64X4rm), X86::sub_ymm);
7670 case X86::VMOVUPSZ256rm_NOVLX:
7671 return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVUPSYrm),
7672 get(X86::VBROADCASTF64X4rm), X86::sub_ymm);
7673 case X86::VMOVAPSZ128mr_NOVLX:
7674 return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVAPSmr),
7675 get(X86::VEXTRACTF32x4Zmr), X86::sub_xmm);
7676 case X86::VMOVUPSZ128mr_NOVLX:
7677 return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVUPSmr),
7678 get(X86::VEXTRACTF32x4Zmr), X86::sub_xmm);
7679 case X86::VMOVAPSZ256mr_NOVLX:
7680 return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVAPSYmr),
7681 get(X86::VEXTRACTF64x4Zmr), X86::sub_ymm);
7682 case X86::VMOVUPSZ256mr_NOVLX:
7683 return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVUPSYmr),
7684 get(X86::VEXTRACTF64x4Zmr), X86::sub_ymm);
7685 case X86::TEST8ri_NOREX:
7686 MI.setDesc(get(X86::TEST8ri));
7687 return true;
7688 case X86::MOV32ri64:
7689 MI.setDesc(get(X86::MOV32ri));
7690 return true;
7691
7692 // KNL does not recognize dependency-breaking idioms for mask registers,
7693 // so kxnor %k1, %k1, %k2 has a RAW dependence on %k1.
7694 // Using %k0 as the undef input register is a performance heuristic based
7695 // on the assumption that %k0 is used less frequently than the other mask
7696 // registers, since it is not usable as a write mask.
7697 // FIXME: A more advanced approach would be to choose the best input mask
7698 // register based on context.
7699 case X86::KSET0W: return Expand2AddrKreg(MIB, get(X86::KXORWrr), X86::K0);
7700 case X86::KSET0D: return Expand2AddrKreg(MIB, get(X86::KXORDrr), X86::K0);
7701 case X86::KSET0Q: return Expand2AddrKreg(MIB, get(X86::KXORQrr), X86::K0);
7702 case X86::KSET1W: return Expand2AddrKreg(MIB, get(X86::KXNORWrr), X86::K0);
7703 case X86::KSET1D: return Expand2AddrKreg(MIB, get(X86::KXNORDrr), X86::K0);
7704 case X86::KSET1Q: return Expand2AddrKreg(MIB, get(X86::KXNORQrr), X86::K0);
7705 case TargetOpcode::LOAD_STACK_GUARD:
7706 expandLoadStackGuard(MIB, *this);
7707 return true;
7708 }
7709 return false;
7710}
7711
7712static void addOperands(MachineInstrBuilder &MIB, ArrayRef<MachineOperand> MOs,
7713 int PtrOffset = 0) {
7714 unsigned NumAddrOps = MOs.size();
7715
7716 if (NumAddrOps < 4) {
7717 // FrameIndex only - add an immediate offset (whether its zero or not).
7718 for (unsigned i = 0; i != NumAddrOps; ++i)
7719 MIB.add(MOs[i]);
7720 addOffset(MIB, PtrOffset);
7721 } else {
7722 // General Memory Addressing - we need to add any offset to an existing
7723 // offset.
7724 assert(MOs.size() == 5 && "Unexpected memory operand list length")((MOs.size() == 5 && "Unexpected m