Bug Summary

File:lib/Target/X86/X86InstrInfo.cpp
Warning:line 3489, column 37
Called C++ object pointer is null

Annotated Source Code

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clang -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name X86InstrInfo.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mthread-model posix -fmath-errno -masm-verbose -mconstructor-aliases -munwind-tables -fuse-init-array -target-cpu x86-64 -dwarf-column-info -debugger-tuning=gdb -momit-leaf-frame-pointer -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-9/lib/clang/9.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-9~svn362543/build-llvm/lib/Target/X86 -I /build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86 -I /build/llvm-toolchain-snapshot-9~svn362543/build-llvm/include -I /build/llvm-toolchain-snapshot-9~svn362543/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0/backward -internal-isystem /usr/include/clang/9.0.0/include/ -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-9/lib/clang/9.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++11 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-9~svn362543/build-llvm/lib/Target/X86 -fdebug-prefix-map=/build/llvm-toolchain-snapshot-9~svn362543=. -ferror-limit 19 -fmessage-length 0 -fvisibility-inlines-hidden -stack-protector 2 -fobjc-runtime=gcc -fdiagnostics-show-option -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -o /tmp/scan-build-2019-06-05-060531-1271-1 -x c++ /build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp -faddrsig
1//===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the X86 implementation of the TargetInstrInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "X86InstrInfo.h"
14#include "X86.h"
15#include "X86InstrBuilder.h"
16#include "X86InstrFoldTables.h"
17#include "X86MachineFunctionInfo.h"
18#include "X86Subtarget.h"
19#include "X86TargetMachine.h"
20#include "llvm/ADT/STLExtras.h"
21#include "llvm/ADT/Sequence.h"
22#include "llvm/CodeGen/LivePhysRegs.h"
23#include "llvm/CodeGen/LiveVariables.h"
24#include "llvm/CodeGen/MachineConstantPool.h"
25#include "llvm/CodeGen/MachineDominators.h"
26#include "llvm/CodeGen/MachineFrameInfo.h"
27#include "llvm/CodeGen/MachineInstrBuilder.h"
28#include "llvm/CodeGen/MachineModuleInfo.h"
29#include "llvm/CodeGen/MachineRegisterInfo.h"
30#include "llvm/CodeGen/StackMaps.h"
31#include "llvm/IR/DerivedTypes.h"
32#include "llvm/IR/Function.h"
33#include "llvm/IR/LLVMContext.h"
34#include "llvm/MC/MCAsmInfo.h"
35#include "llvm/MC/MCExpr.h"
36#include "llvm/MC/MCInst.h"
37#include "llvm/Support/CommandLine.h"
38#include "llvm/Support/Debug.h"
39#include "llvm/Support/ErrorHandling.h"
40#include "llvm/Support/raw_ostream.h"
41#include "llvm/Target/TargetOptions.h"
42
43using namespace llvm;
44
45#define DEBUG_TYPE"x86-instr-info" "x86-instr-info"
46
47#define GET_INSTRINFO_CTOR_DTOR
48#include "X86GenInstrInfo.inc"
49
50static cl::opt<bool>
51 NoFusing("disable-spill-fusing",
52 cl::desc("Disable fusing of spill code into instructions"),
53 cl::Hidden);
54static cl::opt<bool>
55PrintFailedFusing("print-failed-fuse-candidates",
56 cl::desc("Print instructions that the allocator wants to"
57 " fuse, but the X86 backend currently can't"),
58 cl::Hidden);
59static cl::opt<bool>
60ReMatPICStubLoad("remat-pic-stub-load",
61 cl::desc("Re-materialize load from stub in PIC mode"),
62 cl::init(false), cl::Hidden);
63static cl::opt<unsigned>
64PartialRegUpdateClearance("partial-reg-update-clearance",
65 cl::desc("Clearance between two register writes "
66 "for inserting XOR to avoid partial "
67 "register update"),
68 cl::init(64), cl::Hidden);
69static cl::opt<unsigned>
70UndefRegClearance("undef-reg-clearance",
71 cl::desc("How many idle instructions we would like before "
72 "certain undef register reads"),
73 cl::init(128), cl::Hidden);
74
75
76// Pin the vtable to this file.
77void X86InstrInfo::anchor() {}
78
79X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
80 : X86GenInstrInfo((STI.isTarget64BitLP64() ? X86::ADJCALLSTACKDOWN64
81 : X86::ADJCALLSTACKDOWN32),
82 (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64
83 : X86::ADJCALLSTACKUP32),
84 X86::CATCHRET,
85 (STI.is64Bit() ? X86::RETQ : X86::RETL)),
86 Subtarget(STI), RI(STI.getTargetTriple()) {
87}
88
89bool
90X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
91 unsigned &SrcReg, unsigned &DstReg,
92 unsigned &SubIdx) const {
93 switch (MI.getOpcode()) {
94 default: break;
95 case X86::MOVSX16rr8:
96 case X86::MOVZX16rr8:
97 case X86::MOVSX32rr8:
98 case X86::MOVZX32rr8:
99 case X86::MOVSX64rr8:
100 if (!Subtarget.is64Bit())
101 // It's not always legal to reference the low 8-bit of the larger
102 // register in 32-bit mode.
103 return false;
104 LLVM_FALLTHROUGH[[clang::fallthrough]];
105 case X86::MOVSX32rr16:
106 case X86::MOVZX32rr16:
107 case X86::MOVSX64rr16:
108 case X86::MOVSX64rr32: {
109 if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
110 // Be conservative.
111 return false;
112 SrcReg = MI.getOperand(1).getReg();
113 DstReg = MI.getOperand(0).getReg();
114 switch (MI.getOpcode()) {
115 default: llvm_unreachable("Unreachable!")::llvm::llvm_unreachable_internal("Unreachable!", "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 115);
116 case X86::MOVSX16rr8:
117 case X86::MOVZX16rr8:
118 case X86::MOVSX32rr8:
119 case X86::MOVZX32rr8:
120 case X86::MOVSX64rr8:
121 SubIdx = X86::sub_8bit;
122 break;
123 case X86::MOVSX32rr16:
124 case X86::MOVZX32rr16:
125 case X86::MOVSX64rr16:
126 SubIdx = X86::sub_16bit;
127 break;
128 case X86::MOVSX64rr32:
129 SubIdx = X86::sub_32bit;
130 break;
131 }
132 return true;
133 }
134 }
135 return false;
136}
137
138int X86InstrInfo::getSPAdjust(const MachineInstr &MI) const {
139 const MachineFunction *MF = MI.getParent()->getParent();
140 const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering();
141
142 if (isFrameInstr(MI)) {
143 unsigned StackAlign = TFI->getStackAlignment();
144 int SPAdj = alignTo(getFrameSize(MI), StackAlign);
145 SPAdj -= getFrameAdjustment(MI);
146 if (!isFrameSetup(MI))
147 SPAdj = -SPAdj;
148 return SPAdj;
149 }
150
151 // To know whether a call adjusts the stack, we need information
152 // that is bound to the following ADJCALLSTACKUP pseudo.
153 // Look for the next ADJCALLSTACKUP that follows the call.
154 if (MI.isCall()) {
155 const MachineBasicBlock *MBB = MI.getParent();
156 auto I = ++MachineBasicBlock::const_iterator(MI);
157 for (auto E = MBB->end(); I != E; ++I) {
158 if (I->getOpcode() == getCallFrameDestroyOpcode() ||
159 I->isCall())
160 break;
161 }
162
163 // If we could not find a frame destroy opcode, then it has already
164 // been simplified, so we don't care.
165 if (I->getOpcode() != getCallFrameDestroyOpcode())
166 return 0;
167
168 return -(I->getOperand(1).getImm());
169 }
170
171 // Currently handle only PUSHes we can reasonably expect to see
172 // in call sequences
173 switch (MI.getOpcode()) {
174 default:
175 return 0;
176 case X86::PUSH32i8:
177 case X86::PUSH32r:
178 case X86::PUSH32rmm:
179 case X86::PUSH32rmr:
180 case X86::PUSHi32:
181 return 4;
182 case X86::PUSH64i8:
183 case X86::PUSH64r:
184 case X86::PUSH64rmm:
185 case X86::PUSH64rmr:
186 case X86::PUSH64i32:
187 return 8;
188 }
189}
190
191/// Return true and the FrameIndex if the specified
192/// operand and follow operands form a reference to the stack frame.
193bool X86InstrInfo::isFrameOperand(const MachineInstr &MI, unsigned int Op,
194 int &FrameIndex) const {
195 if (MI.getOperand(Op + X86::AddrBaseReg).isFI() &&
196 MI.getOperand(Op + X86::AddrScaleAmt).isImm() &&
197 MI.getOperand(Op + X86::AddrIndexReg).isReg() &&
198 MI.getOperand(Op + X86::AddrDisp).isImm() &&
199 MI.getOperand(Op + X86::AddrScaleAmt).getImm() == 1 &&
200 MI.getOperand(Op + X86::AddrIndexReg).getReg() == 0 &&
201 MI.getOperand(Op + X86::AddrDisp).getImm() == 0) {
202 FrameIndex = MI.getOperand(Op + X86::AddrBaseReg).getIndex();
203 return true;
204 }
205 return false;
206}
207
208static bool isFrameLoadOpcode(int Opcode, unsigned &MemBytes) {
209 switch (Opcode) {
210 default:
211 return false;
212 case X86::MOV8rm:
213 case X86::KMOVBkm:
214 MemBytes = 1;
215 return true;
216 case X86::MOV16rm:
217 case X86::KMOVWkm:
218 MemBytes = 2;
219 return true;
220 case X86::MOV32rm:
221 case X86::MOVSSrm:
222 case X86::VMOVSSZrm:
223 case X86::VMOVSSrm:
224 case X86::KMOVDkm:
225 MemBytes = 4;
226 return true;
227 case X86::MOV64rm:
228 case X86::LD_Fp64m:
229 case X86::MOVSDrm:
230 case X86::VMOVSDrm:
231 case X86::VMOVSDZrm:
232 case X86::MMX_MOVD64rm:
233 case X86::MMX_MOVQ64rm:
234 case X86::KMOVQkm:
235 MemBytes = 8;
236 return true;
237 case X86::MOVAPSrm:
238 case X86::MOVUPSrm:
239 case X86::MOVAPDrm:
240 case X86::MOVUPDrm:
241 case X86::MOVDQArm:
242 case X86::MOVDQUrm:
243 case X86::VMOVAPSrm:
244 case X86::VMOVUPSrm:
245 case X86::VMOVAPDrm:
246 case X86::VMOVUPDrm:
247 case X86::VMOVDQArm:
248 case X86::VMOVDQUrm:
249 case X86::VMOVAPSZ128rm:
250 case X86::VMOVUPSZ128rm:
251 case X86::VMOVAPSZ128rm_NOVLX:
252 case X86::VMOVUPSZ128rm_NOVLX:
253 case X86::VMOVAPDZ128rm:
254 case X86::VMOVUPDZ128rm:
255 case X86::VMOVDQU8Z128rm:
256 case X86::VMOVDQU16Z128rm:
257 case X86::VMOVDQA32Z128rm:
258 case X86::VMOVDQU32Z128rm:
259 case X86::VMOVDQA64Z128rm:
260 case X86::VMOVDQU64Z128rm:
261 MemBytes = 16;
262 return true;
263 case X86::VMOVAPSYrm:
264 case X86::VMOVUPSYrm:
265 case X86::VMOVAPDYrm:
266 case X86::VMOVUPDYrm:
267 case X86::VMOVDQAYrm:
268 case X86::VMOVDQUYrm:
269 case X86::VMOVAPSZ256rm:
270 case X86::VMOVUPSZ256rm:
271 case X86::VMOVAPSZ256rm_NOVLX:
272 case X86::VMOVUPSZ256rm_NOVLX:
273 case X86::VMOVAPDZ256rm:
274 case X86::VMOVUPDZ256rm:
275 case X86::VMOVDQU8Z256rm:
276 case X86::VMOVDQU16Z256rm:
277 case X86::VMOVDQA32Z256rm:
278 case X86::VMOVDQU32Z256rm:
279 case X86::VMOVDQA64Z256rm:
280 case X86::VMOVDQU64Z256rm:
281 MemBytes = 32;
282 return true;
283 case X86::VMOVAPSZrm:
284 case X86::VMOVUPSZrm:
285 case X86::VMOVAPDZrm:
286 case X86::VMOVUPDZrm:
287 case X86::VMOVDQU8Zrm:
288 case X86::VMOVDQU16Zrm:
289 case X86::VMOVDQA32Zrm:
290 case X86::VMOVDQU32Zrm:
291 case X86::VMOVDQA64Zrm:
292 case X86::VMOVDQU64Zrm:
293 MemBytes = 64;
294 return true;
295 }
296}
297
298static bool isFrameStoreOpcode(int Opcode, unsigned &MemBytes) {
299 switch (Opcode) {
300 default:
301 return false;
302 case X86::MOV8mr:
303 case X86::KMOVBmk:
304 MemBytes = 1;
305 return true;
306 case X86::MOV16mr:
307 case X86::KMOVWmk:
308 MemBytes = 2;
309 return true;
310 case X86::MOV32mr:
311 case X86::MOVSSmr:
312 case X86::VMOVSSmr:
313 case X86::VMOVSSZmr:
314 case X86::KMOVDmk:
315 MemBytes = 4;
316 return true;
317 case X86::MOV64mr:
318 case X86::ST_FpP64m:
319 case X86::MOVSDmr:
320 case X86::VMOVSDmr:
321 case X86::VMOVSDZmr:
322 case X86::MMX_MOVD64mr:
323 case X86::MMX_MOVQ64mr:
324 case X86::MMX_MOVNTQmr:
325 case X86::KMOVQmk:
326 MemBytes = 8;
327 return true;
328 case X86::MOVAPSmr:
329 case X86::MOVUPSmr:
330 case X86::MOVAPDmr:
331 case X86::MOVUPDmr:
332 case X86::MOVDQAmr:
333 case X86::MOVDQUmr:
334 case X86::VMOVAPSmr:
335 case X86::VMOVUPSmr:
336 case X86::VMOVAPDmr:
337 case X86::VMOVUPDmr:
338 case X86::VMOVDQAmr:
339 case X86::VMOVDQUmr:
340 case X86::VMOVUPSZ128mr:
341 case X86::VMOVAPSZ128mr:
342 case X86::VMOVUPSZ128mr_NOVLX:
343 case X86::VMOVAPSZ128mr_NOVLX:
344 case X86::VMOVUPDZ128mr:
345 case X86::VMOVAPDZ128mr:
346 case X86::VMOVDQA32Z128mr:
347 case X86::VMOVDQU32Z128mr:
348 case X86::VMOVDQA64Z128mr:
349 case X86::VMOVDQU64Z128mr:
350 case X86::VMOVDQU8Z128mr:
351 case X86::VMOVDQU16Z128mr:
352 MemBytes = 16;
353 return true;
354 case X86::VMOVUPSYmr:
355 case X86::VMOVAPSYmr:
356 case X86::VMOVUPDYmr:
357 case X86::VMOVAPDYmr:
358 case X86::VMOVDQUYmr:
359 case X86::VMOVDQAYmr:
360 case X86::VMOVUPSZ256mr:
361 case X86::VMOVAPSZ256mr:
362 case X86::VMOVUPSZ256mr_NOVLX:
363 case X86::VMOVAPSZ256mr_NOVLX:
364 case X86::VMOVUPDZ256mr:
365 case X86::VMOVAPDZ256mr:
366 case X86::VMOVDQU8Z256mr:
367 case X86::VMOVDQU16Z256mr:
368 case X86::VMOVDQA32Z256mr:
369 case X86::VMOVDQU32Z256mr:
370 case X86::VMOVDQA64Z256mr:
371 case X86::VMOVDQU64Z256mr:
372 MemBytes = 32;
373 return true;
374 case X86::VMOVUPSZmr:
375 case X86::VMOVAPSZmr:
376 case X86::VMOVUPDZmr:
377 case X86::VMOVAPDZmr:
378 case X86::VMOVDQU8Zmr:
379 case X86::VMOVDQU16Zmr:
380 case X86::VMOVDQA32Zmr:
381 case X86::VMOVDQU32Zmr:
382 case X86::VMOVDQA64Zmr:
383 case X86::VMOVDQU64Zmr:
384 MemBytes = 64;
385 return true;
386 }
387 return false;
388}
389
390unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
391 int &FrameIndex) const {
392 unsigned Dummy;
393 return X86InstrInfo::isLoadFromStackSlot(MI, FrameIndex, Dummy);
394}
395
396unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
397 int &FrameIndex,
398 unsigned &MemBytes) const {
399 if (isFrameLoadOpcode(MI.getOpcode(), MemBytes))
400 if (MI.getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex))
401 return MI.getOperand(0).getReg();
402 return 0;
403}
404
405unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr &MI,
406 int &FrameIndex) const {
407 unsigned Dummy;
408 if (isFrameLoadOpcode(MI.getOpcode(), Dummy)) {
409 unsigned Reg;
410 if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
411 return Reg;
412 // Check for post-frame index elimination operations
413 SmallVector<const MachineMemOperand *, 1> Accesses;
414 if (hasLoadFromStackSlot(MI, Accesses)) {
415 FrameIndex =
416 cast<FixedStackPseudoSourceValue>(Accesses.front()->getPseudoValue())
417 ->getFrameIndex();
418 return 1;
419 }
420 }
421 return 0;
422}
423
424unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
425 int &FrameIndex) const {
426 unsigned Dummy;
427 return X86InstrInfo::isStoreToStackSlot(MI, FrameIndex, Dummy);
428}
429
430unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
431 int &FrameIndex,
432 unsigned &MemBytes) const {
433 if (isFrameStoreOpcode(MI.getOpcode(), MemBytes))
434 if (MI.getOperand(X86::AddrNumOperands).getSubReg() == 0 &&
435 isFrameOperand(MI, 0, FrameIndex))
436 return MI.getOperand(X86::AddrNumOperands).getReg();
437 return 0;
438}
439
440unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr &MI,
441 int &FrameIndex) const {
442 unsigned Dummy;
443 if (isFrameStoreOpcode(MI.getOpcode(), Dummy)) {
444 unsigned Reg;
445 if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
446 return Reg;
447 // Check for post-frame index elimination operations
448 SmallVector<const MachineMemOperand *, 1> Accesses;
449 if (hasStoreToStackSlot(MI, Accesses)) {
450 FrameIndex =
451 cast<FixedStackPseudoSourceValue>(Accesses.front()->getPseudoValue())
452 ->getFrameIndex();
453 return 1;
454 }
455 }
456 return 0;
457}
458
459/// Return true if register is PIC base; i.e.g defined by X86::MOVPC32r.
460static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
461 // Don't waste compile time scanning use-def chains of physregs.
462 if (!TargetRegisterInfo::isVirtualRegister(BaseReg))
463 return false;
464 bool isPICBase = false;
465 for (MachineRegisterInfo::def_instr_iterator I = MRI.def_instr_begin(BaseReg),
466 E = MRI.def_instr_end(); I != E; ++I) {
467 MachineInstr *DefMI = &*I;
468 if (DefMI->getOpcode() != X86::MOVPC32r)
469 return false;
470 assert(!isPICBase && "More than one PIC base?")((!isPICBase && "More than one PIC base?") ? static_cast
<void> (0) : __assert_fail ("!isPICBase && \"More than one PIC base?\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 470, __PRETTY_FUNCTION__));
471 isPICBase = true;
472 }
473 return isPICBase;
474}
475
476bool X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr &MI,
477 AliasAnalysis *AA) const {
478 switch (MI.getOpcode()) {
479 default: break;
480 case X86::MOV8rm:
481 case X86::MOV8rm_NOREX:
482 case X86::MOV16rm:
483 case X86::MOV32rm:
484 case X86::MOV64rm:
485 case X86::MOVSSrm:
486 case X86::MOVSDrm:
487 case X86::MOVAPSrm:
488 case X86::MOVUPSrm:
489 case X86::MOVAPDrm:
490 case X86::MOVUPDrm:
491 case X86::MOVDQArm:
492 case X86::MOVDQUrm:
493 case X86::VMOVSSrm:
494 case X86::VMOVSDrm:
495 case X86::VMOVAPSrm:
496 case X86::VMOVUPSrm:
497 case X86::VMOVAPDrm:
498 case X86::VMOVUPDrm:
499 case X86::VMOVDQArm:
500 case X86::VMOVDQUrm:
501 case X86::VMOVAPSYrm:
502 case X86::VMOVUPSYrm:
503 case X86::VMOVAPDYrm:
504 case X86::VMOVUPDYrm:
505 case X86::VMOVDQAYrm:
506 case X86::VMOVDQUYrm:
507 case X86::MMX_MOVD64rm:
508 case X86::MMX_MOVQ64rm:
509 // AVX-512
510 case X86::VMOVSSZrm:
511 case X86::VMOVSDZrm:
512 case X86::VMOVAPDZ128rm:
513 case X86::VMOVAPDZ256rm:
514 case X86::VMOVAPDZrm:
515 case X86::VMOVAPSZ128rm:
516 case X86::VMOVAPSZ256rm:
517 case X86::VMOVAPSZ128rm_NOVLX:
518 case X86::VMOVAPSZ256rm_NOVLX:
519 case X86::VMOVAPSZrm:
520 case X86::VMOVDQA32Z128rm:
521 case X86::VMOVDQA32Z256rm:
522 case X86::VMOVDQA32Zrm:
523 case X86::VMOVDQA64Z128rm:
524 case X86::VMOVDQA64Z256rm:
525 case X86::VMOVDQA64Zrm:
526 case X86::VMOVDQU16Z128rm:
527 case X86::VMOVDQU16Z256rm:
528 case X86::VMOVDQU16Zrm:
529 case X86::VMOVDQU32Z128rm:
530 case X86::VMOVDQU32Z256rm:
531 case X86::VMOVDQU32Zrm:
532 case X86::VMOVDQU64Z128rm:
533 case X86::VMOVDQU64Z256rm:
534 case X86::VMOVDQU64Zrm:
535 case X86::VMOVDQU8Z128rm:
536 case X86::VMOVDQU8Z256rm:
537 case X86::VMOVDQU8Zrm:
538 case X86::VMOVUPDZ128rm:
539 case X86::VMOVUPDZ256rm:
540 case X86::VMOVUPDZrm:
541 case X86::VMOVUPSZ128rm:
542 case X86::VMOVUPSZ256rm:
543 case X86::VMOVUPSZ128rm_NOVLX:
544 case X86::VMOVUPSZ256rm_NOVLX:
545 case X86::VMOVUPSZrm: {
546 // Loads from constant pools are trivially rematerializable.
547 if (MI.getOperand(1 + X86::AddrBaseReg).isReg() &&
548 MI.getOperand(1 + X86::AddrScaleAmt).isImm() &&
549 MI.getOperand(1 + X86::AddrIndexReg).isReg() &&
550 MI.getOperand(1 + X86::AddrIndexReg).getReg() == 0 &&
551 MI.isDereferenceableInvariantLoad(AA)) {
552 unsigned BaseReg = MI.getOperand(1 + X86::AddrBaseReg).getReg();
553 if (BaseReg == 0 || BaseReg == X86::RIP)
554 return true;
555 // Allow re-materialization of PIC load.
556 if (!ReMatPICStubLoad && MI.getOperand(1 + X86::AddrDisp).isGlobal())
557 return false;
558 const MachineFunction &MF = *MI.getParent()->getParent();
559 const MachineRegisterInfo &MRI = MF.getRegInfo();
560 return regIsPICBase(BaseReg, MRI);
561 }
562 return false;
563 }
564
565 case X86::LEA32r:
566 case X86::LEA64r: {
567 if (MI.getOperand(1 + X86::AddrScaleAmt).isImm() &&
568 MI.getOperand(1 + X86::AddrIndexReg).isReg() &&
569 MI.getOperand(1 + X86::AddrIndexReg).getReg() == 0 &&
570 !MI.getOperand(1 + X86::AddrDisp).isReg()) {
571 // lea fi#, lea GV, etc. are all rematerializable.
572 if (!MI.getOperand(1 + X86::AddrBaseReg).isReg())
573 return true;
574 unsigned BaseReg = MI.getOperand(1 + X86::AddrBaseReg).getReg();
575 if (BaseReg == 0)
576 return true;
577 // Allow re-materialization of lea PICBase + x.
578 const MachineFunction &MF = *MI.getParent()->getParent();
579 const MachineRegisterInfo &MRI = MF.getRegInfo();
580 return regIsPICBase(BaseReg, MRI);
581 }
582 return false;
583 }
584 }
585
586 // All other instructions marked M_REMATERIALIZABLE are always trivially
587 // rematerializable.
588 return true;
589}
590
591void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
592 MachineBasicBlock::iterator I,
593 unsigned DestReg, unsigned SubIdx,
594 const MachineInstr &Orig,
595 const TargetRegisterInfo &TRI) const {
596 bool ClobbersEFLAGS = Orig.modifiesRegister(X86::EFLAGS, &TRI);
597 if (ClobbersEFLAGS && !isSafeToClobberEFLAGS(MBB, I)) {
598 // The instruction clobbers EFLAGS. Re-materialize as MOV32ri to avoid side
599 // effects.
600 int Value;
601 switch (Orig.getOpcode()) {
602 case X86::MOV32r0: Value = 0; break;
603 case X86::MOV32r1: Value = 1; break;
604 case X86::MOV32r_1: Value = -1; break;
605 default:
606 llvm_unreachable("Unexpected instruction!")::llvm::llvm_unreachable_internal("Unexpected instruction!", "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 606);
607 }
608
609 const DebugLoc &DL = Orig.getDebugLoc();
610 BuildMI(MBB, I, DL, get(X86::MOV32ri))
611 .add(Orig.getOperand(0))
612 .addImm(Value);
613 } else {
614 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(&Orig);
615 MBB.insert(I, MI);
616 }
617
618 MachineInstr &NewMI = *std::prev(I);
619 NewMI.substituteRegister(Orig.getOperand(0).getReg(), DestReg, SubIdx, TRI);
620}
621
622/// True if MI has a condition code def, e.g. EFLAGS, that is not marked dead.
623bool X86InstrInfo::hasLiveCondCodeDef(MachineInstr &MI) const {
624 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
625 MachineOperand &MO = MI.getOperand(i);
626 if (MO.isReg() && MO.isDef() &&
627 MO.getReg() == X86::EFLAGS && !MO.isDead()) {
628 return true;
629 }
630 }
631 return false;
632}
633
634/// Check whether the shift count for a machine operand is non-zero.
635inline static unsigned getTruncatedShiftCount(const MachineInstr &MI,
636 unsigned ShiftAmtOperandIdx) {
637 // The shift count is six bits with the REX.W prefix and five bits without.
638 unsigned ShiftCountMask = (MI.getDesc().TSFlags & X86II::REX_W) ? 63 : 31;
639 unsigned Imm = MI.getOperand(ShiftAmtOperandIdx).getImm();
640 return Imm & ShiftCountMask;
641}
642
643/// Check whether the given shift count is appropriate
644/// can be represented by a LEA instruction.
645inline static bool isTruncatedShiftCountForLEA(unsigned ShAmt) {
646 // Left shift instructions can be transformed into load-effective-address
647 // instructions if we can encode them appropriately.
648 // A LEA instruction utilizes a SIB byte to encode its scale factor.
649 // The SIB.scale field is two bits wide which means that we can encode any
650 // shift amount less than 4.
651 return ShAmt < 4 && ShAmt > 0;
652}
653
654bool X86InstrInfo::classifyLEAReg(MachineInstr &MI, const MachineOperand &Src,
655 unsigned Opc, bool AllowSP, unsigned &NewSrc,
656 bool &isKill, MachineOperand &ImplicitOp,
657 LiveVariables *LV) const {
658 MachineFunction &MF = *MI.getParent()->getParent();
659 const TargetRegisterClass *RC;
660 if (AllowSP) {
661 RC = Opc != X86::LEA32r ? &X86::GR64RegClass : &X86::GR32RegClass;
662 } else {
663 RC = Opc != X86::LEA32r ?
664 &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass;
665 }
666 unsigned SrcReg = Src.getReg();
667
668 // For both LEA64 and LEA32 the register already has essentially the right
669 // type (32-bit or 64-bit) we may just need to forbid SP.
670 if (Opc != X86::LEA64_32r) {
671 NewSrc = SrcReg;
672 isKill = Src.isKill();
673 assert(!Src.isUndef() && "Undef op doesn't need optimization")((!Src.isUndef() && "Undef op doesn't need optimization"
) ? static_cast<void> (0) : __assert_fail ("!Src.isUndef() && \"Undef op doesn't need optimization\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 673, __PRETTY_FUNCTION__));
674
675 if (TargetRegisterInfo::isVirtualRegister(NewSrc) &&
676 !MF.getRegInfo().constrainRegClass(NewSrc, RC))
677 return false;
678
679 return true;
680 }
681
682 // This is for an LEA64_32r and incoming registers are 32-bit. One way or
683 // another we need to add 64-bit registers to the final MI.
684 if (TargetRegisterInfo::isPhysicalRegister(SrcReg)) {
685 ImplicitOp = Src;
686 ImplicitOp.setImplicit();
687
688 NewSrc = getX86SubSuperRegister(Src.getReg(), 64);
689 isKill = Src.isKill();
690 assert(!Src.isUndef() && "Undef op doesn't need optimization")((!Src.isUndef() && "Undef op doesn't need optimization"
) ? static_cast<void> (0) : __assert_fail ("!Src.isUndef() && \"Undef op doesn't need optimization\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 690, __PRETTY_FUNCTION__));
691 } else {
692 // Virtual register of the wrong class, we have to create a temporary 64-bit
693 // vreg to feed into the LEA.
694 NewSrc = MF.getRegInfo().createVirtualRegister(RC);
695 MachineInstr *Copy =
696 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(TargetOpcode::COPY))
697 .addReg(NewSrc, RegState::Define | RegState::Undef, X86::sub_32bit)
698 .add(Src);
699
700 // Which is obviously going to be dead after we're done with it.
701 isKill = true;
702
703 if (LV)
704 LV->replaceKillInstruction(SrcReg, MI, *Copy);
705 }
706
707 // We've set all the parameters without issue.
708 return true;
709}
710
711MachineInstr *X86InstrInfo::convertToThreeAddressWithLEA(
712 unsigned MIOpc, MachineFunction::iterator &MFI, MachineInstr &MI,
713 LiveVariables *LV, bool Is8BitOp) const {
714 // We handle 8-bit adds and various 16-bit opcodes in the switch below.
715 MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
716 assert((Is8BitOp || RegInfo.getTargetRegisterInfo()->getRegSizeInBits((((Is8BitOp || RegInfo.getTargetRegisterInfo()->getRegSizeInBits
( *RegInfo.getRegClass(MI.getOperand(0).getReg())) == 16) &&
"Unexpected type for LEA transform") ? static_cast<void>
(0) : __assert_fail ("(Is8BitOp || RegInfo.getTargetRegisterInfo()->getRegSizeInBits( *RegInfo.getRegClass(MI.getOperand(0).getReg())) == 16) && \"Unexpected type for LEA transform\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 718, __PRETTY_FUNCTION__))
717 *RegInfo.getRegClass(MI.getOperand(0).getReg())) == 16) &&(((Is8BitOp || RegInfo.getTargetRegisterInfo()->getRegSizeInBits
( *RegInfo.getRegClass(MI.getOperand(0).getReg())) == 16) &&
"Unexpected type for LEA transform") ? static_cast<void>
(0) : __assert_fail ("(Is8BitOp || RegInfo.getTargetRegisterInfo()->getRegSizeInBits( *RegInfo.getRegClass(MI.getOperand(0).getReg())) == 16) && \"Unexpected type for LEA transform\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 718, __PRETTY_FUNCTION__))
718 "Unexpected type for LEA transform")(((Is8BitOp || RegInfo.getTargetRegisterInfo()->getRegSizeInBits
( *RegInfo.getRegClass(MI.getOperand(0).getReg())) == 16) &&
"Unexpected type for LEA transform") ? static_cast<void>
(0) : __assert_fail ("(Is8BitOp || RegInfo.getTargetRegisterInfo()->getRegSizeInBits( *RegInfo.getRegClass(MI.getOperand(0).getReg())) == 16) && \"Unexpected type for LEA transform\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 718, __PRETTY_FUNCTION__));
719
720 // TODO: For a 32-bit target, we need to adjust the LEA variables with
721 // something like this:
722 // Opcode = X86::LEA32r;
723 // InRegLEA = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
724 // OutRegLEA =
725 // Is8BitOp ? RegInfo.createVirtualRegister(&X86::GR32ABCD_RegClass)
726 // : RegInfo.createVirtualRegister(&X86::GR32RegClass);
727 if (!Subtarget.is64Bit())
728 return nullptr;
729
730 unsigned Opcode = X86::LEA64_32r;
731 unsigned InRegLEA = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
732 unsigned OutRegLEA = RegInfo.createVirtualRegister(&X86::GR32RegClass);
733
734 // Build and insert into an implicit UNDEF value. This is OK because
735 // we will be shifting and then extracting the lower 8/16-bits.
736 // This has the potential to cause partial register stall. e.g.
737 // movw (%rbp,%rcx,2), %dx
738 // leal -65(%rdx), %esi
739 // But testing has shown this *does* help performance in 64-bit mode (at
740 // least on modern x86 machines).
741 MachineBasicBlock::iterator MBBI = MI.getIterator();
742 unsigned Dest = MI.getOperand(0).getReg();
743 unsigned Src = MI.getOperand(1).getReg();
744 bool IsDead = MI.getOperand(0).isDead();
745 bool IsKill = MI.getOperand(1).isKill();
746 unsigned SubReg = Is8BitOp ? X86::sub_8bit : X86::sub_16bit;
747 assert(!MI.getOperand(1).isUndef() && "Undef op doesn't need optimization")((!MI.getOperand(1).isUndef() && "Undef op doesn't need optimization"
) ? static_cast<void> (0) : __assert_fail ("!MI.getOperand(1).isUndef() && \"Undef op doesn't need optimization\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 747, __PRETTY_FUNCTION__));
748 BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(X86::IMPLICIT_DEF), InRegLEA);
749 MachineInstr *InsMI =
750 BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(TargetOpcode::COPY))
751 .addReg(InRegLEA, RegState::Define, SubReg)
752 .addReg(Src, getKillRegState(IsKill));
753
754 MachineInstrBuilder MIB =
755 BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(Opcode), OutRegLEA);
756 switch (MIOpc) {
757 default: llvm_unreachable("Unreachable!")::llvm::llvm_unreachable_internal("Unreachable!", "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 757);
758 case X86::SHL8ri:
759 case X86::SHL16ri: {
760 unsigned ShAmt = MI.getOperand(2).getImm();
761 MIB.addReg(0).addImm(1ULL << ShAmt)
762 .addReg(InRegLEA, RegState::Kill).addImm(0).addReg(0);
763 break;
764 }
765 case X86::INC8r:
766 case X86::INC16r:
767 addRegOffset(MIB, InRegLEA, true, 1);
768 break;
769 case X86::DEC8r:
770 case X86::DEC16r:
771 addRegOffset(MIB, InRegLEA, true, -1);
772 break;
773 case X86::ADD8ri:
774 case X86::ADD8ri_DB:
775 case X86::ADD16ri:
776 case X86::ADD16ri8:
777 case X86::ADD16ri_DB:
778 case X86::ADD16ri8_DB:
779 addRegOffset(MIB, InRegLEA, true, MI.getOperand(2).getImm());
780 break;
781 case X86::ADD8rr:
782 case X86::ADD8rr_DB:
783 case X86::ADD16rr:
784 case X86::ADD16rr_DB: {
785 unsigned Src2 = MI.getOperand(2).getReg();
786 bool IsKill2 = MI.getOperand(2).isKill();
787 assert(!MI.getOperand(2).isUndef() && "Undef op doesn't need optimization")((!MI.getOperand(2).isUndef() && "Undef op doesn't need optimization"
) ? static_cast<void> (0) : __assert_fail ("!MI.getOperand(2).isUndef() && \"Undef op doesn't need optimization\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 787, __PRETTY_FUNCTION__));
788 unsigned InRegLEA2 = 0;
789 MachineInstr *InsMI2 = nullptr;
790 if (Src == Src2) {
791 // ADD8rr/ADD16rr killed %reg1028, %reg1028
792 // just a single insert_subreg.
793 addRegReg(MIB, InRegLEA, true, InRegLEA, false);
794 } else {
795 if (Subtarget.is64Bit())
796 InRegLEA2 = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
797 else
798 InRegLEA2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
799 // Build and insert into an implicit UNDEF value. This is OK because
800 // we will be shifting and then extracting the lower 8/16-bits.
801 BuildMI(*MFI, &*MIB, MI.getDebugLoc(), get(X86::IMPLICIT_DEF), InRegLEA2);
802 InsMI2 = BuildMI(*MFI, &*MIB, MI.getDebugLoc(), get(TargetOpcode::COPY))
803 .addReg(InRegLEA2, RegState::Define, SubReg)
804 .addReg(Src2, getKillRegState(IsKill2));
805 addRegReg(MIB, InRegLEA, true, InRegLEA2, true);
806 }
807 if (LV && IsKill2 && InsMI2)
808 LV->replaceKillInstruction(Src2, MI, *InsMI2);
809 break;
810 }
811 }
812
813 MachineInstr *NewMI = MIB;
814 MachineInstr *ExtMI =
815 BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(TargetOpcode::COPY))
816 .addReg(Dest, RegState::Define | getDeadRegState(IsDead))
817 .addReg(OutRegLEA, RegState::Kill, SubReg);
818
819 if (LV) {
820 // Update live variables.
821 LV->getVarInfo(InRegLEA).Kills.push_back(NewMI);
822 LV->getVarInfo(OutRegLEA).Kills.push_back(ExtMI);
823 if (IsKill)
824 LV->replaceKillInstruction(Src, MI, *InsMI);
825 if (IsDead)
826 LV->replaceKillInstruction(Dest, MI, *ExtMI);
827 }
828
829 return ExtMI;
830}
831
832/// This method must be implemented by targets that
833/// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
834/// may be able to convert a two-address instruction into a true
835/// three-address instruction on demand. This allows the X86 target (for
836/// example) to convert ADD and SHL instructions into LEA instructions if they
837/// would require register copies due to two-addressness.
838///
839/// This method returns a null pointer if the transformation cannot be
840/// performed, otherwise it returns the new instruction.
841///
842MachineInstr *
843X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
844 MachineInstr &MI, LiveVariables *LV) const {
845 // The following opcodes also sets the condition code register(s). Only
846 // convert them to equivalent lea if the condition code register def's
847 // are dead!
848 if (hasLiveCondCodeDef(MI))
849 return nullptr;
850
851 MachineFunction &MF = *MI.getParent()->getParent();
852 // All instructions input are two-addr instructions. Get the known operands.
853 const MachineOperand &Dest = MI.getOperand(0);
854 const MachineOperand &Src = MI.getOperand(1);
855
856 // Ideally, operations with undef should be folded before we get here, but we
857 // can't guarantee it. Bail out because optimizing undefs is a waste of time.
858 // Without this, we have to forward undef state to new register operands to
859 // avoid machine verifier errors.
860 if (Src.isUndef())
861 return nullptr;
862 if (MI.getNumOperands() > 2)
863 if (MI.getOperand(2).isReg() && MI.getOperand(2).isUndef())
864 return nullptr;
865
866 MachineInstr *NewMI = nullptr;
867 bool Is64Bit = Subtarget.is64Bit();
868
869 bool Is8BitOp = false;
870 unsigned MIOpc = MI.getOpcode();
871 switch (MIOpc) {
872 default: llvm_unreachable("Unreachable!")::llvm::llvm_unreachable_internal("Unreachable!", "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 872);
873 case X86::SHL64ri: {
874 assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!")((MI.getNumOperands() >= 3 && "Unknown shift instruction!"
) ? static_cast<void> (0) : __assert_fail ("MI.getNumOperands() >= 3 && \"Unknown shift instruction!\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 874, __PRETTY_FUNCTION__));
875 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
876 if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
877
878 // LEA can't handle RSP.
879 if (TargetRegisterInfo::isVirtualRegister(Src.getReg()) &&
880 !MF.getRegInfo().constrainRegClass(Src.getReg(),
881 &X86::GR64_NOSPRegClass))
882 return nullptr;
883
884 NewMI = BuildMI(MF, MI.getDebugLoc(), get(X86::LEA64r))
885 .add(Dest)
886 .addReg(0)
887 .addImm(1ULL << ShAmt)
888 .add(Src)
889 .addImm(0)
890 .addReg(0);
891 break;
892 }
893 case X86::SHL32ri: {
894 assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!")((MI.getNumOperands() >= 3 && "Unknown shift instruction!"
) ? static_cast<void> (0) : __assert_fail ("MI.getNumOperands() >= 3 && \"Unknown shift instruction!\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 894, __PRETTY_FUNCTION__));
895 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
896 if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
897
898 unsigned Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
899
900 // LEA can't handle ESP.
901 bool isKill;
902 unsigned SrcReg;
903 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
904 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
905 SrcReg, isKill, ImplicitOp, LV))
906 return nullptr;
907
908 MachineInstrBuilder MIB =
909 BuildMI(MF, MI.getDebugLoc(), get(Opc))
910 .add(Dest)
911 .addReg(0)
912 .addImm(1ULL << ShAmt)
913 .addReg(SrcReg, getKillRegState(isKill))
914 .addImm(0)
915 .addReg(0);
916 if (ImplicitOp.getReg() != 0)
917 MIB.add(ImplicitOp);
918 NewMI = MIB;
919
920 break;
921 }
922 case X86::SHL8ri:
923 Is8BitOp = true;
924 LLVM_FALLTHROUGH[[clang::fallthrough]];
925 case X86::SHL16ri: {
926 assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!")((MI.getNumOperands() >= 3 && "Unknown shift instruction!"
) ? static_cast<void> (0) : __assert_fail ("MI.getNumOperands() >= 3 && \"Unknown shift instruction!\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 926, __PRETTY_FUNCTION__));
927 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
928 if (!isTruncatedShiftCountForLEA(ShAmt))
929 return nullptr;
930 return convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV, Is8BitOp);
931 }
932 case X86::INC64r:
933 case X86::INC32r: {
934 assert(MI.getNumOperands() >= 2 && "Unknown inc instruction!")((MI.getNumOperands() >= 2 && "Unknown inc instruction!"
) ? static_cast<void> (0) : __assert_fail ("MI.getNumOperands() >= 2 && \"Unknown inc instruction!\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 934, __PRETTY_FUNCTION__));
935 unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r :
936 (Is64Bit ? X86::LEA64_32r : X86::LEA32r);
937 bool isKill;
938 unsigned SrcReg;
939 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
940 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false, SrcReg, isKill,
941 ImplicitOp, LV))
942 return nullptr;
943
944 MachineInstrBuilder MIB =
945 BuildMI(MF, MI.getDebugLoc(), get(Opc))
946 .add(Dest)
947 .addReg(SrcReg, getKillRegState(isKill));
948 if (ImplicitOp.getReg() != 0)
949 MIB.add(ImplicitOp);
950
951 NewMI = addOffset(MIB, 1);
952 break;
953 }
954 case X86::DEC64r:
955 case X86::DEC32r: {
956 assert(MI.getNumOperands() >= 2 && "Unknown dec instruction!")((MI.getNumOperands() >= 2 && "Unknown dec instruction!"
) ? static_cast<void> (0) : __assert_fail ("MI.getNumOperands() >= 2 && \"Unknown dec instruction!\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 956, __PRETTY_FUNCTION__));
957 unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
958 : (Is64Bit ? X86::LEA64_32r : X86::LEA32r);
959
960 bool isKill;
961 unsigned SrcReg;
962 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
963 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false, SrcReg, isKill,
964 ImplicitOp, LV))
965 return nullptr;
966
967 MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
968 .add(Dest)
969 .addReg(SrcReg, getKillRegState(isKill));
970 if (ImplicitOp.getReg() != 0)
971 MIB.add(ImplicitOp);
972
973 NewMI = addOffset(MIB, -1);
974
975 break;
976 }
977 case X86::DEC8r:
978 case X86::INC8r:
979 Is8BitOp = true;
980 LLVM_FALLTHROUGH[[clang::fallthrough]];
981 case X86::DEC16r:
982 case X86::INC16r:
983 return convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV, Is8BitOp);
984 case X86::ADD64rr:
985 case X86::ADD64rr_DB:
986 case X86::ADD32rr:
987 case X86::ADD32rr_DB: {
988 assert(MI.getNumOperands() >= 3 && "Unknown add instruction!")((MI.getNumOperands() >= 3 && "Unknown add instruction!"
) ? static_cast<void> (0) : __assert_fail ("MI.getNumOperands() >= 3 && \"Unknown add instruction!\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 988, __PRETTY_FUNCTION__));
989 unsigned Opc;
990 if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB)
991 Opc = X86::LEA64r;
992 else
993 Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
994
995 bool isKill;
996 unsigned SrcReg;
997 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
998 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
999 SrcReg, isKill, ImplicitOp, LV))
1000 return nullptr;
1001
1002 const MachineOperand &Src2 = MI.getOperand(2);
1003 bool isKill2;
1004 unsigned SrcReg2;
1005 MachineOperand ImplicitOp2 = MachineOperand::CreateReg(0, false);
1006 if (!classifyLEAReg(MI, Src2, Opc, /*AllowSP=*/ false,
1007 SrcReg2, isKill2, ImplicitOp2, LV))
1008 return nullptr;
1009
1010 MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc)).add(Dest);
1011 if (ImplicitOp.getReg() != 0)
1012 MIB.add(ImplicitOp);
1013 if (ImplicitOp2.getReg() != 0)
1014 MIB.add(ImplicitOp2);
1015
1016 NewMI = addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2);
1017 if (LV && Src2.isKill())
1018 LV->replaceKillInstruction(SrcReg2, MI, *NewMI);
1019 break;
1020 }
1021 case X86::ADD8rr:
1022 case X86::ADD8rr_DB:
1023 Is8BitOp = true;
1024 LLVM_FALLTHROUGH[[clang::fallthrough]];
1025 case X86::ADD16rr:
1026 case X86::ADD16rr_DB:
1027 return convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV, Is8BitOp);
1028 case X86::ADD64ri32:
1029 case X86::ADD64ri8:
1030 case X86::ADD64ri32_DB:
1031 case X86::ADD64ri8_DB:
1032 assert(MI.getNumOperands() >= 3 && "Unknown add instruction!")((MI.getNumOperands() >= 3 && "Unknown add instruction!"
) ? static_cast<void> (0) : __assert_fail ("MI.getNumOperands() >= 3 && \"Unknown add instruction!\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 1032, __PRETTY_FUNCTION__));
1033 NewMI = addOffset(
1034 BuildMI(MF, MI.getDebugLoc(), get(X86::LEA64r)).add(Dest).add(Src),
1035 MI.getOperand(2));
1036 break;
1037 case X86::ADD32ri:
1038 case X86::ADD32ri8:
1039 case X86::ADD32ri_DB:
1040 case X86::ADD32ri8_DB: {
1041 assert(MI.getNumOperands() >= 3 && "Unknown add instruction!")((MI.getNumOperands() >= 3 && "Unknown add instruction!"
) ? static_cast<void> (0) : __assert_fail ("MI.getNumOperands() >= 3 && \"Unknown add instruction!\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 1041, __PRETTY_FUNCTION__));
1042 unsigned Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
1043
1044 bool isKill;
1045 unsigned SrcReg;
1046 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1047 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
1048 SrcReg, isKill, ImplicitOp, LV))
1049 return nullptr;
1050
1051 MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1052 .add(Dest)
1053 .addReg(SrcReg, getKillRegState(isKill));
1054 if (ImplicitOp.getReg() != 0)
1055 MIB.add(ImplicitOp);
1056
1057 NewMI = addOffset(MIB, MI.getOperand(2));
1058 break;
1059 }
1060 case X86::ADD8ri:
1061 case X86::ADD8ri_DB:
1062 Is8BitOp = true;
1063 LLVM_FALLTHROUGH[[clang::fallthrough]];
1064 case X86::ADD16ri:
1065 case X86::ADD16ri8:
1066 case X86::ADD16ri_DB:
1067 case X86::ADD16ri8_DB:
1068 return convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV, Is8BitOp);
1069 case X86::VMOVDQU8Z128rmk:
1070 case X86::VMOVDQU8Z256rmk:
1071 case X86::VMOVDQU8Zrmk:
1072 case X86::VMOVDQU16Z128rmk:
1073 case X86::VMOVDQU16Z256rmk:
1074 case X86::VMOVDQU16Zrmk:
1075 case X86::VMOVDQU32Z128rmk: case X86::VMOVDQA32Z128rmk:
1076 case X86::VMOVDQU32Z256rmk: case X86::VMOVDQA32Z256rmk:
1077 case X86::VMOVDQU32Zrmk: case X86::VMOVDQA32Zrmk:
1078 case X86::VMOVDQU64Z128rmk: case X86::VMOVDQA64Z128rmk:
1079 case X86::VMOVDQU64Z256rmk: case X86::VMOVDQA64Z256rmk:
1080 case X86::VMOVDQU64Zrmk: case X86::VMOVDQA64Zrmk:
1081 case X86::VMOVUPDZ128rmk: case X86::VMOVAPDZ128rmk:
1082 case X86::VMOVUPDZ256rmk: case X86::VMOVAPDZ256rmk:
1083 case X86::VMOVUPDZrmk: case X86::VMOVAPDZrmk:
1084 case X86::VMOVUPSZ128rmk: case X86::VMOVAPSZ128rmk:
1085 case X86::VMOVUPSZ256rmk: case X86::VMOVAPSZ256rmk:
1086 case X86::VMOVUPSZrmk: case X86::VMOVAPSZrmk: {
1087 unsigned Opc;
1088 switch (MIOpc) {
1089 default: llvm_unreachable("Unreachable!")::llvm::llvm_unreachable_internal("Unreachable!", "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 1089);
1090 case X86::VMOVDQU8Z128rmk: Opc = X86::VPBLENDMBZ128rmk; break;
1091 case X86::VMOVDQU8Z256rmk: Opc = X86::VPBLENDMBZ256rmk; break;
1092 case X86::VMOVDQU8Zrmk: Opc = X86::VPBLENDMBZrmk; break;
1093 case X86::VMOVDQU16Z128rmk: Opc = X86::VPBLENDMWZ128rmk; break;
1094 case X86::VMOVDQU16Z256rmk: Opc = X86::VPBLENDMWZ256rmk; break;
1095 case X86::VMOVDQU16Zrmk: Opc = X86::VPBLENDMWZrmk; break;
1096 case X86::VMOVDQU32Z128rmk: Opc = X86::VPBLENDMDZ128rmk; break;
1097 case X86::VMOVDQU32Z256rmk: Opc = X86::VPBLENDMDZ256rmk; break;
1098 case X86::VMOVDQU32Zrmk: Opc = X86::VPBLENDMDZrmk; break;
1099 case X86::VMOVDQU64Z128rmk: Opc = X86::VPBLENDMQZ128rmk; break;
1100 case X86::VMOVDQU64Z256rmk: Opc = X86::VPBLENDMQZ256rmk; break;
1101 case X86::VMOVDQU64Zrmk: Opc = X86::VPBLENDMQZrmk; break;
1102 case X86::VMOVUPDZ128rmk: Opc = X86::VBLENDMPDZ128rmk; break;
1103 case X86::VMOVUPDZ256rmk: Opc = X86::VBLENDMPDZ256rmk; break;
1104 case X86::VMOVUPDZrmk: Opc = X86::VBLENDMPDZrmk; break;
1105 case X86::VMOVUPSZ128rmk: Opc = X86::VBLENDMPSZ128rmk; break;
1106 case X86::VMOVUPSZ256rmk: Opc = X86::VBLENDMPSZ256rmk; break;
1107 case X86::VMOVUPSZrmk: Opc = X86::VBLENDMPSZrmk; break;
1108 case X86::VMOVDQA32Z128rmk: Opc = X86::VPBLENDMDZ128rmk; break;
1109 case X86::VMOVDQA32Z256rmk: Opc = X86::VPBLENDMDZ256rmk; break;
1110 case X86::VMOVDQA32Zrmk: Opc = X86::VPBLENDMDZrmk; break;
1111 case X86::VMOVDQA64Z128rmk: Opc = X86::VPBLENDMQZ128rmk; break;
1112 case X86::VMOVDQA64Z256rmk: Opc = X86::VPBLENDMQZ256rmk; break;
1113 case X86::VMOVDQA64Zrmk: Opc = X86::VPBLENDMQZrmk; break;
1114 case X86::VMOVAPDZ128rmk: Opc = X86::VBLENDMPDZ128rmk; break;
1115 case X86::VMOVAPDZ256rmk: Opc = X86::VBLENDMPDZ256rmk; break;
1116 case X86::VMOVAPDZrmk: Opc = X86::VBLENDMPDZrmk; break;
1117 case X86::VMOVAPSZ128rmk: Opc = X86::VBLENDMPSZ128rmk; break;
1118 case X86::VMOVAPSZ256rmk: Opc = X86::VBLENDMPSZ256rmk; break;
1119 case X86::VMOVAPSZrmk: Opc = X86::VBLENDMPSZrmk; break;
1120 }
1121
1122 NewMI = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1123 .add(Dest)
1124 .add(MI.getOperand(2))
1125 .add(Src)
1126 .add(MI.getOperand(3))
1127 .add(MI.getOperand(4))
1128 .add(MI.getOperand(5))
1129 .add(MI.getOperand(6))
1130 .add(MI.getOperand(7));
1131 break;
1132 }
1133 case X86::VMOVDQU8Z128rrk:
1134 case X86::VMOVDQU8Z256rrk:
1135 case X86::VMOVDQU8Zrrk:
1136 case X86::VMOVDQU16Z128rrk:
1137 case X86::VMOVDQU16Z256rrk:
1138 case X86::VMOVDQU16Zrrk:
1139 case X86::VMOVDQU32Z128rrk: case X86::VMOVDQA32Z128rrk:
1140 case X86::VMOVDQU32Z256rrk: case X86::VMOVDQA32Z256rrk:
1141 case X86::VMOVDQU32Zrrk: case X86::VMOVDQA32Zrrk:
1142 case X86::VMOVDQU64Z128rrk: case X86::VMOVDQA64Z128rrk:
1143 case X86::VMOVDQU64Z256rrk: case X86::VMOVDQA64Z256rrk:
1144 case X86::VMOVDQU64Zrrk: case X86::VMOVDQA64Zrrk:
1145 case X86::VMOVUPDZ128rrk: case X86::VMOVAPDZ128rrk:
1146 case X86::VMOVUPDZ256rrk: case X86::VMOVAPDZ256rrk:
1147 case X86::VMOVUPDZrrk: case X86::VMOVAPDZrrk:
1148 case X86::VMOVUPSZ128rrk: case X86::VMOVAPSZ128rrk:
1149 case X86::VMOVUPSZ256rrk: case X86::VMOVAPSZ256rrk:
1150 case X86::VMOVUPSZrrk: case X86::VMOVAPSZrrk: {
1151 unsigned Opc;
1152 switch (MIOpc) {
1153 default: llvm_unreachable("Unreachable!")::llvm::llvm_unreachable_internal("Unreachable!", "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 1153);
1154 case X86::VMOVDQU8Z128rrk: Opc = X86::VPBLENDMBZ128rrk; break;
1155 case X86::VMOVDQU8Z256rrk: Opc = X86::VPBLENDMBZ256rrk; break;
1156 case X86::VMOVDQU8Zrrk: Opc = X86::VPBLENDMBZrrk; break;
1157 case X86::VMOVDQU16Z128rrk: Opc = X86::VPBLENDMWZ128rrk; break;
1158 case X86::VMOVDQU16Z256rrk: Opc = X86::VPBLENDMWZ256rrk; break;
1159 case X86::VMOVDQU16Zrrk: Opc = X86::VPBLENDMWZrrk; break;
1160 case X86::VMOVDQU32Z128rrk: Opc = X86::VPBLENDMDZ128rrk; break;
1161 case X86::VMOVDQU32Z256rrk: Opc = X86::VPBLENDMDZ256rrk; break;
1162 case X86::VMOVDQU32Zrrk: Opc = X86::VPBLENDMDZrrk; break;
1163 case X86::VMOVDQU64Z128rrk: Opc = X86::VPBLENDMQZ128rrk; break;
1164 case X86::VMOVDQU64Z256rrk: Opc = X86::VPBLENDMQZ256rrk; break;
1165 case X86::VMOVDQU64Zrrk: Opc = X86::VPBLENDMQZrrk; break;
1166 case X86::VMOVUPDZ128rrk: Opc = X86::VBLENDMPDZ128rrk; break;
1167 case X86::VMOVUPDZ256rrk: Opc = X86::VBLENDMPDZ256rrk; break;
1168 case X86::VMOVUPDZrrk: Opc = X86::VBLENDMPDZrrk; break;
1169 case X86::VMOVUPSZ128rrk: Opc = X86::VBLENDMPSZ128rrk; break;
1170 case X86::VMOVUPSZ256rrk: Opc = X86::VBLENDMPSZ256rrk; break;
1171 case X86::VMOVUPSZrrk: Opc = X86::VBLENDMPSZrrk; break;
1172 case X86::VMOVDQA32Z128rrk: Opc = X86::VPBLENDMDZ128rrk; break;
1173 case X86::VMOVDQA32Z256rrk: Opc = X86::VPBLENDMDZ256rrk; break;
1174 case X86::VMOVDQA32Zrrk: Opc = X86::VPBLENDMDZrrk; break;
1175 case X86::VMOVDQA64Z128rrk: Opc = X86::VPBLENDMQZ128rrk; break;
1176 case X86::VMOVDQA64Z256rrk: Opc = X86::VPBLENDMQZ256rrk; break;
1177 case X86::VMOVDQA64Zrrk: Opc = X86::VPBLENDMQZrrk; break;
1178 case X86::VMOVAPDZ128rrk: Opc = X86::VBLENDMPDZ128rrk; break;
1179 case X86::VMOVAPDZ256rrk: Opc = X86::VBLENDMPDZ256rrk; break;
1180 case X86::VMOVAPDZrrk: Opc = X86::VBLENDMPDZrrk; break;
1181 case X86::VMOVAPSZ128rrk: Opc = X86::VBLENDMPSZ128rrk; break;
1182 case X86::VMOVAPSZ256rrk: Opc = X86::VBLENDMPSZ256rrk; break;
1183 case X86::VMOVAPSZrrk: Opc = X86::VBLENDMPSZrrk; break;
1184 }
1185
1186 NewMI = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1187 .add(Dest)
1188 .add(MI.getOperand(2))
1189 .add(Src)
1190 .add(MI.getOperand(3));
1191 break;
1192 }
1193 }
1194
1195 if (!NewMI) return nullptr;
1196
1197 if (LV) { // Update live variables
1198 if (Src.isKill())
1199 LV->replaceKillInstruction(Src.getReg(), MI, *NewMI);
1200 if (Dest.isDead())
1201 LV->replaceKillInstruction(Dest.getReg(), MI, *NewMI);
1202 }
1203
1204 MFI->insert(MI.getIterator(), NewMI); // Insert the new inst
1205 return NewMI;
1206}
1207
1208/// This determines which of three possible cases of a three source commute
1209/// the source indexes correspond to taking into account any mask operands.
1210/// All prevents commuting a passthru operand. Returns -1 if the commute isn't
1211/// possible.
1212/// Case 0 - Possible to commute the first and second operands.
1213/// Case 1 - Possible to commute the first and third operands.
1214/// Case 2 - Possible to commute the second and third operands.
1215static unsigned getThreeSrcCommuteCase(uint64_t TSFlags, unsigned SrcOpIdx1,
1216 unsigned SrcOpIdx2) {
1217 // Put the lowest index to SrcOpIdx1 to simplify the checks below.
1218 if (SrcOpIdx1 > SrcOpIdx2)
1219 std::swap(SrcOpIdx1, SrcOpIdx2);
1220
1221 unsigned Op1 = 1, Op2 = 2, Op3 = 3;
1222 if (X86II::isKMasked(TSFlags)) {
1223 Op2++;
1224 Op3++;
1225 }
1226
1227 if (SrcOpIdx1 == Op1 && SrcOpIdx2 == Op2)
1228 return 0;
1229 if (SrcOpIdx1 == Op1 && SrcOpIdx2 == Op3)
1230 return 1;
1231 if (SrcOpIdx1 == Op2 && SrcOpIdx2 == Op3)
1232 return 2;
1233 llvm_unreachable("Unknown three src commute case.")::llvm::llvm_unreachable_internal("Unknown three src commute case."
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 1233);
1234}
1235
1236unsigned X86InstrInfo::getFMA3OpcodeToCommuteOperands(
1237 const MachineInstr &MI, unsigned SrcOpIdx1, unsigned SrcOpIdx2,
1238 const X86InstrFMA3Group &FMA3Group) const {
1239
1240 unsigned Opc = MI.getOpcode();
1241
1242 // TODO: Commuting the 1st operand of FMA*_Int requires some additional
1243 // analysis. The commute optimization is legal only if all users of FMA*_Int
1244 // use only the lowest element of the FMA*_Int instruction. Such analysis are
1245 // not implemented yet. So, just return 0 in that case.
1246 // When such analysis are available this place will be the right place for
1247 // calling it.
1248 assert(!(FMA3Group.isIntrinsic() && (SrcOpIdx1 == 1 || SrcOpIdx2 == 1)) &&((!(FMA3Group.isIntrinsic() && (SrcOpIdx1 == 1 || SrcOpIdx2
== 1)) && "Intrinsic instructions can't commute operand 1"
) ? static_cast<void> (0) : __assert_fail ("!(FMA3Group.isIntrinsic() && (SrcOpIdx1 == 1 || SrcOpIdx2 == 1)) && \"Intrinsic instructions can't commute operand 1\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 1249, __PRETTY_FUNCTION__))
1249 "Intrinsic instructions can't commute operand 1")((!(FMA3Group.isIntrinsic() && (SrcOpIdx1 == 1 || SrcOpIdx2
== 1)) && "Intrinsic instructions can't commute operand 1"
) ? static_cast<void> (0) : __assert_fail ("!(FMA3Group.isIntrinsic() && (SrcOpIdx1 == 1 || SrcOpIdx2 == 1)) && \"Intrinsic instructions can't commute operand 1\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 1249, __PRETTY_FUNCTION__));
1250
1251 // Determine which case this commute is or if it can't be done.
1252 unsigned Case = getThreeSrcCommuteCase(MI.getDesc().TSFlags, SrcOpIdx1,
1253 SrcOpIdx2);
1254 assert(Case < 3 && "Unexpected case number!")((Case < 3 && "Unexpected case number!") ? static_cast
<void> (0) : __assert_fail ("Case < 3 && \"Unexpected case number!\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 1254, __PRETTY_FUNCTION__));
1255
1256 // Define the FMA forms mapping array that helps to map input FMA form
1257 // to output FMA form to preserve the operation semantics after
1258 // commuting the operands.
1259 const unsigned Form132Index = 0;
1260 const unsigned Form213Index = 1;
1261 const unsigned Form231Index = 2;
1262 static const unsigned FormMapping[][3] = {
1263 // 0: SrcOpIdx1 == 1 && SrcOpIdx2 == 2;
1264 // FMA132 A, C, b; ==> FMA231 C, A, b;
1265 // FMA213 B, A, c; ==> FMA213 A, B, c;
1266 // FMA231 C, A, b; ==> FMA132 A, C, b;
1267 { Form231Index, Form213Index, Form132Index },
1268 // 1: SrcOpIdx1 == 1 && SrcOpIdx2 == 3;
1269 // FMA132 A, c, B; ==> FMA132 B, c, A;
1270 // FMA213 B, a, C; ==> FMA231 C, a, B;
1271 // FMA231 C, a, B; ==> FMA213 B, a, C;
1272 { Form132Index, Form231Index, Form213Index },
1273 // 2: SrcOpIdx1 == 2 && SrcOpIdx2 == 3;
1274 // FMA132 a, C, B; ==> FMA213 a, B, C;
1275 // FMA213 b, A, C; ==> FMA132 b, C, A;
1276 // FMA231 c, A, B; ==> FMA231 c, B, A;
1277 { Form213Index, Form132Index, Form231Index }
1278 };
1279
1280 unsigned FMAForms[3];
1281 FMAForms[0] = FMA3Group.get132Opcode();
1282 FMAForms[1] = FMA3Group.get213Opcode();
1283 FMAForms[2] = FMA3Group.get231Opcode();
1284 unsigned FormIndex;
1285 for (FormIndex = 0; FormIndex < 3; FormIndex++)
1286 if (Opc == FMAForms[FormIndex])
1287 break;
1288
1289 // Everything is ready, just adjust the FMA opcode and return it.
1290 FormIndex = FormMapping[Case][FormIndex];
1291 return FMAForms[FormIndex];
1292}
1293
1294static void commuteVPTERNLOG(MachineInstr &MI, unsigned SrcOpIdx1,
1295 unsigned SrcOpIdx2) {
1296 // Determine which case this commute is or if it can't be done.
1297 unsigned Case = getThreeSrcCommuteCase(MI.getDesc().TSFlags, SrcOpIdx1,
1298 SrcOpIdx2);
1299 assert(Case < 3 && "Unexpected case value!")((Case < 3 && "Unexpected case value!") ? static_cast
<void> (0) : __assert_fail ("Case < 3 && \"Unexpected case value!\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 1299, __PRETTY_FUNCTION__));
1300
1301 // For each case we need to swap two pairs of bits in the final immediate.
1302 static const uint8_t SwapMasks[3][4] = {
1303 { 0x04, 0x10, 0x08, 0x20 }, // Swap bits 2/4 and 3/5.
1304 { 0x02, 0x10, 0x08, 0x40 }, // Swap bits 1/4 and 3/6.
1305 { 0x02, 0x04, 0x20, 0x40 }, // Swap bits 1/2 and 5/6.
1306 };
1307
1308 uint8_t Imm = MI.getOperand(MI.getNumOperands()-1).getImm();
1309 // Clear out the bits we are swapping.
1310 uint8_t NewImm = Imm & ~(SwapMasks[Case][0] | SwapMasks[Case][1] |
1311 SwapMasks[Case][2] | SwapMasks[Case][3]);
1312 // If the immediate had a bit of the pair set, then set the opposite bit.
1313 if (Imm & SwapMasks[Case][0]) NewImm |= SwapMasks[Case][1];
1314 if (Imm & SwapMasks[Case][1]) NewImm |= SwapMasks[Case][0];
1315 if (Imm & SwapMasks[Case][2]) NewImm |= SwapMasks[Case][3];
1316 if (Imm & SwapMasks[Case][3]) NewImm |= SwapMasks[Case][2];
1317 MI.getOperand(MI.getNumOperands()-1).setImm(NewImm);
1318}
1319
1320// Returns true if this is a VPERMI2 or VPERMT2 instruction that can be
1321// commuted.
1322static bool isCommutableVPERMV3Instruction(unsigned Opcode) {
1323#define VPERM_CASES(Suffix) \
1324 case X86::VPERMI2##Suffix##128rr: case X86::VPERMT2##Suffix##128rr: \
1325 case X86::VPERMI2##Suffix##256rr: case X86::VPERMT2##Suffix##256rr: \
1326 case X86::VPERMI2##Suffix##rr: case X86::VPERMT2##Suffix##rr: \
1327 case X86::VPERMI2##Suffix##128rm: case X86::VPERMT2##Suffix##128rm: \
1328 case X86::VPERMI2##Suffix##256rm: case X86::VPERMT2##Suffix##256rm: \
1329 case X86::VPERMI2##Suffix##rm: case X86::VPERMT2##Suffix##rm: \
1330 case X86::VPERMI2##Suffix##128rrkz: case X86::VPERMT2##Suffix##128rrkz: \
1331 case X86::VPERMI2##Suffix##256rrkz: case X86::VPERMT2##Suffix##256rrkz: \
1332 case X86::VPERMI2##Suffix##rrkz: case X86::VPERMT2##Suffix##rrkz: \
1333 case X86::VPERMI2##Suffix##128rmkz: case X86::VPERMT2##Suffix##128rmkz: \
1334 case X86::VPERMI2##Suffix##256rmkz: case X86::VPERMT2##Suffix##256rmkz: \
1335 case X86::VPERMI2##Suffix##rmkz: case X86::VPERMT2##Suffix##rmkz:
1336
1337#define VPERM_CASES_BROADCAST(Suffix) \
1338 VPERM_CASES(Suffix) \
1339 case X86::VPERMI2##Suffix##128rmb: case X86::VPERMT2##Suffix##128rmb: \
1340 case X86::VPERMI2##Suffix##256rmb: case X86::VPERMT2##Suffix##256rmb: \
1341 case X86::VPERMI2##Suffix##rmb: case X86::VPERMT2##Suffix##rmb: \
1342 case X86::VPERMI2##Suffix##128rmbkz: case X86::VPERMT2##Suffix##128rmbkz: \
1343 case X86::VPERMI2##Suffix##256rmbkz: case X86::VPERMT2##Suffix##256rmbkz: \
1344 case X86::VPERMI2##Suffix##rmbkz: case X86::VPERMT2##Suffix##rmbkz:
1345
1346 switch (Opcode) {
1347 default: return false;
1348 VPERM_CASES(B)
1349 VPERM_CASES_BROADCAST(D)
1350 VPERM_CASES_BROADCAST(PD)
1351 VPERM_CASES_BROADCAST(PS)
1352 VPERM_CASES_BROADCAST(Q)
1353 VPERM_CASES(W)
1354 return true;
1355 }
1356#undef VPERM_CASES_BROADCAST
1357#undef VPERM_CASES
1358}
1359
1360// Returns commuted opcode for VPERMI2 and VPERMT2 instructions by switching
1361// from the I opcode to the T opcode and vice versa.
1362static unsigned getCommutedVPERMV3Opcode(unsigned Opcode) {
1363#define VPERM_CASES(Orig, New) \
1364 case X86::Orig##128rr: return X86::New##128rr; \
1365 case X86::Orig##128rrkz: return X86::New##128rrkz; \
1366 case X86::Orig##128rm: return X86::New##128rm; \
1367 case X86::Orig##128rmkz: return X86::New##128rmkz; \
1368 case X86::Orig##256rr: return X86::New##256rr; \
1369 case X86::Orig##256rrkz: return X86::New##256rrkz; \
1370 case X86::Orig##256rm: return X86::New##256rm; \
1371 case X86::Orig##256rmkz: return X86::New##256rmkz; \
1372 case X86::Orig##rr: return X86::New##rr; \
1373 case X86::Orig##rrkz: return X86::New##rrkz; \
1374 case X86::Orig##rm: return X86::New##rm; \
1375 case X86::Orig##rmkz: return X86::New##rmkz;
1376
1377#define VPERM_CASES_BROADCAST(Orig, New) \
1378 VPERM_CASES(Orig, New) \
1379 case X86::Orig##128rmb: return X86::New##128rmb; \
1380 case X86::Orig##128rmbkz: return X86::New##128rmbkz; \
1381 case X86::Orig##256rmb: return X86::New##256rmb; \
1382 case X86::Orig##256rmbkz: return X86::New##256rmbkz; \
1383 case X86::Orig##rmb: return X86::New##rmb; \
1384 case X86::Orig##rmbkz: return X86::New##rmbkz;
1385
1386 switch (Opcode) {
1387 VPERM_CASES(VPERMI2B, VPERMT2B)
1388 VPERM_CASES_BROADCAST(VPERMI2D, VPERMT2D)
1389 VPERM_CASES_BROADCAST(VPERMI2PD, VPERMT2PD)
1390 VPERM_CASES_BROADCAST(VPERMI2PS, VPERMT2PS)
1391 VPERM_CASES_BROADCAST(VPERMI2Q, VPERMT2Q)
1392 VPERM_CASES(VPERMI2W, VPERMT2W)
1393 VPERM_CASES(VPERMT2B, VPERMI2B)
1394 VPERM_CASES_BROADCAST(VPERMT2D, VPERMI2D)
1395 VPERM_CASES_BROADCAST(VPERMT2PD, VPERMI2PD)
1396 VPERM_CASES_BROADCAST(VPERMT2PS, VPERMI2PS)
1397 VPERM_CASES_BROADCAST(VPERMT2Q, VPERMI2Q)
1398 VPERM_CASES(VPERMT2W, VPERMI2W)
1399 }
1400
1401 llvm_unreachable("Unreachable!")::llvm::llvm_unreachable_internal("Unreachable!", "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 1401);
1402#undef VPERM_CASES_BROADCAST
1403#undef VPERM_CASES
1404}
1405
1406MachineInstr *X86InstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI,
1407 unsigned OpIdx1,
1408 unsigned OpIdx2) const {
1409 auto cloneIfNew = [NewMI](MachineInstr &MI) -> MachineInstr & {
1410 if (NewMI)
1411 return *MI.getParent()->getParent()->CloneMachineInstr(&MI);
1412 return MI;
1413 };
1414
1415 switch (MI.getOpcode()) {
1416 case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
1417 case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
1418 case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
1419 case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
1420 case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
1421 case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
1422 unsigned Opc;
1423 unsigned Size;
1424 switch (MI.getOpcode()) {
1425 default: llvm_unreachable("Unreachable!")::llvm::llvm_unreachable_internal("Unreachable!", "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 1425);
1426 case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
1427 case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
1428 case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
1429 case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
1430 case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
1431 case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
1432 }
1433 unsigned Amt = MI.getOperand(3).getImm();
1434 auto &WorkingMI = cloneIfNew(MI);
1435 WorkingMI.setDesc(get(Opc));
1436 WorkingMI.getOperand(3).setImm(Size - Amt);
1437 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1438 OpIdx1, OpIdx2);
1439 }
1440 case X86::PFSUBrr:
1441 case X86::PFSUBRrr: {
1442 // PFSUB x, y: x = x - y
1443 // PFSUBR x, y: x = y - x
1444 unsigned Opc =
1445 (X86::PFSUBRrr == MI.getOpcode() ? X86::PFSUBrr : X86::PFSUBRrr);
1446 auto &WorkingMI = cloneIfNew(MI);
1447 WorkingMI.setDesc(get(Opc));
1448 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1449 OpIdx1, OpIdx2);
1450 }
1451 case X86::BLENDPDrri:
1452 case X86::BLENDPSrri:
1453 case X86::VBLENDPDrri:
1454 case X86::VBLENDPSrri:
1455 // If we're optimizing for size, try to use MOVSD/MOVSS.
1456 if (MI.getParent()->getParent()->getFunction().hasOptSize()) {
1457 unsigned Mask, Opc;
1458 switch (MI.getOpcode()) {
1459 default: llvm_unreachable("Unreachable!")::llvm::llvm_unreachable_internal("Unreachable!", "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 1459);
1460 case X86::BLENDPDrri: Opc = X86::MOVSDrr; Mask = 0x03; break;
1461 case X86::BLENDPSrri: Opc = X86::MOVSSrr; Mask = 0x0F; break;
1462 case X86::VBLENDPDrri: Opc = X86::VMOVSDrr; Mask = 0x03; break;
1463 case X86::VBLENDPSrri: Opc = X86::VMOVSSrr; Mask = 0x0F; break;
1464 }
1465 if ((MI.getOperand(3).getImm() ^ Mask) == 1) {
1466 auto &WorkingMI = cloneIfNew(MI);
1467 WorkingMI.setDesc(get(Opc));
1468 WorkingMI.RemoveOperand(3);
1469 return TargetInstrInfo::commuteInstructionImpl(WorkingMI,
1470 /*NewMI=*/false,
1471 OpIdx1, OpIdx2);
1472 }
1473 }
1474 LLVM_FALLTHROUGH[[clang::fallthrough]];
1475 case X86::PBLENDWrri:
1476 case X86::VBLENDPDYrri:
1477 case X86::VBLENDPSYrri:
1478 case X86::VPBLENDDrri:
1479 case X86::VPBLENDWrri:
1480 case X86::VPBLENDDYrri:
1481 case X86::VPBLENDWYrri:{
1482 int8_t Mask;
1483 switch (MI.getOpcode()) {
1484 default: llvm_unreachable("Unreachable!")::llvm::llvm_unreachable_internal("Unreachable!", "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 1484);
1485 case X86::BLENDPDrri: Mask = (int8_t)0x03; break;
1486 case X86::BLENDPSrri: Mask = (int8_t)0x0F; break;
1487 case X86::PBLENDWrri: Mask = (int8_t)0xFF; break;
1488 case X86::VBLENDPDrri: Mask = (int8_t)0x03; break;
1489 case X86::VBLENDPSrri: Mask = (int8_t)0x0F; break;
1490 case X86::VBLENDPDYrri: Mask = (int8_t)0x0F; break;
1491 case X86::VBLENDPSYrri: Mask = (int8_t)0xFF; break;
1492 case X86::VPBLENDDrri: Mask = (int8_t)0x0F; break;
1493 case X86::VPBLENDWrri: Mask = (int8_t)0xFF; break;
1494 case X86::VPBLENDDYrri: Mask = (int8_t)0xFF; break;
1495 case X86::VPBLENDWYrri: Mask = (int8_t)0xFF; break;
1496 }
1497 // Only the least significant bits of Imm are used.
1498 // Using int8_t to ensure it will be sign extended to the int64_t that
1499 // setImm takes in order to match isel behavior.
1500 int8_t Imm = MI.getOperand(3).getImm() & Mask;
1501 auto &WorkingMI = cloneIfNew(MI);
1502 WorkingMI.getOperand(3).setImm(Mask ^ Imm);
1503 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1504 OpIdx1, OpIdx2);
1505 }
1506 case X86::INSERTPSrr:
1507 case X86::VINSERTPSrr:
1508 case X86::VINSERTPSZrr: {
1509 unsigned Imm = MI.getOperand(MI.getNumOperands() - 1).getImm();
1510 unsigned ZMask = Imm & 15;
1511 unsigned DstIdx = (Imm >> 4) & 3;
1512 unsigned SrcIdx = (Imm >> 6) & 3;
1513
1514 // We can commute insertps if we zero 2 of the elements, the insertion is
1515 // "inline" and we don't override the insertion with a zero.
1516 if (DstIdx == SrcIdx && (ZMask & (1 << DstIdx)) == 0 &&
1517 countPopulation(ZMask) == 2) {
1518 unsigned AltIdx = findFirstSet((ZMask | (1 << DstIdx)) ^ 15);
1519 assert(AltIdx < 4 && "Illegal insertion index")((AltIdx < 4 && "Illegal insertion index") ? static_cast
<void> (0) : __assert_fail ("AltIdx < 4 && \"Illegal insertion index\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 1519, __PRETTY_FUNCTION__));
1520 unsigned AltImm = (AltIdx << 6) | (AltIdx << 4) | ZMask;
1521 auto &WorkingMI = cloneIfNew(MI);
1522 WorkingMI.getOperand(MI.getNumOperands() - 1).setImm(AltImm);
1523 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1524 OpIdx1, OpIdx2);
1525 }
1526 return nullptr;
1527 }
1528 case X86::MOVSDrr:
1529 case X86::MOVSSrr:
1530 case X86::VMOVSDrr:
1531 case X86::VMOVSSrr:{
1532 // On SSE41 or later we can commute a MOVSS/MOVSD to a BLENDPS/BLENDPD.
1533 assert(Subtarget.hasSSE41() && "Commuting MOVSD/MOVSS requires SSE41!")((Subtarget.hasSSE41() && "Commuting MOVSD/MOVSS requires SSE41!"
) ? static_cast<void> (0) : __assert_fail ("Subtarget.hasSSE41() && \"Commuting MOVSD/MOVSS requires SSE41!\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 1533, __PRETTY_FUNCTION__));
1534
1535 unsigned Mask, Opc;
1536 switch (MI.getOpcode()) {
1537 default: llvm_unreachable("Unreachable!")::llvm::llvm_unreachable_internal("Unreachable!", "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 1537);
1538 case X86::MOVSDrr: Opc = X86::BLENDPDrri; Mask = 0x02; break;
1539 case X86::MOVSSrr: Opc = X86::BLENDPSrri; Mask = 0x0E; break;
1540 case X86::VMOVSDrr: Opc = X86::VBLENDPDrri; Mask = 0x02; break;
1541 case X86::VMOVSSrr: Opc = X86::VBLENDPSrri; Mask = 0x0E; break;
1542 }
1543
1544 auto &WorkingMI = cloneIfNew(MI);
1545 WorkingMI.setDesc(get(Opc));
1546 WorkingMI.addOperand(MachineOperand::CreateImm(Mask));
1547 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1548 OpIdx1, OpIdx2);
1549 }
1550 case X86::PCLMULQDQrr:
1551 case X86::VPCLMULQDQrr:
1552 case X86::VPCLMULQDQYrr:
1553 case X86::VPCLMULQDQZrr:
1554 case X86::VPCLMULQDQZ128rr:
1555 case X86::VPCLMULQDQZ256rr: {
1556 // SRC1 64bits = Imm[0] ? SRC1[127:64] : SRC1[63:0]
1557 // SRC2 64bits = Imm[4] ? SRC2[127:64] : SRC2[63:0]
1558 unsigned Imm = MI.getOperand(3).getImm();
1559 unsigned Src1Hi = Imm & 0x01;
1560 unsigned Src2Hi = Imm & 0x10;
1561 auto &WorkingMI = cloneIfNew(MI);
1562 WorkingMI.getOperand(3).setImm((Src1Hi << 4) | (Src2Hi >> 4));
1563 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1564 OpIdx1, OpIdx2);
1565 }
1566 case X86::VPCMPBZ128rri: case X86::VPCMPUBZ128rri:
1567 case X86::VPCMPBZ256rri: case X86::VPCMPUBZ256rri:
1568 case X86::VPCMPBZrri: case X86::VPCMPUBZrri:
1569 case X86::VPCMPDZ128rri: case X86::VPCMPUDZ128rri:
1570 case X86::VPCMPDZ256rri: case X86::VPCMPUDZ256rri:
1571 case X86::VPCMPDZrri: case X86::VPCMPUDZrri:
1572 case X86::VPCMPQZ128rri: case X86::VPCMPUQZ128rri:
1573 case X86::VPCMPQZ256rri: case X86::VPCMPUQZ256rri:
1574 case X86::VPCMPQZrri: case X86::VPCMPUQZrri:
1575 case X86::VPCMPWZ128rri: case X86::VPCMPUWZ128rri:
1576 case X86::VPCMPWZ256rri: case X86::VPCMPUWZ256rri:
1577 case X86::VPCMPWZrri: case X86::VPCMPUWZrri:
1578 case X86::VPCMPBZ128rrik: case X86::VPCMPUBZ128rrik:
1579 case X86::VPCMPBZ256rrik: case X86::VPCMPUBZ256rrik:
1580 case X86::VPCMPBZrrik: case X86::VPCMPUBZrrik:
1581 case X86::VPCMPDZ128rrik: case X86::VPCMPUDZ128rrik:
1582 case X86::VPCMPDZ256rrik: case X86::VPCMPUDZ256rrik:
1583 case X86::VPCMPDZrrik: case X86::VPCMPUDZrrik:
1584 case X86::VPCMPQZ128rrik: case X86::VPCMPUQZ128rrik:
1585 case X86::VPCMPQZ256rrik: case X86::VPCMPUQZ256rrik:
1586 case X86::VPCMPQZrrik: case X86::VPCMPUQZrrik:
1587 case X86::VPCMPWZ128rrik: case X86::VPCMPUWZ128rrik:
1588 case X86::VPCMPWZ256rrik: case X86::VPCMPUWZ256rrik:
1589 case X86::VPCMPWZrrik: case X86::VPCMPUWZrrik: {
1590 // Flip comparison mode immediate (if necessary).
1591 unsigned Imm = MI.getOperand(MI.getNumOperands() - 1).getImm() & 0x7;
1592 Imm = X86::getSwappedVPCMPImm(Imm);
1593 auto &WorkingMI = cloneIfNew(MI);
1594 WorkingMI.getOperand(MI.getNumOperands() - 1).setImm(Imm);
1595 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1596 OpIdx1, OpIdx2);
1597 }
1598 case X86::VPCOMBri: case X86::VPCOMUBri:
1599 case X86::VPCOMDri: case X86::VPCOMUDri:
1600 case X86::VPCOMQri: case X86::VPCOMUQri:
1601 case X86::VPCOMWri: case X86::VPCOMUWri: {
1602 // Flip comparison mode immediate (if necessary).
1603 unsigned Imm = MI.getOperand(3).getImm() & 0x7;
1604 Imm = X86::getSwappedVPCOMImm(Imm);
1605 auto &WorkingMI = cloneIfNew(MI);
1606 WorkingMI.getOperand(3).setImm(Imm);
1607 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1608 OpIdx1, OpIdx2);
1609 }
1610 case X86::VPERM2F128rr:
1611 case X86::VPERM2I128rr: {
1612 // Flip permute source immediate.
1613 // Imm & 0x02: lo = if set, select Op1.lo/hi else Op0.lo/hi.
1614 // Imm & 0x20: hi = if set, select Op1.lo/hi else Op0.lo/hi.
1615 int8_t Imm = MI.getOperand(3).getImm() & 0xFF;
1616 auto &WorkingMI = cloneIfNew(MI);
1617 WorkingMI.getOperand(3).setImm(Imm ^ 0x22);
1618 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1619 OpIdx1, OpIdx2);
1620 }
1621 case X86::MOVHLPSrr:
1622 case X86::UNPCKHPDrr:
1623 case X86::VMOVHLPSrr:
1624 case X86::VUNPCKHPDrr:
1625 case X86::VMOVHLPSZrr:
1626 case X86::VUNPCKHPDZ128rr: {
1627 assert(Subtarget.hasSSE2() && "Commuting MOVHLP/UNPCKHPD requires SSE2!")((Subtarget.hasSSE2() && "Commuting MOVHLP/UNPCKHPD requires SSE2!"
) ? static_cast<void> (0) : __assert_fail ("Subtarget.hasSSE2() && \"Commuting MOVHLP/UNPCKHPD requires SSE2!\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 1627, __PRETTY_FUNCTION__));
1628
1629 unsigned Opc = MI.getOpcode();
1630 switch (Opc) {
1631 default: llvm_unreachable("Unreachable!")::llvm::llvm_unreachable_internal("Unreachable!", "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 1631);
1632 case X86::MOVHLPSrr: Opc = X86::UNPCKHPDrr; break;
1633 case X86::UNPCKHPDrr: Opc = X86::MOVHLPSrr; break;
1634 case X86::VMOVHLPSrr: Opc = X86::VUNPCKHPDrr; break;
1635 case X86::VUNPCKHPDrr: Opc = X86::VMOVHLPSrr; break;
1636 case X86::VMOVHLPSZrr: Opc = X86::VUNPCKHPDZ128rr; break;
1637 case X86::VUNPCKHPDZ128rr: Opc = X86::VMOVHLPSZrr; break;
1638 }
1639 auto &WorkingMI = cloneIfNew(MI);
1640 WorkingMI.setDesc(get(Opc));
1641 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1642 OpIdx1, OpIdx2);
1643 }
1644 case X86::CMOV16rr: case X86::CMOV32rr: case X86::CMOV64rr: {
1645 auto &WorkingMI = cloneIfNew(MI);
1646 unsigned OpNo = MI.getDesc().getNumOperands() - 1;
1647 X86::CondCode CC = static_cast<X86::CondCode>(MI.getOperand(OpNo).getImm());
1648 WorkingMI.getOperand(OpNo).setImm(X86::GetOppositeBranchCondition(CC));
1649 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1650 OpIdx1, OpIdx2);
1651 }
1652 case X86::VPTERNLOGDZrri: case X86::VPTERNLOGDZrmi:
1653 case X86::VPTERNLOGDZ128rri: case X86::VPTERNLOGDZ128rmi:
1654 case X86::VPTERNLOGDZ256rri: case X86::VPTERNLOGDZ256rmi:
1655 case X86::VPTERNLOGQZrri: case X86::VPTERNLOGQZrmi:
1656 case X86::VPTERNLOGQZ128rri: case X86::VPTERNLOGQZ128rmi:
1657 case X86::VPTERNLOGQZ256rri: case X86::VPTERNLOGQZ256rmi:
1658 case X86::VPTERNLOGDZrrik:
1659 case X86::VPTERNLOGDZ128rrik:
1660 case X86::VPTERNLOGDZ256rrik:
1661 case X86::VPTERNLOGQZrrik:
1662 case X86::VPTERNLOGQZ128rrik:
1663 case X86::VPTERNLOGQZ256rrik:
1664 case X86::VPTERNLOGDZrrikz: case X86::VPTERNLOGDZrmikz:
1665 case X86::VPTERNLOGDZ128rrikz: case X86::VPTERNLOGDZ128rmikz:
1666 case X86::VPTERNLOGDZ256rrikz: case X86::VPTERNLOGDZ256rmikz:
1667 case X86::VPTERNLOGQZrrikz: case X86::VPTERNLOGQZrmikz:
1668 case X86::VPTERNLOGQZ128rrikz: case X86::VPTERNLOGQZ128rmikz:
1669 case X86::VPTERNLOGQZ256rrikz: case X86::VPTERNLOGQZ256rmikz:
1670 case X86::VPTERNLOGDZ128rmbi:
1671 case X86::VPTERNLOGDZ256rmbi:
1672 case X86::VPTERNLOGDZrmbi:
1673 case X86::VPTERNLOGQZ128rmbi:
1674 case X86::VPTERNLOGQZ256rmbi:
1675 case X86::VPTERNLOGQZrmbi:
1676 case X86::VPTERNLOGDZ128rmbikz:
1677 case X86::VPTERNLOGDZ256rmbikz:
1678 case X86::VPTERNLOGDZrmbikz:
1679 case X86::VPTERNLOGQZ128rmbikz:
1680 case X86::VPTERNLOGQZ256rmbikz:
1681 case X86::VPTERNLOGQZrmbikz: {
1682 auto &WorkingMI = cloneIfNew(MI);
1683 commuteVPTERNLOG(WorkingMI, OpIdx1, OpIdx2);
1684 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1685 OpIdx1, OpIdx2);
1686 }
1687 default: {
1688 if (isCommutableVPERMV3Instruction(MI.getOpcode())) {
1689 unsigned Opc = getCommutedVPERMV3Opcode(MI.getOpcode());
1690 auto &WorkingMI = cloneIfNew(MI);
1691 WorkingMI.setDesc(get(Opc));
1692 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1693 OpIdx1, OpIdx2);
1694 }
1695
1696 const X86InstrFMA3Group *FMA3Group = getFMA3Group(MI.getOpcode(),
1697 MI.getDesc().TSFlags);
1698 if (FMA3Group) {
1699 unsigned Opc =
1700 getFMA3OpcodeToCommuteOperands(MI, OpIdx1, OpIdx2, *FMA3Group);
1701 auto &WorkingMI = cloneIfNew(MI);
1702 WorkingMI.setDesc(get(Opc));
1703 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1704 OpIdx1, OpIdx2);
1705 }
1706
1707 return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
1708 }
1709 }
1710}
1711
1712bool
1713X86InstrInfo::findThreeSrcCommutedOpIndices(const MachineInstr &MI,
1714 unsigned &SrcOpIdx1,
1715 unsigned &SrcOpIdx2,
1716 bool IsIntrinsic) const {
1717 uint64_t TSFlags = MI.getDesc().TSFlags;
1718
1719 unsigned FirstCommutableVecOp = 1;
1720 unsigned LastCommutableVecOp = 3;
1721 unsigned KMaskOp = -1U;
1722 if (X86II::isKMasked(TSFlags)) {
1723 // For k-zero-masked operations it is Ok to commute the first vector
1724 // operand.
1725 // For regular k-masked operations a conservative choice is done as the
1726 // elements of the first vector operand, for which the corresponding bit
1727 // in the k-mask operand is set to 0, are copied to the result of the
1728 // instruction.
1729 // TODO/FIXME: The commute still may be legal if it is known that the
1730 // k-mask operand is set to either all ones or all zeroes.
1731 // It is also Ok to commute the 1st operand if all users of MI use only
1732 // the elements enabled by the k-mask operand. For example,
1733 // v4 = VFMADD213PSZrk v1, k, v2, v3; // v1[i] = k[i] ? v2[i]*v1[i]+v3[i]
1734 // : v1[i];
1735 // VMOVAPSZmrk <mem_addr>, k, v4; // this is the ONLY user of v4 ->
1736 // // Ok, to commute v1 in FMADD213PSZrk.
1737
1738 // The k-mask operand has index = 2 for masked and zero-masked operations.
1739 KMaskOp = 2;
1740
1741 // The operand with index = 1 is used as a source for those elements for
1742 // which the corresponding bit in the k-mask is set to 0.
1743 if (X86II::isKMergeMasked(TSFlags))
1744 FirstCommutableVecOp = 3;
1745
1746 LastCommutableVecOp++;
1747 } else if (IsIntrinsic) {
1748 // Commuting the first operand of an intrinsic instruction isn't possible
1749 // unless we can prove that only the lowest element of the result is used.
1750 FirstCommutableVecOp = 2;
1751 }
1752
1753 if (isMem(MI, LastCommutableVecOp))
1754 LastCommutableVecOp--;
1755
1756 // Only the first RegOpsNum operands are commutable.
1757 // Also, the value 'CommuteAnyOperandIndex' is valid here as it means
1758 // that the operand is not specified/fixed.
1759 if (SrcOpIdx1 != CommuteAnyOperandIndex &&
1760 (SrcOpIdx1 < FirstCommutableVecOp || SrcOpIdx1 > LastCommutableVecOp ||
1761 SrcOpIdx1 == KMaskOp))
1762 return false;
1763 if (SrcOpIdx2 != CommuteAnyOperandIndex &&
1764 (SrcOpIdx2 < FirstCommutableVecOp || SrcOpIdx2 > LastCommutableVecOp ||
1765 SrcOpIdx2 == KMaskOp))
1766 return false;
1767
1768 // Look for two different register operands assumed to be commutable
1769 // regardless of the FMA opcode. The FMA opcode is adjusted later.
1770 if (SrcOpIdx1 == CommuteAnyOperandIndex ||
1771 SrcOpIdx2 == CommuteAnyOperandIndex) {
1772 unsigned CommutableOpIdx2 = SrcOpIdx2;
1773
1774 // At least one of operands to be commuted is not specified and
1775 // this method is free to choose appropriate commutable operands.
1776 if (SrcOpIdx1 == SrcOpIdx2)
1777 // Both of operands are not fixed. By default set one of commutable
1778 // operands to the last register operand of the instruction.
1779 CommutableOpIdx2 = LastCommutableVecOp;
1780 else if (SrcOpIdx2 == CommuteAnyOperandIndex)
1781 // Only one of operands is not fixed.
1782 CommutableOpIdx2 = SrcOpIdx1;
1783
1784 // CommutableOpIdx2 is well defined now. Let's choose another commutable
1785 // operand and assign its index to CommutableOpIdx1.
1786 unsigned Op2Reg = MI.getOperand(CommutableOpIdx2).getReg();
1787
1788 unsigned CommutableOpIdx1;
1789 for (CommutableOpIdx1 = LastCommutableVecOp;
1790 CommutableOpIdx1 >= FirstCommutableVecOp; CommutableOpIdx1--) {
1791 // Just ignore and skip the k-mask operand.
1792 if (CommutableOpIdx1 == KMaskOp)
1793 continue;
1794
1795 // The commuted operands must have different registers.
1796 // Otherwise, the commute transformation does not change anything and
1797 // is useless then.
1798 if (Op2Reg != MI.getOperand(CommutableOpIdx1).getReg())
1799 break;
1800 }
1801
1802 // No appropriate commutable operands were found.
1803 if (CommutableOpIdx1 < FirstCommutableVecOp)
1804 return false;
1805
1806 // Assign the found pair of commutable indices to SrcOpIdx1 and SrcOpidx2
1807 // to return those values.
1808 if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
1809 CommutableOpIdx1, CommutableOpIdx2))
1810 return false;
1811 }
1812
1813 return true;
1814}
1815
1816bool X86InstrInfo::findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1,
1817 unsigned &SrcOpIdx2) const {
1818 const MCInstrDesc &Desc = MI.getDesc();
1819 if (!Desc.isCommutable())
1820 return false;
1821
1822 switch (MI.getOpcode()) {
1823 case X86::CMPSDrr:
1824 case X86::CMPSSrr:
1825 case X86::CMPPDrri:
1826 case X86::CMPPSrri:
1827 case X86::VCMPSDrr:
1828 case X86::VCMPSSrr:
1829 case X86::VCMPPDrri:
1830 case X86::VCMPPSrri:
1831 case X86::VCMPPDYrri:
1832 case X86::VCMPPSYrri:
1833 case X86::VCMPSDZrr:
1834 case X86::VCMPSSZrr:
1835 case X86::VCMPPDZrri:
1836 case X86::VCMPPSZrri:
1837 case X86::VCMPPDZ128rri:
1838 case X86::VCMPPSZ128rri:
1839 case X86::VCMPPDZ256rri:
1840 case X86::VCMPPSZ256rri: {
1841 // Float comparison can be safely commuted for
1842 // Ordered/Unordered/Equal/NotEqual tests
1843 unsigned Imm = MI.getOperand(3).getImm() & 0x7;
1844 switch (Imm) {
1845 case 0x00: // EQUAL
1846 case 0x03: // UNORDERED
1847 case 0x04: // NOT EQUAL
1848 case 0x07: // ORDERED
1849 // The indices of the commutable operands are 1 and 2.
1850 // Assign them to the returned operand indices here.
1851 return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 1, 2);
1852 }
1853 return false;
1854 }
1855 case X86::MOVSDrr:
1856 case X86::MOVSSrr:
1857 case X86::VMOVSDrr:
1858 case X86::VMOVSSrr:
1859 if (Subtarget.hasSSE41())
1860 return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
1861 return false;
1862 case X86::MOVHLPSrr:
1863 case X86::UNPCKHPDrr:
1864 case X86::VMOVHLPSrr:
1865 case X86::VUNPCKHPDrr:
1866 case X86::VMOVHLPSZrr:
1867 case X86::VUNPCKHPDZ128rr:
1868 if (Subtarget.hasSSE2())
1869 return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
1870 return false;
1871 case X86::VPTERNLOGDZrri: case X86::VPTERNLOGDZrmi:
1872 case X86::VPTERNLOGDZ128rri: case X86::VPTERNLOGDZ128rmi:
1873 case X86::VPTERNLOGDZ256rri: case X86::VPTERNLOGDZ256rmi:
1874 case X86::VPTERNLOGQZrri: case X86::VPTERNLOGQZrmi:
1875 case X86::VPTERNLOGQZ128rri: case X86::VPTERNLOGQZ128rmi:
1876 case X86::VPTERNLOGQZ256rri: case X86::VPTERNLOGQZ256rmi:
1877 case X86::VPTERNLOGDZrrik:
1878 case X86::VPTERNLOGDZ128rrik:
1879 case X86::VPTERNLOGDZ256rrik:
1880 case X86::VPTERNLOGQZrrik:
1881 case X86::VPTERNLOGQZ128rrik:
1882 case X86::VPTERNLOGQZ256rrik:
1883 case X86::VPTERNLOGDZrrikz: case X86::VPTERNLOGDZrmikz:
1884 case X86::VPTERNLOGDZ128rrikz: case X86::VPTERNLOGDZ128rmikz:
1885 case X86::VPTERNLOGDZ256rrikz: case X86::VPTERNLOGDZ256rmikz:
1886 case X86::VPTERNLOGQZrrikz: case X86::VPTERNLOGQZrmikz:
1887 case X86::VPTERNLOGQZ128rrikz: case X86::VPTERNLOGQZ128rmikz:
1888 case X86::VPTERNLOGQZ256rrikz: case X86::VPTERNLOGQZ256rmikz:
1889 case X86::VPTERNLOGDZ128rmbi:
1890 case X86::VPTERNLOGDZ256rmbi:
1891 case X86::VPTERNLOGDZrmbi:
1892 case X86::VPTERNLOGQZ128rmbi:
1893 case X86::VPTERNLOGQZ256rmbi:
1894 case X86::VPTERNLOGQZrmbi:
1895 case X86::VPTERNLOGDZ128rmbikz:
1896 case X86::VPTERNLOGDZ256rmbikz:
1897 case X86::VPTERNLOGDZrmbikz:
1898 case X86::VPTERNLOGQZ128rmbikz:
1899 case X86::VPTERNLOGQZ256rmbikz:
1900 case X86::VPTERNLOGQZrmbikz:
1901 return findThreeSrcCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
1902 case X86::VPMADD52HUQZ128r:
1903 case X86::VPMADD52HUQZ128rk:
1904 case X86::VPMADD52HUQZ128rkz:
1905 case X86::VPMADD52HUQZ256r:
1906 case X86::VPMADD52HUQZ256rk:
1907 case X86::VPMADD52HUQZ256rkz:
1908 case X86::VPMADD52HUQZr:
1909 case X86::VPMADD52HUQZrk:
1910 case X86::VPMADD52HUQZrkz:
1911 case X86::VPMADD52LUQZ128r:
1912 case X86::VPMADD52LUQZ128rk:
1913 case X86::VPMADD52LUQZ128rkz:
1914 case X86::VPMADD52LUQZ256r:
1915 case X86::VPMADD52LUQZ256rk:
1916 case X86::VPMADD52LUQZ256rkz:
1917 case X86::VPMADD52LUQZr:
1918 case X86::VPMADD52LUQZrk:
1919 case X86::VPMADD52LUQZrkz: {
1920 unsigned CommutableOpIdx1 = 2;
1921 unsigned CommutableOpIdx2 = 3;
1922 if (X86II::isKMasked(Desc.TSFlags)) {
1923 // Skip the mask register.
1924 ++CommutableOpIdx1;
1925 ++CommutableOpIdx2;
1926 }
1927 if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
1928 CommutableOpIdx1, CommutableOpIdx2))
1929 return false;
1930 if (!MI.getOperand(SrcOpIdx1).isReg() ||
1931 !MI.getOperand(SrcOpIdx2).isReg())
1932 // No idea.
1933 return false;
1934 return true;
1935 }
1936
1937 default:
1938 const X86InstrFMA3Group *FMA3Group = getFMA3Group(MI.getOpcode(),
1939 MI.getDesc().TSFlags);
1940 if (FMA3Group)
1941 return findThreeSrcCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2,
1942 FMA3Group->isIntrinsic());
1943
1944 // Handled masked instructions since we need to skip over the mask input
1945 // and the preserved input.
1946 if (X86II::isKMasked(Desc.TSFlags)) {
1947 // First assume that the first input is the mask operand and skip past it.
1948 unsigned CommutableOpIdx1 = Desc.getNumDefs() + 1;
1949 unsigned CommutableOpIdx2 = Desc.getNumDefs() + 2;
1950 // Check if the first input is tied. If there isn't one then we only
1951 // need to skip the mask operand which we did above.
1952 if ((MI.getDesc().getOperandConstraint(Desc.getNumDefs(),
1953 MCOI::TIED_TO) != -1)) {
1954 // If this is zero masking instruction with a tied operand, we need to
1955 // move the first index back to the first input since this must
1956 // be a 3 input instruction and we want the first two non-mask inputs.
1957 // Otherwise this is a 2 input instruction with a preserved input and
1958 // mask, so we need to move the indices to skip one more input.
1959 if (X86II::isKMergeMasked(Desc.TSFlags)) {
1960 ++CommutableOpIdx1;
1961 ++CommutableOpIdx2;
1962 } else {
1963 --CommutableOpIdx1;
1964 }
1965 }
1966
1967 if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
1968 CommutableOpIdx1, CommutableOpIdx2))
1969 return false;
1970
1971 if (!MI.getOperand(SrcOpIdx1).isReg() ||
1972 !MI.getOperand(SrcOpIdx2).isReg())
1973 // No idea.
1974 return false;
1975 return true;
1976 }
1977
1978 return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
1979 }
1980 return false;
1981}
1982
1983X86::CondCode X86::getCondFromBranch(const MachineInstr &MI) {
1984 switch (MI.getOpcode()) {
1985 default: return X86::COND_INVALID;
1986 case X86::JCC_1:
1987 return static_cast<X86::CondCode>(
1988 MI.getOperand(MI.getDesc().getNumOperands() - 1).getImm());
1989 }
1990}
1991
1992/// Return condition code of a SETCC opcode.
1993X86::CondCode X86::getCondFromSETCC(const MachineInstr &MI) {
1994 switch (MI.getOpcode()) {
1995 default: return X86::COND_INVALID;
1996 case X86::SETCCr: case X86::SETCCm:
1997 return static_cast<X86::CondCode>(
1998 MI.getOperand(MI.getDesc().getNumOperands() - 1).getImm());
1999 }
2000}
2001
2002/// Return condition code of a CMov opcode.
2003X86::CondCode X86::getCondFromCMov(const MachineInstr &MI) {
2004 switch (MI.getOpcode()) {
2005 default: return X86::COND_INVALID;
2006 case X86::CMOV16rr: case X86::CMOV32rr: case X86::CMOV64rr:
2007 case X86::CMOV16rm: case X86::CMOV32rm: case X86::CMOV64rm:
2008 return static_cast<X86::CondCode>(
2009 MI.getOperand(MI.getDesc().getNumOperands() - 1).getImm());
2010 }
2011}
2012
2013/// Return the inverse of the specified condition,
2014/// e.g. turning COND_E to COND_NE.
2015X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
2016 switch (CC) {
2017 default: llvm_unreachable("Illegal condition code!")::llvm::llvm_unreachable_internal("Illegal condition code!", "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 2017);
2018 case X86::COND_E: return X86::COND_NE;
2019 case X86::COND_NE: return X86::COND_E;
2020 case X86::COND_L: return X86::COND_GE;
2021 case X86::COND_LE: return X86::COND_G;
2022 case X86::COND_G: return X86::COND_LE;
2023 case X86::COND_GE: return X86::COND_L;
2024 case X86::COND_B: return X86::COND_AE;
2025 case X86::COND_BE: return X86::COND_A;
2026 case X86::COND_A: return X86::COND_BE;
2027 case X86::COND_AE: return X86::COND_B;
2028 case X86::COND_S: return X86::COND_NS;
2029 case X86::COND_NS: return X86::COND_S;
2030 case X86::COND_P: return X86::COND_NP;
2031 case X86::COND_NP: return X86::COND_P;
2032 case X86::COND_O: return X86::COND_NO;
2033 case X86::COND_NO: return X86::COND_O;
2034 case X86::COND_NE_OR_P: return X86::COND_E_AND_NP;
2035 case X86::COND_E_AND_NP: return X86::COND_NE_OR_P;
2036 }
2037}
2038
2039/// Assuming the flags are set by MI(a,b), return the condition code if we
2040/// modify the instructions such that flags are set by MI(b,a).
2041static X86::CondCode getSwappedCondition(X86::CondCode CC) {
2042 switch (CC) {
2043 default: return X86::COND_INVALID;
2044 case X86::COND_E: return X86::COND_E;
2045 case X86::COND_NE: return X86::COND_NE;
2046 case X86::COND_L: return X86::COND_G;
2047 case X86::COND_LE: return X86::COND_GE;
2048 case X86::COND_G: return X86::COND_L;
2049 case X86::COND_GE: return X86::COND_LE;
2050 case X86::COND_B: return X86::COND_A;
2051 case X86::COND_BE: return X86::COND_AE;
2052 case X86::COND_A: return X86::COND_B;
2053 case X86::COND_AE: return X86::COND_BE;
2054 }
2055}
2056
2057std::pair<X86::CondCode, bool>
2058X86::getX86ConditionCode(CmpInst::Predicate Predicate) {
2059 X86::CondCode CC = X86::COND_INVALID;
2060 bool NeedSwap = false;
2061 switch (Predicate) {
2062 default: break;
2063 // Floating-point Predicates
2064 case CmpInst::FCMP_UEQ: CC = X86::COND_E; break;
2065 case CmpInst::FCMP_OLT: NeedSwap = true; LLVM_FALLTHROUGH[[clang::fallthrough]];
2066 case CmpInst::FCMP_OGT: CC = X86::COND_A; break;
2067 case CmpInst::FCMP_OLE: NeedSwap = true; LLVM_FALLTHROUGH[[clang::fallthrough]];
2068 case CmpInst::FCMP_OGE: CC = X86::COND_AE; break;
2069 case CmpInst::FCMP_UGT: NeedSwap = true; LLVM_FALLTHROUGH[[clang::fallthrough]];
2070 case CmpInst::FCMP_ULT: CC = X86::COND_B; break;
2071 case CmpInst::FCMP_UGE: NeedSwap = true; LLVM_FALLTHROUGH[[clang::fallthrough]];
2072 case CmpInst::FCMP_ULE: CC = X86::COND_BE; break;
2073 case CmpInst::FCMP_ONE: CC = X86::COND_NE; break;
2074 case CmpInst::FCMP_UNO: CC = X86::COND_P; break;
2075 case CmpInst::FCMP_ORD: CC = X86::COND_NP; break;
2076 case CmpInst::FCMP_OEQ: LLVM_FALLTHROUGH[[clang::fallthrough]];
2077 case CmpInst::FCMP_UNE: CC = X86::COND_INVALID; break;
2078
2079 // Integer Predicates
2080 case CmpInst::ICMP_EQ: CC = X86::COND_E; break;
2081 case CmpInst::ICMP_NE: CC = X86::COND_NE; break;
2082 case CmpInst::ICMP_UGT: CC = X86::COND_A; break;
2083 case CmpInst::ICMP_UGE: CC = X86::COND_AE; break;
2084 case CmpInst::ICMP_ULT: CC = X86::COND_B; break;
2085 case CmpInst::ICMP_ULE: CC = X86::COND_BE; break;
2086 case CmpInst::ICMP_SGT: CC = X86::COND_G; break;
2087 case CmpInst::ICMP_SGE: CC = X86::COND_GE; break;
2088 case CmpInst::ICMP_SLT: CC = X86::COND_L; break;
2089 case CmpInst::ICMP_SLE: CC = X86::COND_LE; break;
2090 }
2091
2092 return std::make_pair(CC, NeedSwap);
2093}
2094
2095/// Return a setcc opcode based on whether it has memory operand.
2096unsigned X86::getSETOpc(bool HasMemoryOperand) {
2097 return HasMemoryOperand ? X86::SETCCr : X86::SETCCm;
2098}
2099
2100/// Return a cmov opcode for the given register size in bytes, and operand type.
2101unsigned X86::getCMovOpcode(unsigned RegBytes, bool HasMemoryOperand) {
2102 switch(RegBytes) {
2103 default: llvm_unreachable("Illegal register size!")::llvm::llvm_unreachable_internal("Illegal register size!", "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 2103);
2104 case 2: return HasMemoryOperand ? X86::CMOV16rm : X86::CMOV16rr;
2105 case 4: return HasMemoryOperand ? X86::CMOV32rm : X86::CMOV32rr;
2106 case 8: return HasMemoryOperand ? X86::CMOV32rm : X86::CMOV64rr;
2107 }
2108}
2109
2110/// Get the VPCMP immediate for the given condition.
2111unsigned X86::getVPCMPImmForCond(ISD::CondCode CC) {
2112 switch (CC) {
2113 default: llvm_unreachable("Unexpected SETCC condition")::llvm::llvm_unreachable_internal("Unexpected SETCC condition"
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 2113);
2114 case ISD::SETNE: return 4;
2115 case ISD::SETEQ: return 0;
2116 case ISD::SETULT:
2117 case ISD::SETLT: return 1;
2118 case ISD::SETUGT:
2119 case ISD::SETGT: return 6;
2120 case ISD::SETUGE:
2121 case ISD::SETGE: return 5;
2122 case ISD::SETULE:
2123 case ISD::SETLE: return 2;
2124 }
2125}
2126
2127/// Get the VPCMP immediate if the opcodes are swapped.
2128unsigned X86::getSwappedVPCMPImm(unsigned Imm) {
2129 switch (Imm) {
2130 default: llvm_unreachable("Unreachable!")::llvm::llvm_unreachable_internal("Unreachable!", "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 2130);
2131 case 0x01: Imm = 0x06; break; // LT -> NLE
2132 case 0x02: Imm = 0x05; break; // LE -> NLT
2133 case 0x05: Imm = 0x02; break; // NLT -> LE
2134 case 0x06: Imm = 0x01; break; // NLE -> LT
2135 case 0x00: // EQ
2136 case 0x03: // FALSE
2137 case 0x04: // NE
2138 case 0x07: // TRUE
2139 break;
2140 }
2141
2142 return Imm;
2143}
2144
2145/// Get the VPCOM immediate if the opcodes are swapped.
2146unsigned X86::getSwappedVPCOMImm(unsigned Imm) {
2147 switch (Imm) {
2148 default: llvm_unreachable("Unreachable!")::llvm::llvm_unreachable_internal("Unreachable!", "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 2148);
2149 case 0x00: Imm = 0x02; break; // LT -> GT
2150 case 0x01: Imm = 0x03; break; // LE -> GE
2151 case 0x02: Imm = 0x00; break; // GT -> LT
2152 case 0x03: Imm = 0x01; break; // GE -> LE
2153 case 0x04: // EQ
2154 case 0x05: // NE
2155 case 0x06: // FALSE
2156 case 0x07: // TRUE
2157 break;
2158 }
2159
2160 return Imm;
2161}
2162
2163bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr &MI) const {
2164 if (!MI.isTerminator()) return false;
2165
2166 // Conditional branch is a special case.
2167 if (MI.isBranch() && !MI.isBarrier())
2168 return true;
2169 if (!MI.isPredicable())
2170 return true;
2171 return !isPredicated(MI);
2172}
2173
2174bool X86InstrInfo::isUnconditionalTailCall(const MachineInstr &MI) const {
2175 switch (MI.getOpcode()) {
2176 case X86::TCRETURNdi:
2177 case X86::TCRETURNri:
2178 case X86::TCRETURNmi:
2179 case X86::TCRETURNdi64:
2180 case X86::TCRETURNri64:
2181 case X86::TCRETURNmi64:
2182 return true;
2183 default:
2184 return false;
2185 }
2186}
2187
2188bool X86InstrInfo::canMakeTailCallConditional(
2189 SmallVectorImpl<MachineOperand> &BranchCond,
2190 const MachineInstr &TailCall) const {
2191 if (TailCall.getOpcode() != X86::TCRETURNdi &&
2192 TailCall.getOpcode() != X86::TCRETURNdi64) {
2193 // Only direct calls can be done with a conditional branch.
2194 return false;
2195 }
2196
2197 const MachineFunction *MF = TailCall.getParent()->getParent();
2198 if (Subtarget.isTargetWin64() && MF->hasWinCFI()) {
2199 // Conditional tail calls confuse the Win64 unwinder.
2200 return false;
2201 }
2202
2203 assert(BranchCond.size() == 1)((BranchCond.size() == 1) ? static_cast<void> (0) : __assert_fail
("BranchCond.size() == 1", "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 2203, __PRETTY_FUNCTION__));
2204 if (BranchCond[0].getImm() > X86::LAST_VALID_COND) {
2205 // Can't make a conditional tail call with this condition.
2206 return false;
2207 }
2208
2209 const X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
2210 if (X86FI->getTCReturnAddrDelta() != 0 ||
2211 TailCall.getOperand(1).getImm() != 0) {
2212 // A conditional tail call cannot do any stack adjustment.
2213 return false;
2214 }
2215
2216 return true;
2217}
2218
2219void X86InstrInfo::replaceBranchWithTailCall(
2220 MachineBasicBlock &MBB, SmallVectorImpl<MachineOperand> &BranchCond,
2221 const MachineInstr &TailCall) const {
2222 assert(canMakeTailCallConditional(BranchCond, TailCall))((canMakeTailCallConditional(BranchCond, TailCall)) ? static_cast
<void> (0) : __assert_fail ("canMakeTailCallConditional(BranchCond, TailCall)"
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 2222, __PRETTY_FUNCTION__));
2223
2224 MachineBasicBlock::iterator I = MBB.end();
2225 while (I != MBB.begin()) {
2226 --I;
2227 if (I->isDebugInstr())
2228 continue;
2229 if (!I->isBranch())
2230 assert(0 && "Can't find the branch to replace!")((0 && "Can't find the branch to replace!") ? static_cast
<void> (0) : __assert_fail ("0 && \"Can't find the branch to replace!\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 2230, __PRETTY_FUNCTION__));
2231
2232 X86::CondCode CC = X86::getCondFromBranch(*I);
2233 assert(BranchCond.size() == 1)((BranchCond.size() == 1) ? static_cast<void> (0) : __assert_fail
("BranchCond.size() == 1", "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 2233, __PRETTY_FUNCTION__));
2234 if (CC != BranchCond[0].getImm())
2235 continue;
2236
2237 break;
2238 }
2239
2240 unsigned Opc = TailCall.getOpcode() == X86::TCRETURNdi ? X86::TCRETURNdicc
2241 : X86::TCRETURNdi64cc;
2242
2243 auto MIB = BuildMI(MBB, I, MBB.findDebugLoc(I), get(Opc));
2244 MIB->addOperand(TailCall.getOperand(0)); // Destination.
2245 MIB.addImm(0); // Stack offset (not used).
2246 MIB->addOperand(BranchCond[0]); // Condition.
2247 MIB.copyImplicitOps(TailCall); // Regmask and (imp-used) parameters.
2248
2249 // Add implicit uses and defs of all live regs potentially clobbered by the
2250 // call. This way they still appear live across the call.
2251 LivePhysRegs LiveRegs(getRegisterInfo());
2252 LiveRegs.addLiveOuts(MBB);
2253 SmallVector<std::pair<MCPhysReg, const MachineOperand *>, 8> Clobbers;
2254 LiveRegs.stepForward(*MIB, Clobbers);
2255 for (const auto &C : Clobbers) {
2256 MIB.addReg(C.first, RegState::Implicit);
2257 MIB.addReg(C.first, RegState::Implicit | RegState::Define);
2258 }
2259
2260 I->eraseFromParent();
2261}
2262
2263// Given a MBB and its TBB, find the FBB which was a fallthrough MBB (it may
2264// not be a fallthrough MBB now due to layout changes). Return nullptr if the
2265// fallthrough MBB cannot be identified.
2266static MachineBasicBlock *getFallThroughMBB(MachineBasicBlock *MBB,
2267 MachineBasicBlock *TBB) {
2268 // Look for non-EHPad successors other than TBB. If we find exactly one, it
2269 // is the fallthrough MBB. If we find zero, then TBB is both the target MBB
2270 // and fallthrough MBB. If we find more than one, we cannot identify the
2271 // fallthrough MBB and should return nullptr.
2272 MachineBasicBlock *FallthroughBB = nullptr;
2273 for (auto SI = MBB->succ_begin(), SE = MBB->succ_end(); SI != SE; ++SI) {
2274 if ((*SI)->isEHPad() || (*SI == TBB && FallthroughBB))
2275 continue;
2276 // Return a nullptr if we found more than one fallthrough successor.
2277 if (FallthroughBB && FallthroughBB != TBB)
2278 return nullptr;
2279 FallthroughBB = *SI;
2280 }
2281 return FallthroughBB;
2282}
2283
2284bool X86InstrInfo::AnalyzeBranchImpl(
2285 MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
2286 SmallVectorImpl<MachineOperand> &Cond,
2287 SmallVectorImpl<MachineInstr *> &CondBranches, bool AllowModify) const {
2288
2289 // Start from the bottom of the block and work up, examining the
2290 // terminator instructions.
2291 MachineBasicBlock::iterator I = MBB.end();
2292 MachineBasicBlock::iterator UnCondBrIter = MBB.end();
2293 while (I != MBB.begin()) {
2294 --I;
2295 if (I->isDebugInstr())
2296 continue;
2297
2298 // Working from the bottom, when we see a non-terminator instruction, we're
2299 // done.
2300 if (!isUnpredicatedTerminator(*I))
2301 break;
2302
2303 // A terminator that isn't a branch can't easily be handled by this
2304 // analysis.
2305 if (!I->isBranch())
2306 return true;
2307
2308 // Handle unconditional branches.
2309 if (I->getOpcode() == X86::JMP_1) {
2310 UnCondBrIter = I;
2311
2312 if (!AllowModify) {
2313 TBB = I->getOperand(0).getMBB();
2314 continue;
2315 }
2316
2317 // If the block has any instructions after a JMP, delete them.
2318 while (std::next(I) != MBB.end())
2319 std::next(I)->eraseFromParent();
2320
2321 Cond.clear();
2322 FBB = nullptr;
2323
2324 // Delete the JMP if it's equivalent to a fall-through.
2325 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
2326 TBB = nullptr;
2327 I->eraseFromParent();
2328 I = MBB.end();
2329 UnCondBrIter = MBB.end();
2330 continue;
2331 }
2332
2333 // TBB is used to indicate the unconditional destination.
2334 TBB = I->getOperand(0).getMBB();
2335 continue;
2336 }
2337
2338 // Handle conditional branches.
2339 X86::CondCode BranchCode = X86::getCondFromBranch(*I);
2340 if (BranchCode == X86::COND_INVALID)
2341 return true; // Can't handle indirect branch.
2342
2343 // In practice we should never have an undef eflags operand, if we do
2344 // abort here as we are not prepared to preserve the flag.
2345 if (I->findRegisterUseOperand(X86::EFLAGS)->isUndef())
2346 return true;
2347
2348 // Working from the bottom, handle the first conditional branch.
2349 if (Cond.empty()) {
2350 MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
2351 if (AllowModify && UnCondBrIter != MBB.end() &&
2352 MBB.isLayoutSuccessor(TargetBB)) {
2353 // If we can modify the code and it ends in something like:
2354 //
2355 // jCC L1
2356 // jmp L2
2357 // L1:
2358 // ...
2359 // L2:
2360 //
2361 // Then we can change this to:
2362 //
2363 // jnCC L2
2364 // L1:
2365 // ...
2366 // L2:
2367 //
2368 // Which is a bit more efficient.
2369 // We conditionally jump to the fall-through block.
2370 BranchCode = GetOppositeBranchCondition(BranchCode);
2371 MachineBasicBlock::iterator OldInst = I;
2372
2373 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JCC_1))
2374 .addMBB(UnCondBrIter->getOperand(0).getMBB())
2375 .addImm(BranchCode);
2376 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_1))
2377 .addMBB(TargetBB);
2378
2379 OldInst->eraseFromParent();
2380 UnCondBrIter->eraseFromParent();
2381
2382 // Restart the analysis.
2383 UnCondBrIter = MBB.end();
2384 I = MBB.end();
2385 continue;
2386 }
2387
2388 FBB = TBB;
2389 TBB = I->getOperand(0).getMBB();
2390 Cond.push_back(MachineOperand::CreateImm(BranchCode));
2391 CondBranches.push_back(&*I);
2392 continue;
2393 }
2394
2395 // Handle subsequent conditional branches. Only handle the case where all
2396 // conditional branches branch to the same destination and their condition
2397 // opcodes fit one of the special multi-branch idioms.
2398 assert(Cond.size() == 1)((Cond.size() == 1) ? static_cast<void> (0) : __assert_fail
("Cond.size() == 1", "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 2398, __PRETTY_FUNCTION__));
2399 assert(TBB)((TBB) ? static_cast<void> (0) : __assert_fail ("TBB", "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 2399, __PRETTY_FUNCTION__));
2400
2401 // If the conditions are the same, we can leave them alone.
2402 X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
2403 auto NewTBB = I->getOperand(0).getMBB();
2404 if (OldBranchCode == BranchCode && TBB == NewTBB)
2405 continue;
2406
2407 // If they differ, see if they fit one of the known patterns. Theoretically,
2408 // we could handle more patterns here, but we shouldn't expect to see them
2409 // if instruction selection has done a reasonable job.
2410 if (TBB == NewTBB &&
2411 ((OldBranchCode == X86::COND_P && BranchCode == X86::COND_NE) ||
2412 (OldBranchCode == X86::COND_NE && BranchCode == X86::COND_P))) {
2413 BranchCode = X86::COND_NE_OR_P;
2414 } else if ((OldBranchCode == X86::COND_NP && BranchCode == X86::COND_NE) ||
2415 (OldBranchCode == X86::COND_E && BranchCode == X86::COND_P)) {
2416 if (NewTBB != (FBB ? FBB : getFallThroughMBB(&MBB, TBB)))
2417 return true;
2418
2419 // X86::COND_E_AND_NP usually has two different branch destinations.
2420 //
2421 // JP B1
2422 // JE B2
2423 // JMP B1
2424 // B1:
2425 // B2:
2426 //
2427 // Here this condition branches to B2 only if NP && E. It has another
2428 // equivalent form:
2429 //
2430 // JNE B1
2431 // JNP B2
2432 // JMP B1
2433 // B1:
2434 // B2:
2435 //
2436 // Similarly it branches to B2 only if E && NP. That is why this condition
2437 // is named with COND_E_AND_NP.
2438 BranchCode = X86::COND_E_AND_NP;
2439 } else
2440 return true;
2441
2442 // Update the MachineOperand.
2443 Cond[0].setImm(BranchCode);
2444 CondBranches.push_back(&*I);
2445 }
2446
2447 return false;
2448}
2449
2450bool X86InstrInfo::analyzeBranch(MachineBasicBlock &MBB,
2451 MachineBasicBlock *&TBB,
2452 MachineBasicBlock *&FBB,
2453 SmallVectorImpl<MachineOperand> &Cond,
2454 bool AllowModify) const {
2455 SmallVector<MachineInstr *, 4> CondBranches;
2456 return AnalyzeBranchImpl(MBB, TBB, FBB, Cond, CondBranches, AllowModify);
2457}
2458
2459bool X86InstrInfo::analyzeBranchPredicate(MachineBasicBlock &MBB,
2460 MachineBranchPredicate &MBP,
2461 bool AllowModify) const {
2462 using namespace std::placeholders;
2463
2464 SmallVector<MachineOperand, 4> Cond;
2465 SmallVector<MachineInstr *, 4> CondBranches;
2466 if (AnalyzeBranchImpl(MBB, MBP.TrueDest, MBP.FalseDest, Cond, CondBranches,
2467 AllowModify))
2468 return true;
2469
2470 if (Cond.size() != 1)
2471 return true;
2472
2473 assert(MBP.TrueDest && "expected!")((MBP.TrueDest && "expected!") ? static_cast<void>
(0) : __assert_fail ("MBP.TrueDest && \"expected!\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 2473, __PRETTY_FUNCTION__));
2474
2475 if (!MBP.FalseDest)
2476 MBP.FalseDest = MBB.getNextNode();
2477
2478 const TargetRegisterInfo *TRI = &getRegisterInfo();
2479
2480 MachineInstr *ConditionDef = nullptr;
2481 bool SingleUseCondition = true;
2482
2483 for (auto I = std::next(MBB.rbegin()), E = MBB.rend(); I != E; ++I) {
2484 if (I->modifiesRegister(X86::EFLAGS, TRI)) {
2485 ConditionDef = &*I;
2486 break;
2487 }
2488
2489 if (I->readsRegister(X86::EFLAGS, TRI))
2490 SingleUseCondition = false;
2491 }
2492
2493 if (!ConditionDef)
2494 return true;
2495
2496 if (SingleUseCondition) {
2497 for (auto *Succ : MBB.successors())
2498 if (Succ->isLiveIn(X86::EFLAGS))
2499 SingleUseCondition = false;
2500 }
2501
2502 MBP.ConditionDef = ConditionDef;
2503 MBP.SingleUseCondition = SingleUseCondition;
2504
2505 // Currently we only recognize the simple pattern:
2506 //
2507 // test %reg, %reg
2508 // je %label
2509 //
2510 const unsigned TestOpcode =
2511 Subtarget.is64Bit() ? X86::TEST64rr : X86::TEST32rr;
2512
2513 if (ConditionDef->getOpcode() == TestOpcode &&
2514 ConditionDef->getNumOperands() == 3 &&
2515 ConditionDef->getOperand(0).isIdenticalTo(ConditionDef->getOperand(1)) &&
2516 (Cond[0].getImm() == X86::COND_NE || Cond[0].getImm() == X86::COND_E)) {
2517 MBP.LHS = ConditionDef->getOperand(0);
2518 MBP.RHS = MachineOperand::CreateImm(0);
2519 MBP.Predicate = Cond[0].getImm() == X86::COND_NE
2520 ? MachineBranchPredicate::PRED_NE
2521 : MachineBranchPredicate::PRED_EQ;
2522 return false;
2523 }
2524
2525 return true;
2526}
2527
2528unsigned X86InstrInfo::removeBranch(MachineBasicBlock &MBB,
2529 int *BytesRemoved) const {
2530 assert(!BytesRemoved && "code size not handled")((!BytesRemoved && "code size not handled") ? static_cast
<void> (0) : __assert_fail ("!BytesRemoved && \"code size not handled\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 2530, __PRETTY_FUNCTION__));
2531
2532 MachineBasicBlock::iterator I = MBB.end();
2533 unsigned Count = 0;
2534
2535 while (I != MBB.begin()) {
2536 --I;
2537 if (I->isDebugInstr())
2538 continue;
2539 if (I->getOpcode() != X86::JMP_1 &&
2540 X86::getCondFromBranch(*I) == X86::COND_INVALID)
2541 break;
2542 // Remove the branch.
2543 I->eraseFromParent();
2544 I = MBB.end();
2545 ++Count;
2546 }
2547
2548 return Count;
2549}
2550
2551unsigned X86InstrInfo::insertBranch(MachineBasicBlock &MBB,
2552 MachineBasicBlock *TBB,
2553 MachineBasicBlock *FBB,
2554 ArrayRef<MachineOperand> Cond,
2555 const DebugLoc &DL,
2556 int *BytesAdded) const {
2557 // Shouldn't be a fall through.
2558 assert(TBB && "insertBranch must not be told to insert a fallthrough")((TBB && "insertBranch must not be told to insert a fallthrough"
) ? static_cast<void> (0) : __assert_fail ("TBB && \"insertBranch must not be told to insert a fallthrough\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 2558, __PRETTY_FUNCTION__));
2559 assert((Cond.size() == 1 || Cond.size() == 0) &&(((Cond.size() == 1 || Cond.size() == 0) && "X86 branch conditions have one component!"
) ? static_cast<void> (0) : __assert_fail ("(Cond.size() == 1 || Cond.size() == 0) && \"X86 branch conditions have one component!\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 2560, __PRETTY_FUNCTION__))
2560 "X86 branch conditions have one component!")(((Cond.size() == 1 || Cond.size() == 0) && "X86 branch conditions have one component!"
) ? static_cast<void> (0) : __assert_fail ("(Cond.size() == 1 || Cond.size() == 0) && \"X86 branch conditions have one component!\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 2560, __PRETTY_FUNCTION__));
2561 assert(!BytesAdded && "code size not handled")((!BytesAdded && "code size not handled") ? static_cast
<void> (0) : __assert_fail ("!BytesAdded && \"code size not handled\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 2561, __PRETTY_FUNCTION__));
2562
2563 if (Cond.empty()) {
2564 // Unconditional branch?
2565 assert(!FBB && "Unconditional branch with multiple successors!")((!FBB && "Unconditional branch with multiple successors!"
) ? static_cast<void> (0) : __assert_fail ("!FBB && \"Unconditional branch with multiple successors!\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 2565, __PRETTY_FUNCTION__));
2566 BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(TBB);
2567 return 1;
2568 }
2569
2570 // If FBB is null, it is implied to be a fall-through block.
2571 bool FallThru = FBB == nullptr;
2572
2573 // Conditional branch.
2574 unsigned Count = 0;
2575 X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
2576 switch (CC) {
2577 case X86::COND_NE_OR_P:
2578 // Synthesize NE_OR_P with two branches.
2579 BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(X86::COND_NE);
2580 ++Count;
2581 BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(X86::COND_P);
2582 ++Count;
2583 break;
2584 case X86::COND_E_AND_NP:
2585 // Use the next block of MBB as FBB if it is null.
2586 if (FBB == nullptr) {
2587 FBB = getFallThroughMBB(&MBB, TBB);
2588 assert(FBB && "MBB cannot be the last block in function when the false "((FBB && "MBB cannot be the last block in function when the false "
"body is a fall-through.") ? static_cast<void> (0) : __assert_fail
("FBB && \"MBB cannot be the last block in function when the false \" \"body is a fall-through.\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 2589, __PRETTY_FUNCTION__))
2589 "body is a fall-through.")((FBB && "MBB cannot be the last block in function when the false "
"body is a fall-through.") ? static_cast<void> (0) : __assert_fail
("FBB && \"MBB cannot be the last block in function when the false \" \"body is a fall-through.\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 2589, __PRETTY_FUNCTION__));
2590 }
2591 // Synthesize COND_E_AND_NP with two branches.
2592 BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(FBB).addImm(X86::COND_NE);
2593 ++Count;
2594 BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(X86::COND_NP);
2595 ++Count;
2596 break;
2597 default: {
2598 BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(CC);
2599 ++Count;
2600 }
2601 }
2602 if (!FallThru) {
2603 // Two-way Conditional branch. Insert the second branch.
2604 BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(FBB);
2605 ++Count;
2606 }
2607 return Count;
2608}
2609
2610bool X86InstrInfo::
2611canInsertSelect(const MachineBasicBlock &MBB,
2612 ArrayRef<MachineOperand> Cond,
2613 unsigned TrueReg, unsigned FalseReg,
2614 int &CondCycles, int &TrueCycles, int &FalseCycles) const {
2615 // Not all subtargets have cmov instructions.
2616 if (!Subtarget.hasCMov())
2617 return false;
2618 if (Cond.size() != 1)
2619 return false;
2620 // We cannot do the composite conditions, at least not in SSA form.
2621 if ((X86::CondCode)Cond[0].getImm() > X86::LAST_VALID_COND)
2622 return false;
2623
2624 // Check register classes.
2625 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2626 const TargetRegisterClass *RC =
2627 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
2628 if (!RC)
2629 return false;
2630
2631 // We have cmov instructions for 16, 32, and 64 bit general purpose registers.
2632 if (X86::GR16RegClass.hasSubClassEq(RC) ||
2633 X86::GR32RegClass.hasSubClassEq(RC) ||
2634 X86::GR64RegClass.hasSubClassEq(RC)) {
2635 // This latency applies to Pentium M, Merom, Wolfdale, Nehalem, and Sandy
2636 // Bridge. Probably Ivy Bridge as well.
2637 CondCycles = 2;
2638 TrueCycles = 2;
2639 FalseCycles = 2;
2640 return true;
2641 }
2642
2643 // Can't do vectors.
2644 return false;
2645}
2646
2647void X86InstrInfo::insertSelect(MachineBasicBlock &MBB,
2648 MachineBasicBlock::iterator I,
2649 const DebugLoc &DL, unsigned DstReg,
2650 ArrayRef<MachineOperand> Cond, unsigned TrueReg,
2651 unsigned FalseReg) const {
2652 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2653 const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
2654 const TargetRegisterClass &RC = *MRI.getRegClass(DstReg);
2655 assert(Cond.size() == 1 && "Invalid Cond array")((Cond.size() == 1 && "Invalid Cond array") ? static_cast
<void> (0) : __assert_fail ("Cond.size() == 1 && \"Invalid Cond array\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 2655, __PRETTY_FUNCTION__));
2656 unsigned Opc = X86::getCMovOpcode(TRI.getRegSizeInBits(RC) / 8,
2657 false /*HasMemoryOperand*/);
2658 BuildMI(MBB, I, DL, get(Opc), DstReg)
2659 .addReg(FalseReg)
2660 .addReg(TrueReg)
2661 .addImm(Cond[0].getImm());
2662}
2663
2664/// Test if the given register is a physical h register.
2665static bool isHReg(unsigned Reg) {
2666 return X86::GR8_ABCD_HRegClass.contains(Reg);
2667}
2668
2669// Try and copy between VR128/VR64 and GR64 registers.
2670static unsigned CopyToFromAsymmetricReg(unsigned DestReg, unsigned SrcReg,
2671 const X86Subtarget &Subtarget) {
2672 bool HasAVX = Subtarget.hasAVX();
2673 bool HasAVX512 = Subtarget.hasAVX512();
2674
2675 // SrcReg(MaskReg) -> DestReg(GR64)
2676 // SrcReg(MaskReg) -> DestReg(GR32)
2677
2678 // All KMASK RegClasses hold the same k registers, can be tested against anyone.
2679 if (X86::VK16RegClass.contains(SrcReg)) {
2680 if (X86::GR64RegClass.contains(DestReg)) {
2681 assert(Subtarget.hasBWI())((Subtarget.hasBWI()) ? static_cast<void> (0) : __assert_fail
("Subtarget.hasBWI()", "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 2681, __PRETTY_FUNCTION__));
2682 return X86::KMOVQrk;
2683 }
2684 if (X86::GR32RegClass.contains(DestReg))
2685 return Subtarget.hasBWI() ? X86::KMOVDrk : X86::KMOVWrk;
2686 }
2687
2688 // SrcReg(GR64) -> DestReg(MaskReg)
2689 // SrcReg(GR32) -> DestReg(MaskReg)
2690
2691 // All KMASK RegClasses hold the same k registers, can be tested against anyone.
2692 if (X86::VK16RegClass.contains(DestReg)) {
2693 if (X86::GR64RegClass.contains(SrcReg)) {
2694 assert(Subtarget.hasBWI())((Subtarget.hasBWI()) ? static_cast<void> (0) : __assert_fail
("Subtarget.hasBWI()", "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 2694, __PRETTY_FUNCTION__));
2695 return X86::KMOVQkr;
2696 }
2697 if (X86::GR32RegClass.contains(SrcReg))
2698 return Subtarget.hasBWI() ? X86::KMOVDkr : X86::KMOVWkr;
2699 }
2700
2701
2702 // SrcReg(VR128) -> DestReg(GR64)
2703 // SrcReg(VR64) -> DestReg(GR64)
2704 // SrcReg(GR64) -> DestReg(VR128)
2705 // SrcReg(GR64) -> DestReg(VR64)
2706
2707 if (X86::GR64RegClass.contains(DestReg)) {
2708 if (X86::VR128XRegClass.contains(SrcReg))
2709 // Copy from a VR128 register to a GR64 register.
2710 return HasAVX512 ? X86::VMOVPQIto64Zrr :
2711 HasAVX ? X86::VMOVPQIto64rr :
2712 X86::MOVPQIto64rr;
2713 if (X86::VR64RegClass.contains(SrcReg))
2714 // Copy from a VR64 register to a GR64 register.
2715 return X86::MMX_MOVD64from64rr;
2716 } else if (X86::GR64RegClass.contains(SrcReg)) {
2717 // Copy from a GR64 register to a VR128 register.
2718 if (X86::VR128XRegClass.contains(DestReg))
2719 return HasAVX512 ? X86::VMOV64toPQIZrr :
2720 HasAVX ? X86::VMOV64toPQIrr :
2721 X86::MOV64toPQIrr;
2722 // Copy from a GR64 register to a VR64 register.
2723 if (X86::VR64RegClass.contains(DestReg))
2724 return X86::MMX_MOVD64to64rr;
2725 }
2726
2727 // SrcReg(VR128) -> DestReg(GR32)
2728 // SrcReg(GR32) -> DestReg(VR128)
2729
2730 if (X86::GR32RegClass.contains(DestReg) &&
2731 X86::VR128XRegClass.contains(SrcReg))
2732 // Copy from a VR128 register to a GR32 register.
2733 return HasAVX512 ? X86::VMOVPDI2DIZrr :
2734 HasAVX ? X86::VMOVPDI2DIrr :
2735 X86::MOVPDI2DIrr;
2736
2737 if (X86::VR128XRegClass.contains(DestReg) &&
2738 X86::GR32RegClass.contains(SrcReg))
2739 // Copy from a VR128 register to a VR128 register.
2740 return HasAVX512 ? X86::VMOVDI2PDIZrr :
2741 HasAVX ? X86::VMOVDI2PDIrr :
2742 X86::MOVDI2PDIrr;
2743 return 0;
2744}
2745
2746void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
2747 MachineBasicBlock::iterator MI,
2748 const DebugLoc &DL, unsigned DestReg,
2749 unsigned SrcReg, bool KillSrc) const {
2750 // First deal with the normal symmetric copies.
2751 bool HasAVX = Subtarget.hasAVX();
2752 bool HasVLX = Subtarget.hasVLX();
2753 unsigned Opc = 0;
2754 if (X86::GR64RegClass.contains(DestReg, SrcReg))
2755 Opc = X86::MOV64rr;
2756 else if (X86::GR32RegClass.contains(DestReg, SrcReg))
2757 Opc = X86::MOV32rr;
2758 else if (X86::GR16RegClass.contains(DestReg, SrcReg))
2759 Opc = X86::MOV16rr;
2760 else if (X86::GR8RegClass.contains(DestReg, SrcReg)) {
2761 // Copying to or from a physical H register on x86-64 requires a NOREX
2762 // move. Otherwise use a normal move.
2763 if ((isHReg(DestReg) || isHReg(SrcReg)) &&
2764 Subtarget.is64Bit()) {
2765 Opc = X86::MOV8rr_NOREX;
2766 // Both operands must be encodable without an REX prefix.
2767 assert(X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) &&((X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) &&
"8-bit H register can not be copied outside GR8_NOREX") ? static_cast
<void> (0) : __assert_fail ("X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) && \"8-bit H register can not be copied outside GR8_NOREX\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 2768, __PRETTY_FUNCTION__))
2768 "8-bit H register can not be copied outside GR8_NOREX")((X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) &&
"8-bit H register can not be copied outside GR8_NOREX") ? static_cast
<void> (0) : __assert_fail ("X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) && \"8-bit H register can not be copied outside GR8_NOREX\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 2768, __PRETTY_FUNCTION__));
2769 } else
2770 Opc = X86::MOV8rr;
2771 }
2772 else if (X86::VR64RegClass.contains(DestReg, SrcReg))
2773 Opc = X86::MMX_MOVQ64rr;
2774 else if (X86::VR128XRegClass.contains(DestReg, SrcReg)) {
2775 if (HasVLX)
2776 Opc = X86::VMOVAPSZ128rr;
2777 else if (X86::VR128RegClass.contains(DestReg, SrcReg))
2778 Opc = HasAVX ? X86::VMOVAPSrr : X86::MOVAPSrr;
2779 else {
2780 // If this an extended register and we don't have VLX we need to use a
2781 // 512-bit move.
2782 Opc = X86::VMOVAPSZrr;
2783 const TargetRegisterInfo *TRI = &getRegisterInfo();
2784 DestReg = TRI->getMatchingSuperReg(DestReg, X86::sub_xmm,
2785 &X86::VR512RegClass);
2786 SrcReg = TRI->getMatchingSuperReg(SrcReg, X86::sub_xmm,
2787 &X86::VR512RegClass);
2788 }
2789 } else if (X86::VR256XRegClass.contains(DestReg, SrcReg)) {
2790 if (HasVLX)
2791 Opc = X86::VMOVAPSZ256rr;
2792 else if (X86::VR256RegClass.contains(DestReg, SrcReg))
2793 Opc = X86::VMOVAPSYrr;
2794 else {
2795 // If this an extended register and we don't have VLX we need to use a
2796 // 512-bit move.
2797 Opc = X86::VMOVAPSZrr;
2798 const TargetRegisterInfo *TRI = &getRegisterInfo();
2799 DestReg = TRI->getMatchingSuperReg(DestReg, X86::sub_ymm,
2800 &X86::VR512RegClass);
2801 SrcReg = TRI->getMatchingSuperReg(SrcReg, X86::sub_ymm,
2802 &X86::VR512RegClass);
2803 }
2804 } else if (X86::VR512RegClass.contains(DestReg, SrcReg))
2805 Opc = X86::VMOVAPSZrr;
2806 // All KMASK RegClasses hold the same k registers, can be tested against anyone.
2807 else if (X86::VK16RegClass.contains(DestReg, SrcReg))
2808 Opc = Subtarget.hasBWI() ? X86::KMOVQkk : X86::KMOVWkk;
2809 if (!Opc)
2810 Opc = CopyToFromAsymmetricReg(DestReg, SrcReg, Subtarget);
2811
2812 if (Opc) {
2813 BuildMI(MBB, MI, DL, get(Opc), DestReg)
2814 .addReg(SrcReg, getKillRegState(KillSrc));
2815 return;
2816 }
2817
2818 if (SrcReg == X86::EFLAGS || DestReg == X86::EFLAGS) {
2819 // FIXME: We use a fatal error here because historically LLVM has tried
2820 // lower some of these physreg copies and we want to ensure we get
2821 // reasonable bug reports if someone encounters a case no other testing
2822 // found. This path should be removed after the LLVM 7 release.
2823 report_fatal_error("Unable to copy EFLAGS physical register!");
2824 }
2825
2826 LLVM_DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg) << " to "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("x86-instr-info")) { dbgs() << "Cannot copy " <<
RI.getName(SrcReg) << " to " << RI.getName(DestReg
) << '\n'; } } while (false)
2827 << RI.getName(DestReg) << '\n')do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("x86-instr-info")) { dbgs() << "Cannot copy " <<
RI.getName(SrcReg) << " to " << RI.getName(DestReg
) << '\n'; } } while (false);
2828 report_fatal_error("Cannot emit physreg copy instruction");
2829}
2830
2831bool X86InstrInfo::isCopyInstrImpl(const MachineInstr &MI,
2832 const MachineOperand *&Src,
2833 const MachineOperand *&Dest) const {
2834 if (MI.isMoveReg()) {
2835 Dest = &MI.getOperand(0);
2836 Src = &MI.getOperand(1);
2837 return true;
2838 }
2839 return false;
2840}
2841
2842static unsigned getLoadStoreRegOpcode(unsigned Reg,
2843 const TargetRegisterClass *RC,
2844 bool isStackAligned,
2845 const X86Subtarget &STI,
2846 bool load) {
2847 bool HasAVX = STI.hasAVX();
2848 bool HasAVX512 = STI.hasAVX512();
2849 bool HasVLX = STI.hasVLX();
2850
2851 switch (STI.getRegisterInfo()->getSpillSize(*RC)) {
2852 default:
2853 llvm_unreachable("Unknown spill size")::llvm::llvm_unreachable_internal("Unknown spill size", "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 2853);
2854 case 1:
2855 assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass")((X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass"
) ? static_cast<void> (0) : __assert_fail ("X86::GR8RegClass.hasSubClassEq(RC) && \"Unknown 1-byte regclass\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 2855, __PRETTY_FUNCTION__));
2856 if (STI.is64Bit())
2857 // Copying to or from a physical H register on x86-64 requires a NOREX
2858 // move. Otherwise use a normal move.
2859 if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC))
2860 return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
2861 return load ? X86::MOV8rm : X86::MOV8mr;
2862 case 2:
2863 if (X86::VK16RegClass.hasSubClassEq(RC))
2864 return load ? X86::KMOVWkm : X86::KMOVWmk;
2865 assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass")((X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass"
) ? static_cast<void> (0) : __assert_fail ("X86::GR16RegClass.hasSubClassEq(RC) && \"Unknown 2-byte regclass\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 2865, __PRETTY_FUNCTION__));
2866 return load ? X86::MOV16rm : X86::MOV16mr;
2867 case 4:
2868 if (X86::GR32RegClass.hasSubClassEq(RC))
2869 return load ? X86::MOV32rm : X86::MOV32mr;
2870 if (X86::FR32XRegClass.hasSubClassEq(RC))
2871 return load ?
2872 (HasAVX512 ? X86::VMOVSSZrm : HasAVX ? X86::VMOVSSrm : X86::MOVSSrm) :
2873 (HasAVX512 ? X86::VMOVSSZmr : HasAVX ? X86::VMOVSSmr : X86::MOVSSmr);
2874 if (X86::RFP32RegClass.hasSubClassEq(RC))
2875 return load ? X86::LD_Fp32m : X86::ST_Fp32m;
2876 if (X86::VK32RegClass.hasSubClassEq(RC)) {
2877 assert(STI.hasBWI() && "KMOVD requires BWI")((STI.hasBWI() && "KMOVD requires BWI") ? static_cast
<void> (0) : __assert_fail ("STI.hasBWI() && \"KMOVD requires BWI\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 2877, __PRETTY_FUNCTION__));
2878 return load ? X86::KMOVDkm : X86::KMOVDmk;
2879 }
2880 // All of these mask pair classes have the same spill size, the same kind
2881 // of kmov instructions can be used with all of them.
2882 if (X86::VK1PAIRRegClass.hasSubClassEq(RC) ||
2883 X86::VK2PAIRRegClass.hasSubClassEq(RC) ||
2884 X86::VK4PAIRRegClass.hasSubClassEq(RC) ||
2885 X86::VK8PAIRRegClass.hasSubClassEq(RC) ||
2886 X86::VK16PAIRRegClass.hasSubClassEq(RC))
2887 return load ? X86::MASKPAIR16LOAD : X86::MASKPAIR16STORE;
2888 llvm_unreachable("Unknown 4-byte regclass")::llvm::llvm_unreachable_internal("Unknown 4-byte regclass", "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 2888);
2889 case 8:
2890 if (X86::GR64RegClass.hasSubClassEq(RC))
2891 return load ? X86::MOV64rm : X86::MOV64mr;
2892 if (X86::FR64XRegClass.hasSubClassEq(RC))
2893 return load ?
2894 (HasAVX512 ? X86::VMOVSDZrm : HasAVX ? X86::VMOVSDrm : X86::MOVSDrm) :
2895 (HasAVX512 ? X86::VMOVSDZmr : HasAVX ? X86::VMOVSDmr : X86::MOVSDmr);
2896 if (X86::VR64RegClass.hasSubClassEq(RC))
2897 return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr;
2898 if (X86::RFP64RegClass.hasSubClassEq(RC))
2899 return load ? X86::LD_Fp64m : X86::ST_Fp64m;
2900 if (X86::VK64RegClass.hasSubClassEq(RC)) {
2901 assert(STI.hasBWI() && "KMOVQ requires BWI")((STI.hasBWI() && "KMOVQ requires BWI") ? static_cast
<void> (0) : __assert_fail ("STI.hasBWI() && \"KMOVQ requires BWI\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 2901, __PRETTY_FUNCTION__));
2902 return load ? X86::KMOVQkm : X86::KMOVQmk;
2903 }
2904 llvm_unreachable("Unknown 8-byte regclass")::llvm::llvm_unreachable_internal("Unknown 8-byte regclass", "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 2904);
2905 case 10:
2906 assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass")((X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass"
) ? static_cast<void> (0) : __assert_fail ("X86::RFP80RegClass.hasSubClassEq(RC) && \"Unknown 10-byte regclass\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 2906, __PRETTY_FUNCTION__));
2907 return load ? X86::LD_Fp80m : X86::ST_FpP80m;
2908 case 16: {
2909 if (X86::VR128XRegClass.hasSubClassEq(RC)) {
2910 // If stack is realigned we can use aligned stores.
2911 if (isStackAligned)
2912 return load ?
2913 (HasVLX ? X86::VMOVAPSZ128rm :
2914 HasAVX512 ? X86::VMOVAPSZ128rm_NOVLX :
2915 HasAVX ? X86::VMOVAPSrm :
2916 X86::MOVAPSrm):
2917 (HasVLX ? X86::VMOVAPSZ128mr :
2918 HasAVX512 ? X86::VMOVAPSZ128mr_NOVLX :
2919 HasAVX ? X86::VMOVAPSmr :
2920 X86::MOVAPSmr);
2921 else
2922 return load ?
2923 (HasVLX ? X86::VMOVUPSZ128rm :
2924 HasAVX512 ? X86::VMOVUPSZ128rm_NOVLX :
2925 HasAVX ? X86::VMOVUPSrm :
2926 X86::MOVUPSrm):
2927 (HasVLX ? X86::VMOVUPSZ128mr :
2928 HasAVX512 ? X86::VMOVUPSZ128mr_NOVLX :
2929 HasAVX ? X86::VMOVUPSmr :
2930 X86::MOVUPSmr);
2931 }
2932 if (X86::BNDRRegClass.hasSubClassEq(RC)) {
2933 if (STI.is64Bit())
2934 return load ? X86::BNDMOV64rm : X86::BNDMOV64mr;
2935 else
2936 return load ? X86::BNDMOV32rm : X86::BNDMOV32mr;
2937 }
2938 llvm_unreachable("Unknown 16-byte regclass")::llvm::llvm_unreachable_internal("Unknown 16-byte regclass",
"/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 2938);
2939 }
2940 case 32:
2941 assert(X86::VR256XRegClass.hasSubClassEq(RC) && "Unknown 32-byte regclass")((X86::VR256XRegClass.hasSubClassEq(RC) && "Unknown 32-byte regclass"
) ? static_cast<void> (0) : __assert_fail ("X86::VR256XRegClass.hasSubClassEq(RC) && \"Unknown 32-byte regclass\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 2941, __PRETTY_FUNCTION__));
2942 // If stack is realigned we can use aligned stores.
2943 if (isStackAligned)
2944 return load ?
2945 (HasVLX ? X86::VMOVAPSZ256rm :
2946 HasAVX512 ? X86::VMOVAPSZ256rm_NOVLX :
2947 X86::VMOVAPSYrm) :
2948 (HasVLX ? X86::VMOVAPSZ256mr :
2949 HasAVX512 ? X86::VMOVAPSZ256mr_NOVLX :
2950 X86::VMOVAPSYmr);
2951 else
2952 return load ?
2953 (HasVLX ? X86::VMOVUPSZ256rm :
2954 HasAVX512 ? X86::VMOVUPSZ256rm_NOVLX :
2955 X86::VMOVUPSYrm) :
2956 (HasVLX ? X86::VMOVUPSZ256mr :
2957 HasAVX512 ? X86::VMOVUPSZ256mr_NOVLX :
2958 X86::VMOVUPSYmr);
2959 case 64:
2960 assert(X86::VR512RegClass.hasSubClassEq(RC) && "Unknown 64-byte regclass")((X86::VR512RegClass.hasSubClassEq(RC) && "Unknown 64-byte regclass"
) ? static_cast<void> (0) : __assert_fail ("X86::VR512RegClass.hasSubClassEq(RC) && \"Unknown 64-byte regclass\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 2960, __PRETTY_FUNCTION__));
2961 assert(STI.hasAVX512() && "Using 512-bit register requires AVX512")((STI.hasAVX512() && "Using 512-bit register requires AVX512"
) ? static_cast<void> (0) : __assert_fail ("STI.hasAVX512() && \"Using 512-bit register requires AVX512\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 2961, __PRETTY_FUNCTION__));
2962 if (isStackAligned)
2963 return load ? X86::VMOVAPSZrm : X86::VMOVAPSZmr;
2964 else
2965 return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
2966 }
2967}
2968
2969bool X86InstrInfo::getMemOperandWithOffset(
2970 const MachineInstr &MemOp, const MachineOperand *&BaseOp, int64_t &Offset,
2971 const TargetRegisterInfo *TRI) const {
2972 const MCInstrDesc &Desc = MemOp.getDesc();
2973 int MemRefBegin = X86II::getMemoryOperandNo(Desc.TSFlags);
2974 if (MemRefBegin < 0)
2975 return false;
2976
2977 MemRefBegin += X86II::getOperandBias(Desc);
2978
2979 BaseOp = &MemOp.getOperand(MemRefBegin + X86::AddrBaseReg);
2980 if (!BaseOp->isReg()) // Can be an MO_FrameIndex
2981 return false;
2982
2983 if (MemOp.getOperand(MemRefBegin + X86::AddrScaleAmt).getImm() != 1)
2984 return false;
2985
2986 if (MemOp.getOperand(MemRefBegin + X86::AddrIndexReg).getReg() !=
2987 X86::NoRegister)
2988 return false;
2989
2990 const MachineOperand &DispMO = MemOp.getOperand(MemRefBegin + X86::AddrDisp);
2991
2992 // Displacement can be symbolic
2993 if (!DispMO.isImm())
2994 return false;
2995
2996 Offset = DispMO.getImm();
2997
2998 assert(BaseOp->isReg() && "getMemOperandWithOffset only supports base "((BaseOp->isReg() && "getMemOperandWithOffset only supports base "
"operands of type register.") ? static_cast<void> (0) :
__assert_fail ("BaseOp->isReg() && \"getMemOperandWithOffset only supports base \" \"operands of type register.\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 2999, __PRETTY_FUNCTION__))
2999 "operands of type register.")((BaseOp->isReg() && "getMemOperandWithOffset only supports base "
"operands of type register.") ? static_cast<void> (0) :
__assert_fail ("BaseOp->isReg() && \"getMemOperandWithOffset only supports base \" \"operands of type register.\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 2999, __PRETTY_FUNCTION__));
3000 return true;
3001}
3002
3003static unsigned getStoreRegOpcode(unsigned SrcReg,
3004 const TargetRegisterClass *RC,
3005 bool isStackAligned,
3006 const X86Subtarget &STI) {
3007 return getLoadStoreRegOpcode(SrcReg, RC, isStackAligned, STI, false);
3008}
3009
3010
3011static unsigned getLoadRegOpcode(unsigned DestReg,
3012 const TargetRegisterClass *RC,
3013 bool isStackAligned,
3014 const X86Subtarget &STI) {
3015 return getLoadStoreRegOpcode(DestReg, RC, isStackAligned, STI, true);
3016}
3017
3018void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
3019 MachineBasicBlock::iterator MI,
3020 unsigned SrcReg, bool isKill, int FrameIdx,
3021 const TargetRegisterClass *RC,
3022 const TargetRegisterInfo *TRI) const {
3023 const MachineFunction &MF = *MBB.getParent();
3024 assert(MF.getFrameInfo().getObjectSize(FrameIdx) >= TRI->getSpillSize(*RC) &&((MF.getFrameInfo().getObjectSize(FrameIdx) >= TRI->getSpillSize
(*RC) && "Stack slot too small for store") ? static_cast
<void> (0) : __assert_fail ("MF.getFrameInfo().getObjectSize(FrameIdx) >= TRI->getSpillSize(*RC) && \"Stack slot too small for store\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 3025, __PRETTY_FUNCTION__))
3025 "Stack slot too small for store")((MF.getFrameInfo().getObjectSize(FrameIdx) >= TRI->getSpillSize
(*RC) && "Stack slot too small for store") ? static_cast
<void> (0) : __assert_fail ("MF.getFrameInfo().getObjectSize(FrameIdx) >= TRI->getSpillSize(*RC) && \"Stack slot too small for store\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 3025, __PRETTY_FUNCTION__));
3026 unsigned Alignment = std::max<uint32_t>(TRI->getSpillSize(*RC), 16);
3027 bool isAligned =
3028 (Subtarget.getFrameLowering()->getStackAlignment() >= Alignment) ||
3029 RI.canRealignStack(MF);
3030 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
3031 addFrameReference(BuildMI(MBB, MI, DebugLoc(), get(Opc)), FrameIdx)
3032 .addReg(SrcReg, getKillRegState(isKill));
3033}
3034
3035void X86InstrInfo::storeRegToAddr(
3036 MachineFunction &MF, unsigned SrcReg, bool isKill,
3037 SmallVectorImpl<MachineOperand> &Addr, const TargetRegisterClass *RC,
3038 ArrayRef<MachineMemOperand *> MMOs,
3039 SmallVectorImpl<MachineInstr *> &NewMIs) const {
3040 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
3041 unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*RC), 16);
3042 bool isAligned = !MMOs.empty() && MMOs.front()->getAlignment() >= Alignment;
3043 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
3044 DebugLoc DL;
3045 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
3046 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
3047 MIB.add(Addr[i]);
3048 MIB.addReg(SrcReg, getKillRegState(isKill));
3049 MIB.setMemRefs(MMOs);
3050 NewMIs.push_back(MIB);
3051}
3052
3053
3054void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
3055 MachineBasicBlock::iterator MI,
3056 unsigned DestReg, int FrameIdx,
3057 const TargetRegisterClass *RC,
3058 const TargetRegisterInfo *TRI) const {
3059 const MachineFunction &MF = *MBB.getParent();
3060 unsigned Alignment = std::max<uint32_t>(TRI->getSpillSize(*RC), 16);
3061 bool isAligned =
3062 (Subtarget.getFrameLowering()->getStackAlignment() >= Alignment) ||
3063 RI.canRealignStack(MF);
3064 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
3065 addFrameReference(BuildMI(MBB, MI, DebugLoc(), get(Opc), DestReg), FrameIdx);
3066}
3067
3068void X86InstrInfo::loadRegFromAddr(
3069 MachineFunction &MF, unsigned DestReg,
3070 SmallVectorImpl<MachineOperand> &Addr, const TargetRegisterClass *RC,
3071 ArrayRef<MachineMemOperand *> MMOs,
3072 SmallVectorImpl<MachineInstr *> &NewMIs) const {
3073 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
3074 unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*RC), 16);
3075 bool isAligned = !MMOs.empty() && MMOs.front()->getAlignment() >= Alignment;
3076 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
3077 DebugLoc DL;
3078 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
3079 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
3080 MIB.add(Addr[i]);
3081 MIB.setMemRefs(MMOs);
3082 NewMIs.push_back(MIB);
3083}
3084
3085bool X86InstrInfo::analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
3086 unsigned &SrcReg2, int &CmpMask,
3087 int &CmpValue) const {
3088 switch (MI.getOpcode()) {
3089 default: break;
3090 case X86::CMP64ri32:
3091 case X86::CMP64ri8:
3092 case X86::CMP32ri:
3093 case X86::CMP32ri8:
3094 case X86::CMP16ri:
3095 case X86::CMP16ri8:
3096 case X86::CMP8ri:
3097 SrcReg = MI.getOperand(0).getReg();
3098 SrcReg2 = 0;
3099 if (MI.getOperand(1).isImm()) {
3100 CmpMask = ~0;
3101 CmpValue = MI.getOperand(1).getImm();
3102 } else {
3103 CmpMask = CmpValue = 0;
3104 }
3105 return true;
3106 // A SUB can be used to perform comparison.
3107 case X86::SUB64rm:
3108 case X86::SUB32rm:
3109 case X86::SUB16rm:
3110 case X86::SUB8rm:
3111 SrcReg = MI.getOperand(1).getReg();
3112 SrcReg2 = 0;
3113 CmpMask = 0;
3114 CmpValue = 0;
3115 return true;
3116 case X86::SUB64rr:
3117 case X86::SUB32rr:
3118 case X86::SUB16rr:
3119 case X86::SUB8rr:
3120 SrcReg = MI.getOperand(1).getReg();
3121 SrcReg2 = MI.getOperand(2).getReg();
3122 CmpMask = 0;
3123 CmpValue = 0;
3124 return true;
3125 case X86::SUB64ri32:
3126 case X86::SUB64ri8:
3127 case X86::SUB32ri:
3128 case X86::SUB32ri8:
3129 case X86::SUB16ri:
3130 case X86::SUB16ri8:
3131 case X86::SUB8ri:
3132 SrcReg = MI.getOperand(1).getReg();
3133 SrcReg2 = 0;
3134 if (MI.getOperand(2).isImm()) {
3135 CmpMask = ~0;
3136 CmpValue = MI.getOperand(2).getImm();
3137 } else {
3138 CmpMask = CmpValue = 0;
3139 }
3140 return true;
3141 case X86::CMP64rr:
3142 case X86::CMP32rr:
3143 case X86::CMP16rr:
3144 case X86::CMP8rr:
3145 SrcReg = MI.getOperand(0).getReg();
3146 SrcReg2 = MI.getOperand(1).getReg();
3147 CmpMask = 0;
3148 CmpValue = 0;
3149 return true;
3150 case X86::TEST8rr:
3151 case X86::TEST16rr:
3152 case X86::TEST32rr:
3153 case X86::TEST64rr:
3154 SrcReg = MI.getOperand(0).getReg();
3155 if (MI.getOperand(1).getReg() != SrcReg)
3156 return false;
3157 // Compare against zero.
3158 SrcReg2 = 0;
3159 CmpMask = ~0;
3160 CmpValue = 0;
3161 return true;
3162 }
3163 return false;
3164}
3165
3166/// Check whether the first instruction, whose only
3167/// purpose is to update flags, can be made redundant.
3168/// CMPrr can be made redundant by SUBrr if the operands are the same.
3169/// This function can be extended later on.
3170/// SrcReg, SrcRegs: register operands for FlagI.
3171/// ImmValue: immediate for FlagI if it takes an immediate.
3172inline static bool isRedundantFlagInstr(const MachineInstr &FlagI,
3173 unsigned SrcReg, unsigned SrcReg2,
3174 int ImmMask, int ImmValue,
3175 const MachineInstr &OI) {
3176 if (((FlagI.getOpcode() == X86::CMP64rr && OI.getOpcode() == X86::SUB64rr) ||
3177 (FlagI.getOpcode() == X86::CMP32rr && OI.getOpcode() == X86::SUB32rr) ||
3178 (FlagI.getOpcode() == X86::CMP16rr && OI.getOpcode() == X86::SUB16rr) ||
3179 (FlagI.getOpcode() == X86::CMP8rr && OI.getOpcode() == X86::SUB8rr)) &&
3180 ((OI.getOperand(1).getReg() == SrcReg &&
3181 OI.getOperand(2).getReg() == SrcReg2) ||
3182 (OI.getOperand(1).getReg() == SrcReg2 &&
3183 OI.getOperand(2).getReg() == SrcReg)))
3184 return true;
3185
3186 if (ImmMask != 0 &&
3187 ((FlagI.getOpcode() == X86::CMP64ri32 &&
3188 OI.getOpcode() == X86::SUB64ri32) ||
3189 (FlagI.getOpcode() == X86::CMP64ri8 &&
3190 OI.getOpcode() == X86::SUB64ri8) ||
3191 (FlagI.getOpcode() == X86::CMP32ri && OI.getOpcode() == X86::SUB32ri) ||
3192 (FlagI.getOpcode() == X86::CMP32ri8 &&
3193 OI.getOpcode() == X86::SUB32ri8) ||
3194 (FlagI.getOpcode() == X86::CMP16ri && OI.getOpcode() == X86::SUB16ri) ||
3195 (FlagI.getOpcode() == X86::CMP16ri8 &&
3196 OI.getOpcode() == X86::SUB16ri8) ||
3197 (FlagI.getOpcode() == X86::CMP8ri && OI.getOpcode() == X86::SUB8ri)) &&
3198 OI.getOperand(1).getReg() == SrcReg &&
3199 OI.getOperand(2).getImm() == ImmValue)
3200 return true;
3201 return false;
3202}
3203
3204/// Check whether the definition can be converted
3205/// to remove a comparison against zero.
3206inline static bool isDefConvertible(const MachineInstr &MI, bool &NoSignFlag) {
3207 NoSignFlag = false;
3208
3209 switch (MI.getOpcode()) {
3210 default: return false;
3211
3212 // The shift instructions only modify ZF if their shift count is non-zero.
3213 // N.B.: The processor truncates the shift count depending on the encoding.
3214 case X86::SAR8ri: case X86::SAR16ri: case X86::SAR32ri:case X86::SAR64ri:
3215 case X86::SHR8ri: case X86::SHR16ri: case X86::SHR32ri:case X86::SHR64ri:
3216 return getTruncatedShiftCount(MI, 2) != 0;
3217
3218 // Some left shift instructions can be turned into LEA instructions but only
3219 // if their flags aren't used. Avoid transforming such instructions.
3220 case X86::SHL8ri: case X86::SHL16ri: case X86::SHL32ri:case X86::SHL64ri:{
3221 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
3222 if (isTruncatedShiftCountForLEA(ShAmt)) return false;
3223 return ShAmt != 0;
3224 }
3225
3226 case X86::SHRD16rri8:case X86::SHRD32rri8:case X86::SHRD64rri8:
3227 case X86::SHLD16rri8:case X86::SHLD32rri8:case X86::SHLD64rri8:
3228 return getTruncatedShiftCount(MI, 3) != 0;
3229
3230 case X86::SUB64ri32: case X86::SUB64ri8: case X86::SUB32ri:
3231 case X86::SUB32ri8: case X86::SUB16ri: case X86::SUB16ri8:
3232 case X86::SUB8ri: case X86::SUB64rr: case X86::SUB32rr:
3233 case X86::SUB16rr: case X86::SUB8rr: case X86::SUB64rm:
3234 case X86::SUB32rm: case X86::SUB16rm: case X86::SUB8rm:
3235 case X86::DEC64r: case X86::DEC32r: case X86::DEC16r: case X86::DEC8r:
3236 case X86::ADD64ri32: case X86::ADD64ri8: case X86::ADD32ri:
3237 case X86::ADD32ri8: case X86::ADD16ri: case X86::ADD16ri8:
3238 case X86::ADD8ri: case X86::ADD64rr: case X86::ADD32rr:
3239 case X86::ADD16rr: case X86::ADD8rr: case X86::ADD64rm:
3240 case X86::ADD32rm: case X86::ADD16rm: case X86::ADD8rm:
3241 case X86::INC64r: case X86::INC32r: case X86::INC16r: case X86::INC8r:
3242 case X86::AND64ri32: case X86::AND64ri8: case X86::AND32ri:
3243 case X86::AND32ri8: case X86::AND16ri: case X86::AND16ri8:
3244 case X86::AND8ri: case X86::AND64rr: case X86::AND32rr:
3245 case X86::AND16rr: case X86::AND8rr: case X86::AND64rm:
3246 case X86::AND32rm: case X86::AND16rm: case X86::AND8rm:
3247 case X86::XOR64ri32: case X86::XOR64ri8: case X86::XOR32ri:
3248 case X86::XOR32ri8: case X86::XOR16ri: case X86::XOR16ri8:
3249 case X86::XOR8ri: case X86::XOR64rr: case X86::XOR32rr:
3250 case X86::XOR16rr: case X86::XOR8rr: case X86::XOR64rm:
3251 case X86::XOR32rm: case X86::XOR16rm: case X86::XOR8rm:
3252 case X86::OR64ri32: case X86::OR64ri8: case X86::OR32ri:
3253 case X86::OR32ri8: case X86::OR16ri: case X86::OR16ri8:
3254 case X86::OR8ri: case X86::OR64rr: case X86::OR32rr:
3255 case X86::OR16rr: case X86::OR8rr: case X86::OR64rm:
3256 case X86::OR32rm: case X86::OR16rm: case X86::OR8rm:
3257 case X86::ADC64ri32: case X86::ADC64ri8: case X86::ADC32ri:
3258 case X86::ADC32ri8: case X86::ADC16ri: case X86::ADC16ri8:
3259 case X86::ADC8ri: case X86::ADC64rr: case X86::ADC32rr:
3260 case X86::ADC16rr: case X86::ADC8rr: case X86::ADC64rm:
3261 case X86::ADC32rm: case X86::ADC16rm: case X86::ADC8rm:
3262 case X86::SBB64ri32: case X86::SBB64ri8: case X86::SBB32ri:
3263 case X86::SBB32ri8: case X86::SBB16ri: case X86::SBB16ri8:
3264 case X86::SBB8ri: case X86::SBB64rr: case X86::SBB32rr:
3265 case X86::SBB16rr: case X86::SBB8rr: case X86::SBB64rm:
3266 case X86::SBB32rm: case X86::SBB16rm: case X86::SBB8rm:
3267 case X86::NEG8r: case X86::NEG16r: case X86::NEG32r: case X86::NEG64r:
3268 case X86::SAR8r1: case X86::SAR16r1: case X86::SAR32r1:case X86::SAR64r1:
3269 case X86::SHR8r1: case X86::SHR16r1: case X86::SHR32r1:case X86::SHR64r1:
3270 case X86::SHL8r1: case X86::SHL16r1: case X86::SHL32r1:case X86::SHL64r1:
3271 case X86::ANDN32rr: case X86::ANDN32rm:
3272 case X86::ANDN64rr: case X86::ANDN64rm:
3273 case X86::BLSI32rr: case X86::BLSI32rm:
3274 case X86::BLSI64rr: case X86::BLSI64rm:
3275 case X86::BLSMSK32rr:case X86::BLSMSK32rm:
3276 case X86::BLSMSK64rr:case X86::BLSMSK64rm:
3277 case X86::BLSR32rr: case X86::BLSR32rm:
3278 case X86::BLSR64rr: case X86::BLSR64rm:
3279 case X86::BZHI32rr: case X86::BZHI32rm:
3280 case X86::BZHI64rr: case X86::BZHI64rm:
3281 case X86::LZCNT16rr: case X86::LZCNT16rm:
3282 case X86::LZCNT32rr: case X86::LZCNT32rm:
3283 case X86::LZCNT64rr: case X86::LZCNT64rm:
3284 case X86::POPCNT16rr:case X86::POPCNT16rm:
3285 case X86::POPCNT32rr:case X86::POPCNT32rm:
3286 case X86::POPCNT64rr:case X86::POPCNT64rm:
3287 case X86::TZCNT16rr: case X86::TZCNT16rm:
3288 case X86::TZCNT32rr: case X86::TZCNT32rm:
3289 case X86::TZCNT64rr: case X86::TZCNT64rm:
3290 case X86::BLCFILL32rr: case X86::BLCFILL32rm:
3291 case X86::BLCFILL64rr: case X86::BLCFILL64rm:
3292 case X86::BLCI32rr: case X86::BLCI32rm:
3293 case X86::BLCI64rr: case X86::BLCI64rm:
3294 case X86::BLCIC32rr: case X86::BLCIC32rm:
3295 case X86::BLCIC64rr: case X86::BLCIC64rm:
3296 case X86::BLCMSK32rr: case X86::BLCMSK32rm:
3297 case X86::BLCMSK64rr: case X86::BLCMSK64rm:
3298 case X86::BLCS32rr: case X86::BLCS32rm:
3299 case X86::BLCS64rr: case X86::BLCS64rm:
3300 case X86::BLSFILL32rr: case X86::BLSFILL32rm:
3301 case X86::BLSFILL64rr: case X86::BLSFILL64rm:
3302 case X86::BLSIC32rr: case X86::BLSIC32rm:
3303 case X86::BLSIC64rr: case X86::BLSIC64rm:
3304 case X86::T1MSKC32rr: case X86::T1MSKC32rm:
3305 case X86::T1MSKC64rr: case X86::T1MSKC64rm:
3306 case X86::TZMSK32rr: case X86::TZMSK32rm:
3307 case X86::TZMSK64rr: case X86::TZMSK64rm:
3308 return true;
3309 case X86::BEXTR32rr: case X86::BEXTR64rr:
3310 case X86::BEXTR32rm: case X86::BEXTR64rm:
3311 case X86::BEXTRI32ri: case X86::BEXTRI32mi:
3312 case X86::BEXTRI64ri: case X86::BEXTRI64mi:
3313 // BEXTR doesn't update the sign flag so we can't use it.
3314 NoSignFlag = true;
3315 return true;
3316 }
3317}
3318
3319/// Check whether the use can be converted to remove a comparison against zero.
3320static X86::CondCode isUseDefConvertible(const MachineInstr &MI) {
3321 switch (MI.getOpcode()) {
3322 default: return X86::COND_INVALID;
3323 case X86::LZCNT16rr: case X86::LZCNT16rm:
3324 case X86::LZCNT32rr: case X86::LZCNT32rm:
3325 case X86::LZCNT64rr: case X86::LZCNT64rm:
3326 return X86::COND_B;
3327 case X86::POPCNT16rr:case X86::POPCNT16rm:
3328 case X86::POPCNT32rr:case X86::POPCNT32rm:
3329 case X86::POPCNT64rr:case X86::POPCNT64rm:
3330 return X86::COND_E;
3331 case X86::TZCNT16rr: case X86::TZCNT16rm:
3332 case X86::TZCNT32rr: case X86::TZCNT32rm:
3333 case X86::TZCNT64rr: case X86::TZCNT64rm:
3334 return X86::COND_B;
3335 case X86::BSF16rr: case X86::BSF16rm:
3336 case X86::BSF32rr: case X86::BSF32rm:
3337 case X86::BSF64rr: case X86::BSF64rm:
3338 case X86::BSR16rr: case X86::BSR16rm:
3339 case X86::BSR32rr: case X86::BSR32rm:
3340 case X86::BSR64rr: case X86::BSR64rm:
3341 return X86::COND_E;
3342 }
3343}
3344
3345/// Check if there exists an earlier instruction that
3346/// operates on the same source operands and sets flags in the same way as
3347/// Compare; remove Compare if possible.
3348bool X86InstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
3349 unsigned SrcReg2, int CmpMask,
3350 int CmpValue,
3351 const MachineRegisterInfo *MRI) const {
3352 // Check whether we can replace SUB with CMP.
3353 switch (CmpInstr.getOpcode()) {
1
Control jumps to the 'default' case at line 3354
→
3354 default: break;
2
←
 Execution continues on line 3402
→
3355 case X86::SUB64ri32:
3356 case X86::SUB64ri8:
3357 case X86::SUB32ri:
3358 case X86::SUB32ri8:
3359 case X86::SUB16ri:
3360 case X86::SUB16ri8:
3361 case X86::SUB8ri:
3362 case X86::SUB64rm:
3363 case X86::SUB32rm:
3364 case X86::SUB16rm:
3365 case X86::SUB8rm:
3366 case X86::SUB64rr:
3367 case X86::SUB32rr:
3368 case X86::SUB16rr:
3369 case X86::SUB8rr: {
3370 if (!MRI->use_nodbg_empty(CmpInstr.getOperand(0).getReg()))
3371 return false;
3372 // There is no use of the destination register, we can replace SUB with CMP.
3373 unsigned NewOpcode = 0;
3374 switch (CmpInstr.getOpcode()) {
3375 default: llvm_unreachable("Unreachable!")::llvm::llvm_unreachable_internal("Unreachable!", "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 3375);
3376 case X86::SUB64rm: NewOpcode = X86::CMP64rm; break;
3377 case X86::SUB32rm: NewOpcode = X86::CMP32rm; break;
3378 case X86::SUB16rm: NewOpcode = X86::CMP16rm; break;
3379 case X86::SUB8rm: NewOpcode = X86::CMP8rm; break;
3380 case X86::SUB64rr: NewOpcode = X86::CMP64rr; break;
3381 case X86::SUB32rr: NewOpcode = X86::CMP32rr; break;
3382 case X86::SUB16rr: NewOpcode = X86::CMP16rr; break;
3383 case X86::SUB8rr: NewOpcode = X86::CMP8rr; break;
3384 case X86::SUB64ri32: NewOpcode = X86::CMP64ri32; break;
3385 case X86::SUB64ri8: NewOpcode = X86::CMP64ri8; break;
3386 case X86::SUB32ri: NewOpcode = X86::CMP32ri; break;
3387 case X86::SUB32ri8: NewOpcode = X86::CMP32ri8; break;
3388 case X86::SUB16ri: NewOpcode = X86::CMP16ri; break;
3389 case X86::SUB16ri8: NewOpcode = X86::CMP16ri8; break;
3390 case X86::SUB8ri: NewOpcode = X86::CMP8ri; break;
3391 }
3392 CmpInstr.setDesc(get(NewOpcode));
3393 CmpInstr.RemoveOperand(0);
3394 // Fall through to optimize Cmp if Cmp is CMPrr or CMPri.
3395 if (NewOpcode == X86::CMP64rm || NewOpcode == X86::CMP32rm ||
3396 NewOpcode == X86::CMP16rm || NewOpcode == X86::CMP8rm)
3397 return false;
3398 }
3399 }
3400
3401 // Get the unique definition of SrcReg.
3402 MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
3403 if (!MI) return false;
3
←
Assuming 'MI' is non-null
→
4
←
Taking false branch
→
3404
3405 // CmpInstr is the first instruction of the BB.
3406 MachineBasicBlock::iterator I = CmpInstr, Def = MI;
3407
3408 // If we are comparing against zero, check whether we can use MI to update
3409 // EFLAGS. If MI is not in the same BB as CmpInstr, do not optimize.
3410 bool IsCmpZero = (CmpMask != 0 && CmpValue == 0);
5
←
Assuming 'CmpMask' is not equal to 0
→
6
←
Assuming 'CmpValue' is equal to 0
→
3411 if (IsCmpZero && MI->getParent() != CmpInstr.getParent())
7
←
Assuming the condition is false
→
8
←
Taking false branch
→
3412 return false;
3413
3414 // If we have a use of the source register between the def and our compare
3415 // instruction we can eliminate the compare iff the use sets EFLAGS in the
3416 // right way.
3417 bool ShouldUpdateCC = false;
3418 bool NoSignFlag = false;
3419 X86::CondCode NewCC = X86::COND_INVALID;
3420 if (IsCmpZero && !isDefConvertible(*MI, NoSignFlag)) {
9
←
Assuming the condition is false
→
10
←
Taking false branch
→
3421 // Scan forward from the use until we hit the use we're looking for or the
3422 // compare instruction.
3423 for (MachineBasicBlock::iterator J = MI;; ++J) {
3424 // Do we have a convertible instruction?
3425 NewCC = isUseDefConvertible(*J);
3426 if (NewCC != X86::COND_INVALID && J->getOperand(1).isReg() &&
3427 J->getOperand(1).getReg() == SrcReg) {
3428 assert(J->definesRegister(X86::EFLAGS) && "Must be an EFLAGS def!")((J->definesRegister(X86::EFLAGS) && "Must be an EFLAGS def!"
) ? static_cast<void> (0) : __assert_fail ("J->definesRegister(X86::EFLAGS) && \"Must be an EFLAGS def!\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 3428, __PRETTY_FUNCTION__));
3429 ShouldUpdateCC = true; // Update CC later on.
3430 // This is not a def of SrcReg, but still a def of EFLAGS. Keep going
3431 // with the new def.
3432 Def = J;
3433 MI = &*Def;
3434 break;
3435 }
3436
3437 if (J == I)
3438 return false;
3439 }
3440 }
3441
3442 // We are searching for an earlier instruction that can make CmpInstr
3443 // redundant and that instruction will be saved in Sub.
3444 MachineInstr *Sub = nullptr;
11
←
'Sub' initialized to a null pointer value
→
3445 const TargetRegisterInfo *TRI = &getRegisterInfo();
3446
3447 // We iterate backward, starting from the instruction before CmpInstr and
3448 // stop when reaching the definition of a source register or done with the BB.
3449 // RI points to the instruction before CmpInstr.
3450 // If the definition is in this basic block, RE points to the definition;
3451 // otherwise, RE is the rend of the basic block.
3452 MachineBasicBlock::reverse_iterator
3453 RI = ++I.getReverse(),
3454 RE = CmpInstr.getParent() == MI->getParent()
12
←
'?' condition is true
→
3455 ? Def.getReverse() /* points to MI */
3456 : CmpInstr.getParent()->rend();
3457 MachineInstr *Movr0Inst = nullptr;
3458 for (; RI != RE; ++RI) {
13
←
Loop condition is false. Execution continues on line 3486
→
3459 MachineInstr &Instr = *RI;
3460 // Check whether CmpInstr can be made redundant by the current instruction.
3461 if (!IsCmpZero && isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpMask,
3462 CmpValue, Instr)) {
3463 Sub = &Instr;
3464 break;
3465 }
3466
3467 if (Instr.modifiesRegister(X86::EFLAGS, TRI) ||
3468 Instr.readsRegister(X86::EFLAGS, TRI)) {
3469 // This instruction modifies or uses EFLAGS.
3470
3471 // MOV32r0 etc. are implemented with xor which clobbers condition code.
3472 // They are safe to move up, if the definition to EFLAGS is dead and
3473 // earlier instructions do not read or write EFLAGS.
3474 if (!Movr0Inst && Instr.getOpcode() == X86::MOV32r0 &&
3475 Instr.registerDefIsDead(X86::EFLAGS, TRI)) {
3476 Movr0Inst = &Instr;
3477 continue;
3478 }
3479
3480 // We can't remove CmpInstr.
3481 return false;
3482 }
3483 }
3484
3485 // Return false if no candidates exist.
3486 if (!IsCmpZero && !Sub)
3487 return false;
3488
3489 bool IsSwapped = (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
14
←
Assuming 'SrcReg2' is not equal to 0
→
15
←
Called C++ object pointer is null
3490 Sub->getOperand(2).getReg() == SrcReg);
3491
3492 // Scan forward from the instruction after CmpInstr for uses of EFLAGS.
3493 // It is safe to remove CmpInstr if EFLAGS is redefined or killed.
3494 // If we are done with the basic block, we need to check whether EFLAGS is
3495 // live-out.
3496 bool IsSafe = false;
3497 SmallVector<std::pair<MachineInstr*, X86::CondCode>, 4> OpsToUpdate;
3498 MachineBasicBlock::iterator E = CmpInstr.getParent()->end();
3499 for (++I; I != E; ++I) {
3500 const MachineInstr &Instr = *I;
3501 bool ModifyEFLAGS = Instr.modifiesRegister(X86::EFLAGS, TRI);
3502 bool UseEFLAGS = Instr.readsRegister(X86::EFLAGS, TRI);
3503 // We should check the usage if this instruction uses and updates EFLAGS.
3504 if (!UseEFLAGS && ModifyEFLAGS) {
3505 // It is safe to remove CmpInstr if EFLAGS is updated again.
3506 IsSafe = true;
3507 break;
3508 }
3509 if (!UseEFLAGS && !ModifyEFLAGS)
3510 continue;
3511
3512 // EFLAGS is used by this instruction.
3513 X86::CondCode OldCC = X86::COND_INVALID;
3514 if (IsCmpZero || IsSwapped) {
3515 // We decode the condition code from opcode.
3516 if (Instr.isBranch())
3517 OldCC = X86::getCondFromBranch(Instr);
3518 else {
3519 OldCC = X86::getCondFromSETCC(Instr);
3520 if (OldCC == X86::COND_INVALID)
3521 OldCC = X86::getCondFromCMov(Instr);
3522 }
3523 if (OldCC == X86::COND_INVALID) return false;
3524 }
3525 X86::CondCode ReplacementCC = X86::COND_INVALID;
3526 if (IsCmpZero) {
3527 switch (OldCC) {
3528 default: break;
3529 case X86::COND_A: case X86::COND_AE:
3530 case X86::COND_B: case X86::COND_BE:
3531 case X86::COND_G: case X86::COND_GE:
3532 case X86::COND_L: case X86::COND_LE:
3533 case X86::COND_O: case X86::COND_NO:
3534 // CF and OF are used, we can't perform this optimization.
3535 return false;
3536 case X86::COND_S: case X86::COND_NS:
3537 // If SF is used, but the instruction doesn't update the SF, then we
3538 // can't do the optimization.
3539 if (NoSignFlag)
3540 return false;
3541 break;
3542 }
3543
3544 // If we're updating the condition code check if we have to reverse the
3545 // condition.
3546 if (ShouldUpdateCC)
3547 switch (OldCC) {
3548 default:
3549 return false;
3550 case X86::COND_E:
3551 ReplacementCC = NewCC;
3552 break;
3553 case X86::COND_NE:
3554 ReplacementCC = GetOppositeBranchCondition(NewCC);
3555 break;
3556 }
3557 } else if (IsSwapped) {
3558 // If we have SUB(r1, r2) and CMP(r2, r1), the condition code needs
3559 // to be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
3560 // We swap the condition code and synthesize the new opcode.
3561 ReplacementCC = getSwappedCondition(OldCC);
3562 if (ReplacementCC == X86::COND_INVALID) return false;
3563 }
3564
3565 if ((ShouldUpdateCC || IsSwapped) && ReplacementCC != OldCC) {
3566 // Push the MachineInstr to OpsToUpdate.
3567 // If it is safe to remove CmpInstr, the condition code of these
3568 // instructions will be modified.
3569 OpsToUpdate.push_back(std::make_pair(&*I, ReplacementCC));
3570 }
3571 if (ModifyEFLAGS || Instr.killsRegister(X86::EFLAGS, TRI)) {
3572 // It is safe to remove CmpInstr if EFLAGS is updated again or killed.
3573 IsSafe = true;
3574 break;
3575 }
3576 }
3577
3578 // If EFLAGS is not killed nor re-defined, we should check whether it is
3579 // live-out. If it is live-out, do not optimize.
3580 if ((IsCmpZero || IsSwapped) && !IsSafe) {
3581 MachineBasicBlock *MBB = CmpInstr.getParent();
3582 for (MachineBasicBlock *Successor : MBB->successors())
3583 if (Successor->isLiveIn(X86::EFLAGS))
3584 return false;
3585 }
3586
3587 // The instruction to be updated is either Sub or MI.
3588 Sub = IsCmpZero ? MI : Sub;
3589 // Move Movr0Inst to the appropriate place before Sub.
3590 if (Movr0Inst) {
3591 // Look backwards until we find a def that doesn't use the current EFLAGS.
3592 Def = Sub;
3593 MachineBasicBlock::reverse_iterator InsertI = Def.getReverse(),
3594 InsertE = Sub->getParent()->rend();
3595 for (; InsertI != InsertE; ++InsertI) {
3596 MachineInstr *Instr = &*InsertI;
3597 if (!Instr->readsRegister(X86::EFLAGS, TRI) &&
3598 Instr->modifiesRegister(X86::EFLAGS, TRI)) {
3599 Sub->getParent()->remove(Movr0Inst);
3600 Instr->getParent()->insert(MachineBasicBlock::iterator(Instr),
3601 Movr0Inst);
3602 break;
3603 }
3604 }
3605 if (InsertI == InsertE)
3606 return false;
3607 }
3608
3609 // Make sure Sub instruction defines EFLAGS and mark the def live.
3610 unsigned i = 0, e = Sub->getNumOperands();
3611 for (; i != e; ++i) {
3612 MachineOperand &MO = Sub->getOperand(i);
3613 if (MO.isReg() && MO.isDef() && MO.getReg() == X86::EFLAGS) {
3614 MO.setIsDead(false);
3615 break;
3616 }
3617 }
3618 assert(i != e && "Unable to locate a def EFLAGS operand")((i != e && "Unable to locate a def EFLAGS operand") ?
static_cast<void> (0) : __assert_fail ("i != e && \"Unable to locate a def EFLAGS operand\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 3618, __PRETTY_FUNCTION__));
3619
3620 CmpInstr.eraseFromParent();
3621
3622 // Modify the condition code of instructions in OpsToUpdate.
3623 for (auto &Op : OpsToUpdate) {
3624 Op.first->getOperand(Op.first->getDesc().getNumOperands() - 1)
3625 .setImm(Op.second);
3626 }
3627 return true;
3628}
3629
3630/// Try to remove the load by folding it to a register
3631/// operand at the use. We fold the load instructions if load defines a virtual
3632/// register, the virtual register is used once in the same BB, and the
3633/// instructions in-between do not load or store, and have no side effects.
3634MachineInstr *X86InstrInfo::optimizeLoadInstr(MachineInstr &MI,
3635 const MachineRegisterInfo *MRI,
3636 unsigned &FoldAsLoadDefReg,
3637 MachineInstr *&DefMI) const {
3638 // Check whether we can move DefMI here.
3639 DefMI = MRI->getVRegDef(FoldAsLoadDefReg);
3640 assert(DefMI)((DefMI) ? static_cast<void> (0) : __assert_fail ("DefMI"
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 3640, __PRETTY_FUNCTION__));
3641 bool SawStore = false;
3642 if (!DefMI->isSafeToMove(nullptr, SawStore))
3643 return nullptr;
3644
3645 // Collect information about virtual register operands of MI.
3646 SmallVector<unsigned, 1> SrcOperandIds;
3647 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
3648 MachineOperand &MO = MI.getOperand(i);
3649 if (!MO.isReg())
3650 continue;
3651 unsigned Reg = MO.getReg();
3652 if (Reg != FoldAsLoadDefReg)
3653 continue;
3654 // Do not fold if we have a subreg use or a def.
3655 if (MO.getSubReg() || MO.isDef())
3656 return nullptr;
3657 SrcOperandIds.push_back(i);
3658 }
3659 if (SrcOperandIds.empty())
3660 return nullptr;
3661
3662 // Check whether we can fold the def into SrcOperandId.
3663 if (MachineInstr *FoldMI = foldMemoryOperand(MI, SrcOperandIds, *DefMI)) {
3664 FoldAsLoadDefReg = 0;
3665 return FoldMI;
3666 }
3667
3668 return nullptr;
3669}
3670
3671/// Expand a single-def pseudo instruction to a two-addr
3672/// instruction with two undef reads of the register being defined.
3673/// This is used for mapping:
3674/// %xmm4 = V_SET0
3675/// to:
3676/// %xmm4 = PXORrr undef %xmm4, undef %xmm4
3677///
3678static bool Expand2AddrUndef(MachineInstrBuilder &MIB,
3679 const MCInstrDesc &Desc) {
3680 assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.")((Desc.getNumOperands() == 3 && "Expected two-addr instruction."
) ? static_cast<void> (0) : __assert_fail ("Desc.getNumOperands() == 3 && \"Expected two-addr instruction.\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 3680, __PRETTY_FUNCTION__));
3681 unsigned Reg = MIB->getOperand(0).getReg();
3682 MIB->setDesc(Desc);
3683
3684 // MachineInstr::addOperand() will insert explicit operands before any
3685 // implicit operands.
3686 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
3687 // But we don't trust that.
3688 assert(MIB->getOperand(1).getReg() == Reg &&((MIB->getOperand(1).getReg() == Reg && MIB->getOperand
(2).getReg() == Reg && "Misplaced operand") ? static_cast
<void> (0) : __assert_fail ("MIB->getOperand(1).getReg() == Reg && MIB->getOperand(2).getReg() == Reg && \"Misplaced operand\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 3689, __PRETTY_FUNCTION__))
3689 MIB->getOperand(2).getReg() == Reg && "Misplaced operand")((MIB->getOperand(1).getReg() == Reg && MIB->getOperand
(2).getReg() == Reg && "Misplaced operand") ? static_cast
<void> (0) : __assert_fail ("MIB->getOperand(1).getReg() == Reg && MIB->getOperand(2).getReg() == Reg && \"Misplaced operand\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 3689, __PRETTY_FUNCTION__));
3690 return true;
3691}
3692
3693/// Expand a single-def pseudo instruction to a two-addr
3694/// instruction with two %k0 reads.
3695/// This is used for mapping:
3696/// %k4 = K_SET1
3697/// to:
3698/// %k4 = KXNORrr %k0, %k0
3699static bool Expand2AddrKreg(MachineInstrBuilder &MIB,
3700 const MCInstrDesc &Desc, unsigned Reg) {
3701 assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.")((Desc.getNumOperands() == 3 && "Expected two-addr instruction."
) ? static_cast<void> (0) : __assert_fail ("Desc.getNumOperands() == 3 && \"Expected two-addr instruction.\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 3701, __PRETTY_FUNCTION__));
3702 MIB->setDesc(Desc);
3703 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
3704 return true;
3705}
3706
3707static bool expandMOV32r1(MachineInstrBuilder &MIB, const TargetInstrInfo &TII,
3708 bool MinusOne) {
3709 MachineBasicBlock &MBB = *MIB->getParent();
3710 DebugLoc DL = MIB->getDebugLoc();
3711 unsigned Reg = MIB->getOperand(0).getReg();
3712
3713 // Insert the XOR.
3714 BuildMI(MBB, MIB.getInstr(), DL, TII.get(X86::XOR32rr), Reg)
3715 .addReg(Reg, RegState::Undef)
3716 .addReg(Reg, RegState::Undef);
3717
3718 // Turn the pseudo into an INC or DEC.
3719 MIB->setDesc(TII.get(MinusOne ? X86::DEC32r : X86::INC32r));
3720 MIB.addReg(Reg);
3721
3722 return true;
3723}
3724
3725static bool ExpandMOVImmSExti8(MachineInstrBuilder &MIB,
3726 const TargetInstrInfo &TII,
3727 const X86Subtarget &Subtarget) {
3728 MachineBasicBlock &MBB = *MIB->getParent();
3729 DebugLoc DL = MIB->getDebugLoc();
3730 int64_t Imm = MIB->getOperand(1).getImm();
3731 assert(Imm != 0 && "Using push/pop for 0 is not efficient.")((Imm != 0 && "Using push/pop for 0 is not efficient."
) ? static_cast<void> (0) : __assert_fail ("Imm != 0 && \"Using push/pop for 0 is not efficient.\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 3731, __PRETTY_FUNCTION__));
3732 MachineBasicBlock::iterator I = MIB.getInstr();
3733
3734 int StackAdjustment;
3735
3736 if (Subtarget.is64Bit()) {
3737 assert(MIB->getOpcode() == X86::MOV64ImmSExti8 ||((MIB->getOpcode() == X86::MOV64ImmSExti8 || MIB->getOpcode
() == X86::MOV32ImmSExti8) ? static_cast<void> (0) : __assert_fail
("MIB->getOpcode() == X86::MOV64ImmSExti8 || MIB->getOpcode() == X86::MOV32ImmSExti8"
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 3738, __PRETTY_FUNCTION__))
3738 MIB->getOpcode() == X86::MOV32ImmSExti8)((MIB->getOpcode() == X86::MOV64ImmSExti8 || MIB->getOpcode
() == X86::MOV32ImmSExti8) ? static_cast<void> (0) : __assert_fail
("MIB->getOpcode() == X86::MOV64ImmSExti8 || MIB->getOpcode() == X86::MOV32ImmSExti8"
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 3738, __PRETTY_FUNCTION__));
3739
3740 // Can't use push/pop lowering if the function might write to the red zone.
3741 X86MachineFunctionInfo *X86FI =
3742 MBB.getParent()->getInfo<X86MachineFunctionInfo>();
3743 if (X86FI->getUsesRedZone()) {
3744 MIB->setDesc(TII.get(MIB->getOpcode() ==
3745 X86::MOV32ImmSExti8 ? X86::MOV32ri : X86::MOV64ri));
3746 return true;
3747 }
3748
3749 // 64-bit mode doesn't have 32-bit push/pop, so use 64-bit operations and
3750 // widen the register if necessary.
3751 StackAdjustment = 8;
3752 BuildMI(MBB, I, DL, TII.get(X86::PUSH64i8)).addImm(Imm);
3753 MIB->setDesc(TII.get(X86::POP64r));
3754 MIB->getOperand(0)
3755 .setReg(getX86SubSuperRegister(MIB->getOperand(0).getReg(), 64));
3756 } else {
3757 assert(MIB->getOpcode() == X86::MOV32ImmSExti8)((MIB->getOpcode() == X86::MOV32ImmSExti8) ? static_cast<
void> (0) : __assert_fail ("MIB->getOpcode() == X86::MOV32ImmSExti8"
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 3757, __PRETTY_FUNCTION__));
3758 StackAdjustment = 4;
3759 BuildMI(MBB, I, DL, TII.get(X86::PUSH32i8)).addImm(Imm);
3760 MIB->setDesc(TII.get(X86::POP32r));
3761 }
3762
3763 // Build CFI if necessary.
3764 MachineFunction &MF = *MBB.getParent();
3765 const X86FrameLowering *TFL = Subtarget.getFrameLowering();
3766 bool IsWin64Prologue = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
3767 bool NeedsDwarfCFI =
3768 !IsWin64Prologue &&
3769 (MF.getMMI().hasDebugInfo() || MF.getFunction().needsUnwindTableEntry());
3770 bool EmitCFI = !TFL->hasFP(MF) && NeedsDwarfCFI;
3771 if (EmitCFI) {
3772 TFL->BuildCFI(MBB, I, DL,
3773 MCCFIInstruction::createAdjustCfaOffset(nullptr, StackAdjustment));
3774 TFL->BuildCFI(MBB, std::next(I), DL,
3775 MCCFIInstruction::createAdjustCfaOffset(nullptr, -StackAdjustment));
3776 }
3777
3778 return true;
3779}
3780
3781// LoadStackGuard has so far only been implemented for 64-bit MachO. Different
3782// code sequence is needed for other targets.
3783static void expandLoadStackGuard(MachineInstrBuilder &MIB,
3784 const TargetInstrInfo &TII) {
3785 MachineBasicBlock &MBB = *MIB->getParent();
3786 DebugLoc DL = MIB->getDebugLoc();
3787 unsigned Reg = MIB->getOperand(0).getReg();
3788 const GlobalValue *GV =
3789 cast<GlobalValue>((*MIB->memoperands_begin())->getValue());
3790 auto Flags = MachineMemOperand::MOLoad |
3791 MachineMemOperand::MODereferenceable |
3792 MachineMemOperand::MOInvariant;
3793 MachineMemOperand *MMO = MBB.getParent()->getMachineMemOperand(
3794 MachinePointerInfo::getGOT(*MBB.getParent()), Flags, 8, 8);
3795 MachineBasicBlock::iterator I = MIB.getInstr();
3796
3797 BuildMI(MBB, I, DL, TII.get(X86::MOV64rm), Reg).addReg(X86::RIP).addImm(1)
3798 .addReg(0).addGlobalAddress(GV, 0, X86II::MO_GOTPCREL).addReg(0)
3799 .addMemOperand(MMO);
3800 MIB->setDebugLoc(DL);
3801 MIB->setDesc(TII.get(X86::MOV64rm));
3802 MIB.addReg(Reg, RegState::Kill).addImm(1).addReg(0).addImm(0).addReg(0);
3803}
3804
3805static bool expandXorFP(MachineInstrBuilder &MIB, const TargetInstrInfo &TII) {
3806 MachineBasicBlock &MBB = *MIB->getParent();
3807 MachineFunction &MF = *MBB.getParent();
3808 const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
3809 const X86RegisterInfo *TRI = Subtarget.getRegisterInfo();
3810 unsigned XorOp =
3811 MIB->getOpcode() == X86::XOR64_FP ? X86::XOR64rr : X86::XOR32rr;
3812 MIB->setDesc(TII.get(XorOp));
3813 MIB.addReg(TRI->getFrameRegister(MF), RegState::Undef);
3814 return true;
3815}
3816
3817// This is used to handle spills for 128/256-bit registers when we have AVX512,
3818// but not VLX. If it uses an extended register we need to use an instruction
3819// that loads the lower 128/256-bit, but is available with only AVX512F.
3820static bool expandNOVLXLoad(MachineInstrBuilder &MIB,
3821 const TargetRegisterInfo *TRI,
3822 const MCInstrDesc &LoadDesc,
3823 const MCInstrDesc &BroadcastDesc,
3824 unsigned SubIdx) {
3825 unsigned DestReg = MIB->getOperand(0).getReg();
3826 // Check if DestReg is XMM16-31 or YMM16-31.
3827 if (TRI->getEncodingValue(DestReg) < 16) {
3828 // We can use a normal VEX encoded load.
3829 MIB->setDesc(LoadDesc);
3830 } else {
3831 // Use a 128/256-bit VBROADCAST instruction.
3832 MIB->setDesc(BroadcastDesc);
3833 // Change the destination to a 512-bit register.
3834 DestReg = TRI->getMatchingSuperReg(DestReg, SubIdx, &X86::VR512RegClass);
3835 MIB->getOperand(0).setReg(DestReg);
3836 }
3837 return true;
3838}
3839
3840// This is used to handle spills for 128/256-bit registers when we have AVX512,
3841// but not VLX. If it uses an extended register we need to use an instruction
3842// that stores the lower 128/256-bit, but is available with only AVX512F.
3843static bool expandNOVLXStore(MachineInstrBuilder &MIB,
3844 const TargetRegisterInfo *TRI,
3845 const MCInstrDesc &StoreDesc,
3846 const MCInstrDesc &ExtractDesc,
3847 unsigned SubIdx) {
3848 unsigned SrcReg = MIB->getOperand(X86::AddrNumOperands).getReg();
3849 // Check if DestReg is XMM16-31 or YMM16-31.
3850 if (TRI->getEncodingValue(SrcReg) < 16) {
3851 // We can use a normal VEX encoded store.
3852 MIB->setDesc(StoreDesc);
3853 } else {
3854 // Use a VEXTRACTF instruction.
3855 MIB->setDesc(ExtractDesc);
3856 // Change the destination to a 512-bit register.
3857 SrcReg = TRI->getMatchingSuperReg(SrcReg, SubIdx, &X86::VR512RegClass);
3858 MIB->getOperand(X86::AddrNumOperands).setReg(SrcReg);
3859 MIB.addImm(0x0); // Append immediate to extract from the lower bits.
3860 }
3861
3862 return true;
3863}
3864
3865static bool expandSHXDROT(MachineInstrBuilder &MIB, const MCInstrDesc &Desc) {
3866 MIB->setDesc(Desc);
3867 int64_t ShiftAmt = MIB->getOperand(2).getImm();
3868 // Temporarily remove the immediate so we can add another source register.
3869 MIB->RemoveOperand(2);
3870 // Add the register. Don't copy the kill flag if there is one.
3871 MIB.addReg(MIB->getOperand(1).getReg(),
3872 getUndefRegState(MIB->getOperand(1).isUndef()));
3873 // Add back the immediate.
3874 MIB.addImm(ShiftAmt);
3875 return true;
3876}
3877
3878bool X86InstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
3879 bool HasAVX = Subtarget.hasAVX();
3880 MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI);
3881 switch (MI.getOpcode()) {
3882 case X86::MOV32r0:
3883 return Expand2AddrUndef(MIB, get(X86::XOR32rr));
3884 case X86::MOV32r1:
3885 return expandMOV32r1(MIB, *this, /*MinusOne=*/ false);
3886 case X86::MOV32r_1:
3887 return expandMOV32r1(MIB, *this, /*MinusOne=*/ true);
3888 case X86::MOV32ImmSExti8:
3889 case X86::MOV64ImmSExti8:
3890 return ExpandMOVImmSExti8(MIB, *this, Subtarget);
3891 case X86::SETB_C8r:
3892 return Expand2AddrUndef(MIB, get(X86::SBB8rr));
3893 case X86::SETB_C16r:
3894 return Expand2AddrUndef(MIB, get(X86::SBB16rr));
3895 case X86::SETB_C32r:
3896 return Expand2AddrUndef(MIB, get(X86::SBB32rr));
3897 case X86::SETB_C64r:
3898 return Expand2AddrUndef(MIB, get(X86::SBB64rr));
3899 case X86::MMX_SET0:
3900 return Expand2AddrUndef(MIB, get(X86::MMX_PXORirr));
3901 case X86::V_SET0:
3902 case X86::FsFLD0SS:
3903 case X86::FsFLD0SD:
3904 return Expand2AddrUndef(MIB, get(HasAVX ? X86::VXORPSrr : X86::XORPSrr));
3905 case X86::AVX_SET0: {
3906 assert(HasAVX && "AVX not supported")((HasAVX && "AVX not supported") ? static_cast<void
> (0) : __assert_fail ("HasAVX && \"AVX not supported\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 3906, __PRETTY_FUNCTION__));
3907 const TargetRegisterInfo *TRI = &getRegisterInfo();
3908 unsigned SrcReg = MIB->getOperand(0).getReg();
3909 unsigned XReg = TRI->getSubReg(SrcReg, X86::sub_xmm);
3910 MIB->getOperand(0).setReg(XReg);
3911 Expand2AddrUndef(MIB, get(X86::VXORPSrr));
3912 MIB.addReg(SrcReg, RegState::ImplicitDefine);
3913 return true;
3914 }
3915 case X86::AVX512_128_SET0:
3916 case X86::AVX512_FsFLD0SS:
3917 case X86::AVX512_FsFLD0SD: {
3918 bool HasVLX = Subtarget.hasVLX();
3919 unsigned SrcReg = MIB->getOperand(0).getReg();
3920 const TargetRegisterInfo *TRI = &getRegisterInfo();
3921 if (HasVLX || TRI->getEncodingValue(SrcReg) < 16)
3922 return Expand2AddrUndef(MIB,
3923 get(HasVLX ? X86::VPXORDZ128rr : X86::VXORPSrr));
3924 // Extended register without VLX. Use a larger XOR.
3925 SrcReg =
3926 TRI->getMatchingSuperReg(SrcReg, X86::sub_xmm, &X86::VR512RegClass);
3927 MIB->getOperand(0).setReg(SrcReg);
3928 return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
3929 }
3930 case X86::AVX512_256_SET0:
3931 case X86::AVX512_512_SET0: {
3932 bool HasVLX = Subtarget.hasVLX();
3933 unsigned SrcReg = MIB->getOperand(0).getReg();
3934 const TargetRegisterInfo *TRI = &getRegisterInfo();
3935 if (HasVLX || TRI->getEncodingValue(SrcReg) < 16) {
3936 unsigned XReg = TRI->getSubReg(SrcReg, X86::sub_xmm);
3937 MIB->getOperand(0).setReg(XReg);
3938 Expand2AddrUndef(MIB,
3939 get(HasVLX ? X86::VPXORDZ128rr : X86::VXORPSrr));
3940 MIB.addReg(SrcReg, RegState::ImplicitDefine);
3941 return true;
3942 }
3943 if (MI.getOpcode() == X86::AVX512_256_SET0) {
3944 // No VLX so we must reference a zmm.
3945 unsigned ZReg =
3946 TRI->getMatchingSuperReg(SrcReg, X86::sub_ymm, &X86::VR512RegClass);
3947 MIB->getOperand(0).setReg(ZReg);
3948 }
3949 return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
3950 }
3951 case X86::V_SETALLONES:
3952 return Expand2AddrUndef(MIB, get(HasAVX ? X86::VPCMPEQDrr : X86::PCMPEQDrr));
3953 case X86::AVX2_SETALLONES:
3954 return Expand2AddrUndef(MIB, get(X86::VPCMPEQDYrr));
3955 case X86::AVX1_SETALLONES: {
3956 unsigned Reg = MIB->getOperand(0).getReg();
3957 // VCMPPSYrri with an immediate 0xf should produce VCMPTRUEPS.
3958 MIB->setDesc(get(X86::VCMPPSYrri));
3959 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef).addImm(0xf);
3960 return true;
3961 }
3962 case X86::AVX512_512_SETALLONES: {
3963 unsigned Reg = MIB->getOperand(0).getReg();
3964 MIB->setDesc(get(X86::VPTERNLOGDZrri));
3965 // VPTERNLOGD needs 3 register inputs and an immediate.
3966 // 0xff will return 1s for any input.
3967 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef)
3968 .addReg(Reg, RegState::Undef).addImm(0xff);
3969 return true;
3970 }
3971 case X86::AVX512_512_SEXT_MASK_32:
3972 case X86::AVX512_512_SEXT_MASK_64: {
3973 unsigned Reg = MIB->getOperand(0).getReg();
3974 unsigned MaskReg = MIB->getOperand(1).getReg();
3975 unsigned MaskState = getRegState(MIB->getOperand(1));
3976 unsigned Opc = (MI.getOpcode() == X86::AVX512_512_SEXT_MASK_64) ?
3977 X86::VPTERNLOGQZrrikz : X86::VPTERNLOGDZrrikz;
3978 MI.RemoveOperand(1);
3979 MIB->setDesc(get(Opc));
3980 // VPTERNLOG needs 3 register inputs and an immediate.
3981 // 0xff will return 1s for any input.
3982 MIB.addReg(Reg, RegState::Undef).addReg(MaskReg, MaskState)
3983 .addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef).addImm(0xff);
3984 return true;
3985 }
3986 case X86::VMOVAPSZ128rm_NOVLX:
3987 return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVAPSrm),
3988 get(X86::VBROADCASTF32X4rm), X86::sub_xmm);
3989 case X86::VMOVUPSZ128rm_NOVLX:
3990 return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVUPSrm),
3991 get(X86::VBROADCASTF32X4rm), X86::sub_xmm);
3992 case X86::VMOVAPSZ256rm_NOVLX:
3993 return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVAPSYrm),
3994 get(X86::VBROADCASTF64X4rm), X86::sub_ymm);
3995 case X86::VMOVUPSZ256rm_NOVLX:
3996 return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVUPSYrm),
3997 get(X86::VBROADCASTF64X4rm), X86::sub_ymm);
3998 case X86::VMOVAPSZ128mr_NOVLX:
3999 return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVAPSmr),
4000 get(X86::VEXTRACTF32x4Zmr), X86::sub_xmm);
4001 case X86::VMOVUPSZ128mr_NOVLX:
4002 return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVUPSmr),
4003 get(X86::VEXTRACTF32x4Zmr), X86::sub_xmm);
4004 case X86::VMOVAPSZ256mr_NOVLX:
4005 return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVAPSYmr),
4006 get(X86::VEXTRACTF64x4Zmr), X86::sub_ymm);
4007 case X86::VMOVUPSZ256mr_NOVLX:
4008 return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVUPSYmr),
4009 get(X86::VEXTRACTF64x4Zmr), X86::sub_ymm);
4010 case X86::MOV32ri64: {
4011 unsigned Reg = MIB->getOperand(0).getReg();
4012 unsigned Reg32 = RI.getSubReg(Reg, X86::sub_32bit);
4013 MI.setDesc(get(X86::MOV32ri));
4014 MIB->getOperand(0).setReg(Reg32);
4015 MIB.addReg(Reg, RegState::ImplicitDefine);
4016 return true;
4017 }
4018
4019 // KNL does not recognize dependency-breaking idioms for mask registers,
4020 // so kxnor %k1, %k1, %k2 has a RAW dependence on %k1.
4021 // Using %k0 as the undef input register is a performance heuristic based
4022 // on the assumption that %k0 is used less frequently than the other mask
4023 // registers, since it is not usable as a write mask.
4024 // FIXME: A more advanced approach would be to choose the best input mask
4025 // register based on context.
4026 case X86::KSET0W: return Expand2AddrKreg(MIB, get(X86::KXORWrr), X86::K0);
4027 case X86::KSET0D: return Expand2AddrKreg(MIB, get(X86::KXORDrr), X86::K0);
4028 case X86::KSET0Q: return Expand2AddrKreg(MIB, get(X86::KXORQrr), X86::K0);
4029 case X86::KSET1W: return Expand2AddrKreg(MIB, get(X86::KXNORWrr), X86::K0);
4030 case X86::KSET1D: return Expand2AddrKreg(MIB, get(X86::KXNORDrr), X86::K0);
4031 case X86::KSET1Q: return Expand2AddrKreg(MIB, get(X86::KXNORQrr), X86::K0);
4032 case TargetOpcode::LOAD_STACK_GUARD:
4033 expandLoadStackGuard(MIB, *this);
4034 return true;
4035 case X86::XOR64_FP:
4036 case X86::XOR32_FP:
4037 return expandXorFP(MIB, *this);
4038 case X86::SHLDROT32ri: return expandSHXDROT(MIB, get(X86::SHLD32rri8));
4039 case X86::SHLDROT64ri: return expandSHXDROT(MIB, get(X86::SHLD64rri8));
4040 case X86::SHRDROT32ri: return expandSHXDROT(MIB, get(X86::SHRD32rri8));
4041 case X86::SHRDROT64ri: return expandSHXDROT(MIB, get(X86::SHRD64rri8));
4042 case X86::ADD8rr_DB: MIB->setDesc(get(X86::OR8rr)); break;
4043 case X86::ADD16rr_DB: MIB->setDesc(get(X86::OR16rr)); break;
4044 case X86::ADD32rr_DB: MIB->setDesc(get(X86::OR32rr)); break;
4045 case X86::ADD64rr_DB: MIB->setDesc(get(X86::OR64rr)); break;
4046 case X86::ADD8ri_DB: MIB->setDesc(get(X86::OR8ri)); break;
4047 case X86::ADD16ri_DB: MIB->setDesc(get(X86::OR16ri)); break;
4048 case X86::ADD32ri_DB: MIB->setDesc(get(X86::OR32ri)); break;
4049 case X86::ADD64ri32_DB: MIB->setDesc(get(X86::OR64ri32)); break;
4050 case X86::ADD16ri8_DB: MIB->setDesc(get(X86::OR16ri8)); break;
4051 case X86::ADD32ri8_DB: MIB->setDesc(get(X86::OR32ri8)); break;
4052 case X86::ADD64ri8_DB: MIB->setDesc(get(X86::OR64ri8)); break;
4053 }
4054 return false;
4055}
4056
4057/// Return true for all instructions that only update
4058/// the first 32 or 64-bits of the destination register and leave the rest
4059/// unmodified. This can be used to avoid folding loads if the instructions
4060/// only update part of the destination register, and the non-updated part is
4061/// not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these
4062/// instructions breaks the partial register dependency and it can improve
4063/// performance. e.g.:
4064///
4065/// movss (%rdi), %xmm0
4066/// cvtss2sd %xmm0, %xmm0
4067///
4068/// Instead of
4069/// cvtss2sd (%rdi), %xmm0
4070///
4071/// FIXME: This should be turned into a TSFlags.
4072///
4073static bool hasPartialRegUpdate(unsigned Opcode,
4074 const X86Subtarget &Subtarget,
4075 bool ForLoadFold = false) {
4076 switch (Opcode) {
4077 case X86::CVTSI2SSrr:
4078 case X86::CVTSI2SSrm:
4079 case X86::CVTSI642SSrr:
4080 case X86::CVTSI642SSrm:
4081 case X86::CVTSI2SDrr:
4082 case X86::CVTSI2SDrm:
4083 case X86::CVTSI642SDrr:
4084 case X86::CVTSI642SDrm:
4085 // Load folding won't effect the undef register update since the input is
4086 // a GPR.
4087 return !ForLoadFold;
4088 case X86::CVTSD2SSrr:
4089 case X86::CVTSD2SSrm:
4090 case X86::CVTSS2SDrr:
4091 case X86::CVTSS2SDrm:
4092 case X86::MOVHPDrm:
4093 case X86::MOVHPSrm:
4094 case X86::MOVLPDrm:
4095 case X86::MOVLPSrm:
4096 case X86::RCPSSr:
4097 case X86::RCPSSm:
4098 case X86::RCPSSr_Int:
4099 case X86::RCPSSm_Int:
4100 case X86::ROUNDSDr:
4101 case X86::ROUNDSDm:
4102 case X86::ROUNDSSr:
4103 case X86::ROUNDSSm:
4104 case X86::RSQRTSSr:
4105 case X86::RSQRTSSm:
4106 case X86::RSQRTSSr_Int:
4107 case X86::RSQRTSSm_Int:
4108 case X86::SQRTSSr:
4109 case X86::SQRTSSm:
4110 case X86::SQRTSSr_Int:
4111 case X86::SQRTSSm_Int:
4112 case X86::SQRTSDr:
4113 case X86::SQRTSDm:
4114 case X86::SQRTSDr_Int:
4115 case X86::SQRTSDm_Int:
4116 return true;
4117 // GPR
4118 case X86::POPCNT32rm:
4119 case X86::POPCNT32rr:
4120 case X86::POPCNT64rm:
4121 case X86::POPCNT64rr:
4122 return Subtarget.hasPOPCNTFalseDeps();
4123 case X86::LZCNT32rm:
4124 case X86::LZCNT32rr:
4125 case X86::LZCNT64rm:
4126 case X86::LZCNT64rr:
4127 case X86::TZCNT32rm:
4128 case X86::TZCNT32rr:
4129 case X86::TZCNT64rm:
4130 case X86::TZCNT64rr:
4131 return Subtarget.hasLZCNTFalseDeps();
4132 }
4133
4134 return false;
4135}
4136
4137/// Inform the BreakFalseDeps pass how many idle
4138/// instructions we would like before a partial register update.
4139unsigned X86InstrInfo::getPartialRegUpdateClearance(
4140 const MachineInstr &MI, unsigned OpNum,
4141 const TargetRegisterInfo *TRI) const {
4142 if (OpNum != 0 || !hasPartialRegUpdate(MI.getOpcode(), Subtarget))
4143 return 0;
4144
4145 // If MI is marked as reading Reg, the partial register update is wanted.
4146 const MachineOperand &MO = MI.getOperand(0);
4147 unsigned Reg = MO.getReg();
4148 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
4149 if (MO.readsReg() || MI.readsVirtualRegister(Reg))
4150 return 0;
4151 } else {
4152 if (MI.readsRegister(Reg, TRI))
4153 return 0;
4154 }
4155
4156 // If any instructions in the clearance range are reading Reg, insert a
4157 // dependency breaking instruction, which is inexpensive and is likely to
4158 // be hidden in other instruction's cycles.
4159 return PartialRegUpdateClearance;
4160}
4161
4162// Return true for any instruction the copies the high bits of the first source
4163// operand into the unused high bits of the destination operand.
4164static bool hasUndefRegUpdate(unsigned Opcode, bool ForLoadFold = false) {
4165 switch (Opcode) {
4166 case X86::VCVTSI2SSrr:
4167 case X86::VCVTSI2SSrm:
4168 case X86::VCVTSI2SSrr_Int:
4169 case X86::VCVTSI2SSrm_Int:
4170 case X86::VCVTSI642SSrr:
4171 case X86::VCVTSI642SSrm:
4172 case X86::VCVTSI642SSrr_Int:
4173 case X86::VCVTSI642SSrm_Int:
4174 case X86::VCVTSI2SDrr:
4175 case X86::VCVTSI2SDrm:
4176 case X86::VCVTSI2SDrr_Int:
4177 case X86::VCVTSI2SDrm_Int:
4178 case X86::VCVTSI642SDrr:
4179 case X86::VCVTSI642SDrm:
4180 case X86::VCVTSI642SDrr_Int:
4181 case X86::VCVTSI642SDrm_Int:
4182 // AVX-512
4183 case X86::VCVTSI2SSZrr:
4184 case X86::VCVTSI2SSZrm:
4185 case X86::VCVTSI2SSZrr_Int:
4186 case X86::VCVTSI2SSZrrb_Int:
4187 case X86::VCVTSI2SSZrm_Int:
4188 case X86::VCVTSI642SSZrr:
4189 case X86::VCVTSI642SSZrm:
4190 case X86::VCVTSI642SSZrr_Int:
4191 case X86::VCVTSI642SSZrrb_Int:
4192 case X86::VCVTSI642SSZrm_Int:
4193 case X86::VCVTSI2SDZrr:
4194 case X86::VCVTSI2SDZrm:
4195 case X86::VCVTSI2SDZrr_Int:
4196 case X86::VCVTSI2SDZrm_Int:
4197 case X86::VCVTSI642SDZrr:
4198 case X86::VCVTSI642SDZrm:
4199 case X86::VCVTSI642SDZrr_Int:
4200 case X86::VCVTSI642SDZrrb_Int:
4201 case X86::VCVTSI642SDZrm_Int:
4202 case X86::VCVTUSI2SSZrr:
4203 case X86::VCVTUSI2SSZrm:
4204 case X86::VCVTUSI2SSZrr_Int:
4205 case X86::VCVTUSI2SSZrrb_Int:
4206 case X86::VCVTUSI2SSZrm_Int:
4207 case X86::VCVTUSI642SSZrr:
4208 case X86::VCVTUSI642SSZrm:
4209 case X86::VCVTUSI642SSZrr_Int:
4210 case X86::VCVTUSI642SSZrrb_Int:
4211 case X86::VCVTUSI642SSZrm_Int:
4212 case X86::VCVTUSI2SDZrr:
4213 case X86::VCVTUSI2SDZrm:
4214 case X86::VCVTUSI2SDZrr_Int:
4215 case X86::VCVTUSI2SDZrm_Int:
4216 case X86::VCVTUSI642SDZrr:
4217 case X86::VCVTUSI642SDZrm:
4218 case X86::VCVTUSI642SDZrr_Int:
4219 case X86::VCVTUSI642SDZrrb_Int:
4220 case X86::VCVTUSI642SDZrm_Int:
4221 // Load folding won't effect the undef register update since the input is
4222 // a GPR.
4223 return !ForLoadFold;
4224 case X86::VCVTSD2SSrr:
4225 case X86::VCVTSD2SSrm:
4226 case X86::VCVTSD2SSrr_Int:
4227 case X86::VCVTSD2SSrm_Int:
4228 case X86::VCVTSS2SDrr:
4229 case X86::VCVTSS2SDrm:
4230 case X86::VCVTSS2SDrr_Int:
4231 case X86::VCVTSS2SDrm_Int:
4232 case X86::VRCPSSr:
4233 case X86::VRCPSSr_Int:
4234 case X86::VRCPSSm:
4235 case X86::VRCPSSm_Int:
4236 case X86::VROUNDSDr:
4237 case X86::VROUNDSDm:
4238 case X86::VROUNDSDr_Int:
4239 case X86::VROUNDSDm_Int:
4240 case X86::VROUNDSSr:
4241 case X86::VROUNDSSm:
4242 case X86::VROUNDSSr_Int:
4243 case X86::VROUNDSSm_Int:
4244 case X86::VRSQRTSSr:
4245 case X86::VRSQRTSSr_Int:
4246 case X86::VRSQRTSSm:
4247 case X86::VRSQRTSSm_Int:
4248 case X86::VSQRTSSr:
4249 case X86::VSQRTSSr_Int:
4250 case X86::VSQRTSSm:
4251 case X86::VSQRTSSm_Int:
4252 case X86::VSQRTSDr:
4253 case X86::VSQRTSDr_Int:
4254 case X86::VSQRTSDm:
4255 case X86::VSQRTSDm_Int:
4256 // AVX-512
4257 case X86::VCVTSD2SSZrr:
4258 case X86::VCVTSD2SSZrr_Int:
4259 case X86::VCVTSD2SSZrrb_Int:
4260 case X86::VCVTSD2SSZrm:
4261 case X86::VCVTSD2SSZrm_Int:
4262 case X86::VCVTSS2SDZrr:
4263 case X86::VCVTSS2SDZrr_Int:
4264 case X86::VCVTSS2SDZrrb_Int:
4265 case X86::VCVTSS2SDZrm:
4266 case X86::VCVTSS2SDZrm_Int:
4267 case X86::VGETEXPSDZr:
4268 case X86::VGETEXPSDZrb:
4269 case X86::VGETEXPSDZm:
4270 case X86::VGETEXPSSZr:
4271 case X86::VGETEXPSSZrb:
4272 case X86::VGETEXPSSZm:
4273 case X86::VGETMANTSDZrri:
4274 case X86::VGETMANTSDZrrib:
4275 case X86::VGETMANTSDZrmi:
4276 case X86::VGETMANTSSZrri:
4277 case X86::VGETMANTSSZrrib:
4278 case X86::VGETMANTSSZrmi:
4279 case X86::VRNDSCALESDZr:
4280 case X86::VRNDSCALESDZr_Int:
4281 case X86::VRNDSCALESDZrb_Int:
4282 case X86::VRNDSCALESDZm:
4283 case X86::VRNDSCALESDZm_Int:
4284 case X86::VRNDSCALESSZr:
4285 case X86::VRNDSCALESSZr_Int:
4286 case X86::VRNDSCALESSZrb_Int:
4287 case X86::VRNDSCALESSZm:
4288 case X86::VRNDSCALESSZm_Int:
4289 case X86::VRCP14SDZrr:
4290 case X86::VRCP14SDZrm:
4291 case X86::VRCP14SSZrr:
4292 case X86::VRCP14SSZrm:
4293 case X86::VRCP28SDZr:
4294 case X86::VRCP28SDZrb:
4295 case X86::VRCP28SDZm:
4296 case X86::VRCP28SSZr:
4297 case X86::VRCP28SSZrb:
4298 case X86::VRCP28SSZm:
4299 case X86::VREDUCESSZrmi:
4300 case X86::VREDUCESSZrri:
4301 case X86::VREDUCESSZrrib:
4302 case X86::VRSQRT14SDZrr:
4303 case X86::VRSQRT14SDZrm:
4304 case X86::VRSQRT14SSZrr:
4305 case X86::VRSQRT14SSZrm:
4306 case X86::VRSQRT28SDZr:
4307 case X86::VRSQRT28SDZrb:
4308 case X86::VRSQRT28SDZm:
4309 case X86::VRSQRT28SSZr:
4310 case X86::VRSQRT28SSZrb:
4311 case X86::VRSQRT28SSZm:
4312 case X86::VSQRTSSZr:
4313 case X86::VSQRTSSZr_Int:
4314 case X86::VSQRTSSZrb_Int:
4315 case X86::VSQRTSSZm:
4316 case X86::VSQRTSSZm_Int:
4317 case X86::VSQRTSDZr:
4318 case X86::VSQRTSDZr_Int:
4319 case X86::VSQRTSDZrb_Int:
4320 case X86::VSQRTSDZm:
4321 case X86::VSQRTSDZm_Int:
4322 return true;
4323 }
4324
4325 return false;
4326}
4327
4328/// Inform the BreakFalseDeps pass how many idle instructions we would like
4329/// before certain undef register reads.
4330///
4331/// This catches the VCVTSI2SD family of instructions:
4332///
4333/// vcvtsi2sdq %rax, undef %xmm0, %xmm14
4334///
4335/// We should to be careful *not* to catch VXOR idioms which are presumably
4336/// handled specially in the pipeline:
4337///
4338/// vxorps undef %xmm1, undef %xmm1, %xmm1
4339///
4340/// Like getPartialRegUpdateClearance, this makes a strong assumption that the
4341/// high bits that are passed-through are not live.
4342unsigned
4343X86InstrInfo::getUndefRegClearance(const MachineInstr &MI, unsigned &OpNum,
4344 const TargetRegisterInfo *TRI) const {
4345 if (!hasUndefRegUpdate(MI.getOpcode()))
4346 return 0;
4347
4348 // Set the OpNum parameter to the first source operand.
4349 OpNum = 1;
4350
4351 const MachineOperand &MO = MI.getOperand(OpNum);
4352 if (MO.isUndef() && TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
4353 return UndefRegClearance;
4354 }
4355 return 0;
4356}
4357
4358void X86InstrInfo::breakPartialRegDependency(
4359 MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const {
4360 unsigned Reg = MI.getOperand(OpNum).getReg();
4361 // If MI kills this register, the false dependence is already broken.
4362 if (MI.killsRegister(Reg, TRI))
4363 return;
4364
4365 if (X86::VR128RegClass.contains(Reg)) {
4366 // These instructions are all floating point domain, so xorps is the best
4367 // choice.
4368 unsigned Opc = Subtarget.hasAVX() ? X86::VXORPSrr : X86::XORPSrr;
4369 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(Opc), Reg)
4370 .addReg(Reg, RegState::Undef)
4371 .addReg(Reg, RegState::Undef);
4372 MI.addRegisterKilled(Reg, TRI, true);
4373 } else if (X86::VR256RegClass.contains(Reg)) {
4374 // Use vxorps to clear the full ymm register.
4375 // It wants to read and write the xmm sub-register.
4376 unsigned XReg = TRI->getSubReg(Reg, X86::sub_xmm);
4377 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(X86::VXORPSrr), XReg)
4378 .addReg(XReg, RegState::Undef)
4379 .addReg(XReg, RegState::Undef)
4380 .addReg(Reg, RegState::ImplicitDefine);
4381 MI.addRegisterKilled(Reg, TRI, true);
4382 } else if (X86::GR64RegClass.contains(Reg)) {
4383 // Using XOR32rr because it has shorter encoding and zeros up the upper bits
4384 // as well.
4385 unsigned XReg = TRI->getSubReg(Reg, X86::sub_32bit);
4386 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(X86::XOR32rr), XReg)
4387 .addReg(XReg, RegState::Undef)
4388 .addReg(XReg, RegState::Undef)
4389 .addReg(Reg, RegState::ImplicitDefine);
4390 MI.addRegisterKilled(Reg, TRI, true);
4391 } else if (X86::GR32RegClass.contains(Reg)) {
4392 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(X86::XOR32rr), Reg)
4393 .addReg(Reg, RegState::Undef)
4394 .addReg(Reg, RegState::Undef);
4395 MI.addRegisterKilled(Reg, TRI, true);
4396 }
4397}
4398
4399static void addOperands(MachineInstrBuilder &MIB, ArrayRef<MachineOperand> MOs,
4400 int PtrOffset = 0) {
4401 unsigned NumAddrOps = MOs.size();
4402
4403 if (NumAddrOps < 4) {
4404 // FrameIndex only - add an immediate offset (whether its zero or not).
4405 for (unsigned i = 0; i != NumAddrOps; ++i)
4406 MIB.add(MOs[i]);
4407 addOffset(MIB, PtrOffset);
4408 } else {
4409 // General Memory Addressing - we need to add any offset to an existing
4410 // offset.
4411 assert(MOs.size() == 5 && "Unexpected memory operand list length")((MOs.size() == 5 && "Unexpected memory operand list length"
) ? static_cast<void> (0) : __assert_fail ("MOs.size() == 5 && \"Unexpected memory operand list length\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 4411, __PRETTY_FUNCTION__));
4412 for (unsigned i = 0; i != NumAddrOps; ++i) {
4413 const MachineOperand &MO = MOs[i];
4414 if (i == 3 && PtrOffset != 0) {
4415 MIB.addDisp(MO, PtrOffset);
4416 } else {
4417 MIB.add(MO);
4418 }
4419 }
4420 }
4421}
4422
4423static void updateOperandRegConstraints(MachineFunction &MF,
4424 MachineInstr &NewMI,
4425 const TargetInstrInfo &TII) {
4426 MachineRegisterInfo &MRI = MF.getRegInfo();
4427 const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
4428
4429 for (int Idx : llvm::seq<int>(0, NewMI.getNumOperands())) {
4430 MachineOperand &MO = NewMI.getOperand(Idx);
4431 // We only need to update constraints on virtual register operands.
4432 if (!MO.isReg())
4433 continue;
4434 unsigned Reg = MO.getReg();
4435 if (!TRI.isVirtualRegister(Reg))
4436 continue;
4437
4438 auto *NewRC = MRI.constrainRegClass(
4439 Reg, TII.getRegClass(NewMI.getDesc(), Idx, &TRI, MF));
4440 if (!NewRC) {
4441 LLVM_DEBUG(do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("x86-instr-info")) { dbgs() << "WARNING: Unable to update register constraint for operand "
<< Idx << " of instruction:\n"; NewMI.dump(); dbgs
() << "\n"; } } while (false)
4442 dbgs() << "WARNING: Unable to update register constraint for operand "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("x86-instr-info")) { dbgs() << "WARNING: Unable to update register constraint for operand "
<< Idx << " of instruction:\n"; NewMI.dump(); dbgs
() << "\n"; } } while (false)
4443 << Idx << " of instruction:\n";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("x86-instr-info")) { dbgs() << "WARNING: Unable to update register constraint for operand "
<< Idx << " of instruction:\n"; NewMI.dump(); dbgs
() << "\n"; } } while (false)
4444 NewMI.dump(); dbgs() << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("x86-instr-info")) { dbgs() << "WARNING: Unable to update register constraint for operand "
<< Idx << " of instruction:\n"; NewMI.dump(); dbgs
() << "\n"; } } while (false);
4445 }
4446 }
4447}
4448
4449static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
4450 ArrayRef<MachineOperand> MOs,
4451 MachineBasicBlock::iterator InsertPt,
4452 MachineInstr &MI,
4453 const TargetInstrInfo &TII) {
4454 // Create the base instruction with the memory operand as the first part.
4455 // Omit the implicit operands, something BuildMI can't do.
4456 MachineInstr *NewMI =
4457 MF.CreateMachineInstr(TII.get(Opcode), MI.getDebugLoc(), true);
4458 MachineInstrBuilder MIB(MF, NewMI);
4459 addOperands(MIB, MOs);
4460
4461 // Loop over the rest of the ri operands, converting them over.
4462 unsigned NumOps = MI.getDesc().getNumOperands() - 2;
4463 for (unsigned i = 0; i != NumOps; ++i) {
4464 MachineOperand &MO = MI.getOperand(i + 2);
4465 MIB.add(MO);
4466 }
4467 for (unsigned i = NumOps + 2, e = MI.getNumOperands(); i != e; ++i) {
4468 MachineOperand &MO = MI.getOperand(i);
4469 MIB.add(MO);
4470 }
4471
4472 updateOperandRegConstraints(MF, *NewMI, TII);
4473
4474 MachineBasicBlock *MBB = InsertPt->getParent();
4475 MBB->insert(InsertPt, NewMI);
4476
4477 return MIB;
4478}
4479
4480static MachineInstr *FuseInst(MachineFunction &MF, unsigned Opcode,
4481 unsigned OpNo, ArrayRef<MachineOperand> MOs,
4482 MachineBasicBlock::iterator InsertPt,
4483 MachineInstr &MI, const TargetInstrInfo &TII,
4484 int PtrOffset = 0) {
4485 // Omit the implicit operands, something BuildMI can't do.
4486 MachineInstr *NewMI =
4487 MF.CreateMachineInstr(TII.get(Opcode), MI.getDebugLoc(), true);
4488 MachineInstrBuilder MIB(MF, NewMI);
4489
4490 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
4491 MachineOperand &MO = MI.getOperand(i);
4492 if (i == OpNo) {
4493 assert(MO.isReg() && "Expected to fold into reg operand!")((MO.isReg() && "Expected to fold into reg operand!")
? static_cast<void> (0) : __assert_fail ("MO.isReg() && \"Expected to fold into reg operand!\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 4493, __PRETTY_FUNCTION__));
4494 addOperands(MIB, MOs, PtrOffset);
4495 } else {
4496 MIB.add(MO);
4497 }
4498 }
4499
4500 updateOperandRegConstraints(MF, *NewMI, TII);
4501
4502 MachineBasicBlock *MBB = InsertPt->getParent();
4503 MBB->insert(InsertPt, NewMI);
4504
4505 return MIB;
4506}
4507
4508static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
4509 ArrayRef<MachineOperand> MOs,
4510 MachineBasicBlock::iterator InsertPt,
4511 MachineInstr &MI) {
4512 MachineInstrBuilder MIB = BuildMI(*InsertPt->getParent(), InsertPt,
4513 MI.getDebugLoc(), TII.get(Opcode));
4514 addOperands(MIB, MOs);
4515 return MIB.addImm(0);
4516}
4517
4518MachineInstr *X86InstrInfo::foldMemoryOperandCustom(
4519 MachineFunction &MF, MachineInstr &MI, unsigned OpNum,
4520 ArrayRef<MachineOperand> MOs, MachineBasicBlock::iterator InsertPt,
4521 unsigned Size, unsigned Align) const {
4522 switch (MI.getOpcode()) {
4523 case X86::INSERTPSrr:
4524 case X86::VINSERTPSrr:
4525 case X86::VINSERTPSZrr:
4526 // Attempt to convert the load of inserted vector into a fold load
4527 // of a single float.
4528 if (OpNum == 2) {
4529 unsigned Imm = MI.getOperand(MI.getNumOperands() - 1).getImm();
4530 unsigned ZMask = Imm & 15;
4531 unsigned DstIdx = (Imm >> 4) & 3;
4532 unsigned SrcIdx = (Imm >> 6) & 3;
4533
4534 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
4535 const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum, &RI, MF);
4536 unsigned RCSize = TRI.getRegSizeInBits(*RC) / 8;
4537 if (Size <= RCSize && 4 <= Align) {
4538 int PtrOffset = SrcIdx * 4;
4539 unsigned NewImm = (DstIdx << 4) | ZMask;
4540 unsigned NewOpCode =
4541 (MI.getOpcode() == X86::VINSERTPSZrr) ? X86::VINSERTPSZrm :
4542 (MI.getOpcode() == X86::VINSERTPSrr) ? X86::VINSERTPSrm :
4543 X86::INSERTPSrm;
4544 MachineInstr *NewMI =
4545 FuseInst(MF, NewOpCode, OpNum, MOs, InsertPt, MI, *this, PtrOffset);
4546 NewMI->getOperand(NewMI->getNumOperands() - 1).setImm(NewImm);
4547 return NewMI;
4548 }
4549 }
4550 break;
4551 case X86::MOVHLPSrr:
4552 case X86::VMOVHLPSrr:
4553 case X86::VMOVHLPSZrr:
4554 // Move the upper 64-bits of the second operand to the lower 64-bits.
4555 // To fold the load, adjust the pointer to the upper and use (V)MOVLPS.
4556 // TODO: In most cases AVX doesn't have a 8-byte alignment requirement.
4557 if (OpNum == 2) {
4558 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
4559 const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum, &RI, MF);
4560 unsigned RCSize = TRI.getRegSizeInBits(*RC) / 8;
4561 if (Size <= RCSize && 8 <= Align) {
4562 unsigned NewOpCode =
4563 (MI.getOpcode() == X86::VMOVHLPSZrr) ? X86::VMOVLPSZ128rm :
4564 (MI.getOpcode() == X86::VMOVHLPSrr) ? X86::VMOVLPSrm :
4565 X86::MOVLPSrm;
4566 MachineInstr *NewMI =
4567 FuseInst(MF, NewOpCode, OpNum, MOs, InsertPt, MI, *this, 8);
4568 return NewMI;
4569 }
4570 }
4571 break;
4572 };
4573
4574 return nullptr;
4575}
4576
4577static bool shouldPreventUndefRegUpdateMemFold(MachineFunction &MF,
4578 MachineInstr &MI) {
4579 if (!hasUndefRegUpdate(MI.getOpcode(), /*ForLoadFold*/true) ||
4580 !MI.getOperand(1).isReg())
4581 return false;
4582
4583 // The are two cases we need to handle depending on where in the pipeline
4584 // the folding attempt is being made.
4585 // -Register has the undef flag set.
4586 // -Register is produced by the IMPLICIT_DEF instruction.
4587
4588 if (MI.getOperand(1).isUndef())
4589 return true;
4590
4591 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4592 MachineInstr *VRegDef = RegInfo.getUniqueVRegDef(MI.getOperand(1).getReg());
4593 return VRegDef && VRegDef->isImplicitDef();
4594}
4595
4596
4597MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
4598 MachineFunction &MF, MachineInstr &MI, unsigned OpNum,
4599 ArrayRef<MachineOperand> MOs, MachineBasicBlock::iterator InsertPt,
4600 unsigned Size, unsigned Align, bool AllowCommute) const {
4601 bool isSlowTwoMemOps = Subtarget.slowTwoMemOps();
4602 bool isTwoAddrFold = false;
4603
4604 // For CPUs that favor the register form of a call or push,
4605 // do not fold loads into calls or pushes, unless optimizing for size
4606 // aggressively.
4607 if (isSlowTwoMemOps && !MF.getFunction().hasMinSize() &&
4608 (MI.getOpcode() == X86::CALL32r || MI.getOpcode() == X86::CALL64r ||
4609 MI.getOpcode() == X86::PUSH16r || MI.getOpcode() == X86::PUSH32r ||
4610 MI.getOpcode() == X86::PUSH64r))
4611 return nullptr;
4612
4613 // Avoid partial and undef register update stalls unless optimizing for size.
4614 if (!MF.getFunction().hasOptSize() &&
4615 (hasPartialRegUpdate(MI.getOpcode(), Subtarget, /*ForLoadFold*/true) ||
4616 shouldPreventUndefRegUpdateMemFold(MF, MI)))
4617 return nullptr;
4618
4619 unsigned NumOps = MI.getDesc().getNumOperands();
4620 bool isTwoAddr =
4621 NumOps > 1 && MI.getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
4622
4623 // FIXME: AsmPrinter doesn't know how to handle
4624 // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
4625 if (MI.getOpcode() == X86::ADD32ri &&
4626 MI.getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
4627 return nullptr;
4628
4629 // GOTTPOFF relocation loads can only be folded into add instructions.
4630 // FIXME: Need to exclude other relocations that only support specific
4631 // instructions.
4632 if (MOs.size() == X86::AddrNumOperands &&
4633 MOs[X86::AddrDisp].getTargetFlags() == X86II::MO_GOTTPOFF &&
4634 MI.getOpcode() != X86::ADD64rr)
4635 return nullptr;
4636
4637 MachineInstr *NewMI = nullptr;
4638
4639 // Attempt to fold any custom cases we have.
4640 if (MachineInstr *CustomMI =
4641 foldMemoryOperandCustom(MF, MI, OpNum, MOs, InsertPt, Size, Align))
4642 return CustomMI;
4643
4644 const X86MemoryFoldTableEntry *I = nullptr;
4645
4646 // Folding a memory location into the two-address part of a two-address
4647 // instruction is different than folding it other places. It requires
4648 // replacing the *two* registers with the memory location.
4649 if (isTwoAddr && NumOps >= 2 && OpNum < 2 && MI.getOperand(0).isReg() &&
4650 MI.getOperand(1).isReg() &&
4651 MI.getOperand(0).getReg() == MI.getOperand(1).getReg()) {
4652 I = lookupTwoAddrFoldTable(MI.getOpcode());
4653 isTwoAddrFold = true;
4654 } else {
4655 if (OpNum == 0) {
4656 if (MI.getOpcode() == X86::MOV32r0) {
4657 NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, InsertPt, MI);
4658 if (NewMI)
4659 return NewMI;
4660 }
4661 }
4662
4663 I = lookupFoldTable(MI.getOpcode(), OpNum);
4664 }
4665
4666 if (I != nullptr) {
4667 unsigned Opcode = I->DstOp;
4668 unsigned MinAlign = (I->Flags & TB_ALIGN_MASK) >> TB_ALIGN_SHIFT;
4669 if (Align < MinAlign)
4670 return nullptr;
4671 bool NarrowToMOV32rm = false;
4672 if (Size) {
4673 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
4674 const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum,
4675 &RI, MF);
4676 unsigned RCSize = TRI.getRegSizeInBits(*RC) / 8;
4677 if (Size < RCSize) {
4678 // Check if it's safe to fold the load. If the size of the object is
4679 // narrower than the load width, then it's not.
4680 if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
4681 return nullptr;
4682 // If this is a 64-bit load, but the spill slot is 32, then we can do
4683 // a 32-bit load which is implicitly zero-extended. This likely is
4684 // due to live interval analysis remat'ing a load from stack slot.
4685 if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
4686 return nullptr;
4687 Opcode = X86::MOV32rm;
4688 NarrowToMOV32rm = true;
4689 }
4690 }
4691
4692 if (isTwoAddrFold)
4693 NewMI = FuseTwoAddrInst(MF, Opcode, MOs, InsertPt, MI, *this);
4694 else
4695 NewMI = FuseInst(MF, Opcode, OpNum, MOs, InsertPt, MI, *this);
4696
4697 if (NarrowToMOV32rm) {
4698 // If this is the special case where we use a MOV32rm to load a 32-bit
4699 // value and zero-extend the top bits. Change the destination register
4700 // to a 32-bit one.
4701 unsigned DstReg = NewMI->getOperand(0).getReg();
4702 if (TargetRegisterInfo::isPhysicalRegister(DstReg))
4703 NewMI->getOperand(0).setReg(RI.getSubReg(DstReg, X86::sub_32bit));
4704 else
4705 NewMI->getOperand(0).setSubReg(X86::sub_32bit);
4706 }
4707 return NewMI;
4708 }
4709
4710 // If the instruction and target operand are commutable, commute the
4711 // instruction and try again.
4712 if (AllowCommute) {
4713 unsigned CommuteOpIdx1 = OpNum, CommuteOpIdx2 = CommuteAnyOperandIndex;
4714 if (findCommutedOpIndices(MI, CommuteOpIdx1, CommuteOpIdx2)) {
4715 bool HasDef = MI.getDesc().getNumDefs();
4716 unsigned Reg0 = HasDef ? MI.getOperand(0).getReg() : 0;
4717 unsigned Reg1 = MI.getOperand(CommuteOpIdx1).getReg();
4718 unsigned Reg2 = MI.getOperand(CommuteOpIdx2).getReg();
4719 bool Tied1 =
4720 0 == MI.getDesc().getOperandConstraint(CommuteOpIdx1, MCOI::TIED_TO);
4721 bool Tied2 =
4722 0 == MI.getDesc().getOperandConstraint(CommuteOpIdx2, MCOI::TIED_TO);
4723
4724 // If either of the commutable operands are tied to the destination
4725 // then we can not commute + fold.
4726 if ((HasDef && Reg0 == Reg1 && Tied1) ||
4727 (HasDef && Reg0 == Reg2 && Tied2))
4728 return nullptr;
4729
4730 MachineInstr *CommutedMI =
4731 commuteInstruction(MI, false, CommuteOpIdx1, CommuteOpIdx2);
4732 if (!CommutedMI) {
4733 // Unable to commute.
4734 return nullptr;
4735 }
4736 if (CommutedMI != &MI) {
4737 // New instruction. We can't fold from this.
4738 CommutedMI->eraseFromParent();
4739 return nullptr;
4740 }
4741
4742 // Attempt to fold with the commuted version of the instruction.
4743 NewMI = foldMemoryOperandImpl(MF, MI, CommuteOpIdx2, MOs, InsertPt,
4744 Size, Align, /*AllowCommute=*/false);
4745 if (NewMI)
4746 return NewMI;
4747
4748 // Folding failed again - undo the commute before returning.
4749 MachineInstr *UncommutedMI =
4750 commuteInstruction(MI, false, CommuteOpIdx1, CommuteOpIdx2);
4751 if (!UncommutedMI) {
4752 // Unable to commute.
4753 return nullptr;
4754 }
4755 if (UncommutedMI != &MI) {
4756 // New instruction. It doesn't need to be kept.
4757 UncommutedMI->eraseFromParent();
4758 return nullptr;
4759 }
4760
4761 // Return here to prevent duplicate fuse failure report.
4762 return nullptr;
4763 }
4764 }
4765
4766 // No fusion
4767 if (PrintFailedFusing && !MI.isCopy())
4768 dbgs() << "We failed to fuse operand " << OpNum << " in " << MI;
4769 return nullptr;
4770}
4771
4772MachineInstr *
4773X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
4774 ArrayRef<unsigned> Ops,
4775 MachineBasicBlock::iterator InsertPt,
4776 int FrameIndex, LiveIntervals *LIS) const {
4777 // Check switch flag
4778 if (NoFusing)
4779 return nullptr;
4780
4781 // Avoid partial and undef register update stalls unless optimizing for size.
4782 if (!MF.getFunction().hasOptSize() &&
4783 (hasPartialRegUpdate(MI.getOpcode(), Subtarget, /*ForLoadFold*/true) ||
4784 shouldPreventUndefRegUpdateMemFold(MF, MI)))
4785 return nullptr;
4786
4787 // Don't fold subreg spills, or reloads that use a high subreg.
4788 for (auto Op : Ops) {
4789 MachineOperand &MO = MI.getOperand(Op);
4790 auto SubReg = MO.getSubReg();
4791 if (SubReg && (MO.isDef() || SubReg == X86::sub_8bit_hi))
4792 return nullptr;
4793 }
4794
4795 const MachineFrameInfo &MFI = MF.getFrameInfo();
4796 unsigned Size = MFI.getObjectSize(FrameIndex);
4797 unsigned Alignment = MFI.getObjectAlignment(FrameIndex);
4798 // If the function stack isn't realigned we don't want to fold instructions
4799 // that need increased alignment.
4800 if (!RI.needsStackRealignment(MF))
4801 Alignment =
4802 std::min(Alignment, Subtarget.getFrameLowering()->getStackAlignment());
4803 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
4804 unsigned NewOpc = 0;
4805 unsigned RCSize = 0;
4806 switch (MI.getOpcode()) {
4807 default: return nullptr;
4808 case X86::TEST8rr: NewOpc = X86::CMP8ri; RCSize = 1; break;
4809 case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break;
4810 case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break;
4811 case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break;
4812 }
4813 // Check if it's safe to fold the load. If the size of the object is
4814 // narrower than the load width, then it's not.
4815 if (Size < RCSize)
4816 return nullptr;
4817 // Change to CMPXXri r, 0 first.
4818 MI.setDesc(get(NewOpc));
4819 MI.getOperand(1).ChangeToImmediate(0);
4820 } else if (Ops.size() != 1)
4821 return nullptr;
4822
4823 return foldMemoryOperandImpl(MF, MI, Ops[0],
4824 MachineOperand::CreateFI(FrameIndex), InsertPt,
4825 Size, Alignment, /*AllowCommute=*/true);
4826}
4827
4828/// Check if \p LoadMI is a partial register load that we can't fold into \p MI
4829/// because the latter uses contents that wouldn't be defined in the folded
4830/// version. For instance, this transformation isn't legal:
4831/// movss (%rdi), %xmm0
4832/// addps %xmm0, %xmm0
4833/// ->
4834/// addps (%rdi), %xmm0
4835///
4836/// But this one is:
4837/// movss (%rdi), %xmm0
4838/// addss %xmm0, %xmm0
4839/// ->
4840/// addss (%rdi), %xmm0
4841///
4842static bool isNonFoldablePartialRegisterLoad(const MachineInstr &LoadMI,
4843 const MachineInstr &UserMI,
4844 const MachineFunction &MF) {
4845 unsigned Opc = LoadMI.getOpcode();
4846 unsigned UserOpc = UserMI.getOpcode();
4847 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
4848 const TargetRegisterClass *RC =
4849 MF.getRegInfo().getRegClass(LoadMI.getOperand(0).getReg());
4850 unsigned RegSize = TRI.getRegSizeInBits(*RC);
4851
4852 if ((Opc == X86::MOVSSrm || Opc == X86::VMOVSSrm || Opc == X86::VMOVSSZrm) &&
4853 RegSize > 32) {
4854 // These instructions only load 32 bits, we can't fold them if the
4855 // destination register is wider than 32 bits (4 bytes), and its user
4856 // instruction isn't scalar (SS).
4857 switch (UserOpc) {
4858 case X86::ADDSSrr_Int: case X86::VADDSSrr_Int: case X86::VADDSSZrr_Int:
4859 case X86::CMPSSrr_Int: case X86::VCMPSSrr_Int: case X86::VCMPSSZrr_Int:
4860 case X86::DIVSSrr_Int: case X86::VDIVSSrr_Int: case X86::VDIVSSZrr_Int:
4861 case X86::MAXSSrr_Int: case X86::VMAXSSrr_Int: case X86::VMAXSSZrr_Int:
4862 case X86::MINSSrr_Int: case X86::VMINSSrr_Int: case X86::VMINSSZrr_Int:
4863 case X86::MULSSrr_Int: case X86::VMULSSrr_Int: case X86::VMULSSZrr_Int:
4864 case X86::SUBSSrr_Int: case X86::VSUBSSrr_Int: case X86::VSUBSSZrr_Int:
4865 case X86::VADDSSZrr_Intk: case X86::VADDSSZrr_Intkz:
4866 case X86::VDIVSSZrr_Intk: case X86::VDIVSSZrr_Intkz:
4867 case X86::VMAXSSZrr_Intk: case X86::VMAXSSZrr_Intkz:
4868 case X86::VMINSSZrr_Intk: case X86::VMINSSZrr_Intkz:
4869 case X86::VMULSSZrr_Intk: case X86::VMULSSZrr_Intkz:
4870 case X86::VSUBSSZrr_Intk: case X86::VSUBSSZrr_Intkz:
4871 case X86::VFMADDSS4rr_Int: case X86::VFNMADDSS4rr_Int:
4872 case X86::VFMSUBSS4rr_Int: case X86::VFNMSUBSS4rr_Int:
4873 case X86::VFMADD132SSr_Int: case X86::VFNMADD132SSr_Int:
4874 case X86::VFMADD213SSr_Int: case X86::VFNMADD213SSr_Int:
4875 case X86::VFMADD231SSr_Int: case X86::VFNMADD231SSr_Int:
4876 case X86::VFMSUB132SSr_Int: case X86::VFNMSUB132SSr_Int:
4877 case X86::VFMSUB213SSr_Int: case X86::VFNMSUB213SSr_Int:
4878 case X86::VFMSUB231SSr_Int: case X86::VFNMSUB231SSr_Int:
4879 case X86::VFMADD132SSZr_Int: case X86::VFNMADD132SSZr_Int:
4880 case X86::VFMADD213SSZr_Int: case X86::VFNMADD213SSZr_Int:
4881 case X86::VFMADD231SSZr_Int: case X86::VFNMADD231SSZr_Int:
4882 case X86::VFMSUB132SSZr_Int: case X86::VFNMSUB132SSZr_Int:
4883 case X86::VFMSUB213SSZr_Int: case X86::VFNMSUB213SSZr_Int:
4884 case X86::VFMSUB231SSZr_Int: case X86::VFNMSUB231SSZr_Int:
4885 case X86::VFMADD132SSZr_Intk: case X86::VFNMADD132SSZr_Intk:
4886 case X86::VFMADD213SSZr_Intk: case X86::VFNMADD213SSZr_Intk:
4887 case X86::VFMADD231SSZr_Intk: case X86::VFNMADD231SSZr_Intk:
4888 case X86::VFMSUB132SSZr_Intk: case X86::VFNMSUB132SSZr_Intk:
4889 case X86::VFMSUB213SSZr_Intk: case X86::VFNMSUB213SSZr_Intk:
4890 case X86::VFMSUB231SSZr_Intk: case X86::VFNMSUB231SSZr_Intk:
4891 case X86::VFMADD132SSZr_Intkz: case X86::VFNMADD132SSZr_Intkz:
4892 case X86::VFMADD213SSZr_Intkz: case X86::VFNMADD213SSZr_Intkz:
4893 case X86::VFMADD231SSZr_Intkz: case X86::VFNMADD231SSZr_Intkz:
4894 case X86::VFMSUB132SSZr_Intkz: case X86::VFNMSUB132SSZr_Intkz:
4895 case X86::VFMSUB213SSZr_Intkz: case X86::VFNMSUB213SSZr_Intkz:
4896 case X86::VFMSUB231SSZr_Intkz: case X86::VFNMSUB231SSZr_Intkz:
4897 return false;
4898 default:
4899 return true;
4900 }
4901 }
4902
4903 if ((Opc == X86::MOVSDrm || Opc == X86::VMOVSDrm || Opc == X86::VMOVSDZrm) &&
4904 RegSize > 64) {
4905 // These instructions only load 64 bits, we can't fold them if the
4906 // destination register is wider than 64 bits (8 bytes), and its user
4907 // instruction isn't scalar (SD).
4908 switch (UserOpc) {
4909 case X86::ADDSDrr_Int: case X86::VADDSDrr_Int: case X86::VADDSDZrr_Int:
4910 case X86::CMPSDrr_Int: case X86::VCMPSDrr_Int: case X86::VCMPSDZrr_Int:
4911 case X86::DIVSDrr_Int: case X86::VDIVSDrr_Int: case X86::VDIVSDZrr_Int:
4912 case X86::MAXSDrr_Int: case X86::VMAXSDrr_Int: case X86::VMAXSDZrr_Int:
4913 case X86::MINSDrr_Int: case X86::VMINSDrr_Int: case X86::VMINSDZrr_Int:
4914 case X86::MULSDrr_Int: case X86::VMULSDrr_Int: case X86::VMULSDZrr_Int:
4915 case X86::SUBSDrr_Int: case X86::VSUBSDrr_Int: case X86::VSUBSDZrr_Int:
4916 case X86::VADDSDZrr_Intk: case X86::VADDSDZrr_Intkz:
4917 case X86::VDIVSDZrr_Intk: case X86::VDIVSDZrr_Intkz:
4918 case X86::VMAXSDZrr_Intk: case X86::VMAXSDZrr_Intkz:
4919 case X86::VMINSDZrr_Intk: case X86::VMINSDZrr_Intkz:
4920 case X86::VMULSDZrr_Intk: case X86::VMULSDZrr_Intkz:
4921 case X86::VSUBSDZrr_Intk: case X86::VSUBSDZrr_Intkz:
4922 case X86::VFMADDSD4rr_Int: case X86::VFNMADDSD4rr_Int:
4923 case X86::VFMSUBSD4rr_Int: case X86::VFNMSUBSD4rr_Int:
4924 case X86::VFMADD132SDr_Int: case X86::VFNMADD132SDr_Int:
4925 case X86::VFMADD213SDr_Int: case X86::VFNMADD213SDr_Int:
4926 case X86::VFMADD231SDr_Int: case X86::VFNMADD231SDr_Int:
4927 case X86::VFMSUB132SDr_Int: case X86::VFNMSUB132SDr_Int:
4928 case X86::VFMSUB213SDr_Int: case X86::VFNMSUB213SDr_Int:
4929 case X86::VFMSUB231SDr_Int: case X86::VFNMSUB231SDr_Int:
4930 case X86::VFMADD132SDZr_Int: case X86::VFNMADD132SDZr_Int:
4931 case X86::VFMADD213SDZr_Int: case X86::VFNMADD213SDZr_Int:
4932 case X86::VFMADD231SDZr_Int: case X86::VFNMADD231SDZr_Int:
4933 case X86::VFMSUB132SDZr_Int: case X86::VFNMSUB132SDZr_Int:
4934 case X86::VFMSUB213SDZr_Int: case X86::VFNMSUB213SDZr_Int:
4935 case X86::VFMSUB231SDZr_Int: case X86::VFNMSUB231SDZr_Int:
4936 case X86::VFMADD132SDZr_Intk: case X86::VFNMADD132SDZr_Intk:
4937 case X86::VFMADD213SDZr_Intk: case X86::VFNMADD213SDZr_Intk:
4938 case X86::VFMADD231SDZr_Intk: case X86::VFNMADD231SDZr_Intk:
4939 case X86::VFMSUB132SDZr_Intk: case X86::VFNMSUB132SDZr_Intk:
4940 case X86::VFMSUB213SDZr_Intk: case X86::VFNMSUB213SDZr_Intk:
4941 case X86::VFMSUB231SDZr_Intk: case X86::VFNMSUB231SDZr_Intk:
4942 case X86::VFMADD132SDZr_Intkz: case X86::VFNMADD132SDZr_Intkz:
4943 case X86::VFMADD213SDZr_Intkz: case X86::VFNMADD213SDZr_Intkz:
4944 case X86::VFMADD231SDZr_Intkz: case X86::VFNMADD231SDZr_Intkz:
4945 case X86::VFMSUB132SDZr_Intkz: case X86::VFNMSUB132SDZr_Intkz:
4946 case X86::VFMSUB213SDZr_Intkz: case X86::VFNMSUB213SDZr_Intkz:
4947 case X86::VFMSUB231SDZr_Intkz: case X86::VFNMSUB231SDZr_Intkz:
4948 return false;
4949 default:
4950 return true;
4951 }
4952 }
4953
4954 return false;
4955}
4956
4957MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
4958 MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops,
4959 MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
4960 LiveIntervals *LIS) const {
4961
4962 // TODO: Support the case where LoadMI loads a wide register, but MI
4963 // only uses a subreg.
4964 for (auto Op : Ops) {
4965 if (MI.getOperand(Op).getSubReg())
4966 return nullptr;
4967 }
4968
4969 // If loading from a FrameIndex, fold directly from the FrameIndex.
4970 unsigned NumOps = LoadMI.getDesc().getNumOperands();
4971 int FrameIndex;
4972 if (isLoadFromStackSlot(LoadMI, FrameIndex)) {
4973 if (isNonFoldablePartialRegisterLoad(LoadMI, MI, MF))
4974 return nullptr;
4975 return foldMemoryOperandImpl(MF, MI, Ops, InsertPt, FrameIndex, LIS);
4976 }
4977
4978 // Check switch flag
4979 if (NoFusing) return nullptr;
4980
4981 // Avoid partial and undef register update stalls unless optimizing for size.
4982 if (!MF.getFunction().hasOptSize() &&
4983 (hasPartialRegUpdate(MI.getOpcode(), Subtarget, /*ForLoadFold*/true) ||
4984 shouldPreventUndefRegUpdateMemFold(MF, MI)))
4985 return nullptr;
4986
4987 // Determine the alignment of the load.
4988 unsigned Alignment = 0;
4989 if (LoadMI.hasOneMemOperand())
4990 Alignment = (*LoadMI.memoperands_begin())->getAlignment();
4991 else
4992 switch (LoadMI.getOpcode()) {
4993 case X86::AVX512_512_SET0:
4994 case X86::AVX512_512_SETALLONES:
4995 Alignment = 64;
4996 break;
4997 case X86::AVX2_SETALLONES:
4998 case X86::AVX1_SETALLONES:
4999 case X86::AVX_SET0:
5000 case X86::AVX512_256_SET0:
5001 Alignment = 32;
5002 break;
5003 case X86::V_SET0:
5004 case X86::V_SETALLONES:
5005 case X86::AVX512_128_SET0:
5006 Alignment = 16;
5007 break;
5008 case X86::MMX_SET0:
5009 case X86::FsFLD0SD:
5010 case X86::AVX512_FsFLD0SD:
5011 Alignment = 8;
5012 break;
5013 case X86::FsFLD0SS:
5014 case X86::AVX512_FsFLD0SS:
5015 Alignment = 4;
5016 break;
5017 default:
5018 return nullptr;
5019 }
5020 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
5021 unsigned NewOpc = 0;
5022 switch (MI.getOpcode()) {
5023 default: return nullptr;
5024 case X86::TEST8rr: NewOpc = X86::CMP8ri; break;
5025 case X86::TEST16rr: NewOpc = X86::CMP16ri8; break;
5026 case X86::TEST32rr: NewOpc = X86::CMP32ri8; break;
5027 case X86::TEST64rr: NewOpc = X86::CMP64ri8; break;
5028 }
5029 // Change to CMPXXri r, 0 first.
5030 MI.setDesc(get(NewOpc));
5031 MI.getOperand(1).ChangeToImmediate(0);
5032 } else if (Ops.size() != 1)
5033 return nullptr;
5034
5035 // Make sure the subregisters match.
5036 // Otherwise we risk changing the size of the load.
5037 if (LoadMI.getOperand(0).getSubReg() != MI.getOperand(Ops[0]).getSubReg())
5038 return nullptr;
5039
5040 SmallVector<MachineOperand,X86::AddrNumOperands> MOs;
5041 switch (LoadMI.getOpcode()) {
5042 case X86::MMX_SET0:
5043 case X86::V_SET0:
5044 case X86::V_SETALLONES:
5045 case X86::AVX2_SETALLONES:
5046 case X86::AVX1_SETALLONES:
5047 case X86::AVX_SET0:
5048 case X86::AVX512_128_SET0:
5049 case X86::AVX512_256_SET0:
5050 case X86::AVX512_512_SET0:
5051 case X86::AVX512_512_SETALLONES:
5052 case X86::FsFLD0SD:
5053 case X86::AVX512_FsFLD0SD:
5054 case X86::FsFLD0SS:
5055 case X86::AVX512_FsFLD0SS: {
5056 // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
5057 // Create a constant-pool entry and operands to load from it.
5058
5059 // Medium and large mode can't fold loads this way.
5060 if (MF.getTarget().getCodeModel() != CodeModel::Small &&
5061 MF.getTarget().getCodeModel() != CodeModel::Kernel)
5062 return nullptr;
5063
5064 // x86-32 PIC requires a PIC base register for constant pools.
5065 unsigned PICBase = 0;
5066 if (MF.getTarget().isPositionIndependent()) {
5067 if (Subtarget.is64Bit())
5068 PICBase = X86::RIP;
5069 else
5070 // FIXME: PICBase = getGlobalBaseReg(&MF);
5071 // This doesn't work for several reasons.
5072 // 1. GlobalBaseReg may have been spilled.
5073 // 2. It may not be live at MI.
5074 return nullptr;
5075 }
5076
5077 // Create a constant-pool entry.
5078 MachineConstantPool &MCP = *MF.getConstantPool();
5079 Type *Ty;
5080 unsigned Opc = LoadMI.getOpcode();
5081 if (Opc == X86::FsFLD0SS || Opc == X86::AVX512_FsFLD0SS)
5082 Ty = Type::getFloatTy(MF.getFunction().getContext());
5083 else if (Opc == X86::FsFLD0SD || Opc == X86::AVX512_FsFLD0SD)
5084 Ty = Type::getDoubleTy(MF.getFunction().getContext());
5085 else if (Opc == X86::AVX512_512_SET0 || Opc == X86::AVX512_512_SETALLONES)
5086 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction().getContext()),16);
5087 else if (Opc == X86::AVX2_SETALLONES || Opc == X86::AVX_SET0 ||
5088 Opc == X86::AVX512_256_SET0 || Opc == X86::AVX1_SETALLONES)
5089 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction().getContext()), 8);
5090 else if (Opc == X86::MMX_SET0)
5091 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction().getContext()), 2);
5092 else
5093 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction().getContext()), 4);
5094
5095 bool IsAllOnes = (Opc == X86::V_SETALLONES || Opc == X86::AVX2_SETALLONES ||
5096 Opc == X86::AVX512_512_SETALLONES ||
5097 Opc == X86::AVX1_SETALLONES);
5098 const Constant *C = IsAllOnes ? Constant::getAllOnesValue(Ty) :
5099 Constant::getNullValue(Ty);
5100 unsigned CPI = MCP.getConstantPoolIndex(C, Alignment);
5101
5102 // Create operands to load from the constant pool entry.
5103 MOs.push_back(MachineOperand::CreateReg(PICBase, false));
5104 MOs.push_back(MachineOperand::CreateImm(1));
5105 MOs.push_back(MachineOperand::CreateReg(0, false));
5106 MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
5107 MOs.push_back(MachineOperand::CreateReg(0, false));
5108 break;
5109 }
5110 default: {
5111 if (isNonFoldablePartialRegisterLoad(LoadMI, MI, MF))
5112 return nullptr;
5113
5114 // Folding a normal load. Just copy the load's address operands.
5115 MOs.append(LoadMI.operands_begin() + NumOps - X86::AddrNumOperands,
5116 LoadMI.operands_begin() + NumOps);
5117 break;
5118 }
5119 }
5120 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, InsertPt,
5121 /*Size=*/0, Alignment, /*AllowCommute=*/true);
5122}
5123
5124static SmallVector<MachineMemOperand *, 2>
5125extractLoadMMOs(ArrayRef<MachineMemOperand *> MMOs, MachineFunction &MF) {
5126 SmallVector<MachineMemOperand *, 2> LoadMMOs;
5127
5128 for (MachineMemOperand *MMO : MMOs) {
5129 if (!MMO->isLoad())
5130 continue;
5131
5132 if (!MMO->isStore()) {
5133 // Reuse the MMO.
5134 LoadMMOs.push_back(MMO);
5135 } else {
5136 // Clone the MMO and unset the store flag.
5137 LoadMMOs.push_back(MF.getMachineMemOperand(
5138 MMO->getPointerInfo(), MMO->getFlags() & ~MachineMemOperand::MOStore,
5139 MMO->getSize(), MMO->getBaseAlignment(), MMO->getAAInfo(), nullptr,
5140 MMO->getSyncScopeID(), MMO->getOrdering(),
5141 MMO->getFailureOrdering()));
5142 }
5143 }
5144
5145 return LoadMMOs;
5146}
5147
5148static SmallVector<MachineMemOperand *, 2>
5149extractStoreMMOs(ArrayRef<MachineMemOperand *> MMOs, MachineFunction &MF) {
5150 SmallVector<MachineMemOperand *, 2> StoreMMOs;
5151
5152 for (MachineMemOperand *MMO : MMOs) {
5153 if (!MMO->isStore())
5154 continue;
5155
5156 if (!MMO->isLoad()) {
5157 // Reuse the MMO.
5158 StoreMMOs.push_back(MMO);
5159 } else {
5160 // Clone the MMO and unset the load flag.
5161 StoreMMOs.push_back(MF.getMachineMemOperand(
5162 MMO->getPointerInfo(), MMO->getFlags() & ~MachineMemOperand::MOLoad,
5163 MMO->getSize(), MMO->getBaseAlignment(), MMO->getAAInfo(), nullptr,
5164 MMO->getSyncScopeID(), MMO->getOrdering(),
5165 MMO->getFailureOrdering()));
5166 }
5167 }
5168
5169 return StoreMMOs;
5170}
5171
5172bool X86InstrInfo::unfoldMemoryOperand(
5173 MachineFunction &MF, MachineInstr &MI, unsigned Reg, bool UnfoldLoad,
5174 bool UnfoldStore, SmallVectorImpl<MachineInstr *> &NewMIs) const {
5175 const X86MemoryFoldTableEntry *I = lookupUnfoldTable(MI.getOpcode());
5176 if (I == nullptr)
5177 return false;
5178 unsigned Opc = I->DstOp;
5179 unsigned Index = I->Flags & TB_INDEX_MASK;
5180 bool FoldedLoad = I->Flags & TB_FOLDED_LOAD;
5181 bool FoldedStore = I->Flags & TB_FOLDED_STORE;
5182 if (UnfoldLoad && !FoldedLoad)
5183 return false;
5184 UnfoldLoad &= FoldedLoad;
5185 if (UnfoldStore && !FoldedStore)
5186 return false;
5187 UnfoldStore &= FoldedStore;
5188
5189 const MCInstrDesc &MCID = get(Opc);
5190 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
5191 // TODO: Check if 32-byte or greater accesses are slow too?
5192 if (!MI.hasOneMemOperand() && RC == &X86::VR128RegClass &&
5193 Subtarget.isUnalignedMem16Slow())
5194 // Without memoperands, loadRegFromAddr and storeRegToStackSlot will
5195 // conservatively assume the address is unaligned. That's bad for
5196 // performance.
5197 return false;
5198 SmallVector<MachineOperand, X86::AddrNumOperands> AddrOps;
5199 SmallVector<MachineOperand,2> BeforeOps;
5200 SmallVector<MachineOperand,2> AfterOps;
5201 SmallVector<MachineOperand,4> ImpOps;
5202 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
5203 MachineOperand &Op = MI.getOperand(i);
5204 if (i >= Index && i < Index + X86::AddrNumOperands)
5205 AddrOps.push_back(Op);
5206 else if (Op.isReg() && Op.isImplicit())
5207 ImpOps.push_back(Op);
5208 else if (i < Index)
5209 BeforeOps.push_back(Op);
5210 else if (i > Index)
5211 AfterOps.push_back(Op);
5212 }
5213
5214 // Emit the load instruction.
5215 if (UnfoldLoad) {
5216 auto MMOs = extractLoadMMOs(MI.memoperands(), MF);
5217 loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs, NewMIs);
5218 if (UnfoldStore) {
5219 // Address operands cannot be marked isKill.
5220 for (unsigned i = 1; i != 1 + X86::AddrNumOperands; ++i) {
5221 MachineOperand &MO = NewMIs[0]->getOperand(i);
5222 if (MO.isReg())
5223 MO.setIsKill(false);
5224 }
5225 }
5226 }
5227
5228 // Emit the data processing instruction.
5229 MachineInstr *DataMI = MF.CreateMachineInstr(MCID, MI.getDebugLoc(), true);
5230 MachineInstrBuilder MIB(MF, DataMI);
5231
5232 if (FoldedStore)
5233 MIB.addReg(Reg, RegState::Define);
5234 for (MachineOperand &BeforeOp : BeforeOps)
5235 MIB.add(BeforeOp);
5236 if (FoldedLoad)
5237 MIB.addReg(Reg);
5238 for (MachineOperand &AfterOp : AfterOps)
5239 MIB.add(AfterOp);
5240 for (MachineOperand &ImpOp : ImpOps) {
5241 MIB.addReg(ImpOp.getReg(),
5242 getDefRegState(ImpOp.isDef()) |
5243 RegState::Implicit |
5244 getKillRegState(ImpOp.isKill()) |
5245 getDeadRegState(ImpOp.isDead()) |
5246 getUndefRegState(ImpOp.isUndef()));
5247 }
5248 // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
5249 switch (DataMI->getOpcode()) {
5250 default: break;
5251 case X86::CMP64ri32:
5252 case X86::CMP64ri8:
5253 case X86::CMP32ri:
5254 case X86::CMP32ri8:
5255 case X86::CMP16ri:
5256 case X86::CMP16ri8:
5257 case X86::CMP8ri: {
5258 MachineOperand &MO0 = DataMI->getOperand(0);
5259 MachineOperand &MO1 = DataMI->getOperand(1);
5260 if (MO1.getImm() == 0) {
5261 unsigned NewOpc;
5262 switch (DataMI->getOpcode()) {
5263 default: llvm_unreachable("Unreachable!")::llvm::llvm_unreachable_internal("Unreachable!", "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 5263);
5264 case X86::CMP64ri8:
5265 case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
5266 case X86::CMP32ri8:
5267 case X86::CMP32ri: NewOpc = X86::TEST32rr; break;
5268 case X86::CMP16ri8:
5269 case X86::CMP16ri: NewOpc = X86::TEST16rr; break;
5270 case X86::CMP8ri: NewOpc = X86::TEST8rr; break;
5271 }
5272 DataMI->setDesc(get(NewOpc));
5273 MO1.ChangeToRegister(MO0.getReg(), false);
5274 }
5275 }
5276 }
5277 NewMIs.push_back(DataMI);
5278
5279 // Emit the store instruction.
5280 if (UnfoldStore) {
5281 const TargetRegisterClass *DstRC = getRegClass(MCID, 0, &RI, MF);
5282 auto MMOs = extractStoreMMOs(MI.memoperands(), MF);
5283 storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs, NewMIs);
5284 }
5285
5286 return true;
5287}
5288
5289bool
5290X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
5291 SmallVectorImpl<SDNode*> &NewNodes) const {
5292 if (!N->isMachineOpcode())
5293 return false;
5294
5295 const X86MemoryFoldTableEntry *I = lookupUnfoldTable(N->getMachineOpcode());
5296 if (I == nullptr)
5297 return false;
5298 unsigned Opc = I->DstOp;
5299 unsigned Index = I->Flags & TB_INDEX_MASK;
5300 bool FoldedLoad = I->Flags & TB_FOLDED_LOAD;
5301 bool FoldedStore = I->Flags & TB_FOLDED_STORE;
5302 const MCInstrDesc &MCID = get(Opc);
5303 MachineFunction &MF = DAG.getMachineFunction();
5304 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
5305 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
5306 unsigned NumDefs = MCID.NumDefs;
5307 std::vector<SDValue> AddrOps;
5308 std::vector<SDValue> BeforeOps;
5309 std::vector<SDValue> AfterOps;
5310 SDLoc dl(N);
5311 unsigned NumOps = N->getNumOperands();
5312 for (unsigned i = 0; i != NumOps-1; ++i) {
5313 SDValue Op = N->getOperand(i);
5314 if (i >= Index-NumDefs && i < Index-NumDefs + X86::AddrNumOperands)
5315 AddrOps.push_back(Op);
5316 else if (i < Index-NumDefs)
5317 BeforeOps.push_back(Op);
5318 else if (i > Index-NumDefs)
5319 AfterOps.push_back(Op);
5320 }
5321 SDValue Chain = N->getOperand(NumOps-1);
5322 AddrOps.push_back(Chain);
5323
5324 // Emit the load instruction.
5325 SDNode *Load = nullptr;
5326 if (FoldedLoad) {
5327 EVT VT = *TRI.legalclasstypes_begin(*RC);
5328 auto MMOs = extractLoadMMOs(cast<MachineSDNode>(N)->memoperands(), MF);
5329 if (MMOs.empty() && RC == &X86::VR128RegClass &&
5330 Subtarget.isUnalignedMem16Slow())
5331 // Do not introduce a slow unaligned load.
5332 return false;
5333 // FIXME: If a VR128 can have size 32, we should be checking if a 32-byte
5334 // memory access is slow above.
5335 unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*RC), 16);
5336 bool isAligned = !MMOs.empty() && MMOs.front()->getAlignment() >= Alignment;
5337 Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, Subtarget), dl,
5338 VT, MVT::Other, AddrOps);
5339 NewNodes.push_back(Load);
5340
5341 // Preserve memory reference information.
5342 DAG.setNodeMemRefs(cast<MachineSDNode>(Load), MMOs);
5343 }
5344
5345 // Emit the data processing instruction.
5346 std::vector<EVT> VTs;
5347 const TargetRegisterClass *DstRC = nullptr;
5348 if (MCID.getNumDefs() > 0) {
5349 DstRC = getRegClass(MCID, 0, &RI, MF);
5350 VTs.push_back(*TRI.legalclasstypes_begin(*DstRC));
5351 }
5352 for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
5353 EVT VT = N->getValueType(i);
5354 if (VT != MVT::Other && i >= (unsigned)MCID.getNumDefs())
5355 VTs.push_back(VT);
5356 }
5357 if (Load)
5358 BeforeOps.push_back(SDValue(Load, 0));
5359 BeforeOps.insert(BeforeOps.end(), AfterOps.begin(), AfterOps.end());
5360 // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
5361 switch (Opc) {
5362 default: break;
5363 case X86::CMP64ri32:
5364 case X86::CMP64ri8:
5365 case X86::CMP32ri:
5366 case X86::CMP32ri8:
5367 case X86::CMP16ri:
5368 case X86::CMP16ri8:
5369 case X86::CMP8ri:
5370 if (isNullConstant(BeforeOps[1])) {
5371 switch (Opc) {
5372 default: llvm_unreachable("Unreachable!")::llvm::llvm_unreachable_internal("Unreachable!", "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 5372);
5373 case X86::CMP64ri8:
5374 case X86::CMP64ri32: Opc = X86::TEST64rr; break;
5375 case X86::CMP32ri8:
5376 case X86::CMP32ri: Opc = X86::TEST32rr; break;
5377 case X86::CMP16ri8:
5378 case X86::CMP16ri: Opc = X86::TEST16rr; break;
5379 case X86::CMP8ri: Opc = X86::TEST8rr; break;
5380 }
5381 BeforeOps[1] = BeforeOps[0];
5382 }
5383 }
5384 SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, BeforeOps);
5385 NewNodes.push_back(NewNode);
5386
5387 // Emit the store instruction.
5388 if (FoldedStore) {
5389 AddrOps.pop_back();
5390 AddrOps.push_back(SDValue(NewNode, 0));
5391 AddrOps.push_back(Chain);
5392 auto MMOs = extractStoreMMOs(cast<MachineSDNode>(N)->memoperands(), MF);
5393 if (MMOs.empty() && RC == &X86::VR128RegClass &&
5394 Subtarget.isUnalignedMem16Slow())
5395 // Do not introduce a slow unaligned store.
5396 return false;
5397 // FIXME: If a VR128 can have size 32, we should be checking if a 32-byte
5398 // memory access is slow above.
5399 unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*RC), 16);
5400 bool isAligned = !MMOs.empty() && MMOs.front()->getAlignment() >= Alignment;
5401 SDNode *Store =
5402 DAG.getMachineNode(getStoreRegOpcode(0, DstRC, isAligned, Subtarget),
5403 dl, MVT::Other, AddrOps);
5404 NewNodes.push_back(Store);
5405
5406 // Preserve memory reference information.
5407 DAG.setNodeMemRefs(cast<MachineSDNode>(Store), MMOs);
5408 }
5409
5410 return true;
5411}
5412
5413unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
5414 bool UnfoldLoad, bool UnfoldStore,
5415 unsigned *LoadRegIndex) const {
5416 const X86MemoryFoldTableEntry *I = lookupUnfoldTable(Opc);
5417 if (I == nullptr)
5418 return 0;
5419 bool FoldedLoad = I->Flags & TB_FOLDED_LOAD;
5420 bool FoldedStore = I->Flags & TB_FOLDED_STORE;
5421 if (UnfoldLoad && !FoldedLoad)
5422 return 0;
5423 if (UnfoldStore && !FoldedStore)
5424 return 0;
5425 if (LoadRegIndex)
5426 *LoadRegIndex = I->Flags & TB_INDEX_MASK;
5427 return I->DstOp;
5428}
5429
5430bool
5431X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
5432 int64_t &Offset1, int64_t &Offset2) const {
5433 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
5434 return false;
5435 unsigned Opc1 = Load1->getMachineOpcode();
5436 unsigned Opc2 = Load2->getMachineOpcode();
5437 switch (Opc1) {
5438 default: return false;
5439 case X86::MOV8rm:
5440 case X86::MOV16rm:
5441 case X86::MOV32rm:
5442 case X86::MOV64rm:
5443 case X86::LD_Fp32m:
5444 case X86::LD_Fp64m:
5445 case X86::LD_Fp80m:
5446 case X86::MOVSSrm:
5447 case X86::MOVSDrm:
5448 case X86::MMX_MOVD64rm:
5449 case X86::MMX_MOVQ64rm:
5450 case X86::MOVAPSrm:
5451 case X86::MOVUPSrm:
5452 case X86::MOVAPDrm:
5453 case X86::MOVUPDrm:
5454 case X86::MOVDQArm:
5455 case X86::MOVDQUrm:
5456 // AVX load instructions
5457 case X86::VMOVSSrm:
5458 case X86::VMOVSDrm:
5459 case X86::VMOVAPSrm:
5460 case X86::VMOVUPSrm:
5461 case X86::VMOVAPDrm:
5462 case X86::VMOVUPDrm:
5463 case X86::VMOVDQArm:
5464 case X86::VMOVDQUrm:
5465 case X86::VMOVAPSYrm:
5466 case X86::VMOVUPSYrm:
5467 case X86::VMOVAPDYrm:
5468 case X86::VMOVUPDYrm:
5469 case X86::VMOVDQAYrm:
5470 case X86::VMOVDQUYrm:
5471 // AVX512 load instructions
5472 case X86::VMOVSSZrm:
5473 case X86::VMOVSDZrm:
5474 case X86::VMOVAPSZ128rm:
5475 case X86::VMOVUPSZ128rm:
5476 case X86::VMOVAPSZ128rm_NOVLX:
5477 case X86::VMOVUPSZ128rm_NOVLX:
5478 case X86::VMOVAPDZ128rm:
5479 case X86::VMOVUPDZ128rm:
5480 case X86::VMOVDQU8Z128rm:
5481 case X86::VMOVDQU16Z128rm:
5482 case X86::VMOVDQA32Z128rm:
5483 case X86::VMOVDQU32Z128rm:
5484 case X86::VMOVDQA64Z128rm:
5485 case X86::VMOVDQU64Z128rm:
5486 case X86::VMOVAPSZ256rm:
5487 case X86::VMOVUPSZ256rm:
5488 case X86::VMOVAPSZ256rm_NOVLX:
5489 case X86::VMOVUPSZ256rm_NOVLX:
5490 case X86::VMOVAPDZ256rm:
5491 case X86::VMOVUPDZ256rm:
5492 case X86::VMOVDQU8Z256rm:
5493 case X86::VMOVDQU16Z256rm:
5494 case X86::VMOVDQA32Z256rm:
5495 case X86::VMOVDQU32Z256rm:
5496 case X86::VMOVDQA64Z256rm:
5497 case X86::VMOVDQU64Z256rm:
5498 case X86::VMOVAPSZrm:
5499 case X86::VMOVUPSZrm:
5500 case X86::VMOVAPDZrm:
5501 case X86::VMOVUPDZrm:
5502 case X86::VMOVDQU8Zrm:
5503 case X86::VMOVDQU16Zrm:
5504 case X86::VMOVDQA32Zrm:
5505 case X86::VMOVDQU32Zrm:
5506 case X86::VMOVDQA64Zrm:
5507 case X86::VMOVDQU64Zrm:
5508 case X86::KMOVBkm:
5509 case X86::KMOVWkm:
5510 case X86::KMOVDkm:
5511 case X86::KMOVQkm:
5512 break;
5513 }
5514 switch (Opc2) {
5515 default: return false;
5516 case X86::MOV8rm:
5517 case X86::MOV16rm:
5518 case X86::MOV32rm:
5519 case X86::MOV64rm:
5520 case X86::LD_Fp32m:
5521 case X86::LD_Fp64m:
5522 case X86::LD_Fp80m:
5523 case X86::MOVSSrm:
5524 case X86::MOVSDrm:
5525 case X86::MMX_MOVD64rm:
5526 case X86::MMX_MOVQ64rm:
5527 case X86::MOVAPSrm:
5528 case X86::MOVUPSrm:
5529 case X86::MOVAPDrm:
5530 case X86::MOVUPDrm:
5531 case X86::MOVDQArm:
5532 case X86::MOVDQUrm:
5533 // AVX load instructions
5534 case X86::VMOVSSrm:
5535 case X86::VMOVSDrm:
5536 case X86::VMOVAPSrm:
5537 case X86::VMOVUPSrm:
5538 case X86::VMOVAPDrm:
5539 case X86::VMOVUPDrm:
5540 case X86::VMOVDQArm:
5541 case X86::VMOVDQUrm:
5542 case X86::VMOVAPSYrm:
5543 case X86::VMOVUPSYrm:
5544 case X86::VMOVAPDYrm:
5545 case X86::VMOVUPDYrm:
5546 case X86::VMOVDQAYrm:
5547 case X86::VMOVDQUYrm:
5548 // AVX512 load instructions
5549 case X86::VMOVSSZrm:
5550 case X86::VMOVSDZrm:
5551 case X86::VMOVAPSZ128rm:
5552 case X86::VMOVUPSZ128rm:
5553 case X86::VMOVAPSZ128rm_NOVLX:
5554 case X86::VMOVUPSZ128rm_NOVLX:
5555 case X86::VMOVAPDZ128rm:
5556 case X86::VMOVUPDZ128rm:
5557 case X86::VMOVDQU8Z128rm:
5558 case X86::VMOVDQU16Z128rm:
5559 case X86::VMOVDQA32Z128rm:
5560 case X86::VMOVDQU32Z128rm:
5561 case X86::VMOVDQA64Z128rm:
5562 case X86::VMOVDQU64Z128rm:
5563 case X86::VMOVAPSZ256rm:
5564 case X86::VMOVUPSZ256rm:
5565 case X86::VMOVAPSZ256rm_NOVLX:
5566 case X86::VMOVUPSZ256rm_NOVLX:
5567 case X86::VMOVAPDZ256rm:
5568 case X86::VMOVUPDZ256rm:
5569 case X86::VMOVDQU8Z256rm:
5570 case X86::VMOVDQU16Z256rm:
5571 case X86::VMOVDQA32Z256rm:
5572 case X86::VMOVDQU32Z256rm:
5573 case X86::VMOVDQA64Z256rm:
5574 case X86::VMOVDQU64Z256rm:
5575 case X86::VMOVAPSZrm:
5576 case X86::VMOVUPSZrm:
5577 case X86::VMOVAPDZrm:
5578 case X86::VMOVUPDZrm:
5579 case X86::VMOVDQU8Zrm:
5580 case X86::VMOVDQU16Zrm:
5581 case X86::VMOVDQA32Zrm:
5582 case X86::VMOVDQU32Zrm:
5583 case X86::VMOVDQA64Zrm:
5584 case X86::VMOVDQU64Zrm:
5585 case X86::KMOVBkm:
5586 case X86::KMOVWkm:
5587 case X86::KMOVDkm:
5588 case X86::KMOVQkm:
5589 break;
5590 }
5591
5592 // Lambda to check if both the loads have the same value for an operand index.
5593 auto HasSameOp = [&](int I) {
5594 return Load1->getOperand(I) == Load2->getOperand(I);
5595 };
5596
5597 // All operands except the displacement should match.
5598 if (!HasSameOp(X86::AddrBaseReg) || !HasSameOp(X86::AddrScaleAmt) ||
5599 !HasSameOp(X86::AddrIndexReg) || !HasSameOp(X86::AddrSegmentReg))
5600 return false;
5601
5602 // Chain Operand must be the same.
5603 if (!HasSameOp(5))
5604 return false;
5605
5606 // Now let's examine if the displacements are constants.
5607 auto Disp1 = dyn_cast<ConstantSDNode>(Load1->getOperand(X86::AddrDisp));
5608 auto Disp2 = dyn_cast<ConstantSDNode>(Load2->getOperand(X86::AddrDisp));
5609 if (!Disp1 || !Disp2)
5610 return false;
5611
5612 Offset1 = Disp1->getSExtValue();
5613 Offset2 = Disp2->getSExtValue();
5614 return true;
5615}
5616
5617bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
5618 int64_t Offset1, int64_t Offset2,
5619 unsigned NumLoads) const {
5620 assert(Offset2 > Offset1)((Offset2 > Offset1) ? static_cast<void> (0) : __assert_fail
("Offset2 > Offset1", "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 5620, __PRETTY_FUNCTION__));
5621 if ((Offset2 - Offset1) / 8 > 64)
5622 return false;
5623
5624 unsigned Opc1 = Load1->getMachineOpcode();
5625 unsigned Opc2 = Load2->getMachineOpcode();
5626 if (Opc1 != Opc2)
5627 return false; // FIXME: overly conservative?
5628
5629 switch (Opc1) {
5630 default: break;
5631 case X86::LD_Fp32m:
5632 case X86::LD_Fp64m:
5633 case X86::LD_Fp80m:
5634 case X86::MMX_MOVD64rm:
5635 case X86::MMX_MOVQ64rm:
5636 return false;
5637 }
5638
5639 EVT VT = Load1->getValueType(0);
5640 switch (VT.getSimpleVT().SimpleTy) {
5641 default:
5642 // XMM registers. In 64-bit mode we can be a bit more aggressive since we
5643 // have 16 of them to play with.
5644 if (Subtarget.is64Bit()) {
5645 if (NumLoads >= 3)
5646 return false;
5647 } else if (NumLoads) {
5648 return false;
5649 }
5650 break;
5651 case MVT::i8:
5652 case MVT::i16:
5653 case MVT::i32:
5654 case MVT::i64:
5655 case MVT::f32:
5656 case MVT::f64:
5657 if (NumLoads)
5658 return false;
5659 break;
5660 }
5661
5662 return true;
5663}
5664
5665bool X86InstrInfo::
5666reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
5667 assert(Cond.size() == 1 && "Invalid X86 branch condition!")((Cond.size() == 1 && "Invalid X86 branch condition!"
) ? static_cast<void> (0) : __assert_fail ("Cond.size() == 1 && \"Invalid X86 branch condition!\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 5667, __PRETTY_FUNCTION__));
5668 X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
5669 Cond[0].setImm(GetOppositeBranchCondition(CC));
5670 return false;
5671}
5672
5673bool X86InstrInfo::
5674isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
5675 // FIXME: Return false for x87 stack register classes for now. We can't
5676 // allow any loads of these registers before FpGet_ST0_80.
5677 return !(RC == &X86::CCRRegClass || RC == &X86::DFCCRRegClass ||
5678 RC == &X86::RFP32RegClass || RC == &X86::RFP64RegClass ||
5679 RC == &X86::RFP80RegClass);
5680}
5681
5682/// Return a virtual register initialized with the
5683/// the global base register value. Output instructions required to
5684/// initialize the register in the function entry block, if necessary.
5685///
5686/// TODO: Eliminate this and move the code to X86MachineFunctionInfo.
5687///
5688unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
5689 assert((!Subtarget.is64Bit() ||(((!Subtarget.is64Bit() || MF->getTarget().getCodeModel() ==
CodeModel::Medium || MF->getTarget().getCodeModel() == CodeModel
::Large) && "X86-64 PIC uses RIP relative addressing"
) ? static_cast<void> (0) : __assert_fail ("(!Subtarget.is64Bit() || MF->getTarget().getCodeModel() == CodeModel::Medium || MF->getTarget().getCodeModel() == CodeModel::Large) && \"X86-64 PIC uses RIP relative addressing\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 5692, __PRETTY_FUNCTION__))
5690 MF->getTarget().getCodeModel() == CodeModel::Medium ||(((!Subtarget.is64Bit() || MF->getTarget().getCodeModel() ==
CodeModel::Medium || MF->getTarget().getCodeModel() == CodeModel
::Large) && "X86-64 PIC uses RIP relative addressing"
) ? static_cast<void> (0) : __assert_fail ("(!Subtarget.is64Bit() || MF->getTarget().getCodeModel() == CodeModel::Medium || MF->getTarget().getCodeModel() == CodeModel::Large) && \"X86-64 PIC uses RIP relative addressing\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 5692, __PRETTY_FUNCTION__))
5691 MF->getTarget().getCodeModel() == CodeModel::Large) &&(((!Subtarget.is64Bit() || MF->getTarget().getCodeModel() ==
CodeModel::Medium || MF->getTarget().getCodeModel() == CodeModel
::Large) && "X86-64 PIC uses RIP relative addressing"
) ? static_cast<void> (0) : __assert_fail ("(!Subtarget.is64Bit() || MF->getTarget().getCodeModel() == CodeModel::Medium || MF->getTarget().getCodeModel() == CodeModel::Large) && \"X86-64 PIC uses RIP relative addressing\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 5692, __PRETTY_FUNCTION__))
5692 "X86-64 PIC uses RIP relative addressing")(((!Subtarget.is64Bit() || MF->getTarget().getCodeModel() ==
CodeModel::Medium || MF->getTarget().getCodeModel() == CodeModel
::Large) && "X86-64 PIC uses RIP relative addressing"
) ? static_cast<void> (0) : __assert_fail ("(!Subtarget.is64Bit() || MF->getTarget().getCodeModel() == CodeModel::Medium || MF->getTarget().getCodeModel() == CodeModel::Large) && \"X86-64 PIC uses RIP relative addressing\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 5692, __PRETTY_FUNCTION__));
5693
5694 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
5695 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
5696 if (GlobalBaseReg != 0)
5697 return GlobalBaseReg;
5698
5699 // Create the register. The code to initialize it is inserted
5700 // later, by the CGBR pass (below).
5701 MachineRegisterInfo &RegInfo = MF->getRegInfo();
5702 GlobalBaseReg = RegInfo.createVirtualRegister(
5703 Subtarget.is64Bit() ? &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass);
5704 X86FI->setGlobalBaseReg(GlobalBaseReg);
5705 return GlobalBaseReg;
5706}
5707
5708// These are the replaceable SSE instructions. Some of these have Int variants
5709// that we don't include here. We don't want to replace instructions selected
5710// by intrinsics.
5711static const uint16_t ReplaceableInstrs[][3] = {
5712 //PackedSingle PackedDouble PackedInt
5713 { X86::MOVAPSmr, X86::MOVAPDmr, X86::MOVDQAmr },
5714 { X86::MOVAPSrm, X86::MOVAPDrm, X86::MOVDQArm },
5715 { X86::MOVAPSrr, X86::MOVAPDrr, X86::MOVDQArr },
5716 { X86::MOVUPSmr, X86::MOVUPDmr, X86::MOVDQUmr },
5717 { X86::MOVUPSrm, X86::MOVUPDrm, X86::MOVDQUrm },
5718 { X86::MOVLPSmr, X86::MOVLPDmr, X86::MOVPQI2QImr },
5719 { X86::MOVSDmr, X86::MOVSDmr, X86::MOVPQI2QImr },
5720 { X86::MOVSSmr, X86::MOVSSmr, X86::MOVPDI2DImr },
5721 { X86::MOVSDrm, X86::MOVSDrm, X86::MOVQI2PQIrm },
5722 { X86::MOVSSrm, X86::MOVSSrm, X86::MOVDI2PDIrm },
5723 { X86::MOVNTPSmr, X86::MOVNTPDmr, X86::MOVNTDQmr },
5724 { X86::ANDNPSrm, X86::ANDNPDrm, X86::PANDNrm },
5725 { X86::ANDNPSrr, X86::ANDNPDrr, X86::PANDNrr },
5726 { X86::ANDPSrm, X86::ANDPDrm, X86::PANDrm },
5727 { X86::ANDPSrr, X86::ANDPDrr, X86::PANDrr },
5728 { X86::ORPSrm, X86::ORPDrm, X86::PORrm },
5729 { X86::ORPSrr, X86::ORPDrr, X86::PORrr },
5730 { X86::XORPSrm, X86::XORPDrm, X86::PXORrm },
5731 { X86::XORPSrr, X86::XORPDrr, X86::PXORrr },
5732 { X86::UNPCKLPDrm, X86::UNPCKLPDrm, X86::PUNPCKLQDQrm },
5733 { X86::MOVLHPSrr, X86::UNPCKLPDrr, X86::PUNPCKLQDQrr },
5734 { X86::UNPCKHPDrm, X86::UNPCKHPDrm, X86::PUNPCKHQDQrm },
5735 { X86::UNPCKHPDrr, X86::UNPCKHPDrr, X86::PUNPCKHQDQrr },
5736 { X86::UNPCKLPSrm, X86::UNPCKLPSrm, X86::PUNPCKLDQrm },
5737 { X86::UNPCKLPSrr, X86::UNPCKLPSrr, X86::PUNPCKLDQrr },
5738 { X86::UNPCKHPSrm, X86::UNPCKHPSrm, X86::PUNPCKHDQrm },
5739 { X86::UNPCKHPSrr, X86::UNPCKHPSrr, X86::PUNPCKHDQrr },
5740 { X86::EXTRACTPSmr, X86::EXTRACTPSmr, X86::PEXTRDmr },
5741 { X86::EXTRACTPSrr, X86::EXTRACTPSrr, X86::PEXTRDrr },
5742 // AVX 128-bit support
5743 { X86::VMOVAPSmr, X86::VMOVAPDmr, X86::VMOVDQAmr },
5744 { X86::VMOVAPSrm, X86::VMOVAPDrm, X86::VMOVDQArm },
5745 { X86::VMOVAPSrr, X86::VMOVAPDrr, X86::VMOVDQArr },
5746 { X86::VMOVUPSmr, X86::VMOVUPDmr, X86::VMOVDQUmr },
5747 { X86::VMOVUPSrm, X86::VMOVUPDrm, X86::VMOVDQUrm },
5748 { X86::VMOVLPSmr, X86::VMOVLPDmr, X86::VMOVPQI2QImr },
5749 { X86::VMOVSDmr, X86::VMOVSDmr, X86::VMOVPQI2QImr },
5750 { X86::VMOVSSmr, X86::VMOVSSmr, X86::VMOVPDI2DImr },
5751 { X86::VMOVSDrm, X86::VMOVSDrm, X86::VMOVQI2PQIrm },
5752 { X86::VMOVSSrm, X86::VMOVSSrm, X86::VMOVDI2PDIrm },
5753 { X86::VMOVNTPSmr, X86::VMOVNTPDmr, X86::VMOVNTDQmr },
5754 { X86::VANDNPSrm, X86::VANDNPDrm, X86::VPANDNrm },
5755 { X86::VANDNPSrr, X86::VANDNPDrr, X86::VPANDNrr },
5756 { X86::VANDPSrm, X86::VANDPDrm, X86::VPANDrm },
5757 { X86::VANDPSrr, X86::VANDPDrr, X86::VPANDrr },
5758 { X86::VORPSrm, X86::VORPDrm, X86::VPORrm },
5759 { X86::VORPSrr, X86::VORPDrr, X86::VPORrr },
5760 { X86::VXORPSrm, X86::VXORPDrm, X86::VPXORrm },
5761 { X86::VXORPSrr, X86::VXORPDrr, X86::VPXORrr },
5762 { X86::VUNPCKLPDrm, X86::VUNPCKLPDrm, X86::VPUNPCKLQDQrm },
5763 { X86::VMOVLHPSrr, X86::VUNPCKLPDrr, X86::VPUNPCKLQDQrr },
5764 { X86::VUNPCKHPDrm, X86::VUNPCKHPDrm, X86::VPUNPCKHQDQrm },
5765 { X86::VUNPCKHPDrr, X86::VUNPCKHPDrr, X86::VPUNPCKHQDQrr },
5766 { X86::VUNPCKLPSrm, X86::VUNPCKLPSrm, X86::VPUNPCKLDQrm },
5767 { X86::VUNPCKLPSrr, X86::VUNPCKLPSrr, X86::VPUNPCKLDQrr },
5768 { X86::VUNPCKHPSrm, X86::VUNPCKHPSrm, X86::VPUNPCKHDQrm },
5769 { X86::VUNPCKHPSrr, X86::VUNPCKHPSrr, X86::VPUNPCKHDQrr },
5770 { X86::VEXTRACTPSmr, X86::VEXTRACTPSmr, X86::VPEXTRDmr },
5771 { X86::VEXTRACTPSrr, X86::VEXTRACTPSrr, X86::VPEXTRDrr },
5772 // AVX 256-bit support
5773 { X86::VMOVAPSYmr, X86::VMOVAPDYmr, X86::VMOVDQAYmr },
5774 { X86::VMOVAPSYrm, X86::VMOVAPDYrm, X86::VMOVDQAYrm },
5775 { X86::VMOVAPSYrr, X86::VMOVAPDYrr, X86::VMOVDQAYrr },
5776 { X86::VMOVUPSYmr, X86::VMOVUPDYmr, X86::VMOVDQUYmr },
5777 { X86::VMOVUPSYrm, X86::VMOVUPDYrm, X86::VMOVDQUYrm },
5778 { X86::VMOVNTPSYmr, X86::VMOVNTPDYmr, X86::VMOVNTDQYmr },
5779 { X86::VPERMPSYrm, X86::VPERMPSYrm, X86::VPERMDYrm },
5780 { X86::VPERMPSYrr, X86::VPERMPSYrr, X86::VPERMDYrr },
5781 { X86::VPERMPDYmi, X86::VPERMPDYmi, X86::VPERMQYmi },
5782 { X86::VPERMPDYri, X86::VPERMPDYri, X86::VPERMQYri },
5783 // AVX512 support
5784 { X86::VMOVLPSZ128mr, X86::VMOVLPDZ128mr, X86::VMOVPQI2QIZmr },
5785 { X86::VMOVNTPSZ128mr, X86::VMOVNTPDZ128mr, X86::VMOVNTDQZ128mr },
5786 { X86::VMOVNTPSZ256mr, X86::VMOVNTPDZ256mr, X86::VMOVNTDQZ256mr },
5787 { X86::VMOVNTPSZmr, X86::VMOVNTPDZmr, X86::VMOVNTDQZmr },
5788 { X86::VMOVSDZmr, X86::VMOVSDZmr, X86::VMOVPQI2QIZmr },
5789 { X86::VMOVSSZmr, X86::VMOVSSZmr, X86::VMOVPDI2DIZmr },
5790 { X86::VMOVSDZrm, X86::VMOVSDZrm, X86::VMOVQI2PQIZrm },
5791 { X86::VMOVSSZrm, X86::VMOVSSZrm, X86::VMOVDI2PDIZrm },
5792 { X86::VBROADCASTSSZ128r, X86::VBROADCASTSSZ128r, X86::VPBROADCASTDZ128r },
5793 { X86::VBROADCASTSSZ128m, X86::VBROADCASTSSZ128m, X86::VPBROADCASTDZ128m },
5794 { X86::VBROADCASTSSZ256r, X86::VBROADCASTSSZ256r, X86::VPBROADCASTDZ256r },
5795 { X86::VBROADCASTSSZ256m, X86::VBROADCASTSSZ256m, X86::VPBROADCASTDZ256m },
5796 { X86::VBROADCASTSSZr, X86::VBROADCASTSSZr, X86::VPBROADCASTDZr },
5797 { X86::VBROADCASTSSZm, X86::VBROADCASTSSZm, X86::VPBROADCASTDZm },
5798 { X86::VMOVDDUPZ128rr, X86::VMOVDDUPZ128rr, X86::VPBROADCASTQZ128r },
5799 { X86::VMOVDDUPZ128rm, X86::VMOVDDUPZ128rm, X86::VPBROADCASTQZ128m },
5800 { X86::VBROADCASTSDZ256r, X86::VBROADCASTSDZ256r, X86::VPBROADCASTQZ256r },
5801 { X86::VBROADCASTSDZ256m, X86::VBROADCASTSDZ256m, X86::VPBROADCASTQZ256m },
5802 { X86::VBROADCASTSDZr, X86::VBROADCASTSDZr, X86::VPBROADCASTQZr },
5803 { X86::VBROADCASTSDZm, X86::VBROADCASTSDZm, X86::VPBROADCASTQZm },
5804 { X86::VINSERTF32x4Zrr, X86::VINSERTF32x4Zrr, X86::VINSERTI32x4Zrr },
5805 { X86::VINSERTF32x4Zrm, X86::VINSERTF32x4Zrm, X86::VINSERTI32x4Zrm },
5806 { X86::VINSERTF32x8Zrr, X86::VINSERTF32x8Zrr, X86::VINSERTI32x8Zrr },
5807 { X86::VINSERTF32x8Zrm, X86::VINSERTF32x8Zrm, X86::VINSERTI32x8Zrm },
5808 { X86::VINSERTF64x2Zrr, X86::VINSERTF64x2Zrr, X86::VINSERTI64x2Zrr },
5809 { X86::VINSERTF64x2Zrm, X86::VINSERTF64x2Zrm, X86::VINSERTI64x2Zrm },
5810 { X86::VINSERTF64x4Zrr, X86::VINSERTF64x4Zrr, X86::VINSERTI64x4Zrr },
5811 { X86::VINSERTF64x4Zrm, X86::VINSERTF64x4Zrm, X86::VINSERTI64x4Zrm },
5812 { X86::VINSERTF32x4Z256rr,X86::VINSERTF32x4Z256rr,X86::VINSERTI32x4Z256rr },
5813 { X86::VINSERTF32x4Z256rm,X86::VINSERTF32x4Z256rm,X86::VINSERTI32x4Z256rm },
5814 { X86::VINSERTF64x2Z256rr,X86::VINSERTF64x2Z256rr,X86::VINSERTI64x2Z256rr },
5815 { X86::VINSERTF64x2Z256rm,X86::VINSERTF64x2Z256rm,X86::VINSERTI64x2Z256rm },
5816 { X86::VEXTRACTF32x4Zrr, X86::VEXTRACTF32x4Zrr, X86::VEXTRACTI32x4Zrr },
5817 { X86::VEXTRACTF32x4Zmr, X86::VEXTRACTF32x4Zmr, X86::VEXTRACTI32x4Zmr },
5818 { X86::VEXTRACTF32x8Zrr, X86::VEXTRACTF32x8Zrr, X86::VEXTRACTI32x8Zrr },
5819 { X86::VEXTRACTF32x8Zmr, X86::VEXTRACTF32x8Zmr, X86::VEXTRACTI32x8Zmr },
5820 { X86::VEXTRACTF64x2Zrr, X86::VEXTRACTF64x2Zrr, X86::VEXTRACTI64x2Zrr },
5821 { X86::VEXTRACTF64x2Zmr, X86::VEXTRACTF64x2Zmr, X86::VEXTRACTI64x2Zmr },
5822 { X86::VEXTRACTF64x4Zrr, X86::VEXTRACTF64x4Zrr, X86::VEXTRACTI64x4Zrr },
5823 { X86::VEXTRACTF64x4Zmr, X86::VEXTRACTF64x4Zmr, X86::VEXTRACTI64x4Zmr },
5824 { X86::VEXTRACTF32x4Z256rr,X86::VEXTRACTF32x4Z256rr,X86::VEXTRACTI32x4Z256rr },
5825 { X86::VEXTRACTF32x4Z256mr,X86::VEXTRACTF32x4Z256mr,X86::VEXTRACTI32x4Z256mr },
5826 { X86::VEXTRACTF64x2Z256rr,X86::VEXTRACTF64x2Z256rr,X86::VEXTRACTI64x2Z256rr },
5827 { X86::VEXTRACTF64x2Z256mr,X86::VEXTRACTF64x2Z256mr,X86::VEXTRACTI64x2Z256mr },
5828 { X86::VPERMILPSmi, X86::VPERMILPSmi, X86::VPSHUFDmi },
5829 { X86::VPERMILPSri, X86::VPERMILPSri, X86::VPSHUFDri },
5830 { X86::VPERMILPSZ128mi, X86::VPERMILPSZ128mi, X86::VPSHUFDZ128mi },
5831 { X86::VPERMILPSZ128ri, X86::VPERMILPSZ128ri, X86::VPSHUFDZ128ri },
5832 { X86::VPERMILPSZ256mi, X86::VPERMILPSZ256mi, X86::VPSHUFDZ256mi },
5833 { X86::VPERMILPSZ256ri, X86::VPERMILPSZ256ri, X86::VPSHUFDZ256ri },
5834 { X86::VPERMILPSZmi, X86::VPERMILPSZmi, X86::VPSHUFDZmi },
5835 { X86::VPERMILPSZri, X86::VPERMILPSZri, X86::VPSHUFDZri },
5836 { X86::VPERMPSZ256rm, X86::VPERMPSZ256rm, X86::VPERMDZ256rm },
5837 { X86::VPERMPSZ256rr, X86::VPERMPSZ256rr, X86::VPERMDZ256rr },
5838 { X86::VPERMPDZ256mi, X86::VPERMPDZ256mi, X86::VPERMQZ256mi },
5839 { X86::VPERMPDZ256ri, X86::VPERMPDZ256ri, X86::VPERMQZ256ri },
5840 { X86::VPERMPDZ256rm, X86::VPERMPDZ256rm, X86::VPERMQZ256rm },
5841 { X86::VPERMPDZ256rr, X86::VPERMPDZ256rr, X86::VPERMQZ256rr },
5842 { X86::VPERMPSZrm, X86::VPERMPSZrm, X86::VPERMDZrm },
5843 { X86::VPERMPSZrr, X86::VPERMPSZrr, X86::VPERMDZrr },
5844 { X86::VPERMPDZmi, X86::VPERMPDZmi, X86::VPERMQZmi },
5845 { X86::VPERMPDZri, X86::VPERMPDZri, X86::VPERMQZri },
5846 { X86::VPERMPDZrm, X86::VPERMPDZrm, X86::VPERMQZrm },
5847 { X86::VPERMPDZrr, X86::VPERMPDZrr, X86::VPERMQZrr },
5848 { X86::VUNPCKLPDZ256rm, X86::VUNPCKLPDZ256rm, X86::VPUNPCKLQDQZ256rm },
5849 { X86::VUNPCKLPDZ256rr, X86::VUNPCKLPDZ256rr, X86::VPUNPCKLQDQZ256rr },
5850 { X86::VUNPCKHPDZ256rm, X86::VUNPCKHPDZ256rm, X86::VPUNPCKHQDQZ256rm },
5851 { X86::VUNPCKHPDZ256rr, X86::VUNPCKHPDZ256rr, X86::VPUNPCKHQDQZ256rr },
5852 { X86::VUNPCKLPSZ256rm, X86::VUNPCKLPSZ256rm, X86::VPUNPCKLDQZ256rm },
5853 { X86::VUNPCKLPSZ256rr, X86::VUNPCKLPSZ256rr, X86::VPUNPCKLDQZ256rr },
5854 { X86::VUNPCKHPSZ256rm, X86::VUNPCKHPSZ256rm, X86::VPUNPCKHDQZ256rm },
5855 { X86::VUNPCKHPSZ256rr, X86::VUNPCKHPSZ256rr, X86::VPUNPCKHDQZ256rr },
5856 { X86::VUNPCKLPDZ128rm, X86::VUNPCKLPDZ128rm, X86::VPUNPCKLQDQZ128rm },
5857 { X86::VMOVLHPSZrr, X86::VUNPCKLPDZ128rr, X86::VPUNPCKLQDQZ128rr },
5858 { X86::VUNPCKHPDZ128rm, X86::VUNPCKHPDZ128rm, X86::VPUNPCKHQDQZ128rm },
5859 { X86::VUNPCKHPDZ128rr, X86::VUNPCKHPDZ128rr, X86::VPUNPCKHQDQZ128rr },
5860 { X86::VUNPCKLPSZ128rm, X86::VUNPCKLPSZ128rm, X86::VPUNPCKLDQZ128rm },
5861 { X86::VUNPCKLPSZ128rr, X86::VUNPCKLPSZ128rr, X86::VPUNPCKLDQZ128rr },
5862 { X86::VUNPCKHPSZ128rm, X86::VUNPCKHPSZ128rm, X86::VPUNPCKHDQZ128rm },
5863 { X86::VUNPCKHPSZ128rr, X86::VUNPCKHPSZ128rr, X86::VPUNPCKHDQZ128rr },
5864 { X86::VUNPCKLPDZrm, X86::VUNPCKLPDZrm, X86::VPUNPCKLQDQZrm },
5865 { X86::VUNPCKLPDZrr, X86::VUNPCKLPDZrr, X86::VPUNPCKLQDQZrr },
5866 { X86::VUNPCKHPDZrm, X86::VUNPCKHPDZrm, X86::VPUNPCKHQDQZrm },
5867 { X86::VUNPCKHPDZrr, X86::VUNPCKHPDZrr, X86::VPUNPCKHQDQZrr },
5868 { X86::VUNPCKLPSZrm, X86::VUNPCKLPSZrm, X86::VPUNPCKLDQZrm },
5869 { X86::VUNPCKLPSZrr, X86::VUNPCKLPSZrr, X86::VPUNPCKLDQZrr },
5870 { X86::VUNPCKHPSZrm, X86::VUNPCKHPSZrm, X86::VPUNPCKHDQZrm },
5871 { X86::VUNPCKHPSZrr, X86::VUNPCKHPSZrr, X86::VPUNPCKHDQZrr },
5872 { X86::VEXTRACTPSZmr, X86::VEXTRACTPSZmr, X86::VPEXTRDZmr },
5873 { X86::VEXTRACTPSZrr, X86::VEXTRACTPSZrr, X86::VPEXTRDZrr },
5874};
5875
5876static const uint16_t ReplaceableInstrsAVX2[][3] = {
5877 //PackedSingle PackedDouble PackedInt
5878 { X86::VANDNPSYrm, X86::VANDNPDYrm, X86::VPANDNYrm },
5879 { X86::VANDNPSYrr, X86::VANDNPDYrr, X86::VPANDNYrr },
5880 { X86::VANDPSYrm, X86::VANDPDYrm, X86::VPANDYrm },
5881 { X86::VANDPSYrr, X86::VANDPDYrr, X86::VPANDYrr },
5882 { X86::VORPSYrm, X86::VORPDYrm, X86::VPORYrm },
5883 { X86::VORPSYrr, X86::VORPDYrr, X86::VPORYrr },
5884 { X86::VXORPSYrm, X86::VXORPDYrm, X86::VPXORYrm },
5885 { X86::VXORPSYrr, X86::VXORPDYrr, X86::VPXORYrr },
5886 { X86::VPERM2F128rm, X86::VPERM2F128rm, X86::VPERM2I128rm },
5887 { X86::VPERM2F128rr, X86::VPERM2F128rr, X86::VPERM2I128rr },
5888 { X86::VBROADCASTSSrm, X86::VBROADCASTSSrm, X86::VPBROADCASTDrm},
5889 { X86::VBROADCASTSSrr, X86::VBROADCASTSSrr, X86::VPBROADCASTDrr},
5890 { X86::VMOVDDUPrm, X86::VMOVDDUPrm, X86::VPBROADCASTQrm},
5891 { X86::VMOVDDUPrr, X86::VMOVDDUPrr, X86::VPBROADCASTQrr},
5892 { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrr, X86::VPBROADCASTDYrr},
5893 { X86::VBROADCASTSSYrm, X86::VBROADCASTSSYrm, X86::VPBROADCASTDYrm},
5894 { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrr, X86::VPBROADCASTQYrr},
5895 { X86::VBROADCASTSDYrm, X86::VBROADCASTSDYrm, X86::VPBROADCASTQYrm},
5896 { X86::VBROADCASTF128, X86::VBROADCASTF128, X86::VBROADCASTI128 },
5897 { X86::VBLENDPSYrri, X86::VBLENDPSYrri, X86::VPBLENDDYrri },
5898 { X86::VBLENDPSYrmi, X86::VBLENDPSYrmi, X86::VPBLENDDYrmi },
5899 { X86::VPERMILPSYmi, X86::VPERMILPSYmi, X86::VPSHUFDYmi },
5900 { X86::VPERMILPSYri, X86::VPERMILPSYri, X86::VPSHUFDYri },
5901 { X86::VUNPCKLPDYrm, X86::VUNPCKLPDYrm, X86::VPUNPCKLQDQYrm },
5902 { X86::VUNPCKLPDYrr, X86::VUNPCKLPDYrr, X86::VPUNPCKLQDQYrr },
5903 { X86::VUNPCKHPDYrm, X86::VUNPCKHPDYrm, X86::VPUNPCKHQDQYrm },
5904 { X86::VUNPCKHPDYrr, X86::VUNPCKHPDYrr, X86::VPUNPCKHQDQYrr },
5905 { X86::VUNPCKLPSYrm, X86::VUNPCKLPSYrm, X86::VPUNPCKLDQYrm },
5906 { X86::VUNPCKLPSYrr, X86::VUNPCKLPSYrr, X86::VPUNPCKLDQYrr },
5907 { X86::VUNPCKHPSYrm, X86::VUNPCKHPSYrm, X86::VPUNPCKHDQYrm },
5908 { X86::VUNPCKHPSYrr, X86::VUNPCKHPSYrr, X86::VPUNPCKHDQYrr },
5909};
5910
5911static const uint16_t ReplaceableInstrsAVX2InsertExtract[][3] = {
5912 //PackedSingle PackedDouble PackedInt
5913 { X86::VEXTRACTF128mr, X86::VEXTRACTF128mr, X86::VEXTRACTI128mr },
5914 { X86::VEXTRACTF128rr, X86::VEXTRACTF128rr, X86::VEXTRACTI128rr },
5915 { X86::VINSERTF128rm, X86::VINSERTF128rm, X86::VINSERTI128rm },
5916 { X86::VINSERTF128rr, X86::VINSERTF128rr, X86::VINSERTI128rr },
5917};
5918
5919static const uint16_t ReplaceableInstrsAVX512[][4] = {
5920 // Two integer columns for 64-bit and 32-bit elements.
5921 //PackedSingle PackedDouble PackedInt PackedInt
5922 { X86::VMOVAPSZ128mr, X86::VMOVAPDZ128mr, X86::VMOVDQA64Z128mr, X86::VMOVDQA32Z128mr },
5923 { X86::VMOVAPSZ128rm, X86::VMOVAPDZ128rm, X86::VMOVDQA64Z128rm, X86::VMOVDQA32Z128rm },
5924 { X86::VMOVAPSZ128rr, X86::VMOVAPDZ128rr, X86::VMOVDQA64Z128rr, X86::VMOVDQA32Z128rr },
5925 { X86::VMOVUPSZ128mr, X86::VMOVUPDZ128mr, X86::VMOVDQU64Z128mr, X86::VMOVDQU32Z128mr },
5926 { X86::VMOVUPSZ128rm, X86::VMOVUPDZ128rm, X86::VMOVDQU64Z128rm, X86::VMOVDQU32Z128rm },
5927 { X86::VMOVAPSZ256mr, X86::VMOVAPDZ256mr, X86::VMOVDQA64Z256mr, X86::VMOVDQA32Z256mr },
5928 { X86::VMOVAPSZ256rm, X86::VMOVAPDZ256rm, X86::VMOVDQA64Z256rm, X86::VMOVDQA32Z256rm },
5929 { X86::VMOVAPSZ256rr, X86::VMOVAPDZ256rr, X86::VMOVDQA64Z256rr, X86::VMOVDQA32Z256rr },
5930 { X86::VMOVUPSZ256mr, X86::VMOVUPDZ256mr, X86::VMOVDQU64Z256mr, X86::VMOVDQU32Z256mr },
5931 { X86::VMOVUPSZ256rm, X86::VMOVUPDZ256rm, X86::VMOVDQU64Z256rm, X86::VMOVDQU32Z256rm },
5932 { X86::VMOVAPSZmr, X86::VMOVAPDZmr, X86::VMOVDQA64Zmr, X86::VMOVDQA32Zmr },
5933 { X86::VMOVAPSZrm, X86::VMOVAPDZrm, X86::VMOVDQA64Zrm, X86::VMOVDQA32Zrm },
5934 { X86::VMOVAPSZrr, X86::VMOVAPDZrr, X86::VMOVDQA64Zrr, X86::VMOVDQA32Zrr },
5935 { X86::VMOVUPSZmr, X86::VMOVUPDZmr, X86::VMOVDQU64Zmr, X86::VMOVDQU32Zmr },
5936 { X86::VMOVUPSZrm, X86::VMOVUPDZrm, X86::VMOVDQU64Zrm, X86::VMOVDQU32Zrm },
5937};
5938
5939static const uint16_t ReplaceableInstrsAVX512DQ[][4] = {
5940 // Two integer columns for 64-bit and 32-bit elements.
5941 //PackedSingle PackedDouble PackedInt PackedInt
5942 { X86::VANDNPSZ128rm, X86::VANDNPDZ128rm, X86::VPANDNQZ128rm, X86::VPANDNDZ128rm },
5943 { X86::VANDNPSZ128rr, X86::VANDNPDZ128rr, X86::VPANDNQZ128rr, X86::VPANDNDZ128rr },
5944 { X86::VANDPSZ128rm, X86::VANDPDZ128rm, X86::VPANDQZ128rm, X86::VPANDDZ128rm },
5945 { X86::VANDPSZ128rr, X86::VANDPDZ128rr, X86::VPANDQZ128rr, X86::VPANDDZ128rr },
5946 { X86::VORPSZ128rm, X86::VORPDZ128rm, X86::VPORQZ128rm, X86::VPORDZ128rm },
5947 { X86::VORPSZ128rr, X86::VORPDZ128rr, X86::VPORQZ128rr, X86::VPORDZ128rr },
5948 { X86::VXORPSZ128rm, X86::VXORPDZ128rm, X86::VPXORQZ128rm, X86::VPXORDZ128rm },
5949 { X86::VXORPSZ128rr, X86::VXORPDZ128rr, X86::VPXORQZ128rr, X86::VPXORDZ128rr },
5950 { X86::VANDNPSZ256rm, X86::VANDNPDZ256rm, X86::VPANDNQZ256rm, X86::VPANDNDZ256rm },
5951 { X86::VANDNPSZ256rr, X86::VANDNPDZ256rr, X86::VPANDNQZ256rr, X86::VPANDNDZ256rr },
5952 { X86::VANDPSZ256rm, X86::VANDPDZ256rm, X86::VPANDQZ256rm, X86::VPANDDZ256rm },
5953 { X86::VANDPSZ256rr, X86::VANDPDZ256rr, X86::VPANDQZ256rr, X86::VPANDDZ256rr },
5954 { X86::VORPSZ256rm, X86::VORPDZ256rm, X86::VPORQZ256rm, X86::VPORDZ256rm },
5955 { X86::VORPSZ256rr, X86::VORPDZ256rr, X86::VPORQZ256rr, X86::VPORDZ256rr },
5956 { X86::VXORPSZ256rm, X86::VXORPDZ256rm, X86::VPXORQZ256rm, X86::VPXORDZ256rm },
5957 { X86::VXORPSZ256rr, X86::VXORPDZ256rr, X86::VPXORQZ256rr, X86::VPXORDZ256rr },
5958 { X86::VANDNPSZrm, X86::VANDNPDZrm, X86::VPANDNQZrm, X86::VPANDNDZrm },
5959 { X86::VANDNPSZrr, X86::VANDNPDZrr, X86::VPANDNQZrr, X86::VPANDNDZrr },
5960 { X86::VANDPSZrm, X86::VANDPDZrm, X86::VPANDQZrm, X86::VPANDDZrm },
5961 { X86::VANDPSZrr, X86::VANDPDZrr, X86::VPANDQZrr, X86::VPANDDZrr },
5962 { X86::VORPSZrm, X86::VORPDZrm, X86::VPORQZrm, X86::VPORDZrm },
5963 { X86::VORPSZrr, X86::VORPDZrr, X86::VPORQZrr, X86::VPORDZrr },
5964 { X86::VXORPSZrm, X86::VXORPDZrm, X86::VPXORQZrm, X86::VPXORDZrm },
5965 { X86::VXORPSZrr, X86::VXORPDZrr, X86::VPXORQZrr, X86::VPXORDZrr },
5966};
5967
5968static const uint16_t ReplaceableInstrsAVX512DQMasked[][4] = {
5969 // Two integer columns for 64-bit and 32-bit elements.
5970 //PackedSingle PackedDouble
5971 //PackedInt PackedInt
5972 { X86::VANDNPSZ128rmk, X86::VANDNPDZ128rmk,
5973 X86::VPANDNQZ128rmk, X86::VPANDNDZ128rmk },
5974 { X86::VANDNPSZ128rmkz, X86::VANDNPDZ128rmkz,
5975 X86::VPANDNQZ128rmkz, X86::VPANDNDZ128rmkz },
5976 { X86::VANDNPSZ128rrk, X86::VANDNPDZ128rrk,
5977 X86::VPANDNQZ128rrk, X86::VPANDNDZ128rrk },
5978 { X86::VANDNPSZ128rrkz, X86::VANDNPDZ128rrkz,
5979 X86::VPANDNQZ128rrkz, X86::VPANDNDZ128rrkz },
5980 { X86::VANDPSZ128rmk, X86::VANDPDZ128rmk,
5981 X86::VPANDQZ128rmk, X86::VPANDDZ128rmk },
5982 { X86::VANDPSZ128rmkz, X86::VANDPDZ128rmkz,
5983 X86::VPANDQZ128rmkz, X86::VPANDDZ128rmkz },
5984 { X86::VANDPSZ128rrk, X86::VANDPDZ128rrk,
5985 X86::VPANDQZ128rrk, X86::VPANDDZ128rrk },
5986 { X86::VANDPSZ128rrkz, X86::VANDPDZ128rrkz,
5987 X86::VPANDQZ128rrkz, X86::VPANDDZ128rrkz },
5988 { X86::VORPSZ128rmk, X86::VORPDZ128rmk,
5989 X86::VPORQZ128rmk, X86::VPORDZ128rmk },
5990 { X86::VORPSZ128rmkz, X86::VORPDZ128rmkz,
5991 X86::VPORQZ128rmkz, X86::VPORDZ128rmkz },
5992 { X86::VORPSZ128rrk, X86::VORPDZ128rrk,
5993 X86::VPORQZ128rrk, X86::VPORDZ128rrk },
5994 { X86::VORPSZ128rrkz, X86::VORPDZ128rrkz,
5995 X86::VPORQZ128rrkz, X86::VPORDZ128rrkz },
5996 { X86::VXORPSZ128rmk, X86::VXORPDZ128rmk,
5997 X86::VPXORQZ128rmk, X86::VPXORDZ128rmk },
5998 { X86::VXORPSZ128rmkz, X86::VXORPDZ128rmkz,
5999 X86::VPXORQZ128rmkz, X86::VPXORDZ128rmkz },
6000 { X86::VXORPSZ128rrk, X86::VXORPDZ128rrk,
6001 X86::VPXORQZ128rrk, X86::VPXORDZ128rrk },
6002 { X86::VXORPSZ128rrkz, X86::VXORPDZ128rrkz,
6003 X86::VPXORQZ128rrkz, X86::VPXORDZ128rrkz },
6004 { X86::VANDNPSZ256rmk, X86::VANDNPDZ256rmk,
6005 X86::VPANDNQZ256rmk, X86::VPANDNDZ256rmk },
6006 { X86::VANDNPSZ256rmkz, X86::VANDNPDZ256rmkz,
6007 X86::VPANDNQZ256rmkz, X86::VPANDNDZ256rmkz },
6008 { X86::VANDNPSZ256rrk, X86::VANDNPDZ256rrk,
6009 X86::VPANDNQZ256rrk, X86::VPANDNDZ256rrk },
6010 { X86::VANDNPSZ256rrkz, X86::VANDNPDZ256rrkz,
6011 X86::VPANDNQZ256rrkz, X86::VPANDNDZ256rrkz },
6012 { X86::VANDPSZ256rmk, X86::VANDPDZ256rmk,
6013 X86::VPANDQZ256rmk, X86::VPANDDZ256rmk },
6014 { X86::VANDPSZ256rmkz, X86::VANDPDZ256rmkz,
6015 X86::VPANDQZ256rmkz, X86::VPANDDZ256rmkz },
6016 { X86::VANDPSZ256rrk, X86::VANDPDZ256rrk,
6017 X86::VPANDQZ256rrk, X86::VPANDDZ256rrk },
6018 { X86::VANDPSZ256rrkz, X86::VANDPDZ256rrkz,
6019 X86::VPANDQZ256rrkz, X86::VPANDDZ256rrkz },
6020 { X86::VORPSZ256rmk, X86::VORPDZ256rmk,
6021 X86::VPORQZ256rmk, X86::VPORDZ256rmk },
6022 { X86::VORPSZ256rmkz, X86::VORPDZ256rmkz,
6023 X86::VPORQZ256rmkz, X86::VPORDZ256rmkz },
6024 { X86::VORPSZ256rrk, X86::VORPDZ256rrk,
6025 X86::VPORQZ256rrk, X86::VPORDZ256rrk },
6026 { X86::VORPSZ256rrkz, X86::VORPDZ256rrkz,
6027 X86::VPORQZ256rrkz, X86::VPORDZ256rrkz },
6028 { X86::VXORPSZ256rmk, X86::VXORPDZ256rmk,
6029 X86::VPXORQZ256rmk, X86::VPXORDZ256rmk },
6030 { X86::VXORPSZ256rmkz, X86::VXORPDZ256rmkz,
6031 X86::VPXORQZ256rmkz, X86::VPXORDZ256rmkz },
6032 { X86::VXORPSZ256rrk, X86::VXORPDZ256rrk,
6033 X86::VPXORQZ256rrk, X86::VPXORDZ256rrk },
6034 { X86::VXORPSZ256rrkz, X86::VXORPDZ256rrkz,
6035 X86::VPXORQZ256rrkz, X86::VPXORDZ256rrkz },
6036 { X86::VANDNPSZrmk, X86::VANDNPDZrmk,
6037 X86::VPANDNQZrmk, X86::VPANDNDZrmk },
6038 { X86::VANDNPSZrmkz, X86::VANDNPDZrmkz,
6039 X86::VPANDNQZrmkz, X86::VPANDNDZrmkz },
6040 { X86::VANDNPSZrrk, X86::VANDNPDZrrk,
6041 X86::VPANDNQZrrk, X86::VPANDNDZrrk },
6042 { X86::VANDNPSZrrkz, X86::VANDNPDZrrkz,
6043 X86::VPANDNQZrrkz, X86::VPANDNDZrrkz },
6044 { X86::VANDPSZrmk, X86::VANDPDZrmk,
6045 X86::VPANDQZrmk, X86::VPANDDZrmk },
6046 { X86::VANDPSZrmkz, X86::VANDPDZrmkz,
6047 X86::VPANDQZrmkz, X86::VPANDDZrmkz },
6048 { X86::VANDPSZrrk, X86::VANDPDZrrk,
6049 X86::VPANDQZrrk, X86::VPANDDZrrk },
6050 { X86::VANDPSZrrkz, X86::VANDPDZrrkz,
6051 X86::VPANDQZrrkz, X86::VPANDDZrrkz },
6052 { X86::VORPSZrmk, X86::VORPDZrmk,
6053 X86::VPORQZrmk, X86::VPORDZrmk },
6054 { X86::VORPSZrmkz, X86::VORPDZrmkz,
6055 X86::VPORQZrmkz, X86::VPORDZrmkz },
6056 { X86::VORPSZrrk, X86::VORPDZrrk,
6057 X86::VPORQZrrk, X86::VPORDZrrk },
6058 { X86::VORPSZrrkz, X86::VORPDZrrkz,
6059 X86::VPORQZrrkz, X86::VPORDZrrkz },
6060 { X86::VXORPSZrmk, X86::VXORPDZrmk,
6061 X86::VPXORQZrmk, X86::VPXORDZrmk },
6062 { X86::VXORPSZrmkz, X86::VXORPDZrmkz,
6063 X86::VPXORQZrmkz, X86::VPXORDZrmkz },
6064 { X86::VXORPSZrrk, X86::VXORPDZrrk,
6065 X86::VPXORQZrrk, X86::VPXORDZrrk },
6066 { X86::VXORPSZrrkz, X86::VXORPDZrrkz,
6067 X86::VPXORQZrrkz, X86::VPXORDZrrkz },
6068 // Broadcast loads can be handled the same as masked operations to avoid
6069 // changing element size.
6070 { X86::VANDNPSZ128rmb, X86::VANDNPDZ128rmb,
6071 X86::VPANDNQZ128rmb, X86::VPANDNDZ128rmb },
6072 { X86::VANDPSZ128rmb, X86::VANDPDZ128rmb,
6073 X86::VPANDQZ128rmb, X86::VPANDDZ128rmb },
6074 { X86::VORPSZ128rmb, X86::VORPDZ128rmb,
6075 X86::VPORQZ128rmb, X86::VPORDZ128rmb },
6076 { X86::VXORPSZ128rmb, X86::VXORPDZ128rmb,
6077 X86::VPXORQZ128rmb, X86::VPXORDZ128rmb },
6078 { X86::VANDNPSZ256rmb, X86::VANDNPDZ256rmb,
6079 X86::VPANDNQZ256rmb, X86::VPANDNDZ256rmb },
6080 { X86::VANDPSZ256rmb, X86::VANDPDZ256rmb,
6081 X86::VPANDQZ256rmb, X86::VPANDDZ256rmb },
6082 { X86::VORPSZ256rmb, X86::VORPDZ256rmb,
6083 X86::VPORQZ256rmb, X86::VPORDZ256rmb },
6084 { X86::VXORPSZ256rmb, X86::VXORPDZ256rmb,
6085 X86::VPXORQZ256rmb, X86::VPXORDZ256rmb },
6086 { X86::VANDNPSZrmb, X86::VANDNPDZrmb,
6087 X86::VPANDNQZrmb, X86::VPANDNDZrmb },
6088 { X86::VANDPSZrmb, X86::VANDPDZrmb,
6089 X86::VPANDQZrmb, X86::VPANDDZrmb },
6090 { X86::VANDPSZrmb, X86::VANDPDZrmb,
6091 X86::VPANDQZrmb, X86::VPANDDZrmb },
6092 { X86::VORPSZrmb, X86::VORPDZrmb,
6093 X86::VPORQZrmb, X86::VPORDZrmb },
6094 { X86::VXORPSZrmb, X86::VXORPDZrmb,
6095 X86::VPXORQZrmb, X86::VPXORDZrmb },
6096 { X86::VANDNPSZ128rmbk, X86::VANDNPDZ128rmbk,
6097 X86::VPANDNQZ128rmbk, X86::VPANDNDZ128rmbk },
6098 { X86::VANDPSZ128rmbk, X86::VANDPDZ128rmbk,
6099 X86::VPANDQZ128rmbk, X86::VPANDDZ128rmbk },
6100 { X86::VORPSZ128rmbk, X86::VORPDZ128rmbk,
6101 X86::VPORQZ128rmbk, X86::VPORDZ128rmbk },
6102 { X86::VXORPSZ128rmbk, X86::VXORPDZ128rmbk,
6103 X86::VPXORQZ128rmbk, X86::VPXORDZ128rmbk },
6104 { X86::VANDNPSZ256rmbk, X86::VANDNPDZ256rmbk,
6105 X86::VPANDNQZ256rmbk, X86::VPANDNDZ256rmbk },
6106 { X86::VANDPSZ256rmbk, X86::VANDPDZ256rmbk,
6107 X86::VPANDQZ256rmbk, X86::VPANDDZ256rmbk },
6108 { X86::VORPSZ256rmbk, X86::VORPDZ256rmbk,
6109 X86::VPORQZ256rmbk, X86::VPORDZ256rmbk },
6110 { X86::VXORPSZ256rmbk, X86::VXORPDZ256rmbk,
6111 X86::VPXORQZ256rmbk, X86::VPXORDZ256rmbk },
6112 { X86::VANDNPSZrmbk, X86::VANDNPDZrmbk,
6113 X86::VPANDNQZrmbk, X86::VPANDNDZrmbk },
6114 { X86::VANDPSZrmbk, X86::VANDPDZrmbk,
6115 X86::VPANDQZrmbk, X86::VPANDDZrmbk },
6116 { X86::VANDPSZrmbk, X86::VANDPDZrmbk,
6117 X86::VPANDQZrmbk, X86::VPANDDZrmbk },
6118 { X86::VORPSZrmbk, X86::VORPDZrmbk,
6119 X86::VPORQZrmbk, X86::VPORDZrmbk },
6120 { X86::VXORPSZrmbk, X86::VXORPDZrmbk,
6121 X86::VPXORQZrmbk, X86::VPXORDZrmbk },
6122 { X86::VANDNPSZ128rmbkz,X86::VANDNPDZ128rmbkz,
6123 X86::VPANDNQZ128rmbkz,X86::VPANDNDZ128rmbkz},
6124 { X86::VANDPSZ128rmbkz, X86::VANDPDZ128rmbkz,
6125 X86::VPANDQZ128rmbkz, X86::VPANDDZ128rmbkz },
6126 { X86::VORPSZ128rmbkz, X86::VORPDZ128rmbkz,
6127 X86::VPORQZ128rmbkz, X86::VPORDZ128rmbkz },
6128 { X86::VXORPSZ128rmbkz, X86::VXORPDZ128rmbkz,
6129 X86::VPXORQZ128rmbkz, X86::VPXORDZ128rmbkz },
6130 { X86::VANDNPSZ256rmbkz,X86::VANDNPDZ256rmbkz,
6131 X86::VPANDNQZ256rmbkz,X86::VPANDNDZ256rmbkz},
6132 { X86::VANDPSZ256rmbkz, X86::VANDPDZ256rmbkz,
6133 X86::VPANDQZ256rmbkz, X86::VPANDDZ256rmbkz },
6134 { X86::VORPSZ256rmbkz, X86::VORPDZ256rmbkz,
6135 X86::VPORQZ256rmbkz, X86::VPORDZ256rmbkz },
6136 { X86::VXORPSZ256rmbkz, X86::VXORPDZ256rmbkz,
6137 X86::VPXORQZ256rmbkz, X86::VPXORDZ256rmbkz },
6138 { X86::VANDNPSZrmbkz, X86::VANDNPDZrmbkz,
6139 X86::VPANDNQZrmbkz, X86::VPANDNDZrmbkz },
6140 { X86::VANDPSZrmbkz, X86::VANDPDZrmbkz,
6141 X86::VPANDQZrmbkz, X86::VPANDDZrmbkz },
6142 { X86::VANDPSZrmbkz, X86::VANDPDZrmbkz,
6143 X86::VPANDQZrmbkz, X86::VPANDDZrmbkz },
6144 { X86::VORPSZrmbkz, X86::VORPDZrmbkz,
6145 X86::VPORQZrmbkz, X86::VPORDZrmbkz },
6146 { X86::VXORPSZrmbkz, X86::VXORPDZrmbkz,
6147 X86::VPXORQZrmbkz, X86::VPXORDZrmbkz },
6148};
6149
6150// NOTE: These should only be used by the custom domain methods.
6151static const uint16_t ReplaceableCustomInstrs[][3] = {
6152 //PackedSingle PackedDouble PackedInt
6153 { X86::BLENDPSrmi, X86::BLENDPDrmi, X86::PBLENDWrmi },
6154 { X86::BLENDPSrri, X86::BLENDPDrri, X86::PBLENDWrri },
6155 { X86::VBLENDPSrmi, X86::VBLENDPDrmi, X86::VPBLENDWrmi },
6156 { X86::VBLENDPSrri, X86::VBLENDPDrri, X86::VPBLENDWrri },
6157 { X86::VBLENDPSYrmi, X86::VBLENDPDYrmi, X86::VPBLENDWYrmi },
6158 { X86::VBLENDPSYrri, X86::VBLENDPDYrri, X86::VPBLENDWYrri },
6159};
6160static const uint16_t ReplaceableCustomAVX2Instrs[][3] = {
6161 //PackedSingle PackedDouble PackedInt
6162 { X86::VBLENDPSrmi, X86::VBLENDPDrmi, X86::VPBLENDDrmi },
6163 { X86::VBLENDPSrri, X86::VBLENDPDrri, X86::VPBLENDDrri },
6164 { X86::VBLENDPSYrmi, X86::VBLENDPDYrmi, X86::VPBLENDDYrmi },
6165 { X86::VBLENDPSYrri, X86::VBLENDPDYrri, X86::VPBLENDDYrri },
6166};
6167
6168// Special table for changing EVEX logic instructions to VEX.
6169// TODO: Should we run EVEX->VEX earlier?
6170static const uint16_t ReplaceableCustomAVX512LogicInstrs[][4] = {
6171 // Two integer columns for 64-bit and 32-bit elements.
6172 //PackedSingle PackedDouble PackedInt PackedInt
6173 { X86::VANDNPSrm, X86::VANDNPDrm, X86::VPANDNQZ128rm, X86::VPANDNDZ128rm },
6174 { X86::VANDNPSrr, X86::VANDNPDrr, X86::VPANDNQZ128rr, X86::VPANDNDZ128rr },
6175 { X86::VANDPSrm, X86::VANDPDrm, X86::VPANDQZ128rm, X86::VPANDDZ128rm },
6176 { X86::VANDPSrr, X86::VANDPDrr, X86::VPANDQZ128rr, X86::VPANDDZ128rr },
6177 { X86::VORPSrm, X86::VORPDrm, X86::VPORQZ128rm, X86::VPORDZ128rm },
6178 { X86::VORPSrr, X86::VORPDrr, X86::VPORQZ128rr, X86::VPORDZ128rr },
6179 { X86::VXORPSrm, X86::VXORPDrm, X86::VPXORQZ128rm, X86::VPXORDZ128rm },
6180 { X86::VXORPSrr, X86::VXORPDrr, X86::VPXORQZ128rr, X86::VPXORDZ128rr },
6181 { X86::VANDNPSYrm, X86::VANDNPDYrm, X86::VPANDNQZ256rm, X86::VPANDNDZ256rm },
6182 { X86::VANDNPSYrr, X86::VANDNPDYrr, X86::VPANDNQZ256rr, X86::VPANDNDZ256rr },
6183 { X86::VANDPSYrm, X86::VANDPDYrm, X86::VPANDQZ256rm, X86::VPANDDZ256rm },
6184 { X86::VANDPSYrr, X86::VANDPDYrr, X86::VPANDQZ256rr, X86::VPANDDZ256rr },
6185 { X86::VORPSYrm, X86::VORPDYrm, X86::VPORQZ256rm, X86::VPORDZ256rm },
6186 { X86::VORPSYrr, X86::VORPDYrr, X86::VPORQZ256rr, X86::VPORDZ256rr },
6187 { X86::VXORPSYrm, X86::VXORPDYrm, X86::VPXORQZ256rm, X86::VPXORDZ256rm },
6188 { X86::VXORPSYrr, X86::VXORPDYrr, X86::VPXORQZ256rr, X86::VPXORDZ256rr },
6189};
6190
6191// FIXME: Some shuffle and unpack instructions have equivalents in different
6192// domains, but they require a bit more work than just switching opcodes.
6193
6194static const uint16_t *lookup(unsigned opcode, unsigned domain,
6195 ArrayRef<uint16_t[3]> Table) {
6196 for (const uint16_t (&Row)[3] : Table)
6197 if (Row[domain-1] == opcode)
6198 return Row;
6199 return nullptr;
6200}
6201
6202static const uint16_t *lookupAVX512(unsigned opcode, unsigned domain,
6203 ArrayRef<uint16_t[4]> Table) {
6204 // If this is the integer domain make sure to check both integer columns.
6205 for (const uint16_t (&Row)[4] : Table)
6206 if (Row[domain-1] == opcode || (domain == 3 && Row[3] == opcode))
6207 return Row;
6208 return nullptr;
6209}
6210
6211// Helper to attempt to widen/narrow blend masks.
6212static bool AdjustBlendMask(unsigned OldMask, unsigned OldWidth,
6213 unsigned NewWidth, unsigned *pNewMask = nullptr) {
6214 assert(((OldWidth % NewWidth) == 0 || (NewWidth % OldWidth) == 0) &&((((OldWidth % NewWidth) == 0 || (NewWidth % OldWidth) == 0) &&
"Illegal blend mask scale") ? static_cast<void> (0) : __assert_fail
("((OldWidth % NewWidth) == 0 || (NewWidth % OldWidth) == 0) && \"Illegal blend mask scale\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 6215, __PRETTY_FUNCTION__))
6215 "Illegal blend mask scale")((((OldWidth % NewWidth) == 0 || (NewWidth % OldWidth) == 0) &&
"Illegal blend mask scale") ? static_cast<void> (0) : __assert_fail
("((OldWidth % NewWidth) == 0 || (NewWidth % OldWidth) == 0) && \"Illegal blend mask scale\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 6215, __PRETTY_FUNCTION__));
6216 unsigned NewMask = 0;
6217
6218 if ((OldWidth % NewWidth) == 0) {
6219 unsigned Scale = OldWidth / NewWidth;
6220 unsigned SubMask = (1u << Scale) - 1;
6221 for (unsigned i = 0; i != NewWidth; ++i) {
6222 unsigned Sub = (OldMask >> (i * Scale)) & SubMask;
6223 if (Sub == SubMask)
6224 NewMask |= (1u << i);
6225 else if (Sub != 0x0)
6226 return false;
6227 }
6228 } else {
6229 unsigned Scale = NewWidth / OldWidth;
6230 unsigned SubMask = (1u << Scale) - 1;
6231 for (unsigned i = 0; i != OldWidth; ++i) {
6232 if (OldMask & (1 << i)) {
6233 NewMask |= (SubMask << (i * Scale));
6234 }
6235 }
6236 }
6237
6238 if (pNewMask)
6239 *pNewMask = NewMask;
6240 return true;
6241}
6242
6243uint16_t X86InstrInfo::getExecutionDomainCustom(const MachineInstr &MI) const {
6244 unsigned Opcode = MI.getOpcode();
6245 unsigned NumOperands = MI.getDesc().getNumOperands();
6246
6247 auto GetBlendDomains = [&](unsigned ImmWidth, bool Is256) {
6248 uint16_t validDomains = 0;
6249 if (MI.getOperand(NumOperands - 1).isImm()) {
6250 unsigned Imm = MI.getOperand(NumOperands - 1).getImm();
6251 if (AdjustBlendMask(Imm, ImmWidth, Is256 ? 8 : 4))
6252 validDomains |= 0x2; // PackedSingle
6253 if (AdjustBlendMask(Imm, ImmWidth, Is256 ? 4 : 2))
6254 validDomains |= 0x4; // PackedDouble
6255 if (!Is256 || Subtarget.hasAVX2())
6256 validDomains |= 0x8; // PackedInt
6257 }
6258 return validDomains;
6259 };
6260
6261 switch (Opcode) {
6262 case X86::BLENDPDrmi:
6263 case X86::BLENDPDrri:
6264 case X86::VBLENDPDrmi:
6265 case X86::VBLENDPDrri:
6266 return GetBlendDomains(2, false);
6267 case X86::VBLENDPDYrmi:
6268 case X86::VBLENDPDYrri:
6269 return GetBlendDomains(4, true);
6270 case X86::BLENDPSrmi:
6271 case X86::BLENDPSrri:
6272 case X86::VBLENDPSrmi:
6273 case X86::VBLENDPSrri:
6274 case X86::VPBLENDDrmi:
6275 case X86::VPBLENDDrri:
6276 return GetBlendDomains(4, false);
6277 case X86::VBLENDPSYrmi:
6278 case X86::VBLENDPSYrri:
6279 case X86::VPBLENDDYrmi:
6280 case X86::VPBLENDDYrri:
6281 return GetBlendDomains(8, true);
6282 case X86::PBLENDWrmi:
6283 case X86::PBLENDWrri:
6284 case X86::VPBLENDWrmi:
6285 case X86::VPBLENDWrri:
6286 // Treat VPBLENDWY as a 128-bit vector as it repeats the lo/hi masks.
6287 case X86::VPBLENDWYrmi:
6288 case X86::VPBLENDWYrri:
6289 return GetBlendDomains(8, false);
6290 case X86::VPANDDZ128rr: case X86::VPANDDZ128rm:
6291 case X86::VPANDDZ256rr: case X86::VPANDDZ256rm:
6292 case X86::VPANDQZ128rr: case X86::VPANDQZ128rm:
6293 case X86::VPANDQZ256rr: case X86::VPANDQZ256rm:
6294 case X86::VPANDNDZ128rr: case X86::VPANDNDZ128rm:
6295 case X86::VPANDNDZ256rr: case X86::VPANDNDZ256rm:
6296 case X86::VPANDNQZ128rr: case X86::VPANDNQZ128rm:
6297 case X86::VPANDNQZ256rr: case X86::VPANDNQZ256rm:
6298 case X86::VPORDZ128rr: case X86::VPORDZ128rm:
6299 case X86::VPORDZ256rr: case X86::VPORDZ256rm:
6300 case X86::VPORQZ128rr: case X86::VPORQZ128rm:
6301 case X86::VPORQZ256rr: case X86::VPORQZ256rm:
6302 case X86::VPXORDZ128rr: case X86::VPXORDZ128rm:
6303 case X86::VPXORDZ256rr: case X86::VPXORDZ256rm:
6304 case X86::VPXORQZ128rr: case X86::VPXORQZ128rm:
6305 case X86::VPXORQZ256rr: case X86::VPXORQZ256rm:
6306 // If we don't have DQI see if we can still switch from an EVEX integer
6307 // instruction to a VEX floating point instruction.
6308 if (Subtarget.hasDQI())
6309 return 0;
6310
6311 if (RI.getEncodingValue(MI.getOperand(0).getReg()) >= 16)
6312 return 0;
6313 if (RI.getEncodingValue(MI.getOperand(1).getReg()) >= 16)
6314 return 0;
6315 // Register forms will have 3 operands. Memory form will have more.
6316 if (NumOperands == 3 &&
6317 RI.getEncodingValue(MI.getOperand(2).getReg()) >= 16)
6318 return 0;
6319
6320 // All domains are valid.
6321 return 0xe;
6322 case X86::MOVHLPSrr:
6323 // We can swap domains when both inputs are the same register.
6324 // FIXME: This doesn't catch all the cases we would like. If the input
6325 // register isn't KILLed by the instruction, the two address instruction
6326 // pass puts a COPY on one input. The other input uses the original
6327 // register. This prevents the same physical register from being used by
6328 // both inputs.
6329 if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg() &&
6330 MI.getOperand(0).getSubReg() == 0 &&
6331 MI.getOperand(1).getSubReg() == 0 &&
6332 MI.getOperand(2).getSubReg() == 0)
6333 return 0x6;
6334 return 0;
6335 }
6336 return 0;
6337}
6338
6339bool X86InstrInfo::setExecutionDomainCustom(MachineInstr &MI,
6340 unsigned Domain) const {
6341 assert(Domain > 0 && Domain < 4 && "Invalid execution domain")((Domain > 0 && Domain < 4 && "Invalid execution domain"
) ? static_cast<void> (0) : __assert_fail ("Domain > 0 && Domain < 4 && \"Invalid execution domain\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 6341, __PRETTY_FUNCTION__));
6342 uint16_t dom = (MI.getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
6343 assert(dom && "Not an SSE instruction")((dom && "Not an SSE instruction") ? static_cast<void
> (0) : __assert_fail ("dom && \"Not an SSE instruction\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 6343, __PRETTY_FUNCTION__));
6344
6345 unsigned Opcode = MI.getOpcode();
6346 unsigned NumOperands = MI.getDesc().getNumOperands();
6347
6348 auto SetBlendDomain = [&](unsigned ImmWidth, bool Is256) {
6349 if (MI.getOperand(NumOperands - 1).isImm()) {
6350 unsigned Imm = MI.getOperand(NumOperands - 1).getImm() & 255;
6351 Imm = (ImmWidth == 16 ? ((Imm << 8) | Imm) : Imm);
6352 unsigned NewImm = Imm;
6353
6354 const uint16_t *table = lookup(Opcode, dom, ReplaceableCustomInstrs);
6355 if (!table)
6356 table = lookup(Opcode, dom, ReplaceableCustomAVX2Instrs);
6357
6358 if (Domain == 1) { // PackedSingle
6359 AdjustBlendMask(Imm, ImmWidth, Is256 ? 8 : 4, &NewImm);
6360 } else if (Domain == 2) { // PackedDouble
6361 AdjustBlendMask(Imm, ImmWidth, Is256 ? 4 : 2, &NewImm);
6362 } else if (Domain == 3) { // PackedInt
6363 if (Subtarget.hasAVX2()) {
6364 // If we are already VPBLENDW use that, else use VPBLENDD.
6365 if ((ImmWidth / (Is256 ? 2 : 1)) != 8) {
6366 table = lookup(Opcode, dom, ReplaceableCustomAVX2Instrs);
6367 AdjustBlendMask(Imm, ImmWidth, Is256 ? 8 : 4, &NewImm);
6368 }
6369 } else {
6370 assert(!Is256 && "128-bit vector expected")((!Is256 && "128-bit vector expected") ? static_cast<
void> (0) : __assert_fail ("!Is256 && \"128-bit vector expected\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 6370, __PRETTY_FUNCTION__));
6371 AdjustBlendMask(Imm, ImmWidth, 8, &NewImm);
6372 }
6373 }
6374
6375 assert(table && table[Domain - 1] && "Unknown domain op")((table && table[Domain - 1] && "Unknown domain op"
) ? static_cast<void> (0) : __assert_fail ("table && table[Domain - 1] && \"Unknown domain op\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 6375, __PRETTY_FUNCTION__));
6376 MI.setDesc(get(table[Domain - 1]));
6377 MI.getOperand(NumOperands - 1).setImm(NewImm & 255);
6378 }
6379 return true;
6380 };
6381
6382 switch (Opcode) {
6383 case X86::BLENDPDrmi:
6384 case X86::BLENDPDrri:
6385 case X86::VBLENDPDrmi:
6386 case X86::VBLENDPDrri:
6387 return SetBlendDomain(2, false);
6388 case X86::VBLENDPDYrmi:
6389 case X86::VBLENDPDYrri:
6390 return SetBlendDomain(4, true);
6391 case X86::BLENDPSrmi:
6392 case X86::BLENDPSrri:
6393 case X86::VBLENDPSrmi:
6394 case X86::VBLENDPSrri:
6395 case X86::VPBLENDDrmi:
6396 case X86::VPBLENDDrri:
6397 return SetBlendDomain(4, false);
6398 case X86::VBLENDPSYrmi:
6399 case X86::VBLENDPSYrri:
6400 case X86::VPBLENDDYrmi:
6401 case X86::VPBLENDDYrri:
6402 return SetBlendDomain(8, true);
6403 case X86::PBLENDWrmi:
6404 case X86::PBLENDWrri:
6405 case X86::VPBLENDWrmi:
6406 case X86::VPBLENDWrri:
6407 return SetBlendDomain(8, false);
6408 case X86::VPBLENDWYrmi:
6409 case X86::VPBLENDWYrri:
6410 return SetBlendDomain(16, true);
6411 case X86::VPANDDZ128rr: case X86::VPANDDZ128rm:
6412 case X86::VPANDDZ256rr: case X86::VPANDDZ256rm:
6413 case X86::VPANDQZ128rr: case X86::VPANDQZ128rm:
6414 case X86::VPANDQZ256rr: case X86::VPANDQZ256rm:
6415 case X86::VPANDNDZ128rr: case X86::VPANDNDZ128rm:
6416 case X86::VPANDNDZ256rr: case X86::VPANDNDZ256rm:
6417 case X86::VPANDNQZ128rr: case X86::VPANDNQZ128rm:
6418 case X86::VPANDNQZ256rr: case X86::VPANDNQZ256rm:
6419 case X86::VPORDZ128rr: case X86::VPORDZ128rm:
6420 case X86::VPORDZ256rr: case X86::VPORDZ256rm:
6421 case X86::VPORQZ128rr: case X86::VPORQZ128rm:
6422 case X86::VPORQZ256rr: case X86::VPORQZ256rm:
6423 case X86::VPXORDZ128rr: case X86::VPXORDZ128rm:
6424 case X86::VPXORDZ256rr: case X86::VPXORDZ256rm:
6425 case X86::VPXORQZ128rr: case X86::VPXORQZ128rm:
6426 case X86::VPXORQZ256rr: case X86::VPXORQZ256rm: {
6427 // Without DQI, convert EVEX instructions to VEX instructions.
6428 if (Subtarget.hasDQI())
6429 return false;
6430
6431 const uint16_t *table = lookupAVX512(MI.getOpcode(), dom,
6432 ReplaceableCustomAVX512LogicInstrs);
6433 assert(table && "Instruction not found in table?")((table && "Instruction not found in table?") ? static_cast
<void> (0) : __assert_fail ("table && \"Instruction not found in table?\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 6433, __PRETTY_FUNCTION__));
6434 // Don't change integer Q instructions to D instructions and
6435 // use D intructions if we started with a PS instruction.
6436 if (Domain == 3 && (dom == 1 || table[3] == MI.getOpcode()))
6437 Domain = 4;
6438 MI.setDesc(get(table[Domain - 1]));
6439 return true;
6440 }
6441 case X86::UNPCKHPDrr:
6442 case X86::MOVHLPSrr:
6443 // We just need to commute the instruction which will switch the domains.
6444 if (Domain != dom && Domain != 3 &&
6445 MI.getOperand(1).getReg() == MI.getOperand(2).getReg() &&
6446 MI.getOperand(0).getSubReg() == 0 &&
6447 MI.getOperand(1).getSubReg() == 0 &&
6448 MI.getOperand(2).getSubReg() == 0) {
6449 commuteInstruction(MI, false);
6450 return true;
6451 }
6452 // We must always return true for MOVHLPSrr.
6453 if (Opcode == X86::MOVHLPSrr)
6454 return true;
6455 }
6456 return false;
6457}
6458
6459std::pair<uint16_t, uint16_t>
6460X86InstrInfo::getExecutionDomain(const MachineInstr &MI) const {
6461 uint16_t domain = (MI.getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
6462 unsigned opcode = MI.getOpcode();
6463 uint16_t validDomains = 0;
6464 if (domain) {
6465 // Attempt to match for custom instructions.
6466 validDomains = getExecutionDomainCustom(MI);
6467 if (validDomains)
6468 return std::make_pair(domain, validDomains);
6469
6470 if (lookup(opcode, domain, ReplaceableInstrs)) {
6471 validDomains = 0xe;
6472 } else if (lookup(opcode, domain, ReplaceableInstrsAVX2)) {
6473 validDomains = Subtarget.hasAVX2() ? 0xe : 0x6;
6474 } else if (lookup(opcode, domain, ReplaceableInstrsAVX2InsertExtract)) {
6475 // Insert/extract instructions should only effect domain if AVX2
6476 // is enabled.
6477 if (!Subtarget.hasAVX2())
6478 return std::make_pair(0, 0);
6479 validDomains = 0xe;
6480 } else if (lookupAVX512(opcode, domain, ReplaceableInstrsAVX512)) {
6481 validDomains = 0xe;
6482 } else if (Subtarget.hasDQI() && lookupAVX512(opcode, domain,
6483 ReplaceableInstrsAVX512DQ)) {
6484 validDomains = 0xe;
6485 } else if (Subtarget.hasDQI()) {
6486 if (const uint16_t *table = lookupAVX512(opcode, domain,
6487 ReplaceableInstrsAVX512DQMasked)) {
6488 if (domain == 1 || (domain == 3 && table[3] == opcode))
6489 validDomains = 0xa;
6490 else
6491 validDomains = 0xc;
6492 }
6493 }
6494 }
6495 return std::make_pair(domain, validDomains);
6496}
6497
6498void X86InstrInfo::setExecutionDomain(MachineInstr &MI, unsigned Domain) const {
6499 assert(Domain>0 && Domain<4 && "Invalid execution domain")((Domain>0 && Domain<4 && "Invalid execution domain"
) ? static_cast<void> (0) : __assert_fail ("Domain>0 && Domain<4 && \"Invalid execution domain\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 6499, __PRETTY_FUNCTION__));
6500 uint16_t dom = (MI.getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
6501 assert(dom && "Not an SSE instruction")((dom && "Not an SSE instruction") ? static_cast<void
> (0) : __assert_fail ("dom && \"Not an SSE instruction\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 6501, __PRETTY_FUNCTION__));
6502
6503 // Attempt to match for custom instructions.
6504 if (setExecutionDomainCustom(MI, Domain))
6505 return;
6506
6507 const uint16_t *table = lookup(MI.getOpcode(), dom, ReplaceableInstrs);
6508 if (!table) { // try the other table
6509 assert((Subtarget.hasAVX2() || Domain < 3) &&(((Subtarget.hasAVX2() || Domain < 3) && "256-bit vector operations only available in AVX2"
) ? static_cast<void> (0) : __assert_fail ("(Subtarget.hasAVX2() || Domain < 3) && \"256-bit vector operations only available in AVX2\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 6510, __PRETTY_FUNCTION__))
6510 "256-bit vector operations only available in AVX2")(((Subtarget.hasAVX2() || Domain < 3) && "256-bit vector operations only available in AVX2"
) ? static_cast<void> (0) : __assert_fail ("(Subtarget.hasAVX2() || Domain < 3) && \"256-bit vector operations only available in AVX2\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 6510, __PRETTY_FUNCTION__));
6511 table = lookup(MI.getOpcode(), dom, ReplaceableInstrsAVX2);
6512 }
6513 if (!table) { // try the other table
6514 assert(Subtarget.hasAVX2() &&((Subtarget.hasAVX2() && "256-bit insert/extract only available in AVX2"
) ? static_cast<void> (0) : __assert_fail ("Subtarget.hasAVX2() && \"256-bit insert/extract only available in AVX2\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 6515, __PRETTY_FUNCTION__))
6515 "256-bit insert/extract only available in AVX2")((Subtarget.hasAVX2() && "256-bit insert/extract only available in AVX2"
) ? static_cast<void> (0) : __assert_fail ("Subtarget.hasAVX2() && \"256-bit insert/extract only available in AVX2\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 6515, __PRETTY_FUNCTION__));
6516 table = lookup(MI.getOpcode(), dom, ReplaceableInstrsAVX2InsertExtract);
6517 }
6518 if (!table) { // try the AVX512 table
6519 assert(Subtarget.hasAVX512() && "Requires AVX-512")((Subtarget.hasAVX512() && "Requires AVX-512") ? static_cast
<void> (0) : __assert_fail ("Subtarget.hasAVX512() && \"Requires AVX-512\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 6519, __PRETTY_FUNCTION__));
6520 table = lookupAVX512(MI.getOpcode(), dom, ReplaceableInstrsAVX512);
6521 // Don't change integer Q instructions to D instructions.
6522 if (table && Domain == 3 && table[3] == MI.getOpcode())
6523 Domain = 4;
6524 }
6525 if (!table) { // try the AVX512DQ table
6526 assert((Subtarget.hasDQI() || Domain >= 3) && "Requires AVX-512DQ")(((Subtarget.hasDQI() || Domain >= 3) && "Requires AVX-512DQ"
) ? static_cast<void> (0) : __assert_fail ("(Subtarget.hasDQI() || Domain >= 3) && \"Requires AVX-512DQ\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 6526, __PRETTY_FUNCTION__));
6527 table = lookupAVX512(MI.getOpcode(), dom, ReplaceableInstrsAVX512DQ);
6528 // Don't change integer Q instructions to D instructions and
6529 // use D intructions if we started with a PS instruction.
6530 if (table && Domain == 3 && (dom == 1 || table[3] == MI.getOpcode()))
6531 Domain = 4;
6532 }
6533 if (!table) { // try the AVX512DQMasked table
6534 assert((Subtarget.hasDQI() || Domain >= 3) && "Requires AVX-512DQ")(((Subtarget.hasDQI() || Domain >= 3) && "Requires AVX-512DQ"
) ? static_cast<void> (0) : __assert_fail ("(Subtarget.hasDQI() || Domain >= 3) && \"Requires AVX-512DQ\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 6534, __PRETTY_FUNCTION__));
6535 table = lookupAVX512(MI.getOpcode(), dom, ReplaceableInstrsAVX512DQMasked);
6536 if (table && Domain == 3 && (dom == 1 || table[3] == MI.getOpcode()))
6537 Domain = 4;
6538 }
6539 assert(table && "Cannot change domain")((table && "Cannot change domain") ? static_cast<void
> (0) : __assert_fail ("table && \"Cannot change domain\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 6539, __PRETTY_FUNCTION__));
6540 MI.setDesc(get(table[Domain - 1]));
6541}
6542
6543/// Return the noop instruction to use for a noop.
6544void X86InstrInfo::getNoop(MCInst &NopInst) const {
6545 NopInst.setOpcode(X86::NOOP);
6546}
6547
6548bool X86InstrInfo::isHighLatencyDef(int opc) const {
6549 switch (opc) {
6550 default: return false;
6551 case X86::DIVPDrm:
6552 case X86::DIVPDrr:
6553 case X86::DIVPSrm:
6554 case X86::DIVPSrr:
6555 case X86::DIVSDrm:
6556 case X86::DIVSDrm_Int:
6557 case X86::DIVSDrr:
6558 case X86::DIVSDrr_Int:
6559 case X86::DIVSSrm:
6560 case X86::DIVSSrm_Int:
6561 case X86::DIVSSrr:
6562 case X86::DIVSSrr_Int:
6563 case X86::SQRTPDm:
6564 case X86::SQRTPDr:
6565 case X86::SQRTPSm:
6566 case X86::SQRTPSr:
6567 case X86::SQRTSDm:
6568 case X86::SQRTSDm_Int:
6569 case X86::SQRTSDr:
6570 case X86::SQRTSDr_Int:
6571 case X86::SQRTSSm:
6572 case X86::SQRTSSm_Int:
6573 case X86::SQRTSSr:
6574 case X86::SQRTSSr_Int:
6575 // AVX instructions with high latency
6576 case X86::VDIVPDrm:
6577 case X86::VDIVPDrr:
6578 case X86::VDIVPDYrm:
6579 case X86::VDIVPDYrr:
6580 case X86::VDIVPSrm:
6581 case X86::VDIVPSrr:
6582 case X86::VDIVPSYrm:
6583 case X86::VDIVPSYrr:
6584 case X86::VDIVSDrm:
6585 case X86::VDIVSDrm_Int:
6586 case X86::VDIVSDrr:
6587 case X86::VDIVSDrr_Int:
6588 case X86::VDIVSSrm:
6589 case X86::VDIVSSrm_Int:
6590 case X86::VDIVSSrr:
6591 case X86::VDIVSSrr_Int:
6592 case X86::VSQRTPDm:
6593 case X86::VSQRTPDr:
6594 case X86::VSQRTPDYm:
6595 case X86::VSQRTPDYr:
6596 case X86::VSQRTPSm:
6597 case X86::VSQRTPSr:
6598 case X86::VSQRTPSYm:
6599 case X86::VSQRTPSYr:
6600 case X86::VSQRTSDm:
6601 case X86::VSQRTSDm_Int:
6602 case X86::VSQRTSDr:
6603 case X86::VSQRTSDr_Int:
6604 case X86::VSQRTSSm:
6605 case X86::VSQRTSSm_Int:
6606 case X86::VSQRTSSr:
6607 case X86::VSQRTSSr_Int:
6608 // AVX512 instructions with high latency
6609 case X86::VDIVPDZ128rm:
6610 case X86::VDIVPDZ128rmb:
6611 case X86::VDIVPDZ128rmbk:
6612 case X86::VDIVPDZ128rmbkz:
6613 case X86::VDIVPDZ128rmk:
6614 case X86::VDIVPDZ128rmkz:
6615 case X86::VDIVPDZ128rr:
6616 case X86::VDIVPDZ128rrk:
6617 case X86::VDIVPDZ128rrkz:
6618 case X86::VDIVPDZ256rm:
6619 case X86::VDIVPDZ256rmb:
6620 case X86::VDIVPDZ256rmbk:
6621 case X86::VDIVPDZ256rmbkz:
6622 case X86::VDIVPDZ256rmk:
6623 case X86::VDIVPDZ256rmkz:
6624 case X86::VDIVPDZ256rr:
6625 case X86::VDIVPDZ256rrk:
6626 case X86::VDIVPDZ256rrkz:
6627 case X86::VDIVPDZrrb:
6628 case X86::VDIVPDZrrbk:
6629 case X86::VDIVPDZrrbkz:
6630 case X86::VDIVPDZrm:
6631 case X86::VDIVPDZrmb:
6632 case X86::VDIVPDZrmbk:
6633 case X86::VDIVPDZrmbkz:
6634 case X86::VDIVPDZrmk:
6635 case X86::VDIVPDZrmkz:
6636 case X86::VDIVPDZrr:
6637 case X86::VDIVPDZrrk:
6638 case X86::VDIVPDZrrkz:
6639 case X86::VDIVPSZ128rm:
6640 case X86::VDIVPSZ128rmb:
6641 case X86::VDIVPSZ128rmbk:
6642 case X86::VDIVPSZ128rmbkz:
6643 case X86::VDIVPSZ128rmk:
6644 case X86::VDIVPSZ128rmkz:
6645 case X86::VDIVPSZ128rr:
6646 case X86::VDIVPSZ128rrk:
6647 case X86::VDIVPSZ128rrkz:
6648 case X86::VDIVPSZ256rm:
6649 case X86::VDIVPSZ256rmb:
6650 case X86::VDIVPSZ256rmbk:
6651 case X86::VDIVPSZ256rmbkz:
6652 case X86::VDIVPSZ256rmk:
6653 case X86::VDIVPSZ256rmkz:
6654 case X86::VDIVPSZ256rr:
6655 case X86::VDIVPSZ256rrk:
6656 case X86::VDIVPSZ256rrkz:
6657 case X86::VDIVPSZrrb:
6658 case X86::VDIVPSZrrbk:
6659 case X86::VDIVPSZrrbkz:
6660 case X86::VDIVPSZrm:
6661 case X86::VDIVPSZrmb:
6662 case X86::VDIVPSZrmbk:
6663 case X86::VDIVPSZrmbkz:
6664 case X86::VDIVPSZrmk:
6665 case X86::VDIVPSZrmkz:
6666 case X86::VDIVPSZrr:
6667 case X86::VDIVPSZrrk:
6668 case X86::VDIVPSZrrkz:
6669 case X86::VDIVSDZrm:
6670 case X86::VDIVSDZrr:
6671 case X86::VDIVSDZrm_Int:
6672 case X86::VDIVSDZrm_Intk:
6673 case X86::VDIVSDZrm_Intkz:
6674 case X86::VDIVSDZrr_Int:
6675 case X86::VDIVSDZrr_Intk:
6676 case X86::VDIVSDZrr_Intkz:
6677 case X86::VDIVSDZrrb_Int:
6678 case X86::VDIVSDZrrb_Intk:
6679 case X86::VDIVSDZrrb_Intkz:
6680 case X86::VDIVSSZrm:
6681 case X86::VDIVSSZrr:
6682 case X86::VDIVSSZrm_Int:
6683 case X86::VDIVSSZrm_Intk:
6684 case X86::VDIVSSZrm_Intkz:
6685 case X86::VDIVSSZrr_Int:
6686 case X86::VDIVSSZrr_Intk:
6687 case X86::VDIVSSZrr_Intkz:
6688 case X86::VDIVSSZrrb_Int:
6689 case X86::VDIVSSZrrb_Intk:
6690 case X86::VDIVSSZrrb_Intkz:
6691 case X86::VSQRTPDZ128m:
6692 case X86::VSQRTPDZ128mb:
6693 case X86::VSQRTPDZ128mbk:
6694 case X86::VSQRTPDZ128mbkz:
6695 case X86::VSQRTPDZ128mk:
6696 case X86::VSQRTPDZ128mkz:
6697 case X86::VSQRTPDZ128r:
6698 case X86::VSQRTPDZ128rk:
6699 case X86::VSQRTPDZ128rkz:
6700 case X86::VSQRTPDZ256m:
6701 case X86::VSQRTPDZ256mb:
6702 case X86::VSQRTPDZ256mbk:
6703 case X86::VSQRTPDZ256mbkz:
6704 case X86::VSQRTPDZ256mk:
6705 case X86::VSQRTPDZ256mkz:
6706 case X86::VSQRTPDZ256r:
6707 case X86::VSQRTPDZ256rk:
6708 case X86::VSQRTPDZ256rkz:
6709 case X86::VSQRTPDZm:
6710 case X86::VSQRTPDZmb:
6711 case X86::VSQRTPDZmbk:
6712 case X86::VSQRTPDZmbkz:
6713 case X86::VSQRTPDZmk:
6714 case X86::VSQRTPDZmkz:
6715 case X86::VSQRTPDZr:
6716 case X86::VSQRTPDZrb:
6717 case X86::VSQRTPDZrbk:
6718 case X86::VSQRTPDZrbkz:
6719 case X86::VSQRTPDZrk:
6720 case X86::VSQRTPDZrkz:
6721 case X86::VSQRTPSZ128m:
6722 case X86::VSQRTPSZ128mb:
6723 case X86::VSQRTPSZ128mbk:
6724 case X86::VSQRTPSZ128mbkz:
6725 case X86::VSQRTPSZ128mk:
6726 case X86::VSQRTPSZ128mkz:
6727 case X86::VSQRTPSZ128r:
6728 case X86::VSQRTPSZ128rk:
6729 case X86::VSQRTPSZ128rkz:
6730 case X86::VSQRTPSZ256m:
6731 case X86::VSQRTPSZ256mb:
6732 case X86::VSQRTPSZ256mbk:
6733 case X86::VSQRTPSZ256mbkz:
6734 case X86::VSQRTPSZ256mk:
6735 case X86::VSQRTPSZ256mkz:
6736 case X86::VSQRTPSZ256r:
6737 case X86::VSQRTPSZ256rk:
6738 case X86::VSQRTPSZ256rkz:
6739 case X86::VSQRTPSZm:
6740 case X86::VSQRTPSZmb:
6741 case X86::VSQRTPSZmbk:
6742 case X86::VSQRTPSZmbkz:
6743 case X86::VSQRTPSZmk:
6744 case X86::VSQRTPSZmkz:
6745 case X86::VSQRTPSZr:
6746 case X86::VSQRTPSZrb:
6747 case X86::VSQRTPSZrbk:
6748 case X86::VSQRTPSZrbkz:
6749 case X86::VSQRTPSZrk:
6750 case X86::VSQRTPSZrkz:
6751 case X86::VSQRTSDZm:
6752 case X86::VSQRTSDZm_Int:
6753 case X86::VSQRTSDZm_Intk:
6754 case X86::VSQRTSDZm_Intkz:
6755 case X86::VSQRTSDZr:
6756 case X86::VSQRTSDZr_Int:
6757 case X86::VSQRTSDZr_Intk:
6758 case X86::VSQRTSDZr_Intkz:
6759 case X86::VSQRTSDZrb_Int:
6760 case X86::VSQRTSDZrb_Intk:
6761 case X86::VSQRTSDZrb_Intkz:
6762 case X86::VSQRTSSZm:
6763 case X86::VSQRTSSZm_Int:
6764 case X86::VSQRTSSZm_Intk:
6765 case X86::VSQRTSSZm_Intkz:
6766 case X86::VSQRTSSZr:
6767 case X86::VSQRTSSZr_Int:
6768 case X86::VSQRTSSZr_Intk:
6769 case X86::VSQRTSSZr_Intkz:
6770 case X86::VSQRTSSZrb_Int:
6771 case X86::VSQRTSSZrb_Intk:
6772 case X86::VSQRTSSZrb_Intkz:
6773
6774 case X86::VGATHERDPDYrm:
6775 case X86::VGATHERDPDZ128rm:
6776 case X86::VGATHERDPDZ256rm:
6777 case X86::VGATHERDPDZrm:
6778 case X86::VGATHERDPDrm:
6779 case X86::VGATHERDPSYrm:
6780 case X86::VGATHERDPSZ128rm:
6781 case X86::VGATHERDPSZ256rm:
6782 case X86::VGATHERDPSZrm:
6783 case X86::VGATHERDPSrm:
6784 case X86::VGATHERPF0DPDm:
6785 case X86::VGATHERPF0DPSm:
6786 case X86::VGATHERPF0QPDm:
6787 case X86::VGATHERPF0QPSm:
6788 case X86::VGATHERPF1DPDm:
6789 case X86::VGATHERPF1DPSm:
6790 case X86::VGATHERPF1QPDm:
6791 case X86::VGATHERPF1QPSm:
6792 case X86::VGATHERQPDYrm:
6793 case X86::VGATHERQPDZ128rm:
6794 case X86::VGATHERQPDZ256rm:
6795 case X86::VGATHERQPDZrm:
6796 case X86::VGATHERQPDrm:
6797 case X86::VGATHERQPSYrm:
6798 case X86::VGATHERQPSZ128rm:
6799 case X86::VGATHERQPSZ256rm:
6800 case X86::VGATHERQPSZrm:
6801 case X86::VGATHERQPSrm:
6802 case X86::VPGATHERDDYrm:
6803 case X86::VPGATHERDDZ128rm:
6804 case X86::VPGATHERDDZ256rm:
6805 case X86::VPGATHERDDZrm:
6806 case X86::VPGATHERDDrm:
6807 case X86::VPGATHERDQYrm:
6808 case X86::VPGATHERDQZ128rm:
6809 case X86::VPGATHERDQZ256rm:
6810 case X86::VPGATHERDQZrm:
6811 case X86::VPGATHERDQrm:
6812 case X86::VPGATHERQDYrm:
6813 case X86::VPGATHERQDZ128rm:
6814 case X86::VPGATHERQDZ256rm:
6815 case X86::VPGATHERQDZrm:
6816 case X86::VPGATHERQDrm:
6817 case X86::VPGATHERQQYrm:
6818 case X86::VPGATHERQQZ128rm:
6819 case X86::VPGATHERQQZ256rm:
6820 case X86::VPGATHERQQZrm:
6821 case X86::VPGATHERQQrm:
6822 case X86::VSCATTERDPDZ128mr:
6823 case X86::VSCATTERDPDZ256mr:
6824 case X86::VSCATTERDPDZmr:
6825 case X86::VSCATTERDPSZ128mr:
6826 case X86::VSCATTERDPSZ256mr:
6827 case X86::VSCATTERDPSZmr:
6828 case X86::VSCATTERPF0DPDm:
6829 case X86::VSCATTERPF0DPSm:
6830 case X86::VSCATTERPF0QPDm:
6831 case X86::VSCATTERPF0QPSm:
6832 case X86::VSCATTERPF1DPDm:
6833 case X86::VSCATTERPF1DPSm:
6834 case X86::VSCATTERPF1QPDm:
6835 case X86::VSCATTERPF1QPSm:
6836 case X86::VSCATTERQPDZ128mr:
6837 case X86::VSCATTERQPDZ256mr:
6838 case X86::VSCATTERQPDZmr:
6839 case X86::VSCATTERQPSZ128mr:
6840 case X86::VSCATTERQPSZ256mr:
6841 case X86::VSCATTERQPSZmr:
6842 case X86::VPSCATTERDDZ128mr:
6843 case X86::VPSCATTERDDZ256mr:
6844 case X86::VPSCATTERDDZmr:
6845 case X86::VPSCATTERDQZ128mr:
6846 case X86::VPSCATTERDQZ256mr:
6847 case X86::VPSCATTERDQZmr:
6848 case X86::VPSCATTERQDZ128mr:
6849 case X86::VPSCATTERQDZ256mr:
6850 case X86::VPSCATTERQDZmr:
6851 case X86::VPSCATTERQQZ128mr:
6852 case X86::VPSCATTERQQZ256mr:
6853 case X86::VPSCATTERQQZmr:
6854 return true;
6855 }
6856}
6857
6858bool X86InstrInfo::hasHighOperandLatency(const TargetSchedModel &SchedModel,
6859 const MachineRegisterInfo *MRI,
6860 const MachineInstr &DefMI,
6861 unsigned DefIdx,
6862 const MachineInstr &UseMI,
6863 unsigned UseIdx) const {
6864 return isHighLatencyDef(DefMI.getOpcode());
6865}
6866
6867bool X86InstrInfo::hasReassociableOperands(const MachineInstr &Inst,
6868 const MachineBasicBlock *MBB) const {
6869 assert((Inst.getNumOperands() == 3 || Inst.getNumOperands() == 4) &&(((Inst.getNumOperands() == 3 || Inst.getNumOperands() == 4) &&
"Reassociation needs binary operators") ? static_cast<void
> (0) : __assert_fail ("(Inst.getNumOperands() == 3 || Inst.getNumOperands() == 4) && \"Reassociation needs binary operators\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 6870, __PRETTY_FUNCTION__))
6870 "Reassociation needs binary operators")(((Inst.getNumOperands() == 3 || Inst.getNumOperands() == 4) &&
"Reassociation needs binary operators") ? static_cast<void
> (0) : __assert_fail ("(Inst.getNumOperands() == 3 || Inst.getNumOperands() == 4) && \"Reassociation needs binary operators\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 6870, __PRETTY_FUNCTION__));
6871
6872 // Integer binary math/logic instructions have a third source operand:
6873 // the EFLAGS register. That operand must be both defined here and never
6874 // used; ie, it must be dead. If the EFLAGS operand is live, then we can
6875 // not change anything because rearranging the operands could affect other
6876 // instructions that depend on the exact status flags (zero, sign, etc.)
6877 // that are set by using these particular operands with this operation.
6878 if (Inst.getNumOperands() == 4) {
6879 assert(Inst.getOperand(3).isReg() &&((Inst.getOperand(3).isReg() && Inst.getOperand(3).getReg
() == X86::EFLAGS && "Unexpected operand in reassociable instruction"
) ? static_cast<void> (0) : __assert_fail ("Inst.getOperand(3).isReg() && Inst.getOperand(3).getReg() == X86::EFLAGS && \"Unexpected operand in reassociable instruction\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 6881, __PRETTY_FUNCTION__))
6880 Inst.getOperand(3).getReg() == X86::EFLAGS &&((Inst.getOperand(3).isReg() && Inst.getOperand(3).getReg
() == X86::EFLAGS && "Unexpected operand in reassociable instruction"
) ? static_cast<void> (0) : __assert_fail ("Inst.getOperand(3).isReg() && Inst.getOperand(3).getReg() == X86::EFLAGS && \"Unexpected operand in reassociable instruction\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 6881, __PRETTY_FUNCTION__))
6881 "Unexpected operand in reassociable instruction")((Inst.getOperand(3).isReg() && Inst.getOperand(3).getReg
() == X86::EFLAGS && "Unexpected operand in reassociable instruction"
) ? static_cast<void> (0) : __assert_fail ("Inst.getOperand(3).isReg() && Inst.getOperand(3).getReg() == X86::EFLAGS && \"Unexpected operand in reassociable instruction\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 6881, __PRETTY_FUNCTION__));
6882 if (!Inst.getOperand(3).isDead())
6883 return false;
6884 }
6885
6886 return TargetInstrInfo::hasReassociableOperands(Inst, MBB);
6887}
6888
6889// TODO: There are many more machine instruction opcodes to match:
6890// 1. Other data types (integer, vectors)
6891// 2. Other math / logic operations (xor, or)
6892// 3. Other forms of the same operation (intrinsics and other variants)
6893bool X86InstrInfo::isAssociativeAndCommutative(const MachineInstr &Inst) const {
6894 switch (Inst.getOpcode()) {
6895 case X86::AND8rr:
6896 case X86::AND16rr:
6897 case X86::AND32rr:
6898 case X86::AND64rr:
6899 case X86::OR8rr:
6900 case X86::OR16rr:
6901 case X86::OR32rr:
6902 case X86::OR64rr:
6903 case X86::XOR8rr:
6904 case X86::XOR16rr:
6905 case X86::XOR32rr:
6906 case X86::XOR64rr:
6907 case X86::IMUL16rr:
6908 case X86::IMUL32rr:
6909 case X86::IMUL64rr:
6910 case X86::PANDrr:
6911 case X86::PORrr:
6912 case X86::PXORrr:
6913 case X86::ANDPDrr:
6914 case X86::ANDPSrr:
6915 case X86::ORPDrr:
6916 case X86::ORPSrr:
6917 case X86::XORPDrr:
6918 case X86::XORPSrr:
6919 case X86::PADDBrr:
6920 case X86::PADDWrr:
6921 case X86::PADDDrr:
6922 case X86::PADDQrr:
6923 case X86::PMULLWrr:
6924 case X86::PMULLDrr:
6925 case X86::VPANDrr:
6926 case X86::VPANDYrr:
6927 case X86::VPANDDZ128rr:
6928 case X86::VPANDDZ256rr:
6929 case X86::VPANDDZrr:
6930 case X86::VPANDQZ128rr:
6931 case X86::VPANDQZ256rr:
6932 case X86::VPANDQZrr:
6933 case X86::VPORrr:
6934 case X86::VPORYrr:
6935 case X86::VPORDZ128rr:
6936 case X86::VPORDZ256rr:
6937 case X86::VPORDZrr:
6938 case X86::VPORQZ128rr:
6939 case X86::VPORQZ256rr:
6940 case X86::VPORQZrr:
6941 case X86::VPXORrr:
6942 case X86::VPXORYrr:
6943 case X86::VPXORDZ128rr:
6944 case X86::VPXORDZ256rr:
6945 case X86::VPXORDZrr:
6946 case X86::VPXORQZ128rr:
6947 case X86::VPXORQZ256rr:
6948 case X86::VPXORQZrr:
6949 case X86::VANDPDrr:
6950 case X86::VANDPSrr:
6951 case X86::VANDPDYrr:
6952 case X86::VANDPSYrr:
6953 case X86::VANDPDZ128rr:
6954 case X86::VANDPSZ128rr:
6955 case X86::VANDPDZ256rr:
6956 case X86::VANDPSZ256rr:
6957 case X86::VANDPDZrr:
6958 case X86::VANDPSZrr:
6959 case X86::VORPDrr:
6960 case X86::VORPSrr:
6961 case X86::VORPDYrr:
6962 case X86::VORPSYrr:
6963 case X86::VORPDZ128rr:
6964 case X86::VORPSZ128rr:
6965 case X86::VORPDZ256rr:
6966 case X86::VORPSZ256rr:
6967 case X86::VORPDZrr:
6968 case X86::VORPSZrr:
6969 case X86::VXORPDrr:
6970 case X86::VXORPSrr:
6971 case X86::VXORPDYrr:
6972 case X86::VXORPSYrr:
6973 case X86::VXORPDZ128rr:
6974 case X86::VXORPSZ128rr:
6975 case X86::VXORPDZ256rr:
6976 case X86::VXORPSZ256rr:
6977 case X86::VXORPDZrr:
6978 case X86::VXORPSZrr:
6979 case X86::KADDBrr:
6980 case X86::KADDWrr:
6981 case X86::KADDDrr:
6982 case X86::KADDQrr:
6983 case X86::KANDBrr:
6984 case X86::KANDWrr:
6985 case X86::KANDDrr:
6986 case X86::KANDQrr:
6987 case X86::KORBrr:
6988 case X86::KORWrr:
6989 case X86::KORDrr:
6990 case X86::KORQrr:
6991 case X86::KXORBrr:
6992 case X86::KXORWrr:
6993 case X86::KXORDrr:
6994 case X86::KXORQrr:
6995 case X86::VPADDBrr:
6996 case X86::VPADDWrr:
6997 case X86::VPADDDrr:
6998 case X86::VPADDQrr:
6999 case X86::VPADDBYrr:
7000 case X86::VPADDWYrr:
7001 case X86::VPADDDYrr:
7002 case X86::VPADDQYrr:
7003 case X86::VPADDBZ128rr:
7004 case X86::VPADDWZ128rr:
7005 case X86::VPADDDZ128rr:
7006 case X86::VPADDQZ128rr:
7007 case X86::VPADDBZ256rr:
7008 case X86::VPADDWZ256rr:
7009 case X86::VPADDDZ256rr:
7010 case X86::VPADDQZ256rr:
7011 case X86::VPADDBZrr:
7012 case X86::VPADDWZrr:
7013 case X86::VPADDDZrr:
7014 case X86::VPADDQZrr:
7015 case X86::VPMULLWrr:
7016 case X86::VPMULLWYrr:
7017 case X86::VPMULLWZ128rr:
7018 case X86::VPMULLWZ256rr:
7019 case X86::VPMULLWZrr:
7020 case X86::VPMULLDrr:
7021 case X86::VPMULLDYrr:
7022 case X86::VPMULLDZ128rr:
7023 case X86::VPMULLDZ256rr:
7024 case X86::VPMULLDZrr:
7025 case X86::VPMULLQZ128rr:
7026 case X86::VPMULLQZ256rr:
7027 case X86::VPMULLQZrr:
7028 // Normal min/max instructions are not commutative because of NaN and signed
7029 // zero semantics, but these are. Thus, there's no need to check for global
7030 // relaxed math; the instructions themselves have the properties we need.
7031 case X86::MAXCPDrr:
7032 case X86::MAXCPSrr:
7033 case X86::MAXCSDrr:
7034 case X86::MAXCSSrr:
7035 case X86::MINCPDrr:
7036 case X86::MINCPSrr:
7037 case X86::MINCSDrr:
7038 case X86::MINCSSrr:
7039 case X86::VMAXCPDrr:
7040 case X86::VMAXCPSrr:
7041 case X86::VMAXCPDYrr:
7042 case X86::VMAXCPSYrr:
7043 case X86::VMAXCPDZ128rr:
7044 case X86::VMAXCPSZ128rr:
7045 case X86::VMAXCPDZ256rr:
7046 case X86::VMAXCPSZ256rr:
7047 case X86::VMAXCPDZrr:
7048 case X86::VMAXCPSZrr:
7049 case X86::VMAXCSDrr:
7050 case X86::VMAXCSSrr:
7051 case X86::VMAXCSDZrr:
7052 case X86::VMAXCSSZrr:
7053 case X86::VMINCPDrr:
7054 case X86::VMINCPSrr:
7055 case X86::VMINCPDYrr:
7056 case X86::VMINCPSYrr:
7057 case X86::VMINCPDZ128rr:
7058 case X86::VMINCPSZ128rr:
7059 case X86::VMINCPDZ256rr:
7060 case X86::VMINCPSZ256rr:
7061 case X86::VMINCPDZrr:
7062 case X86::VMINCPSZrr:
7063 case X86::VMINCSDrr:
7064 case X86::VMINCSSrr:
7065 case X86::VMINCSDZrr:
7066 case X86::VMINCSSZrr:
7067 return true;
7068 case X86::ADDPDrr:
7069 case X86::ADDPSrr:
7070 case X86::ADDSDrr:
7071 case X86::ADDSSrr:
7072 case X86::MULPDrr:
7073 case X86::MULPSrr:
7074 case X86::MULSDrr:
7075 case X86::MULSSrr:
7076 case X86::VADDPDrr:
7077 case X86::VADDPSrr:
7078 case X86::VADDPDYrr:
7079 case X86::VADDPSYrr:
7080 case X86::VADDPDZ128rr:
7081 case X86::VADDPSZ128rr:
7082 case X86::VADDPDZ256rr:
7083 case X86::VADDPSZ256rr:
7084 case X86::VADDPDZrr:
7085 case X86::VADDPSZrr:
7086 case X86::VADDSDrr:
7087 case X86::VADDSSrr:
7088 case X86::VADDSDZrr:
7089 case X86::VADDSSZrr:
7090 case X86::VMULPDrr:
7091 case X86::VMULPSrr:
7092 case X86::VMULPDYrr:
7093 case X86::VMULPSYrr:
7094 case X86::VMULPDZ128rr:
7095 case X86::VMULPSZ128rr:
7096 case X86::VMULPDZ256rr:
7097 case X86::VMULPSZ256rr:
7098 case X86::VMULPDZrr:
7099 case X86::VMULPSZrr:
7100 case X86::VMULSDrr:
7101 case X86::VMULSSrr:
7102 case X86::VMULSDZrr:
7103 case X86::VMULSSZrr:
7104 return Inst.getParent()->getParent()->getTarget().Options.UnsafeFPMath;
7105 default:
7106 return false;
7107 }
7108}
7109
7110/// This is an architecture-specific helper function of reassociateOps.
7111/// Set special operand attributes for new instructions after reassociation.
7112void X86InstrInfo::setSpecialOperandAttr(MachineInstr &OldMI1,
7113 MachineInstr &OldMI2,
7114 MachineInstr &NewMI1,
7115 MachineInstr &NewMI2) const {
7116 // Integer instructions define an implicit EFLAGS source register operand as
7117 // the third source (fourth total) operand.
7118 if (OldMI1.getNumOperands() != 4 || OldMI2.getNumOperands() != 4)
7119 return;
7120
7121 assert(NewMI1.getNumOperands() == 4 && NewMI2.getNumOperands() == 4 &&((NewMI1.getNumOperands() == 4 && NewMI2.getNumOperands
() == 4 && "Unexpected instruction type for reassociation"
) ? static_cast<void> (0) : __assert_fail ("NewMI1.getNumOperands() == 4 && NewMI2.getNumOperands() == 4 && \"Unexpected instruction type for reassociation\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 7122, __PRETTY_FUNCTION__))
7122 "Unexpected instruction type for reassociation")((NewMI1.getNumOperands() == 4 && NewMI2.getNumOperands
() == 4 && "Unexpected instruction type for reassociation"
) ? static_cast<void> (0) : __assert_fail ("NewMI1.getNumOperands() == 4 && NewMI2.getNumOperands() == 4 && \"Unexpected instruction type for reassociation\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 7122, __PRETTY_FUNCTION__));
7123
7124 MachineOperand &OldOp1 = OldMI1.getOperand(3);
7125 MachineOperand &OldOp2 = OldMI2.getOperand(3);
7126 MachineOperand &NewOp1 = NewMI1.getOperand(3);
7127 MachineOperand &NewOp2 = NewMI2.getOperand(3);
7128
7129 assert(OldOp1.isReg() && OldOp1.getReg() == X86::EFLAGS && OldOp1.isDead() &&((OldOp1.isReg() && OldOp1.getReg() == X86::EFLAGS &&
OldOp1.isDead() && "Must have dead EFLAGS operand in reassociable instruction"
) ? static_cast<void> (0) : __assert_fail ("OldOp1.isReg() && OldOp1.getReg() == X86::EFLAGS && OldOp1.isDead() && \"Must have dead EFLAGS operand in reassociable instruction\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 7130, __PRETTY_FUNCTION__))
7130 "Must have dead EFLAGS operand in reassociable instruction")((OldOp1.isReg() && OldOp1.getReg() == X86::EFLAGS &&
OldOp1.isDead() && "Must have dead EFLAGS operand in reassociable instruction"
) ? static_cast<void> (0) : __assert_fail ("OldOp1.isReg() && OldOp1.getReg() == X86::EFLAGS && OldOp1.isDead() && \"Must have dead EFLAGS operand in reassociable instruction\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 7130, __PRETTY_FUNCTION__));
7131 assert(OldOp2.isReg() && OldOp2.getReg() == X86::EFLAGS && OldOp2.isDead() &&((OldOp2.isReg() && OldOp2.getReg() == X86::EFLAGS &&
OldOp2.isDead() && "Must have dead EFLAGS operand in reassociable instruction"
) ? static_cast<void> (0) : __assert_fail ("OldOp2.isReg() && OldOp2.getReg() == X86::EFLAGS && OldOp2.isDead() && \"Must have dead EFLAGS operand in reassociable instruction\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 7132, __PRETTY_FUNCTION__))
7132 "Must have dead EFLAGS operand in reassociable instruction")((OldOp2.isReg() && OldOp2.getReg() == X86::EFLAGS &&
OldOp2.isDead() && "Must have dead EFLAGS operand in reassociable instruction"
) ? static_cast<void> (0) : __assert_fail ("OldOp2.isReg() && OldOp2.getReg() == X86::EFLAGS && OldOp2.isDead() && \"Must have dead EFLAGS operand in reassociable instruction\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 7132, __PRETTY_FUNCTION__));
7133
7134 (void)OldOp1;
7135 (void)OldOp2;
7136
7137 assert(NewOp1.isReg() && NewOp1.getReg() == X86::EFLAGS &&((NewOp1.isReg() && NewOp1.getReg() == X86::EFLAGS &&
"Unexpected operand in reassociable instruction") ? static_cast
<void> (0) : __assert_fail ("NewOp1.isReg() && NewOp1.getReg() == X86::EFLAGS && \"Unexpected operand in reassociable instruction\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 7138, __PRETTY_FUNCTION__))
7138 "Unexpected operand in reassociable instruction")((NewOp1.isReg() && NewOp1.getReg() == X86::EFLAGS &&
"Unexpected operand in reassociable instruction") ? static_cast
<void> (0) : __assert_fail ("NewOp1.isReg() && NewOp1.getReg() == X86::EFLAGS && \"Unexpected operand in reassociable instruction\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 7138, __PRETTY_FUNCTION__));
7139 assert(NewOp2.isReg() && NewOp2.getReg() == X86::EFLAGS &&((NewOp2.isReg() && NewOp2.getReg() == X86::EFLAGS &&
"Unexpected operand in reassociable instruction") ? static_cast
<void> (0) : __assert_fail ("NewOp2.isReg() && NewOp2.getReg() == X86::EFLAGS && \"Unexpected operand in reassociable instruction\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 7140, __PRETTY_FUNCTION__))
7140 "Unexpected operand in reassociable instruction")((NewOp2.isReg() && NewOp2.getReg() == X86::EFLAGS &&
"Unexpected operand in reassociable instruction") ? static_cast
<void> (0) : __assert_fail ("NewOp2.isReg() && NewOp2.getReg() == X86::EFLAGS && \"Unexpected operand in reassociable instruction\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 7140, __PRETTY_FUNCTION__));
7141
7142 // Mark the new EFLAGS operands as dead to be helpful to subsequent iterations
7143 // of this pass or other passes. The EFLAGS operands must be dead in these new
7144 // instructions because the EFLAGS operands in the original instructions must
7145 // be dead in order for reassociation to occur.
7146 NewOp1.setIsDead();
7147 NewOp2.setIsDead();
7148}
7149
7150std::pair<unsigned, unsigned>
7151X86InstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
7152 return std::make_pair(TF, 0u);
7153}
7154
7155ArrayRef<std::pair<unsigned, const char *>>
7156X86InstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
7157 using namespace X86II;
7158 static const std::pair<unsigned, const char *> TargetFlags[] = {
7159 {MO_GOT_ABSOLUTE_ADDRESS, "x86-got-absolute-address"},
7160 {MO_PIC_BASE_OFFSET, "x86-pic-base-offset"},
7161 {MO_GOT, "x86-got"},
7162 {MO_GOTOFF, "x86-gotoff"},
7163 {MO_GOTPCREL, "x86-gotpcrel"},
7164 {MO_PLT, "x86-plt"},
7165 {MO_TLSGD, "x86-tlsgd"},
7166 {MO_TLSLD, "x86-tlsld"},
7167 {MO_TLSLDM, "x86-tlsldm"},
7168 {MO_GOTTPOFF, "x86-gottpoff"},
7169 {MO_INDNTPOFF, "x86-indntpoff"},
7170 {MO_TPOFF, "x86-tpoff"},
7171 {MO_DTPOFF, "x86-dtpoff"},
7172 {MO_NTPOFF, "x86-ntpoff"},
7173 {MO_GOTNTPOFF, "x86-gotntpoff"},
7174 {MO_DLLIMPORT, "x86-dllimport"},
7175 {MO_DARWIN_NONLAZY, "x86-darwin-nonlazy"},
7176 {MO_DARWIN_NONLAZY_PIC_BASE, "x86-darwin-nonlazy-pic-base"},
7177 {MO_TLVP, "x86-tlvp"},
7178 {MO_TLVP_PIC_BASE, "x86-tlvp-pic-base"},
7179 {MO_SECREL, "x86-secrel"},
7180 {MO_COFFSTUB, "x86-coffstub"}};
7181 return makeArrayRef(TargetFlags);
7182}
7183
7184namespace {
7185 /// Create Global Base Reg pass. This initializes the PIC
7186 /// global base register for x86-32.
7187 struct CGBR : public MachineFunctionPass {
7188 static char ID;
7189 CGBR() : MachineFunctionPass(ID) {}
7190
7191 bool runOnMachineFunction(MachineFunction &MF) override {
7192 const X86TargetMachine *TM =
7193 static_cast<const X86TargetMachine *>(&MF.getTarget());
7194 const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
7195
7196 // Don't do anything in the 64-bit small and kernel code models. They use
7197 // RIP-relative addressing for everything.
7198 if (STI.is64Bit() && (TM->getCodeModel() == CodeModel::Small ||
7199 TM->getCodeModel() == CodeModel::Kernel))
7200 return false;
7201
7202 // Only emit a global base reg in PIC mode.
7203 if (!TM->isPositionIndependent())
7204 return false;
7205
7206 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
7207 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
7208
7209 // If we didn't need a GlobalBaseReg, don't insert code.
7210 if (GlobalBaseReg == 0)
7211 return false;
7212
7213 // Insert the set of GlobalBaseReg into the first MBB of the function
7214 MachineBasicBlock &FirstMBB = MF.front();
7215 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
7216 DebugLoc DL = FirstMBB.findDebugLoc(MBBI);
7217 MachineRegisterInfo &RegInfo = MF.getRegInfo();
7218 const X86InstrInfo *TII = STI.getInstrInfo();
7219
7220 unsigned PC;
7221 if (STI.isPICStyleGOT())
7222 PC = RegInfo.createVirtualRegister(&X86::GR32RegClass);
7223 else
7224 PC = GlobalBaseReg;
7225
7226 if (STI.is64Bit()) {
7227 if (TM->getCodeModel() == CodeModel::Medium) {
7228 // In the medium code model, use a RIP-relative LEA to materialize the
7229 // GOT.
7230 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::LEA64r), PC)
7231 .addReg(X86::RIP)
7232 .addImm(0)
7233 .addReg(0)
7234 .addExternalSymbol("_GLOBAL_OFFSET_TABLE_")
7235 .addReg(0);
7236 } else if (TM->getCodeModel() == CodeModel::Large) {
7237 // In the large code model, we are aiming for this code, though the
7238 // register allocation may vary:
7239 // leaq .LN$pb(%rip), %rax
7240 // movq $_GLOBAL_OFFSET_TABLE_ - .LN$pb, %rcx
7241 // addq %rcx, %rax
7242 // RAX now holds address of _GLOBAL_OFFSET_TABLE_.
7243 unsigned PBReg = RegInfo.createVirtualRegister(&X86::GR64RegClass);
7244 unsigned GOTReg =
7245 RegInfo.createVirtualRegister(&X86::GR64RegClass);
7246 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::LEA64r), PBReg)
7247 .addReg(X86::RIP)
7248 .addImm(0)
7249 .addReg(0)
7250 .addSym(MF.getPICBaseSymbol())
7251 .addReg(0);
7252 std::prev(MBBI)->setPreInstrSymbol(MF, MF.getPICBaseSymbol());
7253 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOV64ri), GOTReg)
7254 .addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
7255 X86II::MO_PIC_BASE_OFFSET);
7256 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD64rr), PC)
7257 .addReg(PBReg, RegState::Kill)
7258 .addReg(GOTReg, RegState::Kill);
7259 } else {
7260 llvm_unreachable("unexpected code model")::llvm::llvm_unreachable_internal("unexpected code model", "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/X86/X86InstrInfo.cpp"
, 7260);
7261 }
7262 } else {
7263 // Operand of MovePCtoStack is completely ignored by asm printer. It's
7264 // only used in JIT code emission as displacement to pc.
7265 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
7266
7267 // If we're using vanilla 'GOT' PIC style, we should use relative
7268 // addressing not to pc, but to _GLOBAL_OFFSET_TABLE_ external.
7269 if (STI.isPICStyleGOT()) {
7270 // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel],
7271 // %some_register
7272 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
7273 .addReg(PC)
7274 .addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
7275 X86II::MO_GOT_ABSOLUTE_ADDRESS);
7276 }
7277 }
7278
7279 return true;
7280 }
7281
7282 StringRef getPassName() const override {
7283 return "X86 PIC Global Base Reg Initialization";
7284 }
7285
7286 void getAnalysisUsage(AnalysisUsage &AU) const override {
7287 AU.setPreservesCFG();
7288 MachineFunctionPass::getAnalysisUsage(AU);
7289 }
7290 };
7291}
7292
7293char CGBR::ID = 0;
7294FunctionPass*
7295llvm::createX86GlobalBaseRegPass() { return new CGBR(); }
7296
7297namespace {
7298 struct LDTLSCleanup : public MachineFunctionPass {
7299 static char ID;
7300 LDTLSCleanup() : MachineFunctionPass(ID) {}
7301
7302 bool runOnMachineFunction(MachineFunction &MF) override {
7303 if (skipFunction(MF.getFunction()))
7304 return false;
7305
7306 X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
7307 if (MFI->getNumLocalDynamicTLSAccesses() < 2) {
7308 // No point folding accesses if there isn't at least two.
7309 return false;
7310 }
7311
7312 MachineDominatorTree *DT = &getAnalysis<MachineDominatorTree>();
7313 return VisitNode(DT->getRootNode(), 0);
7314 }
7315
7316 // Visit the dominator subtree rooted at Node in pre-order.
7317 // If TLSBaseAddrReg is non-null, then use that to replace any
7318 // TLS_base_addr instructions. Otherwise, create the register
7319 // when the first such instruction is seen, and then use it
7320 // as we encounter more instructions.
7321 bool VisitNode(MachineDomTreeNode *Node, unsigned TLSBaseAddrReg) {
7322 MachineBasicBlock *BB = Node->getBlock();
7323 bool Changed = false;
7324
7325 // Traverse the current block.
7326 for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I != E;
7327 ++I) {
7328 switch (I->getOpcode()) {
7329 case X86::TLS_base_addr32:
7330 case X86::TLS_base_addr64:
7331 if (TLSBaseAddrReg)
7332 I = ReplaceTLSBaseAddrCall(*I, TLSBaseAddrReg);
7333 else
7334 I = SetRegister(*I, &TLSBaseAddrReg);
7335 Changed = true;
7336 break;
7337 default:
7338 break;
7339 }
7340 }
7341
7342 // Visit the children of this block in the dominator tree.
7343 for (MachineDomTreeNode::iterator I = Node->begin(), E = Node->end();
7344 I != E; ++I) {
7345 Changed |= VisitNode(*I, TLSBaseAddrReg);
7346 }
7347
7348 return Changed;
7349 }
7350
7351 // Replace the TLS_base_addr instruction I with a copy from
7352 // TLSBaseAddrReg, returning the new instruction.
7353 MachineInstr *ReplaceTLSBaseAddrCall(MachineInstr &I,
7354 unsigned TLSBaseAddrReg) {
7355 MachineFunction *MF = I.getParent()->getParent();
7356 const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>();
7357 const bool is64Bit = STI.is64Bit();
7358 const X86InstrInfo *TII = STI.getInstrInfo();
7359
7360 // Insert a Copy from TLSBaseAddrReg to RAX/EAX.
7361 MachineInstr *Copy =
7362 BuildMI(*I.getParent(), I, I.getDebugLoc(),
7363 TII->get(TargetOpcode::COPY), is64Bit ? X86::RAX : X86::EAX)
7364 .addReg(TLSBaseAddrReg);
7365
7366 // Erase the TLS_base_addr instruction.
7367 I.eraseFromParent();
7368
7369 return Copy;
7370 }
7371
7372 // Create a virtual register in *TLSBaseAddrReg, and populate it by
7373 // inserting a copy instruction after I. Returns the new instruction.
7374 MachineInstr *SetRegister(MachineInstr &I, unsigned *TLSBaseAddrReg) {
7375 MachineFunction *MF = I.getParent()->getParent();
7376 const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>();
7377 const bool is64Bit = STI.is64Bit();
7378 const X86InstrInfo *TII = STI.getInstrInfo();
7379
7380 // Create a virtual register for the TLS base address.
7381 MachineRegisterInfo &RegInfo = MF->getRegInfo();
7382 *TLSBaseAddrReg = RegInfo.createVirtualRegister(is64Bit
7383 ? &X86::GR64RegClass
7384 : &X86::GR32RegClass);
7385
7386 // Insert a copy from RAX/EAX to TLSBaseAddrReg.
7387 MachineInstr *Next = I.getNextNode();
7388 MachineInstr *Copy =
7389 BuildMI(*I.getParent(), Next, I.getDebugLoc(),
7390 TII->get(TargetOpcode::COPY), *TLSBaseAddrReg)
7391 .addReg(is64Bit ? X86::RAX : X86::EAX);
7392
7393 return Copy;
7394 }
7395
7396 StringRef getPassName() const override {
7397 return "Local Dynamic TLS Access Clean-up";
7398 }
7399
7400 void getAnalysisUsage(AnalysisUsage &AU) const override {
7401 AU.setPreservesCFG();
7402 AU.addRequired<MachineDominatorTree>();
7403 MachineFunctionPass::getAnalysisUsage(AU);
7404 }
7405 };
7406}
7407
7408char LDTLSCleanup::ID = 0;
7409FunctionPass*
7410llvm::createCleanupLocalDynamicTLSPass() { return new LDTLSCleanup(); }
7411
7412/// Constants defining how certain sequences should be outlined.
7413///
7414/// \p MachineOutlinerDefault implies that the function is called with a call
7415/// instruction, and a return must be emitted for the outlined function frame.
7416///
7417/// That is,
7418///
7419/// I1 OUTLINED_FUNCTION:
7420/// I2 --> call OUTLINED_FUNCTION I1
7421/// I3 I2
7422/// I3
7423/// ret
7424///
7425/// * Call construction overhead: 1 (call instruction)
7426/// * Frame construction overhead: 1 (return instruction)
7427///
7428/// \p MachineOutlinerTailCall implies that the function is being tail called.
7429/// A jump is emitted instead of a call, and the return is already present in
7430/// the outlined sequence. That is,
7431///
7432/// I1 OUTLINED_FUNCTION:
7433/// I2 --> jmp OUTLINED_FUNCTION I1
7434/// ret I2
7435/// ret
7436///
7437/// * Call construction overhead: 1 (jump instruction)
7438/// * Frame construction overhead: 0 (don't need to return)
7439///
7440enum MachineOutlinerClass {
7441 MachineOutlinerDefault,
7442 MachineOutlinerTailCall
7443};
7444
7445outliner::OutlinedFunction X86InstrInfo::getOutliningCandidateInfo(
7446 std::vector<outliner::Candidate> &RepeatedSequenceLocs) const {
7447 unsigned SequenceSize =
7448 std::accumulate(RepeatedSequenceLocs[0].front(),
7449 std::next(RepeatedSequenceLocs[0].back()), 0,
7450 [](unsigned Sum, const MachineInstr &MI) {
7451 // FIXME: x86 doesn't implement getInstSizeInBytes, so
7452 // we can't tell the cost. Just assume each instruction
7453 // is one byte.
7454 if (MI.isDebugInstr() || MI.isKill())
7455 return Sum;
7456 return Sum + 1;
7457 });
7458
7459 // FIXME: Use real size in bytes for call and ret instructions.
7460 if (RepeatedSequenceLocs[0].back()->isTerminator()) {
7461 for (outliner::Candidate &C : RepeatedSequenceLocs)
7462 C.setCallInfo(MachineOutlinerTailCall, 1);
7463
7464 return outliner::OutlinedFunction(RepeatedSequenceLocs, SequenceSize,
7465 0, // Number of bytes to emit frame.
7466 MachineOutlinerTailCall // Type of frame.
7467 );
7468 }
7469
7470 for (outliner::Candidate &C : RepeatedSequenceLocs)
7471 C.setCallInfo(MachineOutlinerDefault, 1);
7472
7473 return outliner::OutlinedFunction(RepeatedSequenceLocs, SequenceSize, 1,
7474 MachineOutlinerDefault);
7475}
7476
7477bool X86InstrInfo::isFunctionSafeToOutlineFrom(MachineFunction &MF,
7478 bool OutlineFromLinkOnceODRs) const {
7479 const Function &F = MF.getFunction();
7480
7481 // Does the function use a red zone? If it does, then we can't risk messing
7482 // with the stack.
7483 if (Subtarget.getFrameLowering()->has128ByteRedZone(MF)) {
7484 // It could have a red zone. If it does, then we don't want to touch it.
7485 const X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
7486 if (!X86FI || X86FI->getUsesRedZone())
7487 return false;
7488 }
7489
7490 // If we *don't* want to outline from things that could potentially be deduped
7491 // then return false.
7492 if (!OutlineFromLinkOnceODRs && F.hasLinkOnceODRLinkage())
7493 return false;
7494
7495 // This function is viable for outlining, so return true.
7496 return true;
7497}
7498
7499outliner::InstrType
7500X86InstrInfo::getOutliningType(MachineBasicBlock::iterator &MIT, unsigned Flags) const {
7501 MachineInstr &MI = *MIT;
7502 // Don't allow debug values to impact outlining type.
7503 if (MI.isDebugInstr() || MI.isIndirectDebugValue())
7504 return outliner::InstrType::Invisible;
7505
7506 // At this point, KILL instructions don't really tell us much so we can go
7507 // ahead and skip over them.
7508 if (MI.isKill())
7509 return outliner::InstrType::Invisible;
7510
7511 // Is this a tail call? If yes, we can outline as a tail call.
7512 if (isTailCall(MI))
7513 return outliner::InstrType::Legal;
7514
7515 // Is this the terminator of a basic block?
7516 if (MI.isTerminator() || MI.isReturn()) {
7517
7518 // Does its parent have any successors in its MachineFunction?
7519 if (MI.getParent()->succ_empty())
7520 return outliner::InstrType::Legal;
7521
7522 // It does, so we can't tail call it.
7523 return outliner::InstrType::Illegal;
7524 }
7525
7526 // Don't outline anything that modifies or reads from the stack pointer.
7527 //
7528 // FIXME: There are instructions which are being manually built without
7529 // explicit uses/defs so we also have to check the MCInstrDesc. We should be
7530 // able to remove the extra checks once those are fixed up. For example,
7531 // sometimes we might get something like %rax = POP64r 1. This won't be
7532 // caught by modifiesRegister or readsRegister even though the instruction
7533 // really ought to be formed so that modifiesRegister/readsRegister would
7534 // catch it.
7535 if (MI.modifiesRegister(X86::RSP, &RI) || MI.readsRegister(X86::RSP, &RI) ||
7536 MI.getDesc().hasImplicitUseOfPhysReg(X86::RSP) ||
7537 MI.getDesc().hasImplicitDefOfPhysReg(X86::RSP))
7538 return outliner::InstrType::Illegal;
7539
7540 // Outlined calls change the instruction pointer, so don't read from it.
7541 if (MI.readsRegister(X86::RIP, &RI) ||
7542 MI.getDesc().hasImplicitUseOfPhysReg(X86::RIP) ||
7543 MI.getDesc().hasImplicitDefOfPhysReg(X86::RIP))
7544 return outliner::InstrType::Illegal;
7545
7546 // Positions can't safely be outlined.
7547 if (MI.isPosition())
7548 return outliner::InstrType::Illegal;
7549
7550 // Make sure none of the operands of this instruction do anything tricky.
7551 for (const MachineOperand &MOP : MI.operands())
7552 if (MOP.isCPI() || MOP.isJTI() || MOP.isCFIIndex() || MOP.isFI() ||
7553 MOP.isTargetIndex())
7554 return outliner::InstrType::Illegal;
7555
7556 return outliner::InstrType::Legal;
7557}
7558
7559void X86InstrInfo::buildOutlinedFrame(MachineBasicBlock &MBB,
7560 MachineFunction &MF,
7561 const outliner::OutlinedFunction &OF)
7562 const {
7563 // If we're a tail call, we already have a return, so don't do anything.
7564 if (OF.FrameConstructionID == MachineOutlinerTailCall)
7565 return;
7566
7567 // We're a normal call, so our sequence doesn't have a return instruction.
7568 // Add it in.
7569 MachineInstr *retq = BuildMI(MF, DebugLoc(), get(X86::RETQ));
7570 MBB.insert(MBB.end(), retq);
7571}
7572
7573MachineBasicBlock::iterator
7574X86InstrInfo::insertOutlinedCall(Module &M, MachineBasicBlock &MBB,
7575 MachineBasicBlock::iterator &It,
7576 MachineFunction &MF,
7577 const outliner::Candidate &C) const {
7578 // Is it a tail call?
7579 if (C.CallConstructionID == MachineOutlinerTailCall) {
7580 // Yes, just insert a JMP.
7581 It = MBB.insert(It,
7582 BuildMI(MF, DebugLoc(), get(X86::TAILJMPd64))
7583 .addGlobalAddress(M.getNamedValue(MF.getName())));
7584 } else {
7585 // No, insert a call.
7586 It = MBB.insert(It,
7587 BuildMI(MF, DebugLoc(), get(X86::CALL64pcrel32))
7588 .addGlobalAddress(M.getNamedValue(MF.getName())));
7589 }
7590
7591 return It;
7592}
7593
7594#define GET_INSTRINFO_HELPERS
7595#include "X86GenInstrInfo.inc"