Bug Summary

File:lib/Target/X86/X86MCInstLower.cpp
Warning:line 781, column 3
Value stored to 'Opc' is never read

Annotated Source Code

1//===-- X86MCInstLower.cpp - Convert X86 MachineInstr to an MCInst --------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains code to lower X86 MachineInstrs to their corresponding
11// MCInst records.
12//
13//===----------------------------------------------------------------------===//
14
15#include "X86AsmPrinter.h"
16#include "X86RegisterInfo.h"
17#include "X86ShuffleDecodeConstantPool.h"
18#include "InstPrinter/X86ATTInstPrinter.h"
19#include "InstPrinter/X86InstComments.h"
20#include "MCTargetDesc/X86BaseInfo.h"
21#include "Utils/X86ShuffleDecode.h"
22#include "llvm/ADT/Optional.h"
23#include "llvm/ADT/SmallString.h"
24#include "llvm/ADT/iterator_range.h"
25#include "llvm/CodeGen/MachineFunction.h"
26#include "llvm/CodeGen/MachineConstantPool.h"
27#include "llvm/CodeGen/MachineOperand.h"
28#include "llvm/CodeGen/MachineModuleInfoImpls.h"
29#include "llvm/CodeGen/StackMaps.h"
30#include "llvm/IR/DataLayout.h"
31#include "llvm/IR/GlobalValue.h"
32#include "llvm/IR/Mangler.h"
33#include "llvm/MC/MCAsmInfo.h"
34#include "llvm/MC/MCCodeEmitter.h"
35#include "llvm/MC/MCContext.h"
36#include "llvm/MC/MCExpr.h"
37#include "llvm/MC/MCFixup.h"
38#include "llvm/MC/MCInst.h"
39#include "llvm/MC/MCInstBuilder.h"
40#include "llvm/MC/MCSection.h"
41#include "llvm/MC/MCStreamer.h"
42#include "llvm/MC/MCSymbol.h"
43#include "llvm/MC/MCSymbolELF.h"
44#include "llvm/MC/MCSectionELF.h"
45#include "llvm/MC/MCSectionMachO.h"
46#include "llvm/Support/TargetRegistry.h"
47#include "llvm/Support/ELF.h"
48#include "llvm/Target/TargetLoweringObjectFile.h"
49
50using namespace llvm;
51
52namespace {
53
54/// X86MCInstLower - This class is used to lower an MachineInstr into an MCInst.
55class X86MCInstLower {
56 MCContext &Ctx;
57 const MachineFunction &MF;
58 const TargetMachine &TM;
59 const MCAsmInfo &MAI;
60 X86AsmPrinter &AsmPrinter;
61public:
62 X86MCInstLower(const MachineFunction &MF, X86AsmPrinter &asmprinter);
63
64 Optional<MCOperand> LowerMachineOperand(const MachineInstr *MI,
65 const MachineOperand &MO) const;
66 void Lower(const MachineInstr *MI, MCInst &OutMI) const;
67
68 MCSymbol *GetSymbolFromOperand(const MachineOperand &MO) const;
69 MCOperand LowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym) const;
70
71private:
72 MachineModuleInfoMachO &getMachOMMI() const;
73};
74
75} // end anonymous namespace
76
77// Emit a minimal sequence of nops spanning NumBytes bytes.
78static void EmitNops(MCStreamer &OS, unsigned NumBytes, bool Is64Bit,
79 const MCSubtargetInfo &STI);
80
81void X86AsmPrinter::StackMapShadowTracker::count(MCInst &Inst,
82 const MCSubtargetInfo &STI,
83 MCCodeEmitter *CodeEmitter) {
84 if (InShadow) {
85 SmallString<256> Code;
86 SmallVector<MCFixup, 4> Fixups;
87 raw_svector_ostream VecOS(Code);
88 CodeEmitter->encodeInstruction(Inst, VecOS, Fixups, STI);
89 CurrentShadowSize += Code.size();
90 if (CurrentShadowSize >= RequiredShadowSize)
91 InShadow = false; // The shadow is big enough. Stop counting.
92 }
93}
94
95void X86AsmPrinter::StackMapShadowTracker::emitShadowPadding(
96 MCStreamer &OutStreamer, const MCSubtargetInfo &STI) {
97 if (InShadow && CurrentShadowSize < RequiredShadowSize) {
98 InShadow = false;
99 EmitNops(OutStreamer, RequiredShadowSize - CurrentShadowSize,
100 MF->getSubtarget<X86Subtarget>().is64Bit(), STI);
101 }
102}
103
104void X86AsmPrinter::EmitAndCountInstruction(MCInst &Inst) {
105 OutStreamer->EmitInstruction(Inst, getSubtargetInfo(), EnablePrintSchedInfo);
106 SMShadowTracker.count(Inst, getSubtargetInfo(), CodeEmitter.get());
107}
108
109X86MCInstLower::X86MCInstLower(const MachineFunction &mf,
110 X86AsmPrinter &asmprinter)
111 : Ctx(mf.getContext()), MF(mf), TM(mf.getTarget()), MAI(*TM.getMCAsmInfo()),
112 AsmPrinter(asmprinter) {}
113
114MachineModuleInfoMachO &X86MCInstLower::getMachOMMI() const {
115 return MF.getMMI().getObjFileInfo<MachineModuleInfoMachO>();
116}
117
118
119/// GetSymbolFromOperand - Lower an MO_GlobalAddress or MO_ExternalSymbol
120/// operand to an MCSymbol.
121MCSymbol *X86MCInstLower::
122GetSymbolFromOperand(const MachineOperand &MO) const {
123 const DataLayout &DL = MF.getDataLayout();
124 assert((MO.isGlobal() || MO.isSymbol() || MO.isMBB()) && "Isn't a symbol reference")(((MO.isGlobal() || MO.isSymbol() || MO.isMBB()) && "Isn't a symbol reference"
) ? static_cast<void> (0) : __assert_fail ("(MO.isGlobal() || MO.isSymbol() || MO.isMBB()) && \"Isn't a symbol reference\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301235/lib/Target/X86/X86MCInstLower.cpp"
, 124, __PRETTY_FUNCTION__))
;
125
126 MCSymbol *Sym = nullptr;
127 SmallString<128> Name;
128 StringRef Suffix;
129
130 switch (MO.getTargetFlags()) {
131 case X86II::MO_DLLIMPORT:
132 // Handle dllimport linkage.
133 Name += "__imp_";
134 break;
135 case X86II::MO_DARWIN_NONLAZY:
136 case X86II::MO_DARWIN_NONLAZY_PIC_BASE:
137 Suffix = "$non_lazy_ptr";
138 break;
139 }
140
141 if (!Suffix.empty())
142 Name += DL.getPrivateGlobalPrefix();
143
144 if (MO.isGlobal()) {
145 const GlobalValue *GV = MO.getGlobal();
146 AsmPrinter.getNameWithPrefix(Name, GV);
147 } else if (MO.isSymbol()) {
148 Mangler::getNameWithPrefix(Name, MO.getSymbolName(), DL);
149 } else if (MO.isMBB()) {
150 assert(Suffix.empty())((Suffix.empty()) ? static_cast<void> (0) : __assert_fail
("Suffix.empty()", "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301235/lib/Target/X86/X86MCInstLower.cpp"
, 150, __PRETTY_FUNCTION__))
;
151 Sym = MO.getMBB()->getSymbol();
152 }
153
154 Name += Suffix;
155 if (!Sym)
156 Sym = Ctx.getOrCreateSymbol(Name);
157
158 // If the target flags on the operand changes the name of the symbol, do that
159 // before we return the symbol.
160 switch (MO.getTargetFlags()) {
161 default: break;
162 case X86II::MO_DARWIN_NONLAZY:
163 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: {
164 MachineModuleInfoImpl::StubValueTy &StubSym =
165 getMachOMMI().getGVStubEntry(Sym);
166 if (!StubSym.getPointer()) {
167 assert(MO.isGlobal() && "Extern symbol not handled yet")((MO.isGlobal() && "Extern symbol not handled yet") ?
static_cast<void> (0) : __assert_fail ("MO.isGlobal() && \"Extern symbol not handled yet\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301235/lib/Target/X86/X86MCInstLower.cpp"
, 167, __PRETTY_FUNCTION__))
;
168 StubSym =
169 MachineModuleInfoImpl::
170 StubValueTy(AsmPrinter.getSymbol(MO.getGlobal()),
171 !MO.getGlobal()->hasInternalLinkage());
172 }
173 break;
174 }
175 }
176
177 return Sym;
178}
179
180MCOperand X86MCInstLower::LowerSymbolOperand(const MachineOperand &MO,
181 MCSymbol *Sym) const {
182 // FIXME: We would like an efficient form for this, so we don't have to do a
183 // lot of extra uniquing.
184 const MCExpr *Expr = nullptr;
185 MCSymbolRefExpr::VariantKind RefKind = MCSymbolRefExpr::VK_None;
186
187 switch (MO.getTargetFlags()) {
188 default: llvm_unreachable("Unknown target flag on GV operand")::llvm::llvm_unreachable_internal("Unknown target flag on GV operand"
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301235/lib/Target/X86/X86MCInstLower.cpp"
, 188)
;
189 case X86II::MO_NO_FLAG: // No flag.
190 // These affect the name of the symbol, not any suffix.
191 case X86II::MO_DARWIN_NONLAZY:
192 case X86II::MO_DLLIMPORT:
193 break;
194
195 case X86II::MO_TLVP: RefKind = MCSymbolRefExpr::VK_TLVP; break;
196 case X86II::MO_TLVP_PIC_BASE:
197 Expr = MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_TLVP, Ctx);
198 // Subtract the pic base.
199 Expr = MCBinaryExpr::createSub(Expr,
200 MCSymbolRefExpr::create(MF.getPICBaseSymbol(),
201 Ctx),
202 Ctx);
203 break;
204 case X86II::MO_SECREL: RefKind = MCSymbolRefExpr::VK_SECREL; break;
205 case X86II::MO_TLSGD: RefKind = MCSymbolRefExpr::VK_TLSGD; break;
206 case X86II::MO_TLSLD: RefKind = MCSymbolRefExpr::VK_TLSLD; break;
207 case X86II::MO_TLSLDM: RefKind = MCSymbolRefExpr::VK_TLSLDM; break;
208 case X86II::MO_GOTTPOFF: RefKind = MCSymbolRefExpr::VK_GOTTPOFF; break;
209 case X86II::MO_INDNTPOFF: RefKind = MCSymbolRefExpr::VK_INDNTPOFF; break;
210 case X86II::MO_TPOFF: RefKind = MCSymbolRefExpr::VK_TPOFF; break;
211 case X86II::MO_DTPOFF: RefKind = MCSymbolRefExpr::VK_DTPOFF; break;
212 case X86II::MO_NTPOFF: RefKind = MCSymbolRefExpr::VK_NTPOFF; break;
213 case X86II::MO_GOTNTPOFF: RefKind = MCSymbolRefExpr::VK_GOTNTPOFF; break;
214 case X86II::MO_GOTPCREL: RefKind = MCSymbolRefExpr::VK_GOTPCREL; break;
215 case X86II::MO_GOT: RefKind = MCSymbolRefExpr::VK_GOT; break;
216 case X86II::MO_GOTOFF: RefKind = MCSymbolRefExpr::VK_GOTOFF; break;
217 case X86II::MO_PLT: RefKind = MCSymbolRefExpr::VK_PLT; break;
218 case X86II::MO_ABS8: RefKind = MCSymbolRefExpr::VK_X86_ABS8; break;
219 case X86II::MO_PIC_BASE_OFFSET:
220 case X86II::MO_DARWIN_NONLAZY_PIC_BASE:
221 Expr = MCSymbolRefExpr::create(Sym, Ctx);
222 // Subtract the pic base.
223 Expr = MCBinaryExpr::createSub(Expr,
224 MCSymbolRefExpr::create(MF.getPICBaseSymbol(), Ctx),
225 Ctx);
226 if (MO.isJTI()) {
227 assert(MAI.doesSetDirectiveSuppressReloc())((MAI.doesSetDirectiveSuppressReloc()) ? static_cast<void>
(0) : __assert_fail ("MAI.doesSetDirectiveSuppressReloc()", "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301235/lib/Target/X86/X86MCInstLower.cpp"
, 227, __PRETTY_FUNCTION__))
;
228 // If .set directive is supported, use it to reduce the number of
229 // relocations the assembler will generate for differences between
230 // local labels. This is only safe when the symbols are in the same
231 // section so we are restricting it to jumptable references.
232 MCSymbol *Label = Ctx.createTempSymbol();
233 AsmPrinter.OutStreamer->EmitAssignment(Label, Expr);
234 Expr = MCSymbolRefExpr::create(Label, Ctx);
235 }
236 break;
237 }
238
239 if (!Expr)
240 Expr = MCSymbolRefExpr::create(Sym, RefKind, Ctx);
241
242 if (!MO.isJTI() && !MO.isMBB() && MO.getOffset())
243 Expr = MCBinaryExpr::createAdd(Expr,
244 MCConstantExpr::create(MO.getOffset(), Ctx),
245 Ctx);
246 return MCOperand::createExpr(Expr);
247}
248
249
250/// \brief Simplify FOO $imm, %{al,ax,eax,rax} to FOO $imm, for instruction with
251/// a short fixed-register form.
252static void SimplifyShortImmForm(MCInst &Inst, unsigned Opcode) {
253 unsigned ImmOp = Inst.getNumOperands() - 1;
254 assert(Inst.getOperand(0).isReg() &&((Inst.getOperand(0).isReg() && (Inst.getOperand(ImmOp
).isImm() || Inst.getOperand(ImmOp).isExpr()) && ((Inst
.getNumOperands() == 3 && Inst.getOperand(1).isReg() &&
Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) ||
Inst.getNumOperands() == 2) && "Unexpected instruction!"
) ? static_cast<void> (0) : __assert_fail ("Inst.getOperand(0).isReg() && (Inst.getOperand(ImmOp).isImm() || Inst.getOperand(ImmOp).isExpr()) && ((Inst.getNumOperands() == 3 && Inst.getOperand(1).isReg() && Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) || Inst.getNumOperands() == 2) && \"Unexpected instruction!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301235/lib/Target/X86/X86MCInstLower.cpp"
, 258, __PRETTY_FUNCTION__))
255 (Inst.getOperand(ImmOp).isImm() || Inst.getOperand(ImmOp).isExpr()) &&((Inst.getOperand(0).isReg() && (Inst.getOperand(ImmOp
).isImm() || Inst.getOperand(ImmOp).isExpr()) && ((Inst
.getNumOperands() == 3 && Inst.getOperand(1).isReg() &&
Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) ||
Inst.getNumOperands() == 2) && "Unexpected instruction!"
) ? static_cast<void> (0) : __assert_fail ("Inst.getOperand(0).isReg() && (Inst.getOperand(ImmOp).isImm() || Inst.getOperand(ImmOp).isExpr()) && ((Inst.getNumOperands() == 3 && Inst.getOperand(1).isReg() && Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) || Inst.getNumOperands() == 2) && \"Unexpected instruction!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301235/lib/Target/X86/X86MCInstLower.cpp"
, 258, __PRETTY_FUNCTION__))
256 ((Inst.getNumOperands() == 3 && Inst.getOperand(1).isReg() &&((Inst.getOperand(0).isReg() && (Inst.getOperand(ImmOp
).isImm() || Inst.getOperand(ImmOp).isExpr()) && ((Inst
.getNumOperands() == 3 && Inst.getOperand(1).isReg() &&
Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) ||
Inst.getNumOperands() == 2) && "Unexpected instruction!"
) ? static_cast<void> (0) : __assert_fail ("Inst.getOperand(0).isReg() && (Inst.getOperand(ImmOp).isImm() || Inst.getOperand(ImmOp).isExpr()) && ((Inst.getNumOperands() == 3 && Inst.getOperand(1).isReg() && Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) || Inst.getNumOperands() == 2) && \"Unexpected instruction!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301235/lib/Target/X86/X86MCInstLower.cpp"
, 258, __PRETTY_FUNCTION__))
257 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) ||((Inst.getOperand(0).isReg() && (Inst.getOperand(ImmOp
).isImm() || Inst.getOperand(ImmOp).isExpr()) && ((Inst
.getNumOperands() == 3 && Inst.getOperand(1).isReg() &&
Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) ||
Inst.getNumOperands() == 2) && "Unexpected instruction!"
) ? static_cast<void> (0) : __assert_fail ("Inst.getOperand(0).isReg() && (Inst.getOperand(ImmOp).isImm() || Inst.getOperand(ImmOp).isExpr()) && ((Inst.getNumOperands() == 3 && Inst.getOperand(1).isReg() && Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) || Inst.getNumOperands() == 2) && \"Unexpected instruction!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301235/lib/Target/X86/X86MCInstLower.cpp"
, 258, __PRETTY_FUNCTION__))
258 Inst.getNumOperands() == 2) && "Unexpected instruction!")((Inst.getOperand(0).isReg() && (Inst.getOperand(ImmOp
).isImm() || Inst.getOperand(ImmOp).isExpr()) && ((Inst
.getNumOperands() == 3 && Inst.getOperand(1).isReg() &&
Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) ||
Inst.getNumOperands() == 2) && "Unexpected instruction!"
) ? static_cast<void> (0) : __assert_fail ("Inst.getOperand(0).isReg() && (Inst.getOperand(ImmOp).isImm() || Inst.getOperand(ImmOp).isExpr()) && ((Inst.getNumOperands() == 3 && Inst.getOperand(1).isReg() && Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) || Inst.getNumOperands() == 2) && \"Unexpected instruction!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301235/lib/Target/X86/X86MCInstLower.cpp"
, 258, __PRETTY_FUNCTION__))
;
259
260 // Check whether the destination register can be fixed.
261 unsigned Reg = Inst.getOperand(0).getReg();
262 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
263 return;
264
265 // If so, rewrite the instruction.
266 MCOperand Saved = Inst.getOperand(ImmOp);
267 Inst = MCInst();
268 Inst.setOpcode(Opcode);
269 Inst.addOperand(Saved);
270}
271
272/// \brief If a movsx instruction has a shorter encoding for the used register
273/// simplify the instruction to use it instead.
274static void SimplifyMOVSX(MCInst &Inst) {
275 unsigned NewOpcode = 0;
276 unsigned Op0 = Inst.getOperand(0).getReg(), Op1 = Inst.getOperand(1).getReg();
277 switch (Inst.getOpcode()) {
278 default:
279 llvm_unreachable("Unexpected instruction!")::llvm::llvm_unreachable_internal("Unexpected instruction!", "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301235/lib/Target/X86/X86MCInstLower.cpp"
, 279)
;
280 case X86::MOVSX16rr8: // movsbw %al, %ax --> cbtw
281 if (Op0 == X86::AX && Op1 == X86::AL)
282 NewOpcode = X86::CBW;
283 break;
284 case X86::MOVSX32rr16: // movswl %ax, %eax --> cwtl
285 if (Op0 == X86::EAX && Op1 == X86::AX)
286 NewOpcode = X86::CWDE;
287 break;
288 case X86::MOVSX64rr32: // movslq %eax, %rax --> cltq
289 if (Op0 == X86::RAX && Op1 == X86::EAX)
290 NewOpcode = X86::CDQE;
291 break;
292 }
293
294 if (NewOpcode != 0) {
295 Inst = MCInst();
296 Inst.setOpcode(NewOpcode);
297 }
298}
299
300/// \brief Simplify things like MOV32rm to MOV32o32a.
301static void SimplifyShortMoveForm(X86AsmPrinter &Printer, MCInst &Inst,
302 unsigned Opcode) {
303 // Don't make these simplifications in 64-bit mode; other assemblers don't
304 // perform them because they make the code larger.
305 if (Printer.getSubtarget().is64Bit())
306 return;
307
308 bool IsStore = Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg();
309 unsigned AddrBase = IsStore;
310 unsigned RegOp = IsStore ? 0 : 5;
311 unsigned AddrOp = AddrBase + 3;
312 assert(Inst.getNumOperands() == 6 && Inst.getOperand(RegOp).isReg() &&((Inst.getNumOperands() == 6 && Inst.getOperand(RegOp
).isReg() && Inst.getOperand(AddrBase + X86::AddrBaseReg
).isReg() && Inst.getOperand(AddrBase + X86::AddrScaleAmt
).isImm() && Inst.getOperand(AddrBase + X86::AddrIndexReg
).isReg() && Inst.getOperand(AddrBase + X86::AddrSegmentReg
).isReg() && (Inst.getOperand(AddrOp).isExpr() || Inst
.getOperand(AddrOp).isImm()) && "Unexpected instruction!"
) ? static_cast<void> (0) : __assert_fail ("Inst.getNumOperands() == 6 && Inst.getOperand(RegOp).isReg() && Inst.getOperand(AddrBase + X86::AddrBaseReg).isReg() && Inst.getOperand(AddrBase + X86::AddrScaleAmt).isImm() && Inst.getOperand(AddrBase + X86::AddrIndexReg).isReg() && Inst.getOperand(AddrBase + X86::AddrSegmentReg).isReg() && (Inst.getOperand(AddrOp).isExpr() || Inst.getOperand(AddrOp).isImm()) && \"Unexpected instruction!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301235/lib/Target/X86/X86MCInstLower.cpp"
, 319, __PRETTY_FUNCTION__))
313 Inst.getOperand(AddrBase + X86::AddrBaseReg).isReg() &&((Inst.getNumOperands() == 6 && Inst.getOperand(RegOp
).isReg() && Inst.getOperand(AddrBase + X86::AddrBaseReg
).isReg() && Inst.getOperand(AddrBase + X86::AddrScaleAmt
).isImm() && Inst.getOperand(AddrBase + X86::AddrIndexReg
).isReg() && Inst.getOperand(AddrBase + X86::AddrSegmentReg
).isReg() && (Inst.getOperand(AddrOp).isExpr() || Inst
.getOperand(AddrOp).isImm()) && "Unexpected instruction!"
) ? static_cast<void> (0) : __assert_fail ("Inst.getNumOperands() == 6 && Inst.getOperand(RegOp).isReg() && Inst.getOperand(AddrBase + X86::AddrBaseReg).isReg() && Inst.getOperand(AddrBase + X86::AddrScaleAmt).isImm() && Inst.getOperand(AddrBase + X86::AddrIndexReg).isReg() && Inst.getOperand(AddrBase + X86::AddrSegmentReg).isReg() && (Inst.getOperand(AddrOp).isExpr() || Inst.getOperand(AddrOp).isImm()) && \"Unexpected instruction!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301235/lib/Target/X86/X86MCInstLower.cpp"
, 319, __PRETTY_FUNCTION__))
314 Inst.getOperand(AddrBase + X86::AddrScaleAmt).isImm() &&((Inst.getNumOperands() == 6 && Inst.getOperand(RegOp
).isReg() && Inst.getOperand(AddrBase + X86::AddrBaseReg
).isReg() && Inst.getOperand(AddrBase + X86::AddrScaleAmt
).isImm() && Inst.getOperand(AddrBase + X86::AddrIndexReg
).isReg() && Inst.getOperand(AddrBase + X86::AddrSegmentReg
).isReg() && (Inst.getOperand(AddrOp).isExpr() || Inst
.getOperand(AddrOp).isImm()) && "Unexpected instruction!"
) ? static_cast<void> (0) : __assert_fail ("Inst.getNumOperands() == 6 && Inst.getOperand(RegOp).isReg() && Inst.getOperand(AddrBase + X86::AddrBaseReg).isReg() && Inst.getOperand(AddrBase + X86::AddrScaleAmt).isImm() && Inst.getOperand(AddrBase + X86::AddrIndexReg).isReg() && Inst.getOperand(AddrBase + X86::AddrSegmentReg).isReg() && (Inst.getOperand(AddrOp).isExpr() || Inst.getOperand(AddrOp).isImm()) && \"Unexpected instruction!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301235/lib/Target/X86/X86MCInstLower.cpp"
, 319, __PRETTY_FUNCTION__))
315 Inst.getOperand(AddrBase + X86::AddrIndexReg).isReg() &&((Inst.getNumOperands() == 6 && Inst.getOperand(RegOp
).isReg() && Inst.getOperand(AddrBase + X86::AddrBaseReg
).isReg() && Inst.getOperand(AddrBase + X86::AddrScaleAmt
).isImm() && Inst.getOperand(AddrBase + X86::AddrIndexReg
).isReg() && Inst.getOperand(AddrBase + X86::AddrSegmentReg
).isReg() && (Inst.getOperand(AddrOp).isExpr() || Inst
.getOperand(AddrOp).isImm()) && "Unexpected instruction!"
) ? static_cast<void> (0) : __assert_fail ("Inst.getNumOperands() == 6 && Inst.getOperand(RegOp).isReg() && Inst.getOperand(AddrBase + X86::AddrBaseReg).isReg() && Inst.getOperand(AddrBase + X86::AddrScaleAmt).isImm() && Inst.getOperand(AddrBase + X86::AddrIndexReg).isReg() && Inst.getOperand(AddrBase + X86::AddrSegmentReg).isReg() && (Inst.getOperand(AddrOp).isExpr() || Inst.getOperand(AddrOp).isImm()) && \"Unexpected instruction!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301235/lib/Target/X86/X86MCInstLower.cpp"
, 319, __PRETTY_FUNCTION__))
316 Inst.getOperand(AddrBase + X86::AddrSegmentReg).isReg() &&((Inst.getNumOperands() == 6 && Inst.getOperand(RegOp
).isReg() && Inst.getOperand(AddrBase + X86::AddrBaseReg
).isReg() && Inst.getOperand(AddrBase + X86::AddrScaleAmt
).isImm() && Inst.getOperand(AddrBase + X86::AddrIndexReg
).isReg() && Inst.getOperand(AddrBase + X86::AddrSegmentReg
).isReg() && (Inst.getOperand(AddrOp).isExpr() || Inst
.getOperand(AddrOp).isImm()) && "Unexpected instruction!"
) ? static_cast<void> (0) : __assert_fail ("Inst.getNumOperands() == 6 && Inst.getOperand(RegOp).isReg() && Inst.getOperand(AddrBase + X86::AddrBaseReg).isReg() && Inst.getOperand(AddrBase + X86::AddrScaleAmt).isImm() && Inst.getOperand(AddrBase + X86::AddrIndexReg).isReg() && Inst.getOperand(AddrBase + X86::AddrSegmentReg).isReg() && (Inst.getOperand(AddrOp).isExpr() || Inst.getOperand(AddrOp).isImm()) && \"Unexpected instruction!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301235/lib/Target/X86/X86MCInstLower.cpp"
, 319, __PRETTY_FUNCTION__))
317 (Inst.getOperand(AddrOp).isExpr() ||((Inst.getNumOperands() == 6 && Inst.getOperand(RegOp
).isReg() && Inst.getOperand(AddrBase + X86::AddrBaseReg
).isReg() && Inst.getOperand(AddrBase + X86::AddrScaleAmt
).isImm() && Inst.getOperand(AddrBase + X86::AddrIndexReg
).isReg() && Inst.getOperand(AddrBase + X86::AddrSegmentReg
).isReg() && (Inst.getOperand(AddrOp).isExpr() || Inst
.getOperand(AddrOp).isImm()) && "Unexpected instruction!"
) ? static_cast<void> (0) : __assert_fail ("Inst.getNumOperands() == 6 && Inst.getOperand(RegOp).isReg() && Inst.getOperand(AddrBase + X86::AddrBaseReg).isReg() && Inst.getOperand(AddrBase + X86::AddrScaleAmt).isImm() && Inst.getOperand(AddrBase + X86::AddrIndexReg).isReg() && Inst.getOperand(AddrBase + X86::AddrSegmentReg).isReg() && (Inst.getOperand(AddrOp).isExpr() || Inst.getOperand(AddrOp).isImm()) && \"Unexpected instruction!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301235/lib/Target/X86/X86MCInstLower.cpp"
, 319, __PRETTY_FUNCTION__))
318 Inst.getOperand(AddrOp).isImm()) &&((Inst.getNumOperands() == 6 && Inst.getOperand(RegOp
).isReg() && Inst.getOperand(AddrBase + X86::AddrBaseReg
).isReg() && Inst.getOperand(AddrBase + X86::AddrScaleAmt
).isImm() && Inst.getOperand(AddrBase + X86::AddrIndexReg
).isReg() && Inst.getOperand(AddrBase + X86::AddrSegmentReg
).isReg() && (Inst.getOperand(AddrOp).isExpr() || Inst
.getOperand(AddrOp).isImm()) && "Unexpected instruction!"
) ? static_cast<void> (0) : __assert_fail ("Inst.getNumOperands() == 6 && Inst.getOperand(RegOp).isReg() && Inst.getOperand(AddrBase + X86::AddrBaseReg).isReg() && Inst.getOperand(AddrBase + X86::AddrScaleAmt).isImm() && Inst.getOperand(AddrBase + X86::AddrIndexReg).isReg() && Inst.getOperand(AddrBase + X86::AddrSegmentReg).isReg() && (Inst.getOperand(AddrOp).isExpr() || Inst.getOperand(AddrOp).isImm()) && \"Unexpected instruction!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301235/lib/Target/X86/X86MCInstLower.cpp"
, 319, __PRETTY_FUNCTION__))
319 "Unexpected instruction!")((Inst.getNumOperands() == 6 && Inst.getOperand(RegOp
).isReg() && Inst.getOperand(AddrBase + X86::AddrBaseReg
).isReg() && Inst.getOperand(AddrBase + X86::AddrScaleAmt
).isImm() && Inst.getOperand(AddrBase + X86::AddrIndexReg
).isReg() && Inst.getOperand(AddrBase + X86::AddrSegmentReg
).isReg() && (Inst.getOperand(AddrOp).isExpr() || Inst
.getOperand(AddrOp).isImm()) && "Unexpected instruction!"
) ? static_cast<void> (0) : __assert_fail ("Inst.getNumOperands() == 6 && Inst.getOperand(RegOp).isReg() && Inst.getOperand(AddrBase + X86::AddrBaseReg).isReg() && Inst.getOperand(AddrBase + X86::AddrScaleAmt).isImm() && Inst.getOperand(AddrBase + X86::AddrIndexReg).isReg() && Inst.getOperand(AddrBase + X86::AddrSegmentReg).isReg() && (Inst.getOperand(AddrOp).isExpr() || Inst.getOperand(AddrOp).isImm()) && \"Unexpected instruction!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301235/lib/Target/X86/X86MCInstLower.cpp"
, 319, __PRETTY_FUNCTION__))
;
320
321 // Check whether the destination register can be fixed.
322 unsigned Reg = Inst.getOperand(RegOp).getReg();
323 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
324 return;
325
326 // Check whether this is an absolute address.
327 // FIXME: We know TLVP symbol refs aren't, but there should be a better way
328 // to do this here.
329 bool Absolute = true;
330 if (Inst.getOperand(AddrOp).isExpr()) {
331 const MCExpr *MCE = Inst.getOperand(AddrOp).getExpr();
332 if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(MCE))
333 if (SRE->getKind() == MCSymbolRefExpr::VK_TLVP)
334 Absolute = false;
335 }
336
337 if (Absolute &&
338 (Inst.getOperand(AddrBase + X86::AddrBaseReg).getReg() != 0 ||
339 Inst.getOperand(AddrBase + X86::AddrScaleAmt).getImm() != 1 ||
340 Inst.getOperand(AddrBase + X86::AddrIndexReg).getReg() != 0))
341 return;
342
343 // If so, rewrite the instruction.
344 MCOperand Saved = Inst.getOperand(AddrOp);
345 MCOperand Seg = Inst.getOperand(AddrBase + X86::AddrSegmentReg);
346 Inst = MCInst();
347 Inst.setOpcode(Opcode);
348 Inst.addOperand(Saved);
349 Inst.addOperand(Seg);
350}
351
352static unsigned getRetOpcode(const X86Subtarget &Subtarget) {
353 return Subtarget.is64Bit() ? X86::RETQ : X86::RETL;
354}
355
356Optional<MCOperand>
357X86MCInstLower::LowerMachineOperand(const MachineInstr *MI,
358 const MachineOperand &MO) const {
359 switch (MO.getType()) {
360 default:
361 MI->print(errs());
362 llvm_unreachable("unknown operand type")::llvm::llvm_unreachable_internal("unknown operand type", "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301235/lib/Target/X86/X86MCInstLower.cpp"
, 362)
;
363 case MachineOperand::MO_Register:
364 // Ignore all implicit register operands.
365 if (MO.isImplicit())
366 return None;
367 return MCOperand::createReg(MO.getReg());
368 case MachineOperand::MO_Immediate:
369 return MCOperand::createImm(MO.getImm());
370 case MachineOperand::MO_MachineBasicBlock:
371 case MachineOperand::MO_GlobalAddress:
372 case MachineOperand::MO_ExternalSymbol:
373 return LowerSymbolOperand(MO, GetSymbolFromOperand(MO));
374 case MachineOperand::MO_MCSymbol:
375 return LowerSymbolOperand(MO, MO.getMCSymbol());
376 case MachineOperand::MO_JumpTableIndex:
377 return LowerSymbolOperand(MO, AsmPrinter.GetJTISymbol(MO.getIndex()));
378 case MachineOperand::MO_ConstantPoolIndex:
379 return LowerSymbolOperand(MO, AsmPrinter.GetCPISymbol(MO.getIndex()));
380 case MachineOperand::MO_BlockAddress:
381 return LowerSymbolOperand(
382 MO, AsmPrinter.GetBlockAddressSymbol(MO.getBlockAddress()));
383 case MachineOperand::MO_RegisterMask:
384 // Ignore call clobbers.
385 return None;
386 }
387}
388
389void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
390 OutMI.setOpcode(MI->getOpcode());
391
392 for (const MachineOperand &MO : MI->operands())
393 if (auto MaybeMCOp = LowerMachineOperand(MI, MO))
394 OutMI.addOperand(MaybeMCOp.getValue());
395
396 // Handle a few special cases to eliminate operand modifiers.
397ReSimplify:
398 switch (OutMI.getOpcode()) {
399 case X86::LEA64_32r:
400 case X86::LEA64r:
401 case X86::LEA16r:
402 case X86::LEA32r:
403 // LEA should have a segment register, but it must be empty.
404 assert(OutMI.getNumOperands() == 1+X86::AddrNumOperands &&((OutMI.getNumOperands() == 1+X86::AddrNumOperands &&
"Unexpected # of LEA operands") ? static_cast<void> (0
) : __assert_fail ("OutMI.getNumOperands() == 1+X86::AddrNumOperands && \"Unexpected # of LEA operands\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301235/lib/Target/X86/X86MCInstLower.cpp"
, 405, __PRETTY_FUNCTION__))
405 "Unexpected # of LEA operands")((OutMI.getNumOperands() == 1+X86::AddrNumOperands &&
"Unexpected # of LEA operands") ? static_cast<void> (0
) : __assert_fail ("OutMI.getNumOperands() == 1+X86::AddrNumOperands && \"Unexpected # of LEA operands\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301235/lib/Target/X86/X86MCInstLower.cpp"
, 405, __PRETTY_FUNCTION__))
;
406 assert(OutMI.getOperand(1+X86::AddrSegmentReg).getReg() == 0 &&((OutMI.getOperand(1+X86::AddrSegmentReg).getReg() == 0 &&
"LEA has segment specified!") ? static_cast<void> (0) :
__assert_fail ("OutMI.getOperand(1+X86::AddrSegmentReg).getReg() == 0 && \"LEA has segment specified!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301235/lib/Target/X86/X86MCInstLower.cpp"
, 407, __PRETTY_FUNCTION__))
407 "LEA has segment specified!")((OutMI.getOperand(1+X86::AddrSegmentReg).getReg() == 0 &&
"LEA has segment specified!") ? static_cast<void> (0) :
__assert_fail ("OutMI.getOperand(1+X86::AddrSegmentReg).getReg() == 0 && \"LEA has segment specified!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301235/lib/Target/X86/X86MCInstLower.cpp"
, 407, __PRETTY_FUNCTION__))
;
408 break;
409
410 // Commute operands to get a smaller encoding by using VEX.R instead of VEX.B
411 // if one of the registers is extended, but other isn't.
412 case X86::VMOVZPQILo2PQIrr:
413 case X86::VMOVAPDrr:
414 case X86::VMOVAPDYrr:
415 case X86::VMOVAPSrr:
416 case X86::VMOVAPSYrr:
417 case X86::VMOVDQArr:
418 case X86::VMOVDQAYrr:
419 case X86::VMOVDQUrr:
420 case X86::VMOVDQUYrr:
421 case X86::VMOVUPDrr:
422 case X86::VMOVUPDYrr:
423 case X86::VMOVUPSrr:
424 case X86::VMOVUPSYrr: {
425 if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(0).getReg()) &&
426 X86II::isX86_64ExtendedReg(OutMI.getOperand(1).getReg())) {
427 unsigned NewOpc;
428 switch (OutMI.getOpcode()) {
429 default: llvm_unreachable("Invalid opcode")::llvm::llvm_unreachable_internal("Invalid opcode", "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301235/lib/Target/X86/X86MCInstLower.cpp"
, 429)
;
430 case X86::VMOVZPQILo2PQIrr: NewOpc = X86::VMOVPQI2QIrr; break;
431 case X86::VMOVAPDrr: NewOpc = X86::VMOVAPDrr_REV; break;
432 case X86::VMOVAPDYrr: NewOpc = X86::VMOVAPDYrr_REV; break;
433 case X86::VMOVAPSrr: NewOpc = X86::VMOVAPSrr_REV; break;
434 case X86::VMOVAPSYrr: NewOpc = X86::VMOVAPSYrr_REV; break;
435 case X86::VMOVDQArr: NewOpc = X86::VMOVDQArr_REV; break;
436 case X86::VMOVDQAYrr: NewOpc = X86::VMOVDQAYrr_REV; break;
437 case X86::VMOVDQUrr: NewOpc = X86::VMOVDQUrr_REV; break;
438 case X86::VMOVDQUYrr: NewOpc = X86::VMOVDQUYrr_REV; break;
439 case X86::VMOVUPDrr: NewOpc = X86::VMOVUPDrr_REV; break;
440 case X86::VMOVUPDYrr: NewOpc = X86::VMOVUPDYrr_REV; break;
441 case X86::VMOVUPSrr: NewOpc = X86::VMOVUPSrr_REV; break;
442 case X86::VMOVUPSYrr: NewOpc = X86::VMOVUPSYrr_REV; break;
443 }
444 OutMI.setOpcode(NewOpc);
445 }
446 break;
447 }
448 case X86::VMOVSDrr:
449 case X86::VMOVSSrr: {
450 if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(0).getReg()) &&
451 X86II::isX86_64ExtendedReg(OutMI.getOperand(2).getReg())) {
452 unsigned NewOpc;
453 switch (OutMI.getOpcode()) {
454 default: llvm_unreachable("Invalid opcode")::llvm::llvm_unreachable_internal("Invalid opcode", "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301235/lib/Target/X86/X86MCInstLower.cpp"
, 454)
;
455 case X86::VMOVSDrr: NewOpc = X86::VMOVSDrr_REV; break;
456 case X86::VMOVSSrr: NewOpc = X86::VMOVSSrr_REV; break;
457 }
458 OutMI.setOpcode(NewOpc);
459 }
460 break;
461 }
462
463 // TAILJMPr64, CALL64r, CALL64pcrel32 - These instructions have register
464 // inputs modeled as normal uses instead of implicit uses. As such, truncate
465 // off all but the first operand (the callee). FIXME: Change isel.
466 case X86::TAILJMPr64:
467 case X86::TAILJMPr64_REX:
468 case X86::CALL64r:
469 case X86::CALL64pcrel32: {
470 unsigned Opcode = OutMI.getOpcode();
471 MCOperand Saved = OutMI.getOperand(0);
472 OutMI = MCInst();
473 OutMI.setOpcode(Opcode);
474 OutMI.addOperand(Saved);
475 break;
476 }
477
478 case X86::EH_RETURN:
479 case X86::EH_RETURN64: {
480 OutMI = MCInst();
481 OutMI.setOpcode(getRetOpcode(AsmPrinter.getSubtarget()));
482 break;
483 }
484
485 case X86::CLEANUPRET: {
486 // Replace CATCHRET with the appropriate RET.
487 OutMI = MCInst();
488 OutMI.setOpcode(getRetOpcode(AsmPrinter.getSubtarget()));
489 break;
490 }
491
492 case X86::CATCHRET: {
493 // Replace CATCHRET with the appropriate RET.
494 const X86Subtarget &Subtarget = AsmPrinter.getSubtarget();
495 unsigned ReturnReg = Subtarget.is64Bit() ? X86::RAX : X86::EAX;
496 OutMI = MCInst();
497 OutMI.setOpcode(getRetOpcode(Subtarget));
498 OutMI.addOperand(MCOperand::createReg(ReturnReg));
499 break;
500 }
501
502 // TAILJMPd, TAILJMPd64, TailJMPd_cc - Lower to the correct jump instruction.
503 { unsigned Opcode;
504 case X86::TAILJMPr: Opcode = X86::JMP32r; goto SetTailJmpOpcode;
505 case X86::TAILJMPd:
506 case X86::TAILJMPd64: Opcode = X86::JMP_1; goto SetTailJmpOpcode;
507 case X86::TAILJMPd_CC:
508 case X86::TAILJMPd64_CC:
509 Opcode = X86::GetCondBranchFromCond(
510 static_cast<X86::CondCode>(MI->getOperand(1).getImm()));
511 goto SetTailJmpOpcode;
512
513 SetTailJmpOpcode:
514 MCOperand Saved = OutMI.getOperand(0);
515 OutMI = MCInst();
516 OutMI.setOpcode(Opcode);
517 OutMI.addOperand(Saved);
518 break;
519 }
520
521 case X86::DEC16r:
522 case X86::DEC32r:
523 case X86::INC16r:
524 case X86::INC32r:
525 // If we aren't in 64-bit mode we can use the 1-byte inc/dec instructions.
526 if (!AsmPrinter.getSubtarget().is64Bit()) {
527 unsigned Opcode;
528 switch (OutMI.getOpcode()) {
529 default: llvm_unreachable("Invalid opcode")::llvm::llvm_unreachable_internal("Invalid opcode", "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301235/lib/Target/X86/X86MCInstLower.cpp"
, 529)
;
530 case X86::DEC16r: Opcode = X86::DEC16r_alt; break;
531 case X86::DEC32r: Opcode = X86::DEC32r_alt; break;
532 case X86::INC16r: Opcode = X86::INC16r_alt; break;
533 case X86::INC32r: Opcode = X86::INC32r_alt; break;
534 }
535 OutMI.setOpcode(Opcode);
536 }
537 break;
538
539 // These are pseudo-ops for OR to help with the OR->ADD transformation. We do
540 // this with an ugly goto in case the resultant OR uses EAX and needs the
541 // short form.
542 case X86::ADD16rr_DB: OutMI.setOpcode(X86::OR16rr); goto ReSimplify;
543 case X86::ADD32rr_DB: OutMI.setOpcode(X86::OR32rr); goto ReSimplify;
544 case X86::ADD64rr_DB: OutMI.setOpcode(X86::OR64rr); goto ReSimplify;
545 case X86::ADD16ri_DB: OutMI.setOpcode(X86::OR16ri); goto ReSimplify;
546 case X86::ADD32ri_DB: OutMI.setOpcode(X86::OR32ri); goto ReSimplify;
547 case X86::ADD64ri32_DB: OutMI.setOpcode(X86::OR64ri32); goto ReSimplify;
548 case X86::ADD16ri8_DB: OutMI.setOpcode(X86::OR16ri8); goto ReSimplify;
549 case X86::ADD32ri8_DB: OutMI.setOpcode(X86::OR32ri8); goto ReSimplify;
550 case X86::ADD64ri8_DB: OutMI.setOpcode(X86::OR64ri8); goto ReSimplify;
551
552 // Atomic load and store require a separate pseudo-inst because Acquire
553 // implies mayStore and Release implies mayLoad; fix these to regular MOV
554 // instructions here
555 case X86::ACQUIRE_MOV8rm: OutMI.setOpcode(X86::MOV8rm); goto ReSimplify;
556 case X86::ACQUIRE_MOV16rm: OutMI.setOpcode(X86::MOV16rm); goto ReSimplify;
557 case X86::ACQUIRE_MOV32rm: OutMI.setOpcode(X86::MOV32rm); goto ReSimplify;
558 case X86::ACQUIRE_MOV64rm: OutMI.setOpcode(X86::MOV64rm); goto ReSimplify;
559 case X86::RELEASE_MOV8mr: OutMI.setOpcode(X86::MOV8mr); goto ReSimplify;
560 case X86::RELEASE_MOV16mr: OutMI.setOpcode(X86::MOV16mr); goto ReSimplify;
561 case X86::RELEASE_MOV32mr: OutMI.setOpcode(X86::MOV32mr); goto ReSimplify;
562 case X86::RELEASE_MOV64mr: OutMI.setOpcode(X86::MOV64mr); goto ReSimplify;
563 case X86::RELEASE_MOV8mi: OutMI.setOpcode(X86::MOV8mi); goto ReSimplify;
564 case X86::RELEASE_MOV16mi: OutMI.setOpcode(X86::MOV16mi); goto ReSimplify;
565 case X86::RELEASE_MOV32mi: OutMI.setOpcode(X86::MOV32mi); goto ReSimplify;
566 case X86::RELEASE_MOV64mi32: OutMI.setOpcode(X86::MOV64mi32); goto ReSimplify;
567 case X86::RELEASE_ADD8mi: OutMI.setOpcode(X86::ADD8mi); goto ReSimplify;
568 case X86::RELEASE_ADD8mr: OutMI.setOpcode(X86::ADD8mr); goto ReSimplify;
569 case X86::RELEASE_ADD32mi: OutMI.setOpcode(X86::ADD32mi); goto ReSimplify;
570 case X86::RELEASE_ADD32mr: OutMI.setOpcode(X86::ADD32mr); goto ReSimplify;
571 case X86::RELEASE_ADD64mi32: OutMI.setOpcode(X86::ADD64mi32); goto ReSimplify;
572 case X86::RELEASE_ADD64mr: OutMI.setOpcode(X86::ADD64mr); goto ReSimplify;
573 case X86::RELEASE_AND8mi: OutMI.setOpcode(X86::AND8mi); goto ReSimplify;
574 case X86::RELEASE_AND8mr: OutMI.setOpcode(X86::AND8mr); goto ReSimplify;
575 case X86::RELEASE_AND32mi: OutMI.setOpcode(X86::AND32mi); goto ReSimplify;
576 case X86::RELEASE_AND32mr: OutMI.setOpcode(X86::AND32mr); goto ReSimplify;
577 case X86::RELEASE_AND64mi32: OutMI.setOpcode(X86::AND64mi32); goto ReSimplify;
578 case X86::RELEASE_AND64mr: OutMI.setOpcode(X86::AND64mr); goto ReSimplify;
579 case X86::RELEASE_OR8mi: OutMI.setOpcode(X86::OR8mi); goto ReSimplify;
580 case X86::RELEASE_OR8mr: OutMI.setOpcode(X86::OR8mr); goto ReSimplify;
581 case X86::RELEASE_OR32mi: OutMI.setOpcode(X86::OR32mi); goto ReSimplify;
582 case X86::RELEASE_OR32mr: OutMI.setOpcode(X86::OR32mr); goto ReSimplify;
583 case X86::RELEASE_OR64mi32: OutMI.setOpcode(X86::OR64mi32); goto ReSimplify;
584 case X86::RELEASE_OR64mr: OutMI.setOpcode(X86::OR64mr); goto ReSimplify;
585 case X86::RELEASE_XOR8mi: OutMI.setOpcode(X86::XOR8mi); goto ReSimplify;
586 case X86::RELEASE_XOR8mr: OutMI.setOpcode(X86::XOR8mr); goto ReSimplify;
587 case X86::RELEASE_XOR32mi: OutMI.setOpcode(X86::XOR32mi); goto ReSimplify;
588 case X86::RELEASE_XOR32mr: OutMI.setOpcode(X86::XOR32mr); goto ReSimplify;
589 case X86::RELEASE_XOR64mi32: OutMI.setOpcode(X86::XOR64mi32); goto ReSimplify;
590 case X86::RELEASE_XOR64mr: OutMI.setOpcode(X86::XOR64mr); goto ReSimplify;
591 case X86::RELEASE_INC8m: OutMI.setOpcode(X86::INC8m); goto ReSimplify;
592 case X86::RELEASE_INC16m: OutMI.setOpcode(X86::INC16m); goto ReSimplify;
593 case X86::RELEASE_INC32m: OutMI.setOpcode(X86::INC32m); goto ReSimplify;
594 case X86::RELEASE_INC64m: OutMI.setOpcode(X86::INC64m); goto ReSimplify;
595 case X86::RELEASE_DEC8m: OutMI.setOpcode(X86::DEC8m); goto ReSimplify;
596 case X86::RELEASE_DEC16m: OutMI.setOpcode(X86::DEC16m); goto ReSimplify;
597 case X86::RELEASE_DEC32m: OutMI.setOpcode(X86::DEC32m); goto ReSimplify;
598 case X86::RELEASE_DEC64m: OutMI.setOpcode(X86::DEC64m); goto ReSimplify;
599
600 // We don't currently select the correct instruction form for instructions
601 // which have a short %eax, etc. form. Handle this by custom lowering, for
602 // now.
603 //
604 // Note, we are currently not handling the following instructions:
605 // MOV64ao8, MOV64o8a
606 // XCHG16ar, XCHG32ar, XCHG64ar
607 case X86::MOV8mr_NOREX:
608 case X86::MOV8mr:
609 case X86::MOV8rm_NOREX:
610 case X86::MOV8rm:
611 case X86::MOV16mr:
612 case X86::MOV16rm:
613 case X86::MOV32mr:
614 case X86::MOV32rm: {
615 unsigned NewOpc;
616 switch (OutMI.getOpcode()) {
617 default: llvm_unreachable("Invalid opcode")::llvm::llvm_unreachable_internal("Invalid opcode", "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301235/lib/Target/X86/X86MCInstLower.cpp"
, 617)
;
618 case X86::MOV8mr_NOREX:
619 case X86::MOV8mr: NewOpc = X86::MOV8o32a; break;
620 case X86::MOV8rm_NOREX:
621 case X86::MOV8rm: NewOpc = X86::MOV8ao32; break;
622 case X86::MOV16mr: NewOpc = X86::MOV16o32a; break;
623 case X86::MOV16rm: NewOpc = X86::MOV16ao32; break;
624 case X86::MOV32mr: NewOpc = X86::MOV32o32a; break;
625 case X86::MOV32rm: NewOpc = X86::MOV32ao32; break;
626 }
627 SimplifyShortMoveForm(AsmPrinter, OutMI, NewOpc);
628 break;
629 }
630
631 case X86::ADC8ri: case X86::ADC16ri: case X86::ADC32ri: case X86::ADC64ri32:
632 case X86::ADD8ri: case X86::ADD16ri: case X86::ADD32ri: case X86::ADD64ri32:
633 case X86::AND8ri: case X86::AND16ri: case X86::AND32ri: case X86::AND64ri32:
634 case X86::CMP8ri: case X86::CMP16ri: case X86::CMP32ri: case X86::CMP64ri32:
635 case X86::OR8ri: case X86::OR16ri: case X86::OR32ri: case X86::OR64ri32:
636 case X86::SBB8ri: case X86::SBB16ri: case X86::SBB32ri: case X86::SBB64ri32:
637 case X86::SUB8ri: case X86::SUB16ri: case X86::SUB32ri: case X86::SUB64ri32:
638 case X86::TEST8ri:case X86::TEST16ri:case X86::TEST32ri:case X86::TEST64ri32:
639 case X86::XOR8ri: case X86::XOR16ri: case X86::XOR32ri: case X86::XOR64ri32: {
640 unsigned NewOpc;
641 switch (OutMI.getOpcode()) {
642 default: llvm_unreachable("Invalid opcode")::llvm::llvm_unreachable_internal("Invalid opcode", "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301235/lib/Target/X86/X86MCInstLower.cpp"
, 642)
;
643 case X86::ADC8ri: NewOpc = X86::ADC8i8; break;
644 case X86::ADC16ri: NewOpc = X86::ADC16i16; break;
645 case X86::ADC32ri: NewOpc = X86::ADC32i32; break;
646 case X86::ADC64ri32: NewOpc = X86::ADC64i32; break;
647 case X86::ADD8ri: NewOpc = X86::ADD8i8; break;
648 case X86::ADD16ri: NewOpc = X86::ADD16i16; break;
649 case X86::ADD32ri: NewOpc = X86::ADD32i32; break;
650 case X86::ADD64ri32: NewOpc = X86::ADD64i32; break;
651 case X86::AND8ri: NewOpc = X86::AND8i8; break;
652 case X86::AND16ri: NewOpc = X86::AND16i16; break;
653 case X86::AND32ri: NewOpc = X86::AND32i32; break;
654 case X86::AND64ri32: NewOpc = X86::AND64i32; break;
655 case X86::CMP8ri: NewOpc = X86::CMP8i8; break;
656 case X86::CMP16ri: NewOpc = X86::CMP16i16; break;
657 case X86::CMP32ri: NewOpc = X86::CMP32i32; break;
658 case X86::CMP64ri32: NewOpc = X86::CMP64i32; break;
659 case X86::OR8ri: NewOpc = X86::OR8i8; break;
660 case X86::OR16ri: NewOpc = X86::OR16i16; break;
661 case X86::OR32ri: NewOpc = X86::OR32i32; break;
662 case X86::OR64ri32: NewOpc = X86::OR64i32; break;
663 case X86::SBB8ri: NewOpc = X86::SBB8i8; break;
664 case X86::SBB16ri: NewOpc = X86::SBB16i16; break;
665 case X86::SBB32ri: NewOpc = X86::SBB32i32; break;
666 case X86::SBB64ri32: NewOpc = X86::SBB64i32; break;
667 case X86::SUB8ri: NewOpc = X86::SUB8i8; break;
668 case X86::SUB16ri: NewOpc = X86::SUB16i16; break;
669 case X86::SUB32ri: NewOpc = X86::SUB32i32; break;
670 case X86::SUB64ri32: NewOpc = X86::SUB64i32; break;
671 case X86::TEST8ri: NewOpc = X86::TEST8i8; break;
672 case X86::TEST16ri: NewOpc = X86::TEST16i16; break;
673 case X86::TEST32ri: NewOpc = X86::TEST32i32; break;
674 case X86::TEST64ri32: NewOpc = X86::TEST64i32; break;
675 case X86::XOR8ri: NewOpc = X86::XOR8i8; break;
676 case X86::XOR16ri: NewOpc = X86::XOR16i16; break;
677 case X86::XOR32ri: NewOpc = X86::XOR32i32; break;
678 case X86::XOR64ri32: NewOpc = X86::XOR64i32; break;
679 }
680 SimplifyShortImmForm(OutMI, NewOpc);
681 break;
682 }
683
684 // Try to shrink some forms of movsx.
685 case X86::MOVSX16rr8:
686 case X86::MOVSX32rr16:
687 case X86::MOVSX64rr32:
688 SimplifyMOVSX(OutMI);
689 break;
690 }
691}
692
693void X86AsmPrinter::LowerTlsAddr(X86MCInstLower &MCInstLowering,
694 const MachineInstr &MI) {
695
696 bool is64Bits = MI.getOpcode() == X86::TLS_addr64 ||
697 MI.getOpcode() == X86::TLS_base_addr64;
698
699 bool needsPadding = MI.getOpcode() == X86::TLS_addr64;
700
701 MCContext &context = OutStreamer->getContext();
702
703 if (needsPadding)
704 EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX));
705
706 MCSymbolRefExpr::VariantKind SRVK;
707 switch (MI.getOpcode()) {
708 case X86::TLS_addr32:
709 case X86::TLS_addr64:
710 SRVK = MCSymbolRefExpr::VK_TLSGD;
711 break;
712 case X86::TLS_base_addr32:
713 SRVK = MCSymbolRefExpr::VK_TLSLDM;
714 break;
715 case X86::TLS_base_addr64:
716 SRVK = MCSymbolRefExpr::VK_TLSLD;
717 break;
718 default:
719 llvm_unreachable("unexpected opcode")::llvm::llvm_unreachable_internal("unexpected opcode", "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301235/lib/Target/X86/X86MCInstLower.cpp"
, 719)
;
720 }
721
722 MCSymbol *sym = MCInstLowering.GetSymbolFromOperand(MI.getOperand(3));
723 const MCSymbolRefExpr *symRef = MCSymbolRefExpr::create(sym, SRVK, context);
724
725 MCInst LEA;
726 if (is64Bits) {
727 LEA.setOpcode(X86::LEA64r);
728 LEA.addOperand(MCOperand::createReg(X86::RDI)); // dest
729 LEA.addOperand(MCOperand::createReg(X86::RIP)); // base
730 LEA.addOperand(MCOperand::createImm(1)); // scale
731 LEA.addOperand(MCOperand::createReg(0)); // index
732 LEA.addOperand(MCOperand::createExpr(symRef)); // disp
733 LEA.addOperand(MCOperand::createReg(0)); // seg
734 } else if (SRVK == MCSymbolRefExpr::VK_TLSLDM) {
735 LEA.setOpcode(X86::LEA32r);
736 LEA.addOperand(MCOperand::createReg(X86::EAX)); // dest
737 LEA.addOperand(MCOperand::createReg(X86::EBX)); // base
738 LEA.addOperand(MCOperand::createImm(1)); // scale
739 LEA.addOperand(MCOperand::createReg(0)); // index
740 LEA.addOperand(MCOperand::createExpr(symRef)); // disp
741 LEA.addOperand(MCOperand::createReg(0)); // seg
742 } else {
743 LEA.setOpcode(X86::LEA32r);
744 LEA.addOperand(MCOperand::createReg(X86::EAX)); // dest
745 LEA.addOperand(MCOperand::createReg(0)); // base
746 LEA.addOperand(MCOperand::createImm(1)); // scale
747 LEA.addOperand(MCOperand::createReg(X86::EBX)); // index
748 LEA.addOperand(MCOperand::createExpr(symRef)); // disp
749 LEA.addOperand(MCOperand::createReg(0)); // seg
750 }
751 EmitAndCountInstruction(LEA);
752
753 if (needsPadding) {
754 EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX));
755 EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX));
756 EmitAndCountInstruction(MCInstBuilder(X86::REX64_PREFIX));
757 }
758
759 StringRef name = is64Bits ? "__tls_get_addr" : "___tls_get_addr";
760 MCSymbol *tlsGetAddr = context.getOrCreateSymbol(name);
761 const MCSymbolRefExpr *tlsRef =
762 MCSymbolRefExpr::create(tlsGetAddr,
763 MCSymbolRefExpr::VK_PLT,
764 context);
765
766 EmitAndCountInstruction(MCInstBuilder(is64Bits ? X86::CALL64pcrel32
767 : X86::CALLpcrel32)
768 .addExpr(tlsRef));
769}
770
771/// \brief Emit the largest nop instruction smaller than or equal to \p NumBytes
772/// bytes. Return the size of nop emitted.
773static unsigned EmitNop(MCStreamer &OS, unsigned NumBytes, bool Is64Bit,
774 const MCSubtargetInfo &STI) {
775 // This works only for 64bit. For 32bit we have to do additional checking if
776 // the CPU supports multi-byte nops.
777 assert(Is64Bit && "EmitNops only supports X86-64")((Is64Bit && "EmitNops only supports X86-64") ? static_cast
<void> (0) : __assert_fail ("Is64Bit && \"EmitNops only supports X86-64\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301235/lib/Target/X86/X86MCInstLower.cpp"
, 777, __PRETTY_FUNCTION__))
;
778
779 unsigned NopSize;
780 unsigned Opc, BaseReg, ScaleVal, IndexReg, Displacement, SegmentReg;
781 Opc = IndexReg = Displacement = SegmentReg = 0;
Value stored to 'Opc' is never read
782 BaseReg = X86::RAX;
783 ScaleVal = 1;
784 switch (NumBytes) {
785 case 0: llvm_unreachable("Zero nops?")::llvm::llvm_unreachable_internal("Zero nops?", "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301235/lib/Target/X86/X86MCInstLower.cpp"
, 785)
; break;
786 case 1: NopSize = 1; Opc = X86::NOOP; break;
787 case 2: NopSize = 2; Opc = X86::XCHG16ar; break;
788 case 3: NopSize = 3; Opc = X86::NOOPL; break;
789 case 4: NopSize = 4; Opc = X86::NOOPL; Displacement = 8; break;
790 case 5: NopSize = 5; Opc = X86::NOOPL; Displacement = 8;
791 IndexReg = X86::RAX; break;
792 case 6: NopSize = 6; Opc = X86::NOOPW; Displacement = 8;
793 IndexReg = X86::RAX; break;
794 case 7: NopSize = 7; Opc = X86::NOOPL; Displacement = 512; break;
795 case 8: NopSize = 8; Opc = X86::NOOPL; Displacement = 512;
796 IndexReg = X86::RAX; break;
797 case 9: NopSize = 9; Opc = X86::NOOPW; Displacement = 512;
798 IndexReg = X86::RAX; break;
799 default: NopSize = 10; Opc = X86::NOOPW; Displacement = 512;
800 IndexReg = X86::RAX; SegmentReg = X86::CS; break;
801 }
802
803 unsigned NumPrefixes = std::min(NumBytes - NopSize, 5U);
804 NopSize += NumPrefixes;
805 for (unsigned i = 0; i != NumPrefixes; ++i)
806 OS.EmitBytes("\x66");
807
808 switch (Opc) {
809 default:
810 llvm_unreachable("Unexpected opcode")::llvm::llvm_unreachable_internal("Unexpected opcode", "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301235/lib/Target/X86/X86MCInstLower.cpp"
, 810)
;
811 break;
812 case X86::NOOP:
813 OS.EmitInstruction(MCInstBuilder(Opc), STI);
814 break;
815 case X86::XCHG16ar:
816 OS.EmitInstruction(MCInstBuilder(Opc).addReg(X86::AX), STI);
817 break;
818 case X86::NOOPL:
819 case X86::NOOPW:
820 OS.EmitInstruction(MCInstBuilder(Opc)
821 .addReg(BaseReg)
822 .addImm(ScaleVal)
823 .addReg(IndexReg)
824 .addImm(Displacement)
825 .addReg(SegmentReg),
826 STI);
827 break;
828 }
829 assert(NopSize <= NumBytes && "We overemitted?")((NopSize <= NumBytes && "We overemitted?") ? static_cast
<void> (0) : __assert_fail ("NopSize <= NumBytes && \"We overemitted?\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301235/lib/Target/X86/X86MCInstLower.cpp"
, 829, __PRETTY_FUNCTION__))
;
830 return NopSize;
831}
832
833/// \brief Emit the optimal amount of multi-byte nops on X86.
834static void EmitNops(MCStreamer &OS, unsigned NumBytes, bool Is64Bit,
835 const MCSubtargetInfo &STI) {
836 unsigned NopsToEmit = NumBytes;
837 (void)NopsToEmit;
838 while (NumBytes) {
839 NumBytes -= EmitNop(OS, NumBytes, Is64Bit, STI);
840 assert(NopsToEmit >= NumBytes && "Emitted more than I asked for!")((NopsToEmit >= NumBytes && "Emitted more than I asked for!"
) ? static_cast<void> (0) : __assert_fail ("NopsToEmit >= NumBytes && \"Emitted more than I asked for!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301235/lib/Target/X86/X86MCInstLower.cpp"
, 840, __PRETTY_FUNCTION__))
;
841 }
842}
843
844void X86AsmPrinter::LowerSTATEPOINT(const MachineInstr &MI,
845 X86MCInstLower &MCIL) {
846 assert(Subtarget->is64Bit() && "Statepoint currently only supports X86-64")((Subtarget->is64Bit() && "Statepoint currently only supports X86-64"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->is64Bit() && \"Statepoint currently only supports X86-64\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301235/lib/Target/X86/X86MCInstLower.cpp"
, 846, __PRETTY_FUNCTION__))
;
847
848 StatepointOpers SOpers(&MI);
849 if (unsigned PatchBytes = SOpers.getNumPatchBytes()) {
850 EmitNops(*OutStreamer, PatchBytes, Subtarget->is64Bit(),
851 getSubtargetInfo());
852 } else {
853 // Lower call target and choose correct opcode
854 const MachineOperand &CallTarget = SOpers.getCallTarget();
855 MCOperand CallTargetMCOp;
856 unsigned CallOpcode;
857 switch (CallTarget.getType()) {
858 case MachineOperand::MO_GlobalAddress:
859 case MachineOperand::MO_ExternalSymbol:
860 CallTargetMCOp = MCIL.LowerSymbolOperand(
861 CallTarget, MCIL.GetSymbolFromOperand(CallTarget));
862 CallOpcode = X86::CALL64pcrel32;
863 // Currently, we only support relative addressing with statepoints.
864 // Otherwise, we'll need a scratch register to hold the target
865 // address. You'll fail asserts during load & relocation if this
866 // symbol is to far away. (TODO: support non-relative addressing)
867 break;
868 case MachineOperand::MO_Immediate:
869 CallTargetMCOp = MCOperand::createImm(CallTarget.getImm());
870 CallOpcode = X86::CALL64pcrel32;
871 // Currently, we only support relative addressing with statepoints.
872 // Otherwise, we'll need a scratch register to hold the target
873 // immediate. You'll fail asserts during load & relocation if this
874 // address is to far away. (TODO: support non-relative addressing)
875 break;
876 case MachineOperand::MO_Register:
877 CallTargetMCOp = MCOperand::createReg(CallTarget.getReg());
878 CallOpcode = X86::CALL64r;
879 break;
880 default:
881 llvm_unreachable("Unsupported operand type in statepoint call target")::llvm::llvm_unreachable_internal("Unsupported operand type in statepoint call target"
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301235/lib/Target/X86/X86MCInstLower.cpp"
, 881)
;
882 break;
883 }
884
885 // Emit call
886 MCInst CallInst;
887 CallInst.setOpcode(CallOpcode);
888 CallInst.addOperand(CallTargetMCOp);
889 OutStreamer->EmitInstruction(CallInst, getSubtargetInfo());
890 }
891
892 // Record our statepoint node in the same section used by STACKMAP
893 // and PATCHPOINT
894 SM.recordStatepoint(MI);
895}
896
897void X86AsmPrinter::LowerFAULTING_OP(const MachineInstr &FaultingMI,
898 X86MCInstLower &MCIL) {
899 // FAULTING_LOAD_OP <def>, <faltinf type>, <MBB handler>,
900 // <opcode>, <operands>
901
902 unsigned DefRegister = FaultingMI.getOperand(0).getReg();
903 FaultMaps::FaultKind FK =
904 static_cast<FaultMaps::FaultKind>(FaultingMI.getOperand(1).getImm());
905 MCSymbol *HandlerLabel = FaultingMI.getOperand(2).getMBB()->getSymbol();
906 unsigned Opcode = FaultingMI.getOperand(3).getImm();
907 unsigned OperandsBeginIdx = 4;
908
909 assert(FK < FaultMaps::FaultKindMax && "Invalid Faulting Kind!")((FK < FaultMaps::FaultKindMax && "Invalid Faulting Kind!"
) ? static_cast<void> (0) : __assert_fail ("FK < FaultMaps::FaultKindMax && \"Invalid Faulting Kind!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301235/lib/Target/X86/X86MCInstLower.cpp"
, 909, __PRETTY_FUNCTION__))
;
910 FM.recordFaultingOp(FK, HandlerLabel);
911
912 MCInst MI;
913 MI.setOpcode(Opcode);
914
915 if (DefRegister != X86::NoRegister)
916 MI.addOperand(MCOperand::createReg(DefRegister));
917
918 for (auto I = FaultingMI.operands_begin() + OperandsBeginIdx,
919 E = FaultingMI.operands_end();
920 I != E; ++I)
921 if (auto MaybeOperand = MCIL.LowerMachineOperand(&FaultingMI, *I))
922 MI.addOperand(MaybeOperand.getValue());
923
924 OutStreamer->EmitInstruction(MI, getSubtargetInfo());
925}
926
927void X86AsmPrinter::LowerFENTRY_CALL(const MachineInstr &MI,
928 X86MCInstLower &MCIL) {
929 bool Is64Bits = Subtarget->is64Bit();
930 MCContext &Ctx = OutStreamer->getContext();
931 MCSymbol *fentry = Ctx.getOrCreateSymbol("__fentry__");
932 const MCSymbolRefExpr *Op =
933 MCSymbolRefExpr::create(fentry, MCSymbolRefExpr::VK_None, Ctx);
934
935 EmitAndCountInstruction(
936 MCInstBuilder(Is64Bits ? X86::CALL64pcrel32 : X86::CALLpcrel32)
937 .addExpr(Op));
938}
939
940void X86AsmPrinter::LowerPATCHABLE_OP(const MachineInstr &MI,
941 X86MCInstLower &MCIL) {
942 // PATCHABLE_OP minsize, opcode, operands
943
944 unsigned MinSize = MI.getOperand(0).getImm();
945 unsigned Opcode = MI.getOperand(1).getImm();
946
947 MCInst MCI;
948 MCI.setOpcode(Opcode);
949 for (auto &MO : make_range(MI.operands_begin() + 2, MI.operands_end()))
950 if (auto MaybeOperand = MCIL.LowerMachineOperand(&MI, MO))
951 MCI.addOperand(MaybeOperand.getValue());
952
953 SmallString<256> Code;
954 SmallVector<MCFixup, 4> Fixups;
955 raw_svector_ostream VecOS(Code);
956 CodeEmitter->encodeInstruction(MCI, VecOS, Fixups, getSubtargetInfo());
957
958 if (Code.size() < MinSize) {
959 if (MinSize == 2 && Opcode == X86::PUSH64r) {
960 // This is an optimization that lets us get away without emitting a nop in
961 // many cases.
962 //
963 // NB! In some cases the encoding for PUSH64r (e.g. PUSH64r %R9) takes two
964 // bytes too, so the check on MinSize is important.
965 MCI.setOpcode(X86::PUSH64rmr);
966 } else {
967 unsigned NopSize = EmitNop(*OutStreamer, MinSize, Subtarget->is64Bit(),
968 getSubtargetInfo());
969 assert(NopSize == MinSize && "Could not implement MinSize!")((NopSize == MinSize && "Could not implement MinSize!"
) ? static_cast<void> (0) : __assert_fail ("NopSize == MinSize && \"Could not implement MinSize!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301235/lib/Target/X86/X86MCInstLower.cpp"
, 969, __PRETTY_FUNCTION__))
;
970 (void) NopSize;
971 }
972 }
973
974 OutStreamer->EmitInstruction(MCI, getSubtargetInfo());
975}
976
977// Lower a stackmap of the form:
978// <id>, <shadowBytes>, ...
979void X86AsmPrinter::LowerSTACKMAP(const MachineInstr &MI) {
980 SMShadowTracker.emitShadowPadding(*OutStreamer, getSubtargetInfo());
981 SM.recordStackMap(MI);
982 unsigned NumShadowBytes = MI.getOperand(1).getImm();
983 SMShadowTracker.reset(NumShadowBytes);
984}
985
986// Lower a patchpoint of the form:
987// [<def>], <id>, <numBytes>, <target>, <numArgs>, <cc>, ...
988void X86AsmPrinter::LowerPATCHPOINT(const MachineInstr &MI,
989 X86MCInstLower &MCIL) {
990 assert(Subtarget->is64Bit() && "Patchpoint currently only supports X86-64")((Subtarget->is64Bit() && "Patchpoint currently only supports X86-64"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->is64Bit() && \"Patchpoint currently only supports X86-64\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301235/lib/Target/X86/X86MCInstLower.cpp"
, 990, __PRETTY_FUNCTION__))
;
991
992 SMShadowTracker.emitShadowPadding(*OutStreamer, getSubtargetInfo());
993
994 SM.recordPatchPoint(MI);
995
996 PatchPointOpers opers(&MI);
997 unsigned ScratchIdx = opers.getNextScratchIdx();
998 unsigned EncodedBytes = 0;
999 const MachineOperand &CalleeMO = opers.getCallTarget();
1000
1001 // Check for null target. If target is non-null (i.e. is non-zero or is
1002 // symbolic) then emit a call.
1003 if (!(CalleeMO.isImm() && !CalleeMO.getImm())) {
1004 MCOperand CalleeMCOp;
1005 switch (CalleeMO.getType()) {
1006 default:
1007 /// FIXME: Add a verifier check for bad callee types.
1008 llvm_unreachable("Unrecognized callee operand type.")::llvm::llvm_unreachable_internal("Unrecognized callee operand type."
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301235/lib/Target/X86/X86MCInstLower.cpp"
, 1008)
;
1009 case MachineOperand::MO_Immediate:
1010 if (CalleeMO.getImm())
1011 CalleeMCOp = MCOperand::createImm(CalleeMO.getImm());
1012 break;
1013 case MachineOperand::MO_ExternalSymbol:
1014 case MachineOperand::MO_GlobalAddress:
1015 CalleeMCOp =
1016 MCIL.LowerSymbolOperand(CalleeMO,
1017 MCIL.GetSymbolFromOperand(CalleeMO));
1018 break;
1019 }
1020
1021 // Emit MOV to materialize the target address and the CALL to target.
1022 // This is encoded with 12-13 bytes, depending on which register is used.
1023 unsigned ScratchReg = MI.getOperand(ScratchIdx).getReg();
1024 if (X86II::isX86_64ExtendedReg(ScratchReg))
1025 EncodedBytes = 13;
1026 else
1027 EncodedBytes = 12;
1028
1029 EmitAndCountInstruction(
1030 MCInstBuilder(X86::MOV64ri).addReg(ScratchReg).addOperand(CalleeMCOp));
1031 EmitAndCountInstruction(MCInstBuilder(X86::CALL64r).addReg(ScratchReg));
1032 }
1033
1034 // Emit padding.
1035 unsigned NumBytes = opers.getNumPatchBytes();
1036 assert(NumBytes >= EncodedBytes &&((NumBytes >= EncodedBytes && "Patchpoint can't request size less than the length of a call."
) ? static_cast<void> (0) : __assert_fail ("NumBytes >= EncodedBytes && \"Patchpoint can't request size less than the length of a call.\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301235/lib/Target/X86/X86MCInstLower.cpp"
, 1037, __PRETTY_FUNCTION__))
1037 "Patchpoint can't request size less than the length of a call.")((NumBytes >= EncodedBytes && "Patchpoint can't request size less than the length of a call."
) ? static_cast<void> (0) : __assert_fail ("NumBytes >= EncodedBytes && \"Patchpoint can't request size less than the length of a call.\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301235/lib/Target/X86/X86MCInstLower.cpp"
, 1037, __PRETTY_FUNCTION__))
;
1038
1039 EmitNops(*OutStreamer, NumBytes - EncodedBytes, Subtarget->is64Bit(),
1040 getSubtargetInfo());
1041}
1042
1043void X86AsmPrinter::LowerPATCHABLE_FUNCTION_ENTER(const MachineInstr &MI,
1044 X86MCInstLower &MCIL) {
1045 // We want to emit the following pattern:
1046 //
1047 // .p2align 1, ...
1048 // .Lxray_sled_N:
1049 // jmp .tmpN
1050 // # 9 bytes worth of noops
1051 // .tmpN
1052 //
1053 // We need the 9 bytes because at runtime, we'd be patching over the full 11
1054 // bytes with the following pattern:
1055 //
1056 // mov %r10, <function id, 32-bit> // 6 bytes
1057 // call <relative offset, 32-bits> // 5 bytes
1058 //
1059 auto CurSled = OutContext.createTempSymbol("xray_sled_", true);
1060 OutStreamer->EmitCodeAlignment(2);
1061 OutStreamer->EmitLabel(CurSled);
1062 auto Target = OutContext.createTempSymbol();
1063
1064 // Use a two-byte `jmp`. This version of JMP takes an 8-bit relative offset as
1065 // an operand (computed as an offset from the jmp instruction).
1066 // FIXME: Find another less hacky way do force the relative jump.
1067 OutStreamer->EmitBytes("\xeb\x09");
1068 EmitNops(*OutStreamer, 9, Subtarget->is64Bit(), getSubtargetInfo());
1069 OutStreamer->EmitLabel(Target);
1070 recordSled(CurSled, MI, SledKind::FUNCTION_ENTER);
1071}
1072
1073void X86AsmPrinter::LowerPATCHABLE_RET(const MachineInstr &MI,
1074 X86MCInstLower &MCIL) {
1075 // Since PATCHABLE_RET takes the opcode of the return statement as an
1076 // argument, we use that to emit the correct form of the RET that we want.
1077 // i.e. when we see this:
1078 //
1079 // PATCHABLE_RET X86::RET ...
1080 //
1081 // We should emit the RET followed by sleds.
1082 //
1083 // .p2align 1, ...
1084 // .Lxray_sled_N:
1085 // ret # or equivalent instruction
1086 // # 10 bytes worth of noops
1087 //
1088 // This just makes sure that the alignment for the next instruction is 2.
1089 auto CurSled = OutContext.createTempSymbol("xray_sled_", true);
1090 OutStreamer->EmitCodeAlignment(2);
1091 OutStreamer->EmitLabel(CurSled);
1092 unsigned OpCode = MI.getOperand(0).getImm();
1093 MCInst Ret;
1094 Ret.setOpcode(OpCode);
1095 for (auto &MO : make_range(MI.operands_begin() + 1, MI.operands_end()))
1096 if (auto MaybeOperand = MCIL.LowerMachineOperand(&MI, MO))
1097 Ret.addOperand(MaybeOperand.getValue());
1098 OutStreamer->EmitInstruction(Ret, getSubtargetInfo());
1099 EmitNops(*OutStreamer, 10, Subtarget->is64Bit(), getSubtargetInfo());
1100 recordSled(CurSled, MI, SledKind::FUNCTION_EXIT);
1101}
1102
1103void X86AsmPrinter::LowerPATCHABLE_TAIL_CALL(const MachineInstr &MI, X86MCInstLower &MCIL) {
1104 // Like PATCHABLE_RET, we have the actual instruction in the operands to this
1105 // instruction so we lower that particular instruction and its operands.
1106 // Unlike PATCHABLE_RET though, we put the sled before the JMP, much like how
1107 // we do it for PATCHABLE_FUNCTION_ENTER. The sled should be very similar to
1108 // the PATCHABLE_FUNCTION_ENTER case, followed by the lowering of the actual
1109 // tail call much like how we have it in PATCHABLE_RET.
1110 auto CurSled = OutContext.createTempSymbol("xray_sled_", true);
1111 OutStreamer->EmitCodeAlignment(2);
1112 OutStreamer->EmitLabel(CurSled);
1113 auto Target = OutContext.createTempSymbol();
1114
1115 // Use a two-byte `jmp`. This version of JMP takes an 8-bit relative offset as
1116 // an operand (computed as an offset from the jmp instruction).
1117 // FIXME: Find another less hacky way do force the relative jump.
1118 OutStreamer->EmitBytes("\xeb\x09");
1119 EmitNops(*OutStreamer, 9, Subtarget->is64Bit(), getSubtargetInfo());
1120 OutStreamer->EmitLabel(Target);
1121 recordSled(CurSled, MI, SledKind::TAIL_CALL);
1122
1123 unsigned OpCode = MI.getOperand(0).getImm();
1124 MCInst TC;
1125 TC.setOpcode(OpCode);
1126
1127 // Before emitting the instruction, add a comment to indicate that this is
1128 // indeed a tail call.
1129 OutStreamer->AddComment("TAILCALL");
1130 for (auto &MO : make_range(MI.operands_begin() + 1, MI.operands_end()))
1131 if (auto MaybeOperand = MCIL.LowerMachineOperand(&MI, MO))
1132 TC.addOperand(MaybeOperand.getValue());
1133 OutStreamer->EmitInstruction(TC, getSubtargetInfo());
1134}
1135
1136// Returns instruction preceding MBBI in MachineFunction.
1137// If MBBI is the first instruction of the first basic block, returns null.
1138static MachineBasicBlock::const_iterator
1139PrevCrossBBInst(MachineBasicBlock::const_iterator MBBI) {
1140 const MachineBasicBlock *MBB = MBBI->getParent();
1141 while (MBBI == MBB->begin()) {
1142 if (MBB == &MBB->getParent()->front())
1143 return MachineBasicBlock::const_iterator();
1144 MBB = MBB->getPrevNode();
1145 MBBI = MBB->end();
1146 }
1147 return --MBBI;
1148}
1149
1150static const Constant *getConstantFromPool(const MachineInstr &MI,
1151 const MachineOperand &Op) {
1152 if (!Op.isCPI())
1153 return nullptr;
1154
1155 ArrayRef<MachineConstantPoolEntry> Constants =
1156 MI.getParent()->getParent()->getConstantPool()->getConstants();
1157 const MachineConstantPoolEntry &ConstantEntry =
1158 Constants[Op.getIndex()];
1159
1160 // Bail if this is a machine constant pool entry, we won't be able to dig out
1161 // anything useful.
1162 if (ConstantEntry.isMachineConstantPoolEntry())
1163 return nullptr;
1164
1165 auto *C = dyn_cast<Constant>(ConstantEntry.Val.ConstVal);
1166 assert((!C || ConstantEntry.getType() == C->getType()) &&(((!C || ConstantEntry.getType() == C->getType()) &&
"Expected a constant of the same type!") ? static_cast<void
> (0) : __assert_fail ("(!C || ConstantEntry.getType() == C->getType()) && \"Expected a constant of the same type!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301235/lib/Target/X86/X86MCInstLower.cpp"
, 1167, __PRETTY_FUNCTION__))
1167 "Expected a constant of the same type!")(((!C || ConstantEntry.getType() == C->getType()) &&
"Expected a constant of the same type!") ? static_cast<void
> (0) : __assert_fail ("(!C || ConstantEntry.getType() == C->getType()) && \"Expected a constant of the same type!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301235/lib/Target/X86/X86MCInstLower.cpp"
, 1167, __PRETTY_FUNCTION__))
;
1168 return C;
1169}
1170
1171static std::string getShuffleComment(const MachineInstr *MI,
1172 unsigned SrcOp1Idx,
1173 unsigned SrcOp2Idx,
1174 ArrayRef<int> Mask) {
1175 std::string Comment;
1176
1177 // Compute the name for a register. This is really goofy because we have
1178 // multiple instruction printers that could (in theory) use different
1179 // names. Fortunately most people use the ATT style (outside of Windows)
1180 // and they actually agree on register naming here. Ultimately, this is
1181 // a comment, and so its OK if it isn't perfect.
1182 auto GetRegisterName = [](unsigned RegNum) -> StringRef {
1183 return X86ATTInstPrinter::getRegisterName(RegNum);
1184 };
1185
1186 const MachineOperand &DstOp = MI->getOperand(0);
1187 const MachineOperand &SrcOp1 = MI->getOperand(SrcOp1Idx);
1188 const MachineOperand &SrcOp2 = MI->getOperand(SrcOp2Idx);
1189
1190 StringRef DstName = DstOp.isReg() ? GetRegisterName(DstOp.getReg()) : "mem";
1191 StringRef Src1Name =
1192 SrcOp1.isReg() ? GetRegisterName(SrcOp1.getReg()) : "mem";
1193 StringRef Src2Name =
1194 SrcOp2.isReg() ? GetRegisterName(SrcOp2.getReg()) : "mem";
1195
1196 // One source operand, fix the mask to print all elements in one span.
1197 SmallVector<int, 8> ShuffleMask(Mask.begin(), Mask.end());
1198 if (Src1Name == Src2Name)
1199 for (int i = 0, e = ShuffleMask.size(); i != e; ++i)
1200 if (ShuffleMask[i] >= e)
1201 ShuffleMask[i] -= e;
1202
1203 raw_string_ostream CS(Comment);
1204 CS << DstName;
1205
1206 // Handle AVX512 MASK/MASXZ write mask comments.
1207 // MASK: zmmX {%kY}
1208 // MASKZ: zmmX {%kY} {z}
1209 if (SrcOp1Idx > 1) {
1210 assert((SrcOp1Idx == 2 || SrcOp1Idx == 3) && "Unexpected writemask")(((SrcOp1Idx == 2 || SrcOp1Idx == 3) && "Unexpected writemask"
) ? static_cast<void> (0) : __assert_fail ("(SrcOp1Idx == 2 || SrcOp1Idx == 3) && \"Unexpected writemask\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301235/lib/Target/X86/X86MCInstLower.cpp"
, 1210, __PRETTY_FUNCTION__))
;
1211
1212 const MachineOperand &WriteMaskOp = MI->getOperand(SrcOp1Idx - 1);
1213 if (WriteMaskOp.isReg()) {
1214 CS << " {%" << GetRegisterName(WriteMaskOp.getReg()) << "}";
1215
1216 if (SrcOp1Idx == 2) {
1217 CS << " {z}";
1218 }
1219 }
1220 }
1221
1222 CS << " = ";
1223
1224 for (int i = 0, e = ShuffleMask.size(); i != e; ++i) {
1225 if (i != 0)
1226 CS << ",";
1227 if (ShuffleMask[i] == SM_SentinelZero) {
1228 CS << "zero";
1229 continue;
1230 }
1231
1232 // Otherwise, it must come from src1 or src2. Print the span of elements
1233 // that comes from this src.
1234 bool isSrc1 = ShuffleMask[i] < (int)e;
1235 CS << (isSrc1 ? Src1Name : Src2Name) << '[';
1236
1237 bool IsFirst = true;
1238 while (i != e && ShuffleMask[i] != SM_SentinelZero &&
1239 (ShuffleMask[i] < (int)e) == isSrc1) {
1240 if (!IsFirst)
1241 CS << ',';
1242 else
1243 IsFirst = false;
1244 if (ShuffleMask[i] == SM_SentinelUndef)
1245 CS << "u";
1246 else
1247 CS << ShuffleMask[i] % (int)e;
1248 ++i;
1249 }
1250 CS << ']';
1251 --i; // For loop increments element #.
1252 }
1253 CS.flush();
1254
1255 return Comment;
1256}
1257
1258void X86AsmPrinter::EmitInstruction(const MachineInstr *MI) {
1259 X86MCInstLower MCInstLowering(*MF, *this);
1260 const X86RegisterInfo *RI = MF->getSubtarget<X86Subtarget>().getRegisterInfo();
1261
1262 // Add a comment about EVEX-2-VEX compression for AVX-512 instrs that
1263 // are compressed from EVEX encoding to VEX encoding.
1264 if (TM.Options.MCOptions.ShowMCEncoding) {
1265 if (MI->getAsmPrinterFlags() & AC_EVEX_2_VEX)
1266 OutStreamer->AddComment("EVEX TO VEX Compression ", false);
1267 }
1268
1269 switch (MI->getOpcode()) {
1270 case TargetOpcode::DBG_VALUE:
1271 llvm_unreachable("Should be handled target independently")::llvm::llvm_unreachable_internal("Should be handled target independently"
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301235/lib/Target/X86/X86MCInstLower.cpp"
, 1271)
;
1272
1273 // Emit nothing here but a comment if we can.
1274 case X86::Int_MemBarrier:
1275 OutStreamer->emitRawComment("MEMBARRIER");
1276 return;
1277
1278
1279 case X86::EH_RETURN:
1280 case X86::EH_RETURN64: {
1281 // Lower these as normal, but add some comments.
1282 unsigned Reg = MI->getOperand(0).getReg();
1283 OutStreamer->AddComment(StringRef("eh_return, addr: %") +
1284 X86ATTInstPrinter::getRegisterName(Reg));
1285 break;
1286 }
1287 case X86::CLEANUPRET: {
1288 // Lower these as normal, but add some comments.
1289 OutStreamer->AddComment("CLEANUPRET");
1290 break;
1291 }
1292
1293 case X86::CATCHRET: {
1294 // Lower these as normal, but add some comments.
1295 OutStreamer->AddComment("CATCHRET");
1296 break;
1297 }
1298
1299 case X86::TAILJMPr:
1300 case X86::TAILJMPm:
1301 case X86::TAILJMPd:
1302 case X86::TAILJMPd_CC:
1303 case X86::TAILJMPr64:
1304 case X86::TAILJMPm64:
1305 case X86::TAILJMPd64:
1306 case X86::TAILJMPd64_CC:
1307 case X86::TAILJMPr64_REX:
1308 case X86::TAILJMPm64_REX:
1309 // Lower these as normal, but add some comments.
1310 OutStreamer->AddComment("TAILCALL");
1311 break;
1312
1313 case X86::TLS_addr32:
1314 case X86::TLS_addr64:
1315 case X86::TLS_base_addr32:
1316 case X86::TLS_base_addr64:
1317 return LowerTlsAddr(MCInstLowering, *MI);
1318
1319 case X86::MOVPC32r: {
1320 // This is a pseudo op for a two instruction sequence with a label, which
1321 // looks like:
1322 // call "L1$pb"
1323 // "L1$pb":
1324 // popl %esi
1325
1326 // Emit the call.
1327 MCSymbol *PICBase = MF->getPICBaseSymbol();
1328 // FIXME: We would like an efficient form for this, so we don't have to do a
1329 // lot of extra uniquing.
1330 EmitAndCountInstruction(MCInstBuilder(X86::CALLpcrel32)
1331 .addExpr(MCSymbolRefExpr::create(PICBase, OutContext)));
1332
1333 const X86FrameLowering* FrameLowering =
1334 MF->getSubtarget<X86Subtarget>().getFrameLowering();
1335 bool hasFP = FrameLowering->hasFP(*MF);
1336
1337 // TODO: This is needed only if we require precise CFA.
1338 bool HasActiveDwarfFrame = OutStreamer->getNumFrameInfos() &&
1339 !OutStreamer->getDwarfFrameInfos().back().End;
1340
1341 int stackGrowth = -RI->getSlotSize();
1342
1343 if (HasActiveDwarfFrame && !hasFP) {
1344 OutStreamer->EmitCFIAdjustCfaOffset(-stackGrowth);
1345 }
1346
1347 // Emit the label.
1348 OutStreamer->EmitLabel(PICBase);
1349
1350 // popl $reg
1351 EmitAndCountInstruction(MCInstBuilder(X86::POP32r)
1352 .addReg(MI->getOperand(0).getReg()));
1353
1354 if (HasActiveDwarfFrame && !hasFP) {
1355 OutStreamer->EmitCFIAdjustCfaOffset(stackGrowth);
1356 }
1357 return;
1358 }
1359
1360 case X86::ADD32ri: {
1361 // Lower the MO_GOT_ABSOLUTE_ADDRESS form of ADD32ri.
1362 if (MI->getOperand(2).getTargetFlags() != X86II::MO_GOT_ABSOLUTE_ADDRESS)
1363 break;
1364
1365 // Okay, we have something like:
1366 // EAX = ADD32ri EAX, MO_GOT_ABSOLUTE_ADDRESS(@MYGLOBAL)
1367
1368 // For this, we want to print something like:
1369 // MYGLOBAL + (. - PICBASE)
1370 // However, we can't generate a ".", so just emit a new label here and refer
1371 // to it.
1372 MCSymbol *DotSym = OutContext.createTempSymbol();
1373 OutStreamer->EmitLabel(DotSym);
1374
1375 // Now that we have emitted the label, lower the complex operand expression.
1376 MCSymbol *OpSym = MCInstLowering.GetSymbolFromOperand(MI->getOperand(2));
1377
1378 const MCExpr *DotExpr = MCSymbolRefExpr::create(DotSym, OutContext);
1379 const MCExpr *PICBase =
1380 MCSymbolRefExpr::create(MF->getPICBaseSymbol(), OutContext);
1381 DotExpr = MCBinaryExpr::createSub(DotExpr, PICBase, OutContext);
1382
1383 DotExpr = MCBinaryExpr::createAdd(MCSymbolRefExpr::create(OpSym,OutContext),
1384 DotExpr, OutContext);
1385
1386 EmitAndCountInstruction(MCInstBuilder(X86::ADD32ri)
1387 .addReg(MI->getOperand(0).getReg())
1388 .addReg(MI->getOperand(1).getReg())
1389 .addExpr(DotExpr));
1390 return;
1391 }
1392 case TargetOpcode::STATEPOINT:
1393 return LowerSTATEPOINT(*MI, MCInstLowering);
1394
1395 case TargetOpcode::FAULTING_OP:
1396 return LowerFAULTING_OP(*MI, MCInstLowering);
1397
1398 case TargetOpcode::FENTRY_CALL:
1399 return LowerFENTRY_CALL(*MI, MCInstLowering);
1400
1401 case TargetOpcode::PATCHABLE_OP:
1402 return LowerPATCHABLE_OP(*MI, MCInstLowering);
1403
1404 case TargetOpcode::STACKMAP:
1405 return LowerSTACKMAP(*MI);
1406
1407 case TargetOpcode::PATCHPOINT:
1408 return LowerPATCHPOINT(*MI, MCInstLowering);
1409
1410 case TargetOpcode::PATCHABLE_FUNCTION_ENTER:
1411 return LowerPATCHABLE_FUNCTION_ENTER(*MI, MCInstLowering);
1412
1413 case TargetOpcode::PATCHABLE_RET:
1414 return LowerPATCHABLE_RET(*MI, MCInstLowering);
1415
1416 case TargetOpcode::PATCHABLE_TAIL_CALL:
1417 return LowerPATCHABLE_TAIL_CALL(*MI, MCInstLowering);
1418
1419 case X86::MORESTACK_RET:
1420 EmitAndCountInstruction(MCInstBuilder(getRetOpcode(*Subtarget)));
1421 return;
1422
1423 case X86::MORESTACK_RET_RESTORE_R10:
1424 // Return, then restore R10.
1425 EmitAndCountInstruction(MCInstBuilder(getRetOpcode(*Subtarget)));
1426 EmitAndCountInstruction(MCInstBuilder(X86::MOV64rr)
1427 .addReg(X86::R10)
1428 .addReg(X86::RAX));
1429 return;
1430
1431 case X86::SEH_PushReg:
1432 assert(MF->hasWinCFI() && "SEH_ instruction in function without WinCFI?")((MF->hasWinCFI() && "SEH_ instruction in function without WinCFI?"
) ? static_cast<void> (0) : __assert_fail ("MF->hasWinCFI() && \"SEH_ instruction in function without WinCFI?\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301235/lib/Target/X86/X86MCInstLower.cpp"
, 1432, __PRETTY_FUNCTION__))
;
1433 OutStreamer->EmitWinCFIPushReg(RI->getSEHRegNum(MI->getOperand(0).getImm()));
1434 return;
1435
1436 case X86::SEH_SaveReg:
1437 assert(MF->hasWinCFI() && "SEH_ instruction in function without WinCFI?")((MF->hasWinCFI() && "SEH_ instruction in function without WinCFI?"
) ? static_cast<void> (0) : __assert_fail ("MF->hasWinCFI() && \"SEH_ instruction in function without WinCFI?\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301235/lib/Target/X86/X86MCInstLower.cpp"
, 1437, __PRETTY_FUNCTION__))
;
1438 OutStreamer->EmitWinCFISaveReg(RI->getSEHRegNum(MI->getOperand(0).getImm()),
1439 MI->getOperand(1).getImm());
1440 return;
1441
1442 case X86::SEH_SaveXMM:
1443 assert(MF->hasWinCFI() && "SEH_ instruction in function without WinCFI?")((MF->hasWinCFI() && "SEH_ instruction in function without WinCFI?"
) ? static_cast<void> (0) : __assert_fail ("MF->hasWinCFI() && \"SEH_ instruction in function without WinCFI?\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301235/lib/Target/X86/X86MCInstLower.cpp"
, 1443, __PRETTY_FUNCTION__))
;
1444 OutStreamer->EmitWinCFISaveXMM(RI->getSEHRegNum(MI->getOperand(0).getImm()),
1445 MI->getOperand(1).getImm());
1446 return;
1447
1448 case X86::SEH_StackAlloc:
1449 assert(MF->hasWinCFI() && "SEH_ instruction in function without WinCFI?")((MF->hasWinCFI() && "SEH_ instruction in function without WinCFI?"
) ? static_cast<void> (0) : __assert_fail ("MF->hasWinCFI() && \"SEH_ instruction in function without WinCFI?\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301235/lib/Target/X86/X86MCInstLower.cpp"
, 1449, __PRETTY_FUNCTION__))
;
1450 OutStreamer->EmitWinCFIAllocStack(MI->getOperand(0).getImm());
1451 return;
1452
1453 case X86::SEH_SetFrame:
1454 assert(MF->hasWinCFI() && "SEH_ instruction in function without WinCFI?")((MF->hasWinCFI() && "SEH_ instruction in function without WinCFI?"
) ? static_cast<void> (0) : __assert_fail ("MF->hasWinCFI() && \"SEH_ instruction in function without WinCFI?\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301235/lib/Target/X86/X86MCInstLower.cpp"
, 1454, __PRETTY_FUNCTION__))
;
1455 OutStreamer->EmitWinCFISetFrame(RI->getSEHRegNum(MI->getOperand(0).getImm()),
1456 MI->getOperand(1).getImm());
1457 return;
1458
1459 case X86::SEH_PushFrame:
1460 assert(MF->hasWinCFI() && "SEH_ instruction in function without WinCFI?")((MF->hasWinCFI() && "SEH_ instruction in function without WinCFI?"
) ? static_cast<void> (0) : __assert_fail ("MF->hasWinCFI() && \"SEH_ instruction in function without WinCFI?\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301235/lib/Target/X86/X86MCInstLower.cpp"
, 1460, __PRETTY_FUNCTION__))
;
1461 OutStreamer->EmitWinCFIPushFrame(MI->getOperand(0).getImm());
1462 return;
1463
1464 case X86::SEH_EndPrologue:
1465 assert(MF->hasWinCFI() && "SEH_ instruction in function without WinCFI?")((MF->hasWinCFI() && "SEH_ instruction in function without WinCFI?"
) ? static_cast<void> (0) : __assert_fail ("MF->hasWinCFI() && \"SEH_ instruction in function without WinCFI?\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301235/lib/Target/X86/X86MCInstLower.cpp"
, 1465, __PRETTY_FUNCTION__))
;
1466 OutStreamer->EmitWinCFIEndProlog();
1467 return;
1468
1469 case X86::SEH_Epilogue: {
1470 assert(MF->hasWinCFI() && "SEH_ instruction in function without WinCFI?")((MF->hasWinCFI() && "SEH_ instruction in function without WinCFI?"
) ? static_cast<void> (0) : __assert_fail ("MF->hasWinCFI() && \"SEH_ instruction in function without WinCFI?\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301235/lib/Target/X86/X86MCInstLower.cpp"
, 1470, __PRETTY_FUNCTION__))
;
1471 MachineBasicBlock::const_iterator MBBI(MI);
1472 // Check if preceded by a call and emit nop if so.
1473 for (MBBI = PrevCrossBBInst(MBBI);
1474 MBBI != MachineBasicBlock::const_iterator();
1475 MBBI = PrevCrossBBInst(MBBI)) {
1476 // Conservatively assume that pseudo instructions don't emit code and keep
1477 // looking for a call. We may emit an unnecessary nop in some cases.
1478 if (!MBBI->isPseudo()) {
1479 if (MBBI->isCall())
1480 EmitAndCountInstruction(MCInstBuilder(X86::NOOP));
1481 break;
1482 }
1483 }
1484 return;
1485 }
1486
1487 // Lower PSHUFB and VPERMILP normally but add a comment if we can find
1488 // a constant shuffle mask. We won't be able to do this at the MC layer
1489 // because the mask isn't an immediate.
1490 case X86::PSHUFBrm:
1491 case X86::VPSHUFBrm:
1492 case X86::VPSHUFBYrm:
1493 case X86::VPSHUFBZ128rm:
1494 case X86::VPSHUFBZ128rmk:
1495 case X86::VPSHUFBZ128rmkz:
1496 case X86::VPSHUFBZ256rm:
1497 case X86::VPSHUFBZ256rmk:
1498 case X86::VPSHUFBZ256rmkz:
1499 case X86::VPSHUFBZrm:
1500 case X86::VPSHUFBZrmk:
1501 case X86::VPSHUFBZrmkz: {
1502 if (!OutStreamer->isVerboseAsm())
1503 break;
1504 unsigned SrcIdx, MaskIdx;
1505 switch (MI->getOpcode()) {
1506 default: llvm_unreachable("Invalid opcode")::llvm::llvm_unreachable_internal("Invalid opcode", "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301235/lib/Target/X86/X86MCInstLower.cpp"
, 1506)
;
1507 case X86::PSHUFBrm:
1508 case X86::VPSHUFBrm:
1509 case X86::VPSHUFBYrm:
1510 case X86::VPSHUFBZ128rm:
1511 case X86::VPSHUFBZ256rm:
1512 case X86::VPSHUFBZrm:
1513 SrcIdx = 1; MaskIdx = 5; break;
1514 case X86::VPSHUFBZ128rmkz:
1515 case X86::VPSHUFBZ256rmkz:
1516 case X86::VPSHUFBZrmkz:
1517 SrcIdx = 2; MaskIdx = 6; break;
1518 case X86::VPSHUFBZ128rmk:
1519 case X86::VPSHUFBZ256rmk:
1520 case X86::VPSHUFBZrmk:
1521 SrcIdx = 3; MaskIdx = 7; break;
1522 }
1523
1524 assert(MI->getNumOperands() >= 6 &&((MI->getNumOperands() >= 6 && "We should always have at least 6 operands!"
) ? static_cast<void> (0) : __assert_fail ("MI->getNumOperands() >= 6 && \"We should always have at least 6 operands!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301235/lib/Target/X86/X86MCInstLower.cpp"
, 1525, __PRETTY_FUNCTION__))
1525 "We should always have at least 6 operands!")((MI->getNumOperands() >= 6 && "We should always have at least 6 operands!"
) ? static_cast<void> (0) : __assert_fail ("MI->getNumOperands() >= 6 && \"We should always have at least 6 operands!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301235/lib/Target/X86/X86MCInstLower.cpp"
, 1525, __PRETTY_FUNCTION__))
;
1526
1527 const MachineOperand &MaskOp = MI->getOperand(MaskIdx);
1528 if (auto *C = getConstantFromPool(*MI, MaskOp)) {
1529 SmallVector<int, 64> Mask;
1530 DecodePSHUFBMask(C, Mask);
1531 if (!Mask.empty())
1532 OutStreamer->AddComment(getShuffleComment(MI, SrcIdx, SrcIdx, Mask),
1533 !EnablePrintSchedInfo);
1534 }
1535 break;
1536 }
1537
1538 case X86::VPERMILPSrm:
1539 case X86::VPERMILPSYrm:
1540 case X86::VPERMILPSZ128rm:
1541 case X86::VPERMILPSZ128rmk:
1542 case X86::VPERMILPSZ128rmkz:
1543 case X86::VPERMILPSZ256rm:
1544 case X86::VPERMILPSZ256rmk:
1545 case X86::VPERMILPSZ256rmkz:
1546 case X86::VPERMILPSZrm:
1547 case X86::VPERMILPSZrmk:
1548 case X86::VPERMILPSZrmkz:
1549 case X86::VPERMILPDrm:
1550 case X86::VPERMILPDYrm:
1551 case X86::VPERMILPDZ128rm:
1552 case X86::VPERMILPDZ128rmk:
1553 case X86::VPERMILPDZ128rmkz:
1554 case X86::VPERMILPDZ256rm:
1555 case X86::VPERMILPDZ256rmk:
1556 case X86::VPERMILPDZ256rmkz:
1557 case X86::VPERMILPDZrm:
1558 case X86::VPERMILPDZrmk:
1559 case X86::VPERMILPDZrmkz: {
1560 if (!OutStreamer->isVerboseAsm())
1561 break;
1562 unsigned SrcIdx, MaskIdx;
1563 unsigned ElSize;
1564 switch (MI->getOpcode()) {
1565 default: llvm_unreachable("Invalid opcode")::llvm::llvm_unreachable_internal("Invalid opcode", "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301235/lib/Target/X86/X86MCInstLower.cpp"
, 1565)
;
1566 case X86::VPERMILPSrm:
1567 case X86::VPERMILPSYrm:
1568 case X86::VPERMILPSZ128rm:
1569 case X86::VPERMILPSZ256rm:
1570 case X86::VPERMILPSZrm:
1571 SrcIdx = 1; MaskIdx = 5; ElSize = 32; break;
1572 case X86::VPERMILPSZ128rmkz:
1573 case X86::VPERMILPSZ256rmkz:
1574 case X86::VPERMILPSZrmkz:
1575 SrcIdx = 2; MaskIdx = 6; ElSize = 32; break;
1576 case X86::VPERMILPSZ128rmk:
1577 case X86::VPERMILPSZ256rmk:
1578 case X86::VPERMILPSZrmk:
1579 SrcIdx = 3; MaskIdx = 7; ElSize = 32; break;
1580 case X86::VPERMILPDrm:
1581 case X86::VPERMILPDYrm:
1582 case X86::VPERMILPDZ128rm:
1583 case X86::VPERMILPDZ256rm:
1584 case X86::VPERMILPDZrm:
1585 SrcIdx = 1; MaskIdx = 5; ElSize = 64; break;
1586 case X86::VPERMILPDZ128rmkz:
1587 case X86::VPERMILPDZ256rmkz:
1588 case X86::VPERMILPDZrmkz:
1589 SrcIdx = 2; MaskIdx = 6; ElSize = 64; break;
1590 case X86::VPERMILPDZ128rmk:
1591 case X86::VPERMILPDZ256rmk:
1592 case X86::VPERMILPDZrmk:
1593 SrcIdx = 3; MaskIdx = 7; ElSize = 64; break;
1594 }
1595
1596 assert(MI->getNumOperands() >= 6 &&((MI->getNumOperands() >= 6 && "We should always have at least 6 operands!"
) ? static_cast<void> (0) : __assert_fail ("MI->getNumOperands() >= 6 && \"We should always have at least 6 operands!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301235/lib/Target/X86/X86MCInstLower.cpp"
, 1597, __PRETTY_FUNCTION__))
1597 "We should always have at least 6 operands!")((MI->getNumOperands() >= 6 && "We should always have at least 6 operands!"
) ? static_cast<void> (0) : __assert_fail ("MI->getNumOperands() >= 6 && \"We should always have at least 6 operands!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301235/lib/Target/X86/X86MCInstLower.cpp"
, 1597, __PRETTY_FUNCTION__))
;
1598
1599 const MachineOperand &MaskOp = MI->getOperand(MaskIdx);
1600 if (auto *C = getConstantFromPool(*MI, MaskOp)) {
1601 SmallVector<int, 16> Mask;
1602 DecodeVPERMILPMask(C, ElSize, Mask);
1603 if (!Mask.empty())
1604 OutStreamer->AddComment(getShuffleComment(MI, SrcIdx, SrcIdx, Mask),
1605 !EnablePrintSchedInfo);
1606 }
1607 break;
1608 }
1609
1610 case X86::VPERMIL2PDrm:
1611 case X86::VPERMIL2PSrm:
1612 case X86::VPERMIL2PDYrm:
1613 case X86::VPERMIL2PSYrm: {
1614 if (!OutStreamer->isVerboseAsm())
1615 break;
1616 assert(MI->getNumOperands() >= 8 &&((MI->getNumOperands() >= 8 && "We should always have at least 8 operands!"
) ? static_cast<void> (0) : __assert_fail ("MI->getNumOperands() >= 8 && \"We should always have at least 8 operands!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301235/lib/Target/X86/X86MCInstLower.cpp"
, 1617, __PRETTY_FUNCTION__))
1617 "We should always have at least 8 operands!")((MI->getNumOperands() >= 8 && "We should always have at least 8 operands!"
) ? static_cast<void> (0) : __assert_fail ("MI->getNumOperands() >= 8 && \"We should always have at least 8 operands!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301235/lib/Target/X86/X86MCInstLower.cpp"
, 1617, __PRETTY_FUNCTION__))
;
1618
1619 const MachineOperand &CtrlOp = MI->getOperand(MI->getNumOperands() - 1);
1620 if (!CtrlOp.isImm())
1621 break;
1622
1623 unsigned ElSize;
1624 switch (MI->getOpcode()) {
1625 default: llvm_unreachable("Invalid opcode")::llvm::llvm_unreachable_internal("Invalid opcode", "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301235/lib/Target/X86/X86MCInstLower.cpp"
, 1625)
;
1626 case X86::VPERMIL2PSrm: case X86::VPERMIL2PSYrm: ElSize = 32; break;
1627 case X86::VPERMIL2PDrm: case X86::VPERMIL2PDYrm: ElSize = 64; break;
1628 }
1629
1630 const MachineOperand &MaskOp = MI->getOperand(6);
1631 if (auto *C = getConstantFromPool(*MI, MaskOp)) {
1632 SmallVector<int, 16> Mask;
1633 DecodeVPERMIL2PMask(C, (unsigned)CtrlOp.getImm(), ElSize, Mask);
1634 if (!Mask.empty())
1635 OutStreamer->AddComment(getShuffleComment(MI, 1, 2, Mask),
1636 !EnablePrintSchedInfo);
1637 }
1638 break;
1639 }
1640
1641 case X86::VPPERMrrm: {
1642 if (!OutStreamer->isVerboseAsm())
1643 break;
1644 assert(MI->getNumOperands() >= 7 &&((MI->getNumOperands() >= 7 && "We should always have at least 7 operands!"
) ? static_cast<void> (0) : __assert_fail ("MI->getNumOperands() >= 7 && \"We should always have at least 7 operands!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301235/lib/Target/X86/X86MCInstLower.cpp"
, 1645, __PRETTY_FUNCTION__))
1645 "We should always have at least 7 operands!")((MI->getNumOperands() >= 7 && "We should always have at least 7 operands!"
) ? static_cast<void> (0) : __assert_fail ("MI->getNumOperands() >= 7 && \"We should always have at least 7 operands!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301235/lib/Target/X86/X86MCInstLower.cpp"
, 1645, __PRETTY_FUNCTION__))
;
1646
1647 const MachineOperand &MaskOp = MI->getOperand(6);
1648 if (auto *C = getConstantFromPool(*MI, MaskOp)) {
1649 SmallVector<int, 16> Mask;
1650 DecodeVPPERMMask(C, Mask);
1651 if (!Mask.empty())
1652 OutStreamer->AddComment(getShuffleComment(MI, 1, 2, Mask),
1653 !EnablePrintSchedInfo);
1654 }
1655 break;
1656 }
1657
1658#define MOV_CASE(Prefix, Suffix)case X86::PrefixMOVAPDSuffixrm: case X86::PrefixMOVAPSSuffixrm
: case X86::PrefixMOVUPDSuffixrm: case X86::PrefixMOVUPSSuffixrm
: case X86::PrefixMOVDQASuffixrm: case X86::PrefixMOVDQUSuffixrm
:
\
1659 case X86::Prefix##MOVAPD##Suffix##rm: \
1660 case X86::Prefix##MOVAPS##Suffix##rm: \
1661 case X86::Prefix##MOVUPD##Suffix##rm: \
1662 case X86::Prefix##MOVUPS##Suffix##rm: \
1663 case X86::Prefix##MOVDQA##Suffix##rm: \
1664 case X86::Prefix##MOVDQU##Suffix##rm:
1665
1666#define MOV_AVX512_CASE(Suffix)case X86::VMOVDQA64Suffixrm: case X86::VMOVDQA32Suffixrm: case
X86::VMOVDQU64Suffixrm: case X86::VMOVDQU32Suffixrm: case X86
::VMOVDQU16Suffixrm: case X86::VMOVDQU8Suffixrm: case X86::VMOVAPSSuffixrm
: case X86::VMOVAPDSuffixrm: case X86::VMOVUPSSuffixrm: case X86
::VMOVUPDSuffixrm:
\
1667 case X86::VMOVDQA64##Suffix##rm: \
1668 case X86::VMOVDQA32##Suffix##rm: \
1669 case X86::VMOVDQU64##Suffix##rm: \
1670 case X86::VMOVDQU32##Suffix##rm: \
1671 case X86::VMOVDQU16##Suffix##rm: \
1672 case X86::VMOVDQU8##Suffix##rm: \
1673 case X86::VMOVAPS##Suffix##rm: \
1674 case X86::VMOVAPD##Suffix##rm: \
1675 case X86::VMOVUPS##Suffix##rm: \
1676 case X86::VMOVUPD##Suffix##rm:
1677
1678#define CASE_ALL_MOV_RM()case X86::MOVAPDrm: case X86::MOVAPSrm: case X86::MOVUPDrm: case
X86::MOVUPSrm: case X86::MOVDQArm: case X86::MOVDQUrm: case X86
::VMOVAPDrm: case X86::VMOVAPSrm: case X86::VMOVUPDrm: case X86
::VMOVUPSrm: case X86::VMOVDQArm: case X86::VMOVDQUrm: case X86
::VMOVAPDYrm: case X86::VMOVAPSYrm: case X86::VMOVUPDYrm: case
X86::VMOVUPSYrm: case X86::VMOVDQAYrm: case X86::VMOVDQUYrm:
case X86::VMOVDQA64Zrm: case X86::VMOVDQA32Zrm: case X86::VMOVDQU64Zrm
: case X86::VMOVDQU32Zrm: case X86::VMOVDQU16Zrm: case X86::VMOVDQU8Zrm
: case X86::VMOVAPSZrm: case X86::VMOVAPDZrm: case X86::VMOVUPSZrm
: case X86::VMOVUPDZrm: case X86::VMOVDQA64Z256rm: case X86::
VMOVDQA32Z256rm: case X86::VMOVDQU64Z256rm: case X86::VMOVDQU32Z256rm
: case X86::VMOVDQU16Z256rm: case X86::VMOVDQU8Z256rm: case X86
::VMOVAPSZ256rm: case X86::VMOVAPDZ256rm: case X86::VMOVUPSZ256rm
: case X86::VMOVUPDZ256rm: case X86::VMOVDQA64Z128rm: case X86
::VMOVDQA32Z128rm: case X86::VMOVDQU64Z128rm: case X86::VMOVDQU32Z128rm
: case X86::VMOVDQU16Z128rm: case X86::VMOVDQU8Z128rm: case X86
::VMOVAPSZ128rm: case X86::VMOVAPDZ128rm: case X86::VMOVUPSZ128rm
: case X86::VMOVUPDZ128rm:
\
1679 MOV_CASE(, )case X86::MOVAPDrm: case X86::MOVAPSrm: case X86::MOVUPDrm: case
X86::MOVUPSrm: case X86::MOVDQArm: case X86::MOVDQUrm:
/* SSE */ \
1680 MOV_CASE(V, )case X86::VMOVAPDrm: case X86::VMOVAPSrm: case X86::VMOVUPDrm
: case X86::VMOVUPSrm: case X86::VMOVDQArm: case X86::VMOVDQUrm
:
/* AVX-128 */ \
1681 MOV_CASE(V, Y)case X86::VMOVAPDYrm: case X86::VMOVAPSYrm: case X86::VMOVUPDYrm
: case X86::VMOVUPSYrm: case X86::VMOVDQAYrm: case X86::VMOVDQUYrm
:
/* AVX-256 */ \
1682 MOV_AVX512_CASE(Z)case X86::VMOVDQA64Zrm: case X86::VMOVDQA32Zrm: case X86::VMOVDQU64Zrm
: case X86::VMOVDQU32Zrm: case X86::VMOVDQU16Zrm: case X86::VMOVDQU8Zrm
: case X86::VMOVAPSZrm: case X86::VMOVAPDZrm: case X86::VMOVUPSZrm
: case X86::VMOVUPDZrm:
\
1683 MOV_AVX512_CASE(Z256)case X86::VMOVDQA64Z256rm: case X86::VMOVDQA32Z256rm: case X86
::VMOVDQU64Z256rm: case X86::VMOVDQU32Z256rm: case X86::VMOVDQU16Z256rm
: case X86::VMOVDQU8Z256rm: case X86::VMOVAPSZ256rm: case X86
::VMOVAPDZ256rm: case X86::VMOVUPSZ256rm: case X86::VMOVUPDZ256rm
:
\
1684 MOV_AVX512_CASE(Z128)case X86::VMOVDQA64Z128rm: case X86::VMOVDQA32Z128rm: case X86
::VMOVDQU64Z128rm: case X86::VMOVDQU32Z128rm: case X86::VMOVDQU16Z128rm
: case X86::VMOVDQU8Z128rm: case X86::VMOVAPSZ128rm: case X86
::VMOVAPDZ128rm: case X86::VMOVUPSZ128rm: case X86::VMOVUPDZ128rm
:
1685
1686 // For loads from a constant pool to a vector register, print the constant
1687 // loaded.
1688 CASE_ALL_MOV_RM()case X86::MOVAPDrm: case X86::MOVAPSrm: case X86::MOVUPDrm: case
X86::MOVUPSrm: case X86::MOVDQArm: case X86::MOVDQUrm: case X86
::VMOVAPDrm: case X86::VMOVAPSrm: case X86::VMOVUPDrm: case X86
::VMOVUPSrm: case X86::VMOVDQArm: case X86::VMOVDQUrm: case X86
::VMOVAPDYrm: case X86::VMOVAPSYrm: case X86::VMOVUPDYrm: case
X86::VMOVUPSYrm: case X86::VMOVDQAYrm: case X86::VMOVDQUYrm:
case X86::VMOVDQA64Zrm: case X86::VMOVDQA32Zrm: case X86::VMOVDQU64Zrm
: case X86::VMOVDQU32Zrm: case X86::VMOVDQU16Zrm: case X86::VMOVDQU8Zrm
: case X86::VMOVAPSZrm: case X86::VMOVAPDZrm: case X86::VMOVUPSZrm
: case X86::VMOVUPDZrm: case X86::VMOVDQA64Z256rm: case X86::
VMOVDQA32Z256rm: case X86::VMOVDQU64Z256rm: case X86::VMOVDQU32Z256rm
: case X86::VMOVDQU16Z256rm: case X86::VMOVDQU8Z256rm: case X86
::VMOVAPSZ256rm: case X86::VMOVAPDZ256rm: case X86::VMOVUPSZ256rm
: case X86::VMOVUPDZ256rm: case X86::VMOVDQA64Z128rm: case X86
::VMOVDQA32Z128rm: case X86::VMOVDQU64Z128rm: case X86::VMOVDQU32Z128rm
: case X86::VMOVDQU16Z128rm: case X86::VMOVDQU8Z128rm: case X86
::VMOVAPSZ128rm: case X86::VMOVAPDZ128rm: case X86::VMOVUPSZ128rm
: case X86::VMOVUPDZ128rm:
1689 if (!OutStreamer->isVerboseAsm())
1690 break;
1691 if (MI->getNumOperands() <= 4)
1692 break;
1693 if (auto *C = getConstantFromPool(*MI, MI->getOperand(4))) {
1694 std::string Comment;
1695 raw_string_ostream CS(Comment);
1696 const MachineOperand &DstOp = MI->getOperand(0);
1697 CS << X86ATTInstPrinter::getRegisterName(DstOp.getReg()) << " = ";
1698 if (auto *CDS = dyn_cast<ConstantDataSequential>(C)) {
1699 CS << "[";
1700 for (int i = 0, NumElements = CDS->getNumElements(); i < NumElements; ++i) {
1701 if (i != 0)
1702 CS << ",";
1703 if (CDS->getElementType()->isIntegerTy())
1704 CS << CDS->getElementAsInteger(i);
1705 else if (CDS->getElementType()->isFloatTy())
1706 CS << CDS->getElementAsFloat(i);
1707 else if (CDS->getElementType()->isDoubleTy())
1708 CS << CDS->getElementAsDouble(i);
1709 else
1710 CS << "?";
1711 }
1712 CS << "]";
1713 OutStreamer->AddComment(CS.str(), !EnablePrintSchedInfo);
1714 } else if (auto *CV = dyn_cast<ConstantVector>(C)) {
1715 CS << "<";
1716 for (int i = 0, NumOperands = CV->getNumOperands(); i < NumOperands; ++i) {
1717 if (i != 0)
1718 CS << ",";
1719 Constant *COp = CV->getOperand(i);
1720 if (isa<UndefValue>(COp)) {
1721 CS << "u";
1722 } else if (auto *CI = dyn_cast<ConstantInt>(COp)) {
1723 if (CI->getBitWidth() <= 64) {
1724 CS << CI->getZExtValue();
1725 } else {
1726 // print multi-word constant as (w0,w1)
1727 const auto &Val = CI->getValue();
1728 CS << "(";
1729 for (int i = 0, N = Val.getNumWords(); i < N; ++i) {
1730 if (i > 0)
1731 CS << ",";
1732 CS << Val.getRawData()[i];
1733 }
1734 CS << ")";
1735 }
1736 } else if (auto *CF = dyn_cast<ConstantFP>(COp)) {
1737 SmallString<32> Str;
1738 CF->getValueAPF().toString(Str);
1739 CS << Str;
1740 } else {
1741 CS << "?";
1742 }
1743 }
1744 CS << ">";
1745 OutStreamer->AddComment(CS.str(), !EnablePrintSchedInfo);
1746 }
1747 }
1748 break;
1749 }
1750
1751 MCInst TmpInst;
1752 MCInstLowering.Lower(MI, TmpInst);
1753
1754 // Stackmap shadows cannot include branch targets, so we can count the bytes
1755 // in a call towards the shadow, but must ensure that the no thread returns
1756 // in to the stackmap shadow. The only way to achieve this is if the call
1757 // is at the end of the shadow.
1758 if (MI->isCall()) {
1759 // Count then size of the call towards the shadow
1760 SMShadowTracker.count(TmpInst, getSubtargetInfo(), CodeEmitter.get());
1761 // Then flush the shadow so that we fill with nops before the call, not
1762 // after it.
1763 SMShadowTracker.emitShadowPadding(*OutStreamer, getSubtargetInfo());
1764 // Then emit the call
1765 OutStreamer->EmitInstruction(TmpInst, getSubtargetInfo());
1766 return;
1767 }
1768
1769 EmitAndCountInstruction(TmpInst);
1770}