Bug Summary

File:lib/Target/X86/X86TargetTransformInfo.cpp
Warning:line 708, column 52
Called C++ object pointer is null

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clang -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name X86TargetTransformInfo.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-eagerly-assume -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -mrelocation-model pic -pic-level 2 -mthread-model posix -fmath-errno -masm-verbose -mconstructor-aliases -munwind-tables -fuse-init-array -target-cpu x86-64 -dwarf-column-info -debugger-tuning=gdb -momit-leaf-frame-pointer -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-7/lib/clang/7.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-7~svn329677/build-llvm/lib/Target/X86 -I /build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86 -I /build/llvm-toolchain-snapshot-7~svn329677/build-llvm/include -I /build/llvm-toolchain-snapshot-7~svn329677/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/7.3.0/../../../../include/c++/7.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/7.3.0/../../../../include/x86_64-linux-gnu/c++/7.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/7.3.0/../../../../include/x86_64-linux-gnu/c++/7.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/7.3.0/../../../../include/c++/7.3.0/backward -internal-isystem /usr/include/clang/7.0.0/include/ -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-7/lib/clang/7.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++11 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-7~svn329677/build-llvm/lib/Target/X86 -ferror-limit 19 -fmessage-length 0 -fvisibility-inlines-hidden -fobjc-runtime=gcc -fdiagnostics-show-option -vectorize-loops -vectorize-slp -analyzer-checker optin.performance.Padding -analyzer-output=html -analyzer-config stable-report-filename=true -o /tmp/scan-build-2018-04-11-031539-24776-1 -x c++ /build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86TargetTransformInfo.cpp

/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86TargetTransformInfo.cpp

1//===-- X86TargetTransformInfo.cpp - X86 specific TTI pass ----------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9/// \file
10/// This file implements a TargetTransformInfo analysis pass specific to the
11/// X86 target machine. It uses the target's detailed information to provide
12/// more precise answers to certain TTI queries, while letting the target
13/// independent and default TTI implementations handle the rest.
14///
15//===----------------------------------------------------------------------===//
16/// About Cost Model numbers used below it's necessary to say the following:
17/// the numbers correspond to some "generic" X86 CPU instead of usage of
18/// concrete CPU model. Usually the numbers correspond to CPU where the feature
19/// apeared at the first time. For example, if we do Subtarget.hasSSE42() in
20/// the lookups below the cost is based on Nehalem as that was the first CPU
21/// to support that feature level and thus has most likely the worst case cost.
22/// Some examples of other technologies/CPUs:
23/// SSE 3 - Pentium4 / Athlon64
24/// SSE 4.1 - Penryn
25/// SSE 4.2 - Nehalem
26/// AVX - Sandy Bridge
27/// AVX2 - Haswell
28/// AVX-512 - Xeon Phi / Skylake
29/// And some examples of instruction target dependent costs (latency)
30/// divss sqrtss rsqrtss
31/// AMD K7 11-16 19 3
32/// Piledriver 9-24 13-15 5
33/// Jaguar 14 16 2
34/// Pentium II,III 18 30 2
35/// Nehalem 7-14 7-18 3
36/// Haswell 10-13 11 5
37/// TODO: Develop and implement the target dependent cost model and
38/// specialize cost numbers for different Cost Model Targets such as throughput,
39/// code size, latency and uop count.
40//===----------------------------------------------------------------------===//
41
42#include "X86TargetTransformInfo.h"
43#include "llvm/Analysis/TargetTransformInfo.h"
44#include "llvm/CodeGen/BasicTTIImpl.h"
45#include "llvm/CodeGen/CostTable.h"
46#include "llvm/CodeGen/TargetLowering.h"
47#include "llvm/IR/IntrinsicInst.h"
48#include "llvm/Support/Debug.h"
49
50using namespace llvm;
51
52#define DEBUG_TYPE"x86tti" "x86tti"
53
54//===----------------------------------------------------------------------===//
55//
56// X86 cost model.
57//
58//===----------------------------------------------------------------------===//
59
60TargetTransformInfo::PopcntSupportKind
61X86TTIImpl::getPopcntSupport(unsigned TyWidth) {
62 assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2")(static_cast <bool> (isPowerOf2_32(TyWidth) && "Ty width must be power of 2"
) ? void (0) : __assert_fail ("isPowerOf2_32(TyWidth) && \"Ty width must be power of 2\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86TargetTransformInfo.cpp"
, 62, __extension__ __PRETTY_FUNCTION__))
;
63 // TODO: Currently the __builtin_popcount() implementation using SSE3
64 // instructions is inefficient. Once the problem is fixed, we should
65 // call ST->hasSSE3() instead of ST->hasPOPCNT().
66 return ST->hasPOPCNT() ? TTI::PSK_FastHardware : TTI::PSK_Software;
67}
68
69llvm::Optional<unsigned> X86TTIImpl::getCacheSize(
70 TargetTransformInfo::CacheLevel Level) const {
71 switch (Level) {
72 case TargetTransformInfo::CacheLevel::L1D:
73 // - Penryn
74 // - Nehalem
75 // - Westmere
76 // - Sandy Bridge
77 // - Ivy Bridge
78 // - Haswell
79 // - Broadwell
80 // - Skylake
81 // - Kabylake
82 return 32 * 1024; // 32 KByte
83 case TargetTransformInfo::CacheLevel::L2D:
84 // - Penryn
85 // - Nehalem
86 // - Westmere
87 // - Sandy Bridge
88 // - Ivy Bridge
89 // - Haswell
90 // - Broadwell
91 // - Skylake
92 // - Kabylake
93 return 256 * 1024; // 256 KByte
94 }
95
96 llvm_unreachable("Unknown TargetTransformInfo::CacheLevel")::llvm::llvm_unreachable_internal("Unknown TargetTransformInfo::CacheLevel"
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86TargetTransformInfo.cpp"
, 96)
;
97}
98
99llvm::Optional<unsigned> X86TTIImpl::getCacheAssociativity(
100 TargetTransformInfo::CacheLevel Level) const {
101 // - Penryn
102 // - Nehalem
103 // - Westmere
104 // - Sandy Bridge
105 // - Ivy Bridge
106 // - Haswell
107 // - Broadwell
108 // - Skylake
109 // - Kabylake
110 switch (Level) {
111 case TargetTransformInfo::CacheLevel::L1D:
112 LLVM_FALLTHROUGH[[clang::fallthrough]];
113 case TargetTransformInfo::CacheLevel::L2D:
114 return 8;
115 }
116
117 llvm_unreachable("Unknown TargetTransformInfo::CacheLevel")::llvm::llvm_unreachable_internal("Unknown TargetTransformInfo::CacheLevel"
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86TargetTransformInfo.cpp"
, 117)
;
118}
119
120unsigned X86TTIImpl::getNumberOfRegisters(bool Vector) {
121 if (Vector && !ST->hasSSE1())
122 return 0;
123
124 if (ST->is64Bit()) {
125 if (Vector && ST->hasAVX512())
126 return 32;
127 return 16;
128 }
129 return 8;
130}
131
132unsigned X86TTIImpl::getRegisterBitWidth(bool Vector) const {
133 unsigned PreferVectorWidth = ST->getPreferVectorWidth();
134 if (Vector) {
135 if (ST->hasAVX512() && PreferVectorWidth >= 512)
136 return 512;
137 if (ST->hasAVX() && PreferVectorWidth >= 256)
138 return 256;
139 if (ST->hasSSE1() && PreferVectorWidth >= 128)
140 return 128;
141 return 0;
142 }
143
144 if (ST->is64Bit())
145 return 64;
146
147 return 32;
148}
149
150unsigned X86TTIImpl::getLoadStoreVecRegBitWidth(unsigned) const {
151 return getRegisterBitWidth(true);
152}
153
154unsigned X86TTIImpl::getMaxInterleaveFactor(unsigned VF) {
155 // If the loop will not be vectorized, don't interleave the loop.
156 // Let regular unroll to unroll the loop, which saves the overflow
157 // check and memory check cost.
158 if (VF == 1)
159 return 1;
160
161 if (ST->isAtom())
162 return 1;
163
164 // Sandybridge and Haswell have multiple execution ports and pipelined
165 // vector units.
166 if (ST->hasAVX())
167 return 4;
168
169 return 2;
170}
171
172int X86TTIImpl::getArithmeticInstrCost(
173 unsigned Opcode, Type *Ty,
174 TTI::OperandValueKind Op1Info, TTI::OperandValueKind Op2Info,
175 TTI::OperandValueProperties Opd1PropInfo,
176 TTI::OperandValueProperties Opd2PropInfo,
177 ArrayRef<const Value *> Args) {
178 // Legalize the type.
179 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty);
180
181 int ISD = TLI->InstructionOpcodeToISD(Opcode);
182 assert(ISD && "Invalid opcode")(static_cast <bool> (ISD && "Invalid opcode") ?
void (0) : __assert_fail ("ISD && \"Invalid opcode\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86TargetTransformInfo.cpp"
, 182, __extension__ __PRETTY_FUNCTION__))
;
183
184 static const CostTblEntry GLMCostTable[] = {
185 { ISD::FDIV, MVT::f32, 18 }, // divss
186 { ISD::FDIV, MVT::v4f32, 35 }, // divps
187 { ISD::FDIV, MVT::f64, 33 }, // divsd
188 { ISD::FDIV, MVT::v2f64, 65 }, // divpd
189 };
190
191 if (ST->isGLM())
192 if (const auto *Entry = CostTableLookup(GLMCostTable, ISD,
193 LT.second))
194 return LT.first * Entry->Cost;
195
196 static const CostTblEntry SLMCostTable[] = {
197 { ISD::MUL, MVT::v4i32, 11 }, // pmulld
198 { ISD::MUL, MVT::v8i16, 2 }, // pmullw
199 { ISD::MUL, MVT::v16i8, 14 }, // extend/pmullw/trunc sequence.
200 { ISD::FMUL, MVT::f64, 2 }, // mulsd
201 { ISD::FMUL, MVT::v2f64, 4 }, // mulpd
202 { ISD::FMUL, MVT::v4f32, 2 }, // mulps
203 { ISD::FDIV, MVT::f32, 17 }, // divss
204 { ISD::FDIV, MVT::v4f32, 39 }, // divps
205 { ISD::FDIV, MVT::f64, 32 }, // divsd
206 { ISD::FDIV, MVT::v2f64, 69 }, // divpd
207 { ISD::FADD, MVT::v2f64, 2 }, // addpd
208 { ISD::FSUB, MVT::v2f64, 2 }, // subpd
209 // v2i64/v4i64 mul is custom lowered as a series of long:
210 // multiplies(3), shifts(3) and adds(2)
211 // slm muldq version throughput is 2 and addq throughput 4
212 // thus: 3X2 (muldq throughput) + 3X1 (shift throughput) +
213 // 3X4 (addq throughput) = 17
214 { ISD::MUL, MVT::v2i64, 17 },
215 // slm addq\subq throughput is 4
216 { ISD::ADD, MVT::v2i64, 4 },
217 { ISD::SUB, MVT::v2i64, 4 },
218 };
219
220 if (ST->isSLM()) {
221 if (Args.size() == 2 && ISD == ISD::MUL && LT.second == MVT::v4i32) {
222 // Check if the operands can be shrinked into a smaller datatype.
223 bool Op1Signed = false;
224 unsigned Op1MinSize = BaseT::minRequiredElementSize(Args[0], Op1Signed);
225 bool Op2Signed = false;
226 unsigned Op2MinSize = BaseT::minRequiredElementSize(Args[1], Op2Signed);
227
228 bool signedMode = Op1Signed | Op2Signed;
229 unsigned OpMinSize = std::max(Op1MinSize, Op2MinSize);
230
231 if (OpMinSize <= 7)
232 return LT.first * 3; // pmullw/sext
233 if (!signedMode && OpMinSize <= 8)
234 return LT.first * 3; // pmullw/zext
235 if (OpMinSize <= 15)
236 return LT.first * 5; // pmullw/pmulhw/pshuf
237 if (!signedMode && OpMinSize <= 16)
238 return LT.first * 5; // pmullw/pmulhw/pshuf
239 }
240
241 if (const auto *Entry = CostTableLookup(SLMCostTable, ISD,
242 LT.second)) {
243 return LT.first * Entry->Cost;
244 }
245 }
246
247 if (ISD == ISD::SDIV &&
248 Op2Info == TargetTransformInfo::OK_UniformConstantValue &&
249 Opd2PropInfo == TargetTransformInfo::OP_PowerOf2) {
250 // On X86, vector signed division by constants power-of-two are
251 // normally expanded to the sequence SRA + SRL + ADD + SRA.
252 // The OperandValue properties many not be same as that of previous
253 // operation;conservatively assume OP_None.
254 int Cost = 2 * getArithmeticInstrCost(Instruction::AShr, Ty, Op1Info,
255 Op2Info, TargetTransformInfo::OP_None,
256 TargetTransformInfo::OP_None);
257 Cost += getArithmeticInstrCost(Instruction::LShr, Ty, Op1Info, Op2Info,
258 TargetTransformInfo::OP_None,
259 TargetTransformInfo::OP_None);
260 Cost += getArithmeticInstrCost(Instruction::Add, Ty, Op1Info, Op2Info,
261 TargetTransformInfo::OP_None,
262 TargetTransformInfo::OP_None);
263
264 return Cost;
265 }
266
267 static const CostTblEntry AVX512BWUniformConstCostTable[] = {
268 { ISD::SHL, MVT::v64i8, 2 }, // psllw + pand.
269 { ISD::SRL, MVT::v64i8, 2 }, // psrlw + pand.
270 { ISD::SRA, MVT::v64i8, 4 }, // psrlw, pand, pxor, psubb.
271
272 { ISD::SDIV, MVT::v32i16, 6 }, // vpmulhw sequence
273 { ISD::UDIV, MVT::v32i16, 6 }, // vpmulhuw sequence
274 };
275
276 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue &&
277 ST->hasBWI()) {
278 if (const auto *Entry = CostTableLookup(AVX512BWUniformConstCostTable, ISD,
279 LT.second))
280 return LT.first * Entry->Cost;
281 }
282
283 static const CostTblEntry AVX512UniformConstCostTable[] = {
284 { ISD::SRA, MVT::v2i64, 1 },
285 { ISD::SRA, MVT::v4i64, 1 },
286 { ISD::SRA, MVT::v8i64, 1 },
287
288 { ISD::SDIV, MVT::v16i32, 15 }, // vpmuldq sequence
289 { ISD::UDIV, MVT::v16i32, 15 }, // vpmuludq sequence
290 };
291
292 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue &&
293 ST->hasAVX512()) {
294 if (const auto *Entry = CostTableLookup(AVX512UniformConstCostTable, ISD,
295 LT.second))
296 return LT.first * Entry->Cost;
297 }
298
299 static const CostTblEntry AVX2UniformConstCostTable[] = {
300 { ISD::SHL, MVT::v32i8, 2 }, // psllw + pand.
301 { ISD::SRL, MVT::v32i8, 2 }, // psrlw + pand.
302 { ISD::SRA, MVT::v32i8, 4 }, // psrlw, pand, pxor, psubb.
303
304 { ISD::SRA, MVT::v4i64, 4 }, // 2 x psrad + shuffle.
305
306 { ISD::SDIV, MVT::v16i16, 6 }, // vpmulhw sequence
307 { ISD::UDIV, MVT::v16i16, 6 }, // vpmulhuw sequence
308 { ISD::SDIV, MVT::v8i32, 15 }, // vpmuldq sequence
309 { ISD::UDIV, MVT::v8i32, 15 }, // vpmuludq sequence
310 };
311
312 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue &&
313 ST->hasAVX2()) {
314 if (const auto *Entry = CostTableLookup(AVX2UniformConstCostTable, ISD,
315 LT.second))
316 return LT.first * Entry->Cost;
317 }
318
319 static const CostTblEntry SSE2UniformConstCostTable[] = {
320 { ISD::SHL, MVT::v16i8, 2 }, // psllw + pand.
321 { ISD::SRL, MVT::v16i8, 2 }, // psrlw + pand.
322 { ISD::SRA, MVT::v16i8, 4 }, // psrlw, pand, pxor, psubb.
323
324 { ISD::SHL, MVT::v32i8, 4+2 }, // 2*(psllw + pand) + split.
325 { ISD::SRL, MVT::v32i8, 4+2 }, // 2*(psrlw + pand) + split.
326 { ISD::SRA, MVT::v32i8, 8+2 }, // 2*(psrlw, pand, pxor, psubb) + split.
327
328 { ISD::SDIV, MVT::v16i16, 12+2 }, // 2*pmulhw sequence + split.
329 { ISD::SDIV, MVT::v8i16, 6 }, // pmulhw sequence
330 { ISD::UDIV, MVT::v16i16, 12+2 }, // 2*pmulhuw sequence + split.
331 { ISD::UDIV, MVT::v8i16, 6 }, // pmulhuw sequence
332 { ISD::SDIV, MVT::v8i32, 38+2 }, // 2*pmuludq sequence + split.
333 { ISD::SDIV, MVT::v4i32, 19 }, // pmuludq sequence
334 { ISD::UDIV, MVT::v8i32, 30+2 }, // 2*pmuludq sequence + split.
335 { ISD::UDIV, MVT::v4i32, 15 }, // pmuludq sequence
336 };
337
338 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue &&
339 ST->hasSSE2()) {
340 // pmuldq sequence.
341 if (ISD == ISD::SDIV && LT.second == MVT::v8i32 && ST->hasAVX())
342 return LT.first * 32;
343 if (ISD == ISD::SDIV && LT.second == MVT::v4i32 && ST->hasSSE41())
344 return LT.first * 15;
345
346 // XOP has faster vXi8 shifts.
347 if ((ISD != ISD::SHL && ISD != ISD::SRL && ISD != ISD::SRA) ||
348 !ST->hasXOP())
349 if (const auto *Entry =
350 CostTableLookup(SSE2UniformConstCostTable, ISD, LT.second))
351 return LT.first * Entry->Cost;
352 }
353
354 static const CostTblEntry AVX2UniformCostTable[] = {
355 // Uniform splats are cheaper for the following instructions.
356 { ISD::SHL, MVT::v16i16, 1 }, // psllw.
357 { ISD::SRL, MVT::v16i16, 1 }, // psrlw.
358 { ISD::SRA, MVT::v16i16, 1 }, // psraw.
359 };
360
361 if (ST->hasAVX2() &&
362 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) ||
363 (Op2Info == TargetTransformInfo::OK_UniformValue))) {
364 if (const auto *Entry =
365 CostTableLookup(AVX2UniformCostTable, ISD, LT.second))
366 return LT.first * Entry->Cost;
367 }
368
369 static const CostTblEntry SSE2UniformCostTable[] = {
370 // Uniform splats are cheaper for the following instructions.
371 { ISD::SHL, MVT::v8i16, 1 }, // psllw.
372 { ISD::SHL, MVT::v4i32, 1 }, // pslld
373 { ISD::SHL, MVT::v2i64, 1 }, // psllq.
374
375 { ISD::SRL, MVT::v8i16, 1 }, // psrlw.
376 { ISD::SRL, MVT::v4i32, 1 }, // psrld.
377 { ISD::SRL, MVT::v2i64, 1 }, // psrlq.
378
379 { ISD::SRA, MVT::v8i16, 1 }, // psraw.
380 { ISD::SRA, MVT::v4i32, 1 }, // psrad.
381 };
382
383 if (ST->hasSSE2() &&
384 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) ||
385 (Op2Info == TargetTransformInfo::OK_UniformValue))) {
386 if (const auto *Entry =
387 CostTableLookup(SSE2UniformCostTable, ISD, LT.second))
388 return LT.first * Entry->Cost;
389 }
390
391 static const CostTblEntry AVX512DQCostTable[] = {
392 { ISD::MUL, MVT::v2i64, 1 },
393 { ISD::MUL, MVT::v4i64, 1 },
394 { ISD::MUL, MVT::v8i64, 1 }
395 };
396
397 // Look for AVX512DQ lowering tricks for custom cases.
398 if (ST->hasDQI())
399 if (const auto *Entry = CostTableLookup(AVX512DQCostTable, ISD, LT.second))
400 return LT.first * Entry->Cost;
401
402 static const CostTblEntry AVX512BWCostTable[] = {
403 { ISD::SHL, MVT::v8i16, 1 }, // vpsllvw
404 { ISD::SRL, MVT::v8i16, 1 }, // vpsrlvw
405 { ISD::SRA, MVT::v8i16, 1 }, // vpsravw
406
407 { ISD::SHL, MVT::v16i16, 1 }, // vpsllvw
408 { ISD::SRL, MVT::v16i16, 1 }, // vpsrlvw
409 { ISD::SRA, MVT::v16i16, 1 }, // vpsravw
410
411 { ISD::SHL, MVT::v32i16, 1 }, // vpsllvw
412 { ISD::SRL, MVT::v32i16, 1 }, // vpsrlvw
413 { ISD::SRA, MVT::v32i16, 1 }, // vpsravw
414
415 { ISD::SHL, MVT::v64i8, 11 }, // vpblendvb sequence.
416 { ISD::SRL, MVT::v64i8, 11 }, // vpblendvb sequence.
417 { ISD::SRA, MVT::v64i8, 24 }, // vpblendvb sequence.
418
419 { ISD::MUL, MVT::v64i8, 11 }, // extend/pmullw/trunc sequence.
420 { ISD::MUL, MVT::v32i8, 4 }, // extend/pmullw/trunc sequence.
421 { ISD::MUL, MVT::v16i8, 4 }, // extend/pmullw/trunc sequence.
422
423 // Vectorizing division is a bad idea. See the SSE2 table for more comments.
424 { ISD::SDIV, MVT::v64i8, 64*20 },
425 { ISD::SDIV, MVT::v32i16, 32*20 },
426 { ISD::UDIV, MVT::v64i8, 64*20 },
427 { ISD::UDIV, MVT::v32i16, 32*20 }
428 };
429
430 // Look for AVX512BW lowering tricks for custom cases.
431 if (ST->hasBWI())
432 if (const auto *Entry = CostTableLookup(AVX512BWCostTable, ISD, LT.second))
433 return LT.first * Entry->Cost;
434
435 static const CostTblEntry AVX512CostTable[] = {
436 { ISD::SHL, MVT::v16i32, 1 },
437 { ISD::SRL, MVT::v16i32, 1 },
438 { ISD::SRA, MVT::v16i32, 1 },
439
440 { ISD::SHL, MVT::v8i64, 1 },
441 { ISD::SRL, MVT::v8i64, 1 },
442
443 { ISD::SRA, MVT::v2i64, 1 },
444 { ISD::SRA, MVT::v4i64, 1 },
445 { ISD::SRA, MVT::v8i64, 1 },
446
447 { ISD::MUL, MVT::v32i8, 13 }, // extend/pmullw/trunc sequence.
448 { ISD::MUL, MVT::v16i8, 5 }, // extend/pmullw/trunc sequence.
449 { ISD::MUL, MVT::v16i32, 1 }, // pmulld (Skylake from agner.org)
450 { ISD::MUL, MVT::v8i32, 1 }, // pmulld (Skylake from agner.org)
451 { ISD::MUL, MVT::v4i32, 1 }, // pmulld (Skylake from agner.org)
452 { ISD::MUL, MVT::v8i64, 8 }, // 3*pmuludq/3*shift/2*add
453
454 { ISD::FADD, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/
455 { ISD::FSUB, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/
456 { ISD::FMUL, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/
457
458 { ISD::FADD, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/
459 { ISD::FSUB, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/
460 { ISD::FMUL, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/
461
462 // Vectorizing division is a bad idea. See the SSE2 table for more comments.
463 { ISD::SDIV, MVT::v16i32, 16*20 },
464 { ISD::SDIV, MVT::v8i64, 8*20 },
465 { ISD::UDIV, MVT::v16i32, 16*20 },
466 { ISD::UDIV, MVT::v8i64, 8*20 }
467 };
468
469 if (ST->hasAVX512())
470 if (const auto *Entry = CostTableLookup(AVX512CostTable, ISD, LT.second))
471 return LT.first * Entry->Cost;
472
473 static const CostTblEntry AVX2ShiftCostTable[] = {
474 // Shifts on v4i64/v8i32 on AVX2 is legal even though we declare to
475 // customize them to detect the cases where shift amount is a scalar one.
476 { ISD::SHL, MVT::v4i32, 1 },
477 { ISD::SRL, MVT::v4i32, 1 },
478 { ISD::SRA, MVT::v4i32, 1 },
479 { ISD::SHL, MVT::v8i32, 1 },
480 { ISD::SRL, MVT::v8i32, 1 },
481 { ISD::SRA, MVT::v8i32, 1 },
482 { ISD::SHL, MVT::v2i64, 1 },
483 { ISD::SRL, MVT::v2i64, 1 },
484 { ISD::SHL, MVT::v4i64, 1 },
485 { ISD::SRL, MVT::v4i64, 1 },
486 };
487
488 // Look for AVX2 lowering tricks.
489 if (ST->hasAVX2()) {
490 if (ISD == ISD::SHL && LT.second == MVT::v16i16 &&
491 (Op2Info == TargetTransformInfo::OK_UniformConstantValue ||
492 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue))
493 // On AVX2, a packed v16i16 shift left by a constant build_vector
494 // is lowered into a vector multiply (vpmullw).
495 return LT.first;
496
497 if (const auto *Entry = CostTableLookup(AVX2ShiftCostTable, ISD, LT.second))
498 return LT.first * Entry->Cost;
499 }
500
501 static const CostTblEntry XOPShiftCostTable[] = {
502 // 128bit shifts take 1cy, but right shifts require negation beforehand.
503 { ISD::SHL, MVT::v16i8, 1 },
504 { ISD::SRL, MVT::v16i8, 2 },
505 { ISD::SRA, MVT::v16i8, 2 },
506 { ISD::SHL, MVT::v8i16, 1 },
507 { ISD::SRL, MVT::v8i16, 2 },
508 { ISD::SRA, MVT::v8i16, 2 },
509 { ISD::SHL, MVT::v4i32, 1 },
510 { ISD::SRL, MVT::v4i32, 2 },
511 { ISD::SRA, MVT::v4i32, 2 },
512 { ISD::SHL, MVT::v2i64, 1 },
513 { ISD::SRL, MVT::v2i64, 2 },
514 { ISD::SRA, MVT::v2i64, 2 },
515 // 256bit shifts require splitting if AVX2 didn't catch them above.
516 { ISD::SHL, MVT::v32i8, 2+2 },
517 { ISD::SRL, MVT::v32i8, 4+2 },
518 { ISD::SRA, MVT::v32i8, 4+2 },
519 { ISD::SHL, MVT::v16i16, 2+2 },
520 { ISD::SRL, MVT::v16i16, 4+2 },
521 { ISD::SRA, MVT::v16i16, 4+2 },
522 { ISD::SHL, MVT::v8i32, 2+2 },
523 { ISD::SRL, MVT::v8i32, 4+2 },
524 { ISD::SRA, MVT::v8i32, 4+2 },
525 { ISD::SHL, MVT::v4i64, 2+2 },
526 { ISD::SRL, MVT::v4i64, 4+2 },
527 { ISD::SRA, MVT::v4i64, 4+2 },
528 };
529
530 // Look for XOP lowering tricks.
531 if (ST->hasXOP())
532 if (const auto *Entry = CostTableLookup(XOPShiftCostTable, ISD, LT.second))
533 return LT.first * Entry->Cost;
534
535 static const CostTblEntry SSE2UniformShiftCostTable[] = {
536 // Uniform splats are cheaper for the following instructions.
537 { ISD::SHL, MVT::v16i16, 2+2 }, // 2*psllw + split.
538 { ISD::SHL, MVT::v8i32, 2+2 }, // 2*pslld + split.
539 { ISD::SHL, MVT::v4i64, 2+2 }, // 2*psllq + split.
540
541 { ISD::SRL, MVT::v16i16, 2+2 }, // 2*psrlw + split.
542 { ISD::SRL, MVT::v8i32, 2+2 }, // 2*psrld + split.
543 { ISD::SRL, MVT::v4i64, 2+2 }, // 2*psrlq + split.
544
545 { ISD::SRA, MVT::v16i16, 2+2 }, // 2*psraw + split.
546 { ISD::SRA, MVT::v8i32, 2+2 }, // 2*psrad + split.
547 { ISD::SRA, MVT::v2i64, 4 }, // 2*psrad + shuffle.
548 { ISD::SRA, MVT::v4i64, 8+2 }, // 2*(2*psrad + shuffle) + split.
549 };
550
551 if (ST->hasSSE2() &&
552 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) ||
553 (Op2Info == TargetTransformInfo::OK_UniformValue))) {
554
555 // Handle AVX2 uniform v4i64 ISD::SRA, it's not worth a table.
556 if (ISD == ISD::SRA && LT.second == MVT::v4i64 && ST->hasAVX2())
557 return LT.first * 4; // 2*psrad + shuffle.
558
559 if (const auto *Entry =
560 CostTableLookup(SSE2UniformShiftCostTable, ISD, LT.second))
561 return LT.first * Entry->Cost;
562 }
563
564 if (ISD == ISD::SHL &&
565 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) {
566 MVT VT = LT.second;
567 // Vector shift left by non uniform constant can be lowered
568 // into vector multiply.
569 if (((VT == MVT::v8i16 || VT == MVT::v4i32) && ST->hasSSE2()) ||
570 ((VT == MVT::v16i16 || VT == MVT::v8i32) && ST->hasAVX()))
571 ISD = ISD::MUL;
572 }
573
574 static const CostTblEntry AVX2CostTable[] = {
575 { ISD::SHL, MVT::v32i8, 11 }, // vpblendvb sequence.
576 { ISD::SHL, MVT::v16i16, 10 }, // extend/vpsrlvd/pack sequence.
577
578 { ISD::SRL, MVT::v32i8, 11 }, // vpblendvb sequence.
579 { ISD::SRL, MVT::v16i16, 10 }, // extend/vpsrlvd/pack sequence.
580
581 { ISD::SRA, MVT::v32i8, 24 }, // vpblendvb sequence.
582 { ISD::SRA, MVT::v16i16, 10 }, // extend/vpsravd/pack sequence.
583 { ISD::SRA, MVT::v2i64, 4 }, // srl/xor/sub sequence.
584 { ISD::SRA, MVT::v4i64, 4 }, // srl/xor/sub sequence.
585
586 { ISD::SUB, MVT::v32i8, 1 }, // psubb
587 { ISD::ADD, MVT::v32i8, 1 }, // paddb
588 { ISD::SUB, MVT::v16i16, 1 }, // psubw
589 { ISD::ADD, MVT::v16i16, 1 }, // paddw
590 { ISD::SUB, MVT::v8i32, 1 }, // psubd
591 { ISD::ADD, MVT::v8i32, 1 }, // paddd
592 { ISD::SUB, MVT::v4i64, 1 }, // psubq
593 { ISD::ADD, MVT::v4i64, 1 }, // paddq
594
595 { ISD::MUL, MVT::v32i8, 17 }, // extend/pmullw/trunc sequence.
596 { ISD::MUL, MVT::v16i8, 7 }, // extend/pmullw/trunc sequence.
597 { ISD::MUL, MVT::v16i16, 1 }, // pmullw
598 { ISD::MUL, MVT::v8i32, 2 }, // pmulld (Haswell from agner.org)
599 { ISD::MUL, MVT::v4i64, 8 }, // 3*pmuludq/3*shift/2*add
600
601 { ISD::FADD, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/
602 { ISD::FADD, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/
603 { ISD::FSUB, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/
604 { ISD::FSUB, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/
605 { ISD::FMUL, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/
606 { ISD::FMUL, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/
607
608 { ISD::FDIV, MVT::f32, 7 }, // Haswell from http://www.agner.org/
609 { ISD::FDIV, MVT::v4f32, 7 }, // Haswell from http://www.agner.org/
610 { ISD::FDIV, MVT::v8f32, 14 }, // Haswell from http://www.agner.org/
611 { ISD::FDIV, MVT::f64, 14 }, // Haswell from http://www.agner.org/
612 { ISD::FDIV, MVT::v2f64, 14 }, // Haswell from http://www.agner.org/
613 { ISD::FDIV, MVT::v4f64, 28 }, // Haswell from http://www.agner.org/
614 };
615
616 // Look for AVX2 lowering tricks for custom cases.
617 if (ST->hasAVX2())
618 if (const auto *Entry = CostTableLookup(AVX2CostTable, ISD, LT.second))
619 return LT.first * Entry->Cost;
620
621 static const CostTblEntry AVX1CostTable[] = {
622 // We don't have to scalarize unsupported ops. We can issue two half-sized
623 // operations and we only need to extract the upper YMM half.
624 // Two ops + 1 extract + 1 insert = 4.
625 { ISD::MUL, MVT::v16i16, 4 },
626 { ISD::MUL, MVT::v8i32, 4 },
627 { ISD::SUB, MVT::v32i8, 4 },
628 { ISD::ADD, MVT::v32i8, 4 },
629 { ISD::SUB, MVT::v16i16, 4 },
630 { ISD::ADD, MVT::v16i16, 4 },
631 { ISD::SUB, MVT::v8i32, 4 },
632 { ISD::ADD, MVT::v8i32, 4 },
633 { ISD::SUB, MVT::v4i64, 4 },
634 { ISD::ADD, MVT::v4i64, 4 },
635
636 // A v4i64 multiply is custom lowered as two split v2i64 vectors that then
637 // are lowered as a series of long multiplies(3), shifts(3) and adds(2)
638 // Because we believe v4i64 to be a legal type, we must also include the
639 // extract+insert in the cost table. Therefore, the cost here is 18
640 // instead of 8.
641 { ISD::MUL, MVT::v4i64, 18 },
642
643 { ISD::MUL, MVT::v32i8, 26 }, // extend/pmullw/trunc sequence.
644
645 { ISD::FDIV, MVT::f32, 14 }, // SNB from http://www.agner.org/
646 { ISD::FDIV, MVT::v4f32, 14 }, // SNB from http://www.agner.org/
647 { ISD::FDIV, MVT::v8f32, 28 }, // SNB from http://www.agner.org/
648 { ISD::FDIV, MVT::f64, 22 }, // SNB from http://www.agner.org/
649 { ISD::FDIV, MVT::v2f64, 22 }, // SNB from http://www.agner.org/
650 { ISD::FDIV, MVT::v4f64, 44 }, // SNB from http://www.agner.org/
651
652 // Vectorizing division is a bad idea. See the SSE2 table for more comments.
653 { ISD::SDIV, MVT::v32i8, 32*20 },
654 { ISD::SDIV, MVT::v16i16, 16*20 },
655 { ISD::SDIV, MVT::v8i32, 8*20 },
656 { ISD::SDIV, MVT::v4i64, 4*20 },
657 { ISD::UDIV, MVT::v32i8, 32*20 },
658 { ISD::UDIV, MVT::v16i16, 16*20 },
659 { ISD::UDIV, MVT::v8i32, 8*20 },
660 { ISD::UDIV, MVT::v4i64, 4*20 },
661 };
662
663 if (ST->hasAVX())
664 if (const auto *Entry = CostTableLookup(AVX1CostTable, ISD, LT.second))
665 return LT.first * Entry->Cost;
666
667 static const CostTblEntry SSE42CostTable[] = {
668 { ISD::FADD, MVT::f64, 1 }, // Nehalem from http://www.agner.org/
669 { ISD::FADD, MVT::f32, 1 }, // Nehalem from http://www.agner.org/
670 { ISD::FADD, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/
671 { ISD::FADD, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/
672
673 { ISD::FSUB, MVT::f64, 1 }, // Nehalem from http://www.agner.org/
674 { ISD::FSUB, MVT::f32 , 1 }, // Nehalem from http://www.agner.org/
675 { ISD::FSUB, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/
676 { ISD::FSUB, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/
677
678 { ISD::FMUL, MVT::f64, 1 }, // Nehalem from http://www.agner.org/
679 { ISD::FMUL, MVT::f32, 1 }, // Nehalem from http://www.agner.org/
680 { ISD::FMUL, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/
681 { ISD::FMUL, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/
682
683 { ISD::FDIV, MVT::f32, 14 }, // Nehalem from http://www.agner.org/
684 { ISD::FDIV, MVT::v4f32, 14 }, // Nehalem from http://www.agner.org/
685 { ISD::FDIV, MVT::f64, 22 }, // Nehalem from http://www.agner.org/
686 { ISD::FDIV, MVT::v2f64, 22 }, // Nehalem from http://www.agner.org/
687 };
688
689 if (ST->hasSSE42())
690 if (const auto *Entry = CostTableLookup(SSE42CostTable, ISD, LT.second))
691 return LT.first * Entry->Cost;
692
693 static const CostTblEntry SSE41CostTable[] = {
694 { ISD::SHL, MVT::v16i8, 11 }, // pblendvb sequence.
695 { ISD::SHL, MVT::v32i8, 2*11+2 }, // pblendvb sequence + split.
696 { ISD::SHL, MVT::v8i16, 14 }, // pblendvb sequence.
697 { ISD::SHL, MVT::v16i16, 2*14+2 }, // pblendvb sequence + split.
698 { ISD::SHL, MVT::v4i32, 4 }, // pslld/paddd/cvttps2dq/pmulld
699 { ISD::SHL, MVT::v8i32, 2*4+2 }, // pslld/paddd/cvttps2dq/pmulld + split
700
701 { ISD::SRL, MVT::v16i8, 12 }, // pblendvb sequence.
702 { ISD::SRL, MVT::v32i8, 2*12+2 }, // pblendvb sequence + split.
703 { ISD::SRL, MVT::v8i16, 14 }, // pblendvb sequence.
704 { ISD::SRL, MVT::v16i16, 2*14+2 }, // pblendvb sequence + split.
705 { ISD::SRL, MVT::v4i32, 11 }, // Shift each lane + blend.
706 { ISD::SRL, MVT::v8i32, 2*11+2 }, // Shift each lane + blend + split.
707
708 { ISD::SRA, MVT::v16i8, 24 }, // pblendvb sequence.
709 { ISD::SRA, MVT::v32i8, 2*24+2 }, // pblendvb sequence + split.
710 { ISD::SRA, MVT::v8i16, 14 }, // pblendvb sequence.
711 { ISD::SRA, MVT::v16i16, 2*14+2 }, // pblendvb sequence + split.
712 { ISD::SRA, MVT::v4i32, 12 }, // Shift each lane + blend.
713 { ISD::SRA, MVT::v8i32, 2*12+2 }, // Shift each lane + blend + split.
714
715 { ISD::MUL, MVT::v4i32, 2 } // pmulld (Nehalem from agner.org)
716 };
717
718 if (ST->hasSSE41())
719 if (const auto *Entry = CostTableLookup(SSE41CostTable, ISD, LT.second))
720 return LT.first * Entry->Cost;
721
722 static const CostTblEntry SSE2CostTable[] = {
723 // We don't correctly identify costs of casts because they are marked as
724 // custom.
725 { ISD::SHL, MVT::v16i8, 26 }, // cmpgtb sequence.
726 { ISD::SHL, MVT::v8i16, 32 }, // cmpgtb sequence.
727 { ISD::SHL, MVT::v4i32, 2*5 }, // We optimized this using mul.
728 { ISD::SHL, MVT::v2i64, 4 }, // splat+shuffle sequence.
729 { ISD::SHL, MVT::v4i64, 2*4+2 }, // splat+shuffle sequence + split.
730
731 { ISD::SRL, MVT::v16i8, 26 }, // cmpgtb sequence.
732 { ISD::SRL, MVT::v8i16, 32 }, // cmpgtb sequence.
733 { ISD::SRL, MVT::v4i32, 16 }, // Shift each lane + blend.
734 { ISD::SRL, MVT::v2i64, 4 }, // splat+shuffle sequence.
735 { ISD::SRL, MVT::v4i64, 2*4+2 }, // splat+shuffle sequence + split.
736
737 { ISD::SRA, MVT::v16i8, 54 }, // unpacked cmpgtb sequence.
738 { ISD::SRA, MVT::v8i16, 32 }, // cmpgtb sequence.
739 { ISD::SRA, MVT::v4i32, 16 }, // Shift each lane + blend.
740 { ISD::SRA, MVT::v2i64, 12 }, // srl/xor/sub sequence.
741 { ISD::SRA, MVT::v4i64, 2*12+2 }, // srl/xor/sub sequence+split.
742
743 { ISD::MUL, MVT::v16i8, 12 }, // extend/pmullw/trunc sequence.
744 { ISD::MUL, MVT::v8i16, 1 }, // pmullw
745 { ISD::MUL, MVT::v4i32, 6 }, // 3*pmuludq/4*shuffle
746 { ISD::MUL, MVT::v2i64, 8 }, // 3*pmuludq/3*shift/2*add
747
748 { ISD::FDIV, MVT::f32, 23 }, // Pentium IV from http://www.agner.org/
749 { ISD::FDIV, MVT::v4f32, 39 }, // Pentium IV from http://www.agner.org/
750 { ISD::FDIV, MVT::f64, 38 }, // Pentium IV from http://www.agner.org/
751 { ISD::FDIV, MVT::v2f64, 69 }, // Pentium IV from http://www.agner.org/
752
753 // It is not a good idea to vectorize division. We have to scalarize it and
754 // in the process we will often end up having to spilling regular
755 // registers. The overhead of division is going to dominate most kernels
756 // anyways so try hard to prevent vectorization of division - it is
757 // generally a bad idea. Assume somewhat arbitrarily that we have to be able
758 // to hide "20 cycles" for each lane.
759 { ISD::SDIV, MVT::v16i8, 16*20 },
760 { ISD::SDIV, MVT::v8i16, 8*20 },
761 { ISD::SDIV, MVT::v4i32, 4*20 },
762 { ISD::SDIV, MVT::v2i64, 2*20 },
763 { ISD::UDIV, MVT::v16i8, 16*20 },
764 { ISD::UDIV, MVT::v8i16, 8*20 },
765 { ISD::UDIV, MVT::v4i32, 4*20 },
766 { ISD::UDIV, MVT::v2i64, 2*20 },
767 };
768
769 if (ST->hasSSE2())
770 if (const auto *Entry = CostTableLookup(SSE2CostTable, ISD, LT.second))
771 return LT.first * Entry->Cost;
772
773 static const CostTblEntry SSE1CostTable[] = {
774 { ISD::FDIV, MVT::f32, 17 }, // Pentium III from http://www.agner.org/
775 { ISD::FDIV, MVT::v4f32, 34 }, // Pentium III from http://www.agner.org/
776 };
777
778 if (ST->hasSSE1())
779 if (const auto *Entry = CostTableLookup(SSE1CostTable, ISD, LT.second))
780 return LT.first * Entry->Cost;
781
782 // Fallback to the default implementation.
783 return BaseT::getArithmeticInstrCost(Opcode, Ty, Op1Info, Op2Info);
784}
785
786int X86TTIImpl::getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, int Index,
787 Type *SubTp) {
788 // 64-bit packed float vectors (v2f32) are widened to type v4f32.
789 // 64-bit packed integer vectors (v2i32) are promoted to type v2i64.
790 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Tp);
791
792 // For Broadcasts we are splatting the first element from the first input
793 // register, so only need to reference that input and all the output
794 // registers are the same.
795 if (Kind == TTI::SK_Broadcast)
796 LT.first = 1;
797
798 // We are going to permute multiple sources and the result will be in multiple
799 // destinations. Providing an accurate cost only for splits where the element
800 // type remains the same.
801 if (Kind == TTI::SK_PermuteSingleSrc && LT.first != 1) {
802 MVT LegalVT = LT.second;
803 if (LegalVT.isVector() &&
804 LegalVT.getVectorElementType().getSizeInBits() ==
805 Tp->getVectorElementType()->getPrimitiveSizeInBits() &&
806 LegalVT.getVectorNumElements() < Tp->getVectorNumElements()) {
807
808 unsigned VecTySize = DL.getTypeStoreSize(Tp);
809 unsigned LegalVTSize = LegalVT.getStoreSize();
810 // Number of source vectors after legalization:
811 unsigned NumOfSrcs = (VecTySize + LegalVTSize - 1) / LegalVTSize;
812 // Number of destination vectors after legalization:
813 unsigned NumOfDests = LT.first;
814
815 Type *SingleOpTy = VectorType::get(Tp->getVectorElementType(),
816 LegalVT.getVectorNumElements());
817
818 unsigned NumOfShuffles = (NumOfSrcs - 1) * NumOfDests;
819 return NumOfShuffles *
820 getShuffleCost(TTI::SK_PermuteTwoSrc, SingleOpTy, 0, nullptr);
821 }
822
823 return BaseT::getShuffleCost(Kind, Tp, Index, SubTp);
824 }
825
826 // For 2-input shuffles, we must account for splitting the 2 inputs into many.
827 if (Kind == TTI::SK_PermuteTwoSrc && LT.first != 1) {
828 // We assume that source and destination have the same vector type.
829 int NumOfDests = LT.first;
830 int NumOfShufflesPerDest = LT.first * 2 - 1;
831 LT.first = NumOfDests * NumOfShufflesPerDest;
832 }
833
834 static const CostTblEntry AVX512VBMIShuffleTbl[] = {
835 { TTI::SK_Reverse, MVT::v64i8, 1 }, // vpermb
836 { TTI::SK_Reverse, MVT::v32i8, 1 }, // vpermb
837
838 { TTI::SK_PermuteSingleSrc, MVT::v64i8, 1 }, // vpermb
839 { TTI::SK_PermuteSingleSrc, MVT::v32i8, 1 }, // vpermb
840
841 { TTI::SK_PermuteTwoSrc, MVT::v64i8, 1 }, // vpermt2b
842 { TTI::SK_PermuteTwoSrc, MVT::v32i8, 1 }, // vpermt2b
843 { TTI::SK_PermuteTwoSrc, MVT::v16i8, 1 } // vpermt2b
844 };
845
846 if (ST->hasVBMI())
847 if (const auto *Entry =
848 CostTableLookup(AVX512VBMIShuffleTbl, Kind, LT.second))
849 return LT.first * Entry->Cost;
850
851 static const CostTblEntry AVX512BWShuffleTbl[] = {
852 { TTI::SK_Broadcast, MVT::v32i16, 1 }, // vpbroadcastw
853 { TTI::SK_Broadcast, MVT::v64i8, 1 }, // vpbroadcastb
854
855 { TTI::SK_Reverse, MVT::v32i16, 1 }, // vpermw
856 { TTI::SK_Reverse, MVT::v16i16, 1 }, // vpermw
857 { TTI::SK_Reverse, MVT::v64i8, 2 }, // pshufb + vshufi64x2
858
859 { TTI::SK_PermuteSingleSrc, MVT::v32i16, 1 }, // vpermw
860 { TTI::SK_PermuteSingleSrc, MVT::v16i16, 1 }, // vpermw
861 { TTI::SK_PermuteSingleSrc, MVT::v8i16, 1 }, // vpermw
862 { TTI::SK_PermuteSingleSrc, MVT::v64i8, 8 }, // extend to v32i16
863 { TTI::SK_PermuteSingleSrc, MVT::v32i8, 3 }, // vpermw + zext/trunc
864
865 { TTI::SK_PermuteTwoSrc, MVT::v32i16, 1 }, // vpermt2w
866 { TTI::SK_PermuteTwoSrc, MVT::v16i16, 1 }, // vpermt2w
867 { TTI::SK_PermuteTwoSrc, MVT::v8i16, 1 }, // vpermt2w
868 { TTI::SK_PermuteTwoSrc, MVT::v32i8, 3 }, // zext + vpermt2w + trunc
869 { TTI::SK_PermuteTwoSrc, MVT::v64i8, 19 }, // 6 * v32i8 + 1
870 { TTI::SK_PermuteTwoSrc, MVT::v16i8, 3 } // zext + vpermt2w + trunc
871 };
872
873 if (ST->hasBWI())
874 if (const auto *Entry =
875 CostTableLookup(AVX512BWShuffleTbl, Kind, LT.second))
876 return LT.first * Entry->Cost;
877
878 static const CostTblEntry AVX512ShuffleTbl[] = {
879 { TTI::SK_Broadcast, MVT::v8f64, 1 }, // vbroadcastpd
880 { TTI::SK_Broadcast, MVT::v16f32, 1 }, // vbroadcastps
881 { TTI::SK_Broadcast, MVT::v8i64, 1 }, // vpbroadcastq
882 { TTI::SK_Broadcast, MVT::v16i32, 1 }, // vpbroadcastd
883
884 { TTI::SK_Reverse, MVT::v8f64, 1 }, // vpermpd
885 { TTI::SK_Reverse, MVT::v16f32, 1 }, // vpermps
886 { TTI::SK_Reverse, MVT::v8i64, 1 }, // vpermq
887 { TTI::SK_Reverse, MVT::v16i32, 1 }, // vpermd
888
889 { TTI::SK_PermuteSingleSrc, MVT::v8f64, 1 }, // vpermpd
890 { TTI::SK_PermuteSingleSrc, MVT::v4f64, 1 }, // vpermpd
891 { TTI::SK_PermuteSingleSrc, MVT::v2f64, 1 }, // vpermpd
892 { TTI::SK_PermuteSingleSrc, MVT::v16f32, 1 }, // vpermps
893 { TTI::SK_PermuteSingleSrc, MVT::v8f32, 1 }, // vpermps
894 { TTI::SK_PermuteSingleSrc, MVT::v4f32, 1 }, // vpermps
895 { TTI::SK_PermuteSingleSrc, MVT::v8i64, 1 }, // vpermq
896 { TTI::SK_PermuteSingleSrc, MVT::v4i64, 1 }, // vpermq
897 { TTI::SK_PermuteSingleSrc, MVT::v2i64, 1 }, // vpermq
898 { TTI::SK_PermuteSingleSrc, MVT::v16i32, 1 }, // vpermd
899 { TTI::SK_PermuteSingleSrc, MVT::v8i32, 1 }, // vpermd
900 { TTI::SK_PermuteSingleSrc, MVT::v4i32, 1 }, // vpermd
901 { TTI::SK_PermuteSingleSrc, MVT::v16i8, 1 }, // pshufb
902
903 { TTI::SK_PermuteTwoSrc, MVT::v8f64, 1 }, // vpermt2pd
904 { TTI::SK_PermuteTwoSrc, MVT::v16f32, 1 }, // vpermt2ps
905 { TTI::SK_PermuteTwoSrc, MVT::v8i64, 1 }, // vpermt2q
906 { TTI::SK_PermuteTwoSrc, MVT::v16i32, 1 }, // vpermt2d
907 { TTI::SK_PermuteTwoSrc, MVT::v4f64, 1 }, // vpermt2pd
908 { TTI::SK_PermuteTwoSrc, MVT::v8f32, 1 }, // vpermt2ps
909 { TTI::SK_PermuteTwoSrc, MVT::v4i64, 1 }, // vpermt2q
910 { TTI::SK_PermuteTwoSrc, MVT::v8i32, 1 }, // vpermt2d
911 { TTI::SK_PermuteTwoSrc, MVT::v2f64, 1 }, // vpermt2pd
912 { TTI::SK_PermuteTwoSrc, MVT::v4f32, 1 }, // vpermt2ps
913 { TTI::SK_PermuteTwoSrc, MVT::v2i64, 1 }, // vpermt2q
914 { TTI::SK_PermuteTwoSrc, MVT::v4i32, 1 } // vpermt2d
915 };
916
917 if (ST->hasAVX512())
918 if (const auto *Entry = CostTableLookup(AVX512ShuffleTbl, Kind, LT.second))
919 return LT.first * Entry->Cost;
920
921 static const CostTblEntry AVX2ShuffleTbl[] = {
922 { TTI::SK_Broadcast, MVT::v4f64, 1 }, // vbroadcastpd
923 { TTI::SK_Broadcast, MVT::v8f32, 1 }, // vbroadcastps
924 { TTI::SK_Broadcast, MVT::v4i64, 1 }, // vpbroadcastq
925 { TTI::SK_Broadcast, MVT::v8i32, 1 }, // vpbroadcastd
926 { TTI::SK_Broadcast, MVT::v16i16, 1 }, // vpbroadcastw
927 { TTI::SK_Broadcast, MVT::v32i8, 1 }, // vpbroadcastb
928
929 { TTI::SK_Reverse, MVT::v4f64, 1 }, // vpermpd
930 { TTI::SK_Reverse, MVT::v8f32, 1 }, // vpermps
931 { TTI::SK_Reverse, MVT::v4i64, 1 }, // vpermq
932 { TTI::SK_Reverse, MVT::v8i32, 1 }, // vpermd
933 { TTI::SK_Reverse, MVT::v16i16, 2 }, // vperm2i128 + pshufb
934 { TTI::SK_Reverse, MVT::v32i8, 2 }, // vperm2i128 + pshufb
935
936 { TTI::SK_Alternate, MVT::v16i16, 1 }, // vpblendw
937 { TTI::SK_Alternate, MVT::v32i8, 1 }, // vpblendvb
938
939 { TTI::SK_PermuteSingleSrc, MVT::v4f64, 1 }, // vpermpd
940 { TTI::SK_PermuteSingleSrc, MVT::v8f32, 1 }, // vpermps
941 { TTI::SK_PermuteSingleSrc, MVT::v4i64, 1 }, // vpermq
942 { TTI::SK_PermuteSingleSrc, MVT::v8i32, 1 }, // vpermd
943 { TTI::SK_PermuteSingleSrc, MVT::v16i16, 4 }, // vperm2i128 + 2*vpshufb
944 // + vpblendvb
945 { TTI::SK_PermuteSingleSrc, MVT::v32i8, 4 }, // vperm2i128 + 2*vpshufb
946 // + vpblendvb
947
948 { TTI::SK_PermuteTwoSrc, MVT::v4f64, 3 }, // 2*vpermpd + vblendpd
949 { TTI::SK_PermuteTwoSrc, MVT::v8f32, 3 }, // 2*vpermps + vblendps
950 { TTI::SK_PermuteTwoSrc, MVT::v4i64, 3 }, // 2*vpermq + vpblendd
951 { TTI::SK_PermuteTwoSrc, MVT::v8i32, 3 }, // 2*vpermd + vpblendd
952 { TTI::SK_PermuteTwoSrc, MVT::v16i16, 7 }, // 2*vperm2i128 + 4*vpshufb
953 // + vpblendvb
954 { TTI::SK_PermuteTwoSrc, MVT::v32i8, 7 }, // 2*vperm2i128 + 4*vpshufb
955 // + vpblendvb
956 };
957
958 if (ST->hasAVX2())
959 if (const auto *Entry = CostTableLookup(AVX2ShuffleTbl, Kind, LT.second))
960 return LT.first * Entry->Cost;
961
962 static const CostTblEntry XOPShuffleTbl[] = {
963 { TTI::SK_PermuteSingleSrc, MVT::v4f64, 2 }, // vperm2f128 + vpermil2pd
964 { TTI::SK_PermuteSingleSrc, MVT::v8f32, 2 }, // vperm2f128 + vpermil2ps
965 { TTI::SK_PermuteSingleSrc, MVT::v4i64, 2 }, // vperm2f128 + vpermil2pd
966 { TTI::SK_PermuteSingleSrc, MVT::v8i32, 2 }, // vperm2f128 + vpermil2ps
967 { TTI::SK_PermuteSingleSrc, MVT::v16i16, 4 }, // vextractf128 + 2*vpperm
968 // + vinsertf128
969 { TTI::SK_PermuteSingleSrc, MVT::v32i8, 4 }, // vextractf128 + 2*vpperm
970 // + vinsertf128
971
972 { TTI::SK_PermuteTwoSrc, MVT::v16i16, 9 }, // 2*vextractf128 + 6*vpperm
973 // + vinsertf128
974 { TTI::SK_PermuteTwoSrc, MVT::v8i16, 1 }, // vpperm
975 { TTI::SK_PermuteTwoSrc, MVT::v32i8, 9 }, // 2*vextractf128 + 6*vpperm
976 // + vinsertf128
977 { TTI::SK_PermuteTwoSrc, MVT::v16i8, 1 }, // vpperm
978 };
979
980 if (ST->hasXOP())
981 if (const auto *Entry = CostTableLookup(XOPShuffleTbl, Kind, LT.second))
982 return LT.first * Entry->Cost;
983
984 static const CostTblEntry AVX1ShuffleTbl[] = {
985 { TTI::SK_Broadcast, MVT::v4f64, 2 }, // vperm2f128 + vpermilpd
986 { TTI::SK_Broadcast, MVT::v8f32, 2 }, // vperm2f128 + vpermilps
987 { TTI::SK_Broadcast, MVT::v4i64, 2 }, // vperm2f128 + vpermilpd
988 { TTI::SK_Broadcast, MVT::v8i32, 2 }, // vperm2f128 + vpermilps
989 { TTI::SK_Broadcast, MVT::v16i16, 3 }, // vpshuflw + vpshufd + vinsertf128
990 { TTI::SK_Broadcast, MVT::v32i8, 2 }, // vpshufb + vinsertf128
991
992 { TTI::SK_Reverse, MVT::v4f64, 2 }, // vperm2f128 + vpermilpd
993 { TTI::SK_Reverse, MVT::v8f32, 2 }, // vperm2f128 + vpermilps
994 { TTI::SK_Reverse, MVT::v4i64, 2 }, // vperm2f128 + vpermilpd
995 { TTI::SK_Reverse, MVT::v8i32, 2 }, // vperm2f128 + vpermilps
996 { TTI::SK_Reverse, MVT::v16i16, 4 }, // vextractf128 + 2*pshufb
997 // + vinsertf128
998 { TTI::SK_Reverse, MVT::v32i8, 4 }, // vextractf128 + 2*pshufb
999 // + vinsertf128
1000
1001 { TTI::SK_Alternate, MVT::v4i64, 1 }, // vblendpd
1002 { TTI::SK_Alternate, MVT::v4f64, 1 }, // vblendpd
1003 { TTI::SK_Alternate, MVT::v8i32, 1 }, // vblendps
1004 { TTI::SK_Alternate, MVT::v8f32, 1 }, // vblendps
1005 { TTI::SK_Alternate, MVT::v16i16, 3 }, // vpand + vpandn + vpor
1006 { TTI::SK_Alternate, MVT::v32i8, 3 }, // vpand + vpandn + vpor
1007
1008 { TTI::SK_PermuteSingleSrc, MVT::v4f64, 3 }, // 2*vperm2f128 + vshufpd
1009 { TTI::SK_PermuteSingleSrc, MVT::v4i64, 3 }, // 2*vperm2f128 + vshufpd
1010 { TTI::SK_PermuteSingleSrc, MVT::v8f32, 4 }, // 2*vperm2f128 + 2*vshufps
1011 { TTI::SK_PermuteSingleSrc, MVT::v8i32, 4 }, // 2*vperm2f128 + 2*vshufps
1012 { TTI::SK_PermuteSingleSrc, MVT::v16i16, 8 }, // vextractf128 + 4*pshufb
1013 // + 2*por + vinsertf128
1014 { TTI::SK_PermuteSingleSrc, MVT::v32i8, 8 }, // vextractf128 + 4*pshufb
1015 // + 2*por + vinsertf128
1016
1017 { TTI::SK_PermuteTwoSrc, MVT::v4f64, 4 }, // 2*vperm2f128 + 2*vshufpd
1018 { TTI::SK_PermuteTwoSrc, MVT::v8f32, 4 }, // 2*vperm2f128 + 2*vshufps
1019 { TTI::SK_PermuteTwoSrc, MVT::v4i64, 4 }, // 2*vperm2f128 + 2*vshufpd
1020 { TTI::SK_PermuteTwoSrc, MVT::v8i32, 4 }, // 2*vperm2f128 + 2*vshufps
1021 { TTI::SK_PermuteTwoSrc, MVT::v16i16, 15 }, // 2*vextractf128 + 8*pshufb
1022 // + 4*por + vinsertf128
1023 { TTI::SK_PermuteTwoSrc, MVT::v32i8, 15 }, // 2*vextractf128 + 8*pshufb
1024 // + 4*por + vinsertf128
1025 };
1026
1027 if (ST->hasAVX())
1028 if (const auto *Entry = CostTableLookup(AVX1ShuffleTbl, Kind, LT.second))
1029 return LT.first * Entry->Cost;
1030
1031 static const CostTblEntry SSE41ShuffleTbl[] = {
1032 { TTI::SK_Alternate, MVT::v2i64, 1 }, // pblendw
1033 { TTI::SK_Alternate, MVT::v2f64, 1 }, // movsd
1034 { TTI::SK_Alternate, MVT::v4i32, 1 }, // pblendw
1035 { TTI::SK_Alternate, MVT::v4f32, 1 }, // blendps
1036 { TTI::SK_Alternate, MVT::v8i16, 1 }, // pblendw
1037 { TTI::SK_Alternate, MVT::v16i8, 1 } // pblendvb
1038 };
1039
1040 if (ST->hasSSE41())
1041 if (const auto *Entry = CostTableLookup(SSE41ShuffleTbl, Kind, LT.second))
1042 return LT.first * Entry->Cost;
1043
1044 static const CostTblEntry SSSE3ShuffleTbl[] = {
1045 { TTI::SK_Broadcast, MVT::v8i16, 1 }, // pshufb
1046 { TTI::SK_Broadcast, MVT::v16i8, 1 }, // pshufb
1047
1048 { TTI::SK_Reverse, MVT::v8i16, 1 }, // pshufb
1049 { TTI::SK_Reverse, MVT::v16i8, 1 }, // pshufb
1050
1051 { TTI::SK_Alternate, MVT::v8i16, 3 }, // 2*pshufb + por
1052 { TTI::SK_Alternate, MVT::v16i8, 3 }, // 2*pshufb + por
1053
1054 { TTI::SK_PermuteSingleSrc, MVT::v8i16, 1 }, // pshufb
1055 { TTI::SK_PermuteSingleSrc, MVT::v16i8, 1 }, // pshufb
1056
1057 { TTI::SK_PermuteTwoSrc, MVT::v8i16, 3 }, // 2*pshufb + por
1058 { TTI::SK_PermuteTwoSrc, MVT::v16i8, 3 }, // 2*pshufb + por
1059 };
1060
1061 if (ST->hasSSSE3())
1062 if (const auto *Entry = CostTableLookup(SSSE3ShuffleTbl, Kind, LT.second))
1063 return LT.first * Entry->Cost;
1064
1065 static const CostTblEntry SSE2ShuffleTbl[] = {
1066 { TTI::SK_Broadcast, MVT::v2f64, 1 }, // shufpd
1067 { TTI::SK_Broadcast, MVT::v2i64, 1 }, // pshufd
1068 { TTI::SK_Broadcast, MVT::v4i32, 1 }, // pshufd
1069 { TTI::SK_Broadcast, MVT::v8i16, 2 }, // pshuflw + pshufd
1070 { TTI::SK_Broadcast, MVT::v16i8, 3 }, // unpck + pshuflw + pshufd
1071
1072 { TTI::SK_Reverse, MVT::v2f64, 1 }, // shufpd
1073 { TTI::SK_Reverse, MVT::v2i64, 1 }, // pshufd
1074 { TTI::SK_Reverse, MVT::v4i32, 1 }, // pshufd
1075 { TTI::SK_Reverse, MVT::v8i16, 3 }, // pshuflw + pshufhw + pshufd
1076 { TTI::SK_Reverse, MVT::v16i8, 9 }, // 2*pshuflw + 2*pshufhw
1077 // + 2*pshufd + 2*unpck + packus
1078
1079 { TTI::SK_Alternate, MVT::v2i64, 1 }, // movsd
1080 { TTI::SK_Alternate, MVT::v2f64, 1 }, // movsd
1081 { TTI::SK_Alternate, MVT::v4i32, 2 }, // 2*shufps
1082 { TTI::SK_Alternate, MVT::v8i16, 3 }, // pand + pandn + por
1083 { TTI::SK_Alternate, MVT::v16i8, 3 }, // pand + pandn + por
1084
1085 { TTI::SK_PermuteSingleSrc, MVT::v2f64, 1 }, // shufpd
1086 { TTI::SK_PermuteSingleSrc, MVT::v2i64, 1 }, // pshufd
1087 { TTI::SK_PermuteSingleSrc, MVT::v4i32, 1 }, // pshufd
1088 { TTI::SK_PermuteSingleSrc, MVT::v8i16, 5 }, // 2*pshuflw + 2*pshufhw
1089 // + pshufd/unpck
1090 { TTI::SK_PermuteSingleSrc, MVT::v16i8, 10 }, // 2*pshuflw + 2*pshufhw
1091 // + 2*pshufd + 2*unpck + 2*packus
1092
1093 { TTI::SK_PermuteTwoSrc, MVT::v2f64, 1 }, // shufpd
1094 { TTI::SK_PermuteTwoSrc, MVT::v2i64, 1 }, // shufpd
1095 { TTI::SK_PermuteTwoSrc, MVT::v4i32, 2 }, // 2*{unpck,movsd,pshufd}
1096 { TTI::SK_PermuteTwoSrc, MVT::v8i16, 8 }, // blend+permute
1097 { TTI::SK_PermuteTwoSrc, MVT::v16i8, 13 }, // blend+permute
1098 };
1099
1100 if (ST->hasSSE2())
1101 if (const auto *Entry = CostTableLookup(SSE2ShuffleTbl, Kind, LT.second))
1102 return LT.first * Entry->Cost;
1103
1104 static const CostTblEntry SSE1ShuffleTbl[] = {
1105 { TTI::SK_Broadcast, MVT::v4f32, 1 }, // shufps
1106 { TTI::SK_Reverse, MVT::v4f32, 1 }, // shufps
1107 { TTI::SK_Alternate, MVT::v4f32, 2 }, // 2*shufps
1108 { TTI::SK_PermuteSingleSrc, MVT::v4f32, 1 }, // shufps
1109 { TTI::SK_PermuteTwoSrc, MVT::v4f32, 2 }, // 2*shufps
1110 };
1111
1112 if (ST->hasSSE1())
1113 if (const auto *Entry = CostTableLookup(SSE1ShuffleTbl, Kind, LT.second))
1114 return LT.first * Entry->Cost;
1115
1116 return BaseT::getShuffleCost(Kind, Tp, Index, SubTp);
1117}
1118
1119int X86TTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src,
1120 const Instruction *I) {
1121 int ISD = TLI->InstructionOpcodeToISD(Opcode);
1122 assert(ISD && "Invalid opcode")(static_cast <bool> (ISD && "Invalid opcode") ?
void (0) : __assert_fail ("ISD && \"Invalid opcode\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86TargetTransformInfo.cpp"
, 1122, __extension__ __PRETTY_FUNCTION__))
;
1123
1124 // FIXME: Need a better design of the cost table to handle non-simple types of
1125 // potential massive combinations (elem_num x src_type x dst_type).
1126
1127 static const TypeConversionCostTblEntry AVX512DQConversionTbl[] = {
1128 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i64, 1 },
1129 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 },
1130 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i64, 1 },
1131 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 1 },
1132 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 },
1133 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 },
1134
1135 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 1 },
1136 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 },
1137 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i64, 1 },
1138 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 1 },
1139 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 },
1140 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 },
1141
1142 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f32, 1 },
1143 { ISD::FP_TO_SINT, MVT::v4i64, MVT::v4f32, 1 },
1144 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f32, 1 },
1145 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f64, 1 },
1146 { ISD::FP_TO_SINT, MVT::v4i64, MVT::v4f64, 1 },
1147 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f64, 1 },
1148
1149 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f32, 1 },
1150 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f32, 1 },
1151 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f32, 1 },
1152 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f64, 1 },
1153 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f64, 1 },
1154 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f64, 1 },
1155 };
1156
1157 // TODO: For AVX512DQ + AVX512VL, we also have cheap casts for 128-bit and
1158 // 256-bit wide vectors.
1159
1160 static const TypeConversionCostTblEntry AVX512FConversionTbl[] = {
1161 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 1 },
1162 { ISD::FP_EXTEND, MVT::v8f64, MVT::v16f32, 3 },
1163 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 1 },
1164
1165 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 1 },
1166 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 1 },
1167 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i64, 1 },
1168 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 1 },
1169
1170 // v16i1 -> v16i32 - load + broadcast
1171 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i1, 2 },
1172 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i1, 2 },
1173 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 1 },
1174 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 1 },
1175 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 1 },
1176 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 1 },
1177 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i16, 1 },
1178 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 1 },
1179 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i32, 1 },
1180 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i32, 1 },
1181
1182 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 },
1183 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 },
1184 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i8, 2 },
1185 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i8, 2 },
1186 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 },
1187 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, 2 },
1188 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 },
1189 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 },
1190 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, 26 },
1191 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 26 },
1192
1193 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 },
1194 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 },
1195 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i8, 2 },
1196 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i8, 2 },
1197 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 2 },
1198 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i8, 2 },
1199 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i8, 2 },
1200 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i16, 5 },
1201 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i16, 2 },
1202 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 2 },
1203 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 },
1204 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i16, 2 },
1205 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 2 },
1206 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 1 },
1207 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
1208 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 },
1209 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 },
1210 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 },
1211 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 },
1212 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 5 },
1213 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 5 },
1214 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 12 },
1215 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 26 },
1216
1217 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f32, 1 },
1218 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 },
1219 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 1 },
1220 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f64, 2 },
1221 { ISD::FP_TO_UINT, MVT::v8i8, MVT::v8f64, 2 },
1222 { ISD::FP_TO_UINT, MVT::v16i32, MVT::v16f32, 1 },
1223 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v16f32, 2 },
1224 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v16f32, 2 },
1225 };
1226
1227 static const TypeConversionCostTblEntry AVX2ConversionTbl[] = {
1228 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 3 },
1229 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 3 },
1230 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 3 },
1231 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 3 },
1232 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 3 },
1233 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 3 },
1234 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 3 },
1235 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 3 },
1236 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 1 },
1237 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 1 },
1238 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
1239 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
1240 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 1 },
1241 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 1 },
1242 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 1 },
1243 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 1 },
1244
1245 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 2 },
1246 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 2 },
1247 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 2 },
1248 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 2 },
1249 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 2 },
1250 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 4 },
1251
1252 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 3 },
1253 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 3 },
1254
1255 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 8 },
1256 };
1257
1258 static const TypeConversionCostTblEntry AVXConversionTbl[] = {
1259 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 6 },
1260 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 4 },
1261 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 7 },
1262 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 4 },
1263 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 6 },
1264 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 4 },
1265 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 7 },
1266 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 4 },
1267 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 4 },
1268 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 4 },
1269 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 6 },
1270 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
1271 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 4 },
1272 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 4 },
1273 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 4 },
1274 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 4 },
1275
1276 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 4 },
1277 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 4 },
1278 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 5 },
1279 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 4 },
1280 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 4 },
1281 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 4 },
1282 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 9 },
1283
1284 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 },
1285 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i1, 3 },
1286 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i1, 8 },
1287 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 },
1288 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i8, 3 },
1289 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i8, 8 },
1290 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 3 },
1291 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i16, 3 },
1292 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 5 },
1293 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
1294 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 },
1295 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 },
1296
1297 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i1, 7 },
1298 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i1, 7 },
1299 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i1, 6 },
1300 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 2 },
1301 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i8, 2 },
1302 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 5 },
1303 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
1304 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i16, 2 },
1305 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 5 },
1306 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 6 },
1307 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 6 },
1308 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 6 },
1309 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 9 },
1310 // The generic code to compute the scalar overhead is currently broken.
1311 // Workaround this limitation by estimating the scalarization overhead
1312 // here. We have roughly 10 instructions per scalar element.
1313 // Multiply that by the vector width.
1314 // FIXME: remove that when PR19268 is fixed.
1315 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 10 },
1316 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 20 },
1317 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 13 },
1318 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 13 },
1319
1320 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 1 },
1321 { ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f32, 7 },
1322 // This node is expanded into scalarized operations but BasicTTI is overly
1323 // optimistic estimating its cost. It computes 3 per element (one
1324 // vector-extract, one scalar conversion and one vector-insert). The
1325 // problem is that the inserts form a read-modify-write chain so latency
1326 // should be factored in too. Inflating the cost per element by 1.
1327 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 8*4 },
1328 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 4*4 },
1329
1330 { ISD::FP_EXTEND, MVT::v4f64, MVT::v4f32, 1 },
1331 { ISD::FP_ROUND, MVT::v4f32, MVT::v4f64, 1 },
1332 };
1333
1334 static const TypeConversionCostTblEntry SSE41ConversionTbl[] = {
1335 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 2 },
1336 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 2 },
1337 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 2 },
1338 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 2 },
1339 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 2 },
1340 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 2 },
1341
1342 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i8, 1 },
1343 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i8, 2 },
1344 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i8, 1 },
1345 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i8, 1 },
1346 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i8, 1 },
1347 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i8, 1 },
1348 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 2 },
1349 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 2 },
1350 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 2 },
1351 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 2 },
1352 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 4 },
1353 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 4 },
1354 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 1 },
1355 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 1 },
1356 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 2 },
1357 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 2 },
1358 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 4 },
1359 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 4 },
1360
1361 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i16, 2 },
1362 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i16, 1 },
1363 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i32, 1 },
1364 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 1 },
1365 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 3 },
1366 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 3 },
1367 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 6 },
1368
1369 };
1370
1371 static const TypeConversionCostTblEntry SSE2ConversionTbl[] = {
1372 // These are somewhat magic numbers justified by looking at the output of
1373 // Intel's IACA, running some kernels and making sure when we take
1374 // legalization into account the throughput will be overestimated.
1375 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 },
1376 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 },
1377 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 },
1378 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 },
1379 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 5 },
1380 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v4i32, 4*10 },
1381 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 },
1382 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 2*10 },
1383
1384 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 },
1385 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 },
1386 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 },
1387 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 },
1388 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v4i32, 4*10 },
1389 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 8 },
1390 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 2*10 },
1391 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 },
1392
1393 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 3 },
1394
1395 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i8, 1 },
1396 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i8, 6 },
1397 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i8, 2 },
1398 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i8, 3 },
1399 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 4 },
1400 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 8 },
1401 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i8, 1 },
1402 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i8, 2 },
1403 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 6 },
1404 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 6 },
1405 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 3 },
1406 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 4 },
1407 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 9 },
1408 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 12 },
1409 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 1 },
1410 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 2 },
1411 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
1412 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 10 },
1413 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 3 },
1414 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 4 },
1415 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 6 },
1416 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 8 },
1417 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 3 },
1418 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 5 },
1419
1420 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i16, 4 },
1421 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i16, 2 },
1422 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 3 },
1423 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i32, 3 },
1424 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 3 },
1425 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 4 },
1426 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 7 },
1427 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 5 },
1428 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 10 },
1429 };
1430
1431 std::pair<int, MVT> LTSrc = TLI->getTypeLegalizationCost(DL, Src);
1432 std::pair<int, MVT> LTDest = TLI->getTypeLegalizationCost(DL, Dst);
1433
1434 if (ST->hasSSE2() && !ST->hasAVX()) {
1435 if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD,
1436 LTDest.second, LTSrc.second))
1437 return LTSrc.first * Entry->Cost;
1438 }
1439
1440 EVT SrcTy = TLI->getValueType(DL, Src);
1441 EVT DstTy = TLI->getValueType(DL, Dst);
1442
1443 // The function getSimpleVT only handles simple value types.
1444 if (!SrcTy.isSimple() || !DstTy.isSimple())
1445 return BaseT::getCastInstrCost(Opcode, Dst, Src);
1446
1447 if (ST->hasDQI())
1448 if (const auto *Entry = ConvertCostTableLookup(AVX512DQConversionTbl, ISD,
1449 DstTy.getSimpleVT(),
1450 SrcTy.getSimpleVT()))
1451 return Entry->Cost;
1452
1453 if (ST->hasAVX512())
1454 if (const auto *Entry = ConvertCostTableLookup(AVX512FConversionTbl, ISD,
1455 DstTy.getSimpleVT(),
1456 SrcTy.getSimpleVT()))
1457 return Entry->Cost;
1458
1459 if (ST->hasAVX2()) {
1460 if (const auto *Entry = ConvertCostTableLookup(AVX2ConversionTbl, ISD,
1461 DstTy.getSimpleVT(),
1462 SrcTy.getSimpleVT()))
1463 return Entry->Cost;
1464 }
1465
1466 if (ST->hasAVX()) {
1467 if (const auto *Entry = ConvertCostTableLookup(AVXConversionTbl, ISD,
1468 DstTy.getSimpleVT(),
1469 SrcTy.getSimpleVT()))
1470 return Entry->Cost;
1471 }
1472
1473 if (ST->hasSSE41()) {
1474 if (const auto *Entry = ConvertCostTableLookup(SSE41ConversionTbl, ISD,
1475 DstTy.getSimpleVT(),
1476 SrcTy.getSimpleVT()))
1477 return Entry->Cost;
1478 }
1479
1480 if (ST->hasSSE2()) {
1481 if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD,
1482 DstTy.getSimpleVT(),
1483 SrcTy.getSimpleVT()))
1484 return Entry->Cost;
1485 }
1486
1487 return BaseT::getCastInstrCost(Opcode, Dst, Src, I);
1488}
1489
1490int X86TTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy,
1491 const Instruction *I) {
1492 // Legalize the type.
1493 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy);
1494
1495 MVT MTy = LT.second;
1496
1497 int ISD = TLI->InstructionOpcodeToISD(Opcode);
1498 assert(ISD && "Invalid opcode")(static_cast <bool> (ISD && "Invalid opcode") ?
void (0) : __assert_fail ("ISD && \"Invalid opcode\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86TargetTransformInfo.cpp"
, 1498, __extension__ __PRETTY_FUNCTION__))
;
1499
1500 static const CostTblEntry SSE2CostTbl[] = {
1501 { ISD::SETCC, MVT::v2i64, 8 },
1502 { ISD::SETCC, MVT::v4i32, 1 },
1503 { ISD::SETCC, MVT::v8i16, 1 },
1504 { ISD::SETCC, MVT::v16i8, 1 },
1505 };
1506
1507 static const CostTblEntry SSE42CostTbl[] = {
1508 { ISD::SETCC, MVT::v2f64, 1 },
1509 { ISD::SETCC, MVT::v4f32, 1 },
1510 { ISD::SETCC, MVT::v2i64, 1 },
1511 };
1512
1513 static const CostTblEntry AVX1CostTbl[] = {
1514 { ISD::SETCC, MVT::v4f64, 1 },
1515 { ISD::SETCC, MVT::v8f32, 1 },
1516 // AVX1 does not support 8-wide integer compare.
1517 { ISD::SETCC, MVT::v4i64, 4 },
1518 { ISD::SETCC, MVT::v8i32, 4 },
1519 { ISD::SETCC, MVT::v16i16, 4 },
1520 { ISD::SETCC, MVT::v32i8, 4 },
1521 };
1522
1523 static const CostTblEntry AVX2CostTbl[] = {
1524 { ISD::SETCC, MVT::v4i64, 1 },
1525 { ISD::SETCC, MVT::v8i32, 1 },
1526 { ISD::SETCC, MVT::v16i16, 1 },
1527 { ISD::SETCC, MVT::v32i8, 1 },
1528 };
1529
1530 static const CostTblEntry AVX512CostTbl[] = {
1531 { ISD::SETCC, MVT::v8i64, 1 },
1532 { ISD::SETCC, MVT::v16i32, 1 },
1533 { ISD::SETCC, MVT::v8f64, 1 },
1534 { ISD::SETCC, MVT::v16f32, 1 },
1535 };
1536
1537 static const CostTblEntry AVX512BWCostTbl[] = {
1538 { ISD::SETCC, MVT::v32i16, 1 },
1539 { ISD::SETCC, MVT::v64i8, 1 },
1540 };
1541
1542 if (ST->hasBWI())
1543 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy))
1544 return LT.first * Entry->Cost;
1545
1546 if (ST->hasAVX512())
1547 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy))
1548 return LT.first * Entry->Cost;
1549
1550 if (ST->hasAVX2())
1551 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy))
1552 return LT.first * Entry->Cost;
1553
1554 if (ST->hasAVX())
1555 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy))
1556 return LT.first * Entry->Cost;
1557
1558 if (ST->hasSSE42())
1559 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy))
1560 return LT.first * Entry->Cost;
1561
1562 if (ST->hasSSE2())
1563 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy))
1564 return LT.first * Entry->Cost;
1565
1566 return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy, I);
1567}
1568
1569unsigned X86TTIImpl::getAtomicMemIntrinsicMaxElementSize() const { return 16; }
1570
1571int X86TTIImpl::getIntrinsicInstrCost(Intrinsic::ID IID, Type *RetTy,
1572 ArrayRef<Type *> Tys, FastMathFlags FMF,
1573 unsigned ScalarizationCostPassed) {
1574 // Costs should match the codegen from:
1575 // BITREVERSE: llvm\test\CodeGen\X86\vector-bitreverse.ll
1576 // BSWAP: llvm\test\CodeGen\X86\bswap-vector.ll
1577 // CTLZ: llvm\test\CodeGen\X86\vector-lzcnt-*.ll
1578 // CTPOP: llvm\test\CodeGen\X86\vector-popcnt-*.ll
1579 // CTTZ: llvm\test\CodeGen\X86\vector-tzcnt-*.ll
1580 static const CostTblEntry AVX512CDCostTbl[] = {
1581 { ISD::CTLZ, MVT::v8i64, 1 },
1582 { ISD::CTLZ, MVT::v16i32, 1 },
1583 { ISD::CTLZ, MVT::v32i16, 8 },
1584 { ISD::CTLZ, MVT::v64i8, 20 },
1585 { ISD::CTLZ, MVT::v4i64, 1 },
1586 { ISD::CTLZ, MVT::v8i32, 1 },
1587 { ISD::CTLZ, MVT::v16i16, 4 },
1588 { ISD::CTLZ, MVT::v32i8, 10 },
1589 { ISD::CTLZ, MVT::v2i64, 1 },
1590 { ISD::CTLZ, MVT::v4i32, 1 },
1591 { ISD::CTLZ, MVT::v8i16, 4 },
1592 { ISD::CTLZ, MVT::v16i8, 4 },
1593 };
1594 static const CostTblEntry AVX512BWCostTbl[] = {
1595 { ISD::BITREVERSE, MVT::v8i64, 5 },
1596 { ISD::BITREVERSE, MVT::v16i32, 5 },
1597 { ISD::BITREVERSE, MVT::v32i16, 5 },
1598 { ISD::BITREVERSE, MVT::v64i8, 5 },
1599 { ISD::CTLZ, MVT::v8i64, 23 },
1600 { ISD::CTLZ, MVT::v16i32, 22 },
1601 { ISD::CTLZ, MVT::v32i16, 18 },
1602 { ISD::CTLZ, MVT::v64i8, 17 },
1603 { ISD::CTPOP, MVT::v8i64, 7 },
1604 { ISD::CTPOP, MVT::v16i32, 11 },
1605 { ISD::CTPOP, MVT::v32i16, 9 },
1606 { ISD::CTPOP, MVT::v64i8, 6 },
1607 { ISD::CTTZ, MVT::v8i64, 10 },
1608 { ISD::CTTZ, MVT::v16i32, 14 },
1609 { ISD::CTTZ, MVT::v32i16, 12 },
1610 { ISD::CTTZ, MVT::v64i8, 9 },
1611 };
1612 static const CostTblEntry AVX512CostTbl[] = {
1613 { ISD::BITREVERSE, MVT::v8i64, 36 },
1614 { ISD::BITREVERSE, MVT::v16i32, 24 },
1615 { ISD::CTLZ, MVT::v8i64, 29 },
1616 { ISD::CTLZ, MVT::v16i32, 35 },
1617 { ISD::CTPOP, MVT::v8i64, 16 },
1618 { ISD::CTPOP, MVT::v16i32, 24 },
1619 { ISD::CTTZ, MVT::v8i64, 20 },
1620 { ISD::CTTZ, MVT::v16i32, 28 },
1621 };
1622 static const CostTblEntry XOPCostTbl[] = {
1623 { ISD::BITREVERSE, MVT::v4i64, 4 },
1624 { ISD::BITREVERSE, MVT::v8i32, 4 },
1625 { ISD::BITREVERSE, MVT::v16i16, 4 },
1626 { ISD::BITREVERSE, MVT::v32i8, 4 },
1627 { ISD::BITREVERSE, MVT::v2i64, 1 },
1628 { ISD::BITREVERSE, MVT::v4i32, 1 },
1629 { ISD::BITREVERSE, MVT::v8i16, 1 },
1630 { ISD::BITREVERSE, MVT::v16i8, 1 },
1631 { ISD::BITREVERSE, MVT::i64, 3 },
1632 { ISD::BITREVERSE, MVT::i32, 3 },
1633 { ISD::BITREVERSE, MVT::i16, 3 },
1634 { ISD::BITREVERSE, MVT::i8, 3 }
1635 };
1636 static const CostTblEntry AVX2CostTbl[] = {
1637 { ISD::BITREVERSE, MVT::v4i64, 5 },
1638 { ISD::BITREVERSE, MVT::v8i32, 5 },
1639 { ISD::BITREVERSE, MVT::v16i16, 5 },
1640 { ISD::BITREVERSE, MVT::v32i8, 5 },
1641 { ISD::BSWAP, MVT::v4i64, 1 },
1642 { ISD::BSWAP, MVT::v8i32, 1 },
1643 { ISD::BSWAP, MVT::v16i16, 1 },
1644 { ISD::CTLZ, MVT::v4i64, 23 },
1645 { ISD::CTLZ, MVT::v8i32, 18 },
1646 { ISD::CTLZ, MVT::v16i16, 14 },
1647 { ISD::CTLZ, MVT::v32i8, 9 },
1648 { ISD::CTPOP, MVT::v4i64, 7 },
1649 { ISD::CTPOP, MVT::v8i32, 11 },
1650 { ISD::CTPOP, MVT::v16i16, 9 },
1651 { ISD::CTPOP, MVT::v32i8, 6 },
1652 { ISD::CTTZ, MVT::v4i64, 10 },
1653 { ISD::CTTZ, MVT::v8i32, 14 },
1654 { ISD::CTTZ, MVT::v16i16, 12 },
1655 { ISD::CTTZ, MVT::v32i8, 9 },
1656 { ISD::FSQRT, MVT::f32, 7 }, // Haswell from http://www.agner.org/
1657 { ISD::FSQRT, MVT::v4f32, 7 }, // Haswell from http://www.agner.org/
1658 { ISD::FSQRT, MVT::v8f32, 14 }, // Haswell from http://www.agner.org/
1659 { ISD::FSQRT, MVT::f64, 14 }, // Haswell from http://www.agner.org/
1660 { ISD::FSQRT, MVT::v2f64, 14 }, // Haswell from http://www.agner.org/
1661 { ISD::FSQRT, MVT::v4f64, 28 }, // Haswell from http://www.agner.org/
1662 };
1663 static const CostTblEntry AVX1CostTbl[] = {
1664 { ISD::BITREVERSE, MVT::v4i64, 12 }, // 2 x 128-bit Op + extract/insert
1665 { ISD::BITREVERSE, MVT::v8i32, 12 }, // 2 x 128-bit Op + extract/insert
1666 { ISD::BITREVERSE, MVT::v16i16, 12 }, // 2 x 128-bit Op + extract/insert
1667 { ISD::BITREVERSE, MVT::v32i8, 12 }, // 2 x 128-bit Op + extract/insert
1668 { ISD::BSWAP, MVT::v4i64, 4 },
1669 { ISD::BSWAP, MVT::v8i32, 4 },
1670 { ISD::BSWAP, MVT::v16i16, 4 },
1671 { ISD::CTLZ, MVT::v4i64, 48 }, // 2 x 128-bit Op + extract/insert
1672 { ISD::CTLZ, MVT::v8i32, 38 }, // 2 x 128-bit Op + extract/insert
1673 { ISD::CTLZ, MVT::v16i16, 30 }, // 2 x 128-bit Op + extract/insert
1674 { ISD::CTLZ, MVT::v32i8, 20 }, // 2 x 128-bit Op + extract/insert
1675 { ISD::CTPOP, MVT::v4i64, 16 }, // 2 x 128-bit Op + extract/insert
1676 { ISD::CTPOP, MVT::v8i32, 24 }, // 2 x 128-bit Op + extract/insert
1677 { ISD::CTPOP, MVT::v16i16, 20 }, // 2 x 128-bit Op + extract/insert
1678 { ISD::CTPOP, MVT::v32i8, 14 }, // 2 x 128-bit Op + extract/insert
1679 { ISD::CTTZ, MVT::v4i64, 22 }, // 2 x 128-bit Op + extract/insert
1680 { ISD::CTTZ, MVT::v8i32, 30 }, // 2 x 128-bit Op + extract/insert
1681 { ISD::CTTZ, MVT::v16i16, 26 }, // 2 x 128-bit Op + extract/insert
1682 { ISD::CTTZ, MVT::v32i8, 20 }, // 2 x 128-bit Op + extract/insert
1683 { ISD::FSQRT, MVT::f32, 14 }, // SNB from http://www.agner.org/
1684 { ISD::FSQRT, MVT::v4f32, 14 }, // SNB from http://www.agner.org/
1685 { ISD::FSQRT, MVT::v8f32, 28 }, // SNB from http://www.agner.org/
1686 { ISD::FSQRT, MVT::f64, 21 }, // SNB from http://www.agner.org/
1687 { ISD::FSQRT, MVT::v2f64, 21 }, // SNB from http://www.agner.org/
1688 { ISD::FSQRT, MVT::v4f64, 43 }, // SNB from http://www.agner.org/
1689 };
1690 static const CostTblEntry GLMCostTbl[] = {
1691 { ISD::FSQRT, MVT::f32, 19 }, // sqrtss
1692 { ISD::FSQRT, MVT::v4f32, 37 }, // sqrtps
1693 { ISD::FSQRT, MVT::f64, 34 }, // sqrtsd
1694 { ISD::FSQRT, MVT::v2f64, 67 }, // sqrtpd
1695 };
1696 static const CostTblEntry SLMCostTbl[] = {
1697 { ISD::FSQRT, MVT::f32, 20 }, // sqrtss
1698 { ISD::FSQRT, MVT::v4f32, 40 }, // sqrtps
1699 { ISD::FSQRT, MVT::f64, 35 }, // sqrtsd
1700 { ISD::FSQRT, MVT::v2f64, 70 }, // sqrtpd
1701 };
1702 static const CostTblEntry SSE42CostTbl[] = {
1703 { ISD::FSQRT, MVT::f32, 18 }, // Nehalem from http://www.agner.org/
1704 { ISD::FSQRT, MVT::v4f32, 18 }, // Nehalem from http://www.agner.org/
1705 };
1706 static const CostTblEntry SSSE3CostTbl[] = {
1707 { ISD::BITREVERSE, MVT::v2i64, 5 },
1708 { ISD::BITREVERSE, MVT::v4i32, 5 },
1709 { ISD::BITREVERSE, MVT::v8i16, 5 },
1710 { ISD::BITREVERSE, MVT::v16i8, 5 },
1711 { ISD::BSWAP, MVT::v2i64, 1 },
1712 { ISD::BSWAP, MVT::v4i32, 1 },
1713 { ISD::BSWAP, MVT::v8i16, 1 },
1714 { ISD::CTLZ, MVT::v2i64, 23 },
1715 { ISD::CTLZ, MVT::v4i32, 18 },
1716 { ISD::CTLZ, MVT::v8i16, 14 },
1717 { ISD::CTLZ, MVT::v16i8, 9 },
1718 { ISD::CTPOP, MVT::v2i64, 7 },
1719 { ISD::CTPOP, MVT::v4i32, 11 },
1720 { ISD::CTPOP, MVT::v8i16, 9 },
1721 { ISD::CTPOP, MVT::v16i8, 6 },
1722 { ISD::CTTZ, MVT::v2i64, 10 },
1723 { ISD::CTTZ, MVT::v4i32, 14 },
1724 { ISD::CTTZ, MVT::v8i16, 12 },
1725 { ISD::CTTZ, MVT::v16i8, 9 }
1726 };
1727 static const CostTblEntry SSE2CostTbl[] = {
1728 { ISD::BITREVERSE, MVT::v2i64, 29 },
1729 { ISD::BITREVERSE, MVT::v4i32, 27 },
1730 { ISD::BITREVERSE, MVT::v8i16, 27 },
1731 { ISD::BITREVERSE, MVT::v16i8, 20 },
1732 { ISD::BSWAP, MVT::v2i64, 7 },
1733 { ISD::BSWAP, MVT::v4i32, 7 },
1734 { ISD::BSWAP, MVT::v8i16, 7 },
1735 { ISD::CTLZ, MVT::v2i64, 25 },
1736 { ISD::CTLZ, MVT::v4i32, 26 },
1737 { ISD::CTLZ, MVT::v8i16, 20 },
1738 { ISD::CTLZ, MVT::v16i8, 17 },
1739 { ISD::CTPOP, MVT::v2i64, 12 },
1740 { ISD::CTPOP, MVT::v4i32, 15 },
1741 { ISD::CTPOP, MVT::v8i16, 13 },
1742 { ISD::CTPOP, MVT::v16i8, 10 },
1743 { ISD::CTTZ, MVT::v2i64, 14 },
1744 { ISD::CTTZ, MVT::v4i32, 18 },
1745 { ISD::CTTZ, MVT::v8i16, 16 },
1746 { ISD::CTTZ, MVT::v16i8, 13 },
1747 { ISD::FSQRT, MVT::f64, 32 }, // Nehalem from http://www.agner.org/
1748 { ISD::FSQRT, MVT::v2f64, 32 }, // Nehalem from http://www.agner.org/
1749 };
1750 static const CostTblEntry SSE1CostTbl[] = {
1751 { ISD::FSQRT, MVT::f32, 28 }, // Pentium III from http://www.agner.org/
1752 { ISD::FSQRT, MVT::v4f32, 56 }, // Pentium III from http://www.agner.org/
1753 };
1754 static const CostTblEntry X64CostTbl[] = { // 64-bit targets
1755 { ISD::BITREVERSE, MVT::i64, 14 }
1756 };
1757 static const CostTblEntry X86CostTbl[] = { // 32 or 64-bit targets
1758 { ISD::BITREVERSE, MVT::i32, 14 },
1759 { ISD::BITREVERSE, MVT::i16, 14 },
1760 { ISD::BITREVERSE, MVT::i8, 11 }
1761 };
1762
1763 unsigned ISD = ISD::DELETED_NODE;
1764 switch (IID) {
1765 default:
1766 break;
1767 case Intrinsic::bitreverse:
1768 ISD = ISD::BITREVERSE;
1769 break;
1770 case Intrinsic::bswap:
1771 ISD = ISD::BSWAP;
1772 break;
1773 case Intrinsic::ctlz:
1774 ISD = ISD::CTLZ;
1775 break;
1776 case Intrinsic::ctpop:
1777 ISD = ISD::CTPOP;
1778 break;
1779 case Intrinsic::cttz:
1780 ISD = ISD::CTTZ;
1781 break;
1782 case Intrinsic::sqrt:
1783 ISD = ISD::FSQRT;
1784 break;
1785 }
1786
1787 // Legalize the type.
1788 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, RetTy);
1789 MVT MTy = LT.second;
1790
1791 // Attempt to lookup cost.
1792 if (ST->isGLM())
1793 if (const auto *Entry = CostTableLookup(GLMCostTbl, ISD, MTy))
1794 return LT.first * Entry->Cost;
1795
1796 if (ST->isSLM())
1797 if (const auto *Entry = CostTableLookup(SLMCostTbl, ISD, MTy))
1798 return LT.first * Entry->Cost;
1799
1800 if (ST->hasCDI())
1801 if (const auto *Entry = CostTableLookup(AVX512CDCostTbl, ISD, MTy))
1802 return LT.first * Entry->Cost;
1803
1804 if (ST->hasBWI())
1805 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy))
1806 return LT.first * Entry->Cost;
1807
1808 if (ST->hasAVX512())
1809 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy))
1810 return LT.first * Entry->Cost;
1811
1812 if (ST->hasXOP())
1813 if (const auto *Entry = CostTableLookup(XOPCostTbl, ISD, MTy))
1814 return LT.first * Entry->Cost;
1815
1816 if (ST->hasAVX2())
1817 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy))
1818 return LT.first * Entry->Cost;
1819
1820 if (ST->hasAVX())
1821 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy))
1822 return LT.first * Entry->Cost;
1823
1824 if (ST->hasSSE42())
1825 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy))
1826 return LT.first * Entry->Cost;
1827
1828 if (ST->hasSSSE3())
1829 if (const auto *Entry = CostTableLookup(SSSE3CostTbl, ISD, MTy))
1830 return LT.first * Entry->Cost;
1831
1832 if (ST->hasSSE2())
1833 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy))
1834 return LT.first * Entry->Cost;
1835
1836 if (ST->hasSSE1())
1837 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy))
1838 return LT.first * Entry->Cost;
1839
1840 if (ST->is64Bit())
1841 if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, MTy))
1842 return LT.first * Entry->Cost;
1843
1844 if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, MTy))
1845 return LT.first * Entry->Cost;
1846
1847 return BaseT::getIntrinsicInstrCost(IID, RetTy, Tys, FMF, ScalarizationCostPassed);
1848}
1849
1850int X86TTIImpl::getIntrinsicInstrCost(Intrinsic::ID IID, Type *RetTy,
1851 ArrayRef<Value *> Args, FastMathFlags FMF, unsigned VF) {
1852 return BaseT::getIntrinsicInstrCost(IID, RetTy, Args, FMF, VF);
1853}
1854
1855int X86TTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index) {
1856 assert(Val->isVectorTy() && "This must be a vector type")(static_cast <bool> (Val->isVectorTy() && "This must be a vector type"
) ? void (0) : __assert_fail ("Val->isVectorTy() && \"This must be a vector type\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86TargetTransformInfo.cpp"
, 1856, __extension__ __PRETTY_FUNCTION__))
;
1857
1858 Type *ScalarType = Val->getScalarType();
1859
1860 if (Index != -1U) {
1861 // Legalize the type.
1862 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Val);
1863
1864 // This type is legalized to a scalar type.
1865 if (!LT.second.isVector())
1866 return 0;
1867
1868 // The type may be split. Normalize the index to the new type.
1869 unsigned Width = LT.second.getVectorNumElements();
1870 Index = Index % Width;
1871
1872 // Floating point scalars are already located in index #0.
1873 if (ScalarType->isFloatingPointTy() && Index == 0)
1874 return 0;
1875 }
1876
1877 // Add to the base cost if we know that the extracted element of a vector is
1878 // destined to be moved to and used in the integer register file.
1879 int RegisterFileMoveCost = 0;
1880 if (Opcode == Instruction::ExtractElement && ScalarType->isPointerTy())
1881 RegisterFileMoveCost = 1;
1882
1883 return BaseT::getVectorInstrCost(Opcode, Val, Index) + RegisterFileMoveCost;
1884}
1885
1886int X86TTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment,
1887 unsigned AddressSpace, const Instruction *I) {
1888 // Handle non-power-of-two vectors such as <3 x float>
1889 if (VectorType *VTy = dyn_cast<VectorType>(Src)) {
1890 unsigned NumElem = VTy->getVectorNumElements();
1891
1892 // Handle a few common cases:
1893 // <3 x float>
1894 if (NumElem == 3 && VTy->getScalarSizeInBits() == 32)
1895 // Cost = 64 bit store + extract + 32 bit store.
1896 return 3;
1897
1898 // <3 x double>
1899 if (NumElem == 3 && VTy->getScalarSizeInBits() == 64)
1900 // Cost = 128 bit store + unpack + 64 bit store.
1901 return 3;
1902
1903 // Assume that all other non-power-of-two numbers are scalarized.
1904 if (!isPowerOf2_32(NumElem)) {
1905 int Cost = BaseT::getMemoryOpCost(Opcode, VTy->getScalarType(), Alignment,
1906 AddressSpace);
1907 int SplitCost = getScalarizationOverhead(Src, Opcode == Instruction::Load,
1908 Opcode == Instruction::Store);
1909 return NumElem * Cost + SplitCost;
1910 }
1911 }
1912
1913 // Legalize the type.
1914 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Src);
1915 assert((Opcode == Instruction::Load || Opcode == Instruction::Store) &&(static_cast <bool> ((Opcode == Instruction::Load || Opcode
== Instruction::Store) && "Invalid Opcode") ? void (
0) : __assert_fail ("(Opcode == Instruction::Load || Opcode == Instruction::Store) && \"Invalid Opcode\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86TargetTransformInfo.cpp"
, 1916, __extension__ __PRETTY_FUNCTION__))
1916 "Invalid Opcode")(static_cast <bool> ((Opcode == Instruction::Load || Opcode
== Instruction::Store) && "Invalid Opcode") ? void (
0) : __assert_fail ("(Opcode == Instruction::Load || Opcode == Instruction::Store) && \"Invalid Opcode\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86TargetTransformInfo.cpp"
, 1916, __extension__ __PRETTY_FUNCTION__))
;
1917
1918 // Each load/store unit costs 1.
1919 int Cost = LT.first * 1;
1920
1921 // This isn't exactly right. We're using slow unaligned 32-byte accesses as a
1922 // proxy for a double-pumped AVX memory interface such as on Sandybridge.
1923 if (LT.second.getStoreSize() == 32 && ST->isUnalignedMem32Slow())
1924 Cost *= 2;
1925
1926 return Cost;
1927}
1928
1929int X86TTIImpl::getMaskedMemoryOpCost(unsigned Opcode, Type *SrcTy,
1930 unsigned Alignment,
1931 unsigned AddressSpace) {
1932 VectorType *SrcVTy = dyn_cast<VectorType>(SrcTy);
1933 if (!SrcVTy)
1934 // To calculate scalar take the regular cost, without mask
1935 return getMemoryOpCost(Opcode, SrcTy, Alignment, AddressSpace);
1936
1937 unsigned NumElem = SrcVTy->getVectorNumElements();
1938 VectorType *MaskTy =
1939 VectorType::get(Type::getInt8Ty(SrcVTy->getContext()), NumElem);
1940 if ((Opcode == Instruction::Load && !isLegalMaskedLoad(SrcVTy)) ||
1941 (Opcode == Instruction::Store && !isLegalMaskedStore(SrcVTy)) ||
1942 !isPowerOf2_32(NumElem)) {
1943 // Scalarization
1944 int MaskSplitCost = getScalarizationOverhead(MaskTy, false, true);
1945 int ScalarCompareCost = getCmpSelInstrCost(
1946 Instruction::ICmp, Type::getInt8Ty(SrcVTy->getContext()), nullptr);
1947 int BranchCost = getCFInstrCost(Instruction::Br);
1948 int MaskCmpCost = NumElem * (BranchCost + ScalarCompareCost);
1949
1950 int ValueSplitCost = getScalarizationOverhead(
1951 SrcVTy, Opcode == Instruction::Load, Opcode == Instruction::Store);
1952 int MemopCost =
1953 NumElem * BaseT::getMemoryOpCost(Opcode, SrcVTy->getScalarType(),
1954 Alignment, AddressSpace);
1955 return MemopCost + ValueSplitCost + MaskSplitCost + MaskCmpCost;
1956 }
1957
1958 // Legalize the type.
1959 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, SrcVTy);
1960 auto VT = TLI->getValueType(DL, SrcVTy);
1961 int Cost = 0;
1962 if (VT.isSimple() && LT.second != VT.getSimpleVT() &&
1963 LT.second.getVectorNumElements() == NumElem)
1964 // Promotion requires expand/truncate for data and a shuffle for mask.
1965 Cost += getShuffleCost(TTI::SK_Alternate, SrcVTy, 0, nullptr) +
1966 getShuffleCost(TTI::SK_Alternate, MaskTy, 0, nullptr);
1967
1968 else if (LT.second.getVectorNumElements() > NumElem) {
1969 VectorType *NewMaskTy = VectorType::get(MaskTy->getVectorElementType(),
1970 LT.second.getVectorNumElements());
1971 // Expanding requires fill mask with zeroes
1972 Cost += getShuffleCost(TTI::SK_InsertSubvector, NewMaskTy, 0, MaskTy);
1973 }
1974 if (!ST->hasAVX512())
1975 return Cost + LT.first*4; // Each maskmov costs 4
1976
1977 // AVX-512 masked load/store is cheapper
1978 return Cost+LT.first;
1979}
1980
1981int X86TTIImpl::getAddressComputationCost(Type *Ty, ScalarEvolution *SE,
1982 const SCEV *Ptr) {
1983 // Address computations in vectorized code with non-consecutive addresses will
1984 // likely result in more instructions compared to scalar code where the
1985 // computation can more often be merged into the index mode. The resulting
1986 // extra micro-ops can significantly decrease throughput.
1987 unsigned NumVectorInstToHideOverhead = 10;
1988
1989 // Cost modeling of Strided Access Computation is hidden by the indexing
1990 // modes of X86 regardless of the stride value. We dont believe that there
1991 // is a difference between constant strided access in gerenal and constant
1992 // strided value which is less than or equal to 64.
1993 // Even in the case of (loop invariant) stride whose value is not known at
1994 // compile time, the address computation will not incur more than one extra
1995 // ADD instruction.
1996 if (Ty->isVectorTy() && SE) {
1997 if (!BaseT::isStridedAccess(Ptr))
1998 return NumVectorInstToHideOverhead;
1999 if (!BaseT::getConstantStrideStep(SE, Ptr))
2000 return 1;
2001 }
2002
2003 return BaseT::getAddressComputationCost(Ty, SE, Ptr);
2004}
2005
2006int X86TTIImpl::getArithmeticReductionCost(unsigned Opcode, Type *ValTy,
2007 bool IsPairwise) {
2008
2009 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy);
2010
2011 MVT MTy = LT.second;
2012
2013 int ISD = TLI->InstructionOpcodeToISD(Opcode);
2014 assert(ISD && "Invalid opcode")(static_cast <bool> (ISD && "Invalid opcode") ?
void (0) : __assert_fail ("ISD && \"Invalid opcode\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86TargetTransformInfo.cpp"
, 2014, __extension__ __PRETTY_FUNCTION__))
;
2015
2016 // We use the Intel Architecture Code Analyzer(IACA) to measure the throughput
2017 // and make it as the cost.
2018
2019 static const CostTblEntry SSE42CostTblPairWise[] = {
2020 { ISD::FADD, MVT::v2f64, 2 },
2021 { ISD::FADD, MVT::v4f32, 4 },
2022 { ISD::ADD, MVT::v2i64, 2 }, // The data reported by the IACA tool is "1.6".
2023 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.5".
2024 { ISD::ADD, MVT::v8i16, 5 },
2025 };
2026
2027 static const CostTblEntry AVX1CostTblPairWise[] = {
2028 { ISD::FADD, MVT::v4f32, 4 },
2029 { ISD::FADD, MVT::v4f64, 5 },
2030 { ISD::FADD, MVT::v8f32, 7 },
2031 { ISD::ADD, MVT::v2i64, 1 }, // The data reported by the IACA tool is "1.5".
2032 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.5".
2033 { ISD::ADD, MVT::v4i64, 5 }, // The data reported by the IACA tool is "4.8".
2034 { ISD::ADD, MVT::v8i16, 5 },
2035 { ISD::ADD, MVT::v8i32, 5 },
2036 };
2037
2038 static const CostTblEntry SSE42CostTblNoPairWise[] = {
2039 { ISD::FADD, MVT::v2f64, 2 },
2040 { ISD::FADD, MVT::v4f32, 4 },
2041 { ISD::ADD, MVT::v2i64, 2 }, // The data reported by the IACA tool is "1.6".
2042 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.3".
2043 { ISD::ADD, MVT::v8i16, 4 }, // The data reported by the IACA tool is "4.3".
2044 };
2045
2046 static const CostTblEntry AVX1CostTblNoPairWise[] = {
2047 { ISD::FADD, MVT::v4f32, 3 },
2048 { ISD::FADD, MVT::v4f64, 3 },
2049 { ISD::FADD, MVT::v8f32, 4 },
2050 { ISD::ADD, MVT::v2i64, 1 }, // The data reported by the IACA tool is "1.5".
2051 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "2.8".
2052 { ISD::ADD, MVT::v4i64, 3 },
2053 { ISD::ADD, MVT::v8i16, 4 },
2054 { ISD::ADD, MVT::v8i32, 5 },
2055 };
2056
2057 if (IsPairwise) {
2058 if (ST->hasAVX())
2059 if (const auto *Entry = CostTableLookup(AVX1CostTblPairWise, ISD, MTy))
2060 return LT.first * Entry->Cost;
2061
2062 if (ST->hasSSE42())
2063 if (const auto *Entry = CostTableLookup(SSE42CostTblPairWise, ISD, MTy))
2064 return LT.first * Entry->Cost;
2065 } else {
2066 if (ST->hasAVX())
2067 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy))
2068 return LT.first * Entry->Cost;
2069
2070 if (ST->hasSSE42())
2071 if (const auto *Entry = CostTableLookup(SSE42CostTblNoPairWise, ISD, MTy))
2072 return LT.first * Entry->Cost;
2073 }
2074
2075 return BaseT::getArithmeticReductionCost(Opcode, ValTy, IsPairwise);
2076}
2077
2078int X86TTIImpl::getMinMaxReductionCost(Type *ValTy, Type *CondTy,
2079 bool IsPairwise, bool IsUnsigned) {
2080 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy);
2081
2082 MVT MTy = LT.second;
2083
2084 int ISD;
2085 if (ValTy->isIntOrIntVectorTy()) {
2086 ISD = IsUnsigned ? ISD::UMIN : ISD::SMIN;
2087 } else {
2088 assert(ValTy->isFPOrFPVectorTy() &&(static_cast <bool> (ValTy->isFPOrFPVectorTy() &&
"Expected float point or integer vector type.") ? void (0) :
__assert_fail ("ValTy->isFPOrFPVectorTy() && \"Expected float point or integer vector type.\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86TargetTransformInfo.cpp"
, 2089, __extension__ __PRETTY_FUNCTION__))
2089 "Expected float point or integer vector type.")(static_cast <bool> (ValTy->isFPOrFPVectorTy() &&
"Expected float point or integer vector type.") ? void (0) :
__assert_fail ("ValTy->isFPOrFPVectorTy() && \"Expected float point or integer vector type.\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86TargetTransformInfo.cpp"
, 2089, __extension__ __PRETTY_FUNCTION__))
;
2090 ISD = ISD::FMINNUM;
2091 }
2092
2093 // We use the Intel Architecture Code Analyzer(IACA) to measure the throughput
2094 // and make it as the cost.
2095
2096 static const CostTblEntry SSE42CostTblPairWise[] = {
2097 {ISD::FMINNUM, MVT::v2f64, 3},
2098 {ISD::FMINNUM, MVT::v4f32, 2},
2099 {ISD::SMIN, MVT::v2i64, 7}, // The data reported by the IACA is "6.8"
2100 {ISD::UMIN, MVT::v2i64, 8}, // The data reported by the IACA is "8.6"
2101 {ISD::SMIN, MVT::v4i32, 1}, // The data reported by the IACA is "1.5"
2102 {ISD::UMIN, MVT::v4i32, 2}, // The data reported by the IACA is "1.8"
2103 {ISD::SMIN, MVT::v8i16, 2},
2104 {ISD::UMIN, MVT::v8i16, 2},
2105 };
2106
2107 static const CostTblEntry AVX1CostTblPairWise[] = {
2108 {ISD::FMINNUM, MVT::v4f32, 1},
2109 {ISD::FMINNUM, MVT::v4f64, 1},
2110 {ISD::FMINNUM, MVT::v8f32, 2},
2111 {ISD::SMIN, MVT::v2i64, 3},
2112 {ISD::UMIN, MVT::v2i64, 3},
2113 {ISD::SMIN, MVT::v4i32, 1},
2114 {ISD::UMIN, MVT::v4i32, 1},
2115 {ISD::SMIN, MVT::v8i16, 1},
2116 {ISD::UMIN, MVT::v8i16, 1},
2117 {ISD::SMIN, MVT::v8i32, 3},
2118 {ISD::UMIN, MVT::v8i32, 3},
2119 };
2120
2121 static const CostTblEntry AVX2CostTblPairWise[] = {
2122 {ISD::SMIN, MVT::v4i64, 2},
2123 {ISD::UMIN, MVT::v4i64, 2},
2124 {ISD::SMIN, MVT::v8i32, 1},
2125 {ISD::UMIN, MVT::v8i32, 1},
2126 {ISD::SMIN, MVT::v16i16, 1},
2127 {ISD::UMIN, MVT::v16i16, 1},
2128 {ISD::SMIN, MVT::v32i8, 2},
2129 {ISD::UMIN, MVT::v32i8, 2},
2130 };
2131
2132 static const CostTblEntry AVX512CostTblPairWise[] = {
2133 {ISD::FMINNUM, MVT::v8f64, 1},
2134 {ISD::FMINNUM, MVT::v16f32, 2},
2135 {ISD::SMIN, MVT::v8i64, 2},
2136 {ISD::UMIN, MVT::v8i64, 2},
2137 {ISD::SMIN, MVT::v16i32, 1},
2138 {ISD::UMIN, MVT::v16i32, 1},
2139 };
2140
2141 static const CostTblEntry SSE42CostTblNoPairWise[] = {
2142 {ISD::FMINNUM, MVT::v2f64, 3},
2143 {ISD::FMINNUM, MVT::v4f32, 3},
2144 {ISD::SMIN, MVT::v2i64, 7}, // The data reported by the IACA is "6.8"
2145 {ISD::UMIN, MVT::v2i64, 9}, // The data reported by the IACA is "8.6"
2146 {ISD::SMIN, MVT::v4i32, 1}, // The data reported by the IACA is "1.5"
2147 {ISD::UMIN, MVT::v4i32, 2}, // The data reported by the IACA is "1.8"
2148 {ISD::SMIN, MVT::v8i16, 1}, // The data reported by the IACA is "1.5"
2149 {ISD::UMIN, MVT::v8i16, 2}, // The data reported by the IACA is "1.8"
2150 };
2151
2152 static const CostTblEntry AVX1CostTblNoPairWise[] = {
2153 {ISD::FMINNUM, MVT::v4f32, 1},
2154 {ISD::FMINNUM, MVT::v4f64, 1},
2155 {ISD::FMINNUM, MVT::v8f32, 1},
2156 {ISD::SMIN, MVT::v2i64, 3},
2157 {ISD::UMIN, MVT::v2i64, 3},
2158 {ISD::SMIN, MVT::v4i32, 1},
2159 {ISD::UMIN, MVT::v4i32, 1},
2160 {ISD::SMIN, MVT::v8i16, 1},
2161 {ISD::UMIN, MVT::v8i16, 1},
2162 {ISD::SMIN, MVT::v8i32, 2},
2163 {ISD::UMIN, MVT::v8i32, 2},
2164 };
2165
2166 static const CostTblEntry AVX2CostTblNoPairWise[] = {
2167 {ISD::SMIN, MVT::v4i64, 1},
2168 {ISD::UMIN, MVT::v4i64, 1},
2169 {ISD::SMIN, MVT::v8i32, 1},
2170 {ISD::UMIN, MVT::v8i32, 1},
2171 {ISD::SMIN, MVT::v16i16, 1},
2172 {ISD::UMIN, MVT::v16i16, 1},
2173 {ISD::SMIN, MVT::v32i8, 1},
2174 {ISD::UMIN, MVT::v32i8, 1},
2175 };
2176
2177 static const CostTblEntry AVX512CostTblNoPairWise[] = {
2178 {ISD::FMINNUM, MVT::v8f64, 1},
2179 {ISD::FMINNUM, MVT::v16f32, 2},
2180 {ISD::SMIN, MVT::v8i64, 1},
2181 {ISD::UMIN, MVT::v8i64, 1},
2182 {ISD::SMIN, MVT::v16i32, 1},
2183 {ISD::UMIN, MVT::v16i32, 1},
2184 };
2185
2186 if (IsPairwise) {
2187 if (ST->hasAVX512())
2188 if (const auto *Entry = CostTableLookup(AVX512CostTblPairWise, ISD, MTy))
2189 return LT.first * Entry->Cost;
2190
2191 if (ST->hasAVX2())
2192 if (const auto *Entry = CostTableLookup(AVX2CostTblPairWise, ISD, MTy))
2193 return LT.first * Entry->Cost;
2194
2195 if (ST->hasAVX())
2196 if (const auto *Entry = CostTableLookup(AVX1CostTblPairWise, ISD, MTy))
2197 return LT.first * Entry->Cost;
2198
2199 if (ST->hasSSE42())
2200 if (const auto *Entry = CostTableLookup(SSE42CostTblPairWise, ISD, MTy))
2201 return LT.first * Entry->Cost;
2202 } else {
2203 if (ST->hasAVX512())
2204 if (const auto *Entry =
2205 CostTableLookup(AVX512CostTblNoPairWise, ISD, MTy))
2206 return LT.first * Entry->Cost;
2207
2208 if (ST->hasAVX2())
2209 if (const auto *Entry = CostTableLookup(AVX2CostTblNoPairWise, ISD, MTy))
2210 return LT.first * Entry->Cost;
2211
2212 if (ST->hasAVX())
2213 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy))
2214 return LT.first * Entry->Cost;
2215
2216 if (ST->hasSSE42())
2217 if (const auto *Entry = CostTableLookup(SSE42CostTblNoPairWise, ISD, MTy))
2218 return LT.first * Entry->Cost;
2219 }
2220
2221 return BaseT::getMinMaxReductionCost(ValTy, CondTy, IsPairwise, IsUnsigned);
2222}
2223
2224/// \brief Calculate the cost of materializing a 64-bit value. This helper
2225/// method might only calculate a fraction of a larger immediate. Therefore it
2226/// is valid to return a cost of ZERO.
2227int X86TTIImpl::getIntImmCost(int64_t Val) {
2228 if (Val == 0)
2229 return TTI::TCC_Free;
2230
2231 if (isInt<32>(Val))
2232 return TTI::TCC_Basic;
2233
2234 return 2 * TTI::TCC_Basic;
2235}
2236
2237int X86TTIImpl::getIntImmCost(const APInt &Imm, Type *Ty) {
2238 assert(Ty->isIntegerTy())(static_cast <bool> (Ty->isIntegerTy()) ? void (0) :
__assert_fail ("Ty->isIntegerTy()", "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86TargetTransformInfo.cpp"
, 2238, __extension__ __PRETTY_FUNCTION__))
;
2239
2240 unsigned BitSize = Ty->getPrimitiveSizeInBits();
2241 if (BitSize == 0)
2242 return ~0U;
2243
2244 // Never hoist constants larger than 128bit, because this might lead to
2245 // incorrect code generation or assertions in codegen.
2246 // Fixme: Create a cost model for types larger than i128 once the codegen
2247 // issues have been fixed.
2248 if (BitSize > 128)
2249 return TTI::TCC_Free;
2250
2251 if (Imm == 0)
2252 return TTI::TCC_Free;
2253
2254 // Sign-extend all constants to a multiple of 64-bit.
2255 APInt ImmVal = Imm;
2256 if (BitSize & 0x3f)
2257 ImmVal = Imm.sext((BitSize + 63) & ~0x3fU);
2258
2259 // Split the constant into 64-bit chunks and calculate the cost for each
2260 // chunk.
2261 int Cost = 0;
2262 for (unsigned ShiftVal = 0; ShiftVal < BitSize; ShiftVal += 64) {
2263 APInt Tmp = ImmVal.ashr(ShiftVal).sextOrTrunc(64);
2264 int64_t Val = Tmp.getSExtValue();
2265 Cost += getIntImmCost(Val);
2266 }
2267 // We need at least one instruction to materialize the constant.
2268 return std::max(1, Cost);
2269}
2270
2271int X86TTIImpl::getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm,
2272 Type *Ty) {
2273 assert(Ty->isIntegerTy())(static_cast <bool> (Ty->isIntegerTy()) ? void (0) :
__assert_fail ("Ty->isIntegerTy()", "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86TargetTransformInfo.cpp"
, 2273, __extension__ __PRETTY_FUNCTION__))
;
2274
2275 unsigned BitSize = Ty->getPrimitiveSizeInBits();
2276 // There is no cost model for constants with a bit size of 0. Return TCC_Free
2277 // here, so that constant hoisting will ignore this constant.
2278 if (BitSize == 0)
2279 return TTI::TCC_Free;
2280
2281 unsigned ImmIdx = ~0U;
2282 switch (Opcode) {
2283 default:
2284 return TTI::TCC_Free;
2285 case Instruction::GetElementPtr:
2286 // Always hoist the base address of a GetElementPtr. This prevents the
2287 // creation of new constants for every base constant that gets constant
2288 // folded with the offset.
2289 if (Idx == 0)
2290 return 2 * TTI::TCC_Basic;
2291 return TTI::TCC_Free;
2292 case Instruction::Store:
2293 ImmIdx = 0;
2294 break;
2295 case Instruction::ICmp:
2296 // This is an imperfect hack to prevent constant hoisting of
2297 // compares that might be trying to check if a 64-bit value fits in
2298 // 32-bits. The backend can optimize these cases using a right shift by 32.
2299 // Ideally we would check the compare predicate here. There also other
2300 // similar immediates the backend can use shifts for.
2301 if (Idx == 1 && Imm.getBitWidth() == 64) {
2302 uint64_t ImmVal = Imm.getZExtValue();
2303 if (ImmVal == 0x100000000ULL || ImmVal == 0xffffffff)
2304 return TTI::TCC_Free;
2305 }
2306 ImmIdx = 1;
2307 break;
2308 case Instruction::And:
2309 // We support 64-bit ANDs with immediates with 32-bits of leading zeroes
2310 // by using a 32-bit operation with implicit zero extension. Detect such
2311 // immediates here as the normal path expects bit 31 to be sign extended.
2312 if (Idx == 1 && Imm.getBitWidth() == 64 && isUInt<32>(Imm.getZExtValue()))
2313 return TTI::TCC_Free;
2314 LLVM_FALLTHROUGH[[clang::fallthrough]];
2315 case Instruction::Add:
2316 case Instruction::Sub:
2317 case Instruction::Mul:
2318 case Instruction::UDiv:
2319 case Instruction::SDiv:
2320 case Instruction::URem:
2321 case Instruction::SRem:
2322 case Instruction::Or:
2323 case Instruction::Xor:
2324 ImmIdx = 1;
2325 break;
2326 // Always return TCC_Free for the shift value of a shift instruction.
2327 case Instruction::Shl:
2328 case Instruction::LShr:
2329 case Instruction::AShr:
2330 if (Idx == 1)
2331 return TTI::TCC_Free;
2332 break;
2333 case Instruction::Trunc:
2334 case Instruction::ZExt:
2335 case Instruction::SExt:
2336 case Instruction::IntToPtr:
2337 case Instruction::PtrToInt:
2338 case Instruction::BitCast:
2339 case Instruction::PHI:
2340 case Instruction::Call:
2341 case Instruction::Select:
2342 case Instruction::Ret:
2343 case Instruction::Load:
2344 break;
2345 }
2346
2347 if (Idx == ImmIdx) {
2348 int NumConstants = (BitSize + 63) / 64;
2349 int Cost = X86TTIImpl::getIntImmCost(Imm, Ty);
2350 return (Cost <= NumConstants * TTI::TCC_Basic)
2351 ? static_cast<int>(TTI::TCC_Free)
2352 : Cost;
2353 }
2354
2355 return X86TTIImpl::getIntImmCost(Imm, Ty);
2356}
2357
2358int X86TTIImpl::getIntImmCost(Intrinsic::ID IID, unsigned Idx, const APInt &Imm,
2359 Type *Ty) {
2360 assert(Ty->isIntegerTy())(static_cast <bool> (Ty->isIntegerTy()) ? void (0) :
__assert_fail ("Ty->isIntegerTy()", "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86TargetTransformInfo.cpp"
, 2360, __extension__ __PRETTY_FUNCTION__))
;
2361
2362 unsigned BitSize = Ty->getPrimitiveSizeInBits();
2363 // There is no cost model for constants with a bit size of 0. Return TCC_Free
2364 // here, so that constant hoisting will ignore this constant.
2365 if (BitSize == 0)
2366 return TTI::TCC_Free;
2367
2368 switch (IID) {
2369 default:
2370 return TTI::TCC_Free;
2371 case Intrinsic::sadd_with_overflow:
2372 case Intrinsic::uadd_with_overflow:
2373 case Intrinsic::ssub_with_overflow:
2374 case Intrinsic::usub_with_overflow:
2375 case Intrinsic::smul_with_overflow:
2376 case Intrinsic::umul_with_overflow:
2377 if ((Idx == 1) && Imm.getBitWidth() <= 64 && isInt<32>(Imm.getSExtValue()))
2378 return TTI::TCC_Free;
2379 break;
2380 case Intrinsic::experimental_stackmap:
2381 if ((Idx < 2) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue())))
2382 return TTI::TCC_Free;
2383 break;
2384 case Intrinsic::experimental_patchpoint_void:
2385 case Intrinsic::experimental_patchpoint_i64:
2386 if ((Idx < 4) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue())))
2387 return TTI::TCC_Free;
2388 break;
2389 }
2390 return X86TTIImpl::getIntImmCost(Imm, Ty);
2391}
2392
2393unsigned X86TTIImpl::getUserCost(const User *U,
2394 ArrayRef<const Value *> Operands) {
2395 if (isa<StoreInst>(U)) {
1
Taking false branch
2396 Value *Ptr = U->getOperand(1);
2397 // Store instruction with index and scale costs 2 Uops.
2398 // Check the preceding GEP to identify non-const indices.
2399 if (auto GEP = dyn_cast<GetElementPtrInst>(Ptr)) {
2400 if (!all_of(GEP->indices(), [](Value *V) { return isa<Constant>(V); }))
2401 return TTI::TCC_Basic * 2;
2402 }
2403 return TTI::TCC_Basic;
2404 }
2405 return BaseT::getUserCost(U, Operands);
2
Calling 'TargetTransformInfoImplCRTPBase::getUserCost'
2406}
2407
2408// Return an average cost of Gather / Scatter instruction, maybe improved later
2409int X86TTIImpl::getGSVectorCost(unsigned Opcode, Type *SrcVTy, Value *Ptr,
2410 unsigned Alignment, unsigned AddressSpace) {
2411
2412 assert(isa<VectorType>(SrcVTy) && "Unexpected type in getGSVectorCost")(static_cast <bool> (isa<VectorType>(SrcVTy) &&
"Unexpected type in getGSVectorCost") ? void (0) : __assert_fail
("isa<VectorType>(SrcVTy) && \"Unexpected type in getGSVectorCost\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86TargetTransformInfo.cpp"
, 2412, __extension__ __PRETTY_FUNCTION__))
;
2413 unsigned VF = SrcVTy->getVectorNumElements();
2414
2415 // Try to reduce index size from 64 bit (default for GEP)
2416 // to 32. It is essential for VF 16. If the index can't be reduced to 32, the
2417 // operation will use 16 x 64 indices which do not fit in a zmm and needs
2418 // to split. Also check that the base pointer is the same for all lanes,
2419 // and that there's at most one variable index.
2420 auto getIndexSizeInBits = [](Value *Ptr, const DataLayout& DL) {
2421 unsigned IndexSize = DL.getPointerSizeInBits();
2422 GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(Ptr);
2423 if (IndexSize < 64 || !GEP)
2424 return IndexSize;
2425
2426 unsigned NumOfVarIndices = 0;
2427 Value *Ptrs = GEP->getPointerOperand();
2428 if (Ptrs->getType()->isVectorTy() && !getSplatValue(Ptrs))
2429 return IndexSize;
2430 for (unsigned i = 1; i < GEP->getNumOperands(); ++i) {
2431 if (isa<Constant>(GEP->getOperand(i)))
2432 continue;
2433 Type *IndxTy = GEP->getOperand(i)->getType();
2434 if (IndxTy->isVectorTy())
2435 IndxTy = IndxTy->getVectorElementType();
2436 if ((IndxTy->getPrimitiveSizeInBits() == 64 &&
2437 !isa<SExtInst>(GEP->getOperand(i))) ||
2438 ++NumOfVarIndices > 1)
2439 return IndexSize; // 64
2440 }
2441 return (unsigned)32;
2442 };
2443
2444
2445 // Trying to reduce IndexSize to 32 bits for vector 16.
2446 // By default the IndexSize is equal to pointer size.
2447 unsigned IndexSize = (ST->hasAVX512() && VF >= 16)
2448 ? getIndexSizeInBits(Ptr, DL)
2449 : DL.getPointerSizeInBits();
2450
2451 Type *IndexVTy = VectorType::get(IntegerType::get(SrcVTy->getContext(),
2452 IndexSize), VF);
2453 std::pair<int, MVT> IdxsLT = TLI->getTypeLegalizationCost(DL, IndexVTy);
2454 std::pair<int, MVT> SrcLT = TLI->getTypeLegalizationCost(DL, SrcVTy);
2455 int SplitFactor = std::max(IdxsLT.first, SrcLT.first);
2456 if (SplitFactor > 1) {
2457 // Handle splitting of vector of pointers
2458 Type *SplitSrcTy = VectorType::get(SrcVTy->getScalarType(), VF / SplitFactor);
2459 return SplitFactor * getGSVectorCost(Opcode, SplitSrcTy, Ptr, Alignment,
2460 AddressSpace);
2461 }
2462
2463 // The gather / scatter cost is given by Intel architects. It is a rough
2464 // number since we are looking at one instruction in a time.
2465 const int GSOverhead = (Opcode == Instruction::Load)
2466 ? ST->getGatherOverhead()
2467 : ST->getScatterOverhead();
2468 return GSOverhead + VF * getMemoryOpCost(Opcode, SrcVTy->getScalarType(),
2469 Alignment, AddressSpace);
2470}
2471
2472/// Return the cost of full scalarization of gather / scatter operation.
2473///
2474/// Opcode - Load or Store instruction.
2475/// SrcVTy - The type of the data vector that should be gathered or scattered.
2476/// VariableMask - The mask is non-constant at compile time.
2477/// Alignment - Alignment for one element.
2478/// AddressSpace - pointer[s] address space.
2479///
2480int X86TTIImpl::getGSScalarCost(unsigned Opcode, Type *SrcVTy,
2481 bool VariableMask, unsigned Alignment,
2482 unsigned AddressSpace) {
2483 unsigned VF = SrcVTy->getVectorNumElements();
2484
2485 int MaskUnpackCost = 0;
2486 if (VariableMask) {
2487 VectorType *MaskTy =
2488 VectorType::get(Type::getInt1Ty(SrcVTy->getContext()), VF);
2489 MaskUnpackCost = getScalarizationOverhead(MaskTy, false, true);
2490 int ScalarCompareCost =
2491 getCmpSelInstrCost(Instruction::ICmp, Type::getInt1Ty(SrcVTy->getContext()),
2492 nullptr);
2493 int BranchCost = getCFInstrCost(Instruction::Br);
2494 MaskUnpackCost += VF * (BranchCost + ScalarCompareCost);
2495 }
2496
2497 // The cost of the scalar loads/stores.
2498 int MemoryOpCost = VF * getMemoryOpCost(Opcode, SrcVTy->getScalarType(),
2499 Alignment, AddressSpace);
2500
2501 int InsertExtractCost = 0;
2502 if (Opcode == Instruction::Load)
2503 for (unsigned i = 0; i < VF; ++i)
2504 // Add the cost of inserting each scalar load into the vector
2505 InsertExtractCost +=
2506 getVectorInstrCost(Instruction::InsertElement, SrcVTy, i);
2507 else
2508 for (unsigned i = 0; i < VF; ++i)
2509 // Add the cost of extracting each element out of the data vector
2510 InsertExtractCost +=
2511 getVectorInstrCost(Instruction::ExtractElement, SrcVTy, i);
2512
2513 return MemoryOpCost + MaskUnpackCost + InsertExtractCost;
2514}
2515
2516/// Calculate the cost of Gather / Scatter operation
2517int X86TTIImpl::getGatherScatterOpCost(unsigned Opcode, Type *SrcVTy,
2518 Value *Ptr, bool VariableMask,
2519 unsigned Alignment) {
2520 assert(SrcVTy->isVectorTy() && "Unexpected data type for Gather/Scatter")(static_cast <bool> (SrcVTy->isVectorTy() &&
"Unexpected data type for Gather/Scatter") ? void (0) : __assert_fail
("SrcVTy->isVectorTy() && \"Unexpected data type for Gather/Scatter\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86TargetTransformInfo.cpp"
, 2520, __extension__ __PRETTY_FUNCTION__))
;
2521 unsigned VF = SrcVTy->getVectorNumElements();
2522 PointerType *PtrTy = dyn_cast<PointerType>(Ptr->getType());
2523 if (!PtrTy && Ptr->getType()->isVectorTy())
2524 PtrTy = dyn_cast<PointerType>(Ptr->getType()->getVectorElementType());
2525 assert(PtrTy && "Unexpected type for Ptr argument")(static_cast <bool> (PtrTy && "Unexpected type for Ptr argument"
) ? void (0) : __assert_fail ("PtrTy && \"Unexpected type for Ptr argument\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86TargetTransformInfo.cpp"
, 2525, __extension__ __PRETTY_FUNCTION__))
;
2526 unsigned AddressSpace = PtrTy->getAddressSpace();
2527
2528 bool Scalarize = false;
2529 if ((Opcode == Instruction::Load && !isLegalMaskedGather(SrcVTy)) ||
2530 (Opcode == Instruction::Store && !isLegalMaskedScatter(SrcVTy)))
2531 Scalarize = true;
2532 // Gather / Scatter for vector 2 is not profitable on KNL / SKX
2533 // Vector-4 of gather/scatter instruction does not exist on KNL.
2534 // We can extend it to 8 elements, but zeroing upper bits of
2535 // the mask vector will add more instructions. Right now we give the scalar
2536 // cost of vector-4 for KNL. TODO: Check, maybe the gather/scatter instruction
2537 // is better in the VariableMask case.
2538 if (ST->hasAVX512() && (VF == 2 || (VF == 4 && !ST->hasVLX())))
2539 Scalarize = true;
2540
2541 if (Scalarize)
2542 return getGSScalarCost(Opcode, SrcVTy, VariableMask, Alignment,
2543 AddressSpace);
2544
2545 return getGSVectorCost(Opcode, SrcVTy, Ptr, Alignment, AddressSpace);
2546}
2547
2548bool X86TTIImpl::isLSRCostLess(TargetTransformInfo::LSRCost &C1,
2549 TargetTransformInfo::LSRCost &C2) {
2550 // X86 specific here are "instruction number 1st priority".
2551 return std::tie(C1.Insns, C1.NumRegs, C1.AddRecCost,
2552 C1.NumIVMuls, C1.NumBaseAdds,
2553 C1.ScaleCost, C1.ImmCost, C1.SetupCost) <
2554 std::tie(C2.Insns, C2.NumRegs, C2.AddRecCost,
2555 C2.NumIVMuls, C2.NumBaseAdds,
2556 C2.ScaleCost, C2.ImmCost, C2.SetupCost);
2557}
2558
2559bool X86TTIImpl::canMacroFuseCmp() {
2560 return ST->hasMacroFusion();
2561}
2562
2563bool X86TTIImpl::isLegalMaskedLoad(Type *DataTy) {
2564 // The backend can't handle a single element vector.
2565 if (isa<VectorType>(DataTy) && DataTy->getVectorNumElements() == 1)
2566 return false;
2567 Type *ScalarTy = DataTy->getScalarType();
2568 int DataWidth = isa<PointerType>(ScalarTy) ?
2569 DL.getPointerSizeInBits() : ScalarTy->getPrimitiveSizeInBits();
2570
2571 return ((DataWidth == 32 || DataWidth == 64) && ST->hasAVX()) ||
2572 ((DataWidth == 8 || DataWidth == 16) && ST->hasBWI());
2573}
2574
2575bool X86TTIImpl::isLegalMaskedStore(Type *DataType) {
2576 return isLegalMaskedLoad(DataType);
2577}
2578
2579bool X86TTIImpl::isLegalMaskedGather(Type *DataTy) {
2580 // This function is called now in two cases: from the Loop Vectorizer
2581 // and from the Scalarizer.
2582 // When the Loop Vectorizer asks about legality of the feature,
2583 // the vectorization factor is not calculated yet. The Loop Vectorizer
2584 // sends a scalar type and the decision is based on the width of the
2585 // scalar element.
2586 // Later on, the cost model will estimate usage this intrinsic based on
2587 // the vector type.
2588 // The Scalarizer asks again about legality. It sends a vector type.
2589 // In this case we can reject non-power-of-2 vectors.
2590 // We also reject single element vectors as the type legalizer can't
2591 // scalarize it.
2592 if (isa<VectorType>(DataTy)) {
2593 unsigned NumElts = DataTy->getVectorNumElements();
2594 if (NumElts == 1 || !isPowerOf2_32(NumElts))
2595 return false;
2596 }
2597 Type *ScalarTy = DataTy->getScalarType();
2598 int DataWidth = isa<PointerType>(ScalarTy) ?
2599 DL.getPointerSizeInBits() : ScalarTy->getPrimitiveSizeInBits();
2600
2601 // Some CPUs have better gather performance than others.
2602 // TODO: Remove the explicit ST->hasAVX512()?, That would mean we would only
2603 // enable gather with a -march.
2604 return (DataWidth == 32 || DataWidth == 64) &&
2605 (ST->hasAVX512() || (ST->hasFastGather() && ST->hasAVX2()));
2606}
2607
2608bool X86TTIImpl::isLegalMaskedScatter(Type *DataType) {
2609 // AVX2 doesn't support scatter
2610 if (!ST->hasAVX512())
2611 return false;
2612 return isLegalMaskedGather(DataType);
2613}
2614
2615bool X86TTIImpl::hasDivRemOp(Type *DataType, bool IsSigned) {
2616 EVT VT = TLI->getValueType(DL, DataType);
2617 return TLI->isOperationLegal(IsSigned ? ISD::SDIVREM : ISD::UDIVREM, VT);
2618}
2619
2620bool X86TTIImpl::isFCmpOrdCheaperThanFCmpZero(Type *Ty) {
2621 return false;
2622}
2623
2624bool X86TTIImpl::areInlineCompatible(const Function *Caller,
2625 const Function *Callee) const {
2626 const TargetMachine &TM = getTLI()->getTargetMachine();
2627
2628 // Work this as a subsetting of subtarget features.
2629 const FeatureBitset &CallerBits =
2630 TM.getSubtargetImpl(*Caller)->getFeatureBits();
2631 const FeatureBitset &CalleeBits =
2632 TM.getSubtargetImpl(*Callee)->getFeatureBits();
2633
2634 // FIXME: This is likely too limiting as it will include subtarget features
2635 // that we might not care about for inlining, but it is conservatively
2636 // correct.
2637 return (CallerBits & CalleeBits) == CalleeBits;
2638}
2639
2640const X86TTIImpl::TTI::MemCmpExpansionOptions *
2641X86TTIImpl::enableMemCmpExpansion(bool IsZeroCmp) const {
2642 // Only enable vector loads for equality comparison.
2643 // Right now the vector version is not as fast, see #33329.
2644 static const auto ThreeWayOptions = [this]() {
2645 TTI::MemCmpExpansionOptions Options;
2646 if (ST->is64Bit()) {
2647 Options.LoadSizes.push_back(8);
2648 }
2649 Options.LoadSizes.push_back(4);
2650 Options.LoadSizes.push_back(2);
2651 Options.LoadSizes.push_back(1);
2652 return Options;
2653 }();
2654 static const auto EqZeroOptions = [this]() {
2655 TTI::MemCmpExpansionOptions Options;
2656 // TODO: enable AVX512 when the DAG is ready.
2657 // if (ST->hasAVX512()) Options.LoadSizes.push_back(64);
2658 if (ST->hasAVX2()) Options.LoadSizes.push_back(32);
2659 if (ST->hasSSE2()) Options.LoadSizes.push_back(16);
2660 if (ST->is64Bit()) {
2661 Options.LoadSizes.push_back(8);
2662 }
2663 Options.LoadSizes.push_back(4);
2664 Options.LoadSizes.push_back(2);
2665 Options.LoadSizes.push_back(1);
2666 return Options;
2667 }();
2668 return IsZeroCmp ? &EqZeroOptions : &ThreeWayOptions;
2669}
2670
2671bool X86TTIImpl::enableInterleavedAccessVectorization() {
2672 // TODO: We expect this to be beneficial regardless of arch,
2673 // but there are currently some unexplained performance artifacts on Atom.
2674 // As a temporary solution, disable on Atom.
2675 return !(ST->isAtom());
2676}
2677
2678// Get estimation for interleaved load/store operations for AVX2.
2679// \p Factor is the interleaved-access factor (stride) - number of
2680// (interleaved) elements in the group.
2681// \p Indices contains the indices for a strided load: when the
2682// interleaved load has gaps they indicate which elements are used.
2683// If Indices is empty (or if the number of indices is equal to the size
2684// of the interleaved-access as given in \p Factor) the access has no gaps.
2685//
2686// As opposed to AVX-512, AVX2 does not have generic shuffles that allow
2687// computing the cost using a generic formula as a function of generic
2688// shuffles. We therefore use a lookup table instead, filled according to
2689// the instruction sequences that codegen currently generates.
2690int X86TTIImpl::getInterleavedMemoryOpCostAVX2(unsigned Opcode, Type *VecTy,
2691 unsigned Factor,
2692 ArrayRef<unsigned> Indices,
2693 unsigned Alignment,
2694 unsigned AddressSpace) {
2695
2696 // We currently Support only fully-interleaved groups, with no gaps.
2697 // TODO: Support also strided loads (interleaved-groups with gaps).
2698 if (Indices.size() && Indices.size() != Factor)
2699 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices,
2700 Alignment, AddressSpace);
2701
2702 // VecTy for interleave memop is <VF*Factor x Elt>.
2703 // So, for VF=4, Interleave Factor = 3, Element type = i32 we have
2704 // VecTy = <12 x i32>.
2705 MVT LegalVT = getTLI()->getTypeLegalizationCost(DL, VecTy).second;
2706
2707 // This function can be called with VecTy=<6xi128>, Factor=3, in which case
2708 // the VF=2, while v2i128 is an unsupported MVT vector type
2709 // (see MachineValueType.h::getVectorVT()).
2710 if (!LegalVT.isVector())
2711 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices,
2712 Alignment, AddressSpace);
2713
2714 unsigned VF = VecTy->getVectorNumElements() / Factor;
2715 Type *ScalarTy = VecTy->getVectorElementType();
2716
2717 // Calculate the number of memory operations (NumOfMemOps), required
2718 // for load/store the VecTy.
2719 unsigned VecTySize = DL.getTypeStoreSize(VecTy);
2720 unsigned LegalVTSize = LegalVT.getStoreSize();
2721 unsigned NumOfMemOps = (VecTySize + LegalVTSize - 1) / LegalVTSize;
2722
2723 // Get the cost of one memory operation.
2724 Type *SingleMemOpTy = VectorType::get(VecTy->getVectorElementType(),
2725 LegalVT.getVectorNumElements());
2726 unsigned MemOpCost =
2727 getMemoryOpCost(Opcode, SingleMemOpTy, Alignment, AddressSpace);
2728
2729 VectorType *VT = VectorType::get(ScalarTy, VF);
2730 EVT ETy = TLI->getValueType(DL, VT);
2731 if (!ETy.isSimple())
2732 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices,
2733 Alignment, AddressSpace);
2734
2735 // TODO: Complete for other data-types and strides.
2736 // Each combination of Stride, ElementTy and VF results in a different
2737 // sequence; The cost tables are therefore accessed with:
2738 // Factor (stride) and VectorType=VFxElemType.
2739 // The Cost accounts only for the shuffle sequence;
2740 // The cost of the loads/stores is accounted for separately.
2741 //
2742 static const CostTblEntry AVX2InterleavedLoadTbl[] = {
2743 { 2, MVT::v4i64, 6 }, //(load 8i64 and) deinterleave into 2 x 4i64
2744 { 2, MVT::v4f64, 6 }, //(load 8f64 and) deinterleave into 2 x 4f64
2745
2746 { 3, MVT::v2i8, 10 }, //(load 6i8 and) deinterleave into 3 x 2i8
2747 { 3, MVT::v4i8, 4 }, //(load 12i8 and) deinterleave into 3 x 4i8
2748 { 3, MVT::v8i8, 9 }, //(load 24i8 and) deinterleave into 3 x 8i8
2749 { 3, MVT::v16i8, 11}, //(load 48i8 and) deinterleave into 3 x 16i8
2750 { 3, MVT::v32i8, 13}, //(load 96i8 and) deinterleave into 3 x 32i8
2751 { 3, MVT::v8f32, 17 }, //(load 24f32 and)deinterleave into 3 x 8f32
2752
2753 { 4, MVT::v2i8, 12 }, //(load 8i8 and) deinterleave into 4 x 2i8
2754 { 4, MVT::v4i8, 4 }, //(load 16i8 and) deinterleave into 4 x 4i8
2755 { 4, MVT::v8i8, 20 }, //(load 32i8 and) deinterleave into 4 x 8i8
2756 { 4, MVT::v16i8, 39 }, //(load 64i8 and) deinterleave into 4 x 16i8
2757 { 4, MVT::v32i8, 80 }, //(load 128i8 and) deinterleave into 4 x 32i8
2758
2759 { 8, MVT::v8f32, 40 } //(load 64f32 and)deinterleave into 8 x 8f32
2760 };
2761
2762 static const CostTblEntry AVX2InterleavedStoreTbl[] = {
2763 { 2, MVT::v4i64, 6 }, //interleave into 2 x 4i64 into 8i64 (and store)
2764 { 2, MVT::v4f64, 6 }, //interleave into 2 x 4f64 into 8f64 (and store)
2765
2766 { 3, MVT::v2i8, 7 }, //interleave 3 x 2i8 into 6i8 (and store)
2767 { 3, MVT::v4i8, 8 }, //interleave 3 x 4i8 into 12i8 (and store)
2768 { 3, MVT::v8i8, 11 }, //interleave 3 x 8i8 into 24i8 (and store)
2769 { 3, MVT::v16i8, 11 }, //interleave 3 x 16i8 into 48i8 (and store)
2770 { 3, MVT::v32i8, 13 }, //interleave 3 x 32i8 into 96i8 (and store)
2771
2772 { 4, MVT::v2i8, 12 }, //interleave 4 x 2i8 into 8i8 (and store)
2773 { 4, MVT::v4i8, 9 }, //interleave 4 x 4i8 into 16i8 (and store)
2774 { 4, MVT::v8i8, 10 }, //interleave 4 x 8i8 into 32i8 (and store)
2775 { 4, MVT::v16i8, 10 }, //interleave 4 x 16i8 into 64i8 (and store)
2776 { 4, MVT::v32i8, 12 } //interleave 4 x 32i8 into 128i8 (and store)
2777 };
2778
2779 if (Opcode == Instruction::Load) {
2780 if (const auto *Entry =
2781 CostTableLookup(AVX2InterleavedLoadTbl, Factor, ETy.getSimpleVT()))
2782 return NumOfMemOps * MemOpCost + Entry->Cost;
2783 } else {
2784 assert(Opcode == Instruction::Store &&(static_cast <bool> (Opcode == Instruction::Store &&
"Expected Store Instruction at this point") ? void (0) : __assert_fail
("Opcode == Instruction::Store && \"Expected Store Instruction at this point\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86TargetTransformInfo.cpp"
, 2785, __extension__ __PRETTY_FUNCTION__))
2785 "Expected Store Instruction at this point")(static_cast <bool> (Opcode == Instruction::Store &&
"Expected Store Instruction at this point") ? void (0) : __assert_fail
("Opcode == Instruction::Store && \"Expected Store Instruction at this point\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86TargetTransformInfo.cpp"
, 2785, __extension__ __PRETTY_FUNCTION__))
;
2786 if (const auto *Entry =
2787 CostTableLookup(AVX2InterleavedStoreTbl, Factor, ETy.getSimpleVT()))
2788 return NumOfMemOps * MemOpCost + Entry->Cost;
2789 }
2790
2791 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices,
2792 Alignment, AddressSpace);
2793}
2794
2795// Get estimation for interleaved load/store operations and strided load.
2796// \p Indices contains indices for strided load.
2797// \p Factor - the factor of interleaving.
2798// AVX-512 provides 3-src shuffles that significantly reduces the cost.
2799int X86TTIImpl::getInterleavedMemoryOpCostAVX512(unsigned Opcode, Type *VecTy,
2800 unsigned Factor,
2801 ArrayRef<unsigned> Indices,
2802 unsigned Alignment,
2803 unsigned AddressSpace) {
2804
2805 // VecTy for interleave memop is <VF*Factor x Elt>.
2806 // So, for VF=4, Interleave Factor = 3, Element type = i32 we have
2807 // VecTy = <12 x i32>.
2808
2809 // Calculate the number of memory operations (NumOfMemOps), required
2810 // for load/store the VecTy.
2811 MVT LegalVT = getTLI()->getTypeLegalizationCost(DL, VecTy).second;
2812 unsigned VecTySize = DL.getTypeStoreSize(VecTy);
2813 unsigned LegalVTSize = LegalVT.getStoreSize();
2814 unsigned NumOfMemOps = (VecTySize + LegalVTSize - 1) / LegalVTSize;
2815
2816 // Get the cost of one memory operation.
2817 Type *SingleMemOpTy = VectorType::get(VecTy->getVectorElementType(),
2818 LegalVT.getVectorNumElements());
2819 unsigned MemOpCost =
2820 getMemoryOpCost(Opcode, SingleMemOpTy, Alignment, AddressSpace);
2821
2822 unsigned VF = VecTy->getVectorNumElements() / Factor;
2823 MVT VT = MVT::getVectorVT(MVT::getVT(VecTy->getScalarType()), VF);
2824
2825 if (Opcode == Instruction::Load) {
2826 // The tables (AVX512InterleavedLoadTbl and AVX512InterleavedStoreTbl)
2827 // contain the cost of the optimized shuffle sequence that the
2828 // X86InterleavedAccess pass will generate.
2829 // The cost of loads and stores are computed separately from the table.
2830
2831 // X86InterleavedAccess support only the following interleaved-access group.
2832 static const CostTblEntry AVX512InterleavedLoadTbl[] = {
2833 {3, MVT::v16i8, 12}, //(load 48i8 and) deinterleave into 3 x 16i8
2834 {3, MVT::v32i8, 14}, //(load 96i8 and) deinterleave into 3 x 32i8
2835 {3, MVT::v64i8, 22}, //(load 96i8 and) deinterleave into 3 x 32i8
2836 };
2837
2838 if (const auto *Entry =
2839 CostTableLookup(AVX512InterleavedLoadTbl, Factor, VT))
2840 return NumOfMemOps * MemOpCost + Entry->Cost;
2841 //If an entry does not exist, fallback to the default implementation.
2842
2843 // Kind of shuffle depends on number of loaded values.
2844 // If we load the entire data in one register, we can use a 1-src shuffle.
2845 // Otherwise, we'll merge 2 sources in each operation.
2846 TTI::ShuffleKind ShuffleKind =
2847 (NumOfMemOps > 1) ? TTI::SK_PermuteTwoSrc : TTI::SK_PermuteSingleSrc;
2848
2849 unsigned ShuffleCost =
2850 getShuffleCost(ShuffleKind, SingleMemOpTy, 0, nullptr);
2851
2852 unsigned NumOfLoadsInInterleaveGrp =
2853 Indices.size() ? Indices.size() : Factor;
2854 Type *ResultTy = VectorType::get(VecTy->getVectorElementType(),
2855 VecTy->getVectorNumElements() / Factor);
2856 unsigned NumOfResults =
2857 getTLI()->getTypeLegalizationCost(DL, ResultTy).first *
2858 NumOfLoadsInInterleaveGrp;
2859
2860 // About a half of the loads may be folded in shuffles when we have only
2861 // one result. If we have more than one result, we do not fold loads at all.
2862 unsigned NumOfUnfoldedLoads =
2863 NumOfResults > 1 ? NumOfMemOps : NumOfMemOps / 2;
2864
2865 // Get a number of shuffle operations per result.
2866 unsigned NumOfShufflesPerResult =
2867 std::max((unsigned)1, (unsigned)(NumOfMemOps - 1));
2868
2869 // The SK_MergeTwoSrc shuffle clobbers one of src operands.
2870 // When we have more than one destination, we need additional instructions
2871 // to keep sources.
2872 unsigned NumOfMoves = 0;
2873 if (NumOfResults > 1 && ShuffleKind == TTI::SK_PermuteTwoSrc)
2874 NumOfMoves = NumOfResults * NumOfShufflesPerResult / 2;
2875
2876 int Cost = NumOfResults * NumOfShufflesPerResult * ShuffleCost +
2877 NumOfUnfoldedLoads * MemOpCost + NumOfMoves;
2878
2879 return Cost;
2880 }
2881
2882 // Store.
2883 assert(Opcode == Instruction::Store &&(static_cast <bool> (Opcode == Instruction::Store &&
"Expected Store Instruction at this point") ? void (0) : __assert_fail
("Opcode == Instruction::Store && \"Expected Store Instruction at this point\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86TargetTransformInfo.cpp"
, 2884, __extension__ __PRETTY_FUNCTION__))
2884 "Expected Store Instruction at this point")(static_cast <bool> (Opcode == Instruction::Store &&
"Expected Store Instruction at this point") ? void (0) : __assert_fail
("Opcode == Instruction::Store && \"Expected Store Instruction at this point\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/X86/X86TargetTransformInfo.cpp"
, 2884, __extension__ __PRETTY_FUNCTION__))
;
2885 // X86InterleavedAccess support only the following interleaved-access group.
2886 static const CostTblEntry AVX512InterleavedStoreTbl[] = {
2887 {3, MVT::v16i8, 12}, // interleave 3 x 16i8 into 48i8 (and store)
2888 {3, MVT::v32i8, 14}, // interleave 3 x 32i8 into 96i8 (and store)
2889 {3, MVT::v64i8, 26}, // interleave 3 x 64i8 into 96i8 (and store)
2890
2891 {4, MVT::v8i8, 10}, // interleave 4 x 8i8 into 32i8 (and store)
2892 {4, MVT::v16i8, 11}, // interleave 4 x 16i8 into 64i8 (and store)
2893 {4, MVT::v32i8, 14}, // interleave 4 x 32i8 into 128i8 (and store)
2894 {4, MVT::v64i8, 24} // interleave 4 x 32i8 into 256i8 (and store)
2895 };
2896
2897 if (const auto *Entry =
2898 CostTableLookup(AVX512InterleavedStoreTbl, Factor, VT))
2899 return NumOfMemOps * MemOpCost + Entry->Cost;
2900 //If an entry does not exist, fallback to the default implementation.
2901
2902 // There is no strided stores meanwhile. And store can't be folded in
2903 // shuffle.
2904 unsigned NumOfSources = Factor; // The number of values to be merged.
2905 unsigned ShuffleCost =
2906 getShuffleCost(TTI::SK_PermuteTwoSrc, SingleMemOpTy, 0, nullptr);
2907 unsigned NumOfShufflesPerStore = NumOfSources - 1;
2908
2909 // The SK_MergeTwoSrc shuffle clobbers one of src operands.
2910 // We need additional instructions to keep sources.
2911 unsigned NumOfMoves = NumOfMemOps * NumOfShufflesPerStore / 2;
2912 int Cost = NumOfMemOps * (MemOpCost + NumOfShufflesPerStore * ShuffleCost) +
2913 NumOfMoves;
2914 return Cost;
2915}
2916
2917int X86TTIImpl::getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy,
2918 unsigned Factor,
2919 ArrayRef<unsigned> Indices,
2920 unsigned Alignment,
2921 unsigned AddressSpace) {
2922 auto isSupportedOnAVX512 = [](Type *VecTy, bool HasBW) {
2923 Type *EltTy = VecTy->getVectorElementType();
2924 if (EltTy->isFloatTy() || EltTy->isDoubleTy() || EltTy->isIntegerTy(64) ||
2925 EltTy->isIntegerTy(32) || EltTy->isPointerTy())
2926 return true;
2927 if (EltTy->isIntegerTy(16) || EltTy->isIntegerTy(8))
2928 return HasBW;
2929 return false;
2930 };
2931 if (ST->hasAVX512() && isSupportedOnAVX512(VecTy, ST->hasBWI()))
2932 return getInterleavedMemoryOpCostAVX512(Opcode, VecTy, Factor, Indices,
2933 Alignment, AddressSpace);
2934 if (ST->hasAVX2())
2935 return getInterleavedMemoryOpCostAVX2(Opcode, VecTy, Factor, Indices,
2936 Alignment, AddressSpace);
2937
2938 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices,
2939 Alignment, AddressSpace);
2940}

/build/llvm-toolchain-snapshot-7~svn329677/include/llvm/Analysis/TargetTransformInfoImpl.h

1//===- TargetTransformInfoImpl.h --------------------------------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9/// \file
10/// This file provides helpers for the implementation of
11/// a TargetTransformInfo-conforming class.
12///
13//===----------------------------------------------------------------------===//
14
15#ifndef LLVM_ANALYSIS_TARGETTRANSFORMINFOIMPL_H
16#define LLVM_ANALYSIS_TARGETTRANSFORMINFOIMPL_H
17
18#include "llvm/Analysis/ScalarEvolutionExpressions.h"
19#include "llvm/Analysis/TargetTransformInfo.h"
20#include "llvm/Analysis/VectorUtils.h"
21#include "llvm/IR/CallSite.h"
22#include "llvm/IR/DataLayout.h"
23#include "llvm/IR/Function.h"
24#include "llvm/IR/GetElementPtrTypeIterator.h"
25#include "llvm/IR/Operator.h"
26#include "llvm/IR/Type.h"
27
28namespace llvm {
29
30/// \brief Base class for use as a mix-in that aids implementing
31/// a TargetTransformInfo-compatible class.
32class TargetTransformInfoImplBase {
33protected:
34 typedef TargetTransformInfo TTI;
35
36 const DataLayout &DL;
37
38 explicit TargetTransformInfoImplBase(const DataLayout &DL) : DL(DL) {}
39
40public:
41 // Provide value semantics. MSVC requires that we spell all of these out.
42 TargetTransformInfoImplBase(const TargetTransformInfoImplBase &Arg)
43 : DL(Arg.DL) {}
44 TargetTransformInfoImplBase(TargetTransformInfoImplBase &&Arg) : DL(Arg.DL) {}
45
46 const DataLayout &getDataLayout() const { return DL; }
47
48 unsigned getOperationCost(unsigned Opcode, Type *Ty, Type *OpTy) {
49 switch (Opcode) {
50 default:
51 // By default, just classify everything as 'basic'.
52 return TTI::TCC_Basic;
53
54 case Instruction::GetElementPtr:
55 llvm_unreachable("Use getGEPCost for GEP operations!")::llvm::llvm_unreachable_internal("Use getGEPCost for GEP operations!"
, "/build/llvm-toolchain-snapshot-7~svn329677/include/llvm/Analysis/TargetTransformInfoImpl.h"
, 55)
;
56
57 case Instruction::BitCast:
58 assert(OpTy && "Cast instructions must provide the operand type")(static_cast <bool> (OpTy && "Cast instructions must provide the operand type"
) ? void (0) : __assert_fail ("OpTy && \"Cast instructions must provide the operand type\""
, "/build/llvm-toolchain-snapshot-7~svn329677/include/llvm/Analysis/TargetTransformInfoImpl.h"
, 58, __extension__ __PRETTY_FUNCTION__))
;
59 if (Ty == OpTy || (Ty->isPointerTy() && OpTy->isPointerTy()))
60 // Identity and pointer-to-pointer casts are free.
61 return TTI::TCC_Free;
62
63 // Otherwise, the default basic cost is used.
64 return TTI::TCC_Basic;
65
66 case Instruction::FDiv:
67 case Instruction::FRem:
68 case Instruction::SDiv:
69 case Instruction::SRem:
70 case Instruction::UDiv:
71 case Instruction::URem:
72 return TTI::TCC_Expensive;
73
74 case Instruction::IntToPtr: {
75 // An inttoptr cast is free so long as the input is a legal integer type
76 // which doesn't contain values outside the range of a pointer.
77 unsigned OpSize = OpTy->getScalarSizeInBits();
78 if (DL.isLegalInteger(OpSize) &&
79 OpSize <= DL.getPointerTypeSizeInBits(Ty))
80 return TTI::TCC_Free;
81
82 // Otherwise it's not a no-op.
83 return TTI::TCC_Basic;
84 }
85 case Instruction::PtrToInt: {
86 // A ptrtoint cast is free so long as the result is large enough to store
87 // the pointer, and a legal integer type.
88 unsigned DestSize = Ty->getScalarSizeInBits();
89 if (DL.isLegalInteger(DestSize) &&
90 DestSize >= DL.getPointerTypeSizeInBits(OpTy))
91 return TTI::TCC_Free;
92
93 // Otherwise it's not a no-op.
94 return TTI::TCC_Basic;
95 }
96 case Instruction::Trunc:
97 // trunc to a native type is free (assuming the target has compare and
98 // shift-right of the same width).
99 if (DL.isLegalInteger(DL.getTypeSizeInBits(Ty)))
100 return TTI::TCC_Free;
101
102 return TTI::TCC_Basic;
103 }
104 }
105
106 int getGEPCost(Type *PointeeType, const Value *Ptr,
107 ArrayRef<const Value *> Operands) {
108 // In the basic model, we just assume that all-constant GEPs will be folded
109 // into their uses via addressing modes.
110 for (unsigned Idx = 0, Size = Operands.size(); Idx != Size; ++Idx)
111 if (!isa<Constant>(Operands[Idx]))
112 return TTI::TCC_Basic;
113
114 return TTI::TCC_Free;
115 }
116
117 unsigned getEstimatedNumberOfCaseClusters(const SwitchInst &SI,
118 unsigned &JTSize) {
119 JTSize = 0;
120 return SI.getNumCases();
121 }
122
123 int getExtCost(const Instruction *I, const Value *Src) {
124 return TTI::TCC_Basic;
125 }
126
127 unsigned getCallCost(FunctionType *FTy, int NumArgs) {
128 assert(FTy && "FunctionType must be provided to this routine.")(static_cast <bool> (FTy && "FunctionType must be provided to this routine."
) ? void (0) : __assert_fail ("FTy && \"FunctionType must be provided to this routine.\""
, "/build/llvm-toolchain-snapshot-7~svn329677/include/llvm/Analysis/TargetTransformInfoImpl.h"
, 128, __extension__ __PRETTY_FUNCTION__))
;
129
130 // The target-independent implementation just measures the size of the
131 // function by approximating that each argument will take on average one
132 // instruction to prepare.
133
134 if (NumArgs < 0)
135 // Set the argument number to the number of explicit arguments in the
136 // function.
137 NumArgs = FTy->getNumParams();
138
139 return TTI::TCC_Basic * (NumArgs + 1);
140 }
141
142 unsigned getInliningThresholdMultiplier() { return 1; }
143
144 unsigned getIntrinsicCost(Intrinsic::ID IID, Type *RetTy,
145 ArrayRef<Type *> ParamTys) {
146 switch (IID) {
147 default:
148 // Intrinsics rarely (if ever) have normal argument setup constraints.
149 // Model them as having a basic instruction cost.
150 // FIXME: This is wrong for libc intrinsics.
151 return TTI::TCC_Basic;
152
153 case Intrinsic::annotation:
154 case Intrinsic::assume:
155 case Intrinsic::sideeffect:
156 case Intrinsic::dbg_declare:
157 case Intrinsic::dbg_value:
158 case Intrinsic::invariant_start:
159 case Intrinsic::invariant_end:
160 case Intrinsic::lifetime_start:
161 case Intrinsic::lifetime_end:
162 case Intrinsic::objectsize:
163 case Intrinsic::ptr_annotation:
164 case Intrinsic::var_annotation:
165 case Intrinsic::experimental_gc_result:
166 case Intrinsic::experimental_gc_relocate:
167 case Intrinsic::coro_alloc:
168 case Intrinsic::coro_begin:
169 case Intrinsic::coro_free:
170 case Intrinsic::coro_end:
171 case Intrinsic::coro_frame:
172 case Intrinsic::coro_size:
173 case Intrinsic::coro_suspend:
174 case Intrinsic::coro_param:
175 case Intrinsic::coro_subfn_addr:
176 // These intrinsics don't actually represent code after lowering.
177 return TTI::TCC_Free;
178 }
179 }
180
181 bool hasBranchDivergence() { return false; }
182
183 bool isSourceOfDivergence(const Value *V) { return false; }
184
185 bool isAlwaysUniform(const Value *V) { return false; }
186
187 unsigned getFlatAddressSpace () {
188 return -1;
189 }
190
191 bool isLoweredToCall(const Function *F) {
192 assert(F && "A concrete function must be provided to this routine.")(static_cast <bool> (F && "A concrete function must be provided to this routine."
) ? void (0) : __assert_fail ("F && \"A concrete function must be provided to this routine.\""
, "/build/llvm-toolchain-snapshot-7~svn329677/include/llvm/Analysis/TargetTransformInfoImpl.h"
, 192, __extension__ __PRETTY_FUNCTION__))
;
193
194 // FIXME: These should almost certainly not be handled here, and instead
195 // handled with the help of TLI or the target itself. This was largely
196 // ported from existing analysis heuristics here so that such refactorings
197 // can take place in the future.
198
199 if (F->isIntrinsic())
200 return false;
201
202 if (F->hasLocalLinkage() || !F->hasName())
203 return true;
204
205 StringRef Name = F->getName();
206
207 // These will all likely lower to a single selection DAG node.
208 if (Name == "copysign" || Name == "copysignf" || Name == "copysignl" ||
209 Name == "fabs" || Name == "fabsf" || Name == "fabsl" || Name == "sin" ||
210 Name == "fmin" || Name == "fminf" || Name == "fminl" ||
211 Name == "fmax" || Name == "fmaxf" || Name == "fmaxl" ||
212 Name == "sinf" || Name == "sinl" || Name == "cos" || Name == "cosf" ||
213 Name == "cosl" || Name == "sqrt" || Name == "sqrtf" || Name == "sqrtl")
214 return false;
215
216 // These are all likely to be optimized into something smaller.
217 if (Name == "pow" || Name == "powf" || Name == "powl" || Name == "exp2" ||
218 Name == "exp2l" || Name == "exp2f" || Name == "floor" ||
219 Name == "floorf" || Name == "ceil" || Name == "round" ||
220 Name == "ffs" || Name == "ffsl" || Name == "abs" || Name == "labs" ||
221 Name == "llabs")
222 return false;
223
224 return true;
225 }
226
227 void getUnrollingPreferences(Loop *, ScalarEvolution &,
228 TTI::UnrollingPreferences &) {}
229
230 bool isLegalAddImmediate(int64_t Imm) { return false; }
231
232 bool isLegalICmpImmediate(int64_t Imm) { return false; }
233
234 bool isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset,
235 bool HasBaseReg, int64_t Scale,
236 unsigned AddrSpace, Instruction *I = nullptr) {
237 // Guess that only reg and reg+reg addressing is allowed. This heuristic is
238 // taken from the implementation of LSR.
239 return !BaseGV && BaseOffset == 0 && (Scale == 0 || Scale == 1);
240 }
241
242 bool isLSRCostLess(TTI::LSRCost &C1, TTI::LSRCost &C2) {
243 return std::tie(C1.NumRegs, C1.AddRecCost, C1.NumIVMuls, C1.NumBaseAdds,
244 C1.ScaleCost, C1.ImmCost, C1.SetupCost) <
245 std::tie(C2.NumRegs, C2.AddRecCost, C2.NumIVMuls, C2.NumBaseAdds,
246 C2.ScaleCost, C2.ImmCost, C2.SetupCost);
247 }
248
249 bool canMacroFuseCmp() { return false; }
250
251 bool shouldFavorPostInc() const { return false; }
252
253 bool isLegalMaskedStore(Type *DataType) { return false; }
254
255 bool isLegalMaskedLoad(Type *DataType) { return false; }
256
257 bool isLegalMaskedScatter(Type *DataType) { return false; }
258
259 bool isLegalMaskedGather(Type *DataType) { return false; }
260
261 bool hasDivRemOp(Type *DataType, bool IsSigned) { return false; }
262
263 bool hasVolatileVariant(Instruction *I, unsigned AddrSpace) { return false; }
264
265 bool prefersVectorizedAddressing() { return true; }
266
267 int getScalingFactorCost(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset,
268 bool HasBaseReg, int64_t Scale, unsigned AddrSpace) {
269 // Guess that all legal addressing mode are free.
270 if (isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg,
271 Scale, AddrSpace))
272 return 0;
273 return -1;
274 }
275
276 bool LSRWithInstrQueries() { return false; }
277
278 bool isTruncateFree(Type *Ty1, Type *Ty2) { return false; }
279
280 bool isProfitableToHoist(Instruction *I) { return true; }
281
282 bool useAA() { return false; }
283
284 bool isTypeLegal(Type *Ty) { return false; }
285
286 unsigned getJumpBufAlignment() { return 0; }
287
288 unsigned getJumpBufSize() { return 0; }
289
290 bool shouldBuildLookupTables() { return true; }
291 bool shouldBuildLookupTablesForConstant(Constant *C) { return true; }
292
293 bool useColdCCForColdCall(Function &F) { return false; }
294
295 unsigned getScalarizationOverhead(Type *Ty, bool Insert, bool Extract) {
296 return 0;
297 }
298
299 unsigned getOperandsScalarizationOverhead(ArrayRef<const Value *> Args,
300 unsigned VF) { return 0; }
301
302 bool supportsEfficientVectorElementLoadStore() { return false; }
303
304 bool enableAggressiveInterleaving(bool LoopHasReductions) { return false; }
305
306 const TTI::MemCmpExpansionOptions *enableMemCmpExpansion(
307 bool IsZeroCmp) const {
308 return nullptr;
309 }
310
311 bool enableInterleavedAccessVectorization() { return false; }
312
313 bool isFPVectorizationPotentiallyUnsafe() { return false; }
314
315 bool allowsMisalignedMemoryAccesses(LLVMContext &Context,
316 unsigned BitWidth,
317 unsigned AddressSpace,
318 unsigned Alignment,
319 bool *Fast) { return false; }
320
321 TTI::PopcntSupportKind getPopcntSupport(unsigned IntTyWidthInBit) {
322 return TTI::PSK_Software;
323 }
324
325 bool haveFastSqrt(Type *Ty) { return false; }
326
327 bool isFCmpOrdCheaperThanFCmpZero(Type *Ty) { return true; }
328
329 unsigned getFPOpCost(Type *Ty) { return TargetTransformInfo::TCC_Basic; }
330
331 int getIntImmCodeSizeCost(unsigned Opcode, unsigned Idx, const APInt &Imm,
332 Type *Ty) {
333 return 0;
334 }
335
336 unsigned getIntImmCost(const APInt &Imm, Type *Ty) { return TTI::TCC_Basic; }
337
338 unsigned getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm,
339 Type *Ty) {
340 return TTI::TCC_Free;
341 }
342
343 unsigned getIntImmCost(Intrinsic::ID IID, unsigned Idx, const APInt &Imm,
344 Type *Ty) {
345 return TTI::TCC_Free;
346 }
347
348 unsigned getNumberOfRegisters(bool Vector) { return 8; }
349
350 unsigned getRegisterBitWidth(bool Vector) const { return 32; }
351
352 unsigned getMinVectorRegisterBitWidth() { return 128; }
353
354 bool shouldMaximizeVectorBandwidth(bool OptSize) const { return false; }
355
356 bool
357 shouldConsiderAddressTypePromotion(const Instruction &I,
358 bool &AllowPromotionWithoutCommonHeader) {
359 AllowPromotionWithoutCommonHeader = false;
360 return false;
361 }
362
363 unsigned getCacheLineSize() { return 0; }
364
365 llvm::Optional<unsigned> getCacheSize(TargetTransformInfo::CacheLevel Level) {
366 switch (Level) {
367 case TargetTransformInfo::CacheLevel::L1D:
368 LLVM_FALLTHROUGH[[clang::fallthrough]];
369 case TargetTransformInfo::CacheLevel::L2D:
370 return llvm::Optional<unsigned>();
371 }
372
373 llvm_unreachable("Unknown TargetTransformInfo::CacheLevel")::llvm::llvm_unreachable_internal("Unknown TargetTransformInfo::CacheLevel"
, "/build/llvm-toolchain-snapshot-7~svn329677/include/llvm/Analysis/TargetTransformInfoImpl.h"
, 373)
;
374 }
375
376 llvm::Optional<unsigned> getCacheAssociativity(
377 TargetTransformInfo::CacheLevel Level) {
378 switch (Level) {
379 case TargetTransformInfo::CacheLevel::L1D:
380 LLVM_FALLTHROUGH[[clang::fallthrough]];
381 case TargetTransformInfo::CacheLevel::L2D:
382 return llvm::Optional<unsigned>();
383 }
384
385 llvm_unreachable("Unknown TargetTransformInfo::CacheLevel")::llvm::llvm_unreachable_internal("Unknown TargetTransformInfo::CacheLevel"
, "/build/llvm-toolchain-snapshot-7~svn329677/include/llvm/Analysis/TargetTransformInfoImpl.h"
, 385)
;
386 }
387
388 unsigned getPrefetchDistance() { return 0; }
389
390 unsigned getMinPrefetchStride() { return 1; }
391
392 unsigned getMaxPrefetchIterationsAhead() { return UINT_MAX(2147483647 *2U +1U); }
393
394 unsigned getMaxInterleaveFactor(unsigned VF) { return 1; }
395
396 unsigned getArithmeticInstrCost(unsigned Opcode, Type *Ty,
397 TTI::OperandValueKind Opd1Info,
398 TTI::OperandValueKind Opd2Info,
399 TTI::OperandValueProperties Opd1PropInfo,
400 TTI::OperandValueProperties Opd2PropInfo,
401 ArrayRef<const Value *> Args) {
402 return 1;
403 }
404
405 unsigned getShuffleCost(TTI::ShuffleKind Kind, Type *Ty, int Index,
406 Type *SubTp) {
407 return 1;
408 }
409
410 unsigned getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src,
411 const Instruction *I) { return 1; }
412
413 unsigned getExtractWithExtendCost(unsigned Opcode, Type *Dst,
414 VectorType *VecTy, unsigned Index) {
415 return 1;
416 }
417
418 unsigned getCFInstrCost(unsigned Opcode) { return 1; }
419
420 unsigned getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy,
421 const Instruction *I) {
422 return 1;
423 }
424
425 unsigned getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index) {
426 return 1;
427 }
428
429 unsigned getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment,
430 unsigned AddressSpace, const Instruction *I) {
431 return 1;
432 }
433
434 unsigned getMaskedMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment,
435 unsigned AddressSpace) {
436 return 1;
437 }
438
439 unsigned getGatherScatterOpCost(unsigned Opcode, Type *DataTy, Value *Ptr,
440 bool VariableMask,
441 unsigned Alignment) {
442 return 1;
443 }
444
445 unsigned getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy,
446 unsigned Factor,
447 ArrayRef<unsigned> Indices,
448 unsigned Alignment,
449 unsigned AddressSpace) {
450 return 1;
451 }
452
453 unsigned getIntrinsicInstrCost(Intrinsic::ID ID, Type *RetTy,
454 ArrayRef<Type *> Tys, FastMathFlags FMF,
455 unsigned ScalarizationCostPassed) {
456 return 1;
457 }
458 unsigned getIntrinsicInstrCost(Intrinsic::ID ID, Type *RetTy,
459 ArrayRef<Value *> Args, FastMathFlags FMF, unsigned VF) {
460 return 1;
461 }
462
463 unsigned getCallInstrCost(Function *F, Type *RetTy, ArrayRef<Type *> Tys) {
464 return 1;
465 }
466
467 unsigned getNumberOfParts(Type *Tp) { return 0; }
468
469 unsigned getAddressComputationCost(Type *Tp, ScalarEvolution *,
470 const SCEV *) {
471 return 0;
472 }
473
474 unsigned getArithmeticReductionCost(unsigned, Type *, bool) { return 1; }
475
476 unsigned getMinMaxReductionCost(Type *, Type *, bool, bool) { return 1; }
477
478 unsigned getCostOfKeepingLiveOverCall(ArrayRef<Type *> Tys) { return 0; }
479
480 bool getTgtMemIntrinsic(IntrinsicInst *Inst, MemIntrinsicInfo &Info) {
481 return false;
482 }
483
484 unsigned getAtomicMemIntrinsicMaxElementSize() const {
485 // Note for overrides: You must ensure for all element unordered-atomic
486 // memory intrinsics that all power-of-2 element sizes up to, and
487 // including, the return value of this method have a corresponding
488 // runtime lib call. These runtime lib call definitions can be found
489 // in RuntimeLibcalls.h
490 return 0;
491 }
492
493 Value *getOrCreateResultFromMemIntrinsic(IntrinsicInst *Inst,
494 Type *ExpectedType) {
495 return nullptr;
496 }
497
498 Type *getMemcpyLoopLoweringType(LLVMContext &Context, Value *Length,
499 unsigned SrcAlign, unsigned DestAlign) const {
500 return Type::getInt8Ty(Context);
501 }
502
503 void getMemcpyLoopResidualLoweringType(SmallVectorImpl<Type *> &OpsOut,
504 LLVMContext &Context,
505 unsigned RemainingBytes,
506 unsigned SrcAlign,
507 unsigned DestAlign) const {
508 for (unsigned i = 0; i != RemainingBytes; ++i)
509 OpsOut.push_back(Type::getInt8Ty(Context));
510 }
511
512 bool areInlineCompatible(const Function *Caller,
513 const Function *Callee) const {
514 return (Caller->getFnAttribute("target-cpu") ==
515 Callee->getFnAttribute("target-cpu")) &&
516 (Caller->getFnAttribute("target-features") ==
517 Callee->getFnAttribute("target-features"));
518 }
519
520 bool isIndexedLoadLegal(TTI::MemIndexedMode Mode, Type *Ty,
521 const DataLayout &DL) const {
522 return false;
523 }
524
525 bool isIndexedStoreLegal(TTI::MemIndexedMode Mode, Type *Ty,
526 const DataLayout &DL) const {
527 return false;
528 }
529
530 unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const { return 128; }
531
532 bool isLegalToVectorizeLoad(LoadInst *LI) const { return true; }
533
534 bool isLegalToVectorizeStore(StoreInst *SI) const { return true; }
535
536 bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes,
537 unsigned Alignment,
538 unsigned AddrSpace) const {
539 return true;
540 }
541
542 bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes,
543 unsigned Alignment,
544 unsigned AddrSpace) const {
545 return true;
546 }
547
548 unsigned getLoadVectorFactor(unsigned VF, unsigned LoadSize,
549 unsigned ChainSizeInBytes,
550 VectorType *VecTy) const {
551 return VF;
552 }
553
554 unsigned getStoreVectorFactor(unsigned VF, unsigned StoreSize,
555 unsigned ChainSizeInBytes,
556 VectorType *VecTy) const {
557 return VF;
558 }
559
560 bool useReductionIntrinsic(unsigned Opcode, Type *Ty,
561 TTI::ReductionFlags Flags) const {
562 return false;
563 }
564
565 bool shouldExpandReduction(const IntrinsicInst *II) const {
566 return true;
567 }
568
569protected:
570 // Obtain the minimum required size to hold the value (without the sign)
571 // In case of a vector it returns the min required size for one element.
572 unsigned minRequiredElementSize(const Value* Val, bool &isSigned) {
573 if (isa<ConstantDataVector>(Val) || isa<ConstantVector>(Val)) {
574 const auto* VectorValue = cast<Constant>(Val);
575
576 // In case of a vector need to pick the max between the min
577 // required size for each element
578 auto *VT = cast<VectorType>(Val->getType());
579
580 // Assume unsigned elements
581 isSigned = false;
582
583 // The max required size is the total vector width divided by num
584 // of elements in the vector
585 unsigned MaxRequiredSize = VT->getBitWidth() / VT->getNumElements();
586
587 unsigned MinRequiredSize = 0;
588 for(unsigned i = 0, e = VT->getNumElements(); i < e; ++i) {
589 if (auto* IntElement =
590 dyn_cast<ConstantInt>(VectorValue->getAggregateElement(i))) {
591 bool signedElement = IntElement->getValue().isNegative();
592 // Get the element min required size.
593 unsigned ElementMinRequiredSize =
594 IntElement->getValue().getMinSignedBits() - 1;
595 // In case one element is signed then all the vector is signed.
596 isSigned |= signedElement;
597 // Save the max required bit size between all the elements.
598 MinRequiredSize = std::max(MinRequiredSize, ElementMinRequiredSize);
599 }
600 else {
601 // not an int constant element
602 return MaxRequiredSize;
603 }
604 }
605 return MinRequiredSize;
606 }
607
608 if (const auto* CI = dyn_cast<ConstantInt>(Val)) {
609 isSigned = CI->getValue().isNegative();
610 return CI->getValue().getMinSignedBits() - 1;
611 }
612
613 if (const auto* Cast = dyn_cast<SExtInst>(Val)) {
614 isSigned = true;
615 return Cast->getSrcTy()->getScalarSizeInBits() - 1;
616 }
617
618 if (const auto* Cast = dyn_cast<ZExtInst>(Val)) {
619 isSigned = false;
620 return Cast->getSrcTy()->getScalarSizeInBits();
621 }
622
623 isSigned = false;
624 return Val->getType()->getScalarSizeInBits();
625 }
626
627 bool isStridedAccess(const SCEV *Ptr) {
628 return Ptr && isa<SCEVAddRecExpr>(Ptr);
629 }
630
631 const SCEVConstant *getConstantStrideStep(ScalarEvolution *SE,
632 const SCEV *Ptr) {
633 if (!isStridedAccess(Ptr))
634 return nullptr;
635 const SCEVAddRecExpr *AddRec = cast<SCEVAddRecExpr>(Ptr);
636 return dyn_cast<SCEVConstant>(AddRec->getStepRecurrence(*SE));
637 }
638
639 bool isConstantStridedAccessLessThan(ScalarEvolution *SE, const SCEV *Ptr,
640 int64_t MergeDistance) {
641 const SCEVConstant *Step = getConstantStrideStep(SE, Ptr);
642 if (!Step)
643 return false;
644 APInt StrideVal = Step->getAPInt();
645 if (StrideVal.getBitWidth() > 64)
646 return false;
647 // FIXME: Need to take absolute value for negative stride case.
648 return StrideVal.getSExtValue() < MergeDistance;
649 }
650};
651
652/// \brief CRTP base class for use as a mix-in that aids implementing
653/// a TargetTransformInfo-compatible class.
654template <typename T>
655class TargetTransformInfoImplCRTPBase : public TargetTransformInfoImplBase {
656private:
657 typedef TargetTransformInfoImplBase BaseT;
658
659protected:
660 explicit TargetTransformInfoImplCRTPBase(const DataLayout &DL) : BaseT(DL) {}
661
662public:
663 using BaseT::getCallCost;
664
665 unsigned getCallCost(const Function *F, int NumArgs) {
666 assert(F && "A concrete function must be provided to this routine.")(static_cast <bool> (F && "A concrete function must be provided to this routine."
) ? void (0) : __assert_fail ("F && \"A concrete function must be provided to this routine.\""
, "/build/llvm-toolchain-snapshot-7~svn329677/include/llvm/Analysis/TargetTransformInfoImpl.h"
, 666, __extension__ __PRETTY_FUNCTION__))
;
667
668 if (NumArgs < 0)
669 // Set the argument number to the number of explicit arguments in the
670 // function.
671 NumArgs = F->arg_size();
672
673 if (Intrinsic::ID IID = F->getIntrinsicID()) {
674 FunctionType *FTy = F->getFunctionType();
675 SmallVector<Type *, 8> ParamTys(FTy->param_begin(), FTy->param_end());
676 return static_cast<T *>(this)
677 ->getIntrinsicCost(IID, FTy->getReturnType(), ParamTys);
678 }
679
680 if (!static_cast<T *>(this)->isLoweredToCall(F))
681 return TTI::TCC_Basic; // Give a basic cost if it will be lowered
682 // directly.
683
684 return static_cast<T *>(this)->getCallCost(F->getFunctionType(), NumArgs);
685 }
686
687 unsigned getCallCost(const Function *F, ArrayRef<const Value *> Arguments) {
688 // Simply delegate to generic handling of the call.
689 // FIXME: We should use instsimplify or something else to catch calls which
690 // will constant fold with these arguments.
691 return static_cast<T *>(this)->getCallCost(F, Arguments.size());
692 }
693
694 using BaseT::getGEPCost;
695
696 int getGEPCost(Type *PointeeType, const Value *Ptr,
697 ArrayRef<const Value *> Operands) {
698 const GlobalValue *BaseGV = nullptr;
699 if (Ptr != nullptr) {
10
Assuming pointer value is null
11
Taking false branch
700 // TODO: will remove this when pointers have an opaque type.
701 assert(Ptr->getType()->getScalarType()->getPointerElementType() ==(static_cast <bool> (Ptr->getType()->getScalarType
()->getPointerElementType() == PointeeType && "explicit pointee type doesn't match operand's pointee type"
) ? void (0) : __assert_fail ("Ptr->getType()->getScalarType()->getPointerElementType() == PointeeType && \"explicit pointee type doesn't match operand's pointee type\""
, "/build/llvm-toolchain-snapshot-7~svn329677/include/llvm/Analysis/TargetTransformInfoImpl.h"
, 703, __extension__ __PRETTY_FUNCTION__))
702 PointeeType &&(static_cast <bool> (Ptr->getType()->getScalarType
()->getPointerElementType() == PointeeType && "explicit pointee type doesn't match operand's pointee type"
) ? void (0) : __assert_fail ("Ptr->getType()->getScalarType()->getPointerElementType() == PointeeType && \"explicit pointee type doesn't match operand's pointee type\""
, "/build/llvm-toolchain-snapshot-7~svn329677/include/llvm/Analysis/TargetTransformInfoImpl.h"
, 703, __extension__ __PRETTY_FUNCTION__))
703 "explicit pointee type doesn't match operand's pointee type")(static_cast <bool> (Ptr->getType()->getScalarType
()->getPointerElementType() == PointeeType && "explicit pointee type doesn't match operand's pointee type"
) ? void (0) : __assert_fail ("Ptr->getType()->getScalarType()->getPointerElementType() == PointeeType && \"explicit pointee type doesn't match operand's pointee type\""
, "/build/llvm-toolchain-snapshot-7~svn329677/include/llvm/Analysis/TargetTransformInfoImpl.h"
, 703, __extension__ __PRETTY_FUNCTION__))
;
704 BaseGV = dyn_cast<GlobalValue>(Ptr->stripPointerCasts());
705 }
706 bool HasBaseReg = (BaseGV == nullptr);
707
708 auto PtrSizeBits = DL.getPointerTypeSizeInBits(Ptr->getType());
12
Called C++ object pointer is null
709 APInt BaseOffset(PtrSizeBits, 0);
710 int64_t Scale = 0;
711
712 auto GTI = gep_type_begin(PointeeType, Operands);
713 Type *TargetType = nullptr;
714
715 // Handle the case where the GEP instruction has a single operand,
716 // the basis, therefore TargetType is a nullptr.
717 if (Operands.empty())
718 return !BaseGV ? TTI::TCC_Free : TTI::TCC_Basic;
719
720 for (auto I = Operands.begin(); I != Operands.end(); ++I, ++GTI) {
721 TargetType = GTI.getIndexedType();
722 // We assume that the cost of Scalar GEP with constant index and the
723 // cost of Vector GEP with splat constant index are the same.
724 const ConstantInt *ConstIdx = dyn_cast<ConstantInt>(*I);
725 if (!ConstIdx)
726 if (auto Splat = getSplatValue(*I))
727 ConstIdx = dyn_cast<ConstantInt>(Splat);
728 if (StructType *STy = GTI.getStructTypeOrNull()) {
729 // For structures the index is always splat or scalar constant
730 assert(ConstIdx && "Unexpected GEP index")(static_cast <bool> (ConstIdx && "Unexpected GEP index"
) ? void (0) : __assert_fail ("ConstIdx && \"Unexpected GEP index\""
, "/build/llvm-toolchain-snapshot-7~svn329677/include/llvm/Analysis/TargetTransformInfoImpl.h"
, 730, __extension__ __PRETTY_FUNCTION__))
;
731 uint64_t Field = ConstIdx->getZExtValue();
732 BaseOffset += DL.getStructLayout(STy)->getElementOffset(Field);
733 } else {
734 int64_t ElementSize = DL.getTypeAllocSize(GTI.getIndexedType());
735 if (ConstIdx) {
736 BaseOffset +=
737 ConstIdx->getValue().sextOrTrunc(PtrSizeBits) * ElementSize;
738 } else {
739 // Needs scale register.
740 if (Scale != 0)
741 // No addressing mode takes two scale registers.
742 return TTI::TCC_Basic;
743 Scale = ElementSize;
744 }
745 }
746 }
747
748 // Assumes the address space is 0 when Ptr is nullptr.
749 unsigned AS =
750 (Ptr == nullptr ? 0 : Ptr->getType()->getPointerAddressSpace());
751
752 if (static_cast<T *>(this)->isLegalAddressingMode(
753 TargetType, const_cast<GlobalValue *>(BaseGV),
754 BaseOffset.sextOrTrunc(64).getSExtValue(), HasBaseReg, Scale, AS))
755 return TTI::TCC_Free;
756 return TTI::TCC_Basic;
757 }
758
759 using BaseT::getIntrinsicCost;
760
761 unsigned getIntrinsicCost(Intrinsic::ID IID, Type *RetTy,
762 ArrayRef<const Value *> Arguments) {
763 // Delegate to the generic intrinsic handling code. This mostly provides an
764 // opportunity for targets to (for example) special case the cost of
765 // certain intrinsics based on constants used as arguments.
766 SmallVector<Type *, 8> ParamTys;
767 ParamTys.reserve(Arguments.size());
768 for (unsigned Idx = 0, Size = Arguments.size(); Idx != Size; ++Idx)
769 ParamTys.push_back(Arguments[Idx]->getType());
770 return static_cast<T *>(this)->getIntrinsicCost(IID, RetTy, ParamTys);
771 }
772
773 unsigned getUserCost(const User *U, ArrayRef<const Value *> Operands) {
774 if (isa<PHINode>(U))
3
Taking false branch
775 return TTI::TCC_Free; // Model all PHI nodes as free.
776
777 // Static alloca doesn't generate target instructions.
778 if (auto *A = dyn_cast<AllocaInst>(U))
4
Taking false branch
779 if (A->isStaticAlloca())
780 return TTI::TCC_Free;
781
782 if (const GEPOperator *GEP = dyn_cast<GEPOperator>(U)) {
5
Assuming 'GEP' is non-null
6
Taking true branch
783 return static_cast<T *>(this)->getGEPCost(GEP->getSourceElementType(),
7
Calling 'BasicTTIImplBase::getGEPCost'
784 GEP->getPointerOperand(),
785 Operands.drop_front());
786 }
787
788 if (auto CS = ImmutableCallSite(U)) {
789 const Function *F = CS.getCalledFunction();
790 if (!F) {
791 // Just use the called value type.
792 Type *FTy = CS.getCalledValue()->getType()->getPointerElementType();
793 return static_cast<T *>(this)
794 ->getCallCost(cast<FunctionType>(FTy), CS.arg_size());
795 }
796
797 SmallVector<const Value *, 8> Arguments(CS.arg_begin(), CS.arg_end());
798 return static_cast<T *>(this)->getCallCost(F, Arguments);
799 }
800
801 if (const CastInst *CI = dyn_cast<CastInst>(U)) {
802 // Result of a cmp instruction is often extended (to be used by other
803 // cmp instructions, logical or return instructions). These are usually
804 // nop on most sane targets.
805 if (isa<CmpInst>(CI->getOperand(0)))
806 return TTI::TCC_Free;
807 if (isa<SExtInst>(CI) || isa<ZExtInst>(CI) || isa<FPExtInst>(CI))
808 return static_cast<T *>(this)->getExtCost(CI, Operands.back());
809 }
810
811 return static_cast<T *>(this)->getOperationCost(
812 Operator::getOpcode(U), U->getType(),
813 U->getNumOperands() == 1 ? U->getOperand(0)->getType() : nullptr);
814 }
815
816 int getInstructionLatency(const Instruction *I) {
817 SmallVector<const Value *, 4> Operands(I->value_op_begin(),
818 I->value_op_end());
819 if (getUserCost(I, Operands) == TTI::TCC_Free)
820 return 0;
821
822 if (isa<LoadInst>(I))
823 return 4;
824
825 Type *DstTy = I->getType();
826
827 // Usually an intrinsic is a simple instruction.
828 // A real function call is much slower.
829 if (auto *CI = dyn_cast<CallInst>(I)) {
830 const Function *F = CI->getCalledFunction();
831 if (!F || static_cast<T *>(this)->isLoweredToCall(F))
832 return 40;
833 // Some intrinsics return a value and a flag, we use the value type
834 // to decide its latency.
835 if (StructType* StructTy = dyn_cast<StructType>(DstTy))
836 DstTy = StructTy->getElementType(0);
837 // Fall through to simple instructions.
838 }
839
840 if (VectorType *VectorTy = dyn_cast<VectorType>(DstTy))
841 DstTy = VectorTy->getElementType();
842 if (DstTy->isFloatingPointTy())
843 return 3;
844
845 return 1;
846 }
847};
848}
849
850#endif

/build/llvm-toolchain-snapshot-7~svn329677/include/llvm/CodeGen/BasicTTIImpl.h

1//===- BasicTTIImpl.h -------------------------------------------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10/// \file
11/// This file provides a helper that implements much of the TTI interface in
12/// terms of the target-independent code generator and TargetLowering
13/// interfaces.
14//
15//===----------------------------------------------------------------------===//
16
17#ifndef LLVM_CODEGEN_BASICTTIIMPL_H
18#define LLVM_CODEGEN_BASICTTIIMPL_H
19
20#include "llvm/ADT/APInt.h"
21#include "llvm/ADT/ArrayRef.h"
22#include "llvm/ADT/BitVector.h"
23#include "llvm/ADT/SmallPtrSet.h"
24#include "llvm/ADT/SmallVector.h"
25#include "llvm/Analysis/LoopInfo.h"
26#include "llvm/Analysis/TargetTransformInfo.h"
27#include "llvm/Analysis/TargetTransformInfoImpl.h"
28#include "llvm/CodeGen/ISDOpcodes.h"
29#include "llvm/CodeGen/TargetLowering.h"
30#include "llvm/CodeGen/TargetSubtargetInfo.h"
31#include "llvm/CodeGen/ValueTypes.h"
32#include "llvm/IR/BasicBlock.h"
33#include "llvm/IR/CallSite.h"
34#include "llvm/IR/Constant.h"
35#include "llvm/IR/Constants.h"
36#include "llvm/IR/DataLayout.h"
37#include "llvm/IR/DerivedTypes.h"
38#include "llvm/IR/InstrTypes.h"
39#include "llvm/IR/Instruction.h"
40#include "llvm/IR/Instructions.h"
41#include "llvm/IR/Intrinsics.h"
42#include "llvm/IR/Operator.h"
43#include "llvm/IR/Type.h"
44#include "llvm/IR/Value.h"
45#include "llvm/MC/MCSchedule.h"
46#include "llvm/Support/Casting.h"
47#include "llvm/Support/CommandLine.h"
48#include "llvm/Support/ErrorHandling.h"
49#include "llvm/Support/MachineValueType.h"
50#include "llvm/Support/MathExtras.h"
51#include <algorithm>
52#include <cassert>
53#include <cstdint>
54#include <limits>
55#include <utility>
56
57namespace llvm {
58
59class Function;
60class GlobalValue;
61class LLVMContext;
62class ScalarEvolution;
63class SCEV;
64class TargetMachine;
65
66extern cl::opt<unsigned> PartialUnrollingThreshold;
67
68/// \brief Base class which can be used to help build a TTI implementation.
69///
70/// This class provides as much implementation of the TTI interface as is
71/// possible using the target independent parts of the code generator.
72///
73/// In order to subclass it, your class must implement a getST() method to
74/// return the subtarget, and a getTLI() method to return the target lowering.
75/// We need these methods implemented in the derived class so that this class
76/// doesn't have to duplicate storage for them.
77template <typename T>
78class BasicTTIImplBase : public TargetTransformInfoImplCRTPBase<T> {
79private:
80 using BaseT = TargetTransformInfoImplCRTPBase<T>;
81 using TTI = TargetTransformInfo;
82
83 /// Estimate a cost of shuffle as a sequence of extract and insert
84 /// operations.
85 unsigned getPermuteShuffleOverhead(Type *Ty) {
86 assert(Ty->isVectorTy() && "Can only shuffle vectors")(static_cast <bool> (Ty->isVectorTy() && "Can only shuffle vectors"
) ? void (0) : __assert_fail ("Ty->isVectorTy() && \"Can only shuffle vectors\""
, "/build/llvm-toolchain-snapshot-7~svn329677/include/llvm/CodeGen/BasicTTIImpl.h"
, 86, __extension__ __PRETTY_FUNCTION__))
;
87 unsigned Cost = 0;
88 // Shuffle cost is equal to the cost of extracting element from its argument
89 // plus the cost of inserting them onto the result vector.
90
91 // e.g. <4 x float> has a mask of <0,5,2,7> i.e we need to extract from
92 // index 0 of first vector, index 1 of second vector,index 2 of first
93 // vector and finally index 3 of second vector and insert them at index
94 // <0,1,2,3> of result vector.
95 for (int i = 0, e = Ty->getVectorNumElements(); i < e; ++i) {
96 Cost += static_cast<T *>(this)
97 ->getVectorInstrCost(Instruction::InsertElement, Ty, i);
98 Cost += static_cast<T *>(this)
99 ->getVectorInstrCost(Instruction::ExtractElement, Ty, i);
100 }
101 return Cost;
102 }
103
104 /// \brief Local query method delegates up to T which *must* implement this!
105 const TargetSubtargetInfo *getST() const {
106 return static_cast<const T *>(this)->getST();
107 }
108
109 /// \brief Local query method delegates up to T which *must* implement this!
110 const TargetLoweringBase *getTLI() const {
111 return static_cast<const T *>(this)->getTLI();
112 }
113
114 static ISD::MemIndexedMode getISDIndexedMode(TTI::MemIndexedMode M) {
115 switch (M) {
116 case TTI::MIM_Unindexed:
117 return ISD::UNINDEXED;
118 case TTI::MIM_PreInc:
119 return ISD::PRE_INC;
120 case TTI::MIM_PreDec:
121 return ISD::PRE_DEC;
122 case TTI::MIM_PostInc:
123 return ISD::POST_INC;
124 case TTI::MIM_PostDec:
125 return ISD::POST_DEC;
126 }
127 llvm_unreachable("Unexpected MemIndexedMode")::llvm::llvm_unreachable_internal("Unexpected MemIndexedMode"
, "/build/llvm-toolchain-snapshot-7~svn329677/include/llvm/CodeGen/BasicTTIImpl.h"
, 127)
;
128 }
129
130protected:
131 explicit BasicTTIImplBase(const TargetMachine *TM, const DataLayout &DL)
132 : BaseT(DL) {}
133
134 using TargetTransformInfoImplBase::DL;
135
136public:
137 /// \name Scalar TTI Implementations
138 /// @{
139 bool allowsMisalignedMemoryAccesses(LLVMContext &Context,
140 unsigned BitWidth, unsigned AddressSpace,
141 unsigned Alignment, bool *Fast) const {
142 EVT E = EVT::getIntegerVT(Context, BitWidth);
143 return getTLI()->allowsMisalignedMemoryAccesses(E, AddressSpace, Alignment, Fast);
144 }
145
146 bool hasBranchDivergence() { return false; }
147
148 bool isSourceOfDivergence(const Value *V) { return false; }
149
150 bool isAlwaysUniform(const Value *V) { return false; }
151
152 unsigned getFlatAddressSpace() {
153 // Return an invalid address space.
154 return -1;
155 }
156
157 bool isLegalAddImmediate(int64_t imm) {
158 return getTLI()->isLegalAddImmediate(imm);
159 }
160
161 bool isLegalICmpImmediate(int64_t imm) {
162 return getTLI()->isLegalICmpImmediate(imm);
163 }
164
165 bool isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset,
166 bool HasBaseReg, int64_t Scale,
167 unsigned AddrSpace, Instruction *I = nullptr) {
168 TargetLoweringBase::AddrMode AM;
169 AM.BaseGV = BaseGV;
170 AM.BaseOffs = BaseOffset;
171 AM.HasBaseReg = HasBaseReg;
172 AM.Scale = Scale;
173 return getTLI()->isLegalAddressingMode(DL, AM, Ty, AddrSpace, I);
174 }
175
176 bool isIndexedLoadLegal(TTI::MemIndexedMode M, Type *Ty,
177 const DataLayout &DL) const {
178 EVT VT = getTLI()->getValueType(DL, Ty);
179 return getTLI()->isIndexedLoadLegal(getISDIndexedMode(M), VT);
180 }
181
182 bool isIndexedStoreLegal(TTI::MemIndexedMode M, Type *Ty,
183 const DataLayout &DL) const {
184 EVT VT = getTLI()->getValueType(DL, Ty);
185 return getTLI()->isIndexedStoreLegal(getISDIndexedMode(M), VT);
186 }
187
188 bool isLSRCostLess(TTI::LSRCost C1, TTI::LSRCost C2) {
189 return TargetTransformInfoImplBase::isLSRCostLess(C1, C2);
190 }
191
192 int getScalingFactorCost(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset,
193 bool HasBaseReg, int64_t Scale, unsigned AddrSpace) {
194 TargetLoweringBase::AddrMode AM;
195 AM.BaseGV = BaseGV;
196 AM.BaseOffs = BaseOffset;
197 AM.HasBaseReg = HasBaseReg;
198 AM.Scale = Scale;
199 return getTLI()->getScalingFactorCost(DL, AM, Ty, AddrSpace);
200 }
201
202 bool isTruncateFree(Type *Ty1, Type *Ty2) {
203 return getTLI()->isTruncateFree(Ty1, Ty2);
204 }
205
206 bool isProfitableToHoist(Instruction *I) {
207 return getTLI()->isProfitableToHoist(I);
208 }
209
210 bool useAA() const { return getST()->useAA(); }
211
212 bool isTypeLegal(Type *Ty) {
213 EVT VT = getTLI()->getValueType(DL, Ty);
214 return getTLI()->isTypeLegal(VT);
215 }
216
217 int getGEPCost(Type *PointeeType, const Value *Ptr,
218 ArrayRef<const Value *> Operands) {
219 return BaseT::getGEPCost(PointeeType, Ptr, Operands);
8
Passing value via 2nd parameter 'Ptr'
9
Calling 'TargetTransformInfoImplCRTPBase::getGEPCost'
220 }
221
222 int getExtCost(const Instruction *I, const Value *Src) {
223 if (getTLI()->isExtFree(I))
224 return TargetTransformInfo::TCC_Free;
225
226 if (isa<ZExtInst>(I) || isa<SExtInst>(I))
227 if (const LoadInst *LI = dyn_cast<LoadInst>(Src))
228 if (getTLI()->isExtLoad(LI, I, DL))
229 return TargetTransformInfo::TCC_Free;
230
231 return TargetTransformInfo::TCC_Basic;
232 }
233
234 unsigned getIntrinsicCost(Intrinsic::ID IID, Type *RetTy,
235 ArrayRef<const Value *> Arguments) {
236 return BaseT::getIntrinsicCost(IID, RetTy, Arguments);
237 }
238
239 unsigned getIntrinsicCost(Intrinsic::ID IID, Type *RetTy,
240 ArrayRef<Type *> ParamTys) {
241 if (IID == Intrinsic::cttz) {
242 if (getTLI()->isCheapToSpeculateCttz())
243 return TargetTransformInfo::TCC_Basic;
244 return TargetTransformInfo::TCC_Expensive;
245 }
246
247 if (IID == Intrinsic::ctlz) {
248 if (getTLI()->isCheapToSpeculateCtlz())
249 return TargetTransformInfo::TCC_Basic;
250 return TargetTransformInfo::TCC_Expensive;
251 }
252
253 return BaseT::getIntrinsicCost(IID, RetTy, ParamTys);
254 }
255
256 unsigned getEstimatedNumberOfCaseClusters(const SwitchInst &SI,
257 unsigned &JumpTableSize) {
258 /// Try to find the estimated number of clusters. Note that the number of
259 /// clusters identified in this function could be different from the actural
260 /// numbers found in lowering. This function ignore switches that are
261 /// lowered with a mix of jump table / bit test / BTree. This function was
262 /// initially intended to be used when estimating the cost of switch in
263 /// inline cost heuristic, but it's a generic cost model to be used in other
264 /// places (e.g., in loop unrolling).
265 unsigned N = SI.getNumCases();
266 const TargetLoweringBase *TLI = getTLI();
267 const DataLayout &DL = this->getDataLayout();
268
269 JumpTableSize = 0;
270 bool IsJTAllowed = TLI->areJTsAllowed(SI.getParent()->getParent());
271
272 // Early exit if both a jump table and bit test are not allowed.
273 if (N < 1 || (!IsJTAllowed && DL.getIndexSizeInBits(0u) < N))
274 return N;
275
276 APInt MaxCaseVal = SI.case_begin()->getCaseValue()->getValue();
277 APInt MinCaseVal = MaxCaseVal;
278 for (auto CI : SI.cases()) {
279 const APInt &CaseVal = CI.getCaseValue()->getValue();
280 if (CaseVal.sgt(MaxCaseVal))
281 MaxCaseVal = CaseVal;
282 if (CaseVal.slt(MinCaseVal))
283 MinCaseVal = CaseVal;
284 }
285
286 // Check if suitable for a bit test
287 if (N <= DL.getIndexSizeInBits(0u)) {
288 SmallPtrSet<const BasicBlock *, 4> Dests;
289 for (auto I : SI.cases())
290 Dests.insert(I.getCaseSuccessor());
291
292 if (TLI->isSuitableForBitTests(Dests.size(), N, MinCaseVal, MaxCaseVal,
293 DL))
294 return 1;
295 }
296
297 // Check if suitable for a jump table.
298 if (IsJTAllowed) {
299 if (N < 2 || N < TLI->getMinimumJumpTableEntries())
300 return N;
301 uint64_t Range =
302 (MaxCaseVal - MinCaseVal)
303 .getLimitedValue(std::numeric_limits<uint64_t>::max() - 1) + 1;
304 // Check whether a range of clusters is dense enough for a jump table
305 if (TLI->isSuitableForJumpTable(&SI, N, Range)) {
306 JumpTableSize = Range;
307 return 1;
308 }
309 }
310 return N;
311 }
312
313 unsigned getJumpBufAlignment() { return getTLI()->getJumpBufAlignment(); }
314
315 unsigned getJumpBufSize() { return getTLI()->getJumpBufSize(); }
316
317 bool shouldBuildLookupTables() {
318 const TargetLoweringBase *TLI = getTLI();
319 return TLI->isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
320 TLI->isOperationLegalOrCustom(ISD::BRIND, MVT::Other);
321 }
322
323 bool haveFastSqrt(Type *Ty) {
324 const TargetLoweringBase *TLI = getTLI();
325 EVT VT = TLI->getValueType(DL, Ty);
326 return TLI->isTypeLegal(VT) &&
327 TLI->isOperationLegalOrCustom(ISD::FSQRT, VT);
328 }
329
330 bool isFCmpOrdCheaperThanFCmpZero(Type *Ty) {
331 return true;
332 }
333
334 unsigned getFPOpCost(Type *Ty) {
335 // Check whether FADD is available, as a proxy for floating-point in
336 // general.
337 const TargetLoweringBase *TLI = getTLI();
338 EVT VT = TLI->getValueType(DL, Ty);
339 if (TLI->isOperationLegalOrCustomOrPromote(ISD::FADD, VT))
340 return TargetTransformInfo::TCC_Basic;
341 return TargetTransformInfo::TCC_Expensive;
342 }
343
344 unsigned getOperationCost(unsigned Opcode, Type *Ty, Type *OpTy) {
345 const TargetLoweringBase *TLI = getTLI();
346 switch (Opcode) {
347 default: break;
348 case Instruction::Trunc:
349 if (TLI->isTruncateFree(OpTy, Ty))
350 return TargetTransformInfo::TCC_Free;
351 return TargetTransformInfo::TCC_Basic;
352 case Instruction::ZExt:
353 if (TLI->isZExtFree(OpTy, Ty))
354 return TargetTransformInfo::TCC_Free;
355 return TargetTransformInfo::TCC_Basic;
356 }
357
358 return BaseT::getOperationCost(Opcode, Ty, OpTy);
359 }
360
361 unsigned getInliningThresholdMultiplier() { return 1; }
362
363 void getUnrollingPreferences(Loop *L, ScalarEvolution &SE,
364 TTI::UnrollingPreferences &UP) {
365 // This unrolling functionality is target independent, but to provide some
366 // motivation for its intended use, for x86:
367
368 // According to the Intel 64 and IA-32 Architectures Optimization Reference
369 // Manual, Intel Core models and later have a loop stream detector (and
370 // associated uop queue) that can benefit from partial unrolling.
371 // The relevant requirements are:
372 // - The loop must have no more than 4 (8 for Nehalem and later) branches
373 // taken, and none of them may be calls.
374 // - The loop can have no more than 18 (28 for Nehalem and later) uops.
375
376 // According to the Software Optimization Guide for AMD Family 15h
377 // Processors, models 30h-4fh (Steamroller and later) have a loop predictor
378 // and loop buffer which can benefit from partial unrolling.
379 // The relevant requirements are:
380 // - The loop must have fewer than 16 branches
381 // - The loop must have less than 40 uops in all executed loop branches
382
383 // The number of taken branches in a loop is hard to estimate here, and
384 // benchmarking has revealed that it is better not to be conservative when
385 // estimating the branch count. As a result, we'll ignore the branch limits
386 // until someone finds a case where it matters in practice.
387
388 unsigned MaxOps;
389 const TargetSubtargetInfo *ST = getST();
390 if (PartialUnrollingThreshold.getNumOccurrences() > 0)
391 MaxOps = PartialUnrollingThreshold;
392 else if (ST->getSchedModel().LoopMicroOpBufferSize > 0)
393 MaxOps = ST->getSchedModel().LoopMicroOpBufferSize;
394 else
395 return;
396
397 // Scan the loop: don't unroll loops with calls.
398 for (Loop::block_iterator I = L->block_begin(), E = L->block_end(); I != E;
399 ++I) {
400 BasicBlock *BB = *I;
401
402 for (BasicBlock::iterator J = BB->begin(), JE = BB->end(); J != JE; ++J)
403 if (isa<CallInst>(J) || isa<InvokeInst>(J)) {
404 ImmutableCallSite CS(&*J);
405 if (const Function *F = CS.getCalledFunction()) {
406 if (!static_cast<T *>(this)->isLoweredToCall(F))
407 continue;
408 }
409
410 return;
411 }
412 }
413
414 // Enable runtime and partial unrolling up to the specified size.
415 // Enable using trip count upper bound to unroll loops.
416 UP.Partial = UP.Runtime = UP.UpperBound = true;
417 UP.PartialThreshold = MaxOps;
418
419 // Avoid unrolling when optimizing for size.
420 UP.OptSizeThreshold = 0;
421 UP.PartialOptSizeThreshold = 0;
422
423 // Set number of instructions optimized when "back edge"
424 // becomes "fall through" to default value of 2.
425 UP.BEInsns = 2;
426 }
427
428 int getInstructionLatency(const Instruction *I) {
429 if (isa<LoadInst>(I))
430 return getST()->getSchedModel().DefaultLoadLatency;
431
432 return BaseT::getInstructionLatency(I);
433 }
434
435 /// @}
436
437 /// \name Vector TTI Implementations
438 /// @{
439
440 unsigned getNumberOfRegisters(bool Vector) { return Vector ? 0 : 1; }
441
442 unsigned getRegisterBitWidth(bool Vector) const { return 32; }
443
444 /// Estimate the overhead of scalarizing an instruction. Insert and Extract
445 /// are set if the result needs to be inserted and/or extracted from vectors.
446 unsigned getScalarizationOverhead(Type *Ty, bool Insert, bool Extract) {
447 assert(Ty->isVectorTy() && "Can only scalarize vectors")(static_cast <bool> (Ty->isVectorTy() && "Can only scalarize vectors"
) ? void (0) : __assert_fail ("Ty->isVectorTy() && \"Can only scalarize vectors\""
, "/build/llvm-toolchain-snapshot-7~svn329677/include/llvm/CodeGen/BasicTTIImpl.h"
, 447, __extension__ __PRETTY_FUNCTION__))
;
448 unsigned Cost = 0;
449
450 for (int i = 0, e = Ty->getVectorNumElements(); i < e; ++i) {
451 if (Insert)
452 Cost += static_cast<T *>(this)
453 ->getVectorInstrCost(Instruction::InsertElement, Ty, i);
454 if (Extract)
455 Cost += static_cast<T *>(this)
456 ->getVectorInstrCost(Instruction::ExtractElement, Ty, i);
457 }
458
459 return Cost;
460 }
461
462 /// Estimate the overhead of scalarizing an instructions unique
463 /// non-constant operands. The types of the arguments are ordinarily
464 /// scalar, in which case the costs are multiplied with VF.
465 unsigned getOperandsScalarizationOverhead(ArrayRef<const Value *> Args,
466 unsigned VF) {
467 unsigned Cost = 0;
468 SmallPtrSet<const Value*, 4> UniqueOperands;
469 for (const Value *A : Args) {
470 if (!isa<Constant>(A) && UniqueOperands.insert(A).second) {
471 Type *VecTy = nullptr;
472 if (A->getType()->isVectorTy()) {
473 VecTy = A->getType();
474 // If A is a vector operand, VF should be 1 or correspond to A.
475 assert((VF == 1 || VF == VecTy->getVectorNumElements()) &&(static_cast <bool> ((VF == 1 || VF == VecTy->getVectorNumElements
()) && "Vector argument does not match VF") ? void (0
) : __assert_fail ("(VF == 1 || VF == VecTy->getVectorNumElements()) && \"Vector argument does not match VF\""
, "/build/llvm-toolchain-snapshot-7~svn329677/include/llvm/CodeGen/BasicTTIImpl.h"
, 476, __extension__ __PRETTY_FUNCTION__))
476 "Vector argument does not match VF")(static_cast <bool> ((VF == 1 || VF == VecTy->getVectorNumElements
()) && "Vector argument does not match VF") ? void (0
) : __assert_fail ("(VF == 1 || VF == VecTy->getVectorNumElements()) && \"Vector argument does not match VF\""
, "/build/llvm-toolchain-snapshot-7~svn329677/include/llvm/CodeGen/BasicTTIImpl.h"
, 476, __extension__ __PRETTY_FUNCTION__))
;
477 }
478 else
479 VecTy = VectorType::get(A->getType(), VF);
480
481 Cost += getScalarizationOverhead(VecTy, false, true);
482 }
483 }
484
485 return Cost;
486 }
487
488 unsigned getScalarizationOverhead(Type *VecTy, ArrayRef<const Value *> Args) {
489 assert(VecTy->isVectorTy())(static_cast <bool> (VecTy->isVectorTy()) ? void (0)
: __assert_fail ("VecTy->isVectorTy()", "/build/llvm-toolchain-snapshot-7~svn329677/include/llvm/CodeGen/BasicTTIImpl.h"
, 489, __extension__ __PRETTY_FUNCTION__))
;
490
491 unsigned Cost = 0;
492
493 Cost += getScalarizationOverhead(VecTy, true, false);
494 if (!Args.empty())
495 Cost += getOperandsScalarizationOverhead(Args,
496 VecTy->getVectorNumElements());
497 else
498 // When no information on arguments is provided, we add the cost
499 // associated with one argument as a heuristic.
500 Cost += getScalarizationOverhead(VecTy, false, true);
501
502 return Cost;
503 }
504
505 unsigned getMaxInterleaveFactor(unsigned VF) { return 1; }
506
507 unsigned getArithmeticInstrCost(
508 unsigned Opcode, Type *Ty,
509 TTI::OperandValueKind Opd1Info = TTI::OK_AnyValue,
510 TTI::OperandValueKind Opd2Info = TTI::OK_AnyValue,
511 TTI::OperandValueProperties Opd1PropInfo = TTI::OP_None,
512 TTI::OperandValueProperties Opd2PropInfo = TTI::OP_None,
513 ArrayRef<const Value *> Args = ArrayRef<const Value *>()) {
514 // Check if any of the operands are vector operands.
515 const TargetLoweringBase *TLI = getTLI();
516 int ISD = TLI->InstructionOpcodeToISD(Opcode);
517 assert(ISD && "Invalid opcode")(static_cast <bool> (ISD && "Invalid opcode") ?
void (0) : __assert_fail ("ISD && \"Invalid opcode\""
, "/build/llvm-toolchain-snapshot-7~svn329677/include/llvm/CodeGen/BasicTTIImpl.h"
, 517, __extension__ __PRETTY_FUNCTION__))
;
518
519 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty);
520
521 bool IsFloat = Ty->isFPOrFPVectorTy();
522 // Assume that floating point arithmetic operations cost twice as much as
523 // integer operations.
524 unsigned OpCost = (IsFloat ? 2 : 1);
525
526 if (TLI->isOperationLegalOrPromote(ISD, LT.second)) {
527 // The operation is legal. Assume it costs 1.
528 // TODO: Once we have extract/insert subvector cost we need to use them.
529 return LT.first * OpCost;
530 }
531
532 if (!TLI->isOperationExpand(ISD, LT.second)) {
533 // If the operation is custom lowered, then assume that the code is twice
534 // as expensive.
535 return LT.first * 2 * OpCost;
536 }
537
538 // Else, assume that we need to scalarize this op.
539 // TODO: If one of the types get legalized by splitting, handle this
540 // similarly to what getCastInstrCost() does.
541 if (Ty->isVectorTy()) {
542 unsigned Num = Ty->getVectorNumElements();
543 unsigned Cost = static_cast<T *>(this)
544 ->getArithmeticInstrCost(Opcode, Ty->getScalarType());
545 // Return the cost of multiple scalar invocation plus the cost of
546 // inserting and extracting the values.
547 return getScalarizationOverhead(Ty, Args) + Num * Cost;
548 }
549
550 // We don't know anything about this scalar instruction.
551 return OpCost;
552 }
553
554 unsigned getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, int Index,
555 Type *SubTp) {
556 if (Kind == TTI::SK_Alternate || Kind == TTI::SK_PermuteTwoSrc ||
557 Kind == TTI::SK_PermuteSingleSrc) {
558 return getPermuteShuffleOverhead(Tp);
559 }
560 return 1;
561 }
562
563 unsigned getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src,
564 const Instruction *I = nullptr) {
565 const TargetLoweringBase *TLI = getTLI();
566 int ISD = TLI->InstructionOpcodeToISD(Opcode);
567 assert(ISD && "Invalid opcode")(static_cast <bool> (ISD && "Invalid opcode") ?
void (0) : __assert_fail ("ISD && \"Invalid opcode\""
, "/build/llvm-toolchain-snapshot-7~svn329677/include/llvm/CodeGen/BasicTTIImpl.h"
, 567, __extension__ __PRETTY_FUNCTION__))
;
568 std::pair<unsigned, MVT> SrcLT = TLI->getTypeLegalizationCost(DL, Src);
569 std::pair<unsigned, MVT> DstLT = TLI->getTypeLegalizationCost(DL, Dst);
570
571 // Check for NOOP conversions.
572 if (SrcLT.first == DstLT.first &&
573 SrcLT.second.getSizeInBits() == DstLT.second.getSizeInBits()) {
574
575 // Bitcast between types that are legalized to the same type are free.
576 if (Opcode == Instruction::BitCast || Opcode == Instruction::Trunc)
577 return 0;
578 }
579
580 if (Opcode == Instruction::Trunc &&
581 TLI->isTruncateFree(SrcLT.second, DstLT.second))
582 return 0;
583
584 if (Opcode == Instruction::ZExt &&
585 TLI->isZExtFree(SrcLT.second, DstLT.second))
586 return 0;
587
588 if (Opcode == Instruction::AddrSpaceCast &&
589 TLI->isNoopAddrSpaceCast(Src->getPointerAddressSpace(),
590 Dst->getPointerAddressSpace()))
591 return 0;
592
593 // If this is a zext/sext of a load, return 0 if the corresponding
594 // extending load exists on target.
595 if ((Opcode == Instruction::ZExt || Opcode == Instruction::SExt) &&
596 I && isa<LoadInst>(I->getOperand(0))) {
597 EVT ExtVT = EVT::getEVT(Dst);
598 EVT LoadVT = EVT::getEVT(Src);
599 unsigned LType =
600 ((Opcode == Instruction::ZExt) ? ISD::ZEXTLOAD : ISD::SEXTLOAD);
601 if (TLI->isLoadExtLegal(LType, ExtVT, LoadVT))
602 return 0;
603 }
604
605 // If the cast is marked as legal (or promote) then assume low cost.
606 if (SrcLT.first == DstLT.first &&
607 TLI->isOperationLegalOrPromote(ISD, DstLT.second))
608 return 1;
609
610 // Handle scalar conversions.
611 if (!Src->isVectorTy() && !Dst->isVectorTy()) {
612 // Scalar bitcasts are usually free.
613 if (Opcode == Instruction::BitCast)
614 return 0;
615
616 // Just check the op cost. If the operation is legal then assume it costs
617 // 1.
618 if (!TLI->isOperationExpand(ISD, DstLT.second))
619 return 1;
620
621 // Assume that illegal scalar instruction are expensive.
622 return 4;
623 }
624
625 // Check vector-to-vector casts.
626 if (Dst->isVectorTy() && Src->isVectorTy()) {
627 // If the cast is between same-sized registers, then the check is simple.
628 if (SrcLT.first == DstLT.first &&
629 SrcLT.second.getSizeInBits() == DstLT.second.getSizeInBits()) {
630
631 // Assume that Zext is done using AND.
632 if (Opcode == Instruction::ZExt)
633 return 1;
634
635 // Assume that sext is done using SHL and SRA.
636 if (Opcode == Instruction::SExt)
637 return 2;
638
639 // Just check the op cost. If the operation is legal then assume it
640 // costs
641 // 1 and multiply by the type-legalization overhead.
642 if (!TLI->isOperationExpand(ISD, DstLT.second))
643 return SrcLT.first * 1;
644 }
645
646 // If we are legalizing by splitting, query the concrete TTI for the cost
647 // of casting the original vector twice. We also need to factor in the
648 // cost of the split itself. Count that as 1, to be consistent with
649 // TLI->getTypeLegalizationCost().
650 if ((TLI->getTypeAction(Src->getContext(), TLI->getValueType(DL, Src)) ==
651 TargetLowering::TypeSplitVector) ||
652 (TLI->getTypeAction(Dst->getContext(), TLI->getValueType(DL, Dst)) ==
653 TargetLowering::TypeSplitVector)) {
654 Type *SplitDst = VectorType::get(Dst->getVectorElementType(),
655 Dst->getVectorNumElements() / 2);
656 Type *SplitSrc = VectorType::get(Src->getVectorElementType(),
657 Src->getVectorNumElements() / 2);
658 T *TTI = static_cast<T *>(this);
659 return TTI->getVectorSplitCost() +
660 (2 * TTI->getCastInstrCost(Opcode, SplitDst, SplitSrc, I));
661 }
662
663 // In other cases where the source or destination are illegal, assume
664 // the operation will get scalarized.
665 unsigned Num = Dst->getVectorNumElements();
666 unsigned Cost = static_cast<T *>(this)->getCastInstrCost(
667 Opcode, Dst->getScalarType(), Src->getScalarType(), I);
668
669 // Return the cost of multiple scalar invocation plus the cost of
670 // inserting and extracting the values.
671 return getScalarizationOverhead(Dst, true, true) + Num * Cost;
672 }
673
674 // We already handled vector-to-vector and scalar-to-scalar conversions.
675 // This
676 // is where we handle bitcast between vectors and scalars. We need to assume
677 // that the conversion is scalarized in one way or another.
678 if (Opcode == Instruction::BitCast)
679 // Illegal bitcasts are done by storing and loading from a stack slot.
680 return (Src->isVectorTy() ? getScalarizationOverhead(Src, false, true)
681 : 0) +
682 (Dst->isVectorTy() ? getScalarizationOverhead(Dst, true, false)
683 : 0);
684
685 llvm_unreachable("Unhandled cast")::llvm::llvm_unreachable_internal("Unhandled cast", "/build/llvm-toolchain-snapshot-7~svn329677/include/llvm/CodeGen/BasicTTIImpl.h"
, 685)
;
686 }
687
688 unsigned getExtractWithExtendCost(unsigned Opcode, Type *Dst,
689 VectorType *VecTy, unsigned Index) {
690 return static_cast<T *>(this)->getVectorInstrCost(
691 Instruction::ExtractElement, VecTy, Index) +
692 static_cast<T *>(this)->getCastInstrCost(Opcode, Dst,
693 VecTy->getElementType());
694 }
695
696 unsigned getCFInstrCost(unsigned Opcode) {
697 // Branches are assumed to be predicted.
698 return 0;
699 }
700
701 unsigned getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy,
702 const Instruction *I) {
703 const TargetLoweringBase *TLI = getTLI();
704 int ISD = TLI->InstructionOpcodeToISD(Opcode);
705 assert(ISD && "Invalid opcode")(static_cast <bool> (ISD && "Invalid opcode") ?
void (0) : __assert_fail ("ISD && \"Invalid opcode\""
, "/build/llvm-toolchain-snapshot-7~svn329677/include/llvm/CodeGen/BasicTTIImpl.h"
, 705, __extension__ __PRETTY_FUNCTION__))
;
706
707 // Selects on vectors are actually vector selects.
708 if (ISD == ISD::SELECT) {
709 assert(CondTy && "CondTy must exist")(static_cast <bool> (CondTy && "CondTy must exist"
) ? void (0) : __assert_fail ("CondTy && \"CondTy must exist\""
, "/build/llvm-toolchain-snapshot-7~svn329677/include/llvm/CodeGen/BasicTTIImpl.h"
, 709, __extension__ __PRETTY_FUNCTION__))
;
710 if (CondTy->isVectorTy())
711 ISD = ISD::VSELECT;
712 }
713 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy);
714
715 if (!(ValTy->isVectorTy() && !LT.second.isVector()) &&
716 !TLI->isOperationExpand(ISD, LT.second)) {
717 // The operation is legal. Assume it costs 1. Multiply
718 // by the type-legalization overhead.
719 return LT.first * 1;
720 }
721
722 // Otherwise, assume that the cast is scalarized.
723 // TODO: If one of the types get legalized by splitting, handle this
724 // similarly to what getCastInstrCost() does.
725 if (ValTy->isVectorTy()) {
726 unsigned Num = ValTy->getVectorNumElements();
727 if (CondTy)
728 CondTy = CondTy->getScalarType();
729 unsigned Cost = static_cast<T *>(this)->getCmpSelInstrCost(
730 Opcode, ValTy->getScalarType(), CondTy, I);
731
732 // Return the cost of multiple scalar invocation plus the cost of
733 // inserting and extracting the values.
734 return getScalarizationOverhead(ValTy, true, false) + Num * Cost;
735 }
736
737 // Unknown scalar opcode.
738 return 1;
739 }
740
741 unsigned getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index) {
742 std::pair<unsigned, MVT> LT =
743 getTLI()->getTypeLegalizationCost(DL, Val->getScalarType());
744
745 return LT.first;
746 }
747
748 unsigned getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment,
749 unsigned AddressSpace, const Instruction *I = nullptr) {
750 assert(!Src->isVoidTy() && "Invalid type")(static_cast <bool> (!Src->isVoidTy() && "Invalid type"
) ? void (0) : __assert_fail ("!Src->isVoidTy() && \"Invalid type\""
, "/build/llvm-toolchain-snapshot-7~svn329677/include/llvm/CodeGen/BasicTTIImpl.h"
, 750, __extension__ __PRETTY_FUNCTION__))
;
751 std::pair<unsigned, MVT> LT = getTLI()->getTypeLegalizationCost(DL, Src);
752
753 // Assuming that all loads of legal types cost 1.
754 unsigned Cost = LT.first;
755
756 if (Src->isVectorTy() &&
757 Src->getPrimitiveSizeInBits() < LT.second.getSizeInBits()) {
758 // This is a vector load that legalizes to a larger type than the vector
759 // itself. Unless the corresponding extending load or truncating store is
760 // legal, then this will scalarize.
761 TargetLowering::LegalizeAction LA = TargetLowering::Expand;
762 EVT MemVT = getTLI()->getValueType(DL, Src);
763 if (Opcode == Instruction::Store)
764 LA = getTLI()->getTruncStoreAction(LT.second, MemVT);
765 else
766 LA = getTLI()->getLoadExtAction(ISD::EXTLOAD, LT.second, MemVT);
767
768 if (LA != TargetLowering::Legal && LA != TargetLowering::Custom) {
769 // This is a vector load/store for some illegal type that is scalarized.
770 // We must account for the cost of building or decomposing the vector.
771 Cost += getScalarizationOverhead(Src, Opcode != Instruction::Store,
772 Opcode == Instruction::Store);
773 }
774 }
775
776 return Cost;
777 }
778
779 unsigned getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy,
780 unsigned Factor,
781 ArrayRef<unsigned> Indices,
782 unsigned Alignment,
783 unsigned AddressSpace) {
784 VectorType *VT = dyn_cast<VectorType>(VecTy);
785 assert(VT && "Expect a vector type for interleaved memory op")(static_cast <bool> (VT && "Expect a vector type for interleaved memory op"
) ? void (0) : __assert_fail ("VT && \"Expect a vector type for interleaved memory op\""
, "/build/llvm-toolchain-snapshot-7~svn329677/include/llvm/CodeGen/BasicTTIImpl.h"
, 785, __extension__ __PRETTY_FUNCTION__))
;
786
787 unsigned NumElts = VT->getNumElements();
788 assert(Factor > 1 && NumElts % Factor == 0 && "Invalid interleave factor")(static_cast <bool> (Factor > 1 && NumElts %
Factor == 0 && "Invalid interleave factor") ? void (
0) : __assert_fail ("Factor > 1 && NumElts % Factor == 0 && \"Invalid interleave factor\""
, "/build/llvm-toolchain-snapshot-7~svn329677/include/llvm/CodeGen/BasicTTIImpl.h"
, 788, __extension__ __PRETTY_FUNCTION__))
;
789
790 unsigned NumSubElts = NumElts / Factor;
791 VectorType *SubVT = VectorType::get(VT->getElementType(), NumSubElts);
792
793 // Firstly, the cost of load/store operation.
794 unsigned Cost = static_cast<T *>(this)->getMemoryOpCost(
795 Opcode, VecTy, Alignment, AddressSpace);
796
797 // Legalize the vector type, and get the legalized and unlegalized type
798 // sizes.
799 MVT VecTyLT = getTLI()->getTypeLegalizationCost(DL, VecTy).second;
800 unsigned VecTySize =
801 static_cast<T *>(this)->getDataLayout().getTypeStoreSize(VecTy);
802 unsigned VecTyLTSize = VecTyLT.getStoreSize();
803
804 // Return the ceiling of dividing A by B.
805 auto ceil = [](unsigned A, unsigned B) { return (A + B - 1) / B; };
806
807 // Scale the cost of the memory operation by the fraction of legalized
808 // instructions that will actually be used. We shouldn't account for the
809 // cost of dead instructions since they will be removed.
810 //
811 // E.g., An interleaved load of factor 8:
812 // %vec = load <16 x i64>, <16 x i64>* %ptr
813 // %v0 = shufflevector %vec, undef, <0, 8>
814 //
815 // If <16 x i64> is legalized to 8 v2i64 loads, only 2 of the loads will be
816 // used (those corresponding to elements [0:1] and [8:9] of the unlegalized
817 // type). The other loads are unused.
818 //
819 // We only scale the cost of loads since interleaved store groups aren't
820 // allowed to have gaps.
821 if (Opcode == Instruction::Load && VecTySize > VecTyLTSize) {
822 // The number of loads of a legal type it will take to represent a load
823 // of the unlegalized vector type.
824 unsigned NumLegalInsts = ceil(VecTySize, VecTyLTSize);
825
826 // The number of elements of the unlegalized type that correspond to a
827 // single legal instruction.
828 unsigned NumEltsPerLegalInst = ceil(NumElts, NumLegalInsts);
829
830 // Determine which legal instructions will be used.
831 BitVector UsedInsts(NumLegalInsts, false);
832 for (unsigned Index : Indices)
833 for (unsigned Elt = 0; Elt < NumSubElts; ++Elt)
834 UsedInsts.set((Index + Elt * Factor) / NumEltsPerLegalInst);
835
836 // Scale the cost of the load by the fraction of legal instructions that
837 // will be used.
838 Cost *= UsedInsts.count() / NumLegalInsts;
839 }
840
841 // Then plus the cost of interleave operation.
842 if (Opcode == Instruction::Load) {
843 // The interleave cost is similar to extract sub vectors' elements
844 // from the wide vector, and insert them into sub vectors.
845 //
846 // E.g. An interleaved load of factor 2 (with one member of index 0):
847 // %vec = load <8 x i32>, <8 x i32>* %ptr
848 // %v0 = shuffle %vec, undef, <0, 2, 4, 6> ; Index 0
849 // The cost is estimated as extract elements at 0, 2, 4, 6 from the
850 // <8 x i32> vector and insert them into a <4 x i32> vector.
851
852 assert(Indices.size() <= Factor &&(static_cast <bool> (Indices.size() <= Factor &&
"Interleaved memory op has too many members") ? void (0) : __assert_fail
("Indices.size() <= Factor && \"Interleaved memory op has too many members\""
, "/build/llvm-toolchain-snapshot-7~svn329677/include/llvm/CodeGen/BasicTTIImpl.h"
, 853, __extension__ __PRETTY_FUNCTION__))
853 "Interleaved memory op has too many members")(static_cast <bool> (Indices.size() <= Factor &&
"Interleaved memory op has too many members") ? void (0) : __assert_fail
("Indices.size() <= Factor && \"Interleaved memory op has too many members\""
, "/build/llvm-toolchain-snapshot-7~svn329677/include/llvm/CodeGen/BasicTTIImpl.h"
, 853, __extension__ __PRETTY_FUNCTION__))
;
854
855 for (unsigned Index : Indices) {
856 assert(Index < Factor && "Invalid index for interleaved memory op")(static_cast <bool> (Index < Factor && "Invalid index for interleaved memory op"
) ? void (0) : __assert_fail ("Index < Factor && \"Invalid index for interleaved memory op\""
, "/build/llvm-toolchain-snapshot-7~svn329677/include/llvm/CodeGen/BasicTTIImpl.h"
, 856, __extension__ __PRETTY_FUNCTION__))
;
857
858 // Extract elements from loaded vector for each sub vector.
859 for (unsigned i = 0; i < NumSubElts; i++)
860 Cost += static_cast<T *>(this)->getVectorInstrCost(
861 Instruction::ExtractElement, VT, Index + i * Factor);
862 }
863
864 unsigned InsSubCost = 0;
865 for (unsigned i = 0; i < NumSubElts; i++)
866 InsSubCost += static_cast<T *>(this)->getVectorInstrCost(
867 Instruction::InsertElement, SubVT, i);
868
869 Cost += Indices.size() * InsSubCost;
870 } else {
871 // The interleave cost is extract all elements from sub vectors, and
872 // insert them into the wide vector.
873 //
874 // E.g. An interleaved store of factor 2:
875 // %v0_v1 = shuffle %v0, %v1, <0, 4, 1, 5, 2, 6, 3, 7>
876 // store <8 x i32> %interleaved.vec, <8 x i32>* %ptr
877 // The cost is estimated as extract all elements from both <4 x i32>
878 // vectors and insert into the <8 x i32> vector.
879
880 unsigned ExtSubCost = 0;
881 for (unsigned i = 0; i < NumSubElts; i++)
882 ExtSubCost += static_cast<T *>(this)->getVectorInstrCost(
883 Instruction::ExtractElement, SubVT, i);
884 Cost += ExtSubCost * Factor;
885
886 for (unsigned i = 0; i < NumElts; i++)
887 Cost += static_cast<T *>(this)
888 ->getVectorInstrCost(Instruction::InsertElement, VT, i);
889 }
890
891 return Cost;
892 }
893
894 /// Get intrinsic cost based on arguments.
895 unsigned getIntrinsicInstrCost(Intrinsic::ID IID, Type *RetTy,
896 ArrayRef<Value *> Args, FastMathFlags FMF,
897 unsigned VF = 1) {
898 unsigned RetVF = (RetTy->isVectorTy() ? RetTy->getVectorNumElements() : 1);
899 assert((RetVF == 1 || VF == 1) && "VF > 1 and RetVF is a vector type")(static_cast <bool> ((RetVF == 1 || VF == 1) &&
"VF > 1 and RetVF is a vector type") ? void (0) : __assert_fail
("(RetVF == 1 || VF == 1) && \"VF > 1 and RetVF is a vector type\""
, "/build/llvm-toolchain-snapshot-7~svn329677/include/llvm/CodeGen/BasicTTIImpl.h"
, 899, __extension__ __PRETTY_FUNCTION__))
;
900
901 switch (IID) {
902 default: {
903 // Assume that we need to scalarize this intrinsic.
904 SmallVector<Type *, 4> Types;
905 for (Value *Op : Args) {
906 Type *OpTy = Op->getType();
907 assert(VF == 1 || !OpTy->isVectorTy())(static_cast <bool> (VF == 1 || !OpTy->isVectorTy())
? void (0) : __assert_fail ("VF == 1 || !OpTy->isVectorTy()"
, "/build/llvm-toolchain-snapshot-7~svn329677/include/llvm/CodeGen/BasicTTIImpl.h"
, 907, __extension__ __PRETTY_FUNCTION__))
;
908 Types.push_back(VF == 1 ? OpTy : VectorType::get(OpTy, VF));
909 }
910
911 if (VF > 1 && !RetTy->isVoidTy())
912 RetTy = VectorType::get(RetTy, VF);
913
914 // Compute the scalarization overhead based on Args for a vector
915 // intrinsic. A vectorizer will pass a scalar RetTy and VF > 1, while
916 // CostModel will pass a vector RetTy and VF is 1.
917 unsigned ScalarizationCost = std::numeric_limits<unsigned>::max();
918 if (RetVF > 1 || VF > 1) {
919 ScalarizationCost = 0;
920 if (!RetTy->isVoidTy())
921 ScalarizationCost += getScalarizationOverhead(RetTy, true, false);
922 ScalarizationCost += getOperandsScalarizationOverhead(Args, VF);
923 }
924
925 return static_cast<T *>(this)->
926 getIntrinsicInstrCost(IID, RetTy, Types, FMF, ScalarizationCost);
927 }
928 case Intrinsic::masked_scatter: {
929 assert(VF == 1 && "Can't vectorize types here.")(static_cast <bool> (VF == 1 && "Can't vectorize types here."
) ? void (0) : __assert_fail ("VF == 1 && \"Can't vectorize types here.\""
, "/build/llvm-toolchain-snapshot-7~svn329677/include/llvm/CodeGen/BasicTTIImpl.h"
, 929, __extension__ __PRETTY_FUNCTION__))
;
930 Value *Mask = Args[3];
931 bool VarMask = !isa<Constant>(Mask);
932 unsigned Alignment = cast<ConstantInt>(Args[2])->getZExtValue();
933 return
934 static_cast<T *>(this)->getGatherScatterOpCost(Instruction::Store,
935 Args[0]->getType(),
936 Args[1], VarMask,
937 Alignment);
938 }
939 case Intrinsic::masked_gather: {
940 assert(VF == 1 && "Can't vectorize types here.")(static_cast <bool> (VF == 1 && "Can't vectorize types here."
) ? void (0) : __assert_fail ("VF == 1 && \"Can't vectorize types here.\""
, "/build/llvm-toolchain-snapshot-7~svn329677/include/llvm/CodeGen/BasicTTIImpl.h"
, 940, __extension__ __PRETTY_FUNCTION__))
;
941 Value *Mask = Args[2];
942 bool VarMask = !isa<Constant>(Mask);
943 unsigned Alignment = cast<ConstantInt>(Args[1])->getZExtValue();
944 return
945 static_cast<T *>(this)->getGatherScatterOpCost(Instruction::Load,
946 RetTy, Args[0], VarMask,
947 Alignment);
948 }
949 case Intrinsic::experimental_vector_reduce_add:
950 case Intrinsic::experimental_vector_reduce_mul:
951 case Intrinsic::experimental_vector_reduce_and:
952 case Intrinsic::experimental_vector_reduce_or:
953 case Intrinsic::experimental_vector_reduce_xor:
954 case Intrinsic::experimental_vector_reduce_fadd:
955 case Intrinsic::experimental_vector_reduce_fmul:
956 case Intrinsic::experimental_vector_reduce_smax:
957 case Intrinsic::experimental_vector_reduce_smin:
958 case Intrinsic::experimental_vector_reduce_fmax:
959 case Intrinsic::experimental_vector_reduce_fmin:
960 case Intrinsic::experimental_vector_reduce_umax:
961 case Intrinsic::experimental_vector_reduce_umin:
962 return getIntrinsicInstrCost(IID, RetTy, Args[0]->getType(), FMF);
963 }
964 }
965
966 /// Get intrinsic cost based on argument types.
967 /// If ScalarizationCostPassed is std::numeric_limits<unsigned>::max(), the
968 /// cost of scalarizing the arguments and the return value will be computed
969 /// based on types.
970 unsigned getIntrinsicInstrCost(
971 Intrinsic::ID IID, Type *RetTy, ArrayRef<Type *> Tys, FastMathFlags FMF,
972 unsigned ScalarizationCostPassed = std::numeric_limits<unsigned>::max()) {
973 SmallVector<unsigned, 2> ISDs;
974 unsigned SingleCallCost = 10; // Library call cost. Make it expensive.
975 switch (IID) {
976 default: {
977 // Assume that we need to scalarize this intrinsic.
978 unsigned ScalarizationCost = ScalarizationCostPassed;
979 unsigned ScalarCalls = 1;
980 Type *ScalarRetTy = RetTy;
981 if (RetTy->isVectorTy()) {
982 if (ScalarizationCostPassed == std::numeric_limits<unsigned>::max())
983 ScalarizationCost = getScalarizationOverhead(RetTy, true, false);
984 ScalarCalls = std::max(ScalarCalls, RetTy->getVectorNumElements());
985 ScalarRetTy = RetTy->getScalarType();
986 }
987 SmallVector<Type *, 4> ScalarTys;
988 for (unsigned i = 0, ie = Tys.size(); i != ie; ++i) {
989 Type *Ty = Tys[i];
990 if (Ty->isVectorTy()) {
991 if (ScalarizationCostPassed == std::numeric_limits<unsigned>::max())
992 ScalarizationCost += getScalarizationOverhead(Ty, false, true);
993 ScalarCalls = std::max(ScalarCalls, Ty->getVectorNumElements());
994 Ty = Ty->getScalarType();
995 }
996 ScalarTys.push_back(Ty);
997 }
998 if (ScalarCalls == 1)
999 return 1; // Return cost of a scalar intrinsic. Assume it to be cheap.
1000
1001 unsigned ScalarCost = static_cast<T *>(this)->getIntrinsicInstrCost(
1002 IID, ScalarRetTy, ScalarTys, FMF);
1003
1004 return ScalarCalls * ScalarCost + ScalarizationCost;
1005 }
1006 // Look for intrinsics that can be lowered directly or turned into a scalar
1007 // intrinsic call.
1008 case Intrinsic::sqrt:
1009 ISDs.push_back(ISD::FSQRT);
1010 break;
1011 case Intrinsic::sin:
1012 ISDs.push_back(ISD::FSIN);
1013 break;
1014 case Intrinsic::cos:
1015 ISDs.push_back(ISD::FCOS);
1016 break;
1017 case Intrinsic::exp:
1018 ISDs.push_back(ISD::FEXP);
1019 break;
1020 case Intrinsic::exp2:
1021 ISDs.push_back(ISD::FEXP2);
1022 break;
1023 case Intrinsic::log:
1024 ISDs.push_back(ISD::FLOG);
1025 break;
1026 case Intrinsic::log10:
1027 ISDs.push_back(ISD::FLOG10);
1028 break;
1029 case Intrinsic::log2:
1030 ISDs.push_back(ISD::FLOG2);
1031 break;
1032 case Intrinsic::fabs:
1033 ISDs.push_back(ISD::FABS);
1034 break;
1035 case Intrinsic::minnum:
1036 ISDs.push_back(ISD::FMINNUM);
1037 if (FMF.noNaNs())
1038 ISDs.push_back(ISD::FMINNAN);
1039 break;
1040 case Intrinsic::maxnum:
1041 ISDs.push_back(ISD::FMAXNUM);
1042 if (FMF.noNaNs())
1043 ISDs.push_back(ISD::FMAXNAN);
1044 break;
1045 case Intrinsic::copysign:
1046 ISDs.push_back(ISD::FCOPYSIGN);
1047 break;
1048 case Intrinsic::floor:
1049 ISDs.push_back(ISD::FFLOOR);
1050 break;
1051 case Intrinsic::ceil:
1052 ISDs.push_back(ISD::FCEIL);
1053 break;
1054 case Intrinsic::trunc:
1055 ISDs.push_back(ISD::FTRUNC);
1056 break;
1057 case Intrinsic::nearbyint:
1058 ISDs.push_back(ISD::FNEARBYINT);
1059 break;
1060 case Intrinsic::rint:
1061 ISDs.push_back(ISD::FRINT);
1062 break;
1063 case Intrinsic::round:
1064 ISDs.push_back(ISD::FROUND);
1065 break;
1066 case Intrinsic::pow:
1067 ISDs.push_back(ISD::FPOW);
1068 break;
1069 case Intrinsic::fma:
1070 ISDs.push_back(ISD::FMA);
1071 break;
1072 case Intrinsic::fmuladd:
1073 ISDs.push_back(ISD::FMA);
1074 break;
1075 // FIXME: We should return 0 whenever getIntrinsicCost == TCC_Free.
1076 case Intrinsic::lifetime_start:
1077 case Intrinsic::lifetime_end:
1078 case Intrinsic::sideeffect:
1079 return 0;
1080 case Intrinsic::masked_store:
1081 return static_cast<T *>(this)
1082 ->getMaskedMemoryOpCost(Instruction::Store, Tys[0], 0, 0);
1083 case Intrinsic::masked_load:
1084 return static_cast<T *>(this)
1085 ->getMaskedMemoryOpCost(Instruction::Load, RetTy, 0, 0);
1086 case Intrinsic::experimental_vector_reduce_add:
1087 return static_cast<T *>(this)->getArithmeticReductionCost(
1088 Instruction::Add, Tys[0], /*IsPairwiseForm=*/false);
1089 case Intrinsic::experimental_vector_reduce_mul:
1090 return static_cast<T *>(this)->getArithmeticReductionCost(
1091 Instruction::Mul, Tys[0], /*IsPairwiseForm=*/false);
1092 case Intrinsic::experimental_vector_reduce_and:
1093 return static_cast<T *>(this)->getArithmeticReductionCost(
1094 Instruction::And, Tys[0], /*IsPairwiseForm=*/false);
1095 case Intrinsic::experimental_vector_reduce_or:
1096 return static_cast<T *>(this)->getArithmeticReductionCost(
1097 Instruction::Or, Tys[0], /*IsPairwiseForm=*/false);
1098 case Intrinsic::experimental_vector_reduce_xor:
1099 return static_cast<T *>(this)->getArithmeticReductionCost(
1100 Instruction::Xor, Tys[0], /*IsPairwiseForm=*/false);
1101 case Intrinsic::experimental_vector_reduce_fadd:
1102 return static_cast<T *>(this)->getArithmeticReductionCost(
1103 Instruction::FAdd, Tys[0], /*IsPairwiseForm=*/false);
1104 case Intrinsic::experimental_vector_reduce_fmul:
1105 return static_cast<T *>(this)->getArithmeticReductionCost(
1106 Instruction::FMul, Tys[0], /*IsPairwiseForm=*/false);
1107 case Intrinsic::experimental_vector_reduce_smax:
1108 case Intrinsic::experimental_vector_reduce_smin:
1109 case Intrinsic::experimental_vector_reduce_fmax:
1110 case Intrinsic::experimental_vector_reduce_fmin:
1111 return static_cast<T *>(this)->getMinMaxReductionCost(
1112 Tys[0], CmpInst::makeCmpResultType(Tys[0]), /*IsPairwiseForm=*/false,
1113 /*IsSigned=*/true);
1114 case Intrinsic::experimental_vector_reduce_umax:
1115 case Intrinsic::experimental_vector_reduce_umin:
1116 return static_cast<T *>(this)->getMinMaxReductionCost(
1117 Tys[0], CmpInst::makeCmpResultType(Tys[0]), /*IsPairwiseForm=*/false,
1118 /*IsSigned=*/false);
1119 case Intrinsic::ctpop:
1120 ISDs.push_back(ISD::CTPOP);
1121 // In case of legalization use TCC_Expensive. This is cheaper than a
1122 // library call but still not a cheap instruction.
1123 SingleCallCost = TargetTransformInfo::TCC_Expensive;
1124 break;
1125 // FIXME: ctlz, cttz, ...
1126 }
1127
1128 const TargetLoweringBase *TLI = getTLI();
1129 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(DL, RetTy);
1130
1131 SmallVector<unsigned, 2> LegalCost;
1132 SmallVector<unsigned, 2> CustomCost;
1133 for (unsigned ISD : ISDs) {
1134 if (TLI->isOperationLegalOrPromote(ISD, LT.second)) {
1135 if (IID == Intrinsic::fabs && TLI->isFAbsFree(LT.second)) {
1136 return 0;
1137 }
1138
1139 // The operation is legal. Assume it costs 1.
1140 // If the type is split to multiple registers, assume that there is some
1141 // overhead to this.
1142 // TODO: Once we have extract/insert subvector cost we need to use them.
1143 if (LT.first > 1)
1144 LegalCost.push_back(LT.first * 2);
1145 else
1146 LegalCost.push_back(LT.first * 1);
1147 } else if (!TLI->isOperationExpand(ISD, LT.second)) {
1148 // If the operation is custom lowered then assume
1149 // that the code is twice as expensive.
1150 CustomCost.push_back(LT.first * 2);
1151 }
1152 }
1153
1154 auto MinLegalCostI = std::min_element(LegalCost.begin(), LegalCost.end());
1155 if (MinLegalCostI != LegalCost.end())
1156 return *MinLegalCostI;
1157
1158 auto MinCustomCostI = std::min_element(CustomCost.begin(), CustomCost.end());
1159 if (MinCustomCostI != CustomCost.end())
1160 return *MinCustomCostI;
1161
1162 // If we can't lower fmuladd into an FMA estimate the cost as a floating
1163 // point mul followed by an add.
1164 if (IID == Intrinsic::fmuladd)
1165 return static_cast<T *>(this)
1166 ->getArithmeticInstrCost(BinaryOperator::FMul, RetTy) +
1167 static_cast<T *>(this)
1168 ->getArithmeticInstrCost(BinaryOperator::FAdd, RetTy);
1169
1170 // Else, assume that we need to scalarize this intrinsic. For math builtins
1171 // this will emit a costly libcall, adding call overhead and spills. Make it
1172 // very expensive.
1173 if (RetTy->isVectorTy()) {
1174 unsigned ScalarizationCost =
1175 ((ScalarizationCostPassed != std::numeric_limits<unsigned>::max())
1176 ? ScalarizationCostPassed
1177 : getScalarizationOverhead(RetTy, true, false));
1178 unsigned ScalarCalls = RetTy->getVectorNumElements();
1179 SmallVector<Type *, 4> ScalarTys;
1180 for (unsigned i = 0, ie = Tys.size(); i != ie; ++i) {
1181 Type *Ty = Tys[i];
1182 if (Ty->isVectorTy())
1183 Ty = Ty->getScalarType();
1184 ScalarTys.push_back(Ty);
1185 }
1186 unsigned ScalarCost = static_cast<T *>(this)->getIntrinsicInstrCost(
1187 IID, RetTy->getScalarType(), ScalarTys, FMF);
1188 for (unsigned i = 0, ie = Tys.size(); i != ie; ++i) {
1189 if (Tys[i]->isVectorTy()) {
1190 if (ScalarizationCostPassed == std::numeric_limits<unsigned>::max())
1191 ScalarizationCost += getScalarizationOverhead(Tys[i], false, true);
1192 ScalarCalls = std::max(ScalarCalls, Tys[i]->getVectorNumElements());
1193 }
1194 }
1195
1196 return ScalarCalls * ScalarCost + ScalarizationCost;
1197 }
1198
1199 // This is going to be turned into a library call, make it expensive.
1200 return SingleCallCost;
1201 }
1202
1203 /// \brief Compute a cost of the given call instruction.
1204 ///
1205 /// Compute the cost of calling function F with return type RetTy and
1206 /// argument types Tys. F might be nullptr, in this case the cost of an
1207 /// arbitrary call with the specified signature will be returned.
1208 /// This is used, for instance, when we estimate call of a vector
1209 /// counterpart of the given function.
1210 /// \param F Called function, might be nullptr.
1211 /// \param RetTy Return value types.
1212 /// \param Tys Argument types.
1213 /// \returns The cost of Call instruction.
1214 unsigned getCallInstrCost(Function *F, Type *RetTy, ArrayRef<Type *> Tys) {
1215 return 10;
1216 }
1217
1218 unsigned getNumberOfParts(Type *Tp) {
1219 std::pair<unsigned, MVT> LT = getTLI()->getTypeLegalizationCost(DL, Tp);
1220 return LT.first;
1221 }
1222
1223 unsigned getAddressComputationCost(Type *Ty, ScalarEvolution *,
1224 const SCEV *) {
1225 return 0;
1226 }
1227
1228 /// Try to calculate arithmetic and shuffle op costs for reduction operations.
1229 /// We're assuming that reduction operation are performing the following way:
1230 /// 1. Non-pairwise reduction
1231 /// %val1 = shufflevector<n x t> %val, <n x t> %undef,
1232 /// <n x i32> <i32 n/2, i32 n/2 + 1, ..., i32 n, i32 undef, ..., i32 undef>
1233 /// \----------------v-------------/ \----------v------------/
1234 /// n/2 elements n/2 elements
1235 /// %red1 = op <n x t> %val, <n x t> val1
1236 /// After this operation we have a vector %red1 where only the first n/2
1237 /// elements are meaningful, the second n/2 elements are undefined and can be
1238 /// dropped. All other operations are actually working with the vector of
1239 /// length n/2, not n, though the real vector length is still n.
1240 /// %val2 = shufflevector<n x t> %red1, <n x t> %undef,
1241 /// <n x i32> <i32 n/4, i32 n/4 + 1, ..., i32 n/2, i32 undef, ..., i32 undef>
1242 /// \----------------v-------------/ \----------v------------/
1243 /// n/4 elements 3*n/4 elements
1244 /// %red2 = op <n x t> %red1, <n x t> val2 - working with the vector of
1245 /// length n/2, the resulting vector has length n/4 etc.
1246 /// 2. Pairwise reduction:
1247 /// Everything is the same except for an additional shuffle operation which
1248 /// is used to produce operands for pairwise kind of reductions.
1249 /// %val1 = shufflevector<n x t> %val, <n x t> %undef,
1250 /// <n x i32> <i32 0, i32 2, ..., i32 n-2, i32 undef, ..., i32 undef>
1251 /// \-------------v----------/ \----------v------------/
1252 /// n/2 elements n/2 elements
1253 /// %val2 = shufflevector<n x t> %val, <n x t> %undef,
1254 /// <n x i32> <i32 1, i32 3, ..., i32 n-1, i32 undef, ..., i32 undef>
1255 /// \-------------v----------/ \----------v------------/
1256 /// n/2 elements n/2 elements
1257 /// %red1 = op <n x t> %val1, <n x t> val2
1258 /// Again, the operation is performed on <n x t> vector, but the resulting
1259 /// vector %red1 is <n/2 x t> vector.
1260 ///
1261 /// The cost model should take into account that the actual length of the
1262 /// vector is reduced on each iteration.
1263 unsigned getArithmeticReductionCost(unsigned Opcode, Type *Ty,
1264 bool IsPairwise) {
1265 assert(Ty->isVectorTy() && "Expect a vector type")(static_cast <bool> (Ty->isVectorTy() && "Expect a vector type"
) ? void (0) : __assert_fail ("Ty->isVectorTy() && \"Expect a vector type\""
, "/build/llvm-toolchain-snapshot-7~svn329677/include/llvm/CodeGen/BasicTTIImpl.h"
, 1265, __extension__ __PRETTY_FUNCTION__))
;
1266 Type *ScalarTy = Ty->getVectorElementType();
1267 unsigned NumVecElts = Ty->getVectorNumElements();
1268 unsigned NumReduxLevels = Log2_32(NumVecElts);
1269 unsigned ArithCost = 0;
1270 unsigned ShuffleCost = 0;
1271 auto *ConcreteTTI = static_cast<T *>(this);
1272 std::pair<unsigned, MVT> LT =
1273 ConcreteTTI->getTLI()->getTypeLegalizationCost(DL, Ty);
1274 unsigned LongVectorCount = 0;
1275 unsigned MVTLen =
1276 LT.second.isVector() ? LT.second.getVectorNumElements() : 1;
1277 while (NumVecElts > MVTLen) {
1278 NumVecElts /= 2;
1279 // Assume the pairwise shuffles add a cost.
1280 ShuffleCost += (IsPairwise + 1) *
1281 ConcreteTTI->getShuffleCost(TTI::SK_ExtractSubvector, Ty,
1282 NumVecElts, Ty);
1283 ArithCost += ConcreteTTI->getArithmeticInstrCost(Opcode, Ty);
1284 Ty = VectorType::get(ScalarTy, NumVecElts);
1285 ++LongVectorCount;
1286 }
1287 // The minimal length of the vector is limited by the real length of vector
1288 // operations performed on the current platform. That's why several final
1289 // reduction operations are performed on the vectors with the same
1290 // architecture-dependent length.
1291 ShuffleCost += (NumReduxLevels - LongVectorCount) * (IsPairwise + 1) *
1292 ConcreteTTI->getShuffleCost(TTI::SK_ExtractSubvector, Ty,
1293 NumVecElts, Ty);
1294 ArithCost += (NumReduxLevels - LongVectorCount) *
1295 ConcreteTTI->getArithmeticInstrCost(Opcode, Ty);
1296 return ShuffleCost + ArithCost + getScalarizationOverhead(Ty, false, true);
1297 }
1298
1299 /// Try to calculate op costs for min/max reduction operations.
1300 /// \param CondTy Conditional type for the Select instruction.
1301 unsigned getMinMaxReductionCost(Type *Ty, Type *CondTy, bool IsPairwise,
1302 bool) {
1303 assert(Ty->isVectorTy() && "Expect a vector type")(static_cast <bool> (Ty->isVectorTy() && "Expect a vector type"
) ? void (0) : __assert_fail ("Ty->isVectorTy() && \"Expect a vector type\""
, "/build/llvm-toolchain-snapshot-7~svn329677/include/llvm/CodeGen/BasicTTIImpl.h"
, 1303, __extension__ __PRETTY_FUNCTION__))
;
1304 Type *ScalarTy = Ty->getVectorElementType();
1305 Type *ScalarCondTy = CondTy->getVectorElementType();
1306 unsigned NumVecElts = Ty->getVectorNumElements();
1307 unsigned NumReduxLevels = Log2_32(NumVecElts);
1308 unsigned CmpOpcode;
1309 if (Ty->isFPOrFPVectorTy()) {
1310 CmpOpcode = Instruction::FCmp;
1311 } else {
1312 assert(Ty->isIntOrIntVectorTy() &&(static_cast <bool> (Ty->isIntOrIntVectorTy() &&
"expecting floating point or integer type for min/max reduction"
) ? void (0) : __assert_fail ("Ty->isIntOrIntVectorTy() && \"expecting floating point or integer type for min/max reduction\""
, "/build/llvm-toolchain-snapshot-7~svn329677/include/llvm/CodeGen/BasicTTIImpl.h"
, 1313, __extension__ __PRETTY_FUNCTION__))
1313 "expecting floating point or integer type for min/max reduction")(static_cast <bool> (Ty->isIntOrIntVectorTy() &&
"expecting floating point or integer type for min/max reduction"
) ? void (0) : __assert_fail ("Ty->isIntOrIntVectorTy() && \"expecting floating point or integer type for min/max reduction\""
, "/build/llvm-toolchain-snapshot-7~svn329677/include/llvm/CodeGen/BasicTTIImpl.h"
, 1313, __extension__ __PRETTY_FUNCTION__))
;
1314 CmpOpcode = Instruction::ICmp;
1315 }
1316 unsigned MinMaxCost = 0;
1317 unsigned ShuffleCost = 0;
1318 auto *ConcreteTTI = static_cast<T *>(this);
1319 std::pair<unsigned, MVT> LT =
1320 ConcreteTTI->getTLI()->getTypeLegalizationCost(DL, Ty);
1321 unsigned LongVectorCount = 0;
1322 unsigned MVTLen =
1323 LT.second.isVector() ? LT.second.getVectorNumElements() : 1;
1324 while (NumVecElts > MVTLen) {
1325 NumVecElts /= 2;
1326 // Assume the pairwise shuffles add a cost.
1327 ShuffleCost += (IsPairwise + 1) *
1328 ConcreteTTI->getShuffleCost(TTI::SK_ExtractSubvector, Ty,
1329 NumVecElts, Ty);
1330 MinMaxCost +=
1331 ConcreteTTI->getCmpSelInstrCost(CmpOpcode, Ty, CondTy, nullptr) +
1332 ConcreteTTI->getCmpSelInstrCost(Instruction::Select, Ty, CondTy,
1333 nullptr);
1334 Ty = VectorType::get(ScalarTy, NumVecElts);
1335 CondTy = VectorType::get(ScalarCondTy, NumVecElts);
1336 ++LongVectorCount;
1337 }
1338 // The minimal length of the vector is limited by the real length of vector
1339 // operations performed on the current platform. That's why several final
1340 // reduction opertions are perfomed on the vectors with the same
1341 // architecture-dependent length.
1342 ShuffleCost += (NumReduxLevels - LongVectorCount) * (IsPairwise + 1) *
1343 ConcreteTTI->getShuffleCost(TTI::SK_ExtractSubvector, Ty,
1344 NumVecElts, Ty);
1345 MinMaxCost +=
1346 (NumReduxLevels - LongVectorCount) *
1347 (ConcreteTTI->getCmpSelInstrCost(CmpOpcode, Ty, CondTy, nullptr) +
1348 ConcreteTTI->getCmpSelInstrCost(Instruction::Select, Ty, CondTy,
1349 nullptr));
1350 // Need 3 extractelement instructions for scalarization + an additional
1351 // scalar select instruction.
1352 return ShuffleCost + MinMaxCost +
1353 3 * getScalarizationOverhead(Ty, /*Insert=*/false,
1354 /*Extract=*/true) +
1355 ConcreteTTI->getCmpSelInstrCost(Instruction::Select, ScalarTy,
1356 ScalarCondTy, nullptr);
1357 }
1358
1359 unsigned getVectorSplitCost() { return 1; }
1360
1361 /// @}
1362};
1363
1364/// \brief Concrete BasicTTIImpl that can be used if no further customization
1365/// is needed.
1366class BasicTTIImpl : public BasicTTIImplBase<BasicTTIImpl> {
1367 using BaseT = BasicTTIImplBase<BasicTTIImpl>;
1368
1369 friend class BasicTTIImplBase<BasicTTIImpl>;
1370
1371 const TargetSubtargetInfo *ST;
1372 const TargetLoweringBase *TLI;
1373
1374 const TargetSubtargetInfo *getST() const { return ST; }
1375 const TargetLoweringBase *getTLI() const { return TLI; }
1376
1377public:
1378 explicit BasicTTIImpl(const TargetMachine *ST, const Function &F);
1379};
1380
1381} // end namespace llvm
1382
1383#endif // LLVM_CODEGEN_BASICTTIIMPL_H