Bug Summary

File:include/llvm/Analysis/TargetTransformInfoImpl.h
Warning:line 77, column 25
Called C++ object pointer is null

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clang -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name X86TargetTransformInfo.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mthread-model posix -fmath-errno -masm-verbose -mconstructor-aliases -munwind-tables -fuse-init-array -target-cpu x86-64 -dwarf-column-info -debugger-tuning=gdb -momit-leaf-frame-pointer -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-8/lib/clang/8.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-8~svn350071/build-llvm/lib/Target/X86 -I /build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86 -I /build/llvm-toolchain-snapshot-8~svn350071/build-llvm/include -I /build/llvm-toolchain-snapshot-8~svn350071/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0/backward -internal-isystem /usr/include/clang/8.0.0/include/ -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-8/lib/clang/8.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++11 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-8~svn350071/build-llvm/lib/Target/X86 -fdebug-prefix-map=/build/llvm-toolchain-snapshot-8~svn350071=. -ferror-limit 19 -fmessage-length 0 -fvisibility-inlines-hidden -stack-protector 2 -fobjc-runtime=gcc -fdiagnostics-show-option -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -o /tmp/scan-build-2018-12-27-042839-1215-1 -x c++ /build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86TargetTransformInfo.cpp -faddrsig

/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86TargetTransformInfo.cpp

1//===-- X86TargetTransformInfo.cpp - X86 specific TTI pass ----------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9/// \file
10/// This file implements a TargetTransformInfo analysis pass specific to the
11/// X86 target machine. It uses the target's detailed information to provide
12/// more precise answers to certain TTI queries, while letting the target
13/// independent and default TTI implementations handle the rest.
14///
15//===----------------------------------------------------------------------===//
16/// About Cost Model numbers used below it's necessary to say the following:
17/// the numbers correspond to some "generic" X86 CPU instead of usage of
18/// concrete CPU model. Usually the numbers correspond to CPU where the feature
19/// apeared at the first time. For example, if we do Subtarget.hasSSE42() in
20/// the lookups below the cost is based on Nehalem as that was the first CPU
21/// to support that feature level and thus has most likely the worst case cost.
22/// Some examples of other technologies/CPUs:
23/// SSE 3 - Pentium4 / Athlon64
24/// SSE 4.1 - Penryn
25/// SSE 4.2 - Nehalem
26/// AVX - Sandy Bridge
27/// AVX2 - Haswell
28/// AVX-512 - Xeon Phi / Skylake
29/// And some examples of instruction target dependent costs (latency)
30/// divss sqrtss rsqrtss
31/// AMD K7 11-16 19 3
32/// Piledriver 9-24 13-15 5
33/// Jaguar 14 16 2
34/// Pentium II,III 18 30 2
35/// Nehalem 7-14 7-18 3
36/// Haswell 10-13 11 5
37/// TODO: Develop and implement the target dependent cost model and
38/// specialize cost numbers for different Cost Model Targets such as throughput,
39/// code size, latency and uop count.
40//===----------------------------------------------------------------------===//
41
42#include "X86TargetTransformInfo.h"
43#include "llvm/Analysis/TargetTransformInfo.h"
44#include "llvm/CodeGen/BasicTTIImpl.h"
45#include "llvm/CodeGen/CostTable.h"
46#include "llvm/CodeGen/TargetLowering.h"
47#include "llvm/IR/IntrinsicInst.h"
48#include "llvm/Support/Debug.h"
49
50using namespace llvm;
51
52#define DEBUG_TYPE"x86tti" "x86tti"
53
54//===----------------------------------------------------------------------===//
55//
56// X86 cost model.
57//
58//===----------------------------------------------------------------------===//
59
60TargetTransformInfo::PopcntSupportKind
61X86TTIImpl::getPopcntSupport(unsigned TyWidth) {
62 assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2")((isPowerOf2_32(TyWidth) && "Ty width must be power of 2"
) ? static_cast<void> (0) : __assert_fail ("isPowerOf2_32(TyWidth) && \"Ty width must be power of 2\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86TargetTransformInfo.cpp"
, 62, __PRETTY_FUNCTION__))
;
63 // TODO: Currently the __builtin_popcount() implementation using SSE3
64 // instructions is inefficient. Once the problem is fixed, we should
65 // call ST->hasSSE3() instead of ST->hasPOPCNT().
66 return ST->hasPOPCNT() ? TTI::PSK_FastHardware : TTI::PSK_Software;
67}
68
69llvm::Optional<unsigned> X86TTIImpl::getCacheSize(
70 TargetTransformInfo::CacheLevel Level) const {
71 switch (Level) {
72 case TargetTransformInfo::CacheLevel::L1D:
73 // - Penryn
74 // - Nehalem
75 // - Westmere
76 // - Sandy Bridge
77 // - Ivy Bridge
78 // - Haswell
79 // - Broadwell
80 // - Skylake
81 // - Kabylake
82 return 32 * 1024; // 32 KByte
83 case TargetTransformInfo::CacheLevel::L2D:
84 // - Penryn
85 // - Nehalem
86 // - Westmere
87 // - Sandy Bridge
88 // - Ivy Bridge
89 // - Haswell
90 // - Broadwell
91 // - Skylake
92 // - Kabylake
93 return 256 * 1024; // 256 KByte
94 }
95
96 llvm_unreachable("Unknown TargetTransformInfo::CacheLevel")::llvm::llvm_unreachable_internal("Unknown TargetTransformInfo::CacheLevel"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86TargetTransformInfo.cpp"
, 96)
;
97}
98
99llvm::Optional<unsigned> X86TTIImpl::getCacheAssociativity(
100 TargetTransformInfo::CacheLevel Level) const {
101 // - Penryn
102 // - Nehalem
103 // - Westmere
104 // - Sandy Bridge
105 // - Ivy Bridge
106 // - Haswell
107 // - Broadwell
108 // - Skylake
109 // - Kabylake
110 switch (Level) {
111 case TargetTransformInfo::CacheLevel::L1D:
112 LLVM_FALLTHROUGH[[clang::fallthrough]];
113 case TargetTransformInfo::CacheLevel::L2D:
114 return 8;
115 }
116
117 llvm_unreachable("Unknown TargetTransformInfo::CacheLevel")::llvm::llvm_unreachable_internal("Unknown TargetTransformInfo::CacheLevel"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86TargetTransformInfo.cpp"
, 117)
;
118}
119
120unsigned X86TTIImpl::getNumberOfRegisters(bool Vector) {
121 if (Vector && !ST->hasSSE1())
122 return 0;
123
124 if (ST->is64Bit()) {
125 if (Vector && ST->hasAVX512())
126 return 32;
127 return 16;
128 }
129 return 8;
130}
131
132unsigned X86TTIImpl::getRegisterBitWidth(bool Vector) const {
133 unsigned PreferVectorWidth = ST->getPreferVectorWidth();
134 if (Vector) {
135 if (ST->hasAVX512() && PreferVectorWidth >= 512)
136 return 512;
137 if (ST->hasAVX() && PreferVectorWidth >= 256)
138 return 256;
139 if (ST->hasSSE1() && PreferVectorWidth >= 128)
140 return 128;
141 return 0;
142 }
143
144 if (ST->is64Bit())
145 return 64;
146
147 return 32;
148}
149
150unsigned X86TTIImpl::getLoadStoreVecRegBitWidth(unsigned) const {
151 return getRegisterBitWidth(true);
152}
153
154unsigned X86TTIImpl::getMaxInterleaveFactor(unsigned VF) {
155 // If the loop will not be vectorized, don't interleave the loop.
156 // Let regular unroll to unroll the loop, which saves the overflow
157 // check and memory check cost.
158 if (VF == 1)
159 return 1;
160
161 if (ST->isAtom())
162 return 1;
163
164 // Sandybridge and Haswell have multiple execution ports and pipelined
165 // vector units.
166 if (ST->hasAVX())
167 return 4;
168
169 return 2;
170}
171
172int X86TTIImpl::getArithmeticInstrCost(
173 unsigned Opcode, Type *Ty,
174 TTI::OperandValueKind Op1Info, TTI::OperandValueKind Op2Info,
175 TTI::OperandValueProperties Opd1PropInfo,
176 TTI::OperandValueProperties Opd2PropInfo,
177 ArrayRef<const Value *> Args) {
178 // Legalize the type.
179 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty);
180
181 int ISD = TLI->InstructionOpcodeToISD(Opcode);
182 assert(ISD && "Invalid opcode")((ISD && "Invalid opcode") ? static_cast<void> (
0) : __assert_fail ("ISD && \"Invalid opcode\"", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86TargetTransformInfo.cpp"
, 182, __PRETTY_FUNCTION__))
;
183
184 static const CostTblEntry GLMCostTable[] = {
185 { ISD::FDIV, MVT::f32, 18 }, // divss
186 { ISD::FDIV, MVT::v4f32, 35 }, // divps
187 { ISD::FDIV, MVT::f64, 33 }, // divsd
188 { ISD::FDIV, MVT::v2f64, 65 }, // divpd
189 };
190
191 if (ST->isGLM())
192 if (const auto *Entry = CostTableLookup(GLMCostTable, ISD,
193 LT.second))
194 return LT.first * Entry->Cost;
195
196 static const CostTblEntry SLMCostTable[] = {
197 { ISD::MUL, MVT::v4i32, 11 }, // pmulld
198 { ISD::MUL, MVT::v8i16, 2 }, // pmullw
199 { ISD::MUL, MVT::v16i8, 14 }, // extend/pmullw/trunc sequence.
200 { ISD::FMUL, MVT::f64, 2 }, // mulsd
201 { ISD::FMUL, MVT::v2f64, 4 }, // mulpd
202 { ISD::FMUL, MVT::v4f32, 2 }, // mulps
203 { ISD::FDIV, MVT::f32, 17 }, // divss
204 { ISD::FDIV, MVT::v4f32, 39 }, // divps
205 { ISD::FDIV, MVT::f64, 32 }, // divsd
206 { ISD::FDIV, MVT::v2f64, 69 }, // divpd
207 { ISD::FADD, MVT::v2f64, 2 }, // addpd
208 { ISD::FSUB, MVT::v2f64, 2 }, // subpd
209 // v2i64/v4i64 mul is custom lowered as a series of long:
210 // multiplies(3), shifts(3) and adds(2)
211 // slm muldq version throughput is 2 and addq throughput 4
212 // thus: 3X2 (muldq throughput) + 3X1 (shift throughput) +
213 // 3X4 (addq throughput) = 17
214 { ISD::MUL, MVT::v2i64, 17 },
215 // slm addq\subq throughput is 4
216 { ISD::ADD, MVT::v2i64, 4 },
217 { ISD::SUB, MVT::v2i64, 4 },
218 };
219
220 if (ST->isSLM()) {
221 if (Args.size() == 2 && ISD == ISD::MUL && LT.second == MVT::v4i32) {
222 // Check if the operands can be shrinked into a smaller datatype.
223 bool Op1Signed = false;
224 unsigned Op1MinSize = BaseT::minRequiredElementSize(Args[0], Op1Signed);
225 bool Op2Signed = false;
226 unsigned Op2MinSize = BaseT::minRequiredElementSize(Args[1], Op2Signed);
227
228 bool signedMode = Op1Signed | Op2Signed;
229 unsigned OpMinSize = std::max(Op1MinSize, Op2MinSize);
230
231 if (OpMinSize <= 7)
232 return LT.first * 3; // pmullw/sext
233 if (!signedMode && OpMinSize <= 8)
234 return LT.first * 3; // pmullw/zext
235 if (OpMinSize <= 15)
236 return LT.first * 5; // pmullw/pmulhw/pshuf
237 if (!signedMode && OpMinSize <= 16)
238 return LT.first * 5; // pmullw/pmulhw/pshuf
239 }
240
241 if (const auto *Entry = CostTableLookup(SLMCostTable, ISD,
242 LT.second)) {
243 return LT.first * Entry->Cost;
244 }
245 }
246
247 if ((ISD == ISD::SDIV || ISD == ISD::SREM || ISD == ISD::UDIV ||
248 ISD == ISD::UREM) &&
249 (Op2Info == TargetTransformInfo::OK_UniformConstantValue ||
250 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) &&
251 Opd2PropInfo == TargetTransformInfo::OP_PowerOf2) {
252 if (ISD == ISD::SDIV || ISD == ISD::SREM) {
253 // On X86, vector signed division by constants power-of-two are
254 // normally expanded to the sequence SRA + SRL + ADD + SRA.
255 // The OperandValue properties may not be the same as that of the previous
256 // operation; conservatively assume OP_None.
257 int Cost =
258 2 * getArithmeticInstrCost(Instruction::AShr, Ty, Op1Info, Op2Info,
259 TargetTransformInfo::OP_None,
260 TargetTransformInfo::OP_None);
261 Cost += getArithmeticInstrCost(Instruction::LShr, Ty, Op1Info, Op2Info,
262 TargetTransformInfo::OP_None,
263 TargetTransformInfo::OP_None);
264 Cost += getArithmeticInstrCost(Instruction::Add, Ty, Op1Info, Op2Info,
265 TargetTransformInfo::OP_None,
266 TargetTransformInfo::OP_None);
267
268 if (ISD == ISD::SREM) {
269 // For SREM: (X % C) is the equivalent of (X - (X/C)*C)
270 Cost += getArithmeticInstrCost(Instruction::Mul, Ty, Op1Info, Op2Info);
271 Cost += getArithmeticInstrCost(Instruction::Sub, Ty, Op1Info, Op2Info);
272 }
273
274 return Cost;
275 }
276
277 // Vector unsigned division/remainder will be simplified to shifts/masks.
278 if (ISD == ISD::UDIV)
279 return getArithmeticInstrCost(Instruction::LShr, Ty, Op1Info, Op2Info,
280 TargetTransformInfo::OP_None,
281 TargetTransformInfo::OP_None);
282
283 if (ISD == ISD::UREM)
284 return getArithmeticInstrCost(Instruction::And, Ty, Op1Info, Op2Info,
285 TargetTransformInfo::OP_None,
286 TargetTransformInfo::OP_None);
287 }
288
289 static const CostTblEntry AVX512BWUniformConstCostTable[] = {
290 { ISD::SHL, MVT::v64i8, 2 }, // psllw + pand.
291 { ISD::SRL, MVT::v64i8, 2 }, // psrlw + pand.
292 { ISD::SRA, MVT::v64i8, 4 }, // psrlw, pand, pxor, psubb.
293 };
294
295 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue &&
296 ST->hasBWI()) {
297 if (const auto *Entry = CostTableLookup(AVX512BWUniformConstCostTable, ISD,
298 LT.second))
299 return LT.first * Entry->Cost;
300 }
301
302 static const CostTblEntry AVX512UniformConstCostTable[] = {
303 { ISD::SRA, MVT::v2i64, 1 },
304 { ISD::SRA, MVT::v4i64, 1 },
305 { ISD::SRA, MVT::v8i64, 1 },
306 };
307
308 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue &&
309 ST->hasAVX512()) {
310 if (const auto *Entry = CostTableLookup(AVX512UniformConstCostTable, ISD,
311 LT.second))
312 return LT.first * Entry->Cost;
313 }
314
315 static const CostTblEntry AVX2UniformConstCostTable[] = {
316 { ISD::SHL, MVT::v32i8, 2 }, // psllw + pand.
317 { ISD::SRL, MVT::v32i8, 2 }, // psrlw + pand.
318 { ISD::SRA, MVT::v32i8, 4 }, // psrlw, pand, pxor, psubb.
319
320 { ISD::SRA, MVT::v4i64, 4 }, // 2 x psrad + shuffle.
321 };
322
323 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue &&
324 ST->hasAVX2()) {
325 if (const auto *Entry = CostTableLookup(AVX2UniformConstCostTable, ISD,
326 LT.second))
327 return LT.first * Entry->Cost;
328 }
329
330 static const CostTblEntry SSE2UniformConstCostTable[] = {
331 { ISD::SHL, MVT::v16i8, 2 }, // psllw + pand.
332 { ISD::SRL, MVT::v16i8, 2 }, // psrlw + pand.
333 { ISD::SRA, MVT::v16i8, 4 }, // psrlw, pand, pxor, psubb.
334
335 { ISD::SHL, MVT::v32i8, 4+2 }, // 2*(psllw + pand) + split.
336 { ISD::SRL, MVT::v32i8, 4+2 }, // 2*(psrlw + pand) + split.
337 { ISD::SRA, MVT::v32i8, 8+2 }, // 2*(psrlw, pand, pxor, psubb) + split.
338 };
339
340 // XOP has faster vXi8 shifts.
341 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue &&
342 ST->hasSSE2() && !ST->hasXOP()) {
343 if (const auto *Entry =
344 CostTableLookup(SSE2UniformConstCostTable, ISD, LT.second))
345 return LT.first * Entry->Cost;
346 }
347
348 static const CostTblEntry AVX512BWConstCostTable[] = {
349 { ISD::SDIV, MVT::v64i8, 14 }, // 2*ext+2*pmulhw sequence
350 { ISD::SREM, MVT::v64i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence
351 { ISD::UDIV, MVT::v64i8, 14 }, // 2*ext+2*pmulhw sequence
352 { ISD::UREM, MVT::v64i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence
353 { ISD::SDIV, MVT::v32i16, 6 }, // vpmulhw sequence
354 { ISD::SREM, MVT::v32i16, 8 }, // vpmulhw+mul+sub sequence
355 { ISD::UDIV, MVT::v32i16, 6 }, // vpmulhuw sequence
356 { ISD::UREM, MVT::v32i16, 8 }, // vpmulhuw+mul+sub sequence
357 };
358
359 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue ||
360 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) &&
361 ST->hasBWI()) {
362 if (const auto *Entry =
363 CostTableLookup(AVX512BWConstCostTable, ISD, LT.second))
364 return LT.first * Entry->Cost;
365 }
366
367 static const CostTblEntry AVX512ConstCostTable[] = {
368 { ISD::SDIV, MVT::v16i32, 15 }, // vpmuldq sequence
369 { ISD::SREM, MVT::v16i32, 17 }, // vpmuldq+mul+sub sequence
370 { ISD::UDIV, MVT::v16i32, 15 }, // vpmuludq sequence
371 { ISD::UREM, MVT::v16i32, 17 }, // vpmuludq+mul+sub sequence
372 };
373
374 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue ||
375 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) &&
376 ST->hasAVX512()) {
377 if (const auto *Entry =
378 CostTableLookup(AVX512ConstCostTable, ISD, LT.second))
379 return LT.first * Entry->Cost;
380 }
381
382 static const CostTblEntry AVX2ConstCostTable[] = {
383 { ISD::SDIV, MVT::v32i8, 14 }, // 2*ext+2*pmulhw sequence
384 { ISD::SREM, MVT::v32i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence
385 { ISD::UDIV, MVT::v32i8, 14 }, // 2*ext+2*pmulhw sequence
386 { ISD::UREM, MVT::v32i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence
387 { ISD::SDIV, MVT::v16i16, 6 }, // vpmulhw sequence
388 { ISD::SREM, MVT::v16i16, 8 }, // vpmulhw+mul+sub sequence
389 { ISD::UDIV, MVT::v16i16, 6 }, // vpmulhuw sequence
390 { ISD::UREM, MVT::v16i16, 8 }, // vpmulhuw+mul+sub sequence
391 { ISD::SDIV, MVT::v8i32, 15 }, // vpmuldq sequence
392 { ISD::SREM, MVT::v8i32, 19 }, // vpmuldq+mul+sub sequence
393 { ISD::UDIV, MVT::v8i32, 15 }, // vpmuludq sequence
394 { ISD::UREM, MVT::v8i32, 19 }, // vpmuludq+mul+sub sequence
395 };
396
397 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue ||
398 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) &&
399 ST->hasAVX2()) {
400 if (const auto *Entry = CostTableLookup(AVX2ConstCostTable, ISD, LT.second))
401 return LT.first * Entry->Cost;
402 }
403
404 static const CostTblEntry SSE2ConstCostTable[] = {
405 { ISD::SDIV, MVT::v32i8, 28+2 }, // 4*ext+4*pmulhw sequence + split.
406 { ISD::SREM, MVT::v32i8, 32+2 }, // 4*ext+4*pmulhw+mul+sub sequence + split.
407 { ISD::SDIV, MVT::v16i8, 14 }, // 2*ext+2*pmulhw sequence
408 { ISD::SREM, MVT::v16i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence
409 { ISD::UDIV, MVT::v32i8, 28+2 }, // 4*ext+4*pmulhw sequence + split.
410 { ISD::UREM, MVT::v32i8, 32+2 }, // 4*ext+4*pmulhw+mul+sub sequence + split.
411 { ISD::UDIV, MVT::v16i8, 14 }, // 2*ext+2*pmulhw sequence
412 { ISD::UREM, MVT::v16i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence
413 { ISD::SDIV, MVT::v16i16, 12+2 }, // 2*pmulhw sequence + split.
414 { ISD::SREM, MVT::v16i16, 16+2 }, // 2*pmulhw+mul+sub sequence + split.
415 { ISD::SDIV, MVT::v8i16, 6 }, // pmulhw sequence
416 { ISD::SREM, MVT::v8i16, 8 }, // pmulhw+mul+sub sequence
417 { ISD::UDIV, MVT::v16i16, 12+2 }, // 2*pmulhuw sequence + split.
418 { ISD::UREM, MVT::v16i16, 16+2 }, // 2*pmulhuw+mul+sub sequence + split.
419 { ISD::UDIV, MVT::v8i16, 6 }, // pmulhuw sequence
420 { ISD::UREM, MVT::v8i16, 8 }, // pmulhuw+mul+sub sequence
421 { ISD::SDIV, MVT::v8i32, 38+2 }, // 2*pmuludq sequence + split.
422 { ISD::SREM, MVT::v8i32, 48+2 }, // 2*pmuludq+mul+sub sequence + split.
423 { ISD::SDIV, MVT::v4i32, 19 }, // pmuludq sequence
424 { ISD::SREM, MVT::v4i32, 24 }, // pmuludq+mul+sub sequence
425 { ISD::UDIV, MVT::v8i32, 30+2 }, // 2*pmuludq sequence + split.
426 { ISD::UREM, MVT::v8i32, 40+2 }, // 2*pmuludq+mul+sub sequence + split.
427 { ISD::UDIV, MVT::v4i32, 15 }, // pmuludq sequence
428 { ISD::UREM, MVT::v4i32, 20 }, // pmuludq+mul+sub sequence
429 };
430
431 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue ||
432 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) &&
433 ST->hasSSE2()) {
434 // pmuldq sequence.
435 if (ISD == ISD::SDIV && LT.second == MVT::v8i32 && ST->hasAVX())
436 return LT.first * 32;
437 if (ISD == ISD::SREM && LT.second == MVT::v8i32 && ST->hasAVX())
438 return LT.first * 38;
439 if (ISD == ISD::SDIV && LT.second == MVT::v4i32 && ST->hasSSE41())
440 return LT.first * 15;
441 if (ISD == ISD::SREM && LT.second == MVT::v4i32 && ST->hasSSE41())
442 return LT.first * 20;
443
444 if (const auto *Entry = CostTableLookup(SSE2ConstCostTable, ISD, LT.second))
445 return LT.first * Entry->Cost;
446 }
447
448 static const CostTblEntry AVX2UniformCostTable[] = {
449 // Uniform splats are cheaper for the following instructions.
450 { ISD::SHL, MVT::v16i16, 1 }, // psllw.
451 { ISD::SRL, MVT::v16i16, 1 }, // psrlw.
452 { ISD::SRA, MVT::v16i16, 1 }, // psraw.
453 };
454
455 if (ST->hasAVX2() &&
456 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) ||
457 (Op2Info == TargetTransformInfo::OK_UniformValue))) {
458 if (const auto *Entry =
459 CostTableLookup(AVX2UniformCostTable, ISD, LT.second))
460 return LT.first * Entry->Cost;
461 }
462
463 static const CostTblEntry SSE2UniformCostTable[] = {
464 // Uniform splats are cheaper for the following instructions.
465 { ISD::SHL, MVT::v8i16, 1 }, // psllw.
466 { ISD::SHL, MVT::v4i32, 1 }, // pslld
467 { ISD::SHL, MVT::v2i64, 1 }, // psllq.
468
469 { ISD::SRL, MVT::v8i16, 1 }, // psrlw.
470 { ISD::SRL, MVT::v4i32, 1 }, // psrld.
471 { ISD::SRL, MVT::v2i64, 1 }, // psrlq.
472
473 { ISD::SRA, MVT::v8i16, 1 }, // psraw.
474 { ISD::SRA, MVT::v4i32, 1 }, // psrad.
475 };
476
477 if (ST->hasSSE2() &&
478 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) ||
479 (Op2Info == TargetTransformInfo::OK_UniformValue))) {
480 if (const auto *Entry =
481 CostTableLookup(SSE2UniformCostTable, ISD, LT.second))
482 return LT.first * Entry->Cost;
483 }
484
485 static const CostTblEntry AVX512DQCostTable[] = {
486 { ISD::MUL, MVT::v2i64, 1 },
487 { ISD::MUL, MVT::v4i64, 1 },
488 { ISD::MUL, MVT::v8i64, 1 }
489 };
490
491 // Look for AVX512DQ lowering tricks for custom cases.
492 if (ST->hasDQI())
493 if (const auto *Entry = CostTableLookup(AVX512DQCostTable, ISD, LT.second))
494 return LT.first * Entry->Cost;
495
496 static const CostTblEntry AVX512BWCostTable[] = {
497 { ISD::SHL, MVT::v8i16, 1 }, // vpsllvw
498 { ISD::SRL, MVT::v8i16, 1 }, // vpsrlvw
499 { ISD::SRA, MVT::v8i16, 1 }, // vpsravw
500
501 { ISD::SHL, MVT::v16i16, 1 }, // vpsllvw
502 { ISD::SRL, MVT::v16i16, 1 }, // vpsrlvw
503 { ISD::SRA, MVT::v16i16, 1 }, // vpsravw
504
505 { ISD::SHL, MVT::v32i16, 1 }, // vpsllvw
506 { ISD::SRL, MVT::v32i16, 1 }, // vpsrlvw
507 { ISD::SRA, MVT::v32i16, 1 }, // vpsravw
508
509 { ISD::SHL, MVT::v64i8, 11 }, // vpblendvb sequence.
510 { ISD::SRL, MVT::v64i8, 11 }, // vpblendvb sequence.
511 { ISD::SRA, MVT::v64i8, 24 }, // vpblendvb sequence.
512
513 { ISD::MUL, MVT::v64i8, 11 }, // extend/pmullw/trunc sequence.
514 { ISD::MUL, MVT::v32i8, 4 }, // extend/pmullw/trunc sequence.
515 { ISD::MUL, MVT::v16i8, 4 }, // extend/pmullw/trunc sequence.
516 };
517
518 // Look for AVX512BW lowering tricks for custom cases.
519 if (ST->hasBWI())
520 if (const auto *Entry = CostTableLookup(AVX512BWCostTable, ISD, LT.second))
521 return LT.first * Entry->Cost;
522
523 static const CostTblEntry AVX512CostTable[] = {
524 { ISD::SHL, MVT::v16i32, 1 },
525 { ISD::SRL, MVT::v16i32, 1 },
526 { ISD::SRA, MVT::v16i32, 1 },
527
528 { ISD::SHL, MVT::v8i64, 1 },
529 { ISD::SRL, MVT::v8i64, 1 },
530
531 { ISD::SRA, MVT::v2i64, 1 },
532 { ISD::SRA, MVT::v4i64, 1 },
533 { ISD::SRA, MVT::v8i64, 1 },
534
535 { ISD::MUL, MVT::v32i8, 13 }, // extend/pmullw/trunc sequence.
536 { ISD::MUL, MVT::v16i8, 5 }, // extend/pmullw/trunc sequence.
537 { ISD::MUL, MVT::v16i32, 1 }, // pmulld (Skylake from agner.org)
538 { ISD::MUL, MVT::v8i32, 1 }, // pmulld (Skylake from agner.org)
539 { ISD::MUL, MVT::v4i32, 1 }, // pmulld (Skylake from agner.org)
540 { ISD::MUL, MVT::v8i64, 8 }, // 3*pmuludq/3*shift/2*add
541
542 { ISD::FADD, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/
543 { ISD::FSUB, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/
544 { ISD::FMUL, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/
545
546 { ISD::FADD, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/
547 { ISD::FSUB, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/
548 { ISD::FMUL, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/
549 };
550
551 if (ST->hasAVX512())
552 if (const auto *Entry = CostTableLookup(AVX512CostTable, ISD, LT.second))
553 return LT.first * Entry->Cost;
554
555 static const CostTblEntry AVX2ShiftCostTable[] = {
556 // Shifts on v4i64/v8i32 on AVX2 is legal even though we declare to
557 // customize them to detect the cases where shift amount is a scalar one.
558 { ISD::SHL, MVT::v4i32, 1 },
559 { ISD::SRL, MVT::v4i32, 1 },
560 { ISD::SRA, MVT::v4i32, 1 },
561 { ISD::SHL, MVT::v8i32, 1 },
562 { ISD::SRL, MVT::v8i32, 1 },
563 { ISD::SRA, MVT::v8i32, 1 },
564 { ISD::SHL, MVT::v2i64, 1 },
565 { ISD::SRL, MVT::v2i64, 1 },
566 { ISD::SHL, MVT::v4i64, 1 },
567 { ISD::SRL, MVT::v4i64, 1 },
568 };
569
570 // Look for AVX2 lowering tricks.
571 if (ST->hasAVX2()) {
572 if (ISD == ISD::SHL && LT.second == MVT::v16i16 &&
573 (Op2Info == TargetTransformInfo::OK_UniformConstantValue ||
574 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue))
575 // On AVX2, a packed v16i16 shift left by a constant build_vector
576 // is lowered into a vector multiply (vpmullw).
577 return getArithmeticInstrCost(Instruction::Mul, Ty, Op1Info, Op2Info,
578 TargetTransformInfo::OP_None,
579 TargetTransformInfo::OP_None);
580
581 if (const auto *Entry = CostTableLookup(AVX2ShiftCostTable, ISD, LT.second))
582 return LT.first * Entry->Cost;
583 }
584
585 static const CostTblEntry XOPShiftCostTable[] = {
586 // 128bit shifts take 1cy, but right shifts require negation beforehand.
587 { ISD::SHL, MVT::v16i8, 1 },
588 { ISD::SRL, MVT::v16i8, 2 },
589 { ISD::SRA, MVT::v16i8, 2 },
590 { ISD::SHL, MVT::v8i16, 1 },
591 { ISD::SRL, MVT::v8i16, 2 },
592 { ISD::SRA, MVT::v8i16, 2 },
593 { ISD::SHL, MVT::v4i32, 1 },
594 { ISD::SRL, MVT::v4i32, 2 },
595 { ISD::SRA, MVT::v4i32, 2 },
596 { ISD::SHL, MVT::v2i64, 1 },
597 { ISD::SRL, MVT::v2i64, 2 },
598 { ISD::SRA, MVT::v2i64, 2 },
599 // 256bit shifts require splitting if AVX2 didn't catch them above.
600 { ISD::SHL, MVT::v32i8, 2+2 },
601 { ISD::SRL, MVT::v32i8, 4+2 },
602 { ISD::SRA, MVT::v32i8, 4+2 },
603 { ISD::SHL, MVT::v16i16, 2+2 },
604 { ISD::SRL, MVT::v16i16, 4+2 },
605 { ISD::SRA, MVT::v16i16, 4+2 },
606 { ISD::SHL, MVT::v8i32, 2+2 },
607 { ISD::SRL, MVT::v8i32, 4+2 },
608 { ISD::SRA, MVT::v8i32, 4+2 },
609 { ISD::SHL, MVT::v4i64, 2+2 },
610 { ISD::SRL, MVT::v4i64, 4+2 },
611 { ISD::SRA, MVT::v4i64, 4+2 },
612 };
613
614 // Look for XOP lowering tricks.
615 if (ST->hasXOP()) {
616 // If the right shift is constant then we'll fold the negation so
617 // it's as cheap as a left shift.
618 int ShiftISD = ISD;
619 if ((ShiftISD == ISD::SRL || ShiftISD == ISD::SRA) &&
620 (Op2Info == TargetTransformInfo::OK_UniformConstantValue ||
621 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue))
622 ShiftISD = ISD::SHL;
623 if (const auto *Entry =
624 CostTableLookup(XOPShiftCostTable, ShiftISD, LT.second))
625 return LT.first * Entry->Cost;
626 }
627
628 static const CostTblEntry SSE2UniformShiftCostTable[] = {
629 // Uniform splats are cheaper for the following instructions.
630 { ISD::SHL, MVT::v16i16, 2+2 }, // 2*psllw + split.
631 { ISD::SHL, MVT::v8i32, 2+2 }, // 2*pslld + split.
632 { ISD::SHL, MVT::v4i64, 2+2 }, // 2*psllq + split.
633
634 { ISD::SRL, MVT::v16i16, 2+2 }, // 2*psrlw + split.
635 { ISD::SRL, MVT::v8i32, 2+2 }, // 2*psrld + split.
636 { ISD::SRL, MVT::v4i64, 2+2 }, // 2*psrlq + split.
637
638 { ISD::SRA, MVT::v16i16, 2+2 }, // 2*psraw + split.
639 { ISD::SRA, MVT::v8i32, 2+2 }, // 2*psrad + split.
640 { ISD::SRA, MVT::v2i64, 4 }, // 2*psrad + shuffle.
641 { ISD::SRA, MVT::v4i64, 8+2 }, // 2*(2*psrad + shuffle) + split.
642 };
643
644 if (ST->hasSSE2() &&
645 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) ||
646 (Op2Info == TargetTransformInfo::OK_UniformValue))) {
647
648 // Handle AVX2 uniform v4i64 ISD::SRA, it's not worth a table.
649 if (ISD == ISD::SRA && LT.second == MVT::v4i64 && ST->hasAVX2())
650 return LT.first * 4; // 2*psrad + shuffle.
651
652 if (const auto *Entry =
653 CostTableLookup(SSE2UniformShiftCostTable, ISD, LT.second))
654 return LT.first * Entry->Cost;
655 }
656
657 if (ISD == ISD::SHL &&
658 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) {
659 MVT VT = LT.second;
660 // Vector shift left by non uniform constant can be lowered
661 // into vector multiply.
662 if (((VT == MVT::v8i16 || VT == MVT::v4i32) && ST->hasSSE2()) ||
663 ((VT == MVT::v16i16 || VT == MVT::v8i32) && ST->hasAVX()))
664 ISD = ISD::MUL;
665 }
666
667 static const CostTblEntry AVX2CostTable[] = {
668 { ISD::SHL, MVT::v32i8, 11 }, // vpblendvb sequence.
669 { ISD::SHL, MVT::v16i16, 10 }, // extend/vpsrlvd/pack sequence.
670
671 { ISD::SRL, MVT::v32i8, 11 }, // vpblendvb sequence.
672 { ISD::SRL, MVT::v16i16, 10 }, // extend/vpsrlvd/pack sequence.
673
674 { ISD::SRA, MVT::v32i8, 24 }, // vpblendvb sequence.
675 { ISD::SRA, MVT::v16i16, 10 }, // extend/vpsravd/pack sequence.
676 { ISD::SRA, MVT::v2i64, 4 }, // srl/xor/sub sequence.
677 { ISD::SRA, MVT::v4i64, 4 }, // srl/xor/sub sequence.
678
679 { ISD::SUB, MVT::v32i8, 1 }, // psubb
680 { ISD::ADD, MVT::v32i8, 1 }, // paddb
681 { ISD::SUB, MVT::v16i16, 1 }, // psubw
682 { ISD::ADD, MVT::v16i16, 1 }, // paddw
683 { ISD::SUB, MVT::v8i32, 1 }, // psubd
684 { ISD::ADD, MVT::v8i32, 1 }, // paddd
685 { ISD::SUB, MVT::v4i64, 1 }, // psubq
686 { ISD::ADD, MVT::v4i64, 1 }, // paddq
687
688 { ISD::MUL, MVT::v32i8, 17 }, // extend/pmullw/trunc sequence.
689 { ISD::MUL, MVT::v16i8, 7 }, // extend/pmullw/trunc sequence.
690 { ISD::MUL, MVT::v16i16, 1 }, // pmullw
691 { ISD::MUL, MVT::v8i32, 2 }, // pmulld (Haswell from agner.org)
692 { ISD::MUL, MVT::v4i64, 8 }, // 3*pmuludq/3*shift/2*add
693
694 { ISD::FADD, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/
695 { ISD::FADD, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/
696 { ISD::FSUB, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/
697 { ISD::FSUB, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/
698 { ISD::FMUL, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/
699 { ISD::FMUL, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/
700
701 { ISD::FDIV, MVT::f32, 7 }, // Haswell from http://www.agner.org/
702 { ISD::FDIV, MVT::v4f32, 7 }, // Haswell from http://www.agner.org/
703 { ISD::FDIV, MVT::v8f32, 14 }, // Haswell from http://www.agner.org/
704 { ISD::FDIV, MVT::f64, 14 }, // Haswell from http://www.agner.org/
705 { ISD::FDIV, MVT::v2f64, 14 }, // Haswell from http://www.agner.org/
706 { ISD::FDIV, MVT::v4f64, 28 }, // Haswell from http://www.agner.org/
707 };
708
709 // Look for AVX2 lowering tricks for custom cases.
710 if (ST->hasAVX2())
711 if (const auto *Entry = CostTableLookup(AVX2CostTable, ISD, LT.second))
712 return LT.first * Entry->Cost;
713
714 static const CostTblEntry AVX1CostTable[] = {
715 // We don't have to scalarize unsupported ops. We can issue two half-sized
716 // operations and we only need to extract the upper YMM half.
717 // Two ops + 1 extract + 1 insert = 4.
718 { ISD::MUL, MVT::v16i16, 4 },
719 { ISD::MUL, MVT::v8i32, 4 },
720 { ISD::SUB, MVT::v32i8, 4 },
721 { ISD::ADD, MVT::v32i8, 4 },
722 { ISD::SUB, MVT::v16i16, 4 },
723 { ISD::ADD, MVT::v16i16, 4 },
724 { ISD::SUB, MVT::v8i32, 4 },
725 { ISD::ADD, MVT::v8i32, 4 },
726 { ISD::SUB, MVT::v4i64, 4 },
727 { ISD::ADD, MVT::v4i64, 4 },
728
729 // A v4i64 multiply is custom lowered as two split v2i64 vectors that then
730 // are lowered as a series of long multiplies(3), shifts(3) and adds(2)
731 // Because we believe v4i64 to be a legal type, we must also include the
732 // extract+insert in the cost table. Therefore, the cost here is 18
733 // instead of 8.
734 { ISD::MUL, MVT::v4i64, 18 },
735
736 { ISD::MUL, MVT::v32i8, 26 }, // extend/pmullw/trunc sequence.
737
738 { ISD::FDIV, MVT::f32, 14 }, // SNB from http://www.agner.org/
739 { ISD::FDIV, MVT::v4f32, 14 }, // SNB from http://www.agner.org/
740 { ISD::FDIV, MVT::v8f32, 28 }, // SNB from http://www.agner.org/
741 { ISD::FDIV, MVT::f64, 22 }, // SNB from http://www.agner.org/
742 { ISD::FDIV, MVT::v2f64, 22 }, // SNB from http://www.agner.org/
743 { ISD::FDIV, MVT::v4f64, 44 }, // SNB from http://www.agner.org/
744 };
745
746 if (ST->hasAVX())
747 if (const auto *Entry = CostTableLookup(AVX1CostTable, ISD, LT.second))
748 return LT.first * Entry->Cost;
749
750 static const CostTblEntry SSE42CostTable[] = {
751 { ISD::FADD, MVT::f64, 1 }, // Nehalem from http://www.agner.org/
752 { ISD::FADD, MVT::f32, 1 }, // Nehalem from http://www.agner.org/
753 { ISD::FADD, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/
754 { ISD::FADD, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/
755
756 { ISD::FSUB, MVT::f64, 1 }, // Nehalem from http://www.agner.org/
757 { ISD::FSUB, MVT::f32 , 1 }, // Nehalem from http://www.agner.org/
758 { ISD::FSUB, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/
759 { ISD::FSUB, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/
760
761 { ISD::FMUL, MVT::f64, 1 }, // Nehalem from http://www.agner.org/
762 { ISD::FMUL, MVT::f32, 1 }, // Nehalem from http://www.agner.org/
763 { ISD::FMUL, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/
764 { ISD::FMUL, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/
765
766 { ISD::FDIV, MVT::f32, 14 }, // Nehalem from http://www.agner.org/
767 { ISD::FDIV, MVT::v4f32, 14 }, // Nehalem from http://www.agner.org/
768 { ISD::FDIV, MVT::f64, 22 }, // Nehalem from http://www.agner.org/
769 { ISD::FDIV, MVT::v2f64, 22 }, // Nehalem from http://www.agner.org/
770 };
771
772 if (ST->hasSSE42())
773 if (const auto *Entry = CostTableLookup(SSE42CostTable, ISD, LT.second))
774 return LT.first * Entry->Cost;
775
776 static const CostTblEntry SSE41CostTable[] = {
777 { ISD::SHL, MVT::v16i8, 11 }, // pblendvb sequence.
778 { ISD::SHL, MVT::v32i8, 2*11+2 }, // pblendvb sequence + split.
779 { ISD::SHL, MVT::v8i16, 14 }, // pblendvb sequence.
780 { ISD::SHL, MVT::v16i16, 2*14+2 }, // pblendvb sequence + split.
781 { ISD::SHL, MVT::v4i32, 4 }, // pslld/paddd/cvttps2dq/pmulld
782 { ISD::SHL, MVT::v8i32, 2*4+2 }, // pslld/paddd/cvttps2dq/pmulld + split
783
784 { ISD::SRL, MVT::v16i8, 12 }, // pblendvb sequence.
785 { ISD::SRL, MVT::v32i8, 2*12+2 }, // pblendvb sequence + split.
786 { ISD::SRL, MVT::v8i16, 14 }, // pblendvb sequence.
787 { ISD::SRL, MVT::v16i16, 2*14+2 }, // pblendvb sequence + split.
788 { ISD::SRL, MVT::v4i32, 11 }, // Shift each lane + blend.
789 { ISD::SRL, MVT::v8i32, 2*11+2 }, // Shift each lane + blend + split.
790
791 { ISD::SRA, MVT::v16i8, 24 }, // pblendvb sequence.
792 { ISD::SRA, MVT::v32i8, 2*24+2 }, // pblendvb sequence + split.
793 { ISD::SRA, MVT::v8i16, 14 }, // pblendvb sequence.
794 { ISD::SRA, MVT::v16i16, 2*14+2 }, // pblendvb sequence + split.
795 { ISD::SRA, MVT::v4i32, 12 }, // Shift each lane + blend.
796 { ISD::SRA, MVT::v8i32, 2*12+2 }, // Shift each lane + blend + split.
797
798 { ISD::MUL, MVT::v4i32, 2 } // pmulld (Nehalem from agner.org)
799 };
800
801 if (ST->hasSSE41())
802 if (const auto *Entry = CostTableLookup(SSE41CostTable, ISD, LT.second))
803 return LT.first * Entry->Cost;
804
805 static const CostTblEntry SSE2CostTable[] = {
806 // We don't correctly identify costs of casts because they are marked as
807 // custom.
808 { ISD::SHL, MVT::v16i8, 26 }, // cmpgtb sequence.
809 { ISD::SHL, MVT::v8i16, 32 }, // cmpgtb sequence.
810 { ISD::SHL, MVT::v4i32, 2*5 }, // We optimized this using mul.
811 { ISD::SHL, MVT::v2i64, 4 }, // splat+shuffle sequence.
812 { ISD::SHL, MVT::v4i64, 2*4+2 }, // splat+shuffle sequence + split.
813
814 { ISD::SRL, MVT::v16i8, 26 }, // cmpgtb sequence.
815 { ISD::SRL, MVT::v8i16, 32 }, // cmpgtb sequence.
816 { ISD::SRL, MVT::v4i32, 16 }, // Shift each lane + blend.
817 { ISD::SRL, MVT::v2i64, 4 }, // splat+shuffle sequence.
818 { ISD::SRL, MVT::v4i64, 2*4+2 }, // splat+shuffle sequence + split.
819
820 { ISD::SRA, MVT::v16i8, 54 }, // unpacked cmpgtb sequence.
821 { ISD::SRA, MVT::v8i16, 32 }, // cmpgtb sequence.
822 { ISD::SRA, MVT::v4i32, 16 }, // Shift each lane + blend.
823 { ISD::SRA, MVT::v2i64, 12 }, // srl/xor/sub sequence.
824 { ISD::SRA, MVT::v4i64, 2*12+2 }, // srl/xor/sub sequence+split.
825
826 { ISD::MUL, MVT::v16i8, 12 }, // extend/pmullw/trunc sequence.
827 { ISD::MUL, MVT::v8i16, 1 }, // pmullw
828 { ISD::MUL, MVT::v4i32, 6 }, // 3*pmuludq/4*shuffle
829 { ISD::MUL, MVT::v2i64, 8 }, // 3*pmuludq/3*shift/2*add
830
831 { ISD::FDIV, MVT::f32, 23 }, // Pentium IV from http://www.agner.org/
832 { ISD::FDIV, MVT::v4f32, 39 }, // Pentium IV from http://www.agner.org/
833 { ISD::FDIV, MVT::f64, 38 }, // Pentium IV from http://www.agner.org/
834 { ISD::FDIV, MVT::v2f64, 69 }, // Pentium IV from http://www.agner.org/
835 };
836
837 if (ST->hasSSE2())
838 if (const auto *Entry = CostTableLookup(SSE2CostTable, ISD, LT.second))
839 return LT.first * Entry->Cost;
840
841 static const CostTblEntry SSE1CostTable[] = {
842 { ISD::FDIV, MVT::f32, 17 }, // Pentium III from http://www.agner.org/
843 { ISD::FDIV, MVT::v4f32, 34 }, // Pentium III from http://www.agner.org/
844 };
845
846 if (ST->hasSSE1())
847 if (const auto *Entry = CostTableLookup(SSE1CostTable, ISD, LT.second))
848 return LT.first * Entry->Cost;
849
850 // It is not a good idea to vectorize division. We have to scalarize it and
851 // in the process we will often end up having to spilling regular
852 // registers. The overhead of division is going to dominate most kernels
853 // anyways so try hard to prevent vectorization of division - it is
854 // generally a bad idea. Assume somewhat arbitrarily that we have to be able
855 // to hide "20 cycles" for each lane.
856 if (LT.second.isVector() && (ISD == ISD::SDIV || ISD == ISD::SREM ||
857 ISD == ISD::UDIV || ISD == ISD::UREM)) {
858 int ScalarCost = getArithmeticInstrCost(
859 Opcode, Ty->getScalarType(), Op1Info, Op2Info,
860 TargetTransformInfo::OP_None, TargetTransformInfo::OP_None);
861 return 20 * LT.first * LT.second.getVectorNumElements() * ScalarCost;
862 }
863
864 // Fallback to the default implementation.
865 return BaseT::getArithmeticInstrCost(Opcode, Ty, Op1Info, Op2Info);
866}
867
868int X86TTIImpl::getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, int Index,
869 Type *SubTp) {
870 // 64-bit packed float vectors (v2f32) are widened to type v4f32.
871 // 64-bit packed integer vectors (v2i32) are promoted to type v2i64.
872 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Tp);
873
874 // Treat Transpose as 2-op shuffles - there's no difference in lowering.
875 if (Kind == TTI::SK_Transpose)
876 Kind = TTI::SK_PermuteTwoSrc;
877
878 // For Broadcasts we are splatting the first element from the first input
879 // register, so only need to reference that input and all the output
880 // registers are the same.
881 if (Kind == TTI::SK_Broadcast)
882 LT.first = 1;
883
884 // Subvector extractions are free if they start at the beginning of a
885 // vector and cheap if the subvectors are aligned.
886 if (Kind == TTI::SK_ExtractSubvector && LT.second.isVector()) {
887 int NumElts = LT.second.getVectorNumElements();
888 if ((Index % NumElts) == 0)
889 return 0;
890 std::pair<int, MVT> SubLT = TLI->getTypeLegalizationCost(DL, SubTp);
891 if (SubLT.second.isVector()) {
892 int NumSubElts = SubLT.second.getVectorNumElements();
893 if ((Index % NumSubElts) == 0 && (NumElts % NumSubElts) == 0)
894 return SubLT.first;
895 }
896 }
897
898 // We are going to permute multiple sources and the result will be in multiple
899 // destinations. Providing an accurate cost only for splits where the element
900 // type remains the same.
901 if (Kind == TTI::SK_PermuteSingleSrc && LT.first != 1) {
902 MVT LegalVT = LT.second;
903 if (LegalVT.isVector() &&
904 LegalVT.getVectorElementType().getSizeInBits() ==
905 Tp->getVectorElementType()->getPrimitiveSizeInBits() &&
906 LegalVT.getVectorNumElements() < Tp->getVectorNumElements()) {
907
908 unsigned VecTySize = DL.getTypeStoreSize(Tp);
909 unsigned LegalVTSize = LegalVT.getStoreSize();
910 // Number of source vectors after legalization:
911 unsigned NumOfSrcs = (VecTySize + LegalVTSize - 1) / LegalVTSize;
912 // Number of destination vectors after legalization:
913 unsigned NumOfDests = LT.first;
914
915 Type *SingleOpTy = VectorType::get(Tp->getVectorElementType(),
916 LegalVT.getVectorNumElements());
917
918 unsigned NumOfShuffles = (NumOfSrcs - 1) * NumOfDests;
919 return NumOfShuffles *
920 getShuffleCost(TTI::SK_PermuteTwoSrc, SingleOpTy, 0, nullptr);
921 }
922
923 return BaseT::getShuffleCost(Kind, Tp, Index, SubTp);
924 }
925
926 // For 2-input shuffles, we must account for splitting the 2 inputs into many.
927 if (Kind == TTI::SK_PermuteTwoSrc && LT.first != 1) {
928 // We assume that source and destination have the same vector type.
929 int NumOfDests = LT.first;
930 int NumOfShufflesPerDest = LT.first * 2 - 1;
931 LT.first = NumOfDests * NumOfShufflesPerDest;
932 }
933
934 static const CostTblEntry AVX512VBMIShuffleTbl[] = {
935 {TTI::SK_Reverse, MVT::v64i8, 1}, // vpermb
936 {TTI::SK_Reverse, MVT::v32i8, 1}, // vpermb
937
938 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 1}, // vpermb
939 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 1}, // vpermb
940
941 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 1}, // vpermt2b
942 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 1}, // vpermt2b
943 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 1} // vpermt2b
944 };
945
946 if (ST->hasVBMI())
947 if (const auto *Entry =
948 CostTableLookup(AVX512VBMIShuffleTbl, Kind, LT.second))
949 return LT.first * Entry->Cost;
950
951 static const CostTblEntry AVX512BWShuffleTbl[] = {
952 {TTI::SK_Broadcast, MVT::v32i16, 1}, // vpbroadcastw
953 {TTI::SK_Broadcast, MVT::v64i8, 1}, // vpbroadcastb
954
955 {TTI::SK_Reverse, MVT::v32i16, 1}, // vpermw
956 {TTI::SK_Reverse, MVT::v16i16, 1}, // vpermw
957 {TTI::SK_Reverse, MVT::v64i8, 2}, // pshufb + vshufi64x2
958
959 {TTI::SK_PermuteSingleSrc, MVT::v32i16, 1}, // vpermw
960 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 1}, // vpermw
961 {TTI::SK_PermuteSingleSrc, MVT::v8i16, 1}, // vpermw
962 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 8}, // extend to v32i16
963 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 3}, // vpermw + zext/trunc
964
965 {TTI::SK_PermuteTwoSrc, MVT::v32i16, 1}, // vpermt2w
966 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 1}, // vpermt2w
967 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 1}, // vpermt2w
968 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 3}, // zext + vpermt2w + trunc
969 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 19}, // 6 * v32i8 + 1
970 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 3} // zext + vpermt2w + trunc
971 };
972
973 if (ST->hasBWI())
974 if (const auto *Entry =
975 CostTableLookup(AVX512BWShuffleTbl, Kind, LT.second))
976 return LT.first * Entry->Cost;
977
978 static const CostTblEntry AVX512ShuffleTbl[] = {
979 {TTI::SK_Broadcast, MVT::v8f64, 1}, // vbroadcastpd
980 {TTI::SK_Broadcast, MVT::v16f32, 1}, // vbroadcastps
981 {TTI::SK_Broadcast, MVT::v8i64, 1}, // vpbroadcastq
982 {TTI::SK_Broadcast, MVT::v16i32, 1}, // vpbroadcastd
983
984 {TTI::SK_Reverse, MVT::v8f64, 1}, // vpermpd
985 {TTI::SK_Reverse, MVT::v16f32, 1}, // vpermps
986 {TTI::SK_Reverse, MVT::v8i64, 1}, // vpermq
987 {TTI::SK_Reverse, MVT::v16i32, 1}, // vpermd
988
989 {TTI::SK_PermuteSingleSrc, MVT::v8f64, 1}, // vpermpd
990 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 1}, // vpermpd
991 {TTI::SK_PermuteSingleSrc, MVT::v2f64, 1}, // vpermpd
992 {TTI::SK_PermuteSingleSrc, MVT::v16f32, 1}, // vpermps
993 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 1}, // vpermps
994 {TTI::SK_PermuteSingleSrc, MVT::v4f32, 1}, // vpermps
995 {TTI::SK_PermuteSingleSrc, MVT::v8i64, 1}, // vpermq
996 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 1}, // vpermq
997 {TTI::SK_PermuteSingleSrc, MVT::v2i64, 1}, // vpermq
998 {TTI::SK_PermuteSingleSrc, MVT::v16i32, 1}, // vpermd
999 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 1}, // vpermd
1000 {TTI::SK_PermuteSingleSrc, MVT::v4i32, 1}, // vpermd
1001 {TTI::SK_PermuteSingleSrc, MVT::v16i8, 1}, // pshufb
1002
1003 {TTI::SK_PermuteTwoSrc, MVT::v8f64, 1}, // vpermt2pd
1004 {TTI::SK_PermuteTwoSrc, MVT::v16f32, 1}, // vpermt2ps
1005 {TTI::SK_PermuteTwoSrc, MVT::v8i64, 1}, // vpermt2q
1006 {TTI::SK_PermuteTwoSrc, MVT::v16i32, 1}, // vpermt2d
1007 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 1}, // vpermt2pd
1008 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 1}, // vpermt2ps
1009 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 1}, // vpermt2q
1010 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 1}, // vpermt2d
1011 {TTI::SK_PermuteTwoSrc, MVT::v2f64, 1}, // vpermt2pd
1012 {TTI::SK_PermuteTwoSrc, MVT::v4f32, 1}, // vpermt2ps
1013 {TTI::SK_PermuteTwoSrc, MVT::v2i64, 1}, // vpermt2q
1014 {TTI::SK_PermuteTwoSrc, MVT::v4i32, 1} // vpermt2d
1015 };
1016
1017 if (ST->hasAVX512())
1018 if (const auto *Entry = CostTableLookup(AVX512ShuffleTbl, Kind, LT.second))
1019 return LT.first * Entry->Cost;
1020
1021 static const CostTblEntry AVX2ShuffleTbl[] = {
1022 {TTI::SK_Broadcast, MVT::v4f64, 1}, // vbroadcastpd
1023 {TTI::SK_Broadcast, MVT::v8f32, 1}, // vbroadcastps
1024 {TTI::SK_Broadcast, MVT::v4i64, 1}, // vpbroadcastq
1025 {TTI::SK_Broadcast, MVT::v8i32, 1}, // vpbroadcastd
1026 {TTI::SK_Broadcast, MVT::v16i16, 1}, // vpbroadcastw
1027 {TTI::SK_Broadcast, MVT::v32i8, 1}, // vpbroadcastb
1028
1029 {TTI::SK_Reverse, MVT::v4f64, 1}, // vpermpd
1030 {TTI::SK_Reverse, MVT::v8f32, 1}, // vpermps
1031 {TTI::SK_Reverse, MVT::v4i64, 1}, // vpermq
1032 {TTI::SK_Reverse, MVT::v8i32, 1}, // vpermd
1033 {TTI::SK_Reverse, MVT::v16i16, 2}, // vperm2i128 + pshufb
1034 {TTI::SK_Reverse, MVT::v32i8, 2}, // vperm2i128 + pshufb
1035
1036 {TTI::SK_Select, MVT::v16i16, 1}, // vpblendvb
1037 {TTI::SK_Select, MVT::v32i8, 1}, // vpblendvb
1038
1039 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 1}, // vpermpd
1040 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 1}, // vpermps
1041 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 1}, // vpermq
1042 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 1}, // vpermd
1043 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 4}, // vperm2i128 + 2*vpshufb
1044 // + vpblendvb
1045 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 4}, // vperm2i128 + 2*vpshufb
1046 // + vpblendvb
1047
1048 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 3}, // 2*vpermpd + vblendpd
1049 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 3}, // 2*vpermps + vblendps
1050 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 3}, // 2*vpermq + vpblendd
1051 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 3}, // 2*vpermd + vpblendd
1052 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 7}, // 2*vperm2i128 + 4*vpshufb
1053 // + vpblendvb
1054 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 7}, // 2*vperm2i128 + 4*vpshufb
1055 // + vpblendvb
1056 };
1057
1058 if (ST->hasAVX2())
1059 if (const auto *Entry = CostTableLookup(AVX2ShuffleTbl, Kind, LT.second))
1060 return LT.first * Entry->Cost;
1061
1062 static const CostTblEntry XOPShuffleTbl[] = {
1063 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 2}, // vperm2f128 + vpermil2pd
1064 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 2}, // vperm2f128 + vpermil2ps
1065 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 2}, // vperm2f128 + vpermil2pd
1066 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 2}, // vperm2f128 + vpermil2ps
1067 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 4}, // vextractf128 + 2*vpperm
1068 // + vinsertf128
1069 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 4}, // vextractf128 + 2*vpperm
1070 // + vinsertf128
1071
1072 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 9}, // 2*vextractf128 + 6*vpperm
1073 // + vinsertf128
1074 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 1}, // vpperm
1075 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 9}, // 2*vextractf128 + 6*vpperm
1076 // + vinsertf128
1077 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 1}, // vpperm
1078 };
1079
1080 if (ST->hasXOP())
1081 if (const auto *Entry = CostTableLookup(XOPShuffleTbl, Kind, LT.second))
1082 return LT.first * Entry->Cost;
1083
1084 static const CostTblEntry AVX1ShuffleTbl[] = {
1085 {TTI::SK_Broadcast, MVT::v4f64, 2}, // vperm2f128 + vpermilpd
1086 {TTI::SK_Broadcast, MVT::v8f32, 2}, // vperm2f128 + vpermilps
1087 {TTI::SK_Broadcast, MVT::v4i64, 2}, // vperm2f128 + vpermilpd
1088 {TTI::SK_Broadcast, MVT::v8i32, 2}, // vperm2f128 + vpermilps
1089 {TTI::SK_Broadcast, MVT::v16i16, 3}, // vpshuflw + vpshufd + vinsertf128
1090 {TTI::SK_Broadcast, MVT::v32i8, 2}, // vpshufb + vinsertf128
1091
1092 {TTI::SK_Reverse, MVT::v4f64, 2}, // vperm2f128 + vpermilpd
1093 {TTI::SK_Reverse, MVT::v8f32, 2}, // vperm2f128 + vpermilps
1094 {TTI::SK_Reverse, MVT::v4i64, 2}, // vperm2f128 + vpermilpd
1095 {TTI::SK_Reverse, MVT::v8i32, 2}, // vperm2f128 + vpermilps
1096 {TTI::SK_Reverse, MVT::v16i16, 4}, // vextractf128 + 2*pshufb
1097 // + vinsertf128
1098 {TTI::SK_Reverse, MVT::v32i8, 4}, // vextractf128 + 2*pshufb
1099 // + vinsertf128
1100
1101 {TTI::SK_Select, MVT::v4i64, 1}, // vblendpd
1102 {TTI::SK_Select, MVT::v4f64, 1}, // vblendpd
1103 {TTI::SK_Select, MVT::v8i32, 1}, // vblendps
1104 {TTI::SK_Select, MVT::v8f32, 1}, // vblendps
1105 {TTI::SK_Select, MVT::v16i16, 3}, // vpand + vpandn + vpor
1106 {TTI::SK_Select, MVT::v32i8, 3}, // vpand + vpandn + vpor
1107
1108 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 2}, // vperm2f128 + vshufpd
1109 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 2}, // vperm2f128 + vshufpd
1110 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 4}, // 2*vperm2f128 + 2*vshufps
1111 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 4}, // 2*vperm2f128 + 2*vshufps
1112 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 8}, // vextractf128 + 4*pshufb
1113 // + 2*por + vinsertf128
1114 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 8}, // vextractf128 + 4*pshufb
1115 // + 2*por + vinsertf128
1116
1117 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 3}, // 2*vperm2f128 + vshufpd
1118 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 3}, // 2*vperm2f128 + vshufpd
1119 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 4}, // 2*vperm2f128 + 2*vshufps
1120 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 4}, // 2*vperm2f128 + 2*vshufps
1121 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 15}, // 2*vextractf128 + 8*pshufb
1122 // + 4*por + vinsertf128
1123 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 15}, // 2*vextractf128 + 8*pshufb
1124 // + 4*por + vinsertf128
1125 };
1126
1127 if (ST->hasAVX())
1128 if (const auto *Entry = CostTableLookup(AVX1ShuffleTbl, Kind, LT.second))
1129 return LT.first * Entry->Cost;
1130
1131 static const CostTblEntry SSE41ShuffleTbl[] = {
1132 {TTI::SK_Select, MVT::v2i64, 1}, // pblendw
1133 {TTI::SK_Select, MVT::v2f64, 1}, // movsd
1134 {TTI::SK_Select, MVT::v4i32, 1}, // pblendw
1135 {TTI::SK_Select, MVT::v4f32, 1}, // blendps
1136 {TTI::SK_Select, MVT::v8i16, 1}, // pblendw
1137 {TTI::SK_Select, MVT::v16i8, 1} // pblendvb
1138 };
1139
1140 if (ST->hasSSE41())
1141 if (const auto *Entry = CostTableLookup(SSE41ShuffleTbl, Kind, LT.second))
1142 return LT.first * Entry->Cost;
1143
1144 static const CostTblEntry SSSE3ShuffleTbl[] = {
1145 {TTI::SK_Broadcast, MVT::v8i16, 1}, // pshufb
1146 {TTI::SK_Broadcast, MVT::v16i8, 1}, // pshufb
1147
1148 {TTI::SK_Reverse, MVT::v8i16, 1}, // pshufb
1149 {TTI::SK_Reverse, MVT::v16i8, 1}, // pshufb
1150
1151 {TTI::SK_Select, MVT::v8i16, 3}, // 2*pshufb + por
1152 {TTI::SK_Select, MVT::v16i8, 3}, // 2*pshufb + por
1153
1154 {TTI::SK_PermuteSingleSrc, MVT::v8i16, 1}, // pshufb
1155 {TTI::SK_PermuteSingleSrc, MVT::v16i8, 1}, // pshufb
1156
1157 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 3}, // 2*pshufb + por
1158 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 3}, // 2*pshufb + por
1159 };
1160
1161 if (ST->hasSSSE3())
1162 if (const auto *Entry = CostTableLookup(SSSE3ShuffleTbl, Kind, LT.second))
1163 return LT.first * Entry->Cost;
1164
1165 static const CostTblEntry SSE2ShuffleTbl[] = {
1166 {TTI::SK_Broadcast, MVT::v2f64, 1}, // shufpd
1167 {TTI::SK_Broadcast, MVT::v2i64, 1}, // pshufd
1168 {TTI::SK_Broadcast, MVT::v4i32, 1}, // pshufd
1169 {TTI::SK_Broadcast, MVT::v8i16, 2}, // pshuflw + pshufd
1170 {TTI::SK_Broadcast, MVT::v16i8, 3}, // unpck + pshuflw + pshufd
1171
1172 {TTI::SK_Reverse, MVT::v2f64, 1}, // shufpd
1173 {TTI::SK_Reverse, MVT::v2i64, 1}, // pshufd
1174 {TTI::SK_Reverse, MVT::v4i32, 1}, // pshufd
1175 {TTI::SK_Reverse, MVT::v8i16, 3}, // pshuflw + pshufhw + pshufd
1176 {TTI::SK_Reverse, MVT::v16i8, 9}, // 2*pshuflw + 2*pshufhw
1177 // + 2*pshufd + 2*unpck + packus
1178
1179 {TTI::SK_Select, MVT::v2i64, 1}, // movsd
1180 {TTI::SK_Select, MVT::v2f64, 1}, // movsd
1181 {TTI::SK_Select, MVT::v4i32, 2}, // 2*shufps
1182 {TTI::SK_Select, MVT::v8i16, 3}, // pand + pandn + por
1183 {TTI::SK_Select, MVT::v16i8, 3}, // pand + pandn + por
1184
1185 {TTI::SK_PermuteSingleSrc, MVT::v2f64, 1}, // shufpd
1186 {TTI::SK_PermuteSingleSrc, MVT::v2i64, 1}, // pshufd
1187 {TTI::SK_PermuteSingleSrc, MVT::v4i32, 1}, // pshufd
1188 {TTI::SK_PermuteSingleSrc, MVT::v8i16, 5}, // 2*pshuflw + 2*pshufhw
1189 // + pshufd/unpck
1190 { TTI::SK_PermuteSingleSrc, MVT::v16i8, 10 }, // 2*pshuflw + 2*pshufhw
1191 // + 2*pshufd + 2*unpck + 2*packus
1192
1193 { TTI::SK_PermuteTwoSrc, MVT::v2f64, 1 }, // shufpd
1194 { TTI::SK_PermuteTwoSrc, MVT::v2i64, 1 }, // shufpd
1195 { TTI::SK_PermuteTwoSrc, MVT::v4i32, 2 }, // 2*{unpck,movsd,pshufd}
1196 { TTI::SK_PermuteTwoSrc, MVT::v8i16, 8 }, // blend+permute
1197 { TTI::SK_PermuteTwoSrc, MVT::v16i8, 13 }, // blend+permute
1198 };
1199
1200 if (ST->hasSSE2())
1201 if (const auto *Entry = CostTableLookup(SSE2ShuffleTbl, Kind, LT.second))
1202 return LT.first * Entry->Cost;
1203
1204 static const CostTblEntry SSE1ShuffleTbl[] = {
1205 { TTI::SK_Broadcast, MVT::v4f32, 1 }, // shufps
1206 { TTI::SK_Reverse, MVT::v4f32, 1 }, // shufps
1207 { TTI::SK_Select, MVT::v4f32, 2 }, // 2*shufps
1208 { TTI::SK_PermuteSingleSrc, MVT::v4f32, 1 }, // shufps
1209 { TTI::SK_PermuteTwoSrc, MVT::v4f32, 2 }, // 2*shufps
1210 };
1211
1212 if (ST->hasSSE1())
1213 if (const auto *Entry = CostTableLookup(SSE1ShuffleTbl, Kind, LT.second))
1214 return LT.first * Entry->Cost;
1215
1216 return BaseT::getShuffleCost(Kind, Tp, Index, SubTp);
1217}
1218
1219int X86TTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src,
1220 const Instruction *I) {
1221 int ISD = TLI->InstructionOpcodeToISD(Opcode);
1222 assert(ISD && "Invalid opcode")((ISD && "Invalid opcode") ? static_cast<void> (
0) : __assert_fail ("ISD && \"Invalid opcode\"", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86TargetTransformInfo.cpp"
, 1222, __PRETTY_FUNCTION__))
;
1223
1224 // FIXME: Need a better design of the cost table to handle non-simple types of
1225 // potential massive combinations (elem_num x src_type x dst_type).
1226
1227 static const TypeConversionCostTblEntry AVX512BWConversionTbl[] {
1228 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i8, 1 },
1229 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i8, 1 },
1230
1231 // Mask sign extend has an instruction.
1232 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 1 },
1233 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 1 },
1234 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 },
1235 { ISD::SIGN_EXTEND, MVT::v32i8, MVT::v32i1, 1 },
1236 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i1, 1 },
1237 { ISD::SIGN_EXTEND, MVT::v64i8, MVT::v64i1, 1 },
1238
1239 // Mask zero extend is a load + broadcast.
1240 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 2 },
1241 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 2 },
1242 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 2 },
1243 { ISD::ZERO_EXTEND, MVT::v32i8, MVT::v32i1, 2 },
1244 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i1, 2 },
1245 { ISD::ZERO_EXTEND, MVT::v64i8, MVT::v64i1, 2 },
1246 };
1247
1248 static const TypeConversionCostTblEntry AVX512DQConversionTbl[] = {
1249 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i64, 1 },
1250 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 },
1251 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i64, 1 },
1252 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 1 },
1253 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 },
1254 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 },
1255
1256 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 1 },
1257 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 },
1258 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i64, 1 },
1259 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 1 },
1260 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 },
1261 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 },
1262
1263 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f32, 1 },
1264 { ISD::FP_TO_SINT, MVT::v4i64, MVT::v4f32, 1 },
1265 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f32, 1 },
1266 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f64, 1 },
1267 { ISD::FP_TO_SINT, MVT::v4i64, MVT::v4f64, 1 },
1268 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f64, 1 },
1269
1270 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f32, 1 },
1271 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f32, 1 },
1272 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f32, 1 },
1273 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f64, 1 },
1274 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f64, 1 },
1275 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f64, 1 },
1276 };
1277
1278 // TODO: For AVX512DQ + AVX512VL, we also have cheap casts for 128-bit and
1279 // 256-bit wide vectors.
1280
1281 static const TypeConversionCostTblEntry AVX512FConversionTbl[] = {
1282 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 1 },
1283 { ISD::FP_EXTEND, MVT::v8f64, MVT::v16f32, 3 },
1284 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 1 },
1285
1286 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 1 },
1287 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 1 },
1288 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i64, 1 },
1289 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 1 },
1290
1291 // v16i1 -> v16i32 - load + broadcast
1292 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i1, 2 },
1293 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i1, 2 },
1294 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 1 },
1295 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 1 },
1296 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 1 },
1297 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 1 },
1298 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i16, 1 },
1299 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 1 },
1300 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i32, 1 },
1301 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i32, 1 },
1302
1303 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 },
1304 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 },
1305 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i8, 2 },
1306 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i8, 2 },
1307 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 },
1308 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, 2 },
1309 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 },
1310 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 },
1311
1312 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 },
1313 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 },
1314 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i8, 2 },
1315 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i8, 2 },
1316 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 2 },
1317 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i8, 2 },
1318 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i8, 2 },
1319 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i16, 5 },
1320 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i16, 2 },
1321 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 2 },
1322 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 },
1323 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i16, 2 },
1324 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 2 },
1325 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 1 },
1326 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
1327 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 },
1328 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 },
1329 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 },
1330 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 },
1331 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 5 },
1332 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, 26 },
1333 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 5 },
1334 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 5 },
1335 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 5 },
1336
1337 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 1 },
1338
1339 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f32, 1 },
1340 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 },
1341 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 1 },
1342 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 1 },
1343 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f64, 2 },
1344 { ISD::FP_TO_UINT, MVT::v8i8, MVT::v8f64, 2 },
1345 { ISD::FP_TO_UINT, MVT::v16i32, MVT::v16f32, 1 },
1346 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v16f32, 2 },
1347 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v16f32, 2 },
1348 };
1349
1350 static const TypeConversionCostTblEntry AVX2ConversionTbl[] = {
1351 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 3 },
1352 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 3 },
1353 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 3 },
1354 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 3 },
1355 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 3 },
1356 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 3 },
1357 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 3 },
1358 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 3 },
1359 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 1 },
1360 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 1 },
1361 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
1362 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
1363 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 1 },
1364 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 1 },
1365 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 1 },
1366 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 1 },
1367
1368 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 2 },
1369 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 2 },
1370 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 2 },
1371 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 2 },
1372 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 2 },
1373 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 4 },
1374
1375 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 3 },
1376 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 3 },
1377
1378 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 8 },
1379 };
1380
1381 static const TypeConversionCostTblEntry AVXConversionTbl[] = {
1382 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 6 },
1383 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 4 },
1384 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 7 },
1385 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 4 },
1386 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 6 },
1387 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 4 },
1388 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 7 },
1389 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 4 },
1390 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 4 },
1391 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 4 },
1392 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 6 },
1393 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
1394 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 4 },
1395 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 4 },
1396 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 4 },
1397 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 4 },
1398
1399 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 4 },
1400 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 4 },
1401 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 5 },
1402 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 4 },
1403 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 4 },
1404 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 4 },
1405 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 9 },
1406
1407 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 },
1408 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i1, 3 },
1409 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i1, 8 },
1410 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 },
1411 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i8, 3 },
1412 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i8, 8 },
1413 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 3 },
1414 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i16, 3 },
1415 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 5 },
1416 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
1417 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 },
1418 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 },
1419
1420 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i1, 7 },
1421 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i1, 7 },
1422 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i1, 6 },
1423 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 2 },
1424 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i8, 2 },
1425 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 5 },
1426 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
1427 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i16, 2 },
1428 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 5 },
1429 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 6 },
1430 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 6 },
1431 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 6 },
1432 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 9 },
1433 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 5 },
1434 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 6 },
1435 // The generic code to compute the scalar overhead is currently broken.
1436 // Workaround this limitation by estimating the scalarization overhead
1437 // here. We have roughly 10 instructions per scalar element.
1438 // Multiply that by the vector width.
1439 // FIXME: remove that when PR19268 is fixed.
1440 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 13 },
1441 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 13 },
1442
1443 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 1 },
1444 { ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f32, 7 },
1445 // This node is expanded into scalarized operations but BasicTTI is overly
1446 // optimistic estimating its cost. It computes 3 per element (one
1447 // vector-extract, one scalar conversion and one vector-insert). The
1448 // problem is that the inserts form a read-modify-write chain so latency
1449 // should be factored in too. Inflating the cost per element by 1.
1450 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 8*4 },
1451 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 4*4 },
1452
1453 { ISD::FP_EXTEND, MVT::v4f64, MVT::v4f32, 1 },
1454 { ISD::FP_ROUND, MVT::v4f32, MVT::v4f64, 1 },
1455 };
1456
1457 static const TypeConversionCostTblEntry SSE41ConversionTbl[] = {
1458 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 2 },
1459 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 2 },
1460 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 2 },
1461 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 2 },
1462 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 2 },
1463 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 2 },
1464
1465 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i8, 1 },
1466 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i8, 2 },
1467 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i8, 1 },
1468 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i8, 1 },
1469 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i8, 1 },
1470 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i8, 1 },
1471 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 2 },
1472 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 2 },
1473 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 2 },
1474 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 2 },
1475 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 4 },
1476 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 4 },
1477 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 1 },
1478 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 1 },
1479 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 2 },
1480 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 2 },
1481 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 4 },
1482 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 4 },
1483
1484 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i16, 2 },
1485 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i16, 1 },
1486 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i32, 1 },
1487 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 1 },
1488 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 3 },
1489 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 3 },
1490 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 6 },
1491
1492 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 4 },
1493 };
1494
1495 static const TypeConversionCostTblEntry SSE2ConversionTbl[] = {
1496 // These are somewhat magic numbers justified by looking at the output of
1497 // Intel's IACA, running some kernels and making sure when we take
1498 // legalization into account the throughput will be overestimated.
1499 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 },
1500 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 },
1501 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 },
1502 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 },
1503 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 5 },
1504 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v4i32, 4*10 },
1505 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 },
1506 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 2*10 },
1507
1508 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 },
1509 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 },
1510 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 },
1511 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 },
1512 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v4i32, 4*10 },
1513 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 8 },
1514 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 6 },
1515 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 },
1516
1517 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 3 },
1518
1519 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 6 },
1520
1521 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i8, 1 },
1522 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i8, 6 },
1523 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i8, 2 },
1524 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i8, 3 },
1525 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 4 },
1526 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 8 },
1527 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i8, 1 },
1528 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i8, 2 },
1529 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 6 },
1530 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 6 },
1531 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 3 },
1532 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 4 },
1533 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 9 },
1534 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 12 },
1535 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 1 },
1536 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 2 },
1537 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
1538 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 10 },
1539 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 3 },
1540 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 4 },
1541 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 6 },
1542 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 8 },
1543 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 3 },
1544 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 5 },
1545
1546 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i16, 4 },
1547 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i16, 2 },
1548 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 3 },
1549 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i32, 3 },
1550 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 3 },
1551 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 4 },
1552 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 7 },
1553 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 5 },
1554 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 10 },
1555 };
1556
1557 std::pair<int, MVT> LTSrc = TLI->getTypeLegalizationCost(DL, Src);
1558 std::pair<int, MVT> LTDest = TLI->getTypeLegalizationCost(DL, Dst);
1559
1560 if (ST->hasSSE2() && !ST->hasAVX()) {
1561 if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD,
1562 LTDest.second, LTSrc.second))
1563 return LTSrc.first * Entry->Cost;
1564 }
1565
1566 EVT SrcTy = TLI->getValueType(DL, Src);
1567 EVT DstTy = TLI->getValueType(DL, Dst);
1568
1569 // The function getSimpleVT only handles simple value types.
1570 if (!SrcTy.isSimple() || !DstTy.isSimple())
1571 return BaseT::getCastInstrCost(Opcode, Dst, Src);
1572
1573 MVT SimpleSrcTy = SrcTy.getSimpleVT();
1574 MVT SimpleDstTy = DstTy.getSimpleVT();
1575
1576 // Make sure that neither type is going to be split before using the
1577 // AVX512 tables. This handles -mprefer-vector-width=256
1578 // with -min-legal-vector-width<=256
1579 if (TLI->getTypeAction(SimpleSrcTy) != TargetLowering::TypeSplitVector &&
1580 TLI->getTypeAction(SimpleDstTy) != TargetLowering::TypeSplitVector) {
1581 if (ST->hasBWI())
1582 if (const auto *Entry = ConvertCostTableLookup(AVX512BWConversionTbl, ISD,
1583 SimpleDstTy, SimpleSrcTy))
1584 return Entry->Cost;
1585
1586 if (ST->hasDQI())
1587 if (const auto *Entry = ConvertCostTableLookup(AVX512DQConversionTbl, ISD,
1588 SimpleDstTy, SimpleSrcTy))
1589 return Entry->Cost;
1590
1591 if (ST->hasAVX512())
1592 if (const auto *Entry = ConvertCostTableLookup(AVX512FConversionTbl, ISD,
1593 SimpleDstTy, SimpleSrcTy))
1594 return Entry->Cost;
1595 }
1596
1597 if (ST->hasAVX2()) {
1598 if (const auto *Entry = ConvertCostTableLookup(AVX2ConversionTbl, ISD,
1599 SimpleDstTy, SimpleSrcTy))
1600 return Entry->Cost;
1601 }
1602
1603 if (ST->hasAVX()) {
1604 if (const auto *Entry = ConvertCostTableLookup(AVXConversionTbl, ISD,
1605 SimpleDstTy, SimpleSrcTy))
1606 return Entry->Cost;
1607 }
1608
1609 if (ST->hasSSE41()) {
1610 if (const auto *Entry = ConvertCostTableLookup(SSE41ConversionTbl, ISD,
1611 SimpleDstTy, SimpleSrcTy))
1612 return Entry->Cost;
1613 }
1614
1615 if (ST->hasSSE2()) {
1616 if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD,
1617 SimpleDstTy, SimpleSrcTy))
1618 return Entry->Cost;
1619 }
1620
1621 return BaseT::getCastInstrCost(Opcode, Dst, Src, I);
1622}
1623
1624int X86TTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy,
1625 const Instruction *I) {
1626 // Legalize the type.
1627 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy);
1628
1629 MVT MTy = LT.second;
1630
1631 int ISD = TLI->InstructionOpcodeToISD(Opcode);
1632 assert(ISD && "Invalid opcode")((ISD && "Invalid opcode") ? static_cast<void> (
0) : __assert_fail ("ISD && \"Invalid opcode\"", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86TargetTransformInfo.cpp"
, 1632, __PRETTY_FUNCTION__))
;
1633
1634 static const CostTblEntry SSE2CostTbl[] = {
1635 { ISD::SETCC, MVT::v2i64, 8 },
1636 { ISD::SETCC, MVT::v4i32, 1 },
1637 { ISD::SETCC, MVT::v8i16, 1 },
1638 { ISD::SETCC, MVT::v16i8, 1 },
1639 };
1640
1641 static const CostTblEntry SSE42CostTbl[] = {
1642 { ISD::SETCC, MVT::v2f64, 1 },
1643 { ISD::SETCC, MVT::v4f32, 1 },
1644 { ISD::SETCC, MVT::v2i64, 1 },
1645 };
1646
1647 static const CostTblEntry AVX1CostTbl[] = {
1648 { ISD::SETCC, MVT::v4f64, 1 },
1649 { ISD::SETCC, MVT::v8f32, 1 },
1650 // AVX1 does not support 8-wide integer compare.
1651 { ISD::SETCC, MVT::v4i64, 4 },
1652 { ISD::SETCC, MVT::v8i32, 4 },
1653 { ISD::SETCC, MVT::v16i16, 4 },
1654 { ISD::SETCC, MVT::v32i8, 4 },
1655 };
1656
1657 static const CostTblEntry AVX2CostTbl[] = {
1658 { ISD::SETCC, MVT::v4i64, 1 },
1659 { ISD::SETCC, MVT::v8i32, 1 },
1660 { ISD::SETCC, MVT::v16i16, 1 },
1661 { ISD::SETCC, MVT::v32i8, 1 },
1662 };
1663
1664 static const CostTblEntry AVX512CostTbl[] = {
1665 { ISD::SETCC, MVT::v8i64, 1 },
1666 { ISD::SETCC, MVT::v16i32, 1 },
1667 { ISD::SETCC, MVT::v8f64, 1 },
1668 { ISD::SETCC, MVT::v16f32, 1 },
1669 };
1670
1671 static const CostTblEntry AVX512BWCostTbl[] = {
1672 { ISD::SETCC, MVT::v32i16, 1 },
1673 { ISD::SETCC, MVT::v64i8, 1 },
1674 };
1675
1676 if (ST->hasBWI())
1677 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy))
1678 return LT.first * Entry->Cost;
1679
1680 if (ST->hasAVX512())
1681 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy))
1682 return LT.first * Entry->Cost;
1683
1684 if (ST->hasAVX2())
1685 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy))
1686 return LT.first * Entry->Cost;
1687
1688 if (ST->hasAVX())
1689 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy))
1690 return LT.first * Entry->Cost;
1691
1692 if (ST->hasSSE42())
1693 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy))
1694 return LT.first * Entry->Cost;
1695
1696 if (ST->hasSSE2())
1697 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy))
1698 return LT.first * Entry->Cost;
1699
1700 return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy, I);
1701}
1702
1703unsigned X86TTIImpl::getAtomicMemIntrinsicMaxElementSize() const { return 16; }
1704
1705int X86TTIImpl::getIntrinsicInstrCost(Intrinsic::ID IID, Type *RetTy,
1706 ArrayRef<Type *> Tys, FastMathFlags FMF,
1707 unsigned ScalarizationCostPassed) {
1708 // Costs should match the codegen from:
1709 // BITREVERSE: llvm\test\CodeGen\X86\vector-bitreverse.ll
1710 // BSWAP: llvm\test\CodeGen\X86\bswap-vector.ll
1711 // CTLZ: llvm\test\CodeGen\X86\vector-lzcnt-*.ll
1712 // CTPOP: llvm\test\CodeGen\X86\vector-popcnt-*.ll
1713 // CTTZ: llvm\test\CodeGen\X86\vector-tzcnt-*.ll
1714 static const CostTblEntry AVX512CDCostTbl[] = {
1715 { ISD::CTLZ, MVT::v8i64, 1 },
1716 { ISD::CTLZ, MVT::v16i32, 1 },
1717 { ISD::CTLZ, MVT::v32i16, 8 },
1718 { ISD::CTLZ, MVT::v64i8, 20 },
1719 { ISD::CTLZ, MVT::v4i64, 1 },
1720 { ISD::CTLZ, MVT::v8i32, 1 },
1721 { ISD::CTLZ, MVT::v16i16, 4 },
1722 { ISD::CTLZ, MVT::v32i8, 10 },
1723 { ISD::CTLZ, MVT::v2i64, 1 },
1724 { ISD::CTLZ, MVT::v4i32, 1 },
1725 { ISD::CTLZ, MVT::v8i16, 4 },
1726 { ISD::CTLZ, MVT::v16i8, 4 },
1727 };
1728 static const CostTblEntry AVX512BWCostTbl[] = {
1729 { ISD::BITREVERSE, MVT::v8i64, 5 },
1730 { ISD::BITREVERSE, MVT::v16i32, 5 },
1731 { ISD::BITREVERSE, MVT::v32i16, 5 },
1732 { ISD::BITREVERSE, MVT::v64i8, 5 },
1733 { ISD::CTLZ, MVT::v8i64, 23 },
1734 { ISD::CTLZ, MVT::v16i32, 22 },
1735 { ISD::CTLZ, MVT::v32i16, 18 },
1736 { ISD::CTLZ, MVT::v64i8, 17 },
1737 { ISD::CTPOP, MVT::v8i64, 7 },
1738 { ISD::CTPOP, MVT::v16i32, 11 },
1739 { ISD::CTPOP, MVT::v32i16, 9 },
1740 { ISD::CTPOP, MVT::v64i8, 6 },
1741 { ISD::CTTZ, MVT::v8i64, 10 },
1742 { ISD::CTTZ, MVT::v16i32, 14 },
1743 { ISD::CTTZ, MVT::v32i16, 12 },
1744 { ISD::CTTZ, MVT::v64i8, 9 },
1745 };
1746 static const CostTblEntry AVX512CostTbl[] = {
1747 { ISD::BITREVERSE, MVT::v8i64, 36 },
1748 { ISD::BITREVERSE, MVT::v16i32, 24 },
1749 { ISD::CTLZ, MVT::v8i64, 29 },
1750 { ISD::CTLZ, MVT::v16i32, 35 },
1751 { ISD::CTPOP, MVT::v8i64, 16 },
1752 { ISD::CTPOP, MVT::v16i32, 24 },
1753 { ISD::CTTZ, MVT::v8i64, 20 },
1754 { ISD::CTTZ, MVT::v16i32, 28 },
1755 };
1756 static const CostTblEntry XOPCostTbl[] = {
1757 { ISD::BITREVERSE, MVT::v4i64, 4 },
1758 { ISD::BITREVERSE, MVT::v8i32, 4 },
1759 { ISD::BITREVERSE, MVT::v16i16, 4 },
1760 { ISD::BITREVERSE, MVT::v32i8, 4 },
1761 { ISD::BITREVERSE, MVT::v2i64, 1 },
1762 { ISD::BITREVERSE, MVT::v4i32, 1 },
1763 { ISD::BITREVERSE, MVT::v8i16, 1 },
1764 { ISD::BITREVERSE, MVT::v16i8, 1 },
1765 { ISD::BITREVERSE, MVT::i64, 3 },
1766 { ISD::BITREVERSE, MVT::i32, 3 },
1767 { ISD::BITREVERSE, MVT::i16, 3 },
1768 { ISD::BITREVERSE, MVT::i8, 3 }
1769 };
1770 static const CostTblEntry AVX2CostTbl[] = {
1771 { ISD::BITREVERSE, MVT::v4i64, 5 },
1772 { ISD::BITREVERSE, MVT::v8i32, 5 },
1773 { ISD::BITREVERSE, MVT::v16i16, 5 },
1774 { ISD::BITREVERSE, MVT::v32i8, 5 },
1775 { ISD::BSWAP, MVT::v4i64, 1 },
1776 { ISD::BSWAP, MVT::v8i32, 1 },
1777 { ISD::BSWAP, MVT::v16i16, 1 },
1778 { ISD::CTLZ, MVT::v4i64, 23 },
1779 { ISD::CTLZ, MVT::v8i32, 18 },
1780 { ISD::CTLZ, MVT::v16i16, 14 },
1781 { ISD::CTLZ, MVT::v32i8, 9 },
1782 { ISD::CTPOP, MVT::v4i64, 7 },
1783 { ISD::CTPOP, MVT::v8i32, 11 },
1784 { ISD::CTPOP, MVT::v16i16, 9 },
1785 { ISD::CTPOP, MVT::v32i8, 6 },
1786 { ISD::CTTZ, MVT::v4i64, 10 },
1787 { ISD::CTTZ, MVT::v8i32, 14 },
1788 { ISD::CTTZ, MVT::v16i16, 12 },
1789 { ISD::CTTZ, MVT::v32i8, 9 },
1790 { ISD::FSQRT, MVT::f32, 7 }, // Haswell from http://www.agner.org/
1791 { ISD::FSQRT, MVT::v4f32, 7 }, // Haswell from http://www.agner.org/
1792 { ISD::FSQRT, MVT::v8f32, 14 }, // Haswell from http://www.agner.org/
1793 { ISD::FSQRT, MVT::f64, 14 }, // Haswell from http://www.agner.org/
1794 { ISD::FSQRT, MVT::v2f64, 14 }, // Haswell from http://www.agner.org/
1795 { ISD::FSQRT, MVT::v4f64, 28 }, // Haswell from http://www.agner.org/
1796 };
1797 static const CostTblEntry AVX1CostTbl[] = {
1798 { ISD::BITREVERSE, MVT::v4i64, 12 }, // 2 x 128-bit Op + extract/insert
1799 { ISD::BITREVERSE, MVT::v8i32, 12 }, // 2 x 128-bit Op + extract/insert
1800 { ISD::BITREVERSE, MVT::v16i16, 12 }, // 2 x 128-bit Op + extract/insert
1801 { ISD::BITREVERSE, MVT::v32i8, 12 }, // 2 x 128-bit Op + extract/insert
1802 { ISD::BSWAP, MVT::v4i64, 4 },
1803 { ISD::BSWAP, MVT::v8i32, 4 },
1804 { ISD::BSWAP, MVT::v16i16, 4 },
1805 { ISD::CTLZ, MVT::v4i64, 48 }, // 2 x 128-bit Op + extract/insert
1806 { ISD::CTLZ, MVT::v8i32, 38 }, // 2 x 128-bit Op + extract/insert
1807 { ISD::CTLZ, MVT::v16i16, 30 }, // 2 x 128-bit Op + extract/insert
1808 { ISD::CTLZ, MVT::v32i8, 20 }, // 2 x 128-bit Op + extract/insert
1809 { ISD::CTPOP, MVT::v4i64, 16 }, // 2 x 128-bit Op + extract/insert
1810 { ISD::CTPOP, MVT::v8i32, 24 }, // 2 x 128-bit Op + extract/insert
1811 { ISD::CTPOP, MVT::v16i16, 20 }, // 2 x 128-bit Op + extract/insert
1812 { ISD::CTPOP, MVT::v32i8, 14 }, // 2 x 128-bit Op + extract/insert
1813 { ISD::CTTZ, MVT::v4i64, 22 }, // 2 x 128-bit Op + extract/insert
1814 { ISD::CTTZ, MVT::v8i32, 30 }, // 2 x 128-bit Op + extract/insert
1815 { ISD::CTTZ, MVT::v16i16, 26 }, // 2 x 128-bit Op + extract/insert
1816 { ISD::CTTZ, MVT::v32i8, 20 }, // 2 x 128-bit Op + extract/insert
1817 { ISD::FSQRT, MVT::f32, 14 }, // SNB from http://www.agner.org/
1818 { ISD::FSQRT, MVT::v4f32, 14 }, // SNB from http://www.agner.org/
1819 { ISD::FSQRT, MVT::v8f32, 28 }, // SNB from http://www.agner.org/
1820 { ISD::FSQRT, MVT::f64, 21 }, // SNB from http://www.agner.org/
1821 { ISD::FSQRT, MVT::v2f64, 21 }, // SNB from http://www.agner.org/
1822 { ISD::FSQRT, MVT::v4f64, 43 }, // SNB from http://www.agner.org/
1823 };
1824 static const CostTblEntry GLMCostTbl[] = {
1825 { ISD::FSQRT, MVT::f32, 19 }, // sqrtss
1826 { ISD::FSQRT, MVT::v4f32, 37 }, // sqrtps
1827 { ISD::FSQRT, MVT::f64, 34 }, // sqrtsd
1828 { ISD::FSQRT, MVT::v2f64, 67 }, // sqrtpd
1829 };
1830 static const CostTblEntry SLMCostTbl[] = {
1831 { ISD::FSQRT, MVT::f32, 20 }, // sqrtss
1832 { ISD::FSQRT, MVT::v4f32, 40 }, // sqrtps
1833 { ISD::FSQRT, MVT::f64, 35 }, // sqrtsd
1834 { ISD::FSQRT, MVT::v2f64, 70 }, // sqrtpd
1835 };
1836 static const CostTblEntry SSE42CostTbl[] = {
1837 { ISD::FSQRT, MVT::f32, 18 }, // Nehalem from http://www.agner.org/
1838 { ISD::FSQRT, MVT::v4f32, 18 }, // Nehalem from http://www.agner.org/
1839 };
1840 static const CostTblEntry SSSE3CostTbl[] = {
1841 { ISD::BITREVERSE, MVT::v2i64, 5 },
1842 { ISD::BITREVERSE, MVT::v4i32, 5 },
1843 { ISD::BITREVERSE, MVT::v8i16, 5 },
1844 { ISD::BITREVERSE, MVT::v16i8, 5 },
1845 { ISD::BSWAP, MVT::v2i64, 1 },
1846 { ISD::BSWAP, MVT::v4i32, 1 },
1847 { ISD::BSWAP, MVT::v8i16, 1 },
1848 { ISD::CTLZ, MVT::v2i64, 23 },
1849 { ISD::CTLZ, MVT::v4i32, 18 },
1850 { ISD::CTLZ, MVT::v8i16, 14 },
1851 { ISD::CTLZ, MVT::v16i8, 9 },
1852 { ISD::CTPOP, MVT::v2i64, 7 },
1853 { ISD::CTPOP, MVT::v4i32, 11 },
1854 { ISD::CTPOP, MVT::v8i16, 9 },
1855 { ISD::CTPOP, MVT::v16i8, 6 },
1856 { ISD::CTTZ, MVT::v2i64, 10 },
1857 { ISD::CTTZ, MVT::v4i32, 14 },
1858 { ISD::CTTZ, MVT::v8i16, 12 },
1859 { ISD::CTTZ, MVT::v16i8, 9 }
1860 };
1861 static const CostTblEntry SSE2CostTbl[] = {
1862 { ISD::BITREVERSE, MVT::v2i64, 29 },
1863 { ISD::BITREVERSE, MVT::v4i32, 27 },
1864 { ISD::BITREVERSE, MVT::v8i16, 27 },
1865 { ISD::BITREVERSE, MVT::v16i8, 20 },
1866 { ISD::BSWAP, MVT::v2i64, 7 },
1867 { ISD::BSWAP, MVT::v4i32, 7 },
1868 { ISD::BSWAP, MVT::v8i16, 7 },
1869 { ISD::CTLZ, MVT::v2i64, 25 },
1870 { ISD::CTLZ, MVT::v4i32, 26 },
1871 { ISD::CTLZ, MVT::v8i16, 20 },
1872 { ISD::CTLZ, MVT::v16i8, 17 },
1873 { ISD::CTPOP, MVT::v2i64, 12 },
1874 { ISD::CTPOP, MVT::v4i32, 15 },
1875 { ISD::CTPOP, MVT::v8i16, 13 },
1876 { ISD::CTPOP, MVT::v16i8, 10 },
1877 { ISD::CTTZ, MVT::v2i64, 14 },
1878 { ISD::CTTZ, MVT::v4i32, 18 },
1879 { ISD::CTTZ, MVT::v8i16, 16 },
1880 { ISD::CTTZ, MVT::v16i8, 13 },
1881 { ISD::FSQRT, MVT::f64, 32 }, // Nehalem from http://www.agner.org/
1882 { ISD::FSQRT, MVT::v2f64, 32 }, // Nehalem from http://www.agner.org/
1883 };
1884 static const CostTblEntry SSE1CostTbl[] = {
1885 { ISD::FSQRT, MVT::f32, 28 }, // Pentium III from http://www.agner.org/
1886 { ISD::FSQRT, MVT::v4f32, 56 }, // Pentium III from http://www.agner.org/
1887 };
1888 static const CostTblEntry X64CostTbl[] = { // 64-bit targets
1889 { ISD::BITREVERSE, MVT::i64, 14 }
1890 };
1891 static const CostTblEntry X86CostTbl[] = { // 32 or 64-bit targets
1892 { ISD::BITREVERSE, MVT::i32, 14 },
1893 { ISD::BITREVERSE, MVT::i16, 14 },
1894 { ISD::BITREVERSE, MVT::i8, 11 }
1895 };
1896
1897 unsigned ISD = ISD::DELETED_NODE;
1898 switch (IID) {
1899 default:
1900 break;
1901 case Intrinsic::bitreverse:
1902 ISD = ISD::BITREVERSE;
1903 break;
1904 case Intrinsic::bswap:
1905 ISD = ISD::BSWAP;
1906 break;
1907 case Intrinsic::ctlz:
1908 ISD = ISD::CTLZ;
1909 break;
1910 case Intrinsic::ctpop:
1911 ISD = ISD::CTPOP;
1912 break;
1913 case Intrinsic::cttz:
1914 ISD = ISD::CTTZ;
1915 break;
1916 case Intrinsic::sqrt:
1917 ISD = ISD::FSQRT;
1918 break;
1919 }
1920
1921 if (ISD != ISD::DELETED_NODE) {
1922 // Legalize the type.
1923 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, RetTy);
1924 MVT MTy = LT.second;
1925
1926 // Attempt to lookup cost.
1927 if (ST->isGLM())
1928 if (const auto *Entry = CostTableLookup(GLMCostTbl, ISD, MTy))
1929 return LT.first * Entry->Cost;
1930
1931 if (ST->isSLM())
1932 if (const auto *Entry = CostTableLookup(SLMCostTbl, ISD, MTy))
1933 return LT.first * Entry->Cost;
1934
1935 if (ST->hasCDI())
1936 if (const auto *Entry = CostTableLookup(AVX512CDCostTbl, ISD, MTy))
1937 return LT.first * Entry->Cost;
1938
1939 if (ST->hasBWI())
1940 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy))
1941 return LT.first * Entry->Cost;
1942
1943 if (ST->hasAVX512())
1944 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy))
1945 return LT.first * Entry->Cost;
1946
1947 if (ST->hasXOP())
1948 if (const auto *Entry = CostTableLookup(XOPCostTbl, ISD, MTy))
1949 return LT.first * Entry->Cost;
1950
1951 if (ST->hasAVX2())
1952 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy))
1953 return LT.first * Entry->Cost;
1954
1955 if (ST->hasAVX())
1956 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy))
1957 return LT.first * Entry->Cost;
1958
1959 if (ST->hasSSE42())
1960 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy))
1961 return LT.first * Entry->Cost;
1962
1963 if (ST->hasSSSE3())
1964 if (const auto *Entry = CostTableLookup(SSSE3CostTbl, ISD, MTy))
1965 return LT.first * Entry->Cost;
1966
1967 if (ST->hasSSE2())
1968 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy))
1969 return LT.first * Entry->Cost;
1970
1971 if (ST->hasSSE1())
1972 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy))
1973 return LT.first * Entry->Cost;
1974
1975 if (ST->is64Bit())
1976 if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, MTy))
1977 return LT.first * Entry->Cost;
1978
1979 if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, MTy))
1980 return LT.first * Entry->Cost;
1981 }
1982
1983 return BaseT::getIntrinsicInstrCost(IID, RetTy, Tys, FMF, ScalarizationCostPassed);
1984}
1985
1986int X86TTIImpl::getIntrinsicInstrCost(Intrinsic::ID IID, Type *RetTy,
1987 ArrayRef<Value *> Args, FastMathFlags FMF,
1988 unsigned VF) {
1989 static const CostTblEntry AVX512CostTbl[] = {
1990 { ISD::ROTL, MVT::v8i64, 1 },
1991 { ISD::ROTL, MVT::v4i64, 1 },
1992 { ISD::ROTL, MVT::v2i64, 1 },
1993 { ISD::ROTL, MVT::v16i32, 1 },
1994 { ISD::ROTL, MVT::v8i32, 1 },
1995 { ISD::ROTL, MVT::v4i32, 1 },
1996 { ISD::ROTR, MVT::v8i64, 1 },
1997 { ISD::ROTR, MVT::v4i64, 1 },
1998 { ISD::ROTR, MVT::v2i64, 1 },
1999 { ISD::ROTR, MVT::v16i32, 1 },
2000 { ISD::ROTR, MVT::v8i32, 1 },
2001 { ISD::ROTR, MVT::v4i32, 1 }
2002 };
2003 // XOP: ROTL = VPROT(X,Y), ROTR = VPROT(X,SUB(0,Y))
2004 static const CostTblEntry XOPCostTbl[] = {
2005 { ISD::ROTL, MVT::v4i64, 4 },
2006 { ISD::ROTL, MVT::v8i32, 4 },
2007 { ISD::ROTL, MVT::v16i16, 4 },
2008 { ISD::ROTL, MVT::v32i8, 4 },
2009 { ISD::ROTL, MVT::v2i64, 1 },
2010 { ISD::ROTL, MVT::v4i32, 1 },
2011 { ISD::ROTL, MVT::v8i16, 1 },
2012 { ISD::ROTL, MVT::v16i8, 1 },
2013 { ISD::ROTR, MVT::v4i64, 6 },
2014 { ISD::ROTR, MVT::v8i32, 6 },
2015 { ISD::ROTR, MVT::v16i16, 6 },
2016 { ISD::ROTR, MVT::v32i8, 6 },
2017 { ISD::ROTR, MVT::v2i64, 2 },
2018 { ISD::ROTR, MVT::v4i32, 2 },
2019 { ISD::ROTR, MVT::v8i16, 2 },
2020 { ISD::ROTR, MVT::v16i8, 2 }
2021 };
2022 static const CostTblEntry X64CostTbl[] = { // 64-bit targets
2023 { ISD::ROTL, MVT::i64, 1 },
2024 { ISD::ROTR, MVT::i64, 1 },
2025 { ISD::FSHL, MVT::i64, 4 }
2026 };
2027 static const CostTblEntry X86CostTbl[] = { // 32 or 64-bit targets
2028 { ISD::ROTL, MVT::i32, 1 },
2029 { ISD::ROTL, MVT::i16, 1 },
2030 { ISD::ROTL, MVT::i8, 1 },
2031 { ISD::ROTR, MVT::i32, 1 },
2032 { ISD::ROTR, MVT::i16, 1 },
2033 { ISD::ROTR, MVT::i8, 1 },
2034 { ISD::FSHL, MVT::i32, 4 },
2035 { ISD::FSHL, MVT::i16, 4 },
2036 { ISD::FSHL, MVT::i8, 4 }
2037 };
2038
2039 unsigned ISD = ISD::DELETED_NODE;
2040 switch (IID) {
2041 default:
2042 break;
2043 case Intrinsic::fshl:
2044 ISD = ISD::FSHL;
2045 if (Args[0] == Args[1])
2046 ISD = ISD::ROTL;
2047 break;
2048 case Intrinsic::fshr:
2049 // FSHR has same costs so don't duplicate.
2050 ISD = ISD::FSHL;
2051 if (Args[0] == Args[1])
2052 ISD = ISD::ROTR;
2053 break;
2054 }
2055
2056 if (ISD != ISD::DELETED_NODE) {
2057 // Legalize the type.
2058 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, RetTy);
2059 MVT MTy = LT.second;
2060
2061 // Attempt to lookup cost.
2062 if (ST->hasAVX512())
2063 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy))
2064 return LT.first * Entry->Cost;
2065
2066 if (ST->hasXOP())
2067 if (const auto *Entry = CostTableLookup(XOPCostTbl, ISD, MTy))
2068 return LT.first * Entry->Cost;
2069
2070 if (ST->is64Bit())
2071 if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, MTy))
2072 return LT.first * Entry->Cost;
2073
2074 if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, MTy))
2075 return LT.first * Entry->Cost;
2076 }
2077
2078 return BaseT::getIntrinsicInstrCost(IID, RetTy, Args, FMF, VF);
2079}
2080
2081int X86TTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index) {
2082 assert(Val->isVectorTy() && "This must be a vector type")((Val->isVectorTy() && "This must be a vector type"
) ? static_cast<void> (0) : __assert_fail ("Val->isVectorTy() && \"This must be a vector type\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86TargetTransformInfo.cpp"
, 2082, __PRETTY_FUNCTION__))
;
2083
2084 Type *ScalarType = Val->getScalarType();
2085
2086 if (Index != -1U) {
2087 // Legalize the type.
2088 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Val);
2089
2090 // This type is legalized to a scalar type.
2091 if (!LT.second.isVector())
2092 return 0;
2093
2094 // The type may be split. Normalize the index to the new type.
2095 unsigned Width = LT.second.getVectorNumElements();
2096 Index = Index % Width;
2097
2098 // Floating point scalars are already located in index #0.
2099 if (ScalarType->isFloatingPointTy() && Index == 0)
2100 return 0;
2101 }
2102
2103 // Add to the base cost if we know that the extracted element of a vector is
2104 // destined to be moved to and used in the integer register file.
2105 int RegisterFileMoveCost = 0;
2106 if (Opcode == Instruction::ExtractElement && ScalarType->isPointerTy())
2107 RegisterFileMoveCost = 1;
2108
2109 return BaseT::getVectorInstrCost(Opcode, Val, Index) + RegisterFileMoveCost;
2110}
2111
2112int X86TTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment,
2113 unsigned AddressSpace, const Instruction *I) {
2114 // Handle non-power-of-two vectors such as <3 x float>
2115 if (VectorType *VTy = dyn_cast<VectorType>(Src)) {
2116 unsigned NumElem = VTy->getVectorNumElements();
2117
2118 // Handle a few common cases:
2119 // <3 x float>
2120 if (NumElem == 3 && VTy->getScalarSizeInBits() == 32)
2121 // Cost = 64 bit store + extract + 32 bit store.
2122 return 3;
2123
2124 // <3 x double>
2125 if (NumElem == 3 && VTy->getScalarSizeInBits() == 64)
2126 // Cost = 128 bit store + unpack + 64 bit store.
2127 return 3;
2128
2129 // Assume that all other non-power-of-two numbers are scalarized.
2130 if (!isPowerOf2_32(NumElem)) {
2131 int Cost = BaseT::getMemoryOpCost(Opcode, VTy->getScalarType(), Alignment,
2132 AddressSpace);
2133 int SplitCost = getScalarizationOverhead(Src, Opcode == Instruction::Load,
2134 Opcode == Instruction::Store);
2135 return NumElem * Cost + SplitCost;
2136 }
2137 }
2138
2139 // Legalize the type.
2140 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Src);
2141 assert((Opcode == Instruction::Load || Opcode == Instruction::Store) &&(((Opcode == Instruction::Load || Opcode == Instruction::Store
) && "Invalid Opcode") ? static_cast<void> (0) :
__assert_fail ("(Opcode == Instruction::Load || Opcode == Instruction::Store) && \"Invalid Opcode\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86TargetTransformInfo.cpp"
, 2142, __PRETTY_FUNCTION__))
2142 "Invalid Opcode")(((Opcode == Instruction::Load || Opcode == Instruction::Store
) && "Invalid Opcode") ? static_cast<void> (0) :
__assert_fail ("(Opcode == Instruction::Load || Opcode == Instruction::Store) && \"Invalid Opcode\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86TargetTransformInfo.cpp"
, 2142, __PRETTY_FUNCTION__))
;
2143
2144 // Each load/store unit costs 1.
2145 int Cost = LT.first * 1;
2146
2147 // This isn't exactly right. We're using slow unaligned 32-byte accesses as a
2148 // proxy for a double-pumped AVX memory interface such as on Sandybridge.
2149 if (LT.second.getStoreSize() == 32 && ST->isUnalignedMem32Slow())
2150 Cost *= 2;
2151
2152 return Cost;
2153}
2154
2155int X86TTIImpl::getMaskedMemoryOpCost(unsigned Opcode, Type *SrcTy,
2156 unsigned Alignment,
2157 unsigned AddressSpace) {
2158 VectorType *SrcVTy = dyn_cast<VectorType>(SrcTy);
2159 if (!SrcVTy)
2160 // To calculate scalar take the regular cost, without mask
2161 return getMemoryOpCost(Opcode, SrcTy, Alignment, AddressSpace);
2162
2163 unsigned NumElem = SrcVTy->getVectorNumElements();
2164 VectorType *MaskTy =
2165 VectorType::get(Type::getInt8Ty(SrcVTy->getContext()), NumElem);
2166 if ((Opcode == Instruction::Load && !isLegalMaskedLoad(SrcVTy)) ||
2167 (Opcode == Instruction::Store && !isLegalMaskedStore(SrcVTy)) ||
2168 !isPowerOf2_32(NumElem)) {
2169 // Scalarization
2170 int MaskSplitCost = getScalarizationOverhead(MaskTy, false, true);
2171 int ScalarCompareCost = getCmpSelInstrCost(
2172 Instruction::ICmp, Type::getInt8Ty(SrcVTy->getContext()), nullptr);
2173 int BranchCost = getCFInstrCost(Instruction::Br);
2174 int MaskCmpCost = NumElem * (BranchCost + ScalarCompareCost);
2175
2176 int ValueSplitCost = getScalarizationOverhead(
2177 SrcVTy, Opcode == Instruction::Load, Opcode == Instruction::Store);
2178 int MemopCost =
2179 NumElem * BaseT::getMemoryOpCost(Opcode, SrcVTy->getScalarType(),
2180 Alignment, AddressSpace);
2181 return MemopCost + ValueSplitCost + MaskSplitCost + MaskCmpCost;
2182 }
2183
2184 // Legalize the type.
2185 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, SrcVTy);
2186 auto VT = TLI->getValueType(DL, SrcVTy);
2187 int Cost = 0;
2188 if (VT.isSimple() && LT.second != VT.getSimpleVT() &&
2189 LT.second.getVectorNumElements() == NumElem)
2190 // Promotion requires expand/truncate for data and a shuffle for mask.
2191 Cost += getShuffleCost(TTI::SK_Select, SrcVTy, 0, nullptr) +
2192 getShuffleCost(TTI::SK_Select, MaskTy, 0, nullptr);
2193
2194 else if (LT.second.getVectorNumElements() > NumElem) {
2195 VectorType *NewMaskTy = VectorType::get(MaskTy->getVectorElementType(),
2196 LT.second.getVectorNumElements());
2197 // Expanding requires fill mask with zeroes
2198 Cost += getShuffleCost(TTI::SK_InsertSubvector, NewMaskTy, 0, MaskTy);
2199 }
2200 if (!ST->hasAVX512())
2201 return Cost + LT.first*4; // Each maskmov costs 4
2202
2203 // AVX-512 masked load/store is cheapper
2204 return Cost+LT.first;
2205}
2206
2207int X86TTIImpl::getAddressComputationCost(Type *Ty, ScalarEvolution *SE,
2208 const SCEV *Ptr) {
2209 // Address computations in vectorized code with non-consecutive addresses will
2210 // likely result in more instructions compared to scalar code where the
2211 // computation can more often be merged into the index mode. The resulting
2212 // extra micro-ops can significantly decrease throughput.
2213 unsigned NumVectorInstToHideOverhead = 10;
2214
2215 // Cost modeling of Strided Access Computation is hidden by the indexing
2216 // modes of X86 regardless of the stride value. We dont believe that there
2217 // is a difference between constant strided access in gerenal and constant
2218 // strided value which is less than or equal to 64.
2219 // Even in the case of (loop invariant) stride whose value is not known at
2220 // compile time, the address computation will not incur more than one extra
2221 // ADD instruction.
2222 if (Ty->isVectorTy() && SE) {
2223 if (!BaseT::isStridedAccess(Ptr))
2224 return NumVectorInstToHideOverhead;
2225 if (!BaseT::getConstantStrideStep(SE, Ptr))
2226 return 1;
2227 }
2228
2229 return BaseT::getAddressComputationCost(Ty, SE, Ptr);
2230}
2231
2232int X86TTIImpl::getArithmeticReductionCost(unsigned Opcode, Type *ValTy,
2233 bool IsPairwise) {
2234
2235 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy);
2236
2237 MVT MTy = LT.second;
2238
2239 int ISD = TLI->InstructionOpcodeToISD(Opcode);
2240 assert(ISD && "Invalid opcode")((ISD && "Invalid opcode") ? static_cast<void> (
0) : __assert_fail ("ISD && \"Invalid opcode\"", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86TargetTransformInfo.cpp"
, 2240, __PRETTY_FUNCTION__))
;
2241
2242 // We use the Intel Architecture Code Analyzer(IACA) to measure the throughput
2243 // and make it as the cost.
2244
2245 static const CostTblEntry SSE42CostTblPairWise[] = {
2246 { ISD::FADD, MVT::v2f64, 2 },
2247 { ISD::FADD, MVT::v4f32, 4 },
2248 { ISD::ADD, MVT::v2i64, 2 }, // The data reported by the IACA tool is "1.6".
2249 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.5".
2250 { ISD::ADD, MVT::v8i16, 5 },
2251 };
2252
2253 static const CostTblEntry AVX1CostTblPairWise[] = {
2254 { ISD::FADD, MVT::v4f32, 4 },
2255 { ISD::FADD, MVT::v4f64, 5 },
2256 { ISD::FADD, MVT::v8f32, 7 },
2257 { ISD::ADD, MVT::v2i64, 1 }, // The data reported by the IACA tool is "1.5".
2258 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.5".
2259 { ISD::ADD, MVT::v4i64, 5 }, // The data reported by the IACA tool is "4.8".
2260 { ISD::ADD, MVT::v8i16, 5 },
2261 { ISD::ADD, MVT::v8i32, 5 },
2262 };
2263
2264 static const CostTblEntry SSE42CostTblNoPairWise[] = {
2265 { ISD::FADD, MVT::v2f64, 2 },
2266 { ISD::FADD, MVT::v4f32, 4 },
2267 { ISD::ADD, MVT::v2i64, 2 }, // The data reported by the IACA tool is "1.6".
2268 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.3".
2269 { ISD::ADD, MVT::v8i16, 4 }, // The data reported by the IACA tool is "4.3".
2270 };
2271
2272 static const CostTblEntry AVX1CostTblNoPairWise[] = {
2273 { ISD::FADD, MVT::v4f32, 3 },
2274 { ISD::FADD, MVT::v4f64, 3 },
2275 { ISD::FADD, MVT::v8f32, 4 },
2276 { ISD::ADD, MVT::v2i64, 1 }, // The data reported by the IACA tool is "1.5".
2277 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "2.8".
2278 { ISD::ADD, MVT::v4i64, 3 },
2279 { ISD::ADD, MVT::v8i16, 4 },
2280 { ISD::ADD, MVT::v8i32, 5 },
2281 };
2282
2283 if (IsPairwise) {
2284 if (ST->hasAVX())
2285 if (const auto *Entry = CostTableLookup(AVX1CostTblPairWise, ISD, MTy))
2286 return LT.first * Entry->Cost;
2287
2288 if (ST->hasSSE42())
2289 if (const auto *Entry = CostTableLookup(SSE42CostTblPairWise, ISD, MTy))
2290 return LT.first * Entry->Cost;
2291 } else {
2292 if (ST->hasAVX())
2293 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy))
2294 return LT.first * Entry->Cost;
2295
2296 if (ST->hasSSE42())
2297 if (const auto *Entry = CostTableLookup(SSE42CostTblNoPairWise, ISD, MTy))
2298 return LT.first * Entry->Cost;
2299 }
2300
2301 return BaseT::getArithmeticReductionCost(Opcode, ValTy, IsPairwise);
2302}
2303
2304int X86TTIImpl::getMinMaxReductionCost(Type *ValTy, Type *CondTy,
2305 bool IsPairwise, bool IsUnsigned) {
2306 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy);
2307
2308 MVT MTy = LT.second;
2309
2310 int ISD;
2311 if (ValTy->isIntOrIntVectorTy()) {
2312 ISD = IsUnsigned ? ISD::UMIN : ISD::SMIN;
2313 } else {
2314 assert(ValTy->isFPOrFPVectorTy() &&((ValTy->isFPOrFPVectorTy() && "Expected float point or integer vector type."
) ? static_cast<void> (0) : __assert_fail ("ValTy->isFPOrFPVectorTy() && \"Expected float point or integer vector type.\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86TargetTransformInfo.cpp"
, 2315, __PRETTY_FUNCTION__))
2315 "Expected float point or integer vector type.")((ValTy->isFPOrFPVectorTy() && "Expected float point or integer vector type."
) ? static_cast<void> (0) : __assert_fail ("ValTy->isFPOrFPVectorTy() && \"Expected float point or integer vector type.\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86TargetTransformInfo.cpp"
, 2315, __PRETTY_FUNCTION__))
;
2316 ISD = ISD::FMINNUM;
2317 }
2318
2319 // We use the Intel Architecture Code Analyzer(IACA) to measure the throughput
2320 // and make it as the cost.
2321
2322 static const CostTblEntry SSE42CostTblPairWise[] = {
2323 {ISD::FMINNUM, MVT::v2f64, 3},
2324 {ISD::FMINNUM, MVT::v4f32, 2},
2325 {ISD::SMIN, MVT::v2i64, 7}, // The data reported by the IACA is "6.8"
2326 {ISD::UMIN, MVT::v2i64, 8}, // The data reported by the IACA is "8.6"
2327 {ISD::SMIN, MVT::v4i32, 1}, // The data reported by the IACA is "1.5"
2328 {ISD::UMIN, MVT::v4i32, 2}, // The data reported by the IACA is "1.8"
2329 {ISD::SMIN, MVT::v8i16, 2},
2330 {ISD::UMIN, MVT::v8i16, 2},
2331 };
2332
2333 static const CostTblEntry AVX1CostTblPairWise[] = {
2334 {ISD::FMINNUM, MVT::v4f32, 1},
2335 {ISD::FMINNUM, MVT::v4f64, 1},
2336 {ISD::FMINNUM, MVT::v8f32, 2},
2337 {ISD::SMIN, MVT::v2i64, 3},
2338 {ISD::UMIN, MVT::v2i64, 3},
2339 {ISD::SMIN, MVT::v4i32, 1},
2340 {ISD::UMIN, MVT::v4i32, 1},
2341 {ISD::SMIN, MVT::v8i16, 1},
2342 {ISD::UMIN, MVT::v8i16, 1},
2343 {ISD::SMIN, MVT::v8i32, 3},
2344 {ISD::UMIN, MVT::v8i32, 3},
2345 };
2346
2347 static const CostTblEntry AVX2CostTblPairWise[] = {
2348 {ISD::SMIN, MVT::v4i64, 2},
2349 {ISD::UMIN, MVT::v4i64, 2},
2350 {ISD::SMIN, MVT::v8i32, 1},
2351 {ISD::UMIN, MVT::v8i32, 1},
2352 {ISD::SMIN, MVT::v16i16, 1},
2353 {ISD::UMIN, MVT::v16i16, 1},
2354 {ISD::SMIN, MVT::v32i8, 2},
2355 {ISD::UMIN, MVT::v32i8, 2},
2356 };
2357
2358 static const CostTblEntry AVX512CostTblPairWise[] = {
2359 {ISD::FMINNUM, MVT::v8f64, 1},
2360 {ISD::FMINNUM, MVT::v16f32, 2},
2361 {ISD::SMIN, MVT::v8i64, 2},
2362 {ISD::UMIN, MVT::v8i64, 2},
2363 {ISD::SMIN, MVT::v16i32, 1},
2364 {ISD::UMIN, MVT::v16i32, 1},
2365 };
2366
2367 static const CostTblEntry SSE42CostTblNoPairWise[] = {
2368 {ISD::FMINNUM, MVT::v2f64, 3},
2369 {ISD::FMINNUM, MVT::v4f32, 3},
2370 {ISD::SMIN, MVT::v2i64, 7}, // The data reported by the IACA is "6.8"
2371 {ISD::UMIN, MVT::v2i64, 9}, // The data reported by the IACA is "8.6"
2372 {ISD::SMIN, MVT::v4i32, 1}, // The data reported by the IACA is "1.5"
2373 {ISD::UMIN, MVT::v4i32, 2}, // The data reported by the IACA is "1.8"
2374 {ISD::SMIN, MVT::v8i16, 1}, // The data reported by the IACA is "1.5"
2375 {ISD::UMIN, MVT::v8i16, 2}, // The data reported by the IACA is "1.8"
2376 };
2377
2378 static const CostTblEntry AVX1CostTblNoPairWise[] = {
2379 {ISD::FMINNUM, MVT::v4f32, 1},
2380 {ISD::FMINNUM, MVT::v4f64, 1},
2381 {ISD::FMINNUM, MVT::v8f32, 1},
2382 {ISD::SMIN, MVT::v2i64, 3},
2383 {ISD::UMIN, MVT::v2i64, 3},
2384 {ISD::SMIN, MVT::v4i32, 1},
2385 {ISD::UMIN, MVT::v4i32, 1},
2386 {ISD::SMIN, MVT::v8i16, 1},
2387 {ISD::UMIN, MVT::v8i16, 1},
2388 {ISD::SMIN, MVT::v8i32, 2},
2389 {ISD::UMIN, MVT::v8i32, 2},
2390 };
2391
2392 static const CostTblEntry AVX2CostTblNoPairWise[] = {
2393 {ISD::SMIN, MVT::v4i64, 1},
2394 {ISD::UMIN, MVT::v4i64, 1},
2395 {ISD::SMIN, MVT::v8i32, 1},
2396 {ISD::UMIN, MVT::v8i32, 1},
2397 {ISD::SMIN, MVT::v16i16, 1},
2398 {ISD::UMIN, MVT::v16i16, 1},
2399 {ISD::SMIN, MVT::v32i8, 1},
2400 {ISD::UMIN, MVT::v32i8, 1},
2401 };
2402
2403 static const CostTblEntry AVX512CostTblNoPairWise[] = {
2404 {ISD::FMINNUM, MVT::v8f64, 1},
2405 {ISD::FMINNUM, MVT::v16f32, 2},
2406 {ISD::SMIN, MVT::v8i64, 1},
2407 {ISD::UMIN, MVT::v8i64, 1},
2408 {ISD::SMIN, MVT::v16i32, 1},
2409 {ISD::UMIN, MVT::v16i32, 1},
2410 };
2411
2412 if (IsPairwise) {
2413 if (ST->hasAVX512())
2414 if (const auto *Entry = CostTableLookup(AVX512CostTblPairWise, ISD, MTy))
2415 return LT.first * Entry->Cost;
2416
2417 if (ST->hasAVX2())
2418 if (const auto *Entry = CostTableLookup(AVX2CostTblPairWise, ISD, MTy))
2419 return LT.first * Entry->Cost;
2420
2421 if (ST->hasAVX())
2422 if (const auto *Entry = CostTableLookup(AVX1CostTblPairWise, ISD, MTy))
2423 return LT.first * Entry->Cost;
2424
2425 if (ST->hasSSE42())
2426 if (const auto *Entry = CostTableLookup(SSE42CostTblPairWise, ISD, MTy))
2427 return LT.first * Entry->Cost;
2428 } else {
2429 if (ST->hasAVX512())
2430 if (const auto *Entry =
2431 CostTableLookup(AVX512CostTblNoPairWise, ISD, MTy))
2432 return LT.first * Entry->Cost;
2433
2434 if (ST->hasAVX2())
2435 if (const auto *Entry = CostTableLookup(AVX2CostTblNoPairWise, ISD, MTy))
2436 return LT.first * Entry->Cost;
2437
2438 if (ST->hasAVX())
2439 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy))
2440 return LT.first * Entry->Cost;
2441
2442 if (ST->hasSSE42())
2443 if (const auto *Entry = CostTableLookup(SSE42CostTblNoPairWise, ISD, MTy))
2444 return LT.first * Entry->Cost;
2445 }
2446
2447 return BaseT::getMinMaxReductionCost(ValTy, CondTy, IsPairwise, IsUnsigned);
2448}
2449
2450/// Calculate the cost of materializing a 64-bit value. This helper
2451/// method might only calculate a fraction of a larger immediate. Therefore it
2452/// is valid to return a cost of ZERO.
2453int X86TTIImpl::getIntImmCost(int64_t Val) {
2454 if (Val == 0)
2455 return TTI::TCC_Free;
2456
2457 if (isInt<32>(Val))
2458 return TTI::TCC_Basic;
2459
2460 return 2 * TTI::TCC_Basic;
2461}
2462
2463int X86TTIImpl::getIntImmCost(const APInt &Imm, Type *Ty) {
2464 assert(Ty->isIntegerTy())((Ty->isIntegerTy()) ? static_cast<void> (0) : __assert_fail
("Ty->isIntegerTy()", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86TargetTransformInfo.cpp"
, 2464, __PRETTY_FUNCTION__))
;
2465
2466 unsigned BitSize = Ty->getPrimitiveSizeInBits();
2467 if (BitSize == 0)
2468 return ~0U;
2469
2470 // Never hoist constants larger than 128bit, because this might lead to
2471 // incorrect code generation or assertions in codegen.
2472 // Fixme: Create a cost model for types larger than i128 once the codegen
2473 // issues have been fixed.
2474 if (BitSize > 128)
2475 return TTI::TCC_Free;
2476
2477 if (Imm == 0)
2478 return TTI::TCC_Free;
2479
2480 // Sign-extend all constants to a multiple of 64-bit.
2481 APInt ImmVal = Imm;
2482 if (BitSize % 64 != 0)
2483 ImmVal = Imm.sext(alignTo(BitSize, 64));
2484
2485 // Split the constant into 64-bit chunks and calculate the cost for each
2486 // chunk.
2487 int Cost = 0;
2488 for (unsigned ShiftVal = 0; ShiftVal < BitSize; ShiftVal += 64) {
2489 APInt Tmp = ImmVal.ashr(ShiftVal).sextOrTrunc(64);
2490 int64_t Val = Tmp.getSExtValue();
2491 Cost += getIntImmCost(Val);
2492 }
2493 // We need at least one instruction to materialize the constant.
2494 return std::max(1, Cost);
2495}
2496
2497int X86TTIImpl::getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm,
2498 Type *Ty) {
2499 assert(Ty->isIntegerTy())((Ty->isIntegerTy()) ? static_cast<void> (0) : __assert_fail
("Ty->isIntegerTy()", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86TargetTransformInfo.cpp"
, 2499, __PRETTY_FUNCTION__))
;
2500
2501 unsigned BitSize = Ty->getPrimitiveSizeInBits();
2502 // There is no cost model for constants with a bit size of 0. Return TCC_Free
2503 // here, so that constant hoisting will ignore this constant.
2504 if (BitSize == 0)
2505 return TTI::TCC_Free;
2506
2507 unsigned ImmIdx = ~0U;
2508 switch (Opcode) {
2509 default:
2510 return TTI::TCC_Free;
2511 case Instruction::GetElementPtr:
2512 // Always hoist the base address of a GetElementPtr. This prevents the
2513 // creation of new constants for every base constant that gets constant
2514 // folded with the offset.
2515 if (Idx == 0)
2516 return 2 * TTI::TCC_Basic;
2517 return TTI::TCC_Free;
2518 case Instruction::Store:
2519 ImmIdx = 0;
2520 break;
2521 case Instruction::ICmp:
2522 // This is an imperfect hack to prevent constant hoisting of
2523 // compares that might be trying to check if a 64-bit value fits in
2524 // 32-bits. The backend can optimize these cases using a right shift by 32.
2525 // Ideally we would check the compare predicate here. There also other
2526 // similar immediates the backend can use shifts for.
2527 if (Idx == 1 && Imm.getBitWidth() == 64) {
2528 uint64_t ImmVal = Imm.getZExtValue();
2529 if (ImmVal == 0x100000000ULL || ImmVal == 0xffffffff)
2530 return TTI::TCC_Free;
2531 }
2532 ImmIdx = 1;
2533 break;
2534 case Instruction::And:
2535 // We support 64-bit ANDs with immediates with 32-bits of leading zeroes
2536 // by using a 32-bit operation with implicit zero extension. Detect such
2537 // immediates here as the normal path expects bit 31 to be sign extended.
2538 if (Idx == 1 && Imm.getBitWidth() == 64 && isUInt<32>(Imm.getZExtValue()))
2539 return TTI::TCC_Free;
2540 ImmIdx = 1;
2541 break;
2542 case Instruction::Add:
2543 case Instruction::Sub:
2544 // For add/sub, we can use the opposite instruction for INT32_MIN.
2545 if (Idx == 1 && Imm.getBitWidth() == 64 && Imm.getZExtValue() == 0x80000000)
2546 return TTI::TCC_Free;
2547 ImmIdx = 1;
2548 break;
2549 case Instruction::UDiv:
2550 case Instruction::SDiv:
2551 case Instruction::URem:
2552 case Instruction::SRem:
2553 // Division by constant is typically expanded later into a different
2554 // instruction sequence. This completely changes the constants.
2555 // Report them as "free" to stop ConstantHoist from marking them as opaque.
2556 return TTI::TCC_Free;
2557 case Instruction::Mul:
2558 case Instruction::Or:
2559 case Instruction::Xor:
2560 ImmIdx = 1;
2561 break;
2562 // Always return TCC_Free for the shift value of a shift instruction.
2563 case Instruction::Shl:
2564 case Instruction::LShr:
2565 case Instruction::AShr:
2566 if (Idx == 1)
2567 return TTI::TCC_Free;
2568 break;
2569 case Instruction::Trunc:
2570 case Instruction::ZExt:
2571 case Instruction::SExt:
2572 case Instruction::IntToPtr:
2573 case Instruction::PtrToInt:
2574 case Instruction::BitCast:
2575 case Instruction::PHI:
2576 case Instruction::Call:
2577 case Instruction::Select:
2578 case Instruction::Ret:
2579 case Instruction::Load:
2580 break;
2581 }
2582
2583 if (Idx == ImmIdx) {
2584 int NumConstants = divideCeil(BitSize, 64);
2585 int Cost = X86TTIImpl::getIntImmCost(Imm, Ty);
2586 return (Cost <= NumConstants * TTI::TCC_Basic)
2587 ? static_cast<int>(TTI::TCC_Free)
2588 : Cost;
2589 }
2590
2591 return X86TTIImpl::getIntImmCost(Imm, Ty);
2592}
2593
2594int X86TTIImpl::getIntImmCost(Intrinsic::ID IID, unsigned Idx, const APInt &Imm,
2595 Type *Ty) {
2596 assert(Ty->isIntegerTy())((Ty->isIntegerTy()) ? static_cast<void> (0) : __assert_fail
("Ty->isIntegerTy()", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86TargetTransformInfo.cpp"
, 2596, __PRETTY_FUNCTION__))
;
2597
2598 unsigned BitSize = Ty->getPrimitiveSizeInBits();
2599 // There is no cost model for constants with a bit size of 0. Return TCC_Free
2600 // here, so that constant hoisting will ignore this constant.
2601 if (BitSize == 0)
2602 return TTI::TCC_Free;
2603
2604 switch (IID) {
2605 default:
2606 return TTI::TCC_Free;
2607 case Intrinsic::sadd_with_overflow:
2608 case Intrinsic::uadd_with_overflow:
2609 case Intrinsic::ssub_with_overflow:
2610 case Intrinsic::usub_with_overflow:
2611 case Intrinsic::smul_with_overflow:
2612 case Intrinsic::umul_with_overflow:
2613 if ((Idx == 1) && Imm.getBitWidth() <= 64 && isInt<32>(Imm.getSExtValue()))
2614 return TTI::TCC_Free;
2615 break;
2616 case Intrinsic::experimental_stackmap:
2617 if ((Idx < 2) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue())))
2618 return TTI::TCC_Free;
2619 break;
2620 case Intrinsic::experimental_patchpoint_void:
2621 case Intrinsic::experimental_patchpoint_i64:
2622 if ((Idx < 4) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue())))
2623 return TTI::TCC_Free;
2624 break;
2625 }
2626 return X86TTIImpl::getIntImmCost(Imm, Ty);
2627}
2628
2629unsigned X86TTIImpl::getUserCost(const User *U,
2630 ArrayRef<const Value *> Operands) {
2631 if (isa<StoreInst>(U)) {
1
Taking false branch
2632 Value *Ptr = U->getOperand(1);
2633 // Store instruction with index and scale costs 2 Uops.
2634 // Check the preceding GEP to identify non-const indices.
2635 if (auto GEP = dyn_cast<GetElementPtrInst>(Ptr)) {
2636 if (!all_of(GEP->indices(), [](Value *V) { return isa<Constant>(V); }))
2637 return TTI::TCC_Basic * 2;
2638 }
2639 return TTI::TCC_Basic;
2640 }
2641 return BaseT::getUserCost(U, Operands);
2
Calling 'TargetTransformInfoImplCRTPBase::getUserCost'
2642}
2643
2644// Return an average cost of Gather / Scatter instruction, maybe improved later
2645int X86TTIImpl::getGSVectorCost(unsigned Opcode, Type *SrcVTy, Value *Ptr,
2646 unsigned Alignment, unsigned AddressSpace) {
2647
2648 assert(isa<VectorType>(SrcVTy) && "Unexpected type in getGSVectorCost")((isa<VectorType>(SrcVTy) && "Unexpected type in getGSVectorCost"
) ? static_cast<void> (0) : __assert_fail ("isa<VectorType>(SrcVTy) && \"Unexpected type in getGSVectorCost\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86TargetTransformInfo.cpp"
, 2648, __PRETTY_FUNCTION__))
;
2649 unsigned VF = SrcVTy->getVectorNumElements();
2650
2651 // Try to reduce index size from 64 bit (default for GEP)
2652 // to 32. It is essential for VF 16. If the index can't be reduced to 32, the
2653 // operation will use 16 x 64 indices which do not fit in a zmm and needs
2654 // to split. Also check that the base pointer is the same for all lanes,
2655 // and that there's at most one variable index.
2656 auto getIndexSizeInBits = [](Value *Ptr, const DataLayout& DL) {
2657 unsigned IndexSize = DL.getPointerSizeInBits();
2658 GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(Ptr);
2659 if (IndexSize < 64 || !GEP)
2660 return IndexSize;
2661
2662 unsigned NumOfVarIndices = 0;
2663 Value *Ptrs = GEP->getPointerOperand();
2664 if (Ptrs->getType()->isVectorTy() && !getSplatValue(Ptrs))
2665 return IndexSize;
2666 for (unsigned i = 1; i < GEP->getNumOperands(); ++i) {
2667 if (isa<Constant>(GEP->getOperand(i)))
2668 continue;
2669 Type *IndxTy = GEP->getOperand(i)->getType();
2670 if (IndxTy->isVectorTy())
2671 IndxTy = IndxTy->getVectorElementType();
2672 if ((IndxTy->getPrimitiveSizeInBits() == 64 &&
2673 !isa<SExtInst>(GEP->getOperand(i))) ||
2674 ++NumOfVarIndices > 1)
2675 return IndexSize; // 64
2676 }
2677 return (unsigned)32;
2678 };
2679
2680
2681 // Trying to reduce IndexSize to 32 bits for vector 16.
2682 // By default the IndexSize is equal to pointer size.
2683 unsigned IndexSize = (ST->hasAVX512() && VF >= 16)
2684 ? getIndexSizeInBits(Ptr, DL)
2685 : DL.getPointerSizeInBits();
2686
2687 Type *IndexVTy = VectorType::get(IntegerType::get(SrcVTy->getContext(),
2688 IndexSize), VF);
2689 std::pair<int, MVT> IdxsLT = TLI->getTypeLegalizationCost(DL, IndexVTy);
2690 std::pair<int, MVT> SrcLT = TLI->getTypeLegalizationCost(DL, SrcVTy);
2691 int SplitFactor = std::max(IdxsLT.first, SrcLT.first);
2692 if (SplitFactor > 1) {
2693 // Handle splitting of vector of pointers
2694 Type *SplitSrcTy = VectorType::get(SrcVTy->getScalarType(), VF / SplitFactor);
2695 return SplitFactor * getGSVectorCost(Opcode, SplitSrcTy, Ptr, Alignment,
2696 AddressSpace);
2697 }
2698
2699 // The gather / scatter cost is given by Intel architects. It is a rough
2700 // number since we are looking at one instruction in a time.
2701 const int GSOverhead = (Opcode == Instruction::Load)
2702 ? ST->getGatherOverhead()
2703 : ST->getScatterOverhead();
2704 return GSOverhead + VF * getMemoryOpCost(Opcode, SrcVTy->getScalarType(),
2705 Alignment, AddressSpace);
2706}
2707
2708/// Return the cost of full scalarization of gather / scatter operation.
2709///
2710/// Opcode - Load or Store instruction.
2711/// SrcVTy - The type of the data vector that should be gathered or scattered.
2712/// VariableMask - The mask is non-constant at compile time.
2713/// Alignment - Alignment for one element.
2714/// AddressSpace - pointer[s] address space.
2715///
2716int X86TTIImpl::getGSScalarCost(unsigned Opcode, Type *SrcVTy,
2717 bool VariableMask, unsigned Alignment,
2718 unsigned AddressSpace) {
2719 unsigned VF = SrcVTy->getVectorNumElements();
2720
2721 int MaskUnpackCost = 0;
2722 if (VariableMask) {
2723 VectorType *MaskTy =
2724 VectorType::get(Type::getInt1Ty(SrcVTy->getContext()), VF);
2725 MaskUnpackCost = getScalarizationOverhead(MaskTy, false, true);
2726 int ScalarCompareCost =
2727 getCmpSelInstrCost(Instruction::ICmp, Type::getInt1Ty(SrcVTy->getContext()),
2728 nullptr);
2729 int BranchCost = getCFInstrCost(Instruction::Br);
2730 MaskUnpackCost += VF * (BranchCost + ScalarCompareCost);
2731 }
2732
2733 // The cost of the scalar loads/stores.
2734 int MemoryOpCost = VF * getMemoryOpCost(Opcode, SrcVTy->getScalarType(),
2735 Alignment, AddressSpace);
2736
2737 int InsertExtractCost = 0;
2738 if (Opcode == Instruction::Load)
2739 for (unsigned i = 0; i < VF; ++i)
2740 // Add the cost of inserting each scalar load into the vector
2741 InsertExtractCost +=
2742 getVectorInstrCost(Instruction::InsertElement, SrcVTy, i);
2743 else
2744 for (unsigned i = 0; i < VF; ++i)
2745 // Add the cost of extracting each element out of the data vector
2746 InsertExtractCost +=
2747 getVectorInstrCost(Instruction::ExtractElement, SrcVTy, i);
2748
2749 return MemoryOpCost + MaskUnpackCost + InsertExtractCost;
2750}
2751
2752/// Calculate the cost of Gather / Scatter operation
2753int X86TTIImpl::getGatherScatterOpCost(unsigned Opcode, Type *SrcVTy,
2754 Value *Ptr, bool VariableMask,
2755 unsigned Alignment) {
2756 assert(SrcVTy->isVectorTy() && "Unexpected data type for Gather/Scatter")((SrcVTy->isVectorTy() && "Unexpected data type for Gather/Scatter"
) ? static_cast<void> (0) : __assert_fail ("SrcVTy->isVectorTy() && \"Unexpected data type for Gather/Scatter\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86TargetTransformInfo.cpp"
, 2756, __PRETTY_FUNCTION__))
;
2757 unsigned VF = SrcVTy->getVectorNumElements();
2758 PointerType *PtrTy = dyn_cast<PointerType>(Ptr->getType());
2759 if (!PtrTy && Ptr->getType()->isVectorTy())
2760 PtrTy = dyn_cast<PointerType>(Ptr->getType()->getVectorElementType());
2761 assert(PtrTy && "Unexpected type for Ptr argument")((PtrTy && "Unexpected type for Ptr argument") ? static_cast
<void> (0) : __assert_fail ("PtrTy && \"Unexpected type for Ptr argument\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86TargetTransformInfo.cpp"
, 2761, __PRETTY_FUNCTION__))
;
2762 unsigned AddressSpace = PtrTy->getAddressSpace();
2763
2764 bool Scalarize = false;
2765 if ((Opcode == Instruction::Load && !isLegalMaskedGather(SrcVTy)) ||
2766 (Opcode == Instruction::Store && !isLegalMaskedScatter(SrcVTy)))
2767 Scalarize = true;
2768 // Gather / Scatter for vector 2 is not profitable on KNL / SKX
2769 // Vector-4 of gather/scatter instruction does not exist on KNL.
2770 // We can extend it to 8 elements, but zeroing upper bits of
2771 // the mask vector will add more instructions. Right now we give the scalar
2772 // cost of vector-4 for KNL. TODO: Check, maybe the gather/scatter instruction
2773 // is better in the VariableMask case.
2774 if (ST->hasAVX512() && (VF == 2 || (VF == 4 && !ST->hasVLX())))
2775 Scalarize = true;
2776
2777 if (Scalarize)
2778 return getGSScalarCost(Opcode, SrcVTy, VariableMask, Alignment,
2779 AddressSpace);
2780
2781 return getGSVectorCost(Opcode, SrcVTy, Ptr, Alignment, AddressSpace);
2782}
2783
2784bool X86TTIImpl::isLSRCostLess(TargetTransformInfo::LSRCost &C1,
2785 TargetTransformInfo::LSRCost &C2) {
2786 // X86 specific here are "instruction number 1st priority".
2787 return std::tie(C1.Insns, C1.NumRegs, C1.AddRecCost,
2788 C1.NumIVMuls, C1.NumBaseAdds,
2789 C1.ScaleCost, C1.ImmCost, C1.SetupCost) <
2790 std::tie(C2.Insns, C2.NumRegs, C2.AddRecCost,
2791 C2.NumIVMuls, C2.NumBaseAdds,
2792 C2.ScaleCost, C2.ImmCost, C2.SetupCost);
2793}
2794
2795bool X86TTIImpl::canMacroFuseCmp() {
2796 return ST->hasMacroFusion();
2797}
2798
2799bool X86TTIImpl::isLegalMaskedLoad(Type *DataTy) {
2800 // The backend can't handle a single element vector.
2801 if (isa<VectorType>(DataTy) && DataTy->getVectorNumElements() == 1)
2802 return false;
2803 Type *ScalarTy = DataTy->getScalarType();
2804 int DataWidth = isa<PointerType>(ScalarTy) ?
2805 DL.getPointerSizeInBits() : ScalarTy->getPrimitiveSizeInBits();
2806
2807 return ((DataWidth == 32 || DataWidth == 64) && ST->hasAVX()) ||
2808 ((DataWidth == 8 || DataWidth == 16) && ST->hasBWI());
2809}
2810
2811bool X86TTIImpl::isLegalMaskedStore(Type *DataType) {
2812 return isLegalMaskedLoad(DataType);
2813}
2814
2815bool X86TTIImpl::isLegalMaskedGather(Type *DataTy) {
2816 // This function is called now in two cases: from the Loop Vectorizer
2817 // and from the Scalarizer.
2818 // When the Loop Vectorizer asks about legality of the feature,
2819 // the vectorization factor is not calculated yet. The Loop Vectorizer
2820 // sends a scalar type and the decision is based on the width of the
2821 // scalar element.
2822 // Later on, the cost model will estimate usage this intrinsic based on
2823 // the vector type.
2824 // The Scalarizer asks again about legality. It sends a vector type.
2825 // In this case we can reject non-power-of-2 vectors.
2826 // We also reject single element vectors as the type legalizer can't
2827 // scalarize it.
2828 if (isa<VectorType>(DataTy)) {
2829 unsigned NumElts = DataTy->getVectorNumElements();
2830 if (NumElts == 1 || !isPowerOf2_32(NumElts))
2831 return false;
2832 }
2833 Type *ScalarTy = DataTy->getScalarType();
2834 int DataWidth = isa<PointerType>(ScalarTy) ?
2835 DL.getPointerSizeInBits() : ScalarTy->getPrimitiveSizeInBits();
2836
2837 // Some CPUs have better gather performance than others.
2838 // TODO: Remove the explicit ST->hasAVX512()?, That would mean we would only
2839 // enable gather with a -march.
2840 return (DataWidth == 32 || DataWidth == 64) &&
2841 (ST->hasAVX512() || (ST->hasFastGather() && ST->hasAVX2()));
2842}
2843
2844bool X86TTIImpl::isLegalMaskedScatter(Type *DataType) {
2845 // AVX2 doesn't support scatter
2846 if (!ST->hasAVX512())
2847 return false;
2848 return isLegalMaskedGather(DataType);
2849}
2850
2851bool X86TTIImpl::hasDivRemOp(Type *DataType, bool IsSigned) {
2852 EVT VT = TLI->getValueType(DL, DataType);
2853 return TLI->isOperationLegal(IsSigned ? ISD::SDIVREM : ISD::UDIVREM, VT);
2854}
2855
2856bool X86TTIImpl::isFCmpOrdCheaperThanFCmpZero(Type *Ty) {
2857 return false;
2858}
2859
2860bool X86TTIImpl::areInlineCompatible(const Function *Caller,
2861 const Function *Callee) const {
2862 const TargetMachine &TM = getTLI()->getTargetMachine();
2863
2864 // Work this as a subsetting of subtarget features.
2865 const FeatureBitset &CallerBits =
2866 TM.getSubtargetImpl(*Caller)->getFeatureBits();
2867 const FeatureBitset &CalleeBits =
2868 TM.getSubtargetImpl(*Callee)->getFeatureBits();
2869
2870 // FIXME: This is likely too limiting as it will include subtarget features
2871 // that we might not care about for inlining, but it is conservatively
2872 // correct.
2873 return (CallerBits & CalleeBits) == CalleeBits;
2874}
2875
2876const X86TTIImpl::TTI::MemCmpExpansionOptions *
2877X86TTIImpl::enableMemCmpExpansion(bool IsZeroCmp) const {
2878 // Only enable vector loads for equality comparison.
2879 // Right now the vector version is not as fast, see #33329.
2880 static const auto ThreeWayOptions = [this]() {
2881 TTI::MemCmpExpansionOptions Options;
2882 if (ST->is64Bit()) {
2883 Options.LoadSizes.push_back(8);
2884 }
2885 Options.LoadSizes.push_back(4);
2886 Options.LoadSizes.push_back(2);
2887 Options.LoadSizes.push_back(1);
2888 return Options;
2889 }();
2890 static const auto EqZeroOptions = [this]() {
2891 TTI::MemCmpExpansionOptions Options;
2892 // TODO: enable AVX512 when the DAG is ready.
2893 // if (ST->hasAVX512()) Options.LoadSizes.push_back(64);
2894 if (ST->hasAVX2()) Options.LoadSizes.push_back(32);
2895 if (ST->hasSSE2()) Options.LoadSizes.push_back(16);
2896 if (ST->is64Bit()) {
2897 Options.LoadSizes.push_back(8);
2898 }
2899 Options.LoadSizes.push_back(4);
2900 Options.LoadSizes.push_back(2);
2901 Options.LoadSizes.push_back(1);
2902 // All GPR and vector loads can be unaligned. SIMD compare requires integer
2903 // vectors (SSE2/AVX2).
2904 Options.AllowOverlappingLoads = true;
2905 return Options;
2906 }();
2907 return IsZeroCmp ? &EqZeroOptions : &ThreeWayOptions;
2908}
2909
2910bool X86TTIImpl::enableInterleavedAccessVectorization() {
2911 // TODO: We expect this to be beneficial regardless of arch,
2912 // but there are currently some unexplained performance artifacts on Atom.
2913 // As a temporary solution, disable on Atom.
2914 return !(ST->isAtom());
2915}
2916
2917// Get estimation for interleaved load/store operations for AVX2.
2918// \p Factor is the interleaved-access factor (stride) - number of
2919// (interleaved) elements in the group.
2920// \p Indices contains the indices for a strided load: when the
2921// interleaved load has gaps they indicate which elements are used.
2922// If Indices is empty (or if the number of indices is equal to the size
2923// of the interleaved-access as given in \p Factor) the access has no gaps.
2924//
2925// As opposed to AVX-512, AVX2 does not have generic shuffles that allow
2926// computing the cost using a generic formula as a function of generic
2927// shuffles. We therefore use a lookup table instead, filled according to
2928// the instruction sequences that codegen currently generates.
2929int X86TTIImpl::getInterleavedMemoryOpCostAVX2(unsigned Opcode, Type *VecTy,
2930 unsigned Factor,
2931 ArrayRef<unsigned> Indices,
2932 unsigned Alignment,
2933 unsigned AddressSpace,
2934 bool UseMaskForCond,
2935 bool UseMaskForGaps) {
2936
2937 if (UseMaskForCond || UseMaskForGaps)
2938 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices,
2939 Alignment, AddressSpace,
2940 UseMaskForCond, UseMaskForGaps);
2941
2942 // We currently Support only fully-interleaved groups, with no gaps.
2943 // TODO: Support also strided loads (interleaved-groups with gaps).
2944 if (Indices.size() && Indices.size() != Factor)
2945 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices,
2946 Alignment, AddressSpace);
2947
2948 // VecTy for interleave memop is <VF*Factor x Elt>.
2949 // So, for VF=4, Interleave Factor = 3, Element type = i32 we have
2950 // VecTy = <12 x i32>.
2951 MVT LegalVT = getTLI()->getTypeLegalizationCost(DL, VecTy).second;
2952
2953 // This function can be called with VecTy=<6xi128>, Factor=3, in which case
2954 // the VF=2, while v2i128 is an unsupported MVT vector type
2955 // (see MachineValueType.h::getVectorVT()).
2956 if (!LegalVT.isVector())
2957 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices,
2958 Alignment, AddressSpace);
2959
2960 unsigned VF = VecTy->getVectorNumElements() / Factor;
2961 Type *ScalarTy = VecTy->getVectorElementType();
2962
2963 // Calculate the number of memory operations (NumOfMemOps), required
2964 // for load/store the VecTy.
2965 unsigned VecTySize = DL.getTypeStoreSize(VecTy);
2966 unsigned LegalVTSize = LegalVT.getStoreSize();
2967 unsigned NumOfMemOps = (VecTySize + LegalVTSize - 1) / LegalVTSize;
2968
2969 // Get the cost of one memory operation.
2970 Type *SingleMemOpTy = VectorType::get(VecTy->getVectorElementType(),
2971 LegalVT.getVectorNumElements());
2972 unsigned MemOpCost =
2973 getMemoryOpCost(Opcode, SingleMemOpTy, Alignment, AddressSpace);
2974
2975 VectorType *VT = VectorType::get(ScalarTy, VF);
2976 EVT ETy = TLI->getValueType(DL, VT);
2977 if (!ETy.isSimple())
2978 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices,
2979 Alignment, AddressSpace);
2980
2981 // TODO: Complete for other data-types and strides.
2982 // Each combination of Stride, ElementTy and VF results in a different
2983 // sequence; The cost tables are therefore accessed with:
2984 // Factor (stride) and VectorType=VFxElemType.
2985 // The Cost accounts only for the shuffle sequence;
2986 // The cost of the loads/stores is accounted for separately.
2987 //
2988 static const CostTblEntry AVX2InterleavedLoadTbl[] = {
2989 { 2, MVT::v4i64, 6 }, //(load 8i64 and) deinterleave into 2 x 4i64
2990 { 2, MVT::v4f64, 6 }, //(load 8f64 and) deinterleave into 2 x 4f64
2991
2992 { 3, MVT::v2i8, 10 }, //(load 6i8 and) deinterleave into 3 x 2i8
2993 { 3, MVT::v4i8, 4 }, //(load 12i8 and) deinterleave into 3 x 4i8
2994 { 3, MVT::v8i8, 9 }, //(load 24i8 and) deinterleave into 3 x 8i8
2995 { 3, MVT::v16i8, 11}, //(load 48i8 and) deinterleave into 3 x 16i8
2996 { 3, MVT::v32i8, 13}, //(load 96i8 and) deinterleave into 3 x 32i8
2997 { 3, MVT::v8f32, 17 }, //(load 24f32 and)deinterleave into 3 x 8f32
2998
2999 { 4, MVT::v2i8, 12 }, //(load 8i8 and) deinterleave into 4 x 2i8
3000 { 4, MVT::v4i8, 4 }, //(load 16i8 and) deinterleave into 4 x 4i8
3001 { 4, MVT::v8i8, 20 }, //(load 32i8 and) deinterleave into 4 x 8i8
3002 { 4, MVT::v16i8, 39 }, //(load 64i8 and) deinterleave into 4 x 16i8
3003 { 4, MVT::v32i8, 80 }, //(load 128i8 and) deinterleave into 4 x 32i8
3004
3005 { 8, MVT::v8f32, 40 } //(load 64f32 and)deinterleave into 8 x 8f32
3006 };
3007
3008 static const CostTblEntry AVX2InterleavedStoreTbl[] = {
3009 { 2, MVT::v4i64, 6 }, //interleave into 2 x 4i64 into 8i64 (and store)
3010 { 2, MVT::v4f64, 6 }, //interleave into 2 x 4f64 into 8f64 (and store)
3011
3012 { 3, MVT::v2i8, 7 }, //interleave 3 x 2i8 into 6i8 (and store)
3013 { 3, MVT::v4i8, 8 }, //interleave 3 x 4i8 into 12i8 (and store)
3014 { 3, MVT::v8i8, 11 }, //interleave 3 x 8i8 into 24i8 (and store)
3015 { 3, MVT::v16i8, 11 }, //interleave 3 x 16i8 into 48i8 (and store)
3016 { 3, MVT::v32i8, 13 }, //interleave 3 x 32i8 into 96i8 (and store)
3017
3018 { 4, MVT::v2i8, 12 }, //interleave 4 x 2i8 into 8i8 (and store)
3019 { 4, MVT::v4i8, 9 }, //interleave 4 x 4i8 into 16i8 (and store)
3020 { 4, MVT::v8i8, 10 }, //interleave 4 x 8i8 into 32i8 (and store)
3021 { 4, MVT::v16i8, 10 }, //interleave 4 x 16i8 into 64i8 (and store)
3022 { 4, MVT::v32i8, 12 } //interleave 4 x 32i8 into 128i8 (and store)
3023 };
3024
3025 if (Opcode == Instruction::Load) {
3026 if (const auto *Entry =
3027 CostTableLookup(AVX2InterleavedLoadTbl, Factor, ETy.getSimpleVT()))
3028 return NumOfMemOps * MemOpCost + Entry->Cost;
3029 } else {
3030 assert(Opcode == Instruction::Store &&((Opcode == Instruction::Store && "Expected Store Instruction at this point"
) ? static_cast<void> (0) : __assert_fail ("Opcode == Instruction::Store && \"Expected Store Instruction at this point\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86TargetTransformInfo.cpp"
, 3031, __PRETTY_FUNCTION__))
3031 "Expected Store Instruction at this point")((Opcode == Instruction::Store && "Expected Store Instruction at this point"
) ? static_cast<void> (0) : __assert_fail ("Opcode == Instruction::Store && \"Expected Store Instruction at this point\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86TargetTransformInfo.cpp"
, 3031, __PRETTY_FUNCTION__))
;
3032 if (const auto *Entry =
3033 CostTableLookup(AVX2InterleavedStoreTbl, Factor, ETy.getSimpleVT()))
3034 return NumOfMemOps * MemOpCost + Entry->Cost;
3035 }
3036
3037 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices,
3038 Alignment, AddressSpace);
3039}
3040
3041// Get estimation for interleaved load/store operations and strided load.
3042// \p Indices contains indices for strided load.
3043// \p Factor - the factor of interleaving.
3044// AVX-512 provides 3-src shuffles that significantly reduces the cost.
3045int X86TTIImpl::getInterleavedMemoryOpCostAVX512(unsigned Opcode, Type *VecTy,
3046 unsigned Factor,
3047 ArrayRef<unsigned> Indices,
3048 unsigned Alignment,
3049 unsigned AddressSpace,
3050 bool UseMaskForCond,
3051 bool UseMaskForGaps) {
3052
3053 if (UseMaskForCond || UseMaskForGaps)
3054 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices,
3055 Alignment, AddressSpace,
3056 UseMaskForCond, UseMaskForGaps);
3057
3058 // VecTy for interleave memop is <VF*Factor x Elt>.
3059 // So, for VF=4, Interleave Factor = 3, Element type = i32 we have
3060 // VecTy = <12 x i32>.
3061
3062 // Calculate the number of memory operations (NumOfMemOps), required
3063 // for load/store the VecTy.
3064 MVT LegalVT = getTLI()->getTypeLegalizationCost(DL, VecTy).second;
3065 unsigned VecTySize = DL.getTypeStoreSize(VecTy);
3066 unsigned LegalVTSize = LegalVT.getStoreSize();
3067 unsigned NumOfMemOps = (VecTySize + LegalVTSize - 1) / LegalVTSize;
3068
3069 // Get the cost of one memory operation.
3070 Type *SingleMemOpTy = VectorType::get(VecTy->getVectorElementType(),
3071 LegalVT.getVectorNumElements());
3072 unsigned MemOpCost =
3073 getMemoryOpCost(Opcode, SingleMemOpTy, Alignment, AddressSpace);
3074
3075 unsigned VF = VecTy->getVectorNumElements() / Factor;
3076 MVT VT = MVT::getVectorVT(MVT::getVT(VecTy->getScalarType()), VF);
3077
3078 if (Opcode == Instruction::Load) {
3079 // The tables (AVX512InterleavedLoadTbl and AVX512InterleavedStoreTbl)
3080 // contain the cost of the optimized shuffle sequence that the
3081 // X86InterleavedAccess pass will generate.
3082 // The cost of loads and stores are computed separately from the table.
3083
3084 // X86InterleavedAccess support only the following interleaved-access group.
3085 static const CostTblEntry AVX512InterleavedLoadTbl[] = {
3086 {3, MVT::v16i8, 12}, //(load 48i8 and) deinterleave into 3 x 16i8
3087 {3, MVT::v32i8, 14}, //(load 96i8 and) deinterleave into 3 x 32i8
3088 {3, MVT::v64i8, 22}, //(load 96i8 and) deinterleave into 3 x 32i8
3089 };
3090
3091 if (const auto *Entry =
3092 CostTableLookup(AVX512InterleavedLoadTbl, Factor, VT))
3093 return NumOfMemOps * MemOpCost + Entry->Cost;
3094 //If an entry does not exist, fallback to the default implementation.
3095
3096 // Kind of shuffle depends on number of loaded values.
3097 // If we load the entire data in one register, we can use a 1-src shuffle.
3098 // Otherwise, we'll merge 2 sources in each operation.
3099 TTI::ShuffleKind ShuffleKind =
3100 (NumOfMemOps > 1) ? TTI::SK_PermuteTwoSrc : TTI::SK_PermuteSingleSrc;
3101
3102 unsigned ShuffleCost =
3103 getShuffleCost(ShuffleKind, SingleMemOpTy, 0, nullptr);
3104
3105 unsigned NumOfLoadsInInterleaveGrp =
3106 Indices.size() ? Indices.size() : Factor;
3107 Type *ResultTy = VectorType::get(VecTy->getVectorElementType(),
3108 VecTy->getVectorNumElements() / Factor);
3109 unsigned NumOfResults =
3110 getTLI()->getTypeLegalizationCost(DL, ResultTy).first *
3111 NumOfLoadsInInterleaveGrp;
3112
3113 // About a half of the loads may be folded in shuffles when we have only
3114 // one result. If we have more than one result, we do not fold loads at all.
3115 unsigned NumOfUnfoldedLoads =
3116 NumOfResults > 1 ? NumOfMemOps : NumOfMemOps / 2;
3117
3118 // Get a number of shuffle operations per result.
3119 unsigned NumOfShufflesPerResult =
3120 std::max((unsigned)1, (unsigned)(NumOfMemOps - 1));
3121
3122 // The SK_MergeTwoSrc shuffle clobbers one of src operands.
3123 // When we have more than one destination, we need additional instructions
3124 // to keep sources.
3125 unsigned NumOfMoves = 0;
3126 if (NumOfResults > 1 && ShuffleKind == TTI::SK_PermuteTwoSrc)
3127 NumOfMoves = NumOfResults * NumOfShufflesPerResult / 2;
3128
3129 int Cost = NumOfResults * NumOfShufflesPerResult * ShuffleCost +
3130 NumOfUnfoldedLoads * MemOpCost + NumOfMoves;
3131
3132 return Cost;
3133 }
3134
3135 // Store.
3136 assert(Opcode == Instruction::Store &&((Opcode == Instruction::Store && "Expected Store Instruction at this point"
) ? static_cast<void> (0) : __assert_fail ("Opcode == Instruction::Store && \"Expected Store Instruction at this point\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86TargetTransformInfo.cpp"
, 3137, __PRETTY_FUNCTION__))
3137 "Expected Store Instruction at this point")((Opcode == Instruction::Store && "Expected Store Instruction at this point"
) ? static_cast<void> (0) : __assert_fail ("Opcode == Instruction::Store && \"Expected Store Instruction at this point\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86TargetTransformInfo.cpp"
, 3137, __PRETTY_FUNCTION__))
;
3138 // X86InterleavedAccess support only the following interleaved-access group.
3139 static const CostTblEntry AVX512InterleavedStoreTbl[] = {
3140 {3, MVT::v16i8, 12}, // interleave 3 x 16i8 into 48i8 (and store)
3141 {3, MVT::v32i8, 14}, // interleave 3 x 32i8 into 96i8 (and store)
3142 {3, MVT::v64i8, 26}, // interleave 3 x 64i8 into 96i8 (and store)
3143
3144 {4, MVT::v8i8, 10}, // interleave 4 x 8i8 into 32i8 (and store)
3145 {4, MVT::v16i8, 11}, // interleave 4 x 16i8 into 64i8 (and store)
3146 {4, MVT::v32i8, 14}, // interleave 4 x 32i8 into 128i8 (and store)
3147 {4, MVT::v64i8, 24} // interleave 4 x 32i8 into 256i8 (and store)
3148 };
3149
3150 if (const auto *Entry =
3151 CostTableLookup(AVX512InterleavedStoreTbl, Factor, VT))
3152 return NumOfMemOps * MemOpCost + Entry->Cost;
3153 //If an entry does not exist, fallback to the default implementation.
3154
3155 // There is no strided stores meanwhile. And store can't be folded in
3156 // shuffle.
3157 unsigned NumOfSources = Factor; // The number of values to be merged.
3158 unsigned ShuffleCost =
3159 getShuffleCost(TTI::SK_PermuteTwoSrc, SingleMemOpTy, 0, nullptr);
3160 unsigned NumOfShufflesPerStore = NumOfSources - 1;
3161
3162 // The SK_MergeTwoSrc shuffle clobbers one of src operands.
3163 // We need additional instructions to keep sources.
3164 unsigned NumOfMoves = NumOfMemOps * NumOfShufflesPerStore / 2;
3165 int Cost = NumOfMemOps * (MemOpCost + NumOfShufflesPerStore * ShuffleCost) +
3166 NumOfMoves;
3167 return Cost;
3168}
3169
3170int X86TTIImpl::getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy,
3171 unsigned Factor,
3172 ArrayRef<unsigned> Indices,
3173 unsigned Alignment,
3174 unsigned AddressSpace,
3175 bool UseMaskForCond,
3176 bool UseMaskForGaps) {
3177 auto isSupportedOnAVX512 = [](Type *VecTy, bool HasBW) {
3178 Type *EltTy = VecTy->getVectorElementType();
3179 if (EltTy->isFloatTy() || EltTy->isDoubleTy() || EltTy->isIntegerTy(64) ||
3180 EltTy->isIntegerTy(32) || EltTy->isPointerTy())
3181 return true;
3182 if (EltTy->isIntegerTy(16) || EltTy->isIntegerTy(8))
3183 return HasBW;
3184 return false;
3185 };
3186 if (ST->hasAVX512() && isSupportedOnAVX512(VecTy, ST->hasBWI()))
3187 return getInterleavedMemoryOpCostAVX512(Opcode, VecTy, Factor, Indices,
3188 Alignment, AddressSpace,
3189 UseMaskForCond, UseMaskForGaps);
3190 if (ST->hasAVX2())
3191 return getInterleavedMemoryOpCostAVX2(Opcode, VecTy, Factor, Indices,
3192 Alignment, AddressSpace,
3193 UseMaskForCond, UseMaskForGaps);
3194
3195 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices,
3196 Alignment, AddressSpace,
3197 UseMaskForCond, UseMaskForGaps);
3198}

/build/llvm-toolchain-snapshot-8~svn350071/include/llvm/Analysis/TargetTransformInfoImpl.h

1//===- TargetTransformInfoImpl.h --------------------------------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9/// \file
10/// This file provides helpers for the implementation of
11/// a TargetTransformInfo-conforming class.
12///
13//===----------------------------------------------------------------------===//
14
15#ifndef LLVM_ANALYSIS_TARGETTRANSFORMINFOIMPL_H
16#define LLVM_ANALYSIS_TARGETTRANSFORMINFOIMPL_H
17
18#include "llvm/Analysis/ScalarEvolutionExpressions.h"
19#include "llvm/Analysis/TargetTransformInfo.h"
20#include "llvm/Analysis/VectorUtils.h"
21#include "llvm/IR/CallSite.h"
22#include "llvm/IR/DataLayout.h"
23#include "llvm/IR/Function.h"
24#include "llvm/IR/GetElementPtrTypeIterator.h"
25#include "llvm/IR/Operator.h"
26#include "llvm/IR/Type.h"
27
28namespace llvm {
29
30/// Base class for use as a mix-in that aids implementing
31/// a TargetTransformInfo-compatible class.
32class TargetTransformInfoImplBase {
33protected:
34 typedef TargetTransformInfo TTI;
35
36 const DataLayout &DL;
37
38 explicit TargetTransformInfoImplBase(const DataLayout &DL) : DL(DL) {}
39
40public:
41 // Provide value semantics. MSVC requires that we spell all of these out.
42 TargetTransformInfoImplBase(const TargetTransformInfoImplBase &Arg)
43 : DL(Arg.DL) {}
44 TargetTransformInfoImplBase(TargetTransformInfoImplBase &&Arg) : DL(Arg.DL) {}
45
46 const DataLayout &getDataLayout() const { return DL; }
47
48 unsigned getOperationCost(unsigned Opcode, Type *Ty, Type *OpTy) {
49 switch (Opcode) {
16
Control jumps to 'case IntToPtr:' at line 74
50 default:
51 // By default, just classify everything as 'basic'.
52 return TTI::TCC_Basic;
53
54 case Instruction::GetElementPtr:
55 llvm_unreachable("Use getGEPCost for GEP operations!")::llvm::llvm_unreachable_internal("Use getGEPCost for GEP operations!"
, "/build/llvm-toolchain-snapshot-8~svn350071/include/llvm/Analysis/TargetTransformInfoImpl.h"
, 55)
;
56
57 case Instruction::BitCast:
58 assert(OpTy && "Cast instructions must provide the operand type")((OpTy && "Cast instructions must provide the operand type"
) ? static_cast<void> (0) : __assert_fail ("OpTy && \"Cast instructions must provide the operand type\""
, "/build/llvm-toolchain-snapshot-8~svn350071/include/llvm/Analysis/TargetTransformInfoImpl.h"
, 58, __PRETTY_FUNCTION__))
;
59 if (Ty == OpTy || (Ty->isPointerTy() && OpTy->isPointerTy()))
60 // Identity and pointer-to-pointer casts are free.
61 return TTI::TCC_Free;
62
63 // Otherwise, the default basic cost is used.
64 return TTI::TCC_Basic;
65
66 case Instruction::FDiv:
67 case Instruction::FRem:
68 case Instruction::SDiv:
69 case Instruction::SRem:
70 case Instruction::UDiv:
71 case Instruction::URem:
72 return TTI::TCC_Expensive;
73
74 case Instruction::IntToPtr: {
75 // An inttoptr cast is free so long as the input is a legal integer type
76 // which doesn't contain values outside the range of a pointer.
77 unsigned OpSize = OpTy->getScalarSizeInBits();
17
Called C++ object pointer is null
78 if (DL.isLegalInteger(OpSize) &&
79 OpSize <= DL.getPointerTypeSizeInBits(Ty))
80 return TTI::TCC_Free;
81
82 // Otherwise it's not a no-op.
83 return TTI::TCC_Basic;
84 }
85 case Instruction::PtrToInt: {
86 // A ptrtoint cast is free so long as the result is large enough to store
87 // the pointer, and a legal integer type.
88 unsigned DestSize = Ty->getScalarSizeInBits();
89 if (DL.isLegalInteger(DestSize) &&
90 DestSize >= DL.getPointerTypeSizeInBits(OpTy))
91 return TTI::TCC_Free;
92
93 // Otherwise it's not a no-op.
94 return TTI::TCC_Basic;
95 }
96 case Instruction::Trunc:
97 // trunc to a native type is free (assuming the target has compare and
98 // shift-right of the same width).
99 if (DL.isLegalInteger(DL.getTypeSizeInBits(Ty)))
100 return TTI::TCC_Free;
101
102 return TTI::TCC_Basic;
103 }
104 }
105
106 int getGEPCost(Type *PointeeType, const Value *Ptr,
107 ArrayRef<const Value *> Operands) {
108 // In the basic model, we just assume that all-constant GEPs will be folded
109 // into their uses via addressing modes.
110 for (unsigned Idx = 0, Size = Operands.size(); Idx != Size; ++Idx)
111 if (!isa<Constant>(Operands[Idx]))
112 return TTI::TCC_Basic;
113
114 return TTI::TCC_Free;
115 }
116
117 unsigned getEstimatedNumberOfCaseClusters(const SwitchInst &SI,
118 unsigned &JTSize) {
119 JTSize = 0;
120 return SI.getNumCases();
121 }
122
123 int getExtCost(const Instruction *I, const Value *Src) {
124 return TTI::TCC_Basic;
125 }
126
127 unsigned getCallCost(FunctionType *FTy, int NumArgs) {
128 assert(FTy && "FunctionType must be provided to this routine.")((FTy && "FunctionType must be provided to this routine."
) ? static_cast<void> (0) : __assert_fail ("FTy && \"FunctionType must be provided to this routine.\""
, "/build/llvm-toolchain-snapshot-8~svn350071/include/llvm/Analysis/TargetTransformInfoImpl.h"
, 128, __PRETTY_FUNCTION__))
;
129
130 // The target-independent implementation just measures the size of the
131 // function by approximating that each argument will take on average one
132 // instruction to prepare.
133
134 if (NumArgs < 0)
135 // Set the argument number to the number of explicit arguments in the
136 // function.
137 NumArgs = FTy->getNumParams();
138
139 return TTI::TCC_Basic * (NumArgs + 1);
140 }
141
142 unsigned getInliningThresholdMultiplier() { return 1; }
143
144 unsigned getIntrinsicCost(Intrinsic::ID IID, Type *RetTy,
145 ArrayRef<Type *> ParamTys) {
146 switch (IID) {
147 default:
148 // Intrinsics rarely (if ever) have normal argument setup constraints.
149 // Model them as having a basic instruction cost.
150 // FIXME: This is wrong for libc intrinsics.
151 return TTI::TCC_Basic;
152
153 case Intrinsic::annotation:
154 case Intrinsic::assume:
155 case Intrinsic::sideeffect:
156 case Intrinsic::dbg_declare:
157 case Intrinsic::dbg_value:
158 case Intrinsic::dbg_label:
159 case Intrinsic::invariant_start:
160 case Intrinsic::invariant_end:
161 case Intrinsic::launder_invariant_group:
162 case Intrinsic::strip_invariant_group:
163 case Intrinsic::is_constant:
164 case Intrinsic::lifetime_start:
165 case Intrinsic::lifetime_end:
166 case Intrinsic::objectsize:
167 case Intrinsic::ptr_annotation:
168 case Intrinsic::var_annotation:
169 case Intrinsic::experimental_gc_result:
170 case Intrinsic::experimental_gc_relocate:
171 case Intrinsic::coro_alloc:
172 case Intrinsic::coro_begin:
173 case Intrinsic::coro_free:
174 case Intrinsic::coro_end:
175 case Intrinsic::coro_frame:
176 case Intrinsic::coro_size:
177 case Intrinsic::coro_suspend:
178 case Intrinsic::coro_param:
179 case Intrinsic::coro_subfn_addr:
180 // These intrinsics don't actually represent code after lowering.
181 return TTI::TCC_Free;
182 }
183 }
184
185 bool hasBranchDivergence() { return false; }
186
187 bool isSourceOfDivergence(const Value *V) { return false; }
188
189 bool isAlwaysUniform(const Value *V) { return false; }
190
191 unsigned getFlatAddressSpace () {
192 return -1;
193 }
194
195 bool isLoweredToCall(const Function *F) {
196 assert(F && "A concrete function must be provided to this routine.")((F && "A concrete function must be provided to this routine."
) ? static_cast<void> (0) : __assert_fail ("F && \"A concrete function must be provided to this routine.\""
, "/build/llvm-toolchain-snapshot-8~svn350071/include/llvm/Analysis/TargetTransformInfoImpl.h"
, 196, __PRETTY_FUNCTION__))
;
197
198 // FIXME: These should almost certainly not be handled here, and instead
199 // handled with the help of TLI or the target itself. This was largely
200 // ported from existing analysis heuristics here so that such refactorings
201 // can take place in the future.
202
203 if (F->isIntrinsic())
204 return false;
205
206 if (F->hasLocalLinkage() || !F->hasName())
207 return true;
208
209 StringRef Name = F->getName();
210
211 // These will all likely lower to a single selection DAG node.
212 if (Name == "copysign" || Name == "copysignf" || Name == "copysignl" ||
213 Name == "fabs" || Name == "fabsf" || Name == "fabsl" || Name == "sin" ||
214 Name == "fmin" || Name == "fminf" || Name == "fminl" ||
215 Name == "fmax" || Name == "fmaxf" || Name == "fmaxl" ||
216 Name == "sinf" || Name == "sinl" || Name == "cos" || Name == "cosf" ||
217 Name == "cosl" || Name == "sqrt" || Name == "sqrtf" || Name == "sqrtl")
218 return false;
219
220 // These are all likely to be optimized into something smaller.
221 if (Name == "pow" || Name == "powf" || Name == "powl" || Name == "exp2" ||
222 Name == "exp2l" || Name == "exp2f" || Name == "floor" ||
223 Name == "floorf" || Name == "ceil" || Name == "round" ||
224 Name == "ffs" || Name == "ffsl" || Name == "abs" || Name == "labs" ||
225 Name == "llabs")
226 return false;
227
228 return true;
229 }
230
231 void getUnrollingPreferences(Loop *, ScalarEvolution &,
232 TTI::UnrollingPreferences &) {}
233
234 bool isLegalAddImmediate(int64_t Imm) { return false; }
235
236 bool isLegalICmpImmediate(int64_t Imm) { return false; }
237
238 bool isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset,
239 bool HasBaseReg, int64_t Scale,
240 unsigned AddrSpace, Instruction *I = nullptr) {
241 // Guess that only reg and reg+reg addressing is allowed. This heuristic is
242 // taken from the implementation of LSR.
243 return !BaseGV && BaseOffset == 0 && (Scale == 0 || Scale == 1);
244 }
245
246 bool isLSRCostLess(TTI::LSRCost &C1, TTI::LSRCost &C2) {
247 return std::tie(C1.NumRegs, C1.AddRecCost, C1.NumIVMuls, C1.NumBaseAdds,
248 C1.ScaleCost, C1.ImmCost, C1.SetupCost) <
249 std::tie(C2.NumRegs, C2.AddRecCost, C2.NumIVMuls, C2.NumBaseAdds,
250 C2.ScaleCost, C2.ImmCost, C2.SetupCost);
251 }
252
253 bool canMacroFuseCmp() { return false; }
254
255 bool shouldFavorPostInc() const { return false; }
256
257 bool isLegalMaskedStore(Type *DataType) { return false; }
258
259 bool isLegalMaskedLoad(Type *DataType) { return false; }
260
261 bool isLegalMaskedScatter(Type *DataType) { return false; }
262
263 bool isLegalMaskedGather(Type *DataType) { return false; }
264
265 bool hasDivRemOp(Type *DataType, bool IsSigned) { return false; }
266
267 bool hasVolatileVariant(Instruction *I, unsigned AddrSpace) { return false; }
268
269 bool prefersVectorizedAddressing() { return true; }
270
271 int getScalingFactorCost(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset,
272 bool HasBaseReg, int64_t Scale, unsigned AddrSpace) {
273 // Guess that all legal addressing mode are free.
274 if (isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg,
275 Scale, AddrSpace))
276 return 0;
277 return -1;
278 }
279
280 bool LSRWithInstrQueries() { return false; }
281
282 bool isTruncateFree(Type *Ty1, Type *Ty2) { return false; }
283
284 bool isProfitableToHoist(Instruction *I) { return true; }
285
286 bool useAA() { return false; }
287
288 bool isTypeLegal(Type *Ty) { return false; }
289
290 unsigned getJumpBufAlignment() { return 0; }
291
292 unsigned getJumpBufSize() { return 0; }
293
294 bool shouldBuildLookupTables() { return true; }
295 bool shouldBuildLookupTablesForConstant(Constant *C) { return true; }
296
297 bool useColdCCForColdCall(Function &F) { return false; }
298
299 unsigned getScalarizationOverhead(Type *Ty, bool Insert, bool Extract) {
300 return 0;
301 }
302
303 unsigned getOperandsScalarizationOverhead(ArrayRef<const Value *> Args,
304 unsigned VF) { return 0; }
305
306 bool supportsEfficientVectorElementLoadStore() { return false; }
307
308 bool enableAggressiveInterleaving(bool LoopHasReductions) { return false; }
309
310 const TTI::MemCmpExpansionOptions *enableMemCmpExpansion(
311 bool IsZeroCmp) const {
312 return nullptr;
313 }
314
315 bool enableInterleavedAccessVectorization() { return false; }
316
317 bool enableMaskedInterleavedAccessVectorization() { return false; }
318
319 bool isFPVectorizationPotentiallyUnsafe() { return false; }
320
321 bool allowsMisalignedMemoryAccesses(LLVMContext &Context,
322 unsigned BitWidth,
323 unsigned AddressSpace,
324 unsigned Alignment,
325 bool *Fast) { return false; }
326
327 TTI::PopcntSupportKind getPopcntSupport(unsigned IntTyWidthInBit) {
328 return TTI::PSK_Software;
329 }
330
331 bool haveFastSqrt(Type *Ty) { return false; }
332
333 bool isFCmpOrdCheaperThanFCmpZero(Type *Ty) { return true; }
334
335 unsigned getFPOpCost(Type *Ty) { return TargetTransformInfo::TCC_Basic; }
336
337 int getIntImmCodeSizeCost(unsigned Opcode, unsigned Idx, const APInt &Imm,
338 Type *Ty) {
339 return 0;
340 }
341
342 unsigned getIntImmCost(const APInt &Imm, Type *Ty) { return TTI::TCC_Basic; }
343
344 unsigned getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm,
345 Type *Ty) {
346 return TTI::TCC_Free;
347 }
348
349 unsigned getIntImmCost(Intrinsic::ID IID, unsigned Idx, const APInt &Imm,
350 Type *Ty) {
351 return TTI::TCC_Free;
352 }
353
354 unsigned getNumberOfRegisters(bool Vector) { return 8; }
355
356 unsigned getRegisterBitWidth(bool Vector) const { return 32; }
357
358 unsigned getMinVectorRegisterBitWidth() { return 128; }
359
360 bool shouldMaximizeVectorBandwidth(bool OptSize) const { return false; }
361
362 unsigned getMinimumVF(unsigned ElemWidth) const { return 0; }
363
364 bool
365 shouldConsiderAddressTypePromotion(const Instruction &I,
366 bool &AllowPromotionWithoutCommonHeader) {
367 AllowPromotionWithoutCommonHeader = false;
368 return false;
369 }
370
371 unsigned getCacheLineSize() { return 0; }
372
373 llvm::Optional<unsigned> getCacheSize(TargetTransformInfo::CacheLevel Level) {
374 switch (Level) {
375 case TargetTransformInfo::CacheLevel::L1D:
376 LLVM_FALLTHROUGH[[clang::fallthrough]];
377 case TargetTransformInfo::CacheLevel::L2D:
378 return llvm::Optional<unsigned>();
379 }
380
381 llvm_unreachable("Unknown TargetTransformInfo::CacheLevel")::llvm::llvm_unreachable_internal("Unknown TargetTransformInfo::CacheLevel"
, "/build/llvm-toolchain-snapshot-8~svn350071/include/llvm/Analysis/TargetTransformInfoImpl.h"
, 381)
;
382 }
383
384 llvm::Optional<unsigned> getCacheAssociativity(
385 TargetTransformInfo::CacheLevel Level) {
386 switch (Level) {
387 case TargetTransformInfo::CacheLevel::L1D:
388 LLVM_FALLTHROUGH[[clang::fallthrough]];
389 case TargetTransformInfo::CacheLevel::L2D:
390 return llvm::Optional<unsigned>();
391 }
392
393 llvm_unreachable("Unknown TargetTransformInfo::CacheLevel")::llvm::llvm_unreachable_internal("Unknown TargetTransformInfo::CacheLevel"
, "/build/llvm-toolchain-snapshot-8~svn350071/include/llvm/Analysis/TargetTransformInfoImpl.h"
, 393)
;
394 }
395
396 unsigned getPrefetchDistance() { return 0; }
397
398 unsigned getMinPrefetchStride() { return 1; }
399
400 unsigned getMaxPrefetchIterationsAhead() { return UINT_MAX(2147483647 *2U +1U); }
401
402 unsigned getMaxInterleaveFactor(unsigned VF) { return 1; }
403
404 unsigned getArithmeticInstrCost(unsigned Opcode, Type *Ty,
405 TTI::OperandValueKind Opd1Info,
406 TTI::OperandValueKind Opd2Info,
407 TTI::OperandValueProperties Opd1PropInfo,
408 TTI::OperandValueProperties Opd2PropInfo,
409 ArrayRef<const Value *> Args) {
410 return 1;
411 }
412
413 unsigned getShuffleCost(TTI::ShuffleKind Kind, Type *Ty, int Index,
414 Type *SubTp) {
415 return 1;
416 }
417
418 unsigned getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src,
419 const Instruction *I) { return 1; }
420
421 unsigned getExtractWithExtendCost(unsigned Opcode, Type *Dst,
422 VectorType *VecTy, unsigned Index) {
423 return 1;
424 }
425
426 unsigned getCFInstrCost(unsigned Opcode) { return 1; }
427
428 unsigned getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy,
429 const Instruction *I) {
430 return 1;
431 }
432
433 unsigned getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index) {
434 return 1;
435 }
436
437 unsigned getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment,
438 unsigned AddressSpace, const Instruction *I) {
439 return 1;
440 }
441
442 unsigned getMaskedMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment,
443 unsigned AddressSpace) {
444 return 1;
445 }
446
447 unsigned getGatherScatterOpCost(unsigned Opcode, Type *DataTy, Value *Ptr,
448 bool VariableMask,
449 unsigned Alignment) {
450 return 1;
451 }
452
453 unsigned getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy,
454 unsigned Factor,
455 ArrayRef<unsigned> Indices,
456 unsigned Alignment, unsigned AddressSpace,
457 bool UseMaskForCond = false,
458 bool UseMaskForGaps = false) {
459 return 1;
460 }
461
462 unsigned getIntrinsicInstrCost(Intrinsic::ID ID, Type *RetTy,
463 ArrayRef<Type *> Tys, FastMathFlags FMF,
464 unsigned ScalarizationCostPassed) {
465 return 1;
466 }
467 unsigned getIntrinsicInstrCost(Intrinsic::ID ID, Type *RetTy,
468 ArrayRef<Value *> Args, FastMathFlags FMF, unsigned VF) {
469 return 1;
470 }
471
472 unsigned getCallInstrCost(Function *F, Type *RetTy, ArrayRef<Type *> Tys) {
473 return 1;
474 }
475
476 unsigned getNumberOfParts(Type *Tp) { return 0; }
477
478 unsigned getAddressComputationCost(Type *Tp, ScalarEvolution *,
479 const SCEV *) {
480 return 0;
481 }
482
483 unsigned getArithmeticReductionCost(unsigned, Type *, bool) { return 1; }
484
485 unsigned getMinMaxReductionCost(Type *, Type *, bool, bool) { return 1; }
486
487 unsigned getCostOfKeepingLiveOverCall(ArrayRef<Type *> Tys) { return 0; }
488
489 bool getTgtMemIntrinsic(IntrinsicInst *Inst, MemIntrinsicInfo &Info) {
490 return false;
491 }
492
493 unsigned getAtomicMemIntrinsicMaxElementSize() const {
494 // Note for overrides: You must ensure for all element unordered-atomic
495 // memory intrinsics that all power-of-2 element sizes up to, and
496 // including, the return value of this method have a corresponding
497 // runtime lib call. These runtime lib call definitions can be found
498 // in RuntimeLibcalls.h
499 return 0;
500 }
501
502 Value *getOrCreateResultFromMemIntrinsic(IntrinsicInst *Inst,
503 Type *ExpectedType) {
504 return nullptr;
505 }
506
507 Type *getMemcpyLoopLoweringType(LLVMContext &Context, Value *Length,
508 unsigned SrcAlign, unsigned DestAlign) const {
509 return Type::getInt8Ty(Context);
510 }
511
512 void getMemcpyLoopResidualLoweringType(SmallVectorImpl<Type *> &OpsOut,
513 LLVMContext &Context,
514 unsigned RemainingBytes,
515 unsigned SrcAlign,
516 unsigned DestAlign) const {
517 for (unsigned i = 0; i != RemainingBytes; ++i)
518 OpsOut.push_back(Type::getInt8Ty(Context));
519 }
520
521 bool areInlineCompatible(const Function *Caller,
522 const Function *Callee) const {
523 return (Caller->getFnAttribute("target-cpu") ==
524 Callee->getFnAttribute("target-cpu")) &&
525 (Caller->getFnAttribute("target-features") ==
526 Callee->getFnAttribute("target-features"));
527 }
528
529 bool isIndexedLoadLegal(TTI::MemIndexedMode Mode, Type *Ty,
530 const DataLayout &DL) const {
531 return false;
532 }
533
534 bool isIndexedStoreLegal(TTI::MemIndexedMode Mode, Type *Ty,
535 const DataLayout &DL) const {
536 return false;
537 }
538
539 unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const { return 128; }
540
541 bool isLegalToVectorizeLoad(LoadInst *LI) const { return true; }
542
543 bool isLegalToVectorizeStore(StoreInst *SI) const { return true; }
544
545 bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes,
546 unsigned Alignment,
547 unsigned AddrSpace) const {
548 return true;
549 }
550
551 bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes,
552 unsigned Alignment,
553 unsigned AddrSpace) const {
554 return true;
555 }
556
557 unsigned getLoadVectorFactor(unsigned VF, unsigned LoadSize,
558 unsigned ChainSizeInBytes,
559 VectorType *VecTy) const {
560 return VF;
561 }
562
563 unsigned getStoreVectorFactor(unsigned VF, unsigned StoreSize,
564 unsigned ChainSizeInBytes,
565 VectorType *VecTy) const {
566 return VF;
567 }
568
569 bool useReductionIntrinsic(unsigned Opcode, Type *Ty,
570 TTI::ReductionFlags Flags) const {
571 return false;
572 }
573
574 bool shouldExpandReduction(const IntrinsicInst *II) const {
575 return true;
576 }
577
578protected:
579 // Obtain the minimum required size to hold the value (without the sign)
580 // In case of a vector it returns the min required size for one element.
581 unsigned minRequiredElementSize(const Value* Val, bool &isSigned) {
582 if (isa<ConstantDataVector>(Val) || isa<ConstantVector>(Val)) {
583 const auto* VectorValue = cast<Constant>(Val);
584
585 // In case of a vector need to pick the max between the min
586 // required size for each element
587 auto *VT = cast<VectorType>(Val->getType());
588
589 // Assume unsigned elements
590 isSigned = false;
591
592 // The max required size is the total vector width divided by num
593 // of elements in the vector
594 unsigned MaxRequiredSize = VT->getBitWidth() / VT->getNumElements();
595
596 unsigned MinRequiredSize = 0;
597 for(unsigned i = 0, e = VT->getNumElements(); i < e; ++i) {
598 if (auto* IntElement =
599 dyn_cast<ConstantInt>(VectorValue->getAggregateElement(i))) {
600 bool signedElement = IntElement->getValue().isNegative();
601 // Get the element min required size.
602 unsigned ElementMinRequiredSize =
603 IntElement->getValue().getMinSignedBits() - 1;
604 // In case one element is signed then all the vector is signed.
605 isSigned |= signedElement;
606 // Save the max required bit size between all the elements.
607 MinRequiredSize = std::max(MinRequiredSize, ElementMinRequiredSize);
608 }
609 else {
610 // not an int constant element
611 return MaxRequiredSize;
612 }
613 }
614 return MinRequiredSize;
615 }
616
617 if (const auto* CI = dyn_cast<ConstantInt>(Val)) {
618 isSigned = CI->getValue().isNegative();
619 return CI->getValue().getMinSignedBits() - 1;
620 }
621
622 if (const auto* Cast = dyn_cast<SExtInst>(Val)) {
623 isSigned = true;
624 return Cast->getSrcTy()->getScalarSizeInBits() - 1;
625 }
626
627 if (const auto* Cast = dyn_cast<ZExtInst>(Val)) {
628 isSigned = false;
629 return Cast->getSrcTy()->getScalarSizeInBits();
630 }
631
632 isSigned = false;
633 return Val->getType()->getScalarSizeInBits();
634 }
635
636 bool isStridedAccess(const SCEV *Ptr) {
637 return Ptr && isa<SCEVAddRecExpr>(Ptr);
638 }
639
640 const SCEVConstant *getConstantStrideStep(ScalarEvolution *SE,
641 const SCEV *Ptr) {
642 if (!isStridedAccess(Ptr))
643 return nullptr;
644 const SCEVAddRecExpr *AddRec = cast<SCEVAddRecExpr>(Ptr);
645 return dyn_cast<SCEVConstant>(AddRec->getStepRecurrence(*SE));
646 }
647
648 bool isConstantStridedAccessLessThan(ScalarEvolution *SE, const SCEV *Ptr,
649 int64_t MergeDistance) {
650 const SCEVConstant *Step = getConstantStrideStep(SE, Ptr);
651 if (!Step)
652 return false;
653 APInt StrideVal = Step->getAPInt();
654 if (StrideVal.getBitWidth() > 64)
655 return false;
656 // FIXME: Need to take absolute value for negative stride case.
657 return StrideVal.getSExtValue() < MergeDistance;
658 }
659};
660
661/// CRTP base class for use as a mix-in that aids implementing
662/// a TargetTransformInfo-compatible class.
663template <typename T>
664class TargetTransformInfoImplCRTPBase : public TargetTransformInfoImplBase {
665private:
666 typedef TargetTransformInfoImplBase BaseT;
667
668protected:
669 explicit TargetTransformInfoImplCRTPBase(const DataLayout &DL) : BaseT(DL) {}
670
671public:
672 using BaseT::getCallCost;
673
674 unsigned getCallCost(const Function *F, int NumArgs) {
675 assert(F && "A concrete function must be provided to this routine.")((F && "A concrete function must be provided to this routine."
) ? static_cast<void> (0) : __assert_fail ("F && \"A concrete function must be provided to this routine.\""
, "/build/llvm-toolchain-snapshot-8~svn350071/include/llvm/Analysis/TargetTransformInfoImpl.h"
, 675, __PRETTY_FUNCTION__))
;
676
677 if (NumArgs < 0)
678 // Set the argument number to the number of explicit arguments in the
679 // function.
680 NumArgs = F->arg_size();
681
682 if (Intrinsic::ID IID = F->getIntrinsicID()) {
683 FunctionType *FTy = F->getFunctionType();
684 SmallVector<Type *, 8> ParamTys(FTy->param_begin(), FTy->param_end());
685 return static_cast<T *>(this)
686 ->getIntrinsicCost(IID, FTy->getReturnType(), ParamTys);
687 }
688
689 if (!static_cast<T *>(this)->isLoweredToCall(F))
690 return TTI::TCC_Basic; // Give a basic cost if it will be lowered
691 // directly.
692
693 return static_cast<T *>(this)->getCallCost(F->getFunctionType(), NumArgs);
694 }
695
696 unsigned getCallCost(const Function *F, ArrayRef<const Value *> Arguments) {
697 // Simply delegate to generic handling of the call.
698 // FIXME: We should use instsimplify or something else to catch calls which
699 // will constant fold with these arguments.
700 return static_cast<T *>(this)->getCallCost(F, Arguments.size());
701 }
702
703 using BaseT::getGEPCost;
704
705 int getGEPCost(Type *PointeeType, const Value *Ptr,
706 ArrayRef<const Value *> Operands) {
707 const GlobalValue *BaseGV = nullptr;
708 if (Ptr != nullptr) {
709 // TODO: will remove this when pointers have an opaque type.
710 assert(Ptr->getType()->getScalarType()->getPointerElementType() ==((Ptr->getType()->getScalarType()->getPointerElementType
() == PointeeType && "explicit pointee type doesn't match operand's pointee type"
) ? static_cast<void> (0) : __assert_fail ("Ptr->getType()->getScalarType()->getPointerElementType() == PointeeType && \"explicit pointee type doesn't match operand's pointee type\""
, "/build/llvm-toolchain-snapshot-8~svn350071/include/llvm/Analysis/TargetTransformInfoImpl.h"
, 712, __PRETTY_FUNCTION__))
711 PointeeType &&((Ptr->getType()->getScalarType()->getPointerElementType
() == PointeeType && "explicit pointee type doesn't match operand's pointee type"
) ? static_cast<void> (0) : __assert_fail ("Ptr->getType()->getScalarType()->getPointerElementType() == PointeeType && \"explicit pointee type doesn't match operand's pointee type\""
, "/build/llvm-toolchain-snapshot-8~svn350071/include/llvm/Analysis/TargetTransformInfoImpl.h"
, 712, __PRETTY_FUNCTION__))
712 "explicit pointee type doesn't match operand's pointee type")((Ptr->getType()->getScalarType()->getPointerElementType
() == PointeeType && "explicit pointee type doesn't match operand's pointee type"
) ? static_cast<void> (0) : __assert_fail ("Ptr->getType()->getScalarType()->getPointerElementType() == PointeeType && \"explicit pointee type doesn't match operand's pointee type\""
, "/build/llvm-toolchain-snapshot-8~svn350071/include/llvm/Analysis/TargetTransformInfoImpl.h"
, 712, __PRETTY_FUNCTION__))
;
713 BaseGV = dyn_cast<GlobalValue>(Ptr->stripPointerCasts());
714 }
715 bool HasBaseReg = (BaseGV == nullptr);
716
717 auto PtrSizeBits = DL.getPointerTypeSizeInBits(Ptr->getType());
718 APInt BaseOffset(PtrSizeBits, 0);
719 int64_t Scale = 0;
720
721 auto GTI = gep_type_begin(PointeeType, Operands);
722 Type *TargetType = nullptr;
723
724 // Handle the case where the GEP instruction has a single operand,
725 // the basis, therefore TargetType is a nullptr.
726 if (Operands.empty())
727 return !BaseGV ? TTI::TCC_Free : TTI::TCC_Basic;
728
729 for (auto I = Operands.begin(); I != Operands.end(); ++I, ++GTI) {
730 TargetType = GTI.getIndexedType();
731 // We assume that the cost of Scalar GEP with constant index and the
732 // cost of Vector GEP with splat constant index are the same.
733 const ConstantInt *ConstIdx = dyn_cast<ConstantInt>(*I);
734 if (!ConstIdx)
735 if (auto Splat = getSplatValue(*I))
736 ConstIdx = dyn_cast<ConstantInt>(Splat);
737 if (StructType *STy = GTI.getStructTypeOrNull()) {
738 // For structures the index is always splat or scalar constant
739 assert(ConstIdx && "Unexpected GEP index")((ConstIdx && "Unexpected GEP index") ? static_cast<
void> (0) : __assert_fail ("ConstIdx && \"Unexpected GEP index\""
, "/build/llvm-toolchain-snapshot-8~svn350071/include/llvm/Analysis/TargetTransformInfoImpl.h"
, 739, __PRETTY_FUNCTION__))
;
740 uint64_t Field = ConstIdx->getZExtValue();
741 BaseOffset += DL.getStructLayout(STy)->getElementOffset(Field);
742 } else {
743 int64_t ElementSize = DL.getTypeAllocSize(GTI.getIndexedType());
744 if (ConstIdx) {
745 BaseOffset +=
746 ConstIdx->getValue().sextOrTrunc(PtrSizeBits) * ElementSize;
747 } else {
748 // Needs scale register.
749 if (Scale != 0)
750 // No addressing mode takes two scale registers.
751 return TTI::TCC_Basic;
752 Scale = ElementSize;
753 }
754 }
755 }
756
757 // Assumes the address space is 0 when Ptr is nullptr.
758 unsigned AS =
759 (Ptr == nullptr ? 0 : Ptr->getType()->getPointerAddressSpace());
760
761 if (static_cast<T *>(this)->isLegalAddressingMode(
762 TargetType, const_cast<GlobalValue *>(BaseGV),
763 BaseOffset.sextOrTrunc(64).getSExtValue(), HasBaseReg, Scale, AS))
764 return TTI::TCC_Free;
765 return TTI::TCC_Basic;
766 }
767
768 using BaseT::getIntrinsicCost;
769
770 unsigned getIntrinsicCost(Intrinsic::ID IID, Type *RetTy,
771 ArrayRef<const Value *> Arguments) {
772 // Delegate to the generic intrinsic handling code. This mostly provides an
773 // opportunity for targets to (for example) special case the cost of
774 // certain intrinsics based on constants used as arguments.
775 SmallVector<Type *, 8> ParamTys;
776 ParamTys.reserve(Arguments.size());
777 for (unsigned Idx = 0, Size = Arguments.size(); Idx != Size; ++Idx)
778 ParamTys.push_back(Arguments[Idx]->getType());
779 return static_cast<T *>(this)->getIntrinsicCost(IID, RetTy, ParamTys);
780 }
781
782 unsigned getUserCost(const User *U, ArrayRef<const Value *> Operands) {
783 if (isa<PHINode>(U))
3
Taking false branch
784 return TTI::TCC_Free; // Model all PHI nodes as free.
785
786 // Static alloca doesn't generate target instructions.
787 if (auto *A = dyn_cast<AllocaInst>(U))
4
Taking false branch
788 if (A->isStaticAlloca())
789 return TTI::TCC_Free;
790
791 if (const GEPOperator *GEP = dyn_cast<GEPOperator>(U)) {
5
Taking false branch
792 return static_cast<T *>(this)->getGEPCost(GEP->getSourceElementType(),
793 GEP->getPointerOperand(),
794 Operands.drop_front());
795 }
796
797 if (auto CS = ImmutableCallSite(U)) {
6
Taking false branch
798 const Function *F = CS.getCalledFunction();
799 if (!F) {
800 // Just use the called value type.
801 Type *FTy = CS.getCalledValue()->getType()->getPointerElementType();
802 return static_cast<T *>(this)
803 ->getCallCost(cast<FunctionType>(FTy), CS.arg_size());
804 }
805
806 SmallVector<const Value *, 8> Arguments(CS.arg_begin(), CS.arg_end());
807 return static_cast<T *>(this)->getCallCost(F, Arguments);
808 }
809
810 if (const CastInst *CI = dyn_cast<CastInst>(U)) {
7
Taking false branch
811 // Result of a cmp instruction is often extended (to be used by other
812 // cmp instructions, logical or return instructions). These are usually
813 // nop on most sane targets.
814 if (isa<CmpInst>(CI->getOperand(0)))
815 return TTI::TCC_Free;
816 if (isa<SExtInst>(CI) || isa<ZExtInst>(CI) || isa<FPExtInst>(CI))
817 return static_cast<T *>(this)->getExtCost(CI, Operands.back());
818 }
819
820 return static_cast<T *>(this)->getOperationCost(
11
Calling 'BasicTTIImplBase::getOperationCost'
821 Operator::getOpcode(U), U->getType(),
822 U->getNumOperands() == 1 ? U->getOperand(0)->getType() : nullptr);
8
Assuming the condition is false
9
'?' condition is false
10
Passing null pointer value via 3rd parameter 'OpTy'
823 }
824
825 int getInstructionLatency(const Instruction *I) {
826 SmallVector<const Value *, 4> Operands(I->value_op_begin(),
827 I->value_op_end());
828 if (getUserCost(I, Operands) == TTI::TCC_Free)
829 return 0;
830
831 if (isa<LoadInst>(I))
832 return 4;
833
834 Type *DstTy = I->getType();
835
836 // Usually an intrinsic is a simple instruction.
837 // A real function call is much slower.
838 if (auto *CI = dyn_cast<CallInst>(I)) {
839 const Function *F = CI->getCalledFunction();
840 if (!F || static_cast<T *>(this)->isLoweredToCall(F))
841 return 40;
842 // Some intrinsics return a value and a flag, we use the value type
843 // to decide its latency.
844 if (StructType* StructTy = dyn_cast<StructType>(DstTy))
845 DstTy = StructTy->getElementType(0);
846 // Fall through to simple instructions.
847 }
848
849 if (VectorType *VectorTy = dyn_cast<VectorType>(DstTy))
850 DstTy = VectorTy->getElementType();
851 if (DstTy->isFloatingPointTy())
852 return 3;
853
854 return 1;
855 }
856};
857}
858
859#endif

/build/llvm-toolchain-snapshot-8~svn350071/include/llvm/CodeGen/BasicTTIImpl.h

1//===- BasicTTIImpl.h -------------------------------------------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10/// \file
11/// This file provides a helper that implements much of the TTI interface in
12/// terms of the target-independent code generator and TargetLowering
13/// interfaces.
14//
15//===----------------------------------------------------------------------===//
16
17#ifndef LLVM_CODEGEN_BASICTTIIMPL_H
18#define LLVM_CODEGEN_BASICTTIIMPL_H
19
20#include "llvm/ADT/APInt.h"
21#include "llvm/ADT/ArrayRef.h"
22#include "llvm/ADT/BitVector.h"
23#include "llvm/ADT/SmallPtrSet.h"
24#include "llvm/ADT/SmallVector.h"
25#include "llvm/Analysis/LoopInfo.h"
26#include "llvm/Analysis/TargetTransformInfo.h"
27#include "llvm/Analysis/TargetTransformInfoImpl.h"
28#include "llvm/CodeGen/ISDOpcodes.h"
29#include "llvm/CodeGen/TargetLowering.h"
30#include "llvm/CodeGen/TargetSubtargetInfo.h"
31#include "llvm/CodeGen/ValueTypes.h"
32#include "llvm/IR/BasicBlock.h"
33#include "llvm/IR/CallSite.h"
34#include "llvm/IR/Constant.h"
35#include "llvm/IR/Constants.h"
36#include "llvm/IR/DataLayout.h"
37#include "llvm/IR/DerivedTypes.h"
38#include "llvm/IR/InstrTypes.h"
39#include "llvm/IR/Instruction.h"
40#include "llvm/IR/Instructions.h"
41#include "llvm/IR/Intrinsics.h"
42#include "llvm/IR/Operator.h"
43#include "llvm/IR/Type.h"
44#include "llvm/IR/Value.h"
45#include "llvm/MC/MCSchedule.h"
46#include "llvm/Support/Casting.h"
47#include "llvm/Support/CommandLine.h"
48#include "llvm/Support/ErrorHandling.h"
49#include "llvm/Support/MachineValueType.h"
50#include "llvm/Support/MathExtras.h"
51#include <algorithm>
52#include <cassert>
53#include <cstdint>
54#include <limits>
55#include <utility>
56
57namespace llvm {
58
59class Function;
60class GlobalValue;
61class LLVMContext;
62class ScalarEvolution;
63class SCEV;
64class TargetMachine;
65
66extern cl::opt<unsigned> PartialUnrollingThreshold;
67
68/// Base class which can be used to help build a TTI implementation.
69///
70/// This class provides as much implementation of the TTI interface as is
71/// possible using the target independent parts of the code generator.
72///
73/// In order to subclass it, your class must implement a getST() method to
74/// return the subtarget, and a getTLI() method to return the target lowering.
75/// We need these methods implemented in the derived class so that this class
76/// doesn't have to duplicate storage for them.
77template <typename T>
78class BasicTTIImplBase : public TargetTransformInfoImplCRTPBase<T> {
79private:
80 using BaseT = TargetTransformInfoImplCRTPBase<T>;
81 using TTI = TargetTransformInfo;
82
83 /// Estimate a cost of Broadcast as an extract and sequence of insert
84 /// operations.
85 unsigned getBroadcastShuffleOverhead(Type *Ty) {
86 assert(Ty->isVectorTy() && "Can only shuffle vectors")((Ty->isVectorTy() && "Can only shuffle vectors") ?
static_cast<void> (0) : __assert_fail ("Ty->isVectorTy() && \"Can only shuffle vectors\""
, "/build/llvm-toolchain-snapshot-8~svn350071/include/llvm/CodeGen/BasicTTIImpl.h"
, 86, __PRETTY_FUNCTION__))
;
87 unsigned Cost = 0;
88 // Broadcast cost is equal to the cost of extracting the zero'th element
89 // plus the cost of inserting it into every element of the result vector.
90 Cost += static_cast<T *>(this)->getVectorInstrCost(
91 Instruction::ExtractElement, Ty, 0);
92
93 for (int i = 0, e = Ty->getVectorNumElements(); i < e; ++i) {
94 Cost += static_cast<T *>(this)->getVectorInstrCost(
95 Instruction::InsertElement, Ty, i);
96 }
97 return Cost;
98 }
99
100 /// Estimate a cost of shuffle as a sequence of extract and insert
101 /// operations.
102 unsigned getPermuteShuffleOverhead(Type *Ty) {
103 assert(Ty->isVectorTy() && "Can only shuffle vectors")((Ty->isVectorTy() && "Can only shuffle vectors") ?
static_cast<void> (0) : __assert_fail ("Ty->isVectorTy() && \"Can only shuffle vectors\""
, "/build/llvm-toolchain-snapshot-8~svn350071/include/llvm/CodeGen/BasicTTIImpl.h"
, 103, __PRETTY_FUNCTION__))
;
104 unsigned Cost = 0;
105 // Shuffle cost is equal to the cost of extracting element from its argument
106 // plus the cost of inserting them onto the result vector.
107
108 // e.g. <4 x float> has a mask of <0,5,2,7> i.e we need to extract from
109 // index 0 of first vector, index 1 of second vector,index 2 of first
110 // vector and finally index 3 of second vector and insert them at index
111 // <0,1,2,3> of result vector.
112 for (int i = 0, e = Ty->getVectorNumElements(); i < e; ++i) {
113 Cost += static_cast<T *>(this)
114 ->getVectorInstrCost(Instruction::InsertElement, Ty, i);
115 Cost += static_cast<T *>(this)
116 ->getVectorInstrCost(Instruction::ExtractElement, Ty, i);
117 }
118 return Cost;
119 }
120
121 /// Estimate a cost of subvector extraction as a sequence of extract and
122 /// insert operations.
123 unsigned getExtractSubvectorOverhead(Type *Ty, int Index, Type *SubTy) {
124 assert(Ty && Ty->isVectorTy() && SubTy && SubTy->isVectorTy() &&((Ty && Ty->isVectorTy() && SubTy &&
SubTy->isVectorTy() && "Can only extract subvectors from vectors"
) ? static_cast<void> (0) : __assert_fail ("Ty && Ty->isVectorTy() && SubTy && SubTy->isVectorTy() && \"Can only extract subvectors from vectors\""
, "/build/llvm-toolchain-snapshot-8~svn350071/include/llvm/CodeGen/BasicTTIImpl.h"
, 125, __PRETTY_FUNCTION__))
125 "Can only extract subvectors from vectors")((Ty && Ty->isVectorTy() && SubTy &&
SubTy->isVectorTy() && "Can only extract subvectors from vectors"
) ? static_cast<void> (0) : __assert_fail ("Ty && Ty->isVectorTy() && SubTy && SubTy->isVectorTy() && \"Can only extract subvectors from vectors\""
, "/build/llvm-toolchain-snapshot-8~svn350071/include/llvm/CodeGen/BasicTTIImpl.h"
, 125, __PRETTY_FUNCTION__))
;
126 int NumSubElts = SubTy->getVectorNumElements();
127 assert((Index + NumSubElts) <= (int)Ty->getVectorNumElements() &&(((Index + NumSubElts) <= (int)Ty->getVectorNumElements
() && "SK_ExtractSubvector index out of range") ? static_cast
<void> (0) : __assert_fail ("(Index + NumSubElts) <= (int)Ty->getVectorNumElements() && \"SK_ExtractSubvector index out of range\""
, "/build/llvm-toolchain-snapshot-8~svn350071/include/llvm/CodeGen/BasicTTIImpl.h"
, 128, __PRETTY_FUNCTION__))
128 "SK_ExtractSubvector index out of range")(((Index + NumSubElts) <= (int)Ty->getVectorNumElements
() && "SK_ExtractSubvector index out of range") ? static_cast
<void> (0) : __assert_fail ("(Index + NumSubElts) <= (int)Ty->getVectorNumElements() && \"SK_ExtractSubvector index out of range\""
, "/build/llvm-toolchain-snapshot-8~svn350071/include/llvm/CodeGen/BasicTTIImpl.h"
, 128, __PRETTY_FUNCTION__))
;
129
130 unsigned Cost = 0;
131 // Subvector extraction cost is equal to the cost of extracting element from
132 // the source type plus the cost of inserting them into the result vector
133 // type.
134 for (int i = 0; i != NumSubElts; ++i) {
135 Cost += static_cast<T *>(this)->getVectorInstrCost(
136 Instruction::ExtractElement, Ty, i + Index);
137 Cost += static_cast<T *>(this)->getVectorInstrCost(
138 Instruction::InsertElement, SubTy, i);
139 }
140 return Cost;
141 }
142
143 /// Estimate a cost of subvector insertion as a sequence of extract and
144 /// insert operations.
145 unsigned getInsertSubvectorOverhead(Type *Ty, int Index, Type *SubTy) {
146 assert(Ty && Ty->isVectorTy() && SubTy && SubTy->isVectorTy() &&((Ty && Ty->isVectorTy() && SubTy &&
SubTy->isVectorTy() && "Can only insert subvectors into vectors"
) ? static_cast<void> (0) : __assert_fail ("Ty && Ty->isVectorTy() && SubTy && SubTy->isVectorTy() && \"Can only insert subvectors into vectors\""
, "/build/llvm-toolchain-snapshot-8~svn350071/include/llvm/CodeGen/BasicTTIImpl.h"
, 147, __PRETTY_FUNCTION__))
147 "Can only insert subvectors into vectors")((Ty && Ty->isVectorTy() && SubTy &&
SubTy->isVectorTy() && "Can only insert subvectors into vectors"
) ? static_cast<void> (0) : __assert_fail ("Ty && Ty->isVectorTy() && SubTy && SubTy->isVectorTy() && \"Can only insert subvectors into vectors\""
, "/build/llvm-toolchain-snapshot-8~svn350071/include/llvm/CodeGen/BasicTTIImpl.h"
, 147, __PRETTY_FUNCTION__))
;
148 int NumSubElts = SubTy->getVectorNumElements();
149 assert((Index + NumSubElts) <= (int)Ty->getVectorNumElements() &&(((Index + NumSubElts) <= (int)Ty->getVectorNumElements
() && "SK_InsertSubvector index out of range") ? static_cast
<void> (0) : __assert_fail ("(Index + NumSubElts) <= (int)Ty->getVectorNumElements() && \"SK_InsertSubvector index out of range\""
, "/build/llvm-toolchain-snapshot-8~svn350071/include/llvm/CodeGen/BasicTTIImpl.h"
, 150, __PRETTY_FUNCTION__))
150 "SK_InsertSubvector index out of range")(((Index + NumSubElts) <= (int)Ty->getVectorNumElements
() && "SK_InsertSubvector index out of range") ? static_cast
<void> (0) : __assert_fail ("(Index + NumSubElts) <= (int)Ty->getVectorNumElements() && \"SK_InsertSubvector index out of range\""
, "/build/llvm-toolchain-snapshot-8~svn350071/include/llvm/CodeGen/BasicTTIImpl.h"
, 150, __PRETTY_FUNCTION__))
;
151
152 unsigned Cost = 0;
153 // Subvector insertion cost is equal to the cost of extracting element from
154 // the source type plus the cost of inserting them into the result vector
155 // type.
156 for (int i = 0; i != NumSubElts; ++i) {
157 Cost += static_cast<T *>(this)->getVectorInstrCost(
158 Instruction::ExtractElement, SubTy, i);
159 Cost += static_cast<T *>(this)->getVectorInstrCost(
160 Instruction::InsertElement, Ty, i + Index);
161 }
162 return Cost;
163 }
164
165 /// Local query method delegates up to T which *must* implement this!
166 const TargetSubtargetInfo *getST() const {
167 return static_cast<const T *>(this)->getST();
168 }
169
170 /// Local query method delegates up to T which *must* implement this!
171 const TargetLoweringBase *getTLI() const {
172 return static_cast<const T *>(this)->getTLI();
173 }
174
175 static ISD::MemIndexedMode getISDIndexedMode(TTI::MemIndexedMode M) {
176 switch (M) {
177 case TTI::MIM_Unindexed:
178 return ISD::UNINDEXED;
179 case TTI::MIM_PreInc:
180 return ISD::PRE_INC;
181 case TTI::MIM_PreDec:
182 return ISD::PRE_DEC;
183 case TTI::MIM_PostInc:
184 return ISD::POST_INC;
185 case TTI::MIM_PostDec:
186 return ISD::POST_DEC;
187 }
188 llvm_unreachable("Unexpected MemIndexedMode")::llvm::llvm_unreachable_internal("Unexpected MemIndexedMode"
, "/build/llvm-toolchain-snapshot-8~svn350071/include/llvm/CodeGen/BasicTTIImpl.h"
, 188)
;
189 }
190
191protected:
192 explicit BasicTTIImplBase(const TargetMachine *TM, const DataLayout &DL)
193 : BaseT(DL) {}
194
195 using TargetTransformInfoImplBase::DL;
196
197public:
198 /// \name Scalar TTI Implementations
199 /// @{
200 bool allowsMisalignedMemoryAccesses(LLVMContext &Context,
201 unsigned BitWidth, unsigned AddressSpace,
202 unsigned Alignment, bool *Fast) const {
203 EVT E = EVT::getIntegerVT(Context, BitWidth);
204 return getTLI()->allowsMisalignedMemoryAccesses(E, AddressSpace, Alignment, Fast);
205 }
206
207 bool hasBranchDivergence() { return false; }
208
209 bool isSourceOfDivergence(const Value *V) { return false; }
210
211 bool isAlwaysUniform(const Value *V) { return false; }
212
213 unsigned getFlatAddressSpace() {
214 // Return an invalid address space.
215 return -1;
216 }
217
218 bool isLegalAddImmediate(int64_t imm) {
219 return getTLI()->isLegalAddImmediate(imm);
220 }
221
222 bool isLegalICmpImmediate(int64_t imm) {
223 return getTLI()->isLegalICmpImmediate(imm);
224 }
225
226 bool isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset,
227 bool HasBaseReg, int64_t Scale,
228 unsigned AddrSpace, Instruction *I = nullptr) {
229 TargetLoweringBase::AddrMode AM;
230 AM.BaseGV = BaseGV;
231 AM.BaseOffs = BaseOffset;
232 AM.HasBaseReg = HasBaseReg;
233 AM.Scale = Scale;
234 return getTLI()->isLegalAddressingMode(DL, AM, Ty, AddrSpace, I);
235 }
236
237 bool isIndexedLoadLegal(TTI::MemIndexedMode M, Type *Ty,
238 const DataLayout &DL) const {
239 EVT VT = getTLI()->getValueType(DL, Ty);
240 return getTLI()->isIndexedLoadLegal(getISDIndexedMode(M), VT);
241 }
242
243 bool isIndexedStoreLegal(TTI::MemIndexedMode M, Type *Ty,
244 const DataLayout &DL) const {
245 EVT VT = getTLI()->getValueType(DL, Ty);
246 return getTLI()->isIndexedStoreLegal(getISDIndexedMode(M), VT);
247 }
248
249 bool isLSRCostLess(TTI::LSRCost C1, TTI::LSRCost C2) {
250 return TargetTransformInfoImplBase::isLSRCostLess(C1, C2);
251 }
252
253 int getScalingFactorCost(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset,
254 bool HasBaseReg, int64_t Scale, unsigned AddrSpace) {
255 TargetLoweringBase::AddrMode AM;
256 AM.BaseGV = BaseGV;
257 AM.BaseOffs = BaseOffset;
258 AM.HasBaseReg = HasBaseReg;
259 AM.Scale = Scale;
260 return getTLI()->getScalingFactorCost(DL, AM, Ty, AddrSpace);
261 }
262
263 bool isTruncateFree(Type *Ty1, Type *Ty2) {
264 return getTLI()->isTruncateFree(Ty1, Ty2);
265 }
266
267 bool isProfitableToHoist(Instruction *I) {
268 return getTLI()->isProfitableToHoist(I);
269 }
270
271 bool useAA() const { return getST()->useAA(); }
272
273 bool isTypeLegal(Type *Ty) {
274 EVT VT = getTLI()->getValueType(DL, Ty);
275 return getTLI()->isTypeLegal(VT);
276 }
277
278 int getGEPCost(Type *PointeeType, const Value *Ptr,
279 ArrayRef<const Value *> Operands) {
280 return BaseT::getGEPCost(PointeeType, Ptr, Operands);
281 }
282
283 int getExtCost(const Instruction *I, const Value *Src) {
284 if (getTLI()->isExtFree(I))
285 return TargetTransformInfo::TCC_Free;
286
287 if (isa<ZExtInst>(I) || isa<SExtInst>(I))
288 if (const LoadInst *LI = dyn_cast<LoadInst>(Src))
289 if (getTLI()->isExtLoad(LI, I, DL))
290 return TargetTransformInfo::TCC_Free;
291
292 return TargetTransformInfo::TCC_Basic;
293 }
294
295 unsigned getIntrinsicCost(Intrinsic::ID IID, Type *RetTy,
296 ArrayRef<const Value *> Arguments) {
297 return BaseT::getIntrinsicCost(IID, RetTy, Arguments);
298 }
299
300 unsigned getIntrinsicCost(Intrinsic::ID IID, Type *RetTy,
301 ArrayRef<Type *> ParamTys) {
302 if (IID == Intrinsic::cttz) {
303 if (getTLI()->isCheapToSpeculateCttz())
304 return TargetTransformInfo::TCC_Basic;
305 return TargetTransformInfo::TCC_Expensive;
306 }
307
308 if (IID == Intrinsic::ctlz) {
309 if (getTLI()->isCheapToSpeculateCtlz())
310 return TargetTransformInfo::TCC_Basic;
311 return TargetTransformInfo::TCC_Expensive;
312 }
313
314 return BaseT::getIntrinsicCost(IID, RetTy, ParamTys);
315 }
316
317 unsigned getEstimatedNumberOfCaseClusters(const SwitchInst &SI,
318 unsigned &JumpTableSize) {
319 /// Try to find the estimated number of clusters. Note that the number of
320 /// clusters identified in this function could be different from the actural
321 /// numbers found in lowering. This function ignore switches that are
322 /// lowered with a mix of jump table / bit test / BTree. This function was
323 /// initially intended to be used when estimating the cost of switch in
324 /// inline cost heuristic, but it's a generic cost model to be used in other
325 /// places (e.g., in loop unrolling).
326 unsigned N = SI.getNumCases();
327 const TargetLoweringBase *TLI = getTLI();
328 const DataLayout &DL = this->getDataLayout();
329
330 JumpTableSize = 0;
331 bool IsJTAllowed = TLI->areJTsAllowed(SI.getParent()->getParent());
332
333 // Early exit if both a jump table and bit test are not allowed.
334 if (N < 1 || (!IsJTAllowed && DL.getIndexSizeInBits(0u) < N))
335 return N;
336
337 APInt MaxCaseVal = SI.case_begin()->getCaseValue()->getValue();
338 APInt MinCaseVal = MaxCaseVal;
339 for (auto CI : SI.cases()) {
340 const APInt &CaseVal = CI.getCaseValue()->getValue();
341 if (CaseVal.sgt(MaxCaseVal))
342 MaxCaseVal = CaseVal;
343 if (CaseVal.slt(MinCaseVal))
344 MinCaseVal = CaseVal;
345 }
346
347 // Check if suitable for a bit test
348 if (N <= DL.getIndexSizeInBits(0u)) {
349 SmallPtrSet<const BasicBlock *, 4> Dests;
350 for (auto I : SI.cases())
351 Dests.insert(I.getCaseSuccessor());
352
353 if (TLI->isSuitableForBitTests(Dests.size(), N, MinCaseVal, MaxCaseVal,
354 DL))
355 return 1;
356 }
357
358 // Check if suitable for a jump table.
359 if (IsJTAllowed) {
360 if (N < 2 || N < TLI->getMinimumJumpTableEntries())
361 return N;
362 uint64_t Range =
363 (MaxCaseVal - MinCaseVal)
364 .getLimitedValue(std::numeric_limits<uint64_t>::max() - 1) + 1;
365 // Check whether a range of clusters is dense enough for a jump table
366 if (TLI->isSuitableForJumpTable(&SI, N, Range)) {
367 JumpTableSize = Range;
368 return 1;
369 }
370 }
371 return N;
372 }
373
374 unsigned getJumpBufAlignment() { return getTLI()->getJumpBufAlignment(); }
375
376 unsigned getJumpBufSize() { return getTLI()->getJumpBufSize(); }
377
378 bool shouldBuildLookupTables() {
379 const TargetLoweringBase *TLI = getTLI();
380 return TLI->isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
381 TLI->isOperationLegalOrCustom(ISD::BRIND, MVT::Other);
382 }
383
384 bool haveFastSqrt(Type *Ty) {
385 const TargetLoweringBase *TLI = getTLI();
386 EVT VT = TLI->getValueType(DL, Ty);
387 return TLI->isTypeLegal(VT) &&
388 TLI->isOperationLegalOrCustom(ISD::FSQRT, VT);
389 }
390
391 bool isFCmpOrdCheaperThanFCmpZero(Type *Ty) {
392 return true;
393 }
394
395 unsigned getFPOpCost(Type *Ty) {
396 // Check whether FADD is available, as a proxy for floating-point in
397 // general.
398 const TargetLoweringBase *TLI = getTLI();
399 EVT VT = TLI->getValueType(DL, Ty);
400 if (TLI->isOperationLegalOrCustomOrPromote(ISD::FADD, VT))
401 return TargetTransformInfo::TCC_Basic;
402 return TargetTransformInfo::TCC_Expensive;
403 }
404
405 unsigned getOperationCost(unsigned Opcode, Type *Ty, Type *OpTy) {
406 const TargetLoweringBase *TLI = getTLI();
407 switch (Opcode) {
12
Control jumps to the 'default' case at line 408
408 default: break;
13
Execution continues on line 419
409 case Instruction::Trunc:
410 if (TLI->isTruncateFree(OpTy, Ty))
411 return TargetTransformInfo::TCC_Free;
412 return TargetTransformInfo::TCC_Basic;
413 case Instruction::ZExt:
414 if (TLI->isZExtFree(OpTy, Ty))
415 return TargetTransformInfo::TCC_Free;
416 return TargetTransformInfo::TCC_Basic;
417 }
418
419 return BaseT::getOperationCost(Opcode, Ty, OpTy);
14
Passing null pointer value via 3rd parameter 'OpTy'
15
Calling 'TargetTransformInfoImplBase::getOperationCost'
420 }
421
422 unsigned getInliningThresholdMultiplier() { return 1; }
423
424 void getUnrollingPreferences(Loop *L, ScalarEvolution &SE,
425 TTI::UnrollingPreferences &UP) {
426 // This unrolling functionality is target independent, but to provide some
427 // motivation for its intended use, for x86:
428
429 // According to the Intel 64 and IA-32 Architectures Optimization Reference
430 // Manual, Intel Core models and later have a loop stream detector (and
431 // associated uop queue) that can benefit from partial unrolling.
432 // The relevant requirements are:
433 // - The loop must have no more than 4 (8 for Nehalem and later) branches
434 // taken, and none of them may be calls.
435 // - The loop can have no more than 18 (28 for Nehalem and later) uops.
436
437 // According to the Software Optimization Guide for AMD Family 15h
438 // Processors, models 30h-4fh (Steamroller and later) have a loop predictor
439 // and loop buffer which can benefit from partial unrolling.
440 // The relevant requirements are:
441 // - The loop must have fewer than 16 branches
442 // - The loop must have less than 40 uops in all executed loop branches
443
444 // The number of taken branches in a loop is hard to estimate here, and
445 // benchmarking has revealed that it is better not to be conservative when
446 // estimating the branch count. As a result, we'll ignore the branch limits
447 // until someone finds a case where it matters in practice.
448
449 unsigned MaxOps;
450 const TargetSubtargetInfo *ST = getST();
451 if (PartialUnrollingThreshold.getNumOccurrences() > 0)
452 MaxOps = PartialUnrollingThreshold;
453 else if (ST->getSchedModel().LoopMicroOpBufferSize > 0)
454 MaxOps = ST->getSchedModel().LoopMicroOpBufferSize;
455 else
456 return;
457
458 // Scan the loop: don't unroll loops with calls.
459 for (Loop::block_iterator I = L->block_begin(), E = L->block_end(); I != E;
460 ++I) {
461 BasicBlock *BB = *I;
462
463 for (BasicBlock::iterator J = BB->begin(), JE = BB->end(); J != JE; ++J)
464 if (isa<CallInst>(J) || isa<InvokeInst>(J)) {
465 ImmutableCallSite CS(&*J);
466 if (const Function *F = CS.getCalledFunction()) {
467 if (!static_cast<T *>(this)->isLoweredToCall(F))
468 continue;
469 }
470
471 return;
472 }
473 }
474
475 // Enable runtime and partial unrolling up to the specified size.
476 // Enable using trip count upper bound to unroll loops.
477 UP.Partial = UP.Runtime = UP.UpperBound = true;
478 UP.PartialThreshold = MaxOps;
479
480 // Avoid unrolling when optimizing for size.
481 UP.OptSizeThreshold = 0;
482 UP.PartialOptSizeThreshold = 0;
483
484 // Set number of instructions optimized when "back edge"
485 // becomes "fall through" to default value of 2.
486 UP.BEInsns = 2;
487 }
488
489 int getInstructionLatency(const Instruction *I) {
490 if (isa<LoadInst>(I))
491 return getST()->getSchedModel().DefaultLoadLatency;
492
493 return BaseT::getInstructionLatency(I);
494 }
495
496 /// @}
497
498 /// \name Vector TTI Implementations
499 /// @{
500
501 unsigned getNumberOfRegisters(bool Vector) { return Vector ? 0 : 1; }
502
503 unsigned getRegisterBitWidth(bool Vector) const { return 32; }
504
505 /// Estimate the overhead of scalarizing an instruction. Insert and Extract
506 /// are set if the result needs to be inserted and/or extracted from vectors.
507 unsigned getScalarizationOverhead(Type *Ty, bool Insert, bool Extract) {
508 assert(Ty->isVectorTy() && "Can only scalarize vectors")((Ty->isVectorTy() && "Can only scalarize vectors"
) ? static_cast<void> (0) : __assert_fail ("Ty->isVectorTy() && \"Can only scalarize vectors\""
, "/build/llvm-toolchain-snapshot-8~svn350071/include/llvm/CodeGen/BasicTTIImpl.h"
, 508, __PRETTY_FUNCTION__))
;
509 unsigned Cost = 0;
510
511 for (int i = 0, e = Ty->getVectorNumElements(); i < e; ++i) {
512 if (Insert)
513 Cost += static_cast<T *>(this)
514 ->getVectorInstrCost(Instruction::InsertElement, Ty, i);
515 if (Extract)
516 Cost += static_cast<T *>(this)
517 ->getVectorInstrCost(Instruction::ExtractElement, Ty, i);
518 }
519
520 return Cost;
521 }
522
523 /// Estimate the overhead of scalarizing an instructions unique
524 /// non-constant operands. The types of the arguments are ordinarily
525 /// scalar, in which case the costs are multiplied with VF.
526 unsigned getOperandsScalarizationOverhead(ArrayRef<const Value *> Args,
527 unsigned VF) {
528 unsigned Cost = 0;
529 SmallPtrSet<const Value*, 4> UniqueOperands;
530 for (const Value *A : Args) {
531 if (!isa<Constant>(A) && UniqueOperands.insert(A).second) {
532 Type *VecTy = nullptr;
533 if (A->getType()->isVectorTy()) {
534 VecTy = A->getType();
535 // If A is a vector operand, VF should be 1 or correspond to A.
536 assert((VF == 1 || VF == VecTy->getVectorNumElements()) &&(((VF == 1 || VF == VecTy->getVectorNumElements()) &&
"Vector argument does not match VF") ? static_cast<void>
(0) : __assert_fail ("(VF == 1 || VF == VecTy->getVectorNumElements()) && \"Vector argument does not match VF\""
, "/build/llvm-toolchain-snapshot-8~svn350071/include/llvm/CodeGen/BasicTTIImpl.h"
, 537, __PRETTY_FUNCTION__))
537 "Vector argument does not match VF")(((VF == 1 || VF == VecTy->getVectorNumElements()) &&
"Vector argument does not match VF") ? static_cast<void>
(0) : __assert_fail ("(VF == 1 || VF == VecTy->getVectorNumElements()) && \"Vector argument does not match VF\""
, "/build/llvm-toolchain-snapshot-8~svn350071/include/llvm/CodeGen/BasicTTIImpl.h"
, 537, __PRETTY_FUNCTION__))
;
538 }
539 else
540 VecTy = VectorType::get(A->getType(), VF);
541
542 Cost += getScalarizationOverhead(VecTy, false, true);
543 }
544 }
545
546 return Cost;
547 }
548
549 unsigned getScalarizationOverhead(Type *VecTy, ArrayRef<const Value *> Args) {
550 assert(VecTy->isVectorTy())((VecTy->isVectorTy()) ? static_cast<void> (0) : __assert_fail
("VecTy->isVectorTy()", "/build/llvm-toolchain-snapshot-8~svn350071/include/llvm/CodeGen/BasicTTIImpl.h"
, 550, __PRETTY_FUNCTION__))
;
551
552 unsigned Cost = 0;
553
554 Cost += getScalarizationOverhead(VecTy, true, false);
555 if (!Args.empty())
556 Cost += getOperandsScalarizationOverhead(Args,
557 VecTy->getVectorNumElements());
558 else
559 // When no information on arguments is provided, we add the cost
560 // associated with one argument as a heuristic.
561 Cost += getScalarizationOverhead(VecTy, false, true);
562
563 return Cost;
564 }
565
566 unsigned getMaxInterleaveFactor(unsigned VF) { return 1; }
567
568 unsigned getArithmeticInstrCost(
569 unsigned Opcode, Type *Ty,
570 TTI::OperandValueKind Opd1Info = TTI::OK_AnyValue,
571 TTI::OperandValueKind Opd2Info = TTI::OK_AnyValue,
572 TTI::OperandValueProperties Opd1PropInfo = TTI::OP_None,
573 TTI::OperandValueProperties Opd2PropInfo = TTI::OP_None,
574 ArrayRef<const Value *> Args = ArrayRef<const Value *>()) {
575 // Check if any of the operands are vector operands.
576 const TargetLoweringBase *TLI = getTLI();
577 int ISD = TLI->InstructionOpcodeToISD(Opcode);
578 assert(ISD && "Invalid opcode")((ISD && "Invalid opcode") ? static_cast<void> (
0) : __assert_fail ("ISD && \"Invalid opcode\"", "/build/llvm-toolchain-snapshot-8~svn350071/include/llvm/CodeGen/BasicTTIImpl.h"
, 578, __PRETTY_FUNCTION__))
;
579
580 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty);
581
582 bool IsFloat = Ty->isFPOrFPVectorTy();
583 // Assume that floating point arithmetic operations cost twice as much as
584 // integer operations.
585 unsigned OpCost = (IsFloat ? 2 : 1);
586
587 if (TLI->isOperationLegalOrPromote(ISD, LT.second)) {
588 // The operation is legal. Assume it costs 1.
589 // TODO: Once we have extract/insert subvector cost we need to use them.
590 return LT.first * OpCost;
591 }
592
593 if (!TLI->isOperationExpand(ISD, LT.second)) {
594 // If the operation is custom lowered, then assume that the code is twice
595 // as expensive.
596 return LT.first * 2 * OpCost;
597 }
598
599 // Else, assume that we need to scalarize this op.
600 // TODO: If one of the types get legalized by splitting, handle this
601 // similarly to what getCastInstrCost() does.
602 if (Ty->isVectorTy()) {
603 unsigned Num = Ty->getVectorNumElements();
604 unsigned Cost = static_cast<T *>(this)
605 ->getArithmeticInstrCost(Opcode, Ty->getScalarType());
606 // Return the cost of multiple scalar invocation plus the cost of
607 // inserting and extracting the values.
608 return getScalarizationOverhead(Ty, Args) + Num * Cost;
609 }
610
611 // We don't know anything about this scalar instruction.
612 return OpCost;
613 }
614
615 unsigned getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, int Index,
616 Type *SubTp) {
617 switch (Kind) {
618 case TTI::SK_Broadcast:
619 return getBroadcastShuffleOverhead(Tp);
620 case TTI::SK_Select:
621 case TTI::SK_Reverse:
622 case TTI::SK_Transpose:
623 case TTI::SK_PermuteSingleSrc:
624 case TTI::SK_PermuteTwoSrc:
625 return getPermuteShuffleOverhead(Tp);
626 case TTI::SK_ExtractSubvector:
627 return getExtractSubvectorOverhead(Tp, Index, SubTp);
628 case TTI::SK_InsertSubvector:
629 return getInsertSubvectorOverhead(Tp, Index, SubTp);
630 }
631 llvm_unreachable("Unknown TTI::ShuffleKind")::llvm::llvm_unreachable_internal("Unknown TTI::ShuffleKind",
"/build/llvm-toolchain-snapshot-8~svn350071/include/llvm/CodeGen/BasicTTIImpl.h"
, 631)
;
632 }
633
634 unsigned getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src,
635 const Instruction *I = nullptr) {
636 const TargetLoweringBase *TLI = getTLI();
637 int ISD = TLI->InstructionOpcodeToISD(Opcode);
638 assert(ISD && "Invalid opcode")((ISD && "Invalid opcode") ? static_cast<void> (
0) : __assert_fail ("ISD && \"Invalid opcode\"", "/build/llvm-toolchain-snapshot-8~svn350071/include/llvm/CodeGen/BasicTTIImpl.h"
, 638, __PRETTY_FUNCTION__))
;
639 std::pair<unsigned, MVT> SrcLT = TLI->getTypeLegalizationCost(DL, Src);
640 std::pair<unsigned, MVT> DstLT = TLI->getTypeLegalizationCost(DL, Dst);
641
642 // Check for NOOP conversions.
643 if (SrcLT.first == DstLT.first &&
644 SrcLT.second.getSizeInBits() == DstLT.second.getSizeInBits()) {
645
646 // Bitcast between types that are legalized to the same type are free.
647 if (Opcode == Instruction::BitCast || Opcode == Instruction::Trunc)
648 return 0;
649 }
650
651 if (Opcode == Instruction::Trunc &&
652 TLI->isTruncateFree(SrcLT.second, DstLT.second))
653 return 0;
654
655 if (Opcode == Instruction::ZExt &&
656 TLI->isZExtFree(SrcLT.second, DstLT.second))
657 return 0;
658
659 if (Opcode == Instruction::AddrSpaceCast &&
660 TLI->isNoopAddrSpaceCast(Src->getPointerAddressSpace(),
661 Dst->getPointerAddressSpace()))
662 return 0;
663
664 // If this is a zext/sext of a load, return 0 if the corresponding
665 // extending load exists on target.
666 if ((Opcode == Instruction::ZExt || Opcode == Instruction::SExt) &&
667 I && isa<LoadInst>(I->getOperand(0))) {
668 EVT ExtVT = EVT::getEVT(Dst);
669 EVT LoadVT = EVT::getEVT(Src);
670 unsigned LType =
671 ((Opcode == Instruction::ZExt) ? ISD::ZEXTLOAD : ISD::SEXTLOAD);
672 if (TLI->isLoadExtLegal(LType, ExtVT, LoadVT))
673 return 0;
674 }
675
676 // If the cast is marked as legal (or promote) then assume low cost.
677 if (SrcLT.first == DstLT.first &&
678 TLI->isOperationLegalOrPromote(ISD, DstLT.second))
679 return 1;
680
681 // Handle scalar conversions.
682 if (!Src->isVectorTy() && !Dst->isVectorTy()) {
683 // Scalar bitcasts are usually free.
684 if (Opcode == Instruction::BitCast)
685 return 0;
686
687 // Just check the op cost. If the operation is legal then assume it costs
688 // 1.
689 if (!TLI->isOperationExpand(ISD, DstLT.second))
690 return 1;
691
692 // Assume that illegal scalar instruction are expensive.
693 return 4;
694 }
695
696 // Check vector-to-vector casts.
697 if (Dst->isVectorTy() && Src->isVectorTy()) {
698 // If the cast is between same-sized registers, then the check is simple.
699 if (SrcLT.first == DstLT.first &&
700 SrcLT.second.getSizeInBits() == DstLT.second.getSizeInBits()) {
701
702 // Assume that Zext is done using AND.
703 if (Opcode == Instruction::ZExt)
704 return 1;
705
706 // Assume that sext is done using SHL and SRA.
707 if (Opcode == Instruction::SExt)
708 return 2;
709
710 // Just check the op cost. If the operation is legal then assume it
711 // costs
712 // 1 and multiply by the type-legalization overhead.
713 if (!TLI->isOperationExpand(ISD, DstLT.second))
714 return SrcLT.first * 1;
715 }
716
717 // If we are legalizing by splitting, query the concrete TTI for the cost
718 // of casting the original vector twice. We also need to factor in the
719 // cost of the split itself. Count that as 1, to be consistent with
720 // TLI->getTypeLegalizationCost().
721 if ((TLI->getTypeAction(Src->getContext(), TLI->getValueType(DL, Src)) ==
722 TargetLowering::TypeSplitVector) ||
723 (TLI->getTypeAction(Dst->getContext(), TLI->getValueType(DL, Dst)) ==
724 TargetLowering::TypeSplitVector)) {
725 Type *SplitDst = VectorType::get(Dst->getVectorElementType(),
726 Dst->getVectorNumElements() / 2);
727 Type *SplitSrc = VectorType::get(Src->getVectorElementType(),
728 Src->getVectorNumElements() / 2);
729 T *TTI = static_cast<T *>(this);
730 return TTI->getVectorSplitCost() +
731 (2 * TTI->getCastInstrCost(Opcode, SplitDst, SplitSrc, I));
732 }
733
734 // In other cases where the source or destination are illegal, assume
735 // the operation will get scalarized.
736 unsigned Num = Dst->getVectorNumElements();
737 unsigned Cost = static_cast<T *>(this)->getCastInstrCost(
738 Opcode, Dst->getScalarType(), Src->getScalarType(), I);
739
740 // Return the cost of multiple scalar invocation plus the cost of
741 // inserting and extracting the values.
742 return getScalarizationOverhead(Dst, true, true) + Num * Cost;
743 }
744
745 // We already handled vector-to-vector and scalar-to-scalar conversions.
746 // This
747 // is where we handle bitcast between vectors and scalars. We need to assume
748 // that the conversion is scalarized in one way or another.
749 if (Opcode == Instruction::BitCast)
750 // Illegal bitcasts are done by storing and loading from a stack slot.
751 return (Src->isVectorTy() ? getScalarizationOverhead(Src, false, true)
752 : 0) +
753 (Dst->isVectorTy() ? getScalarizationOverhead(Dst, true, false)
754 : 0);
755
756 llvm_unreachable("Unhandled cast")::llvm::llvm_unreachable_internal("Unhandled cast", "/build/llvm-toolchain-snapshot-8~svn350071/include/llvm/CodeGen/BasicTTIImpl.h"
, 756)
;
757 }
758
759 unsigned getExtractWithExtendCost(unsigned Opcode, Type *Dst,
760 VectorType *VecTy, unsigned Index) {
761 return static_cast<T *>(this)->getVectorInstrCost(
762 Instruction::ExtractElement, VecTy, Index) +
763 static_cast<T *>(this)->getCastInstrCost(Opcode, Dst,
764 VecTy->getElementType());
765 }
766
767 unsigned getCFInstrCost(unsigned Opcode) {
768 // Branches are assumed to be predicted.
769 return 0;
770 }
771
772 unsigned getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy,
773 const Instruction *I) {
774 const TargetLoweringBase *TLI = getTLI();
775 int ISD = TLI->InstructionOpcodeToISD(Opcode);
776 assert(ISD && "Invalid opcode")((ISD && "Invalid opcode") ? static_cast<void> (
0) : __assert_fail ("ISD && \"Invalid opcode\"", "/build/llvm-toolchain-snapshot-8~svn350071/include/llvm/CodeGen/BasicTTIImpl.h"
, 776, __PRETTY_FUNCTION__))
;
777
778 // Selects on vectors are actually vector selects.
779 if (ISD == ISD::SELECT) {
780 assert(CondTy && "CondTy must exist")((CondTy && "CondTy must exist") ? static_cast<void
> (0) : __assert_fail ("CondTy && \"CondTy must exist\""
, "/build/llvm-toolchain-snapshot-8~svn350071/include/llvm/CodeGen/BasicTTIImpl.h"
, 780, __PRETTY_FUNCTION__))
;
781 if (CondTy->isVectorTy())
782 ISD = ISD::VSELECT;
783 }
784 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy);
785
786 if (!(ValTy->isVectorTy() && !LT.second.isVector()) &&
787 !TLI->isOperationExpand(ISD, LT.second)) {
788 // The operation is legal. Assume it costs 1. Multiply
789 // by the type-legalization overhead.
790 return LT.first * 1;
791 }
792
793 // Otherwise, assume that the cast is scalarized.
794 // TODO: If one of the types get legalized by splitting, handle this
795 // similarly to what getCastInstrCost() does.
796 if (ValTy->isVectorTy()) {
797 unsigned Num = ValTy->getVectorNumElements();
798 if (CondTy)
799 CondTy = CondTy->getScalarType();
800 unsigned Cost = static_cast<T *>(this)->getCmpSelInstrCost(
801 Opcode, ValTy->getScalarType(), CondTy, I);
802
803 // Return the cost of multiple scalar invocation plus the cost of
804 // inserting and extracting the values.
805 return getScalarizationOverhead(ValTy, true, false) + Num * Cost;
806 }
807
808 // Unknown scalar opcode.
809 return 1;
810 }
811
812 unsigned getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index) {
813 std::pair<unsigned, MVT> LT =
814 getTLI()->getTypeLegalizationCost(DL, Val->getScalarType());
815
816 return LT.first;
817 }
818
819 unsigned getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment,
820 unsigned AddressSpace, const Instruction *I = nullptr) {
821 assert(!Src->isVoidTy() && "Invalid type")((!Src->isVoidTy() && "Invalid type") ? static_cast
<void> (0) : __assert_fail ("!Src->isVoidTy() && \"Invalid type\""
, "/build/llvm-toolchain-snapshot-8~svn350071/include/llvm/CodeGen/BasicTTIImpl.h"
, 821, __PRETTY_FUNCTION__))
;
822 std::pair<unsigned, MVT> LT = getTLI()->getTypeLegalizationCost(DL, Src);
823
824 // Assuming that all loads of legal types cost 1.
825 unsigned Cost = LT.first;
826
827 if (Src->isVectorTy() &&
828 Src->getPrimitiveSizeInBits() < LT.second.getSizeInBits()) {
829 // This is a vector load that legalizes to a larger type than the vector
830 // itself. Unless the corresponding extending load or truncating store is
831 // legal, then this will scalarize.
832 TargetLowering::LegalizeAction LA = TargetLowering::Expand;
833 EVT MemVT = getTLI()->getValueType(DL, Src);
834 if (Opcode == Instruction::Store)
835 LA = getTLI()->getTruncStoreAction(LT.second, MemVT);
836 else
837 LA = getTLI()->getLoadExtAction(ISD::EXTLOAD, LT.second, MemVT);
838
839 if (LA != TargetLowering::Legal && LA != TargetLowering::Custom) {
840 // This is a vector load/store for some illegal type that is scalarized.
841 // We must account for the cost of building or decomposing the vector.
842 Cost += getScalarizationOverhead(Src, Opcode != Instruction::Store,
843 Opcode == Instruction::Store);
844 }
845 }
846
847 return Cost;
848 }
849
850 unsigned getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy,
851 unsigned Factor,
852 ArrayRef<unsigned> Indices,
853 unsigned Alignment, unsigned AddressSpace,
854 bool UseMaskForCond = false,
855 bool UseMaskForGaps = false) {
856 VectorType *VT = dyn_cast<VectorType>(VecTy);
857 assert(VT && "Expect a vector type for interleaved memory op")((VT && "Expect a vector type for interleaved memory op"
) ? static_cast<void> (0) : __assert_fail ("VT && \"Expect a vector type for interleaved memory op\""
, "/build/llvm-toolchain-snapshot-8~svn350071/include/llvm/CodeGen/BasicTTIImpl.h"
, 857, __PRETTY_FUNCTION__))
;
858
859 unsigned NumElts = VT->getNumElements();
860 assert(Factor > 1 && NumElts % Factor == 0 && "Invalid interleave factor")((Factor > 1 && NumElts % Factor == 0 && "Invalid interleave factor"
) ? static_cast<void> (0) : __assert_fail ("Factor > 1 && NumElts % Factor == 0 && \"Invalid interleave factor\""
, "/build/llvm-toolchain-snapshot-8~svn350071/include/llvm/CodeGen/BasicTTIImpl.h"
, 860, __PRETTY_FUNCTION__))
;
861
862 unsigned NumSubElts = NumElts / Factor;
863 VectorType *SubVT = VectorType::get(VT->getElementType(), NumSubElts);
864
865 // Firstly, the cost of load/store operation.
866 unsigned Cost;
867 if (UseMaskForCond || UseMaskForGaps)
868 Cost = static_cast<T *>(this)->getMaskedMemoryOpCost(
869 Opcode, VecTy, Alignment, AddressSpace);
870 else
871 Cost = static_cast<T *>(this)->getMemoryOpCost(Opcode, VecTy, Alignment,
872 AddressSpace);
873
874 // Legalize the vector type, and get the legalized and unlegalized type
875 // sizes.
876 MVT VecTyLT = getTLI()->getTypeLegalizationCost(DL, VecTy).second;
877 unsigned VecTySize =
878 static_cast<T *>(this)->getDataLayout().getTypeStoreSize(VecTy);
879 unsigned VecTyLTSize = VecTyLT.getStoreSize();
880
881 // Return the ceiling of dividing A by B.
882 auto ceil = [](unsigned A, unsigned B) { return (A + B - 1) / B; };
883
884 // Scale the cost of the memory operation by the fraction of legalized
885 // instructions that will actually be used. We shouldn't account for the
886 // cost of dead instructions since they will be removed.
887 //
888 // E.g., An interleaved load of factor 8:
889 // %vec = load <16 x i64>, <16 x i64>* %ptr
890 // %v0 = shufflevector %vec, undef, <0, 8>
891 //
892 // If <16 x i64> is legalized to 8 v2i64 loads, only 2 of the loads will be
893 // used (those corresponding to elements [0:1] and [8:9] of the unlegalized
894 // type). The other loads are unused.
895 //
896 // We only scale the cost of loads since interleaved store groups aren't
897 // allowed to have gaps.
898 if (Opcode == Instruction::Load && VecTySize > VecTyLTSize) {
899 // The number of loads of a legal type it will take to represent a load
900 // of the unlegalized vector type.
901 unsigned NumLegalInsts = ceil(VecTySize, VecTyLTSize);
902
903 // The number of elements of the unlegalized type that correspond to a
904 // single legal instruction.
905 unsigned NumEltsPerLegalInst = ceil(NumElts, NumLegalInsts);
906
907 // Determine which legal instructions will be used.
908 BitVector UsedInsts(NumLegalInsts, false);
909 for (unsigned Index : Indices)
910 for (unsigned Elt = 0; Elt < NumSubElts; ++Elt)
911 UsedInsts.set((Index + Elt * Factor) / NumEltsPerLegalInst);
912
913 // Scale the cost of the load by the fraction of legal instructions that
914 // will be used.
915 Cost *= UsedInsts.count() / NumLegalInsts;
916 }
917
918 // Then plus the cost of interleave operation.
919 if (Opcode == Instruction::Load) {
920 // The interleave cost is similar to extract sub vectors' elements
921 // from the wide vector, and insert them into sub vectors.
922 //
923 // E.g. An interleaved load of factor 2 (with one member of index 0):
924 // %vec = load <8 x i32>, <8 x i32>* %ptr
925 // %v0 = shuffle %vec, undef, <0, 2, 4, 6> ; Index 0
926 // The cost is estimated as extract elements at 0, 2, 4, 6 from the
927 // <8 x i32> vector and insert them into a <4 x i32> vector.
928
929 assert(Indices.size() <= Factor &&((Indices.size() <= Factor && "Interleaved memory op has too many members"
) ? static_cast<void> (0) : __assert_fail ("Indices.size() <= Factor && \"Interleaved memory op has too many members\""
, "/build/llvm-toolchain-snapshot-8~svn350071/include/llvm/CodeGen/BasicTTIImpl.h"
, 930, __PRETTY_FUNCTION__))
930 "Interleaved memory op has too many members")((Indices.size() <= Factor && "Interleaved memory op has too many members"
) ? static_cast<void> (0) : __assert_fail ("Indices.size() <= Factor && \"Interleaved memory op has too many members\""
, "/build/llvm-toolchain-snapshot-8~svn350071/include/llvm/CodeGen/BasicTTIImpl.h"
, 930, __PRETTY_FUNCTION__))
;
931
932 for (unsigned Index : Indices) {
933 assert(Index < Factor && "Invalid index for interleaved memory op")((Index < Factor && "Invalid index for interleaved memory op"
) ? static_cast<void> (0) : __assert_fail ("Index < Factor && \"Invalid index for interleaved memory op\""
, "/build/llvm-toolchain-snapshot-8~svn350071/include/llvm/CodeGen/BasicTTIImpl.h"
, 933, __PRETTY_FUNCTION__))
;
934
935 // Extract elements from loaded vector for each sub vector.
936 for (unsigned i = 0; i < NumSubElts; i++)
937 Cost += static_cast<T *>(this)->getVectorInstrCost(
938 Instruction::ExtractElement, VT, Index + i * Factor);
939 }
940
941 unsigned InsSubCost = 0;
942 for (unsigned i = 0; i < NumSubElts; i++)
943 InsSubCost += static_cast<T *>(this)->getVectorInstrCost(
944 Instruction::InsertElement, SubVT, i);
945
946 Cost += Indices.size() * InsSubCost;
947 } else {
948 // The interleave cost is extract all elements from sub vectors, and
949 // insert them into the wide vector.
950 //
951 // E.g. An interleaved store of factor 2:
952 // %v0_v1 = shuffle %v0, %v1, <0, 4, 1, 5, 2, 6, 3, 7>
953 // store <8 x i32> %interleaved.vec, <8 x i32>* %ptr
954 // The cost is estimated as extract all elements from both <4 x i32>
955 // vectors and insert into the <8 x i32> vector.
956
957 unsigned ExtSubCost = 0;
958 for (unsigned i = 0; i < NumSubElts; i++)
959 ExtSubCost += static_cast<T *>(this)->getVectorInstrCost(
960 Instruction::ExtractElement, SubVT, i);
961 Cost += ExtSubCost * Factor;
962
963 for (unsigned i = 0; i < NumElts; i++)
964 Cost += static_cast<T *>(this)
965 ->getVectorInstrCost(Instruction::InsertElement, VT, i);
966 }
967
968 if (!UseMaskForCond)
969 return Cost;
970
971 Type *I8Type = Type::getInt8Ty(VT->getContext());
972 VectorType *MaskVT = VectorType::get(I8Type, NumElts);
973 SubVT = VectorType::get(I8Type, NumSubElts);
974
975 // The Mask shuffling cost is extract all the elements of the Mask
976 // and insert each of them Factor times into the wide vector:
977 //
978 // E.g. an interleaved group with factor 3:
979 // %mask = icmp ult <8 x i32> %vec1, %vec2
980 // %interleaved.mask = shufflevector <8 x i1> %mask, <8 x i1> undef,
981 // <24 x i32> <0,0,0,1,1,1,2,2,2,3,3,3,4,4,4,5,5,5,6,6,6,7,7,7>
982 // The cost is estimated as extract all mask elements from the <8xi1> mask
983 // vector and insert them factor times into the <24xi1> shuffled mask
984 // vector.
985 for (unsigned i = 0; i < NumSubElts; i++)
986 Cost += static_cast<T *>(this)->getVectorInstrCost(
987 Instruction::ExtractElement, SubVT, i);
988
989 for (unsigned i = 0; i < NumElts; i++)
990 Cost += static_cast<T *>(this)->getVectorInstrCost(
991 Instruction::InsertElement, MaskVT, i);
992
993 // The Gaps mask is invariant and created outside the loop, therefore the
994 // cost of creating it is not accounted for here. However if we have both
995 // a MaskForGaps and some other mask that guards the execution of the
996 // memory access, we need to account for the cost of And-ing the two masks
997 // inside the loop.
998 if (UseMaskForGaps)
999 Cost += static_cast<T *>(this)->getArithmeticInstrCost(
1000 BinaryOperator::And, MaskVT);
1001
1002 return Cost;
1003 }
1004
1005 /// Get intrinsic cost based on arguments.
1006 unsigned getIntrinsicInstrCost(Intrinsic::ID IID, Type *RetTy,
1007 ArrayRef<Value *> Args, FastMathFlags FMF,
1008 unsigned VF = 1) {
1009 unsigned RetVF = (RetTy->isVectorTy() ? RetTy->getVectorNumElements() : 1);
1010 assert((RetVF == 1 || VF == 1) && "VF > 1 and RetVF is a vector type")(((RetVF == 1 || VF == 1) && "VF > 1 and RetVF is a vector type"
) ? static_cast<void> (0) : __assert_fail ("(RetVF == 1 || VF == 1) && \"VF > 1 and RetVF is a vector type\""
, "/build/llvm-toolchain-snapshot-8~svn350071/include/llvm/CodeGen/BasicTTIImpl.h"
, 1010, __PRETTY_FUNCTION__))
;
1011 auto *ConcreteTTI = static_cast<T *>(this);
1012
1013 switch (IID) {
1014 default: {
1015 // Assume that we need to scalarize this intrinsic.
1016 SmallVector<Type *, 4> Types;
1017 for (Value *Op : Args) {
1018 Type *OpTy = Op->getType();
1019 assert(VF == 1 || !OpTy->isVectorTy())((VF == 1 || !OpTy->isVectorTy()) ? static_cast<void>
(0) : __assert_fail ("VF == 1 || !OpTy->isVectorTy()", "/build/llvm-toolchain-snapshot-8~svn350071/include/llvm/CodeGen/BasicTTIImpl.h"
, 1019, __PRETTY_FUNCTION__))
;
1020 Types.push_back(VF == 1 ? OpTy : VectorType::get(OpTy, VF));
1021 }
1022
1023 if (VF > 1 && !RetTy->isVoidTy())
1024 RetTy = VectorType::get(RetTy, VF);
1025
1026 // Compute the scalarization overhead based on Args for a vector
1027 // intrinsic. A vectorizer will pass a scalar RetTy and VF > 1, while
1028 // CostModel will pass a vector RetTy and VF is 1.
1029 unsigned ScalarizationCost = std::numeric_limits<unsigned>::max();
1030 if (RetVF > 1 || VF > 1) {
1031 ScalarizationCost = 0;
1032 if (!RetTy->isVoidTy())
1033 ScalarizationCost += getScalarizationOverhead(RetTy, true, false);
1034 ScalarizationCost += getOperandsScalarizationOverhead(Args, VF);
1035 }
1036
1037 return ConcreteTTI->getIntrinsicInstrCost(IID, RetTy, Types, FMF,
1038 ScalarizationCost);
1039 }
1040 case Intrinsic::masked_scatter: {
1041 assert(VF == 1 && "Can't vectorize types here.")((VF == 1 && "Can't vectorize types here.") ? static_cast
<void> (0) : __assert_fail ("VF == 1 && \"Can't vectorize types here.\""
, "/build/llvm-toolchain-snapshot-8~svn350071/include/llvm/CodeGen/BasicTTIImpl.h"
, 1041, __PRETTY_FUNCTION__))
;
1042 Value *Mask = Args[3];
1043 bool VarMask = !isa<Constant>(Mask);
1044 unsigned Alignment = cast<ConstantInt>(Args[2])->getZExtValue();
1045 return ConcreteTTI->getGatherScatterOpCost(
1046 Instruction::Store, Args[0]->getType(), Args[1], VarMask, Alignment);
1047 }
1048 case Intrinsic::masked_gather: {
1049 assert(VF == 1 && "Can't vectorize types here.")((VF == 1 && "Can't vectorize types here.") ? static_cast
<void> (0) : __assert_fail ("VF == 1 && \"Can't vectorize types here.\""
, "/build/llvm-toolchain-snapshot-8~svn350071/include/llvm/CodeGen/BasicTTIImpl.h"
, 1049, __PRETTY_FUNCTION__))
;
1050 Value *Mask = Args[2];
1051 bool VarMask = !isa<Constant>(Mask);
1052 unsigned Alignment = cast<ConstantInt>(Args[1])->getZExtValue();
1053 return ConcreteTTI->getGatherScatterOpCost(Instruction::Load, RetTy,
1054 Args[0], VarMask, Alignment);
1055 }
1056 case Intrinsic::experimental_vector_reduce_add:
1057 case Intrinsic::experimental_vector_reduce_mul:
1058 case Intrinsic::experimental_vector_reduce_and:
1059 case Intrinsic::experimental_vector_reduce_or:
1060 case Intrinsic::experimental_vector_reduce_xor:
1061 case Intrinsic::experimental_vector_reduce_fadd:
1062 case Intrinsic::experimental_vector_reduce_fmul:
1063 case Intrinsic::experimental_vector_reduce_smax:
1064 case Intrinsic::experimental_vector_reduce_smin:
1065 case Intrinsic::experimental_vector_reduce_fmax:
1066 case Intrinsic::experimental_vector_reduce_fmin:
1067 case Intrinsic::experimental_vector_reduce_umax:
1068 case Intrinsic::experimental_vector_reduce_umin:
1069 return getIntrinsicInstrCost(IID, RetTy, Args[0]->getType(), FMF);
1070 case Intrinsic::fshl:
1071 case Intrinsic::fshr: {
1072 Value *X = Args[0];
1073 Value *Y = Args[1];
1074 Value *Z = Args[2];
1075 TTI::OperandValueProperties OpPropsX, OpPropsY, OpPropsZ, OpPropsBW;
1076 TTI::OperandValueKind OpKindX = TTI::getOperandInfo(X, OpPropsX);
1077 TTI::OperandValueKind OpKindY = TTI::getOperandInfo(Y, OpPropsY);
1078 TTI::OperandValueKind OpKindZ = TTI::getOperandInfo(Z, OpPropsZ);
1079 TTI::OperandValueKind OpKindBW = TTI::OK_UniformConstantValue;
1080 OpPropsBW = isPowerOf2_32(RetTy->getScalarSizeInBits()) ? TTI::OP_PowerOf2
1081 : TTI::OP_None;
1082 // fshl: (X << (Z % BW)) | (Y >> (BW - (Z % BW)))
1083 // fshr: (X << (BW - (Z % BW))) | (Y >> (Z % BW))
1084 unsigned Cost = 0;
1085 Cost += ConcreteTTI->getArithmeticInstrCost(BinaryOperator::Or, RetTy);
1086 Cost += ConcreteTTI->getArithmeticInstrCost(BinaryOperator::Sub, RetTy);
1087 Cost += ConcreteTTI->getArithmeticInstrCost(BinaryOperator::Shl, RetTy,
1088 OpKindX, OpKindZ, OpPropsX);
1089 Cost += ConcreteTTI->getArithmeticInstrCost(BinaryOperator::LShr, RetTy,
1090 OpKindY, OpKindZ, OpPropsY);
1091 // Non-constant shift amounts requires a modulo.
1092 if (OpKindZ != TTI::OK_UniformConstantValue &&
1093 OpKindZ != TTI::OK_NonUniformConstantValue)
1094 Cost += ConcreteTTI->getArithmeticInstrCost(BinaryOperator::URem, RetTy,
1095 OpKindZ, OpKindBW, OpPropsZ,
1096 OpPropsBW);
1097 // For non-rotates (X != Y) we must add shift-by-zero handling costs.
1098 if (X != Y) {
1099 Type *CondTy = Type::getInt1Ty(RetTy->getContext());
1100 if (RetVF > 1)
1101 CondTy = VectorType::get(CondTy, RetVF);
1102 Cost += ConcreteTTI->getCmpSelInstrCost(BinaryOperator::ICmp, RetTy,
1103 CondTy, nullptr);
1104 Cost += ConcreteTTI->getCmpSelInstrCost(BinaryOperator::Select, RetTy,
1105 CondTy, nullptr);
1106 }
1107 return Cost;
1108 }
1109 }
1110 }
1111
1112 /// Get intrinsic cost based on argument types.
1113 /// If ScalarizationCostPassed is std::numeric_limits<unsigned>::max(), the
1114 /// cost of scalarizing the arguments and the return value will be computed
1115 /// based on types.
1116 unsigned getIntrinsicInstrCost(
1117 Intrinsic::ID IID, Type *RetTy, ArrayRef<Type *> Tys, FastMathFlags FMF,
1118 unsigned ScalarizationCostPassed = std::numeric_limits<unsigned>::max()) {
1119 SmallVector<unsigned, 2> ISDs;
1120 unsigned SingleCallCost = 10; // Library call cost. Make it expensive.
1121 switch (IID) {
1122 default: {
1123 // Assume that we need to scalarize this intrinsic.
1124 unsigned ScalarizationCost = ScalarizationCostPassed;
1125 unsigned ScalarCalls = 1;
1126 Type *ScalarRetTy = RetTy;
1127 if (RetTy->isVectorTy()) {
1128 if (ScalarizationCostPassed == std::numeric_limits<unsigned>::max())
1129 ScalarizationCost = getScalarizationOverhead(RetTy, true, false);
1130 ScalarCalls = std::max(ScalarCalls, RetTy->getVectorNumElements());
1131 ScalarRetTy = RetTy->getScalarType();
1132 }
1133 SmallVector<Type *, 4> ScalarTys;
1134 for (unsigned i = 0, ie = Tys.size(); i != ie; ++i) {
1135 Type *Ty = Tys[i];
1136 if (Ty->isVectorTy()) {
1137 if (ScalarizationCostPassed == std::numeric_limits<unsigned>::max())
1138 ScalarizationCost += getScalarizationOverhead(Ty, false, true);
1139 ScalarCalls = std::max(ScalarCalls, Ty->getVectorNumElements());
1140 Ty = Ty->getScalarType();
1141 }
1142 ScalarTys.push_back(Ty);
1143 }
1144 if (ScalarCalls == 1)
1145 return 1; // Return cost of a scalar intrinsic. Assume it to be cheap.
1146
1147 unsigned ScalarCost = static_cast<T *>(this)->getIntrinsicInstrCost(
1148 IID, ScalarRetTy, ScalarTys, FMF);
1149
1150 return ScalarCalls * ScalarCost + ScalarizationCost;
1151 }
1152 // Look for intrinsics that can be lowered directly or turned into a scalar
1153 // intrinsic call.
1154 case Intrinsic::sqrt:
1155 ISDs.push_back(ISD::FSQRT);
1156 break;
1157 case Intrinsic::sin:
1158 ISDs.push_back(ISD::FSIN);
1159 break;
1160 case Intrinsic::cos:
1161 ISDs.push_back(ISD::FCOS);
1162 break;
1163 case Intrinsic::exp:
1164 ISDs.push_back(ISD::FEXP);
1165 break;
1166 case Intrinsic::exp2:
1167 ISDs.push_back(ISD::FEXP2);
1168 break;
1169 case Intrinsic::log:
1170 ISDs.push_back(ISD::FLOG);
1171 break;
1172 case Intrinsic::log10:
1173 ISDs.push_back(ISD::FLOG10);
1174 break;
1175 case Intrinsic::log2:
1176 ISDs.push_back(ISD::FLOG2);
1177 break;
1178 case Intrinsic::fabs:
1179 ISDs.push_back(ISD::FABS);
1180 break;
1181 case Intrinsic::canonicalize:
1182 ISDs.push_back(ISD::FCANONICALIZE);
1183 break;
1184 case Intrinsic::minnum:
1185 ISDs.push_back(ISD::FMINNUM);
1186 if (FMF.noNaNs())
1187 ISDs.push_back(ISD::FMINIMUM);
1188 break;
1189 case Intrinsic::maxnum:
1190 ISDs.push_back(ISD::FMAXNUM);
1191 if (FMF.noNaNs())
1192 ISDs.push_back(ISD::FMAXIMUM);
1193 break;
1194 case Intrinsic::copysign:
1195 ISDs.push_back(ISD::FCOPYSIGN);
1196 break;
1197 case Intrinsic::floor:
1198 ISDs.push_back(ISD::FFLOOR);
1199 break;
1200 case Intrinsic::ceil:
1201 ISDs.push_back(ISD::FCEIL);
1202 break;
1203 case Intrinsic::trunc:
1204 ISDs.push_back(ISD::FTRUNC);
1205 break;
1206 case Intrinsic::nearbyint:
1207 ISDs.push_back(ISD::FNEARBYINT);
1208 break;
1209 case Intrinsic::rint:
1210 ISDs.push_back(ISD::FRINT);
1211 break;
1212 case Intrinsic::round:
1213 ISDs.push_back(ISD::FROUND);
1214 break;
1215 case Intrinsic::pow:
1216 ISDs.push_back(ISD::FPOW);
1217 break;
1218 case Intrinsic::fma:
1219 ISDs.push_back(ISD::FMA);
1220 break;
1221 case Intrinsic::fmuladd:
1222 ISDs.push_back(ISD::FMA);
1223 break;
1224 // FIXME: We should return 0 whenever getIntrinsicCost == TCC_Free.
1225 case Intrinsic::lifetime_start:
1226 case Intrinsic::lifetime_end:
1227 case Intrinsic::sideeffect:
1228 return 0;
1229 case Intrinsic::masked_store:
1230 return static_cast<T *>(this)
1231 ->getMaskedMemoryOpCost(Instruction::Store, Tys[0], 0, 0);
1232 case Intrinsic::masked_load:
1233 return static_cast<T *>(this)
1234 ->getMaskedMemoryOpCost(Instruction::Load, RetTy, 0, 0);
1235 case Intrinsic::experimental_vector_reduce_add:
1236 return static_cast<T *>(this)->getArithmeticReductionCost(
1237 Instruction::Add, Tys[0], /*IsPairwiseForm=*/false);
1238 case Intrinsic::experimental_vector_reduce_mul:
1239 return static_cast<T *>(this)->getArithmeticReductionCost(
1240 Instruction::Mul, Tys[0], /*IsPairwiseForm=*/false);
1241 case Intrinsic::experimental_vector_reduce_and:
1242 return static_cast<T *>(this)->getArithmeticReductionCost(
1243 Instruction::And, Tys[0], /*IsPairwiseForm=*/false);
1244 case Intrinsic::experimental_vector_reduce_or:
1245 return static_cast<T *>(this)->getArithmeticReductionCost(
1246 Instruction::Or, Tys[0], /*IsPairwiseForm=*/false);
1247 case Intrinsic::experimental_vector_reduce_xor:
1248 return static_cast<T *>(this)->getArithmeticReductionCost(
1249 Instruction::Xor, Tys[0], /*IsPairwiseForm=*/false);
1250 case Intrinsic::experimental_vector_reduce_fadd:
1251 return static_cast<T *>(this)->getArithmeticReductionCost(
1252 Instruction::FAdd, Tys[0], /*IsPairwiseForm=*/false);
1253 case Intrinsic::experimental_vector_reduce_fmul:
1254 return static_cast<T *>(this)->getArithmeticReductionCost(
1255 Instruction::FMul, Tys[0], /*IsPairwiseForm=*/false);
1256 case Intrinsic::experimental_vector_reduce_smax:
1257 case Intrinsic::experimental_vector_reduce_smin:
1258 case Intrinsic::experimental_vector_reduce_fmax:
1259 case Intrinsic::experimental_vector_reduce_fmin:
1260 return static_cast<T *>(this)->getMinMaxReductionCost(
1261 Tys[0], CmpInst::makeCmpResultType(Tys[0]), /*IsPairwiseForm=*/false,
1262 /*IsSigned=*/true);
1263 case Intrinsic::experimental_vector_reduce_umax:
1264 case Intrinsic::experimental_vector_reduce_umin:
1265 return static_cast<T *>(this)->getMinMaxReductionCost(
1266 Tys[0], CmpInst::makeCmpResultType(Tys[0]), /*IsPairwiseForm=*/false,
1267 /*IsSigned=*/false);
1268 case Intrinsic::ctpop:
1269 ISDs.push_back(ISD::CTPOP);
1270 // In case of legalization use TCC_Expensive. This is cheaper than a
1271 // library call but still not a cheap instruction.
1272 SingleCallCost = TargetTransformInfo::TCC_Expensive;
1273 break;
1274 // FIXME: ctlz, cttz, ...
1275 }
1276
1277 const TargetLoweringBase *TLI = getTLI();
1278 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(DL, RetTy);
1279
1280 SmallVector<unsigned, 2> LegalCost;
1281 SmallVector<unsigned, 2> CustomCost;
1282 for (unsigned ISD : ISDs) {
1283 if (TLI->isOperationLegalOrPromote(ISD, LT.second)) {
1284 if (IID == Intrinsic::fabs && LT.second.isFloatingPoint() &&
1285 TLI->isFAbsFree(LT.second)) {
1286 return 0;
1287 }
1288
1289 // The operation is legal. Assume it costs 1.
1290 // If the type is split to multiple registers, assume that there is some
1291 // overhead to this.
1292 // TODO: Once we have extract/insert subvector cost we need to use them.
1293 if (LT.first > 1)
1294 LegalCost.push_back(LT.first * 2);
1295 else
1296 LegalCost.push_back(LT.first * 1);
1297 } else if (!TLI->isOperationExpand(ISD, LT.second)) {
1298 // If the operation is custom lowered then assume
1299 // that the code is twice as expensive.
1300 CustomCost.push_back(LT.first * 2);
1301 }
1302 }
1303
1304 auto MinLegalCostI = std::min_element(LegalCost.begin(), LegalCost.end());
1305 if (MinLegalCostI != LegalCost.end())
1306 return *MinLegalCostI;
1307
1308 auto MinCustomCostI = std::min_element(CustomCost.begin(), CustomCost.end());
1309 if (MinCustomCostI != CustomCost.end())
1310 return *MinCustomCostI;
1311
1312 // If we can't lower fmuladd into an FMA estimate the cost as a floating
1313 // point mul followed by an add.
1314 if (IID == Intrinsic::fmuladd)
1315 return static_cast<T *>(this)
1316 ->getArithmeticInstrCost(BinaryOperator::FMul, RetTy) +
1317 static_cast<T *>(this)
1318 ->getArithmeticInstrCost(BinaryOperator::FAdd, RetTy);
1319
1320 // Else, assume that we need to scalarize this intrinsic. For math builtins
1321 // this will emit a costly libcall, adding call overhead and spills. Make it
1322 // very expensive.
1323 if (RetTy->isVectorTy()) {
1324 unsigned ScalarizationCost =
1325 ((ScalarizationCostPassed != std::numeric_limits<unsigned>::max())
1326 ? ScalarizationCostPassed
1327 : getScalarizationOverhead(RetTy, true, false));
1328 unsigned ScalarCalls = RetTy->getVectorNumElements();
1329 SmallVector<Type *, 4> ScalarTys;
1330 for (unsigned i = 0, ie = Tys.size(); i != ie; ++i) {
1331 Type *Ty = Tys[i];
1332 if (Ty->isVectorTy())
1333 Ty = Ty->getScalarType();
1334 ScalarTys.push_back(Ty);
1335 }
1336 unsigned ScalarCost = static_cast<T *>(this)->getIntrinsicInstrCost(
1337 IID, RetTy->getScalarType(), ScalarTys, FMF);
1338 for (unsigned i = 0, ie = Tys.size(); i != ie; ++i) {
1339 if (Tys[i]->isVectorTy()) {
1340 if (ScalarizationCostPassed == std::numeric_limits<unsigned>::max())
1341 ScalarizationCost += getScalarizationOverhead(Tys[i], false, true);
1342 ScalarCalls = std::max(ScalarCalls, Tys[i]->getVectorNumElements());
1343 }
1344 }
1345
1346 return ScalarCalls * ScalarCost + ScalarizationCost;
1347 }
1348
1349 // This is going to be turned into a library call, make it expensive.
1350 return SingleCallCost;
1351 }
1352
1353 /// Compute a cost of the given call instruction.
1354 ///
1355 /// Compute the cost of calling function F with return type RetTy and
1356 /// argument types Tys. F might be nullptr, in this case the cost of an
1357 /// arbitrary call with the specified signature will be returned.
1358 /// This is used, for instance, when we estimate call of a vector
1359 /// counterpart of the given function.
1360 /// \param F Called function, might be nullptr.
1361 /// \param RetTy Return value types.
1362 /// \param Tys Argument types.
1363 /// \returns The cost of Call instruction.
1364 unsigned getCallInstrCost(Function *F, Type *RetTy, ArrayRef<Type *> Tys) {
1365 return 10;
1366 }
1367
1368 unsigned getNumberOfParts(Type *Tp) {
1369 std::pair<unsigned, MVT> LT = getTLI()->getTypeLegalizationCost(DL, Tp);
1370 return LT.first;
1371 }
1372
1373 unsigned getAddressComputationCost(Type *Ty, ScalarEvolution *,
1374 const SCEV *) {
1375 return 0;
1376 }
1377
1378 /// Try to calculate arithmetic and shuffle op costs for reduction operations.
1379 /// We're assuming that reduction operation are performing the following way:
1380 /// 1. Non-pairwise reduction
1381 /// %val1 = shufflevector<n x t> %val, <n x t> %undef,
1382 /// <n x i32> <i32 n/2, i32 n/2 + 1, ..., i32 n, i32 undef, ..., i32 undef>
1383 /// \----------------v-------------/ \----------v------------/
1384 /// n/2 elements n/2 elements
1385 /// %red1 = op <n x t> %val, <n x t> val1
1386 /// After this operation we have a vector %red1 where only the first n/2
1387 /// elements are meaningful, the second n/2 elements are undefined and can be
1388 /// dropped. All other operations are actually working with the vector of
1389 /// length n/2, not n, though the real vector length is still n.
1390 /// %val2 = shufflevector<n x t> %red1, <n x t> %undef,
1391 /// <n x i32> <i32 n/4, i32 n/4 + 1, ..., i32 n/2, i32 undef, ..., i32 undef>
1392 /// \----------------v-------------/ \----------v------------/
1393 /// n/4 elements 3*n/4 elements
1394 /// %red2 = op <n x t> %red1, <n x t> val2 - working with the vector of
1395 /// length n/2, the resulting vector has length n/4 etc.
1396 /// 2. Pairwise reduction:
1397 /// Everything is the same except for an additional shuffle operation which
1398 /// is used to produce operands for pairwise kind of reductions.
1399 /// %val1 = shufflevector<n x t> %val, <n x t> %undef,
1400 /// <n x i32> <i32 0, i32 2, ..., i32 n-2, i32 undef, ..., i32 undef>
1401 /// \-------------v----------/ \----------v------------/
1402 /// n/2 elements n/2 elements
1403 /// %val2 = shufflevector<n x t> %val, <n x t> %undef,
1404 /// <n x i32> <i32 1, i32 3, ..., i32 n-1, i32 undef, ..., i32 undef>
1405 /// \-------------v----------/ \----------v------------/
1406 /// n/2 elements n/2 elements
1407 /// %red1 = op <n x t> %val1, <n x t> val2
1408 /// Again, the operation is performed on <n x t> vector, but the resulting
1409 /// vector %red1 is <n/2 x t> vector.
1410 ///
1411 /// The cost model should take into account that the actual length of the
1412 /// vector is reduced on each iteration.
1413 unsigned getArithmeticReductionCost(unsigned Opcode, Type *Ty,
1414 bool IsPairwise) {
1415 assert(Ty->isVectorTy() && "Expect a vector type")((Ty->isVectorTy() && "Expect a vector type") ? static_cast
<void> (0) : __assert_fail ("Ty->isVectorTy() && \"Expect a vector type\""
, "/build/llvm-toolchain-snapshot-8~svn350071/include/llvm/CodeGen/BasicTTIImpl.h"
, 1415, __PRETTY_FUNCTION__))
;
1416 Type *ScalarTy = Ty->getVectorElementType();
1417 unsigned NumVecElts = Ty->getVectorNumElements();
1418 unsigned NumReduxLevels = Log2_32(NumVecElts);
1419 unsigned ArithCost = 0;
1420 unsigned ShuffleCost = 0;
1421 auto *ConcreteTTI = static_cast<T *>(this);
1422 std::pair<unsigned, MVT> LT =
1423 ConcreteTTI->getTLI()->getTypeLegalizationCost(DL, Ty);
1424 unsigned LongVectorCount = 0;
1425 unsigned MVTLen =
1426 LT.second.isVector() ? LT.second.getVectorNumElements() : 1;
1427 while (NumVecElts > MVTLen) {
1428 NumVecElts /= 2;
1429 Type *SubTy = VectorType::get(ScalarTy, NumVecElts);
1430 // Assume the pairwise shuffles add a cost.
1431 ShuffleCost += (IsPairwise + 1) *
1432 ConcreteTTI->getShuffleCost(TTI::SK_ExtractSubvector, Ty,
1433 NumVecElts, SubTy);
1434 ArithCost += ConcreteTTI->getArithmeticInstrCost(Opcode, SubTy);
1435 Ty = SubTy;
1436 ++LongVectorCount;
1437 }
1438
1439 NumReduxLevels -= LongVectorCount;
1440
1441 // The minimal length of the vector is limited by the real length of vector
1442 // operations performed on the current platform. That's why several final
1443 // reduction operations are performed on the vectors with the same
1444 // architecture-dependent length.
1445
1446 // Non pairwise reductions need one shuffle per reduction level. Pairwise
1447 // reductions need two shuffles on every level, but the last one. On that
1448 // level one of the shuffles is <0, u, u, ...> which is identity.
1449 unsigned NumShuffles = NumReduxLevels;
1450 if (IsPairwise && NumReduxLevels >= 1)
1451 NumShuffles += NumReduxLevels - 1;
1452 ShuffleCost += NumShuffles *
1453 ConcreteTTI->getShuffleCost(TTI::SK_PermuteSingleSrc, Ty,
1454 0, Ty);
1455 ArithCost += NumReduxLevels *
1456 ConcreteTTI->getArithmeticInstrCost(Opcode, Ty);
1457 return ShuffleCost + ArithCost +
1458 ConcreteTTI->getVectorInstrCost(Instruction::ExtractElement, Ty, 0);
1459 }
1460
1461 /// Try to calculate op costs for min/max reduction operations.
1462 /// \param CondTy Conditional type for the Select instruction.
1463 unsigned getMinMaxReductionCost(Type *Ty, Type *CondTy, bool IsPairwise,
1464 bool) {
1465 assert(Ty->isVectorTy() && "Expect a vector type")((Ty->isVectorTy() && "Expect a vector type") ? static_cast
<void> (0) : __assert_fail ("Ty->isVectorTy() && \"Expect a vector type\""
, "/build/llvm-toolchain-snapshot-8~svn350071/include/llvm/CodeGen/BasicTTIImpl.h"
, 1465, __PRETTY_FUNCTION__))
;
1466 Type *ScalarTy = Ty->getVectorElementType();
1467 Type *ScalarCondTy = CondTy->getVectorElementType();
1468 unsigned NumVecElts = Ty->getVectorNumElements();
1469 unsigned NumReduxLevels = Log2_32(NumVecElts);
1470 unsigned CmpOpcode;
1471 if (Ty->isFPOrFPVectorTy()) {
1472 CmpOpcode = Instruction::FCmp;
1473 } else {
1474 assert(Ty->isIntOrIntVectorTy() &&((Ty->isIntOrIntVectorTy() && "expecting floating point or integer type for min/max reduction"
) ? static_cast<void> (0) : __assert_fail ("Ty->isIntOrIntVectorTy() && \"expecting floating point or integer type for min/max reduction\""
, "/build/llvm-toolchain-snapshot-8~svn350071/include/llvm/CodeGen/BasicTTIImpl.h"
, 1475, __PRETTY_FUNCTION__))
1475 "expecting floating point or integer type for min/max reduction")((Ty->isIntOrIntVectorTy() && "expecting floating point or integer type for min/max reduction"
) ? static_cast<void> (0) : __assert_fail ("Ty->isIntOrIntVectorTy() && \"expecting floating point or integer type for min/max reduction\""
, "/build/llvm-toolchain-snapshot-8~svn350071/include/llvm/CodeGen/BasicTTIImpl.h"
, 1475, __PRETTY_FUNCTION__))
;
1476 CmpOpcode = Instruction::ICmp;
1477 }
1478 unsigned MinMaxCost = 0;
1479 unsigned ShuffleCost = 0;
1480 auto *ConcreteTTI = static_cast<T *>(this);
1481 std::pair<unsigned, MVT> LT =
1482 ConcreteTTI->getTLI()->getTypeLegalizationCost(DL, Ty);
1483 unsigned LongVectorCount = 0;
1484 unsigned MVTLen =
1485 LT.second.isVector() ? LT.second.getVectorNumElements() : 1;
1486 while (NumVecElts > MVTLen) {
1487 NumVecElts /= 2;
1488 Type *SubTy = VectorType::get(ScalarTy, NumVecElts);
1489 CondTy = VectorType::get(ScalarCondTy, NumVecElts);
1490
1491 // Assume the pairwise shuffles add a cost.
1492 ShuffleCost += (IsPairwise + 1) *
1493 ConcreteTTI->getShuffleCost(TTI::SK_ExtractSubvector, Ty,
1494 NumVecElts, SubTy);
1495 MinMaxCost +=
1496 ConcreteTTI->getCmpSelInstrCost(CmpOpcode, SubTy, CondTy, nullptr) +
1497 ConcreteTTI->getCmpSelInstrCost(Instruction::Select, SubTy, CondTy,
1498 nullptr);
1499 Ty = SubTy;
1500 ++LongVectorCount;
1501 }
1502
1503 NumReduxLevels -= LongVectorCount;
1504
1505 // The minimal length of the vector is limited by the real length of vector
1506 // operations performed on the current platform. That's why several final
1507 // reduction opertions are perfomed on the vectors with the same
1508 // architecture-dependent length.
1509
1510 // Non pairwise reductions need one shuffle per reduction level. Pairwise
1511 // reductions need two shuffles on every level, but the last one. On that
1512 // level one of the shuffles is <0, u, u, ...> which is identity.
1513 unsigned NumShuffles = NumReduxLevels;
1514 if (IsPairwise && NumReduxLevels >= 1)
1515 NumShuffles += NumReduxLevels - 1;
1516 ShuffleCost += NumShuffles *
1517 ConcreteTTI->getShuffleCost(TTI::SK_PermuteSingleSrc, Ty,
1518 0, Ty);
1519 MinMaxCost +=
1520 NumReduxLevels *
1521 (ConcreteTTI->getCmpSelInstrCost(CmpOpcode, Ty, CondTy, nullptr) +
1522 ConcreteTTI->getCmpSelInstrCost(Instruction::Select, Ty, CondTy,
1523 nullptr));
1524 // The last min/max should be in vector registers and we counted it above.
1525 // So just need a single extractelement.
1526 return ShuffleCost + MinMaxCost +
1527 ConcreteTTI->getVectorInstrCost(Instruction::ExtractElement, Ty, 0);
1528 }
1529
1530 unsigned getVectorSplitCost() { return 1; }
1531
1532 /// @}
1533};
1534
1535/// Concrete BasicTTIImpl that can be used if no further customization
1536/// is needed.
1537class BasicTTIImpl : public BasicTTIImplBase<BasicTTIImpl> {
1538 using BaseT = BasicTTIImplBase<BasicTTIImpl>;
1539
1540 friend class BasicTTIImplBase<BasicTTIImpl>;
1541
1542 const TargetSubtargetInfo *ST;
1543 const TargetLoweringBase *TLI;
1544
1545 const TargetSubtargetInfo *getST() const { return ST; }
1546 const TargetLoweringBase *getTLI() const { return TLI; }
1547
1548public:
1549 explicit BasicTTIImpl(const TargetMachine *TM, const Function &F);
1550};
1551
1552} // end namespace llvm
1553
1554#endif // LLVM_CODEGEN_BASICTTIIMPL_H