Bug Summary

File:lib/Target/X86/X86TargetTransformInfo.cpp
Warning:line 77, column 25
Called C++ object pointer is null

Annotated Source Code

/build/llvm-toolchain-snapshot-6.0~svn318211/lib/Target/X86/X86TargetTransformInfo.cpp

1//===-- X86TargetTransformInfo.cpp - X86 specific TTI pass ----------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9/// \file
10/// This file implements a TargetTransformInfo analysis pass specific to the
11/// X86 target machine. It uses the target's detailed information to provide
12/// more precise answers to certain TTI queries, while letting the target
13/// independent and default TTI implementations handle the rest.
14///
15//===----------------------------------------------------------------------===//
16/// About Cost Model numbers used below it's necessary to say the following:
17/// the numbers correspond to some "generic" X86 CPU instead of usage of
18/// concrete CPU model. Usually the numbers correspond to CPU where the feature
19/// apeared at the first time. For example, if we do Subtarget.hasSSE42() in
20/// the lookups below the cost is based on Nehalem as that was the first CPU
21/// to support that feature level and thus has most likely the worst case cost.
22/// Some examples of other technologies/CPUs:
23/// SSE 3 - Pentium4 / Athlon64
24/// SSE 4.1 - Penryn
25/// SSE 4.2 - Nehalem
26/// AVX - Sandy Bridge
27/// AVX2 - Haswell
28/// AVX-512 - Xeon Phi / Skylake
29/// And some examples of instruction target dependent costs (latency)
30/// divss sqrtss rsqrtss
31/// AMD K7 11-16 19 3
32/// Piledriver 9-24 13-15 5
33/// Jaguar 14 16 2
34/// Pentium II,III 18 30 2
35/// Nehalem 7-14 7-18 3
36/// Haswell 10-13 11 5
37/// TODO: Develop and implement the target dependent cost model and
38/// specialize cost numbers for different Cost Model Targets such as throughput,
39/// code size, latency and uop count.
40//===----------------------------------------------------------------------===//
41
42#include "X86TargetTransformInfo.h"
43#include "llvm/Analysis/TargetTransformInfo.h"
44#include "llvm/CodeGen/BasicTTIImpl.h"
45#include "llvm/IR/IntrinsicInst.h"
46#include "llvm/Support/Debug.h"
47#include "llvm/Target/CostTable.h"
48#include "llvm/Target/TargetLowering.h"
49
50using namespace llvm;
51
52#define DEBUG_TYPE"x86tti" "x86tti"
53
54//===----------------------------------------------------------------------===//
55//
56// X86 cost model.
57//
58//===----------------------------------------------------------------------===//
59
60TargetTransformInfo::PopcntSupportKind
61X86TTIImpl::getPopcntSupport(unsigned TyWidth) {
62 assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2")((isPowerOf2_32(TyWidth) && "Ty width must be power of 2"
) ? static_cast<void> (0) : __assert_fail ("isPowerOf2_32(TyWidth) && \"Ty width must be power of 2\""
, "/build/llvm-toolchain-snapshot-6.0~svn318211/lib/Target/X86/X86TargetTransformInfo.cpp"
, 62, __PRETTY_FUNCTION__))
;
63 // TODO: Currently the __builtin_popcount() implementation using SSE3
64 // instructions is inefficient. Once the problem is fixed, we should
65 // call ST->hasSSE3() instead of ST->hasPOPCNT().
66 return ST->hasPOPCNT() ? TTI::PSK_FastHardware : TTI::PSK_Software;
67}
68
69llvm::Optional<unsigned> X86TTIImpl::getCacheSize(
70 TargetTransformInfo::CacheLevel Level) const {
71 switch (Level) {
72 case TargetTransformInfo::CacheLevel::L1D:
73 // - Penry
74 // - Nehalem
75 // - Westmere
76 // - Sandy Bridge
77 // - Ivy Bridge
78 // - Haswell
79 // - Broadwell
80 // - Skylake
81 // - Kabylake
82 return 32 * 1024; // 32 KByte
83 case TargetTransformInfo::CacheLevel::L2D:
84 // - Penry
85 // - Nehalem
86 // - Westmere
87 // - Sandy Bridge
88 // - Ivy Bridge
89 // - Haswell
90 // - Broadwell
91 // - Skylake
92 // - Kabylake
93 return 256 * 1024; // 256 KByte
94 }
95
96 llvm_unreachable("Unknown TargetTransformInfo::CacheLevel")::llvm::llvm_unreachable_internal("Unknown TargetTransformInfo::CacheLevel"
, "/build/llvm-toolchain-snapshot-6.0~svn318211/lib/Target/X86/X86TargetTransformInfo.cpp"
, 96)
;
97}
98
99llvm::Optional<unsigned> X86TTIImpl::getCacheAssociativity(
100 TargetTransformInfo::CacheLevel Level) const {
101 // - Penry
102 // - Nehalem
103 // - Westmere
104 // - Sandy Bridge
105 // - Ivy Bridge
106 // - Haswell
107 // - Broadwell
108 // - Skylake
109 // - Kabylake
110 switch (Level) {
111 case TargetTransformInfo::CacheLevel::L1D:
112 LLVM_FALLTHROUGH[[clang::fallthrough]];
113 case TargetTransformInfo::CacheLevel::L2D:
114 return 8;
115 }
116
117 llvm_unreachable("Unknown TargetTransformInfo::CacheLevel")::llvm::llvm_unreachable_internal("Unknown TargetTransformInfo::CacheLevel"
, "/build/llvm-toolchain-snapshot-6.0~svn318211/lib/Target/X86/X86TargetTransformInfo.cpp"
, 117)
;
118}
119
120unsigned X86TTIImpl::getNumberOfRegisters(bool Vector) {
121 if (Vector && !ST->hasSSE1())
122 return 0;
123
124 if (ST->is64Bit()) {
125 if (Vector && ST->hasAVX512())
126 return 32;
127 return 16;
128 }
129 return 8;
130}
131
132unsigned X86TTIImpl::getRegisterBitWidth(bool Vector) const {
133 if (Vector) {
134 if (ST->hasAVX512())
135 return 512;
136 if (ST->hasAVX())
137 return 256;
138 if (ST->hasSSE1())
139 return 128;
140 return 0;
141 }
142
143 if (ST->is64Bit())
144 return 64;
145
146 return 32;
147}
148
149unsigned X86TTIImpl::getLoadStoreVecRegBitWidth(unsigned) const {
150 return getRegisterBitWidth(true);
151}
152
153unsigned X86TTIImpl::getMaxInterleaveFactor(unsigned VF) {
154 // If the loop will not be vectorized, don't interleave the loop.
155 // Let regular unroll to unroll the loop, which saves the overflow
156 // check and memory check cost.
157 if (VF == 1)
158 return 1;
159
160 if (ST->isAtom())
161 return 1;
162
163 // Sandybridge and Haswell have multiple execution ports and pipelined
164 // vector units.
165 if (ST->hasAVX())
166 return 4;
167
168 return 2;
169}
170
171int X86TTIImpl::getArithmeticInstrCost(
172 unsigned Opcode, Type *Ty,
173 TTI::OperandValueKind Op1Info, TTI::OperandValueKind Op2Info,
174 TTI::OperandValueProperties Opd1PropInfo,
175 TTI::OperandValueProperties Opd2PropInfo,
176 ArrayRef<const Value *> Args) {
177 // Legalize the type.
178 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty);
179
180 int ISD = TLI->InstructionOpcodeToISD(Opcode);
181 assert(ISD && "Invalid opcode")((ISD && "Invalid opcode") ? static_cast<void> (
0) : __assert_fail ("ISD && \"Invalid opcode\"", "/build/llvm-toolchain-snapshot-6.0~svn318211/lib/Target/X86/X86TargetTransformInfo.cpp"
, 181, __PRETTY_FUNCTION__))
;
182
183 static const CostTblEntry SLMCostTable[] = {
184 { ISD::MUL, MVT::v4i32, 11 }, // pmulld
185 { ISD::MUL, MVT::v8i16, 2 }, // pmullw
186 { ISD::MUL, MVT::v16i8, 14 }, // extend/pmullw/trunc sequence.
187 { ISD::FMUL, MVT::f64, 2 }, // mulsd
188 { ISD::FMUL, MVT::v2f64, 4 }, // mulpd
189 { ISD::FMUL, MVT::v4f32, 2 }, // mulps
190 { ISD::FDIV, MVT::f32, 17 }, // divss
191 { ISD::FDIV, MVT::v4f32, 39 }, // divps
192 { ISD::FDIV, MVT::f64, 32 }, // divsd
193 { ISD::FDIV, MVT::v2f64, 69 }, // divpd
194 { ISD::FADD, MVT::v2f64, 2 }, // addpd
195 { ISD::FSUB, MVT::v2f64, 2 }, // subpd
196 // v2i64/v4i64 mul is custom lowered as a series of long:
197 // multiplies(3), shifts(3) and adds(2)
198 // slm muldq version throughput is 2 and addq throughput 4
199 // thus: 3X2 (muldq throughput) + 3X1 (shift throuput) +
200 // 3X4 (addq throughput) = 17
201 { ISD::MUL, MVT::v2i64, 17 },
202 // slm addq\subq throughput is 4
203 { ISD::ADD, MVT::v2i64, 4 },
204 { ISD::SUB, MVT::v2i64, 4 },
205 };
206
207 if (ST->isSLM()) {
208 if (Args.size() == 2 && ISD == ISD::MUL && LT.second == MVT::v4i32) {
209 // Check if the operands can be shrinked into a smaller datatype.
210 bool Op1Signed = false;
211 unsigned Op1MinSize = BaseT::minRequiredElementSize(Args[0], Op1Signed);
212 bool Op2Signed = false;
213 unsigned Op2MinSize = BaseT::minRequiredElementSize(Args[1], Op2Signed);
214
215 bool signedMode = Op1Signed | Op2Signed;
216 unsigned OpMinSize = std::max(Op1MinSize, Op2MinSize);
217
218 if (OpMinSize <= 7)
219 return LT.first * 3; // pmullw/sext
220 if (!signedMode && OpMinSize <= 8)
221 return LT.first * 3; // pmullw/zext
222 if (OpMinSize <= 15)
223 return LT.first * 5; // pmullw/pmulhw/pshuf
224 if (!signedMode && OpMinSize <= 16)
225 return LT.first * 5; // pmullw/pmulhw/pshuf
226 }
227 if (const auto *Entry = CostTableLookup(SLMCostTable, ISD,
228 LT.second)) {
229 return LT.first * Entry->Cost;
230 }
231 }
232
233 if (ISD == ISD::SDIV &&
234 Op2Info == TargetTransformInfo::OK_UniformConstantValue &&
235 Opd2PropInfo == TargetTransformInfo::OP_PowerOf2) {
236 // On X86, vector signed division by constants power-of-two are
237 // normally expanded to the sequence SRA + SRL + ADD + SRA.
238 // The OperandValue properties many not be same as that of previous
239 // operation;conservatively assume OP_None.
240 int Cost = 2 * getArithmeticInstrCost(Instruction::AShr, Ty, Op1Info,
241 Op2Info, TargetTransformInfo::OP_None,
242 TargetTransformInfo::OP_None);
243 Cost += getArithmeticInstrCost(Instruction::LShr, Ty, Op1Info, Op2Info,
244 TargetTransformInfo::OP_None,
245 TargetTransformInfo::OP_None);
246 Cost += getArithmeticInstrCost(Instruction::Add, Ty, Op1Info, Op2Info,
247 TargetTransformInfo::OP_None,
248 TargetTransformInfo::OP_None);
249
250 return Cost;
251 }
252
253 static const CostTblEntry AVX512BWUniformConstCostTable[] = {
254 { ISD::SHL, MVT::v64i8, 2 }, // psllw + pand.
255 { ISD::SRL, MVT::v64i8, 2 }, // psrlw + pand.
256 { ISD::SRA, MVT::v64i8, 4 }, // psrlw, pand, pxor, psubb.
257
258 { ISD::SDIV, MVT::v32i16, 6 }, // vpmulhw sequence
259 { ISD::UDIV, MVT::v32i16, 6 }, // vpmulhuw sequence
260 };
261
262 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue &&
263 ST->hasBWI()) {
264 if (const auto *Entry = CostTableLookup(AVX512BWUniformConstCostTable, ISD,
265 LT.second))
266 return LT.first * Entry->Cost;
267 }
268
269 static const CostTblEntry AVX512UniformConstCostTable[] = {
270 { ISD::SRA, MVT::v2i64, 1 },
271 { ISD::SRA, MVT::v4i64, 1 },
272 { ISD::SRA, MVT::v8i64, 1 },
273
274 { ISD::SDIV, MVT::v16i32, 15 }, // vpmuldq sequence
275 { ISD::UDIV, MVT::v16i32, 15 }, // vpmuludq sequence
276 };
277
278 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue &&
279 ST->hasAVX512()) {
280 if (const auto *Entry = CostTableLookup(AVX512UniformConstCostTable, ISD,
281 LT.second))
282 return LT.first * Entry->Cost;
283 }
284
285 static const CostTblEntry AVX2UniformConstCostTable[] = {
286 { ISD::SHL, MVT::v32i8, 2 }, // psllw + pand.
287 { ISD::SRL, MVT::v32i8, 2 }, // psrlw + pand.
288 { ISD::SRA, MVT::v32i8, 4 }, // psrlw, pand, pxor, psubb.
289
290 { ISD::SRA, MVT::v4i64, 4 }, // 2 x psrad + shuffle.
291
292 { ISD::SDIV, MVT::v16i16, 6 }, // vpmulhw sequence
293 { ISD::UDIV, MVT::v16i16, 6 }, // vpmulhuw sequence
294 { ISD::SDIV, MVT::v8i32, 15 }, // vpmuldq sequence
295 { ISD::UDIV, MVT::v8i32, 15 }, // vpmuludq sequence
296 };
297
298 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue &&
299 ST->hasAVX2()) {
300 if (const auto *Entry = CostTableLookup(AVX2UniformConstCostTable, ISD,
301 LT.second))
302 return LT.first * Entry->Cost;
303 }
304
305 static const CostTblEntry SSE2UniformConstCostTable[] = {
306 { ISD::SHL, MVT::v16i8, 2 }, // psllw + pand.
307 { ISD::SRL, MVT::v16i8, 2 }, // psrlw + pand.
308 { ISD::SRA, MVT::v16i8, 4 }, // psrlw, pand, pxor, psubb.
309
310 { ISD::SHL, MVT::v32i8, 4+2 }, // 2*(psllw + pand) + split.
311 { ISD::SRL, MVT::v32i8, 4+2 }, // 2*(psrlw + pand) + split.
312 { ISD::SRA, MVT::v32i8, 8+2 }, // 2*(psrlw, pand, pxor, psubb) + split.
313
314 { ISD::SDIV, MVT::v16i16, 12+2 }, // 2*pmulhw sequence + split.
315 { ISD::SDIV, MVT::v8i16, 6 }, // pmulhw sequence
316 { ISD::UDIV, MVT::v16i16, 12+2 }, // 2*pmulhuw sequence + split.
317 { ISD::UDIV, MVT::v8i16, 6 }, // pmulhuw sequence
318 { ISD::SDIV, MVT::v8i32, 38+2 }, // 2*pmuludq sequence + split.
319 { ISD::SDIV, MVT::v4i32, 19 }, // pmuludq sequence
320 { ISD::UDIV, MVT::v8i32, 30+2 }, // 2*pmuludq sequence + split.
321 { ISD::UDIV, MVT::v4i32, 15 }, // pmuludq sequence
322 };
323
324 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue &&
325 ST->hasSSE2()) {
326 // pmuldq sequence.
327 if (ISD == ISD::SDIV && LT.second == MVT::v8i32 && ST->hasAVX())
328 return LT.first * 32;
329 if (ISD == ISD::SDIV && LT.second == MVT::v4i32 && ST->hasSSE41())
330 return LT.first * 15;
331
332 // XOP has faster vXi8 shifts.
333 if ((ISD != ISD::SHL && ISD != ISD::SRL && ISD != ISD::SRA) ||
334 !ST->hasXOP())
335 if (const auto *Entry =
336 CostTableLookup(SSE2UniformConstCostTable, ISD, LT.second))
337 return LT.first * Entry->Cost;
338 }
339
340 static const CostTblEntry AVX2UniformCostTable[] = {
341 // Uniform splats are cheaper for the following instructions.
342 { ISD::SHL, MVT::v16i16, 1 }, // psllw.
343 { ISD::SRL, MVT::v16i16, 1 }, // psrlw.
344 { ISD::SRA, MVT::v16i16, 1 }, // psraw.
345 };
346
347 if (ST->hasAVX2() &&
348 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) ||
349 (Op2Info == TargetTransformInfo::OK_UniformValue))) {
350 if (const auto *Entry =
351 CostTableLookup(AVX2UniformCostTable, ISD, LT.second))
352 return LT.first * Entry->Cost;
353 }
354
355 static const CostTblEntry SSE2UniformCostTable[] = {
356 // Uniform splats are cheaper for the following instructions.
357 { ISD::SHL, MVT::v8i16, 1 }, // psllw.
358 { ISD::SHL, MVT::v4i32, 1 }, // pslld
359 { ISD::SHL, MVT::v2i64, 1 }, // psllq.
360
361 { ISD::SRL, MVT::v8i16, 1 }, // psrlw.
362 { ISD::SRL, MVT::v4i32, 1 }, // psrld.
363 { ISD::SRL, MVT::v2i64, 1 }, // psrlq.
364
365 { ISD::SRA, MVT::v8i16, 1 }, // psraw.
366 { ISD::SRA, MVT::v4i32, 1 }, // psrad.
367 };
368
369 if (ST->hasSSE2() &&
370 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) ||
371 (Op2Info == TargetTransformInfo::OK_UniformValue))) {
372 if (const auto *Entry =
373 CostTableLookup(SSE2UniformCostTable, ISD, LT.second))
374 return LT.first * Entry->Cost;
375 }
376
377 static const CostTblEntry AVX512DQCostTable[] = {
378 { ISD::MUL, MVT::v2i64, 1 },
379 { ISD::MUL, MVT::v4i64, 1 },
380 { ISD::MUL, MVT::v8i64, 1 }
381 };
382
383 // Look for AVX512DQ lowering tricks for custom cases.
384 if (ST->hasDQI())
385 if (const auto *Entry = CostTableLookup(AVX512DQCostTable, ISD, LT.second))
386 return LT.first * Entry->Cost;
387
388 static const CostTblEntry AVX512BWCostTable[] = {
389 { ISD::SHL, MVT::v8i16, 1 }, // vpsllvw
390 { ISD::SRL, MVT::v8i16, 1 }, // vpsrlvw
391 { ISD::SRA, MVT::v8i16, 1 }, // vpsravw
392
393 { ISD::SHL, MVT::v16i16, 1 }, // vpsllvw
394 { ISD::SRL, MVT::v16i16, 1 }, // vpsrlvw
395 { ISD::SRA, MVT::v16i16, 1 }, // vpsravw
396
397 { ISD::SHL, MVT::v32i16, 1 }, // vpsllvw
398 { ISD::SRL, MVT::v32i16, 1 }, // vpsrlvw
399 { ISD::SRA, MVT::v32i16, 1 }, // vpsravw
400
401 { ISD::SHL, MVT::v64i8, 11 }, // vpblendvb sequence.
402 { ISD::SRL, MVT::v64i8, 11 }, // vpblendvb sequence.
403 { ISD::SRA, MVT::v64i8, 24 }, // vpblendvb sequence.
404
405 { ISD::MUL, MVT::v64i8, 11 }, // extend/pmullw/trunc sequence.
406 { ISD::MUL, MVT::v32i8, 4 }, // extend/pmullw/trunc sequence.
407 { ISD::MUL, MVT::v16i8, 4 }, // extend/pmullw/trunc sequence.
408
409 // Vectorizing division is a bad idea. See the SSE2 table for more comments.
410 { ISD::SDIV, MVT::v64i8, 64*20 },
411 { ISD::SDIV, MVT::v32i16, 32*20 },
412 { ISD::UDIV, MVT::v64i8, 64*20 },
413 { ISD::UDIV, MVT::v32i16, 32*20 }
414 };
415
416 // Look for AVX512BW lowering tricks for custom cases.
417 if (ST->hasBWI())
418 if (const auto *Entry = CostTableLookup(AVX512BWCostTable, ISD, LT.second))
419 return LT.first * Entry->Cost;
420
421 static const CostTblEntry AVX512CostTable[] = {
422 { ISD::SHL, MVT::v16i32, 1 },
423 { ISD::SRL, MVT::v16i32, 1 },
424 { ISD::SRA, MVT::v16i32, 1 },
425
426 { ISD::SHL, MVT::v8i64, 1 },
427 { ISD::SRL, MVT::v8i64, 1 },
428
429 { ISD::SRA, MVT::v2i64, 1 },
430 { ISD::SRA, MVT::v4i64, 1 },
431 { ISD::SRA, MVT::v8i64, 1 },
432
433 { ISD::MUL, MVT::v32i8, 13 }, // extend/pmullw/trunc sequence.
434 { ISD::MUL, MVT::v16i8, 5 }, // extend/pmullw/trunc sequence.
435 { ISD::MUL, MVT::v16i32, 1 }, // pmulld
436 { ISD::MUL, MVT::v8i64, 8 }, // 3*pmuludq/3*shift/2*add
437
438 // Vectorizing division is a bad idea. See the SSE2 table for more comments.
439 { ISD::SDIV, MVT::v16i32, 16*20 },
440 { ISD::SDIV, MVT::v8i64, 8*20 },
441 { ISD::UDIV, MVT::v16i32, 16*20 },
442 { ISD::UDIV, MVT::v8i64, 8*20 }
443 };
444
445 if (ST->hasAVX512())
446 if (const auto *Entry = CostTableLookup(AVX512CostTable, ISD, LT.second))
447 return LT.first * Entry->Cost;
448
449 static const CostTblEntry AVX2ShiftCostTable[] = {
450 // Shifts on v4i64/v8i32 on AVX2 is legal even though we declare to
451 // customize them to detect the cases where shift amount is a scalar one.
452 { ISD::SHL, MVT::v4i32, 1 },
453 { ISD::SRL, MVT::v4i32, 1 },
454 { ISD::SRA, MVT::v4i32, 1 },
455 { ISD::SHL, MVT::v8i32, 1 },
456 { ISD::SRL, MVT::v8i32, 1 },
457 { ISD::SRA, MVT::v8i32, 1 },
458 { ISD::SHL, MVT::v2i64, 1 },
459 { ISD::SRL, MVT::v2i64, 1 },
460 { ISD::SHL, MVT::v4i64, 1 },
461 { ISD::SRL, MVT::v4i64, 1 },
462 };
463
464 // Look for AVX2 lowering tricks.
465 if (ST->hasAVX2()) {
466 if (ISD == ISD::SHL && LT.second == MVT::v16i16 &&
467 (Op2Info == TargetTransformInfo::OK_UniformConstantValue ||
468 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue))
469 // On AVX2, a packed v16i16 shift left by a constant build_vector
470 // is lowered into a vector multiply (vpmullw).
471 return LT.first;
472
473 if (const auto *Entry = CostTableLookup(AVX2ShiftCostTable, ISD, LT.second))
474 return LT.first * Entry->Cost;
475 }
476
477 static const CostTblEntry XOPShiftCostTable[] = {
478 // 128bit shifts take 1cy, but right shifts require negation beforehand.
479 { ISD::SHL, MVT::v16i8, 1 },
480 { ISD::SRL, MVT::v16i8, 2 },
481 { ISD::SRA, MVT::v16i8, 2 },
482 { ISD::SHL, MVT::v8i16, 1 },
483 { ISD::SRL, MVT::v8i16, 2 },
484 { ISD::SRA, MVT::v8i16, 2 },
485 { ISD::SHL, MVT::v4i32, 1 },
486 { ISD::SRL, MVT::v4i32, 2 },
487 { ISD::SRA, MVT::v4i32, 2 },
488 { ISD::SHL, MVT::v2i64, 1 },
489 { ISD::SRL, MVT::v2i64, 2 },
490 { ISD::SRA, MVT::v2i64, 2 },
491 // 256bit shifts require splitting if AVX2 didn't catch them above.
492 { ISD::SHL, MVT::v32i8, 2+2 },
493 { ISD::SRL, MVT::v32i8, 4+2 },
494 { ISD::SRA, MVT::v32i8, 4+2 },
495 { ISD::SHL, MVT::v16i16, 2+2 },
496 { ISD::SRL, MVT::v16i16, 4+2 },
497 { ISD::SRA, MVT::v16i16, 4+2 },
498 { ISD::SHL, MVT::v8i32, 2+2 },
499 { ISD::SRL, MVT::v8i32, 4+2 },
500 { ISD::SRA, MVT::v8i32, 4+2 },
501 { ISD::SHL, MVT::v4i64, 2+2 },
502 { ISD::SRL, MVT::v4i64, 4+2 },
503 { ISD::SRA, MVT::v4i64, 4+2 },
504 };
505
506 // Look for XOP lowering tricks.
507 if (ST->hasXOP())
508 if (const auto *Entry = CostTableLookup(XOPShiftCostTable, ISD, LT.second))
509 return LT.first * Entry->Cost;
510
511 static const CostTblEntry SSE2UniformShiftCostTable[] = {
512 // Uniform splats are cheaper for the following instructions.
513 { ISD::SHL, MVT::v16i16, 2+2 }, // 2*psllw + split.
514 { ISD::SHL, MVT::v8i32, 2+2 }, // 2*pslld + split.
515 { ISD::SHL, MVT::v4i64, 2+2 }, // 2*psllq + split.
516
517 { ISD::SRL, MVT::v16i16, 2+2 }, // 2*psrlw + split.
518 { ISD::SRL, MVT::v8i32, 2+2 }, // 2*psrld + split.
519 { ISD::SRL, MVT::v4i64, 2+2 }, // 2*psrlq + split.
520
521 { ISD::SRA, MVT::v16i16, 2+2 }, // 2*psraw + split.
522 { ISD::SRA, MVT::v8i32, 2+2 }, // 2*psrad + split.
523 { ISD::SRA, MVT::v2i64, 4 }, // 2*psrad + shuffle.
524 { ISD::SRA, MVT::v4i64, 8+2 }, // 2*(2*psrad + shuffle) + split.
525 };
526
527 if (ST->hasSSE2() &&
528 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) ||
529 (Op2Info == TargetTransformInfo::OK_UniformValue))) {
530
531 // Handle AVX2 uniform v4i64 ISD::SRA, it's not worth a table.
532 if (ISD == ISD::SRA && LT.second == MVT::v4i64 && ST->hasAVX2())
533 return LT.first * 4; // 2*psrad + shuffle.
534
535 if (const auto *Entry =
536 CostTableLookup(SSE2UniformShiftCostTable, ISD, LT.second))
537 return LT.first * Entry->Cost;
538 }
539
540 if (ISD == ISD::SHL &&
541 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) {
542 MVT VT = LT.second;
543 // Vector shift left by non uniform constant can be lowered
544 // into vector multiply.
545 if (((VT == MVT::v8i16 || VT == MVT::v4i32) && ST->hasSSE2()) ||
546 ((VT == MVT::v16i16 || VT == MVT::v8i32) && ST->hasAVX()))
547 ISD = ISD::MUL;
548 }
549
550 static const CostTblEntry AVX2CostTable[] = {
551 { ISD::SHL, MVT::v32i8, 11 }, // vpblendvb sequence.
552 { ISD::SHL, MVT::v16i16, 10 }, // extend/vpsrlvd/pack sequence.
553
554 { ISD::SRL, MVT::v32i8, 11 }, // vpblendvb sequence.
555 { ISD::SRL, MVT::v16i16, 10 }, // extend/vpsrlvd/pack sequence.
556
557 { ISD::SRA, MVT::v32i8, 24 }, // vpblendvb sequence.
558 { ISD::SRA, MVT::v16i16, 10 }, // extend/vpsravd/pack sequence.
559 { ISD::SRA, MVT::v2i64, 4 }, // srl/xor/sub sequence.
560 { ISD::SRA, MVT::v4i64, 4 }, // srl/xor/sub sequence.
561
562 { ISD::SUB, MVT::v32i8, 1 }, // psubb
563 { ISD::ADD, MVT::v32i8, 1 }, // paddb
564 { ISD::SUB, MVT::v16i16, 1 }, // psubw
565 { ISD::ADD, MVT::v16i16, 1 }, // paddw
566 { ISD::SUB, MVT::v8i32, 1 }, // psubd
567 { ISD::ADD, MVT::v8i32, 1 }, // paddd
568 { ISD::SUB, MVT::v4i64, 1 }, // psubq
569 { ISD::ADD, MVT::v4i64, 1 }, // paddq
570
571 { ISD::MUL, MVT::v32i8, 17 }, // extend/pmullw/trunc sequence.
572 { ISD::MUL, MVT::v16i8, 7 }, // extend/pmullw/trunc sequence.
573 { ISD::MUL, MVT::v16i16, 1 }, // pmullw
574 { ISD::MUL, MVT::v8i32, 1 }, // pmulld
575 { ISD::MUL, MVT::v4i64, 8 }, // 3*pmuludq/3*shift/2*add
576
577 { ISD::FDIV, MVT::f32, 7 }, // Haswell from http://www.agner.org/
578 { ISD::FDIV, MVT::v4f32, 7 }, // Haswell from http://www.agner.org/
579 { ISD::FDIV, MVT::v8f32, 14 }, // Haswell from http://www.agner.org/
580 { ISD::FDIV, MVT::f64, 14 }, // Haswell from http://www.agner.org/
581 { ISD::FDIV, MVT::v2f64, 14 }, // Haswell from http://www.agner.org/
582 { ISD::FDIV, MVT::v4f64, 28 }, // Haswell from http://www.agner.org/
583 };
584
585 // Look for AVX2 lowering tricks for custom cases.
586 if (ST->hasAVX2())
587 if (const auto *Entry = CostTableLookup(AVX2CostTable, ISD, LT.second))
588 return LT.first * Entry->Cost;
589
590 static const CostTblEntry AVX1CostTable[] = {
591 // We don't have to scalarize unsupported ops. We can issue two half-sized
592 // operations and we only need to extract the upper YMM half.
593 // Two ops + 1 extract + 1 insert = 4.
594 { ISD::MUL, MVT::v16i16, 4 },
595 { ISD::MUL, MVT::v8i32, 4 },
596 { ISD::SUB, MVT::v32i8, 4 },
597 { ISD::ADD, MVT::v32i8, 4 },
598 { ISD::SUB, MVT::v16i16, 4 },
599 { ISD::ADD, MVT::v16i16, 4 },
600 { ISD::SUB, MVT::v8i32, 4 },
601 { ISD::ADD, MVT::v8i32, 4 },
602 { ISD::SUB, MVT::v4i64, 4 },
603 { ISD::ADD, MVT::v4i64, 4 },
604
605 // A v4i64 multiply is custom lowered as two split v2i64 vectors that then
606 // are lowered as a series of long multiplies(3), shifts(3) and adds(2)
607 // Because we believe v4i64 to be a legal type, we must also include the
608 // extract+insert in the cost table. Therefore, the cost here is 18
609 // instead of 8.
610 { ISD::MUL, MVT::v4i64, 18 },
611
612 { ISD::MUL, MVT::v32i8, 26 }, // extend/pmullw/trunc sequence.
613
614 { ISD::FDIV, MVT::f32, 14 }, // SNB from http://www.agner.org/
615 { ISD::FDIV, MVT::v4f32, 14 }, // SNB from http://www.agner.org/
616 { ISD::FDIV, MVT::v8f32, 28 }, // SNB from http://www.agner.org/
617 { ISD::FDIV, MVT::f64, 22 }, // SNB from http://www.agner.org/
618 { ISD::FDIV, MVT::v2f64, 22 }, // SNB from http://www.agner.org/
619 { ISD::FDIV, MVT::v4f64, 44 }, // SNB from http://www.agner.org/
620
621 // Vectorizing division is a bad idea. See the SSE2 table for more comments.
622 { ISD::SDIV, MVT::v32i8, 32*20 },
623 { ISD::SDIV, MVT::v16i16, 16*20 },
624 { ISD::SDIV, MVT::v8i32, 8*20 },
625 { ISD::SDIV, MVT::v4i64, 4*20 },
626 { ISD::UDIV, MVT::v32i8, 32*20 },
627 { ISD::UDIV, MVT::v16i16, 16*20 },
628 { ISD::UDIV, MVT::v8i32, 8*20 },
629 { ISD::UDIV, MVT::v4i64, 4*20 },
630 };
631
632 if (ST->hasAVX())
633 if (const auto *Entry = CostTableLookup(AVX1CostTable, ISD, LT.second))
634 return LT.first * Entry->Cost;
635
636 static const CostTblEntry SSE42CostTable[] = {
637 { ISD::FDIV, MVT::f32, 14 }, // Nehalem from http://www.agner.org/
638 { ISD::FDIV, MVT::v4f32, 14 }, // Nehalem from http://www.agner.org/
639 { ISD::FDIV, MVT::f64, 22 }, // Nehalem from http://www.agner.org/
640 { ISD::FDIV, MVT::v2f64, 22 }, // Nehalem from http://www.agner.org/
641 };
642
643 if (ST->hasSSE42())
644 if (const auto *Entry = CostTableLookup(SSE42CostTable, ISD, LT.second))
645 return LT.first * Entry->Cost;
646
647 static const CostTblEntry SSE41CostTable[] = {
648 { ISD::SHL, MVT::v16i8, 11 }, // pblendvb sequence.
649 { ISD::SHL, MVT::v32i8, 2*11+2 }, // pblendvb sequence + split.
650 { ISD::SHL, MVT::v8i16, 14 }, // pblendvb sequence.
651 { ISD::SHL, MVT::v16i16, 2*14+2 }, // pblendvb sequence + split.
652 { ISD::SHL, MVT::v4i32, 4 }, // pslld/paddd/cvttps2dq/pmulld
653 { ISD::SHL, MVT::v8i32, 2*4+2 }, // pslld/paddd/cvttps2dq/pmulld + split
654
655 { ISD::SRL, MVT::v16i8, 12 }, // pblendvb sequence.
656 { ISD::SRL, MVT::v32i8, 2*12+2 }, // pblendvb sequence + split.
657 { ISD::SRL, MVT::v8i16, 14 }, // pblendvb sequence.
658 { ISD::SRL, MVT::v16i16, 2*14+2 }, // pblendvb sequence + split.
659 { ISD::SRL, MVT::v4i32, 11 }, // Shift each lane + blend.
660 { ISD::SRL, MVT::v8i32, 2*11+2 }, // Shift each lane + blend + split.
661
662 { ISD::SRA, MVT::v16i8, 24 }, // pblendvb sequence.
663 { ISD::SRA, MVT::v32i8, 2*24+2 }, // pblendvb sequence + split.
664 { ISD::SRA, MVT::v8i16, 14 }, // pblendvb sequence.
665 { ISD::SRA, MVT::v16i16, 2*14+2 }, // pblendvb sequence + split.
666 { ISD::SRA, MVT::v4i32, 12 }, // Shift each lane + blend.
667 { ISD::SRA, MVT::v8i32, 2*12+2 }, // Shift each lane + blend + split.
668
669 { ISD::MUL, MVT::v4i32, 1 } // pmulld
670 };
671
672 if (ST->hasSSE41())
673 if (const auto *Entry = CostTableLookup(SSE41CostTable, ISD, LT.second))
674 return LT.first * Entry->Cost;
675
676 static const CostTblEntry SSE2CostTable[] = {
677 // We don't correctly identify costs of casts because they are marked as
678 // custom.
679 { ISD::SHL, MVT::v16i8, 26 }, // cmpgtb sequence.
680 { ISD::SHL, MVT::v8i16, 32 }, // cmpgtb sequence.
681 { ISD::SHL, MVT::v4i32, 2*5 }, // We optimized this using mul.
682 { ISD::SHL, MVT::v2i64, 4 }, // splat+shuffle sequence.
683 { ISD::SHL, MVT::v4i64, 2*4+2 }, // splat+shuffle sequence + split.
684
685 { ISD::SRL, MVT::v16i8, 26 }, // cmpgtb sequence.
686 { ISD::SRL, MVT::v8i16, 32 }, // cmpgtb sequence.
687 { ISD::SRL, MVT::v4i32, 16 }, // Shift each lane + blend.
688 { ISD::SRL, MVT::v2i64, 4 }, // splat+shuffle sequence.
689 { ISD::SRL, MVT::v4i64, 2*4+2 }, // splat+shuffle sequence + split.
690
691 { ISD::SRA, MVT::v16i8, 54 }, // unpacked cmpgtb sequence.
692 { ISD::SRA, MVT::v8i16, 32 }, // cmpgtb sequence.
693 { ISD::SRA, MVT::v4i32, 16 }, // Shift each lane + blend.
694 { ISD::SRA, MVT::v2i64, 12 }, // srl/xor/sub sequence.
695 { ISD::SRA, MVT::v4i64, 2*12+2 }, // srl/xor/sub sequence+split.
696
697 { ISD::MUL, MVT::v16i8, 12 }, // extend/pmullw/trunc sequence.
698 { ISD::MUL, MVT::v8i16, 1 }, // pmullw
699 { ISD::MUL, MVT::v4i32, 6 }, // 3*pmuludq/4*shuffle
700 { ISD::MUL, MVT::v2i64, 8 }, // 3*pmuludq/3*shift/2*add
701
702 { ISD::FDIV, MVT::f32, 23 }, // Pentium IV from http://www.agner.org/
703 { ISD::FDIV, MVT::v4f32, 39 }, // Pentium IV from http://www.agner.org/
704 { ISD::FDIV, MVT::f64, 38 }, // Pentium IV from http://www.agner.org/
705 { ISD::FDIV, MVT::v2f64, 69 }, // Pentium IV from http://www.agner.org/
706
707 // It is not a good idea to vectorize division. We have to scalarize it and
708 // in the process we will often end up having to spilling regular
709 // registers. The overhead of division is going to dominate most kernels
710 // anyways so try hard to prevent vectorization of division - it is
711 // generally a bad idea. Assume somewhat arbitrarily that we have to be able
712 // to hide "20 cycles" for each lane.
713 { ISD::SDIV, MVT::v16i8, 16*20 },
714 { ISD::SDIV, MVT::v8i16, 8*20 },
715 { ISD::SDIV, MVT::v4i32, 4*20 },
716 { ISD::SDIV, MVT::v2i64, 2*20 },
717 { ISD::UDIV, MVT::v16i8, 16*20 },
718 { ISD::UDIV, MVT::v8i16, 8*20 },
719 { ISD::UDIV, MVT::v4i32, 4*20 },
720 { ISD::UDIV, MVT::v2i64, 2*20 },
721 };
722
723 if (ST->hasSSE2())
724 if (const auto *Entry = CostTableLookup(SSE2CostTable, ISD, LT.second))
725 return LT.first * Entry->Cost;
726
727 static const CostTblEntry SSE1CostTable[] = {
728 { ISD::FDIV, MVT::f32, 17 }, // Pentium III from http://www.agner.org/
729 { ISD::FDIV, MVT::v4f32, 34 }, // Pentium III from http://www.agner.org/
730 };
731
732 if (ST->hasSSE1())
733 if (const auto *Entry = CostTableLookup(SSE1CostTable, ISD, LT.second))
734 return LT.first * Entry->Cost;
735
736 // Fallback to the default implementation.
737 return BaseT::getArithmeticInstrCost(Opcode, Ty, Op1Info, Op2Info);
738}
739
740int X86TTIImpl::getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, int Index,
741 Type *SubTp) {
742 // 64-bit packed float vectors (v2f32) are widened to type v4f32.
743 // 64-bit packed integer vectors (v2i32) are promoted to type v2i64.
744 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Tp);
745
746 // For Broadcasts we are splatting the first element from the first input
747 // register, so only need to reference that input and all the output
748 // registers are the same.
749 if (Kind == TTI::SK_Broadcast)
750 LT.first = 1;
751
752 // We are going to permute multiple sources and the result will be in multiple
753 // destinations. Providing an accurate cost only for splits where the element
754 // type remains the same.
755 if (Kind == TTI::SK_PermuteSingleSrc && LT.first != 1) {
756 MVT LegalVT = LT.second;
757 if (LegalVT.getVectorElementType().getSizeInBits() ==
758 Tp->getVectorElementType()->getPrimitiveSizeInBits() &&
759 LegalVT.getVectorNumElements() < Tp->getVectorNumElements()) {
760
761 unsigned VecTySize = DL.getTypeStoreSize(Tp);
762 unsigned LegalVTSize = LegalVT.getStoreSize();
763 // Number of source vectors after legalization:
764 unsigned NumOfSrcs = (VecTySize + LegalVTSize - 1) / LegalVTSize;
765 // Number of destination vectors after legalization:
766 unsigned NumOfDests = LT.first;
767
768 Type *SingleOpTy = VectorType::get(Tp->getVectorElementType(),
769 LegalVT.getVectorNumElements());
770
771 unsigned NumOfShuffles = (NumOfSrcs - 1) * NumOfDests;
772 return NumOfShuffles *
773 getShuffleCost(TTI::SK_PermuteTwoSrc, SingleOpTy, 0, nullptr);
774 }
775
776 return BaseT::getShuffleCost(Kind, Tp, Index, SubTp);
777 }
778
779 // For 2-input shuffles, we must account for splitting the 2 inputs into many.
780 if (Kind == TTI::SK_PermuteTwoSrc && LT.first != 1) {
781 // We assume that source and destination have the same vector type.
782 int NumOfDests = LT.first;
783 int NumOfShufflesPerDest = LT.first * 2 - 1;
784 LT.first = NumOfDests * NumOfShufflesPerDest;
785 }
786
787 static const CostTblEntry AVX512VBMIShuffleTbl[] = {
788 { TTI::SK_Reverse, MVT::v64i8, 1 }, // vpermb
789 { TTI::SK_Reverse, MVT::v32i8, 1 }, // vpermb
790
791 { TTI::SK_PermuteSingleSrc, MVT::v64i8, 1 }, // vpermb
792 { TTI::SK_PermuteSingleSrc, MVT::v32i8, 1 }, // vpermb
793
794 { TTI::SK_PermuteTwoSrc, MVT::v64i8, 1 }, // vpermt2b
795 { TTI::SK_PermuteTwoSrc, MVT::v32i8, 1 }, // vpermt2b
796 { TTI::SK_PermuteTwoSrc, MVT::v16i8, 1 } // vpermt2b
797 };
798
799 if (ST->hasVBMI())
800 if (const auto *Entry =
801 CostTableLookup(AVX512VBMIShuffleTbl, Kind, LT.second))
802 return LT.first * Entry->Cost;
803
804 static const CostTblEntry AVX512BWShuffleTbl[] = {
805 { TTI::SK_Broadcast, MVT::v32i16, 1 }, // vpbroadcastw
806 { TTI::SK_Broadcast, MVT::v64i8, 1 }, // vpbroadcastb
807
808 { TTI::SK_Reverse, MVT::v32i16, 1 }, // vpermw
809 { TTI::SK_Reverse, MVT::v16i16, 1 }, // vpermw
810 { TTI::SK_Reverse, MVT::v64i8, 2 }, // pshufb + vshufi64x2
811
812 { TTI::SK_PermuteSingleSrc, MVT::v32i16, 1 }, // vpermw
813 { TTI::SK_PermuteSingleSrc, MVT::v16i16, 1 }, // vpermw
814 { TTI::SK_PermuteSingleSrc, MVT::v8i16, 1 }, // vpermw
815 { TTI::SK_PermuteSingleSrc, MVT::v64i8, 8 }, // extend to v32i16
816 { TTI::SK_PermuteSingleSrc, MVT::v32i8, 3 }, // vpermw + zext/trunc
817
818 { TTI::SK_PermuteTwoSrc, MVT::v32i16, 1 }, // vpermt2w
819 { TTI::SK_PermuteTwoSrc, MVT::v16i16, 1 }, // vpermt2w
820 { TTI::SK_PermuteTwoSrc, MVT::v8i16, 1 }, // vpermt2w
821 { TTI::SK_PermuteTwoSrc, MVT::v32i8, 3 }, // zext + vpermt2w + trunc
822 { TTI::SK_PermuteTwoSrc, MVT::v64i8, 19 }, // 6 * v32i8 + 1
823 { TTI::SK_PermuteTwoSrc, MVT::v16i8, 3 } // zext + vpermt2w + trunc
824 };
825
826 if (ST->hasBWI())
827 if (const auto *Entry =
828 CostTableLookup(AVX512BWShuffleTbl, Kind, LT.second))
829 return LT.first * Entry->Cost;
830
831 static const CostTblEntry AVX512ShuffleTbl[] = {
832 { TTI::SK_Broadcast, MVT::v8f64, 1 }, // vbroadcastpd
833 { TTI::SK_Broadcast, MVT::v16f32, 1 }, // vbroadcastps
834 { TTI::SK_Broadcast, MVT::v8i64, 1 }, // vpbroadcastq
835 { TTI::SK_Broadcast, MVT::v16i32, 1 }, // vpbroadcastd
836
837 { TTI::SK_Reverse, MVT::v8f64, 1 }, // vpermpd
838 { TTI::SK_Reverse, MVT::v16f32, 1 }, // vpermps
839 { TTI::SK_Reverse, MVT::v8i64, 1 }, // vpermq
840 { TTI::SK_Reverse, MVT::v16i32, 1 }, // vpermd
841
842 { TTI::SK_PermuteSingleSrc, MVT::v8f64, 1 }, // vpermpd
843 { TTI::SK_PermuteSingleSrc, MVT::v4f64, 1 }, // vpermpd
844 { TTI::SK_PermuteSingleSrc, MVT::v2f64, 1 }, // vpermpd
845 { TTI::SK_PermuteSingleSrc, MVT::v16f32, 1 }, // vpermps
846 { TTI::SK_PermuteSingleSrc, MVT::v8f32, 1 }, // vpermps
847 { TTI::SK_PermuteSingleSrc, MVT::v4f32, 1 }, // vpermps
848 { TTI::SK_PermuteSingleSrc, MVT::v8i64, 1 }, // vpermq
849 { TTI::SK_PermuteSingleSrc, MVT::v4i64, 1 }, // vpermq
850 { TTI::SK_PermuteSingleSrc, MVT::v2i64, 1 }, // vpermq
851 { TTI::SK_PermuteSingleSrc, MVT::v16i32, 1 }, // vpermd
852 { TTI::SK_PermuteSingleSrc, MVT::v8i32, 1 }, // vpermd
853 { TTI::SK_PermuteSingleSrc, MVT::v4i32, 1 }, // vpermd
854 { TTI::SK_PermuteSingleSrc, MVT::v16i8, 1 }, // pshufb
855
856 { TTI::SK_PermuteTwoSrc, MVT::v8f64, 1 }, // vpermt2pd
857 { TTI::SK_PermuteTwoSrc, MVT::v16f32, 1 }, // vpermt2ps
858 { TTI::SK_PermuteTwoSrc, MVT::v8i64, 1 }, // vpermt2q
859 { TTI::SK_PermuteTwoSrc, MVT::v16i32, 1 }, // vpermt2d
860 { TTI::SK_PermuteTwoSrc, MVT::v4f64, 1 }, // vpermt2pd
861 { TTI::SK_PermuteTwoSrc, MVT::v8f32, 1 }, // vpermt2ps
862 { TTI::SK_PermuteTwoSrc, MVT::v4i64, 1 }, // vpermt2q
863 { TTI::SK_PermuteTwoSrc, MVT::v8i32, 1 }, // vpermt2d
864 { TTI::SK_PermuteTwoSrc, MVT::v2f64, 1 }, // vpermt2pd
865 { TTI::SK_PermuteTwoSrc, MVT::v4f32, 1 }, // vpermt2ps
866 { TTI::SK_PermuteTwoSrc, MVT::v2i64, 1 }, // vpermt2q
867 { TTI::SK_PermuteTwoSrc, MVT::v4i32, 1 } // vpermt2d
868 };
869
870 if (ST->hasAVX512())
871 if (const auto *Entry = CostTableLookup(AVX512ShuffleTbl, Kind, LT.second))
872 return LT.first * Entry->Cost;
873
874 static const CostTblEntry AVX2ShuffleTbl[] = {
875 { TTI::SK_Broadcast, MVT::v4f64, 1 }, // vbroadcastpd
876 { TTI::SK_Broadcast, MVT::v8f32, 1 }, // vbroadcastps
877 { TTI::SK_Broadcast, MVT::v4i64, 1 }, // vpbroadcastq
878 { TTI::SK_Broadcast, MVT::v8i32, 1 }, // vpbroadcastd
879 { TTI::SK_Broadcast, MVT::v16i16, 1 }, // vpbroadcastw
880 { TTI::SK_Broadcast, MVT::v32i8, 1 }, // vpbroadcastb
881
882 { TTI::SK_Reverse, MVT::v4f64, 1 }, // vpermpd
883 { TTI::SK_Reverse, MVT::v8f32, 1 }, // vpermps
884 { TTI::SK_Reverse, MVT::v4i64, 1 }, // vpermq
885 { TTI::SK_Reverse, MVT::v8i32, 1 }, // vpermd
886 { TTI::SK_Reverse, MVT::v16i16, 2 }, // vperm2i128 + pshufb
887 { TTI::SK_Reverse, MVT::v32i8, 2 }, // vperm2i128 + pshufb
888
889 { TTI::SK_Alternate, MVT::v16i16, 1 }, // vpblendw
890 { TTI::SK_Alternate, MVT::v32i8, 1 }, // vpblendvb
891
892 { TTI::SK_PermuteSingleSrc, MVT::v4f64, 1 }, // vpermpd
893 { TTI::SK_PermuteSingleSrc, MVT::v8f32, 1 }, // vpermps
894 { TTI::SK_PermuteSingleSrc, MVT::v4i64, 1 }, // vpermq
895 { TTI::SK_PermuteSingleSrc, MVT::v8i32, 1 }, // vpermd
896 { TTI::SK_PermuteSingleSrc, MVT::v16i16, 4 }, // vperm2i128 + 2*vpshufb
897 // + vpblendvb
898 { TTI::SK_PermuteSingleSrc, MVT::v32i8, 4 }, // vperm2i128 + 2*vpshufb
899 // + vpblendvb
900
901 { TTI::SK_PermuteTwoSrc, MVT::v4f64, 3 }, // 2*vpermpd + vblendpd
902 { TTI::SK_PermuteTwoSrc, MVT::v8f32, 3 }, // 2*vpermps + vblendps
903 { TTI::SK_PermuteTwoSrc, MVT::v4i64, 3 }, // 2*vpermq + vpblendd
904 { TTI::SK_PermuteTwoSrc, MVT::v8i32, 3 }, // 2*vpermd + vpblendd
905 { TTI::SK_PermuteTwoSrc, MVT::v16i16, 7 }, // 2*vperm2i128 + 4*vpshufb
906 // + vpblendvb
907 { TTI::SK_PermuteTwoSrc, MVT::v32i8, 7 }, // 2*vperm2i128 + 4*vpshufb
908 // + vpblendvb
909 };
910
911 if (ST->hasAVX2())
912 if (const auto *Entry = CostTableLookup(AVX2ShuffleTbl, Kind, LT.second))
913 return LT.first * Entry->Cost;
914
915 static const CostTblEntry XOPShuffleTbl[] = {
916 { TTI::SK_PermuteSingleSrc, MVT::v4f64, 2 }, // vperm2f128 + vpermil2pd
917 { TTI::SK_PermuteSingleSrc, MVT::v8f32, 2 }, // vperm2f128 + vpermil2ps
918 { TTI::SK_PermuteSingleSrc, MVT::v4i64, 2 }, // vperm2f128 + vpermil2pd
919 { TTI::SK_PermuteSingleSrc, MVT::v8i32, 2 }, // vperm2f128 + vpermil2ps
920 { TTI::SK_PermuteSingleSrc, MVT::v16i16, 4 }, // vextractf128 + 2*vpperm
921 // + vinsertf128
922 { TTI::SK_PermuteSingleSrc, MVT::v32i8, 4 }, // vextractf128 + 2*vpperm
923 // + vinsertf128
924
925 { TTI::SK_PermuteTwoSrc, MVT::v16i16, 9 }, // 2*vextractf128 + 6*vpperm
926 // + vinsertf128
927 { TTI::SK_PermuteTwoSrc, MVT::v8i16, 1 }, // vpperm
928 { TTI::SK_PermuteTwoSrc, MVT::v32i8, 9 }, // 2*vextractf128 + 6*vpperm
929 // + vinsertf128
930 { TTI::SK_PermuteTwoSrc, MVT::v16i8, 1 }, // vpperm
931 };
932
933 if (ST->hasXOP())
934 if (const auto *Entry = CostTableLookup(XOPShuffleTbl, Kind, LT.second))
935 return LT.first * Entry->Cost;
936
937 static const CostTblEntry AVX1ShuffleTbl[] = {
938 { TTI::SK_Broadcast, MVT::v4f64, 2 }, // vperm2f128 + vpermilpd
939 { TTI::SK_Broadcast, MVT::v8f32, 2 }, // vperm2f128 + vpermilps
940 { TTI::SK_Broadcast, MVT::v4i64, 2 }, // vperm2f128 + vpermilpd
941 { TTI::SK_Broadcast, MVT::v8i32, 2 }, // vperm2f128 + vpermilps
942 { TTI::SK_Broadcast, MVT::v16i16, 3 }, // vpshuflw + vpshufd + vinsertf128
943 { TTI::SK_Broadcast, MVT::v32i8, 2 }, // vpshufb + vinsertf128
944
945 { TTI::SK_Reverse, MVT::v4f64, 2 }, // vperm2f128 + vpermilpd
946 { TTI::SK_Reverse, MVT::v8f32, 2 }, // vperm2f128 + vpermilps
947 { TTI::SK_Reverse, MVT::v4i64, 2 }, // vperm2f128 + vpermilpd
948 { TTI::SK_Reverse, MVT::v8i32, 2 }, // vperm2f128 + vpermilps
949 { TTI::SK_Reverse, MVT::v16i16, 4 }, // vextractf128 + 2*pshufb
950 // + vinsertf128
951 { TTI::SK_Reverse, MVT::v32i8, 4 }, // vextractf128 + 2*pshufb
952 // + vinsertf128
953
954 { TTI::SK_Alternate, MVT::v4i64, 1 }, // vblendpd
955 { TTI::SK_Alternate, MVT::v4f64, 1 }, // vblendpd
956 { TTI::SK_Alternate, MVT::v8i32, 1 }, // vblendps
957 { TTI::SK_Alternate, MVT::v8f32, 1 }, // vblendps
958 { TTI::SK_Alternate, MVT::v16i16, 3 }, // vpand + vpandn + vpor
959 { TTI::SK_Alternate, MVT::v32i8, 3 }, // vpand + vpandn + vpor
960
961 { TTI::SK_PermuteSingleSrc, MVT::v4f64, 3 }, // 2*vperm2f128 + vshufpd
962 { TTI::SK_PermuteSingleSrc, MVT::v4i64, 3 }, // 2*vperm2f128 + vshufpd
963 { TTI::SK_PermuteSingleSrc, MVT::v8f32, 4 }, // 2*vperm2f128 + 2*vshufps
964 { TTI::SK_PermuteSingleSrc, MVT::v8i32, 4 }, // 2*vperm2f128 + 2*vshufps
965 { TTI::SK_PermuteSingleSrc, MVT::v16i16, 8 }, // vextractf128 + 4*pshufb
966 // + 2*por + vinsertf128
967 { TTI::SK_PermuteSingleSrc, MVT::v32i8, 8 }, // vextractf128 + 4*pshufb
968 // + 2*por + vinsertf128
969
970 { TTI::SK_PermuteTwoSrc, MVT::v4f64, 4 }, // 2*vperm2f128 + 2*vshufpd
971 { TTI::SK_PermuteTwoSrc, MVT::v8f32, 4 }, // 2*vperm2f128 + 2*vshufps
972 { TTI::SK_PermuteTwoSrc, MVT::v4i64, 4 }, // 2*vperm2f128 + 2*vshufpd
973 { TTI::SK_PermuteTwoSrc, MVT::v8i32, 4 }, // 2*vperm2f128 + 2*vshufps
974 { TTI::SK_PermuteTwoSrc, MVT::v16i16, 15 }, // 2*vextractf128 + 8*pshufb
975 // + 4*por + vinsertf128
976 { TTI::SK_PermuteTwoSrc, MVT::v32i8, 15 }, // 2*vextractf128 + 8*pshufb
977 // + 4*por + vinsertf128
978 };
979
980 if (ST->hasAVX())
981 if (const auto *Entry = CostTableLookup(AVX1ShuffleTbl, Kind, LT.second))
982 return LT.first * Entry->Cost;
983
984 static const CostTblEntry SSE41ShuffleTbl[] = {
985 { TTI::SK_Alternate, MVT::v2i64, 1 }, // pblendw
986 { TTI::SK_Alternate, MVT::v2f64, 1 }, // movsd
987 { TTI::SK_Alternate, MVT::v4i32, 1 }, // pblendw
988 { TTI::SK_Alternate, MVT::v4f32, 1 }, // blendps
989 { TTI::SK_Alternate, MVT::v8i16, 1 }, // pblendw
990 { TTI::SK_Alternate, MVT::v16i8, 1 } // pblendvb
991 };
992
993 if (ST->hasSSE41())
994 if (const auto *Entry = CostTableLookup(SSE41ShuffleTbl, Kind, LT.second))
995 return LT.first * Entry->Cost;
996
997 static const CostTblEntry SSSE3ShuffleTbl[] = {
998 { TTI::SK_Broadcast, MVT::v8i16, 1 }, // pshufb
999 { TTI::SK_Broadcast, MVT::v16i8, 1 }, // pshufb
1000
1001 { TTI::SK_Reverse, MVT::v8i16, 1 }, // pshufb
1002 { TTI::SK_Reverse, MVT::v16i8, 1 }, // pshufb
1003
1004 { TTI::SK_Alternate, MVT::v8i16, 3 }, // 2*pshufb + por
1005 { TTI::SK_Alternate, MVT::v16i8, 3 }, // 2*pshufb + por
1006
1007 { TTI::SK_PermuteSingleSrc, MVT::v8i16, 1 }, // pshufb
1008 { TTI::SK_PermuteSingleSrc, MVT::v16i8, 1 }, // pshufb
1009
1010 { TTI::SK_PermuteTwoSrc, MVT::v8i16, 3 }, // 2*pshufb + por
1011 { TTI::SK_PermuteTwoSrc, MVT::v16i8, 3 }, // 2*pshufb + por
1012 };
1013
1014 if (ST->hasSSSE3())
1015 if (const auto *Entry = CostTableLookup(SSSE3ShuffleTbl, Kind, LT.second))
1016 return LT.first * Entry->Cost;
1017
1018 static const CostTblEntry SSE2ShuffleTbl[] = {
1019 { TTI::SK_Broadcast, MVT::v2f64, 1 }, // shufpd
1020 { TTI::SK_Broadcast, MVT::v2i64, 1 }, // pshufd
1021 { TTI::SK_Broadcast, MVT::v4i32, 1 }, // pshufd
1022 { TTI::SK_Broadcast, MVT::v8i16, 2 }, // pshuflw + pshufd
1023 { TTI::SK_Broadcast, MVT::v16i8, 3 }, // unpck + pshuflw + pshufd
1024
1025 { TTI::SK_Reverse, MVT::v2f64, 1 }, // shufpd
1026 { TTI::SK_Reverse, MVT::v2i64, 1 }, // pshufd
1027 { TTI::SK_Reverse, MVT::v4i32, 1 }, // pshufd
1028 { TTI::SK_Reverse, MVT::v8i16, 3 }, // pshuflw + pshufhw + pshufd
1029 { TTI::SK_Reverse, MVT::v16i8, 9 }, // 2*pshuflw + 2*pshufhw
1030 // + 2*pshufd + 2*unpck + packus
1031
1032 { TTI::SK_Alternate, MVT::v2i64, 1 }, // movsd
1033 { TTI::SK_Alternate, MVT::v2f64, 1 }, // movsd
1034 { TTI::SK_Alternate, MVT::v4i32, 2 }, // 2*shufps
1035 { TTI::SK_Alternate, MVT::v8i16, 3 }, // pand + pandn + por
1036 { TTI::SK_Alternate, MVT::v16i8, 3 }, // pand + pandn + por
1037
1038 { TTI::SK_PermuteSingleSrc, MVT::v2f64, 1 }, // shufpd
1039 { TTI::SK_PermuteSingleSrc, MVT::v2i64, 1 }, // pshufd
1040 { TTI::SK_PermuteSingleSrc, MVT::v4i32, 1 }, // pshufd
1041 { TTI::SK_PermuteSingleSrc, MVT::v8i16, 5 }, // 2*pshuflw + 2*pshufhw
1042 // + pshufd/unpck
1043 { TTI::SK_PermuteSingleSrc, MVT::v16i8, 10 }, // 2*pshuflw + 2*pshufhw
1044 // + 2*pshufd + 2*unpck + 2*packus
1045
1046 { TTI::SK_PermuteTwoSrc, MVT::v2f64, 1 }, // shufpd
1047 { TTI::SK_PermuteTwoSrc, MVT::v2i64, 1 }, // shufpd
1048 { TTI::SK_PermuteTwoSrc, MVT::v4i32, 2 }, // 2*{unpck,movsd,pshufd}
1049 { TTI::SK_PermuteTwoSrc, MVT::v8i16, 8 }, // blend+permute
1050 { TTI::SK_PermuteTwoSrc, MVT::v16i8, 13 }, // blend+permute
1051 };
1052
1053 if (ST->hasSSE2())
1054 if (const auto *Entry = CostTableLookup(SSE2ShuffleTbl, Kind, LT.second))
1055 return LT.first * Entry->Cost;
1056
1057 static const CostTblEntry SSE1ShuffleTbl[] = {
1058 { TTI::SK_Broadcast, MVT::v4f32, 1 }, // shufps
1059 { TTI::SK_Reverse, MVT::v4f32, 1 }, // shufps
1060 { TTI::SK_Alternate, MVT::v4f32, 2 }, // 2*shufps
1061 { TTI::SK_PermuteSingleSrc, MVT::v4f32, 1 }, // shufps
1062 { TTI::SK_PermuteTwoSrc, MVT::v4f32, 2 }, // 2*shufps
1063 };
1064
1065 if (ST->hasSSE1())
1066 if (const auto *Entry = CostTableLookup(SSE1ShuffleTbl, Kind, LT.second))
1067 return LT.first * Entry->Cost;
1068
1069 return BaseT::getShuffleCost(Kind, Tp, Index, SubTp);
1070}
1071
1072int X86TTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src,
1073 const Instruction *I) {
1074 int ISD = TLI->InstructionOpcodeToISD(Opcode);
1075 assert(ISD && "Invalid opcode")((ISD && "Invalid opcode") ? static_cast<void> (
0) : __assert_fail ("ISD && \"Invalid opcode\"", "/build/llvm-toolchain-snapshot-6.0~svn318211/lib/Target/X86/X86TargetTransformInfo.cpp"
, 1075, __PRETTY_FUNCTION__))
;
1076
1077 // FIXME: Need a better design of the cost table to handle non-simple types of
1078 // potential massive combinations (elem_num x src_type x dst_type).
1079
1080 static const TypeConversionCostTblEntry AVX512DQConversionTbl[] = {
1081 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i64, 1 },
1082 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 },
1083 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i64, 1 },
1084 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 1 },
1085 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 },
1086 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 },
1087
1088 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 1 },
1089 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 },
1090 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i64, 1 },
1091 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 1 },
1092 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 },
1093 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 },
1094
1095 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f32, 1 },
1096 { ISD::FP_TO_SINT, MVT::v4i64, MVT::v4f32, 1 },
1097 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f32, 1 },
1098 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f64, 1 },
1099 { ISD::FP_TO_SINT, MVT::v4i64, MVT::v4f64, 1 },
1100 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f64, 1 },
1101
1102 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f32, 1 },
1103 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f32, 1 },
1104 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f32, 1 },
1105 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f64, 1 },
1106 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f64, 1 },
1107 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f64, 1 },
1108 };
1109
1110 // TODO: For AVX512DQ + AVX512VL, we also have cheap casts for 128-bit and
1111 // 256-bit wide vectors.
1112
1113 static const TypeConversionCostTblEntry AVX512FConversionTbl[] = {
1114 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 1 },
1115 { ISD::FP_EXTEND, MVT::v8f64, MVT::v16f32, 3 },
1116 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 1 },
1117
1118 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 1 },
1119 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 1 },
1120 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i64, 1 },
1121 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 1 },
1122
1123 // v16i1 -> v16i32 - load + broadcast
1124 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i1, 2 },
1125 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i1, 2 },
1126 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 1 },
1127 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 1 },
1128 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 1 },
1129 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 1 },
1130 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i16, 1 },
1131 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 1 },
1132 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i32, 1 },
1133 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i32, 1 },
1134
1135 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 },
1136 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 },
1137 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i8, 2 },
1138 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i8, 2 },
1139 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 },
1140 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, 2 },
1141 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 },
1142 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 },
1143 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, 26 },
1144 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 26 },
1145
1146 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 },
1147 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 },
1148 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i8, 2 },
1149 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i8, 2 },
1150 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 2 },
1151 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i8, 2 },
1152 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i8, 2 },
1153 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i16, 5 },
1154 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i16, 2 },
1155 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 2 },
1156 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 },
1157 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i16, 2 },
1158 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 2 },
1159 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 1 },
1160 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
1161 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 },
1162 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 },
1163 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 },
1164 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 },
1165 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 5 },
1166 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 5 },
1167 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 12 },
1168 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 26 },
1169
1170 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f32, 1 },
1171 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 },
1172 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 1 },
1173 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f64, 2 },
1174 { ISD::FP_TO_UINT, MVT::v8i8, MVT::v8f64, 2 },
1175 { ISD::FP_TO_UINT, MVT::v16i32, MVT::v16f32, 1 },
1176 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v16f32, 2 },
1177 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v16f32, 2 },
1178 };
1179
1180 static const TypeConversionCostTblEntry AVX2ConversionTbl[] = {
1181 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 3 },
1182 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 3 },
1183 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 3 },
1184 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 3 },
1185 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 3 },
1186 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 3 },
1187 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 3 },
1188 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 3 },
1189 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 1 },
1190 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 1 },
1191 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
1192 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
1193 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 1 },
1194 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 1 },
1195 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 1 },
1196 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 1 },
1197
1198 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 2 },
1199 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 2 },
1200 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 2 },
1201 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 2 },
1202 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 2 },
1203 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 4 },
1204
1205 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 3 },
1206 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 3 },
1207
1208 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 8 },
1209 };
1210
1211 static const TypeConversionCostTblEntry AVXConversionTbl[] = {
1212 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 6 },
1213 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 4 },
1214 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 7 },
1215 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 4 },
1216 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 6 },
1217 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 4 },
1218 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 7 },
1219 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 4 },
1220 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 4 },
1221 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 4 },
1222 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 6 },
1223 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
1224 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 4 },
1225 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 4 },
1226 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 4 },
1227 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 4 },
1228
1229 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 4 },
1230 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 4 },
1231 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 5 },
1232 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 4 },
1233 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 4 },
1234 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 4 },
1235 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 9 },
1236
1237 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 },
1238 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i1, 3 },
1239 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i1, 8 },
1240 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 },
1241 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i8, 3 },
1242 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i8, 8 },
1243 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 3 },
1244 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i16, 3 },
1245 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 5 },
1246 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
1247 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 },
1248 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 },
1249
1250 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i1, 7 },
1251 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i1, 7 },
1252 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i1, 6 },
1253 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 2 },
1254 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i8, 2 },
1255 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 5 },
1256 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
1257 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i16, 2 },
1258 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 5 },
1259 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 6 },
1260 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 6 },
1261 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 6 },
1262 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 9 },
1263 // The generic code to compute the scalar overhead is currently broken.
1264 // Workaround this limitation by estimating the scalarization overhead
1265 // here. We have roughly 10 instructions per scalar element.
1266 // Multiply that by the vector width.
1267 // FIXME: remove that when PR19268 is fixed.
1268 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 10 },
1269 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 20 },
1270 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 13 },
1271 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 13 },
1272
1273 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 1 },
1274 { ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f32, 7 },
1275 // This node is expanded into scalarized operations but BasicTTI is overly
1276 // optimistic estimating its cost. It computes 3 per element (one
1277 // vector-extract, one scalar conversion and one vector-insert). The
1278 // problem is that the inserts form a read-modify-write chain so latency
1279 // should be factored in too. Inflating the cost per element by 1.
1280 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 8*4 },
1281 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 4*4 },
1282
1283 { ISD::FP_EXTEND, MVT::v4f64, MVT::v4f32, 1 },
1284 { ISD::FP_ROUND, MVT::v4f32, MVT::v4f64, 1 },
1285 };
1286
1287 static const TypeConversionCostTblEntry SSE41ConversionTbl[] = {
1288 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 2 },
1289 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 2 },
1290 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 2 },
1291 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 2 },
1292 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 2 },
1293 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 2 },
1294
1295 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i8, 1 },
1296 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i8, 2 },
1297 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i8, 1 },
1298 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i8, 1 },
1299 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i8, 1 },
1300 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i8, 1 },
1301 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 2 },
1302 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 2 },
1303 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 2 },
1304 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 2 },
1305 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 4 },
1306 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 4 },
1307 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 1 },
1308 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 1 },
1309 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 2 },
1310 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 2 },
1311 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 4 },
1312 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 4 },
1313
1314 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i16, 2 },
1315 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i16, 1 },
1316 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i32, 1 },
1317 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 1 },
1318 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 3 },
1319 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 3 },
1320 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 6 },
1321
1322 };
1323
1324 static const TypeConversionCostTblEntry SSE2ConversionTbl[] = {
1325 // These are somewhat magic numbers justified by looking at the output of
1326 // Intel's IACA, running some kernels and making sure when we take
1327 // legalization into account the throughput will be overestimated.
1328 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 },
1329 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 },
1330 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 },
1331 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 },
1332 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 5 },
1333 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v4i32, 4*10 },
1334 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 },
1335 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 2*10 },
1336
1337 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 },
1338 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 },
1339 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 },
1340 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 },
1341 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v4i32, 4*10 },
1342 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 8 },
1343 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 2*10 },
1344 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 },
1345
1346 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 3 },
1347
1348 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i8, 1 },
1349 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i8, 6 },
1350 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i8, 2 },
1351 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i8, 3 },
1352 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 4 },
1353 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 8 },
1354 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i8, 1 },
1355 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i8, 2 },
1356 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 6 },
1357 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 6 },
1358 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 3 },
1359 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 4 },
1360 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 9 },
1361 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 12 },
1362 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 1 },
1363 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 2 },
1364 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
1365 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 10 },
1366 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 3 },
1367 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 4 },
1368 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 6 },
1369 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 8 },
1370 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 3 },
1371 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 5 },
1372
1373 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i16, 4 },
1374 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i16, 2 },
1375 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 3 },
1376 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i32, 3 },
1377 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 3 },
1378 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 4 },
1379 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 7 },
1380 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 5 },
1381 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 10 },
1382 };
1383
1384 std::pair<int, MVT> LTSrc = TLI->getTypeLegalizationCost(DL, Src);
1385 std::pair<int, MVT> LTDest = TLI->getTypeLegalizationCost(DL, Dst);
1386
1387 if (ST->hasSSE2() && !ST->hasAVX()) {
1388 if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD,
1389 LTDest.second, LTSrc.second))
1390 return LTSrc.first * Entry->Cost;
1391 }
1392
1393 EVT SrcTy = TLI->getValueType(DL, Src);
1394 EVT DstTy = TLI->getValueType(DL, Dst);
1395
1396 // The function getSimpleVT only handles simple value types.
1397 if (!SrcTy.isSimple() || !DstTy.isSimple())
1398 return BaseT::getCastInstrCost(Opcode, Dst, Src);
1399
1400 if (ST->hasDQI())
1401 if (const auto *Entry = ConvertCostTableLookup(AVX512DQConversionTbl, ISD,
1402 DstTy.getSimpleVT(),
1403 SrcTy.getSimpleVT()))
1404 return Entry->Cost;
1405
1406 if (ST->hasAVX512())
1407 if (const auto *Entry = ConvertCostTableLookup(AVX512FConversionTbl, ISD,
1408 DstTy.getSimpleVT(),
1409 SrcTy.getSimpleVT()))
1410 return Entry->Cost;
1411
1412 if (ST->hasAVX2()) {
1413 if (const auto *Entry = ConvertCostTableLookup(AVX2ConversionTbl, ISD,
1414 DstTy.getSimpleVT(),
1415 SrcTy.getSimpleVT()))
1416 return Entry->Cost;
1417 }
1418
1419 if (ST->hasAVX()) {
1420 if (const auto *Entry = ConvertCostTableLookup(AVXConversionTbl, ISD,
1421 DstTy.getSimpleVT(),
1422 SrcTy.getSimpleVT()))
1423 return Entry->Cost;
1424 }
1425
1426 if (ST->hasSSE41()) {
1427 if (const auto *Entry = ConvertCostTableLookup(SSE41ConversionTbl, ISD,
1428 DstTy.getSimpleVT(),
1429 SrcTy.getSimpleVT()))
1430 return Entry->Cost;
1431 }
1432
1433 if (ST->hasSSE2()) {
1434 if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD,
1435 DstTy.getSimpleVT(),
1436 SrcTy.getSimpleVT()))
1437 return Entry->Cost;
1438 }
1439
1440 return BaseT::getCastInstrCost(Opcode, Dst, Src, I);
1441}
1442
1443int X86TTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy,
1444 const Instruction *I) {
1445 // Legalize the type.
1446 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy);
1447
1448 MVT MTy = LT.second;
1449
1450 int ISD = TLI->InstructionOpcodeToISD(Opcode);
1451 assert(ISD && "Invalid opcode")((ISD && "Invalid opcode") ? static_cast<void> (
0) : __assert_fail ("ISD && \"Invalid opcode\"", "/build/llvm-toolchain-snapshot-6.0~svn318211/lib/Target/X86/X86TargetTransformInfo.cpp"
, 1451, __PRETTY_FUNCTION__))
;
1452
1453 static const CostTblEntry SSE2CostTbl[] = {
1454 { ISD::SETCC, MVT::v2i64, 8 },
1455 { ISD::SETCC, MVT::v4i32, 1 },
1456 { ISD::SETCC, MVT::v8i16, 1 },
1457 { ISD::SETCC, MVT::v16i8, 1 },
1458 };
1459
1460 static const CostTblEntry SSE42CostTbl[] = {
1461 { ISD::SETCC, MVT::v2f64, 1 },
1462 { ISD::SETCC, MVT::v4f32, 1 },
1463 { ISD::SETCC, MVT::v2i64, 1 },
1464 };
1465
1466 static const CostTblEntry AVX1CostTbl[] = {
1467 { ISD::SETCC, MVT::v4f64, 1 },
1468 { ISD::SETCC, MVT::v8f32, 1 },
1469 // AVX1 does not support 8-wide integer compare.
1470 { ISD::SETCC, MVT::v4i64, 4 },
1471 { ISD::SETCC, MVT::v8i32, 4 },
1472 { ISD::SETCC, MVT::v16i16, 4 },
1473 { ISD::SETCC, MVT::v32i8, 4 },
1474 };
1475
1476 static const CostTblEntry AVX2CostTbl[] = {
1477 { ISD::SETCC, MVT::v4i64, 1 },
1478 { ISD::SETCC, MVT::v8i32, 1 },
1479 { ISD::SETCC, MVT::v16i16, 1 },
1480 { ISD::SETCC, MVT::v32i8, 1 },
1481 };
1482
1483 static const CostTblEntry AVX512CostTbl[] = {
1484 { ISD::SETCC, MVT::v8i64, 1 },
1485 { ISD::SETCC, MVT::v16i32, 1 },
1486 { ISD::SETCC, MVT::v8f64, 1 },
1487 { ISD::SETCC, MVT::v16f32, 1 },
1488 };
1489
1490 if (ST->hasAVX512())
1491 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy))
1492 return LT.first * Entry->Cost;
1493
1494 if (ST->hasAVX2())
1495 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy))
1496 return LT.first * Entry->Cost;
1497
1498 if (ST->hasAVX())
1499 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy))
1500 return LT.first * Entry->Cost;
1501
1502 if (ST->hasSSE42())
1503 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy))
1504 return LT.first * Entry->Cost;
1505
1506 if (ST->hasSSE2())
1507 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy))
1508 return LT.first * Entry->Cost;
1509
1510 return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy, I);
1511}
1512
1513unsigned X86TTIImpl::getAtomicMemIntrinsicMaxElementSize() const { return 16; }
1514
1515int X86TTIImpl::getIntrinsicInstrCost(Intrinsic::ID IID, Type *RetTy,
1516 ArrayRef<Type *> Tys, FastMathFlags FMF,
1517 unsigned ScalarizationCostPassed) {
1518 // Costs should match the codegen from:
1519 // BITREVERSE: llvm\test\CodeGen\X86\vector-bitreverse.ll
1520 // BSWAP: llvm\test\CodeGen\X86\bswap-vector.ll
1521 // CTLZ: llvm\test\CodeGen\X86\vector-lzcnt-*.ll
1522 // CTPOP: llvm\test\CodeGen\X86\vector-popcnt-*.ll
1523 // CTTZ: llvm\test\CodeGen\X86\vector-tzcnt-*.ll
1524 static const CostTblEntry AVX512CDCostTbl[] = {
1525 { ISD::CTLZ, MVT::v8i64, 1 },
1526 { ISD::CTLZ, MVT::v16i32, 1 },
1527 { ISD::CTLZ, MVT::v32i16, 8 },
1528 { ISD::CTLZ, MVT::v64i8, 20 },
1529 { ISD::CTLZ, MVT::v4i64, 1 },
1530 { ISD::CTLZ, MVT::v8i32, 1 },
1531 { ISD::CTLZ, MVT::v16i16, 4 },
1532 { ISD::CTLZ, MVT::v32i8, 10 },
1533 { ISD::CTLZ, MVT::v2i64, 1 },
1534 { ISD::CTLZ, MVT::v4i32, 1 },
1535 { ISD::CTLZ, MVT::v8i16, 4 },
1536 { ISD::CTLZ, MVT::v16i8, 4 },
1537 };
1538 static const CostTblEntry AVX512BWCostTbl[] = {
1539 { ISD::BITREVERSE, MVT::v8i64, 5 },
1540 { ISD::BITREVERSE, MVT::v16i32, 5 },
1541 { ISD::BITREVERSE, MVT::v32i16, 5 },
1542 { ISD::BITREVERSE, MVT::v64i8, 5 },
1543 { ISD::CTLZ, MVT::v8i64, 23 },
1544 { ISD::CTLZ, MVT::v16i32, 22 },
1545 { ISD::CTLZ, MVT::v32i16, 18 },
1546 { ISD::CTLZ, MVT::v64i8, 17 },
1547 { ISD::CTPOP, MVT::v8i64, 7 },
1548 { ISD::CTPOP, MVT::v16i32, 11 },
1549 { ISD::CTPOP, MVT::v32i16, 9 },
1550 { ISD::CTPOP, MVT::v64i8, 6 },
1551 { ISD::CTTZ, MVT::v8i64, 10 },
1552 { ISD::CTTZ, MVT::v16i32, 14 },
1553 { ISD::CTTZ, MVT::v32i16, 12 },
1554 { ISD::CTTZ, MVT::v64i8, 9 },
1555 };
1556 static const CostTblEntry AVX512CostTbl[] = {
1557 { ISD::BITREVERSE, MVT::v8i64, 36 },
1558 { ISD::BITREVERSE, MVT::v16i32, 24 },
1559 { ISD::CTLZ, MVT::v8i64, 29 },
1560 { ISD::CTLZ, MVT::v16i32, 35 },
1561 { ISD::CTPOP, MVT::v8i64, 16 },
1562 { ISD::CTPOP, MVT::v16i32, 24 },
1563 { ISD::CTTZ, MVT::v8i64, 20 },
1564 { ISD::CTTZ, MVT::v16i32, 28 },
1565 };
1566 static const CostTblEntry XOPCostTbl[] = {
1567 { ISD::BITREVERSE, MVT::v4i64, 4 },
1568 { ISD::BITREVERSE, MVT::v8i32, 4 },
1569 { ISD::BITREVERSE, MVT::v16i16, 4 },
1570 { ISD::BITREVERSE, MVT::v32i8, 4 },
1571 { ISD::BITREVERSE, MVT::v2i64, 1 },
1572 { ISD::BITREVERSE, MVT::v4i32, 1 },
1573 { ISD::BITREVERSE, MVT::v8i16, 1 },
1574 { ISD::BITREVERSE, MVT::v16i8, 1 },
1575 { ISD::BITREVERSE, MVT::i64, 3 },
1576 { ISD::BITREVERSE, MVT::i32, 3 },
1577 { ISD::BITREVERSE, MVT::i16, 3 },
1578 { ISD::BITREVERSE, MVT::i8, 3 }
1579 };
1580 static const CostTblEntry AVX2CostTbl[] = {
1581 { ISD::BITREVERSE, MVT::v4i64, 5 },
1582 { ISD::BITREVERSE, MVT::v8i32, 5 },
1583 { ISD::BITREVERSE, MVT::v16i16, 5 },
1584 { ISD::BITREVERSE, MVT::v32i8, 5 },
1585 { ISD::BSWAP, MVT::v4i64, 1 },
1586 { ISD::BSWAP, MVT::v8i32, 1 },
1587 { ISD::BSWAP, MVT::v16i16, 1 },
1588 { ISD::CTLZ, MVT::v4i64, 23 },
1589 { ISD::CTLZ, MVT::v8i32, 18 },
1590 { ISD::CTLZ, MVT::v16i16, 14 },
1591 { ISD::CTLZ, MVT::v32i8, 9 },
1592 { ISD::CTPOP, MVT::v4i64, 7 },
1593 { ISD::CTPOP, MVT::v8i32, 11 },
1594 { ISD::CTPOP, MVT::v16i16, 9 },
1595 { ISD::CTPOP, MVT::v32i8, 6 },
1596 { ISD::CTTZ, MVT::v4i64, 10 },
1597 { ISD::CTTZ, MVT::v8i32, 14 },
1598 { ISD::CTTZ, MVT::v16i16, 12 },
1599 { ISD::CTTZ, MVT::v32i8, 9 },
1600 { ISD::FSQRT, MVT::f32, 7 }, // Haswell from http://www.agner.org/
1601 { ISD::FSQRT, MVT::v4f32, 7 }, // Haswell from http://www.agner.org/
1602 { ISD::FSQRT, MVT::v8f32, 14 }, // Haswell from http://www.agner.org/
1603 { ISD::FSQRT, MVT::f64, 14 }, // Haswell from http://www.agner.org/
1604 { ISD::FSQRT, MVT::v2f64, 14 }, // Haswell from http://www.agner.org/
1605 { ISD::FSQRT, MVT::v4f64, 28 }, // Haswell from http://www.agner.org/
1606 };
1607 static const CostTblEntry AVX1CostTbl[] = {
1608 { ISD::BITREVERSE, MVT::v4i64, 12 }, // 2 x 128-bit Op + extract/insert
1609 { ISD::BITREVERSE, MVT::v8i32, 12 }, // 2 x 128-bit Op + extract/insert
1610 { ISD::BITREVERSE, MVT::v16i16, 12 }, // 2 x 128-bit Op + extract/insert
1611 { ISD::BITREVERSE, MVT::v32i8, 12 }, // 2 x 128-bit Op + extract/insert
1612 { ISD::BSWAP, MVT::v4i64, 4 },
1613 { ISD::BSWAP, MVT::v8i32, 4 },
1614 { ISD::BSWAP, MVT::v16i16, 4 },
1615 { ISD::CTLZ, MVT::v4i64, 48 }, // 2 x 128-bit Op + extract/insert
1616 { ISD::CTLZ, MVT::v8i32, 38 }, // 2 x 128-bit Op + extract/insert
1617 { ISD::CTLZ, MVT::v16i16, 30 }, // 2 x 128-bit Op + extract/insert
1618 { ISD::CTLZ, MVT::v32i8, 20 }, // 2 x 128-bit Op + extract/insert
1619 { ISD::CTPOP, MVT::v4i64, 16 }, // 2 x 128-bit Op + extract/insert
1620 { ISD::CTPOP, MVT::v8i32, 24 }, // 2 x 128-bit Op + extract/insert
1621 { ISD::CTPOP, MVT::v16i16, 20 }, // 2 x 128-bit Op + extract/insert
1622 { ISD::CTPOP, MVT::v32i8, 14 }, // 2 x 128-bit Op + extract/insert
1623 { ISD::CTTZ, MVT::v4i64, 22 }, // 2 x 128-bit Op + extract/insert
1624 { ISD::CTTZ, MVT::v8i32, 30 }, // 2 x 128-bit Op + extract/insert
1625 { ISD::CTTZ, MVT::v16i16, 26 }, // 2 x 128-bit Op + extract/insert
1626 { ISD::CTTZ, MVT::v32i8, 20 }, // 2 x 128-bit Op + extract/insert
1627 { ISD::FSQRT, MVT::f32, 14 }, // SNB from http://www.agner.org/
1628 { ISD::FSQRT, MVT::v4f32, 14 }, // SNB from http://www.agner.org/
1629 { ISD::FSQRT, MVT::v8f32, 28 }, // SNB from http://www.agner.org/
1630 { ISD::FSQRT, MVT::f64, 21 }, // SNB from http://www.agner.org/
1631 { ISD::FSQRT, MVT::v2f64, 21 }, // SNB from http://www.agner.org/
1632 { ISD::FSQRT, MVT::v4f64, 43 }, // SNB from http://www.agner.org/
1633 };
1634 static const CostTblEntry SSE42CostTbl[] = {
1635 { ISD::FSQRT, MVT::f32, 18 }, // Nehalem from http://www.agner.org/
1636 { ISD::FSQRT, MVT::v4f32, 18 }, // Nehalem from http://www.agner.org/
1637 };
1638 static const CostTblEntry SSSE3CostTbl[] = {
1639 { ISD::BITREVERSE, MVT::v2i64, 5 },
1640 { ISD::BITREVERSE, MVT::v4i32, 5 },
1641 { ISD::BITREVERSE, MVT::v8i16, 5 },
1642 { ISD::BITREVERSE, MVT::v16i8, 5 },
1643 { ISD::BSWAP, MVT::v2i64, 1 },
1644 { ISD::BSWAP, MVT::v4i32, 1 },
1645 { ISD::BSWAP, MVT::v8i16, 1 },
1646 { ISD::CTLZ, MVT::v2i64, 23 },
1647 { ISD::CTLZ, MVT::v4i32, 18 },
1648 { ISD::CTLZ, MVT::v8i16, 14 },
1649 { ISD::CTLZ, MVT::v16i8, 9 },
1650 { ISD::CTPOP, MVT::v2i64, 7 },
1651 { ISD::CTPOP, MVT::v4i32, 11 },
1652 { ISD::CTPOP, MVT::v8i16, 9 },
1653 { ISD::CTPOP, MVT::v16i8, 6 },
1654 { ISD::CTTZ, MVT::v2i64, 10 },
1655 { ISD::CTTZ, MVT::v4i32, 14 },
1656 { ISD::CTTZ, MVT::v8i16, 12 },
1657 { ISD::CTTZ, MVT::v16i8, 9 }
1658 };
1659 static const CostTblEntry SSE2CostTbl[] = {
1660 { ISD::BITREVERSE, MVT::v2i64, 29 },
1661 { ISD::BITREVERSE, MVT::v4i32, 27 },
1662 { ISD::BITREVERSE, MVT::v8i16, 27 },
1663 { ISD::BITREVERSE, MVT::v16i8, 20 },
1664 { ISD::BSWAP, MVT::v2i64, 7 },
1665 { ISD::BSWAP, MVT::v4i32, 7 },
1666 { ISD::BSWAP, MVT::v8i16, 7 },
1667 { ISD::CTLZ, MVT::v2i64, 25 },
1668 { ISD::CTLZ, MVT::v4i32, 26 },
1669 { ISD::CTLZ, MVT::v8i16, 20 },
1670 { ISD::CTLZ, MVT::v16i8, 17 },
1671 { ISD::CTPOP, MVT::v2i64, 12 },
1672 { ISD::CTPOP, MVT::v4i32, 15 },
1673 { ISD::CTPOP, MVT::v8i16, 13 },
1674 { ISD::CTPOP, MVT::v16i8, 10 },
1675 { ISD::CTTZ, MVT::v2i64, 14 },
1676 { ISD::CTTZ, MVT::v4i32, 18 },
1677 { ISD::CTTZ, MVT::v8i16, 16 },
1678 { ISD::CTTZ, MVT::v16i8, 13 },
1679 { ISD::FSQRT, MVT::f64, 32 }, // Nehalem from http://www.agner.org/
1680 { ISD::FSQRT, MVT::v2f64, 32 }, // Nehalem from http://www.agner.org/
1681 };
1682 static const CostTblEntry SSE1CostTbl[] = {
1683 { ISD::FSQRT, MVT::f32, 28 }, // Pentium III from http://www.agner.org/
1684 { ISD::FSQRT, MVT::v4f32, 56 }, // Pentium III from http://www.agner.org/
1685 };
1686 static const CostTblEntry X64CostTbl[] = { // 64-bit targets
1687 { ISD::BITREVERSE, MVT::i64, 14 }
1688 };
1689 static const CostTblEntry X86CostTbl[] = { // 32 or 64-bit targets
1690 { ISD::BITREVERSE, MVT::i32, 14 },
1691 { ISD::BITREVERSE, MVT::i16, 14 },
1692 { ISD::BITREVERSE, MVT::i8, 11 }
1693 };
1694
1695 unsigned ISD = ISD::DELETED_NODE;
1696 switch (IID) {
1697 default:
1698 break;
1699 case Intrinsic::bitreverse:
1700 ISD = ISD::BITREVERSE;
1701 break;
1702 case Intrinsic::bswap:
1703 ISD = ISD::BSWAP;
1704 break;
1705 case Intrinsic::ctlz:
1706 ISD = ISD::CTLZ;
1707 break;
1708 case Intrinsic::ctpop:
1709 ISD = ISD::CTPOP;
1710 break;
1711 case Intrinsic::cttz:
1712 ISD = ISD::CTTZ;
1713 break;
1714 case Intrinsic::sqrt:
1715 ISD = ISD::FSQRT;
1716 break;
1717 }
1718
1719 // Legalize the type.
1720 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, RetTy);
1721 MVT MTy = LT.second;
1722
1723 // Attempt to lookup cost.
1724 if (ST->hasCDI())
1725 if (const auto *Entry = CostTableLookup(AVX512CDCostTbl, ISD, MTy))
1726 return LT.first * Entry->Cost;
1727
1728 if (ST->hasBWI())
1729 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy))
1730 return LT.first * Entry->Cost;
1731
1732 if (ST->hasAVX512())
1733 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy))
1734 return LT.first * Entry->Cost;
1735
1736 if (ST->hasXOP())
1737 if (const auto *Entry = CostTableLookup(XOPCostTbl, ISD, MTy))
1738 return LT.first * Entry->Cost;
1739
1740 if (ST->hasAVX2())
1741 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy))
1742 return LT.first * Entry->Cost;
1743
1744 if (ST->hasAVX())
1745 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy))
1746 return LT.first * Entry->Cost;
1747
1748 if (ST->hasSSE42())
1749 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy))
1750 return LT.first * Entry->Cost;
1751
1752 if (ST->hasSSSE3())
1753 if (const auto *Entry = CostTableLookup(SSSE3CostTbl, ISD, MTy))
1754 return LT.first * Entry->Cost;
1755
1756 if (ST->hasSSE2())
1757 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy))
1758 return LT.first * Entry->Cost;
1759
1760 if (ST->hasSSE1())
1761 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy))
1762 return LT.first * Entry->Cost;
1763
1764 if (ST->is64Bit())
1765 if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, MTy))
1766 return LT.first * Entry->Cost;
1767
1768 if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, MTy))
1769 return LT.first * Entry->Cost;
1770
1771 return BaseT::getIntrinsicInstrCost(IID, RetTy, Tys, FMF, ScalarizationCostPassed);
1772}
1773
1774int X86TTIImpl::getIntrinsicInstrCost(Intrinsic::ID IID, Type *RetTy,
1775 ArrayRef<Value *> Args, FastMathFlags FMF, unsigned VF) {
1776 return BaseT::getIntrinsicInstrCost(IID, RetTy, Args, FMF, VF);
1777}
1778
1779int X86TTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index) {
1780 assert(Val->isVectorTy() && "This must be a vector type")((Val->isVectorTy() && "This must be a vector type"
) ? static_cast<void> (0) : __assert_fail ("Val->isVectorTy() && \"This must be a vector type\""
, "/build/llvm-toolchain-snapshot-6.0~svn318211/lib/Target/X86/X86TargetTransformInfo.cpp"
, 1780, __PRETTY_FUNCTION__))
;
1781
1782 Type *ScalarType = Val->getScalarType();
1783
1784 if (Index != -1U) {
1785 // Legalize the type.
1786 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Val);
1787
1788 // This type is legalized to a scalar type.
1789 if (!LT.second.isVector())
1790 return 0;
1791
1792 // The type may be split. Normalize the index to the new type.
1793 unsigned Width = LT.second.getVectorNumElements();
1794 Index = Index % Width;
1795
1796 // Floating point scalars are already located in index #0.
1797 if (ScalarType->isFloatingPointTy() && Index == 0)
1798 return 0;
1799 }
1800
1801 // Add to the base cost if we know that the extracted element of a vector is
1802 // destined to be moved to and used in the integer register file.
1803 int RegisterFileMoveCost = 0;
1804 if (Opcode == Instruction::ExtractElement && ScalarType->isPointerTy())
1805 RegisterFileMoveCost = 1;
1806
1807 return BaseT::getVectorInstrCost(Opcode, Val, Index) + RegisterFileMoveCost;
1808}
1809
1810int X86TTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment,
1811 unsigned AddressSpace, const Instruction *I) {
1812 // Handle non-power-of-two vectors such as <3 x float>
1813 if (VectorType *VTy = dyn_cast<VectorType>(Src)) {
1814 unsigned NumElem = VTy->getVectorNumElements();
1815
1816 // Handle a few common cases:
1817 // <3 x float>
1818 if (NumElem == 3 && VTy->getScalarSizeInBits() == 32)
1819 // Cost = 64 bit store + extract + 32 bit store.
1820 return 3;
1821
1822 // <3 x double>
1823 if (NumElem == 3 && VTy->getScalarSizeInBits() == 64)
1824 // Cost = 128 bit store + unpack + 64 bit store.
1825 return 3;
1826
1827 // Assume that all other non-power-of-two numbers are scalarized.
1828 if (!isPowerOf2_32(NumElem)) {
1829 int Cost = BaseT::getMemoryOpCost(Opcode, VTy->getScalarType(), Alignment,
1830 AddressSpace);
1831 int SplitCost = getScalarizationOverhead(Src, Opcode == Instruction::Load,
1832 Opcode == Instruction::Store);
1833 return NumElem * Cost + SplitCost;
1834 }
1835 }
1836
1837 // Legalize the type.
1838 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Src);
1839 assert((Opcode == Instruction::Load || Opcode == Instruction::Store) &&(((Opcode == Instruction::Load || Opcode == Instruction::Store
) && "Invalid Opcode") ? static_cast<void> (0) :
__assert_fail ("(Opcode == Instruction::Load || Opcode == Instruction::Store) && \"Invalid Opcode\""
, "/build/llvm-toolchain-snapshot-6.0~svn318211/lib/Target/X86/X86TargetTransformInfo.cpp"
, 1840, __PRETTY_FUNCTION__))
1840 "Invalid Opcode")(((Opcode == Instruction::Load || Opcode == Instruction::Store
) && "Invalid Opcode") ? static_cast<void> (0) :
__assert_fail ("(Opcode == Instruction::Load || Opcode == Instruction::Store) && \"Invalid Opcode\""
, "/build/llvm-toolchain-snapshot-6.0~svn318211/lib/Target/X86/X86TargetTransformInfo.cpp"
, 1840, __PRETTY_FUNCTION__))
;
1841
1842 // Each load/store unit costs 1.
1843 int Cost = LT.first * 1;
1844
1845 // This isn't exactly right. We're using slow unaligned 32-byte accesses as a
1846 // proxy for a double-pumped AVX memory interface such as on Sandybridge.
1847 if (LT.second.getStoreSize() == 32 && ST->isUnalignedMem32Slow())
1848 Cost *= 2;
1849
1850 return Cost;
1851}
1852
1853int X86TTIImpl::getMaskedMemoryOpCost(unsigned Opcode, Type *SrcTy,
1854 unsigned Alignment,
1855 unsigned AddressSpace) {
1856 VectorType *SrcVTy = dyn_cast<VectorType>(SrcTy);
1857 if (!SrcVTy)
1858 // To calculate scalar take the regular cost, without mask
1859 return getMemoryOpCost(Opcode, SrcTy, Alignment, AddressSpace);
1860
1861 unsigned NumElem = SrcVTy->getVectorNumElements();
1862 VectorType *MaskTy =
1863 VectorType::get(Type::getInt8Ty(SrcVTy->getContext()), NumElem);
1864 if ((Opcode == Instruction::Load && !isLegalMaskedLoad(SrcVTy)) ||
1865 (Opcode == Instruction::Store && !isLegalMaskedStore(SrcVTy)) ||
1866 !isPowerOf2_32(NumElem)) {
1867 // Scalarization
1868 int MaskSplitCost = getScalarizationOverhead(MaskTy, false, true);
1869 int ScalarCompareCost = getCmpSelInstrCost(
1870 Instruction::ICmp, Type::getInt8Ty(SrcVTy->getContext()), nullptr);
1871 int BranchCost = getCFInstrCost(Instruction::Br);
1872 int MaskCmpCost = NumElem * (BranchCost + ScalarCompareCost);
1873
1874 int ValueSplitCost = getScalarizationOverhead(
1875 SrcVTy, Opcode == Instruction::Load, Opcode == Instruction::Store);
1876 int MemopCost =
1877 NumElem * BaseT::getMemoryOpCost(Opcode, SrcVTy->getScalarType(),
1878 Alignment, AddressSpace);
1879 return MemopCost + ValueSplitCost + MaskSplitCost + MaskCmpCost;
1880 }
1881
1882 // Legalize the type.
1883 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, SrcVTy);
1884 auto VT = TLI->getValueType(DL, SrcVTy);
1885 int Cost = 0;
1886 if (VT.isSimple() && LT.second != VT.getSimpleVT() &&
1887 LT.second.getVectorNumElements() == NumElem)
1888 // Promotion requires expand/truncate for data and a shuffle for mask.
1889 Cost += getShuffleCost(TTI::SK_Alternate, SrcVTy, 0, nullptr) +
1890 getShuffleCost(TTI::SK_Alternate, MaskTy, 0, nullptr);
1891
1892 else if (LT.second.getVectorNumElements() > NumElem) {
1893 VectorType *NewMaskTy = VectorType::get(MaskTy->getVectorElementType(),
1894 LT.second.getVectorNumElements());
1895 // Expanding requires fill mask with zeroes
1896 Cost += getShuffleCost(TTI::SK_InsertSubvector, NewMaskTy, 0, MaskTy);
1897 }
1898 if (!ST->hasAVX512())
1899 return Cost + LT.first*4; // Each maskmov costs 4
1900
1901 // AVX-512 masked load/store is cheapper
1902 return Cost+LT.first;
1903}
1904
1905int X86TTIImpl::getAddressComputationCost(Type *Ty, ScalarEvolution *SE,
1906 const SCEV *Ptr) {
1907 // Address computations in vectorized code with non-consecutive addresses will
1908 // likely result in more instructions compared to scalar code where the
1909 // computation can more often be merged into the index mode. The resulting
1910 // extra micro-ops can significantly decrease throughput.
1911 unsigned NumVectorInstToHideOverhead = 10;
1912
1913 // Cost modeling of Strided Access Computation is hidden by the indexing
1914 // modes of X86 regardless of the stride value. We dont believe that there
1915 // is a difference between constant strided access in gerenal and constant
1916 // strided value which is less than or equal to 64.
1917 // Even in the case of (loop invariant) stride whose value is not known at
1918 // compile time, the address computation will not incur more than one extra
1919 // ADD instruction.
1920 if (Ty->isVectorTy() && SE) {
1921 if (!BaseT::isStridedAccess(Ptr))
1922 return NumVectorInstToHideOverhead;
1923 if (!BaseT::getConstantStrideStep(SE, Ptr))
1924 return 1;
1925 }
1926
1927 return BaseT::getAddressComputationCost(Ty, SE, Ptr);
1928}
1929
1930int X86TTIImpl::getArithmeticReductionCost(unsigned Opcode, Type *ValTy,
1931 bool IsPairwise) {
1932
1933 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy);
1934
1935 MVT MTy = LT.second;
1936
1937 int ISD = TLI->InstructionOpcodeToISD(Opcode);
1938 assert(ISD && "Invalid opcode")((ISD && "Invalid opcode") ? static_cast<void> (
0) : __assert_fail ("ISD && \"Invalid opcode\"", "/build/llvm-toolchain-snapshot-6.0~svn318211/lib/Target/X86/X86TargetTransformInfo.cpp"
, 1938, __PRETTY_FUNCTION__))
;
1939
1940 // We use the Intel Architecture Code Analyzer(IACA) to measure the throughput
1941 // and make it as the cost.
1942
1943 static const CostTblEntry SSE42CostTblPairWise[] = {
1944 { ISD::FADD, MVT::v2f64, 2 },
1945 { ISD::FADD, MVT::v4f32, 4 },
1946 { ISD::ADD, MVT::v2i64, 2 }, // The data reported by the IACA tool is "1.6".
1947 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.5".
1948 { ISD::ADD, MVT::v8i16, 5 },
1949 };
1950
1951 static const CostTblEntry AVX1CostTblPairWise[] = {
1952 { ISD::FADD, MVT::v4f32, 4 },
1953 { ISD::FADD, MVT::v4f64, 5 },
1954 { ISD::FADD, MVT::v8f32, 7 },
1955 { ISD::ADD, MVT::v2i64, 1 }, // The data reported by the IACA tool is "1.5".
1956 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.5".
1957 { ISD::ADD, MVT::v4i64, 5 }, // The data reported by the IACA tool is "4.8".
1958 { ISD::ADD, MVT::v8i16, 5 },
1959 { ISD::ADD, MVT::v8i32, 5 },
1960 };
1961
1962 static const CostTblEntry SSE42CostTblNoPairWise[] = {
1963 { ISD::FADD, MVT::v2f64, 2 },
1964 { ISD::FADD, MVT::v4f32, 4 },
1965 { ISD::ADD, MVT::v2i64, 2 }, // The data reported by the IACA tool is "1.6".
1966 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.3".
1967 { ISD::ADD, MVT::v8i16, 4 }, // The data reported by the IACA tool is "4.3".
1968 };
1969
1970 static const CostTblEntry AVX1CostTblNoPairWise[] = {
1971 { ISD::FADD, MVT::v4f32, 3 },
1972 { ISD::FADD, MVT::v4f64, 3 },
1973 { ISD::FADD, MVT::v8f32, 4 },
1974 { ISD::ADD, MVT::v2i64, 1 }, // The data reported by the IACA tool is "1.5".
1975 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "2.8".
1976 { ISD::ADD, MVT::v4i64, 3 },
1977 { ISD::ADD, MVT::v8i16, 4 },
1978 { ISD::ADD, MVT::v8i32, 5 },
1979 };
1980
1981 if (IsPairwise) {
1982 if (ST->hasAVX())
1983 if (const auto *Entry = CostTableLookup(AVX1CostTblPairWise, ISD, MTy))
1984 return LT.first * Entry->Cost;
1985
1986 if (ST->hasSSE42())
1987 if (const auto *Entry = CostTableLookup(SSE42CostTblPairWise, ISD, MTy))
1988 return LT.first * Entry->Cost;
1989 } else {
1990 if (ST->hasAVX())
1991 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy))
1992 return LT.first * Entry->Cost;
1993
1994 if (ST->hasSSE42())
1995 if (const auto *Entry = CostTableLookup(SSE42CostTblNoPairWise, ISD, MTy))
1996 return LT.first * Entry->Cost;
1997 }
1998
1999 return BaseT::getArithmeticReductionCost(Opcode, ValTy, IsPairwise);
2000}
2001
2002int X86TTIImpl::getMinMaxReductionCost(Type *ValTy, Type *CondTy,
2003 bool IsPairwise, bool IsUnsigned) {
2004 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy);
2005
2006 MVT MTy = LT.second;
2007
2008 int ISD;
2009 if (ValTy->isIntOrIntVectorTy()) {
2010 ISD = IsUnsigned ? ISD::UMIN : ISD::SMIN;
2011 } else {
2012 assert(ValTy->isFPOrFPVectorTy() &&((ValTy->isFPOrFPVectorTy() && "Expected float point or integer vector type."
) ? static_cast<void> (0) : __assert_fail ("ValTy->isFPOrFPVectorTy() && \"Expected float point or integer vector type.\""
, "/build/llvm-toolchain-snapshot-6.0~svn318211/lib/Target/X86/X86TargetTransformInfo.cpp"
, 2013, __PRETTY_FUNCTION__))
2013 "Expected float point or integer vector type.")((ValTy->isFPOrFPVectorTy() && "Expected float point or integer vector type."
) ? static_cast<void> (0) : __assert_fail ("ValTy->isFPOrFPVectorTy() && \"Expected float point or integer vector type.\""
, "/build/llvm-toolchain-snapshot-6.0~svn318211/lib/Target/X86/X86TargetTransformInfo.cpp"
, 2013, __PRETTY_FUNCTION__))
;
2014 ISD = ISD::FMINNUM;
2015 }
2016
2017 // We use the Intel Architecture Code Analyzer(IACA) to measure the throughput
2018 // and make it as the cost.
2019
2020 static const CostTblEntry SSE42CostTblPairWise[] = {
2021 {ISD::FMINNUM, MVT::v2f64, 3},
2022 {ISD::FMINNUM, MVT::v4f32, 2},
2023 {ISD::SMIN, MVT::v2i64, 7}, // The data reported by the IACA is "6.8"
2024 {ISD::UMIN, MVT::v2i64, 8}, // The data reported by the IACA is "8.6"
2025 {ISD::SMIN, MVT::v4i32, 1}, // The data reported by the IACA is "1.5"
2026 {ISD::UMIN, MVT::v4i32, 2}, // The data reported by the IACA is "1.8"
2027 {ISD::SMIN, MVT::v8i16, 2},
2028 {ISD::UMIN, MVT::v8i16, 2},
2029 };
2030
2031 static const CostTblEntry AVX1CostTblPairWise[] = {
2032 {ISD::FMINNUM, MVT::v4f32, 1},
2033 {ISD::FMINNUM, MVT::v4f64, 1},
2034 {ISD::FMINNUM, MVT::v8f32, 2},
2035 {ISD::SMIN, MVT::v2i64, 3},
2036 {ISD::UMIN, MVT::v2i64, 3},
2037 {ISD::SMIN, MVT::v4i32, 1},
2038 {ISD::UMIN, MVT::v4i32, 1},
2039 {ISD::SMIN, MVT::v8i16, 1},
2040 {ISD::UMIN, MVT::v8i16, 1},
2041 {ISD::SMIN, MVT::v8i32, 3},
2042 {ISD::UMIN, MVT::v8i32, 3},
2043 };
2044
2045 static const CostTblEntry AVX2CostTblPairWise[] = {
2046 {ISD::SMIN, MVT::v4i64, 2},
2047 {ISD::UMIN, MVT::v4i64, 2},
2048 {ISD::SMIN, MVT::v8i32, 1},
2049 {ISD::UMIN, MVT::v8i32, 1},
2050 {ISD::SMIN, MVT::v16i16, 1},
2051 {ISD::UMIN, MVT::v16i16, 1},
2052 {ISD::SMIN, MVT::v32i8, 2},
2053 {ISD::UMIN, MVT::v32i8, 2},
2054 };
2055
2056 static const CostTblEntry AVX512CostTblPairWise[] = {
2057 {ISD::FMINNUM, MVT::v8f64, 1},
2058 {ISD::FMINNUM, MVT::v16f32, 2},
2059 {ISD::SMIN, MVT::v8i64, 2},
2060 {ISD::UMIN, MVT::v8i64, 2},
2061 {ISD::SMIN, MVT::v16i32, 1},
2062 {ISD::UMIN, MVT::v16i32, 1},
2063 };
2064
2065 static const CostTblEntry SSE42CostTblNoPairWise[] = {
2066 {ISD::FMINNUM, MVT::v2f64, 3},
2067 {ISD::FMINNUM, MVT::v4f32, 3},
2068 {ISD::SMIN, MVT::v2i64, 7}, // The data reported by the IACA is "6.8"
2069 {ISD::UMIN, MVT::v2i64, 9}, // The data reported by the IACA is "8.6"
2070 {ISD::SMIN, MVT::v4i32, 1}, // The data reported by the IACA is "1.5"
2071 {ISD::UMIN, MVT::v4i32, 2}, // The data reported by the IACA is "1.8"
2072 {ISD::SMIN, MVT::v8i16, 1}, // The data reported by the IACA is "1.5"
2073 {ISD::UMIN, MVT::v8i16, 2}, // The data reported by the IACA is "1.8"
2074 };
2075
2076 static const CostTblEntry AVX1CostTblNoPairWise[] = {
2077 {ISD::FMINNUM, MVT::v4f32, 1},
2078 {ISD::FMINNUM, MVT::v4f64, 1},
2079 {ISD::FMINNUM, MVT::v8f32, 1},
2080 {ISD::SMIN, MVT::v2i64, 3},
2081 {ISD::UMIN, MVT::v2i64, 3},
2082 {ISD::SMIN, MVT::v4i32, 1},
2083 {ISD::UMIN, MVT::v4i32, 1},
2084 {ISD::SMIN, MVT::v8i16, 1},
2085 {ISD::UMIN, MVT::v8i16, 1},
2086 {ISD::SMIN, MVT::v8i32, 2},
2087 {ISD::UMIN, MVT::v8i32, 2},
2088 };
2089
2090 static const CostTblEntry AVX2CostTblNoPairWise[] = {
2091 {ISD::SMIN, MVT::v4i64, 1},
2092 {ISD::UMIN, MVT::v4i64, 1},
2093 {ISD::SMIN, MVT::v8i32, 1},
2094 {ISD::UMIN, MVT::v8i32, 1},
2095 {ISD::SMIN, MVT::v16i16, 1},
2096 {ISD::UMIN, MVT::v16i16, 1},
2097 {ISD::SMIN, MVT::v32i8, 1},
2098 {ISD::UMIN, MVT::v32i8, 1},
2099 };
2100
2101 static const CostTblEntry AVX512CostTblNoPairWise[] = {
2102 {ISD::FMINNUM, MVT::v8f64, 1},
2103 {ISD::FMINNUM, MVT::v16f32, 2},
2104 {ISD::SMIN, MVT::v8i64, 1},
2105 {ISD::UMIN, MVT::v8i64, 1},
2106 {ISD::SMIN, MVT::v16i32, 1},
2107 {ISD::UMIN, MVT::v16i32, 1},
2108 };
2109
2110 if (IsPairwise) {
2111 if (ST->hasAVX512())
2112 if (const auto *Entry = CostTableLookup(AVX512CostTblPairWise, ISD, MTy))
2113 return LT.first * Entry->Cost;
2114
2115 if (ST->hasAVX2())
2116 if (const auto *Entry = CostTableLookup(AVX2CostTblPairWise, ISD, MTy))
2117 return LT.first * Entry->Cost;
2118
2119 if (ST->hasAVX())
2120 if (const auto *Entry = CostTableLookup(AVX1CostTblPairWise, ISD, MTy))
2121 return LT.first * Entry->Cost;
2122
2123 if (ST->hasSSE42())
2124 if (const auto *Entry = CostTableLookup(SSE42CostTblPairWise, ISD, MTy))
2125 return LT.first * Entry->Cost;
2126 } else {
2127 if (ST->hasAVX512())
2128 if (const auto *Entry =
2129 CostTableLookup(AVX512CostTblNoPairWise, ISD, MTy))
2130 return LT.first * Entry->Cost;
2131
2132 if (ST->hasAVX2())
2133 if (const auto *Entry = CostTableLookup(AVX2CostTblNoPairWise, ISD, MTy))
2134 return LT.first * Entry->Cost;
2135
2136 if (ST->hasAVX())
2137 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy))
2138 return LT.first * Entry->Cost;
2139
2140 if (ST->hasSSE42())
2141 if (const auto *Entry = CostTableLookup(SSE42CostTblNoPairWise, ISD, MTy))
2142 return LT.first * Entry->Cost;
2143 }
2144
2145 return BaseT::getMinMaxReductionCost(ValTy, CondTy, IsPairwise, IsUnsigned);
2146}
2147
2148/// \brief Calculate the cost of materializing a 64-bit value. This helper
2149/// method might only calculate a fraction of a larger immediate. Therefore it
2150/// is valid to return a cost of ZERO.
2151int X86TTIImpl::getIntImmCost(int64_t Val) {
2152 if (Val == 0)
2153 return TTI::TCC_Free;
2154
2155 if (isInt<32>(Val))
2156 return TTI::TCC_Basic;
2157
2158 return 2 * TTI::TCC_Basic;
2159}
2160
2161int X86TTIImpl::getIntImmCost(const APInt &Imm, Type *Ty) {
2162 assert(Ty->isIntegerTy())((Ty->isIntegerTy()) ? static_cast<void> (0) : __assert_fail
("Ty->isIntegerTy()", "/build/llvm-toolchain-snapshot-6.0~svn318211/lib/Target/X86/X86TargetTransformInfo.cpp"
, 2162, __PRETTY_FUNCTION__))
;
2163
2164 unsigned BitSize = Ty->getPrimitiveSizeInBits();
2165 if (BitSize == 0)
2166 return ~0U;
2167
2168 // Never hoist constants larger than 128bit, because this might lead to
2169 // incorrect code generation or assertions in codegen.
2170 // Fixme: Create a cost model for types larger than i128 once the codegen
2171 // issues have been fixed.
2172 if (BitSize > 128)
2173 return TTI::TCC_Free;
2174
2175 if (Imm == 0)
2176 return TTI::TCC_Free;
2177
2178 // Sign-extend all constants to a multiple of 64-bit.
2179 APInt ImmVal = Imm;
2180 if (BitSize & 0x3f)
2181 ImmVal = Imm.sext((BitSize + 63) & ~0x3fU);
2182
2183 // Split the constant into 64-bit chunks and calculate the cost for each
2184 // chunk.
2185 int Cost = 0;
2186 for (unsigned ShiftVal = 0; ShiftVal < BitSize; ShiftVal += 64) {
2187 APInt Tmp = ImmVal.ashr(ShiftVal).sextOrTrunc(64);
2188 int64_t Val = Tmp.getSExtValue();
2189 Cost += getIntImmCost(Val);
2190 }
2191 // We need at least one instruction to materialize the constant.
2192 return std::max(1, Cost);
2193}
2194
2195int X86TTIImpl::getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm,
2196 Type *Ty) {
2197 assert(Ty->isIntegerTy())((Ty->isIntegerTy()) ? static_cast<void> (0) : __assert_fail
("Ty->isIntegerTy()", "/build/llvm-toolchain-snapshot-6.0~svn318211/lib/Target/X86/X86TargetTransformInfo.cpp"
, 2197, __PRETTY_FUNCTION__))
;
2198
2199 unsigned BitSize = Ty->getPrimitiveSizeInBits();
2200 // There is no cost model for constants with a bit size of 0. Return TCC_Free
2201 // here, so that constant hoisting will ignore this constant.
2202 if (BitSize == 0)
2203 return TTI::TCC_Free;
2204
2205 unsigned ImmIdx = ~0U;
2206 switch (Opcode) {
2207 default:
2208 return TTI::TCC_Free;
2209 case Instruction::GetElementPtr:
2210 // Always hoist the base address of a GetElementPtr. This prevents the
2211 // creation of new constants for every base constant that gets constant
2212 // folded with the offset.
2213 if (Idx == 0)
2214 return 2 * TTI::TCC_Basic;
2215 return TTI::TCC_Free;
2216 case Instruction::Store:
2217 ImmIdx = 0;
2218 break;
2219 case Instruction::ICmp:
2220 // This is an imperfect hack to prevent constant hoisting of
2221 // compares that might be trying to check if a 64-bit value fits in
2222 // 32-bits. The backend can optimize these cases using a right shift by 32.
2223 // Ideally we would check the compare predicate here. There also other
2224 // similar immediates the backend can use shifts for.
2225 if (Idx == 1 && Imm.getBitWidth() == 64) {
2226 uint64_t ImmVal = Imm.getZExtValue();
2227 if (ImmVal == 0x100000000ULL || ImmVal == 0xffffffff)
2228 return TTI::TCC_Free;
2229 }
2230 ImmIdx = 1;
2231 break;
2232 case Instruction::And:
2233 // We support 64-bit ANDs with immediates with 32-bits of leading zeroes
2234 // by using a 32-bit operation with implicit zero extension. Detect such
2235 // immediates here as the normal path expects bit 31 to be sign extended.
2236 if (Idx == 1 && Imm.getBitWidth() == 64 && isUInt<32>(Imm.getZExtValue()))
2237 return TTI::TCC_Free;
2238 LLVM_FALLTHROUGH[[clang::fallthrough]];
2239 case Instruction::Add:
2240 case Instruction::Sub:
2241 case Instruction::Mul:
2242 case Instruction::UDiv:
2243 case Instruction::SDiv:
2244 case Instruction::URem:
2245 case Instruction::SRem:
2246 case Instruction::Or:
2247 case Instruction::Xor:
2248 ImmIdx = 1;
2249 break;
2250 // Always return TCC_Free for the shift value of a shift instruction.
2251 case Instruction::Shl:
2252 case Instruction::LShr:
2253 case Instruction::AShr:
2254 if (Idx == 1)
2255 return TTI::TCC_Free;
2256 break;
2257 case Instruction::Trunc:
2258 case Instruction::ZExt:
2259 case Instruction::SExt:
2260 case Instruction::IntToPtr:
2261 case Instruction::PtrToInt:
2262 case Instruction::BitCast:
2263 case Instruction::PHI:
2264 case Instruction::Call:
2265 case Instruction::Select:
2266 case Instruction::Ret:
2267 case Instruction::Load:
2268 break;
2269 }
2270
2271 if (Idx == ImmIdx) {
2272 int NumConstants = (BitSize + 63) / 64;
2273 int Cost = X86TTIImpl::getIntImmCost(Imm, Ty);
2274 return (Cost <= NumConstants * TTI::TCC_Basic)
2275 ? static_cast<int>(TTI::TCC_Free)
2276 : Cost;
2277 }
2278
2279 return X86TTIImpl::getIntImmCost(Imm, Ty);
2280}
2281
2282int X86TTIImpl::getIntImmCost(Intrinsic::ID IID, unsigned Idx, const APInt &Imm,
2283 Type *Ty) {
2284 assert(Ty->isIntegerTy())((Ty->isIntegerTy()) ? static_cast<void> (0) : __assert_fail
("Ty->isIntegerTy()", "/build/llvm-toolchain-snapshot-6.0~svn318211/lib/Target/X86/X86TargetTransformInfo.cpp"
, 2284, __PRETTY_FUNCTION__))
;
2285
2286 unsigned BitSize = Ty->getPrimitiveSizeInBits();
2287 // There is no cost model for constants with a bit size of 0. Return TCC_Free
2288 // here, so that constant hoisting will ignore this constant.
2289 if (BitSize == 0)
2290 return TTI::TCC_Free;
2291
2292 switch (IID) {
2293 default:
2294 return TTI::TCC_Free;
2295 case Intrinsic::sadd_with_overflow:
2296 case Intrinsic::uadd_with_overflow:
2297 case Intrinsic::ssub_with_overflow:
2298 case Intrinsic::usub_with_overflow:
2299 case Intrinsic::smul_with_overflow:
2300 case Intrinsic::umul_with_overflow:
2301 if ((Idx == 1) && Imm.getBitWidth() <= 64 && isInt<32>(Imm.getSExtValue()))
2302 return TTI::TCC_Free;
2303 break;
2304 case Intrinsic::experimental_stackmap:
2305 if ((Idx < 2) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue())))
2306 return TTI::TCC_Free;
2307 break;
2308 case Intrinsic::experimental_patchpoint_void:
2309 case Intrinsic::experimental_patchpoint_i64:
2310 if ((Idx < 4) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue())))
2311 return TTI::TCC_Free;
2312 break;
2313 }
2314 return X86TTIImpl::getIntImmCost(Imm, Ty);
2315}
2316
2317unsigned X86TTIImpl::getUserCost(const User *U,
2318 ArrayRef<const Value *> Operands) {
2319 if (isa<StoreInst>(U)) {
1
Taking false branch
2320 Value *Ptr = U->getOperand(1);
2321 // Store instruction with index and scale costs 2 Uops.
2322 // Check the preceding GEP to identify non-const indices.
2323 if (auto GEP = dyn_cast<GetElementPtrInst>(Ptr)) {
2324 if (!all_of(GEP->indices(), [](Value *V) { return isa<Constant>(V); }))
2325 return TTI::TCC_Basic * 2;
2326 }
2327 return TTI::TCC_Basic;
2328 }
2329 return BaseT::getUserCost(U, Operands);
2
Calling 'TargetTransformInfoImplCRTPBase::getUserCost'
2330}
2331
2332// Return an average cost of Gather / Scatter instruction, maybe improved later
2333int X86TTIImpl::getGSVectorCost(unsigned Opcode, Type *SrcVTy, Value *Ptr,
2334 unsigned Alignment, unsigned AddressSpace) {
2335
2336 assert(isa<VectorType>(SrcVTy) && "Unexpected type in getGSVectorCost")((isa<VectorType>(SrcVTy) && "Unexpected type in getGSVectorCost"
) ? static_cast<void> (0) : __assert_fail ("isa<VectorType>(SrcVTy) && \"Unexpected type in getGSVectorCost\""
, "/build/llvm-toolchain-snapshot-6.0~svn318211/lib/Target/X86/X86TargetTransformInfo.cpp"
, 2336, __PRETTY_FUNCTION__))
;
2337 unsigned VF = SrcVTy->getVectorNumElements();
2338
2339 // Try to reduce index size from 64 bit (default for GEP)
2340 // to 32. It is essential for VF 16. If the index can't be reduced to 32, the
2341 // operation will use 16 x 64 indices which do not fit in a zmm and needs
2342 // to split. Also check that the base pointer is the same for all lanes,
2343 // and that there's at most one variable index.
2344 auto getIndexSizeInBits = [](Value *Ptr, const DataLayout& DL) {
2345 unsigned IndexSize = DL.getPointerSizeInBits();
2346 GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(Ptr);
2347 if (IndexSize < 64 || !GEP)
2348 return IndexSize;
2349
2350 unsigned NumOfVarIndices = 0;
2351 Value *Ptrs = GEP->getPointerOperand();
2352 if (Ptrs->getType()->isVectorTy() && !getSplatValue(Ptrs))
2353 return IndexSize;
2354 for (unsigned i = 1; i < GEP->getNumOperands(); ++i) {
2355 if (isa<Constant>(GEP->getOperand(i)))
2356 continue;
2357 Type *IndxTy = GEP->getOperand(i)->getType();
2358 if (IndxTy->isVectorTy())
2359 IndxTy = IndxTy->getVectorElementType();
2360 if ((IndxTy->getPrimitiveSizeInBits() == 64 &&
2361 !isa<SExtInst>(GEP->getOperand(i))) ||
2362 ++NumOfVarIndices > 1)
2363 return IndexSize; // 64
2364 }
2365 return (unsigned)32;
2366 };
2367
2368
2369 // Trying to reduce IndexSize to 32 bits for vector 16.
2370 // By default the IndexSize is equal to pointer size.
2371 unsigned IndexSize = (VF >= 16) ? getIndexSizeInBits(Ptr, DL) :
2372 DL.getPointerSizeInBits();
2373
2374 Type *IndexVTy = VectorType::get(IntegerType::get(SrcVTy->getContext(),
2375 IndexSize), VF);
2376 std::pair<int, MVT> IdxsLT = TLI->getTypeLegalizationCost(DL, IndexVTy);
2377 std::pair<int, MVT> SrcLT = TLI->getTypeLegalizationCost(DL, SrcVTy);
2378 int SplitFactor = std::max(IdxsLT.first, SrcLT.first);
2379 if (SplitFactor > 1) {
2380 // Handle splitting of vector of pointers
2381 Type *SplitSrcTy = VectorType::get(SrcVTy->getScalarType(), VF / SplitFactor);
2382 return SplitFactor * getGSVectorCost(Opcode, SplitSrcTy, Ptr, Alignment,
2383 AddressSpace);
2384 }
2385
2386 // The gather / scatter cost is given by Intel architects. It is a rough
2387 // number since we are looking at one instruction in a time.
2388 const int GSOverhead = 2;
2389 return GSOverhead + VF * getMemoryOpCost(Opcode, SrcVTy->getScalarType(),
2390 Alignment, AddressSpace);
2391}
2392
2393/// Return the cost of full scalarization of gather / scatter operation.
2394///
2395/// Opcode - Load or Store instruction.
2396/// SrcVTy - The type of the data vector that should be gathered or scattered.
2397/// VariableMask - The mask is non-constant at compile time.
2398/// Alignment - Alignment for one element.
2399/// AddressSpace - pointer[s] address space.
2400///
2401int X86TTIImpl::getGSScalarCost(unsigned Opcode, Type *SrcVTy,
2402 bool VariableMask, unsigned Alignment,
2403 unsigned AddressSpace) {
2404 unsigned VF = SrcVTy->getVectorNumElements();
2405
2406 int MaskUnpackCost = 0;
2407 if (VariableMask) {
2408 VectorType *MaskTy =
2409 VectorType::get(Type::getInt1Ty(SrcVTy->getContext()), VF);
2410 MaskUnpackCost = getScalarizationOverhead(MaskTy, false, true);
2411 int ScalarCompareCost =
2412 getCmpSelInstrCost(Instruction::ICmp, Type::getInt1Ty(SrcVTy->getContext()),
2413 nullptr);
2414 int BranchCost = getCFInstrCost(Instruction::Br);
2415 MaskUnpackCost += VF * (BranchCost + ScalarCompareCost);
2416 }
2417
2418 // The cost of the scalar loads/stores.
2419 int MemoryOpCost = VF * getMemoryOpCost(Opcode, SrcVTy->getScalarType(),
2420 Alignment, AddressSpace);
2421
2422 int InsertExtractCost = 0;
2423 if (Opcode == Instruction::Load)
2424 for (unsigned i = 0; i < VF; ++i)
2425 // Add the cost of inserting each scalar load into the vector
2426 InsertExtractCost +=
2427 getVectorInstrCost(Instruction::InsertElement, SrcVTy, i);
2428 else
2429 for (unsigned i = 0; i < VF; ++i)
2430 // Add the cost of extracting each element out of the data vector
2431 InsertExtractCost +=
2432 getVectorInstrCost(Instruction::ExtractElement, SrcVTy, i);
2433
2434 return MemoryOpCost + MaskUnpackCost + InsertExtractCost;
2435}
2436
2437/// Calculate the cost of Gather / Scatter operation
2438int X86TTIImpl::getGatherScatterOpCost(unsigned Opcode, Type *SrcVTy,
2439 Value *Ptr, bool VariableMask,
2440 unsigned Alignment) {
2441 assert(SrcVTy->isVectorTy() && "Unexpected data type for Gather/Scatter")((SrcVTy->isVectorTy() && "Unexpected data type for Gather/Scatter"
) ? static_cast<void> (0) : __assert_fail ("SrcVTy->isVectorTy() && \"Unexpected data type for Gather/Scatter\""
, "/build/llvm-toolchain-snapshot-6.0~svn318211/lib/Target/X86/X86TargetTransformInfo.cpp"
, 2441, __PRETTY_FUNCTION__))
;
2442 unsigned VF = SrcVTy->getVectorNumElements();
2443 PointerType *PtrTy = dyn_cast<PointerType>(Ptr->getType());
2444 if (!PtrTy && Ptr->getType()->isVectorTy())
2445 PtrTy = dyn_cast<PointerType>(Ptr->getType()->getVectorElementType());
2446 assert(PtrTy && "Unexpected type for Ptr argument")((PtrTy && "Unexpected type for Ptr argument") ? static_cast
<void> (0) : __assert_fail ("PtrTy && \"Unexpected type for Ptr argument\""
, "/build/llvm-toolchain-snapshot-6.0~svn318211/lib/Target/X86/X86TargetTransformInfo.cpp"
, 2446, __PRETTY_FUNCTION__))
;
2447 unsigned AddressSpace = PtrTy->getAddressSpace();
2448
2449 bool Scalarize = false;
2450 if ((Opcode == Instruction::Load && !isLegalMaskedGather(SrcVTy)) ||
2451 (Opcode == Instruction::Store && !isLegalMaskedScatter(SrcVTy)))
2452 Scalarize = true;
2453 // Gather / Scatter for vector 2 is not profitable on KNL / SKX
2454 // Vector-4 of gather/scatter instruction does not exist on KNL.
2455 // We can extend it to 8 elements, but zeroing upper bits of
2456 // the mask vector will add more instructions. Right now we give the scalar
2457 // cost of vector-4 for KNL. TODO: Check, maybe the gather/scatter instruction
2458 // is better in the VariableMask case.
2459 if (VF == 2 || (VF == 4 && !ST->hasVLX()))
2460 Scalarize = true;
2461
2462 if (Scalarize)
2463 return getGSScalarCost(Opcode, SrcVTy, VariableMask, Alignment,
2464 AddressSpace);
2465
2466 return getGSVectorCost(Opcode, SrcVTy, Ptr, Alignment, AddressSpace);
2467}
2468
2469bool X86TTIImpl::isLSRCostLess(TargetTransformInfo::LSRCost &C1,
2470 TargetTransformInfo::LSRCost &C2) {
2471 // X86 specific here are "instruction number 1st priority".
2472 return std::tie(C1.Insns, C1.NumRegs, C1.AddRecCost,
2473 C1.NumIVMuls, C1.NumBaseAdds,
2474 C1.ScaleCost, C1.ImmCost, C1.SetupCost) <
2475 std::tie(C2.Insns, C2.NumRegs, C2.AddRecCost,
2476 C2.NumIVMuls, C2.NumBaseAdds,
2477 C2.ScaleCost, C2.ImmCost, C2.SetupCost);
2478}
2479
2480bool X86TTIImpl::isLegalMaskedLoad(Type *DataTy) {
2481 Type *ScalarTy = DataTy->getScalarType();
2482 int DataWidth = isa<PointerType>(ScalarTy) ?
2483 DL.getPointerSizeInBits() : ScalarTy->getPrimitiveSizeInBits();
2484
2485 return ((DataWidth == 32 || DataWidth == 64) && ST->hasAVX()) ||
2486 ((DataWidth == 8 || DataWidth == 16) && ST->hasBWI());
2487}
2488
2489bool X86TTIImpl::isLegalMaskedStore(Type *DataType) {
2490 return isLegalMaskedLoad(DataType);
2491}
2492
2493bool X86TTIImpl::isLegalMaskedGather(Type *DataTy) {
2494 // This function is called now in two cases: from the Loop Vectorizer
2495 // and from the Scalarizer.
2496 // When the Loop Vectorizer asks about legality of the feature,
2497 // the vectorization factor is not calculated yet. The Loop Vectorizer
2498 // sends a scalar type and the decision is based on the width of the
2499 // scalar element.
2500 // Later on, the cost model will estimate usage this intrinsic based on
2501 // the vector type.
2502 // The Scalarizer asks again about legality. It sends a vector type.
2503 // In this case we can reject non-power-of-2 vectors.
2504 if (isa<VectorType>(DataTy) && !isPowerOf2_32(DataTy->getVectorNumElements()))
2505 return false;
2506 Type *ScalarTy = DataTy->getScalarType();
2507 int DataWidth = isa<PointerType>(ScalarTy) ?
2508 DL.getPointerSizeInBits() : ScalarTy->getPrimitiveSizeInBits();
2509
2510 // AVX-512 allows gather and scatter
2511 return (DataWidth == 32 || DataWidth == 64) && ST->hasAVX512();
2512}
2513
2514bool X86TTIImpl::isLegalMaskedScatter(Type *DataType) {
2515 return isLegalMaskedGather(DataType);
2516}
2517
2518bool X86TTIImpl::hasDivRemOp(Type *DataType, bool IsSigned) {
2519 EVT VT = TLI->getValueType(DL, DataType);
2520 return TLI->isOperationLegal(IsSigned ? ISD::SDIVREM : ISD::UDIVREM, VT);
2521}
2522
2523bool X86TTIImpl::areInlineCompatible(const Function *Caller,
2524 const Function *Callee) const {
2525 const TargetMachine &TM = getTLI()->getTargetMachine();
2526
2527 // Work this as a subsetting of subtarget features.
2528 const FeatureBitset &CallerBits =
2529 TM.getSubtargetImpl(*Caller)->getFeatureBits();
2530 const FeatureBitset &CalleeBits =
2531 TM.getSubtargetImpl(*Callee)->getFeatureBits();
2532
2533 // FIXME: This is likely too limiting as it will include subtarget features
2534 // that we might not care about for inlining, but it is conservatively
2535 // correct.
2536 return (CallerBits & CalleeBits) == CalleeBits;
2537}
2538
2539const X86TTIImpl::TTI::MemCmpExpansionOptions *
2540X86TTIImpl::enableMemCmpExpansion(bool IsZeroCmp) const {
2541 // Only enable vector loads for equality comparison.
2542 // Right now the vector version is not as fast, see #33329.
2543 static const auto ThreeWayOptions = [this]() {
2544 TTI::MemCmpExpansionOptions Options;
2545 if (ST->is64Bit()) {
2546 Options.LoadSizes.push_back(8);
2547 }
2548 Options.LoadSizes.push_back(4);
2549 Options.LoadSizes.push_back(2);
2550 Options.LoadSizes.push_back(1);
2551 return Options;
2552 }();
2553 static const auto EqZeroOptions = [this]() {
2554 TTI::MemCmpExpansionOptions Options;
2555 // TODO: enable AVX512 when the DAG is ready.
2556 // if (ST->hasAVX512()) Options.LoadSizes.push_back(64);
2557 if (ST->hasAVX2()) Options.LoadSizes.push_back(32);
2558 if (ST->hasSSE2()) Options.LoadSizes.push_back(16);
2559 if (ST->is64Bit()) {
2560 Options.LoadSizes.push_back(8);
2561 }
2562 Options.LoadSizes.push_back(4);
2563 Options.LoadSizes.push_back(2);
2564 Options.LoadSizes.push_back(1);
2565 return Options;
2566 }();
2567 return IsZeroCmp ? &EqZeroOptions : &ThreeWayOptions;
2568}
2569
2570bool X86TTIImpl::enableInterleavedAccessVectorization() {
2571 // TODO: We expect this to be beneficial regardless of arch,
2572 // but there are currently some unexplained performance artifacts on Atom.
2573 // As a temporary solution, disable on Atom.
2574 return !(ST->isAtom());
2575}
2576
2577// Get estimation for interleaved load/store operations for AVX2.
2578// \p Factor is the interleaved-access factor (stride) - number of
2579// (interleaved) elements in the group.
2580// \p Indices contains the indices for a strided load: when the
2581// interleaved load has gaps they indicate which elements are used.
2582// If Indices is empty (or if the number of indices is equal to the size
2583// of the interleaved-access as given in \p Factor) the access has no gaps.
2584//
2585// As opposed to AVX-512, AVX2 does not have generic shuffles that allow
2586// computing the cost using a generic formula as a function of generic
2587// shuffles. We therefore use a lookup table instead, filled according to
2588// the instruction sequences that codegen currently generates.
2589int X86TTIImpl::getInterleavedMemoryOpCostAVX2(unsigned Opcode, Type *VecTy,
2590 unsigned Factor,
2591 ArrayRef<unsigned> Indices,
2592 unsigned Alignment,
2593 unsigned AddressSpace) {
2594
2595 // We currently Support only fully-interleaved groups, with no gaps.
2596 // TODO: Support also strided loads (interleaved-groups with gaps).
2597 if (Indices.size() && Indices.size() != Factor)
2598 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices,
2599 Alignment, AddressSpace);
2600
2601 // VecTy for interleave memop is <VF*Factor x Elt>.
2602 // So, for VF=4, Interleave Factor = 3, Element type = i32 we have
2603 // VecTy = <12 x i32>.
2604 MVT LegalVT = getTLI()->getTypeLegalizationCost(DL, VecTy).second;
2605
2606 // This function can be called with VecTy=<6xi128>, Factor=3, in which case
2607 // the VF=2, while v2i128 is an unsupported MVT vector type
2608 // (see MachineValueType.h::getVectorVT()).
2609 if (!LegalVT.isVector())
2610 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices,
2611 Alignment, AddressSpace);
2612
2613 unsigned VF = VecTy->getVectorNumElements() / Factor;
2614 Type *ScalarTy = VecTy->getVectorElementType();
2615
2616 // Calculate the number of memory operations (NumOfMemOps), required
2617 // for load/store the VecTy.
2618 unsigned VecTySize = DL.getTypeStoreSize(VecTy);
2619 unsigned LegalVTSize = LegalVT.getStoreSize();
2620 unsigned NumOfMemOps = (VecTySize + LegalVTSize - 1) / LegalVTSize;
2621
2622 // Get the cost of one memory operation.
2623 Type *SingleMemOpTy = VectorType::get(VecTy->getVectorElementType(),
2624 LegalVT.getVectorNumElements());
2625 unsigned MemOpCost =
2626 getMemoryOpCost(Opcode, SingleMemOpTy, Alignment, AddressSpace);
2627
2628 VectorType *VT = VectorType::get(ScalarTy, VF);
2629 EVT ETy = TLI->getValueType(DL, VT);
2630 if (!ETy.isSimple())
2631 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices,
2632 Alignment, AddressSpace);
2633
2634 // TODO: Complete for other data-types and strides.
2635 // Each combination of Stride, ElementTy and VF results in a different
2636 // sequence; The cost tables are therefore accessed with:
2637 // Factor (stride) and VectorType=VFxElemType.
2638 // The Cost accounts only for the shuffle sequence;
2639 // The cost of the loads/stores is accounted for separately.
2640 //
2641 static const CostTblEntry AVX2InterleavedLoadTbl[] = {
2642 { 3, MVT::v2i8, 10 }, //(load 6i8 and) deinterleave into 3 x 2i8
2643 { 3, MVT::v4i8, 4 }, //(load 12i8 and) deinterleave into 3 x 4i8
2644 { 3, MVT::v8i8, 9 }, //(load 24i8 and) deinterleave into 3 x 8i8
2645 { 3, MVT::v16i8, 11}, //(load 48i8 and) deinterleave into 3 x 16i8
2646 { 3, MVT::v32i8, 13}, //(load 96i8 and) deinterleave into 3 x 32i8
2647 { 3, MVT::v8f32, 17 }, //(load 24f32 and)deinterleave into 3 x 8f32
2648
2649 { 4, MVT::v2i8, 12 }, //(load 8i8 and) deinterleave into 4 x 2i8
2650 { 4, MVT::v4i8, 4 }, //(load 16i8 and) deinterleave into 4 x 4i8
2651 { 4, MVT::v8i8, 20 }, //(load 32i8 and) deinterleave into 4 x 8i8
2652 { 4, MVT::v16i8, 39 }, //(load 64i8 and) deinterleave into 4 x 16i8
2653 { 4, MVT::v32i8, 80 }, //(load 128i8 and) deinterleave into 4 x 32i8
2654
2655 { 8, MVT::v8f32, 40 } //(load 64f32 and)deinterleave into 8 x 8f32
2656 };
2657
2658 static const CostTblEntry AVX2InterleavedStoreTbl[] = {
2659 { 3, MVT::v2i8, 7 }, //interleave 3 x 2i8 into 6i8 (and store)
2660 { 3, MVT::v4i8, 8 }, //interleave 3 x 4i8 into 12i8 (and store)
2661 { 3, MVT::v8i8, 11 }, //interleave 3 x 8i8 into 24i8 (and store)
2662 { 3, MVT::v16i8, 11 }, //interleave 3 x 16i8 into 48i8 (and store)
2663 { 3, MVT::v32i8, 13 }, //interleave 3 x 32i8 into 96i8 (and store)
2664
2665 { 4, MVT::v2i8, 12 }, //interleave 4 x 2i8 into 8i8 (and store)
2666 { 4, MVT::v4i8, 9 }, //interleave 4 x 4i8 into 16i8 (and store)
2667 { 4, MVT::v8i8, 10 }, //interleave 4 x 8i8 into 32i8 (and store)
2668 { 4, MVT::v16i8, 10 }, //interleave 4 x 16i8 into 64i8 (and store)
2669 { 4, MVT::v32i8, 12 } //interleave 4 x 32i8 into 128i8 (and store)
2670 };
2671
2672 if (Opcode == Instruction::Load) {
2673 if (const auto *Entry =
2674 CostTableLookup(AVX2InterleavedLoadTbl, Factor, ETy.getSimpleVT()))
2675 return NumOfMemOps * MemOpCost + Entry->Cost;
2676 } else {
2677 assert(Opcode == Instruction::Store &&((Opcode == Instruction::Store && "Expected Store Instruction at this point"
) ? static_cast<void> (0) : __assert_fail ("Opcode == Instruction::Store && \"Expected Store Instruction at this point\""
, "/build/llvm-toolchain-snapshot-6.0~svn318211/lib/Target/X86/X86TargetTransformInfo.cpp"
, 2678, __PRETTY_FUNCTION__))
2678 "Expected Store Instruction at this point")((Opcode == Instruction::Store && "Expected Store Instruction at this point"
) ? static_cast<void> (0) : __assert_fail ("Opcode == Instruction::Store && \"Expected Store Instruction at this point\""
, "/build/llvm-toolchain-snapshot-6.0~svn318211/lib/Target/X86/X86TargetTransformInfo.cpp"
, 2678, __PRETTY_FUNCTION__))
;
2679 if (const auto *Entry =
2680 CostTableLookup(AVX2InterleavedStoreTbl, Factor, ETy.getSimpleVT()))
2681 return NumOfMemOps * MemOpCost + Entry->Cost;
2682 }
2683
2684 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices,
2685 Alignment, AddressSpace);
2686}
2687
2688// Get estimation for interleaved load/store operations and strided load.
2689// \p Indices contains indices for strided load.
2690// \p Factor - the factor of interleaving.
2691// AVX-512 provides 3-src shuffles that significantly reduces the cost.
2692int X86TTIImpl::getInterleavedMemoryOpCostAVX512(unsigned Opcode, Type *VecTy,
2693 unsigned Factor,
2694 ArrayRef<unsigned> Indices,
2695 unsigned Alignment,
2696 unsigned AddressSpace) {
2697
2698 // VecTy for interleave memop is <VF*Factor x Elt>.
2699 // So, for VF=4, Interleave Factor = 3, Element type = i32 we have
2700 // VecTy = <12 x i32>.
2701
2702 // Calculate the number of memory operations (NumOfMemOps), required
2703 // for load/store the VecTy.
2704 MVT LegalVT = getTLI()->getTypeLegalizationCost(DL, VecTy).second;
2705 unsigned VecTySize = DL.getTypeStoreSize(VecTy);
2706 unsigned LegalVTSize = LegalVT.getStoreSize();
2707 unsigned NumOfMemOps = (VecTySize + LegalVTSize - 1) / LegalVTSize;
2708
2709 // Get the cost of one memory operation.
2710 Type *SingleMemOpTy = VectorType::get(VecTy->getVectorElementType(),
2711 LegalVT.getVectorNumElements());
2712 unsigned MemOpCost =
2713 getMemoryOpCost(Opcode, SingleMemOpTy, Alignment, AddressSpace);
2714
2715 unsigned VF = VecTy->getVectorNumElements() / Factor;
2716 MVT VT = MVT::getVectorVT(MVT::getVT(VecTy->getScalarType()), VF);
2717
2718 if (Opcode == Instruction::Load) {
2719 // The tables (AVX512InterleavedLoadTbl and AVX512InterleavedStoreTbl)
2720 // contain the cost of the optimized shuffle sequence that the
2721 // X86InterleavedAccess pass will generate.
2722 // The cost of loads and stores are computed separately from the table.
2723
2724 // X86InterleavedAccess support only the following interleaved-access group.
2725 static const CostTblEntry AVX512InterleavedLoadTbl[] = {
2726 {3, MVT::v16i8, 12}, //(load 48i8 and) deinterleave into 3 x 16i8
2727 {3, MVT::v32i8, 14}, //(load 96i8 and) deinterleave into 3 x 32i8
2728 {3, MVT::v64i8, 22}, //(load 96i8 and) deinterleave into 3 x 32i8
2729 };
2730
2731 if (const auto *Entry =
2732 CostTableLookup(AVX512InterleavedLoadTbl, Factor, VT))
2733 return NumOfMemOps * MemOpCost + Entry->Cost;
2734 //If an entry does not exist, fallback to the default implementation.
2735
2736 // Kind of shuffle depends on number of loaded values.
2737 // If we load the entire data in one register, we can use a 1-src shuffle.
2738 // Otherwise, we'll merge 2 sources in each operation.
2739 TTI::ShuffleKind ShuffleKind =
2740 (NumOfMemOps > 1) ? TTI::SK_PermuteTwoSrc : TTI::SK_PermuteSingleSrc;
2741
2742 unsigned ShuffleCost =
2743 getShuffleCost(ShuffleKind, SingleMemOpTy, 0, nullptr);
2744
2745 unsigned NumOfLoadsInInterleaveGrp =
2746 Indices.size() ? Indices.size() : Factor;
2747 Type *ResultTy = VectorType::get(VecTy->getVectorElementType(),
2748 VecTy->getVectorNumElements() / Factor);
2749 unsigned NumOfResults =
2750 getTLI()->getTypeLegalizationCost(DL, ResultTy).first *
2751 NumOfLoadsInInterleaveGrp;
2752
2753 // About a half of the loads may be folded in shuffles when we have only
2754 // one result. If we have more than one result, we do not fold loads at all.
2755 unsigned NumOfUnfoldedLoads =
2756 NumOfResults > 1 ? NumOfMemOps : NumOfMemOps / 2;
2757
2758 // Get a number of shuffle operations per result.
2759 unsigned NumOfShufflesPerResult =
2760 std::max((unsigned)1, (unsigned)(NumOfMemOps - 1));
2761
2762 // The SK_MergeTwoSrc shuffle clobbers one of src operands.
2763 // When we have more than one destination, we need additional instructions
2764 // to keep sources.
2765 unsigned NumOfMoves = 0;
2766 if (NumOfResults > 1 && ShuffleKind == TTI::SK_PermuteTwoSrc)
2767 NumOfMoves = NumOfResults * NumOfShufflesPerResult / 2;
2768
2769 int Cost = NumOfResults * NumOfShufflesPerResult * ShuffleCost +
2770 NumOfUnfoldedLoads * MemOpCost + NumOfMoves;
2771
2772 return Cost;
2773 }
2774
2775 // Store.
2776 assert(Opcode == Instruction::Store &&((Opcode == Instruction::Store && "Expected Store Instruction at this point"
) ? static_cast<void> (0) : __assert_fail ("Opcode == Instruction::Store && \"Expected Store Instruction at this point\""
, "/build/llvm-toolchain-snapshot-6.0~svn318211/lib/Target/X86/X86TargetTransformInfo.cpp"
, 2777, __PRETTY_FUNCTION__))
2777 "Expected Store Instruction at this point")((Opcode == Instruction::Store && "Expected Store Instruction at this point"
) ? static_cast<void> (0) : __assert_fail ("Opcode == Instruction::Store && \"Expected Store Instruction at this point\""
, "/build/llvm-toolchain-snapshot-6.0~svn318211/lib/Target/X86/X86TargetTransformInfo.cpp"
, 2777, __PRETTY_FUNCTION__))
;
2778 // X86InterleavedAccess support only the following interleaved-access group.
2779 static const CostTblEntry AVX512InterleavedStoreTbl[] = {
2780 {3, MVT::v16i8, 12}, // interleave 3 x 16i8 into 48i8 (and store)
2781 {3, MVT::v32i8, 14}, // interleave 3 x 32i8 into 96i8 (and store)
2782 {3, MVT::v64i8, 26}, // interleave 3 x 64i8 into 96i8 (and store)
2783
2784 {4, MVT::v8i8, 10}, // interleave 4 x 8i8 into 32i8 (and store)
2785 {4, MVT::v16i8, 11}, // interleave 4 x 16i8 into 64i8 (and store)
2786 {4, MVT::v32i8, 14}, // interleave 4 x 32i8 into 128i8 (and store)
2787 {4, MVT::v64i8, 24} // interleave 4 x 32i8 into 256i8 (and store)
2788 };
2789
2790 if (const auto *Entry =
2791 CostTableLookup(AVX512InterleavedStoreTbl, Factor, VT))
2792 return NumOfMemOps * MemOpCost + Entry->Cost;
2793 //If an entry does not exist, fallback to the default implementation.
2794
2795 // There is no strided stores meanwhile. And store can't be folded in
2796 // shuffle.
2797 unsigned NumOfSources = Factor; // The number of values to be merged.
2798 unsigned ShuffleCost =
2799 getShuffleCost(TTI::SK_PermuteTwoSrc, SingleMemOpTy, 0, nullptr);
2800 unsigned NumOfShufflesPerStore = NumOfSources - 1;
2801
2802 // The SK_MergeTwoSrc shuffle clobbers one of src operands.
2803 // We need additional instructions to keep sources.
2804 unsigned NumOfMoves = NumOfMemOps * NumOfShufflesPerStore / 2;
2805 int Cost = NumOfMemOps * (MemOpCost + NumOfShufflesPerStore * ShuffleCost) +
2806 NumOfMoves;
2807 return Cost;
2808}
2809
2810int X86TTIImpl::getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy,
2811 unsigned Factor,
2812 ArrayRef<unsigned> Indices,
2813 unsigned Alignment,
2814 unsigned AddressSpace) {
2815 auto isSupportedOnAVX512 = [](Type *VecTy, bool &RequiresBW) {
2816 RequiresBW = false;
2817 Type *EltTy = VecTy->getVectorElementType();
2818 if (EltTy->isFloatTy() || EltTy->isDoubleTy() || EltTy->isIntegerTy(64) ||
2819 EltTy->isIntegerTy(32) || EltTy->isPointerTy())
2820 return true;
2821 if (EltTy->isIntegerTy(16) || EltTy->isIntegerTy(8)) {
2822 RequiresBW = true;
2823 return true;
2824 }
2825 return false;
2826 };
2827 bool RequiresBW;
2828 bool HasAVX512Solution = isSupportedOnAVX512(VecTy, RequiresBW);
2829 if (ST->hasAVX512() && HasAVX512Solution && (!RequiresBW || ST->hasBWI()))
2830 return getInterleavedMemoryOpCostAVX512(Opcode, VecTy, Factor, Indices,
2831 Alignment, AddressSpace);
2832 if (ST->hasAVX2())
2833 return getInterleavedMemoryOpCostAVX2(Opcode, VecTy, Factor, Indices,
2834 Alignment, AddressSpace);
2835
2836 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices,
2837 Alignment, AddressSpace);
2838}

/build/llvm-toolchain-snapshot-6.0~svn318211/include/llvm/Analysis/TargetTransformInfoImpl.h

1//===- TargetTransformInfoImpl.h --------------------------------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9/// \file
10/// This file provides helpers for the implementation of
11/// a TargetTransformInfo-conforming class.
12///
13//===----------------------------------------------------------------------===//
14
15#ifndef LLVM_ANALYSIS_TARGETTRANSFORMINFOIMPL_H
16#define LLVM_ANALYSIS_TARGETTRANSFORMINFOIMPL_H
17
18#include "llvm/Analysis/ScalarEvolutionExpressions.h"
19#include "llvm/Analysis/TargetTransformInfo.h"
20#include "llvm/Analysis/VectorUtils.h"
21#include "llvm/IR/CallSite.h"
22#include "llvm/IR/DataLayout.h"
23#include "llvm/IR/Function.h"
24#include "llvm/IR/GetElementPtrTypeIterator.h"
25#include "llvm/IR/Operator.h"
26#include "llvm/IR/Type.h"
27
28namespace llvm {
29
30/// \brief Base class for use as a mix-in that aids implementing
31/// a TargetTransformInfo-compatible class.
32class TargetTransformInfoImplBase {
33protected:
34 typedef TargetTransformInfo TTI;
35
36 const DataLayout &DL;
37
38 explicit TargetTransformInfoImplBase(const DataLayout &DL) : DL(DL) {}
39
40public:
41 // Provide value semantics. MSVC requires that we spell all of these out.
42 TargetTransformInfoImplBase(const TargetTransformInfoImplBase &Arg)
43 : DL(Arg.DL) {}
44 TargetTransformInfoImplBase(TargetTransformInfoImplBase &&Arg) : DL(Arg.DL) {}
45
46 const DataLayout &getDataLayout() const { return DL; }
47
48 unsigned getOperationCost(unsigned Opcode, Type *Ty, Type *OpTy) {
49 switch (Opcode) {
16
Control jumps to 'case IntToPtr:' at line 74
50 default:
51 // By default, just classify everything as 'basic'.
52 return TTI::TCC_Basic;
53
54 case Instruction::GetElementPtr:
55 llvm_unreachable("Use getGEPCost for GEP operations!")::llvm::llvm_unreachable_internal("Use getGEPCost for GEP operations!"
, "/build/llvm-toolchain-snapshot-6.0~svn318211/include/llvm/Analysis/TargetTransformInfoImpl.h"
, 55)
;
56
57 case Instruction::BitCast:
58 assert(OpTy && "Cast instructions must provide the operand type")((OpTy && "Cast instructions must provide the operand type"
) ? static_cast<void> (0) : __assert_fail ("OpTy && \"Cast instructions must provide the operand type\""
, "/build/llvm-toolchain-snapshot-6.0~svn318211/include/llvm/Analysis/TargetTransformInfoImpl.h"
, 58, __PRETTY_FUNCTION__))
;
59 if (Ty == OpTy || (Ty->isPointerTy() && OpTy->isPointerTy()))
60 // Identity and pointer-to-pointer casts are free.
61 return TTI::TCC_Free;
62
63 // Otherwise, the default basic cost is used.
64 return TTI::TCC_Basic;
65
66 case Instruction::FDiv:
67 case Instruction::FRem:
68 case Instruction::SDiv:
69 case Instruction::SRem:
70 case Instruction::UDiv:
71 case Instruction::URem:
72 return TTI::TCC_Expensive;
73
74 case Instruction::IntToPtr: {
75 // An inttoptr cast is free so long as the input is a legal integer type
76 // which doesn't contain values outside the range of a pointer.
77 unsigned OpSize = OpTy->getScalarSizeInBits();
17
Called C++ object pointer is null
78 if (DL.isLegalInteger(OpSize) &&
79 OpSize <= DL.getPointerTypeSizeInBits(Ty))
80 return TTI::TCC_Free;
81
82 // Otherwise it's not a no-op.
83 return TTI::TCC_Basic;
84 }
85 case Instruction::PtrToInt: {
86 // A ptrtoint cast is free so long as the result is large enough to store
87 // the pointer, and a legal integer type.
88 unsigned DestSize = Ty->getScalarSizeInBits();
89 if (DL.isLegalInteger(DestSize) &&
90 DestSize >= DL.getPointerTypeSizeInBits(OpTy))
91 return TTI::TCC_Free;
92
93 // Otherwise it's not a no-op.
94 return TTI::TCC_Basic;
95 }
96 case Instruction::Trunc:
97 // trunc to a native type is free (assuming the target has compare and
98 // shift-right of the same width).
99 if (DL.isLegalInteger(DL.getTypeSizeInBits(Ty)))
100 return TTI::TCC_Free;
101
102 return TTI::TCC_Basic;
103 }
104 }
105
106 int getGEPCost(Type *PointeeType, const Value *Ptr,
107 ArrayRef<const Value *> Operands) {
108 // In the basic model, we just assume that all-constant GEPs will be folded
109 // into their uses via addressing modes.
110 for (unsigned Idx = 0, Size = Operands.size(); Idx != Size; ++Idx)
111 if (!isa<Constant>(Operands[Idx]))
112 return TTI::TCC_Basic;
113
114 return TTI::TCC_Free;
115 }
116
117 unsigned getEstimatedNumberOfCaseClusters(const SwitchInst &SI,
118 unsigned &JTSize) {
119 JTSize = 0;
120 return SI.getNumCases();
121 }
122
123 int getExtCost(const Instruction *I, const Value *Src) {
124 return TTI::TCC_Basic;
125 }
126
127 unsigned getCallCost(FunctionType *FTy, int NumArgs) {
128 assert(FTy && "FunctionType must be provided to this routine.")((FTy && "FunctionType must be provided to this routine."
) ? static_cast<void> (0) : __assert_fail ("FTy && \"FunctionType must be provided to this routine.\""
, "/build/llvm-toolchain-snapshot-6.0~svn318211/include/llvm/Analysis/TargetTransformInfoImpl.h"
, 128, __PRETTY_FUNCTION__))
;
129
130 // The target-independent implementation just measures the size of the
131 // function by approximating that each argument will take on average one
132 // instruction to prepare.
133
134 if (NumArgs < 0)
135 // Set the argument number to the number of explicit arguments in the
136 // function.
137 NumArgs = FTy->getNumParams();
138
139 return TTI::TCC_Basic * (NumArgs + 1);
140 }
141
142 unsigned getInliningThresholdMultiplier() { return 1; }
143
144 unsigned getIntrinsicCost(Intrinsic::ID IID, Type *RetTy,
145 ArrayRef<Type *> ParamTys) {
146 switch (IID) {
147 default:
148 // Intrinsics rarely (if ever) have normal argument setup constraints.
149 // Model them as having a basic instruction cost.
150 // FIXME: This is wrong for libc intrinsics.
151 return TTI::TCC_Basic;
152
153 case Intrinsic::annotation:
154 case Intrinsic::assume:
155 case Intrinsic::sideeffect:
156 case Intrinsic::dbg_declare:
157 case Intrinsic::dbg_value:
158 case Intrinsic::invariant_start:
159 case Intrinsic::invariant_end:
160 case Intrinsic::lifetime_start:
161 case Intrinsic::lifetime_end:
162 case Intrinsic::objectsize:
163 case Intrinsic::ptr_annotation:
164 case Intrinsic::var_annotation:
165 case Intrinsic::experimental_gc_result:
166 case Intrinsic::experimental_gc_relocate:
167 case Intrinsic::coro_alloc:
168 case Intrinsic::coro_begin:
169 case Intrinsic::coro_free:
170 case Intrinsic::coro_end:
171 case Intrinsic::coro_frame:
172 case Intrinsic::coro_size:
173 case Intrinsic::coro_suspend:
174 case Intrinsic::coro_param:
175 case Intrinsic::coro_subfn_addr:
176 // These intrinsics don't actually represent code after lowering.
177 return TTI::TCC_Free;
178 }
179 }
180
181 bool hasBranchDivergence() { return false; }
182
183 bool isSourceOfDivergence(const Value *V) { return false; }
184
185 bool isAlwaysUniform(const Value *V) { return false; }
186
187 unsigned getFlatAddressSpace () {
188 return -1;
189 }
190
191 bool isLoweredToCall(const Function *F) {
192 assert(F && "A concrete function must be provided to this routine.")((F && "A concrete function must be provided to this routine."
) ? static_cast<void> (0) : __assert_fail ("F && \"A concrete function must be provided to this routine.\""
, "/build/llvm-toolchain-snapshot-6.0~svn318211/include/llvm/Analysis/TargetTransformInfoImpl.h"
, 192, __PRETTY_FUNCTION__))
;
193
194 // FIXME: These should almost certainly not be handled here, and instead
195 // handled with the help of TLI or the target itself. This was largely
196 // ported from existing analysis heuristics here so that such refactorings
197 // can take place in the future.
198
199 if (F->isIntrinsic())
200 return false;
201
202 if (F->hasLocalLinkage() || !F->hasName())
203 return true;
204
205 StringRef Name = F->getName();
206
207 // These will all likely lower to a single selection DAG node.
208 if (Name == "copysign" || Name == "copysignf" || Name == "copysignl" ||
209 Name == "fabs" || Name == "fabsf" || Name == "fabsl" || Name == "sin" ||
210 Name == "fmin" || Name == "fminf" || Name == "fminl" ||
211 Name == "fmax" || Name == "fmaxf" || Name == "fmaxl" ||
212 Name == "sinf" || Name == "sinl" || Name == "cos" || Name == "cosf" ||
213 Name == "cosl" || Name == "sqrt" || Name == "sqrtf" || Name == "sqrtl")
214 return false;
215
216 // These are all likely to be optimized into something smaller.
217 if (Name == "pow" || Name == "powf" || Name == "powl" || Name == "exp2" ||
218 Name == "exp2l" || Name == "exp2f" || Name == "floor" ||
219 Name == "floorf" || Name == "ceil" || Name == "round" ||
220 Name == "ffs" || Name == "ffsl" || Name == "abs" || Name == "labs" ||
221 Name == "llabs")
222 return false;
223
224 return true;
225 }
226
227 void getUnrollingPreferences(Loop *, ScalarEvolution &,
228 TTI::UnrollingPreferences &) {}
229
230 bool isLegalAddImmediate(int64_t Imm) { return false; }
231
232 bool isLegalICmpImmediate(int64_t Imm) { return false; }
233
234 bool isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset,
235 bool HasBaseReg, int64_t Scale,
236 unsigned AddrSpace, Instruction *I = nullptr) {
237 // Guess that only reg and reg+reg addressing is allowed. This heuristic is
238 // taken from the implementation of LSR.
239 return !BaseGV && BaseOffset == 0 && (Scale == 0 || Scale == 1);
240 }
241
242 bool isLSRCostLess(TTI::LSRCost &C1, TTI::LSRCost &C2) {
243 return std::tie(C1.NumRegs, C1.AddRecCost, C1.NumIVMuls, C1.NumBaseAdds,
244 C1.ScaleCost, C1.ImmCost, C1.SetupCost) <
245 std::tie(C2.NumRegs, C2.AddRecCost, C2.NumIVMuls, C2.NumBaseAdds,
246 C2.ScaleCost, C2.ImmCost, C2.SetupCost);
247 }
248
249 bool isLegalMaskedStore(Type *DataType) { return false; }
250
251 bool isLegalMaskedLoad(Type *DataType) { return false; }
252
253 bool isLegalMaskedScatter(Type *DataType) { return false; }
254
255 bool isLegalMaskedGather(Type *DataType) { return false; }
256
257 bool hasDivRemOp(Type *DataType, bool IsSigned) { return false; }
258
259 bool hasVolatileVariant(Instruction *I, unsigned AddrSpace) { return false; }
260
261 bool prefersVectorizedAddressing() { return true; }
262
263 int getScalingFactorCost(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset,
264 bool HasBaseReg, int64_t Scale, unsigned AddrSpace) {
265 // Guess that all legal addressing mode are free.
266 if (isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg,
267 Scale, AddrSpace))
268 return 0;
269 return -1;
270 }
271
272 bool LSRWithInstrQueries() { return false; }
273
274 bool isTruncateFree(Type *Ty1, Type *Ty2) { return false; }
275
276 bool isProfitableToHoist(Instruction *I) { return true; }
277
278 bool isTypeLegal(Type *Ty) { return false; }
279
280 unsigned getJumpBufAlignment() { return 0; }
281
282 unsigned getJumpBufSize() { return 0; }
283
284 bool shouldBuildLookupTables() { return true; }
285 bool shouldBuildLookupTablesForConstant(Constant *C) { return true; }
286
287 unsigned getScalarizationOverhead(Type *Ty, bool Insert, bool Extract) {
288 return 0;
289 }
290
291 unsigned getOperandsScalarizationOverhead(ArrayRef<const Value *> Args,
292 unsigned VF) { return 0; }
293
294 bool supportsEfficientVectorElementLoadStore() { return false; }
295
296 bool enableAggressiveInterleaving(bool LoopHasReductions) { return false; }
297
298 const TTI::MemCmpExpansionOptions *enableMemCmpExpansion(
299 bool IsZeroCmp) const {
300 return nullptr;
301 }
302
303 bool enableInterleavedAccessVectorization() { return false; }
304
305 bool isFPVectorizationPotentiallyUnsafe() { return false; }
306
307 bool allowsMisalignedMemoryAccesses(LLVMContext &Context,
308 unsigned BitWidth,
309 unsigned AddressSpace,
310 unsigned Alignment,
311 bool *Fast) { return false; }
312
313 TTI::PopcntSupportKind getPopcntSupport(unsigned IntTyWidthInBit) {
314 return TTI::PSK_Software;
315 }
316
317 bool haveFastSqrt(Type *Ty) { return false; }
318
319 unsigned getFPOpCost(Type *Ty) { return TargetTransformInfo::TCC_Basic; }
320
321 int getIntImmCodeSizeCost(unsigned Opcode, unsigned Idx, const APInt &Imm,
322 Type *Ty) {
323 return 0;
324 }
325
326 unsigned getIntImmCost(const APInt &Imm, Type *Ty) { return TTI::TCC_Basic; }
327
328 unsigned getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm,
329 Type *Ty) {
330 return TTI::TCC_Free;
331 }
332
333 unsigned getIntImmCost(Intrinsic::ID IID, unsigned Idx, const APInt &Imm,
334 Type *Ty) {
335 return TTI::TCC_Free;
336 }
337
338 unsigned getNumberOfRegisters(bool Vector) { return 8; }
339
340 unsigned getRegisterBitWidth(bool Vector) const { return 32; }
341
342 unsigned getMinVectorRegisterBitWidth() { return 128; }
343
344 bool
345 shouldConsiderAddressTypePromotion(const Instruction &I,
346 bool &AllowPromotionWithoutCommonHeader) {
347 AllowPromotionWithoutCommonHeader = false;
348 return false;
349 }
350
351 unsigned getCacheLineSize() { return 0; }
352
353 llvm::Optional<unsigned> getCacheSize(TargetTransformInfo::CacheLevel Level) {
354 switch (Level) {
355 case TargetTransformInfo::CacheLevel::L1D:
356 LLVM_FALLTHROUGH[[clang::fallthrough]];
357 case TargetTransformInfo::CacheLevel::L2D:
358 return llvm::Optional<unsigned>();
359 }
360
361 llvm_unreachable("Unknown TargetTransformInfo::CacheLevel")::llvm::llvm_unreachable_internal("Unknown TargetTransformInfo::CacheLevel"
, "/build/llvm-toolchain-snapshot-6.0~svn318211/include/llvm/Analysis/TargetTransformInfoImpl.h"
, 361)
;
362 }
363
364 llvm::Optional<unsigned> getCacheAssociativity(
365 TargetTransformInfo::CacheLevel Level) {
366 switch (Level) {
367 case TargetTransformInfo::CacheLevel::L1D:
368 LLVM_FALLTHROUGH[[clang::fallthrough]];
369 case TargetTransformInfo::CacheLevel::L2D:
370 return llvm::Optional<unsigned>();
371 }
372
373 llvm_unreachable("Unknown TargetTransformInfo::CacheLevel")::llvm::llvm_unreachable_internal("Unknown TargetTransformInfo::CacheLevel"
, "/build/llvm-toolchain-snapshot-6.0~svn318211/include/llvm/Analysis/TargetTransformInfoImpl.h"
, 373)
;
374 }
375
376 unsigned getPrefetchDistance() { return 0; }
377
378 unsigned getMinPrefetchStride() { return 1; }
379
380 unsigned getMaxPrefetchIterationsAhead() { return UINT_MAX(2147483647 *2U +1U); }
381
382 unsigned getMaxInterleaveFactor(unsigned VF) { return 1; }
383
384 unsigned getArithmeticInstrCost(unsigned Opcode, Type *Ty,
385 TTI::OperandValueKind Opd1Info,
386 TTI::OperandValueKind Opd2Info,
387 TTI::OperandValueProperties Opd1PropInfo,
388 TTI::OperandValueProperties Opd2PropInfo,
389 ArrayRef<const Value *> Args) {
390 return 1;
391 }
392
393 unsigned getShuffleCost(TTI::ShuffleKind Kind, Type *Ty, int Index,
394 Type *SubTp) {
395 return 1;
396 }
397
398 unsigned getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src,
399 const Instruction *I) { return 1; }
400
401 unsigned getExtractWithExtendCost(unsigned Opcode, Type *Dst,
402 VectorType *VecTy, unsigned Index) {
403 return 1;
404 }
405
406 unsigned getCFInstrCost(unsigned Opcode) { return 1; }
407
408 unsigned getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy,
409 const Instruction *I) {
410 return 1;
411 }
412
413 unsigned getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index) {
414 return 1;
415 }
416
417 unsigned getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment,
418 unsigned AddressSpace, const Instruction *I) {
419 return 1;
420 }
421
422 unsigned getMaskedMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment,
423 unsigned AddressSpace) {
424 return 1;
425 }
426
427 unsigned getGatherScatterOpCost(unsigned Opcode, Type *DataTy, Value *Ptr,
428 bool VariableMask,
429 unsigned Alignment) {
430 return 1;
431 }
432
433 unsigned getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy,
434 unsigned Factor,
435 ArrayRef<unsigned> Indices,
436 unsigned Alignment,
437 unsigned AddressSpace) {
438 return 1;
439 }
440
441 unsigned getIntrinsicInstrCost(Intrinsic::ID ID, Type *RetTy,
442 ArrayRef<Type *> Tys, FastMathFlags FMF,
443 unsigned ScalarizationCostPassed) {
444 return 1;
445 }
446 unsigned getIntrinsicInstrCost(Intrinsic::ID ID, Type *RetTy,
447 ArrayRef<Value *> Args, FastMathFlags FMF, unsigned VF) {
448 return 1;
449 }
450
451 unsigned getCallInstrCost(Function *F, Type *RetTy, ArrayRef<Type *> Tys) {
452 return 1;
453 }
454
455 unsigned getNumberOfParts(Type *Tp) { return 0; }
456
457 unsigned getAddressComputationCost(Type *Tp, ScalarEvolution *,
458 const SCEV *) {
459 return 0;
460 }
461
462 unsigned getArithmeticReductionCost(unsigned, Type *, bool) { return 1; }
463
464 unsigned getMinMaxReductionCost(Type *, Type *, bool, bool) { return 1; }
465
466 unsigned getCostOfKeepingLiveOverCall(ArrayRef<Type *> Tys) { return 0; }
467
468 bool getTgtMemIntrinsic(IntrinsicInst *Inst, MemIntrinsicInfo &Info) {
469 return false;
470 }
471
472 unsigned getAtomicMemIntrinsicMaxElementSize() const {
473 // Note for overrides: You must ensure for all element unordered-atomic
474 // memory intrinsics that all power-of-2 element sizes up to, and
475 // including, the return value of this method have a corresponding
476 // runtime lib call. These runtime lib call definitions can be found
477 // in RuntimeLibcalls.h
478 return 0;
479 }
480
481 Value *getOrCreateResultFromMemIntrinsic(IntrinsicInst *Inst,
482 Type *ExpectedType) {
483 return nullptr;
484 }
485
486 Type *getMemcpyLoopLoweringType(LLVMContext &Context, Value *Length,
487 unsigned SrcAlign, unsigned DestAlign) const {
488 return Type::getInt8Ty(Context);
489 }
490
491 void getMemcpyLoopResidualLoweringType(SmallVectorImpl<Type *> &OpsOut,
492 LLVMContext &Context,
493 unsigned RemainingBytes,
494 unsigned SrcAlign,
495 unsigned DestAlign) const {
496 for (unsigned i = 0; i != RemainingBytes; ++i)
497 OpsOut.push_back(Type::getInt8Ty(Context));
498 }
499
500 bool areInlineCompatible(const Function *Caller,
501 const Function *Callee) const {
502 return (Caller->getFnAttribute("target-cpu") ==
503 Callee->getFnAttribute("target-cpu")) &&
504 (Caller->getFnAttribute("target-features") ==
505 Callee->getFnAttribute("target-features"));
506 }
507
508 unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const { return 128; }
509
510 bool isLegalToVectorizeLoad(LoadInst *LI) const { return true; }
511
512 bool isLegalToVectorizeStore(StoreInst *SI) const { return true; }
513
514 bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes,
515 unsigned Alignment,
516 unsigned AddrSpace) const {
517 return true;
518 }
519
520 bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes,
521 unsigned Alignment,
522 unsigned AddrSpace) const {
523 return true;
524 }
525
526 unsigned getLoadVectorFactor(unsigned VF, unsigned LoadSize,
527 unsigned ChainSizeInBytes,
528 VectorType *VecTy) const {
529 return VF;
530 }
531
532 unsigned getStoreVectorFactor(unsigned VF, unsigned StoreSize,
533 unsigned ChainSizeInBytes,
534 VectorType *VecTy) const {
535 return VF;
536 }
537
538 bool useReductionIntrinsic(unsigned Opcode, Type *Ty,
539 TTI::ReductionFlags Flags) const {
540 return false;
541 }
542
543 bool shouldExpandReduction(const IntrinsicInst *II) const {
544 return true;
545 }
546
547protected:
548 // Obtain the minimum required size to hold the value (without the sign)
549 // In case of a vector it returns the min required size for one element.
550 unsigned minRequiredElementSize(const Value* Val, bool &isSigned) {
551 if (isa<ConstantDataVector>(Val) || isa<ConstantVector>(Val)) {
552 const auto* VectorValue = cast<Constant>(Val);
553
554 // In case of a vector need to pick the max between the min
555 // required size for each element
556 auto *VT = cast<VectorType>(Val->getType());
557
558 // Assume unsigned elements
559 isSigned = false;
560
561 // The max required size is the total vector width divided by num
562 // of elements in the vector
563 unsigned MaxRequiredSize = VT->getBitWidth() / VT->getNumElements();
564
565 unsigned MinRequiredSize = 0;
566 for(unsigned i = 0, e = VT->getNumElements(); i < e; ++i) {
567 if (auto* IntElement =
568 dyn_cast<ConstantInt>(VectorValue->getAggregateElement(i))) {
569 bool signedElement = IntElement->getValue().isNegative();
570 // Get the element min required size.
571 unsigned ElementMinRequiredSize =
572 IntElement->getValue().getMinSignedBits() - 1;
573 // In case one element is signed then all the vector is signed.
574 isSigned |= signedElement;
575 // Save the max required bit size between all the elements.
576 MinRequiredSize = std::max(MinRequiredSize, ElementMinRequiredSize);
577 }
578 else {
579 // not an int constant element
580 return MaxRequiredSize;
581 }
582 }
583 return MinRequiredSize;
584 }
585
586 if (const auto* CI = dyn_cast<ConstantInt>(Val)) {
587 isSigned = CI->getValue().isNegative();
588 return CI->getValue().getMinSignedBits() - 1;
589 }
590
591 if (const auto* Cast = dyn_cast<SExtInst>(Val)) {
592 isSigned = true;
593 return Cast->getSrcTy()->getScalarSizeInBits() - 1;
594 }
595
596 if (const auto* Cast = dyn_cast<ZExtInst>(Val)) {
597 isSigned = false;
598 return Cast->getSrcTy()->getScalarSizeInBits();
599 }
600
601 isSigned = false;
602 return Val->getType()->getScalarSizeInBits();
603 }
604
605 bool isStridedAccess(const SCEV *Ptr) {
606 return Ptr && isa<SCEVAddRecExpr>(Ptr);
607 }
608
609 const SCEVConstant *getConstantStrideStep(ScalarEvolution *SE,
610 const SCEV *Ptr) {
611 if (!isStridedAccess(Ptr))
612 return nullptr;
613 const SCEVAddRecExpr *AddRec = cast<SCEVAddRecExpr>(Ptr);
614 return dyn_cast<SCEVConstant>(AddRec->getStepRecurrence(*SE));
615 }
616
617 bool isConstantStridedAccessLessThan(ScalarEvolution *SE, const SCEV *Ptr,
618 int64_t MergeDistance) {
619 const SCEVConstant *Step = getConstantStrideStep(SE, Ptr);
620 if (!Step)
621 return false;
622 APInt StrideVal = Step->getAPInt();
623 if (StrideVal.getBitWidth() > 64)
624 return false;
625 // FIXME: Need to take absolute value for negative stride case.
626 return StrideVal.getSExtValue() < MergeDistance;
627 }
628};
629
630/// \brief CRTP base class for use as a mix-in that aids implementing
631/// a TargetTransformInfo-compatible class.
632template <typename T>
633class TargetTransformInfoImplCRTPBase : public TargetTransformInfoImplBase {
634private:
635 typedef TargetTransformInfoImplBase BaseT;
636
637protected:
638 explicit TargetTransformInfoImplCRTPBase(const DataLayout &DL) : BaseT(DL) {}
639
640public:
641 using BaseT::getCallCost;
642
643 unsigned getCallCost(const Function *F, int NumArgs) {
644 assert(F && "A concrete function must be provided to this routine.")((F && "A concrete function must be provided to this routine."
) ? static_cast<void> (0) : __assert_fail ("F && \"A concrete function must be provided to this routine.\""
, "/build/llvm-toolchain-snapshot-6.0~svn318211/include/llvm/Analysis/TargetTransformInfoImpl.h"
, 644, __PRETTY_FUNCTION__))
;
645
646 if (NumArgs < 0)
647 // Set the argument number to the number of explicit arguments in the
648 // function.
649 NumArgs = F->arg_size();
650
651 if (Intrinsic::ID IID = F->getIntrinsicID()) {
652 FunctionType *FTy = F->getFunctionType();
653 SmallVector<Type *, 8> ParamTys(FTy->param_begin(), FTy->param_end());
654 return static_cast<T *>(this)
655 ->getIntrinsicCost(IID, FTy->getReturnType(), ParamTys);
656 }
657
658 if (!static_cast<T *>(this)->isLoweredToCall(F))
659 return TTI::TCC_Basic; // Give a basic cost if it will be lowered
660 // directly.
661
662 return static_cast<T *>(this)->getCallCost(F->getFunctionType(), NumArgs);
663 }
664
665 unsigned getCallCost(const Function *F, ArrayRef<const Value *> Arguments) {
666 // Simply delegate to generic handling of the call.
667 // FIXME: We should use instsimplify or something else to catch calls which
668 // will constant fold with these arguments.
669 return static_cast<T *>(this)->getCallCost(F, Arguments.size());
670 }
671
672 using BaseT::getGEPCost;
673
674 int getGEPCost(Type *PointeeType, const Value *Ptr,
675 ArrayRef<const Value *> Operands) {
676 const GlobalValue *BaseGV = nullptr;
677 if (Ptr != nullptr) {
678 // TODO: will remove this when pointers have an opaque type.
679 assert(Ptr->getType()->getScalarType()->getPointerElementType() ==((Ptr->getType()->getScalarType()->getPointerElementType
() == PointeeType && "explicit pointee type doesn't match operand's pointee type"
) ? static_cast<void> (0) : __assert_fail ("Ptr->getType()->getScalarType()->getPointerElementType() == PointeeType && \"explicit pointee type doesn't match operand's pointee type\""
, "/build/llvm-toolchain-snapshot-6.0~svn318211/include/llvm/Analysis/TargetTransformInfoImpl.h"
, 681, __PRETTY_FUNCTION__))
680 PointeeType &&((Ptr->getType()->getScalarType()->getPointerElementType
() == PointeeType && "explicit pointee type doesn't match operand's pointee type"
) ? static_cast<void> (0) : __assert_fail ("Ptr->getType()->getScalarType()->getPointerElementType() == PointeeType && \"explicit pointee type doesn't match operand's pointee type\""
, "/build/llvm-toolchain-snapshot-6.0~svn318211/include/llvm/Analysis/TargetTransformInfoImpl.h"
, 681, __PRETTY_FUNCTION__))
681 "explicit pointee type doesn't match operand's pointee type")((Ptr->getType()->getScalarType()->getPointerElementType
() == PointeeType && "explicit pointee type doesn't match operand's pointee type"
) ? static_cast<void> (0) : __assert_fail ("Ptr->getType()->getScalarType()->getPointerElementType() == PointeeType && \"explicit pointee type doesn't match operand's pointee type\""
, "/build/llvm-toolchain-snapshot-6.0~svn318211/include/llvm/Analysis/TargetTransformInfoImpl.h"
, 681, __PRETTY_FUNCTION__))
;
682 BaseGV = dyn_cast<GlobalValue>(Ptr->stripPointerCasts());
683 }
684 bool HasBaseReg = (BaseGV == nullptr);
685
686 auto PtrSizeBits = DL.getPointerTypeSizeInBits(Ptr->getType());
687 APInt BaseOffset(PtrSizeBits, 0);
688 int64_t Scale = 0;
689
690 auto GTI = gep_type_begin(PointeeType, Operands);
691 Type *TargetType = nullptr;
692
693 // Handle the case where the GEP instruction has a single operand,
694 // the basis, therefore TargetType is a nullptr.
695 if (Operands.empty())
696 return !BaseGV ? TTI::TCC_Free : TTI::TCC_Basic;
697
698 for (auto I = Operands.begin(); I != Operands.end(); ++I, ++GTI) {
699 TargetType = GTI.getIndexedType();
700 // We assume that the cost of Scalar GEP with constant index and the
701 // cost of Vector GEP with splat constant index are the same.
702 const ConstantInt *ConstIdx = dyn_cast<ConstantInt>(*I);
703 if (!ConstIdx)
704 if (auto Splat = getSplatValue(*I))
705 ConstIdx = dyn_cast<ConstantInt>(Splat);
706 if (StructType *STy = GTI.getStructTypeOrNull()) {
707 // For structures the index is always splat or scalar constant
708 assert(ConstIdx && "Unexpected GEP index")((ConstIdx && "Unexpected GEP index") ? static_cast<
void> (0) : __assert_fail ("ConstIdx && \"Unexpected GEP index\""
, "/build/llvm-toolchain-snapshot-6.0~svn318211/include/llvm/Analysis/TargetTransformInfoImpl.h"
, 708, __PRETTY_FUNCTION__))
;
709 uint64_t Field = ConstIdx->getZExtValue();
710 BaseOffset += DL.getStructLayout(STy)->getElementOffset(Field);
711 } else {
712 int64_t ElementSize = DL.getTypeAllocSize(GTI.getIndexedType());
713 if (ConstIdx) {
714 BaseOffset +=
715 ConstIdx->getValue().sextOrTrunc(PtrSizeBits) * ElementSize;
716 } else {
717 // Needs scale register.
718 if (Scale != 0)
719 // No addressing mode takes two scale registers.
720 return TTI::TCC_Basic;
721 Scale = ElementSize;
722 }
723 }
724 }
725
726 // Assumes the address space is 0 when Ptr is nullptr.
727 unsigned AS =
728 (Ptr == nullptr ? 0 : Ptr->getType()->getPointerAddressSpace());
729
730 if (static_cast<T *>(this)->isLegalAddressingMode(
731 TargetType, const_cast<GlobalValue *>(BaseGV),
732 BaseOffset.sextOrTrunc(64).getSExtValue(), HasBaseReg, Scale, AS))
733 return TTI::TCC_Free;
734 return TTI::TCC_Basic;
735 }
736
737 using BaseT::getIntrinsicCost;
738
739 unsigned getIntrinsicCost(Intrinsic::ID IID, Type *RetTy,
740 ArrayRef<const Value *> Arguments) {
741 // Delegate to the generic intrinsic handling code. This mostly provides an
742 // opportunity for targets to (for example) special case the cost of
743 // certain intrinsics based on constants used as arguments.
744 SmallVector<Type *, 8> ParamTys;
745 ParamTys.reserve(Arguments.size());
746 for (unsigned Idx = 0, Size = Arguments.size(); Idx != Size; ++Idx)
747 ParamTys.push_back(Arguments[Idx]->getType());
748 return static_cast<T *>(this)->getIntrinsicCost(IID, RetTy, ParamTys);
749 }
750
751 unsigned getUserCost(const User *U, ArrayRef<const Value *> Operands) {
752 if (isa<PHINode>(U))
3
Taking false branch
753 return TTI::TCC_Free; // Model all PHI nodes as free.
754
755 // Static alloca doesn't generate target instructions.
756 if (auto *A = dyn_cast<AllocaInst>(U))
4
Taking false branch
757 if (A->isStaticAlloca())
758 return TTI::TCC_Free;
759
760 if (const GEPOperator *GEP = dyn_cast<GEPOperator>(U)) {
5
Taking false branch
761 return static_cast<T *>(this)->getGEPCost(GEP->getSourceElementType(),
762 GEP->getPointerOperand(),
763 Operands.drop_front());
764 }
765
766 if (auto CS = ImmutableCallSite(U)) {
6
Taking false branch
767 const Function *F = CS.getCalledFunction();
768 if (!F) {
769 // Just use the called value type.
770 Type *FTy = CS.getCalledValue()->getType()->getPointerElementType();
771 return static_cast<T *>(this)
772 ->getCallCost(cast<FunctionType>(FTy), CS.arg_size());
773 }
774
775 SmallVector<const Value *, 8> Arguments(CS.arg_begin(), CS.arg_end());
776 return static_cast<T *>(this)->getCallCost(F, Arguments);
777 }
778
779 if (const CastInst *CI = dyn_cast<CastInst>(U)) {
7
Taking false branch
780 // Result of a cmp instruction is often extended (to be used by other
781 // cmp instructions, logical or return instructions). These are usually
782 // nop on most sane targets.
783 if (isa<CmpInst>(CI->getOperand(0)))
784 return TTI::TCC_Free;
785 if (isa<SExtInst>(CI) || isa<ZExtInst>(CI) || isa<FPExtInst>(CI))
786 return static_cast<T *>(this)->getExtCost(CI, Operands.back());
787 }
788
789 return static_cast<T *>(this)->getOperationCost(
11
Calling 'BasicTTIImplBase::getOperationCost'
790 Operator::getOpcode(U), U->getType(),
791 U->getNumOperands() == 1 ? U->getOperand(0)->getType() : nullptr);
8
Assuming the condition is false
9
'?' condition is false
10
Passing null pointer value via 3rd parameter 'OpTy'
792 }
793
794 int getInstructionLatency(const Instruction *I) {
795 SmallVector<const Value *, 4> Operands(I->value_op_begin(),
796 I->value_op_end());
797 if (getUserCost(I, Operands) == TTI::TCC_Free)
798 return 0;
799
800 if (isa<LoadInst>(I))
801 return 4;
802
803 Type *DstTy = I->getType();
804
805 // Usually an intrinsic is a simple instruction.
806 // A real function call is much slower.
807 if (auto *CI = dyn_cast<CallInst>(I)) {
808 const Function *F = CI->getCalledFunction();
809 if (!F || static_cast<T *>(this)->isLoweredToCall(F))
810 return 40;
811 // Some intrinsics return a value and a flag, we use the value type
812 // to decide its latency.
813 if (StructType* StructTy = dyn_cast<StructType>(DstTy))
814 DstTy = StructTy->getElementType(0);
815 // Fall through to simple instructions.
816 }
817
818 if (VectorType *VectorTy = dyn_cast<VectorType>(DstTy))
819 DstTy = VectorTy->getElementType();
820 if (DstTy->isFloatingPointTy())
821 return 3;
822
823 return 1;
824 }
825};
826}
827
828#endif

/build/llvm-toolchain-snapshot-6.0~svn318211/include/llvm/CodeGen/BasicTTIImpl.h

1//===- BasicTTIImpl.h -------------------------------------------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10/// \file
11/// This file provides a helper that implements much of the TTI interface in
12/// terms of the target-independent code generator and TargetLowering
13/// interfaces.
14//
15//===----------------------------------------------------------------------===//
16
17#ifndef LLVM_CODEGEN_BASICTTIIMPL_H
18#define LLVM_CODEGEN_BASICTTIIMPL_H
19
20#include "llvm/ADT/APInt.h"
21#include "llvm/ADT/ArrayRef.h"
22#include "llvm/ADT/BitVector.h"
23#include "llvm/ADT/SmallPtrSet.h"
24#include "llvm/ADT/SmallVector.h"
25#include "llvm/Analysis/LoopInfo.h"
26#include "llvm/Analysis/TargetTransformInfo.h"
27#include "llvm/Analysis/TargetTransformInfoImpl.h"
28#include "llvm/CodeGen/ISDOpcodes.h"
29#include "llvm/CodeGen/MachineValueType.h"
30#include "llvm/CodeGen/ValueTypes.h"
31#include "llvm/IR/BasicBlock.h"
32#include "llvm/IR/CallSite.h"
33#include "llvm/IR/Constant.h"
34#include "llvm/IR/Constants.h"
35#include "llvm/IR/DataLayout.h"
36#include "llvm/IR/DerivedTypes.h"
37#include "llvm/IR/InstrTypes.h"
38#include "llvm/IR/Instruction.h"
39#include "llvm/IR/Instructions.h"
40#include "llvm/IR/Intrinsics.h"
41#include "llvm/IR/Operator.h"
42#include "llvm/IR/Type.h"
43#include "llvm/IR/Value.h"
44#include "llvm/MC/MCSchedule.h"
45#include "llvm/Support/Casting.h"
46#include "llvm/Support/CommandLine.h"
47#include "llvm/Support/ErrorHandling.h"
48#include "llvm/Support/MathExtras.h"
49#include "llvm/Target/TargetLowering.h"
50#include "llvm/Target/TargetSubtargetInfo.h"
51#include <algorithm>
52#include <cassert>
53#include <cstdint>
54#include <limits>
55#include <utility>
56
57namespace llvm {
58
59class Function;
60class GlobalValue;
61class LLVMContext;
62class ScalarEvolution;
63class SCEV;
64class TargetMachine;
65
66extern cl::opt<unsigned> PartialUnrollingThreshold;
67
68/// \brief Base class which can be used to help build a TTI implementation.
69///
70/// This class provides as much implementation of the TTI interface as is
71/// possible using the target independent parts of the code generator.
72///
73/// In order to subclass it, your class must implement a getST() method to
74/// return the subtarget, and a getTLI() method to return the target lowering.
75/// We need these methods implemented in the derived class so that this class
76/// doesn't have to duplicate storage for them.
77template <typename T>
78class BasicTTIImplBase : public TargetTransformInfoImplCRTPBase<T> {
79private:
80 using BaseT = TargetTransformInfoImplCRTPBase<T>;
81 using TTI = TargetTransformInfo;
82
83 /// Estimate a cost of shuffle as a sequence of extract and insert
84 /// operations.
85 unsigned getPermuteShuffleOverhead(Type *Ty) {
86 assert(Ty->isVectorTy() && "Can only shuffle vectors")((Ty->isVectorTy() && "Can only shuffle vectors") ?
static_cast<void> (0) : __assert_fail ("Ty->isVectorTy() && \"Can only shuffle vectors\""
, "/build/llvm-toolchain-snapshot-6.0~svn318211/include/llvm/CodeGen/BasicTTIImpl.h"
, 86, __PRETTY_FUNCTION__))
;
87 unsigned Cost = 0;
88 // Shuffle cost is equal to the cost of extracting element from its argument
89 // plus the cost of inserting them onto the result vector.
90
91 // e.g. <4 x float> has a mask of <0,5,2,7> i.e we need to extract from
92 // index 0 of first vector, index 1 of second vector,index 2 of first
93 // vector and finally index 3 of second vector and insert them at index
94 // <0,1,2,3> of result vector.
95 for (int i = 0, e = Ty->getVectorNumElements(); i < e; ++i) {
96 Cost += static_cast<T *>(this)
97 ->getVectorInstrCost(Instruction::InsertElement, Ty, i);
98 Cost += static_cast<T *>(this)
99 ->getVectorInstrCost(Instruction::ExtractElement, Ty, i);
100 }
101 return Cost;
102 }
103
104 /// \brief Local query method delegates up to T which *must* implement this!
105 const TargetSubtargetInfo *getST() const {
106 return static_cast<const T *>(this)->getST();
107 }
108
109 /// \brief Local query method delegates up to T which *must* implement this!
110 const TargetLoweringBase *getTLI() const {
111 return static_cast<const T *>(this)->getTLI();
112 }
113
114protected:
115 explicit BasicTTIImplBase(const TargetMachine *TM, const DataLayout &DL)
116 : BaseT(DL) {}
117
118 using TargetTransformInfoImplBase::DL;
119
120public:
121 /// \name Scalar TTI Implementations
122 /// @{
123 bool allowsMisalignedMemoryAccesses(LLVMContext &Context,
124 unsigned BitWidth, unsigned AddressSpace,
125 unsigned Alignment, bool *Fast) const {
126 EVT E = EVT::getIntegerVT(Context, BitWidth);
127 return getTLI()->allowsMisalignedMemoryAccesses(E, AddressSpace, Alignment, Fast);
128 }
129
130 bool hasBranchDivergence() { return false; }
131
132 bool isSourceOfDivergence(const Value *V) { return false; }
133
134 bool isAlwaysUniform(const Value *V) { return false; }
135
136 unsigned getFlatAddressSpace() {
137 // Return an invalid address space.
138 return -1;
139 }
140
141 bool isLegalAddImmediate(int64_t imm) {
142 return getTLI()->isLegalAddImmediate(imm);
143 }
144
145 bool isLegalICmpImmediate(int64_t imm) {
146 return getTLI()->isLegalICmpImmediate(imm);
147 }
148
149 bool isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset,
150 bool HasBaseReg, int64_t Scale,
151 unsigned AddrSpace, Instruction *I = nullptr) {
152 TargetLoweringBase::AddrMode AM;
153 AM.BaseGV = BaseGV;
154 AM.BaseOffs = BaseOffset;
155 AM.HasBaseReg = HasBaseReg;
156 AM.Scale = Scale;
157 return getTLI()->isLegalAddressingMode(DL, AM, Ty, AddrSpace, I);
158 }
159
160 bool isLSRCostLess(TTI::LSRCost C1, TTI::LSRCost C2) {
161 return TargetTransformInfoImplBase::isLSRCostLess(C1, C2);
162 }
163
164 int getScalingFactorCost(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset,
165 bool HasBaseReg, int64_t Scale, unsigned AddrSpace) {
166 TargetLoweringBase::AddrMode AM;
167 AM.BaseGV = BaseGV;
168 AM.BaseOffs = BaseOffset;
169 AM.HasBaseReg = HasBaseReg;
170 AM.Scale = Scale;
171 return getTLI()->getScalingFactorCost(DL, AM, Ty, AddrSpace);
172 }
173
174 bool isTruncateFree(Type *Ty1, Type *Ty2) {
175 return getTLI()->isTruncateFree(Ty1, Ty2);
176 }
177
178 bool isProfitableToHoist(Instruction *I) {
179 return getTLI()->isProfitableToHoist(I);
180 }
181
182 bool isTypeLegal(Type *Ty) {
183 EVT VT = getTLI()->getValueType(DL, Ty);
184 return getTLI()->isTypeLegal(VT);
185 }
186
187 int getGEPCost(Type *PointeeType, const Value *Ptr,
188 ArrayRef<const Value *> Operands) {
189 return BaseT::getGEPCost(PointeeType, Ptr, Operands);
190 }
191
192 int getExtCost(const Instruction *I, const Value *Src) {
193 if (getTLI()->isExtFree(I))
194 return TargetTransformInfo::TCC_Free;
195
196 if (isa<ZExtInst>(I) || isa<SExtInst>(I))
197 if (const LoadInst *LI = dyn_cast<LoadInst>(Src))
198 if (getTLI()->isExtLoad(LI, I, DL))
199 return TargetTransformInfo::TCC_Free;
200
201 return TargetTransformInfo::TCC_Basic;
202 }
203
204 unsigned getIntrinsicCost(Intrinsic::ID IID, Type *RetTy,
205 ArrayRef<const Value *> Arguments) {
206 return BaseT::getIntrinsicCost(IID, RetTy, Arguments);
207 }
208
209 unsigned getIntrinsicCost(Intrinsic::ID IID, Type *RetTy,
210 ArrayRef<Type *> ParamTys) {
211 if (IID == Intrinsic::cttz) {
212 if (getTLI()->isCheapToSpeculateCttz())
213 return TargetTransformInfo::TCC_Basic;
214 return TargetTransformInfo::TCC_Expensive;
215 }
216
217 if (IID == Intrinsic::ctlz) {
218 if (getTLI()->isCheapToSpeculateCtlz())
219 return TargetTransformInfo::TCC_Basic;
220 return TargetTransformInfo::TCC_Expensive;
221 }
222
223 return BaseT::getIntrinsicCost(IID, RetTy, ParamTys);
224 }
225
226 unsigned getEstimatedNumberOfCaseClusters(const SwitchInst &SI,
227 unsigned &JumpTableSize) {
228 /// Try to find the estimated number of clusters. Note that the number of
229 /// clusters identified in this function could be different from the actural
230 /// numbers found in lowering. This function ignore switches that are
231 /// lowered with a mix of jump table / bit test / BTree. This function was
232 /// initially intended to be used when estimating the cost of switch in
233 /// inline cost heuristic, but it's a generic cost model to be used in other
234 /// places (e.g., in loop unrolling).
235 unsigned N = SI.getNumCases();
236 const TargetLoweringBase *TLI = getTLI();
237 const DataLayout &DL = this->getDataLayout();
238
239 JumpTableSize = 0;
240 bool IsJTAllowed = TLI->areJTsAllowed(SI.getParent()->getParent());
241
242 // Early exit if both a jump table and bit test are not allowed.
243 if (N < 1 || (!IsJTAllowed && DL.getPointerSizeInBits() < N))
244 return N;
245
246 APInt MaxCaseVal = SI.case_begin()->getCaseValue()->getValue();
247 APInt MinCaseVal = MaxCaseVal;
248 for (auto CI : SI.cases()) {
249 const APInt &CaseVal = CI.getCaseValue()->getValue();
250 if (CaseVal.sgt(MaxCaseVal))
251 MaxCaseVal = CaseVal;
252 if (CaseVal.slt(MinCaseVal))
253 MinCaseVal = CaseVal;
254 }
255
256 // Check if suitable for a bit test
257 if (N <= DL.getPointerSizeInBits()) {
258 SmallPtrSet<const BasicBlock *, 4> Dests;
259 for (auto I : SI.cases())
260 Dests.insert(I.getCaseSuccessor());
261
262 if (TLI->isSuitableForBitTests(Dests.size(), N, MinCaseVal, MaxCaseVal,
263 DL))
264 return 1;
265 }
266
267 // Check if suitable for a jump table.
268 if (IsJTAllowed) {
269 if (N < 2 || N < TLI->getMinimumJumpTableEntries())
270 return N;
271 uint64_t Range =
272 (MaxCaseVal - MinCaseVal)
273 .getLimitedValue(std::numeric_limits<uint64_t>::max() - 1) + 1;
274 // Check whether a range of clusters is dense enough for a jump table
275 if (TLI->isSuitableForJumpTable(&SI, N, Range)) {
276 JumpTableSize = Range;
277 return 1;
278 }
279 }
280 return N;
281 }
282
283 unsigned getJumpBufAlignment() { return getTLI()->getJumpBufAlignment(); }
284
285 unsigned getJumpBufSize() { return getTLI()->getJumpBufSize(); }
286
287 bool shouldBuildLookupTables() {
288 const TargetLoweringBase *TLI = getTLI();
289 return TLI->isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
290 TLI->isOperationLegalOrCustom(ISD::BRIND, MVT::Other);
291 }
292
293 bool haveFastSqrt(Type *Ty) {
294 const TargetLoweringBase *TLI = getTLI();
295 EVT VT = TLI->getValueType(DL, Ty);
296 return TLI->isTypeLegal(VT) &&
297 TLI->isOperationLegalOrCustom(ISD::FSQRT, VT);
298 }
299
300 unsigned getFPOpCost(Type *Ty) {
301 // By default, FP instructions are no more expensive since they are
302 // implemented in HW. Target specific TTI can override this.
303 return TargetTransformInfo::TCC_Basic;
304 }
305
306 unsigned getOperationCost(unsigned Opcode, Type *Ty, Type *OpTy) {
307 const TargetLoweringBase *TLI = getTLI();
308 switch (Opcode) {
12
Control jumps to the 'default' case at line 309
309 default: break;
13
Execution continues on line 320
310 case Instruction::Trunc:
311 if (TLI->isTruncateFree(OpTy, Ty))
312 return TargetTransformInfo::TCC_Free;
313 return TargetTransformInfo::TCC_Basic;
314 case Instruction::ZExt:
315 if (TLI->isZExtFree(OpTy, Ty))
316 return TargetTransformInfo::TCC_Free;
317 return TargetTransformInfo::TCC_Basic;
318 }
319
320 return BaseT::getOperationCost(Opcode, Ty, OpTy);
14
Passing null pointer value via 3rd parameter 'OpTy'
15
Calling 'TargetTransformInfoImplBase::getOperationCost'
321 }
322
323 unsigned getInliningThresholdMultiplier() { return 1; }
324
325 void getUnrollingPreferences(Loop *L, ScalarEvolution &SE,
326 TTI::UnrollingPreferences &UP) {
327 // This unrolling functionality is target independent, but to provide some
328 // motivation for its intended use, for x86:
329
330 // According to the Intel 64 and IA-32 Architectures Optimization Reference
331 // Manual, Intel Core models and later have a loop stream detector (and
332 // associated uop queue) that can benefit from partial unrolling.
333 // The relevant requirements are:
334 // - The loop must have no more than 4 (8 for Nehalem and later) branches
335 // taken, and none of them may be calls.
336 // - The loop can have no more than 18 (28 for Nehalem and later) uops.
337
338 // According to the Software Optimization Guide for AMD Family 15h
339 // Processors, models 30h-4fh (Steamroller and later) have a loop predictor
340 // and loop buffer which can benefit from partial unrolling.
341 // The relevant requirements are:
342 // - The loop must have fewer than 16 branches
343 // - The loop must have less than 40 uops in all executed loop branches
344
345 // The number of taken branches in a loop is hard to estimate here, and
346 // benchmarking has revealed that it is better not to be conservative when
347 // estimating the branch count. As a result, we'll ignore the branch limits
348 // until someone finds a case where it matters in practice.
349
350 unsigned MaxOps;
351 const TargetSubtargetInfo *ST = getST();
352 if (PartialUnrollingThreshold.getNumOccurrences() > 0)
353 MaxOps = PartialUnrollingThreshold;
354 else if (ST->getSchedModel().LoopMicroOpBufferSize > 0)
355 MaxOps = ST->getSchedModel().LoopMicroOpBufferSize;
356 else
357 return;
358
359 // Scan the loop: don't unroll loops with calls.
360 for (Loop::block_iterator I = L->block_begin(), E = L->block_end(); I != E;
361 ++I) {
362 BasicBlock *BB = *I;
363
364 for (BasicBlock::iterator J = BB->begin(), JE = BB->end(); J != JE; ++J)
365 if (isa<CallInst>(J) || isa<InvokeInst>(J)) {
366 ImmutableCallSite CS(&*J);
367 if (const Function *F = CS.getCalledFunction()) {
368 if (!static_cast<T *>(this)->isLoweredToCall(F))
369 continue;
370 }
371
372 return;
373 }
374 }
375
376 // Enable runtime and partial unrolling up to the specified size.
377 // Enable using trip count upper bound to unroll loops.
378 UP.Partial = UP.Runtime = UP.UpperBound = true;
379 UP.PartialThreshold = MaxOps;
380
381 // Avoid unrolling when optimizing for size.
382 UP.OptSizeThreshold = 0;
383 UP.PartialOptSizeThreshold = 0;
384
385 // Set number of instructions optimized when "back edge"
386 // becomes "fall through" to default value of 2.
387 UP.BEInsns = 2;
388 }
389
390 int getInstructionLatency(const Instruction *I) {
391 if (isa<LoadInst>(I))
392 return getST()->getSchedModel().DefaultLoadLatency;
393
394 return BaseT::getInstructionLatency(I);
395 }
396
397 /// @}
398
399 /// \name Vector TTI Implementations
400 /// @{
401
402 unsigned getNumberOfRegisters(bool Vector) { return Vector ? 0 : 1; }
403
404 unsigned getRegisterBitWidth(bool Vector) const { return 32; }
405
406 /// Estimate the overhead of scalarizing an instruction. Insert and Extract
407 /// are set if the result needs to be inserted and/or extracted from vectors.
408 unsigned getScalarizationOverhead(Type *Ty, bool Insert, bool Extract) {
409 assert(Ty->isVectorTy() && "Can only scalarize vectors")((Ty->isVectorTy() && "Can only scalarize vectors"
) ? static_cast<void> (0) : __assert_fail ("Ty->isVectorTy() && \"Can only scalarize vectors\""
, "/build/llvm-toolchain-snapshot-6.0~svn318211/include/llvm/CodeGen/BasicTTIImpl.h"
, 409, __PRETTY_FUNCTION__))
;
410 unsigned Cost = 0;
411
412 for (int i = 0, e = Ty->getVectorNumElements(); i < e; ++i) {
413 if (Insert)
414 Cost += static_cast<T *>(this)
415 ->getVectorInstrCost(Instruction::InsertElement, Ty, i);
416 if (Extract)
417 Cost += static_cast<T *>(this)
418 ->getVectorInstrCost(Instruction::ExtractElement, Ty, i);
419 }
420
421 return Cost;
422 }
423
424 /// Estimate the overhead of scalarizing an instructions unique
425 /// non-constant operands. The types of the arguments are ordinarily
426 /// scalar, in which case the costs are multiplied with VF.
427 unsigned getOperandsScalarizationOverhead(ArrayRef<const Value *> Args,
428 unsigned VF) {
429 unsigned Cost = 0;
430 SmallPtrSet<const Value*, 4> UniqueOperands;
431 for (const Value *A : Args) {
432 if (!isa<Constant>(A) && UniqueOperands.insert(A).second) {
433 Type *VecTy = nullptr;
434 if (A->getType()->isVectorTy()) {
435 VecTy = A->getType();
436 // If A is a vector operand, VF should be 1 or correspond to A.
437 assert((VF == 1 || VF == VecTy->getVectorNumElements()) &&(((VF == 1 || VF == VecTy->getVectorNumElements()) &&
"Vector argument does not match VF") ? static_cast<void>
(0) : __assert_fail ("(VF == 1 || VF == VecTy->getVectorNumElements()) && \"Vector argument does not match VF\""
, "/build/llvm-toolchain-snapshot-6.0~svn318211/include/llvm/CodeGen/BasicTTIImpl.h"
, 438, __PRETTY_FUNCTION__))
438 "Vector argument does not match VF")(((VF == 1 || VF == VecTy->getVectorNumElements()) &&
"Vector argument does not match VF") ? static_cast<void>
(0) : __assert_fail ("(VF == 1 || VF == VecTy->getVectorNumElements()) && \"Vector argument does not match VF\""
, "/build/llvm-toolchain-snapshot-6.0~svn318211/include/llvm/CodeGen/BasicTTIImpl.h"
, 438, __PRETTY_FUNCTION__))
;
439 }
440 else
441 VecTy = VectorType::get(A->getType(), VF);
442
443 Cost += getScalarizationOverhead(VecTy, false, true);
444 }
445 }
446
447 return Cost;
448 }
449
450 unsigned getScalarizationOverhead(Type *VecTy, ArrayRef<const Value *> Args) {
451 assert(VecTy->isVectorTy())((VecTy->isVectorTy()) ? static_cast<void> (0) : __assert_fail
("VecTy->isVectorTy()", "/build/llvm-toolchain-snapshot-6.0~svn318211/include/llvm/CodeGen/BasicTTIImpl.h"
, 451, __PRETTY_FUNCTION__))
;
452
453 unsigned Cost = 0;
454
455 Cost += getScalarizationOverhead(VecTy, true, false);
456 if (!Args.empty())
457 Cost += getOperandsScalarizationOverhead(Args,
458 VecTy->getVectorNumElements());
459 else
460 // When no information on arguments is provided, we add the cost
461 // associated with one argument as a heuristic.
462 Cost += getScalarizationOverhead(VecTy, false, true);
463
464 return Cost;
465 }
466
467 unsigned getMaxInterleaveFactor(unsigned VF) { return 1; }
468
469 unsigned getArithmeticInstrCost(
470 unsigned Opcode, Type *Ty,
471 TTI::OperandValueKind Opd1Info = TTI::OK_AnyValue,
472 TTI::OperandValueKind Opd2Info = TTI::OK_AnyValue,
473 TTI::OperandValueProperties Opd1PropInfo = TTI::OP_None,
474 TTI::OperandValueProperties Opd2PropInfo = TTI::OP_None,
475 ArrayRef<const Value *> Args = ArrayRef<const Value *>()) {
476 // Check if any of the operands are vector operands.
477 const TargetLoweringBase *TLI = getTLI();
478 int ISD = TLI->InstructionOpcodeToISD(Opcode);
479 assert(ISD && "Invalid opcode")((ISD && "Invalid opcode") ? static_cast<void> (
0) : __assert_fail ("ISD && \"Invalid opcode\"", "/build/llvm-toolchain-snapshot-6.0~svn318211/include/llvm/CodeGen/BasicTTIImpl.h"
, 479, __PRETTY_FUNCTION__))
;
480
481 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty);
482
483 bool IsFloat = Ty->isFPOrFPVectorTy();
484 // Assume that floating point arithmetic operations cost twice as much as
485 // integer operations.
486 unsigned OpCost = (IsFloat ? 2 : 1);
487
488 if (TLI->isOperationLegalOrPromote(ISD, LT.second)) {
489 // The operation is legal. Assume it costs 1.
490 // TODO: Once we have extract/insert subvector cost we need to use them.
491 return LT.first * OpCost;
492 }
493
494 if (!TLI->isOperationExpand(ISD, LT.second)) {
495 // If the operation is custom lowered, then assume that the code is twice
496 // as expensive.
497 return LT.first * 2 * OpCost;
498 }
499
500 // Else, assume that we need to scalarize this op.
501 // TODO: If one of the types get legalized by splitting, handle this
502 // similarly to what getCastInstrCost() does.
503 if (Ty->isVectorTy()) {
504 unsigned Num = Ty->getVectorNumElements();
505 unsigned Cost = static_cast<T *>(this)
506 ->getArithmeticInstrCost(Opcode, Ty->getScalarType());
507 // Return the cost of multiple scalar invocation plus the cost of
508 // inserting and extracting the values.
509 return getScalarizationOverhead(Ty, Args) + Num * Cost;
510 }
511
512 // We don't know anything about this scalar instruction.
513 return OpCost;
514 }
515
516 unsigned getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, int Index,
517 Type *SubTp) {
518 if (Kind == TTI::SK_Alternate || Kind == TTI::SK_PermuteTwoSrc ||
519 Kind == TTI::SK_PermuteSingleSrc) {
520 return getPermuteShuffleOverhead(Tp);
521 }
522 return 1;
523 }
524
525 unsigned getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src,
526 const Instruction *I = nullptr) {
527 const TargetLoweringBase *TLI = getTLI();
528 int ISD = TLI->InstructionOpcodeToISD(Opcode);
529 assert(ISD && "Invalid opcode")((ISD && "Invalid opcode") ? static_cast<void> (
0) : __assert_fail ("ISD && \"Invalid opcode\"", "/build/llvm-toolchain-snapshot-6.0~svn318211/include/llvm/CodeGen/BasicTTIImpl.h"
, 529, __PRETTY_FUNCTION__))
;
530 std::pair<unsigned, MVT> SrcLT = TLI->getTypeLegalizationCost(DL, Src);
531 std::pair<unsigned, MVT> DstLT = TLI->getTypeLegalizationCost(DL, Dst);
532
533 // Check for NOOP conversions.
534 if (SrcLT.first == DstLT.first &&
535 SrcLT.second.getSizeInBits() == DstLT.second.getSizeInBits()) {
536
537 // Bitcast between types that are legalized to the same type are free.
538 if (Opcode == Instruction::BitCast || Opcode == Instruction::Trunc)
539 return 0;
540 }
541
542 if (Opcode == Instruction::Trunc &&
543 TLI->isTruncateFree(SrcLT.second, DstLT.second))
544 return 0;
545
546 if (Opcode == Instruction::ZExt &&
547 TLI->isZExtFree(SrcLT.second, DstLT.second))
548 return 0;
549
550 if (Opcode == Instruction::AddrSpaceCast &&
551 TLI->isNoopAddrSpaceCast(Src->getPointerAddressSpace(),
552 Dst->getPointerAddressSpace()))
553 return 0;
554
555 // If this is a zext/sext of a load, return 0 if the corresponding
556 // extending load exists on target.
557 if ((Opcode == Instruction::ZExt || Opcode == Instruction::SExt) &&
558 I && isa<LoadInst>(I->getOperand(0))) {
559 EVT ExtVT = EVT::getEVT(Dst);
560 EVT LoadVT = EVT::getEVT(Src);
561 unsigned LType =
562 ((Opcode == Instruction::ZExt) ? ISD::ZEXTLOAD : ISD::SEXTLOAD);
563 if (TLI->isLoadExtLegal(LType, ExtVT, LoadVT))
564 return 0;
565 }
566
567 // If the cast is marked as legal (or promote) then assume low cost.
568 if (SrcLT.first == DstLT.first &&
569 TLI->isOperationLegalOrPromote(ISD, DstLT.second))
570 return 1;
571
572 // Handle scalar conversions.
573 if (!Src->isVectorTy() && !Dst->isVectorTy()) {
574 // Scalar bitcasts are usually free.
575 if (Opcode == Instruction::BitCast)
576 return 0;
577
578 // Just check the op cost. If the operation is legal then assume it costs
579 // 1.
580 if (!TLI->isOperationExpand(ISD, DstLT.second))
581 return 1;
582
583 // Assume that illegal scalar instruction are expensive.
584 return 4;
585 }
586
587 // Check vector-to-vector casts.
588 if (Dst->isVectorTy() && Src->isVectorTy()) {
589 // If the cast is between same-sized registers, then the check is simple.
590 if (SrcLT.first == DstLT.first &&
591 SrcLT.second.getSizeInBits() == DstLT.second.getSizeInBits()) {
592
593 // Assume that Zext is done using AND.
594 if (Opcode == Instruction::ZExt)
595 return 1;
596
597 // Assume that sext is done using SHL and SRA.
598 if (Opcode == Instruction::SExt)
599 return 2;
600
601 // Just check the op cost. If the operation is legal then assume it
602 // costs
603 // 1 and multiply by the type-legalization overhead.
604 if (!TLI->isOperationExpand(ISD, DstLT.second))
605 return SrcLT.first * 1;
606 }
607
608 // If we are legalizing by splitting, query the concrete TTI for the cost
609 // of casting the original vector twice. We also need to factor int the
610 // cost of the split itself. Count that as 1, to be consistent with
611 // TLI->getTypeLegalizationCost().
612 if ((TLI->getTypeAction(Src->getContext(), TLI->getValueType(DL, Src)) ==
613 TargetLowering::TypeSplitVector) ||
614 (TLI->getTypeAction(Dst->getContext(), TLI->getValueType(DL, Dst)) ==
615 TargetLowering::TypeSplitVector)) {
616 Type *SplitDst = VectorType::get(Dst->getVectorElementType(),
617 Dst->getVectorNumElements() / 2);
618 Type *SplitSrc = VectorType::get(Src->getVectorElementType(),
619 Src->getVectorNumElements() / 2);
620 T *TTI = static_cast<T *>(this);
621 return TTI->getVectorSplitCost() +
622 (2 * TTI->getCastInstrCost(Opcode, SplitDst, SplitSrc, I));
623 }
624
625 // In other cases where the source or destination are illegal, assume
626 // the operation will get scalarized.
627 unsigned Num = Dst->getVectorNumElements();
628 unsigned Cost = static_cast<T *>(this)->getCastInstrCost(
629 Opcode, Dst->getScalarType(), Src->getScalarType(), I);
630
631 // Return the cost of multiple scalar invocation plus the cost of
632 // inserting and extracting the values.
633 return getScalarizationOverhead(Dst, true, true) + Num * Cost;
634 }
635
636 // We already handled vector-to-vector and scalar-to-scalar conversions.
637 // This
638 // is where we handle bitcast between vectors and scalars. We need to assume
639 // that the conversion is scalarized in one way or another.
640 if (Opcode == Instruction::BitCast)
641 // Illegal bitcasts are done by storing and loading from a stack slot.
642 return (Src->isVectorTy() ? getScalarizationOverhead(Src, false, true)
643 : 0) +
644 (Dst->isVectorTy() ? getScalarizationOverhead(Dst, true, false)
645 : 0);
646
647 llvm_unreachable("Unhandled cast")::llvm::llvm_unreachable_internal("Unhandled cast", "/build/llvm-toolchain-snapshot-6.0~svn318211/include/llvm/CodeGen/BasicTTIImpl.h"
, 647)
;
648 }
649
650 unsigned getExtractWithExtendCost(unsigned Opcode, Type *Dst,
651 VectorType *VecTy, unsigned Index) {
652 return static_cast<T *>(this)->getVectorInstrCost(
653 Instruction::ExtractElement, VecTy, Index) +
654 static_cast<T *>(this)->getCastInstrCost(Opcode, Dst,
655 VecTy->getElementType());
656 }
657
658 unsigned getCFInstrCost(unsigned Opcode) {
659 // Branches are assumed to be predicted.
660 return 0;
661 }
662
663 unsigned getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy,
664 const Instruction *I) {
665 const TargetLoweringBase *TLI = getTLI();
666 int ISD = TLI->InstructionOpcodeToISD(Opcode);
667 assert(ISD && "Invalid opcode")((ISD && "Invalid opcode") ? static_cast<void> (
0) : __assert_fail ("ISD && \"Invalid opcode\"", "/build/llvm-toolchain-snapshot-6.0~svn318211/include/llvm/CodeGen/BasicTTIImpl.h"
, 667, __PRETTY_FUNCTION__))
;
668
669 // Selects on vectors are actually vector selects.
670 if (ISD == ISD::SELECT) {
671 assert(CondTy && "CondTy must exist")((CondTy && "CondTy must exist") ? static_cast<void
> (0) : __assert_fail ("CondTy && \"CondTy must exist\""
, "/build/llvm-toolchain-snapshot-6.0~svn318211/include/llvm/CodeGen/BasicTTIImpl.h"
, 671, __PRETTY_FUNCTION__))
;
672 if (CondTy->isVectorTy())
673 ISD = ISD::VSELECT;
674 }
675 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy);
676
677 if (!(ValTy->isVectorTy() && !LT.second.isVector()) &&
678 !TLI->isOperationExpand(ISD, LT.second)) {
679 // The operation is legal. Assume it costs 1. Multiply
680 // by the type-legalization overhead.
681 return LT.first * 1;
682 }
683
684 // Otherwise, assume that the cast is scalarized.
685 // TODO: If one of the types get legalized by splitting, handle this
686 // similarly to what getCastInstrCost() does.
687 if (ValTy->isVectorTy()) {
688 unsigned Num = ValTy->getVectorNumElements();
689 if (CondTy)
690 CondTy = CondTy->getScalarType();
691 unsigned Cost = static_cast<T *>(this)->getCmpSelInstrCost(
692 Opcode, ValTy->getScalarType(), CondTy, I);
693
694 // Return the cost of multiple scalar invocation plus the cost of
695 // inserting and extracting the values.
696 return getScalarizationOverhead(ValTy, true, false) + Num * Cost;
697 }
698
699 // Unknown scalar opcode.
700 return 1;
701 }
702
703 unsigned getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index) {
704 std::pair<unsigned, MVT> LT =
705 getTLI()->getTypeLegalizationCost(DL, Val->getScalarType());
706
707 return LT.first;
708 }
709
710 unsigned getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment,
711 unsigned AddressSpace, const Instruction *I = nullptr) {
712 assert(!Src->isVoidTy() && "Invalid type")((!Src->isVoidTy() && "Invalid type") ? static_cast
<void> (0) : __assert_fail ("!Src->isVoidTy() && \"Invalid type\""
, "/build/llvm-toolchain-snapshot-6.0~svn318211/include/llvm/CodeGen/BasicTTIImpl.h"
, 712, __PRETTY_FUNCTION__))
;
713 std::pair<unsigned, MVT> LT = getTLI()->getTypeLegalizationCost(DL, Src);
714
715 // Assuming that all loads of legal types cost 1.
716 unsigned Cost = LT.first;
717
718 if (Src->isVectorTy() &&
719 Src->getPrimitiveSizeInBits() < LT.second.getSizeInBits()) {
720 // This is a vector load that legalizes to a larger type than the vector
721 // itself. Unless the corresponding extending load or truncating store is
722 // legal, then this will scalarize.
723 TargetLowering::LegalizeAction LA = TargetLowering::Expand;
724 EVT MemVT = getTLI()->getValueType(DL, Src);
725 if (Opcode == Instruction::Store)
726 LA = getTLI()->getTruncStoreAction(LT.second, MemVT);
727 else
728 LA = getTLI()->getLoadExtAction(ISD::EXTLOAD, LT.second, MemVT);
729
730 if (LA != TargetLowering::Legal && LA != TargetLowering::Custom) {
731 // This is a vector load/store for some illegal type that is scalarized.
732 // We must account for the cost of building or decomposing the vector.
733 Cost += getScalarizationOverhead(Src, Opcode != Instruction::Store,
734 Opcode == Instruction::Store);
735 }
736 }
737
738 return Cost;
739 }
740
741 unsigned getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy,
742 unsigned Factor,
743 ArrayRef<unsigned> Indices,
744 unsigned Alignment,
745 unsigned AddressSpace) {
746 VectorType *VT = dyn_cast<VectorType>(VecTy);
747 assert(VT && "Expect a vector type for interleaved memory op")((VT && "Expect a vector type for interleaved memory op"
) ? static_cast<void> (0) : __assert_fail ("VT && \"Expect a vector type for interleaved memory op\""
, "/build/llvm-toolchain-snapshot-6.0~svn318211/include/llvm/CodeGen/BasicTTIImpl.h"
, 747, __PRETTY_FUNCTION__))
;
748
749 unsigned NumElts = VT->getNumElements();
750 assert(Factor > 1 && NumElts % Factor == 0 && "Invalid interleave factor")((Factor > 1 && NumElts % Factor == 0 && "Invalid interleave factor"
) ? static_cast<void> (0) : __assert_fail ("Factor > 1 && NumElts % Factor == 0 && \"Invalid interleave factor\""
, "/build/llvm-toolchain-snapshot-6.0~svn318211/include/llvm/CodeGen/BasicTTIImpl.h"
, 750, __PRETTY_FUNCTION__))
;
751
752 unsigned NumSubElts = NumElts / Factor;
753 VectorType *SubVT = VectorType::get(VT->getElementType(), NumSubElts);
754
755 // Firstly, the cost of load/store operation.
756 unsigned Cost = static_cast<T *>(this)->getMemoryOpCost(
757 Opcode, VecTy, Alignment, AddressSpace);
758
759 // Legalize the vector type, and get the legalized and unlegalized type
760 // sizes.
761 MVT VecTyLT = getTLI()->getTypeLegalizationCost(DL, VecTy).second;
762 unsigned VecTySize =
763 static_cast<T *>(this)->getDataLayout().getTypeStoreSize(VecTy);
764 unsigned VecTyLTSize = VecTyLT.getStoreSize();
765
766 // Return the ceiling of dividing A by B.
767 auto ceil = [](unsigned A, unsigned B) { return (A + B - 1) / B; };
768
769 // Scale the cost of the memory operation by the fraction of legalized
770 // instructions that will actually be used. We shouldn't account for the
771 // cost of dead instructions since they will be removed.
772 //
773 // E.g., An interleaved load of factor 8:
774 // %vec = load <16 x i64>, <16 x i64>* %ptr
775 // %v0 = shufflevector %vec, undef, <0, 8>
776 //
777 // If <16 x i64> is legalized to 8 v2i64 loads, only 2 of the loads will be
778 // used (those corresponding to elements [0:1] and [8:9] of the unlegalized
779 // type). The other loads are unused.
780 //
781 // We only scale the cost of loads since interleaved store groups aren't
782 // allowed to have gaps.
783 if (Opcode == Instruction::Load && VecTySize > VecTyLTSize) {
784 // The number of loads of a legal type it will take to represent a load
785 // of the unlegalized vector type.
786 unsigned NumLegalInsts = ceil(VecTySize, VecTyLTSize);
787
788 // The number of elements of the unlegalized type that correspond to a
789 // single legal instruction.
790 unsigned NumEltsPerLegalInst = ceil(NumElts, NumLegalInsts);
791
792 // Determine which legal instructions will be used.
793 BitVector UsedInsts(NumLegalInsts, false);
794 for (unsigned Index : Indices)
795 for (unsigned Elt = 0; Elt < NumSubElts; ++Elt)
796 UsedInsts.set((Index + Elt * Factor) / NumEltsPerLegalInst);
797
798 // Scale the cost of the load by the fraction of legal instructions that
799 // will be used.
800 Cost *= UsedInsts.count() / NumLegalInsts;
801 }
802
803 // Then plus the cost of interleave operation.
804 if (Opcode == Instruction::Load) {
805 // The interleave cost is similar to extract sub vectors' elements
806 // from the wide vector, and insert them into sub vectors.
807 //
808 // E.g. An interleaved load of factor 2 (with one member of index 0):
809 // %vec = load <8 x i32>, <8 x i32>* %ptr
810 // %v0 = shuffle %vec, undef, <0, 2, 4, 6> ; Index 0
811 // The cost is estimated as extract elements at 0, 2, 4, 6 from the
812 // <8 x i32> vector and insert them into a <4 x i32> vector.
813
814 assert(Indices.size() <= Factor &&((Indices.size() <= Factor && "Interleaved memory op has too many members"
) ? static_cast<void> (0) : __assert_fail ("Indices.size() <= Factor && \"Interleaved memory op has too many members\""
, "/build/llvm-toolchain-snapshot-6.0~svn318211/include/llvm/CodeGen/BasicTTIImpl.h"
, 815, __PRETTY_FUNCTION__))
815 "Interleaved memory op has too many members")((Indices.size() <= Factor && "Interleaved memory op has too many members"
) ? static_cast<void> (0) : __assert_fail ("Indices.size() <= Factor && \"Interleaved memory op has too many members\""
, "/build/llvm-toolchain-snapshot-6.0~svn318211/include/llvm/CodeGen/BasicTTIImpl.h"
, 815, __PRETTY_FUNCTION__))
;
816
817 for (unsigned Index : Indices) {
818 assert(Index < Factor && "Invalid index for interleaved memory op")((Index < Factor && "Invalid index for interleaved memory op"
) ? static_cast<void> (0) : __assert_fail ("Index < Factor && \"Invalid index for interleaved memory op\""
, "/build/llvm-toolchain-snapshot-6.0~svn318211/include/llvm/CodeGen/BasicTTIImpl.h"
, 818, __PRETTY_FUNCTION__))
;
819
820 // Extract elements from loaded vector for each sub vector.
821 for (unsigned i = 0; i < NumSubElts; i++)
822 Cost += static_cast<T *>(this)->getVectorInstrCost(
823 Instruction::ExtractElement, VT, Index + i * Factor);
824 }
825
826 unsigned InsSubCost = 0;
827 for (unsigned i = 0; i < NumSubElts; i++)
828 InsSubCost += static_cast<T *>(this)->getVectorInstrCost(
829 Instruction::InsertElement, SubVT, i);
830
831 Cost += Indices.size() * InsSubCost;
832 } else {
833 // The interleave cost is extract all elements from sub vectors, and
834 // insert them into the wide vector.
835 //
836 // E.g. An interleaved store of factor 2:
837 // %v0_v1 = shuffle %v0, %v1, <0, 4, 1, 5, 2, 6, 3, 7>
838 // store <8 x i32> %interleaved.vec, <8 x i32>* %ptr
839 // The cost is estimated as extract all elements from both <4 x i32>
840 // vectors and insert into the <8 x i32> vector.
841
842 unsigned ExtSubCost = 0;
843 for (unsigned i = 0; i < NumSubElts; i++)
844 ExtSubCost += static_cast<T *>(this)->getVectorInstrCost(
845 Instruction::ExtractElement, SubVT, i);
846 Cost += ExtSubCost * Factor;
847
848 for (unsigned i = 0; i < NumElts; i++)
849 Cost += static_cast<T *>(this)
850 ->getVectorInstrCost(Instruction::InsertElement, VT, i);
851 }
852
853 return Cost;
854 }
855
856 /// Get intrinsic cost based on arguments.
857 unsigned getIntrinsicInstrCost(Intrinsic::ID IID, Type *RetTy,
858 ArrayRef<Value *> Args, FastMathFlags FMF,
859 unsigned VF = 1) {
860 unsigned RetVF = (RetTy->isVectorTy() ? RetTy->getVectorNumElements() : 1);
861 assert((RetVF == 1 || VF == 1) && "VF > 1 and RetVF is a vector type")(((RetVF == 1 || VF == 1) && "VF > 1 and RetVF is a vector type"
) ? static_cast<void> (0) : __assert_fail ("(RetVF == 1 || VF == 1) && \"VF > 1 and RetVF is a vector type\""
, "/build/llvm-toolchain-snapshot-6.0~svn318211/include/llvm/CodeGen/BasicTTIImpl.h"
, 861, __PRETTY_FUNCTION__))
;
862
863 switch (IID) {
864 default: {
865 // Assume that we need to scalarize this intrinsic.
866 SmallVector<Type *, 4> Types;
867 for (Value *Op : Args) {
868 Type *OpTy = Op->getType();
869 assert(VF == 1 || !OpTy->isVectorTy())((VF == 1 || !OpTy->isVectorTy()) ? static_cast<void>
(0) : __assert_fail ("VF == 1 || !OpTy->isVectorTy()", "/build/llvm-toolchain-snapshot-6.0~svn318211/include/llvm/CodeGen/BasicTTIImpl.h"
, 869, __PRETTY_FUNCTION__))
;
870 Types.push_back(VF == 1 ? OpTy : VectorType::get(OpTy, VF));
871 }
872
873 if (VF > 1 && !RetTy->isVoidTy())
874 RetTy = VectorType::get(RetTy, VF);
875
876 // Compute the scalarization overhead based on Args for a vector
877 // intrinsic. A vectorizer will pass a scalar RetTy and VF > 1, while
878 // CostModel will pass a vector RetTy and VF is 1.
879 unsigned ScalarizationCost = std::numeric_limits<unsigned>::max();
880 if (RetVF > 1 || VF > 1) {
881 ScalarizationCost = 0;
882 if (!RetTy->isVoidTy())
883 ScalarizationCost += getScalarizationOverhead(RetTy, true, false);
884 ScalarizationCost += getOperandsScalarizationOverhead(Args, VF);
885 }
886
887 return static_cast<T *>(this)->
888 getIntrinsicInstrCost(IID, RetTy, Types, FMF, ScalarizationCost);
889 }
890 case Intrinsic::masked_scatter: {
891 assert(VF == 1 && "Can't vectorize types here.")((VF == 1 && "Can't vectorize types here.") ? static_cast
<void> (0) : __assert_fail ("VF == 1 && \"Can't vectorize types here.\""
, "/build/llvm-toolchain-snapshot-6.0~svn318211/include/llvm/CodeGen/BasicTTIImpl.h"
, 891, __PRETTY_FUNCTION__))
;
892 Value *Mask = Args[3];
893 bool VarMask = !isa<Constant>(Mask);
894 unsigned Alignment = cast<ConstantInt>(Args[2])->getZExtValue();
895 return
896 static_cast<T *>(this)->getGatherScatterOpCost(Instruction::Store,
897 Args[0]->getType(),
898 Args[1], VarMask,
899 Alignment);
900 }
901 case Intrinsic::masked_gather: {
902 assert(VF == 1 && "Can't vectorize types here.")((VF == 1 && "Can't vectorize types here.") ? static_cast
<void> (0) : __assert_fail ("VF == 1 && \"Can't vectorize types here.\""
, "/build/llvm-toolchain-snapshot-6.0~svn318211/include/llvm/CodeGen/BasicTTIImpl.h"
, 902, __PRETTY_FUNCTION__))
;
903 Value *Mask = Args[2];
904 bool VarMask = !isa<Constant>(Mask);
905 unsigned Alignment = cast<ConstantInt>(Args[1])->getZExtValue();
906 return
907 static_cast<T *>(this)->getGatherScatterOpCost(Instruction::Load,
908 RetTy, Args[0], VarMask,
909 Alignment);
910 }
911 }
912 }
913
914 /// Get intrinsic cost based on argument types.
915 /// If ScalarizationCostPassed is std::numeric_limits<unsigned>::max(), the
916 /// cost of scalarizing the arguments and the return value will be computed
917 /// based on types.
918 unsigned getIntrinsicInstrCost(
919 Intrinsic::ID IID, Type *RetTy, ArrayRef<Type *> Tys, FastMathFlags FMF,
920 unsigned ScalarizationCostPassed = std::numeric_limits<unsigned>::max()) {
921 SmallVector<unsigned, 2> ISDs;
922 unsigned SingleCallCost = 10; // Library call cost. Make it expensive.
923 switch (IID) {
924 default: {
925 // Assume that we need to scalarize this intrinsic.
926 unsigned ScalarizationCost = ScalarizationCostPassed;
927 unsigned ScalarCalls = 1;
928 Type *ScalarRetTy = RetTy;
929 if (RetTy->isVectorTy()) {
930 if (ScalarizationCostPassed == std::numeric_limits<unsigned>::max())
931 ScalarizationCost = getScalarizationOverhead(RetTy, true, false);
932 ScalarCalls = std::max(ScalarCalls, RetTy->getVectorNumElements());
933 ScalarRetTy = RetTy->getScalarType();
934 }
935 SmallVector<Type *, 4> ScalarTys;
936 for (unsigned i = 0, ie = Tys.size(); i != ie; ++i) {
937 Type *Ty = Tys[i];
938 if (Ty->isVectorTy()) {
939 if (ScalarizationCostPassed == std::numeric_limits<unsigned>::max())
940 ScalarizationCost += getScalarizationOverhead(Ty, false, true);
941 ScalarCalls = std::max(ScalarCalls, Ty->getVectorNumElements());
942 Ty = Ty->getScalarType();
943 }
944 ScalarTys.push_back(Ty);
945 }
946 if (ScalarCalls == 1)
947 return 1; // Return cost of a scalar intrinsic. Assume it to be cheap.
948
949 unsigned ScalarCost = static_cast<T *>(this)->getIntrinsicInstrCost(
950 IID, ScalarRetTy, ScalarTys, FMF);
951
952 return ScalarCalls * ScalarCost + ScalarizationCost;
953 }
954 // Look for intrinsics that can be lowered directly or turned into a scalar
955 // intrinsic call.
956 case Intrinsic::sqrt:
957 ISDs.push_back(ISD::FSQRT);
958 break;
959 case Intrinsic::sin:
960 ISDs.push_back(ISD::FSIN);
961 break;
962 case Intrinsic::cos:
963 ISDs.push_back(ISD::FCOS);
964 break;
965 case Intrinsic::exp:
966 ISDs.push_back(ISD::FEXP);
967 break;
968 case Intrinsic::exp2:
969 ISDs.push_back(ISD::FEXP2);
970 break;
971 case Intrinsic::log:
972 ISDs.push_back(ISD::FLOG);
973 break;
974 case Intrinsic::log10:
975 ISDs.push_back(ISD::FLOG10);
976 break;
977 case Intrinsic::log2:
978 ISDs.push_back(ISD::FLOG2);
979 break;
980 case Intrinsic::fabs:
981 ISDs.push_back(ISD::FABS);
982 break;
983 case Intrinsic::minnum:
984 ISDs.push_back(ISD::FMINNUM);
985 if (FMF.noNaNs())
986 ISDs.push_back(ISD::FMINNAN);
987 break;
988 case Intrinsic::maxnum:
989 ISDs.push_back(ISD::FMAXNUM);
990 if (FMF.noNaNs())
991 ISDs.push_back(ISD::FMAXNAN);
992 break;
993 case Intrinsic::copysign:
994 ISDs.push_back(ISD::FCOPYSIGN);
995 break;
996 case Intrinsic::floor:
997 ISDs.push_back(ISD::FFLOOR);
998 break;
999 case Intrinsic::ceil:
1000 ISDs.push_back(ISD::FCEIL);
1001 break;
1002 case Intrinsic::trunc:
1003 ISDs.push_back(ISD::FTRUNC);
1004 break;
1005 case Intrinsic::nearbyint:
1006 ISDs.push_back(ISD::FNEARBYINT);
1007 break;
1008 case Intrinsic::rint:
1009 ISDs.push_back(ISD::FRINT);
1010 break;
1011 case Intrinsic::round:
1012 ISDs.push_back(ISD::FROUND);
1013 break;
1014 case Intrinsic::pow:
1015 ISDs.push_back(ISD::FPOW);
1016 break;
1017 case Intrinsic::fma:
1018 ISDs.push_back(ISD::FMA);
1019 break;
1020 case Intrinsic::fmuladd:
1021 ISDs.push_back(ISD::FMA);
1022 break;
1023 // FIXME: We should return 0 whenever getIntrinsicCost == TCC_Free.
1024 case Intrinsic::lifetime_start:
1025 case Intrinsic::lifetime_end:
1026 case Intrinsic::sideeffect:
1027 return 0;
1028 case Intrinsic::masked_store:
1029 return static_cast<T *>(this)
1030 ->getMaskedMemoryOpCost(Instruction::Store, Tys[0], 0, 0);
1031 case Intrinsic::masked_load:
1032 return static_cast<T *>(this)
1033 ->getMaskedMemoryOpCost(Instruction::Load, RetTy, 0, 0);
1034 case Intrinsic::ctpop:
1035 ISDs.push_back(ISD::CTPOP);
1036 // In case of legalization use TCC_Expensive. This is cheaper than a
1037 // library call but still not a cheap instruction.
1038 SingleCallCost = TargetTransformInfo::TCC_Expensive;
1039 break;
1040 // FIXME: ctlz, cttz, ...
1041 }
1042
1043 const TargetLoweringBase *TLI = getTLI();
1044 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(DL, RetTy);
1045
1046 SmallVector<unsigned, 2> LegalCost;
1047 SmallVector<unsigned, 2> CustomCost;
1048 for (unsigned ISD : ISDs) {
1049 if (TLI->isOperationLegalOrPromote(ISD, LT.second)) {
1050 if (IID == Intrinsic::fabs && TLI->isFAbsFree(LT.second)) {
1051 return 0;
1052 }
1053
1054 // The operation is legal. Assume it costs 1.
1055 // If the type is split to multiple registers, assume that there is some
1056 // overhead to this.
1057 // TODO: Once we have extract/insert subvector cost we need to use them.
1058 if (LT.first > 1)
1059 LegalCost.push_back(LT.first * 2);
1060 else
1061 LegalCost.push_back(LT.first * 1);
1062 } else if (!TLI->isOperationExpand(ISD, LT.second)) {
1063 // If the operation is custom lowered then assume
1064 // that the code is twice as expensive.
1065 CustomCost.push_back(LT.first * 2);
1066 }
1067 }
1068
1069 auto MinLegalCostI = std::min_element(LegalCost.begin(), LegalCost.end());
1070 if (MinLegalCostI != LegalCost.end())
1071 return *MinLegalCostI;
1072
1073 auto MinCustomCostI = std::min_element(CustomCost.begin(), CustomCost.end());
1074 if (MinCustomCostI != CustomCost.end())
1075 return *MinCustomCostI;
1076
1077 // If we can't lower fmuladd into an FMA estimate the cost as a floating
1078 // point mul followed by an add.
1079 if (IID == Intrinsic::fmuladd)
1080 return static_cast<T *>(this)
1081 ->getArithmeticInstrCost(BinaryOperator::FMul, RetTy) +
1082 static_cast<T *>(this)
1083 ->getArithmeticInstrCost(BinaryOperator::FAdd, RetTy);
1084
1085 // Else, assume that we need to scalarize this intrinsic. For math builtins
1086 // this will emit a costly libcall, adding call overhead and spills. Make it
1087 // very expensive.
1088 if (RetTy->isVectorTy()) {
1089 unsigned ScalarizationCost =
1090 ((ScalarizationCostPassed != std::numeric_limits<unsigned>::max())
1091 ? ScalarizationCostPassed
1092 : getScalarizationOverhead(RetTy, true, false));
1093 unsigned ScalarCalls = RetTy->getVectorNumElements();
1094 SmallVector<Type *, 4> ScalarTys;
1095 for (unsigned i = 0, ie = Tys.size(); i != ie; ++i) {
1096 Type *Ty = Tys[i];
1097 if (Ty->isVectorTy())
1098 Ty = Ty->getScalarType();
1099 ScalarTys.push_back(Ty);
1100 }
1101 unsigned ScalarCost = static_cast<T *>(this)->getIntrinsicInstrCost(
1102 IID, RetTy->getScalarType(), ScalarTys, FMF);
1103 for (unsigned i = 0, ie = Tys.size(); i != ie; ++i) {
1104 if (Tys[i]->isVectorTy()) {
1105 if (ScalarizationCostPassed == std::numeric_limits<unsigned>::max())
1106 ScalarizationCost += getScalarizationOverhead(Tys[i], false, true);
1107 ScalarCalls = std::max(ScalarCalls, Tys[i]->getVectorNumElements());
1108 }
1109 }
1110
1111 return ScalarCalls * ScalarCost + ScalarizationCost;
1112 }
1113
1114 // This is going to be turned into a library call, make it expensive.
1115 return SingleCallCost;
1116 }
1117
1118 /// \brief Compute a cost of the given call instruction.
1119 ///
1120 /// Compute the cost of calling function F with return type RetTy and
1121 /// argument types Tys. F might be nullptr, in this case the cost of an
1122 /// arbitrary call with the specified signature will be returned.
1123 /// This is used, for instance, when we estimate call of a vector
1124 /// counterpart of the given function.
1125 /// \param F Called function, might be nullptr.
1126 /// \param RetTy Return value types.
1127 /// \param Tys Argument types.
1128 /// \returns The cost of Call instruction.
1129 unsigned getCallInstrCost(Function *F, Type *RetTy, ArrayRef<Type *> Tys) {
1130 return 10;
1131 }
1132
1133 unsigned getNumberOfParts(Type *Tp) {
1134 std::pair<unsigned, MVT> LT = getTLI()->getTypeLegalizationCost(DL, Tp);
1135 return LT.first;
1136 }
1137
1138 unsigned getAddressComputationCost(Type *Ty, ScalarEvolution *,
1139 const SCEV *) {
1140 return 0;
1141 }
1142
1143 /// Try to calculate arithmetic and shuffle op costs for reduction operations.
1144 /// We're assuming that reduction operation are performing the following way:
1145 /// 1. Non-pairwise reduction
1146 /// %val1 = shufflevector<n x t> %val, <n x t> %undef,
1147 /// <n x i32> <i32 n/2, i32 n/2 + 1, ..., i32 n, i32 undef, ..., i32 undef>
1148 /// \----------------v-------------/ \----------v------------/
1149 /// n/2 elements n/2 elements
1150 /// %red1 = op <n x t> %val, <n x t> val1
1151 /// After this operation we have a vector %red1 where only the first n/2
1152 /// elements are meaningful, the second n/2 elements are undefined and can be
1153 /// dropped. All other operations are actually working with the vector of
1154 /// length n/2, not n, though the real vector length is still n.
1155 /// %val2 = shufflevector<n x t> %red1, <n x t> %undef,
1156 /// <n x i32> <i32 n/4, i32 n/4 + 1, ..., i32 n/2, i32 undef, ..., i32 undef>
1157 /// \----------------v-------------/ \----------v------------/
1158 /// n/4 elements 3*n/4 elements
1159 /// %red2 = op <n x t> %red1, <n x t> val2 - working with the vector of
1160 /// length n/2, the resulting vector has length n/4 etc.
1161 /// 2. Pairwise reduction:
1162 /// Everything is the same except for an additional shuffle operation which
1163 /// is used to produce operands for pairwise kind of reductions.
1164 /// %val1 = shufflevector<n x t> %val, <n x t> %undef,
1165 /// <n x i32> <i32 0, i32 2, ..., i32 n-2, i32 undef, ..., i32 undef>
1166 /// \-------------v----------/ \----------v------------/
1167 /// n/2 elements n/2 elements
1168 /// %val2 = shufflevector<n x t> %val, <n x t> %undef,
1169 /// <n x i32> <i32 1, i32 3, ..., i32 n-1, i32 undef, ..., i32 undef>
1170 /// \-------------v----------/ \----------v------------/
1171 /// n/2 elements n/2 elements
1172 /// %red1 = op <n x t> %val1, <n x t> val2
1173 /// Again, the operation is performed on <n x t> vector, but the resulting
1174 /// vector %red1 is <n/2 x t> vector.
1175 ///
1176 /// The cost model should take into account that the actual length of the
1177 /// vector is reduced on each iteration.
1178 unsigned getArithmeticReductionCost(unsigned Opcode, Type *Ty,
1179 bool IsPairwise) {
1180 assert(Ty->isVectorTy() && "Expect a vector type")((Ty->isVectorTy() && "Expect a vector type") ? static_cast
<void> (0) : __assert_fail ("Ty->isVectorTy() && \"Expect a vector type\""
, "/build/llvm-toolchain-snapshot-6.0~svn318211/include/llvm/CodeGen/BasicTTIImpl.h"
, 1180, __PRETTY_FUNCTION__))
;
1181 Type *ScalarTy = Ty->getVectorElementType();
1182 unsigned NumVecElts = Ty->getVectorNumElements();
1183 unsigned NumReduxLevels = Log2_32(NumVecElts);
1184 unsigned ArithCost = 0;
1185 unsigned ShuffleCost = 0;
1186 auto *ConcreteTTI = static_cast<T *>(this);
1187 std::pair<unsigned, MVT> LT =
1188 ConcreteTTI->getTLI()->getTypeLegalizationCost(DL, Ty);
1189 unsigned LongVectorCount = 0;
1190 unsigned MVTLen =
1191 LT.second.isVector() ? LT.second.getVectorNumElements() : 1;
1192 while (NumVecElts > MVTLen) {
1193 NumVecElts /= 2;
1194 // Assume the pairwise shuffles add a cost.
1195 ShuffleCost += (IsPairwise + 1) *
1196 ConcreteTTI->getShuffleCost(TTI::SK_ExtractSubvector, Ty,
1197 NumVecElts, Ty);
1198 ArithCost += ConcreteTTI->getArithmeticInstrCost(Opcode, Ty);
1199 Ty = VectorType::get(ScalarTy, NumVecElts);
1200 ++LongVectorCount;
1201 }
1202 // The minimal length of the vector is limited by the real length of vector
1203 // operations performed on the current platform. That's why several final
1204 // reduction operations are performed on the vectors with the same
1205 // architecture-dependent length.
1206 ShuffleCost += (NumReduxLevels - LongVectorCount) * (IsPairwise + 1) *
1207 ConcreteTTI->getShuffleCost(TTI::SK_ExtractSubvector, Ty,
1208 NumVecElts, Ty);
1209 ArithCost += (NumReduxLevels - LongVectorCount) *
1210 ConcreteTTI->getArithmeticInstrCost(Opcode, Ty);
1211 return ShuffleCost + ArithCost + getScalarizationOverhead(Ty, false, true);
1212 }
1213
1214 /// Try to calculate op costs for min/max reduction operations.
1215 /// \param CondTy Conditional type for the Select instruction.
1216 unsigned getMinMaxReductionCost(Type *Ty, Type *CondTy, bool IsPairwise,
1217 bool) {
1218 assert(Ty->isVectorTy() && "Expect a vector type")((Ty->isVectorTy() && "Expect a vector type") ? static_cast
<void> (0) : __assert_fail ("Ty->isVectorTy() && \"Expect a vector type\""
, "/build/llvm-toolchain-snapshot-6.0~svn318211/include/llvm/CodeGen/BasicTTIImpl.h"
, 1218, __PRETTY_FUNCTION__))
;
1219 Type *ScalarTy = Ty->getVectorElementType();
1220 Type *ScalarCondTy = CondTy->getVectorElementType();
1221 unsigned NumVecElts = Ty->getVectorNumElements();
1222 unsigned NumReduxLevels = Log2_32(NumVecElts);
1223 unsigned CmpOpcode;
1224 if (Ty->isFPOrFPVectorTy()) {
1225 CmpOpcode = Instruction::FCmp;
1226 } else {
1227 assert(Ty->isIntOrIntVectorTy() &&((Ty->isIntOrIntVectorTy() && "expecting floating point or integer type for min/max reduction"
) ? static_cast<void> (0) : __assert_fail ("Ty->isIntOrIntVectorTy() && \"expecting floating point or integer type for min/max reduction\""
, "/build/llvm-toolchain-snapshot-6.0~svn318211/include/llvm/CodeGen/BasicTTIImpl.h"
, 1228, __PRETTY_FUNCTION__))
1228 "expecting floating point or integer type for min/max reduction")((Ty->isIntOrIntVectorTy() && "expecting floating point or integer type for min/max reduction"
) ? static_cast<void> (0) : __assert_fail ("Ty->isIntOrIntVectorTy() && \"expecting floating point or integer type for min/max reduction\""
, "/build/llvm-toolchain-snapshot-6.0~svn318211/include/llvm/CodeGen/BasicTTIImpl.h"
, 1228, __PRETTY_FUNCTION__))
;
1229 CmpOpcode = Instruction::ICmp;
1230 }
1231 unsigned MinMaxCost = 0;
1232 unsigned ShuffleCost = 0;
1233 auto *ConcreteTTI = static_cast<T *>(this);
1234 std::pair<unsigned, MVT> LT =
1235 ConcreteTTI->getTLI()->getTypeLegalizationCost(DL, Ty);
1236 unsigned LongVectorCount = 0;
1237 unsigned MVTLen =
1238 LT.second.isVector() ? LT.second.getVectorNumElements() : 1;
1239 while (NumVecElts > MVTLen) {
1240 NumVecElts /= 2;
1241 // Assume the pairwise shuffles add a cost.
1242 ShuffleCost += (IsPairwise + 1) *
1243 ConcreteTTI->getShuffleCost(TTI::SK_ExtractSubvector, Ty,
1244 NumVecElts, Ty);
1245 MinMaxCost +=
1246 ConcreteTTI->getCmpSelInstrCost(CmpOpcode, Ty, CondTy, nullptr) +
1247 ConcreteTTI->getCmpSelInstrCost(Instruction::Select, Ty, CondTy,
1248 nullptr);
1249 Ty = VectorType::get(ScalarTy, NumVecElts);
1250 CondTy = VectorType::get(ScalarCondTy, NumVecElts);
1251 ++LongVectorCount;
1252 }
1253 // The minimal length of the vector is limited by the real length of vector
1254 // operations performed on the current platform. That's why several final
1255 // reduction opertions are perfomed on the vectors with the same
1256 // architecture-dependent length.
1257 ShuffleCost += (NumReduxLevels - LongVectorCount) * (IsPairwise + 1) *
1258 ConcreteTTI->getShuffleCost(TTI::SK_ExtractSubvector, Ty,
1259 NumVecElts, Ty);
1260 MinMaxCost +=
1261 (NumReduxLevels - LongVectorCount) *
1262 (ConcreteTTI->getCmpSelInstrCost(CmpOpcode, Ty, CondTy, nullptr) +
1263 ConcreteTTI->getCmpSelInstrCost(Instruction::Select, Ty, CondTy,
1264 nullptr));
1265 // Need 3 extractelement instructions for scalarization + an additional
1266 // scalar select instruction.
1267 return ShuffleCost + MinMaxCost +
1268 3 * getScalarizationOverhead(Ty, /*Insert=*/false,
1269 /*Extract=*/true) +
1270 ConcreteTTI->getCmpSelInstrCost(Instruction::Select, ScalarTy,
1271 ScalarCondTy, nullptr);
1272 }
1273
1274 unsigned getVectorSplitCost() { return 1; }
1275
1276 /// @}
1277};
1278
1279/// \brief Concrete BasicTTIImpl that can be used if no further customization
1280/// is needed.
1281class BasicTTIImpl : public BasicTTIImplBase<BasicTTIImpl> {
1282 using BaseT = BasicTTIImplBase<BasicTTIImpl>;
1283
1284 friend class BasicTTIImplBase<BasicTTIImpl>;
1285
1286 const TargetSubtargetInfo *ST;
1287 const TargetLoweringBase *TLI;
1288
1289 const TargetSubtargetInfo *getST() const { return ST; }
1290 const TargetLoweringBase *getTLI() const { return TLI; }
1291
1292public:
1293 explicit BasicTTIImpl(const TargetMachine *ST, const Function &F);
1294};
1295
1296} // end namespace llvm
1297
1298#endif // LLVM_CODEGEN_BASICTTIIMPL_H