Bug Summary

File:projects/compiler-rt/lib/scudo/scudo_utils.cpp
Warning:line 63, column 29
The left operand of '==' is a garbage value

Annotated Source Code

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clang -cc1 -triple i386-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name scudo_utils.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-eagerly-assume -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -mrelocation-model pic -pic-level 2 -mthread-model posix -fmath-errno -masm-verbose -mconstructor-aliases -munwind-tables -fuse-init-array -target-cpu pentium4 -dwarf-column-info -debugger-tuning=gdb -momit-leaf-frame-pointer -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-7/lib/clang/7.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-7~svn329677/build-llvm/projects/compiler-rt/lib/scudo -I /build/llvm-toolchain-snapshot-7~svn329677/projects/compiler-rt/lib/scudo -I /build/llvm-toolchain-snapshot-7~svn329677/build-llvm/include -I /build/llvm-toolchain-snapshot-7~svn329677/include -I /build/llvm-toolchain-snapshot-7~svn329677/projects/compiler-rt/lib/scudo/.. -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/7.3.0/../../../../include/c++/7.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/7.3.0/../../../../include/x86_64-linux-gnu/c++/7.3.0/32 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/7.3.0/../../../../include/i386-pc-linux-gnu/c++/7.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/7.3.0/../../../../include/c++/7.3.0/backward -internal-isystem /usr/include/clang/7.0.0/include/ -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-7/lib/clang/7.0.0/include -internal-externc-isystem /include -internal-externc-isystem /usr/include -O3 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -Wno-unused-parameter -Wno-variadic-macros -Wno-non-virtual-dtor -std=c++11 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-7~svn329677/build-llvm/projects/compiler-rt/lib/scudo -ferror-limit 19 -fmessage-length 0 -fvisibility hidden -fvisibility-inlines-hidden -fno-rtti -fobjc-runtime=gcc -fdiagnostics-show-option -vectorize-loops -vectorize-slp -analyzer-checker optin.performance.Padding -analyzer-output=html -analyzer-config stable-report-filename=true -o /tmp/scan-build-2018-04-11-031539-24776-1 -x c++ /build/llvm-toolchain-snapshot-7~svn329677/projects/compiler-rt/lib/scudo/scudo_utils.cpp

/build/llvm-toolchain-snapshot-7~svn329677/projects/compiler-rt/lib/scudo/scudo_utils.cpp

1//===-- scudo_utils.cpp -----------------------------------------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9///
10/// Platform specific utility functions.
11///
12//===----------------------------------------------------------------------===//
13
14#include "scudo_utils.h"
15
16#if defined(__x86_64__) || defined(__i386__1)
17# include <cpuid.h>
18#elif defined(__arm__) || defined(__aarch64__)
19# include "sanitizer_common/sanitizer_getauxval.h"
20# if SANITIZER_POSIX(0 || 1 || 0 || 0 || 0 || 0)
21# include "sanitizer_common/sanitizer_posix.h"
22# include <fcntl.h>
23# endif
24#endif
25
26#include <stdarg.h>
27
28// TODO(kostyak): remove __sanitizer *Printf uses in favor for our own less
29// complicated string formatting code. The following is a
30// temporary workaround to be able to use __sanitizer::VSNPrintf.
31namespace __sanitizer {
32
33extern int VSNPrintf(char *buff, int buff_length, const char *format,
34 va_list args);
35
36} // namespace __sanitizer
37
38namespace __scudo {
39
40FORMAT(1, 2)__attribute__((format(printf, 1, 2))) void NORETURN__attribute__((noreturn)) dieWithMessage(const char *Format, ...) {
41 static const char ScudoError[] = "Scudo ERROR: ";
42 static constexpr uptr PrefixSize = sizeof(ScudoError) - 1;
43 // Our messages are tiny, 256 characters is more than enough.
44 char Message[256];
45 va_list Args;
46 va_start(Args, Format)__builtin_va_start(Args, Format);
47 internal_memcpy(Message, ScudoError, PrefixSize);
48 VSNPrintf(Message + PrefixSize, sizeof(Message) - PrefixSize, Format, Args);
49 va_end(Args)__builtin_va_end(Args);
50 RawWrite(Message);
51 Die();
52}
53
54#if defined(__x86_64__) || defined(__i386__1)
55// i386 and x86_64 specific code to detect CRC32 hardware support via CPUID.
56// CRC32 requires the SSE 4.2 instruction set.
57# ifndef bit_SSE4_20x00100000
58# define bit_SSE4_20x00100000 bit_SSE420x00100000 // clang and gcc have different defines.
59# endif
60bool hasHardwareCRC32() {
61 u32 Eax, Ebx, Ecx, Edx;
1
'Ebx' declared without an initial value
62 __get_cpuid(0, &Eax, &Ebx, &Ecx, &Edx);
2
Calling '__get_cpuid'
4
Returning from '__get_cpuid'
63 const bool IsIntel = (Ebx == signature_INTEL_ebx0x756e6547) &&
5
The left operand of '==' is a garbage value
64 (Edx == signature_INTEL_edx0x49656e69) &&
65 (Ecx == signature_INTEL_ecx0x6c65746e);
66 const bool IsAMD = (Ebx == signature_AMD_ebx0x68747541) &&
67 (Edx == signature_AMD_edx0x69746e65) &&
68 (Ecx == signature_AMD_ecx0x444d4163);
69 if (!IsIntel && !IsAMD)
70 return false;
71 __get_cpuid(1, &Eax, &Ebx, &Ecx, &Edx);
72 return !!(Ecx & bit_SSE4_20x00100000);
73}
74#elif defined(__arm__) || defined(__aarch64__)
75// For ARM and AArch64, hardware CRC32 support is indicated in the AT_HWCAP
76// auxiliary vector.
77# ifndef AT_HWCAP
78# define AT_HWCAP 16
79# endif
80# ifndef HWCAP_CRC32
81# define HWCAP_CRC32 (1 << 7) // HWCAP_CRC32 is missing on older platforms.
82# endif
83# if SANITIZER_POSIX(0 || 1 || 0 || 0 || 0 || 0)
84bool hasHardwareCRC32ARMPosix() {
85 uptr F = internal_open("/proc/self/auxv", O_RDONLY);
86 if (internal_iserror(F))
87 return false;
88 struct { uptr Tag; uptr Value; } Entry = { 0, 0 };
89 for (;;) {
90 uptr N = internal_read(F, &Entry, sizeof(Entry));
91 if (internal_iserror(N) || N != sizeof(Entry) ||
92 (Entry.Tag == 0 && Entry.Value == 0) || Entry.Tag == AT_HWCAP)
93 break;
94 }
95 internal_close(F);
96 return (Entry.Tag == AT_HWCAP && (Entry.Value & HWCAP_CRC32) != 0);
97}
98# else
99bool hasHardwareCRC32ARMPosix() { return false; }
100# endif // SANITIZER_POSIX
101
102// Bionic doesn't initialize its globals early enough. This causes issues when
103// trying to access them from a preinit_array (b/25751302) or from another
104// constructor called before the libc one (b/68046352). __progname is
105// initialized after the other globals, so we can check its value to know if
106// calling getauxval is safe.
107extern "C" SANITIZER_WEAK_ATTRIBUTE__attribute__((weak)) char *__progname;
108INLINEinline bool areBionicGlobalsInitialized() {
109 return !SANITIZER_ANDROID0 || (&__progname && __progname);
110}
111
112bool hasHardwareCRC32() {
113 if (&getauxval && areBionicGlobalsInitialized())
114 return !!(getauxval(AT_HWCAP) & HWCAP_CRC32);
115 return hasHardwareCRC32ARMPosix();
116}
117#else
118bool hasHardwareCRC32() { return false; }
119#endif // defined(__x86_64__) || defined(__i386__)
120
121} // namespace __scudo

/usr/include/clang/7.0.0/include/cpuid.h

1/*===---- cpuid.h - X86 cpu model detection --------------------------------===
2 *
3 * Permission is hereby granted, free of charge, to any person obtaining a copy
4 * of this software and associated documentation files (the "Software"), to deal
5 * in the Software without restriction, including without limitation the rights
6 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
7 * copies of the Software, and to permit persons to whom the Software is
8 * furnished to do so, subject to the following conditions:
9 *
10 * The above copyright notice and this permission notice shall be included in
11 * all copies or substantial portions of the Software.
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
16 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
17 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
18 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
19 * THE SOFTWARE.
20 *
21 *===-----------------------------------------------------------------------===
22 */
23
24#if !(__x86_64__ || __i386__1)
25#error this header is for x86 only
26#endif
27
28/* Responses identification request with %eax 0 */
29/* AMD: "AuthenticAMD" */
30#define signature_AMD_ebx0x68747541 0x68747541
31#define signature_AMD_edx0x69746e65 0x69746e65
32#define signature_AMD_ecx0x444d4163 0x444d4163
33/* CENTAUR: "CentaurHauls" */
34#define signature_CENTAUR_ebx0x746e6543 0x746e6543
35#define signature_CENTAUR_edx0x48727561 0x48727561
36#define signature_CENTAUR_ecx0x736c7561 0x736c7561
37/* CYRIX: "CyrixInstead" */
38#define signature_CYRIX_ebx0x69727943 0x69727943
39#define signature_CYRIX_edx0x736e4978 0x736e4978
40#define signature_CYRIX_ecx0x64616574 0x64616574
41/* INTEL: "GenuineIntel" */
42#define signature_INTEL_ebx0x756e6547 0x756e6547
43#define signature_INTEL_edx0x49656e69 0x49656e69
44#define signature_INTEL_ecx0x6c65746e 0x6c65746e
45/* TM1: "TransmetaCPU" */
46#define signature_TM1_ebx0x6e617254 0x6e617254
47#define signature_TM1_edx0x74656d73 0x74656d73
48#define signature_TM1_ecx0x55504361 0x55504361
49/* TM2: "GenuineTMx86" */
50#define signature_TM2_ebx0x756e6547 0x756e6547
51#define signature_TM2_edx0x54656e69 0x54656e69
52#define signature_TM2_ecx0x3638784d 0x3638784d
53/* NSC: "Geode by NSC" */
54#define signature_NSC_ebx0x646f6547 0x646f6547
55#define signature_NSC_edx0x43534e20 0x43534e20
56#define signature_NSC_ecx0x79622065 0x79622065
57/* NEXGEN: "NexGenDriven" */
58#define signature_NEXGEN_ebx0x4778654e 0x4778654e
59#define signature_NEXGEN_edx0x72446e65 0x72446e65
60#define signature_NEXGEN_ecx0x6e657669 0x6e657669
61/* RISE: "RiseRiseRise" */
62#define signature_RISE_ebx0x65736952 0x65736952
63#define signature_RISE_edx0x65736952 0x65736952
64#define signature_RISE_ecx0x65736952 0x65736952
65/* SIS: "SiS SiS SiS " */
66#define signature_SIS_ebx0x20536953 0x20536953
67#define signature_SIS_edx0x20536953 0x20536953
68#define signature_SIS_ecx0x20536953 0x20536953
69/* UMC: "UMC UMC UMC " */
70#define signature_UMC_ebx0x20434d55 0x20434d55
71#define signature_UMC_edx0x20434d55 0x20434d55
72#define signature_UMC_ecx0x20434d55 0x20434d55
73/* VIA: "VIA VIA VIA " */
74#define signature_VIA_ebx0x20414956 0x20414956
75#define signature_VIA_edx0x20414956 0x20414956
76#define signature_VIA_ecx0x20414956 0x20414956
77/* VORTEX: "Vortex86 SoC" */
78#define signature_VORTEX_ebx0x74726f56 0x74726f56
79#define signature_VORTEX_edx0x36387865 0x36387865
80#define signature_VORTEX_ecx0x436f5320 0x436f5320
81
82/* Features in %ecx for leaf 1 */
83#define bit_SSE30x00000001 0x00000001
84#define bit_PCLMULQDQ0x00000002 0x00000002
85#define bit_PCLMUL0x00000002 bit_PCLMULQDQ0x00000002 /* for gcc compat */
86#define bit_DTES640x00000004 0x00000004
87#define bit_MONITOR0x00000008 0x00000008
88#define bit_DSCPL0x00000010 0x00000010
89#define bit_VMX0x00000020 0x00000020
90#define bit_SMX0x00000040 0x00000040
91#define bit_EIST0x00000080 0x00000080
92#define bit_TM20x00000100 0x00000100
93#define bit_SSSE30x00000200 0x00000200
94#define bit_CNXTID0x00000400 0x00000400
95#define bit_FMA0x00001000 0x00001000
96#define bit_CMPXCHG16B0x00002000 0x00002000
97#define bit_xTPR0x00004000 0x00004000
98#define bit_PDCM0x00008000 0x00008000
99#define bit_PCID0x00020000 0x00020000
100#define bit_DCA0x00040000 0x00040000
101#define bit_SSE410x00080000 0x00080000
102#define bit_SSE4_10x00080000 bit_SSE410x00080000 /* for gcc compat */
103#define bit_SSE420x00100000 0x00100000
104#define bit_SSE4_20x00100000 bit_SSE420x00100000 /* for gcc compat */
105#define bit_x2APIC0x00200000 0x00200000
106#define bit_MOVBE0x00400000 0x00400000
107#define bit_POPCNT0x00800000 0x00800000
108#define bit_TSCDeadline0x01000000 0x01000000
109#define bit_AESNI0x02000000 0x02000000
110#define bit_AES0x02000000 bit_AESNI0x02000000 /* for gcc compat */
111#define bit_XSAVE0x04000000 0x04000000
112#define bit_OSXSAVE0x08000000 0x08000000
113#define bit_AVX0x10000000 0x10000000
114#define bit_F16C0x20000000 0x20000000
115#define bit_RDRND0x40000000 0x40000000
116
117/* Features in %edx for leaf 1 */
118#define bit_FPU0x00000001 0x00000001
119#define bit_VME0x00000002 0x00000002
120#define bit_DE0x00000004 0x00000004
121#define bit_PSE0x00000008 0x00000008
122#define bit_TSC0x00000010 0x00000010
123#define bit_MSR0x00000020 0x00000020
124#define bit_PAE0x00000040 0x00000040
125#define bit_MCE0x00000080 0x00000080
126#define bit_CX80x00000100 0x00000100
127#define bit_CMPXCHG8B0x00000100 bit_CX80x00000100 /* for gcc compat */
128#define bit_APIC0x00000200 0x00000200
129#define bit_SEP0x00000800 0x00000800
130#define bit_MTRR0x00001000 0x00001000
131#define bit_PGE0x00002000 0x00002000
132#define bit_MCA0x00004000 0x00004000
133#define bit_CMOV0x00008000 0x00008000
134#define bit_PAT0x00010000 0x00010000
135#define bit_PSE360x00020000 0x00020000
136#define bit_PSN0x00040000 0x00040000
137#define bit_CLFSH0x00080000 0x00080000
138#define bit_DS0x00200000 0x00200000
139#define bit_ACPI0x00400000 0x00400000
140#define bit_MMX0x00800000 0x00800000
141#define bit_FXSR0x01000000 0x01000000
142#define bit_FXSAVE0x01000000 bit_FXSR0x01000000 /* for gcc compat */
143#define bit_SSE0x02000000 0x02000000
144#define bit_SSE20x04000000 0x04000000
145#define bit_SS0x08000000 0x08000000
146#define bit_HTT0x10000000 0x10000000
147#define bit_TM0x20000000 0x20000000
148#define bit_PBE0x80000000 0x80000000
149
150/* Features in %ebx for leaf 7 sub-leaf 0 */
151#define bit_FSGSBASE0x00000001 0x00000001
152#define bit_SGX0x00000004 0x00000004
153#define bit_BMI0x00000008 0x00000008
154#define bit_HLE0x00000010 0x00000010
155#define bit_AVX20x00000020 0x00000020
156#define bit_SMEP0x00000080 0x00000080
157#define bit_BMI20x00000100 0x00000100
158#define bit_ENH_MOVSB0x00000200 0x00000200
159#define bit_RTM0x00000800 0x00000800
160#define bit_MPX0x00004000 0x00004000
161#define bit_AVX512F0x00010000 0x00010000
162#define bit_AVX512DQ0x00020000 0x00020000
163#define bit_RDSEED0x00040000 0x00040000
164#define bit_ADX0x00080000 0x00080000
165#define bit_AVX512IFMA0x00200000 0x00200000
166#define bit_CLFLUSHOPT0x00800000 0x00800000
167#define bit_CLWB0x01000000 0x01000000
168#define bit_AVX512PF0x04000000 0x04000000
169#define bit_AVX512ER0x08000000 0x08000000
170#define bit_AVX512CD0x10000000 0x10000000
171#define bit_SHA0x20000000 0x20000000
172#define bit_AVX512BW0x40000000 0x40000000
173#define bit_AVX512VL0x80000000 0x80000000
174
175/* Features in %ecx for leaf 7 sub-leaf 0 */
176#define bit_PREFTCHWT10x00000001 0x00000001
177#define bit_AVX512VBMI0x00000002 0x00000002
178#define bit_PKU0x00000004 0x00000004
179#define bit_OSPKE0x00000010 0x00000010
180#define bit_AVX512VBMI20x00000040 0x00000040
181#define bit_SHSTK0x00000080 0x00000080
182#define bit_GFNI0x00000100 0x00000100
183#define bit_VAES0x00000200 0x00000200
184#define bit_VPCLMULQDQ0x00000400 0x00000400
185#define bit_AVX512VNNI0x00000800 0x00000800
186#define bit_AVX512BITALG0x00001000 0x00001000
187#define bit_AVX512VPOPCNTDQ0x00004000 0x00004000
188#define bit_RDPID0x00400000 0x00400000
189
190/* Features in %edx for leaf 7 sub-leaf 0 */
191#define bit_AVX5124VNNIW0x00000004 0x00000004
192#define bit_AVX5124FMAPS0x00000008 0x00000008
193#define bit_IBT0x00100000 0x00100000
194
195/* Features in %eax for leaf 13 sub-leaf 1 */
196#define bit_XSAVEOPT0x00000001 0x00000001
197#define bit_XSAVEC0x00000002 0x00000002
198#define bit_XSAVES0x00000008 0x00000008
199
200/* Features in %ecx for leaf 0x80000001 */
201#define bit_LAHF_LM0x00000001 0x00000001
202#define bit_ABM0x00000020 0x00000020
203#define bit_LZCNT0x00000020 bit_ABM0x00000020 /* for gcc compat */
204#define bit_SSE4a0x00000040 0x00000040
205#define bit_PRFCHW0x00000100 0x00000100
206#define bit_XOP0x00000800 0x00000800
207#define bit_LWP0x00008000 0x00008000
208#define bit_FMA40x00010000 0x00010000
209#define bit_TBM0x00200000 0x00200000
210#define bit_MWAITX0x20000000 0x20000000
211
212/* Features in %edx for leaf 0x80000001 */
213#define bit_MMXEXT0x00400000 0x00400000
214#define bit_LM0x20000000 0x20000000
215#define bit_3DNOWP0x40000000 0x40000000
216#define bit_3DNOW0x80000000 0x80000000
217
218/* Features in %ebx for leaf 0x80000001 */
219#define bit_CLZERO0x00000001 0x00000001
220
221
222#if __i386__1
223#define __cpuid(__leaf, __eax, __ebx, __ecx, __edx)__asm("cpuid" : "=a"(__eax), "=b" (__ebx), "=c"(__ecx), "=d"(
__edx) : "0"(__leaf))
\
224 __asm("cpuid" : "=a"(__eax), "=b" (__ebx), "=c"(__ecx), "=d"(__edx) \
225 : "0"(__leaf))
226
227#define __cpuid_count(__leaf, __count, __eax, __ebx, __ecx, __edx)__asm("cpuid" : "=a"(__eax), "=b" (__ebx), "=c"(__ecx), "=d"(
__edx) : "0"(__leaf), "2"(__count))
\
228 __asm("cpuid" : "=a"(__eax), "=b" (__ebx), "=c"(__ecx), "=d"(__edx) \
229 : "0"(__leaf), "2"(__count))
230#else
231/* x86-64 uses %rbx as the base register, so preserve it. */
232#define __cpuid(__leaf, __eax, __ebx, __ecx, __edx)__asm("cpuid" : "=a"(__eax), "=b" (__ebx), "=c"(__ecx), "=d"(
__edx) : "0"(__leaf))
\
233 __asm(" xchgq %%rbx,%q1\n" \
234 " cpuid\n" \
235 " xchgq %%rbx,%q1" \
236 : "=a"(__eax), "=r" (__ebx), "=c"(__ecx), "=d"(__edx) \
237 : "0"(__leaf))
238
239#define __cpuid_count(__leaf, __count, __eax, __ebx, __ecx, __edx)__asm("cpuid" : "=a"(__eax), "=b" (__ebx), "=c"(__ecx), "=d"(
__edx) : "0"(__leaf), "2"(__count))
\
240 __asm(" xchgq %%rbx,%q1\n" \
241 " cpuid\n" \
242 " xchgq %%rbx,%q1" \
243 : "=a"(__eax), "=r" (__ebx), "=c"(__ecx), "=d"(__edx) \
244 : "0"(__leaf), "2"(__count))
245#endif
246
247static __inline int __get_cpuid_max (unsigned int __leaf, unsigned int *__sig)
248{
249 unsigned int __eax, __ebx, __ecx, __edx;
250#if __i386__1
251 int __cpuid_supported;
252
253 __asm(" pushfl\n"
254 " popl %%eax\n"
255 " movl %%eax,%%ecx\n"
256 " xorl $0x00200000,%%eax\n"
257 " pushl %%eax\n"
258 " popfl\n"
259 " pushfl\n"
260 " popl %%eax\n"
261 " movl $0,%0\n"
262 " cmpl %%eax,%%ecx\n"
263 " je 1f\n"
264 " movl $1,%0\n"
265 "1:"
266 : "=r" (__cpuid_supported) : : "eax", "ecx");
267 if (!__cpuid_supported)
268 return 0;
269#endif
270
271 __cpuid(__leaf, __eax, __ebx, __ecx, __edx)__asm("cpuid" : "=a"(__eax), "=b" (__ebx), "=c"(__ecx), "=d"(
__edx) : "0"(__leaf))
;
272 if (__sig)
273 *__sig = __ebx;
274 return __eax;
275}
276
277static __inline int __get_cpuid (unsigned int __leaf, unsigned int *__eax,
278 unsigned int *__ebx, unsigned int *__ecx,
279 unsigned int *__edx)
280{
281 unsigned int __max_leaf = __get_cpuid_max(__leaf & 0x80000000, 0);
282
283 if (__max_leaf == 0 || __max_leaf < __leaf)
284 return 0;
3
Returning without writing to '*__ebx'
285
286 __cpuid(__leaf, *__eax, *__ebx, *__ecx, *__edx)__asm("cpuid" : "=a"(*__eax), "=b" (*__ebx), "=c"(*__ecx), "=d"
(*__edx) : "0"(__leaf))
;
287 return 1;
288}
289
290static __inline int __get_cpuid_count (unsigned int __leaf,
291 unsigned int __subleaf,
292 unsigned int *__eax, unsigned int *__ebx,
293 unsigned int *__ecx, unsigned int *__edx)
294{
295 unsigned int __max_leaf = __get_cpuid_max(__leaf & 0x80000000, 0);
296
297 if (__max_leaf == 0 || __max_leaf < __leaf)
298 return 0;
299
300 __cpuid_count(__leaf, __subleaf, *__eax, *__ebx, *__ecx, *__edx)__asm("cpuid" : "=a"(*__eax), "=b" (*__ebx), "=c"(*__ecx), "=d"
(*__edx) : "0"(__leaf), "2"(__subleaf))
;
301 return 1;
302}