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Differential D125703

[RISCV] Fix missing vsetvli in transparent block case
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Authored by reames on May 16 2022, 10:16 AM.

Details

Reviewers
craig.topper
frasercrmck
Commits
rG3d17c917099a: [RISCV] Fix missing vsetvli in transparent block case
Summary

We've got a lurking problem with our data flow implementation where different phases disagree, resulting in possible miscompiles. D119518 introduced a workaround, but failed to consider blocks which only contain load/stores compatible with their incoming state.

When I went to rebase and simplify D125232, it turned out that not all of the correctness issues had been fixed yet after all. This is the correctness fix accidentally embedded in the original more complicated version.

Note that the test changes here are mostly regressions. It's worth noting that the simplified version of D125232 exactly reverses all the non-functional diffs in the test caused here. I expect to land them both close in time.

Diff Detail

Event Timeline

reames created this revision.May 16 2022, 10:16 AM
Herald added a project: Restricted Project. · View Herald TranscriptMay 16 2022, 10:16 AM
Herald added subscribers: sunshaoce, VincentWu, luke957 and 31 others. · View Herald Transcript
reames requested review of this revision.May 16 2022, 10:16 AM
Herald added a project: Restricted Project. · View Herald TranscriptMay 16 2022, 10:16 AM
Herald added subscribers: • pcwang-thead, eopXD, MaskRay. · View Herald Transcript
reames mentioned this in D125232: [riscv] Use classic dataflow for VSETVLI insertion .May 16 2022, 10:36 AM
craig.topper added inline comments.May 16 2022, 10:45 AM
llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
1124–1125

Use CurInfo in the assert?

llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
30

Does this mean that ExitInfo and CurInfo don't match at the end? Why did that occur? There's nothing that has any special cases in this function.

Is it because of the AVL being from a vsetvli?

reames updated this revision to Diff 429779.May 16 2022, 10:48 AM

Address review comment

reames marked an inline comment as done.May 16 2022, 10:51 AM
reames added inline comments.
llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
30

It's because the AVL on the abstract state is technically not equal. They both represent the same runtime value, but the first state has an AVL of a0, the vfsub produces one with an AVL of x0 (vlmax). This is due to my recently introduce prepass which creates this canonicalization.

We could pretty easily fix this with a minor improvement to insertVSETVLI, but given the following patch immediately reverses this, I left it to avoid complicating the patch series further. :)

Harbormaster completed remote builds in B164698: Diff 429779.May 16 2022, 12:05 PM
reames added inline comments.May 16 2022, 1:36 PM
llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
30

Slight correction here. The final state after the vfsub has an AVL produced by the first instruction (not vlmax as I said before.) The difference between stage 1/2 and 3 is that having the prior state lets us realize that is compatible (e.g. same bits in registers). We then emit the end of block check to bring the abstract state back in sync.

This hints we could reuse needVSETVLI in the compensation check, but since the compensation code is about to disappear, I don't know this is worth doing.

craig.topper accepted this revision.May 16 2022, 1:39 PM

LGTM

llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
30

Makes sense. Thanks for the explanation.

This revision is now accepted and ready to land.May 16 2022, 1:39 PM
This revision was landed with ongoing or failed builds.May 16 2022, 5:06 PM
Closed by commit rG3d17c917099a: [RISCV] Fix missing vsetvli in transparent block case (authored by reames). · Explain Why
This revision was automatically updated to reflect the committed changes.
reames added a commit: rG3d17c917099a: [RISCV] Fix missing vsetvli in transparent block case.

Revision Contents

PathSize
llvm/
lib/
Target/
RISCV/
8 lines
test/
CodeGen/
RISCV/
rvv/
75 lines
13 lines

Diff 429905

llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp

Show First 20 Lines • Show All 1,115 Lines • ▼ Show 20 Lines if (RISCVII::hasSEWOp(TSFlags)) {
MI.addOperand(MachineOperand::CreateReg(RISCV::VL, /*isDef*/ false, MI.addOperand(MachineOperand::CreateReg(RISCV::VL, /*isDef*/ false,
/*isImp*/ true)); /*isImp*/ true));
} }
MI.addOperand(MachineOperand::CreateReg(RISCV::VTYPE, /*isDef*/ false, MI.addOperand(MachineOperand::CreateReg(RISCV::VTYPE, /*isDef*/ false,
/*isImp*/ true)); /*isImp*/ true));
if (!CurInfo.isValid()) { if (!CurInfo.isValid()) {
// We haven't found any vector instructions or VL/VTYPE changes yet, // We haven't found any vector instructions or VL/VTYPE changes yet,
// use the predecessor information. // use the predecessor information.
assert(BlockInfo[MBB.getNumber()].Pred.isValid() && CurInfo = BlockInfo[MBB.getNumber()].Pred;
craig.topperUnsubmitted
Done
ReplyInline Actions

Use CurInfo in the assert?

craig.topper: Use CurInfo in the assert?
"Expected a valid predecessor state."); assert(CurInfo.isValid() && "Expected a valid predecessor state.");
if (needVSETVLI(NewInfo, BlockInfo[MBB.getNumber()].Pred)) { if (needVSETVLI(NewInfo, CurInfo)) {
// If this is the first implicit state change, and the state change // If this is the first implicit state change, and the state change
// requested can be proven to produce the same register contents, we // requested can be proven to produce the same register contents, we
// can skip emitting the actual state change and continue as if we // can skip emitting the actual state change and continue as if we
// had since we know the GPR result of the implicit state change // had since we know the GPR result of the implicit state change
// wouldn't be used and VL/VTYPE registers are correct. Note that // wouldn't be used and VL/VTYPE registers are correct. Note that
// we *do* need to model the state as if it changed as while the // we *do* need to model the state as if it changed as while the
// register contents are unchanged, the abstract model can change. // register contents are unchanged, the abstract model can change.
if (needVSETVLIPHI(NewInfo, MBB)) if (needVSETVLIPHI(NewInfo, MBB))
insertVSETVLI(MBB, MI, NewInfo, BlockInfo[MBB.getNumber()].Pred); insertVSETVLI(MBB, MI, NewInfo, CurInfo);
CurInfo = NewInfo; CurInfo = NewInfo;
} }
} else { } else {
// If this instruction isn't compatible with the previous VL/VTYPE // If this instruction isn't compatible with the previous VL/VTYPE
// we need to insert a VSETVLI. // we need to insert a VSETVLI.
// If this is a unit-stride or strided load/store, we may be able to use // If this is a unit-stride or strided load/store, we may be able to use
// the EMUL=(EEW/SEW)*LMUL relationship to avoid changing vtype. // the EMUL=(EEW/SEW)*LMUL relationship to avoid changing vtype.
// NOTE: We can't use predecessor information for the store. We must // NOTE: We can't use predecessor information for the store. We must
▲ Show 20 Lines • Show All 217 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll

Show All 17 Lines
declare <vscale x 2 x float> @llvm.riscv.vfmv.v.f.nxv2f32.f32( <vscale x 2 x float>, float, i64) declare <vscale x 2 x float> @llvm.riscv.vfmv.v.f.nxv2f32.f32( <vscale x 2 x float>, float, i64)
declare void @llvm.riscv.vse.nxv1f64(<vscale x 1 x double>, <vscale x 1 x double>* nocapture, i64) declare void @llvm.riscv.vse.nxv1f64(<vscale x 1 x double>, <vscale x 1 x double>* nocapture, i64)
declare void @llvm.riscv.vse.nxv2f32(<vscale x 2 x float>, <vscale x 2 x float>* nocapture, i64) declare void @llvm.riscv.vse.nxv2f32(<vscale x 2 x float>, <vscale x 2 x float>* nocapture, i64)
define <vscale x 1 x double> @test1(i64 %avl, i8 zeroext %cond, <vscale x 1 x double> %a, <vscale x 1 x double> %b) nounwind { define <vscale x 1 x double> @test1(i64 %avl, i8 zeroext %cond, <vscale x 1 x double> %a, <vscale x 1 x double> %b) nounwind {
; CHECK-LABEL: test1: ; CHECK-LABEL: test1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli a0, a0, e64, m1, ta, mu
; CHECK-NEXT: beqz a1, .LBB0_2 ; CHECK-NEXT: beqz a1, .LBB0_2
; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: # %bb.1: # %if.then
; CHECK-NEXT: vfadd.vv v8, v8, v9 ; CHECK-NEXT: vfadd.vv v8, v8, v9
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
craig.topperUnsubmitted
Not Done
ReplyInline Actions

Does this mean that ExitInfo and CurInfo don't match at the end? Why did that occur? There's nothing that has any special cases in this function.

Is it because of the AVL being from a vsetvli?

craig.topper: Does this mean that ExitInfo and CurInfo don't match at the end? Why did that occur? There's…
reamesAuthorUnsubmitted
Done
ReplyInline Actions

It's because the AVL on the abstract state is technically not equal. They both represent the same runtime value, but the first state has an AVL of a0, the vfsub produces one with an AVL of x0 (vlmax). This is due to my recently introduce prepass which creates this canonicalization.

We could pretty easily fix this with a minor improvement to insertVSETVLI, but given the following patch immediately reverses this, I left it to avoid complicating the patch series further. :)

reames: It's because the AVL on the abstract state is technically not equal. They both represent the…
reamesAuthorUnsubmitted
Done
ReplyInline Actions

Slight correction here. The final state after the vfsub has an AVL produced by the first instruction (not vlmax as I said before.) The difference between stage 1/2 and 3 is that having the prior state lets us realize that is compatible (e.g. same bits in registers). We then emit the end of block check to bring the abstract state back in sync.

This hints we could reuse needVSETVLI in the compensation check, but since the compensation code is about to disappear, I don't know this is worth doing.

reames: Slight correction here. The final state after the vfsub has an AVL produced by the first…
craig.topperUnsubmitted
Not Done
ReplyInline Actions

Makes sense. Thanks for the explanation.

craig.topper: Makes sense. Thanks for the explanation.
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK-NEXT: .LBB0_2: # %if.else ; CHECK-NEXT: .LBB0_2: # %if.else
; CHECK-NEXT: vfsub.vv v8, v8, v9 ; CHECK-NEXT: vfsub.vv v8, v8, v9
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%0 = tail call i64 @llvm.riscv.vsetvli(i64 %avl, i64 3, i64 0) %0 = tail call i64 @llvm.riscv.vsetvli(i64 %avl, i64 3, i64 0)
%tobool = icmp eq i8 %cond, 0 %tobool = icmp eq i8 %cond, 0
br i1 %tobool, label %if.else, label %if.then br i1 %tobool, label %if.else, label %if.then
if.then: ; preds = %entry if.then: ; preds = %entry
%1 = tail call <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> %a, <vscale x 1 x double> %b, i64 %0) %1 = tail call <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> %a, <vscale x 1 x double> %b, i64 %0)
br label %if.end br label %if.end
if.else: ; preds = %entry if.else: ; preds = %entry
%2 = tail call <vscale x 1 x double> @llvm.riscv.vfsub.nxv1f64.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> %a, <vscale x 1 x double> %b, i64 %0) %2 = tail call <vscale x 1 x double> @llvm.riscv.vfsub.nxv1f64.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> %a, <vscale x 1 x double> %b, i64 %0)
br label %if.end br label %if.end
if.end: ; preds = %if.else, %if.then if.end: ; preds = %if.else, %if.then
%c.0 = phi <vscale x 1 x double> [ %1, %if.then ], [ %2, %if.else ] %c.0 = phi <vscale x 1 x double> [ %1, %if.then ], [ %2, %if.else ]
ret <vscale x 1 x double> %c.0 ret <vscale x 1 x double> %c.0
} }
@scratch = global i8 0, align 16 @scratch = global i8 0, align 16
define <vscale x 1 x double> @test2(i64 %avl, i8 zeroext %cond, <vscale x 1 x double> %a, <vscale x 1 x double> %b) nounwind { define <vscale x 1 x double> @test2(i64 %avl, i8 zeroext %cond, <vscale x 1 x double> %a, <vscale x 1 x double> %b) nounwind {
; CHECK-LABEL: test2: ; CHECK-LABEL: test2:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli a0, a0, e64, m1, ta, mu
; CHECK-NEXT: beqz a1, .LBB1_2 ; CHECK-NEXT: beqz a1, .LBB1_2
; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: # %bb.1: # %if.then
; CHECK-NEXT: vfadd.vv v9, v8, v9 ; CHECK-NEXT: vfadd.vv v9, v8, v9
; CHECK-NEXT: vfmul.vv v8, v9, v8 ; CHECK-NEXT: j .LBB1_3
; CHECK-NEXT: ret
; CHECK-NEXT: .LBB1_2: # %if.else ; CHECK-NEXT: .LBB1_2: # %if.else
; CHECK-NEXT: vfsub.vv v9, v8, v9 ; CHECK-NEXT: vfsub.vv v9, v8, v9
; CHECK-NEXT: .LBB1_3: # %if.end
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vfmul.vv v8, v9, v8 ; CHECK-NEXT: vfmul.vv v8, v9, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%0 = tail call i64 @llvm.riscv.vsetvli(i64 %avl, i64 3, i64 0) %0 = tail call i64 @llvm.riscv.vsetvli(i64 %avl, i64 3, i64 0)
%tobool = icmp eq i8 %cond, 0 %tobool = icmp eq i8 %cond, 0
br i1 %tobool, label %if.else, label %if.then br i1 %tobool, label %if.else, label %if.then
if.then: ; preds = %entry if.then: ; preds = %entry
▲ Show 20 Lines • Show All 102 Lines • ▼ Show 20 Linesif.end: ; preds = %if.else, %if.then
%8 = tail call <vscale x 1 x double> @llvm.riscv.vfmul.nxv1f64.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> %l, <vscale x 1 x double> %r, i64 %avl) %8 = tail call <vscale x 1 x double> @llvm.riscv.vfmul.nxv1f64.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> %l, <vscale x 1 x double> %r, i64 %avl)
ret <vscale x 1 x double> %8 ret <vscale x 1 x double> %8
} }
define <vscale x 1 x double> @test5(i64 %avl, i8 zeroext %cond, <vscale x 1 x double> %a, <vscale x 1 x double> %b) nounwind { define <vscale x 1 x double> @test5(i64 %avl, i8 zeroext %cond, <vscale x 1 x double> %a, <vscale x 1 x double> %b) nounwind {
; CHECK-LABEL: test5: ; CHECK-LABEL: test5:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: andi a2, a1, 1 ; CHECK-NEXT: andi a2, a1, 1
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli a0, a0, e64, m1, ta, mu
; CHECK-NEXT: bnez a2, .LBB4_3 ; CHECK-NEXT: bnez a2, .LBB4_2
; CHECK-NEXT: # %bb.1: # %if.else ; CHECK-NEXT: # %bb.1: # %if.else
; CHECK-NEXT: vfsub.vv v9, v8, v9 ; CHECK-NEXT: vfsub.vv v9, v8, v9
; CHECK-NEXT: andi a0, a1, 2 ; CHECK-NEXT: j .LBB4_3
; CHECK-NEXT: beqz a0, .LBB4_4 ; CHECK-NEXT: .LBB4_2: # %if.then
; CHECK-NEXT: .LBB4_2: # %if.then4
; CHECK-NEXT: vfmul.vv v8, v9, v8
; CHECK-NEXT: ret
; CHECK-NEXT: .LBB4_3: # %if.then
; CHECK-NEXT: vfadd.vv v9, v8, v9 ; CHECK-NEXT: vfadd.vv v9, v8, v9
; CHECK-NEXT: .LBB4_3: # %if.end
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: andi a0, a1, 2 ; CHECK-NEXT: andi a0, a1, 2
; CHECK-NEXT: bnez a0, .LBB4_2 ; CHECK-NEXT: bnez a0, .LBB4_5
; CHECK-NEXT: .LBB4_4: # %if.else5 ; CHECK-NEXT: # %bb.4: # %if.else5
; CHECK-NEXT: vfmul.vv v8, v8, v9 ; CHECK-NEXT: vfmul.vv v8, v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK-NEXT: .LBB4_5: # %if.then4
; CHECK-NEXT: vfmul.vv v8, v9, v8
; CHECK-NEXT: ret
entry: entry:
%0 = tail call i64 @llvm.riscv.vsetvli(i64 %avl, i64 3, i64 0) %0 = tail call i64 @llvm.riscv.vsetvli(i64 %avl, i64 3, i64 0)
%conv = zext i8 %cond to i32 %conv = zext i8 %cond to i32
%and = and i32 %conv, 1 %and = and i32 %conv, 1
%tobool = icmp eq i32 %and, 0 %tobool = icmp eq i32 %and, 0
br i1 %tobool, label %if.else, label %if.then br i1 %tobool, label %if.else, label %if.then
if.then: ; preds = %entry if.then: ; preds = %entry
Show All 26 Lines
; FIXME: The explicit vsetvli in if.then4 could be removed as it is redundant ; FIXME: The explicit vsetvli in if.then4 could be removed as it is redundant
; with the one in the entry, but we lack the ability to remove explicit ; with the one in the entry, but we lack the ability to remove explicit
; vsetvli instructions. ; vsetvli instructions.
define <vscale x 1 x double> @test6(i64 %avl, i8 zeroext %cond, <vscale x 1 x double> %a, <vscale x 1 x double> %b) nounwind { define <vscale x 1 x double> @test6(i64 %avl, i8 zeroext %cond, <vscale x 1 x double> %a, <vscale x 1 x double> %b) nounwind {
; CHECK-LABEL: test6: ; CHECK-LABEL: test6:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: andi a3, a1, 1 ; CHECK-NEXT: andi a3, a1, 1
; CHECK-NEXT: vsetvli a2, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli a2, a0, e64, m1, ta, mu
; CHECK-NEXT: bnez a3, .LBB5_3 ; CHECK-NEXT: bnez a3, .LBB5_2
; CHECK-NEXT: # %bb.1: # %if.else ; CHECK-NEXT: # %bb.1: # %if.else
; CHECK-NEXT: vfsub.vv v8, v8, v9 ; CHECK-NEXT: vfsub.vv v8, v8, v9
; CHECK-NEXT: andi a1, a1, 2 ; CHECK-NEXT: j .LBB5_3
; CHECK-NEXT: beqz a1, .LBB5_4 ; CHECK-NEXT: .LBB5_2: # %if.then
; CHECK-NEXT: .LBB5_2: # %if.then4
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: lui a0, %hi(.LCPI5_0)
; CHECK-NEXT: addi a0, a0, %lo(.LCPI5_0)
; CHECK-NEXT: vlse64.v v9, (a0), zero
; CHECK-NEXT: lui a0, %hi(.LCPI5_1)
; CHECK-NEXT: addi a0, a0, %lo(.LCPI5_1)
; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vfadd.vv v9, v9, v10
; CHECK-NEXT: lui a0, %hi(scratch)
; CHECK-NEXT: addi a0, a0, %lo(scratch)
; CHECK-NEXT: vse64.v v9, (a0)
; CHECK-NEXT: j .LBB5_5
; CHECK-NEXT: .LBB5_3: # %if.then
; CHECK-NEXT: vfadd.vv v8, v8, v9 ; CHECK-NEXT: vfadd.vv v8, v8, v9
; CHECK-NEXT: .LBB5_3: # %if.end
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: andi a1, a1, 2 ; CHECK-NEXT: andi a1, a1, 2
; CHECK-NEXT: bnez a1, .LBB5_2 ; CHECK-NEXT: bnez a1, .LBB5_5
; CHECK-NEXT: .LBB5_4: # %if.else5 ; CHECK-NEXT: # %bb.4: # %if.else5
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: lui a0, %hi(.LCPI5_2) ; CHECK-NEXT: lui a0, %hi(.LCPI5_2)
; CHECK-NEXT: addi a0, a0, %lo(.LCPI5_2) ; CHECK-NEXT: addi a0, a0, %lo(.LCPI5_2)
; CHECK-NEXT: vlse32.v v9, (a0), zero ; CHECK-NEXT: vlse32.v v9, (a0), zero
; CHECK-NEXT: lui a0, %hi(.LCPI5_3) ; CHECK-NEXT: lui a0, %hi(.LCPI5_3)
; CHECK-NEXT: addi a0, a0, %lo(.LCPI5_3) ; CHECK-NEXT: addi a0, a0, %lo(.LCPI5_3)
; CHECK-NEXT: vlse32.v v10, (a0), zero ; CHECK-NEXT: vlse32.v v10, (a0), zero
; CHECK-NEXT: vfadd.vv v9, v9, v10 ; CHECK-NEXT: vfadd.vv v9, v9, v10
; CHECK-NEXT: lui a0, %hi(scratch) ; CHECK-NEXT: lui a0, %hi(scratch)
; CHECK-NEXT: addi a0, a0, %lo(scratch) ; CHECK-NEXT: addi a0, a0, %lo(scratch)
; CHECK-NEXT: vse32.v v9, (a0) ; CHECK-NEXT: vse32.v v9, (a0)
; CHECK-NEXT: .LBB5_5: # %if.end10 ; CHECK-NEXT: j .LBB5_6
; CHECK-NEXT: .LBB5_5: # %if.then4
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: lui a0, %hi(.LCPI5_0)
; CHECK-NEXT: addi a0, a0, %lo(.LCPI5_0)
; CHECK-NEXT: vlse64.v v9, (a0), zero
; CHECK-NEXT: lui a0, %hi(.LCPI5_1)
; CHECK-NEXT: addi a0, a0, %lo(.LCPI5_1)
; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vfadd.vv v9, v9, v10
; CHECK-NEXT: lui a0, %hi(scratch)
; CHECK-NEXT: addi a0, a0, %lo(scratch)
; CHECK-NEXT: vse64.v v9, (a0)
; CHECK-NEXT: .LBB5_6: # %if.end10
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: vfmul.vv v8, v8, v8 ; CHECK-NEXT: vfmul.vv v8, v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%0 = tail call i64 @llvm.riscv.vsetvli(i64 %avl, i64 3, i64 0) %0 = tail call i64 @llvm.riscv.vsetvli(i64 %avl, i64 3, i64 0)
%conv = zext i8 %cond to i32 %conv = zext i8 %cond to i32
%and = and i32 %conv, 1 %and = and i32 %conv, 1
%tobool = icmp eq i32 %and, 0 %tobool = icmp eq i32 %and, 0
▲ Show 20 Lines • Show All 48 Lines • ▼ Show 20 Lines
; CHECK-NEXT: sd s0, 16(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; CHECK-NEXT: csrr a2, vlenb ; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 1 ; CHECK-NEXT: slli a2, a2, 1
; CHECK-NEXT: sub sp, sp, a2 ; CHECK-NEXT: sub sp, sp, a2
; CHECK-NEXT: vsetvli s0, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli s0, a0, e64, m1, ta, mu
; CHECK-NEXT: beqz a1, .LBB6_2 ; CHECK-NEXT: beqz a1, .LBB6_2
; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: # %bb.1: # %if.then
; CHECK-NEXT: vfadd.vv v8, v8, v9 ; CHECK-NEXT: vfadd.vv v8, v8, v9
; CHECK-NEXT: vsetvli zero, s0, e64, m1, ta, mu
; CHECK-NEXT: j .LBB6_3 ; CHECK-NEXT: j .LBB6_3
; CHECK-NEXT: .LBB6_2: # %if.else ; CHECK-NEXT: .LBB6_2: # %if.else
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: add a0, a0, sp ; CHECK-NEXT: add a0, a0, sp
; CHECK-NEXT: addi a0, a0, 16 ; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs1r.v v9, (a0) # Unknown-size Folded Spill ; CHECK-NEXT: vs1r.v v9, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: addi a0, sp, 16 ; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs1r.v v8, (a0) # Unknown-size Folded Spill ; CHECK-NEXT: vs1r.v v8, (a0) # Unknown-size Folded Spill
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; CHECK-NEXT: vl1r.v v9, (a0) # Unknown-size Folded Reload ; CHECK-NEXT: vl1r.v v9, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: add a0, a0, sp ; CHECK-NEXT: add a0, a0, sp
; CHECK-NEXT: addi a0, a0, 16 ; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload ; CHECK-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: j .LBB7_3 ; CHECK-NEXT: j .LBB7_3
; CHECK-NEXT: .LBB7_2: # %if.else ; CHECK-NEXT: .LBB7_2: # %if.else
; CHECK-NEXT: vfsub.vv v9, v8, v9 ; CHECK-NEXT: vfsub.vv v9, v8, v9
; CHECK-NEXT: vsetvli zero, s0, e64, m1, ta, mu
; CHECK-NEXT: .LBB7_3: # %if.end ; CHECK-NEXT: .LBB7_3: # %if.end
; CHECK-NEXT: vsetvli zero, s0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, s0, e64, m1, ta, mu
; CHECK-NEXT: vfmul.vv v8, v9, v8 ; CHECK-NEXT: vfmul.vv v8, v9, v8
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 1 ; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: add sp, sp, a0 ; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
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llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir

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; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: dead $x0 = PseudoVSETVLI [[COPY]], 88 /* e64, m1, ta, mu */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: dead $x0 = PseudoVSETVLI [[COPY]], 88 /* e64, m1, ta, mu */, implicit-def $vl, implicit-def $vtype
; CHECK-NEXT: [[PseudoVSUB_VV_M1_:%[0-9]+]]:vr = PseudoVSUB_VV_M1 [[COPY1]], [[COPY1]], $noreg, 6 /* e64 */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[PseudoVSUB_VV_M1_:%[0-9]+]]:vr = PseudoVSUB_VV_M1 [[COPY1]], [[COPY1]], $noreg, 6 /* e64 */, implicit $vl, implicit $vtype
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.if.end: ; CHECK-NEXT: bb.3.if.end:
; CHECK-NEXT: [[PHI:%[0-9]+]]:vr = PHI [[PseudoVADD_VV_M1_]], %bb.1, [[PseudoVSUB_VV_M1_]], %bb.2 ; CHECK-NEXT: [[PHI:%[0-9]+]]:vr = PHI [[PseudoVADD_VV_M1_]], %bb.1, [[PseudoVSUB_VV_M1_]], %bb.2
; CHECK-NEXT: [[PseudoVMV_X_S_M1_:%[0-9]+]]:gpr = PseudoVMV_X_S_M1 [[PHI]], 6 /* e64 */, implicit $vtype ; CHECK-NEXT: [[PseudoVMV_X_S_M1_:%[0-9]+]]:gpr = PseudoVMV_X_S_M1 [[PHI]], 6 /* e64 */, implicit $vtype
; CHECK-NEXT: $x10 = COPY [[PseudoVMV_X_S_M1_]] ; CHECK-NEXT: $x10 = COPY [[PseudoVMV_X_S_M1_]]
; CHECK-NEXT: dead $x0 = PseudoVSETVLIX0 killed $x0, 88 /* e64, m1, ta, mu */, implicit-def $vl, implicit-def $vtype, implicit $vl
; CHECK-NEXT: PseudoRET implicit $x10 ; CHECK-NEXT: PseudoRET implicit $x10
bb.0.entry: bb.0.entry:
successors: %bb.2(0x30000000), %bb.1(0x50000000) successors: %bb.2(0x30000000), %bb.1(0x50000000)
liveins: $x10, $v8, $v9, $x11 liveins: $x10, $v8, $v9, $x11
%6:gprnox0 = COPY $x11 %6:gprnox0 = COPY $x11
%5:vr = COPY $v9 %5:vr = COPY $v9
%4:vr = COPY $v8 %4:vr = COPY $v8
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; CHECK: bb.0.entry: ; CHECK: bb.0.entry:
; CHECK-NEXT: successors: %bb.2(0x30000000), %bb.1(0x50000000) ; CHECK-NEXT: successors: %bb.2(0x30000000), %bb.1(0x50000000)
; CHECK-NEXT: liveins: $x10, $v8, $v9, $x11 ; CHECK-NEXT: liveins: $x10, $v8, $v9, $x11
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x11 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x11
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vr = COPY $v8 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vr = COPY $v8
; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x10 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x10
; CHECK-NEXT: $x0 = PseudoVSETVLI [[COPY]], 88 /* e64, m1, ta, mu */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: [[PseudoVSETVLI:%[0-9]+]]:gprnox0 = PseudoVSETVLI [[COPY]], 88 /* e64, m1, ta, mu */, implicit-def $vl, implicit-def $vtype
; CHECK-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY $x0 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY $x0
; CHECK-NEXT: BEQ [[COPY3]], [[COPY4]], %bb.2 ; CHECK-NEXT: BEQ [[COPY3]], [[COPY4]], %bb.2
; CHECK-NEXT: PseudoBR %bb.1 ; CHECK-NEXT: PseudoBR %bb.1
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1.if.then: ; CHECK-NEXT: bb.1.if.then:
; CHECK-NEXT: successors: %bb.3(0x80000000) ; CHECK-NEXT: successors: %bb.3(0x80000000)
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 [[COPY2]], [[COPY1]], $noreg, 6 /* e64 */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 [[COPY2]], [[COPY1]], $noreg, 6 /* e64 */, implicit $vl, implicit $vtype
; CHECK-NEXT: dead $x0 = PseudoVSETVLI [[PseudoVSETVLI]], 88 /* e64, m1, ta, mu */, implicit-def $vl, implicit-def $vtype
; CHECK-NEXT: PseudoBR %bb.3 ; CHECK-NEXT: PseudoBR %bb.3
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.if.else: ; CHECK-NEXT: bb.2.if.else:
; CHECK-NEXT: successors: %bb.3(0x80000000) ; CHECK-NEXT: successors: %bb.3(0x80000000)
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[PseudoVSUB_VV_M1_:%[0-9]+]]:vr = PseudoVSUB_VV_M1 [[COPY2]], [[COPY1]], $noreg, 6 /* e64 */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[PseudoVSUB_VV_M1_:%[0-9]+]]:vr = PseudoVSUB_VV_M1 [[COPY2]], [[COPY1]], $noreg, 6 /* e64 */, implicit $vl, implicit $vtype
; CHECK-NEXT: dead $x0 = PseudoVSETVLI [[PseudoVSETVLI]], 88 /* e64, m1, ta, mu */, implicit-def $vl, implicit-def $vtype
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.if.end: ; CHECK-NEXT: bb.3.if.end:
; CHECK-NEXT: [[PHI:%[0-9]+]]:vr = PHI [[PseudoVADD_VV_M1_]], %bb.1, [[PseudoVSUB_VV_M1_]], %bb.2 ; CHECK-NEXT: [[PHI:%[0-9]+]]:vr = PHI [[PseudoVADD_VV_M1_]], %bb.1, [[PseudoVSUB_VV_M1_]], %bb.2
; CHECK-NEXT: $v8 = COPY [[PHI]] ; CHECK-NEXT: $v8 = COPY [[PHI]]
; CHECK-NEXT: PseudoRET implicit $v8 ; CHECK-NEXT: PseudoRET implicit $v8
bb.0.entry: bb.0.entry:
successors: %bb.2(0x30000000), %bb.1(0x50000000) successors: %bb.2(0x30000000), %bb.1(0x50000000)
liveins: $x10, $v8, $v9, $x11 liveins: $x10, $v8, $v9, $x11
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; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1: ; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000) ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, %10, %bb.1 ; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, %10, %bb.1
; CHECK-NEXT: [[PseudoVADD_VX_M1_:%[0-9]+]]:vr = PseudoVADD_VX_M1 [[PseudoVID_V_M1_]], [[PHI]], -1, 6 /* e64 */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[PseudoVADD_VX_M1_:%[0-9]+]]:vr = PseudoVADD_VX_M1 [[PseudoVID_V_M1_]], [[PHI]], -1, 6 /* e64 */, implicit $vl, implicit $vtype
; CHECK-NEXT: [[MUL:%[0-9]+]]:gpr = MUL [[PHI]], [[SRLI]] ; CHECK-NEXT: [[MUL:%[0-9]+]]:gpr = MUL [[PHI]], [[SRLI]]
; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[COPY]], [[MUL]] ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[COPY]], [[MUL]]
; CHECK-NEXT: dead $x0 = PseudoVSETVLIX0 killed $x0, 87 /* e32, mf2, ta, mu */, implicit-def $vl, implicit-def $vtype, implicit $vl
; CHECK-NEXT: PseudoVSE32_V_MF2 killed [[PseudoVADD_VX_M1_]], killed [[ADD]], -1, 5 /* e32 */, implicit $vl, implicit $vtype ; CHECK-NEXT: PseudoVSE32_V_MF2 killed [[PseudoVADD_VX_M1_]], killed [[ADD]], -1, 5 /* e32 */, implicit $vl, implicit $vtype
; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[PHI]], 1 ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[PHI]], 1
; CHECK-NEXT: dead $x0 = PseudoVSETVLIX0 killed $x0, 88 /* e64, m1, ta, mu */, implicit-def $vl, implicit-def $vtype, implicit $vl
; CHECK-NEXT: BLTU [[ADDI]], [[COPY1]], %bb.1 ; CHECK-NEXT: BLTU [[ADDI]], [[COPY1]], %bb.1
; CHECK-NEXT: PseudoBR %bb.2 ; CHECK-NEXT: PseudoBR %bb.2
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2: ; CHECK-NEXT: bb.2:
; CHECK-NEXT: PseudoRET ; CHECK-NEXT: PseudoRET
bb.0: bb.0:
liveins: $x10, $x11 liveins: $x10, $x11
%0:gpr = COPY $x10 %0:gpr = COPY $x10
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; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1: ; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.2(0x80000000) ; CHECK-NEXT: successors: %bb.2(0x80000000)
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, %10, %bb.2 ; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, %10, %bb.2
; CHECK-NEXT: [[PseudoVADD_VX_M1_:%[0-9]+]]:vr = PseudoVADD_VX_M1 [[PseudoVID_V_M1_]], [[PHI]], -1, 6 /* e64 */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[PseudoVADD_VX_M1_:%[0-9]+]]:vr = PseudoVADD_VX_M1 [[PseudoVID_V_M1_]], [[PHI]], -1, 6 /* e64 */, implicit $vl, implicit $vtype
; CHECK-NEXT: [[MUL:%[0-9]+]]:gpr = MUL [[PHI]], [[SRLI]] ; CHECK-NEXT: [[MUL:%[0-9]+]]:gpr = MUL [[PHI]], [[SRLI]]
; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[COPY]], [[MUL]] ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[COPY]], [[MUL]]
; CHECK-NEXT: dead $x0 = PseudoVSETVLIX0 killed $x0, 87 /* e32, mf2, ta, mu */, implicit-def $vl, implicit-def $vtype, implicit $vl
; CHECK-NEXT: PseudoVSE32_V_MF2 killed [[PseudoVADD_VX_M1_]], killed [[ADD]], -1, 5 /* e32 */, implicit $vl, implicit $vtype ; CHECK-NEXT: PseudoVSE32_V_MF2 killed [[PseudoVADD_VX_M1_]], killed [[ADD]], -1, 5 /* e32 */, implicit $vl, implicit $vtype
; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[PHI]], 1 ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[PHI]], 1
; CHECK-NEXT: dead $x0 = PseudoVSETVLIX0 killed $x0, 88 /* e64, m1, ta, mu */, implicit-def $vl, implicit-def $vtype, implicit $vl
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2: ; CHECK-NEXT: bb.2:
; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.3(0x40000000) ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.3(0x40000000)
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: BLTU [[ADDI]], [[COPY1]], %bb.1 ; CHECK-NEXT: BLTU [[ADDI]], [[COPY1]], %bb.1
; CHECK-NEXT: PseudoBR %bb.3 ; CHECK-NEXT: PseudoBR %bb.3
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3: ; CHECK-NEXT: bb.3:
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%20:vr = PseudoVMV_S_X_M1 %21, %19, 1, 5 %20:vr = PseudoVMV_S_X_M1 %21, %19, 1, 5
%24:vr = IMPLICIT_DEF %24:vr = IMPLICIT_DEF
%23:vr = PseudoVREDSUM_VS_M1 %24, %16, killed %20, 4, 5 %23:vr = PseudoVREDSUM_VS_M1 %24, %16, killed %20, 4, 5
PseudoVSE32_V_M1 killed %23, %8, 1, 5 :: (store (s32) into %ir.res) PseudoVSE32_V_M1 killed %23, %8, 1, 5 :: (store (s32) into %ir.res)
PseudoRET PseudoRET
... ...
--- ---
# FIXME: This test shows incorrect VSETVLI insertion. The VLUXEI64 needs
# configuration for SEW=8 but it instead inherits a SEW=64 from the entry
# block.
name: vsetvli_vluxei64_regression name: vsetvli_vluxei64_regression
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
; CHECK-LABEL: name: vsetvli_vluxei64_regression ; CHECK-LABEL: name: vsetvli_vluxei64_regression
; CHECK: bb.0: ; CHECK: bb.0:
; CHECK-NEXT: successors: %bb.1(0x80000000) ; CHECK-NEXT: successors: %bb.1(0x80000000)
; CHECK-NEXT: liveins: $x10, $x11, $x12, $v0, $v1, $v2, $v3 ; CHECK-NEXT: liveins: $x10, $x11, $x12, $v0, $v1, $v2, $v3
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
Show All 9 Linesbody: |
; CHECK-NEXT: %t6:vr = PseudoVMSEQ_VI_M1 %t1, 0, -1, 6 /* e64 */, implicit $vl, implicit $vtype ; CHECK-NEXT: %t6:vr = PseudoVMSEQ_VI_M1 %t1, 0, -1, 6 /* e64 */, implicit $vl, implicit $vtype
; CHECK-NEXT: PseudoBR %bb.1 ; CHECK-NEXT: PseudoBR %bb.1
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1: ; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000) ; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %mask:vr = PseudoVMANDN_MM_MF8 %t6, %t3, -1, 0 /* e8 */, implicit $vl, implicit $vtype ; CHECK-NEXT: %mask:vr = PseudoVMANDN_MM_MF8 %t6, %t3, -1, 0 /* e8 */, implicit $vl, implicit $vtype
; CHECK-NEXT: %t2:gpr = COPY $x0 ; CHECK-NEXT: %t2:gpr = COPY $x0
; CHECK-NEXT: dead $x0 = PseudoVSETVLIX0 killed $x0, 69 /* e8, mf8, ta, mu */, implicit-def $vl, implicit-def $vtype, implicit $vl
; CHECK-NEXT: BEQ %a, %t2, %bb.3 ; CHECK-NEXT: BEQ %a, %t2, %bb.3
; CHECK-NEXT: PseudoBR %bb.2 ; CHECK-NEXT: PseudoBR %bb.2
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2: ; CHECK-NEXT: bb.2:
; CHECK-NEXT: successors: %bb.3(0x80000000) ; CHECK-NEXT: successors: %bb.3(0x80000000)
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: $v0 = COPY %mask ; CHECK-NEXT: $v0 = COPY %mask
; CHECK-NEXT: early-clobber %t0:vrnov0 = PseudoVLUXEI64_V_M1_MF8_MASK %t5, killed %inaddr, %idxs, $v0, -1, 3 /* e8 */, 1, implicit $vl, implicit $vtype ; CHECK-NEXT: early-clobber %t0:vrnov0 = PseudoVLUXEI64_V_M1_MF8_MASK %t5, killed %inaddr, %idxs, $v0, -1, 3 /* e8 */, 1, implicit $vl, implicit $vtype
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