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Assertion in register allocation on ARM #32418

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yuyichao opened this issue May 17, 2017 · 5 comments
Closed

Assertion in register allocation on ARM #32418

yuyichao opened this issue May 17, 2017 · 5 comments
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@MatzeB
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backend:ARM bugzilla Issues migrated from bugzilla

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@yuyichao
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Bugzilla Link 33071
Resolution FIXED
Resolved on Jan 11, 2018 13:59
Version trunk
OS Linux
Attachments Test case, regalloc log
CC @Keno,@MatzeB,@qcolombet

Extended Description

The IR attached causes an assertion in LLC on at least 3.9 and 4.0.

The failure is

llc: /home/yuyichao/projects/julia/tests/master/deps/srccache/llvm-4.0.0/lib/CodeGen/VirtRegMap.cpp:443: void {anonymous}::VirtRegRewriter::rewrite(): Assertion `PhysReg && "Invalid SubReg for physical register"' failed.

Which is triggered on %D16<def> = COPY %vreg29:ssub_0<kill>; DPR:%vreg29.

Enclosing BB

400B    BB#1: derived from LLVM BB %if
            Live Ins: %R4 %R5 %R8 %R9 %S16
            Predecessors according to CFG: BB#0
416B            %D16<def> = FCONSTD 128, pred:14, pred:%noreg; dbg:/home/yuyichao/projects/julia/tests/master/script.jl:2
432B            %D17<def> = VCVTDS %S16<kill>, pred:14, pred:%noreg; dbg:/home/yuyichao/projects/julia/tests/master/script.jl:2
448B            %D16<def> = VADDD %D17<kill>, %D16<kill>, pred:14, pred:%noreg; dbg:/home/yuyichao/projects/julia/tests/master/script.jl:2
464B            %R10<def>, %R7<def> = VMOVRRD %D16, pred:14, pred:%noreg; dbg:/home/yuyichao/projects/julia/tests/master/script.jl:2
480B            %R0<def> = MOVi 1, pred:14, pred:%noreg, opt:%noreg
512B            %D16<def> = COPY %vreg29:ssub_0<kill>; DPR:%vreg29
560B            B <BB#4>; dbg:/home/yuyichao/projects/julia/tests/master/script.jl:2
            Successors according to CFG: BB#4(?%)

Enclosing BB before rewrite

BB#1: derived from LLVM BB %if
    Live Ins: %R4 %R5 %R8 %R9 %S16
    Predecessors according to CFG: BB#0
        %vreg27<def> = FCONSTD 128, pred:14, pred:%noreg; DPR:%vreg27 dbg:/home/yuyichao/projects/julia/tests/master/script.jl:2
        %vreg28<def> = VCVTDS %vreg17<kill>, pred:14, pred:%noreg; DPR:%vreg28 SPR:%vreg17 dbg:/home/yuyichao/projects/julia/tests/master/script.jl:2
        %vreg29<def> = VADDD %vreg28<kill>, %vreg27<kill>, pred:14, pred:%noreg; DPR:%vreg29,%vreg28,%vreg27 dbg:/home/yuyichao/projects/julia/tests/master/script.jl:2
        %vreg6<def>, %vreg5<def> = VMOVRRD %vreg29, pred:14, pred:%noreg; GPR:%vreg6,%vreg5 DPR:%vreg29 dbg:/home/yuyichao/projects/julia/tests/master/script.jl:2
        %vreg72<def> = MOVi 1, pred:14, pred:%noreg, opt:%noreg; GPR:%vreg72
        %vreg67<def> = COPY %vreg29:ssub_0<kill>; DPR:%vreg67,%vreg29
        B <BB#4>; dbg:/home/yuyichao/projects/julia/tests/master/script.jl:2
    Successors according to CFG: BB#4(?%)

Ref JuliaLang/julia#21926
@yuyichao
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assigned to @MatzeB

@Keno
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Keno commented May 17, 2017

Bugpoint reduced test case:

target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
target triple = "armv7l-unknown-linux-gnueabihf"

declare i8** @&#8203;jl_box_float32(float)

define { i8**, i8 } @&#8203;julia_expm1_2_69502([16 x i8]* noalias nocapture, float) {
top:
  br i1 undef, label %L5, label %if

if:                                               ; preds = %top
  %2 = fadd double undef, -2.000000e+00
  %3 = bitcast double %2 to i64
  %"#temp#.sroa.0.sroa.0.0.extract.trunc" = trunc i64 %3 to i32
  br label %box_union10

L5:                                               ; preds = %top
  %4 = call float inttoptr (i32 -194201728 to float (float)*)(float %1)
  %5 = bitcast float %4 to i32
  br label %box_union10

box_union10:                                      ; preds = %L5, %if
  %"#temp#.sroa.0.sroa.0.0" = phi i32 [ %5, %L5 ], [ %"#temp#.sroa.0.sroa.0.0.extract.trunc", %if ]
  %6 = bitcast i32 %"#temp#.sroa.0.sroa.0.0" to float
  %7 = call i8** @&#8203;jl_box_float32(float %6)
  unreachable
}

@qcolombet
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The register class for COPY vreg29:ssub_0 does not look correct. Should be DPR_VFP2 or something. DPR does not supports ssub_0 for the upper registers.

Likely a bug in the code that added the copy (ISel?)

@MatzeB
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MatzeB commented Nov 28, 2017

Turns out this was caused by the peephole optimizer. There's been an extra problem where the machine verifier doesn't perform all checks on PHI operands hence the problem isn't detected by the machine verifier until the PHIs are lowered.

@MatzeB
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MatzeB commented Jan 11, 2018

Fixed in r322313

@llvmbot llvmbot transferred this issue from llvm/llvm-bugzilla-archive Dec 10, 2021
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@MatzeB @yuyichao @Keno @qcolombet