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Bug 12205 - MachinePointerInfo does not refer to a stack frame object.
Summary: MachinePointerInfo does not refer to a stack frame object.
Status: RESOLVED FIXED
Alias: None
Product: new-bugs
Classification: Unclassified
Component: new bugs (show other bugs)
Version: trunk
Hardware: PC Linux
: P normal
Assignee: Unassigned LLVM Bugs
URL:
Keywords:
Depends on:
Blocks:
 
Reported: 2012-03-07 13:12 PST by Akira Hatanaka
Modified: 2019-01-23 04:22 PST (History)
4 users (show)

See Also:
Fixed By Commit(s):

Attachments
.ll file (1.49 KB, application/octet-stream)
2012-03-07 13:12 PST, Akira Hatanaka 		Details
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Description Akira Hatanaka 2012-03-07 13:12:23 PST 
Created attachment 8151 [details]
.ll file

These are the gdb commands to reproduce the problem:

(gdb) b SelectionDAGISel.cpp:565
(gdb) r convert.ll -o - -mcpu=mips32r2
(gdb) p CurDAG->dump()
SelectionDAG has 69 nodes:
  0x1e47430: ch = EntryToken [ORD=2]
  ...
  0x1e70220: i32 = FrameIndex<-1> [ORD=1]
  ...
      0x1e70620: ch = store 0x1e47430, 0x1e70420, 0x1e70220, 0x1e70520<ST4[FixedStack-1]> [ORD=2]
  ...
      0x1e70820: i32 = add 0x1e70220, 0x1e70720 [ORD=2]
  ...
      0x1e70a20: ch = store 0x1e47430, 0x1e70920, 0x1e70820, 0x1e70520<ST4[FixedStack-1+4]> [ORD=2]
  ...
  0x1e70e20: f64,ch = load 0x1e70d20, 0x1e70220, 0x1e70520<LD8[%x2]> [ORD=2]

The two store nodes (0x1e70620 and 0x1e70a20) and the f64 load (0x1e70e20) all write to or read from FrameIndex<-1> (0x1e70220), but the MachinePointerInfo of the load refers to %x2. This turned out to be a problem when I tried to enable post-RA scheduling for Mips.

The two stores were created here in MipsISelLowering.cpp:2528.
     SDValue Store = DAG.getStore(Chain, dl, DAG.getRegister(Reg, MVT::i32),
                                  StorePtr, MachinePointerInfo(), false,
                                  false, 0);


This is the machine function dump after isel:

(gdb) b 705
(gdb) c
(gdb) p MF->dump()
# Machine code for function PointToHPoint:
Frame Objects:
  fi#-1: size=48, align=8, fixed, at location [SP+8]
  fi#0: size=32, align=8, at location [SP]
Function Live Ins: %A0 in %vreg0, %A2 in %vreg1, %A3 in %vreg2

BB#0: derived from LLVM BB %entry
	SW %vreg2, <fi#-1>, 4; mem:ST4[FixedStack-1+4] CPURegs:%vreg2
	SW %vreg1, <fi#-1>, 0; mem:ST4[FixedStack-1](align=8) CPURegs:%vreg1
	%vreg3<def> = COPY %vreg0; CPURegs:%vreg3,%vreg0
	%vreg4<def> = LDC1 <fi#-1>, 0; mem:LD8[%x2] AFGR64:%vreg4



This issue was discussed here:
http://lists.cs.uiuc.edu/pipermail/llvmdev/2012-March/048055.html