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Bug 1388 - ARM THUMB: cpy instruction mustn't be emitted by default
Summary: ARM THUMB: cpy instruction mustn't be emitted by default
Status: RESOLVED FIXED
Alias: None
Product: libraries
Classification: Unclassified
Component: Backend: ARM (show other bugs)
Version: trunk
Hardware: All All
: P normal
Assignee: Unassigned LLVM Bugs
URL:
Keywords:
Depends on: 1401
Blocks:
  Show dependency tree
 
Reported: 2007-05-05 09:49 PDT by Lauro Venancio
Modified: 2015-05-18 07:11 PDT (History)
5 users (show)

See Also:
Fixed By Commit(s):


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Description Lauro Venancio 2007-05-05 09:49:39 PDT
The cpy instruction is only defined in ARMv6.
Comment 1 Lauro Venancio 2007-05-07 17:13:43 PDT
A possible solution for this bug is to emit 'mov' instead of 'cpy'. The problem
is that the mov sets the flags and I'm afraid that it can break something in
rematerialization. 

Cheng?
Comment 2 Lauro Venancio 2007-05-08 16:36:08 PDT
If all mov are changed to cpy, the backend emits wrong code:

        cmp r5, r2
        mov r0, r5
        bgt .LBB1_6     @cond_true99
Comment 3 Evan Cheng 2007-05-08 17:24:23 PDT
The proper fix is to model CC as explicit register(s). Then you can fix the scheduler and register allocator, 
i.e. any machine instruction level module that insert move, load, store ops, to insert instructions at the 
right spot to avoid clobbering the CC registers. Not only is it useful for this bug, it also makes it easier to 
implement a pass that optimize away cmp / test, etc.

Perhaps it's ok to just add instruction properties that tells us whether a instruction sets / reads CC. It's 
hard to say.
Comment 4 Chris Lattner 2007-05-08 18:59:21 PDT
removing me from cc list.  I am aka unassignedbugs@nondot, so I'm getting two copies :)
Comment 5 Chris Lattner 2007-05-08 19:00:18 PDT
FWIW, I think that it is about time we start modelling CC's correctly.  This would require, at the minimum, 
adding a new physreg to represent the CC, then marking each instruction that sets it as clobbering it.
Comment 6 Al Grant 2010-07-08 07:56:29 PDT
It's better to model each flag individually e.g. N, Z, C, V, Q, the GE bits (collectively) etc.  That way you can correctly model instructions that set N and Z but leave C and V unaffected.  This allows you to move a MOV in between a CMP and a BCS, or between an ADDS and an ADC.
Comment 7 John Brawn 2015-05-18 07:11:33 PDT
This was fixed by r216138:

Author: Jonathan Roelofs <jonathan@codesourcery.com>
Date:   Wed Aug 20 23:38:50 2014 +0000

    Lower thumbv4t & thumbv5 lo->lo copies through a push-pop sequence
    
    On pre-v6 hardware, 'MOV lo, lo' gives undefined results, so such copies need to
    be avoided. This patch trades simplicity for implementation time at the expense
    of performance... As they say: correctness first, then performance.
    
    See http://lists.cs.uiuc.edu/pipermail/llvmdev/2014-August/075998.html for a few
    ideas on how to make this better.

AsmParser also doesn't permit MOV lo, lo (or CPY, as it used to be known), so you can't use it in embedded asm, but MC does permit it, so using clang to assemble a .s file with --target=thumbv4t-none-eabi gives no error but should. That's less of a problem though.