$ cat t.s .bss .globl _g0 .text mov rbx, qword ptr [_g0] mov rcx, qword ptr [_g0 + 8] $ llvm-mc t.s -triple x86_64-unknown-unknown -x86-asm-syntax=intel .text .bss .globl _g0 .text movq _g0, %rbx movq _g0, %rcx I'm pretty sure the second load should be at offset 8: movq %rcx, _g0+8
Fixed in r202774.