LLVM Bugzilla is read-only and represents the historical archive of all LLVM issues filled before November 26, 2021. Use github to submit LLVM bugs

Bug 22346 - Turn off DAGCombine at -O0
Summary: Turn off DAGCombine at -O0
Status: NEW
Alias: None
Product: libraries
Classification: Unclassified
Component: Common Code Generator Code (show other bugs)
Version: trunk
Hardware: PC Windows NT
: P normal
Assignee: Unassigned LLVM Bugs
URL:
Keywords:
Depends on:
Blocks:
 
Reported: 2015-01-27 05:08 PST by Paul Robinson
Modified: 2015-04-14 03:55 PDT (History)
7 users (show)

See Also:
Fixed By Commit(s):

Attachments
Add an attachment (proposed patch, testcase, etc.)

Note You need to log in before you can comment on or make changes to this bug.
Description Paul Robinson 2015-01-27 05:08:56 PST 
DAGCombine should not run at -O0 (see discussion on review D7181).
http://reviews.llvm.org/D7181

However, doing that at the moment causes 19 test failures, including
one crash and one fail-to-select.
Comment 1 Paul Robinson 2015-01-27 05:45:33 PST 
Here's the list of failing tests that I got:

Failing Tests (19):
    LLVM :: CodeGen/AArch64/aarch64_f16_be.ll
    LLVM :: CodeGen/AArch64/and-mask-removal.ll
    LLVM :: CodeGen/ARM/2010-05-18-LocalAllocCrash.ll
    LLVM :: CodeGen/ARM/Windows/alloca.ll
    LLVM :: CodeGen/ARM/alloc-no-stack-realign.ll
    LLVM :: CodeGen/ARM/big-endian-ret-f64.ll
    LLVM :: CodeGen/ARM/vst3.ll
    LLVM :: CodeGen/X86/atomic16.ll
    LLVM :: CodeGen/X86/atomic32.ll
    LLVM :: CodeGen/X86/atomic6432.ll
    LLVM :: CodeGen/X86/avx-load-store.ll
    LLVM :: CodeGen/X86/fast-isel-gep.ll
    LLVM :: CodeGen/X86/inline-asm-tied.ll
    LLVM :: CodeGen/X86/musttail.ll
    LLVM :: CodeGen/X86/win32_sret.ll
    LLVM :: CodeGen/X86/win64_eh.ll
    LLVM :: CodeGen/XCore/threads.ll
    LLVM :: DebugInfo/X86/op_deref.ll
    LLVM :: DebugInfo/X86/vla.ll

CodeGen/ARM/2010-05-18-LocalAllocCrash.ll crashes in llc:
/home/probinson/projects/upstream/writeable/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp:776: void llvm::InstrEmitter::EmitMachineNode(llvm::SDNode*, bool, bool, llvm::DenseMap<llvm::SDValue, unsigned int>&): Assertion `NumMIOperands >= II.getNumOperands() && NumMIOperands <= II.getNumOperands() + II.getNumImplicitDefs() + NumImpUses && "#operands for dag node doesn't match .td file!"' failed.


CodeGen/X86/avx-load-store.ll gets a selection failure:
LLVM ERROR: Cannot select: 0x44b4df0: v2f64 = vector_shuffle 0x44b5230, 0x44b74c0<0,3> [ORD=3] [ID=14]
  0x44b5230: v2f64 = scalar_to_vector 0x44b48a0 [ORD=3] [ID=13]
    0x44b48a0: f64,ch = load 0x44a12e0, 0x44b4bd0, 0x44b5120<LD8[%ptr]> [ORD=2] [ID=10]
      0x44b4bd0: i64,ch = CopyFromReg 0x44a12e0, 0x44b73b0 [ORD=2] [ID=7]
        0x44b73b0: i64 = Register %vreg2 [ID=1]
      0x44b5120: i64 = undef [ID=3]
  0x44b74c0: v2f64 = bitcast 0x44b63a0 [ORD=3] [ID=12]
    0x44b63a0: v4i32 = BUILD_VECTOR 0x44b6c20, 0x44b6c20, 0x44b6c20, 0x44b6c20 [ORD=3] [ID=9]
      0x44b6c20: i32 = Constant<0> [ID=6]
      0x44b6c20: i32 = Constant<0> [ID=6]
      0x44b6c20: i32 = Constant<0> [ID=6]
      0x44b6c20: i32 = Constant<0> [ID=6]
In function: mov01
Comment 2 Matt Arsenault 2015-01-27 11:36:35 PST 
I don't think this is an entirely reasonable goal. DAGCombiner performs various canonicalizations the targets rely on, and being able to disable it increases the complexity they will need to deal with. There isn't really a way to have separate phases with the current DAG, so these aren't cleanly separated from "real" optimizations.